UP 8604_1100 80_4x4prog Ref 8604 1100 80 4x4prog

UP-8604_1100-80_4x4progRef UP-8604_1100-80_4x4progRef

User Manual: UP-8604_1100-80_4x4progRef

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4x4 Capability
Processor and Storage
Programmer Reference

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"1l UNIVAC
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COMPUTER SYSTEMS

UP-8604 Rev, 1

8804 Rev.1

I

.

SPERRY UNIVAC 1100/80 Systems

_~~~X4 Capability Processor and Storage Programmer Reference

U"I)ATI LEVEL

PSS-1
PAGI

Page Status Summary
Issue: UP-8604 Rev. 1
Section

Pages

Update

Section

Covllf'/Dlsclaime.'
PSS;

1

Contents

1 thru 14

1

1 thru 11

2

1 thru 4

3

1 thru 21

4

1 thru 28

5

1 thru 78

6

1 thru 71

7

1 thru 35

8

, thru 13

Appendix A

1 thru 10

Appendix B

1 thru 14

Applndlx C

1 thru 21

Apptndix 0

1 thru 8

Appendix E

1 thru 77

Ind.,x

1 thru 18

UMt~

Comment

Sheiltt
TOUII: 420 pig"

and cover

I

Pages

Update

Section

Pages

Update

8804 ReY.1

I

SftERRY UNIVAC 1100/80 Systems

_~~~1(4 Capability Processor and Stor3ge Programmer Reference

UP'OAn: LEVEl.

Contents--1
'AGI

Contents

Paige Staltus Summary
Cc)ntents.

1. Introduction
1. 1. Cieneral

1.2. System Components and Configurations
1.2. 1. Central Processor Unit
1.2.2. Storage System
1.2.3. Input/Output Unit
1.2.4. System Console
1.2.5. System Transition Unit (STU)
1.2.6. Subsystem Availability Unit (SAU)
1.2.7. Svstem Maintenance Unit (SMU)
1.2.S. Auxiliary Storage and Peripheral Subsystems
1.2.9. Destandardized Subsystems
1.2.10. Minin\um Peripheral Complement

2. ProcE!ssing Unit
2. 1. Cieneral
2.2. Control Section
2.2. 1. Control Section Operation
2.2.2. Instruction Repertoire
2.2.3. Control Registers

1-1
1-1
1-1

1-2
1-7
1-7
1-8
1-9
1-10
1-10
1-10
1-11

1-1 1
2-1
2-1
2-1

2-1
2-1

2.2.4. Data Shift/Complement/Store Operation

2-2
2-2

2.3. Arithmetic Section

2-2

2.4. Maintenance Section

2-2

2.5. Input/Output Unit (IOU)

2-3

2.S. System Status Word

2-3

8eo~

Rev.1

~

SPERRY UNIVAC 1100/80 SY8Iem.

4x4 Capability Processor and Storage Programmer Reference

3. Storage S'ystem

Content.--2
,AGE

3-1

3. 1. General

3-1

3.2. Main Storage Unit

3-1

3.2. 1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
3.2.S.
3.2.7.

3-2
3-2

Write Data Error Detection
Panial Write Error Detection
EeC Write Check Disable
Write Control Parity Checking
Address Parity Checking
Refresh Fault
Fixed Address Assignments

3.3. Storage Interface Unit
3.3. 1. Functional Characteristics
3.3.2. Tag and Data Buffer
3.3.3. Main Store Interface Stack
3.3.4. Invalidate Interface
3.3.5.. Error Detection and Reponing
3.3.S. Storage Interleave
3.3.S.1. Addressing Modes
3.3.6.2. Partitioning of Storage Configurations
3.3.7. Storage Configurations

3.4. Control Storage
3.4. 1. Control Register Selection Designator
3.4.2. Control Register Address Assignments
3.4.2.1. Storage for MSR Value - 0143 .
3.4.2.2. User Index (X) Registers - 0001-0017
3.4.2.3. User Accumulator (A) Registers - 0014-0033
3.4.2.4. Uner Unassigned Registers - 0034-0037
3.4.2.5. Executive Bank Descriptor Table Pointer Register - 0040
3.4.2.6. Immediate Storage Check Interrupts - 0041-0042
3.4.2.7. Normal Interrupts - 0043-0044
3.4.2.8. User Bank Descriptor Table Pointer Register - 0045
3.4.2.9. Bank Descriptor Index Registers - 0046-0047
3.4.2.10. Quantum Timer - 0050
3.4.2. 11. Guard Mode - 005 1-0053
3.4.2.12. Immediate Storage Check Status - 0054
3.4.2.13. Norma. Status - 0055
3.4.2.14. IOU Error Interrupts - 0056-0057
3.4.2.15. Unassigned Registers - 0060-0067
3.4.2. 16. Jump History Stack - 0070-0077
3.4.2. 17 . Real-Time Clock Register (RO) - 0100
3.4.2. 18. User (R 1) Repeat Count Register - 0101
3.4.2. 19. User (R2)1Mask Register - 0102
3.4.2.20. User (R2-R5)/Staging Registers (SR 1-SR3) - 0103-0105
3.4.2.21. User (R8-R9)/J-Registers (JO-J3) - 0106-0111
3.4.2.22. User R-Registers (R 1O-R 15) - 0112-0117
3.4.2.23. Executive (RO) R-Register - 0120
3.4.2.24. Executive (R 1) Repeat Count Register - 0121
- 3.4.2.25. Executive (R2)1Mask Register - 0122
3.4.2.26. Executive (R3-R5)/Staging Registers (SR 1-SR3) - 0123-0125
3.4.2.27. Executive (R6-R9)/J-Registers (JO-J3) - 0126-0131
3.4.2.28. Executive R-Registers (R 1O-R 15) - 0132-0137

3-3
3-3

3-3
3-3
3-4
3-5
3-6

3-7
3-8
3-8

3-8
3-9
3-10
3-14
3-15
3-15
3-15
3-16
3-16
3-17
3-18

3-18
3-18
3-18

3-18
3-18
3-18
3-18
3-18
3-19

3-19
3-19
3-19
3-19
3-19
3-19
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-21

8804 Rev.l

I

SPERRY UNIVAC 1100/80 Systems

~_ _~ 4)1~4 Capability Processor and Storage Programmer Reference

UPOATI LML

3.4.2.2!~. Executive Index Regist9rs (X1-X15) - 0141-0157
3.4.2.30. Executive Accumulator Registers (AO-A 15) - 0154-0173
3.4.2.31. Executive Unassigned Registers - 0140, 0174-0177
3.4.2.32. Control Register Protection

4. CPU Arithmetic and Control

Contents-,3
PAGI

3-21
3-21
3-21
3-21
4-1

4.1. General

4-1

4.2. Arithmetic Section
4.2. 1. General Operation
4.2.1.1. Data Word
4.2. 1.2. Data Word Complement
4.2. 1.3. Absolute Values
4.2.2. Microprogrammed Control
4.2.3. Main Adder Characteristics
4.2.4. Fixed-Point Single- or Double-Precision Add or Subtract Overflow and

4-1
4-1
4-1
4-2
4-2
4-2
4-2
4-3

Carry

4.2.4.1. Overflow
4.2.4.2. Carry
4.2.4.3. Arithmetic Interrupt
4.2.5. Fixed-Point Division
4.2.6. Fixed-Point Multiplication
4.2.7. Floating-Point Arithmetic
4.2.8. Floating-Point Numbers and Word Formats
4.2.8.1. Single-PreciSion Floating-Point Numbers
4.2.8.2. Double-Precision Floating-Point Numbers
4.2.8.3. Negative Floating-Point Numbers
4.2.8.4. Residue
4.2.9. Normalized/Unnormalized Floating-Point Numbers
4.2.10. Floating-Point Characteristic Overflow/Underflow
4.2. 10. 'I. Floating-Point Characteristic Overflow
4.2.10.2. Floating-Point Characteristic Underflow
4.2.10.:3. Floating-Point Divide Fault
4.2. 11. Fixed-Point to Floating-Point Conversion
4.2. 12. Floating-Point Addition
4.2. 13. Double-Precision Floating-Point Addition
4.2. 14. Floating-Point Subtraction (Add Negative)
4.2. 15. Floating-Point Multiplication
4.2. 16. Floating-Point Division
4.2. 17. Floating-Point Zero
4.2. 18. Byte Instruc~ions

4-3
4-3
4-4
4-4
4-4

4.3. Clontrol Section
4.3. 1. Instruction Word Format
4.3.2. Instruction Word Fields
4.3.2.1. Use of the f-Field
4.3.2.2. Description of the j-Fiefd

4-1 1
4-1 1
4-12
4-12
4-12
4-12
4-15
4-20
4-20
4-20
4-20
4-21

4.3.2.2.1. Use of the j-Field as an Operand Qualifier
4.3.2.2.2. Use of the j-Field to Specify Character Addressing
4.3.2.2.3. Use of j-Field as Partial Control Register Address
4.3.2.2.4. Use of j-Field as Minor Function Code
4.3.2.3. Uses of the a-Field
4.3.2.3. 1. Use of the a-Field to Reference an A-Register
4.3.2.3.2. Use of the a-Field to Reference an X-Register

4...4

4-5
4-7
4-7
4-7
4-8
4-8
4-8
4-8
4-9
4-9
4-9
4-10
4-10
4-10
4-1 0
4-10
4-1 1
4-1 1

1104 Rev. l'
tJII-MIIII8I

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

4.3.2.3.3. Use of the a-Field to Reference an R-Register .
4.3.2.3.4. Use of the a-Field to Reference a Jump Key
4.3.2.3.5. Use of the a-Field to Reference Halt Keys
4.3.2.3.6. Use of the a-Field as Minor Function Code
4.3.2.4. Use of the j- and a-Fields to Specify GRS Control Register Address
4.3.2.5. Use of the x-Field
4.3.2.6. Use of the h-Field
4.3.2.7. Use of the i-Field
4.3.2.8. Description of the u-Field
4.3.2.8. 1. Use of the u",:,Field as an Operand Address Designator
4.3.2.8.2. Use of the u-Field as an Operand Designator
4.3.2.8.3. Use of the u-Field as a Shift Count Designator
4.3.2.S.4. Restrictions on the Use of the u-Field

5,. Instruction Repertoire

4.:..21
4-21
4-21
4-21
4-22
4-22
4-23

4-23
4-24
4-25
4-25
4-25
4-26

5-1

5. 1.. General

i::-1

5.2. Load Instructions
5.2.1. Load A loLA

5-2
5-2
5-2
5-2
5-2
5-3

10
5.2.2. Load Negative A LN,LNA
11
5.2.3. Load Magnitude A LM,LMA
12
LNMA
13
5.2.4. Load Negative Magnitude A 5.2.5. Load R L,LA
23
5.2.6. Load X Modifier LXM
26
5.2.7. Load X loLX 27
5.2.S. Load X Increment LXI 46
5.2.9. Double Load A DL
71, 13
5.2.10. Double Load Negative A DLN
71, 14
5.2. 11. Double Load Magnitude A DLM
71, 15

5-3

5-3
5-3
5-3
5-3
5-4

5.3. Store Instructions

5-4

5.3. 1.
5.3.2.
5.3.3.
5.3.4.
5.3.5.
5.3.S.
5.3.7.
5.3.S.

5-4
5-4
5-5
5-5
5-5
5-5

Store A S,SA
01
Store Negative A SN,SNA
02
Store Magnitude A SM,SMA
03
Store R S,SR
04
Store Constant Instructions XX
05; a - 00-07
Store X S,SX
06
Double Store A OS
71, 12
Block Transfer BT
22

5.4. Fixed-Point Arithmetic Instructions
5.4.1. Add to A A,AA
14
AN,ANA
15
5.4.2. Add Negative to A AM,AMA
16
5.4.3. Add Magnitude to A 5.4.4. Add Negative Magnitude to A ANM,ANMA
5.4.5. Add Upper AU
20
5.4.S. Add Negative Upper ANU
21
5.4.7. Add to X A,AX
24
5.4.S. Add Negative to X AN,ANX
2.5
5.4.9. Multiply Integer MI
30
5.4.10. Multiply Single Integer MS.
31
5.4. 11. Multiply Fractional MF
32
5.4. 12. Divide Integer 01
34
5.4. 13. Divide Singl. Fractional D5F
35

17

5-4

5-6

5-6
5-7
5-7
5-7 . .
5-7
5-8
5-8
5-8

5-8
5-8
5-8
5-9
5-9

5-3

8804 Rev.1
~MHR

I

SPERRY UNIVAC 1100/80 Systems

~'X4 Capability Processor and Storage Programmer Reference

5.4.14,.
5.4. 15.
5.4. 16.
5.4.17.
5.4.18.
5.4.19.
5.4.20.

Divide Fractional DF
36
Double-Precision Fixed-Point Add DA
71, 10
Double-Precision Fixed-Point ,Add Negative DAN
Add Halves AH
72,04
Add Negative Halves ANH
72,05
Add Thirds AT
72,06
Add Negative Thirds ANT
72,07

uJIOAn LEVU

71, 1 1

Content~6
PAGE

5-10
5-10
5-10
5-10
5-10
5-11
5-11

5.5. Floating-Point Arithmetic Instructions
5.5.1. Floating Add FA
76,00
5.5.2. Floating Add Negative FAN
76,01
5.5.3. Double-Precision Floating Add DFA
76,10
5.5.4. Double-Precision Floating Add Negative DFAN
76,11
5.5.5. Floating Multiply FM
76,02
5.5.8. Double-Precision Floating Multiply DFM
78,12
5.5.7. Floating Divide FD
76,03
5.5.S. Double-Precision Floating Divide DFD
76,13
5.5.9. Load and Unpack Floating LUF
76,04
5.5.1(). Double Load and Unpack Floating DFU
76,14
5.5.1 'I. Load and Convert tQ Floating LCF
76,05
5.5. 1;t Double Load and Convert to Floating..;. DFP, DLCF 76,15
5.5.1:3. Floating Expand and Load FEL
76,16
5.5. 14. Floating Compress and Load FCL
76,17
5.5.1 !5. Magnitude of Characteristic Difference to Upper MCL1U
76,Oe
5.5.16. Characteristic Difference to Upper COU
76,07

5-11
5-11
5-12
5-12
5-13
5-13
5-14
5-15
5-15
5-16
5-16
5-17
5-17
5-18
5-18
5-19
5-19

5.S. $earch and Masked-Search Instructions
5.6.1., Search Equal SE
62
5.6.2.. Search Not Equal SNE
63
5.6.3" Search Less Than or Equal/Search Not Greater SLE,SNG
64
5.6.4. Search Greater SG
65·
5.6.5. Searcn Within Range SW
66
5.6.6, Search Not Within Range SNW
67
5.6.7. Masked Search Equal MSE
71,00
5.6.S. Masked Search Not Equal MSNE
71,01
5.6.9. Masked Search Less Than or Equal/Not Greater - MSLE,MSNG 71,02
5.6.10. Masked Search Greater MSG
71,03
5.6.11. Masked Search Within Range MSW
71,04
5.6.12. Masked Search Not Within Range MSNW
71,05
5.6. 13. Masked Alphanumeric Search Less Than or Equal MASL
71,06
5.6.14. Masked Alphanumeric Search Greater MASG
71,07

5-20
5-21
5-22
5-22
5-23
5-23
5-24
5-24
5-25
5-25
5-25
5-26
5-26
5-27
5-28

5.7. Test (or Skip) Instructions
5.7.1. Test Even Parity TEP
44
5.7.2. Test Odd Parity TOP
45
5.7.3. Test Less Than or EqualITest Not Greater Than Modifier - TLEM,TNGM 47
5.7.4. Test Zero TZ
50
5.7.5. Test Nonzero TNZ
61
5.7.S. ' Test Equal TE
52
6.7.7. Test Not Equal - . TNE
53
5.7.EI. Test Les, Than or EqualITest No't Greater - TLE,TNG 54
5.7.9. Test Greater TG
55
5.7.10. Test Within Range TW
56
5.7.11. Test Not Within Range TNW
57
5.7. '12. Test Positive TP
80

5-28
5-28
5-29
5-29
5-29
5-30
5-30
5-30
5-30
5-31
5-31
5-31
5-32

8104 Rev.1
Ufl-MII • •

SPERRY UNIVAC 1100/80 Syttems

4x4 Capability Processor and Storage Programmer Reference

5.7.13. Test Negative TN
61
5.7. 14. Double-Precision Test Equal -

DTE

71, 17

Contents-6
UPOATI LIVIl.

PAGI

5-32
5-32

5.S. Shift Instructions
5.8. 1. Single Shift Circular SSC
73,00
5.8.2. Double Shift Circular DSC
73,01
5.S.3. Single Shift Logical SSL
73,02
5.S.4. Double Shift Logical DSL
73,03
5.S.5. Single Shift Algebraic SSA
73.04
5.8.6. Double Shift Algebraic DSA
73,05
5.8.7. Load Shift and Count LSC
73.08
5.S.8. Double Load Shift and Count DLSC
73,07
5.S.9. Left Single Shift Circular LSSC
73,10
5.S. 1O. Left Double Shift Circular LOSC
73, 11
5.S.11. Left Single Shift Logical LSSL
73, 12
5.S.12. Left D9uble Shift Logic~1 LOSL
73. 13

5-32
5-34
5-34
5-34
5-35
5-35
5-35
5-35
5-36
5-36
5-36
5-36
5-37

5.9. Unconditional Jump Instructions
72,01
5.9. 1. Store Location and Jump SW
5.9.2. Load Modifier and Jump _. LMJ
74,13
AAIJ
74,07
5.9.3. Allow All Interrupts and Jump -

5-37
5-37
5-37
5-38

5.10. Bank Descriptor Selection Instructions
5. 10. 1. Load Bank and Jump LBJ
07,17
5.10.2. Load I-Bank Base and Jump LIJ
07, 13
5.10.3. Load D-Bank Base and Jump LOJ
07, 12

5-38
5-38
5-39
5-39

5. 11. Conditional Jump Instructions
5.11. 1. Jump Greater and Decrement JGD
70
5. 11.2. Double-Precision Jump Zero DJZ
71.16
5. 11.3. Jump Positive and Shift JPS
72,02
5.11.4. Jump Negative and Shift JNS
72,03
5. 11.5. Jump Zero JZ
74,00
5.11.S. Jump Nonzero JNZ
74,01
5.11.7. Jump Positive JP
74,02
5. 11.8. Jump Negative IN
74.03
5.11.9. Jump/Jump Keys J,JK
7~,04
5. 11. 10. Halt Jump/Halt Keys and Jump HJ,HKJ
74,05
5.11.11. Jump No Low Bit JNB
74,10
5.11.12. Jump Low Bit JB
74.11
5. 11. 13. Jump Modifier Greater and Increment JMGI
74, 12
5.11.14. Jump Overflow JO
74,14; a - 0
5.11.15. Jump Floating Underflow JFU
74,14; a - 1
5. 11 ~ 18. Jump Floating Overflow JFO
74, 14; a - 2
5.11.17. Jump Divide Fault JDF
74.14; a - 3
5. 11. 18. Jump No Overflow JNO
74, 15; a - 0
5.11. 19. Jump No Floating Underflow JNFU
74,15; a - 1
JNFO
74. 15; a - 2
5. 11.20. Jump No Floating Overflow 5.11.21. Jump No Divide Fault JNDF
74,15; a - 3
5. 11.22. Jump Carry JC
74,1 a
5. 11.23. Jum" No Carry JNC
74, 17

5-39
5-40
5-40
5-40
5-40
5-40
5-41
5-41
5-41
5-41
5-41
5-42
5-42
5-42
5-42
5-43
5-43
5-43
5-43
5-43
5-43
5-44
5-44
5-44

5. 12. Logical Instructions
5. 12. 1. Logical OR OR
40
5. 12.2. Logical Exclusive OR XOR

5-44
5-45
5-45

41

8804 Aev.1

I

SI:IIERRY UNIVAC 1100/80 Systems

Contents--7

_~~~K4 Capability Processor and Storage Programmer Reference

5.12.3., Logical AND AND
5. 12.4., Masked Load Upper -

42
MLU

UPDATE LIVIL

!tAOI

5-46
5-46

43

5. 13. Miscellaneous Instructions
5. 13. 1. Load OR Designators LPo
07, 14
5.13.2. Store DR Designators SPO
07,15
5.13.3., Execute EX
72,10
5.13.4. Executive Request ER
72,11
5.13.5. Test and Set TS
73,17; a =- 0
5.13.6. Test and Set and Skip TSS
73,17; a=-1
5.13.7., Test and Clear and Skip TCS
73,17; a - 2
TSA
73,17; a - 4
5.13.8. Test and Set Alternate TSSA
73,17; a
5.13.9. Test and Set and Skip Alternate 5. 13. 1~J. No Operation NOP
74,06
5.13.11. Store Register Set SRS
72,16
5.13.1 :2. Load Register Set LRS
72,17
5.13.13. Test Relative Address TRA
72.15
5. 13. 14. Increase Instructions XX
05; a
10-17

5-46
5-46
5-47
5-47
5-47

5-48
5-48

=-

=

5. 14. Byte Instructions

5

5-48
5-48
n-48

5-49
5-49

5-49
5-49
5-51

5-51

5. 14. 1. Byte Move BM
33,00
5. 14.2., Byte Move With Translate BMT
33,01
5. 14.3. Byte Translate and Compare BTC
33,03
5. 14.4. Byte Compare BC
33,04
5. 14.5. Edit EDIT
33,07
5. 14.5. 1. Function Byte
5.14.5.2. Subfunction Byte
5. 14.6. Byte to Binary Single Integer Convert BI
33,10
5. 14.7. Byte to Binary Double Integer Convert Bol
33, 11
5.14.8. Binary Single Integer to Byte Convert IB
33,12
5.14.9. Binary Double Integer to Byte Convert DIB
33,13
5. 14. 1O. Byte to Single Floating Convert BF
33, 14
5.14.11. Byte to Double Floating Convert -' BDF
33,15
5.14.1 :2. Single Floating to Byte Convert FB
33,16
5. 14. 13. Double Floating to Byte Convert DFB
33, 17
5.14.14. Byte Add BA
37,06
5.14.15. Byte Add Negative BAN
37,07

5.15. Executive Instructions
5.15.1. Prevent All Interrupts and Jump -

PAIJ

72.13

5.15.2. Load Dayclock - LOC
73,14,10
5.15.3. Enable/Disable Oayclock EOC,OOC
73,14, 11-12
5.15.4. Select Daycfock SOC
73,14, 13
5.15.5. Select Interrupt Locations SIL
73,15, 00
5.15.6. Load Breakpoint Register LBRX
73,15, 02
5.15.7,. Store Processor 10 SPfD
73,15, 05
5. 15.8.. Load Quantum Timer LQT
73, 15, 03
5. 15.9.. Load Base LB
73, 1 10
5.15.10. Load Limits LL 73,15, 1 '1
5.15.11. Load Addressing Environment··
LAE
73,15, 12
5 . 15.12. Store Quantum Time SQT
73,15, 13
LD
73,15, 14
5.15.13. Load Designator Register SO
73,15, 15
5.15.14. Store Designator Register UR
73,15, 16
5.15.15. User Return RAT
73,15, 08
5.15.16. Reset Auto-Recovery Timer -

s:

5-54
5-56
5-57

5-58
5-58

5-59
5-60
5-64
5-64
5-64

5-65
5-65
5-67

5-67
5-68
5-68
5-69
5-69
5-69

5-70
5-70
5-70
5-70

5-73
5-74
5-74
5-74
5-74
5-74

5-75
5-75
5-75
5-75

5-76

8104 Rev.1

SPERRY UNIVAC 1100/80 Systems

4x4 Capability ProCAssor and Storage Programmer Reference

5.15.17.
5. 15. 18.
5.15.19.
5.15.20.
5. 15.21.
5. 15.22.

Toggle Auto-Recovery Path TAP
73,15, 07
-Store System Status SSS
73,15, 17
Initiate Interprocessor Interrupt III X
73,15, 04
Diagnostics 73,14, 14 - 17
Initiate Maintenance Interrupt IMI
72,00
Input/Output Instructions

5. 16. Invalid Function Codes

«3. Input/Output

5-76
5-76
5-76
5-76
5-77
5-77
5-77

6-1

6. 1. General

6-1

6.2. Functional Characteristics
6.2. 1. Channels
6.2.2. Subchannels

6-1
6-3
6-5

6.3. Control of Input/Output Devices
6.3. 1. Input/Output Device Addressing
6.3.2. States of the Input/Output System
6.3.3. Condition Codes
6.3.4. Instruction Format and Channel Address Word
6.3.5. Instruction Operation

6-5
6-5

6.4. I/O Instructions
6.4.1. Operation Code - 75,00
6.4.2. Start I/O Fast Release - SIOF 75,01
6.4.2.1. Byte or Block Multiplexer Channel Operation
6.4.2.2. Word Channel Operation
6.4.3. Operation Code ~ 75,02
.6.4.4. Test Subchannel - TSC 75,03
6.4.4. 1. Byte or Block Multiplexer Channel
6.4.4.2. Word Channel Operation
6.4.5. Halt Device - HDV 75,04
6.4.5. 1. Byte or Block .Multiplexer Channel Operation
6.4.5.2. Word Channel Operation
6.4.6. Halt Channel - HCH 75,05
6.4.6. 1. Byte or Block Multiplexer Channel Operation
6.4.6.2. Word Channel Operation
6.4.7. Load Channel Register - LCR 75,10
6.4.7. 1. Byte and Block Multiplexer Channel
6.4.7.2. Word Channel Operation
6.4.8. Load Tabl. Control Words - LTCW 75,11
6.4.8. 1. Byte and Block Multiplexer Channel
6.4.8.2. Word Channel Operation

. 6-6

6-9
6-14

6-15
6-16

6-16
6-17
6-17
6-18
6-18

-6-19
6-19
6-19
6-20
6-20
6-21
6-21

6-21
6-22
6-22

6-22
6-23
6-23

6-23
6-24

6.5. execution of I/O Operations
6.5. 1. Channel Command Word
6.5.2. CCW Completion

6-25
6-25

6.6. Command Code
6.6. 1. Transfer in Channe' Command - TIC
8.6.2. Store Subchannel Status Command - SST

6-35
6-36
6-37

6-28

8804 Rev.'
Uf'-HUMIH

I

f;PERRY UNIVAC' 100/80 Systems

~'x4 Capability Processor and Storage Programmer Reference

6.7. Data Transfer
6.7.1.
6.7.2.
6.7.3.
6.7.4.

Format Flags (E, A, B, and C)
Skip Data - SK
Data Address Decrement - DAD
Data Address Lock - DAL

Contents-9
UPOATI LIYIL

PAGI

6-37
6-37

6-38
6-38
6-38

6.S. Chaining Operations

6-38

6.S.1.
6.S.2.
8.S.3.
6.S.4.
6.S.S.

6-39

6.9.

Data Chaining
Command Chaining
EI Chaining (ESI Word Interface Only)
Truncated Search
Truncated Search Restrictions
~nterrupt

Generation Flags

6-39
6-40
6-41
6-42

6.9. 1. Progra.m Controlled Interrupt - PCI
6.9.2. Monitor - MON (Word Channel Only)

6-44
6-44
6-44

6.10. Status

6-45

6.11. Instruction Status

6-50

6. 12. Status Table

6-51

6. 13. Store Subchannel Status - SST

6-53

6. 14. Subchannel Status

6-53

6. 14. 1. SIOF Device Check (Byte or Block Multiplexer Channels Only)
8. 14.2. SIOF-EI Collision (Word Channel Only)
8. 14.3. Interface Control Check
6. 14.4. Channel Control Check
6. 14.5. Channel Data Check
6.14.EI. A Format Stop Code (Block Multiplexer Channel Only)
6. 14.7. Program Check
6. 14.2. Monitor (Word Channel Only)
6.14.9. Incorrect Length (Byte or Block Multiplexer Channels Only)
6. 14. 10. Program Controlled Interrupt

6-53
6-53
6-53
6-54
6-54
6-54
6-54

6-55
6-55
6-56

6.15. Device Status

6-56

6. 16. Data Chaining Precautions

6-57

6. 17. Subchannel expansion Feature and Channel Base Register

6-64

6. 1S. Interrupt Mask Register

6-64

6. 19. Initial load

6-66

6.20. Back-to-Back Operation (Word Channel Only)

6-66

6.2 1. Priorities

6-67

6.22. Basic Programming Procedure

6-67

8804 Rev.1

SPERRY UNIVAC 1100/80 Systema

4x4 Capability Processor and Storage Programmer Reference

6.23. Programming Examples

7. Interrupts

Contenta-10
,AGI

6-68

7-1

7. 1. General

7-1

7.2. Interrupt Sequence

7-3
7-3

7.2.1. Program Status
7.2.2. Addressing Status
7.2.3. Interrupt Status

7.3. Interrupt Types
7.3. 1. Program Exception Interrupts
7.3.2. Arithmetic Exception Interrupts
7.3.3. Program-lnitiated Interrupts
7.3.4. Interprocessor Interrupt
7.3.5. Clock Interrupts
7.3.S. Storage Check Interrupts
7.3.6. 1. Immediate Storage Checks
7.3.6.2. Delayed Storage Check Interrupts
7.3.6.2. 1. Internal SIU Check
7.3.6.2.2. SIU/MSU Interface Check
7.3.6.2.3. SIU/MSU Read or Partial Write ECC Check
7 .3~ 7. Power Check Interrupt
7.3.8. Byte Status Code
7.3.9. Multiprocessor Interrupt Synchronization

7.4. Input/Output Interrupts
7.4. 1. Machine Check Interrupts
7.4.2. Normal InterruptS
7.4.3. TAbled Interrupts

7.5. Interrupt Errors
7.5.1. Processor Interrupt Errors
7.5.2. Input/Output Interrupt Errors
7.5.2. 1. Cause of Even/Odd I/O Interrupt Errors
7.5.2.2. Operation of Even/Odd I/O Interrupts
7.5.2.3. Software Action on Even/Odd I/O Interrupts
7.5.2.4. Logging

U. Executive Control

7-4

7-5
7-5
7-5
7-6

7-8
7-9

7-10
7-10
7-11
7-12
7-13
7-14
7-16

7-17
7-18
7-18
7-19
7-19
7-21
7-29
7-32
7-32
7-33
7-33
7-33
7-33
7-35

8-1

8. 1. General

8-1

8.2. Processor State

8-1
8-1
8-7

8.2. 1. Designator Register
8.2.2. Dayciock

8.3. Introduction to Addressing
8.3. 1.
8.3.2.
8.3.3.
8.3.4.
8.3.5.
8.3. S.

Main Storage Organization
Program ~egmentation
General Theory of 1100/80 Addressing
Bank Descriptor
Umits
Control Information

8-8
8-8
8-8
8-8
8-9
8-9
8-9

8804 ADv.1

.

I

SP'ERAY UNIVAC 1100/80 Systems

~_~,4 Capability Processor and Storage Programmer Reference

8.3.7. Bank Descriptor Registers
8.3.8. Address Generation
S.3.9. P-Capturing Instructions

Contents-1 1
IIAGE

8-9

8-10
8-13

Appendbc: A. Abbreviations, Definitions, and Symbols

A-l

Appendbc: B. Summary of Word Formats

B-1

Appendix C. Instruction Repertoire

C-1

Appendix D. Code Conversions .

0-1

D. 1. ASCII and Fieldata Code Conversion Tables

0-1

0.2. Special Characters in ASCII

0-6

Appendix E. Storage Configurations
E.1. General

E-l

E.2. Dt3finition of Terms

E-1

E.3. Address Interleave
E.l. 1. )~ddress Interleaving in Segment/Cabinet Storage Configur~ltions
E.l. 1. 1. One Segment/One Bank
E.3.1.2. One SegmentITwo Banks
E.l.l.3. Two SegmentslTwo Banks
E.l.l.4. Two SegmentslThree Banks - Basic
E.l.l.S. Two Segments/Three Banks - Alternate
E.l.l.6. Two Segments/Four Banks
E.l. 1.7. Trrae Segments/Six Banks
E.3.1.8. Four Segments/Eight Banks
E.3. 1.8. 1. Partitioned by Storage Halves
E.3.1.8.:2. Partitioned Across Storage Halves
E.3.1.9. Eight Segments/Eight Banks
E.l.2. Address Interleaving in Segment/Bank Storage Configurations
E.J.2.1. Four Segments/Four Banks
E.3.2.2. Degraded Mode - Failed Segment
E.3.2.3. Degraded Mode - Failed Bank

E-2
E-3
E-J

E.4. S.!tgmentiCabinet Storage Configurations

E-18
E-18
E-18
E-19
E-20
E-20
E-21
E-22
E-23
E-24
E-25
E-26
E-26
E-27
E-28

E.4.1. (Jne-Segment Configurations
E.4.1.1. One Segment/One Bank
E.4.1.2. One SegmentlTwo Banks
E.4.2. Two-Segment Configurations
E.4.2.1. Two-Segments/Two Banks - Basic
E.4.2.2. Two Segments/Two Banks - Alternate
E.4.2.3. Two Segments/Three Banks - Basic
E.4.2.4. Two Segments/Three Banks - Alternate
E.4.2.S. Two Segments/Four Banks - Basic
E.4.2.6. Two Segments/Four Banks - Alternate
E.4.3. 'rhree-Segment Configurations
E.4.l.1. Three SegmentslThree Banks
E.4.J.2. Three Segments/Four Banks
E.4.l.3. Three Segments/Five Banks

E-4
E-S
E-6
E-7
E-8
E-9
E-10
E-l1
E-12
E-13
E-15
E-15
E-16
E-17

8804 Rev.1

SPERRY UNIVAC 1100/80 Syttema

~

4x4 Capability Processor and Storage Programmer Reference

E.4.3.4. Three Segments/Six Banks
E.4.3.4.1 .. Partitioned by SIU halves
E.4.3.4.2. Partitioned Across SIU Halves
E.4.4. Four-Segment Configurations
E.4.4.1. Four SegmentslTwo Banks - Dual Cluster
E.4.4.2. Four Segments/Three Banks - Dual Cluster
E.4.4.3. Four Segments/Four Banks
E.4.4.4. Four Segments/Four Ban,ks - Dual Cluster
E.4.4.5. Four Segments/Six Banks
E.4.4.6. Four Segments/Eight Banks
E.4.5. Six-Segment Configurations
E.4.S.1. Six SegmentslThree Banks - Dual Cluster
E.4.S.1.1. Partitioned by Cluster and SIU Halves
E.4.5.1.2. Partitioned by Cluster Across SIU Halves
E.4.5.1.3. Partitioned Within Cluster and SIU Halves
E.4.5.2. Six Segments/Four Banks - Dual Cluster
E.4.5.3. Six Segments/Five Banks - Dual Cluster
E.4.5.3.1. Partitioned by Cluster
E.4.5.3.2. Partitioned by Cluster by SIU Halves
E.4.5.3.3. Partitioned by Cluster Across SIU Halves
E.4.5.4. Six Segments/Six Banks - Dual Cluster
E.4.6. Eight-Segment Configurations
E.4.6.1. Eight Segments/Four Banks - Dual Cluster
E.4.6.1.1. Par~itioned by Cluster and SIU Halves
E.4.6.1.2. Par:itioned by Cluster Across SIU Halves
E.4.6.1.3. Partitioned Within Cluster by SIU Halves
E.4.6.1.4. P~rtitioned Within Cluster Across SIU Halves
E.4.6.1.5. Minimal Storage Partitioned Out
E.4.6.2. Eight Segments/Six Banks - Dual Cluster
E.4.6.2.1. Partitioned by Cluster
E.4.6.2.2. ~artitioning One MSU Out
E.4.6.3. Eight Segments/Eight Banks - Dual Cluster
E.4.6.3.1. Partitioned by Cluster Across SIU Halves
E.4.6.3.2. Partitioned by Cluster by SIU Halves

E.5. Segment/Bank Storage C&nfigurations
E.S. 1. One Segment/One Bank
E.5.2. Two SegmentslTwo Banks
E.S.2.1. Degraded Mode - Failed Segment
E.5.2.2. Degraded Mode - Failed Bank
E.5.3. Three SegmentslThree Banks
E.5.3.1. Degraded Mode - Failed Lower Segment
E.5.3.2. Degraded Mode - Failed Upper Segment
E.S.3.3. Degraded Mode - Failed Lower Bank
E.S.3.4. Degraded Mode - Failed Upper Bank
E.5.4. Four Segments/Four Banks
E.5.4.1. Degraded Mode - Failed Segment
E.5.4.2. Degraded Mode - Failed Bank
E.5.4.3. Partitioned by SIU Halves
E.5.4.4. Partitioned Across SIU Halves

Contenta-' 2
U..oATi L.IVIL

"AGE

E-29
E-30
E-31
E-32
E-32
E-34
E-35
E-36
E-38
E-39
E-40
E-40
E-41
E-42
E-43
E-44
E-46
E-47
E-48
E-49
E-50
E-52
E-52
E-53
E-54
E-55
E-56
E-57
E-58
E-59
E-60
E-61
E-62
E-63
E-64
E-64
E-65
E-66
. E-67
E-68
E-69
E-70
E-71
E-72
E-73
E-74
E-75
E-76
E-77

I

8604 Rev.1

SPERRY UNIVAC 1100/80 Systems

~~--L4x4 Capability Processor and Storage Programmer Reference

Contenlts-1 3
UItOATE lIV£L

'AGE

Index
User Comment Sheet
Fiigures
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Filgure
Fiigure
Fiigure
Fiigure
Fiigure
Fiigure
Fiigure
Fiigure
Fugure
Fiigure
Fiigure
Fiigure

1-1.
1-2.
1-3.
2-1.
3-1.
3-2.
3-3.
4-1.
4-2.
4-3:
4-4.
5-1.
5-2..
6-1.
6-2.
6-3,.
6-4.
7-1.
7-2..
7-3.
7-4.
7-5"
7-6.
7-7.
7-8.
7-9.
8-2.
8-3.

SPERRY UNIVAC 1100/82 2x2 System Segment/Cabinet Configuration
SPERRY UNIVAC 1100/82 2x2 System Segment/Bank Configuration
SPERRY UNIVAC 1100/84 4x4 System Segment/Cat1inet Configuration
System Status Word Format
First Level Storage Interleave
Second Level Storage Interleave
Configurations for Addressing Modes
Data Transfers from Storage
Data Transfers to Storage
J-Register Format for Character Addressing Mode
Byte Selected for Valid Combinations of BL and Ob Field Values
J-Register Format
Select Interrupt Locations
1100/80 Input/Output Unit
Byte or Block Multiplexer Channel and Word Channel Configuration
Block Multiplexer Channel Example CCW List
Word Channel 151 Interface Example CCW List
Format of Guard Mode Interrupt Status
Format of Addressing Exception Interrupt Status
Format of Breakpoint Interrupt Status
Format of Interprocessor Interrupt Status
Format of Immediate Storage Check Interrupt Status
Internal SIU Check Format
SIU/MSU Interface Check Format
SIU/MSU Read or Partial Write ECC Check Format
Power Check Interrupt Status Word
Bank Descriptor and BOT Pointer Formats
Base Value Selection

1-3
1-4
1-5
2-4
3-9
3-10
3-12
4-13
4-14
4-16
4-17
5-52
5-71
6-2
6-4
6-69
6-71
7-7
7-8
7-9
7-10
7-12
7-13.
7-14
7-16
7-18
8-10
8-12

Minimum/Maximum Functional Configurations
Fixed Address Assignments 0200-0237
Fixed Address Assignments 0240-0277
System Addressing Modes
MSU Address Generation
SIU/MSU Address Bit Manipulation
GRS Register Assignments 0 Through 63
GRS Register Assignments 64 Through 127
Instructions Thot Condition the Carry and Overflow Designators
Sign Bit Combinations Which Set Carry Designator
Single-Precision Floating-Point Characteristic Values and Exponent Values
Double-Precision Floating-Point Characteristic Values and Exponent Values
Explanation of J-Register Fields for Character Addressing Mode
Output Ob Values Produced When BL == 0
Output Ob Values Produced When BL == 1
Output Ob Values Produced When BL == 2
Output Ob Values Produced When BL =- 3

1-6
3-4
3-5
3-1 1
3-13
3-14
3-16
3-17
4-3
4-4
4-6
4-6
4-16
4-18
4-19
4-19
4-20

Tables
Table
Table
Table
Table
Table
T'able
T'able
T'able
T'able
T'able
T'able
T'able
l'able
"abls
Table
"able
"able

1-1.
3-1"
3-2.
3-3.
3-4.
3-5"
3-6.
3-7"
4-1"
4-2,
4-3,
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.

8804 Rev.1
UP-NUMIIR

SPERRY UNIVAC 1100/80 Syatems

.

4x4 Capability Processor and Storage Programmer Reference

Table 4-10. Summary of Use of i-Field
Table 5-1. Truth Table for Logical OR, XOR, and AND
Ta,ble 5-2. J-Register Increment Field Values
Table 5-3. Byte Status Word
Table 5-4. Byte String Sign Codes
Table 5-5. Function Byte Interpretation
Table 5-6. Subfunction Byte Interpretaion
Table 5-7. Summary of Staging Register and J-Register Fields
Table 5-8. General Input' Format for Byte-to-Floating Instructions
Table 5-9. Invalid Function Codes
Table 6- t . Device Addressing
,
Table 6-2. Channel, Subchannel, and Device States
Table 6-3. I/O System Composite State vs Condition Codes
Table 6-4. I/O Instruction Condition Codes for Byte or Block Multiplexer
Channels
Table 6-5. I/O Instruction Condition Codes for Word Channels
Tabie 6':'6. MSU Data Format - 36-Bit Format, Forward Operation
Tcable 6-7. MSU Data Format - 36-Bit Format, Backward Operation
Table 6-8. Format Flags vs Type of Channel
Tuble 6-9. CCW Flags vs Termination Conditions on Byte or Block Multiplexer
Channel
Table 6-10. CCW Flags vs Termination Conditions on Word Channel
Table 6-11. CCW Command Code
Table 6-12. I/O Statu~
T~Jble 6-13. IOU Fixed Addresses
Table 6-14. Byte Data I'acking on Abnormal Boundaries
TiJble 6-15. Scratch Pad Formats for Subchannel Expansion Feature
Table 6-16. Interrupt Mask Register
Table 7-1. Interrupt Priority
Table 7-2. Internal SIU Check
T'Clble 7-3. SIU/MSU Interface Check
TiBbie 7-4. SIU/MSU Read or Partial Write ECC Check'
Table 7-5. Machine Check lAW Bit Description
T,able 7-6. Normal Interrupt lAW Bit Description
T,able 7-7. Normal Interrupt CSW Bit Description
Table 7-8. Tabled Interrupt lAW Bit Description
Table 7-9. Tabled Interrupt CSW Bit Description
Table C-1. Mnemonic/Function Code Cross-Reference
Table C-2. Instruction Repertoire
Table C-3. Octal vs Mnemonic Instruction COde
Table 0-1. Fieldata to ASCII Code Conversion
Table 0-2. ASCII to Fieldata Code Conversion

Content.. 1 4
"AGI

4-24
5-45
5-53
5-55
5-56
5-59
5-61
5-63
5-66
5-78
6-8
6-9
6-10
6-11
6-13
6-30
6-31
6-32
6-33
6-35
6-36
6-46
6-49
6-69
6-66
6-66
7-2
7-13
7-15
7-16
7-20
7-22
7-24
7-30
7-32
C-1
C-4
C-20
0-2
0-4

I

8804 Rev. 1

SIJERRY UNIVAC 1100/80 Systems

~X4 Capability Processor and Storage Programmer Reference

UI'-MIMHR

UPOATI LEVEL

1-1
PAGE

1. Introduction

1. 1. General
This manual provides information on the SPERRY UNIVAC 1100/80 Systems central processor unit
(CPU), main storage unit (MSU), buffer storage interface unit (SIU), and input/output unit (IOU).
ThEt SPERRY UNIVAC 1 100/80 Systems are high-performance, software compatible, extensions to
the proven SPERRY UNIVAC Series 1100 Systems. The 1100/80 Systems enhance the efficiency
of 1the Serie:s 1100 Systems by offering dependable and highly effective processing in real-time,
dernand, and batch modes and excel in multiprocessing applications.
Although the Series 1100 Systems may differ in hardware design, .software compatibility is
maintained. All components of the 1100/80 Systems (CPUs, IOUs, MSUs, SIUs, and peripherals~ are
corltrolled by the SPERRY UNIVAC Series 1100 Operating System. Industry standard language
processors and application software are provided. The flexibility of the 1100/80 Systems allows the
USElr to selec:t a sy~tem to best meet his individual requirements.

1.2~.

System Components and Configurations

ThE. 1100/80 Systems configurations range from a 1x 1 (one CPU and one IOU) system up to a 4x4
(follr CPUs and four IOUs~ system. Other system components include: main storage units, storage
intEtriace units, system console, system transition unit system maintenance unit, and
motor/alternators. Table 1-1 lists all fully supported configurations. Processor organization is
baslicaUy that of a multitask processor that operates in a multiprogramming environment. A 2x2
configuration is shown in Figure 1-1 and Figure 1-2. Figure 1-3 shows a 4x4 configuration.
ThEt expansion capabilities of the 1100/80 Systems units are:
•

Main storage - expandable in 524K word increments to a maximum of 4194K words.

•

Storagn interface unit - expandable in 4K word increments to a maximum of 16K words. Two
SIUs are the maximum for any configuration, one per cluster.

•

Central processor unit - one to three CPUs' may be added to the system to form clusters of two
CPUs nrtaximum. Each cluster has access to main storage through its own SIU. Each CPU in
a clust~tr can access only the fOUs within the same cluster (i.e., no ring configurations).

•

Input/C)utput unit - one to three IOUs may be added to the system to form clusters with the CPUs.
No mo,.e than two IOUs may be present in a cluster. Each IOU can contain up to eight channel
modules which gives a total of 32 channel modules for a maximum system.

8eo4 Rev.1

SPERRY UNIVAC 1100/80 SysUtrm

4x4 Capability Processor and Storage Programmer Reference

1-2
UPDAlI LEYIL

'AGI

•

System transition unit - the system transition unit (STU) may be expanded to control and partition
SIU segments, MSU banks, CPUs, and IOUs, into two smaller independent systems called
applications, or offline for maintenance.

•

System console - one or more system consoles may be added to the system, depending on
configuration requirements and user requirements.

•

System maintenance unit - up to two system maintenance units (SMUs) may be configured in
a 2x2 system, and up to four SMUs may be configured in a 4x4 system.

•

Motor/alternator - one to three motor/alternators may be used with the system, depending up'on
system power requirements and upon degraded mode operation requirements.

The 1100/80 System can also include a subsystem availability unit which, when used in conjunction
W'ith a byte channel transfer switch, can be used for partitioning both byte and word subsystems from
a remote location.

1.2. 1. Central Processor Unit
Tne CPU is the central element of a large-scale system that is capable of serving both business and
scientific applications in batch, demand, and real-time environments. The CPU provides compatibility
with prior Series 1100 Systems at the user object code level, depending on internal code selections,
p'8ripheral configurations, and software implementation of hardware enhancements and user
irtterlaces.
The basic CPU consists of the following components:

I'

A control and arithmetic section that includes fixed-point and floating-point arithmetic:
byte-oriented instruction handling; logical data manipulation; instruction, interrupt, and
arithmetic control and control storage.

II

A maintenance section which acts as a device and a control during offline maintenance
procedures initiated, by the maintenance processor. ,-

I.

Interfaces for two IOUs, one SIU, one SMU, one STU, and the system interrupt network.

'''e CPU has the following general characteristics:
..

A complete set of arithmetic, logical, manipulative, data transfer, and sequence control
instructions.

•

A comprehensive relative addressing mechanism providing program segmentation and storage
protection.

H

An absolute addressing range of 16 million 36-bit words.

H

A basic instruction fetch period of 200 nanoseconds.

•

A general purpose microprogrammed arithmetic section.

..

A scientific accelerator module (SAM) feature that increases the execution speed of scientific
floating-point type programs.

I

8804 Rev. 1

SIIIERRY UNIVAC 1100/80 Systems

IJI'.MIMIID
_~X4

Capability Processor and Storage Programmer Reference

STORAGE 0

STORAGE 1

,-_._----.,.-------,
1

I

1

1

262K

1

I

,-

1
1

1

262K

1
1

t

282K

,

STORAGE 2

------.,. ---- ---,
I
,

,

262K

1

262K

262K

I
1

i - - - - - -.,. - - - - -

I
I

1

I
I

I

I

I

262K

1

I

1

262K

r - - -- - -

1

MMA

MMA

I

1

I

262K

1

:

I
I
'1' - - - - - - - I
1
I

I

I

1

262K

1
MMA
I
MMA
t
I
1- _ - , . ___ 1. ___ 1_ - -

MMA

1

j------------r-----

1

4K

4K

4K

MMA

MMA

MMA

MMA

I

I

1
I

..!

I
I

I

I

262K

:
I

:

MMA

I

:

IOU

IOU
EXP.

0

....

_------

SYST~M

TRANSITlON
UNIT (1)

I I

,
,,
,

j ______

t

I

IOU
EXP.

I
I
I
1

.-,-_ ... _--400 Hz

MOTOR!ALTERNATOR
(2)

SYSTEM
MAINTENANCE
UNIT (1 or 2)

SYSTEM
CONSOLES
(2 or more,

NOTES:
1.
2.

MMA

:
I

l ___ ~------------

-------,

IOU
1

~

I

I

1

I
I
I
I
I

I

262K

~-------r-------,
I
I

CPU

-------,

I
I

I

~

--

I

262K

~-------~-------:

I

CPU
0

[

~

4K

Ii

1
- - __ ~. __ I

I

I

262K

-------------------------~

t
_I

I

I

l-------.J
StU

I

--------~-------1
I
I

I
I

I

I

1

MMA

STORAGE 3
--I

I-------..L-------I
t i l

262K

262K

UPDATI LIYIL

Option.' .xp8n.ion.
MM.4 - Multi-modul. 8t:C••• unit

Figur. 1-1. SPERRY UNIVAC 1100/82 2x2 S~tfIm S.gmtHfr/C8b;n.t Configur8tion

'

.J

SPeRRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

STORAGE 0

STORAGE 1

1"'------.,.-------,

r'------.,.-------,
I
I
I
I

I
I
I
I

262K

I
I
I
I

I
I
I
I

262K

I
I
I
I

262K

262K

262K

262K

282K

MMA

MMA

MMA

MMA

:

SIU

~....

..

·····r

4K

4K

4K

4K

MMA

MMA

MMA

MMA

I

I
I
I
I

262K

I

j

CPU

CPU

0

1

~

,-

-------,

·1

I

I

IOU
EXP.

IOU

0

------

SYSTEM
TRANSITION
UNIT (1)

I

,
I

....

,.

IOU
1

I -------,

I
I

IOU
EXP.

,
I

----_ .. ..
I

.-

400 Hz
MOTOR/ALTERNATOR .

SYSTEM

MAINTENANCE
UNIT (1 or 2)

(2)

SYSTEM
CONSOLES
(2

or more.

NOTES:
1.
2.

3.
4.

Option'" .xPMJMNI.
MMA - Multi-modultl ~.. unit
S~Mt/B"'k CDIIflguntion• .,. ,.ltrict~ to singltl t:lu.,., .,.,.",. only.
. . .. RmundMJt intwfM:n only M:titI.tm if til.
HglNnt i. mung from til• •pplic.tion.

om.,

Flgurtl 1-2. SPERRY UNIVAC' '00/12 b2 S~ S~""t/B"'k Conliguntion

-----b

080.. R.v.1

PERRY UNIVAC 1100/80 Systems

4)1~4

.

Uf'.HUMBSl

STORAGE 1

STORAGE 0

,I

I
I

~~62K

I

262K

I
I

,,

,
,I

, - - - - - - i - - - - - --,

I

I

, - _. - - - - i - .. - - - - -,
I

.

1-5

Capability Processor and Storage Programmer Reference

,

I

,I

I
I
I

262K

262K

-

STORAGE Z
,------,-------,
,
,

,

STORAGE 3

,,- -- - -,,.------ -,

I

t

I

I

I

I

262K

I
I

262K

PAGI

UPDATE LEVEL

t
I
I

I

I
I

I
I

262K

262K

I

:~62K

282K

282K

282K

262K

282K

262K

282K

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

I I
I

l

I

I

J

I

I

SIU 0

·1

r

SIU 1

4K

4K

4K

4K

4K

4K

4K

4K

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

I I

I

I I

J

I

I

I

I
CPU
.

0

CPU
1

J

"-

I ---._-,,

IOU

0

IOU

I

EXP.

I
I

-.-----

I

sys'"E]:M
TRANsmON

~(11
i

I -----,
IOU
1

IOU

EXP.

I
I
I

2

(2)

3

-----,

-----,

t
I

400 Hz
MOTOR/ALTERNATOR

CPU

2

J

-

IOU

_.. _---

CPU

IOU
EXP.

I
t
I
I
I

------

SYSTEM
MAINTENANCE
UNITS (2 to 4)

I

IOU

IOU

I

3

EXP.

I
I
I

-----SYSTEM
CONSO,LES
(4

or more.

NOTES:
1.
Option.' eXfMnsion.
2.
MMA - Multi-module M:ceu unit
3.
Sto".gII interfllce units must ellch contllin lin sqUill lIf'Itount of storllge.

Figun, 1-3. SPERRY UNIVAC 1100/84 4x4 5",.", Seg",."t/Cebinet Configul'lltion

I
I
I

I

T=!JI= 1- I. Minimu/p'/Ahximut" Function.1

i:

Configur.tio,,~

~C4

Configurations

System
Components

~m

&>~

lxl

lx2

2x1

2x2

2(lxl)

2x3

2x4

3x2

3x3

3x4

4x2

4x3

4x4

CPU

1

1

2

2

2

2

2

3

3

3

4

4

4

IOU

1

2

1

2

2

3

4

2

3

4

2

3

4

'Oc

QlZ

2:<

f~
"11g~

CD

(I

.0

262K- 262K- 624K- 624K- 624K- 624K- 624K- 624K- 624K- 624K- 624K- 624K- 624K4194K 4194K 4194K 4194K 4194K 4194K 4194K 4194K 4194K 4194K 4.194K 4194K 4194K

Main Storage
Words
SIU

1

1

1

1

2

2

2

2

2

2

2

2

2

SIU
Words

4K16K

4K16K

4K16K

4K16K

8K32K

8K32K

8K32K

8K32K

8K32K

8K32K

8K32K

8K32K

8K32K

-en
~1
~;

a.-

en
S
Q1

System Console

l-N

2-N

1-N

2-N

2-N

3-N

4-N

2-N

3-N

4-N

2-N

3-N

4-N

STU

1

1

1

1

1

1

1

1

1

1

1

1

1

cO
(D

"11

a

cQ

Q1

3
3

CD
~

::D

CD

SMU

1

1

1

1-2

2

2

2

2-3

2-3

2-3

2-4

2-4

2-4

;-

MotorlAlt.

1-2*

1-2*

1-2*

2-3*

2-3*

2-3*

2-3*

2-3*

2-3*

2-3*

2-3*

2-3*

2-3*

~
~
n

~----~

..

_- '------

--

--

NOTES:

* A rlJdundanl motor/lllttlfnlltor may blJ configuftld only as a static unit.
1.
2.

This chart includes the minimum configurations which can be supported in degraded operations.
N equals any number required.

3.

Configurations greater than a 2x2 muSI be configured as two clusters (e.g., a 2x3 is configured 81 8 1x 1 and a 1x2).

4.

The number of motor/ahernalor. configured dependl on system load and motor/alternator power rating and on site degraded mode operating requirements.

(D

!
~

i_

~

8804 Rev.1
UP-HUMIIR

I

SPERRY UNIVAC 1100/80 Systems

~'x4 Capability Processor and Storage Programmer Reference

1.~~.2.

1-7
UIIOATI L&VEL

PAGE

Stolrage System

Th.~

1100/80 Systems storage system consists o,f large capacity, low cost, main storage units (MSUs);
inttHfaced by moderate cal)acity, high speed storage buffers located in a separate cabinet called a
storage interface unit (SIU). The high-speed storage buffers are used to achieve increased
pe,'formance from the relatively low-speed MSUs. Each MSU can be divided into two separate banks.
Eac:h SIU contains from one to four logically independent storage buffers called segments. A main
storage bank has a 2-port multimodule access (MMA) unit which allows access by two SIU segments,
and providel; a means for common accessing of main storage. The SIUs also provide the main storage
intfltrface to the system" requesters (IOUs and CPUs). This interface is provided by 8-port MMA units
ass~ociated with each segment of the SIU.,
An SIU buffer segment is a set associative buffer having four words per block and four blocks per
set. The interface between an SIU and main storage provides a 4-word wide transfer on a single
reald reques'r, and a 1-word wide transfer on a write request. When a word is required from a block
of data not ,already resident in the SIU, the request is made to the MSU and the new 4-word block
of data is brought in. During the wait for this new block, the SIU segment is free to service other
reCluests. On a write operation, the storing of a full word or hr:llf word consists of modifying the word
in the buffer segment (if present), and also storing the word in the MSU. On a partial-word write,
thE' word in the buffer segment (if present) is invalidated, and the partial write is made into the MSU.
A '"ext request for this invalidated word will cause its 4-word block to be brought in from the MSU.
Operation of the SIU buffers is transparent to software, although performance of the main storage
is dependent on the organization of the software. This is true to the extent that software organization
aff:ects the miss rate. or percentage of instructions or operands not located in the buffer when first
rec~uested. ,
The minimum system contains 524K words of storage located in a single cabinet. This can be
expanded tC) t-048K words in the cabinet, and up to four storage cabinets may be employed to provide
a total of 4194K words of main storage. Three or more MSUs are required in a system larger than

a :2x2.
The basic SIU contains 4K words of buffer storage and can be expanded by adding ,one to three
lo~~ically independent 4K buffers, giving a maximum buffer size of 16K in the SIU. Two SIUs are
required for all systems having more than two CPUs, aHowing a maximum of 32K words of buffer
st4)rage in the system.
A detailed description of the SJU/MSU configuration assignments is given in Section 3. Figures 1-1,
1··2, and ,·-3 show the different configurations.

1.2.3. Input/Output Unit
AI' 1100/8:0 Systems configuration includes at least one IOU: The IOU controls all transfers of data
btttween the peripheral devices and main storage. Transfers are initiated by a CPU under program
ccmtrol. The! IOU includes independent control paths to the CPU and data paths to main storage. The
mode of I/O transmission is through either byte channels or word channels.
The IOU consists of two sections: a control section and a section containing three or four input/output
channel modules. An IOU expansion allows up to four additional channel modules to be added to
the IOU. The word 1/0 channel module provides four independent word I/O channel interfaces and
ol:cupies one channel module position. A second IOU with identical expansion capabilities can be
added to each CPU cluster.
The control section includes all logic associated with the tra'nsfer of function, data, and status words
'between ",ain storage and the subsystems." It also services I/O requests from either one or both of

...........

8SO.. Rev. 1

SPERRY UNIVAC 1100/80 Systeme

4x4 Cap-9bility Processor and Storage Programmer Reference

1-8
,AGI

the CPUs (in a multiprocessor system) and routes interrupts to one of the two CPUs. Interrupt routing
may be specified by program.
Sorne capabilities of the IOU are:
•

I/O transmission through byte channels or word channels

•

Channel transfer rates

at.

1.67 x 106 bytes per second (maximum) on a block multiplexer channel;
200 x 103 bytes per second (maximum) on a byte multiplexer channel; or
500 x 103 words per second aggregate for a word channel module.
•

Externally specified index (ESI) and internally specified index (151) transfer modes on the word
channels.

•

Channel buffering

•

Interrupt tabling

•

Parity generation/checking capability on all 151 channels and byte channels.

1.:t4. System Console
The system console provides the means for operator communications with the Executive System. The
basic console consists of the following major components:
•

The CRT/keyboard consists of a UNISCOPE 200 Display Terminal. The display format is 24 lines,
with 64 characters per line. The 7-bit ASCII character set, consisting of 95 characters plus the
space. is used. The keyboard provides all of the operator controls to use the UNISCOPE display
.
terminal and communicate with the CPU.

•

The incremental printer operates at 30 characters per second and provides a hard copy of
console messages. (Five additional incrementa. printers may be connected to a console.)

•

Maintenance interface for remote console operation by means of the system maintenance unit
and a remote maintenance system.

•

The fault indicator, located on the incremental printer, provides the operator with a visual
indication of a fault condition in a major system component. The actual component and nature
of the fault may then be determined from indicators on the operator/maintenance panel on the
system transition unit.

•

A standard byte .multiplexerchanne' interface.

8804 Rev.1
UI'-NUMID

I

SPERRY UNIVAC 1100/80 Systems

~'X4

1.:tS.

Capability Processor and Storage Programmer Reference

1-9
U~T1!

L!VII.

!fAGE

System Transition Unit (STU)

Thi9 STU contains the controls and indicators required for control and assignment of the system units.
Thi9 functions controlled by the STU are:
•

Partitioning
The STU partitioning function provides the ability to assign the individual central complex units
(CPUs, IOUs, SIU segments. and MSU banks) of a system to either one or two independent
smaller systems (applications 0 or 1), or to isolate a unit from either application for offline
concurrent maintenance.
The partitioning function also indicates the operational status of each central complex unit.
These status conditions are available to system software for configuration control.
The ability to partition peripheral subsystems is provided by the subsystem availability unit
(SAU), controls on the individual subsystems and, optionally, for some subsystems by software
comm2lnd. In addition, a form of partitioning is provided in that the STU has the capability of
partitioning at the channel module level in the IOU. Each channel module may be placed offline
or onlil1e by toggling a switch on the STU.

•

Initial Load
InitiallcJad provides the ability to set module select register (MSR) values, select initial load paths,
and initiate the initial load operation for either one of two applications. The MSR selects the
section of main storage where the instruction execution sequence is initiated on an initial load.

•

Automl!tic Recovery
Automi3tic recovery provides the system, specified in Application 0 or 1, with an automatic
. system recovery capabifity. When automatic recovery is enabled, and the system software does
not reset tne automatic recovery timer within the preset time interval, the STU ctears, reloads,
and reinitiates the system. The system provides two recovery paths. If the two recovery paths
are within the same application and the first recovery path fails, the alternate recovery path is
automcltically initiated. If only one recovery path is in the application, and the first recovery
attempt fails, the same path is tried once more. If recovery again fails, an indicator on the STU
panel is lit and no more. recovery attempts are made. The recovery function provides for
software resetting of the automatic recovery timer and for selection of the automatic recovery
path tel be used by the next recovery attempt (two paths in the application).

•

Proces:sor and Input/Output Unit Controls
This palnel provides the controls and indicators required for manual control of up to four CPUs,
four IOUs, eight SIU segments, and eight MSU banks.

•

Interface with SAU
The interface with the SAU is used to convey IOU application information to the SAU for the
purpose of word channel subsystems partitioning.

8104 Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

IJILM . . . .

UPDATI LIVIL

1.2.6. Subsystem Availability Unit (SAU)
The SAU provides the 1100/80 System with the ability to partition word subsystems. and byte
subsystem strings by means of 'an operator-controlled panel. Word subsystems and byte subsystem
strings may also be placed offline. The SAU also provides subsystem partitioning status. Partitioning
of major system components is still accomplished at the partitioning panel on the STU.
The SAU is the primary device used to control partitioning of peripheral subsystems within a
multiprocessor system. The SAU contains the controls for partitioning word control units (CUs) by
application. The CUs must have a UNIVAC Shared Peripheral Interface (SPI) for the SAU to exercise
this controL The SAU allows the word subsystems with SPls, to be assigned to Application 0,
Application 1, or offline. The SAU provides a status word to the Operating System, through one word
channel per IOU, which contains CU path partitioning selection information.

1.:2.7. System Maintenance Unit (SMU)
The SMU provides for diagnostic checkout and fault isolation of the CPU, IOU, and SIU by the
automatic comparison of logic status against known correct data. The SMU includes a maintenance
pr,ocessor, card tester, communications capability, UNISCOPE 200 Display Terminal, and peripherals.

1.2.8. Auxiliary Storage and Peripheral Subsystems
The 1100/80 Systems offer a full range of auxiliary storage and peripheral subsystems to provide
the capability to satisfy many requirements. The standard SPERRY UNIVAC Subsystems include:
•

SPERRY UNIVAC 8405/8430/8433/8434/8450/8470 Disk Subsystems

•

SPERRY UNIVAC 8425 Disk'Subsystem

•

UNIVAC FH-432/FH-1782 Drum Subsystem

•

UNISERVO 30 Group Magnetic Tape Subsystems

•

UNISERVO 22/24 Magnetic Tape Subsystem

•.

UNISERVO 14 Magnetic Tape Subsystem

•

UNISERVO 20 Magnetic Tape Subsystem

.;

UNIVAC 0716 Card Reader Subsystem

•

UNIVAC 0604 Card Punch Subsystem

•

UNIVAC 0768 Printer Subsystem

•

UNIVAC 0770 Printer Subsystem

•

SPERRY UNIVAC 0776 Printer Subsystem

•

SPERRY UNIVAC Telcon System

..

SPERRY UNIVAC General Communications Subsystem (GCS)

8804 Aft.1

SF'ERRY UNIVAC 1100/80 SYiternl

UlLMIMI...

4,,4 Capability Processor and Storage Programmer Reference

•

SPERRY UNIVAC UTS 400 Display Terminal

•

SPERRY UNIVAC UTS 400 Text Editor

•

SPERRY UNIVAC BC/7 System

•

UNISCQPE 200 Display Terminal

••

UNISCQPE 100 Display Terminal

•

UNIVAC OCT 500 Series Data Communications Terminals

•

Remote SPERRY UNIVAC 90/30 Subsystem

1-11
'AGE

1.2.9. DestcJndardized Subsystems
Some auxiliary storage and peripheral subsystems used on earlier model Series 1 100 <;ystems can
be c1onfigured, but Sperry Univac will not enhance any of the existing Series 1100 software for these
dest:andardizEld subsystems.

1.2.10. Minimum Peripheral Complement
The 'following list of peripheral equipment is the minimum for the 1100/80 Systems. This minimum
has Ibeen est~tblished to ensure an adequate complement for Sperry Univac customer engineering
and software support.
Minimum Complement

Alternate

1.

One 0716 Card Reader and one 0770
High SpI,ed Printer Subsystem

One 0716 Card Reader and one 0776 or 0768
High Speed Printer Subsystem

2.

8450 Di:sk Subsystem with one control
unit and two 8450 Disk Storage Units

8470 Disk Subsystem with one control unit and
two
8470
Disk
Storage
Units:
or
8430/8433/8434 Disk Subsystem with one
control unit and two 8430, 8'433, or 8434 Disk
Storage Units; or 8425 Disk Subsystem with one
control unit and two 8425 Disk Storage Units

3.

Magnetic: tape subsystem with one
control unit and four UNISERVO 30, 32,
34, or 316 Magnetic Tape Units

Magnetic tape subsystem with one control unit
and four UNISERVO 22, 24 Magnetic Tapl! Units.
or one control unit and four UNISERVO 20
Magnetic Tape Units; or one control unit and four
UNISERVO 14 Magnetic Tape Units

peRRY
~
----S804 Rev.l

Ul'-MJ. . . .

UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Program~er Ref.rence

uflDAn LIVEL

2-1
IIAG&

2. Processing Unit

2. 1. General
The! 1100/80 Systems central processor unit (CPU) contains a conuol section, an arithmetic section,
a maintenanl:e section, a general register stack, and interfaces through which it is connected to other
equipment. The IOU controls all data transfers between peripheral devices and storage. Transfers
are initiated by a CPU under program control.

2.2. Contrc)1 Section
The' control section of the CPU interprets instructions and directs all processor operations except
certain I/O clperations. It is discussed briefly in this section and in more detail in 4.2.

2.2. 1. Con'trol Section Operation
The! program instruction words are sequentially loaded into the control section. Each instruction word
is interpreted by the control section which generates the signals necessary to perform the instruction.
The! instruction words are located in main storage and the data words (operands) are located either
in main storlJge or in the addressable control registers which are part of the control section. The
con,trol sectilon includes an address formation segment which generates the absolute main storage
addresses tCI obtain the instruction words.
Thel instruction word is divided into fields. These fields specify to the control section the function
to be performed, which portion of the operand is to be used, a control register, indexing, index register
modification, indirect addressing, and an operand address.

).2.. 2. Instl'uction Repertoire
Thel instruction repertoire includes fixe~oint and floating-point arithmetic. logical functions, byte
opElrations, block transfers, comparisons, tests, 1/0 control, and special purpose instructions. There
are over 200 basic instructions in the repertoire. 'Partial-word data transfers and repetitive operations
are .included in the instruction repertoire. Indexing capability is provided with all instructions. Indirect
addressing capability is also provided and is usable to any level with full indexing capability at each
leV4tl.
Ins1tructions such as data transfers. singJe-precision flxed-point adds, and certain logical functions,
require less'than 250 nanoseconds for complete execution. Indexing (18-bit) does not add to the
exe!cution tirne of an instruction. Details of the instruction repertoire are found in Section 5.

8804 Rev.1

SPERRY UNIVAC 1100/80 Systema

4x4 Capability Processor and Storage Programmer Reference

2-2
ftAGI

2.:Z.3. Control Registers
The 128 addressable control registers in the general register stack (GRS) of the control section are
integrated-circuit registers. These control registers are addressed either explicitly or implicitly by
thtt instructions. They fall into four categories: index registers, arithmetic registers, special registers,
and unassigned registers.
The control registers are discussed in detail in Section 3.

2.,2.4. Data ShiftiComplemerit/Store Operation
The CPU includes circuitry which permits the various. store instructions to bypass the arithmetic
se'ction. This circuitry includes the shifting capability needed for storing partial words in main
storage, the sign testing capability needed for the St~re Magnitude A instruction, and the·
complementing capability needed for the Store Negative A and Store Negative Magnitude A
instructions.

2.3. Arithmetic Section
All arithmetic computation is microprogram controlled and is performed using the nonaddressable
re'gisters of the arithmetic section. These arithmetic processes can be performed in either fixed-point
or floating-point mode.
Fixed-point arithmetic instructions provide for single-precision,
double-precision, half-word, and third-word addition and subtraction, and for fraction and integer
m1ultiplication and division. Floating-point instructions provide for both single-precision and
double-precision operation. The arithmetic section also performs certain logical operations such as
shifting and comparisons. The instruction word may be used to specify the transfer of any chosen
portion of a word (half, third, quarter, or sixth) to the arithmetic section. The ability to transfer only
the selected portion of a word minimizes the number of masking and shifting operations required.
A shift matrix in the arithmetic section permits the completion of an entire single word shift operation
in one main storage cycle time. By use of the matrix, the shift operation can shift a singte or double
w'ord operand in either direction up to 72 bit positions.
A scientific accelerator module (SAM) will enhance the performance of the following arithmetic
instructions:

Add
Multiply (Fixed point)
Divide (Fixed point)
All floating-point instructions, both single and double precision
Details on the operation of the arithmetic section are found in 4. 1.

2.4. Maintenance Section
The maintenance section performs all diagnostic tests using its own repertoire of commands. It
operates only when the CPU is in maintenance mode. In this mode the processing system can be
operating either online or offline. When online, the processing system and the maintenance system
operate concurrently. In this case the maintenance system is connected to and operating on the byte
bus, and the processing system operates normally, except that the processing operation is suspended

8804 Rev.1

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whenever the maintenance system needs to use the processor data and control paths for executing
a flnaintenance function.

2.fS. Input/Output Unit (IOU)
The IOU is j~ separate functional entity. I/O activity is initiated when the interpretation of certain
instructions by the CPU causes signals to be sent to the IOU. Once an I/O operation is initiated. the
10lJ and the subsystem control the input and output transfers. The IOU operates with a wide variety
of peripheral devices, and it requires minimal attention from the CPU.
Once an I/O operation is initiated by the program, I/O activity is independent of program control. The
1/01 data flows between main storage and the peripheral subsystem through an I/O channel. Each
1/01 channel consists of 36 input data lines. 2 input parity lines, 36 output data lines, 2 output parity
lintts, and v~Jrious control signal lines. All data word bits are transmitted in parallel to or from the
subsystem.
The! IOU has five interfaces: a storage interface, a processor interface, a control unit-peripheral
intl!rface, a system transition unit interface, and a maintenance interface.
De'tails of the IOU are presented in Section 6.

2.Et System Status Word
The, system status word, which originates in the system transistion unit (STU), indicates to the system
software thl!t partitioning status of each unit and also system status. This status information is
transferred to each storage interface unit (SIU) segment where it can be read by a CPU through a
spEtclal command code. The status information is not interpreted by the SIU. The power status in
eac:h unit will be indicated on the partitioning panel of the STU, and loss of dc power in a unit will
force the stl3tus of that unit to be offline.
The!!! system status word is divided into two 36-bit words (System Status Word 0 and System Status
W()rd 1). Figure 2-1 shows how the status words are divided into fields. Each word contains two
fields of data, one for application information and the other for load path information. Each system
component has two application bits that are translated as follows:
Applic~.tion

()

0

Application

o

- Offline

= Application 0

()

o

- Application 1
- No System Transition Unit

8104 "".1

SPERRY UNIVAC 1100/80 Syama

4x4 Capability Processor and Storage Programmer Reference

~MI_

N

LOAD PATH 0

0

F

APPliCATION 0

R
I

T

T

U

U L S

S

L U I 0 0 L H H N
T S U U C P 1 0 T

AUTO

A C

E
0

M

P

I

M

sau

MSU

R N P P I

7 IS..

3

2

1 0

7 1 S .. 3

2

1 032

•• 35 3. 33 32 31 30 28 28 27 21 25 24 23 22 21 20 18 18 17 11 1S 14 13 12 11 10 9 8

LOAD PATH 1

F
P

7 1

1 032

1 0

5

1 0

4 3

M

MSU

SIU

IOU

PAOC

A

U L S I R N P P I
.L U I 0 0 L H H N
T S U U C P 1 0 T

USED

7 1 5 .. 3

2:

1

o

7

e

5

..

3

2

1

032

•• 31 34 33 32 31 30 29 28 27 21 25 24 23 22 21 20 18 18 17 1IS 1!5 14 13 12 11 10 9 8
MAINT -

7 1

1 032:
5

4 3

2:

1

0

1 0

Maintenance Mode 1 - One or more system components In that Ippllcation are in maintenance mode.

R/T M - R..I TIme Mode 1 - Real Time Mode
AUTO - Auto Recovery

HLP - 1 - Load Plth·1 next if both laid pathl in the same word Ire in auto recovery mode.
PH 1 -

1 - Load Path 1 is enabfed II In auto recovery load path for thlt application.

PHO - 1 - Load Path 0 il enabled

81 an auto recovery load path for thlt application.

LOAD PATH

- 1 - Indic~ that 10ld path ha. failed.
- 1 _ Indieat.. that the following thr.. components Ire in Cluater 1.
- 1 - IndiC8tH
upper il in the load path.
- 1 - Indicat.. the odd IOU i. in the load path.
- 1 - IndicatH the odd PAOC Is in the load path.

sau

-IOU

·PAOC
NOTES:

..•

2:

APPUCATION 1
AUTO

A C

NOT

PROC

IOU

A

Th... ItJgit: ,.".. rwuIt 1ft.,. • #iQnM invwsion ., th. SIU•
.,.". bit poMion 01 the mtw won:J .. • ent by the SIU 6egmen, to the eN.

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SPERRY UNIVAC 1100/80 Systems

UI'-NIJMe8I_~X4 Capability Processor and Storage Programmer Reference

3-1
UPDATI LI\1L

"AGE

3. Storage System

3. 1. Genef'al
ThEt storage system comprises up to 4,194,304 words of main storage, up to 32,768 words of
high-speed buffer storage, and 128 addressable control registers.
Main storag'8 consists of one to four main storage units. depending on user requirements. Main
storage provides the storage for the instruction and data words. The high-speed buffer storage
corlsists of elne or two storage interface units, depending on user requirements. The high speed
buffer stora~Je provides accelerated response between main storage and the central processor units,
and between main storage and the input/output units. The 128 addressable control registers are
loc,ated in the control section of each central processor unit. These registers provide fast access
storage for data and control words.
ThEt storage interlace unit (SIU) high-speed storage buffers are grouped in sets of four blocks of four
words each. A set is addressed directly by selected bits of a 24-bit absolute address. The remaining
bitn are used to make a comparison with the 4 block addresses to determine if the required block,
and hence word, is present in the set. When a word is required from a block of data not resident
in the SIU buffer, the SIU makes a request to main storage and the new block of data is loaded into
the buffer.
3.~~.

Main Storage Unit

Th4t main stl)rage unit (MSU) consists of two independent banks. Each bank contains 262K 43-bit
words consisting of 36 data bits and 7 error correction code (ECC) bits. Each bank is expandable
to CI maximulm of 524K words. The MSU bank js accessible via a two port multi-module access (MMA.)
module.
Thlt MSU contains an internal exerciser for offline operation in the maintenance mode. The exerciser
USEtS much ()f the logic contained in the interface section of the MSU. and is capable of operating
in ~In offline mode with either bank while the other bank is online. The maintenance mode is switch
selectable at the MSU. Online availability is indicated to the SIU by the presence of the MSU
AVAILABLE signal.
The! MSU is capable of performing read, write, and partial write operations. Data is transferred from
thel MSU on a read operation and to the MSU on a write or partial write operation. A description
of the open.tions performed within the MSU follows:

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SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

...... 1UIIIt

3-2
ftAQI

•

Read - The MSU reads a full block of data consisting of four contiguous words (172 bits, 144
data and 28 ECC bits) from storage and transfers the information to the SIU via a 4-word
interface in one data transfer.

•

Write - The MSU writes one word (36 data and 7 ECC bits) of new information into the specified
storage location.

•

Partial Write - The MSU reads a data block (four contiguous words) from storag~. Only that
portion of the addressed word (one of the four words) which is enabled by the write control lines
is modified with new write data. A new ECC is generated for the combined read and new write
data. Then both the new word and the ECC bits are stored.

•

Refresh - The MSU is a volatile storage device and requires a refresh cycle to maintain the data.
Each MSU bank generates its own refresh cycle. Refresh signals are generated at 24
microsecond intervals. The refresh cycle is continually sequenced through the storage bank
such that 1/128 of the bank is refreshed during each refresh cycle.

3 ..2. 1. Write Data Error Detection
The requester (the SIU) sends 36 bits of write data plus a 7-bit ECC to the MSU. The MSU generates
a 7-bit ECC from the 36 data bits received and then compares that code with the 7-bit code received.
If ill single bit error or multiple error is detected. the reference is executed, the special ECC is stored
in the addressed location to indicate corrupt data on future requests to that location, and a WRITE
D)~TA CHECK signal is sent to the requester. All 144 read data lines and all 28 ECC lines from the
M:SU to the requester remain inactive during a write cycle.

3.2.2. Partial Write Error Detection
On a partial write request. the MSU 'retrieves the data word to be modified from storage and compares
the 7-bit ECC retrieved from storage with the 7-bit ECC generated from the read data by the MSU.
If no errors are detected on the data word retrieved from storage or on the write data to be written,
the word is modified and a new ECC is stored. If errors are detected on the data during a partial
write. the MSU responds as follows:
•

If a single bit error is detected on the data word retrieved from storage. the data bit in error is
corrected. the word modified. and a new ECC is stored.

•

If a multiple bit uncorrectable error or the special ECC is detected on the data word retrieved
from storage. the word is not modified and the stored ECC is retained.

•

If the MSU detects a single bit error or a multiple bit uncorrectable error on write data. the data
word is modified and the special ECC is stored-in the ECC bits. The MSU sends a WRITE DATA
CHECK signal to the requester.

•

If the MSU detects both a single bit error on the data word retrieved from storage and a single
bit error or multiple bit un correctable error on the write data. the word is modified and the special
stored in the
bits. The MSU sends a WRITE DATA CHECK signa. to the requester.

ecc

..

ecc

If the MSU detects both a multiple bit uncorrectable error or the special ECC on the data word
retrieved from storage and a single bit error or multiple bit uncorrectable error on the write data
to be written. the word is not modified and the ECC is retained as stored. The MSU sends a
WRITE OATA CHECK signal to the requester.

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SPERRY UNr/AC 1100/80 Systems

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UPDATI LIYB.

3.2,.3. ECC Write Check Disable
When the EC:C WRITE CHECK DISABLE signal is activated by the requester, the MSU writes the data
anell the ECC as received for either a full-word write or a partial write. The WRITE DATA CHECK signal
is not transfttrred and the special ECC is not stored in the ECC bits if a write data error is detected.
Thel specia' I:CC is stored, however, if the MSU detects a write-control parity error. When the ECC
wri1te-check disable operation is performed, the stored data must be restored to correct the ECC by
either software or by the MSU offline exerciser before returning the bank to an online condition.

3.2.4. Write Control Parity Checking
Thel requestEtr sends nine write-contro' plus one write-contro' parity signals. The MSU checks for
odd parity. If a write-control parity error is detected, the MSU performs a partial write function and
the special ECC is stored in the location to indicate corrupt data on future requests to that location.
Thel MSU sends a WRITE CONTROL CHECK signa' to the requester.

3.2.5. Address Parity Checking
Thel requestEtr sends 21 address bits plus one address parity bit. The MSU checks for odd parity.
If the MSU detects an address parity error, the MSU responds as follows:
•

If the request is for a read, the data block is transferred and the MSU sends an ADDRESS CHECK
signal to the requester. Future requests are accepted by the MSU.

•

If the rEtquest is for a write. the word is stored with the new ECC bits at the location selected.
The MSU notifies the requester via the ADDRESS CHECK signal and the system transition unit
(STU) via the write address check line. The MSU does not accept further requests to the bank
in which the address parity error was detected until any requester partitioned to that bank sends
a system CLEAR signal. The WRITE ADDRESS CHECK signal sent to the STU is maintained by
the MSU until ,cleared manually at the MSU.

•

If the request is for a partial write. the data word selected is modified and a new ECC is stored.
The MSU notifies the requester via the ADDRESS CHECK signal and the STU via the write
address check line. The MSU does not accept further requests to the bank in which the address
parity error was detected until a requester partitioned to that bank sends a system CLEAR signal.
The Wf~ITE ADDRESS CHECK signal sent to the STU is maintained by the MSU until cleared
manually at the MSU.

3.2~.6.

Refr'esh Fault

If al refresh fault is detected, theMSU completes the cycle upon which it is operating. Upon
cOl'1npletion ()f the cycle, the MSU .stops and no further requests are honored. A signal is sent to the
STU to indicate an error; also, the error is indicated at the MSU. To clear a refresh fault from a bank
of l~torage r4tquires one of the following:
•
•
•

powerh,g down that bank and powering. back up,
. going from an offline condition to an online condition at the STU, or
performing a check reset at the MSU maintenance panel while the bank is offline.

....

8804 Aw.1

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SPERRY UNIVAC 1100/80 Syaema

4x4 Capability Processor and Storage Programmer Reference

3.,2.7. Fixed

Addr~ss

Assignments

The interrupt subroutine entrances and certain status words are assigned fixed'iocations in main
storage as shown in Tables 3-1 and 3-2. The listed addresses are relative to the contents of the
7-bit module select register (MSR) and the position of the MSR ACTIVE UPPER/LOWER switch. MSR
may be manually loaded by sening the desired combination of the seven MSR switches and the MSR
ACTIVE UPPER/LOWER switch on the STU partitioning panel. When an initial load operation is
performed, the value in the MSR identifies the main storage area in which the incoming data is to
be stored. During an externally specified index input/output (ESI-1I0) operation the value in the MSR
identifies the high order bits of the address of the main storage locations from which the ESI access
control words and chain pointer words are obtained.

r.bl.3-1. FiXH Add,... AuignmtMttI 020O-.NUMIBI

I

SPERRY UNIVAC 1100/80 Systems

~J Capability Processor and Storage Programmer Reference

4-3
UIlDATi LiYIL

IIAG.

4.2.4. Fixed·-Point Single- or Double-Precision Add or Subtract Overflow and Carry
In fix1ed-point arithmetic. the execution of certain instructions can result in an overflow or a carry
condi:tion. During execution, the overflow designator (01) and the carry designator (DO) bits are
clear.,d to zeros; the overflow and carry conditions set bits 01 and DO. respectively. in the designator
regis1ter. These bits can be sensed by certain other instructions. Each of these designators, when
set t(J1 one, remains in the set condition until the next time anyone of the instructions in Table 4-1
is ex.tcuted or until the Load Designator Register instruction is executed.

4.2.4~.

1. Overflow

An overflow cc)ndition is detected when one of the 10 instructions in Table 4-1 is executed and the
numeric value of the result obtained exceeds the maximum numeric value that can be contained in
the r.!tgister hc)lding the final result. Under this condition the resulting sign will be incorrect. an
overflow enable is generated and sent to control, and 01 is set.

Function Code (Octal)

f . 14,

j

-=

f - 15,

j

== 00-17

f . 16,

j • 00-17

f •

'17.

f.20.

-=

j

::I

00-17

00-17

j - 00-17

Instruction
Add to A
Add Negative to A
Add Magnitude to A
Add Nega'tive Magnitude to A
Add Upper

21.

j -

00-17

Add Negative Upper

f -

24,

j -

00-17

Add to X

f -

:ZS,

j - 00-17

Add Negative to X

f -

'71,

j - 10

Double-Precision Fixed-Point Add

'71,

j - 11

Double-Precision Fixed-Point Add Negative

f

f

==

4.2.4.2. Caf'ry
A calrry condition is detected when an end-around carry occurs during the execution of an instruction
listed in TablEt 4-1. The detection of a carry condition indicates that a carry was propagated out of
the !Sign bit position and automatically added into the low-order bit position. The detection of the
car", condition is significant when programming multiple-precision routines. In ones complement
subtractive arithmetic, the carry condition can be equated to the no borrow condition, and the no carry
condition to the borrow condition.
The condition of the carry designator can be tested by executing either the Jump Carry or Jump No
Carry instructions. Table 4-2 lists the sign combinations for which the carry designator would be
set to 1 indicating that a carry has occurred.

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8104 Rev.1
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4x4 Capability Processor and Storage Programmer Reference

Input Operand Sign

Operation

Resultant Sign

Augend

Addend

+

-

+

-

+

+

-

+

-

-

Minuend

Subtrahend

+

+

+

-

-

+

+

+

-

+

-

Addition

Subtraction
(add negative)

-

4.2.4.3. Arithmetic Interrupt
Thl! arithmetic section cannot cause a system interrupt. But, when an arithmetic fault occurs, it
gel,erates a fault condition signal which allows the control section to set the appropriate designator
bit. Other processor 'conditions in conjunction with those arithmetic fault conditions determine
whether or not control generates an interrupt.

4.2.5. Fixed-Point Division
The process of dividing one fixed-point number by another consists of,transferring the numbers to
the, arithmetic section, performing a series of trial subtractions to form a quotient and a remainder,
transferring the properly signed quotient to a register and, if the remainder is to be saved, transferring
the properly signed remainder to another register. All divide operations use the main adder and
shifter.
~I

4.2.6. Fixed-Point Multiplication
The arithmetic section contains a fast multiplier unit to handle multiplications. The main adder and
shifter are used only in the beginning and 'ending cycles for input and output data adjustments.

4.2.7. Floating-Point Arithmetic
Floating-point arithmetic handles the scaling problems which arise in computations involving
numbers which vary widely in range. In floating-point arithmetic, the numbers are represented in
a :special format so that the computer can automatically handle the scaling.

-------U
8804 Rev.1

PE:RRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

UflDATi LIYIL

4.2.EI. Floating-Point Numbers and Word Formats
Floatling-point numbers in the instructions are represented in single-precision format as a 27-bit
fractional qual1tity multiplied by the appropriate power of two, or in the double-precision format as
a 60--bit fractional quantity multiplied by the appropriate power of two. The power of two is called
the exponent. In machine representation, the exponents are biased to make them lie in the range
of positive nurnbers or zero. These biased exponents are called characteristics. The fractional part
is referred to ctS the mantissa. The two format types, single-precision and double-precision, are as
follows.

~_'_~_~_._ri_'U_·C__~~_______________________M_a_n_ti_~________________________~
o

2725

3534

Ooub'.-Pr.cision Flollting-Point Formst

~
71 70

Mantissa

Chara....ristic
6059

36

~
MantisSl
L
-_ _ _ _
_ _ ____
o

35

.An e,Kpianation of the sign bit, characteristic, and mantissa follows:
•

Sign - "he sign bit expresses the sign (5) of the numerical quantity represented by the
floating-point number.
If S - 0, the numerical quantity ;s positive (+).
If S -

•

1, the numerical quantity is negative (-).

Characteristic - The characteristic represents both the numerical value and the sign of the
exponent.
1.

Single-Precision Characteristic - The a-bit characteristic of a single-precision
floating-point number represents an exponent value in the range + 127 through -128. The
characteristic is formed by adding a bias of + 128 (200 8) to the exponent. Table 4-3 shows
the range of characteristic values and corresponding exponent values.

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SPERRY UNIVAC 1100/80 SyatetM

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Decimal Values
Characteristic

Octal Values

Unbiased
Exponent

-'

2.

Unbiased
Exponent

"

255

+127

377

+177

128

000

200

000

000

-128

000

-200

Double-Precision Characteristic - The 11-bit characteristic of a double-precision
floating-point number represents an exponent value in the range + 1023 through -1024.
The characteristic is formed by adding a bias of + 1024 (2000a) to the exponent. Table
4-4 shows the range of characteristic values and the corresponding exponent values.

,

Decimal Values

•

Characteristic

Octal Values

Characteristic

Unbiased
ExpQnent

Characteristic

Unbiased
Exponent

2047

+1023

3777

+1777

1024

0000

2000

0000

0000

-1024

0000

-2000

Mantissa - The mantissa portion of a floating-point number represents the fractional part of the
number. . In the instructions, the fractional part is normalized so that the absolute values
represented are greater than or equal to 1/2. but less than one. Zero cannot be represented
in this range: it is considered to be normalized as it stands. The binary point of a floating-point
number is assumed to lie between the last bit of the characteristic and the first bit of the
mantissa. The mantissa of a single-precision floating-point number contains 27 bits: for a
double-precision floating-point number. the mantissa contains eo bits. The mantissa need not
be normalized for all instructions.

I

8104 Rev.1

SPEI.RY UNIVAC 1100/80 Sytteml

~, Capability Processor and Storage Programmer Reference

~

UPDATI LIYIL

4.2.8. 1. Single-Precision Floating-Point Numbers
, A sinule-precielion floating-point number can be derived from a positive decimal number as follows:
Examlple:
t3iven nUlnber

I.

I.

Sign -

== + 12 10

+ =-

Characteristic

0

== exponent + bias
- 00 000 1002
-

+

10 000 000 2

10 000 100 2

1.

Mantissa

:.

The format for the floating-point number is as shown (sign included):

In

=- .110000 .... 000 2

Characteristic

Mantissa

10 000 100

1100 ...... 0
2128

4.2J~.2.

- 204800000000 8
o

Double-Precision Floating-Point Numbers

A double-prec:ision floating-point number can be derived from a positive decimal number following
the Siame ste~ts that were used for single-precision with these two exceptions:

•

A bias value of 2000 8 is added to the exponent to form the characteristic. For single-precision
the valuo is 200 8 ,

•

The mantissa is 60 bits instead of 27 bits.

4.2.B.3. Negative Floating-Point Numbers
A flctating-point number can be derived to represent a given negative number as follows:

•

Represent the given number as a positive floating-point number.

•

Form th4t ones complement of the entire positive floating-point number.

Exarnple:
Given number

=- -12,0

8804 Rev.1

SPERRY UNIVAC 1100/80 Syateml

UP-MJ •••

4x4 Capability Processor and Storage Programmer Reference

+ 12'0 (including

•

The single-precision floating-point number .for

sign) is 204 600 000 OOOs.

•

The single-precision floating-point number for -12,0 (including sign) is 573 177 777 777 s.

4.2.. 8.4. Residue
During single-precision floating-point Add or Add Negative, the bits shifted off the right end of the
register during alignment of the mantissas is not included in the addition but saved, becoming the
residue. After the addition is performed, the sum and the residue are each packed into floating-poi~t
format, the sum is stored, and the residue is stored if the floating-point residue store enable
designator (0 17) is one.
When the two 36-bit input operands for an Add or Add Negative instruction are transferred to the
arithmetic section, their characteristics are examined, and the mantissa of the input operand with the
smaller characteristic is right-shifted a number of bit positions equal to the difference between the
characteristics. The bits shifted out of the 36-bit arithmetic register are saved in an auxiliary ,·egister.
The portion of the mantissa saved in the auxiliary register is used to form the residue and is not
included in the algebraic addition. After completion of th" addition and any shifting necessary to
normalize the sum, the sum and the residue are packed into single-precision floating-point format
and transferred to two consecutive A-registers.

4.2.9. Normalized/Unnormalized Floating-Point Numbers
A floating-point number is normalized when the leftmost bit of the mantissa is not identical to the
sign bit or when all bits of the mantissa are identical to the sign bit. A floating-point number is not
normalized when aU bits of the mantissa are not sign bits and the leftmost- bit of the mantissa is
id,entical to· the sign bit.
AU floating-point operations produce a normalized result when the input operands are normalized.
The sums produced by Floating Add and Floating Add Negative instructions and the result produced
by the Load and Convert to Floating instruction are always normalized. regardless of whether or not
the input operands are normalized. When either or both input operands are not normalized, the result
obtained may be less accurate than if normalized input operands had been used.
Normalized input operands must be used for the Floating Multiply, Divide, Compress and Load, and
Expand and Load instructions. If normalized input operands are not used for these instructions, the
results are undefined.

4.2.10. Floating-Point Characteristic Overflow/Underflow
Floating-point characteristic overflow/underflow occurs when the characteristic does not lie in the
range represented in the number of bits allowed for the characteristic.
When any of the Floating-Point Add, Add Negative, Multiply, Divide, or Load and Convert instructions.
or the Compress and Load instruction are performed, overflow or underflow may occur.·

4.2. 1O. 1. Floating-Point Characteristic Overflow
Single-precision floating-point characteristic overflow occurs when the 8-bit characteristic of the
resultant most significant single-precision floating-point word represents a number greater than
3778 and the associated mantissa is not zero.

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

UP'DATI LEVEL

------------------------------------------~------~----------------~----------~---------

Doublle-precision floating-point characteristic overflow occurs when the l1-bit characteristic of the
resultant double-precision floating-point number "epresents a number greater than 37778 and the
associated mantissa is not zero.
Wher11 overflo,-" is detected, the action taken depends on the arithmetic exception interrupt designator
(020),. The characteristic overflow designator (022) is always set.

4.2.10.2. Floating-Point Characteristic Underflow
Singlct-precisi()n floating-point characteristic underflow occurs when the resultant floating-point
word represents a negative number and the associated mantissa of the result is not zero. This means
that the exponent of the result is Jess than -200 8 , thus the attached sign (positive - because absolute
value is used) c:hanges due to the borrow. If the characteristic of the residue (Floating Add, Floating
Add Negative), remainder (Floating Divide}, or the least significant single-precision word of the
product (Floating Multiply) represents a negative number, this fact by itself does not result in
undel"flow. Instead, the residue, remainder, or least significant word of the product is cleared to all
zero bits or set to all one bits (to reflect the appropriate sign).
Double-precision floating-point characteristic underflow occurs when the 11-bit characteristic of the
result: represents a negative number, i.e., the exponent of the result is ,less than 2000 8 , the mantissa
of thu reSUlt is not zero, and the double-precision underflow designator (05) is cleared.
Wher, underflc)w is detected, the characteristic underflow designator (021) is always set and the
action taken by the CPU depends on the state of 020.

4.2.10.3. Flc)ating-Point Divide Fault
For single- or double-precision floating-point division, a divide fault condition will be detected when
the mantissa I:)f the divisor is zero. The action taken depends on the floating-point zero format
selection desi~Jnator (08, for single-precision floating-point division only) and 020. The divide check
designator (023) is always set.

4.2. 11 1. Fixed-Point to Floating-Point Conversion
Conversion of a fixed-point number to floating-point number is performed in the arithmetic section.
The first input operand contains a characteristic (biased exponent) which defines the location of the
binary point fc)r the fixed-point number with respect to the standard position of the binary point for
a fl02lting-point number. The second input operand is the signed fixed-point number to be converted.
The (:onversion process consists of transferring the two operands to the arithmetic section, shifting
the 1fixed-point number, jf necessary, to position its bits as the mantissa for a normalized
floatiing-point number. Modify the characteristic to reflect the magnitude and direction of the
normlalizing shift. Pack the shifted fixed-point number (mantissa~ and the modified characteristic in
float.ing-point format. Load the packed results in a register (conversion to single-precision
floati!ng-point format) or into two consecutive registers (conversion to double-precision floating-point
form,at).
(

SPERRY UNIVAC 1100/80 SyttefM

4x4 Capability Processor and Storage Programmer Reference

4-10
UPDATI LIYIL

'AU

4.2.12. Floating-Point Addition
The process of adding two floating-point numbers consists of loading the numbers into the arithmetic
section, determining the difference between the characteristics of the two numbers, shifting (right)
the mantissa of the number having the smaller characteristic, adding the mantissas, combining the
results in floating-point format, and transferring the resulting floating-point numbers to GRS.
The input operands for floating-point addition need not be normalized numbers. For single-precision
addition, the sum (most significant word produced) is always a normalized number. The residue word
mayor may not be a normalized number. For double-precision addition, the sum is always a
nOITnatized number.

4.2. 13. Double-Precision Floating-Point Addition
The steps performed for double-precision floating-point addition are similar to those for the
single-precision addition with these six differences:
1.

Each of the two operands occupy two 3S-bit r&gisters in the arithmetic section.
single-precision addition both operands are contained in two 36-bit registers.

In

2.

The mantissa sum can contain a maximum of 60 bits in double-precision addition. instead of
27 bits as in single-precision addition.

3.

The bits that are shifted out of the right end of the 36-bit register when the operands are lined
up prior to addition are lost. There is no residue.

4.

Oouble-precision characteristic overflow occurs when the characteristic is greater than 37778
and the mantissa is not zero.

5.

Double-precision underflow occurs when the exponent is less than -2000 8 and the mantissa
is not zero. In single-preC'ision the value is -2008'

6.

The sum is stored in two consecutive registers, A and A+ 1. No residue is stored.

4.2. 14. Floating-Point Subtraction (Add Negative)
Floating-point subtraction (both single-precision and double-precjsion) uses the same routine as for
the Floating-point Add operation.

4 . 2. 15. Floating-Point Multiplication
The process of multiplying two floating-point numbers consists of loading normalized mput operands
into the arithmetic section, unpacking, multiplying the mantissas, adding the characteristics, packing
the rHults into floating-point format, and transferring the result to GRS. The results obtained for aU
cases in which either or both input operands are not normalized numbers are undefined.

4.2. 16. Floating-Point Division
The process of dividing one floating-point number by another consists of loading the normalized input
operands into the arithmetic section, unpacking, dividing one mantissa by the other, subtracting the
characteristics. packing the results into floating-point format. and transferring the result to GRS. The
results obtained for all cases in which either or both input operands are not normalized numbers are
undefined.

8804

I

Rev. 1

UfI..MUMI8i

SPERiRY UNIVAC 1100/80 Systems

~~ Capability

Processor and Storage Programmer Reference

4-11
UPDATE L.EVB.

'MI

4.2. 17. Floating-Point Zero
Ffoatif'llg-point zero can be defined as a floating-point number having all mantissa bits identical to
the si~~n bit.

4.2. 1 ~a. Byte Instructions
This cllass of im;tructions is designed to permit transference, translation, comparison, and arithmetic
computation of data in the form of predetermined bit patterns (e.g., half words, third words, Quarter
words, and sixth words) referred to as bytes.
There are a total of 15 distinct instructions that perform the various multiword (byte string) operations
noted above. "rhese instructions may be arranged under three functional groups:

1.

iIr,structions that involve byte transfers and manipulations between one storage location and
sinother;

2.

instructions that permit the mutual transference and manipulation of data among storage and
~rarious ccmtrol and arithmetic registers; and

3.

instructions that perform decimal arithmetic addition and subtraction operations.

Twelve of the byte instructions are performed in the arithmetic section. The remaining three
instructions (3=3,00 - Byte Move; 33,01 - Byte Move with Translate; and 33,07 - Edit) are performed
in the' main control section.

4.3. Control Section
4.3. 1. Instru1ction Word Format
During the running of a program in the 1100/80 Systems CPU, instructions are transferred from main
storalge locations to the control section of the CPU. The instructions are transferred from sequentially
addrEtSsed main storage locations until the sequence is broken by the program or interrupted by the
control section's reaction to some special condition or event. Each instruction is a coded directive
to th~B control section; the control section initiates a sequence of steps necessary to perform the
partic:ular operation prescribed by the instruction. The 36-bit instruction word, illustrated below, is
subd:ivided into seven fields.

35

30 29

2825

2221

18 17 18 15

o

whef~e:

f -

Function Code

j -

Op~9rand Qualifier, Character Addressing, Partial Control Register Address, or Minor
Furlction Code

8eo.. Rev.1

SPERRY UNIVAC '.100/80 Syttem8

4x4 Capability Processor and Storage Programmer Reference

a

1.~12

=- A-, X-, or R-register; Channel Number, Jump Key or Stop Keys Number; Minor Function
Code; Partial Control Register Address

x

= Index Register

h .. Index

R~gister

Incrementation Control

i-Indirect Addressing Control, Base Register Suppression Control, 24-Bit Indexing Control,
or Operand Basing Selector
u

=- Operand Address or Operand Base

4.3.2. Instruction Word Fields
Tho following paragraphs describe the manner in which the CPU's control section reacts to the
cor1tents of each of the seven fields of an instruction word.

4.3.2. 1. Use of the f-Field
The f-field is used to define the basic operation to be performed for all legal values of f less than
or equal to 70 8 (except 07 8, 33 8, and 37 8), When the f-field is 07 8, 33 8, 378 or greater than 70 8,
the f- and j-fields are combined to form a 1O-bit field used to define the basic operation. For 11
of these f, j combinations, the value in the a-field is used to define variations of the basic operation.
All function codes are defined in Section 5 and listed in Appendix C.

4.3.2.2. Description of the j-Field
When f is less than 70 8 (except 07 8, 33 8, and 3'1 8), the j-field is used as an operand qualifier or to
identify a J-reglster used in the character addressing mode. When f is equal to 70 8, the j-field is
used as part of a control register address. When f is 07 8, 33 8, 378 or greater than 70 s, the j-field
and the f-field are used to define a basic operation; in this instance, the j-field operates as a minor
function code.

4.3.2.2. 1. Use of the j-Field as an Operand Qualifier
When the f-field of an instruction contains a value in the range 0 1s through 678 (except 07 8, 33 s'
and 37 8) and the character addressing mode designator (04) =- 0, the j-field is used as an operand
qualifier which specifies the data transfer pattern to or from main storage, except as specified in
4.3.2.2:2.

The j-field can contain values ranging from 0 through 17 8 , Each value, except 48 through 7 8 ,
determines a specific data transfer pattern. Each of the j-field values 48 through 78 may specify either
of two different data transfer patterns. or character addressing with the choice dependent on the
contents of the quarter word mode selector (010) and 04 of the designator register (see S.2. 1). If
04 - 1. character addressing is specified and each of the j-field values 48 through 78 specify a
J-register as explained in 4.3.2.2.2. Figures 4-·1 ,and 4-2 illustrate all the possible data transfer
patterns which can be specified by the j-field when 04 - O.

I

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

~___ ~, Capability Processor and Storage Programmer Reference

..,

.

(Octal)

QU2lrter-Word
Designator*

c>

Storage Location

(I

o or

1

135

1

o or

1

I

~~

o or

1

1315

~I

o or

1

I

1,7
181
1,7

4-13
PAGE

UIIOATI LEVEL

Arithmetic Register

O~35

01

0~i!5-_-_-_;~~~-_~-_~~1'7

01

~i~~~~;~~~-_-_-_~131'7

01

0~i~~~~;~~~~-_~~~1'7

01

~;5---;i;~S---~81'7
1.: ___________

4 ..'.

0

5..·•

0

8 ..·•

0

7",.

0

4 ..·•

1

5 ..·•

1

8 ..·•

1

7 ..·•

136

I
I

~;;-----;e~;s-------9Is

1s1

I.:~----------------

1.:: _________________
0~;5- - - - - ;e;;,- - - - - - -91s

Is
1,7

135

1

11

o or 1

12

o or

1

13

o or

1

14

o or

1

1IS

o or

1

••

o or

1

17.,••

o or

1

*.
*..

1.: _______________
~;5-----;i;~'----·-~21,1

241
126

o or

•

1.:: _______________
~;;----;i;~,--·---~21,1

121

123

1

01

0~i!5~~~~~;~;_;~-_~~~~~1,1

1, 1

35

110

18"~

1s1

1.:: _________________
~;5------;.;;s-------918

91

1.:: _________________
~;5------;.~,-------918

271

I

Is
1,1
1,7121

81

01
01'
01
01
01
01
01

1.:: ___________________
o~;;------~;;;-------~

~;;------~;;;-------8~
1.:: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

1.:: ___________________
~;;------~~;;-------~
~;5-------;.;;s--------~
1.: ___________________

1231s1

~;;------~;~--------~
1.:: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

129241

1.: ___________________
~;;------;;~--------~

1315301

I
I

1,7

0~i!5~-_-J~~;~~~~~1,7

01

1,7

0~i!5~-_~;~;~~-_-_~~!1,7

01

Th. Quan.r-Word Mod. D••lgnltor bit (010) I. held in the d••ignltor regi.ter.

Chlract.r Addr....ng Mod. OHignator bit (04) wlllimpty J-fegister usege for instruction cod •• leas than f
07, 33, 37) for chlrlet.r or byte manipu'ation. D4 ov.rrid.. D1O.
If x _ 0, the h, i, and u are transferred. If x is not equet to zero, then u

+ (X)

is transferred.

-

70 (except

8104 "".1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

J
(Octal)

Quarter-Word
Designator·

¢>

. Arithmetic Register

0

Oor1

135

1

o or

1

2

o or

1

I
I

3

o or

1

Storage Location

0~3!5
117

0t--@-1

117

ot--@-136

1,7

0t--@-1

1,7

0t--@-13!5

4**

0

5**

0

111

0f--@-1

1**

0

111

0f--@-1

7**

0

111

of--@-135

4**

1

01
117

117

123

1

Is

7**

1

18

10

o or 1

11

Oor1

12

o or 1

15 0H!)--1

13

o or 1

15 oH!)--1

14

Oor1

15

15

Oor1

15 oH!)--135301

11

o or 1

No O.ta T... nsfer

17

Oor1

No O.ta Tr.nsfe,

*
**

The Quanet-Word Mode Oeaign.tor bit

(010) is hefd

115

0H!)--1

Ol---C!H

I
I
I

121

181

128

8**

I

01

241

18

,

I
1,1

,

oH!)--1

01

181

5**

115

I

181

o~
O~
O~
0~36

18

01

01

18

1,7

I

91

271

1
115

1,1
1,7121
123181
129241

&1

01

I

I
I
I
I

in the dHign.tor regilte,.

Cher8cter Addrenmg Mode OHignetor bit (0.) will imply .kegiltet uaege for in.tructton code. I... then f -

07. 33. 37) for ch.,.cter or byte m.nipuI8tion. 04 overTidH 010.

70 (except

880. Rev. 1

I SPE~rRY

UNIYAC 1100/80 Systems

_~_~ Capability Processor and Storage Programmer Reference

•

Operand qualification when f

==

4-15
PAGI

10s through 67 a (except 33 8 and 37 8)

1"hese instructions require the transfer of a full 36-bit word or a partial word to the arithmetic
election.

11.

If j

:!.

If j =1 0 1a through 15 s and U specifies a main storage location (U ~ 200 8 ), a partial word
is trllnsferred to the arithmetic section. In the arithmetic section, the partial word is
extended to a full 36-bit word, either by zero fill or by sign bit fill from the leftmost bit
position of the partial word, as illustrated in Figure 4-1.

:3.

If j :III 16 8 or 17 s, an la-bit partial word is transferred to the arithmetic section. Details
on the formation of this partie' word and its extension are given in 4.3.2.8.2.

:III

0a' the full 36-bit word addressed by U is transferred to the arithmetic section.

Wherl j =- 0 '8 through 15 s arid U specifies a control register (U ~ 177 8 ), the j-field is treated as
jf it clontained Os and the full 36-bit word is transferred from the control register to the arithmetic
sectic»".
•

IOperand qualification for store and block transfer instructions
'The full 36-bit word in the control register specified by the a-field (see 4.3.2.3.1 ) is transferred
to a nonaddressable register in the data shift/complement/store section (f==O '8 through 04 8
and 06"s)" The nonaddressable register, is cleared to 0 when f-05 s'
1.

If j •• Os' the full 36-bit word is transferred from the nonaddressable register to the location
(main storage or control register) specified by U.

2.

If j := 018 through 15 s and U specifies a main storage location (U ~ 20° 8 ), a partial word
is transferred from the least significant bit positions of the nonaddressable register to the
main storage location as shown in Figure 4-2. The contents of the remaining bit positions
of the main storage location are not changed. Partial word writes of a third word, quarter
word, or sixth word increase the storage cycle time to 200 nanoseconds.

3.

If j

:a:

16s or 17 8 , data is never transferred from the nonaddressable register to any storage
(main storage or control register).

Joc~.tion

When j - 018 through 15 a and U specifies a control register (U ~ 177 8 ), the j-fieJd is treated as
if it Icontainecl Os' and the full 36-bit word is transferred to the control register,

4.3.2.2.2. Ltse of the j-Field to Specify Character Addressing
WhEtn the f-field of an instruction contains a value in the range 01 through 678 (except 07 8 , 33 8 ,
and 37 8), 04 (the character addressing mode selector) - 1, and j - 4 8, 5 s, 6 s, or 7 8, the character
addt'essing mode is specified. When the character addressing mode is specified, a j-field value of
4, 5, 6, or 7 lspecifies JO, J 1, J2, or J3, respectively, in the GRS, as the register defining character
or byte size, the position of the byte within a word, and other details. When the GRS selection
designator (06) - 0, the J-register is selected from the set of four J-registers at GRS locations 106
through 11' 8 , When 06 - ',the J-register is selected from the set of four J-registers at GRS
locations 12~5 through 131 8, The format of a J-register word as used in the character addressing
mode is shown in Figure 4-3 and explained in Table 4-5.

........

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

4-18

4x4 Capability Processor and Storage Programmer Reference

2120

31S U 33 32 31

Bit Positions

J-Register
Field Identifier

35

I

•
•
•

E

0

I - 0 or h - 0 specifies no J-register mOdification*
I =- h - 1 specifies modification of Ow and Ob by Iw
and Ib, respectively.

Specifies the byte length, as follows:

•
32

3 2

The l-bit of the J-Register, in conjunction with the h-bit of the
instruction, specifies whether or not the contents of the Ow- and
Ob-fields are modified when the instruction is performed as
follows:

•

Bl

1817

Interpretation

•
34,33

Ow

Ib

Iw

,AGI

Bl

=-

0 specifies a 9-bit byte

Bl - 1 specifies an 18-bit byte
Bl - 2 specifies a 6-bit byte
Bl - 3 specifies a 12-bit byte

Specifies the bit used to extend the byte to 36 bits, if necessary,
as follows:

•
•

E - 0 specifies extension with 0 bits
E - 1 specifies extension with the high order bit of the
byte

31-21

Iw

Iw specifies the increment (or decrement) in words. Ib specifies
the increment (or decrement) in bytes. If I - 0, or h - 0 these
two values are ignored.

20-18

Ib

If I - 1 and h - 1, the· values in the Iw- and Ib-fields are added
to the values in the Ow- and Ob-fields, and the sums are stored
in the Ow- and Ob-fields after the initial values in these two fields
are used to form the absolute address of a word and select a byte
within the word.

I

8104 "",1

SPE:RRY UNIVAC 1100/80 Systems

~, Capability Processor and Storage Programmer Reference

Uf\ooMJMIIft

UIIDATI UYIL

Tabl. 4-6. Explanation of ./-R-rJist.r Fields for Characttlr Addressing Modtl (continutld)

Bit

I~ositions

J-Register
Field Identifier

Interpretation

17-3

Ow

The offset in words. This value is used to form the relative
address U and the absolute addresses 51 and SO.

2-0

Ob

The offset in bytes. This value is used to select a particular byte
within the selected word. The valid values of Ob for the possible
values of BL are shown in Figure 4-4. Other byte selections are
not defined.

... If I _ O. h _ V in the instruction word specifi.. inde. register modification when x , O.

BL == 0
(9-bit bytes)

Ob

Ob - 0

I

Ob ... 0

38

The Iidditions performed when I Ib -

1Ob -

3029

1

0

9 8

4
0

1Ob ... 21 Ob - 31 Ob - 41 Ob = 51

2423

2' 23

12 t 1

18 17

Ob

Ob - 0

BL - 3
(1 2-bit bytes)

+

= 6

18 17

35

lOb

Ob

Ob -

38

=

=4

Ob - 0

BL - 1
( 1 8-bit bytes)

BL
2
(6-bit bytes)

Ob
18 17

2728

38

=2

=-

2

Ob
12 1 t

and the h-bit of the instruction -

0

IS 5

==

4
0

1 are symbolized by

Ob

and
IOw+lw-Ow
The ,,'alues in the Ow- and Ob-fields are always treated as positive values in these additions. The
high .lrder bit in the Iw-field (bit 31 of the specified J-register) is applied as the sign of both the 'wand Ib-fields. If this sign is a zero bit, forward modification of Ow/Ob is performed. Forward
modi1fication permits incrementing the Ow- or Ob-field value (or both) to produce new Ow- and

........

8804 Mev.1

SPERRY UNIVAC 1100/80 Sy8tem8

4x4 Capability Processor and Storage Programmer Reference

'

4-18
UPOATI LIYIL

"AGE

Ob-field values to select any desired byte in lower order bit positions of the same word or select any
desired byte in any word having a higher address. If the sign bit applied to the Iw- and Ib-fields is
a lOne bit. backward modification of Ow/Ob is performed. Backward modification permits
decrementing the Ow- and Ob-field value (or both) to produce new Ow- and Ob-field values to select
any desired byte in higher order bit position of the same word or select any desJred byte in any word
having a ·lower address.
The result produced for the addition Ob + Ib ... Ob is dependent on the two values used as inputs.
the sign in the Iw-field, and tt,e value in the BL- field. as shown in Tables 4-6 through 4-9. The valid
combinations of Ob and Ib are shown in these tables. The result produced when any other
combination is used is undefined.
Tba addition Ow + Iw ... Ow is performed in an 18-bit ones complement subtractive adder after
extending the 15-bit Ow-field to 18 bits with three high order zero bits and extending the 11-bit
Iw-field to 18 bits with seven high order bits identical to the sign bit in the Iw-field. A carry-or borrow
generated in the addition Ob + Ib ... Ob also enters the Ow + Iw ... Ow addition. The sum is stored
in the Ow-field of the specified J-register after the initial value in the Ow-field is used to form the
relative and absolute addresses needed for the instruction.
If the value in the Ow-field is modified by adding a positive Iw value to produce an 18-bit sum greater
than 0777778 or by adding a negative Iw value to produce a negative 18-bit sum, the 15-bit value
stored in Ow is undefined. Producing a negative 18-bit sum is a common programming error which
can be avoided by choosing an artificially high-initial value for Ow and reducing the initial value of
Xm by a like amount.
If t.he value U produced by the addition u + Xm + Ow (see 4.3.2.S) for an instruction which specifies
the character addressing mode is less than 200 a, a register in the GRS is not referenced. Instead.
thll values 51 and SO are produced, and if U passes the storage limits test, an attempt is made to
reference main storage.

0

0

o·

1
2
3
0
1
2
3

2
4
6
.7
5
3
1

0
2
4
6

Number of
Bytes
Forward or
Backward

Forward
Modification
(J31 - 0)
Backward
Modification
(J 31 ill: 1)

For valid Ob/lb input combinations
C - Carry (+ 1) to Ow
B - Borrow (-1) to Ow

+ Iw
+

Valid Input Ob Values
4
2
6

Valid
Ib
Value

BL - 0 (9-8it
Bytes)

... Ow addition

Iw ... Ow addition

0
6R
4a
2R

4

4
6

2

6

Oc

Oc

2~

2
0
68
4R

4

6

Oc
2c
4c

2

6
4

6R

2
0

a

sea.. Rev.1

SPERRY UNIVAC 1100/80 S.,.-tems

UI4tUMIIII

4x4 Capability Processor and Storage Programmer Reference

4-19
UI'OATI LIVIL

III4GI

r.bl.4-7. Output Ob Valun Productld Whtln 8L - 1

BL -

1 (18-Bit Bytes)

Forward
Modification (J~ 1
Backward
Modification (J':I1

For

Vali~

BL - 2 (6-Uit
Bytes)

Forward
M,odification
(.J 31 - 0)

nackward
Modification
(.J31 - 1)

0)

==

1)

Valid
Ib
Value

0

0

1
0
1

4

0
4

7
3

4R

4
Or.
4
0

0

Ob/lb Input Combinations

C - Carry
B -

==

Valid Input Ob Values
4
0

Number of
Bytes
Forward or
Backward

(+ 1) to

Ow

Borrow (-1) to Ow

+

Iw -

+ Iw

Ow addition
-

Ow addition

Number of
'Bytes
Forward or
Backward
0
1
2

Valid Ib
Value

0

0
1

3
4

3
4

0
1
2
3
4

5

5

5

0
1
2

7

0

6
5

5g

2

Valid Input Ob Values
1
4
2
3

1
2

2

3

4

5

3

4

5
Or.
1r.

Or.

3

4

5

4

5

5
Or.

Or.

Or.
1r.

4R

5A

1t"
2
1
0

3A

4

4
3

5

2

'9

4R
3R
2R

5.
4"
3R

3

For villid Ob/lb combinations
C - Carry (+ 1) to Ow Iw'" Ow addition
B - ISorrow (-1) to Ow Iw ... Ow addition

2R

1
0

5

2c
3t"
4

1~

2c
3c
4~

2t"

2
1

3

0
59

1
0

2

4"

5A

0

3

2

5
4
31

8804 Rev.1
\MLNI . . .

SPERRY UNIVAC 1100/80 System.

4-20

4x4 Capability Processor and Storage Programmer Reference

BL

=- 3 (12-Bit
Bytes)

Forward
Modification
(J~t .. 0)
Backward
Modification
(J~, .. 1)

Valid Input Ob Values
4
2
0

Number of
Bytes
Forward or
Backward

Valid Ib
Value

0

0

0

1
2

2
4
7
5
3

2
4

0
1
2

'AGE

0

2

49
2ft

0

4
Oc
2c
4
2

4ft

0

2
4
O~

For valid Ob/lb combinations
C

:II

Carry (+ 1) to Ow Iw -

B

==

Borrow (-1) to Ow lw -

Ow addition

Ow addition

4.:3.2.2.3. Use of j-Field as Partial Control Register Address
When f =- 708 , the most significant bit of the j-field is ignored by the hardware, and the three
low-order bits are combined with the contents of the 'a-field to form a 7-bit control register address.

4.3.2.2.4. Use of j-Field as Minor Function Code
When f == 0.7 8 , 33 a,· 37 a' or 71a through 76 a, the value in the j-field is a minor function code
delsignator. An explanation of the details of each of these instructions is given in Section 5. They
are summarized in Appendix C.

4.3.2.3. Uses of the a-Field
The contents of the &-field of an instruction word has a number of uses. The exact use is dependent
on the instruction being performed and, in many cases, on the contents of the designator register.

4,,3.2.3. 1. Use of the a-Field to Reference an A-Register
Fc)r most of the instructions, the value in the a-field references one of the A-f'egisters. When the A-,
X··, and R-register set selector, 06, is equal to 0, each value in the range 0 through 17 a in the a-field
retferences one of the user A-f'egisters in the range of control register addresses 14a through 33 a,
retspectively. When 06 - 1, each value in the range 0 through 17 a in the &-field references one
of the Executive A-registers in the range of control register addresses 154 a through 173 a,
rEtspectively. In some instructions, the value in the a-field references two or three A-registers. When
two or three A-registers are referenced, the value in the a-field explicitly references register Aa, and
innplicitly references registers Aa+ 1 and Aa+2.
'Tine unassigned control registers at addresses 34 a, 35 a• 174 8 , and 175 a can be used as extensions
01f the two sets of 16 A-f'egisters. For example, when a - 1 7 a and the instruction requires referencing
three A-registers (Aa, Aa + 1, and Aa + 2) then:

8604 Rev.1

I

SPERRY UNIVAC 1100/80 Systemt

.

_~~ Capability Processor and Storage Programmer Reference

\JINfUMUJt

•

Ilf 06 ::II 0, the last user A-register (address 33 8) is referenced for Aa, the first user unassigned
,control register at address 348 is referenced for Aa+ 1, and address 35 8 is referenced for Aa + 2.

•

a 06

::II 1, the last Executive A-register at address 173
8 is referenced for Aa, the following
'Executive unassigned control register at address 1748 is referenced for Aa + 1, and address
175 8 is referenced for Aa + 2.

4.3.~~.3.2.

Use of the a-Field to Reference an X-Register

For certain ins,tructions, the value in the a-field references one of the X-registers. When 06 ::II 0,
each value in the range of 018 through 178 in the a-field references one of the user X-registers in
the nlnge of c()ntrof register addresses 018 through 17 8 , respectively; if a ::II 0, the user nonindexing
X-re~Jister at control register address 0 is referenced. When 06 == 1, each value in the range of 018
through 178 in the a-field references one of the Executive X-registers in the range of control register
addrEtsses 1418 through 157 8, respectively; if a ::II 0, the Executive nonindexing X-register at control
regis1ter address 140 8 is referenced.
4.3.:~.3.3.

Use of the a-Field to Reference an R-Register

For certain instructions. the value in the a-field references one of the R-registers. When 06 - 0,
each value in the range of 0 through 178 in the a-field references one of the user R-registers at control
register addresses 1008 through 117 8 , respectively. When 06 == 1. each value in the range of 0
thro\Jlgh 178 i., the a-field references one of the Executive R-registers at control register addresses
120~1 through 137 8 , respectively.

4.3.:!.3.4. Use of the a-Field to Reference a Jump Key
For a Jump Kety i"struction, each value in the range of 0 18 through 178 in the a-field references one
of this 15 select jump control circuits in the CPU. These circuits may be individually set and cleared
via switches on the operator/maintenance panel on the system transition unit (STU).

4.3.:2.3.5. Use of the a-Field to Reference Halt Keys
For ~I Halt Keys and Jump instruction, each of the four bit positions in the a-field references one of
the four selec:t stop control circuits in the CPU. These circwt5 may be individuaUy set and cleared
via switches ()n the STU.

4.3.2.3.6. Use of the a-Field as Minor Function Code
The value in the a-field specifies a particular variation of the basic operation initiated by the f, j
combination of the following instructions:
•

load Brt!akpoint Register/Store Jump Stack

•

load Pr()cessor State Register

•

Initiate Iinterprocessor Interrupt/Enable Second Day Clock/Enable Day Clock/Disable Day Clock

•

Test and Set/Test and Set and Skip/Test and Clear and Skip

a804 Rev. 1

-

UNAlMIIIt

~

SPERRY UNIVAC 11oo/aO Systems

4-22

4x4 Capability Processor and Storage Programmer Reference

'AGI
----~------

•

Jump Overflow/Jump Floating Underflow/Jump Floating Overflow/Jump Divide Fault

•

Jump No Overflow/Jump No Floating Underflow/Jump No Floating Overflow/Jump No Divide
Fault

4.3.2.4. Use of the j- and a-Fields to Specify GRS Control Register Address
For' the Jump on Greater and Decrement instruction, the values in the j-field and a-field combine to
form a 7-bit address (the leftmost bit of the j-field is ignored). The 7-bit address specifies which
On4!' of the 128 addressable GRS control registers is to be used as the counter for the instruction.

4.:t2.S. Use of the x-Field
An indexing operation which utilizes a ones complement subtractive adder occurs for every
ins,truction. If the A-, X-, and R-register set selector, 06, is equal to 0, each x-field value in the range
018 through 178 references one of the user X-registers at control register addresses 018 through
17 8, respectively. If 06
1, each x-field value in the range 018 through 178 references one of the
Executive X-registers at control register addresses 1418 through 157 8, respectively. When the value
in 'the x-field is not zero, the value in the Xm-field of the X-register specified by the x-field is added
to the extended contents of the u-field to form the relative operand address or an operand. This
indexing operation is symbolized by the notation: u + Xm =- U except for instructions which specify
the character addressing mode (see 4.3.2.2.2) and for most byte instructions (see 4.2.18). In these
U. Xm is an 18-bit field unless 24-bit indexing
caises it is symbolized by the notation u + Xm + Ow
is specified.

=

=-

When the value in the x-field is zero, no index register is referenced. An indexing operation, however,
does occur. It consists of adding an 18-bit half word of all zero bits to the extended u-field value
to form the relative operand address or operand. This indexing operation is symbolized by the
no,tation: u + 0
U or u + 0 + Ow
U.

=

=

An indexing operation never produces a U value consisting of all one bits. This applies when U is
16 8) or with sign bits (j
17 8)
a relative address and also when U is extended with zero bits (j
fall' use as an immediate operand.

=

Ex,ample:
If j

16 or 17 8, u

1.

=- 000001 8, and Xm =- 777776 a
then

u

+

Xm

= U = 0000018 + 777776 a

:II

000000 8

Example:
If f

==

10-67 a (except 33 and 37 a), j

=-

16 or 178

and
h

= i = 0, u = 177777 8, and Xm = 600000 8,
then

u

+

Xm =- U

= 1777778 + 600000 8 .r 000000 8

=

8804 Rev.'
UJJt.oNUM8IR

I SPEI~RY

UNIVAC 1100/80 Systems

~ Capability Processor and Storage Programmer Reference·

4-23

UfIOATI LEVEL

PAGE

Example:
If f

== 1()..·67 8 (except 33 and 37 8),

j

= 16 or

17 8 ,

and
h

== i == 'I, u

= 177777 8 , and x ==

0,

then
h, i, u

+

~)

-

U

==

7777778

==

0

==

000000 8

4.3.2.6. Use of the h-Field
If the x-field of an instruction contains a nonzero value, the h-bit determines whether or not the
contelnts of the X-register specified by the x-field of the instruction or the Ow- and Ob-fields of an
instrulction specifying the character addressing mode are modified.
After the indexing operation is complete, if h == 1, and x t 0 for an instruction which does not specify
the character addressing mode, or an instruction which specifies the character addressing mode and
a J-register containing I == 0 (see 4.3.2.2.2), the contents of the Xi-field of the specified X-register
is addled to thn contents of the Xm-field of the same register, and the sum is stored back in the
Xm-fi70-60 1 -

DFU

76/14

A 10-0' zero fill;

(U,U+ 1)59-38 - A+ '23-0' sign fill:
(U,U+ 1)35-0 - A+2
1rhe double-precision floating-point number from locations U and U + 1 is transferred to the
arithmetic section and unpacked. The absolute value of the biased characteristic of the input operand
is transferred to bits 10 through 0 of Aa; bits 35 through 11 of Aa are filled with 0 bits. The leftmost
24 bits of the mantissa, (U)23-0' are transferred to bits 23 through 0 of Aa+ 1; bits 35 through 24
()f Aa+ 1 are filled with bits identical to the sign of the floating-point number in locations U and U+ 1.
-rhe rightmost 36 bits of the mantissas (U+ 1) are transferred to Aa+2.
1.

No attempt is made to normalize the operand.

8604 Rev.1
Ult-HUMIU

I

SPER:AY UNIVAC 1100/80 Systems

~ Capability Processor and Storage Programmer Reference

5.5.1 '1. Load and Convert to Floating (lJ)35 -

A+ 135 ; [normalized (U)]26-0 -

LCF

"AGE

76,05

A+ 12 6-0;

if (U)35 . == 0: (Ah-O :: normalizing count if (U)35 -

5-17
UflDATI L£VIt.

1: ones complement of [(A)7-O

A+ 1 34- 27 ;
:!:

normalizing count] -

A+ 134-27

The fb:ed-point number from location U is sent to the arithmetic section where it is shifted right or
left, aSi required, .to normalize it. The normalizing shift count is added to the characteristic from the
rightmost eight bits of Aa if a normalizing right-shift is required. It is subtracted from the
charac:teristic if a normalizing left-shift is required. The adjusted characteristic (complemented if U
is negiative) is J)acked with the normalized value from U to form a single-precision floating-point
numbElr. The packed result is stored in Aa+ 1. The contents of Aa remain unchanged.
1.

A Floating,-Point Characteristic Overflow/Underflow interrupt may occur.

2.

The 28 lef1most bits from Aa are ignored: (Aah-O must be prebiased.

3.

If the resultant mantissa is zero, the following applies:

== 0, the result stored in Aa is

a"

If the floating-point zero format selection designator (08)
+0.

b.

If 08 == 1, and the resultant characteristic is in the range 000 through 377, the
characteristic is packed with the zero mantissa and stored in Aa.

c.

If 08 - 1, and the resultant characteristic is a negative number,
depending on the sign of the input operand.

5.5.1 :~. Double Load and Convert to Floating (lJ)35 -

A+ 13S ; [normalized (U,U+ 1)]59-0 -

if (U)35 .. 0: (Aho-o :!: normalizing count if (U)35 -

DFP, DLCF

to

is stored in Aa.

76,15

A+ 123-0 and A+2;
A+ 134-24;

1: ones complement of [(A),o-o :!: normaHzing count] -

A+ 134-24

The dCtuble-precision fixed-point number from locations U and U + 1 is sent to the arithmetic section
where it is shifted right or left, if necessary. to normalize it. The normalizing shift count is added to
the characteristic from the rightmost 11 bits of Aa if a normalizing right-shift is required. It is
subtracted frorr, the characteristic if a normalizing left-shift is required. The adjusted characteristic
(compllemented if U is negative) is packed with the normalized value from U and U + 1 to form a
doublEt-precision floating-point number, and the packed result is stored in Aa+ 1 and Aa+2. The
conterats of Aa remain unchanged.
1.

A~

2.

The 25 leftmost bits from Aa are ignored; (Aah 0-0 must be prebiased.

3.

If: the 72-bit input operand from U and U+ 1 is :0, the result stored is +0, regardless of the
sign of th4t 72-bit operand.

4.

If: the adjusted characteristic represents a negative number when the arithmetic exception
interrupt designator (020) and the double-precision underflow designator (05) - 1. a

Floating-Point Characteristic Overflow/Underflow interrupt may occur.

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

~

5-18
UPOATI LIVIL

ftAGI

Floating-Point Characteristic Underflow interrupt does not occur. Instead +0, regardless of the
sign of the 72-bit operand, is stored.

5.5.13. Floating Expand and Load If (U)36 == 0: (U)35-27

+

1600 s

if (U)35 .. 1: (U)36-27 - 1600 s
(U)28-3 (U)2-o -

-

-

FEL

76,16

A 35- 24;
A 3S - 24 ;

A 23-0;
A+ 135- 33 ;

(Ubs - A+ 132-0
The single-precision floating-point input operand from location U is transferred to the arithmetic
section. The three fields of the operand are expanded to form a double-precision floating-point
number as follows:
•

I'
It

The sign bit is stored in bits 71 and 32 through O.
The a-bit characteristic, which includes a bias of 200 8, is modified to an 11-bit characteristic.
which includes a bias of 2000 s, and is stored in bits 70 through 60.
The 27-bit mantissa is stored in bits 59 through 33.

T'he result is transferred to Aa and Aa+ 1.
1.

If the operand is not in the normalized single-precision floating-point format, the result stored
is undefined. The following notes apply only if the input operand is a normalized number.

2.

If the mantissa of the input operand is :0, the result stored in Aa and Aa+ 1 is +0, regardless
of the sign of the operand.

3.

A Floating-Point Characteristic Overflow/Underflow interrupt will not occur as a result of this
instruction.

!i.5.14. Floating Compress and Load If (U)38 .. 0: (U)35-24 - 16008 if (U)35

=- 1: (U)35-24

+

16008 -

FCL

76,17

A 36- 27 ;
A 3 5-27; .

(U)23-0 - A 2 fS-3;
(U + 1)35-33 -

A 2-o

The double-precision floating-point operand from locations U and U + 1 is transferred to the
2arithmetic section. The three fields of the operand are compressed to form a single-precision
noating-point number as follows:

8804 Rev. 1

I

SPI:RRY UNIVAC 1100/80 Systems

UI'-MUMIU_~4

5-19

Capability Processor and Storage Programmer Reference

~AGE

•

The sign bit is stored in bit 35.

•

The 11-bit characteristic, which includes a bias of 20008' is modified to an a-bit characteristic,
which inc:ludes a bias of 200 s• and is stored in bits 34 through 27.

•

The 27 htftmost bits of the mantissa (bits 23 through a from location U, and bits 35 through
33 from location U+ 1) are stored in bits 26 through O.

The result is transferred to Aa.
1.

The following notes apply only if the operand is a normalized number.

2.

If the arithmetic exception interrupt designator (020) =- 1, a Floating-Point Characteristic
Overflow interrupt occurs if the characteristic of the operand is greater than + 127, and a
Floating-Point Characteristic Underflow interrupt occurs if the characteristic of the operand is
less than -128. The characteristic underflow designator (021) is set when an underflow
condition is detected, and the characteristic overflow designator (022) is set when an' overflow
condition is detected.

3.

'The contl"nts of U + 132-0 is ignored.

4.

If the operand is not a normalized number or is equal to :!: 0, the result stored in Aa is +0,
regardless of the characteristic of the input operand.

5.5. 15. Magnitude of Characteristic Difference to Upper -

II

(AI13!-27 -

I (UI136-27

I-

A+ 18-0; zeros -

MCDU

76,06

A+ 13!-9

The albsolute value of the characteristic of the single-precision floating-point number from location
U is !tubtracted from the absolute value of the characteristic of the single-precision floating-point
number from As.
The 81bsolute ,-'alue of the 9-bit difference is stored in bits a through 0 of Aa+ 1. Bits 35 through
9 of Aa+ 1 arn zero filled. The contents of Aa is not changed.
1.

'The mantissas from location U and from As are ignored.

5.5.16. Char'acteristic
1 (A) 135-21

Differenc~

-I (U) 138-27

-

to Upper -

CDU

76,07

A+ 1~ sign bits to A+ 138-9

The albsolute value of the characteristic of the single-preciSion floating-point number from location
U is nubtracted from the absolute value of the characteristic of the single-precision floating-point
number from Aa. The 9-bit signed difference is stored in bits 8 through 0 of Aa+ 1. Bits 35 through
9 of ~,a+ 1 are filled with bits identical to the sign of the difference. The contents of As is not changed.
1.

'The mantissas from location U and from Aa are ignored.

8604 Aft.1

SPeRRY UNIVAC 1100/80 Systems

UP-HUMIEII

4x4 Capability Processor and Storage Programmer Reference

5-20
UPDATI LEVEL

'AGE

5.t;. Search and Masked-Search Instructions
Th,ere are six search instructions, each of which compares the contents of either one or two
A-registers with the contents of storage locations or control registers. There are eight masked-search
instructions, each of which compares contents of predefined bit positions of either one or two
A-registers with the contents of the corresponding bit positions of storage locations or control
registers.
These are all multistage instructions. The various stages required to perform these instructions are
as follows:
•

An initial stage

•

Repeated test stages (18 , repeat count , 777776 8)

•

Termination stage

If indirect addressing is specified, it proceeds prior to initiation of the first test stage.
The initial stage prepares the control section and the arithmetic section for the test stages. The
following steps are performed during the initial stage:
•

The contents of the repeat count register (R 1) is read from GRS.

•

The content~ of the specified A-registers are transferred to the arithmetic section.

•

The contents of the mask register (R2) is transferred to the arithmetic section for a
masked-search instruction.

These steps are performed only during the initial stage and are not repeated during the test stages.
The rightmost 18 bit positions of R1 contain the repeat count; that is, the maximum number of test
stages to be performed. R1 must be loaded with the desired repeat count prior to initiating a search
or masked-search instruction. If the initial repeat count is !: 0, the R1 location is written to +0 and
proceeds to the next instruction. If the initial repeat count is not:: 0, the search instruction continues.
Ouring each test stage. the value U is formed in the index subsection. For the search instructions,
an input operand is transferred to the arithmetic section under j-field control. The inputs to the test
process are the values obtained using the effective U address and the A-register or registers specified
by the instruction.
For the masked-search instructions, the contents of the j-field is a minor function code. The inputs
to the test process are:
•

the logical product of the mask from R2 and the input operand addressed by U and,

•

the logical products of the ,!,ask and. the specified A-registers.

Ealch bit of the logica' product is the logical product of the contents of corresponding bit positions
of the two words. The logical product of two bits gives the same results as the Logical ~.
The search and masked-search instructions include algebraic and alphanumeric comparisons.
During an algebraic comparison. the leftmost bit of each of the 36-bit values is considered to be a
sign bit; a positive number is always recognized as being greater than a negative number. During
an alphanumeric comparison. the leftmost bit of each of the 36-bit values is considered to be a
ntJlmeric bit rather than a sign bit.

8604 Rev.1
U,.......,MIER

I

SPERRY UNIVAC 1100/80 Systems

~ Capability Processor and Storage Programmer Reference

UPDATI LIVEL

5-21
'AGE

For each test process, the repeat count is decreased by one. If the test process shows that the
speci'fied conditions are met, the termination stage is initiated and the next instruction is skipped.
If th'e specified conditions are not met and the repeat count is not zero, another test stage is normally
initiated. If th~~ repeat count is zero, the search instruction is terminated. It should be noted that if
Xn - 0, Xi (the increment portion of the X-register) = 0, or h
0, the value of U will not change.

=

Interrupts are detected during the test stages if the repeat count is greater than 1 and the instruction
does not indicnte a skip condition. The instruction terminates and stores the remaining repeat count
in R1. The correct return address is captured.
If the search or' masked-search instruction is entered by means of an Execute instruction, the h-field
of the Execute instruction should be zero (that is, no incrementation) so that when the program returns
to thet Execute instruction after an interrupt, the effective U address will again lead to the search or
maskiltd-search instruction.
If the search ()r masked-search instruction specifies indirect aqdressing (i-field ,- 1), the h-field
should be zero to enable the program to return to the same effective U address and resume the search
or mSlsked search after an interrupt.
For e(~uality searches (SE, SNE, MSE, MSNE), +0 does not equal-O; for arithmetic searches (SLE, SG,
SW, :$NW, MSLE, MSE, MSW, MSNW), +0 is greater than -0; for alphanumeric searches (MASL,
MAS G), -0 is greater than +0.
When a search or masked-search is resumed after an interrupt, the initial stage is again performed
to prf!pare the control section for the remaining test stages and to transfer the contents of the
specilfied A-renister to the arithmetic section for the comparisons performed in the test stages. When
h -, 11 (that is, index register incrementation is specified), if the a- and x-fields reference the same
contrt::»1 registel~, the contents of that register will have been altered by the index incrementation which
occurred before the search or masked search was interrupted. As a result, when the search or masked
search is resumed, the value referenced by the a-field to be used in the test stages is no longer the
original test value used before the interrupt occurred. Therefore, when h
1, the a-field and x-field
should not specify the same control register so that the search or masked-search instruction can be
resun'ed in tho event of an interrupt.

=

5.6. 1. Search Equal -

SE

62

:Skip NI if (U) - (A), else repeat
During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subSEtction, the contents of Aa is transferred to the arithmetic section, and the P-register is
incremented.
If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
count is decrellsed and the contents of U is transferred to the arithmetic section under j-field control.
This "alue frorn U is compared with the value from Aa and:
•

.•
•

=

'If (U)
(Aa), the termination stage is initiated. This stage stores the remnant repeat count and
iincrements the P-register.(Skip to NL)

Ilf (U)

= (Aa~ and

the repeat count is not zero, another test stage is initiated.

Ilf (U) =(A •• ) and the repeat count is zero, the termination stage stores zero as the remnant repeat
Icount and the P-register is not incremented.

..,...,.,...

ae04 Rev.1

SPERRY UNIVAC 1100/80 Syatema

5-22

4x4 Capability Processor and Storage Programmer Reference

1.

'AGI

+0 is not equal to -0.

5.6.2. Search Not Equal -

SNE

63

Skip NI if (U) -: (A), else repeat
During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subsection, the contents of Aa is transferred to the arithmetic section, and the P-register is
inlcremented.
If the initial repeat count is zero, the next instruction (Nt) is initiated.
If the initial repeat count is not zero. the first test stage is initiated. During each test stage, the repeat
count is decreased and the contents of U is transferred to the arithmetic section under j-field ·control.
The value from U is compared with the value from Aa and:
•

If (U) -: (Aa). the termination stage is initiated. The termination stage stores the remnant repeat
count and increments the P-register. (Skip Nt.)

•

If (U) - (Aa) and the repeat count is not zero. another test stage is initiated.

•

If (U) =- (Aa) and the repeat count is zero, the termination stage is initiated. The termination stage
stores zero as the remnant repeat count and the P-register is not incremented.

1.

+0 is not equal to -0.

5.6.3. Search Less Than or Equal/Search Not Greater -

SLE,SNG

64

Skip NI if (U) ~ (A), else repeat
During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subsection. the contents of Aa transferred to the arithmetic section. and the P-register is incremented.
If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
cctunt is decreased and the contents of U is transferred to the arithmetic section under j-field control.
nte value from U is compared with the value from Aa and:
•

If (U) ~ (Aa); the termination stage is initiated. The termination stage stores the remnant repeat
count and increments the P-register. (Skip Nt)

•

If (U)

•

If (U) > (Aa) and the repeat count is zero, the termination stage is initiated. The termination stage
stores zero as the remnant repeat count and the P-register is not incremented.

1.

+0 is greater than -0.

>

(Aa) and the repeat count is not zero, another test stage is initiated.

-------~

peRRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

5.6.4. Search Greater :Skip NI if: (U)

>

SG

5-23
I'AGI

65

(A), else repeat

During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subSEtction, the contents of Aa is transferred to the arithmetic section, and the P-register is
incremented.
If the initial repeat count is zero, the next instruction (NI) is initiated.

If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
count is decree.sed and the contents of U is transferred to the arithmetic section under j-field control.
The \/'alue from, U is compared with the value from Aa and:
•

Ilf (U) > (Aa), the termination stage is initiated. The termination stage stores the remnant repeat
Icount and increments the P-register. (Skip NI.)

•

Ilf (U) ~ (Aa) and the repeat count is not zero, another test stage is initiated.

•

ilf (U) ~ (Aa) and the repeat count is zero, the termination stage is initiated. The termination
:stage stores zero as the remnant repeat count and the P-register is not incremented.

1.

+0 is grt!ater. than -0.

5.S.Ei. Search Within Range Skip NI if (A)

<

SW

66

(U) ~ (A+ 1), else repeat

During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subs.tction, tht! contents of Aa and Aa+ 1 are transferred to the arithmetic section, and the P-register
is inc:remented.
If thel initial repeat count is zero, the next instruction (NI) is initiated.

If the initial re"eat count is not zero, the first test stage is initiated. During each test stage, the repeat
coun't is decreased and the contents of U is transferred to the arithmetic section under j-field control.
The "alue frorn U is compared with the value from Aa and:
•

If (U) > (J~a) and (U) , (Aa+ 1), the termination stage is initiated. The termination stage stores
the remnant repeat count and increments the P-register. (Skip Nt.)

•

If (U) ~ (As) or (U)

•

If (U) , (Aa) or (U) > (Aa+ 1), and the repeat count is zero, the termination stage is initiated.
The termination stage stores zero as the remnant repeat count and the P-register is not
incremented.

1.

+0 is greater than -0.

2.

Normallv', (As) < (Aa+ 1). However, if (Aa) ~ (Aa+ 1), there is no value from U which can satisfy
the conditions (Aa) < (U) ~ (Aa + 1).

>

(Aa + 1), and the repeat count is not zero, another test stage is initiated.

8804 Rev.1

SPERRY UNIVAC 1100/80 System,

.

4x4 Capability Processor and Storage Programmer Reference

IJII.NUMIIR

5 . 6.6. Search Not Within Range Skip NI if (U) ~ (A) or (U)

>

SNW

67

(A+ 1), else repeat

During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subsection. the contents of Aa and Aa + 1 are transferred to the arithmetic section, and the P-register
is incremented.
If the initial repeat count is zero. the next instruction (NI) is initiated.
If the initial repeat count is not zero, the firsttest stage is initiated. During each test stage. the repeat
count is decreased and the contents of U is transferred to the arithmetic section under j-field control.
The value from U is compared with the value from Aa and:
•

If (U) ~ (Aa) or (U) > (Aa+ 1), the termination stage is initiated. The termination stage stores
the remnant repeat count and increments the P-register. (Skip NI.)

•

If (U}

•

If (U) > (Aa) and (U) ~ (Aa+ 1), and the repeat count is zero, the termination stage is initiated.
The termination stage stores zero as the remnant repeat count and the P-register is not
incremented.

1.

Normally, (Aa) < (Aa+ 1). If, however, (Aa) ~ (Aa+ 1), there is no value from U which will not
satisfy the conditions (U) ~ (Aa) or (U) > (Aa + 1).

2.

+0 is greater than -0.

> (Aa) and (U)

~ (Aa+ 1), and the repeat count is not zero, another test stage is initiated.

5.6.7. Masked Search Equal -

MSE

71,00

Skip NI if (U) ~ (R2) == (A) ~ (R2), else repeat
During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
siubsection, the contents of Aa and R2 are transferred to the arithmetic section, the logical product
of the values from Aa and R2 is formed, and the P-register is incremented.
If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
(R2) is
count is decreased and the contents of U is transferred to the arithmetic section. (U)
(R2) and:
compared to (Aa)

g

g

g

..

If (U) ~ (R2) - (Aa)
(R2), the termination stage is initiated. This stage stores the remnant
repeat count and increments the P-register (skip NI).

..

If (U)

..

If (U) ~ (R2) = (Aa)
(R2) and the repeat count is zero, the termination stage stores zero
as the remnant repeat count and the P-register is not incremented.

11.

+0 is not equal to -0.

g

(R2)

= (Aa) g

g

(R2) and ~he repeat count is not zero, another test stage is initiated.

8604 Rev. 1

I

SPERRY UNIVAC 1100/80 Systems

~~_ _ ~~ Capability Processor and Storage Programmer Reference

5.S.S:. Maskud Search Not Equal -

MSNE

5-25
PAGE

71,01

Skip NI if (U) ~ (R2) -: (A) IANCj (R2), else repeat.
During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
SubSElction, th4! contents of Aa and R2 are transferred to the arithmetic section, the logical product
of th4t values f:rom Aa and R2 is formed, and the P-register is incremented.
If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
coun1t is decreased and the contents of U is "transferred to the arithmetic section. (U) ~ (R2) is
comp,ared' to (Aa) IANij (R2l and:
.
•

If (U) ~ (R2) -: (Aa) IANet (R2l, the termination stage is initiated. This stage stores the remnant
repeat count and increments the P-register (skip NI).

•

If (U) ~I (R2l

•

If (U) JANDt (R2)
(Aa) ~ (R2) and the repeat count is zero, the termination stage stores zero
as the remnant repeat count and the P-register is not incremented.

1.

+0 is not equal to -0.

=

(Aa) ~ (R2) and the repeat count is not zero, another test stage is initiated.

=

5.6.S" Masked Search Less Than or Equal/Not Greater - MSLE,MSNG 71,02
Skip NI i·f (U) IANQ (R2) ~ (A) ~ (R2), else repeat
During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
SUbS4!ction, the contents of Aa and R2 are transferred to the arithmetic section, the logical product
of this values 'from Aa and R2 is formed, and the P-register is incremented.
If thet initial repeat count is zero. the next instruction (NI) is initiated.
If the initial repeat count is not zero. the first test stage is initiated. During each test stage, the repeat
count is decreased and the contents of U is transferred to the arithmetic section. (U) ~ (R2) is
compared to (Aa) ~ (R2) and:
•

If (U) ~ (R2l ~ {Aa~ ~ (R2), the termination stage is initiated. This stage stores the remnant
repeat cc)unt and increments the P-register (skip NI).

•

If (U) ~ (R2)

•

If (U) ~j (R2) > (Aa) ~ (R2) and the repeat count is zero, the termination stage stores zero
as the remnant repeat count· and the P-register is not incremented.

1.

+0 is greater than -0.

> (Aa) ~

(R2) and the repeat count is not zero, another test stage is initiated.

5.6.10. Mas.ked Search Greater Skip NI if (U) ~ (R2)

>

MSG

71,03

(A) ~ (R2), else repeat

Durililg the initial stage, the conter:'lts of the repeat count register (R 1) is transferred to the index
subs,ection, the contents of Aa and R2 are transferred to the arithmetic section, the logical product
of the values from Aa and R2 is formed, and the, P-register is incremented.

8804 Rev.1

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SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
count is decreased and the contents of U is transferred to the arithmetic section. (U) IANC4 (R2) is
compared to (Aa) ~ (R2) and:
•

If (U) ~ (R2) > (Aa) ~ (R2), the termination stage is initiated. This stage stores the remnant
repeat count and increments the P-register. (Skip NI.)

•

If (U) ~ (R2) ~ (Aa) ~ (R2) and the repeat count is not zero, another test stage is initiated.

II

If (U) ~ (R2) ~ (Aa) ~ (R2) aod the repeat count is zero, the termination stage stores zero
as the remnant repeat count and the P-register is not incremented.

1.

+0 is greater than -0.

5.6. 11. Masked Search Within Range Skip NI if (A) ~ (R2)

<

MSW

71,04

(U) ~ (R2) ~ (A+ 1) ~ (R2), else repeat.

During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subsection, the contents of Aa, Aa+ 1, and R2 are transferred to the arithmetic section, the logical
products of the values from Aa and R2 and the values from Aa+ 1 and R2 are formed, and the
F'-register is incremented; If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage, the repeat
count is decreased and the contents of U is transferred to the arithmetic section. The logical products·
are compared and:

II

If (U) ~ (R2) > (Aa) ~ (R2) and (U) ~ (R2) ~ (Aa+ 1) ~ (R2) the termination stage is
initiated. This stage stores the remnant repeat count and increments the P-register. (Skip NI.)

•

If (U) ~ (R2) ~ (Aa) ~ (R2) or (U) ~ (R2)
zero, another test stage is initiated.

..

If (U) ~ (R2) ~ (Aa) ~ (R2) or (U) ~ (R2) > (Aa+ 1) ~ (R2) and the repeat count is zero,
the termination stage stores zero as the remnant repeat count and the P-register is not
incremented.

'1.

Normally, (Aa) ~ (R2) < (Aa+ 1) ~ (R2). If, however, (Aa) ~ (R2) ~ (Aa+ 1)
no possible value of U will satisify the search condition.

2.

+0 is greater than -0.

5.S.12. Masked Search Not Within Range -

>

(Aa + 1) IANC4 (R2) and the repeat count is not

MSNW

Skip NI if (U) ~ (R2) ~ (A) ~ (R2) or (U) ~ (R2l

lANa

(R2),

71,05

>

(A+ 1)

lANa

(R2), else repeat

lOuring the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subsection, the contents of Aa and R2 are transferred to the arithmetic section, the logical products
of the values from Aa and R2 and the values from Aa+ 1 and R2 are formed, and the P-register is
lincremented.

I

8804 AeY.1

SPERRY UNIVAC 1100/80 System.

~_~ Capability Processor and Storage Programmer Reference

If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial reJ:leat count is not zero, the first test stage is initiated. During each test stage, the repeat
count: is decre~lsed and the contents of U is transferred to the arithmetic section. The logical products
are cI)mpared and:
•

I:f (U) ~I (R2) ~ (Aa) Iamj (R2) or (U) Iamj (R2) > (Aa + 1) Iamj (R2) the termination stage is
initiated. This stage stores the remnant repeat count and increments the P-register. (Skip NI.)

•

I:f (U) Iamj (R2) > (Aa) Iamj (R2) and (U) Iamj (R2) ~ (Aa+ 1) Iamj (R2) and the repeat count is
"ot zero, another test stage is initiated. .

•

Ilf (U) Iamj (R2) > (Aa) Iamj (R2) and (U) Iamj (R2) ~ (Aa-1) Iamj (R2) and the repeat count is zero,
1the termination stage stores zero as the remnant repeat count and the P-register is not
ilncremen'ted.
.

1.

I~ormally, (Aa) Iamj (R2) < (Aa+ 1) Iamj (R2). If, however, (Aa) Iamj (R2) ~ (Aa+ 1)
livery poslsible value of U will satisfy at least one of the following conditions:

2.

(U)

l6Jm

(IR2) ~ (Aa) lANa (R2)

(U)

Iamj

(R2)

>

(Aa+ 1)

Iamj

Iamj

(R2),

(R2)

+0 is greater than -0.

5.S.13. Masf (Aa) Iamj (R2) and the repeat count is zero, the termination stage stores zero
as the remnant· repeat count and the P-register is not incremented.

1.

.-0 is gre,lter than +0.

ml (R2) > (Aa) Iamj (R2) and the repeat count is not zero, another test stage is initiated.
gl

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

UI4IIlMIa

4x4 Capability Processor and Storage Programmer Reference

5.6. 14. Masked Alphanumeric Search Greater Skip NI if (U) ~ (R2)

>

MASG

5-28
UfIOATi LIYIL

I'AGI

71,07

(A) ~ (R2), else repeat

During the initial stage, the contents of the repeat count register (R 1) is transferred to the index
subsection, the contents of Aa and R2 are transferred to the arithmetic section, the logical product
of: the values from Aa and R2 is formed, and the P-register is incremented.
If the initial repeat count is zero, the next instruction (NI) is initiated.
If the initial repeat count is not zero, the first test stage is initiated. During each test stage. the repeat
cc)unt is decreased and the contents of U is transferred to the arithmetic section. (U) ~ (R2) is
compared alphanumericaUy to (Aa) ~ (R2), and:
•

If (U) ~ (R2) > (Aa) ~ (R2), the termination stage is initiated. This stage stores the remnant
repeat count and increments the P-register (skip NI).

•

If (U) ~ (rl2) ~ (Aa) ~ (R2) and the repeat count is not zero, another test stage is initiated.

•

If (U) ~ (R2) ~ (Aa) ~ (R2) and the repeat count is zero, the termination stage stores zero
as the remnant repeat count and the P-register is not incremented.

1.

-0 is greater than +0.

5.7. Test (or Skip) Instructions
Test instructions are used to read one or more words from storage or control registers and test for
certain conditions. The result of the test is used to determine whether the instruction addressed by
the incremented contents of the P-register (next instruction) should be performed or skipped.
The next instruction (NI) is always read from storage. If the decision is made to skip NI, it is discarded,
the P-register is incremented a second time. and the contents of the P-register is then used to address
the following instruction.
Indirect addressing, indexing, and index register incrementation/decrementation operate normally.

5.7. 1. Test Even Parity -

TEP

44

Skip NI if (U) ~ (A) has even parity.
The value from U is transferred to the arithmetic s8Ot10n under j-field control. where it is used with
the contents of Aa to form a 36-bit logical product.
If (U) ~ (Aa) has an even number of 1 bits. the next instruction (NI) is skipped and the instruction
following NI is performed.
If (U) ~ (Aa) has an odd number of 1 bits, NI is performed.

I

8804 AeY.l

SPERRY UNIVAC 1100/80 Systems

Uf'..,MIER_~~

Capability Processor and Storage Programmer Reference

5.7.2. Test Odd Parity -

TOP

5-29
UIIOATI LEVEL

flAGI

45

Skip NI if (A) ~ (U) has odd parity.
The contents of U is transferred to the arithmetic section under j-field control. where it is used with
the cc)ntents of Aa to form a 36-bit logical product.
If (U) I~ (Aa) has an odd number of 1 bits. the next instruction (NI) is skipped and the instruction
following NI is performed.
If (U) :~ (Aa) has an even number of 1 bits, NI is performed .

. 5.7.3. Test Less Than or EquallTest Not Greater Than Modifier - TLEM,TNGM 47
Skip NI if (U), 7-0 ~ (Xa), 1-0; always (Xa), 1-0

+ (Xa) 35-18

-

Xa 11-0

The clontents of U is transferred to the arithmetic section under j-field control. The contents of the
index register addressed by the a-field (Xa) is transferred to the arithmetic section. The rightmost
18 bi1ts of the value from U is subtracted from the rightmost 18 bits of the value from Xa (this is
performed as if the leftmost 18 bits of each operand were zeros).
If (U)11-O ~ (Xa)17-O (the sign of the difference is positive), the next instruction is skipped and the
instrulction follc)wing NI is performed.
If (U),1-O

>

(X~ilh 7-0

(thiS sign of the difference is negative), NI is performed.

In either case. the leftmc)st 18 bits from Xa are added to the rightmost 18 bits from Xa. and the sum
is stored in the rightmost 18 bit positions of Xa. The leftmost 18 bit positions of Xa are not changed.
1.

I~f

2.

+0 is les!1 than -0.

3.

Eloth Xa 17-0 and the value from U are considered to be 18-bit numeric values with a positive
s,ign impli,ed.

4.

()nly the rightmost 18 bits of the value from U are involved in the operation. Values of O. 1.
clr 3 in the j-field yi.tld the same results. Values of 16 a or 178 in the j-field yield the same result.

5.

1if h -

a

::II

0, index register zero (XO) is referenced.

1 alnd a

5.·7.4" Test Zero -

= ", the specified index register is incremented or modified only once.
TZ

50

Sikip NI if (U) - :0.
The Cl3ntents of U is transferred to the arithmetic section under j-field control.
If the value tralnsferred is
performed.

!: 0,

the next instruction is skipped and the instruction following Nt is

If the value transferred lis not :0, NI is performed.

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

1.

. The contents of the a-field is ignored.

5.7.5. Test Nonzero Skip NI if (U)

TNZ

51

= :!: O.

The contents of U is transferred to the arithmetic section under j-field control.
If: the value transferred is not:!: 0, the next instruction is skipped and the instruction following NI is

performed.
If: the value transferred is :!: 0, NI is performed.

1.

The contents of the a-field is ignored.

5.7.6. Test Equal -

TE

52

Skip NI if (U) -. (A).
The contents of U is transferred to the arithmetic section under j-field control. The contents of Aa
is also transferred to the arithmetic section.
If (U) -

(Aa), the next instruction is skipped and the instruction following NI is performed.

If (U)

= (Aa). Nt

1!.

+0 is not equal to -0.

is performed.

E>'7.7. Test Not Equal Skip Nt if (U)

TNE

53

= (A).

1ne contents of U is transferred to the arithmetic section under j-field control. The contents of Aa
i:s also transferred to the arithmetic section.
If (U) ~ (As), the next instruction is skipped and the instruction following NI is performed.

If (U) - (Aa), Nt is performed.

•

'1.

+0 is not equal to -0.

!5.7.S. Test Less Than or EquallTest Not Greater - TLE,TNG

54

Skip Nt if (U) ~ (A).
"lne contents of U is transferred to the arithmetic section under j-field controJ. The contents of Aa
iiS also transferred to the arithmetic section.
Ilf (U) ~ (Aa), the next instruction is skipped and the instruction foHowing NI is performed.
IIf (U)
'1.

>

(Aa). NI is performed.

+0 is greater than -0.

I

8e04 Aev.1

SPI:RRY UNIVAC 1100/80 Systems

~4 Capability Processor and Storage Programmer Reference

UI'-MJMIM

5.7.9. Test Greater Skip NI if (U)

>

TG

5-31
I'M.

55

(A).

The contents of U is tl'ansferred to the arithmetic section under j-field control. The contents of Aa
is also transferred to the arithmetic section.

>

If (U')

(Aa), the next instruction is skipped and the instruction following NI is performed.

If (U) ~ (Aa), Nt is performed.

1.

+0 is greater theJn -0.

5.7 . 1O. Tes~t Within Range Skip NI if (A)

<

TW

56

(U) ~ (A+ 1).

The contents of U is transferred to the arithmetic section under j-field control. The contents of Aa
and Aa+ 1 al'e also transferred to the arithmetic section.
If (Aa)

< (U)

~~ (Aa+ 1), the next instruction is skipped and the instruction following NI is performed.

If (UI) ~ (Aa) or (U)

>

(Aa+ 1), NI is performed.

1.

+0 is greater ,th~Jn -0.

2.

Normally, (Aa}
condition (Aa)

< (Aa+ 1). If, however, (Aa)
< (U) ~ (Aa + 1).

5.7" 11. Te~it Not Within. Range Skip NI if (U) ~ (A) or (U)

>

~ (Aa+ 1), there is no value of U that can satisfy the

TNW

57

(A+ 1).

The contents of U is transferred to the arithmetic section under j-field control. The contents of Aa
and Aa+ 1 are also transferred to the arithmetic section.
If (Ul ~ (Aa) or (U)
perf:ormed.

>

(Aa+ 1), the next instruction is skipped and the instruction following NI is

If (tI)

>

1.

+0 is greater than -0.

2.

Normally, (Aa) < (Aa+ 1). If, however, (Aa) ~ (Aa+ 1), every. possible value of U will satisfy at
least one of the following conditions:

(Aa) and (U) ~ (Aa+ 1), Nl'is performed.

(U) ~ (Aa)

or
(U)-> (Aa+ 1)

880.. Rev.1

SPERRY UNIVAC 1100/80 Systems

Ufl-NUMia

4x4 Capability Processor and Storage Programmer Reference

5.7.12. Test Positive Skip NI if (U)35

:=II:

TP

60

O.

"he contents of U is transferred to the arithmetic section under j-field control.
I'f the sign bit (bit 35) of the value from U is a 0 bit. the next instruction is skipped and the instruction
following NI is performed.
,If the sign bit is a 1 bit, NI is performed.
1.

The contents of the a-field is ignored.

:2.

Always skip when j

= H 1, H2, Q 1-04, or S 1-S6.

5.7.13. Test Negative Skip NI if (Ubs

TN

61

= 1.

The contents of U is transferred to the arithmetic section under j-field control.
If the sign bit (bit 35) of the value from U is a 1 bit, the next instruction is skipped and the instruction
following NI is performed.
If the sign bit is a 0 bit, NI is performed.
1.

The contents of the a-field is ignored.

2.

Never skip when j

= H 1, H2, Q 1-04, or 51-56.

5.7. 14. Double-Precision Test Equal -

DTE

71,17

5kip NI if (U. U+ 1) - (A, A+ 1).
The contents of U. U+ 1, Aa, and Aa+ 1 are transferred to the arithmetic section. U, U+ 1 and Aa,
Aa + 1 are 72-bit operands.
If (U. U+ 1) - (Aa, Aa+ 1). the next instruction is skipped and the instruction following NI is performed.
If (U. U+ 1)
'1.

= (Aa.

Aa+ 1), NI is performed.

+0 is not equal to -0.

5.8. Shift Instructions
each shift instruction transfers either one or two words to the arithmetic section, moves or shifts the
bits of the words. and stores the shifted word or words in one or two control registers.
The following basic types of shifts are provided for both single-word (36-bit input operand) and
double-word (two 38-bit words treated as a 72-bit input operand) operations:

880<4 Rev.1

I

SPERRY UNIVAC 1100/80 Systems

~~___ ~ Capability Processor and Storage Programmer Reference

•

5-33
UftOATi LIVIL

"AGI

Flight circular
F:or a right-circular shift, a shift count of n moves the contents of all bit positions of the register
holding the input operand n bit positions to the right. Bits shifted out the right end'of the register
alppear in the leftmostlbit positions vacated by the shift.

•

l.eft circular
F:or a left-circular shift, a shift count of n moves the contents of all bit positions of the register
holding the input operand n places to the'left. Bits shifted out the left end of the register appear
iln the rightmost bit positions vacated by the shift.
F:or example: A shift count of 6 for a right-circuJar shift applied to 765432101234 8 as the input
clperand produces 347654321012 8 as the result. The same result is produced using a shift
c:ount of 30 for a left-circuJar shift.
F:or a single-word circular shift, a shift count of 72 or 36 produces the same result as a shift
count of 0 (no shift). A shift count of 37 produces the same effect as a shift count of 1, a shift
c:ount of ~i8 produces the same effect as a shift count of 2, and so on.

•

Hight logical
For a right-logical shift, a shift count of n moves the contents of all bit positions of the register
holding the input operand n places to the right. Bits shifted out the right end of the register
~Ire lost. The leftmost bit positions vacated by the shift are zero filled.
F:or exam~)le: A shift count of 6 for a right-togical shift applied to 765432101234 8 as the input
()perand ~)foduces 007654321012 8 as the result.

•

l.eft logic:al
'=or a left·~ogical shift, a shift count of n moves the contents of all bit positions of the input
()perand register n places to the left. Bits shifted out the left end of the register are lost. The
rightmost bit positions vacated by the shift are zero filled,

':or example: A shift count of 6 for a left-logical shift applies to 765432101234 8 as the input
c)perand produces 543210123400 8 as the result.
•

I~ight algttbraic

I=or an algebraic shift (right only, since no left algebraic shift is provided), a shift count of n moves
the contents of all bit positions of the register holding the input operand n places to the right.
IBits shiftEld out the right end of the register are lost. The bit positions vacated by the shift are
jfilled with bits identical to the leftmost bit (sign bit) of the original input operand.
IFor example: A shift count of e for an algebraic shift applied to 765432101234 8 as the input
loperand produces 777654321012 8 as the result.
The two Load Shift and Count instructions are basically left circular shift instructions. The shift count
is determined by the configuration of the bits of the input operand. If the two leftmost bits are not
identiical, the !ihift count is zero. If the two leftmost bits are identical, the operand is shifted left
circuliar by the' minimum amount to position the bits of the input operand so that the two leftmost
bits alr8 not identical. The shift count is the count of the number of bit positions shifted. If all bits
of an input operand are identical, no amount of circular shifting will position its bits so that the two
left-most bits are not identical. In this instance, the shift count is 35 (single-word operand) or 71
(double-word operand). The shift count is stored in a control register.

8e04 Rev.1

SPERRY UNIVAC 1100/80 Systems

IJII..M .....

4x4 Capability Processor and Storage Programmer Reference

For all shift instructions, except the two Load Shift and Count instructions. the input operands are
specified by one or two A-registers, and the shift count is specified by bits 6 through 0 of the effective
LI. Indirect addressing, indexing, and index register incrementation/decrementation operate normally
flor all shift instructions.
The shift count can be any number between <;> and 72. If a shift count of 73 to 127 (1118 through
177 8) is specified, the result produced is undefined. The value in the u-field of the shift instruction
and the value of Xm (if x = 0) must be chosen accordingly.
For the two Load Shift and Count instructions, the effective U specifies the input operand address
just as for the other load instructions. The scaled result is loaded in the specified A-register (A, A+ 1
for Double Load Shift and Count instruction). The number of shifts required for scaling is stored in
the next consecutive register A+ 1 (or A+2 for Double Load Shift and Count instruction).

5.S.1. Single Shift Circular -

SSC

73,00

Shift (A) right circularly U places.
'rhe contents of Aa is transferred to the arithmetic section. The shift count from bits 6 through 0
of U is transferred to the arithmetic section. The value from Aa is shifted right circularly by the number
of bit positions specified by the shift count. The shifted value is stored in Aa.
1.

The result stored is not defined for shift counts greater than 72.

2.

If 36 ~ n ~ 72, a shift count of n produces the same result as a shift count of n-36.

5.S.2. Double Shift Circular -

DSC

73,01

Shift (A. A+ 1) right circularly U places.
The contents of Aa and Aa+ 1 are transferred to the arithmetic section. The shift count from bits
6 through 0 of U is transferred to the arithmetic section. The 72-bit value from Aa and Aa+ 1 is shifted
right circularly the number of bit positions specified by the shift count. The shifted value is stored
in Aa and Aa+ 1.
1.

The result stored is not defined for shift counts greater than 72.

5.S.3. Single Shift Logical -

SSL

73,02

Shift (A) right U ptaces, zero fill.
The contents of Aa is transferred to the arithmetic section. The shift count from bits 6 through 0
of U is transferred to the arithmetic section. The value from Aa is right shifted the number of bit
positions specified by the shift count. Bits shifted out of the rightmost bit positions are lost; the
vacated leftmost bit positions are zero filled. The shifted value is stored in Aa.
1.

- 2.

The result stored is not defined for shift counts greater than 72.
If 36 ~ U ~ 72, the result stored in Aa is +0.

PERRY
~
-----

8804 Rev. 1
u......,...

UNIVAC 1100/80 Systems

4x4 CapabiUty Processor and Storage Programmer Reference

5.8.4. Double Shift Logical -

DSL

U.-oATi LIVIL

5-315
'AGI

73,03

:Shift (A,A+ 1) right U places, zero fill.
The c:ontents ()f Aa and Aa+ 1 are transferred to the arithmetic section. The shift count from bits
6 thrc.ugh 0 of U is transferred to the arithmetic section. The 72-bit value from Aa and Aa+ 1 is right
shifted the nurnber of bit positions specified by the shift count. Bits shifted out of the rightmost bit
positions are lost; the vacated leftmost bit positions are zero filled.

1.

'rhe result stored is not defined for shift counts greater than 72.

5.8.5. Single Shift Algebraic -

SSA

73,04

:Shift (A) r'ight U places. sign fill.
The contents c)f Aa is transferred to the arithmetic section. The shift count from bits 6 through 0
of U is transferred to the arithmetic section. The value from Aa is right shifted the number of bit
positions specified by the shift count. Bits shifted out of the rightmost bit positions are lost; bits
identical to the content of bit 35 of the initial value from Aa appear in the vacated leftmost bit
positi,ons. The shifted count is stored in Aa.

1.

'rhe resul1t stored. is not defined for shift counts greater than 72.

2.

If 35 ~ LJ ~ 72, all bits of the result stored in Aa are identical to the leftmost bit of the input
()perand fTom A.a.

5.8.6. Doublle Shift Algebraic Shift (A,

J~+ 1)

DSA

73,05

right U places, sign fill.

The contents of Aa and Aa+ 1 are transferred to the arithmetic section. The shift count from bits 6
throu~gh 0 of U is transferred to the arithmetic section. The 72-bit value from Aa and Aa+ 1 is right
shifted the number of bit positions specified by the shift count. Bits shifted out of the rightmost bit
positions are 14)$t; bits identical to the contents of bit 35 of the initial value from Aa appear in the
vacatlsd leftmost bit positions. The shifted value is stored in Aa and Aa+ 1.

1.

'lne result stored is not defined for shift counts greater than 72.

5.8.7. Load Shift and Count ~:U)

LSC

73,06

- A; :shift (A) left circularly until (A)3!5

= (A)34;

number of shifts -

A+ 1.

The contents of location U is transferred to a nonaddressable 36-bit register in the arithmetic section
and then shiftetd left circularly the minimum number of bit positions which will make bit 35 unequal
to bit 34. Thel resultant scaled number is transferred to Aa and the shift count to Aa + 1.
1.

Ilf bit 35 ()f the value from location U is not equal to bit 34, the number is already scaled and
Ino shift Olccurs: (U) - Aa; +0 - Aa+ 1.

2.

Ilf the value from location U is :0: (U) -

Aa, the shift count is 35, and 43 8 -

Aa+ 1.

8804 Rev.1

SPERRY UNIVAC 1100/80 Syst.m.

~D

4x4 Capability Processor and Storage Programmer Reference

5.8.8. Double load Shift and Count -

DlSC

UllDAl1 LIVIL

73,07

(U, U+ 1) - A, A+ 1; shift (A, A+ 1) left circularly until (A, A+ 1),1
-A+2.

= (A,A+ 1),0; number of shifts

The' contents of U and U+ 1 are transferred to a nonaddressable 72-bit register in the arithmetic
sec'tion and then shifted left circularly the minimum number of bit positions which will make bit 71
une'Qual to bit 70. The resultant scaled number is transferred to Aa and Aa+ 1 and the shift count
to Aa+2.
1.

If bit 71 of the value from U and U + 1 is not equal to bit 70, the double length number is already
scaled and no shift occurs: (U) - Aa; (U+ 1) - Aa+ 1; +0 - Aa+2.

2.

If the double-length value from locations U and U + 1 is:: 0: (U) - Aa; (U + 1) - Aa + 1; the shift
count is 71; 107 8 - Aa+2.

5.81.9. left Single Shift Circular -

LSSC

73,10

Shift (A) left circularly U places.
The contents of Aa is transferred to the arithmetic section. The shift count from bits 6 through 0
of U is transferred to the arithmetic section. The value from Aa is shifted left circularly the number
of bit positions specified by the shift count. The shifted value is stored in Aa.
1.

The result stored is undefined for shift counts greater than 72.

2.

If 36 ~ n ~ 72, a shift count of n produces the same result as a shift count of n-3S.

5J3. 1O. left Double Shift Circular -

lDSC

73,11

Shift (A, A+ 1) left circularly U places.
The contents of Aa and Aa+ 1 are transferred to the arithmetic section. The shift count from bits
6 through 0 of U is transferred to the arithmetic section. The 72-bit value from Aa and Aa+ 1 is shifted
left circularly the number of bit positions specified by the shift count. The shifted value is stored in
Aa and Aa+ 1.
1.

The result stored is undefined for shift counts greater th'n 72.

5.8.11. left Single Shift logical -

lSSL

73,12

Shift (A) left U places, zero fill.
The contents of Aa is transferred to the arithmetic section. The shift count from bits S through 0
of U is transferred to the arithmetic section. The value from Aa is left shifted the number of bit
positions specified by the shift count. Bits shifted out of the leftmost bit positions are lost the vacated
ri~Jhtmost bit positions are zero filled. The shifted value is stored in Aa.

1:

The result stored is undefined for shift counts greater than 72.

2.

If 36 ~ U ~ 72. the result stored in Aa is +0.

-----~

PERRY UNIVAC 1100/80 Systems

a8Q4 Rev.1

4x4 Capability Processor and Storage Programmer Reference

U"-HUMIIER

5.8.12. Left Double Shift Logical -

LDSL

5-37
'AGI

73,13

:Shift (A, A+ 1) left U places, zero fill.
The contents (.f Aa and Aa+ 1 are transferred to the arithmetic section. The shift count from bits 6
throu1gh 0 of U is transferred to the arithmetic section. The 72-bit value from Aa and Aa+ 1 is left
shifted the nurnber of bit positions specified by the shift count. Bits shifted out of the leftmost bit
positions are lost; the vacated rightmost bit positions are zero filled. The shifted value is stored in
Aa arId Aa+ 1.

1.

'rhe result stored is undefined for shift counts greater than 72.

5.9. Unconditional Jump Instructions
A jump is a ch~lnge in the sequence in which instructions are executed. It is accomplished by placing
a new value in the program address register (P-register). Each unconditional jump instruction
performs a, unique operation in addition to the common operation of placing a new value in the
P-register.
If the relative "jump to" address is less than 200 s, the next instruction is taken from the storage
location addressed by the value rather than from a control register.
The Jump KeY!1 instruction can be used to specify either a conditional or an unconditional jump. The
Halt ..lump/Halt Keys and Jump instruction specifies an unconditional jump, but the halt portion is
conditional. Both of these instructions are included in the section on conditional jump instructions
(see f5. 11).

5.9. 1. Store Location and Jump -

SW

~

72,01

.Relative F)+ 1 -, U 17-O; jump to U+ 1
The ft-register is incremented. An l8-bit relative return address is stored in the rightmost 18 bits
of thf~ locatioTi specified by the operand address. The value of the operand address plus one is
trans1ferred to the P-register as the "jump to" address. The upper half of the operand is unchanged.
1.

'The contlants of the a-field is ignored.

2.

If U < 2C)Os, the l8-bit relative return address is stored in the rightmost 18 bits of the control
register addressed by U, and the leftmost 18 bit positions of that control register are unchanged.

3.

The la-bit address always represents a relative address. Therefore, executing this instruction
in absolute addressing mode may produce erroneous results.

4.

The relative return address is stored in the low-order 18 bits of a word. If this la-bit relative
return address is larger than 16 bits, the two high-order bits will be interpreted as hand i bits
if the address is used in an instruction. The instruction may produce erroneous results.

S.9.:L Load Modifier and Jump Relative P+ 1 -

LMJ

74,13

Xa17-O; jump to U

The I;I-registef' is incremented. An 18-bit relative return address is stored in the rightmost 18 bits
of the index register specified by the a-field. The leftmost 18 bits of that index register are not
affected. The value of the operand is transferred to the P-register as the "jump to" address.

8804 Rev.1

SPERRY UNIVAC 1100/80 Svaem.

UP-HUMIIR

4x4 Capability Processor and Storage Programmer Reference

U.-oATI LEVEL

1."':-38

=

1.

If the GRS selection designator (06)
0 and the value in the a-field is zero, the relative return
address is stored in index register zero (XO).

2.

If index register incrementation is specified, the relative return address is stored in the index
register specified by the a-field after the new value for Xm is stored in the index register
specified by the x-field. As a consequence, if the value in the a-field is not zero and it is the
same as the value in the x-field, it makes no difference whether the value in the h-field is zero
or one.

5.9.3. Allow All Interrupts and Jump -

AAIJ

74,07

Allow all interrupts and jump to U.
This instruction allows interrupts prevented by the occurrence of an interrupt or the execution of a
'Prevent All Interrup~s and Jump inst~ction.
1.

The contents of the a-field is ignored.

2.

The Allow All Interrupts and Jump instruction does not affect the Oayclock interrupt when it is
disabled by the Disable Dayclock instruction and enabled by the Enable Dayclock instruction.

5.10. Bank Descriptor Selection Instructions
Each program may be composed of or associated with a large number of program or data segments;
of these. up to four may be active at any given time. Bank Descriptor selection instructions allow
a program to select which segments are among the four that are currently active.

5 . 10. 1. Load Bank and Jump -

LBJ

07,17

The LBJ instruction loads the bank descriptor register selected by bit position 34 and 3;3 of the index
re.gister specified by the a-field of the instruction word (Xa) with a new bank descriptor, stores the
old bank descriptor indexing information and relative program address in Xa as return information,
and then jumps to the location specified by the operand address. The new bank descriptor is located
by adding the bank descriptor index contained in bit positions 18 through 29 of Xa to the bank
descriptor table pointer selected by bit position 35 of Xa. If bit 35 is zero, the user pointer and table
are selected: if bit 35 is one, the Executive pointer and table are selected. An Address Exception
interrupt occurs when bit 35 is one and the EXEC bank descriptor table pointer enable designator
(019) is zero. An Address Exception interrupt also occurs if the bank descriptor index value exceeds
the length of the table.
Before the new bank descriptor values are actually loaded, the old bank descriptor is . located and
the use-count field is decreased by one under storage lock. An Addressing Exception interrupt occurs
if the C-flag of the old bank descriptor is one and the use count is decreased to zero, or if the use
cc)unt is decreased from zero to aU ones. The new bank descriptor is loaded in the bank descriptor
register, the P-flag is transferred to the privileged instruction, GRS protect, and interrupt lockout
detect designator (02), and the W-flag of the new bank descriptor is placed in the appropriate
w'rite-protection bit of the bank descriptor register designator bits (013 through 016).
~/hen

the new bank descriptor is located, the associated use count field is increased by one under
storage lock. and an Addressing Exception interrupt occurs if the R-flag of the bank descriptor is one,
if there is a V-flag violation, or if the use count field is increased from all ones to zero.

-----D

8804 fWv.1
UNAlMIIR

PE:RRY UNIVAC 1100/80 Sv-tems

4x,4 Capability

Proc~ssor

5-39

and Storage Programmer Reference

UII'OATE LIV!L

"AGE

The Etppropriate bank descriptor indexing information is copied from the GRS processor state area
into the upper half of Xa, the relative program address is copied into the lower half of Xa, and the
new bank descriptor indexing information is stored in the appropriate half word of GAS 46 8 or 47 8 ,
The (»perand alddress is formed and a jump to that location is effected. If both an address exception
and jiump address guard mode limits violation occur during the execution of this instruction, the
addmss exception will be taken.
The f:ollowing are the formats of Xa before and after execution of the instruction:

~O ·_O~I__________~__
___

35 34 33 32

W
__
B_Df________

30 29

N_ot_U_~

_______________

___________________

O_ld__
BD_'________

30 29

6.101.2. Load I-Bank Base and Jump -

~

__________R_ef_aw_'_e_p_rog
__ra_m__A_dd_r_e_
••_________

~
o

18 17

LlJ

~

o

18 17

~_O_-__O~I___________
31 3. 33 32

~

07, 13

The 11..IJ instruction is executed as a special case of the lBJ instruction. Bit positions 34-33 of Xa
are i~lnored; if the BOA selector designator (0 12) is zero, BOAO is loaded and the BOR field (bits 34-33)
of the bank djascriptor index is written to 08; and if 012 is one, BOR 1 is loaded and the BOA field
is wr'itten to 18 ,

5. 1CI.3. Load D-Bank Base and Jump -

LDJ

07, 12

The Il.DJ instruction is executed as a special case of the lBJ instruction. Bit positions 34-33, of Xa
are i~~nored; if the BOA selector designator (0 12) is zero, BOR2 is loaded and the BOR field (bits 34-33)
of the bank dl9scriptor index is written to 2 8; and if 012 is one, BOR3 is loaded and the BOR field
is written to ~J8'

5.11. Conditional Jump Instructions
Each of the conditio'nal jump instructions performs a test for a specific condition (or set of conditions).
If the. condition is satisfied, the value U is transferred to the P-register, and the instruction addressed
by U is performed next. If the condition is not ~atisfied, the next instruction (Nt) is performed.

S804 Rev. 1

SPERRY UNIVAC 1100/S0 System,

UNtUMIER

4x4 Capability Processor and Storage Programmer Reference

5. 11. 1. Jump Greater a':1d Decrement Jump to U if (control register)ja
-1 - control registerja'

JGD

5~0

UPDATE LIVIL

'AGI

70

> 0'; go to NI if (control register)ja

~ 0; always (controlregister)ja

If the 36-bit signed number in the control register addressed by the rightmost 7 bits of the ja-field
is greater than zero (bit 35 contains a 0 bit and the number does not consist of all 0 bits), the
instruction at location U is executed next. If the number is less than, or equal to, zero (bit 35 contains
a 1 bit or the number consists of all 0 bits), the next instruction· is performed. In either case, the
number is decreased by one and the difference is stored in the control register addressed by the
ja-field.
1.

A Guard Mode interrupt occurs (if guard mode is set) when the ja-field specifies a value in the
range 40 s through 100 8, or 120s through 1778 if the privileged instruction, GRS protect, and
interrupt lockout detect designator (02) := 1. This is true regardless of the value of the GRS
selection designator (06).

2.

The leftmost bit in the j-field is ignored.

5. 11.2. Double-Precision Jump Zero Jump to U if (A,A+ 1)

DJZ

71, 16

= :0; go to NI if (A.A+ 1) ~

:0.

If the 72-bit operand contained in Aa and Aa+ 1 is: 0, the instruction at location U is performed next.
If the operand is not: O. the next instruction (NI) is performed.

5. 11.3. Jump Positive and Shift -

JPS

72,02

Jump to U if (A}35 =- 0; go to NI if (A)3! =- 1; always shift (A) left circularly one bit position.
If bit 35 of Aa contains a 0 bit, the instruction at location U is performed next. If bit 35 contains
a 1 bit, the next instruction is performed. The contents of Aa is always shifted left circularly one bit
position.
'I.

The bit shifted out of bit 35 of Aa is shifted to bit

!5.11.4. Jump Negative and Shift -

JNS

a of Aa.

72,03

Jump to U if (A)3! .. 1; go to NI if (A)3! =- 0; always shift (A) left circularly one bit position.
If bit 35 of Aa is a 1 bit, the instruction at location U is performed next. If bit 35 is a 0 bit, the next
instruction is performed. The contents of Aa is always shifted left circularly one bit position.
1.

The bit shifted out of bit 35 of Aa is shifted to bit 0 of Aa.

5. 11.5. Jump Zero -

JZ

74,00

Jump to U if (A) .. :0; go to NI if (A)

= :0.

If (Aa) is ! 0, the instruction at location U is performed next. If As does not contain ! 0, the next
instruction is performed.

8804 Ftev.1
UNfUM8IIl

I

SPERRY UNIVAC 1100/80 Systems

~, Capability Processor and Storage Programmer Reference

5. 11 ,.6. Jump Nonzero .Jump to U if (A)

= :!: 0;

JNZ

UPOATI LEVEL

74,01

go to NI 'if (A)

::I

:!: O.

If (Aa~ is not:!: 0, the instruction at location U is performed next. If (Aa) is :: 0, the next instruction is
performed.

5.11.7. Jump Positive -

JP

74,02

,Jump to U jf (A)35 - 0; go to NI if (A)35

::I

1.

If bit 35 of Aa is a 0 bit, the rnstruction at location U is performed next. If bit 35 is a 1 bit, the next
instruction is Ilerformed.

5. 11.8. Jump Negative Jump to U if (A)35

IN

74,03

= 1; go to NI if (Ab5

::I

O.

If bit 35 of Aa is a 1 bit, the instruction at location U is performed next. If bit 35 is a
instruction is performed.

5.11.9. Jump/Jump Keys Jump to U if a -

0 or if a -

J,JK

a bit, the next"

74,04

set JUMP SELECT switch; go to NI if neither is true.

If the a-fiefd contains all 0 bits, the instruction at location U is performed next. If the a-field contains
a value in the range of 1 through 15 (18 through 17 8 ) and the correspondingly numbered JUMP
SELE,CT switch/indicator is set. the instruction at location U is performed next; if the correspondingly
. numbered JUMP SELECT switch/indicator is not set. the next instruction is performed.
1.

The indic:ator for each of the 15 JUMP SELECT switch/indicators is turned on by pressing that
JUMP SIELECT switch/indicator. Each is turned off by pressing the associated clear switch.
Either can be done while the central processor unit (CPU) is running.

2.

Care should be exercised in using a value other than aU 0 bits in the a-field if the program is
to run concurrently with onear more other programs. Any other program may include a Jump.
Keys ins'truction with the same value in the a-field and specify that it is to be run with the
corresponding JUMP SELECT switch/indicator set.

5. 111. 1O. Halt Jump/Halt Keys and Jump -

HJ,HKJ

. Stop if [aaO IQBI if (a lANa set STOP SELECT switches)
continuation jump to U.

74,05

= 0] g

02 .. 0; on restart or

If th~!t a-field contains all 0 bits, the execution of program instruction halts. If the a-field contains
a 1 bit in a bit position which corresponds to a lit STOP SELECT switch/indicator, the program halts.
A m~mual restart causes the instruction at location U to be executed next unless the program address
regi~~ter was manually changed while the CPU was halted.
Whetn the privileged instruction, GRS protect.and interrupt lockout detect designator (02) :. 1 and
the Ihalt conditions are satified. the jump is executed without halting.

SPERRY UNIVAC 1-100/80 Svst.ms

4x4 Capability Processor and Storage Programmer Reference

UfIOATi LIVIL

1.

The indicator for each of the four STOP SELECT switch/indicators is turned on by pressing one
of the STOP SELECT switch/indicators. They are turned off by pressing the associated clear
switch.

2.

If the program address register is manually changed while the CPU is halted, program execution
will resume at the new address when the CPU is restarted.

5.11.11. Jump No Low Bit Jump to U if (A)o

JNB

74,10

= 0; go to NI if (A)o = 1.

If bit 0 of Aa is a 0 bit~ the instruction at location U is performed next. If bit 0 is a 1 bit, the next
i"struction is performed.

1.

If the Jump No Low Bit instruction is used to determine whether the value in Aa is an even or
an odd integer, consideration must be g.iven to the sign of the value.

5. 11. 12. Jump Low Bit Jump to U if (A)o

JB

74, 11

= 1; go to NI if (A)o == O.

If bit 0 of Aa is a 1 bit, the instruction at location U is performed next. If bit 0 is a 0 bit. the next
h1struction is performed.

1.

If a Jump Low Bit instruction is used to determine whether the value in Aa is an even or an odd
integer, consideration must be given to the sign of the value.

5.11.13. Jump Modifier Greater and Increment Jump to U if (Xah7-O

>

JMGI

74,12

0; go to NI if (Xah7-O ~ 0;· always (Xa)17-O

+ (Xa)35_18

-

Xa17-O'

I'f the signed number in bits 17 through 0 of the X-register specified by the a-field is greater than
zero (bit 17 is a 0 bit and the number does not consist of aU 0 bits), the instruction at location U is
~)erformed next. If the number is less than or equal to zero (bit 1 7 is a 1 bit or the number consists
of all 0 bits), the next instruction is performed. In either case, the signed number in bits 35 through
'18 of the X-register is added to the signed number in bits 17 through 0, and the sum is stored in
bits 17 through 0 of the X-register.
".

The number in Xa 17-0 before the addition is tested, rather than the number resulting from the
addition.

:Z.

If a - x and h - 1, the specified index register is effectively modified only once for each
execution of the instruction.

5.11.14. Jump Overflow Jump to U if 01 -

JO

74,14; a

==

0

1; go to NI if 01 ... O.

Where' the a-field is an extention of the f- and j-fields.
If the overflow designator (01) is one, the instruction at location U is performed next. If 01 is zero,
the next instruction is performed.

8804

I

~eY.1

SPIERRY UNIVAC 1100/80 Systems

~4 Capability Processor and Storage Programmer Reference

Ufl-HUMIEIt

1.

5-43
PAGE

Performing the Jump Overflow instruction does not change 01.

5. 11.15. Jump Floating Underflow Jump to U if 021

==

JFU

74, 14; a = 1

1, clear 021; go to NI if 021

==

O.

If thel characteristic underflow designator (021) is one, the instruction at location U is performed next
and 021 is cleared by the instruction. If 021 is zero, the next instruction is performed.

5. 11. 16. Jump Floating Overflow Jump to U if 022 -

JFO

74, 14; a

=2

1, clear 022; go to NI if 022 - O.

If thEI charactEtristic overflow designator (022) is one, the instruction at location U is performed next
and 022 is cleared by the instruction. If 022 is zero, the next instruction is performed.

5.11.17. Jump Divide Fault -

JDF

74,14; a

=3

Jump to U if 023 == 1, clear 023; go to NI if 023 == O.
If thEt divide fault designator (023) is one, the instruction at location U is performed next and 023
is c'Etared by the instruction.
If 023 is zero, the next instruction is performed.
!

5.11.18. Jump No Overflow -

JNO

Jump to U if 01 == 0; go to NI if 01

74,15: a

==

=0

1.

If thEI overflow designator (01) is zero, the instruction at location U is performed. If 01 is one, the
next instructicm is performed.
1.

Executing the Jump No Overflow instruction does not change 01.

5. 11. 19. Jump No Floating Underflow Jump to U if 021 =- 0; go to NI if 021

JNFU

=-

74, 15; a

-= 1

1; clear 021.

If the! characteristic underflow designator (021) is zero, the instruction at location U is performed next.
If 02: 1 is one, the next instruction is performed. 021 is cleared by the instruction.

5. 11.20. Jump No Floating Overflow Jump to U if 022

=-

0; go to NI jf 022

JNFO

=-

74, 15; a = 2

1; clear 022.

If thEI charactElristic overflow designator (022) is zero, the instruction at location U is performed next.
If 02~2 i$ one, the next instruction (NI) is performed. 022 is cleared by the instruction.

8804 ArI.1

SPERRY UNIVAC 1100/80 Systems

tJI'..NtJMIrR

4x4 Capability Processor and Storage Programmer Reference

5. '11.21. Jump No Divide Fault Jump to U if 023

JNDF

= 0; go to NI if 023

74, 15; a

==

3

=- 1; clear 023.

If the divide fault designator (023) is zero, the instruction at location U is performed. If 023 is one,
tho next instruction is performed. 023 is cleared by the instruction.

5. 11.22. Jump Carry Jump to U if DO

JC

74, 16

= 1; go to NI if DO = O.

If the carry designator (00) is one, the instruction at location U is performed next. If DO is zero, the
next instruction is performed.
1.

The contents of the a-field is ignored.

2.

Performing the Jump Carry instruction does not cha"ge

5. 11.23. Jump No Carry Jump to U if DO

::1111'

JNC

0: go to NI if DO

~O.

74,17

= 1.

If the carry designator (DO) is zero, the instruction at location U is performed next. If DO is one, the
nEtxt instruction is performed.
1.

The contents of the a-field is ignored.

2..

Performing the Jump No Carry instruction does not change ~O.

5.12. Logical Instructions
The three logical operations are the Logical Inclusive OR (referred to as the Logical OR and symbolized
by iQE). the Logical Exclusive OR (symbolized by IXORU; and the Logical AND (symbolized by ~). Each
01f these instructions uses two input operands. One input operand is obtained from location U and
the other from an A-register. Table 5-1 lists the four possible combinations of the two bits from any
bit position of the two input operands and the result produced for that bit position for each of the
three basic operations.

8804 Rev. 1
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I

SPERRY UNIVAC 1100/80 Systems

I

.

Tabl. 5-1.

First Op-arand

Truth TlJbl. for Logical OR, XOR, and AND

Input Bits
Second Operand

0

OR

1
1

Output (Result) Bit
XOR

0

0

0

1
1

1
1

1

1

0

0
1

0

5-46

~

~t C.apability Processor and Storage Programmer Reference

AND
0
0

0
1

The Masked Lc)ad Upper instruction performs a compound logical operation; the contents of selected
bit pClsitions of one operand are merged with the contents of the remaining bit positions of a second
openlnd.

5. 12. 1. Logical OR I[A)

(QE]

(U) -

OR

40

A+ 1

The contents of Aa is transferred to the arithmetic section. The contents of U is transferred to the
arithrnetic section under j-field control. A 36-bit result is formed in the arithmetic section, as follows:
•

''''e result contains a 1 in each bit position for which the corresponding bit position of either
I[or both) of the input operands contains a 1.

•

'The result contains a 0 in each bit position for which the corresponding bit position of both input
operands contains a O.

The resu It is stored' in Aa + 1.

5. 12.2. Logical Exclusive OR (A)

[QE]

XOR

41

(U) - A+ 1

The c:ontents ()f Aa is transferred to the arithmetic section. The contents of U is transferred to the
arithrnetic section under j-field control. A 36-bit result is formed in the arithmetic section, as follows:
•

'The result contains a 1 in each bit position for which the corresponding bit position of either
[but not both) of the input operands contains a 1.

•

The result contains a 0 in each bit position for which the contents of the corresponding bit
position elf the input operands are both 0 or both 1.

The f'esult is stored in Aa + 1.

8804 Rev.l

SPERRY UNIVAC 1100/80 Syaems

4x4 Capability Processor and Storage Programmer ·Reference

UNIUMIIIt

5. '12.3. Logical AND (A) ~ (U) -

AND

5-46
UP'OATI LIYIL

I'AGi

42

A+1

The contents of Aa is transferred to the arithmetic section. The contents of U is transferred to the
arithmetic section under j-field control. A 36-bit result is formed in the arithmetic section, as follows:
•

The result contains a 1 in each bit position for which the corresponding bit position of both input
operands contains a 1.

•

The result contains a 0 in each bit position for which the corresponding bit position of either
(or both) of the input operands contains a O.

The result is stored in Aa + 1.

5. 12.4. Masked Load Upper [ (U) ~ (R2) ]

fQBJ [

MLU

·(A) ~ NOT (R2) ]

43
-

A+ 1

The contents of Aa and R2 are transferred to the arithmetic section. The contents of U is transferred
to the arithmetic section under j-field control. A 36-bit result is formed in the arithmetic section,
as follows:
•

The result contains a 1 in each bit position for which the corresponding bit position of the
operand from U and the operand from R2 both contain 1 bits.

•

The result contains a 1 in each bit position for which the corresponding bit position of the
operand from Aa and the ones complement of the operand from R2 both contain 1 bits.

•

The result contains 0 bits in the remaining bit positions.

The result is stored in Aa + 1.
1.

The desired value must be loaded in R2 (mask register) by an instruction preceding the Masked
Load Upper instruction.

5. 13. Miscellaneous Instructions
Each of the eight following instructions is classed as miscellaneous.

5. 13. 1. Load DR Designators Us,S.3-0 -

07, 14

Designator register:

a-

04

Bit 3 -

010

Bit 1 -

05

Bit 5 -

017

Bit 2 -

08

Bit 6 -

020

Bit

LPO

B,its 0, T, 2, 3, 5, and 6 of U are transferred to the designator register bits (see 8.2.1); 04, 05. 08.
010, 017, and 020, respectively. These are the only designator bits which can be changed by a
user program.

I

SPERRY UNIVAC 1100/80 Systems

~ Capability Processor and Storage Programmer Reference

5.13.2. Stort! DR Designators -

SPO

5-47
PAGE

UPDATI LEVIL .

07,15

Us-o; zeros - U, 7-7

I)esignatc.r register bits -

1)4 - Bit 0

012 -

Bit 4

1)5 - Bit 1

017 -

Bit 5

1)8 ... Bit 2

020 - Bit 6

1)10 ... Bit 3
020, 017, 012, 010, 08, 05, and 04 of the designator register (see 8.2.1) are transferred to bit
positi,ons 7-0 of U, respectively. The upper half of the operation location is unaffected.

5.13.3. Execute -

EX

72,10

I:xecute the instruction at U.
The P-register is incremented provided the instruction was addressed by the contents of the
P-register. The instruction at location U is transferred to the control section to replace the Execute
onstruction as 1the next instruction to be performed.

1.

~rhe

2.

-rhe remote instruction, specified by U, is always obtained from a storage location.

3.

I:xecute instructions may be cascaded; that is, the instruction in the remote location may be an
l:xecute instruction.

4.

"rhe P-register is incremented only once, when the original Execute instruction is obtaineq for
Itxecution.

5.

Generally, an interrupt cannot occur between the time an Execute instruction is started and the
instructioln (or instructions) it leads to has been completed except when an Execute instruction
leads to a repeated instruction (see 5.3·.8 and 5.6). An interrupt cannot occur between the start
I)f the Execute instruction and the completion of the initial stage of the repeated instruction. The
interrupt, however, can cause initiation of a termination stage immediately following completion
13f the initial stage or any time thereafter in order to permit the interrupt to occur.

6.

Ilf an Exec:ute instruction leads to a repeated instruction, index register incrementation should
Irtot be specified for the Execute instructions or for any indirect addressing sequence involved
~:see 5.3.S. note 6, and 5.6).

contents of the a-field are ignored.

5. 13 . 4. Executive Request -

ER

72. 11

IGenerate Executive Request interrupt
An EJtecutive nequest interrupt is generated.
1.

',~

=

Guard Mode/Storage Limits interrupt will occur if indirect addressing is specified (i
1, the
,relocation and storage suppression designator, 07 =- 0) and the operand address causes a
:storage limits violation.

8604 Rev.1

SPERRY UNIVAC 1100/80 Syatems

4x4 Capability Processor and Storage Programmer Reference

U~

2.

U~TllIVIl.

The contents of the a-field is ignored.

5,.13.5. Test and Set If (U)30

TS

73,17; a = 0

= 1, Generate Test and Set interrupt;

then 018 -

if (U)30

= 0, go to NI, if U ;;,

200,

U 36- 30; (U)29-0 unchanged.

An operand fetch (from GRS if U < 200; from storage if U ) 200) is initiated to read the operand
sllecified by the operand address. If bit 30 of the operand is zero, the next instruction is performed.
If U ) 200 and bit 30 of the operand is zero, then a 18 is written into bits 35 through 30 of the storage
operand. Bits 29 through 0 at location U are neither examined nor altered. When U < 200 no write
b,ack wiU occur.

5.13.6. Test and Set and Skip If (U)30

TSS

73,17; a = 1

= 1, go to NI; if (Ubo..= 0, skip NI, if U )

.

200, then 018 - U35 - 30; (U)29-0 unchanged .

A,n operand fetch (from GRS if U < 200; from storage if U ) 200) is initiated to read the dperand
specified by the operand address. If bit 30 of the operand is zero, the next instruction is skipped.
If bit 30 of the operand is one, the next instruction is performed. If U ) 200 and bit 30 of the operand
is zero, then 01a is written into bits 35 through 30 of the storage operand. Bits 29 through a at
location U are neither examined or altered. When U < 200 no write back will occur.

5.13.7. Test and Clear and Skip If (Ubo

TeS

73,17; 'a = 2

= 0, perform Nt; if (Ubo = 1, skip NI, if U )

200 clear (U) 35-30; (U)29-0

unch~nged.

An operand fetch (from GRS if U < 200; from storage if U ) 200) is initiated to read the operand
specified by the operand address. If bit 30 of the operand is zero, the next instruction is performed.
If bit 30 of the operand is one, the next instruction is skipped. If U ) 200 and bit 30 of the operand
is one, then bits 35 through 30 of the storage operand are cleared. Bits 29 through a at location
U are neither examined or altered. When U < 200 no write back will occur.

5.13.8. Test and Set Alternate -

TSA

73,17; a

=4

The TSA instruction is intended to allow access to data under test and set. The instruction is like
Test and Set except that bit position 14 is tested, and bits 0 through 14 are set to one. An interrupt
occurs if bit 14 is one when the test is performed. If U < 200 a, bit 14 of the GRS word is tested
as above; however, the word is not modified. This instruction is used only with 494 mode capability.

Ei. 13.9. Test and Set and Skip Alternate -

TSSA

73,17; a

=5

"he TSSA instruction is like Test and Set Alternate except that the next instruction is skipped if bit
14 is zero. The next instruction is not skipped if, bit 14 is one, rather than causing an interrupt. In
this respect, the TSSA instruction is like the Test and Set and Skip instruction. If U < 200 s• bit 14
of the GRS word is tested as above; however, the word is not modified. This instruction is used only
with 494 mode capability.

8604 Re".1

I

SPERRY UNIVAC 1100/S0 Systems

~~_~, Capability Processor and Storage Programmer Reference

5. 13. 1O. No Operation -

UIlDATE LML

5-49
'AGI

74,06

NQP

Proceed to next instruction.
The NOP instruction ensures that there is an interval between the end of the instruction that precedes
it and the start of the one that follows it.
1.

The contents of the a-field is ignored.

2.

The only effects that the values in the x-, h-, i-, and u-fields can have on the operation is the
index register incrementation obtained when x =0 and h
1, and the indirect addressing delay
introducEld when i == 1 and the relocation and storage suppression designator (07) == O. Indirect
addressing can cause a guard mode if the relative address generated from X and U does not
fall within limits on any of the bank descriptors.

=

5. 13. 11. Stc)re Register Set -

72,16

SRS

Aa c()ntains an address and count for each of two GRS areas. These areas are stored consecutively,
starting at the location specified by the operand address of the instruction, If either or both count
valUEtS are zero, no transfer occurs to the respective area(s). Relative addresses less than 2008 are
treatlEtd as storage addresses, not GRS addresses.
The ifollowing is the format of Aa for this instruction:

Are. 2
Count
363433

Area 2
Address

00

18 17 t815

2721 25 24

5. 1~1. 12. Load Register Set -

00

LRS

Area 1
Count

Area 1
Address

00
98

78

o

72,17

The format of Aa and the operation of· the instruction are like that of SRS, except that information
is tralnsferred from the location specified by the operand address to the area specified by Aa. Relative
addr'esses less than 200s are treated as storage addresses, not GRS addresses.

5.1:t 13. Test Relative Address -

TRA

72, 15

The TRA instr'uction provides a means to determine whether a specific relative address is within a
given relative addressing range. The operand address is the first word of a 4-word packet defining

ae04

Rev.1

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

U~MIIIl

UPOATlLML

5-50
'AGE

art addressing environment to be used in testing the relative address. The packet contains a
designator register, bank descriptor table pointer, four bank descriptor indexes, and E bits. in the
following format:

Designator Register

WOl'd 0

Bank Oucriptor Table Pointer

WOlrd 1

E

Word 2

BOlO

ignored

E
1

3b 34

E

ignored

BOl2

ignored

BOI 3

2

0

BOI 1

ignored

30.29

E
3

181718

12 11

o

The four E bits within the packet determine whether the BOT pointer in the packet (E == 0) or the EXEC
BOT pointer (E == 1) is to be used with the appropriate BOI to reference the respective bark descriptor.
The relative address to be tested is contained in Xa 17-0' This relative address is translated into an
absolute address within the addressing environment specified by the above packet. Relative
addresses less than 200 8 are treated as storage addresses, not GAS addresses. There.is no check
for table length violation.
To determine the order of descriptor usage during testing, the bank descriptor register (BOR) selector
designator (012) is used. When 012 == 1, the order is 1. 3, 0, 2. When 012 == 0, the order is 0,
2, 1, 3. These orders are followed regardless of 035. 012 is obtained from the current 012 in the
hardware designator register if the address for the designator register is 44 8 (U =- 44 8 ); otherwise,
012 is obtained from the designator register in the packet.
"he results of this instruction are stored in Xa and indicated by skip or no skip. If the relative address
tlBsted is within limits, the number of the bank descriptor register within whose limits the relative
address exists. is stored in Xa 34-33' and the absolute address produced is stored in Xa23-00' If the
relative address does not fall within any limits, Xa is cleared to zero and the next instruction is
executed. If the relative address tested is within limits, the write protect bit of the bank descriptor
within whose limits the relative address exists is tested. If it is zero, the next instruction is skipped;
H it is one. the next instruction is executed.
The bank descriptors which are fetched from storage are loaded, one at a time. into hardware BORa
where the limits check is done. Since these test bank descriptors are loaded into BORO, the resident
bank descriptor will be destroyed. The BORO must be returned to the original values once all the
testing is done. To do this the hardware will fetch the current BOO from storage using the current
index values and pointers in the GRS at the start of the TRA. Once the current BOO comes from
storage, it is loaded into GRS addresses 66 and 67. Then at the end of the TRA, these GRS addresses
care read up and loaded into BORO.

I

8804 ReY.1

SPEFtRY UNIVAC 1100/80 Systems
.
~ Capability Processor and Storage Programmer Reference

UP-oIIIUMISI

5. 13. 14. Increase Instructions -

XX

05; a

UPOATI lEVEL

5-61
"AGE

= 10-17

The operand s~)ecified by the operand address is transferred under j-field control to the a.rithmetic
section, increa~.ed by a value specified by the a-field control to the arithmetic section, and stored
under j-field c()ntrol in the location specified by the operand address; the operation is performed
under storage lock (test and set). If the initial operand or the result is zero, the next instruction is
executed; othelwise, the next instruction is skipped. If 077 + 1 (per j transfer) is not equal to zero,
a skip does n01t occur. The following values may be selected by the a-field:
!!"nemonic~

!::!!!!!!

increase value

INC

10

+1

DEC

11

-1

INC2

12

+2

DEC2

13

-2

ENZ

14-17

o (-0

is changed to +0 for sign-extended
operands)

The inlcrease and zero test operations depend on the j-field values to some degree. Certain j-field
valuesi extend or interpret the sign of the operand (W, XH 1-XH2, T1-T3); for these values, the increase
is a Olr'les complement, sign-extended operation, and either positive zero or negative zero satisfies
the zero test. "he remaining j-field values do not consider the sign of the operand (H 1-H2, a 1-04,
S 1-5«;); for these values, the increase is a twos complement, field-size operation, and only positive
zero satisfies the zero test.

5. 14. Byte

In~jtructio.ns

This c:lass of instructions is designed to permit transference. translation, comparison, testing, and
arithmetic computation of data in the form of predetermined bit patterns (e,g., half words, third words,
QuartEtr words, and sixth words) referred to as bytes.
There are a totelll of 15 distinct instructions that perform the various multiword (byte string) operations
noted above. 'rhese instructions may be arranged under three functional groups:
1.

Instructions that involve byte transfers and manipulations between one storage location and
2lnother.

2.

Instructions that permit the mutual transference and manipulation of data among storage and
"arious control and arithmetic registers.

3.

Instructiol's that perform decimal arithmetic addition and subtraction operations.

Thesel instructions operate on strings of characters (byte strings) under control of J-registers and
stagir1lg registers. The J-registers are implicitly addressed by the instruction and are used to index
throu.~h the byte strings. One J-register is ·provided for each of four possible byte strings used by
an ins~truction. These registers. JO through J3, are located in GRS addresses 106 8 - 1118 for user
prognlms, or 1:26 8 - 131 8 for Executive programs. Figure 5-1 shows the J-register format, including
the function of the various fields.
Stagitr"lg and c()ntrol information necessary to handle the byte .strings are held in staging registers.
Three R-registers (R 3 , R4, and Rs of GRS), designated as SR 1, SR2, and SR3, respectively, are used

8804 Rev.1

SPERRY UNIVAC 1100/80 System,

~

4x4 Capability Processor and Storage Programmer Reference

5-62

II'"

for this purpose. The information stored in these registers provides the capability of interrupting the
performance of certain instructions. The actual information stored may vary from one instruction to
tho next. See the individual instructions for use of the staging registers.
Byte string addressing is accomplished through use of the instruction's u-field, index registers
sp,ecified by the x-field of the instruction, and the Ow (offset in words) field of the appropriate
J-rQgister. The address of byte string 0 (designated SJO), for example, is given by summing the
contents of u, Xx, and the Ow field of JO (U + Xx + JO Ow)' The address of byte string 1 (SJ 1) would
be given by (U + Xx + 1 + J 1Ow), etc. A particular byte within the word of a byte string is pointed
to by the Ob-field (offset in bytes) of the J-register. Byte strings may begin on any word-fraction
boundary compatible with byte size; i.e., strings of 6-bit bytes must be located on sixth-word
boundaries, 9-bit bytes on Quarter-word boundaries, etc. The length of a byte string, in number of
bytes, is stored in staging register SR3. The length of byte string 0 (designated WO) is stored in bit
locations 35-27 of SR3, the length of byte string 1 (W 1) in bit locations 26-18 of SR3, and the length
of byte string 2 (W2) in bit locations 17-9 of SR3. Any, aU, or none of these values may apply for
a particular instruction.

Iw

Ib
21

31 34 33 32 31

20 18

Ow
17

Ob
3

2

0

Function
J-register modifier bit; used with the h-bit of the instruction to control J
(1== 1) or X(I==O) register modification.
M

Mode 6/9-bit modulus: 0 == 9-bit mode (ASCJI)
-

w

Width 6-12 or 9-18 bits:

6-bit mode (Fieldata)

0 - 6/9 bits
1 -

E

a)

12/1 8 bits

for 33,03
E - Translate:

o ==

translation

1 - no translation
b)

for all other byte instructions E must be zero.

c)

for character addressing (non-byte instructions):

o ==

no sign. extension

1 - sign extension

I

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SPERRY UNIVAC 1100/80 Systems

5-63

~~___ ~ Capability Processor and Storage Programmer Reference

Iw

Increment in words

Ib

Increment in bytes

Ow

Offset in words

Ob

Offset in bytes

UPDATI LIYIL

!tACH

The dilrection in which each instruction progresses through its operand byte strings is specified per
instruc:tion in the J-register. The increment word (Iw) and increment byte (Ib) fields of the J-register
are aSled durinG' instruction execution to update the effective byte address. The effective value of
Iw and! Ib may be either! 1, the actual value loaded into the register by the program depends on the
byte letngth being used. The value of Iw must be ! 0 and have the same sign as lb. Therefore, Iw
is effe,ctively Ib sign-extended (Iwb).
Table 15-2 gives, the values of Iwb for

+ 1 and -1

effective increments for 6, 9, 12, and la-bit bytes.

Some of the extended-sequence byte-manipulation instructions are designed to permit their
interruption dU"ing their execution. However. interrupts are accepted only following the store or
compslre phase of the instruction. As the instruction comoletes each of these phases, a check is made
to see if an interrupt is waiting to be processed. If an interrupt request is current, it is acknowledged
and processed immediately. When the instruction is again activated, the interrupt control bits are
decodred, and control is returned to the appropriate phase of execution. There are three bits (29-27)
in SR 1 that are available for interrupt control. thus providing up to 7 types of interrupt classification
within an instruction.

F:or

~

Byte Length
of
6 bits

6
9
9
12
12
Ul
18

And an Effective Increment of

The Value of Ib Must be

+1
- 1
+1
- 1
+1

+1
- 1
+2
-2
+2
-2
+4
=4

- 1
+1
- 1

There are seven restrictions on byte- addressing that should be noted:
1.

"he result of an instruction performed on overlapping byte strings is undefined.

2.

~~ byte string may not wrap around its J-register offset field; i.e., Ow cannot be incremented
through itlS maximum value of 77777 ~ or decremented through its minimum value of OOOOOs·

3.

Normal acldress limits violation detection and interrupt will be in effect.

4.

~,II

5.

rhe h-field of all byte instructions must be set to 1. This is set automatically by the assembler
~"hen a byte mnemonic is encountered.

instruc:tions utilizing the J-registers must have their operands located in storage.

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

~

4x4 Capability Processor and Storage Programmer Reference

.

~e

5-54
UfI'OATI LIYIL

IIAQI

6.

The I-field of all J-registers used must

set to 1.

7.

The E-field of all J-registers used must be set to 0 for all byte instructions except 33, 03.

The 33, 03-04; 33,10-11; 33,14-15; and 37,06-07 instructions will store a 7-bit status word in
SR3,7_9 either upon successful completion of the instruction or upon detection of an error condition
which prevents completion of the instruction. A definition of the 7 status bits is contained in Table
5-3.
Successful completion of an instruction will result in the storing of an all-zero word, except for the
cases of a decimal-add overflow (37, 06-07) or a missing mantissa field (33, 14-15) or roundup
status (33, 16-17).
When dealing with 9-bit bytes, the ASCII format shall be accepted and only ASCII is generated when
usttd for operations involving signed numeric-byte strings. An ASCII byte is the eight lowest-order
bits in a quarter word. The byte is divided into a 4-bit zone and a 4-bit digit; the zone is the most
siglnificant part of the byte. The sign convention adopted for a byte string is called "trailing-included
sigln format." i.e., the sign of the byte string is contained in the zone (Z) portion of the least significant
byte.
Th'sre are three exceptions to the "trailing-included sign convention". The Byte-ta-Single Floating
Conversion (fj == 33, 14) and Byte-ta-Double Floating Conversion (fj == 33, 15) instructions use a
seloarate non-included sign byte with the byte string. This byte is simply a "+" or "_It character.
Table 5-4 gives the binary coding for the plus and minus signs to be used in ASCII and Fieldata
coding. The hardware checks for a minus sign in arithmetic operations. If the sign of the arithmetic
operations is not minus, then the result is assumed to be plus. The types of signs accepted and
generated by each of the byte-manipulation instructions are listed in the table.

5. 14. 1. Byte Move -

8M

33,00

Transfer W 1 bytes from source string to receiving string. Truncate or fill.
The BM instruction transfers 1-.1 1 bytes from a source string starting at address SJO to a receiving
string starting at address SJ 1. The byte string at address SJO contains WO bytes; the byte string
at address SJ 1 contains W 1 bytes. If W 1 is less than WO, the move will be truncated when W 1
bytes have been transferred. If W 1 is greater than WO, then (W 1-WO) fill bytes will be added in
the trailing positions of the byte string located at address SJ 1. The contents of SR2'7-O are used
as the fill byte.
When byte strings of different byte size are transferred, the receiving string determines how many
bits from each source string byte will be accepted. For example, if SJ 1 is in the 9-bit mode and SJO
is in 6-bit mode, the three leading bits of the SJ 1 byte are made zero. If SJ 1 is in the 6-bit mode
and SJO is in the 9-bit mode, only the six least significant bits of the SJO byte are accepted, the rest
being lost.

I~! ..!

I~

I: •
S:.D

Tab/II 6-3. Bytll Status Word

I

Status
Bit
Bit 0 Set

Type of Error
format Error

Instruction
33-10,11
31-08,01
33-14,16

Bit 1 Set

Bit 2 Set

Underflow

Overflow

33-14
33-16
33-14,16
33-10
33-11
31-08.01
33-14
33-16
33-14,16
33-14,16

Bit 3 Set

Decimal Point Error

Bit 4 Set

No Significant Character
found

33-14.16

Bit 6 Set

Exponent Found or Byte
Roundup
Mode Error

Bit 1 Set

Byte Compare

33-14,16
33-16.11
33-10.11
33-.14.16
33-03.04

Bit 5 Set

f;

Condition Detected
Byte not digit or blank (checked on aU but last byte) or least significant 4 bits of last byte
greater than 9.
Byte not digit (checked on aU but first byte) or least lignificant 4 bits or first bytes greater
than 9.
Two signa in string not separated by at least one non-blank character.
a.
b.
Two decimal points in mantissa
Significant character not found.
c.
d.
Illegal character in string.
Illegal character in exponent.
e.
Decimal point last character and no digit in string.
l
Magnitude 01 input too small to repr~sent in single-precision floating-point number.
Magnitude of input too small to represent in double-precision floating-point number.
Exponent negative and power of ten too small to represent double-precision floating-point
format.
Magnitude of input too large to represent in 35 binary bits.
Magnitude of input too large to represent in 11 binary bits.
Decimal-add overflow.
Magnitude of input too large to repreunt in single-precision floating-point.
Magnitude of input too large to represent in double-precision floating-point.
Mantissa interpreted as integer too large to represent in 60 binary bits.
a.
Decimal point count greater than 31.
b.
Two decimal points in mantissa.
c.
Decimal point last character and no digit in string.
a.
Bits 0, 3 let and significant character not read yet.
b.
Mantissa field does not contain at least one digit (note that a blank following a decimal
point is considered a digit).
String does not contain at least one nonblank and nonsign character.
c.
a.
Bits 0, " 2. 3 set and exponent field detected.
b.
Byte 10 (33,16) or 19 (33.11) is greater than four.
6- or 9-bit mode not selected fN bit) on one of the following instructions.

fn

><;R
J:Io:u

O~

&»

"DC
QJZ

CT_.<

~~
-g ....
ag
n'
CDOD

UtO
Uta)
I

~l

&»-

::J3

~.

(J)

5
Ql

CO
CD
"'D

a
co
....
3
QJ

3

CD

....

-

::0
CD
CD
CD
::J

....

n

CD

c
~

a
i

Set if non-compare encountered during instruction.

i

MUI

I

(JI

UI

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

~

4x4 Capability Processor and Storage Programmer Reference

5-66
UP'DATI LIVIL

"AM

B01th the values W 1 and WO are reduced by one following each byte move. This instruction is
terminated when the value of W 1 equals zero (W 1 = 0).

1.

This instruction is interruptible after each store operation.

2.

The Iwb fields in JO and J 1 must be loaded with effective values of
and width.

3.

The desired fill byte must be loaded in SR2,7-O'

:!:

1, depending on mode

T.bI. 5-4. Byte String Sign Codes

Sign Conventions

+

Character Code Formats
1. ASCII
2. Fieldate

3. ASCII
4. Fieldat.

1010
11
00101011
100010

Included (Zone ponion)
Included
Separated (Entire byte)
Separate

5. 14.2. Byte Move With Translate -

BMT

1011
10
00101101
100001

33,01

Translate and transfer W 1 bytes from source string to receiving string. Truncate or fill.
The BMT instruction translates and transfers W 1 byte from byte string SJO to byte string SJ 1. The
translation and transfer process uses byte string SJ2 as a translation table for byte string SJO. That
is, each byte of the string SJO is used as an index to a byte in string SJ2. The SJ2 byte thus addressed
is transferred to the byte string SJ 1. If the value of W 1 is less than WO, the transfer terminates when
LI1 bytes have been processed. If the value W 1 is greater than WO, then (W 1-W0) translated fill
bytes are placed in the trailing positions of SJ 1. The contents of SR2'7-O are used to index the fill
byte.
When byte strings of different byte size are transferred, the receiving string determines how many
bilts from each byte of the source string will be accepted. If SJ 1 is in·the 6-bit mode and SJ2 is
inl the 9-bit mode, only the six least significant bits of SJ2 byte are accepted, the rest being '9st.
The translation table pointer register, J2, must be in the 9- or 18-bit mode. This restriction does
n40t prevent Fieldata translations, but it requires that the translation table bytes are either 9- or 18-bit
entries. Both the values W 1 and WO are decreased by one following each byte translation. When
the value of W 1 is equal to zero (W" - 0), the instruction is t~rminated.

=

The fill byte referenced by SR2 17-O must be preloaded left shifted one bit if MW 0 in JO (see Figure
5,-1), indicating the source string is 9-bit bytes, and must be preloaded left shifted two bits if BL =1 in JO, indicating the source string is 18-bit bytes.
1.

This instruction is interruptible after each byte store operation.

2.

The Iwb fields of JO and J 1 must be loaded with effective values of
and width.

!

1, depending on mode

I

8804 Aev.1

4x4 Capability Processor and Storage Programmer Reference
-------~
peRIRY UNIVAC 1100/80 Systems

IJII-WMIIR

5. 14.:~. Byte Translate and Compare -

BTC

33,03

Optionally, translate and compare WO bytes from SJO with LJ 1 bytes from SJ 1; terminate the
instruction on not equal or when both WO and W 1 equal zero; when:
(A)

>

>

SJ 1

(A)

== 0;

string SJO

==

SJ 1

(A)

<

0; string SJO

<

SJ 1

0; string SJO

The B-rC instruc:tion optionally translates and compares WO bytes of string SJO with the optionally
transl~lted W 1 bytes of string SJ 1. String SJ2, starting at address (u+(X+2}+J2 ow)' is used as the
translcltion table for strings SJO and SJ 1 when the corresponding E-bit is zero. A one in the
corresponding E-bit inhibits translation. Thus. a translation can be made on either or both strings.
If no translation is desired, the Byte Compare instruction (33,04) should be used. The comparison
is madle by subt.racting the optionally translated SJ 1 byte from the optionally translated SJO byte and
storin,~ the result in register Aa. If the contents of Aa is zero (Aa == 0), then the next pair of bytes
are tralnslated or not, according to the content of (E) and compared. If the contents of Aa is not zero
(Aa :. (», or if both of th'e strings SJO and SJ 1 have a value of W 1 == 0 and WO == 0, then the instruction
is terminated. The values of W 1 and WO are always decreased by one, and the JO- and J 1-registers
are inlcreased c)r decreased by one, depending upon the direction addressed.
When the instruction termination occurs, the relative value of an SJO string in respect to the value
of an SJ 1 string may be determined as follows:
•

I~f the contents of the Aa-register is positive (A
sitring (after optional translations).

>

•

I'f the contents of the Aa-register is zero (Aa
(,after optional translations).

0), then the SJO string is equal to the SJ 1 string

•

If the contents of "the Aa-register is negative (Aa
!itring (after optional translations).

1.

If either S1tring SJO or string SJ 1 is depleted before the other, trailing fill characters are added
to the sh()rter string.

2.

The fill byte for string SJO is contained in SA 1 ,7-0 and the fill byte for string SJ 1 is contained
in SA2 3 5-.t8'

3.

'rhe fill bytes in SA2 must be preloaded left shifted one bit if MW == 0 in JO indicating the source
lltring is 9-bit bytes and must be preloaded left shifted two bits if MW - 1 in JO indicating the
:Iource string is 18-4lit bytes (see Figure 5-1).

4.

'This instruction is interruptible after each test.

5.

'The Iwb-:fields of JO and J 1 must be loaded with effective values of
,and width (see Table 5-2).

6.

If the byte strings do not compare, then bit '1 of the byte status word is set (see Table 5-3).

=:

0), then the SJO string is greater than the SJ 1

< 0), then the

SJO string is less than the SJ 1

:!:

1, depending on mode

.....

880.. Rev.1

SPERRY UNIVAC 1100/80 Systems

~

4x4 Capability Processor and Storage Programmer Reference

5. '14.4. Byte Compare -

Be

5-58
UfIOATI LIVIL

PAGI

33,04

Compare WO bytes from string SJO with W 1 bytes from string SJ 1; terminate instruction on
not eQual or when both WO and W 1 are zero.
The corresponding string SJ 1 byte is subtracted from the string SJO byte, the result is stored in Aa,
and a zero test is performed. The value of W 1 and WO are always decreased by one, and the JOand J 1-registers are updated. If the contents of the Aa is zero, the next pair of bytes are tested. If
the value of Aa is nonzero, or both W 1 and WO are zero (i.e., the longer string has been depleted),
the BC instruction is terminated.
When the instruction termination occurs, the relative value of an SJO string in respect to the value
of an SJ 1 string may be determined as follows:

>

•

If the contents of the Aa-register is positive (Aa
SJ 1 string.

•

If the contents of the Aa-register is zero (Aa

•

If the contents of the Aa-register is negative (Aa < 0), then the SJO string is less than the SJ 1
string.

1.

If either string SJO or string SJ 1 are depleted before the other, trailing fill characters are added
to the shorter string. The fill byte for the string SJO is contained in SR2 17-o and the fill byte
for string SJ 1 is contained in SR2 35_ 18•

2.

This instruction is interruptible ,after each compare.

3.

The Iwb-fields of JO and J 1 must be loaded with effective values of ! 1, depending on mode
and width (see Table 5-2).

4.

If the byte strings do not compare, then bit 7 of the byte status word is set (see Table 5-3).

5. 14.5. Edit -

EDIT

0), then the SJQ- string is greater than the

= 0), then the SJO string is equal to the SJ 1 string.

33,07

Edit byte string SJO and transfer to string SJ 1 under the control of string SJ2.
A source byte string (string SJO) specified by the u-field of the Edit instruction, using registers Xx
and JO, is edited into a receiving byte string (string SJ 1) specified by the u-field of the instruction,
X(x+ 1), and J 1. Specific editing commands are coded within a control byte string (string SJ2) whose
location is designated by the J2 register, the u-field of the instruction, and the register X(x+2). The
control stream commands are designed to duplicate all of the functions of the P1CTURE clause of the
COBOL compiler. Therefore, the main use of the Edit instruction is to make the appropriate editing
changes to a numeric byte string for output to the printer. For example, blanking-out the leading
zeros, adding a "S· character or the appropriate sign code, inserting commas or a decimal point within
the number, or appending a descriptor word such as "CR· or "DB.
It

The following information describes and summarizes the basic operational steps of the Edit
instruction.
A typical field in the control stream (string SJ2) will contain the following elements:

Function Byte
(Table 5-5)

Skip Count
(optional)

Subfunction
(Table 5-6)

Subfunction
(or Text)

Flag Byte
(End-of-Field)

8004 Rev.1
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5-59

~ Capability Processor and Storage Programmer Reference

~AG.

The function byte specifies control information for the whole field following it (see Table 5-5). One
functi()n of this byte is to specify whether there is a skip count or not. If there is a skip count, it is
given in the next byte. The rest of the field contains a series of subfunction bytes and text bytes.
The· sllbfunctioln bytes are those described in Table 5-6 and specify operations to be performed as
the source string is edited into the receiving string. The text bytes are bytes similar to the soure'!
string bytes which may be edited into the receiving string. The last subfunction byte in the field is
the flag byte which establishes the end-of-file action. The flag byte may be followed by another field
starting with a function byte, or a second flag byte indicating termination of the Edit instruction.
Operation of the Edit instruction is based on performing a sequence of field "microprograms" defined
by the control s'tring. A field scan is established when the instruction is initiated or when the initiation
of a nletw field ctccurs and results in certain "function initiation" actions based on the contents of the
functic:m byte. The first control stream byte must be the function byte. It will be stored in staging
regist.!tr SR 12 8-.18' If a skip count is required. as indicated by the function byte, the second control
strean1 byte contains the skip count and is transferred from the control stream to staging register
SR 1 , .,'-9' Next. the J 1-register is saved in J3. This saves the position of ·the first byte of the receiving
string for use iit the "blank-if-zero" command (bit 0 of function byte is set) is required when the end
of the field is Etncountered. Finally, the skip count (SR 1 ,7- 9 ) is used to skip the indicated number
of bytll:ts in the I'eceiving string. This is done by updating J 1 position Owb as many times as the value
in SR 117- 9 (skip count).
When the function initiation actions are completed for this field, the first subfunction byte is
transferred frorn the control stream to SR 18-0 for interrogation. The subfunction byte is transferred
from the control stream to SR 18-0 for interrogation. The subfunction and text bytes are sequentially
interrclgated until a "flag" (end-of-field) subfunction byte is encountered. At this point the end-of-field
. actio"l is completed and another function is initiated. This proceS$ continues until two "flag" bytes
are encounterEtd together indicating termination of the instruction. A detailed description of the
function byte, ~subfunction, and text bytes follows.

5. 14.5. 1. Function Byte
The irlterpretation of the function byte is given in Table 5-5. A more detailed descripton of each bit
positi1on follows:

Function Byte

!Bit

0

-1

5
4

No Skip Count
Fixed Sign
Fixed Symbol
Sign - Minus or Fill
Edit - No Sign Action
Normal Edit

Skip Count Follows
Floating Sign
Floating Symbol
Sign - Minus or Plus
Sign Action on Edit
Blank if Zero

3
2
1

0

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

Ull-NUMIIR

4x4 Capability Processor and Storage Programmer Reference

5-60
!tAU

•

Function Bit 5 - A skip mechanism is included tha"t allows the programmer the option of ignoring
a series of bytes in the receiving string. "The skip count is placed in position SR 1 17- 9 during
function initiation and specifies the number of bytes to be skipped in the receiving string before
the first subfunction byte is interrogated. The maximum value allowed is 63,0 for either the
6- or 9-bit mode.

•

Function Bit 4 - If fixed sign is indicated, an appropriate sign byte (as specified by function bit
2) is placed in the receivif'lg string position specified by SA2 3S _ l8 ' SA2 35_ 18 must be loaded
by the subfunction "sign-position indicator" discussed in 5.14.5.2. If floating sign is indicated,
an appropriate sign byte is placed in the receiving string position specified by SA2,7-O'
SR2 ,7-O is loaded by the subfunctions ttdigit select" or "significance start indicator" as discussed
in 5. 14.5.2. In either case, a fill byte is transferred to the receiving string where the sign will
be. The sign bytes are specified by the programmer in SR3 and are transferred to the receiving
string when a "flag" subfunction byte is interrogated (end-of-field action). This bit has no
meaning unless function bit 2 (sign action on edit) is set to 1.

•

Function Bit 3 - If this bit is a 1 bit, the symbol specified by the programmer in SR3s-o is
transferrred to the receiving string at the position specified by SR2 17-o. Position SR2 17-o is
loaded the same way as for "froating sign" above. If both function bits 3 and 4 are set to one,
the floating sign will be inserted and the floating symbol ignored. As with the sign codes, the
symbol is actually inserted during end-of-field action. If function bit 3 is a zero there is no symbol
inserted during end-of-field action. A symbol may still be inserted into the receiving string
during subfunction interrogation with a "symbol-position indicator" subfunction (described in
5.14.5.2).

•

Function Bit 2 - If function bit 2 is a 0, the sign code inserted into the receiving string is either
a minus or a fill, as appropriate. If function bit 2 is a 1 bit, the sign code is either a minus or
a plus. The plus, minus, and fill bytes are specified by the programmer in SR3 ,7_9 , SR3 26-18'
or SR3 3 5-27' respectively. This bit has no meaning unless function bit 1 (sign action on edit)
is set to one.

•

Function BIt 1 - U function bit 1 is a 1, the sign action indicated by bits 4, 2, and the sign of
the source string is taken (i.e., a plus, minus, or fill byte is inserted into the receiving string). If
bit 1 is zero, no plus or minus bytes are inserted into the receiving string. The only effect bit
4 (floating sign) would have is to insert a fill byte in the position where the floating sign byte
should be.

•

Function Bit 0 - The programmer has the option of leaving an all-zero receiving field or replacing
it with fill bytes. The field is considered to be all-zero until a nonzero byte has been transferred
from the source string by a "digit select" subfunction. Position SR 13 1 is set to one when the
first nonzero digit is transferred. SR131 is not set to one by any subfunction other than "digit
select." The entire receiving string field is replaced with fill bytes during end-of-field action (see
"flag" subfunction in 5.14.5.2) if function bit 0 and SR 131 are both set to 1. The start and end
of the field are indicated by J3 (loaded during function initiation) and J 1, respectively.

5.14.5.2. Subfunction Byte
lne interpretation of the subfunction byte is given in Table 5-6 and discussed in the following
paragraphs.

860.. Rev. 1

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SPERRY UNIVAC 1100/80 Systems

~~ ___ ~Capability Processor and Storage Programmer Reference

Tabl. 5-8. $ubfunction Byts Intsrprstllion

Byte
000
000
'000
1000
000
000
000

000
101
100
111
111
101
111

011
111
110
110
010
001
111

Subfunction
Pass Byte
Significance Start Indicator
Digit Select
Symbol Position Indicator
Sign Position Indicator
Trailing Text Start Indicator
Flag (End-of-Field)

I

Fieldata Symbol

#
\
&
c

. (apostrophe)
(

=

.

•

PI!lSS Byte - If the subfunction of the control stream byte is a "pass byte," the byte currently
pf)inted at by the source field pointer is transferred to the receiving string intact.

•

Siignificance Start Indicator - If the subfunction of the control stream is a "significance start
b'(te," the "significance trigger" SR 134 is set to one. Also, if either floating sign (function bit 4
SEtt) or a filoating symbol (function bit 3 set) will be required, then the receiving field pointer,
J1-registel', is stored in SR2 17-1J' and a fill byte SR3 3S_27 is inserted in the receiving field. This
fill byte is ,'eplaced by the appropriate sign byte in end-of-field processing as indicated by the
fUlnction byte bit settings. If the "significant trigger" has already been set to one, this byte is
ignored.

•

Digit Select - If the subfunction of the control stream is a "digit select byte," the byte currentJy
pl)inted ~t by the source field pointer and the significance trigger are examined, according to
the following criteria:
1"

If the significance trigger is off, and the source byte has a zero digit portion, the receiving
field will have a fill character (SR3 35 _27) inserted into it.

2..

If the significance trigger is off and the source byte is not a zero,
a.

the significance trigger is set on, and

b.

if either floating sign or floating symbol will be required, the receiving field pointer
(J 1) is stored in SR2 17-1J' and a fill byte, (SR3 3 8-27) is inserted in the receiving string.
This fill byte is replaced by the appropriate sign byte in end-of-field processing as
indicated by the function byte bit settings. The receiving field pointer (J 1) is
incremented. and

c.

the source byte is transferred to the receiving string.

3"

If the significance trigger is "on," then the source byte is transferred to-the receiving field.

4"

If this is the first nonzero digit to be transferred from the source string, the C bit, SR 131
is set to one for use when interrogating the "blank-if-zero" function bit in end-of-field
processing.

5"

The appropriate zone code, as prescribed by the receiving string pointer (J 1), is always
written into the receiving string.

An exception to the "digit-select" transmission exists if the zone portion of the byte is negative
sign (sign c)verpunch). In this case, the "N" bit is turned "on· (SR 132) and the negative sign bits
alre replacttd by the appropriate zone code.
'

8e04 Rev.1

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4x4 Capability Processor and Storage Programmer Reference

UNtUMIIII

5-62
flAGI

•

Symbol Position Indicator - If the subfunction of the control stream is a "symbol position
indicator," the symbol byte (SR3 s-o) is stored in the receiving field. The setting of function bit
3 does not affect the operation of this subfunction byte.

•

Sign Position Indicator - If the subfunction of the control stream is a "sign position indicator."
the receiving field poielter, contained in the J 1-register, is copied into the fixed-sign position
pointer (SR2 36-1S)' and the fill character (SR3 36 _27) is transmitted to the receiving field. This
fill byte is replaced by the appropriate sign byte in end-of-field processing as indicated by the
function byte bit settings. This subfunction byte must be used to indicate the position of the
fixed sign if the function bit 4 is 0 (fixed sign).

•

Trailing Text Start Indicator -If the subfunction of the control stream is a "trailing text start" byte,
the trailing text trigger SR 133 is set to one. If a negative sign has been detected in the source
string scan (SR 132 set to one), any text information encountered in the control string is now
transferred to the receiving string. If SR 132 equals zero, fill bytes (SR3 35_27) are transferred to
the receiving field rather than the text bytes.

•

Flag Byte (End-of-Field) - If the subfunction of the control stream is a "flag" byte, then the
end-of-field action will be established. At this point the appropriate sign insertion and
·blank-if-zero· command actions are done as indicated by the function byte. The net control
stream byte is either a function byte starting a new field or another flag byte terminating the
Edit instruction.

If the subfunction of the control stream is none of the subfunction bytes of Table 5-6, it is assumed
to be a text byte. If either SR1 33 and SR1 32 are set (see Table 5-7), or SR1 34 is set and SR1 33 is
not set. the text will' be transferred to the receiving field. In all other cases, the fill byte (SR3 36-27)
will be transferred to the, receiving field.
A summary of staging register (SR 1-SR3) and J-register (JO-J3) usage are given in Table 5-7.
1.

The Iwb-fields of JO,J 1, and J2 must be loaded with effective values of
and width (see Table 5-2).

2.

SR3 must be loaded with the desired codes.

3.

This instruction is interruptible.

+ 1, depending on mode

I~I ,r
~

!II

Tablll 6-7. Summary of Staging Rsgistllr and J-RlJgistlJr Filllcis

Field

Position

Function

f;
cn

x"Q
~m
::u

CMP (Complement Mode)
5T (Significance Trigger)
T (Trailing Text Trigger)
N (Negative Bit)
C (Control Bit)

SR1 36
5R1 34
5R133
5R1 32
SR1 31

l (Skip Bit)
I (Interrupt Bits)
Function
Skip Count
5ubfunction
Fixed-Position Pointer

SR1 30 (BT5)
5R 1 2 9-21 (OT6-8)
5R1 26-18 (BS2)
SR 1 11- 9 (053)
5R18-O (BS4)
SR2 36- 18 (OHO)

Floating-Position Pointer

Fill Byte
Negative-Sign Byte
Plus-Sign Byte
Symbol Byte
Source Pointer
Receiving Pointer
Control Pointer
Start-of-Field Pointer

(BTO)
(BTl)
(BT2)
(OT3)
(OT4)

SR2 11-O (OH 1)
SR3 36- 21 (BBO)
5R3 28-18 (BB 1)
5R3 11_9 (BB2)
SR3 8-o (BB3)

JO
J1

J2
J3

No complement if 0, complement if 1.
Set to 1 if the control byte is a "significant start byte."
Set to 1 when a trailing text start indicator has been detected.
Set to 1 when a negative sign has been detected.
Set to 1 when the first nonzero digit is transferred from the source string
by the "digit select" subfunction.
Set to 1 if a skip is in progress.
Controls return after instruction interrupt.
Contains active Edit field function.


5 and status after five bytes

Eo are not transferred to

storage on input

E3 to Eo are transfered to the device on output (valid data)

o

Th... bit positions set to zeto by hardware on input and are ignored on output.

.........

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SPERRY UNIVAC 1100/10 SystemS

4x4 Capability Processor and Storage Programmer Reference

36-Bit Format C - Forward Operation

34

32

30

28

2.,

24

22

20

18

18

14

12

10

8

8

4

2

0

34

32

30

28

28

24

22

20

18

18

14

12

10

8

.,

4

2

0

22

20

18

18

14

12

10

8

8

4

2,

0

20

18

18

14

12

10

8

e

4

2

0

Data count .. 9

34

32

30

28

28

24

34

32

30

28

28

24

s~

Data count .. 4

o

Addtwl Sp«ill«J by CCW2

Data chained to data count .. 9

TheM bit positiOM ......t to zero by h.rdw.... on input .nd ignored on output.

ael04 Rev.1
UNtUMIIR

I ~3

I
.LE
Capability Processor and Storage Programmer Reference
SPERRY UNIVAC 1100/80 Systems

"AGE

36-Bit .Format C - Forward Operation

:34

32

30

34

32

30

28

28

24

24

22

20

18

18

18

14

12

10

8

14

12

10

8

$ttJf'6gt1 Add,.... $P«#fi«/ by CCW2

Dati' count

o

=-

6

Data chained to data count

==

4

Thnl bit poaitloM at. set to zero by hardware en input and ignored on output.

8

4

..

2

o

.........

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SPERRY UNIVAC 1100/80 SyMema

4x4 Capability Processor and Storage Programmer Reference

UPOATI t.ML

6. '17. Subchannel Expansion Feature and Channel Base Register
As described in 6.2.2 and 6.3.1, the subchannel expansion feature enables the channel to. maintain
the control words for the four or eight (depending on the option) most recently active subchannels
in the channel while storing the control words of the remaining 120 or 124 subchannels in main
storage. Four storage addresses per subchannel and 512 addresses per channel must be reserved
for each channel with the subchannel expansion feature. These addresses are a hardware scratch
pad and are for hardware use only and should not be interrogated or changed by software except
during initialization or error recovery. During system initialization, the software must initialize these
addresses by setting equal to 1 ,6 bits 24-27 of every fourth address (each address with bits 0 and
1 equal to 0). The format of the control words held in storage is shown in Table 6-15.
If the mode bits 27-24 - 0001 2 , all four words are not used. All other values of the mode bits
indicate a hardware fault.
Each channel that has the subct1annel expansion feature has a channel base register that consists
of 15 bits. The channel base register specifies the locati,on of the 5 12 addresses that are the
channel's scratch pad. The channel base register provides bits 09 through 23 of the storage
addresses that are used when swapping subchannel c.ontrol words between main storage and the
channel.

6. 18. Interrupt Mask Register
The interrupt mask register is loaded with the contents of bits 36-71 of the CAW during an LCR
instruction that has bit 0 of the CAW set. One interrupt mask register is provided in each IOU. This
register provides the capability of determining which channel modules are allowed to present
communications or noncommunications interrupts. It also provides a means of selecting to which
Cf'U or CPUs the interrupts are to be sent. The register is divided into four bytes. Two bytes for
each CPU. These two bytes are then separated into communications or noncommunications
in1terrupts. The interrupt mask register has the format shown in Table 6-1 6. A set bit suppresses
in'terrupts of the specified type from the corresponding channel 'module to the corresponding CPU;
i.e., a one bit in position 39 suppresses the reporting of noncommunications interrupts on channel
m,odule 3 to CPU O. If bit position 57 is also set. the reporting of noncommunications interrupts on
channel module 3 is completely suppressed. An interrupt that is completely suppressed will be
reported when either of the corresponding mask bits is later changed to O. Any interrupts that are
currently being presented to the CPU when an LCR instruction is received will be reported before
the interrupt mask takes effect. In a unit CPU system, software must mask out both communications
and noncommunications interrupts to the nonexistent CPU during system initialization and each time
.
the LCR instruction is used.

I.

8804 Rev.1

SPEFtRV UNIVAC 1100/80 Systems

~ Capability Processor and Storage Programmer Reference

UP-NUMIM

Tabls 6- 15. Scratch Pad Formats for Subchann" Expansion Feature

[u':
35

~:::

I
32 31

[U~d
35

28 27

I,____

F
_a_gs ~I
____

3231

35

3231

o

24 23

C_cw
___

__

2423

I~_U_:_~_t ~

Fo_FI_:;_:_t__

__

2019

_____________
D_at_._c_o_u_n_t____________

~
o

18 15

Device

.;Jot
Used

[

Data Addres.

Modo

Next CCW Addre..

Addre••

,--------------~--------------------------------------------------~
2423
o
Not Used

[
35

, - - - - - - -o
J=ormat above for: Mode Bits 27-24 == 0010 2 or 10002 or 1001 2 or 1010 2 or 1100 2

@I
35

3231

@I
Used

35

Device
Mode
2827

323'J

Not Used

Address
2423

0

18 15

Subchannel
Device StatuI

3231

@I
[
31

Not
Used

Data Count

StatuI
2423

0

18 115

Device
Next CCW Addre..

Add .....

0

2423

Not Used

0

35

Format above for: Mode Bits 27-24

:II

0000 2 or 00.112

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

UPDATI LIVIL

Processors 1 and 3
Bit Positions of the
CAW

71 70 69 68 67 66 65 64 63

Channel Module
Number

*

7

6

5

4

3

2

1

0

62 61 60 59 58 57 56 55 54

*

7

Communications

Interrupt Type

6

5

4

3

2

1

0

Noncommunications

Processors 0 and 2
e'it Position of the
CAW

53 52 51 50 49 48 47 46 45

Channel Module
Number

*

.

Interrupt Type

7

6

5

4

3

.2

1

0

Communications

44 43 42 41 40 39 38 37 36

*

7

6

5

4

3

2

1

0

Noncommunications

* Not u6t1d
6. '19. Initial Load
Th '8 initial load capability is included in each channel. The initial load operation is performed in only
the 36-bit mode of operation. On a byte or block multiplexer channel, format C (8-bit packed) is
specified, the starting data address is set to MSR, and the byte count is set to 4608 ,0, On a word
channel, the starting Ciata address is set to MSR and the word count is set to 1024 ,0, The size of
the initial load boot block is determined by the channel and the device. The channel ~iII terminate
the operation after 1024,0 full 36-bit words have been loaded into storage. If the device presents
status before 1024,0 words have been loaded. the channel immediately terminates the operation and
presents an interrupt to the CPU
6.20~

Back-to-Back Operation (Word Channel Only)

The word channel back-to-back capability will allow the software to execute block transfers or
scatter/gather operations via an I/O channel. Two lSI interfaces on the same channel are required,
an output interface and an input interface. The back-to-back interfaces must be initialized after the
IOU is master cleared, after any hardware or software error on the back-to-back interfaces. or after
a back-to-back operation that did not have the output buffer data count equal to the input buffer data
count. The back-to-back interfaces are initialized by using the following procedure:
1.

To the output interface, issue an SIOF instruction that initiates the execution of one CCW. The
CCW must have a forced external function command and a data count of one.

2.

Handle the external interrupt from the input interface. This external interrupt was generated
by the forced external function operation on the output interface.

pelRAY
~
-----,

lle04 Aw.1

UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

~

UfIOATI LIVEL

To execute a back-to-back operation the following procedure must be followed:
1.

Issue an SIOF instruction to the input interface to' activate the input buffer.

2.

Issue an SIOF instruction to the output interface to activate the output buffer..

Once the back·-ta-back interfaces are initialized, many back-ta-back operations may be performed
by fol!lowing the above procedure for each operation. Data chaining is allowed on both the output
and irlput interfaces for each back-to-back operation, but the total output buffer data count must
equal the total input buffer data count. The use of the DAD, SK, OAL, PCI, and MON CCW flags is
allowEtd, but cc)mmand chaining is prohibited.

6.2 1. Priorities
The c.~mtrol module establishes data handling priority among the eight channel modules. Channel
modul!e 0 has the highest priority and channel module 7 has the lowest priority. The channel module
gives highest priority to data transfers, second highest priority to interrupts, and lowest priority to
instruc:tions. Word channel data handling priority is a homing priority with interface A having the
highent priority, then interfaces S, C, and 0, with interface 0 having the lowest priority.

6.22. Basic Programming Procedure
The p,'ogrammer should use the following basic procedure in order to execute a series of operations
on a byte or block multiplexer device or a word subchannel:
1.

. 2.

B:uild the list of CCWs, making sure that the correct flags in each CCW are set. and build any
necessary external function words or data buffers.
Load the clddress of the first CCW in Xa bits 0-23.

+ Xm bits 0-12 specifies the IOU, channel, and device

3.

Load the u and Xm registers such that u
numbers.

4.

Clisable IIC) interrupts.

5.

II~sue

e.

Test the condition code to determine the result of the SIOF instruction. (Note that the next
instruction is skipped if the condition code equaled 0 and the CPU did not timeout the
instruction.)

7.

If the instrluction is not timed out by the CPU and a condition code of 0 is received, enable I/O
irlterrupts and continue with the CPU program. If another condition code is received or the
irtstruction is timed out, the appropriate action should be taken.

8.

Vlllait for the 1/0 interrupt or interrupts. Use the resultant status to determine if the CCW list
~ras executed successfully. If the CCW list was terminated before it was comp'eted, the status
will conta;', enough information to determine how much of the CCW list was executed, and why
the CCW list was terminated before it was completed.

the lSIOF instruction.

..........

1804 Rev.1

SPIRRY UNIVAC 1 100/10 S~

4x4 Capability Processor and Storage Programmer Reference

IJIIDATI LIVIL

6.23. Programming Examples
For an example of the block multiplexer channel CCW list see Figure 6-3. The execution of this CCW
list is initiated by an SIOF instruction with a CCW address of BO 18' The CCW list is executed as
follows:
1.

The channel reads the first CCW and issues the Read command to the device.

2.

Nine bytes are transferred from the device to the channel, but none of the bytes are written into
storage because the skip data flag is set.

3.

The device presents Channel End and Device End status (chaining status).

4.

The channel initiates the command chain and issues the Write command to the device.

5.

Thirty-Six bytes are transferred from the channel to the device. All the bytes are transferred from
the same storage address because the data address lock flag is set.

6.

The channel executes a data chain and transfers two bytes from storage address FO 18 and two
bytes from storage address EF 18 because the data address decrement flag is set.

7.

The device presents Channel End and Device End status (chaining status).

8.

The channel initiates the command chain and executes the Store Subchannel Status command.
A two word CSW is stored at storage address 44 18, In the CSW, the next CCW address field
equals B8, the data count field equals zero, and the subchannel ~nd device status fields equal
zero.

9.

The channel continues the command chain and issues the read backward command to the
device and then terminates the operation because an illegal combination of format flags is
detected.

10. The device presents Channel End and Device End status.
11. The channel accepts the device status and presents an interrupt request to the CPU.
1:2. The interrupt is acknowledged and a CSW is written with the next CCW address field equal to
BA,8' the data count field equal to 1 18, the Program Check and PCI subchannel status bits set,
and the Channel End and Device End device status bits set.

~

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P£IRRY UNfVAC 1100/80 Systeml

6-69

4x4 Capability Processor and Storage Programmer Reference

Bits

'.141

Read Command
~

Modifier Bits
,.-~ Write Command

~

1 0

o

0 0 1 0 0 0

O~ O~ [X

1 1 , 0

I~~
)ata Chain

o

0

o

0

o

O~ 0: ~ ~

0 0 0 0 0 0 0

o

1 1 0 0 0 0

0 0 0 0 0 0 0 0 0

o

1 0

o

1 1

1 0

0

Format A
30 bit
Data Address Lock

-

o 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

B4

o

B5

0 0 0 0 0 0 0 0 0 0 0 0 , 0 0

Data Address Decrement
.. Command Chain
~ore

Modifior

I

Bits

,.-~

1m
C8J

Subchannel Status Command

r - Read Backward Command

I

10'
0 0 0

Don't C~lre bit

..

\

1 0 0 0 0 0
0

1 0 1

o

0

o

0

1 1 0 0 0

,X XXX

o .1

0

o

1

1 1

1

1

1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

~ Illegal Secause Two Formats are Specified

o

1

16

16

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

~

UPDATE LlYIL

8-70
"AGI

The interrupt mechanism was assumed to be busy during the execution of this CCW list, causing the
PCts to be overlaid.
For an example of the word channel lSI interface CCW list see Figure 6-4. The execution of this CCW
list is initiated by an SIOF instruction with a CCW address of A2. The CCW list is executed as follows:
1.

The channel reads the first CCW and issues the forced external function to the device. The
forced external function contains a Write command for the device.

2.

The channel then executes the command chain. The TIC command is executed and the CCW
address- field is changed to 54,8' .

3.

The channel continues the command chain and executes the Write command by activating the
output data buffer.

4.

Four words are transferred from the channel to the device. All the words are transferred from
the same storage address because the data address lock flag is set.

5.

The channel executes a data chain and transfers three words from storage addresses 29 18,
28 18, and 27 18 because the data address decrement flag is set.

6.

The channel executes a command chain and issues a forced external function to the device. The
forced external function contains a Read command for the device.

7.

The channel executes the Read command by activating the input buffer.

8.

Two words are transferred from the device to the channel but not to storage because the skip
data flag is set.

9.

The channel terminates the operation and presents an interrupt request to the CPU when the
interrupt mechanism is free.

10. The interrupt is acknowledged and a CSW is written with the next CCW address field equal to
62,8' the data count field equal to zero, and the Monitor and PCI subchannel status bits set.
The interrupt mechanism was assumed to be busy during the execution of the CCW list, causing the
PCls to be overtaid. The device was assumed to be non-fnterrupting. On an 151 interface, an external
interrupt immediately terminates the execution of a CCW list.

I

SPIERRY UNIVAC 1100/80 Systems

~t4 Capability Processor and Storage Programmer Reference

UllOA11 L&VIL

8-71
PAGI

o 0 0 0 0 0 0 0 001
o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

A3

Command Chain
TIC Command
,---A-.
A4

AS

o
o

0 0 0 0 0 0 0 0 0 0 0 001 0

54

0 000 000 000 0 0 1 0 0

55

Checked only for TIC Command

o

0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

56

o 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

57

o 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0

58

o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

59

Command Chain
Forced EF Command
t-'-.

Command Chain
Read Command
,,-A-.,

60
61

L8J

Don't Care Bit

--------U!
se04

Rev."

PERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

UfI..wMIM

7-1
UPOATI t.EV!L

PAGE

7. Interrupts

7.1. General
An intt9rrupt causes the current instruction sequence to be suspended and an instruction sequence
starting at a fixed storage location to be initiated; the fixed address replaces the value in the program
addrens register. The fixed storage address is associated with the event or condition that caused
the interrupt to be generated. and thereby allows switching to a program to respond to thet condition
or event. Excepting those instructions that are explicitly named as interruptible, such as repeated
instruc:tions like Block Transfer, the central processor units (CPU) honors interrupts only after the
currenlt instruction is completed and only if the interrupt to be honored is allowed. Table 7-1 shows
the interrupts and their priorities. The interrupts are categorized by levels of priority. The following
interrupts are always allowed:

•

A~U

•

A~1I

•

Certain program initiated interrupts. including Executive Request, Test and Set. Quantum Timer,
Elreakpoint. and Emulation interrupts.

•

Storage Check interrupts caused as the result of transfers between the CPU and storage
ill1terface unit (SIU).

program exception interrupts, including Guard Mode and Addressing Exception interrupts.

arithmotic exception interrupts. including Characteristic Overflow. Characteristic Underflow,
81nd Divid«t Check interrupts.

Certain interruJ)ts are disallowed between the execution of a Prevent All Interrupts and Jump (PAIJ)
instrulction or the occurrence of an interrupt. and the execution of an Allow All Interrupts and Jump
(AAIJ) instructiCln or User Return (UR) or Load Designator Register (LD) instruction that sets the allow
intermpts desi1~nator (03). These include the following:
•

)~II I/O interrupts, including those for Normal status. Tabled status. and Machine Check

interrupts..
•

f'ower Check interrupts

leo4 Rev.1
\,ILM._

SPERRY UNIVAC 1100/10 SyReml

4x4 Capability Processor and Storage Programmer Reference

Priority Level

Interrupt Type

o

Immediate Storage Check (oper port)
Immediate Storage Check (inst port)
Guard Mode (oper port)
Guard Mode (inst port)
IOU 0 ERR
IOU 1 ERR
Addressing Exception
Invalid Instruction
Executive Request
Test and Set
Characteristic Overflow
Characteristic Underflow
Divide Check
Emulation
Breakpoint
Quantum Timer
Jump History Stack
Power Restored
Power Loss
Real, Time Clock
Dayclock
Delayed Storage Check Upp1er
Delayed Storage Check Lowler
IOU 0 Machine Check
IOU 1 Machine Check
IOU 0 Normal Status
IOU 1 Normal Status
IOU 0 Tabled Status
IOU 1 Tabled Status
IPI P
IPt P+ 1 or P-3
IPt P+2 or P-2
IPt P+3 or P-1

2

3
4

5

e

7,

8
9
10
11
12
13
14
15
16
17
18

19
20

NOTES:
1. I'rforlty I.".,. 0 thl'OUgh 6 Nfl int",.,," int.,-rupts. which c.n "- ntlith.,. lod:«I (Jut nfJl'
_ , . " . (Mw~ .,IowtId).
2. Priority Iw./. 6 thtOUgh 20 .,.. .t.,.".' intMnlpt8, which c.n ". both loct«l (JUt .nd
d.,.,.,-.d.
3. For in~nMH' intMnlpn. Pi. th. CPUnumlHl' (Jf th. CPU btling ;ntllmJpted~ FfJI' priority
I".". , S, '9,.nd 20 UMI t"- tMm th« g;"•••n IPI numbM from 0 to po.itiI'f. 3.

I

8804 Aev.1

SPEflAY UNIVAC 1100/80 Systems

~ Capability Processor and Storage Programmer Reference

UNIIU....

•

7-3
UPDATI I.IVE1.

"AGE

InterprocElssor interrupts (IPls)

NOTE:'
If int~'rrupts are locked out and the CPU is stopped via Halt Jump (HJ) instruction, Interprocessor
interrupts and Power Check restoration interrupts are allowed; and if the CPU is stopped in the cleared
state, in additicm to Interprocessor interrupts, I/O normal status interrupts are allowed if the CPU has
been selected for initial load. (The I/O normal status interrupts are not allowed until software has
sent ~, function to the channel or word channel interface.)
•

[)ayclock and Real-Time Clock interrupts.

•

Storage Check interrupts caused as the result of transfers from the SIU to storage units.

•

Jlump History Stack interrupts.

7.2. Interrupt Sequence
When the CPU honors an interrupt request, the following ttvents occur:
•

,'heprocessor state is stored in the general register stack (GRS) in three groupings: program
s,tatus (041-044, 050-052, and 056-057), addressing status (040 and 045-047 not actually
s,tored during interrupt), and interrupt status (053-055).

•

,l~1I designator register bits are set to zero except the GRS selection designator (06) and the

r·elocation and storage suppression designator (07), which are set to one, and the BOR selector
OIesignatolr (01 2), which is not altered.
•

E~ternal

•

Control is transferred to the associated interrupt location. Note that this instruction must be an
unconditional jump, but need not be a Load Modifier and Jump (LMJ) instruction. LMJ may
c:apture the wrong relative address because of the processor state change (e.g., LBJ interrupt).

irlterrupts are prevented from occurring until allowed by an AAIJ. UR, or LD instruction.

7.2. 1.. Program Status
Progmm status is stored for all interrupts, and includes the following information:
•

FJrogram Return Address

- GRS Location 043 for Normal interrupts
GRS Location 05 1 for Guard Modes
GRS Location 04 1 for Immediate Storage Checks
GRS Location 056 for IOU Error Interrupt

•

(luantum Timer Value

- GRS Location 050 for all interrupts.

•

[)esignator Register Value

- GRS Location 044 for Normal interrupts
GRS Location 052 for Guard Modes
,

GRS Location 042 for Immediate Storage Checks

a804 Rev.1

SPERRY UNIVAC 1100/80 System.

.............

4x4 Capability Processor and Storage Programmer Reference

GRS Location 057 for IOU Error Intttrrupt
A program return address is the address of the instruction following the last instruction that was fully
executed; program control would normally be returned at this point for reco-,,'erable errors. The
program return address stored in GRS locations 041, 043, 051, and 056 is in the following format:

[~A~I________

N_ot_U_H
__d________

35 34

24

~

._~_o_g_~_m

______________

d_r~

__R_.t_u_m_Ad
__ ________________

23

~1
o

The' program return address value will vary depending on the operation being pEtriormed at the time
of interrupt
•

If an incomplete block transfer, search instruction, or byte instruction is in1:errupted, the return
address will be P.

•

If a satisfied (the condition specified by the instruction exists) skip instructicln is interrupted, the
return address will be P+ 2.

..

If a satisfied (the condition specified by the instruction exists) jump instruction is interrupted,
the return address will be U.

•

If an instruction other than the above is interrupted, the return address will be P+ 1.

The contents of the program address register is changed only by a jump instruc:tion (including User
Return) or interrupt. Instruction references following a jump instruction are m~lde under the same
addressing constraints that conditioned the operand address of the jump instruc:tion that began the
straight line instruction stream.
Bit position 35 of the. first word of the 2-word program status packet contains iii flag that identifies
the correct program addressing mode. The two modes of program address generation include
absolute (A-1), corresponding to 035-0 and 07-i.1, and relative (A-O), corresponding to
035.1, or 034, or i-O.
Bit positions 18 through 23 of the relative:: rogram address are zero unless absolute 24-bit indexing
mode is selected. For straight line instrUction sequencing, the relative program ~.ddress is increased
by one for each instruction that is executed or skipped. This increase is acc:omplhshed by twos
complement addition with wraparound at 18 or 24 bits, depending on the vallue of the A-flag.

7.2.2. Addressing Status
Addressing status is not actually stored during the inte"upt sequence. The inflormation within this
group is placed in GRS by the software either directly (load, store~ or indirectly (LI,ad Bank and Jump,
LB,J; Load Addressing Environment. LAE) and is used from GRS by the CPU for addressing operations.
Addressing status includes the following information:
•

Executive bank descriptor table pointer.

•

user bank descriptor table pointer.

PEIFtRY
~
-----,

UNIVAC 1100/80

S~

4x4 Capability Processor and Storage Programmer Reference

I~ank

•

descriptor specifications in the following format:

lEO 00

IE 1

o

1

() - 0

BOlO

E2 1

0 0-0

801 2

() - 0

8011

E3 1

1

0-0

BOI 3

:II 34 33 32

30 29

'8 17 "

15'4

12 11

o

7.2.3. Interrupt Status
IntemJpt status is information associated with a particular type of interrupt, and is stored only when
its tyJl~e of interrupt occurs. Immediate Storage Check status is stored in GRS-location 054, Guard
Mode status is stored in GRS location 053, all other CPU-generated interrupt status is stored in the
Normlill status location, GRS 055. Interrupt status is associated with the following types of interrupts:
•

Immediatft Storage Check interrupts

•

C;uard Mode interrupt

•

E:xecutive Request, Test and Set, and Invalid Instruction interrupts

•

C)elayed Storage Check interrupts

•

Breakpoint and EmuJation interrupts

•

F'ower Check interrupt

•

~~ddressing Exception interrupt

•

Itrtterprocessor interrupt

7.3. Interrupt Types
The CPU provides 20 interrupt priorities. The interrupt types are listed in Table 7-1.

7.3. 1. Program Exception Interrupts
Invalid Instruction - This interrupt occurs when the CPU attempts to execute an instruction with an
invalid function code. The operand address of the instruction (24 bits of U) is stored in GRS as
interrupt status.
Guard Mode - This interrupt occurs in the following cases:
•

VVhen the privileged instruction, GRS protect, and interrupt lockout detect designator (02) equals
one, and the execution of a privileged instruction is attempted, or interrupt lockout period is
exceeded.

•

VVhen the storage limit fails and either 07 is zero or the i-bit of the instruction word is zero.

8eo4 Rev.1

SPERRY UNIVAC 1100/80 System.

UNIJUMIIR

4x4 Capability Processor and Storage Programmer Reference

UlIIOATI LIYIL

I

•

When any reference is made to an SIU that has its interface to the CPU disabled.

•

When attempting to store in GRS locations other than those allowed for thu user (40 a ·through
100a, and 1208 through 177 8, when 02 is one).

•

When attempting to write into a storage area specified by bank descriptOlr register (BORO, 1,
2, or 3) for which the corresponding write protection designator bit (013 through 016) is one.

See Figure 7-1 for the format of the Guard Mode interrupt status stored in GRS during the interrupt
sequence.
Addressing Exception - This interrupt occurs in the following cases:
•

E-bit violation -If the E-bit (bit 35) from Xa of an lBJ, load I-Bank Base and Jump (UJ) or load
O-Bank Base and Jump (lOJ) instruction is one and the exEC bank desc:riptor table ,pointer
enable designator (0 19) is zero.

•

Table length violation -If a bank descriptor index value from Xa of an lBJ, ll.J, or lOJ instruction
is greater than the selected BOT pointer length valu~.

•

Residency interrupt - If the R-flag of the new bank descriptor is one.

•

Entry point violation - If the V-flag of the new bank descriptor is one.

•

Use count overflow on lBJ, UJ. or lOJ new bank descriptor.

•

Use count underflow on lBJ, llJ, or LOJ old bank descriptor.

•

Use count decreased to zero and C-flag was one.

Seo Figure 7-2 for the format of the Addressing Exception interrupt stored in GRS during the interrupt
sequence. The program return address stored for this interrupt is P+ 1 for E: bit or table length
vio~ations. and the jump to address for all other violations.

7.3.2. Arithmetic Exception Interrupts
An interrupt occurs in the following cases only if the arithmetic exception interrupt designator (020)
is ()ne.
Ch:aracteristic Overflow - Occurs when the exponent value of a floating-point result is greater than
+ 127 10 (single precision) or + ~ 023 10 (double precision). When this condition is detected, the
.
characteristic overflow designator (022) is set to one.
Characteristic Underflow - Occurs when the exponent value of a floating-poirlt result is less than
When this condition is detected, the
characteristic underflow designator (021) is set to one.

-128.,0 (single precision) or -1024,0 (doubte precision).

Divide Check - Occurs when the magnitude of the quotient exceeds the range of the specified register.
When this condition is detected. the divide check designator (023) is set to one.

SPEltRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

7-7
'AGE

Zeros

:15 3" 3332 31 30 29 28 27 28

Elit 35

Write protection violation.

Elits 34-33

BDR number associated with write protection violation.

Elit 32

Storage limits violation.

EUt 31

Reference to disabled storage.

Elit 30

Is zero.

Elit 29

In~errupt

Elit 28

Control register violation.

Elit 27

Privileged instruction violation

Elits 26-0

Are zeros.

lockout exceeded.

o

8804 Rev.1

SPERRY UNIVAC 1100/80 SysteIM

UI'-fIUMIIIIl

4x4 Capability Processor and Storage Programmer Reference

New BOI

31 34 33 32 31 30 29

Old BOt
18 17 18 15 14 13 12 11

o

Bit 35

New bank descriptor E-flag specification from Xa.

Bit 34

The V-flag indicates an entry point violation on the new bcllnk descriptor.

Bit 33

The E-flag indicates an E-bit violation on the new bank dellcriptor.

Bit 32

The R-flag indicates the residency flag of the new bank descriptor was one.

Bit 31

The CO-flag indicates a use count overflow on the new bank descriptor.

Bit 30

The T-flag indicates a table length violation on the new bank descriptor.

Bits 29-18

New bank descriptor BDI specification from Xa.

Bit 17

Old bank descriptor E-flag specification from GRS.

Bits 16-15

The bank descriptor register specification from Xa.

Bit 14

Is zero.

Bit 13

The CU-flag indicates a use count underflow on the old bunk descriptor.

Bit 12

The CZ-flag indicates the old bank descriptor use count was decreased from one
to zero and the C-flag was one.

Bits 11-0

Old bank descriptor BDI specification from GRS.

NOTE:

Thi.'nt«TUpt ,..ul,. only from die exHution 01." LBJ, LIJ, (JIf' LDJ In<
ANH
ANM,ANMA
AN"r
ANIJ
AT
AU
BA
BAN
BC
BOI=
BOI
BF
BI
aM
BM'T
aT
BTC

ceu
oA
DAN

Function
Code (Octal)
f
j

14
24
74
72
16
15
25
42.
72
17
72
21
72
20
37
37
33
33
33
33
33
33
33
22
33
76
71
71

07
04

05
07
06
06
07
04
15
11
14
10
00
01
03
07
10
11

Paragraph
Reference

5.4.1
5.4.7
5.9.3
5.4.17
5.4.3
5.4.2
5.4.8
5.12.3
5.4.18
5.4.4
5.4.20
5.4.6
5.4.19
5.4.5'
5.14.14
5.14.15
5.14.4
5.14.11
5.14.7
5.14.10
5.14.6
5.14.1
5.14.2
5.3.8
5.14.3
5.5.16
5.4.15
5.4.16

Function
Code (Octal)
f
j

Mnemonic
DOC
DEC
OF
DFA
oFAN
DFB
oFO
OFM
OFP,OlCF
OFU
01
DIS
OJZ
Ol
OlM
OlN
OlSC
OS
OSA
OSC
OSF
OSl
OTE
EOC
EOIT

I

14
73
12
a =
05 00-17
a= 11, 13
36
76
10
11
76
17
33
76
13
12
76
15
76
14
76
34
13
33
71
16
71
13
71
15
14
71
07
73
71
12
73
05
73
01
35
73
03
17
71
14
73
a =- 1 1
07
33

Paragraph
Reference

5.15.3
5.13.14
5.4.14
5.5.3
5.5.4
5.14. 13
5.5.8
5.5.6
5.5.12
5.5.10
5.4.12
5.14.9
5.11.2
5.2.9
5.2.11
5.2.10
5.8.8
5.3.7
5.8.6
5.8.2
5.4.13
5.8.4
5.7.14
5.15.3
5.14.5

8804 Rev. '1

SPERRY UNIVAC 1100/80 Systems

~MlER

4x4 Capability Processor and' Storage Programmer Reference

C-2
U.-oATI LEVEl.

PAGE

rable C-I. Mnemonic/Function Code Cross-Reference (continued)

Function
Code (Octal)
Mnemonic

f

ENZ
ER
EX
FA
FAN
FB
FCL
FD
FEL
FM
HCH
HDV
HJ,HKJ
IB
lUX
IMI
INC
:

I

J,JK
JB
JC
JDF
.JFO
JFU
JGO
JMGI
IN
JNB
JNC
JNDF
JNFO
JNFU
JNO
JNS
JNZ
JO
JP

I

j

05
00-17
a == 14-17
72
11
72
10
76
00
76
01
33
16
76
17
76
03
76
16
76
02
75
05
75
04
74
05
12
33
15
73
a == 04
72
00
05
00-17
a== 10,12
74
04
74
11
74
16
74
14
a == 03
74
14
a == 02
"'74
14
a == 01
70
74
12
74
03
74
10
74
17
74
15
a == 03
74
15
a =- 02
74
15
a == 01
74
15
a == 00
72
03
74
01
74
14
a == 00
74
02

Paragraph
Reference
5.13.14
5.13.4
5.13.3
5.5.1
5.5.2
5.14.12
5.5.14
5.5.7
5.5.13
5.5.5
6.4.6 '
6.4.5
5. 11. 10
5.14.8
5.15.19

Mnemonic
JPS
JZ
L,LA
L,LR
L,LX
LAE
LB
LBJ
LBRX
LCF
LCR
LD
LDC

5.15.21
5.13.14
5.11.9
5. 11. 12
5. 11.22
5.11.17
5. 11. 16
5.11'.15
5.11. 1
5.11.13
5.11.8
5.11. 11
5.11.23
5.11.21
5.11.20
5.11.19
5.11.18
5.11.4
5.11.6
5.11.14
5.11.7

LOJ
LOSC
LOSL
L1J
LL
LM,LMA
LMJ
LN,LNA
LNMA
LPD
LaT
LRS
LSC
LSSC
LSSL
LTCW
LUF
LXI
LXM
MASG
MASL
MCOU
MDA
MOB
MF

Function
Code (Octal)
f
j
72
74
10
23
27
73
a ==
73
a==
07
73
a ==
76
75
73
a ==
73
a==
07
73
73
07
73
a ==
12
74
11
13
07
73
a ==
72
73
73
73
75
76
46
26
71
71
76
73
a=

02
00
I

15
12
15
10
17
15
02
05
10
15
14
14
10
12
11
13
13
15
11
13

14
15
03
17
06
10
12
11
04

07
06
06
14
14
14
73
a== 15
32

Paragraph
Reference
5. 11.3
5.11.5
5.2.1
5.2.5
5.2.7
5.15.11
5.15.9
5.10.1
5.15.6
5.5.11
6.4.7
5.15.13
5.15.2
5. 1 0.3
5.8.10
5.8.12
5.10.2
5.15.10
5.2.3
5.9.2
5.2.2
5.2.4
5.13.1
5.15.8
5.13.12
5.8.7
5.8.9
5.8.11
6.4.8
5.5.9
5.2.8
5.2.6
5.6.14
5.6.13
5.5.15
5.15.20

15.15.20
5.4.11

8804 Rev. 1
U'-',ffUM8ER

I

SPERRY UNIVAC 1100180 Systems

~

Capability

~rocessor

C-3

and Storage Programmer Reference

UPOATI LEVEL

PAGE

rable C- 1. Mnemonic/Function Code Cross-Reference (continued)

Function
Code (Octal)
Mnemonic
MI
MLLI
MSe:
MSCi
MSI
MSl.E,MSNG
MSNE
MSNW
MS\N
NOFI
• OR
PAI ..I
RAT

f

j

Function
Code (Octal)

1

Paragraph
Reference
5.4.9
5.12.4
5.6.7
5.6.10
5.4.10
5.6.9
5.6.8
5.6.12
5.6.11
5.13.10
5.12.1
5.15.1
5.15.16

30
43
71
00
71
03
31
71
02
71
01
71
05
71
04
74
06
40
I 72
13
I 73
15
a = 06
S,5J~
01
5.3.1
S,5J~
04
5.3.4
5,5;(
I 06
5.3.6
SAS
05 00-17 5.3.5
a = 06
SAZ
05 00-17 5.3.5
a = 07
SO
73
15
5.15. 14
a = 15
SOC:
14
73
5.15.4
!
a = 13
SE
62
1
1 5 .6.
SFS
05 00-17 5.3.5
a =: 04
5FZ:
05 00-17 5.3.5
a :II 05
SG
65
5.6.4
SIL
73
15
5.15.5
a = 00
SIOF
75
01
6.4.2
SLE:.SNG
64
5.6.3
SLJ
72
01
5.9.1
03
5.3.3
SM"SMA
SN,SNA
02
5.3.2
SNI:
63
5.6.2
67
5.6.6
SN'N
SN~~
05 00-17 5.3.5
a == 01
SN1
05 00-17 5.3.5
I a = 03
I SP[,_)_____ ~__0_7____1~5~_5_.1~3_.2____~

Mnemonic
SPIO

I

SP1
SaT
SAS
SSA
SSC
SSL
5SS
SW
SZ
TAP
TCS
TE
TEP
TG
TLE,TNG
TLEM,TNGM
TN
TNE
TNW
TNZ
TOP
TP
TRA
, TS
TSA
TSC
TSS
TSSA
TW
TZ

UR
I XOR

f

j

I
I

I

Paragraph
Reference
5.15.7

73
15
a = 05 I
05 00-17 5.3.5
a = 02
73
15
5.15.12
a = 13
72
16
5. 13. 11
73
04
5.8.5
73
00
5.8.1
73
5.8.3
02
15
73
5.15. 18
a = 17
66
5.6.5
05 00-17 5.3.5
a = 00
73
15
5.15.17
a =- 07
17
73
5.13.7
a :II 02
5.7.6
52
44
7 .1
5.7.9
55
54
5.7.8
47
5.7.3
61
5.7.13
5.7.7
53
5.7.11
57
51
5.7.5
45
5.7.2
5.7.12
60
72
5.13.13
15
17
5.13.5
73
a = 00
17
5.13.8
73
a = 04
6.4.4
75
03
17' 5.13.6
73
a = 01
17
5.13.9
73
a = 05
5.7.10
56
5.7.4
50
5.15.15
73
15
a = 16
41
5.12.2

lti.

I

I
I

I

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

~

4x4 Capability Processor and Storage Programmer Reference

Tabl. C-2. Instruction Repertoire

Function
Code
(Octal)
f

j

Mnemonic

00

0-17

-

01

0-15

02

Instruction

Description

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

S.SA

'Store A

(Aa) -

0-15

SN.SNA

Store Negative A

- (Aa) -

03

0-15

SM,SMA

Store Magnitude
A

I (Aa) 1- U

·04

0-15

S.SR

Store R

(Ra) -

05

0-17

SZ
a =- 00

Store Zero

Store constant 000000 000000, zeros. in
location specified by operand address

05

0-17

SNZ
a =- 01

Store Negative
Zero

Store constant 777777 777777, all ones, in
location specified by operand address

05

0-17

SP1
a = 02

Store Postive
One

Store constant 000000 000001, postive one,
in location specified by operand address

05

0-17

SN1
a =- 03

Store Negative
One

Store constant 777777 777776. negative one.
in location specified by operand address

05

0-17

SFS
a =- 04

Store Fieldata
Spaces

Store constant 050505 050505, Fieldata
spaces. in location specified by operand
address

05

0-17

SFZ
a - 05

Store Fieldata
Zeros

Store constant 606060 606060, Fieldata
zeros, in location specified by operand address

05

0-17

SAS
a - 06

Store ASCII
Spaces

Store constant 040040 040040. ASCII spaces,
in location specified by operand address

05

0-17

SAl
1-07

Store ASCII
Zeros

Store constant 060060 060060. ASCII zeros.
in location spe~ified by operand address

I

U
U

U

05

0-17

INC
a- 10

Increase Operand
by One

Increase operand by one. If initial operand or
result is zero. execute NI; if not zero, skip NI.

05

0-17

DEC
a =- 11

Decrease
Operand by One

Decrease operand by one. If initial operand or
result is zero, execute NI; if not zero, skip Nt.

05

0-17

INC2
a =- 12

Increase Operand
by Two

Increase operand by two. If initial operand or
result is zero, execute NI; if not zero, skip Nt.

I

leo.. Rev.1

SPIERRY UNIVAC 1100/80 Syetems

~4

IJIf-HuMIU

Capability Processor and Storage Programmer Reference

UIIOATI LIVI1.

Tablll C-2. Instruction R.ptlftOir. (continutHil

Function
Code
(IOctal)

f

j

05

0-17

05

06

Mnemonic

Instruction

Description

DEC2
a =- 13

Decrease
Operand by Two

Decrease operand by two. If initial operand or
result is zero, execute NI; if not zero, skip NI.

0-17

ENZ
a - 14-17

Increase ·Operand
by Zero

Increase operand by zero. If initial operand or
result is zero execute NI; if not zero, skip NI.

0-15

S,SX

Store X

(Xa) -

07 .0-11

-

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 221.8

07'

12

LOJ

Load D-Bank
Base and Jump

Ignore Xa bit positions 34-33; if 012 - 0,
select BOR2; if 012 =- 1, select BOR3

07'

13

LJJ

Load I-Bank
Base and Jump

Ignore Xa bit positions 34-33; if 012 - 0,
select BORO; if 01 2 - 1, select BOR 1

07'

14

LPO

Load DR
Designators

Ue.5 .3-0
Bit 6 Bit 5 Bit 3 -

07'

15

SPO

Store DR
Designators

i

Ojr

16

-

O'4r

17

1()

U

.

Designator Register
020
Bit 2 - 08
017
Bit 1 - 05
010
Bit 0 - 04

-

.

Designator Register D-bits 020 - Bit 6
08 - Bit 2
017 - Bit 5
05 - Bit 1
012 - Bit' 4
04 - Bit 0
010 - Bit 3

Us-o

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

LBJ

Load Bank and
Jump

Load BOR; jump to location specified by the
operand address

0-17

L,LA

Load A

(U) -A

1 'I

0-17

LN,LNA

Load Negative A

- (U) - A

1 :l

0-17

LM,LMA

Load Magnitude·
A

1(U) 1- A

13

0-17

LNMA

Load Negative
Magnitude A

-I (U) 1- A

144

0-17

A,AA

Add to A

(A)

+ (U)

- A

8804 Aw.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

UfII..HUMIp

Function
Code
(Octal)

I

I

\

f

j

15

0-17

AN,ANA

Add Negative To
A

(A) - (U) -

16

0-17

AM,AMA

Add Magnitude
To A

(A) +

17 0-17

ANM,ANMA

Add Negative
Magnitude to A

(A) -

20 0-17

AU

Add Upper

(A) + (U) - A+l

21

ANU

Add Negative
Upper

(A) - (U) - A+ 1

22 0-15

BT

Block Transfer

(Xx

23 0-17

L.LR

Load R

(U) -

24

A,AX

Add to X

(Xa) + (U) - Xa

25 0-17

AN,ANX

Add Negative to
X

(Xa) - (U) -

26 0-17

LXM

Load X Modifier

(U) -

Xa17-O; Xa35-18 unchanged

27

L,LX

Load X

(U) -

Xa

30 0-17

MI

Multiply Integer

(A) x (U) - A, A + 1

31

MSI

Multiply Single
Integer

(A) x (U) - A

MF

Multiply
Fractional

(A) x (U) - A, A+ 1, left circular one bit

BM

Byte Move

Transfer WO bytes from source string to
receiving string. Truncate or fill receiving
string as required

33 01

BMT

Byte Move With
Translate

Translate and transfer WO bytes from source
string to receiving string. Truncate or fill
receiving string as required

33 02

BTT

Byte Translate
and Test

Translate and test N bytes against (A); if not
equal, terminate instruction with JO pointing to
unequal byte and N -: O. (This instruction
simulated by library procedures and routines.)

0-17

0-17

0-17

0-17

32 0-17
33

00

Mnemonic

Instruction

Description
A

I (U) I -

A

I (U) I -

+

u) -

A

Xa

+

u; repeat k times

Ra

Xa

I

El404 Rev.1

SPERRY UNIVAC 1100/80 Svstems

~~

~

Capability Processor and Storage Programmer Reference

C-7
ftAGE

Tablll C-2. Instruction Rllpllrroirll (continulld)

Function
Code
()ctal)
f
33

j

03

Mnemonic
BTC

Instruction
Byte Translate
and Compare

Description
Translate and compare WO bytes from string
SJO to W 1 bytes from string SJ.1; terminate
instruction on not equal or if both WO and W 1
are zero, when:
(Aa) > 0; string SJO > SJ 1
(Aa)
0; string SJO == SJ 1
(Aa) < 0; string SJO < SJ 1

=

33

04

BC

Byte Compare

Compare WO bytes from string SJO to W 1
bytes from string SJ 1; terminate instruction on
not equal or if both WO and W 1 are zero

33

05

BPD

Byte to Packed
Decimal Convert

Convert N bytes in string E to packed decimal
in string F. (This instruction simulated by
library procedures and routines.)

33

06

POB

Packed Decimal
to Byte Convert

Convert N packed decimal digits in string E to
bytes in string F. (This instruction simulated by
library procedures and routines.)

33

07

eDIT

Edit

Edit string SJO and transfer to string SJ 1
under the control of string SJ 2

33

10

BI

Byte to Binary
Single Integer
Convert

Convert WO bytes in string SJO to a signed
binary integer in register A

33

11

BOI

Byte to Binary
Double Integer
Convert

Convert WO bytes in string SJO to a signed
binary integer in registers A and A+ 1

33

12

18

Binary Single
Integer to Byte
Convert

Convert signed binary integer in A to byte
format and store in string SJO

33

13

OIB

Binary Double
Integer to Byte
Convert

Convert the binary integer in A and A+ 1 to
byte format and store in string SJO

331

14

BF

Byte to Single
Floating Convert

Convert WO bytes in string SJO to a single
length floating point format in register A

3~1

15

BOF

Byte to Double
Floating Convert

Convert WO bytes in string SJO to a double
length floating point format in registers A and
A+1

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

~

4x4 Capability Processor and Storage Programmer Reference

.

C-8
UII'DATI LIVIL

PAGE

Function
Code
(Octal)
f

j

Mnemonic

Instruction

Description

33

16

FB

Single Floating
to Syte Convert

Convert the single length floating point number
in A to byte format and store in string SJO

33

17

DFB

Double Floating
to Byte Convert

Convert double length floating point number in
A and A+ 1 to byte format and store in string
SJO

34

0-17

01

Divide Integer

(A, A+ 1) divided by (U) A+1

35

0-17

DSF

Divide Single
Fractional

[(A, 36 sign bits) right algebraic shift 1 place]
divided by (U) - A + 1

36

0-17

OF

Divide Fractional

[(A, A+ 1) right algebraic shift 1 place] divided
by (U) - A; REMAINDER - A+ 1

37

00

as

37

01

BO

Binary to Quarter
Word Byte
Extend

Discard (Ab5-32; place the remaining bits in
A 34-27' A 25-1S' A , 6-9' and A 7-O; zero fill A 3B •
A 26 • A ,7 • and Aa. (This instruction simulated
by library procedures and routines.)

37

02

aSH

Quarter Word
Byte to Binary
Halves Compress

Discard (A)3S' (A)27' (A), 7' and (A)a; place the
remaining bits in A 3l- 18 and A'5-O; (Ab3 A35-34; (A),5 - A 17- US ' (This instruction
simulated by library procedures and routines.)

37

03

SHa

Binary Halves to
Quarter Word
Byte Extend

Discard (A)35-34 and (A)17-16; place the
remaining bits in A 34-27' A 25-1a. A,e-9' and
A7-o; zero fill A 3B • A 26 • A ,7 • and As· (This
instruction simulated by library procedures and
routines.)

37

04

aoB

Quarter Word
Byte to Double
Binary Compress

Discard A 35 • A 26• A'7' Aa. A+ 1 35 , A+ 1 26,
A+ 1 ,7, and A+ ls; place the remaining bits in
A 27-O and A+ 1; (A)27 - A 3B- 2a . (This
instruction simulated by library procedures and
routines.)

Quarter Word
Byte to Binary
. Compress

A; REMAINDER -

Discard (A)3S' (A)26' (A)17' and (A)a; place the
remaining bits in A 31 -O; (A)31 - A 35-32' (This
instruction simulated by library procedures and
routines.)

L!

8804 Rev.1

PI:RRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

----~

r.bltJ C-2. In6truction RtJptJnoirtJ (continutJd)

Function
Code
(Octal)
f

j

Mnemonic

Instruction

Description

37

05

DBQ

Double Binary to
Quarter Word.
Byte Extend

Discard (A)35-2S; place the remaining bits from
A and A+ 1 in A 34-27' A 2!-18' A uS- 9' and A 7-o.
A+ 13 4-27' A+ 125-18' A+ 1 18-9' and A+ 17-0;
zero fill A 3!. A 28• A'7' A 8• A+ 136 , A+ 128,
A+ 1 17, and A+ 18, (This instruction simulated
by library procedures and routines.)

37

06

BA

Byte Add

Add the WO bytes in string SJO to the W 1
bytes in string SJ 1 and store the results in
string SJ2

37

07

BAN

Byte Add
Negative

Subtract the WO bytes in string SJO from the
W 1 bytes in string SJ 1 and store the results in
string SJ2

37

10-1j

-

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

40

0-17

OR

Logical OR

(A)

m

41

0-17

XOR

Logical Exclusive
OR

(A)

IXQBI

(U) ... A+ 1

42

0-17

AND

Logical AND

(A)

g

(U) ... A+1

43

0-17

MLU

Masked Load
Upper

[(U) ~ (R2)] IQBI
[(A) N NOT (R2)] - A+ 1

44,

0-17

TEP

Test Even Parity

Skip NI if (U)

45,

0-17

TOP

Test Odd Parity

481

0-17

LXI

Load X
Increment

(U) ... (Xa)35-18; (Xah 7-0 unchanged

47'

0-17

TLEM

Test Less Than
or Equal to
Modifier
Test Not Greater
Than Modifier

Skip NI if (U) 17-0 ~ (Xa), 7-0; always (Xah 7-0
+ (Xa)35-18 - Xa17-o

TNGM

(U) - A+1

g
Skip NI if (U) g

(A) has even parity
(A) has odd parity

5C~

0-17

TZ

Test Zero

Skip NI if (U)

== to

51

0-17

TNZ

Test Nonzero

Skip Nt if (U)

~

5~~

0-17

TE

Test Equal

Skip Nt if (U) - (A)

to

8eo. Rev.l

SPERRY UNIVAC 1100/80 System.

UILNU_ER

4x4 Capability Processor and Storage Programmer Reference

C-10
UPOATI LIVEL

PAGI

Tab/e C-2. /nmvction Repertoire (continued)

Function
Code
(Octal)
f

j

53

0-17

TNE

Test Not Equal

Skip NI if (U) : (A)

54

0-17

TLE

Skip Nt if (U) ~ (A)

TNG

Test Less Than
or Equal
Test Not' Greater

Mnemonic

Instruction

Description

55

0-17

TG

Test Greater

Skip Nt if (U)

>

(A)

56

0-17

TW

Test Within
Range

Skip Nt if (A)

<

(U) ~ (A+ 1)

57

0-17

TNW

Test Not Within
Range

Skip NI if (U) ~ (A) or (U)

60

0-17

TP

Test Positive

81

0-17

TN

Test Negative

=0
Skip Nt if (U)36 . = 1

62

0-17

SE

Search Equal

Skip Nt if (U) == (A), else repeat

63

0-17

SNE

Search Not Equal

Skip NI if (U)

64

0-17

SLE

Search Less
Than or Equal
Search Not
Greater

Skip NI if (U) ~ (A), else repeat

SNG

>

(A+ 1)

Skip Nt if (U)35

~

(A), else repeat

I

65

0-17

SG

Search Greater

Skip NI if (U)

>

(A), else repeat

66

0-17

SW

Search Within
Range

Skip NI if (A)

<

(U) ~ (A+ 1), else repeat

67

0-17

SNW

Search Not
Within Range

Skip Nt if (U) ~ (A) or (U)

70

0-17

JGD

Jump Greater
and Decrement

Jump to U if (Control Register)ja > 0; go to NI
if (Control Register)j. ~ 0; always (Control
Register)j. -1 - Control Registerja

71

00

MSE

Masked Search
Equal

Skip NI if (U)
repeat

g

(R2) - (A)

71

01

MSNE

Masked Search
Not Equal

Skip Nt if (U)
repeat

g

(R2l : (A)

71

02

MSlE

Masked Search
Less Than or
Equal

Skip NI if (U)
repeat

g

(R2) ~ (A)

>

(A+ 1), else repeat

g
g
g

(R2), else

(R2), else

(R2), else

-----b
8604 Rev.1

UP-NUMBM

p'5RRY UNIVAC 1100/80 System.

C-l1

4x4 Capability Processor and Storage Programmer Reference

r"bl.

UPDATI l.E'm.

PAGE

C-2. Instruction RtlpMtoirtl (continued)

FUlnction
Code
(Octal)
f

j

Mnemonic

Instruction

Description

MSNG

Masked Search
Not Greater

MSG

Masked Search
Greater

Skip NI if (U) ~ (R2)
repeat

71· 04

MSW

Masked Search
Within Range

Skip NI if (A) ~ (R2) < (U) ~ (R2) ~
(A+ 1) ~ (R2), else repeat

71

05

MSNW

Masked Search
Not Within
Range

Skip NI if (U) ~ (R2) ~ (A) ~ (R2) or (U)
~ (R2) > (A+ 1)
(R2), else repeat

71

06

MASL

Masked
Alphanumeric
Search Less
Than or Equal

Skip NI if (U) ~ (A2) ~ (A) ~ (R2), else
repeat

71

07

MASG

Masked
Alphanumeric
Search Greater

Skip Nt if (U) ~ (R2)
repeat

71

10

OA

Double-Precision
Fixed-Point Add

(A, A+1) + (U, U+1) -

71

11

DAN

Double-Precision
Fixed-Point Add
Negative

(A, A+ 1) - (U, U+ 1) -

71

12

OS

Double Store A

(A. A+ 1) -

U, U + 1

71

13

Dl

Doub'e Load A

(U, U + 1) -

A, A+ 1

71

14

DLN

Double Load
Negative A

- (U, U + 1) -

71

15

DlM

Double Load
Magnitude A

I·(U, U+1)

711

16

DJZ

Double-Precision
Jump Zero

Jump to U if (A, A+ 1) - : 0; go to NI if (A,
A+ 1) : !: 0 .

7;1

17

OTE

Double-Precision
Test Equal

Skip NI if.(U

7:~

00

IMI

Initiate
Maintenance
Interrupt

Send Attention Interrupt to Maintenance
Processor, if in Maintenance Mode, otherwise
NO-OP

71

03

;

>

(A~ ~ (R2), else

ram3

>

(A) ~ (R2), else

A, A+1

A, A+ 1

A, A+ 1

I - A, A+1

<

U+ 1) - (A, A+ 1)

.........

8804 Rw.1

1100/80 System.
4x4 Capability Processor and Storage Programmer Reference

SPERRY UNIVAC

C-12
'AGI

r.ble C-2. In.truction Repenoire (continued)

Function
Code
(Octal)
f

j

Mnemonic

Instruction

Description

72

01

SW

Store Location
and Jump

Relative P+ 1 -

72

02

JPS

Jump Positive
and Shift

0; go to NI if (A)35
1;
Jump to U if (A)35
always shift (A) left circularly one bit position

72

03

JNS

Jump Negative
and Shift

Jump to U if (A)35 - 1; go to NI if (A)35 :II: 0;
always shift (A) left circularly one bit position

72

04

AH

72

05

ANH

Add Negative
Halves

(A)36-18 - (U}35-18 - (A)35-18; (A)17-O - (U)17-O
- A17-O

72

06

AT

Add Thirds

(A)36-24 + (U)35-24 - A 35-24; (A)23-12 +
(U)23-12 - A 23-12; (A)11-O + (U), 1-0 - A 11 -O

72

07

ANT

Add Negative
Thirds

(A)35-24 - (U)35-24 - A35-24; (A)23-12 (U)23-12 - A 23-12; (A),,-o - (U)l1-O - A l1 -O

72

10

EX

Execute

Execute the instruction at U

72

11

ER

Executive
Request

Interrupt to MSR + 2228

72

12

-

Invalid Code

Causes Invalid Code Fault interrupt to MSR +
221 8

72

13

PAIJ

Prevent All
Interrupts and
Jump

Prevent all interrupts and jump to U

72

14

-

Invalid Code

Causes Invalid Code Fault interrupt to MSR
221 8

72

15

TAA

Test Relative
Address

Used to determine whether a relative address
is within a given relative addressing range
Transfer GRS areas defined in Aa to storage
starting at address U

.Add Halves

U 17-O; jump to U+ 1

=

=

(A)36-18 + (U)36-18; - (A)35-18; (A),7-O +
(U)17-O - A17-O

.

+

I

I

12

16

SRS

Store Register
Set

12

17

LRS

Load Register
Set

Transfer from storage starting at location U to
areas defined in Aa

73

00

SSC

Single Shift
Circular

Shift (Al right circularly U places

..

,-----D
880.. RIw.1

PERRY UNIVAC 1100/80 Systems

C-13

4)1:4 Capability Processor and Storage Programmer Reference

UI'-NUMIIIt

'AG!

Tab/II C-2. Innruction R"".rtoirtl (continuttd)

Function
Code
(IOctal)
f

j

Mnemonic

Instruction

Description

73

01

DSC

Double Shift
Circular

Shift (A, A+ 1) right circularly U places

73

02

SSL

Single Shift
Logical

Shift (A) right U places, zero fill

73

03

DSL

Double Shift .
logical

Shift (A, A+ 1) right U places, zero fill

73

04

SSA

Single Shift
Algebraic

Shift (A) right U places. sign fill

73

05

DSA

Double Shift
Algebraic

Shift (A, A+ 1) right U places. sign fill

73:

06

LSC

Load Shift and
Count

(U) - A; shift (A) left circularly until (A)3!
(A)3"; number of shifts - A+ 1

07

DlSC

Double load
Shift and Count

(U, U+1) - A, A+1; shift (A. A+1) left
circularly until (A, A+ 1h1 = (A, A+ 1ho;
number of shifts - A+ 2

7:31

10

LSSC

Left Single Shift
Circular

Shift (A) left circularly U places

7:31

11

LDSC

Left Double Shift
Circular

Shift (A. A+ 1) left circularly U places

7~1

12

LSSl

Left Single Shift
Logical

Shift (A) left U places. zero fill

7~l

13

lDSL

Left Double Shift
Logical

Shift (A, A+ 1) left U places. zero fill

7~1

14

a - 00-07

Invatid Code

Causes Invalid Instruction Fault interrupt to
MSR +,221 8

7~1

14

LOC
a .10

load Daycfock

Replace dayclock register value with fixed
storage value at start of next update cycle.

7:.

14

EDC
a - 11

Enable Day Clock

Enable the internal davclock of the processor.

7:1

14

DOC
a • 12

Disable Day
Clock

Disable the internal dayclock of the processor.

73:

"

=

I

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

~

4x4 Capability Processor and Storage Programmer Reference

UPOATlLEVB.

r.ble C-2. In$truction Repertoire (continued)

Function
Code
(Octal)

f

j

Mnemonic

Instruction

Description

73

14

SOC
a =- 13

Select Day Clock

Select internal dayclock

73

14

MDA
a - 14

Diagnostics

'Generates A and A+ 1 operands, U ope.r and ,
U+ 1 operand, Store results A, A+ 1 in GRS
addresses 62 and 63.

73

14

MOB

Diagnostics

Generates A and A+ 1 operands, U operand,
U+ 1 operand, Store results A, A+ 1 in GRS
addresses 62 and 63.

a

==

15

73

14

a= 16,17

Diagnostics

Undefined, will NO-OP

73

15

SIL
a =- 00

Select Interrupt
Locations

(U)a-o -

73

15

-

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

a

=-

01

MSR

73

15

LBRX
a =- 02,

Load Breakpoint
Register

Transfer operand to Breakpoint Register

73

15

LQT
a =- 03

Load Quantum
Timer

P,lace full-word operand in Quantum Timer

173

15

III X
a - 04

Initiate
Interprocessor
Interrupt

Interrupt processor specified by operand
address value

73

15

SPIO

Store Processor
10

Store: binary serial number in first third;
2-character Fieldata revision level in second
third; processor features in the fifth sixth;
processor number in last sixth of operand

a - 05

13

15

RAT
a - 06

Reset
Auto-Recovery
Timer

Reset auto-recovery timer in system transition
unit

73

15

TAP

Toggle
Auto-Recovery
Path

Toggle path selection after each auto-recovery
attempt

a - 07

I

S804 Rev.1

SPERRY UNIVAC 1100i80 Systems

~,

'If'-HUMIIJI

Capability Processor and Storage Programmer Reference

C-16
PAGI

r.bltl C-2. Instruction Rtlptlnoirtl (continutldJ

Function
Code
((:lctal)
f

73

j

15

Mnemonic

Instruction

LB
a~

Description

Load Base

Place operand bits 0 through 17 in base value
field of BDR specified by bits 33 and 34 of Xx

10
,

73

15

LL
a- 11

Load Limits

Place operand bits 15 through 23 and 24
through 35 in BOR limits fields specified by Xx
bits 33 and 34

73

15

LAE
a- 12

Load Addressing
Environment

Place the double-word operand in GRS
location 046 and 047 and place the limits and
base values of the four Bank Descriptors
specified by this operand in four respective
Bank Descriptor Registe'rs

73,

15

SQT
a - 13

Store Quantum
Time

Store Quantum Timer value at the operand
address location. Executing this instruction
has no effect on 029.

73:

15

LD
a- 14

Load Designator
Register

Place full-word operand in Designator Register

731

15

SO

Store Designator
Register

Store Designator Register contents at location
specified by operand 'address

-

a- 15
7~1

15

UR
a- 16

User Return

(U

7:1

15

SSS
a- 17

Store System
Status

Store two system status words at the location
specified by operand address

7:!

16

-

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR +2218

7:~

17

TS
a - 00

Test and Set

If (U)30 - 1, Generate Test and Set interrupt: if
(U)30 =- 0, go to ,NI, if U ) 200, then 018 U 35-30; (U)29-0 unchanged

7:3

17

TSS
a - 01

Test and Set and
Skip

if (U)30 -

+ 1) - Designator Register; jump to address
specified by (U)23-o using new register set

U )

1, go to NI; if (U)30 - 0, skip NI, if
200, then 01 8 - U3t5-30; (U)29-0

unchanged

7:3

17

TCS
a - 02

Test and Clear
and Skip

If (U)30 - 0, perform NI; if (U)30 - 1. skip NI.
if U ) 200 clear (U)3t5-30; (U)29-0 unchanged

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

~

4x4 Capability Processor and Storage Programmer Reference

C-16
PAGE

UIIOATllEVIL

Function
Code
(Octal)
'. f
!

I

j

Mnemonic

Instruction

Description

73

17

a - 03

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

73

17

TSA
a - 04

Test and Set
Alternate

Test bit position 14; if (U),4 =- 1, interrupt; if
(U), 4 - 0, take next instruction and set bits 00
through 14 to one.

73

17

TSSA
a - 05

Test and Set and
Skip Alternate

If (U),4 == 1, take next instruction; if (U)14 == 0,
skip next instruction and set bits 00 through
14 to one.

73

17

a - 06-17

Invalid Code

Causes Invalid Instruction Operation Fault
interrupt to MSR + 22 18

74

00

JZ

Jump Zero

Jump to U if (A)

74

01

JNZ

Jump Nonzero

Jump to U if (A) : :: 0; go to NI if (A)

74

02

JP

Jump Positive

Jump to U if (A)3S

74

03

JN

Jump Negative

Jump to U if (A)35 == 1; go to NI if (Abs

74

04

J
JK

Jump
Jump Key

74

05

HJ
HKJ

Halt Jump
Halt Keys and
Jump

Jump to U if a == 0 or if a == set JUMP
SELECT control circuit; go to NI !f neither is
true
Stop if a=-O or if [a-field ~ set STOP
SELECT control circuits] t 0; on restart or
continuation jump to U

74

06

NOP

No Operation

74

07

AAIJ

Allow All
Interrupts and
Jump

Allow all interrupts and jump to U

74

10

JNB

Jump No Low Bit

Jump to U if (A)o =- 0; go to Nt if (A)o =- 1

74

11

JB

Jump Low Bit

Jump to U if (A)o -

74

12

JMGI

Jump Modifier
Greater and
Increment

Jump to U if (Xa), 7-0 > 0; go to NI if (Xa), 7-0
~ 0; always (Xa h7-O + (Xa)35-18 - Xa,7..o

74

13

LMJ

Load Modifier
and Jump

Relative P

== ::

==

0 go to NI if (A) : :: 0

== ::

0

0; go to NI if (A)3S == 1

==

0

. Proceed to next Instruction

+

1; go to Nt if (A)o

1 - (Xa)17".o; jump to U

=0

I

8e04 Rev."

SPERRY UNIVAC 1100/80 Syatems

C-17

~Capability Processor and Storage Programmer Reference

Uf'.HUMIIR

r.bl.

'AGE

C-2. In6vuction RepelTtJi,.. (continued'

Function
C()de
(Oc:tal)
t--r-.'--~

j

f

74

14

Mnemonic

JO
21 -

74

14

74

14

74

14

=:

=-

=- 0

Jump Overflow

Jump to U if 01

Jump Floating
Underflow

Jump to U if 021
021 - 0

= 1, clear 021; go to NI if

01

Jump Floating
Overflow

Jump to U if 022

=-

02

..'FO

a

Description
1; go to NI if 01

00

..IFU
21 -

Instruction

JOF

1, clear 022; go to NI if

022 - 0

= 1, clear 023; go to Nt if

= 03

Jump Divide
Fault

Jump to U if 023

il

=- 04-17

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

Jump No
Overflaw

Jump to U if 01

74

14

il

74

15

.JNO
.:1

=-

00

023

=-

0

-=

0; go to NI if 01 =- 1

= 0; go to NI if 021

-

= 0; go to NI if 022

-= 1;

15

.JNFU
;s =- 01

Jump No
Floating
Underflow

Jump to U if 021
clear 021

74

15

JNFO
a - 02

Jump No
Floating Overflow

Jump to U if 022
clear 022

74

15

JNOF

a - 03

Jump No Divide
Fault

Jump to U if 023 == 0; go to NI if 023
clear 023

Causes Invalid Instruction Fault interrupt to
MSR + 2218

74

I

=-

1;

1;

74

15

a - 04-17

Invalid Code

74

16

JC

Jump Carry

74

17

JNC

Jump No Carry

Jump to U if 00 - 0; go to NI if DO -

75

00

Invalid Code

Causes IOU to return a condition code of 3 to
the CPU, indicating instruction not available

75

01

Stan I/O Fast
Release

Initiates operation on subchannel specified by
bit 00 through 15 of CAW

SIOF

. Jump to U if 00

=-

1; go to NI if 00 - 0
1

8104 Rev.1

SPERRY UNIVAC 1100/80 Sytteml

UNAIMIIR

4x4· Capability Processor and Storage Programmer Reference

C-18
fIIAGE

r.ble C-2. Instruction Repertoire (continued)

Function
Code
(Octal)')
f

j

Mnemonic

Instruction

Description

75

02

-

Invalid Code

Causes IOU to return a condition code of 3 to
the CPU, indicating instruction not available

75

03

TSC

Test Subchannel

Interrogates the channel and subchannel

75

04

HDV

Halt Device

Terminates current operation on channel and
subchannel

75

05

HCH

Halt Channel

Terminates current operation on channel

75

06,07

-

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

75

10

LCR

Load Channel
Register

Load the interrupt mask register or load the
channel base register

75

11

LTCW

Load Control
Words

Loads the status table subchannel

75

12-1 i

-

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

76

00

FA

Floating Add

(A) + (U) - A; RESIDUE - A+ 1 if 017

7'6

01

FAN

Floating Add
Negative

(A) - (U) -

76

02

FM

Floating Multiply

(A) x (U) - A (and A+ 1 if 017 = 1)

76

03

FD

Floating Divide

(A) divided by (U) - A; REMAINDER - A+ 1 if
017 - 1

76

04

LUF

Load and Unpack
Floating

I (U) 134-27

-"6

05

LCF

Load and
Convert to
Floating

(U)35 - A+ 135 , [NORMALIZED (U)h6-0 A+ 12 5-0; if tUbs =- 0, (A),-O t NORMALIZING
COUNT - A+ 134-27; if tUbs == 1, ones
complement of [(A) 7-0 t NORMALIZING
COUNT] - A+ 134-27

16

06

MCOU

Magnitude of
Characteristic
Difference to
Upper

II (A) 135-27 -I

=1

A; RESIDUE - A+ 1 if 017 = 1

- A 7-O' zero fill
{U)26-00 - A+ 126-00' sign fill
(Ul 35 - A+ 135

A+ 135-9

(U) 135-27

I-

A+ 18-0; zeros -

~_"~A~.I
__

/S_O_s_~._m_.-...___________________________~___________~_~__19_______

S_P_ER_R_.Y_U_N_'
V_A_C__
11_00
___
__and Storage Programmer Reference
4x4
Capability
Processor

1 ___

r.bl.

UPDATI LIYIL

flAGE

C-2. Instruction R.p.rto;r. (continutJd)

Function
Code
(Oc~tal)

f

Mnemonic

j

Instruction

Description

76

t07

CDU

Characteristic
Difference to
Upper

1(A) 135-27 A+ 135-9

76

10

DFA

Double-Precision
,Floating Add

(A, A+1) + (U, U+1) -

76

11

DFAN

Double-Precision
Floating Add
Negative

(A, A+1) - (U, U+1) -

A, A+1

76

12

DFM

Double-Precision
Floating Multiply

(A, A+1) x (U, U+1) -

A, A+1

76

13

DFD

Double-Precision
Floating Divide

(A, A+ 1) divided by (U, U+ 1) -

76

14

O'FU

Double Load and
Unpack Floating

I (U,

76

15

DFP, DLCF

Double Load and
Convert to
Floating

(Ubs - A+ 13S ; [NORMALIZED (U, U+ 1)]69-0
- A+ 123-0 and A+2; if (U)35' (Aho-o !
NORMALIZING COUNT - A+ 134-24; if (Ula5
1, ones complement of [(A) 10-0 :
NORMALIZIN.G COUNT] - A+ 134-24

I (U) 135-27 - A+ 18-0; sign bits -

A, A+1

A, A+ 1

U+ 1) r70-80 - A,Q-O, zero fill; (U,
U+1hs9-36 - A+1 23-0' sign fill; (U, U+1)35-0
-A+2
)

=

76

16

FEl

Floating Expand
and Load

If (U)3S - 0; (U)36-27 + 16008 - A 35-24' If
(U)3S - 1; (U)35-27 - 16008 - A35-24 (U)28-3
- A 23-0; (U)2-O - A+ 135-33; (U)3S - A+ 132 -0

76

17

FCL

Floating
Compress and
Load

If (Ubs - 0; (U)35-24 - 1600 s - A 35-27' If
1; (U)35-24 + 16008 - A3!5-27 (U)23-O
- A28-3; (U + 1)315-33 - A2-O

Invalid Code

Causes Invalid Instruction Fault interrupt to
MSR + 2218

77

0-17

•.

(Uba -

8804 Rev.1

SPERRY UNIVAC 1100/80 Systeml

C-20

4x4 Capability Processor and Storage Programmer Reference

tJP-NIJMaIt

UP'DAT! LIVIL

'AGE

r.bl. C-3. 0".,., vs Mn.monic In6truction Cod.
First Digit

Function Code - Second Digit
0

1

2

3

4

5

6

7

SM
SMA
LNMA

S
SR
A
AA
A
AX

(1 ),

S
SX
AM
AMA
LXM

(see below)

l

SN
SNA
lM
LMA
BT

2

AU

S
SA
LN
lNA
ANU

3

MI

MSI

MF

4

OR

XOR

AND

L
LR
Bytes
(see
below)
MLU

5

TZ

TNZ

TE

TNE

6

TP

TN

SE

7

JGD

0
1

LA

Funct.
Code

First j
Digit

07
33

0
1
0
1

BI

37

0

OB

71
72

0
1
0

73

0

01

AN
ANA
AN
ANX
DSF

TEP

TOP

LXI

TlE
TNG
SNE
SlE
SNG
See Below

TG

TW

TlEM'
TNGM
TNW

SG

SW

SNW

OF

ANM
ANMA
L
LX
Bytes (see
below)

Second j Digit
0

1

2

3

4

5

6

7

BM

BMT
BDI
Ba

lDJ
BTT
IB
OHB

llJ
BTC
olB
BHQ

LPO
BC
BF
aDB

SPo
BPo
BOF
DBa

PoB
FB
BA

LBJ
EDIT
DFB
BAN

(2)

MSG
OL
JNS
PAIJ
oSL
loSl
IN
LMJ
TSC

MSW
oLN
AH

MSNW
oLM
ANH
TRA
DSA

MASL
OJZ
AT
SRS
LSC

MASG
OTE
ANT
LRS
DlSC

(6)

(7)

NOP
JC

AAIJ
JNC

HDV

HCH

FO
OFD

LUF
DFU

lCF

MCDU

(8)

FEl

CDU
FCL

1

1
1

74

0

75

0
1

76

0

1

:

1

MSE
OA
IMI
EX
sse
lsse
JZ
JNB
lCR
FA
oFA

MSNE
DAN
SW
ER
oSC
lose
JNZ
JB
SIOF
lTCW
FAN
oFAN

OS
JPS
SSL
lSSl
JP
JMGI
FM
OFM

NdTES:

sn. $AS. SAZ INC. DEC. INC2. DEC2, ENZ

t.

SZ SNZ, SPt, SNt, SFS.

2.

MSLE. MSNG

3.

LDC. EDC, DOC, SOC. MDA, MOB

SSA
(3)

(4)

J.JK

HJ,HKJ

(5)

~.,

Sp_e_R_RV.~U_N_W_A_C__'_'00__1_8_0_S_~__._m_.____________________________~__________~~_C_-_2_'______

1____
4x4

Capability Processor and Storage Programmer Reference

4.

S"L. LBRX, Ll'JT, 111)(, SPIO, RAT, TAp, LB, LL. LA£. SOT, LD, SO, UR. SSS

5.

T.S. TSS,

8.

JjO. JFU, JFO, JDF

7.

JlVO, JNFU, .INFO, JNDF

I.

()~FP,

TC~~

DLCF

TSA, TSSA

UfIIMTi LIYIL

'AGI

8604 Rev.1

u......,..... ;

~PERIRY
UNIVAC 1100/80 Systems
4)(4 Capability Processor and Storage Programmer Reference

---,----

0-1
!'AGE

Appendix D. Code Conversions

D. 1. ASCII and Fieldata Code Conversion Tables
Code!I,"Which ,.'so represent collating se$luence, are given in octal in Tables 0-1 and 0-2.
ASCII codes from 00 8 to 378 are used for communications. They are format, separator, and control
chara4::ters. These are not converted into Fieldata.
The ~ISCII symbols represented by codes 408 to 137 8 are converted into the identical Fieldata
symbc)ls, except that the quotation marks symbol (428) is converted into a lozenge (76 8), the
circunraffex (13E5 8 ) is converted into a delta (04 8 ), underscore (137 8) is converted into a not equal sign
(77 8),
There are no remaining unique Fieldata symbols into which to convert the balance of the ASCII
symbc)ls, reprelsented by codes 1408 to 177 8, (these codes are shown boxed in Table 0-2), so most
of these codes are "folded" over codes 100 8 to 137 8 (by clearing bit 5, which amounts to subtracting
40 8), This means that ASCII codes 101 8 (A) and 14 18 (a), for example, are both translated as if they
were Icode 101 8 (converted to Fieldata 06 8 for A). Two exceptions to this general rule are the ASCII
opening brace (173 8) and closing brace (175 8 ) which are converted to Fieldata question mark (54 8 )
and exclamaticln point (55 8 ), respectively, to satisfy overpunch sign considerations. The Operating
System folds all codes from 1408 to 177 8,

8104 Rev.1

SPERRY UNIVAC 1100/80 Syateml

UNIMI. . . .

4x4 Capability Processor and Storage Programmer Reference

UPOATI LIVIL

r.bltl 0- t. Fitlld.t. to ASCII Codtl Convtlrsion

ASCII
Fieldata Code
(Octal)

Fieldata
SO-Column
Card Code

Symbol

00
01
02
03

7-8
12-5-S
11-5-8
12-7-8

04
05
06
07

11-7-8
(blank)
12-1
12-2

10
11
12
13

12-3
12-4
12-5
12-6

C

14
15
16
17

12-7
12-8
12-9
11-1

G
H
I

20
21
22
23

@

[
]

#
A

(space)
A

B

Octal Code

100
133
135
43
136
40
101
102

Symbol

@

[
]

#

.
(space)
A

B

103
104
105
106

C

G

J

107
110
111
112

11-2
11-3
11-4
11-5

K
L
M
N

113
114
115
116

K
L
M
N

24
25
26
27

11-6
11-7
11-8
11-9

0
P

117
120
121
122

0
P

30
31
32
33

0-2
0-3

0

e
F

Q

R

0-4

S
T
U

P-5

V

0-6

W

0-7

X

34
35
36
37

0-8

y

0-9

Z

40
41
42
43

12-4-8
11
12
12-6-8

44
45

3-8
6-8

H
I

J

a

R

127
130
131
132

W

>

75
76

I

F

S
T
U

+
<

-

E

123
124
125
126

51
55
53
74

)

- (minus)

0

V

X
Y

Z
)

- (minus)

+
<

:Ill

>

~~~_4~~~~t
S_P_E_R~.~Capability
__U_N_IV_A_C____
"_00
____
/a_o_s_va
__
.m_.___________________________
~________~___~_3______
--.--J '4x4
Processor
,and
Storage Programmer Reference

--:Jt

I _ ! "_ _

UPOATI LIVIL

r.b/II 0-1. Fill/d.,. to ASCII Code Convllrsion (continued)

ASCII

Fieldata Cc.de
(Octal)

Fieldata
SO-Column
Card Code

Symbol

Octal Code

Symbol

8&
$

46
44

&
$

*(

52
50
45
72

*(
%
: (colon)

77
41
54
134

?
!
,(comma)
\

eo

0
1

46
47

2-8
11-3-8

50
51
52
53

11-4-8
0-4-8
0-5-8
5-8

54
55
56
57

12-0
11-0
0-3-8
0-6-8

60
61
62
63

0
1
2
3

0
1
2
3

61
62
63

64
66
66
67

4

4
5
6
7

64
65
66
67

4
5
6
7

70

8

8

71

9

72
73

4-8
11-6-8

9
'(apostrophe)

70
71
47
73

S
9
'(apostrophe)

74
75
76
77

0-1
12-3-8
0-7-8
0-2-8

5
6
7

-

%
: (colon)
?
!
,(comma)

\

;

/
.(period)
CI

= or

stop

57
56
42
137

~

3

/
.(period)
"

PlAGI

..........

81041 Rev.1

SPERRY UNIVAC 1100/80 Syetemt

4x4 Capability Processor and Storage Programmer Reference

ASCII
Octal
Code
40
41
42
43
44
45
46
47
50
51
52
53

Symbol

System Console
CRT
Incremental
Symbol
Printer Symbol
(space)
(space)
!
!

SP
!

Keyboard
Symbol
(space bar)
!

It

It

It

It

#

#

#

#

S

S

S

S

%
&
• (apos.)

%
&
• (apos.)

%
&
• (apos.)

%
&
• (apos.)

(
)

(
)

(
)

(
)

*

*

*

*

+

+

+

+

54
55
56
57

, (comma)
- (minus)
. (period)

, (comma)
- (minus)
. (period)

, (comma)
- (minus)
. (period)

• (comma)
- (minus)
. (period)

/

/

/

/

60
61
62
63

0
1
2
3

0
1
2
3

0
1
2
3

0
1
2

64
65
66
67

4
5
6
7

4
5
6
7

70
71
72
73

8
9

Octal
Code
05
55
76
03
47
52
46
72
51
40
50
42

Fieldata
Symbol
(space)
!
c
=IF

S
%

&.
• (apos.)
(
)

*

+

56
41
75
74

, (comma)
- (minus)
. (period)

0
1

3

60
61
62
63

4
5
6
7

4
5
6
7

64
65
66
67

4
5
6

8
9

8
9

8
9

8
9

: (colon)

: (colon)
;

: (colon)
;

: (colon)

;

70
71
53
73

;

- - -

=:II

100
101
102
103
104
105
106
107

74
75
76
77

UPOAT1 LIYIL

<

>

<

<

<

>

>

>

@

@

@

@

A

A

A

A

B
C

B
C

B
C

B
C

0

0

0'

D

E

E

E

E

F

F

F

F

G

G

G

G

1

1

7

1

43
44
45
54

/

2
3

7

: (colon)
,

<
:=

>
7

00
06
07
10

@

11
12
13
14

0

A

B
C

E
F

G

PERRY
~
-----8e04 Rev.1

UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

IJP.oMJMIM

r.bl. 0-2. ASCII to Fitlld.t. Cod. COnlltlFS;On (continu~)

ASCII
Symbol

Keyboard
Symbol

110
111
112
113

H
I

H
I

H
I

H
I

J

J

J

K

K

J
K

L

L
M
N
0

L
M
N

M
N

0

0

P
Q
R
S

P
Q
R
S

P
Q
R

T
U

T
U

V
W

T
U
V
W

V
W

V
W

130
131
132
133

X
Y

X
Y

X
Y

X

Z

Z

Z

Z

[

[

[

134
135
136
137

\
]

\
]

\
]

114
115
116
117

*

.*

System Console
CRT
Incremental
Symbol
Printer Symbol

Octal
Code

M
N

0

120
121
122
123

P
Q
R

124
125
126
127

T
U

S

..

..

..

K

L

S

Octal
Code

Fieldata
Symbol

15
16
17
20

H

21
22
23
24

L
M

25
26
27
30

P
Q
R

31
32
33
34

T
U

I

J
K

N

0

S

V
W

X
y

[

35
36
37
01

\
]

57
60

\

04

Y

.

Z
[

]

-

-

-

-

77

f.l
t

140
141

@

a*

A··

a*

A··

00
06

A*·

through

through

through

through

through

through

through

172
173

z*

Z··

z·

Z··

I

I

I

37
54

Z·*

[

174
175
176
177

:

..

:

\

I

I

I

]

57
55
04
77

\
!

-

OEL

Ilowercase alphabet
Uppercase alphabet

-

(no key)

-

'/.

.

-

@

?

t:,.

f.

1804 Rev.1

SPERRY UNIVAC 1100/80 Systems

UfLMIMIIR

4x4 Capability Processor and Storage Programmer Reference

I

0.2. Special Characters in ASCII
The special characters in ASCII are:
SP
DEL

designates space, which is normally nonprinting.
designates delete, and has a code of all 1 bits. This code eliminates the previous character
- even on paper tape or other nonerasable medium.

Definitions of the 32 ASCII control characters, codes 00 8 to 378:
00 NUL Null - all zero character which may serve as time fill
01 SOH Start of heading
()2 STX Start of text
()3 ETX End of text
()4 EaT End of transmission
05 ENQ Enquire - ·Who Are You?06 ACK Acknowledge - ·Yes·
07 BEL Bell - human attention required
10 BS
Backspace
11 HT
Horizontal tabulation
12 LF
Line feed
format effectors for
printing or punching
Vertical tabulation
13 VT
1 4 FF
Form feed
15 CR
Carriage return
16 SO
Shift out - nonstandard code follows
Shift in - return to standard code
17 SJ
20 OLE Data link escape - change limited data communication control

21 DC1
22 OC2
230C3
24DC4
25 NAK
26 SYN.
27 EST
30 CAN
31 EM
32 SUB
33 ESC
34 FS
35 GS
36 RS
37 US

}

Device control for turning on or off auxiliary devices

Ne9at!ve acknowledge - RNa"
Synchronous idle - from which to achieve synchronism
End of transmission block - relates to physical communication block
Cancel previous data
End of medium - end of used, or wanted. portion of information
Substitute character for one in error
Escape - for' code extension - change some character interpretations
File separator
}
These information separators are ordered in
Group separator
descending hierarchy_ They are followed by
Record separator
ASCII 40 8 (space), which can also be thought
Unit separator
of as a word separator.

I~Capability Processor and Storage Programmer Reference
SPERfN' UNIYAC 1100/80 Systems

Appendix E. Storage Configurations

E.1. General
The 1100/80 Systems with 4x4 capability allow expansion to three or four processor configurations.
These! configurations require a system transition unit (STU) and a storage system having different
chara,cteristics than those used in systems whose maximum configuration cannot be expanded
beyond two processors.
The rnaximum storage configuration consists of eight partitionable storage interface unit (SlU)
segm l9nts and eight partitionable main storage unit (MSU) banks. With this number of components
there is a wide variety of possible storage configurations. Illustrations and data presented in this
Appet1dix provide a better understanding of the flexmbility and restrictions of these configurations. The
instaillation may use this information as a reference, as a guide to storage configuration options, as
a guide to partitioning, and as an aid to reconfiguring for multiple applications or to recover after the
loss clf a storalge component.
The 11100/80 Systems storage system consists of large capacity, low cost MSUs: interfaced by
moderate capacity, high speed storage buffers located in the SlU. The high speed storage buffers
are u~sed to achieve increased performance from the relatively low speed MSUs. Each MSU can be
dividftd into two separate banks. Each SIU contains from one to four logically independent storage
buffelrs called segments. A main storage bank has a 2-port multi module access (MMA) unit which
allows access by two Stu segments and provides a means for common accessing of main storage.
AU pc»ssible stc)rage configurations are not shown in this subsection; however, any combination not
shown can be derived from the information presented in this subsection.

E.2. Definition of Terms
Terms pertaining to the storage configurations are defined in the following listing.
Application

This term is used in the STU sense. i.e., it is an operable partition of
the total configuration at a site.

Cluster

Standard system components are grouped into clusters 0 and 1.
Cluster 0 components are central processor unit (CPU) 0, CPU 1,
input/output unit (IOU) 0, IOU 1, SIU segments 0, 2, 4 and 6. Cluster
1 components are CPU 2, CPU 3, IOU 2, IOU 3 and SIU segments 1,
3, 5, and 7. MSUs are not cluster-oriented.

leott Rev.1

SPERRY UNIVAC 1100/10 Systema

UNII . . .

4x4 Capability Processor and Storage Programmer Reference

E-2
UfllDATI LEVEL

'AGI

Failure

Failure of a storage component refers to a hardware condition such
that the component is not usable in the application, i.e., it is offfine or
otherwise inaccessible.

Loss

Refers to either removal or failure of a component.

MSU

Main storage unit. A storage cabinet containing one or two banks.

MSU Bank (also Bank)

A portion of main storage which is partitionable at the STU.

F'emoval

Removal or addition of a storage component refers to a planned event.

Segment/bank

Qne SIU segment interfacing with one MSU bank. Applicable to single
cluster system only.

~;egment/ cabinet

One Stu segment interfacing with one MSU cabinet. A cabinet
contains two banks. Applicable to both single and double cluster
systems.

StU-Generated MSR .

The system hardware allows the s_etting of module select register
(MSR) to be hardware generated rather than manually set at the STU.
This is not usable for bootstrap into SIU lower when unusable
addresses exist in the lower half. MSR must then be set manually.

SIU Half
l(a180 Half)

This is two interleavable Stu segments (0 and 2, 4 and 6, 1 and 3, or
5 and 7). A half can exist, however, with only one of the SIU segments.
An SIU half represents an address range. either those words above
40M a (SIU upper) or below 40M a (SIU lower).

StU Segment
(also Segment'

A unit of cache memory containing 4K words, partitionable at the STU,
which may service one MSU which may have one or two MSU banks.

Unusable Addresses

It is possible to configure an application in which interleaved
components are of unequal sizes, and addresses in one part are not
satisfied by corresponding addresses in the other part of the
interleave. This occurrence is referred to as unusable addresses.

E..3. Address Interleave
The following examples illustrate the octal address distribution for vario'us storage configurations.
There are two basic options for storage configurations. The first is a segment/cabinet storage
configuration with examples in E.3. 1, and the second is a segment/bank storage configuration with
examples in E.3.2.
The addresses shown in the MSU bank configurations are the lower absolute address bits, in octal,
which represent the distribution of the storage addresses. Absolute addresses consist of 24 bits.
labeled bit positions 23-0, in which bit 0 is.the least significani Address interleaving between the
requesters and the SIU segments is controlled by the contents of bit position 2. Address interleaving
between the SIU segments and the MSU banks is controlled by the contents of bit position 3. The
contents of bit position 23 is used by the requesters to determine whether the request is sent to SIU
upper or SIU lower. This divides the addressing range into addresses below 40M a (SIU lower) and
addr"ses above 40M a (SIU upper). Note that there is no interleave between SIU halves, and that
the address ranges do not have to be of equal size in two SIU halves.

I

8004 Rev.l

SPERRY UNIVAC 1100/80 System.

~
____.~ Capability Processor and Storage Programmer Reference

E.3.1. Address Interleaving in Segment/Cabinet Storage Configurations
E.3. 1. 1. One Segment/One Bank

CLUSTER 0

. - LOWER

SEG~ENT1

EIANK 0
All
Addr......

NOTE.~:

2.

Unuubl• .,dd,...... do not occur.

E-3
flAG.

8S04 Rev.1

SPeRRY UNIVAC 1100/80 Sv-te"'-

.

4x4 Capability Processor and Storage Programmer Reference

UNIUMI8I

E.3.1.2. One Segment/Two Banks

CLUSTER 0
-

LOWER
SEGMENT

o

BANKO

BANK 1

0-7
20-27

10-17
30-37

NOTES:

2.

Th. b6nks m,,,SI ~ ~u., in siz. 01' unus.bl••ddfW...S occur. If th.y .,.. not ~u., in siz••nd .1'. in th. low.,. h.d,
MSR c6nnot ~ S« to SIU g.net8ttHJ fOl' boot6tMp into th. low.I' h." 6nd would h... to ~ m.nu.'1y Ht on th. STU.

8804 ArI.1

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

UNtU....

1.~-6

E.3.1.:3. Two Segments/Two Banks

CLUSTER 0
- - LOWIeR

~eG~ENT SEG~ENT

BANK 2
4-7
14-17

NOTES:

2.

T'I,.

blinks must btl equill in siz. or unuubl. IIddl'.utlJl occur, If thtl,!II1'. not tlquill in siztl lind "I'tI in thtl lowtll' hlllf,
MSR Cllnnot btl 'tlt to SIU gtmtll'lItlHllol' bootstf'lIp into thtl lowtlf' hilI! lind would hllve to b. mllnulIlI'! ••t on thtl STU.

...........

1804 Rev.1

SPERRY UNIVAC 1100/80 SystfHM

4x4 Capability Processor and Storage Programmer Reference

E.3.1.4. Two SegmentsIThree Banks - Basic

CLusnR 0
-

LOWER
SEGMENT

SEGMENT

o

2

BANKO

BANK 1

0-3
20-23

10-13
30-33

BANK 2

4-7
14-17

24-27
34-37

NOTES:

3.

T'htI two Nnlt. conn.ctMJ to the ume H(/mtlnt mu., btl tItIU1I1 ln size lind the bank conntICt«i to the othe, segment
mu" h..,. a 6iztI «IuIII to the totIII
the othlll' two blink. or unuuble addr..... occur. If unuuble addre"e. occur
and the b."k6 a,. ln the lowtlt' hlllf, MSR cannot be set to SIU I1t1ntll'lltwJ for bootstrllP into the lower half and would
hllfltl to be mMUllily Stlt on the STU.

0'

S804 Rev.1

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

~a

E-7
UPDATlI.IYEL

PAGE

E.3.1.:I. Two SegmentsIThree Banks - Alternate

CLUSTER 0

- - LOWER

~EG~ENT SEG~ENT

BAI~K

0

01-3
101-13
201-23
301-33

BANK 2

BANK 3

4-7
24-27

14-17
34-37

NOTES:

3.

mil two bani,. cDnnllCt«l to mil UtrN ugm""t mu.t bll tHlUM in siZII and thtl bank conntICtN to thll Oth.f .lIgm"nt
a ~rizll tHlU61 tD m" tOrM of mil Othllf two blink. or unuubltl .ddT..... occur. "'unuubltl .dd,.u". OCCUf
a/td mil bank••f. in thll low.,. hMf, MSR unnot btl Ht to SIU 9"".,.at«l fOf bootstrap into mtl IOW.f half and would
h4WII to bll mllnulllly .lIt on mil STU.
mUIIt hll.,.

8804 Rev.1

SPERRY UNIVAC 1100/80 Syfteml .

4x4 Capability Processor and Storage Programmer Reference

UN«JMII1II

E-a
IJIIOATI LIYIL

'AQI

-

E.3.1.S. Two Segments/Four Banks

CLUSTER 0
-

LOWER
SEGMENT

SEGMENT

o

2

BANK 0

BANK 1

BANK 2

BANK 3

0-3
,20-23

10-13

4-7
24-27

14-17
34-37

30-33

NOTES:
1'.

IntlJrle..,. berwHn H(Jmenr. 0 .nd 2 on bit 2.

-,

.oil..

3.

All b6ltt6 mU6t I» equ.' in .w QI' unuubl. MldrtJaft occur. If unuuble .dd,.".... Qt:t:u, snd the IMnk6 .,.. in the
10M1M' hMf. MSR unnot I» Ht to SIU genenr.d for boot6tnp into the IOWM hslf .nd would h..,. to I» msnu.lly Ht
on the STU.

880~Rev.1

U~MIIER

SPeRRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

E-9
'AGE

'--------------------------------------------------------~----------~----------

E.3.1.'7. ThreEt Segments/Six Banks

CLUSTER 0
- - LOWER

- - - - - uppeR

[SEG~ENT SEG~ENT SEG~ENT

BANKO

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

0-3
2'0-23

10-13

4-7
24-27

14-17
34-37

0-7
20-27

10-17
30-37

30-33

NOTES:

3.

I.r.nk$ 0, 1, :Z••nd 3 must be of tlqu.' size. 4nd benk. " 6nd 5 mu.t be of (#qu.' ./Z. Of' unuuble ~df'''''. occur. It
;Ir m:c.pt.bl., fOf' IMnk. " .nd 5 to cont4in m",e ", I".. 6ttJr8ge then the othtlf' b8nk.. "unuubl. 4ddf'..... OCCUf' .nd
tfJe b.nk• • ,. in the lowtlf' h.11. MSR c.nnot b. $lit to SIU g.nef'.ted fof' boo,."..p into the low.,. h." md would h6t1t1
to be m.nu.,I/y ••t on the STU,

1104 Rev.1

SPeRRY UNIVAC 1100/80 System.

E-10

4x4 Capability Processor and Storage Programmer Reference

'AG!

E.3.1.8. Four Segments/Eight Banks

CLUSTER 0
-

LOWER

- - - - - UPPER

--

SEGMENT

SEGMENT

SEGMENT

SEGMENT

o

2

4

8

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 8

BANK 7

0-3 .

10-13
30-33

14-17
34-37

0-3

20-23

4-7
24-27

10-13
30-33

4-7
24-27

14-17
34-37

20-23

"'OTES:

•.,.

S.nkll O. t. Z. MId 3 mUlIt b. of tHlulII • • MId Nnu II. 6. 8, .nd 7 mwt b. of tHlu61 • • or unu••bI••ddr.sufl occur.
If unuabl.Mld,...... occur Mtd tit. /unkfl .,. in tIt.'owtll' h./f. MSR c.nnot ~ fllIt to SIU glHltll'.t6d for boot!ltrllp into
tIt.'tItNf hMf md would h.~ to ~ m.nulll/~ ••t on tit. STU.

PE~IRY
~
-------8eo.. Rev.1

UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

I.Ifl-NUMIP

UllOATI L!YIL

E-l1
PAGE

E.3. 1.8. 1. Partitioned by Storage Halves

CLUSTER 0

. _ - LOWER
SEGMENT

- - - - - UPPER

SEGMENT

SEGMENT

024
Appl.O

Appl.O

--

SEGMENT

8

Appl.1

Appl. 1

!tANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

0-3

10-13

4-7

0-3

30-33
Appt.O

24-27
Appl. 0

14-17
34-37

20-23

10-13
30-33

Appl. 0

Appl. 1

Appl.1

20-23
I~ppl.

0

NOTE'S:

t.

Interi..". b.twHn ugm.nts 0 MId 2 on bit 2 in Appliclltion O.

2.

In,,,,••,,. betwe." bllnlc$ 0 lind t, lind 2 lind 3 on bit 3 in Application O.

3.

Inter/.IIV.

~twHn

ugm.nts 4 lind 8 on bit 2 in Appliclltion 1.

BANK 8
4-7

BANK 7
14-17

24-27

34-37

Appl.1

Appl. 1

8804 AtIv.1

SPERRY UNIVAC 1100/80 Svatema

E-12

4x4 Capability Processor and Storage Programmer Reference

~

I'AGI

E.3.1.8.2. Partitioned Across Storage Halves

CLUSTER 0
-

LOWER
SEGMENT

- - - - - UPPER

SEGMENT

SEGMENT

02..
Appl.O

Appl. 1

Appl.1

--

SEGMENT

e
Appl.O

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 8

BANK 7

0-7
20-27

10-17

10-17
30-37

0-7
20-27

10-17

30-37

0-7
20-27

30-37

0-7
20-27

30-37

AppL 0

Appl.O

Appl.1

AJ)p1. 1

Appl.1

Appl.1

Appl.O

Appl.O

NOTES:
I.

Inr"'.lVe btltwHlf /Un•• 0 .nd 1, MId 8 .nd 7 on bit 3 in Appliution O.

10-17

I

880-4 Rev.1

SPER,RY UNIVAC 1100/80 Systems

Uf'-lltUMla
_ _ _ _ _~

E-13

Capability Processor and Storage Programmer Reference

,AGI

E.3.1.9. Eight Segments/Eight Banks

CLUSTER 0
. - LOWER
SEGMENT

CLUSTER 1

- - - UPPER

SEGMENT

SEOMENT

024

--

SEGMENT

LOWER

-

SEGMENT

SEGMENT

BANK 1

BANK 2

BANK 3

0-3
20-23

10-13
30-33

4-7

14-17
34-37

24-27

SEGMENT

--

SEGMENT

357

8

ISANK 0

UPPER

BAi~K

4

0-3
20-23

BANK 5

BANK 8

BANK 7

10-13

4-7
24-27

14-17
34-37

30-33

NOn~:

2.

Interieetle between banks 0 and 1, 2 and 3, 4 and 5, and 6 and 7 on bit 3.

3.

Sanks 0, " 2, and 3 must be of Mlua' size and banb 4, 5, 8, and 7 must be of Mlua' size", unuuble addresses occur.
If unU$8bl., .ddr. . . . occur and the Nnks MW in the lower h.,1, MSR t;6nnot be Ht to SIU gene,.ttld for boo,."..p into
the 10WfH' h." and would h..,e to be manuelly HI on the STU.

8804 Rev.1

SPeRRY UNIVAC 1100/80 SyRem8

UP-M . . .

4x4 Capability Processor and Storage Programmer Reference

E-14
ItAGI

The following configuration is an eight segment/eight bank configuration partitioned by cluster
ac:ross MSU storage halves.

CLUSTER 0
-

LOWER
SEGMENT

CLUSTER 1

-- -

SEGMENT

UPPER
SEGMENT

024
Appl. 0

App'. 0

Appl. 0

--

SEGMENT

- - LOWER
SEGMENT

8
App'. 0

- - - - - UPPER

SEGMENT

SEGMENT

--

SEGMENT

357
App'.1

Appl. 1

Appl. 1

Appl. 1

BANK 1

BANK 2

BANK 3

BANK 4

BANK !5

BANK 6

BANK 7

0-3
. 10-13

0-3
10-13

10-13

0-3
10-13

Appl.1

4-7
14-17
Appl.1

0-3

AppL 0

4-7
14-17
Appl. 0

Appl.O

Appl.1

4-7
14-17
Appl. 0

4-7
14-17
Appl.1

BANK 0

NOTES:

~_~.~~~.1

1_'_00_1_8_0_S_~__._m_I______~______________________~__________~_E_-_'_5______

1____
__U_N_'_VA_C__
__ S_PE_R_RY.
4x4 Capability

__

Processor and Storage Programmer Reference

UIlDATlI.EVIL

IIAG!

E.3.2. Address Interleaving in Segment/Bank Storage Configurations
E.3.2.1. Four Segments/Four Banks

CLUSTER 0
- - LOWIER

-- ---

UPPER - -

[SEG~eNT SeG~ENT SeG~eNT SeG~ENT

BANK 1

BANK 2

BANK 3

4-7
14-17

0-3
10-13

4-7
14-17

NOTES:

1.

1"r.rltHI"" b.,twHn ugmllnts 0 and 2. and 4 and 6 on bit 2.

2.

Sank!l 0 and 1 mu!lt bll of IIqua' size and bank. 2 and 3 mu!lt ". of 6qua' !liz" or unuublll addr(!JSH!I occur. If th"y
are not equlJ'l in !lizll IJnd IJt'II In th" IOWII,. hIJ11, MSR cIJnnot IH Ht to SIU gllnllntlld fOf boDtstmp into th" lower half
IJnd WDuld h6tl1l to be mIJnually !lilt on thll STU.

8804 Rev.1

SPERRY UNIVAC 1100/80 Svateml

4x4 Capability Processor and St!lrage Programmer Reference

Ufl-NUMIIJt

E.3.2.2. Oegraded Mode - Failed Segment

CLUSTER 0
-

LOWER
SEGMENT

o

- - - - - UPPER

SEGMENT
2
FAILED
FFLINE

BANK 0

BANK 1

0-7
20-27

10-17
30-37

SEGMENT

--

SEGMENT

8

BANK 2

BANK 3

0-3
10-13
20-23

4-7
14-17
24-27

30-33

34-37

NOTES:
1.

InterlellVe betwHII _gmenr. 4 end 8 on bit 2.

2.

Interl.elltl ".tween benk. 0 end 1 on bit 3.

E-18
UPDATI LIYEL

!tAG!

I

8604 Rev. 1

SPERRY UNIVAC 1100/80 Systems

UP-MI~ 4x4 Capability Processor and Storage Programmer Reference

E.3.2;3. Degraded Mode - Failed Bank

CLUSTER 0

UPPER

- - - LOWER
SEGMENT

0

BANte: 0
ALL.
LOWER
ODREsse

SEGMENT

2

OFFLINE

BANK 1
FAILED
OFFLINE

SEGMENT

SEGMENT

4

6

BANK 2
0-3
10-13
20-23
30-33.

BANK 3
4-7
14-17
24-27
34-37

NOTES:

2.

--

Unu;s6bltl lIddrtlSH6 do not occur.

I

E-17
'AGE

8eo4 Rev.1

SPERRY UNIVAC 1100/80 System,

UNtUMi.

4x4 Capability Processor and Storage Programmer Reference

UIIOA'TI LIVB.

E-18
PAGE

E.4. Segment/Cabinet Storage Configurations
The following examples illustrate some of· the possible segment/cabinet storage configurations.
These configurations are not, in any way, being recommended over other usable configurations. They
are configurations that could be used in a situation where a configuration is needed for partitioned
operation or for degraded-mode operation. The data in this section provides a better understanding
of system storage configuration.

E.4.1. One-Segment Configurations
E.4. 1'. 1. One Segment/One Bank

CLUSTER 0
- - LOWER
SEGMENI

0'

BANK 0

NOTES:

1..

No in""••" •..

2.

UnuNbi. Mldt'HN. do not occur.

8104 Rtw.1

SPERRY UNIVAC 1100/80 Systems

UNIUMaIR

4x4 Capability Processor and Storage I;'rogrammer Reference

I

E-19
'AGI

E.4.1.2. One SegmentiTwo Banks

CLUSTER 0
- - LOWER
SEGMENT

o

BANK 0

BANK 1

NOTES:
1.

Intllrl...,. b.twHII !J6nlcs 0 md , on bit 3.

2.

Th. b.nlcs "'ust b. ~u.1 in size or unusable "dd,.e..e .• occur. If they are not _qual in size and are in the lower half,
MSR cannot be $lit to SIU gen.ated for boot$tt'Bp into the lowe,. half and would havtl to be ",anually set on the STU.

~20

SPERRY UNIVAC 1100/80 SysterM

I 'AGE

4x4 Capability Processor and Storage Programmer Reference

E.4.2. Two-Segment Configurations
E.4.2.1. Two-SegmentslTwo Banks - Basic

CLUSTER 0

-

LOWER
SEGMENT

o

BANK 0

SEGMENT
2

BANK 2

NOTES:
1.

IntMle..,. betw.." ugments 0 6nd 2 on bit 2.

2.

The IMnk. must 1M «Iu.' in sa. 0' unuM"'• •dd,.".... occur. If they .,.. not «Iu61 in
end .,. in til. low./' h611,
MSR c.nnot be .et to SIU gene'6r.d for boo,."..p into the 10WtI' helf .nd would hl.,e to be m6nuelly .et on til, STU.

3.

LON of 6 .egment re.ults in bringing down the 6pplit:ltion.
s.gment.

4.

.iz.

The .pplic.tion m.." be rebooted with the ""'Iining

Loa of b."k rwults in bringing dawn the 6pplicltion 6nd loa of thll b.nk:t s.gtrHlnt
with the "","-ning lMnk end ugment.

Th. spplic.tion mly btl rtlbootH

8804 Rev.l

SPERRY UNIVAC 1100/80 Syateml

Ufl-HUMHJt

4x4 Capability Processor and Storage IProgrammer Reference

I

E-21
..AGE

E.4.2.2. Two Segments!Two Banks - Alternclte

CLUSTER 0
- - LOWER

I

ISEG~ENT

BANK 0

- - - - - UPPER
SEGMENT

4

BANK 4

NOTES:

3.

Lo•• of a H{JMtMt iN b."k in a half which conta,"'. th. r.sid""t EXEC brings thll appliution down. "thll rll.id"nt EXEC
;. rHtrictN to onll half of sttH'6gll, rtlmoval of a HIIm"nt iN blllflc in th" om.r half do". not ntICllUitat" 8 rebDDt, but
a failurll in thi. om., half will protMbly "un • rtIbDlrJt.

8e04 Rev.1

SPERRY UNIVAC 1100/80 Systems
4x4 Capability ~rocessor and

Storage Programmer Reference

' •...:-22

E.4.2.3. Two Segments/Three S"anks - Basic

CLUSTER 0
-

LOWER

SEGMENT

o

BANK 0

SEGMENT
2

BANK 1

BANK 2

NOTES:

3.

·4.

17M two INInn conn.ct«J to the a",. $#gm."t mu" btl «Iu.' in size .nd the b.nk conntlCttld to the oth., s-r/ment
mllft hwe • lize «Iu.' to the ttJtIII of m. oth", two bMQ 01' unuable M/tIrH$. . occur. If unuUbie .ddre••". occur
Mfd the bMIc• • ,.. in the low", h.lf, MSR c.nnot be . t to SIU gen",.ttld for boomnp into the lower h.1f .nd would
hw. to btl m.nu.11y ..t on the STU.
L~

of • MfII"Mt /WUIr. in bringing down

thfI

.pplic.tion. The .pplic.tion m.y btl reboottld with the r"",.ining

.."",."t

6.

LDa of • /Mnlc raul,. in bringing down the .pplic."On. If the banlc i. the only one connected to • segment, m"
~pllutJon m~ be tWbootMJ wfth the oth", .egment .nd i,./Mnlc.. If the tMnlc "'./1 one of two conntICted to • ugmtllJt,
the .ppllution m.y be rwbooMd with both ugmen,. MId the r.",.ining two b.nlc..

..........

8eo4 "".1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor anc;j Storage Programmer Reference

E-23
"AGE

E.4.2.4. Two SegmentslThree Banks - Alternate

CLUSTER 0
- - - - - UPPER
SEGMENT
4

BANK 4

BlANK 1

NOTES;~

2.

3.

Llnus.bltl add,..u.. do not occur for ontl b.nk in a h.,l.
J~OI' two btlnl~s

.I"" in
,~t

in a htllf, tnil junks mullt IHI tlqu.' in sizlI or unus.bltl add,.,,"tI. occur. If thllY a,.. not "utll in size and
MSR c.nnot btlHt to SIIJ I/tlntlrstlld for /xx1t$tT.p into thelowtl' half and would h.llil ttl btl manually

thilltltJ~'" h.,f,

on thtl STU.

4.

Loa 0/ ....,mfHIt or bank in a haN which cont.ins thil rHidfHIt EXEC brln,gs tntl .ppllc.tion down. If mil r.sidtlnt EXEC
i.. I'Htrlt:t«I to on. half 01 $'tOragtl, ,.",01161 01 a HgmfHlt Of' btlnk in m. othtH hllli dOtls not n«lI#it6ttl a rMJoot, but
4' filii... in til;. othtll' "." will proIMbIy QUa a rtlboot.

I.

1'1 a IMnk Itnt i. th. only on. conntICttld to 6 ugmfHIt,

m. application may b. rMx»tlld with m. oth., stlgmfHIt and

i,. bank.. /'I th. bMlk W . . ontl Qf two conntlCt«i tQ a .lI(JmfHI" m. appliC6tion may b. ,..bootlld with both stlgmtlfl"
4",d

mtl ,..",tI,,,ing two b""ks.

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

Uf'.NUMIIII

4x4 Capability Processor and Storage Programmer Reference

E-24
UPDATI LIYIL

'AGI

EA.2.S. Two Segments/Four Banks - Basic

CLUSTER 0
- - LOWER
SEGMENT

SEGMENT

o

2

BANK 0

BANK 1

BANK 2

BANK 3

NOTES:

2.

Int,",.I1". b.tM(".n blink. 0 lind f, lind 2 lind 3 an bit 3.

3.

All blinks must "- tKlUM in !Iiu 01' unUNbl. Mid,...... tJt:CUr. If unuubltl .ddfft6H occur .nd thtl blinks .,.. in the
ItJWIIt' hilI!, MSR c.nnQt ~ Nt to SIU g.".,..te for boat6tTllp into the lower hillf lind WtJuld h..,tI to "- mllnulllly ••t
on the STU.

4"

Loa tR II ugmMlt ,...u". in bringing down the IIppliudon. Th. IIppliution

m~

b. rebooted with the r",,"ining

.."",.,,1.

$.,

Loa af II blink r..ul,. in bringing down the lIpp1iclltion. Th. IIppl/utian m." ~ rtIbooted with the
"",,"ining thrH blink. (UII E. 4.2.3. Not. 3) or with MO ugm.",. IItId two blinks

twO ugm.",. lind

8804J~ev.,

_____
UNdUMBER

SPERRY UNIVAC 1100180 System,

4x4 Capability Processor and Storage Programmer Reference

E-2S

_ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _~~~~~
\WOATI LIYIL _ _L_~
"AGI _ _ _ ______

E.4.2.EL Two Segments/Four Banks - Alternate

CLUSTER 0
- - - - - UPPER
SEGMENT
4

BANK 0

BANK 4

BANK 1

BANK !5

NOTES:

t, and

5 on bit 3~

t.

Ill''''''••''. "-twHn b.nlcs 0 and

2.

S"mlc. 0 and 1 must be of fHlual size and banlcs 4 and 5 must be of fHlual siz. or unuubl. addresses occur. If they
a4'. not fHluS' in size and are in the lowIN hslf, MSR csnntJt be set ttJ SIU g~erated lor bootstrap inttJ the lower hlllf
ajIJd would
to b. fNnu.lly set on the STU.

4 and

hI"'.

3.

L,Ct. of a segment tJr b.nlc in s half which cont.ins the resid~t EXEC brings the application down. /I the resident EXEC
i,: reMrict«i to one hlllf of Stof'Q•• remo..," tJf augment 01' b.nk in th. om.,. h.1f do.s not ntICeaitat. a rMJoot. but
a f.ilur. in thi. tJth.,. half will prob6blJl CIJII$• • rMJoot.

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

UfIIOATi LIVIL

E-26
PAGE

E.4.3. Three-Segment Configurations
E.4.3.1. Three SegmentslThree Banks

CLUSTER 0
- - LOWER
SEGMENT

o

-

SEGMENT
2

BANK 0

- - UPPER
SEGMENT
4

BANK 2

BANK 4

N'OTES:

1..

In"""", IHItwHnHgments 0 .nd 2 on bit 2.

3.

FOI' two.unlt. in e he/f. the b6nb mU6t be «Iuel in liZ. 01' unu.ebl••ddr. . . . occur. If they ere not «Iue' in size .nd
.re in the lower hMf, MSR cennot be set to SIU 11",.,..t«i for boo,."..p into th.low.,. helf end would helle to be menu./ly

Ht on the STU.
4.

Loa of. Hflment DI' b.nlt in • h.1f which conr.in. the ,..sid."t EXEC bring6 the epplic.tion down. "th. rHident EXEC

i. f'Ntrlcted to on. he" of stor.g•• '.",0,,(1/ of. segm."t or benlt in the oth.,. h.1f doe. not nee."it.te e reboot. but
• '.'ure in this oth", h.1I will prob8bly c.uu e reboot
6.

The ."",ic.tion mey be rebooted with the r.",eining Hgm.",.. /I e two Hgment h." w•• downed dyn.mice/ly, it mey
". ,.."t.,-.d into the epplicet;on with the on. ,.",eining segment

~_~.1

U_N_I_V_A_C_'_'_00_1_8_0_S_~__~_m_.______~__~__________________~~~~~__~~e-_2_7______

1_·___
S_PE_R_RY.
__
4x4 Capability

E.4.3.2.

Thre~~

Processor and Storage Programmer Reference

UfIOATI\.IVIt.

,.AGE

Segments/Four Banks

CLUSTER 0
- - LOWER

[

-

- - UPPER

SEG~ENT SEG~ENT SEG~ENT

B,ANK 0

BANK 2

BANK 4

BANK 5

NOTE~~

3.

Sanle!l 0 and 2 mU$t b. of «/wl !liz. and banle!l " and 5 mu.t b. of lHIual !liztl 0' unuubltl IIddrtl!l!ltl!l occur. If thtl'l
.,.. not «/utll in siz• •nd .r. in til. low., htllf, MSR cannot btl !ltlt to SIU g"".,.lIttld 10' boOt8t'IIP into thtl lowe, hll/f
."d WtJUld hav. to btl mllnually !I.t on tlltl STU.

III.

Ftx two btI/rJle!l in HCh htl/f, loa of. bllnle in tI h.1f which cont6in!l til.
EXEC bring!l thtl .ppllctltion down. If
til. ,Hid.", EXEC I!I fHtrit:tH to on. hillf of !ItOf'tIgtl, 'tlmQlltll of. btlnlc in tlltl om.,. h.1f dOH not ntICtlaittlttl • ,eboot
but tI ,.;JUl. In til;'
Mil will pI'tJInbIy CtlUH tI rtIboot.

,Hid"",

om.,

6.

If til. btlnle 1000t w•• til. only one conntlCttld to tI !ltlflmtlllr, tlltl tlpp/lt:6tion mtIY b. 'tlboottld with thtl 'tlfnllining .tlgment
I»nle In mtlt htl" lind thtI untlHtlCttld htllf. If til. btlnlc 10« Wtl. on. of two conntICttld to (I !ltIgIfI""t the application
mtIY btl tWboottld wffh til. ,..",tlining thfH btlnu MKI thf'H !ltlgm""rs

(Inti

8804 R.".1

SPERRY UNIVAC 1100/80 System.

~

4x4 Capability Processor and Storage Programmer Reference

...

E-28
UfllDATlLIYIL

!'AGE

E.4.3.3. Three Segments/Five Banks

CLUSTER 0
- - LOWER
SEGMENT

- - - - - UPPER

SEGMENT

SEGMENT

024

BANKO

BANK 1

BANK 2

BANK 3

BANK 4

NOTES:

""twe"" banks 0 and 1, and 2 .nd 3 on bit 3.

2.

Intllrlllatlll

3.

Unu.abl• •dd,.".... do not occur for on. bank in a hilif.

4!.

For four bank. in ahlllf, ." bllnkllmust bll tJqual in siz. or unuNbl. sddrtl.... occur. If unuNblll.dd,.".... occu, .nd
th. bank• • ,." in thll low.,. half, MSR CIInnot /HI .lIt to SIU g"".,."ttld for bootstrap into thll 10MIfIf' half and would hlltlll
to b. mllnulllly Nt on th. STU.

5.

Loa of a ugmfHtt or blink in a hilif which contains th. tWid.nt EXEC brin(/$ th••ppl/ution down. If th. , ••idllnt EXEC
ill ,ntricttHi to on. hilif of nofWgfI. remottM of • Mgm.nt Of blink in th. oth.,. half dolls not ntIClluitatll • 1WHH1t. but
II failurll in this oth., hilif will probably CIIUIUI • r«Joot.

8.

Thll IIPpl/r:"ation may b. rtlboot«J with th. r.",aining MgmfHtts. If II two tUlf/mllnt hilif wa. downtHi dynamicII/1y. it mllY
btl rHfltflr«i into th. IIppiiClltion with th. on. rllmllining IUlgmtlfft.

;r.

If the blink lo.t Willi thll only on. In th. hlllf, thll appl/Clltion may'" IWbootlHl with th. om., hilI/. If th. blink wa. Dnll
of fOUl' in • half, thll IIPpl/ution may /HI r.bootlHl with th. unaHect«J half .nd tlith., th. ,.",aining th,.. banks and
two Hgmtlfl" in th••H«:ttld half
E.4.2.3, Nor. 3} Of' two banks IItfd two stlf/mfHt,. in th••HtICltHi half.

'flIH

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

UMlUMlm

4x4 Capability Processor and Storage Programmer Reference

I ~29
PAGE

E.4.3.4. Three Segments/Six Banks

CLUSTER 0
- - LOW1:R

- - - - - UPPER

~EG~ENT SEG~ENT SEG~ENT

B.A.NK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

NOTES:
1.

''''''''tlWtl betw.." s'f1ments 0 and 2 on bit 2.

2.

Imerltlatle ttetween banks 0 and " 2 lind 3, and 4 and 5 on bit 3.

3.

B'anks 0, 1, :1 and 3 must be of "qual siz. and Nnk. 4 and 5 mu.t btl of "qual size or unu.abl. addr."e. occur. If
unuuble addre"•• occur and the banks artl in th. low., half, MSR clInnot b. Stlt to SIU gtlntlrat«l for bootstrllp into
t1'l. low.,. hl/f lind would hatl. to b. manually Ht onth. STU.

4.

Lou of a segmfHIt 01' tunic in a half which contains th. rHidtllJt EXEC bring. th. IIpplication down. If th. , ••id.nt EXEC
iA' rHtrict«i to on. half of stor.g•• ,.motllll of a .-gmtllJt or blink in th. oth.,. half do•• not n.ctlUitat. II 'tlboot. but
II' failure in this oth., half will prolJMJJly c. . a ,.boot.

5.

'71. lippI/clition may b. ,eboottld with th. ,.maining ugments.

If II two s.gm.nt hllif wa. down«l dyn.miclllly, it mlly

t .. ,.."t(Jf(J(f into th. appliClltion with th. on. ,..",aining ugmMlt.
6.

'if th. blnk lost WIIS ontl of two in II hall, th. application may btl reboot«l with th. oth.,. half and th. remaining blink
lind .'f1m.nt in the afftlcttKI half. If th. /Mnk w... on. of four in II half. til. application may b. r.boottKI with th. other
",.,f and tlith.,. two Ngmtlnts and thrH bank. in til. affflCt«/ half (... E. 4.2.3, Note 3) or two S'f1mtllJl$ and two banks.

............

8104 Rev.1

SPERRY UNIVAC 1100/80 SY1IteIM

4x4 Capability Processor and Storage Programmer Reference

E-30
UItOATi LIVIL

'AGI

E.4.3.4.1. Partitioned by SIU halves

CLUSTER 0
-

UPPER

LOWER
SEGMENT

SEGMENT

SEGMENT

02.
Appl.O

BANK 0
Appt. 0

Appl.O

BANK 1
~pl.O

Appl. 1

BANK 2
Appl.O

BANK 3
Appt. 0

BANK 4
Appt. 1

BANK 5
Appl.1

!..fOTES:

<4'.

In Appliution 0. Iou of a Hgm."t ,...ul,. in bringing down the application. ,.". appliution may be
tWnaining Hgmtlflt.

~r.

In Appllution 0, loa of. IHInk in a half which t:Dntllin. the retJidM' EXEC bring. the application down. If the resident
EXEC 1.1'Htrir:t«J to one half of ftOnge. ,..",o"al of a bank In ",. odt.,. half do.. not n.cHSitate a ,..btJot but a failu"
in m;. om.,. hall will pt'Obably QUM a r~oot .",. appliCltlon may be ,eboo_ with two $-rJm.",. and the rtHrt,;ning
tit,.. bank..

I'.
,7.

reboot~

with the

In Appliutlon 1. loa of a Hgmtlfl' 'Hults in loa of the application. No reboot option..
In AppllCltion t. I".. of a IMnlt
,.",aining banlt.

/'HUn. in bringing down

the application. T?te application may be rtIboor.d with the

~.,

S~

1___S_P£
__R_R_Y_U_N_'V_A_C_1_1_00
__/8_0_____m_I____________________________

4x4 Capability Processor and Storage Programmer Reference

~__________~__E_-_3_1_____
UIIOATI LEVB.

flAG!

E.4.3.4.2. Partitioned Across SIU Halves

CLUSTeR 0
- - LOW1:R

- - - - - UPPER

rsEG~ENT SEG~ENT SEG~ENT

L

AppL 0

Appl. 1

Appl. 0

BA,NK 0

BANK 1

BANK 2

BANK 3

Ac:tpl.O

Appl. 0

Appl.1

Appl.1

BANK 4
Appl.O

BANK 5
Appl. 0

NOTES:
1.

1",,,,fI••..,. b.twHlf ~nks 0 and " and 1# and 5 on bit 3 in Application O.

2.

I",t""e• .,e b"tween banks 2 and 3 on bit 3 in Application 1.

3.

I" Application 0, loa of II stlgmtmt or bank In a half which contllins the ,esident EXEC brings the application down.
IIr the fftid.nt EXEC i. r••trictfld to one half of .torllge. r"",o.,al of a segment or blink in the othe, half doe. not
mJt:"";Ute

4.

4' ,..boo1. but a f.i/ure in thi. om", half will prob.bly c.uu a ,.boo1.

I" AppIlulion 0, the .ppllution mil., be l'tlbootfld with the ugment in the oth.,. hllif. For lou of a ~nk, the appllcation
nrey I» rtJboDtfld with two 6tlgfntlntJI and the rem.ining thr. benks

••

I" ApplIcMiD'It t, loa of a HflmMtt ruuIf6 in loa of the .ppliutitltt. No rtIboot options.

8.

11'1

AppliutiDn " loa of a ~nlc fHUir. In bringing down the IIppliulion.

n""lIinlng b4,nlt.

The application mil., b. rtlboottHJ with the

880.. Rev.1

SPERRY UNIVAC 1100/80 Syatema

4x4 Capability Processor and Storage Programmer Reference

IJII-HUMIIIII

E-32
UPOATI LIYIL

'AGE

E.4.4. Four-Segment Configurations
E.4.4.1. Four Segments/Two Banks - Dual Cluster

CLUSTER 0
-

CLUSTER 1

LOWER

- - LOWER

SEGMENT

SEGMENT

o

2

BANK 0

SEGMENT

SEGMENT

3

BANK 2

2.

The bMllts must btl «Iulll in size or unuuble .dd,..... «CUI'. If they sre not «Iusl in siz. snd s'" in the 10WtH hs/f,
MSR CMfnot be set to SIU 9en.,.st«l fOl' boo~p into the 10wtH' hs" .nd would hs.", to 1M msnuslly ut on the STU.

3.

Loa of s stlf1mfltrt 'Hults in bringing down the sppllc.tion. The applicstion m~ btllWHJotlld in s $ingle clust.,. with
the two ugmtllfts fOl' the c/ullt.,-, protlidlld th., this cluster h.. ." IOU. If it isnlboattHJ in this msnn.,-, ." bMJb ,em';n
..,s/lsbl. f",. UH but procH6ing powtll' i. 1....,,1Id.
The .pplic.tion msy S/SD b. reboot«l •• dusl clustlH' with on. segment in e.ch clu6tel'. ." it is ,.bootlld in this mllnn.,-,
b."lt. connecttHJ to the two ugmen,. """t1tIIKi .'" not ..,.ilsble

4..

Loa of • b.nlt brings the .ppliC6tion down.
segments.

fOl' IIH.

Th. spplicstion msy be ,.bootlld with the ,.",sining bsnlt 6nd its two

860~Rev.'

~M

----

SPeRRY UNIVAC 1100/80 Systems

E-33

4x4 Capability Processor and Storage Programmer Reference
..AGE
---------------------------------------------------------~----------~----------......

The following is an example of a partitioned configuration.

CLUSTER 1

CLUSTER 0
- - LOWER

- - LOWI:R

rSEG~ENT SEG~ENT

L

Appl. 0

SEGMENT

1

3
Appl. 1

OFFLINE

OFFUNE

BANK 2

Appl. 1

NOTES:'

2.

SEGMENT

Llnuubl. IIddrllu•• do not occur.

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

E-34
UfIOATi LIYII.

'AGE

E.4.4.2. Four SegmentslThree Banks - Dual Cluster

CLUSTER 0

CLUSTER 1
- - LOWER

- - LOWER
SEGMENT

SEGMENT

o

2

BANK 0

BANK 1

SEGMENT

SEGMENT

3

BANK 2

NOTES:

2.

3.

/nttHIHtltl tt.twHfl bllnlts 0 lind 1 on bit 3.
Thll two blln*- connectMJ to

mil umll NgmfllJt mint btl «lUll' in ';ZII lind thll blink conn.cttld to

th. oth., slIgmllnt

muM hWII • $U" «lUll' to th" tot.' of thtI otft.,. two blinks 01' unuub'" .ddr,,"n occur. If unuHbl1l addr,,"". occur
lind th" btlnks II,. in th. low.,. hlllf, MSR cllnnot b. Slit to SIU glln",lIttld lor boot6tTllP into thll low", hll/f and would
h..,. to btl mllnu.'Iy Nt on
II.

m. STU.

Loa 01 II .-gm""t 'Hu1't8 in bringing down thll lippi/Clition. Thll IIPpliclltion mil" bll ,"boottld in • sing/II clusttN with
",. two Hf11"M" fIN th" clustM", pt'OtfidIHi milt thi. dumr hn ." IOU. If It Is flIboDtMJ in this mllnntH', 811 blinks ,,,,,"in
wllil.bl. fIN UH but pt'Ot:tIUing pow.r is ,...."tId.
Thll liPpi/ClItion mq lliso btl ,..bootH .. dUIII t:/U$ttIr with on" NgmfllJt in flllCh c/usttH: If it is r.bootMJ in this mllnnllr,
/JMk. t:DfIntlCttld to

6.

m" two stl(Jm""" tWmtItItId .,.. not """il,,blll lor UN.

Loa of II b."k brinf/$ thll lippi/Clition down. If th" b""k wn th. only on" conn«tMJ to two Hgm"",., thll s".tllm /TIlly
btl ,.boottld with thll """"ining two btlnn lind thtlir two sll9m",,'" If thll blink
on. of two conntlCt..-i to two
.tlgllltIIJtS th"
mq btl r"minMJ with thll om.r bllnlts 101'
,"boot (Notll thllt lor 10•• of 1 of 4 ""nits, Notll
3 /n E. 11.2.3 mIIY IIPP/Y.,

Ng""""

m"

w".

PERflY

--------~
8804 Rev.1

UNIVAC 1100/80 System.

E-35
PAGE

4x4 Capability Processor and Storage Programmer Reference

UP-NUMIM

E.4.4.3. Four Segments/Four Banks

CLUSTER 0
- - LOWER

-- -

UPPER

BANK 2

BANK 4

BANK 6

NOTES':

2.

j~"'ks 0 and 2 must b" of equal siz" and 4 and 6 must b" of "qual size or unusable addr"S$". occur. If thtly ar" not
4Jqual in size and an in the lower half, MSR cannot be .et to SIU gtme,attld for bootstrap into the lower half and would
I',,,,,e to be manually $lit on the STU.

3.

j~OU of a H;gtrI"nt or bank in a half which contsins

4.

The spplia"ion m"y be f'tIboDNd with the r.",.ining u(JmtHfts. If. two $tI(Jm.nt hsll wa. downtlld dynamically, it may
,tHI r..",.,.d into th. appllt:6tion with tIN one ,..",";nin(J ~t.

the r,,';dtMt EXEC bring. th" application down. If thll f'II.id"nt EXEC
l. ,.,,6tri~t«i to ontl half of sto,..g., r.mDflsl of a segmtlnt or bank in the om", half dOli. not n.ctl..it.ttl a ,."boot. but
.1 ,,,ilu,.,, in thi" Om., h,,1f will probsbly CHH a rtlboot

8804 Rw.l

SPERRY UNIVAC 1100/80 Systems

4x4 Capabifity ProCessor and Storage Programmer Reference

UNIUMIIR

E-38
UPDATE LIVIL

I'AGI

E.4.4.4. Four Segments/Four Banks - Dual Cluster

CLUSTER 0

CLUSTER 1
LOWER

- - LOWER
SEGMENT

o

BANK 0

SEGMENT
2

BANK 1

SEGMENT

SEGMENT

3

BANK 2

BANK 3

NOTES:

3.,

All benks must ~ tJqUM in siD or unuuble .dd,...... oet:ur. If unu..bl••ddr..... occur .nd the b6nIc:J .,.. in the
lower h61f. MSR t:6nnot be set to SIU gen.r6ttld IOf' btJomr6p into the lowtN' h61f .nd would h6ve to b. m6nu61/y ••t
on the STU.

4.

Loa of • Hgm""t ,nul,. in bringing down the .pplit:6tion. The .pplit:6tion m6Y ~ ,eboot.d in

6 singl. cluster with
th. two ugm.n,. 1M rh. clus,.,., provid«l th.t thl" clu6tllf h.s MlIOU. If it is r.tHJDt«l in this mMrn.r, 611 b.nb '''''6in
I", UN but proCllaing potWf is l.u.n.

..,.iI""e

Th. 6pplit:6tion m.y .1." ~ r.tJoot«l.s du.' clu.,.,. with on. $lI(1ment in uch clu6ttH'. If It is fWbtx1ttId in this m.nn.r,
b""ks conntlCtrld to th. two Hgm",," '"",ovtld .r. not ..,.il.bl. lor us..

5.

two ugmlHla. th. ~r.m mey
rllbtJotfld with th. """.ining two b.nlcs .nd th';r two segments. If the b.nlc w•• one of two conn6Ct«i to two
ugmlMft£ m. ugfNn,. mey ~ fWuin«l with th. other IMnlcs /()I' th. ,.boot (Nor. th.t lor loa of 1 01 4 b.nlc.. Nor.
3 in £4.2.3 mq 6I)p/y.)

Loa 01. b.nlt brings th. 6pp/ic.tion down. If th. b.nk we. the only one conn6Ct«l to
~

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

The following

i~5

an example of a configuration partitioned by cluster.

CLUSTER 1

CLUSTER 0
LOWER

- - LOWER

[

SEG~ENT SEG~ENT
Appl. 0

E-37
,AGE

SEGMENT
1
OFFLINE

OFFLINE

"ANK 1
Appl. 0

BANK 2
Appl. 1

SEGMENT
3
Appl. 1

BANK 3
Appl. ':

NOTES!:

4.

l.ou of a b••nk ,nul,. in bringing down the ."pliclltlon. The application mll'l be reboottKi with the ,.",aining blink.

880~

Rev.1

SPERRY UNIVAC 1100/80 Systeml

E-38

4x4 Capability Processor and Storage Programmer Reference

~

UI'OATI LIVIL

fIIAGI

E.4.4.S. Four Segments/Six Banks

CLUSTER 0
LOWER
SEGMENT

- - - - - UPPER

SEGMENT

SEGMENT

024

BANK 0

BANK 1

BANK 2

--

SEGMENT

8

BANK 3

BANK 4

BANK 6

NOTES:

3.

Slinks 0, ',2. lind 3 must b. 01 «Iu" siz• •nd b~1cs 4 .nd 8 mun tJ. 01 «Iu.' Sizll

or unus.bl. addrll$Us occur. If

m. bMlks ar. in mil lottI1M' hllH, MSR cllnnot btl s.t to SIU g.".rllttld for bootstrll" into
m. IOWM hMf lind would hllV. to b. mllnulIl/y ut on m. STU.

unuubl. Midr..... «CUI' Mtd

4.

Loa ofll ugmllllt 0' blink in II hllif which cont.ins

m. mid""t EXEC brings m. 1I""liclltion down. If mil ,.s,dllnt EXEC

is ""';ct«l to on. hMf 01 stong•• '''''0,,111 of II ugm."t or blink in th. oth.,. hllil dOllS not ntIClluitll'lI " ,.boor. but
II '.ilu,. in this oth.,. hll'li will proIMbly CMlS. II ftIboot

5.

Th. 1I""liclltion mil., btl r.bootH with th. rllm"ining s~mllnts. If II two ugmlll1t h"lf WIIS downH dynllmiclllly, it mllY
H r.."tlllWd into th.lI"pliution with th. 0". ,.",.ining StlgmMt

6.

/I th. blink 10" wu on. of two in • h./f, th• •",,'iC6tion mllY b. reboottHi with
unllffllctH hllif lind the ''''''"ining
b.nk Mtd its s~m."t in th. ilffKtlld h,,1f.
ank 106t wu on. of four in II hili!,
IIPpliClltion mllY be ,lIbootlld
with thII un"ffllCt«l hllif lind .;dI.,. th,... blinks MId two .."",.",. in
IIfftICtH hllif (s". E. 4.2.3, Notll 3) or two blinks
lind two ugm.",. in
IIff«:ttHi hll/f.

"m.

m.

m.

m.

m.

~~;.~.,

.

__

U_N_~A_C_1_1_00_1_8_0_S_~m_.____~____~'________________~~~~----~~~e--3_9

1_
___S_PE_R_RV
__
4x4 __
Capability

___
Processor
and Storage Programmer Reference

UIIOATI L1VEL

PAGE

______

E.4.4.Si. Four Segments/Eight Banks

CLUSTER 0
LOWE:R

BA,NK 0

- - - - - UPPER

BANK 2

BANK 1

--

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

NOTES:

t.

II'ItMl. ..,. b9twHn

2.

' ' ' ' '.11.,. b••twe.n ban/c$ 0 and " 2 and 3, 4 and 5, and 6 and 7 on bit 3.

.~.nt8

0 and 2. and 4 and 6 on bit 2.

3.

6rank. 0, 1, .7, lind 3 must be of «Iual .ize and bank. 4, $, 6, and 7 mu.t be of flqulIl size or unusable addre••e. occur.
It unuuble 4Idd,..... occur and the bank. are in the 10wtH' half. MSR cannot be .et to SIU gen"rated for bootstrap into
t."e low./' h.rlf and would ha.,e to be manually set on th" STU.

4.

t.oa of a ...1ment or bank in a half which contain. the r_dent EXEC bring. the application down. If the re';dent EXEC
,:, r..tricted to one half of storage, rtlmOtlM of a segment or blink in the other half doe. not necessitate a reboot, but
4' failure In dli. oth., half Wl11 pf'O/Mbly C.UH a reboot.

5.

~""e appliudon m~ btl
~.,.

S.

rebootlld with the ,,,,,,aining .egment& If a two .egment half w.. downed dynamically, it may
r..,.,rer.d into tIN application with the one ,..",aining Hgment.

I~

I".. of " bank, the application may btl ffibooted ..wtlt the oth.,. half and "ith.,. two $tI(/tnents and thl'H bank. in

Ime aff«:t«l ha" (... E.4.2. 3, No,. 3J or two ..""."" and two /»nk..

880 .. Rev.1

SPERRY UNIVAC 1100/80 Syltetnl

U'-*IMIIJII

4x4 Capability Processor and Storage Programmer Reference

.

E-40
UPDATI LIYB.

I'AGI

E.4.S. Six-Segment Configurations
E.4.S.1. Six SegmentslThree Banks - Dual Cluster

CLUSTER 0

CLUSTER 1
UPPER

- - LOWER
SEGMENT

SEGMENT

SEGMENT

- - LOWER
SEGMENT

024

BANK 0

BANK 2

UPPER

SEGMENT

SEGMENT

3

5

BANK 4

NOTES:

1..

'nrerlelltle between Hgments 0 lind 2. and 1 a"d 3 on bit 2.

3~

Slinks 0 lind 2 must be equlIl in size or unuuble Ilddresses occur. If they lI,e not «lUll' in size lind lire in the low.r
hllif. MSR cllnnot be Ht to SIU gen",lIted for btJDtstnIp into the 'Owtit' hlllf lind would hll"e to be mllnu.lly set on the
STU.

41.

Lou of II Illlg",."t ()I' bsnk in II hslf which contll"'s the rnident EXEC brin~ the IIppllClltion down. If the rHident EXEC
i. I'Htricted to one hlllf of 6'tDng.. removIII of II Ngmllflt or blink in the othtH' hllif doe. not nfICH6itlltll II 1WHxJt. but
II flli/uTe in this omtH hslf will probllbly CIlUN • reboot.

~r.

The IIppliClltiDn mllY be rebooted in II flingle clu.•t.,. with the thrH ugment1l lor thll cluntN, proflid«i thllt this clulttH
h.. lin IOU. If it is rebooted in this mllnntlf'. II" blinks remllin 1I"lIilllbie for u.. but procasing pow", is ,...."tHi. 11Ie
spplicstion mllY lllso bll rebootlld
dUM cluswr with two S#lgments in ellt:h cluster. If it is rebooted in this msnn.,.,

II.

blinks connt/lC1fHl to the two segment1l ,..",ovtICf lire not 1I"lIl'lllbis for uu.

86~OR.Y"

IJI'.MIMIER

SPeRRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

E-41
UP'DATlLIYU

"AGI

--------------------------------~----------------------~----------~----------

E.4.S.1.1. Partitioned by Cluster and SIU Halves

CLUSTER 1

CLUSTER 0
- - LOWER

[

- - - - - UPPER

'SEG~ENT SEG~ENT SEG~ENT
Appl: 0

Appl. 0

;:===...;;.LO.;;.W.;...;,.;;:E;.;.R__==-_--,..-:..-===.-.;:U;.;..;PPER
SEGMENT
OFFLINE

OFFUNE

BANK 2
Appl. 0

SEGMENT

SEGMENT

3

5

OFFLINE

Appl. 1

BANK 4
Appl.1

NOTES:'
1.

'''tsr's.vs b4,twHn MlgmMt6 0 and 2 on bit 2 in Application O.

2.

Alo

3.

interl.8v,~

in Application 1.

It, AppliuticJ'n 0, lou of a s~m."t rIJ6ults in bringing down the application. Ths application may blJ rebootH with the

",m.ining slJflment.
4.

/,., Application 0, lou of II blink results in bringing down thlJ application and 106$ of ths bank's ugment ThIJ appliclltion
m.y btt r.bc'DtH with ths ,.",.ining b.nk .nd segment

6.

Llnu..bI• •dd,...... do not OC:CUl' in Appllt:6tion 1.

.........

a804 ReY.1

SPEARY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

E.4.S.1.2. Partitioned by Cluster Across SIU Halves

CLUSTER 1

CLUSTER 0
-

LOWER

- - - - - UPPER

SEGMENT

SEGMENT

o

2

Appl.O

OFFUNE

-

LOWER
SEGMENT
1
OFFUNE

SEGMENT
4
Appl.O

BANK 0

BANK 2

B,o.NK 4

Appl. 0

Appl. 1

Appl. 0

- - - - - UPPER

SEGMENT
3
Appl. 1

SEGMENT
5
OFFLINE

NOTES:

2.

Unuubl. IIddrHM16 do not occur in BithlH IIPpliclltion.

_1.

Loa of II ugm.t 01' blink in App/lclltion 0 in II h.,f which contllin. til. r ••,'d.nt EXEC bnng. til. IIppliclltion down.
If til. TtI.d.t EXEC i. r • .mctlld to. on. hllif of $tDf'6gtl. """0'*'111 of II ••gmtHJt or blink in til. otll.r hllif dOB. not
nt#CllNitllt. II 1'tIboo'L but II 'llilur. in
oth.r hllif w"" probllbly CIIU• • II rtlboot

til,.

.,.

FtN loa of II HgmtIM. til• ."pllution mllY btl ,.bootlld with til. MJgmtlnt in til. othtlr hllif in Appliclltion O.

6.

For loa of II blink.
0.

~.

Loa of II ugmtIM (N blink in AppliClltion 1 r••ulr. in lou of th. IIppliution. No r.bt:Jot options.

m. IIppHution m.., btl rtlbootlld with til. blink lind .lIfII'HHIt in til. unllffet:ttld hlllf in AppliC6tion

I

SPERFrf UNIVAC 1100/80 Syttema

~Capability Processor and Storage Programmer Reference

UfIOATI LEVEL

E.4.S.1.3. Partitioned Within Cluster and SIU Halves

CLUSTER 0
- - LOWER
SEG:ENT
[

Appl. 0

CLUSTER 1

;:===__

LO_W~E.;..;.R_==-:...,..~-::==....;;U;.;...;PPER

- - - - - UPPER

SEG~ENT SEG~ENT
Appl. 0

SEGMENT

Appl. 1

B,ANK 0

BANK 2

AIPPI.O

Appl.O

Appl. 0

SEGMENT

SEGMENT

3

5

Appl.O

Appt. 1

BANK 4
Appl. 1

NOTE~t·

t.

In''''"", tlfltwHn flllgm"",. 0 .nd 2• • nd t .nd 3 on bit 2 in Applia.tion O.

2.

No intflrl••

3.

In Application O. the bMlks must In «/u.1 in siz. or unuubl••ddr....s OCCUI'. If they Ill'll nor equill in size lind lire
in the/owego half. MSR cannot b. s.t to SIU gMerattld for boot8tnp into the lower hMf lind would halle to b. manually

IY. in Application

1.

/HI' on the ,STU.
4.

Loa of • s-r/m.", or bank rHU/tlI in bringing down Application O.

6.

ApplIcation 0 may be f'fIbotJtN in a single c/uMtJI' with the' two MI(1IfJMr. " " the clun.r, fNOtIidtld that thl. clwtM' hn
." IOU. If it i. reboDtlld in this tnMIntw, MI blinks r.",ain WllliMJle fIN ,.. but prot:e.ing PDW.tII' is l..-ntld. The
application may alMJ be reIJootlld a. dUM clwrtH with one Sll{/mMt in HCh clU6tel'. lilt is rMJlJIJttId in this m.nntll',
bMtu ctNI".,;rtld to the two HgmtllllS r~ .,. not /IIIaHabie
u...

'Of'

~'dd,.....

t.

7.

Unuuble

8.

In Applit:tJc", t, loa of /I segment IN bMllt fUlJIts In bringing down the application. The application may b" reboottld
in a llingle cluster with the on. tWmaining s,.gm""" ",."v;dlld th.t th;s clusr.r has In IOU.

do not Ot:CUI' in Application

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

~MIIR

E.4.S.2. Six Segments/Four Banks - Dual Cluster

CLUSTeR 1

CLUSTeR 0

-

LOWER
SEGMENT

- - - UPPER

SEGMENT

SEGMENT

SEGMENT

024

BANK 0

-BANK 2

UPPER

- - LOWER

BANK 4

SEGMENT

SEGMENT

3

5

BANK 5

NOTES:

1.

ImMl...,. /HItwHn segments 0 .rnd 2. .rnd 1 .rnd 3 on bit 2.

2.

IntMl• .rve b.twHn b.rnb·4 .rnd 5 on bit 3.

3.

S.rnk. 0 .rnd 2 must btl of tlqUM .a. MId b.rnk6 4 .rnd 5 mu6t /HI of tlqu.rl siztI or unuubltl Mid,....". occur. If th"y
.rr. not tlqUM in .atl .rnd .r,.. in thtl low", h.rlf. MSR unnot /HI $lit to SIU g.".,..tlld for btJtJt6tnp into th. lowtlt' h.rlf
.rnd would h...,. to /HI m.rnu.rlly ••t on th. STU.

4..

L.t:ta of.r Hgm"", tH' b."k in .r h.r/f which conuins th. tWid"", EXEC brings th• .rppliution down. If th" "';d"nt EXEC

i. r..mcttHJ to on" hMf of stor.rgtl, removM of.r Hgment or /HInk in the om", h.rlf don not n.clltl6lt.,. .r rtlbDot. but

.r f.rilure in this othtN h.rlf will pt'f)/Mbly CMJH .r t'IIboot.
5:

The .rpplic.rtltJn mlly/HI ,..bootlJd in II singl. CIU6"" with the thfH H(Jmllftts for the clu6tlH', providlld thllt thi. clu6t1H
hll• .rn IOU. If it i6 fIIbotJ~ in this mllnn." MI bMr/a """.rin 1tI,,;llIbIe for u.. but PfOCH.;ng ptIWIIf' i. 1• ..."tId. Thtl
.rppllc.rtltJn mlly M60 I» ftIIJootlld •• dUIII dust", with two • ."m.nts in HCh c/U6t1lT. II it i6 ,..btJtJtlld in thi. m.nn""
bIIn/a connected to the two H(Jments removlld .,.. not .rvllil.bl. for UA.

tlt

If rhII bMlk 1M' W.. 'htl only ontl connllCtlld to two Mgments, thtl .rppliution mllY b. f'IIbotJtIId with mil rllm.rining th,..
blink• .rnd four Hgm"nts. If thll bMtk Wll6 one of two connllCtlld to • .-gm""t. thll .rppliution m.y/HI rebtJtJtIId with
the remllining th,.. b.rnks .nd MI six H(Jmllnts.

~~?~~.1
_

1_1_00_1_8_0_S_~

SP_e_R_R,_Y_U_N_'
V_A_C
__ Processor
___
m_.____________________________
4x4 Capability
and
Storage Programmer Reference

~

1_ _ _ _

~__________~~_E_~__5______
UPDAn LIY8.

'AGE

The following is an example of a configuration partitioned by cluster.

CLUSTeR 0
- - LOWIER

[

CLUSTeR 1

- - - - - UPPER

'$EG~ENT SEG~ENT SEG~ENT
App'. 0

B~,NK

Appl. 0

Appl. 0

- - LOWER

- - - - - UPPER

SEGMENT SEGMENT SEGMENT
135
OFFLINE
OFFLINE
Appl. 1

0

BANK 2

BANK 4

BANK 5

At:»pl.O

Appl.O

Appf. 0

Appl.1

NOTES.~

4.

i~oa

of a 6t1gm."t at' Innle in a half which contain. tit. t'.lIid.nt EXEC bnngs tit. application down. If tit. r".id.nt EXEC

i. ,..8trlctlld to an. half of ""'8(1•• remoffM of a .egm.nt 01' /)MIle in the om.t' half do•• nat nee.aitat. a ,.boat but
4' failut'. in thl. am.,. half will prt1bab/~ caUH a reboat

5.

I=ot'loa of ••egment. applic.tlon 0",., btll'tIbDottld with the """';ning .."",.",.. If a two .."",."t " . " w.. dawn.d
.1ynamlcally. it ma~ b. ,.HtltfHfH/ into ",. appJic.tiDII with the one ,..",.;n;ng ugm."t Far lou of aNnie, the appliutian
tna~ btl rebCHlttld wl'm th. remalmng two bank. and their Ml(Jm.",..

8804 ""'.1

I

SPERRY UNIVAC 1100/80 S'f8'C8rM

E-48
PAGE

4x4 Capability' Processor and Storage Programmer Reference

~

E.4.S.3. Six Segments/Five Banks - Dual Cluster

CLUSTER 0

CLUSTER 1

,_
._
-_
LO
....W..,...E_R_==_-_------U_.PPER
SEGMENT

SEGMENT

SEGMENT

SEGMENT

024

BANKO

BANK 1

BANK 2

UPPER

- - LOWER

BANK 3

SEGMENT

SEGMENT

3

5

BANK 4

NOTES:

.u. ",

4'.

Sank. O. to 2• ."d 3 mwt b. of «IUM
unUMbl. Mldr..... occur. If unuNbi. «Jd,...... occur and th. bank•
.,.. in th.,oww hall, MSR c.nnot H Ht to StU g.".,..t«1 for booutrap into th.,ow," hall and would hw. to b. manually
HI on th. STU.

I.

Loa of a HfII"."t", blnk in • h." whit:h cont"" th. rftid.", EXEC brin~ th. applludon down. If th. fNid.nr EXEC
i. ~ct«I to on. hMf of .ror.g•• r.",tW6I of a HgI1HInt tN I»nk in th. othw' hMf tIM. not n«:H$it.,. a "'boot. but
a ;lIiIur. in thi. om.r half will pt'Ob.6b/t/ CWH a rWJoot.

~,.

.,.". appliunon mq ". ",boot«J in a 6ingJ. clU6t", with th. thrH ugmllll" I", th. clu.,.,., providH that thi. clU$t.r
h.. ." IOU. If it i. IWbDDtlHl in thi. mann." all banD ,..",ain ."ailabl. for uu but proc••61ng pow., ,. ' ....ntld. Th.
appliution mq alMJ ". rwboot«1 a. dUM c/,.,.,. wffh two Hgm.",. in .ach clu.,.,.. If it i. r.tJoottHJ in this mann.,.,
b."k. conn«:t«J to th. two Hgmtm" ,.",Ott«/ a", not nailabl. fIN u...

7.

/I th. IMnk IDIII w.. th. only on. in lb. h6/l, lb••pplic«ion may'" r.boDt«J wr'th th. unaH«:t«J half. If th. IMnk wa.

on. DI four in a hMf, lb. appliution may'" rMNJDt«l with lb. unaH.ct«l half and "ith", lb. ,.",.ining thf'H bank.
and four HgmM" in th. aff.ct«l half (IN £.4.2.3. Not. 3} or two bank• •nd four ugm.nt.. in th. affllCt«J half.

8804 Rev.1

SPERFIY UNIVAC 1100/80 Systems

Uf'o.NUMIIIIt

4x4 Capability Processor and Storage Programmer Reference

E-47
PAGE

E.4.S.3.1. Partitioned by Cluster

CLUSTER 1

CLUSTER 0
- - LOWER

[

;:===__

- - - - - UPPER

LO;.W.;..;,.;;E_R_==-_---.--:.::==....;:U;.;...;PPER

SEG~eNT SEG~ENT SEG~ENT
Appl. 0

Appl. 0

SEGMENT

Appi. 0

Appl.1

ElANK 1

BANK 2

BANK 3

Appt. 1

Appl.O

AppL 1

SEGMENT

SEGMENT

3

5

Appl. 1

OFFLINE

BANK 4
Appl.O

NOTES.:

"',twHn

t.

Imtll'lHWI

3.

/,,, AppliC6tiCJn 0, loa of • Mlgm."t Of' btlnk in a htlll which conta,n. the ,.~dtmt EXEC bring. the application down.
If the ,.,;,J"nt EXEC i. ,..rrlcted tD one htllf af .torage, rtlmotlal of a .egment or bank in the other half dOH not

Mlgment6 0 MId 2 on bit 2 in Applicnion O.

".eaittlle a rtlboot, but a failure in th,.. odt.,. hall will probably C6use a ,..boot.
4.

the applluJ'ion may btll'tlbootMJ with the """tlining Hgments. If a twO Hgm.", hall Wtl. downMJ dyntlrn;C6l1y, it mtly
r..",IIfWi into the applit:6tion with the one "",,(lining ugrn."t.

~)(I

6.

Jln AppllcMic"lt I, .lou of a NflmlHlt rnull8 in lou of the app/ic:stion. The applit:6tion may be ,.booted with the ,emaining
~JtIf1trNttt.

1.

J~oaof a btlfllc ,.1JU118 in

bringing down the tlpplication tlnd lou of the bsnk's HgmlHlr. The tlpplictltion may be reboot«l

t'Wlth the ,.,,"';ning bMlk tlnd Hgm"'r.

SS04 Rev.1

SPERRY UNIVAC 11oo/S0 Syete,.,.

4x4 Capability Processor and Storage Programmer Reference

~

E.4.5.3.2. Partitioned by

C~uster

SEGMENT

CLUSTER 1
,_
. ._
- . ; ; LO;; .W.; .;,; ;E,;.;,R__
- _ _-:.-:.::=--U..;",;PPER

- - - - - UPPER

SEGMENT

SEGMENT

SEGMENT
1
OFfliNE

024
Appl. 0

BANK 0
~pt.O

Appt. 0

BANK 1
Appl. 0

'AGI

by SIU Halves

CLUSTER 0
- - LOWER

E-4S
U.-oATI LIYIL

OFFUNE

BANK 2
Appl. 0

BANK 3
~pl.O

SEGMENT
3
OFFUNE

SEGMENT
5
Appl. 1

BANK 4
Appl.1

NOTES:

2.

3.

InttJrl••.,. o.twHn b.nk. 0 MId 1• • nd 2 lind 3 on bit 3 in Applit:6tion O.
LD66 of • NgmtHIt f'Hu'" in bringing down Appl/clltion O.

Th. lippI/ClItion mil,! bIJ r.bootlJd with th. """.ining

Ml(JtJttHlt&

m.

"

LD66 of II /Mnk /WUItt in bringing dDwn
IIppliution. Th••ppI/Clltion mil,! b. ",boottld with th. two ugmlJl1" lind
,.",#lining th,... b."k. (NIl £'''.2.3, No,. 3) Of' with two NgmtHlts lind two bMQ.

5:

No intlJrl• ..,. in Appllution 1. UnuabIIJ Mid,...... do not oct:U1'.

6.

Loa of II

MgmIJl1' 0'

blink in Appliution 1 1WIJIt:t in loa of th. IIppllClltion. No rtIboot option&

SPERRY UNIVAC 1100/80 Systems

E-49

4x4 Capability Processor and Storage Programmer Reference

JlAGE

E.4.S.:3.3. Partitioned by Cluster Across SIU Halves

CLUSTER 0
- - LOWIER

-

CLUSTER 1
- - LOWER

- - UPPER

C)EG~ENT SEG~ENT SEG~ENT

[

Appl. 0

B~~NK

0

A,)pl.O

OFFLINE

BlANK 1
Appl. 0

SEGMENT
1
OFFLINE

Appl. 0

BANK 2
Appl. 1

BANK 3
Appl. 1

SEGMENT
3
Appl. 1

UPPER
SEGMENT
5·
OFFLINE

BANK 4
Appl. 0

NOTES;'

3.

In Applic6tir..n O. loa of a stI(Jmsnt or bsnk in s hslf which contsin~ ths ,."-dsnt EXEC brings ms aplicstion down. If
tft. ,.sid."t EXEC is ,s.trictN to ons half of sto,ags. femoval of a ssgmsnt or blink in ths oms' hslf dOH not nscsssitate
" ,..boot. but II failure in this other hslf will probably csu•• a ,eboot

6.

I,' th. bllnlt Irost i. ms only on. connsctN to II Hgmtlflt. ms appHution mst' bs ,.boot. with m. om", stlgmtlflt and
it. 1NInIts. II' ms bsnk ws. ""s of two connt/ICtMJ to s ssgm."t. ms sppliution mst' btl ,sbootsd with both HgmtH1t$
.,nd ms rsmsining two blinks. .

8.

l'nttlrl...,. bHWHn bsnks 2 snd 3 on bit 3 in Applicstion 1.

7.

I'.DIU of II Hgm."r in Applicstion 1 fnul,. in loa of ms spplic6tion. No rsboot option..

8.

4'.Da of s IMnk in App/i'ut;on 1 ,nulf$ in loa of ms sppliution. Th. sppllutlon mst' btl rebootMJ with th. f.msining
j""/t.

8804 Rev.1
UP-NUMIIII

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmar Reference

E-50
UPDAT! LEVEL

PAGE

E.4.S.4. Six Segments/Six Banks - Dual Cluster

CLUSTER 0
-

LOWER
SEGMENT

o

BANK 0

;:===___

L...
O_W....E....R____-_-_-..,.==:_-_U~P-.PER

- - - - - UPPER

SEGMENT
2

BANK 1

SEGMENT

SEGMENT

4

BANK 2

CLUSTER 1

BANK 3

BANK 4

SEGMENT

SEGMENT

3

5

BANK 5

NOTES:

2.

S.nks 0, T. 2. 3 mu6t be of tlqu.lsize 6nd b.nb 4 .nd 6 must be 01 tlqual $iztl or unUNble .ddre"'$ occur. If unuubltl

.tid,...... occur .nd the banks a", in the lowtlr half. MSR cannot be .et to SIU gentlr.ttld lor bootstrap into thtl lowtlr
half .nd would h..,. to be manually s.t on the STU.

3.

Lou 01. Hgment or b.nk in a h./f which contains the midMft EXEC brings the .pplication down. If th" r"sid"nt EXEC
i. """';cted to one half 01 $tor6g., '''''O~M 01 a .~Mft Dr b.nk in the oth",. half do.s not ntICtluirar• • reboot. but
a Ipur. in this oth",. hM/ will prolMbly uus. a reboot.

4.

Th••ppllcltion ",., be IWbooted in a ';ngl. clustM with the thfH Hgm.nts foI' the clU6tM, provided thllt this clus"".
ha .n IOU. /I it Is IWHJotH in thl. m."nM, .11 banks r.m.in availabl. lor 1J6. but proc.aing pow.,. ;$ 1• ..."lId. The
.pplic.tion m.y MMJ be ,~ttld .. dUM clusttlf' with two ugmMfts in ,,6Ch cJu.ttlf'. If it is rtlboottld in this m.nn.r,
b6nlcs connected to the two Hgm.",. """otltld
not .v.il.bI. lor UMI.

.1'.

5.

1/ the bMlk 1061 Wft on. 01 two in 6 half, the application may btl rtlboottKi with the oth",. half 6nd th. ,,,,,,.ining b."k
and two
In thtI MfB.t:tHh/llf. If the b.nk w•• on. of four in • h.1I, the 6ppllcation m.y btl reboor.d with th.
unaffflCted h.1I and .ith.,. thrH NnU 6nd four _gm."ts in the 6f1t1Cttld h.1f (SH £4.2.3, Noftl 3) or four Hgm.nts
and two b.nlc..

Hgm"'''

1.~__SP_E_R_~._~_U_N_I_V_A_C_1_1_00

~~_.1

_

.m__.______~______________________~__________~__.E_-_6_1______

__
/8_0__S_v.d
__
4x4 Capability Processor
and Storage, Programmer Reference

UflDATI LIVEL

flAGE

The following is an example of a configuration partitioned by cluster.

CLUSTER 0
- - LOWI:R

CLUSTER 1

- - - - - UPPER

- - LOWER

fseG~eNT SEG~ENT SEG~ENT

L

"",pI. 0

SA,HK 0

AlltP': 0

Appl. 0

SEGMENT

Appl.1

Appl. 0

BANK 1
Appl. 1

SANK 2
Appl. 0

SANK 3
Appl.1

BANK 4
Appl. 0

- - - - - UPPER

SEGMENT

SEGMENT

3

5

Appl. 1

Appl. 1

SANK 5
Appt. 1

NOTES:
1.

Ir.ttllrlll""

~twHn

ugmllnt8 0 .nd 2 on bit 2 in Appliclltion O.

2.

ImtlrlHvII

""twe."

s~mlln"

3.

/..CtU of II SllQmllnt 01' b.nk in II h.1f which contll'n. mil rll~dllnt EXEC bn'ngs mil lippI/clition down. If mil rUldent EXEC
i,r l'Htf'icttKJ to on. h.1f of sttH'llgll. I'llmowl of II ugm.,,' 01' bllftk in th. othM hlllf do•• not nllClluitlltll • rllboot. but
• f.i/ufW in this om",. h.1f will pro/Mbly CIlUH II rtlboot

4.

E'lthlll' .pplic.tion
bll ,"boottKI with tlllI r.",.inl'ng H(Jmllnt!l. If. two
mil, I» I'Hlftlll'tId into tlllI IIPplic.tJon with mil on. ,-.mMning M(Jmlll7r.

m."

1 lind 3 on bit 2 in Application 1.

$~mllnt

h.,f WI. downtKJ dynllmiclllly, it

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

U~

E-62

'AG.

UfIOATi LIVIL

E.4.S. Eight-Segment Configurations
E.4.B.1. Eight Segments/Four Banks - Dual Cluster

CLUSTER 1

CLUSTER 0
- - LOWER
SEGMENT

- - - - - UPPER

SEGMENT

SEGMENT

024

BANK 0

--

SEGMENT

- - LOWER
SEGMENT

8

- - - - - UPPER

SEGMENT

SEGMENT

--

SEGMENT

357

BANK 2

BANK 4

BANK

e

NOTES:

•

T.

2.

SMlb 0 6nd 2 mu.t be 01 Mlu61 .a. .nd b."ks 4 .nd 5 mUM I» 01 Mlu.' lize or unuNble .dd,.".... occur. If they
.,.. not MlUM in size .nd IIr. in the IOWM h.,f. MSR C6nnot b. Ht to SIU f/MM.t«i for boot6tr11p into the lower hilif
.nd would h..,. to btl m.nuelly ••t on the STU.

3..

Loa 0111 Hgment 01' blink in II hell which conteins the rHidtlnt EXEC brings thtIllppllution down. If the rnidllnt EXEC
is rHtrit:t«1 to one hell of nong., remo". 01 e HQmMt 01' blink in the oth., hMf dOH not n«:...ite,. e ,..boot. but
II

4~

f.,uIW in this othe, h." will probllbly uuu

II

1Wboot.

The .ppliclltitJn mey be rebootfld in • singl. clufttH' with the four Hgmenr. for the clusttH', provid«i th.t thi. cluntll'
hu .n IOU. "it i. rtlbootMJ in this mMln.,., .11 b6nlcs 'emein .".illlble for UH but proceuing power i. I....n«l.

Th • ."pliution me., ./so be tWIoot«i .s • duM clu.'" with thrH ugment8 in .6ch cluner. If it i. ,..booted in this
menn.,., blink. conn«:t«l to the two Stlf/men,. ,.",Otl'tld .re not ."eil.ble fOl' us..

5.

FOI'lou of. benk, the IIpplic.tion m.., I» f'tIboottHI with the un.ff.a«i h." .nd the r.",~ning blink .nd't8 two ugmen,.
in the .ff«:rtHI h.1/.

I

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

E-53

u......uM~ 4x4 Cal)ability Processor and Storage Programmer Reference

PAGI

E.4.6. 1. 1. Partitioned by Cluster and SIU Halves

CLUSTeR 0

--.-- LOWER

I

SEG:ENT
Ajppl. 0

-- -

CLUSTER 1

UPPER

--

SEG~ENT SEG~ENT SEG~ENT
Appl. 0

OFFUNE

OFFLINE

-

LOWER

SEGMENT
1
OFFUNE

UPPER

--

SEGMENT SEGMENT SEGMENT
357
OFFUNE
Appl. 1
Appt 1

BANK 0

BANK 2

BANK 4

BANK 8

Appl.O

Appl. 0

Appl. 1

Appl.1

NOTES:

3.

Loa of a

4.

LOIN

$~m."t

re.ults in lou of t"- applicltion. The application may be ,."booted with the remlining Hgment.

of a banI', bring6 the appl'ution down. The applt'cltion mlY be rebODttId with the remlining bank and Hgment.

8104 Rev.1

SPiRRY UNIVAC 1100/80 Systeml

E-64
PAGI

4x4 Capability Processor and Storage Programmer Reference

UNiIIUMIIIl

E.4.S.1.2. Partitioned by Cluster Across SIU Halves

CLUSTER 0
-

LOWER
SEGMENT

CLUSTER 1

- - - UPPER

SEGMENT

SEGMENT

024
Appl. 0

BANKO

Appl.O

OFFLINE'

Appl. 0

BANK 2
Appl.1

--

UPPER

- - LOWER

SEGMENT

SEGMENT

8

1

OFFUNE

OFFUNE

BANK 4
Appl.O

SEGMENT

SEGMENT

--

SEGMENT

351
Appl. 1

OFFLINE

Appl. 1

BANK 6
Appl.1

NOTES:

1.

No int"""""

2.

Unuubl. MidI'ft6•• do not occur.

3.

Loa 01. ugmwrt iN IMnIt in • h." which cont.in. the rHidtHIt EXEC bring. the .pp!Ic.tion down. If the re.,dent EXEC
i.,ntrictMJ to one h." of .tonge. removel of e ugmtHIt or benlt'in the tJth.- h61f doe. not nee'-t.te e reboot but
e IMlUIW in mi. other he" will prol»bIy ~u.. 6 rtIboot.

SPERRV UNIVAC 1100/80 Systems

E-65

4x4 Capability Processor and Storage Programmer Reference

PAGE

E.4.6. '1.3. Partitioned Within Cluster by SIU Halves

CLUSTER 1

CLUSTER 0

- - LOWI:R

- - - - - UPPER

--

rqEG~ENT SEG~ENT SEG~ENT SeG~eNT

L

At>I>J.

0

Appt. 0

Appl. 1

Appl. 1

UPPER

- - LOWER
SEGMENT

SEGMENT

SEGMENT

SEGMENT

357
App"O

Appt. 0

Appl.1

BA,NK 0

BANK 2

BANK 4

BANK 6

A~,pl.

Appt. 0

Appt. 1

Appl.1

0

--

Appt. 1

NOTES:
f.

1",ttIrl.w. ""rwHn $tIf1mttn,. 0 and 2. and 1 and 3 on bit 2 in Applic6tion O.

2.

I"t.rl.av. b4ttwe."

3.

L.oa of a s."mttnt 'Hults in bringing down th. application; Th" application may b. rtlboottld in a singl. clusttlr with
two $tIfInHlllts fIN til. clust.,., protlidtld that this clu.,.,. has an IOU. If it is r.boottld in this'mann.,., all banlc6 remain
a~.il.bl" for us. but pl'DCnsing pow., is l...."tId. Th" application may al$D b. r.boottld .s dual clust.r witll on.
s.tgmttnt In ."ch clum" If it is r.bootH in this mann"" banks ConnllCtH to til. two sllgm""ts ,..".,o~tId ar. not .~ailabl"

s~m.n,.

4 and 6. and 5 and 7 on bit 2 in Application 1.

tJ,.

fc" UN.
4.

Loa g/ a IM"k brin~ th. application down. Th. appllution may 1M 1'tIbocIr.d with th. """aining ank and its two
.,~I&

8804 Rev.1

SPERRY UNIVAC 1100/80 Sy8tem8

4x4 Capability Processor and Storage Programmer Reference

lJIl-NUM8IIt

E-56

PAGE

UPDATE LIYIL

E.4.S.1.4. Partitioned Within Cluster Across SlU Halves

CLUSTER 0
-

LOWER
SEGMENT

CLUSTER 1

- - - - - UPPER

SEGMENT

SEGMENT

024
Appl. 0

Appl. 1

BANKO
Appt. 0

Appl.O

BANK 2
Appl.1

--

SEGMENT

LOWER

-

SEGMENT

SEGMENT

SEGMENT

--

SEGMENT

357

6
Appl. 1

UPPER

Appl.O

BANK 4
Appl. 0

Appl. 1

Appl.O

Appl. 1

BANK 6
Appl. 1

NOTES:

2.

Unuubl. sdd,..u.. do not occur.

3.

Lo.. of •••gm.", 0' b.nk in • h.If which cont.in. th. ,..~d."t EXEC bring. th••ppllc.tion down. If th. 'Hid.nt EXEC
i. ,.MrictH to on. h.1f of nang., ,..",ov.' of • Mlgm."t or b.nk in th. oth", hMf do•• not n.CHIIit.t• • reboot. but
• f.ilure in thi. oth", h.If will prob6bly c.uu • reboot

-tI.

Th • •ppliution m.y b. ,.bootH in • Mngl. c/u.ttH with th. two Hgm.nt8 for th. c/u.,." providtld th.t
h•••n IOU. If it i. r.tJoot«J in thi. m.nnM, ." b.nk. r.",.in .v.ilM». for UH but proc.66ing POWIH' i.
• ppliution m~ .,." btl rflboottld •• dUM c/U6ttII' with on. ugmMl, in NCh clwtM. "it i. fWbooltld in
IHHtk. connllCtH to
two Hgm."t8 r.",owd .,.. not w.iI.bI. for UH.

th,. c/u.t",

'.611.,,«1.

th.

Th •

mi. mMtnM,

8804~.
.1

u........,.....

SPERRV' UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

IE-57
UIIOATI L.IVS.

PAGE

------------------------------------------------------~----------~------------

E.4.S. '1.5. Minimal Storage Partitioned Out

CLUSTER 0
- - LaWleR

';EGMo ENT

~

CLUSTER 1

- - - - - UPPER

SEGMENT

SEGMENT

--

SEGMENT

SEGMENT

246
Appt. 0

Appl. 0

Appf. 0

BANK 2
Appl. 0

OFFUNE

UPPER

- - LOWER

Appl.O

--

SEGMENT SEGMENT SEGMENT
357
Appl. 1
Appl.O
Appl.O

BANK 4
Appl.O

BANK 6
Appt.1

NarES;'

1.

Im.rl••". b.,rwe." ugm.nr. 0 and 2. and 1 and 3 on bit 2 In ~ppllcation O.

2.

L.o.. of a ."gment or bank in a half which contains the r ••id.nt EXEC brlng!l the application down. If the r.,ident EXEC
iJr fHtrit:ted to on. half of .torag•• r.mo"tli of a s~m.nt or bank in the other half do•• not neclH!litat. a r.boot, but
., fMlure in ''his oth.,. htllf will probably cau.. a reboot.

3.

Application ,0 ma., be rebooted in a !lingle clust.' with the th,.. segmen,. for the clust.r. pro"ided that this clustllr ha.
4,n IOU. If it l!l ftIbootlld in thi. mann.,., tI/I ban" rem.in a"ailabl. for u.. but proclluing pow.r ,. I.Ullntld. Thll
4,ppllcation mq al$O ". r.booted a. dual clust.,. with two !lll(Jm."r. in .lICh clu.tel'. If it i!l reboor.d in thi. manniif'.
~UIIIQ conmH:ttld to thll two IIIIfImlltr,. ,..",owd a,.. not tI"anabie for ,...

6.

No intBI..... in Appllatlon to

s.

~~oa

of a !I4'f/m."t or bank in Application 1 fHUlts in loa of the application. No ,..boot options.

8804 Rw.1

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

U~

E-58
Ufl'DATU.lVB.

flAGE

E.4.S.2. Eight Segments/Six Banks - Dual Cluster

CLUSTER 0
- - LOWER

CLUSTER 1
LOWER

- - UPPER

SEGMENT

SEGMENT

o

2

BANKO

BANK 1

SEGMENT

SEGMENT

SEGMENT

8

BANK 2

BANK 3

BANK 4

UPPER

SEGMENT SEGMENT SEGMENT
357

BANK

e

NOTES:

.1.

Sank. 0, ',2, and 3 must b. of «Iual size lind /Mnb 4 and 8 mU!lt ~ of tH/ual siztl or unuubl. addr."•• occur. If
unuubltl add,...... occur lind th. /Mnk. II,.. in thtl lowtN' half, MSR Cllnnot btl s.t to SIU g.n.rattld for bootstrll" into
th. lowtlt' half and would hatl. to ~ manually Ht on STU.

'..

I.Da of a ugm."t in a half which contain. th. rHid.", EXEC bn"g. th. application down. If th. rHid."t EXEC is
r"";ctH to on. half of !ltorag.. ,.",otlal of a ugmMlt or bank in th. oth",. half dOH not ntIC.uit.t. a r.boot but a
IMlu,.. in thi. oth., half will probMJ/y C6USB a rtIboot.

5.

Th. ap"liut/on m.., b. reboottJd in a singl. cJwt",. with th. lour stI(Jm.,," for th. clust",., "fOtlidtld that this clu."'"
h_ an IOU. If it i. rebtJDtH in this mann." all b.,.k. """ain atlailabl. for USB but proc.uing pow.r i. 1....nBd. Th •
• ""lit:6tion may .Iso ~ rBbootH a. dual clu/lt",. with six ugm.nts in Hch clu/ltBl'. If it i. rBbootH in thi. mann.,.,
bank. eonntICtH to th. two ssgmMtts removH .,.. not atlai/abla for uu.

8.

LDa of a bank in a half which eom.,,,. tha r.d.", EXEC brinp tha a"pliC6tion down. If tha r.sid.nt EXEC i. r ••met.d
to ona half of $'I",ag., rtHrlOtlai of II bank in tha oth",. half doH not ntIC.Uitat. II r.boot but. failur. in this othtH' half
will probably t:6UH • rBboDt.

1.

If th. /Mnk lost wa on. of two in II hBlf, th••""Iication may ~ fBbootBd with th. untlffsct.d half lind th. ,,,,,"ining
/Mnk lind i,. two ugm.nts in th••fftICtH half. If tM bank WH on. of four in II half, tha 1I""liclltion mllY b. r.boot.d
whit th. unlflKtBd h.1f lind Bith., th. r.maining thr. . blink. lind lou, $Bgm.",. (... E.4.2.3, Not. 3) or two blinks
..nd lou, $tl(Jm.",. in th• .IffllCttld half.

:::~.~_.1

R_R._~_U_N_'V_A_C

1___S_PE
__ Capability
__
1_'OO
__I_8_0_S_yn
__
._m_.
4x4
Processor
and____________________________
Storage Programmer Reference

........

~_______________

E_-_69____

UPOATI L&VB.

"AGE

E.4.S.:t 1. Partitioned by Cluster

CLUSTER 0
- - LOWI:R

-- -

CLUSTER 1
UPPER

--

fsEG~ENT SEG~ENT SEG~ENT SEG~ENT

L

Appl. 0

Appl. 0

AppL 0

Appl.

a

- - LOWER
SEGMENT

UPPER

SEGMENT

SEGMENT

--

SEGMENT

357
Appl. 1

Appl. 1

OFFUNE

SANK 1

BANK 2

BANK 3

BANK 4

BANK 6

Appl. 1

Appl.O

Appl.1

Appl. 0

Appl. 0

OFFLINE

NOTES~'

2.

Lou 01. Hgmtlnt 0' b.nk in a half which cont.inll th. 'tlllid.nr EXEC bn'ngll th" application down. If the rtlsident EXEC

i:, ,tWtrictfld to on. h.1f of IItorage, remo".1 of a stlgm"nr or bank in the othe, half aoell not neeeuit.te a 'eboot. but
" lailu,. in this othtN' half will probably causa a reboot

3.

Application ,0 may btl rtlboottld with thll rwmaim'ng IItlgmtlnts. If. two $lI(Jment h.1f wall aowntKJ ayn.mically, it may

t."
4.

""""~f into the .pplication with the one remaining .tlgment.

J:'" loa 01. bank, the .ppllcltion ",.., be rtlbootlld with the unaHIICttId half and the ,.",';ning bank and Hgment in
Itte a~h.1f.

6.

~~oa

of a MgmtMt rHuM in bringing down the .ppliClltion.

The application may btl I'tIbODttld with thtl remaining

~Jtlgm""t.

7.

~,.... oIa bank reMJ/ts ill

bringing down the applk:ation and lou 01 the bank'. s.gmMlt. The application may btl reboot.a

lwith the fW,.,.mng bank and ugmIMt.

~.

8604 Rev.1

SPERRY UNIVAC 1100/80 Syttems

4x4 Capability Processor and Storage Programmer Reference

Ull-NUMHR

E-60

"AGE

UPOATllE'IB.

E.4.S.2.2. Partitioning One MSU Out

CLUSTER 0
- - LOWER

CLUSTER 1

- - - - - UPPER

--

SEGMENT

SEGMENT

SEGMENT

SEGMENT

o

2

4

6

Appl. 0

Appl. 1

Appl.1

Appl. 1

.

BANK 0
Appl. 0

BANK 1
Appl.O

BANK 2
Appl.1

BANK 3
Appl. 1

-

LOWER
SEGMENT

- - - - - UPPER

SEGMENT

SEGMENT

--

SEGMENT

357
OFFLINE

BANK 4
Appl. 1

Appl. 1

Appl.1

Appf.1

BANK 6
Appf.1

NOTES:

f.

Int.r/••". ~twHn banlc. 0 .nd 1 on bit 3 in Application O.

6.

Int"'"". b.twHn banb 2 and 3 on bit 3 in Application 1.

8.

In Application 1, lou of a .~."t rx /»nk in a half which con,.in. the ,...u:t.nt EXEC brin~ the applit:4tion down.
If the ,.,,"-dent EXEC ,. r ••tn'ct«J to OM half of .ror.ge, '«riOt/III of • 6t1(/1nM1t Dr bank in the oth", half· dOH not
n.c#lUitate a ,eboot, but a failure in mi. oth", half will prowbly caUH • r-"«Jt

7.

Th. appl;cation m.ylM f'tIbootfld in a "-ngl. c!U.tllf with the thfH 6egm.",. frx the clu$f",., pf'DtlidMJ that thi. clu6t",
hu an IOU. If it i. f'tIbootMJ in mi. mann." ,,11 banlc. r.main a"ailabl. for u•• but procH6ing POWtit' i. 1....nfHi. The
application may al$O be rMJootfld .. duM clU$ltIt' with two ugmMts in eM:h clusttll'. /I it i. ,../NHJted in thi. mann.,.,
bllnu connKtIld to the two Hl(/m.",. ,..".,owd ",. not ..,a,1MJ1. for UH.

8.

If the /»nk 1D$f wn the only one connKttlll ttl two H(/ment6, the application may b. rl/lbootMJ with the rtlmaining th,..
bank. and four H(/ments. "the bMtk wa. on. of two connectMJ to a 6egmtmt, the application may be r""ootH with
the '.",aining thr.. IMnlcs and all .uc segm.nts.

I

· S804 Rev.l

U~

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

I

I

UP'OATI LEVEL

E-61

PAGe

---------------------------------.----------------~----------~~-------

E.4.S.:3. Eight Segments/Eight Banks - Dual Cluster

CLUSTER 0
- - LOWI:R

CLUSTER 1

- - - - - UPPER

['1EG~ENT SEG~ENT SEG~ENT

BANK 1

BANK 2

UPPER

- - LOWER

SEG:ENT

SEGMENT

SEGMENT

SEGMENT

SEGMENT

357

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

NOTES:

2.

Ime"ea,," ht;tween banks 0 lind ,1. 2 .nd 3, 4 and 5. lind 6 lind 7 on bit 3.

3.

S.nks O. ',2. and 3 must be of equal sizil .nd banks 4, 5, 6, .nd 7 must be of equal size or unusable IIddreSSlls occur.
It unusable atidrllSUS occur and the banks a,.. in thil 10wII' half, MSR cllnnot bll Stlt to StU gllnerlltlld for bootstrap into
tI'e lowllr h.1f and would hll"" to bll mllnually set on the STU.

4.

L,,," of II
I~t

ullm.", tN blink in II half which contains thll rssidlln, EXEC brings the IIppliclltion down. If the rnidlmt EXEC

ratrict«J .to onll half of ~~, rllm".,al of II slltlm."t or bank in mil om.,. hall dOllS not necllun.tll II reboot but

a failu", in this
5.

8.

om.,. half will probably CIIUH a f'f#boot.

The appliclltion ma" bll rebooted in II ';n9'. clwt/lt' with thll four segmtmts lor the clust.r, pro"ided thllt this clustllr
has an IOU. If it is rtlboot.d in this mllnn." 1111 banlcs remllin a"ailable for uu but procllUing pow.,. is 1• ...,,«1. Th •
• "plicllt;"" may also be r.bootlld u dUIII clustlll" with six stlgmllnts in .ach cluster. If it is reboot«l in this mllnn."
b,.nks connt'Ctild to the two ugm.nts rtHnOVH a", not a"lIilllbl. lor us..

PM loa ola blink, thll IIpplication mllY be rebooted with thll unllffllCttld half lind eith.,. thr.. blln/c6 and foul' Sfl(Jmllnts
£4.2.3. Notll 3) or foul' sttgmlltrts lind two benks in the afflICted half.

~JH

..........

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

E-62
PAGE

4x4 Capability Processor and Storage Programmer Reference

E.4.S.3.1. Partitioned by Cluster Across SIU Halves

CLUSTER 0
-

LOWER
SEGMENT

CLUSTER 1

- - - UPPER

SEGMENT

SEGMENT

024
Appl. 0

BANK 0
Appl. 0

Appl. 0

Appl. 0

BANK 1
Appl. 1

BANK 2
AppL 0

--

SEGMENT

- - LOWER
SEGMENT

UPPER

SEGMENT

BANK 3
Appl. 1

SEGMENT

357

6
Appl. 0

SEGMENT

--

Appl. ,

DANK 4
Appt. 0

Appl. 1.

BANK 5
Appl. 1

Appl. 1

BANK 8
Appl. 0

Appl. 1

BANK 7
Appl. 1

NOTES: •
1.

1m"'""" btl,.",,,.,, ugmtInt8 0 and 2, .nd 4 .nd 6 on bit 2 in Applie4tJon O.

2.

Interle."" NtwllfllJ

3..

LDa of. ugment iN /Mnlt in a half whiclt contain. the ,Hid."t EXEC bn'ngll the application down. If the fHident EXEC
ill ,..mcted to one half of smr.ge,. ,emoval of a Mlf/ment Of banlt in the oth.,. half don not n.ce.t.,. a ,eboot. but
a failure in thill at/J",. ha" will probably c.u.e a reboot

4.

The app/ic4tion may be rebooted with the femaining HgmMl,.. If a two Hgm.m half wa. downtld dynamically, it may
H ",."ttInId into the application with tIN one ,..",aining segmMt

6~

FtN I"". of a /unit. tIM application may btl ,eboottld with the unaffecttld hMf and the remaining banlt and ugmem in
the afftH:t1ld h.1f.

Hgm~"

1 and 3, and 5 and 7 on bit 2 in Application 1.

'04 Rev.1
'-fMIIIIR

I

I

SPER:AY UNIVAC 1100/80 Systems

_~ Capabili1ty Processor and Storage Programmer Reference

E.4.B.3.2.

Partition~d

by Cluster by SIU Halves

CLUSTER 1

CI.USTER 0
-

LOWER
SEGMEfllT

-- -

SEGMEINT

UPPER
SEGMENT

024
Appl. ()

BANK 0
Appf. 0

Appl. 0

BANK 1
Appl. ()

E-63

PAGE

OFFUNE

BANK 2
Appf. 0

-

SEGMENT

- - LOWER
SEGMENT

6

SEGMENT

UPPER
SEGMENT

135
OFFUNE
OFFUNE
Appl. 1

OFFLINE

BANK 3
Appl.O

-- -

B"NK 4
Appl.1

BANK 5
Appt. 1

BANK 8
Appl. 1

--

SEGMENT

1
Appl. 1

BANK 7
Appl.l

NO res:

t.

Int"'I''''. b.tween $lIf1men,. 0 lind 2 on bit 2 in Appliclltion O.

2.

Int."••.,. "etwl!'en bllnk$ 0 lind 1, lind 2 lind 3 on bit 3 in Appliclltion O.

3.

Interlell.,e betwttfln $egmen,. 5 lind 7 on bit 2 in Application T.

4.

Int.,1• ..,. b.rw,Hn banks 4 lind 5. lind 6 and 7 on bit 3 in Application 1.

6.

LO$I.' 01 II

s~",ent

r.sul,. in bringing down the IIppliC6tion.

Th. IIppliclltian mllY b. r.baotN with the femllining

M1gm."t

6.

Lon 01 II blink fHIII,. in bringing down the IIpplication. Th. lippI/clition mllY ". rM300tlld with the two segmen,. lind
ftHItsining
blinks ($/HI £4.2.3. Not. 3) 01' with two s.gm"n,. lind two blink$,

th,..

8804 Rev.1

SPERRY UNIVAC 1100/80 Sv-tema

4x4 Capability Processor and Storage Programmer Reference

UNtUMIIR

E-84
fIIAGI

E.fi. Segment/Bank Storage Configurations
The following examples illustrate some of the possible segment/bank storage configurations which
can be used only in systems involving single clusters. These configurations are different from
segment/cabinet configurations in that they require different printed circuit card placement in the
STU and different cable routing between the SIU and the MSUs. These configurations cannot be
expanded beyond one SIU and two MSUs.

E.S. 1. One Segment/One Bank

CLUSTER 0

- - LOWER
SEGMENT

o

BANK 0

IYOTES:
,.

No inttlrl...,..

3.

Loa of • ugmMlt

01'

"-nit fHUI,. in IDa of th••ppliC6tion. No fMHxJt option..

I

I

8604 Rev.1
I SPERRY UNIVAC 1100/80 Systems
e 65
~~~___4_X_4__C_.a_p__a_b_il_j~__P_r_o_c_e_s_s_o_r_a_n_d__S_t_O_r_a~g_e_P_r_O_g~r_a_m_m
__e_r_R
__
ef_e_r_e_n_c_e____~U~.~
__
An
__~
______~P_AG_i_-_________

E.S.2. Two Segments/Two Banks

CLUSTER 0
- - LOWER

~EG~ENT SEG~ENT

BANK 0

BANK 1

NOTES:

2.

3.

n'e banks must be equal in size or unusable sddr.sses occur. If thllY are not equal in sizlI snd sre in the lowllr half.
M,SR cannot be set to ~/U generatlld for bootstrap into the lower half snd would have to be msnually set on the STU.
L~lu

of s SBflment results in bringing down the application.

segment snd two banks.

The application may be rebooted with the ,ems;ning

8804 Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

Uft-HUMIIII

E:.S.2.1. Degraded Mode - Failed Segment

CLUSTER 0
-

LOWER
SEGMENT

o

SEGMENT

FAILED

2

BANK 0

BANK 1

NOTES:

2.

m.

Thtl bMlt. mun btl tKlu.' in siz. 01' unuubl• •ddrBU.S occur. If th.y .", not equ.' in siztl .nd .rtl in
low", helf.
MSR unnot btl ••t to SIU g.ntlnttld for /Joo,.tnp into th. 10WtIf' he" .nd would helltl to btl menu.",! s.t on thtl STU.

88(~"
Rev.1

SPERRY UNIVAC 1100/80 System.

4x4 Capability Processor and Storage Programmer Reference

Ufl-HUMIP

E-67
PAGE

--------~----------------------------------------------~----------~----------

E.5.2.:2.. Degr;:lded Mode - Failed. Bank

CLUSTER 0
- - LOWER

[

'3EG~ENT

SEGMENT

OFFLINE

2

81~NI(

0

F/"LED

flANK 1

Of:FLINE

NOTES:
1.

/110 intefttN"e.

2.

/'Jnu.sble tf(tdf'(Jue. do not

3.

j~D"

OCCUI'.

of s $egment or bsnlt re.ults in /0" of the spplicstion. No reboot option•.

8eo4 Rev.l

SPERRY 'UNIVAC 1100/80 Syatem8

4x4 Capability Processor and Storage Programmer Reference

UNIUMIIII

UPOATI UYIL .

e-8a
'AU

E.S.3. Three SegmentsIThree Banks

CLUSTER 0
-

LOWER

-

-

UPPER

SEGMENT SEGMENT' SEGMENT
024

BANKO

BANK 2

BANK 1

NOTES:

3.

6,..

S.nks 0 6nd , mu.t b" of ."uM $;a 01' unuNbltl 6dd",.... occur. II mtly .,. not «1u61 in . . • nd
in thtl low.,.
h./f, MSR CMlnot b.
to SIU g.".,..tlHi 10,. boo,.".p into thtl low.,. h.1f 6nd would h6.,. to be m6nu.lly Nt on til"

$_

STU.
·4.

Loa of 6 $.gmtIM 01' b.nk in 6 h.1f whlc/l cont.in. th. rHid.", EXEC brinl16 th. 6pplic.don down. "thtl , • .HJtlnt EXEC
i. fNtrit:t«J to on. h." of $ton~. ,.",twM of 6 MIgm."t 01' benk in th. oth.,. h.1f doH not nM:H6ir.t• .. ,Hoot but
6 IMlul'tl in thi. om.,. htlif will prob.bly CIIUH 6 ffIboot

5.

/I thtl $tlgmtlflt w•• tIHI only on. in th.t htl/f, th. 6pp1lution m.y be rtIboottJd with thtl un6fftICttJd h.1f. If th. ugm.nt
....a on. of two in 6 h./f, thtl $~ mlY ". ,.bootfld with th. untlfftlCttld htllf .nti th. ,.m6ining ugm."t 6nd two

b.nu in thtl ."-crtld h.1f.

8804 Rev.1

SPERRY UNIVAC 1100/80 Systems

U......tUMIE"

4x4 Capability Processor and Storage Programmer Reference

E-69
PAGE

E.S.3.1. Degrc!ded Mode - Failed Lower Segment

CLUSTER 0

- - LOW1:R

- - - - - UPPER

SEGMENT
SEGM ENT

2

SEGMENT

o

FAILED

4

[

BANK 1

BANK 2

NOTES:
,.

Imtlrleavtl be'tween banks 0 and 1 on bit 3.

2.

I)nullllbitl addrenell do not occur for one bank in a half.

3.

the bankll mUllt be equal in size or unullilble IIddrtllllleS occur. If they are not equal in size and are in the lower half,
MSR Cllnno, be ser to SIU gtln.rllttld for bootstrap into the towel' half and would have to be manulIlI." set on the STU.

4,

Lou of II segment or bank in a half which containll the resident EXEC brings the application down. If th. rellidtmt EXEC
i~r rHtricrtld to one half 01 storage, .,emoval of II IItl(Jmtlnt or bank in the other half doell not nec.uitate II r.boot but

.' '"ilure in t,hill other hllll will probllbl." CIIUH a reboot.

6.

'0$'

I" the bank
WN the only one in a hlllf, the appliclltion mar btl reboo't«l Wf'th the unaHtteted half. If the blink Willi
c,ne of two in a half, the appliC6tion ma." be 'tlbootH with the unaHttetH half and the remaining bank and segment

;4" the aHeeted half.

8eo4 Rw.1

SPERRY UNIVAC 1100/80 SyatemS

4x4 Capability Processor and Storage Programmer Refttrence

E.5.3.2. Oegraded Mode - Failed Upper Segment

CLUSTER 0
- - LOWER

- - - - - UPPER
SEGMENT

SEGMENT

SEGMENT

o

..

2

FAILED

BANKO

BANK 1

BANK 2
OFFLINE

...

2.

3.

The b.nks must be tlqu.1 in size or unuubl••dd,...... occur. If the." .r. not tlqu.' in si,e .nd .re in the lower h.lf.
MSR CMtnot b. s.t to SIU g.n.,..,H for boot8tnp into th. low.r h." .nd would h."" to be menu.lI." HI on the STU.

Loa of • ugment ,...ulr. in bringing down th• •pP/iC6tion. The .pplicltion m• ." b. r.boottJd with the rem.ining
MId two b6nks.

U(1mMft

8804 Rev.1

SPERR'I( UNIVAC 1100/80 Svst..".

4x4 Capability Processor and Storage Programmer Reference

IJIl-NUMIIR

I
!

E-71
IIAGE

E.S.3.:I. Degraded Mode - Failed Lower Bank

CLUSTER 0
- - LOWI:R

~EG~ENT

L

SEGMENT

SEGMENT

2

4

OFFLINE

B~\NK

- - - - - UPPER

0

F~"LED

BANK 1

BANK 2

OFFLINE

NOTES;'

t.

No intMl.II"",

2.

Llnuubl. atJ'dr~S$flS do not occur for onll Junk in II h/llf.

3.

/.,0" of /I ugm.nt or b/lnk in /I h/l" which cO"'lIins thll resident EXEC bring. the appliclltion down. "the re$idllnt EXEC
~, ,...tricrlld to one hllll of $torllgll, rllmov61 of. ugmllnt or b.nk in thll other h/llf dOlls not neclluitllte II reboot, but
" f/li/ure in "hi$ omllr h/lll will probllbly CIIU•• II reboot

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Prog.rammer Reference

E-72·
UPOATI LIYIL

'AU

E.S.3.4. Degraded Mode - Failed Upper Bank

CLUSTER 0
LOWER

- - - - - UPPER

SEGMENT

SEGMENT

SEGMENT
4

o

2

OFFUNE

BANK 0

BANK 1

BANK 2

FAILED
OFFUNE

NOTES:

2~

The b.nlcs mus, be eqUIII in size 0' unuuble .ddIWUH occur. If the,! s,.. not squ.1 in size 8nd s,.. in the low.,. h8lf,
MSR csnnot b. s.t to SIU g.".,.tlHi fo, bootsusp into the low.,. hs" snd would hs"e to /HI msnusll'! s.t on the STU.

3.

Lou of • Stlgment ,"ults in bringing down the sppllution.
segment snd two bsnks.

Th. spplicstion mq be ,lIbootlHi with th., """.ining

8e04~fIV.1

U'~UM'ER

SpeRFrf UNIVAC 1100/80 Systems

E-73

4x4 Capability Processor Ctnd Storage Programmer Reference

UPDATE LEVIL

'AGE

------------------------------------~----------------~----------~------------

E.S.4. Four Segments/Four Banks

CLUSTER 0

- - LOWI:R

ISEGM ENT

L,

o

-- -

UPPER

SEGMENT

SEGMENT

SEGMENT

2

4

8

BANK 2

BANK 3

NOTE5~'

1.

lnterllla"e between sflgments 0 lind 2. lind 4 lind 8 on bit 2.

2.

19anks 0 lind 1 must be of IIqulll size and blinks 2 and 3 must be of equal size or unusabl", addreS$e$ occur. If thllY
,If. not lHIu,.' in siz. and ar. in thll lower half, MSR cannot be Slit to SIU generat.d for bootstrap into th. lower half
lind would ha". to be mllnually Slit on the STU.

3.

Lo.. of II segment or blink in II half which contains the resident EXEC brings thll appliclltion down. If the , ••ident EXEC
,. restricttJd to one hllif of storllge, 'IImo".1 of II segment or bank in the other half dOllS not nllee..itat. II reboot, but
., faitul'll in this other half will probsbly cause a reboot.

4.

For 1D$6 of s sBgmsnt, the application mS'lH rtlboot«l with the unaHsctBd half lind the remsining segment and two
bMks in the sHIICtBd hslf.

1804 Rev.1

SPERRY UNIVAC 1100/10 System.

4x4 Capability Processor and Storage Programmer Reference

~

E-74
PAGE

E.S.4.1. Degraded Mode - Failed Segmen.t

CLUSTER 0

- - LOWER
- - - - - UPPER - SEGMENT
SEGMENT
2
SEGMENT SEGMENT
4
8
o
FAILED

BANK 0

BANK 1

BANK 2

BANK 3

NOTES:

.1'.

2.

Th. bank. ",u.t b. tHlual in !liz. or unu.abl••dd,...... occur. If th.y
not equal in Mz. and .,.. in the low.,. h.,f.
MSR cannot b•••t to SIU 9.n",.ted fOf' boo,."..p into the lower half .nd would ha". to b. manually Nt on thll STU.

3.

Lou of II Hgment or bank in a half which contain. the rll.dent EXEC brinrP thll application down. If thll rHident EXEC
,. rBtricted to on. half of .toIWg•• remo".1 of. Hgment 01' bank in the oth.,. h.1f do•• not neell.tat. a reboot. but
a failure in this oth., half will {H'OIMbly caUH a tWboot

II.

If the ugment wa. the only on. In th., half. the appl/Clltion may b. rtlbooted with thll unaffeeted hlllf. If tItll .tlgmtll7t
""n on. of two in a half, the ~ may be I'f#IHxJted with the unafftIt::ttHI hlllf and the r.",aining ••gment and two
/»tIk. in the afftH:ted half.

5.

II the bMrk 1tW/ ""a on. of two connflCted to a .(lgment. the application may be rebooted w;m the remaining thrH banks
and .11 th,... Hgments. If the bilnk ""a. the only on. connllcted to a $tlgm.nt. the applic.tion may In rllbaotN with
the "",,"-n;nl/ tit,.. blinks and thei, two s.gmen,.,

I~Capability Processor and Storage Programmer Reference

8804 Rev.l
UNUiIa

SPER"V UNIVA.C 1100/80 Systems

E-75
IIAG!

E.S.4.2. Degraded Mode - Failed Bank

CLUSTER 0
- - LOWER
SEGMO ENT
[

- - - - - UPPER

SEGMENT

SEG~ENT

2

OFFLINE

SEGMENT
8

BANK 2
BlANK 0

BANK 1

FA.ILED
OFFLINE

BANK 3

NO~S:

2.

Unusable addresses do not occur for one bank in a half.

3.

The banks must be «Iual in size or unuubl. addrsue. occur. If they are not squal in size and are in the lowe, half,
MSR cannc7t be set to SIU generatttd for bootstrap into the lowe, half and would ha"e to be manually SlIt on the STU.

4.

Lou of a ugment or bank in a half which contains the 'e$ident EXEC bring6 th. application down. If the 'Hident EXEC
i$ fHtrlcred to one hllif of storage, 'emo"al of B Hgmen, or bank in the other half doe. not nee.aitate a reboot, but
II faIlure in this om., half will probably C6U•• II reboot.

6.

If the ugment w.. the only one in thM half, the a"pliC6tion m.... be IWbootlld with the unaffected half. If the segment
..,a. one of two in a half, the system may be reboot«J with the unafflJCttHi half and th. remaining segment and two

bana in the afftICttHi half.
6.

For lou of a bank, the appliution m.... be reboottHi with the ,,,,,,ain;ng two bank. and their segments.

SPERRY UNIVAC 1 100/80 Svaem.

4x4 Capability Processor and Storage Programmer Reference

E.S.4.3. Partitioned by SIU Halves

CLUSTER 0
-

LOWER
SEGMENT

SEGMENT

UPPER
SEGMENT

024
Appl. 0

BANK 0
Appl. 0

Appl. 0

BANK 1
Appl. 0

Appl. 1

BANK 2
Appl. 1

--

SEGMENT

8
Appl. 1

BANK 3
Appl. 1

;VOTES:

.2.

Int.rl• ...,. btlrwefHI Hgmllnr. " .nd 8 on bit 2 in Applic.tion 1.

3.

Th. bIn". mu.t btl «lull in size IN unuNbl••ddl'..... OCCUT. If th.y .,.. not «Iu.' in .iz••nd
in th" low",. hIli,
MSR Clnnot btl ••t to SIU gen.,..tMl for boot8tnJp into the 10Ml' h.1f .nd would h",," to btl mlnu.'/y . t on the STU.

4.

Loa of • Hgm""t rHu1t8 in bringing down

.1'.

.egm""t .nd two blink..

m. Ipp/iCMion.

Th• •ppllc.tion ml, btl rtlbootMi with thll rtlmllining

~

8604 Rev.1

PERFIY

UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

------

UP-NllJMIIR

i

E-77
PAGE

E.S.4.4. Partitioned Across SIU Halves

·
l

CLUSTER 0

- - LOWER

r

,sEGMO ENT

Appl. 0

- - - - - UPPER

SEGMENT

SEGMENT

--

SEGMENT

246
Appl. 1

Appl. 0

Appl. ,

BANI< 0

BANI< 2

BANK 3

AII:lPI. 0

Appl. 0

Appl. 1

NOTES.~

2.

Unusable lI,fdreue$ do not occur.

3.

L.oss of a s(fI(Jment or bank in a half which contains the rBsidllf7t EXEC brings thtl application down. If thll rtlsidllnt EXEC
;" rllsmcttld to ontl half 01 storagll. rllmoval of a segment Of' bank in the other half dOtls not nllClluitattl a reboot but
~, failuTtI in this omll' half will probably caustl a reboot

4.

jr"htl appliClltion may bll rtllboot«J with thtl unafffICttld half.

8604 Rev. 1

SPERRY UNIVAC 1100/80 Systems

UP-HUM8EA

4x4 C.lpability Processor and Storage Programmer Reference

.

Index-1
UIIOATlI.EVEL

PAGE

Index

Reference.

Term

Page

A

Term

Reference

Page

Add Thirds instruction

5.4.19

5-11

Add to A instruction

5.4:1

5-7

Add to X instruction

5.4.7

5-8

Add Upper instruction

5.4.5

5-8

Addition
double-precision
floating-point
floating-point

4.2.13
4.2.12

4-10
4-10

Abbrevii3tions. definitions.
and symbols

Appendix A

Absolutf~

8.3.3

8-8

AbsolutISt values

4.2.1.3

4-2

Accumulator regasters

3.4.2.30
3.4.2.3

3-21
3-18

Add Hallves instruction

5.4.17

5-10

Address assignments
control register
fixed

3.4.2
3.2.7

3-16
3-4

Add Magnitude to A
instruction

5.4.3

5-7

ADDRESS CHECK signal

3.2.5

3-3

Add Negative Halves
instruction

Address generation

8.3.8

8-10

5.4.18

5-10
E.3

E-2

Address parity checking

3.2.5

3-3

4.3.2.2.2
6.3.1
3.3.6.1
8.3.3

4.,.15
6-5
3-10
8-8

address

. Address interleave
Add Negative Ml:lgnitude to
A instruction
5.4.4

5-7

Add Negative Thirds
instruction

5.4.20

5-11

Add Negative to A
instruction

5.4.2

5-7

Addressing
character
device
modes
theory

Add Negative to X
instrl.llction

5.4.8

5-8

Addressing Exception
interrupt

7.3.1

7-5

Add Ne'gative Upper
instruction

Addressing modes

3.3.6.1

3-10

5.4.6

5-8

8804 Rev. 1

SPERRY UNIVAC 1100/80 Systems

~

4x4 Capability Processor and Storage Programmer Reference

Term

AUow All Interrupts and
Jump instruction
Arithmetic exception
interrupts
Characteristic
Overflow
Characteristic
Underflow
Divide Check

Reference

Page

5.9.3

5-38

7.3.2

7-6

7.3.2
7.3.2

7-6
7-6

Arithmetic instructions
fixed-point
floating-point

5.4
5.5

5-6
5-11

A,rithmetic interrupt

4.2.4.3

4-4

4.2.1.3
4.2.4.2
4.2.1.1

4-2
4-3
4-1

4.2.1.2
4.2.1

4-2
4-1

4.2.2
4.2.4.1

4-2
4-3

Arithmetic section
absolute values
carry
data word
data word
complement
general operation
microprogrammed
control
overflow

Term

Bank descriptor registers
control information
format

Table 0-2

0-4

Automatic recovery

1.2.5

1-9

1.2.8

1-10

"AGE

Reference

Page

8.3.6
8.3.7

8-9
8-9

Bank descriptor selection
instructions
Load Bank and Jump 5.10.1
Load D-8ank Base and
Jump
5.10.3
Load I-Bank Base and
Jump
5.10.2

5-38
5-39
5-39

Base value selection

Figure 8-3

8-12

Binary Double Integer to
Byte Convert instruction

5.14.9

5-65

Binary Single Integer to
Byte Convert instruction

5.14.8

5-64

Block multiplexer channel

6.2.1

6-3

Block transfer

5.3.8

5-6

7.3.3
Figure 7-3

7-8
7-9

Byte Add instruction

5.14.14

5-68

Byte Add Negative
instruction

5.14.15

5-69

Byte Compare instruction

5.14.4

5-58

6.16

6-57

Breakpoint interrupt status

ASCII to Fieldata code
conversion

Auxiliary storage
subsystems

Inde~-2

UI'OA1'E L£YEL

Byte data packing formats

Table 6-14 6-59

4.3.2.3

a-field
A-registers
Executive
user

3.4.2.30
3.4.2.3

4-20
3-21
3-18

B
Back-to-back operation

6.20

6-66

Bank descriptor

8.3.4

8-9

Bank descriptor index
registers

3.4.2.9

3-18

Byte instructions
Binary Double Integer
to Byte Convert
Binary Single Integer
.
to Byte Convert
Byte Add
Byte Add Negative
Byte Compare
Byte Move
Byte Move With
Translate
Byte to Binary Double
Integer Convert
Byte to Binary Single
Integer Convert

5.14.9

5-65

5.14.8
5.14.14
5. 14. 15
5.14.4
5.14.1

5-64
5-68
5-69
5-58
5-54

5.14.2

5-56

5.14.7

5-64

5.14.6

5-64

86()4' Rev. 1

SPERRY UNIVAC 1100/80 Systems

UI4JUMIEIII

4x4 Capability Processor and Storage Programmer Reference

Index-3
UItDATt LEVEL

PAGE

8604 Rev. 1

SPERRY UNIVAC 1100/80 Systems

~M8Eft

4x4 Capability Processor and Storage Programmer Reference

Term

Conditional jump
instructions
Double-Precision
Jump Zero
Halt Jump/Halt Keys
and Jump
Jump Carry
Jump Divide Fault
Jump Floating
Overflow
Jump Floating
Underflow
Jump Greater and
Decrement
Jump Low Bit
Jump Modifier Greater
and Increment
Jump Negative
Jump Negative and
Shift
Jump No Carry
Jump No Divide Fault
Jump No Floating
Overflow
Jump No Floating
Underflow
Jump No Low Bit
Jump No Overflow
Jump Nonzero
Jump Overflow·
Jump Positive
Jump Positive and
Shift
Jump Zero
Jump/Jump Keys
Configuration assignments
Configurations
general
segment/bank
segment/cabinet

Reference

.

Page

Term

Index-4
PAGE

Reference

Page

Control section

4.3

4-11

Control storage

3.4

3-15

5.11.2

5-40

5.11.10
5.11.22
5.11. 17

5-41
5-44
5-43

Data chaining

6.8.1

6-39

5.11.16

5-43

Data chaining precautions

6.16

6-57

5.11.15

5-43

Data transfer

6.7

6-37

5.11. 1
5.11. 12

·5-40
5-42

5.11.13
5.11.8

5-42
5-41

5.11.4
5.11.23
5. 1 1.21

5-40
5-44
5-44

5.1 1.20

5-43

5.1 1.19
5.1'.11
5.11.18
5.11.6
5. 11. 14
5.11. 7

5-43
5-42
5-43
5-41
5-42
5-41

5.11.3
5.11.5
5.11.9

5-40
5-40
5-41

3.3.7

3-15

1.2
E.5
E.4

1-1
E-64
E-18

0

Data transfers from storage Figure 4-1

4-13

Data transfers to storage

Figure 4-2

4-14

Data word formats

Table 6-6

6-30

Dayclock

8.2.2

8-7

Delayed storage check
interrupts

7.3.6.2

7-12

Designator register

8.2.1

8-1

Device addressing

6.3.1

6-5

Device states

6.3.2
Table 6-2

6-6
6-9

Device status

6.15

6-56

Diagnostics instruction

5.15.20

5-76

Divide fault

4.2.10.3

4-9

Divide Fractional instruction 5.4.14

5-10

Divide Integer instruction

5.4.12

5-9

Divide Single Fractional
instruction

5.4.13

5-9

4.2.5
4.2.16

4-4
4-10

Control register address
assignments

3.4.2

3-16

Control register protection

3.4.2.32

3-21

Division
fixed-point
floating-point

Control register selection
designator

3.4.1

3-15

Double Floating to Byte
Convert instruction

5.14.13

5-68

Control registers

3.4

3-15

Double Load A instruction

5.2.9

5-3

I

8604 Rev. 1

up~u~

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

Page

Double Load and Convert
to Flclating instruction

5.5.12

5-17

Double Load and Unpack
Floating instruction

5.5.10

5-16

Double Load Magnitude A
instrLlction

5.2.11

5-4'

Double Load Shift and
Count instruction

5.8.8

5-36

Double Shift Algebraic
instruction

5.8.6

5-35

Double Shift Circular
instruction

5.8.2

Index-5
UPOAT! L&V!L

Term

Reference

Double-Precision Test Equal
5.7.14
instruction

5.8.4

5-35

Double Store A instruction

5.3.7

5-5

Double-Load Negative A
instruction

5.2.10

5-3

Double-Precision
Fixed-Point Add
instruction

5.4.15

5-10

DoublEt-Precision
Fixed-Point Add
Negative instruction

5.4.16

5-10

ECC

3.2

3-1

Edit instruction
function byte
subfunction byte

5.14.5. 1
5.14.5.2

5-59
5-60

EI chaining

6.8.3

6-40

Enable/Disable Dayclock
instruction

5.15.3

5-70

3.2
3.3.1

3-1
3-6

Error detection and
reporting

3.3.5

3-8

Execute instruction

5.13.3

5-47

3.4.2.30
3.4.2.29
3.4.2.27
3.4.2.23
3.4.2.24
3.4.2.25
3.4.2.26
3.4.2.27
3.4.2.28
3.4.2.29

3-21
3-21
3-20
3-20
3-20
3-20
3-20
3-20
3-21
3-21

5.5.3

5-12

Doublf!-Precision Floating
Add NegativI3 instruction

5.5.4

5-13

Executive bank descriptor
table pointer register

3.4.2.5

3-18

Doubll3-Precisi(m Fleating
Divide instruction

5.5.8

5-15

Executive control

Section 8

Executive registers
A-registers
Index registers
J-registers
R-registers

Floating

Doubl'e-Precisic)n Floati ng
Mulltiply instruction
Double-precision
floclting-point
clddition
Oouble-Precision Jump
Zero instruction

5.5.6

4.2.13

5.11.2

5-32

E

Error correction code

Add instruction

Page

5-34

Double Shift Logical
instruction

DoubIE~-Precision

'AGI

5-14

4-10

5-40

X-registers

Executive instructions
Diagnostics
Enable/Disable
Dayclock
Initiate Interprocessor
Interrupt
Initiate Maintenance
Interrupt
Input/Output

5.15.20

5-76

5.15.3

5-70

5.15.19

5-76

5.15.21
5.15.22

5-77
5-77

8604 Rev. 1

SPERRY UNIVAC 1100/80 Systems

UP-NUMIIR

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

..
load Base
load Breakpoint
Register
Load Dayclock
Load Designator
Register
load limits
Load Quantum Timer
Prevent All Interrupts
and Jump
Reset Auto-Recovery
Timer
Select Dayclock
Select Interrupt
Locations
Store Designator
Register
Store Processor 10
Store Quantum Time
Store System Status
Toggle Auto-Recovery
Path
User Return
Executive Request
instruction
Externally specified index
(ESI)

Page

5.15.9

5-74

5.15.6
5.15.2

5-73
5-70

5.15.13
5.15.10
5.15.8

5-75
5-74
5-74

5.15.1

5-69

5.15.16
5.15.4

5-76
5-70

5.15.5

5-70

5.15.14
5.15.7
5.15.12
5.15.18

5-75
5-74
5-75
5-76

5.15.17
5.15.15

5-76
5-75

5.13.4·

·5-47

1.2.3
6.2.1

1-8
6-3

F
Fieldata to ASCII code
conversion
Fixed address assignments

Fixed-point arithmetic
division
multiplication
lFixed-point arithmetic
instructions
Add Halves
Add Magnitude to A
Add Negative Halves
Add Negative
Magnitude to A
Add Negative Thirds

Term
Add Negative to A
Add Negative to X
Add Negative Upper
Add Thirds
Add to A
Add to X
Add Upper
Divide Fractional
Divide Integer
Divide Single
Fractional
Double-Precision
Fixed-Point Add
Double-Precision
Fixed-Point
Add Negative
Multiply Fractional
Multiply Integer
Multiply Single Integer

Index-6
'AGE·

Reference

Page

5.4.2
5.4.8
5.4.6
5.4.19
5.4.1
5.4.7
5.4.5
5.4.14
5.4.12

5-7
5-8
5-8
5-11
5-7
5-8
5-8
5-10
5-9

5.4. 13

5-9

5.4.15

5-10

5.4.16
5.4.11
5.4.9
5.4.10

5-10

5-9
5-8
5-8

Fixed-point division

4.2.5

4-4

Fixed-point multiplication

4.2.6

4-4

Fixed-point to
floating-point conversion 4.2. , 1

4-9

Floating Add instruction

5.5.1

5-11

Floating Add Negative
instruction

5.5.2

5-12

Floating Compress and
Load instruction

5.5.14

5-18

Table 0-1

0-2

Floating Divide instruction

5.5.7

5-15

3.2.7
Table 3-1
Table 3-2

3-4
3-4
3-5

Floating Expand and Load
instruction

5.5.13

5-18

4.2.5
4.2.6

4-4
4-4

5.4.17
5.4.3
5.4.18

5-10
5-7
5-11

5.4.4
5.4.20

5-7
5-11

Floating Multiply instruction 5.5.5

5-13

Floating-point
Addition
Arithmetic instructions
Division
Multiplication

4.2.12
5.5
4.2.16
4.2.15

4-10
5-11
4-10
4-10

Floating-point arithmetic
instructions
Characteristic
Difference to
Upper

5.5.16

5-19

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

Term
D,)uble LOcld and
Convert to Floating
Dc:)uble Load and
Unpack Floating
Dc)ubfe-PrEtcision
Floating Add
D4)uble-Precision
Floating Add
Negative
DfDuble-PrEtcision
Floating Divide
OIDuble-Precision
Floating Multiply
Floating Add
Floating Add Negative
Floating Compress and
Load
Floating Divide
Floating Expand and
Load
Floating Multiply
L()ad and Convert to
Floating
Lc)ad and Unpack
Floating
Magnitude of

Reference

Page

5.5.12

5-17

5.5.10

5-16

5.5.3

5-12

5.5.4

5-13

5.5.8

5-15

5.5.6
5.5.1
5.5.2

5-14
5-11
5-12

5.5.14
5.5.7

5-18
5-15

5.5.13
5.5.5

5-18
5-13

5.5.11

5-17

5.5.9

5-16

Charactc~ri~tic

Difference to
Upper
Floating-point numbers
characteristic
overflow/underflow
divide fault
division
dou ble-prt!cision
double-pmcision
addition
multiplication
negative numbers
normalized
fI!sidue
single-precision
addition
single-precision
subtraction
word formats

5.5.15

5-19

4.2.10
4'.2.10.3
4.2.16
4.2.8.2

4-8
4-9
4-10
4-7

4.2.13
4.2.15
4.2.8.3
4.2.9
4.2.8.4

4-10
4-10
4-7
4-8
4-8

4.2.12
4.2.8.1
4.2.14
4.2.8

4-10
4-7
4-10
4-11

Floating-point ;zero

4.2.17

4-11

Format flags

Table 6-8
6.7.1

6-32
6-37

. UPDATE LEVEL

Index-7
PAGE

Reference

Page

Function byte

5.14.5.1

5-59

Function code
cross-reference

Table C-1

C-1

f-field

4.3.2.1

4-12

General configurations

1.2

1-1

General register stack

3.4

3-15

GAS register assignments

Table 3-6
Table 3-7

3-16
3-17

Guard Mode interrupt

7.3.1
Figure 7-1

7-5
7-7

Guard mode register

3.4.2.11

3-18

Halt Channel instruction

6.4.6

6-21

Halt Device instruction

6.4.5

6-20

Halt Jump/Halt Keys and
Jump instruction

5.11.10

5-41

h-field

4.3.2.6

4-23

Immediate storage check
interrupt registers

3.4.2.6

3-18

Immediate storage check
status register

3.4.2.12

3-19

Increase instructions

5. 13. 14

5-51

Index registers
Executive
user

3.4.2.29
3.4.2.2

3-21
3-17

1.2.5
6.19

1-9
6-66

Term

G

H

Initial load

8604 Rey. 1

SPERRY UNIVAC 1 100/80 Systems

UIl-MUMHft

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

Page

Initiate Interprocessor
Interrupt instruction

5. 15. 19

5-76

Initiate Maintenance
Interrupt instruction

5.15.2 ,

5-77

Input/Output device
addressing

6.3.1

6-5

Input/Output interrupts
Machine Check
Normal
TC!bled

7.4.1
7.4.2
7.4.3

7-19
7-21
7-29

Input/Output system states

6.3.2

6-6

Input/Output unit

1.2.3
Section 6

1-7

Table C-1

C-1

Instruction mnemonic
cross-reference
Instruction repertiore
summary
In:struction repertoire
bank descriptor
selection
instructions
byte instructions
conditional jump
instructions
Executive instructions
fixed-point arithmetic
instructions
floating-point
arithmetic
instructions
load instructions
logical instructions
miscellaneous
instructions
search and
masked-search
instructions
shift instructions
store instructions
test (or skip)
instructions
unconditional jump
instructions

Appendix C

Index-8
UPOATI LEVEl

Term

PAGE

Reference

Page

Instruction ~ord fields
a-field
f-field
h-field
i-field
j-field
u-field
x-field

4.3.2.3
4.3.2.1
4.3.2.6
4.3.2.7
4.3.2.2
4.3.2.8
4.3.2.5

4-20
4-12
4-23
4-23
4-12
4-24
4-22

Instruction word format

4.3.1

4-11

Internal SIU check interrupt 7.3.6.2.1
Internally specified index
(151)

7-13

1.2.3
6.2.1

1-8
6-3

Interprocessor interrupt

7.3.4

7-9

Interrupt address word

6.10

6-45

Interrupt errors

7.5

7-32

Interrupt generation flags

6.9

6-44

Interrupt mask register

6.18

6-64

Interrupt priority

Table 7-1

7-2

Interrupt seQuence

7.2

7-3

7.3.2
7.3.5
7.4 I
7.3.4
7.3.7
7.3.1
7.3.3
7.3.6

7-6
7-10
7-19
7-9
7-17
7-5
7-8
7-10

5.10
5.14

5-38
5-51

5. 11
5.15

5-39
5-69

5.4

5-6

5.5
5.2
5.12

5-11
5-2
5-44

Interrupt types
arithmetic exception
clock
input! output
interprocessor
power check
program exception
program-initiated
storage check

5.13

5-46

Interrupts

Section 7

Invalid function codes

5.16

5-77

5.6
5.8
5.3

5-20
5-32
5-4

Invalid Instruction
interrupt

7.3.1

7-5

5.7

5-28

Invalidate interface

3.3.4

3-8

5.9

5-37

IOU error interrupt register

3.4.2.14

3-19

8804 Rev. 1

I

UP-HUM~

SPERRY UNIVAC 1100/80 Svstems

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

Page

UPDATE L!VEL

Term

Index-9
PAGE

Reference

Page

Jump Negative and Shift
instruction

5.11.4

5-40

IOU functional
characteristics
channels
subchannehs

6.2.1
6.2.2

6-3
6-5

Jump Negative instruction

5.11.8

5-41

i-field

4.3.2.7

4-23

Jump No Carry instruction

5. 11.23

5-44

1/0 instlruction format

6.3.4

6-14

Jump No Divide Fault
instruction

5. 11.2 1

5-44

I/O inst:ruction operation

6.3.5

6-15

I/O instruction status

6.11

6-50

Jump No Floating Overflow
instruction
5.11.20

5-43

6.4.5
6.4.7

6-20
6-22

Jump No Floating
Underflow instruction

5.11. 19

5-43

6.4.8
6.4.1
6.4.4

6-23
6-16
6-19

Jump No Low Bit
instruction

5.11.11

5-42

Jump No Overflow
instruction

5.11.18

5-43

6.4.5.2

6-21
Jump Nonzero instruction

5.11.6

5-41

I/O operations

6.5

6-25
Jump Overflow instruction

5.11.14

5-42

I/O status

6.10
6-45
Table 6-12 6-46

5.11.3

5-40

Jump Positive instruction

5.11.7

5-41

I/O instructions
Halt Device
Lo,ad Channel Register
LOiad Table Control
Words
Start 1/0 Fast Release
Te~st Subchi:Jnnel
Word Channel
Operation

J

Jump Positive and Shift
instruction

-

Jump Carry instruction

5.11.22

5-44

Jump Zero instruqtion

5.11.5

5-40

Jump Divide Fault
instruction

5. 11. 17

5-43

Jump/Jump Keys
instruction

5.11.9

5-41

Jump Floating Overflow
instruction

j-field

4.3.2.2

4-12

5.11.16

5-43
J-register
fields
format

4.3.2.2.2
Table 4-5
Figure 4-3

4-15
4-16
4-16

Jump Floating Und&rflow
instruction

5.11.15

5-43

Jump Greater and
Decrlement im»truction

5.11. 1

5-40

Jump history stack

3.4.2.16

3-19

Left circular shifting

5.8

5-32

Jump L.ow Bit instruction

5.11.12

5-42

Left Double Shift Circular
instruction

5.8.10

5-36

Jump Modifier Greater and
Incre~ment instruction

5. 11. 13

5-42

L

8804 Rev. 1
UP-NUMIIIt

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

Page

Inde)t-10
UI'OATl LML

Term
Load A
Load Magnitude A
Load Negative
Magnitude A
Load R
Load X
Load X Increment
Load X Modifier

PAGE

Reference

Page

5.2.1
5.2.3

5-2
5-2

5.2.4
5.2.5
5.2.7
5.2.8
5.2.6

5-2
5-3
5-3
5-3
5-3

Left Double Shift Logical
instruction

5.S.12

5-37

Left logical shifting

5.S

5-32

Left Single Shift Circular
instruction

5.S.9

5-36

Left Single Shift Logical
iinstruction

5.S.11

5-36

Load I-Bank Base and
Jump instruction

5.10.2

5-39

Limits

8.3.5

8-9

Load Limits instruction

5.15.10

5-74

Load A instruction

5.2.1

5-2

Load Magnitude A
instruction

5.2.3

5-2

Load Modifier and Jump
instruction

5.9.2

5-37

Load Addressing
Environment instruction

5. 15. 11

5-74

Load and Convert to
Floating instruction

5.5.11

5-17

Load Negative A instruction 5.2.2

5-2

Load and Unpack Floating
instruction

5.5.9

5-16

Load Negative Magnitude A
5.2.4
instruction

5-2

Load Bank and Jump
instruction

5.10.1

5-38

Load Quantum Timer
instruction

5.15.8

5-74

Load Base instruction

5.15.9

5-74

Load R instruction

5.2.5

5-3

Load Breakpoint Register
instruction

5.15.6

5-73

Load Register Set
instruction

5. 13. 12

5-49

Load Channel Register
instruction

6.4.7

6-22

Load Shift and Count
instruction

5.8.7

5-35

Load Dayclock instruction

5.15.2

5-70

Load Table Control Words
instruction

6.4.8

6-23

Load X Increment
instruction

5.2.8

5-3

Load X instruction

5.2.7

5-3

Load X Modifier instruction 5.2.6

5-3

Load Designator Register
instruction

5.15.13

5-75

Load DR Designators
instruction

5.13.1

5-46

Load D-Bank Base and
Jump instruction

5.10.3

5-39

Load instructions
Double Load A
Double Load
Magnitude A
Double-Load
Negative A

5.2.9

5-3

5.2.11

5-4

5.2.10

5-3

Logical AND instruction

5.12.3

5-45

Logical Exclusive OR
instruction

5.12.2

5-45

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

Page

Logical instructions
LClgical AND
Logical Exclusive OR
Logical OR
Masked Load Upper

5.12.3
5.12.2
5.12.1
5.12.4

5-45
5-45
5-45
5-46

Logical OR instruction

5.12.1

5-45

M
Machine check interrupts

7.4.1

Magnitude of Characteristic
DiffEtrence to Upper
instruction
5.5.15

7-19

Index-11
UPDATE \.lV£L

Term

PAGE

Reference

Page

Masked Load Upper
instruction

5.12.4

5-46

Masked Search Equal
instruction

5.6.7

5-24

Masked Search Greater
instruction

5.6.10

5-25

Masked Search Less Than
or Equal/Not Greater
instruction

5.6.9

5-25

5.6.8

5-25

Mask~d

Search N'ot Equal
instruction

5-19

Main storage organization

8.3.1

8-8

Masked Search Not Within
Range instruction

5.6.12

5-26

Main storage unit
address generation
address parity

Table 3-4

3-13

Masked Search Within
Range instruction

5.6.11

5-26

3.2.5

3-3

3.2.3

3-3

3.2.7

3-4

3.2.2
3.3.6.2
3.2.6

3-2
3-14
3-3

5.13.3
5.13.4
5.13.14
5.13; 1
5.13.12
5.13.10
5.13.2
5. 13. 11

5-47
5-47 .
5-51
5-46
5-49
5-49
5-47
5-49

3.2.4

3-3

3.2.1

3-2

5.13.7
5.13.5
5.13.8
5.13.6

5-48
5-48
5-48
5-48

Main store interlace
(MSI) stack

3.3.3

3-8

5.13.9
5.13.13

5-48
5-49

MaintEtnance SEtction

2.4

2-1
Mode, addressing

3.3.6.1

3-10

Mask register

3.4.2.19
3.4.2.25

3-20
3-20

Module select register

3.2.7
5.15.5

3-4
5-70

Monitor

6.9.2

6-44

5.6.14

5-28
MSR

3.2.7

3-4

Multiplication
fixed-point
floating-point

4.2.6
4.2.15

4-4
4-10

checkinl~

ECC write check
disable
fbted addrf~ss
assignments
partial write error
detection
partitioning
rE~fresh fault
write control parity
checking
write data error
detection

Maskeld Alphanumeric
Sealrch Greater
i"structions
Masketd Alphanumeric
Sealrch Less Than or
E:qual instruction

5.6.13

5-27

Miscellaneous instructions
Execute
Executive Request
Increase
Load DR Designators
Load Register Set
No Operation
Store DR Designators
Store Register Set
Test and Clear and
Skip
Test and Set
Test and Set Alternate
Test and Set and Skip
Test and Set and Skip
Alternate
Test Relative Address

8804 Rev. 1

SPERRY'UNIVAC 1100/80 Systems

UP-NUMiER

4x4 Capability Processor and Storage Programmer Reference

Reference

Page

Multiply Fractional
instruction

5.4.11

5-9

Multiply Integer instruction

5.4.9

5-8

Mlultiply Single Integer
instruction

5.4.10

5-8

Term

Multiprocessor interrupt
synchronization

7.3.9

7-18

·N
Nc:> Operation instruction

5.13.10

5-49

Normal interrupt registers

3.4.2.7

3-18

Nlormal interrupts

7.4.2

7-21

Normal status register

3.4.2.13

3-19

Normalized floating-point
numbers

4.2.9

4-8

0
Octal vs mnemonic
instruction code

Table C-3

C-20

Overflow

4.2.4.1

4-3

IPAGE

Ind••-12

UPDATE L£Vn

Reference

Page

Processing unit
arithmetic section
control section
maintenance section

2.3
2.2
2.4

2-2
2-1
2-2

Processor interrupt errors

7.5.1

7-32

Processor state

8.2

8-1

Program Controlled
interrupt

6.9.1

6-44

Program exception
interrupts
Address Exception
Guard Mode
Invalid Instruction

7.3.1
7.3.1
7.3.1

7-5
7-5
7-5

Program initiated interrupts
Breakpoint
Executive Request
Jump History Stack
Test and Set

7.3.3
7.3.3
7.3.3
7.3.3

7-8
7-8
7-8
7-8

Program segmentation

8.3.2

8-8

P-capturing instructions

8.3.9

8-13

3.4.2.10

3-18

Term

Q
Quantum timer register

R

P
Parity checking

3.2.4

3-3

Real-time clock interrupts

7.3.5

7-10

Partitioning

1.2.5
3.3.&.2

1-9
3-14

Real-time clock register

3.4.2.17

3-19

Relative address

8.3.3

8-8

Repeat count register

3.4.2.18
3.4.2.24

3-19
3-20

Reset Auto-Recovery Timer
5.15.16
instruction

5-76

Peripheral subsystems
destandardized
minimum complement
standard
Power Check interrupt

Prevent All Interrupts and
Jump instruction

1.2.9
1.2.10
1.2.8

1-11
1-11
1-10

7.3.7
Figure 7-9

7-17
7-18

5.15.1

5-69

Residue

4.2.8.4

4-8

Right algebraic shifting

5.8

5-32

8604 Rev. 1
U'.......'M8ER

SPERR" UNIVAC 1 tOO/80 Syster'ls

4x4 Capability Processor and Storage Programmer Reference

Term

Reference

Page

Inclex-t 3
UPOATE I.&VEl.

Term

PAGE

Reference

Page

I
Right circular shifting

5.8

5-32

Search Equal instruction

5.6.1

5-21

Right .Iogical shifting

5.8

5-32

Search Greater instruction

5.6.4

5-23

3.4.2.23
3.4.2.24
3.4.2.25
3.4.2.26
3.4.2.27
3.4.2.28
3.4.2.18
3.4.2.18
3.4.2.19
3.4.2.20
3.4.2.22

3-20 .
3-20
3-20
3-20
3-20
3-21
3-19
3-19
3-20
3-20
3-20

Search Less Than or
Equal/Search Not
Greater instruction

5.6.3

5-22

Search Not Equal
instruction

5.6.2

5-22

Search Not Within Range
instruction

5.6.6

5-24

Search Within Range
instruction

5.6.5

5-23

3.3.7
E.5

3-15
E-64

3.3.7
E.4

3-15
E-18

Select Oayclock instruction

5.15.4

5-70

Select interrupt locations

Figure 5-2

5-71

R-regis1ters
Executive

user

Segment/bank storage
configurations

S
Scientific accelEtrator
module
Search and ma~~ked-search
instructions
Masked Alphanumeric
Search Greater
Masked Alphanumeric
Search Less Than
or Equal
Masked SE~arch Equal
Masked SE~arch
Greater
Masked S4~arch Less
Than or Equal/Not
Greater
Masked Search Not
Equal
Masked Search, Not
Within Range
Masked Slearch Within
Range
S;earch Equal
Search Greater
Search Less Than or
Equal/Search Not
Greater
Search Not Equal
Search N(lt Within
Range
Search Within Range

2.3

5.6.14

2-2

Segment/cabinet storage
configurations

5-28

5.6.13
5.6.7

5-27
5-24

I

Select Interrupt Locations
instruction

5.15.5

5-70

5.6.10

5-25

Shift count

4.3.2.8.3

4-25

5.6.9

5-25

5.6.8

5-25

5.6.12

5-26

5.8.8
5.8.6
5.8.2
5.8.4

5-36
5-35
5-34
5-35

5.6.11
5.6.1
5.6.4

5-26
5-21
5-23

5.8.10

5-36

5.8.12

5-37

5.8.9

5-36

5.6.3
5.6.2

5-22
5-22

5.6.6
5.6.5

5-24
5-23

5.8.11
5.8.7
5.8.5
5.8.1
5.8.3

5-36
5-35
5-35
5-34
5-34

Shift instructions
Double Load Shift and
Count
Double Shift Algebraic
Double Shift Circular
Double Shift Logical
Left Double Shift
Circular
Left Double Shift
Logical
Left Single Shift
Circular
Left Single Shift
Logical
Load Shift and Count
Single Shift Algebraic
Single Shift Circular
Single Shift Logical

SPERRY UNIVAC 1100/80 Systems

4x4 Capability Processor and Storage Programmer Reference

Term

Shifting
left circular
left logical
right algebraic
right circular
right logical

Reference

5.8
5.8
5.8
5.8
5.8

Page

5-32
5-32
5-32
5-32
5-32

Term
partitioning
storage interleave
tag and data buffer
Storage interleave
Storage system

Index-14

Reference

Page

3.3.6.2
3.3.6
3.3.2

3-14
3-9
3-7

3.3.6

3-9

Figure 5-2

1-7

1.2.2
S~ction

SIL data word

!lAGE

U!tOATI LIVEL

3

5-71
Store A instruction

5.3.1

5-4

5-35

Store Constant instructions 5.3.5

5-5

5.8.1

5-34

Store Designator Register
instruction

5.15.14

5-75

Single Shift Logical
instruction

5.8.3

5-34

Store DR Designators
instruction

5.13.2

5-47

SIU/MSU interface check
interrupt

7.3.6.2.2

7-14

SIU/MSU read or partial
write ECC check
interrupt

5.3.8
5.3.7
5.3.1

5-6
5-5
5-4

7.3.6.2.3

7-16

3.4.2.20
3.4.2.26

3-20
3-20

5.3.5
5.3.3
5.3.2
5.3.4
5.3.6

5-5
5-4
5-4
5-5
5-5

Start I/O Fast Release
instruction

6.4.2

6-17

Store Location and Jump
instruction

5.9.1

5-37

Status table

6.12

6-51
Store Magnitude A
instruction

5.3.3

5-4

Store Negative A
instruction

5.3.2

5-4

Store Processor 10
instruction

5.15.7

5-74

Store Quantum Time
instruction

5.15.12

5-75

Store R instruction

5.3.4

5-5

Store Register Set
instruction

5. 13. 11

5-49

6.6.2
6.13

6-37
6-53

Single Shift Algebraic
instruction

5.8.5

S;ingle Shift Circular
instruction

Staging registers

Storage check interrupts
Delayed Storage
Check
Immediate Storage
Check
Storage configurations

Storage interface unit
addressing modes
error detection and
reporting
functional
characteristics
general
invalidate interface
main store interlace
stack

7.3.6.2

7-12

7.3.6.1

7-11

3.3.7
3-15
Appendix E

3.3.6.1

3-10

3.3.5

3-8

3.:l.1
3.3
3.3.4

3-6
3-5
3-8

3.3.3

3-8

Store instructions
Block Transfer
Double Store A
Store A
Store Constant
instructions
Store Magnitude A
Store Negative A
Store R
Store X

Store Subchannel Status
command

peR"Y UNIVAC 1100/80 Systems

-------~
8604 Rev. 1

Index-15

4x4 Capability Processor and Storage Programmer Reference

UI'oMIMIP

Reference

Page

Store System Status
instlruction

5. 15. 18

5-76

Store X instruction

5.3.6

5-5

Term

Subchannel expan~on
feature channel base
r.,gister
Subchannel states

Subchannel status

6.17

6-64

6.3.2
Table 6-2

6-6
6-9

6.14

6-53

Subchannels, IOU
fun.:tional
characteristics

6.2.2

6-5

Subfunction byte

5.14.5.2

5-60

Subsystem availability unit

1.2.6

1-10

1.2.4

1-8

1.2.7

1-10

System

consoh~

System maintenance unit

System minimum/maximum
Table 1-1
configurations
System status word

Systelm transition unit

2.6

Term

'AGE

Reference

Page

Test and Set Alternate
instruction

5.13.8

5-48

Test and Set and Skip
Alternate instruction

5.13.9

5-48

Test and Set and Skip
instruction

5.13.6

5-48

Test and Set instruction

5.13.5

5-48

Test Equal instruction

5.7.6

5-30

Test Even Parity instruction 5.7.1

5-28

Test Greater instruction

5.7.9

5-31

Test Less Than or
Equal/Test Not Greater
instruction

5.7.8

·5-30

T est Less Than or
Equal/Test Not Greater
Than Modifier
instruction

5.7.3

5-29

Test Negative instruction

5.7.13

5-32

Test Nonzero instruction

5.7.5

5-30

Test Not Equal instruction

5.7.7

5-30

Test Not Within Range
instruction

5.7.11

5-31

Test Odd Parity instruction

5.7.2

5-29

1-6

Figure 2-1

2-3
2-4

1.2.5

1-9

T
Tabled interrupts

7.4.3

7-29

Test Positive instruction

5.7.12

5-32

Tabled status word

6.10

6-45

Test Relative Address
instruction

5.13.13

5-49

Termination conditiorts
byte or block
multiplc!xer
. channel
word channel

Table 6-9 6-33
Table 6-10 6-35

Test clnd Clear and Skip
instruction

5.13.7

Test Subchannel instruction 6.4.4

6-19

Test Within Range
instruction

5.7.10

5-31

Test Zero instruction

5.7.4

5-29

Test (or skip) instructions
Double-Precision Test
Equal

5.7.14

5-32

5-48

8804 Rev. 1

SPERRY UNIVAC 1100/80 Systems

\JNIIU......

4x4 Capability Processor and Storage Programmer Reference

T«trm
Test Equal
Test Even Parity
Test Greater
Test Less Than or
EQual/Test Not
Greater
Test Less Than or
Equal/Test Not
Greater Than
Modifier
Test Negative
Test Nonzero '
Test Not Equal
Test Not Within Range
Test Odd Parity
Test Positive
Test Within Range
Test Zero

Reference

Page

5.7.6
5.7.1
5.7.9

5-30
5-28
5-31

5',7.8

5-30

Term

Index-16
'AGE

Reference

Page

3.4.2.18
3.4.2.19
3.4.2.20
3.4.2.22
3.4.2.2

3-19
3-20
3-20
3-20
3-17

yser bank descriptor table
pointer register

3.4.2.8

3-18

R-registers

X-registers

5.7.3
5.7.13
5.7.5
5.7.7
5.7.11
5.7.2
5.7.12
5.7.10
5.7.4

5-29
5-32
5-30
5-30
5-31
5-29
5-32
5-31
5-29

User Return instruction

5.15.15

5-75

u-field

4.3.2.8

4-24

Word channel
termination conditions

Table 6-10 6-35

8.3.3

8-8

Word formats

Appendix B

Toggle Auto-Recovery Path
instruction .
5.15.17

76-5

WRITE DATA CHECK signal 3.2.1
3.2.2

Transfer in Channel
command

6.6.1

6-36

Truncated search

6.8.4

6-41

x-field

4.3.2.5

4-22

Truncated search
restrictions

6.S.5

6-42

X-registers
Executive
user

3.4.2.29
3.4.2.2

3-21
3-17

Theory, addressing

.

U
Unconditional jump
instructions
Allow All Interrupt and
"1
Jump
5.9.3
Load Modifier and
Jump
5.9.2
Store Location and
Jump
5.9.1

5-37

User registers
A-registers
Index registers
J-registers

3-18
3-17
3-20

3.4.2.3
3.4.2.2
3.4.2.21

5-38
5-37

W

3-2
3-2

X

o

18 17

35 34 33 32

ESI ACCESS CONTROL WORD (QUARTER WORD)

o

18 17

35 34 33 32 31 30 29

BYTE MANIPULATION STAGING REGISTER 1

BT
BS2
0

BS3

BS4

1 2 3 4 5 6 7 8
18 17

27 26

315

0

9 8

BYTE MANIPULATION STAGING REGISTER 2

[

BH1

BHO

0

18 17

:'15

BYTE MANIPULATION STAGING REGISTER 3

[ _______B_B_O______
35

~

_______B_B_1______

~

________
BB_2______

18 17

27 26

~

________
B_B3____

9 8

,~
o

J REGISTER

~'5

34 33 32 31

21 20

18 17

320

163

Appendix C. Instruction Repertoire and Instruction Times

The estirnated im.truction times given below are a subset of the actual execution times, Actual
execution times are a function of SIU conflicts, storage spigot conflicts, internal CPU instruction
sequencing conflicts, register conflicts, timing between CPU and storage, and interrupt processing,
Also, system parameters which affect actual execution times are instruction storage access, storage
characteristics (i.e" cycle time, storage refresh time, access time, and service time) and cable lengths,
See AppE~ndix A for notational conventions used in the description column, and the notes at the end
of the table for additional information on the instruction times, For the meaning of the symbol '*'
(used in the Mnemonic column), and the symbols 'a' and 'b' (used in the Instruction Time column, see
the end of the table,

Mnemonic

Functicm
Code
(Octal)

f
00

Instruction

Description

Instruction
Time (in
ns)

ji
0-117

-

Invalid Code

Causes Invalid Instruction interrupt to address

1150

221 8
01

0-~17

S, SA

Store A

(A.) -

02

0-'17

SN,SNA

Store Negative A

- (A.) -

U

200

03

0-'17

SM, SMA

Store Magnitude A

I (A.) I - U

200

04

0-'17

S, SR

Store R

(R.) -

200

05

0-'17

SZ
(a=O)

Store Zero

000000 000000 -

164

200

U

U
U

200

Mne~monic

Function
Code
(Octal)

Instruction

Description

Instruction
Time (in
ns)

f
05

j
0-17

SNZ

Store Negative Zero

777777 777777 -

U

200

Store Positive One

000000 000001

-u

200

Store Negative One

777777 777776 -

Store Fieldata Blanks

050505 050505 -

U

200

Store Fieldata Zeros

606060 606060 -

u

200

Store ASCII Blanks

040040 040040 -

U

200

Store ASCII Zeros

060060 060060 -

U

200

(a= 1)

05

0-17'

SP1
(a=2)

05

0-17'

I SN1

U

200

(a=3)

05

0-17

SFS
(a=4)

05

0-17

05

0-17

I

SFZ
I (a=5)

SAS
(a=6)

05

0-17

SAZ
(a=7)

, 'c

05

0-17

INC

ilncrease

(a= 10)

05

0-17

DEC

Decrease

(a= 1'1)

05

0-17

INC 2
(a=

05

0-1'1

Incr~~se

by 2

1:~)

DEC 2
(a= 1 :3)

Decrease by 2

(U) + 1 - U. If initial or final value of U=O,
execute N; else skip NI

5501750

(U) - 1 - U. If initial or final value of U=O,
execute NI; else skip NI

5501750

(U) + 2 - U. If initial or final value of U=O,
execute NI; else skip NI

5501750

(U) - 2 - U. If initial or final value of U=O,
execute NI; else skip NI

5501750

165

-.~

.'"
I



>

F

(A.)

= 0; string E ==

F

(A.)

<

F

0; string E
0; string E

<

1600 +
2000N

33

04

BC

Byte Compare

Compare N bytes from string E to M bytes
from string F; terminate instruction on not
equal or when both M and N are zero

1600 +
2000N

33

05

BPD*

Byte to Packed
Decimal Convert

Convert N bytes in string E to packed decimal
in string F

-

33

0~3

PDB*

Packed Decimal to
Byte Convert

Convert N packed decimal digits in string E to
bytes in string F

-

33

0~7

EDIT

Edit

Edit byte string E and transfer to byte string F
under the control of string G (see Note 2 (b))

• -

Simulated in software by the Executive System.

168

Skip

4600 +
500N,

Editing action

4600 +
2300N 2

Blank if zero

4600 +
1000N 2

FunctionF-monic
Code
I
(Octal)
!

i

'fl'
33

Instruction
Time (in
ns)

II

I
I

I
i

i
;

I
BI

10

Description

Instruction

I
!
!

I

j

I

i
Byte to Binary

Convert N bytes in string E into a signed

1800 +

Single Integer

binary integer ·in register A.

750N

Convert
33

i

11

BDI

: Byte to Binary

!

I

I

!

I

DIB

I

i

II 33
I
I 33

IB

13

33

14

BF

I

1950 +
750N

Binary Single Integer

Convert the binary integer in A. to byte format

8850 +

and store in string E

SOON

Binary Double Integer

Convert the binary integer in A. and A. + 1 to

9100 +

to Byte Convert

byte format and store in string E

SOON

Byte to Single

Convert N bytes in string E into a single

13,850+

length floating point format in register Aa

1050N

I

Bytp. to Double

Convert N bytes in string E into a double

13,850+

i

Floating Convert

length floating point format in registers A a,
As+ 1

1050N

Single Floating to

Convert the single length floating point

5150 +

Byte Convert

number in As to byte format and store in

1050N

:

I

:
:

15

BDF

16

33

FB

i

string E

!

:

33

17

OrB

i

I

Double Floating to
Byte Convert

I
I

Convert the double length floating point

5150 +

number in As and A. + 1 to byte format and

1050N

I store in string E

Ii
I

signed

Floating Convert

,
,

I

iI

a

to Byte Convert

I
I

Convert N bytes in string E into

binary integer in registers A. and A. + 1

Convert

i

12

33

I

Double Integer

I

34

i

i

01

0-17

Divide Integer

i (As' A. + 1~ (U) I

As: REMAINDER -

Aa+ 1

1400 +
100b

I

35

0-17

DSF

Divide Single

(Aa)f(U) -

5800

A.+ 1

Fractional
36
37

0-17

I 00

OF

Divide Fractional

OB*

Ouarter-Word Byte

(A., As+ 1)f(U) -

Discard (A)35' (A)26,(A)17' and (A)s: place the

I

remaining bits in A 31 -O: (A)31 -

i
37

01

Binary to Ouarter-

\

• -

==

5800

-

A 35 - 32

I

BO*

Word Byte Extend

b

A a, REMAINDER ~ As+ 1

Discard (A)35-32; place the remaining bits in
I A - , A - ' A _ , and A7-O: zero fill A ,
,6 9
34 27
25 1S
35
I A 26 , A 17 , and As

-

I

Simulatlsd in software by the Executive System.
Number- of arithmetic loops

169

Mnemonic

Function
Code

Instruction

Description

Instruction
Time (in
ns)

(Oct~JI)

f
37

j
02

OBH*

Ouarter-Word Byte to
Binary Halves
Compress

A U - 34 ; (A),5 -

-

Discard (A)35' (A)2e' (A)17' and (A)8; placa the
remaining bits in A 33- 18 and A'5-O; (A)33
A 17_ 18

37

03

BHO*

Binary Halves to
Ouarter- Word Byte
Extend

Discard (A)35-34 and (A)17_1e; place the
remaining bits in A u -27 • A 25 - 18 • A 18- 9. and
A 7-o; zero fill A 35 • A 28 • A 17 • and As

-

37

04

ODB*

Ouarter-Word Byte to
Double Binary
Compress

Discard A35 • A28 • A 17 • A 8• A+ '35' A+ '28'
A+ 1 17 , and A+ 's; place the remaining bits in
A 27-O and A+ 1; (A)27 - A 35- 2S

-

37

05

DBO*

Double Binary to
Ouarter-Word Byte
Extend

Discard (A)35-2S; place the remaining bits from

-

A and A+ 1 in A 34- 27 • A 25- 18 - A uS- 9 ' A7-01
A+ 134- 27 , A+ 125- 18, A+ 1 18- 91 and A+ '7-0;
zero fill A 35 • A281 A 17 • As. A+ 135 , A+ 126 A+ 117 , and A+ 18

37

06

BA

Byte Add

Add the N bytes in string E to the M bytes in
string F and place the result in string G (see
Note 7)

1300 +
15001
2500N

37

07

BAN

Byte Add Negative

Subtract the N bytes in string E from the M
bytes in string F and place the result in string
G (see Note 7)

1300 +
15001
2500N

37

10-17

-

Invalid Code

Causes invalid instruction interrupt to address
221 8

-

40

0-17

OR

Logical OR

(A.)

rem (U)

41

0-17

XOR

Logical Exclusive OR

(A.)

ImBI (U)

42

0-17

AND

Logical AND

(A.)

rAfm

43

0-17

MLU

Masked Load Upper

[(U) AND (R2)] OR [(A.) AND (R2)'] -

44

0-17

TEP

Test Even Parity

Skip NI if (U) AND (A.) has even parity

450/650

45

0-17

TOP

Test Odd Parity

Skip NI if (U) AND (A.) has odd parity

450/650

46

()"'17

LXI

Load X Increment

(U) -

200

• - Simulated in software by the Executive System.

170

-

250

A.+1
-

A. + 1

250

(U) -

A. + 1

250

(X.)35-18; (X.),7-O unchanged

A.+1

550

Function

Mnemonic

Instruction

Instruction
Time (in
ns)

Description

Code!
(Octall)

f

,j

47

0-'17

TLEM

Test Less Than or
Equal to Modifier

Skip NI if (U) ( (X.)17-O; always (X.) 17-0
35-18 -

+ (X.)

600/800

X. 17 -O

TNGM

Test Not Greater
Modifier

Alternate mnemonic for TLEM instruction

50

0-17

TZ

Test Zero

SkQP NI if (U)=t 0

350/550

51

0-17

TNZ

Test Nonzero

Skip NI if (U) tt 0

350/550

52

0-17

TE

Test Equal

Skip NI if (U)=(A.)

350/550

53

0-17

TNE

Test Not Equal

Sk:ip NI if (U) t (A.)

350/550

54

0-17

TLE

Test Less Than or
Equal

Skip NI if (U) ( (A.)

450/650

TNG

Test Not Greater

55

0-17

TG

Test Greater

Skip NI if (U»(A.)

450/650

56

0-17

TW

Test Within Range

Skip NI if (A.)«U) ( (A.+ 1)

5001700

57

0-17

TNW

Test Not Within

Skip NI if (U) ( (A.) or (U»(A. + 1)

5001700

Range
60

0-17

TP

Test Positive

Skip NI if (U)3S=0

350/550

61

0-17

TN

Test Negative

Skip NI if (U)35= 1

350/550

62

0-17

SE

Search Equal

Skip NI if (U)=(A.), else repeat

1050 +
200a

63

0-'17

SNE

Search Not Equal

Skip NI if (U) t (A.), else repeat

1050 +
200a

64

0-'17

SLE

Search Less Than or
Equal

Skip NI if (U) ( (A.), else repeat

1050 +
200a

SNG

Search Not Greater

Alternate mnemonic for SLE instruction

SG

Search Greater

Skip NI jf (U)

65

0-17

>

(A.), else repeat

1050 +
200a

a - Number of words

171

Function
Code
(Octal)

Mnemonic

Instruction

Description

Instruction
Time (in
ns)

_.

f

j

66

0--1 '7

SW

67

0--17

SNW

Search Within Range

Skip NI if (A.)«U) , (A.+ 1). else repeat

1100 +
200a

Search Not Within

Skip NJ if (U) , (A.) or (U»(A.+ 1). else repeat

1100
200a

Jump to U if (Control Registerj.»O; go to NI if
(Control Registerj.) , 0; always (Control

200/300

Range
70

0--17

JGD

Jump Greater and
Decrement

Registerj .) -1 -

+

Control Registerj •

71

00

MSE

Mask Search Equal

Skip NI if (U) ~ (R2) - (A.) ~ (R2). else
repeat

1050
200a

+

71

01

MSNE

Mask Search Not
Equal

Skip NI if (U) ~ (R2) ~ (A.) ~ (R2). else
repeat

1050
200a

+

71

02

MSLE

Mask Search Less
Than or Equal

Skip NI if (U) ~ (R2) , (A.) ~ (R2). else
repeat

1050
200a

+

MSNG

Mask Search Not
Greater

Alternate mnemonic for MSLE instruction

Skip NI if (U)
repeat

1050
200a

+

1100
200a

+

1100
200a

+

71

03

MSG

Mask Search Greater

71

04

MSW

Masked Search
Within Range

71

71

71

05

06

07

MSNW

MASL

MASG

Masked Search Not
Within Range
Masked Alphanumeric Search Less
Than or Equal
Masked
Alphanumeric

mm (R2) > (A.) mm (R2). else

Skip NI if (A.)

mm (R2) < (U) mm (R2) ,

mm (R2). else repeat
Skip NI if (U) mm (R2) , (A.) mm (R2) or (U)
mm (R2) > (A.+ 1) (R2). else repeat
Skip NI if (U) m (R2) , (A.) mm (R2). else
(A. + 1)

~

repeat

Skip NI if (U)
repeat

m (R2) > (A.) mm (R2). else

1050 +
200a

1050
200a

Search Greater
71

10

DA

• - NUrT'lber of words

172

Double Precision
Fixed-Point Add

(A•• A.

+ 1) + (U.

U + 1) -

A•• A. + 1

450

+

Function
Code
(Octal)

f

Mnemonic

Instruction

Description

Instruction
Time (in
ns)

j

71

11

DAN

Double Precision
Fixed-Point Add
Negative

(A., A.+ 1) - (U,U+ 1) -

71

12

OS

Double Store A

(A., A.+ 1) -

71

.13

Dl

Double load A

(U, U+1) -

71

14

DlN

Double load
Negative A

- (U, U+1) -

A., A.+1

400

71

15

DlM

Double load
Magnitude A

I (U, U+ 1) I - A., A.+1

400

71

16

DJZ

Double Precision
Jump Zero

Jump to U if (A., A.+ 1) = :to; go to NI if (A.,

250/350

A., A.+ 1

450

U, U+ 1

400

A., A.+1

400

A.+ 1) ~:!:O

71

17

DTE

Double Precision
Test Equal

Skip NI if (U, U+1) = (A., A.+1)

5501750

72

00

IMI

Initiate Maintenance
Interrupt

Send Attention interrupt to Maintenance
Processor if in maintenance mode, otherwise
NOP

200

72

01

SlJ

Store location and
Jump

(p~Base

400

Address Modifier -

U , '-O; jump to

U+1

72

02

JPS

Jump Positive and
Shift

Jump to U if (A.)35=0; go to NI if (A.)35= 1;
always shift (A.) left circularly one bit position

200/300

72

03

JNS

Jump Negative and
Shift

Jump to U if (A.)35= 1; go to NI if (A.)35=0;
always shift (A.) left circularly one bit pOSition

200/300

72

04

AH

Add Halves

(A.)35_ 1S+ (U)35_ 1e (U) 17-0 - A. 17 -O

(A.)35-1S; (A.)17-O+

500

(A.)35-1e- (U)35-1S -

(A.)35-1a; (A.)17-O- (U)17-O

500

-

72

05

ANH

Add Negative Halves

72

06

AT

Add Thirds

A. ,7 -O

(A.)35-24+(U)35-24 - A. 35- 24 ;
(A.)23-12+(U) 23-12 - A. 23-12

800

173

Function
Code
(Octal)

f

Mnemonic

Instruction

Description

Instruction
Time (in
ns)

j
(A.)11-O +(U)11-O

-

A. 11-O

72

07

ANT

Add Negative Thirds

(A.)35-2 .. - (U)35-24 - A d5 - 24 ;
(A.)23-12- (U)23-12 - A. 23- 12 ;
(A.), 1-0- (U) 11-0 - A. 11 -O

850

72

10

EX

Execute

Execute the instruction at U

300

72

1 'I

ER

Executive Request

Causes Executive Request interrupt to address

1250

2228
72

12

-

Invalid Code

Causes Invalid Instruction interrupt to address
221 8

1150

72

13

PAIJ

Prevent all Interrupts
and Jump

Disable all interrupts and jump to U

300

72

14

-

'nvalid Code

Causes Invalid Instruction interrupt to address
221 8

1150

72

15

TRA

Test Relative Address

Test a given relative address against limits

20501

(see Note 8)

2850

72

16

SRS

Store Register Set

Transfer GRS areas defined in A. to storage
starting at address U

800 +
200a

72

1'7

LRS

Load Register Set

Transfer from storage starting at location U to
GRS areas defined in A.

800 +
200a

73

OlD

SSC

Single Shift Circular

Shift (A.) right circularly U places

350

73

01

DSC

Double Shift Circular

Shift (A., A. + 1) right circularly U places

400

73

02

SSL

Single Shift Logical

Shift (A.) right U places; zero fill

200

73

03

DSL

Double Shift Logical

Shift (A.- A. + 1) right U places; zero fill

300

73

04

SSA

Single Shift Algebraic

Shift (A.) right U places; sign fill

200

73

05

DSA

Double Shift
Algebraic

Shift (A._ A.+ 1) right U places; sign fill

300

a - Number of words

174

Function
Code
(Octal)

f
73

Mnemonic

Description

Instruction

Instruction
Time (in
ns)

j
06

LSC

Load Shift and Count

(U) -

A., shift (A.) left circularly until (A.i35 t.

(A.)34; NUMBER OF SHIFTS -

550

A.+ 1

73

07

DlSe:

Double load Shift
and Count

(U,U+ 1) - A., A.+ 1; shift (A., A.+ 1) left
circularly until (A., A. + 1)71 t. (A., A. + 1)70;
NUMBER OF SHIFTS - A.+2

1350

73

10

LSSC

Left Single Shift
Circular

Shift (A.) left circularly U places

350

73

11

LOSe

Left Double Shift

Shift (A., A. + 1) left circU"Hly U places

400

Circular
73

12

lSSl.

Left Single Shift
Logical

Shift (A.) left U place; zero fill

200

73

13

LDSL.

left Double Shift
logical

Shift (A., As + 1) left U places; zero fill

300

73

14

lDC

load Dayclock

(MSR + 216 8) update cycle

200

(a== 10)

dayclock at start of next

~

73

14

EDC
(a== 11)

Enable Dayclock

Enable dayclock

200

73

14

DOC
(a== 12)

Disable Dayclock

Disable dayclock

200

73

14

SOC
(a== 13)

Select Dayclock

Select dayclock in processor number U

200

73

14

MDA
(a== ~ 4)

Diagnostics A

Generates A, A+ 1 and U, U+ 1 operands to
test arithmetic; stores results,

4850

A=00372706711 and A+ 1 =
256171354400 in GRS addresses 628 and
63 8
73

14

MOB
(a='15)

Diagnostics B

Generates A. A+ 1 and U, U+ 1 operands to
test arithmetic; stores results,
A=771177117711 and

4850

A+ 1 =777777776677 in GRS addresses 628
and 63 8

175

Functlion
Code
(Octnl)

Mnemonic

Instruction

Description

Instruction
Time (in
ns)

j

f
73

14

NOP
(a=:16.17)

73

15

SIL
(a=:O)

Location

-

Invalid Code

Causes Invalid Instruction interrupt to address
221 8

1150

Load Breakpoint
Register

(U) -

Breakpoint Register (see Note 9)

5501750

(a=2)

LOT

Load Ouantum Timer

(U) -

Quantum Timer

500

Initiate Interprocessor
Interrupt

Interrupt CPU specified by U

200

(a=4)

SPIO

Store Processor 10

Store processor serial number. revision level.

200

73

15

No Operation

Proceed to NI

200

Select Interrupt

(U)22-1e -

600

(a= 1)

73

73

15

15

LBRX

MSR specified by (U)23

(a=3)

73

73

15

15

III

(a=5)

73

73

73

15

15

15

RAT

features provided. and system number in U

(a=6)

Reset Auto-Recovery
Timer

Set auto-recovery timer to zero

200

TAP
(a=7)

Toggle

Toggle auto-recovery path selection after each

200

Auto-Recovery Path

attempt

LB

Load Base

(U),7-O -

Load Limits

(U)35-24 and (U)23-15 specified (X x)34,33

BOR specified by (X x)34.33

600

(a=10)

73

176

15

LL
(a= 11)

BOR limits fields

600

Function
Code
(Octal)

f

Mnemonic

Instruction

Description

Instruction
Time (in
ns)

j

73

15

LAE
(a.12)

Load Addressing
Environment

(U,U+ 1) - BDI Registers in GRS locations
46 8 and 478: BD limits and Base Values to
BDRs.

1850

73

15

SQT
(a-13)

Store Quantum Timer

(Quantum Timer) - U

200

73

15

LD
(a-14)

Load Designator
Register

(U) -

650

73

15

SO
(a-15)

Store Designator
Register

(Designator Register) -

73

15

UR
(a-16)

User Return

(U + 1) - Designator Register; jump to
address specified by (U)23-O using new
register set

850

73

15

SSS
(a-17)

Store System Status

System Status -

1050

73

16

-

Invalid Code

Causes Invalid Instruction interrupt to address

Designator Register

U

U,U+l

450

1150

221 8
73

73

73

73

17

17

17

17

TS
(a-O)

Test and Set

TSS
(a-1)

Test and Set and
Skip

TCS
(a-2)

Test and Clear and
Skip-·

;> 200 clear (U)36-30

TSA
(a-4)

Test and Set
Alternate

If (U)'4- 1 interrupt; if (U)'4-0 go to NI;
always set (U)'4-O to ones

If (U)30- 1, interrupt: if (U)30.0. go to NI, and

1450/400

if U )I 200 set (U)36-30 to 018

If (U)30- 1. go to NI; if (U)30 - O. skip. and if

400/600

U ;> 200 set (U)36-30 to 018

If (U)30-0. go to NI; if (U)30- 1, skip. and if U

400/600

1450/400

177

Function
Code
(Octal)

f
73

Mnemonic

Instruction

Description

Instruction
Time (in
ns)

j
17

I
Test and Set and
Skip Alternate

If (U)'4-1 go to NI, if (U)'4-0 skip NI; aiways
set (U), 4-0 to ones

400/600

(a-51

TSSA

± 0

200/300

± 0; go to NI if (A.) - ± 0

200/300

74

00

JZ

Jump Zero

Jump to U if (A.) -

74

01

JNZ

Jump Nonzero

Jump to U if (A.)

74

02

JP

Jump Positive

Jump to U if (A')35-0; go to NI if (A.I35 = 1

200/300

74

03

JN

Jump Negative

Jump to U if (A.)3S= 1; go to NI if (A.135-0

200/300

74

04

J

Jump

Jump to U

300

Jump Keys

Jump to U if a-lit SELECT JUMP indicator

200/300

Halt Jump

Jump to U and halt

Halt

Halt Keys and Jump

Jump to U; stop if a

'I.

:t

0; go to NI if (A.)

'I.

(a-Ol

74

04

JK
(atOI

74

05

HJ
(a=OI

74

05

HKJ
(at. 01

74

06

NOP

74

07

AAIJ

indicators

'I.

mm lit SELECT STOP

200/Hait

0

No Operation

Proceed to N I

200

Allow All Interrupts

Allow all interrupts and jump to U

300

and Jump
74

10

JNB

Jump No Low Bit

Jump to U if (A.lo-O; go to NI if (A.lo - 1

200/300

74

11

JB

Jump Low Bit

Jump to U if (A.lo = 1; go to NI if (A.lo=O

200/300

74

12

JMGI

Jump Modifier

Jump to U if (X.I 17-O>O; go to NI if (X.I17-O (

200/300

Greater

0; always (X.I, 7-0

+

(X.135-O -

X. ,7-O

and Increment
74

178

.113

LMJ

Load Modifier and
Jump

(P) - Base Address Modifier to U

(X.I'7-O; jump

300

Function
Code
(Octal)

f
74

Mnemonic

1_.

Instruction
Time (in
ns)

Description

Instruction

j
14

Jump Overflow

Jump to U if 01=1; go to NI if 01=0

200/300

JFU

Jump Floating

Jump to U if 021 = 1; go to NI if 021 =0;

200/300

(8=1)

Underflow

clear 021

JO
(8=0)

74

14

I

74

74

14

14

JFO

Jump Floating

Jump to U if 022= 1; go to NI if 022=0;

(a=2)

Overflow

clear 022

JOF

Jump Divide Fault

Jump to U if 023= 1; go to NI if 023=0;
clear 023

(a=3)

74

15

JNO

Jump No Overflow

200/300

200/300
I

I

Jump to U if 01 =0; go to NI if 01= 1

200/300

200/300

(a=O)

74

74

74

15

15

15

JNFU

Jump No Floating

Jump to U if 021 =0; go to NI if 021 = 1.

(a=1)

Underflow

clear 021

JNFO

Jump No Floating

Jump to U if 022=0; go to NI if 022= 1;

(8=2)

Overflow

clear 022

JNOF

Jump No Divide Fault

Jump to U if 023=0; go to NI if 023= 1;

(8=3)

200/300

200/300

clear 023

I
74

16

JC

Jump Carry

Jump to U if 00= 1; go to NI if 00=0

200/300

74

17

JNC

Jump No Carry

Jump to U if 00=0; go to NI if 00= 1

200/300

75

00

-

Invalid Code

Causes IOU to return a condition code of 3 to

-

the CPU indicating instruction not available
75

01

SIOF

Start I/O Fast Release

(U.U+ 1) -

CAW; initiate operation defined in

1150

CCW at address (CAW)S9_36 on device
spe,cifiedby (CAW)'6-00

179

Mnemonic

function
Code
(Octal)

Instruction

Description

Instruction
Time (in
ns)

j

f
75

02

-

.nvalid Code

Causes IOU to return a condition code of 3 to
the CPU indicating instruction not available

-

75

03

TSC

Tesl Subchannel

(U,U+ 1) -

1150

CAW; interrogate subchannel

specified by (CAW)15-O
75

04

HDV

Halt Device

(U,U+ 1) - CAW; terminate current operation
on subchannel and device specified by

1150

(CAW)15-O
75

05

HCH

Halt Channel

(U,U+ 1) -

CAW; terminate current operation

1150

on channel specified by (CAW)'5-O
75

06,07

-

75

10

lCR

75

11

LTCW

Invalid Code

Causes Invalid Instruction interrupt to address
221 8

1150

Load Channel

(U,U+ 1) - CAW; if (CAW)o=O, (CAW)50-36
- CBR; if (CAW)o= 1, (CAW)71_36 - interrupt
mask register

1150

Register

Load Table Control

(U,U+ 1) -

1150

Words

CAW; load HCAW and HSTCW in
channel specified by (CAW hs_8; (CAW)59_36
- HCAW; STCW at address specified by
(CAW)S9_38 -

HSTCW

75

12-17

-

Invalid Code

Causes Invalid Instruction interrupt to address
221 8

1150

76

00

FA

Floating Add

(A.)+(U) -

A.; RESIDUE -

A. + 1 if 017 = 1

800/1050

76

01

FAN

Floating Add

(A.)-(U) -

A.; RESIDUE- A.+1 if 017=1

800/1050

Negative
76

02

FM

Floating Multiply

(A.)'(U) -

A.(and A.+1 if 017=1)

1350 +
100b

76

03

FD

Floating Divide

(A.Ii (U) 017= 1

A.; REMAINDER -

48001

76

04

LUF

b .. Number of arithmetic loops

180

Load and Unpack
Floating

1 ,U) 134 - 27

A.+ 1 if

4850
-

28-0' sign fill

A. 7-O,zero fill; (U)26-O -

A.+1

300

Function :LnoniC

Instruction

Description

Code
(Octal)

j

f
76

Instruction
Time (in
ns)

05

LCF

Load and Convert
to Floating

(U)35 -

A. + 135 , [NORMALIZED
(U)]u-o - A.+ 126-0; if (U)35=0,
(A.)7-o± NORMALIZING COUNT] A.+ 134 - 27 ; if (U)35-1, ones complement
of [(A.)7-O ± NORMALIZING COUNT] -

550

A.+ 134 - 27
76

06

MCDU

Magnitude of
Characteristic

I

(A.) 136 - 27- 1 (U) 135- 27 1
ZEROS - A. + 135 _9

-

(A. + 1)8-0

350

1 (A.) 136 - 27 - 1 (U) 136 - 27

-

A. + 18-0; SIGN BITS

350

Difference to Upper
76

07

CDU

76

10

DFA

76

11

DFAN

Characteristic
Difference to Upper

-

A.+ 135- 9

Double Precision
Floating Add

(A., A.+ 1) + (U, U+ 1) -

Double Precision

(A., A.+ 1) - (U, U+ 1) -

A., A.+ 1

A., A.+ 1

950

950

Floating Add
Negative
76

12

DFM

Double Precision

(A., A.+ 1)' (U, U+ 1) -

A., A.+ 1

2450

A., A.+ 1

9850

Floating Multiply
76

13

DFD

Double Precision
Floating Divide

(A., A.+ 1r.(U, U+ 1) -

76

14

DFU

Double Load and
Unpack Floating

1 (U,U + 1)70-50 1 A. 10-0, zero fill;
(U,U+ 1)59-38 - A. + 123-0' sign fill;
(U,U+ 1)36-0 - A.+2

850

76

15

DLCF, [.FP

Double Load and
Convert to Floating

(U)35 -

700/1100

A. + 135 ; [NORMALIZED
(U, U+ 1)]59-0 - A.+ 123-0 and
A.+2; If (U)36=0, (A.),a-o±
NORMALIZING COUNT A. + 134 - 24 : If (U)35 = 1, ones
complement of [(A.)'0-0 ± NORMALIZING
COUNT] - A.+ 134- 24 (see Note 10)

76

16

FEL

Floating Expand
and Load

(Ui 26_3 -

A. 23-O; (U)2-O -

A. + 136 - 33 ;

450

181

Function
Code
(Octal)

Mnemonic

Instruction

Description

j

f

(U)35 16008 , 600 8 76

17

FCL

Floating Compress
and Load

182

0-17

-

Invalid Code

A. + 132-0; If (U)35 - 0, (U)36-27 +
Ae36- 24 ; If (U)35 - 1, (U)35-27 Ae36- 24

(U)23-O - A. 28-3; (U+ 1)36-33- A. 2-o
if (U)35.0 (U)36-24 + 16008
- A. 36 _27 if (lJ)36 -1, (U)36-24 + 16008

A. 36- 27
77

Instruction
Time (in
ns)

700

-

Causes Invalid Instruction interrupt to address
221 8

1150

NOTES:
1.

The timing estimlltions use only whole word stores with the exception of the byte instructions which must use panial
stores.

2.

3.

Repeated instruction times can be estimated by these formulas:

+ number of repeats (K

8.

Total time - set up

or N) x basic time.

b.

Edit in the byte instruction is estimated by N,

=:

skip count. N2

=:

number of control bytes.

Instruc:tion set up times are special sequences to condition the control for repeated sequences and are added to the
total tiime required for the repeated instruction.

4.

Test or skip instruction times are stated as xxx/yyy. The first number is th~_!~'!.!.!..!o!..~kip not .~.~~~~ the second is for
skip tltken .
.....

--._--

5.

Condi1tional jump times are stated as xxx/yyy. The first ~~~~! is time for jump not taken, the second for. jump taken.

6.

Byte instruction times are, in general, data dependent as well as string length dependent; therefore, times given
repres.ent a given set of data but could change for different data.

7.
8.

For the 37-06, 07 (Byte Add and Add Negative) instructions, the greater time applies if a refetch is required.
For th·e 72-15 (Test Relative Address) instruction, the lesser time applies if the address tested is within the first pair
of limlits used in the test.

9.

For thle 73-15 (LI)ad Breakpoint) instruction, the greater time applies when bit 29 of the operand specifies clear jump
histonf stack.

, O.

For this 76-15 (Double Load and Conven to Floating) instruction, the greater time applies when 020= 1 (no instruction
overlap).

11.

The times given for the I/O instructions are processor times. Add 200 ns if skip, and wait-time for IOU to respond.

183



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