UM10114 LPC21xx And LPC22xx User Manual LPC 21xx
User Manual:
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- Chapter 1: Introductory information
- Chapter 2: LPC21xx/22xx Memory map
- Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM)
- Chapter 4: LPC21xx/22xx External Memory Controller (EMC)
- Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC)
- 5.1 How to read this chapter
- 5.2 Features
- 5.3 Description
- 5.4 Register description
- 5.5 VIC registers
- 5.5.1 Software Interrupt register (VICSoftInt - 0xFFFF F018)
- 5.5.2 Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)
- 5.5.3 Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)
- 5.5.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)
- 5.5.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)
- 5.5.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)
- 5.5.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000)
- 5.5.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004)
- 5.5.9 Vector Control registers 0-15 (VICvectCntl0-15 - 0xFFFF F200-23C)
- 5.5.10 Vector Address registers 0-15 (VICVectAddr0-15 - 0xFFFF F100-13C)
- 5.5.11 Default Vector Address register (VICDefVectAddr - 0xFFFF F034)
- 5.5.12 Vector Address register (VICVectAddr - 0xFFFF F030)
- 5.5.13 Protection Enable register (VICProtection - 0xFFFF F020)
- 5.6 Interrupt sources
- 5.7 Spurious interrupts
- 5.8 VIC usage notes
- Chapter 6: LPC21xx/22xx System control
- 6.1 How to read this chapter
- 6.2 Summary of system control block functions
- 6.3 Pin description
- 6.4 Register description
- 6.5 Crystal oscillator
- 6.6 External interrupt inputs
- 6.6.1 Register description
- 6.6.2 External Interrupt Flag register (EXTINT - 0xE01F C140)
- 6.6.3 External interrupt Wake-up register (EXTWAKE - 0xE01F C144)
- 6.6.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)
- 6.6.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
- 6.6.6 Multiple external interrupt pins
- 6.7 Other system controls
- 6.8 Memory mapping control
- 6.9 Phase Locked Loop (PLL)
- 6.9.1 Register description
- 6.9.2 PLL Control register (PLLCON - 0xE01F C080)
- 6.9.3 PLL Configuration register (PLLCFG - 0xE01F C084)
- 6.9.4 PLL Status register (PLLSTAT - 0xE01F C088)
- 6.9.5 PLL Interrupt
- 6.9.6 PLL Modes
- 6.9.7 PLL Feed register (PLLFEED - 0xE01F C08C)
- 6.9.8 PLL and Power-down mode
- 6.9.9 PLL frequency calculation
- 6.9.10 Procedure for determining PLL settings
- 6.9.11 PLL configuring examples
- 6.10 Power control
- 6.11 Reset
- 6.12 APB divider
- 6.13 Wakeup timer
- 6.14 Code security vs. debugging
- Chapter 7: LPC21xx/22xx Pin configuration
- Chapter 8: LPC21xx/22xx Pin connect block
- Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller
- 9.1 How to read this chapter
- 9.2 Features
- 9.3 Applications
- 9.4 Pin description
- 9.5 Register description
- 9.5.1 GPIO port Direction register IODIR (IO0DIR - 0xE002 8008, IO1DIR - 0xE002 8018, IO2DIR - 0xE002 8028, IO3DIR - 0xE002 8038, FIO0DIR - 0x3FFF C000, FIO1DIR - 0x3FFF C020)
- 9.5.2 GPIO port output Set register IOSET (IO0SET - 0xE002 8004, IO1SET - 0xE002 8014, IO2SET - 0xE002 8024, IO3SET - 0xE002 8034, FIO0SET - 0x3FFF C018, FIO1SET - 0x3FFF C038)
- 9.5.3 GPIO port output Clear register IOCLR (IO0CLR - 0xE002 800C, IO1CLR - 0xE002 801C, IO2CLR - 0xE002 802C, IO3CLR - 0xE002 803C, FIO0CLR - 0x3FFF C01C, FIO1CLR - 0x3FFF C03C)
- 9.5.4 GPIO port Pin value register IOPIN (IO0PIN - 0xE002 8000, IO1PIN - 0xE002 8010, IO2PIN - 0xE002 8020, IO3PIN - 0xE002 8030, FIO0PIN - 0x3FFF C014, FIO1PIN - 0x3FFF C034)
- 9.5.5 Fast GPIO port Mask register FIOMASK(FIO0MASK - 0x3FFF C010, FIO1MASK - 0x3FFF C030)
- 9.6 GPIO usage notes
- Chapter 10: LPC21xx/22xx Universal Asynchronous Receiver/Transmitter 0 (UART0)
- 10.1 How to read this chapter
- 10.2 Features
- 10.3 Pin description
- 10.4 Register description
- 10.4.1 UART0 Receiver Buffer register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only)
- 10.4.2 UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB = 0, Write Only)
- 10.4.3 UART0 Divisor Latch registers (U0DLL - 0xE000 C000 and U0DLM - 0xE000 C004, when DLAB = 1)
- 10.4.4 UART0 Fractional Divider Register (U0FDR - 0xE000 C028)
- 10.4.5 UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when DLAB = 0)
- 10.4.6 UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only)
- 10.4.7 UART0 FIFO Control Register (U0FCR - 0xE000 C008)
- 10.4.8 UART0 Line Control Register (U0LCR - 0xE000 C00C)
- 10.4.9 UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only)
- 10.4.10 UART0 Scratch Pad Register (U0SCR - 0xE000 C01C)
- 10.4.11 UART0 Auto-baud Control Register (U0ACR - 0xE000 C020)
- 10.4.12 UART0 Transmit Enable Register (U0TER - 0xE000 C030)
- 10.5 Architecture
- Chapter 11: LPC21xx/22xx Universal Asynchronous Receiver/Transmitter 1 (UART1)
- 11.1 How to read this chapter
- 11.2 Features
- 11.3 Pin description
- 11.4 Register description
- 11.4.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only)
- 11.4.2 UART1 Transmitter Holding Register (U1THR - 0xE001 0000, when DLAB = 0 Write Only)
- 11.4.3 UART1 Divisor Latch registers 0 and 1 (U1DLL - 0xE001 0000 and U1DLM - 0xE001 0004, when DLAB = 1)
- 11.4.4 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)
- 11.4.5 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when DLAB = 0)
- 11.4.6 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)
- 11.4.7 UART1 FIFO Control Register (U1FCR - 0xE001 0008)
- 11.4.8 UART1 Line Control Register (U1LCR - 0xE001 000C)
- 11.4.9 UART1 Modem Control Register (U1MCR - 0xE001 0010)
- 11.4.10 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)
- 11.4.11 UART1 Modem Status Register (U1MSR - 0xE001 0018)
- 11.4.12 UART1 Scratch Pad Register (U1SCR - 0xE001 001C)
- 11.4.13 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020)
- 11.4.14 Auto-baud
- 11.4.15 Auto-baud modes
- 11.4.16 UART1 Transmit Enable Register (U1TER - 0xE001 0030)
- 11.5 Architecture
- Chapter 12: LPC21xx/22xx I2C interface
- 12.1 How to read this chapter
- 12.2 Features
- 12.3 Applications
- 12.4 Description
- 12.5 Pin description
- 12.6 I2C operating modes
- 12.7 I2C Implementation and operation
- 12.8 Register description
- 12.8.1 I2C Control Set register (I2CONSET - 0xE001 C000)
- 12.8.2 I2C Control Clear register (I2CONCLR - 0xE001 C018)
- 12.8.3 I2C Status register (I2STAT - 0xE001 C004)
- 12.8.4 I2C Data register (I2DAT - 0xE001 C008)
- 12.8.5 I2C Slave Address register (I2ADR - 0xE001 C00C)
- 12.8.6 I2C SCL High duty cycle register (I2SCLH - 0xE001 C010)
- 12.8.7 I2C SCL Low duty cycle register (I2SCLL - 0xE001 C014)
- 12.8.8 Selecting the appropriate I2C data rate and duty cycle
- 12.9 Details of I2C operating modes
- 12.9.1 Master Transmitter mode
- 12.9.2 Master Receiver mode
- 12.9.3 Slave Receiver mode
- 12.9.4 Slave Transmitter mode
- 12.9.5 Miscellaneous States
- 12.9.6 I2STAT = 0xF8
- 12.9.7 I2STAT = 0x00
- 12.9.8 Some special cases
- 12.9.9 Simultaneous repeated START conditions from two masters
- 12.9.10 Data transfer after loss of arbitration
- 12.9.11 Forced access to the I2C-bus
- 12.9.12 I2C-bus obstructed by a low level on SCL or SDA
- 12.9.13 Bus error
- 12.9.14 I2C State service routines
- 12.9.15 Initialization
- 12.9.16 I2C interrupt service
- 12.9.17 The State service routines
- 12.9.18 Adapting State services to an application
- 12.10 Software example
- 12.10.1 Initialization routine
- 12.10.2 Start Master Transmit function
- 12.10.3 Start Master Receive function
- 12.10.4 I2C interrupt routine
- 12.10.5 Non mode specific States
- 12.10.6 State: 0x00
- 12.10.7 Master States
- 12.10.8 State: 0x08
- 12.10.9 State: 0x10
- 12.10.10 Master Transmitter States
- 12.10.11 State: 0x18
- 12.10.12 State: 0x20
- 12.10.13 State: 0x28
- 12.10.14 State: 0x30
- 12.10.15 State: 0x38
- 12.10.16 Master Receive States
- 12.10.17 State: 0x40
- 12.10.18 State: 0x48
- 12.10.19 State: 0x50
- 12.10.20 State: 0x58
- 12.10.21 Slave Receiver States
- 12.10.22 State: 0x60
- 12.10.23 State: 0x68
- 12.10.24 State: 0x70
- 12.10.25 State: 0x78
- 12.10.26 State: 0x80
- 12.10.27 State: 0x88
- 12.10.28 State: 0x90
- 12.10.29 State: 0x98
- 12.10.30 State: 0xA0
- 12.10.31 Slave Transmitter States
- 12.10.32 State: 0xA8
- 12.10.33 State: 0xB0
- 12.10.34 State: 0xB8
- 12.10.35 State: 0xC0
- 12.10.36 State: 0xC8
- Chapter 13: LPC21xx/22xx SPI
- 13.1 How to read this chapter
- 13.2 Features
- 13.3 Description
- 13.4 Pin description
- 13.5 Register description
- 13.5.1 SPI Control Register (S0SPCR - 0xE002 0000 and S1SPCR - 0xE003 0000)
- 13.5.2 SPI Status Register (S0SPSR - 0xE002 0004 and S1SPSR - 0xE003 0004)
- 13.5.3 SPI Data Register (S0SPDR - 0xE002 0008, S1SPDR - 0xE003 0008)
- 13.5.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C and S1SPCCR - 0xE003 000C)
- 13.5.5 SPI Interrupt Register (S0SPINT - 0xE002 001C and S1SPINT - 0xE003 001C)
- 13.6 Architecture
- Chapter 14: LPC21xx/22xx SSP interface
- 14.1 How to read this chapter
- 14.2 Features
- 14.3 Description
- 14.4 Bus description
- 14.5 Register description
- 14.5.1 SSP Control Register 0 (SSPCR0 - 0xE005 C000)
- 14.5.2 SSP Control Register 1 (SSPCR1 - 0xE005 C004)
- 14.5.3 SSP Data Register (SSPDR - 0xE005 C008)
- 14.5.4 SSP Status Register (SSPSR - 0xE005 C00C)
- 14.5.5 SSP Clock Prescale Register (SSPCPSR - 0xE005 C010)
- 14.5.6 SSP Interrupt Mask Set/Clear Register (SSPIMSC - 0xE005 C014)
- 14.5.7 SSP Raw Interrupt Status Register (SSPRIS - 0xE005 C018)
- 14.5.8 SSP Masked Interrupt Register (SSPMIS - 0xE005 C01C)
- 14.5.9 SSP Interrupt Clear Register (SSPICR - 0xE005 C020)
- Chapter 15: LPC21xx/22xx Timer 0/1
- 15.1 How to read this chapter
- 15.2 Features
- 15.3 Applications
- 15.4 Description
- 15.5 Pin description
- 15.6 Register description
- 15.6.1 Interrupt Register (IR, TIMER0: T0IR - 0xE000 4000 and TIMER1: T1IR - 0xE000 8000)
- 15.6.2 Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and TIMER1: T1TCR - 0xE000 8004)
- 15.6.3 Count Control Register (CTCR, TIMER0: T0CTCR - 0xE000 4070 and TIMER1: T1CTCR - 0xE000 8070)
- 15.6.4 Timer Counter (TC, TIMER0: T0TC - 0xE000 4008 and TIMER1: T1TC - 0xE000 8008)
- 15.6.5 Prescale Register (PR, TIMER0: T0PR - 0xE000 400C and TIMER1: T1PR - 0xE000 800C)
- 15.6.6 Prescale Counter Register (PC, TIMER0: T0PC - 0xE000 4010 and TIMER1: T1PC - 0xE000 8010)
- 15.6.7 Match Registers (MR0 - MR3)
- 15.6.8 Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 and TIMER1: T1MCR - 0xE000 8014)
- 15.6.9 Capture Registers (CR0 - CR3)
- 15.6.10 Capture Control Register (CCR, TIMER0: T0CCR - 0xE000 4028 and TIMER1: T1CCR - 0xE000 8028)
- 15.6.11 External Match Register (EMR, TIMER0: T0EMR - 0xE000 403C; and TIMER1: T1EMR - 0xE000 803C)
- 15.7 Example timer operation
- 15.8 Architecture
- Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM)
- 16.1 How to read this chapter
- 16.2 Features
- 16.3 Description
- 16.4 Pin description
- 16.5 Register description
- 16.5.1 PWM Interrupt Register (PWMIR - 0xE001 4000)
- 16.5.2 PWM Timer Control Register (PWMTCR - 0xE001 4004)
- 16.5.3 PWM Timer Counter (PWMTC - 0xE001 4008)
- 16.5.4 PWM Prescale Register (PWMPR - 0xE001 400C)
- 16.5.5 PWM Prescale Counter Register (PWMPC - 0xE001 4010)
- 16.5.6 PWM Match Registers (PWMMR0 - PWMMR6)
- 16.5.7 PWM Match Control Register (PWMMCR - 0xE001 4014)
- 16.5.8 PWM Control Register (PWMPCR - 0xE001 404C)
- 16.5.9 PWM Latch Enable Register (PWMLER - 0xE001 4050)
- Chapter 17: LPC21xx/22xx WatchDog Timer (WDT)
- Chapter 18: LPC21xx/22xx Real-Time Clock (RTC)
- 18.1 How to read this chapter
- 18.2 Features
- 18.3 Description
- 18.4 Architecture
- 18.5 Register description
- 18.5.1 RTC interrupts
- 18.5.2 Miscellaneous register group
- 18.5.3 Interrupt Location Register (ILR - 0xE002 4000)
- 18.5.4 Clock Tick Counter Register (CTCR - 0xE002 4004)
- 18.5.5 Clock Control Register (CCR - 0xE002 4008)
- 18.5.6 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
- 18.5.7 Alarm Mask Register (AMR - 0xE002 4010)
- 18.5.8 Consolidated time registers
- 18.5.9 Consolidated Time register 0 (CTIME0 - 0xE002 4014)
- 18.5.10 Consolidated Time register 1 (CTIME1 - 0xE002 4018)
- 18.5.11 Consolidated Time register 2 (CTIME2 - 0xE002 401C)
- 18.5.12 Time counter group
- 18.5.13 Leap year calculation
- 18.5.14 Alarm register group
- 18.6 RTC usage notes
- 18.7 Reference clock divider (prescaler)
- Chapter 19: LPC21xx/22xx CAN controller and acceptance filter
- 19.1 How to read this chapter
- 19.2 CAN controllers
- 19.3 Features
- 19.4 Pin description
- 19.5 Memory map of the CAN block
- 19.6 CAN controller registers
- 19.6.1 Mode Register (MOD: CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000, CAN3MOD - 0x004 C000, CAN4MOD - 0x005 0000)
- 19.6.2 Command Register (CMR: CAN1CMR- 0xE004 4004, CAN2CMR - 0xE004 8004, CAN3CMR - 0x004 C004, CAN4CMR - 0x005 0004)
- 19.6.3 Global Status Register (GSR: CAN1GSR - 0xE004 0008, CAN2GSR - 0xE004 8008, CAN3GSR - 0xE004 C008, CAN4GSR 0xE005 0008)
- 19.6.4 Interrupt and Capture Register (ICR: CAN1ICR- 0xE004 400C, CAN2ICR - 0xE004 800C, CAN3ICR - 0xE004 C00C, CAN4ICR - 0xE005 000C)
- 19.6.5 Interrupt Enable Register (IER: CAN1IER - 0xE004 4010, CAN2IER 0xE004 8010, CAN3IER - 0xE004 C010, CAN4IER - 0xE005 0010)
- 19.6.6 Bus Timing Register (BTR: CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014, CAN3BTR - 0xE004 C014, CAN4BTR - 0xE005 0014)
- 19.6.7 Error Warning Limit Register (EWL: CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018, CAN3EWL - 0xE004 C018, CAN4EWL - 0xE005 0018)
- 19.6.8 Status Register (SR - CAN1SR 0xE004 401C, CAN2SR - 0xE004 801C, CAN3SR - 0xE004 C01C, CAN4SR - 0xE005 001C)
- 19.6.9 Receive Frame Status register (RFS - CAN1RFS - 0xE004 4020, CAN2RFS - 0xE004 8020, CAN3RFS - 0xE004 C020, CAN4RFS - 0xE005 0020)
- 19.6.10 Receive Identifier register (RID - CAN1RID - 0xE004 4024, CAN2RID - 0xE004 8024, CAN3RID - 0xE004 C024, CAN4RID - 0xE005 0024)
- 19.6.11 Receive Data register A (RDA: CAN1RDA - 0xE004 4028, CAN2RDA - 0xE004 8028, CAN3RDA - 0xE004 C028, CAN4RDA - 0xE005 0028)
- 19.6.12 Receive Data register B (RDB: CAN1RDB - 0xE004 402C, CAN2RDB - 0xE004 802C, CAN3RDB - 0xE004 C02C, CAN4RDB - 0xE005 002C)
- 19.6.13 Transmit Frame Information register (TFI1, 2, 3 - CAN1TF1n - 0xE004 4030, 40, 50; CAN2TFIn - 0xE004 8030, 40, 50; CAN3TFIn - 0xE004 C030, 40, 50; CAN4TFIn - 0xE005 0030, 40, 50)
- 19.6.14 Transmit Identifier register (TID1, 2, 3 - CAN1TIDn - 0xE004 4034, 44, 54; CAN2TIDn - 0xE004 8034, 44, 54; CAN3TIDn - 0xE004 C034, 44, 54; CAN4TIDn - 0xE005 0034, 44, 54)
- 19.6.15 Transmit Data register A (TDA1, 2, 3: CAN1TDAn - 0xE004 4038, 48, 58; CAN2TDAn - 0xE004 8038, 48, 58; CAN3TDAn - 0xE004 C038, 48, 58; CAN4TDAn - 0xE005 0038, 48, 58)
- 19.6.16 Transmit Data Register B (TDB1, 2, 3: CAN1TDBn - 0xE004 403C, 4C, 5C; CAN2TDBn - 0xE004 803C, 4C, 5C; CAN3TDBn - 0xE004 C03C, 4C, 5C; CAN4TDBn - 0xE005 003C, 4C, 5C)
- 19.7 CAN controller operation
- 19.8 Centralized CAN registers
- 19.9 Global acceptance filter
- 19.10 Acceptance filter registers
- 19.10.1 Acceptance Filter Mode Register (AFMR - 0xE003 C000)
- 19.10.2 Standard Frame Individual Start Address register (SFF_sa - 0xE003 C004)
- 19.10.3 Standard Frame Group Start Address Register (SFF_GRP_sa - 0xE003 C008)
- 19.10.4 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C)
- 19.10.5 Extended Frame Group Start Address Register (EFF_GRP_sa - 0xE003 C010)
- 19.10.6 End of AF Tables register (ENDofTable - 0xE003 C014)
- 19.10.7 LUT Error Address register (LUTerrAd - 0xE003 C018)
- 19.10.8 LUT Error register (LUTerr - 0xE003 C01C)
- 19.10.9 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020)
- 19.10.10 FullCAN Interrupt and Capture registers (FCANIC0 - 0xE003 C024 and FCANIC1 - 0xE003 C028)
- 19.11 Examples of acceptance filter tables and ID index values
- 19.12 Fullcan mode
- Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC)
- Chapter 21: LPC21xx/22xx Flash memory controller
- 21.1 How to read this chapter
- 21.2 Flash boot loader
- 21.3 Features
- 21.4 Applications
- 21.5 Description
- 21.5.1 Memory map after any reset
- 21.5.2 Criterion for valid user code
- 21.5.3 Communication protocol
- 21.5.4 ISP command format
- 21.5.5 ISP response format
- 21.5.6 ISP data format
- 21.5.7 ISP flow control
- 21.5.8 ISP command abort
- 21.5.9 Interrupts during ISP
- 21.5.10 Interrupts during IAP
- 21.5.11 RAM used by ISP command handler
- 21.5.12 RAM used by IAP command handler
- 21.5.13 RAM used by RealMonitor
- 21.5.14 Boot process flowchart
- 21.6 Sector numbers
- 21.7 Flash content protection mechanism
- 21.8 Code Read Protection (CRP)
- 21.9 ISP commands
- 21.9.1 Unlock <unlock code>
- 21.9.2 Set Baud Rate <baud rate> <stop bit>
- 21.9.3 Echo <setting>
- 21.9.4 Write to RAM <start address> <number of bytes>
- 21.9.5 Read memory <address> <no. of bytes>
- 21.9.6 Prepare sector(s) for write operation <start sector number> <end sector number>
- 21.9.7 Copy RAM to Flash <Flash address> <RAM address> <no of bytes>
- 21.9.8 Go <address> <mode>
- 21.9.9 Erase sector(s) <start sector number> <end sector number>
- 21.9.10 Blank check sector(s) <sector number> <end sector number>
- 21.9.11 Read Part Identification number
- 21.9.12 Read Boot code version number
- 21.9.13 Compare <address1> <address2> <no of bytes>
- 21.9.14 ISP Return codes
- 21.10 IAP commands
- 21.11 JTAG Flash programming interface
- Chapter 22: LPC21xx/22xx On-chip serial boot loader for LPC2210/20/90
- 22.1 How to read this chapter
- 22.2 Description
- 22.3 Memory map after reset
- 22.4 Communication protocol
- 22.5 ISP command format
- 22.6 ISP response format
- 22.7 ISP data format
- 22.8 ISP flow control
- 22.9 ISP command abort
- 22.10 Interrupts during ISP
- 22.11 Interrupts during IAP
- 22.12 RAM used by ISP command handler
- 22.13 RAM used by IAP command handler
- 22.14 RAM used by RealMonitor
- 22.15 Boot process flowchart
- 22.16 ISP commands
- 22.16.1 Unlock <Unlock code>
- 22.16.2 Set Baud Rate <Baud Rate> <stop bit>
- 22.16.3 Echo <setting>
- 22.16.4 Write to RAM <start address> <number of bytes>
- 22.16.5 Read Memory <address> <number of bytes>
- 22.16.6 Go <address> <Mode>
- 22.16.7 Read Part ID
- 22.16.8 Read Boot code version
- 22.16.9 Compare <address1> <address2> <number of bytes>
- 22.16.10 ISP Return Codes Summary
- 22.17 IAP Commands
- 22.18 JTAG external memory programming interface
- Chapter 23: LPC21xx/22xx Embedded ICE controller
- Chapter 24: LPC21xx/22xx Embedded Trace Module (ETM)
- Chapter 25: LPC21xx/22xx RealMonitor
- Chapter 26: Supplementary information