Book.B V2300A_PG1 V2300A PG1

V2300A_PG1 V2300A_PG1

User Manual: V2300A_PG1

Open the PDF directly: View PDF .
Page Count: 292

Download
Open PDF In Browser	View PDF

MVME2300-Series
VME Processor Module
Programmer’s
Reference Guide
V2300A/PG1

Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document,
or from the use of the information obtained therein. Motorola reserves the right to
revise this document and to make changes from time to time in the content hereof
without obligation of Motorola to notify any person of such revision or changes.
No part of this material may be reproduced or copied in any tangible medium, or
stored in a retrieval system, or transmitted in any form, or by any means, radio,
electronic, mechanical, photocopying, recording or facsimile, or otherwise,
without the prior written permission of Motorola, Inc.
It is possible that this publication may contain reference to, or information about
Motorola products (machines and programs), programming, or services that are
not announced in your country. Such references or information must not be
construed to mean that Motorola intends to announce such Motorola products,
programming, or services in your country.

Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in
writing by Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set
forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer
Software clause at DFARS 252.227-7013.
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

Preface
The MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide
provides brief board level information, complete memory maps, and detailed
ASIC chip information including register bit descriptions for the MVME2300 series
VME Processor Modules (also called MVME230x in this manual). The information
contained in this manual applies to the single board computers built from some of
the plug-together components listed in the following table.
Model
MVME2301
MVME2302

MPC
MPC603
@ 200 MHz

MVME2303

MVME2306

16MB ECC DRAM
32MB ECC DRAM
64MB ECC DRAM

MVME2304
MVME2305

Memory

128MB ECC DRAM
MPC604
@ 300 MHz

16MB ECC DRAM
32MB ECC DRAM

MVME2307

64MB ECC DRAM

MVME2308

128MB ECC DRAM

This manual is intended for anyone who wants to program these boards in order to
design OEM systems, supply additional capability to an existing compatible
system, or work in a lab environment for experimental purposes.
A basic knowledge of computers and digital logic is assumed.
To use this manual, you should be familiar with the publications listed in Appendix
A, Related Documentation.
The following conventions are used in this document:
bold
is used for user input that you type just as it appears. Bold is also used for
commands, options and arguments to commands, and names of programs,
directories, and files.
italic
is used for names of variables to which you assign values. Italic is also used
for comments in screen displays and examples.
courier

is used for system output (e.g., screen displays, reports), examples, and
system prompts.
or
represents the carriage return or enter key.

CTRL
represents the Control key. Execute control characters by pressing the
CTRL key and the letter simultaneously, e.g., CTRL-d.
The computer programs stored in the Read Only Memory of this device contain
material copyrighted by Motorola Inc., Þrst published 1990, and may be used only
under a license such as the License for Computer Programs (Article 14) contained
in Motorola's Terms and Conditions of Sale, Rev. 1/79.
All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized
manufacturers, with a ßammability rating of 94V-0.

!
WARNING

This equipment generates, uses, and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used in a
cabinet with adequate EMI protection.

Motorola¨ and the Motorola symbol are registered trademarks of Motorola, Inc.
PowerStackTM, VMEmoduleTM, and VMEsystemTM are trademarks of Motorola,
Inc.
PowerPCTM, PowerPC 603TM, and PowerPC 604TMare trademarks of IBM Corp,
and are used by Motorola, Inc. under license from IBM Corp.
AIXTM is a trademark of IBM Corp.
TimekeeperTM and ZeropowerTM are trademarks of Thompson Components.
All other products mentioned in this document are trademarks or registered
trademarks of their respective holders.
©Copyright Motorola 1997
All Rights Reserved
Printed in the United States of America
October 1997

Safety Summary
Safety Depends On You
The following general safety precautions must be observed during all phases of operation, service, and
repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in
this manual violates safety standards of design, manufacture, and intended use of the equipment.
Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You,
as the user of the product, should follow these warnings and all other safety precautions necessary for the
safe operation of the equipment in your operating environment.

Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground.
The equipment is supplied with a three-conductor ac power cable. The power cable must be plugged into
an approved three-contact electrical outlet. The power jack and mating plug of the power cable meet
International Electrotechnical Commission (IEC) safety standards.

Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in the presence of ßammable gases or fumes. Operation of any electrical
equipment in such an environment constitutes a deÞnite safety hazard.

Keep Away From Live Circuits.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or
other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or
component replacement or any internal adjustment. Do not replace components with power cable
connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To
avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone.
Do not attempt internal service or adjustment unless another person capable of rendering Þrst aid and
resuscitation is present.

Use Caution When Exposing or Handling the CRT.
Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion).
To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should
be done only by qualiÞed maintenance personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.
Because of the danger of introducing additional hazards, do not install substitute parts or perform any
unauthorized modiÞcation of the equipment. Contact your local Motorola representative for service and
repair to ensure that safety features are maintained.

Dangerous Procedure Warnings.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety
precautions which you deem necessary for the operation of the equipment in your operating environment.

!
WARNING

Dangerous voltages, capable of causing death, are present in
this equipment. Use extreme caution when handling, testing,
and adjusting.

Contents
Introduction 1-1
Manual Terminology 1-1
Overview 1-3
Feature Summary 1-3
System Block Diagram 1-5
Functional Description 1-7
Overview 1-7
Programming Model 1-8
Memory Maps 1-8
Processor Memory Maps 1-8
PCI Memory Maps 1-14
VMEbus Mapping 1-21
Falcon-Controlled System Registers 1-27
System Configuration Register (SYSCR) 1-28
Memory Configuration Register (MEMCR) 1-30
System External Cache Control Register (SXCCR) 1-32
Processor 0 External Cache Control Register (P0XCCR) 1-33
Processor 1 External Cache Control Register (P1XCCR) 1-33
CPU Control Register 1-33
ISA Local Resource Bus 1-34
W83C553 PIB Registers 1-34
16550 UART 1-34
General-Purpose Software-Readable Header (J17) 1-35
NVRAM/RTC & Watchdog Timer Registers 1-36
Module ConÞguration and Status Registers 1-36
CPU Configuration Register 1-37
Base Module Feature Register 1-38
Base Module Status Register (BMSR) 1-39
Seven-Segment Display Register 1-40
VME Registers 1-40
LM/SIG Control Register 1-41
LM/SIG Status Register 1-42
Location Monitor Upper Base Address Register 1-43
Location Monitor Lower Base Address Register 1-44
Semaphore Register 1 1-44
Semaphore Register 2 1-45
VME Geographical Address Register (VGAR) 1-45

Emulated Z8536 CIO Registers and Port Pins 1-46
Emulated Z8536 Registers 1-46
Z8536 CIO Port Pins 1-46
ISA DMA Channels 1-47
Introduction 2-1
Overview 2-1
Features 2-1
Block Diagram 2-3
Functional Description 2-4
Architectural Overview 2-4
MPC Bus Interface 2-4
MPC Address Mapping 2-4
MPC Slave 2-6
MPC Write Posting 2-8
MPC Master 2-8
MPC Arbiter 2-10
MPC Bus Timer 2-10
PCI Interface 2-10
PCI Address Mapping 2-11
PCI Slave 2-14
PCI Write Posting 2-17
PCI Master 2-17
Generating PCI Cycles 2-21
Endian Conversion 2-25
When MPC Devices are Big-Endian 2-25
When MPC Devices are Little Endian 2-26
Raven Registers 2-27
Error Handling 2-28
Transaction Ordering 2-29
Registers 2-31
MPC Registers 2-31
Vendor ID/Device ID Registers 2-33
Revision ID Register 2-33
General Control-Status/Feature Registers 2-34
MPC Arbiter Control Register 2-37
Prescaler Adjust Register 2-37
MPC Error Enable Register 2-38
MPC Error Status Register 2-40
MPC Error Address Register 2-42
MPC Error Attribute Register - MERAT 2-43
PCI Interrupt Acknowledge Register 2-45

MPC Slave Address (0,1 and 2) Registers 2-47
MPC Slave Address (3) Register 2-48
MPC Slave Offset/Attribute (0,1 and 2) Registers 2-49
MPC Slave Offset/Attribute (3) Registers 2-50
General Purpose Registers 2-51
PCI Registers 2-51
Vendor ID/ Device ID Registers 2-53
PCI Command/ Status Registers 2-53
Revision ID/ Class Code Registers 2-55
I/O Base Register 2-56
Memory Base Register 2-57
PCI Slave Address (0,1,2 and 3) Registers 2-58
PCI Slave Attribute/ Offset (0,1,2 and 3) Registers 2-59
CONFIG_ADDRESS Register 2-60
CONFIG_DATA Register 2-63
Raven Interrupt Controller Implementation 2-65
Introduction 2-65
The Raven Interrupt Controller (RavenMPIC) Features 2-65
Architecture 2-65
CSRÕs Readability 2-66
Interrupt Source Priority 2-66
ProcessorÕs Current Task Priority 2-66
Nesting of Interrupt Events 2-66
Spurious Vector Generation 2-67
Interprocessor Interrupts (IPI) 2-67
8259 Compatibility 2-67
Raven-Detected Errors 2-68
Timers 2-68
Interrupt Delivery Modes 2-69
Block Diagram Description 2-70
Program Visible Registers 2-71
Interrupt Pending Register (IPR) 2-71
Interrupt Selector (IS) 2-71
Interrupt Request Register (IRR) 2-72
In-Service Register (ISR) 2-72
Interrupt Router 2-72
MPIC Registers 2-74
RavenMPIC Registers 2-74
Feature Reporting Register 2-79
Global Configuration Register 2-80
Vendor Identification Register 2-81
Processor Init Register 2-81

IPI Vector/Priority Registers 2-82
Spurious Vector Register 2-83
Timer Frequency Register 2-83
Timer Current Count Registers 2-84
Timer Basecount Registers 2-84
Timer Vector/Priority Registers 2-85
Timer Destination Registers 2-86
External Source Vector/Priority Registers 2-87
External Source Destination Registers 2-88
Raven-Detected Errors Vector/Priority Register 2-89
Raven-Detected Errors Destination Register 2-90
Interprocessor Interrupt Dispatch Registers 2-90
Interrupt Task Priority Registers 2-91
Interrupt Acknowledge Registers 2-92
End-of-Interrupt Registers 2-92
Programming Notes 2-93
External Interrupt Service 2-93
Reset State 2-94
Operation 2-95
Interprocessor Interrupts 2-95
Dynamically Changing I/O Interrupt Configuration 2-95
EOI Register 2-96
Interrupt Acknowledge Register 2-96
8259 Mode 2-96
Current Task Priority Level 2-96
Architectural Notes 2-97
Introduction 3-1
Overview 3-1
Bit Ordering Convention 3-1
Features 3-1
Block Diagrams 3-2
Functional Description 3-6
Performance 3-6
Four-beat Reads/Writes 3-6
Single-beat Reads/Writes 3-7
DRAM Speeds 3-7
ROM/Flash Speeds 3-11
PowerPC 60x Bus Interface 3-12
Responding to Address Transfers 3-12
Completing Data Transfers 3-12
Cache Coherency 3-12

Cache Coherency Restrictions 3-13
L2 Cache Support 3-13
ECC 3-13
Cycle Types 3-13
Error Reporting 3-14
Error Logging 3-15
DRAM Tester 3-15
ROM/Flash Interface 3-16
Refresh/Scrub 3-20
Blocks A and/or B Present, Blocks C and D Not Present 3-20
Blocks A and/or B Present, Blocks C and/or D present 3-21
DRAM Arbitration 3-22
Chip Defaults 3-22
External Register Set 3-23
CSR Accesses 3-23
Programming Model 3-24
CSR Architecture 3-24
Register Summary 3-29
Detailed Register Bit Descriptions 3-32
Vendor/Device Register 3-33
Revision ID/ General Control Register 3-33
DRAM Attributes Register 3-35
DRAM Base Register 3-37
CLK Frequency Register 3-37
ECC Control Register 3-38
Error Logger Register 3-42
Error_Address Register 3-45
Scrub/Refresh Register 3-45
Refresh/Scrub Address Register 3-46
ROM A Base/Size Register 3-47
ROM B Base/Size Register 3-50
DRAM Tester Control Registers 3-53
32-Bit Counter 3-53
Test SRAM 3-54
Power-Up Reset Status Register 1 3-55
Power-Up Reset Status Register 2 3-55
External Register Set 3-56
Software Considerations 3-57
Parity Checking on the PowerPC Bus 3-57
Programming ROM/Flash Devices 3-57
Writing to the Control Registers 3-57

Sizing DRAM 3-58
ECC Codes 3-61
Data Paths 3-63
General Information 4-1
Introduction 4-1
Product Overview - Features 4-1
Functional Description 4-2
Architectural Overview 4-2
VMEbus Interface 4-4
PCI Bus Interface 4-5
Interrupter and Interrupt Handler 4-6
DMA Controller 4-7
Registers - Universe Control and Status Registers (UCSR) 4-8
Universe Register Map 4-9
Universe Chip Problems after a PCI Reset 4-14
Problem Description 4-14
Examples 4-16
Example 1: MVME2600 Series Board Exhibits Problem 4-16
Example 2: MVME3600 Series Board Acts Differently 4-17
Example 3: Universe Chip is Checked at Tundra 4-19
Introduction 5-1
PCI Arbitration 5-1
Interrupt Handling 5-2
RavenMPIC 5-3
8259 Interrupts 5-4
ISA DMA Channels 5-7
Exceptions 5-8
Sources of Reset 5-8
Soft Reset 5-9
Universe Chip Problems after a PCI Reset 5-9
Error NotiÞcation and Handling 5-10
Endian Issues 5-11
Processor/Memory Domain 5-14
RavenÕs Involvement 5-14
PCI Domain 5-14
PCI-SCSI 5-14
PCI-Ethernet 5-14
PCI-Graphics 5-15
UniverseÕs Involvement 5-15
VMEbus Domain 5-15
ROM/Flash Initialization 5-16

Motorola Computer Group Documents A-1
ManufacturersÕ Documents A-2
Related SpeciÞcations A-5
Abbreviations, Acronyms, and Terms to Know GL-1

List of Figures
MVME2300 Series System Block Diagram 1-6
VMEbus Master Mapping 1-22
VMEbus Slave Mapping 1-24
General-Purpose Software-Readable Header 1-35
Raven Block Diagram 2-3
MPC to PCI Address Decoding 2-5
MPC to PCI Address Translation 2-6
PCI to MPC Address Decoding 2-12
PCI to MPC Address Translation 2-13
PCI Spread I/O Address Translation 2-22
Big to Little Endian Data Swap 2-26
RavenMPIC Block Diagram 2-70
Falcon Pair Used with DRAM in a System 3-3
Falcon Internal Data Paths (SimpliÞed) 3-4
Overall DRAM Connections 3-5
Data Path for Reads from the Falcon Internal CSRs 3-24
Data Path for Writes to the Falcon Internal CSRs 3-25
Memory Map for Byte Reads to the CSR 3-26
Memory Map for Byte Writes to the Internal Register Set and Test SRAM 3-27
Memory Map for 4-Byte Reads to the CSR 3-28
Memory Map for 4-Byte Writes to the Internal Register Set and Test SRAM 3-28
PowerPC Data to DRAM Data Correspondence 3-64
Architectural Diagram for the Universe 4-3
UCSR Access Mechanisms 4-8
MVME2300 Series Interrupt Architecture 5-2
PIB Interrupt Handler Block Diagram 5-5
Big-Endian Mode 5-12
Little-Endian Mode 5-13

1Board Description and
Memory Maps

Introduction
This manual provides programming information for the
MVME230x VME Processor Modules. Extensive programming
information is provided for several Application-Specific Integrated
Circuit (ASIC) devices used on the boards. Reference information is
included in Appendix A for the Large Scale Integration (LSI)
devices used on the boards and sources for additional information
are listed.
This chapter briefly describes the board level hardware features of
the MVME2300-series VME Processor Modules. The chapter begins
with a board level overview and features list. Memory maps are
next, and are the major feature of this chapter.
Programmable registers in the MVME2300-series that reside in
ASICs are covered in the chapters on those ASICs. Chapter 2 covers
the Raven chip, Chapter 3 covers the Falcon chip set, Chapter 4
covers the Universe chip, and Chapter 5 covers certain
programming features, such as interrupts and exceptions.
Appendix A lists all related documentation.

Manual Terminology
Throughout this manual, a convention is used which precedes data
and address parameters by a character identifying the numeric
format as follows:
$
%
&

dollar
percent
ampersand

speciÞes a hexadecimal character
speciÞes a binary number
speciÞes a decimal number

For example, Ò12Ó is the decimal number twelve, and Ò$12Ó is the
decimal number eighteen.

1-1

Board Description and Memory Maps

Unless otherwise specified, all address references are in
hexadecimal.
An asterisk (*) following the signal name for signals which are level
significant denotes that the signal is true or valid when the signal is
low.
An asterisk (*) following the signal name for signals which are edge
significant denotes that the actions initiated by that signal occur on
high to low transition.
Note

In some places in this document, an underscore (_)
following the signal name is used to indicate an active
low signal.

In this manual, assertion and negation are used to specify forcing a
signal to a particular state. In particular, assertion and assert refer
to a signal that is active or true; negation and negate indicate a
signal that is inactive or false. These terms are used independently
of the voltage level (high or low) that they represent.
Data and address sizes for MPC60x chips are defined as follows:
❏

A byte is eight bits, numbered 0 through 7, with bit 0 being the
least significant.

❏

A half-word is 16 bits, numbered 0 through 15, with bit 0 being
the least significant.

❏

A word or single word is 32 bits, numbered 0 through 31, with
bit 0 being the least significant.

❏

A double word is 64 bits, numbered 0 through 63, with bit 0
being the least significant.

Refer to Chapter 5 for Endian Issues, which covers which parts of the
MVME2300 series use big-endian byte ordering, and which use
small-endian byte ordering.
The terms control bit and status bit are used extensively in this
document. The term control bit is used to describe a bit in a register
that can be set and cleared under software control. The term true is

1-2

Overview

used to indicate that a bit is in the state that enables the function it
controls. The term false is used to indicate that the bit is in the state
that disables the function it controls. In all tables, the terms 0 and 1
are used to describe the actual value that should be written to the
bit, or the value that it yields when read. The term status bit is used
to describe a bit in a register that reflects a specific condition. The
status bit can be read by software to determine operational or
exception conditions.

Overview
The MVME2300-series VME Processor Module family, hereafter
sometimes referred to simply as the MVME230x or the V2300 series,
provides many standard features required by a computer system:
Ethernet interface, async serial port, boot Flash, and up to 128MB of
ECC DRAM.

Feature Summary
There are many models based on the MVME2300 series
architecture. The following table summarizes the major features of
the MVME2300 series:
Table 1-1. MVME230x Features
Feature
Microprocessor
Form factor
ECC DRAM

Description
200 MHZ MPC603 PowerPCTM processor
(MVME2301 - 2304 models)
300 MHZ MPC604 PowerPCTM processor
(MVME2305 - 2308 models)
6U VMEbus
Two-way interleaved, ECC-protected 16MB, 32MB, 64MB, or
128MB

1-3

Board Description and Memory Maps

Table 1-1. MVME230x Features (Continued)
Feature
Flash memory

Real-time clock
Switches
Status LEDs
Timers
Interrupts
VME I/O
Serial I/O
Ethernet I/O

PCI interface

VMEbus interface

1-4

Description
Bank B consists of two 32-pin PLCC sockets that can be populated
with 1MB 8-bit Flash devices
Bank A consists of four 16-bit Smart Voltage SMT devices that can
be populated with 8Mbit Flash devices (4MB) or 4Mbit (2MB)
8KB NVRAM with RTC and battery backup (SGS-Thomson
M48T59/T559)
Reset (RST) and abort (ABT)
Four: Board fail (BFL), CPU, PMC (one for PMC slot 2, one for slot 1)
One 16-bit timer in W83C553 ISA bridge; four 32-bit timers in
Raven (MPIC) device)
Watchdog timer provided in SGS-Thomson M48T59
Software interrupt handling via Raven (PCI-MPU bridge) and
Winbond (PCI-ISA bridge) controllers
VMEbus P2 connector
One asynchronous debug port via RJ45 connector on front panel
10Base-T/100Base-TX connections via RJ45 connector on front
panel
Two IEEE P1386.1 PCI Mezzanine Card (PMC) slots for one
double-width or two single-width PMCs
Front panel and/or VMEbus P2 I/O on both PMC slots
One 114-pin Mictor connector for optional PMCspan expansion
module
VMEbus system controller functions
VME64 extension
VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block
transfer [D8/D16/D32/D64])
Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32)
VMEbus interrupter
VMEbus interrupt handler
Global Control/Status Register (GCSR) for interprocessor
communications
DMA for fast local memory/VMEbus transfers (A16/A24/A32,
D16/D32/D64)

System Block Diagram

System Block Diagram
The MVME2300 series does not provide any look-aside external
cache option. The Falcon chip set controls the boot Flash and the
ECC DRAM. The Raven ASIC functions as the 64-bit PCI host
bridge and the MPIC interrupt controller. PCI devices include:
VME, Ethernet, and two PMC slots. Standard I/O functions are
provided by the UART device which resides on the ISA bus. The
NVRAM/RTC also resides on the ISA bus. The general system
block diagram for MVME2300 series is shown below:

1-5

Board Description and Memory Maps

CLOCK
GENERATOR

DEBUG CONNECTOR

66MHz MPC604 PROCESSOR BUS

DRAM
16/32/64/128MB

PHB & MPIC
RAVEN ASIC

FLASH
3MB or 5MB

SYSTEM
REGISTERS

MEMORY CONTROLLER
FALCON CHIPSET
PCI EXPANSION

PROCESSOR
MPC603/604

64-BIT PMC SLOT

33MHz 32/64-BIT PCI LOCAL BUS

10BT/100BTX

PIB
W83C553

VME BRIDGE
UNIVERSE

ETHERNET
DEC21140

PC16550
UART

BUFFERS

ISA
REGISTERS

FRONT PANEL

ISA BUS

SERIAL
PORT

RTC/NVRAM/WD
MK48T59/559

PMC FRONT I/O SLOT
PMC FRONT I/O SLOT

VME P2

VME P1

2067 9708

Figure 1-1. MVME2300 Series System Block Diagram
1-6

Functional Description

Functional Description
Overview
The MVME2300 series is a family of single-slot VME processor
modules. It consists of the MPC603/604 processor, the Raven PCI
Bridge & Interrupt Controller, the ECC Memory Controller Falcon
chipset, 3MB or 5MB of Flash memory, 16MB to 128MB of ECCprotected DRAM, and a rich set of features of I/O peripherals.
I/O peripheral devices on the PCI bus are: Ethernet chip, Universe
VMEbus interface ASIC, and two PMC slots. Functions provided
from the ISA bus are: one asynchronous serial port, a real-time
clock, counters/timers, and a software-readable header.
The MVME2300 series board interfaces to the VMEbus via the P1
and P2 connectors, which use the new 5-row 160-pin connectors as
specified in the proposed VME64 Extension Standard. It also draws
+5V, +12V, and -12V power from the VMEbus backplane through
these two connectors. 3.3V supply is regulated onboard from the
+5V power.
Front panel connectors on the MVME2300 series board include: an
RJ45 connector for the Ethernet 10Base-T/100Base-TX interface,
and an RJ45 connector for the async serial debug port.
The MVME2300 series contains two IEEE1386.1 PCI Mezzanine
Card (PMC) slots. These PMC slots are 64-bit capable and support
both front and rear I/O. Pins 1 through 64 of PMC slot 1 connector
J14 are routed to row C and row A of the 5-row DIN P2 connector.
Pins 1 through 46 of PMC slot 2 connector J24 are routed to row D
and row Z of P2.
Additional PCI expansion is supported with a 114-pin Mictor
connector. This connection allows stacking of one or two PMCspan
dual-PMC carrier boards, to increase the I/O capability. Each
PMCspan board requires an additional VME slot.

1-7

Board Description and Memory Maps

Programming Model
Memory Maps
The following sections describe the memory maps for the
MVME2300 series.
Processor Memory Maps
The Processor memory map is controlled by the Raven ASIC and
the Falcon chipset. The Raven ASIC and the Falcon chipset have
flexible programming Map Decoder registers to customize the
system to fit many different applications.

1-8

Programming Model

Default Processor Memory Map
After a reset, the Raven ASIC and the Falcon chipset provide the
default processor memory map as shown in the following table.
Table 1-2. Default Processor Memory Map
Size
Start

DeÞnition

End

0000 0000

7FFF FFFF

8000 0000

8001 FFFF

128K

8002 0000

FEF7 FFFF

2G - 16M
- 640K

FEF8 0000

FEF8 FFFF

64K

Falcon Registers

FEF9 0000

FEFE FFFF

384K

Not mapped

FEFF 0000

FEFF FFFF

64K

Raven Registers

FF00 0000

FFEF FFFF

15M

Not mapped

FFF0 0000

FFFF FFFF

ROM/FLASH Bank A or Bank B

Notes

Processor Address

Not mapped
PCI/ISA I/O Space

Not mapped

Notes:
1. This default map for PCI/ISA I/O space allows software to
determine if the system is MPC105-based or Falcon/Ravenbased by examining either the PHB Device ID or the CPU
Type Register.
2. The first one Mbyte of ROM/FLASH Bank A appears at this
range after a reset if the rom_b_rv control bit is cleared. If the
rom_b_rv control bit is set then this address range maps to
ROM/FLASH Bank B.

1-9

Board Description and Memory Maps

Processor CHRP Memory Map
The following table shows a recommended CHRP memory map
from the point of view of the processor.
Table 1-3. CHRP Memory Map Example
Size
Start

DeÞnition

End

Notes

Processor Address

0000 0000

top_dram

dram_size

System Memory (onboard DRAM)

1, 2

4000 0000

FCFF FFFF

3G - 48M

PCI Memory Space:
4000 0000 to FCFF FFFF

3,4,8

FD00 0000

FDFF FFFF

16M

Zero-Based PCI/ISA Memory Space
(mapped to 00000000 to 00FFFFFF)

3,8

FE00 0000

FE7F FFFF

Zero-Based PCI/ISA I/O Space
(mapped to 00000000 to 007FFFFF)

3,5,8

FE80 0000

FEF7 FFFF

7.5M

Reserved

FEF8 0000

FEF8 FFFF

64K

Falcon Registers

FEF9 0000

FEFE FFFF

384K

Reserved

FEFF 0000

FEFF FFFF

64K

Raven Registers

FF00 0000

FF7F FFFF

ROM/FLASH Bank A

1,7

FF80 0000

FF8F FFFF

ROM/FLASH Bank B

1,7

FF50 0000

FFEF FFFF

Reserved

FFF0 0000

FFFF FFFF

ROM/FLASH Bank A or Bank B

Notes:
1. Programmable via Falcon chipset. For the MVME2300 series,
RAM size is limited to 128MB and ROM/FLASH to 4MB.
2. To enable the ÒProcessor-holeÓ area, program the Falcon
chipset to ignore 0x000A0000 - 0x000BFFFF address range
and program the Raven to map this address range to PCI
memory space.

1-10

Programming Model

3. Programmable via Raven ASIC.
4. CHRP requires the starting address for the PCI memory
space to be 256MB-aligned.
5. Programmable via Raven ASIC for either contiguous or
spread-I/O mode.
6. The actual size of each ROM/FLASH bank may vary.
7. The first one Mbyte of ROM/FLASH Bank A appears at this
range after a reset if the rom_b_rv control bit is cleared. If the
rom_b_rv control bit is set then this address range maps to
ROM/FLASH Bank B.
8. This range can be mapped to the VMEbus by programming
the Universe ASIC accordingly. The map shown is the
recommended setting which uses the Special PCI Slave Image
and two of the four programmable PCI Slave Images.
9. The only method to generate a PCI Interrupt Acknowledge
cycle (8259 IACK) is to perform a read access to the RavenÕs
PIACK register at 0xFEFF0030.
The following table shows the programmed values for the associated Raven MPC registers for the processor CHRP memory map.
Table 1-4. Raven MPC Register Values for CHRP Memory Map
Address

FEFF 0040

MSADD0

4000 FCFF

FEFF 0044

MSOFF0 & MSATT0

0000 00C2

FEFF 0048

MSADD1

FD00 FDFF

FEFF 004C

MSOFF1 & MSATT1

0300 00C2

FEFF 0050

MSADD2

0000 0000

FEFF 0054

MSOFF2 & MSATT2

0000 0002

FEFF 0058

MSADD3

FE00 FE7F

FEFF 005C

MSOFF3 & MSATT3

0200 00C0

1-11

Board Description and Memory Maps

Processor PREP Memory Map
The Raven/Falcon chipset can be programmed for PREPcompatible memory map. The following table shows the PREP
memory map of the MVME2300 series from the point of view of the
processor.
Table 1-5. PREP Memory Map Example
Processor Address
Size
Start

DeÞnition

Notes

End

0000 0000

top_dram

dram_size

System Memory (onboard DRAM)

8000 0000

BFFF FFFF

Zero-Based PCI I/O Space:
0000 0000 - 3FFFF FFFF

C000 0000

FCFF FFFF

1G - 48M

FD00 0000

FEF7 FFFF

40.5M

FEF8 0000

FEF8 FFFF

64K

Falcon Registers

FEF9 0000

FEFE FFFF

384K

Reserved

FEFF 0000

FEFF FFFF

64K

Raven Registers

FF00 0000

FF7F FFFF

ROM/FLASH Bank A

1, 3

FF80 0000

FF8F FFFF

ROM/FLASH Bank B

1, 3

FF90 0000

FFEF FFFF

Reserved

FFF0 0000

FFFF FFFF

ROM/FLASH Bank A or Bank B

Zero-Based PCI/ISA Memory Space:
0000 0000 - 3CFFFFFF

2, 5

Reserved

Notes:
1. Programmable via Falcon chipset. For the MVME2300 series,
RAM size is limited to 128MB and ROM/FLASH to 4MB.
2. Programmable via Raven ASIC.
3. The actual size of each ROM/FLASH bank may vary.

1-12

Programming Model

4. The first 1 Mbyte of ROM/FLASH Bank A appears at this
range after a reset if the rom_b_rv control bit is cleared. If the
rom_b_rv control bit is set then this address range maps to
ROM/FLASH Bank B.
5. This range can be mapped to the VMEbus by programming
the Universe ASIC accordingly.
6. The only method to generate a PCI Interrupt Acknowledge
cycle (8259 IACK) is to perform a read access to the RavenÕs
PIACK register at 0xFEFF0030.
The following table shows the programmed values for the
associated Raven MPC registers for the processor PREP memory
map.
Table 1-6. Raven MPC Register Values for PREP Memory Map
Address

FEFF 0040

MSADD0

C000 FCFF

FEFF 0044

MSOFF0 & MSATT0

4000 00C2

FEFF 0048

MSADD1

0000 0000

FEFF 004C

MSOFF1 & MSATT1

0000 0002

FEFF 0050

MSADD2

0000 0000

FEFF 0054

MSOFF2 & MSATT2

0000 0002

FEFF 0058

MSADD3

8000 BFFF

FEFF 005C

MSOFF3 & MSATT3

8000 00C0

PCI ConÞguration Access
PCI Configuration accesses are accomplished via the
CONFIG_ADD and CONFIG_DAT registers. These two registers
are implemented by the Raven ASIC. In the CHRP memory map
example, the CONFIG_ADD and CONFIG_DAT registers are
located at 0xFE000CF8 and 0xFE000CFC, respectively. With the

1-13

Board Description and Memory Maps

PREP memory map, the CONFIG_ADD register and the
CONFIG_DAT register are located at 0x80000CF8 and 0x80000CFC,
respectively.
PCI Memory Maps
The PCI memory map is controlled by the Raven ASIC and the
Universe ASIC. The Raven ASIC and the Universe ASIC have
flexible programming Map Decoder registers to customize the
system to fit many different applications.
Default PCI Memory Map
After a reset, the Raven ASIC and the Universe ASIC turn all the
PCI slave map decoders off. Software must program the
appropriate map decoders for a specific environment.
PCI CHRP Memory Map
The following table shows a PCI memory map of the MVME2300
series that is CHRP-compatible from the point of view of the PCI
local bus.
Table 1-7. PCI CHRP Memory Map
PCI Address
Size
Start

DeÞnition

Notes

End

0000 0000

top_dram

dram_size

Onboard ECC DRAM

4000 0000

EFFF FFFF

3G - 256M

VMEbus A32/D32 (Super/Program)

F000 0000

F7FF FFFF

128M

VMEbus A32/D16 (Super/Program)

F800 0000

F8FE FFFF

16M - 64K

VMEbus A24/D16 (Super/Program)

F8FF 0000

F8FF FFFF

64K

VMEbus A16/D16 (Super/Program)

F900 0000

F9FE FFFF

16M - 64K

VMEbus A24/D32 (Super/Data)

F9FF 0000

F9FF FFFF

64K

VMEbus A16/D32 (Super/Data)

FA00 0000

FAFE FFFF

16M - 64K

VMEbus A24/D16 (User/Program)

1-14

Programming Model

Table 1-7. PCI CHRP Memory Map (Continued)
PCI Address
Size
Start

DeÞnition

Notes

End

FAFF 0000

FAFF FFFF

64K

VMEbus A16/D16 (User/Program)

FB00 0000

FBFE FFFF

16M - 64K

VMEbus A24/D32 (User/Data)

FBFF 0000

FBFF FFFF

64K

VMEbus A16/D32 (User/Data)

FC00 0000

FC03 FFFF

256K

RavenMPIC

FC04 0000

FCFF FFFF

16M - 256K

PCI Memory Space

FD00 0000

FDFF FFFF

16M

PCI Memory Space or
System Memory Alias Space
(mapped to 00000000 to 00FFFFFF)

FE00 0000

FFFF FFFF

48M

Reserved

Notes:
1. Programmable via the RavenÕs PCI Configuration registers.
For the MVME2300 series, RAM size is limited to 128MB.
2. To enabled the CHRP Òio-holeÓ, program the Raven to ignore
the 0x000A0000 - 0x000FFFFF address range.
3. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.
4. Programmable mapping via the Special Slave Image (SLSI) in
the Universe ASIC.

1-15

Board Description and Memory Maps

The following table shows the programmed values for the
associated Raven PCI registers for the PCI CHRP memory map.
Table 1-8. Raven PCI Register Values for CHRP Memory Map
ConÞguration
Address
Offset

ConÞguration
Register Name

$14

RavenMPIC MBASE

FC00 0000

$80

PSADD0

0000 3FFF

0100 3FFF

$84

PSOFF0 & PSATT0

0000 00FX

$88

PSADD1

0000 0000

FD00 FDFF

$8C

PSOFF1 & PSATT1

0000 0000

0000 00FX

$90

PSADD2

0000 0000

$94

PSOFF2 & PSATT2

0000 0000

$98

PSADD3

0000 0000

$9C

PSOFF3 & PSATT3

0000 0000

The next table shows the programmed values for the associated
Universe PCI registers for the PCI CHRP memory map.
Table 1-9. Universe PCI Register Values for CHRP Memory Map
ConÞguration
Address
Offset

1-16

ConÞguration
Register Name

$100

LSI0_CTL

C082 5100

$104

LSI0_BS

4000 0000

$108

LSI0_BD

F000 0000

$10C

LSI0_TO

XXXX 0000

$114

LSI1_CTL

C042 5100

$118

LSI1_BS

F000 0000

Programming Model

Table 1-9. Universe PCI Register Values for CHRP Memory Map (Continued)
ConÞguration
Address
Offset

ConÞguration
Register Name

$11C

LSI1_BD

F800 0000

$120

LSI1_TO

XXXX 0000

$128

LSI2_CTL

0000 0000

$12C

LSI2_BS

XXXX XXXX

$130

LSI2_BD

XXXX XXXX

$134

LSI2_TO

XXXX XXXX

$13C

LSI3_CTL

0000 0000

$140

LSI3_BS

XXXX XXXX

$144

LSI3_BD

XXXX XXXX

$148

LSI3_TO

XXXX XXXX

$188

SLSI

C0A053F8

1-17

Board Description and Memory Maps

PCI PREP Memory Map
The following table shows a PCI memory map of the MVME2300
series that is PREP-compatible from the point of view of the PCI
local bus.
Table 1-10. PCI PREP Memory Map
PCI Address
Size
Start

DeÞnition

Notes

End

0000 0000

00FF FFFF

16M

PCI/ISA Memory Space

0100 0000

2FFF FFFF

752M

VMEbus A32/D32 (Super/Program)

3000 0000

37FF FFFF

128M

VMEbus A32/D16 (Super/Program)

3800 0000

38FE FFFF

16M - 64K

VMEbus A24/D16 (Super/Program)

38FF 0000

38FF FFFF

64K

VMEbus A16/D16 (Super/Program)

3900 0000

39FE FFFF

16M - 64K

VMEbus A24/D32 (Super/Data)

39FF 0000

39FF FFFF

64K

VMEbus A16/D32 (Super/Data)

3A00 0000

3AFE FFFF

16M - 64K

VMEbus A24/D16 (User/Program)

3AFF 0000

3AFF FFFF

64K

VMEbus A16/D26 (User/Program)

3B00 0000

3BFE FFFF

16M - 64K

VMEbus A24/D32 (User/Data)

3BFF 0000

3BFF FFFF

64K

VMEbus A16/D32 (User/Data)

3C00 0000

7FFF FFFF

1G + 64M

PCI Memory Space

8000 0000

FBFF FFFF

2G - 64M

Onboard ECC DRAM

FC00 0000

FC03 FFFF

256K

RavenMPIC

FC04 0000

FFFF FFFF

64M - 256K

PCI Memory Space

Notes:
1. Programmable via the RavenÕs PCI Configuration registers.
For the MVME2300 series, RAM size is limited to 128MB.

1-18

Programming Model

2. To enabled the CHRP Òio-holeÓ, program the Raven to ignore
the 0x000A0000 - 0x000FFFFF address range.
3. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.
4. Programmable mapping via the Special Slave Image (SLSI) in
the Universe ASIC.
The following table shows the programmed values for the
associated Raven PCI registers for the PREP-compatible memory
map.
Table 1-11. Raven PCI Register Values for PREP Memory Map
ConÞguration
Address
Offset

ConÞguration
Register Name

$14

RavenMPIC MBASE

FC00 0000

$80

PSADD0

8000 FBFF

$84

PSOFF0 & PSATT0

8000 00FX

$88

PSADD1

0000 0000

$8C

PSOFF1 & PSATT1

0000 0000

$90

PSADD2

0000 0000

$94

PSOFF2 & PSATT2

0000 0000

$98

PSADD3

0000 0000

$9C

PSOFF3 & PSATT3

0000 0000

1-19

Board Description and Memory Maps

The next table shows the programmed values for the associated
Universe PCI registers for the PCI PREP memory map.
Table 1-12. Universe PCI Register Values for PREP Memory Map
ConÞguration
Address
Offset

1-20

ConÞguration
Register Name

$100

LSI0_CTL

C082 5100

$104

LSI0_BS

0100 0000

$108

LSI0_BD

3000 0000

$10C

LSI0_TO

XXXX 0000

$114

LSI1_CTL

C042 5100

$118

LSI1_BS

3000 0000

$11C

LSI1_BD

3800 0000

$120

LSI1_TO

XXXX 0000

$128

LSI2_CTL

0000 0000

$12C

LSI2_BS

XXXX XXXX

$130

LSI2_BD

XXXX XXXX

$134

LSI2_TO

XXXX XXXX

$13C

LSI3_CTL

0000 0000

$140

LSI3_BS

XXXX XXXX

$144

LSI3_BD

XXXX XXXX

$148

LSI3_TO

XXXX XXXX

$188

SLSI

C0A05338

Programming Model

VMEbus Mapping
Note

For the MVME2300 series, RAM size is limited to
128MB.

VMEbus Master Map
The processor can access any address range in the VMEbus with the
help from the address translation capabilities of the Universe ASIC.
The recommended mapping is shown in the Processor Memory Map
section. The following figure illustrates how the VMEbus master
mapping is accomplished.

1-21

Board Description and Memory Maps

PROCESSOR

VMEBUS

PCI MEMORY

ONBOARD
MEMORY

PROGRAMMABLE
SPACE

NOTE 2

NOTE 1

PCI MEMORY
SPACE

VME A24
VME A16
NOTE 3

VME A24
VME A16

NOTE 1
PCI/ISA
MEMORY SPACE

VME A24
VME A16

PCI
I/O SPACE

VME A24
VME A16

MPC
RESOURCES

11553.00 9609

Figure 1-2. VMEbus Master Mapping
Notes:
1. Programmable mapping done by the Raven ASIC.

1-22

Programming Model

2. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.
3. Programmable mapping via the Special Slave Image (SLSI) in
the Universe ASIC.
VMEbus Slave Map
The four programmable VME Slave Images in the Universe ASIC
allow other VMEbus masters to get to any devices on the
MVME2300 series. The combination of the four Universe VME
Slave Images and the four Raven PCI Slave Decoders offers a lot of
flexibility for mapping the system resources as seen from the
VMEbus. In most applications, the VMEbus only needs to see the
system memory and, perhaps, the software interrupt registers
(SIR1 and SIR2 registers). An example of the VMEbus slave map is
shown below:

1-23

Board Description and Memory Maps

PCI Memory

Processor

VMEbus

NOTE 2

Onboard
Memory

NOTE 1

ISA Space

PCI I/O Space
NOTE3

Software INT
Registers

1896 9609

Figure 1-3. VMEbus Slave Mapping
Notes:
1. Programmable mapping via the four VME Slave Images in
the Universe ASIC.
2. Programmable mapping via PCI Slave Images in the Raven
ASIC.
3. Fixed mapping via the PIB device.

1-24

Programming Model

The following table shows the programmed values for the
associated Universe registers for the VMEbus slave function.
Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example
ConÞguration
Address
Offset

ConÞguration
Register Name

$F00

VSI0_CTL

C0F2 0001

$F04

VSI0_BS

4000 0000

$F08

VSI0_BD

4000 1000

$F0C

VSI0_TO

C000 1000

$F14

VSI1_CTL

E0F2 00C0

$F18

VSI1_BS

1000 0000

$F1C

VSI1_BD

2000 0000

$F20

VSI1_TO

F000 0000

7000 0000

$F28

VSI2_CTL

0000 0000

$F2C

VSI2_BS

XXXX XXXX

$F30

VSI2_BD

XXXX XXXX

$F34

VSI2_TO

XXXX XXXX

$F3C

VSI3_CTL

0000 0000

$F40

VSI3_BS

XXXX XXXX

$F44

VSI3_BD

XXXX XXXX

$F48

VSI3_TO

XXXX XXXX

The above register values yield the following VMEbus slave map:

1-25

Board Description and Memory Maps

Table 1-14. VMEbus Slave Map Example
VMEbus Address
Size
Range

CHRP Map

PREP Map

Mode

4000 0000 4000 0FFF

A32 U/S/P/D
D08/16/32

PCI/ISA I/O Space:
0000 1000 - 0000 1FFF

1000 0000 1FFF FFFF

A32 U/S/P/D
D08/16/32/64
RMW

256M

PCI/ISA Memory Space
(On-board DRAM)
0000 0000 - 0FFF FFFF

PCI/ISA Memory Space
(On-board DRAM)
8000 0000 - 8FFF FFFF

1-26

Programming Model

Falcon-Controlled System Registers
The Falcon chipset latches the states of the DRAM data lines onto
the PR_STAT1 and PR_STAT2 registers. The MVME2300 series
uses these status registers to provide the system configuration
information. In addition, the Falcon chipset performs the decode
and control for an external register port. This function is utilized by
the MVME2300 series to provide the system control registers.
Table 1-15. System Register Summary

FEF88300

CPU Control Register

The following sub-sections describe these system registers in detail.

1-27

System External Cache
Control Register

FEF88000

Memory Configuration Register (Lower Falcon’s PR_STAT1)

FEF80404

System Configuration Register (Upper Falcon’s PR_STAT1)

FEF80400

BIT # ---->

Board Description and Memory Maps

System Configuration Register (SYSCR)
The states of the RD[0:31] DRAM data pins, which have weak
internal pull-ups, are latched by the upper Falcon chip at a rising
edge of the power-up reset and stored in this System Configuration
Register to provide some information about the system.
Configuration is accomplished with external pull-down resistors.
This 32-bit read-only register is defined as follows:
REG

System Configuration Register - $FEF80400

BIT

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYSID

SYSCLK

SYSXC

P0STAT

P1STAT

FIELD
OPER
RESET

READ ONLY
$FD

1111

SYSID

1111

0111

1111

1 1

System IdentiÞcation. This Þeld speciÞes the type of
the overall system conÞguration so that the software
may appropriately handle any software visible
differences. For the MVME2300 series, this Þeld
returns a value of $FD.

SYSCLK System Clock Speed. This Þeld relays the system
clock speed and the PCI clock speed information as
follows:

1-28

SYSCLK Value

System Clock Speed

PCI Clock Speed

0b0000 to 0b1100

Reserved

0b1101

50MHz

25MHz

0b1110

60MHz

30MHz

0b1111

66.66MHz

33.33MHz

Programming Model

SYSXC

System External Cache Size. The MVME2300 series
does not offer any external caching options. Reads
from this Þeld will always return a hardwired value
of 0b1111 indicating the absence of external caching.

P0/1STAT Processor 0/1 Status. This Þeld is encoded as
follows:
P0/1STAT Value

Processor 0/1 Present

External In-line
Cache Size

0b0000 to 0b0011

Reserved

0b0100

YES

0b0101

YES

512K

0b0110

YES

256K

0b0111

YES

None

0b1000 to 0b1111

N/A

1-29

Board Description and Memory Maps

Memory Configuration Register (MEMCR)
The states of the RD[00:31] DRAM data pins, which have weak
internal pull-ups, are latched by the lower Falcon chip at a rising
edge of the power-up reset and stored in this Memory
Configuration Register to provide some information about the
system memory. Configuration is accomplished with external pulldown resistors. This 32-bit read-only register is defined as follows:
REG

Memory Configuration Register - $FEF80404

BIT

63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
FLSHP2FLSHP1_
FLSHP0_

L2_PLL3
L2_PLL2
L2_PLL1
L2_PLL0
L3_TYPE3
L2_TYP2
L2_TYPE1
L2_TYPE0
R_B_TYP2
R_B_TYP1
R_B_TYP0

R_A_TYP2
R_A_TYP1
R_A_TYP0

M_SPD1
M_SPD0

M_FREF

M_SIZE1
M_SIZE0

FIELD

OPER
1
1
1
X
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
1
X
X
1
1
X
1
X
X

RESET

M_SIZE[0:1]

Memory Size. This Þeld is encoded as follows:

M_SIZE[0:1]

Total Memory On Board

0b00

16 Megabytes

0b01

32 Megabytes

0b10

64 Megabytes

0b11

128 Megabytes

M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it
indicates that a DRAM block requires faster refresh
rate. If any of the four blocks requires faster refresh
rate then the ram ref control bit should be set.

1-30

Programming Model

M_SPD[0:1] Memory Speed. This Þeld relays the memory
speed information as follows:
M_SPD[0:1]

DRAM Speed

DRAM Type

0b00

70ns

Past Page

0b01

60ns

Fast Page

0b10

Reserved

0b11

50ns

EDO

These two bits reßect the combined status of the four
blocks of DRAM. Initialization software uses this
information to program the ram_spd0 and
ram_spd1 control bits in the FalconÕs Chip Revision
Register.
R_A/B_TYP[0:2] ROM/Flash Type. This Þeld is encoded as
follows:
ROM_A/B_TYP[0:2]
0b000 to 0b101

ROM/FLASH Type
Reserved

0b110

Intel 16-bit wide FLASH with 16K Bottom Boot
Block

0b111

Unknown type (i.e. ROM/FLASH Sockets)

Note: The device width is different from the width of the FLASH
bank. If the bank width is 64-bit and the device width is 16-bit then
the FLASH bank consists of four FLASH devices.
L2_TYPE[0:3] L2 Memory Type. This Þeld is encoded as
follows:
L2_TYPE[0:3]

ConÞguration

0b0000

Late write Sync

0b0001

Pipelined Sync Burst

0b0010 to 0B1111

Reserved

1-31

Board Description and Memory Maps

L2_PLL[0:3] L2 Core Frequency to L2 Frequency Divider.
This Þeld is encoded as follows:
PLL Value]

Size

0b0000

Disable

0b0001

0b0010

1.5

0b0011

0b0100

2.5

0b0101

0b0110 to 0B1111

Reserved

FLSHP[0:2]_ Bank A Flash memory size. This Þeld is encoded
as follows:
Flash Size

FLSHP0_

FLSHP1_

FLSHP2_

1MB

2MB

4MB

8MB

16MB

32MB

64MB

No Flash

System External Cache Control Register (SXCCR)
The MVME2300 series does not implement this register. Writes to
this register location ($FEF88000) will have no system effects. Reads
from this register location will return undefined data.

1-32

Programming Model

Processor 0 External Cache Control Register (P0XCCR)
The MVME2300 series does not implement this register. Writes to
this register location ($FEF88100) will have no system effects. Reads
from this register location will return undefined data.
Processor 1 External Cache Control Register (P1XCCR)
The MVME2300 series does not implement this register. Writes to
this register location ($FEF88200) will have no system effects. Reads
from this register location will return undefined data.
CPU Control Register
The CPU Control Register is accessed via the RD[32:39] data lines
of the upper Falcon device. This 8-bit register is defined as follows:
REG
BIT

CPU Control Register - $FEF88300
2

OPER

RESET

FIELD

R/W

P0_TBEN

1
LEMODE

LEMODE Little Endian Mode. This bit must be set in
conjunction with the LEND bit in the Raven for
little-endian mode.
P0_TBEN Processor 0 Time Base Enable. When this bit is
cleared, the TBEN pin of the processor will be driven
low.

1-33

Board Description and Memory Maps

ISA Local Resource Bus
W83C553 PIB Registers
The PIB contains ISA Bridge I/O registers for various functions.
These registers are actually accessible from the PCI bus. Refer to the
W83C553 Data Book for details.

16550 UART
The 16550 UART provides the MVME2300 series with an
asynchronous serial port. Refer to the 16550 Data Sheet for
additional details and programming information.
The following table shows the mapping of the 16550 registers
within the MVME2300 seriesÕs ISA I/O space beginning at address
0x3f8:
Table 1-16. 16550 Access Registers
ISA I/O Address

1-34

Function

0000 02f8

Receiver Buffer (Read);
Transmitter Holding (Write)

0000 -03f9

Interrupt Enable

0000 03fa

Interrupt Identification (Read);
FIFO Control (Write)

0000 03fb

Line Control

0000 03fc

MODEM control

0000 03fd

Line Status

0000 03fe

MODEM Status

0000 03ff

Scratch

ISA Local Resource Bus

General-Purpose Software-Readable Header (J17)
Header J17 provides eight readable jumpers. These jumpers can be
read as a register at ISA I/O address $801 (hexadecimal). Bit 0 is
associated with header pins 1 and 2; bit 7 is associated with pins 15
and 16. The bit values are read as a 0 when the jumper is installed,
and as a 1 when the jumper is removed. The MVME230x is shipped
from the factory with J17 set to all 0s (jumpers on all pins), as shown
in Figure 1-4.
The PowerPC firmware, PPCBug, reserves all bits, SRH0 to SRH7.
With the jumper installed between pins 3 and 4 (factory
configuration), the debugger uses the current user setup/operation
parameters in Flash. When the jumper is removed (making the bit
a 1), the debugger uses the default setup/operation parameters in
NVRAM instead. Refer to the ENV command description in the
MVME2300-Series VME Processor Module Installation and Use
manual for the NVRAM defaults.
J17
Bit 0 (SRH0)

PPCBug INSTALLED
2

Reserved for future use

Bit 1 (SRH1)

Setup parameter source (In=Flash; Out=NVRAM)

Bit 2 (SRH2)

Reserved for future use

Bit 3 (SRH3)

Reserved for future use

Bit 4 (SRH4)

Reserved for future use

Bit 5 (SRH5)

Reserved for future use

Bit 6 (SRH6)

Reserved for future use

Bit 7 (SRH7) 15

Reserved for future use

Figure 1-4. General-Purpose Software-Readable Header

1-35

Board Description and Memory Maps

NVRAM/RTC & Watchdog Timer Registers
The MK48T59/559 provides the MVME2300 series with 8K of nonvolatile SRAM, a time-of-day clock, and a watchdog timer.
Accesses to the MK48T59559 are accomplished via three registers:
The NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC
Address Strobe 1 Register, and the NVRAM/RTC Data Port
Register. The NVRAM/RTC Address Strobe 0 Register latches the
lower 8 bits of the address and the NVRAM/RTC Address Strobe 1
Register latches the upper 5 bits of the address.
Table 1-17. MK48T59/559 Access Registers
PCI I/O Address

Function

0000 0074

NVRAM/RTC Address Strobe 0 (A7 - A0)

0000 0075

NVRAM/RTC Address Strobe 1 (A15 - A8)

0000 0077

NVRAM/RTC Data Register

The NVRAM and RTC is accessed through the above three
registers. When accessing a NVRAM/RTC location, follow the
following procedure:
1. Write the low address (A7-A0) of the NVRAM to the
NVRAM/RTC STB0 register,
2. Write the high address (A15-A8) of the NVRAM to the
NVRAM/RTC STB1 register, and
3. Then read or write the NVRAM/RTC Data Port.
Refer to the MK48T59 Data Sheet for additional details and
programming information.

Module Configuration and Status Registers
Four registers provide the configuration and status information
about the board. These registers are listed in the following table:

1-36

ISA Local Resource Bus

Table 1-18. Module Configuration and Status Registers
PCI I/O Address

Function

0000 0800

CPU Configuration Register

0000 0802

Base Module Feature Register

0000 0803

Base Module Status Register

0000 08C0 - 0000 08C1

Seven-Segment Display Register

The following sub sections describe these registers in detail.
CPU Configuration Register
The CPU Configuration Register is an 8-bit register located at ISA
I/O address x0800. This register is defined for the MVME2300
series to provide some backward compatibility with older
MVME1600 products. The Base Module Status Register should be
used to identify the base module type and the System
Configuration Register should be used to obtain information about
the overall system.
REG
BIT

Old CPU Configuration Register - $FE000800
SD7

SD6

SD5

SD4

SD3

SD2

SD1

FIELD

CPUTYPE

OPER

RESET

SD0

CPUTYPE CPU Type. This Þeld will always read as $E for the
MVME2300 series. (The whole register will read
$EF.) The System ConÞguration Register should be
used for additional information.

1-37

Board Description and Memory Maps

Base Module Feature Register
The Base Module Feature Register is an 8-bit register providing the
configuration information about the MVME2300-series VME
Processor Module. This read-only register is located at ISA I/O
address x0802.
REG
BIT

Base Module Feature Register - Offset $0802
SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

PCIXP_

PMC2P_

PMC1P_

VMEP_

OPER

RESET

PCIXP_

LANP_

FIELD

PCI Expansion Slot Present. If set, there is no PCIX
device installed. If cleared, the PCIX slot contains a
PCI Mezzanine Card.

PMC2P_ PMC Slot 2 Present. If set, there is no PCI Mezzanine
Card installed in the PMC Slot 2. If cleared, the PMC
Slot 2 contains a PMC.
PMC1P_ PMC Slot 1 Present. If set, there is no PCI Mezzanine
Card installed in the PMC Slot 1. If cleared, the PMC
Slot 1 contains a PMC.

1-38

VMEP_

VMEbus Present. If set, there is no VMEbus
interface. If cleared, VMEbus interface is supported.

LANP_

Ethernet Present. If set, there is no Ethernet
transceiver interface. If cleared, there is on-board
Ethernet support.

ISA Local Resource Bus

Base Module Status Register (BMSR)
The Base Module Status Register is an 8-bit read-only register
located at ISA I/O address x0803.
REG
BIT

Base Module Status Register - Offset $0803
SD7

SD6

SD5

SD4

SD3

FIELD

SD1

SD0

BASE_TYPE

OPER
RESET

SD2

R
1

N/A

BASE_TYPEBase Module Type. This four bit Þeld is used to
provide the category of the base module and is
deÞned as follows:
BASE_TYPE Value

Base Module Type

$0 to $8

Reserved

MVME2300

$A to $F

Reserved

1-39

Board Description and Memory Maps

Seven-Segment Display Register
Note

This register is NOT USED on the MVME2300-series
boards.

This 16-bit register allows data to be sent to the 4-digit hexadecimal
diagnostic display. The register also allows the data to be read back.
REG

DIG0[3:0]

R/W
X

DIG3[3:0] Hexadecimal value of the most signiÞcant digit.
DIG2[3:0] Hexadecimal value of the third signiÞcant digit.
DIG1[3:0] Hexadecimal value of the second signiÞcant digit.
DIG0[3:0] Hexadecimal value of the least signiÞcant digit.

VME Registers
The following registers provide the following functions for the
VMEbus interface: a software interrupt capability, a location
monitor function, and a geographical address status. For these
registers to be accessible from the VMEbus, the Universe ASIC
must be programmed to map the VMEbus Slave Image 0 into the
appropriate PCI I/O address range. Refer to the VMEbus Slave
Map section for additional details. The following table shows the
registers provided for various VME functions:

1-40

SD0

SD1

DIG1[3:0]

SD2

SD3

SD4

SD5

SD6

SD7

DIG2[3:0]

OPER
RESET

SD8

SD9

DIG3[3:0]

SD10

SD11

SD12

SD13

FIELD

SD14

SD15

BIT

7-Segment Display Register - Offset $08C0

ISA Local Resource Bus

Table 1-19. VME Registers
PCI I/O Address

Function

0000 1000

SIG/LM Control Register

0000 1001

SIG/LM Status Register

0000 1002

VMEbus Location Monitor Upper Base Address

0000 1003

VMEbus Location Monitor Lower Base Address

0000 1004

VMEbus Semaphore Register 1

0000 1005

VMEbus Semaphore Register 2

0000 1006

VMEbus Geographical Address Status

These registers are described in the following sub-sections.
LM/SIG Control Register
The LM/SIG Control Register is an 8-bit register located at ISA I/O
address x1000. This register provides a method to generate
software interrupts. The Universe ASIC is programmed so that this
register can be accessed from the VMEbus to generate software
interrupts to the processor(s).
REG

LM/SIG Control Register - Offset $1000

BIT

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

FIELD

SET
SIG1

SET
SIG0

SET
LM1

SET
LM0

CLR
SIG1

CLR
SIG0

CLR
LM1

CLR
LM0

OPER
RESET

WRITE-ONLY
0

SET_SIG1 Writing a 1 to this bit will set the SIG1 status bit.
SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit.

1-41

Board Description and Memory Maps

SET_LM1 Writing a 1 to this bit will set the LM1 status bit.
SET_LM0 Writing a 1 to this bit will set the LM0 status bit.
CLR_SIG1Writing a 1 to this bit will clear the SIG1 status bit.
CLR_SIG0Writing a 1 to this bit will clear the SIG0 status bit.
CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit.
CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit.
LM/SIG Status Register
The LM/SIG Status Register is an 8-bit register located at ISA I/O
address x1001. This register, in conjunction with the LM/SIG
Control Register, provides a method to generate interrupts. The
Universe ASIC is programmed so that this register can be accessed
from the VMEbus to provide a capability to generate software
interrupts to the onboard processor(s) from the VMEbus.
REG

LM/SIG Status Register - Offset $1001

BIT

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

FIELD

EN
SIG1

EN
SIG0

EN
LM1

EN
LM0

SIG1

SIG0

LM1

LM0

OPER
RESET

R/W
0

READ-ONLY
0

EN_SIG1 When the EN_SIG1 bit is set, a LM/SIG Interrupt 1
is generated if the SIG1 bit is asserted.
EN_SIG0 When the EN_SIG0 bit is set, a LM/SIG Interrupt 0
is generated if the SIG0 bit is asserted.
EN_LM1 When the EN_LM1 bit is set, a LM/SIG Interrupt 1
is generated and the LM1 bit is asserted.
EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrupt 0
is generated and the LM0 bit is asserted.

1-42

ISA Local Resource Bus

SIG1

SIG1 status bit. This bit can only be set by the
SET_LM1 control bit. It can only be cleared by a reset
or by writing a 1 to the CLR_LM1 control bit.

SIG0

SIG0 status bit. This bit can only be set by the
SET_LM0 control bit. It can only be cleared by a reset
or by writing a 1 to the CLR_LM0 control bit.

LM1

LM1 status bit. This bit can be set by either the
location monitor function or the SET_LM1 control
bit. LM1 correspond to offset 3 from the location
monitor base address. This bit can only be cleared by
a reset or by writing a 1 to the CLR_LM1 control bit.

LM0

LM0 status bit. This bit can be set by either the
location monitor function or the SET_LM0 control
bit. LM0 correspond to offset 1 from the location
monitor base address. This bit can only be cleared by
a reset or by writing a 1 to the CLR_LM0 control bit.

Location Monitor Upper Base Address Register
The Location Monitor Upper Base Address Register is an 8-bit
register located at ISA I/O address x1002. The Universe ASIC is
programmed so that this register can be accessed from the VMEbus
to provide VMEbus location monitor function.
REG

Location Monitor Upper Base Address Register - Offset $1002

BIT

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

FIELD

VA15

VA14

VA13

VA12

VA11

VA10

VA9

VA8

OPER
RESET

R/W
0

VA[15:8]

Upper Base Address for the location monitor
function.

1-43

Board Description and Memory Maps

Location Monitor Lower Base Address Register
The Location Monitor Lower Base Address Register is an 8-bit
register located at ISA I/O address x1003. The Universe ASIC is
programmed so that this register can be accessed from the VMEbus
to provide VMEbus location monitor function.
REG

Location Monitor Lower Base Address Register - Offset $1003

BIT

SD7

SD6

SD5

SD4

SD3

FIELD

VA7

VA6

VA5

VA4

LMEN

OPER
RESET

R/W
0

SD2

SD1

SD0

VA[7:4]

Lower Base Address for the location monitor
function.

LMEN

This bit must be set to enable the location monitor
function.

Semaphore Register 1
The Semaphore Register 1 is an 8-bit register located at ISA I/O
address x1004. The Universe ASIC is programmed so that this
register can be accessible from the VMEbus. This register can only
be updated if bit 7 is low or if the new value has the most significant
bit cleared. When bit 7 is high, this register will not latch in the new
value if the new value has the most significant bit set.
REG
BIT

Semaphore Register 1 - Offset $1004
SD7

SD6

SD5

SD4

FIELD

SEM1

OPER

R/W

RESET

1-44

SD3

SD2

SD1

SD0

ISA Local Resource Bus

Semaphore Register 2
The Semaphore Register 2 is an 8-bit register located at ISA I/O
address x1005. The Universe ASIC is programmed so that this
register can be accessible from the VMEbus. This register can only
be updated if bit 7 is low or if the new value has the most significant
bit cleared. When bit 7 is high, this register will not latch in the new
value if the new value has the most significant bit set.
REG
BIT

Semaphore Register 2 - Offset $1005
SD7

SD6

SD5

SD4

FIELD

SEM2

OPER

R/W

RESET

SD3

SD2

SD1

SD0

VME Geographical Address Register (VGAR)
The VME Geographical Address Register is an 8-bit read-only
register located at ISA I/O address x1006. This register reflects the
states of the geographical address pins at the 5-row, 160-pin P1
connector.
REG
BIT

VME Geographical Address Register - Offset $1006
SD7

SD6

FIELD

SD5

SD4

SD3

SD2

SD1

SD0

GAP#

GA4#

GA3#

GA2#

GA1#

GA0#

OPER
RESET

READ ONLY
X

1-45

Board Description and Memory Maps

Emulated Z8536 CIO Registers and Port Pins
Although the MVME2300 series does not use a Z8536, there are
several functions within this part that are emulated within an ISA
Register PLD. These functions are accessed by reading/writing the
Port A, B, C Data Registers and Control Register. Note that the
Pseudo IACK function is not implemented in the MVME2300
series.
Emulated Z8536 Registers
The MVME2300 series implements the Z8536 CIO functions
according to the following table.
Table 1-20. Emulated Z8536 Access Registers
PCI I/O Address

Function

0000 0844

Port C’s Data Register

0000 0845

Port B’s Data Register

0000 0846

Port A’s Data Register

0000 0847

Control Register

Z8536 CIO Port Pins
The following table shows the signal function and port mapping for
the Z8536 CIO emulation. The direction of these ports are fixed in
hardware.
Table 1-21. Z8536 CIO Port Pins Assignment
Port
Pin

Signal
Name

Direction

Descriptions

PA0

I/O

Not used

PA1

I/O

Not used

PA2

I/O

Not used

PA3

I/O

Not used

1-46

ISA Local Resource Bus

Table 1-21. Z8536 CIO Port Pins Assignment (Continued)
Port
Pin

Signal
Name

Direction

Descriptions

PA4

I/O

Not used

PA5

I/O

Not used

PA6

BRDFAIL

Output

Board Fail: When set will cause BFL LED to be lit.

PA7

I/O

Not used

PB0

I/O

Not used

PB1

I/O

Not used

PB2

I/O

Not used

PB3

I/O

Not used

PB4

I/O

Not used

PB5

I/O

Not used

PB6

I/O

Not used

PB7

ABORT_

Input

Status of ABORT# signal

PC0

I/O

Not used

PC1

I/O

Not used

PC2

BASETYP0

Input

PC3

BASETYP1

Input

Genesis Base Module Type:
00b = Genesis II (see Base Module Status Register)
01b = MVME1600-011
10b = Reserved
11b = MVME1600-001

ISA DMA Channels
The MVME2300 series does not implement any ISA DMA channels.

1-47

Board Description and Memory Maps

1-48

2Raven PCI Host Bridge & MultiProcessor Interrupt Controller Chip

Introduction
Overview
This document describes the architecture and usage of the Raven, a
PowerPC to PCI Local Bus Bridge ASIC. The Raven is intended to
provide PowerPC 60x (MPC60x) compliant devices access to
devices residing on the PCI Local Bus. In the remainder of this
chapter, the MPC60x bus will be referred to as the MPC bus and the
PCI Local Bus as PCI. PCI is a high performance 32-bit or 64-bit,
burst mode, synchronous bus capable of transfer rates of 132
MByte/sec in 32-bit mode or 264 MByte/sec in 64-bit mode using a
33 MHz clock.

Features
❏

MPC Bus Interface
Ð Direct interface to MPC603 or MPC604 processors.
Ð 64-bit data bus, 32-bit address bus.
Ð Four independent software programmable slave map
decoders.
Ð Multi-level write post FIFO for writes to PCI.
Ð Support for MPC bus clock speeds up to 66 MHz.
Ð Selectable big or little endian operation.
Ð 3.3 V signal levels

❏

PCI Interface
Ð Fully PCI Rev. 2.0 compliant.
Ð 32-bit or 64-bit address/data bus.
Ð Support for accesses to all four PCI address spaces.

2-1

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Ð Single-level write posting buffers for writes to the MPC
bus.

Ð Read-ahead buffer for reads from the MPC bus.
Ð Four independent software programmable slave map
decoders.
❏

Interrupt Controller
Ð MPIC compliant.
Ð Support for 16 external interrupt sources and two
processors.
Ð Multiprocessor interrupt control allowing any interrupt
source to be directed to either processor.
Ð Multilevel cross processor interrupt control for
multiprocessor synchronization.
Ð Four 31 bit tick timers.

❏

2-2

Two 64-bit general purpose registers for cross-processor
messaging.

MPC Slave

PCI Slave

Raven

MPC Dec

Reg

MPCADIN

Reg

PCIADIN

PCI Dec

Mux

MPC Bus

MPC Regs

Endian

Data Path ‘B’

Endian

Data Path ‘A’

PCI Regs

MPIC

PCI Bus

FIFO

Reg

MPC Master

Mux

Mux MPC

Mux PCI
Mux
Reg

PCI Master

Block Diagram

Block Diagram
2

1914 9702

Figure 2-1. Raven Block Diagram

2-3

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Functional Description
Architectural Overview
A functional block diagram of the Raven is shown in Figure 2-1. The
Raven control logic is subdivided into the following functions: PCI
slave, PCI master, MPC slave and MPC master. The Raven data
path logic is subdivided into the following functions: Data Path ÔAÕ
FIFOs/muxes, Data Path ÔBÕ FIFOs/muxes, PCIADIN, MPCADIN,
Mux PCI, and Mux MPC. Address decoding is handled in the PCI
Decode and MPC Decode blocks. The control register logic is
contained in the PCI Registers and MPC Registers blocks. The
interrupt controller (RavenMPIC) and the MPC arbiter functions
make up the remainder of the Raven design.
The data path function imposes some restrictions on access to the
RavenMPIC, the PCI Registers, and the MPC Registers. The
RavenMPIC and the PCI Registers are only accessible to PCIoriginated transactions. The MPC Registers are only accessible to
MPC-originated transactions.

MPC Bus Interface
The MPC Bus Interface is designed to be coupled directly to up to
two MPC603 or MPC604 microprocessors as well as a
memory/cache subsystem. It uses a subset of the capabilities of the
MPC60x bus protocol.
MPC Address Mapping
The Raven will map either PCI memory space or PCI I/O space into
MPC address space using four programmable map decoders. These
decoders provide windows into the PCI bus from the MPC bus. The
most significant 16 bits of the MPC address are compared with the
address range of each map decoder, and if the address falls within
the specified range, the access is passed on to PCI. An example of
this is shown in Figure 2-2.

2-4

Functional Description

2
MPC Bus Address

8 0 8 0 1 2 3 4
0

1516

Decode is

MSADDx Register

and

7 0 8 0 9 0 0 0
0

1516

Figure 2-2. MPC to PCI Address Decoding
There are no limits imposed by Raven on how large of an address
space a map decoder can represent. There is a lower limit of a
minimum of 64 KBytes due to the resolution of the address
compare logic.
For each map, there is an associated set of attributes. These
attributes are used to enable read accesses, enable write accesses,
enable write posting, and define the PCI transfer characteristics.

2-5

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Each map decoder also includes a programmable 16-bit address
offset. The offset is added to the 16 most significant bits of the MPC
address, and the result is used as the PCI address. This offset allows
PCI devices to reside at any PCI address, independent of the MPC
address map. An example of this is shown in Figure 2-3.

MPC Bus Address

8 0 8 0 1 2 3 4
0

1516

MSOFFx Register

9 0 0 0
0

PCI Bus Address

1 0 8 0 1 2 3 4
31

1615

Figure 2-3. MPC to PCI Address Translation
Care should be taken to assure that all programmable decoders
decode unique address ranges since overlapping address ranges
will lead to undefined operation.
MPC Slave
The MPC slave provides the interface between the MPC bus and the
Raven FIFOs. The MPC slave is responsible for tracking and
maintaining coherency to the 60x processor bus protocol.
The MPC slave divides MPC command types into three categories:
address only, write, and read. If a command type is an address only
and the address presented at the time of the command is a valid
Raven address, the MPC slave will respond immediately. The

2-6

Functional Description

Raven will not respond to address only cycles where the address
presented is not a Raven address. The response of the MPC slave to
command types is listed in Table 2-1.
Table 2-1. MPC Slave Response Command Types
MPC Transfer Type

Transfer
Encoding

Transaction

Clean Block

00000

Addr Only

Flush Block

00100

Addr Only

SYNC

01000

Addr Only

Kill Block

01100

Addr Only

EIEIO

10000

Addr Only

ECOWX

10100

No Response

TLB Invalidate

11000

Addr Only

ECIWX

11100

No Response

LWARX

00001

Addr Only

STWCX

00101

Addr Only

TLBSYNC

01001

Addr Only

ICBI

01101

Addr Only

Reserved

1XX01

No Response

Write-with-ßush

00010

Write

Write-with-kill

00110

Write

Read

01010

Read

Read-with-intent-to-modify

01110

Read

Write-with-ßush-atomic

10010

Write

Reserved

10110

No Response

Read-atomic

11010

Read

Read-with-intent-to-modify-atomic

11110

Read

Reserved

00011

No Response

Reserved

00111

No Response

Read-with-no-intent-to-cache

01011

Read

Reserved

01111

No Response

Reserved

1xx11

No Response

2-7

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

MPC Write Posting
The MPC write FIFO stores up to eight data beats in any
combination of single- and four-beat (burst) transactions. If write
posting is enabled, Raven stores the data necessary to complete an
MPC write transfer to the PCI bus and immediately acknowledges
the transaction on the MPC bus. This frees the MPC bus from
waiting for the potentially long PCI arbitration and transfer. The
MPC bus may be used for more useful work while the Raven
manages the completion of the write posted transaction on PCI.
All transactions will be completed on the PCI bus in the same order
that they are completed on the MPC bus. A read or a compelled
write transaction will force all previously issued write posted
transactions to be flushed from the FIFO. All write posted transfers
will be completed before a non-write posted read or write is begun,
to assure that all transfers are completed in the order issued. All
write posted transfers will also be completed before any access to
the RavenÕs registers is begun.
MPC Master
The MPC master will attempt to move data using burst transfers
wherever possible. A 64-bit by 16 entry FIFO is used to hold data
between the PCI slave and the MPC master to ensure that optimum
data throughput is maintained. While the PCI slave is filling the
FIFO with one cache line worth of data, the MPC master can be
moving another cache line worth onto the MPC bus. This will allow
the PCI slave to receive long block transfers without stalling.
When programmed in Òread aheadÓ mode (the RAEN bit in the
PSATTx register is set) and the PCI slave receives a Memory Read
Line or Memory Read Multiple command, the MPC master will
fetch data in bursts and store it in the FIFO. The contents of the FIFO
will then be used to attempt to satisfy the data requirements for the
remainder of the PCI block transaction. If the data requested is not
in the FIFO, the MPC master will read another cache line. The
contents of the FIFO are ÒinvalidatedÓ at the end of each PCI block
transaction.

2-8

Functional Description

Notes 1. Read ahead mode should not be used when data
coherency may be a problem, as there is no way to
snoop all MPC bus transactions and invalidate the
contents of the FIFO.

2. Accesses near the top of local memory with readahead mode enabled could cause the MPC master to
perform reads beyond the top of local memory which
could result in an MPC bus timeout error.
The MPC bus transfer types generated by the MPC master depend
on the PCI command code and the INV/GBL bits in the PSATTx
registers. The GBL bit determines whether or not the GBL* signal is
asserted for all portions of a transaction, and is fully independent of
the PCI command code and INV bit. Table 2-2 shows the
relationship between PCI command codes and the INV bit.
Table 2-2. MPC Transfer Types
PCI Command Code

INV

MPC Transfer Type

MPC Transfer Size

TT0-TT4

Memory Read
Memory Read Multiple
Memory Read Line

Read

Burst/Single Beat

01010

Memory Read
Memory Read Multiple
Memory Read Line

Read With Intent to
Modify

Burst/Single Beat

01110

Memory Write
Memory Write and
Invalidate

Write with Kill

Burst

00110

Memory Write
Memory Write and
Invalidate

Write with Flush

Single Beat

00010

The MPC master incorporates an optional operating mode called
Bus Hog. When Bus Hog is enabled, the MPC master will
continually request the MPC bus for the entire duration of each PCI
transfer. When Bus Hog is not enabled, the MPC master will

2-9

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

structure its bus request actions according to the requirements of
the FIFO. Caution should be exercised when using this mode since
the over-generosity of bus ownership to the MPC master can be
detrimental to the host CPUÕs performance. The Bus Hog mode can
be controlled by the BHOG bit within the GCSR. The default state
for BHOG is disabled.

MPC Arbiter
The MPC Arbiter is an optional feature in the Raven, and is not
used on the MVME2300 series. Arbitration for the MPC bus on the
MVME2300 series is performed external to the Raven.
MPC Bus Timer
The MPC bus timer allows the current bus master to recover from a
lock-up condition caused when no slave responds to the transfer
request.
The time-out length of the bus timer is determined by the MBT field
in the Global Control/Status Register.
The bus timer starts ticking at the beginning of an address transfer
(TS* asserted), and if the address transfer is not terminated (AACK*
asserted) before the time-out period has passed, the Raven will
assert the MATO bit in the MPC Error Status Register, latch the
MPC address in the MPC Error Address Register, and then
terminate the cycle.
The MATO bit may be configured to generate an interrupt or a
machine check through the MEREN register.
The timer is disabled if the transfer is intended for PCI. PCI bound
transfers will be timed by the PCI master.

PCI Interface
The Raven PCI Interface is designed to connect directly to a PCI
Local Bus, and supports Master and Target transactions within
Memory space, I/O Space, and Configuration Space.

2-10

Functional Description

The PCI interface may operate at any clock speed up to 33 MHz.
The PCLK input must be externally synchronized with the MCLK
input, and the frequency of the PCLK input must be exactly half the
frequency of the MCLK input.
PCI Address Mapping
Raven provides three resources to PCI:
❏

Configuration registers mapped into PCI Configuration
space

❏

MPC bus address space mapped into PCI Memory space

❏

RavenMPIC control registers mapped into either PCI I/O
space or PCI Memory space

ConÞguration Registers:
The Raven does not have an IDSEL pin. An internal connection is
made within the Raven that logically associates the assertion of
IDSEL with the assertion of AD31.
Raven provides a configuration space that is fully compliant with
the PCI Local Bus Specification 2.0 definition for configuration
space. There are two base registers within the standard 64 byte
header that are used to control the mapping of RavenMPIC. One
register is dedicated to mapping RavenMPIC into PCI I/O space,
and the other register is dedicated to mapping RavenMPIC into PCI
Memory space. The mapping of MPC address space is handled by
device specific registers located above the 64 byte header. These
control registers support a mapping scheme that is functionally
similar to the PCI-to-MPC mapping scheme described in the section
on MPC Address Mapping earlier in this chapter.
MPC Bus Address Space:
The Raven will map MPC address space into PCI Memory space
using four programmable map decoders. The most significant 16
bits of the PCI address is compared with the address range of each

2-11

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

map decoder, and if the address falls within the specified range, the
access is passed on to the MPC bus. An example of this is shown in
Figure 2-4.

PCI Bus Address

8 0 8 0 1 2 3 4
31

Decode is

PSADDx Register

1615

and

7 0 8 0 9 0 0 0
31

1615

Figure 2-4. PCI to MPC Address Decoding
There are no limits imposed by Raven on how large of an address
space a map decoder can represent. There is a lower limit of a
minimum of 64 KBytes due to the resolution of the address
compare logic.
For each map, there is an independent set of attributes. These
attributes are used to enable read accesses, enable write accesses,
enable write posting, and define the MPC bus transfer
characteristics.

2-12

Functional Description

Each map decoder also includes a programmable 16-bit address
offset. The offset is added to the 16 most significant bits of the PCI
address, and the result is used as the MPC address. This offset
allows devices to reside at any MPC address, independent of the
PCI address map. An example of this is shown in Figure 2-5.
PCI Bus Address

8 0 8 0 1 2 3 4
31

1615

PSOFFx Register

9 0 0 0
31

MPC Bus Address

1 0 8 0 1 2 3 4
0

1516

Figure 2-5. PCI to MPC Address Translation
All Raven address decoders are prioritized so that programming
multiple decoders to respond to the same address is not a problem.
When the PCI address falls into the range of more than one decoder,
only the highest priority one will respond. The decoders are
prioritized as shown below.
Decoder
PCI Slave 0

Priority
highest

PCI Slave 1
PCI Slave 2
PCI Slave 3

lowest

2-13

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

RavenMPIC Control Registers:

The RavenMPIC control registers are located within either PCI
Memory or PCI I/O space using traditional PCI defined base
registers within the predefined 64-byte header. Please see the
section on Raven Interrupt Controller Implementation for more
information.
PCI Slave
The PCI slave provides the control logic needed to interface the PCI
bus to RavenÕs FIFOs. The PCI slave can accept either 32-bit or 64bit transactions, however it can only accept 32-bit addressing. There
is no limit to the length of the transfer that the slave can handle.
During posted write cycles, the slave will continue to accept write
data until the write post FIFO is full. If the write post FIFO is full,
the slave will hold off the master with wait states until there is more
room in the FIFO. The slave will not initiate a disconnect. If the
write transaction is compelled, the slave will hold off the master
with wait states while each beat of data is being transferred. The
slave will acknowledge the completion of the transfer only after the
data transfer has successfully completed on the MPC bus. If a read
transaction is being performed within an address space marked for
prefetching, the slave (in conjunction with the MPC master) will
attempt to read ahead far enough on the MPC bus to allow for an
uninterrupted burst transaction on the PCI bus. Read transactions
within address spaces marked for no prefetching will be
acknowledged on the PCI bus only after a single beat read has
successfully completed on the MPC bus. Each read on the MPC bus
will only be started after the previous read has been acknowledged
on the PCI bus and there is an indication that the PCI master wishes
for more data to be transferred.
The following paragraphs identify some associations between the
operation of the PCI slave and the PCI 2.0 Local Bus Specification
requirements.

2-14

Functional Description

Command Types:

Table 2-3 shows which types of PCI cycles the slave has been
designed to accept.
Table 2-3. PCI Slave Response Command Types
Command Type

Slave Response?

Interrupt Acknowledge

Special Cycle

I/O Read

Yes

I/O Write

Yes

Reserved

Memory Read

Yes

Memory Write

Yes

Reserved

ConÞguration Read

Yes

ConÞguration Write

Yes

Memory Read Multiple

Yes

Dual Address Cycle

Memory Read Line

Yes

Memory Write and
Invalidate

Yes

Addressing:
The slave will accept any combination of byte enables during read
or write cycles. During write cycles, a discontinuity (i.e., a ÔholeÕ) in
the byte enables will force the slave to issue a disconnect. During all
read cycles, the slave will return an entire word of data regardless
of the byte enables. During I/O read cycles, the slave will perform
integrity checking of the byte enables against the address being
presented and assert SERR* in the event there is an error.

2-15

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

The slave will only honor the Linear Incrementing addressing
mode. The slave will perform a disconnect with data if any other
mode of addressing is attempted.

Device Selection:
The PCI slave will always respond valid decoded cycles as a
medium responder.
Target Initiated Termination:
The PCI slave normally strives to complete transactions without
issuing disconnects or retries. One exception is where the slave is
performing configuration cycles. All configuration cycles will be
terminated with a disconnect after one data beat has been
transferred. Another exception is the issue of a disconnect when
asked to perform a transaction with byte enable ÔholesÕ.
Fast Back-to-Back Transactions:
The PCI slave supports both of the fundamental target
requirements for fast back-to-back transactions. The PCI slave
meets the first criteria of being able to successfully track the state of
the PCI bus without the existence of an IDLE state between
transactions. The second criteria associate with signal turn-around
timing is met by default since the slave functions as a medium
responder.
Latency:
The PCI slave does not have any hardware mechanisms in place to
guarantee that the initial and subsequent target latency
requirements are met. Typically this is not a problem since the
bandwidth of the MPC bus far exceeds the bandwidth of the PCI
bus. The Raven MPC arbiter has been designed to give the highest
priority for its own transactions which further reduces PCI bus
latency.
Exclusive Access:
The PCI slave has no mechanism to support exclusive access.

2-16

Functional Description

Parity:

The PCI slave supports address parity error detection, data parity
generation and data parity error detection.
Cache Support:
The PCI slave does not participate in the PCI caching protocol.
PCI Write Posting
If write posting is enabled, the Raven stores the target address,
attributes, and up to 128 bytes of data from one PCI write
transaction and immediately acknowledges the transaction on the
PCI bus. This allows the slower PCI to continue to transfer data at
its maximum bandwidth, and the faster MPC bus to accept data in
high performance cache-line burst transfers.
Only one PCI transaction may be write posted at any given time. If
the Raven is busy processing a previous write posted transaction
when a new PCI transaction begins, the next PCI transaction will be
delayed (TRDY* will not be asserted) until the previous transaction
has completed. If during a transaction the write post buffer gets
full, subsequent PCI data transfers will be delayed (TRDY* will not
be asserted) until the Raven has removed some data from the FIFO.
Under normal conditions, the Raven should be able to empty the
FIFO faster than the PCI bus can fill it.
PCI Configuration cycles intended for internal Raven registers will
also be delayed if Raven is busy so that control bits which may
affect write posting do not change until all write posted
transactions have completed.
PCI Master
The PCI master, in conjunction with the capabilities of the MPC
slave, will attempt to move data in either single beat or four-beat
(burst) transactions. All single beat transactions will be subdivided
into one or two 32-bit transfers, depending on the alignment and
size of the transaction. The PCI master will attempt to transfer all
four-beat transactions in 64-bit mode if the PCI bus has 64-bit mode

2-17

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

enabled. If at any time during the transaction the PCI target
indicates it can not support 64-bit mode, the PCI master will
continue to transfer the remaining data in 32-bit mode.

The PCI master can support Critical Word First (CWF) burst
transfers. The PCI master will divide this transaction into two parts.
The first part will start on the address presented with the CWF
transfer request and continue up to the end of the current cache
line. The second transfer will start at the beginning of the associated
cache line and work its way up to (but not including) the word
addressed by the CWF request.
It should be noted that even though the master can support burst
transactions, a majority of the transaction types handled are singlebeat transfers. Typically PCI space is not configured as cache-able,
therefore burst transactions to PCI space would not naturally occur.
It must be supported since it is conceivable that bursting could
happen. For example, nothing prevents the processor from loading
up a cache line with PCI write data and manually flushing the cache
line.
The following paragraphs identify some associations between the
operation of the PCI master and the PCI 2.0 Local Bus Specification
requirements.
Command Types:
The PCI Command Codes generated by the PCI master depend on
the type of transaction being performed on the MPC bus. Please
refer to the section on the MPC Slave earlier in this chapter for a

2-18

Functional Description

further description of MPC bus read and MPC bus write. Table 2-4
summarizes the command types supported and how they are
generated.
Table 2-4. PCI Master Command Codes
Entity Addressed

MPC
Transfer Type

TBST*

MEM C/BE

PCI Command

PIACK

Read

0000

Interrupt Acknowledge

CONADD/CONDAT

Write

0001

Special Cycle

MPC Mapped PCI
Space

Read

0010

I/O Read

Write

0011

I/O Write

-- Unsupported --

0100

Reserved

-- Unsupported --

0101

Reserved

MPC Mapped PCI
Space

Read

0110

Memory Read

Write

0111

Memory Write

-- Unsupported --

1000

Reserved

-- Unsupported --

1001

Reserved

CONADD/CONDAT

Read

1010

ConÞguration Read

CONADD/CONDAT

Write

1011

ConÞguration Write

-- Unsupported --

1100

Memory Read Multiple

-- Unsupported --

1101

Dual Address Cycle

1110

Memory Read Line

1111

Memory Write and
Invalidate

MPC Mapped PCI
Space

Read
-- Unsupported --

Addressing:
The PCI master will generate all memory transactions using the
linear incrementing addressing mode.
Combining, Merging, and Collapsing:
The PCI master does not participate in any of these protocols.

2-19

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Master Initiated Termination:

The PCI master can handle any defined method of target retry,
target disconnect, or target abort. If the target responds with a retry,
the PCI master will wait for the required two clock periods and
attempt the transaction again. This will continue indefinitely until
the transaction has completed, the transaction is aborted by the
target, or if the transaction is aborted due to a Raven detected
bridge lock. The same happens if the target responds with a
disconnect and there is still data to be transferred.
If the PCI master detects a target abort during a read, any
untransferred read data will be filled with ones. If the PCI master
detects a target abort during a write, any untransferred portions of
data will be dropped. The same rule applies if the PCI master
generates a Master Abort cycle.
Arbitration:
The PCI master can support parking on the PCI bus. If the PCI
master starts a transaction that is going to take more than one beat,
the PCI master will continuously assert its request until the
transaction has completed. The one exception is when the PCI
master receives a disconnect or a retry.
Fast Back-to-Back Transactions:
The PCI master does not generate fast back-to-back transactions.
Arbitration Latency:
Because a bulk of the transactions are limited to single-beat
transfers on PCI, the PCI master does not implement a Master
Latency Timer.
Exclusive Access:
The PCI master is not able to initiate exclusive access transactions.

2-20

Functional Description

Address/Data Stepping:

The PCI master does not participate in the Address/Data Stepping
protocol.
Parity:
The PCI master supports address parity generation, data parity
generation, and data parity error detection.
Cache Support:
The PCI master does not participate in the PCI caching protocol.
Generating PCI Cycles
There are four basic types of bus cycles that can be generated on the
PCI bus:
❏

Memory and I/O

❏

Configuration

❏

Special Cycle

❏

Interrupt Acknowledge

Generating PCI Memory and I/O Cycles
Each programmable slave may be configured to generate PCI I/O
or memory accesses through the MEM and IOM fields in its
Attribute register as shown below.
:

MEM

IOM

PCI Cycle Type

Memory

Contiguous I/O

Spread I/O

2-21

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

If the MEM bit is set, the Raven will perform Memory addressing
on the PCI bus. The Raven will take the MPC bus address, apply the
offset specified in the MSOFFx register, and map the result directly
to the PCI bus.

The IBM CHRP specification describes two approaches for
handling PCI I/O addressing: contiguous or spread address
modes. When the MEM bit is cleared, the IOM bit is used to select
between these two modes whenever a PCI I/O cycle is to be
performed.
The Raven will perform contiguous I/O addressing when the MEM
bit is clear and the IOM bit is clear. The Raven will take the MPC
address, apply the offset specified in the MSOFFx register, and map
the result directly to PCI.
The Raven will perform spread I/O addressing when the MEM bit
is clear and the IOM bit is set. The Raven will take the MPC address,
apply the offset specified in the MSOFFx register, and map the
result to PCI as shown in Figure 2-6.
.

MPC Address + Offset
31

12 11

25 24

5 4

0 0
00 00 00 00 00 0
PCI Address
1915 9702

Figure 2-6. PCI Spread I/O Address Translation
Spread I/O addressing allows each PCI deviceÕs I/O registers to
reside on a different MPC memory page, so device drivers can be
protected from each other using memory page protection.

2-22

Functional Description

All I/O accesses must be performed within natural word
boundaries. Any I/O access that is not contained within a natural
word boundary will result in unpredictable operation. For
example, an I/O transfer of four bytes starting at address $80000010
is considered a valid transfer. An I/O transfer of four bytes starting
at address $80000011 is considered an invalid transfer since it
crosses the natural word boundary at address
$80000013/$80000014.
Generating PCI ConÞguration Cycles
The Raven uses configuration mechanism #1 as defined in the PCI
Local Bus Specification 2.0 to generate configuration cycles. Please
refer to this specification for a complete description of this function.
Configuration mechanism #1 uses an address register/data register
format. Performing a configuration access is a two step process. The
first step is to place the address of the configuration cycle within the
CONFIG_ADDRESS register. Note that this action does not
generate any cycles on the PCI bus. The second step is to either read
or write configuration data into the CONFIG_DATA register. If the
CONFIG_ADDRESS register has been set up correctly, the Raven
will pass this access on to the PCI bus as a configuration cycle.
The addresses of the CONFIG_ADDRESS and CONFIG_DATA
registers are actually embedded within PCI I/O space. If the
CONFIG_ADDRESS register has been set incorrectly or the access
to either the CONFIG_ADDRESS or CONFIG_DATA register is not
1,2, or 4 bytes wide, the Raven will pass the access on to PCI as a
normal I/O Space transfer.
The CONFIG_ADDRESS register is located at offset $CF8 from the
bottom of PCI I/O space. The CONFIG_DATA register is located at
offset $CFC from the bottom of PCI I/O space. The Raven address
decode logic has been designed such that MSADD3 and MSOFF3
must be used for mapping to PCI Configuration (consequently I/O)
space. The MSADD3/MSOFF3 register group is initialized at reset
to allow PCI I/O access starting at address $80000000. The

2-23

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

powerup location (i.e., Little Endian disabled) of the
CONFIG_ADDRESS register is $80000CF8, and the
CONFIG_DATA register is located at $80000CFC.

The CONFIG_ADDRESS register must be prefilled with four fields:
the Register Number, the Function Number, the Device Number,
and the Bus Number.
The Register Number and the Function Number get passed along
to the PCI bus as portion of the lower address bits.
When performing a configuration cycle, Raven uses the upper 20
address bits as IDSEL lines. During the address phase of a
configuration cycle, only one of the upper address bits will be set.
The device that has its IDSEL connected to the address bit being
asserted will be selected for a configuration cycle. Raven decodes
the Device Number to determine which of the upper address lines
to assert. The decoding of the five-bit Device Number is show as
follows:.
Device Number

Address Bit

00000

AD31

00001 - 01010

All Zeros

01011

AD11

01100

AD12

(etc.)

11101

AD29

11110

AD30

11111

All Zeros

The Bus Number determines which bus is the target for the
configuration read cycle. Raven will always host PCI bus #0.
Accesses that are to be performed on the PCI bus connected to the
Raven must have zero programmed into the Bus Number. If the
configuration access is targeted for another PCI bus, then that bus
number should be programmed into the Bus Number field. The
Raven will detect a non-zero field and convert the transaction to a
Type 1 Configuration cycle.
2-24

Functional Description

Generating PCI Special Cycles

Raven supports the method stated in PCI Local Bus Specification
2.0 using Configuration Mechanism #1 to generate special cycles.
To prime Raven for a special cycle, the host processor must write a
32 bit value to the CONFIG_ADDRESS register. The contents of the
write are defined later in this chapter under the
CONFIG_ADDRESS register definition. After the write to
CONFIG_ADDRESS has been accomplished, the next write to the
CONFIG_DATA register causes the Raven to generate a special
cycle on the PCI bus. The write data is driven onto AD[31:0] during
the special cycleÕs data phase.
Generating PCI Interrupt Acknowledge Cycles
Performing a read from the PIACK register will initiate a single PCI
Interrupt Acknowledge cycle. Any single byte or combination of
bytes may be read from, and the actual byte enable pattern used
during the read will be passed on to the PCI bus. Upon completion
of the PCI interrupt acknowledge cycle, the Raven will present the
resulting vector information obtained from the PCI bus as read
data.

Endian Conversion
The Raven supports both Big- and Little-Endian data formats. Since
the PCI bus is inherently Little-Endian, conversion is necessary if all
MPC devices are configured for Big-Endian operation. The Raven
may be programmed to perform the Endian conversion described
below.
When MPC Devices are Big-Endian
When all MPC devices are operating in Big-Endian mode, all data
to/from the PCI bus must be swapped such that the PCI bus looks
big endian from the MPC busÕs perspective. This association is true
regardless of whether the transaction originates on the PCI bus or
the MPC bus. This is shown in Figure 2-7.

2-25

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

DL31-24
D7

PPC Bus

64-bit PCI

DL07-00

DL15-08

DL23-16

DL31-24

32-bit PCI

D0
AD07-00

DH31-24

AD15-08

DH23-16

AD23-16

DH15-08

AD31-24

DH07-00

AD07-00

DL23-16
D6

AD15-08

DL15-08
D5

AD23-16

DL07-00
D4

AD31-24

DH31-24
D3

AD39-32

DH23-16
D2

AD47-40

DH15-08
D1

AD55-48

AD63-56

DH07-00

PPC Bus

1916 9610

Figure 2-7. Big to Little Endian Data Swap
When MPC Devices are Little Endian
When all MPC devices are operating in little endian mode, the
originating address is modified to remove the exclusive-ORing
applied by MPC60x processors before being passed on to the PCI
bus. Note that no data swapping is performed. Address
modification happens to the originating address regardless of
whether the transaction originates from the PCI bus or the MPC
2-26

Functional Description

bus. The three low order address bits are exclusive-ORed with a
three-bit value that depends on the length of the operand, as shown
in Table 2-5.
Table 2-5. Address Modification for Little Endian Transfers
Data Length
(bytes)

Note

Address Modification

XOR with 111

XOR with 110

XOR with 100

no change

The only legal data lengths supported in little endian
mode are 1, 2, 4, or 8-byte aligned transfers.

Since this method has some difficulties dealing with unaligned PCIoriginated transfers, the Raven MPC master will break up all
unaligned PCI transfers into multiple aligned PCI transfers into
multiple aligned transfers on the MPC bus.
Raven Registers
The Raven registers are not sensitive to changes in Big-Endian and
Little-Endian mode. With respect to the MPC bus (but not always
the address internal to the processor), the MPC registers are always
represented in Big-Endian mode. This means that the processorÕs
internal view of the MPC registers will appear different depending
on which mode the processor is operating in.
With respect with the PCI bus, the RavenMPIC registers and the
configuration registers are always represented in Little-Endian
mode.
The CONFIG_ADDRESS and CONFIG_DATA registers are
actually represented in PCI space to the processor and are subject to
the Endian functions. For example, the powerup location of the

2-27

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

CONFIG_ADDRESS register with respect to the MPC bus is
$80000cf8 when Raven is in Big-Endian mode. When Raven is
switched to Little-Endian mode, the CONFIG_ADDRESS register
with respect to the MPC bus is $80000cfc. Note that in both cases the
address generated internal to the processor will be $80000cf8.

The contents of the CONFIG_ADDRESS register are not subject to
the Endian function.
The data associated with PIACK accesses is subject to the Endian
swapping function. The address of a PIACK cycle is undefined,
therefore address modification during Little-Endian mode is not an
issue.

Error Handling
The Raven will be capable of detecting and reporting the following
errors to one or more MPC masters:
❏

MPC address bus time-out

❏

PCI master signalled master abort

❏

PCI master received target abort

❏

PCI parity error

❏

PCI system error

Each of these error conditions will cause an error status bit to be set
in the MPC Error Status Register. If a second error is detected while
any of the error bits is set, the OVFL bit is asserted, but none of the
error bits are changed. Each bit in the MPC Error Status Register
may be cleared by writing a 1 to it; writing a 0 to it has no effect.
New error bits may be set only when all previous error bits have
been cleared.
When any bit in the MPC Error Status register is set, the Raven will
attempt to latch as much information as possible about the error in
the MPC Error Address and Attribute Registers. Information is
saved as follows:

2-28

Functional Description

2
Error Status

Error Address and Attributes

MATO

From MPC bus

SMA

From PCI bus

RTA

From PCI bus

PERR

Invalid

SERR

Invalid

Each MERST error bit may be programmed to generate a machine
check and/or a standard interrupt. The error response is
programmed through the MPC Error Enable Register on a source
by source basis. When a machine check is enabled, either the MID
field in the MPC Error Attribute Register or the DFLT bit in the
MEREN Register determine the master to which the machine check
is directed. For errors in which the master who originated the
transaction can be determined, the MID field is used, provided the
MID is%00 (processor 0), %01 (processor 1), or %10 (processor 2).
For errors not associated with a particular MPC master, or
associated with masters other than processor 0,1 or 2, the DFLT bit
is used. One example of an error condition which cannot be
associated with a particular MPC master would be a PCI system
error.

Transaction Ordering
Raven supports transaction ordering with an optional FIFO
flushing option. The FLBRD (Flush Before Read) bit within the
GCSR register controls the flushing of PCI write posted data when
performing MPC-originated read transactions.
When the FLBRD bit is set, Raven will handle read transactions
originating from the MPC bus in the following manner:
❏

Write posted transactions originating from the processor bus
are flushed by the nature of the FIFO architecture. The Raven

2-29

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

will hold the processor with wait states until the PCI bound
FIFO is empty.

2
❏

2-30

Write posted transactions originated from the PCI bus are
flushed whenever the PCI slave has accepted a write-posted
transaction and the transaction has not completed on the
MPC bus.

2Raven PCI Host Bridge & Multi-Processor Interrupt
Controller Chip
Registers

Registers

This chapter provides a detailed description of all Raven registers.
These registers are broken into two groups: the MPC Registers and
the PCI Configuration Registers. The MPC Registers are accessible
only from the MPC bus using any valid transfer size. The PCI
Configuration Registers reside in PCI configuration space. They are
accessible from the MPC bus through the Raven. The MPC
Registers are described first; the PCI Configuration Registers are
described next. A complete discussion of the RavenMPIC registers
can be found later in this chapter.
The following conventions are used in the Raven register charts:
❏

Read Only field.

❏

R/W

Read/Write field.

❏

Writing a ONE to this field sets this field.

❏

Writing a ONE to this field clears this field.

MPC Registers
The Raven MPC register map is shown in Table 2-6.

Table 2-6. Raven MPC Register Map
Bit --->
$FEFF0000

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
VENID

$FEFF0004
$FEFF0008
$FEFF000C

DEVID
REVID

GCSR

FEAT
MARB

$FEFF0010

PADJ

$FEFF0014
$FEFF0018
$FEFF001C
$FEFF0020

MEREN

2-31

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Table 2-6. Raven MPC Register Map (Continued)

2
Bit --->

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

$FEFF0024

MERST

$FEFF0028

MERAD

$FEFF002C

MERAT

$FEFF0030

PIACK

$FEFF0034
$FEFF0038
$FEFF003C
$FEFF0040
$FEFF0044

MSADD0
MSOFF0

$FEFF0048
$FEFF004C

MSADD1
MSOFF1

$FEFF0050
$FEFF0054

MSATT1
MSADD2

MSOFF2

$FEFF0058
$FEFF005C

MSATT0

MSATT2
MSADD3

MSOFF3

MSATT3

$FEFF0060
$FEFF0064
$FFEF0068
$FEFF006C
$FEFF0070

GPREG0(Upper)

$FEFF0074

GPREG0(Lower)

$FEFF078

GPREG1(Upper)

$FEFF07C

GPREG1(Lower)

2-32

Registers

Vendor ID/Device ID Registers

Address
Bit

$FEFF0000
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

VENID

DEVID

$1057

$4801

Operation
Reset

VENID

Vendor ID. This register identiÞes the manufacturer
of the device. This identiÞer is allocated by the PCI
SIG to ensure uniqueness. $1057 has been assigned
to Motorola. This register is duplicated in the PCI
ConÞguration Registers.

DEVID

Device ID. This register identiÞes this particular
device. The Raven will always return $4801. This
register is duplicated in the PCI ConÞguration
Registers.

Revision ID Register
Address
Bit

$FEFF0004
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name
Operation
Reset

REVID
R

$00

$02

$00

REVID

Revision ID. This register identiÞes the Raven
revision level. This register is duplicated in the PCI
ConÞguration Registers.

2-33

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

General Control-Status/Feature Registers
Address
Bit

$FEFF0008
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

GCSR

FEAT

2-34

0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Reset

EXT00 R
EXT01 R
EXT02 R
EXT03 R
EXT04 R
EXT05 R
EXT06 R
EXT07 R
EXT08 R
EXT09 R
EXT10 R
EXT11 R
EXT12 R
EXT13 R
EXT14 R
R
MID0
R
MID1
R
R
R
R
MPIC
R
MARB R
P64
R
R/W
MBT0
MBT1
R/W
FLBRD R/W
BHOG R/W
R
R
R
R/W

LEND
Operation

LEND

Endian Select. If set, the MPC bus is operating in
little endian mode. The MPC address will be
modiÞed as described in the section When MPC
Devices are Little Endian. When LEND is clear, the
MPC bus is operating in big endian mode, and all
data to/from PCI is swapped as described in the
section When MPC Devices are Big-Endian.

FLBRD

Flush Before Read. If set, the Raven will guarantee
that all PCI initiated posted write transactions will
be completed before any MPC initiated read
transactions will be allowed to complete. When
FLBRD is clear, there will be no correlation between
these transaction types and their order of
completion. Please refer to the section on PCI/MPC
Contention Handling for more information.

BHOG

Bus Hog. If set, the Raven MPC master will operate
in the Bus Hog mode. Bus Hog mode means the
MPC master will continually request the MPC bus
for the entire duration of each PCI transfer. If Bus
Hog is not enabled, the MPC master will request the
bus in a normal manner. Please refer to the section
on MPC Master for more information.

Registers

MBTx

MPC Bus Time-out. This Þeld speciÞes the MPC bus
time-out length. The time-out length is encoded as
follows:
MBT

Time Out Length

256 µsec

64 µsec

8 µsec

disabled

P64

64-bit PCI Mode Enable. If set, the Raven is
connected to a 64-bit PCI bus. This bit is set if
REQ64* is asserted on the rising edge of RESET*.

MARB

MPC Arbiter Enable. If set, the Raven internal MPC
Arbiter is enabled. This bit is set if CPUID is %111 on
the rising edge of RESET*.

MPIC

Multi-Processor Interrupt Controller Enable. If set,
the Raven internal MPIC interrupt controller is
enabled. This bit is set if EXT15 is high on the rising
edge of RESET*. If cleared, Raven detected errors
will be passed on to processor 0 INT pin.

MIDx

Master ID. This Þeld is encoded as shown below to
indicate who is currently the MPC bus master. When
the internal MPC arbiter is enabled (MARB is set),
these bits are controlled by the internal arbiter.
When the internal arbiter is disabled (MARB is clear)
these bits reßect the status of the CPUID pins. In a
multi- processor environment, these bits allow
software to determine on which processor it is currently
running. The internal MPC arbiter encodes this Þeld
as follows:

FEAT

MID

Current MPC Data Bus Master

device on ABG0*

device on ABG1*

device on ABG2

Raven

Feature Register. Each bit in this register reßects the
state of one of the external interrupt input pins on
the rising edge of RESET*. This register may be used
to report hardware conÞguration parameters to
2-35

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

system software.

2-36

Registers

MPC Arbiter Control Register

Address
Bit

$FEFF000C
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MARB

$00

DEFM0
DEFM1

BAMD
GLMD
PKMD
PKEN
BREN0
BREN1
BREN2

1
1
0
0
1
0
0
0
1
1
1
0
0
0
0
0

Reset

R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R

Operation

This register is not used by the MVME2300 series.
Prescaler Adjust Register
Address
Bit

$FEFF0010
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name
Operation
Reset

PADJ
R

R/W

$00

$B4

PADJ

Prescaler Adjust. This register is used to specify a
scale factor for the prescaler to ensure that the time
base for the bus timer is 1 MHz. The scale factor is
calculated as follows:
PADJ = 256 - Clk,
where Clk is the frequency of the CLK input in MHz.
This register should be written with the value $BE
indicating a 66MHz MPC bus.

2-37

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

MPC Error Enable Register
Address
Bit

$FEFF0020
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

Reset

$00

DFLT

RTAI
R/W 0
SMAI
R/W 0
SERRI R/W 0
PERRI R/W 0
R
0
MATOII R/W 0
R
0
R
0
R/W 0
RTAM
SMAM
R/W 0
SERRM R/W 0
PERRM R/W 0
R
0
MATOM R/W 0
DFLT
R/W 0
R
0

Operation

MEREN

Default MPC Master ID. This bit determines which
MCHK* pin will be asserted for error conditions in
which the MPC master ID can not be determined or
the Raven was the MPC master. For example, in
event of a PCI parity error for a transaction in which
the RavenÕs PCI master was not involved, the MPC
master ID can not be determined. When DFLT is set,
MCHK1* is used. When DFLT is clear, MCHK0* will
be used.

MATOM MPC Address Bus Time-out Machine Check
Enable. When this bit is set, the MATO bit in the
MERST register will be used to assert the MCHK
output to the current address bus master. When this
bit is clear, MCHK will not be asserted.

2-38

PERRM

PCI Parity Error Machine Check Enable. When this
bit is set, the PERR bit in the MERST register will be
used to assert the MCHK output to bus master 0.
When this bit is clear, MCHK will not be asserted.

SERRM

PCI System Error Machine Check Enable. When
this bit is set, the SERR bit in the MERST register will
be used to assert the MCHK output to bus master 0.
When this bit is clear, MCHK will not be asserted.

Registers

SMAM

PCI Signalled Master Abort Machine Check
Enable. When this bit is set, the SMA bit in the
MERST register will be used to assert the MCHK
output to the bus master which initiated the
transaction. When this bit is clear, MCHK will not be
asserted.

RTAM

PCI Master Received Target Abort Machine Check
Enable.When this bit is set, the RTA bit in the
MERST register will be used to assert the MCHK
output to the bus master which initiated the
transaction. When this bit is clear, MCHK will not be
asserted.

MATOI

MPC Address Bus Time-out Interrupt
Enable.When this bit is set, the MATO bit in the
MERST register will be used to assert an interrupt
through the MPIC interrupt controller. When this bit
is clear, no interrupt will be asserted.

PERRI

PCI Parity Error Interrupt Enable.When this bit is
set, the PERR bit in the MERST register will be used
to assert an interrupt through the MPIC interrupt
controller. When this bit is clear, no interrupt will be
asserted.

SERRI

PCI System Error Interrupt Enable.When this bit is
set, the PERR bit in the MERST register will be used
to assert an interrupt through the MPIC interrupt
controller. When this bit is clear, no interrupt will be
asserted.

SMAI

PCI Master Signalled Master Abort Interrupt
Enable.When this bit is set, the SMA bit in the
MERST register will be used to assert an interrupt
through the MPIC interrupt controller. When this bit
is clear, no interrupt will be asserted.

2-39

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

RTAI

PCI Master Received Target Abort Interrupt
Enable.When this bit is set, the RTA bit in the
MERST register will be used to assert an interrupt
through the MPIC interrupt controller. When this bit
is clear, no interrupt will be asserted.

MPC Error Status Register
Address
Bit

$FEFF0024
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MERST

2-40

$00

0
0
0
0
0
0
0
0

Reset

RTA
R/C
SMA
R/C
SERR R/C
PERR R/C
R
MATO R/C
R
R/C

OVF

Operation

OVF

Error Status Overßow. This bit is set when any error
is detected and any of the error status bits are
already set. It may be cleared by writing a 1 to it;
writing a 0 to it has no effect.

MATO

MPC Address Bus Time-out. This bit is set when the
MPC address bus timer times out. It may be cleared
by writing it to a 1; writing it to a 0 has no effect.
When the MATOM bit in the MEREN register is set,
the assertion of this bit will assert MCHK to the
master designated by the MID Þeld in the MERAT
register. When the MATOI bit in the MEREN register
is set, the assertion of this bit will assert an interrupt
through the MPIC interrupt controller.

PERR

PCI Parity Error. This bit is set when the PCI PERR*
pin is asserted. It may be cleared by writing it to a 1;
writing it to a 0 has no effect. When the PERRM bit
in the MEREN register is set, the assertion of this bit

Registers

will assert MCHK to the master designated by the
DFLT bit in the MERAT register. When the PERRI bit
in the MEREN register is set, the assertion of this bit
will assert an interrupt through the MPIC interrupt
controller.
SERR

PCI System Error. This bit is set when the PCI SERR*
pin is asserted. It may be cleared by writing it to a 1;
writing it to a 0 has no effect. When the SERRM bit
in the MEREN register is set, the assertion of this bit
will assert MCHK to the master designated by the
DFLT bit in the MERAT register. When the SERRI bit
in the MEREN register is set, the assertion of this bit
will assert an interrupt through the MPIC interrupt
controller.

SMA

PCI Master Signalled Master Abort. This bit is set
when the PCI master signals master abort to
terminate a PCI transaction. It may be cleared by
writing it to a 1; writing it to a 0 has no effect. When
the SMAM bit in the MEREN register is set, the
assertion of this bit will assert MCHK to the master
designated by the MID Þeld in the MERAT register.
When the SMAI bit in the MEREN register is set, the
assertion of this bit will assert an interrupt through
the MPIC interrupt controller.

RTA

PCI Master Received Target Abort. This bit is set
when the PCI master receives target abort to
terminate a PCI transaction. It may be cleared by
writing it to a 1; writing it to a 0 has no effect. When
the RTAM bit in the MEREN register is set, the
assertion of this bit will assert MCHK to the master
designated by the MID Þeld in the MERAT register.
When the RTAI bit in the MEREN register is set, the
assertion of this bit will assert an interrupt through
the MPIC interrupt controller.

2-41

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

MPC Error Address Register
Address
Bit
Name
Operation
Reset

$FEFF0028
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
MERAD
R
$00000000

MERAD MPC Error Address. This register captures the MPC
address when the MATO bit is set in the MERST
register. It captures the PCI address when the SMA
or RTA bits are set in the MERST register. Its contents
are not deÞned when the PERR or SERR bits are set
in the MERST register.

2-42

Registers

MPC Error Attribute Register - MERAT

If the PERR or SERR bits are set in the MERST register, the contents
of the MERAT register are zero. If the MATO bit is set the register
is defined by the following figure:
Address
Bit

$FEFF002C
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

$00

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Reset

TT4
R
TT3
R
TT2
R
TT1
R
TT0
R
TSIZ2 R
TSIZ1 R
TSIZ0 R
TBST R
R
R
R
MID0 R
MID1 R
R
R

Operation

MERAT

MIDx

MPC Master ID. This Þeld contains the ID of the
MPC master which originated the transfer in which
the error occurred. The encoding scheme is identical
to that used in the GCSR register.

TBST

Transfer Burst. This bit is set when the transfer in
which the error occurred was a burst transfer.

TSIZx

Transfer Size. This Þeld contains the transfer size of
the MPC transfer in which the error occurred.

TTx

Transfer Type. This Þeld contains the transfer type
of the MPC transfer in which the error occurred.

2-43

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

If the SMA or RTA bit are set the register is defined by the following
figure:

2
Address
Bit

$FEFF002C
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MERAT

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

$00

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Reset

BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
COMM0
COMM1
COMM2
COMM3
MID0
MID1

Operation

Write Post Completion. This bit is set when the PCI
master detects an error while completing a write
post transfer.

MIDx

MPC Master ID. This Þeld contains the ID of the
MPC master which originated the transfer in which
the error occurred. The encoding scheme is identical
to that used in the GCSR register

COMMx PCI Command. This Þeld contains the PCI
command of the PCI transfer in which the error
occurred.
BYTEx

2-44

PCI Byte Enable. This Þeld contains the PCI byte
enables of the PCI transfer in which the error
occurred. A set bit designates a selected byte.

Registers

PCI Interrupt Acknowledge Register
Address
Bit

2
$FEFF0030

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

PIACK

Operation

Reset

$00000000

PIACK

PCI Interrupt Acknowledge. Performing a read
from this register will initiate a single PCI Interrupt
Acknowledge cycle. Any single byte or combination
of bytes may be read from, and the actual byte
enable pattern used during the read will be passed
on to the PCI bus. Upon completion of the PCI
interrupt acknowledge cycle, the Raven will present
the resulting vector information obtained from the
PCI bus as read data.

2-45

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2-46

2Raven PCI Host Bridge & Multi-Processor Interrupt
Controller Chip
Registers

0Registers

MPC Slave Address (0,1 and 2) Registers
Address

Bit

MSADD0 - $FEFF0040
MSADD1 - $FEFF0048
MSADD2 - $FEFF0050
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MSADDx
START

END

R/W

$0000

Operation
Reset

To initiate a PCI cycle from the MPC bus, the MPC address must be
greater than or equal to the START field and less than or equal to
the END field.
START

Start Address. This Þeld determines the start
address of a particular memory area on the MPC bus
which will be used to access PCI bus resources. The
value of this Þeld will be compared with the upper
16 bits of the incoming MPC address.

END

End Address. This Þeld determines the end address
of a particular memory area on the MPC bus which
will be used to access PCI bus resources. The value
of this Þeld will be compared with the upper 16 bits
of the incoming MPC address.

2-47

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

MPC Slave Address (3) Register
Address
Bit

MSADD3 - $FEFF0058
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MSADD3
START

END

R/W

$8000

$8080

Operation
Reset

MSADD3, MSOFF3 and MSATT3 represent the only register group
which can be used to initiate access to the PCI Configuration
Address ($80000CF8) and Configuration Data ($80000CFC)
registers. Note that this implies that MSxxx3 also represents the
generation of PCI Special Cycles. The power up default values of
MSADD3, MSOFF3 and MSATT3 are set to allow access to PCI
configuration space without MPC register initialization. Please see
the description of the MSOFF3/MSATT3 Registers for additional
information.
To initiate a PCI cycle from the MPC bus the MPC address must be
greater than or equal to the START field and less than or equal to
the END field.

2-48

START

END

Registers

MPC Slave Offset/Attribute (0,1 and 2) Registers
Address

Bit

MSOFF0/MSATT0 - $FEFF0044
MSOFF1/MSATT1 - $FEFF004C
MSOFF2/MSATT2 - $FEFF0054
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MSOFFx

MSATTx

$0000

$00

0
0
0
0
0
0
0
0

Reset

R/W

IOM
R/W
MEM
R/W
R
R
WPEN R/W
R
R/W
R/W

WEN
REN

Operation

MSOFFx MPC Slave Offset. This register contains a 16-bit
offset that is added to the upper 16 bits of the MPC
address to determine the PCI address used for
transfers from the MPC bus to PCI. This offset allows
PCI resources to reside at addresses that would not
normally be visible from the MPC bus.
REN

Read Enable. If set, the corresponding MPC slave is
enabled for read transactions.

WEN

Write Enable. If set, the corresponding MPC slave is
enabled for write transactions.

WPEN

Write Post Enable. If set, write posting is enabled for
the corresponding MPC slave.

MEM

PCI Memory Cycle. If set, the corresponding MPC
slave will generate transfers to or from PCI memory
space. When clear, the corresponding MPC slave
will generate transfers to or from PCI I/O space
using the addressing mode deÞned by the IOM Þeld.

2-49

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

PCI I/O Mode. If set, the corresponding MPC slave
will generate PCI I/O cycles using spread
addressing as deÞned in the section on Generating
PCI Memory and I/O Cycles. When clear, the
corresponding MPC slave will generate PCI I/O
cycles using contiguous addressing. This Þeld only
has meaning when the MEM bit is clear.

IOM

MPC Slave Offset/Attribute (3) Registers
Address
Bit

MSOFF3/MSATT3 - $FEFF005C
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

MSOFF3

MSATT3

$8000

$00

0
0
0
0
0
0
1
1

Reset

R/W

IOM
R/W
R
R
R
WPEN R/W
R
R/W
R/W

WEN
REN

Operation

MSOFF3 MPC Slave Offset. This register contains a 16-bit
offset that is added to the upper 16 bits of the MPC
address to determine the PCI address used for
transfers from the MPC bus to PCI. This offset allows
PCI resources to reside at addresses that would not
normally be visible from the MPC bus. It is
initialized to $8000 to facilitate a zero-based access to
PCI space.

2-50

REN

Read Enable. If set, the corresponding MPC slave is
enabled for read transactions.

WEN

Write Enable. If set, the corresponding MPC slave is
enabled for write transactions.

WPEN

Write Post Enable. If set, write posting is enabled for
the corresponding MPC slave.

Registers

IOM

General Purpose Registers
Address

Bit

GPREG0 (Upper) - $FEFF0070
GPREG0 (Lower) - $FEFF0074
GPREG1 (Upper) - $FEFF0078
GPREG1 (Lower) - $FEFF007C
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

GPREGx

Operation

R/W

Reset

$00000000

These general purpose read/write registers are provided for interprocess message passing or general purpose storage. They do not
control any hardware.

PCI Registers
The PCI Configuration Registers are compliant with the
configuration register set described in the PCI Local Bus
Specification, Revision 2.0. The CONFIG_ADDRESS and
CONFIG_DATA registers described in this section are accessed
within PCI I/O space.
All write operations to reserved registers will be treated as no-ops.
That is, the access will be completed normally on the bus and the
data will be discarded. Read accesses to reserved or
unimplemented registers will be completed normally and a data
value of 0 returned.

2-51

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

The Raven PCI Configuration Register map is shown in Table 2-7.
The Raven PCI I/O Register map is shown in Table 2-8.

Table 2-7. Raven PCI Configuration Register Map
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

<--- Bit

DEVID

VENID

$00

PSTAT

PCOMM

$04

CLASS

REVID

$08
$0C

IOBASE

$10

MEMBASE

$14
$18 - $7F

PSADD0
PSOFF0

$80
PSATT0

PSADD1
PSOFF1

$88
PSATT1

PSADD2
PSOFF2

$8C
$90

PSATT2
PSADD3

PSOFF3

$84

$94
$98

PSATT3

$9C

Table 2-8. Raven PCI I/O Register Map
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

<--- Bit

CONFIG_ADDRESS

$CF8

CONFIG_DATA

$CFC

2-52

Registers

Vendor ID/ Device ID Registers
Offset
Bit
Name

$00
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
DEVID

VENID

$4801

$1057

Operation
Reset

VENID

DEVID

Device ID. This register identiÞes the particular
device. The Raven will always return $4801. This
register is duplicated in the MPC Registers.

PCI Command/ Status Registers
Offset
Bit
Name

$04
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
PSTAT

PCOMM
IOSP
MEMSP
MSTR

PERR

SERR

FAST
DPAR
SELTIM0
SELTIM1
SIGTA
RCVTA
RCVMA
SIGSE
RCVPE
Operation

R/W
R/W
R/W
R
R
R
R/W
R
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/C
R
R
R/C
R/C
R/C
R/C
R/C

Reset

0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0

2-53

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2-54

IOSP

IO Space Enable. If set, the Raven will respond to
PCI I/O accesses when appropriate. If cleared, the
Raven will not respond to PCI I/O space accesses.

MEMSP

Memory Space Enable. If set, the Raven will
respond to PCI memory space accesses when
appropriate. If cleared, the Raven will not respond to
PCI memory space accesses.

MSTR

Bus Master Enable. If set, the Raven may act as a
master on PCI. If cleared, the Raven may not act as a
PCI master.

PERR

Parity Error Response. If set, the Raven will check
parity on all PCI transfers. If cleared, the Raven will
ignore any parity errors that it detects and continue
normal operation.

SERR

System Error Enable. This bit enables the SERR*
output pin. If clear, the Raven will never drive
SERR*. If set, the Raven will drive SERR* active
when a system error is detected.

FAST

Fast Back-to-Back Capable. This bit indicates that
the Raven is capable of accepting fast back-to-back
transactions with different targets.

DPAR

Data Parity Detected. This bit is set when three
conditions are met: 1) the Raven asserted PERR*
itself or observed PERR* asserted; 2) the Raven was
the PCI master for the transfer in which the error
occurred; 3) the PERR bit in the PCI Command
Register is set. This bit is cleared by writing it to 1;
writing a 0 has no effect.

SELTIM

DEVSEL Timing. This Þeld indicates that the Raven
will always assert DEVSEL* as a ÔmediumÕ
responder.

Registers

SIGTA

Signalled Target Abort. This bit is set by the PCI
slave whenever it terminates a transaction with a
target-abort. It is cleared by writing it to 1; writing a
0 has no effect.

RCVTA

Received Target Abort. This bit is set by the PCI
master whenever its transaction is terminated by a
target-abort. It is cleared by writing it to 1; writing a
0 has no effect.

RCVMA Received Master Abort. This bit is set by the PCI
master whenever its transaction (except for Special
Cycles) is terminated by a master-abort. It is cleared
by writing it to 1; writing a 0 has no effect.
SIGSE

Signaled System Error. This bit is set whenever the
Raven asserts SERR*. It is cleared by writing it to 1;
writing a 0 has no effect.

RCVPE

Detected Parity Error. This bit is set whenever the
Raven detects a parity error, even if parity error
checking is disabled (see bit PERR in the PCI
Command Register). It is cleared by writing it to 1;
writing a 0 has no effect.

Revision ID/ Class Code Registers
Offset
Bit

$08
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name
Operation
Reset

REVID

CLASS

REVID

$060000

$02

Revision ID. This register identiÞes the Raven
revision level. This register is duplicated in the MPC
Registers.

2-55

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

CLASS

Class Code. This register identiÞes Raven as the
following:
Base Class Code

$06

PCI Bridge Device

Subclass Code

$00

PCI Host Bridge

Program Class Code $00

Not Used

I/O Base Register
Offset
Bit

$10
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

IOBASE

Reset

R/W

$0000

1
0

Operation

IO/MEM R
RES
R

IOBA

This register controls the mapping of the MPIC control registers in
PCI I/O space.
IO/MEM IO Space Indicator. This bit is hard-wired to a logic
one to indicate PCI I/O space.

2-56

RES

Reserved. This bit is hard-wired to zero.

IOBA

I/O Base Address. These bits deÞne the I/O space
base address of the MPIC control registers. The
IOBASE decoder is disabled when the IOBASE
value is zero.

Registers

Memory Base Register
Offset
Bit

2
$14

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

MEMBASE

$0000

0
0
0
0

Reset

R/W

R
R
R
R

Operation

IO/MEM
MTYP0
MTYP1
PRE

MEMBA

This register controls the mapping of the MPIC control registers in
PCI memory space.
IO/MEM IO Space Indicator. This bit is hard-wired to a logic
zero to indicate PCI memory space.
MTYPx

Memory Type. These bits are hard-wired to zero to
indicate that the MPIC registers can be located
anywhere in the 32-bit address space

PRE

Prefetch. This bit is hard-wired to zero to indicate
that the MPIC registers are not prefetchable.

MEMBA Memory Base Address. These bits deÞne the
memory space base address of the MPIC control
registers. The MBASE decoder is disabled when the
MBASE value is zero.

2-57

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

PCI Slave Address (0,1,2 and 3) Registers
Offset

Bit

PSADD0 - $80
PSADD1 - $88
PSADD2 - $90
PSADD3 - $98
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

PSADDx
START

END

R/W

$0000

Operation
Reset

To initiate an MPC cycle from the PCI bus the PCI address must be
greater than or equal to the START field and less than or equal to
the END field.

2-58

START

Start Address. This Þeld determines the start
address of a particular memory area on the PCI bus
which will be used to access MPC bus resources. The
value of this Þeld will be compared with the upper
16 bits of the incoming PCI address.

END

End Address. This Þeld determines the end address
of a particular memory area on the PCI bus which
will be used to access MPC bus resources. The value
of this Þeld will be compared with the upper 16 bits
of the incoming PCI address.

Registers

PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
Offset

Bit

PSATT0/PSOFF0 - $84
PSATT1/PSOFF1 - $8C
PSATT2/PSOFF2 - $94
PSATT3/PSOFF3 - $9C
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

PSOFFx

PSATTx

R/W

R/W
R/W
R
R
R/W
R/W
R/W
R/w

$0000

$00

0
0
0
0
0
0
0
0

Reset

INV
GBL

RAEN
WPEN
WEN
REN

Operation

INV

Invalidate Enable. If set, the MPC master will issue
a transfer type code which speciÞes the current
transaction should cause an invalidate for each MPC
transaction originated by the corresponding PCI
slave. The transfer type codes generated are shown
in Table 2-3.

GBL

Global Enable. If set, the MPC master will assert the
GBL* pin for each MPC transaction originated by the
corresponding PCI slave.

RAEN

Read Ahead Enable. If set, read ahead is enabled for
the corresponding PCI slave.

WPEN

Write Post Enable. If set, write posting is enabled for
the corresponding PCI slave.

WEN

Write Enable. If set, the corresponding PCI slave is
enabled for write transactions.

REN

Read Enable. If set, the corresponding PCI slave is
enabled for read transactions.

PSOFFx

PCI Slave Offset. This register contains a 16-bit
offset that is added to the upper 16 bits of the PCI
address to determine the MPC address used for
transfers from PCI to the MPC bus. This offset allows
MPC resources to reside at addresses that would not

2-59

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

normally be visible from PCI.

CONFIG_ADDRESS Register
The description of the CONFIG_ADDRESS register is presented in
three perspectives: from the PCI bus, from the MPC Bus in Big
Endian mode, and from the MPC bus in Little Endian mode. Note
that the view from the PCI bus is purely conceptual, since there is
no way to access the CONFIG_ADDRESS register from the PCI bus.
Conceptual perspective from the PCI bus:
Offset
Bit
Name

$CFB
$CFA
$CF9
$CF8
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
CONFIG_ADDRESS
BUS
DEV
FUN
REG
R/W

R/W

$00

R
R

0
0

Reset

R/W

Operation

Perspective from the MPC bus in Big Endian mode:
Offset
Bit (DH)
Name

$CF8

$CF9
$CFA
$CFB
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
CONFIG_ADDRESS
REG
DEV
FUN
BUS

$00

R/W

$00

0
0

Reset

R/W

R/W
R
R

Operation

$00

Perspective from the MPC bus in Little Endian mode:
Offset
Bit (DL)
Name

$CFC

$CFD
$CFE
$CFF
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
CONFIG_ADDRESS
BUS
DEV
FUN
REG

2-60

Registers

$CFC
R

$CFD
R/W

$CFE
R/W
R/W

$CFF
R/W

$00

2
R
R

$00

0
0

Reset

R/W

Offset
Operation

2-61

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

The register fields are defined as follows:

REG

ConÞguration Cycles: IdentiÞes a target double word within
a targetÕs conÞguration space. This Þeld is copied to the PCI
AD bus during the address phase of a ConÞguration cycle.
Special Cycles: This Þeld must be written with all zeros.
FUN

Function Number.

ConÞguration Cycles: IdentiÞes a function number within a
targetÕs conÞguration space. This Þeld is copied to the PCI
AD bus during the address phase of a ConÞguration cycle.
Special Cycles: This Þeld must be written with all ones.
DEV

Device Number.

ConÞguration Cycles: IdentiÞes a targetÕs physical PCI
device number. Refer to the section on Generating PCI Cycles
for a description of how this Þeld is encoded.
Special Cycles: This Þeld must be written with all ones.
BUS

Bus Number.

ConÞguration Cycles: IdentiÞes a targeted bus number. If
written with all zeros, a Type 0 ConÞguration Cycle will be
generated. If written with any value other than all zeros,
then a Type 1 ConÞguration Cycle will be generated.
Special Cycles: IdentiÞes a targeted bus number. If written
with all zeros, a Special Cycle will be generated. If written
with any value other than all zeros, then a Special Cycle
translated into a Type 1 ConÞguration Cycle will be
generated.
EN

Enable.
ConÞguration Cycles: Writing a one to this bit enables
CONFIG_DATA to ConÞguration Cycle translation. If this
bit is a zero, subsequent accesses to CONFIG_DATA will be
passed though as I/O Cycles.
Special Cycles: Writing a one to this bit enables
CONFIG_DATA to Special Cycle translation. If this bit is a
zero, subsequent accesses to CONFIG_DATA will be passed
though as I/O Cycles.

2-62

Registers

CONFIG_DATA Register
The description of the CONFIG_DATA register is also presented in
three perspectives; from the PCI bus, from the MPC Bus in Big
Endian mode, and from the MPC bus in Little Endian mode. Note
that the view from the PCI bus is purely conceptual, since there is
no way to access the CONFIG_DATA register from the PCI bus.
Conceptual perspective from the PCI bus:
Offset
Bit

$CFF

$CFE

$CFD

$CFC

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

CONFIG_DATA
Data ‘D’

Data ‘C’

Data ‘B’

Data ‘A’

Operation

R/W

Reset

n/a

Perspective from the MPC bus in Big Endian mode:
Offset
Bit (DL)

$CFC

$CFD

$CFE

$CFF

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

CONFIG_DATA
Data ‘A’

Data ‘B’

Data ‘C’

Data ‘D’

Operation

R/W

Reset

n/a

Perspective from the MPC bus in Little Endian mode:
Offset
Bit (DH)

$CF8

$CF9

$CFA

$CFB

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Name

CONFIG_DATA
Data ‘D’

Data ‘C’

Data ‘B’

Data ‘A’

Operation

R/W

Reset

n/a

2-63

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2-64

2Raven PCI Host Bridge & Multi-Processor Interrupt
Controller Chip
Raven Interrupt Controller Implementation

Raven Interrupt Controller Implementation

Introduction
This section describes the Raven Interrupt Controller in general.
The Raven Interrupt Controller (RavenMPIC) Features
❏

MPIC programming model

❏

Support for two processors

❏

Support for 16 external interrupts

❏

Support for 15 programmable Interrupt & Processor Task
priority levels

❏

Support for the connection of an external 8259 for ISA/AT
compatibility

❏

Distributed interrupt delivery for external I/O interrupts

❏

Direct/Multicast interrupt delivery for Interprocessor and
timer interrupts

❏

Four Interprocessor Interrupt sources

❏

Four timers

❏

Processor initialization control

Architecture
The Raven PCI Slave implements two address decoders for placing
the RavenMPIC registers in PCI IO or PCI Memory space. Access to
these registers require MPC and PCI bus mastership. These
accesses include interrupt and timer initialization and interrupt
vector reads.
The RavenMPIC receives interrupt inputs from 16 external sources,
four interprocessor sources, four timer sources, and one Raven
internal error detection source. The externally sourced interrupts

2-65

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

1 through 15 have two modes of activation; low level or active high
positive edge. External interrupt 0 can be either level or edge
activated with either polarity. The Interprocessor and timers
interrupts are event activated.

CSR’s Readability
Unless explicitly specified, all registers are readable and return the
last value written. The exceptions are the IPI dispatch registers and
the EOI registers which return zeros on reads, the interrupt source
ACT bit which returns current interrupt source status, the interrupt
acknowledge register which returns the vector of the highest
priority interrupt which is currently pending, and reserved bits
which returns zeros. The interrupt acknowledge register is also the
only register which exhibits any read side-effects.
Interrupt Source Priority
Each interrupt source is assigned a priority value in the range from
0 to 15 where 15 is the highest. In order for delivery of an interrupt
to take place the priority of the source must be greater than that of
the destination processor. Therefore setting a source priority to zero
inhibits that interrupt.
Processor’s Current Task Priority
Each processor has a task priority register which is set by system
software to indicate the relative importance of the task running on
that processor. The processor will not receive interrupts with a
priority level equal to or lower than its current task priority.
Therefore setting the current task priority to 15 prohibits the
delivery of all interrupts to the associated processor.
Nesting of Interrupt Events
A processor is guaranteed never to have an in-service interrupt
preempted by an equal or lower priority source. An interrupt is
considered to be in service from the time its vector is returned

2-66

Raven Interrupt Controller Implementation

during an interrupt acknowledge cycle until an EOI is received for
that interrupt. The EOI cycle indicates the end of processing for the
highest priority in-service interrupt.
Spurious Vector Generation
Under certain circumstances the RavenMPIC will not have a valid
vector to return to the processor during an interrupt acknowledge
cycle. In these cases the spurious vector from the spurious vector
register will be returned. The following cases would cause a
spurious vector fetch.
❏

INT is asserted in response to an externally sourced interrupt
which is activated with level sensitive logic and the asserted
level is negated before the interrupt is acknowledged.

❏

INT is asserted for an interrupt source which is masked using
the mask bit in the Vector-Priority register before the
interrupt is acknowledged.

Interprocessor Interrupts (IPI)
Processor 0 and 1 can generate interrupts which are targeted for the
other processor or both processors. There are four Interprocessor
Interrupts (IPI) channels. The interrupts are initiated by writing a
bit in the IPI dispatch registers. If subsequent IPIs are initiated
before the first is acknowledged, only one IPI will be generated. The
IPI channels deliver interrupts in the Direct Mode and can be
directed to more than one processor.
8259 Compatibility
The RavenMPIC provides a mechanism to support PC-AT
compatible chip sets using the 8259 interrupt controller
architecture. After power-on reset, the RavenMPIC defaults to 8259
pass-through mode. In this mode, interrupts from external source
number 0 (the interrupt signal from the 8259 is connected to this
external interrupt source on the RavenMPIC) are passed directly to

2-67

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

processor 0. If the pass-through mode is disabled, the 8259
interrupts are delivered using the priority and distribution
mechanisms of the RavenMPIC.

The RavenMPIC does not interact with the vector fetch from the
8259 interrupt controller.
Raven-Detected Errors
Raven-detected errors are grouped together and sent to the
interrupt logic as a singular interrupt source. The interrupt delivery
mode for this interrupt is distributed. The Raven Error VectorPriority Register should be programed for high true level sensitive
activation.
For system implementations where the RavenMPIC controller is
not used, the Raven-Detected Error condition will be made
available by a signal which is external to the Raven ASIC.
Presumably this signal would be connected to an externally
sourced interrupt input of a MPIC controller in a different device.
Since the MPIC specification defines external I/O interrupts to
operate in the distributed mode, the delivery mode of this error
interrupt should be consistent.
Timers
There is a divide by eight pre-scaler which is synchronized to the
Raven clock (MPC processor clock). The output of the prescaler
enables the decrement of the four timers. The timers may be used
for system timing or to generate periodic interrupts. Each timer has
four registers which are used for configuration and control. They
are:

2-68

❏

Current Count Register

❏

Base Count Register

❏

Vector-Priority Register

❏

Destination Register

Raven Interrupt Controller Implementation

Interrupt Delivery Modes

The direct and distributed interrupt delivery modes are supported.
Note that the direct deliver mode has sub modes of multicast or
non-multicast. The Interprocessor Interrupts (IPIs) and Timer
interrupts operate in the direct delivery mode. The externally
sourced or I/O interrupts operate in the distributed mode.
In the direct delivery mode, the interrupt is directed to one or both
processors. If it is directed to two processors (i.e. multicast), it will
be delivered to two processors. The interrupt is delivered to the
processor when the priority of the interrupt is greater than the
priority contained in the task register for that processor, and when
the priority of the interrupt is greater than any interrupt which is inservice for that processor. An interrupt is considered to be in service
from the time its vector is returned during an interrupt
acknowledge cycle until an EOI is received for that interrupt. The
EOI cycle indicates the end of processing for the highest priority inservice interrupt.
In the distributed delivery mode, the interrupt is pointed to one or
more processors but it will be delivered to only one processor.
Therefore, for externally sourced or I/O interrupts, multicast
delivery is not supported.The interrupt is delivered to a processor
when the priority of the interrupt is greater than the priority
contained in the task register for that processor, and when the
priority of the interrupt is greater than any interrupt which is inservice for that processor, and when the priority of that interrupt is
the highest of all interrupts pending for that processor, and when
that interrupt is not in-service for the other processor. If both
destination bits are set for each processor, the interrupt will be
delivered to the processor that has a lower task register priority.
Note

Because a deadlock condition can occur when the task
register priorities for each processor are the same and
both processors are targeted for interrupt delivery, the
interrupt will be delivered to processor 0.

2-69

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Block Diagram Description
The description of the block diagram focuses on the theory of
operation for the interrupt delivery logic. If the preceding section is
a satisfactory description of the interrupt delivery modes and the
reader is not interested the logic implementation, this section can be
skipped.
interrupt
signals

Program
Visible
Registers

IPR

Interrupt
Selector_1

Interrupt
Selector_0

IRR_1

IRR_0

ISR_1

ISR_0

Interrupt
Router

INT1

INT 0

1917 9610

Figure 2-8. RavenMPIC Block Diagram

2-70

Raven Interrupt Controller Implementation

Program Visible Registers

These are the registers which software can access. They are
described in detail in the Register section.
Interrupt Pending Register (IPR)
The interrupt signals to RavenMPIC are qualified and
synchronized to the clock by the IPR. If the interrupt source is
internal to the Raven ASIC or external with their Sense bit = 0 (edge
sensitive), a bit is set in the IPR. That bit is cleared when the
interrupt associated with that bit is acknowledge. If the interrupt
source is external and level activated, the output from the IPR is not
negated until the level into the IPR is negated.
Externally sourced interrupts are qualified based upon their Sense
and/or Pol bits in the Vector-Priority register. IPI and Timer
Interrupts are generated internally to the Raven ASIC and are
qualified by their Destination bit. Since the internally generated
interrupts use direct delivery mode with multicast capability, there
are two bits in the IPR, one for each processor, associated with each
IPI and Timer interrupt source.
The MASK bits from the Vector-Priority registers are used to
qualify the output of the IPR. Therefore, if an interrupt condition is
detected when the MASK bit is set, that interrupt will be requested
when the MASK bit is lowered.
Interrupt Selector (IS)
There is a Interrupt Selector (IS) for each processor. The IS receives
interrupt requests from the IPR. If the interrupt request are from an
external source, they are qualified by the destination bit for that
interrupt and processor. If they are from an internal source, they
have been qualified. The output of the IS will be the highest priority
interrupt that has been qualified. This output is the priority of the
selected interrupt and its source identification. The IS will resolve
an interrupt request in two Raven clock ticks.

2-71

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

The IS also receives a second set of inputs from the ISR. During the
End Of Interrupt cycle, these inputs are used to select which bits are
to be cleared in the ISR.

Interrupt Request Register (IRR)
There is a Interrupt Request Register (IRR) for each processor. The
IRR always passes the output of the IS except during Interrupt
Acknowledge cycles. This guarantees that the vector which is read
from the Interrupt Acknowledge Register is not changing due to the
arrival of a higher priority interrupt. The IRR also serves as a
pipeline register for the two tick propagation time through the IS.
In-Service Register (ISR)
There is a In-Service Register (ISR) for each processor. The contents
of the ISR is the priority and source of all interrupts which are inservice. The ISR receives a bit-set command during Interrupt
Acknowledge cycles and a bit-clear command during End Of
Interrupt cycles.
The ISR is implemented as a 40 bit register with individual bit set
and clear functions. Fifteen bits are used to store the priority level
of each interrupt which is in-service. Twenty-five bits are used to
store the source identification of each interrupt which is in service.
Therefore there is one bit for each possible interrupt priority and
one bit for each possible interrupt source.
Interrupt Router
The Interrupt Router monitors the outputs from the ISRs, Current
Task Priority Registers, Destination Registers, and the IRRs to
determine when to assert a processorÕs INT pin.
When considering the following rule sets, it is important to
remember that there are two types of inputs to the Interrupt
Selectors. If the interrupt is a distributed class interrupt, there is a
single bit in the IPR associated with this interrupt and it is delivered
to both Interrupt Selectors. This IPR bit is qualified by the
destination register contents for that interrupt before the Interrupt

2-72

Raven Interrupt Controller Implementation

Selector compares its priority to the priority of all other requesting
interrupts for that processor. If the interrupt is programmed to be
edge sensitive, the IPR bit is cleared when the vector for that
interrupt is returned when the Interrupt Acknowledge register is
examined. On the other hand, if the interrupt is a direct/multicast
class interrupt, there are two bits in the IPR associated with this
interrupt. One bit for each processor. Then one of these bits are
delivered to each Interrupt Selector. Since this interrupt source can
be multicast, each of these IPR bits must be cleared separately when
the vector is returned for that interrupt to a particular processor.
If one of the following sets of conditions are true, the interrupt pin
for processor 0 is driven active.
❏

Set1
The source ID in IRR_0 is from an external source.
The destination bit for processor 1 is a 0 for this interrupt.
The priority from IRR_0 is greater than the highest priority in
ISR_0.
The priority from IRR_0 is greater than the contents of task
register_0.

❏

Set2
The source ID in IRR_0 is from an external source.
The destination bit for processor 1 is a 1 for this interrupt.
The source ID in IRR_0 is not present is ISR_1.
The priority from IRR_0 is greater than the highest priority in
ISR_0.
The priority from IRR_0 is greater than the Task Register_0
contents.
The contents of Task Register_0 is less than the contents of
Task Register_1.

❏

Set3
The source ID in IRR_0 is from an internal source.

2-73

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

The priority from IRR_0 is greater than the highest priority in
ISR_0.

The priority from IRR_0 is greater than the Task Register_0
contents.
There is a possibility for a priority tie between the two processors
when resolving external interrupts. In that case the interrupt is
always delivered to processor 0. This case is not defined in the
above rule set.

MPIC Registers
The following conventions are used in the Raven register charts:
❏

Read Only field.

❏

R/W Read/Write field.

❏

Writing a ONE to this field sets this field.

❏

Writing a ONE to this field clears this field.

RavenMPIC Registers
The RavenMPIC register map is shown in the following table. The
Off field is the address offset from the base address of the
RavenMPIC registers in the MPC-IO or MPC-MEMORY space.
Note that this map does not depict linear addressing. The Raven
PCI-SLAVE has two decoders for generating the RavenMPIC select.
These decoders will generate a select and acknowledge all accesses
which are in a reserved 256K byte range. If the index into that 256K
block does not decode a valid RavenMPIC register address, the
logic will return $00000000.
The registers are 8, 16, or 32 bits accessible.

2-74

Raven Interrupt Controller Implementation

Table 2-9. RavenMPIC Register Map

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Off

FEATURE REPORTING REGISTER 0

$01000

GLOBAL CONFIGURATION REGISTER 0

$01020

MPIC VENDOR IDENTIFICATION REGISTER

$01080

PROCESSOR INIT REGISTER

$01090

IPI0 VECTOR-PRIORITY REGISTER

$010a0

IPI1 VECTOR-PRIORITY REGISTER

$010b0

IPI2 VECTOR-PRIORITY REGISTER

$010c0

IPI3 VECTOR-PRIORITY REGISTER

$010d0
SP REGISTER

$010e0

TIMER FREQUENCY REPORTING REGISTER

$010f0

TIMER 0 CURRENT COUNT REGISTER

$01100

TIMER 0 BASE COUNT REGISTER

$01110

TIMER 0 VECTOR-PRIORITY REGISTER

$01120

TIMER 0 DESTINATION REGISTER

$01130

TIMER 1 CURRENT COUNT REGISTER

$01140

TIMER 1 BASE COUNT REGISTER

$01150

TIMER 1VECTOR-PRIORITY REGISTER

$01160

TIMER 1DESTINATION REGISTER

$01170

TIMER 2 CURRENT COUNT REGISTER

$01180

TIMER 2 BASE COUNT REGISTER

$01190

TIMER 2 VECTOR-PRIORITY REGISTER

$011a0

TIMER 2 DESTINATION REGISTER

$011b0

TIMER 3 CURRENT COUNT REGISTER

$011c0

TIMER 3 BASE COUNT REGISTER

$011d0

2-75

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Off

TIMER 3 VECTOR-PRIORITY REGISTER

$011e0

TIMER 3 DESTINATION REGISTER

$011f0

INT. SRC. 0 VECTOR-PRIORITY REGISTER

$10000

INT. SRC. 0 DESTINATION REGISTER

$10010

INT. SRC. 1 VECTOR-PRIORITY REGISTER

$10020

INT. SRC. 1 DESTINATION REGISTER

$10030

INT. SRC. 2 VECTOR-PRIORITY REGISTER

$10040

INT. SRC. 2 DESTINATION REGISTER

$10050

INT. SRC. 3 VECTOR-PRIORITY REGISTER

$10060

INT. SRC. 3 DESTINATION REGISTER

$10070

INT. SRC. 4 VECTOR-PRIORITY REGISTER

$10080

INT. SRC. 4 DESTINATION REGISTER

$10090

INT. SRC. 5 VECTOR-PRIORITY REGISTER

$100a0

INT. SRC. 5 DESTINATION REGISTER

$100b0

INT. SRC. 6 VECTOR-PRIORITY REGISTER

$100c0

INT. SRC. 6 DESTINATION REGISTER

$100d0

INT. SRC. 7 VECTOR-PRIORITY REGISTER

$100e0

INT. SRC. 7 DESTINATION REGISTER

$100f0

INT. SRC. 8 VECTOR-PRIORITY REGISTER

$10100

INT. SRC. 8 DESTINATION REGISTER

$10110

INT. SRC. 9 VECTOR-PRIORITY REGISTER

$10120

INT. SRC. 9 DESTINATION REGISTER

$10130

INT. SRC. 10 VECTOR-PRIORITY REGISTER

$10140

INT. SRC. 10 DESTINATION REGISTER

$10150

INT. SRC. 11 VECTOR-PRIORITY REGISTER

$10160

INT. SRC. 11 DESTINATION REGISTER

$10170

INT. SRC. 12 VECTOR-PRIORITY REGISTER

$10180

2-76

Raven Interrupt Controller Implementation

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Off

INT. SRC. 12 DESTINATION REGISTER

$10190

INT. SRC. 13 VECTOR-PRIORITY REGISTER

$101a0

INT. SRC. 13 DESTINATION REGISTER

$101b0

INT. SRC. 14 VECTOR-PRIORITY REGISTER

$101c0

INT. SRC. 14 DESTINATION REGISTER

$101d0

INT. SRC. 15 VECTOR-PRIORITY REGISTER

$101e0

INT. SRC. 15 DESTINATION REGISTER

$101f0

RAVEN DETECTED ERRORS VECTOR-PRIORITY REGISTER

$10200

RAVEN DETECTED ERRORS DESTINATION REGISTER

$10210

IPI 0 DISPATCH REGISTER PROC. 0

$20040

IPI 1 DISPATCH REGISTER PROC. 0

$20050

IPI 2 DISPATCH REGISTER PROC. 0

$20060

IPI 3 DISPATCH REGISTER PROC. 0

$20070

CURRENT TASK PRIORITY REGISTER PROC. 0

$20080

IACK REGISTER
P0

$200a0

EOI REGISTER P0

$200b0

IPI 0 DISPATCH REGISTER PROC. 1

$21040

IPI 1 DISPATCH REGISTER PROC. 1

$21050

IPI 2 DISPATCH REGISTER PROC. 1

$21060

IPI 3 DISPATCH REGISTER PROC. 1

$21070

CURRENT TASK PRIORITY REGISTER PROC. 1

$21080

2-77

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

2-78

Off

IACK REGISTER
P1

$210a0

EOI REGISTER P1

$210b0

Raven Interrupt Controller Implementation

Feature Reporting Register

Offset
Bit

$01000
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

FEATURE REPORTING
NIRQ

NCPU

VID

Operation

Reset

$00F

$01

$02

NIRQ

NUMBER OF IRQs. The number of the highest
external IRQ source supported. The IPI, Timer, and
Raven Detected Error interrupts are excluded from
this count.

NCPU

NUMBER OF CPUs. The number of the highest
physical CPU supported. There are two CPUs
supported by this design. CPU #0 and CPU #1.

VID

VERSION ID. Version ID for this interrupt
controller. This value reports what level of the
speciÞcation is supported by this implementation.
Version level of 02 is used for the initial release of the
MPIC speciÞcation.

2-79

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Global Configuration Register
Offset
Bit

$01020
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

2-80

M
R/W 0
R
0
RESET C
0

Operation

GLOBAL CONFIGURATION

$00

RESET CONTROLLER. Writing a one to this bit
forces the controller logic to be reset. This bit is
cleared automatically when the reset sequence is
complete. While this bit is set, the values of all other
register are undeÞned.

CASCADE MODE. Allows cascading of an external
8259 pair connected to the Þrst interrupt source
input pin (0). This bit will always be set to a one,
indicating mixed mode. In the mixed mode, 8259
interrupts are delivered using the priority and
distribution mechanism of the RavenMPIC. The
Vector/Priority and Destination registers for
interrupt source 0 are used to control the delivery
mode for all 8259 generated interrupt sources.

2Raven PCI Host Bridge & Multi-Processor Interrupt
Controller Chip
Raven Interrupt Controller Implementation

0Raven Interrupt Controller Implementation

Vendor Identification Register
Offset
Bit

$01080
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

VENDOR IDENTIFICATION
STP

Operation
Reset

$00

$02

$00

There are two fields in the Vendor Identification Register which are
not defined for the RavenMPIC implementation but are defined in
the MPIC specification. They are the vendor identification and
device ID fields.
STP

STEPPING.The stepping or silicon revision number
is initially 0.

Processor Init Register
Offset
Bit

$01090
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

$00

P0 R/W 0
P1 R/W 0

Operation

PROCESSOR INIT

PROCESSOR 1. Writing a 1 to P1 will assert the Soft
Reset input of processor 1. Writing a 0 to it will
negate the SRESET signal.

2-81

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

PROCESSOR 0. Writing a 1 to P0 will assert the Soft
Reset input of processor 0. Writing a 0 to it will
negate the SRESET signal.

The Soft Reset input to the 604 is negative edge-sensitive.
IPI Vector/Priority Registers
Offset

Bit

IPI 0 - $010A0
IPI 1 - $010B0
IPI 2 - $010C0
IPI 3 - $010D0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

PRIOR

ACT
R
0
MASK R/W 1

Operation

IPI VECTOR/PRIORITY
VECTOR

R/W

$000

$00

MASK

MASK. Setting this bit disables any further
interrupts from this source. If the mask bit is cleared
while the bit associated with this interrupt is set in
the IPR, the interrupt request will be generated.

ACT

ACTIVITY. The activity bit indicates that an
interrupt has been requested or that it is in-service.
The ACT bit is set to a one when its associated bit in
the Interrupt Pending Register or In-Service Register
is set.

PRIOR

Interrupt priority 0 is the lowest and 15 is the
highest. Note that a priority level of 0 will not enable
interrupts.

VECTOR This vector is returned when the Interrupt
Acknowledge register is examined during a request
for the interrupt associated with this vector.

2-82

Raven Interrupt Controller Implementation

Spurious Vector Register

Offset
Bit

$010E0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name
Operation
Reset

VECTOR
R

R/W

$00

$FF

VECTOR This vector is returned when the Interrupt
Acknowledge register is read during a spurious
vector fetch.
Timer Frequency Register
Offset
Bit
Name
Operation
Reset

$010F0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
TIMER FREQUENCY
R/W
$00000000

This register is used to report the frequency (in Hz) of the clock
source for the global timers. Following reset, this register contains
zero. For the Raven implementation of MPIC on the MVME2300
series, this register must be written with a value of $7de290 (which
is 66/8 MHz or 8.25 MHz) which corresponds to a 66 MHz MPC
bus.

2-83

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Timer Current Count Registers
Offset

Bit

Timer 0 - $01100
Timer 1 - $01140
Timer 2 - $01180
Timer 3 - $011C0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

T
Operation

TIMER CURRENT COUNT

$00000000

TOGGLE. This bit toggles when ever the current
count decrements to zero.

CURRENT COUNT. The current count Þeld
decrements while the Count Inhibit bit is the Base
Count Register is zero. When the timer counts down
to zero, the Current Count register is reloaded from
the Base Count register.

Timer Basecount Registers
Offset

Bit

Timer 0 - $01110
Timer 1 - $01150
Timer 2 - $01190
Timer 3 - $011D0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

CI R/W 1

Operation

TIMER BASECOUNT

R/W
$00000000

2-84

COUNT INHIBIT. Setting this bit to one inhibits
counting for this timer. Setting this bit to zero allows
counting to proceed.

Raven Interrupt Controller Implementation

BASE COUNT. This Þeld contains the 31 bit count
for this timer. When a value is written into this
register and the CI bit transitions from a 1 to a 0, it is
copied into the corresponding Current Count
register and the toggle bit in the Current Count
register is cleared. When the timer counts down to
zero, the Current Count register is reloaded from the
Base Count register.

Timer Vector/Priority Registers
Offset

Bit

Timer 0 - $01120
Timer 1 - $01160
Timer 2 - $011A0
Timer 3 - $011E0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

PRIOR

ACT
R
0
MASK R/W 1

Operation

TIMER VECTOR/PRIORITY
VECTOR

R/W

$000

$00

MASK

ACT

PRIOR

Interrupt priority 0 is the lowest and 15 is the
highest. Note that a priority level of 0 will not enable
interrupts.

2-85

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

VECTOR This vector is returned when the Interrupt
Acknowledge register is examined upon
acknowledgment of the interrupt associated with
this vector.

Timer Destination Registers
Offset

Bit

Timer 0 - $01130
Timer 1 - $01170
Timer 2 - $011B0
Timer 3 - $011F0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

$00

P0 R/W 0
P1 R/W 0

Operation

TIMER DESTINATION

This register indicates the destinations for this timerÕs interrupts.
Timer interrupts, operate in the Directed delivery interrupt mode.
This register may specify multiple destinations (multicast delivery).

2-86

PROCESSOR 1. The interrupt is directed to
processor 1.

PROCESSOR 0. The interrupt is directed to
processor 0.

Raven Interrupt Controller Implementation

External Source Vector/Priority Registers
Offset
Bit

Int Src 0 - $10000
Int Src 2 -> Int Src15 - $10020 -> $101E0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

EXTERNAL SOURCE VECTOR/PRIORITY

R
0
R/W 1

Reset

R
$000

R
0
R
0
SENSE R/W 0
POL
R/W 0

ACT
MASK
Operation

PRIOR

VECTOR

R/W

$00

MASK

ACT

POL

POLARITY. This bit sets the polarity for external
interrupts. Setting this bit to a zero enables active
low or negative edge. Setting this bit to a one enables
active high or positive edge. Only External Interrupt
Source 0 uses this bit in this register.

SENSE

SENSE. This bit sets the sense for external
interrupts. Setting this bit to a zero enables edge
sensitive interrupts. Setting this bit to a one enables
level sensitive interrupts. For external interrupt
sources 1 through 15, setting this bit to a zero enables
positive edge triggered interrupts. Setting this bit to
a one enables active low level triggered interrupts.

2-87

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

PRIOR

Interrupt priority 0 is the lowest and 15 is the
highest. Note that a priority level of 0 will not enable
interrupts.

VECTOR This vector is returned when the Interrupt
Acknowledge register is examined upon
acknowledgment of the interrupt associated with
this vector.
External Source Destination Registers
Offset
Bit

Int Src 0 - $10010
Int Src 2 -> Int Src 15 - $10030 -> $101F0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

$00

P0 R/W 0
P1 R/W 0

Operation

EXTERNAL SOURCE DESTINATION

This register indicates the possible destinations for the external
interrupt sources. These interrupts operate in the Distributed
interrupt delivery mode.

2-88

PROCESSOR 1. The interrupt is pointed to
processor 1.

PROCESSOR 0. The interrupt is pointed to
processor 0.

Raven Interrupt Controller Implementation

Raven-Detected Errors Vector/Priority Register
Offset
Bit

$10200
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

RAVEN DETECTED ERRORS VECTOR/PRIORITY

$000

PRIOR

R/W

0
0
0
0

R
0
R/W 1

Reset

R
R
SENSE R/W
R

ACT
MASK
Operation

VECTOR

$00

MASK

ACT

SENSE

SENSE. This bit sets the sense for external
interrupts. Setting this bit to a zero enables positive
edge sensitive interrupts. Setting this bit to a one
enables active low level sensitive interrupts.

PRIOR

Interrupt priority 0 is the lowest and 15 is the
highest. Note that a priority level of 0 will not enable
interrupts.

VECTOR This vector is returned when the Interrupt
Acknowledge register is examined upon
acknowledgment of the interrupt associated with
this vector.

2-89

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Raven-Detected Errors Destination Register
Offset
Bit

$10210
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

$00

P0 R/W 0
P1 R/W 0

Operation

RAVEN DETECTED ERROR DESTINATION

This register indicates the possible destinations for the Raven
detected error interrupt source. These interrupts operate in the
Distributed interrupt delivery mode.
P1

PROCESSOR 1. The interrupt is pointed to
processor 1.

PROCESSOR 0. The interrupt is pointed to
processor 0.

Interprocessor Interrupt Dispatch Registers
Offset
Bit

Processor 0 $20040, $20050, $20060, $20070
Processor 1 $21040, $21050,$21060, $21070
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

Reset

$00

P0 R/W 0
P1 R/W 0

Operation

IPI DISPATCH

There are four Interprocessor Interrupt Dispatch Registers. Writing
to an IPI Dispatch Register with the P0 and/or P1 bit set causes an
interprocessor interrupt request to be sent to one or more

2-90

Raven Interrupt Controller Implementation

processors. Note that each IPI Dispatch Register has two addresses.
These registers are considered to be per processor registers and
there is one address per processor. Reading these registers returns
zeros.
P1

PROCESSOR 1. The interrupt is directed to
processor 1.

PROCESSOR 0. The interrupt is directed to
processor 0.

Interrupt Task Priority Registers
Offset
Bit

Processor 0 $20080
Processor 1 $21080
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name

INTERRUPT TASK PRIORITY
TP

Operation
Reset

R/W

$00

There is one Task Priority Register per processor. Priority levels
from 0 (lowest) to 15 (highest) are supported. Setting the Task
Priority Register to 15 masks all interrupts to this processor.
Hardware will set the task register to $F when it is reset or when the
Init bit associated with this processor is written to a one.

2-91

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Interrupt Acknowledge Registers
Offset
Bit

Processor 0 $200A0
Processor 1 $210A0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name
Operation
Reset

VECTOR
R

$00

$FF

On PowerPC-based systems, Interrupt Acknowledge is
implemented as a read request to a memory-mapped Interrupt
Acknowledge register. Reading the Interrupt Acknowledge
register returns the interrupt vector corresponding to the highest
priority pending interrupt. Reading this register also has the
following side effects.
❏

The associated bit in the Interrupt Pending Register is
cleared.

❏

Reading this register will update the In-Service register.

Reading this register without a pending interrupt will return a
value of $FF hex.
End-of-Interrupt Registers
Offset
Bit

Processor 0 $200B0
Processor 1 $210B0
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Name
Operation
Reset

EOI
R

$00

EOI

2-92

END OF INTERRUPT. There is one EOI register per
processor. EOI Code values other than 0 are
currently undeÞned. Data values written to this
register are ignored; zero is assumed. Writing to this

Raven Interrupt Controller Implementation

register signals the end of processing for the highest
priority interrupt currently in service by the
associated processor. The write operation will
update the In-Service register by retiring the highest
priority interrupt. Reading this register returns
zeros.

Programming Notes
External Interrupt Service
The following summarizes how an external interrupt is serviced:
1. An external interrupt occurs.
2. The processor state is saved in the machine status
save/restore registers. A new value is loaded into the
Machine State Register (MSR). The External Interrupt Enable
bit in the new MSR (MSRee) is set to zero. Control is
transferred to the O/S external interrupt handler.
3. The external interrupt handler calculates the address of the
Interrupt Acknowledge register for this processor
(RavenMPIC Base Address + 0x200A00 + (processor ID
shifted left 12 bits)).
4. The external interrupt handler issues an Interrupt
Acknowledge request to read the interrupt vector from the
RavenMPIC. If the interrupt vector indicates the interrupt
source is the 8259, the interrupt handler issues a second
Interrupt Acknowledge request to read the interrupt vector
from the 8259. The RavenMPIC does not interact with the
vector fetch from the 8259.
5. The interrupt handler saves the processor state and other
interrupt-specific information in system memory and reenables for external interrupts (the MSRee bit is set to 1).
RavenMPIC blocks interrupts from sources with equal or
lower priority until an End-of-Interrupt is received for that
interrupt source. Interrupts from higher priority interrupt

2-93

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

sources continue to be enabled. If the interrupt source was the
8259, the interrupt handler issues an EOI request to the
RavenMPIC. This resets the In-Service bit for the 8259 within
the RavenMPIC and allows it to recognize higher priority
interrupt requests, if any, from the 8259. If none of the nested
interrupt modes of the 8259 are enabled, the interrupt
handler issues an EOI request to the 8259.

a. The device driver interrupt service routine associated with
this interrupt vector is invoked.
b. If the interrupt source was not the 8259, the interrupt
handler issues an EOI request for this interrupt vector to
the RavenMPIC. If the interrupt source was the 8259 and
any of the nested interrupt modes of the 8259 are enabled,
the interrupt handler issues an EOI request to the 8259.
Normally, interrupts from ISA devices are connected to the
8259 interrupt controller. ISA devices typically rely on the
8259 Interrupt Acknowledge to flush buffers between the ISA
device and system memory. If interrupts from ISA devices
are directly connected to the RavenMPIC (bypassing the
8259), the device driver interrupt service routine must read
status from the ISA device to ensure buffers between the
device and system memory are flushed.
Reset State
After a power-on reset the RavenMPIC state is:

2-94

❏

Current task priority for all CPUs set to 15.

❏

All interrupt source priorities set to zero.

❏

All interrupt source mask bits set to a one.

❏

All interrupt source activity bits cleared.

❏

Processor Init Register is cleared.

❏

All counters stopped and interrupts disabled.

❏

Controller mode set to 8259 pass-through.

Raven Interrupt Controller Implementation

Operation

Interprocessor Interrupts
Four interprocessor interrupt (IPI) channels are provided for use by
all processors. During system initialization the IPI vector/priority
registers for each channel should be programmed to set the priority
and vector returned for each IPI event. During system operation a
processor may generate an IPI by writing a destination mask to one
of the IPI dispatch registers.
Note that each IPI dispatch register is shared by both processors.
Each IPI dispatch register has two addresses but they are shared by
both processors. That is, there is a total of four IPI dispatch registers
in the RavenMPIC.
The IPI mechanism may be used for self interrupts by
programming the dispatch register with the bit mask for the
originating processor.
Dynamically Changing I/O Interrupt Configuration
The interrupt controller provides a mechanism for safely changing
the vector, priority, or destination of I/O interrupt sources. This is
provided to support systems which allow dynamic configuration of
I/O devices. In order to change the vector, priority, or destination
of an active interrupt source, the following sequence should be
performed:
1. Mask the source using the MASK bit in the vector/priority
register.
2. Wait for the activity bit (ACT) for that source to be cleared.
3. Make the desired changes.
4. Unmask the source.
This sequence ensures that the vector, priority, destination, and
mask information remain valid until all processing of pending
interrupts is complete.

2-95

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

EOI Register
Each processor has a private EOI register which is used to signal the
end of processing for a particular interrupt event. If multiple nested
interrupts are in service, the EOI command terminates the interrupt
service of the highest priority source. Once an interrupt is
acknowledged, only sources of higher priority will be allowed to
interrupt the processor until the EOI command is received. This
register should always be written with a value of zero which is the
nonspecific EOI command.
Interrupt Acknowledge Register
Upon receipt of an interrupt signal, the processor may read this
register to retrieve the vector of the interrupt source which caused
the interrupt.
8259 Mode
The 8259 mode bits control the use of an external 8259 pair for PCAT compatibility. Following a reset, this mode is set for passthrough, which essentially disables the advanced controller and
passes an 8259 input on external interrupt source 0 directly through
to processor zero. During interrupt controller initialization this
channel should be programmed for mixed mode in order to take
advantage of the interrupt delivery modes.
Current Task Priority Level
Each processor has a separate Current Task Priority Level register.
The system software uses this register to indicate the relative
priority of the task running on the corresponding processor. The
interrupt controller will not deliver an interrupt to a processor
unless it has a priority level which is greater than the current task
priority level of that processor. This value is also used in
determining the destination for interrupts which are delivered
using the distributed deliver mode.

2-96

Raven Interrupt Controller Implementation

Architectural Notes

The hardware and software overhead required to update the task
priority register synchronously with instruction execution may far
outweigh the anticipated benefits of the task priority register. To
minimize this overhead, the interrupt controller architecture
should allow the task priority register to be updated
asynchronously with respect to instruction execution. Lower
priority interrupts may continue to occur for an indeterminate
number of cycles after the processor has updated the task priority
register. If this is not acceptable, the interrupt controller
architecture should recommend that, if the task priority register is
not implemented with the processor, the task priority register
should be updated only when the processor enter or exits an idle
state.
Only when the task priority register is integrated within the
processor, (such that it can be accessed as quickly as the MSRee bit
defined in the Programming Notes section, for example), should the
architecture require the task priority register to be updated
synchronously with instruction execution.

2-97

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2-98

3Falcon ECC Memory Controller
Chip Set

Introduction
The Falcon DRAM controller ASIC is designed for the MVME2300
family of boards. It is used in sets of two to provide the interface
between the PowerPC 60x bus (also called MPC60x bus or MPC
bus) and a 144-bit ECC-DRAM memory system. It also provides an
interface to ROM/Flash.

Overview
This chapter provides a functional description and programming
model for the Falcon. Most of the information for using the device
in a system, programming it in a system, and testing it is contained
here.

Bit Ordering Convention
All Falcon bused signals are named using big-endian bit ordering
(bit 0 is the most significant bit).

Features
❏

DRAM Interface
Ð Double-bit error detect/Single-bit error correct on 72-bit
basis.
Ð Up to four blocks.
Ð Programmable base address for each block.
Ð Two-way interleave factor.
Ð Built-in Refresh/Scrub.

❏

Error Notification for DRAM

3-1

Falcon ECC Memory Controller Chip Set

Ð Software programmable Interrupt on Single/Double-Bit
Error.
Ð Error address and Syndrome Log Registers for Error
Logging.

Ð Does not provide TEA_ on Double-Bit Error. (Chip has no
TEA_ pin.)
❏

ROM/Flash Interface
Ð Two blocks with two 8-bit devices, or two 32-bit devices
per block.

Block Diagrams
Figure 3-1 depicts a Falcon pair as it would be connected in a
system. Figure 3-2 shows the FalconÕs internal data paths. Figure
3-3 shows the overall DRAM connections.

3-2

Block Diagrams

Lower
DRAM
ARRAYS

3
Lower PowerPC

Lower DRAM

Data (32Bits)

Data (64 Bits)

Lower DRAM
Address & Control

Lower DRAM

Check

PowerPC
Address &
Control

Serial Bus

Check-bits (8 Bits)

Upper
DRAM
ARRAYS
Upper DRAM
Data (64 Bits)

Data
FALCON

PowerPC 60x Bus

FALCON

Data

Upper DRAM
Address & Control

Upper PowerPC
Data (32 Bits)
Upper DRAM

Check

Check-bits (8 Bits)

1900 9609

Figure 3-1. Falcon Pair Used with DRAM in a System

3-3

Falcon ECC Memory Controller Chip Set

Latched D

CKD[0:7]

(64 Bits)

(8 Bits)

Uncorrected Data
(64 Bits)

RD[0:63]

LATCHES

(8 Bits)

HAMGEN

SYNDEC

(8 Bits)

(64 Bits)

Corrected Data

D[0:31]

(64 Bits)

MUX

DFF’s

DRAM
Side

HAMGEN

PowerPC
Side

1901 9609

Figure 3-2. Falcon Internal Data Paths (Simplified)

3-4

Block Diagrams

BD_RAS_/CAS_
AC_RAS_/CAS_

RA/OE_/WE_

LOWER
FALCON

RD0-63

CKD0-7

DRAM
BLOCK A
LOWER

DRAM
BLOCK B
LOWER

DRAM
BLOCK C
LOWER

DRAM
BLOCK D
LOWER

DRAM
BLOCK A
UPPER

DRAM
BLOCK B
UPPER

DRAM
BLOCK C
UPPER

DRAM
BLOCK D
UPPER

BD_RAS_/CAS_
AC_RAS_/CAS_

RA/OE_/WE_

UPPER
FALCON

RD0-63

CKD0-7

1902 9609

Figure 3-3. Overall DRAM Connections
3-5

Falcon ECC Memory Controller Chip Set

Functional Description
The following sections describe the logical function of the ASIC.
The Falcon is designed to be used as a set of two chips. A pair of
Falcons works with x1 or wider DRAM memory devices to form a
memory system for the PowerPC 60x bus. A pair of Falcons that is
connected to implement a memory control function is referred to in
this document as a ÒFalcon pairÓ.

Performance
Four-beat Reads/Writes
The Falcon pair is specifically designed to provide maximum
performance for cache line (four-beat) cycles to and from the
PowerPC 60x bus at 66MHz. This is done by providing a two-way
interleave between the 64-bit PowerPC 60x data bus and the 128-bit
(144 with check-bits) DRAM bus. When a PowerPC 60x bus master
begins a quad-aligned, four-beat read to DRAM, the Falcon pair
accesses the full 144-bit width of DRAM at once so that when the
DRAM access time is reached, not only is the first 64-bit doubleword of data ready to be transferred to the PowerPC 60x bus
master, but so is the next. While the Falcon pair is presenting the
first two double-words to the PowerPC 60x bus, it cycles CAS
without cycling RAS to obtain the next two double-words. The
Falcon pair transfers the next two double-words to the PowerPC
60x bus after 0 or more idle clocks.
The Falcon pair also takes advantage of the fact that PowerPC 60x
processors can do address pipelining. Many times while a data
cycle is finishing, the PowerPC 60x processor begins a new address
cycle. The Falcon pair can begin the next DRAM access earlier when
this happens, thus shortening the access time. Further savings come
when the new address cycle is to an address close enough to the
previous one that it falls within the same row in the DRAM array.
When this happens, the Falcon pair can transfer the data for the
next cycle by cycling CAS without cycling RAS.

3-6

Functional Description

Single-beat Reads/Writes
Single-beat cycles to and from the PowerPC 60x bus do not achieve
data rates as high as do four-beat cycles. The Falcon pair does take
advantage of the PowerPC 60x address pipelining as much as
possible for single-beat accesses.
Single-beat writes are the slowest kind of accesses because they
require that the Falcon pair perform a read cycle then a write cycle
to the DRAM in order to complete. When the Falcon pair can take
advantage of address pipelining, back-to-back single-beat writes
take 10 clocks to complete.
DRAM Speeds
The Falcon pair can be configured for 3 different speeds of DRAM:
50ns, 60ns and 70ns. When the Falcon pair is configured for 50ns
DRAMs, it assumes that the devices are Hyper-Page parts. When
the Falcon pair is configured for 70ns DRAMs it assumes that the
devices are Page parts. When the pair is configured for 60ns
DRAMs, it allows the devices to be either Page or Hyper-Page parts.
Performance summaries using the different devices are shown in
Tables 3-1, 3-2, and 3-3.

3-7

Falcon ECC Memory Controller Chip Set

Table 3-1. PowerPC 60x Bus to DRAM Access Timing When Configured for
70ns Page Devices

CLOCK PERIODS REQUIRED FOR:
ACCESS TYPE

Total
Clocks

1st
Beat

2nd
Beat

3rd
Beat

4th
Beat

4-Beat Read after Idle (Quadword aligned)

4-Beat Read after Idle (Quadword misaligned)

4-Beat Read after 4-Beat Read
(Quad-word aligned)

9/3 1

14/8

4-Beat Read after 4-Beat Read
(misaligned)

7/2 1

13/8

10/6 1

13/9

11/7 1

11/7

15/11

4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write

15/11

Notes:
1. These numbers assume that the PowerPC 60x bus master is
doing address pipelining with TS_ occurring at the minimum
time after AACK_ is asserted. Also the two numbers shown
in the 1st beat column are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.

3-8

Functional Description

Table 3-2. PowerPC 60x Bus to DRAM Access Timing When Configured for
60ns Page Devices.
CLOCK PERIODS REQUIRED FOR:
ACCESS TYPE

Total
Clocks

1st
Beat

2nd
Beat

3rd
Beat

4th
Beat

4-Beat Read after Idle (Quadword aligned)

4-Beat Read after Idle (Quadword misaligned)

4-Beat Read after 4-Beat Read
(Quad-word aligned)

7/3 1

11/7

4-Beat Read after 4-Beat Read
(misaligned)

6/2 1

11/7

7/3 1

10/6

9/6 1

9/6

13/10

4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write

13/10

3-9

Falcon ECC Memory Controller Chip Set

Table 3-3. PowerPC 60x Bus to DRAM Access Timing When Configured for
50ns Hyper Devices
CLOCK PERIODS REQUIRED FOR:

ACCESS TYPE

Total
Clocks

1st
Beat

2nd
Beat

3rd
Beat

4th
Beat

4-Beat Read after Idle (Quadword aligned)

4-Beat Read after Idle (Quadword misaligned)

4-Beat Read after 4-Beat Read
(Quad-word aligned)

5/2 1

8/5

4-Beat Read after 4-Beat Read
(misaligned)

4/2 1

8/6

4/3 1

7/6

7/5 1

7/5

9/7 1

9/7

4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write

Notes:
1. These numbers assume that the PowerPC 60x bus master is
doing address pipelining with TS_ occurring at the minimum
time after AACK_ is asserted. Also the two numbers shown
in 1st beat column are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.

3-10

Functional Description

ROM/Flash Speeds
The Falcon pair provides the interface for two blocks of
ROM/Flash. Each block can address up to 64Mbytes of memory
depending on the width implemented for that block (16 bits or 64
bits). Bank A is 64-bit wide and bank B is 16-bit wide. The access
times for ROM/Flash are shown in Tables 3-4 and 3-5.
Table 3-4. PowerPC 60x Bus to ROM/Flash Access Timing When Configured
for 64 Bits (32 Bits per Falcon)
CLOCK PERIODS REQUIRED FOR:
ACCESS TYPE

Total
Clocks

1st
Beat

2nd
Beat

3rd
Beat

4th
Beat

4-Beat Read

4-Beat Write

N/A

1-Beat Read

1-Beat Write

Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing When Configured
for 16 Bits (8 Bits per Falcon)
CLOCK PERIODS REQUIRED FOR:
ACCESS TYPE

Total
Clocks

1st
Beat

2nd
Beat

3rd
Beat

4th
Beat

4-Beat Read

260

4-Beat Write

N/A

1-Beat Read (2 bytes to 8 bytes)

1-Beat Read (1 byte)

1-Beat Write

3-11

Falcon ECC Memory Controller Chip Set

PowerPC 60x Bus Interface
The Falcon pair has a PowerPC slave interface only. It has no
PowerPC master interface. The slave interface is the mechanism for
all accesses to DRAM, ROM/Flash, and Falcon registers/SRAM.

Responding to Address Transfers
When the Falcon pair detects an address transfer that it is to
respond to, it asserts AACK_ immediately if there is no
uncompleted PowerPC 60x bus data transfer in process. If there is
one in process, then the Falcon pair waits and asserts AACK_
coincident with the uncompleted data transferÕs last data beat if the
Falcon pair is the slave for the previous data. If it is not, it holds off
AACK_ until the CLOCK after the previous data transferÕs last data
beat.
Completing Data Transfers
If an address transfer to the Falcon pair will have an associated data
transfer, the Falcon pair begins a read or write cycle to the accessed
entity (DRAM/ROM/Flash/Internal Register) as soon as the entity
is free. If the data transfer will be a read, the Falcon pair begins
providing data to the PowerPC 60x bus as soon as the entity has
data ready and the PowerPC 60x data bus is granted. If the data
transfer will be a write, the Falcon pair begins latching data from
the PowerPC data bus as soon as any previously latched data is no
longer needed and the PowerPC 60x data bus has been granted.
Cache Coherency
The Falcon pair supports cache coherency by monitoring the
ARTRY_ control signal on the PowerPC 60x bus and behaving
appropriately when it is asserted. When ARTRY_ is asserted, if the
access is a read, the Falcon pair does not source the data for that
access. If the access is a write, the Falcon does not write the data for
that access to the DRAM array. Depending upon when the retry
occurs however, the Falcon pair may cycle the DRAM even though
the data transfer does not happen.

3-12

Functional Description

Cache Coherency Restrictions
The PowerPC 60x GBL_ signal must not be asserted in the CSR areas.

L2 Cache Support
The Falcon pair provides support for a look-aside L2 cache by
implementing a hold-off input, L2CLM_. On cycles that select the
Falcon pair, the Falcon pair samples L2CLM_ on the second rising
edge of CLOCK after the assertion of TS_. If L2CLM_ is high, the
Falcon pair responds normally to the cycle. If it is low, the Falcon
pair ignores the cycle.
Note

The MVME2300 series boards have no L2 cache.

ECC
The Falcon pair performs single-bit error correction and double-bit
error detection for DRAM. (No checking is provided for ROM
/Flash.) The 64-bit wide PowerPC 60x data bus is divided into
upper (DH0-DH31) and lower (DL0-DL31) halves. Each half is
routed through a Falcon which multiplexes it with half of the
DRAM data bus. Each Falcon connects to 64 DRAM data-bits and
to 8 DRAM check-bits. The total DRAM array width is 144 bits
(2*[64+8]).
Cycle Types
To support ECC, the Falcon pair always deals with DRAM using
full width (144-bit) accesses. When the PowerPC 60x bus master
requests any size read of DRAM, the Falcon pair reads 144 bits at
least once. When the PowerPC 60x bus master requests a four-beat
write to DRAM, the Falcon pair writes all 144 bits twice. When the
PowerPC 60x bus master requests a single-beat write to DRAM, the
Falcon pair performs a 144-bit wide read cycle to DRAM, merges in
the appropriate PowerPC 60x bus write data, and writes 144 bits
back to DRAM.

3-13

Falcon ECC Memory Controller Chip Set

Error Reporting
The Falcon pair checks data from the DRAM during single- and fourbeat reads, during single-beat writes, and during scrubs. Table 3-6
shows the actions it takes for different errors during these accesses.

Note that the Falcon pair does not assert TEA_ on double-bit errors.
In fact, the Falcon pair does not have a TEA_ signal pin and it
assumes that the system does not implement TEA_. The Falcon can,
however, assert machine check (MCP_) on double-bit error.
Table 3-6. Error Reporting
Error Type

Single-Bit
Error

Double-Bit
Error

Triple- (or
greater)
Bit Error

Single-Beat/FourSingle-Beat Write Four-Beat Write
Beat Read

Scrub

Terminate the
Terminate the
PowerPC 60x bus cycle PowerPC 60x bus cycle
normally.
normally.

This cycle is not seen
on the PowerPC 60x
bus.

Provide corrected data Correct the data read
to the PowerPC 60x
from DRAM, merge
bus master.
with the write data,
and write the corrected, merged data to
DRAM.
Assert INT_ if so
enabled.
Assert INT_ if so
enabled.
Terminate the
Terminate the
PowerPC 60x bus cycle PowerPC 60x bus cycle
normally.
normally.

Write corrected data
back to DRAM if so
enabled.

Provide miss-corrected, raw DRAM
data to the PowerPC
60x bus master.

Do not perform the
write portion of the
read-modify-write
cycle to DRAM.

N/A 1

Assert INT_ if so
enabled.
This cycle is not seen
on the PowerPC 60x
bus.
N/A 1

Do not perform the
write portion of the
read-modify-write
cycle to DRAM.

Assert INT_ if so
Assert INT_ if so
Assert INT_ if so
enabled.
enabled.
enabled.
Assert MCP_ if so
Assert MCP_ if so
enabled.
enabled.
Some of these errors are detected correctly and are treated the same as double-bit errors. The
rest could show up as Òno errorÓ or Òsingle-bit errorÓ, both of which are incorrect.

Notes:
1. No opportunity for error since no read of DRAM occurs
during a four-beat write.
3-14

Functional Description

Error Logging
ECC error logging is facilitated by the Falcon because of its internal
latches. When an error (single- or double-bit) occurs in the DRAMs
to which a Falcon is connected, it records the address and syndrome
bits associated with the data in error. Each Falcon performs this
logging function independently of the other. Once a Falcon has
logged an error, it does not log any more until the elog control
/status bit has been cleared by software unless the currently logged
error is single-bit and a new, double-bit error is encountered. The
logging of errors that occur during scrub can be enabled/disabled
in software. Refer to the Error Logger Register in this chapter.

DRAM Tester

The DRAM tester is for in-house manufacturing testing
purposes only and should not be used by customers.

Caution

3-15

Falcon ECC Memory Controller Chip Set

ROM/Flash Interface
The Falcon pair provides the interface for two blocks of
ROM/Flash. Each block provides addressing and control for up to
64Mbytes. Note that no error checking (ECC or Parity) is provided
for the ROM/Flash.

The ROM/Flash interface allows each block to be individually
configured by jumpers and/or by software as follows:
1. Access for each block is controlled by two software
programmable control register bits: an overall enable, a write
enable, and a reset vector enable. The overall enable controls
normal read accesses. The write enable is used to program
Flash devices. The reset vector enable controls whether the
block is also enabled at $FFF00000 - $FFFFFFFF. The overall
enable and write enable bits are always cleared at reset. The
reset vector enable bit is cleared or set at reset depending on
external jumper configuration. This allows the board
designer to use external jumpers to enable/disable Block A/B
ROM/Flash as the source of reset vectors.
The write enable bit is cleared at reset for both blocks.
2. The base address for each block is software programmable.
At reset, Block AÕs base address is $FF000000 and Block BÕs
base address is $FF400000.
As noted above, in addition to appearing at the programmed
base address, the first 1Mbyte of Block A/B also appears at
$FFF00000-$FFFFFFFF if the reset vector enable bit is set.
3. The assumed size for each block is software programmable. It
is initialized to its smallest setting at reset.
4. The assumed device type for Block A/B is determined by an
external jumper at reset time. It also is available as a status bit
and cannot be changed by software.
When the width status bit is cleared, the blockÕs ROM /Flash
is considered to be t16 bits wide, where each Falcon interfaces
to 8 bits. In this mode, the following rules are enforced:

3-16

Functional Description

a. only single-byte writes are allowed (all other sizes are
ignored), and
b. all reads are allowed (multiple accesses are performed to
the ROM/Flash devices when the read is for greater than
one byte).
When the width status bit is set, the blockÕs ROM/Flash is
considered to be 64 bits wide, where each Falcon interfaces
with 32 bits. In this mode, the following rules are enforced:
a. only aligned, 4-byte writes should be attempted (all other
sizes are ignored), and
b. all reads are allowed (multiple accesses to the ROM/Flash
device are performed for burst reads).
More information about ROM/Flash is found in the section on the
Programming Model in this chapter.
In order to place code correctly in the ROM/Flash devices, address
mapping information is required. Table 3-7 shows how PowerPC
60x addresses map to the ROM/Flash addresses when ROM/Flash
is 16 bits wide (8 bits per Falcon). Table 3-8 shows how they map
when Flash is 64 bits wide (32 bits per Falcon).

3-17

Falcon ECC Memory Controller Chip Set

Table 3-7. PowerPC 60x to ROM/Flash Address Mapping when ROM/Flash is
16 Bits Wide (8 Bits per Falcon)

PowerPC 60x A0-A31

ROM/Flash A22-A0

ROM/Flash Device Selected

$XX000000

$000000

Upper

$XX000001

$000001

Upper

$XX000002

$000002

Upper

$XX000003

$000003

Upper

$XX000004

$000000

Lower

$XX000005

$000001

Lower

$XX000006

$000002

Lower

$XX000007

$000003

Lower

$XX000008

$000004

Upper

$XX000009

$000005

Upper

$XX00000A

$000006

Upper

$XX00000B

$000007

Upper

$XX00000C

$000004

Lower

$XX00000D

$000005

Lower

$XX00000E

$000006

Lower

$XX00000F

$000007

Lower

.
.
.

$XXFFFFF8

$7FFFFC

Upper

$XXFFFFF9

$7FFFFD

Upper

$XXFFFFFA

$7FFFFE

Upper

$XXFFFFFB

$7FFFFF

Upper

$XXFFFFFC

$7FFFFC

Lower

$XXFFFFFD

$7FFFFD

Lower

$XXFFFFFE

$7FFFFE

Lower

$XXFFFFFF

$7FFFFF

Lower

3-18

Functional Description

Table 3-8. PowerPC 60x to ROM/Flash Address Mapping when ROM/Flash
is 64 Bits Wide (32 Bits per Falcon)
PowerPC 60x A0-A31

ROM/Flash A22-A0

ROM/Flash Device Selected

$X0000000

$000000

Upper

$X0000001

$000000

Upper

$X0000002

$000000

Upper

$X0000003

$000000

Upper

$X0000004

$000000

Lower

$X0000005

$000000

Lower

$X0000006

$000000

Lower

$X0000007

$000000

Lower

$X0000008

$000001

Upper

$X0000009

$000001

Upper

$X000000A

$000001

Upper

$X000000B

$000001

Upper

$X000000C

$000001

Lower

$X000000D

$000001

Lower

$X000000E

$000001

Lower

$X000000F

$000001

Lower

.
.
.

$X3FFFFF0

$7FFFFE

Upper

$X3FFFFF1

$7FFFFE

Upper

$X3FFFFF2

$7FFFFE

Upper

$X3FFFFF3

$7FFFFE

Upper

$X3FFFFF4

$7FFFFE

Lower

$X3FFFFF5

$7FFFFE

Lower

$X3FFFFF6

$7FFFFE

Lower

$X3FFFFF7

$7FFFFE

Lower

$X3FFFFF8

$7FFFFF

Upper

3-19

Falcon ECC Memory Controller Chip Set

Table 3-8. PowerPC 60x to ROM/Flash Address Mapping when ROM/Flash
is 64 Bits Wide (32 Bits per Falcon) (Continued)

PowerPC 60x A0-A31

ROM/Flash A22-A0

ROM/Flash Device Selected

$X3FFFFF9

$7FFFFF

Upper

$X3FFFFFA

$7FFFFF

Upper

$X3FFFFFB

$7FFFFF

Upper

$X3FFFFFC

$7FFFFF

Lower

$X3FFFFFD

$7FFFFF

Lower

$X3FFFFFE

$7FFFFF

Lower

$X3FFFFFF

$7FFFFF

Lower

Refresh/Scrub
Refresh/Scrub is done differently based on which DRAM blocks
are populated: (A and/or B) but not (C and D), or (A and/or B) and
(C and/or D).
Blocks A and/or B Present, Blocks C and D Not Present
The Falcon pair performs refresh by doing a burst of four RAS_
cycles approximately once every 60µs. This increases to once every
30µs when certain DRAM devices are used. (Controlled by the
ram_fref bit in the status registers.) RAS_ is asserted to both of
Blocks A and B during each of the 4 cycles. Along with RAS_, the
Falcon pair also asserts CAS_ with (OE_ then WE_) to one of the
blocks during one of the four cycles. This forms a read-modifywrite which is a scrub cycle to that location.
After each of the 4 cycles, the DRAM row address increments by
one. When it reaches all 1Õs, it rolls over and starts over at 0. Each
time the row address rolls over, the block that is scrubbed toggles
between A and B. Every second time that the row address rolls
over, which of the 4 cycles that is a scrub changes from 1st to 2nd,
from 2nd to 3rd, from 3rd to 4th, or from 4th to 1st. Every eighth
time that the row address rolls over, the column address increments
by one. When the column address reaches all 1Õs, it rolls over and
starts over at 0. Each time the column address rolls over, the
SC1, SC0 bits in the scrub/refresh register increment by one.

3-20

Functional Description

Blocks A and/or B Present, Blocks C and/or D present
The Falcon pair performs refresh by doing a burst of four RAS_
cycles approximately once every 30µs. This increases to once every
15µs when certain DRAM devices are used. (Controlled by the
ram_fref bit in the status registers.) RAS_ is asserted to blocks A and
B during the first cycle, to blocks C and D during the second cycle,
back to blocks A and B during the third cycle and to blocks C and
D during the fourth cycle. Along with RAS, the Falcon pair also
asserts CAS_ with (OE_ then WE_) to one of the blocks during one
of the four cycles. This forms a read-modify-write which is a scrub
cycle to that location.
After the second and fourth cycles, the DRAM row address
increments by one. When it reaches all 1Õs, it rolls over and starts
over at 0. Each time the row address rolls over, the block that is
scrubbed toggles between A/C and B/D. Every second time the
row address rolls over, which of the 4 cycles that is a scrub changes
from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th, or from 4th to 1st.
Every eighth time that the row address rolls over, the column
address increments by one. When the column address reaches all
1Õs, it rolls over and starts over at 0. Each time the column address
rolls over, the SC1, SC0 bits in the scrub/refresh register increment
by one.

Note that an entire refresh of DRAM is achieved every time the row
address rolls over, and that an entire scrub of DRAM is achieved
every time the column address rolls over.
During scrub cycles, if the SWEN bit is cleared, the Falcon pair does
not perform the write portion of the read-modify write cycle. If the
SWEN bit is set, the Falcon pair does perform the write unless it
encounters a double-bit error during the read.
If so enabled, single- and double-bit scrub errors are logged, and
the PowerPC 60x bus master is notified via interrupt.

3-21

Falcon ECC Memory Controller Chip Set

DRAM Arbitration
The Falcon pair has 3 different entities that can request use of the
DRAM cycle controller:

❏

The PowerPC 60x bus master

❏

The tester

❏

The refresher/scrubber

The Falcon pairÕs arbiters assign priority with the
refresher/scrubber highest, the tester next, and the PowerPC 60x
bus lowest. When no requests are pending, the arbiter defaults to
providing a PowerPC 60x bus grant. This provides fast response for
PowerPC 60x bus cycles. Although the arbiter operates on a priority
basis, it also performs a pseudo round-robin algorithm in order to
prevent starving any of the requesting entities. Note that PowerPC
DRAM or ROM/Flash accesses should not be attempted while the
tester is in operation.

Chip Defaults
Some jumper option kinds of parameters need to be configured by
software in the Falcon pair. These parameters include DRAM and
ROM/Flash attributes. In order to set up these parameters
correctly, software needs some way of knowing about the devices
that are being used with the Falcon pair. One way of providing this
information is by using the power-up status registers in the Falcon
pair. At power-up reset, each Falcon latches the level on its RD0RD63 signal pins into its power-up status registers. Since the RD
signal pins are high impedance during reset, their power-up reset
level can be controlled by pullup/pulldown resistors. (They are
pulled-up internally.)

3-22

Functional Description

External Register Set
Each chip in the Falcon pair has an external register chip select pin
which enables it to talk to an external set of registers. This interface
is like the ROM/Flash interface but with less flexibility. It is
intended for the system designer to be able to implement generalpurpose status/control signals with this external set. Refer to the
Programming Model in this chapter for a description of this register
set.

CSR Accesses
An important part of the operation of a Falcon pair is that the value
written to the internal control registers and SRAM in each of the
two chips must be the same at all times. In order to facilitate this,
writes to the pair itself are restricted to the upper Falcon only.
When software writes to the upper Falcon, hardware in the two
chips shifts this same value into the lower Falcon before the cycle
completion is acknowledged. The shifting is done in holding
registers such that the actual update of the control register happens
on the same CLOCK cycle in both chips. Writes to the upper Falcon
can be single-byte or 4-byte. Writes to the lower Falcon are ignored.
This duplicating of writes from upper to lower applies to the
FalconÕs internal registers and SRAM only. No duplication is
performed for writes to DRAM, ROM/Flash, or the External
Register set.

3-23

3Falcon ECC Memory Controller Chip Set

Falcon ECC Memory Controller Chip Set

Programming Model
CSR Architecture
The CSR (control and status register set) consists of the chipÕs
internal register set, its test SRAM, and its external register set. The
base address of the CSR is hard coded to the address $FEF80000 (or
$FEF90000 if the SIO pin is low at reset).
Accesses to the CSR are mapped differently depending on whether
they are reads or writes. For reads, CSR data read on the upper half
of the data bus comes from the upper Falcon while CSR data read
on the lower half of the data bus comes from the lower Falcon. (See
Figure 3-4.)

Lower
Data Bus

MPC60x Master
Upper
Data Bus

CSR

Upper FALCON

Lower FALCON

1903 9609

Figure 3-4. Data Path for Reads from the Falcon Internal CSRs
For writes, internal register or test SRAM data written on the upper
half of the data bus goes to the upper Falcon and is automatically
copied by hardware to the lower Falcon. Internal register or test SRAM

3-24

Programming Model

data written on the lower half of the data bus does not go to either
Falcon in the pair, but the access is terminated normally with TA_.
(See Figure 3-5.).

Lower
Data Bus

Upper
Data Bus

MPC60x Master

CSR

Upper FALCON

Lower FALCON

1904 9609

Figure 3-5. Data Path for Writes to the Falcon Internal CSRs
External register data that is written on the upper data bus goes
through the upper Falcon, while data that is written on the lower
data bus goes through the lower Falcon. Unlike the internal register
set, there is no automatic copying of upper data to lower data for the
external register set.
CSR read accesses can have a size of 1, 2, 4, or 8 bytes with any
alignment. CSR write accesses are restricted to a size of 1 or 4 bytes
and they must be aligned. Some Tester registers are limited to 4byte only accesses. Figures 3-6, 3-7, 3-8, and 3-9 show the memory
map for the different kinds of access.

3-25

Falcon ECC Memory Controller Chip Set

$FEF80000

Upper Falcon

$FEF80001

Upper Falcon

$FEF80002

Upper Falcon

$FEF80003

Upper Falcon

$FEF80004

Lower Falcon

$FEF80005

Lower Falcon

$FEF80006

Lower Falcon

$FEF80007

Lower Falcon

$FEF80008

Upper Falcon

$FEF80009

Upper Falcon

$FEF807FF

Lower Falcon

1905 9609

Figure 3-6. Memory Map for Byte Reads to the CSR

3-26

Programming Model

$FEF80000

Both Falcons

$FEF80001

Both Falcons

$FEF80002

Both Falcons

$FEF80003

Both Falcons

3
Writes not allowed Here

$FEF80004
$FEF80005
$FEF80006
$FEF80007
$FEF80008

Both Falcons

$FEF80009

Both Falcons

$FEF807FF

1906 9609

Figure 3-7. Memory Map for Byte Writes to the Internal Register Set and Test SRAM

3-27

Falcon ECC Memory Controller Chip Set

$FEF80000

Upper Falcon

$FEF80004

Lower Falcon

$FEF80008

Upper Falcon

$FEF8000C

Lower Falcon

$FEF807FC

Lower Falcon

1907 9609

Figure 3-8. Memory Map for 4-Byte Reads to the CSR

Writes not allowed Here
$FEF80000

Both Falcons

$FEF80004
$FEF80008

Both Falcons

$FEF8000C

$FEF807FC

1908 9609

Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set and Test SRAM

3-28

Programming Model

Register Summary
Table 3-9 on the following page shows a summary of the CSR. Note
that the table only shows addresses for accesses to the upper
Falcon. To get the addresses for accesses to the lower Falcon, add 4
to the address shown. Since the only way to write to the lower
FalconÕs internal register set and test SRAM is to duplicate what is
written to the upper Falcon, only the addresses shown in the table
should be used for writes to them. Writes to the external register set
are not duplicated from upper to lower, so writes to them can be via
the upper or lower Falcon.

3-29

Falcon ECC Memory Controller Chip Set

Table 3-9. Register Summary
27

adis

ram fref

ram spd0

ram spd1

chipu

isa_hole

aonly_en

RAM C
SIZ

ram d en

ram c en

RAM B
SIZ
RAM B BASE

RAM C BASE

RAM D
SIZ
RAM D BASE
por
mcken

mien

sien

tien

FEF80038

scof

esblk0

ERROR_SYNDROME

esblk1

embt

esbt

scien

derc

esen

escb

elog

rwcb

refdis

FEF80028

SBE COUNT

ERROR_ADDRESS
rtest2

rtest1

rtest0

swen

scb0

scb1

FEF80048

ROW ADDRESS

rom b we

tb0

tb1

tzbit

tfail

tpass

tsse

trun

TEST PC

rom b en

ROM B
SIZ

rom a we

ROM A
SIZ

rom a en

rom_a_rv rom_b_rv

ROM B BASE

FEF80058

COL ADDRESS
rom_a_64 rom_b_64

ROM A BASE

FEF80050

FEF80068

CLK FREQUENCY

FEF80060

FEF80020

ram b en

ram a en

RAM A
SIZ
RAM A BASE

FEF80040

DEVID
REVID

FEF80018

FEF80030

VENDID

FEF80008

FEF80010

FEF80000

BIT # ---->

TEST IR

FEF80070

TEST A0

FEF80078

TEST A1

FEF80080
FEF80088

TEST D0 (Upper 8 Bits)

FEF80090

TEST D0 (Middle 32 Bits)

FEF80098

TEST D0 (Lower 32 Bits)

3-30

Programming Model

Table 3-9. Register Summary (Continued)
FEF800A0
FEF800A8

TEST D1 (Upper 8 Bits)

FEF800B0

TEST D1 (Middle 32 Bits)

FEF800B8

TEST D1 (Lower 32 Bits)

FEF800C0
FEF800C8

TEST D2 (Upper 8 Bits)

FEF800D0

TEST D2 (Middle 32 Bits)

FEF800D8

TEST D2 (Lower 32 Bits)

FEF800E0
FEF800E8

TEST D3 (Upper 8 Bits)

FEF800F0

TEST D3 (Middle 32 Bits)

FEF800F8

TEST D3 (Lower 32 Bits)

FEF80100

CTR32

FEF80200
.
.
FEF803F8
FEF80400

PR_STAT1

FEF80408
.
.
FEF804F8
FEF80500

PR_STAT2

FEF80508
.
.
FEF807F8
FEF80800
.
.
FEF80BF8

TEST SRAM

3-31

Falcon ECC Memory Controller Chip Set

Table 3-9. Register Summary (Continued)

FEF80C00
.
.
FEF87FF8
FEF88000
.
.
FEF8FFF8

BIT # ---->

EXTERNAL REGISTER SET

Notes 1. All shaded bit fields are reserved and read as zeros.
2. All status bits are shown in italics.
3. All control bits are shown with underline.
4. All control-and-status bits are shown with italics and
underline.

Detailed Register Bit Descriptions
The following sections describe the registers and their bits in detail.
The possible operations for each bit in the register set are as follows:
R

The bit is a read only status bit.

R/W The bit is readable and writable.
R/C The bit is cleared by writing a one to itself.
C

The bit is readable. Writing a zero to the bit will clear it.

The possible states of the bits after local and power-up reset are as
defined below.

3-32

The bit is affected by power-up reset.

The bit is affected by local reset.

The bit is not affected by reset.

Programming Model

The effect of reset on the bit is variable.

Vendor/Device Register

RESET

READ ONLY

DEVID

VENDID

OPERATION

NAME

BIT

$FEF80000

ADDRESS

VENDID This read-only register contains the value $1507. It is
the vendor number assigned to Motorola Inc.
Note that the current value ($1507) of VENDID is not
correct. The correct vendor ID should be $1057. This
issue will be treated as just an erratum for now.

Note

This read-only register contains the value $4802. It is
the device number for the Falcon.

DEVID

Revision ID/ General Control Register
$FEF80008

ADDRESS

chipu
ram spd1
ram spd0
ram fref
adis
0
0
0
isa_hole
aonly_en
0
0
0
0
0
0
R
R
R

X
X
X
X

VP
X
X

VP
0P
0P
1P
0P
X
X

R
R
R
R

R
R/W
R/W
R/W
R/W
R
R

READ ONLY

R
X
R/W 0 PL

READ ZERO

REVID

RESET

REVID

NAME

OPERATION

BIT

The REVID bits are hard-wired to indicate the
revision level of the Falcon. The value for the Þrst
revision is $01, for the second is $02.

3-33

Falcon ECC Memory Controller Chip Set

aonly_en Normally, the Falcon pair responds to address-only
cycles only if they fall within the address range of
one of its enabled map decoders. When the aonly_en
bit is set, the Falcon pair also responds to addressonly cycles that fall outside of the range of its
enabled map decoders provided they are not
acknowledged by some other slave within 8 clock
periods. aonly_en is read-only and reßects the level
that was on the CKD4 pin at power-up reset.

isa_hole

When it is set, isa_hole disables any of the DRAM or
ROM/Flash blocks from responding to PowerPC
accesses in the range from $000A0000 to $000BFFFF.
This has the effect of creating a hole in the DRAM
memory map for accesses to ISA. When isa_hole is
cleared, there is no hole created in the memory map.

adis

When adis is clear, fast page mode operation is used
for back-to-back pipelined accesses to the same page
within DRAM. When it is set, RAS is cycled between
accesses. This bit should normally be cleared unless
the Falcon has a problem operating that way.

ram fref

Some DRAMs require that they be refreshed at the
rate of 7.8µs per row rather than the standard 15.6µs
per row. If any of the DRAM devices require the
higher rate, then the ram fref bit should be left set,
otherwise, it can be cleared.

ram spd0,ram spd1 Together ram spd0,ram spd1 control
DRAM timing used by the Falcon pair. They are
encoded as shown:
Table 3-10. ram spd1,ram spd0 and DRAM Type
ram spd0, ram spd1 DRAM Speed DRAM Type
%00
70ns
Page Mode
%01
60ns
Page Mode
%10
Reserved
%11
50ns
EDO

3-34

Programming Model

EDO refers to DRAMs that use an output latch on
data. Sometimes these parts are referred to as
Hyper-Page Mode DRAMs.

To ensure reliable operation, the system should
always be conÞgured so that these two bits are
encoded to match the slowest devices that are used.
Also, if any parts do not support EDO, then these
bits must set for Page Mode. The only case in which
it is permissible to set ram spd0,ram spd1 for Ò50ns,
EDOÓ is when all parts are 50ns and all support
EDO.
chipu indicates which of the two positions within
the Falcon pair is occupied by this chip. When chipu
is low, this chip is connected to the lower half of the
PowerPC 60x data bus and it does not drive TA_ or
AACK_. When chipu is high, this chip is connected
to the upper half of the PowerPC 60x data bus, and
it drives TA_ and AACK_. chipu reßects the level
that was on the ERCS_ pin during power-up reset.

chipu

DRAM Attributes Register
$FEF80010

ADDRESS

ram d siz2
ram d siz1
ram d siz0
0
0
0
0
ram d en
ram c siz2
ram c siz1
ram c siz0
0
0
0
0
ram c en
ram b siz2
ram b siz1
ram b siz0
0
0
0
0
ram b en
ram a siz2
ram a siz1
ram a siz0
0
0
0
0
ram a en

NAME

BIT

R
R
R
R
R/W

R
R
R
R
R/W
R/W
R/W
R/W

RESET

X
X
X
X
0 PL

X
X
X
X
0 PL
0P
0P
0P

R/W 0 P
R/W 0 P
R/W 0 P

OPERATION

ram a/b/c/d en enables accesses to the
ram a/b/c/d en
corresponding block of DRAM when set, and
disables them when cleared.

3-35

Falcon ECC Memory Controller Chip Set

ram a/b/c/d siz0-2
These control bits deÞne the size of their
corresponding block of DRAM. Table 3-11 shows the
block conÞguration assumed by the Falcon pair for
each value of ram siz0-ram siz2.

Table 3-11. Block_A/B/C/D Configurations
ram a/b/c/d
siz0-2

Block
SIZE

Devices Used

%000

0MB

1Mx4Õs

4Mb

1Mx18Õs

16Mb

1Mx36Õs

4Mb/1Mb

2Mx8Õs

16Mb

144

4Mx1Õs

4Mb

4Mx4Õs

16Mb

4Mx18Õs

64Mb

4Mx36Õs

16Mb/4Mb

8Mx8Õs

64Mb

144

16Mx1Õs

16Mb

16Mx4Õs

64Mb

16Mx36Õs

64Mb/16Mb

144

64Mx1Õs

64Mb

%001

%010

%011

%100

%101

16MB

32MB

64MB

128MB

256MB

%110

1024MB

%111

0MB

Technology

Comments

Block Not Present

SIMM/DIMM

Reserved

Note that it is important that all of the ram a/b/c/d siz0-2 bits be set
to accurately match the actual size of their corresponding blocks.
This includes clearing them to %000 if their corresponding blocks
are not present. Failure to do so will cause problems with
addressing and with scrub error logging.

3-36

Programming Model

DRAM Base Register
$FEF80018

ADDRESS

NAME

RAM A BASE

RAM B BASE

RAM C BASE

RAM D BASE

OPERATION

READ/WRITE

0 PL

RESET

BIT

RAM A/B/C/D BASE These control bits deÞne the base address
for their blockÕs DRAM. RAM A/B/C/D BASE bits 07/8-15/16-23/24-31 correspond to PowerPC 60x
address bits 0 - 7. For larger DRAM sizes, the lower
signiÞcant bits of A/B/C/D BASE are ignored. This
means that the blockÕs base address will always
appear at an even multiple of its size. Note that bit 0
is MSB.
Also note that the combination of RAM_X_BASE
and ram_x_siz should never be programmed such
that DRAM responds at the same address as the
CSR, ROM/Flash, External Register Set, or any other
slave on the PowerPC bus.
CLK Frequency Register
$FEF80020

ADDRESS

por
0
0
0
0
0
0
0

CLK FREQUENCY
READ/WRITE

READ ZERO

R/C
R
R
R
R
R
R

42 P

1P
X
X
X
X
X
X

RESET

OPERATION

NAME

BIT

CLK FREQUENCY These bits should be programmed with
the hexadecimal value of the operating CLOCK
frequency in MHz (i.e. $42 for 66MHz). When these
bits are programmed this way, the chipÕs prescale
counter produces a 1MHz output. The output of the
chip prescale counter is used by the

3-37

Falcon ECC Memory Controller Chip Set

refresher/scrubber and the 32-bit counter. After
power-up, this register is initialized to $42 (for
66MHz).

por is set by the occurrence of power up reset. It is
cleared by writing a one to it. Writing a 0 to it has no
effect.

por

ECC Control Register
$FEF80028

ADDRESS

mcken R/W 0 PL

X
X
X
X
X
X

R
R
R
R
R
R

0 PL
0 PL
0 PL
0 PL
X
X
X

R/W
R/W
R/W
R/W
R
R
R

X
1 PL
0 PL
0 PL
X
X
X
X

0
0
0
0
0
0
0

R
R/W
R/W
R/W
R
R
R
R

3-38

READ ZERO

RESET

OPERATION

mien
sien
tien
scien
0
0
0
0
derc
rwcb
refdis
0
0
0
0
0

NAME

BIT

refdis

When set, refdis causes the refresher and all of its
associated counters and state machines to be cleared
and maintained that way until refdis is removed
(cleared). If a refresh cycle is in process when refdis
is updated by a write to this register, the update does
not take effect until the refresh cycle has completed.
This prevents the generation of illegal cycles to the
DRAM when refdis is updated.

rwcb

rwcb, when set, causes reads and writes to DRAM
from the PowerPC 60x bus to access check-bit data
rather than normal data. The data path used for this
mode is DH24-31 for check-bit data controlled by the
upper Falcon, and DL24-31 for check-bit data
controlled by the lower Falcon. Each 8-bit check-bit
location services 64 bits of normal data. The 64 bits
of data are all within the same Falcon. Each Falcon
provides every other 32 bits of data in the normal
mode. The Þgure below shows the relationship
between normal data and check-bit data.

Programming Model

Connected to
Lower Falcon

Connected to
Upper Falcon

Normal
View of
Data
(rwcb=0)
32 bits

Check-bit
View
(rwcb=1
11707.00 9701

So, for example, the check-bits that correspond to
the 64 bits of data found in normal mode (rwcb=0) at
$00001000-$00001003 and $00001008-$0000100b are
written and read in check-bit mode (rwcb=1) at
location $00001003.
Note that if test software wishes to force a single-bit
error to a location using the rwcb function, the
scrubber may correct the location before the test
software gets a chance to check for the single-bit
error. This can be avoided by disabling scrub writes.
Also note that writing bad check-bits can set the elog
bit in the Error Logger Register. The writing of
check-bits causes the Falcon to perform a readmodify-write to DRAM. If the location to which
check-bits are being written has a single- or doublebit error, data in the location may be altered by the
write check-bits operation. To avoid this, it is

3-39

Falcon ECC Memory Controller Chip Set

recommended that the derc bit also be set while the
rwcb bit is set. A possible sequence for performing
read-write check-bits is as follows:

1. Disable scrub writes by clearing the swen bit if it is set.
2. Stop all DRAM Tester operations by clearing the trun bit.
3. Make sure software is not using DRAM at this point, because
while rwcb is set, DRAM will not function as normal
memory.
4. Set the derc and rwcb bits in the Data Control register.
5. Perform the desired read and/or write check-bit operations.
6. Clear the derc and rwcb bits in the Data Control register.
7. Perform the desired testing related to the location/locations
that have had their check-bits altered.
8. Enable scrub writes by setting the swen bit if it was set before.
derc

Setting derc to one alters Falcon pair operation as
follows:

1. During reads, data is presented to the PowerPC 60x data bus
uncorrected from the DRAM array.
2. During single-beat writes, data is written without correcting
single-bit errors that may occur on the read portion of the
read-modify-write. Check-bits are generated for the data
being written.
3. During single-beat writes, the write portion of the readmodify-write happens regardless of whether there is a
multiple-bit error during the read portion. No correction of
data is attempted. Check-bits are generated for the data being
written.
4. During refresh/scrub cycles, if swen is set, a read-write to
DRAM happens with no attempt to correct data bits. Checkbits are generated for the data being written.

3-40

Programming Model

derc is useful for initializing DRAM after power-up
and for testing DRAM, but it should be cleared
during normal system operation.

3
scien

When scien is set, the rolling over of the
SBE COUNT register causes the INT_ signal pin to
pulse true.

tien

When tien is set, the setting of the tpass or the tfail
bit causes the INT_ signal pin to pulse true.

sien

When sien is set, the logging of a single-bit error
causes the INT_ signal pin to pulse true.

mien

When mien is set, the logging of a non-correctable
error causes the INT_ signal pin to pulse true.

mcken

When mcken is set, the detection of a multiple-bit
error during a PowerPC read or write causes the
Falcon to pulse its machine check interrupt request
pin (MCP_) true. When mcken is cleared, the Falcon
does not ever assert its MCP_ pin.
The Falcon never asserts its MCP_ pin in response to
a multiple-bit error detected during a scrub cycle.

!
Caution

Note that the INT_ and MCP_ pins are the only nonpolled notification that a multiple-bit error has
occurred. The Falcon pair does not assert TEA as a result
of a multiple bit error. In fact, the Falcon pair does not
have a TEA_ signal pin and it assumes that the system
does not implement TEA_.

3-41

Falcon ECC Memory Controller Chip Set

Error Logger Register
$FEF80030

ADDRESS

R/C
R
R
R
R
R
R
R
0P
X
X
X
X
X
X
X

The Error Logger and Error Address Registers behave the same as
the other registers, in that data written to the upper Falcon is
automatically duplicated in the lower Falcon. They also behave the
same as the other registers, in that status read from the upper
Falcon pertains to the upper Falcon, and status read from the lower
Falcon pertains to the lower Falcon. Unlike most of the other
registers, however, it is normal for this status to differ between the
two. This is due to the fact that each Falcon is connected to its own
set of DRAMs. The upper Falcon can log an error during a cycle and
the local Falcon not, or vice-versa. Or they can both log an error
during the same cycle and have the attributes of the errors differ.
Because of the above, software needs to monitor both the upper and
lower FalconÕs Error Logger and Error Address Registers. This
includes checking the elog bit from the upper Falcon and from the
lower Falcon. When the upper Falcon logs an error, it updates its
attribute bits (escb, embt, esbt, ERROR_SYNDROME, eblk0, eblk1,
and ERROR_ADDRESS) to match the results of the read cycle for
its portion of the DRAM array. When the lower Falcon logs an
error, it updates its attribute bits to match the results of the read
cycle for its portion of the DRAM array.
While the logging of errors by one Falcon in a pair does not affect
the logging of errors by the other, writing to the Error Logger
Register control bits affects both Falcons. This is of particular
interest as regards the elog bit. Writing a one to the elog bit clears
the elog bit for both the upper and lower Falcons. Because of this,

3-42

scof
0
0
0
eblk1
eblk0
0
0

RESET

XP
XP
0 PL
XP
X
X
X

READ ONLY

READ/WRITE

OPERATION

R
R
R/W
R
R
R
R

SBE_COUNT

R/C

ERROR_SYNDROME

esbt
embt
esen
escb
0
0
0
elog

NAME

BIT

Programming Model

software needs to check the status of both upper and lower Error
Logger and Error Address Registers before it clears the elog bits.
Otherwise, it could miss a logged error.
elog

When set, elog indicates that a single- or a multiplebit error has been logged by its Falcon. If elog is set
by a multiple-bit error, then no more errors will be
logged until software clears it. If elog is set by a
single-bit error, then no more single-bit errors will be
logged until software clears it, however if elog is set
by a single-bit error and a multiple-bit error occurs,
the multiple-bit error will be logged and the singlebit error information overwritten. elog can only be
set by the logging of an error and cleared by the
writing of a one to itself or by power-up reset.

escb

escb indicates the entity that was accessing DRAM at
the last logging of a single- or multiple-bit error by
its Falcon. If escb is 1, it indicates that the scrubber
was accessing DRAM. If escb is 0, it indicates that the
PowerPC 60x bus master was accessing DRAM.
Note that the DRAM Tester cannot cause an error to
be logged.

esen

When set, esen allows errors that occur during
scrubs to be logged. When cleared, esen does not
allow errors that occur during scrubs to be logged.

embt

embt is set by the logging of a multiple-bit error in its
Falcon. It is cleared by the logging of a single-bit
error in its Falcon. It is undeÞned after power-up
reset. A FalconÕs syndrome code is meaningless if its
embt bit is set.

esbt

esbt is set by the logging of a single-bit error in its
Falcon. It is cleared by the logging of a multiple-bit
error in its Falcon. When a Falcon logs a single-bit
error, its syndrome code indicates which bit was in
error. (Refer to the section on ECC Codes.)

3-43

Falcon ECC Memory Controller Chip Set

ERROR_SYNDROME
ERROR_SYNDROME reßects the
syndrome value at the last logging of an error by its
Falcon. This eight-bit code indicates the position of
the data error. When all the bits are zero, there was
no error. Note that if the logged error was noncorrectable, then these bits are meaningless. Refer to
the section on ECC Codes for a decoding of the
syndromes.

esblk0,esblk1 Together these two bits indicate which block of
DRAM was being accessed when their Falcon
logged a scrub error. esblk0,esblk1 are 0,0 for Block
A; 0,1 for Block B; 1,0 for Block C; and 1,1 for Block
D.
scof

scof is set by the SBE COUNT register rolling over
from $FF to $00. It is cleared by software writing a 1
to it.

SBE COUNT This register keeps track of the number of singlebit errors that have occurred since it was last cleared.
It counts up by one each time its half of the Falcon
pair detects a single-bit error (independent of the
state of the elog bit). It is cleared by power-up reset
and by software writing all zeros to it. When
SBE COUNT rolls over from $FF to $00, its Falcon
sets the scof bit. It also pulses the INT_ signal low if
the scien bit is set.

3-44

3Falcon ECC Memory Controller Chip Set
0Programming Model
Programming Model

Error_Address Register
$FEF80038

ADDRESS

READ ONLY

X
X
X
X

RESET

R
R
R
R

OPERATION

0
0
0
0

ERROR_ADDRESS

NAME

BIT

ERROR_ADDRESS These bits reßect the value that
corresponds to bits 0-27 of the PowerPC 60x address
bus when their Falcon last logged an error during a
PowerPC access to DRAM. They reßect the value of
the DRAM row and column addresses if the error
was logged during a scrub cycle. In this case, bits
2-14 correspond to row address signals 0-12
respectively and bits 15-27 correspond to column
address signals 0-12 respectively. Refer to Table 3-18
in the subsection on Sizing DRAM in the section on
Software Considerations. It shows how PowerPC
addresses correspond to DRAM row and column
addresses.
Scrub/Refresh Register
$FEF80040

ADDRESS

R
R/W
R
R
R
R
R
R

X
0P
X
X
X
X
X
0P

READ ZERO

0P
0P
0P
X
X
X
X

RESET

R/W
R/W
R/W
R
R
R
R

OPERATION

scb0,scb1 These bits increment every time the scrubber
completes a scrub of the entire DRAM. When these
bits reach binary 11, they roll over to binary 00 and
continue. They are cleared by power-up reset.

3-45

rtest2
rtest1
rtest0
0
0
0
0
0
swen
0
0
0
0
0
scb1
scb0

NAME

BIT

Falcon ECC Memory Controller Chip Set

When set, swen allows the scrubber to perform
write cycles. When cleared, swen prevents scrubber
writes.

swen

rtest0,1,2 The rtest bits enable certain refresh counter test
modes. Table 3-12 shows their encodings. Note that
these test modes are not intended to be used once the
chip is in a system.
Table 3-12. rtest encodings
Test Mode selected
Normal Counter Operation
RA counts at 16x
RA counts at 256x
RA is always at roll value for CA
CA counts at 16x
CA counts at 256x
reserved
reserved

rtest0,rtest1,rtest2
%000
%001
%010
%011
%100
%101
%110
%111

Refresh/Scrub Address Register
$FEF80048

ADDRESS

X
X
X

ROW ADDRESS These bits form the row address counter
used by the refresher/scrubber for all blocks of
DRAM. The row address counter increments by one
after each refresh/scrub cycle. When it reaches all 1s,
it rolls back over to all 0s and continues counting.
ROW ADDRESS is readable and writable for test
purposes.

3-46

R
R
R

READ/WRITE

0
0
0

READ/WRITE

COL ADDRESS

X
X
X

RESET

ROW ADDRESS

R
R
R

OPERATION

0
0
0

NAME

BIT

Programming Model

Note that within each block, the most signiÞcant bits
of ROW ADDRESS are used only when their DRAM
devices are large enough to require them.

COL ADDRESS These bits form the column address counter
used by the refresher/scrubber for all blocks of
DRAM. The counter increments by one every eighth
time the ROW ADDRESS rolls over. COL ADDRESS
is readable and writable for test purposes.
Note that within each block, the most signiÞcant bits
of COL ADDRESS are only used when their DRAM
devices are large enough to require them.
ROM A Base/Size Register
$FEF80050

ADDRESS

rom a we
rom a en
rom_a_rv

0
0
0
0
0
R

R/W
R/W
R/W
R
R
R
R

0 PL
0 PL
VP
X
X
X
X

0 PL
0 PL
0 PL
VP

$FF0 PL

R/W
R/W
R/W
R

READ ZERO

rom a siz2
rom a siz1
rom a siz0
rom_a_64

READ/WRITE

RESET

ROM A BASE
NAME

OPERATION

BIT

These control bits deÞne the base address for
ROM A BASE
ROM/Flash Block A. ROM A BASE bits 0-11
correspond to PowerPC 60x address bits 0 - 11
respectively. For larger ROM/Flash sizes, the lower
signiÞcant bits of ROM A BASE are ignored. This
means that the blockÕs base address will always
appear at an even multiple of its size. ROM A BASE
is initialized to $FF0 at power-up or local bus reset.
Note that in addition to the programmed address,
the Þrst 1Mbyte of Block A also appears at
$FFF00000 - $FFFFFFFF if the rom_a_rv bit is set and
the rom_b_rv bit is cleared.

3-47

Falcon ECC Memory Controller Chip Set

Also note that the combination of ROM_A_BASE
and rom_a_siz should never be programmed such
that ROM/Flash Block A responds at the same
address as the CSR, DRAM, External Register Set, or
any other slave on the PowerPC bus.

rom_a_64 rom_a_64 indicates the width of ROM/Flash
device/devices being used for Block A. When
rom_a_64 is cleared, Block A is 16 bits wide, where
each Falcon interfaces to 8 bits. When rom_a_64 is
set, Block A is 64 bits wide, where each Falcon
interfaces to 32 bits. rom_a_64 matches the value
that was on the CKD2 pin at power-up reset. It
cannot be changed by software.
rom a siz The rom a siz control bits are the size of ROM/Flash
for Block A. They are encoded as shown in Table 3-13.
Table 3-13. ROM Block A Size Encoding

3-48

rom a siz

BLOCK
SIZE

%000

1MB

%001

2MB

%010

4MB

%011

8MB

%100

16MB

%101

32MB

%110

64MB

%111

Reserved

Programming Model

rom_a_rv rom_a_rv and rom_b_rv determine which if either of
Blocks A and B is the source of reset vectors or any
other access in the range $FFF00000 - $FFFFFFFF as
shown in the table below.
Table 3-14. rom_a_rv and rom_b_rv encoding
rom_a_rv

rom_b_rv

Result

Neither Block is the source
of reset vectors.

Block B is the source of reset
vectors.

Block A is the source of reset
vectors.

Block B is the source of reset
vectors.

rom_a_rv is initialized at power-up reset to match
the value on the CKD0 pin.
rom a en When rom a en is set, accesses to Block A
ROM/Flash in the address range selected by ROM
A BASE are enabled. When rom a en is cleared, they
are disabled.
rom a we When rom a we is set, writes to Block A ROM/Flash
are enabled. When rom a we is cleared, they are
disabled. Note that if rom_a_64 is cleared, only 1byte writes are allowed. If rom_a_64 is set, only 4byte writes are allowed. The Falcon ignores other
writes. If a valid write is attempted and rom a we is
cleared, the write does not happen but the cycle is
terminated normally. See Table 3-15 for details of
ROM/Flash accesses.

3-49

Falcon ECC Memory Controller Chip Set

Table 3-15. Read/Write to ROM/Flash

Cycle

Transfer
Size

Alignment

rom_x_64

rom_x_we

Falcon Response

write

1-byte

Normal termination, but
no write to ROM/Flash

write

1-byte

Normal termination,
write occurs to
ROM/Flash

write

1-byte

No Response

write

4-byte

Misaligned

No Response

write

4-byte

Aligned

No Response

write

4-byte

Aligned

Normal termination, but
no write to ROM/Flash

write

4-byte

Aligned

Normal termination,
write occurs to
ROM/Flash

write

2,3,5,6,7,
8,32-byte

No Response

read

Normal Termination

ROM B Base/Size Register
$FEF80058

ADDRESS

rom b we
rom b en
rom_b_rv

0 PL
0 PL
VP
X
X
X
X

These control bits deÞne the base address for
ROM B BASE
ROM/Flash Block B. ROM B BASE bits 0-11
correspond to PowerPC 60x address bits 0 - 11
3-50

R/W
R/W
R/W
R
R
R
R

0 PL
0 PL
0 PL
VP

0
0
0
0
0

$FF4 PL

R/W
R/W
R/W
R

READ ZERO

rom b siz2
rom b siz1
rom b siz0
rom_b_64

READ/WRITE

RESET

ROM B BASE
NAME

OPERATION

BIT

Programming Model

respectively. For larger ROM/Flash sizes, the lower
signiÞcant bits of ROM B BASE are ignored. This
means that the blockÕs base address will always
appear at an even multiple of its size. ROM B BASE
is initialized to $FF4 at power-up or local bus reset.
Note that in addition to the programmed address,
the Þrst 1Mbyte of Block B also appears at
$FFF00000 - $FFFFFFFF if the rom_b_rv bit is set.
Also note that the combination of ROM_B_BASE
and rom_b_siz should never be programmed such
that ROM/Flash Block B responds at the same
address as the CSR, DRAM, External Register Set, or
any other slave on the PowerPC bus.
rom_b_64 rom_b_64 indicates the width of ROM/Flash
device/devices being used for Block B. When
rom_b_64 is cleared, Block B is 16 bits wide, where
each Falcon interfaces to 8 bits. When rom_b_64 is
set, Block B is 64 bits wide, where each Falcon
interfaces to 32 bits. rom_b_64 matches the inverse of
the value that was on the CKD3 pin at power-up
reset. It cannot be changed by software.

3-51

Falcon ECC Memory Controller Chip Set

rom b siz The rom b siz control bits are the size of ROM/Flash
for Block B. They are encoded as shown in Table
3-16.

Table 3-16. ROM Block B Size Encoding
rom b siz

BLOCK
SIZE

%000

1Mbytes

%001

2Mbytes

%010

4Mbytes

%011

8Mbytes

%100

16Mbytes

%101

32Mbytes

%110

64Mbytes

%111

Reserved

rom_b_rv rom_b_rv and rom_a_rv determine which if either of
Blocks A and B is the source of reset vectors or any
other access in the range $FFF00000 - $FFFFFFFF as
shown in Table 3-14.
rom_b_rv is initialized at power-up reset to match
the inverse of the value on the CKD1 pin.
rom b en When rom b en is set, accesses to Block B
ROM/Flash in the address range selected by ROM
B BASE are enabled. When rom b en is cleared they
are disabled.
rom b we When rom b we is set, writes to Block B ROM/Flash
are enabled. When rom b we is cleared they are
disabled. Refer back to Table 3-15 for more details.

3-52

Programming Model

DRAM Tester Control Registers
The tester should not be used by software. The trun and
tsse bits (bits 0 and 1 of the register at address
$FEF80060) should never be set.

!
Caution

32-Bit Counter
$FEF80100

ADDRESS

CTR32

NAME

READ/WRITE

OPERATION

0 PL

RESET

CTR32

Note

CTR32 is a 32-bit, free-running counter that
increments once per microsecond if the
CLK_FREQUENCY register has been programmed
properly. Notice that CTR32 is cleared by power-up
and local reset. It does not exist in Revision 1 of
Falcon.

When the system clock is a fractional frequency, such
as 66.67MHz, CTR32 will count at a fractional amount
faster or slower than 1MHz, depending on the
programming of the CLK_FREQUENCY Register.

3-53

BIT

Falcon ECC Memory Controller Chip Set

Test SRAM
(Deleted)

3-54

Programming Model

Power-Up Reset Status Register 1
$FEF80400

ADDRESS

BIT

PR_STAT1

NAME
OPERATION

READ

RESET

PR_STAT1

PR_STAT1 (power-up reset status) reßects the
value that was on the RD0-RD31 signal pins at
power-up reset. This register is read-only.

For descriptions of how this register is used in the
MVME2300 series boards, refer to the Falcon-Controlled
System Registers in Chapter 1, especially the System
Configuration Register and the Memory Configuration
Register.

Note

Power-Up Reset Status Register 2
$FEF80500

ADDRESS

BIT

PR_STAT2

NAME
OPERATION

READ

RESET

PR_STAT2

PR_STAT2 (power-up reset status) reßects the
value that was on the RD32-RD63 signal pins at
power-up reset. This register is read-only.

3-55

Falcon ECC Memory Controller Chip Set

External Register Set
$FEF88000 - $FEF8FFF8

ADDRESS

EXTERNAL REGISTER SET

READ/WRITE
X PL

EXTERNAL REGISTER SET
The EXTERNAL REGISTER SET is user provided
and is external to the Falcon pair. The Falcon pair
provides a static RAM style interface for the external
registers. The external registers can be SRAM, ROM,
Flash or some other user device. There can be one
device connected to either the upper or lower
Falcon, or there can be two devices with one
connected to each Falcon. The devices can be 8, 16, or
32 bits wide. The data path to the external devices is
via the RD32-RD63 pins. Reads to the external
devices can be any size except burst. Note that if the
devices are less than 32 bits wide, reads to unused
data lanes will yield undeÞned data. Note that
writes are restricted to one or 4-byte length only. 4byte writes can be used for any size device, data
should be placed on the correct portion of the data
bus so that valid data is written to the device. Data
duplication is turned off for the EXTERNAL
REGISTER SET so writes can be to either the upper
Falcon, or to the lower Falcon.
Note For descriptions of how these registers are used in the
MVME2300 series boards, refer to the Falcon-Controlled
System Registers in Chapter 1, especially the System
External Cache Control Register and the CPU Control
Register.

3-56

RESET

OPERATION

NAME

BIT

3Falcon ECC Memory Controller Chip Set

Software Considerations

Software Considerations
This section contains information that will be useful in
programming a system that uses the Falcon pair.

Parity Checking on the PowerPC Bus
The Falcon does not generate parity on the PowerPC address or
data buses. Because of this, the appropriate registers in the MPC60x
should be programmed to disable parity checking for the address
bus and for the data bus.

Programming ROM/Flash Devices
Those who program devices to be controlled by the Falcon should
make note of the address mapping that is shown in Table 3-7 and in
Table 3-8. For example, when using 8-bit devices, the code will be
split so that every other 4-byte segment goes in each device.

Writing to the Control Registers
Software should not change control register bits that affect DRAM
operation while DRAM is being accessed. Because of pipelining,
software should always make sure that the two accesses before and
after the updating of critical bits are not DRAM accesses. A possible
scenario for trouble would be to execute code out of DRAM while
updating the critical DRAM control register bits. The preferred
method is to be executing code out of ROM/Flash and avoiding
DRAM accesses while updating these bits.
Since software has no way of controlling refresh accesses to DRAM,
the hardware is designed so that updating control bits
coincidentally with refreshes is not a problem. An exception to this
is the ROW_ADDRESS and COL_ADDRESS bits. It is not intended
that software write to these bits anyway.

3-57

Falcon ECC Memory Controller Chip Set

As with DRAM, software should not change control register bits
that affect ROM/Flash while the affected Block is being accessed.
This generally means that the ROM/Flash size, base address,
enable, write enable, etc. are changed only while executing initially
in the reset vector area ($FFF00000 - $FFFFFFFF).

Sizing DRAM
The following routine can be used to size DRAM for the Falcon.
Initialize the Falcon control register bits to a known state as follows:
1. Clear the isa_hole bit.
2. Make sure that ram_fref and ram_spd0,ram_spd1 are correct.
3. Set CLK_FREQUENCY to match the operating frequency.
4. Clear the refdis, rwcb bits.
5. Set the derc bit.
6. Clear the scien, tien, sien, and mien bits.
7. Clear the mcken bit.
8. Clear the swen and rtest0,rtest1,rtest2 bits.
9. Make sure that ROM/Flash banks A and B are not enabled to
respond in the range from $00000000 to $40000000.
10. Make sure that no other devices respond in the range from
$00000000 to $40000000.
For each block:
1. Set the blockÕs base address to $00000000.
2. Enable the block and make sure that the other three blocks are
disabled.
3. Set the blockÕs size control bits. Start with the largest possible
(1024MB).

3-58

Software Considerations

4. Write differing 64-bit data patterns to certain addresses
within the block. The data patterns do not matter as long as
each 64-bit data pattern is unique. The addresses to be written
vary depending on the size that is currently being checked
and are specified in Table 3-17. Table 3-18 shows how
PowerPC addresses correspond to DRAM row/column
addresses.
5. Read back all of the addresses that have been written.
If all of the addresses still contain exactly what was written
then the blockÕs size has been found. It is the size for which
the block is currently programmed.
If any of the addresses do not match exactly then the amount
of memory is less than that for which it is currently
programmed. Sizing needs to continue for this block by
programming its control bits to the next smaller size and
repeating steps 4 and 5.
6. If no match is found for any size then the block is
unpopulated and has a size of 0MB.
Each size that is checked has a specific set of locations that must be
written and read. The following table shows the addresses that go
with each size.
Table 3-17. Sizing Addresses
1024MB

256MB

128MB

64MB

32MB

16MB

$00000000
$20000000

$00000000,
$02000000,
$08000000,
$0A000000

$00000000
$00002000
$02000000
$02002000
$04000000
$04002000
$06000000
$06002000

$00000000
$00002000
$02000000
$02002000

$00000000
$00001000
$00002000
$00003000
$01000000
$01001000
$01002000
$01003000

$00000000

3-59

Falcon ECC Memory Controller Chip Set

Table 3-18. PowerPC 60x Address to DRAM Address Mappings

RA ---->
Block Size
|
V
16MB

ROW
COL

1024MB

3-60

A9 A10 A11 A12 A13 A14 A15 A16 A17

A18 A19 A20 A21 A22 A23 A24 A25 A26 A27
A18 A6

A9 A10 A11 A12 A13 A14 A15 A16 A17

A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27
A6

A9 A10 A11 A12 A13 A14 A15 A16 A17

A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27

COL
ROW

256MB

A18 A7

COL
ROW

128MB

A18 A19 A20 A21 A22 A23 A24 A25 A26 A27

COL
ROW

64MB

A19 A18 A8

ROW
32MB

COL

A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27
A8

A9 A10 A11 A12 A13 A14 A15 A16 A17

ROW

A9 A10 A11 A12 A13 A14 A15 A16 A17

COL

A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27

ECC Codes

ECC Codes
When the Falcon reports a single-bit error, software can use the
syndrome that was logged by the Falcon (upper or lower
depending where the error occurred) to determine which bit was in
error. Table 3-19 shows the syndrome for each possible single bit
error. Table 3-20 shows the same information ordered by
syndrome. In order to relate this information to PowerPC addresses
and bit numbers, the user needs to understand how the Falcon pair
positions PowerPC data in DRAM. See the section on Data Paths for
an explanation of this.
Note that Tables 3-19 and 3-20 are the same whether the Falcon is
configured as upper or as lower.
Table 3-19. Syndrome Codes Ordered by Bit in Error
Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome
rd0

$4A

rd16

$92

rd32

$A4

rd48

$29

ckd0

$01

rd1

$4C

rd17

$13

rd33

$C4

rd49

$31

ckd1

$02

rd2

$2C

rd18

$0B

rd34

$C2

rd50

$B0

ckd2

$04

rd3

$2A

rd19

$8A

rd35

$A2

rd51

$A8

ckd3

$08

rd4

$E9

rd20

$7A

rd36

$9E

rd52

$A7

ckd4

$10

rd5

$1C

rd21

$07

rd37

$C1

rd53

$70

ckd5

$20

rd6

$1A

rd22

$86

rd38

$A1

rd54

$68

ckd6

$40

rd7

$19

rd23

$46

rd39

$91

rd55

$64

ckd7

$80

rd8

$25

rd24

$49

rd40

$52

rd56

$94

rd9

$26

rd25

$89

rd41

$62

rd57

$98

rd10

$16

rd26

$85

rd42

$61

rd58

$58

rd11

$15

rd27

$45

rd43

$51

rd59

$54

rd12

$F4

rd28

$3D

rd44

$4F

rd60

$D3

rd13

$0E

rd29

$83

rd45

$E0

rd61

$38

rd14

$0D

rd30

$43

rd46

$D0

rd62

$34

rd15

$8C

rd31

$23

rd47

$C8

rd63

$32

3-61

Falcon ECC Memory Controller Chip Set

Table 3-20. Single-Bit Errors Ordered by Syndrome Code

Syn- Bit Syn- Bit Syn- Bit Syn- Bit Syn- Bit Syn- Bit Syn- Bit Syn- Bit
drome
drome
drome
drome
drome
drome
drome
drome
$00

$20

ckd5

$40

ckd6

$60

$80

ckd7

$A0

$C0

$E0

rd45

$01

ckd0

$21

$41

$61

rd42

$81

$A1

rd38

$C1

rd37

$E1

$02

ckd1

$22

$42

$62

rd41

$82

$A2

rd35

$C2

rd34

$E2

$03

$23

rd31

$43

rd30

$63

$83

rd29

$A3

$C3

$E3

$04

ckd2

$24

$44

$64

rd55

$84

$A4

rd32

$C4

rd33

$E4

$05

$25

rd8

$45

rd27

$65

$85

rd26

$A5

$C5

$E5

$06

$26

rd9

$46

rd23

$66

$86

rd22

$A6

$C6

$E6

$07

rd21

$27

$47

$67

$87

$A7

rd52

$C7

$E7

$08

ckd3

$28

$48

$68

rd54

$88

$A8

rd51

$C8

rd47

$E8

$09

$29

rd48

$49

rd24

$69

$89

rd25

$A9

$C9

$E9

rd4

$0A

$2A

rd3

$4A

rd0

$6A

$8A

rd19

$AA

$CA

$EA

$0B

rd18

$2B

$4B

$6B

$8B

$AB

$CB

$EB

$0C

$2C

rd2

$4C

rd1

$6C

$8C

rd15

$AC

$CC

$EC

$0D

rd14

$2D

$4D

$6D

$8D

$AD

$CD

$ED

$0E

rd13

$2E

$4E

$6E

$8E

$AE

$CE

$EE

$0F

$2F

$4F

rd44

$6F

$8F

$AF

$CF

$EF

$10

ckd4

$30

$50

$70

rd53

$90

$B0

rd50

$D0

rd46

$F0

$11

$31

rd49

$51

rd43

$71

$91

rd39

$B1

$D1

$F1

$12

$32

rd63

$52

rd40

$72

$92

rd16

$B2

$D2

$F2

$13

rd17

$33

$53

$73

$93

$B3

$D3

rd60

$F3

$14

$34

rd62

$54

rd59

$74

$94

rd56

$B4

$D4

$F4

rd12

$15

rd11

$35

$55

$75

$95

$B5

$D5

$F5

$16

rd10

$36

$56

$76

$96

$B6

$D6

$F6

$17

$37

$57

$77

$97

$B7

$D7

$F7

$18

$38

rd61

$58

rd58

$78

$98

rd57

$B8

$D8

$F8

$19

rd7

$39

$59

$79

$99

$B9

$D9

$F9

$1A

rd6

$3A

$5A

$7A

rd20

$9A

$BA

$DA

$FA

$1B

$3B

$5B

$7B

$9B

$BB

$DB

$FB

$1C

rd5

$3C

$5C

$7C

$9C

$BC

$DC

$FC

$1D

$3D

rd28

$5D

$7D

$9D

$BD

$DD

$FD

$1E

$3E

$5E

$7E

$9E

rd36

$BE

$DE

$FE

$1F

$3F

$5F

$7F

$9F

$BF

$DF

$FF

3-62

Data Paths

Data Paths
Because of the Falcon ÒpairÓ architecture, data paths can be
confusing. Figure 3-10 attempts to show the placement of data that
is written by a PowerPC master to DRAM. Table 3-21 shows the
same information in tabular format.

3-63

ra12=1

ra12=0

Falcon ECC Memory Controller Chip Set

a[27:28]=3

a[27:28]=2

a[27:28]=1

a[27:28]=0

rd63

rd32
rd31

Lower Falcon’s
DRAM

dl31

rd0

ra12=1

ra12=0

PowerPC
dl0
Data
dh31

rd63

dh0

rd32
rd31

Upper Falcon’s
DRAM

rd0
1909 9609

Figure 3-10. PowerPC Data to DRAM Data Correspondence
3-64

Data Paths

Table 3-21. PowerPC Data to DRAM Data Mapping
PowerPC
A[27]

A[28]

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Data Bits RA[12]
dh[00:07]
dh[08:15]
dh[16:23]
dh[24:31]
dl[00:07]
dl[08:15]
dl[16:23]
dl[24:31]
dh[00:07]
dh[08:15]
dh[16:23]
dh[24:31]
dl[00:07]
dl[08:15]
dl[16:23]
dl[24:31]
dh[00:07]
dh[08:15]
dh[16:23]
dh[24:31]
dl[00:07]
dl[08:15]
dl[16:23]
dl[24:31]
dh[00:07]
dh[08:15]
dh[16:23]
dh[24:31]
dl[00:07]
dl[08:15]
dl[16:23]
dl[24:31]

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

DRAM Array
Upper Falcon DRAM
Lower Falcon DRAM
Data Bits
Data Bits
rd[00:07]
rd[08:15]
rd[16:23]
rd[24:31]
rd[00:07]
rd[08:15]
rd[16:23]
rd[24:31]
rd[32:39]
rd[40:47]
rd[48:55]
rd[56:63]
rd[32:39]
rd[40:47]
rd[48:55]
rd[56:63]
rd[00:07]
rd[08:15]
rd[16:23]
rd[24:31]
rd[00:07]
rd[08:15]
rd[16:23]
rd[24:31]
rd[32:39]
rd[40:47]
rd[48:55]
rd[56:63]
rd[32:39]
rd[40:47]
rd[48:55]
rd[56:63]

3-65

Falcon ECC Memory Controller Chip Set

3-66

4Universe (VMEbus to PCI) Chip

Note

All of the information in this chapter (except the section
Universe Chip Problems after a PCI Reset) is taken from
the Universe User Manual, which is listed in
ManufacturersÕ Documents in Appendix A. Refer to that
manual for complete information.

General Information
Introduction
The Universe VMEbus interface chip (CA91C042) provides a
reliable high performance 64-bit VMEbus to PCI interface in one
device.
Designed by Tundra Semiconductor Corporation in consultation
with Motorola, the Universe is compliant with the VME64
specification and is tuned to the new generation of high speed
processors.
The Universe is ideally suited for CPU boards acting as both master
and slave in the VMEbus system, and is particularly fitted for PCI
local systems. The Universe is manufactured in a CMOS process.

Product Overview - Features
❏

Fully compliant, 64-bit, 33 MHz PCI local bus interface

❏

Fully compliant, high performance 64-bit VMEbus interface

❏

Integral FIFOs for write posting to maximize bandwidth
utilization

❏

Programmable DMA controller with linked list support

4-1

Universe (VMEbus to PCI) Chip

❏

VMEbus transfer rates of 60-70 MBytes/sec

❏

Complete suite of VMEbus address and data transfer modes
Ð A32/A24/A16 master and slave
Ð D64 (MBLT)/D32/D16/D08 master and slave
Ð BLT, ADOH, RMW, LOCK

4
❏

Automatic initialization for slave-only applications

❏

Flexible register set, programmable from both the PCI bus
and VMEbus ports

❏

Full VMEbus system controller functionality

❏

IEEE 1149.1 JTAG testability support, and

❏

Available in 313-pin Plastic BGA and 324-pin contact Ceramic
BGA

Functional Description
Architectural Overview
This section introduces the general architecture of the Universe.
This description makes reference to the functional block diagram
provided in Figure 4-1 that follows. Notice that for each of the
interfaces, VMEbus and PCI bus, there are three functionally
distinct modules: master module, slave module, and interrupt
module. These modules are connected to the different functional
channels operating in the Universe. These channels are:

4-2

❏

VME Slave Channel

❏

PCI Bus Slave Channel

❏

DMA Channel

❏

Interrupt Channel

❏

Functional Description

The Architectural Overview is organized into the following
sections:
❏

VMEbus Interface

❏

PCI Bus Interface

❏

Interrupter and Interrupt Handler

❏

DMA Controller

These sections describe the operation of the Universe in terms of the
different modules and channels illustrated in Figure 4-1.

DMA Channel
DMA bidirectional FIFO

PCI Bus
Interface

VMEbus
Interface
VMEbus Slave Channel

PCI
Master

posted writes FIFO
prefetch read FIFO
coupled read

VME
Slave

PCI Bus Slave Channel

PCI
BUS

PCI
Slave

posted writes FIFO
coupled read logic

VME
Master

VMEbus

Interrupt Channel

PCI
Interrupts

Interrupt Handler
Interrupter

VME
Interrupts

1894 9609

Figure 4-1. Architectural Diagram for the Universe

4-3

Universe (VMEbus to PCI) Chip

VMEbus Interface
Universe as VMEbus Slave
The Universe VME Slave Channel accepts all of the addressing and
data transfer modes documented in the VME64 specification
(except A64 and those intended to support 3U applications, i.e. A40
and MD32). Incoming write transactions from the VMEbus may be
treated as either coupled or posted, depending upon the
programming of the VMEbus slave image. (Refer to VME Slave
Images in the Universe User Manual.) With posted write transactions,
data is written to a Posted Write Receive FIFO (RXFIFO), and the
VMEbus master receives data acknowledgment from the Universe.
Write data is transferred to the PCI resource from the RXFIFO
without the involvement of the initiating VMEbus master (Refer to
Posted Writes in the Universe User Manual for a full explanation of
this operation.). With a coupled cycle, the VMEbus master only
receives data acknowledgment when the transaction is complete on
the PCI bus. This means that the VMEbus is unavailable to other
masters while the PCI bus transaction is executed.

Read transactions may be prefetched or coupled. If enabled by the
user, a prefetched read is initiated when a VMEbus master requests
a block read transaction (BLT or MBLT) and this mode is enabled.
When the Universe receives the block read request, it begins to fill
its Read Data FIFO (RDFIFO) using burst transactions from the PCI
resource. The initiating VMEbus master then acquires its block read
data from the RDFIFO rather than from the PCI resources directly.
Universe as VMEbus Master
The Universe becomes VMEbus master when the VME Master
Interface is internally requested by the PCI Bus Slave Channel, the
DMA Channel, or the Interrupt Channel. The Interrupt Channel
always has priority over the other two channels. Several
mechanisms are available to configure the relative priority that the
PCI Bus Slave Channel and DMA Channel have over ownership of
the VMEbus Master Interface.

4-4

Functional Description

The UniverseÕs VME Master Interface generates all of the
addressing and data transfer modes documented in the VME64
specification (except A64 and those intended to support 3U
applications, i.e. A40 and MD32). The Universe is also compatible
with all VMEbus modules conforming to pre-VME64
specifications. As VMEbus master, the Universe supports ReadModify-Write (RMW), and Address-Only-with-Handshake
(ADOH) but does not accept RETRY* as a termination from the
VMEbus slave. The ADOH cycle is used to implement the VMEbus
Lock command allowing a PCI master to lock VMEbus resources.
PCI Bus Interface
Universe as PCI Slave
Read transactions from the PCI bus are always processed as
coupled. Write transactions may be either coupled or posted,
depending upon the setting of the PCI bus slave image. (Refer to
PCI Bus Slave Images in the Universe User Manual.) With a posted
write transaction, write data is written to a Posted Write Transmit
FIFO (TXFIFO) and the PCI bus master receives data
acknowledgment from the Universe with zero wait states.
Meanwhile, the Universe obtains the VMEbus and writes the data
to the VMEbus resource independent of the initiating PCI master.
(Refer to Posted Writes in the Universe User Manual for a full
description of this operation.)
To allow PCI masters to perform RMW and ADOH cycles, the
Universe provides a Special Cycle Generator. The Special Cycle
Generator can be used in combination with a VMEbus ownership
function to guarantee PCI masters exclusive access to VMEbus
resources over several VMEbus transactions, and. (Refer to
Exclusive Accesses and RMW and ADOH Cycles in the Universe User
Manual for a full description of this functionality.)

4-5

Universe (VMEbus to PCI) Chip

Universe as PCI Master
The Universe becomes PCI master when the PCI Master Interface is
internally requested by the VME Slave Channel or the DMA
Channel. There are mechanisms provided which allow the user to
configure the relative priority of the VME Slave Channel and the
DMA Channel.

Interrupter and Interrupt Handler
Interrupter
The Universe interrupt channel provides a flexible scheme to map
interrupts to either the PCI bus or VMEbus interface. Interrupts are
generated from either hardware or software sources (Refer to
Interrupter in the Universe User Manual for a full description of
hardware and software sources.). Interrupt sources can be mapped
to any of the PCI bus or VMEbus interrupt output pins. Interrupt
sources mapped to VMEbus interrupts are generated on the
VMEbus interrupt output pins VIRQ#[7:1]. When a software and
hardware source are assigned the same VIRQn# pin, the software
source always has higher priority.
Interrupt sources mapped to PCI bus interrupts are generated on
one of the INT#[7:0] pins. To be fully PCI compliant, all interrupt
sources must be routed to a single INT# pin.
For VMEbus interrupt outputs, the Universe interrupter supplies
an 8-bit STATUS/ID to a VMEbus interrupt handler during the
IACK cycle, and optionally generates an internal interrupt to signal
that the interrupt vector has been provided. (Refer to VMEbus
Interrupt Generation in the Universe User Manual.)
Interrupts mapped to PCI bus outputs are serviced by the PCI
interrupt controller. The CPU determines which interrupt sources
are active by reading an interrupt status register in the Universe.
The source negates its interrupt when it has been serviced by the
CPU. (Refer to PCI Interrupt Generation in the Universe User Manual.)

4-6

Functional Description

VMEbus Interrupt Handling
A VMEbus interrupt triggers the Universe io generate a normal
VMEbus IACK cycle and generate the specified interrupt output.
When the IACK cycle is complete, the Universe releases the
VMEbus and the interrupt vector is read by the PCI resource
servicing the interrupt output. Software interrupts are ROAK,
while hardware, and internal interrupts are RORA.
DMA Controller
The Universe provides an internal DMA controller for high
performance data transfer between the PCI and VMEbus. DMA
operations between the source and destination bus are decoupled
through the use of a single bidirectional FIFO (DMAFIFO).
Parameters for the DMA transfer are software configurable in the
Universe registers. (Refer to DMA Controller in the Universe User
Manual.)
The principal mechanism for DMA transfers is the same for
operations in either direction (PCI to VME, or VME to PCI), only the
relative identity of the source and destination bus changes. In a
DMA transfer, the Universe gains control of the source bus and
reads data into its DMAFIFO. Following specific rules of DMAFIFO
operation (refer to FIFO Operation and Bus Ownership in the Universe
User Manual), it then acquires the destination bus and writes data
from its DMAFIFO.
The DMA controller can be programmed to perform multiple
blocks of transfers using entries in a linked list. The DMA will work
through the transfers in the linked-list following pointers at the end
of each linked-list entry. Linked-list operation is initiated through a
pointer in an internal Universe register, but the linked list itself
resides in PCI bus memory.

4-7

Universe (VMEbus to PCI) Chip

Registers - Universe Control and Status
Registers (UCSR)
The Universe Control and Status Registers (UCSR) facilitate host
system configuration and allow the user to control Universe
operational characteristics. The UCSRs are divided into three
groups:

❏

PCI Configuration Space (PCICS)

❏

VMEbus Control and Status Registers (VCSR), and

❏

Universe Device Specific Status Registers (UDSR)

The Universe registers are little-endian.
Figure 4-2 below summarizes the supported register access
mechanisms.
VMEbus Configuration
and Status Registers
(VCSR)

UNIVERSE DEVICE
SPECIFIC REGISTERS
(UDSR)

4 Kbytes

PCI CONFIGURATION
SPACE
(PCICS)

1895 9609

Figure 4-2. UCSR Access Mechanisms

4-8

Registers - Universe Control and Status Registers (UCSR)

Universe Register Map
Table 4-1 below lists the Universe registers by address offset. Tables
in the Universe User Manual provide detailed descriptions of each
register.
Address offsets in Table 4-1 below apply to accesses from the PCI
bus and to accesses from the VMEbus side using the VMEbus
Register Access Image (Refer to Registers in the Universe User
Manual.). For register accesses in CR/CSR space, be sure to add 508
KBytes (0x7F00) to the address offsets provided in the table.
Table 4-1. Universe Register Map
Offset

Name

000

PCI ConÞguration Space ID Register

PCI_ID

004

PCI ConÞguration Space Control and Status Register

PCI_CSR

008

PCI ConÞguration Class Register

PCI_CLASS

00C

PCI ConÞguration Miscellaneous 0 Register

PCI_MISC0

010

PCI ConÞguration Base Address Register

PCI_BS

014

PCI Unimplemented

018

PCI Unimplemented

01C

PCI Unimplemented

020

PCI Unimplemented

024

PCI Unimplemented

028

PCI Reserved

02C

PCI Reserved

030

PCI Unimplemented

034

PCI Reserved

038

PCI Reserved

03C

PCI ConÞguration Miscellaneous 1 Register

040 - 0FF

PCI_MISC1

PCI Unimplemented

4-9

Universe (VMEbus to PCI) Chip

Table 4-1. Universe Register Map (Continued)
Offset

100

PCI Slave Image 0 Control

LSI0_CTL

104

PCI Slave Image 0 Base Address Register

LSI0_BS

108

PCI Slave Image 0 Bound Address Register

LSI0_BD

10C

PCI Slave Image 0 Translation Offset

LSI0_TO

110

Universe Reserved

114

PCI Slave Image 1 Control

LSI1_CTL

118

PCI Slave Image 1 Base Address Register

LSI1_BS

11C

PCI Slave Image 1 Bound Address Register

LSI1_BD

120

PCI Slave Image 1 Translation Offset

LSI1_TO

124

Universe Reserved

128

PCI Slave Image 2 Control

LSI2_CTL

12C

PCI Slave Image 2 Base Address Register

LSI2_BS

130

PCI Slave Image 2 Bound Address Register

LSI2_BD

134

PCI Slave Image 2 Translation Offset

LSI2_TO

138

Universe Reserved

13C

PCI Slave Image 3 Control

LSI3_CTL

140

PCI Slave Image 3 Base Address Register

LSI3_BS

144

PCI Slave Image 3 Bound Address Register

LSI3_BD

148

PCI Slave Image 3 Translation Offset

LSI3_TO

14C - 16C

4-10

Name

Universe Reserved

170

Special Cycle Control Register

SCYC_CTL

174

Special Cycle PCI bus Address Register

SCYC_ADDR

178

Special Cycle Swap/Compare Enable Register

SCYC_EN

17C

Special Cycle Compare Data Register

SCYC_CMP

180

Special Cycle Swap Data Register

SCYC_SWP

Registers - Universe Control and Status Registers (UCSR)

Table 4-1. Universe Register Map (Continued)
Offset

Name

184

PCI Miscellaneous Register

LMISC

188

Special PCI Slave Image

SLSI

18C

PCI Command Error Log Register

L_CMDERR

190

PCI Address Error Log

LAERR

194 - 1FC

Universe Reserved

200

DMA Transfer Control Register

DCTL

204

DMA Transfer Byte Count Register

DTBC

208

DMA PCI bus Address Register

DLA

20C
210

Universe Reserved
DMA VMEbus Address Register

214
218

DVA

Universe Reserved
DMA Command Packet Pointer

21C

DCPP

Universe Reserved

220

DMA General Control and Status Register

DGCS

224

DMA Linked List Update Enable Register

D_LLUE

228 - 2FC

Universe Reserved

300

PCI Interrupt Enable

LINT_EN

304

PCI Interrupt Status

LINT_STAT

308

PCI Interrupt Map 0

LINT_MAP0

30C

PCI Interrupt Map 1

LINT_MAP1

310

VMEbus Interrupt Enable

VINT_EN

314

VMEbus Interrupt Status

VINT_STAT

318

VMEbus Interrupt Map 0

VINT_MAP0

31C

VMEbus Interrupt Map 1

VINT_MAP1

320

Interrupt Status/ID Out

STATID

4-11

Universe (VMEbus to PCI) Chip

Table 4-1. Universe Register Map (Continued)
Offset

324

VIRQ1 STATUS/ID

V1_STATID

328

VIRQ2 STATUS/ID

V2_STATID

32C

VIRQ3 STATUS/ID

V3_STATID

330

VIRQ4 STATUS/ID

V4_STATID

334

VIRQ5 STATUS/ID

V5_STATID

338

VIRQ6 STATUS/ID

V6_STATID

33C

VIRQ7 STATUS/ID

V7_STATID

340 - 3FC

Universe Reserved

400

Master Control

MAST_CTL

404

Miscellaneous Control

MISC_CTL

408

Miscellaneous Status

MISC_STAT

40C

User AM Codes Register

USER_AM

410 - EFC

Universe Reserved

F00

VMEbus Slave Image 0 Control

VSI0_CTL

F04

VMEbus Slave Image 0 Base Address Register

VSI0_BS

F08

VMEbus Slave Image 0 Bound Address Register

VSI0_BD

F0C

VMEbus Slave Image 0 Translation Offset

VSI0_TO

F10

Universe Reserved

F14

VMEbus Slave Image 1 Control

VSI1_CTL

F18

VMEbus Slave Image 1 Base Address Register

VSI1_BS

F1C

VMEbus Slave Image 1 Bound Address Register

VSI1_BD

F20

VMEbus Slave Image 1 Translation Offset

VSI1_TO

F24

4-12

Name

Universe Reserved

F28

VMEbus Slave Image 2 Control

VSI2_CTL

F2C

VMEbus Slave Image 2 Base Address Register

VSI2_BS

Registers - Universe Control and Status Registers (UCSR)

Table 4-1. Universe Register Map (Continued)
Offset

Name

F30

VMEbus Slave Image 2 Bound Address Register

VSI2_BD

F34

VMEbus Slave Image 2 Translation Offset

VSI2_TO

F38

Universe Reserved

F3C

VMEbus Slave Image 3 Control

VSI3_CTL

F40

VMEbus Slave Image 3 Base Address Register

VSI3_BS

F44

VMEbus Slave Image 3 Bound Address Register

VSI3_BD

F48

VMEbus Slave Image 3 Translation Offset

VSI3_TO

F4C - F6C

Universe Reserved

F70

VMEbus Register Access Image Control Register

VRAI_CTL

F74

VMEbus Register Access Image Base Address

VRAI_BS

F78

Universe Reserved

F7C

Universe Reserved

F80

VMEbus CSR Control Register

VCSR_CTL

F84

VMEbus CSR Translation Offset

VCSR_TO

F88

VMEbus AM Code Error Log

V_AMERR

F8C

VMEbus Address Error Log

VAERR

F90 - FEC

Universe Reserved

FF0

VME CR/CSR Reserved

FF4

VMEbus CSR Bit Clear Register

VCSR_CLR

FF8

VMEbus CSR Bit Set Register

VCSR_SET

FFC

VMEbus CSR Base Address Register

VCSR_BS

!
Caution

Register space marked as ÒReservedÓ should not be
overwritten. Unimplemented registers return a value of
0 on reads; writes complete normally.

4-13

Universe (VMEbus to PCI) Chip

Universe Chip Problems after a PCI Reset
Under the conditions described below, there are problems with the
Universe chip after a PCI reset.

Problem Description
The Universe chip is being enabled on the PCI bus after a PCI reset.
The problem does not occur after a board reset or power up.
The Universe is causing the "bye" command to hang the system.
The Universe Master Enable and Memory Enable in the PCI_CSR
(Configuration Space register) are enabled, even before the PCI_BS
register has been initialized. The symptoms can be alleviated by
modifying the PCI probe list such that the Universe PCI
configuration is done first.
The Configuration Space enables are not the only things enabled
after a PCI reset. The LSI0 image may also not be disabled by a PCI
reset, regardless of the enable bit's Power Up condition. If the image
is active at the time the reset occurs, it will remain enabled through
the reset. Additionally, the image is not staying at the same VME or
PCI address range.
MCG is not sure how many of the Power Up (P/U) Option bits
actually get latched as the Universe manual indicates they should.
At least the EN bit in the LSI0_CTL bit is not latched; in our board,
its P/U state is disabled but is not honored.
The software cannot completely correct this problem, but it can
minimize it. Two methods are presented:
Method 1:
1. Modify the PCI probe code to disable each PCI device prior to
writing its configuration space BS registers. This will prevent
the Universe from being active on the PCI bus while it has a
base addr of 0.
2. Once the Universe has been assigned a valid PCI Base
Address, enable register space access and disable the LSI0
slave image by clearing the EN bit of the LSI0_CTL register.
4-14

Universe Chip Problems after a PCI Reset

Method 2:
The port 92 reset code can be modiÞed to disable the LSI0
image prior to propagating the reset. This will cause the
LSI0 image to come up disabled.
We at MCG understand that both of these methods are awkward,
because the PCI probe/reset code should not contain any devicespecific patches. It should only need to follow the probing
conventions of the PCI specification. However, the only other
option appears to be avoidance of the LSI0 image altogether.
Tundra engineering describes the problem thus:
"Following are the most recently discovered bugs which will be
addressed in Universe 1.1.

1. LSIO image
Description: After a PCI reset, the LSIO image is still enabled,
but the base, bound, and translation offset changes value.
Workaround: None."
Motorola Firmware Engineering has implemented firmware workaround Method 1 in the PPCBug debugger release 3.1.
Note

The above notes describing this Universe chip PCI reset
problem are for those customers who replace the MCG
firmware with their own. Many of these customers
replace Motorola's firmware, or overwrite the
firmware settings for the Universe chip. These
customers may run into this problem.

Customers should not encounter any problems if they leave
Motorola's PPCBug debugger intact.

4-15

Universe (VMEbus to PCI) Chip

Examples
Example 1: MVME2600 Series Board Exhibits Problem
Use an MVME2600 series board to exhibit the problem.
Conditions:

MVME260x
running PPCOF2.0 Ir05
all the Universe code which initializes the Universe has been
disabled
(not the PCI code, the driver code)
modiÞed probe list to d,c,e,f,10
env parameters set such that LSI0 image will be enabled
1. Manually call each Universe initialize word, to duplicate
typical operation.
With the LSI0 enabled, the registers are:
CTL
BS
BD
TO
80821000 1012000 21012000 3efee000
2. Execute a bye command.
3. Manually enable access to the Universe register set, and read
the LSI0 registers:
CTL
BS
BD
TO
80820000
0
20000000
0
This means that the PCI reset changed the image as follows:
from supervisor address modifier to user
from PCI space base address 1012000 to 0 (size of 2000.0000
constant)
from VME address range 4000.0000 thru 5fff.ffff to a new
VMEbus range of 0 thru 1fff.ffff
It is still enabled.

4-16

Universe Chip Problems after a PCI Reset

Example 2: MVME3600 Series Board Acts Differently
Repeat portions of the earlier example on an MVME3600 series
board. This board had not previously been seen to hang upon PCI
reset. This particular board had customized values for the LSI0
setup parameters.
The Universe register init code is still disabled, and must be
manually called. The PCI init code is enabled, so the Universe PCI
memory space requirement defined by its Configuration Space
register at offset 0x10 is being accommodated and enabled during
PCI probing. PCI probe list d,c,e,f,10
1. After a P/U reset, before the init code has written the
registers, the LSI0 register settings are:
CTL
800000

BS
0

BD
0

TO
0

2. Run the init code and the LSI0 registers become:
CTL
BS
BD
TO
80821000 3000000 300a000 4d000000
3. After a bye, before the init code has run:
CTL
80820000

BS
0

BD
0

TO
0

Therefore the PCI reset caused the following changes in the
LSI0 image:
from supervisor to user
from PCI space base address 300.0000 to 0
from PCI space size of a000 to size of 0
from a VME base address of 5000.0000 to 0
This explains why it has never been a problem on this
particular MVME360x. The fact that the PCI base and PCI
bound registers are both 0 makes the effective size of the
image 0 bytes. Therefore this "enabled" image will never
utilize any PCI address space.

4-17

Universe (VMEbus to PCI) Chip

4. Now try modifying the LSI0 env parameters, to be the same
as those on the MVME260x which failed:
printenv
vme3_lsi0_vmeaddr
vme3_lsi0_size
vme3_lsi0_phi

1073741824
536870912
77

After a power-up, before the init code ran, the LSI0 values are:
800000 0 0 0
5. Do NOT run the init code, but press push-button RESET, and
the values become:
830001 f0000000 f0000000 0
6. Run the vme3 init code, and the values are set to
accommodate env parameters:
80821000 3000000 23000000 3d000000
7. Do a bye
The values before the init code runs are:
80820000 0 20000000 0
This gets the same results with the MVME360x as with the
MVME260x, and the difference seen earlier is related to the
values of the LSI0 slave at the time the PCI reset occurred.

4-18

Universe Chip Problems after a PCI Reset

Example 3: Universe Chip is Checked at Tundra
An engineer at Tundra Semiconductor Corporation had run a
simulation on the LSI0_CTL register, and could see that it was
going to be enabled after a port 92 reset. Motorola engineers
mentioned that the problem is primarily with the _BS, _BD, and
_TO registers. He said he would run more simulations to look at the
outcome on those registers. Motorola engineers explained what
they had seen.
The engineer at Tundra re-ran the simulation based on the
information given him. He saw exactly what the Motorola
engineers had seen, i.e., that the LSI0_BS, LSI0_BD, and LSI0_TO
values change, as well as the LSI0_CTL fields for program, super,
and vct. He checked to see if this is in fact what the Universe is
supposed to do.
The following are his results:
Register
-------LSI0_CTL
LSI0_BS
LSI0_BD
LSIO_TO

Before RST#
----------8082_5FFF
FFFF_FFFF
FFFF_FFFF
FFFF_FFFF

After RST#
----------8082_0001
F000_0000
F000_0000
0000_0000

Explanation:
All the fields in the LSI0 registers which are "Power-up Options"
cannot be reset by assertion of RST# (PCI reset).
The following fields in the LSIO registers cannot be reset by a PCI
reset:
LSI0_CTL register: EN, VAS, LAS
LSI0_BS register: Bits [31:28]
LSI0_BD register: Bits [31:28]
All the other fields in the LSI0 registers are reset to 0, which
explains why the PGM and SUPER fields changed, the translation
offset reset to 0, etc.

4-19

Universe (VMEbus to PCI) Chip

4-20

5Programming Details

Introduction
This chapter contains details of several programming functions that
are not tied to any specific ASIC chip.

PCI Arbitration
PCI arbitration is performed by the PCI-to-ISA Bridge (PIB) which
supports six PCI external PCI masters. The PIB can also be a PCI
master for ISA DMA functions. The arbitration assignments on the
MVME2300 series are as follows:
Table 5-1. PCI Arbitration Assignments
PCI BUS
REQUEST

PCI Master(s)

PIB (internal)

PIB

CPU

Raven ASIC

Request 0

PMC Slot 2

Request 1

PMC Slot 1

Request 2

PCIX Slot

Request 3

Ethernet

Request 4

Universe ASIC (VMEbus)

Upon power-up, the PIB defaults to a Òround-robinÓ arbitration
mode. The relative priority of each request/grant pair can be
customized via the PCI Priority Control Register 1. Refer to the
W83C553 Data Book for additional details.

5-1

Programming Details

Interrupt Handling
The interrupt architecture of the MVME2300 series SBC is shown in
the following figure:

INT

INT_

PIB
(8529 Pair)

Processor

MCP_

RavenMPIC
INT_

Processor
SERR_& PERR_
PCI Interrupts
ISA Interrupts

MCP_

11559.00 9609

Figure 5-1. MVME2300 Series Interrupt Architecture

5-2

Interrupt Handling

RavenMPIC
The Raven ASIC has a built-in interrupt controller that meets the
Multi-Processor Interrupt Controller (MPIC) Specification. This
MPIC supports up to two processors and 16 external interrupt
sources. There are also six other interrupt sources inside the MPIC:
Two cross-processor interrupts and four timer interrupts. All ISA
interrupts go through the 8259 pair in the PIB. The output of the PIB
then goes through the MPIC in the Raven. Refer to Chapter 2 on the
Raven for details on the RavenMPIC. The following table shows the
interrupt assignments for the RavenMPIC on the MVME2300
series:
Table 5-2. RavenMPIC Interrupt Assignments
MPIC
IRQ

Edge/
Level

Polarity

IRQ0

Level

High

PIB (8259)

IRQ1

Edge

Low

Falcon-ECC Error

IRQ2

Level

Low

PCI-Ethernet

IRQ3

N/A

Not used

IRQ4

N/A

Not used

IRQ5

Level

Low

PCI-VME INT 0 (Universe LINT0#)

3, 4

IRQ6

Level

Low

PCI-VME INT 1 (Universe LINT1#)

IRQ7

Level

Low

PCI-VME INT 2 (Universe LINT2#)

IRQ8

Level

Low

PCI-VME INT 3 (Universe LINT3#)

IRQ9

Level

Low

PCI-PMC1 INTA#, PMC2 INTB#, PCIX INTA#

IRQ10

Level

Low

PCI-PMC1 INTB#, PMC2 INTC#, PCIX INTB#

IRQ11

Level

Low

PCI-PMC1 INTC#, PMC2 INTD#, PCIX INTC#

IRQ12

Level

Low

PCI-PMC1 INTD#, PMC2 INTA#, PCIX INTD#

IRQ13

Level

Low

LM/SIG Interrupt 0

Interrupt Source

Notes

5-3

Programming Details

Table 5-2. RavenMPIC Interrupt Assignments (Continued)
MPIC
IRQ

Edge/
Level

Polarity

IRQ14

Level

Low

LM/SIG Interrupt 1

IRQ15

N/A

Not used

Interrupt Source

Notes
4

Notes:

1. Interrupt from the PCI/ISA Bridge.
2. Interrupt from the Falcon chipset for a single and/or double
bit memory error.
3. The mapping of interrupt sources from the VMEbus and
Universe internal interrupt sources is programmable via the
Local Interrupt Map 0 Register and the Local Interrupt Map 1
Register in the Universe ASIC.
4. These interrupts also appear at the PIB for backward
compatibility with older MVME1600 and PM603/4 modules.

8259 Interrupts
There are 15 interrupt requests supported by the PIB. These 15
interrupts are ISA-type interrupts that are functionally equivalent
to two 82C59 interrupt controllers. Except for IRQ0, IRQ1, IRQ2,
IRQ8_, and IRQ13, each of the interrupt lines can be configured for
either edge-sensitive mode or level-sensitive mode by
programming the appropriate ELCR registers in the PIB.
There is also support for four PCI interrupts, PIRQ3_-PIRQ0_. The
PIB has four PIRQ Route Control Registers to allow each of the PCI
interrupt lines to be routed to any of eleven ISA interrupt lines
(IRQ0, IRQ1, IRQ2, IRQ8_, and IRQ13 are reserved for ISA system
interrupts). Since PCI interrupts are defined as level-sensitive,
software must program the selected IRQ(s) for level-sensitive
mode. Note that more than one PCI interrupt can be routed to the
same ISA IRQ line. The PIB can be programmed to handle the PCI
interrupts if the RavenMPIC is either not present or not used.
5-4

Interrupt Handling

The following figure shows the interrupt structure of the PIB.

Timer1/Counter0
IRQ1

0
1
2

PIRQ0_

PIRQ Route
Control Register

IRQx

IRQ3
IRQ4

3
4

Controller 1
(INT1)

INTR

IRQ5
5
IRQ6
PIRQ1_

PIRQ2_

PIRQ Route
Control Register

IRQx

PIRQ Route
Control Register

IRQx

IRQ7

IRQ8
IRQ9
IRQ10
IRQ11

PIRQ3_

PIRQ Route
Control Register

IRQx

IRQ12

6
7

0
1
2
3
4

Controller 2
(INT2)

IRQ13
5
IRQ14
IRQ15

6
7

1897 9609

Figure 5-2. PIB Interrupt Handler Block Diagram

5-5

Programming Details

The assignments of the PCI and ISA interrupts supported by the
PIB are as follows:
Table 5-3. PIB PCI/ISA Interrupt Assignments

IRQ0

Interrupt Source

Edge

High

Timer 1 / Counter 0

IRQ1

N/A

Not used

3-10

IRQ2

Edge

High

Cascade Interrupt from INT2

IRQ8_

Edge

Low

ABORT Switch Interrupt

IRQ9

N/A

Not used

IRQ10

PIRQ0_

Level

Low

PCI-Ethernet Interrupt

2,3,4

IRQ11

PIRQ1_

Level

Low

Universe Interrupt (LINT0#)

2,3,4

IRQ12

N/A

Not used

IRQ13

N/A

Not used

IRQ14

PIRQ2_

N/A

Not used

IRQ15

PIRQ3_

Level

Low

PMC/PCIX Interrupt

IRQ3

N/A

Not used

IRQ4

Edge

High

COM1 (16550)

IRQ5

Level

High

LM/SIG Interrupt 0/1

IRQ6

N/A

Not used

IRQ7

N/A

Not used

5-6

INT1

Edge/
Level

Notes

PCI
IRQ

Polarity

ISA
IRQ

Controller

PRI

INT2

INT1

2,3,4

ISA DMA Channels

Notes:
1. Internally generated by the PIB.
2. After a reset, all ISA IRQ interrupt lines default to edgesensitive mode.
3. These PCI interrupts are routed to the ISA interrupts by
programming the PRIQ Route Control Registers in the PIB.
The PCI to ISA interrupt assignments in this table are
suggested. Each ISA IRQ to which a PCI interrupt is routed to
MUST be programmed for level-sensitive mode. Use this
routing for PCI interrupts only when the RavenMPIC is either
not present or not used.
4. The RavenMPIC, when present, should be used for these
interrupts.

ISA DMA Channels
The MVME2300 series does not implement any ISA DMA channels.

5-7

Programming Details

Exceptions
Sources of Reset
There are nine potential sources of reset on the MVME2300 series.
They are:
1. Power-On Reset

2. RESET Switch
3. Watchdog Timer Reset via the MK48T59 Timekeeper device
4. Port 92 Register via the PIB
5. I/O Reset via the Clock Divisor Register in the PIB
6. VMEbus SYSRESET# signal
7. Local software reset via the Universe ASIC (MISC_CTL
Register)
8. VME System Reset Via the Universe ASIC (MISC_CTL
Register)
9. VME CSR reset via the Universe ASIC (VCSR_SET Register)

5-8

Exceptions

The following table shows which devices are affected by various
reset sources:
Table 5-4. Reset Sources and Devices Affected
Falcon Chipset

PCI Devices

VMEbus (System
Controller)

Raven ASIC

✓

Reset Switch

✓

Watchdog (MK48T59)

✓

VME System Reset (SYSRESET# Signal)

✓

VME System Software Reset (MISC_CTL
Register)

✓

VME Local Software Reset (MISC_CTL
Register)

✓

VME CSR Reset (VCSR_SET Register)

✓

Hot Reset (Port 92 Register)

✓

PCI/ISA Reset (Clock Divisor Register)

ISA Devices

Processor (s)

Power-On

Device Affected

Soft Reset
Software can assert the SRESET# pin of any processor by
programming the Processor Init Register of the RavenMPIC
appropriately.

Universe Chip Problems after a PCI Reset
Under certain conditions, there can be problems with the Universe
chip after a PCI reset. Refer to Chapter 4 for the details.

5-9

Programming Details

Error Notification and Handling
The Raven and Falcon chipset can detect certain hardware errors
and can be programmed to report these errors via the RavenMPIC
interrupts or Machine Check Interrupt. Note that the TEA* signal is
not used at all by the MVME2300 series. The following table
summarizes how the hardware errors are handled by the
MVME2300 series:
Table 5-5. Error Notification and Handling

5
Cause

Action

Single-bit ECC

Store: Write corrected data to memory
Load: Present corrected data to the MPC master
Generate interrupt via RavenMPIC if so enabled

Double-bit ECC

Store: Terminate the bus cycle normally without writing to DRAM
Load: Present un-corrected data to the MPC master
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled

MPC Bus Time Out

Store: Discard write data and terminate bus cycle normally
Load: Present undeÞned data to the MPC master
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled

PCI Target Abort

Store: Discard write data and terminate bus cycle normally
Load: Return all 1Õs and terminate bus cycle normally
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled

PCI Master Abort

PERR# Detected

Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled

SERR# Detected

Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled

5-10

Endian Issues

Endian Issues
The MVME2300 series supports both little endian software and bigendian software. Because the PowerPC processor is inherently big
endian, PCI is inherently little-endian, and the VMEbus is big
endian, things do get rather confusing. The following figures shows
how the MVME2300 series handles the endian issue in big-endian
and little-endian modes:

5-11

Programming Details

Big-Endian PROGRAM
Falcons

5
DRAM

60X System Bus

Raven
N-way Byte Swap

Big Endian
Little Endian

PCI Local Bus

Universe
Little Endian
N-way Byte Swap
Big Endian

VMEbus
1898 9609

Figure 5-3. Big-Endian Mode

5-12

Endian Issues

Little-Endian PROGRAM

Little Endian
Big Endian

EA Modification (XOR)

Falcons

DRAM

60X System Bus

Raven
Big Endian
EA Modification
Little Endian

PCI Local Bus

Universe
Little Endian
N-way Byte Swap
Big Endian

VMEbus
1899 9609

Figure 5-4. Little-Endian Mode

5-13

Programming Details

Processor/Memory Domain
The MPC604 processor can operate in both big-endian and littleendian mode. However, it always treats the external
processor/memory bus as big-endian by performing address
rearrangement and reordering when running in little-endian mode.
The MPC registers inside Raven, the registers inside the Falcon
chipset, the DRAM, the ROM/FLASH and the system registers
always appear as big-endian.

Raven’s Involvement
Since PCI is little-endian, the Raven performs byte swapping in
both directions (from PCI to memory and from the processor to
PCI) to maintain address invariance when it is programmed to
operate in big-endian mode with the processor and the memory
sub-system.
In little-endian mode, it reverse-rearranges the address for PCIbound accesses and rearranges the address for memory-bound
accesses (from PCI). In this case, no byte swapping is done.

PCI Domain
The PCI bus is inherently little-endian and all devices connected
directly to PCI will operate in little-endian mode, regardless of the
mode of operation in the processorÕs domain.
PCI-SCSI
The MVME2300 series does not implement SCSI.
PCI-Ethernet
Ethernet is byte stream oriented with the byte having the lowest
address in memory being the first one to be transferred regardless
of the endian mode. Since address invariance is maintained by the
Raven in both little-endian and big-endian mode, there should be

5-14

Endian Issues

no endian issues for the Ethernet data. Big-endian software must
still however be aware of the byte-swapping effect when accessing
the registers of the PCI-Ethernet device.
PCI-Graphics
The effects of byte swapping on big-endian software must be
considered by big-endian software.
Note

There are no graphics on the MVME2300 series boards.

Universe’s Involvement
Since PCI is little-endian and the VMEbus is big-endian, the
Universe performs byte swapping in both directions (from PCI to
VMEbus and from VMEbus to PCI) to maintain address invariance,
regardless of the mode of operation in the processorÕs domain.

VMEbus Domain
The VMEbus is inherently big-endian and all devices connected
directly to VMEbus are expected to operate in big-endian mode,
regardless of the mode of operation in the processorÕs domain.
In big-endian mode, byte-swapping is performed by the Universe
and then by the Raven. The result has the desirable effect by being
transparent to the big-endian software.
In little-endian mode, however, software must be aware of the byteswapping effect from the Universe and the address reverserearranging effect of the Raven.

5-15

Programming Details

ROM/Flash Initialization
There are two methods used to inject code into the Flash in Bank A:
(1) In-circuit programming and (2) Loading it from the ROM/Flash
Bank B. For the second method, the hardware must direct the
Falcon chipset to map the FFF00000-FFFFFFFF address range to
Bank B following a hard reset. Bank A then can be programmed by
code from Bank B.
Software can determine the mapping of the FFF00000-FFFFFFFF
address range by examining the rom_b_rv bit in the FalconÕs Rom
B Base/Size Register.

Table 5-6. ROM/FLASH Bank Default
rom_b_rv

5-16

Default Mapping for FFF00000-FFFFFFFF

ROM/FLASH Bank A

ROM/FLASH Bank B

AOrdering Related

Documentation

Motorola Computer Group Documents
The publications listed below are on related products, and some
may be referenced in this document. If not shipped with this
product, manuals may be purchased by contacting your local
Motorola sales office.
Table A-1. Motorola Computer Group Documents
Document Title

Publication
Number

MVME2300-Series VME Processor Module
Installation and Use

V2300A/IH

MVME2300-Series VME Processor Module
ProgrammerÕs Reference Guide (this manual)

V2300A/PG

PPCBug Firmware Package UserÕs Manual (Parts 1 and 2)

PPCBUGA1/UM
PPCBUGA2/UM

PPCBug Diagnostics Manual

PPCDIAA/UM

PMCspan PMC Adapter Carrier Module Installation and Use

PMCSPANA/IH

Note

Although not shown in the above list, each Motorola
Computer Group manual publication number is
suffixed with characters that represent the revision
level of the document, such as Ò/xx2Ó (the second
revision of a manual); a supplement bears the same
number as the manual but has a suffix such as
Ò/xx2A1Ó (the first supplement to the second revision
of the manual).

A-1

Ordering Related Documentation

Manufacturers’ Documents
For additional information, refer to the following table for
manufacturersÕ data sheets or userÕs manuals. As an additional
help, a source for the listed document is also provided. Please note
that in many cases, the information is preliminary and the revision
levels of the documents are subject to change without notice.

Table A-2. Manufacturers’ Documents
Document Title and Source

Publication
Number

PowerPC 603TM RISC Microprocessor Technical Summary
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150
E-mail: ldcformotorola@hibbertco.com

MPC603/D

PowerPC 603TM RISC Microprocessor UserÕs Manual
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150
E-mail: ldcformotorola@hibbertco.com
OR
IBM Microelectronics
Mail Stop A25/862-1
PowerPC Marketing
1000 River Street
Essex Junction, Vermont 05452-4299
Telephone: 1-800-PowerPC
Telephone: 1-800-769-3772
FAX: 1-800-POWERfax
FAX: 1-800-769-3732

MPC603UM/AD

A-2

MPR603UMU-01

ManufacturersÕ Documents

Table A-2. Manufacturers’ Documents (Continued)
Document Title and Source

Publication
Number

PowerPCTM Microprocessor Family: The Programming Environments
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150
E-mail: ldcformotorola@hibbertco.com
OR
IBM Microelectronics
Mail Stop A25/862-1
PowerPC Marketing
1000 River Street
Essex Junction, Vermont 05452-4299
Telephone: 1-800-PowerPC
Telephone: 1-800-769-3772
FAX: 1-800-POWERfax
FAX: 1-800-769-3732

MPCFPE/AD

PC16550 UART
National Semiconductor Corporation
Customer Support Center (or nearest Sales OfÞce)
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, California 95052-8090
Telephone: 1-800-272-9959

PC16550DV

82378 System I/O (SIO) PCI-to-ISA Bridge Controller
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, Illinois 60056-7641
Telephone: 1-800-548-4725

290473-003

DECchip 21140 PCI Fast Ethernet LAN Controller
Hardware Reference Manual
Digital Equipment Corporation
Maynard, Massachusetts
DECchip Information Line
Telephone (United States and Canada): 1-800-332-2717
TTY (United States only): 1-800-332-2515
Telephone (outside North America): +1-508-568-6868

EC-QC0CA-TE

MPRPPCFPE-01

A-3

Ordering Related Documentation

Table A-2. Manufacturers’ Documents (Continued)
Document Title and Source

Publication
Number

W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB)
Winbond Electronics Corporation
Winbond Systems Laboratory
2730 Orchard Parkway
San Jose, CA 95134
Telephone: (408) 943-6666
FAX:(408) 943-6668

W83C553

M48T59 CMOS 8K x 8 TIMEKEEPERTM SRAM Data Sheet
SGS-Thomson Microelectronics Group
Marketing Headquarters (or nearest Sales OfÞce)
1000 East Bell Road
Phoenix, Arizona 85022
Telephone: (602) 867-6100

M48T59

Universe User Manual
Tundra Semiconductor Corporation
603 March Road
Kanata, ON K2K 2M5, Canada
Telephone: 1-800-267-7231
OR
695 High Glen Drive
San Jose, California 95133, USA
Telephone: (408) 258-3600
FAX: (408) 258-3659

Universe
(Part Number
9000000.MD303.01

A-4

Related Specifications

Related Specifications
For additional information, refer to the following table for related
specifications. As an additional help, a source for the listed
document is also provided. Please note that in many cases, the
information is preliminary and the revision levels of the documents
are subject to change without notice.
Table A-3. Related Specifications
Document Title and Source
VME64 SpeciÞcation
VITA (VMEbus International Trade Association)
7825 E. Gelding Drive, Suite 104
Scottsdale, Arizona 85260-3415
Telephone: (602) 951-8866
FAX: (602) 951-0720

Publication
Number
ANSI/VITA 1-1994

NOTE: An earlier version of this speciÞcation is available as:
Versatile Backplane Bus: VMEbus
Institute of Electrical and Electronics Engineers, Inc.
Publication and Sales Department
345 East 47th Street
New York, New York 10017-21633
Telephone: 1-800-678-4333
OR
Microprocessor system bus for 1 to 4 byte data
Bureau Central de la Commission Electrotechnique Internationale
3, rue de VarembŽ
Geneva, Switzerland
IEEE - Common Mezzanine Card SpeciÞcation (CMC)
Institute of Electrical and Electronics Engineers, Inc.
Publication and Sales Department
345 East 47th Street
New York, New York 10017-21633
Telephone: 1-800-678-4333

ANSI/IEEE
Standard 1014-1987

IEC 821 BUS

P1386 Draft 2.0

A-5

Ordering Related Documentation

Table A-3. Related Specifications (Continued)
Document Title and Source

Publication
Number

IEEE - PCI Mezzanine Card SpeciÞcation (PMC)
Institute of Electrical and Electronics Engineers, Inc.
Publication and Sales Department
345 East 47th Street
New York, New York 10017-21633
Telephone: 1-800-678-4333

P1386.1 Draft 2.0

Bidirectional Parallel Port Interface SpeciÞcation
Institute of Electrical and Electronics Engineers, Inc.
Publication and Sales Department
345 East 47th Street
New York, New York 10017-21633
Telephone: 1-800-678-4333

IEEE Standard 1284

Peripheral Component Interconnect (PCI) Local Bus SpeciÞcation,
Revision 2.0
PCI Special Interest Group
P.O. Box 14070
Portland, Oregon 97214-4070
Marketing/Help Line
Telephone: (503) 696-6111
Document/SpeciÞcation Ordering
Telephone: 1-800-433-5177or (503) 797-4207
FAX: (503) 234-6762

PCI Local Bus
SpeciÞcation

PowerPC Reference Platform (PRP) SpeciÞcation,
Third Edition, Version 1.0, Volumes I and II
International Business Machines Corporation
Power Personal Systems Architecture
11400 Burnet Rd.
Austin, TX 78758-3493
Document/SpeciÞcation Ordering
Telephone: 1-800-PowerPC
Telephone: 1-800-769-3772
Telephone: 708-296-9332

MPR-PPC-RPU-02

A-6

Related Specifications

Table A-3. Related Specifications (Continued)
Document Title and Source

Publication
Number

PowerPC Microprocessor Common Hardware Reference Platform
A System Architecture (CHRP), Version 1.0
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150
E-mail: ldcformotorola@hibbertco.com
OR
AFDA, Apple Computer, Inc.
P. O. Box 319
Buffalo, NY 14207
Telephone: 1-800-282-2732
FAX: (716) 871-6511
OR
IBM 1580 Route 52, Bldg. 504
Hopewell Junction, NY 12533-7531
Telephone: 1-800-PowerPC
OR
Morgan Kaufmann PUblishers, Inc.
340 Pine street, Sixth Floor
San Francisco, CA 94104-3205, USA
Telephone: (413) 392-2665
FAX: (415) 982-2665I
Interface Between Data Terminal Equipment and Data Circuit-Terminating
Equipment Employing Serial Binary Data Interchange (EIA-232-D)
Electronic Industries Association
Engineering Department
2001 Eye Street, N.W.
Washington, D.C. 20006

ANSI/EIA-232-D
Standard

A-7

Ordering Related Documentation

A-8

Glossary
Abbreviations, Acronyms, and Terms to Know
This glossary defines some of the abbreviations, acronyms, and key terms
used in this document.
10Base-5

An Ethernet implementation in which the physical medium
is a doubly shielded, 50-ohm coaxial cable capable of
carrying data at 10 Mbps for a length of 500 meters (also
referred to as thicknet). Also known as thick Ethernet.

10Base-2

An Ethernet implementation in which the physical medium
is a single-shielded, 50-ohm RG58A/U coaxial cable capable
of carrying data at 10 Mbps for a length of 185 meters (also
referred to as AUI or thinnet). Also known as thin Ethernet.

10Base-T

An Ethernet implementation in which the physical medium
is an unshielded twisted pair (UTP) of wires capable of
carrying data at 10 Mbps for a maximum distance of 185
meters. Also known as twisted-pair Ethernet.

100Base-TX

An Ethernet implementation in which the physical medium
is an unshielded twisted pair (UTP) of wires capable of
carrying data at 100 Mbps for a maximum distance of 100
meters. Also known as fast Ethernet.

ACIA

Asynchronous Communications Interface Adapter

AIX

Advanced Interactive eXecutive (IBM version of UNIX)

architecture

The main overall design in which each individual hardware
component of the computer system is interrelated. The most
common uses of this term are 8-bit, 16-bit, or 32-bit
architectural design systems.

ASCII

American Standard Code for Information Interchange. This
is a 7-bit code used to encode alphanumeric information. In
the IBM-compatible world, this is expanded to 8-bits to
encode a total of 256 alphanumeric and control characters.

GL-1

Glossary

G
L
O
S
S
A
R
Y

ASIC

Application-Specific Integrated Circuit

AUI

Attachment Unit Interface

BBRAM

Battery Backed-up Random Access Memory

bi-endian

Having big-endian and little-endian byte ordering
capability.

big-endian

A byte-ordering method in memory where the address
n of a word corresponds to the most significant byte. In
an addressed memory word, the bytes are ordered (left
to right) 0, 1, 2, 3, with 0 being the most significant byte.

BIOS

Basic Input/Output System. This is the built-in
program that controls the basic functions of
communications between the processor and the I/O
(peripherals) devices. Also referred to as ROM BIOS.

BitBLT

Bit Boundary BLock Transfer. A type of graphics
drawing routine that moves a rectangle of data from one
area of display memory to another. The data specifically
need not have any particular alignment.

BLT

BLock Transfer

board

The term more commonly used to refer to a PCB
(printed circuit board). Basically, a flat board made of
nonconducting material, such as plastic or fiberglass, on
which chips and other electronic components are
mounted. Also referred to as a circuit board or card.

bpi

bits per inch

bps

bits per second

bus

The pathway used to communicate between the CPU,
memory, and various input/output devices, including
floppy and hard disk drives. Available in various
widths (8-, 16-, and 32-bit), with accompanying
increases in speed.

cache

A high-speed memory that resides logically between a
central processing unit (CPU) and the main memory.
This temporary memory holds the data and/or

GL-2

Glossary

instructions that the CPU is most likely to use over and over
again and avoids accessing the slower hard or floppy disk
drive.
CAS

Column Address Strobe. The clock signal used in dynamic
RAMs to control the input of column addresses.

Compact Disc. A hard, round, flat portable storage unit that
stores information digitally.

CD-ROM

Compact Disk Read-Only Memory

CFM

Cubic Feet per Minute

CHRP

See Common Hardware Reference Platform (CHRP).

CHRP-compliant

See Common Hardware Reference Platform (CHRP).

CHRP Spec

See Common Hardware Reference Platform (CHRP).

CISC

Complex-Instruction-Set Computer. A computer whose
processor is designed to sequentially run variable-length
instructions, many of which require several clock cycles,
that perform complex tasks and thereby simplify
programming.

CODEC

COder/DECoder

Color Difference (CD)

The signals of (R-Y) and (B-Y) without the luminance (-Y)
signal. The Green signals (G-Y) can be extracted by these
two signals.

Common Hardware Reference Platform (CHRP)

A specification published by the Apple, IBM, and Motorola
which defines the devices, interfaces, and data formats that
make up a CHRP-compliant system using a PowerPC
processor.
Composite Video Signal (CVS/CVBS)

Signal that carries video picture information for color,
brightness and synchronizing signals for both horizontal
and vertical scans. Sometimes referred to as ÒBaseband
VideoÓ.
cpi

characters per inch

cpl

characters per line

GL-3

G
L
O
S
S
A
R
Y

Glossary

G
L
O
S
S
A
R
Y

CPU

Central Processing Unit. The master computer unit in a
system.

DCE

Data Circuit-terminating Equipment.

DLL

Dynamic Link Library. A set of functions that are linked to
the referencing program at the time it is loaded into
memory.

DMA

Direct Memory Access. A method by which a device may
read or write to memory directly without processor
intervention. DMA is typically used by block I/O devices.

DOS

Disk Operating System

dpi

dots per inch

DRAM

Dynamic Random Access Memory. A memory technology
that is characterized by extreme high density, low power,
and low cost. It must be more or less continuously refreshed
to avoid loss of data.

DTE

Data Terminal Equipment.

ECC

Error Correction Code

ECP

Extended Capability Port

EEPROM

Electrically Erasable Programmable Read-Only Memory. A
memory storage device that can be written repeatedly with
no special erasure fixture. EEPROMs do not lose their
contents when they are powered down.

EISA (bus)

Extended Industry Standard Architecture (bus) (IBM). An
architectural system using a 32-bit bus that allows data to be
transferred between peripherals in 32-bit chunks instead of
16-bit or 8-bit that most systems use. With the transfer of
larger bits of information, the machine is able to perform
much faster than the standard ISA bus system.

EPP

Enhanced Parallel Port

EPROM

Erasable Programmable Read-Only Memory. A memory
storage device that can be written once (per erasure cycle)
and read many times.

ESCC

Enhanced Serial Communication Controller

ESD

Electro-Static Discharge/Damage

GL-4

Glossary

Ethernet

A local area network standard that uses radio frequency
signals carried by coaxial cables.

Falcon

The DRAM controller chip developed by Motorola for the
MVME2600 and MVME3600 series of boards. It is intended
to be used in sets of two to provide the necessary interface
between the Power PC60x bus and the 144-bit ECC DRAM
(system memory array) and/or ROM/Flash.

fast Ethernet

See 100Base-TX.

FDC

Floppy Disk Controller

FDDI

Fiber Distributed Data Interface. A network based on the
use of optical-fiber cable to transmit data in non-return-tozero, invert-on-1s (NRZI) format at speeds up to 100 Mbps.

FIFO

First-In, First-Out. A memory that can temporarily hold
data so that the sending device can send data faster than the
receiving device can accept it. The sending and receiving
devices typically operate asynchronously.

firmware

The program or specific software instructions that have
been more or less permanently burned into an electronic
component, such as a ROM (read-only memory) or an
EPROM (erasable programmable read-only memory).

frame

One complete television picture frame consists of 525
horizontal lines with the NTSC system. One frame consists
of two Fields.

graphics controller

On EGA and VGA, a section of circuitry that can provide
hardware assist for graphics drawing algorithms by
performing logical functions on data written to display
memory.

HAL

Hardware Abstraction Layer. The lower level hardware
interface module of the Windows NT operating system. It
contains platform specific functionality.

hardware

A computing system is normally spoken of as having two
major components: hardware and software. Hardware is
the term used to describe any of the physical embodiments

GL-5

G
L
O
S
S
A
R
Y

Glossary

of a computer system, with emphasis on the electronic
circuits (the computer) and electromechanical devices
(peripherals) that make up the system.

G
L
O
S
S
A
R
Y

HCT

Hardware Conformance Test. A test used to ensure that
both hardware and software conform to the Windows NT
interface.

I/O

Input/Output

IBC

PCI/ISA Bridge Controller

IDC

Insulation Displacement Connector

IDE

Intelligent Device Expansion

IEEE

Institute of Electrical and Electronics Engineers

interlaced

A graphics system in which the even scanlines are refreshed
in one vertical cycle (field), and the odd scanlines are
refreshed in another vertical cycle. The advantage is that the
video bandwidth is roughly half that required for a noninterlaced system of the same resolution. This results in less
costly hardware. It also may make it possible to display a
resolution that would otherwise be impossible on given
hardware. The disadvantage of an interlaced system is
flicker, especially when displaying objects that are only a
few scanlines high.

IQ Signals

Similar to the color difference signals (R-Y), (B-Y) but using
different vector axis for encoding or decoding. Used by
some USA TV and IC manufacturers for color decoding.

ISA (bus)

Industry Standard Architecture (bus). The de facto
standard system bus for IBM-compatible computers until
the introduction of VESA and PCI. Used in the reference
platform specification. (IBM)

ISASIO

ISA Super Input/Output device

ISDN

Integrated Services Digital Network. A standard for
digitally transmitting video, audio, and electronic data over
public phone networks.

LAN

Local Area Network

LED

Light-Emitting Diode

GL-6

Glossary

LFM

Linear Feet per Minute

little-endian

A byte-ordering method in memory where the address n of
a word corresponds to the least significant byte. In an
addressed memory word, the bytes are ordered (left to
right) 3, 2, 1, 0, with 3 being the most significant byte.

MBLT

Multiplexed BLock Transfer

MCA (bus)

Micro Channel Architecture

MCG

Motorola Computer Group

MFM

Modified Frequency Modulation

MIDI

Musical Instrument Digital Interface. The standard format
for recording, storing, and playing digital music.

MPC

Multimedia Personal Computer

MPC105

The PowerPC-to-PCI bus bridge chip developed by
Motorola for the Ultra 603/Ultra 604 system board. It
provides the necessary interface between the MPC603/
MPC604 processor and the Boot ROM (secondary cache),
the DRAM (system memory array), and the PCI bus.

MPC601

MotorolaÕs component designation for the PowerPC 601
microprocessor.

MPC603

MotorolaÕs component designation for the PowerPC 603
microprocessor.

MPC604

MotorolaÕs component designation for the PowerPC 604
microprocessor.

MPIC

Multi-Processor Interrupt Controller

MPU

MicroProcessing Unit

MTBF

Mean Time Between Failures. A statistical term relating to
reliability as expressed in power on hours (poh). It was
originally developed for the military and can be calculated
several different ways, yielding substantially different
results. The specification is based on a large number of
samplings in one place, running continuously, and the rate
at which failure occurs. MTBF is not representative of how

GL-7

G
L
O
S
S
A
R
Y

Glossary

long a device, or any individual device is likely to last, nor
is it a warranty, but rather, of the relative reliability of a
family of products.

G
L
O
S
S
A
R
Y

multisession

The ability to record additional information, such as
digitized photographs, on a CD-ROM after a prior
recording session has ended.

non-interlaced

A video system in which every pixel is refreshed during
every vertical scan. A non-interlaced system is normally
more expensive than an interlaced system of the same
resolution, and is usually said to have a more pleasing
appearance.

nonvolatile memory

A memory in which the data content is maintained whether
the power supply is connected or not.

NTSC

National Television Standards Committee (USA)

NVRAM

Non-Volatile Random Access Memory

OEM

Original Equipment Manufacturer

OMPAC

Over - Molded Pad Array Carrier

Operating System. The software that manages the
computer resources, accesses files, and dispatches
programs.

OTP

One-Time Programmable

palette

The range of colors available on the screen, not necessarily
simultaneously. For VGA, this is either 16 or 256
simultaneous colors out of 262,144.

parallel port

A connector that can exchange data with an I/O device
eight bits at a time. This port is more commonly used for the
connection of a printer to a system.

PCI (local bus)

Peripheral Component Interconnect (local bus) (Intel). A
high-performance, 32-bit internal interconnect bus used for
data transfer to peripheral controller components, such as
those for audio, video, and graphics.

GL-8

Glossary

PCMCIA (bus)

PCR
PHB
PDS
physical address
PIB

Personal Computer Memory Card International
Association (bus). A standard external interconnect bus
which allows peripherals adhering to the standard to be
plugged in and used without further system modification.
PCI Configuration Register
PCI Host Bridge
Processor Direct Slot
A binary address that refers to the actual location of
information stored in secondary storage.
PCI-to-ISA Bridge

pixel

An acronym for picture element, and is also called a pel. A
pixel is the smallest addressable graphic on a display screen.
In RGB systems, the color of a pixel is defined by some Red
intensity, some Green intensity, and some Blue intensity.

PLL

Phase-Locked Loop

PMC

PCI Mezzanine Card

POWER

Performance Optimized With Enhanced RISC architecture
(IBM)

PowerPC™

The trademark used to describe the Performance Optimized
With Enhanced RISC microprocessor architecture for
Personal Computers developed by the IBM Corporation.
PowerPC is superscalar, which means it can handle more
than one instruction per clock cycle. Instructions can be sent
simultaneously to three types of independent execution
units (branch units, fixed-point units, and floating-point
units), where they can execute concurrently, but finish out
of order. PowerPC is used by Motorola, Inc. under license
from IBM.

PowerPC 601™

The first implementation of the PowerPC family of
microprocessors. This CPU incorporates a memory
management unit with a 256-entry buffer and a 32KB
unified (instruction and data) cache. It provides a 64-bit
data bus and a separate 32-bit address bus. PowerPC 601 is
used by Motorola, Inc. under license from IBM.

GL-9

G
L
O
S
S
A
R
Y

Glossary

PowerPC 603™

The second implementation of the PowerPC family of
microprocessors. This CPU incorporates a memory
management unit with a 64-entry buffer and an 8KB
(instruction and data) cache. It provides a selectable 32-bit
or 64-bit data bus and a separate 32-bit address bus.
PowerPC 603 is used by Motorola, Inc. under license from
IBM.

PowerPC 604™

The third implementation of the PowerPC family of
microprocessors. PowerPC 604 is used by Motorola, Inc.
under license from IBM.

PowerPC Reference Platform (PRP)

A specification published by the IBM Power Personal
Systems Division which defines the devices, interfaces, and
data formats that make up a PRP-compliant system using a
PowerPC processor.
PowerStack™ RISC PC (System Board)

A PowerPC-based computer board platform developed by
the Motorola Computer Group. It supports MicrosoftÕs
Windows NT and IBMÕs AIX operating systems.

G
L
O
S
S
A
R
Y

PRP

See PowerPC Reference Platform (PRP).

PRP-compliant

See PowerPC Reference Platform (PRP).

PRP Spec

See PowerPC Reference Platform (PRP).

PROM

Programmable Read-Only Memory

PS/2

Personal System/2 (IBM)

QFP

Quad Flat Package

RAM

Random-Access Memory. The temporary memory that a
computer uses to hold the instructions and data currently
being worked with. All data in RAM is lost when the
computer is turned off.

RAS

Row Address Strobe. A clock signal used in dynamic RAMs
to control the input of the row addresses.

GL-10

Glossary

Raven

The PowerPC-to-PCI local bus bridge chip developed by
Motorola for the MVME2600 and MVME3600 series of
boards. It provides the necessary interface between the
PowerPC 60x bus and the PCI bus, and acts as interrupt
controller.

Reduced-Instruction-Set Computer (RISC)

A computer in which the processorÕs instruction set is
limited to constant-length instructions that can usually be
executed in a single clock cycle.
RFI

Radio Frequency Interference

RGB

The three separate color signals: Red, Green, and Blue.
Used with color displays, an interface that uses these three
color signals as opposed to an interface used with a
monochrome display that requires only a single signal. Both
digital and analog RGB interfaces exist.

RISC

See Reduced Instruction Set Computer (RISC).

ROM

Read-Only Memory

RTC

Real-Time Clock

SBC

Single Board Computer

SCSI

Small Computer Systems Interface. An industry-standard
high-speed interface primarily used for secondary storage.
SCSI-1 provides up to 5 Mbps data transfer.

SCSI-2 (Fast/Wide)

An improvement over plain SCSI; and includes command
queuing. Fast SCSI provides 10 Mbps data transfer on an 8bit bus. Wide SCSI provides up to 40 Mbps data transfer on
a 16- or 32-bit bus.

serial port

A connector that can exchange data with an I/O device one
bit at a time. It may operate synchronously or
asynchronously, and may include start bits, stop bits, and/
or parity.

SIM

Serial Interface Module

SIMM

Single Inline Memory Module. A small circuit board with
RAM chips (normally surface mounted) on it designed to fit
into a standard slot.

GL-11

G
L
O
S
S
A
R
Y

Glossary

G
L
O
S
S
A
R
Y

SIO

Super I/O controller

SMP

Symmetric MultiProcessing. A computer architecture in
which tasks are distributed among two or more local
processors.

SMT

Surface Mount Technology. A method of mounting devices
(such as integrated circuits, resistors, capacitors, and others)
on a printed circuit board, characterized by not requiring
mounting holes. Rather, the devices are soldered to pads on
the printed circuit board. Surface-mount devices are
typically smaller than the equivalent through-hole devices.

software

A computing system is normally spoken of as having two
major components: hardware and software. Software is the
term used to describe any single program or group of
programs, languages, operating procedures, and
documentation of a computer system. Software is the real
interface between the user and the computer.

SRAM

Static Random Access Memory

SSBLT

Source Synchronous BLock Transfer

standard(s)

A set of detailed technical guidelines used as a means of
establishing uniformity in an area of hardware or software
development.

SVGA

Super Video Graphics Array (IBM). An improved VGA
monitor standard that provides at least 256 simultaneous
colors and a screen resolution of 800 x 600 pixels.

Teletext

One way broadcast of digital information. The digital
information is injected in the broadcast TV signal, VBI, or
full field, The transmission medium could be satellite,
microwave, cable, etc. The display medium is a regular TV
receiver.

thick Ethernet

See 10Base-5.

thin Ethernet

See 10Base-2.

twisted-pair Ethernet

See 10Base-T.

UART

Universal Asynchronous Receiver/Transmitter

GL-12

Glossary

Universe

ASIC developed by Tundra in consultation with Motorola,
that provides the complete interface between the PCI bus
and the 64-bit VMEbus.

UltraViolet

UVGA

Ultra Video Graphics Array. An improved VGA monitor
standard that provides at least 256 simultaneous colors and
a screen resolution of 1024 x 768 pixels.

Vertical Blanking Interval (VBI)

The time it takes the beam to fly back to the top of the screen
in order to retrace the opposite field (odd or even). VBI is in
the order of 20 TV lines. Teletext information is transmitted
over 4 of these lines (lines 14-17).
VESA (bus)

Video Electronics Standards Association (or VL bus). An
internal interconnect standard for transferring video
information to a computer display system.

VGA

Video Graphics Array (IBM). The third and most common
monitor standard used today. It provides up to 256
simultaneous colors and a screen resolution of 640 x 480
pixels.

virtual address

A binary address issued by a CPU that indirectly refers to
the location of information in primary memory, such as
main memory. When data is copied from disk to main
memory, the physical address is changed to the virtual
address.

VL bus

See VESA Local bus (VL bus).

VMEchip2

MCG second generation VMEbus interface ASIC (Motorola)

VME2PCI

MCG ASIC that interfaces between the PCI bus and the
VMEchip2 device.

volatile memory

A memory in which the data content is lost when the power
supply is disconnected.

VRAM

Video (Dynamic) Random Access Memory. Memory chips
with two ports, one used for random accesses and the other
capable of serial accesses. Once the serial port has been
initialized (with a transfer cycle), it can operate
independently of the random port. This frees the random

GL-13

G
L
O
S
S
A
R
Y

Glossary

port for CPU accesses. The result of adding the serial port is
a significantly reduced amount of interference from screen
refresh. VRAMs cost more per bit than DRAMs.
Windows NT™

The trademark representing Windows New Technology, a
computer operating system developed by the Microsoft
Corporation.

XGA

EXtended Graphics Array. An improved IBM VGA monitor
standard that provides at least 256 simultaneous colors and
a screen resolution of 1024 x 768 pixels.

Y Signal

Luminance. This determines the brightness of each spot
(pixel) on a CRT screen either color or B/W systems, but not
the color.

G
L
O
S
S
A
R
Y

GL-14

Index

Numerics

16550 access registers 1-34
16550 UART 1-34
32-Bit Counter 3-53
8259 compatibility 2-67
8259 interrupts 5-4
8259 mode 2-96

Base Module Feature Register 1-38
Base Module Status Register (BMSR) 1-39
big to little endian data swap 2-26
big-endian 1-2
big-endian mode 5-12
binary number 1-1
bit descriptions 3-32
bit ordering convention 3-1
block diagram 2-3
block diagram description 2-70
block diagrams 3-2
Block_A/B/C/D Configurations 3-36
blocks A and/or B present, blocks C and
D not present 3-20
blocks A and/or B present, blocks C
and/or D present 3-21
bus interface (60x) 3-12
byte ordering 1-2
byte, definition 1-2

A
A0-A31 3-5
abbreviations, acronyms, and terms to
know GL-1
access timing (DRAM) 3-8, 3-9, 3-10
access timing (ROM) 3-11
address modification for little endian
transfers 2-27
address pipelining 3-6
address transfers 3-12
address/data stepping 2-21
addressing 2-15, 2-19
Application-Specific Integrated Circuit
(ASIC) 1-1
arbitration 2-20
arbitration latency 2-20
architectural diagram for the Universe
4-3
architectural notes 2-97
architectural overview 2-4, 4-2
architecture 2-65
ARTRY_ 3-12
assertion, definition 1-2
asterisk (*) 1-2

C
cache coherency 3-12
cache coherency restrictions 3-13
cache support 2-17, 2-21
CAS* 3-20
CHRP memory map example 1-10
CLK FREQUENCY 3-37
CLK Frequency Register 3-37
clock frequency 3-37
Column Address 3-47
combining, merging, and collapsing 2-19
command types 2-15, 2-18

IN-15

Index

CONFIG_ADDRESS Register 2-60
CONFIG_DATA Register 2-63
configuration registers
2-11
control bit descriptions 3-32
control bit, definition 1-2
conventions, manual 1-1
CPU Configuration Register 1-37
CPU Control Register 1-33
CSR accesses 3-23
CSR architecture 3-24
CSR base address 3-24
CSR reads and writes 3-24
CSRÕs readability 2-66
current task priority level 2-96
cycle types 3-13

I
N
D
E
X

data path diagram 3-64
data path for reads from the Falcon internal CSRs 3-24
data path for writes to the Falcon internal
CSRs 3-25
data path mapping 3-65
data paths 3-63
data transfers 3-12
decimal number 1-1
default PCI memory map 1-14
default processor memory map 1-9
defaults 3-22
derc 3-40
device selection 2-16
Disable Error Correction control bit 3-40
DMA controller 4-7
documentation, related A-1
double word, definition 1-2
DRAM addressing 3-60
DRAM arbitration 3-22
DRAM Attributes Register 3-35
DRAM Base Register 3-37
DRAM connection diagram 3-5
DRAM enable bits 3-35

IN-16

DRAM size control bits 3-36
DRAM speed control bits 3-34
DRAM speeds 3-7
DRAM tester 3-15
DRAM Tester Control Registers 3-53
DRAM tester control registers 3-53
dynamically changing I/O interrupt configuration 2-95

E
ECC 3-13
ECC codes 3-61
ECC Control Register 3-38
elog 3-43
embt 3-43
emulated Z8536 access registers 1-46
emulated Z8536 CIO registers and port
pins 1-46
emulated Z8536 registers 1-46
endian conversion 2-25
endian issues 5-11
End-of-Interrupt Registers 2-92
EOI Register 2-96
Error Address Register 3-45
error correction 3-13
Error Correction Codes 3-61
error detection 3-13
error handling 2-28
Error Logger Register 3-42
error logging 3-15
error notification and handling 5-10
error reporting 3-14
ERROR_ADDRESS 3-45
ERROR_SYNDROME 3-44
esbt 3-43
escb 3-43
esen 3-43
example 1 4-16
example 2 4-17
example 3 4-19
examples 4-16
exceptions 5-8

exclusive access 2-16, 2-20
external interrupt service 2-93
External Register Set 3-56
external register set 3-23
external register set reads and writes 3-24
External Source Destination Registers
2-88
External Source Vector/Priority Registers 2-87

F
Falcon ECC Memory Controller chip set
3-1
Falcon internal data paths (simplified)
3-4
Falcon pair used with DRAM in a system
3-3
Falcon-controlled system registers 1-27
false, definition 1-3
fast back-to-back transactions 2-16, 2-20
fast refresh control bit 3-34
Feature Reporting Register 2-79
features 2-1, 3-1
Flash (see ROM/Flash) 3-16
four-beat reads/writes 3-6
functional description 1-7, 2-4, 3-6, 4-2

G
General Control Register 3-33
General Control-Status/Feature Registers 2-34
general information 4-1
General Purpose Registers 2-51
general-purpose
software-readable
header 1-35
general-purpose
software-readable
header (J17) 1-35
generating PCI configuration cycles 2-23
generating PCI cycles 2-21
generating PCI interrupt acknowledge
cycles 2-25

generating PCI memory and I/O cycles
2-21
generating PCI special cycles 2-25
Global Configuration Register 2-80
glossary GL-1

H
half-word, definition 1-2
headers
J17 1-35
hexadecimal character 1-1

I
I/O Base Register 2-56
In-Service Register (ISR) 2-72
Interprocessor Interrupt Dispatch Registers 2-90
interprocessor interrupts 2-95
interprocessor interrupts (IPI) 2-67
Interrupt Acknowledge Register 2-96
Interrupt Acknowledge Registers 2-92
interrupt delivery modes 2-69
Interrupt Enable control bits 3-41
interrupt handling 5-2
Interrupt Pending Register (IPR) 2-71
Interrupt Request Register (IRR) 2-72
interrupt router 2-72
interrupt selector (IS) 2-71
interrupt source priority 2-66
Interrupt Task Priority Registers 2-91
interrupter 4-6
interrupter and interrupt handler 4-6
introduction 2-1, 2-65, 3-1, 4-1, 5-1
IPI Vector/Priority Registers 2-82
ISA DMA channels 1-47, 5-7
ISA local resource bus 1-34

J
jumpers, software readable 1-35

L
L2 cache support 3-13

IN-17

I
N
D
E
X

Index

L2CLM_ 3-13
Large Scale Integration (LSI) 1-1
latency 2-16
little-endian mode 5-13
LM/SIG Control Register 1-41
LM/SIG Status Register 1-42
Location Monitor Lower Base Address
Register 1-44
Location Monitor Upper Base Address
Register 1-43

I
N
D
E
X

manual terminology 1-2
manufacturersÕ documents A-2
master initiated termination 2-20
mcken 3-41
Memory Base Register 2-57
Memory Configuration Register (MEMCR) 1-30
memory map for 4-byte reads to the CSR
3-28
memory map for 4-byte writes to the internal register set and test SRAM
3-28
memory map for byte reads to the CSRs
3-26
memory map for byte writes to the internal register set and test SRAM
3-27
memory maps 1-8
mien 3-41
MK48T59/559 access registers 1-36
module configuration and status registers 1-36
Motorola Computer Group documents
A-1
MPC address mapping 2-4
MPC arbiter 2-10
MPC Arbiter Control Register 2-37
MPC bus address space
2-11
MPC bus interface 2-4

IN-18

MPC bus timer 2-10
MPC Error Address Register 2-42
MPC Error Attribute Register - MERAT
2-43
MPC Error Enable Register 2-38
MPC Error Status Register 2-40
MPC master 2-8
MPC registers 2-31
MPC slave 2-6
MPC Slave Address (0,1 and 2) Registers
2-47
MPC Slave Address (3) Register 2-48
MPC Slave Offset/Attribute (0,1 and 2)
Registers 2-49
MPC Slave Offset/Attribute (3) Registers
2-50
MPC slave response command types 2-7
MPC to PCI address decoding 2-5
MPC to PCI address translation 2-6
MPC transfer types 2-9
MPC write posting 2-8
MPIC registers 2-74
MVME2300 series 1-1
MVME2300 series system block diagram
1-6
MVME230x features 1-3
MVME2600 series interrupt architecture
5-2

N
negation, definition 1-2
nesting of interrupt events 2-66
NVRAM/RTC & Watchdog Timer Registers 1-36

O
OE* 3-20
operation 2-95
overall DRAM connections 3-5
overview 1-3, 2-1, 3-1

P
parity 2-17, 2-21
parity checking 3-57
PCI 2-17
PCI address mapping 2-11
PCI arbitration 5-1
PCI arbitration assignments 5-1
PCI bus interface 4-5
PCI CHRP memory map 1-14
PCI Command/ Status Registers 2-53
PCI configuration access 1-13
PCI domain 5-14
PCI interface 2-10
PCI Interrupt Acknowledge Register
2-45
PCI master 2-17
PCI master command codes 2-19
PCI memory maps 1-14
PCI PREP memory map 1-18
PCI registers 2-51
PCI slave 2-14
PCI Slave Address (0,1,2 and 3) Registers
2-58
PCI Slave Attribute/ Offset (0,1,2 and 3)
Registers 2-59
PCI slave response command types 2-15
PCI spread I/O address translation 2-22
PCI to MPC address decoding 2-12
PCI to MPC address translation 2-13
PCI write posting 2-17
PCI-Ethernet 5-14
PCI-graphics 5-15
PCI-SCSI 5-14
performance 3-6
PIB interrupt handler block diagram 5-5
PIB PCI/ISA interrupt assignments 5-6
PowerPC 60x Address to DRAM Address Mappings 3-60
PowerPC 60x address to ROM/Flash address mapping with 2, 32-bit or
1, 64-bit 3-19

PowerPC 60x bus to DRAM access timing using 50ns hyper devices
3-10
PowerPC 60x bus to DRAM access timing using 60ns page devices 3-9
PowerPC 60x bus to ROM/Flash access
timing using 32/64-bit devices
3-11
PowerPC 60x bus to ROM/Flash access
timing using 8-bit devices 3-11
PowerPC 60x to ROM/Flash address
mapping when ROM/Flash is 16
bits wide (8 bits per Falcon) 3-18
PowerPC 60x to ROM/Flash address
mapping with 2, 8-bit devices
3-18
PowerPC bus to DRAM access timing 3-8
PowerPC data to DRAM data mapping
3-65
PowerPC to DRAM data correspondence
3-64
Power-Up Reset status bit 3-38
Power-Up Reset Status Registers 3-55
PR_STAT1 3-55
PR_STAT2 3-55
PREP memory map example 1-12
Prescaler Adjust Register 2-37
problem description 4-14
processor CHRP memory map 1-10
Processor Init Register 2-81
processor memory maps 1-8
processor PREP memory map 1-12
processor/memory domain 5-14
processorÕs current task priority 2-66
product overview - features 4-1
program visible registers 2-71
programming details 5-1
programming model 1-8, 3-24
programming notes 2-93
programming ROM/Flash 3-57

IN-19

I
N
D
E
X

Index

I
N
D
E
X

RAM A BASE 3-37
RAM B BASE 3-37
RAM C BASE 3-37
RAM D BASE 3-37
RAS* 3-20
Raven block diagram 2-3
Raven interrupt controller (RavenMPIC)
features 2-65
Raven interrupt controller implementation 2-65
Raven MPC register map 2-31
Raven MPC register values for CHRP
memory map 1-11
Raven MPC register values for PREP
memory map 1-13
Raven PCI configuration register map
2-52
Raven PCI Host Bridge & Multi-Processor Interrupt Controller chip 2-1
Raven PCI I/O register map 2-52
Raven PCI register values for CHRP
memory map 1-16
Raven PCI register values for PREP
memory map 1-19
Raven registers 2-27
RavenÕs involvement 5-14
Raven-detected errors 2-68
Raven-Detected Errors Destination Register 2-90
Raven-Detected Errors Vector/Priority
Register 2-89
RavenMPIC 5-3
RavenMPIC block diagram 2-70
RavenMPIC control registers
2-14
RavenMPIC interrupt assignments 5-3
RavenMPIC register map 2-75
RavenMPIC registers 2-74
Read/Write Checkbits control bit 3-38
Read/Write to ROM/Flash 3-50
readable jumpers 1-35

IN-20

Refresh Counter Test control bits 3-46
refresh/scrub 3-20
Refresh/Scrub Address Register 3-46
register bit descriptions 3-32
register summary 3-29, 3-30
registers 2-31
registers - Universe Control and Status
Registers (UCSR) 4-8
related documentation, ordering A-1
related specifications A-5
reset sources and devices affected 5-9
reset state 2-94
Revision ID 3-33
Revision ID Register 2-33
Revision ID/ Class Code Registers 2-55
Revision ID/General Control Register
3-33
ROM 5-16
ROM Block A Size Encodings 3-48
ROM Block B Size Encoding 3-52
ROM/Flash 3-16
ROM/Flash A Base Address control bits
3-47
ROM/Flash A Base/Size Register 3-47
ROM/Flash A size encoding 3-48
ROM/Flash A Width control bit 3-48
ROM/Flash B Base Address control bits
3-50
ROM/Flash B Base/Size Register 3-50
ROM/Flash B Width control bit 3-51
ROM/FLASH bank default 5-16
ROM/Flash initialization 5-16
ROM/Flash interface 3-16
ROM/Flash speed 3-11
rom_a_64 3-48
ROM_A_BASE 3-47
rom_a_en 3-49
rom_a_rv 3-49
rom_a_rv and rom_b_rv encoding 3-49
rom_a_siz 3-48
rom_a_we 3-49
rom_b_64 3-51

ROM_B_BASE 3-50
rom_b_en 3-52
rom_b_rv 3-52
rom_b_siz 3-52
rom_b_we 3-52
Row Address 3-46
rtest encodings 3-46
rtest0-rtest2 3-46
rwcb 3-38

S
SBE_COUNT 3-44
scb0,scb1 3-45
scien 3-38, 3-41
scof 3-44
scrub counter 3-45
Scrub Write Enable control bit 3-46
Scrub/Refresh Register 3-45
Semaphore Register 1 1-44
Semaphore Register 2 1-45
Seven-Segment Display Register 1-40
sien 3-41
Single Bit Error Counter 3-44
single word, definition 1-2
single-beat reads/writes 3-7
single-beat writes 3-7
single-bit error 3-14
single-bit errors ordered by syndrome
code 3-62
sizing addresses 3-59
sizing DRAM 3-58
small-endian 1-2
soft reset 5-9
software considerations 3-57
software readable jumpers 1-35
sources of reset 5-8
specifications
related A-5
spurious vector generation 2-67
Spurious Vector Register 2-83
SRAM base address 3-24
SRAM reads and writes 3-24

status bit descriptions 3-32
status bit, definition 1-2
swen 3-46
SWREN 3-21
syndrome codes ordered by bit in error
3-61
System Configuration Register (SYSCR)
1-28
System External Cache Control Register
(SXCCR) 1-32
system register summary 1-27

T
target initiated termination
2-16
Test SRAM 3-54
tester control registers 3-53
tester description 3-15
tien 3-41
Timer Basecount Registers 2-84
Timer Current Count Registers 2-84
Timer Destination Registers 2-86
Timer Frequency Register 2-83
Timer Vector/Priority Registers 2-85
timers 2-68
timing (DRAM access) 3-8, 3-9, 3-10
timing (ROM/Flash access) 3-11
transaction ordering 2-29
triple- (or greater) bit error 3-14
true, definition 1-2
trun 3-53
tsse 3-53

U
UCSR access mechanisms 4-8
Universe (VMEbus to PCI) chip 4-1
Universe as PCI master 4-6
Universe as PCI slave 4-5
Universe as VMEbus master 4-4
Universe as VMEbus slave 4-4
Universe chip problems after a PCI reset
4-14, 5-9

IN-21

I
N
D
E
X

Index

Universe PCI Register values for CHRP
memory map 1-16
Universe PCI register values for PREP
memory map 1-20
Universe PCI register values for VMEbus
slave map example 1-25
Universe register map 4-9
UniverseÕs involvement 5-15
upper/lower chip status bit 3-35

V
Vendor ID/ Device ID Registers 2-53
Vendor ID/Device ID Registers 2-33
Vendor Identification Register 2-81
Vendor/Device Register 3-33
VME Geographical Address Register
(VGAR) 1-45
VME registers 1-40, 1-41
VMEbus domain 5-15
VMEbus interface 4-4
VMEbus interrupt handling 4-7
VMEbus mapping 1-21
VMEbus master map 1-21
VMEbus master mapping 1-22
VMEbus slave map 1-23
VMEbus slave map example 1-26
VMEbus slave mapping 1-24

W
W83C553 PIB registers 1-34
WE* 3-20
when MPC devices are big-endian 2-25
when MPC devices are little endian 2-26
word, definition 1-2
writing to the control registers 3-57

I
N
D
E
X

Z
Z8536 CIO port pins 1-46
Z8536 CIO port pins assignment 1-46

IN-22

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Format                          : application/pdf
Creator                         : sikard
Title                           : Book.B
Create Date                     : 1998:04:13 15:04:45Z
Creator Tool                    : FrameMaker 5.1.1
Modify Date                     : 2016:05:26 15:13:54-07:00
Metadata Date                   : 2016:05:26 15:13:54-07:00
Producer                        : Acrobat Distiller 3.0 for Power Macintosh
Document ID                     : uuid:5a0e0003-0ae6-7f44-98c2-dfecd5a7a7db
Instance ID                     : uuid:3201847b-27a5-fd4c-ae14-99521960965f
Page Layout                     : SinglePage
Page Count                      : 292
Author                          : sikard

EXIF Metadata provided by EXIF.tools

Book.B V2300A_PG1 V2300A PG1

V2300A_PG1 V2300A_PG1

Navigation menu

Versions of this User Manual:

Views

Navigation