WE_32100_Microprocessor_Information_Manual_Jan85 WE 32100 Microprocessor Information Manual Jan85

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UNIX™ MICROSYSTEM

WE® 32100
MICROPROCESSOR
INFORMATION MANUAL

MAXI COMPUTING
IN

MICROSPACE

-AYlaY

451-000

~

UNIX™ MICROSYSTEM

WE® 32100
MICROPROCESSOR
INFORMATION MANUAL

451-000

-------------------------------------------~

ACKNOWLEDGEMENTS
Prepared and published by
Document Development Organization - Microelectronics Projects Group
AT&T Technologies, Inc., Morristown
for the
Microsystem Product Management
AT&T Technologies, Inc.
and the
4516 Microsystems Laboratory
AT&T Bell Laboratories, Holmdel

A WORD ABOUT TRADEMARKS
The following trademarks are mentioned in this manual:
W£® 32100 Microprocessor
W£® 32101 Memory Management Unit
W£® 32102 Clock
W£® 321AP Microprocessor Analysis Pod
W£® 321DS Microprocessor Development System
W£® 321EB Microprocessor Evaluation Board
W£® 321SD Development Software Programs
W£® 321SE Software Evaluation Program
W£® 321SG Software Generation Programs

are registered trademarks of AT&T Technologies, Inc.
AT&T 3B20S Computers is a trademark of AT&T.

UNIX™ Operating System is a trademark of AT&T Bell Laboratories.
PDp™ 11170 Computer and VAXTM 111780 Computer are trademarks of Digital
Equipment Corporation.

IBM® 370 Computer is a registered trademark of the IBM Corporation.
AT & T Technologies, Inc., reserves the right to make changes to the products(s) or circuit(s) described herein
without notice. No 6ahiJity is assumed as a result of their use or app6cation. No right under any patent
accompany the sale of any such product or circuit.
1985 AT&T Technologies, Inc. AU Rights Reserved.
Printed in the United States of America

@

104287958
IM23210OCPU01l5

January 1985

_

ATSaT

WE® 32H)0 Microprocessor
KmformatioHll MamliaR

The information contained herein is subject to change.

FOREWORD

This manual contains information on the WE 32100 Microprocessor that is essential
to computer designers, software architects, and system design engineers. The support
software and development tools available simplify system integration for this complex
32-bit microprocessor. This issue contains a description of the version SVR2.0 of the
WE 321SG Software Generation Programs.
Additional information is available in the form of data sheets, application notes, and
on-line documentation from the UNIX Operating System.

For additional information contact your Sales Account Representative or call:

o Commercial sales: 1-800-372-2447
o AT&T and Associated Company sales: (215) 770-3204 or (CORNET) 8+624-3204.
To obtain additional copies of this manual, Select Code 451-000, call:

o 1-800-432-6600.
iii

WE 32100 MICROPROCESSOR INFORMATION MANUAL

CONTENTS
CHAPTER 1.

INTRODUCTION

1. Introduction .................................................................................................................
1.1 Overview ....................................................................................................................
1.2 Architecture ..............................................................................................................
1.3 Instruction Set...........................................................................................................
1.4 Operating System Support........................................................................................
1.5 Software Generation Programs.................................................................................

CHAPTER 2.

1-1
1-1
1-2
1-4
1-4
1-5

ARCHITECTURE AND BUS OPERATION

2. WE 32100 MICROPROCESSOR OVERVIEW .................................................... 2-1

2.1 USER REGISTERS ...............................................................................................
2.1.1 General-Purpose Registers (rO-r8) ....................................................................
2.1.2 Frame Pointer .......................................................................................................
2.1.3 Argument Pointer .................................................................................................
2.1.4 Processor Status Word..........................................................................................
2.1.5 Stack Pointer .........................................................................................................
2.1.6 Process Control Block Pointer ..............................................................................
2.1.7 Interrupt Stack Pointer .........................................................................................
2.1.8 Program Counter ..................................................................................................
2.2 DATA HANDLING ...............................................................................................
2.2.1 Data Types ............................................................................................................
2.2.2 Data in Memory ...................................................................................................
2.2.3 Memory Management ..........................................................................................
2.3 SIGNAL SAMPLING POINTS ...........................................................................
2.4 READ AND WRITE OPERATIONS ..................................................................
2.4.1 Read Transaction Using SRDY ............................................................................
2.4.2 Read Transaction Using DTACK .........................................................................
2.4.3 Read Transaction With Wait Cycle Using SRDY ...............................................
2.4.4 Read Transaction With Two Wait Cycles Using DTACK ..................................
2.4.5 Write Transaction Using SRDY ...........................................................................
2.4.6 Write Transaction Using DTACK ........................................................................
2.4.7 Write Transaction With Wait Cycle Using SRDY..............................................
2.4.8 Write Transaction With Wait Cycle Using DTACK ...........................................
2.5 READ INTERLOCKED OPERATION ...............................................................
2.6 BLOCKFETCH OPERATION ..............................................................................
2.6.1 Blockfetch Transaction Using SRDY ...................................................................
2.6.2 Blockfetch Transaction Using DTACK ................................................................
2.6.3 Blockfetch Transaction Using DTACK With Wait Cycle On Second Word ......
2.6.4 Blockfetch Transaction Using SRDY With Wait Cycles On Both Words .........
2.7 BUS EXCEPTIONS ...............................................................................................

2-3
2-4
2-4
2-4
2-4
2-7
2-7
2-7
2-8
2-8
2-8
2-10
2-10
2-11
2-12
2-13
2-15
2-16
2-17
2-18
2-18
2-18
2-22
2-22
2-25
2-25
2-27
2-28
2-29
2-30

v

2.7.1 Faults......................................................................................................................
Fault With SRDy.................................................................................................
Fault After DTACK..............................................................................................
2.7.2 Retry .......................................................................................................................
2.7.3 Relinquish and Retry .............................................................................................
2.8 BLOCKFETCH SPECIAL CASES .. .,....................................................................
2.8.1 Fault on First Word of Blockfetch With Status Code Other Than Prefetch ......
2.8.2 Fault on First Word of Blockfetch With Status of Prefetch ................................
2.8.3 Retry on First Word of Blockfetch .......................................................................
2.8.4 Retry on Second Word of Blockfetch....................................................................
2.8.5 Relinquish and Retry of Blockfetch ......................................................................
2.9 INTERRUPTS .........................................................................................................
2.9.1 Interrupt Acknowledge ..........................................................................................
2.9.2 Auto-vector Interrupt.............................................................................................
2.9.3 Nonmaskable Interrupt..........................................................................................
2.9.4 Quick Interrupt ......................................................................................................
2.10 BUS ARBITRATION ...........................................................................................
2.10.1 Bus Request During a Bus Transaction ..............................................................
2.10.2 DMA Operation ...................................................................................................
2.11 RESET ....................................................................................................................
2.11.1 System Reset ........................................................................................................
2.11.2 Internal Reset .......................................................................................................
2.11.3 Reset Sequence.....................................................................................................
2.12 ABORTED MEMORY ACCESSES ....................................................................
2.12.1 Aborted Access on PC Discontinuity With Instruction Cache Hit....................
2.12.2 Alignment Fault Bus Activity..............................................................................
2.13 SINGLE-STEP OPERATION ..............................................................................
2.14 COPROCESSOR OPERATIONS ........................................................................
2.14.1 Coprocessor Broadcast .........................................................................................
2.14.2 Coprocessor Operand Fetch.................................................................................
2.14.3 Coprocessor Status Fetch.....................................................................................
2.14.4 Coprocessor Data Write.......................................................................................
2.15 EXCEPTIONAL CONDITIONS .........................................................................
2.16 TRACE MECHANISM ........................................................................................
2.17 PIN ASSIGNMENTS ...........................................................................................
2.18 MICROPROCESSOR OPERATING REQUIREMENTS ................................
2.18.1 Electrical Requirements .......................................................................................
2.18.2 Clocking Requirements ........................................................................................
2.18.3 Thermal Requirements ........................................................................................
2.19 SUPPLEMENTARY PROTOCOL DIAGRAMS ...............................................

CHAPTER 3.

INSTRUCTION SET AND ADDRESSING MODES

3. INSTRUCTION SET ................................................................................................
3.1 DATA TyPES..........................................................................................................
3.1.1 Sign and Zero Extension ........................................................................................
3.2 REGISTERS ............................................................................................................
3.2.1 Writing and Reading Registers .............................................................................
3.3 INSTRUCTION FORMAT ....................................................................................
3.3.1 Data Embedded in Operands .................................................................................
3.4 ADDRESS MODES ................................................................................................

vi

2-30
2-32
2-33
2-34
2-34
2-37
2-37
2-37
2-37
2-37
2-42
2-42
2-42
2-45
2-45
2-48
2-48
2-48
2-51
2-52
2-52
2-52
2-54
2-54
2-55
2-56
2-57
2-58
2-58
2-632-64
2-65
2-66
2-69
2-70
2-83
2-84
2-85
2-85
2-87

3-1
3-1
3-3
3-3
3-6
3-6
3-6
3-6

3.4.1 Absolute Address Modes .......................................................................................
Absolute..................................................................................................................
Absolute Deferred ..................................................................................................
3.4.2 Displacement Modes ..............................................................................................
Byte Displacement.. ........ ........ ......... ........................................................... ...........
Byte Displacement Deferred..................................................................................
Halfword Displacement ................................. ........................................................
Halfword Displacement Deferred..........................................................................
Word Displacement................................................................................................
Word Displacement Deferred .......................... ........................................ ..............
AP Short Offset.............................................. .................................. ......................
FP Short Offset ......................................................................................................
3.4.3 Immediate Modes...................................................................................................
Byte Immediate......................................................................................................
Halfword Immediate ..............................................................................................
Word Immediate ....................................................................................................
Positive Literal.......................................................................................................
Negative Literal.....................................................................................................
3.4.4 Register Modes ......................................................................................................
Register Mode........................................................................................................
Register Mode Deferred ......... ....................... .............. ..........................................
3.4.5 Expanded-Operand Type Mode.............................................................................
3.5 CONDITION FLAGS .............................................................................................
3.6 FUNCTIONAL GROUPS ......................................................................................
3.6.1 Data Transfer Instructions ....................................................................................
3.6.2 Arithmetic Instructions ..........................................................................................
3.6.3 Logical Instructions................................................................................................
3.6.4 Program Control Instructions ................................................................................
Subroutine Transfer .............................................................................................
Procedure Transfer ..............................................................................................
3.6.5 Coprocessor Instructions ........................................................................................
3.6.6 Stack and Miscellaneous Instructions ...................................................................
3.7 INSTRUCTION SET LISTINGS..........................................................................
3.7.1 Notation..................................................................................................................
Assembler Syntax ................................................................................................
Opcodes ................................................................................................................
Operation..............................................................................................................
Address Modes.....................................................................................................
Condition Flags ....................................................................................................
Exceptions ............................................................................................................
Examples ..............................................................................................................
Notes (Optional) ..................................................................................................
3.7.2 Instruction Set Descriptions...................................................................................
Add (ADDB2, ADDH2, ADDW2) ......................................................................
Add, 3 Address (ADDB3, ADDH3, ADDW3) ....................................................
Arithmetic Left Shift (ALSW3) ...........................................................................
AND (ANDB2, ANDH2, ANDW2) ...................................................................
AND, 3 Address (ANDB3, ANDH3, ANDW3) .................................................
Arithmetic Right Shift (ARSB3, ARSH3, ARSW3) ..........................................
Branch on Carry Clear (BCCB, BCCH).... .................. ...... .......................... ........
Branch on Carry Set (BCSB, BCSH) ..................................................................
Branch on Equal (BEB, BEH) ..............................................................................

3-10
3-10
3-11
3-11
3-11
3-12
3-12
3-13
3-14
3-14
3-15
3-15
3-16
3-16
3-17
3-17
3-18
3-18
3-19
3-19
3-19
3-20
3-22
3-23
3-23
3-25
3-26
3-28
3-28
3-28
3-32
3-32
3-33
3-34
3-34
3-34
3-34
3-34
3-34
3-34
3-34
3-34
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
3-45

vii

Branch on Greater Than (Signed) (BGB, BGH) .................................................
Branch on Greater Than or Equal (Signed) (BGEB, BGEH) ............................
Branch on Greater Than or Equal (Unsigned) (BGEUB, BGEUH) .................
Branch on Greater Than (Unsigned) (BGUB, BGUH) ......................................
Bit Test (BITB, BITH, BITW) ............................................................................
Branch on Less Than (Signed) (BLB, BLH) .......................................................
Branch on Less Than or Equal (Signed) (BLEB, BLEH) ..................................
Branch on Less Than or Equal (Unsigned) (BLEUB, BLEUH) .......................
Branch on Less Than (Unsigned) (BLUB, BLUH) .............................................
Branch on Not Equal (BNEB, BNEH) ................................................................
Breakpoint Trap (BPT) .........................................................................................
Branch (BRB, BRH) .............................................................................................
Branch to Subroutine (BSBB, BSBH) ..................................................................
Branch on Overflow Clear (BVCB, BVCH) .........................................................
Branch on Overflow Set (BVSB, BVSH) .............................................................
Call Procedure (CALL) ........................................................................................
Cache Flush (CFLUSH) .......................................................................................
Clear (CLRB, CLRH, CLRW) ............................................................................
Compare (CMPB, CMPH, CMPW) ....................................................................
Decrement (DECB, DECH, DECW) ...................................................................
Divide (DIVB2, DIVH2, DIVW2) .......................................................................
Divide, 3 Address (DIVB3, DIVH3, DIVW3) .....................................................
Extract Field (EXTFB, EXTFH, EXTFW) .................................. ......................
Extended Opcode (EXTOP) ..................................................................................
Increment ONCB, INCH, INCW) ......................................................................
Insert Field ONSFB, INSFH, INSFW) ..............................................................
Jump (JMP) ...........................................................................................................
Jump to Subroutine (JSB) .....................................................................................
Logical Left Shift (LLSB3, LLSH3, LLSW3) ....................................................
Logical Right Shift (LRSW3) ..............................................................................
Move Complemented (MCOMB, MCOMH, MCOMW) ...................................
Move Negated (MNEGB, MNEGH, MNEGW) ................................................
Modulo (MODB2, MODH2, MODW2) ..............................................................
Modulo, 3 Address (MODB3, MODH3, MODW3) ............................................
Move (MOVB, MOVH, MOVW) ........................................................................
Move Address, Word (MOV A W) ........................................................................
Move Block (MOVBLW) ......................................................................................
Multiply (MULB2, MULH2, MUL W2) .............................................................
Multiply, 3 Address (MULB3, MULH3, MULW3) ...........................................
Move Version Number (MVERNO) ....................................................................
No Operation (NOP, NOP2, NOP3) ...................................................................
OR (ORB2, ORH2, ORW2) ................................................................................
OR, 3 Address (ORB3, ORH3, ORW3) ..............................................................
Pop (Word) (POPW) ............................................................................................
Push Address (Word) (PUS HAW) ......................................................................
Push (Word) (PUSHW) .......................................................................................
Return on Carry Clear (RCC) ..............................................................................
Return on Carry Set (RCS) ..................................................................................
Return on Equal (REQL, REQLU) .....................................................................
Restore Registers (RESTORE) ............................................................................

viii

3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-65
3-66
3-67
3-68
3-69
3-70
3-71
3-72
3-73
3-74
3-75
3-76
3-77
3-78
3-79
3-80
3-82
3-83
3-85
3-86
3-87
3-88
3-89
3-90
3-91
3-92
3-93
3-94
3-95
3-96
3-97

Return from Procedure (RET) .............................................................................
Return on Greater Than or Equal (Signed) (RGEQ) .........................................
Return on Greater Than or Equal (Unsigned) (RGEQU) .................................
Return on Greater Than (Signed) (RGTR). ........................................................
Return on Greater Than (Unsigned) (RGTRU) .................................................
Return on Less Than or Equal (Signed) (RLEQ) ...............................................
Return on Less Than or Equal (Unsigned) (RLEQU) ........................................
Return on Less Than (Signed) (RLSS) ...............................................................
Return on Less Than (Unsigned) (RLSSU) ........................................................
Return on Not Equal (RNEQ, RENQV» ...........................................................
Rotate (ROTW) ....................................................................................................
Return from Subroutine (RSB) ............................................................................
Return on Overflow Clear (RVC) .........................................................................
Return on Overflow Set (R VS) .............. ...............................................................
Save Registers (SAVE) .........................................................................................
Coprocessor Operation (no operands) (SPOP) ....................................................
Coprocessor Operation Read (SPOPRS, SPOPRD, SPOPRT) ..........................
Coprocessor Operation, 2-Address (SPOPS2, SPOPD2, SPOPT2) ....................
Coprocessor Operation Write (SPOPWS, SPOPWD, SPOPWT) ......................
String Copy (STRCPY) ........................................................................................
String End (STREND) .........................................................................................
Subtract (SUBB2, SUBH2, SUBW2) ..................................................................
Subtract, 3 Address (SUBB3, SUBH3, SUBW3) ...............................................
Swap (Interlocked) (SWAPBI, SWAPHI, SWAPWI) .......................................
Test (TSTB, TSTH, TSTW) ................................................................................
Exclusive Or (XORB2, XORH2, XORW2) ........................................................
Exclusive Or, 3 Address (XORB3, XORH3, XORW3) ......................................
3.7.3 Instruction Set Summary by Function ..................................................................
3.7.4 Instruction Set Summary by Mnemonic ...............................................................
3.7.5 Instruction Set Summary by Opcode ....................................................................

CHAPTER 4.

3-98
3-99
3-100
3-101
3-102
3-103
3-104
3-105
3-106
3-107
3-108
3-109
3-110
3-111
3-112
3-113
3-114
3-115
3-116
3-117
3-119
3-120
3-121
3-122
3-123
3-124
3-125
3-126
3-132
3-136

OPERATING SYSTEM CONSIDERATIONS

4. OPERATING SYSTEM CONSIDERATIONS ......................................................
4.1 FEATURES OF THE OPERATING SYSTEM ...................................................
4.1.1 Memory Management Considerations for Virtual Memory Systems ..................
4.2 STRUCTURE OF A PROCESS ............................................................................
4.2.1 Execution Privilege.................................................................................................
4.2.2 Execution Stack......................................................................................................
4.2.3 Process Control Block ................................................................... .........................
Initial Context for a Process ........................................................ ..........................
Saved Context for a Process ..................................................................................
Memory Specifications ...........................................................................................
4.2.4 Processor Status Word...........................................................................................
4.3 SYSTEM CALL .......................................................................................................
4.3.1 Gate Mechanism ....................................................................................................
Pointer Table..........................................................................................................
Handling-Routine Tables.......................................................................................

4-1
4-1
4-4
4-4
4-5
4-5
4-6
4-9
4-9
4-9
4-10
4-10
4-13
4-13
4-13

ix

4.3.2 GATE Instruction ..................................................................................................
First Entry Point ....................................................................................................
Second Entry Point - The Gate Mechanism .......................................................
4.3.3 Return-From-Gate Instruction ..............................................................................
4.4 PROCESS SWITCHING ........................................................................................
4.4.1 Context Switching Strategy .................. .................................................................
RBit .......................................................................................................................
I Bit ........................................................................................................................
4.4.2 Call Process Instruction .........................................................................................
4.4.3 Return-to-Process Instruction ................................................................................
4.5 INTERRUPTS .........................................................................................................
4.5.1 Interrupt-Handler Model.......................................................................................
4.5.2 Interrupt Mechanism .............................................................................................
Full-Interrupt Handler's PCB ...............................................................................
Interrupt Stack and ISP ........................................................................................
Interrupt-Vector Table...........................................................................................
4.5.3 On-Interrupt Microsequence..................................................................................
4.5.4 Returning From an Interrupt ................................................................................
Full Interrupts ........................................................................................................
Quick Interrupts.....................................................................................................
4.6 EXCEPTIONS .........................................................................................................
4.6.1 Levels of Exception Severity..................................................................................
4.6.2 Exception Handler .................................................................................................
4.6.3 Exception Microsequences .....................................................................................
Normal Exceptions.................................................................................................
Stack Exceptions ....................................................................................................
Process Exceptions .................................................................................................
Reset Exceptions ....................................................................................................
4.7 MEMORY MANAGEMENT FOR VIRTUAL MEMORY SYSTEMS ...........
4.7.1 Initializing the Memory Management Unit.. ........................................................
Defining Virtual Memory ......................................................................................
Peripheral Mode..................................... ................................................................
4.7.2 MMU Interactions.................................................................................................
MMU Exceptions...................................................................................................
Flushing..................................................................................................................
4.7.3 Efficient Mapping Strategies .................................................................................
4.7.4 Object Traps...........................................................................................................
4.7.5 Indirect Segment Descriptors ................................................................................
4.7.6 Using the Cacheable Bit ........................................................................................
4.7.7 Using the Page-Write Fault ..................................................................................
4.7.8 Access Protection ...................................................................................................
4.7.9 Using the Software Bits.........................................................................................
4.8 OPERATING SYSTEM INSTRUCTIONS .........................................................
4.8.1 Notation..................................................................................................................
4.8.2 Privileged Instructions............................................................................................
4.8.3 Nonprivileged Instructions.....................................................................................
4.8.4 Microsequences ...................................... ................................................................

x

4-14
4-14
4-15
4-16
4-16
4-17
4-17
4-17
4-20
4-22
4-23
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-29
4-29
4-29
4-30
4-30
4-32
4-32
4-33
4-35
4-35
4-36
4-40
4-40
4-40
4-40
4-41
4-41
4-41
4-42
4-42
4-42
4-42
4-43
4-43
4-43
4-43
4-44
4-56
4-64

CHAPTER 5.

SOFTW ARE GENERATION PROGRAMS

5. INTRODUCTION TO THE SOFTWARE GENERATION
PROGRAMS (SGP) ...............................................................................................
Distinctive SGP Features............................................................................................
Host Computers ..........................................................................................................
5.1 COMPILER AND THE C LANGUAGE .............................................................
5.1.1 Compiler .................................................................................................................
Compiler Options .................................................................................................
Register Usage .....................................................................................................
5.1.2 C Language ............................................................................................................
Flexnames.............................................................................................................
Enumerations .......................................................................................................
Structure Assignment ..........................................................................................
Nonunique Structure Member Names ................................................................
Former Member Name Restrictions ...............................................................
New Flexibility for Member Names ...............................................................
Complete Structure and Union Member Reference Qualifications ...................
Nonunique Tag Names Allowed .........................................................................
Vertical Tab Character Literal...........................................................................
In-Line Procedure Expansion ..............................................................................
5.2 ASSEMBLER AND ASSEMBLY LANGUAGE .................................................
5.2.1 Assembler ...............................................................................................................
Assembled Files......................................................................................................
Diagnostics .............................................................................................................
Macro Processing Facilities ...................................................................................
Interface Macros ....................................................................................................
Function Interface Macros ..................................................................................
Scratch Register Macros .....................................................................................
Stack Frame Macros............................................................................................
Restrictions...........................................................................................................
Using Predefined Macros.......................................................................................
Examples ..............................................................................................................
M4 Reserved Words ..............................................................................................
5.2.2 Assembly Language ...............................................................................................
Statements ..............................................................................................................
Symbols ..................................................................................................................
Values and Types .................................................................................................
Assigning Values and Types to Symbols .............................................................
Constants ................................................................................................................
Location Counter ...................................................................................................
Registers .................................................................................................................
Executable Instructions..........................................................................................
Operands ................................................................................................................
Expressions .............................................................................................................
Assembler Directives..............................................................................................
Section Control Pseudo Operations .....................................................................
Pseudo Operations Dealing with Symbols...........................................................
Assignment Pseudo Operation .............................................................................
Assignment to Dot ...............................................................................................
Alignment Pseudo Operation...............................................................................
Data Generation Pseudo Operations ...................................................................

5-1
5-1
5-2
5-3
5-3
5-4
5-6
5-7
5-7
5-7
5-9
5-9
5-10
5-10
5-11
5-12
5-13
5-13
5-13
5-14
5-15
5-15
5-16
5-17
5-18
5-19
5-19
5-19
5-20
5-21
5-22
5-22
5-23
5-24
5-24
5-25
5-25
5-25
5-26
5-27
5-28
5-30
5-31
5-31
5-33
5-33
5-34
5-35
5-35
xi

Symbolic Debugging Pseudo Operations.............................................................
File Name Pseudo Operation ..............................................................................
Line Number Pseudo Operation..........................................................................
Function Calling Sequence ....................................................................................
Stack Frame.........................................................................................................
Actions of Calling Function.................................................................................
Actions of Called Function..................................................................................
5.2.3 Exception Conditions .............................................................................................
5.2.4 Programming Example ..........................................................................................
5.2.5 Machine Independent Instruction Set ...................................................................
5.3 LINK EDITOR ........................................................................................................
5.3.1 Link Editor Command ...........................................................................................
Command Line Options ... ....... ..... ..... ............................... .......................... ...... ......
5.3.2 Link Editor Command Language ..........................................................................
Expressions .............................................................................................................
Assignment Statements..........................................................................................
Memory Configurations .........................................................................................
Section Definition Directives .................................................................................
Virtual Address and Bindings..............................................................................
File Specifications ................................................................................................
Load a Section at a Specified Address................................................................
Aligning an Output Section.................................................................................
Grouping Sections Together ................................................................................
Creating Holes Within Output Sections .............................................................
Creating And Defining Symbols at Link-Edit Time...........................................
Allocating a Section Into Named Memory .........................................................
Initialized Section Holes or BSS Sections ..........................................................
Notes on the Use of m32ld..................................................................................
Changing the Entry Point....................................................................................
Use of Archive Libraries .....................................................................................
Dealing With Holes In Physical Memory ...........................................................
Allocation Algorithm ...........................................................................................
Subsystems (Incremental) Link Editing .............................................................
Nonrelocatable Input Files ..................................................................................
DSECT, COPY and NLOAD Sections ..............................................................
Output File Blocking............................................................................................
5.3.3 Error Messages.......................................................................................................
Corrupt Input Files ................................................................................................
Errors During Output ............................................................................................
Internal Errors ....... ................. ................... .... ....... ............ ......... ................... .........
Allocation Errors....................................................................................................
Misuse of Link Editor Directives ..........................................................................
Misuse of Expressions ............................................................................................
Misuse of Options ..................................................................................................
Space Restraints..... ...... ....................... ............................... ............... .....................
Miscellaneous Errors..............................................................................................
5.3.4 Syntax Diagram for Input Directives ....................................................................
5.4 OBJECT FILE FORMAT .......................................................................................
5.4.1 Definitions...............................................................................................................
5.4.2 File Header.............................................................................................................
Flags .......................................................................................................................
Optional Header Information ..............................................................................
Standard UNIX System a.out Header ..................................................................
xii

5-36
5-37
5-37
5-37
5-38
5-39
5-39
5-43
5-43
5-45
5-48
5-48
5-50
5-51
5-52
5-53
5-53
5-55
5-56
5-56
5-57
5-57
5-58
5-59
5-60
5-61
5-61
5-62
5-62
5-63
5-64
5-65
5-66
5-67
5-67
5-68
5-68
5-68
5-69
5-70
5-70
5-71
5-72
5-72
5-73
5-73
5-74
5-77
5-78
5-79
5-79
5-80
5-80

5.4.3 Section Header Table ............................................................................................
Flags .......................................................................................................................
.bss Section Header................................................................................................
5.4.4 Sections...................................................................................................................
5.4.5 Relocation Information ..........................................................................................
5.4.6 Line Numbers ........................................................................................................
5.4.7 Symbol Table .........................................................................................................
Special Symbols .....................................................................................................
Inner Blocks .........................................................................................................
Symbols For Functions ........................................................................................
Symbol Table Entries ............................................................................................
Symbol Name Field (n name) ............................................................................
Symbol Value Field And Storage Classes (n_value) ..........................................
Section Number Field (n scnum) .......................................................................
Type Field (n_type) ........-::...................................................................................
Structure for Symbol Table Entry......................................................................
Auxiliary Table Entries .........................................................................................
File Names ...........................................................................................................
Sections.. ...... ........... ....................... ........... ........................................ ....................
Tag Names...........................................................................................................
End of Structures .................................................................................................
Functions .. ............ ................ ......................................... .......................................
Arrays...................................................................................................................
End of Blocks and Functions ...... ............ ...................... .......................................
Beginning of Blocks and Functions.. .................................................. .................
Names Related to Structures, Unions, and Enumerations .................................
5.4.8 String Table ...........................................................................................................
5.5 UTILITIES AND LIBRARY ROUTINES ...........................................................
5.5.1 Utility Programs.....................................................................................................
m32ar ...................................................................................................................
m32convert ...........................................................................................................
m32cprs ................................................................................................................
m32dis ..................................................................................................................
m32dump..............................................................................................................
m32list ..................................................................................................................
m32lorder .............................................................................................................
m32nm..................................................................................................................
m32size.................................................................................................................
m32strip................................................................................................................
5.5.2 Accessing Library ..................................................................................................
Use of the Accessing Library................................................................................
Library Functions And Macros .............................. ...............................................
Functions That Open or Close Object Files ........................................................
Functions That Read ...........................................................................................
Functions That Seek ............................................................................................
Function That Returns the Index of a Symbol Table Entry ..............................
Macros ..................................................................................................................
5.5.3 General-Purpose Library .......................................................................................
Use of the General Purpose Library ...................................................................
Routines in the General Purpose Library ...........................................................
Routines Required When Using printf and scanf.. .............................................
5.6 SGP MANUAL PAGES .........................................................................................

5-81
5-82
5-82
5-82
5-83
5-84
5-84
5-84
5-86
5-89
5-89
5-90
5-90
5-93
5-94
5-97
5-97
5-98
5-98
5-99
5-99
5-99
5-99
5-100
5-100
5-100
5-101
5-102
5-103
5-103
5-105
5-107
5-108
5-111
5-113
5-114
5-114
5-116
5-116
5-117
5-117
5-118
5-118
5-120
5-120
5-120
5-121
5-121
5-121
5-122
5-123
5-124

xiii

GLOSSARY AND ACRONYMS
INDEX
LIST OF FIGURES
Figure 1-1.
Figure 1-2.
Figure 1-3.

The WE 32100 Microprocessor ................................................................. 1-1
WE 321AP Microprocessor Analysis Pod ................................................. 1-3
WE 321EB Microprocessor Evaluation Board .......................................... 1-3

Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

WE 32100 Microprocessor Block Diagram .............................................. .
Programmer's Model for User Registers .................................................. .
Processor Status Word .............................................................................. .
Bit Order of Data ...................................................................................... .
Bit Field Data Type .................................................................................. .
Signal Sampling Points ............................................................................. .
Read Transaction (Using SRDY) ............................................................. .
Read Transaction (Using DTACK) .......................................................... .
Read Transaction with One Wait Cycle (Using SRDY) ........................ ..
Read Transaction With Two Wait Cycles (Using DTACK) .................. ..
Write Transaction (Using SRDY) ............................................................ .
Write Transaction (Using DTACK) ......................................................... .
Write Transaction With Two Wait Cycles (Using SRDY) ..................... .
Write Transaction With One Wait Cycle (Using DTACK) .................... .
Read Interlocked Transaction (Using DTACK).. .................................... ..
Blockfetch Transaction (Using SRDY) ................................................... ..
Blockfetch Transaction (Using DTACK) ................................................. .
Blockfetch Transaction (Using DTACK) ................................................. .
Blockfetch Transaction (Using SRDY) .................................................... .
Asynchronous Fault Without DTACK and SRDY (Read Transaction) .. .
Fault with Synchronous Ready (SRDY); i.e., Synchronous Fault .......... .
Fault After Assertion of DTACK (Write Transaction is Shown) ........... .
Retry of Transaction (Read Transaction is Shown) ................................ .
Relinquish and Retry ................................................................................ .
Fault on First Word of Blockfetch Transaction
With Access Status Code (Not Instruction Prefetch) ........................... .
Fault on First Word of Blockfetch Transaction
With Access Status Code of Prefetch ..................................................... .
Retry on First Word of Blockfetch Transaction ...................................... .
Retry on Second Word of Blockfetch ....................................................... .
Interrupt Acknowledge ............................................................................. .
Auto-Vector Interrupt Acknowledge ........................................................ .
Nonmaskable Interrupt Acknowledge ...................................................... .
Bus Request During a Transaction .......................................................... .
Reset Sequence .......................................................................................... .
Aborted Access on I-Cache Hit with PC Discontinuity .......................... .
Alignment Fault Bus Activity (Write Transaction is Shown) ................ .
Start of Single-Step Operation ................................................................. .
Single-Step Operation ............................................................................... .

2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.

Figure 2-26.
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
2-34.
2-35.
2-36.
2-37.

2-2
2-3
2-4
2-9
2-9
2-11

2-14
2-15
2-16
2-17
2-19
2-20
2-21
2-23
2-24
2-26
2-27
2-28
2-29
2-31
2-32
2-33
2-35
2-36
2-38
2-39
2-40
2-41
2-43
2-46
2-47
2-49
2-54
2-55
2-56
2-57
2-58

Figure 2-38. Coprocessor Command and ID Transfer...................................................
Figure 2-39. Coprocessor Command and ID Transfer
(No Coprocessor Present) ........................................................................
Figure 2-40. Coprocessor Operand Fetch .......................................................................
Figure 2-41. Coprocessor Status Fetch (Using SRDY) .................................................
Figure 2-42. Coprocessor Data Write.............................................................................
Figure 2-43. WE 32100 Microprocessor Pin Configuration...........................................
Figure 2-44. Read Transaction Followed by a Read Transaction .................................
Figure 2-45. Read Transaction Followed by a Write Transaction
(Using DTACK) ........................................................................................
Figure 2-46. Write Transaction Followed by a Write Transaction ................................
Figure 2-47. Write Transaction Followed by a Read Transaction .................................
Figure 2-48. Double-Word Program Fetch Without Blockfetch
Transaction (using DTACK) ....................................................................
Figure 2-49. Bus Arbitration During Relinquish and Retry ..........................................

2-59
2-62"
2-63
2-64
2-65
2-71
2-88
2-89
2-90
2-91
2-92
2-93

Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.

Bit Order of Data.......................................................................................
Bit Order in a Bit Field .............................................................................
Extending Data to 32 Bits .........................................................................
Register as a Source Operand ...................................................................
General Instruction Format .......................................................................
Data Embedded in an Operand .................................................................
Expanded-Operand Type Descriptor .........................................................
Condition Flags ..........................................................................................
Stack After CALL-SAVE Sequence.........................................................

3-2
3-2
3-5
3-5
3-7
3-7
3-21
3-22
3-31

Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.

A Typical Process Control Biock .......................... "...................................
Tables for the Gate Mechanism ................................................................
A PCB on an Initial Process Switch to a Process .....................................
A PCB on a Process Switch During Execution of a Process ....................
An Interrupt Stack.....................................................................................
Interrupt Vector Tables .............................................................................
Exception-Vector Table .............................................................................
Virtual Address Fields for a Contiguous Segment ...................................
Virtual Address Fields for a Paged Segment............................................
Virtual to Physical Translation for Contiguous Segments ........................
Virtual to Physical Translation for Paged Segments ................................

4-8
4-15
4-19
4-20
4-26
4-27
4-31
4-37
4-37
4-38
4-39

Figure
Figure
Figure
Figure
Figure
Figure
Figure

5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.

Major Steps in the SGP.............................................................................
Mapping Program Sections........................................................................
Typical Stack Frame for a Function Call .................................................
Stack Frame Following a Call Instruction ................................................
Stack Frame After Three Registers are Saved .........................................
Object File Format.....................................................................................
COFF Symbol Table..................................................................................

5-2
5-16
5-41
5-42
5-42
5-78
5-85

xv

LIST OF TABLES
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table

2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.

Processor Status Word Fields .....................................................................
Memory Write Summary ............................................................................
Simultaneously Asserted Exception Conditions ................... :......................
Interrupt Level Code Assignments .............................................................
Interrupt Acknowledge Summary ...............................................................
Output Signal States after DMA Request is Acknowledged .....................
Output States on Reset ...............................................................................
Exception Conditions...................................................................................
Truth Table for Trace Trap ........................................................................
WE 32100 Microprocessor Pin Descriptions ..............................................
Address and Data Signals ...........................................................................
Interface and Control Signals .....................................................................
Access Status Signals ..................................................................................
Interrupt Signals ..........................................................................................
Arbitration Signals ......................................................................................
Bus Exception Signals .................................................................................
Development System Support Signals ........................................................
Clock Signals ...............................................................................................
Operating Requirements .............................................................................
Output Electrical Specifications ..................................................................
Input Electrical Specifications ....................................................................

2-5
2-10
2-30
2-44
2-50
2-51
2-53
2-66
2-69
2-72
2-75
2-76
2-77
2-79
2-80
2-81
2-83
2-83
2-85
2-86
2-86

Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table

3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.

Register Set ...................................................... .............................. .............
Addressing Modes .......................................................................................
Options for type in Expanded-Operand Mode ...........................................
Data Transfer Instruction Group................................................................
Arithmetic Instruction Group .....................................................................
Logical Group..............................................................................................
Program Control Instructions......................................................................
Coprocessor Instructions..............................................................................
Stack and Miscellaneous Instructions.........................................................
Condition Flag Code Assignments ..............................................................
Assembly Language Operators and Symbols .............................................
Data Transfer Instruction Group ................................................................
Arithmetic Instruction Group .....................................................................
Logical Group..............................................................................................
Program Control Instructions ......................................................................
Coprocessor Instructions..............................................................................
Stack and Miscellaneous Instructions.........................................................
Instruction Set Summary by Mnemonic .....................................................
Instruction Set Summary by Opcode ..........................................................

3-4
3-9
3-21
3-24
3-25
3-27
3-29
3-33
3-33
3-34
3-36
3-126
3-126
3-128
3-129
3-131
3-131
3-132
3-136

Table 4-1.
Table '4-2.
Table 4-3.

xvi

Operating System Instructions .................................................................... 4-2
PCBP Locations........................................................................................... 4-7
Processor Status Word Fields ..................................................................... 4-11

Table
Table
Table
Table
Table

4-4.
4-5.
4-6.
4-7.
4-8.

Severity Levels for Exceptions ....................................................................
Normal Exceptions (ET=3) ........................................................................
Stack Exceptions (ET=2) ...........................................................................
Process Exceptions (ET=I) ........................................................................
Reset Exceptions (ET=O) ...........................................................................

4-30
4-33
4-34
4-35
4-36

Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table

5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
5-37.
5-38.
5-39.

SGP Tools ....................................................................................................
m32cc Command Line Options...................................................................
m32as Command Line Options ...................................................................
Address Modes ............................................................................................
Alphabetical List of Pseudo-Operations .....................................................
Machine Independent Instruction Set.........................................................
m321d Command Line Options ...................................................................
File Header Contents ..................................................................................
File Header Flags ........................................................................................
Optional Header Contents...........................................................................
Section Header Contents .............................................................................
Section Types...............................................................................................
Special Symbols in the Symbol Table ........................................................
Symbol Table Entry Format.......................................................................
n_name Entry Formats ................................................................................
Symbol Values .............................................................................................
Dummy Storage Classes..............................................................................
Restricted Special Symbols .........................................................................
Restricted Storage Classes ..........................................................................
Section Numbers .........................................................................................
Restricted Storage Classes ..........................................................................
Fundamental Types .....................................................................................
Derived Types ..............................................................................................
Storage Class Type Entries .........................................................................
Auxiliary Symbol Table Entries .................................................................
Section Format ............................................................................................
Tag Name Format.......................................................................................
End of Structure Format.............................................................................
Function Format..........................................................................................
Array Format...............................................................................................
End of Block and Function Format............................................................
Beginning of Block and Function Format ..................................................
Structure, Union, and Enumeration Format ..............................................
m32ar Command Line Keys .......................................................................
m32convert Target Machines......................................................................
m32dis Command Line Options ..................................................................
m32dump Command Line Options .............................................................
m32nm Command Line Options .................................................................
SGP Manual Pages .....................................................................................

5-3
5-5
5-16
5-29
5-32
5-46
5-50
5-79
5-80
5-80
5-81
5-82
5-85
5-89
5-90
5-91
5-92
5-92
5-92
5-93
5-94
5-95
5-95
5-96
5-98
5-98
5-99
5-99
5-99
5-100
5-100
5-100
5-101
5-104
5-107
5-109
5-112
5-115
5-124

xvii

Chapter 1

Introduction

CHAPTER 1. INTRODUCTION
CONTENTS

1. Introduction..................................................................................................................
1.1 Overview .....................................................................................................................
1.2 Architecture ..... ....... ....... ........ ..... ....... ....... ............. ..... .... ........ ..... ..... .........................
1.3 Instruction Set............................................................................................................
1.4 Operating System Support.........................................................................................
1.5 Software Generation Programs..................................................................................

1·1
1·1
1·2
1·4
1·4
1·5

INTRODUCTION
Overview

I. INTRODUCfION
This chapter introduces the WE 32100 Microprocessor and summarizes the support
products available for it. The chapters describing the WE 32100 Microprocessor
architecture, instructiun set, operating system considerations, and software generation
programs are also introduced.

1.1 Overview
The WE 32100 Microprocessor is a high-performance, single-chip, 32-bit central processing
unit designed for efficient operation in a high-level language environment. The WE 32100
Microprocessor represents a state-of-the-art concept in microprocessor architecture,
providing one of the most powerful and extensive instruction sets available with any
microprocessor. The WE 32100 Microprocessor, packaged in .a I 32-pin ceramic pin array,
is shown on Figure I-I.

Figure 1-1. The WE 32100 Microprocessor

The system memory space is addressed over a full 32-bit address bus using either physical
or virtual addresses. The 32-bit address bus produces a vast memory space of more than
four billion bytes which increases the flexibility of memory organization and provides
ample space for the storage of software and data. Data can be read or written over the
separate 32-bit data bus in byte (S-bit), halfword (16-bit), or word (32-bit) lengths.
The WE 32100 Microprocessor is an efficient execution vehicle for operating systems and
high-level languages. The operating system instructions included in the instruction set
establish an environment that permits process switching and interrupt handling with a
minimum of operating system support. Other instructions allow the use of coprocessors
and provide the necessary signals for interfacing with the WE 32101 Memory Management
Unit for virtual memory systems.

1-1

INTRODUCTION
Architecture

Software support for the WE 32100 Microprocessor is available through the WE 321SG
Software Generation Programs (SGP). This collection of programs and utilities provides
everything necessary for rapid development of software. The high-level development
language is the C language, and the entire SGP resides in the UNIX Operating System.
The SGP includes a C compiler, an assembler, a link editor, and various utility programs.
Development support is available through the WE 321DS Microprocessor Development
System. The development system is a powerful development tool that can expedite the
integration of hardware and software into a finished application. It permits the debugging
of hardware and software to occur in parallel. The development system components
include the WE 321AP Microprocessor Analysis Pod, the WE 321SD Development
Software Programs, a UNIX System Host, and a logic analyzer. The modular design of
the development system enables the user to configure the system for maximum productivity
from initial hardware debug through the final stage of hardware and software integration.
The WE 321AP Microprocessor Analysis Pod is shown on Figure 1-2.
Prototyping and performance evaluation support is available through the WE 321EB
Microprocessor Evaluation Board. The evaluation board is a single-board microcomputer
evaluation system that provides a prototyping vehicle to evaluate the hardware and
software capabilities and performance of the WE 32100 Microprocessor in an application
environment. The board is supplied with a WE 32100 Microprocessor as the CPU, a
WE 32101 Memory Management Unit, a WE 32102 Clock, a ROM-based monitor,
read/write memory (RAM), and sockets for additional memory. Also included are address
decoding circuitry, RS-232C ports, programmable parallel 110 lines, programmable
interval timers, and an interrupt controller. The WE 321EB Microprocessor Evaluation
Board is shown on Figure 1-3.

1.2 Architecture
The WE 32100 Microprocessor performs all the system address generation, control,
memory access, and processing functions required in a 32-bit microcomputer system.
Execution speed is enhanced by its unique pipelined architecture. Using this architecture,
the microprocessor overlaps the execution of instructions while tracking each separately. In
addition, as each instruction is fetched from memory it is cached in an internal instruction
cache, resulting in even greater operating efficiency.
The CPU utilizes a combination of address and data strobes and interface and control
signals to provide the bus protocol required for efficient transfer of data. The protocol
facilitates interfacing to commercial memories and peripherals, as well as providing waitstate generation for handshaking with slow peripherals. In addition, the CPU also provides
special coprocessor signals for a high throughput coprocessing environment.
The architecture and a bus protocol for the WE 32100 Microprocessor is discussed in
Chapter 2. ARCHITECTURE AND BUS OPERATION.

1-2

INTRODUCTION
Architecture

.,
•• "IS'

__,

.

.,
.... .,

Figure 1-2.

Figure 1-3.

0 .. .. '

WE 321AP Microprocessor Analysis Pod

WE 321EB Microprocessor Evaluation Board

1-3

INTRODUCTION
Instruction Set

1.3 Instruction Set
The WE 32100 Microprocessor supports a powerful instruction set that includes standard
data transfer, arithmetic, and logical operations for microprocessors, plus several unique
operations. Its many program control instructions (branch, jump, return) provide
flexibility for altering the sequence of execution. Other instructions are designed to aid in
process switching for operating systems by manipulating the context of the processor with a
minimum of code. In addition, special coprocessor instructions are included in the
instruction set to implement a high-speed interface with special purpose coprocessors
planned for the WE 32100 Microprocessor.
Eighteen addressing modes are provided that include special high-level language support
modes such as frame pointer short offset and argument pointer short offset. These modes
are designed for referring to local variables of high-level functions and function arguments.
Chapter 3. INSTRUCTION SET AND ADDRESSING MODES contains a detailed
description of the WE 32100 Microprocessor Instruction Set.

1.4 Operating System Support
The WE 32100 Microprocessor is designed for high-level language and operating system
support. To aid in the design of process-oriented systems, it provides:
• four execution privilege levels: kernel, executive, supervisor, and user
• flexible transfer of execution control between privilege levels
• capability to have the operating system contained within the address space of every
process
• support of explicit process switching by a scheduler
• implicit switching of processes through the interrupt structure
• layered exception handling structure, with different mechanisms used for different
exceptions.
The processor groups all of the switchable process context into a compact area in memory
called the process control block. This feature, plus the use of the special operating system
instructions and microsequences, provides the programmer with an excellent tool for the
creation and support of process-oriented systems.
Chapter 4. OPERATING SYSTEM CONSIDERATIONS discusses the techniques for
efficient operating system design using the WE 32100 Microprocessor and also describes
the use of the WE 32101 Memory Management Unit in a virtual memory operating
system.

1-4

INTRODUCTION
Software Generation Programs

1.5 Software Generation Programs
The WE 321SG Software Generation Programs (SGP) is a package of support tools used
to create and test programs for the WE 32100 Microprocessor. The SGP runs under the
UNIX Operating System and uses many features of the UNIX System shell. The SGP
allows the programmer to generate code in the high-level C language and test programs at
the source leveL This improves productivity and program accuracy by freeing
programmers from the details of the hardware architecture associated with assembly
language programming.
The SGP contains a C compiler that converts C language programs into assembly language
programs. The assembly language programs are ultimately translated into object files by
the SGP assembler for the WE 32100 Microprocessor and link-edited into executable load
modules by the link editor (also contained in the SGP). Each of these tools preserves all
symbolic information necessary for meaningful symbolic testing at the source level. The
SGP also provides a variety of utilities that read and manipulate object files.
The SGP is described in detail in Chapter 5. SOFfWARE GENERATION PROGRAMS.

1-5

Chapter 2

Architecture and
Bus Operation

CHAPTER 2.

ARCHITECTURE & BUS OPERATION
CONTENTS

2. WE 32100 MICROPROCESSOR
OVERVIEW ......................................
2.1 USER REGISTERS......................
2. J.l General-Purpose Registers
(rO-r8) .......................................
2.1.2 Frame Pointer ..............................
2.1.3 Argument Pointer ........................
2.1.4 Processor Status Word ................
2.1.5 Stack Pointer ...............................
2.1.6 Process Control Block Pointer....
2.1. 7 Interrupt Stack Pointer ...............
2.1.8 Program Counter ................ .........
2.2 DATA HANDLING .....................
2.2.1 Data Types ..................................
2.2.2 Data in Memory ..........................
2.2.3 Memory Management.................
2.3 SIGNAL SAMPLING
POINTS .........................................
2.4 READ AND WRITE
OPERATIONS ..............................
2.4.1 Read Transaction
Using SRDY ................................
2.4.2 Read Transaction
Using DTACK .............................
2.4.3 Read Transaction With Wait
Cycle Using SRDY ......................
2.4.4 Read Transaction With Two
Wait Cycles Using DTACK ........
2.4.5 Write Transaction
Using SRDY................................
2.4.6 Write Transaction
Using DTACK .............................
2.4.7 Write Transaction With
Wait Cycle Using SRDY ............
2.4.8 Write Transaction With Wait
Cycle Using DTACK ...................
2.5 READ INTERLOCKED
OPERATION ................................
2.6 BLOCKFETCH OPERATION ....
2.6.1 Blockfetch Transaction
Using SRDY................................
2.6.2 Blockfetch Transaction
Using DTACK .............................
2.6.3 B10ckfetch Transaction Using
DTACK With Wait
Cycle On Second Word ..............

2-1
2-3
2-4
2-4
2-4
2-4
2-7
2-7
2-7
2-8
2-8
2-8
2-10
2·10
2-11
2-12
2-13
2-15
2-16
2-17
2·18
2-18
2-18
2-22
2-22
2-25
2-25
2-27
2-28

2.6.4 Blockfetch Transaction Using
SRDY With Wait
Cycles On Both Words ...............
2.7 BUS EXCEPTIONS .....................
2.7.1 Faults ...........................................
Fault With SRDY........................
Fault After DTACK ....................
2.7.2 Retry ............................................
2.7.3 Relinquish and Retry ..................
2.8 BLOCKFETCH SPECIAL
CASES ...........................................
2.8.1 Fault on First Word of
Blockfetch With Status
Code Other Than Prefetch .........
2.8.2 Fault on First Word
of Blockfetch With
Status of Prefetch .......................
2.8.3 Retry on First Word of
Blockfetch ...................................
2.8.4 Retry on Second Word of
Blockfetch ...................................
2.8.5 Relinquish and Retry of
Blockfetch ...................................
2.9 INTERRUPTS ..............................
2.9.1 Interrupt Acknowledge ................
2.9.2 Auto-vector Interrupt.. ................
2.9.3 Nonmaskable Interrupt.. .............
2.9.4 Quick Interrupt ...........................
2.10 BUS ARBITRATION .................
2.10.1 Bus Request During a
Bus Transaction ........ ..................
2.1 0.2 DMA Operation ........................
2.11 RESET .........................................
2.11.1 System Reset .............................
2.11.2 Internal Reset ............................
2.11.3 Reset Sequence ..........................
2.12 ABORTED MEMORY
ACCESSES..................................
2.12.1 Aborted Access on PC
Discontinuity With
Instruction Cache Hit.................
2.12.2 Alignment Fault Bus Activity ...
2.13 SINGLE-STEP OPERATION ...
2.14 COPROCESSOR
OPERATIONS ..............................

2-29
2-30
2-30
2-32
2·33
2-34
2-34
2-37
2-37
2·37
2-37
2-37
2·42
2·42
2-42
2-45
2-45
2-48
2-48
2-48
2-51
2-52
2-52
2·52
2-54
2-54
2-55
2·56
2-57
2·58

CONTENTS
2.14.1 Coprocessor Broadcast ..............
2.14.2 Coprocessor Operand Fetch ......
2.14.3 Coprocessor Status Fetch ..........
2.14.4 Coprocessor Data Write ............
2.15 EXCEPTIONAL
CONDITIONS ............................
2.16 TRACE MECHANISM .............
2.17 PIN ASSIGNMENTS ................

2-58
2-63
2-64
2-65
2-66
2-69
2-70

2.18 MICROPROCESSOR
OPERATING
REQUIREMENTS .....................
2.18.1 Electrical Requirements ............
2.18.2 Clocking Requirements .............
2.18.3 Thermal Requirements ..............
2.19 Supplementary Protocol
Diagrams ......................................

2-83
2-84
2-85
2-85
2-87

ARCHITECTURE & BUS OPERATION
Overview

2. WE 32100 MICROPROCESSOR OVERVIEW
The WE 32100 Microprocessor is the first 32-bit microprocessor with separate 32-bit
address and data buses. Using either physical or virtual addresses, the 32-bit address
bus can access over four billion (2 32) bytes of system memory or peripherals. Data is read
or written over the 32-bit bidirectional data bus in either byte (8-bit), halfword (16-bit), or
word (32-bit) lengths and is processed internally over 32-bit internal data paths.
The execution speed of the microprocessor is enhanced by an internal instruction queue and
an internal instruction cache that store prefetched instructions. Also, the microprocessor's
extensive use of pipelining allows overlapping of the execution of instructions while
tracking each one individually. Should a fault or interrupt occur during instruction
execution, the instruction that caused it can be easily determined and execution restarted.
This feature is essential for systems with demand-paged memory management.
Using a group of address and data strobes and interface and control signals, the
microprocessor controls information flow over the address and data buses. These signals
provide the timing required for transfer of data and facilitate interfacing to commercial
memories and peripherals. The microprocessor also accommodates wait-state generation to
allow handshaking with slow peripherals.
The WE 32100 Microprocessor consists of the four major sections shown on Figure 2-1.
These are the main controller, the fetch unit, the execute unit, and the bus interface
control. The main controller is responsible for acquiring and decoding instruction opcodes
and directing the action of the fetch and execute controllers as the specified instruction is
executed. The main controller also has the responsibility of responding to and directing the
handling of interrupts and exception conditions.
The fetch unit handles the instruction stream and performs memory-based operand
accesses. It consists of a fetch controller, an instruction cache, an instruction queue, an
immediate and displacement extractor, and an address arithmetic unit (AAU). The fetch
controller directs the action of the elements in the fetch unit. The instruction cache is a 64
by 32-bit on-chip cache which is used to increase the microprocessor's performance by
reducing external memory reads for instruction fetches. When an instruction fetch from
memory occurs, instruction data is placed in the cache and in the instruction queue. If
that instruction data is needed again, it is fetched from the cache rather than from external
memory, which improves performance. The instruction queue is an 8-byte first-in-first-out
queue that stores prefetched instructions. Instructions are taken from the queue for
execution, and the fetch controller fills it asynchronously with respect to instruction
execution. The immediate and displacement extractor provides address calculation data to
the AAU for its use in calculating 32-bit addresses.
The execute unit performs all arithmetic and logic operations, performs all shift and rotate
operations, and computes condition flags. It consists of:
• an execute controller that directs the actions of the elements in the execute unit

2-1

ARCHITECTURE & BUS OPERATION
Overview

• sixteen 32-bit registers that are user-accessible and include:

o nine general-purpose registers (rO-r8)
o seven dedicated registers (r9-r15)
• working registers that are used exclusively by the microprocessor and.are not useraccessible
• a 33-bit ALU that performs arithmetic operations on 32-bit data, with an extra bit that
is used whenever an operation requires a carry or borrow beyond 32 bits.
The bus interface control provides all the strobes and control signals necessary to
implement the interface with peripherals.
The WE 32100 Microprocessor pin assignments are summarized in 2.17 Pin Assignments.

,---

ADDRESS

~

I
1f

H

j

MAIN CONTROLLER

I

I

FROM INSTRUCTION
QUEUE

I
J

FETCH CONTROLLER

EXECUTE CONTROLLER

I

TO MAIN
CONTROLLER

32-8IT
REGISTERS

S4-WORD

DATA

~
~

INSTRUCTION
CACHE

BUS

H9-'>

B-BYTE
INSTRUCTION
QUEUE

rO
r1
r2
r3
r'
r5
r6
r7
rB
FP
AP
PSW
SP
PCBP
ISP
PC

r--

INTERFACE
CONTROL

1
IMMEDIATE

I--

G
DISPLACEMENT

EXTRACTOR

INTERFAC
G
CONTROL

rJ
\

E~
32

32

WORKING
REGISTERS

I-

r:r

~Iif}
LOGIC
UNIT

j

ADDRESS
ARITHMETIC
UNIT

32

-'---

32

ABUS

32
JO,.

32

32

32

CBUS

~

"------

1+----·

Figure 2-1.

2-2

- - - FETCH UNIT

- -

- - - --

'*'

WE 32100 Microprocessor Block Diagram

EXECUTE UNIT -------bj

ARCHITECTURE & BUS OPERATION
User Registers

2.1 USER REGISTERS
Figure 2-2 shows the programming model for the microprocessor's sixteen 32-bit registers
(rO-r15). This register set is designed for efficient support of high-level language
program execution. All of these registers, except for the program counter (r15) and the
processor status word (r11), may be accessed in any addressing mode. The processor
status word (r1l), process control block pointer (r13), and interrupt stack pointer (r14) are
privileged registers. These may be read at any time, but may be written only when the
microprocessor is in kernel mode (i.e., the operating system is in control). The other
registers may be read or written in any of the four execution levels.

r15

16J 15
SI7
PROGRAM COUNTER (PC)

r14

INTERRUPT STACK POINTER (ISP)*

r13

PROCESS CONTROL SLOCK POINTER (PCSP)*

r12

STACK POINTER (SP)

r1 1

PROCESSOR STATUS WORO (PSW)*

r10

ARGUMENT POINTER (AP)

r9

FRAME POINTER (FP)

31

rB

rO

31

0

I

I

;

;

"i

1

1
BI7

o

16 1 15

''--'''sy""T:-E--'
HALFWORD
WORD
* KERNEL LEVEL PRIVILEGED

Figure 2-2.

Programmer's Model for User Registers

2-3

ARCHITECTURE & BUS OPERATION
General-Purpose Registers

2.1.1 General-Purpose Registers (rO-rS)
The nine general-purpose registers may be used for high-speed accumulation, for
addressing, or for temporary data storage. The first three registers (rO-r2) are the
microprocessor's scratch registers. These three registers are used by the C compiler to
store temporary values during expression evaluation. They also pass and return specific
values during procedure calls. For example, rO should always be used to return the value
of a procedure. If a floating point double value is returned from a procedure, it is stored in
rO and rl. If a procedure returns a structure, then the pointer to that structure should be
returned to r2. In addition, registers rO-r2 are implicitly used by the data transfer
instructions MOVBLW (move block of words), STRCPY (string copy), and STREND
(string end) and also by the MVERNO (move version number), INTACK (interrupt
acknowledge), ENBVJMP (enable virtual pin and jump), DISVJMP (disable virtual pin
and jump), GATE (system-cal!), and CALLPS (call process) operating system
instructions.

2.1.2 Frame Pointer
The frame pointer (FP), r9, points to the beginning location in the stack of a function's
local variables. It is affected implicitly only by the save register (SAVE) and the restore
register (RESTORE) instructions.

2.1.3 Argument Pointer
The argument pointer (AP), rIO, points to the beginning location in the stack where a set
of arguments for a function has been pushed. The AP is affected implicitly only by the
procedure call (CALL) and return (RET) instructions.

2.1.4 Processor Status Word
The processor status word (PSW), r1l, contains status information about the
microprocessor and the current process. It is divided into 14 fields, as shown on Figure
2-3. Although the PSW is a privileged register, the microprocessor may alter some of its
fields at any execution level. Most instructions alter the N, Z, V, and C bits (condition
flags) in the PSW. In general, the PSW changes as a whole only when a process switch
occurs. The final values of the PSW bits are based on the result of the last calculation and
are latched into the PSW at the end of the instruction. The PSW may not be referenced
in some addressing modes.
Table 2-1 contains a description of each of the processor status word fields.

Figure 2-3.

2-4

Processor Status Word

ARCHITECTURE & BUS OPERATION
Processor Status Word

Table 2-1. Processor Status Word Fields
Bit(s)

Field

Contents

Description

0-1

ET

Exception
Type

This read-only field indicates the type of exception
generated during operations and is interpreted as:
Code
Description
Bit I Bit 0
0
0
On Reset Exception
0
1
On Process Exception
1
0
On Stack Exception
On Normal Exception
I
I
(See 2.12 Exceptional Conditions,)

2

TM

Trace
Mask

The read-only TM field enables masking of a trace trap.
This bit masks the trace enable (TE) bit for the duration
of one instruction to avoid a trace trap. The TM bit is
set (1) at the beginning of every instruction and cleared
(0) as part of every microsequence that performs a
context switch or a return from gate (RETG) or when
any fault or interrupt is detected and responded to.

3-6

ISC

This 4-bit code distinguishes between exceptions of the
same exception type. The ISC is a read-only field. (See
2.15 Exceptional Conditions,)

7-8

RI

Internal
State
Code
RegisterInitial
Context

9-10

PM

11-12 CM

These bits control the context switching strategy. The I
bit (bit 7) determines if a process executes from initial
or intermediate saved context. The R bit (bit 8, read
only) determines if the registers of a process should be
saved during a process switch. It also controls block
moves to change map information. (See Chapter 4,)
Previous
This field defines the previous execution level. The code
Execution is interpreted as:
Level
Description
Code
Bit 10 Bit 9
0
0
Kernel level
0
1
Executive level
1
Supervisor level
0
1
1
User level
Current
This field defines the current execution level. The code
Execution for bits II and 12 is interpreted in the same manner as
Level
that of bits 9 and 10 of the PM code, respectively.
Changes to the CM field via instructions with the PSW
as an explicit destination may affect the XMD pins
during a prefetch access. Therefore, only microsequence
instructions should be used to change the CM field state.

2-5

ARCHITECTURE & BUS OPERATION
Processor Status Word

Table 2-1. Processor Status Word Fields (Continued)
Bit(s)

2-6

Field

Contents

Description

13-16

IPL

Interrupt
Priority
Level

The IPL field represents the current interrupt priority
level. Fifteen levels of interrupts are available. An
interrupt, unless it is a nonmaskable interrupt, must have
a higher priority level than the current IPL in order to
be acknowledged. Therefore, level 0000 indicates that
any of the fifteen interrupt priority levels (0001 through
1111) can interrupt the microprocessor. Level 1111, the
highest interrupt priority level, indicates that no
interrupts (except a nonmaskable interrupt) can
interrupt the microprocessor.

17

TE

Trace
Enable

This bit enables the trace function. When TE is set (1),
it causes a trace trap to occur after execution of the next
instruction. Debugging and analysis software use this
facility for single-stepping a program. Changes to the
TE field via instructions with the PSW as an explicit
destination may cause unpredictable trace trap behavior
(i.e., the instruction that changed the TE field in the
PSW mayor may not cause a trace trap). Therefore,
only microsequence instructions should be used to change
the TE field state.

18-21

NZVC

Condition
Codes

The condition codes reflect the resulting status of the
most recent instruction execution that affects them.
These codes are tested using the conditional branch
instructions and indicate the following when set (1);
N - Negative (bit 21)
V - Overflow (bit 19)
(bit 20)
(bit 18)
Z - Zero
C - Carry

22

OE

Enable
Overflow
Trap

This bit enables overflow traps when set (1). It is
cleared (0) whenever an overflow trap is detected and
handled.

23

CD

Cache
Disable

This bit enables and disables the instruction cache.
When the CD bit is cleared (0), the cache is used to
store and read text. When the CD bit is set (l), the
cache is not used. The instruction cache should only be
disabled when its use could cause problems, e.g., when
self-modifying code is executing. Changes to the CD
field via instructions with the PSW as an explicit
destination may corrupt the contents of the instruction
cache. Therefore, only microsequence instructions
should be used to change the CD field state.

ARCHITECTURE & BUS OPERATION
Interrupt Stack Pointer

Table 2-1. Processor Status Word Fields (Continued)
Bit(s)

Field

Contents

Description

24

QIE

QuickInterrupt
Enable

The QIE enables and disables the quick-interrupt
facility. If QIE is set ([), an interrupt is handled via the
quick-interrupt sequence. If QIE is cleared (0), the
interrupt causes a process switch (full-interrupt
sequence).

25

CFD

Cache
Flush
Disable

When set (I), bit 25 disables instruction cache flushing
(emptying of the cache's contents) when a new process is
loaded via the XSWITCH_TWO microsequence (see
4.8.4 Microsequences). When cleared (0), the contents
of the cache are flushed when a new process is loaded
via the XSWITCH TWO microsequence.

Unused

These bits are not used and must always be cleared (0).

26-31

2.1.5 Stack Pointer
The stack pointer (SP), rl2, contains the current 32-bit address of the top of the execution
stack; i.e., the memory address of the next item to be stored on (pushed on) the stack or
the last item retrieved (popped) from the stack. The stack pointer and the related
instructions implement a LIFO Oast-in-first-out) queue that supports efficient subroutine
linkage and local variable storage.

2.1.6 Process Control Block Pointer
The process control block pointer (peBP), rl3, points to the starting address of the process
control block for the current process. The process control block is a data structure in
external memory that contains the hardware context of a process when the process is not
running. This context consists of the initial and current contents of the processor status
word, program counter, and stack pointer; the last contents of registers rO through rlO;
boundaries for an execution stack; and block move specifications (and possibly memory
specifications) for the process. The PCBP may only be written when the microprocessor is
in kernel mode.

2.1.7 Interrupt Stack Pointer
The interrupt stack pointer (ISP), rl4, contains the 32-bit memory address of the top of
the interrupt stack. This stack is used when an interrupt request is received and also by
the call process (CALLPS) and return to process (RETPS) instructions. The ISP may
only be written when in kernel mode.

2-7

ARCHITECTURE & BUS OPERATION
Program Counter

2.1.8 Program Counter
The program counter (PC), r15, contains the 32-bit memory address of the instruction
being executed or, upon completion, the starting address of the next instruction to be
executed. The PC may not be referenced in some addressing modes and is usually
implicitly referenced by all program control instructions and all function calls and returns.

2.2 DATA HANDLING
All operations within the microprocessor are performed on 32-bit quantities, but data may
be read or written as a byte, halfword, or word. Bits are numbered from right to left,
starting at 0, and are right-adjusted on the address/data bus. The microprocessor
automatically extends a byte or halfword to 32 bits before performing an operation. Zeros
fill the high-order bits for unsigned operations, while the sign bit (bit 7 for bytes, bit 15 for
halfwords) fills the high-order bits for signed operations. See Chapter 3 for a detailed
description of data handling.

2.2.1 Data Types
The WE 32100 Microprocessor supports the following integer data types:
• byte

A byte is an 8-bit quantity that may appear at any address. Bits are
numbered from right to left starting with 0, the least significant bit (LSB),
and ending with 7, the most significant bit (MSB). (See Figure 2-4.)

• halfword

A halfword is a 16-bit quantity that may appear at any address that is
divisible by 2. Bits are numbered from right to left starting with 0, the
LSB, and ending with 15, the MSB.

• word

A word is a 32-bit quantity. A word may appear at any address that is
divisible by 4. Bits are numbered right to left starting with 0, the LSB,
and ending with 31, the MSB.

A bit field data type is also supported by the WE 32100 Microprocessor. A bit field is a
sequence of 1 to 32 bits contained in a base word. The field is specified by the address of
its base word, a bit offset, and a width. The bit offset ranges from 0 to 31 and identifies
the starting bit of the field. The offset is numbered from the LSB of the base word and
corresponds to the number of the bit in the word. That bit becomes bit 0, the LSB, of the
field. The width ranges from 0 to 31 and specifies the size of the field. (Width plus one is
the number of bits in the field.) The width is numbered from right to left in the field and
corresponds to the bit number of the field's MSB. Fields do not extend across word
boundaries and will wrap around from the MSB to LSB when the word boundary is
reached. Figure 2-5 illustrates a bit field located at address a, with an offset of 6, and a
width of 9. (Notice that the field contains 10 bits, one bit more than the width.)

2-8

ARCHITECTURE & BUS OPERATION
Data Types

7

BITS

a

Fi

MSB

LSB

A. BYTE OAT A
BITS

15

a

81 7

:

I

t
MSB

I

t
LSB

B. HALFWORD DATA
BITS

31

24: 23

16: 15

a

8: 7

l

I

t
MSB

t

LSB

C. WORD DATA

Bit Order of Data

Figure 2-4.

LSB

MSB

t

31

16 15

24: 23

x : a 1 1 1 1 a 1 1!

~

ta

8 7
D 1 X0

0

0

xl

~ WIDTH~
I OFFSET

I
BASE WORD AT ADDRESS a

MSB

t
9

LEGEND:
BASEWORD ADDRESS = a
OFFSET = 6
WIDTH = 9

Figure 2-5.

LSB

ta

101 1 1 101 1011

Bit Field Data Type

2-9

ARCHITECTURE & BUS OPERATION
Data in Memory

2.2.2 Data in Memory
Memory locations consist of a series of 8-bit (byte) locations for storing data. Halfwords
occupy two consecutive memory locations and words occupy four consecutive memory
locations. Boundary restrictions apply to the starting location of halfwords and words.
Halfwords may only appear at addresses divisible by 2, and words may only appear at
addresses divisible by 4. The microprocessor generates a fault if these boundaries are
violated.
During memory reads the memory system must provide a word of data. The memory
system must ignore the two lowest address bits (ADDROO and ADDROl) and provide the
word data beginning at this resulting word address.
Memory writes require that the memory system be set up in byte format, i.e., each byte
must be writable independent of all other bytes. During memory writes, only the byte or
bytes the CPU wants to write are to be changed. The remaining byte or bytes of the same
word, if any, must not be altered. The CPU informs the memory system which byte(s)
should be written based on the contents of the data size bits (DSIZEO and DSIZEl) and
the lower two address bits (ADDROO and ADDROI). Table 2-2 indicates which byte(s)
should be written based on the following byte addressing.
Data
Byte
Increasing Addresses
Table 2-2.
DSIZEI DSIZEO

Memory Write Summary

ADDROI ADDROO

I

0
0

(Word)
(Halfword)

I

I

(Byte)

0

0
0
I
0
0
I
I

•

0
0
0
0
I
0
I

Byte 0
Written
Written
Unchanged
Written
Unchanged
Unchanged
Unchanged

Memory Byte

CLK23

CLK34

---,

I

V l\-f

~

~ ~ '3'

0

1'---'

SASOSAS3
DSIZEODSIZEI
ADDROOADDR31

AS

os

V l\-V I\-r
~

x ~
~ '---'

~

~

READ INTERLOCKED

- ,<<<
- ,( «

-

VALID

)

_\ «

X

-

1.\ \\

'I I /
VALID

XXX :XXX ~

XXX :J\M ~XXX ::XXX :XXX :XXX: (XXX (XM (X

DRDY

ID (XM ::XM ~XXX :XM:

'I I I,

)

01:1:1

16t"'i

rJl

o

~

'11/

1:1:1

g

'I II

Z
VALID

X XXX W\X ()Q

-'

XXX XIX \;\IX

X ~XXX ~XXX W\X W\X :xf.x XXX KXXX KXXX
XKXXX, oo:x ::iJ:L ~ ~
h

t\\\
t\\\

~

rI I I

Notes:
I.

Number of cycles between the read transaction and write transaction is four for swap word interlocked (SW APWI) and
six for swap halfword interlocked (SW APHO and swap byte interlocked (SWAPBO instructions.

2.

Zero wait cycles.

Figure 2-15.

g("'l
~...,

Q-C:
NEXT VALID

3 - STATE IF VIRTUAL

ill

h

'II I

- .\\ \

KxM t(

:::!.t"'i

=c:

VALID

1.\ \ \

SRDY

;-:=i

a~

,\\\

XXX XIX 0CO( 0:

XXX W\X 0A

;'=

o· t:I:I

:« <

3 - STATE IF VIRTUAL

'11/

-

Lr--n"' 1'---' ~
'---'
10

t"

1

1.\ \ \

R/W

I~

~ ~ r-;-'

READ INTERLOCKED

-

DTACK

V I\-~ ~ J l\-V I\-

I-.

OATAOODATA31

CYCLEl

~

IEQ-("'l
1:1:1

Read Interlocked Transaction (Using DTACK)

ARCHITECTURE & BUS OPERATION
Blockfetch Transaction Using SRDY

2.6 BLOCK FETCH OPERATION
The CPU can fetch two words of instruction code in one bus transaction via a blockfetch
operation. The CPU generates one address, and the memory provides two words of
instruction code. This reduces the number of cycles that it takes to fetch two words. The
CPU starts the transaction with the DSIZE of double word, which indicates that it is ready
to perform a blockfetch.
If the memory is designed to handle blockfetch, it will respond with the blockfetch
(BLKFTCH) signal and an acknowledge signal, either SROY or OTACK.

2.6.1 Blockfetch Transaction Using SRDY
After the memory issues BLKFTCH and SROY, the CPU latches the data being sourced by
the memory during clock state four, removes OS, and keeps AS in the active state. One
cycle later the CPU reissues OS and is ready to latch the second word.
The memory drives the data bus with the second word and a SROY. The CPU samples the
SROY at the end of clock state seven, then latches the data during clock state eight and
terminates the transaction. This operation is shown on Figure 2-16.
AS stays low for both words fetched. OS goes inactive for one cycle in between the first
and second words. DSIZE changes from double word to word at clock state six. R/w is
held in the read mode for the entire transaction. Only one CYCLEr is issued for this
transaction. Two OROY's are issued, one for each word. The BLKFTCH pin is sampled
only with the first SROY. It is not used during the second word. The SAS code for the
first word can be "instruction fetch," "instruction fetch after PC discontinuity," or
"prefetch." SAS for the second word is always "prefetch." If the memory does not issue a
BLKFTCH with the acknowledgement on the first word then the CPU will latch the data
and terminate the transaction by removing both AS and OS. It will then precede to start
up a second read with SAS of "prefetch" and issue a new address.
For a blockfetch transaction, the CPU issues only one address. If it is in virtual mode the
CPU 3-states the address during clock state two which allows the MMU to drive the
physical address for fetching both words. Also note that the CPU is fetching the two
words from a double word address block. It will ask for either the even or odd address
first, as indicated by the value on the address bus. For the second word it expects the
memory to provide the data corresponding to the address location with ADDR02
complemented. This is the other corresponding word from the double word block.
For example, assuming physical addressing, the CPU drives ADDR with 0003COOO.
Memory provides data for the first word corresponding to location 0003COOO. Memory
provides data for the second word corresponding to location 0003C004.
As another example of physical mode, consider the CPU driving ADDR with 00078004.
Memory provides data for the first word corresponding to location 00078004. Memory
provides data for the second word corresponding to location 0007800.

2-25

ARCHITECTURE & BUS OPERATION
Blockfetch Transaction Using SRDY

-4

I~l«ls- 2ND WORD FETCH

--;.j

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r--;-'

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Note: Zero wait cycles.
Figure 2-17.

Blockretch Transaction (Using DTACK)

2-27

ARCHITECTURE & BUS OPERATION
Blockretch Transaction Using DTACK With Wait Cycle on Second Word

2.6.3 Blockfetch Transaction Using

DTACK With Wait Cycle on Second Word

In this case (see Figure 2-18), during the fetch of the second word there was no DTACK
during clock state six nor SRDY during clock state seven. Therefore, the CPU inserted a
wait cycle. It sampled DTACK during the first clock state "W," then latched the data and
terminated the transaction.

CLK23

CLK34

--

,

~

J
I~

Lr ~Lr ~Lr ~Lr ~ J

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~

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DATAOODATA31

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INST. PREFETCH

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WORD 2

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Note: Wait cycle on both words.

Figure 2-19.

Blockfetch Transaction 

2-31

ARCHITECTURE & BUS OPERATION
Fault With SRDY

FAULT With Siij)y
The CPU can sample FAULT synchronously if it has a SRDY with it. Figure 2-21 shows
both SRDY and FAULT being sampled during the last clock state "W." The CPU then
terminates the transaction and does not issue a DRDY. For reads and writes, the CPU
samples the SRDY and FAULT in the same way.

CLK23

CLK34

~

J l"-V I"-Lrl\-V ~V
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:~

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I']'

ADDROOADDR31

r----\
w

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Figure 2-23.

Retry of Transaction (Read Transaction is Shown)

ao

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CLK34

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Note: If RRREQ is asserted instead of RETRY, the CPU 3-states the bus at A and asserts RRRACK one clock cycle later at B.

Figure 2-27.

,\\\'

Retry on First Word of BIockfetch Transaction

@
CLK23

CLK34

- Lr l\-V ~V ~V I\- Lr l\-V ~V I\- Lr l\-V ~ Lr f\- ~ ~ ~ I~ ~ 1'7' ~ ~ I~ 1,-- ~ ITX' rr---. 1,-- ~ ~
Ir--

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BLKFTCH

j\--

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r; / /

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r; / /

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DDRESS

KXXX (XXX
KXXX (XXX KXXX KXXX (XXX KXXX KXXX (XXX KXXX KXXX (XXX (XXX (XXX (XXX

KXXX ~XXX (X\

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Notes:
I. On RRREQ, the following pins are 3-stated between points A and B. ADDROO- ADDR31, DATAOO-DATA32,
AS, CYCLEI, DRDY, DS, DSIZEO-DSIZE1, R/W, SASO-SAS3.
2. If RRREQ or RETRY is asserted during the first word, then the entire blockfetch access is retried.

Figure 2-28.

Retry on Second Word of Blockfetcb

Q

~

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Q

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g.Z

ARCHITECTURE & BUS OPERATION
Relinquish & Retry on Blockfetch

2.8.5 Relinquish and Retry on Blockfetch
Figures 2-27 and 2-28 can be used to illustrate the RRREQ bus exception for the first and
second word of a blockfetch.
The timing and bus transaction for Figure 2-27 will look the same if the bus exception is
RRREQ rather than RETRY. However, the CPU will release the bus before doing the
retried transaction. Additionally, the CPU will 3-state the bus at the end of the second
clock state X (indicated by A on the diagram). One cycle later it will issue a relinquish
and retry request acknowledge (RRRACK) to tell the requesting device that it can now use
the bus. When RRREQ is removed, the CPU will continue with the retried transaction
starting at point B.
The same explanation applies for a RRREQ on the second word of a blockfetch (Figure
2-28). As above, the CPU will 3-state the bus at point A and issue a RRRACK. Once the
RRREQ is removed, the CPU will continue with the next bus transaction starting at point
B and would not retry the blockfetch.

2.9 INTERRUPTS
The microprocessor accepts fifteen levels of interrupts. An interrupt request is made to the
microprocessor by placing an interrupt request value on the interrupt priority level pins
(IPLO-IPL3) or by requesting a nonmaskable interrupt by asserting NMINT. Pending
interrupts are not acknowledged until the currently executing instructions are completed.
The exceptions to this are multiply, divide, modulo, move block word, string copy, and
string end instructions which abort upon a pending interrupt.
The pending interrupt value input on IPLO-IPL3 is internally inverted and compared to
the value contained in the interrupt priority level (IpL) field of the processor status word
(PSW). In order for the pending interrupt to be acknowledged, its inverted value must be
greater than the IPL field value. Pending interrupts whose inverted values are equal to or
less than the IPL field value are ignored. However, if the pending interrupt is
nonmaskable, it will always interrupt the microprocessor regardless of the IPL field value.
The microprocessor also provides autovector, nonmaskable, and quick-interrupt facilities.
The following describes these facilities.

2.9.1 Interrupt Acknowledge
The microprocessor acknowledges an interrupt by transmitting the inverted interrupt value
on bits 2 through 5 of the address bus. In addition, the value placed on the interrupt
option (INTOPT) pin is inverted and transmitted on bit 6 of the address bus. (The
INTOPT input has no effect on the microprocessor; however, it could be used to indicate,
for example, whether the interrupt was hardware- or software-generated.) The
microprocessor then fetches the interrupt vector number from the interrupting device on
bits 0 through 7 of the data bus and begins execution of the interrupt handling routine.
The interrupt acknowledge transaction is illustrated by Figure 2-29 which depicts the case
where a value placed on the IPLO-IPL3 inputs causes an interrupt. In this case, :,:th:::-e~=
interrupt acknowledge is issued in response to the application of the IPL pins and INTOPT

2-42

ARCHITECTURE & BUS OPERATION
Interrupt Acknowledge

pin with no AVEC and NMINT active. During the interrupt acknowledge transaction, the
CPU reads in an 8-bit offset provided by the interrupting device and used by the CPU as
an offset to a table. The SAS code is "interrupt acknowledge." The DSIZE is a byte. The
address corresponding to the interrupt acknowledge is indicated at the bottom of the figure.
The interrupting device drives the data bus with the 8-bit offset and a memory
acknowledge; in this case a DTACK. The bus exceptions are accepted during this bus
transaction. The IPL input values should be removed once the corresponding interrupt
acknowledge has occurred.

CLK23

r-

J

i--""I

CLK:34

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Ir---""'

r-;--'

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~

rL J rL J
2

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IPLO-tPL3

SAS3

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DSIZED·
DSIZEI

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SASO.

ADDROD.
ADDR31

INTERRUPT ACKNOWLEDGE

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Note: During the interrupt acknowledge the address bus (ADDROO-ADDR31)
contains the following data.

Figure 2-29.

Interrupt Acknowledge

2-43

ARCHITECTURE & BUS OPERATION
Interrupt Acknowledge

Table 2-4 summarizes how the interrupt priority levels are to be interpreted and shows the
corresponding acknowledge for each level.

Table 2-4.

Interrupt Level Code Assignments

Interrupt
Request
Input

Interrupt
Option
Input

Interrupt
Acknowledge
Output

IPLO-IPL3
Bits:

INTOPT

ADDR02-ADDR06
Bits:

3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
1

06
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
x
x

05
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

x
x

x signifies no value placed on address bus.

2-44

04
1
1
1
1
1
1
1
1
0

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
x
x

03
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1
0
0
x
x

Priority
Level

02
1
1
0
0
1
1
0
0
1
1
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
x

Highest
Priority
2nd
3rd
4th
5th
6th
7th
8th
9th
10th
11th
12th
13th
14th
Lowest
Priority
No Interrupt
Pending

ARCHITECTURE & BUS OPERATION
Nonmaskable Interrupt

2.9.2 Auto-vector Interrupt
If the auto-vector (A VEe) input is active during an interrupt request, the microprocessor
will not fetch a vector number from the interrupting device. Instead, the microprocessor
provides the interrupt vector by treating the inverted INTOPT input, concatenated with the
interrupt priority level input (IPLO-IPL3), as a vector number. The auto-vector facility
reduces hardware costs in smaller, less complex systems because the interrupt vector is
supplied by the microprocessor instead of by external hardware.

Refer to Figure 2-30 for an illustration of the auto-vector interrupt acknowledge
transaction. In this transaction, an auto-vector acknowledge is issued in response to the
application of the IPL pins and INTOPT pin with AVEe active and no NMINT. Since the
CPU does not need to read in an external value, it does an auto-vector interrupt
acknowledge without looking for a memory acknowledge or a bus exception. The
transaction goes through the clock states without inserting wait cycles. This transaction is
used to tell the interrupting device that it should remove the IPL and AVEe input values.
No DRDY is issued because there is no latching of data.

2.9.3 Nonmaskable Interrupt
The nonmaskable interrupt facility is provided to satisfy reliability and recover ability
requirements of various systems. As previously mentioned, a nonmaskable interrupt can
interrupt the microprocessor regardless of the current priority level in the IPL field. A
nonmaskable interrupt occurs if the nonmaskable interrupt input (NMINT) is asserted.
The interrupt is then treated as an autovector interrupt with vector number O. During the
interrupt acknowledge cycle of a nonmaskable interrupt, address bus bits ADDROOADDR31 contain zeros. This distinguishes a nonmaskable interrupt from all other
interrupts.
Figure 2-31 illustrates the nonmaskable interrupt acknowledge transaction. Here, a
nonmaskable interrupt acknowledge is issued in response to the application of the NMINT
input. For a nonmaskable interrupt, the CPU uses an internal offset corresponding to an
IPL of zero. Since the CPU does not need to read in data, it performs the transaction
without looking for a memory acknowledge or a bus exception. The transaction goes
through the clock states without inserting wait cycles. Again, the interrupting device
should release NMINT when it sees the acknowledge. The SAS code is "auto-vector
acknowledge," but the interrupt vector is O. ADDROO can be used to determine the
difference between the AVEe and NMINT interrupts. It is a 1 for auto-vector and a 0 for
nonmaskable interrupt.

2-45

ARCHITECTURE & BUS OPERATION
Nonmaskable Interrupt

CLK23

l-

~f

f

v----;

~

CLK34

'----J

~ Lr ~ f

~

Lr ~

~ ~ ~ ~ ~ '5' ~ ~ ~

IPLO-IPL3

~

SASOSAS3

-t---ri

DSIZEODSIZEI

-t---ri

"
~

«<

ADDROOADDR31 - I - - - r l

AUTO-VECTOR INTERRUPT ACKNOWLEDGE

1< «K

II

«<
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BYTE

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3-ST ATE IF VIRTUAL

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R/W

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Note: During the interrupt acknowledge the address bus (ADDROO-ADDR31) contains the following data.

Figure 2-30.

2-46

Auto-vector Interrupt Acknowledge

ARCHITECTURE & BUS OPERATION
Nonmaskable Interrupt

CLK23

~

0-V "-V 0- f 0-V 0-

f

II"---;

CLK34

'""'

SASOSAS3 ---1_-+~

t-

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0

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r

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Note: The address bus ADDROO-ADDR31 contains all zeroes during the acknowledge of a
nonmaskable interrupt.

Figure 2-31.

Nonmaskable Interrupt Acknowledge

2-47

ARCHITECTURE & BUS OPERATION
Quick Interrupt

2.9.4 Quick Interrupt
The quick-interrupt facility enchances the performance of systems that do not require the
functionality of the "full interrupt." Its handling routine (a microsequence that stores the
PSW and PC) requires less time than that of a "full interrupt." All interrupts are serviced
via the quick-interrupt facility if the quick-interrupt enable (QIE) bit in the PSW is set
(1). Table 2-5 summarizes how the microprocessor handles the various interrupt requests.
See Chapter 4 for more information on full and quick interrupts.

2.10 BUS ARBITRATION
The microprocessor's bus may be requested in two ways. External devices may request the
bus by asserting the relinquish and retry request input (RRREQ), as explained previously,
or by asserting the bus request input (BUSREQ).
The relinquish and retry request has priority over a bus request. The microprocessor will
only acknowledge a relinquish and retry request during bus transactions; however, it will
ignore the request during the write portion of a read interlocked transaction.
A bus request during a CPU bus transaction is not acknowledged until the end of a bus
transaction or until the end of the write portion of a read interlocked transaction.

2.10.1 Bus Request During a Bus Transaction
BUSRQ is sampled independently of bus transactions at the beginning of every clock cycle.
On Figure 2-32 it is sampled for the first time at the beginning of clock state two. After
sampling BUSRQ, the CPU continues the current bus transaction. After the transaction is
completed, the CPU 3-states the address and data buses and some control signals just after
the last clock state X. A cycle later it issues the bus request acknowledge, BRACK. At
this point the device requesting the bus can perform its operations. When finished, the
device drops the BUSRQ. After seeing this drop, the CPU removes BRACK and takes back
the bus. Note that if the bus request occurred during an active retry request or relinquish
and retry request it would not be acknowledged until after the current transaction had been
retried. Refer to 2.19 SUPPLEMENTARY PROTOCOL DIAGRAMS for an example.

For a bus request that does not occur during a bus transaction, the CPU will 3-state the
bus a cycle after sampling BUSRQ and issue BRACK a cycle after that.

2-48

CLK23

CLK34

-

,

' f~ ' f~ f
i~

~

SASOSAS3
DSIZEODSIZEI

-

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DATAOODATA31

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N

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~

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Figure 2-32,

Bus Request During a Transaction

~~

'" ....
::-,0
§z

ARCHITECTURE & BUS OPERATION
Bus Request During a Bus Transaction

Table 2-5.
Interrupt
Priority
Less than
PSW
IPL field
priority
Equal to
PSW
IPL field
priority
Greater
than PSW
IPL field
priority
Greater
than PSW
IPL field
priority
Any level
compared
to PSW
IPL field
priority
Greater
than PSW
IPL field
priority
Greater
than PSW
IPL field
priority
Any level
compared
to PSW
IPL field
priority

2-50

Interrupt
Acknowledge
No

Interrupt Acknowledge Summary

--- - NMINT
x

1

x

Result
Interrupt is not acknowledged.

No

x

1

x

Interrupt is not acknowledged.

Yes

1

1

0

Yes

0

1

0

Yes

x

0

0

Yes

1

1

1

Yes

0

1

1

Yes

x

0

1

Interrupt is acknowledged and
serviced via the full-interrupt
sequence. Microprocessor fetches
vector number from interrupting
device.
Interrupt is acknowledged and
serviced via the full-interrupt
sequence. Microprocessor supplies
the vector number.
Interrupt is acknowledged and
serviced via the full-interrupt
sequence. It is treated as an au tovector at vector number O. The
address bus contains all zeros during
the acknowledge.
Interrupt is acknowledged and
serviced via quick-interrupt sequence.
Microprocessor fetches vector number
from interrupting device.
Interrupt is acknowledged and
serviced via quick-interrupt sequence.
Microprocessor supplies the vector
number.
Interrupt is acknowledged and
serviced via quick-interrupt sequence.
It is treated as an auto-vector
interrupt at vector number O. The
address bus contains all zeros during
the acknowledge.

AVEC

QIE

ARCHITECTURE & BUS OPERATION
DMA Operation

2.10.2 DMA Operation

The microprocessor provides the support for direct memory access (DMA) and shares bus
control responsibilities with the system DMA controller. To initiate a DMA operation, the
controller requests the microprocessor bus by asserting (BUSRQ). Recall that this request
is not acknowledged until the end of a bus transaction or until the end of the write portion
of a read interlocked transaction. However, if the CPU is not using the bus, the request is
acknowledged immediately. Once the microprocessor recognizes the request, it 3-states the
following signals:

ABORT
ADDROO-ADDR31
AS
CYCLEI

DATAOO-DATA31
DRDY
DS
DSIZEO-DSIZEI

R/w
SASO-SAS3
VAD
XMDO-XMDI

After the microprocessor has 3-stated the above signals, it acknowledges the DMA request
by asserting the bus request acknowledge output (BRACK). Table 2-6 summarizes the
output signal states once the DMA has been acknowledged.
Terminating a DMA operation reverses the start of DMA. The DMA controller removes
the request by negating BUSRQ (drives the input high). The microprocessor then negates
the acknowledge (BRACK), and, finally, the 3-stated signals are returned to the
microprocessor's control. The next operation may then begin.

Table 2-6.

Output Signal States After DMA Request is Acknowledged

Output Signal

Signal State

Output Signal

Signal State

ABORT

Z'

DSIZEO-DSIZEI

Z

ADDROO-ADDR31

Z

R/W

Z'

AS

Z'

RESET

Logic I

RRRACK

Logic I

BRACK

Logic 0

CYCLE I

Z'

SASO-SAS3

Z'

DATAOO-DATA31

Z

VAD

Z

DRDY

Z'

XMDO-XMDI

Z

DS

Z'

Where:
Z High impedance state.
Z' High impedance. Held at logic I with external passive hold resistor.

2-51

ARCHITECTURE & BUS OPERATION
Reset

2.11 RESET
The microprocessor handles two types of reset requests: system and internal. A reset has
the highest priority and will preempt any ongoing microprocessor operation.

2.11.1 System Reset
A system reset is initiated when the system drives the reset request input (RESETR) low.
This double-latched input must be active on three consecutive latchings before being
recognized. This ensures noise immunity. After recognizing the reset request, the
microprocessor sends a reset acknowledge to the system by asserting RESET. All
microprocessor outputs are then driven to a temporary state that prevents control signal
and bus conflicts while the system responds to the reset acknowledge.
Once the system has responded to the acknowledge, it negates RESETR. The
microprocessor continues to hold RESET active for 128 clock cycles after ~R=E==SE=T=R::- has
been negated, allowing the external system to go through its own initialization sequence.
At the end of this period the microprocessor negates RESET and begins executing the
internal reset sequence. Table 2-6 indicates the states of the microprocessor's output pins
once RESET is negated. During this sequence, the microprocessor performs the following
register initialization to restart the operation.
• The microprocessor changes to physical addressing mode.
• The microprocessor fetches a word at location 80 hexadecimal and stores it in the
process control block pointer (PCBP). This word is the beginning address of the reset
process control block, PCB.
• The microprocessor fetches a word at the PCB address and stores it in the processor
status word.
• The microprocessor fetches a word at the location four bytes from the PCB address and
stores it in the program counter (PC). This word is the PC value for initial execution.
• The microprocessor fetches a word at the location eight bytes from the initial PCB
address and stores it in the stack pointer.
• If the PSW I bit is set (1), the microprocessor clears the bit (0), fetches a word at the
location twelve bytes from the initial PCBP, and stores it as the new PCBP.
• The microprocessor begins execution at the address specified by the PC.

2.11.2 Internal Reset
An internal reset sequence is like a system reset sequence except there is no external reset
request signal. The request is generated internally. Note that the RESET line will still go
active for 128 clock cycles after RESETR is released.

2-52

ARCHITECTURE & BUS OPERATION
Internal Reset

Table 2-7.

Output States on Reset
Signal State

Output
Signal
ABORT
ADDROO-ADDR31
AS
BRACK
BUSRQ
CYCLEI
DATAOO-DATA31
DROY
OS
DSIZEO, DSIZEI
IQSO, IQSl
R/W
RRRACK
SASO-SAS3
SOl
VAO
XMDO, XMDI

CPU· is Not
Bus Arbiter

CPU· is
Bus Arbiter
Logic 1
High Impedance

High Impedance
High Impedance
High Impedance

Logic 1
Logic 1

-

-

Logic 1
High Impedance
High Impedance

Logic 1
High Impedance
Logic 1

High Impedance

Logic 1
Logic 0
Logic 1

High Impedance
High Impedance

Logic 1
High Impedance, (a)

Logic 1
High Impedance
High Impedance, (a)

Logic 1
(b)

High Impedance
Logic 1
High Impedance

(c)

High Impedance

Logic 1

·CPU is the WE 32100 Microprocessor.
Notes:
a
Open drain output not actively driven under
this condition.
b Not guaranteed to be logic 1 (i.e., physical
address) until approximately 38 clock
cycles after RESET is negated.
Not guaranteed to be in kernel mode until
c
approximately 18 clock cycles after RESET is
negated.

2-53

ARCHITECTURE & BUS OPERATION
Reset Sequence

2" CLOCK CYCLES

<3

128 CLOCK CYCLES

INTERNAL RESET SEQUENCE
BEGINS

Note:

RESETR must be asserted for at least two clock cycles to be recognized.
RESET is negated 128 clock cycles after negation of RESETR.

Figure 2-33.

Reset Sequence

2.11.3 Reset Sequence
The reset sequence is depicted on Figure 2-33. As previously stated, after RESETR is
sampled for at least two consecutive clock cycles, the CPU issues the reset acknowledge
(RESET). While RESETR is active, the CPU holds RESET active. Once RESETR is
removed by the requesting device, the CPU counts 128 clock cycles and then removes
RESET. At this point the CPU enters the internal reset sequence (see Chapter 4).
Note that if the CPU receives a fault during certain high-level bus transactions it can enter
a reset exception (see 2.15 EXCEPTIONAL CONDITIONS). This exception goes through
a simulated system reset and includes issuing RESET for 128 clock cycles.

2.12 ABORTED MEMORY ACCESSES
There are two events that cause the CPU to abort a memory access; when the CPU has a
program counter (PC) discontinuity with an instruction cache hit, and when an alignment
fault occurs. These two events are illustrated next.

2-54

ARCHITECTURE & BUS OPERATION
Aborted Access on PC Discontinuity With Instruction Cache Hit

2.12.1 Aborted Access on PC Discontinuity With Instruction Cache Hit
Figure 2-34 depicts the protocol associated with this event. When the CPU does a PC
discontinuity it starts to fetch the next instruction word from memory. The SAS code is
"instruction fetch after PC discontinuity." If there is a hit in the cache for this instruction
fetch, the CPU cancels the external instruction fetch by terminating the transaction. The
CPU ignores memory acknowledges and bus exceptions during this transaction. To
indicate that it is terminating the transaction, the CPU issues ABORT for two cycles,
starting with clock state four. No DRDY is issued and the CPU ignores the data bus. The
CPU uses the instruction word that it obtained from the instruction cache.

CLK23

CLK34

SASOSAS3
DSIZEODSIZEI
ADDROOADDR31

-

J ~ J ~ J ~V ~

~

-

0

'----J

C:=;~RUCTION
-

,< «

-

~

I~

~

~

NEXT VALID

FETCH ON PC DISCONTINUITY
DOUBLE WORD

VALID

)

3 - STATE IF VIRTUAL

'/1/

1.\\ \
1.\\ \

-

I~

,< <<

,< «

-

R/W

~ ~~

mzv

'/ / /

lli

'iLL

Note: BLKFTCH, DATAOO-DATA3J, DTACK, FAULT, RETRY, RRREQ, and SRDY
are ignored.

Figure 2-34.

Aborted Access on I-Cache Hit With PC Discontinuity

2-55

ARCHITECTURE & BUS OPERATION
Alignment Fault Bus Activity

2.12.2 Alignment Fault Bus Activity
If the CPU detects an alignment fault on an intended CPU-generated bus transaction, it
will terminate the transaction and proceed to the fault handler. The write transaction on
Figure 2-35 started with the address bus, as well as the DSIZE, SAS, R/w, and CYCLE I
being driven by the CPU. The CPU detects the alignment fault and does not issue AS and
DS. It issues ABORT, starting at clock state three, to indicate that it is terminating the
transaction. The CPU ignores memory acknowledges and bus t;xceptions during this time
(see note Figure 2-35). DRDY is not issued.

CLK23

CLK34

- J ~ Lr ~ Lr ~ Lr ~--'"

-

~~~~~

SASOSAS3
DSIZEODSIZEI
ADDROOADDR31

«<
«<

VALID

~

Ir---'I
X

«<

WRITE

-

.'5'

)

3 - STATE IF VIRTUAL

711

,\\ \

R/w

- ,\\ \'
- ,\\ \'

'Ill

Notes:
1. DATAOO-DATA31, DTACK, FAULT, RETRY, RRREQ, and
SRDY are ignored.
2. Protocol is the same for a read transaction.

Figure 2-35.

2-56

Alignment Fault Bus Activity (Write Transaction Is Shown)

ARCHITECTURE & BUS OPERATION
Single-Step Operation

2.13 SINGLE-STEP OPERATION
Hardware single-step can be performed by use of the stop input (STOP). This input halts
the execution of instructions beyond the ones already started by the microprocessor.
Because of the pipelined architecture, the CPU may execute, at most, one more instruction
beyond the instruction during which STOP was asserted. The microprocessor then remains
in a halt state until the STOP input is released.
A bus request (BUSREQ) is honored while the microprocessor is halted. Additionally,
interrupts are acknowledged upon release of STOP, but not while STOP remains asserted.
Figure 2-36 depicts the start of single-step operation. The operation is started by the
assertion of STOP. The CPU will complete the current instruction and execute, at most,
one more instruction. After this the CPU stops execution and issues the SAS code "stop
acknowledge." The CPU will remain in this state until STOP is released.

CLK23

CLK34
SASQSAS3
STOP

-

ACKNOWLEDG~

H
h,

-

V-t

Notes:
I. At most, one full assertion of SOl may appear before STOP is acknowledge.
2. BARB = 0 and BRACK = 1 in order to see stop acknowledge access status code.

Figure 2-36.

Start of Single-Step Operation

2-57

ARCHITECTURE & BUS OPERA nON
Coprocessor Operations

CLK23

CLK34

SASOSAS3

STOP ACKNOWLEDGE
STOP

Note: BARB

ACKNOWLEDG~

= 0 and BRACK = 1 in order to see stop acknowledge access status code.

Figure 2-37.

Single-Step Operation

After the CPU has stopped, and until a start of instruction output (SOU is issued,
instruction by instruction execution can be performed by releasing STOP. At this point,
immediate application and holding of STOP will prevent a second instruction from starting.
With STOP asserted, the CPU will complete the instruction and issue the stop acknowledge
SAS code. To resume normal execution, STOP must be completely released. The singlestep operation is shown on Figure 2-37.

2.14 COPROCESSOR OPERATIONS
The WE 32100 Microprocessor provides a coprocessor interface consisting of ten
instructions and the associated pinout and bus transactions. The coprocessor interface
assures high performance and system throughput. When a coprocessor instruction is
executed by the CPU, a series of bus transactions occur. The following details the process
and provides the associated protocol.

2.14.1 Coprocessor Broadcast
This transaction notifies the coprocessor of the action the CPU wants performed. To
prevent memory from being selected, AS is not issued during this transaction. Since this is
a write operation, R/w is in write mode and the timing of DS is for a write. The CPU
drives the data bus with the information that it wants to send to the coprocessor. The
coprocessor responds with a memory acknowledge. The CPU then terminates the
transaction and goes on to the next one. The CPU will insert up to two wait cycles while it

2-58

ARCHITECTURE & BUS OPERATION
Coprocessor Broadcast

waits for the memory acknowledge from the coprocessor. This gives the coprocessor a
limited time to respond to this transaction. Figure 2-38 shows the zero, one, and two wait
cycle cases before the coprocessor responds with a memory acknowledge (in this case,
SRDY).

CLK23

CLK34
SASOSAS3

-

rLLr ~ J rL J

-

f

"'

L.:........J
!~
COPROCESSOR BROADCAST

E

f3\ ~
4
~ I~ ~ \

Vi'

0

~

<((

-&-

NEXT VALID

-

DATAOODATA31

'// /,

,\ \ \'

-

«<
x:M XIX Y1

COMMAND liD

'\X x:M XIX XIX 'XIX

:XXX :XXX :XXX :X\

IX :XXX :XXX :XXX
.\\ \'

Riw

'// I.

- ,\\\
- ,\ \ \'

'// I.
A. Zero Wait Cycles

Notes:
1. Zero, one, and two wait cycles using SRDY.
2. Greater than two wait cycles causes internal CPU memory fault.

Figure 2-38.

Coprocessor Command and ID Transfer (Sheet 1 of 3)

2-59

ARCHITECTURE & BUS OPERATION
Coprocessor Broadcast

CLK23

-

V l\-V l\-V l\-V I\-' fI\-

CLK34

,

SASOSAS3

E

~

Vi' ~ ~ ~ VW"' ~ ~ ~ ~ 1\

COPROCESSOR BROADCAST

<<<

~

NEXT VALID

DATAOODATA31

\\\ \'

-

'I I I

<<<

-

COMMAND/ID

' The microprocessor also
executes the appropriate microsequence before passing control to the operating system.
These sequences save the context of the current process and give the operating system
information it needs to locate the correct exception handler. The saved context enables the
program to resume execution after the exception is handled.

Table 2-8.

Exception Type

Exception

Normal Exception
(ET=l1)

Integer zero-divide
Trace trap
Illegal opcode
Reserved opcode
Invalid descriptor
External memory fault
Gate vector fault
Illegal level change
Reserved data type
Integer overflow
Privileged opcode
Breakpoint trap
Privileged register
Stack bound
Stack fault
Interrupt ID fetch
Old PCB fault
Gate PCB fault
New PCB fault
Old PCB fault
System data
Interrupt stack fault
External reset
New PCB fault
Gate vector fault

Stack Exception
(ET=01)
Process Exception
(ET=10)
Reset Exception
(ET=OO)

* These exceptions

2-66

Exception Conditions
Internal
State
Code Bit
5 4 3
6
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1

0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
0

1

1

reset the processor status word flags.

0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0

ARCHITECTURE & BUS OPERATION
Exceptional Conditions

The exceptions increase in levels of severity, with normal exceptions being the least severe
and reset exceptions being the most severe. An exception (but not reset exceptions which
require restarting the system) can ripple up through levels of exception severity if its
handling routine cannot resolve the condition that caused the exception.
1.

Normal Exception. The microprocessor generates this class of exception when it
detects a condition such as trap, invalid opcode, incorrect address mode, or illegal
operation. Most normal exceptions occur during the translation or execution of an
instruction.

2.

Stack Exception. This exception may occur during a process switch or a GATE
sequence (see Chapter 4).

3.

Process Exception. This exception may occur during a process switch (see Chapter 4).

4.

Reset Exception. This exception is triggered by an error condition in accessing critical
system data and requires restarting of the system. Since exceptions can ripple up to
higher levels of severity, reset exceptions may occur during reset and also during
process and normal exceptions. The microprocessor reacts as if an external reset
occurred when a reset exception is detected. (See 2.11 Reset and Chapter 4.
OPERATING SYSTEM CONSIDERATIONS'>

Normal exceptions consist of two types of events generated by the microprocessor - traps
and exceptions. When a trap is generated, the instruction that caused the trap is executed
completely, and the program counter (PC) points to the next executable instruction.
(Integer overflows may not behave this way due to pipelining; see part b under Integer
Overflow.) When an exception is generated, the PC points to the opcode of the instruction
that caused the exception; this instruction may have been executed partially or not at all.
Each different trap or exception uses a different trap vector to branch to the corresponding
trap or exception-handling software.
There are three kinds of traps:
1.

Breakpoint Trap (BPT). This trap is invoked whenever the breakpoint trap (BPT)
instruction is executed.

2.

Integer Overflow. This trap is enabled when the enable overflow trap (OE) bit in the
processor status word is set. Overflow trapping behaves as follows:
a.

When an overflow trap occurs, the OE bit is cleared before the PSW is saved.

b.

When an overflow trap occurs, the instruction following the instruction that
caused the overflow trap mayor may not be executed before the microsequence is
entered. Consequently, the saved PC may point to the instruction following the
trapped instruction or to the next instruction after that one. If the instruction
following the trapped instruction is completed, it may not set the PSW flags.

c.

If two consecutive instructions cause overflow traps, only one overflow trap
occurs.

d.

An overflow trap occurs if the OE bit is set and the execution of an instruction
causes the V (overflow) bit in the PSW to be set (1) after the instruction is
completed. In particular, this can be caused by the return from gate (RETG)
and return to process (RETPS) instructions or by an explicit move to the PSW.

2-67

ARCHITECTURE & BUS OPERATION
Exceptional Conditions

3.

Trace Trap. Trace trapping is enabled when the trace enable (TE) bit in the PSW is
set. This causes a trace trap to occur after each instruction is executed (except for the
RETPS, CALLPS, and RETG instructions).

There are ten types of exceptions:
1.

External Memory Fault. This exception occurs if alignment requirements are violated,
if an external device asserts the FAULT input on an access, if a fault occurs during a
coprocessor status fetch, or if no coprocessor responds to a support processor
broadcast. Alignment fault behavior has the following properties:
a.

No alignment fault ever occurs on a byte access.

b.

No alignment fault ever occurs on an instruction fetch access.

c.

An alignment fault occurs if the access is a data access of word length and if
address bit 1 (ADDROI) or address bit 0 (ADDROO) is 1.

d.

An alignment fault occurs if the access is a data access of halfword length and
address bit 0 (ADD ROO) is 1.

2.

Gate Vector Fault. This exception is caused by a memory fault when reading gate
tables during a gate (GATE) instruction.

3.

Illegal Level Change. This exception is caused when attempting to increase the current
execution privilege on a return from gate (RETG) instruction.

4.

Illegal Opcode. The opcode is not defined for the microprocessor.

5.

Integer Zero-divide. This exception is caused by an attempt to divide by zero and is
always enabled. This exception resets the PSW flags.

6.

Invalid Descriptor. The address mode generated cannot be used in the specified way.
This exception resets the PSW flags and may result from the following causes:
a.

Literal or immediate used as destination.

b.

Effective address requested of literal or immediate.

c.

Effective address requested of a register.

7.

Privileged Opcode. The opcode is defined for kernel execution level only. An attempt
to execute it in another execution level causes this exception.

8.

Privileged Register. An attempt to write the three privileged registers (process status
word, process control block pointer, and interrupt stack pointer) in an execution level
other than kernel causes this exception. This exception resets the PSW flags.

9.

Reserved Data Type. The operand type described by the expanded operand-type
descriptor is not implemented in the microprocessor. This exception resets the PSW
flags.

10. Reserved Opcode. The opcode is not implemented on the microprocessor, but is
reserved for future use.

2-68

ARCHITECTURE & BUS OPERATION
Trace Mechanism

2.16 TRACE MECHANISM
Every instruction for the WE 32100 Microprocessor consists of an interruptible and a
non interruptible portion. Because a trace trap is detected in the noninterruptible portion,
trace traps have priority over interrupts. The microprocessor's trace trap mechanism uses
two bits in the processor status word: trace enable (TE) and trace mask (TM).
Trace traps are enabled if TE is set (1), but a trace trap is generated only if TM is also set
(see Table 2-9). In the table:
o TE-beg is the value of the TE bit at the start of an instruction.
o TE-end is the value of the TE bit at the time the trace trap is detected.
o TM-end is the value of the TM bit at the same instant the trace trap is detected.
The microprocessor detects a trace trap before the next instruction starts. Any of the
following actions may change the values of the TE and TM bits at the end of an
instruction:
o

An instruction, other than an operating system instruction or microsequence, writes to
the PSW and changes TE. However, this method of changing TE causes inconsistent
trace behavior and should be avoided.

o A return from gate (RETG) instruction restores the PSW from the stack.
o A context switch to a process loads the PSW from the process control block.
Because of the way a return to process (RETPS), call process (CALLPS), or return from
gate (RETG) instruction changes TE and TM when it overwrites the PSW, these
instructions cannot be traced.

Table 2-9.

Truth Table for Trace Trap

TE-beg

TE-end

TM-end

Trap

0

0

o or

I

No

0

I

0

No

0

1

1

Yes

1

0

o or 1

No

1

1

0

No

1

1

1

Yes

Note: This table is valid only if an operating
system instruction or microsequence is used
to alter the TE bit of the PSW.

2-69

ARCHITECTURE & BUS OPERATION
Pin Assignments

The TM bit cannot be set by software. However, the microprocessor changes TM
automatically by:
• Setting TM to 1 at the beginning of every instruction.
• Clearing TM to 0 as part of every microsequence that performs a context switch.
• Clearing TM to 0 as part of the return from gate microsequence.
• Clearing TM to 0 when it detects and responds to a fault or interrupt.
The TM bit masks the TE bit for the duration of one instruction. The user's trace-trap
handler should use TM to prevent a trace trap when a return from gate instruction returns
control to a process. Similarly, the microprocessor uses the TM bit to prevent a trace trap
from occurring in the context of a newly switched process when the previous process is
being traced.

2.17 PIN ASSIGNMENTS
The WE 32100 Microprocessor contains 107 active pins, ten power pins, and eleven ground
pins. Figure 2-43 illustrates the WE 32100 Microprocessor pin-array package as viewed
from both the top and bottom. The top view shows the scratch pad test points and the 700
mil square heat sink attachment area. The scratch pads provide test points for each pin.
The heat sink is user-supplied and is used in applications that require additional cooling.
The following tables list the pins both in numerical order and by functional groups.
In the following pin function descriptions the term asserted means that a signal is driven to
its active state either by the microprocessor (outputs) or an external device (inputs). The
term negated means that the signal is driven to its inactive state. A bar over a signal name
(e.g., As) indicates that the signal is active low, logic O. The 0 bit is the least significant
bit for signals which occupy two or more pins (e.g., DSIZEO-DSIZEI). The signal type
column is interpreted as input (I), output (0), or bidirectional (110).

2-70

ARCHITECTURE & BUS OPERATION
Pin Assignments

Atl

o

AtD

811

elt

011

Elt

Fl1

Jl1

Kl1

Ll1

Ml1

Ntl

Pt1

all

Rtt

S11

Ttl

U11

0

0

0

0

DOD

0

0

0

0

0

0

0

0

0

0

DOD

810

eta

010

EtO

FtO

Gl0

Jl0

Kl0

LtD

M1D

Nl0

PtO

010

Rl0

510

110

UtO

Vl0

10110

0

0

0

DOD

0

0

0

0

0

0

0

0

0

0

0

0

~

n

~

n

~

DOD
AS

o

Hll
Hl0

Ba

CB

08

E8

FB

~

0

0

0

0

0

DOD

Vl1

10111

DOD

~

~

~

u

n

~

0

0

0

0

0

DOD

DOD

~

u

o

G11

o

U

H

~

~

~

~

0

0

0

0

0

u

~

~

n

~

.

~

~

~

00000

~

~

"

0

~
M
"
DOD

0"

"

0

0~

0

0

~

M

~

~

DOD

0

0

0

o

0

0

0

0

DOD
~

"

~

0

0

0

0

0

0

0

0

0

0

0

o
Al

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DOD

u

"

B1

~

Cl

"

01

~

El

Fl

81

Hl

~

Jl

H
Kl

~

U

II

Ml

~

Nt

~

Pl

"

at

U

Rt

H

81

"

11

"

U1

n

Vt

~

Wl

Top View

o

10111

0

0

000

000

0

0

0

0

0

0

0

000

0

~

Vl1

U11

Tl1

all

Ml1

l11

Kl1

Jl1

Hl1

G11

Fl1

Elt

Bl1

Att

S11

Rtt

000

000

0

\.rIl0

Vl0

Ul0

110

810

RtO

Ql0

o

0

n

0

0

0

0

~

~

~

o

Pt1

0

pta

Ntl

all

elt

0

0

0

0

0

0

0

0

0

0

000

NtO

M10

L 10

Kl0

Jl0

Hl0

Gl0

FtO

Eta

010

eto

810

AtO

o

0

0

0

0

0

~

~

~

0

0

~

m

0

0

0

0

0

000

~

n

u

0

~

~

"

o

0

"

0

0

0

0

0

~

~

~

H

0

~

o

0

~

o

0

0

0

.

0

~

0

~

"

"

"

~

~

~

n

~

0

~

~

~

M

u

U

0

0

000

0

0

M

~

~

~

~

u

0

00000

~

M

000

0

0

0

0

0

0

0

000

0

0

~

~

~

U

H

~

~

"

~

~

"

~

"

u

0

000

0

0

0

0

0

0

0

0

0

0

0

0

0

S1

Rt

Nt

Ml

II

Kl

Jl

Hl

61

Fl

Et

01

Cl

81

At

~

n

"

"

un"

o

0

0

0

Vl

U1

11

.1011

~

at

Pl

Bottom View

Figure 2-43.

WE 32100 Microprocessor Pin Configuration

2-71

ARCHITECTURE & BUS OPERATION
Pin Assignments

Table 2-10.

2-72

WE 32100 Microprocessor Pin Descriptions

Pin

Name

Type

Al
A2
A4
AS

DATAl 8
ADDR17
DATAI7
DATAI4

I/O

A7
A8
AIO
All

ADDR12
ADDRII
DATA08
ADDR06

BI
B2
B4
BS

DATAI9
GRD
DATAI6
ADDRI3

I/O

B7
B8
BIO
B11
CI
C2
C4
CS
C7
C8
CIO
CII
DI
D2
D4
DS
D7
D8
DIO
D11
EI
E2
E4
E5
E7
E8
EIO
Ell

ADDRIO
ADDR09
ADDROS
ADDR04
DATA22
DATA20
DATAIS
+SV
DATA09
+SV
DATA04
DATA03
ADDR23
+SV
GRD
DATAOS
GRD
ADDR07
GRD
DATA02
DATAI2
DATA 11
ADDR08
DATA06
ADDR03
ADDROI
IPLl
DATAOI

0
0
0
0

0
I/O
I/O

0
0
1/0

0

I/O

0

I/O
I/O
1/0

I/O

1/0
I/O

0

I/O

0

I/O
I/O
I/O

0
I/O

0
0
I
I/O

Description
Microprocessor
Microprocessor
Microprocessor
Microprocessor

Data 18
Address 17
Data 17
Data 14

Microprocessor
Microprocessor
Microprocessor
Microprocessor

Address 12
Address II
Data 08
Address 06

Microprocessor
Microprocessor
Microprocessor
Microprocessor

Data 19
Ground
Data 16
Address 13

Microprocessor Address 10
Microprocessor Address 09
Microprocessor Address 05
Microprocessor Address 04
Microprocessor Data 22
Microprocessor Data 20
Microprocessor Data IS
Microprocessor Power
Microprocessor Data 09
Microprocessor Power
Microprocessor Data 04
Microprocessor Data 03
Microprocessor Address 23
Microprocessor Power
Microprocessor Ground
Microprocessor Data 05
Microprocessor Ground
Microprocessor Address 07
Microprocessor Ground
Microprocessor Data 02
Microprocessor Data 12
Microprocessor Data II
Microprocessor Address 08
Microprocessor Data 06
Microprocessor Address 03
Microprocessor Address 01
Interrupt Priority Level I
Microprocessor Data 01

ARCHITECTURE & BUS OPERATION
Pin Assignments

Table 2-10.

WE 32100 Microprocessor Pin Descriptions (Continued)

Pin

Name

Type

F1
F2
F4
F5
F7
F8
FlO
F11
01
G2
GIO
Gil

ADDR14
DATA13
DATAIO
DATA07
ADDR02
ADDROO
+5V
DATAOO
ADDR15
GRD
IPL3
VAD

0
I/O
I/O
I/O
0
0

I
0

Microprocessor Address 14
Microprocessor Data 13
Microprocessor Data 10
Microprocessor Data 07
Microprocessor Address 02
Microprocessor Address 00
Microprocessor Power
Microprocessor Data 00
Microprocessor Address 15
Microprocessor Ground
Interrupt Priority Level 3
Virtual Address

HI
H2
HIO
HII

ADDRI8
ADDR16
AVEC
IPLO

0
0
I
I

Microprocessor Address 18
Microprocessor Address 16
Auto-vector
Interrupt Priority Level 0

11
J2
110
111

ADDRl9
+5V
IPL2
INTOPT

0

Microprocessor Address 19
Microprocessor Power
Interrupt Priority Level 2
Interrupt Option

K1
K2
K10
K11

ADDR20
DATA21
-NMINT

0
I/O
I

LI
L2
LlO
Lli
M1
M2
M10
Mll
N1
N2
N10
Nil
PI
P2
P10
P11

ADDR21
ADDR22
--

ABORT
DRDY

DATA23
DATA25
CLK34
AS
DATA24
GRD
CLK23
DS
DATA26
ADDR28
--FAULT
RESETR

I/O
0

-

I
I

0
0
0
0
I/O
I/O
I
0
I/O

I
0
1/0
0
I
I

Description

Microprocessor Address 20
Microprocessor Address 21
Nonmaskable Interrupt
WARNING: This pin is for
manufacturing use only and must be
tied high (+5 Vdc).
Microprocessor Address 21
Microprocessor Address 22
Access Abort
Data Ready
Microprocessor Data 23
Microprocessor Data 25
Input Clock 34
Address Strobe
Microprocessor Data 24
Microprocessor Ground
Input Clock 23
Data Strobe
Microprocessor Data 26
Microprocessor Address 28
Fault
Reset Request

2-73

ARCHITECTURE & BUS OPERATION
Pin Assignments

Table 2-10.
Pin

2-74

WE 32100 Microprocessor Pin Descriptions (Continued)
Name

QI
Q2
QIO
Qll
RI
R2
R4
RS
R7
R8
RIO
Ril
SI
S2
S4
SS
S7
S8
SIO
Sll

ADDR27
+SV
--RESET
BLKFTCH
ADDR29
ADDR30
DATA31
IQSI
SAS2
-SRDY
--RETRY
-DTACK
ADDR24
ADDR3I
DATA30
XMDI
BRACK
DSIZEI
GRD
-STOP

TI
T2
T4
TS
T7
T8
TIO
TIl
UI
U2
U4
US
U7
U8
UIO
Ull

ADDR2S
GRD
+SV
XMDO
+SV
SASO
--DSHAD
CYCLEI
ADDR26
DATA27
IQSO
GRD
R/W
GRD
+SV
No Connect

VI
V2
V4
VS

DATA28
+SV
SOl
BUSRQ

Type

0

0
I
0
0
I/O

0
0
I
I
I
0
0
I/O

0
I/O

0

I

0

0

0
I
0
0
I/O

0

0

I/O

0
I/O

Description
Microprocessor Address 27
Microprocessor Power
Reset Acknowledge
Block (Double Word) Fetch
Microprocessor Address 29
Microprocessor Address 30
Microprocessor Data 31
Instruction Queue Status 1
Access Status Code 2
Synchronous Ready
Retry
Data Transfer Acknowledge
Microprocessor Address 24
Microprocessor Address 31
Microprocessor Data 30
Execution Mode 1
Bus Request Acknowledge
Data Size 1
Microprocessor Ground
32100 Stop
Microprocessor Address 2S
Microprocessor Ground
Microprocessor Power
Execution Mode 0
Microprocessor Power
Access Status Code 0
Data Bus Shadow
Cycle Initiate
Microprocessor Address 26
Microprocessor Data 27
Instruction Queue Status 0
Microprocessor Ground
Read/Write
Microprocessor Ground
Microprocessor Power
WARNING: This pin must be
left unconnected.
Microprocessor Data 28
Microprocessor Power
Start of Instruction
Bus Request

ARCHITECTURE & BUS OPERATION
Pin Assignments

Table 2-10.

WE 32100 Microprocessor Pin Descriptions (Continued)

Pin

Name

V7
VS
VIO
VII
WI
W2
W4
WS
W7
WS

DSIZEO

WIO,
WII

-HIGHZ

RRREQ
BARB
GRD
DATA29
SAS3
SASI

DONE
RRRACK
No Connect

Table 2-11.

Type

Description

0
I
I
I

Data Size 0
High Impedance
Relinquish and Retry Request
Bus Arbiter
Microprocessor Ground
Microprocessor Data 29
Access Status Code 3
Access Status Code I
Coprocessor Done
Relinquish and Retry
Request Acknowledge
WARNING: These pins must be
left unconnected.

110
0
0
I
0

-

Address and Data Signals

Name

Pin(s)

Type

ADDROO-ADDR3I

FS,ES,F7,E7,
BII,BlO,All,
DS,E4,BS,B7,
AS,A7,BS,FI,
Gl,H2,A2,Hl,
J1,KI,Ll,L2,
DI,SI,Tl,Ul,
QI ,P2,R I ,R2,
S2

0

DATAOO-DATA3I

Fll,Ell,Dll,
CII,ClO,DS,
ES,FS,AIO,
C7,F4,E2,EI,
F2,AS,C4,B4,
A4,AI,BI,C2,
K2,CI,MI,NI,
M2,PI,U2,VI,
W2,S4,R4

110

Description
Address. These pins are used by the
microprocessor to issue 32-bit addresses
for off-chip accesses. They also convey
the interrupt acknowledge level on bits 2
through 6 during an interrupt
acknowledge operation.

Data. These bidirectional pins are used to
convey data to and from the
microprocessor. This data may be an
interrupt vector (bits 0 through 7).

2-75

ARCHITECTURE & BUS OPERATION
Pin Assignments

Table 2-12.
Pines)

Type

Description

AS

Mll

0

Address Strobe. When low (0), this signal indicates the
presence of a valid physical address on the address pins. If
the address is virtual, the falling edge of AS indicates a valid
address, and the address pins are 3-stated subsequent to the
falling edge of AS.

CYCLEI

Til

0

DONE

W7

I

Cycle Initiate. This signal is asserted at the beginning of a
bus transaction and negated two clock cycles later. CYCLEI
is asserted in both the read and write halves of an
interlocked read transaction.
Coprocessor Done. This input is recognized during a
coprocessor instruction. It informs the microprocessor that a
slave processor has completed its operation.

DRDY

LII

0

Data Ready. When asserted, this signal indicates that the
microprocessor has not detected any bus exceptions (FA UL T,
RETRY, RRREQ signals) during the current bus cycle. The
trailing edge of this signal indicates the end of a bus
transaction which has no bus exceptions.

DS

NIl

0

Data Strobe. During a read operation this signal, when low,
indicates that a slave device can place data on the data bus.
During a write operation, this signal, when low, indicates
that the microprocessor has placed valid data on the data
bus.

DTACK

Rll

I

Data Transfer Acknowledge. This signal is used to
handshake between the microprocessor and a slave device.
During a read operation, the microprocessor latches data
present on the data bus and terminates the bus transaction
one cycle after DTACK is driven low by a slave device.
During a write operation, the transaction is terminated when
a slave device drives DTACK low. If DTACK is high, wait
states are inserted in current cycle. DTACK is ignored if the
data bus shadow (DSHAD) input is asserted. The DTACK
input can be returned asynchronously and is double latched
to avoid metastability.

SRDY

R8

I

Synchronous Ready. When asserted, this signal is a
synchronous input that begins the termination of a read or
write operation. It is sampled only once on the leading edge
of the fifth clock state during read and write operations. If
SRDY is not asserted at this time and DTACK was not
asserted during the previous cycle, then wait-state cycles are
inserted until either signal is asserted. SRDY is ignored if
the data bus shadow (DSHAD) input was previously
asserted.

Name

2-76

Interface and Control Signals

ARCHITECTURE & BUS OPERATION
Pin Assignments

Table 2-13.
Name

Pin(s}

Type

Access Status Signals
Description

BLKITCH

QII

Block r

XX :XXX :XXX

,\ \ \

3 .....

'" ..-j

~rJl

YiX YJ(i XiX :XXX :XXX :XX

--

;"X

8-t"'l
e.~

<<<

<<
<

~0

FETCH/PREFETCH

.xXX XIX :XA

SRDY

R/W

~

~

~

«<

----

DTACK

DRDY

READ

3

CJl>

=~
:g("l

V777/

zo

CLK23

CLK34

~

Lr ~Lrl\-f l\- f
~

SASOSAS3
DSIZEODSIZEI
ADDROOADDR31

~

I~

v---;--.

-

~

~

I~

(((

READ

-

4
'------J

Lr ~Lr ~Lrl\-f
"'-'X'
~

~

I~

~

(((

WRITE

x

'------J

~

NEXT VALID

«(

(((

«(

~

I\-

VALID

)

3 - STATE IF VIRTUAL

(

«(

VALID

)

3 - STATE IF VIRTUAL
I

I
AS

-

,\\\

'I I I.

OS

-

,\\ \

'///.

I

f I I I.

,\\\

I

DATAOODATA31

VALID

SRDY

DRDY

R/W

BLKFTCH

CYCLEI

-

U I 1.1

«(

XX :XXX XIX

VALID

I

:XXXI ;XX\'

I

;;

:XXX :XXX: :XXX :XXX XIX XIX YXX XIX X'M y;j){ XM 'XXX XXX ~XXX :XXX )(AI\ \

::t

'XM ~XXx: ~XXX: ~XXX :MX X"

X'M XIX J(\

DTACK

.\\\

,\\\

'I I I.

,~XXX

'I I I.

,\\\

,\ \ \

::3
t"l

m(""l

= ..-j

:gL:
;"::r::l
3t"l
to

s-S
...~ ....
0

~..-j

~ Z

00>

N

~

0

CLK23

CLK34

- f
-,

~ U-l\-f
0

~

ADDROOADDR31

AS

os

-

-

«<

I~

~

!r---s-'

v--;:--;
I~

~ ~ f""'3'

4

'---'

;;"=
3 ....
... ,...;j

::"t"l
'" (j
~,...;j

<<<

WRITE

NEXT VALID

..~t"l
~

e..~

Ot=
~r

VALID

)

3 - STATE IF VIRTUAL

x< <<<

VALID

)

"'0

z

:<<<

VALID

XXX XXX XXX :XXX :XXX: :XA

(XXX :XXX )(\

~
>
~
o

'I I I.

,\ \ \'

VALID

~ ~

'// I.

'I I I.

&\

:XXX XIX :XXX

(XXX :XXX :XXX :XXX (XXX (XXX: :XXX :XXX :XXX :XXX :XXX (XXX :XXX. :XXX :XXX (XXX

,\ \ \'

-

,\\,i

'I I I.

- ,\ \ \
-

ill

'I I /

,\ \ \

c::

~00

3 - STATE IF VIRTUAL

,\\ \'

'// /,

,\ \ \

<<<

~

CYCLEI

0

U-I\-

<<<

-

SRDY

BLKFTCH

.r---;-'

.\ <~

-

DTACK

R/W

X

<<<

WRITE

DATAOODATA31

DRDY

~~~
I~
2

~'J ~

~c::

SASOSAS3
DSIZEODSIZEI

.~

~ U-l\-f

~f

=~
:g(j

'I I I.

Note: Zero wait cycles.
Figure 2-46. Write Transaction Followed by a Write Transaction

rm

v '-- f

CLK23

-

CLK34

--- ~

SASOSAS3
DSIZEODSIZEI
ADDROOADDR31

AS

os

-

CYCLEI

'3"

~

~V
~

~

~f
~

,\ \ \

~

~

V

'7' I~

~V ~ f

~

Ir-----\

'Y.' ,

3

I~

Irs-'

,\ \\

READ

~

NEXT VALID

<<<

:\ \\

)

3 - STATE IF VIRTUAL

,\\\
,\\ \'

-

\\\

~XXX, \'IX/: (xXX

(

\ \\

VALID

)

,\ \ \'

'III,

'Ill

,\\ \'

'Ill

~XXX

:XXX :XXX

VALID

:XXX: (XXX' (XXX :XXX :X\

:X~ ~XXX, ~XXX, ~XX.

,\\\

-

3 - STATE IF VIRTUAL

'III,

VALID

(XXX: (XXX' (X\

SRDY

BLKFTCH

~

V

:<<<

-

DTACK

R/W

I

~

VlRITE

DATAOODATA31

iiRiiY

r---'I

:XXX (XXX: (XXX:

:XXx. :XXX ~XX :XXX :XX7v ~XXX, ,XXX,

>
~

rm;

:=3

'II/,

,\ \\

::t:

t"l

oo(""l
=~

'III,

- ,\\ \'

XX: :XXX: (X)--

I

:gc:::

iO::e

3t"l

'"s-~

'II I

- ,\ \ \'

,\ \ \'

'Ill

~=

"'=c:::
.. 00

S.o

Note: Zero wait cycles.

:; "tj

S2.t"l
t:;;~

N

~

....

Figure 2-47. Write Transaction Followed by a Read Transaction

-->

Jg~

~S

~

z

00>
=~
:g('j

N
I

~

N

CLK23

CLK34

-

---,

v

~f

~

'7' '----'
2
~ ~ '5'

l\-f

~

,rt--INSTRUCTION FETCH/PREFETCH

SASOSAS3
DSIZEODSIZEI
ADDROOADDR31

AS,DS

-

I

XU, 
::0

;-J

--

BO"SR5

-

BRACK

-

(j

\

""'

-

I

I

r-V

I

I

r'-'

-c-

r

::e
~

l'!'l
Vll'J.
0-3

=
::ge
.. ::0
~l'!'l

Note: The same protocol diagram applies for retry and bus arbitration except that the address bus, data
bus, and control signals are not 3-stated during the time RETRY is active and RRRACK is not issued.

~St:o
.:ltX'

~5i

..,S"O
~

Figure 2-49.

Bus Arbitration During Relinquish and Retry

g.,l'!'l
t;I::O

;.>

IJQ..-..j
N

,:c,
...,

........
=
0
~Z

Chapter 3

Instruction Set and
Addressing Modes

CHAPTER 3.

INSTRUCTION SET AND ADDRESSING MODES
CONTENTS

3. INSTRUCTION SEL ................
3.1 DATA TyPES ............................
3.1.1 Sign and Zero Extension ..........
3.2 REGISTERS ...............................
3.2.1 Writing and Reading
Registers .................................
3.3 INSTRUCTION FORMAT ......
3.3.1 Data Embedded in Operands ...
3.4 ADDRESS MODES ...................
3.4.1 Absolute Address Modes ..........
Absolute ....................................
Absolute Deferred.....................
3.4.2 Displacement Modes ................
Byte Displacement ....................
Byte Displacement Deferred ....
Halfword Displacement ............
Halfword Displacement
Deferred ..................................
Word Displacement ..................
Word Displacement Deferred ...
AP Short Offset ........................
FP Short Offset.. .......................
3.4.3 Immediate Modes .....................
Byte Immediate .........................
Halfword Immediate.................
Word Immediate .......................
Positive LiteraL.......................
Negative LiteraL .....................
3.4.4 Register Modes .........................
Register Mode... ........................
Register Mode Deferred ...........
3.4.5 Expanded-Operand Type
Mode ......................................
3.5 CONDITION FLAGS ...............
3.6 FUNCTIONAL GROUPS ........
3.6.1 Data Transfer Instructions .......
3.6.2 Arithmetic Instructions ............
3.6.3 Logical Instructions ..................
3.6.4 Program Control Instructions ..
Subroutine Transfer ................
Procedure Transfer .................

3·1
3·1
3·3
3·3
3·6
3-6
3·6
3-6
3·10
3-10
3·11
3-11
3-11
3·12
3-12
3-13
3-14
3-14
3·15
3-15
3-16
3-16
3·17
3-17
3-18
3-18
3-19
3-19
3-19
3-20
3-22
3-23
3·23
3-25
3-26
3-28
3·28
3·28

3.6.5 Coprocessor Instructions ..........
3.6.6 Stack and Miscellaneous
Instructions.............................
3.7 INSTRUCTION SET
LISTINGS ................................
3.7.1 Notation ....................................
Assembler Syntax....................
Opcodes ...................................
Operation .................................
Address Modes ..... ...................
Condition Flags .......................
Exceptions................................
Examples ......... .............. ..........
Notes (Optional) .....................
3.7.2 Instruction Set Descriptions .....
Add (ADDB2, ADDH2,
ADDW2) ................................
Add,3 Address (ADDB3,
ADDH3, ADDW3) ................
Arithmetic Left Shift
(ALSW3) ................................
AND (ANDB2, ANDH2,
ANDW2) ................................
AND, 3 Address (ANDB3,
ANDH3, ANDW3) ................
Arithmetic Right Shift
(ARSB3, ARSH3, ARSW3).
Branch on Carry Clear
(BCCB, BCCR) ................. ....
Branch on Carry Set
(BCSB, BCSH) ......................
Branch on Equal
(BEB, BEH) . ..... .............. .......
Branch on Greater Than
(Signed) (BGB, BGH) ...........
Branch on Greater Than
or Equal (Signed)
(BGEB, BGEH) .....................
Branch on Greater Than
or Equal (Unsigned)
(BGEUB, BGEUH) ...............

3-32
3-32
3-33
3-34
3-34
3-34
3-34
3-34
3-34
3-34
3-34
3-34
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3·44
3-45
3-46

3-47
3·48

CONTENTS
Branch on Greater Than
(Unsigned) (BGUB,
BGUH) ...................................
Bit Test (BITB, BITH,
BITW) .....................................
Branch on Less Than
(Signed) (BLB, BLH) ............
Branch on Less Than or
Equal (Signed)
(BLEB, BLEH) ......................
Branch on Less Than or
Equal (Unsigned)
(BLEUB, BLEUH) ................
Branch on Less Than
(Unsigned) (BLUB, BLUH)..
Branch on Not Equal
(BNEB, BNEH) .....................
Breakpoint Trap (BPT) ............
Branch (BRB, BRH) ................
Branch to Subroutine
(BSBB, BSBH) .......................
Branch on Overflow Clear
(BVCB, BVCH) .....................
Branch on Overflow Set
(BVSB, BVSH) ......................
Call Procedure (CALL) ...........
Cache Flush (CFLUSH) ..........
Clear (CLRB, CLRH,
CLRW) ...................................
Compare (CMPB, CMPH,
CMPW) ..................................
Decrement (DECB, DECH,
DECW) ...................................
Divide (DIVB2, DIVH2,
DIVW2) ..................................
Divide, 3 Address
(DIVB3, DIVH3, DIVW3)....
Extract Field (EXTFB,
EXTFH, EXTFW) .................
Extended Opcode (EXTOP) ....
Increment (INCB, INCH,
INCW) ....................................
Insert Field (INSFB,
INSFH, INSFW) ...................
Jump (JMP) .............................
Jump to Subroutine (JSB) .......

3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-65
3·66
3-67
3·68
3·69
3-70
3-71
3·12
3-73

Logical Left Shift
(LLSB3, LLSH3, LLSW3) ...
Logical Right Shift
(LRSW3) ................................
Move Complemented
(MCOMB, MCOMH,
MCOMW) ..............................
Move Negated (MNEGB,
MNEGH, MNEGW) .............
Modulo (MODB2, MODH2,
MODW2) ................................
Modulo, 3 Address (MODB3,
MODH3, MODW3) ...............
Move (MOVB, MOVH,
MOVW) ..................................
Move Address (Word)
(MOVAW) .............................
Move Block (MOVBLW) ........
Multiply (MULB2,
MULH2, MULW2) ...............
Multiply, 3 Address (MULB3,
MULH3, MUL W3) ...............
Move Version Number
(MVERNO) ...........................
No Operation (NOP,
NOP2, NOP3) ........................
OR (ORB2, ORH2,
ORW2) ...................................
OR, 3 Address (ORB3,
ORH3, ORW3) ......................
Pop (Word) (POPW) ...............
Push Address (Word)
(PUSHAW) ............................
Push (Word) (PUSHW) ..........
Return on Carry Clear
(RCC) .....................................
Return on Carry Set
(RCS) .....................................
Return on Equal
(REQL, REQLU) ..................
Restore Registers
(RESTORE) ...........................
Return from Procedure
(RET) .....................................
Return on Greater Than
or Equal (Signed) (RGEQ)...

3-74
3-75
3-76
3·77
3-78
3·79
3-80
3-82
3-83
3-85
3·86
3·87
3·88
3-89
3-90
3-91
3·92
3-93
3-94
3-95
3·96
3·97
3-98
3·99

CONTENTS
Return on Greater Than
or Equal (Unsigned)
(RGEQU) ...............................
Return on Greater Than
(Signed) (RGTR) ...................
Return on Greater Than
(Unsigned) (RGTRU) ...........
Return on Less Than
or Equal (Signed) (RLEQ) ....
Return on Less Than or Equal
(Unsigned) (RLEQU) ............
Return on Less Than
(Signed) (RLSS) ..... ...............
Return on Less Than
(Unsigned) (RLSSU) .............
Return on Not Equal
(RNEQ, RNEQU) .................
Rotate (ROTW) .......................
Return from Subroutine
(RSB) .............. ........... .............
Return on Overflow Clear
(RVC) .....................................
Return on Overflow Set
(RVS) .....................................
Save Registers (SAVE) ............
Coprocessor Operation
(no operands) (SPOP) ............
Coprocessor Operation
Read (SPOPRS, SPOPRD,
SPOPRT) ................................

3·100
3·101
3·102
3-103
3-104
3-105
3-106
3-107
3-108
3-109
3-110
3·111
3-112
3-113

3-114

Coprocessor Operation,
2-Address (SPOPS2,
SPOPD2, SPOPT2L ..............
Coprocessor Operation
Write (SPOPWS, SPOPWD,
SPOPWT) ...............................
String Copy (STRCPY) ... ........
String End (STREND) ............
Subtract (SUBB2,
SUBH2, SUBW2) ..................
Subtract, 3 Address
(SUBB3, SUBH3, SUBW3) ..
Swap (Interlocked)
(SW APBI, SW APHI,
SWAPWI) ..............................
Test (TSTB, TSTH, TSTW) ...
Exclusive Or (XORB2,
XORH2, XORW2) ................
Exclusive Or, 3 Address
(XORB3, XORH3,
XORW3) ................................
3.7.3 Instruction Set Summary by
Function .................................
3.7.4 Instruction Set Summary by
Mnemonic ...............................
3.7.5 Instruction Set Summary by
Opcode....................................

3-115

3-116
3-117
3-119
3-120
3-121

3-122
3-123
3-124

3-125
3-126
3-132
3-136

INSTRUCTION SET & ADDRESSING MODES
Data Types

3. INSTRUCTION SET
The WE 32100 Microprocessor has a powerful instruction set that includes the standard
data transfer, arithmetic, and logical operations for microprocessors, plus some unique
operating system operations. Its many program control instructions (branch, jump, return)
provide flexibility for altering the sequence in which instructions are executed. Some of
these instructions check the setting of the processor's condition flags before execution. For
operating systems, the processor has instructions to establish an environment that permits
other processes to take control of the processor. The special instructions dedicated to
operating system use are discussed in Chapter 4.
The microprocessor instructions are mnemonic-based assembly language statements.
However, programs may be written in C language and translated into assembly language
by its C compiler.
A mnemonic defines the operation an instruction performs. For most arithmetic or logical
operations, the mnemonic also defines one of the data types:
o byte

8-bit data

o halfword - 16-bit data
o word

- 32-bit data.

Some instructions perform operations on a bit field, a sequence of I to 32 bits contained in
a word, or on a block (or string) of data locations.

3.1 DATA TYPES
The data types supported by the WE 32100 Microprocessor instruction set are illustrated
on Figure 3-1 and are defined as:
byte - An 8-bit quantity that may appear at any address in memory. Its bits are numbered
from right to left starting with 0, the least significant bit (LSB), and ending with 7, the
most significant bit (MSB).
halfword - A 16-bit quantity that may appear at any address in memory divisible by 2. Its
bits are numbered from right to left starting with 0, the LSB, and ending with 15, the
MSB.
word - A 32-bit quantity that may appear at any address in memory divisible by 4. Its bits
are numbered from right to left starting with 0, the LSB, and ending with 31, the MSB.
Each of these types may be interpreted as a signed or unsigned quantity. A signed
quantity is represented in 2's complement form. Therefore, for a signed quantity, the MSB
indicates the sign of the quantity; 0 for a positive quantity and I for a negative quantity.
A bit field is a sequence of I to 32 bits contained in a base word. The field is specified by
the address of its base word, a bit offset, and a width. The bit offset ranges from 0 to 31

3-1

INSTRUCTION SET & ADDRESSING MODES
Data Types

7

BITS

0

Fi

MSB
LSB
A. BYTE OATA
BITS

81 7

15

:

~

I

MSB
B. HALFWORD DATA
BITS

31

24: 23

~

0

t
LSB

16: 15

0

8:7

l
t

MSB
C. WORD DATA

LSB

Figure 3-1.

Bit Order of Data

MSB

t

31

LSB
24 23

16 15

IX ••• x:X •••

I

r----

x : 0 1 1 1 1 0 1 1: 0 1 X.

r-

WIDTH

BASE WORD AT ADDRESS

Figure 3-2.

3-2

0

••

xl

~

a~

MSB

LSB

9

0

t

LEGEND:
BASEWORD ADDRESS = a
OFFSET = 6
WIDTH = 9

t

8 7

t

101 11 1011011

Bit Order in a Bit Field

INSTRUCTION SET & ADDRESSING MODES
Registers

and identifies the starting bit of the field. The offset count starts at the LSB of the base
word and corresponds to the number of the bit in the word. That bit becomes bit 0, the
LSB of the field. The width ranges from 0 to 31 and specifies the size of the field. Width
plus one is the number of bits in the field. The width is numbered from right to left in the
field and corresponds to the bit number of the field's MSB. Fields do not extend across
word boundaries. Fields wrap around from MSB to LSB at the word boundary. Figure
3-2 illustrates a bit field located at address a, with an offset of 6, and a width of 9. Notice
that the field contains 10 bits, one bit more than the width.
3.1.1 Sign and Zero Extension
All operations are performed only on 32-bit quantities even though an instruction may
specify a byte or halfword operand. The WE 32100 Microprocessor reads in the correct
number of bits for the operand and extends the data automatically to 32 bits. It uses sign
extension when reading signed data or halfwords and zero extension when reading
unsigned data or bytes (or bit fields that contain less than 32 bits). The data type of the
source operand determines how many bits are fetched and what type of extension is
applied. Bytes are treated as unsigned, while halfwords and words are considered signed.
The type of extension applied can be changed using the expanded-operand type mode as
described in 3.4.5 Expanded-Operand Type Mode. For sign extension, the value of the
MSB or sign bit of the data fills the high-order bits to form a 32-bit value. In zero
extension, zeros fill the high order bits. The microprocessor automatically extends a byte
or halfword to 32 bits before performing an operation. Figure 3-3 illustrates sign and zero
extension.
An arithmetic, logical, data transfer, or bit field operation always yields an intermediate
result that is 32 bits in length. If the result is to be stored in a register, the processor
writes all 32 bits to that register. The processor automatically strips any surplus highorder bits from a result when writing bytes or halfwords to memory.

3.2 REGISTERS
A processor register may contain the operand for an instruction or may be used when
computing an address of an operand. Therefore, most address modes, other than absolute,
immediate, or literal, reference a processor register. In general, any of the sixteen
processor registers may be used as an operand in all of the address modes. Table 3-1 lists
the registers and assigned functions.
General-purpose registers rO through r8 may be used for accumulation, addressing, or
temporary data storage. The remaining processor registers are special purpose and are
usually referenced with different names. Three of these registers are pointers to data
stored on an execution stack: the frame pointer (FP), register 9 (r9), the argument pointer
(AP), register 10 (riO), and the stack pointer (SP), register 12 (rI2). Function calls and
returns affect the AP, FP, and SP implicitly. The FP identifies the starting location of
local variables for the function, while the AP identifies the beginning of the set of
arguments passed to the function. The SP always points to the next available word
location on the stack. Note that the stack grows upward to higher memory addresses.

3-3

INSTRUCTION SET & ADDRESSING MODES
Registers

Table 3-1.

Register Set

12
13

Name
rO
r1
r2
r3
r4
r5
r6
r7
r8
FP
AP
PSW
SP
PCBP

Assembler
Syntax
%rO
%r1
%r2
%r3
%r4
%r5
%r6
%r7
%r8
%fp or %r9
%ap or %r10
%psw or %rll
%sp or %r12
%pcbp or %r13

14
15

ISP
PC

%isp or %r14
%pc or %r15

Register
0
1
2
3
4
5
6
7
8
9
10
11

Assigned Function
General-purpose (Note 1)
General-purpose (Note 1)
General-purpose (Note 1)
General-purpose
General-purpose
General-purpose
General-purpose
General-purpose
General-purpose
Frame pointer
Argument pointer
Processor status word (Note 2)
Stack pointer
Processor control block
pointer (Note 2)
Interrupt stack pointer (Note 2)
Program counter (Note 3)

Notes:
1. Block or string instructions may use this register as an implied argument
for indexing or addressing. Operating system instructions also use these
registers.
2. Privileged register. Writing to this register when the processor is not in
kernel execution level causes a privileged-register exception (see 4.2.1
Execution Privilege).
3. Registers 11 and 15 may not be used in some address modes (see 3.4
Address Modes).

Some of the registers have restrictions on usage in instructions. Because registers 11, 13,
and 14 (r11, r13, and r14) are privileged, these may be written only when kernel execution
level is in effect. Register 11, the processor status word (PSW), contains status
information about the current instruction and process. Register 13, the process control
block pointer (PCBP), identifies a block of status information and pointers for a process.
Register 14, the interrupt stack pointer (ISP), functions as a stack pointer for the interrupt
stack.
The last register is the program counter, register 15 (r15). This register and register 11
may not be referenced in some address modes (see 3.4 Address Modes). In addition, it is
referenced implicitly in all program-control instructions and for all function calls and
returns.

3-4

INSTRUCTION SET & ADDRESSING MODES
Registers

HALFWORD DATA

BYTE DATA

a

7

~

MSB

MSB
A. VALUE READ IN

31

G

a

81 7
1: 1X

0

0

31

S~

aX11

; < , - - - ;- - - ' - - - - - - '

81 7

16 1 15
0:

ox

0

0

• X1: ox

•

o

0

X11

B. AFTER SIGN EXTENSION

a

81 7
0: 1X

0

o

0

31

S~

X11

c.

Figure 3-3.

O:OX

0

o

0

X1: OX

0

•

0

X11

Extending Data to 32 Bits

16115

a

8 17

X: 1 a 1 100 11: 101 1 10

31
10 : :

BYTE 3

I DESCRIPTOR I
~

BYTE ---t>ji>'rE,..
B. OPERANO FORMAT

Figure 3-5.

BITS

General Instruction Format

INCREASING ADDRESS-+

o

710

rrrr! mmmm:

BYTE 0

71

8

31
15 16
1

23 24
.
BYTE 4
1

I

A. EMBEDDED WORD DATA

BITS
0

3

23

718

15 16
rrrr! mmmm:
BYTE 0
.
BYTE 1
1
B. EMBEDDED HALFWORD DATA

8ITS

Io rrrr! mmmm718
3

15

~BYTE DAT~
I

C. EMBEDDED BYTE

Figure 3-6.

I

I

LEGEND:

mmmm ADDRESS f1DDE (O-15)
rrrr = REGISTER (D-15)

Data Embedded in an Operand

3-7

INSTRUCTION SET & ADDRESSING MODES
Address Modes

In assembly language, the syntax of the operand defines the operand and its address mode.
Each address mode description in this section includes an example using a move instruction
(MOVB, MOVH, or MOVW) to be described later. Because each example includes two
operands, only the first operand demonstrates the address mode being described. The
second operand uses the register mode.
Table 3-2 lists the address modes and gives the syntax for each. The descriptions and the
table use the following notation:
Oxnnn

Hexadecimal number nnn, where n is a hexadecimal digit 0 to 9 or a to f (or A to
F); may also be written OXnnn

ap

Argument pointer (AP); contains the starting location on the stack of a list of
arguments for a function

expr

User-supplied expression that yields a byte, halfword, or word

fp

Frame pointer (FP); contains the starting location on the stack of local variables
for a function
Signed integer in the range -128 to +127 (j.e., _2 7 to +27-0

imm8

imm16 Signed integer in the range -32768 to +32767; Le., _2 15 to (+2 15 _1)
imm32 Signed integer in the range _2 31 to (+2 31 _1)
lit

Signed integer in the range -16 to +63

opnd

An operand that uses a mode other than the expanded-operand type

%rn

References a processor register; use the syntax shown in Table 3-1 for the desired
register

so

Short offset; an integer in the range 0 to 14

type

Data type: sbyte (for signed byte), byte or ubyte (for unsigned byte), half or shalf
(for signed halfword), uhalf (for unsigned halfword), word or sword (for signed
word), uword (for unsigned word); see 3.4.5 Expanded-Operand Type Mode for
more details.

In machine language, a descriptor defines all source or destination operands and occupies
one or more bytes in the instruction stream.
The first byte of the operand, called the descriptor byte, defines the address mode. (The
expanded-operand type mode uses two descriptor bytes and is discussed later in this
section.) Bytes that follow the descriptor byte contain any data required by the address
mode for that operand. Table 3-2 identifies the total bytes in memory required for each
mode.

3-8

INSTRUCTION SET & ADDRESSING MODES
Address Modes

Addressing Modes

Table 3-2.

Mode
Field
Absolute

Syntax

Mode
Absolute
Absolute deferred

$expr
15
7
*$expr
15
14
Displacement (from a register)
expr(%rn)
12 0-10,12-15

Byte displacement
Byte displacement
deferred
Halfword displacement
Halfword displacement
deferred
Word displacement
Word displacement
deferred
AP short offset
FP short offset
Byte immediate
Halfword immediate
Word immediate
Positive literal
Negative literal
Register
Register deferred
Expanded-operand
type

Register
Field

Total
Bytes

Notes

5
5

-

2

-

*expr(%rn)
expr(%rn)

13
10

0-10,12-15
0-10,12-15

2
3

*expr(%rn)
expr(%rn)

11
8

0-10,12-15
0-10,12-15

3
5

-

*expr(%rn)
9 0-10,12-15
so (%ap)
7
0-14
so (%fp)
0-14
6
Immediate
6
15
&imm8
&imm16
5
15
&imm32
4
15
0-3
0-15
& lit
15
0-15
&lit
Register
%rn
0-14
4
(%rn)
5 0-10,12-14
Special Mode

5
1
1

-

{type}opnd

14

0-14

-

1
1

2
3
5
1
1

2,3
2,3
2,3
2,3
2,3

1
1

1,3
1

2-6

4

Notes:
1. Mode field has special meaning if register field is 15; see absolute or
immediate mode.
2. Mode may not be used for a destination operand.
3. Mode may not be used if the instruction takes effective address of the
operand.
4. type overrides instruction type; type determines the operand type,
except that it does not determine the length for immediates or literals
or whether literals are signed or unsigned. opnd determines actual
address mode. For total bytes, add 1 to byte count for address mode
determined by opnd.

3-9

INSTRUCTION SET & ADDRESSING MODES
Address Modes

As described before, the descriptor byte has two 4-bit fields:
7

4

I mmmm

3 0
rrrr

The register field rrrr, bits 0 through 3, contains the number of a register, 0 through 15.
The mode field mmmm, bits 4 through 7, contains an address-mode number, 0 through 15.
Table 3-2 lists the value in the mode field and the possible values in the register field for
each address mode. If the register field contains 15, the mode field may be interpreted
differently.
In the following examples for the address modes, the first operand illustrates the mode
while the second operand uses the register mode. For assembly language programming,
values follow the C language conventions:
• Leading Ox or OX denotes a hexadecimal value
• Leading 0 followed by the digits 0 through 7 is octal
• Digits 0 through 9, but no leading zero is decimal.
The byte boxes illustrating the instruction stream in the following examples contain
hexadecimal values.

3.4.1 Absolute Address Modes
In this mode, an absolute address is embedded in the operand. This may be the address of
the operand or of a pointer.

Absolute
The operand is accessed by an absolute address computed from the expression expr.
Syntax: $expr
mmmm: 7
rrrr: 15
Total bytes: 5
Example: MOYB $Oxl00,%rO
87
7F
00
01
00
00
40

3-10

Opcode
First Operand

Second Operand

INSTRUCTION SET & ADDRESSING MODES
Byte Displacement

This instruction moves the byte at location 100 to register O(rO). %rO is the syntax for the
register mode. In the instruction stream, the four bytes that follow the descriptor byte
form the 32-bit absolute address of the operand. The bytes follow the order shown on
Figure 3-6 for word data.

Absolute Deferred
The operand is accessed through the absolute address of a pointer, a location in general
memory that contains the address of the operand. The absolute address of this pointer is
computed from the expression expr.
Syntax: *$expr
mmmm: 14
rrrr: 15
Total bytes: 5
Example: MOVB *$Ox2EOO,%rl
87
EF
00
2E
00
00
41

Opcode
First Operand

Second Operand

This example moves a byte from memory to register 1 (r1). However, it uses a pointer
(the word starting at location Ox2EOO) to locate the byte in memory. In the instruction
stream, the four bytes that follow the descriptor byte form the 32-bit absolute address of a
word location in memory. That location contains the address of the operand. The 32-bit
absolute address in the instruction follows the byte order shown on Figure 3-6 for word
data.

3.4.2 Displacement Modes
For these modes, a displacement contained in the operand added to a register forms the
address of the operand or a pointer to the operand. Sign-extension expands the
displacement of 32 bits before the addition occurs.

Byte Displacement
A byte displacement added to a register forms the address of the operand. The
displacement, computed from the expression expr, ranges from -128 to +127, and n ranges
from 0 to 10 and 12 to 15 (use the syntax given in Table 3-1).

3-11

INSTRUCTION SET & ADDRESSING MODES
Byte Displacement Deferred

Syntax: expr(%rn)
mmmm: 12
rrrr: 0 to 10, 12 to 15
Total bytes: 2
Example: MOYB 6(%rI),%rO
7
Opcode
Cl
; ] First Operand
06
40
Second Operand
This example moves a byte from memory to register O. This byte in memory is located by
adding the displacement 6 to register 1. The displacement is the byte that follows the
descriptor byte in the instruction stream. This displacement is sign extended and added to
the contents of the register 1. The sum is the address of the operand.

Byte Displacement Deferred
A byte displacement added to a register forms a pointer. The word location identified by
the pointer contains the address of the operand. The displacement computed from the
expression expr ranges from -128 to + 127, and n ranges from 0 to 10 and 12 to 15 (use
the syntax given in Table 3-1).
Syntax: *expr(%rn)
mmmm:13
rrrr: 0 to 10, 12 to 15
Total bytes: 2
Example: MOYB*Ox30(%r2),%r3
7. Opcode
;D2
] First Operand
30
43
Second Operand
This example adds the byte displacement Ox30 to the contents of register 2 (r2) to form
the starting address of a pointer in memory. The pointer is the address of a byte in
memory. After zero extension of the byte, the value is written to register 3 (r3). The
displacement is the byte that follows the descriptor byte in the instruction stream. This
byte is sign extended and added to the contents of register 2. The sum is the address of a
word location in memory that contains the address of the operand.

Halfword Displacement
A halfword displacement added to a register forms the address of the operand. The
displacement is computed from the expression expr and ranges from _215 to (+215_1.)

3-12

INSTRUCTION SET & ADDRESSING MODES
Halfword Displacement Deferred

Syntax: expr(%rn)
mmmm: 10
rrrr: 0 to 10, 12 to 15
Total bytes: 3
Example: MOVB Ox 11 0 I (%r2), %r8
87
A2
01
11
48

Opcode
First Operand

Second Operand

This example adds the halfword displacement OxllOI to the contents of register 2. The
result is the address of a byte in memory. This byte is written to register 8 after zero
extension. In the instruction stream, the halfword that follows the descriptor byte is the
displacement. This displacement is sign extended and added to the contents of register 2.
The sum is the address of the operand. The displacement stored in the instruction follows
the byte ordering shown on Figure 3-6 for halfword data.

Halfword Displacement Deferred
A halfword displacement added to a register n forms a pointer. The word location
identified by the pointer contains the address of the operand. The displacement computed
from the expression expr ranges from _is to (+is_l), and n ranges from 0 to 10 and 12
to 15 (use the syntax given in Table 3-1).
Syntax: *expr(%rn)
mmmm: 11
rrrr: 0 to 10, 12 to 15
Total bytes: 3
Example: MOVB *Ox200(%r2),%r6
87
B2
00
02
46

Opcode
First Operand

Second Operand

This instruction adds the halfword displacement Ox200 to the contents of register 2,
forming the address that locates a pointer in memory. The pointer locates a byte in
memory that is written to register 6 after zero extension. In the instruction stream, the
halfword that follows the descriptor byte is the displacement. This displacement is sign
extended and added to the contents of register 2. The sum is the address of a word
location in memory that contains the address of the operand. The displacement in the
instruction stream follows the byte order shown on Figure 3-6 for halfword data.

3-13

INSTRUCTION SET & ADDRESSING MODES
Word Displacement

Word Displacement
A word displacement added to a register forms the address of the operand. The
displacement computed from the expression expr ranges from _2 31 to (+il_l), and n
ranges from 0 to 10 and 12 to 15 (use the syntax given in Table 3- I).
Syntax: expr(%rn)
mmmm: 8
rrrr: 0 to 10, 12 to 15
Total bytes: 5
Example: MOVB Oxl12234(%r2),%r4
87
82
34
22

Opcode
First Operand

II

00
44

Second Operand

The word displacement Oxl12234 added to the contents of register 2 forms the address of a
byte. The byte is stored in register 4 (r4) after zero extension. In the instruction stream,
the byte that follows the descriptor byte is the displacement. This displacement is sign
extended and added to the contents of the register 2. The sum is the address of the
operand. The displacement stored in the instruction follows the byte ordering shown on
Figure 3-6 for word data.

Word Displacement Deferred
A word displacement added to a register forms the address of a pointer. The pointer is the
address of the operand in memory. The displacement computed from the expression
expr ranges from _2 31 to +2 31 _1, and n ranges from 0 to 10 and 12 to 15 (use the syntax
given in Table 3-1).

Syntax: *expr(%rn)
mmmm: 9
rrrr: 0 to 10, 12 to 15
Total bytes: 5

3-14

INSTRUCTION SET & ADDRESSING MODES
FP Short Offset

Example: MOVB *Ox20304050(%r2),%rO
87
92
50
40
30
20
40

Opcode
First Operand

Second Operand

The word displacement Ox20304050 added to the contents of register 2 forms an address of
a pointer in memory. That pointer identifies the location of a byte to be written to register
o after zero extension. In the instruction stream, the word that follows the descriptor byte
is the displacement. This displacement is sign extended and added to the contents of
register 2. The sum is the address of a word location in memory that contains the address
of the operand. The displacement in the instruction stream follows the byte order shown
on Figure 3-6 for word data.
AP Short Offset
This mode applies a short offset to the argument pointer (referenced as %ap) to locate an
argument to a function. The offset so ranges from 0 through 14 and is added to AP to
form the address of the argument.
Syntax: so(%ap)
mmmm: 7
rrrr: 0 through 14 (see text that follows)
Total bytes: 1
Example: MOVW 4(%ap),%r3

§§
4
74
43

Opcode
First Operand
Second Operand

The offset 4 added to the contents of AP locates a word that is written to register 3. In the
instruction stream, the 4-bit register field serves as the offset (a literal ranging from 0
through 14). This offset is sign extended and added to the contents of AP to locate a word,
or argument, on the stack.
FP Short Offset
This mode applies a short offset to the frame pointer, referenced as %fp, to locate a local
variable for a function. The offset so ranges from 0 through 14 and is added to FP to form
the address of the variable.

3-15

INSTRUCTION SET & ADDRESSING MODES
Immediate Modes

Syntax: so (%fp)
mmmm: 6
rrrr: 0 through 14 (see text that follows)
Total bytes: I
Example: MOVW 12(%fp),%rO

§E
4
6C
40

Opcode
First Operand
Second Operand

The offset 12 added to the contents of FP locates a word (a local variable) that is written
to register O. In the instruction stream, the 4-bit register field serves as the offset (a literal
ranging from 0 through 14). This offset is sign extended and added to the contents of FP.

3.4.3 Immediate Modes
For these modes, the instruction stream contains the operand data. The type of the
mnemonic does not affect the width of an operand that uses these address modes.

Byte Immediate
The operand is the signed 8-bit immediate value imm8 that ranges from -128 to +127.

Note: This address mode may not be used as a destination or for an effective address.
Either usage causes an illegal-operand exception.
Syntax: &imm8
mmmm: 6
rrrr: 15

Total bytes: 2

1

Example: MOVW &40,%r6
4
6F
28
46

Opcode
First Operand
Second Operand

The byte value 40 replaces the contents of register 6. The mnemonic specifies a word
operation, but the immediate value remains a byte. In the instruction stream, the byte that
follows the descriptor byte contains an 8-bit immediate value that ranges from -128 to
+127.

3-16

INSTRUCTION SET & ADDRESSING MODES
Word Immediate

Halfword Immediate
The operand is the signed 16-bit immediate value imm16 that ranges from

(+i 5-1).

_i 5 to

Note: This address mode may not be used as a destination or for an effective address.
Either usage causes an illegal-operand exception.
Syntax: &imm16
mmmm: 5
rrrr: 15
Total bytes: 3
Example: MOVW &OxI234,%r2
84
5F
34
12
42

Opcode
First Operand

Second Operand

Here, the halfword value Ox1234 replaces the contents of register 2. In the instruction
stream, the halfword that follows the descriptor byte contains a 16-bit immediate value
that ranges from _2 15 to (+2 15 _1). This immediate value is stored in the byte order shown
on Figure 3-6 for halfword data.

Word Immediate
The operand is the signed 32-bit immediate value imm32 that ranges from _2 31 to
(+2 31 _1).
Note: This address mode may not be used as a destination or for an effective address.
Either usage causes an illegal-operand exception.
Syntax: &imm32
mmmm: 4
rrrr: 15
Total bytes: 5

3-17

INSTRUCTION SET & ADDRESSING MODES
Positive Literal

Example: MOVW &OxI2345678,%r3
84
4F
78
56
34
12

Opcode
First Operand

----:0-

Second Operand

In this example, the word value Oxl2345678 replaces the contents of register 3. In the
instruction stream, the word that follows the descriptor byte contains a 32-bit immediate
value that ranges from _2 31 to +il_l. This immediate value is stored in the byte order
shown on Figure 3-6 for word data.

Positive Literal
The operand is the unsigned 6-bit literal value lit that ranges from 0 to 63.
Note: This address mode may not be used as a destination or for an effective address.
Either usage causes an illegal-operand exception.
Syntax: & lit
mmmm: 0 to 3
rrrr: 0 to 15
Total bytes: I
Example: MOVB &4,%r4

~
7
04
44

Opcode
First Operand
Second Operand

Here, the positive literal 4 replaces the contents of register 4. Zeros fill the high-order bits
in the register. In the instruction stream, the descriptor byte provides an unsigned 6-bit
literal that ranges from 0 to 63. It is formed by concatenating the 4-bit register (rrrr) field
with the two low-order bits of the mode (mmmm) field; i.e., bits 0 through 5 of the
descriptor byte form the literal.

Negative Literal
The operand is the signed 8-bit literal value lit that ranges from -I to -16.
Note: This address mode may not be used as a destination or for an effective address.
Either usage causes an illegal-operand exception.

3-18

INSTRUCTION SET & ADDRESSING MODES
Register Mode Deferred

Syntax: &lit
mmmm: 15
rrrr: 0 to 15
Total bytes:
Example: MOVB &-I,%rO

§8
7
FF
40

Opcode
First Operand
Second Operand

In the instruction stream, the descriptor byte provides a signed 8-bit literal that ranges
from -I to -16. It is formed by concatenating the 4-bit register (rrrr) field with the 4-bit
mode (mmmm) field; i.e., the 8-bit descriptor byte forms the literal.

3.4.4 Register Modes
These modes use the contents of a register as the operand or as a pointer to the operand.

Register Mode
In this mode, the register n, which ranges from 0 to 14, is the operand.
Note: This mode may not be used if the opcode takes the effective address of the operand.
Syntax: %rn
mmmm: 4
rrrr: 0 to 14
Total bytes:
Example: MOVB %rO,%ap

§§
7
40
4A

Opcode
First Operand
Second Operand

This example moves a byte from one register to another. It reads bits 0 through 7 of
register 0, extends a zero through 32 bits, and writes the result to register 10, the argument
pointer. In the instruction stream, the register specified in the register field is the operand.

Register Mode Deferred
The register n, which ranges from 0 to 10 and 12 to 14, contains a pointer to the operand.

3-19

INSTRUCTION SET & ADDRESSING MODES
Expanded-Operand Type Mode

Syntax: (%rn)
mmmm: 5
rrrr: to 10, 12 to 14
Total bytes: 1

°

Example: MOVH (%r2),%r1

§§
6
52
41

Opcode
First Operand
Second Operand

Here, register 2 contains the address of a halfword that is read. The halfword is sign
extended through 32 bits, and the result is written to register 1. In the instruction stream,
the register specified in the register field contains a pointer to a word location in memory
that is the operand.

3.4.5 Expanded-Operand Type Mode
Normally, the opcode controls the type of all operands for the instruction. This mode
changes the type of an operand and those that follow it in an instruction.

Note: The expanded-operand type mode does not affect the length of immediate operands,
but does affect whether they are treated as signed or unsigned. The expanded-operand
mode does not affect the treatment of literals.
In assembly language, the syntax of this mode is
{type}opnd

where opnd is an operand descriptor that uses any address mode other than the expandedoperand type mode.
When the expanded-operand type mode is used, type overrides the type for this operand,
except as noted above, and opnd becomes the real address mode for the operand. The new
type remains in effect for the operands that follow in the instruction unless another
expanded-operand mode overrides it. Table 3-3 lists the syntax for type.
This mode requires two descriptor bytes (see Figure 3-7). The first byte identifies the
expanded-operand mode and the new type, while the second is the descriptor byte for the
address mode.
The type field ttt! contains the value of the new type (see Table 3-3). The second byte
contains the mode field (mmmm) and the register field (rrrr) for the address mode. This
byte is the descriptor byte for the new address mode.
For example, the following instruction converts a signed byte into an unsigned halfword:
MOVB {sbyte}%rO,{uhalf}4(%r1)

3-20

INSTRUCTION SET & ADDRESSING MODES
Expanded-Operand Type Mode

The first operand's real mode is register, the second operand is byte displacement. The
instruction reads bits 0 through 7 from register 0, extends the sign through 32 bits, and
writes an unsigned halfword. In the instruction stream, the bytes contain the following:
Opcode
First Operand

87
E7

40
Second Operand

E2
Cl

04
Note: Expanded-operand type mode is illegal with coprocessor instructions with operands
CALL, SAVE, RESTORE, SWAP INTERLOCKED, PUSHW, PUSHAW, POPW, and
JSB instructions and will generate an illegal operand fault.

Table 3-3.

Options for type in Expanded-Operand Mode

Type

UU Field
(See Note)
7
6
4

Syntax
sbyte
half or shalf
word or sword
byte or ubyte
uhalf
uword

Signed byte
Signed halfword
Signed word
Unsigned byte
Unsigned halfword
Unsigned word

3

2
0

Note: Types are not defined for the values 1, 5, and 8
through 14; using these generates a reserved-data-type
exception.

~ REAL ADDRESS MDDE

-----e4

I

C:
:.s-

I

7

3

D7

3

0

Immmm! rrrr 1 1110 ! tttt 1

0-4 DATA BYTES-e>l

I

I

_

INCREASING ADDRESS
LEGEND

mmmm=
rrrr =

ADDRESS MODE (0-13, 15)
REGISTER (0-15)

tttt = NEW TYPE

Figure 3-7.

Expanded-Operand Type Descriptor

3-21

INSTRUCTION SET & ADDRESSING MODES
Condition Flags

3.5 CONDITION FLAGS
Bits 21 to 18 of the processor status word (PSW) contain four condition flags (N, Z, V,
and C) that are set by most instructions. The order is shown on Figure 3-8. The
conditional program-control instructions check one or more of these flags before executing
the branch, jump, or return. In general, these flags reflect the result of the most recent
instruction that affects them. Most instructions set the flags according to standard criteria.
Before defining that criteria, the following terms are defined:
• Result refers to the internal result of the operation as if it were performed in an
infinite-precision machine. The microprocessor operates on 32-bit data internally and
uses a 33-bit space for the internal result. Bytes and halfwords read in are extended to
32 bits before the operation. The destination operand determines the type (i.e., signed or
unsigned, and size: byte, halfword, or word) of this result.
• Output value refers to the data written to the destination location. The size of this data,
8, 16, or 32 bits, corresponds to the data type of the destination operand: byte, halfword,
or word, respectively.

The following conditions cause the appropriate flag bit to be altered:
N

Negative (PSW bit 21) - Logical instructions change N to the setting of the output
value of the MSB: bit 31 for words, bit 15 for halfwords, and bit 7 for bytes. For all
other instructions, N is set if the sign of the result is negative. If truncation occurs,
the N flag may be set even though the sign bit of the output value is zero. Zero is
considered positive.

Z

Zero (PSW bit 20) - Logical instructions set Z if the output value is zero. For all
other instructions Z is set if the result is equal to zero. If truncation occurs, the Z flag
may not be set even though all bits of the output value are zero.

V

Overflow (PSW bit 19) - For instructions with a signed destination, V is set if the sign
bit of the output value is different from any truncated bit of the result. For
instructions with an unsigned destination, V is set if any truncated bit is a 1. The
arithmetic left shift operation sets the V bit only if a truncation error occurs. Bit,
compare, and test instructions always reset V.

31

C

21

20

19

18

1 -,---,I
z I,----,-v

' s - ' -N:

::J

0

1

---,---,>C

/

PSW

Figure 3-8.

3-22

Condition Flags

INSTRUCTION SET & ADDRESSING MODES
Data Transfer Instructions

C

Carry/Borrow (PSW bit 18) - Logical instructions clear this bit. For all other
instructions, the type of the result determines the state of the C bit. C is set if a carry
occurs into the 33rd bit for word operations, into the 17th bit for halfword operations,
or into the 9th bit for byte operations. The C bit is set if a borrow occurs from these
bits for subtract, negate, and decrement. For example, consider A minus B where A
and B are unsigned. If A ~ B after both are extended to 32 bits, then C is cleared.
Otherwise, the C flag is set.

Note: If a memory-write fault occurs, the flags are set as if the instruction was completed
normally.
The instruction descriptions later in this chapter include the effect that each instruction has
on the condition flags.

3.6 FUNCTIONAL GROUPS
The WE 32100 Microprocessor instruction set may be separated into six functional groups:
data transfer instructions, arithmetic instructions, logical instructions, program control
instructions, coprocessor instructions, and stack and miscellaneous instructions. This
section contains a description of each group, along with an instruction listing of each group.
The conditions column in the instruction listing refers to the condition flag code assignment
cases listed in Table 3-10. (For more details of individual instructions see
3.7 INSTRUCTION SET LISTINGS.)

3.6.1 Data Transfer Instructions
These instructions transfer data to and from registers and memory. Most of them have
three types (indicated by the last character of the mnemonic): byte (B), halfword (H),
and word (W). A mnemonic's type determines the type of each operand in the instruction,
unless the expanded-operand type mode changes an operand's type. The type of the
destination operand (dst) determines how the condition flags are set (see 3.5 CONDITION
FLAGS). The instructions have a read-only source operand (src) and a read/write
destination operand.

3-23

INSTRUCTION SET & ADDRESSING MODES
Data Transfer Instructions

Table 3-4.

Data Transfer Instruction Group

Instruction
Move:
Move byte
Move halfword
Move word
Move address (word)
Move complemented byte
Move complemented halfword
Move complemented word
Move negated byte
Move negated halfword
Move negated word
Move version number
Swap (Interlocked):
Swap byte interlocked
Swap halfword interlocked
Swap word interlocked
Block Operations:
Move block of words
Field Operations:
Extract field byte
Extract field halfword
Extract field word
Insert field byte
Insert field halfword
Insert field word
String Operations:
String copy
String end

*

3-24

Conditions *

Mnemonic

Opcode

MOVB
MOVH
MOVW
MOVAW
MCOMB
MCOMH
MCOMW
MNEGB
MNEGH
MNEGW
MVERNO

Ox87
Ox86
Ox84
Ox04
Ox8B
Ox8A
Ox88
Ox8F
Ox8E
Ox8C
Ox3009

SWAPBI
SWAPHI
SWAPWI

OxlF
OxlE
OxiC

Case I

MOVBLW

Ox30l9

Unchanged

EXTFB
EXTFH
EXTFW
INSFB
INSFH
INSFW

OxCF
OxCE
OxCC
OxCB
OxCA
OxC8

Case I

STRCPY
STREND

Ox3035
Ox30lF

Unchanged

Case I

Case 2
Unchanged

Refer to Table 3-10 for condition flag code assignments.

INSTRUCTION SET & ADDRESSING MODES
Arithmetic Instructions

3.6.2 Arithmetic Instructions
Arithmetic instructions perform arithmetic operations on data in registers and memory.
Most of these instructions have three types (specified by the last character of the
mnemonic): byte (B), halfword (R), and word (W). This type specification applies to
each operand in the instruction, unless the expanded-operand type mode changes an
operand's type. The type of the destination operand (dst) determines how the condition
flags are set (see 3.5 CONDITION FLAGS).
Many arithmetic operations are available as two· or three-address instructions. A twoaddress instruction has a read-only source operand (src) and a read/write destination
operand. Three-address instructions have two read-only source operands (src1. src2) and a
write-only destination operand. A few instructions also have a read-only count operand
(count).

If the result of an arithmetic operation is too large to be represented in 32 bits, the highorder bits are truncated and the processor issues an integer-overflow exception.

Table 3-5.

Arithmetic Instruction Group

Instruction
Add:
Add byte
Add halfword
Add word
Add byte, 3-address
Add halfword, 3-address
Add word, 3-address
Subtract:
Subtract byte
Subtract halfword
Subtract word
Subtract byte, 3-address
Subtract halfword, 3-address
Subtract word, 3-address
Increment:
Increment byte
Increment halfword
Increment word
Decrement:
Decrement byte
Decrement halfword
Decrement word

Mnemonic

Opcode

ADDB2
ADDH2
ADDW2
ADDB3
ADDH3
ADDW3

Ox9F
Ox9E
Ox9C
OxDF
OxDE
OxDC

SUBB2
SUBH2
SUBW2
SUBB3
SUBH3
SUBW3

OxBF
OxBE
OxBC
OxFF
OxFE
OxFC

INCB
INCH
INCW

Ox93
Ox92
Ox90

DECB
DECH
DECW

Ox97
Ox96
Ox94

Conditions*

Case 2

* Refer to Table 3-10 for condition flag code assignments.

3-25

INSTRUCTION SET & ADDRESSING MODES
Logical Instructions

Table 3-5.

Arithmetic Instruction Group (Continued)

Instruction
Multiply:
Multiply byte
Multiply halfword
Multiply word
Multiply byte, 3-address
Multiply halfword, 3-address
Multiply word, 3-address
Divide:
Divide byte
Divide halfword
Divide word
Divide byte, 3-address
Divide halfword, 3-address
Divide word, 3-address
Modulo:
Modulo byte
Modulo halfword
Modulo word
Modulo byte, 3-address
Modulo halfword, 3-address
Modulo word, 3-address
Arithmetic Shift:
Arithmetic left shift word
Arithmetic right shift byte
Arithmetic right shift halfword
Arithmetic right shift word

*

Mnemonic

Opcode

MULB2
MULH2
MULW2
MULB3
MULH3
MULW3

OxAB
OxAA
OxA8
OxEB
OxEA
OxE8

DIVB2
DIVH2
DIVW2
DIVB3
DIVH3
DIVW3

OxAF
OxAE
OxAC
OxEF
OxEE
OxEC

MODB2
MODH2
MODW2
MODB3
MODH3
MODW3

OxA7
OxA6
OxA4
OxE7
OxE6
OxE4

ALSW3
ARSB3
ARSH3
ARSW3

OxCO
OxC7
OxC6
OxC4

Conditions*

Case 3

Case 4

Case 3

Case 4

Case 3

Case 4
Case 5
Case 3

Refer to Table 3-10 for condition flag code assignments.

3.6.3 Logical Instructions
Logical instructions perform logical operations on data in registers and memory. Most of
these instructions have three types (specified by the last character of the mnemonic):
byte (B), halfword (H), and word (W). A mnemonic's type determines the type of each
operand in the instruction, unless the expanded-operand type mode changes an operand's
type. The type of the destination operand (dst) determines how the condition flags are set
(see 3.5 CONDITION FLAGS).
Many logical operations are available as two- or three-address instructions. A two-address
instruction has a read-only source operand (src) and a read/write destination operand
(dst). Three-address instructions have two read-only source operands (srcJ. src2) and a
write-only destination operand. A few instructions have a read-only count operand (count).

3-26

INSTRUCTION SET & ADDRESSING MODES
Logical Instructions

Table 3-6.
Instruction
AND:
AND byte
AND halfword
AND word
AND byte, 3-address
AND halfword, 3-address
AND word, 3-address
Exclusive OR (XOR):
Exclusive OR byte
Exclusive OR halfword
Exclusive OR word
Exclusive OR byte, 3-address
Exclusive OR halfword, 3-address
Exclusive OR word, 3-address
OR:
OR byte
OR halfword
OR word
OR byte, 3-address
OR halfword, 3-address
OR word, 3-address
Compare or Test:
Compare byte
Compare halfword
Compare word
Test byte
Test halfword
Test word
Bit test byte
Bit test halfword
Bit test word
Clear:
Clear byte
Clear halfword
Clear word
Rotate or Logical Shift:
Rotate word
Logical left shift byte
Logical left shift halfword
Logical left shift word
Logical right shift word

*

Logical Group
Mnemonic

Opcode

ANDB2
ANDH2
ANDW2
ANDB3
ANDH3
ANDW3

OxBB
OxBA
OxB8
OxFB
OxFA
OxF8

XORB2
XORH2
XORW2
XORB3
XORH3
XORW3

OxB7
OxB6
OxB4
OxF7
OxF6
OxF4

ORB2
ORH2
ORW2
ORB3
ORH2
ORW3

OxB3
OxB2
OxBO
OxF3
OxF2
OxFO

CMPB
CMPH
CMPW
TSTB
TSTH
TSTW
BITB
BITH
BITW

Ox3F
Ox3E
Ox3C
Ox2B
Ox2A
Ox28
Ox3B
Ox3A
Ox38

CLRB
CLRH
CLRW

Ox83
Ox82
Ox80

ROTW
LLSB3
LLSH3
LLSW3
LRSW3

OxD8
OxD3
OxD2
OxDO
OxD4

Conditions*

Case I

Case 2

Case 6

Case 1

Case 2

Case 1

Refer to Table 3-10 for condition flag code assignments.

3-27

INSTRUCTION SET & ADDRESSING MODES
Program Control Instructions

3.6.4 Program Control Instructions
Program control instructions change the program sequence, but generally do not alter the
condition flags.
Branch instructions have two types specified by the last character of the mnemonic: byte
displacement (B) and halfword displacement (H). A mnemonic's type determines if an
8- or a l6-bit displacement is embedded in the instruction. This displacement (disp8.
disp 16) is read, its sign is extended through 32 bits, and the result is added to the program
counter (PC) to compute the target address. Jump instructions have a read-only, 32-bit
destination (dst) operand that replaces the contents of the PC.
Jump instructions are always unconditional, but both conditional and unconditional branch
and return instructions are provided. Unconditional transfers change the contents of the
PC to the value specified. Conditional transfers first examine the status of the processor's
condition flags to determine if the transfer should be executed.
Subroutine and procedure-call (function) transfer instructions save or restore registers so
execution can transfer to the subroutine or function and then return to the original
program sequence.
Subroutine Transfer. A subroutine transfer is different from a normal transfer. Before
transferring to a subroutine, it is necessary to save the address of the next instruction.
Branch, jump, and return instructions for subroutines always implicitly affect the stack
pointer (SP). For subroutines, branch and jump save the address of the next instruction on
the stack at the location identified by the SP, increment the SP by 4, and then alter the
PC. Return from subroutine decrements the SP by 4, retrieves the saved address from the
stack, and writes it to the PC.
Procedure Transfer. For procedure transfers it is necessary to save other registers. These
instructions establish the environment for a function in a high-level language. Call and
save instructions automatically save the calling function's pointers, set up pointers to the
new function's environment, call the function, and save registers for local variables.
Restore and return instructions remove that environment and return to the calling function.
A stack frame provides reserved space, including a register-save area, for each function.
The register-save area stores the calling function's FP, AP, PC, and registers 3 through 8
(r3 through r8), if requested. Saving r3 through r8 gives the new function space for up to
six register variables. The SP is not saved because its value is always implicit.
All function calls have a fixed-size register-save area, even though some of it may not be
used. Save and restore control how many of the six user registers r3 through r8 will be
saved and restored. A return from a function retrieves the saved pointers and registers to
restore the original function's environment.

3-28

INSTRUCTION SET & ADDRESSING MODES
Program Control Instructions

Table 3-7.

Program Control Instructions

Instruction
Unconditional Transfer:
Branch with byte (8-bit) displacement
Branch with halfword (16-bit) displacement
Jump
Conditional Transfers:
Branch on carry clear byte
Branch on carry clear halfword
Branch on carry set byte
Branch on carry set halfword
Branch on overflow clear, byte displacement
Branch on overflow clear, halfword displacement
Branch on overflow set, byte displacement
Branch on overflow set, halfword displacement
Branch on equal byte (duplicate)
Branch on equal byte
Branch on equal halfword (duplicate)
Branch on equal halfword
Branch on not equal byte (duplicate)
Branch on not equal byte
Branch on not equal halfword (duplicate)
Branch on not equal halfword
Branch on less than byte (signed)
Branch on less than halfword (signed)
Branch on less than byte (unsigned)
Branch on less than halfword (unsigned)
Branch on less than or equal byte (signed)
Branch on less than or equal halfword (signed)
Branch on less than or equal byte (unsigned)
Branch on less than or equal halfword (unsigned)
Branch on greater than byte (signed)
Branch on greater than halfword (signed)
Branch on greater than byte (unsigned)
Branch on greater than halfword (unsigned)
Branch on greater than or equal byte (signed)
Branch on greater than or equal halfword (signed)
Branch on greater than or equal byte (unsigned)
Branch on greater than or equal halfword (unsigned)
Return on carry clear
Return on carry set

Mnemonic

Opcode

BRB
BRH
JMP

Ox7B
Ox7A
Ox24

BCCB
BCCH
BCSB
BCSH
BVCB
BVCH
BVSB
BVSH
BEB
BEB
BEH
BEH
BNEB
BNEB
BNEH
BNEH
BLB
BLH
BLUB
BLUH
BLEB
BLEH
BLEUB
BLEUH
BGB
BGH
BGUB
BGUH
BGEB
BGEH
BGEUB
BGEUH
RCC
RCS

Ox53*
Ox52*
Ox5B*
Ox5A*
Ox63
Ox62
Ox6B
Ox6A
Ox6F
Ox7F
Ox6E
Ox7E
Ox67
Ox77
Ox66
Ox76
Ox4B
Ox4A
Ox5B*
Ox5A*
Ox4F
Ox4E
Ox5F
Ox5E
Ox47
Ox46
Ox57
Ox56
Ox43
Ox42
Ox53*
Ox52*
Ox50*
Ox58*

Conditions

Unchanged

* Indicates that opcode matches another instruction but operation is the same.

3-29

INSTRUCTION SET & ADDRESSING MODES
Program Control Instructions

Table 3-7.

Program Control Instructions (Continued)

Instruction
Conditional Transfers (Continued):
Return on overflow clear
Return on overflow set
Return on equal (unsigned)
Return on equal (signed)
Return on not equal (unsigned)
Return on not equal (signed)
Return on less than (signed)
Return on less than (unsigned)
Return on less than or equal (signed)
Return on less than or equal (unsigned)
Return on greater than (signed)
Return on greater than (unsigned)
Return on greater than or equal (signed)
Return on greater than or equal (unsigned)
Subroutine Transfer:
Branch to subroutine, byte displacement
Branch to subroutine, halfword displacement
Jump to subroutine
Return from subroutine
Procedure Transfer:
Save registers
Restore registers
Call procedure
Return from procedure

Mnemonic

Opcode

RVC
RVS
REQLU
REQL
RNEQU
RNEQ
RLSS
RLSSU
RLEQ
RLEQU
RGTR
RGTRU
RGEQ
RGEQU

Ox60
Ox68
Ox6C
Ox7C
Ox64
Ox74
Ox48
Ox58*
Ox4C
Ox5C
Ox44
Ox54
Ox40
Ox50*

BSBB
BSBH
JSB
RSB

Ox37
Ox36
Ox34
Ox78

SAVE
RESTORE
CALL
RET

OxiO
OxI8
Ox2C
Ox08

Conditions

Unchanged

I

* Indicates that opcode matches another instruction but operation is the same.
Program control instructions explicitly manipulate four registers:

3-30

1.

PC - The call instruction saves the old PC as the return address (RA) and sets PC to
the first executable instruction of the function being called. The return instruction
restores PC to the RA (the next executable instruction of the calling function).

2.

SP - These instructions adjust SP automatically to point to the top of the stack
whenever they store or retrieve items.

3.

FP - The save instruction sets FP to the address just above the saved registers. The
FP accesses a region on the stack that stores temporary (or automatic) variables for
the function.

4.

AP - The call instruction adjusts AP to the beginning of a list of arguments for the
function.

INSTRUCTION SET & ADDRESSING MODES
Program Control Instructions

On a function call, the calling function contains a call instruction; the save instruction
should be the first statement of the called function. For a return, a restore and a return
appear in the function being exited.
Figure 3-9 shows the stack after the CALL-SAVE sequence:
PUSHWargl
PUSHWarg2
PUSHWarg3
CALL -(3*4) (%sp),funcl

/*push three arguments* /

/*call function*/
/*other instructions */

funcl:

SAVE %r3

/*save r3 through r8 */

First, three arguments are pushed onto the stack; each push increments SP. Then CALL
automatically saves the old pointers. It uses its first operand to set AP to the beginning of
the three arguments and its second operand to call the function. Next, SAVE, the first
statement in the function, is executed, automatically saving registers r3 through r8. It also
adjusts SP and FP for each push.

SP, FP_
(FP-4)

r8

(FP-8)

r7

(FP-12)

r6

(FP-16)

r5

(FP-20)

r4

(FP-24)

r3

(FP-28)

OLD FP

(FP-32)
(FP-36)

OLD AP
RA (OLD PC)
arg3
arg2

AP_

Figure 3-9.

arg1

T
REGISTER
SAVE AREA

1
t

INCREASING
ADDRESS

Stack After CALL-SAVE Sequence

3-31

INSTRUCTION SET & ADDRESSING MODES
Coprocessor Instructions
To return to the original sequence, the function funel contains the following instructions:
funcI:

SAVE %r3

I*save r3 through r8*1
I*other instructions*1

RESTORE %r3
RET

I*restore r3 through r8 *1
I*return to main function*1

The restore instruction retrieves registers r8 through r3 from the stack. It must have the
same operand as the original SA VE; otherwise, the return (RET) cannot restore the
correct AP and PC. Both instructions decrement SP as they pop the register contents from
the stack.

3.6.5 Coprocessor Instructions
These instructions implement the interface with coprocessors. All coprocessor instructions
have an 8-bit opcode followed by one word. This word is transmitted on the data bus and
interpreted by the coprocessor. The word is not used by the CPU. If no coprocessor
responds to the transmitted word, an external memory fault occurs.
After the word following the opcode is transmitted, the source operands, if any, are fetched
from memory. The CPU then waits until the "coprocessor done" signal is asserted, after
which the CPU attempts to read a word. If this access is faulted, an external memory
fault occurs. If this access is not faulted, bits 18 through 21 of the word are copied into
bits 18 through 21 (condition flags) of the PSW. The resulting operand, if any, is then
written to memory.
Coprocessor instructions can have from zero to two operands. The operands may be of
three data types (specified by the last character of the mnemonic): single-word (S),
double-word (D), and triple-word (T). All operands must start on an address evenly
divisible by four (a word boundary)'

3.6.6 Stack and Miscellaneous Instructions
The stack instructions are used to manipulate the stack. The push and pop instructions
always process a word and alter the SP. They have a read-only source operand src or a
write-only destination operand dst.
Miscellaneous instructions include those that alter the machine state or have an effect on
the cache memory. The breakpoint instruction causes a breakpoint-trap exception.
Control transfers to the operating system for the appropriate exception handler. The NOP
instructions come in three lengths: 1, 2, or 3 bytes. If an instruction, other than a
conditional transfer, reads the PSW, the 'assembler m32as inserts a NOP before that
instruction. This allows time for the PSW codes to settle before the new instruction tries
to access them. Cache flush makes the instruction cache invalid.

3-32

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Listings

Table 3-8.
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor

Coprocessor Instructions

Instruction
operation
operation read single
operation double
operation triple
operation single 2-address
operation double 2-address
operation triple 2-address
operation write single
operation write double
operation write triple

Mnemonic
SPOP
SPOPRS
SPOPRD
SPOPRT
SPOPS2
SPOPD2
SPOPT2
SPOPWS
SPOPWD
SPOPWT

Opcode
Ox32
Ox22
Ox02
Ox06
Ox23
Ox03
Ox07
Ox33
Ox13
Ox17

Conditions*

Case 10

* Refer to Table 3-10 for condition flag code assignments.
Table 3-9.

Stack and Miscellaneous Instructions

Instruction
Stack Operations:
Push address word
Push word
Pop word
Miscellaneous:
No operation, 1 byte
No operation, 2 byte
No operation, 3 byte
Breakpoint trap
Cache flush
Extended opcode

*

Mnemonic

Opcode

Conditions*

PUS HAW
PUSHW
POPW

OxEO
OxAO
Ox20

Case 1

NOP
NOP2
NOP3
BPT
CFLUSH
EXTOP

Ox70
Ox73
Ox72
Ox2E
Ox27
Ox14

Unchanged

Refer to Table 3-10 for condition flag code assignments.

3.7 INSTRUCTION SET LISTINGS
Section 3.7.2 Instruction Set Descriptions presents descriptions of each member of the
instruction set for the WE 32100 Microprocessor. The descriptions are in alphabetical
order, and any instructions that operate on more than one type of operand, byte, halfword,
or word are listed on the same page. (For quick reference to the instructions by function,
mnemonic, or opcode see Sections 3.7.3 Instruction Set Sumary by Fuction,
3.7.4 Instruction Set Summary by Mnemoic, and 3.7.5 Instruction Set Summary by
Opcode.)

3-33

INSTRUCTION SET & ADDRESSING MODES
Notation

3.7.1 Notation
Each instruction description contains several parts: assembler syntax, opcode operation,
address modes, condition flags, exceptions, examples, and notes (optionaL).
Assembler Syntax. Presents the assembly language syntax for the instruction, including
any required spacing and punctuation. The user-specified elements appear in italics. All
operands must appear in the order shown. If an instruction has byte, halfword, and word
forms, all three forms are presented.
The syntax uses the following symbols to denote operands that may be written in the
address modes shown in Table 3-2: count, dst, offset, src, width. Program control
instructions use disp8 or disp16 as a displacement operand. The operand does not use an
address mode, but is written as an 8- or 16-bit literal.
Opcodes. Lists each opcode with the appropriate mnemonic and function.
Operation. Describes the operation performed. The description generally uses C language
syntax and the operators and symbols shown in Table 3-11.
Address Modes. Identifies the valid address modes for each operand. Refer to Table 3-2
for address mode syntax and to Table 3-1 for the syntax for referencing registers.
Condition Flags. Identifies the effect of the instruction on each of the condition flags.
Exceptions. Identifies any error conditions that may result in illegal operands, opcodes, or
operations.
Examples. Presents examples of the instruction written in assembly language. In some
cases, it will give the contents of registers before and after execution. Register bytes are
read from right to left and their contents are given as hexadecimal values.
Notes (Optional). Explains other parts of the description when necessary.

Table 3-10. Condition Flag Code Assignments
Condition Flags
Case

3-34

Special Conditions·
N(Negative)

Z(Zero)

1

MSB of dst

1 if dst = 0

2

1 if result < 0

1 if result = 0

Cy
x==y
x!=y
+-

AP
count
dst
FP
PC
PSW
SEXT(x)
SP
*(--Sp)
* (SP++)
src
Oxn
/*comment*/
{opera tion}

Assembly Language Operators and Symbols

Description
Indirection; value pointed to by x
Address of x
Not x
Increment x
Decrement x
Complement x
Negate x; form two's complement of x
Add y to x
Subtract y from x
Multiply x by y
Divide y into x
Modulo x and y (remainder of x/y)
Bitwise AND x and y
Bitwise inclusive OR x and y
Bitwise exclusive OR (XOR) x and y
Shift x to the left y bits
Shift x to the right y bits
x less than y
x greater than y
Equality; x equal to y
x not equal to y
Assigns the value on the right to the location identified on the left
(same as the C language assignment operator '=')
Argument pointer; register 10 (riO)
Count operand
Destination operand
Frame pointer; register 9 (r9)
Program counter; register 15 (r15)
Processor status word; register 11 (rIl)
Function that returns x, sign extended through 32 bits.
Stack pointer; register 12 (rI2)
A pop from the stack; decrement SP by 4 before removing data ( )
from the stack
A push onto the stack; store data and increment SP by 4
Source operand
Hexadecimal value where n is the digits a through 9 and a through
f (or A through F); may also be written OXn
A comment, not an operation
An operation other than an instruction

3.7.2 Instruction Set Descriptions
The instruction set is described in detail on the following pages.

3-36

ADDB2
ADDH2
ADDW2

ADDB2
ADDH2
ADDW2

ADD
Add byte
Add halfword
Add word

Assembler
Syntax

ADDB2 src,dst
ADDH2 src,dst
ADDW2 src,dst

Opcodes

Ox9F
Ox9E
Ox9C

ADDB2
ADDH2
ADDW2

Operation

dst

dst

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

+-

N

+-

Z

+-

C

+

src

1, if (dst

I, if (dst

+ src) < 0
+ src) == 0

I, if carry out of sign bit of dst

V I , if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if there is truncation.

Examples

ADDB2 $OxIOO,%rO
ADDH2 %rO,%r3
ADDW2 4(%r3),*$OxII0

3-37

ADDB3
ADDH3
ADDW3

ADDB3
ADDH3
ADDW3
ADD, 3 Address
Add byte, 3 address
Add halfword, 3 address
Add word, 3 address

Assembler
Syntax

ADDB3 srcJ,src2,dst
ADDH3 srcJ ,src2,dst
ADDW3 srcJ,src2,dst

Opcodes

OxDF
OxDE
OxDC

ADDB3
ADDH3
ADDW3

Operation

dst

srcJ

Address
Modes

srcJ

all modes

src2

all modes

dst

all modes except literal or immediate

Condition
Flags

N

+-

+-

+

src2

1, if (srcJ

Z +- 1, if (srcJ

+ src2) < 0
+ src2) == 0

C +- 1, if carry out of sign bit of dst
V+-l, if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if there is truncation.

Examples

3-38

ADDB3 %rO,%r3,%r5
ADDH3 4(%r2),*$OxllO,%r3
ADDW3 *$OxlFO,4(%rl),%rO

ALSW3

ALSW3
ARITHMETIC LEFT SHIFT
Assembler
Syntax

ALSW3 count,src,dst

Opcode

OxCO

ALSW3

Operation

dst -

src < < (count & Oxl F) bits

Address
Modes

count all modes

Condition
Flags

Arithmetic left shift word

src

all modes

dst

all modes except literal or immediate

N -

I, if dst

Z -

1, if dst == 0

C -

0

V -

0 (see Note)

< 0

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I 8F I OF I DF I FD I
-increasing bits

ALSW3 &2,%rO,%rO
After:

Note

rO

I 3C I 3F I 7F

F4

All operands are of type word. However, only the five low-order bits of
count are used; the upper bits are ignored. No bits are shifted past the
sign bit, so integer overflow cannot occur. However, the V bit can be
set if an expanded-operand type mode changes the type of dst. Zeros
replace bits that are shifted out. The sign bit is not changed.

3-39

ANDB2
ANDH2
ANDW2

ANDB2
ANDH2
ANDW2

AND
Assembler
Syntax

ANDB2 src,dst
ANDH2 src,dst
ANDW2 src,dst

Opcodes

OxBB ANDB2
OxBA ANDH2
OxB8 ANDW2

Operation

dst +- dst & src

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

AND byte
AND halfword
AND word

N +- MSB of dst

Z +- I, if dst == 0
C+-O

v ;-

1, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

ANDB2 &7,6(%rl)
ANDH2 %rO, *$result
ANDW2 (%rl),%r4

3-40

ANDB3
ANDH3
ANDW3

ANDB3
ANDH3
ANDW3

AND, 3 ADDRESS
AND byte, 3 address
AND halfword, 3 address
AND word, 3 address

Assembler
Syntax

ANDB3 srcJ ,src2,dst
AND H3 src 1,src2,dst
ANDW3 srcJ ,src2,dst

Opcodes

OxFB ANDB3
OxFA ANDH3
OxF8 ANDW3

Operation

dst -- src2

Address
Modes

srcJ

all modes

src2

all modes

dst

all modes except literal or immediate

Condition
Flags

+

srcJ

N -- MSB of dst
Z -

I, if dst

== 0

C-O

vExceptions

I, if result must be truncated to fit dst size

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

ANDB3 &Ox27,*$Ox300,%r6
ANDH3 Ox31(%rS),%rO,%r1
ANDW3 %r2,%r1,%rO

3-41

ARSB3
ARSH3
ARSW3

ARSB3
ARSH3
ARSW3

ARITHMETIC RIGHT SHIFT
Assembler
Syntax

ARSB3 count,src,dst
ARSH3 count,src,dst
ARSW3 count,src,dst

Opcodes

OxC7
OxC6
OxC4

ARSB3
ARSH3
ARSW3

Operation

dst -

srcI > > (count & Oxlf) bits

Address
Modes

count all modes

Condition
Flags

Arithmetic right shift byte
Arithmetic right shift halfword
Arithmetic right shift word

src

all modes

dst

all modes except literal or immediate

< 0
Z - 1, if dst == 0

N -

1, if dst

C-O
V -

0

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I OF I OF I 77 I AF I
-increasing bits

ARSH3 &2,%rO,%rO
After:

Note

3-42

rO

I 00 I 00 I lD I EB I

All operands are of type word. However, only the five low-order bits of
count are used; the upper bits are ignored. The sign bit (MSB) of src is
copied as bits are shifted out. The type of src does not affect sign
extension.

BCCB
BCCH

BCCB
BCCH

BRANCH ON CARRY CLEAR
Assembler
Syntax

BCCB disp8
BCCH dispJ6

Opcodes

Ox53
Ox52

Operation

if (C == 0)
PC +- PC

Address
Modes

Branch on carry clear, byte displacement
Branch on carry clear, halfword displacement

BCCB
BCCH

None valid
disp8
dispJ6

+

SEXT(disp)

= signed 8-bit value
=

Condition
Flags

Unchanged

Exceptions

None

Examples

BCCB Ox9
BCCH OxFF23

signed l6-bit value

3-43

BCSB
BCSH

BCSB
BCSH
BRANCH ON CARRY SET
Assembler
Syntax

BCSB disp8
BCSH dispJ6

Opcodes

Ox5B
Ox5A

Operation

if (C ==1)
PC +- PC

Address
Modes

BCSB
BCSH

+

SEXT(disp)

None valid
disp8 = signed 8-bit value
dispJ6

= signed 16-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BCSB OxFF
BCSH Ox1234

3-44

Branch on carry set, byte displacement
Branch on carry set, halfword displacement

BEB
BEH

BEB
BEH

BRANCH ON EQUAL
Assembler
Syntax

BEB disp8
BEH dispJ6

Opcodes

Ox7F
Ox6F
Ox7E
Ox6E

Operation

if (Z == 1)

BEB
BEB
BEH
BEH

PC Address
Modes

Branch on equal, byte displacement
Branch on equal, byte displacement

PC

+

SEXT(disp)

None valid
disp8 = signed 8-bit value
dispJ6

= signed 16-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BEB OxFl
BEH Ox4221

3-45

BGB
BGH

BGB
BGH

BRANCH ON GREATER THAN (SIGNED)
Assembler
Syntax

BGB disp8
BGH dispJ6

Opcodes

Ox47
Ox46

Operation

if «NIZ)
PC -

Address
Modes

BGB
BGH

==

None valid
disp8

disp16
Condition
Flags

Unchanged

Exceptions

None

Examples

BGB more
BGH less

3-46

Branch on greater than, byte displacement
(signed)
Branch on greater than, halfword displacement
(signed)

PC

0)

+ SEXT(disp)

= signed 8-bit value
= signed

16-bit value

BGEB
BGEH

BGEB
BGEH
BRANCH ON GREATER THAN OR EQUAL (SIGNED)
Assembler
Syntax

BGEB disp8
BGEH dispJ6

Opcodes

Ox43
Ox42

Operation

if «N

BGEB
BGEH

PC

Address
Modes

Branch on greater than or equal, byte
displacement (signed)
Branch on greater than or equal, halfword
displacement (signed)

== 0) I(Z ==
<-

PC

+

1))
SEXT(disp)

None valid
disp8 = signed 8-bit value
dispJ6 = signed 16-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BGEB again
BGEH OxF102

3-47

BGEUB
BGEUH

BGEUB
BGEUH

BRANCH ON GREATER THAN OR EQUAL (UNSIGNED)
Assembler
Syntax

BGEUB disp8

Branch on greater than or equal, byte
displacement (unsigned)
Branch on greater than or equal, halfword
displacement (unsigned)

BGEUH disp16

Opcodes

Ox53
Ox52

Operation

if (C == 0)
PC .- PC

Address
Modes

BGEUB
BGEUH

+

SEXT(disp)

None valid
disp8 = signed 8-bit value

disp16 = signed l6-bit value
Condition
Flags

Unchanged

Exceptions

None

Examples

BGEUB OxAl
BGEUH ahead

3-48

BGUB
BGUH

BGUB
BGUH
BRANCH ON GREATER THAN (UNSIGNED)
Assembler
Syntax

BGUB disp8

Branch on greater than, byte displacement
(unsigned)
Branch on greater than, halfword displacement
(unsigned)

BGUH dispJ6

Opcodes

Ox57
Ox56

Operation

if «CIZ)
PC -

Address
Modes

BGUB
BGUH

== 0)

None valid
disp8
dispJ6

PC

+

SEXT(disp)

= signed 8-bit value
= signed l6-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BGUB OxDE
BGUH OxF123

3-49

BITB
BITH
BITW

BITB
BITH
BITW

BIT TEST
Assembler
Syntax

BITB src1,src2
BITH src1,src2
BITW src1,src2

Opcodes

Ox3B BITB
Ox3A BITH
Ox38 BITW

Operation

temp

+-

Address
Modes

src1

all modes

src2

all modes

N

+-

MSB of temp

Z

+-

1, if temp == 0

Condition
Flags

Bit test byte
Bit test halfword
Bit test word

src2 & src1

C+-O
V+-O

Exceptions

None

Examples

BITB %rO, {uhalf}%rl
BITH *$OxFF,%r3
BITW bit (%r3),(%rO)

Note

The final value of temp, a temporary register, determines the setting of
the condition codes. Temp is discarded upon completion of the
instruction.

3-50

BLB
BLH

BLB
BLH
BRANCH ON LESS THAN (SIGNED)
Assembler
Syntax

BLB disp8
BLH dispJ6

Branch on less than, byte displacement
(signed)
Branch on less than, halfword displacement
(signed)

Opcodes

Ox4B BLB
Ox4A BLH

Operation

if «N == I) & (Z == 0))
PC ...... PC + SEXT(disp)

Address
Modes

None valid
disp8

= signed 8-bit value

dispJ6 = signed l6-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BLB OxlF
BLH back

3-51

BLEB
BLEH

BLEB
BLEH
BRANCH ON LESS THAN OR EQUAL (SIGNED)
Assembler
Syntax

BLEB disp8
BLEH dispJ6

Branch on less than or equal, byte displacement
(signed)
Branch on less than or equal, halfword
displacement (signed)

Opcodes

Ox4F
Ox4E

Operation

if ((NIZ) == I)
PC +- PC + SEXT(disp)

Address
Modes

None valid
disp8

BLEB
BLEH

= signed 8-bit value

dispJ6 = signed 16-bit value
Condition
Flags

Unchanged

Exceptions

None

Examples

BLEB Ox6
BLEH OxFFF

3-52

BLEUB
BLEUH

BLEUB
BLEUH

BRANCH ON LESS THAN OR EQUAL (UNSIGNED)
Assembler
Syntax

BLEUB disp8

Branch on less than or equal, byte
displacement (unsigned)
Branch on less than or equal, halfword
displacement (unsigned)

BLEUH dispJ6

Opcodes

Ox5F
Ox5E

Operation

if

BLEUB
BLEUH

«Clz)

== 1)

PC Address
Modes

PC

+

SEXT(disp)

None valid
disp8 = signed 8-bit value
dispJ6 = signed 16-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BLEUB Ox14
BLEUH back

3-53

BLUB
BLUH

BLUB
BLUH
BRANCH ON LESS THAN (UNSIGNED)
Assembler
Syntax

BLUB disp8
BLUH dispJ6

Opcodes

Ox5B
Ox5A

Operation

if (C == 1)
PC +- PC

Address
Modes

BLUB
BLUH

None valid
disp8
dispJ6

+

SEXT(disp)

= signed 8-bit value
= signed I6-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BLUB OxI2
BLUH OxFF12

3-54

Branch on less than byte displacement
(unsigned)
Branch on less than halfword displacement
(unsigned)

BNEB
BNEH

BNEB
BNEH
BRANCH ON NOT EQUAL
Assembler
Syntax

BNEB disp8
BNEH dispJ6

Opcodes

Ox77
Ox67
Ox76
Ox66

Operation

if (Z == 0)
PC +- PC

Address
Modes

Branch on less than, byte displacement
Branch on less than, halfword displacement

BNEB
BNEB
BNEH
BNEH

None valid
disp8
dispJ6

+

SEXT(disp)

= signed 8-bit value
= signed 16-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BNEB Ox FE
BNEH OxFF13

3-55

BPT

BPT
BREAKPOINT TRAP
Assembler
Syntax

BPT Breakpoint trap

Opcodes

Ox2E

Operation

I*BPT executes the following processor operation*1

BPT

{breakpoint trap}
Address
Modes

None

Condition
Flags

Unchanged

Exceptions

Generates breakpoint trap exception.

Examples

BPT

3-56

BRB
BRH

BRB
BRH
BRANCH
Branch with byte displacement
Branch with halfword displacement

Assembler
Syntax

BRB disp8
BRH dispJ6

Opcodes

Ox7B
Ox7A

BRB
BRH

Operation

PC

PC

Address
Modes

None valid
disp8 = signed 8-bit value

+-

+

SEXT(disp)

dispJ6 = signed 16-bit value
Condition
Flags

Unchanged

Exceptions

None

Examples

BRB OxA
BRH OxFAA

3-57

BSBB
BSBH

BSBB
BSBH

BRANCH TO SUBROUTINE
Branch to subroutine, byte displacement
Branch to subroutine, halfword displacement

Assembler
Syntax

BSBB disp8
BSBH dispJ6

Opcodes

Ox37
Ox36

Operation

* (SP++) +- address of next instruction
PC +- PC + SEXT(disp)

Address
Modes

None valid
disp8 = signed 8-bit value

BSBB
BSBH

dispJ6 = signed l6-bit value
Condition
Flags

Unchanged

Exceptions

None

Examples

BSBB sub2
BSBH subl

3-58

BVCB
BVCH

BVCB
BVCH

BRANCH ON OVERFLOW CLEAR
Assembler
Syntax

BVCB disp8
BVCH dispJ6

Opcodes

Ox63
Ox62

Operation

if (V

BVCB
BVCH

== 0)
PC

Address
Modes

Branch to subroutine, byte displacement
Branch to subroutine, halfword displacement

+-

None valid
disp8
dispJ6

PC

+

SEXT(disp)

= signed 8-bit value
= signed 16-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BVCB Ox7E
BVCH Ox8F21

3-59

BVSB
BVSH

BVSB
BVSH

BRANCH ON OVERFLOW SET
Assembler
Syntax

BVSB disp8
BVSH disp16

Opcodes

Ox6B
Ox6A

Operation

if (V == 1)
PC +- PC

Address
Modes

Branch on overflow set, byte displacement
Branch on overflow set, halfword displacement

BVSB
BVSH

SEXT(disp)

None valid
disp8 = signed 8-bit value

disp16

=

signed l6-bit value

Condition
Flags

Unchanged

Exceptions

None

Examples

BVS OxFl
BVSB OxFF77

3-60

+

CALL

CALL
CALL PROCEDURE
Assembler
Syntax

CALL src,dst

Opcode

Ox2C

Operation

tempa
tempb
* (SP+4)
*SP
SP
PC
AP

Address
Modes

Call procedure

CALL
+++++++-

&src
&dst
AP
address of next instruction
SP+8
tempb
tempa

src

all modes except literal, register, or immediate

dst

all modes except literal, register, or immediate

Condition
Flags

Unchanged

Exceptions

Illegal operand exception occurs if literal, register, expanded-operand
type, or immediate mode is used for src or dst.

Examples

CALL -(3*4)(%sp),funcl (see Figure 3-9)

Note

Both operands are effective addresses. Temp is a temporary register.
CALL sets up the protocol for a C language function call. (Also see
Return from procedure.) CALL sets AP to first of the word arguments
that the calling function pushed on the stack before executing the call.

3-61

CFLUSH

CFLUSH

CACHE FLUSH
Assembler
Syntax

CFLUSH

Cache flush

Opcode

Ox27

Operation

/*CFLUSH executes the following processor operation*/
{all entries in instruction cache are marked invalid}

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Examples

CFLUSH

Notes

CFLUSH is a nonprivileged instruction.

CFLUSH

This instruction operates identically whether the instruction cache is
enabled (PSW==O) or disabled (PWS==I).

3-62

CLRB
CLRH
CLRW

CLRB
CLRH
CLRW
CLEAR
Assembler
Syntax

CLRB dst
CLRH dst
CLRW dst

Opcodes

Ox83
Ox82
Ox80

Operation

dst +- 0

Address
Modes

dst

Clear byte
Clear halfword
Clear word

CLRB
CLRH
CLRW

all modes except literal or immediate

Condition
Flags

Z+-l
C+-O
V+-O
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

CLRB * &Ox300
CLRH %r1
CLRW (%rO)

3-63

CMPB
CMPH
CMPW

CMPB
CMPH
CMPW
COMPARE
Assembler
Syntax

CMPB srcl,src2
CMPH srcl,src2
CMPW srcl,src2

Opcodes

Ox3F CMPB
Ox3E CMPH
Ox3C CMPW

Operation

src2 +- srcl

Address
Modes

srcl

all modes

src2

all modes

Condition
Flags

N +- 1, if src2

Compare byte
Compare halfword
Compare word

<

srcl (signed)

Z

1, if src2 == srcl

C

1, if src2

<

srcl (unsigned)

Y+-O
Exceptions

None

Examples

CMPB &lO,%rO
CMPH (%rO),(%rI)
CMPW *$OxI2F7,%r2

Note

This instruction sets the condition flags N, Z, and C as if a subtract had
been executed. Neither operand is altered. (Also see Test,)

3-64

DECB
DECH
DECW

DECB
DECH
DECW

DECREMENT
Assembler
Syntax

DECB ';st
DECH dst
DECW dst

Opcodes

Ox97
Ox96
Ox94

DECB
DECH
DECW

Operation

dst

dst -

Address
Modes

dst

Condition
Flags

N

+-

Decrement byte
Decrement halfword
Decrement word

I

all modes except literal or immediate

+-

1, if Cdst - 1)

<

0

Z

1, if Cdst - 1) == 0

C

1, if borrow into sign bit of dst

V I , if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Integer overflow exception occurs if there is truncation.
Examples

DECB 4C%fp)
DECH $resuIt
DECW *$last

3-65

DIVB2
DIVH2
DIVW2

DIVB2
DIVH2
DIVW2

DIVIDE
Assembler
Syntax

DIVB2 src,dst
DIVH2 src,dst
DIVW2 src,dst

Opcodes

OxAF DIVB2
OxAE DIVH2
OxAC DIVW2

Operation

dst -

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Divide byte
Divide halfword
Divide word

dst I src

N -

1, if (dst I src)

Z -

1, if (dst I src)

C -

0

< 0
==

0

V-I, if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer zero-divide exception occurs if src is equal to

o.

Integer overflow exception occurs if there is truncation.
Examples

3-66

DIVB2 &40,%r6
DIVH2 4(%r3),(%r4)
DIVW2 $first,$last

DIVB3
DIVH3
DIVW3

DIVB3
DIVH3
DIVW3

DIVIDE, 3 ADDRESS
Assembler
Syntax

DIVB3 srcJ ,src2,dst
D IVH3 src 1,src2,dst
DIVW3 srcJ ,src2,dst

Opcodes

OxEF
OxEE
OxEC

DIVB3
DIVH3
DIVW3

Operation

dst

src2 / srci

Address
Modes

srcJ

all modes

src2

all modes

dst

all modes except literal or immediate

N -

1, if (src2 / srcJ)

Z -

1, if (src2 / srcJ) == 0

Condition
Flags

+-

Divide byte, 3 address
Divide halfword, 3 address
Divide word, 3 address

< 0

C-O

v
Exceptions

+-

1, if overflow

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer zero-divide exception occurs if src 1 is equal to O.
Integer overflow exception occurs if there is truncation.

Examples

DIVB3 &Ox30,%r3,12(%ap)
DIVH3 &Ox3030, (%r2) ,5 (%r2)
DIVW3 &Ox304050, (%r 1),4 (%r1)

3-67

EXTFB
EXTFH
EXTFW

EXTFB
EXTFH
EXTFW

EXTRACT FIELD
Assembler
Syntax

EXTFB width,offset,src,dst
EXTFH width,offset,src,dst
EXTFW width,offset,src,dst

Opcodes

OxCF
OxCE
OxCC

Operation

dst +- FIELD(offset,width,src)

Address
Modes

width

Condition
Flags

Extract field from byte
Extract field from halfword
Extract field from word

EXTFB
EXTFH
EXTFW

all modes

offset

all modes

src

all modes

dst

all modes except literal or immediate

N +- high-order bit of dst
Z +- 1, if dst == 0
C+-O
V+-O (see Note)

Exceptions
Examples

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Before:

Location Ll = Ox01234567

EXTFW &1O,&4,Ll,%rO
After:

rO

I 00 I 00 I 04

56

+- increasing bits
The field extracted starts at bit 4 of location Ll, skipping bits 0 through
3, and extends through bit 14 of Ll. These eleven bits are written to
bits 0 through 10 of rO; zeros fill the remaining bits of rOo
Note

3-68

Only the low-order five bits of width and offset are examined. If the
sum width plus offset is greater than 32 (bits), then the field wraps
around through bit 0 of the base word. The field specified by width,
offset, and src is stored, right adjusted, in dst. The remaining bits of
dst are set to O. If the field is too large for the size of dst. the excess
high-order bits are discarded and the V flag is set.

EXTOP

EXTOP

EXTENDED OPCODE
Assembler
Syntax

EXTOP byte

Extended opcode

Opcode

Ox14

Operation

I*EXTOP executes the following processor operation*1
{reserved-opcode exception}

Address
Modes

None valid
byte = 8-bit value

Condition
Flags

Unchanged

Exceptions

Generates reserved opcode exception. See Note.

Examples

EXTOP Ox2F

Note

The EXTOP opcode is an escape to form additional instructions. The
processor does not access byte when executing this instruction. Instead,
it generates a reserved-opcode exception after decoding the opcode. The
operating system's exception handler should access byte.

EXTOP

3-69

INCB
INCH
INCW

INCB
INCH
INCW

INCREMENT
Assembler
Syntax

INCB dst
INCH dst
INCW dst

Opcodes

Ox93
Ox92
Ox90

INCB
INCH
INCW

Operation

dst -

dst

Address
Modes

dst

Condition
Flags

N -

1, if (dst

+

I)

Z -

1, if (dst

+

I) == 0

C -

I, if carry into sign bit of dst

v -

I, if overflow

Exceptions

Increment byte
Increment halfword
Increment word

+

I

all modes except literal or immediate

< 0

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if truncation takes place.

Examples

3-70

INCB 4(%r2)
INCH %rO
INCW (%rl)

INSFB
INSFH
INSFW

INSFB
INSFH
INSFW
INSERT FIELD
Assembler
Syntax

INSFB width,offset,src,dst
INSFH width,offset,src,dst
INSFW width,offset,src,dst

Opcodes

OxCB
OxCA
OxC8

Operation

FIELD (offset, width,dst) -- src

Address
Modes

Condition
Flags

Insert field from byte
Insert field from halfword
Insert field from word

INSFB
INSFH
INSFW

width

all modes

offset

all modes

src

all modes

dst

all modes except literal or immediate

N -- bit 31 of dst
Z -- 1, if dst == 0
C--O
V -- 0 (see Note)

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

AB

I CD I EF I 01 I

-- increasing bits
INSFW & 11,&8,%r1,%rO
After:

rO

I

AB

I C5 I 67 I 01 I

The field insertion starts at bit 8 of rO, skipping bits 0 through 7, and
extends through bit 19. Therefore, bits 8 through 19 of rO now contain
the same value as bits 0 through 11 of rl.
Note

Only the low-order five bits of width and offset are examined. If the
sum width plus offset is greater than 32 (bits), the field wraps around to
bit 0 of the destination. Starting with bit 0 of src, (width+ 1) bits are
placed into dst beginning at the bit designated by offset. If dst is a byte
or halfword and (width+offset) specifies a field that extends beyond dst,
no bits beyond dst are altered but the V flag is set.
3-71

JMP

JMP

JUMP
Assembler
Syntax

JMP dst

Opcode

Ox24

Operation

PC

Address
Modes

dst

Condition
Flags

Unchanged

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

JMP .L12

Note

The operand dst is an effective address; i.e., the 32-bit address of dst is
used as the destination rather than the word stored at that address.

3-72

Jump

JMP

+-

&dst

all modes except literal, register, or immediate

I

JSB

JSB

JUMP TO SUBROUTINE
Assembler
Syntax

JSB dst

Opcode

Ox34

Operation

JSB

* (SP++)
PC

Jump to subroutine

+-

+-

address of next instruction

&dst

Address
Modes

dst

Condition
Flags

Unchanged

Exceptions

Illegal operand exception occurs if literal, expanded-operand type, or
immediate mode is used for dst.

Examples

JSB error

Note

The operand dst is an effective address; i.e., the 32-bit address of dst is
used as the destination rather than the word at that address.

all modes except literal, register, or immediate

3-73

LLSB3
LLSH3
LLSW3

LLSB3
LLSH3
LLSW3

LOGICAL LEFT SHIFT
Assembler
Syntax

LLSB3 count,src,dst
LLSH3 count,src,dst
LLSW3 count,src,dst

Opcodes

OxD3
OxD2
OxDO

Operation

dst --- src < < (count & OxIF) bits

Address
Modes

count

all modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Logical left shift byte
Logical left shift halfword
Logical left shift word

LLSB3
LLSH3
LLSW3

N --- MSB of dst

Z --- I, if dst == 0

v ---

0, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I

OF

I OF I DF I FD I

--- increasing bits
LLSH3 &2,%rO,%rO
After:
Note

3-74

rO

I

FF

I FF I 7F

F4

Only the five low-order bits of count are used; the high-order bits are
ignored. Zeros replace the bits shifted out of the low-order bit position
(bit 0).

LRSW3

LRSW3

LOGICAL RIGHT SHIFT
Assembler
Syntax

LRSW3 count,src,dst

Opcode

OxD4

LRSW3

Operation

dst -

src > > (count & OxIF) bits

Address
Modes

count

all modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

N -

MSB of dst

Z -

I, if dst == 0

Logical right shift word

C-O

v-

I, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I

C3

I CO I 00 I 00 I

- increasing bits
LRSW3 &Oxll,%rO,%rO
After:
Note

rO

I

00

I 00 I 61 I EO I

All operands are type word. However, only the five low-order bits of
count are used; the high-order bits are ignored. Zeros replace the bits
shifted out of the high-order bit position (bit 31).

3-75

MCOMB
MCOMH
MCOMW

MCOMB
MCOMH
MCOMW

MOVE COMPLEMENTED
Assembler
Syntax

MCOMB src,dst
MCOMH src,dst
MCOMW src,dst

Opcodes

Ox8B
Ox8A
Ox88

MCOMB
MCOMH
MCOMW

Operation

dst

-src

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Move complemented byte
Move complemented halfword
Move complemented word

N +-- MSB of dst

Z +-- 1, if dst == 0
C+--O

v
Exceptions

+-- 1, if result must be truncated to fit dst size

Illegal operand exception occurs if literal or immediate mode is used for

dst.
Examples

Before:

rO

12

I 34 I 56 I 78 I

+-- increasing bits
MCOMW %rO,%rl
After:

Note

3-76

rl

I

ED

I CB I A9 I 87 I

dst is the one's complement of src

MNEGB
MNEGH
MNEGW

MNEGB
MNEGH
MNEGW

MOVE NEGATED
Assembler
Syntax

MNEGB src,dst
MNEGH src,dst
MNEGW src,dst

Opcodes

Ox8F MNEGB
Ox8E MNEGH
Ox8C MNEGW

Operation

dst -

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Move negated byte
Move negated halfword
Move negated word

-src

N -

MSB of dst

Z -

I, if dst == 0

C -

0

v -

I, if integer overflow

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I

01

I 23 I 45 I 67 I

- increasing bits
MNEGB %rO,%rl
After:
Note

rl

I

FF

I FF I FF I 99 I

dst is the two's complement of src.

3-77

MODB2
MODH2
MODW2

MODB2
MODH2
MODW2
MODULO
Assembler
Syntax

MODB2 src,dst
MODH2 src,dst
MODW2 src,dst

Opcodes

OxA7
OxA6
OxA4

Operation

dst -- dst % src

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Modulo byte
Modulo halfword
Modulo word

MODB2
MODH2
MODW2

N -- 1, if (dst % src)

< 0

Z -- 1, if (dst % src)

== 0

C--O

v -Exceptions

1, if overflow

IlIegal operand exception occurs if literal or immediate mode is used for
dst.
Integer zero-divide exception occurs if src is equal to O.
Integer overflow exception occurs if there is truncation.

Examples

3-78

MODB2 &40,%r3
MODH2 4(%r3),%r3
MODW2 %rO, *$result

MODB3
MODH3
MODW3

MODB3
MODH3
MODW3

MODULO, 3 ADDRESS
Assembler
Syntax

MODB3 src1.src2.dst
MODH3 src1.src2.dst
MODW3 src1.src2.dst

Opcodes

OxE7
OxE6
OxE4

Operation

dst +- srcl 9b src2

Address
Modes

src1

all modes

src2

all modes

dst

all modes except literal or immediate

Condition
Flags

Modulo byte, 3 address
Modulo halfword, 3 address
Modulo word, 3 address

MODB3
MODH3
MODW3

N +- 1, if (src1 9b src2)

< 0

Z +- I, if (src1 % src2) == 0
C+-O
V+-I, if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer zero-divide exception occurs if src1 is equal to O.
Integer overflow exception occurs if there is truncation.

Examples

MODB3 &40,9br3,OxIIOI (9br2)
MODH3 9br3,$real,9br3
MODW3 4(9br2),*$Ox34,9brO

3-79

MOVB
MOVH
MOVW

MOVB
MOVH
MOVW
MOVE
Assembler
Syntax

MOVB src,dst
MOVH src,dst
MOVW src,dst

Opcodes

Ox87
Ox86
Ox84

MOVB
MOVH
MOVW

Operation

dst -

src

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Move byte
Move halfword
Move word

N -

MSB of dst

Z -

1, if dst == 0

C -

0

V-I, if result must be truncated to fit dst size
See Note
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I 01

r1

I AB I AB I AB I AB I

23

45

67

-increasing bits
MOVW %rO,%rl
After:

rO

I 01 I 23

rl

I 01 I 23 I 45 I 67

NZCV

3-80

=

0000

45

67

MOVB
MOVH
MOVW
Notes

MOVB
MOVH
MOVW
If the expanded-type mode is used for dst or for both operands, this
instruction can convert data from one type to another. The src operand
determines the type of extension performed: if src is signed byte or
halfword, sign extension occurs; if src is byte or unsigned halfword, zero
extension occurs.

Use the following instructions for conversions if the destination is not a
register.
Instruction

Conversion

MOVB {sbyte} src, (shalf}dst
MOVB (sbyte}src, (sword}dst
MOVH src,(sword}dst
MOVB src, {shalf}dst
MOVB src,{sword}dst
MOVH {uhalf}src, {sword} dst
MOVH src, {sbyte}dst
MOVW src, {sbyte}dst
MOVW src,{shalf}dst

Signed byte to signed halfword
Signed byte to signed word
Byte to signed word
Byte to signed halfword
Byte to signed word
Unsigned halfword to signed word
Halfword to signed byte
Word to signed byte
Word to signed halfword

If the destination is a register, use the following instructions for
conversions:
Instruction

Conversion

ANDH3 & Oxff,src, {byte} dst
ANDW3 &Oxff,src, (byte}dst
MOVW src,dst; MOVH dst,dst

Halfword to byte
Word to byte
Word to halfword

The instructions 'MOVW -,%psw' and 'MOVW %psw,-' do not
change the condition flags.

3-81

MOVAW

MOVAW

MOVE ADDRESS (WORD)
Assembler
Syntax

MOVA W src,dst

Opcode

Ox04

Operation

dst +- &src

Address
Modes

src

all modes except literal, register, or immediate

dst

all modes except literal or immediate

Condition
Flags

Move address (word)

MOVAW

N +- MSB of dst
Z +- I, if dst

== 0

C+-O
V+-O
Exceptions

Illegal operand exception occurs if literal, register, or immediate mode
is used for src, or if literal or immediate mode is used for dst.

Examples

Before:

rO
rl

I 00 I 00 I 10 I 10 I
I AB I AB I AB I AB I
+- increasing bits

MOVAW 4(%rO),%rl
After:

Note

3-82

rl

00

00

10

14

Source operand type is effective address.

MOVBLW

MOVBLW

MOVE BLOCK
Assembler
Syntax

MOVBL W

Move block of words

Opcode

Ox3019

Operation

while (R2 > 0) {
*Rl = *RO;
{disable interrupts)
--R2;
RO=RO+4;
Rl=R1+4;
{enable interrupts)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

External memory fault may occur in the middle of an iteration.

Examples

Before:

MOVBLW

rO
rl

r2

I 00 I 00 I 01 I 00
I 00 I 00 I 02 I 00
I 00 I 00 I 00 I 03
-- increasing bits

Assume three word locations starting at OxlOO contain the word values
Ox5, OxlO and Ox20, respectively.
MOVBLW
After:

rO
rI
r2

I 00 I 00 I 01 I DC I
I 00 I 00 I 02 I DC I
I 00 I 00 I 00 I 00 I

3-83

MOVBLW

MOVBLW
Three word locations starting at Ox200 now also contain Ox5, Oxl0 and
Ox20, respectively.

Notes

Opcode occupies 16 bits. All operands are implicitly defined in the
registers (rO, rl, and r2) and are 32-bit words. These registers must be
preset with the following information before executing MOVBL W:
rO
r1

r2

Address of source
Address of destination
Number of words to be moved.

The instruction may be interrupted only at the end of an iteration. A
memory fault may occur in the middle of an iteration. To restart the
instruction after a fault, execute MOVBL W again; the registers are
updated after the only memory access that could cause the fault. At
each iteration, rO and rl are incremented by 4, and r2 is decremented
by 1. Execution of MOVBL W is finished when r2 is O.

3-84

MULB2
MULH2
MULW2

MULB2
MULH2
MULW2
MULTIPLY
Assembler
Syntax

MULB2 src,dst
MULH2 src,dst
MUL W2 src,dst

Opcodes

OxAB
OxAA
OxA8

Operation

dst +- dst

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Multiply byte
Multiply halfword
Multiply word

MULB2
MULH2
MULW2

* src

N +- 1, if (dst

*

src)

< 0

Z +- 1, if (dst

*

src)

== 0

C+-O
V+-l, if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if there is truncation.

Example

MULBH2 %r2,{sbyte}4(%r6)

3-85

MULB3
MULH3
MULW3

MULB3
MULH3
MULW3
MULTIPLY, 3 ADDRESS
Assembler
Syntax

MULB3 src1 ,src2,dst
MULH3 srcl ,src2,dst
MUL W3 srcl ,src2,dst

Opcodes

OxEB MULB3
OxEA MULH3
OxE8 MULW3

Operation

dst -

Address
Modes

srcl

all modes

src2

all modes

dst

all modes except literal or immediate

N -

1, if (src1

*

src2)

Z -

1, if (srcl

*

src2) == 0

C -

0

Condition
Flags

srcl

*

Multiply byte, 3 address
Multiply halfword, 3 address
Multiply word, 3 address

src2

< 0

V-I, if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if there is truncation.

Examples

3-86

MULH3 %r3,*$Oxl004,%r4

MVERNO

MVERNO
MOVE VERSION NUMBER
Assembler
Syntax

MVERNO

Opcode

Ox3009

Operation

rO

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

MVERNO

Note

Opcode occupies 16 bits. Version number is the version of the processor
and may range from -128 to +127.

+-

Move processor version number

MVERNO

processor version number

3-87

NOP
NOP2
NOP3

NOP
NOP2
NOP3

NO OPERATION
No operation, 1 byte
No operation, 2 bytes
No operation, 3 bytes

Assembler
Syntax

NOP
NOP2
NOP3

Opcodes

Ox70
Ox73
Ox72

Operation

None

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Examples

NOP
NOP2
NOP3

Notes

The assembler inserts a NOP before instructions (other than branch)
that read the PSW. This NOP allows the conditions bits to stabilize.
The bytes following NOP2 and NOP3 are generated by the assembler
and are ignored by the processor. They may be any value.

3-88

NOP
NOP2
NOP3

ORB2
ORH2
ORW2

ORB2
ORH2
ORW2

OR
Assembler
Syntax

ORB2 src,dst
ORH2 src,dst
OR W2 src,dst

Opcodes

OxB3
OxB2
OxBO

Operation

dst +- dstlsrc

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

OR byte
OR halfword
OR word

ORB2
ORH2
ORW2

N +- MSB of dst
Z +- 1, if dst

== 0

C+-O

v

+- 1, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

ORB2 & 12,4 (%fp)
ORH2 %rO,4(%rO)
OR W2 %r3,$result

3-89

ORB3
ORH3
ORW3

ORB3
ORH3
ORW3
OR, 3 ADDRESS
OR byte, 3 address
OR halfword, 3 address
OR word, 3 address

Assembler
Syntax

ORB3 srci ,src2,dst
ORH3 srci,src2,dst
ORW3 srci,src2,dst

Opcodes

OxF3
OxF2
OxFO

Operation

dst -- src21srci

Address
Modes

srci

all modes

src2

all modes

dst

all modes except literal or immediate

Condition
Flags

ORB3
ORH3
ORW3

N -- MSB of dst

Z -- 1, if dst == 0

C--O

v --

1, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

ORB3 &16,*$Ox304,%rO
ORH3 %r1,4(%rI),%r1
ORW3 %r2,%r3,%r1

3-90

POPW

POPW

POP (WORD)
Assembler
Syntax

POPW dst

Pop (word)

Opcode

Ox20

POPW

Operation

dst -

*(--SP)

Address
Modes

dst

Condition
Flags

N -

MSB of dst

Z

1, if dst

C

0

all modes except literal or immediate (see Note)

==

0

v-O
Exceptions

Illegal operand exception occurs if literal, expanded-operand type, or
immediate mode is used for dst.

Example

POPW (%r2)

Note

If dst is the stack pointer (%sp), the results are indeterminate.

3-91

PUSHAW

PUSHAW

PUSH ADDRESS (WORD)
Assembler
Syntax

PUSHA W src

Opcode

Ox EO

Operation

*(SP++)

Address
Modes

src

Condition
Flags

N

Push address (word)

PUSHAW
+-

&src

all modes except literal, register, or immediate

+-

MSB of address of src

Z

1, if src

C

0

v

0

== 0

Exceptions

Illegal operand exception occurs if literal, register, expanded-operand
type, or immediate mode is used for src.

Example

PUSHA W Ox14(%r6)

Note

Source operand type is effective address. This instruction is the same as
a move address (MOV A W) instruction, except that the destination for
PUSHA W is an implied stack push.

3-92

PUSHW

PUSHW
PUSH (WORD)
Assembler
Syntax

PUSHW src

Push (word)

Opcode

OxAO

Operation

* (SP++) +-

Address
Modes

src

Condition
Flags

N +- MSB of src

PUSHW
src

all modes

Z +- 1, if src

==

0

C+-O

Exceptions

Illegal operand exception occurs if expanded-operand type addressing
mode is used.

Example

PUSHW (%r2)

3-93

RCC

RCC

RETURN ON CARRY CLEAR
Assembler
Syntax

RCC

Opcode

Ox50

Operation

if (C==O)
PC - *(--sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RCC

3-94

Return on carry clear
RCC

RCS

RCS

RETURN ON CARRY SET
Assembler
Syntax

RCS

Return on carry set

Opcode

Ox58

Operation

if (C==l)

RCS
PC

+-

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RCS

*(--SP)

3-95

REQL
REQLU

REQL
REQLU

RETURN ON EQUAL
Assembler
Syntax

REQL
REQLU

Return on equal (signed)
Return on equal (unsigned)

Opcodes

Ox7C
Ox6C

Operation

if (Z==1)

REQL
REQLU

PC

+-

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

REQL

3-96

*(--sp)

RESTORE

RESTORE
RESTORE REGISTERS
Assembler
Syntax

RESTORE %rn

Restore registers

Opcode

OxlS

Operation

tempa <- FP - 2S;
tempb <- * (FP - 2S);
tempc <- FP - 24;
while (n != FP) {
{
registednl <- (tempc)+;
n+=l;
}
FP <- tempb;
SP <- temp a

Address
Modes

Register mode, where n ranges from 0 through 9

Condition
Flags

Unchanged

Exceptions

See Notes.

Example

RESTORE %r3

Notes

If the operand is not register mode or n is not in the range 0 through 9,
the results are indeterminate. Although the results are determinate if n
is 0, 1 or 2, the effect is not that of a register restore in a functioncalling sequence.

RESTORE

RESTORE is the inverse of SAVE and should precede a return from
procedure (RET). (Also see SAVE and CALL.) The operand %rn
should be the same as in the corresponding SAVE, where n specifies the
number of registers (9 - n) to be restored for the original function.
RESTORE implements a stack frame for use in the C language
function-calling sequence. The instruction can restore up to six registers
(from register S through register 3) for use by the function. While
restoring these registers, it also adjusts SP and FP.
Illegal operand exception occurs if expanded-operand type address mode
is used.

3-97

RET

RET

RETURN FROM PROCEDURE
Assembler
Syntax

RET

Opcode

Oxl8

Operation

tempa
tempb
tempe
AP
PC
SP

Return from procedure
RET
++++++-

AP;
* (SP-4);
*(SP-8);
tempb;
tempe;
tempa;

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RET

Note

The return (RET) is the inverse of the call (CALL) instruction. A
restore should precede a return (RET) inside the function being exited.
RESTORE sets up the protocol for a C language return from function.
RET restores AP, PC, and SP to the values saved on the stack with the
corresponding CALL.

3-98

RGEQ

RGEQ

RETURN ON GREATER THAN OR EQUAL (SIGNED)
Assembler
Syntax

RGEQ

Return on greater than or equal (signed)

Opcode

Ox40

Operation

if «N==O) I(Z==1)

RGEQ
PC

+-

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RGEQ

*(--sp)

3-99

RGEQU

RGEQU
RETURN ON GREATER THAN OR EQUAL (UNSIGNED)
Assembler
Syntax

RGEQU

Opcode

Ox50

Operation

if (C==O)
PC +- *(--sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RGEQU

3-100

Return on greater than or equal (unsigned)

REGEQU

RGTR

RGTR
RETURN ON GREATER THAN (SIGNED)
Assembler
Syntax

RGTR

Return on greater than (signed)

Opcode

Ox44

Operation

if ((NIZ)==O)

RGTR
PC

<-

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RGTR

*(--sp)

3-101

RGTRU

RGTRU

RETURN ON GREATER THAN (UNSIGNED)
Assembler
Syntax

RGTRU

Opcode

Ox54

Operation

if «CIZ)==O)
PC +- *(--sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RGTRU

3-102

Return on greater than

RGTRU

RLEQ

RLEQ

RETURN ON LESS THAN OR EQUAL (SIGNED)
Assembler
Syntax

RLEQ

Return on less than or equal

Opcode

Ox4C

Operation

if «NIZ)==l)
PC +- *(--sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RLEQ

RLEQ

3-103

RLEQU

RLEQU

RETURN ON LESS THAN OR EQUAL (UNSIGNED)
Assembler
Syntax

RLEQU

Opcode

Ox5C

Operation

if «CIZ)==l)
PC - *(--sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RLEQU

3-104

Return on less than or equal (unsigned)

RLEQU

RLSS

RLSS

RETURN ON LESS THAN (SIGNED)
Assembler
Syntax

RLSS

Return on less than (signed)

Opcode

Ox48

Operation

if «N == 1) & (Z==O»
PC <- *(--Sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RLSS

RLSS

3-105

RLSSU

RLSSU

RETURN ON LESS THAN (UNSIGNED)
Assembler
Syntax

RLSSU

Opcode

Ox58

Operation

if (C==l)
PC ..- *(--Sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RLSSU

3-106

Return on less than (unsigned)

RLSSU

RNEQ
RNEQU

RNEQ
RNEQU

RETURN ON NOT EQUAL
Return on not equal (signed)
Return on not equal (unsigned)

Assembler
Syntax

RNEQ
RNEQU

Opcode

Ox74
Ox64

Operation

if (Z==O)
PC +- *(--sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RNEQ

RNEQ
RNEQU

3-107

ROTW

ROTW

ROTATE
Assembler
Syntax

ROTW count,src,dst

Opcode

OxD8

Operation

dst +- src rotated right (count & OxlF) bits

Address
Modes

count

all modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Rotate word

ROTW

N +- MSB of dst

== 0

Z +- 1, if dst
C+-O
V+-O
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

Before:

rO

I

OF

+-

I 00 I 00 I 7E I

increasing bits

ROTW &Ox404,%rO,%rO
After:

Note

3-108

rO

EO

I FO I 00 I 07 I

All operands are type word. However, only the five low-order bits of
count are used; the high-order bits are ignored.

RSB

RSB

RETURN FROM SUBROUTINE
Assembler
Syntax

RSB

Opcode

Ox78

RSB

Operation

PC

*(--Sp)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RSB

+-

Return from subroutine (unconditionaI)

3-109

Rve

Rve
RETURN ON OVERFLOW CLEAR
Assembler
Syntax

RVC

Return on overflow clear

Opcode

Ox60

Operation

if (V==O)

RVC
PC

+-

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RVC

3·110

*(--SP)

RVS

RVS

RETURN ON OVERFLOW SET
Assembler
Syntax

RVS

Return on overflow set

Opcode

Ox68

Operation

if (V==I)
PC +- *(--SP)

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

None

Example

RVS

RVS

3-111

SAVE

SAVE

SAVE REGISTERS
Assembler
Syntax

SA VE %rn

Save registers

Opcode

OxlO

Operation

temp +- SP
* (SP++) +- FP
while (n !=FP){
*(SP++) +- registednl
n+=l;
}
SP +-temp + 28;
FP +- SP;

Address
Modes

Register mode, where n ranges from 0 through 9

Condition
Flags

Unchanged

Exceptions

See Notes.

Example

SAVE %r3

Notes

If the operand is not register mode or n is not in the range 0 to 9, the
results are indeterminate. However, if n is 0, 1, or 2, the results are
determinate, but SP and FP will not point beyond the register-save area.

SAVE

(see Figure 3-9)

Temp is a temporary register, and n specifies the number of registers
(9 - n) to be saved for the calling function.
SAVE implements a stack frame for use in the C language functioncalling sequence. It should be the first statement in the called function.
(Also see Restore and Return from Procedure instructions') SAVE can
save up to six registers, from register 8 (r8) through register 3 (r3),
freeing them for the new function. After saving these registers, SA VE
adjusts SP and FP to point beyond the end of a fixed-size register-save
area. Figure 3-9 shows the stack after executing 'SAVE %r3'.
Illegal operand exception occurs if expanded-operand type addressing
mode is used.

3-112

SPOP

SPOP
COPROCESSOR OPERATION (no operands)
Coprocessor operation

Assembler
Syntax

SPOP word

Opcode

Ox32

Operation

/* coprocessor operation executes the following
processor operations */
( "word" is written out with an access status of
"coprocessor broadcast" }
( wait for "coprocessor done" }
( a word is written into PSW with an access status of
"coprocessor status fetch" }

Address
Modes

None valid, word

Condition
Flags

Unchanged

Exceptions

External memory fault may occur.

Example

SPOP

SPOP

=

32-bit value

OXFFFFFFFF

3-113

SPOPRS
SPOPRD
SPOPRT

SPOPRS
SPOPRD
SPOPRT
COPROCESSOR OPERATION READ
Coprocessor operation read single
Coprocessor operation read double
Coprocessor operation read triple

Assembler
Syntax

SPOPRS word,src
SPOPRD word,src
SPOPPT word,src

Opcode

Ox22
Ox02
Ox06

Operation

/* coprocessor operation read executes the following
processor operations */
"word" is written out with an access status of
"coprocessor broadcast" }
"src" is read with an access status of
"coprocessor data fetch" }
wait for "coprocessor done" }
a word is written into PSW with an access status of
"coprocessor status fetch" }

Address
Modes

word
src

Condition
Flags

Determined by the coprocessor status

Exceptions

External memory fault may occur.

Example

SPOPRS OxF379FFFF,*$OxFF37
SPOPRD OxFFFFFFFF,%r3
SPOPRT OxOOOOOOOO,(%r4)

3-114

SPOPRS
SPOPRD
SPOPRT

none valid, 32-bit value
all modes except register, literal, or immediate

SPOPS2
SPOPD2
SPOPT2

SPOPS2
SPOPD2
SPOPT2

COPROCESSOR OPERATION, 2-ADDRESS
Assembler
Syntax

SPOPS2 word,src,dst
SPOPD2 word,src,dst
SPOPT2 word,src,dst

Coprocessor operation single,
2-address
Coprocessor operation double,
2-address
Coprocessor operation triple,
2-address

Opcode

Ox23
Ox03
Ox07

Operation

/* coprocessor operation executes the following
processor operations */
"word" is written out with an access status of
"coprocessor broadcast" }
"src" is read with an access status of "coprocessor
<:lata fetch" }
{ wait for "coprocessor done" }
{ a word is written into PSW with an access status of
"coprocessor status fetch" }
{ "dst" is written with an access status of
coprocessor data write" }

Address
Modes

word
src
dst

Condition
Flags

Determined by the coprocessor status

Exceptions

External memory fault may occur.

Example

SPOPS2 OxFF,4(%rO)
SPOPD2 OxFFF,%r3
SPOPT2 OxFE,(%rO)

SPOPWS
SPOPWD
SPOPWT

none valid, 32-bit value
all modes except register, literal, or immediate
all modes except register, literal, or immediate

3-115

SPOPWS
SPOPWD
SPOPWT

SPOPSW
SPOPWD
SPOPWT

COPROCESSOR OPERAnON WRITE
Assembler
Syntax

SPOPWS word,dst
SPOPWD word,dst
SPOPWT word,dst

Coprocessor operation write single
Coprocessor operation write double
Coprocessor operation write triple

Opcode

Ox33
Oxl3
Oxl7

Operation

1* coprocessor operation write executes the following

SPOPWS
SPOPWD
SPOPWT

processor operations *I

( "word" is written out with an access status of

"coprocessor broadcast" }
( wait for "coprocessor done" }
( a word is written into PSW with an access status of
coprocessor status fetch" }
"dst" is written with an access status of
coprocessor data write" }
none valid, 32-bit value
all modes except register, literal, or immediate

Address
Modes

word
dst

Condition
Flags

Determined by the coprocessor status.

Exceptions

External memory fault may occur.

Example

SPOPWS OxOO,%rO
SPOPWD OxOF,(%r1)
SPOPWT OxIOOO,4(%r2)

3-116

STRCPY

STRCPY
STRING COPY
Assembler
Syntax

STRCPY

String copy

Opcode

Ox303S

Operation

while ((*r1 = *rO)!=O)(
{disable interrupts}
rO++;
r1++;
{enable interrupts}

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

External memory fault may occur in the middle of an iteration.

Examples

Before:

STRCPY

rO

I 00 I 00 I 01 I 00 I

r1

I 00 I 00 I 40 I 00 I
+-

increasing bits

The byte locations starting at OxlOO contain the values OxOI, Ox24,
OxE6, Ox7F, Oxll, and OxOO (Iocation OxlOS).
STRCPY
After:

rO

I 00 I 00 I 01 I 05 I

rl

I 00 I 00 I 40 I 05 I

The byte locations from Ox4000 through Ox400S now contain the same
values as locations OxlOO through OxIOS.

3-117

STRCPY
Notes

STRCPY
Opcode occupies 16 bits. All operands are defined implicitly in the
registers, rO and rl, that function as byte pointers. These registers must
be preset with the following information before executing STRCPY:
rO
rl

Address of source string
Address of destination string

STRCPY implements the string-copy function commonly used in C
language. The instruction may be interrupted only at the end of an
iteration. A memory fault may occur in the middle of an iteration. To
restart the instruction after a fault, execute STRCPY again; the
registers are updated after the only memory access that could cause the
fault. The assignment is a byte move, and both RO and Rl are
incremented by 1 at each iteration. Execution of STRCPY is finished
when a null (zero) byte is reached. The null byte is always copied.

3-118

STREND

STREND
STRING END
Assembler
Syntax

STREND

String end

Opcode

Ox301F

Operation

while (*rO !=O) {
rO++;

Address
Modes

None

Condition
Flags

Unchanged

Exceptions

External memory fault may occur in the middle of an iteration.

Examples

Before:

STREND

rO

I 00 I 00 I 04 I 00 I
<-

increasing bits

The byte locations Ox400 through Ox404 contain the values Ox44, Ox55,
OxOl, Ox22, OxOO, respectively.
STREND
After:
Notes

rO

I 00 I 00 I 04 I 04 I

Opcode occupies 16 bits. The operand is defined implicitly in the
register rO, a byte pointer that must be preset with the starting address
of the source C language string. STREND moves the pointer to the
end of the string and could be used as part of a string-length or string·
concatenation function. The instruction may be interrupted at any timL.
A memory fault may occur in the middle of an iteration. To restart the
instruction after a fault, execute STREND again; the register is
updated after the only instruction that could cause the fault. Each
iteration tests a byte and increments the pointer rO by 1. Execution of
STREND terminates when a null (zero) byte is found. rO will be left
with the address of the null byte.

3-119

SUBB2
SUBH2
SUBW2

SUBB2
SUBH2
SUBW2
SUBTRACf
Subtract byte
Subtract halfword
Subtract word

Assembler
Syntax

SUBB2 src,dst
SUBH2 src,dst
SUBW2 src,dst

Opcodes

OxBF SUBB2
OxBE SUBH2
OxBC SUBW2

Operation

dst

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

Exceptions

+-

dst - src

I, if (dst - src)

<

0

N

+-

Z

+-

1, if (dst - src) == 0

C

+-

1, if borrow from sign bit of dst

v

+-

1, if overflow

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if there is truncation.

Examples

3-120

SUBB2 %r6, *$Ox30 (%r2)
SUBH2 %rO,$resulth
SUBW2 %r3,$resultw

SUBB3
SUBH3
SUBW3

SUBB3
SUBH3
SUBW3

SUBTRACT, 3 ADDRESS
Subtract byte, 3 address
Subtract halfword, 3 address
Subtract word, 3 address

Assembler
Syntax

SUBB3 src1 ,src2,dst
SUBH3 src1 ,src2,dst
SUBW3 src1 ,src2,dst

Opcodes

OxFF SUBB3
OxFE SUBH3
OxFC SUBW3

Operation

dst

Address
Modes

src1

all modes

src2

all modes

dst

all modes except literal or immediate

Condition
Flags

N

+-

+-

src2 - src1

< 0

1, if (src2 - srcJ)

Z

1, if (src2 - srcJ)

C

1, if carry out of sign bit of dst

==

0

V I , if overflow
Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.
Integer overflow exception occurs if there is truncation.

Examples

SUBB3 %r3,*$Oxl005,%r2
SUBH3 %rl,%r3,%rO
SUBW3 $Nl,$N2,$result

3-121

SWAPBI
SWAPHI
SWAPWI

SWAPBI
SWAPHI
SWAPWI

SWAP (INTERLOCKED)
Swap byte (interlocked)
Swap halfword (interlocked)
Swap word (interlocked)

Assembler
Syntax

SWAPBI dst
SWAPHI dst
SWAPWI dst

Opcodes

OxlF SWAPBI
OxlE SWAPHI
OxIC SWAPWI

Operation

{set interlock}
tempa - dst
dst - rO
rO - tempa

Address
Modes

dst

Condition
Flags

N -

MSB of rO

Z -

I, if rO == 0

all modes except register, literal, or immediate

C-O

V-O
Exceptions

Illegal operand exception occurs if register, literal, expanded-operand
type, or immediate mode is used for dst.

Examples

The swap instruction can manipulate interlocks for multiprocessors.
Suppose location A is the interlock for a critical section of code, and a
nonzero means the lock is busy. Then, the following instructions
provide a busy-waiting loop:
L1:

Note

3-122

MOVW &1,%rO
SWAPWI A
BNEB L1

Final value of rO sets the condition codes. The SAS code is read
interlocked (7) for both the read and write bus transactions.

TSTB
TSTH
TSTW

TSTB
TSTH
TSTW

TEST
Assembler
Syntax

TSTB src
TSTH src
TSTW src

Test byte
Test halfword
Test word

Opcodes

Ox2B TSTB
Ox2A TSTH
Ox28 TSTW

Operation

src +- 0

Address
Modes

src

Condition
Flags

N +- I, if src < 0 (signed)

all modes

Z

1, if src == 0

C

0

V+-O
Exceptions

None

Examples

TSTH 14(%r2)

Note

This instruction only sets condition codes. Its action is the same as a
compare instruction, where the first operand is zero, such as
CMPB &O,src2
However, test is faster because it is one byte shorter.

3-123

XORB2
XORH2
XORW2

XORB2
XORH2
XORW2

EXCLUSIVE OR
Exclusive OR byte
Exclusive OR halfword
Exclusive OR word

Assembler
Syntax

XORB2 src,dst
XORH2 src,dst
XORW2 src,dst

Opcodes

OxB7
OxB6
OxB4

Operation

dst ... dst • src

Address
Modes

src

all modes

dst

all modes except literal or immediate

Condition
Flags

XORB2
XORH2
XORW2

N ... MSB of dst
Z ... 1, if dst

==

0

C'" 0

v ...

1, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

XORB2 &40,4(%r4)
XORH2 %rl,$result
XORW2 4(%rl),$resuit

3-124

XORB3
XORH3
XORW3

XORB3
XORH3
XORW3

EXCLUSIVE OR, 3 ADDRESS
Assembler
Syntax

XORB3 mask,src,dst
XORH3 mask,src,dst
XOR W3 mask,src,dst

Opcodes

OxF7
OxF6
OxF4

XORB3
XORH3
XORW3

Operation

dst

src "mask

Address
Modes

mask

Condition
Flags

+-

Exclusive OR byte, 3 address
Exclusive OR halfword, 3 address
Exclusive OR word, 3 address

all modes

src

all modes

dst

all modes except literal or immediate

N

+-

MSB of dst

Z

+-

1, if dst

== 0

C+-O

v

+- 1, if result must be truncated to fit dst size

Exceptions

Illegal operand exception occurs if literal or immediate mode is used for
dst.

Examples

XORB3 &4,*12(%r3),*$Ox400
XORH3 %rl,4(%r1),%rO
XORW3 %rO,%r1,%r3

3-125

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Function

3.7.3 Instruction Set Summary by Function

Table 3-12.

Data Transfer Instruction Group

Instruction
Move:
Move byte
Move halfword
Move word
Move address (word)
Move complemented byte
Move complemented halfword
Move complemented word
Move negated byte
Move negated halfword
Move negated word
Move version number
Swap :
Swap byte interlocked
Swap halfword interlocked
Swap word interlocked
Block Operations:
Move block of words
Field Operations:
Extract field byte
Extract field halfword
Extract field word
Insert field byte
Insert field halfword
Insert field word
String Operations:
String copy
String end
Table 3-13.

Opcode

MOVB
MOVH
MOVW
MOVAW
MCOMB
MCOMH
MCOMW
MNEGB
MNEGH
MNEGW
MVERNO

Ox87
Ox86
Ox84
Ox04
Ox8B
Ox8A
Ox88
Ox8F
Ox8E
Ox8C
Ox3009

SWAPBI
SWAPHI
SWAPWI

OxlF
OxlE
OxIC

MOVBLW

Ox3019

EXTFB
EXTFH
EXTFW
INSFB
INSFH
INSFW

OxCF
OxCE
OxCC
OxCB
OxCA
OxC8

STRCPY
STREND

Ox3035
Ox30lF

Arithmetic Instruction Group

Instruction
Add:
Add byte
Add halfword
Add word
Add byte, 3-address
Add halfword, 3-address
Add word, 3-address

3-126

Mnemonic

Mnemonic

Opcode

ADDB2
ADDH2
ADDW2
ADDB3
ADDH3
ADDW3

Ox9F
Ox9E
Ox9C
OxDF
Ox DE
OxDC

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Function

Table 3-13.

Arithmetic Instruction Group (Continued)

Instruction
Subtract:
Subtract byte
Subtract halfword
Subtract word
Subtract byte, 3·address
Subtract halfword, 3-address
Subtract word, 3-address
Increment:
Increment byte
Increment halfword
Increment word
Decrement:
Decrement byte
Decrement halfword
Decrement word
Multiply:
MUltiply byte
Multiply halfword
Multiply word
Multiply byte, 3-address
Multiply halfword, 3-address
Multiply word, 3-address
Divide:
Divide byte
Divide halfword
Divide word
Divide byte, 3-address
Divide halfword, 3-address
Divide word, 3-address
Modulo:
Modulo byte
Modulo halfword
Modulo word
Modulo byte, 3-address
Modulo halfword, 3-address
Modulo word, 3-address
Arithmetic Shift:
Arithmetic left shift word
Ari thmetic right shift byte
Arithmetic right shift halfword
Arithmetic right shift word

Mnemonic

Opcode

SUBB2
SUBH2
SUBW2
SUBB3
SUBH3
SUBW3

OxBF
OxBE
OxBC
OxFF
OxFE
OxFC

INCB
INCH
INCW

Ox93
Ox92
Ox90

DECB
DECH
DECW

Ox97
Ox96
Ox94

MULB2
MULH2
MULW2
MULB3
MULH3
MULW3

OxAB
OxAA
OxA8
OxEB
OxEA
OxE8

DlVB2
DlVH2
DlVW2
DlVB3
DlVH3
DlVW3

OxAF
OxAE
OxAC
OxEF
OxEE
OxEC

MODB2
MODH2
MODW2
MODB3
MODH3
MODW3

OxA7
OxA6
OxA4
OxE7
OxE6
OxE4

ALSW3
ARSB3
ARSH3
ARSW3

Ox CO
OxC7
OxC6
OxC4

3-127

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Function

Table 3-14.

Logical Group

Instruction
AND:
AND byte
AND halfword
AND word
AND byte, 3-address
AND halfword, 3-address
AND word, 3-address
Exclusive OR (XOR):
Exclusive OR byte
Exclusive OR halfword
Exclusive OR word
Exclusive OR byte, 3-address
Exclusive OR halfword, 3-address
Exclusive OR word, 3-address
OR:
OR byte
OR halfword
OR word
OR byte, 3-address
OR halfword, 3-address
OR word, 3-address
Compare or Test:
Compare byte
Compare halfword
Compare word
Test byte
Test halfword
Test word
Bit test byte
Bit test halfword
Bit test word
Clear:
Clear byte
Clear halfword
Clear word
Rotate or Logical Shift:
Rotate word
Logical left shift byte
Logical left shift halfword
Logical left shift word
Logical right shift word

3-128

Mnemonic

Opcode

ANDB2
ANDH2
ANDW2
ANDB3
ANDH3
ANDW3

OxBB
OxBA
OxB8
OxFB
OxFA
OxF8

XORB2
XORH2
XORW2
XORB3
XORH3
XORW3

OxB?
OxB6
OxB4
OxF?
OxF6
OxF4

ORB2
ORH2
ORW2
ORB3
ORH2
ORW3

OxB3
OxB2
OxBO
OxF3
OxF2
OxFO

CMPB
CMPH
CMPW
TSTB
TSTH
TSTW
BITB
BITH
BITW

Ox3F
Ox3E
Ox3C
Ox2B
Ox2A
Ox28
Ox3B
Ox3A
Ox38

CLRB
CLRH
CLRW

Ox83
Ox82
Ox80

ROTW
LLSB3
LLSH3
LLSW3
LRSW3

OxD8
OxD3
OxD2
OxDO
OxD4

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Function

Table 3-15.

Program Control Instructions

Instruction
Unconditional Transfer:
Branch with byte (8-bit) displacement
Branch with halfword (I6-bit) displacement
Jump
Conditional Transfers:
Branch on carry clear byte
Branch on carry clear halfword
Branch on carry set byte
Branch on carry set halfword
Branch on overflow clear, byte displacement
Branch on overflow clear, halfword displacement
Branch on overflow set, byte displacement
Branch on overflow set, halfword displacement
Branch on equal byte (duplicate)
Branch on equal byte
Branch on equal halfword (duplicate)
Branch on equal halfword
Branch on not equal byte (duplicate)
Branch on not equal byte
Branch on not equal halfword (duplicate)
Branch on not equal halfword
Branch on less than byte (signed)
Branch on less than halfword (signed)
Branch on less than byte (unsigned)
Branch on less than halfword (unsigned)
Branch on less than or equal byte (signed)
Branch on less than or equal halfword (signed)
Branch on less than or equal byte (unsigned)
Branch on less than or equal halfword (unsigned)
Branch on greater than byte (signed)
Branch on greater than halfword (signed)
Branch on greater than byte (unsigned)
Branch on greater than halfword (unsigned)
Branch on greater than or equal byte (signed)
Branch on greater than or equal halfword (signed)
Branch on greater than or equal byte (unsigned)
Branch on greater than or equal halfword (unsigned)

Mnemonic

Opcode

BRB
BRH
JMP

Ox7B
Ox7A
Ox24

BCCB
BCCH
BCSB
BCSH
BVCB
BVCH
BVSB
BVSH
BEB
BEB
BEH
BEH
BNEB
BNEB
BNEH
BNEH
BLB
BLH
BLUB
BLUH
BLEB
BLEH
BLEUB
BLEUH
BGB
BGH
BGUB
BGUH
BGEB
BGEH
BGEUB
BGEUH

Ox53*
Ox52*
Ox5B
Ox5A*
Ox63
Ox62
Ox6B
Ox6A
Ox6F
Ox7F
Ox6E
Ox7E
Ox67
Ox77
Ox66
Ox76
Ox4B
Ox4A
Ox5B*
Ox5A*
Ox4F
Ox4E
Ox5F
Ox5E
Ox47
Ox46
Ox57
Ox56
Ox43
Ox42
Ox53*
Ox52*

* Indicates that opcode matches another instruction but operation is the same.

3-129

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Function

Table 3-15.

Program Control Instructions (Continued)

Instruction
Conditional Transfers (Continued):

Mnemonic

Opcode

Return
Return
Return
Return
Return
Return
Return
Return
Return
Return
Return
Return
Return
Return
Return
Return

RCC
RCS
RVC
RVS
REQLU
REQL
RNEQU
RNEQ
RLSS
RLSSU
RLEQ
RLEQU
RGTR
RGTRU
RGEQ
RGEQU

Ox50*
Ox58*
Ox60
Ox68
Ox6C
Ox7C
Ox64
Ox74
Ox48
Ox58*
Ox4C
Ox5C
Ox44
Ox54
Ox40
Ox50*

BSBB
BSBH
JSB
RSB

Ox37
Ox36
Ox34
Ox78

SAVE
RESTORE
CALL
RET

OxlO
Oxl8
Ox2C
Ox08

on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on

carry clear
carry set
overflow clear
overflow set
equal (unsigned)
equal (signed)
not equal (unsigned)
not equal (signed)
less than (signed)
less than (unsigned)
less than or equal (signed)
less than or equal (unsigned)
greater than (signed)
greater than (unsigned)
greater than or equal (signed)
greater than or equal (unsigned)

Subroutine Transfer:

Branch to subroutine, byte displacement
Branch to subroutine, halfword displacement
Jump to subroutine
Return from subroutine
Procedure Transfer:

Save registers
Restore registers
Call procedure
Return from procedure

* Indicates that opcode matches another instruction but operation is the same.

3-130

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Function

Table 3-16.
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor
Coprocessor

Coprocessor Instructions

Instruction
operation
operation read single
operation read double
operation read triple
operation single 2-address
operation double 2-address
operation triple 2-address
operation write single
operation write double
operation write triple

Table 3-17.

Mnemonic
SPOP
SPOPRS
SPOPRD
SPOPRT
SPOPS2
SPOPD2
SPOPT2
SPOPWS
SPOPWD
SPOPWT

Opcode
Ox32
Ox22
Ox02
Ox06
Ox23
Ox03
Ox07
Ox33
Oxl3
Oxl7

Stack and Miscellaneous Instructions

Instruction
Stack Operations:
Push address word
Push word
Pop word
Miscellaneous:
No operation, 1 byte
No operation, 2 bytes
No operation, 3 bytes
Breakpoint trap
Extended opcode
Cache flush

Mnemonic

Opcode

PUS HAW
PUSHW
POPW

OxEO
OxAO
Ox20

NOP
NOP2
NOP3
BPT
EXTOP
CFLUSH

Ox70
Ox73
Ox72
Ox2E
Oxl4
Ox27

3-131

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Mnemonic

3.7.4 Instruction Set Summary by Mnemonic

Mnemonic
ADDB2
ADDB3
ADDH2
ADDH3
ADDW2
ADDW3
ALSW3
ANDB2
ANDB3
ANDH2
ANDH3
ANDW2
ANDW3
ARSB3
ARSH3
ARSW3
BCCB
BCCH
BCSB
BCSH
BEB
BEB
BEH
BEH
BGB
BGEB
BGEH
BGEUB
BGEUH
BGH
BGUB
BGUH
BITB
BITH
BITW
BLB
BLEB
BLEH

Table 3-18. Instruction Set Summary by Mnemonic
Opcode
Instruction
Ox9F
Add byte
OxDF
Add byte, 3-address
Ox9E
Add halfword
Add halfword, 3-address
OxDE
Add word
Ox9C
Add word, 3-address
OxDC
Ox CO
Arithmetic left shift word
OxBB
AND byte
OxFB
AND byte, 3-address
OxBA
AND halfword
AND halfword, 3-address
OxFA
AND word
OxB8
OxF8
AND word, 3-address
Arithmetic right shift byte
OxC7
OxC6
Arithmetic right shift halfword
OxC4
Arithmetic right shift word
Ox53*
Branch on carry clear byte
Ox52*
Branch on carry clear halfword
Ox5B* Branch on carry set byte
Ox5A* Branch on carry set halfword
Branch on equal byte (duplicate)
Ox6F
Ox7F
Branch on equal byte
Branch on equal halfword (duplicate)
Ox6E
Branch on equal halfword
Ox7E
Branch on greater than byte (signed)
Ox47
Branch on greater than or equal byte (signed)
Ox43
Ox42
Branch on greater than or equal halfword (signed)
Ox53*
Branch on greater than or equal byte (unsigned)
Branch on greater than or equal halfword (unsigned)
Ox52*
Branch on greater than halfword (signed)
Ox46
Branch on greater than byte (unsigned)
Ox57
Branch on greater than halfword (unsigned)
Ox56
Bit test byte
Ox3B
Bit test halfword
Ox3A
Ox38
Bit test word
Ox4B
Branch on less than byte (signed)
Branch on less than or equal byte (signed)
Ox4F
Branch on less than or equal halfword (signed)
Ox4E

* Indicates that opcode matches

3-132

another instruction but operation is the same.

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Mnemonic

Table 3-18.
Mnemonic
BLEUB
BLEUH
BLH
BLUB
BLUH
BNEB
BNEB
BNEH
BNEH
BPT
BRB
BRH
BSBB
BSBH
BVCB
BVCH
BVSB
BVSH
CALL
CFLUSH
CLRB
CLRH
CLRW
CMPB
CMPH
CMPW
DECB
DECH
DECW
DIVB2
DIVB3
DIVH2
DIVH3
DIVW2
DIVW3
EXTFB
EXTFH
EXTFW
EXTOP
INCB
INCH
INCW
INSFB

Instruction Set Summary by Mnemonic (Continued)

Opcode
Ox5F
Ox5E
Ox4A
Ox5B*
Ox5A*
Ox67
Ox77
Ox66
Ox76
Ox2E
Ox7B
Ox7A
Ox37
Ox36
Ox63
Ox62
Ox6B
Ox6A
Ox2C
Ox27
Ox83
Ox82
Ox80
Ox3F
Ox3E
Ox3C
Ox97
Ox96
Ox94
OxAF
OxEF
OxAE
OxEE
OxAC
OxEC
OxCF
OxCE
OxCC
Ox14
Ox93
Ox92
Ox90
OxCB

Instruction
Branch on less than or equal byte (unsigned)
Branch on less than or equal halfword (unsigned)
Branch on less than halfword (signed)
Branch on less than byte (unsigned)
Branch on less than halfword (unsigned)
Branch on not equal byte (duplicate)
Branch on not equal byte
Branch on not equal halfword (duplicate)
Branch on not equal halfword
Breakpoint trap
Branch with byte (8-bit) displacement
Branch with halfword (l6-bit) displacement
Branch to subroutine, byte displacement
Branch to subroutine, halfword displacement
Branch on overflow clear, byte displacement
Branch on overflow clear, halfword displacement
Branch on overflow set, byte displacement
Branch on overflow set, halfword displacement
Call procedure
Cache flush
Clear byte
Clear halfword
Clear word
Compare byte
Compare halfword
Compare word
Decrement byte
Decrement halfword
Decrement word
Divide byte
Divide byte 3-address
Divide halfword
Divide halfword, 3-address
Divide word
Divide word, 3-address
Extract field byte
Extract field halfword
Extract field word
Extended opcode
Increment byte
Increment halfword
Increment word
Insert field byte

* Indicates that opcode matches another instruction but operation is the same.
3-133

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Mnemonic

Table 3-18.
Mnemonic
INSFH
INSFW
JMP
JSB
LLSB3
LLSH3
LLSW3
LRSW3
MCOMB
MCOMH
MCOMW
MNEGB
MNEGH
MNEGW
MODB2
MODB3
MODH2
MODH3
MODW2
MODW3
MOVAW
MOVB
MOVBLW
MOVH
MOVW
MULB2
MULB3
MULH2
MULH3
MULW2
MULW3
MVERNO
NOP
NOP2
NOP3
ORB2
ORB3
ORH2
ORH3
ORW2
ORW3
POPW
PUSHAW
PUSHW

3-134

Instruction Set Summary by Mnemonic (Continued)
Opcode
OxCA
OxC8
Ox24
Ox34
OxD3
OxD2
OxDO
OxD4
Ox8B
Ox8A
Ox88
Ox8F
Ox8E
Ox8C
OxA7
OxE7
OxA6
OxE6
OxA4
OxE4
Ox04
Ox87
Ox30l9
Ox86
Ox84
OxAB
OxEB
OxAA
OxEA
OxA8
OxE8
Ox3009
Ox70
Ox73
Ox72
OxB3
OxF3
OxB2
OxF2
OxBO
OxFD
Ox2D
OxED
OxAO

Instruction
Insert field halfword
Insert field word
Jump
Jump to subroutine
Logical left shift byte
Logical left shift halfword
Logical left shift word
Logical right shift word
Move complemented byte
Move complemented halfword
Move complemented word
Move negated byte
Move negated halfword
Move negated word
Modulo byte
Modulo byte, 3-address
Modulo halfword
Modulo halfword, 3-address
Modulo word
Modulo word, 3-address
Move address (word)
Move byte
Move block of words
Move halfword
Move word
Multiply byte
Multiply byte, 3-address
Multiply halfword
Multiply halfword, 3-address
MUltiply word
Multiply word, 3·address
Move version number
No operation, 1 byte
No operation, 2 bytes
No operation, 3 bytes
OR byte
OR byte, 3·address
OR halfword
OR halfword, 3-address
OR word
OR word, 3-address
Pop word
Push address word
Push word

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Mnemonic

Table 3-18.

*

Instruction Set Summary by Mnemonic (Continued)

Mnemonic

Opcode

Instruction

RCC
RCS
REQLU
REQL
RESTORE
RET
RGEQ
RGEQU
RGTR
RGTRU
RLEQ
RLEQU
RLSS
RLSSU
RNEQU
RNEQ
ROTW
RSB
RVC
RVS
SAVE
SPOP
SPOPRS
SPOPRD
SPOPRT
SPOPS2
SPOPD2
SPOPT2
SPOPWS
SPOPWD
SPOPWT
STRCPY
STREND
SUBB2
SUBB3
SUBH2
SUBH3
SUBW2
SUBW3

Ox50*
Ox58*
Ox6C
Ox7C
Oxl8
Ox08
Ox40
Ox50*
Ox44
Ox54
Ox4C
Ox5C
Ox48
Ox58*
Ox64
Ox74
OxD8
Ox78
Ox60
Ox68
OxlO
Ox32
Ox22
Ox02
Ox06
Ox23
Ox03
Ox07
Ox33
Oxl3
Oxl7
Ox3035
Ox30lF
OxBF
OxFF
OxBE
OxFE
OxBC
OxFC

Return on carry clear
Return on carry set
Return on equal (unsigned)
Return on equal (signed)
Restore registers
Return from procedure
Return on greater than or equal (signed)
Return on greater than or equal (unsigned)
Return on greater than (signed)
Return on greater than (unsigned)
Return on less than or equal (signed)
Return on less than or equal (unsigned)
Return on less than (signed)
Return on less than (unsigned)
Return on not equal (unsigned)
Return on not equal (signed)
Rotate word
Return from subroutine
Return on overflow clear
Return on overflow set
Save registers
Coprocessor operation
Coprocessor operation read single
Coprocessor operation read double
Coprocessor operation read triple
Coprocessor operation single 2-address
Coprocessor operation double 2-address
Coprocessor operation triple 2-address
Coprocessor operation write single
Coprocessor operation write double
Coprocessor operation write triple
String copy
String end
Subtract byte
Subtract byte, 3-address
Subtract halfword
Subtract halfword, 3-address
Subtract word
Subtract word, 3-address

Indicates that opcode matches another instruction but operation is the same.

3-135

\INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Opcode

Table 3-18.
Mnemonic
SWAPBI
SWAPHI
SWAPWI
TSTB
TSTH
TSTW
XORB2
XORB3
XORH2
XORH3
XORW2
XORW3

Instruction Set Summary by Mnemonic (Continued)
Opcode
OxlF
OxlE
OxiC
Ox2B
Ox2A
Ox28
OxB7
OxF7
OxB6
OxF6
OxB4
OxF4

Instruction
Swap byte interlocked
Swap halfword interlocked'
Swap word interlocked
Test byte
Test halfword
Test word
Exclusive OR byte
Exclusive OR byte, 3-address
Exclusive OR halfword
Exclusive OR halfword, 3-address
Exclusive OR word
Exclusive OR word, 3-address

3.7.5 Instruction Set Summary by Opcode
Table 3-19.
Menemonic
SPOPRD
SPOPD2
MOVAW
SPOPRT
SPOPT2
RET
SAVE
SPOPWD
EX TOP
SPOPWT
RESTORE
SWAPWI
SWAPHI
SWAPBI
POPW
SPOPRS
SPOPS2
JMP
TSTW
TSTH
TSTB
CALL
BPT
MVERNO
MOVBLW
STREND
STRCPY
3-136

Instruction Set Summary by Opcode

Opcode
Ox02
Ox03
Ox04
Ox06
Ox07
Ox08
Ox 10
Oxl3
Oxl4
Oxl7
Oxl8
OxiC
OxlE
OxlF
Ox20
Ox22
Ox23
Ox24
Ox28
Ox2A
Ox2B
Ox2C
Ox2E
Ox3009
Ox3019
Ox301F
Ox3035

Instruction
Coprocessor operation read double
Coprocessor operation double, 2-address
Move address (word)
Coprocessor operation read triple
Coprocessor operation triple, 2-address
Return from procedure
Save registers
Coprocessor operation write double
Extended opcode
Coprocessor operation write triple
Restore registers
Swap word interlocked
Swap halfword interlocked
Swap byte interlocked
Pop word
Coprocessor operation read single
Coprocessor operation single, 2-address
Jump
Test word
Test halfword
Test byte
Call procedure
Breakpoint trap
Move version number
Move block of words
String end
String copy

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Opcode

Table 3-19.
Mnemonic
SPOP
SPOPWS
JSB
BSBH
BSBB
BITW
BITH
BITB
CMPW
CMPH
CMPB
RGEQ
BGEH
BGEB
RGTR
BGH
BGB
RLSS
BLH
BLB
RLEQ
BLEH
BLEB
RCC
RGEQU
BCCH
BGEUH
BCCB
BGEUB
RGTRU
BGUH
BGUB
RCS
RLSSU
BCSH
BLUH
BCSB
BLUB
RLEQU
BLEUH
BLEUB

Opcode
Ox32
Ox33
Ox34
Ox36
Ox37
Ox38
Ox3A
Ox3B
Ox3C
Ox3E
Ox3F
Ox40
Ox42
Ox43
Ox44
Ox46
Ox47
Ox48
Ox4A
Ox4B
Ox4C
Ox4E
Ox4F
Ox50*
Ox50*
Ox52*
Ox52*
Ox53*
Ox53*
Ox54
Ox56
Ox57
Ox58*
Ox58*
Ox5A*
Ox5A*
Ox5B*
Ox5B*
Ox5C
Ox5E
Ox5F

Instruction Set Summary by Opcode (Continued)
Instruction
Coprocessor operation
Coprocessor operation write single
Jump to subroutine
Branch to subroutine, halfword displacement
Branch to subroutine, byte displacement
Bit test word
Bit test halfword
Bit test byte
Compare word
Compare halfword
Compare byte
Return on greater than or equal (signed)
Branch on greater than or equal halfword (signed)
Branch on greater than or equal byte (signed)
Return on greater than (signed)
Branch on greater than halfword (signed)
Branch on greater than byte (signed)
Return on less than (signed)
Branch on less than halfword (signed)
Branch on less than byte (signed)
Return on less than or equal (signed)
Branch on less than or equal halfword (signed)
Branch on less than or equal byte (signed)
Return on carry clear
Return on greater than or equal (unsigned)
Branch on carry clear halfword
Branch on greater than or equal halfword (unsigned)
Branch on carry clear byte
Branch on greater than or equal byte (unsigned)
Return on greater than (unsigned)
Branch on greater than halfword (unsigned)
Branch on greater than byte (unsigned)
Return on carry set
Return on less than (unsigned)
Branch on carry set halfword
Branch on less than halfword (unsigned)
Branch on carry set byte
Branch on less than byte (unsigned)
Return on less than or equal (unsigned)
Branch on less than or equal halfword (unsigned)
Branch on less than or equal byte (unsigned)

* Indicates that opcode matches another instruction but operation is the same.

3-137

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Opcode

Table 3-19.
Mnemonic
RVC
BVCH
BVCB
RNEQU
BNEH
BNEB
RVS
BVSH
BVSB
REQLU
BEH
BEB
NOP
NOP3
NOP2
RNEQ
BNEH
BNEB
RSB
BRH
BRH
REQL
BEH
BEB
CLRW
CLRH
CLRB
MOVW
MOVH
MOVB
MCOMW
MCOMH
MCOMB
MNEGW
MNEGH
MNEGB
INCW
INCH
INCB
DECW
DECH
DECB
ADDW2
ADDH2
ADDB2

3-138

Instruction Set Summary by Opcode (Continued)

Opcode
Ox60
Ox62
Ox63
Ox64
Ox66
Ox67
Ox68
Ox6A
Ox6B
Ox6C
Ox6E
Ox6F
Ox70
Ox72
Ox73
Ox74
Ox76
Ox77
Ox78
Ox7A
Ox7B
Ox7C
Ox7E
Ox7F
Ox80
Ox82
Ox83
Ox84
Ox86
Ox87
Ox88
Ox8A
Ox8B
Ox8C
Ox8E
Ox8F
Ox90
Ox92
Ox93
Ox94
Ox96
Ox97
Ox9C
Ox9E
Ox9F

Instruction
Return on overflow clear
Branch on overflow clear, halfword displacement
Branch on overflow clear, byte displacement
Return on not equal (unsigned)
Branch on not equal halfword (duplicate)
Branch on not equal byte (duplicate)
Return on overflow set
Branch on overflow set, halfword displacement
Branch on overflow set, byte displacement
Return on equal (unsigned)
Branch on equal halfword (duplicate)
Branch on equal byte (duplicate)
No operation, 1 byte
No operation, 3 bytes
No operation, 2 bytes
Return on not equal (signed)
Branch on not equal halfword
Branch on not equal
Return from subroutine
Branch with halfword (J 6-bit) displacement
Branch with byte (8-bit) displacement
Return on equal (signed)
Branch on equal halfword
Branch on equal byte
Clear word
Clear halfword
Clear byte
Move word
Move halfword
Move byte
Move complemented word
Move complemented halfword
Move complemented byte
Move negated word
Move negated halfword
Move negated byte
Increment word
Increment halfword
Increment byte
Decrement word
Decrement halfword
Decrement byte
Add word
Add halfword
Add byte

INSTRUCTION SET & ADDRESSING MODES
Instruction Set Summary by Opcode

Table 3-19.

Instruction Set Summary by Opcode 

1)

PCBP 2 (PSW

0)

INIT PC
INIT SP
PSW

'SAVE' AREA
FOR CONTROL
REGISTERS.

PC

PCBP 2+4

SP

PCBP 2+8

STACK LOWER BOUND

STACK BOUNOS

ST ACK UPPER BOUND
r10
r9

'SAVE' AREA
FOR GENERAL
REGISTERS.

rO

I

PCBP 2+60
PCBP 2+64

r8

BLOCK SIZE
BLOCK AODRESS

FIRST
BLOCK MOVE

I

BLOCK DATA

I
BLOCK SIZE
BLOCK AODRESS

NEXT
BLOCK MOVE

I
I
•

BLOCK DATA

f

-----

_NULL ~~OVE

31

Figure 4-1.

4-8

:

-----------BLOCK SIZE

=

0

{
0

A Typical Process Control Block

OPERATING SYSTEM CONSIDERATIONS
Memory Specifications

Initial Context for a Process
The initial context of the executing process is set up as follows:
o The PCBP, stored in memory, points to the initial-context area of its PCB .
• The initial PSW occupies the first PCB location, and its I bit should be set (1) to
identify that the process starts executing from its initial context. (The R bit should be
set if this process will use general registers.) See 4.2.4 Processor Status Word and
4.4.1 Context Switching Strategy for more details about the R and I bits.
o The second PCB word, the initial PC, is the address of the first instruction that process
executes.
co The third PCB word contains the initial SP (the address of the first location on the
execution stack).
co The seventh and eighth PCB words define the upper and lower limits of the execution
stack.
The values in the initial-context area and the stack bounds never change during normal
execution.
Saved Context for a Process
When a process switch occurs, the processor uses the current PCBP to save the context of
Process A (the executing process) in the current PCB. Using offsets from PCBP to access
the correct PCB location for Process A, the processor stores PC, PSW, SP, and if the PSW
R bit is set to 1, the general registers. It then reads in a new PCBP value for Process B
(the incoming process) and loads the Process B context from its PCB.
Memory Specifications
On each process switch, if the R bit in the PSW is set (I), the processor, using information
in the process PCB, performs a series of block moves. The PCB provides three elements
for each block move (see Figure 4- 1):
1.

Block size - This word value specifies the length of the block (number of words to be
moved) and implicitly identifies the starting location of the next block-move area.

2.

Block address - This word value is the destination address where the processor starts
writing the block data.

3.

Block data - This series of words represents the data to be moved. If the system has
an MMU, it could be the information written to MMU registers (or tables) to set up
the memory context for the new process.

The processor executes a move block (MOVBL W) instruction for each block until a zerolength block (Block size = 0) is reached.

4-9

OPERATING SYSTEM CONSIDERATIONS
Processor Status Word

A memory management scheme does not alter the way the processor performs the block
moves or how many block moves occur. However, memory management may affect block
addresses. Systems with an MMU should use a virtual address for each block when the
MMU is enabled and physical addresses when the MMU is disabled. For a system
without an MMU, a block address must be a physical address.

4.2.4 Processor Status Word
The processor maintains a 32-bit processor status word (PSW) register which defines the
state of a currently running process. Table 4-3 identifies its contents.
The read-only fields of the PSW cannot be altered by software regardless of the execution
mode. An exception or process switch always directly affects the ET, ISC, and TM fields.
The ET and ISC fields, which identify the type and cause of an exception, are part of the
exception mechanism described in 4.6 EXCEPTIONS. The TE and TM fields are part of
the trace-trap mechanism.
An instruction may read the PSW at any time, but may write it explicitly only when the
process is in kernel mode. However, the processor implicitly alters some fields during
normal execution at other levels. In particular, most instructions change the condition
flags.

4.3 SYSTEM CALL
The system-call (gate) mechanism provides a means of controlled entry into a function by
installing a new PSW and PC value. If the new PSW has a different privilege level than
the current PSW, a transition to a different execution level occurs.
On simpler processors, a trap or supervisor call instruction picks up a new PC and PSW
from a fixed location. Then the software has to perform further indirection based on the
"trap number:' The gate mechanism, embodied in its gate (GATE) instruction,
automatically performs this second level of indirection for the user. The gate mechanism is
described 4.3.1 Gate Mechanisms.

4-10

OPERATING SYSTEM CONSIDERATIONS
Processor Status Word

Table 4-3. Processor Status Word Fields
Bit(s)

Field

Contents

Description

0-1

ET

Exception
Type

This read-only field indicates the type of exception
generated during operations and is interpreted as:
Code Description
00
On Reset Exception
01
On Process Exception
10
On Stack Exception
On Normal Exception
11

2

TM

Trace
Mask

The read-only TM field enables masking of a trace
trap. This bit masks the trace enable (TE) bit for
the duration of one instruction to avoid a trace trap.
The TM bit is set (I) at the beginning of every
instruction and cleared (0) as part of every
microsequence that performs a context switch or a
return from gate.

3-6

ISC

Internal
State
Code

This 4-bit code distinguishes between exceptions of
the same exception type. The ISC is a read-only
field.

7-8

RI

RegisterInitial
Context

9-10

PM

11-12 CM

These bits control the context switching strategy.
The I bit (bit 7) determines if a process executes
from initial or intermediate context. The R bit (bit
8, read only) determines if the registers of a process
should be saved. It also controls block moves to
change map information.
Previous
This field defines the previous execution level. The
Execution code is interpreted as:
Level
Code Description
00
Kernel level
01
Executive level
Supervisor level
10
User level
11
Current
This field defines the current execution level. The
Execution CM code is interpreted the same way as the PM
Level
code. Changes to the CM field via instructions with
the PSW as an explicit destination may cause the
XMD pins to change in the middle of a memory
access, which could cause a spurious exception or
system problem. Therefore, only microsequence
instructions should be used to change the CM field
state.

4-11

OPERATING SYSTEM CONSIDERATIONS
Processor Status Word

Table 4-3. Processor Status Word Fields (Continued)
Bit(s)

Field

Contents

Description

13-16

IPL

Interrupt
Priority
Level

The IPL field represents the current interrupt priority level.
Fifteen levels of interrupts are available. An interrupt,
unless it is a nonmaskable interrupt, must have a higher
priority level than the current IPL in order to be
acknowledged. Therefore, level 0000 indicates that any of
the fifteen interrupt priority levels <0001 through 1111) can
interru pt the microprocessor; level 1111, the highest
interrupt priority level, indicates that no interrupts (except a
nonmaskable interrupt) can interrupt the microprocessor.

17

TE

Trace
Enable

This bit enables the trace function. When TE is set (I), it
causes a trace trap to occur after execution of the next
instruction. Debugging and analysis software use this
facility for single-stepping a program. Changes to the state
of the TE bit via instructions with the PSW as an explicit
destination may cause unpredictable trace behavior.
Therefore, only microsequence instructions should be used to
change the TE bit state.

18-21

NZVC

Condition
Codes

The condition codes reflect the resulting status of the most
recent instruction execution that affects them. These codes
are tested using the conditional branch instructions and
indicate the following when set (1):
N - Negative (bit 21)
V - Overflow (bit 19)
(bit 18)
(bit 20)
Z - Zero
C - Carry

22

OE

Enable
Overflow
Trap

This bit enables overflow traps. It is cleared (0) whenever
an overflow trap is detected and handled.

23

CD

Cache
Disable

This bit enables and disables the instruction cache. When
the CD bit is set (1), the cache is not used. Changes to the
state of the CD bit via instructions with the PSW as an
explicit destination may corrupt the contents of the
instruction cache. Therefore, only microsequence
instructions should be used to change the CD bit state.

24

QIE

QuickInterrupt
Enable

The QIE enables and disables the quick-interrupt facility. If
QIE is set (1), an interrupt is handled via the
quick-interrupt sequence.

25

CFD

Cache
Flush
Disable

When this bit is set (1), it disables cache flushing (emptying
of the instruction cache contents) during the
XSWITCH TWO microsequence.

Unused

These bits are not used and are always cleared (0).

26-31

4-12

OPERATING SYSTEM CONSIDERATIONS
Handling-Routine Tables

4.3.1 Gate Mechanism
The CPU contains a microsequence program that locates the handling routine for the gate
mechanism. To use this mechanism, the operating system must provide the following gate
mechanism tables:
• Pointer table - Contains the 32-bit starting addresses for a set of handling-routine tables.
The processor assumes address 0 as the beginning of the table. The table contains
thirty-two 4-byte (word) addresses, one for each handling-routine table.
Note: Use of kernel level is forced whenever this table is accessed during execution of the
GATE instruction.
II

Handling-routine tables - Each table in the set contains the entry points (PSW and PC
values) for a group of functions. A table is limited to 4096 two-word entries; one a new
PSW and the other a new PC (in that order) for a controlled transfer.

Two indexes, obtained from a GATE instruction's implied operands, locate the appropriate
PC and PSW pair for the controlled transfer.

Pointer Table
This table contains thirty-two entries and starts at location o. It must be contained in
secure memory (write permission for kernel level only) to prevent unwarranted access. The
first entry is reserved for normal-exception handling. Therefore, address 0 must locate the
handling-routine table (entry point set) for the normal-exception handlers.
The rest of the addresses in the pointer table may define sets of entry points for controlled
transfers. For example, one entry can be used to locate the handling-routine table for
kernel level entries, one entry for executive level entries, one for supervisor level entries,
and one for user level entries.
All thirty-two entries in the pointer table must be defined. A typical use for the remaining
entries is to define all unused pointer table entries to point to a dummy handling-routine
table. The dummy table is typically used to prevent an exception from occurring should an
offset into the pointer table result in locating an undefined handling-routine table.

Handling-Routine Tables
A handling-routine table stores a maximum of 4096 entry points (PSW and PC pairs) and
may be placed anywhere in memory (virtual memory if the system has an MMU that is
enabled; physical memory if it does not). However, each must start at an address that is a
multiple of eight. In a typical system, the handling-routine tables for entry into kernel
level reside in a section of memory that is shared by all processes.
Note: Sections of memory do not imply execution level. The GATE instruction forces
kernel level before it accesses any handling-routine tables. To preserve table security, these
tables should be protected so only the kernel level can write to them.

4-13

OPERATING SYSTEM CONSIDERATIONS
GATE Instruction

4.3.2 GATE Instruction
The GATE instruction is modeled after the jump to subroutine USB) instruction rather
than the call procedure (CALL) instruction which calls a function. In the typical system
environment (e.g., UNIX System, C compiler), the compiler generates a call to an
assembly-language function which then executes the gate instruction. GATE needs only to
execute a simple jump since the 'call frame' already exists.
Although GATE may be executed at any privilege level, the CPU forces and releases
kernel level for memory access. The gate instruction has two entry points. GATE starts
execution at the first entry point, while the on-normal exception microsequence enters at
the second (see 4.6 EXCEPTIONS). The second entry point is also the start of the gate
mechanism.
Before a GATE instruction is executed, two registers must be loaded:
• Register 0 (rO) must be loaded with the offset for constructing index1 (the index into
the pointer table). Indexl identifies the starting address of the appropriate handlingroutine table. Only five bits of rO are used .
• Register 1 (rI) must be loaded with the offset for constructing index2 (the index into
the handling-routine table). Index2 locates the new PSW and PC.
The on-normal exception microsequence is modelled after a GATE. On a normal
exception, the CPU supplies all appropriate information needed to execute a GATE-like
sequence.
The GATE instruction executes the following tasks in sequence (see Figure 4-2).

First Entry Point
I.

GATE forces kernel level on memory accesses and checks the current SP against the
upper- and lower-stack bounds in the currently executing process PCB. A memory
exception on accessing either of the stack bounds from the PCB causes a process
exception (GATE-PCB). If SP is outside either boundary, a stack exception (stack
bound) is generated. GATE then releases kernel level for memory accesses.

2.

GATE writes 1,0, 2 to the ISC, TM, and ET fields, respectively, of PSW. Then it
saves the address of the next instruction (PC + 2) and the current PSW on the
execution stack. If a memory exception occurs on the stack accesses, the processor
generates a stack exception (stack).

3.

GATE computes index 1 for the pointer table by masking the contents of rO with Ox7C
and places the result in tempa. It then masks the contents of rl with Ox7FF8 for
index2 and stores the result in tempb. (Special registers tempa and tempb are used in
later steps for accessing the handling-routine tables.)

4-14

OPERATING SYSTEM CONSIDERATIONS
Second Entry Point

Second Entry Point - The Gate Mechanism
1.

GATE again forces kernel execution level for memory accesses.

2.

GATE uses tempa as a pointer to read the starting address of a handling-routine table
from the pointer table and write it to tempa. It then adds tempa and tempb (the
offset into the handling-routine table) and stores the result, index2, in tempb. This is
the address of the new PSW and entry point PC for the GATE jump.

3.

GATE uses index2 to get new values for PSW fields OE, NZVC, TE, CM, R, and 1.
It then sets PSW fields ISC, TM, and ET to 7, 0, and 3, respectively.

4.

GATE uses index2 to locate and load the new PC.

5.

GATE adjusts SP to a location above the saved PC and PSW (thus completing a push
of the PC and PSW onto the stack) and releases kernel level for memory accesses.

The processor then begins executing the handling routine. When the routine finishes, a
return from gate (RET G) instruction returns to the function that issued the system call.
Note: If the GATE instruction is invoked directly, a memory exception that occurs during
the remaining steps causes a normal exception (gate-vector). A normal-exception
microsequence entering here will already have kernel level in effect and values in temp a
and tempb. Entering at this point from a normal-exception microsequence means that a
memory exception for any step generates a reset exception (gate-vector).

ADDRESS

a

POINTER
TABLE

INDEX1!

HANDLING-ROUTINE
TABLE

INDEX2 !

NEW PSW

1----NEW PC

indexl
index2
Entry Address for Handler Routine

Figure 4-2.

rO & Ox7C
rl & Ox7FF8
(Address Pointed to by index!)

J

+

ONE ENTRY

index2

Tables for the Gate Mechanism

4-15

OPERATING SYSTEM CONSIDERATIONS
Return-From-Gate Instruction

4.3.3 Return-From-Gate Instruction
The return-from-gate (RETG) instruction is modeled after a return-from-subroutine
(RSB) instruction rather than after a return-from-procedure (RET) instruction. Unlike
the gate instruction, RETG enforces linear ordering of execution levels, which means the
new execution level may not be more privileged than the current level. During an RETG,
the microsequence forces and releases kernel level as required for memory access.
The return-from-gate instruction performs the following sequential actions to return to the
calling function.
1.

Retrieves the old PSW and next-instruction address (stored on the execution stack by
the corresponding GATE) and places these in tempa and tempb, respectively.

2.

Sets the trace mask (TM) bit in PSW to zero.

3.

Compares the CM field in the current PSW to the CM field of the old PSW (in
tempa) to verify that the new execution level is less than or equal to the current level.
If this test fails, the microprocessor issues a normal exception (illegal-level change).

4.

Writes the PSW fields OE, NZVC, TE, CM, PM, R, and I using the values in tempa
(the saved PSW).

5.

Loads PC from tempb.

6.

Adjusts SP to the location below the saved PSW and PC (thus completing a pop of
the PSW and PC from the stack).

7.

Writes 7, 0, and 3 to PSW fields ISC, TM, and ET, respectively.

The function that called the GATE then starts executing its next instruction.
Note: If a memory exception occurs on a stack access during these steps, a stack
exception is issued.

4.4 PROCESS SWITCHING
Using its PCB, the WE 32100 Microprocessor explicitly invokes a process by automatically
saving or restoring its context. However, a PCB only defines hardware context (as
described in 4.2.3 Process Control Block), not software-maintained information (i.e.,
variables and arguments pointed to by the argument pointer and frame pointer) for the
process. The PCBP register always contains the address of the PCB of the current process.
To avoid destroying the PCB content on a process switch, the call process (CALLPS)
instruction performs both the save of the previous context and load of the new process
context. The processor does not accept interrupts until the CALLPS instruction is
completed. This prevents an undefined state between a save and a load. In this state, a
PCBP would still point to the PCB for the old (exiting) process. If the system completes a
save just as an interrupt occurs, then the interrupt-handling scheme causes the saved PCB
context to be overwritten. This cannot happen with the WE 32100 Microprocessor.

4-16

OPERATING SYSTEM CONSIDERATIONS
I Bit

4.4.1 Context Switching Strategy
The process-switch mechanism uses two PSW parameter bits, R and I, to control the
context-switching strategy:
• The R bit determines if the CPU general registers used by a process should be saved. It
also controls block moves .
• The I bit determines if a process executes from an initial context or intermediate context.
It also affects the setting of the PCBP register.
To save or load the appropriate information on a process switch, the processor uses the R
and I bits in the PSW of the new or incoming process. The use of the R and I bits is
explained next.

R Bit
The use of the R bit is explained by considering two processes: Process A as the current or
old process, and Process B as an incoming process. If Process B's PSW R bit is set, this
signifies that Process B wants to use the general registers, and thus the CPU's general
registers are saved in Process A's PCB save area for general registers when the process
switch occurs. Later, on return to Process A, the general registers will be restored for
Process A. If Process B requires block moves, the R bit must be set. On a process switch,
where a CALLPS (call process instruction) or simulated CALLPS is performed, the
processor saves general registers for Process A and performs block moves contained in
Process B if the R bit of Process B's PSW is set. When a process switch occurs as a result
of the RETPS instruction, the general registers are restored if Process A's PSW R bit is
set. (This value was copied from Process B's PSW when CALLPS occurred.)
To generalize, set the R bit in the initial-context PSW of any process that uses the general
registers or requires block moves. The R bit setting never changes, even though a process
switches in and out many times.

I Bit
The I bit function identifies whether a process is to start from an initial or intermediate
context. It also affects the PCBP register.
Consider two processes: Process A, the current or old process, and Process B, the incoming
or new process. The function of the I bit is explained as follows:
.. On leaving Process A, the microprocessor always writes the PC, SP, and PSW values
starting at the location pointed to by Process A's PCBP and then saves Process A's
PCBP on the interrupt stack. On entry to Process B, the microprocessor always reads
the PSW, PC, and SP values starting from the location pointed to by the Process B's
PCBP. These operations are the same for the CALLPS instruction, full interrupts, and
exceptions that perform a process switch.

4-17

OPERATING SYSTEM CONSIDERATIONS
I Bit

• If the I bit is set (1) in Process B's PSW, Process B's PCBP is incremented by twelve
bytes (three words) after the PSW, PC, and SP are loaded, and the I bit is set to zero.
Incrementing the PCBP guarantees that the initial context loaded in the first step will
not be overwritten if Process B is interrupted or executes a CALLPS instruction.
Clearing the I bit ensures that the adjustment of the PCBP is done only once. (If this
was not done and the I bit was to remain set, and if Process B was repeatedly
interrupted and resumed, Process B's PCBP would be incremented by twelve on each
RETPS instruction,)

• When Process B executes a RETPS instruction, Process A's PC, SP, and PSW context is
loaded from the locations pointed to by PCBP popped off the interrupt stack.
The main idea is that the effect of the I bit of a given process is not seen until that process
is itself interrupted and then returned to by another process.
If the I bit of a process is set when it is entered initially, the process' initial context will be
preserved if it is interrupted or if it calls another process. The saved context will be
written to and retrieved from the twelve bytes adjacent to the initial context. Otherwise, if
the I bit is zero initially, the initial context (if writable) will be overwritten in the course of
servicing the interrupt or CALLPS instruction.

Another way to look at the I bit is that if the PSW I bit feature did not exist, and the user
wanted to modify the PCBP via software to save the initial process context, it could not be
guaranteed that the PCBP would be adjusted before another interrupt was taken. Since
the I bit adjustment is done in a CPU microsequence, it guarantees that the PCBP
adjustment is made while the CPU is immune to interrupts.
The following describes the effects on the PCBP and the initial- and saved-context areas
during process switches.
When Process A is called initially by the CALLPS instruction (an explicit process switch),
the processor loads the PCBP register with the starting address (Address A) of the
Process A PCB (see part A of Figure 4-3). It then loads the PSW, the program counter
(PC), and the stack pointer (SP) with their initial context. Next, if the I bit in the PSW
is set (1), the processor clears the I bit and increments the PCBP register by twelve bytes
to the saved-context area (Address B) of the Process A PCB (see part B of Figure 4-3).
This will cause any later process switch to save PSW, PC, and SP values in the
intermediate context area instead of overwriting the initial-context values. The Process A
initial-context area and its PCBP stored in memory are not affected on this process switch.
Part A of Figure 4-4 shows the effect on the PCBP and the Process A PCB if a process
switch occurs before Process A is finished. Here, the processor uses the adjusted PCBP
(assuming the I bit was set when Process A was initiated) to save the intermediate context
of the control registers and stores the PCBP on the interrupt stack. This time, the PSW I
bit will be clear and the PC points to the next Process A instruction.
When the processor restores Process A (see part B of Figure 4-4), the processor retrieves
the PCBP from the interrupt stack. Remember that the PCBP points to the saved-context

4-18

OPERATING SYSTEM CONSIDERATIONS
I Bit

area (if the initial I bit value was zero, then the saved-context area overwrote the initialcontext area) and the I bit of the PSW is clear. The processor then loads the control
registers with their intermediate context and Process A resumes execution with its next
instruction. If the initial value of the I bit for Process A was clear (0), then the initialcontext area becomes the save area since the PCBP was never adjusted to point to the
saved-context area. That is, the Address B in Figures 4-3 and 4-4 is the same as Address
A, and the initial-context area no longer exists.
The initial context of a process never changes, provided the initial I bit setting is one.
Also, the PCBP stored in memory always points to the initial context. This enables an
interrupt-handler process to get its PCBP from memory without going through a scheduler.
A suspended process restarts from an intermediate context on a return from a full-interrupt
handler, certain exception handlers, or the RETPS (return-to-process) instruction. Also, a
process that had an initial I bit value of zero is restarted from an intermediate context on
any subsequent CALLPS instruction after it was first switched to. A process starts from
its initial context (initial I bit value is set) whenever a CALLPS instruction is executed.
PCB
ADDRESS A

MEMORY

INITIAL PSW
INITIAL PC

ADDRESS A

INITIAL SP

(PCBP FOR PROCESS A)
ADDRESS B

A.

-

PCBP

SAVE AREA

Context at Start of Switch to Process A

PCB
ADDRESS A

MEMORY

INITIAL PSW

ADDRESS A

INITIAL PC

(PCBP FOR PROCESS A)

INITIAL SP
ADDRESS B

B.

Figure 4-3.

SAVE AREA

~ PCBP

Context After Switch to Process A

A PCB on an Initial Process Switch to a Process

4-19

OPERATING SYSTEM CONSIDERATIONS
Call Process Instruction

PCB

MEMORY
ADDRESS A

I

INITIAL PSW

ADDRESS A

INITIAL PC

(PCBP FOR PROCESS A)

INITIAL SP

g

SAVED PSW

ADDRESS B

INTERRUPT STACK

SAVED PC
SAVED SP

•
•

·
A.

f

SAVE AREA
( INTERMEDIATE CONTEXT)

L

Context After Switch to Some Other Process

PCB
ADDRESS A

INITIAL PSW
INITIAL PC

MEMORY
ADDRESS A

INITIAL SP

(PCBP FOR PROCESS A)

ADDRESS B

OBSOLETE PSW

~ PCBP

OBSOLETE PC
OBSOLETE SP

•
•
•
B.

Context After Process A Is Switched Back to and Restored

Figure 4-4.

A PCB on a Process Switch During Execution of a Process

4.4.2 Call Process Instruction
The call process (CALLPS) instruction, mentioned in the discussion of the R and I bits, is
the process analog of the call procedure (CALL) and save registers (SAVE) instructions
that carry out a function call. To execute CALLPS, the processor must be in kernel mode.
In addition, rO must be preloaded with the new PCBP (address of the PCB for the new
process) .

4-20

OPERATING SYSTEM CONSIDERATIONS
Call Process Instruction

The call process instruction performs an explicit process switch. Using Process A as the
current (old) process and Process B as the incoming (new) process, CALLPS performs the
following sequential steps:
1.

Places the content of rO (Process B PCBP) into register tempa and forces kernel
execution level on memory accesses.

2.

Saves Process A PCBP on the interrupt stack (see Interrupt Stack and ISP under
4.5.2 Interrupt Mechanism). If a memory exception occurs when accessing this stack,
the processor issues a reset exception (interrupt stack).

3.

Adjusts PC to the address of the instruction that Process A would have executed next
(PC + 2).

4.

Calls the function XSWITCH_ONEO to save Process A context. (All writes are
made to the saved-context area of process PCB because the I bit of an executing
process PSW is always clear.) If a memory exception occurs on a PCB access, the
processor issues a process exception (old PCB).
XSWITCH_ONE does the following:

5.

a.

Using tempa as a pointer to the Process B PCB, copies the R bit from the new
PSW into the R bit of the current PSW. (The R bit will be used later.)

b.

Stores the current PSW in the Process A PCB and writes 0, 0, 1 to the ISC, TM,
and ET fields, respectively, of the saved PSW.

c.

Saves PC (address of the next instruction) and SP in the Process A PCB.

d.

Writes rO through rIO to the general register area of the Process A PCB if the R
bit of the Process B PSW is set. Otherwise, these registers are not saved.

e.

Returns control to CALLPS.

Calls the function XSWITCH TWOO to load the Process B context. If a memory
exception occurs when accessi~g its PCB, the processor issues a process exception (new
PCB).
XSWITCH_TWO does the following:
a.

Loads PCBP from tempa (which contains Process B's PCBP value).

b.

Reads in the new PSW and sets its TM bit to O. Next, it loads the new PC and
SP. PC now contains the address of the first instruction for Process B.

c.

Tests the PSW I bit. If the I bit is set, the I bit is cleared, and the PCBP is
adjusted to the saved-context area of the Process B PCB.

d.

Returns control to CALLPS.

4-21

OPERATING SYSTEM CONSIDERATIONS
Return-to-Process Instruction

6.

Writes 7, 0, 3 to the ISC, TM, and ET fields, respectively, of the PSW.

7.

Calls the function XSWITCH_THREEO for block moves.
XSWITCH_THREE does the following:
a.

Tests the R bit in the PSW .
• If the R bit is set, it loads the block-move information from the block-move
areas of the Process B PCB. For each block to be moved, it preloads rO with
the starting address of the block-move area, rl with the size of the block
(number of words to be moved), and r2 with the destination of the move. Then
it executes a move block (MOVBL W) instruction .
• If the R bit is clear (0), no block moves are performed.

b.
8.

Returns control to CALLPS.

Releases kernel execution level on memory accesses and Process B begins executing.

4.4.3 Return-to-Process Instruction
The RETPS instruction restores a process from its interrupted state and may be executed
only when the processor is in kernel mode. RETPS is the process analog of a function
return that uses the restore registers (RESTORE) and return-from-procedure (RET)
instructions. Again, the R and I bits in the PSW determine the context-switching strategy.
The CALLPS and RETPS instructions act similarly, except the RETPS does not save the
context of the exiting process. For this discussion, Process A is the returned-to-process.
RETPS performs the following sequential steps:
I.

Forces kernel execution level on memory access and moves the Process A PCBP from
the interrupt stack into register tempa. If a memory exception occurs on the stack
access, the processor issues a reset exception (interrupt-stack).

2.

Loads the PSW R bit with R bit from tempa.

3.

Calls XSWITCH_TWOO to restore the Process A context. If a memory exception
occurs when accessing its PCB, process exception (new PCB) is issued. (The PCBP
for Process A is still at the top of the interrupt stack.)
XSWITCH_TWO does the following:
a.

Loads PCBP from tempa.

b.

Loads PSW from the PCB, writes a 0 to the TM bit, and then loads PC and SP.
Because this is a return process, the I bit is clear and all control registers are
loaded from the saved-context area of its PCB.

c.

Returns control to RETPS.

4.

Writes 7, 0, 3 to the ISC, TM, and ET fields, respectively, of PSW.

5.

If R bit is set (1), calls XSWITCH]HREEO to perform any block moves.

4-22

OPERATING SYSTEM CONSIDERATIONS
Interrupt-Handler Model

XSWITCH_THREE does the following:
a.

Tests the R bit in the PSW .
• If the R bit is set (I), it does the block moves in the block-move areas of the
Process A PCB. For each block to be moved, rO gets the starting address of a
block-move area in the PCB, r1 gets the size of the block (number of words to
be moved), and r2 gets the destination of the move. Then the function executes
a move block instruction (MOVBL W).

• If the R bit is clear (0), no block moves are performed.
b.
6.

Returns control to RETPS.

If the R bit is set (1), RETPS loads rO-r10 from general register save area of

Process A PCB.
7.

Releases kernel execution level on memory accesses and Process A resumes executing.

4.5 INTERRUPTS
When an external device requests an interrupt, a processor temporarily stops its current
execution and jumps to code that services the interrupt. On completion of the interrupt
handler code, execution resumes at the point where the interrupt occurred. An interrupt
mechanism performs the execution switch.

4.5.1 Interrupt-Handler Model
An interrupt handler may be modeled after a gate (system call) or process switch. In most
existing architectures, an interrupt handler is a function that is invoked on an interrupt.
The function executes as part of the interrupted process context or as part of a system-wide
context. Although easy to implement, the function call does not isolate interrupt handlers,
execute them at any level, or return from them to a different process.
The WE 32100 Microprocessor uses either the process switch or gate switch. In the
process switch model, an interrupt (called a full interrupt in this case) causes an implicit
process switch to a new process. In the gate switch model, an interrupt (called a quick
interrupt in this case) causes an implicit gate to a handler function. When full interrupts
are used, the processor interrupt mechanism meets the isolation and execution-level
requirements because each interrupt handler is a separate process with its own execution
stack. The processor tracks full-interrupt nesting in such a way that a full-interrupt
handler at any priority level may preempt the original process, thus meeting the return
requirement. With the quick-interrupt feature, interrupts can be handled as described
above for most existing architectures.
For efficient operation, the implicit process switch on a full interrupt does the following:
• Minimizes the loading and saving of an interrupt handler's context
• Allocates only one stack to each interrupt-handler.

4-23

OPERATING SYSTEM CONSIDERATIONS
Interrupt Mechanism

4.5.2 Interrupt Mechanism
There are three functions of the interrupt mechanism:
o Determining whether or not there will be an interrupt.
• Determining how an interrupt request will be acknowledged and what the interrupt-ID
value is.
o

Saving the old context and bringing in a new context.

The first part involves checking the NMINT and IPL[3-01 pins, and the IPL field of the
PSW. The next part involves the NMINT, AVEC, IPL[3-01 and INTOPT pins, and an
interrupt acknowledge or auto-vector interrupt acknowledge bus cycle. The final part
involves the QIE field of the PSW and a quick-interrupt (gate-like) sequence or a fullinterrupt (process-switch) sequence.
The following algorithm describes the interrupt behavior. The notation used is:
• 1==1 if there is to be an interrupt
• ID is the value used as the interrupt-ID in the on-interrupt microsequence
• NMI, INTOPT, and AVEC represent the complements of the values of the nonmaskable
interrupt (NMINT), interrupt option (INTOPT), and auto-vector (AVEe) pins,
respectively.
1=0;
if(NMI==1) {
1=1;
10=0;
else if«requestedjnterrupUevel) > (PSW ))
1=1;
if(AVEC== 1)
ID=(INTOPT concatenated with interrupt request level);
else ID=(value fetched in interrupt acknowledge cycle);
}

if(I==l) {
call on-interrupt microsequence;
}

else {
no interrupt;
An interrupt occurs if the priority level requested is greater than the priority level in the
'IPL field of the PSW. Thus, if PSW==15, no interrupts will be acknowledged
(except for nonmaskable interrupt).

4-24

OPERATING SYSTEM CONSIDERATIONS
Full-Interrupt Handler's PCB

After acknowledging an interrupt (full or quick as determined from Table 2-4), the
processor performs its on-interrupt micro sequence (an implicit process or gate switch). Its
actions are similar to a call process (CALLPS) instruction for a full interrupt and a gate
(GATE) instruction for a quick interrupt, but with a few differences.
When a full interrupt activates an interrupt-handler process, the interrupt handler starts
from its initial state. However, unlike ordinary processes, this initial context consists of
only the three registers and the stack bounds; general registers are not loaded for any
process starting from an initial context.
A higher priority interrupt may interrupt the current interrupt-handler process. When this
happens, its intermediate context is stored in the save area of the PCB, rather than the
initial-context area. Thus, the interrupted interrupt handler can resume execution from that
point later.
The I bit in the process PSW controls which starting point and context to use (see 4.4.1
Context Switching Strategy).
To return from a full interrupt, an interrupt-handler process executes a return-to-process
(RETPS) instruction. This process switch does not save the state of the exiting interrupthandler process (see 4.4.3 Return-to-Process Instruction).
When a quick interrupt activates an interrupt handler, the current PC and PSW values are
stored on the execution stack. A simulated gate is then performed to load the PC and
PSW registers with the initial information for the interrupt handler. A quick-interrupt
gate does not perform any stack bounds check; therefore, quick interrupts should not occur
in processes where the stack may be bad (e.g., a user process with a stack that is
unreliable). Also, a quick-interrupt gate sets the PSW interrupt priority level (IpL) field
to 15, thus disabling all interrupts except a nonmaskable interrupt.
Only a nonmaskable interrupt may interrupt the current quick-interrupt handler. When
this happens, the PC and PSW values of the interrupted interrupt handler are stored on the
execution stack and another simulated gate is performed. Thus, the interrupted interrupt
handler can resume execution from its interrupted state.
To return from a quick interrupt, an interrupt handler should restore the IPL field in the
PSW and then execute a return from gate (RETG) instruction (see 4.3.3 Return-FromGate Instruction).

Full-Interrupt Handler's PCB
Before an interrupt handler is activated, its PCBP points to the initial-context area of its
PCB, which contains initial values for the PSW, PC, and SP. The IPL field in this PSW
is usually set at least as high as the priority level of the device associated with the interrupt
handler. (Interrupt-priority levels range from 0, the lowest, to 15, the highest, which
indicates "no interrupts.") In addition, the I bit in this PSW should contain 1. If the
interrupt handler wants to use the general registers, the PSW R bit should be 1.

4-25

OPERATING SYSTEM CONSIDERATIONS
Interrupt Stack and ISP

If the new PSW has its I bit set when an interrupt handler is activated, the I bit in the
PSW register is cleared and the PCBP register is adjusted to the saved-context area of the
handler's PCB. The save area is used to store the handler's control registers if another
interrupt occurs.
If the PSW's I bit is set, an interrupt-handler process always starts from the same initial
state whenever it is initially activated because its initial-context values never change.
However, after being interrupted, the saved-context area always reflects its state at the
time of the interrupt. Thus, the restored interrupt handler starts from the appropriate
intermediate state.

An interrupt handler's MMU map specification, if maintained in the PCB block-move
areas, is used when loading an initial context or restoring an intermediate context.
Therefore, the user must ensure that the operating system restores the map data to its
initial state before a return-from-interrupt. This can be done by maintaining appropriate
R bit values in the PCBs involved.

Interrupt Stack and ISP
The user must design the operating system to allocate memory space for one interrupt
stack. This system data structure enables the processor to track the nesting of interrupt
handlers and active processes and is never used as an execution stack.
The processor uses its interrupt stack pointer (ISP) register to access the interrupt stack.
This privileged register always contains the address of the top of the stack. When it saves
the current PCBP, a CALLPS or on-interrupt microsequence automatically increments ISP
by four. A RETPS decrements ISP by four when it restores the PCBP. An attempt to
write this register other than in kernel level causes a normal exception privileged register.
At any level of full-interrupt handling, the interrupt stack contains the PCBPs for all lower
priority interrupt handlers that were interrupted while executing. The entry at the bottom
of the stack is the PCBP for the process that was interrupted by the first interrupt handler
(see Figure 4-5).
INTERRUPT STACK
E!--

ISP

PCBP PROCESS N+1
PCBP PROCESS N

PCBP PROCESS B
PCBP PROCESS A
PROCESS B INTERRUPTED PROCESS A.
PROCESS N+1 IS LAST PROCESS INTERRUP'ED.

Figure 4-5.

4-26

An Interrupt Stack

OPERATING SYSTEM CONSIDERATIONS
Interrupt-Vector Table

Because a return-from-process (RETPS) restores the process that was interrupted, the
process at the bottom of the stack is eventually restored. However, any interrupt handler
whose PCBP is on this stack may force a return to a different process. If any interrupt
handler does this, be sure that it overwrites the normal-process PCBP at the bottom of this
stack with the PCBP of the desired process.
Interrupt-Vector Table
The user must provide interrupt-vector tables for full and quick interrupts, depending on
how interrupts are to be handled (process switches and/or gates). Figure 4-6 shows the
memory locations where interrupt PCBPs and PC/PSW pairs must be stored. If the
nonmaskable and auto-vector interrupts are not used, those locations can be used to store
the PCBPs for device-interrupt handlers. The full-interrupt-vector table starts at location
140 (8C hex) to store the PCBP (up to 256 PCBPs) for each interrupt handler and the
quick-interrupt-vector table starts at location 1164 (48C hex) to store PC/PSW pairs (up
to 256 pairs) for each interrupt handler. Commonly, each device that requests an interrupt
may require a different handling routine. The processor locates the appropriate interrupt
handler by using an 8-bit code (interrupt-ID) as an offset into the vector tables. The code
is used to form the address (140 + 4*interrupt-ID) to obtain the PCBP for a full-interrupt
handler or the address (1164 + 8*interrupt-ID) to obtain the PC/PSW pair for a quickinterrupt handler.

Hex
Address
8C

Hex
Address
48C

Nonmaskable Interrupt
Handler PCBP
"0 word)
8F
90
Auto-vector
Interrupt
Handler PCBPs
(31 words)
lOB
10C
Device Interrupt
Handler PCBPs
(224 words)
48B

493
494

Nonmaskable Interrupt
Handler PC/PSW Pair
(2 word)
Auto-vector
Interrupt Handler
PC/PSW Pairs
(62 words)

58B
58C
Device Interrupt
Handler
PC/PSW Pairs
(448 words)
C8B

A. Full-Interrupt Vector Table

B. Quick-Interrupt Vector Table

Figure 4-6. Interrupt Vector Tables

4-27

OPERATING SYSTEM CONSIDERATIONS
On-Interrupt Microsequence

4.5.3 On-Interrupt Microsequence
The on-interrupt microsequence is a sequence of actions built into the WE 32100
Microprocessor that responds to interrupts. The on-interrupt microsequence handles both
full and quick interrupts. For full interrupts, the processor performs an implicit process
switch. For quick interrupts, the processor performs a GATE-like PSWfPC switch. Here,
Process A is the interrupted process and Process B is the interrupt handler. (See 4.4.2 Call
Process Instruction for descriptions of the XSWITCH functions.)
The microsequence performs the following sequential steps:
1.

Writes the interrupt-ID to register tempa. If a memory exception occurs, the
processor generates a stack exception (interrupt-ID fetchr

2.

Forces kernel level on memory accesses.

3.

Skips to step 12 if it is a quick interrupt (the PSW's QIE field is set to I).

4

Performs steps 5 through 11 for a full interrupt.

5.

Forms an index 140+4*tempa, which is written to tempa. This index is used to
locate the PCBP of the appropriate interrupt handler.

6.

Stores the Process A PCBP on the interrupt stack. If a memory exception occurs on
this stack operation, the processor generates a reset exception (interrupt stack).

7.

Calls XSWITCH_ONEO to store the Process A context in the saved-context area of
its PCB and then writes 0, 0, 1 to the ISC, TM, and ET fields, respectively, of the
saved PSW. If any of these operations causes a memory exception, the processor
generates a process exception (old-PCB).

8.

Calls XSWITCH_TWOO to load the Process B PCBP and new PC, PSW, and SP
values from the initial-context area of its PCB. A memory exception on any
XSWITCH_TWO operation causes a process exception (new-PCB). If it is set, the
PSW I bit will be cleared and PCBP adjusted to the saved-context area of Process B
PCB.

9.

Writes 7, 0, 3 to the PSW's ISC, TM, and ET fields, respectively.

10.

Calls XSWITCH_THREEO to make any necessary block moves. A memory
exception here causes a process exception (new-PCB).

11.

Releases kernel level on memory accesses. For full interrupts, this is the last step of
the on-interrupt microsequence.

12.

Resumes quick interrupt here.

13.

Forms an index, 1164+tempa*8, which is written to tempa. This index is used to
locate the PSW and PC of the appropriate interrupt handler.

14.

Releases kernel level on memory accesses.

4-28

OPERATING SYSTEM CONSIDERATIONS
Exceptions

15.

Pushes the PSW and PC of Process A onto the execution stack.

16.

Forces kernel level on memory accesses.

17.

Sets the PSW with value indexed by tempa, and PC with value indexed by 4+tempa.
Some fields in the PSW are unchanged. Also, the IPL field is set to 15 to mask any
subsequent interrupts. If a memory exception occurs, a normal exception (gate
vector) is generated.

18.

Releases kernel level on memory accesses. For quick interrupts this is the last step of
the on-interrupt microsequence.

Process B (the interrupt handler) takes its priority level from the PSW that was just
loaded and starts executing. Execution may be interrupted only by a higher priority
interrupt (higher than the IPL value of the PSW).

4.5.4 Returning From an Interrupt
Full Interrupts
A full-interrupt handler may restore the inte~rupted process or may return to another
process after servicing the interrupting device. To accomplish either process switch, the
full-interrupt handler must contain a return-to-process (RETPS) instruction. Unlike the
call process, RETPS does not save the exiting process (interrupt handler) context.
Note: If a full-interrupt handler is not to return to the process interrupted, the interrupthandler routine must alter the interrupt stack before a RETPS instruction. The PCBP for
the process returned to must replace the PCBP that was saved for the interrupted process.
The PCBP of the process to which the return-from-interrupt occurs is removed from the
interrupt stack. The full context of the returning process is restored from its PCB, and any
required map changes are made (block moves are performed).

Quick Interrupts
A quick-interrupt handler returns to the function that was interrupted (i.e., restores the PC
and PSW registers with the values popped off the execution stack). To return from a
quick-interrupt handler, the handler must execute a return-from-GATE (RETG)
instruction. Also, before returning from a quick interrupt, the IPL field of the PSW
should be set to the previous state of the interrupted process.

4.6 EXCEPTIONS
An exception is an error condition, other than an interrupt, that requires special processing
for recovery. That is, an exception mechanism is needed to correct the error condition so

4-29

OPERATING SYSTEM CONSIDERATIONS
Levels of Exception Severity
that normal processing can continue. Exceptions are caused by the following three types of
events:
• Internal faults - error conditions detected by the processor during instruction execution.
The fault handler for such events may restart the instruction that caused the fault.
• External faults - error conditions detected outside the processor and conveyed to it over
its fault input. The processor recognizes the fault during instruction execution and the
appropriate fault handler may then restart the execution .
• Traps - internal error conditions detected by the processor at the end of an instruction.
After the trap is handled, execution may resume with the next instruction.
The exception mechanism for the WE 32100 Microprocessor is implemented through
microsequences. Depending on the level of exception severity, the microprocessor responds
with the appropriate microsequence to facilitate correction of the condition.

4.6.1 Levels of Exception Severity
The processor recognizes four levels of exception severity, with zero (0) as the highest
level. It uses the ET (exception type) and ISC (internal state code) fields of the PSW to
identify the severity and type of exception, respectively. Because all exception
microsequences preserve the ET and ISC values in the current PSW, the incoming
exception handler may use them. The ET value gives the class of exception and
corresponds to its severity level, while ISC distinguishes among error conditions of the
same class. During normal program execution, ET is 3 and ISC is 7. Table 4-4 identifies
the severity levels, giving the ET value in decimal. The meaning of the ISC values for
each exception severity level is identified later.

4.6.2 Exception Handler
On-stack, on-process, and on-reset exception microsequences do not use the ET and ISC
values, but preserve them for an incoming exception handler. The on-normal exception
microsequence uses them to locate the appropriate handling routine, as well as preserving
them.

Table 4-4.
ET

Level

Processor Response

0

Reset
Process
Stack
Normal

Executes on-reset microsequence; highest severity level
Executes on-process exception microsequence
Executes on-stack exception microsequence
Executes on-normal exception microsequence; lowest
severity level

1

2
3

4-30

Severity Levels for Exceptions

OPERATING SYSTEM CONSIDERATIONS
Exception Handler

The ET and ISC values help identify the task an exception handler must perform. What
an exception handler should do with the ET and ISC values or how it should handle the
error depends on the needs of the system. In general, if computation can continue,
resumption of the process may be chosen. However, if an error is too serious for the
original process to continue its computations, the exception handler should ask the
scheduler to terminate the bad process.
The operating system designer must provide exception-vector tables. Figure 4-7 shows the
addresses where the vector tables reside. All locations must be filled with either PCBPs or
the address of the handling-routine table (for normal exceptions).

Hex
Address
00

03
04

Normal Exception
Pointer Table Entry
(1 word)
Gate Pointer
Table
(31 words)
(Not Used by
Exception
Handler)

7F
80
83
84

87

Reset Exception
Handler PCBP
(1 word)
Process Exception
Handler PCBP
(I word)

88

8B

Stack Exception
Handler PCBP
(I word)

Figure 4-7. Exception-Vector Table

4-31

OPERATING SYSTEM CONSIDERATIONS
Exception Microsequences

4.6.3 Exception Microsequences

The processor's microsequences enable it to execute an appropriate sequence of actions
when it detects an exception. By design, an exception that occurs during one of these
microsequences has a higher severity level. Such an exception, therefore, stops the current
microsequence, and the processor starts performing a higher level microsequence. Thus,
the processor can ripple up levels of exception severity.
Any exception during an on-reset sequence (the severest exception level) causes the
processor to restart the on-reset sequence. Trying to recover from the exception, the
processor goes into an infinite loop and consequently can recover from transient faults.
The sections that follow describe the error conditions for each class of exception and the
response of the microsequence. When describing this response, Process A is the process
that caused the exception and Process B is the exception handler. In general, a normal
exception results in a simulated gate instruction, but a stack, process, or reset exception
causes an implicit process switch. Descriptions of microsequences follow the operating
system instructions at the end of this chapter.
Normal Exceptions

This group of exceptions includes most of those that occur in other microprocessor
architectures. Table 4-5 identifies the ISC and the cause of each normal exception.
When a normal exception occurs, the processor executes the on-normal exception
microsequence. After some set up operations, the microsequence enters the gate instruction
at its second entry point (see 4.3.2 Gate Instruction). Using the ISC code, this simulated
GATE finds the appropriate exception-handler function and transfers control to it. Both
the microsequence and the exception handler execute within the process that caused the
error condition.
To locate the exception handler, GATE requires two implied operands that serve as indexes
into the pointer table and the correct handling-routine table. (See 4.3.1 Gate Mechanism
for a description of these tables') For GATE indexl, the microsequence supplies the value
of O. For GATE index2, it uses the internal-state code (ISC) in the saved PSW, shifted
three bits toward the most significant bit. This shifted ISC value forms an index into the
handling-routine table. Thus, a normal exception results in a controlled transfer to the
corresponding exception handler. On completion of the on-normal exception
microsequence, the ISC, TM, and ET fields of the PSW presented to the exception handler
will contain 7, 1,3, respectively.
Because a normal-exception handler executes as part of Process A, it uses the same
execution stack. After handling the error condition, a normal-exception handler must
execute a return from gate instruction to restore control to Process A.

4-32

OPERATING SYSTEM CONSIDERATIONS
Stack Exceptions

Table 4-5.
ISC

Exception

0

Integer zero divide
(Internal fault)
Trace
(Trap)
Illegal opcode
(Internal fault)
Reserved opcode
(Internal fault)

1
2

3

4

Invalid descriptor
(Internal fault)

5

External memory
(External fault)
Gate vector
(External fault)
Illegal level change
(Internal fault)
Reserved data type
(Internal fault)
Integer overflow
(Internal fault)

6
7
8

9

10

11-13
14

15

Privileged opcode
(Internal fault)
Unused
Breakpoint
(Trap)
Privileged register
(Internal fault)

Normal Exceptions (ET=3)
Cause

An attempt to divide by zero. This exception is
always enabled. (Note 1)
Normal response to the end of an instruction if the
TE bit is set in the PSW.
Use of an undefined opcode.
Use of an opcode reserved for future implementation.
This is also the normal response to the extended
opcode (EXTOP) instruction.
Use of literal or immediate address mode for a
destination operand; instruction's opcode requests
the effective address of a literal, immediate, or
register operand. (Note 1)
A exception when accessing external memory.
A memory exception when accessing the gate tables as
part of a GATE.
An attempt to increase the current execution
privilege level on a RETG.
Use of an operand type that is not defined for the
expanded-operand type address mode. (Note 1)
An attempt to write data into a destination that is
too small. This exception is enabled when the OE
bit is set in the PSW. (Note 2)
An attempt to execute an opcode defined for kernel
level at a different execution level.

Normal response to a breakpoint trap (BPT)
instruction.
An attempt to write the ISP, PCBP, or PSW
when not in kernel level. (Note 1)

Notes:
1. This exception sets the condition flags as if the instruction was successfully completed.
2. Before the overflow trap occurs, the processor may execute the next instruction after
the one that caused the overflow.
Stack Exceptions
Table 4-6 lists the ISC and the cause of each stack exception. A stack-bound exception
occurs when the stack-bound check fails on a system call (a gate instruction or on-normal
exception microsequence). A stack fault occurs on an execution stack access to save the

4-33

OPERATING SYSTEM CONSIDERATIONS
Stack Exceptions

current PC and PSW. An interrupt-ID-fetch exception occurs during the on-interrupt
microsequence if an exception occurs during the acknowledge access.
On a stack fault, the memory exception occurs when SP is used as an operand. Thus, the
processor first detects a normal exception and then detects the stack exception while
executing the implicit GATE (system call). In effect, the processor automatically ripples
up to a stack exception from a normal exception.
A stack exception occurs because Process A (the process at fault) cannot use its execution
stack. As a result, a stack exception cannot be handled as part of Process A (unlike
normal exceptions). Instead, the processor performs the on-stack exception microsequence,
which performs a process switch and thus provides the exception handler with a new
execution stack.
The interrupt-ID-fetch exception does not involve the stack, but it is treated as a stack
exception since it is systemwide. Thus, no context information is lost.
The on-stack exception microsequence saves the Process A PCBP on the interrupt stack,
stores the control registers in its PCB, and loads a new PCBP (for Process B) from location
136 (88 hex). Then it carries out an implicit process switch to the stack-exception handler,
Process B. Although the microsequence does not use the ISC value, it preserves this value
across the process switch. On completion of the microsequence, the ISC field in the PSW
saved for Process A still contains the code for the stack exception, and the TM and ET
fields contain 0 and 3, respectively. When Process B starts executing, the PSW's ISC,
TM, and ET fields contain 7, 0, 3, respectively.
Because a stack-exception handler is implemented as a process, the user may want to
prevent interrupts from entering the handler. Entry prevention is accomplished by raising
the interrupt priority level (the IPL field of its PSW) to 15 and thus disabling all
interrupts except a nonmaskable interrupt. Such a stack-exception handler should execute
only a few instructions.
A stack-exception handler can correct a stack-bound or stack-fault problem by:
• Growing the stack of the process
• Bringing in a missing page of the stack (in demand-paging systems).
Table 4-6.
ISC

Exception

Cause

0

Stack bound
(Internal fault)
Stack
(External fault)
Interrupt ID fetch
(External fault)

An SP value outside the upper or lower stack bound
on a system call.
A memory exception when storing the PC or PSW on
the execution stack during a system call.
A memory exception during the interrupt acknowledge
access during an interrupt sequence.

1

3

4-34

Stack Exceptions (ET = 2)

OPERATING SYSTEM CONSIDERATIONS
Reset Exceptions

Process Exceptions
A process exception is generated if the process receives a memory exception signal on a
PCB access. The exception is local to Process A (the process that caused it) and implies a
~evere error condition. The ISC field of the Process A PSW is presented to the exception
handler (Process B) and identifies the condition that caused the exception. Table 4-7 lists
the ISC and the cause for each process exception.
When a process exception occurs, the processor executes its on-process exception
microsequence, an implicit process switch. Because the error condition signifies that the
Process A PCB cannot be accessed, its context cannot be saved. The microsequence stores
the Process A PCBP on the interrupt stack and loads the Process B PCBP from location
132 (84 hex). Then it loads the Process B context, preserving the ISC value from the
Process A PSW. When Process B begins executing, its PSW contains the code for the
exception condition, and the TM and ET fields contain 0 and 3, respectively.
Because the processor could not save the Process A hardware context, Process B normally
kills Process A. However, it can identify an old (good) process from its PCBP on the
interrupt stack. If the exception is a new PCB exception, the Process A PCBP is at the top
of the interrupt stack. If it is an old PCB exception and a process switch from a third
process (Process C) had been made previously, then the Process C PCBP is the second
element from the top of the stack. In either case, Process B could restart the last good
process because its context was not lost.

Reset Exceptions
A reset exception implies an error condition in accessing critical system data and requires
restarting of the system. On a reset exception, the processor acts as if an external reset
occurred. The ISC field in the PSW of the current process identifies if the condition is an
internal error or external request for a system reset. Table 4-8 lists the ISC and cause of
the reset exceptions.
Table 4-7.

Process Exceptions (ET = 1)

ISC

Exception

Cause

0

Old PCB
(External fault)
Gate PCB
(External fault)
New PCB
(External fault)

A memory exception when accessing the PCB for the
exiting process on a process switch.
A memory exception when accessing the PCB for a stack
bounds check during a GATE.
A memory exception when accessing the PCB for the new
process during a process switch.

1

4

4-35

OPERATING SYSTEM CONSIDERATIONS
Memory Management for Virtual Memory Systems

On a reset exception, the processor performs an implicit process switch. It executes the
On-Reset microsequence after first disabling the memory management unit. The
microsequence picks up a new PCBP from physical address location 128 (80 hex) and
loads the reset-handler process (Process B). When Process B begins executing, its PSW
contains the code corresponding to the condition that caused the reset exception, and its
TM and ET fields contain 0 and 3, respectively.
Process B should restart the system (i.e., reinitialize the system), possibly after checking
the validity of system data.
Table 4-8.

Reset Exceptions (ET=O)

ISC

Exception

Cause

0

Old PCB
(External fault)
System data
(External fault)
Interrupt stack
(External fault)
External reset
(External fault)
New PCB
(External fault)
Gate-vector
(External fault)

A memory exception when accessing the PCB of a processexception handler.
A memory exception when accessing an interrupt vector
or while processing an exception.
A memory exception when accessing the interrupt stack
while processing an exception.
Normal response to an external (system) reset signal.

1

2
3
4

6

A memory exception when accessing the PCB of an
exception-handler process.
A memory exception when accessing a gate table while
processing a normal exception. (Here, the PSW ET
field contains O. If ET is 3, a gate-vector exception
is treated as a normal exception because it occurred
during a GATE instruction, rather than as part of
the on-normal exception microsequence.>

4.7 MEMORY MANAGEMENT FOR VIRTUAL MEMORY SYSTEMS
When a virtual memory system is used for a WE 32100 Microprocessor based system, a
memory management unit (MMU) is required. The main function of an MMU is to
translate virtual addresses into physical addresses. The MMU has the additional
responsibility of providing protection for the system memory space.
The virtual address space is divided into a number of sections by the MMU. Each section
is in turn subdivided into segments. Segments may either be contiguous or paged and are
mapped into physical address space by the MMU.
The WE 32101 Memory Management Unit (MMU) was developed to complement the
WE 32100 Microprocessor for creation of a virtual memory system. This section describes
the features of the MMU that are important for system design. A complete technical
summary of the MMU is provided in the WE 32101 Memory Management Unit Data
Sheet.

4-36

OPERATING SYSTEM CONSIDERATIONS
Memory Management for Virtual Memory Systems
The WE 32101 Memory Management Unit divides the virtual address space into four
sections and provides both contiguous and paged segments for the system. A contiguous
segment can be as large as 128 Kbytes and a paged segment can contain up to sixty-four
2 Kbyte pages.
The MMU divides virtual addresses into three fields for contiguous segments and four
fields for paged segments. A virtual address referencing a contiguous segment is divided
into three fields: a section ID (SID) field, a segment select (SSL) field, and a segment
offset (SOT) field: The SID field specifies the section of virtual address space, the SSL
field specifies the segment within the section, and the SOT field specifies the byte within
the segment. The format of these virtual addresses is shown on Figure 4-8.
For paged segments, the SOT field is subdivided into a page select (psL) field and a page
offset (POT) field. The PSL field specifies which page within the segment and the POT
field specifies which byte within the page. The format of these virtual addresses is shown
on Figure 4-9.
The MMU performs address translation using descriptors that contain the information
necessary for segment and page mapping. The MMU has two types of descriptors:
segment descriptors (SO) for mapping contiguous and paged segments and page descriptors
(PO) for mapping pages within paged segments. An SO contains a segment base address
that is added to an offset (from the virtual address SOT) to form the physical address.
The PO contains a page base address that is concatenated with a page offset (from the
virtual address POT) to form the physical address.
Other fields contained in SOs and POs provide functions other than address translation.
For example, the access fields in the SOs are used by the MMU to enforce protection of
system memory. This field and other fields are described later in this section.
The SOs for each of the four sections of virtual memory are located in physical memory in
segment descriptor tables (SOTs). There is one SOT associated with each section. The
POs for each paged segment are located in physical memory in page descriptor tables
(POTs), and there is one POT associated with each paged segment. Contiguous segments
are represented by an SOT entry, while paged segments are represented by both an SOT
entry and an entire POT (the SOT entry contains the physical base address of the POT).

I

31 30
SID

29 17
SSL

16 0
SOT

Figure 4-8. Virtual Address Fields For a Contiguous Segment

I

31 30
SID

29 17
SSL

16 11
PSL

10 0
POT

Figure 4-9. Virtual Address Fields For a Paged Segment

4-37

OPERATING SYSTEM CONSIDERATIONS
Memory Management for Virtual Memory Systems

Figure 4-1 C is a model showing how a virtual address is translated to a physical address for
a contigucus segment. The SID field is used to find the base address of the required SDT.
(The base address of the SDT for each section is stored in the MMU.) This address and
the SSL field are combined to index an SD within the SDT. The starting physical address
of the contiguous segment is contained in the indexed SD. This address is added to the
SOT field to form the required physical address.
Figure 4-11 shows the paged segment model. This translation is identical to the contiguous
segment address translation up to the point where the SD is indexed. For paged segments,
the addrcss in the SD is used as the base address of a PDT. This address is combined with
the PSL field to index a PD. This PD contains the starting address of the paged segment
that is concatenated with the POT field to form the required physical address.

VIRTUAL ADDRESS
SID I SSL I SDT

BASE

~
+ .,"'"
OF SDT _,t

--£>f

lL
SDT
BASE
ADDRESS
TABLE
(SRAMA)

INDEXED
SEGMENT
DESCRIPTOR

SDT 0

SD
SOT 1

D
D

STARTING
ADDRESS OF

~"'H,"'",

+

SEGMENT ~t.
SgT

TRANSLATED
PHYSICAL
ADDRESS

////

SDT 2

SDT 3

D

PHYSICAL
MEMORY

SEGMENT
DESCRIPTOR
TABLES

Figure 4-10. Virtual to Physical Translation for Contiguous Segments

4-38

]

CONTIGUOUS
SEGMENT

VIRTUAL ADDRESS

D
o
o
o

SOT
BASE
ADDRESS
TABLE
(SRAMA)

SOT 1

D
D
D
SOT 2

SOT 3

SEGMENT
DESCRIPTOR
TABLES

"'"
I

W

""

INDEXED
PAGE
DESCRIPTOR

I

PO

I6rb ~6~~g~G
I

PO

I PDT I

F PAGE

D '" "
D

o
~~
g~ ~>

ADDRESS

~ ~
~Z

0
0

g:

0

PAGE
DESCRIPTOR
TABLES

Figure 4-11. Virtual to Physical Translation for Paged Segments

~

~
00

<

~
!3 00
~

..-3

-~

i~
PHYSICAL
MEMORY

~n
~O

=Z
e:.oo
~

.....
0

o
~

>

~

!3 ~
~

~~
~O
~

~

Z

00

OPERATING SYSTEM CONSIDERATIONS
Initializing the Memory Management Unit

4.7.1 Initializing the Memory Management Unit
The operating system is required to initialize the MMU. Typical MMU initialization
consists of:
• Defining physical memory with segment descriptor tables and page descriptor tables for
each process
• Writing SDT addresses and length into MMU section RAMs.
The operating system should also set up the block-move area of the process control block
(PCB) for each process in the system. Block moves can be used to set the MMU section
RAMs, if desired, when process switches occur. Setting the section RAMs causes the
MMU to flush its caches.
Defining Virtual Memory
The operating system must define the way virtual memory is to be configured. In systems
using an MMU this requires that segment and page descriptor tables be set up in physical
memory. The way these tables are set up determines which segments in virtual memory
are to be contiguous or paged and where the segments and pages reside in physical
memory.
Peripheral Mode
The peripheral mode of the MMU is used by the operating system in several ways. One
use is to initialize some of the internal elements of the MMU. The elements that require
initialization are the section RAMs and the configuration register (CR). Section RAMs
are loaded with the SDT's base addresses and length. The descriptor caches may be
preloaded to avoid miss-processing (for a real-time process or other special case).
Other uses of the peripheral mode by the operating system include:
• Setting or clearing the configuration register referenced and/or modified bits
• Reading the fault code register (FLTCR) and fault address register (FLTAR) in order
to handle MMU-generated exceptions
• Reading the cache contents in the case of serious exceptions (e.g., double-page-hit).
4.7.2 MMU Interactions
The MMU interacts with the operating system through address translation, missprocessing, exception detection, and other events. Once the MMU is initialized, it
translates virtual addresses by using the SDs and PDs. It caches descriptors from the
SDTs and PDTs to minimize translation time. The MMU handles the transfer of
descriptors between its caches and physical memory during miss-processing without
operating system intervention. The MMU also checks for violations (e.g., address or
access) without operating system action. If violations occur, exceptions are issued and the
operating system's exception handler can respond accordingly.

4-40

OPERATING SYSTEM CONSIDERATIONS
Efficient Mapping Strategies

MMU Exceptions
Operating system action is required when the MMU signals to the CPU that an exception
(external fault) has occurred. The MMU detects several exceptions that relate to errors
(such as memory exceptions when the MMU does not correctly read an SDT or PDT) and
places the corresponding code in the fault code register (FLTCR) and the fault address
register (FL TAR).
Other exceptions signal that data is not present in physical memory. In these cases, the
MMU tells the CPU that a required page or segment is not in physical memory and must
be brought into physical memory. The operating system is responsible for these activities;
it must do any I/O that is necessary and adjust the appropriate SDT and/or PDT values.
The MMU provides hardware support for operating system page- or segment-replacement
algorithms by setting the Rand M bits in the segment and page descriptors whenever a
segment or page is referenced or modified. If the operating system periodically clears all
of the R bits, for example, it can use the R bits to implement a variation of the least
recently used (LRU) replacement algorithm. It could choose to replace segments or pages
that still have their R bits clear when an exception occurs, reasoning that those segments or
pages have been referenced less recently than the ones with the R bits set.

Flushing
The operating system occasionally alters the contents of the descriptor tables in memory.
For example, it must do this to set and clear bits that indicate whether a page or segment
is present whenever they are swapped in and out of physical memory. Any alteration of
the table contents must be followed by some type of flushing of the MMU caches to
prevent the chaos that would result if tables and caches contained conflicting information.
If the operating system alters a table entry for one page or segment, it must flush the
cache entry for that page or segment, if there is such a cache entry. If the operating
system alters or deletes many entries in a table, it may be more efficient to flush an entire
section than to flush several cache entries one at a time.

4.7.3 Efficient Mapping Strategies
The memory mapping defined by the operating system may have an enormous effect on the
performance of the system. There are some basic rules for efficient mapping strategies.
Large blocks that will remain in physical memory for long periods could be defined as
contiguous segments so that few entries will be needed in the descriptor tables and
descriptor caches. If physical memory is scarce, however, use of several large contiguous
blocks could result in long waits to move the blocks in and out, thus wasting the physical
memory where another large block cannot fit.
If only part of a segment need be in memory at a time, paged segments make more
efficient use of memory.

4-41

OPERATING SYSTEM CONSIDERATIONS
Object Traps

4.7.4 Object Traps
Through object traps, the operating system can invoke a process or procedure whenever
virtual addresses in a given segment are generated. The MMU can then save the virtual
address that caused the trap. This facility can be used to make 110 devices or external
processors appear as normal segments from the user-software point of view.

4.7.5 Indirect Segment Descriptors
Indirect segment descriptors provide a mechanism to create shared segments that may be
easily swapped out. The only segment descriptor that has to be modified by the operating
system when the shared segment is swapped or moved is the last one (i.e., the descriptor
that directly references the segment data).
Indirect segment descriptors are useful for shared segments where different processes
running at the same execution level are given different access permissions to the segment.
The access permissions in the last descriptor are superseded by the access permissions in
the first descriptor used in the reference.
Indirect segment descriptors can also be used to provide chains of descriptors so that the
path to the last segment descriptor can be passed on from one process to another. This is
similar to the passing of pointers in a programming language, except that here each process
that owns a descriptor that others are linked to can rewrite that descriptor, thus breaking
or redirecting the chain.

4.7.6 Using the Cacheable Bit
Cached segment and page descriptors each contain one cacheable bit (represented by $ for
the MMU). Whenever a descriptor is used for translation, the MMU reflects the value of
the $ bit in the cached descriptor through the cacheable (CABLE) output.
The $ bit in the segment descriptor is copied into the cached page descriptor during missprocessing so that (from the operating system designer's point of view) the $ bit values are
associated with segments, not individual pages.
The MMU does not manipulate the $ bits and the CABLE output signal in any other way,
so this facility can be used in any way desired by the system designer. As an example, one
possible use (from which the name cacheable is derived) is to provide an interface to a
cache memory other than the MMU's own descriptor caches. In this scenario, the
cacheable bit is used to indicate the contents of the associated segment that are not
cacheable.

4.7.7 Using the Page-Write Fault
The fault on write (W) bit in the MMU's page descriptors is checked during address
translation after all other checks have been done. If the W bit is set and the access type is
a write, a page-write fault occurs. This feature can lead to increased efficiency in the
implementation of a UNIX System fork. The W bit could be set when the fork is invoked,

4-42

OPERATING SYSTEM CONSIDERATIONS
Notation

and then both the parent and child processes could continue to use those pages without
having the MMU and operating system physically copy the shared pages until one of those
pages is written. A write operation would cause a page-write fault, and the pages would be
copied and the write bits reset. In this way the system copies pages only as necessary.

4.7.8 Access Protection
Access bits contained within segment descriptors specify the access permission (no access,
execute-only, read/execute, and read/write) for each execution level (kernel, executive,
supervisor, and user). These bits provide protection so that segments are accessed on the
appropriate level. If an access permission is disallowed, an access exception occurs.

4.7.9 Using the Software Bits
Three software bits are contained in each segment and page descriptor. The MMU does
not alter the value of these bits at any time. This allows the operating system designer to
use these bits in any manner. For example, a software bit can be used to avoid allocating
any stack space until a process actually needs it. This is done by assigning the software bit
to signify that a page does not exist. Normally, a process start-up would create a
(sometimes large) stack of zeros. The software bit could be used to avoid creating the
stack until the user program references that page. Only then would the page-not-present
fault cause the operating system to allocate the stack space. If the user program never
references that page, the software bit saves memory for other processes.

4.8 OPERATING SYSTEM INSTRUCTIONS
The remainder of this chapter describes the operating system instructions Oisted in Table
4-1) and the microsequences. Each description includes the assembler syntax, operation
performed, effect of address modes on condition flags, exceptions generated, and an
example.
Some operating system instructions and all microsequences call at least one XSWITCH
function to do parts of the context switch. These functions, XSWITCH_ONEO,
XSWITCH_TWOO, and XSWITCH_THREEO, are included among the microsequences.

4.8.1 Notation
Operations are described in C language where possible. In particular, the following
notation is used where a C language operator or symbol did not exist:
*x

Word of register x contains the address of
(a pointer to) the operand.

*x++

Use word or register x as a· pointer to the operand;
then increment x by I, 2, or 4 for a byte, halfword,
or word operation, respectively.

4-43

OPERATING SYSTEM CONSIDERATIONS
Privileged Instructions

*--x

Decrement word or register x by I, 2, or 4 for a
byte, halfword, or word operation, respectively; then
use x as a pointer to the operand.

interrupt_ID

An 8-bit value, generated on the interrupt
acknowledge access cycle, identifies the interrupt
vector to the process.

dst

Replace with destination operand.

src

Replace with source operand.

{operation}

Text between braces describes an operation in
general terms.

R

= 

Replace field (or bits) a of word R with the value x.

Table 4-3 lists the symbols used to define the bits fields being altered in the PSW. See
Tables 4-5 through 4-8 for the ISC values.
The following symbols are used to identify processor registers:
AP

Argument pointer, riO (assembler syntax %ap)

FP

Frame pointer, r9 (assembler syntax %fp)

ISP

Interrupt stack pointer, r13 (assembler syntax %isp)

PC

Program counter, r15 (assembler syntax %pc)

PCBP

Program control block pointer, r14 (assembler syntax
%pcbp)

PSW

Processor status word, rll (assembler syntax %psw)

Rn

Register n, rn,n

SP

Stack pointer, r12 (assembler syntax %sp)

= 0 to 8 (assembler syntax %rn)

4.8.2 Privileged Instructions
These instructions are executed only when the process is in the kernel execution mode.
Attempting to invoke them at a lower level causes a normal exception (privileged opcode).

4-44

OPERATING SYSTEM CONSIDERATIONS
Privileged Instructions

Instruction

Mnemonic

Call process
Disable virtual pin and jump
Enable virtual pin and jump
Interrupt acknowledge
Fteturn-to-process
Wait

CALLPS
DISVJMP
ENBVJMP
INTACK
FtETPS
WAIT

The DISV JMP and ENBV JMP instructions disable or enable the processor's virtual
address pin and then jump to an address. ENBVJMP enables an MMU, signalling that
the processor is now supplying virtual addresses for translation. DISV JMP disables the
MMU and only physical addresses are supplied. With an ENBV JMP instruction, a new
(virtual) address is loaded into the PC; hence the jump. For DISV JMP, a physical address
is loaded into the PC. The use of CALLPS and FtETPS was previously discussed in 4.4.2
Call Process Instruction and 4.4.3 Return-to-Process Instruction, respectively. WAIT
provides a processor-level execution halt that remains in effect until an interrupt occurs.
The following descriptions provide more detail about the instructions.

4-45

CALLPS

CALLPS

Call Process
Assembler
Syntax

CALLPS

Opcode

Ox30AC

Description

This instruction performs a process switch, saving the current process,
pushing its PCBP onto the interrupt stack, and entering a new process.
It:
• Saves the context (register contents) of the current process in the
current PCB (if R bit of new process is set).
• Pushes the current PCBP value onto the interrupt stack.
• Puts the new PCBP value (from register rO) into the PCBP
register.
• Sets the PSW, PC, and SP registers from the new PCB.
• Performs block moves (if any) for the new process (if R bit of
PSW is set).
• Exits, going to the new process.

Operands

rO is an implicit source operand (it should contain the PCBP of the new
process).

Operation

if Okernel-leveO
normal-exception (privileged-opcode)
1* put new PCBP into tempa *1
tempa = rO
1* push old PCBP onto interrupt stack *1
(force kernel level on memory accesses}
*ISP++ = PCBP
if (memory-exception)
reset-exception (interrupt-stack)
1* Any memory exception in the first XSWITCH subroutine will cause
a process exception (old PCB). The address of the next instruction is
always PC + 2 *1
PC = address of next instruction
1* set old PSW ISC/TM/ET to 010/1 respectively *1
PSW = 0
PSW = 0
PSW = 1

4-46

CALLPS

CALLPS
1* save current registers in current PCB *1
XSWITCH ONEO
1* XSWITCH_ONEO performs the following operations *1
* (PCBP + 4) = PC
PSW = *tempa
*PCBP = PSW
* (PCBP + 8) = SP
if(PSW  unchanged here *1
PSW = 0
PC = *(PCBP + 4)
SP = * (PCBP + 8)
if(PSW  = 0
PCBP = PCBP + 12
}
if(PSW  == 0)
{flush instruction cache}

/* set new PSW ISC/TM/ET to 7/013 respectively *1
PSW = 7
PSW  = 0 1* avoid CALLPS trace trap *1
PSW = 3

4-47

CALLPS

CALLPS
/* do block moves if PSW  is set (1) */
XSWITCH THREEO
/* XSWITCH_THREEO performs the following operations */
if(PSW = *tempa
/* Any memory exception in the following microsequence will cause a
process exception (new PCB).

4-52

RETPS

RETPS
Put new PCBP in PCBP register and get new PC, PSW, and SP. *1
XSWITCH_TWOO
1* XSWITCH_TWOO performs the following operation *1
PCBP = tempa
PSW = *PCBP 1* PSW  unchanged here *1
PSW = 0
PC = *(PCBP + 4)
SP = * (PCBP + 8)
if(PSW = 0
PCBP = PCBP + 12
)
if(PSW == 0)
{flush instruction cache}
1* set new PSW ISC/TM/ET to 7/0/3 respectively */
PSW = 7
PSW  = 0 1* prevent RETPS trace trap *1
PSW = 3
1* do block moves, if R bit set *1
XSWITCH_THREEO
1* XSWITCHJHREEO performs the following operation *1
if(PSW= *(PCBP + 12»
stack-exception (stack-bound)
if(SP >= *(PCBP + 16»
stack-exception (stack-bound)
{unforce kernel level on memory accesses}

1* When writing to the stack in the following two operations, a memory
exception causes a stack exception (stack).
The address of the next instruction is always PC+2.
Save old PC and PSW on execution stack. *1
*SP = address of next instruction
1* set PSW ISC/TM/ET to 1/0/2, respectively *1
PSW = 1
PSW = 0
PSW = 2
*(SP + 4) = PSW
1* mask index values and put in registers *1
tempa = rO & Ox7C 1* index 1 *1
tempb = rl & Ox7FF8 1* index2 *1

1* A memory exception from here to the end of the microsequence
causes a normal exception (gate vector).
Get new PC and PSW values from table. *1
{force kernel level on memory accesses}
1* get pointer to second-level table *1
tempa = *tempa
1* add offset within second-level table */
tempa = tempa + tempb
1* get new PSW from second-level table *1
tempb = *tempa
1* set PM in new PSW to CM in old PSW *1
tempb = PSW
1* new PSW same IPUR values as old PSW */
tempb = PSW
tempb = PSW
1* set new PSW ISC/TM/ET to 711/3, respectively *1
tempb = 7
tempb = 1
tempb = 3

4-58

GATE

GATE
/* put new PC/PSW values into PC/PSW registers
get new PC from second-level table */
PC = *(tempa + 4)
PSW = tempb
/* finish push of old PC and PSW */
SP = SP + 8
{un force kernel level on memory accesses}
{end of operation}

Address
Modes

None

Condition
Flags

Set by new PSW

Exceptions

normal exception (gate vector)
stack exception (stack bound and stack)
process exception (gate PCB)
reset exception (gate vector)

Example

GATE

Notes

Opcode occupies 16 bits.
The values of rO and rl should be byte-valued offsets. The value of
register rO must be a multiple of 4; and the value of rl must be a
multiple of 8. These two registers are source operands only; GATE
does not alter their contents.

4-59

MOVTRW

MOVTRW
Move Translated Word
Assembler
Syntax

MOVTRW src,dst

Opcode

OxOC

Description

This instruction is intended for use with a memory mangement unit
(MMU). An access using the address of the source operand and an
MT access status is performed, and it is expected that the MMU will
translate the address and return the corresponding physical address.

Operands

src - contains virtual address to be translated
dst - contains the physical address after translation

Operation

{under MT status}
dst = &src

Address
Modes

src - all modes except immediate, literal, or register
dst - all modes except immediate or literal

Condition
Flags

N = Bit 31 of word returned
Z = 1, if word returned == 0

v=o

C =0
Exceptions

normal exception (invalid descriptor and external memory)

Example

MOVTRW X,%rO

Notes

Opcode occupies 8 bits.
When MOVTRW is executed in virtual mode with the WE 32101
Memory Management Unit present, the address is translated to the
corresponding physical address. If there is no exception, the MMU
returns the translated physical address, which is then stored at the
destination. If there is an exception, the MMU notifies the CPU in the
normal fashion.

4-60

MOVTRW

MOVTRW
When MOVTRW is executed in physical mode with the WE 32101
Memory Management Unit present, the MMU will behave as if a read
operation in physical mode is taking place.
In systems without an MMU, some other device must respond to the
MT access.
The source operand is an address of operand. The destination operand
is of the type word. If &src is not a word address, a normal exception
(external memory) will occur.
During an MOVTRW instruction, the status pins identify the memory
access as being MT.

4-61

RETG

RETG
Return from Gate
Assembler
Syntax

RETG

Opcode

Ox3045

Description

This instruction can be used to return from a GATE, normal exception,
or quick interrupt. The PC and PSW values to return to are popped
from the execution stack, the current and new execution levels are
compared to prevent a return to a higher execution level, and then the
new values are put into the PC and PSW registers.

Operands

None

Operation

1* get old PC/PSW values from execution stack *1
tempa = *(SP - 4)
tempb = * (SP - 8)
if(memory-exception)
stack-exception (stack)
1* compare execution levels to prevent return to a higher execution
level. *1
if(tempa < PSW = PSW
tempa = PSW
tempa = PSW
tempa = PSW
tempa = PSW
1* set new PSW ISC/TM/ET to 7/0/3, respectively *1
tempa = 7
tempa = 0 1* avoids RETG trace trap *1
tempa = 3
1* put new PC/PSW values into PC/PSW registers *1
PSW =tempa
PC = tempb
1* finish pop of old PC and PSW *1
SP = SP-8

{end of operation}

4-62

RETG

RETG
Address
Modes

None

Condition
Flags

Set by new PSW

Exceptions

normal exception (illegal level change)
stack exception (stack)

Example

RETG

Notes

Opcode occupies 16 bits

4-63

OPERATING SYSTEM CONSIDERATIONS
Microsequences

4.8.4 Microsequences

The microsequences represent built-in microprocessor functions. These are executed
automatically when the processor accepts an interrupt, generates an exception, or
acknowledges a reset request. The XSWITCH functions are called by some operating
system instructions and the microsequences.

4-64

ON-NORMAL EXCEPTION

ON-NORMAL EXCEPTION

On-Normal Exception
Description

A normal exception is caused by some action of the current process,
such as execution of an illegal opcode, and it causes the CPU to
perform the following GATE-like actions. This sequence is identical to
that of GATE except that zero (instead of rO) is used as the offset into
the first-level table (index 1), and the ISC value (instead of rl) is used
as the offset into the second-level table (index2).
A RETG instruction can be used to return from a normal exception.

Operation

1* When reading from the PCB in the following two operations, a
memory exception causes a process exception (gate PCB).
Check SP against stack bounds in PCB. *1
(force kernel level on memory accesses}
if(SP < *(PCBP + 12»
stack-exception (stack -bound)
if(SP >= *(PCBP + 16»
stack-exception (stack-bound)
(un force kernel level on memory accesses}

1* When writing to the stack in the following two operations, a memory
exception causes a stack exception (stack).
Save old PC and PSW on execution stack. *1
*SP = PC
1* set PSW TM/ET to 013, respectively *1
PSW = 0
PSW  = 3 1* normal exception *1
*(SP + 4) = PSW
1* set temp registers to GATE table index values *1
temp a = 0
tempb = PSW « 3

1* A memory exception from here to the end of the microsequence
causes a reset exception (gate vector).

4-65

ON-NORMAL EXCEPTION

ON-NORMAL EXCEPTION

Get new PC and PSW values from table. *1
{force kernel level on memory accesses}
1* get pointer into second-level table *1
tempa = *tenwa
1* add offset within second-level table *1
tempa = tempa + tempb
1* get new PSW from second-level table *1
tempb = *tempa
1* set PM in new PSW *1
tempb = PSW
1* set new PSW ISC/TM/ET to 7/1/3, respectively *1
tempb = 7
tempb = I
tempb = 3
1* put new PC/PSW values into PC/PSW registers *1
PC = * (tempa + 4) 1* get new PC *1
PSW = tempb
1* finish push of old PC and PSW *1
SP = SP + 8

{unforce kernel level on memory accesses}
{end of operation}
Condition
Flags

Set by new PSW

Exceptions

stack exception (stack-bound and stack)
process exception (gate PCB)
reset exception (ga te vector)

Notes

The value of the ISC field of the PSW is the identity of the normal
exception. See Table 4-5 for a list of normal exceptions. The ISC field
of the saved PSW contains this code.
Some exceptions set the condition flags as if the instruction that caused
the exception was successfully completed.

4-66

ON-STACK EXCEPTION

ON-STACK EXCEPTION

On-Stack Exception
Description

A stack exception is caused by discovery of a stack-bound violation
during a GATE or normal exception. Such an event causes the CPU to
perform the following process switching action, similar to a CALLPS
instruction except that the new PCBP is obtained from a fixed address
instead of from rOo
A RETPS instruction can be used to return from the stack exception
handler process.

Operation

/* Get new PCBP value from fixed address */
(force kernel level on memory accesses}
tempa = *136 /* 88 hex */
if (memory-exception)
reset -exception (system -data)
/* push old PCBP onto interrupt stack :/
*ISP++ = PCBP
if (memory-exception)
reset-exception (interrupt-stack)
/* Any memory exception in the first XSWITCH microsequence will
cause a process exception (old PCB). '" /
PSW  = 2 /* stack exception */
PSW < ISC> = code for cause of exception
/* save current registers in current PCB '" /
XSWITCH_ONEO
/* XSWITCH_ONE performs the following operation */
*(PCBP + 4) = PC
PSW = *tempa
*PCBP = PSW
* (PCBP + 8) = SP
if(PSW unchanged here *1
PSW = 0
PC = *(PCBP + 4)
SP = *(PCBP + 8)
if(PSW = 0
PCBP = PCBP + 12
}
if(PSW == 0)
{flush instruction cache}

1* set new PSW ISC/TM/ET to 7/0/3, respectively *1
PSW = 7
PSW  = 0 1* prevent trace trap *1
PSW = 3
{unforce kernel level on memory accesses}
{end of operation}
Condition
Flags

Set by the new PSW

Exceptions

process exception (old PCB and new PCB)
reset exception (interrupt stack and system data)

Notes

The ISC field of the saved PSW contains the code that caused the stack
exception.

4-68

ON-PROCESS EXCEPTION

ON-PROCESS EXCEPTION

On-Process Exception
Description

A process exception is caused by a memory exception while accessing a
PCB. Such an event causes the CPU to perform the following process
switching action, similar to a CALLPS instruction except that there is
no attempt to save the context of the current process (except for its
PCBP value), and the new PCBP value is obtained from a fixed address
instead of from rOo
There is no automatic way to return from a process exception because
the exception is caused when there is a fatal error in the old process.
The operating system is expected to choose some other process to invoke
or return to.

Operation

/* Get new PCBP from fixed address. */
(force kernel level on memory accesses)
temp a = *132 /* 84 hex */
if (memory-exception)
reset -exception (system -da ta)
/* push old PCBP onto interrupt stack */
*ISP++ = PCBP
if (memory-exception)
reset -exception (interru pt -stack)
/* Any memory exception in the XSWITCH microsequence will cause
a reset exception (new PCB).
Put new PCBP value in PCBP register and get new PC, PSW, and SP.
*/
XSWITCH _TWO 0
/* XSWITCH_TWO performs the following operation */
PCBP = tempa
PSW = *PCBP /* PSW unchanged here */
PSW = 0
PC = *(PCBP + 4)
SP = * (PCBP + 8)
if(PSW = 0
PCBP = PCBP + 12
)
if(PSW  == 0)
(flush instruction cache)

4-69

ON-PROCESS EXCEPTION

ON-PROCESS EXCEPTION

/* set new PSW TMiET to 0/3, respectively */
PSW = 0 /* prevent trace trap */
PSW = 3
(unforce kernel level on memory accesses)
(end of operation)
Condition

Set by new PSW

Flags
Exceptions

reset exception (system data, interrupt stack, and new PCB)

Notes

The ISC field of the PSW presented to the exception handling process
will contain the code corresponding to the condition that caused the
process exception.

4-70

ON-RESET EXCEPTION

ON-RESET EXCEPTION

On-Reset Exception
Description

A reset exception is caused by an external reset request or by an
exception while accessing the interrupt stack, the GATE tables, or the
interrupt tables. Such an event causes the CPU to go to physical
addressing mode, obtain a new PCBP value from a fixed address, and
set the PSW, PC, and SP registers from values in the new PCB. No
information from the current (old) context is saved because the CPU
may be powering up for the first time or else the old software context
was so damaged that it caused a reset exception.

Operation

{flush instruction cache]
if{external-reset}
PSW = 0
{force kernel level on memory accesses]

1* force physical mode *1
{Set VAD pin to one}

1* get new PCBP from fixed address *1
tempa = *128 1* 80 hex *1
if(memory-exception}
reset-exception (system-data)

1* Any memory exception in the XSWITCH microsequence will cause
a reset exception (new PCB).
Put new PCBP value in PCBP register and get new PC, PSW, and SP
values. *1
XSWITCH_TWOO
1* XSWITCH_TWO performs the following operations *1
PCBP = tempa
PSW = *PCBP 1* PSW < R/ISC/TM/ET > unchanged here *1
PSW =0
PC = * (PCBP + 4)
SP = * (PCBP + 8)
if(PSW} {
PSW = 0
PCBP = PCBP + 12
}

if{PSW  == O}
{flush instruction cache]

4-71

ON-RESET EXCEPTION

ON-RESET EXCEPTION

1* set new PSW TM/ET to 013, respectively *1
PSW  = 0 1* prevent trace trap *1
PSW = 3
(unforce kernel level on memory accesses}
(end of operation}

Condition
Flags

Set by new PSW

Exceptions

reset exception (system data and new PCB)

Notes

The ISC field of the PSW presented to the exception handling process
will contain the code corresponding to the condition that caused the
reset exception.

4-72

ON-INTERRUPT

ON-INTERRUPT

On-Interrupt
Description

An interrupt is triggered by a request from external hardware and
causes the CPU to perform a process switch or a GATE-like action
(depending on the value of PSW  field to act.
If an interrupt request is granted and auto-vectoring is requested (via
the AVEC pin), an auto-vector interrupt acknowledge cycle is
performed and no Interrupt-ID is fetched. The complement of the
value of the interrupt option pin concatenated with the priority level at
which the interrupt was requested is used as the Interrupt-ID. That is,
bits 0-3 of the ID correspond to the requested level, bit 4 corresponds
to the interrupt option pin, and bits 5 - 7 are zeros.
If a nonmaskable interrupt request is received (via the NMINT pin), an
auto-vector interrupt acknowledge cycle is performed (as if an
autovector interrupt at level 0 was being acknowledged) and no
Interrupt-ID is fetched. The value 0 is used as the ID.

Operation

{Get interrupt-ID value via interrupt acknowledge bus cycle}
tempa = interrupt-ID
if(memory-exception)
stack-exception (interrupt-ID-fetch)

1* test for full or quick interrupt *1
if(PSW ==l)
goto QINT 1* quick interrupt *1

1* it is a full interrupt *1

4-73

ON-INTERRUPT

ON-INTERRUPT

/* get new PCBP from full interrupt table */
{force kernel level on memory accesses}
temp a = *(140 + tempa * 4) /* 8C+tempa*4 hex */
if (memory-exception)
reset-exception (system-data)
/* push old PCBP onto interrupt stack */
*ISP++ = PCBP
if (memory-exception)
reset-exception (interrupt-stack)
/* Any memory exception in the first XSWITCH micro sequence will
cause a process exception (old PCB).
Set old PSW ISC/TM/ET to 0/0/1, respectively. */
PSW = 0
PSW = 0
PSW = 1
/* save current registers in current PCB */
XSWITCH_ONEO
/* XSWITCH_ONE performs the following operations */
* (PCBP + 4) = PC
PSW = *tempa
*PCBP = PSW
*(PCBP + 8) = SP
if(PSW unchanged here *1
PSW = 0
PC = *(PCBP + 4)
SP = *(PCBP + 8)
if(PSW = 0
PCBP = PCBP + 12
}
if(PSW  == 0)
{flush instruction cache}
1* set new PSW ISC/TM/ET to 7/0/3, respectively *1
PSW = 7
PSW  = 0 1* prevent trace trap *1
PSW = 3

1* do block moves, if R-bit set (1) *1
XSWITCH_THREEO

1* XSWITCH_THREE performs the following operations *1
if(PSW = 1
PSW =0
PSW = 2
1* push PSW *1
*(SP + 4) = PSW
1* A memory exception from here until the end of the microsequence
causes a normal exception (gate vector).
Get new PC and PSW values from table. *1
{force kernel level on memory accesses}
tempb = *tempa
1* adjust previous execution level in new PSW *1
tempb = PSW
1* set new PSW IPL to 15 *1
tempb = 15
1* new PSW ISC/TM/ET values same as old values *1
tempb = PSW
tempb = PSW 
tempb = PSW
1* put new PC/PSW values into PC/PSW registers *1
PSW = tempb
PC = * (tempa + 4)
1* finish push of old PC and PSW *1
SP = SP + 8
{unforce kernel level on memory accesses}
{end of operation}
Condition
Flags

Set by new PSW

Exceptions

normal exception (gate vector)
stack exception (stack and interrupt-ID fetch)
process exception (old PCB and new PCB)
reset exception (system data and interrupt stack)

Notes

The interrupt-ID fetch is 8 bits, and is zero-extended to 32 bits in
tempa.

4-76

XSWITCH

XSWITCH

XSWITCH Microsequences
Description

These micro sequences implement context-switching. They are used, in
various combinations, by the instructions CALLPS and RETPS and by
the implicit micro sequences On-Interrupt, On-Process, On-Stack, and
On-Reset.
XSWITCH_ONE performs a context save, saving the current registers
in the current PCB. XSWITCH_TWO performs a context switch,
putting a new value in the PCBP register and reading the new PSW,
SP, and PC values from the new PCB. XSWITCH_THREE performs
block moves specified in the PCB.
The action taken when a memory exception is encountered in the
XSWITCH microsequences is determined by the calling sequence.

Operation

/* Save current registers in current PCB. One argument: tempa is
expected to contain new PCBP value. */

XSWITCH ONE:

/* save current PC in PCB */
* (PCBP + 4) = PC
/* copy R-bit from new PSW to current PSW */ .
PSW = *tempa

/* save current PSW and SP in PCB */
*PCBP = PSW
*(PCBP + 8) = SP
/* if R-bit==l, save
if(PSW unchanged here *1
PSW = 0
PC = *(PCBP + 4)
SP = *(PCBP + 8)
1* if I-bit==I, increment PCBP past initial context area *1
if(PSW = 0
1* increment PCBP past initial context area *1
PCBP = PCBP + 12
1* if cache flushing not disabled, flush cache *1
if(PSW == 0)
{flush instruction cache}
return

4-78

XSWITCH

XSWITCH
/* do block moves, if PSW ==1 */
XSWITCH_THREE:
if(PSW , the directory
of the file argument is not searched. See Note.
Invoke an object code optimizer.
Same as the -E option except output is directed to
corresponding files suffixed .i.
Compile the named C language programs, and
leave the assembly-language output on corresponding files suffixed .s.
Undefine the named identifier to the preprocessor.
See Note.
Print versions of m32cc and tools it invokes.
Allow user to set limit on the percent growth per
file from in-line expansion. Values for limit are: u,
allows unlimited growth; integer;::: 0, allows
indicated percent growth; s, suppresses in-line
procedure expansion.
Pass along the argument(s) argi to pass c, where c
is one of [p02aIl, indicating preprocessor, compiler,
or link editor, respectively. See Note.

-p

Note:

Argument is appended to option with no embedded blanks.

5-5

SOFTWARE GENERATION PROGRAMS
Register Usage

If an asm instruction is encountered under the -0 option, the optimizer suppresses
optimization of any function containing an asm.
The -g option produces information for a symbolic debugger. The SGP does not currently
support a symbolic debugger, but one may be available as part of an application.
Register Usage
With the -0 option, the compiler and optimizer provide automatic global register
allocation on a procedural basis. Automatic allocation tries to move quantities to the
scratch registers that are not saved/restored during procedure call/return. Also, it
attempts to move quantities that cannot be placed in scratch registers into saved registers,
if there is a net payoff. The movement into registers is impeded by constraints that restrict
the registers' quantities. First, quantities that can be addressed in more that one way
cannot be safely placed in registers. Second, scratch registers are changed by calls to
procedures or move block instructions. Third, the number of registers is finite. And
fourth, there is an overhead for using saved registers.
For most uses, the details of register usage or assignment are not needed by programmers.
Registers can be accessed through an assembler escape, although this practice is not
recommended. Registers have the following usage in the compiler:
III

III

rO-r2
r3-r8

Scratch registers
Saved register variables

III
III

ap Argument Pointer
sp Stack Pointer

III

fp

Frame Pointer

Six saved register variables are allowed by m32cc and are assigned to r8-r3 in descending
order. If more than six registers are declared in a C source program, the compiler silently
assigns stack space instead.
Register 0 (rO) holds the return value from a function call. Registers 0 (rO) and 1 (rl)
hold the return value from a call to a double precision floating point function. For a
function returning a structure, r2 passes the address in which the returned structure value
should be stored. Function calls are assumed to require all scratch registers.
5.1.2 C Language
The C language used by the WE 32100 Microprocessor has features to accommodate both
systems and general-purpose programming. The version of C language used is the one
described in The C Programming Language by B. W. Kernighan and D. M. Ritchie
(Prentice-Hall, 1978), except that it includes recent enhancements to C language. This
section describes the extensions to C language not covered in Kernighan and Ritchie's
book.
With the WE 32100 Microprocessor, C language data types map in the natural way for a
32-bit processor. That is, char maps to the processor type byte (8 bits), int and long map
to word (32 bits), and short to halfword (16 bits). The compiler also accepts floating point
data types. Codes for these data types assemble to opcodes which are illegal on the
WE 32100 Microprocessor. Applications can trap on these opcodes and provide emulation
of floating point operations.

5-6

SOFTW ARE GENERATION PROGRAMS
Enumerations

C language leaves identification of the assembler escape keyword (asm) to the designer.
The asm has been implemented for m32cc with the syntax:
asm ("assembly instruction").
For example,
asm ("movw &0, % rO")
loads register rO with a O. The assembly language instruction within the quotation marks
is transmitted unchanged to the assembler.
The C language enhancements recognized by m32cc are:
• Flexnames
• Enumarations

- Structure Assignments
• Structure-valued arguments

- Functions returning structure values
• Nonunique structure member names

A detailed discussion of each enhancement follows. These details are not required by many
programmers, but are included to completely describe the C language used by the
processor.

Flexnames
Flexnames allow the use of arbitrary length variable names. The restriction of eight
significant characters for C language variable names is removed. To allow names of
arbitrary length, a string table was added to the object file, and the symbol table was
modified to support the string table (see 5.4 OBJECT FILE FORMAT).

Enumerations
Enumerations are unique data types with named constants. These partly replace the use of
#define constants and offer the advantage of scoped constant names and strong type
checking in the use of such names. Enumerations are analogous to the scalar types of the
Pascal language.
To the type-specifiers listed in Section 8.2 of The C Programming Language by Kernighan
and Ritchie, add:
enum -specifier
with the syntax
enum-specifier:
enum {enum-Iist}
enum identifier {enum-Iist}
enum identifier

5-7

SOFTWARE GENERATION PROGRAMS
Enumerations

enum-list:
enumerator
enum-list , enumerator
enumerator:
identifier
identifier

=

constant-expression.

The role of the identifier in the en urn-specifier is entirely analogous to that of the
structure-tag in a struct-specifier; it names a particular enumeration. For example,
enum color { red, green, yellow, blue };
enum color *cp, col;
col = yellow;
cp = & col;
if( *cp

==

green) ...

makes color the enumeration-tag of a type describing various colors and then declares cp as
a pointer to an object of that type and col as an object of that type.
The identifiers in the enum-list are declared as constants and may appear whenever
constants are required. If no enumerators with "=" appear, then the values of the constants
begin at zero and increase by one, as the declaration is read from left to right. An
enumerator with "=" gives the associated identifier the value indicated; subsequent
identifiers continue the progression from the assigned value. For example,
enum interrupt{
halt = 0,
badJnstr = 01001,
memJault,
div_zero = 02001,
overflow,
underflow
} icode;
if( (intHcode & 02000 ) /* arithmetic fault

*/

illustrates specific value specification. In particular, the symbol overflow has the internal
value 02002.
All enumeration constants must be distinct. Unlike structure members, enumeration
constants are drawn from the same set as ordinary identifiers.
Objects of a given enumeration type are regarded as having a type distinct from objects of
all other types. The compiler maps enumerations into the int storage class.

5-8

SOFTWARE GENERATION PROGRAMS
Nonunique Structure Member Names

Structure Assignment
Structure assignment was added to the C language to simplify the transferring of the value
of one structure instance to another, and to allow functions to return aggregate values.
Structure assignment permits more efficient use of the processor and also improves source
program readability.
Structures may be assigned as a unit, passed as arguments to functions, or returned by
functions. All structure operands taking part in these operations must be of the same type.
The following example demonstrates the new structure assignment features:
struct clock {
int hour, minute, second;
};
struct date {
int year, month, day;
struct clock time;
};
struct clock now={l3,2,36};
extern struct date spring 0;
struct date today, tomorrow;
struct date nextday( day) struct date day;
struct date tempday;
return tempday;

mainO
today = springO;
tomorrow = nextday( today);
tomorrow.time = now;

Nonunique Structure Member Names
The current standard C language allows more flexibility in the reuse of structure member
and structure field names than the original. The C language now permits reuse of
structure member or field names. The exception is that a particular name may not be used
for two distinct members within the same structure. This enhancement will, in one case,
preclude the use of a type of reference to structure members that was permitted in older
versions of the C language. This obscure case, where upward compatibility has not been
maintained, is explained in detail. Nonunique member names permit more natural
structure and union member naming conventions; which result in stronger and more
efficient type checking of both structure and union member references.

5-9

SOFTWARE GENERATION PROGRAMS
Nonunique Structure Member Names

Former Member Name Restrictions. Prior to this change, there were only two ways in
which structure member names could be reused.
1.

Names of members of two distinct structures could be identical only if those names
represented the same member type and offset. For example, the name xyz is used in
both of the following two structures:
struct sl {
long abc;
char xyz;
int def;

};
struct s2 {
long rst;
char xyz;
short jkl;
};

With such a construction, the structure member name xyz could be referenced from
any structure variable of type s 1 or s2, or any pointer to these types without
ambiguity.
2.

Member names could be reused within a new name scoping (block) level. In the
following code section, the member name f_one is reused:
struct outer {
int Czero:2,Cone:4,Ctwo:l0;
struct outer *next;
};
functO

struct inner {
int Cone, g_one, h_one;
};

When member names are redeclared at different block levels, the innermost declaration
serves to block the outer declarations of the same name within the inner scope. In a
structure of the type outer, the four-bit field f_one could not be referenced within the
function funct. This restriction would hold even for structures that were explicitly declared
to be of type outer.
New Flexibility for Member Names. The language change for structure member names
allows the reuse or redeclaration of structure member or field names with only a single
restriction:
A particular name may not be used for two distinct members within the same
structure. A name may, however, be reused within nested structures.

5-10

SOFTWARE GENERATION PROGRAMS
Complete Structure and Union Member Reference Qualifications

Due to this change, type-checking is performed more strongly for structures and unions. A
structure (or union) member is referred to as unique if it is declared only once, or if all its
declarations conform to the requirements of Case 1 above. If a uniquely named member is
mentioned in a structure reference where it is not a member of the structure, a warning
diagnostic is issued. This allows old C language programs that violate these new rules to
continue to compile. However, if a member that is not uniquely named is used in a
structure reference while it is not a member of the structure, a fatal diagnostic is issued.
The case in which upward compatibility is not maintained involves structure member name
declarations of Case 2 above.
struct x {
int a,b;
lx_obj;
mainO {
int *ip;
struct{
int b,a;
lLobj;
... ip-+a ...
···Lobj.a .. .
... x_obj.a .. .

In the example above, prior to the language change, each of the references ip-+a, y_obj.a,
and x_obj.a was considered legitimate, and an offset of one word for the integer referenced
by "a" was used. With nonunique structure members, the integer referenced by "a" in
x_obj.a would have an offset of zero bytes from the address of x_obj. The portable C
compiler used by m32cc considers such a reference to be a user error and issues a fatal
diagnostic for ip-+a.
Complete Structure and Union Member Reference Qualifications
Complete qualifications are now required for structure and union member references in the
C language because ambiguities can arise with incomplete qualifications and nonunique
structure member names. Incomplete qualifications are flagged with fatal error messages.
In earlier C compilers, a reference to a structure or union member could be abbreviated in
some cases. When an abbreviation was used, a structure or union reference became a
chain of member references (also called qualifications).
Qualifications were prefixed either by a structure or union proper or by a pointer to a
structure or union. Because each qualification implied the addition of an offset within an
address computation, it had been possible to omit those qualifications that had an offset

5-11

SOFTWARE GENERATION PROGRAMS
Nonunique Tag Names Allowed

of zero. Zero offsets occur in the first member of a structure and in all members of
unions. With the following two declarations:
struct xx {
struct yy {
int y 1; char y2;
} ym;
} *xp;
union u {
struct a {
int a 1,a2,a3;
} merna;
struct b {
char bl,b2,b3;
} memb;
} *up;
the following references were allowed:
xp-+y2
up-+b2

/* same as */
/* same as */

xp-+ym.y2
up-+memb.b2

Of the references in the previous example, only the following structure and union member
references are now legitimate:
xp-+ym.y2
up-+memb.b2

Nonunique Tag Names Allowed
Declared types of structure, union, and enumeration can be named by tag names that
appear after the keywords enum, struct, and union, as shown in the following examples:
typedef enum bool {false, true} bool;
struct list *head;
union cell {unsigned word; char byte[21;};
Previous implementations of the C language required that all union and structure tag
names be distinct from member names. The recent enhancements remove this restriction.
As a result, four name pools now exist:
• #define macro names
., Structure, union, and enumeration tag names
• Structure and union members (which may be nonunique)
• All other names, including typedef, array, structure instance, and variable names; and
enumeration constant names.

5-12

SOFTWARE GENERATION PROGRAMS
Assembler and Assembly Language

Vertical Tab Character Literal
The vertical tab character literal has been added to the C language. The character VT
(octal 013 in ASCII) can now be represented as \v in addition to \013. This character
may also be used within character string literals (e.g.: Upper left\t\t\t\v\vLower right\n).
Vertical tab is now included in the definition of white space and therefore can be used to
delimit tokens in a source file.
In-Line Procedure Expansion
With the -0 option, the optimizer provides performance enhancements by expanding small
procedures in-line to reduce discontinuities and the number of saves and restores executed.
The optimizer expands a call to a procedure only if, after global register allocation, the
procedure has no local variables and no saved registers, and if the call appears in the same
file in which the procedure appears. When a procedure is expanded in-line this fact is
noted in the object file symbol table (see the description of Auxiliary Table Entries in 5.4.7
Symbol Table).
Procedures are expanded to only one level (i.e., calls within expanded procedures are not
expanded). When the optimizer expands a procedure, it leaves the original copy in place,
but strips the call, save, restore, and ret instructions from the copies expanded in-line. A
procedure always appears once as a complete routine, but may appear many times as an
in-line expansion. Arguments to an in-line copy are placed on the stack and referenced
with the frame pointer of the calling routine. If a nested call is expanded, the frame
pointer offsets for the in-line copy's argument references are corrected for the presence of
other arguments on the stack.
The optimizer controls the amount of code growth resulting from the expansion by limiting
the percentage code growth per file. It does this by controlling the number of calls
expanded. The limit on the percent growth per file can be set by the user and a default
value can be set at SGP build time.

5.2 ASSEMBLER AND ASSEMBLY LANGUAGE
This section describes the WE 32100 Microprocessor assembler (m32as) and assembly
language. Most applications of the processor involve programming in a C language
environment only. However, some applications may require assembly language
programming for speed or access to functions not accessible at the C level. Short,
frequently executed routines, such as the ones needed to handle I/O, interrupts, and device
drivers are most likely written in assembly language.
The assembler constructs an object file from an assembly language source file. The object
file is relocatable and may include an extensive symbol table for symbolic debugging. This
relocatable object file is in "common" object file format and can be linked to other such
files using the m32ld link editor.
The assembler translates operation code mnemonics and operands into the target machine
bit pattern representing the particular instructions. The m32as assembler attempts to
optimize its output, thus reducing the number of machine cycles required for a given task.

5-13

SOFTWARE GENERATION PROGRAMS
Assembler

This optimization improves program speed. The assembler resolves local text labels,
identifies global text symbols defined in the input files, and identifies symbols referenced
but not defined.
The assembly language is made up of the WE 32100 Microprocessor instruction set,
assembler directives, and a machine-independent instruction set. The machine-independent
instructions are mapped into one or more WE 32100 Microprocessor instructions. The
processor instruction set contains special-purpose I/O and system instructions local to the
processor and a syntax for the variety of addressing modes that can be used to encode
operand references. The assembler directives, called pseudo-operations (or pseudo-ops)
permit description of high-level symbols and their types and storage classes, thus
facilitating symbolic testing. Source line numbers can also be described. Other assembler
directives can set location counters to allow flexibility in coding multiple sections in a
single file.
5.2.1 Assembler
The assembler is normally called by the m32cc command rather than directly by the user.
It has no flags of its own when called by m32cc, although it can be invoked directly with
the command line
m32as options filename
where options are chosen from Table 5-3.
Table 5-3.

m32as Command Line Options

Option

Argument

Description

-m
-n

None
None
objfile
None

Invoke the m4 macro processor.
Turn off long/short address optimization.
Place the assembled output in objfile.
Print the version of the assembler being
run on standard error.

-0

-V

The input assembly language program is read from filename, and the output is written to
an output object file. Unlike m32cc, only one file at a time may be input to m32as. If the
output file name is not specified by the -0 option, the output name is created from
filename using the following algorithm:
• If filename ends with the two characters .s, the output name is created by replacing

these last two characters with

.0.

• If filename does not end in .s and is no more than twelve characters in length, the output

name is created by appending

.0

to filename.

• If filename does not end with .s and has more than twelve characters, the output name is
created by appending .0 to the first twelve characters of filename. (File names on the
UNIX Operating System can be no longer than fourteen characters).

5-14

SOFTWARE GENERATION PROGRAMS
Diagnostics

Usage of the assembler options entails a few potential pitfalls. If the -n option is not used,
address optimization is invoked. The .align assembler directive is not guaranteed to work
in a .text section when optimization is performed. Therefore, aligned constants should not
be defined in the .text section. See 5.2.2 Assembler Directives for a more detailed
description of .align.
When the assembler is implicitly run by using m32cc, there are no key or reserved words.
However, when the assembler is run explicitly, macro processing may be invoked. In this
case, M4 keywords and predefined macros must not be used as symbols (variables,
functions, labels) in the input file, since the macro processors cannot distinguish assembler
symbols from macros. If macro expansion is not required, this problem cannot occur.

Assembled Files
The output of the assembler is an object file that has the format described in 5.4 Object
File Format. Each assembled file contains three sections: .text, .data, and .bss. Each
section begins at an address that is a multiple of four and consists of a contiguous sequence
of bytes. The .text section is used for the executable statements, the .data section is used
for the initialized variables, and the .bss section is used for the uninitialized variables.
Every statement in the input assembly language that produces code or data generates it
into one of these sections.
The assembler maintains three location counters for each assembled file, one for each of
the program sections. The initial value of each counter is set to zero. When an assignment
is made to the corresponding program section, the assembler increments the appropriate
location counter. On its final pass, the assembler concatenates the three sections for each
file in the order .text, .data, and .bss and sets each location counter to the correct starting
address. That is, the text origin is set to zero; the data origin is set to the location that
follows the .text section; and the .bss origin is set to the location that follows the data
entry. Figure 5-2 shows these starting memory locations.
Because the assembler produces relocatable code, modular program development is possible
and is encouraged.
Diagnostics
Many different errors may occur when using the assembler. Nearly as many error
messages are possible. The error messages are intended to be self-explanatory.
The most common error occurs when the input file cannot be read. The assembly then
terminates with the message "Can't open filename". If assembly errors are detected in the
input file, the following information is written to standard error: the input file name, the
line number where the error occurred in the assembly code, and possibly a descriptive
message for the problem. If the input file is produced by the C compiler, the line number
in the C source program that generated the erroneous code is written on standard error.

5-15

SOFTWARE GENERATION PROGRAMS
Macro Processing Facilities

~

. text ORIGIN

~

.data ORIGIN (A 512K-BYTE BOUNOARY)

~

.bss ORIGIN

.text
SECTION

.data
SECTION

(=

.data ORIGIN + .data SIZE)

. bss
SECTION

UNASSIGNEO

Figure 5-2.

Mapping Program Sections

Macro Processing Facilities
Macro processors enhance programming languages by making them more readable, or by
tailoring them to specific applications. The basic facility provided by any macro processor
is replacement of text by other text. The #define statement in the C language performs a
function for the compiler analogous to the function performed for the assembler by the
macro processor.
When the -m option of m32as is specified, the M4 processor is invoked. The M4 macro
processor provides a collection of about thirty-two built-in (default) macros; in addition,
the user can define new macros using the M4 define function. As part of the programming
environment provided by the SGP, many interfacing macros have been predefined. That is,
the define function of M4 has already been used to establish several macros that interface
assembly language routines with C code.
The M4 processor operates by copying its input to its output. As the input is read, each
alphanumeric token (i.e., string of letters and digits) is checked. If the token matches the
name of a macro, the name of the macro is replaced by the defining text, and the resulting
string is pushed back onto the input and rescanned. In M4, built-ins and user-defined
macros work exactly the same way, except that some of the built-in macros have side
effects on the state of the process. Macros may be called with arguments, in which case
the arguments are collected and substituted into the right places in the defining text before
that text is rescanned.

5-16

SOFTWARE GENERATION PROGRAMS
Interface Macros

Use of the M4 helps facilitate symbolic debugging when assembly code is used by tailoring
the input file to look as though it came from the compiler. When an assembly language
program uses the provided M4 macros, symbol table information can be generated, as well
as the prologue and epilogue pseudo-code sequences that the compiler normally provides.
The assembly language programming example demonstrates the prologue and epilogue
sequences. (See 5.2.4 Programming Example.)
Interface Macros
A set of predefined macros is provided to enable assembly language function linkages to C
code to be specified independently from the details of the calling sequence. The macros
therefore not only make programming easier; they also provide some insulation from any
changes to the calling sequence that may occur. It must be emphasized, however, that
while these macros make assembly language programming easier, they do not change the
fact that, whenever possible, C language code should be used. Assembly code, no matter
how well designed, is more difficult to write and debug than C code. In addition, assembly
language routines do not necessarily perform a given task faster than high-level programs.
When the -m option is used, M4 preprocesses all input assembly language source files.
The macros described below are made available as part of this preprocessing step. The M4
processor operates on both assembly language source files and on intermediate assembly
language files generated by the compiler for C source files (i.e., .c files) that contain asm
assembler escapes.
Note: When using m32as, the -m option can be specified on the command line. When
using m32cc, the -Wa, -m option must be specified to access the macro package.
Function Interface Macros. The M4 macro package uses a functional notation for macros
with arguments. Function interface macros should appear alone on a line with the
arguments enclosed in parentheses and separated by commas. Additional white space
(blanks and tabs) is ignored. Macros without arguments should appear in the assembly
text just as if they were normal assembly language expressions.
C_PROLOGUE(name[,nregs])
This macro generates the standard C function prologue that finishes saving the caller's
environment on the stack and sets up a new stack frame for use by the called routine. The
operand name is the function name in the C source code; e.g., prefix in the example shown
in 5.2.4 Programming Example. The name must be a valid C language identifier.
The optional argument nregs gives the number of C language register variables that are
saved by C_PROLOGUE (default is six registers>' The assembly language function may
use the saved registers for any purpose. Register variable arguments and stack arguments

5-17

SOFTWARE GENERA nON PROGRAMS
Interface

~acros

are not available to C_PROLOGUE. Another predefined macro, _RESULT, names the
register that must be loaded with any value to be returned to the calling function.

C_RETURN(nregs)
This macro generates the standard function return sequence. It restores the caller's
environment and executes a branch to the return address that was saved with the
environment on the stack at the time of the call. The number of registers to be restored is
given by nregs and should be the same as that specified in C_PROLOGUE. The default is
six.

C_CALL({und.argl ....• arg5D
This macro generates a call to the C language function june. The operand june must be a
valid function name for either another normal assembly routine or a C source function that
has become known by link editing. Up to five arguments can be passed with C_CALL.
The arguments can be any valid operands to the assembler pushw instruction. Note that
the function arguments are passed through without change (except for macro expansion).
In the assembler language syntax, a variable name or constant operand is normally treated
as if addressing a word in memory. The ampersand (&) can be used to show that the
address itself is wanted. Thus, to use a specific value as an argument, an ampersand is
used with the value. For example, the value 3 would be designated by &3. An argument
that is to be the value stored at some address is indicated by giving the address with no
ampersand. For instance, to obtain the contents at address x, designate the letter x. If the
address itself is to be used as the value, write the value as an ampersand address; e.g.,
designate address x by &x.

This macro operates the same as C_PROLOGUE, but doe, not allow any registers to be
saved.
A_EPILOGUE (name)
This macro generates the symbolic code indicating the end of a function. Programmers
must still write the actual return instructions before the A_EPILOGUE macro call; e.g.,
RESTORE and RET. Lines 30 through 33 in the example shown in 5.2.4 Programming
Example show the code generated by the A_EPILOGUE macro.
The macros that begin with C were written to connect assembly language segments to C
language programs. However, they can also be used to connect two assembly language
segments. In this use, the macros provide symbol table definitions, beginning and ending
statements, and a save instruction for the new segment.
If only the symbol table definition and the beginning and end statements are needed, the
A_PROLOGUE A_EPILOGUE pair should be used. The pair does not contain a save
command, and its use requires explicit coding of save and return instructions.

5-18

SOFfWARE GENERATION PROGRAMS
Interface

~acros

Scratch Register ~acros. The C compiler uses three scratch registers to store temporary
results of expression computations. When the compiler processes a function call, it
guarantees that no current values in the scratch registers will be needed after the call (by
storing the values in temporary locations on the stack if necessary). Therefore, each
function is free to use the scratch registers in any way and does not have to save or restore
them. The macros _SCR1, _SCR2, and _SCR3 expand to the register numbers of the
scratch registers and may be used freely inside a normal assembly language routine. Note
that _SRCI names the same register as ~ESULT. Register _SCRI has special meaning
during the call and return sequence, but is available for general use inside the called
function.
Stack Frame ~acros. Stack frame macros start with an underscore () and provide access
to the current stack frame environment. The argument macros _ISTARG, _2NDARG,
_3RDARG, _4THARG, and _5THARG reference the first through fifth arguments to the
function (via memory address), respectively. The macros _ISTREG, _2NDREG,
_3RDREG, _4THREG, _5THREG, and _6THREG reference the six general purpose
registers, r8 through r3, respectively. The macro _RESULT references the register
(typically rO) used by the C compiler to contain the value returned from a function.
If these macros are used in a normal assembly language routine (for example, one that
uses C_PROLOGUE and C_RETURN), they refer to the stack frame set up by
C_PROLOGUE. Note that C_PROLOGUE does not allocate any automatic storage.
The C stack frame can also be accessed directly by the stack pointer register (SP, rI2), the
frame pointer register (FP, r9), and the argument pointer register (AP, rIO). The function
interface and stack frame macros track any changes in the calling sequence. If the SP,
FP, or AP registers are used to get closer to the stack frame layout, code will no longer be
insulated from the details of the stack frame, and may have to be rewritten later.
Restrictions. In effect, the argument and register macros independently follow the same
algorithm used by the C compiler to allocate storage. Because there is no way for the
macro processor to know about the real environment of the assembly function or calling
function, the following restrictions must be considered when using these macros:
o

The use of argument and register macros is inherently machine-dependent; the macros
cannot be recognized by processors not based on the assembler.

o

All arguments, up to and including the last argument referenced by the macros, must be
ints or pointers. These macros do not deal with char, short, or struct arguments.
Functions that return structures require a more complicated calling sequence that is not
handled by this macro package .

• For assembly language routines, any copying of arguments into registers must be done
explicitly by the assembly code .
• Macro usage is not checked during the compiling and assembling of programs.
Therefore, an assembly language routine that incorrectly changes the value of FP will
cause run-time errors rather than compile-time errors.

5-19

SOFTWARE GENERATION PROGRAMS
Using Predefined Macros

Using Predefined Macros
A normal assembly language routine is called from a C source program just like any other
function. The routine can have arguments passed to it, and it establishes its own
environment on the stack. The file containing the assembly language source must have a
name ending in .s. The.s tells the compiler (m32cc) to skip compilation and send the
source directly to the assembler.
Examples. In the following example, a function named bump adds one to its argument and
returns that result.
C_PROLOGUE (bump)
movw
_ISTARG,%_RESULT
addw2
&1,%_RESULT
C RETURN
If bump were called by the following C language routine

mainO
(
int i = 3;
int j;
j = bump(j);
then j would have the value 4.
The next example gets two pointers as arguments and swaps the values pointed to:
C_PROLOGUE(swap)
movw ISTARG,% ISTREG
movw O(%_ISTREG),%_SCRI
movw 2NDARG,% 2NDREG
movw 0(% 2NDREG),% SCR2
movw % SCR2,O(% ISTREG)
movw %=SCR1,O(%)NDREG)
C_RETURN

#lst arg is a pointer
#get value pointed to
#2nd arg is also a pointer
#get its value
#store 2nd args value
#store 1st args value

Suppose swap was called by the following program:
mainO
{
int i = 3;
int j = -4;
swap(&i,&j);

5-20

SOFTWARE GENERATION PROGRAMS
M4 Reserved Words

Then i would get the value -4 and j would get the value 3. A C language function to
accomplish the same task is
swapG,j)
int *i, *j;
{
register int temp;
temp = *i;
*i = *j;
*j = temp;

In the final example, assembly function chkster checks to see whether, after stepping the
first character, a text string has a common prefix with the string "abcdef' is defined using
the function prefix. (See 5.2.4 Programming Example.) This is a contrived example that
has no place in real code, but is presented to demonstrate how a C language function is
called with the C_CALL macro.
C_PROLOGUE (chkstr)
addw3 &l,_lSTARG,%_SCRl #skip first character
C_CALL(prefix, & string, %_SCRI)
C RETURN
.data
string:
.byte Ox61 ,Ox62,Ox63,Ox64,Ox65,Ox66,OxO
Note that the address of the format string must be passed to prefix and that the null byte
terminating the string must be explicitly coded. Also note that unlike some
implementations, the m32cc compiler does not prepend an underscore before global names.
Thus prefix is used in assembly code, not yrefix.

M4 Reserved Words
Detailed discussion of the M4 processor can be found in the UNIX System User's Manual.
A list of the M4 reserved words is:
changecom
changequote
decr
define
defn
divert

ifdef
ifelse
include
incr
index
len

shift
sinclude
substr
syscmd
sysval
traceoff

5-21

SOFTWARE GENERATION PROGRAMS
Assembly Language

divnum
dnl
dumpdef
errprint
eval

m4exit
m4wrap
maketemp
popdef
pushdef

traceon
translit
undefine
undivert

5.2.2 Assembly Language

This section describes the WE 32100 Microprocessor assembly language syntax and
semantics. The basic actions of evaluation, assignment, and control of evaluation order are
specified by statements. Statements are either machine instructions, assembler directives,
or macro instructions.
The data types supported by the assembly language are byte, halfword, word, and bit field.
A byte is an 8-bit quantity; a halfword is a 16-bit quantity; a word is a 32-bit quantity; and
a bit field is a sequence of 1 to 32 bits.
The instruction set provides that bytes, halfwords, and words can be interpreted as either
signed or unsigned quantities for arithmetic or logical operations. The processor does not
generate any fault internally in the event of word or halfword data specified at improper
addresses. The memory subsystem must generate a memory fault if such a fault is to be
provided.
Detailed information on the instruction set, if needed, may be found in Chapter 3.
Statements

An assembly language program consists of a sequence of lines of code. Each line consists
of a sequence of characters terminated by the new-line character (\n). Each line may
contain one or more statements. If several statements appear on a line, they must be
separated by semicolons (;). Each statement must be one of the following:
• Assembler Directive - a statement that is a command to the assembler. It consists of a
pseudo-operation code followed by zero or more operands.
• Machine Instruction - a mnemonic representation of an executable machine instruction.
It consists of an operation code followed by zero or more operands.
• Machine Independent Instruction - a statement that maps into one or more executable
machine instructions.
• Empty - a statement that contains only spaces and tabs. It signifies nothing to the
assembler, but is often used to enhance program readability.
Operation codes are separated from their operands by at least one space or tab. Operands
and arguments are separated by commas. Unless otherwise stated, any other use of space
and tab characters is optional. White space characters may be used freely to improve
readability.

5-22

SOFTWARE GENERATION PROGRAMS
Symbols

Each statement may be modified by one or more of the following:
• A label may be placed on any statement. The label consists of a symbol that begins in
the first character position of a statement (j.e., it must begin IMMEDIATELY after a
new-line character or semicolon) and is followed by a colon. Symbols are described in
detail in the following section. An unlabeled statement MUST have a space, tab, or
pound sign (#) in the first character position.
o A comment may be inserted at the end of any statement by preceding the comment with
a pound sign. The assembler will ignore the pound sign and all characters following it
up to the first new-line character. A new statement begins with the first character after
the new-line character.
There are no limits on the number of characters in a statement or on the number of
statements on a line. Multi-line comments are made by inserting a pound sign as the first
nonwhite-space character of each line.
An example showing the four parts of assembly language statements follows. The first
statement shows an assembler directive. The second statement is empty and was inserted
to provide a visual break between directive and machine-instruction sections. The last two
statements are machine independent instructions.
Label

main:

Mnemonic

Operand

.globl

prefix

save
addw2

&.RI
&.FI,%sp

Comment

#begin the function

These statements are taken from the example in 5.2.4 Programming Example.
Symbols

Symbols are tokens recognized by the assembler. They always have a value and type,
either specified explicitly by an assignment statement (see 5.2.2 Assembler Directives) or
determined from the context. Value and type are described in detail in this section. A
symbol name consists of a string of the characters a-z, A-Z, 0-9, underscore (), and
period (.). Names may not begin with a digit. Because embedded blanks are not
permitted in symbols, the underscore is generally used in place of a blank to make an
identifier more readable.
Symbols are primarily used as labels. Four examples of symbols are:
Rtn Nam5

abc

DEF

xyz.QQQ.

The assembler does not put symbols beginning with. (read as 'dot') into the object file
symbol table. Exceptions to this rule are .text, .data, and .bss; these symbols are used for
relocation.

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SOFTWARE GENERATION PROGRAMS
Symbols

The following symbols are reserved for use by the assembler:
1.

. This symbol (read as dot) is used as the location counter while assembling a
program. Whenever actual code is generated by the assembler, the value of this
symbol is increased by the size of the generated code. Hence, this symbol effectively
represents the address of the code being generated. Depending on the section for
which code is being generated, dot may be of type TEXT, DATA, or BSS. Null data
can be generated by pseudo-op assignment to this symbol.

2.

.text This symbol has type TEXT and is used to label the beginning of the .text
section for the program being assembled.

3.

.data This symbol has type DATA and is used to label the beginning of the .data
section for the program being assembled.

4.

.bss This symbol has type BSS and is used to label the beginning of the .bss section
for the program being assembled.

Values and Types. Values are represented in the assembler by signed 32-bit 2's
complement numbers. Every value is an instance of one of the following types:
TEXT

A TEXT value is one that is defined relative to the beginning of the .text
section. Whenever the .text section is relocated forward (backward) by N
bytes, the number N will be added to (subtracted from) every value of
type TEXT. The most common example of a TEXT value is a label
appearing in the .text section.

DATA

A DATA value is one that is defined relative to the beginning of the .data
section. Whenever the .data section is relocated forward (backward) by N
bytes, the number N will be added to (subtracted from) every value of
type DATA. The most common example of a DATA value is a label
appearing in the .data section.

BSS

A BSS value is one that is defined relative to the beginning of the .bss
section. Whenever the .bss section is relocated forward (backward) by N
bytes, the number N will be added to (subtracted from) every value of
type BSS.

UNDEFINED An UNDEFINED value is one whose type has not yet been determined.
The UNDEFINED value may be a reference to a symbol whose definition
has not been encountered yet (i.e., a forward reference) or a reference to a
symbol that is assumed to be defined in a program other than the one
currently being assembled (i.e., an external reference).
ABSOLUTE

An ABSOLUTE value is one that will not change as a result of relocating
any section of the program being assembled. Constants described in the
following section have absolute type.

In addition, any of the above types may be given the attribute EXTERNAL. For values of
the types ABSOLUTE, TEXT, DATA, and BSS; the attribute EXTERNAL indicates that
a value defined in the program currently being assembled will be made available to other
programs. For values of type UNDEFINED, EXTERNAL means that the value is
referenced in the program currently being assembled, but is defined in some other program.

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SOFTWARE GENERATION PROGRAMS
Location Counter

Assigning Values and Types to Symbols. There are two ways to assign a value and type to
a symbol. The first is to write the symbol as a label. The label will be assigned the
current value and type of the location counter. The second is through the use of the .set
assembler directive. An arbitrary value and type can be assigned with this directive.
Constants
A constant is an object of ABSOLUTE type and fixed value. The size and appropriate
number of digits are controlled by the generation pseudo-ops .byte, .half, and .word. A
constant may be one of the following:
• A decimal constant is represented by a contiguous string of the digits 0-9, beginning with
a nonzero digit. Examples of decimal constants are:
123

75

1943

2

o An octal constant is represented by a contiguous string of the digits 0-7 beginning with a
zero digit. Examples of octal constants are:
077

0123

06

037777777777

o A hexadecimal constant is represented by a contiguous string of the digits 0-9 and the
letters a-f or A-F, prefixed by Ox or OX. Examples of hexadecimal constants are:
Ox3f

OX9aC

Oxabcd

OXFE

Note: Floating point operations and declarations are not supported by the processor, but
are available in some applications. If supported, floating point constants have the same
syntax and interpretation as floating point constants in the C language with the exception
that the constant may be preceded by an optional minus (-) sign indicating a negative
constant. The precision of the constant (single or double) is always determined by its
context.
In order to be recognized as floating point, a constant must contain either a decimal point
or one of the exponential characters (e or E). Floating point constants that cannot be
encoded exactly in the specified form are rounded off.
Examples of floating point data types are:
31.0500

-16.

0.1024e4

500e-3

Floating point data specifications are expected to conform to the IEEE standard for binary
floating-point arithmetic.
Location Counter
The symbol. (read as dot) is the location counter used during the assembly of a program
and is reserved for use by the assembler. The type of this symbol is either TEXT, if code
is currently being generated for the .text section, or DATA, if code is currently being
generated for the .data section. The initial type of the location counter is TEXT and the
initial value is zero.

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SOFTWARE GENERATION PROGRAMS
Registers

The location counter represents the address of the next available byte for the placement of
assembled code or data, and can change in the following ways:
• as a result of the .text, .data, .set, .zero, .align, .byte, .balf, or .word pseudo-ops
• as a result of the generation of code for a machine instruction.
In the first case, the change is explained in the description associated with each pseudo-op.
In the second case, the location counter is incremented by the size of the assembled code
after the statement is completely assembled.
For each section (.text, .data, or .bss) there exists a saved location counter value. Initially
each saved location counter value is zero. When the programmer issues a section change
pseudo-op, the current location counter (i.e., the section being changed from) is saved.
The current location counter is then assigned the value of the location counter for the
destination section.
Registers
Registers 3 through 8, which are referred to by the assembly language syntax %r3, %r4,
%r5, ... , %r8, are the general purpose registers that are always available to the
programmer. Registers 0, 1, and 2 are considered general purpose, but have implicit
definitions because of certain conventions of the C language. For example, rO should
always be used to return the value of a function. If a floating point double value is
returned from a function, it is stored in rO and rl. If a function returns a structure, then
the pointer to that structure should be returned to r2. In general, rO, rl, and r2 are scratch
registers. Data transfer instructions MOVBLW, STRCPY, and STREND also implicitly
use these three registers as do the system instructions MVERNO, INTACK, ENBVJMP,
DlSVJMP, GATE, RETPS and CALLPS.
Registers 9 (frame pointer), 10 (argument pointer), and 12 (stack pointer) are also
implicitly used, in this case by call and return instructions. These registers can be referred
to by the assembly language syntax %fp, %ap, and %sp, respectively.
Registers 0, 1,2, 9, 10, and 12 may be used in any addressing mode, privileged or
non privileged. The use of rO, rl, and r2 for function calls and returns is described in 5.2.2
Function Calling Sequence.
The program counter (rl5) is a special register that does not work in all addressing modes.
The three registers not yet discussed are privileged, and any attempt to write them when
the processor is not at kernel execution level results in a privileged register exception.
These three registers are the interrupt stack pointer nSp), the process control block
pointer (PCBP), and the process status word (PSW).
The PSW (rl1) contains four condition bits - N,Z,V, and C. Because of the pipelining
architecture of the processor, the condition codes in the PSW may not be valid immediately
after the execution of an instruction. This inherent delay is not a problem for any
conditional branch instructions because they wait until the condition codes are valid before
testing them. However, if the PSW is read by any non-machine independent instruction,

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SOFTWARE GENERATION PROGRAMS
Executable Instructions

a NOP instruction should be inserted between the instruction affecting the condition codes
and the instruction trying to read the PSW to allow sufficient time for the condition codes
to settle.
Note:

The assembler supplies the NOP, if needed, for macro ROM instructions.

Executable Instructions
Mnemonics for processor instructions use uppercase letters and machine independent
instruction mnemonics use lowercase letters. When coding in assembly language, this
distinction must be maintained. Therefore, all machine-specific mnemonics must be coded
in uppercase, while mnemonics common to the machine independent instructions must be
coded in lowercase.
Be careful when switching between processor and machine independent instructions.
Although the mnemonics are identical in many cases, the operations are not. For example,
the machine independent instruction cmpw &1,&2 will set the less than flag, while the
processor instruction CMPW &1,&2 would, under the same conditions, set the greater
than flag, because the operand order is reversed.
The processor instruction set is more complete than the machine independent instruction
set, but is machine dependent. Machine independent instructions can be portable.
Because floating point operations are not supported by the processor, use of floating point
instructions results in a run-time exception. However, these instructions become legal in
applications that support floating point operations.
In many cases, the mapping of machine independent instructions to processor instructions is
obvious, particularly when synonymous instructions exist in both instruction sets. However,
the mappings of machine independent instructions to corresponding processor instructions
can be obscure. In particular, there is only a rough correspondence between machine
independent instruction set jumps and processor branch instructions. The machine
independent instruction set also has four push instructions and several unsigned instructions
that have no synonyms in the processor instruction set.
Mappings can be obscure, not only from the lack of equivalent instructions, but also from
the considerable changes that are made as part of optimization. About half of the
mappings change when optimization is performed. Hence, the only way to determine the
mappings is by studying a disassembly.
The MOVEs of the two instruction sets also have a complex mapping. MOVEs can
perform conversion from one data type to another. Sign extension, if necessary, is
determined by the type of the source. Signs are extended if the source is signed byte or
signed halfword. Zero-extension is performed if the source is unsigned byte or unsigned
halfword.

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SOFTWARE GENERATION PROGRAMS
Operands

The basis for the mappings of MOVE instructions is:
movbbh
movbbw
movbhw
movzbh
movzbw
movzhw
movthb
movtwb
movtwh

MOVB {sbyte}src, {shalf}dst
MOVB {sbyte}src, {sword}dst
MOVH src, {sword}dst
MOVB src, {shalf}dst
MOVB src, {sword}dst
MOVH {uhalf}src, {sword}dst
MOVH src, {sbyte}dst
MOVW src, {sbyte}dst
MOVW src, {shalf}dst

If the dst operand is a register, the three truncate instructions are:

movthb
movtwb
movtwh

ANDH3
ANDW3
MOVW

& Oxff,src, {byte} dst
&oxff,src,{byte}dst
src,dst;MOVH dst,dst

The notations used in the above mappings are:
src - source
dst - destination
s - signed

u
- unsigned
byte - 8-bit data

half - 16-bit data
word - 32-bit data

Operands
The operand and address modes in assembly language are determined by the syntax. The
kinds of operands are:
• Basic
• Effective address
• Offset
The basic operand can be used as either a source or destination. The effective address
operand is used as a source. The offset is used as a destination. The basic and effective
address operands are described by operand descriptors. However, offset is not described by
a descriptor. Basic operands read or write a specified location. Effective address operands
contain the source address in the instruction. The offset is a signed 8- or 16-bit
displacement from the program counter. The resulting address serves as the target for a
branch instruction.

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SOFTWARE GENERATION PROGRAMS
Operands

Mode
Absolute
Absolute deferred

Table 5-4. Address Modes
Mode
Register
Syntax
Field
Field
Absolute
7
15
$expr
*$expr
14
15
Displacement (from a Register)
expr(%rn)
12 0-10,12-15

Byte displacement
Byte displacement
deferred
Halfword displacement
Halfword displacement
deferred
Word displacement
Word displacement
deferred
AP short offset
FP short offset
Byte immediate
Halfword immediate
Word immediate
Positive literal
Negative literal
Register
Register deferred
Expanded operand
type

Total
Bytes

Notes

5
5

-

2

-

*expr(%rn)
expr(%rn}

13
10

0-10,12-15
0-10,12-15

2
3

-

*expr(%rn)
expr(%rn)

II

0-10,12-15
0-10,12-15

3
5

-

*expr(%rn)
9 0-10,12-15
so(%ap)
0-14
7
so (%fp)
0-14
6
Immediate
15
&imm8
6
&imm16
5
15
&imm32
4
15
0-3
0-15
&lit
0-15
15
&lit
Register
0-14
%rn
4
(%rn)
5 0-10,12-14
Special Mode

5
1
1

-

2
3
5
1
1

2,3
2,3
2,3
2,3
2,3,5

1
1

1,3
1

{type}opnd

8

14

0-14

2-6

1
1

4

Notes
1. Mode field has special meaning if the register field is 15; see Absolute
or Immediate mode.
2. Mode may not be used for a destination operand.
3. Mode may not be used if the instruction takes effective address of the
operand.
4. type overrides instruction type; opnd is any of the other valid address
modes and becomes the real address mode. For total bytes, add 1 to byte
count for address mode determined by opnd.
5. Negative quantity; overrides expanded operand type and instruction type.

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SOFTWARE GENERATION PROGRAMS
Expressions

Each operand descriptor identifies the location of the operand. An operand descriptor may
be one or more bytes. The format of the first byte of a descriptor is:
mmmmrrrr
where rrrr is the register field (bits 0-3) and represents one of rO-r15. The mode field,
mmmm, is comprised of bits 4-7 and represents the addressing mode. Table 5-4 can be
used to determine the proper syntax and mode based on the value of the mode field.
Unless otherwise specified by the instruction, all operands are addressed by a descriptor.
The value of the PC is the address of the first byte of the instruction and retains that value
for all operand evaluations during the instruction.
Note: Data in the instruction stream may not be ordered the same way that data is
ordered when fetched into the processor. In the instruction stream, the byte order is rightto-left; that is, the first byte of the data stream is always the least significant byte. For
example, the first byte of a 32-bit immediate value represents bits 0-7 of the operand.
The second byte represents bits 8-15; the third byte, bits 16-23; and the fourth byte, bits
24-31.

Expressions
An expression is a sequence of operands separated by operators. An operand is either a
constant, a symbol, or an expression enclosed in parentheses.
Expressions can be used as operands to assembler directives and machine instructions, as
appropriate. All operators are fundamentally binary in nature. The operator "-" may be
used as a unary operator with the interpretation 0-. For example, -x is interpreted as
(O-x).
All operators are assumed to be of EQUAL precedence. If anything other than left-toright evaluation. is desired, parentheses must be used for grouping.
If, in the process of evaluating an expression, an intermediate result will not fit in 32 bits,
the final value of that expression will be undefined.

The following operators are available:

+

Produces the 2's complement sum of its operands. One operand must be type
ABSOLUTE - the other can be any type. The sum has the type of the other operand.
All other combinations of operands are illegal.
Produces the 2's complement result of subtracting the right operand from the left
operand. If the right operand is ABSOLUTE, the difference has the type of the left
operand. Otherwise, both operands must be of the same type (which cannot be
UNDEFINED), and the result has type ABSOLUTE. All other combinations of
operands are illegal.
The result of the subtraction can be erroneous when taking the difference between two
relocatable symbols. For example, the value of labl-lab2, where labl and lab2 are
labels that are both of type TEXT, DATA or BSS, may change due to various

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SOFTWARE GENERAnON PROGRAMS
Assembler Directives

optimizations of the code between labl and lab2 that are made after the assignment of
values and types to labl and lab2. In such cases, the value of labl-lab2 will not
correctly indicate the distance between labl and lab2.

*

Produces the 2's complement product of its operands. It requires both operands to be of
ABSOLUTE type and produces an ABSOLUTE result.

/

Produces the 2's complement quotient of the left operand divided by the right operand.
Uneven divisions result in the integer that is the result of truncating the quotient toward
zero; for example, 5/-2 = -2. The quotient operator requires both operands to be of
ABSOLUTE type and produces an ABSOLUTE result.

Assembler Directives

An assembler directive is a command to the assembler that does not necessarily generate
any code. Directives are distinct from executable instructions, that contain mnemonics for
machine operations. Every assembler directive is coded as a pseudo-operation (pseudo-op)
code followed by zero or more operands. All assembler directives begin with a period (.).
Table 5-5 lists all pseudo-ops alphabetically.
Section Control Pseudo Operations. These pseudo-ops provide a method of changing the
section in which code is generated and the section in which labels are defined. They work
as follows: each of the sections .text, .data, and .bss has its own hidden dot or location
counter that indicates where the next code is to be generated for that section. The actual
symbol "." starts out with a type of TEXT and a value of zero. Whenever a section control
pseudo operation is encountered, the value of dot is stored away into whichever hidden dot
is indicated by its type. The value of some other hidden dot is then retrieved and stored as
the value of the symbol ".", and the type of dot is set depending on which hidden dot is
used.

The following section control pseudo operations are recognized:
.text
.data
.bss symbol,size,align

where:
.text

causes the current location counter to be saved and then assigned the value of the
location counter for the text section. The type of the current location counter is set
to TEXT .

.data

causes the current location counter to be saved and then assigned the value of the
saved value of the location counter for the data section. The type of the current
location counter is set to DATA .

.bss

causes the bss location counter to be advanced to a multiple of align (which must
be an ABSOLUTE expression with a value of 2 or 4), and assigns to symbol the
type BSS and the current value of the bss location counter. The .bss section then
advances its dot by the value of size. size refers to the number of bytes; it must be
greater than or equal to 0 and have type ABSOLUTE. The type and value of the
current location counter remain unchanged.
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SOFTWARE GENERATION PROGRAMS
Assembler Directives

Table 5-5.
Name
.align expr

Alphabetical List of Pseudo-Operations
Operation

Increment the current location counter to a multiple of expr .
expr must evaluate to an ABSOLUTE of 2 or 4.
.bss sym, size, align Define the symbol name sym in the .bss section, and add
size to the value of dot and .bss after aligning it to a
multiple of align. This does NOT change the current
section to .bss. size must be an ABSOLUTE value and
align must be an ABSOLUTE value of 2 or 4 .
.byte valL vall...
Generate initialized bytes containing the 8-bit value val in
the current section.
.data
Change the current section to .data .
.def name
Start of the symbolic description for the symbol name .
.dim exprL exprl... If the name in .def is an array, then the expression gives the
dimensions. Up to five dimensions are accepted. The type
of each expression should be ABSOLUTE.
.endef
Ending bracket for .def.
.file "name"
Pass the UNIX System source file name to the assembler .
Only one .file is allowed per assembly file.
.global name
Treat name as a global symbol, equivalent to storage class
extern in the C language .
.half valL vall...
Generate initialized halfwords containing val in the current
section. Each val must be a 16-bit value.
.il
Indicates that a procedure has been expanded in line .
.line expr
Define the source line number of the definition of block
symbol "name" in .def. expr should yield an ABSOLUTE
value .
.In line[, addrl
Create an entry in the line number table for a section. The
current dot becomes the default for addr. The type of addr
tells which section owns the line number. The operand line
should be an ABSOLUTE value of the source line number.
Within .def give name the storage class of expr. The type of
.scl expr
expr should be ABSOLUTE.
.set name,expr
Set the value of the symbol name to expr; name must be a
symbol.
.size expr
If name of .def is an object such as a structure or an array,
assign it size expr. The type of expr should be
ABSOLUTE.

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SOFTWARE GENERATION PROGRAMS
Assembler Directives

Table 5-5.

Alphabetical List oC Pseudo-Operations (Continued)

Name
.tag sIr

.text
.type expr
.val expr
•word vall, vall ...
.zero size

Operation
If name of .deC is a structure or union, sIr should be the
name of that structure or union tag as defined in the
previous .deC-.endeC pair. The operand sIr must be a symbol.
Change the current section to .text.
Within a .deC, give name the C compiler type representation
expr. The type of expr should be ABSOLUTE.
Within .deC, give name the value expr. The type of expr
should be ABSOLUTE .
Generate initialized words containing val in the current
section. Each val must be a 32-bit value.
Advance the location counter by size and put zeros in the
area skipped. The type of size should be ABSOLUTE.
This pseudo-op is legal only in a .data section.

Pseudo Operations Dealing With Symbols. The pseudo-op .glob! is used to declare that a
symbol is to be accessed by more than one program (j.e., given the EXTERNAL
attribute). The format is:
.glob! symbol
This statement has one of two effects:
o If symbol is defined in the program in which the .glob! statement appears, a symbol
table entry will appear in the object file that will allow other programs to access symbol.
o If symbol is not defined in the program in which the .globl statement appears, then
references to symbol will be treated as references to something defined externally. This
use of .globl is entirely optional since any symbol that is undefined in a program will be
assumed to be external.
It is important to note that .glob! does not define the symbol. This pseudo operation is
similar to the "extern" declaration in the C language. A symbol is defined either when it is
used as a label, when it is used in one, of the data generating operations or when it is given
a value in an assignment statement. A .glob! pseudo-op is used on line 9 of the example in
5.2.4 Programming Example.
Assignment Pseudo Operation. A symbol may be given an arbitrary value and type through
the use of the .set pseudo-op. It has the form:
.set symbol, expression
The expression is evaluated and its value and type are assigned to symbol. Every symbol
that appears in expression must either be defined or have the EXTERNAL attribute.
Lines 30 and 31 of the example in 5.2.4 Programming Example show the use of .set
pseudo-ops.

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SOFTWARE GENERATION PROGRAMS
Assembler Directives

Assignments are performed during the assembler's first pass over the input program. This
has several important consequences:
• The .set pseudo-op does not allow forward referencing; i.e., every symbol that appears in
expression must be defined prior to the assignment statement. Forward references are
allowed in other contexts because all other expressions are not evaluated until later
passes.
• The result of the assignment may be different from the expected result. For example,
consider the assignment
.set abc,labl-lab2
where labJ and lab2 are labels appearing in the .text section. An ABSOLUTE value is
assigned to abc, which is the distance from lab2 to labJ, during the first pass. This
distance may change during subsequent passes if there are offsets between lab2 and labl
that need to be altered. For example, the jmp instruction can assemble into a short form
(2 bytes) or a long form (3 bytes) depending on the value of the offset. The first pass of
the assembler assumes that the 2-byte form can be used. This will be expanded to the 3byte form if a subsequent pass determines that the label is out of the range for a short
jump. This expansion will not be reflected in the value of abc if the jmp occurs between
labl and lab2.
Other assignments may have no problem at all. For example, expressions containing only
ABSOLUTE operands always yield the correct result. Assignments such as
.set xyz.labl
where labJ is a label in the .text section, also behave as desired. When code is modified,
the assembler changes the values of labels to point to the correct locations. If the value of
labl changes, so will the value of xyz, because both are TEXT symbols with the same
value.
Assignment to Dot. Null data may be generated by assignment to the location counter.
The location counter is represented by the dot symbol (.). Assignment to dot may be
performed under the following conditions:
• The result type of the expression to be assigned to dot has the same type as dot.
• The value of the expression to be assigned is not less than the value of dot.
If the assignment increases the value of dot by N, then N bytes of null data are generated.
Assignment to dot is most often used to provide holes or spaces in code. For example, the
. statement

.set .,.+10
generates 10 bytes of null data. The assembler defines null data in the .text section as
NOPs (Ox70); null data in the data section is zero.

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SOFTWARE GENERATION PROGRAMS
Assembler Directives

Alignment Pseudo Operation. The alignment pseudo-op .align causes the next data item or
instruction to be assembled at an address that is a multiple of 2 or 4. It has the form
.align expression
where expression must evaluate to an ABSOLUTE 2 or 4. A .align 2 causes the value of
current location counter to be incremented by one if its current value is not a multiple of 2.
A .align 4 causes the value of the current location counter to be incremented by one, two or
three, if its current value is not a multiple of four. The appropriate increment (one, two,
or three) needed to bring the location counter to a multiple of four is chosen. If this
directive is used in the .text section, any space skipped will be filled with NOP instructions.
If it is used in the .data section, any space skipped will be filled with zeros.
Data Generation Pseudo Operations. Data generation pseudo-ops are used for declaring
variables. The data generation pseudo operations - .byte,.half, and .word generate 8-, 16-,
and 32-bit integer constants, respectively. The forms are
.byte expr, .. .
.half expr, .. .
.word expr, .. .
Each expression will be converted into its perspective data type. The location counter must
be properly aligned with .align before each use of one of these pseudo-ops. Dot is then
incremented by one, two, or four (depending on the pseudo-op) after the generation of each
data item in the list of expressions for that statement. For example, .word .,.,. generates
three words of data and each word contains the address of the first byte of that word.
Therefore, each word contains a different value.
Each expression may be given a bit width by prefacing it with an integer constant followed
by a colon. This format for bit width is
n:expr

where n ranges from 0 to 8 for .byte, 0 to 16 for .half, and 0 to 32 for .word. Nonprefaced
expressions have an assumed bit width of 8, 16, or 32, depending on whether the .byte,
.half, or .word pseudo-op is used. The expression, which must be ABSOLUTE, is
converted into the proper representation and placed in a field of the indicated width.
For example,
mode: .byte 5:x+y, 3:0

initializes an 8-bit variable, mode, by setting the upper five bits of mode to the result of
the expression x + y, and the lower three bits to zero.
Fields are assigned from high order bit positions (i.e., bit 7 of a byte) to low-order bit
positions. Each successive expression is placed into a field that begins with the next lower
bit position. The location counter is adjusted after the generation of each data item; it
always indicates the address of the first byte into which the current data item is to be
placed.

5-35

SOFTWARE GENERATION PROGRAMS
Assembler Directives

A field is not allowed to cross the implied boundary indicated by one of the above pseudoops. If too few fields are encountered to fiII the indicated unit of memory, enough zeros
are supplied to fiII the low order bits.
The data generation pseudo-op .zero allocates an area of memory and fiIls it with zeros. It
has the form
.zero size
where size is the number of bytes to allocate and fill with zeros. The .zero pseudo-op
advances the location counter by size and puts zeros in each byte of memory that is
skipped. It is legal only in the .data section. Variables declared static in a C source
program are assembled through this pseudo-op.
Symbolic Debugging Pseudo Operations. Symbolic debugging pseudo-ops are provided for
making entries in the symbol and line number tables in the object file. The presence of
symbolic debugging pseudo operations in an assembly language program has no effect on
program execution. These statements merely serve to transparently pass information from
the user code to the symbolic debugger.
The basic symbolic debugging pseudo operations are .def and .endef. These are used as a
pair to surround a list of pseudo operations that assign attributes to a symbol. The format
used is:
.def name

(Attribute-assigning pseudo operations}

.endef
The attribute-assigning pseudo operations between .def and .endef assign attributes to the
symbol name. These attribute-assigning pseudo operations are available:
.val expr

Gives the value expr to the symbol name. In general, the type of
expr (TEXT, DATA, etc.) is used to determine the section with
which the symbol name is associated.

.scI expr

Declares a storage class for the symbol name. expr must yield a
value of ABSOLUTE type that corresponds to the portable C
compiler's internal representation of a storage class.

.type expr

Declares a data type for the symbol name. expr must yield a value
of ABSOLUTE type that corresponds to the portable C compiler's
internal representation of a type and derived type.

.tag str

Used when name is a C level structure or a union. str is a structure
or union tag that is defined by some other .def-.endef pair.

.line expr

Used when name is a block symbol. expr yields a value of
ABSOLUTE type that gives the line number of the declaration for
name.

5-36

SOFTWARE GENERATION PROGRAMS
Function Calling Sequence

.size expr

Used when name is a C level structure or an array that does not
have a predetermined size. expr should yield a value of
ABSOLUTE type that gives the size of name, usually in bytes, or in
bits if name is a bit field.

.dim exprl,expr2, ...

Used when name is an array. Each expression yields a value of
ABSOLUTE type that gives the corresponding dimension of the
array. Since the UNIX System implementation of the C language
supports up to five dimensions for an array, there may be up to five
arguments to the .dim pseudo-op.

. il

Used to indicate that a procedure has been expanded in-line .

For symbolic debugging purposes, the order of symbols is very important. The assembler
has no knowledge of this ordering; it just passes the symbols through from the C compiler
so they may be accessed by the symbolic debugger.
As with .glob!, the .def pseudo-op does not define the symbol. A symbol table entry is
created but no definition occurs.
File Name Pseudo Operation. Associated with each assembly file can be at most one .file
pseudo-op. It has the form
.file "name"
where "name" is a double-quoted string of 1 to 14 characters. This pseudo-op is normally
used to pass the name of the C source file from which the assembly program originated.
name then becomes part of the symbol table and can be accessed at run time. Line 1 of
the example in 5.2.4 Programming Example demonstrates the .file pseudo-op.
Line Number Pseudo Operation. Each section in the object file has a line-number table
associated with it that maps line numbers in the source code to addresses within the
section. A line-number entry may be made using the .In pseudo operation as:
.In lind,valuel
The operand line must have a value of ABSOLUTE type that gives a line number in the
source code. The optional operand value, if present, must have a value of type TEXT,
DATA, or BSS that gives the address within the section where the line number occurs. If
the value operand is missing, the value of the current location counter will be used as the
address of the line number.
Function Calling Sequence
The WE 32100 Microprocessor C language stack frame and calling sequence are discussed
in this section. This information is intended for those who require a detailed knowledge of
the implementation of C function calls or need to perform assembly language function
calls. The stack frame is examined, paying particular attention to the size and location of
its contents. An example of a typical function call is given, describing the needs of the
called and calling programs. High-level code that depends on these implementation details
should be avoided.
5-37

SOFTWARE GENERATION PROGRAMS
Function Calling Sequence

Four registers are manipulated as part of each function call. These are the frame pointer
(FP), r9; the argument pointer (AP), rIO; the stack pointer (SP), r12; and the program
counter (PC), r15.
The frame pointer and argument pointer are only affected by the function call and return
instructions. In C language, the frame pointer points to the location in the stack that is the
start of the area containing local variables for that function. The argument pointer points
to the location in the stack that contains the first of the set of arguments for that function.
The calling sequence is presented as if the C compiler were implementing the function call,
i.e., assembler instructions have been generated, and m32as is translating to the processor
instruction set. Two machine independent instructions, call and save, establish the calling
environment and one machine independent instruction, ret, unwinds it. If the
corresponding processor instructions were being used, the CALL and SA VE instructions
would establish the calling environment, and two instructions RESTORE and RET would
be required to conclude the function properly. Thus the processor instruction set requires
two instructions as opposed to one assembler instruction for this task. The machine
independent instructions give an additional degree of control in the calling sequence, while
the processor instructions have a closer interaction with the CPU. The processor
implementation of these instructions is described in the Stack Frame section below. The
four affected registers are initially set as:
1.

PC. The program counter is set to the address of the first executable instruction of
the calling program.

2.

SP. The stack pointer points to the top of the stack and is properly set so that a new
procedure may be called.

3.

FP. The frame pointer points just past the top of the register save area. The register
save area is a FIXED size region created on the stack by the function call instructions
for saving registers. Just past the register save area is a stack region reserved to store
temporary (also called automatic) variables for a function.

4.

AP. The argument pointer points to the BEGINNING of a list of arguments to the
function.

The stack frame reserves space for six registers in addition to the PC, FP, and AP. These
six registers correspond to the six registers available as register variables in C programs.
Note that the PC, FP, and AP are always pushed on the stack in a function calling
sequence; the SP is not because its value is always implicit.
Although space is reserved on the stack for up to six registers plus the AP and FP, only the
AP and FP MUST be pushed. The remaining six user registers should be pushed (via the
save instruction) only when necessary.
Stack Frame. A stack frame is created at run time for each instance of a function call.
The frame is destroyed when the called function returns to the calling function. Each
stack frame contains the information needed to restore the calling function to its prior state
(i.e., the state it was in before it made the function call). The stack frame also contains
the arguments passed to it by the caller, space for its automatic variables, and space for
any temporary variables needed during execution. The stack begins at lower addresses and
5-38

SOFfW ARE GENERA nON PROGRAMS
Function Calling Sequence

grows upward to higher addresses. Figure 5-3 shows a diagram of a typical stack frame.
Actions of Calling Function. To make a function call, the calling function must first push
all of the called functions onto the stack. The arguments are pushed in the same order as
they appeared in the function call. Every argument must be pushed on the stack as a 32bit quantity. Characters must be converted to integers, and structures of uneven length
must be filled out to word boundaries, even though the last byte(s) are meaningless. Also,
multiple word arguments, such as structures, will require multiple pushes.

For example, the following section of code implements a C level function of the form
func (A,B,C)
where A and C are integer arguments and B is a character (byte) argument. The machine
independent code to call func is:

pushw
pushzb
pushw
call

A
8
C
&3,func

#extend byte to 32 bits

#call the function, specifying
#the number of arguments

The equivalent processor instructions are:
PUSHW
PUSHW
PUSHW
CALL

A

{ubyte}8
C
-12(%sp),func

The last statement is a call to the desired function, thus transferring control to the called
function. This process is accomplished by the machine independent call instruction.
Figure 5-4 shows the stack after the call has been executed.
Actions of Called Function. The called function completes the initialization started by the
caller. The first responsibility of the called function is to use the save instruction to
implement a C procedure frame. The save instruction can save up to six registers (r3
through r8) so they may be used by the function. After saving the specified number of
registers, the save instruction adjusts the stack pointer and frame pointer to point beyond
the end of the fixed-size register save area. After executing a save instruction specifying
that five registers should be saved, the stack would look like Figure 5-5.

The remaining responsibility of the called function is to allocate space for the automatic
and temporary variables it will use. The function does this by adding a constant to the
stack pointer. This leaves %sp pointing somewhere above %fp in the stack. The stack
frame then appears as shown on Figure 5-3. Only after this has been accomplished should

5-39

SOFfWARE GENERATION PROGRAMS
Function Calling Sequence

the called function begin to execute.
In the above example of the call to function func, the called function should have the
machine independent syntax:
func:

save
addw2

&5
&8,%sp

#save the caller's registers
#allocate stack space for the
automatic and temporary variables

&5

#restore registers and return to caller

{function body}

ret

The equivalent processor instructions are:
func:

SAVE
ADDW

%r4
&8,%sp

RESTORE
RET

%r4

To return to the caller, a function should execute an machine independent return (RET)
instruction. This is mapped into processor RESTORE and RET instructions. The
RESTORE instruction is the inverse of the SAVE instruction; Le., it restores up to six
registers and the frame pointer. After the RESTORE instruction, the stack is as described
after the call instruction (see Figure 5-4).
Note: The number of registers to be restored MUST be the same as the number of
registers saved; otherwise the results are undefined.
The RET instruction is the inverse of the call instruction; Le., RET returns the stack to the
state it was in before the function call.
When the routine accesses local data in the stack, it must do so by offsets from the frame
pointer. A routine accessing data passed to it as an argument must use offsets from the
argument pointer.
Locations in the stack area above the stack pointer are not protected from being destroyed
by interrupting processes and should not, therefore, be used without first incrementing the
stack pointer. The push instruction provides a convenient way of allocating stack space a
word at a time. In cases where speed is critical and a large number of words are to be
stored, it may be more efficient to allocate the total size of the area needed with a single
add to the stack pointer.

5-40

SOFfWARE GENERATION PROGRAMS
Function Calling Sequence

% sp

% fp

--

AUTOMATIC VARIABLES
REGISTER 8

•
•
•
REGISTER 3
FRAME POINTER
ARGUMENT POINTER
PROGRAM COUNTER

SAVED
REGISTERS

ARGUMENT N
ARGUMENT N-1

•

% ap

-

·•

ARGUMENT 1
PREVIOUS STACK FRAME

Figure 5-3. Typical Stack Frame for a Function Call

5-41

SOFfWARE GENERATION PROGRAMS
Function CaUing Sequence

"sp~

r-----------------~

OLD AP
OLD PC
ARGUI'IENT C
ARGUI'IENT B
"ap~

ARGUI'IENT A
PREVIOUS FRAI'IES

Figure 5-4. Stack Frame Following a Call Instruction

Figure 5-5. Stack Frame After Three Registers are Saved

5-42

SOFTWARE GENERATION PROGRAMS
Programing Example

The SP should never be modified directly except with the push and pop instructions. These two
instructions automatically increment or decrement the stack pointer. If a program took such action
directly, and care was not taken, the contents of the restored registers could be destroyed. by
subsequent stack manipulations.

5.2.3 Exception Conditions
Several kinds of events may occur that will interrupt the execution of a program. These may either
be internally generated, that is, recognized and generated by the processor, or externally generated,
such as an I/O interrupt for a memory fault.

5.2.4 Programming Example
Following is an example of the compiler output and the assembler output for the function prefix.
The prefix function consists of C language code that determines if one string is a prefix of another.
The example includes many of the pseudo-ops explained in this chapter. These pseudo-ops form the
prologue and epilogue sections that the compiler always generates. The M4 processor can provide
these sections for assembly language programs if the -m option is specified and the defined macros
are used.
This example shows a program that was compiled, but not optimized. Therefore, the assembly code
contains #REGAL statements that were inserted by the compiler for use by the optimizer, but never
used. Since these lines have the format of assembler comments, they are simply ignored by the
assembler.
Line numbers have been added for convenience; otherwise, the left column presents all of the
machine code produced by the m32cc compiler. The right column presents the corresponding C
language statements. The correspondence between C code and assembly code can be seen for if and
while statements.

Assembly Code
1.
2.
3.
4.
5.

6.
prefix:
7.
8.

9.
10.
11.

.file
.data
.text
.align
.def
.val
.scl
.type
.endef
.globJ
save
addw2
movw
movw
jmp

C Language Statement

"prefix.c"

prefix(a,b)

4
prefix;
prefix;
2;
044;

char *a,*b;
{char *p;

prefix
&.Rl
&.Fl,%sp
4(%ap),4(%fp)
O(%ap),O(%fp)
.L30

char *q=b;
p=a;

5-43

SOFTWARE GENERATION PROGRAMS
Programing Example

.L31:
12.
13.
14.
15.
16.
17 .
.L32:
.L30:
18.
19.
20.
21.
.L33:
.L29:
22.
23.
#REGAL
#REGAL
#REGAL
.L28:
24.

25.
26.
27.
28.
29.

30.

addw2
addw2
cmpb
je
movw
jmp

&1,O(%fp)
&1,4(%fp)
*0(%fp),*4(%fp)
.L32
&O,%rO
.L28

cmpb
je
cmpb
jne

*O(%fp),&O
.L33
*4(%fp),&0
.L31

while«*p!=NULL)
&&
(*q!=NULL» (

movw
jmp
0
48
48

&1,%rO
.L28
NODBL
AUTO
AUTO

return(J);

.def
.val
.scl
.line
.endif
.In
.set
.set
ret
.def
.val
.scl
.endif
.data

p++;
q++;
if(*p!=*q)
return (O);}

o(%fp)
4 (%fp)

.ef;

.,
101;
10;
10
.Fl,8
.RI,O
&.Rl
prefix;

.,
-1;

A disassembly of the assembler output below shows the processor instructions for this
routine. Note that the function saves no registers, and therefore starts with SAVE %fp.
The assembler directives have been omitted.
section
prefix 0

.text
SAVE
ADDW2
MOVW

5-44

%fp
&Ox8,%sp
Ox4(%ap) .Ox4(%fp)

SOFTWARE GENERATION PROGRAMS
Machine Independent Instruction Set

MOVW
BRB
INCW
INCW
CMPB
BEB
CLRW
BRB
TSTB
BEB
TSTB
BNEB
MOVW
BRB
RESTORE
RET
NOP
NOP

o(%ap) ,0 (%fp)
Ox11 <20>

o(%fp)

Ox4(%fp)
*Ox4(%fp}, *OxO(%fp)
Ox6 <20>
%rO
Ox11 <2f>
*OxO(%fp)
Ox7 <2a>
*Ox4(%fp)
-Ox17 <11>
&Ox1,%rO
Ox2 <2f>
%fp

This listing was actually produced by disassembling the object file prefix.o with the m32dis
utility described in 5.5 UTILITIES AND LIBRARY ROUTINES.

5.2.5 Machine Independent Instruction Set
The machine independent instructions are listed alphabetically by mnemonic in Table 5-6.
Many instructions have three forms (byte, halfword and word) that are characterized by a
b, h, or w in their names. The term "complex" appearing under the mapping heading
indicates that an instruction has a complex (one-to-many) mapping into a sequence of
WE 32100 Microprocessor instructions. Instructions with simple (one-to-one) mapping
map to a corresponding processor instruction with the possibility of an optimized form. If
an instruction has an optimized form, the m32as assembler will map that instruction into a
different hexadecimal encoding than is used for the unoptimized form.

5-45

SOFTWARE GENERATION PROGRAMS
Machine Independent Instruction Set

Table 5-6.
Mnemonic
acjl
acjle
acjleu
acjlu
addb2,addh2,addw2
addb3,addh3,addw3
alsw2
alsw3
andb2,andh2,andw2
andb3,andh3,andw3
arsw2
arsw3
atjnzb,atjnzh,
atjnzw
bitb,bith,bitw
call
cmpb,cmph,cmpw
divw2
divw3
extzv
insv
jbc
jbs
je
jg
jge
jgeu
jgu
jl
jle
jleu
jlu
jmp
jne
jneg
jnneg
jnpos

5-46

Machine Independent Instruction Set

,

Name
Add, compare, and jump less
Add, compare, and jump less or equal
Add, compare, and jump less or equal
unsigned
Add, compare, and jump less unsigned
Add (2 operand) - byte, halfword, word
Add (3 operand) - byte, halfword, word
Arithmetic left shift (2 operand)
Arithmetic left shift (3 operand)
AND (2 operand) - byte, halfword, word
AND (3 operand) - byte, halfword, word
Arithmetic right shift (2 operand)
Arithmetic right shift (3 operand)
Add, test, and jump not zero - byte,
halfword, word
Bit test - byte, halfword, word
Call
Compare - byte, halfword, word
Divide (2 operand)
Divide (3 operand)
Extract field
Insert field
Jump on bit clear
Jump on bit set
Jump equal
Jump greater
Jump greater or equal
Jump greater or equal unsigned
Jump greater unsigned
Jump less
Jump less or equal
Jump less or equal unsigned
Jump less unsigned
Jump
Jump not equal
Jump negative
Jump not negative
Jump not positive

Mapping
Complex
Complex
Complex
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Complex
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple

SOFfWARE GENERATION PROGRAMS
Machine Independent Instruction Set

Table 5-6.
Mnemonic

Machine Independent Instruction Set  < <= >=

&

I

&&

II
= += -= *= /=

5-52

SOFfWARE GENERATION PROGRAMS
Memory Configurations

The above operators have the same meaning as in C language. The associativity is also the
same as in C language, with left to right associativity except for !, -(unary), =, +=, -=,
*=, and 1=. Operators on the same line have the same precedence.
Assignment Statements
External symbols may be defined and assigned addresses using the assignment statement.
The assignment statement syntax is:
symbol

expression;
or
symbol op = expression;
=

where op is one of the operators
by a semicolon (;) .

+, -,

*, or I. Assignment statements must be terminated

All assignment statements, with the exception of the one case described in the following
paragraph, are evaluated after allocation has been performed and all input-file-defined
symbols have been appropriately relocated, but before the actual relocation of the text and
data itself. Therefore, if an assignment statement expression contains any symbol name,
the address used for that symbol in the evaluation of the expression reflects the symbol
address in the output object file. However, within text and data, references to symbols
given a value through an assignment statement will access this latest assigned value.
Assignment statements are processed in the same order as input to m321d.
Assignment statements are normally placed outside the scope of section-definition
directives (see Creating and Defining Symbols at Link-Edit Time in this section). However,
there exists a special symbol, called dot or ".", which can occur only within a sectiondefinition directive. This symbol refers to the current virtual address of the link editor
location counter. Thus, assignment expressions involving "." are evaluated during the
allocation phase of m321d. Assigning a value to the "." symbol within a section-definition
directive increments and resets the m321d location counter, and can create holes within the
section. Assigning the value of the "." symbol to a conventional symbol permits the final,
allocated address of a particular point within the link edit run to be saved.
Align is provided as a shorthand notation to allow alignment of a symbol to an n-byte
boundary within an output section, where n is a power of two. For example, the expression
align(n)
is equivalent to
(.+n-) & '" (n-I)

Memory Configurations
By default, the link editor considers the target processor to have an address range of 56
kbytes, numbered from OxlOOOOO to OxlOCFFF. This comprises the virtual address space
into which all input files are linked.

5-53

SOFTWARE GENERATION PROGRAMS
Memory Configurations

To help allocate space, virtual memory is partitioned into configured and un configured
memory. By default, all virtual memory is treated as configured, and unconfigured
memory is treated as reserved and unusable by the link editor.
Note: Nothing can ever be linked into unconfigured memory. Thus, making a certain
memory range unconfigured is one way of marking the addresses in that range as illegal or
nonexistent with respect to the linking process.

Memory configurations other than the default must be explicitly set up using the link
editor command language.
MEMORY directives are used to specify:
• The total size of the virtual space of the target WE 32100 Microprocessor.
• The configured and un configured areas of the virtual space.
If no directives are supplied, the link editor assumes that virtual memory is configured for
56 kbytes, beginning at address OxlOOOOO and ending at address OxlOCFFF.

MEMORY directives can assign an arbitrary name of up to eight characters to a virtual
address range. Output sections can then be forced to be bound at virtual addresses within
specific named memory areas. Memory names may contain upper- or lower-case letters,
digits, and the special characters '$', '.', and '_'. Names of memory ranges are only used
by the link editor and are not carried in the output file symbol table or headers.
When MEMORY directives are used, all virtual memory not described in a memory·
directive is considered to be unconfigured. Unconfigured memory is not used in the
allocation process of m32Id, and hence nothing can be link edited, bound, or assigned to
any address within unconfigured memory.
As an option to a MEMORY directive, attributes may be associated with a named
memory area. The attributes permit an output section to restrict where it will be bound;
such a section will be bound only to a memory area with the named attributes. The
attributes assigned to output sections in this manner are recorded in appropriate section
headers in the output file, thus making possible error checking in the future. (For
example, putting a text section into writable memory is a potential error condition.)
Currently, error checking of this type is not implemented.
Attributes that are currently accepted are:
• R

Readable memory

• W Writable memory
• X

Executable memory, i.e., instructions may reside in this memory

• I

Memory that can be initialized; stack areas are typically not initialized.

Other attributes may be added in the future if necessary. If no attributes are specified on
a MEMORY directive, or if no MEMORY directives are supplied, memory areas will
assume all the attributes R, W, X, and I.

5-54

SOFTWARE GENERAnON PROGRAMS
Section Definition Directives

The syntax of the MEMORY directive is:
MEMORY {

namel (attr): origin = nl,length = n2
name2(attr): origin = n3, length = n4
etc.
The keyword origin (or org or 0) must precede the origin of a memory range, and the
keyword length (or len or l) must precede the length, as shown in the above prototype.
The origin operand refers to the virtual address of the memory range. Origin and length
are entered as 32-bit constants in either decimal, octal, or hexadecimal (using standard C
syntax). Origin and length specifications, as well as individual MEMORY directives, may
be separated by either white space or commas.
By specifying MEMORY directives, the user can tell the link editor that memory is
configured in some manner other than the default. For example, if it is necessary to
prevent anything from being linked to the first OxlOOOO words of memory, a MEMORY
directive can accomplish this:
MEMORY

valid: org

=

OxlOOOO, len

=

OxfeOOOO

Section Definition Directives
A section is the smallest relocatable unit of an object file and must reside in a contiguous
block of memory. Each section has a starting virtual address and a size. Section headers
(which are described in 5.4 OBJECT FILE FORMAT) start each file and contain
information describing all included sections. Sections from input files are combined to
form output sections containing executable text, data, or a mixture of both. Although
there may be "holes" or gaps between input sections and between output sections,
contiguous storage is allocated within each output section.
SECTIONS directives describe how input sections are to be combined, direct where to
place output sections (both in relation to each other, and to the entire virtual memory
space), and permit the renaming of output sections.
In the default case where no SECTIONS directives are given, each input section appears
in an output section of the same name. For example, if a number of object files from the
compiler are linked, each containing the three sections, .text, .data, and .bss, the output
object file will also contain three sections, .text, .data, and .bss. If two objects files are
linked, one containing sections sl and s2, and the other containing sections s3 and s4, then
the output object file will contain the four sections sl, s2, s3, and s4. The order of these
sections depends on the order in which the link editor saw the input files.

5-55

SOFTWARE GENERATION PROGRAMS
Section Definition Directives

The basic syntax of the SECTIONS directive is:
SECTIONS
secnamel:

secname2:

file_specifications,
assignment _statements
}
file_specifications,
assignment _statements
}

etc.
The various types of section definition directives are discussed in the remainder of this
section.
Virtual Address and Bindings. All addresses manipulated by m321d are 32-bit absolute
addresses defined relative to address zero. The address of a section means the virtual
address of the start of the section. The address of a symbol is the virtual address of the
text or data word defining the symbol. Physical addresses to the link-editing are equivalent
to virtual addresses, Le., no distinction is made by m321d.
It is often necessary to have a section begin at a specific, predefined address. The process
of specifying this starting address is called binding, and the named section is said to be
"bound at" or "bound to" the required address. Binding generally refers to output sections,
but it is also possible to bind global symbols using an assignment statement from the link
editor command language.

File Specifications. Within a section definition, the files and sections of files to be included
in the output section are listed as they appear in the output section. Sections from an input
file are specified by
filename (secname)

or

filename (secnaml secnam2 .,. )

Input file sections are separated either by white space or commas, as are the file
specifications.
If a filename appears with no sections listed, all sections from the file are linked into the
current output section. For example,

SECTIONS
outsec1:
file 1.0 (sec 1)
file2.0
file 3.0 (sec 1,sec2)

links all sections from file2.0 into the output.

5-56

SOFTWARE GENERATION PROGRAMS
Section Definition Directives

The order in which the input sections appear in the output section outsecl is given by:
1.

Section sec 1 from file 1.0

2.

All sections from file2.0, in the order they appear in the file

3.

Section secl from file3.0, and then section sec2 from file3.0.

If there are any additional input files that contained input sections also named outsecl,
these sections are linked following the last section named in the definition of outsecl (in
this example, file3.0 (sec2)).

There may be additional input sections in the files file.o, file2.0, and file3.0, other than
those specified as going into output section outsecl. These input sections are put into
output sections with corresponding names.
Load a Section at a Specified Address. Binding an output section to a specific virtual
address is done by a link editor command language option, as shown in the following
SECTIONS directive example:
SECTIONS
outsec addr: { ... }
etc.

where addr is the binding address, expressed as a C language constant. If outsec will not
fit at addr (perhaps because of holes in the memory configuration, or because out sec is too
large to fit without overlapping some other output section), then m32ld issues an
appropriate error message.
As long as output sections do not overlap, they can be bound anywhere in configured
memory. The SECTIONS directives defining output sections need not be given to m321d
in any particular order.
Aligning an Output Section. It is possible to request that an output section be bound to a
virtual address that falls on an n-byte boundary, where n is a power of 2. The ALIGN
option of the SECTIONS directive performs this function, so that the option
ALIGN(n)
is equivalent to specifying a binding address of
(.+n- 1) &

'V

(n- 1)

For example:
SECTIONS
outsec ALIGN(Ox20000): { ... }
etc.

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SOFfWARE GENERATION PROGRAMS
Section Definition Directives

The output section outsec is not bound to any given address, but will be linked to some
virtual address that is a multiple of Ox20000 (e.g., at address OxO, Ox20000, Ox40000,
Ox60000, etc.).
Grouping Sections Together. The default allocation algorithm for m32ld is:
1.

Link all input .text sections together into one output section. This output section is
called .text and is bound at the address OxIOOOOO.

2.

Link all input .data sections together into one output section. This output section is
called .data and is bound at an address aligned to OxS.

3.

Link all input .bss sections together into one output section. This output section is
called .bss and is allocated to follow immediately after the output section .data. Note
that the output section .bss is not given any particular address alignment.

Specifying any SECTIONS directive with an ifile inhibits this default allocation.
The default allocation of m32ld is equivalent to supplying the following directives:
SECTIONS

(
.text OxIOOOOO: 0
GROUP ALIGN(OxS):
.data: 0
.bss: 0
}

The GROUP command ensures that the two output sections .data and .bss are allocated
together (j.e., grouped). Binding or alignment information may be supplied only for the
group and not for the output sections contained within the group. The sections making up
the group are allocated in the order listed in the directive.
If .text, .data, and .bss are to be placed in the same segment, the following SECTIONS
directive could be used:

SECTIONS

(
GROUP:
.text: 0
.data: 0
.bss: 0

Note that there are still three output sections <.text, .data, and .bss), but now they are
allocated into consecutive virtual memory.
This entire group of output sections could be bound to a starting address, or aligned, simply
by adding a field to the GROUP directive. To bind at OxcOOOO, use:
GROUP OxcOOOO: {

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SOFTWARE GENERATION PROGRAMS
Section Definition Directives

The output section .text is bound at OxcOOOO with this directive. To align to OxlOOOO use:
GROUP ALIGN(OxIOOOO): (
Now the output section .text is aligned to OxIOOOO. In both cases, the remaining members
of the group are allocated, in order of their appearance, into the next available memory
locations.
When the GROUP directive is not used, each output section is treated as an independent
entity. Thus the directive
SECTIONS

.text: U
.data ALIGN(Ox20000):
.bss: U

U

causes the .text section to start at virtual address OxO, and the .data section to start at a
virtual address aligned to Ox20000. The .bss section follows immediately after the .text
section if there is enough space. If there is not, it follows the .data section.
Note: The order in which output sections are defined to the link editor can not be used to
force a certain allocation order in the output file.
Creating Holes Within Output Sections. The dot symbol (".,,) can appear in an assignment
instruction only within a section definition. When appearing on the left side of an
assignment statement, dot causes the link editor location counter to be incremented/reset,
and leaves a hole in the output section. Consider the following section definition:
outsec:

.+= OxIOOO;
fl.o Ctext)

.+= OxIOO;
f2.oCtext)

.= align (4);
f3.oCtext)

The effects of this command are:
• A OxlOOO-byte hole is left at the beginning of the section. Input file fl.oCtext) is linked
after this hole.
e The .text section of input file f2.0 begins OxlOO bytes following the end of fl.o(.text) .
• The .text section of f3.0 is linked to start at the next full word boundary following the
text of f2.0, with respect to the beginning of "outsec".
Holes built into output sections in this manner are initialized using a fill character, either
the default fill character (OxOO) or a supplied fill character. The option -f is used to
supply a fill character.

5-59

SOFTWARE GENERATION PROGRAMS
Section Definition Directives

To help allocate and align addresses within an output section, the link editor treats the
output section as if it began at address zero. As a result, if (in the above example), outsec
ultimately was linked to start at an odd address, then the part of outsec built from
f3.oCtext) would also start at an odd address - even though f3.oCtext) was aligned to a
full-word boundary. This could be prevented by specifying an alignment factor for the
entire output section:
outsec ALIGN(4):
Note that the m32as assembler always pads the sections it generates to a full word length,
making explicit alignment specifications unnecessary. This also holds true for the m32cc
compiler.
Expressions that decrement dot are illegal. For example, subtracting a value from the
location counter is not allowed, because overwrites are not allowed. The most common
operators in expressions that assign a value to dot are += and align.
Creating and Defining Symbols at Link-Edit Time. The assignment instruction of the link
editor can be used to give symbols a value that is link-edit dependent. Typically, there are
three types of assignments:
1.

Use of dot to adjust the m32ld location counter during allocation.

2.

Use of dot to assign an allocation-dependent value to a symbol.

3.

Assigning an allocation-independent value to a symbol.

The first type of assignment has already been discussed in the previous section. The
second type provides a means to assign addresses, known only after allocation, to symbols.
For example:
SECTIONS

{
outsecl:
outsec2:

{ ... }
(
file 1.0
file2.o(s2)
s2 end =.-1;

The symbol s2_start is defined to be the address of file2.o(s2), and s2_end is the address of
the last byte of file2.0 (s2) .
Assignment instructions involving "." must appear within sections definitions, because they
are evaluated during allocation. Assignment instructions that do not involve ".", although
they can appear within sections definitions, typically do not. Such instructions are
evaluated after allocation is complete. Reassignment of a defined symbol to a different
address is dangerous. If a symbol within .data is defined, initialized, and referenced within
a set of object files being link edited, the symbol table entry for that symbol will be

5-60

SOFfWARE GENERATION PROGRAMS
Section Definition Directives

changed to reflect the new, reassigned address, but the associated initialized data will not
be moved. This link editor issues warning messages for each defined symbol that is being
redefined with an ifile. However, assignments of absolute values to undefined symbols is
safe, because there are no initialized data associated with the symbol.
Allocating a Section Into Named Memory. Within a SECTIONS directive, it is possible to
specify that a section be linked somewhere within a named memory (as previously shown in
a MEMORY directive). This allocation method uses the> notation borrowed from the
UNIX System concept of "redirected output".
MEMORY

(
meml:
mem2(RW):
mem3(RW):
meml:

O=OxOOOOOO
O=Ox020000
O=Ox070000
O=Ox120000

I=Oxl0000
I=Ox40000
I=Ox40000
I=Ox04000

}
SECTIONS

(

outsec 1:
outsec2:

(fl.o (.da ta) } > mem 1
(r2.0(.data)} > mem3

This ifile segment directs m321d to place outsecl anywhere within the memory area named
meml; i.e., somewhere within the address range OxO-Oxffff or OxI20000-0xI23fff. Output
section outsec2 is placed somewhere in the address range Ox70000-0xaffff.
Initialized Section Holes or BSS Sections. When "holes" are created within a section, the
link editor normally outputs bytes of zeros as "fill". By default, .bss sections are not
initialized at all. That is, no initialized data are generated for any .bss section by the
assembler nor supplied by the link editor (not even zeros).
Initialization options can be used in a SECTIONS directive to set such holes or output .bss
sections to an arbitrary two-byte pattern. Such initialization options apply only to .bss
sections or holes. As an example, an application might want an uninitialized data table to
be initialized to a constant value without recompiling the .0 files; another application may
want a hole in the text area to be filled with a transfer to an error routine.
Either specific areas within an output section or the entire output section may be specified
as being initialized. However, since no text is generated for an uninitialized .bss section,
initializing part of such a section causes the entire section to be initialized. In other words,
to combine a .bss section with a .text or .data section (both of which are initialized), or to
initialize only part of an output .bss section, one of the following must hold:
1.

Explicit initialization options must be used to initialize all .bss sections in the output
section.

2.

The link editor must use the default fill value to initialize all .bss sections in the
output section.

5-61

SOFTWARE GENERATION PROGRAMS
Notes on the Use of m321d

Consider the following ifile:

SECTIONS
sec1:
fLo

. =+ Ox200;
f2.oCtext)
) = Ox2f2f
sec2:

(
fl.o(.bss)
f2.0(.bss) = Ox1234
)

sec3:

(

f3.0(.bss)

) = Oxffff
sec4:

(
f4.0(.bss) )

In this example, the Ox200 byte hole in section sed is filled with WAIT instructions
(Ox2f2f). In the section sec2, fl.o(.bss) is initialized to the default fill value of OxOO, and
f2.0(.bss) is initialized to Ox1234. All .bss sections within sec3 as well as holes are
initialized to Oxffff. Section sec4 is not initialized (i.e., no data are written to the object
file for sec4).
Notes on the Use of m32ld
Notes and special considerations on the use of the link editor, including initialization, use
of archive libraries, and other detailed aspects of m321d are presented here.
Changing the Entry Point. By default, a a.out header is written to the output file. The
a.out header contains a field for the primary entry point of the file. This field is set by the
following rules (listed in the order of application):
I.

The value of the symbol in the -e flag, if present, is used.

2.

The value of the symbol _start, if present, is used.

3.

The value of the symbol main, if present, is used.

4.

The value zero is used.

Thus, an explicit entry point can be assigned to this m32a.out header field through the -e
option, or by using an assignment instruction in an input file of the form:
_start

=

expression;

If the link editor is called through m32cc, a startup routine will automatically be linked in.
The user must be careful when calling the link editor directly or when changing the entry

5-62

SOFTWARE GENERATION PROGRAMS
Notes on the Use of m321d

point. The user must supply the startup routine or insure that the program performs the
necessary steps in order to execute correctly.
Use of Archive Libraries. Each member of an archive library (e.g., libc.a) is a complete
object file (typically consisting of the standard three sections: .text, .data, and .bss).
Archive libraries are created through the use of the m32ar command from object files
generated by running m32cc or m32as. Each library member has a "magic number". The
link editor enforces a policy that all input object files must have the same magic number.
Any object file that fails this test is not processed and generates a fatal m321d error.
However, this policy has an important exception - members of archive libraries with the
wrong magic number are silently skipped. This is not considered an error, and no message
is generated.
An archive library is always processed using selective inclusion. Only those members
which resolve existing undefined symbol references are taken from the library for link
editing.
Libraries can be placed both inside and outside section definitions. In both cases, a
member of a library is included for linking whenever:
• There is a reference to a symbol defined in that member
• The reference is found by the link editor before the actual scanning of the library.
When a library member is included by searching the library inside a SECTIONS directive,
all input sections from the member are included in the output section being defined. When
a library member is included by searching the library outside of a SECTIONS directive,
all input sections from the member are included into the output section with the same
name. That is, the .text section of the member goes into the output section named .text,
the .data section of the member goes into .data, and the .bss section of the member goes
into .bss. If necessary, m321d defines new output sections to provide a place to put the
input sections.
The -I option is a shorthand notation for specifying an input file coming from a predefined
directory and having a predefined name. By convention, such files are archive libraries,
although they need not be. Furthermore, archive libraries can be specified without using
the -I option, by simply giving the full or relative file pathname.
The ordering of archive libraries is important, since for a member to be extracted from the
library it must satisfy a reference that is known to be unresolved at the time the library is
searched. Archive libraries can be specified more than once; they are searched from the
beginning every time they are encountered. The proper order can often be determined with
the utility m3210rder, as described in 5.5 UTILITIES AND LIBRARY ROUTINES.
Consider the following example:
• The input files filel.O and file2.0 each contain a reference to the external function FCN
• Input filel.O contains a reference to symbol ABC
• Input file2.0 contains a reference to symbol XYZ

5-63

SOFTWARE GENERATION PROGRAMS
Notes on the Use of m32ld

• Library liba.a, member 0, contains a definition of XYZ
• Library libc.a, member 0, contains a definition of ABC
• Both libraries have a member 1 that defines FCN.
If the m32ld command line is entered as

m32ld filel.o -la file2.0 -Ie
the FCN references are satisfied by liba.a, member 1; ABC is obtained from libc.a,
member 0; and XYZ remains undefined because the library liba.a is searched before file
2.0 is specified. If the m32ld command line is entered as
m32ld filel.o file2.0 -/a -Ie
the FCN references are satisfied by liba.a, member 1; ABC is obtained from libc.a,
member 0; and XYZ is obtained from liba.a, member o. If the m32ld command line is
entered as
m32ld filel.o file2.0 -Ie -la
the FCN references are satisfied by libc.a, member 1; ABC is obtained from libc.a,
member 0; and XYZ is obtained from liba.a, member o. If the m32ld command line is
entered as
m32ld file.o file2.0 -Ie -/a
The FCN references are satisfied by libc.a., member 1; ABC is obtained from libc.a.,
member 0; and XYZ is obtained from liba.a., member O.
The -u option can be used to force the linking of library members when the link edit run
does not contain an actual external reference to the members. For example,
m32ld -u rout! -/a
created the undefined symbol rout! in the link editor global symbol table. If any member
of library liba.a defines this symbol, that member (and perhaps other members as well) is
extracted. Without the -u option, there would have been no trigger to cause m32ld to
search the archive library.
Dealing With Holes in Physical Memory. When memory configurations are defined such
that unconfigured areas exist in the virtual memory, each application or user must assume

5-64

SOFTWARE GENERATION PROGRAMS
Notes on the Use of m32ld

the responsibility of forming output sections that fit into memory. For example, assume
memory is configured as:

MEMORY {
meml:
mem2:
mem3:

0
0
0

=
=
=

OxOOOOO
Ox40000
Ox20000

1 = Ox02000
1 = Ox05000
1 = OxlOOOO

Let the files fl.o, f2.0, ... fn.o each contain the standard three sections .text, .data, and
.bss, and suppose the combined .text section contains Oxl2000 bytes. There is no
configured area of memory where this section can be placed. Appropriate directives must
be supplied to break up the .text output section so that m32ld can perform allocation. For
example:

SECTIONS {
txtl:
fLo (text)
f2.0 (.text)
f3.o (.text)

}
txt2:

{
f4.0 (.text)
f5.0 (text)
f6.0 (text)

etc.

Allocation Algorithm. The link editor forms output sections either according to
specifications in a SECTIONS directive or by combining input sections with the same
name. An output section can contain zero or more input sections. After determining the
composition of an output section, m32ld must then allocate the necessary configured virtual
memory. This task is performed using an algorithm that attempts to minimize
fragmentation of memory, thereby increasing the possibility that a link edit run will be able
to allocate all output sections within the specified virtual memory configuration. The
algorithm proceeds as:
1.

Any output sections with explicitly specified binding addresses are allocated.

2.

Any output sections to be included in a specific named memory are allocated. In both
this and the preceding step, each output section is placed into the first available space
within the (named) memory, with any alignment taken into consideration.

3.

Output sections not handled by one of the above steps are allocated.

If all memory is contiguous and configured (the default case), and no SECTIONS
directives are given, then output sections are allocated in the order of appearance to the

5-65

SOFTWARE GENERATION PROGRAMS
Notes on the Use of m321d

link editor, normally .text, .data and .bss. The .text output section starts at virtual address
OxlOOOOO; the .data and .bss output sections are grouped together and aligned to a Ox8byte virtual address. Otherwise, output sections are allocated in the order they were
defined or made known to the link editor. The first available space large enough to hold
them is used.
Subsystems (Incrementa)) Link Editing. To help generate a large system with modular and
hierarchical design methodology, m321d provides the capability to form subsystems and link
edit in smaller, more manageable increments. As previously mentioned, the output of the
link editor can be used as an input file to subsequent m321d runs providing that the
relocation information is retained (-r option). In large applications it may be desirable to
partition C programs into subsystems, link each subsystem independently, and then linkedit the entire application. For example:
Step I.
m321d -r

-0

outfilel ifilel

1* ifile *1
SECTIONS
ssl:
fLo
f2.0
fn.o

Step 2.
m321d -r

-0

outfiJe2 ifile2

1* ifile2 *1
SECTIONS
ss2:
g1.o
g2.0
gn.o

Step 3.
m321d -a -m

-0

final.out outfilel outfile2

By judiciously forming subsystems, applications may achieve a form of "incremental link
editing" whereby it is only necessary to re-Iink a portion of the total link edit when a few
programs are recompiled.

5-66

SOFTWARE GENERA nON PROGRAMS
DSECT, COPY and NOLOAD Sections

Two simple rules are followed when applying this technique:
I.

Place SECTIONS declarations only in incremental link edits. Be concerned only with
the formation of output sections from input files and input sections. Do not bind
output sections in these runs.

2.

Only allocation and memory directives, as well as any assignment statements, should
be included in the final m321d call.

Nonrelocatable Input Files. Normally an input file produced by a previous m321d run was

produced under the -r option. This option preserves relocation information and permits
sections of the output file to be relocated by subsequent m321d runs.
Upon detecting an input file that does not have relocation or symbol table information, the
link editor issues a warning message. Such information may have been removed by the -a
or -s options of the link editor, as described in 5.3.1 Command Line Options. However, the
link editor continues using the nonrelocatable input file.
For such a link edit to succeed (i.e., to actually and correctly incorporate all input files,
relocate all symbols, resolve all unresolved references, etc'), two conditions must be met by
the nonrelocatable input file:
I.

Each input file must not contain any unresolved external references.

2.

Each input file must be bound at the same virtual address where it was bound during
the m321d run that created it.

The m321d link editor does not issue an error message if these two conditions are
not met for all nonrelocatable input files. Therefore, extreme care must be exercised when
supplying such input files to the link editor.
Note:

DSECT, COPY and NOLOAD Sections
Sections may be given a "type" in a section definition as shown in the following example:
SECTIONS
{
name I Ox200000 (DSECT)
name20x400000 (COPY)
name3 Ox600000 (NOLOAD)

:{filel.o}
:{file2.0}
:{file3.0}

The DSECT option creates what is called a "dummy section". A "dummy section" has the
following properties:
• It does not participate in the memory allocation for output sections. As a result, it takes
up no memory and does not show up in the memory map (the "-m" option) generated by
the link editor.
• It may overlay other output sections and even unconfigured memory. DSECTs may
overlay other DSECTs.

5-67

SOFTWARE GENERATION PROGRAMS
Output File Blocking

• The global symbols defined with the "dummy section" are relocated normally. That is,
they appear in the output file's symbol table with the same value they would have had if
the DSECT were actually loaded at its virtual address. DSECT-defined symbols can be
referenced by other input sections. Undefined external symbols found within a DSECT
will cause specified archive libraries to be searched and any members which define such
symbols will be link-edited normally (j.e., not in the DSECT or as a DSECT).
• None of the section contents, relocation information, or line number information
associated with the section is written to the output file.
In the above example, none of the sections from filel.o are allocated, but all symbols are
relocated as though the sections were link edited at the specified address. Other sections
may refer to any of the global symbols and they are resolved correctly.
A "copy section" created by the COpy option is similar to a "dummy section"; the only
difference being that the contents of a "copy section" and all associated information is
written to the output file.
A section with the "type" of NOLOAD differs in only one respect from a normal output
section: its text and/or data is not written to the output file. A NOLOAD section is
allocated virtual space, appears in the memory map, etc.

Output File Blocking
The BLOCK option, which can be applied to any output section or GROUP directive, is
used to direct m321d to align a section at a specified byte offset in the output file. It has
no effect on the address at which the section is allocated, nor on any part of the link editor
process. It is used only to adjust the physical position of the section in the output file.
SECTIONS
(

.text BLOCK(Ox200) : {}
.data ALIGN (Ox20000) BLOCK(Ox200) : { }
With this SECTIONS directive, m321d will ensure that each section (text and .data) is
physically written at a file offset which is a multiple of Ox200 (e.g., at an offset of 0,
Ox200, Ox400, ... , etc. in the file).

5.3.3 Error Messages
Corrupt Input Files
The following error messages indicate that the input file is corrupt, nonexistent, or
unreadable. The user should check that the file is in the correct directory with the correct
permissions. If the object file is corrupt, try recompiling or reassembling it.
• Can't open name
• Can't read archive header from archive name

5-68

SOFTWARE GENERATION PROGRAMS
Errors During Output

• Can read file header of archive name
• Can't read 1st word of file name
• Can't seek to the beginning of file name
• Fail to read file header of name
• Fail to read lnno of section sect of file name
• Fail to read magic number of file name
• Fail to read section headers of file name
• Fail to read section headers of library name member number
• Fail to read symbol table of file name
• Fail to ready symbol table when searching libraries
• Fail to read the aux entry of file name
• Fail to read the field to be relocated
• Fail to seek to symbol table of file name
• Fail to seek to symbol table when searching libraries
• Fail to seek to the end of library name member number
• Fail to skip aux entries when searching libraries
• Fail to skip the mem of struct of name
o Illegal relocation type
• Line nbr entry (num num) found for non-relocatable symbol: section sect, file name
• No reloc entry found for symbol
• Reloc entries out of order in section sect of file name
• Seek to name section sect failed
• Seek to name section sect lnno failed
• Seek to name section sect reloc entries failed
• Seek to relocation entries for section sect in file name failed

Errors During Output
These errors and messages occur because the link editor cannot write to the output file,
usually indicating that the file system is out of space.
• Cannot complete output file name. Write error.
• Fail to copy the rest of section num of file name
• Fail to copy the bytes that need no reloc of section num of file name
• 110 error on output file name

5-69

SOFTWARE GENERATION PROGRAMS
Internal Errors

Internal Errors
These messages indicate that something is wrong with the link editor internally. There is
probably nothing the user can do except get help.
• Attempt to free nonallocated memory
• Attempt to reinitialize the SDP aux space
• Attempt to reinitialize the SDP slot space
• Default allocation didn't put .data and .bss into the same region
• Failed to close SDP symbol space
• Failure dumping an AIDFNxxx data structure
• Failure in closing SDP aux space
• Failure to initialize the SDP aux space
• Failure to initialize the SDP slot space
• Internal error: audit...Eroups, address mismatch
• Internal error: audit...Eroups finds anode failure
• Internal error: auditJegions detected no regions built
• Internal error: fail to seek to the member of name
• Internal error: in allocate lists, list confusion (num num)
• Internal error: invalid aux table id
• Internal error: invalid symbol table id
• Internal error: negative aux table id
• Internal error: negative symbol table id
• Internal error: no symtab entry for DOT
• Internal error: out of tv slots
• Internal error: split_scns, size of sect exceeds its new displacement
• Internal error: .tv not aligned
• Internal error: .tv not built

Allocation Errors
These error messages appear during the allocation phase of the link edit. They generally
appear if a section or group will not fit at a certain address, or if the given MEMORY,
REGION, or SECTION directives conflict in some way. If using an ifile, the user should
check that MEMORY and SECTION directives allow enough room for the sections, that
nothing overlaps, and that nothing is being placed in configured memory.
• Bond address address for sect is not in configured memory

5-70

SOFTWARE GENERATION PROGRAMS
Misuse of Link Editor Directives

• Bond address address for sect overlays previously allocated section sect at address
• Can't allocate output section sect, of size num
• Can't allocate section sect into owner mem
• Default allocation failed: name is too large
• GROUP containing section sect is too big
• Memory types name1 and name2 overlap
• Output section sect not allocated into a region
• Sect at address overlays previously allocated section sect at address
• Sect, bonded at address, won't fit into configured memory
• Sect enters unconfigured memory at address

• Section sect in file name is too big

Misuse of Link Editor Directives
These errors and messages arise from the misuse of an input directive. Review the
appropriate section in the manual.
• Adding name(sect} to multiple output sections
The input section is mentioned twice in the SECTION directive.
• Bad attribute value in MEMORY directive: c
An attribute must be one of "R", "W", "X", or "I".
• Bad flag value in SECTIONS directive, option
Only the "-1" option is allowed inside of a SECTIONS directive.
• Bad fill value
The fill value must be a two-byte constant.
• Bonding excludes alignment
The section will be bound at the given address, regardless of the alignment of that
address.
• Cannot align a section within a group
• Cannot bond a section within a group
• Cannot specify an owner for sections within a group
The entire group is treated as one unit, so the group may be aligned or bound to an
address, but the sections making up the group may not be handled individually.
• DSECT sect can't be given an owner
• DSECT sect can't be linked to an attribute
Since dummy sections do not participate in the memory allocation, it is meaningless for
a dummy section to be given an owner or an attribute.
• REGIONS command not allowed in any instantiation other than b16

5·71

SOFTWARE GENERATION PROGRAMS
Misuse of Expressions

• Sect is a reserved section name
Currently only ".tv" is a reserved section name.
• Section sect not built
The most likely cause of this is a syntax error in the SECTIONS, directive.
• Semicolon required after expression
• Statement ignored
Caused by a syntax error in an expression.
• Usage of unimplemented syntax

Misuse of Expressions
These errors and messages arise from the misuse of expressions.
• Absolute symbol name being redefined
An absolute symbol may not be redefined.
• ALIGN illegal in this context
Alignment of a symbol may only be done within a SECTIONS directive.
• Attempt to decrement DOT
• Illegal operator in expression
• Misuse of DOT symbol in assignment instruction
The DOT symbol (".,,) cannot be used in assignment statements that are outside
SECTIONS directives.
• Symbol name is undefined
All symbols referenced in an assignment statement must be defined.
• Symbol name from file name being redefined
A defined symbol may not be redefined in an assignment statement.
• Undefined symbol in expression

Misuse of Options
These errors and messages arise from the misuse of options.
• Both -r and -s flags are set. -s flag turn off
Further relocation requires a symbol table
• Can't find library libx.a
• -L path too long (string)
• -0

file name too large (> 128 char), truncated to (string)

• Too many -L options, 7 allowed
Some options require whitespace before the argument, some do not. Including extra
whitespace, or not including the required whites pace is the most likely cause of the
following messages.
5-72

SOFTWARE GENERATION PROGRAMS
Miscellaneous Errors

• option flag does not specify a number
• option is an invalid flag
• -e flag does not specify a legal symbol name name
• -f flag does not specify a two-byte number
• No directory given with -L
• -0

flag does not specify a valid file name: string

• the -I flag (specifying a default library) is not supported
• -u flag does not specify a legal symbol name: name

Space Restraints
The following error messages may occur if the link editor attempts to allocate more space
than is available. This is more likely to occur on a PDP 11/70 Computer than on other
machines. The user should attempt to decrease the amount of space used by the link
editor. This may be accomplished by making the ifile less complicated, or by using the
"-r" option to create intermediate files.
• Fail to allocate num bytes for slotvec table
It

Internal error: aux table overflow

• Internal error: symbol table overflow
• Memory allocation failure on num-byte 'calloc' call
• Memory allocation failure on realloc call
• Run is too large and complex

Miscellaneous Errors
These errors and messages occur because of a misuse of the link editor in general.
• Archive symbol table is empty in archive name, execute 'ar ts name' to restore archive
symbol table
On systems with a random access archive capability, the link editor requires that all
archives have a symbol table. This symbol table may have been removed by strip.
• Can't create intermediate id file name
• Can't open internal file name
These two messages are possible only when the link editor is two processes. This would
indicate that the temp directory (usually /tmp or /usr/tmp) is out of space, or that the
link editor does not have permission to write in it.
• Can't create output file name
The user may not have write permission in the directory where the output file is to be
written.
5-73

SOFTWARE GENERATION PROGRAMS
Syntax Diagram for Input Directives

• Failure to load pass 2 of ld
This can only occur when the link editor is built as two processes (j.e., on the PDP
11170). The most likely cause is that the second process is not accessible to the first
one.
• File name has a section name which is a reserved ld identifier: .tv
• File name has no relocation information
• File name is of unknown type, magic number

=

num

• Ifile nesting limit exceeded with file name
Hiles may be nested 16 deep.
• Library name, member has no relocation information
• Multiply defined symbol sym, in name has more than one size
A mUltiply defined symbol may not have been defined in the same manner in all files.
• name(sect) not found
An input section specified in a SECTIONS directive was not found in the input file.
• Section sect starts on an odd byte boundary!
This will happen only if the user specifically binds a section at an odd boundary.
• Sections .text .data or .bss not found. Optional header may be useless
The UNIX System a.out header uses values found in the .text, .data, and .bss section
headers.
• Undefined symbol sym first referenced in file name
Unless the -r option is used, the link editor requires that all referenced symbols must be
defined.
• Unexpected EOF
Syntax error in the ifile.

5.3.4 Syntax Diagram for Input Directives


-> {}



-> 



- >
->
->
- >
->

< memory_spec>

- > < name> [ < attributes> 1: < origin _spec> i, 1< length _spec>



->

5-74

< sections>


< options>
MEMORY { ([,1 }}

({RlwlxlI})

SOFTWARE GENERATION PROGRAMS
Syntax Diagram for Input Directives



-> 

=





-> 

=





-> ORIGIN lolorglorigin



-> LENGTHllllenllength



-> SECTIONS {{ }}



-> 
lI



-> GROUP : {}[  1



-> 
 {[,l
l



->  :{ }[ ][  1



-> [][ ][  1



-> [][  l[ ][  1



-> 

< align_option>

->  «long»



-> ALIGN Ialign

< block_option>

->  «long»



-> BLOCKlbiock

< type _option>

-> (DSECT) I(NOLOADI (COpy)



-> = 
-> > 
-> > 



->  [(  1
-> 
-> 



->  {[,ll



-> -I

5-75

SOFTWARE GENERATION PROGRAMS
Syntax Diagram for Input Directives



->    



->  I.

< assign_op >

-> =1+=1-=1*=1/=



-> ;1,



->   
-> 

< binary_op >

->
->
->
->
->
->
->
->

*1/1%
+1»1«
==I!=I>I=

&
I

&&
II



->
->
->
->
->



 «term»
(  



->

!I-



->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->

-a
-e < wht_space > 
-f 
-i
-l
-m
-o 
-r
-s
-t
-u 
-x
-z

5-76

-F
-L

-M
-N

-s

SOFTWARE GENERATION PROGRAMS
Object File Format

-v
-x

->
-> -VS
->


-> any valid symbol name



-> any valid long integer constant

< wht_space >

-> blanks, tabs and new lines



-> any valid UNIX System filename.
This may include a full or partial pathname



-> any valid UNIX System pathname (full or partial)

5.4 OBJECT FILE FORMAT
The output file produced by the m32as assembler and the m321d link editor is in a format
called the Common Object File Format (COFF). Several target machines use this format,
and more than one operating system on some of those machines use it. Hence the word
Common is both descriptive and widely recognized as a unique name. Because systems
other than the WE 32100 Microprocessor use COFF, the format includes some symbols
and fields that appear to be extraneous. These items are extraneous for processor users,
and are only included to maintain commonality.
An object file that contains no errors or unresolved references can be executed on the
target processor.
The object file supports user-defined sections and contains extensive information for
symbolic software testing. An object file consists of a file header, optional header
information, a table of section headers, the data corresponding to the section headers,
relocation information, line numbers, a symbol table, and a string table. Figure 5-6 shows
this overall structure.
The common object file is not only simple enough to be incorporated into existing projects,
but advanced enough to meet the needs of yet unspecified operating systems. Some key
features are:
• Applications may add system-dependent information to the object file without causing
access utilities to become obsolete.
• A wealth of symbolic information is provided for the use of debuggers and other
applications.
• Some modifications in object file construction may be made by the user or source file
application at compile time.

5-77

SOFTWARE GENERATION PROGRAMS
Definitions

FILE HEADER
OPTIDNAL INFORMATION
(UNIX SYSTEM a.out HEADER)

••
•

SECTION 1 HEADER

•••

SECTION n HEADER
RAW DATA FOR SECTION 1

••
•
RAW DATA FOR SECTION

n

RELOCATION INFORMATION FOR SECTION 1

•••

RELOCATION INFORMATION FOR SECTION
LINE NUMBERS FOR SECTION 1

••
•

LINE NUMBERS FOR SECTION
SYMBOL TABLE
STRING TABLE

Figure 5-6.

n

n

Object File Format

5.4.1 Definitions
The object file specification uses the following terms:
Section

A section is the smallest portion of an object file that can be
relocated and can be treated as one distinct entity. The default
case has three sections: .text, .data, and .bss. Additional sections
are added to the default sections for multiple text segments, shared
data segments, or user-specified segments.

Physical Address

This is the 32-bit offset of a section with respect to the beginning of
memory. All relocatable references in a section assume that the
section resides at that address at execution time.

Virtual Address

The virtual address is used by only a few systems. In WE 32100
Microprocessor object files, the physical address is equivalent to the
virtual address.

5-78

SOFTWARE GENERATION PROGRAMS
Flags

5.4.2 File Header
The file header contains the twenty bytes of information described in Table 5-8. The last
two bytes are flags that may be of use to m321d. The manual page for FILEHDR, found
in 5.6 SGP MANUAL PAGES, gives the exact C language structure for the file header.
The size of optional header information should be used by all referencing programs that
need to seek the beginning of section header table.
Table 5-8.

File Header Contents

Bytes

Contents

Mnemonic

Description

0-1

Unsigned Short

Cmagic

2-3

Unsigned Short

f nscns

4-7

Long Int

f timdat

8-11

Long Int

Csymptr

Long Int
Unsigned Short
Unsigned Short

f nsyms
f opthdr
f flags

Magic number equal to 0560, also
defined by the mnemonic FBOMAGIC.
Number of section headers (equals
the number of sections).
Time and date stamp containing
the number of elapsed seconds since
00:00:00 GMT, January 1, 1970.
File pointer containing the starting
address of the symbol table.
Number of entries in the symbol table.
Number of bytes in the optional header.
Flags (see Table 5-9).

12-15
16-17
18-19

Flags
The last two bytes of the file header are flags that describe the type of the object file. The
WE 32100 Microprocessor version of the COFF has no use for some of these flags, but
keeps them to maintain commonality.
The notation AR16WR in Table 5-9 signifies the architecture of the host machine where
the file was created. The AR stands for architecture, the digits give the number of bits per
word, W signifies left-to-right byte-ordering (most significant bit first), and WR signifies
right-to-left byte-ordering (least significant bit first). The AR32W machines are either
members of the AT&T 3B .Computer family or the "MAXI" version of the UNIX
Operating System that runs on a host IBM Computer.

5-79

SOFfWARE GENERATION PROGRAMS
Standard UNIX System a.out Header

Table 5-9.
Mnemonic
F RELFLG
F_EXC
F
F
F
F

LNNO
LSYMS
MIN MAL
SWABD

F JtR16WR
F AR32WR
F AR32W
F PATCH
F_BM32B

Flag
00001
00002
00004
00010
00020
00100
00200
00400
01000
02000
020000

File Header Flags

Meaning
Relocation information stripped from file.
File is executable (i.e., no unresolved external
references) .
Line numbers stripped from file.
Local symbols stripped from file.
Not applicable to the WE 32100 Microprocessor.
This file has had its bytes swapped (i.e., the bytes
of symbol table name entries have been reversed.)
Created on AR16WR machine (e.g., PDP 11170 Computer).
Created on AR32WR machine (e.g., VAX 111780 Computer).
Created on AR32W machine (e.g., 3B MAXI Computer).
Not applicable to the WE 32100 Microprocessor.
File contains WE 32100 Microprocessor code

Optional Header Information. The template for optional information varies among
different systems that use the COFF. Applications place all systems-dependent
information into this record. General utility programs (e.g., the table access library
functions, the m32size utility, the m32strip utility, etc.) can be made to work properly on
any Common object file by seeking past this record using the size of optional header
information in the file header (bytes 16 and 17).
Standard UNIX System a.out Header
By default, files produced by the link editor always have a standard UNIX Operating
System a.out header in the optional header field. It contains the 28 bytes of information
listed in Table 5-10.

Bytes
0-1
0-3
4-7
8-11
12-15
16-19
20-23
24-27

Table 5-10. Optional Header Contents
Contents
Name
magic
Magic number
vstamp
Version stamp
Size of text (bytes)
tsize
Size of initialized data (bytes)
dsize
Size of uninitialized data (bytes)
bsize
entry
Entry point
text_start
Base address of text
data start Base address of data

Possible values for the UNIX System header magic number are 0407, 0410 and 0413.

5-80

SOFTWARE GENERAnON PROGRAMS
Section Header Table

The following C language struct declaration is currently used for standard UNIX
Operating System a.out file header:
typedef struct aouthdr {
short
magic;
short
vstamp;
long
tsize;
long
long
long
long
long
AOUTHDR;

dsize;
bsize;
entry;
text_start;
data_start;

1* text size in bytes,padded to FW
1*
1*
1*
1*
1*

bdry*1
initialized data" "*1
uninitialized data" "*1
entry pt. *1
base of text used for this file* I
base of data used for this file* I

5.4.3 Section Header Table
Every object file has a section header table that specifies the layout of data within the file.
Each section within an object file also has its own header.
The section header table consists of one entry for every section in the file. Each entry
contains the information in Table 5-11.
Table 5-11.

Section Header Contents

Bytes

Name

Contents

0-7
8-11
12-15
16-19
20-23
24-27
28-31
32-33
34-35
36-39

S name
S"'paddr
S vaddar
S size
S_scnptr
S relptr
SJnnoptr
S nreloc
S nlnno
S_flags

8-character null padded section name
Physical address of section
Virtual address of section
Section size
File pointer to raw data
File pointer to relocation entries
File pointer to line number entries
Number of relocation entries
Number of line number entries
Flags. Only byte 36 is used; bytes
37-39 are pads.

Section sizes are always padded to a multiple of 4 bytes.
File pointers are byte offsets that can be used to directly and exactly locate the start of
data, relocation, or line number entries for the section. They can be readily used with the
UNIX Operating System function fseekC3S).

5-81

SOFTWARE GENERATION PROGRAMS
Flags

Flags
The flag field indicates section types. The flags are defined in Table 5-12.
Table 5-12. Section Types
Flag

Meaning

STYP REG

OxOO

STYP DSECT

OxOl

STYP_NOLOAD

Ox02

STYP_GROUP

Ox04

STYP_PAD

Ox08

STYP COPY

OxlO

STYP TEXT
STYP DATA
STYP BSS

Ox20
Ox40
Ox80

Regular section
(allocated, relocated, loaded)
Dummy section
(not allocated, relocated, not loaded)
Noload section
(allocated, relocated, not loaded)
Grouped section
(formed from input sections)
Padding section
(not allocated, not relocated, loaded)
Copy section
(for a decision function used in updating
fields; not allocated, not relocated, loaded,
relocation and line number entries
processed normally)
Section contains executable text.
Section contains initialized data.
Section contains un initialized data.

Mnemonic

The C language data structure that is used to declare section headers can be found on the
manual page for SCNHDR.H(5L) in 5.6 SGP MANUAL PAGES .

.bss Section Header
The one anomaly in the section header table is the entry for uninitialized data in a .bss
section. A .bss section has a size, symbols that refer to it, and symbols that are defined in
it. At the same time a .bss section has no relocation entries, no line number entries, and no
data. Therefore, a .bss section has an entry in the section header table but occupies no
space in the section area of the file. That is, there are no raw data for .bss sections in the
area of the COFF immediately following the section headers. In this case, the number of
relocation and line number entries, as well as all file pointers in a .bss section header, are
zero.

5.4.4 Sections
Figure 5-6 shows that section headers are followed by the appropriate number of bytes of
text or data. The raw data for each section begins on a full word boundary in the file.

5-82

SOFTWARE GENERATION PROGRAMS
Relocation Information

Files produced by the compiler and the assembler always contain three sections, .text,
.data, and .bss. The .text section contains the instruction text (e.g., code), the .data section
contains initialized data variables, and the .bss section contains uninitialized data variables.
The link editor SECTIONS directives allow users to describe how input sections are to be
combined, to direct where to place output sections, and to rename output sections. If no
SECTIONS directives are given, each input section appears in an output section of the
same name. For example, if a number of object files from the compiler are linked, each
containing the three sections .text, .data, and .bss, the output object file will also contain
three sections, .text, .data, and .bss.

5.4.5 Relocation Information
Object files have one relocation entry for each relocatable reference in the text or data.
The relocation information consists of entries with the following lO-byte format:
VIRTUAL ADDRESS

4 BYTES

SYMBOL TABLE INDEX

4 BYTES

RELOCATION TYPE

2 BYTES

The first 4 bytes of the entry is the virtual address of the text or data. The next 4 byte
field, counted from 0, indexes the symbol table entry being referenced. The last 2 bytes
indicate the type of relocation to be applied.
The C language data structure that is used to declare relocation information can be found
on the manual page for RELOC in 5.6 SGP MANUAL PAGES.
As the link editor reads each input section and performs relocation, the relocation entries
are read. Relocation entries direct how references found within the input section are
treated.
Relocation types currently recognized are:
R ABS

The reference is absolute and no relocation is needed. The entry is ignored.

R DIR32

The entry is a direct, 32-bit reference to the virtual address of the symbol.

R_DIR32S The entry is a direct, 32-bit reference to the virtual address of the symbol,
with the 32-bit value stored in reverse order in the object file.
The m32cc compiler and m32as assembler automatically generate relocation entries, which
are automatically used by the link editor. The -r link editor option retains relocation
entries in an object file. The -a link editor option is used to remove relocation entries
from an object file.

5-83

SOFTWARE GENERATION PROGRAMS
Line Numbers

5.4.6 Line Numbers
The m32cc compiler generates an entry in the object file for every C language source line
where a breakpoint can be inserted. Users can then reference line numbers when using the
appropriate debugger. All line numbers in a section are grouped by function, as shown
below.
SYMBOL INDEX
PHYSICAL ADDRESS
PHYSICAL ADDRESS

0
LINE NUMBER
LINE NUMBER

SYMBOL INDEX
PHYSICAL ADDRESS
PHYSICAL ADDRESS

0
LINE NUMBER
LINE NUMBER

The first entry in a function grouping has line number zero, and has an index into the
symbol table for the entry containing the function name in place of the physical address.
Subsequent entries will have actual line numbers and addresses of the text corresponding to
the line numbers. The line number entries appear in increasing order of address.
The C language data structure that is used to declare line numbers can be found on the
manual page for LINENUM in 5.6 SGP MANUAL PAGES.

5.4.7 Symbol Table
The ordering of symbols in the symbol table determines the scope of the symbols. The
order of symbols in the symbol table is, therefore, very important because of the symbolic
debugging requirements for the SGP. Symbols appear in the sequence shown on Figure
5-7.
The word STATICS on Figure 5-7 refers to symbols defined in the C language storage
class static outside any function. The symbol table consists of at least one fixed-length
entry per symbol, with some symbols followed by an auxiliary entry of the same size. The
entry for each symbol is a structure that holds the value, the type and other information.

Special Symbols
The symbol table contains some special symbols that are created by the compiler,
assembler, link editor, or utilities. These symbols are listed in Table 5-13.
When a structure, union, or enumeration has no tag name (a legitimate C language
syntax) the symbol table must create a name. The name chosen by the symbol table is
.xfake, where x is an integer. If there are 3 unnamed structures, unions, or enumerations
in the source; their tag names will be .Ofake, .1fake, and .2fake.

5-84

SOFTWARE GENERATION PROGRAMS
Special Symbols

FILE NAME 1
FUNCTION 1
LOCAL SYMBOLS FOR FUNCTION 1
FUNCTION 2
LOCAL SYMBOLS FOR FUNCTION 2

••
•
STATICS

••
•
FILE NAME 2
FUNCTION 1
LOCAL SYMBOLS FOR FUNCTION 1

•••
STATICS

••
•

DEFINED GLOBAL SYMBOLS
UNDEFINED GLOBAL SYMBOLS

Figure 5-7.

COFF Symbol Table

Table 5-13. Special Symbols in the Symbol Table
Symbol
.fiIe

Meaning

.text
.data
.bss
.bb
.eb

File name
Address of .text section
Address of .data section
Address of .bss section
Address of start of inner block
Address of end of inner block

.bf
.ef

Address of start of function
Address of end of function

.target
.xfake
.eos
.etext

Pointer to the function returned structure or union .
Dummy tag name for structure, union, or enumeration .
End of members of structure, union, or enumeration .
Next available address after the end of the .text section .
Next available address after the end of the .data section .
Next available address after the end of the .bss section .

.edata
.end

5-85

SOFTWARE GENERATION PROGRAMS
Special Symbols

Six of these special symbols occur in pairs. The .bb and .eb symbols indicate the
boundaries of inner blocks; a .bf and .ef pair brackets each function; and a .xfake and .eos
pair names and defines the limit of structures, unions, and enumerations that were not
named. The .eos symbol also appears after named structures, unions, and enumerations.
Each of the special symbols has different information stored in the symbol table entry as
well as in the auxiliary entry.
Inner Blocks. The C language defines a block as a compound statement that begins and
ends with braces ( { and} ). An inner block is a block that occurs within a function
(which is also a block).
For each inner block that has local symbols defined, a special symbol .bb is put in the
symbol table immediately before the first local symbol of that block. Also a special symbol
.eb is put in the symbol table immediately after the last local symbol of that block. The
sequence is:

.bb
LOCAL SYMBOLS
FOR THAT BLOCK
.eb

5-86

SOFTWARE GENERATION PROGRAMS
Special Symbols

Because inner blocks can be nested by several levels, nested inner blocks may have the
following sequence:

.bb FOR BLOCK 1
LOCAL SYMBOLS
FOR BLOCK 1
.bb FOR BLOCK 2
LOCAL SYMBOLS
FOR BLOCK 2
.eb FOR BLOCK 2

.bb FOR BLOCK m
LOCAL SYMBOLS
FORBLOCKm
.bb FOR BLOCK ml
LOCAL SYMBOL
FOR BLOCK ml

.bb FOR BLOCK mn
LOCAL SYMBOLS
FOR BLOCKmn
.eb FOR BLOCK mn

.eb FOR BLOCK ml
.eb FOR BLOCK m

.eb FOR BLOCK 1

5-87

SOFTWARE GENERATION PROGRAMS
Special Symbols

For example: given the following code:

/* Begin Block 1 */
int i;
char c;

/* Begin Block 2 */
long a;

/* Begin Block 3 */
int x;

/* End Block 3 */
/* End Block 2 */
/* Begin Block 4 */
long i;

/* End Block 4 */
/* End Block 1 */

The symbol table would look like:
.bb for Block 1
i
c
.bb for Block 2
a
.bb for Block 3
x
.eb for Block 3
.eb for Block 2
.bb for Block 4
i
.eb for Block 4
.eb for Block 1

5-88

SOFTWARE GENERATION PROGRAMS
Symbol Table Entries

Symbols for Functions. For each function, a special symbol .bf is put between the function
name and the first local symbol of the function in the symbol table. Also a special symbol
.ef is put immediately after the last local symbol of the function in the symbol table. The
sequence is:

FUNCTION NAME
.bf
LOCAL SYMBOLS
.ef

If the return value of the function is a structure or union, the special .target symbol is put
between the function name and the .bf. The sequence becomes:

FUNCTION NAME
.target
.bf
LOCAL SYMBOLS
.ef

The m32cc compiler creates .target to store the function·returned structure or union. The
.target symbol is an automatic variable with pointer type. Its stack offset (value field in
the symbol table entry) is always zero.
Symbol Table Entries
All symbols, regardless of storage class and type, have the same format for their entries in
the symbol table. The symbol table entries contain the 18 bytes of information shown in
Table 5-14. Indices for symbol table entries begin at zero and count upward. Each
auxiliary entry also counts as one symbol.
Table 5-14. Symbol Table Entry Format
Bytes
0-7
8-11
12-13
14-15
16
17

Mnemonic
n name
n
n
n
n
n

value
scnum
type
sci ass
numaux

Contents
These 8 bytes contain either the name or a
pointer to the name of the symbol
Value (depends on storage class)
Section number
Type specification (basic and derived types)
Storage class
Number of auxiliary entries

5-89

SOFTWARE GENERATION PROGRAMS
Symbol Table Entries

Symbol Name Field (n_name). The first eight bytes in the symbol table entry are a union
of a character array and two long integers. These eight bytes are described in Table 5-15.
If the symbol name is eight characters or less, the (null-padded) symbol name will be
stored in n_name field. If the symbol name is longer than eight characters, then the entire
symbol name will be stored in the string table. In this case, the eight bytes will contain
two long integers, the first of which will be zero, and the second will be the offset (relative
to the beginning of the string table) of the name in the string table. Since there can be no
symbols with a null name, the zeroes in the first four bytes serve to distinguish a symbol
table entry with an offset from one with a name in the first eight bytes.
Table 5-15. n_name Entry Formats
Bytes

Mnemonic

Description

0-7
0-3

n name

Eight character null-padded symbol name.

n zeroes

Zero in this field indicates the symbol name
is in the string table.

4-7

n_offset

Offset of the symbol name in the string table.

Some special symbols are created by the compiler and link editor, as discussed in Special
Symbols. The names of special symbols usually start with a dot (.); e.g., .fiIe, .5fake, .bb.
Symbol Value Field and Storage Classes (o_value). The meaning of the value of a symbol
depends on its storage class. Table 5-16 lists storage classes, values, and meanings.

5-90

SOFTWARE GENERATION PROGRAMS
Symbol Table Entries

Table 5-16. Symbol Values

Storage Class

Mnemonic

Automatic variable
External symbol
Static
Register variable
Label

C_AUTO
C_EXT
C STAT
C_REG
C LABEL

Member of structure
Function argument
Structure tag
Member of union
Union tag

CMOS
C_ARG
C_STRTAG
C MOU
C UN TAG

Type definition '
Enumeration tag
Member of enumeration
Register parameter
Bit field

C TPDEF
C ENTAG
C MOE
C_REGPARM
C FIELD

Beginning and end of block
Beginning and end of function
End of structure
File name
Duplicated tag

C_BLOCK
C-FCN
C_EOS
C_FILE
C ALIAS

Storage
Class
Value
1

2
3
4
6

8
9

10
11
12
13
15
16
17

18
100
101
102
103
105

Meaning of Value Field
Stack offset (bytes)
Relocatable address
Relocatable address
Register number
Relocatable address
Offset (bytes)
Stack offset
o (always zero)
Offset (bytes)

0
0
0
Enumeration value
Register number
Bit displacement
Relocatable address
Relocatable address
Size
(See Note)
Tag index

Note: If the current symbol is the last symbol that has storage class C_FILE (.file
symbol), its value is the symbol table entry index of the first global symboL Otherwise the
symbol value equals the symbol table entry index of the next .file symbol (j.e., the .file
entries form a one-way linked list in the symbol table).
Relocatable symbols have a value equal to the virtual address of that symboL When the
section is relocated by the link editor, the value of these symbols changes.
The m32cprs symbol table compressor utility creates the C_ALIAS mnemonic. This
utility, which is described in 5.5 UTILITIES AND LIBRARY ROUTINES, removes
duplicated structure, union, and enumeration definitions and puts ALIAS entries in their
places.
There are also some dummy storage classes defined in the header file. They are used only
internally by the compiler and the assembler. These storage classes are listed in Table
5-17.

5-91

SOFTWARE GENERATION PROGRAMS
Symbol Table Entries

Table 5-17. Dummy Storage Classes
Storage Class

Mnemonic

Physical end of function
External definition
Undefined label
Uninitialized static
Used only by utility programs

C EFCN
C EXTDEF
C_ULABEL
C_USTATIC
CLINE

Value
-1
5
7
14
104

Table 5-18 lists special symbols that are restricted to certain storage classes.
Table 5-18. Restricted Special Symbols
Special Symbol
.file
.bb
.eb
.bf
.ef
.target
.xfake
.eos
.text
.data
.bss

Storage Class
C FILE
C_BLOCK
C BLOCK
C FCN
C FCN
C_AUTO
C _STRT AG,C_UNTAG,C_ENTAG
C EOS
C STAT
C STAT
C STAT

Some storage classes are used only for certain special symbols. Table 5-19 summarizes
these storage classes.
Table 5-19. Restricted Storage Classes
Storage Class
C_BLOCK
C FCN
C ESO
C FILE

5-92

Special Symbol
.bb,.eb
.bf,.ef
.eos
.file

SOFTWARE GENERATION PROGRAMS
Symbol Table Entries

Section Number Field (n_scnum). Table 5-20 lists the section numbers and their meanings.
Table 5-20. Section Numbers
Section Number

-2
-1
0
1-077767

Mnemonic
N_DEBUG
N ARB
N_UNDEF
N SCNUM

Meaning
Special symbolic debugging symbol
Absolute symbol
Undefined external symbol
Section number where symbol was defined

A special section number (-2) marks symbolic debugging symbols, including
structure/union/enumeration tag names, typedefs, and the name of the file. A section
number of -1 indicates that the symbol has a value, but is not relocatable. Examples of
absolute-valued symbols include automatic and register variables, function arguments, and
.eos symbols. If the SECTIONS directive-capability of the link editor is not used, .text,
.data, and .bss symbols default to section numbers 1,2, and 3, respectively.
A section number of zero indicates a relocatable external symbol that is not defined in the
current file, with one exception: a multiply-defined external symbol (i.e., FORTRAN
Common, or an uninitialized variable defined external to a function in C). In the symbol
table of each file where the symbol is defined, the section number of the symbol will be
zero and the value of the symbol will be a positive number giving the size of the symbol.
When the files are combined, the link editor will combine all the input symbols into one
symbol with the section number of the .bss section (or of the .data section, if one of the
input symbols is initialized). The maximum size of all the input symbols with the same
name will be used to allocate space for the symbol and the value will become the address of
the symbol. This is the only case where a symbol may have a section number of zero and a
non-zero value.
Symbols having certain storage classes are also restricted to certain section numbers.
Table 5-21 lists these storage classes.

5-93

SOFfWARE GENERATION PROGRAMS
Symbol Table Entries

Table 5-21. Restricted Storage Classes
Storage Class
C_AUTO
C_EXT
C_STAT
C_REG
C LABEL
C_MOS
C_ARG
C_STRTAG
C_MOU
C UNTAG
C_TPDEF
C_ENTAG
C_MOE
C_REGPARM
C FIELD
C_BLOCK
C]CN
C_EOS
C]ILE
C_ALIAS

Section Number
NABS
N_ABS, N_UNDEF, N_SCNUM
N_SCNUM
N_ABS
N UNDEF, N SCNUM
N_ABS
N_ABS
N_DEBUG
N_ABS
N DEBUG
N_DEBUG
N_DEBUG
N_ABS
N_ABS
NABS
N_SCNUM
N_SCNUM
N_ABS
N_DEBUG
N_DEBUG

Type Field  is computed address 40). These addresses appear in the operand field of
control transfer instructions following a relative displacement. The computed address
is the sum of the relative displacement and the address of the instruction currently
being disassembled.

Note that items 1 and 2 occur only if the information exists in the object file (e.g., the
code was compiled by m32cc with the -g option and the information was not removed by a
utility or link editor option).

5-108

SOFTWARE GENERATION PROGRAMS
m32dis

Table 5-36. m32dis Command Line Options
Option
-d

Argument

-da

section

-F

function

-I

string

-0

None

-t

section
None

-v

section

Description
Disassembles the named section as data, and prints
the offset of the data from the beginning of the
section.
Disassembles the named section as data, and prints
the actual address of the data.
Disassembles single named functions in each object
file that is specified on the command line.
Disassembles the library file specified by string.
For example, one would issue the command line
m32dis -I x -I z to disassemble the libraries Iibx.a
and Iibz.a. The libraries are assumed to be in the
SGP lib directory.
Prints numbers in octal; without this option, default
is hexadecimal.
Disassembles the named section as text.
Prints the version number of the disassembler being
executed.

Note: Arguments are appended to options with no embedded blanks,
except for the -I option.
The -d option causes the named section of the object file to be disassembled as a data
section. The object code and its address relative to the beginning of the section are listed.
m32dis makes no attempt to determine the corresponding assembly language statement.
Addresses relative to the beginning of the named section are printed on the left side; object
code bytes are printed on the right side, eight bytes per line.
The -da option causes disassembly of the named section of the object file as a data section.
The object code and its absolute addresses are listed. No attempt is made to determine the
corresponding assembly language statement.
If the -F option is used, only those named functions from each file will be disassembled.

The -t option causes the named section of the object file to be disassembled as a text
section. The listing consists of the object code, its machine address, and the assembly
language statements that produced the code. For example, if the command line is
m32dis -t section files
then the bytes of that section of object code are assumed to be opcode and operand
encodings. The opcodes are looked up in the opcode disassembly table, and the operands
are disassembled and printed.

5-109

SOFTWARE GENERATION PROGRAMS
m32dis

The following is a list of error messages commonly encountered while executing the
disassembler:
• m32dis: : CANNOT OPEN:
Means the input file cannot be read.
• m32dis: : BAD MAGIC NUMBER
The input file is not a processor object file.
• m32dis:  CANT FIND SECTION 

An unknown section has been specified by the -t or -d option.
• m32dis: : CANT FIND SECTION HEADER 

The input file is not a processor object file or the file was not properly converted
using m32conv.
• m32dis: BAD FLAG 
An unrecognized option has been specified.
• m32dis: PREMATURE EOF
• m32dis: QUIRK--DATA SECfION HAS LINE NUMBER ENTRIES
If the disassembler cannot find an opcode in the disassembler opcode lookup table, the
message

ERROR UNKNOWN OPCODE
is printed on the same line as the bad object code and the disassembler then attempts to
resynchronize itself. There are three cases determining how the disassembler
resynchronizes.
1. If the file has been stripped of line number information as well as the symbol table,
the following message is printed:
NO LINE NUMBER ENTRIES EXIST
NO SYMBOL TABLE EXISTS
FOLLOWING DISASSEMBLY MAYBE OUT OF SYNC
The disassembler will then continue with the two bytes immediately following the bad
opcode.
2.

If the file has been stripped of line number entries but has a symbol table, the
following message is printed:
NO LINE NUMBER INFORMATION EXISTS
DUMP TO NEXT FUNCTION OR SECTION END
IN ATTEMPT TO RESYNCHRONIZE

5-110

SOFTWARE GENERATION PROGRAMS
m32dump

The disassembler then dumps bytes of object code until the next function or the
section end (whichever comes first) is reached. At this point, the disassembler prints
out:
DISASSEMBLER RESYNCHRONIZED
3.

The file has line number entries. The disassembler then dumps bytes of object code
until it reaches the next line where a breakpoint can be inserted. At that point the
disassembler prints:
DISASSEMBLER RESYNCHRONIZED

m32dump
The m32dump utility allows examination of an object file by listing the contents of the file
on standard output. The dump utility is normally used to look at different parts of an
object file, with the parts being selected by options. m32dump attempts to format the
information in a meaningful way by printing certain information in ASCII, hexadecimal,
octal, or decimal as appropriate. The input file is unchanged after execution of m32dump,
and no new files are created. m32dump accepts as input both object files and archive
libraries of object files.
The options for m32dump are listed in Table 5-37. The -a, -c, -f, -g, -h, -I, -0, -p,
-r, -s, -t, -u, and -z options specify which parts of an object file are to be dumped.
These are the basic options, and can be used independently; others are modifying options.
The options -d, +d, -n, -t (used with an argument), and -z (used with a numerical
argument) are used in combination with other options to limit the range and type of
information that is to be printed. The -v option is used to modify all but the -0 and -s
options. The -v option causes m32dump to interpret the information and print symbols
instead of numbers; e.g., static instead of Ox03. The -p and - 0 options control the
printing of header information.
Blanks separating an option and its modifier are optional. The comma separating the
name from the number modifying the -z option may be replaced with a blank.
A simple example of m32dump is the command line
m32dump -t m32a.out
which would display the symbol table from the file m32a.out. The command line
m32dump -tv m32a.out
displays the symbol table from the file m32a.out in symbolic form. The command line
m32dump

-f -h

-r -t 3 +t 10 test.o > testdump

lists the file and section headers, the relocation information, and the symbol table entries
three through ten for the object file tesLo; the command also places the output in the file
testdump.

5-111

SOFTWARE GENERATION PROGRAMS
m32dump

Table 5·37. m32dump Command Line Options
Option
-a

None

-c
-d

None
number

+d

number

-f
-g

None
None

-h
-I
-n

None
None
name

-0

-p
-r
-s
-t
-t

None
None
None
None
None
index

+t

index

-u
-z
-z

None
None
name
name, number

+z

number

-v

5-112

Argument

Description
Dump the archive header of each member of each input
archive file.
Dump the string table.
Dump the section number given or dump the range
of sections beginning with the given number and ending
either at the last section or at the number specified
by +d.
Dump only those sections having section numbers less
than number. Begin either with the first section or
with the section specified by the -d option.
Dump each file header.
Dump the global symbols in the symbol table of a
UNIX System release 6.0 archive file.
Dump all section headers.
Dump line number information.
Dump only the information pertaining to the named entity.
This option is used with -h, -s, -r, -I, and -to
Dump each optional header.
Suppress printing of the headers.
Dump relocation information.
Dump section contents.
Dump symbol table entries.
Dump only the indexed symbol table entry. -t used
with the +t option specifies a range of symbol table
entries.
Dump symbol table entries in the range ending with
the indexed entry. The range begins at the first symbol
table entry or at the entry specified by the -t
option.
Underline the name of the file emphasis.
Print symbolic, rather than numeric, information.
Dump line number entries for the named function.
Dump line number entry or range of line numbers
starting at number for the named function.
Dump line numbers starting at either the function
name or number specified by -z up to number
specified by +z.

SOFTWARE GENERATION PROGRAMS
m321ist

The more common error messages produced by m32dump are:
o usage: m32dump !flagsl file .•.
Occurs when the object file to be dumped is not named.
• m32object: bad magic file. out
Occurs when the file file.out is not a WE 32100 Microprocessor object file.
• m32object: cannot open file. out
Means file. out cannot be read.
o m32dump: unknown option OPTION.
m321ist
The m321ist utility lists C source files with line number information attached. m32list uses
the object file corresponding to the input C language source file to determine the lines
where breakpoints can be set. Generally breakpoints can be set at each executable
statement that begins a new line of source code.
To invoke the processor list utility, use the command
m32list [-VII-bl source {source ...][objectJ
where the square brackets denote optional entries, source is the source file name, and
object is the object file name. If several C source files were used to create the object file,
then a list of source files should be input to m321ist. The last name in the list of files is
considered to be the name of the object file. The default object file, m32a.out, is used
when no object file appears on the command line. The input object file MUST have
symbolic debugging symbols for m32list to work.
Line numbers are printed for each compiler-generated line where a breakpoint can be
inserted. Line numbering begins anew for each C language function. Line number 1
always indicates the line containing the left curly brace (0 that begins a function body.
Line numbers are also printed for inner block redeclarations of local variables so that those
variables can be distinguished by the symbolic debugger.
The -b option suppresses the printing of headings.
The -V option prints the version of m32list being executed.
Object files that have no line numbers cause an error message to be printed. Because
m321ist does not use the C preprocessor, it may not recognize function definitions whose
syntax has been distorted by the use of C preprocessor macro substitutions.
Some errors commonly encountered when using m32list are:
• usage: m32list sourcefile [sourcefile... llobject filel
Caused when no object file or no source file is specified.
• m32list: name: cannot open
Caused when an input file name cannot be read.

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SOFTWARE GENERATION PROGRAMS
m3210rder

• m32list: unknown option option
m32lorder
The m3210rder library orders object file libraries for the link editor, m321d. If the archive
members are arranged by m3210rder so that every symbol and function is defined after it is
referenced, m321d will make fewer passes over the library and will therefore be more
efficient. The SGP command line for library ordering works the same way as its UNIX
System counterpart. To invoke the library ordering utility, use the command line
m3210rder files
where files indicates the input of one or more object or library archive files. The
m3210rder output is a list of pairs of object file names, where the first file of the pair
contains references to external identifiers defined in the second. Therefore, the second
member of the pair must appear after the first to be properly loaded.
The names of input object files must end with .0, even when contained in library archives.
Files with names not adhering to this rule have their global symbols and references
attributed to some other file, and nonsense results.
The m3210rder output may be processed by the UNIX System tsort command to find an
ordering of a library suitable for one-pass access by the m32ld link editor. The following
example shows the use of tsort, along with m32ar, to build a new library from all existing
files with names ending in .0. The archive library is named /ibx.a both before and after
the operation:
m32ar cr Iibx.a 'm3210rder *.0 I tsort'
m32nm
The m32nm name list utility displays the symbol table for each processor object file that is
given as input. The input may be a relocatable or an absolute processor object file; or it
may be an archive library of relocatable or absolute object files.
For each symbol in the table, the following information is printed:

5-114

Name

the name of the symbol.

Value

the symbol value expressed as an offset or an address depending on storage
class.

Class

the symbol storage class.

Type

the symbol type and derived type. If the symbol is an instance of a structure
or of a union, then the structure or union tag is given following the type (e.g.,
struct-person where person is the structure tag). If the symbol is an array,
then the array dimensions are given following the type (e.g., charfn][mJ).

Size

the symbol size in bytes, if applicable. Special symbols have undefined size.

SOFTWARE GENRATION PROGRAMS
m32nm

Line

the source line number where it is defined, if applicable.

Section

for storage classes static and external, the object file section containing the
symbol.

m32nm does not change the input file and produces no new file. The syntax to invoke the
name list utility is
m32nm options filenames
where options are chosen from Table 5-38 and filenames are the names of the input file(s)
and/ or archive(s).
Table 5-38. m32nm Command Line Options
Option

Description

-e

Prints only static and external symbols.
Produces full output. Redundant symbols Ctext,
.data, and .bss) normally suppressed, are printed.
Sorts the external symbols by name before printing them.
Prints the value and size for each symbol in octal instead
of the normal decimal.
Truncates very long names.
Prints only the undefined symbols.
Sorts external symbols by value before printing them.
Prints the version name of m32nm that is executing.
Prints the value and size in hexadecimal.

-(

-n
-0

-T
-u

-v

-V
-x

The options may be specified in any order, either singly or in combination, and may appear
anywhere on the command line. Therefore, both m32nm name -e -v and m32nm -ve
name print the static and external symbols in name, with the external symbols sorted by
value. If neither the -n nor the -v option is specified, the external symbols are printed in
the order in which they are encountered.
Some common error messages that m32nm produces are:
• usage: m32nm: file: bad magic
Input file is not a WE 32100 Microprocessor object file.
G

m32nm: name: cannot open
Input file cannot be read.

• m32nm: name: bad magic
Input file is not a processor object file.
o

m32nm: name: no symbols
Symbols were stripped from the input file before it was input to m32nm.

• m32nm: unknown option option

5-115

SOFTWARE GENERATION PROGRAMS
m32size

m32size
m32size prints the number of bytes required for each section (e.g., .text,.data, and .bss) of
the input processor object file and the total number of bytes for all three sections. Such
information may be needed for locating sections in memory.
The file input to m32size remains unchanged. The output consists of the name of each
section, followed by its size in bytes, its physical address, and its virtual address. The form
of the command line for m32size is:
m32size (-oll-dll-VI filename[s]
By default, numbers are printed in hexadecimal. The -d option specifies decimal numbers;
the -0 option specifies octal. Version information is printed when the -V option is
specified.
Commonly encountered diagnostics are:
• m32size: filename: cannot open
Occurs when filename cannot be read.
• m32size: filename: bad magic
Occurs when filename is not a WE 32100 Microprocessor object file.
m32strip
The m32strip strip utility removes the symbol table and line number information from
processor object files and archive libraries, thus saving space. The effect of m32strip is the
same as the -s option of m32ld. After a file has been stripped, no symbolic debugging
access is available for that file. This command should be run only on production versions
of object files that have been debugged and tested.
The command line used to strip symbol table and line numbers is
m32strip (-III-xll-rll-VI name ...
where name is the name of a processor object file or archive library. Any number of
names may be specified. If name is an archive, m32strip removes the local symbols from
each object module in the archive. By deleting these symbols, the size of the archive is
decreased and link-editing performance improves.
The amount of information stripped from the symbol table can be controlled by using
either the -lor the -x options. With the -I option, only line number information is
stripped. Symbol table information remains unchanged. With the -x option, no static or
external symbol information gets stripped. The -V option prints version information.
If there are any relocation entries in the object file and symbol table information is to be
stripped, m32strip terminates without stripping name and prints the error message:

m32strip: name: relocation entries present; cannot strip

5-116

SOFTW ARE GENERAnON PROGRAMS
Use of the Accessing Library

The -r option allows the user to override this warning and force m32strip to strip an object
module even if the module contains relocation information. When the -r option is used,
m32strip will strip only local symbols and line number information. It will retain the
global and static symbols and relocation information needed for link editing.
Other commonly encountered error messages are:
• m32strip: name: cannot open
Occurs when name cannot be read.
• m32strip: name: bad magic
Occurs when name is not a WE 32100 Microprocessor object file.
o

usage: m32strip [-lII-xll-rl file ...
Occurs when no input file was specified.

5.5.2 Accessing Library
A library of object file access routines is available to aid in the development of application
programs. Specific applications may need to examine the contents of an object file from
within a C language program. Although these programs must know the detailed structure
of the parts of the object file that they process, the access routines insulate these calling
programs from detailed knowledge of the overall structure of the object file.
The interface between the calling program and the object file access routines is based on
the defined type LDFILE, defined as struct ldfile, and declared in the header file Idfcn.h.
The primary purpose of this structure is to provide uniform access to both simple object
files and to object files that are members of an archive library.
All library functions except ldopen. ldaopen. ldtbindex, ldgetname, sgetl, and sputl return
either the constant SUCCESS, defined as 1, or FAILURE, defined as O. ldopen and
ldaopen both return pointers to a LDFILE structure, while ldtbindex returns an index to a
symbol table entry. ldgetname returns a character pointer, sgetl returns a long integer,
and sputl does not return a value.

Use of the Accessing Library
To use the object file access functions, a C language program must include at least the
files , "INCDIR/filehdr.h", and "INCDIRndjcn.h", as described on the manual
pages for each function. If the path names present a problem, consult the manual page for
INTRO. Any program that uses the object file access routines must also be loaded with
the access routine library, Hbld.a. This is done by adding -lId on the final link edit line
when compiling a program.
The functions comprising the accessing library can be accessed from assembly language
code by simulating the C calling sequence. This is best accomplished by using the
interface macros described under Macro Processing Facilities, found in 5.2.1 Assembler.
I\n example, the assembly language function getindex, is defined here. This function calls
.he Idtbindex library routine and places the result (a symbol table index) in rOo

5-117

SOFTWARE GENERATION PROGRAMS
Library Functions and Macros

C_PROLOGUE(getindex)
C_CALLOdtbindex,_ISTARG)
movw
%rO,%_RESULT
C RETURN
Note that the movw statement is unnecessary as long as _RESULT is defined as register
zero (this is currently true). Nevertheless, it is good practice to insulate code from
potential changes through this type of statement.
Library Functions and Macros
The object file access functions may be divided into four categories:
1.

Functions that open or close an object file

2.

Functions that read header or symbol table information

3.

Functions that seek to the start of the section, relocation, or line number information
for a particular section

4.

A function to return the index of a particular symbol table entry, ldtbindex.

Additional access to an object file is provided through a set of macros contained in the
library. The operation of these macros parallels the standard input/output file reading and
manipulating functions.
Functions That Open or Close Object Files. The functions ldopen and ldaopen open object
files and archives of object files. These two functions, along with their counterparts for
closing functions (Idclose and ldaclose), are designed to provide uniform access to both
simple object files and object files that are members of archive files. Thus an archive of
processor object files can be processed as if it were a series of simple processor object files.
The function ldopen allocates and initializes the LDFILE structure and returns a pointer to
the LDFILE structure to the calling program. The fields of the LDFILE structure may be
accessed individually through macros defined in the header file ldfcn.h, and contain the
following information:
TYPEOdptr)

the file magic number, used to distinguish between archive members and
simple object files.

IOPTROdptr)

the file pointer returned by the UNIX System function fopen and used
by the standard input/output functions.

OFFSETOdptr)

the file address of the beginning of the object file; the offset is nonzero if
the object file is a member of an archive file.

HEADEROdptr) the file header structure of an object file.
In addition to the #include files, the functions that open or close files must be declared
within the user program. For example,
LDFILE

5-118

*ldopen(), *ldaopen( );

SOFTWARE GENERATION PROGRAMS
Library Functions and Macros

ldopen and ldaopen both take two arguments, filename, a pointer to a character string, and
ldptr, a pointer to an LDFILE structure. If ldptr has the value NULL, ldopen opens the
file filename, allocates and initializes the LDFILE structure, and returns a pointer (to the
structure) to the calling program. If ldptr is valid and if TYPEUdptr) is the archive
magic number, ldopen reinitializes the LDFILE structure for the next member of the
archive file, filename.
ldopen and ldc/ose are designed to work together. ldc/ose returns FAILURE only when
TYPEUdptr) is the archive magic number and there is another file in the archive to be
processed. Only then should ldopen be called with the current value of ldptr. In all other
cases, (particularly when a new file, filename, is opened), ldopen should be called with a
NULL ldptr argument.
The following is a prototype for the use of ldopen and ldc/ose:

/* for each filename to be processed */
ldptr = NULL;
do
(
if «(Jdptr = ldopen(filename, ldptr» != NULL)
(
/*check magic number */
/*process the file */

J
J while (Jdclose(ldptr)

==

FAILURE);

If the value of oldptr is not NULL, ldaopen opens filename anew and allocates and
initializes a new LDFILE structure, copying the TYPE, OFFSET, and HEADER fields
from oldptr. ldaopen returns a pointer to the new LDFILE structure. This new pointer is
independent of the old pointer, oldptr. The two pointers may be used concurrently to read
separate parts of the object file. For example, one pointer may be used to step sequentially
through the relocation information, while the other is used to read indexed symbol table
entries.
Both ldopen and ldaopen open filename for reading. Both functions return NULL if
filename cannot be opened, or if memory for the LDFILE structure cannot be allocated.
Successfully opening a file does not insure that the given file is a processor object file or an
archived object file.
If TYPE([dptr) does not represent an archive file, ldc/ose closes the file and frees the
memory allocated to the LDFILE structure associated with ldptr. If TYPE([dptr) is the
magic number of an archive file, and if there are any more files in the archive, ldc/ose
reinitializes OFFSET([dptr) to the file address of the next archive member and returns
FAILURE. The LDFILE structure is prepared for a subsequent ldopen. In all other cases,
ldclose returns SUCCESS.

5-119

SOFTWARE GENERATION PROGRAMS
Library Functions and Macros

Idaclose closes the file and frees the memory allocated to the LDFILE structure associated
with ldptr regardless of the value of TYPEOdptr). Idaclose always returns SUCCESS.
The function is often used in conjunction with Idaopen.

Functions That Read. Six functions read header or symbol table information. Five return
either SUCCESS or FAILURE, and all must be loaded with the object file access library.
Manual pages for each function are in 5.5 UTILITIES AND LIBRARY ROUTINES.
These functions are:
ldahread

reads the archive header of a member of an archive file;

ldfhread

reads the file header of a processor object file;

Idshread
Idnshread

read an indexed or named section header of a processor object file, respectively;

ldtbread

reads a symbol table entry of a processor object file;

ldgetname

retrieves a symbol name from a symbol table entry or from the string table.

Functions That Seek. Eight functions position an object file at (j.e., seek to) the start of
the section, or the relocation or line number information for a particular section. These
functions point to, and thus identify, the parts of object files. All eight return either
SUCCESS or FAILURE, and must be loaded with the object file access library, as
previously described. Some unusual FAILUREs can occur when using these functions;
consult the manual pages for details. The seeking functions are:
ldohseek

points to the optional file header of an object file;

ldsseek
Idnsseek

point to an indexed or named section of an object file, respectively;

ldrseek
Idrnseek

Idlseek
ldlnseek

Idtbseek

point to the indexed or named relocation entries of a section of an object
file;

point to the indexed or named line number entries of a section of an object
file;
points to the symbol table of an object file.

Function That Returns the Index of a Symbol Table Entry. The function Idtbindex returns
the index of a symbol table entry. This index may be used in subsequent calls to Idtbread.
However, because Idtbindex returns the index of the symbol table entry that begins at the
current position of the object file, calling ldtbindex after a particular symbol table entry
has been read causes the index of the next entry to be returned.
The function Idtbindex fails if there are no symbols in the object file or if the object file is
not positioned at the beginning of a symbol table entry. Note that the first symbol in the
symbol table has an index of zero. Consult the manual page for additional usage details.

5-120

SOFTWARE GENERATION PROGRAMS
Use of the General-Purpose Library

Macros. A set of macros defined in ldfcn.h provides additional access to object files. The
macros parallel the standard input/output file reading and manipulating functions,
translating a reference in the LDFILE structure into a reference to its file descriptor field.
The following macros are provided:
GETC

get a character from a stream (same as C language's getchar);

FGETC

a function to retrieve a character from a stream;

GETW

get a word from a stream;

UNGETC

push a character back onto the input stream;

FGETS

get a string from a stream;

FREAD

buffered binary input/output;

FSEEK

set the position of the next input or output operation on a stream;

FfELL

obtain an offset for FSEEK;

REWIND

reposition a stream;

FEOF

tell when end of file is read on an input stream;

FERROR

tell when an error has occurred in reading or writing a stream;

FILENO

return the file descriptor associated with a stream;

SETBUF

assign buffering to a stream.

STROFFSET

calculates the address of the string table in an object file.

These macros and functions are described on the manual page LDFCN and are essentially
the same as the standard UNIX System input/output library functions.
Note: The macro FSEEK translates into a call to the standard UNIX System input/output
function, fseek(3S). The macro FSEEK should not be used to seek to the end of an
archive file, because the end of an archive file may not be the same as the end of one of its
object file members.

5.5.3 General-Purpose Library
A general-purpose library is available with the SGP to provide the functions of I/O
formatting and conversion, string operations, memory operations, searching, random
number generation, absolute value calculation, encryption, and byte order conversion.
Use of the General-Purpose Library
To use routines from the general-purpose library, a C language program must include the
header files described in the manual pages for the routines used. For instance, the memory
access routines require the header . Any program that uses the generalpurpose routines must be loaded with the general-purpose library, libcm32.a. This is done
when compling the program by adding -lcm32 on the final link edit line.

5-121

SOFTWARE GENERATION PROGRAMS
Routines in the General-Purpose Library

The general-purpose routines can be accessed from assembly language code by simulating
the C calling sequence. This is best accomplished by using the interface macros described
in Macro Processing Facilities (found in 5.2.1 Assembler), and as illustrated in
5.5.2 Accessing Library.

Routines in the General-Purpose Library
The following routines comprise the general-purpose library:
Routine
a641
abs
atoi
atol
bsearch
crypt
ctype
13tol
164a
lfind
Isearch
itol13
memccpy
memchr
memcmp
memcpy
memset
printf
rand
scanf
sprintf
srand
sscanf
strcat
strchr
strcmp
strcpy
strcspn
strlen
strncat
strncmp
strncpy
strpbrk
strrchr
strspn
strtok
strtol
swab

5-122

Summary
convert base-64 ASCII strings to long integers
return integer absolute value
convert string to integer
convert string to long integer
binary search a sorted table
generate DES encryption
table of character types
convert 3-byte integers to long integers
convert long integers to base-64 ASCII strings
linear search and update routine
line search routine
convert long integers to 3-byte integers
memory copy till character
return pointer to first occurrence of character
compares first n characters of arguments
copies n characters from memory
sets first n characters to c
print formatted output
simple random-number generator
reads formatted input
generates formatted strings
initial random-number generator
parses formatted strings
appends string
returns pointer to first occurrence of character c
compares two strings lexigraphically
copies string
returns length of initial string segment not from string2
returns number of characters in string
appends at most n characters
compares at most n characters
copies at most n characters
returns pointer to first occurrence of character from string2
returns pointer to last occurrence of character c
returns length of initial string segment from string2
returns pointer to next token
convert string to long integer
swap bytes

SOFTWARE GENERATION PROGRAMS
SGP Manual Pages

toascii
tolower
to upper

zero out non-ASCII bits
translate to lower case
translate to upper case

Routines Required When Using printf and scanf
There are two routines which reference other functions that are not in the general purpose
library: print! calls putchar, and scan! calls getchar.
If the WE 321EB Microprocessor Evaluation Board is the target on which the user's
programs will be run, then the putchar and getchar routines are provided in the WE 321SE
Evaluation Software Programs. If the user's target is the WE 321AP Microprocessor
Analysis Pod, putchar and getchar are in the WE 321SD Development Software Programs.
Otherwise, to use printf, the user must supply putchar and to use scanf, the user must
supply getchar. putchar accepts a characer and returns an int which is EOF (-1) on
error. getchar returns an int that is EOF (- 1) on end-of-file or error.

sprint! and sscan! do not require any additional routines.

5.6 SGP MANUAL PAGES
The manual pages for the command, subroutines and file formats that comprise the SGP
are contained in this section. They were current at the time of publication and are similar
to those obtained with the man command. Use the man command to obtain the manual
pages that apply to your version of the SGP. Table 5-39 lists the manual pages that are in
this section.

5-123

SOFTWARE GENERATION PROGRAMS
SGP Manual Pages

Table 5-39. SGP Manual Pages
Commands

Subroutines

File Formats

M32AR
M32AS
M32CC
M32CONV
M32CONVERT
M32CPRS
M32DIS
M32DUMP
M32LD
M32LIST
M32LORDER
M32MAN
M32NM
M32SIZE
M32STRIP

A64L
ABS
BSEARCH
CONY
CRYPT
CYTYPE
L3TOL
LDAHREAD
LDCLOSE
LDFHREAD
LDGETNAME
LDLREAD
LSEARCH
LDLSEEK
LDOHSEEK
LDOPEN
LDRSEEK
LDSHREAD
LDSSEEK
LDTBINDEX
LDTBREAD
LDTBSEEK
MEMORY
PRINTF
RAND
SCANF
SPUTL
STRING
STROTL
SWAB

INTRO
FILEHDR
LDFCN
LINENUM.H
M32A.OUT
PATHS
RELOC
SCNHDR
SYMS

Synopsis entries for the command manual pages list the command line. For the
subroutines (libraries) the synopsis lists the information of the library file. The file
formats synopsis lists the file(s) for the file format.

5-124

M32AR

(Command)

M32AR

NAME
m32ar - archive and library maintainer for portable archives
SYNOPSIS
m32ar key [ posname ] afile [name] ...
DESCRIPTION
The m32ar command maintains groups of files combined into a single archive file. Its
main use is to create and update library files as used by the link editor. It can be
used, though, for any similar purpose. The magic string and the file headers used by
m32ar consist of printable ASCII characters. If an archive is composed of printable
files, the entire archive is printable.

When m32ar creates an archive, it creates headers in a format that is portable across
all machines. The portable archive format and structure is described in detail in
m32ar. The archive symbol table is used by the link editor (m32Id) to effect multiple
passes over libraries of object files in an efficient manner. An archive symbol table is
only created and maintained by m32ar when there is at least one object file in the
archive. The archive symbol table is in a specially-named file which is always the first
file in the archive. This file is never mentioned or accessible to the user. Whenever
the m32ar command is used to create or update the contents of such an archive, the
symbol table is rebuilt. The s option described below will force the symbol table to be
rebuilt.

Key is an optional -m, followed by one character from the set drqtpmx, optionally
concatenated with one or more of vuaibc/s. Afile is the archive file. The names are
constituent files in the archive file. The meanings of the key characters are:
d

Delete the named files from the archive file.

r

Replace the named files in the archive file. If the optional character u is used
with r, then only those files with dates of modification later than the archive files
are replaced. If an optional positioning character from the set abi is used, then
the posname argument must be present and specifies that new files are to be
placed after (a) or before (b or i) posname. Otherwise new files are placed at
the end.

q

Quickly append the named files to the end of the archive file. Optional
positioning characters are invalid. The command does not check whether the
added members are already in the archive. Useful only to avoid quadratic
behavior when creating a large archive piece-by-piece.
Print a table of contents of the archive file. If no names are given, all files in
the archive are tabled. If names are given, only those files are tabled.

5-125

(Command)

M32AR

M32AR

p

Print the named files in the archive.

m

Move the named files to the end of the archive. If a positioning character is
present, then the posname argument must be present and, as in r, specifies
where the files are to be moved.

x

Extract the named files. If no names are given, all files in the archive are
extracted. In neither case does x alter the archive file.

v

Give a verbose file-by-file description of the making of a new archive file from
the old archive and the constituent files. When used with t, give a long listing of
all information about the files. When used with x, precede each file with a
name.

c

Suppress the message that is produced by default when file is created.
Place temporary files in the local current working directory, rather than in the
directory specified by the environment variable IMPDIR or in the default
directory \tmp.

s

Force the regeneration of the archive symbol table even if m32ar is not invoked
with a command which will modify the archive contents. This command is
useful to restore the archive symbol table after the m32strip command has been
used on the archive.

FILES
\tmp\ar*

temporaries

SEE ALSO
m32convert, m321d, m32lorder, m32strip, m32a.out
NOTES
This archive format is new to this release. The m32convert command can be used to
change an older archive file into an archive file that is recognized by this m32ar
command.
BUGS
If the same file is mentioned twice in an argument list, it may be put in the archive
twice.

5-126

M32AS

(Command)

M32AS

NAME
m32as - WE 32100 Microprocessor Assembler
SYNOPSIS
m32as [-0 objfilel [-nl [-ml [-Rl [-vl file-name
DESCRIPTION
The m32as command assembles the named file.
The following flags are recognized by the assembler and may be specified in any
order:
-0

objfile
Output of assembly is put in objfile. By default, the output file name is formed
by removing the .s suffix, if there is one, from the input file name and appending
a .0 suffix.

-n Turns off long/short address optimization. By default, address optimization takes
place.
-m Invokes the m4 macro processor. By default, does not invoke m4 on the input to
the assembler.
-R Remove (unlink) the input file after assembly is completed.
-V Causes the version number of the assembler being run to be written on standard
error.
FILES
/usr/tmp/m32as[1-6]XXXXXX temporary files
SEE ALSO
m32Id,m32nm,m32strip, m32a.out.
DIAGNOSTICS
If the input file cannot be read, the assembly terminates with the message "Unable to
open input file". If assembly errors are detected in the input file the following
information is written to standard error: the input file name, line number where the
error occurred in the assembly code, a descriptive message of the problem, and, if the
input file was produced by the C compiler (see m32cc), and the line number in the C
program that generated the erroneous code.

5-127

M32AS

(Command)

M32AS

CAVEATS
If the input file does not contain a .fiIe assembler, then the file name given by the
assembler when an error occurs is one of the temporary files.
If the m4 macro processor (see 5.2.1 Assembler) is used, then m4 keywords cannot be
used as symbols (variables, functions, labels) in the input assembly file, since m4
cannot determine which are assembler symbols and which are real m4 macros.

BUGS
The .align assembler directive is not guaranteed to work in the .text section when
optimization is performed. Arithmetic expressions may have only one forwardreferenced symbol per expression.

5-128

M32CC

(Command)

M32CC

NAME
m32cc - WE 32100 Microprocessor C Compiler
SYNOPSIS
m32cc [-c1 [-pI [-gl [-yl [-01 [-SI [-pI [-EI [-VI [-Dsymboll ••.I-Usymboll
.. ,[Idirl files
DESCRIPTION
The m32cc command is the interface to the C compiler, assembler, and link editor.
Arguments whose names end with .c are taken to be C source programs and those
with .s are taken as assembly programs; they are compiled/assembled, and link edited.
The resulting object and code is left in a file named m32a.out.
The following flags are interpreted by m32cc. See m32ld or m32as for other useful
flags.

-c

Run the preprocessor, compiler, and assembler, and leave the
object code on corresponding files suffixed with .0.

-p

This flag is reserved for invoking a profiler.

-g

Produce additional information needed for the use of sdb.

-y limit

Set limit on percent growth per file due to in-line expansion.
Values for limit are: u, allows unlimited growth; integer >0
allows indicated percent growth; s, suppresses in-line expansion.

-0

Invoke an object-code optimizer. The optimizer will move,
modify, merge and delete code, so symbolic debugging with line
numbers could be confusing when the optimizer is used.

-S

Compile the named C programs, and leave the assemblerlanguage output on corresponding files suffixed .5.

-p

Run only the macro preprocessor on the named C programs,
and leave the output on corresponding files suffixed .i.

-E

Same as the -p option except the output is directed to the
standard output. This allows the preprocessor to be used as a
filter for any other compiler.

-V

Print the version of the compiler, optimizer, assembler or linkeditor that is invoked.

-D

Define symbol to the preprocessor. This mechanism is useful
with the conditional statements in the preprocessor by allowing
symbols to be defined external to the source file.

5-129

M32CC

(Command)

M32CC

-u

Undefine symbol to the preprocessor.

-I

Change the algorithm for searching for #include files whose
names do not begin with I to look in dir before looking into the
directions on the standard list. Thus, #include files whose
names are enclosed in " "will be searched for first in the
directory of the file argument, then in directories named in -I
options, and last in directories on a standard list. For #include
files whose names are enclosed in < >, the directory of the file
argument is not searched.

-We, arg1 [,arg2 .. .1

Hand off the argument[s] m32argn to pass e where e is one of
[p02all indicating preprocessor, compiler, optimizer, assembler,
and link editor, respectively. For example, -Wa, -m invokes
the m4 macro preprocessor on the input to the assembler.

-B string

Construct pathnames for substitute preprocessor, compiler,
assembler, and link editor passes by concatenating string with
the suffixes cpp, comp, optim, m32as, m321d.

-t [p02all

Find only the designated preprocessor, compiler, assembler, and
link edit passes in the file whose names are constructed by a
-B option. " "is equivalent to -tp02.

Other arguments are taken to be either link-editor flag arguments, or C compatible
object programs, typically produced by an earlier m32ee run, or perhaps libraries of C
compatible routines. These programs, together with the results of any compilations
specified, are link-edited (in the order given) to produce an executable program with
name m32a.out unless the -0 option of the link-editor is used.

FILES
File
file.c
file.o
file.s
m32a.out
lusrltmp/m32?
LIBDIR/comp
LIBDIR/optim
LIBDIRllibc.a

Description
input file
object file
assembly language file
link-edited output
temporary
compiler
optimizer
WE 32100 Microprocessor Library

SEE ALSO
m32as, m32dis, m321d, m321ist.

5-130

M32CC

(Command)

M32CC

DIAGNOSTICS
The diagnostics produced by the C compiler are sometimes cryptic. Occasional
messages may be produced by the assembler or link-editor.
NOTES
By default, the return value from a C program is completely random. The only two
guaranteed ways to return a specific value is to explicitly call exit (2) or to leave the
function mainO with a "return expression;" construct.

5-131

M32CONV

(Command)

M32CONV

NAME
m32conv - WE 32100 Microprocessor SGP Object File Converter
SYNOPSIS
m32conv [-][ -s1 [-al-01-p1 -t target files
DESCRIPTION
The m32conv command converts object files from their current format to the format of
the target machine. The converted file is written to file.v.
Command line options are:
indicates files should be read from stdin.
-a

If the input file is an archive, produce the output file in the UNIX System
V Release 2 portable archive format.

-0

If the input file is an archive, produce the output file in the old (pre
UNIX System Release 5.0) archive format.

-p

If the input file is an archive, produce the output file in the UNIX System
V Release random access archive format. This is the default.

-s

causes m32conv to function exactly as the UNIX System swab command.
This is useful only for 3B20 object files which are to be "swab-dumped"
from a DEC Computer to a 3B20 Computer.

-t target

indicates the machine (target) to which the object file is being shipped.
This may be another host or a target machine. Legal values for target
are: pdp, vax, ibm, iSO, xS6, b16, n3b and m32.

m32conv can be used to convert all object files in common object file format, not only
object files. it can be used on either the source (sending) or target (receiving)
machine.
m32conv is meant to ease the problems created by a multihost cross-compilation
development environment. m32conv is best used within a procedure for shipping object
files from one machine to another.
m32conv will recognize and produce archive files in three formats: the pre UNIX
System Release 5.0 format, the 5.0 random access format, and the System V Release
2 portable ASCII format.
EXAMPLE
*ship object files from vax to ibm
$echo *.outlm32conv -t ibm -$OFC/foo.o
$uucp *.v my370nrjel

5-132

M32CONV

(Command)

M32CONV

DIAGNOSTICS
All intended to be self-explanatory. Fatal diagnostics on the command lines cause
termination. Fatal diagnostics on an input file cause the program to continue to the
next input file.
BUGS
Special applications must compile m32conv differently if it is to convert special object
files, e.g., products of Idp, correctly. m32conv will not convert archives from one
format to another if both the source and target machines have the same byte ordering.
The UNIX System tool m32convert should be used for this purpose.

5-133

M32CONVERT

(Command)

M32CONVERT

NAME
m32convert - convert object and archive files to common formats
SYNOPSIS
m32convert {-51 infile outfile
DESCRIPTION
m32convert transforms input infile to output outfile. Infile must be different from
outfile. The -5 option causes m32convert to work exactly as it did for UNIX System
Release 5.0. Infile may be anyone of the following:

1.

a pre UNIX System Release VAX Computer object file or link-edited (a.out)
module (only with the -5 option).

2.

a pre UNIX System Release VAX Computer archive of object files or link-edited
(a.out) modules (only with the -5 option).

3.

a pre UNIX System Release 3B20S Computer archive of object files or linkedited (a.out) modules (only with the -5 option), or

4.

a UNIX System Release 5.0 VAX Computer or 3B20S Computer archive file
(without the -5 option).

m32convert will transform infile to one of the following (respectively):
1.

an equivalent UNIX System Release 5.0 VAX Computer object file or link-edited
(a.out) module (with the -5 option).

2.

an equivalent UNIX System Release 5.0 VAX Computer archive of equivalent
object files or link-edited (a.out) modules (with the -5 option).

3.

an equivalent UNIX System Release 5.0 archive of unaltered 3B20S Computer
object files or link-edited (a.out) modules (with the -5 option), and

4.

an equivalent VAX Computer or 3B20S Computer UNIX System Release 5.0
portable archive containing unaltered members (without the -5 option).

All other types of input to the m32convert command will be passed unmodified from
the input file to the output file (along with appropriate warning messages). When
transforming archive files with the -5 option, the m32convert command will inform
the user that the archive symbol table has been deleted. To generate an archive
symbol table, this archive file must be transformed again by m32convert without the
-5 option to create a UNIX System Release 5.0 archive file. Then the archive symbol
table may be created by executing the m32ar command with the ts option. If a UNIX
System Release 5.0 archive with an archive symbol table is being transformed, the
archive symbol table will automatically be converted.

5-134

M32CONVERT

(Command)

M32CONVERT

FILES

/tmp/conv*
SEE ALSO

m32ar
m32a.out,m32ar

5-135

M32CPRS

(Command)

M32CPRS

NAME
m32cprs - Compress an Assembler Object File
SYNOPSIS
m32cprs [-pv1 infile outfile
DESCRIPTION
The m32cprs command reduces the size of an assembler object file, infile, by removing
duplicate structure and union descriptors. The reduced file, outfile, is produced as
output.
The options are:
-p Print statistical messages including: total number of tags, total duplicate tags,
and total reduction of infile.
-v Print verbose error messages if error condition occurs.

EXAMPLE
m32cprs m32a.out sm3b
SEE ALSO
m32strip.

5-136

M32DIS

(Command)

M32DIS

NAME
m32dis - WE 32100 Microprocessor Disassembler
SYNOPSIS
m32dis [-o][-V][-L][-d secl [-da sec][-F function][-t sec] [-I string] files
DESCRIPTION
The m32dis command produces an assembly language listing of each of its object file
arguments. The listing includes assembly statements and the binary code that
produced those statements.
The following options are interpreted by the disassembler and may be specified in any
order.
-0

Print numbers in octal. Default is hexadecimal.

-v

Version number of the disassembler is written to standard error.

-L

Invokes a lookup of C source labels in the symbol table for subsequent
printing.

-d sec

Disassembles the named section as data, printing the offset of the data
from the beginning of the section.

-da sec

Disassembles the named section as data, printing the actual address of
the data.

-F function Disassembles single named functions in each object file that is specified

on the command line.
-t sec

Disassembles the named section as text.

-I string

Disassemble the library file specified as string. For example, one would
issue the command m32dis -I x -Iz to disassemble libx.a and libz.a. All
libraries are assumed to be in lusr/m321lib.

If the -d, -da or -t options are specified, only those named sections from each usersupplied file name are disassembled. Otherwise, all sections containing text are
disassembled. If the -F option is specified, only those named functions from each
user-supplied filename will be disassembled.

On output, a number enclosed in brackets at the beginning of a line, such as [5],
represents that the C breakpointable line number starts with the following instruction.
An expression such as <40> in the operand field, following a relative displacement
for control transfer instructions, is the computed address within the section to which
control will be transferred. A C function name appears in the first column, followed
by O.

5-137

M32D1S

(Command)

M32D1S

DIAGNOSTICS
The self-explanatory diagnostics indicate errors in the command line or problems
encountered with the specified files.
SEE ALSO
m32as, m32cc, m321d.

5-138

M32DUMP

(Command)

M32DUMP

NAME
m32dump - Dump Selected Parts of an Object File
SYNOPSIS
m32dump [-acd fgblooprstuv] [-z name] files
DESCRIPTION
The m32dump command dumps selected parts of each of its objectfi/e arguments.
This command accepts both object files and archives of object files. It processes each
file argument according to one or more of the following options:
-a

Dump the archive header of each member of each archive file argument.

-g

Dump the global symbols in the symbol table of an archive.

-f

Dump each file header.

-0

Dump each optional header.

-b

Dump section headers.

-s

Dump section contents.

-r

Dump relocation information.

-I

Dump line number information.

-t

Dump symbol table entries.

-z name

Dump line number entries for the named function.

-c

Dump the string table.

The following modifiers are used in conjunction with the options listed above to
modify their capabilities.
-d number Dump the section number or range of sections starting at number and
ending either at the last section number or number specified by +d.
+d number Dump sections in the range either beginning with first section or
beginning with section specified by -d.
-0

name

Dump information pertaining only to the named entity. This modifier
applies to -b -s, -r, -I, and -to

-p

Suppress printing of the headers.

-t index

Dump only the indexed symbol table entry. The -t used in conjunction
with +t specifies a range of symbol table entries.

5-139

M32DUMP

(Command)

M32DUMP

+t index

Dump the symbol table entries in the range ending with the indexed
entry. The range begins at the first symbol table entry or at the entry
specified by the -t option.

-u

Underline the name of the file for emphasis.

-v

Dump information in symbolic representation rather than numeric (e.g.,
C_STATIC instead of OX02). This modifier can be used with the above
options except -s and -0 options of m32dump.

-z name,
number

Dump line number entry or range of line numbers starting at number for
the named function.

+z number Dump line numbers starting at either function name or number specified
by -z, up to number specified by +z.
Blanks separating an option and its modifier are optional. The comma separating the
name from the number modifying the -z option may be replaced by a blank.
The m32dump command attempts to format the information it dumps in a meaningful
way, printing certain information in character, hex, octal or decimal representation as
appropriate.
SEE ALSO
m32a.out, m32ar

5·140

M32LD

(Command)

M32LD

NAME
m321d - Link Editor for WE 32100 Microprocessor Object Files
SYNOPSIS
m321d [-al [-e epsyml [-f filll [-Ixl [-ml [-rl [-sl [-0 outfilel [-u symnamel
[-L dirl [-Nl [-vl [-VS numl [-xl file-names
DESCRIPTION
The m321d command combines several object files into one, performs relocation,
resolves external symbols, and supports symbol table information for symbolic
debugging. In the simplest case, the names of several object programs are given, and
m321d combines them, producing an object module that can either be executed or used
as input for a subsequent m321d run. The output of m321d is left in m32a.out. This
file is executable if no errors occurred during the load. If any input file, file-name, is
not an object file, m32ld assumes it is either an ASCII file containing link editor
directives or an archive library.
If any argument is a library, it is searched exactly once at the point it is encountered
in the argument list. Only those routines defining an unresolved external reference are
loaded. The library (archive) symbol table is searched sequentially with as many
passes as are necessary to resolve external references which can be satisfied by library
members. Thus, the ordering of library members is unimportant.
The following options are recognized by m321d.

-a

Produce an absolute file; give warnings for undefined references.
Relocation information is stripped from the output object file unless the
-r option is given. The -r option is needed only when an absolute file
should retain its relocation information (not the normal case). If neither
-a nor -r is given, -a is assumed.

-e epsym

Set the default entry point address for the output file to be that of the
symbol epsym. This option forces the -x option to be set.

-f fill

Set the default fill pattern for "holes" within an output section as well as
initialized bss sections. The argument fill is a two-byte constant.

-I

Specify a library named x. It stands for Iibx.a where x is up to seven
characters. A library is searched when its name is encountered, so the
placement of a -I is significant. By default, libraries are located in
LIBDIR.

-m

Generate a map or listing of the input/output sections on the standard
output.

5-141

(Command)

M32LD

M32LD

-ooutfile

Produce an output object file named outfile. The name of the default
object file is m32a.out.

-r

Retain relocation entries in the output object file. Relocation entries
must be saved if the output file is to become an input file in a
subsequent m321d run. Unless -a is also given, the link editor will not
complain about unresolved references.

-s

Strip line number entries and symbol table information from the output
object file.

-t

Turn off the warning about multiply-defined symbols that are the same
size.

-u symname Enter the argument symname as an undefined symbol in the symbol
table. This is useful for loading entirely from a library, since initially
the symbol table is empty and an unresolved reference is needed to force
the loading of the first routine.
-L dir

Change the algorithm of searching for Iibx.a to look in djr before
looking in LIBDIR.

-m

Output a message for each multiply-defined external definition.
However, if the object being loaded include debugging information,
extraneous outputs is produced (see the -g option in m32cc).

-N
-V

Put the data section immediately following the text in the output file.

-VS num

Output version of m321d being used.
Use num as a decimal version number identifying the m32a.out file that
is produced. The version stamp is stored in the optional header.

FILES
File
LIBDIR/libx.a
m32a.out

Description
libraries
output file

CAVEATS
Through its input directives, the link editor gives users great flexibility; however,
people who use the input directives must assume some added responsibilities. Input
directives should insure the following properties for programs:
C defines a zero pointer as null. A pointer to which zero has been assigned must not
point to any object. To satisfy this, users must not place any object at virtual address
zero in the data space.

5-142

M32LIST

(Command)

M32LIST

NAME
m32list - Produce C Source Listing from WE 32100 Microprocessor Object File
SYNOPSIS
m32list [-V] [-h] source file ... [object-file]
DESCRIPTION
The m321ist command produces a C source listing with line number information. If
multiple C source files were used to create the object file, m32list will accept multiple
file names. The object file is taken to be the last non-C source file argument. If no
object file is specified, the m32a.out default object file, m32.out is used.
Line numbers are printed for each breakpoint inserted by the compiler (generally,
each executable C statement that begins a new line of source code). Line numbering
begins at once for each function. Line number I is always the line containing the left
curly brace (() that begins the function body. Line numbers are also supplied for
inner block redeclarations of local variables so that they can be distinguished by the
symbolic debugger.
The -V flag supplies m32list version information.
The -h flag suppresses heading output.
CAVEATS
Object files given to m32list must have symbolic debugging symbols.
Since m32list does not use the C preprocessor, it may be unable to recognize function
definitions whose syntax has been distorted by the use of C preprocessor macro
substitutions.
SEE ALSO
m32as, m32cc, m321d.
DIAGNOSTICS
m32list will produce the error message.
m32list: name: cannot open if name cannot be read.
The following messages are produced when m32list has become confused by #ifdef's in
the source file:
m32list: name: out of synch: too many}
m32list: name: unexpected end-of-file

5-143

M32LIST

(Command)

M32LIST

The error message

m32list: name: missing or inappropriate line numbers
means that either symbolic debugging information is missing or m32list has been
confused by C preprocessor statements.
If the source file names do not end in .c the message is

m32list: name: invalid C source name
An invalid object file will cause the message

m32list: name: bad magic
to be produces. If some or all of the symbolic debugging information is missing, one
of the following messages will be printed:

m32list: name: symbols have been stripped, cannot proceed
m32list: name: cannot read line numbers
m32list: name: not in symbol table

5-144

M32LORDER

M32LORDER

(Command)

NAME
m3210rder - Find Ordering Relation for an Object Library
SYNOPSIS
m3210rder files
DESCRIPTION
The input is one or more object or library archive files. The standard output is a list
of pairs of object file names, meaning that the first file of the pair refers to external
identifiers defined in the second.
The output may be processed by tsort(t) to find a ordering of a library suitable for
one-pass access by m321d(t). The link editor is capable of mUltiple passes over the
archive and does not require that m3210rder be used when building an archive. The
usage of m3210rder may, however, allow for a slightly more efficient access of the
archive during the link edit process.
The following example builds a new library from existing

.0

files.

ar cr library 'm3210rder *.0 I tsort'
FILES
*symref, *symdef temporary files
SEE ALSO
m321d, m32ar, sort
BUGS
Object files whose names do not end with .0, even when contained in library archives,
are overlooked. Their global symbols and references are attributed to some other file.

5·145

(Command)

M32MAN

M32MAN

NAME
m32man -

Print On-Line Documentation for WE 32100 Microprocessor

SYNOPSIS
m32man command

DESCRIPTION
m32man is a shell command file which prints on-line documentation for WE 32100

Microprocessor commands.
DIAGNOSTICS

can't open MANDIR/command.out
Manual page for command is not on system.
FILES

MAND IRI command.out

5-146

M32NM

(Command)

M32NM

NAME
m32nm - Print Name List of WE 32100 Microprocessor Object File
SYNOPSIS
m32nm [-o][-x] [-v] [-0] [-e] [-f] [-u] [-V] file name ...
DESCRIPTION
The m32nm command displays the symbol table of each object file file-name. filename may be a relocatable or absolute object file or it may be an archive of such
object files. For each symbol, the following information is printed:
Name

The name of the symbol.

Value

Its value expressed as an offset or an address depending on its storage
class.

Class

Its storage class.

Type

Its type and derived type. If the symbol is an instance of a structure or of
a union then the structure or union tag is given following the type (e.g.,
struct-tag). If the symbol is an array, then the array dimensions are given
following the type (e.g., charln][m)).

Size

Its size in bytes, if available.

Line

The source line number at which it is defined, if available.

Section

For storage classes static and external, the object file section containing
the symbol.

The output of m32nm may be controlled using the following flags:
-0

A symbol's value and size are printed in octal instead of decimal.

-x

A symbol's value and size are printed in hexadecimal instead of decimal.

-h

Do not display the output header data.

-v

External symbols are sorted by value before being printed.

-n

External symbols are sorted by name before being printed.

-e

Only static and external symbols are printed.

-f

"Fancy" output is produced; that is, the symbol table information is postprocessed to reflect the block structure of the source code.

-u

Only undefined symbols are printed.

-r

Prep end the name of the object file to each output line.

5-147

M32NM

(Command)

M32NM

-p

Produce easily parsed, terse output. Each symbol name is preceded by its
value (blanks if undefined) and one of the letters U (undefined), A
(absolute), T (text segment symbol), D (data segment symbol), S (userdefined segment symbol), R (register symbol), F (file symbol), or C
(common symboO. If the symbol is local (nonexternaO, the type letter is
in lower case.

-v

Print the version of nm command executing on the standard error output.

-T

By default, nm prints the entire name of the symbols listed. Since object
files can have symbol names with an arbitrary number of characters, a
name that is longer than the width of the column set aside for names will
overflow its column, forcing every column after the name to be misaligned.
The -T option causes nm to truncate every name which would otherwise
overflow its column and place an asterisk as the last character in the
displayed name to mark it as truncated.

Flags may be used in any order, either singly or in combination, and may appear
anywhere in the command line. Therefore, both m32nm name -e -v and m32nm -ve
name print the static and external symbols in name, with external symbols sorted by
value.
FILES
lusr/tmp/nm??????
SEE ALSO
m32as,m32cc,m32Id.
DIAGNOSTICS

5-148

m32nm:

name: cannot open
if name cannot be read.

m32nm:

name: bad magic
if name is not an object file.

m32nm:

name: no symbols
if the symbols have been stripped from name.

M32SIZE

(Command)

M32SIZE

NAME
m32size - Print Section Sizes for WE 32100 Microprocessor Object Files
SYNOPSIS
m32size [-01 [-xl [-vI files
DESCRIPTION
The m32size command produces section size information for each section in the object
files.
Numbers are printed in decimal unless either the -0 or the -x option is used, in
which case they are printed in octal or in hexadecimal, respectively.
The -V flag supplies version information on the m32size command.
SEE ALSO
m32as, m32cc, m321d.
DIAGNOSTICS
m32size: name: cannot open
if name cannot be read.
m32size:

name: bad magic
if name is not a WE 32100 Microprocessor object file.

5-149

M32STRIP

(Command)

M32STRIP

NAME
m32strip - Strip Symbol and Line Number Information From WE 32100
Microprocessor Object File
SYNOPSIS
m32strip [-I] [-x] [-r] [-s] [ -V] file-names
DESCRIPTION
The m32strip command strips the symbol table and line number information from
object files, including archives. Once this has been done, no symbolic debugging
access is available for that file; therefore, this command is normally run only on
production models that have been debugged and tested.
The amount of information stripped from the symbol table can be controlled using the
following options:
-I

Strip line number information only; do not strip any symbol table information.

-x

Do not strip static or external symbol information.

-r

Reset the relocation indices into the symbol table.

-b

Same as the -x option, but also do not strip scoping information (i.e., beginning
and end of block delimiters).

-V

Print version of m32strip command executing.

If there are any relocation entries in the object file and any symbol table information
is to be stripped, m32strip will terminate without stripping file-name unless the -r
flag is used.

If the m32strip command is executed on a common archive file (see m32ar file
format), the archive symbol table will be removed. The archive symbol table must be
restored by executing the m32ar command with the s option before the archive can be
link-edited by the Id command. m32strip will instruct the user with appropriate
warning messages when this instruction arises.
The purpose of this command is to reduce the file storage overhead taken by the
object file.
FILES
/usr/tmp/m32str???? ??
SEE ALSO
m32as, m32cc, m321d

5-150

M32STRIP

(Command)

M32STRIP

DIAGNOSTICS

m32strip:

name: cannot open

m32strip:

name: bad magic
if name is not a WE 32100 Microprocessor object file

m32strip:

name relocation entries present; cannot strip
if name contains relocation entries, the -r flag not used, and any symbol
table information was to be stripped.

5-151

A64L
L64A

(Subroutine)

A64L
L64A

NAME
a64l, 164a - convert between long integer and base-64 ASCII string
SYNOPSIS
long a641 (s)
char *s;
char *164a (J)
long I;
DESCRIPTION
These functions are used to maintain numbers stored in base-64 ASCII characters.
This is a notation by which long integers can be represented by up to six characters;
each character represents a "digit" in a radix-64 notation.
The characters used to represent "digits" are. for 0, / for 1,0 through 9 for 2-11, A
through Z for 12-37, and a through z for 38-63.

a641 takes a pointer to a null-terminated base-64 representation and returns a
corresponding long value. If the string pointed to by s contains more than six
characters, a641 will use the first six.
164a takes a long argument and returns a pointer to the corresponding base-64
representation. If the argument is 0, 164a returns a pointer to a null string.

BUGS
The value returned by 164a is a pointer into a static buffer, the contents of which are
overwritten by each call.

5-152

ABS

(Subroutine)

ABS

NAME
abs - return integer absolute value
SYNOPSIS
iot abs (j)
iot i;
DESCRIPTION
abs returns the absolute value of its integer operand.

BUGS
, In two's complement representation, the absolute value of the negative integer with
largest magnitude is undefined. Some implementations trap this error, but others
simply ignore it.
SEE ALSO
floor (3 M).

5-153

BSEARCH

(Subroutine)

BSEARCH

NAME
bsearch - binary search a sorted table
SYNOPSIS
#include 
char *bsearch «char *) key, (char *) base, nel, sizeof (*key), compar)
unsigned nel;
int (*compar) ( );

DESCRIPTION
bsearch is a binary search routine generalized from Knuth (6.2.1) Algorithm B. It
returns a pointer into a table indicating where a datum may be found. The table must
be previously sorted in increasing order according to a provided comparison function.
key points to a datum instance to be sought in the table. base points to the element at
the base of the table. nel is the number of elements in the table. compar is the name
of the comparison function, which is called with two arguments that point to the
elements being compared. The function must return an integer less than, equal to, or
greater than zero as accordingly the first argument is to be considered less than, equal
to, or greater than the second.
EXAMPLE
The example below searches a table containing pointers to nodes consisting of a string
and its length. The table is ordered alphabetically on the string in the node pointed to
by each entry.
This code fragment reads in strings and either finds the corresponding node and prints
out the string and its length, or prints an error message.
#incIude 
#incIude 
#define T ABSIZE

1000

struct node {
char *string;
int length;
};
struct node table[TABSIZE];

1* these are stored in the table *1

1* table to be searched *1

struct node *node.JJtr, node;
int node_compare ( ); 1* routine to compare 2 nodes *1
char str_space[20]; I*space to read string into *1

5-154

BSEARCH

(Subroutine)

BSEARCH

node. string = str_space;
while (scanf{"%s", node. string) != EOF) {
node--ptr = {struct node *)bsearch«char *)(node),
(char *hable, T ABSIZE,
sizeof(struct node), node_compare);
if (node--ptr != NULL) {
(void)printf{"string = %20s, length = %d\n",
node--ptr- > string, node--ptr- > length);
} else {
(void)printf{"not found: %s\n", node.string);
}

/*

This routine compares two nodes based on an
alphabetical ordering of the string field.
*/
int
node_compare{nodel, node2)
struct node *nodel, *node2;
{
return strcmp (node 1- > string, node2- > string);

NOTES
The pointers to the key and the element at the base of the table should be of type
pointer-to-element, and cast to type pointer-to-character. The comparison function
need not compare every byte, so arbitrary data may be contained in the elements in
addition to the values being compared. Although declared as type pointer-tocharacter, the value returned should be cast into type pointer-to-element.
SEE ALSO
hsearch (3C), lsearch, qsort (3 C) , tsearch (3C).
DIAGNOSTICS
A NULL pointer is returned if the key cannot be found in the table.

5-155

CONY

(Subroutine)

CONY

NAME
toupper, tolower, _toupper, _tolower, toascii - translate characters
SYNOPSIS
#incIude 
int toupper (c)
int c;
int tolower (c)
int c;
int _toupper (c)
int c;
int _tolower (c)
int c;
int toascii (c)
int c;
DESCRIPTION
toupper and tolower have as domain the range of getc(3S): the integers from -)
through 255. If the argument of toupper represents a lower-case letter, the result is
the corresponding upper-case letter. If the argument of tolower represents an uppercase letter, the result is the corresponding lower-case letter. All other arguments in
the domain are returned unchanged.
The macros _to upper and _tolower are macros that accomplish the same thing as
toupper and tolower but have restricted domains and are faster. _toupper requires a
lower-case letter as its argument; its result is the corresponding upper-case letter. The
macros _tolower requires an upper-case letter as its argument; its result is the
corresponding lower-case letter. Arguments outside the domain cause undefined
results.
toascii yields its argument with all bits turned off that are not part of a standard
ASCII character; it is intended for compatibility with other systems.

SEE ALSO
ctype, getc(3S).

5-156

CRYPT

(Subroutine)

CRYPT

NAME
crypt, setkey, encrypt - generate DES encryption
SYNOPSIS
char *crypt (key, salt)
char *key, *salt;
void setkey (key)
char *key;
void encrypt (block, edflag)
char *block;
int edflag;
DESCRIPTION
crypt is the password encryption function. It is based on the NBS Data Encryption
Standard (DES), with variations intended (among other things) to frustrate use of
hardware implementations of the DES for key search.
key is a user's typed password. salt is a two-character string chosen from the set [azA-ZO-9.11; this string is used to perturb the DES algorithm in one of 4096 different
ways, after which the password is used as the key to encrypt repeatedly a constant
string. The returned value points to the encrypted password. The first two characters
are the salt itself.
The set key and encrypt entries provide (rather primitive) access to the actual DES
algorithm. The argument of setkey is a character array of length 64 containing only
the characters with numerical value 0 and 1. If this string is divided into groups of 8,
the low-order bit in each group is ignored; this gives a 56-bit key which is set into the
machine. This is the key that will be used with the above mentioned algorithm to
encrypt or decrypt the string block with the function encrypt.
The argument to the encrypt entry is a character array of length 64 containing only
the characters with numerical value 0 and 1. The argument array is modified in place
to a similar array representing the bits of the argument after having been subjected to
the DES algorithm using the key set by setkey. If edflag is zero, the argument is
encrypted; if non-zero, it is decrypted.

SEE ALSO
10gin(1), passwd(J), getpass{3C), passwd(4).
BUGS
The return value points to static data that are overwritten by each call.

5-157

CTYPE

(Subroutine)

CTYPE

NAME
isalpha, is upper, islower, isdigit, isxdigit, isalnum, isspace, ispunct, isprint, isgraph,
iscontrl, isascii - classify characters
SYNOPSIS
#incIude 
int isaJpha (c)
int c;
DESCRIPTION
These macros classify character-coded integer values by table lookup. Each is a
predicate returning nonzero for true, zero for false. isascii is defined on all integer
values; the rest are defined only where isascii is true and on the single non-ASCII
value EOF (-1 - see stdio(3S).
isalpha

c is a letter.

is upper

c is an upper-case letter.

islower

c is a lower-case letter.

isdigit

c is a digit [0-91.

isxdigit

c is a hexadecimal digit [O-9UA-FJ or [a-f1.

isalnum

c is an alphanumeric (Jetter or digit).

isspace

c is a space, tab, carriage return, new-line, vertical tab, or form-feed.

ispunct

c is a punctuation character (neither control nor alphanumeric).

isprint

c is a printing character, code 040 (space) through 0176 (tilde).

isgraph

c is a printing character, like isprint except false for space.

iscntrl

c is a delete character (0177) or an ordinary control character (Jess than
040).

isascii

c is an ASCII character, code less than 0200.

DIAGNOSTICS
If the argument to any of these macros is not in the domain of the function, the result
is undefined.
SEE ALSO
stdio(3S), ascii(5).

5-158

L3TOL

(Subroutine)

L3TOL

NAME
13tollto13 - convert between 3-byte integers and long integers
SYNOPSIS
void l3tol Op, cp, n)
long *Ip;
char *cp;
int n;
void Itol3 (cp, Ip, n)
char *cp;
long *Ip;
int n;
DESCRIPTION
I3tol converts a list of n three-byte integers packed into a character string pointed to
by cp into a list of long integers pointed to by Ip.
Itol3 performs the reverse conversion from long integers Up) to three-byte integers
(cp).

These functions are useful for file-system maintenance where the block numbers are
three bytes long.
SEE ALSO
fs(4).

BUGS
Because of possible differences in byte ordering, the numerical values of the long
integers are machine-dependent.

5-159

LDAHREAD

(Subroutine)

LDAHREAD

NAME
Idahread - Read Archive Header of an Archive File Member
SYNOPSIS
#incIude
#include
#incIude
#incIude



"INCDIR/filehdr.h"
"INCDIR/Idfcn.h"

int Idahread Odptr,arhead)
LDFILE *Idptr;
ARCHDR *arhead;
DESCRIPTION
If TYPE([dptr) is the archive file magic number, idahread reads the archive header of
the object file currently associated with Idptr into the area of memory beginning at
arhead.
Idahread returns SUCCESS or FAILURE. Idahread fails if TYPE([dptr) does not
represent an archive file, or if it cannot read the archive header.

The program must be loaded with the object file access routine library
LIBDIR/Iibld.a.
intro describes LlBDIR and INCDIR.

SEE ALSO
idc/ose, Idopen, Idfcn, m32ar format

5-160

LDCLOSE

(Subroutine)

LDCLOSE

NAME
ldclose. ldaclose - Close a WE 32100 Microprocessor Object File
SYNOPSIS
#include 
#include "INCDIR/fiIehdr.h"
#include "INCDIR/ldfcn.h"
int Idclose Odptr)
LDFILE *Idptr;
int Idaclose Odptr)
LDFILE *Idptr;
DESCRIPTION
ldopen and idc/ose provide uniform access to both simple object files and object files
that are members of archive files. Thus an archive of object files can be processed as
if it were a series of simple object files.
If TYPE(ldptr) does not represent an archive file, idc/ose will close the file and free
the memory allocated to the LDFILE structure associated with ldptr. If TYPE(Jdptr)
is the magic number of an archive file, and if there are any more files in the archive,
idc/ose reinitializes OFFSET(Jdptr) to the file address of the next archive member and
returns FAILURE. The LDFILE structure is prepared for a subsequent ldopen. In
all other cases, ldc/ose returns SUCCESS.

ldac/ose closes the file and frees the memory allocated to the LDFILE structure
associated with ldptr regardless of the value of TYPE(Jdptr). ldaclose always returns
SUCCESS. The function is often used in conjunction with idaopen.

The program must be loaded with the object file access routine library
LIBDIR/libld.a.
intro describes INCDIR and LIBDIR.

SEE ALSO
idopen, intro, idfcn, paths

5-161

LDFHREAD

(Subroutine)

LDFHREAD

NAME
ldfhread - Read the File Header for a WE 32100 Microprocessor Object File
SYNOPSIS
#incIude 
#incIude "INCDIR/filehdr.h"
#incIude "INCDIR/ldfcn.h"
int Idfhread Odptr, filehead)
LDFILE *Idptr;
FILHDR *filehead;
DESCRIPTION
ldfhread reads the file header of the object file currently associated with ldptr into the
area of memory beginning at filehead.
ldfhread returns SUCCESS or FAILURE. ldfhread fails if it cannot read the file
header.
In most cases the use of ldfhread can be avoided by using the macro HEADER([dptr)
defined in Idfcn.h (see ldfcn). The information in any field, fieldname, of the file
header may be accessed using HEADER(tdptr)/ieldname.
The program must be loaded with the object file access routine library
LIBDIR/libld.a.
intro describes INCDIR and LlBDIR.
SEE ALSO
ldclose, ldopen, intro, ldfcn, paths

5·162

LDGETNAME<3X)

(Subroutine)

LDGETNAME(3X)

NAME
ldgetname - retrieve symbol name for object file symbol table entry
SYNOPSIS
#include
#include
#include
#include


"INCDIR/filehdr.h"
"INCDIRlsyms.h"
"INCDIR/ldfcn.h"

char *ldgetname (Jdptr, symbol)
LDFILE *ldptr;
SYMENT *symbol;
DESCRIPTION
Ldgetname returns a pointer to the name associated with symbol as a string. The
string is contained in a static buffer local to ldgetname that is overwritten by each call
to ldgetname, and therefore must be copied by the caller if the name is to be saved.
Ldgetname will return NULL (defined in stdio.h) for an object file if the name cannot
be retrieved. This situation can occur:
o

if the "string table" cannot be found,

• if enough memory cannot be allocated for the string table,
o if the string table appears not to be a string table (for example, if an auxiliary entry
is handed to ldgetname that looks like a reference to a name in a nonexistent string
table), or
• if the name's offset into the string table is past the end of the string table.
Typically, ldgetname will be called immediately after a successful call to ldtbread to
retrieve the name associated with the symbol table entry filled by ldtbread.
The program must be loaded with the object file access routine library
LlBDIR/libld.a.
intro describes INCDIR and LIBDIR.
SEE ALSO
ldclose, ldopen, ldtbseek, ldtbread, intra ldfcn, paths

5-163

LDLREAD

(Subroutine)

LDLREAD

NAME
ldlread, ldlinit, ldlitem - Manipulate Line Number Entries for a WE 32100
Microprocessor Object File Function
SYNOPSIS
#include < stdio.h >
#include "INCDIR/fiIehdr.h"
#include "INCDIR/linenum.h"
#include "INCDIR/Idfcn.h"
int Idlread Odptr,fcnindx,linenum,linent>
LDFILE *Idptr;
long fcnindx;
unsigned short Iinenum;
LINENO Iinent;
int Idlinit Odptr,fcnindx)
LDFILE *Idptr;
long fcnindx;
int IdlitemOdptr, linenum, Iinent)
LDFILE *Idptr;
unsigned short Iinenum;
LINENO Iinent;
DESCRIPTION
ldlread searches the line number entries of the object file currently associated with
ldptr. ldlread begins its search with the line number entry for the beginning of a
function and confines its search to the line numbers associated with a single function.
The function is identified by fcnindx, the index of its entry in the object file symbol
table. ldlread reads the entry with the smallest line number equal to or greater than
linenum into linent.

ldlinit and ldlitem together perform exactly the same function as Idlread. After an
initial call to ldlread or ldlinit, ldlitem may be used to retrieve a senes of line RUmber
entries associated with a single function. ldlinit simply locates the line number entries
for the function identified by fcnindx. ldlitem finds and reads the entry with the
smallest line number equal to or greater than linenum into linent.

5-164

LDLREAD

(Subroutine)

LDLREAD

ldlread, ldlinit, and ldlitem each return either SUCCESS or FAILURE. ldlread fails
if there are no line number entries in the object file, if fcnindx does not index a
function entry in the symbol table, or if it finds no line number equal to or greater
than linenum. ldlinit fails if there are no line number entries in the object file or if
fcnindx does not index a function entry in the symbol table. ldlitem fails if it finds no
line number equal to or greater than linenum.
The programs must be loaded with the object file access routine library
LIBDIRflibld.a.
SEE ALSO
ldclase, ldapen, ldtbindex, intra, ldfcn, paths.

5-165

LSEARCH

LSEARCH

(Subroutine)

NAME
lsearch, lfind - linear search and update
SYNOPSIS
#include 
#include < search.h >
char *lsearch «char *)key, (char *)base, nelp, sizeof(*key), compar)
unsigned *nelp;
int (*compar) ( );
char *lfind «char *)key, (char *)base, nelp, sizeof(*key), compar)
unsigned *nelp;
int (*compar)( );
DESCRIPTION
lsearch is a linear search routine generalized from Knuth (6.1) Algorithm S. It
returns a pointer into a table indicating where a datum may be found. If the datum
does not occur, it is added at the end of the table. key points to the datum to be
sought in the table. base points to the first element in the table. nelp points to an
integer containing the current number of elements in the table. The integer is
incremented if the datum is added to the table. compar is the name of the comparison
function which the user must supply (strcmp, for example). It is called with two
arguments that point to the elements being compared. The function must return zero
if the elements are equal and nonzero otherwise.

/find is the same as lsearch except that if the datum is not found, it is not added to
the table. Instead, a NULL pointer is returned.
NOTES
The pointers to the key and the element at the base of the table should be of type
pointer-to-element, and cast to type pointer-to-character. The comparison function
need not compare every byte, so arbitrary data may be contained in the elements in
addition to the values being compared. Although declared as type pointer-tocharacter, the value returned should be cast into type pointer-to-element.
EXAMPLE
This fragment will read in ~ T ABSIZE strings of length
in a table, eliminating duplicates.
#include 
#include 
#define T ABSIZE 50
#define ELSIZE 120

5-166

~

ELSIZE and store them

LSEARCH

(S u brou tine)

LSEARCH

char line(ELSIZE1, tab[TABSIZE][ELSIZE1, *Isearch( );
unsigned nel = 0;
int strcmp( );

while (fgets(Jine, ELSIZE, stdin) != NULL &&
nel < T ABSIZE)
(void) Isearch(!ine, (char *}tab, &nel,
ELSIZE, strcmp);
SEE ALSO
bsearch, hsearch (3C), tsearch (3C).
DIAGNOSTICS

If the searched for datum is found, both /search and /find return a pointer to it.
Otherwise, /find returns NULL and /search returns a pointer to the newly added
element.
BUGS

Undefined results can occur if there is not enough room in the table to add a new
item.

5-167

LDLSEEK

(Subroutine)

LDLSEEK

NAME
ldlseek,idnlseek - Seek to Line Number Entries of a Section of a WE 32100
Microprocessor Object File
SYNOPSIS
#include 
#include "INCDIR/filehdr.h"
#include "INCDIR/ldfcn.h"
int Idlseek Odptr, sectindx)
LDFILE *Idptr;
unsigned short sectindx;
int Idnlseek Odptr, sectname)
LDFILE *Idptr;
char *sectname;
DESCRIPTION
ldlseek seeks to the line number entries of the section specified by sectindx of the
object file currently associated with ldptr.
ldnlseek seeks to the line number entries of the section specified by sectname.
ldlseek and ldnlseek return SUCCESS or FAILURE. ldlseek fails if sectindx is
greater than the number of sections in the object file; ldnlseek fails if there is no
section name corresponding with *sectname. Either function fails if the specified
section has no line number entires or if it cannot seek to the specified line number
entries.
Note that the first section has an index of one.
The program must be loaded with the object file access routine library
LIBDIR/libld.a.
intro describes INCDIR and LIBDIR.
SEE ALSO
ldclose, ldopen, ldshread, intro, ldfcn, paths

5-168

LDOHSEEK

(Subroutine)

LDOHSEEK

NAME
Idohseek - Seek to the Optional File Header of a WE 32100 Microprocessor Object
File
SYNOPSIS
#include 
#include "INCDIRifilehdr.h"
#include "INCDIRildfcnh.h"
int Idohseek Odptr)
LDFILE *Idptr;
DESCRIPTION
Idohseek seeks to the optional file header of object file currently associated with Idptr.
ldohseek returns SUCCESS or FAILURE. Idohseek fails if the object file has no
optional header or if it cannot seek to the optional header.

The program must be loaded with the object file access routine library
LIBDIRllibld.a.
intro describes INCDIR and LIBDIR.

SEE ALSO
Idclose, Idopen, Idfhread, intro, Idfcn, paths

5-169

LDOPEN

(Subroutine)

LDOPEN

NAME
ldopen. ldaopen - Open a WE 32100 Microprocessor File for Reading
SYNOPSIS
#include 
#include "INCDIR/filebdr.b"
#include "INCDIR/ldfcn.b"
LDFILE *ldopen (filename, Idptr)
cbar *filename;
LDFILE *ldptr;
LDFILE *ldaopen (filename, oldptr)
cbar *filename;
LDFILE *oldptr;
DESCRIPTION
ldopen and Idclose provide uniform access to both simple object files and object files
that are members of archive files. Thus an archive of object files can be processed as
if it were a series of simple object files.
If Idptr has the value NULL, then Idopen opens filename and allocates and initializes
the LDFILE structure, and returns a pointer to the structure to the calling program.

If Idptr is valid and if TYPEUdptr) is the archive magic number, Idopen reinitializes
the LDFILE structure for the next archive member of filename.
Idopen and Idclose are designed to work in concert. Idclose returns FAILURE only
when TYPEUdptr) is the archive magic number and there is another file in the
archive to be processed. Only then should Idopen be called with the current value of
ldptr. In all other cases, in particular whenever a new filename is opened, ldopen
should be called with a NULL Idptr argument.

The following is a prototype for the use of Idopen and ldclose.
/*for each filename to be processed*/
ldptr = NULL;
do
if (Jdptr + ldopen(filename, ldptr» != NULL)
{
/* check magic number */
/* process the file */
}
}while (Jdc1ose(Jdptr) == FAILURE);

5·170

LDOPEN

(Subroutine)

LDOPEN

If the value of oldptr is not NULL, Idaopen opens filename anew and allocates and
initializes a new LDFILE structure, copying the TYPE, OFFSET, and HEADER
fields from oldptr. Idaopen returns a pointer to the new LDFILE structure. This new
pointer is independent of the old pointer, oldptr. The two pointers may be used
concurrently to read separate parts of the object file. For example, one pointer may
be used to step sequentially through the relocation information, while the other is used
to read indexed symbol table entries.

Both Idopen and Idaopen open filename for reading. Both functions return NULL if
filename cannot be opened, or if memory for the LDFILE structure cannot be
allocated. A successful open does not insure that the given file is an object file or an
archived object file.
The program must be loaded with the object file access routine library
LIBDlR/libld.a.
intro describes INCDIR and LIBDIR.

SEE ALSO
Idclose. intro. Idfcn. paths

5-171

(Subroutine)

LDRSEEK
NAME
ldrseek,ldnrseek

LDRSEEK

Seek to Relocation Entries of a Section of a WE 32100
Microprocessor Object File

SYNOPSIS
#include 
#include "INCDIR/filebdr.b"
#include "INCDIR/ldfcn.b"
int Idrseek Odptr, sectindx)
LDFILE *Idptr;
unsigned sbort sectindx;
int Idnrseek Odptr, sectname)
LDFILE *Idptr;
cbar *sectname;
DESCRIPTION
ldrseek seeks to the relocation entries of tbe section specified by sectindx of the object
file currently associated witb ldptr.
ldnrseek seeks to the relocation entries of the section specified by sectname.
ldrseek and ldnrseek return SUCCESS or FAILURE. ldrseek fails if sectindx is
greater than the number of sections in the object file; ldnrseek fails if there is no
section name corresponding with sectname. Either function fails if the specified
section has no relocation entries or if it cannot seek to the specified relocation entries.
Note that the first section has an index of one.
The program must be loaded with the object file access routine library
LIBDIRllibld.a.
intro describes INCDIR and LIBDIR.
SEE ALSO
ldclose, ldopen, ldshread, intro, ldfcn, paths

5-172

(Subroutine)

LDSHREAD
NAME
ldshread,ldnshread
SYNOPSIS
#include
#include
#include
#include

LDSHREAD

Read an Indexed/Named Section Header of a WE 32100
Microprocessor Object File


"INCDIR/fiIehdr.h"
"INCDIR/scnhdr.h"
"INCDIR/ldfcn.h"

int ldshread Odptr, sectindx, secthead}
LDFILE *ldptr;
unsigned short sectindx;
SCNHDR *secthead;
int ldnshread Odptr, sectname, secthead}
LDFILE *ldptr;
char sectname;
SCNHDR *secthead;
DESCRIPTION
ldshread reads the section header specified by sectindx of the object file currently
associated with ldptr into the area of memory beginning at secthead.

ldnshread reads the section header specified by sectname into the area of memory
beginning at secthead.
ldshread and ldnshread return SUCCESS or FAILURE. ldshread fails if sectindx is
greater than the number of sections in the object file; ldnshread fails if there is no
section name corresponding with sectname. Either function fails if it cannot read the
specified section header.
Note that the first section header has an index of one.
The program must be loaded with the object file access routine library
LIBDIR/lihld.a.

intra describes INCDIR and LIBDIR.
SEE ALSO
ldclose. ldopen. intra. ldfcn. paths

5-173

LDSSEEK
NAME
ldsseek, ldnsseek

(Subroutine)

LDSSEEK

Seek to an Indexed/Named Section of a WE 32100
Microprocessor Object File

SYNOPSIS
#incIude < stdio.b >
#incIude "INCDIR/filebdr.b"
#incIude "INCDIRlldfcn.b"
int Idsseek Odptr, sectindx}
LDFILE *Idptr;
unsigned sbort sectindx;
int Idnsseek Odptr, sectname}
LDFILE *Idptr;
cbar *sectname;
DESCRIPTION
ldsseek seeks to the section specified by sectindx of the object file currently associated
with ldptr.
ldnsseek seeks to the section specified by sectname.
ldsseek and ldnsseek return SUCCESS or FAILURE. ldsseek fails if sectindx is
greater than the number of sections in the object file; ldnsseek fails if there is no
section name corresponding with sectname. Either function fails if there is no section
data for the specified section or if it cannot seek to the specified section.

Note that the first section has an index of one.
The program must be loaded with the object file access routine library LIDIR/libld.a.
intro describes INCDIR and LIBDIR.

SEE ALSO
ldclose, ldopen, ldshread, intra, ldjcn, paths

5-174

LDTBINDEX
NAME
ldtbindex
SYNOPSIS
#include

(Subroutine)

LDTBINDEX

Compute the Index of a Symbol Table Entry of a WE 32100
Microprocessor Object File

< stdio.b >

#include "INCDIR/filehdr.b"
#include "INCDIRlsyms.b"
#include "INCDIR/ldfcn.b"
long Idtbindex Odpd
LDFILE *Idptr;
DESCRIPTION
ldtbindex returns the (long) index of the symbol table entry at the current position of
the object file associated with ldpr.
The index returned by ldtbindex may be used in subsequent calls to ldtbread.
However, since ldtbindex returns the index of the symbol table entry that begins at
the current position of the object file, if ldtbindex is called immediately after a
particular symbol table entry has been read, it returns the index of the next entry.

ldtbindex fails if there are no symbols in the object file, or if the object file is not
positioned at the beginning of a symbol table entry.
Note that the first symbol in the symbol table has an index of zero.
The program must be loaded with the object file access routine library
LlBDIR/libld.a.

intro describes INCDIR and LIBDIR.
SEE ALSO
Ide lose, ldopen, ldtbread, ldtbseek, intro, ldfen, paths

5-175

LDTBREAD
NAME
ldtbread
SYNOPSIS
#include
#include
#include
#include

(Subroutine)

LDTBREAD

Read an Indexed Symbol Table Entry of a WE 32100
Microprocessor Object File

"INCDIR/filehdr.h"
"INCDIR/syms.h"
"INCDIRl1dfcn.h"

int Idtbread Odptr, symindex, symbol)
LDFILE *Idptr;
long symindex;
SYMENT *symbol;
DESCRIPTION
ldtbread reads the symbol table entry specified by symindex of the object file
currently associated with ldptr into the area of memory beginning at symbol.

ldtbread returns SUCCESS or FAILURE. ldtbread fails if symindex is greater than
the number of symbols in the object file, or if it cannot read the specified symbol table
entry.
Note that the first symbol in the symbol table has an index of zero.
The program must be loaded with the object file access routine library
LIBDIR/libld.a.

intro describes INCDIR and LIBDIR.
SEE ALSO
ldclose, ldopen, ldtbseek, intro, ldfcn, paths

5-176

LDTBSEEK

(Subroutine)

LDTBSEEK

NAME
ldtbseek - Seek to the Symbol Table of a WE 32100 Microprocessor Object File
SYNOPSIS
#include < stdio.h >
#include "INCDIR/fiIehdr.h"
#include "INCDIR/ldfcnh.h"
int Idtbseek Odptr)
LDFILE *Idptr
DESCRIPTION
ldtbseek seeks to the symbol table of the object file currently associated with ldptr.
ldtbseek return SUCCESS or FAILURE. ldtbseek fails if the symbol table has been
stripped from the object file, or if it cannot seek to the symbol table.
The program must be loaded with the object file access routine library
LIBDIR/libld.a.
intra describes INCDIR and LIBDIR.
SEE ALSO
ldclase, ldapen, ldtbread, intra, ldfcn, paths

5-177

MEMORY

(Subroutine)

MEMORY

NAME
memccpy, memchr, memcmp, memcpy, memset - memory operations
SYNOPSIS
#ioclude 
char *memccpy (st, s2, c, 0)
char *st, *s2;
iot c, 0;
char *memchr (s, c, 0)
char *s;
iot c, 0;
iot memcmp (st, s2, 0)
char *st, *s2;
iot 0;
char *memcpy (st, s2, 0)
char *st, *s2;
iot 0;
char *memset (s, c, 0)
char *s;
iot c, 0;
DESCRIPTION
These functions operate as efficiently as possible on memory areas (arrays of
characters bounded by a count, not terminated by a null character). They do not
check for the overflow of any receiving memory area.

memccpy copies characters from memory areas s2 into sl, stopping after the first
occurrence of character c has been copied, or after 0 characters have been copied,
whichever comes first. It returns a pointer to the character after the copy of c in st,
or a NULL pointer if c was not found in the first 0 characters of s2.
memchr returns a pointer to the first occurrence of character c in the first
characters of memory areas s, or a NULL pointer if c does not occur.

0

memcmp compares its arguments, looking at the first 0 characters only, and returns an
integer less than, equal to, or greater than 0, according as sl is lexicographically less
than, equal to, or greater than s2.
memcpy copies

0

characters from memory area s2 to sl. It returns st.

memset sets the first
returns s.

0

characters in memory area s to the value of character c. It

NOTE
For user convenience, all these functions are declared in the optional 
header file.

5-178

MEMORY

(Subroutine)

MEMORY

BUGS
memcmp uses native character comparison, which is signed on PDP 11 Computers and
VAX 11 Computers, unsigned on other machines. Thus the sign of the value returned
when one of the characters has its high-order bit set is implementation-dependent.
Character movement is performed differently in different implementations. Thus
overlapping moves may yield surprises.

5-179

PRINTF

(Subroutine)

PRINTF

NAME
printf, sprintf - print formatted output
SYNOPSIS
#include 
int printf (format [ , arg I ...)
char *format;
int sprintf (s, format [ , arg I ... )
char *s format;
DESCRIPTION
printfplaces output on the standard output stream stdout. sprintfplaces "output,"
followed by the null character (\0), in consecutive bytes starting at *s; it is the user's
responsibility to ensure that enough storage is available. Each function returns the
number of characters transmitted (not including the \0 in the case of sprintj), or a
negative value if an output error was encountered.
Each of these functions converts, formats, and prints its args under control of the
format. The format is a character string that contains two types of objects: plain
characters, which are simply copied to the output stream, and conversion
specifications, each of which results in fetching of zero or more args. The results are
undefined if there are insufficient args for the format. If the format is exhausted
while args remain, the excess args are simply ignored.
Each conversion specification is introduced by the character %. After the %, the
following appear in sequence:
Zero or more flags, which modify the meaning of the conversion specification.
An optional decimal digit string specifying a minimum field width. If the
converted value has fewer characters than the field width, it will be padded on
the left (or right, if the left-adjustment flag' -', described below, has been
given) to the field width. If the field width for an s conversion is preceded by
a 0, the string is right adjusted with zero-padding on the left.
A precision that gives the minimum number of digits to appear for the d, 0, u,
x, or X conversions, or the maximum number of characters to be printed from
a string in s conversion. The precision takes the form of a period (.) followed
by a decimal digit string; a null digit string is treated as zero.
An optionall (ell) specifying that a following d, 0, u, x, or X conversion
character applies to a long integer argo An 1 before any other conversion
character is ignored.
A character that indicates the type of conversion to be applied.

5-180

PRINTF

(Subroutine)

PRINTF

A field width of precision may be indicated by an asterisk (*) instead of a digit string.
In this case, an integer arg supplied the field width or precision. The arg that is
actually converted is not fetched until the conversion letter is seen, so the args
specifying field width or precision must appear before the arg (if any) to be converted.
The flag characters and their meanings are:
The result of the conversion will be left-justified within the field.

+

The result of a signed conversion will always begin with a sign (+ or -).

blank

If the first character of a signed conversion is not a sign, a blank will be

prefixed to the result. This implies that if the blank and
appear, the blank flag will be ignored.

#

+ flags both

This flag specifies that the value is to be converted to an "alternate form."
For c, d, s, and u conversions, the flag has no effect. For 0 conversion, it
increases the precision to force the first digit of the result to be a zero.
For x or X conversion, a non-zero result will have Ox or OX prefixed to it.

The conversion characters and their meanings are:
d,o,u,x,x

The integer arg is converted to signed decimal, unsigned octal, decimal,
or hexadecimal notation (x and X) respectively; the letters abcdef are
used for x conversion and the letters ABCDEF for X conversion. The
precision specifies the minimum number of digits to appear; if the value
being converted can be represented in fewer digits, it will be explained
with leading zeros. (For compatibility with older versions, padding with
leading zeros may alternatively be specified by prep ending a zero to the
field width. This does not imply an actual value for the field width.)
The default precision is 1. The result of converting a zero value with a
precision of zero is a null string.

c

The character arg is printed.

S

The arg is taken to be a string (character pointer) and characters from
the string are printed until a null character (\0) is encountered or the
number of characters indicated by the precision specification is reached.
If the precision is missing, it is taken to be infinite so all characters up to
the first null character are printed. A NULL value for arg will yield
undefined results.

%

Print a %; no argument is converted.

In no case does a nonexistent or small field width cause truncation of a field; if the
result of a conversion is wider than the field width, the field is simply expanded to
contain the conversion result. Characters generated by printf are printed as if
putc(3S) had been called.

5-181

PRINTF

(Subroutine)

PRINTF

EXAMPLE
To print a data and time in the form "Sunday, July 3, 10:02," w4ere weekday and
month are pointers to null-terminated strings:
printf("%s, %s %d, %d:%.2d", weekday, month, day, hour, min);
SEE ALSO

ecvt(3C), putc(3S), scanf, stdio(3S)

5-182

RAND

(Subroutine)

RAND

NAME
rand, srand - simple random-number generator
SYNOPSIS
iot rand ( )
void sraod (seed)
unsigned seed;
DESCRIPTION
rand uses a multiplicative congruential random-number generator with period 2 32 that
returns successive pseudo-random numbers in the range from 0 to 2 15 _1.

srand can be called at any time to reset the random-number generator to a random
starting point. The generator is initially seeded with a value of 1.
NOTE
The spectral properties of rand leave a great deal to be desired. drand48(3C) provides
a much better, though more elaborate, random-number generator.
SEE ALSO
drand48 (3C)

5-183

SCANF

(Subroutine)

SCANF

NAME
scanf, sscanf - convert formatted input
SYNOPSIS
#include 
int scanf (format [ , pointer
char *format;

1 ... )

int sscanf (s, format [ , pointer
char *s, *format;

1 ... )

DESCRIPTION
scanf reads from the standard input stream stdin. sscanf reads from the character
string s. Each function reads characters, interprets them according to a format, and
stores the results in its arguments. Each expects, as arguments, a control string
format described below, and a set of pointer arguments indicating where the converted
input should be stored.
The control string usually contains conversion specifications, which are used to direct
interpretation of input sequences. The control string may contain:
1.

White-space characters (blanks, tabs, new-lines, or form-feeds) which, except in
two cases described below, cause input to be read up to the next non-white-space
character.

2.

An ordinary character (not %), which must match the next character of the input
stream.

3.

Conversion specifications, consisting of the character %, an optional assignment
suppressing character *, an optional numerical maximum field width, an optional
I (ell) or h indicating the size of the receiving variable, and a conversion code.

A conversion specification directs the conversion of the next input field; the result is
placed in the variable pointed to by the corresponding argument, unless assignment
suppression was indicated by *. The suppression of assignment provides a way of
describing an input field which is to be skipped. An input field is defined as a string
of non-space characters; it extends to the next inappropriate character or until the
field width, if specified, is exhausted. For all descriptors except "[,, and "c", white
space leading an input field is ignored.
The conversion code indicates the interpretation of the input field; the corresponding
pointer argument must usually be of a resticted type. For a suppressed field, no
pointer argument is given. The following conversion codes are legal:

5-184

%

a single % is expected in the input at this point; no assignment is done.

d

a decimal integer is expected; the corresponding argument should be an
integer pointer.

SCANF

(Subroutine)

SCANF

u

an unsigned decimal integer is expected; the corresponding argument should
be an unsigned integer pointer.

o

an octal integer is expected; the corresponding argument should be an integer
pointer.

x

a hexadecimal integer is expected; the corresponding argument should be an
integer pointer.

s

a character string is expected; the corresponding argument should be a
character pointer pointing to an array of characters large enough to accept
the string and a terminating \0, which will be added automatically. The
input field is terminated by a white-space character.

c

a character is expected; the corresponding argument should be a character
pointer. The normal skip over white space is suppressed in this case; to read
the next non-space character, use % Is. If a field width is given, the
corresponding argument should refer to a character array; the indicated
number of characters is read.
indicates string data and the normal skip over leading white space is
suppressed. The left bracket is followed by a set of characters, which we will
call the scanset, and a right bracket; the input field is the maximal sequence
of input characters consisting entirely of characters in the scan set. The
circumflex ("), when it appears as the first character in the scanset, serves as
a complement operator and redefines the scanset as the set of all characters
not contained in the remainder of the scanset string. There are some
conventions used in the construction of the scanset. A range of characters
may be represented by the construct first -last, thus [01234567891 may be
expressed [0-91. Using this convention, first must be lexically less than or
equal to last, or else the dash will stand for itself. The dash will also stand
for itself whenever it is the first or the last character in the scanset. To
include the right square bracket as an element of the scanset, it must appear
as the first character (possibly preceded by a circumflex) of the scanset, and
in this case it will ot be syntactically interpreted as the closing bracket. The
corresponding argument must point to a character array large enough to hold
the data field and the terminating \0, which will be added automatically. At
least one character must match for this conversion to be considered
successful.
The conversion characters d, u, 0, and x may be preceded by I or h to
indicate that a pointer to long or to short rather than to int is in the
argument list. The I or h modifier is ignored for other conversion characters.

scan! conversion terminates at EOF, at the end of the control string, or when
an input character conflicts with the control string. In the latter case, the
offending character is left unread in the input steam.

5-185

SCANF

(Subroutine)

SCANF

scan! returns the number of successfully matched and assigned input items;
this number can be zero in the event of an early conflict between an input
character and the control string. If the input ends before the first conflict or
conversion, EOF is returned.
EXAMPLES
The call:
int i, n; float x; char name[50];
n = scanf ("%d%f%s", &i, &x, name);
with the input line:
25 54.32E-I thompson
will assign to n the value 3, to i the value 25, to x the value 5.432, and name will
contain thompson\O. Or:
int i; float x; char name[50];
(void) scanf("%2d%f%*d %[0-9]", &i, &x, name);
with input:
567890123 56a72
will assign 56 to i, 789.0 to x, skip 0123, and place the string 56\0 in name. The next
call to getchar (see getc(JS» will return a.
SEE ALSO
getc (38), printf, strtod (3C), strtol
NOTE
Trailing white space (including a new-line) is left unread unless matched in the
control string.
DIAGNOSTICS
These functions return EOF on end of input and a short count for missing or illegal
data items.
BUGS
The success of literal matches and suppressed assignments is not directly determinable.

5-186

SPUTL

(Subroutine)

SPUTL

NAME
sputJ, sgetl - access long integer data in a machine independent fashion.
SYNOPSIS
void sput! (value, buffer>
long value;
char *buffer;
long sgetl (buffer)
char *buffer;
DESCRIPTION
sputJ takes the four bytes of the long integer value and places them in memory
starting at the address pointed to by buffer. The ordering of the bytes is the same
across all machines.
sgetl retrieves the four bytes in memory starting at the address pointed to by buffer
and returns the long integer value in the byte ordering of the host machine.

The combination of sputl and sgetJ provides a machine-independent way of storing
long numeric data in a file in binary form without conversion to characters.
A program which uses these functions must be loaded with the object-file access
routine library LIBDIR/libld.a.

5-187

STRING

(Subroutine)

STRING

NAME
strcat, strncat, strcmp, strncmp, strcpy, strncpy, strlen, strchr, strrchr, strpbrk, strspn,
strcspn, strtok - string operations.

SYNOPSIS
#include 
char *strcat (sl, s2)
char *sl, *s2;
char *strncat (sl, s2, n)
char *sl, *s2;
int n;
int strcmp (sl, s2)
char *sl, *s2;
int strncmp (sl, s2, n)
char *sl, *s2;
int n;
char *strcpy (sl, s2)
char *sl, *s2;
char *strncpy (sl, s2, n)
char *sl, *s2;
int n;
int strlen (s)
char *s;
char *strchr (s, c)
char *s;
int c;
char *strrchr (s, c)
char *s;
int c;
char *strpbrk (sl, s2)
char *sl, *s2;
int strspn (s I, s2)
char *sl, *s2;

5-188

STRING

(Subroutine)

STRING

iot strcspo (sl, s2)
char *sl, *s2;

char *strtok (sl, s2)
char *sl, *s2;

DESCRIPTION
The arguments sl, s2 and s point to strings (arrays of characters terminated by a null
character). The functions straet, strneat, strepy, and strnepy all alter s1. These
functions do not check for overflow of the array pointed to by sl.
streat appends a copy of string s2 to the end of string sl. strneat appends at most n
characters. Each returns a pointer to the null-terminated result.
stremp compares its arguments and returns an integer less than, equal to, or greater
than 0, according as sl is lexicographically less than, equal to, or greater than s2.
strnemp makes the same comparison but looks at most n characters.
strepy copies string s2 to sl, stopping after the null character has been copied.
strnepy copies exactly 0 characters, truncating s2 or adding null characters to sl if
necessary. The result will not be null-terminated if the length of s2 is 0 or more.
Each function returns sl.
str/en returns the number of characters in s, not including the terminating null
character.
strehr (strrehr) returns a pointer to the first (last) occurrence of character c in string
s, or a NULL pointer if c does not occur in the string. The null character terminating
a string is considered to be part of the string.
strpbrk returns a pointer to the first occurrence in string sl of any character from
string s2, or a NULL pointer if no character from s2 exists in s1.
strspn (strespn) returns the length of the initial segment of string sl which consists
entirely of characters from (not from) string s2.
strtok considers the string sl to consist of a sequence of zero or more text tokens
separated by spans or one more characters from the separator string s2. The first call
(with pointer sl specified) returns a pointer to the first character of the first token,
and will have written a null character into sl immediately following the returned
token. The function keeps track of its position in the string between separate calls, so
that subsequent calls (which must be made with the first argument a NULL pointer)
will work through the string sl immediately following that token. In this way,
subsequent calls will work through the string sl until no tokens remain. The separator
string s2 may be different from call to call. When no token remains in sl, a NULL
pointer is returned.

5-189

STRING

(Subroutine)

STRING

NOTE
For user convenience, all these functions are declared in the optional 
header file.

BUGS
strcmp and strncmp use native character comparison, which is signed on PDP II
Computers and VAX II Computers, unsigned on other machines. Thus the sign of the
value returned when one of the characters has its high-order bit set is
implementation-dependent.
Character movement is performed differently in different implementations. Thus
overlapping moves may yield surprises.

5-190

STRTOL

(Subroutine)

STRTOL

NAME
strto1, atol, atoi - convert string to integer

SYNOPSIS
long strtol (str, ptr, base)
cbar *str, **ptr;
int base;
long atol (str)
cbar *str;
int atoi (str>
cbar *str;

DESCRIPTION'
strtol returns as a long integer the value represented by the character string pointed to
by str. The string is scanned up to the first character inconsistent with the base.
Leading "white-space" characters (as defined by isspace in ctype) are ignored.
If the value of ptr is not (char **)NULL, a pointer to the character terminating the
scan is returned in the location pointed to by ptr. If no integer can be formed, that
location is set to str, and zero is returned.
If base is positive (and not greater than 36), it is used as the base for conversion.
After an optional leading sign, leading zeros are ignored, and "Ox" or "OX" is ignored if
base is 16.
If base is zero, the string itself determines the base thusly: After an optional leading
sign a leading zero indicates octal conversion, and a leading "Ox" or "OX" hexadecimal
conversion. Otherwise, decimal conversion is used.

Truncation from long to int can, of course, take place upon assignment or by an
explicit cast.

atol(str) is equivalent to strtol(str. (char **)NULL. 10).
atodstr) is equivalent to (int) strtol(str. (char** )NULL. 10).
SEE ALSO
ctype, scanf, strtod (3)

BUGS
Overflow conditions are ignored.

5-191

SWAB

(Subroutine)

SWAB

NAME
swab - swap bytes
SYNOPSIS
void swab (from, to, nbytes>
char *from, *to;
int nybtes;
DESCRIPTION
swab copies nbytes bytes pointed to by from to the array pointed to by to, exchanging
adjacent even and odd bytes. It is useful for carrying binary data between PDP 11
Computers and other machines. nbytes should be even and nonnegative. If nbytes is
odd and positive swab uses nbytes-l instead. If nbytes is negative, swab does nothing.

5-192

INTRO

(File Format)

INTRO

NAME
intra - Introduction to WE 32100 Microprocessor File Formats and Include Files
DESCRIPTION
This section describes the header files and file formats used. C struct declarations
appear where useful. Several of the files apply to the object file format. The others
are useful for assembly language programming or for installation of the various pieces
of the processor. Normally, these files reside in directories under lusr/m32. Specific
installations may alter this directory as described in paths.
Briefly, three main directories contain any files for users. All descriptions of these
files use the names BINDIR, INCDIR, and LIBDIR for the command, include, and
library directories, respectively. They are set at build time.
SEE ALSO
paths

5-193

(File Format)

FILEHDR

FILEHDR

NAME
filehdr - File Header for WE 32100 Microprocessor Object File

SYNOPSIS
#include "filehdr.h"
DESCRIPTION
Every object file begins with a 20-byte header. The following C struct declaration is
used:
struct
{

filehdr
unsigned
unsigned
long
long
long
unsigned
unsigned

short
short

short
short

Cmagic;
Cnscns;
Uimdat;
f_symptr;
Cnsyms;
Copthdr;
fJlags;

1*
1*
1*
1*
1*
1*
1*

magic number *1
number of sections *1
time & date stamp *1
file ptr to symtab *1
# symtab entries *1
sizeof(opt hdr} *1
flags *1

};
f_symptr is the byte offset into the file at which the symbol table can be found. Its
value can be used as the offset in the UNIX System fseek command to position an I/O
stream to the symbol table. The processor uses the optional header for a UNIX
System header, which is always 28 bytes. The only valid processor magic number is:
#define FBOMAGIC 0560
#define RBOMAGIC 0562
The value in Ltimdat is obtained from the time system call. Flag bits currently
defined are:
#define F_RELFLG
#define F _EXEC
#define F_LNNO
#define F_LSYMS
#define F_MINMAL
#define F_VPDATE
#define F_SWABD
#define F_ARI6WR
#define F_AR32WR
#define F_AR32W
#define F_PATCH
#define F_BM32B
SEE AlSO

m32a.out

5-194

00001/* relocation entries stripped *1
00002/* file is executable *1
00004/* line numbers stripped *1
00010/* local symbols stripped *1
00020/* minimal object file *1
00040/* update file, ogen produced *1
00100/* file is "pre-swabbed" *1
00200/* 16 bit DEC host *1
00400/* 32 bit DEC host *1
010001* non-DEC host *1
02000/* "patch"list in opt hdr *1
020001 *file contains WE 32100 code *1

(File Format)

LDFCN

LDFCN

NAME
Idfcn - WE 32100 Microprocessor Object File Access Routines
SYNOPSIS
#include 
#include "INCDIR/fiIehdr.h"
#include "INCDIR/Idfcn.h"
DESCRIPTION
The object file access routines are a collection of functions for reading an object file
that is in common object file form. Although the calling program must know the
detailed structure of the parts of the object file that it processes, the routines
effectively insulate the calling program from knowledge of the overall structure of the
object file.
The interface between the calling program and the object file access routines is based
on the defined type LDFILE, defined as struct Idfile, declared in the header file
Idfcn.h. The primary purpose of this structure is to provide uniform access to both
simple object files and to object files that are members of an archive file.
The function /dopen allocates and initializes the LDFILE structure and returns a
pointer to the structure to the calling program. The fields of the LDFILE structure
may be accessed individually through macros defined in Idfcn.h and contain the
following information:
LDFILE *ldptr;
TYPE (Jdptr)

The file magic number, used to distinguish between archive
members and simple object files.

IOPTROdptr)

The file pointer returned by Jopen and used by the standard
input/output functions.

OFFSETOdptr)

The file address of the beginning of the object file; the offset is
non-zero if the object file is a member of an archive file.

HEADEROdptr) The file header structure of the object file.

5-195

LDFCN

(File Format)

LDFCN

The object file access functions themselves may be divided into four categories:
(1)

Functions that open or close an object file:
ldopen and ldaopen open a processor object file,
ldclose and ldaclose close a processor object file.

(2)

Functions that read header or symbol table information:
ldahread reads the archive header of a member of an archive file,
ldfhread reads the file header of an object file,
ldshread and ldnshread read a section header of an object file,
ldtbread reads a symbol table entry of an object file.
ldgetname retrieves a symbol name from a symbol table entry or from the string table.

(3)

Functions that position an object file at (seek to) the start of the section,
relocation, or line number information for a particular section:
Idohseek seeks to the optional file header of an object file,
Idsseek and Idnsseek seek to a section of an object file,
Idrseek and Idnrseek seek to the relation information for a section
of an object file,
Idlseek and Idnlseek seek to the line number information for a section
of an object file,
Idtbseek seek to the symbol table of an object file.

(4)

The function Idtbindex which returns the index of a particular object file symbol
table entry.

These functions are described in detail on their respective manual pages.
All the functions except Idopen. Idaopen, Idgetname, and Idtbindex return either
SUCCESS or FAILURE, both constants defined in Idfcn.h. Idopen and Idaopen both
return pointers to a LDFILE structure.
MACROS
Additional access to an object file is provided through a set of macros defined in
Idfcn.h. These macros parallel the standard input/output file reading and
manipUlating functions, translating a reference of the LDFILE structure into a
reference to its file descriptor field.

5-196

LDFCN

(File Format)

LDFCN

The following macros are provided:
LDFILE *ldptr;
GETC(\dptr)
FGETC (\pdptr)
GETW(Jdptr)
UNGETC(c,ldptr)
FGETS(s, n, ldptr)
FRED«char *)ptr, sizeof (*ptr), nitems, ldptr)
FSEEK(Jdptr, offset, ptrname)
FTELL (Jdptr)
REWIND (\dptr)
FEOF(\dptr)
FERROR([dptr)
FILENO (Jdptr)
SETBUF(\dptr, bur)
STROFFSET(\dptr)
The STROFFSET macro calculates the address of the string table in an object file.
See the manual pages for the corresponding standard input/output library functions
for details on the use of the rest of these macros.
The program must be loaded with the object file access routine library
LIBDIRlIibld.a.

intra describes LlBDIR and INCDIR.
CAVEATS
The macro FSEEK defined in the header file Idfcn.h translates into a call to the
standard input/output UNIX System function fseek. FSEEK should not be used to
seek from the end of an archive file since the end of an archive file may not be the
same as the end of one of its object file members!
SEE ALSO
ldahread. ldclase. ldfhread. ldlread. ldlseek. ldahseek, ldapen, ldrseek, ldlseek,
ldshread, ldtbindex, ldtbread, ldtbseek, intra, ldfcn. paths

5-197

(File Format)

LINENUM.H

LINENUM.H

NAME
linenum - Line Number Entries in a WE 32100 Microprocessor Object File
SYNOPSIS
#include "linenum.h"
DESCRIPTION
Compilers based on pee generate an entry in the object file for each C source line on
which a breakpoint is possible. Users can then reference line numbers when using the
appropriate software test system. The structure of these line number entries appears
below.
struct
(

lineno
union
(
long
long
Unsigned

short

Uymndx;
tpaddr;
l_addr;
Unno;

};
Numbering starts with one for each function. The initial line number entry for a
function has 1_lnno equal to zero, and the symbol table index of the function's entry is
in I_symndx. Otherwise, 1_lnno is non-zero and Iyaddr is the physical address of the
code for the referenced line. Thus the overall structure is the following:
I_addr
function symtab index
physical address
physical address

1_lnno

function symtab index
physical address
physical address

o

SEE ALSO
m32ee, m32a.out.

5-198

o

line
line

line
line

(File Format)

M32A.OUT

M32A.OUT

NAME
m32a.out - WE 32100 Microprocessor Object File Format
DESCRIPTION
This describes the default output file format from the m32as assembler, and the m32ld
link editor. The resultant file can be executed on the target machine if no errors or
unresolved references were found. In no case is the file given UNIX System execute
permissions because the object code is for the target machine; not the host machine on
which the file was created.

An object file supports user-defined sections and contains extensive information for
symbolic software testing. The overall structure of an object file is given below.
File header.
UNIX System header.
Section I header.
Section n header.
Section 1 data.
Section n data.
Section I relocation.
Section n relocation.
Section I line numbers.
Section n line numbers.
Symbol table.
See filehdr, scnhdr, reloc, linenum, and syms for descriptions of the individual parts.
Every section created by m32as contains a multiple of four number of bytes; directives
to m32ld can create a section with an odd number of bytes.
A set of functions exist to manipulate object files. See Idfcn and its associated
references for more information.
SEE ALSO
m32as, m321d, Idfcn, filehdr, linenum, reloc, schhdr, syms.

5-199

PATHS

(File Format)

PATHS

NAME
paths - Directory Path Names for the WE 32100 Microprocessor
SYNOPSIS
#include "paths.h"
DESCRIPTION
Users may install the SGP under four separate directories: bin for the commands, lib
for the libraries, include for the header files, and man for manual pages. After the
SGP is installed, the directories should not be moved. Users must specify the
installation directories by using the "pathedit" command before installation. "Pathedit"
is described in the README file delivered with the SGP. The following are among
the modified definitions:
#define
#define
#define
#define

BINDIR
INCDIR
LIBDIR
MANDIR

"/usr/m32/bin"
"/usr/m32/include"
"/usr/m32/lib"
"/usr/m32/man"

Additionally, users may specify a directory that processor tools should use for
temporary files.
#define

5-200

TMPDIR

"/usrltmp"

RELOC

(File Format)

RELOC

NAME
reloc - Relocation Information for a WE 32100 Microprocessor Object File
SYNOPSIS
#incIude "reloc.h"
DESCRIPTION
Object files have one relocation entry for each relocatable reference in the text or
data. If relocation information is present, it is in the following format:
struct
(

);
#define
#define
#define

reloc
long
long
short

r_vaddr ;
r_symndx;
r_type ;

R ABS
R DIR32
R DIR32S

0
06
012

/* (virtual) address of reference */
/* index into symbol table */
/* relocation type */

As the link editor reads each input section and performs relocation, the relocation
entries are read. They direct how references found within the input section are
treated.
R ABS

The reference is absolute, and no relocation is necessary.
The entry is ignored.

R DIR32

A direct, 32·bit reference to a symbol's virtual address.

R DIR32S

A direct, 32-bit reference to a symbol's virtual address.
The 32-bit value is stored in reverse order in the object file.

Other relocation types will be defined as they are needed.
Relocation entries are generated automatically by the compiler and the assembler, and
automatically utilized by the link editor. A link editor option exists for removing the
relocation entries from an object file.
SEE ALSO
m321d, m32strip, m32a.out, syms.

5-201

(File Format)

SCNHDR

SCNHDR

NAME

scnhdr - Section Header for a WE 32100 Microprocessor Object File
SYNOPSIS

#include "scnhdr.h"
DESCRIPTION
Every object file has a table of section headers to specify the layout of the data within
the file. Each section within an object file has its own header. The C structure
appears below.

struct
{

scnhdr
s_name[81 ;
char
long
sJladdr;
long
s_vaddr;
long
s_size ;
long
s_scnptr ;
long
sJelptr;
long
sJnnoptr;
unsigned short s_nreloc;
unsigned short s_nlnno;
long
sJlag;

/* physical address */
/* virtual address */
/* section size */
/* file ptr to raw data */
/* file ptr to relocation */
/* file ptr to line numbers */
/* # reloc entries */ /
/* # line number entries */
/* flags */

};
File pointers are byte offsets into the file; they can be used as the offset in a call to
the UNIX System command fseek. If a section is initialized, the file contains the
actual bytes. An uninitialized section is somewhat different. It has a size, symbols
defined in it, and symbols that refer to it. But it can have no relocation entries, line
numbers, or data. Consequently, an uninitialized section has no raw data in the object
file, and the values for s_scnptr, sJelptr, sJnnoptr, s_nreloc, and s_nlnno are zero.
SEE ALSO
m321d, m32a.out.

5-202

(File Format)

SYMS

SYMS

NAME
syms - WE 32100 Microprocessor Object File Symbol Table Format
SYNOPSIS
#include "syms.h"
DESCRIPTION
Processor object files contain information to support symbolic software testing. Line
number entries, linenum, and extensive symbolic information permit testing at the C
source level. The symbol table for every object file is organized as:

File name 1.
Function 1.
Local symbols for function 1.
Function 2.
Local symbols for function 2.
Static externs for file 1.
File name 2.
Function 1.
Local symbols for function 1.
Function 2.
Local symbols for function 2.
Static externs for file 2.
Defined global symbols.
Undefined global symbols.
The entry for a symbol is a fixed-length structure. The members of the structure hold
the name (null padded), its value, and other information. The C structure is:
#define
#define

SYMNMLEN 8
FILNMLEN 14

struct
{
union
{

syment

char _n_name[SYMNMLEN);
struct
{

/* symbol name */
long JI_zeros;
long _n_offset;

/* ==OL when in
string table */
/* location of
name in table */

5-203

(File Format)

SYMS

SYMS

} n n;

char- *_n_nptr[21;

/* allows overlaying */

unsigned long
short
unsigned short
char
char

n_value ;/* value of symbol */
n_scnum ;/* section number */
n_type ;/* type and derived type */
n_sclass ;/* storage class */
n_numaux ;/* number of aux entries */

};
#define
#define
#define
#define

n_name _n._n_name
n_zeros _n._n_n._n_zeros
n offset n. n n. n offset
n=nptr _~._~_~ptai1

Some symbols require more information than a single entry; they are followed by
auxiliary entries that are the same size as a symbol entry. The format is:
union auxent
{
struct
{
long
union
{
struct
{
unsigned short xJnno;
unsigned short x_size;
}xJnsz;
long

xJsize;

}x_mise;
union
{
struct
{
long xJnnoptr;
long x_endndx;
} xJcn;
struct
{

unsigned short

5-204

unsigned short x_dimen[DIMNUM1;
x-ary;
xJcnary;
iUvndx;

SYMS

(File Format)

SYMS

struct
{
char
xJile;

xJname[FILNMLEN);

struct
{
long x_scnlen;
unsigned short
unsigned short

x_nreloc:
x nlinno:

struct
{
long x_tvfill;
unsigned short
unsigned short
x_tv;

x tvlen;
x=tvran[2);

};
Indices of symbol table entries begin at zero.
SEE ALSO

m32a.out, linenum.

5-205

Glossary and
Acronyms

GLOSSARY

Absolute deferred mode - An address
mode that uses an address embedded in
the operand to locate a pointer to data.
Absolute mode - An address mode that
uses an address embedded in the
operand to locate data.
Address arithmetic unit (AAU) - Fetch
unit element that calculates 32-bit
addresses.
Argument pointer (AP) - User register
that points to the beginning location in
the stack where a set of arguments for
a function has been pushed.
Arithmetic logic unit (ALU) - On-chip
unit that performs arithmetic
operations on 32-bit data.
Assert - To drive a signal to its active
state.
Bit field - A sequence of I to 32 bits
contained in a base word. The field is
specified by the address of its base
word, a bit offset, and a width.

Bit offset - Identifies the starting bit of
the field in its base word. The offset
ranges from 0 to 31.
Bus interface control - Provides all the
strobes and control signals necessary to
implement the interface with
peripherals.
Byte - An 8-bit quantity that may appear
at any address in memory.
Cache - A high-speed memory filled at a
lower speed from main memory. Used
to reduce memory access time.
Cache disable (CD) - A field in the PSW
that enables and disables the
instruction cache.
Cache flush disable (CFD) - A field in
the processor status word (PSW) that
enables and disables instruction cache
flushing (emptying of the cache's
contents) when a new process is loaded

via the XSWITCH_TWO
micro sequence.
Condition codes (NZVC) - The flags in
this 4-bit field reflect the resulting
status of the most recent instruction
execution which affects them. The
four flags are negative (N), zero (Z),
overflow (V), and carry (CL
Coprocessor - A support processor that
operates synchronously with the CPU
to provide greater throughput in
arithmetic or I/O functions.
Current execution level (CM) - A 2-bit
field in the PSW that represents the
current execution level. The four
execution levels are kernel, executive,
supervisor, and user.
Dedicated registers - Seven registers
(r9-rl5) that have specific,
predetermined functions.
Displacement mode - An address mode
that uses a register and an offset, both
embedded in the operand, added
together to form the address of data.
Displacement deferred mode - An address
mode that uses a register and an offset,
both embedded in the operand, added
together to form the address of a
pointer to data.
Enable overflow trap (OE) - A field in
the PSW that enables overflow traps.
Exception type (ET) - A 2-bit field in the
PSW that indicates exceptions
generated during operations. The four
types of exceptions are normal, stack,
process, and reset.
Exceptional conditions - Events other
than interrupts and reset requests that
may interrupt the execution of a
program. The four classes of
exceptional conditions are normal
exceptions, stack exceptions, process
exceptions, and reset exceptions.

GLOSSARY

Execute unit - The elements in this unit
perform all arithmetic and logic
operations, perform all shift and all
rotate operations, and compute the
condition flags.
Expanded-operand-type mode - An
address mode that changes the type of
the instruction for an operand and
those that follow it in the instruction.
It does not affect immediate operands.
Faults - Error conditions that are
detected outside the microprocessor
and conveyed to the microprocessor
over its fault input FAULT.
Fetch unit - The elements in this unit
handle the instruction stream and
perform memory-based operand
accesses.
Frame pointer (FP) - User register that
points to the beginning location in the
stack of a function's local variables.
Full interrupt - Interrupt whose handling
routine implements a process switch to
the interrupt's handler. All interrupts
are handled via the full interrupt
sequence if the QIE bit in the PSW is
cleared (0).
General-purpose registers - Nine registers
(rO-r8) that may be used for highspeed accumulation, for addressing, or
for temporary data storage.

reducing external memory reads for
instruction fetches.
Instruction queue - An 8-byte, first-infirst-out (FIFO) on-chip queue that
stores prefetched instructions.
Internal state code (ISC) - A 4-bit field
in the PSW that distinguishes between
exceptions of the same exception type.
Interrupt - A means by which external
devices may request service by the
microprocessor.
Interrupt priority level (IpL) - A 4-bit
field in the PSW that represents the
current interrupt priority level.
Interrupt stack pointer (ISP) - User
register that contains the 32-bit
memory address of the top of the
interrupt stack.
Main controller - The microprocessor's
central control unit. It is responsible
for acquiring and decoding instruction
opcodes and directing the action of the
fetch and execute controllers.
Memory management unit (MMU) - A
software or hardware unit, or
combination of both, that translates
virtual addresses into physical
addresses and verifies access
authorization. The WE 32101
Memory Management Unit provides
this function for the CPU.

Halfword - 16-bit quantity that may
appear at any address in memory that
is divisible by 2.

Negate - To drive a signal to its inactive
state.

Immediate and displacement extractor Provides address calculation data to the
address arithmetic unit (AAU) for its
use in calculating 32-bit addresses.

Nonmaskable interrupt - Type of
interrupt that interrupts the
microprocessor regardless of the
priority level in the IPL field of the
PSW.

Immediate mode - An address mode
where the operand contains actual data
to be used by instruction.
Instruction cache - A 64- by 32-bit
on-chip cache used to increase the
microprocessor's performance by

Normal exceptions - A class of
exceptional conditions generated by the
microprocessor when it detects a
condition such as a trap, invalid
opcode, or illegal operation.

GLOSSARY

Operand descriptor - First byte of an
operand defining which address mode
and register the operand uses.
Pipe lining - Overlapping the execution of
instructions to increase the
microprocessor's performance.
Prefetch - A technique where the CPU
fetches an instruction prior to the
completion of previous instructions.
Previous execution level (PM) - A 2-bit
field in the PSW that represents the
previous execution level. The four
execution levels are kernel, executive,
supervisor, and user.
Privileged instruction - An operating
system group instruction that can
execute only in kernel execution level.
Process control block (PCB) - A process
data structure in external memory that
saves the context of a process when the
process is not running. This context
consists of the initial and current
contents of control registers (PSW, PC,
and SP), the last contents of registers
rO through riO, boundaries for an
execution stack, and memory
specifications for the process.
Process control block pointer (PCBP) User register that points to the starting
address of the process control block for
the current process.
Process exceptions - A class of
exceptional conditions that may occur
during a process switch.
Processor status word (PSW) - User
register that contains status
information about the microprocessor
and the current process.
Program counter (PC) - User register
that contains the 32-bit memory
address of the instruction being
executed or, upon completion, contains
the starting address of the next
instruction to be executed.

Quick interrupt - An interrupt whose
handling routine pushes the old PSW
and PC on the stack and fetches a new
PSW and PC that correspond to the
interrupt's handler. For this reason the
quick interrupt handling routine
requires less time than a full interrupt
which implements a process switch to
the interrupt's handler. Interrupts are
handled via the quick-interrupt
sequence if the QIE bit in the PSW is
set (1).
Quick-interrupt enable (QIE) - A field in
the PSW that enables and disables the
quick-interrupt facility.
Read interlocked operation - An operation
which consists of a memory fetch (read
access), one or more internal
microprocessor operations, and then a
write access to the same memory
location.
Register deferred mode - An address
mode that uses a register name,
embedded in an operand, which
contains a pointer to data to be used
by the instruction.
Register mode - An address mode that
uses a register name, embedded in an
operand, which contains data to be
used by the instruction.
Register-initial context (RI) - A 2-bit
field in the PSW that controls the
microprocessor context switching
strategy.
Reset exceptions - A class of exceptional
conditions that is triggered by an error
condition in accessing critical system
data.
Scratch registers - User registers rO, rl,
and r2. These three registers are used
by the C compiler to store temporary
values and also return specific values
during procedure calls.

GLOSSARY

Short offset mode - An address mode that
uses an offset embedded in an operand.
The offset is added to the frame
pointer or argument pointer to form
the address of data.
Sign extension - Automatic extension of a
byte or halfword value to 32 bits by
filling the high-order bits with the
value of the sign bit.
Stack exceptions - A class of exceptional
conditions that may occur during a
process switch or a GATE sequence.
Stack pointer (SP) - User register that
contains the current 32-bit address of
the top of the execution stack; i.e., the
memory address of the next item to be
stored on (pushed onto) the stack or
the last item retrieved (popped) from
the stack.
Trace enable (TE) - A field in the PSW
that enables the trace function.
Trace mask (TM) - A field in the PSW
that enables masking of a trace trap.
Trace mechanism - An interpretive
diagnostic trace trap using two bits in
the PSW, trace enable (TE) and trace
mask (TM), to analyze each executed
instruction.
User registers - The sixteen 32-bit
registers (rO-rI5) that are available to
the user. The user registers consist of
nine general purpose registers (rO-r8)
and seven dedicated registers
(r9-rI5).
Vestigial cycle - A clock cycle that
follows every access and is provided to
allow enough time for a memory
management unit to release the shared
address bus.
Wait-state - Idle periods that may be
generated during a bus transaction to
allow slow peripherals to handshake
with the microprocessor.

Width - The size of a bit field. Width
plus one is the number of bits in the
field. The width ranges from 0 to 31.
Word - A 32-bit quantity that may
appear at any address divisible by 4.
Working registers - Registers that are
used exclusively by the microprocessor
and are not user-accessible.
Zero extension - Automatically extending
a byte or halfword value to 32 bits by
filling the high-order bits with zeros.
3-state - To place an input in a highimpedance state.

ACRONYMS

AAU - Address arithmetic unit

N - Condition flag bit negative

ALU - Arithmetic logic unit

NOP - No operation

AP - Argument pointer

OE - Overflow enable

BPT - Breakpoint trap

PC - Program counter

BSS - Bounded static storage

PCB - Process control block

C - Condition flag bit carry

PCBP - Process control block pointer

CALLPS - Call process

PD - Page descriptors

CD - Cache disable

PDT - Page descriptor table

CFD - Cache flush disable

PM - Previous execution level

CM - Current execution level

POT - Page offset field

CMOS - Complimentary metal-oxide

PPC - Prefetch counter

semiconductor

PSL - Page select field

COFF - Common object file format

PSW - Processor status word

COPY - "Copy" section

QIE - Quick-interrupt enable

CPU - Central processing unit

RAM - Random access read/write memory

CR - Configuration register

RI - Register-initial

DMA - Direct memory access

ROM - Read-only memory

DSECT - "Dummy" section

rrrr - Register field

EPROM - Eraseable programmable ROM

RSB - Return from subroutine

ET - Exception type

SD - Segment descriptors

FL T AR - Fault address register

SDP - Software demand paging

FL TCR - Fault code register

SDT - Segment descriptor table

FP - Frame pointer

SGP - Software generation programs

I/O - Input/output

SID - Section ID field

IPL - Interrupt priority level

SOT - Segment offset field

ISC - Internal state code

SP - Stack pointer

ISP - Interrupt stack pointer

SSL - Segment select field

LIFO - Last-in-first-out

TE - Trace enable

LRU - Least recently used

TM - Trace mask

LSB - Least significant bit

TT - Trace trap

mmmm - Mode field

TTL - Transistor-transistor logic

MMU - Memory management unit

V - Condition flag bit overflow

MSB - Most significant bit

Z - Condition flag bit zero

Index

INDEX

A
AAU. See Address arithmetic unit
ABSOLUTE, 5-24
Absolute
address modes, 3-10
binary file, 5-3, See also Object
file format
deferred, 3-11
Access protection, 4-43
Accessing
library, 5-117
macros, 5-121
Address
and data bus, 2-1
assigned to symbols, 5-53
assigning of, 5-53
fault, 2-30
mode absolute, 3-10
mode absolute deferred, 3-11
modes, 3-6
mode syntax, 3-8
physical, 5-56, 5-78
printing of computed, 5-108
range of target processor, 5-53
signals, 2-75
virtual, 4-36, 5-56, 5-78
Address arithmetic unit (AAU), 2-1
Addressing modes
absolute, 3-10
absolute deferred, 3-10
argument pointer (AP) short offset, 3-15
byte displacement, 3-11
byte displacement deferred, 3-12
byte immediate, 3-16
displacement, 3-11
expanded operand type, 3-20
frame pointer (FP) short offset, 3-15
halfword displacement, 3-12
halfword displacement deferred, 3-13
halfword immediate, 3-1 7
immediate, 3-16
negative literal, 3-18
positive literal, 3-18
register, 3-19
register deferred, 3-19
short offset mode, 3-15

syntax, 3-8
word displacement, 3-14
word displacement deferred, 3-14
word immediate, 3-17
.align, 5-35
Alignment
data, 2-10
fault, 2-10, 2-68
fault bus activity, 2-56
fault properties, 2-68
output section, 5-57
pseudo operation, 5-35
Allocating sections, 5-61, 5-65
Allocation algorithm, 5-65
Allocation errors, 5-70
ALU. See Arithmetic logic unit
a.out header, 5-80
Arbitration signals, 2-48
Architecture, 1-2, Chapt. 2
overview, 2-1
pipelining, 2-1, 2-57
Archive
distinguishing members from object
files, 5-118
magic number, 5-118
maintainer, m32ar, 5-103
opening and closing files, 5-118
ordering of libraries, m3210rder, 5-114
reading of header, 5-120
stripping information from
libraries, m32strip, 5-116
use of libraries, 5-63, 5-121, 5-117
Argument macros, 5-19
Argument pointer (AP), 2-4, 3-8, 5-38
short offset mode, 3-15
Arithmetic instructions, 3-25
Arithmetic logic unit (ALU), 2-2
execute controller, 2-1
Arrays, symbol table entry, 5-99
asm, assembler escape, 5-7
Assembled files, 5-15
Assembler, 5-13
directives, 5-31
escapes, 5-7
example of programming, 5-43
language, 5-22
m32as, 5-14

INDEX

m32as and registers, 5-26
m32as and sections, 5-15
m32as diagnostics, 5-15
m32as location counter, 5-15
m32as macro processing facilities, 5-16
m32as options, 5-14
m32as use; 5-13
predefined interface macros,
M4 processor, 5-16
restrictions on macros, 5-19
syntax, 5-14
Assembly language, 5-22
applications requiring, 5-13
descriptions, 5-22 thru 5-43
function calling, 5-37
statements, 5-22
symbols, 3-36, 5-23
Asserted signal, 2-13, 2-70
Assigning of structures, 5-9
Assigning of values and
types to symbols, 5-25
Assignment
pseudo operation, 5-33
statements, 5-53
to dot, 5-34
Asynchronous read, 2-15
Asynchronous write, 2-18
Auto-vector interrupt, 2-45, 4-24
Auxiliary table entries, 5-97

B
Beginning of blocks
and functions, 5-100
Bit field
base word, 2-8
defined, 2-8, 3-1
instructions, 3-1
offset, 2-8, 3-1
width, 2-8, 3-1
Blockfetch operation, 2-25
Borrow, 3-23
Branch, 3-43 thru 3-60, See also
Program control instructions
BSS,5-24
.bss section, 5-15, 5-31, 5-32, 5-82

finding size of, 5-82
grouping together, 5-58
section header, 5-82
initialized, 5-61
Bus
address, 2-1, 2-12, 2-75
arbitration, 2-49
data, 2-1, 2-75
exceptions, 2-30
exceptions, retry and relinquish, 2-34
operation, Chapt. 2
request, 2-51
.byte, 5-32, 5-35
Byte
data, 2-8, 3-1
descriptor, 3-8
displacement deferred mode, 3-12
displacement mode, 3-11
immediate mode, 3-16
ordering and m32conv, 5-106

c
Carry, 3-23
C language, 5-1, 5-6
calling sequence, 5-37
examining object files from, 5-117
features, 5-1, 5-6
flag, 5-79
macros, 5-16
preprocessor, 5-4
stack frame, 5-37
Cache
instruction, 2-1, 2-6
instruction cache flush, 2-7
instruction cache hit, 2-55
memory, 4-42
MMU descriptor, flushing, 4-41
Call process instruction, 4-16, 4-46
Central processing unit (CPU), 1-2
architecture, Chapt. 2
instructions, Chapt. 3
operation, Chapt. 2
register syntax, 3-3, 3-9, 5-26
registers, 2-3, 3-3, 5-26
Changing entry point, 5-62

INDEX

Classes, CPU output, 2-84
Clock
input, 2-11, 2-83
state, 2-12
Closing object files, 5-118
Common object file format (COFF), 5-77
Compiler, 5-3
m32cc,5-3
options, 5-4
register usage, 5-6
Complete structure and union member
reference qualifications, 5-11
Compress utility, m32cprs, 5-107
Condition flags, 2-4, 3-1, 3-22, 3-23, 3-34
Constants, 5-25
Context switching strategy, 4-17
Control-register save area, 4-7
Controllers
main, 2-1
executive, 2-1
fetch, 2-1
Coprocessor, 2-58
broadcast, 2-58
data write, 2-65
instructions, 3-32
operand fetch, 2-63
status fetch, 2-64
Corrupt input files, 5-68
Creating and defining symbols, 5-60
Creating holes within
output sections, 5-59
Current execution level (cm),
2-5,4-11

D
.data, 5-31, 5-32
Data
alignment fault properties, 2-68
embedded in operands, 3-6
generation pseudo operations, 5-35
in memory, 2-10
transfer instructions, 3-23
types, 2-8, 3-1
Deferred address modes, 3-6
Diagnostics, See Error

Direct memory access (DMA), 2-51
Disassembler
m32dis, 5-108
m32dis error messages, 5-110
options, 5-108
Disassembly, 5-27, 5-44
Displacement modes, 3-11
DMA, See Direct Memory Access
DSECT, COPY and NLOAD sections
output file blocking, 5-67

E
Efficient mapping strategies, 4-41
Electrical
requirements, 2-84
specifications, 2-86
End
of blocks and functions, 5-100
of structures, 5-99
Entry point, 4-14
Enumerations
constants, 5-7
enumeration-tag, 5-7
Epilogue sections, 5-43
Error
messages, 5-68
messages, m32as, 5-15
messages, m32conv, 5-107
messages, m32cprs, 5-107
messages, m32dis, 5-110
messages, m32dump, 5-113
messages, m321d, 5-68
messages, m32list, 5-113
messages, m32nm, 5-115
messages, m32strip, 5-116
Exception
breakpoint trap, 2-67, 4-33
conditions, 2-66, 4-30
defined, 2-66, 4-30
external memory, 2-68, 4-33
gate vector, 2-68, 4-36
handler, 4-30
illegal level change, 2-68, 4-33
illegal opcode, 2-68, 4-33
integer overflow, 2-67, 4-33

INDEX

integer zerodivide, 2-68, 4-33
interrupt-stack fault, 2-66, 4-36
invalid descriptor, 2-68, 4-33
new-PCB fault, 2-66, 4-35
normal, 2-67, 4-32
old-PCB fault, 2-66, 4-35
on-normal exception, 2-67, 4-32, 4-65
on-process exception, 2-67, 4-35, 4-69
on-reset exception, 2-67, 4-35, 4-71
on-stack exception, 2-67, 4-33, 4-67
privileged-opcode, 2-68, 4-33
privileged-register, 2-68, 4-33
process, 2-67, 4-35
reserved-data-type, 2-68, 4-33
reserved opcode, 2-68, 4-33
reset, 2-67, 4-35
severity, levels of, 2-67, 4-30
stack, 2-67, 4-33
system-data, 2-66, 4-36
trace trap, 2-68, 4-33
Executable instructions, assembly
language, 5-27
Execution
modes, levels, 2-5,4-1,4-5,4-11
privilege, 4-5
stack, 4-5
Executive mode (level 1),4-1
Expanded -operand
type mode, 3-20
Explicit process switch, 4-3, 4-16

F
Fault,
blockfetch, 2-37
defined, 2-30
exception mechanism, 4-30, 2-68
memory, 2-30, 2-68, 4-41
stack fault, 4-33
Features of the operating system, 4-1
Fields in the PSW, 2-4, 4-10
File
a.out header, 5-80
address, 5-118
contents of header, 5-79
conversion, 5-105

flags, 5-79
header, 5-79
magic number, 5-118
name pseudo operation, 5-37
names, auxiliary table, 5-98
pointer, 5-118
reading of header, 5-120
sections, 5-82
seeking to header, 5-120
specifications, 5-56
Flexnames, 5-7
Flushing
instruction cache, 2-7
MMU descriptor cache, 4-41
Frame pointer (FP), 2-4, 3-8
short offset mode, 3-15
Full interrupts, 2-42, 4-29
Full-interrupt handler's PCB, 4-25
Function
accessing, 5-118
auxiliary table entries, 5-100
call stack frame, 5-41
called, 5-39
calling, 5-39
calling sequence, 5-37
index return, 5-120
interface macros, 5-17
names, listing, 5-108
returning structure values, 5-9
saving no registers, 5-44
symbols for, 5-84
to close, 5-118
to open, 5-118
to read, 5-120
to return aggregate values, 5-9
to return symbol index, 5-120
to seek, 5-120

G
Gate, 4-10
instruction, 4-14, 4-57
mechanism, 4-13
return from, 4-16
Gate-PCB fault, 4-16, 4-35
Gate-vector fault, 4-15, 4-36

INDEX

General-purpose library, 5-121
General-purpose registers, 2-4, 3-3, 5-26
General-register save area, 4-7

H
Halfword
boundary, 2-10
data, 2-8, 3-1
displacement deferred mode, 3-13
displacement mode, 3-12
immediate mode, 3-17
Handling-routine tables, 4-13
Header
file Odfcn), 5-117
reading of information, 5-120
Holes in physical memory, 5-64
Host computers for SGP, 5-2

I bit, 4-17
ifiles, 5-48
Immediate modes, 3-16
Implicit process switch, 4-3, 4-23, 4-28,
4-34, 4-35, 4-36
Include files, 5-118
Indirect segment descriptors, 4-42
Initial context for a process, 4-9, 4-17
Initialize
section holes, 5-61
memory management unit, 4-40
In-line procedure expansion, 5-13
Inner blocks, 5-86
Input specifications, 2-86
Instruction format, 3-6
Instruction set, 1-4, 3-1, 5-13, 5-38
descri ptions, 3-33
functional groups, 3-23
listings, 3-33
operating system, 4-2, 4-43
summary by function, 3-126
summary by mnemonic, 3-132
summary by opcode, 3-136
Instruction cache hit, 2-55

Interface macros, 5-17
Interlocked operation, read, 2-22
Internal errors, 5-70
Internal reset, 2-52
Internal State Code (ISC), 2-5, 2-66,
4-11,4-32 thru 4-36
Interrupt
acknowledge, 2-42, 4-24
auto-vector, 2-45, 4-24
handler model, 4-23
handler's PCB, 4-25
mechanism, 4-24
nonmaskable, 2-45
on-interrupt microsequence, 4-28, 4-73
request and acknowledge codes, 2-44
returning from, 4-29
quick interrupt, 2-48, 4-29
signals, 2-79
stack, 4-26
stack pointer (ISP), 2-7, 4-26
stack and ISP, 4-26
structure, 4-23
vector table, 4-27

li\:
Kernel mode Clevel 0), 4-1

L
Ldaclose, 5-118
Ldaopen, 5-117
Ldclose, 5-118
Ldfcn. See Header file, 5-117
Ldfile structure, 5-117
Ldopen, 5-117
Ldtbindex, 5-117
Least significant bit (LSB), 2-8, 3-1
Least significant byte, 5-30
Levels of exception severity, 4-30
Library,
access routines, 5-117
archive file, 5-63
functions and macros, 5-118
general purpose, 5-121

INDEX

routines, 5-102, 5-122
Line
listing of numbers, 5-113
number pseudo operation, 5-37
numbers, 5-84
numbers, stripping from an object
file, 5-116
seeking numbers, 5-118, 5-120
Link editing in one pass, 5-102
Link editor, m321d, 5-48
assignment statements, 5-53
command language, 5-51
command line options, 5-50
error messages, 5-68
ifiles, 5-48
initialization of .bss, 5-61
library order and m321d, 5-114
memory configurations, 5-53
notes on m32ld use, 5-62
options to m321d, 5-50
reserved names for m321d, 5-52
section definition directives, 5-55
List utility, m32list, 5-113
Listing
assembly language programs,
m32dis, 5-108
instruction set, 3-33
&lit defined, 3-8, 3-18
Load specified address section, 5-57
Location counter, 5-25
Logical instructions, 3-26

M
m32a.out. See Object file format
m32ar. See Archive
m32as. See Assembler
m32cc. See Compiler
m32convert. See Object file converter
m32cprs. See Compress utility
m32dis. See Disassembler
m32dump. See Object file dumper
m321d. See Link editor
m32list. See List utility
m32lorder. See Object file order
m32man. See On-line documentation

m32nm. See Name list utility
m32size. See Object file section size
m32strip. See Strip utility
Machine independent instruction set, 5-45
Macro processing facilities, M4, 5-16
reserved words, 5-21
Macros
accessing, object files, 5-121
assembler, 5-17
Main controller, 2-1
Memory
link editor configurations, 5-53
management, 2-10, 4-36
management, virtual, 4-4, 4-36
options, 4-37, 2-10
PCB specifications, 4-9
translation, 4-37
Memory management unit
(MMU), 2-10, 4-36
exceptions, 4-41
initialized, 4-40
interactions, 4-40
mapping strategies, 4-41
peripheral mode, 4-40
transla tion
continuous segment, 4-37
paged segment, 4-37
Microprocessor
architecture, 2-1, 4-1
bus arbitration, 2-48
bus exceptions, 2-30
characteristics, Cha pt. 2
coprocessor interface, 2-58
data handling, 2-8
exceptional conditions, 2-66
features of the operating systems, 4-1
operating requirements, 2-83
output classes, 2-84
outputs during DMA, 2-51
outputs during reset, 2-53
pin assignments, 2-70
registers, 2-3, 3-3
signals for interfacing, 2-75 thru 2-83
specifications, 2-83
trace mechanism, 2-69
Microsequence, 4-2, 4-64
on-interrupt, 4-28, 4-73

INDEX

on-normal, 4-32, 4-65
on-process, 4-35, 4-69
on-reset, 4-35, 4-71
on-stack, 4-33, 4-67
XSWITCH, 4-21, 4-22, 4-28, 4-77
Misuse
expressions, 5-72
link editor directives, 5-71
options, 5-72
mmmm field (address mode
field), 3-10
Mnemonic, 3-1, 3-6
Modifier options, 5-111
Most significant bit, 2-8, 3-1

N
Name list utility, m32nm, 5-114
Names related to structures, unions
and enumerations, 5-100
Negated signal, 2-13, 2-70
Negative literal mode, 3-18
New flexibility for member
names, 5-10
New-PCB fault, 2-66,4-35
Nonmaskable interrupt, 2-45
NonpriviJeged instructions, 4-56
Nonrelocatable input files, 5-67
Nonunique structure member
names, 5-9
Nonunique tag names allowed, 5-12
Normal exceptions, 4-32

o
Object file
archive, m32ar, 5-103
access functions, 5-118
access routines, 5-117
conversion, m32conv, 5-105
converter, m32convert, 5-105
dumper, m32dump, 5-111
format, features of, 5-77
opening and closing, 5-118

order, m3210rder, 5-114
relocatable, 5-83
section headers, 5-81
section size, m32size, 5-116
sections of, 5-82
stripping information from,
m32strip, 5-116
symbols, 5-84
symbol table, 5-114
Object traps, 4-42
Old-PCB fault, 2-66, 4-35
On-interrupt microsequence, 4-28, 4-73
On-line documentation,
m32man, 5-103, 5-123
On-normal exception, 2-67, 4-32, 4-65
On-process exception, 2-67, 4-35, 4-69
On-reset exception, 2-67, 4-35, 4-71
On-stack exception, 2-67, 4-33,4-67
Opcodes, 3-34, 3-136
Operand, 3-6, 5-28
See also Addressing modes
data embedded in, 3-6
descriptor, 3-6, 5-30
in instruction format, 3-6
syntax, 3-8, 5-28
Operating system
considerations, Chapt. 4
features, 4-1
instructions, 4-2, 4-43
support, 1-4, Chapt. 4
Operation
read,2-12
write, 2-12
Operator precedence, 5-52
opnd. See Operand
Optimization, 5-4, 5-43
Optimizer, 5-4
Optional header, 5-80
Output
classes, 2-84
errors in m321d, 5-69
file blocking, 5-68
file, redirection from
m32conv, 5-106
sections, 5-55, 5-65
specifications, 2-86

INDEX

p

R

PC. See Program counter
PCB. See Process control block
PCBP. See Process control block pointer
Peripheral mode, 4-40
Physical
address, 2-10, 4-36
memory, 2-10, 4-13, 4-36
Pin assignments, 2-70
Pipelining, 2-1, 2-57
Pointer table, 4-13
Positive literal mode, 3-18
Predefined macros, use of, 5-20
Previous execution level (PM), 2-5, 4-11
Privileged
execution modes, 4-1, 4-5
instructions, 4-2, 4-44
opcode, exception, 2-68
register, 2-3, 3-4
register exception, 2-68
Procedure transfer, 3-28
Process,
defined, 4-1
exceptions, 2-67, 4-35
structure of a, 4-4
switching, 4-1, 4-16
Process control block (PCB), 4-4, 4-6
Process control block pointer
(PCBP), 2-7, 4-5
locations, 4-6, 4-7
register, 3-3, 4-5
Processor. See Central processing unit
Processor status word (PSW), 2-4, 4-10
fields, 2-5, 4-11
register, 2-3, 3-3
Program control instructions, 3-28
Program counter (PC), 2-8, 3-4
Programming example, assembly, 5-43
Prologue sequence, 5-17, 5-43
Pseudo operations, 5-31

R bit, 4-17
Register, 2-3, 3-3
as an operand, 3-3
assembler syntax, 3-4
compiler usage, 5-6
modes, 3-19
reading from a, 3-6
save area, 3-28, 5-38
writing to a, 3-6
Registers defined, 5-26
Relinquish and retry, 2-34
Relinquish and retry of blockfetch, 2-42
Relocatable symbols, 5-83
Relocation, 5-83
entries, 5-83
seeking entries, 5-118, 5-120
stripping entries, 5-116
types, 5-83
Removing duplicate structures, 5-107
Reserved
data type exception, 2-68, 4-33
opcode, exception, 2-68, 4-33
symbol names, 5-52, 5-21
Reset, 2-52
exceptions, 4-35, 4-71, 2-66
internal, 2-52
sequence, 2-54
signal, 2-53
states, 2-53
Restrictions, macros, 5-19
Retry, 2-34
Return
from gate, 4-16, 4-62
from interrupt, 4-29
instruction set commands, 3-94
to process, 4-22, 4-52
rrrr field (register field), 3-10
Routines
general purpose library, 5-122
printf and scanf, 5-123

Q
Quick interrupt, 2-48, 4-29, 4-23

INDEX

s
Save-context area, 4-7
Saved context for a process, 4-9, 4-17
Scratch register ~acros, 5-19
Second entry point, 4-15
Section
control pseudo operations, 5-31
definition directives, 5-55
definition of, 5-78
headers, 5-81
numbers, 5-93
Sections, See also .bss section,
.data section, and .text section
aligning, 5-57
allocating into memory, 5-61
assigning symbols, 5-60
auxiliary table entry for, 5-98
binding, 5-56
creating holes in, 5-59
grouping of, 5-58
initialize, 5-61
loading, 5-57
output, 5-56
seeking to, 5-ll8, 5-120
user-defined, 5-55
SECTIONS directives,
5-55 thru 5-68, 5-82
Seeking file headers, 5-79, 5-120
Selective inclusion, 5-63
Sending object files, 5-106
Shell commands, and utilities, 5-102
Sign and zero extension, 3-3
Signal sampling points, 2-11
Software Generation Programs
(SGP), 1-5, Chapt. 5
distinctive features, 5-1
SP. See Stack pointer
Space restraints, 5-73
Special symbols, 5-84
Stack
and miscellaneous
instructions, 3-32, 3-l31
bounds, 4-6, 4-33
exceptions, 2-67, 4-33, 4-67
execution, 4-5
fault, 4-33

frame, 3-28, 5-38
frame macros, 5-19
interrupt, 4-6, 4-26
Stack-bound, 4-8
exception, 4-33
fault, 4-33
Stack-exception handler, 3-32,4-6, 4-34
Stack pointer (SP), 2-7, 3-28, 3-36
Standard UNIX System a.out
header, 5-80
Statements, assembly language, 5-22
Standard input (output),
Stdio, 5-117
Storage classes, 5-90
String table, 5-101
Strip utility, m32strip, 5-116
S truc'ture,
assignment, 5-7, 5-9
field names, 5-9, 5-10
member name restrictions, 5-10
member names, 5-9, 5-10
of a process, 4-4
operands, 5-9
references, 5-11
symbol table entries, 5-97
tag names, 5-12
Structure-tag, 5-8
Structure-valued arguments, 5-7
Subroutine transfer, 3-28
Subsystems link editing, 5-66
Supervisor mode (level 2), 4-1
Support, application, 1-4
Symbol information
finding index of, 5-ll8
name field, 5-90
reading, 5-120
storage classes, 5-90
value field, 5-90
Symbol table, 5-84
auxiliary entries, 5-97
displaying, 5-114
entries, 5-89
entry format, 5-89, 5-97
functions reading, 5-89
removing, 5-ll6
seeking, 5-120
stripping, 5-116

INDEX

Symbolic
debugger, 5-6
debugging, and assembly code, 5-17
debugging pseudo operations, 5-36
debugging symbols, 5-93
information, 5-1, 5-2
Symbols
creating and defining, 5-23
for functions, 5-89
pseudo-ops for, 5-33
Synchronous
read, 2-13
write, 2-18
Syntax diagram for input, 5-74
System reset, 2-52

T
Tag names, 5-99
Target machine, 5-106
Target processor address range, 5-53
TEXT,5-24
.text section, 5-31, 5-33
and m32conv, 5-106
Trace mechanism, 2-69
trace enable (TE), 2-69
trace mask (TM), 2-69
trace trap (TT), 2-68
truth table, 2-69
Transferring structure value, 5-9
Translation virtual, 4-37
Trap, 2-66, 4-30
TTL
input, 2-84
input specifications, 2-86
tttt field (data type), 3-20, 3-21
TYPE,5-118
Type
entry, 5-94
field, 5-94
Type-checking for structures, 5-11
Types, symbol, 5-24

u
UNDEFINED, 5-24
Unions, 5-11, 5-12
UNIX System, 1-5, 5-1
and utilities, 5-103
a.out header, 5-80
archive maintainer, 5-103, 5-114
User mode {level 3),4-1
User registers, 2-3, 3-3
Utilities and library routines, 5-102
Utility programs
m32ar, 5-103
m32conv, 5-105
m32convert, 5-105
m32cprs, 5-107
m32dis, 5-108
m32dump, 5-111
m32list, 5-113
m3210rder, 5-114
m32nm, 5-114
m32size, 5-116
m32strip, 5-116

v
Value types, assembler, 5-24
ABSOLUTE, 5-24
BSS, 5-24
DATA,5-24
TEXT,5-24
UNDEFINED, 5-24
Vertical tab character literal, 5-13
Virtual
address, 5-56, 4-37
address space, 4-36, 5-53
memory, 4-36, 4-40, 5-53
memory, division of, 5-54, 4-37

INDEX

w
Word
address modes, 3-9
data, 2-10, 3-1
boundary, 2-10
displacement deferred mode, 3-14
displacement mode, 3-14
immediate mode, 3-17
Writing and reading registers, 3-6

x
XSWITCH function, 4-21, 4-22, 4-28, 4-77
XSWITCH_ONE,4-77
XSWITCH_TWO,4-78
XSWITCH_THREE,4-79

z
Zero extension, 3-3, 3-6



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