WbXbc Manual Wb Xbc

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WbXbc Manual
Dirk Heisswolf
October 22, 2018

CONTENTS

Contents
1 Overview

2 Integration Parameters

3 Interface Signals
3.1 Address Region Descriptors
3.2 General Signals (SYSCON)
3.3 Initiator Bus Signals . . . .
3.4 Target Bus Signals . . . . .

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4 Crossbar Switch components
4.1 WbXbc Address Decoder . . .
4.1.1 Integration Parameters
4.1.2 Interface Signals . . . .
4.1.3 Verification Status . . .
4.2 WbXbc Error Generator . . . .
4.2.1 Integration Parameters
4.2.2 Interface Signals . . . .
4.2.3 Verification Status . . .
4.3 WbXbc Splitter . . . . . . . . .
4.3.1 Integration Parameters
4.3.2 Interface Signals . . . .
4.3.3 Verification Status . . .
4.4 WbXbc Arbiter . . . . . . . . .
4.4.1 Integration Parameters
4.4.2 Interface Signals . . . .
4.4.3 Verification Status . . .
4.5 WbXbc Expander . . . . . . .
4.5.1 Integration Parameters
4.5.2 Interface Signals . . . .
4.5.3 Verification Status . . .
4.6 WbXbc Reducer . . . . . . . .
4.6.1 Integration Parameters
4.6.2 Interface Signals . . . .
4.6.3 Verification Status . . .
4.7 WbXbc Accelerator . . . . . .
4.7.1 Integration Parameters
4.7.2 Interface Signals . . . .
4.7.3 Verification Status . . .
4.8 WbXbc Decelerator . . . . . .
4.8.1 Integration Parameters
4.8.2 Interface Signals . . . .
4.8.3 Verification Status . . .
4.9 WbXbc Pipeliner . . . . . . . .
4.9.1 Integration Parameters
4.9.2 Interface Signals . . . .
4.9.3 Verification Status . . .
4.10 WbXbc Standardizer . . . . . .

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CONTENTS

4.10.1 Integration Parameters
4.10.2 Interface Signals . . . .
4.10.3 Verification Status . . .
4.11 WbXbc Distributor . . . . . . .
4.11.1 Integration Parameters
4.11.2 Interface Signals . . . .
4.11.3 Verification Status . . .
4.12 WbXbc Xbar . . . . . . . . . .
4.12.1 Integration Parameters
4.12.2 Interface Signals . . . .
4.12.3 Verification Status . . .

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CONTENTS

Revision History
Date
October 22, 2018

Change
Initial release

OVERVIEW

Overview

WbXbc stands for “Wishbone crossbar components”. It is a collection of
soft IP blocks for building customized crossbar switches. As all WbXbc blocks
interconnect via a common interface (pipelined Wishbone protocol [1]), they can
be easily arranged to fulfil application specific performance or size requirements.
An example of different ways a set of Wishbone initiators may be connected to
a set of Wishbone targets shown in Figure 1-1. The four implementations differ
in the number of concurrent bus accesses they support and in the amount of
logic gates they require. The WbXbc components in this example are described
in Section 4 “Crossbar Switch components“.

Initiator

OVERVIEW

Initiator

2-Way Arbiter
WbXbc arbiter

Initiator

2-Way Arbiter
WbXbc arbiter

4x4 Crossbar Switch
WbXbc xbar
2x4 Crossbar Switch
WbXbc xbar

Target

Initiator

4x2 Crossbar Switch
WbXbc xbar

4-Way Arbiter
WbXbc arbiter

2-Way Distributor

WbXbc distributor

Target

4-Way Distributor
WbXbc distributor

Target

Figure 1-1: Examples of Different Crossbar Implementations

Target

INTEGRATION PARAMETERS

Integration Parameters

This section specifies the integration parameters to configure the WbXbc components.
Each WbXbc component supports a subset of the parameters listed below.
ITR CNT
The number of initiator bus interfaces to be offered by the WbXbc component
TGT CNT
The number of target bus interfaces to be offered by the WbXbc component
ADR WIDTH
Width of all address busses (ADR I and ADR 0)
ITR ADR WIDTH
Width of the initiator address bus(ses) (ADR I), in case it differs from the
target address bus(es) (ADR O)
SEL WIDTH
Number data select lines of all initiator and target busses (SEL I and
SEL O)
ITR SEL WIDTH
Number of data select lines of the initiator bus (SEL I), in case it from
the target bus (SEL O)
DAT WIDTH
Width of all data busses (initiator and target, read and write direction)
ITR DAT WIDTH
Width of the initiator’s data busses (read and write direction
TGA WIDTH
Number of tags associated with the address busses of the initiator and the
target (TGA I and TGA O)
TGC WIDTH
Number of tags associated with the cycle indicators (CYC I and CYC O) of
thw initiator and the target (TGC I and TGC O)
TGRD WIDTH
Number of tags assoociated with the read data busses of the initiator and
the target (TGD O and TGD I)
TGWD WIDTH
Number of tags associated with the write data busses of the initiator and
the target (TGD I and TGD O)
BIG ENDIAN
Selects the endianess of the design (1=big endian, 0=little endian)

INTERFACE SIGNALS

Interface Signals

All WbXbc components share common interface signals, which are described in
this chapter. Most of these signals refer directly to the Wishbone specification [1].
Some WbXbc components offer multiple of instances of a particular interface
type (e.g. the WbXbx Splitter offers multiple Wishbone target interfaces, the
WbXbc Arbiter offers multiple Wishbone initiator interfaces). In these cases,
the interfaces are concatinated on a signal by signal basis. For instance, a set of
concatinated Wishbone initiator interfaces shares a single itr adr i bus signal.
The individual bus signals are concatinated as a whole (see Figure 3-1). The
order of the signal concatination is consistent throughout all interface signals.
MSB

{

LSB
MSB

LSB

itrN adr i

MSB

,...,

LSB

itr2 adr i

MSB

LSB

itr1 adr i

MSB

LSB

itr0 adr i

}

itr adr i
Figure 3-1: Concatination of Interface signals

3.1

Address Region Descriptors

region adr i
Target region descriptors (base addresses).
The address range of each bus target is determined by a base address and
an address mask. An address itr adr i is within the range of the n-th
bus target if
itr adr i[ADR WIDTH-1:0] |
region msk i[(ADR WIDTH*(n+1))-1:ADR WIDTH*n]
≡
region adr i[(ADR WIDTH*(n+1))-1:ADR WIDTH*n] |
region msk i[(ADR WIDTH*(n+1))-1:ADR WIDTH*n]
region msk i
Target region descriptors (address masks).
See region adr i.

3.2

General Signals (SYSCON)

clk i
Common clock input for all Wishbone interfaces.
This clock input corresponds to signal CLK I of the Wishbone specification [1].
itr clk i
Clock input for all initiator busses.
Target busses must be clocked by synchronous and subdivided clock. This
clock input corresponds to signal CLK I of the Wishbone specification [1].
7

3.3

Initiator Bus Signals

INTERFACE SIGNALS

tgt clk i
Clock input for all target busses.
Initiator busses must be clocked by synchronous and subdivided clock.
This clock input corresponds to signal CLK I of the Wishbone specification [1].
itr2tgt sync i
Clock phase indicator for for the WbXbc Decelerator component.
This signal indicates a common positive clock edge of the initiator clock
and the synchronous and subdivided target clock (see Figure 3-2).
itr clk i
tgt clk i
itr2tgt sync i
Figure 3-2: itr2tgt sync i Timing Example

tgt2itr sync i
Clock phase indicator for for the WbXbc Accelerator component.
This signal indicates a common positive clock edge of the target clock and
the synchronous and subdivided initiator clock (see Figure 3-3).
itr clk i
tgt clk i
itr2tgt sync i
Figure 3-3: tgt2itr sync i Timing Example

async rst i
Optional asynchronous reset input for all sequential logic.
This reset signal may assert asynchronously, but must deassert synchronously.
If no asynchrounous reset is implemented, this input must be tied to zero.
sync rst i
Synchronous reset input.
For WbXBC components, this synchronous reset is not required, if an
asynchronous reset is provided. If no synchrounous reset is implemented,
this input must be tied to zero. This reset input corresponds to signal
RST I of the Wishbone specification [1].

3.3

Initiator Bus Signals

itr cyc i
Cycle indicator input.
This input signal corresponds to signal CYC I of the Wishbone specification [1].
itr stb i
Strobe input.
This input signal corresponds to signal STB I of the Wishbone specification [1].
8

3.3

Initiator Bus Signals

INTERFACE SIGNALS

itr we i
Write enable input.
This input signal corresponds to signal WE I of the Wishbone specification [1].
itr lock i
Cycle lock input.
This input signal corresponds to signal LOCK I of the Wishbone specification [1].
itr sel i
Write data select inputs.
These input signals correspond to bus SEL I of the Wishbone specification [1].
itr adr i
Address bus.
These input signals correspond to bus ADR I of the Wishbone specification [1].
itr dat i
Write data bus.
These input signals correspond to bus DAT I of the Wishbone specification [1].
itr tga i
Address bus tags.
These input signals correspond to bus TGA I of the Wishbone specification [1].
itr tgc i
Cycle tags.
These input signals correspond to bus TGC I of the Wishbone specification [1].
itr tgd i
Write data tags.
These input signals correspond to bus TGD I of the Wishbone specification [1].
itr ack o
Acknowlede output.
This output signal corresponds to signal ACK O of the Wishbone specification [1].
itr err o
Error indicator output.
This output signal corresponds to signal ERR O of the Wishbone specification [1].
itr rty o
Retry output.
This output signal corresponds to signal RTY O of the Wishbone specification [1].
For all WbXbc components this signal serves as indicator for a lost bus
arbitration.
itr stall o
Pipeline stall output.
This output signal corresponds to signal STALL O of the Wishbone specification [1].
itr dat o
Read data bus.
These output signals correspond to bus DAT O of the Wishbone specification [1].

3.4

Target Bus Signals

INTERFACE SIGNALS

itr tgd o
Read data tags.
These output signals correspond to bus TGD O of the Wishbone specification [1].

3.4

Target Bus Signals

tgt cyc o
Cycle indicator output.
This output signal corresponds to signal CYC O of the Wishbone specification [1].
tgt stb o
Strobe output.
This output signal corresponds to signal STB O of the Wishbone specification [1].
tgt we o
Write enable output.
This output signal corresponds to signal WE O of the Wishbone specification [1].
tgt lock o
Cycle lock output.
This output signal corresponds to signal LOCK O of the Wishbone specification [1].
tgt sel o
Write data select outputs.
These output signals correspond to bus SEL O of the Wishbone specification [1].
tgt adr o
Address bus.
These output signals correspond to bus ADR O of the Wishbone specification [1].
tgt dat o
Write data bus.
These output signals correspond to bus DAT O of the Wishbone specification [1].
tgt tga o
Address bus tags.
These output signals correspond to bus TGA O of the Wishbone specification [1].
tgt tgc o
Cycle tags.
These output signals correspond to bus TGC O of the Wishbone specification [1].
tgt tgd o
Write data tags.
These output signals correspond to bus TGD O of the Wishbone specification [1].
tgt ack i
Acknowlede input.
This input signal corresponds to signal ACK I of the Wishbone specification [1].
tgt err i
Error indicator input.
This input signal corresponds to signal ERR I of the Wishbone specification [1].

3.4

Target Bus Signals

INTERFACE SIGNALS

tgt rty i
Retry input.
This output signal corresponds to signal RTY I of the Wishbone specification [1].
For all WbXbc components this signal serves as indicator for a lost bus
arbitration.
tgt stall i
Pipeline stall input.
This input signal corresponds to signal STALL I of the Wishbone specification [1].
tgt dat i
Read data bus.
These input signals correspond to bus DAT I of the Wishbone specification [1].
tgt tgd i
Read data tags.
These input signals correspond to bus TGD I of the Wishbone specification [1].

CROSSBAR SWITCH COMPONENTS

Crossbar Switch components

The WbXbc tontains components to connect Wishbone intefaces of various
types. Table 4-1 summarizes the components, which are currently available.
Detailed descriptions are given in the following sections.
Table 4-1: List of WbXbc Components
Component
WbXbc address decoder
WbXbc error generator
WbXbc splitter
WbXbc arbiter
WbXbc expander
WbXbc reducer
WbXbc accelerator
WbXbc decellerator
WbXbc pipeliner
WbXbc standardizer
WbXbc distributor
WbXbc xbar

Decription
Decodes the initiator address and generates tags selecting
the target memory.
Generates an error response, if no target is selected.
Connects an initiator bus to a set of targets. Tatgets are
selected based on tags.
Propagates a bus cycle from one of many initiator
interfaces to a single target.
Connects an initiator bus to a target with a wider data
bus.
Connects an initiator bus to a target with a narrower data
bus.
Connects an initiator bus to a target running at a higher
clock frequency.
Connects an initiator bus to a target running at a lower
clock frequency.
Connects a standard Wishbone interface to a pipelined
target.
Connects a pipelined Wishbone interface to a standard
target.
Connects an initiator bus to a set of targets. Tatgets are
selected based on the address.
Preassembled full crossbar switch.

4.1

WbXbc Address Decoder

4.1

CROSSBAR SWITCH COMPONENTS

WbXbc Address Decoder (WbXbc addesss decoder)

This module implements an address decoder for the Wishbone protocol. It
propagates accesses from the initiator bus to the target bus and adds a set of
address tags which selecting the target block (see Figure 4-1).

Address
Regions
Initiator Bus
without
Selects

WbXbc
Address
Decoder

Target
Bus with
Selects

Figure 4-1: Block Diagram of the WbXbc Address Decoder

4.1.1

Integration Parameters

The WbXbc Address Decoder supports the integration parameters listed in
Table 4-2. See Section 2 “Integration Parameters“ for a detailed description of
all integration parameters.
Table 4-2: Integration Parameters of the WbXbc Address Decoder
Parameter
TGT CNT
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.1.2

Default
4
16
16
2
1
1
1
1

Decription
Number of target addresses to decode
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags

Interface Signals

Table 4-3 lists the interface signals of the WbXbc Address Decoder. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.1

WbXbc Address Decoder

CROSSBAR SWITCH COMPONENTS

Table 4-3: Interface Signals of the WbXbc Address Decoder
Signal

Range

Direction

Decription

Target Address Regions

region adr i

(TGT CNT*ADR WIDTH)1:0

input

region msk i

(TGT CNT*ADR WIDTH)1:0

input

target address regions
selects relevant address bits
1: relevant, 0: ignored)

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
itr
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tga tgtsel o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

bus cycle indicator
access request
write enable
uninterruptable bus cycle
write data selects
address bus
write data bus
address tags
bus cycle tags
write data tags
bus cycle acknowledge
error indicator
retry request
access delay
read data bus
read data tags

Target Interface

4.1.3

SEL WIDTH-1:0
ADR WIDTH-1:0
DAT WIDTH-1:0
TGA WIDTH-1:0
TGT CNT-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

bus cycle indicator
access request
write enable
uninterruptable bus cycle
write data selects
write data selects
write data bus
address tags
target select tags
bus cycle tags
write data tags
bus cycle acknowledge
error indicator
retry request
access delay
read data bus
read data tags

Verification Status

Table 4-4 provides an overview of the verification status of the WbXbc Address
Decoder. Lint checks have been done with the Icarus Verilog simulator [2] and

4.1

WbXbc Address Decoder

CROSSBAR SWITCH COMPONENTS

the Yosys synthesis tool [3].
Table 4-4: Verification Status of the WbXbc Address Decoder
Configuration
default:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.2

WbXbc Error Generator

4.2

CROSSBAR SWITCH COMPONENTS

WbXbc Error Generator (WbXbc error generator)

This module implements an error generator or dummy target for the pipelined
Wishbone protocol. It propagates accesses from the initiator to the target bus,
but intercepts accesses without a target, signaling an error condition to the
initiator. The target association is determined by a set of address tags, generated
by the address decoder (see Figure 4-2).

WbXbc
Error
Generator

Initiator
Bus with
Selects

Target
Bus with
Selects

Figure 4-2: Block Diagram of the WbXbc Error Generator

4.2.1

Integration Parameters

The WbXbc Error Generator supports the integration parameters listed in
Table 4-5. See Section 2 “Integration Parameters“ for a detailed description
of all integration parameters.
Table 4-5: Integration Parameters of the WbXbc Error Generator
Parameter
TGT CNT
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.2.2

Default
4
16
16
2
1
1
1
1

Interface Signals

Table 4-6 lists the interface signals of the WbXbc Error Generator. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.2

WbXbc Error Generator

CROSSBAR SWITCH COMPONENTS

Table 4-6: Interface Signals of the WbXbc Error Generator
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tga tgtsel i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
itr
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tga tgtsel o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL WIDTH-1:0
ADR WIDTH-1:0
DAT WIDTH-1:0
TGA WIDTH-1:0
TGT CNT-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

bus cycle indicator
access request
write enable
uninterruptable bus cycle
write data selects
address bus
write data bus
address tags
target select tags
bus cycle tags
write data tags
bus cycle acknowledge
error indicator
retry request
access delay
read data bus
read data tags

Target Interface

SEL WIDTH-1:0
ADR WIDTH-1:0
DAT WIDTH-1:0
TGA WIDTH-1:0
TGT CNT-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

4.2

WbXbc Error Generator

4.2.3

CROSSBAR SWITCH COMPONENTS

Verification Status

Table 4-7 provides an overview of the verification status of the WbXbc Error
Generator. Lint checks have been done with the Icarus Verilog simulator [2] and
the Yosys synthesis tool [3].
Table 4-7: Verification Status of the WbXbc Error Generator
Configuration
default:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.3

WbXbc Splitter

4.3

CROSSBAR SWITCH COMPONENTS

WbXbc Splitter (WbXbc splitter)

Initiator
Bus with
Selects

WbXbc
Splitter

...

This module implements a bus splitter for the pipelined Wishbone protocol.
Accesses from the initiator bus are propagated to one of the target busses. The
target busses are selected by a set of address tags, generated by the address
decoder (see Figure 4-3).

Multiple
Target
Buses

Figure 4-3: Block Diagram of the WbXbc Splitter

4.3.1

Integration Parameters

The WbXbc Splitter supports the integration parameters listed in Table 4-8. See
Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-8: Integration Parameters of the WbXbc Splitter
Parameter
TGT CNT
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.3.2

Default
4
16
16
2
1
1
1
1

Decription
Number of target busses
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags

Interface Signals

Table 4-9 lists the interface signals of the WbXbc Splitter. See Section 3 “Interface Signals“
for a detailed description of all interface signals.

4.3

WbXbc Splitter

CROSSBAR SWITCH COMPONENTS

Table 4-9: Interface Signals of the WbXbc Splitter
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tga tgtsel i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL WIDTH-1:0
ADR WIDTH-1:0
DAT WIDTH-1:0
TGA WIDTH-1:0
TGT CNT-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

4.3.3

TGT CNT-1:0
TGT CNT-1:0
TGT CNT-1:0
TGT CNT-1:0
(TGT CNT*SEL WIDTH)-1:0
(TGT CNT*ADR WIDTH)-1:0
(TGT CNT*DAT WIDTH)-1:0
(TGT CNT*TGA WIDTH))-1:0
(TGT CNT*TGC WIDTH)-1:0
(TGT CNT*TGWD WIDT)-1:0
TGT CNT-1:0
TGT CNT-1:0
TGT CNT-1:0
TGT CNT-1:0
(TGT CNT*DAT WIDTH-1):0
(TGT CNT*TGRD WIDTH-1):0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated
concatinated

bus cycle indicators
access requests
write enables
bus cycle locks
write data selects
write data selects
write data busses
address tags
bus cycle tags
write data tags
bus cycle acknowledges
error indicators
retry requests
access delays
read data busses
read data tags

Verification Status

Table 4-10 provides an overview of the verification status of the WbXbc Splitter.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys

4.3

WbXbc Splitter

CROSSBAR SWITCH COMPONENTS

synthesis tool [3].
Table 4-10: Verification Status of the WbXbc Splitter
Configuration
default:
TGT CNT
4
ADR WIDTH
16
16
DAT WIDTH
SEL WIDTH
2
1
TGA WIDTH
1
TGC WIDTH
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.4

WbXbc Arbiter

4.4

CROSSBAR SWITCH COMPONENTS

WbXbc Arbiter (WbXbc arbiter)

This module implements a bus arbiter for the pipelined Wishbone protocol.
Accesses from multiple initiator busses are arbitrated and propagated to the
target bus (see Figure 4-4). Each initiator bus can request bus accesses at two
priority levels. The priority levels are selected via a set of address tags. Access
requests of equal priority are arbitrated with a fixed priority (initiator 0 has the
higheest priority).

WbXbc
Arbiter

...

Multiple
Initiator
Busses

Single
Target
Bus

Figure 4-4: Block Diagram of the WbXbc Arbiter

4.4.1

Integration Parameters

The WbXbc Arbiter supports the integration parameters listed in Table 4-11.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-11: Integration Parameters of the WbXbc Arbiter
Parameter
ITR CNT
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.4.2

Default
4
16
16
2
1
1
1
1

Decription
Number of initiator busses
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags

Interface Signals

Table 4-12 lists the interface signals of the WbXbc Arbiter. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.4

WbXbc Arbiter

CROSSBAR SWITCH COMPONENTS

Table 4-12: Interface Signals of the WbXbc Arbiter
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tga prio i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

ITR CNT-1:0
ITR CNT-1:0
ITR CNT-1:0
ITR CNT-1:0
(ITR CNT*SEL WIDTH)-1:0
(ITR CNT*ADR WIDTH)-1:0
(ITR CNT*DAT WIDTH)-1:0
(ITR CNT*TGA WIDTH)-1:0
ITR CNT-1:0
(ITR CNT*TGC WIDTH)-1:0
(ITR CNT*TGWD WIDTH)-1:0
ITR CNT-1:0
ITR CNT-1:0
ITR CNT-1:0
ITR CNT-1:0
(ITR CNT*DAT WIDTH)-1:0
(ITR CNT*TGRD WIDTH)-1:0

input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

bus cycle indicators
access requests
write enables
bus cycle locks
write data selects
address busses
write data busses
address tags
access priorities
bus cycle tags
write data tags
bus cycle acknowledges
error indicators
retry requests
access delays
read data buses
read data tags

Target Interface

4.4.3

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

bus cycle indicator
access request
write enable
uninterruptable bus cycle
write data selects
write data selects
write data bus
address tags
bus cycle tags
write data tags
bus cycle acknowledge
error indicator
retry request
access delay
read data bus
read data tags

Verification Status

Table 4-13 provides an overview of the verification status of the WbXbc Arbiter.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys

4.4

WbXbc Arbiter

CROSSBAR SWITCH COMPONENTS

synthesis tool [3].
Table 4-13: Verification Status of the WbXbc Arbiter
Configuration
default:
ITR CNT
4
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.5

WbXbc Expander

4.5

CROSSBAR SWITCH COMPONENTS

WbXbc Expander (WbXbc expander)

This module connects a pipelined Wishbone initiator to a target with twice the
data bus width (see Figure 4-5).

Narrow
Initiator
Bus

WbXbc
Expander

Wide
Target
Bus

Figure 4-5: Block Diagram of the WbXbc Expander

4.5.1

Integration Parameters

The WbXbc Expander supports the integration parameters listed in Table 4-14.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-14: Integration Parameters of the WbXbc Expander
Parameter
ITR ADR WIDTH
ITR DAT WIDTH
ITR SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH
BIG ENDIAN

4.5.2

Default
16
16
2
1
1
1
1
1

Decription
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags
Endianess of the component

Interface Signals

Table 4-15 lists the interface signals of the WbXbc Expander. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.5

WbXbc Expander

CROSSBAR SWITCH COMPONENTS

Table 4-15: Interface Signals of the WbXbc Expander
Signal

Range

Direction

Decription

Target Address Regions

region addr i

(TGT CNT*ADR WIDTH)1:0

input

region mask i

(TGT CNT*ADR WIDTH)1:0

input

target address
selects relevant address
bits
(1:
relevant,
0:
ignored)

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr

cyc i
stb i
we i
lock i

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

input
input
input
input
ITR SEL WIDTH-1:0
ITR ADR WIDTH-1:0
ITR DAT WIDTH-1:0
TGA WIDTH-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
output
output
output
output
output
output

bus cycle indicator
access request
write enable
uninterruptable
bus
cycle
write data selects
address bus
write data bus
address tags
bus cycle tags
write data tags
bus cycle acknowledge
error indicator
retry request
access delay
read data bus
read data tags
...continued

4.5

WbXbc Expander

CROSSBAR SWITCH COMPONENTS

Table 4-15: Interface Signals of the WbXbc Expander
Signal

Range

Direction

Decription

Target Interface

tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

4.5.3

output
output
output
output
(ITR SEL WIDTH*2)-1:0
ITR ADR WIDTH-2:0
(ITR DAT WIDTH*2)-1:0
TGA WIDTH-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
input
input
input
input
input
input

bus cycle indicator
access request
write enable
uninterruptable
bus
cycle
write data selects
write data selects
write data bus
address tags
bus cycle tags
write data tags
bus cycle acknowledge
error indicator
retry request
access delay
read data bus
read data tags

Verification Status

Table 4-16 provides an overview of the verification status of the WbXbc Expander.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys
synthesis tool [3].
Table 4-16: Verification Status of the WbXbc Expander
Configuration
default:
ITR ADR WIDTH
16
ITR DAT WIDTH
16
ITR SEL WIDTH
2
1
TGA WIDTH
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
BIG ENDIAN
1

Linting

Simulation

Formal

FPGA

iVerilog [2]
Yosis [3]

...continued

4.5

WbXbc Expander

CROSSBAR SWITCH COMPONENTS

Table 4-16: Verification Status of the WbXbc Expander
Configuration
little endian:
ITR ADR WIDTH
16
ITR DAT WIDTH
16
ITR SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
BIG ENDIAN
0

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.6

WbXbc Reducer

4.6

CROSSBAR SWITCH COMPONENTS

WbXbc Reducer (WbXbc reducer)

This module connects a pipelined Wishbone initiator to a target with half the
data bus width (see Figure 4-6). Initiator bus accesses may be converted into
two consecutive accesses to the target bus.

Wide
Initiator
Bus

WbXbc
Reducer

Narrow
Target
Bus

Figure 4-6: Block Diagram of the WbXbc Reducer

4.6.1

Integration Parameters

The WbXbc Reducer supports the integration parameters listed in Table 4-17.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-17: Integration Parameters of the WbXbc Reducer
Parameter
ITR ADR WIDTH
ITR DAT WIDTH
ITR SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH
BIG ENDIAN

4.6.2

Default
16
16
2
1
1
1
1
1

Interface Signals

Table 4-18 lists the interface signals of the WbXbc Reducer. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.6

WbXbc Reducer

CROSSBAR SWITCH COMPONENTS

Table 4-18: Interface Signals of the WbXbc Reducer
Signal

Range

Direction

Decription

Target Address Regions

region addr i

(TGT CNT*ADR WIDTH)1:0

input

region mask i

(TGT CNT*ADR WIDTH)1:0

input

target address
selects relevant address bits
(1: relevant, 0: ignored)

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

ITR SEL WIDTH-1:0
ITR ADR WIDTH-1:0
ITR DAT WIDTH-1:0
TGA WIDTH-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

(ITR SEL WIDTH/2)-1:0
ITR ADR WIDTH:0
(ITR DAT WIDTH/2)-1:0
TGA WIDTH-1:0
TGC WIDTH-1:0
TGWD WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

4.6

WbXbc Reducer

4.6.3

CROSSBAR SWITCH COMPONENTS

Verification Status

Table 4-19 provides an overview of the verification status of the WbXbc Reducer.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys
synthesis tool [3].
Table 4-19: Verification Status of the WbXbc Reducer
Configuration
default:
ITR ADR WIDTH
16
ITR DAT WIDTH
16
ITR SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
BIG ENDIAN
1
little endian:
ITR ADR WIDTH
16
ITR DAT WIDTH
16
ITR SEL WIDTH
2
1
TGA WIDTH
1
TGC WIDTH
TGRD WIDTH
1
TGWD WIDTH
1
0
BIG ENDIAN

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.7

WbXbc Accelerator

4.7

CROSSBAR SWITCH COMPONENTS

WbXbc Accelerator (WbXbc accelerator)

This module connects a pipelined Wishbone initiator, running at a higher frequency
to a target, running at a lower frequency (see Figure 4-7).

Slow
Initiator
Bus

WbXbc
Accelerator

Fast
Target
Bus

Figure 4-7: Block Diagram of the WbXbc Accelerator

4.7.1

Integration Parameters

The WbXbc Accelerator supports the integration parameters listed in Table 4-20.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-20: Integration Parameters of the WbXbc Accelerator
Parameter
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH
REG ITR

4.7.2

Default
16
16
2
1
1
1
1
0

Decription
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags
Register initiator bus inputs

Interface Signals

Table 4-21 lists the interface signals of the WbXbc Accelerator. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.7

WbXbc Accelerator

CROSSBAR SWITCH COMPONENTS

Table 4-21: Interface Signals of the WbXbc Accelerator
Signal

Range

Direction

Decription

Clock and Reset

input
input
input
input

tgt clk i
tgt2itr sync i
async rst i
sync rst i

target clock
clock sync signal
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

4.7.3

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

Verification Status

Table 4-22 provides an overview of the verification status of the WbXbc Accelerator.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys

4.7

WbXbc Accelerator

CROSSBAR SWITCH COMPONENTS

synthesis tool [3].
Table 4-22: Verification Status of the WbXbc Accelerator
Configuration
default:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
REG ITR
0
reg itr:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
1
REG ITR

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.8

WbXbc Decelerator

4.8

CROSSBAR SWITCH COMPONENTS

WbXbc Decelerator (WbXbc decelerator)

This module connects a pipelined Wishbone initiator, running at a higher frequency
to a target, running at a lower frequency (see Figure 4-8).

Fast
Initiator
Bus

WbXbc
Decelerator

Slow
Target
Bus

Figure 4-8: Block Diagram of the WbXbc Decelerator

4.8.1

Integration Parameters

The WbXbc Decelerator supports the integration parameters listed in Table 4-23.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-23: Integration Parameters of the WbXbc Decelerator
Parameter
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH
REG ITR
REG TGT

4.8.2

Default
16
16
2
1
1
1
1
0
0

Interface Signals

Table 4-24 lists the interface signals of the WbXbc Decelerator. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.8

WbXbc Decelerator

CROSSBAR SWITCH COMPONENTS

Table 4-24: Interface Signals of the WbXbc Decelerator
Signal

Range

Direction

Decription

Clock and Reset

input
input
input
input

itr clk i
itr2tgt sync i
async rst i
sync rst i

initiator clock
clock sync signal
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

4.8.3

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

Verification Status

Table 4-25 provides an overview of the verification status of the WbXbc Decelerator.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys

4.8

WbXbc Decelerator

CROSSBAR SWITCH COMPONENTS

synthesis tool [3].
Table 4-25: Verification Status of the WbXbc Decelerator
Configuration
default:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
REG ITR
0
REG TGT
0
reg itr:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
1
TGWD WIDTH
1
REG ITR
0
REG TGT
reg itrtgt:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
1
TGWD WIDTH
REG ITR
1
1
REG TGT
reg tgt:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1
REG ITR
0
REG TGT
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.9

WbXbc Pipeliner

4.9

CROSSBAR SWITCH COMPONENTS

WbXbc Pipeliner (WbXbc pipeliner)

This module connects a standard protocol Wishbone initiator to a pipelined
target (see Figure 4-9).

Standard
Initiator
Bus

WbXbc
Pipeliner

Pipelined
Target
Bus

Figure 4-9: Block Diagram of the WbXbc Pipeliner

4.9.1

Integration Parameters

The WbXbc Pipeliner supports the integration parameters listed in Table 4-26.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-26: Integration Parameters of the WbXbc Pipeliner
Parameter
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.9.2

Default
16
16
2
1
1
1
1

Decription
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags

Interface Signals

Table 4-27 lists the interface signals of the WbXbc Pipeliner. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.9

WbXbc Pipeliner

CROSSBAR SWITCH COMPONENTS

Table 4-27: Interface Signals of the WbXbc Pipeliner
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

4.9.3

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

Verification Status

Table 4-28 provides an overview of the verification status of the WbXbc Pipeliner.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys
synthesis tool [3].

4.9

WbXbc Pipeliner

CROSSBAR SWITCH COMPONENTS

Table 4-28: Verification Status of the WbXbc Pipeliner
Configuration
default:
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.10

WbXbc Standardizer

4.10

CROSSBAR SWITCH COMPONENTS

WbXbc Standardizer (WbXbc standardizer)

This module connects a pipelined Wishbone initiator to a standard protocol
target (see Figure 4-10).

Pipelined
Initiator
Bus

WbXbc
Standardizer

Standard
Target
Bus

Figure 4-10: Block Diagram of the WbXbc Standardizer

4.10.1

Integration Parameters

The WbXbc Standardizer supports the integration parameters listed in Table 4-29.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-29: Integration Parameters of the WbXbc Standardizer
Parameter
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.10.2

Default
16
16
2
1
1
1
1

Decription
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags

Interface Signals

Table 4-30 lists the interface signals of the WbXbc Standardizer. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

4.10

WbXbc Standardizer

CROSSBAR SWITCH COMPONENTS

Table 4-30: Interface Signals of the WbXbc Standardizer
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

4.10.3

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

Verification Status

Table 4-31 provides an overview of the verification status of the WbXbc Standardizer.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys
synthesis tool [3].

4.10

WbXbc Standardizer

CROSSBAR SWITCH COMPONENTS

Table 4-31: Verification Status of the WbXbc Standardizer
Configuration
default configuration:
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

Linting
16
16
2
1
1
1
1

iVerilog [2]
Yosis [3]

Simulation

Formal

FPGA

4.11

WbXbc Distributor

4.11

CROSSBAR SWITCH COMPONENTS

WbXbc Distributor (WbXbc distributor)

This module combines an address decoder, an error generator, and a bus splitter
for the pipelined Wishbone protocol (see Figure 4-11).

WbXbc Distributor

Initiator Bus
w/ Selects

WbXbc
Address
Decoder

WbXbc Error
Generator

WbXbc
Splitter

...

Address
Regions

Figure 4-11: Block Diagram of the WbXbc Distributor

4.11.1

Integration Parameters

The WbXbc Distributor supports the integration parameters listed in Table 4-32.
See Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-32: Integration Parameters of the WbXbc Distributor
Parameter
TGT CNT
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.11.2

Default
4
16
16
2
1
1
1
1

Interface Signals

Table 4-33 lists the interface signals of the WbXbc Distributor. See Section 3
“Interface Signals“ for a detailed description of all interface signals.

Multiple
Target
Buses

4.11

WbXbc Distributor

CROSSBAR SWITCH COMPONENTS

Table 4-33: Interface Signals of the WbXbc Distributor
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Target Address Regions

region adr i

(TGT CNT*ADR WIDTH)1:0

input

region msk i

(TGT CNT*ADR WIDTH)1:0

input

target address regions
selects relevant address bits
(1: relevant, 0: ignored)

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

SEL
ADR
DAT
TGA
TGC
TGWD

WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0
WIDTH-1:0

DAT WIDTH-1:0
TGRD WIDTH-1:0

input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

4.11

WbXbc Distributor

4.11.3

CROSSBAR SWITCH COMPONENTS

Verification Status

Table 4-34 provides an overview of the verification status of the WbXbc Distributor.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys
synthesis tool [3].
Table 4-34: Verification Status of the WbXbc Distributor
Configuration
default:
TGT CNT
4
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

4.12

WbXbc Xbar

4.12

CROSSBAR SWITCH COMPONENTS

WbXbc Xbar (WbXbc xbar)

This module implements a full crossbar switch between a set of initator busses
and a set of target busses, all using the pipelined Wishbone protocol. The
WbXbc Xbar consists ditributor and arbiter components (see Figure 4-12).
...
Initiator

WbXbc
Distributor

...

WbXbc
Distributor

...

WbXbc Arbiter

Target

WbXbc Arbiter

Target

...

Initiator

...

WbXbc Xbar

WbXbc Arbiter

Figure 4-12: Block Diagram of the WbXbc Xbar

...

Initiator

Target

4.12

WbXbc Xbar

4.12.1

CROSSBAR SWITCH COMPONENTS

Integration Parameters

The WbXbc Xbar supports the integration parameters listed in Table 4-35. See
Section 2 “Integration Parameters“ for a detailed description of all integration
parameters.
Table 4-35: Integration Parameters of the WbXbc Xbar
Parameter
ITR CNT
TGT CNT
ADR WIDTH
DAT WIDTH
SEL WIDTH
TGA WIDTH
TGC WIDTH
TGRD WIDTH
TGWD WIDTH

4.12.2

Default
4
4
16
16
2
1
1
1
1

Decription
Number of initiator busses
Number of target busses
Width of the address bus
Width of each data bus
Number of data select lines
Number of address tags
Number of cycle tags
Number of read data tags
Number of write data tags

Interface Signals

Table 4-36 lists the interface signals of the WbXbc Xbar. See Section 3 “Interface Signals“
for a detailed description of all interface signals.
Table 4-36: Interface Signals of the WbXbc Xbar
Signal

Range

Direction

Decription

Clock and Reset

input
input
input

clk i
async rst i
sync rst i

module clock
asynchronous reset
synchronous reset

Target Address Regions

region adr i

(TGT CNT*ADR WIDTH)1:0

input

region msk i

(TGT CNT*ADR WIDTH)1:0

input

target address
selects relevant address bits
(1: relevant, 0: ignored)
...continued

4.12

WbXbc Xbar

CROSSBAR SWITCH COMPONENTS

Table 4-36: Interface Signals of the WbXbc Xbar
Signal

Range

Direction

Decription

Initiator Interface

itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr
itr

cyc i
stb i
we i
lock i
sel i
adr i
dat i
tga i
tga prio i
tgc i
tgd i
ack o
err o
rty o
stall o
dat o
tgd o

input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output

Target Interface

tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt
tgt

cyc o
stb o
we o
lock o
sel o
adr o
dat o
tga o
tgc o
tgd o
ack i
err i
rty i
stall i
dat i
tgd i

4.12.3

output
output
output
output
output
output
output
output
output
output
input
input
input
input
input
input

Verification Status

Table 4-37 provides an overview of the verification status of the WbXbc Xbar.
Lint checks have been done with the Icarus Verilog simulator [2] and the Yosys
synthesis tool [3].

4.12

WbXbc Xbar

CROSSBAR SWITCH COMPONENTS

Table 4-37: Verification Status of the WbXbc Xbar
Configuration
default:
ITR CNT
4
TGT CNT
4
ADR WIDTH
16
DAT WIDTH
16
SEL WIDTH
2
TGA WIDTH
1
TGC WIDTH
1
TGRD WIDTH
1
TGWD WIDTH
1

Linting

Simulation

iVerilog [2]
Yosis [3]

Formal

FPGA

REFERENCES

References
[1] Wishbone b4.
2010.

http://cdn.opencores.org/downloads/wbspec_b4.pdf,

[2] Stephen Williams. Icarus verilog. http://iverilog.icarus.com/.
[3] Clifford Wolf.
yosys/.

Yosys open synthesis suite.

http://www.clifford.at/

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