Western_Digital_Caviar_WDAC140_AC280_Technical_Ref_Feb92 Western Digital Caviar WDAC140 AC280 Technical Ref Feb92

Western_Digital_Caviar_WDAC140_AC280_Technical_Ref_Feb92 Western_Digital_Caviar_WDAC140_AC280_Technical_Ref_Feb92

User Manual: Western_Digital_Caviar_WDAC140_AC280_Technical_Ref_Feb92

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Caviar WDAC140lAC280
40 and 80 Megabyte
3.5 -inch drive

eee WESTERN DIGITAL

Copyright © 1993 Western Digital Corporation
All Rights Reserved
Information furnished by Western Digital Corporation is believed to be accurate and reliable. 'However,
no responsibility is assumed by Western Digital Corporation for its use; nor for. any infringements of
patents or other rights of third parties which may 'result from its use. No license.is granted by implication
or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change specifications at any time without notice.
Western Digital, AutoSwitch, and Paradise are registered trademarks and Cache Flow, Caviar, FIT.
L.at>, Hyperseek, Interarchitecture, PinScan, Piranha, SAM, Tidbit, and TrueShadeare trademarks of
Western Digital Corporation.
Other marks may be mentioned herein that belong to other companies.
Western Digital Corporation
Western Digital Plaza, 8105 .Irvine Center Drive, Irvine, CA 92718
For Service and Literature, call:
(714) 932-4900

CONTENTS
1.0

2.0

DESCRIPTION AND FEATURES
1.1
General Description
1.2
Advanced Product Features
Cache Flow . . .
Automatic Head Parking
Advanced Defect Management
Embedded Sector Servo Control
Dual Drive Operation
Intelligent Drive . . . .
Translation . . . . . .
Error Recovery . . . . .
Guaranted Compatability

1
1
2
2
2
2
2
2
2
3

SPECIFICATIONS . . . . . . . . .
2.1
Performance Specifications
2.2
Physical Specifications . . .
2.2.1
Physical Dimensions
2.2.2 Weight . . . . .
2.2.3 Mechanical Specifications
2.3
Electrical Specifications
2.3.1
12VDC and 5VDC Typical Current
2.3.2 Ripple
........ .
2.3.3 Power Connectors and Cables
2.3.4 Grounding . . . . . .
2.4
Environmental Specifications
2.4.1
Shock and Vibration
2.4.2 Temperature and Humidity
2.4.3 Atmosphere Pressure . .
2.5
Agency Approvals . . . . . . .
2.6
Reliability Specification . . . . .
2.7
Compatibility Per Functional Integrity Testing
Alpha Tests . . . . . . . .
Benchmark Tests . . . . . . . .
Peripheral Compatibility Tests
Host Compatibility Tests . . . . .
Operating System Compatibility Tests

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Western Digital Corporation

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Caviar ACl40IAC280 Technical Reference Manual
3.0

4.0

PRINCIPLES OF OPERATION
3.1
Block Diagram
. . . . . . . . . . .
3.2
Drive Electronics
.......... .
3.2.1
WD42C22 Winchester Disk Controller
3.2.2 Buffer RAM . . . . . . .
3.~.3
WDSOC11 Servo Controller
3.2.4 WD10C23 Data Separator . .
3.2.5 Microprocessor ROM and RAM
3.2.S Pulse Detector ..
3.2.7 Spindle Motor Driver
3.2.8 Actuator Driver . . .
3.3
Head Disk Assembly (HDA) . .
3.3.1
Base/Cover Assembly
3.3.2 Spindle Motor
3.3.3 Disk Stack Assembly
3.3.4 Headstack Assembly
Read/Write Heads . .
Actuator Arm Assembly
Flex Circuit . . . .
3.3.5 Voice Coil Assembly
3.3.S Air Filtration System
ADVANCED PRODUCT FEATURES ..
4.1
CacheFlow........
4.1.1
Purpose of CacheFlow
4.1.2 Benefits of Cache Flow
4.1.3 CacheFlow Operation
4.1.4 Sequential Mode ..
4.1.5 Repetitive Mode
4.2
Defect Management and Format Characteristics
4.2.1
Defect Management
4.2.2 Format Characteristics
4.3
Error Recovery
4.4
Translation
4.5
Dual Drive Option . . . . . .

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Western Digital Corporation

5.0

HOST INTERFACE AND AT COMMAND SET
5.1
J2 Pin Assignments . . . . .
5.2
Host Interface Registers
5.2.1
Register Address Map
5.2.2 Data Register . . . .
5.2.3 Error Register . . . .
5.2.4 Write Precompensation Register
5.2.5 Sector Count Register . . . . .
5.2.6 Sector Number Register . . . .
5.2.7 Cylinder low/Cylinder High Registers
5.2.B SDH Register . . . . .
5.2.9 Status Register . . . . .
5.2.10 Command Register . . . .
5.2.11 Alternate Status Register .
5.2.12 Fixed Disk Control Register
5.2.13 Digital Input Register .
5.3
Caviar AC14O/AC2BO Commands
5.3.1
Recalibrate (10H)
5.3.2 Seek (70H) . . .
5.3.3 Read Sector (20H)
5.3.4 Write Sector (30H)
5.3.5 Format Track (50H)
5.3.6 Read Verify (4OH) . . .
5.3.7 Executive Diagnostics (90H)
5.3.B Set Drive Parameters (91 H)
5.3.9 Read Multiple (C4H)
5.3.10 Write Multiple (C5H)
5.3.11 Set Multiple (C6H)
5.3.12 Read Buffer (E4H) .
5.3.13 Write Buffer (EBH) .
5.3.14 Identify Drive (ECH) .
5.3.15 Set Buffer Mode (EFH)
5.4
Host Interface Read liming
5.5
Host Interface Write liming
5.6
Error Reporting . . . . . . .

Western Digital Corporation

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Caviar AC140lAC280 Technical Reference Manual
6.0

INSTALLATION AND SETUP PROCEDURES
6.1
Unpacking.........
6.1.1
Handling Precautions .
Inspection of Shipping Container
6.1.2 Removal From Shipping Container
6.1.3 Removal From Antistatic Bag
6.1.4 Moving Precautions .
6.2
Mounting Restrictions . . . .
6.2.1
Orientation........
6.2.2 Screw Size limitations . . .
6.3
Installation Configuration . . . . . .
6.3.1
Determining Your Configuration
6.3.2 Dual Installations .
6.3.3 Jumper Settings . . . . .
6.4
Installing the Caviar Drive . . . . .
6.4.1
Mounting The Drive . . . .
6.4.2 Cabling and Installation Steps
6.5
Installing the Adapter Card . . . . .
6.6
Setup Procedures . . . . . . . . .
6.6.1
Preparing the Caviar Drive For Use
6.6.2 Selecting Drive Tables . . . . .
6.6.3 Partitioning the Drive . . . . . .
6.6.4 High-level Formatting . . . . .
6.6.5 Preparing the Caviar Drive for a Novell Network
6.6.6 Booting the System . . . . . . . . . . .

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. . . . . . . . . . . . . . . . . . . . . . . . 81

7.0

MAINTENANCE

8.0

WESTERN DIGITAL DRIVE UTILITY . . . . . . .
Technical Support Bulletin Board

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9.0

TROUBLESHOOTING

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10.0

GLOSSARY

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....

Western Digital Corporation

FIGURES
Figure 2-1.
Figure 2-2.

+12V Current Draw During Spin Up (Master Mode)

Figure 3-1.
Figure 3-2.

Block Diagram . . . . .
Mechanical Exploded View

.21

Figure 4-1.
Figure 5-1.
Figure 5-2.
Figure 5-3.

CacheFlow Algorithm . . .
Standard Factory Connectors
Host Read Timing
Host Write Timing . . . .

.27
.33
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Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.

Jumper Settings . . . . .
Standard Factory Connectors
Caviar Connector locations
Adapter Cabling . . . . .

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Caviar AC140/AC280 Mounting Dimensions

. 8
. 10
.17

TABLES
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.

J2 Pin Descriptions . . . . . . . . . . . .
AT Host Electrical Characteristics . . . . . .
Data BusSDO-16, INTRQand I/OCS16 CircuitA
Schmitt Trigger Inputs lOR, lOW Circuit B
Task File Map . . . . . .
Standard Command Opcodes
Identify Drive Command
Error Reporting . . . . .

Western Digital Corporation

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Caviar AC140lAC280 Technical Reference Manual
Radio Frequency Interference StateJ1'lent
This Western Digital product has been verified to comply with the limits for a
Class Bcomputing device pursuant to Part 15, subpart B, of FCC rules. This does
not guarantee that interference will not occur in individual installations.
Western Digital is not responsible for any television, radio, or other interference
caused by unauthorized modifications of this product.
If interference problems do occur. please consu It the system equ ipment owner's
manual for suggestions. Some of these suggestions include the relocation of
the computer system away from the television or radio. or placing the computer
AC power connection on a different circuit or outlet.
This digital apparatus does not exceed the Class B limits for radio noise for digital
apparatus set out in the Radio Interference Regulations of the Canadian Department
of Communications.

Western Digital Corporation

Description and Features

1.0
1.1

DESCRIPTION AND FEATURES
General Description
The Caviar series of Western Digital intelligent drives provides 42/85 megabytes of
storage in a 3.5-inch form factor and low profile 1-inch height. Designed for use in
AT-compatible systems,· Caviar is the premier storage solution that achieves
unsurpassed reliability and optimum performance.
Caviar features Cache Flow, Western Digital's exclusive multi-segmented adaptive
disk caching system, which dynamically partitions the 8-Kbyte (32-Kbyte optional)
buffer and adapts during disk operations to the optimum caching mode to
dramatically enhance read/write performance. To meet the demands of high
performance 80386, 80386SX, and 80486 systems, Caviar has an average seek time
of less than 17 milliseconds. When coupled with Western Digital's 7600 core logic
chipset. Caviar achieves higher data transfer rates with zero wait states, which
means even faster system performance.
Caviar drives are preformatted (low-level), and defects are mapped out before
shipment, ensuring defect-free media. Additional Caviar features include linear
logical/physical address translation, automatic head parking, embedded servo
control data on each track, and 56-bit error correction code.
Western Digital offers reliable, cost-effective storage solutions by integrating design
and manufacturing in a process known as "interarchitecture." Critical functions,
including storage, intelligent drive control. core logic, video, and communication
functions, are integrated into a variety of platform-specific solutions. Designers in
each arena work closely with each other, developing solutions with a first-hand
knowledge of all the components that interact in the platform. This interaction
between component designers means Western Digital can guarantee compatibility
and build in exclusive functionality.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

1.2

Advanced Product Features
CacheFlow
Designed exclusively by Western Digital to minimize disk-seeking operations and
rotational latency delays, CacheFlow is the industry's first adaptive,
multi-segmented disk caching system. CacheFlow constantly evaluates not only the
size of the data request but the type of data request, that is, whether the application
is sequential, random, or repetitive.CacneFJow then dynamically partitions the
Caviar's 8-Kbyte (32-Kbyte optional) RAM buffer into equal-sized segments and
selects the appropriate caching mode for optimum system performance.

Automatic Head Parking
Head parking is automatic with the Caviar series of intelligent drives. On
power-down, the heads retract to a safe, non-data landing zone and lock into
position, improving data integrity and resistance to shock.

Advanced Defect Management
The Caviar is preformatted (low level) at the factory and comes equipped with afull
complement of defect management characteristics. Extensively tested during the
manufacturing process, media defects found during intelligent burn in are mapped
out with Western Digital's high performance defect management technique. No
modifications are required before installation.

Embedded Sector Servo Control
The Caviar records servo data on every sector for precise head positioning by the
servo.

Dual Drive Operation
The Caviar supports dual drive operation by means of a "daisy chain" cable assembly
and configuration options for master or slave drive designation.

InteUigent Drive
The Caviar does not require a slot-mounted controller card. The hard disk has the
controller circuitry and 4O-pin ATA IDE connector attached directly to the drive.

Western Digital Corporation

Description and Features
Translation
The Caviar provides a linear disk address translator to convert logical sector
addresses to physical sector addresses which means Caviar guarantees
compatibility to any drive set-up parameter.

Error Recovery
Caviar uses a 56-bit Error Correction Code (ECC) for automatic detection and
correction of errors in the data field.

Guaranteed Compatibility
Western Digital performs extensive testing in its Functional Integrity Testing Labs
(FIT Lab) to ensure compatibility with all AT-compatible computers and standard
operating systems.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

Western Digital Corporation

SpecifICations

2.0 SPECIFICATIONS
2.1

Performance Specifications

Average Seek •
Track-to-Track Seek
Maximum Seek
Index Pulse Period
Average Latency
Rotational Speed
Controller Overhead
Data Transfer Rate Buffer to Disk
Data Transfer Rate Buffer to Host**
Interleave
Buffer Size
Error Rate Soft
Error Rate Hard
Spindle Start lime
Spindle Stop lime
Start/Stop Cycles
Acoustics···
Idle Mode
Seek Mode

•

Sub-17 Milliseconds
6 Milliseconds
28 Milliseconds
16.67 Milliseconds (0.1 %)
8.34 Milliseconds (0.1 %)
3595 Revolutions/min. (0.1 %)
0.3 Milliseconds average
1.2 MBytes/sec
4.5 MBytes/second
1:1
8-Kbyte (32-Kbyte optional)
Static RAM
<1 in 1010 bits read
<1 in 1012 bits read
5 seconds typical
15 seconds maximum
6 seconds
10,000 cycles minimum
40 dBA at 1 meter
42 dBA at 1 meter

"Average Seek" is determined by dividing the total time required to seek
between all possible ordered pairs of track addresses by the total number of
these ordered pairs.

** "Data Transfer Rate from the Buffer to the Host" is based on the sustained
transfer of buffered data in MBytes per second .
• ** The maximum difference between adjacent octave bands is 12 db (no pure
tones).

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual

2.2

Physical Specifications
Physical
Specifications

Caviar AC280

Caviar AC140

Recommended Setup
Parameters·

980 x 10x 17
(CYl x heads x SPT)

980x5x17
(CYl x heads x SPT)

Formatted Capacity

85.3 MBytes

42.7 MBytes

Interface

4O-pin PCIAT

Actuator Type

Rotary Voice Coil

Number of Disks

Data Surfaces

Number of Heads

Number of Cylinders

1082

Average Track Density

1,405 TPI

1,405TPI

Formatted Cylinder
Capacity

78,848 bytes

39,424 bytes

Bytes per Sector

512

User Sectors per Drive

166,628

83,314

User Sectors per
Cylinder

(4x39)-2=154

(2 x 39) - 1 = 77

PhySical Sectors per
Track

Servo Type

Embedded Sector
Servo

Recording Method

2,7 Rll

Recording Density

31,591 BPI

Flux Density

21,061 FCI

Ecc

56 bit

Head Park**

Automatic Head
Parking

Western Digital Corporation

SpecifICations

Do not exceed the maximum sector capacity (83.314 sectors for Caviar AC140.
166.628 sectors for Caviar AC280) when specifying the number of cylinders.
heads. and sectors per track. Exceeding the specified limits resu Its in the
drive parking, spinning down and the disk controller returning the ID NOT
FOUND error to the host.

** Seeking to a cylinder greater than or equal to cylinder 981 (translation mode:
'~ 980 cylinder.s X 10 heads X 17sector.s/track for the Caviar AC280, or 980
cylinders x 5 heads x 17 sectors per track forthe Caviar AC140) parks the
read/write heads and spins down the drive. Turning the system power off
causes the Caviar to perform an automatic head park operation.

2.2.1

2.2.2

Physical Dimensions
Height

1.00 (±O.02) Inches (2.54 ±O.05 cm)

Length

5.75 (±O.02) Inches (14.60 ±O.05 cm)

Width

4.00(±O.02)lnches (10.16±O.05cm)

1Ve~t

I Weight

Western Digital Corporation

11.12 Pounds ( 508 grams)

Caviar AC140lAC280 Technical Reference Manual

2.2.3

Mechanical Specifications
Figure 2·1 shows the mounting dimensions and locations of the screw holes for the
Caviar intelligent drive.

~!.---------------------~ooo--------------------~.;
: :.

3.750

:. o
o

'+'
••••••••
\:!!I ••••••••

;"i"'-",-"
2.376

_ ._.1_ . _ _._._

I
.I

_ _......,--,--_ _ _ _@_+__ ._••

ltoOOOJ.~

Figure 2-1. Caviar AC140/AC280 Mounting Dimensions

Western Digital Corporation

SpecifICations

2.3
2.3.1

Electrical Specificatioll8
12 VDC and 5 VDC Typical Current
Operation

Input Voltage

Power

12VDC

5VDC

(±5%)

Read

0.350 A

0.220 A

5.30W

Write

0.350 A

0.220 A

5.30W

Random
Seek

0.375 A

0.220 A

5.60W

Spin up·

1.20A

0.200 A

15.4OW

1.40 A max

0.25Amax

*Note: Spin-up mode begins at zero RPM spindle speed and ends with
normal spindle speed. A complete spin-up operation typically requires
five seconds. Maximum spin-up power is dissipated during the first
two seconds of spin up. Refer to Figure 2-2

2.3.2

2.3.3

IUpple
Ripple

Maximum

Frequency

12VDC

200 mV (peak-to-peak)

0-20 MHz

5VDC

100 mV (peak-to-peak)

0-20 MHz

Power Connectors and Cables
Power Connector

4-Pin MOlEX (PIN 15-24-4041 or equivalent)

Mating Connector

Body (AMP 1-480424-0 or equivalent)
Pins (AMP 60619-4 or equivalent)

Power Cable Wire Gauge

1BAWG

Western Digital Corporation

Caviar AC140lAC280 Technical Reference "Manual

AC280
1.20
1.16
1.08
1.00

m
p

0.80

a
0.60

0.40

0.20

0.00

_ _" "_ _"&"'_ _' - _ - - "_ _- '
1.00
2.00
3.00

~_-L

nme In aeconda

Figure 2-2. +12V Current Draw During Spin Up (Master Mode)

2.3.4

Grounding
The mounting screws connect the head disk assembly and the printed circuit board
to the system chassis ground. Therefore. no external grounding strap is required.

Western Digital Corporation

SpecifICations

2.4

Environmental Specifications
Note: Non-operating limits indicate where device damage can occur.
Operation at these limits is not intended and should be limited to
the conditions specified in the operating characteristics.

2.4.1

Shock and Vibration
Shock

Operating

10Gs

Non-operating

75Gs

Note: Half-sine wave of 11 msec duration, two half-sine waves per second
maximum with no non-recoverable e"ors.
Vibration
Operating

5-17 Hz, 0.034" (double amplitude)
17-400 Hz, 0.75G (Peak)

Non-Operating

5-20 Hz, 0.195" (double amplitude)
20-500 Hz, 4G (Peak)

Sweep Rate

One-half octave/minute

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

2.4.2

Temperature and Humidity
Temperature
Operating

5° Ctc 50° C
10· C/hour Therma I Gradient

Non-Operating

-40° Cto SO° C
20· C/hour Thermal Gradient

Note: The system environment must allow sufficient air flow to maintain the
casting temperature at or below 55° C
Relative Humidity
Operating
Maximum Wet Bulb
Non-operating
Maximum Wet Bulb

2.4.3

8% to 80% RH non-condensing
2So C
5% to 95% RH non-condensing
2SoC

Atmospheric Pressure
Altitude - Operating

-1000 to 10,000 feet

Altitude - Non-Operating

-1000 tc 40,000 feet

Western Digital Corporation

Speci[rcations

2.5

Agency Approvals
The Caviar meets the standards of the following regulatory agencies:
Underwriters laboratories
UL-Standard 1950, Standard for Safety, Information Processing and Business
Equipment; File Number - E101559
Federal Communication Commission
Verified to comply with FCC Rules for Radiated and Conducted Emission, Part
15, Subpart B, for Class BEquipment
Canadian Standards Association
CSA-Standard C22.2, No. 950 -M89 Information Processing and Business
Equipment; File Number LR 68850
TUV Essen laboratories
IEC 950 (EN 60 950) Safety of Information Technology Equipment Including
Electrical Business Equipment

2.6

Reliability Specification
MTBF

100,000 Power-on hours

MTTR

10 Minutes typical

Component Design Life

5 Years

Warranty Period

Two Year

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

2.7

Compatibility Per Functional Integrity Testing
The FIT lab™ or Functional Integrity Testing lab ensures that the Caviar has
guaranteed compatibility. Before any drive is released to the factory, it must
complete atwo-phase FIT process. The FIT process results in a matrix compatibility
test which includes:
•
•
•
•

•

Host systems
Other intelligent drives
Operating systems (e.g., DOS, Novell, Xenix, Unix, OS/2)
Application programs (e.g., word processing, data base management, spreadsheets, desktop publishing, CAD and graphics in single and multi-user environments)
Benchmarks (e.g., third party benchmarks such as Core Test and P.C. Bench)

In the first phase of FIT the Caviar is run through the following tests:
•
•
•

Mechanical mounting
EMI susceptibility
BIOS compatibility with third party and Western Digital hardware

In addition to these tests, there are five types of tests that are run in both Phase I
and Phase II:
•
•
•
•
•

Alpha tests (Western Digital Proprietary compatibility test suite)
Benchmark tests
Peripheral compatibility tests
Host compatibility tests
Operating system compatibility tests

Western Digital Corporation

Specifications
The selection of host systems is based upon market representation and systems that
have previously presented unique compatibility problems. Examples of host systems
used in FIT include:
•
•
•

Extremely fast units with very short timing windows
Specific OEM systems that utilize unique operating systems
Additional host systems supplied by OEMs requesting FIT

The five types of tests that are run in both Phase I and Phase II are described below:

Alpha Tests
The Alpha Tests exercise all of the read. write and seek functions of the firmware
in both the physical and translation modes.

Benchmark Tests
The benchmark tests are listed in the following table:
Bench Test
Bench 23
Bench 26
Core Test
MasmTest
ASM51 Test
dBase Test
MS ·C· Compiler Test
File copy and compare test
Wordstar Word search test
Wordstar Spelling test
Wordstar loading and saving test
lotus Test
Testdisk

Western Digital Corporation

Caviar AC140/AC280 Technical Reference Manual

Peripheral Compatibility Tests
The peripheral compatibility tests verify the drive's operation with other intelligent
disk drives, i.e., dual-drive compatibility.

Host Compatibility Tests
The host compatibility tests verify the disk's operation with a variety of host
computers. The tests include formatting, diagnostics, benchmark testing and file
··copy and compare.

Operating System Compatibility Tests
The operating system compatibility tests verify the drive's operation in various
operating systems including DOS, Novell, Xenix, Unix and OS/2.

Western Digital Corporation

Principles Of Operation

3.0

PRINCIPLES OF OPERATION
This section describes the principles of operation of the Caviar from the following
viewpoints:
e Drive electronics
e_. Head disk assembly (HDA)

3.1

Block Diagram
A block diagram of the Caviar is provided in Figure 3-1.

PULSE DETECTOR

IIICROPROCESSOR

Figure 3-1. Block Diagram

Western Digital Corporation

Caviar AC140/AC280 Technical Reference Manual

3.2

Drive Electronic8
Caviar's intelligence resides in the specialized electronic components mounted on
the four-layer printed circuit board assembly. These devices perform the intricate
operations described in section 4. The Caviar consists of the following drive
electronic components:
•
•
•
•
•
•
•
•

3.2.1

WD42C22 Wincl1ester Disk Controller
BufferRAM
WD60C11 Servo Controller
WD10Cn Data Separator
Microprocessor ROM and RAM
Pu lse Detector
Spindle Motor Driver
Actuator Driver

WD42C22 Winchester Disk Controller
TheWD42C22 integrates a high performance, low cost Winchester
formatter/controller, CRC/ECC generator/checker, host interface, and buffer
manager into a single, 84-pin POFP device. The controller/formatter encodes and
decodes data to and from the WD10C23 data separator. The CRC/ECC
generator/checker calculates ECC for the data field. The host interface directly
connects to the host system bus via intemal12 rnA drivers. The buffer manager
controls the buffer RAM and handles the arbitration between the host interface and
drive controller.

3.2.2

Buffer RAM
A 8-Kbyte (32-Kbyte optional) static RAM buffer enhances data throughput by
buffering sector data between the Caviar and the AT system bus. The RAM only
buffers readlwrite data and ECC information. The buffer is accessed by two
channels, each having a separate 15-bit address and byte-count register. The
channels operate simultaneously, accepting read and write operations from two data
paths. The address access time for the buffer RAM is 120 ns (maximum).

Western Digital Corporation

Principles

Of Operation

I
rj

3.2.3

WD60Cll Servo Controller
The WD60C11 provides servo discrimination, track address capture, and measures
servo burst amplitudes. A servo burst is a momentary servo pattern used in
embedded servo control implementations, usually positioned between sectors. The
WDSOC11 also provides spindle motor control.

3.2.4

WD lOC23 Data Separator
The WD10C23 handles the sensitive read/write signals between the WD42C22 and
the read channel circuitry at a rate of 12 megabits-per-second. Read data refers to
previously written data, with phase, frequency, and write splice noise. The WDl OC23
removes the noise and sends clean digital read signals to the WD42C22. The
WD10C23 conditions write data to be recorded on the drive. Data to and from the
WD42C22 is precisely clocked to the WD10C23.

3.2.5

Microprocessor ROM and RAM
A 1S-bit microprocessor controls and coordinates the activity of the HDA and the
WD42C22. The microprocessor receives and sends command or status information
over an internal mu Itiplexed address/data bus. The microprocessor monitors spindle
and actuator activity until the WD42C22 asserts the microprocessor's interrupt line.
The WD42C22 asserts the interrupt when the host writes to the Command Register
or at the end of either a host or disk transfer. The microprocessor uses 8 Kbytes (32
Kbytes optional) of external ROM and 2 Kbytes of external static RAM. Firmware
controlling all these functions, including the adaptive multi-segmented cache,
resides in the microprocessor's external 32-Kbyte ROM.

3.2.6

Pulse Detector
The pulse detector amplifies and qualifies the RLL-encoded signals from the
preamplifier on the flex circuit. Pulse qualification in read mode is accomplished
using level qualifications of differentiated input zero crossings. An AGC amplifier
compensates for variations in head preamp output levels, presenting a constant
input level to the pulse qualification circuitry.
In write mode, the circuitry is disabled. The AGC gain stage input impedance
switches to a lower level to allow fast settling of the input coupling capacitors during
a write-to-read transition.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

3.2.7

Spindle Motor Driver

The three-phase spindle motor driver can supply up to 1.4A to the spindle motor.
The driver is controlled by the WD60C11 Servo Controller.

3.2.8

Actuator Driver

The actuator driver provides precision placement of the read/write heads by means
of the voice coil motor.- A digital-to-analog converter in the WD60C11 controls this
H-bridge driver, which uses +l2V, +5V and ground.

Western Digital Corporation

Principles Of Operation

Figure 3-2. Mechanical Exploded View

Western Digital Corporation

Caviar AC140lAC280 Technical Re(erence Manual

3.3

Head Disk Assembly (HDA)
The functional parts of the HDA are mounted to a common die-cast housing with a
sealed cover. The assembly provides exact mechanical relationships between the
spindle. headstack. and voice coil through precise machined dimensions on the
housing. A clean environment is also maintained within the HDA enclosure.
The HDA tonsists of the following mechanical subassemblies:
•
•
•
•
•
•

3.3.1

Base/Cover Assembly
Spindle Motor
Disk Stack Assembly
Headstack Assembly
Voice Coil Assembly
Air Filtration System

Base/Cover Assembly
The single-piece cast base provides a mounting platform for the components of the
assembly. The base/cover assembly has machined mounting surfaces for the
spindle motor. voice coil. and pivot. To ensure a Class 100 environment within the
HDA, a tape seal is wrapped around the base and cover castings.

3.3.2

Spindle Motor
The spindle motor assembly consists of a brush less three-phase motor. spindle
bearing assembly. disk mounting hub. and a ferrofluid magnetic seal. The entire
spindle motor assembly is completely enclosed in the HDA and bolted to the base
casting. The motor rotates the spindle shaft at 3595 RPM.
Proprietary spindle electronics sense motor speed and angular position by
monitoring the spindle motor's back electromotive force (BEMF). Using BEMF
sensing. instead of the conventional Hall effect or inductive motor position sensors.
lowers the power consumption and increases reliability. Motor driver circuits
dynamically brake the spindle during motor spin down.

Western Digital Corporation

Principles Of Operation

I
il
i,J

3.3.3

Disk Stack Assembly
The disk stack assembly consists of disks, disk spacers, and a disk clamp. In the
Caviar AC2BO, two disks and one spacer are placed on the hub and clamped into
place. The Caviar AC140 has one disk and a spacer.
The platters of the Caviar drives are thin inflexible aluminum disks. Each disk is
plated with a layer of nickel, followed by the magnetic media coating. A thin film
of-carbon overcoat protects the magnetic material against wear and abrasion from
the read/Write heads. The final lubricant layer provides further protection between
the read/write heads and media during take-offs and landings.

3.3.4

Headstack Assembly
The headstack assembly consists of the following mechanical subassemblies:
•
•
•

Read/Write Heads
Actuator Arm
Flex Circuit

ReadIWrite Heads
The metal-in-gap (MIG) read/write heads consist of a mini-composite slider
assembly mounted on a Whitney class suspension system. MIG heads have
sputtered metal in the head gap. The metal in the gap allows greater sensitivity to
magnetic flux reversals than normal composite heads. The mini-composite slider is
a small block of ceramic material. Bonded into the outer rail of the mini-slider is the
read/write head. The read/write head induces voltages in a coil mounted above
the head. A linkage between the actuator block and the read/write heads, the
flexure, connects the slider to the actuator arm. The Caviar actuator is statically
balanced about the pivot center.

Actuator Arm Assembly
The actuator arm assembly is illustrated in Figure 3-2. This assembly is
servo-controlled and derives position information from the sector servo data
embedded in all disk tracks.

Flex Circuit
The head conductors are flex cables routed through the flex circuit assembly inside
the HDA. The flex circuit assembly transfers signals between the read/write heads
and the voice coil actuator motor. A preamplifier IC, located on the flex circuit,
maximizes the read/write heads' signal strength while minimizing noise.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

3.3.5

Voice CoB Assembly
The voice coil assembly consists of an upper and lower magnet plate, a flat rotary
coil, a bidirectional crash stop, and a pivot bearing.
The pivot assembly fits in the actuator block bore.

3.3.6

Air FBtration System
It is absolutely essential that air Circulating within the drive be particle free. The
HDAis assembled in a Class 100 purified air environment, then sealed with tape.
To retain this clean environment, the Caviar is equipped with two filters. One filter,
the recirculating filter, cleans the air within the HDA. The recirculating filter traps
any particulates which may be generated during head landings or take-ofts.
Mounting the recirculating filter next to the disk places the filter in the direction of
the air flow. This strategic placement of the filter allows the rotating disks to act as
an air pump forcing air through the recirculating filter. A second filter, the breather
filter, cleans any external air entering the HDA. The breather filter also equalizes
the internal and external air pressure. The breather filter is located on the bottom
of the HDA.

Western Digital Corporation

Advanced Product Features

4.0

ADVANCED PRODUCT FEATURES
Western Digital's Caviar series of intelligent drives provides achoice of data storage
capacities for the IBM PCIAT and compatibles with afull complement of advanced
product features. This section describes the following Caviar advanced product
features:
•
•
•
•
•

4.1

CacheFiow
Defect Management and Format Characteristics
Error Recovery Process
Translation
Dual Drive Option

CacheFlow
CacheFlow is the industry's first adaptive, multi-segmented disk caching system.

4.1.1

Purpose of CacheFiow
Cache Flow was designed by Western Digital to minimize disk seeking operations
and the overhead due to rotational latency delays. CacheFlow constantly evaluates
not only the size of the data request but the type of data request, that is, whether
the application is sequential. random or repetitive. Cache Flow then dynamically
partitions the Caviar's 8-Kbyte (32-Kbyte optional) RAM buffer into segments and
selects the appropriate caching mode for optimum system performance.

4.1.2

Benefits of CacheFiow
In a typical application, most host requests are for sequential data. CacheFlow's
adaptive design enables the Caviarto eliminate unnecessary disk seeking operations
by immediately implementing the Sequential mode once the data has been analyzed.
Applications such as "Core Test" or other benchmark utilities, on the other hand,
request the same data over and over again. CacheFlow provides a similar
performance edge by switching to the Repetitive mode of operation.

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual

4.1.3

CacheFiow Operation
Sequential mode is the default mode of operation for Cache Flow. The Caviar initially
partitions the 8-Kbyte (32-Kbyte optional) cache buffer into four caching segments.
As seeking operations begin, CacheFlow monitors the data's sector address and
sector count parameters as illustrated in Figure 4-1. CacheFlow then uses a simple
hit score algorithm to either increase or decrease the segment size for optimal
performance.
CacheFlow switches from Sequential mode to Repetitive mode during read
operations if the same block is accessed twice. Both modes read ahead after the
host-requested data has been read. By storing read-ahead data in the sector
buffers, the cache hit score can be significantly improved.
CacheFlow transfers host write data immediately to the sector buffer. A write
operation does not affect the buffer's cache segments since write data is not cached.
Only the sectors that are rewritten are purged from the buffer.

Western Digital Corporation

Advanced Product Features

Sequential

Mode Selected
(Default Mode)

Read
Host-Requested
Data

Monitor
Sector Address
and Sector Count
Parameters

1
Hit Score
Algorithm

I
Read Ahead
and Partition
New Segments

I+-

Host Reads
Data and
Empties Buffers

:+-

Sequential
Mode
Selected

Same
Blocks
Accessed
Twice?

Read Ahead
and Partition
New Segments

CD
Repetitive
Mode

Selected

f
1-+

Host Reads
Data and
Data Retained

Figure 4-1. Cache Flow Algorithm

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

4.1.4

Sequential Mode
The sequential caching mode is the standard read-ahead cache. After reading all of
the host-requested data into the segment(s), CacheFlow continues to read ahead
until the cache is full. After the host reads the requested data from the cache, a new
cache beginning is established following the last sector buffer returned to the host.
Based on the hit score algorithm, sequential mode adapts the number of segments
to optimize segment performance.
The default mode of four cache segments provides optimum cache performance. A
larger number of segments may limit cache effectiveness because the segment may
not store enough sequential sectors. A smaller number of segments may limit
effectiveness for random reads.

4.1.5

Repetitive Mode
The Repetitive caching mode resembles a static buffer. If the same blocks are
accessed twice, the Repetitive mode is selected. Repetitive mode also reads ahead
and can override the number of segments to build one large segment with the
maximum hit score. Unlike Sequential Mode, however, the sector buffers containing
the host-requested data remain valid after the hosts reads the data.

Western Digital Corporation

Advanced Product Features

4.2
4.2.1

Defect Management and Format Characteristic8
Defect Management

Every Caviar undergoes factory-level intelligent burn in. which thoroughly tests for
any defective sectors on the media before the drive leaves the manufacturing facility.
Following the extensive tests. a primary defect list is created. The list contains the
-··sector;,cylinder. and head·numbers for,all defects. The purpose ofthe sector/track
map is to manage the reallocation of spare sectors and tracks after they have been
assigned.
Western Digital offers a defect management utility called WDAT_IDE. to manage
any additional defects that may occur after prolonged use. Refer to section 8 for
additional information.
4.2.2

Format Characteristic8

The Caviar is shipped from the factory preformatted (low level) with all the defects
mapped out. This eliminates the need for the end-user to enter defects during
installation. No additional low-level formatting is required. although a high-level
format must still be performed.
In order to be compatible with existing. industry standard defect management utility
programs. the Caviar supports log ica Iformat. When the host issues the Format Track
command. the Caviar performs a logical version of this command in response to the
host's interleave table request for good and bad sector marking. (The logical format
does not corrupt the defect management that has been applied to the drive.)
If the host issues the Format Track command during normal operating modes. the
data fields of the specified track are filled with a data pattern of all zeroes. The
interleave table identifies any bad sectors on a given track. The interleave table
must contain 512 bytes of data. There are two bytes per sector for each entry in the
interleave table. The first byte marks the sector as good or bad. The first byte is set
to "OOH" to indicate a good sector or to "SOH" to indicate a bad sector. The second
byte designates the logical sector 10 number.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

4.3

Error Recovery
The Caviar has two means of error recovery:
•
•

Read/Write Retry Procedure
Extended Read Retry Procedure

The Caviar's retry procedures are implemented for the following errors:
•
•
•

10 Not Found (ION F)
Data Address Mark Not Found (DAMNF)
Error Correction Code (ECC)

The host may explicitly enable/disable retries in the Read, Write and Read Verify
commands. All other commands and the controller's internal disk read and write
operations are always performed with retries enabled. If retries are disabled, the
Caviar will not perform any disk controller retl'( operations and will immediately set
the appropriate bit in the Error Register.
The Read/Write Retl'( Procedure will perform up to ten basic retry operations to
succeed in reading or writing a specified sector. If recovery is achieved, the Caviar
continues executing the command. For a write operation, if these retries fail to
validate the 10 fields on a specified track, then an IDNF error is reported to the
Caviar's Error Register and the command is terminated.
For a read operation, the Caviar will perform the Extended Read Retry Procedure to
recover the data. The Extended Read Ret!'( Procedure employs up to sixteen
combinations of early/late window shifts and positive/negative track offsets to
recover read data. This procedure is used for the IDNF, DAMNF and ECC errors. If
the retry operation is successful. the Caviar clears any existing window shift or track
offset before continuing with the command. If the retry operation failed, the Caviar
reports the appropriate error to the Error Register, with the exception of an ECC error.
In the case of an ECC error, the drive performs up to eight retries to obtain two
consecutive matching syndromes. If matching syndromes are found, and the error
spans eleven bits or less, the data is corrected, the CORR bit is set in the host's status
register, and the command continues. If two consecutive matching syndromes are
not found, or if the error spans more than eleven bits, the Caviar reports an ECC
(uncorrectable) error to the Error Register.

Western Digital Corporation

Advanced Product Features

4.4

Tr8118lation
The Caviar implements linear address translation. The translation mode and
translated drive configuration are selected by using the Set Drive Parameters
command to issue head, and sector/track counts to the translator. The product of
the cylinder, head, and sector/track counts must be equal to or less than the
maximum number of sectors available to the user. The maximum number of sectors
per 'drive for the" Caviar AC140 andAC280 are B3,314 -and·166;"62B sectors,
respectively. Each sector consists of 512 bytes.
The minimum value for any translation parameter is one. The maximum value for
any translation parameter is as follows:
Sectors/track
Heads
Cylinders/drive

63
16
1024

The values in the Sector Count Register and the SOH Register determine the sectors
pertrack (SPTI. and heads. Regardless of the values of the SPT and the heads, Caviar
will always be in the translation mode. Refer to section 2.2 for the recommended
setup parameters.

4.5

Dual Drive Option
The Caviar supports dual drive operations by means of configuration options for
master or slave drive designation. Ajumper must be placed in the drive's option area
for both master and slave configurations. Connection to the host is implemented by
means of a daisy-chain cable assembly. These configurations are described in
section 6.
The SOH Register contains the master/slave select bit for the Caviar. The OASP
Signal is atime-multiplexed indicator of "drive active or slave present" on the Caviar's
I/O interface. At reset, this signal is an output from the slave drive, and an input to
the master drive, showing that aslave drive is present. For all times other than reset
and drive diagnostics, OASP is asserted at the beginning of command processing
and released upon completion of the command. If the master drive option has been
configured, the Caviar will not respond to commands or drive status on the interface
when the slave bit is selected in the SOH Register. -

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

Western Digital Corporation

Host Interface and AT Command Set

5.0

HOST INTERFACE AND AT COMMAND SET
This section describes:
• J2 pin assignments
• Caviar registers
• .£aviar mmmands
• Host interface read timing
• Host interface write timing
• Error reporting

5.1

J2 PIN ASSIGNMENTS
The Caviar interfaces with the host 110 bus via the 4O-pin connector (J2) illustrated
in Figure 5-1. Table 5-1 identifies the pin numbers of the J2 connector and the
corresponding signal names and signal functions.

J2
39

I•••••••••••••••••••••
0
••••••••• 0 ••••••••• 0
2

531
··~I
•••

.....
J3

4 3 2 1

642

C ErnpIV box. represent removed pins.
J2 pin 20 k~ed
Row of pins removed III separate J2 from J8

L+12V
GN)

+5V

Figure 5-1. Standard Factory Connectors

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual

Pin
Number

Mnemonic Signal Name

RST

Reset

3,5.7,9,
11,13,15,
17

HD7-O

Host Data
Bus Bits 7-0

VO
I

4,6,8,10,12, HD8-15
14,16,18

Host Data Bus
Bits 8-15

2,19,22,
GND
24,26,30,40

Ground

Function
Initializes the Caviar when
asserted.

I/O The tristate, 8-bit.
bidirectional bus for
transferring status and control
information between the host
and the Caviar.
I The upper data bus is used
during data transfer only
(16-bit data transfer).

Key - Not connected.

21,27,
28,29

Reserved - Not
connected

lOW

i7QWrite

I The host controller asserts
lOW when a data or control
byte is written to the Caviar.

lOR

I/O Read

I The host controller asserts
lOR when a data or status
byte is read from the Caviar.

INTRQ

Interrupt Reques1

0 The Caviar asserts INTRQ to
request interrupt service from
the host.

I/OCS16

1[0 Channel
Select 16

0 Identifies data transfers to or
from the host as 16 bits wide.

Table 5-1. J2 Pin Descriptions

Western Digital Corporation

Host Interface and AT Command Set

Pin
Number

Mnemonic Signal Name

35,33,36

HAO-2

Host Address
Bus

I AO, A1 and A2 address I/O
ports 0 through 7.

PDIAG

Passed
Diagnostics

I/O Output from slave drive when
it has passed its diagnostics.
Input to master drive.

HCSO

Host Chip Select
0

I The host asserts CSO to
address and communicate
with the Caviar on the I/O
channel.

HCS1

Host Chip Select
1

I The host asserts CS1 to
address and communicate
with the Caviar auxilliary
registers.

DASP

Drive
Active/Slave
Present

Function

I/O This open collector output is a
time multiplexed Signal
indicating drive active or slave
present. At reset, this signal is
an output from the slave drive
and an input to the master
drive, showing that a slave
drive is present. For all times
other than reset and drive
diagnostics, DASP should be
asserted by the master and
slave drives during command
execution.

Table 5-1. J2 Pin Descriptions (cant.)

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

Pin
Number

Mnemonic Signal Name

3-18

DO - D16

Host Data Bus

Bidirectional- Circuit A

35
33
36

SAO
SA1
SA2

Host Addr Bus
AO, A1 and A2

Input - Circuit B

lOW

I/O Write

Input - Circuit B

iDA

I/O Read

Input Circuit B

HINTRQ

Interrupt
Request

Output - Circuit A

IOCS16

I/O Channel
Select 16

Output - Circuit A

PDIAG

Passed Diag

Output - Circuit A
Open collector

37
38

CSO

card Selects

Input - Circuit B

HACT

Host Active

Output - Circuit A
Open collector

CS1

Circuit Definition Code

Table 5-2. AT Host Electrical Characteristics

Western Digital Corporation

Host Interface and AT Command Set

Symbol Parameter

Min

Type

Max

Units

Test

loh

High level
Output Current

-5

rnA

2.4 volts

101

low level
Output Current

rnA

0.4 volts

Vih

High level
.Input-Voltage

Vii

low level
Input Voltage

Voh

High level
Input Voltage

Vol

low level
Input Voltage

Iii

Input leakage

V
0.8

2.4

V
V

VCC=MIN
Vih=Vih min
Vil=Vil max

0.4

VCC=MIN
Vih=Vih min
Vil=Vil max
101= 12 rnA

±10

VCC =0 to VCC

Table 5-3. Data Bus SOO-16, INmO, and I/OCS 16; Circuit A

Western Digital Corporation

Caviar AC140lAC280 Technical Reference· Manual

Symbol Parameter

Min

Type

Max

Units

Test

Vt+

High Level
Threshold

1.5

1.7

2.0

VCC=TYP

Vt-

Low Level
Threshold

0.6

0.9

1.1

VCC= TYP

Vik

Input Clamp
···Voltage

-0.5

VCC=MIN

VCC=MIN
(VT +-VT-)

VCC=MAX

Hysteresis

0.4

0.8

Input Current
MAX Input
Voltage

Vol

High Level
Input Voltage

Iii

Low Level
Input Current

VCC=MIAX
Vih=2.7V
uA

VCC=MAX
Vil=0.4V

Table 5-4. Schmitt ffigger Inputs lOR, lOW,· Circuit 8

Western Digital Corporation

Host Inteiface and AT Command Set

5.2
5.2.1

Host Interface Registers
Register Address Map
The task file occupies the address space shown in Table 5-5. The task file's ten
registers pass command, status, and data information between the host and the
Caviar. All registers are eight bits wide, except for the Data Register which is 16
bits wide. ,,·These registers are accessed via control lines HAO-2,CSO, and CS1.
When the drive is busy, only the Status Register is accessible with CSO active. The
Alternate Status Register is always accessible with CS1 active.
Registers

CSD

CS1

HA2

HA1

HAD

Read
Function

Write
Function

Data

Error

Sector
Count

Sector
Number

Cylinder
Low

Cylinder
High

SOH

Status

Command

Ait Status

Fixed Disk
Control

Oigitallnput

Table 5-5. Task File Map

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

5.2.2

Data Register
The Data Register holds the data to be transferred to or from the host on read and
write commands. All data transfers are high speed and 16 bits wide, except for the
ECC bytes transferred during read long or write long commands which are B bits
wide.

5.2.3

Error Register
The Error Register contains an error code that indicates a particular type of failure.
Not used.
The Error Register contains an error code that indicates a particular type of failure.
The register contains a valid error code only if the Status Register error bit 0 is set.
The only exceptions are power-up and issuance of a diagnostic command. In these
cases the Error Register contents are valid regardless of the condition of the Status
Register's error bit. These two exceptions cause the following error values:
01 =No error
02 = Not applicable
03 = Buffer RAM error
04 =WD42C22 register error
05 = Microprocessor internal RAM error or ROM checksum error
ax =Slave drive failed

If a slave drive is present and has failed its diagnostic, SOH is ORed with the master
drive's status bits. To read the slave's error code, the host should select the D bit in
the SDH Register. In all other cases the Error Register bits are defined as follows
when asserted:

Western Digital Corporation

Host Interface andAT Command Set

Bit Positions
7

BBD

ECC

IDNF

TKO

DAMNF

BBD

Bad Block Detected

ECC

Error Correction Code (uncorrectable error detected)

IDNF

ID Not Found (target sector could not be found)

Aborted Command

TKO

Track 0 (unable to find a valid track 0)

DAMNF

Data Address Mark Not Found

Error Register Bit 7 (BBD)
If bit 7 is asserted. it indicates that the Caviar detected a bad block mark in a sector
ID field while attempting a read or write.
Error Register Bit 6 (ECC)
If bit 6 is asserted. it indicates that the Caviar detected an uncorrectable data error
while reading a target sector.
Error Register Bit 5
Not used.
Error Register Bit 4 (lDNF)
If bit 4 is asserted. it indicates that the Caviar was unable to locate a valid ID field
for the specified logical address.
Error Register Bit 3
Not used.

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual
Error Register Bit 2 (AC)
If bit 2 is asserted, it indicates that the Caviar has terminated the current command.
This is due to one of the following:
•
•
•
•

Illegal write current condition (write fault)
No seek complete
Drive not ready condition
Invalid command code

Error Register Bit 1(TKO)
If bit 1 is asserted, it indicates that the Caviar was unable to locate a valid track 0
indication. This bit is only valid after a Recalibrate command.
Error Register Bit 0 (DAMNF)
If bit 0 is asserted, it indicates that the Caviar was unable to locate a valid Data
Address Mark (DAM) within a given number of byte times after the 10 field.

5.2.4

Write Precompensation Register
The Write Precompensation Register is ignored during normal write operations since
the Caviar automatically determines the proper write precompensation. The
contents of this register are only used by the Set Buffer Mode command.

5.2.5

Sector Count Register
The Sector Count Register indicates the number of sectors to be transferred during
a read, write or verify operation. (A value of zero indicates a count of 256 sectors.)
During a format operation, this register contains the number of sectors per track
(SPT) and must correspond with the values indicated by the Set Drive Parameters
command. When read by the host, this register indicates the number of sectors, if
any, that were not read or written during the previous command. The Sector Count
Register contents are used by the following commands:
Read Sector
Write Sector
Format Track
Read Verify
Set Drive Parameters
Read Multiple
Write Multiple
Set Multiple

Western Digital Corporation

Host Interface and AT Command Set

5.2.6

Sector Number Register
The Sector Number Register defines the target sector for the current operation when
written to by the host. The contents of this register are used by the following
commands:
Read Sector
Write Sector
Read Verify
Read Multiple
Write Multiple

5.2.7

Cylinder Low/Cylinder High Registers
The Cylinder low/Cylinder High Registers contain the logical cylinder addresses for
commands that require an address. These registers also selVe as a 16-bit command
register for extended commands. Extended commands are beyond the scope of this
document. The Cylinder low Register contains the eight low-order bits of the
starting cylinder number. The Cylinder High Register contains the three high-order
bits of the starting cylinder number.

Bit Position
4
3

7
LSB

6
lSB

5
LSB

lSB

LSB

2
lSB
MSB

1
lSB
MSB

0
lSB
MSB

The contents of the Cylinder low/Cylinder High Registers are used by the following
commands:
Seek
Read Sector
Write Sector
Format Track
Read Verify
Read Multiple
Write Multiple

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

5.2.8

SDH Register
The SOH Register selects the drive and head number for a particular operation. The
bit assignments are as follows:
Bit Positions
7

SS1

5
··SSO

3
°HS3

HS2

HS1

0
HSO

SS1 - SSO =Sector Size (512 byte) =01

o=Drive Select Bit
HS3 - HSO =Logical Head Select Bits
SS1 and SSO (sector size bits) are set to 0 and 1, respectively. This setting fixes the
sector size at 512 bytes/sector. When the 0 bit is set, the slave drive is selected.
When the 0 bit is reset, the master drive is selected. HS3 -HSO specify the desired
logical head number. The contents of this register are used by the following
commands:
Recalibrate
Seek
Read Sector
Write Sector
Format Track
Read Verify
Set Drive Parameters

Read Multiple
Write Multiple
Set Multiple
Read Buffer
Write Buffer
Identify Drive
Set Buffer Mode

Western Digital Corporation

Host Interface and AT Command Set

5.2.9

Statu8 Register

The Status Register contains the drive's status following a command. Reading the
Status Register resets any pending interrupt. These are the bit assignments:

7
'BSY
BSY

6
ROY

Bit Position
4
3
--ORO
SC

CORR
'WF
Busy, indicates state of controller

'lOX

ERR

ROY

Ready, indicates state of target drive

Write Fault, indicates hazardous condition and aborts the
requested command

Seek Complete

ORQ

Data Request

CORR

Data Was Corrected

lOX

Index, index pulse of target drive

ERR

Unrecoverable error

Status Bit 7 (BSY)
This bit reflects the state of the controller. It is activated with a command request,
and it is deactivated at command completion. An attempt by the host to read any
task file register other than the Status Register while BSY = 1 results in the host
receiving the contents of the Status Register.
Status Bit 6 (ROY)
This bit reflects the state of the target drive. Arf.t command requested while ROY =
ois not honored. If a command request is executed and, if ROY becomes inactive,
the command is aborted.
Status Bit 5 (WF)
This bit indicates the occurrence of a write fault at the target drive. The presence
of awrite fault condition causes the current command request to abort. Subsequent
command requests are not honored until the condition clears.
Status Bit 4 (SC)
When set, this bit indicates the last requested seek has been completed.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual
Status Bit 3 (ORO)
This bit is high when data is to be transmitted between the host and target controller.
Status Bit 2 (CORR)
When this bit is set, it indicates that one or more of the sectors sent to the host had
a correctable error in the data field which was corrected via the ECC algorithm.
Status Bit 1 (lOX)
This bit reflects the target drive's index pulse.
Status Bit 0 (ERR)
When this bit is set, it indicates that an unrecoverable error has occurred. The host
may ascertain the type of error by reading the Error Register.

5.2.10
The host requests a controller/drive function by writing a function code in the
Command Register. The write action sets the BSY bit in the Status Register. See
section 5.3 for a description of all commands supported by the Caviar.

5.2.11

Alternate StatUI Register
The Alternate Status Register provides the same information (without resetting a
pending interrupt) as the Status Register at a different address.

5.2.12

Fixed Disk Control Register
The Fixed Disk Control Register allows for a programmable controller reset and
provides the ability to enable or disable control of the fixed disk priority interrupt.

Bit Position
7
0

6
0

5
0

RST

IDS

0
0

The software-controlled reset bit (RST) maintains the fixed disk in a reset condition
as long as it is active (high). This bit must be turned on for a minimum of 5.0
microseconds, then off, to complete the reset function.

Western Digital Corporation

Host Interface and AT Commnnd Set
In dual drive configurations, the slave drive negates POIAG upon receiving the reset
signal and asserts PDlAG after completing its reset routines. The master drive, after
completing its reset routines and before negating BSY. wa.its up to 3 milliseconds
for the slave drive to assert POIAG.
The interrupt disable control bit (IDS) is used to disable (high) or enable (low)
controller interrupts. Disabling an interrupt does not clear a pending interrupt.
Disabling interrupts also tristates the INTRO line. Apending interrupt executes once
interrupts are re~nabled. Interrupts are disabled following a system master reset.

5.2.13

D~bdInputRegm~r

The Digital Input Register reflects the current state of the floppy change flag and the
fixed disk drive's select, head select and write gate signals. °If the floppy disk option
on the adapter board is not installed, bit 7 remains tristated.

7
DCG
DCG
WfG

6
WfG

Bit Position
4
3
5
HS3
HS2
HS1
Diskette Change Flag

1
DS2

0
DS1

Write Gate On

HS3,I:!&
HS1, HSO

Drive Head Select (binary)

DS2,DS1

Drive Select

Western Digital Corporation

2
HSO

Caviar AC140lAC280 Technical Reference ·Manual

•

Binary Opcode

'a
0

Command

:::a:::c

.a.

Recalibrate

Seek

Read

Write

Format Track

Read Verify

Execute Diag.

Set Drive
Parameters

Read Multiple

Write Multiple

Set Multiple

Reserved

Read Buffer

Write Buffer

Identify Drive

Set Buffer
Mode

iIC

L= Long mode bit

o= Normal mode. normal ECC functions
1= Long Mode

R= Retry bit

0= Error retries and ECC enabled
1= Error retries disabled

X= Don't Care

Table 5-6. Standard Command Opcodes

Western Digital Corporation

Host Interface and AT Command Set

5.3

Caviar ACl40/AC280 Commands
Table 5-6 lists the binary/hexadecimal codes specific to each command supported
by Western Digital's Caviar intelligent drive.
To initiate a controller operation, the host first transfers the pertinent information to
the task file and writes the command to the Command Register. The controller
" ~validates the "contents-of the"1ask file registers and then performs -the desired
function. The Caviar commands are briefly defined in the following subsections.

5.3.1

Recalibrate (lOB)
The Recalibrate command causes the Caviar to move the read/write heads from
anywhere on the disk to cylinder zero. Upon receipt of the command, the intelligent
drive asserts BSYand issues a seek to cylinder zero. The intelligent drive waits for
assertion of SEEK COMPlETE before updating the Status Register, clearing BSY, and
setting INTRQ. If the read/write heads cannot reach cylinder zero, the ERR bit and
TKO bit are asserted in the Status and Error Registers, respectively.
The Reca librate command does not invalidate any cache segments, but ensures that
any segment associated with the new physical cylinder number becomes the current
read/cache segment.
Register

Binary Opcode

7
Command

6
0

SDH

5
0

Write Precomp

Don't Care

Sector Count

Don't Care

Sector Number

Don't Care

Cylinder Low

Don't Care

Cylinder High

Don't Care

D =Drive Designation Bit

X =Don't Care

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual

5.3.2

Seek (708)
The Seek command positions the read/write heads over the cylinder specified in the
task file's cylinder number registers. When the command is received, the Caviar
asserts BSY in the Status Register, starts the seek operation, and sets INTRO. The
seek is not completed before the Caviar returns the interrupt. If BSY is cleared before
SEEK COMPLETE is asserted, the Caviar can receive another command. SEEK
COMPLETE is asserted when the heads reach the specified cylinder.
Seek does not invalidate any cache segments, but ensures that any segment
associated with the new physical cylinder number becomes the current read/cache
segment. For performance in multi-tasking environments where overlapped seeks
are utilized, the Seek command references the cache hit score and defers the seek
until a cache run has completed.
Register

Binary Opcode

7
Command
SDH
Write Precomp
Sector Count
Sector Number
Cylinder Low
Cylinder High

6
1

5
1

1
X
X
Drive and Head
Don't Care
Don't Care
Don't Care
Starting Cylinder LSB
Starting Cylinder MSB

1
X

0
X

X=Don't Care

Western Digital Corporation

Host Interface and AT Command Set

5.3.3

Read Sector (20H)
For a Read Sector command, the task file's registers determine the number and
location of the sectors transferred to the host. The host can request a maximum of
256 sectors, but only single-sector reads are allowed in long mode. A sector count
of zero specifies 256 sectors. If the drive is not positioned at the specified cylinder,
an implied seek occurs. If the long mode bit is set, four ECC bytes are transferred
along with the data. Single burst data errors of up to 11 bits are corrected if retries
are enabled and the 10ng mode is not selected: An interrupt occurs'beforelhe data
read from each sector is transferred to the host.
With CacheFlow, the requested sector address and sector count parameters are
monitored to perform segment partitioning and sequential/repetitive switching. If
partitioning changes are not required, the currently active segment is checked for
data. If the physical cylinder is valid, but 00 data is present, a read disk operation
begins. If the physical cylinder is invalid, other active cache segments are checked
for data before the seeking operation begins. If the read disk operation must proceed
to the next cylinder, other active cache segments are once again checked for data
before the seek. Switching cylinders always opens a new cache segment for the
new read disk operation.
Register

Binary Opcode
7

Command
SDH
Write Precomp
Sector Count
Sector Number

6
0

Sector Size, Drive and Head
Don't Care
1 - 256 Sectors to be Read

Starting Sector Number

Cylinder Low

Starting Cylinder LSB

Cylinder High

Starting Cylinder MSB

L= Long Mode Bit

Western Digital Corporation

R= Retry Bit

Caviar ACl40IAC280 Technical Reference Manual
5.3.4

Write Sector (30B)
For a Write Sector command, the host transfers a number of sectors (1-256) to the
drive, starting at the logical address specified by the task file registers. Only
single-sector writes are allowed in long mode. An implied seek occurs if the drive
is not positioned at the specified address. If the long mode bit is set, then the host
will transfer four ECC bytes along with the data.

An interrupt is generated as the data for each sector is required, except the first.
The first data buffer contents are sent after the host has issued the command and
the data request status bit is ·on.·
ORO must be received before the host write buffers begin transferring to the base
segment. The base segment is reserved for write operations. Other caching
segments remain valid. Caching segments that contain sectors that were referenced
by the disk write operation become invalid before the write is completed.
Register

Binary Opcode
7

Command
SOH
Write Precomp
Sector Count
Sector Number

4
1

2
3
0
0
Sector Size, Drive and Head

5
1

Don't Care
1 - 256 Sectors to be Written
Starting Sector Number

Cylinder Low

Starting Cylinder LSB

Cylinder High

Starting Cylinder MSB

L= Long Mode Bit

6
0

R= Retry Bit

Western Digital Corporation

Host Interface and AT Command Set
5.3.5

Format Track (SOH)
The track specified by the task file is formatted with 10 and data fields in accordance
with the interleave table transferred to the sector buffer. The buffer contains SPT
entries, 1through SPT for the track's 10 fields. These SPT values are totally dependent
upon the translation mode selected. The buffer must contain descriptors for the
current translation SPT value. If these entries are not present. then no operation is
executed on that sector. The data fields are initialized to zeroes. The interleave table
identifies any bad sectors on a given track and must contain 512 bytes of data. This
table is composed of two bytes per sector as follows:
•
•

The first byte is set to ·OOH" to indicate a good sector or to "SOH" to indicate
a bad sector.
The second byte designates the logical sector 10 number (1-SPT).

Unused bytes may be uninitialized. The Sectors-per-Track (SPT) and Sector-Size
values are specified in the Sector Count and SOH Registers, respectively. Only 512
bytes per sector are allowed. The Sectors-per-Track value in the Sector Count
Register must correspond with the value indicated by the Set Drive Parameters
command. An interrupt is generated upon completion of the command.
Binary Opcode

7
Command
SOH
Write Precomp
Sector Count
Sector Number

6
1

Sector Size, Drive and Head
Don't Care
Sectors per Track
Don't Care

Cylinder low

Cylinder Address lSB

Cylinder High

Cylinder Address MSB

Western Digital Corporation

0
0

Caviar AC140lAC280 Technical Reference Manual
5.3.6

Read Verify (40H)
The Read Verify command is the same as aRead command except that the requested
sectors are not transferred to the host.
With CacheFlow, the requested sector address and sector count parameters are
monitored to perform segment partitioning and sequential/repetitive switching. If
partitioning changes are not required, the currently active segment is checked for
data. If the physical cylinder is valid, but no. data is present, a read disk operation
begins. If the physical cylinder is invalid, other active cache segments are checked
for data before the seeking operation begins. If the read disk operation must proceed
to the next cylinder, other active cache segments are once again checked for data
before the seek. Switching cylinders always opens a new cache segment for the
new read disk operation.

Binary Opcode
7

Sector Size, Drive and Head
Don't Care

Sector Count

1- 256 Sectors to Verify

Sector Number

Starting Sector Number

Cylinder Low

Starting Cylinder LSB

Cylinder High

Starting Cylinder MSB

R=Retry Bit

Western Digital Corporation

Host Interface and AT Command Set

5.3.7

Execute Diagnostics (908)
The Execute Diagnostics command causes the Caviar to execute its self-test
routines and to report a result code in the Error Register as follows:
01 No Error
'
02 Not Applicable
03 Buffer RAM error
04 WD42C22 register error
. 05 :Microprocessor Interna1 RAM error orROM checksum error
ax Slave drive failed
The following tests are performed:
• ROM checksum test
• RAM test. Tests 2 Kbytes of the microprocessor and the 8-Kbyte (32-Kbyte optional) buffer RAM. An incrementing pattern is written to both internal and
external RAM and then read back.
• A register test of the WD42C22.
If the Caviar is configured as a master drive, it monitors the PDIAG (passed
diagnostics) line. A slave drive pulls this line active low once it has successfully
performed its diagnostics. If the Execute Diagnostics command is issued with the
slave drive selected, both drives execute the command just as if the command had
been issued to the master drive. The master drive's task file drives the bus, and it
waits up to five seconds for the slave drive to assert PDIAG. The D bit is always
returned as zero to the host following the Execute Diagnostics command.

Command
SDH

Binary Opcode

Drive

Write Precomp

Don't Care

Sector Count

Don't Care

Sector Number

Don't Care

Cylinder Low

Don't Care

Cylinder High

Don't Care

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

5.3.8

Set Drive Parameters (91B)
The Set Drive Parameters command configures the Caviar for a specific number of
sectors per track (SPT) and heads. The values in the Sector Count register and the
SOH Register determine SPT and heads, respectively. Regardless of the values for
SPT and heads, the Caviar will always be in translation mode. A value of 17 for SPT
and a value of 10 heads for the Caviar AC280 and 5 heads for the Caviar AC140 are
recommended. These configurations yield 980 host-addressable cylinders.
Register

Binary Opcode
7

Command
SOH
Write Precomp
Sector Count

6
0

0
1

Drive and Heads
Don't Care
Sectors per Track

Sector Number

Don't Care

Cylinder low

Don't Care

Cylinder High

Don't Care

Western Digital Corporation

Host Interface and AT Command Set

5.3.9

Read Multiple (C4H)
The Read Multiple command operates similarly to the Read Sectors command except
for the following conditions:
•
•
•

Data transfers occur in multiple sector blocks.
Long bit is invalid.
Retries are always performed.

Interrupts and DRDs occur once per block of multiple sectors. The number of sectors
per block is set using the Set Multiple command. When the Read Multiple command
is issued, the Sector Count value sets the total number of sectors to be transferred
(not blocks or block count). Sector count need not be a multiple of the block. Partial
block transfers are completed when the remaining sectors are ready for transfer. The
Caviar must be in multiple mode for this command to operate correctly. Otherwise,
the command aborts.
Binary Opcode

4
2
3
5
1
0
0
0
Sector Size, Drive and Head

0
0

Don't Care
1 - 256 Sectors to be Read
Starting Sector Number

Cylinder Low

Starting Cylinder LSB

Cylinder High

Starting Cylinder MSB

Long Mode Bit invalid for this command. Retries always allowed

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual

5.3.10

Write Multiple (C5H)
The Write Multiple command operates similarly to the Write Sectors command
except for the following conditions:
•
•
•

Data transfers occur in multiple sector blocks.
long bit is invalid.
Retries are always performed.

Interrupts and DROs occur once per block of multiple sectors. The Number of
Sectors-per-Block value is set using the Set Multiple command. When the Write
Multiple command is issued, the Sector Count value sets the total number of sectors
to be transferred (not blocks or block count). Sector count need not be a multiple of
the block. Partial block transfers are completed when the rema ining sectors are ready
for transfer. The Caviar must be in multiple mode for this command to operate
correctly. Otherwise, the command aborts.
ORO must be received before the host write buffers begin transferring to the base
segment. The base segment is reserved for write operations. Other caching
segments remain valid. Caching segments that contain sectors that were referenced
by the disk write operation become inva lid before the write is completed.
Register

Command
SOH
Write Precomp
Sector Count
Sector Number

Binary Opcode

5
0

1
0

0
1

Sector Size, Drive and Head
Don't Care
1 - 256 Sectors to be Written
Starting Sector Number

Cylinder low

Starting Cylinder lSB

Cylinder High

Starting Cylinder MSB

long Mode Bit invalid for this command. Retries always allowed

Western Digital Corporation

Host Interface and AT Command Set

I
I,;.
'1

5.3.11

Set Multiple (C6H)
The Set Multiple command sets the number of sectors per block to be transferred
between the host and the Caviar for the Read and Write Multiple commands. The
Number of Sectors-per-Block value is loaded into the Sector Count register. The
maximum number of sectors per block is eight. A value beyond the limit causes
command termination. A value of one is considered valid. A value of zero disables
multiple mode.
Register

Binary Opcode

3
0

0
0

Command

SDH

Write Precomp
Sector Cou nt

Don't Care
Number of SectorS/Block

Sector Number

Don't Care

Cylinder Low

Don't Care

Cylinder High

Don't Care

D= Drive Designation Bit

Western Digital Corporation

X = Don't Care

Caviar AC140lAC280 Technical Reference Manual

5.3.12

Read Buffer (E4H)
The Read Buffer command allows the host to read "Buffer 0" of the Caviar 32-Kbyte
RAM cache, i.e., the 512 bytes of the first sector buffer in the base cache segment.

Binary Opcode
7

Command

SOH

0
0

Write Precomp

Don't Care

Sector Count

Don't Care

Sector Number

Don't Care

Cylinder low

Don't Care

Cylinder High

Don't Care

o=Drive Designation Bit

X =Don't Care

Western Digital Corporation

Host Interface and AT Command Set

5.3.13

Write Buffer (E8B)
The Write Buffer command functions identically to the Read Buffer command except
that 512 bytes of data are transferred from the host to the Caviar RAM cache.
Note: The Read and Write Buffer commands only affect the first 512
bytes of the Caviar RAM cache.
Register

Binary Opcode

2
0

0
0

Command

SDH

Write Precomp

Don't Care

Sector Count

Don't Care

Sector Number

Don't Care

Cylinder Low

Don't Care

Cylinder High

Don't Care

D =Drive Designation Bit

X=Don't Care

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

5.3.14

Identify Drive (ECH)
The Identify Drive command transfers 512 bytes of data that specify the drive's
parameters. The host is required to read the parameters out of the sector buffer
when the Caviar sets DRO and IRO. Table 5-7 lists the parameters read by the host.
Binary Opcode

Command

0
0

SDH

Write Precomp

Don't Care

Sector Count

Don't Care

Sector Number

Don't Care

Cylinder low

Don't Care

Cylinder High

Don't Care

D =Drive Designation Bit

X=Don't Care

Western Digital Corporation

Host Interface and AT Command Set

Word

Description·

General configuration (427A hex)

Number of fixed cylinders (980)

Number of removable cylinders (0)

Number of heads (10) (5)

Unformatted bytes per track (9656)

Unformatted bytes per sector (568)

Physical sectors per track (17)

Minimum size of ISG in bytes (7)

Reserved

Minimum PlO bytes (14)

10 -19

Serial number (ASCII characters, WOnnnnnn)

Controller type (3)

Controller buffer size in 512-byte increments (62)

Number of ECC bytes transferred on long operations (4)

23-26

Firmware Rev. (ASCII characters, X.XX)

27 -46

Controller model number (ASCII characters, WOAC280 or
WOAC140)

Number of sectors/interrupt on read/write multiples (B008 hex)

Double word I/O (0)

Relocation capabilities (0)

50-255

Reserved

* Note: The data structure for the identify drive command contains 512
bytes of information

Table 5-7. Identify Drive Command

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

5.3.15

Set Buffer Mode (EFH)
The Set Buffer Mode command enables or disables CacheFlow. If the
Precompensation Register is set to MH, then CacheFlow is enabled. If the
Precompensation Register is set to 55H, then CacheFlow is disabled. To modify the
defau It number of cache segments, the Precompensation Reg ister is set to A1H-A5H
to enable caching with one to five segments as speCified in the following table.
Register

Command
SDH

Binary Opcode

7
1
X

Write Precomp

MH or 55H, A1 H-A5H

Sector Count

Don't Care

Sector Number

Don't Care

Cylinder Low

Don't Care

Cylinder High

Don't Care

D=Drive Designation Bit

MH enables look-ahead read.

X=Don't Care

55H disables look-ahead read.
A1Henables caching with 1 segment.
A2H enables caching with 2 segments.
A3H enables caching with 3 segments.
A4H enables caching with 4 segments.
A5H enables caching with 5 segments.

Western Digital Corporation

Host Interface and AT Command Set

5.4

Host Interface Read Timing
ADDRESS VALID TIME (HAO·2)

--I~-,

! tASU1,

i' '\.

,
,
,:

tCS01:'

tMRIRA

tAH1 ,:

I •

• '.

•

tRCY

HOST DATA 0.15

"'--j

---iL
.

tRO-+R

.:,
:

:+-----+'
,

tDV1 ,

:.
:
. '
: tOH1
:.;.--

:HOST DATA BUS VALID (HDO·HD15)

...................................--~r--.
tAlCSI
tCieSI

tClCSV

., .,

---

,,, tAlCSV
,

(Data Port Only) IOCS16 :

I---

:r-

SYMBOL

DESCRIPTION

MIN

tABUI

Address setup time
Chip select setup time
110 read active· Port 0
I/O read active • olher ports
Chip seIectIAddress hold time
Data valid time • Port 0
Data valid time • other ports
Data hold time

30
22
75
100
10

tCS01
!MRIRA
tAH1
tOV1
tDH1
tRDR
tClCSV
tAlCSV
tClCSI
tAlCSI
tRCY

~sread
reco~ time
valid from em>
~ valid from HAO
~ inactive form ~
~ inactive form HAO
Read cycle time· Port 0
Read cycle time • olher ports

5
20

MAX

60
100
50
42
40

47
45

444
150

Note: All unI1s of me8SI.II8rI18I1 are In nanoaec:onds, unless olhelWlse noted.
All values based on a maxlmum load capacitance 01 50 pl.

Figure 5-2. Host Interface Read Timing
Western Digital Corporation

Caviar AC140lAC280 Technical Reference ·Manual

5.5

Host Interlace Write Timing

--1_1--ADDRESS VALID TIME (HA0-2)

tASUI,

,I ':,l

~:.

: tCS02:
:I tASU2:I

I.
i

tlWA

••

i5W!

l
I"

,
,:

tDV2

•

HOST DATA 0-15

•1+--------+:
:l tWER i .:
i
: ",
I

tWCY

tAH2 :
fCHW:I

,
:,

: tDH4 :
I

I !1

:HOST DATA BUS VALID (HDO-HD15)

--------------~~----,
,

tClCSV
,, tAlCSV
,

(Data Port Only) Il%m

SYMBOL
tASU2
tCS02
tlWA
tAH2
tOV2
tDH4
tCHW
tCICSV
tAlCSV
tCICSI
tAlCSI
tWCY

: tAlCSI

,,: tClCSI
,,
~

:r-

I
DESCRIPTION
Address setup time
Chip select setup time
I/O read actM! - Port 0
110 read active - other ports
Address hold time
Data setup - Port 0
Data setup - other ports
Data hold time
select hold time
16 valid from ~
~ valid from HAO
~ inactive form ~
~ inactive form HAO
Write cycle time - Port 0
Write cycle time - other ports
Write recovery time

I8'ls

MIN

MAX

30
22
75
100
20
50
50
15
10
42

40
47
45

444
150
tWER
20
No..: Nt units 01 ~rement are In 11IIIlCIII8COI'ds, unIe8s otherwise nollld.
All V1IIu8s balled on a maximum load capacitance of 50 pf.

Figure 5-3. Host Interface Write Timing

Western Digital Corporation

Host Interface and AT Command Set

5.6

Error Reporting
Table 5-8 lists all the valid error conditions which can occur for a given command.
The Caviar drive checks the Command Register at the start of a command to
determine if any condition exists which could result in a terminated command. The
command is then attempted. Any subsequent error terminates the command at the
point where it is encountered.
EmIr ........
ClllDlllaRd

BBD

UNC

IDNF

DRDY

Recal ibrate·
V
V
V
V
Seek
Read-V
V
V
V
V
Read Long-V
V
V
V
V
V
V
Write
V
V
V
Write Long
V
V
V
V
Format Track
V
ReadVerifv
V
V
V
Execute Diag.
Set Drive
Parameters
V
Read MultiDle
V
V
V
V
Write MultiDle
V
V
V
V
Set MultiDle
V
Read Buffer
Write Buffer
Identify Drive
V
Set Buffer Mode
V
Invalid
V
Command
BBD
Bad Block Detected
DWF
UNC
Uncorrectable Data &!Or DSC
IDNF
10 Not Found
CORR
AC
Abort Command &!Or
ERR
DRDY
Drive Not Readv &mr
V
- Also sets TKO in &mr Register if track zero not found .
• - Also sets DAMNF in Error Reaister if data address men: not found.

DWF

DSC

V
V
V

V
V
V
V
V
V
V

CORR

V
V

ERR
V
V
V
V
V
V
V
V
V

V
V
V

Drive Write Fault Detected
Drive Seek Complete &mr
Data was Corrected
Error Bit is Status Register
Valid &!Orfor Command

Table 5-8. Error Reporting

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

Western Digital Corporation

Installation and Set-Up Procedures

6.0

INSTALLATION AND SETUP PROCEDURES

6.1
6.1.1

Unpacking
Handling Precautions
-Western ·I)jgital··products are· designed-~to withstand normal handling when
unpacking and installing the drive. Care must be taken to avoid excessive
mechanical shock or electrostatic discharge that can permanently damage the Caviar
and void the warranty. When the Caviar is not in its shipping container or installed
in its proper host enclosure, it must be placed on an antistatic surface. To prevent
damage, do not unpack your Caviar until you are ready to install it.

Inspection

0/ Shipping Container

Carefully examine the container for obvious shipping damage, e.g., holes, signs of
crushing, or stains. Notify the carrier and your Western Digital representative if you
observe any shipment damage. Always move the shipping container in the upright
position indicated by the arrows on the container.

6.1.2

Removal From Shipping Container
Remove the Caviar from the shipping container only for inspection or installation.
Carefully open the box. The Caviar is always shipped in a foam-insert package.
When removing the Caviar from the foam insert, grasp the drive at the sides, behind
the bezel (if the Caviar has been shipped with a bezel). Gently place the Caviar in
its antistatic bag on a clean, level, grounded work station. Do not stack drives or
stand the Caviar on edge.

CAUTION:

Never drop the Caviar from any height when removing it
from the shipping conlBiner. Dropping the Caviar can
severely damage the head disk assembly or printed circuitboard.

Handle the Caviar only by holding the metal cover of the head disk assembly. Do
nottouch circuit board components. Do not attempt to open its sealed compartment.
Failure to observe these restrictions will void the warranty.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual
6.1.3

Removal From Antistatic Bag
Before removing the Caviar from its antistatic bag:
•
•
•

Make sure that your work station is properly grounded.
Wear a properly grounded wrist strap with good skin contact.
Avoid contact with any component on the printed circuit board.

After attaching your wrist strap. gently remove the Caviar from the antistatic bag.
Handle the Caviar only by the base casting areas. Never lift the Caviar by the printed
circuit board or the bezel. Handle the Caviar with the printed circuit board facing
downward during installation.

6.1.4

Moving Precautions
If it becomes necessalY to move your computer system. turn off the power to
automatically park the heads. Parking moves the heads to a safe. non-data landing
zone where they are locked into place. This helps protect the media and the heads
from accidental damage due to vibration. moving. or shipping.

6.2
6.2.1

Mounting Restrictioll8
Orientation
The Caviar can be mounted in many different ways depending upon the physical
design of your system. Figure 2-1 shows the Caviar AC140/AC280 mounting
dimensions and location of the screw holes.

6.2.2

Screw Size Limitations
The Caviar is mounted to the chassis using four 6-32 screws.
CAUTION:

Screws which are too lon, will dama,e board components. The screw must en,a,e no mote than six
threads (3/16 inch).

Western Digital Corporation

Installation and Set-Up Procedures

6.3
6.3.1

Installation ComJglll"ation
Determining Your Connguration
You can configure the Caviar in one of two ways:
• The drive is cabled directly to a 4O-pin connector on the motherboard.
.....• •The drive is cabled to em adapter card mounted in one ofthe-expansion slots
in the computer.
Both configurations use a 4O-pin host interface cable.

If you are using the Caviar drive as one of two hard disk drives in the computer (dual
installation). you may use either configuration. In dual installations. you must use
a 4O-pin host interface cable with three connectors. and daisy-chain the two drives
to the motherboard or adapter card. Western Digital provides three adapter cards
for use with the Caviar drive:
•
•
•

6.3.2

The WDAT-140 supports two intelligent drives.
The WDAT-240 supports two intelligent drives and two floppy drives.
The WDAT-440 supports two intelligent drives. two floppy drives. two serial
ports. and one parallel port.

Dual Installations
Dual installations require a master/slave drive configuration. where one drive is
designated as the primary (master) drive and the other is designated as the
secondary (slave) drive. The Caviar drive is compatible in dual installations with
other intelligent drives that support a master/slave configuration. The Caviar drive
is not compatible with ST-506 drives.
You can install the Caviar drive with a Conner CP342 or CP3022 drive if the Conner
is configured as the master drive. This configuration is supported for all
PC/AT-compatible computers except the original IBM PC/AT.

If your installation requires the use of an adapter card. it is useful to know that you
may also be able to connect your floppy drive(s) to the adapter card. If you use the
WDAT-240 adapter card. you may connect two floppy drives to the adapter card.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

6.3.3

Jumper Settings
The Caviar drive has a jumper block (J8) located next to the 40-pin connector on the
drive. If you are installing the Caviar drive as the only intelligent drive in the system,
you do not need to install jumpers on the J8 connector. This is considered astandard
single drive installation, and no jumpers are required.

Note: Even with no jumper installed, the Caviar checks the DRIVE AC. -"-nVE/SLAVFPRESENr(DASP) signal to determine if a slave intelligent drive is present.
If you have a dual installation (two intelligent drives), you must designate one of the
drives as the master and the other as the slave drive. The jumper pins on the J8
connector need to be configured for the dual installation. Refer to Figure 6-1 for an
illustration of all jumper settings.
To designate the intelligent drive as the master, place a jumper shunt on pins 5-6.
With the Caviar configured as the master drive, the Caviar assumes that a slave drive
is present. The jumper on pins 5-6 is optional if the slave drive follows the same
protocol (Common Access Method AT Bus Attachment) as the Caviar.
To designate the intelligent drive as the slave, place a jumper shunt on pins 3-4.
When the Caviar is configured as the slave drive, the Caviar delays spin up for four
seconds after power-up reset. This feature prevents overloading of the power supply
during power-up.

If your system is a PC/AT compatible computer not manufactured by IBM, and it
contains a Conner CP342 or CP3022 drive, you can install the Caviar drive as a second
drive. In this configuration, the Conner drive must be configured as the master, and
the Caviar as the slave. To designate the Caviar drive as the slave to the Conner
drive, place the jumper shunts on pins 1-2 and 3-4.

Western Digital Corporation

Installation and Set-Up Procedures

Single (Standard Installation)
"'----:-~

5 3 1

S:: III:: I Dual (Master)
6 4 2

Dual (Slave)
"'----:oI-:L::-I
Dual (Slave)
"'--~~ with Conner CP342 or CP3022

Key:

Jumper added

: Jumper pins

Figure 6-1. Jumper Settings

6.4
6.4.1

Installing the Caviar Drive
Mounting the Drive
For dual installations, it is usually easier to completely install one intelligent drive
in the lower position first. The order of intelligent drives is unimportant if you are
using two Western Digital drives. As explained previously, one must be jumpered
as the master drive and the other as the slave drive. When the installation is
complete, the drives are daisy-chained together.

6.4.2

Cabling and Instal1ation Steps
Make sure your interface cable is no longer than 18 inches to minimize the noise
which is induced on the data and control buses. Also, if you are connecting two
drives together, you need a daisy-chain cable that has three 4O-pin connectors.
CAUTION:

Western Digital Corporation

You may damage the Caviar drive if the inledace cable is
not connected properly. To prevent inco"sct connection, use a cable that has keyed connectors at both the
drive and host ends. Refer to Rgure 6-2 which shows
pin 20 as the key. (This pin has been removed from the
J2 connector. The female connector on the intedace
cable will have a plug in position 20 to prevent incorrect connection.)

Caviar AC140lAC280 Technical Reference Manual

J2
39

J8
1531

J3
4321

L•••••••••• c ••••••••• c

"re •• ~I
••• 111-II

642

, •••••••••••••••••••• C •••

r..-n

C Empty boxa8
IWIIcwaI pins•
.J2 pin 20 karad
Raw 01 pins I'8IIICMd 10 II8JI8IIII8 J2 fnIm J8

L~:

' - - - - - +5V

Figure 6-2. Standard Factory Connectors

Connect the 4O-pin interface cable to the 4O-pin J2 connector on the Cavia r
hard drive as shown in Figure 6-3. For dual installations, daisy-chain the two
drives together by connecting them with a three-connector interface cable.

Route the cable toward the motherboard or card slot area. The cable should
easily route from the hard drive to the card slot area. The cable should not
block any air flow paths.

Insert the drive halfway into the drive bay.

Western Digital Corporation

InstaUation and Set-Up Procedures

Jumper

Power connector
Marked wire

Figure 6-3. Caviar Connector Locations
4.

Connect the power supply cable to the J3 connector (4-pin power connector
shown in Figure 6-2) on the Caviar drive. Dual drive installations: If you do
not have two internal power connectors. you will require a V-adapter to
provide power to both units as shown in Figure 6-4.

Attach the other end ofthe power cable to the power supply in your computer.

Completely insert the drive into your system drive bay.

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference "Manual

To MoIhaIboanI
01' Adapter IIoanI

Figure 6-4. Y-Adapter Cabling
7.

Mount the Caviar drive to the drive bay using four 6-32 screws. Be sure to use
the correct size screws. Do not install the screws past six threads (3/16
inch). Screws that are too long will damage the Caviar drive.

CAUTION:

Connect the interface cable from the intelligent drive to the host as follows:

•

If you have a 4O-pin connector on the motherboard. connect the other end of
the interface cable to the motherboard connector.
If your installation requires an adapter card. as explained previously. install
the adapter card as described in section 6.5.
If you do not need to install the adapter card. close the computer case according to the instructions provided in your system manual and proceed to section6.6.

•
•

Screws which Bre too long will dBmBge bosrd components. 1IIe screw must engBge no more thBn six
threBds (3/16 inch).

Western Digital Corporation

InstaUation and Set-Up Procedures

6.S

Installing the Adapter Card
If you are installing the Western Digital adapter card, configuration will probably be
unnecessary. You only need to change the default jumper settings if you want to
disable the floppy drive controller or set an alternate address at 370-377.
If you need to change the adapter card configuration, do so before attaching any
-cables or installing the card into the s10t.

NOTE.·Remove or disable any existing floppy or serial/parallel controllers which are being replaced by the adapter card controllers.

For more information on Western Digital adapter cards, contact the Western Digital
Literature Distribution Department and request a copy of the AT Host Adapters
Installation Guide (Part NumberWDATHAIG).

6.6
6.6.1

SetopProcedures
Preparing the Caviar Drive for Use
The Caviar is preformatted (low level) at the factory and comes equipped with afull
complement of defect management characteristics. No modifications are required
before installation. If at some later time you need to perform defect management,
contact Western Digital Technical Support for information on the WDATJOE utility
as described in section 8.
Your computer operating system provides an initial setup utility which is either
ROM-based or on floppy diskettes. The system setup procedures vary from system
to system, but each setup procedure allows you to tell the system what type of
hardware you are using. Follow the setup instructions in your operating system
manual (MS-DOS or other operating system).

Western Digital Corporation

Caviar AC140lAC280 Technical Re[erence Manual

6.6.2

Selecting Drive Tables
One step in your computer system setup utility procedure asks you to specify the
type of drive used in your system. Use the following procedure to specify your drive
type:
•

If you are installing the 40 MByte drive in your system, select "drive type 17"
from the drive tables displayed during the setup utility procedure. Type 17
typically defines a drive with 977 cylinders, 5 heads, and 17 sectors per track.

•

There are no specific standards for the 80 MByte drive. However, the Caviar
uses a translation scheme that provides complete compatibility with any
drive setup parameters you select. Refer to Table 6-1 for a list of recommended drive parameters. Choose the 80 MByte drive table from the drive
tables displayed during the setup utility procedure. Make sure that the total
drive capacity (number of cylinders multiplied by the numbers of heads multiplied by the number of sectors/track) does not exceed the total number of
sectors available on the drive. i.e., 166,628 for the Caviar AC280 and 83,314
for the Caviar AC14O. Refer to section 2 for information on the Caviar drive's
physical specifications.

Caviar AC140
Cylinders

Heads

980
977

Sectors/Track
17

SectorS/Drivers

83,045

700

5
7

83,300

640

83,200

Cylinders

Heads

Sectors/Track

SectorS/Drivers

980

166,600

640
841

166,400

166,518

980

166,600

83,300

Caviar AC280

Table 6-1. Drive Table Parameters
78

Western Digital Corporation

Installation and Set-Up Procedures

6.6.3

Partitioning the Drive For Use Under DOS
You need to partition your drive(s) to meet certain DOS version requirements.
Partitioning divides your disk into one or more partitions that function as separate
disk drives. Use the DOS "FDISK" command to display a series of menus that help
you partition the hard disk for MS-DOS.
Your version of DOS determines how you can partition your disk(s):
•

If you have a DOS version earlier than 3.3, you can only address 32 MBytes
maximum on your drive. You cannot partition the drive(s) without secondparty software. We recommend that you upgrade to DOS 3.3 or above.

•

If you have DOS version 3.3 or above (less than version 4.0), DOS allows you
to partition larger drives into logical disk drives with a maximum of 32 MBytes per partition.

•

If you are working with DOS version 4.0 or higher, you can partition the disk
drive(s) into one or more logical drives. You are not limited to 32 MBytes per
partition.

"FDISK" automatically assigns drive IDs to the partitions. Refer to your system
manual for more information on partitioning drives.

6.6.4

High-level DOS Formatting
High-level format the first logical drive (the "C:" drive) by entering "FORMAT C:/S" at
the "A:" prompt.
If you designated other drives or partitions during the "FDISK" routine, you need to
format those drives as well.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual
6.6.5

Preparing the Caviar Drive For a Novell Network
If you are installing Novell, you must "COMPSURF" the Caviar drive using the
following parameters:
Format the disk?

Maintain the current media defect list?

Enter media defects?

Number of sequential passes

Default

Number of I/O random test

Default

Are parameters correct?

Yes

After running "COMPSURF" on the Caviar drive, enter "NETGEN: Refer to your
Novell installation manual for more information on "COMPSURF" and "NETGEN."

6.6.6

Booting the System
After you have formatted your drive(s) and installed the operating system on your
intelligent drive, re-boot your system.

If your system will not boot or if you are unable to make the new drive the current
drive, refer to your operating system documentation to be sure that you ran the
system utility correctly, specified the drive tables, and that you partitioned and
formatted your hard disk(s) correctly. If your system still won't boot, you may have
improperly installed or connected your hard drive. Re-read the installation
instructions provided in this manual to be sure that you installed and connected
everything properly.

Western Digital Corporation

Maintenance

7.0

MAINTENANCE
The Caviar requires no preventive maintenance and contains no user-serviceable
parts. The service and repair of the Caviar can only be performed ata Western Digital
Service Center. Please Contact your Western Digital representative for warranty
information and service/return procedures.
-Observe the following precautions to prolong the life of the drive:
•
•
•
•
•
•
•

•

Do not attempt to open the sealed compartment of the Caviar as this will
void the warranty.
Do not lift the Caviar by the bezel or the printed circuit board.
Avoid static discharge when handling the Caviar.
Avoid harsh shocks or vibrations.
Do not touch the components on the printed circuit board.
Observe the environmental limits specified for this product.
If it becomes necessary to move your computer system, tum off the power to
automatically park the heads. Parking the heads moves the heads to a safe,
non-data landing zone and locks the heads into place. This helps protect the
media and the heads from accidental damage due to vibration, moving or
shipping.
To protect your data, back it up regularly. Western Digital assumes no
responsibility for loss of data. For information about back-up and restore procedures, consult your DOS manual. There are also a number of utility
programs available that you can use to back up your data.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

Western Digital Corporation

Western Digital Drive Utility

8.0

WESTERN DIGITAL DRIVE UTILITY
All Caviar intelligent drives are defect-free and pre-formatted (low level) at the
factory. After prolonged use, any drive, including Caviar, may develop additional
defects. If you continue receiving read (or write) data errors in any given file at the
DOS level, then you can use the defect management utility WDAT_IDE. The
WDATJDE utility program developed for the Caviar recovers, relocates, and rewrites
user data to the nearest spare sector and maintains a secondary defect list.
WDATJDE does not format the entire drive; WDAT_IDE only re-formats the
defective sector or track. The Caviar has two spare sectors per cylinder. An entire
track is not relocated unless the track contains three bad sectors or multiple
non-recoverable errors.

Technical Support Bulletin Board
You may download Western Digital's diagnostic utility, WDAT_IDE from the
Technical Support Bulletin Board if you have a modem.
To access the bulletin board you require:
•
•
•

A Hayes-compatible modem
1200 or 2400 Baud rate
Format: 8 data bits, 1 stop bit, no parity

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual
The Bulletin Board numbers are (714) 753-1234 with a Hayes-compatible modem of
1200 or 2400 baud rate or (714) 753-1068 with a Hayes-compatible modem of 9600
baud rate. The Bulletin Board will ask you some preliminary questions about your
modem set-up and the type of system you are calling from before sending you the
main menu. Refer to your modem manual for instructions on proper modem setup.
To gain access to the main menu, follow these general steps:
•
•
•
•
•

Select for software
Select "Storage"
Select "Utilities"
Specify WDAT_IDE for the Caviar
To receive the software program, select and then the transfer protocol.
Respond to the prompts for transfer protocol. file name, etc.

On screen Help (H) is available if you have any problems. If you need additional
assistance, contact Technical Support at (714) 932-4900.

Western Digital Corporation

Troubleshooting

9.0

TROUBLESHOOTING
The following tips and procedures may help you determine the cause of a problem.
•

If you have a problem with your Caviar, first re-read the installation instructions to be sure that you followed them correctly. It is important to enter in·formation exactly as instructed.

•

Verify that you have correctly followed the setup procedures for your system.

•

Verify that you have properly formatted and partitioned the Caviar with DOS
FDISK and FORMAT (or an equivalent utility).

•

Check your physical installation:
- Jumper selections on the Caviar
- Correct cabling
- Adapter card - properly seated and configured
- System power supply
- Controller conflicts

•

Observe the environmental limits specified for this product.

If you are unable to resolve your problem, contact your Western Digital
representative. If you are unable to contact your Western Digital representative,
please contact Western Digital Technical Support at (714) 932-4900.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual

Western Digital Corporation

Glossary

10.0

GLOSSARY
AT Bus Attachment (ATA) =The interface defined by International Business
Machines for the original AT disk controller. Western Digital designed the Caviar
drives to be fully ATA compatible.
Auto Park = Turning off the intelligent drive's power causes the Caviar
AC140/AC280 to move the read/write heads to a safe non-data landing zone and
locks them in place.
Average Access Time =The average access time indicates how long it takes the
drive to find a block of data on the disk. Average access time is determined by
dividing the total time required to seek between all ordered address pairs by the
total number of these ordered pairs.
Block =Agroup of bytes handled, stored and accessed as a logical data unit, such
as an individual file record.
Buffer =A temporary data storage area that compensates for a difference in data
transfer rates and/or data processing rates between sender and receiver.
Class 100 =Aclean room standard specified by a U.S. Federal standard. Essentially,
the standard limits the number of particles per cubic foot to no more than 100
particles. No particle can exceed 0.5 micron.
Correctable error = An error that can be overcome by the use of Error Detection
and Correction schemes.
Data separator =The data separator (WD10C23) removes phase, frequency and
write splice noise from the read data and presents clean digital read signals to the
controller. It also conditions write data to be recorded on the drive. Data to be written
is precisely clocked from the controller to the WD1 OC23.
Data Synchronizer =An electronic circuit that produces a clock signal that is
synchronous with the incoming data stream. The clock signal is then used to decode
the data using the appropriate recording code.

Western Digital Corporation

Caviar AC140lAC280 Technical Reference Manual
Data Transfer Rate =The rate that digital data is transferred from one point to
another, expresses in bits per second or bytes per second.
•
•

"Data Transfer Rate to Disk" is the internal disk transfer rate in Mbits per
second.
"Data Transfer Rate from the Buffer to the Host" is based on the susta ined
transfer of buffered data in Mbvtes per second.

Dedicated Landing Zone =Adesignated radial zone on the disk chosen to avoid
contact with the data cylinders, where contact starting and stopping occur by design.
Defect Free. Aterm used to describe recording surfaces which have no detectable
defects.
Defect Management. A general methodology of eliminating data errors on a
recording surface by mapping out known bad areas of the media. Defective sectors
are retried and data is written in alternate locations.
Error Correction Code =A mathematical algorithm that can detect and correct
errors in a data field by adding check bits to the original data.
Error Rate =The number of errors of a given type that occur when reading a
specified number of bits.
Formatted Capacity =The actual capacity available to store data in amass storage
device. The formatted capacity is the gross capacity minus the capacity taken up by
the overhead data required for formatting the media.
Hard Error = An error that cannot be overcome by repeated readings and
repositioning of the head.
Hard Sectored. Atechnique which uses a digital signal to indicate the beginning
of a sector on a track. In contrast, soft sectoring allows the controller to determine
the beginning of a sector by reading the format information from the disk.
Index Pulse Signal. A digital pulse signal indicating the beginning of a disk
revolution. An embedded servo pattern or other prerecorded information is present
on the disk following Index.
Landing Zone. The heads move to this location on the inner cylinders following a
Park command. User data is not stored at this location.

Western Digital Corporation

Glossary
Latency =The period of time that the read/write heads wait for data to rotate in
an accessible position. For a disk rotating at 3558 RPM. the average latency is 8.45
milliseconds.
Logical Address =A storage location address that mayor may not relate directly
to a physical location. The logical address is usually used when requesting
information from a controller. The controller performs a logical-to-physical address
conversion and retrieves the data from a physical location in the storage device.

MTBF =Mean Time Between Failures
MITR =Mean Time to Repair
Recoverable Error =A read error. transient or otherwise. that can be corrected by
ECC recovery or by rereading the data.
Rotational Latency =The amount of delay in obtaining information from a disk
drive that can be attributed to the rotation of the disk.
Servo Burst = A momentary servo pattern used in embedded servo control
implementations. usually positioned between sectors or at the end of a track.
Soft Error = A data error which can be overcome by rereading the data or
repositioning the head.
Uncorrectable Error =An error that cannot be overcome with Error Detection and
Correction.
Unrecoverable Error =A read error which cannot be overcome by an ECC scheme
or by rereading the data.

Western Digital Corporation

Caviar ACl40IAC280 Technical Reference Manual

Western Digital Corporation

~ WESTERN DIGITAL
WESTERN DIGITAL CORPORATION 8105 IRVINE CENTER DRIVE
IRVINE. CALIFORNIA 92718 TELEPHONE: 714.932.5000
FOR SERVICE AND LITERATURE. CALL: 714.932.4900

COVER PRINTED ON 100% RECYCLED PAPER

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