Westinghouse_P50_computer Westinghouse P50 Computer

Westinghouse_P50_computer Westinghouse_P50_computer

User Manual: Westinghouse_P50_computer

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OPERATION & MAINTENANCE
PROGRAMS
HAGAN/CSD
TRAINING DEPARTMENT

Westinghouse Electric Corporation

TABLE OF CONTENTS
Section

Title

Page

1

Bootstrap S3A. . . . . .

1-1

2

Bootstrapped Binary Loader S4A .

2-1

3

Command Execute Test D9A

3-1

4

Core Crosstalk Test D10A .

4-1

5

Worst Case Core Pattern Test DllA .

5-1

6

Adder Test D12A . . . . . . . . . .

6-1

7

735 Selectric Typewriter Test D13A

7-1

8

Extended Core Memory Test D14A .

8-1

9

ASR Punch Reader Test D15A

9-1

10

High Speed Punch Reader Test D16A .

10-1

11

Mark II Analog Input Statistical Test D17B.

11-1

12

Analog Input Scanner Test D18B . . . . . .

12-1

13

Contact Closure Output vs. Contact Closure
Input Test D19A . . . . . . . . . • . . • . .

. • . . . . . 13-1

14

Contact Closure Output vs. Process Interrupt
Test D20A. . . . . . . . . . . . . .

14-1

15

P50 CCI Test Without Cables 037 A .

15-1

16

Interrupt Test Without Cables D38A

16-1

17

P50 CCO Test Without Cables D39A

17-1

18

P50 Programmer's Console Package.

18-1

BOOTSTRAP (S3A)
1.

Purpose
To load the binary loader Into core.

II.

Description of Operation
A.

Place the tape "BINARY LOADER, BOOTSTRAP FORMAT" under the reader;
turn the reader on.

1.

When using the high speed reader, place the ON/OFF switch in the ON
position.

2.

When using the ASR set, the turn-on procedure is as follows:
a.

Set ASR switch to OFF position.

b.

Put machine In WRITE mode; depress the Master Clear button.

c.

Using the probe, load the S-Register with the location.

d.

Using the probe, load the X-Register with the contents of the location;
depress the Start button.

e.

Repeat c and d until all three words below have been entered:
Location

Contents

000008
001018
001028

001018
377408
340 .... 8

The two asterisks above denote the output channel number of the ASH
set.

f.
B.

Put machine in INSTRUCTION STEP mode; depress the Master Clear
and Start buttons.

Load the bootstrap manually (1); or use the bootstrap card (2).
1.

Manual Load
a.

Put machine in WRITE mode; depress the Master Clear button.

b.

Using the probe, load the S-Register with the location.

c.

Using the probe, load the X-Register with the contents of the location;
depress the Start button.

d.

Repeat b and c untU all the words on the program listing (locations
0-278) have been entered.

1-1

2.

m.

Bootetrap Card lDad

a.

CoMect the bootstrap card to the proper main frame plUI.

b.

Put machine in WRITE mode; depress the Master Clear button.

c.

Using the probe, carefully trace the path on the bootstrap card crossing all exposed conductors in sequence.

d.

Remove the bootstrap card from the main frame p llg.

C.

Verify that location 258 of the bootstrap program contains the proper Input
command to reference the selected reader.

D.

Put machine in RUN mode; depress the Master Clear and Start buttons.

Run Time
In less than one minute, with lockout set. the bootstrap program wtll read in the

binary loader and transfer to its starting location.
IV.

Storage
Number of locations used: 278 (1-278).

1-2

DATE

4/27/65.

PROJECT

~D.

liME

5jOO~J

2/~0/20

PRO~RAM~ER

p.M,

paGE

E,E. D.HAHE

TAPE NUMBER

~12632

1

2
3

PROCHA" LIBRARy
PROCHA" NO.
p·50

4

5
6

S3A

7
10

11
12
13
14
15

16
17

20
21
22
23
l4
25

26

27
30
31
32
33
34
35
36
37

40
41

42
43

••

A. UPERATING INSTRUCTIONS.
1, CDN~ECT THE BOOTSTRAP CARD TO PROPER PLUG ON MAIN 'RAME.
2. VEHIFY THAT THE READER AND LOCATION 25 (OCTAL) or THE
dOOTSTRAP PROGRA~ ~ILL RE~ER TO THE SAME CHANNEL.
3

SEL~CT

~RITE

"DOE AND MASTER CLEAR.

4 USING A GHOUNDED PROBE. CAREFULLY TRACE PATH ON BOOTSTRAP CARD. CHOSSI~G ALL EXPOSED CONDUCTORS IN SEQUENCE.
(TH~ BDU!STMAP ALSO MAY SE LUADED MANUALLY,)
5,

~E"OVE

BOOTSTRAP CARD rROM MAIN rRAME PLUG.

6. PLACE THE TAPE or THE BINARY LOADER, BOOTSTRAP rORMAT,
IN HEAOt R AND Tu~N HEADE~ ON,
!Ir THE ASR READER IS USED.
PLACE 5~!TCH ON LINE.
Ir THE ASR SET IS NOT TURNED ON,
~XECUTE A~ OUTPUT INSTRUCTION TO THE ASR SET w~ILE IN SINGLE
5TE~ ~ITH THE ACCU~UlATOR CONTAINING THE TURN-ON CHR-J77 4 0.)
7. SELtCT

RU~

MOOt. MASTER CLEAR. AND START,

8. wiTH LOC~OuT St T • T~E BOOTSTRAP PROGRA" WILL READ IN
THE dlNARY LOADER AND TRANSFER TO THE rlRST LOCATION or IT.
9,

r~R

THE REMAINDER or THE START UP PROCEDURE. SEE THE
~INAR' LOADER DESCRIPTION,

~OO!iT~APPED

1

'ROJECT NO. 510051 PAOGRA""EA E.E. O,HARE
45

EJE

46
47
50
51
52
53
54

8. WOOTSTRAP JORMATI
rlRST WORD or TME TAPE 15 TME LAST LOCATION PLUS aNI 0,
THE PROGAlM.

55
56

EACH WOAD IS COMPOSED 0' TWO lEVEN-liT CHARACTiRS IN
REVEASE OROEA.

61

THE fiRST CHARACTER, WHICH IS THE LOW OADER IEVEN IrTS.
IS DENOTED BY A PUNCM IN TAPE CHANNEL I.

'760
62
63

64
65
66

67
70

71

THE fOLLowING wORDS ON TME TAPE ARE STORED IN DECENDING
ORDEA.

BLlNK TAPE IS IGNORED WHEN LOOKINQ 'OR 'IRIT CHARACTEA.
THE SECOND CHARACTER, WHICH IS THE HIIH ORDSR SEVEN
BITS. 15 DENOTED BY A NON-PUNCH IN TAPE CHANNEL I.
I' , WORD CONTAINS TWO PUNCHES IN TAPE CHANNEL I, CONTAOL
IS TAlNS'ERRED TO THE IEIINNING or THE LOADED PADIR'".

72

n

....I
..,.

74
75
76
77
100

111
111

C. TIME DELAY

LOCKOUT AND A TIME DELAY AEPLACE THe READER INT&AAUPT.
THE TIME DELAY IS ".1) • 4.5US&C • 6209

•

.1,7SICONDS

THE SLONEST READER IS ASSUMED TO 8E 'ASTER THAN SIX
CHARACTEAS PEA SECOND.

D~TE

T I"E

41'l7/tJr;

E:iCOJECT 11;0.

r;JO~53

.....

I
C11

111
112
113
114
115
116
117
120
121
122
1" (
1/.1

1 :."
126
127
130
131
132

133
U4
135

136
137
140
141
142

P ,11.

PAGE

PROGRA"MER E.E, O.114RE

103
10"
105
106
107

UO

2150lJ')

3

!APE NUl'lttEH 512632

EJE
WIRED BOOTSTRAP F'OR TWE P-50 SERIES COMPUTER
00000
OIJOOO

01)001
0lJ002
01~003

OIJOO"

U005
0la006
01~007

0ia01O
01~011

OU012
OlaOl.}
0lU014
0 0015
1

0,~O16

Ou017
O[J02o
00021
00022
00023
000i!4
00025
00026
OU027

OOOC!O

10
14
37
01
36
20
02
14
14
27
37
36
21
24
01
27
32
31
30
24

00001
o 0"0
o 101
1 001
o 001
o 020
o 005
0 101
0 101
0 O'P
0 010
0 040
0 o4!O
0 O:U
1 001
aeoor;
o 100
o 020
o 003
a 100
0 000
1 020
20100
00040
00100
00000

UHG PC
OCT ~EADC
STOMAIi OCT L
2HALr ADD ~EMP
ql'lCON LSH ACC
S~L SiORAG.I
OCR i~ORAG
lHALF k':P READe
£JP L-l
::Ma Ace
~SM Ace
!.SH S~:F"Y7
~Ji3 L.-2
S":.. -':MP
HJP READt.:
E:':P b"'~F'
J"P STC.HAG. I
~EAIJC

l~Ai.F

-!

DCR "[I1DLY
PJP L-l
eN:" '!'I"CUN
S-~ '!I"DLY
IN~ .e
"-:'N
SHIrT7 ucr 20100
TEMP
I:UU 32
Tl"DlY cUU 64
I:ND

READ A CMARACTER AND IG~ORE,
STORAGE IIliDEX, rIRST WORD HERE.
COMBINE rlAST CHARACTER WITH FIRST.
PLACE BITS IN PRopeR POSITION.
STORE COMP~ETE WORD IN CORE.
DECREASE STORAGE INDEX By ONE.
GET rlAST CHARACTER or WORD,
IGNORE B~~NK FIRST CHARACTERS,
CLEAR TAPE CHANNEL 8.
SHIrT rlRST CHARACTER TO lOW END.
'iHE SHIF'~ IS PERrORMED SeVEN TIMES,
IS THE SMlr-ING OPERATION DONE1
STORE SHrF''iEO F'lHS· CHARACTER,
GEi SECOND CMA~ACTER or WORD,
IF' YI- ll:TAPE CM.8' orr. rORM WORD.
IF' ON. TRANSF'E~ "0 PHOGlh ' ••
r!AST Yl"E. REYUHN -0 GET r:RST CHR.
DECAEMENr ~I"E DELAY,
DELAY UN~I~ TI"E DEL.AY Ii NEGAqVE,
TJ "CON • (3·3,e4.5 e 6209 • ,16 7 SEC.
RESET DELAY WIT~ TIME DELAY CONSTANT.
INPUT ONE EIGHT-BIT CHAR,(6-1]).
RETURN WIT~ CHARACTE~ INPUTED,
FLAG rOR SHirTING SEVEN TIMES,
TEMPORARY STORAGE rOR rIRST CHR.
T IME DE~AY, AUTO"ATICAl~T RESET.

S

00
01

02
D3
04
05
06
07
10
11

12
13
14
15
10

17
20
21
22
23
24
25
26
2;

(5.
00020
00001
10040
14101
l7401
01001
U020
20005
02101
14101
14027
27010
37040
3tJ020
21001
2HOl
00005
01100
27020
leOOl
37100
laO •• 1./0 ;
2H20
20100 <"

DATE

PABE

4/27/b5.

PROJECT NO.

STARTED
OOMPLETED
NUMBER or
NUMBER or
NUMBER Or

5~Q053

PROGRAMMER E.E. O,HARE

./27/65. 2~50/00
4/21/65. 2/50/38

INPUT RECORDS
OUTPUT RECORDS
BINARY RECORDS

P.M.
P.M.
98.
98.
27.

4

BOOTSTRAPPED BINARY LOADER (S4A)
1.

Purpose
To load P-50 binary tapes into core with both latitudinal (parity) and
(checksum) error checking.

II.

lon~itudinal

Description of Operation
A.

Read in the "Binary Loader, Bootstrap Format" paper tape using the bootstrap.
(See Bootstrap Description for details.)

B.

Enter the following parameters if necessary:
1.

Put machine in WRIT E mode; depress the Master Clear button.

2.

Using the probe, load the S-Regtster with the parameter location.

3.

Using the probe, load the X-Register with the parameter constant; depress
the Start button.

4.

Repeat 2 and 3 until all the desired parameters have been entered.
Location

Preset

Description

X7750

300XX

Input command to access same reader as used by
bootstrap. (XX denotes reader channel.)

X7766

00007

Standard High Speed Reader Interrupt Location.

X7767

000] 0

Standard ASR Reader Interrupt Location.

X7771

X7601

Address, minus one, where control is transferred
when a stop code is read.

(X is 0, I, 2 or 3 depending on which bay the binary loader is in.)
C.

Read in the desired binary tape using the bootstrapped binary loader.
1.

Place the binary tape under the pnper tape reader. If the ASR reader is
used, the binary loader assumes that it has already been turned on by the
computer. (See turn on procedure in Bootstrap description.)

2.

Place machine in RUN mode.

3.

Depress the Master Clear button.

4.

Depress the Start button.

5.

If no errors are detected, the tape will be input up to and including the

stop or transfer code.
D. Normal Completion
1.

If the tape contains

A stop code at the end of the tape, the computer will
either stop with the S-Regtster (bits 0-7) set to 2028 or will transfer

2-1

automatically to the T<'P program in the P-50 Executives, depend I", on
whether location X7771 was preset to X7801 or 401.
2.

If the tape contains a transfer code at the end of the tape, the computer

will transfer control to the specified transfer location.
E.

Error Stop

If the error checking procedure finds an error, the computer wi
the S-Regtster (bits 0-7) set to either of the follOWing:

= 4:

1.

S-Regtster (0-7)

2.

S-Regtster (0-7) = 5:

stop with

Partty Error
Checksum Error

To reread the binary tape, replace It under the reader at the beginning of the
tape and depress the Start button.
F.

Using the Binary Loader after a Time Lapse
To read in binary tapes after other programs have been executed, the following procedure must be followed. (This assumes that the bootstrapped binary
loader remains in core.)

nI.

1.

Put machine in WRITE mode; depress Master Clear button.

2.

Using the probe, load the X-Register with the starting location of the
bootstrapped binary loader (X7602, where X =0, I, 2, or 3 depending on
which bay the loader is in); depress the Start button.

3.

Execute Step C of this section.

Program Comments
A.

When the bootstrap program transfers control to the binary loader. the input
command used by the bootstrap is stored in location X7750, thus the loader
is preset to use the same reader as the bootstrap.

B.

The loader assumes that the reader interrupt location Is either 78 or lOa.

C.

The input of a stop code on the binary tape will either result in a stop with
the P-Regtster set to X7602 or a transfer to the executives, depending on
how location X7771 is preset.

D.

The above three Items may be changed as Indicated In Section II. B.

E.

The bootstrapped binary loader does not load any Interrupt locations until it
is completely finished so that It cannot be Interrupted during the loading
process. Because of this precaution, the loader will not function properly
when an attempt Is made to load into core locations 74758 to 77778 or when
binary tapes are loaded consecutively in bay zero. (This Is no restriction
since the programmer's console will perform these functions once the executives are entered. Also, a binary loader In the binary form may be entered in this manner.)

2-2

IV.

F.

The bootstrapped binary loader will not load correctly into its particular
area of core (X76008 - X7777 8', where X =0, 1, 2, or 3 depending on which
bay the loader is in.

G.

A transfer to location zero or location 377778 is interpreted as a stop code.
Attempted storage into location zero Is ignored.

H.

Tapes containing the bootstrapped binary loader in the bootstrap format are
available from the Program Library for all four bays of core; tapes containing the binary loader in the binary form are also available for all four bays
of core.

Storage
Number of locations used:

V.

2008 (X7600-X7777).

Run Time
The bootstrapped binary loader runs at the speed of the reader.

2-3

PAGE
PROJECT NO. 530053

PROGRAM~ER

E.E, O.HARE

TAPE NUMBER 512633
BOOTSTRAPPED BINARY LOADER

1

2

PROGRAM LIBRARY
PROGRAM NO.
P-50

3
4

S4A

5

,

6

1. READ IN BINARY LOADER, BOOTSTRAP rORMAT, USING

10

T~E

11
12
13
14

2. ArTER THE HOOTS TRAP PROGRAM TRANSFERS TO THE BINARY
LOADER, THE BINARY LOADER wILL STOP .IT~ THE S-REGISTER
(BITS 0-7) SET TO A '202J.

15
16
17
20
21
22
23

24

25

26
27
30
31
32
33
34

35
36
J7
40
41
42
43

44

45
46
47

SOOTSTRAP PROGRAM (SEE BOOTSTRAP DESCRIPTION).

3. PLACE BINARY TAPE TO BE LOADED IN SAME INPUT DEVICE
AS USED BY THE BOOTSTRAP PROGRAM CTHE FORMAT or A BINARY
TAPE IS DESCRIBED IN T~E PROGRAMMER,S CONSOLE WRITEUP).
4. PLACE MACHINE IN AUN MODE, PUSH MAS TEA CLEAR BUTTON,
AND THEN PUSH THE STAAT BUTTON.
5. IF BINARY TAPE CONTAINS A STOP CODE AT THE END, THE
PROGRAM WILL EITHER STOP WITH THE S-REGISTER CBITS 0-7) SET
TO A [2021 OR TRANsrER TO THE P-50 EXECUTIVES, DEPENDING
ON HOW THE BINARY LOADER WAS PRESET.

IF BINARy TAPE CONTAINS A TRANsrER CODE AT THE END, THe
PROGRAM WILL TRANsrER TO THAT LOCATION SPEciFIED BY THE
TRANSF'ER CODE.
6.

IF' A PARITY ERROR (ODD PARITY CHECKING) OCCURS. THE
WILL STOP WITH THE S-AEGISTERCBITS 0-7) SET TO A (41.

PROG~AM

Ir A CHECKSUM ERROR (14 BIT SUM ON WORDS) OCCURS, THE
PROGHAM WILL STOP WITH THE S-REGISTERCBITS 0-7) seT '0 A [5).
TO ReSTART ON EITHER or THE ABOVE TWO ERRORS, DEPRESS
MASTER CLEAR BUTTON AND THEN DEPRESS START BUTTON, AfTER
REPOSITIO~ING TAPE IN INPUT DEVICE.

1

DATE

,A&E

4/27/65.

PROJECT NO. 530053 PROGRAMMER E.E. O.HARE
EJE

50
51
52

53
54
55

5.
5'
60

1. TO RESTART. SET THE P-REGISTER TO X7'02. WMERE 'Xl
IS EITHER O. 1, 2, OR 3 DEPENDING ON WHICH BAY or CORE
THE YINARY LOADER HAS BEEN ASSEMB~ED rOR.
••••••
••••••
••••••
••••••

N.B •••• THE BINARY ~OADER USES THE SAME INPUT DEVICE AS TMe
YOOTSTRAP. ASSUMES THAT THE INPUT DEVICE.S INTERRUPT IS
EITHER AT LOCATION SEVEN OR TEN (OCTA~), AND WILL NOT LOAD
CORE LOCATIONS 7475 TO 7777 'OCTA~) PROPEALY.

2

DATE

4/27/65,

T1P1E

2153139

PAGE

P ,1'1,

PROJECT NO, 530053 PROGRAI'1I'1ER E,E, O,HARE
61
62
63

TAPE NUMBER 512633

EJE
BOOTSTRAPPED BINARY LOADER rOR TWE P-50 SERIeS cOMPuTeR

64

65
66
00000
00000
00007
00010
00025

67

70
71
72

73
74
75
76
77
101
102
103
104
105
106
107
~1O

t,j

I
Q)

111
112
113
114
115
116
117
120
121
122
123
124
125
126
127

UNL
A
HED THE VOL.LOWING ARE
Eau 0
BAY
STPNO Eau 0
HSRLO EUU 7
ASRL.O BEau 10
RCHL.O BEau 25
STPEX BEau
STPYl BEau
RPT
DLE
STP
EUU

00402
07602
07602
07600
07600
07601
07602

32 1 370
37 o 350

07603
07604
07605
07606
07607
07610

32
37
32
37
01
27

0 365
0 375
0 364
1 375
0 375
0 205

07611
0761i
07613
07614
07615
07616
07617

23
32
37
32
37

0
0
1
0

BINLD BORG
ENL
STL.
STP

00 o 202

211
363
362
361
1 366

37 1 367

36 0 347

JSTART
J

J
J
J

402
BAY·10000~7602

STPND
STPND
STPBL
8AY-l0000·7600
ROCHl.1
INCOI1
l

PARAMETERS.
BAY or CORE WHEAE BINARY LOADER wILL BE
STOP INDEX' O-STOP, l-TRANsrER TO EXECS.
HIGW SPEED READER INTERRUPT LOCATION
ASR SET READER INTERRUPT lOCATION
INPUT DEVICE.S CHANNEL LOC. FRO" BOOTSTRAP

PROGRA~

STOP FOR EXECUTIVES (TOP ROUTINE)
STOP FOR BINARY LOADER
STOP IN BINARY LOADER (S-REGISTER • tz02'

GET CORRECT READER CHANNEL rAOM BOOTSTRAP
STORE INPUT COMMAND IN BINARy LOADER
NORMAL STOP FOR BINAAY LOADERI S-REG-t202J

ENl
STL
BENl
STL
OCR
PJP

ACC)
COUNT
2HOO)
COUNT.I
COUNT
L-2

NORMAL START FOR BINARY LOADER

CLJ
ENL
STL
8ENL.
STL
STL.
RJP

L·l
RORTN-l)
ACC·l
2,HOO·ACC+l)

CLEAR INITIAL LOCKour

STORE IGNORE INTERRUPTS tCLJ ,I • 23400,
IN ALL THE INTERRUPT LOCATIONS

STORE READER INTERRUPT RETURN
READER INTERRUPT COM"AND CCLJ ACC.l,l.

HS~IL.I

ASRJL.ol
If'4PUT

STORE IN READER fNTEARUPT ~OCATIO.S
IGNORE FIRST GARBAGE CHARACTER

3

DATE

4127/65.

TIME

2153/43

P,M,

PAGE

PROJECT NO, 530053 PROGRAMMER E,E, O,HARE
130

l\:)

.....I

131
132
133
134
135
136
137
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162

TAPE NUMbER 512633

~JE

07620
07621
07622
07623

36 0
05 0
21 0
22 0

276
316
223
250

07624
01625

31 0
10 0
31 0
12 0
20 0
32 0
37 0
36 0
01 0
21 0
37 1
10 0
37 0
32 0
10 0
01 0
21 0
32 0
20 0
00 0
24 0

373
360
374
351
232
373
374
276
376
236
374
373

07626
01627

07630
07631
07632

07633
07634
07635
07636
07637
07640
07641
01642
07643
07644
07645
07646
07647
0765n

373

374
356
376
231
373

217
005
202

NBNBK

RJP
EDR
EJP
SLJ

STL
ADD
STL
UNO
J
ZJP
ENL
NYNWO STL
RJP
OCR
EJP
STL
ADD
STL
ENL
J
ADD
OCR
EJP
ENL
ZJP
STP
.IMP
J

ISNWD
TORCS
L·2
STPTR

GET FIRST WORD OF NEXT BINARy BLOCK
CHECK rOR A TRANsrER OR STOP CODE

CKSUI1
ACC·2)

STORE AS FIRST WORD Dr CHECKSUM
MOVE ORIGIN ABOVE INTERRU?T LOCATIONS
STORE CURRENT ~RIGIN STATEMENT

O~IGN

30000)
NBNWO·1
CKSUM
ORIGN
18NWD
TORCS
L·2
ORIGN.I
CICSUM
CKSUP1
OtllGN
I)
TORCS
NBNWD
CKSUf'I
NBNBK
5
START

WORD IS A TRANsrER OR STOP CODE

ORIGIN STATEMENT IS IN BAY ZERO
ORIGIN NOT IN BAY ZEROI USE ACTUAL ORIGIN
STORE CURRENT ORIGIN STATEMENT
GET CONTENTS or CURRENT ORIGIN STATEMENT
WORD IS NOT A CHECKSUM' STORE CONTENTS
PLACE WORD IN CHECKSUM AND STORE
INCREASE ORIGN BY ONE
WORD IS NOT A CHECKSUM' GET NEXT WORD
WORD IS A CHECKSUM
BINARY BurrER CORRECT, PROCEED WITH NEXT
CHECKSUM ERRORI S-REGISTER SeT TO A riVE
ReSTART BINARY LOADER

4

nATe

412,/65.

T I ME

21531-4 b

PROJECT NO. 1)30053 PROGRAMMER
163
164
165
166
167
170
171
172
173
l1jf

115
176
177
200
201
202
203
204
205
206
207
210
211
t..:>
I

00

07651
07652
07653
07654
07655
07656

32 1 365
20 0 254
11 0 356
24 0 2~5
32 0 371
37 0 3H

07657
07660
07661
07662
07663
07664
07665
07666
07667
07670
07671
07672
07673
07674
07675

32
37
32
37
32
10
37
32
37
32
10
37

0
0
0
0
0
0

0
1
1

0
0
0
11 0
20 1
24 0

360
376
356
375
376
356
376
376
375
375
356
375
355
374
262

p. M.
E.~.

STPTR

PAGE
TAPE "UMBER 512633

O,H~i134

1

DCR
DCR
OCR
DCR
OCR
DCR
OCR
OCR
DCR
OCR
OCR
DCR
DCR
OCR
OCR
OCR

21
23
21

7115

1
1

14

1

16

1

1

20

2

23

2
2

25
26

~001
~003

..

13

15

LOCA T1 ON

2
2

CMB
CMS
CMB
CMB
CMB
CMS
CMS
CMS
CMB

7165
7165

23

7215

20

6547

22

6577
6547
7165
6577

20

21

22

23

7215

20

6547

21

7165
6577

22

23

7215

20

6547

22

6577

13

5434

20
22
20

6546

6546

22

6576

20

6576

6546

22

6576

20
22

6546

6576

DESCRIPTION OF STOP
CHECK
CHECK
CHECK
CHECK

STOP,
STOP,
STOP,
STOP,

SHOULD
SHOULD
SHOULD
SHOULD

OCCUR
OCCUR
OCCUR
OCCUR

STL INTO BAY 1 DID NOT NORK
STL INTO BAY 2 DID NOT WORK
STL INTO BAY J DID NOT WORK
CONTINUOUSLY OCR THE NUMBER IN ONE LOCATION AND SUBTRACT 3N~
FROM THE NUMBER IN ANOTHER LOCATION. BOTH DID NOT REACH ZEAC
AT THE SAME TIME
OCR NESATIVE NUMBER SET THE POSITIVE INDICATOR
OCR NEGATIVE NUMBER SET THE POSITIVE INDICATOR
OCR NEGATIVE NUMBER SET THE OVERr~ON INDICATOR
OCR NEGATIVE NUMBER lET THE OVERFLOW IND1~'TOR
OCR POSITIVE NUMBER DID NOT SET THE OVERFLOW INDICATOR
OCR POSITIVE NUMBER 010 NOT SET THE OVERFLOW INDICATOR
DCR POSITIve NUMBER seT THE ZERO INDICATOR
OCR NEGATIVE NUMBER lET THE ZERO INDICATOR
OCR POSITIVE NUMBER SET THE ZERO INDICATOR
OCR NEGATIV~ NUMBER lET THE ZERO INDICATOR
OCR POSITIVE NUMBER DID NOT SET END AROUND CARRY INDICATOR
OCR NEGATIVE NUMBER DID NOT SET END AROUND CARRY INDICATOR
OCR POSITIVE NUMBER DID NOT SET END AROUND CARRY INDICATOR
OCR NEGATIVE NUMBER DID NOT SET END AROUND CARRY INDICATOR
OCR POSITIVE NUMBER DID NOT SET THE POI'TIVE INDICATOR
OCR POSITIVE NUMBER DID NOT SET THE POSITIVE INDICATOR
CMB
eMB
CMB
CMB
CMB
eMB
CMB
eMB
CMB

NEGATIVE
NE;ATIVE
NE;ATIVE
NE&ATIVE
NEGATIVE
NEGATIVE
NEGATIVE
NEGATIVE
NEGATIVE

NUMBER
NUMBER
NUMBER
NUMBER
NU"BER
NUMBER
NUMBER
NUMBER
NUMBER

CHeCK LOCATION TEST (6604) Ir STOP INVOLVES TESTS 20-23.
P-50

D9A

5S-2

DID NOT
CLEARED
CLEARED
SEI THE
SET THE
SET THE
SET THE
DID NOT
DID NOT

SET THE POSITIVE INDICATOR
THE OVERFLOW INDICATOR
THE OVERFLOW INDICATOR
ZERO INDICATOR
ZEAO INDICATOR
END AROUND CARRY IN~JCATOR
END AROUND CARRY INDICATOR
SET THE POSITIVE INDICATOR
SET THE POSITIVE INDICATOR

IT OONTAINS THE TEST NUMBER.

STOP
30

31

3
3

33

;)

34

3

35

c."
I

01

DES~ATOR

3

MNEMONIC

TEST

LOCATION

5MB
S"B
S"B
5MB

12
13
21
23

5422

5"8

21

7164

~4J4

7164
7214

5MB
S"B
S"B
5MB
S"B

23

7214

21
23
21
23

7214
7164
7214

:'164

DESCRIPTION or STOP
5MB NUMBER SET THE POSITIVE
S"B NU"BER SET THE POSIT lYE
5"8 POSITive NUMBER CLEARED
5MB POSITIVE NUMBER CLEARED
5"8 POSITIVi NUMBER SiT THE
5MB POSITIVE NUM8ER lET THE
5M8 POSITIve NU"BER SET THE
5MB POSITIVi .uMBER SET THE
5MB POSITIVE NUMBER lET THe
5MB POSITIVi NUMBER SET THE

INDIC~TOR

INDICATOR
THE OVERFLOW INDICATOR
THe OVERFLOW INDICATOR
ZERO INDIC~TOR
ZERO INDICATOR
END AROUND C~RA' INDICATOR
iND AROUND CARRY INDrCATOR
POSITIYE INDICATOR
POSITIVE INDICATOR

36

3

60

6

SDA

10

~162

SDR IN ACCUMULATOR' IUBTRACT REAL VALUE.
ZERO INDrCATOR NOT SET

70

7

SOR

10

5162

SDR IN ACCUMULATO', SU8TRACT REAL VALUE.
ZERO INDICATOR NOT SiT

100

11)

ADD

15A

5526

lot

11)

102

11)

ADD

103

11)

ADO

ADD POSITIVE ZERO TO POSITIVE ZERO.
RESULT WAS NOT POSITIVE ZENO
ADD NEGATIVE ZERO TO POSITIVE ZERO,
RESULT WAS NOT NEGATIVE ZERO
ADD POSITIVE ZERO TO NEGATIVE ZERO.
RESULT WAS NOT NEGATIVE ZERO
ADD NEGATIYE ZERO TO NEGATIVE ZERO.
RESULT WAS ~OT NEgATIVE ZERO
ADD NEGATIVE NUMBER TO POSITIVE NU"BER'
RESULT WAS NOT NEGATIVE ZERO
ADD POSITIVE NUMBER TO NE.ATIVE NuMBER.
RESULT WAS NOT NEGATIVE ZERO
ERROR IN THE ADDER TiST, SEE THE PROGRA"

~526

S526

UA

~526

5526

ADD

104
11J

ADD

15"

lllJ

"DD

!'Sit

110

U

111

1:1

SUB

8

112

1:1

SUB

8

5075

113

11

SUB

8

~075

SUB

6

~ISTJNG

SUB A NU"8~R rROM ITSELf. RESULT WAS NOT ZERO
SUB POSJTJVE ZiRO rROM POSITIVE ZERO'
RESU~T WAS NOT NEGATIVE ZERO
SUB NEGATIVE Z&RO rROM POSITIVE ZERO'
RESULT WAS NOT POSITIVE ZERO
SUB POSITIVE Z~RO rROM NE~ATIVE ZeRO.
RESULT WAS NOT NEGATIVE ZERO

CHeCK LOCATION TeST (6604) IF STOP INVOLVES TESTS

20-~3.

P-so D9A SS-3

IT CONTAINS THE TEST NUMBER.

STOP

D!.tGNATOR

MNEHONIC

TEST

LUCAT!ON

114

11

SUB

8

'075

D~SCRIPTION

or STOP

SUB NEGATIVE ZERO rRO" NEGATIVE ZERO.
WAS NOT NEGATIVE ZERO
SUB PoS!TIVE NUMBER rROM SAME POSITIVE NU"BER
~ESULT WAS NOT NEGATIVE ZERO
SUB NEGATIVE NUMBER rROM SAME NEGATIVE NUMBER
HESULT WAS NOT NEGATIVE ZERO

~ESULT

115

11

SUB

8

~G75

116

11

SUB

8

~C75

120

12

AND

121

12

AND

122

12

AND

123

12

AND

14A

130

EOR

148

!:J500

131

EOR

148

~500

1 ··,
~-

EOR

148

~500

EOR

148

'::'500

LSH

17

~625

14

LS~
LS~

17A
17A

~6J7

145

14
14
14
1"

146

1~

133
c"
I
O'l

loS

140

141
142

143
144

CHICK

LOCArIO~

LS~
LS~

LSH
L.SH

54')1
14A

~451

~"51

24
24

~t37

6214
e214

2"

6214

2"

b214

ANO POSITIVE ZERO WITH POSITIVE
HESULT WAS NO- POSITIVE ZERO
AND POSITIVE ZERO WITH NEGATIVE
RESULT WAS NOT POSITIVE ZEAO
AND NEGATIVE ZERO WITH POSITIVE
RESULT WAS NOT POSITIVE ZERO
AND NEGATIVE ZERO WITH NEGATIVE
~ESULT WAS NOT NEGATIVE ZENO

ZERO'

EOR POSITIVE ZERO WITH POSIrlVE
RESUL.T WAS NOT POSITIVE ZERO
EOR POSITIVE ZERO WITH NEGATIVE
MESU~T WAS NOT NEGATIVE ZERO
EOR NEGATIVE ZERO WITH POSITIVE
HESU~T WAS NOT NEGATIVE ZERO
EOR NEGATIVE lERO WITH NEGATIVE
HESUL.: WAS NOT POSlrlVE ZERO

ZERO'

ZEAO.
ZERO'
ZERO.

ZERO'
ZERO.
ZERO'

L.SH NEGATIVE ALTERNATE ONES TwiCE
HESULT WAS NOT NEGATIVE ALTERNATEONES
LSH NEGATIVE ZERO, R&SULT WAS NOT NEGATIYE ZERO
LSH POSITIVE ZERO, RISULT WAS NOT POSITIVE ZFRO
LSW ALrERNATE ONES DID ~OT SET
THE OVERr~ow INDICATOR
L.SH ALTERNATE OHIS SiT THE EYEN INDICATOR
LSH ALTERNATE ONES SeT THE lERO INDICATOR
LSH POSITIVE A~TERNATE ONES SET THE POSITIVE OR
SeT THE END AROUND CARRY INDICATOR
OR LSH NEGATIVE A~TERNATE ONES C~EARED THE P051. IVE OR THE
END AROUND CARRY INDICATOR

TEST (6604) lr STOP INVOLVES TEsrs 20-23,
P-SO D9A

SS-4

IT CONTAINS THE TEST NU"BER,

STOP

OI1QG.NATOR

MNEMONIC

TEST

152

15
15

LSH
LSH

17&
178

153

16

RSH
RSH
RSH
RSH
RSH

21

23
21

RSH

23

7214

qSM

21

4SH

23
2l
23

7164
7214
7164
7214

1 p,

6(.;44

151

154
155

lr;~

16

16

16

1.~

. .,

1:'

RSH

1.6;)

1"

R: ...

23
21

RSH

~.j

I

-'I

LOCATION
~652
~652

7164
7214
7164
7214

7164

DeSCRIPTION or STOP
LoSH POSITIVE ZERO. R6SULT WAS NOT POS IT 1VE ZERO
LSH NEGAT I YE ZERO, R&5ULT WAS NOT NEGATIVE ZERO
RSH
RSH
RSH
RSH
RSH
SET
RSH
SET

NEGATIVE
HE GAT I VE
NEGATIVE
NEGATIVE
NEGATl VE
THE EV&N
NEGATIYE
THE eVEN

RSH

NEGAT1V~

"ISH

NEGAT 1liE

RSH NEGATIVE
115M

NEGATIVE

NUMBER SET THE END AROUND CARRY INDICATOR
NUMBER SET THE 6ND AROUND CARAY INDICATOR
NUM8ER SET THE POS I Tl VE INDICATOR
NUMBER seT THE POSITIVE INDICATOR
NUMBER WITH YITS 1-0 SET TO ZERO
INDICATOR
NUMBER WITH 81TS 1-0 SET TO Z&RO
INDICATOR
NUMBER CLEARED OVERrLOw INI)1CATOR
NUMBER CLEARED OVERrLOw iNDICArOR
~U~!)ER SET ZERO INDICA'OR
NUMBER SeT ZERO IND!CATOR
AL.TS~NATE O"'ESi SEE TkE PROGRAM ~lSiING
Ai.iERNATE ONE)I SEE TH~ ~ROGRlH l!\'I~~
ZiH~O. R6su~r w.S NOT POSITIVE ZERQ
ONE. RESU~T ~AS NOT POSITIVE ZERO
ZERO. RESULT WAS NOT NEGATIVE ZERO
O"'E. RE9U~T WAS NOT NEGATIVE ZERO

()

P5i-l

l~

b04~

161
Hl

H,

i-i~H

leA

~O74

1~

RS~

18A

[ D74

16.
UI§

1.6
It

~SH

RSH

18A
18A

R::," NEGAT I 'JE
115H POSITiVE
RS!-l PQS 11'1 VE
RSH POSITIVE

6074
607.c

RSH
fiSH

',71
172
173
114

17

RSH

18B

17

RSH

leE!

1.7

RS~

RSH

18B

1.7

6122
6122
6122
6122

RSH POSITIVE ZiRO. ReSU~T WAS NOT POSITIVE ZERO
RSH POSITIVE ONE, RESU~T WAS NOT POSITIVE ZERO
RSH NEGATIVE URO, RESULT WAS NOT NEGATIVE ZERO
RSH NEGATIVE ONE, RESULT WAS NOT NEGATIVE ZEAO

175

1,0

RSH

22
20
22
20

6546
6576
6546
6576
6546

22

6576

RSH POSITIVE NUMBER SET THE END AROUND CARRT 1ND I CATOR
RSH POSITIVE NUMBER SET THE END AROUND CARRY INDICATOR
RSH POSITIVE NUMilER DID NOT SET THE POS IT I VE INDICATOR
RSH POSITIVE NUMBER DID NOT SET THE POSITIVE INDICATOR
RSH POSITIVE NUMBER WITH YITS 1-0 seT TO lERO
DID NOT SET TH& EVEN INDICATOR
ASH POSITIVE NUMBER WlTH BITS 1-0 seT TO ZERO
DID NOT SET THE EVEN INOICATOR

ZJP
ZJP

3
10

5162

ZJP

DSIGCI< 6605

161

':

176

1.6

RSH

177

3.6

RSH

200

201

202
CHE~K

'!O

20
4~ !l

~OCAlrl0N

TEST (6604)

18E!
20

I~

~OO6

Nf:GATIVE
NEGATIVE

IoI1TH THE ZERO INDICATOR SET, ZJP DID NOT OCCUR
11H THE ZERO INDICATOR SET, ZJP DID NOl OCCUR
EOR ZERO SiT T~E ZERO INDICATOR
~

STOP 1NVOUES TESTS

p-s:>

20-~J.

DlA

ss-s

IT

CONTAl~S

T~E

TEST NU"BER.

DESCRIPTION or STOP
lOJ

304

30'

31'

307

10

10

10

10

10

SUB

20

b542

ADD

22

b572

SUB

20

SUB

21

7!60

ADD

22

6572

ADD

23

1210

SUB

21

7160

ADD

23

1210

SUB

21

1160

ADD

23

7210

SUB

20

b544

SUB
W
I

00

310

10

10

7162

ADD

22

6574

ADD

23

7213

SUB

20

6544

ADD

22

6574

SUB

20

b544

SUB

21

7162

ADD

22

6574

ADD

23

7213

CM6CK LOCATION TeST (66U4) Ir STOP

~NVOl~ES

SUB
DID
ADD
DID
SUB
DID
SUB
DID
ADD
DID
ADD
DID

sue

SET
ADD
SET
SUB
DID
ADD
DID
SUB
DID
SUB
DID
ADD
DID
ADD
DID
SUB
SET
ADD
SET
SUB
SET
SUB
seT
ADD
SET
ADD
SET

NEGATIVE HUMBER WITH HESULT POSITIVE'
NOT SET THE POSITIVE INDICATOR
TWO POSITIVE NUMBERS WITH RESULT POSI!IVE'
NOT SET THE POSITIVE INDICATOR
NEGATIVE NUMBER WITH RESULT POSITIVE.
NOT SET THE EVEN INDICATOR
PUSITiYE NUMBER WITH RESULT NEGATIVE'
NOT SET THE EYEN INDICATOR
TWO POSITIVE NUMBER WITH RESULT POSITIVE.
NOT SET THE EVEN INDICATOR
TWO NEGATIVE NUMBER WITH RESULT N&IATIYE.
NOT SE! THE EYEN INDICATOR
POSITIVE NUMBER WITH RESULT NEGATIVE'
THE POSITIYE INDICATOR
TWO NEGATIVE NUMBER WITH RESULT NEgATIVE.
THE POSITIVE INDICATOR
POSITIVE NUMBER WITH RESULT NEGATIVE.
NOT SET END AROUND CARRY INDICATOR
TWO NEGATIVE NUMBER WITH RESULT NEIATIVE.
NOT SET END AROUND CARRY INDICATOR
NEGATIYE NUMBER rROM POSITIVE WITH R&SULT NEgATIYE
NOT SET THE OVERrLOw INDICATOR
POSITIYE NUMBER rROM NEGATIVE WITH RESULT POSITIVE.
NOT SET OVERrLOw INDICATOR
TWO POSITIVE NUMBERS WITH RESULT NEIATIYE
NOT SET OVERrLOW INDICATOR
TWO NEGATIVE NUMBERS WITH RESULT POiITIYE.
NOT SET OVERrLOw INDICATOR
NEGATIVE NUMBER rRO" POSITIVE WITH RESULT NEIATIYE
THE POSITIVE INDICATOR
TWO POSITIVE NUMBERS WITH RESULT NEGATIVE
THE POSITIYE INDICATOR
NEGATIVE NUMBER rROM POSITIYE WITH R&SULT NESATIVE
rHE ZERO INDICATOR
POSITIVE NUMBER rROM NEGATIVE WITH R&SULT lSITIVE'
THE ZERO INDICATOR
TWO POSITIVE NUMBeRS WITH RESULT NEIATIYE
THE ZERO INDICATOR
TWO NEGATIYE NUMBERS NITH RESULT POSITIve.
THE ZERO INDICATOR

TESTS 20-23.
P-50 D9A SS-7

IT CONTAINS THe TEST NUMBER.

iTOP

nISIQ"J,TOR

MNEMONIC

TEST

~OCATION

210
211

21
21

EJP
EJP

19
19

6153
6153

EDN ZERO SET THE EVE" INDICATOR
WITH THE EYEN INDICATOR SET, EJP DID NOT OCCUR

221

22

SLJ

25

6236

SLJ, BUT JUMP DID NOT OCCUR

231

23

CLJ

25

6240

CLJ. BUT JUMP DID NOT OCCUR

241

24

JMP

2

5003

J"P DID NOT OCCUR

250
251

25
25

CJP
CJP

16
16

~606

~606

EDR ZERO SET THe END AROUND CARMY INDICATOR
wITH THE END AROUND CARRY INDICATOR SET, CJP DID NOT OCCUR

260
261

26
26

OJP
OJP

19A
19A

6170
6170

EDR ZERO SET THE OYERrLOW INDICATOR
WITH ~HE OYERrLOW INDICATOR SET, OJP DID NOT OCCUR

270
271

27
27

P~P

PJP

11
11

~230
523~

EDR ZERO SET THE POSITIYE INDICATOR
WITH T~E POSITIVE INDICATOR SET, PJP DID NOT OCCUR

300

10

SUB

20

6542

SUB

21

7160

ADD

22

6572

ADD

23

7210

SUB

20

6542

SUB

21

7160

ADD

22

6572

ADD

23

7~10

SUB

20

6542

ADD

22

6572

SUB
SET
SUB
SET
ADD
SEr
ADD
SET
SUB
SET
SUB
SET
ADD
SET
ADD
SET
SUB
SET
ADD
SET

301

302

10

10

CHECK LOCATION TeST (6604, Ir STOP

I~VOL~es

DESCRIPTION or STOP

"EGATIVE NUMBER WITH RESULT POSITIVE'
THE OVER~LOW INDICATOR
POSITIYE NUMBER WITH RESULT "EGATIVE'
THE OVERFLOW INDICATOR
TWO POSITIVE NUMBER WITH RESULT POSITIVE.
THE OYER FLOW INDICATOR
iWO "EGATIVE NUMBER WITH RESULT NEGATIVE.
rHE OVERFLOW INDICATOR
NEGATIYE NUMBER WITH RESULT POSITIVE'
THe ZERO INDICATOR
POSITIVE NUMBER WITH RESULT "EGAT1VE.
THE ZERO INDICATOR
TWO POSITIYE NUMBERS WITH RESULT POSITIYE'
rHE ZERO INDrCArOR
TWO "EGATIVE NUMBERS WITH RESULT NliATIVE.
THE ZERO INDICATOR
"EGATIVE NUMBER WITH RESULT POSITIVi'
rHE END AROUND CARRY INDICATOR
TWO POSITIVE NU"BERS WITH RiSULT POSITIVE.
THE END AROUND CARRY INDICATOR

TeSTS 20-23.
P-so D9A

SS-6

IT CONTAINS THE TEST NUMBER.

STOP

DfS" ;NA10R

MltEMOH!C

351

12

352

553

S54

355

....0,

c,.,

356

12

U

12

12

1~

357 •

1J

360

1J

361

13

362
361

13
13

TES~

LOCATION

AND

20

6546

AND

21

7164

AND

22

6576

AND

23

7214

AND
AND
AfliD
ANO
AND

20
21

l2
23
20

6546
7164
6576
7214
6546

AND

22

6576

ANC

20

6546

AND

22

6576

AND

21

7164

Atil:!

23

7214

AND

21

7164

AND

23

7214

EOR
EOR

20
20

6552
6552

EO~

20
21
21
21

6552
7170
7170
7170

EOR
rOR
EaR

DESCRIPTION or STOP
AND
THE
AND
THE
AND
THE
AND
THE
AND
AND
AfliD
AND
AND
DID
AND
DID
AND
DID
AND
DID
AND
SET
AND
SET
AND
SET
AND
SET

POSITIVE NUMBER. DID NOT SET
END AROUND CARRY INDICATOR
NEGATIVE NUMBER. DID NOT SiT
END AROUND CARRY INDICATOR
POSITIVE NUMBER. DlD NOT SiT
END AROUND CARRY INDICATOR
NEGATIVE NUMBER. DID NOT SET
END AROUND CARRY INDICATOR
POSITIVE NUMBRR. SET THE ZERO INDICATOR
NEGATIVE NUMIER. SET TME ZERO INDICATOR
POSITIVE NUMBER. SET TME ZENO INDICATOR
NEGATIVE NUMBERr SET TME ZENO INDICATOR
POSl!lVE NUMBER MITH liT 0 SET TO ZiRO.
NOT SET TME EVEN INDICATOR
POSITIVE NUMBER MITM BIT 0 SET TO ZERO.
NOT SET THE EYEN INDICATOR
POSITIVE NUMBER MITH liT 13 SET TO ONE.
NOT SET POSI~IVE INDICATOR
POSITIVE NUMBER NITH BIT 13 SET TO ONE.
NOT SET TME POSITIVE INDICATOR
NEGATIVE NU~8ER NITH BIT 13 SET TO ONE.
THE POSITIVE INDICATOR
NEGATIVE NUMBER WITH BIT 13 SET TO ONE.
THE POSITIVE INDICATOR
NEGATIVE NUMBER NITH BIT 0 SET TO lERO.
THE EVEN INDICATOR
NEGATIVE NU"BER NITH BIT 0 SET TO ZERO'
THE EVEN INDICATOR

EOR
EOR
SET
EOR
EOR
EOR
EOR
DID

POSITIVE NUMBER. CLEAR THE OVERfLOW INDICATOR
POSITIVE NUMBER WITH ALL ONES
THE POSITIVE INDICATON
POSITIVE NUMBER NIT" ALL ONES. SET THE ZERO INDICATOR
NEGATIVE NUMIER WITH ALL ONEI. SET THE Z~RO INDICaTOR
NEQATIVE NUMBER. SET TME OVERFLOW INOIC~ 1R
NEGATIVE NUMBER WITH ALL ONit
NOT SET THi POSITIVE .NDICATOR

CHICK LOCATION TEST (6604: IF' STOP INVOLVES TESTS 20-23.
P-50 DIA

55-9

IT CONTAINS THI TEIT NUMIER.

STOP

OEIJGNJ,!OR

312

1C

313

314

1~

10

320
321
322

"~E"ON~C

TEST

LuCATION

SUB

20

6544

AUO

22

~574

SUB

21

7162

ADD

23

7213

SUB

21

7:62

ADD

23

?213

ENL
ENL

5

EN~

22
20

~011
6~40
657~
~54U

334
335

ENL
ENL

6570

ENL

5

5022

ENL WITH ZiRO, THE ZIRO INDICATOR NOT SET

ENL
ENL

21
23
21

1151

ENL
ENL
ENL
ENL

23

7206

21
23
21
23

~157

ENL
ENL
ENL
ENL
ENL
ENL
ENL
ENL

NEgATIVE
NEgATIVE
NEgATIVE
NEGATIVE
NEGATIVE
NEGATIVE
NEGATIVE
NEGATIYE

NUMBER
NUMBER
NUMBER
NUMBER
NUM8ER
NUM8ER
NUM8ER
NUM8ER

AND

~o

AN~

21

6546
7164

23

7214

AND
AND
AND
AND

POSITIVE
NEGATIVE
POSITIVE
NEGATIVE

NUMBER.
NU"8ER.
NUMBERI
NUMBER.

EN~
EN~

336

337
350

1~

WITH ZERO. THE ZERO
POSITIVE NUMBER SET
POSITIVE NUMBER SET
POSITIVE NUMBER SET
POSITIVE NUMBER SET
POSITIVE NUMBER SET
POSITIVE NUMBER SET
POSITIVE NUMBER DID
POSITIVE NUMBER DID

6540
6570

E~L

3c

NEGATIVE NUMBER rROM POSITIVE WITH RESULT NEGATIVE
ThE END AROUND CARRY INDICATOR
TwO POSITIVE NUMBERS ~ITH HiSULT NEGATIVE
THE END AROUND CARRY INDICATOR
POSITIVE NUMBER 'ROM NEGATIVE WITH RESULT POSITIVE'
NOT SET THE POSITIVE INDICATOR
TWO NEGATIVE NUMBERS WITH RESULT POSITIVi.
NOT SET THE POSITIVE INDICATOR
POSITIVE NUMBER rROM NEGATIVE WITH RISULT POSITIVE'
NOT SET END AROUND CARRy INDICATOR
Two NEGATIVE NUMBERS WITH RESULr POiITIVE.
NOT SET END AROUND CARRY INDICATOR

22
20
22
20
22

ENL

330

SUB
SET
ADD
SET
SUB
DID
ADD
DID
SUB
DID
ADD
DID
ENL
ENL
ENL
ENL
ENL
ENL
ENL
ENL
ENL

E~~
EN~

324

D&SCRIPTION or STOP

AND
AND

20

22

6570
6540

7206
~157

1206
7~57

7206

6576

CHECK LOCATl:ON reST (6604) Ir STOP INVOLVES TESTS 20-23,
'-50 D9A 55-8

SET
SET
SET
SET
SET
SET
lET
lET

INDICATOR NOT SET
THE OViRrLOW INDICATOR
THE OVER'LOW INDICATOR
THE ZERO INDICATOR
THE ZERO INDICATOR
THE END AROUND CARRY INDICATOR
THE iND AROUND CARRY INDICATOR
NOT lET THE POSITIVE INDICATOR
NOT SET THE POSITIVE INDICATOR

THE
THE
END
END
THE
THE
THE
THE

CLEAR
CLEAR
CLEAR
CLEAR

OVERrLOW INDICATOR
OVERrLOw INDICATOR
AROUND CARRY INDICATOR
AROUND CARRy INDICATOR
ZERO INDICATOR
ZERO INDICATOR
POilTIVE INDICATOR
~OSITIVE INDICATOR
THE
TME
THE
TME

OVERrLON
OVERrLOW
OViRrLON
OYER'LOW

INDICATOR
INDICATOR
INDICATOR
INDICATOR

IT CONTAINS THE TEST NUM8ER,

STOP

1'ISJQNATOR

"NE"ONIC

TEST

31
31
31
31
37

3"

37

376

37
37

STL
STL
SlL
STl
STl
STl
STl
STl
STl
STl

7

371
172
373
374

370

:In

9

21
20
20
21
20
21
20
21

LUCATION
!»Dl!)
!)14!)

1172

6554
6554

7172

6554

7172

6554

7172

DESCRIPTION OF STOP
STL
STL
STL
STL
STL
STL
STL
SlL
STL
STL

A NURIER. IUITRACT ITI THe lERO 'NDICATOR NOT se~
A NURIER' SUITRACT ITI TME lERO INDICATOR NOT SiT
POS,TlVE NUNBER. SET THe OVERFLOW INDICATOR
Ne&AlIVE NURIERI CLEAR TME OVERFLOW INDICATOR
Me&AlIVE NUNIER. SET TME ZERO INDICATOR
POSITIVE _NIER. SET TME ZENO INDICATOR
NE&aTIVE NUNBER. SEl END THE AAOUND CARRY INDICATOA
POSITI"E NURBERI SET END TMe AAOUND CARAY 'NDICATOR
NE&ATIVE NUNBeR. SET POSITIVE INDICATOR
POSITiVe _NBERI DID NoT SET THE P051TIVE INDICATOR

CHICK LOCATION TEST (6604) ,F STOP ,_VOLVES TeSTS

2D-2~.

. . . . . . . 15-1.1

IT CONTAIN. THE TilT NUMBER •

· 'ME

~1/~7!O'

• H.

PAGE

1

COMMAND ElECUTi TEiT

2
3

PHOfiRA" ~IBRjR'
PHOiRAM NO, P-50 09&

4

5
6

,
10

OECHE"ENT COUNTER MACRO

OSK

11
12
13
14
15
16

"AC INDEx.T'ST,~OO~
DCM ,NOEX

tJP TEST
J"P LOOP
~l:~

ERROR STOP MACRO
ERR ABC WHERE ABC IS SOME NUMBER REriR5 TO STOP AHe
S-REGISTER CONTAINS ABC
O~SIGNATOR CONTAINS &B
liN MOST CASES)

17

20
21
22

EHH

~UR

23

2'

A1

A2
JMP JUMP
Tl:N
~TP

24
26

"AC Al,A2.JUMP

"NE

yrO 5,l&1t

1

DATF

PAlii

3122165.

PROJ&CT NO, 5J005J PROGRAMMER J,E
27
30
J1
32

JJ
34
35

36
37
40
41

42
U

44

4'

46
47

50
51

52
53

'4

"'6

51
60
61

PHIL~tPPI

2

TAPE NUMBER 345116
Ir A STOP Ii

D'SJ~ED

ArTER ONE CYCLE. DO THE

rO~~UWIN'

SINCE THERE IS A TRANsrER CODE AT THE END or THE TAPE.
THE TEST W1LL BEGIN I"MEDIATELY AfT&R IT IS READ IN
HOWEYER, ArTIR ONE IN5TRUCTION HAS BEEN EXECUTED. iHE
"ACHINe WILL iTOP WITH THE S-REGIS'ER CBITS ,~O) SET
TO 1, THIS IS THE rlRsr CHECk S'OP or THE TEST
1.
2.
J,
4.
5.
6.
7.
8.

WHEN &TOP 1 OCCUR5. DEPRESS THE 5TOP BUTTON.
PUT THE "ACMINE IN MRITE "ODE.
DEPRESS THE MASTER CLEAR BUTTON,
USIN& TME PROBE, LOAD TME S-RE&ISTER NITH 6244,
USINS TME PROlE. LOAD TME X-RiIISTER NITM 6,
DEPRESS TME START BUTTON.
DEPRESS TME "ASTER CLEAR lUTTON,
USIN& TME PROlE, LO,D THE x-RESISTER NITH THE
STARTINS LOCATION OF TNE '&IT. 5000.
9. DEPRESS THE ITART IUTTON.
10, PUT THE "ACMINE IN RUN MODE.
ll.DEPRESS THE "ASTiR CLEAR BUTTON.
12; DEPRESS TME "ART IUTTON.
13. TMi TEST SMOULD RUN THROUSH ONE CYCLE, STOPPING
AT TNE FOUR CHECk STOPS AND CONTINUING.
14. WHEN ONE CYCLE IS COMPLETE. TMi "ACHINE Will ~TOP
NITH TME S-RESISTER eBITS 1-0) SET TO 6.
1'. ONE CYCLI RUNS rOR 14 SECONDS,

62
63
64

.,
66
67
10

71
72

n

74
75
76

TO NESTGRE TWE CONTINUOU£ CYCLING or TWE
THE rULO".NS,
1. DEPRESS TWi STO' IUTTO_.
2. PUT TWi MACN.NE IN .RrTE "ODE,
J. DEPRESS TWi "ASTER CLEAR BUTTON.
4. USING TN& PROlE. LOAD TME S.REGISTEk
5. USING TME PROlE. LOAD THE X-REGI5TER
6. DEPRESS TWi START IUTTON.
7. DEPRESS TME "ASTER CLEAR ~UTrON.
8. USIN8 TME PROlE. LOAD TME X.REGII'ER
STAR·l_S LOCATION or TME TiST, 5'00.

TEST, DO

MlrM 6244.
NITM 24745.
wrTM 'HI

DATE

PAGE

3/22165.

~7

100

lei

UZ
10l
104

9,

·HE STAAT HUrTOH,
PUr THE "ACHINE IN RUN "ODE,
11;DEPR~SS THE "ASTEA CLEA~ BUr!ON:
12, DEPR~SS 7HE START 8UTiOH,
13. rHE ·ES~ WILL RUN CONYINUOUSLY
T"E CHECK 5'OPS,

J

DE~H~SS

10·

A~T&R

STOPPI"' AT

DATE

ll22165.

TIME 11/29/57

lD1

A.".

PAGE

~JE

~D6

INITIALLY THE PAOGRAM &TOP5 AT 4 CHECK STOPS

'107

110
111

05001

IOHG 5001

'112

TEST 01

113
114
115
loU

117
tao

1'21

122
113
124

0100l
05002

~

05

o

377

04001

JTEST018EDA 5 )
MNE 4 •• 1

iDR

ENTER DESIGNATOR WITH A NUMBER N, N.5, AND STOP
S-REGISTER IS 1
IF" DESIGNATOR IS N. ASSUME EDR WORKS
IF" DESIGNATOR IS NOT N
1. CHECK LOCATION 5oS77 SHOULD IIi 5
2. Ir LOCATION IS 5, EDR DOES NOT WORK
J. I r LOCH I ON IS NOT 5. MAKE IT 5 AND ReSTART

116
1.17

c.J
I

I--'

O'l

TEST 02

130
1.11
112
113

137

140

05003
05004
05005

24 0 010
0' 0 376
00 0 240

JMQ

JUMP AND STOP
DESIGNATOR IS
IF" S-REGISTER
IF" S-REGISTER
COMPARE

1~

13'
136

4

TEST02 J"P L.·6
IEDR 24)
8STP 240

24
IS 2. ASSU"E .IMP WOAKS
IS 240. JUMP DID NOT OCCUR
LOCATION 500J WITH LISTING

DUE

'3/2216!1.

TIME ll/JO/OO

A.M,

'ROJICT NO. g30053 PROGRAMMER J.E. PHILLIPPI TAPi NUMBER 141116
~41

EJE

142

TEIT 01

145
144
145

146
1..,
11.
1'1
1'1

ta

.'OU

"011

.,
II
14
"

"7
III

"014

"

111006
11'007

"4
1"
.1013
U. ""1
1.61

S,~

'I''''

0 In
0 OU
0 261
0 316
. . 002
14 0 ell

"TiSTnIEDR 10»

"

0 374

"00.1

'.71

L.'

NNE

U.

".
''H

I'

It",

RETURI JU", ,ND IT"
DEIIINATO.
36
I' S-RIIIITE. IS 4. ASIU"E R", WORKS
I' STOP DOli NOT OCCUR. JUNP DID NOT OCCUR
CHICK LOCATION 11'6 CO",AR' MIT" LISTIN'

'1

U~

36 0 III

ZJ' WDRKI
DID lOT OCCUR
SHOULD
ll-IERO INDICAT"

4 •• 3

T,IT 14

11'0"

INDICATOR AND ZIRO JUN'

IE DR 20'

Ut

sn

INTiR OEIIINATOIl WITH ZERO
DiSla"ATDR II 21
IF I-REIISTiR II 3. ASIUME
IF S-RiIIIT,. '1 a••• JU"P
CHICK LOCATIO.

ZJP
"NP illlllll
IEDR 24,
NNE 4 •• 2
JNP TlIT03

UI

S7J.

IJP

TEiTU

HJP ITOPCK

DATE

1/22/6'.

PROJBCl NO.

TIME

'~OO'3

11/~0/0~

A.M.

PAGE

PROGRAMMER J.&. PHILLIPPI JAPE NUMBER

17J

TEST 05

1.7'
17.
~77

au
au

102

213

111

UI

au

au
21J

U4

•

373
20 0 021
24 I 272

0'017
.,.20
"121

32

.'122
0'123
05024

33373
20 o 024
24 o 325

./TEST05 ENL 0'
lJP L·2
.IMP ERRJaO

au

I

""""
00

221.

an
al3
22.
225

ft6

D1

aso
211

au

UI
114
2J,

ENL (311

fiST 06

217
Uo

0'02'
05026
0'027
D5o.JI
1'011
15132
I'IU
0'014

32
11
20
24
32
11
ZO
24

o 372
1 371
.30
I 275
0 171
I 171
I 014
0 275

°

JTEST061ENL
SUB
ZJP
.IMP
liNL
J
SUB
lJP
J"P

J

21476)
Ace
L.Z
iRRUO
1611U
ACC
TEST07
ERRllO

iNL

ENTER ACCU"ULATOR W(TH .tiRO AND ZiRO JUM'
IF STOP OCCURS
1. S-REGISTER IS 320
2. DESIGNATOR IS S2
~. CHECK lCCU"ULATOR 101 SHOULD IE ZERO
4, CHECK LOCATION 5373 SHOULD BE lliRO
I~ LOCATION IS ZERO, ENL DOES NOT MORK

IMNE 33 .. ~73
lJP TliST06
.IMP ERR330

216
w

~4'11'

iJE

t~4

204
205
al6

•

SUP

ENTER ACCUMULATOR WITH SOME NUMBER N. SUI TRACT N. ZJP
IF STOP OCCURS
1. S-REGISTER IS 110
2. DESlaNATOR IS 11
3, CHECK ACCU"ULATOR 101 SHOULD IE ZERO
IF ACCUMULATOR NOT ZERO. SUB DOES NOT MOtelC

SATE

.~Ia/".

TIME

11/~O/a7

A.M.

'AGE

7

paoJiCT WI. " •• '~ PROgRAMMER J.i. PHILLIPPI TAPE NUM8ER ]45116

...
....,"4...

EJE

01

07

TEST 07

Ml
MI

SUBTRACT Y. lERO JUMP

ENTER ACCUMULATOR

..
lSI
aN

a',

WIT~

SOME NUMBER HI STORE N IN Y

If STOP OCCURS

~

••7
Be
8t

iTl

1. S-RiQISTER IS J70
2. DESIgNATOR Ii l~

.,••,

31 0 3'7

• ••11
"1.1
••••,

11 • •1'
a..
141
I"
III

",.1 37' a63

JTEST071iNL J7776'
iTL TEMP
lUI TlMP
JJP nST7A
JMP iRRnG

3. CHECK ACCU"ULATC~ SHOULD Ie ZiRO
4. CHECK LOCATIONS 5167 '261 SHOULD 8E EQUAL
tr NOT EQUAL ITl DOES NOT WORK

~!"E

11""09

156
"7
"1
2'1
262
263
264

A;~.

EJE
T~ST

I.,

w
I

I:\:)

0

'.1
a'2
1"
1.4

I"

1'1
1'7
11'
all
all
all
al"
al'

III

117
12'
121
liZ
all

STL

SI"ILAM :0 Ten 01
N IN TWREE OTHER BATS or CORE
I~ STO" OCCURS S AEGISTER IS ,
1. DESICiNATOR Ii 1
iA' 1 DOES NOT EXIST OR
N STORED INCQRREcrLY IN ,
, AND LOCATION 5372 SHOULD
2, DESI&NA·OM IS 2
BAT 2 DOES NO~ EXIST OR
N STORED INCORHECTl' iN Y
Y AND LOCATION 5110 SHOULD
J, DEStGNATOR Ii ;S
BAY ~ DOES NOT EIIST OR
N STORED 'NCORRECTLY IN Y
, AND LOCATION 5372 SHOULD

~-ORE

a"2"

Z'7
17.
171
271
17a
17.
17'
176
277

7A

.

"'.2
.5 ... 3
.5,.. 4

.,.,....,
.5... ,
.'.10

""1
""2
.5.53

.,.,..

"",
"1'6
"1'7

"I"

""1

"'12
,'.11
,5'1"

"."
"'I'
IU
""
".11

12 ,
I? 1
n I
11 1
12 1
11 I
21 0
" I

III
166
11"
165
1'6
112
.51
16.

,,,,,5

al o 11'
a7 1 III
II o 17.
17 1
12 1 , , ,
11 • 171
I.
, 112
.....5
II • 172
a7 , 1'7
12 • 174

I.'
., , .,1
J1

1 II'

,:,eS~7AliNL

J
J

J

IslL
Ie ilL
IsTL
liNL
'SUB
lJP
EDR
..lie

21476)
17716 •• 1
21.
77761 .1
11776 •• 1
2141.)

L·I

11
.... 5

'EII\. 'IIOU

J

.STl 2777'1: I
lEN'. 20'
l~lL

J

777, •• 1

Ie II:. 277761 .1
Isua lilD1)
l.JP L.I
EDit 2.
.... e 4 •• 5
Itl".. 214~')
I~"'L 17716». I

.e-.
,••
• tt!L 7176». I

-,-"

T IS 17776
iE EQUAL
Y

IS

~7176

IE EQUAL
Y IS 11776

liE EQUAL

DArE

l/221U.

TI ME 11/30/13

PAGE

A,M

PROJECT NO. '!SJOO53 PROGRAM"ER J,E, PHII.'-!PPI T4PE NUMBEH 345116
l26
327

no

.1U
3U

n070
05071
D5072
05073
05074

l2 1 367
11 o 372
ao o D74
05 o 361
04005

8EN!. 377~6)(1
8SU8 21476)
lJP TESTOff

J

':IlR 31

"HE

4 •• 5

9

".".

OHE

11221".
Tl"E 11/30/14
;J'fOJECT NO. !~I053 'ROGRA""ER J,E, PHILLIPPI TAPE
113
114

343

344
14,
346
347

ISo

"1
311
1S3
354
3"
lI6
317
360
361
c.v

I
1:\:1
1:\:1

362
3n
364
36,
366
367
370
.J71
.)72
373
37.
.J7!I
316

J45116

NU"~eR

EJE
nST 8

In

136
317
340
141
142

"AGE 10

SUI
ACe

05075
05076
05071
05100
05101
05102
0510,)
05104
05105
05106
05107
"110
051U
05112
05U3
05114

0511'
05116
05111

oUao

15121
05122
05123
05124
0512'
05126
05127
O5UO
05111
0'112
.'111

~2

0

11
20
24
27

0 37.1

TES!08 ENL 0)

37~

0 100
0 3.JO
0 017
;sa 0 37~
11 0 160
2. 0 105
24 0 377
21 0 107
24
104
12 0 360
U 0 37$
ao 0 1105
24 1 IS7
27 0 112
32 0 360
11 0 ~60
ao 0 120
24 1 J~6
27 0 117
n 0 355
11 0 355
20 0 125
a- t 354
27 0 124
32 0 351
11 0 J5J
20 0 U2
24 1 3!)2
27 0 131

~UB

y

RESULT

ERROR

·0

·0

-0

111

·0

-0

·0

112

-0

·0

-0

113

-0

-0

-0

114

.N

·N

-0

115

-N

-N

-0

116

OJ

t.JP 1.·2
J"P ERR111
PJP 1.-1
l:NL OJ

J

•

J

J
J

J
J

J

SUB
I.JP
J"P
"JP
J"P
ENL
SUB
ZJP
J"P
"JP

aO)

~NL

1.·2
ERR112
1.·2
1.-2
-D)
0)
1.·2
ERRU1
1.-1
-0)

~UB

-0)

t.JP
J"P
"JP
&ENI.
8SU8

1.·2
ERRU4
1.-1
1252~ )
12525)
t.J" 1.·2
J"P ERR115
PJP 1.-1
&ENI. 252~;'D
8SUS 252!)2)
lJP 1.·2
J"P EARll'
PJP 1.-1

DATE

31221611.

TIME 11/.10/18

'.M.

P'fiE 11

PROJECT NO. '30053 PROGRAMMER J.E. PMILLIPPI

CI)

I
I.\:)
Co)

317
400
401
402
403
404
405
406
407
410
411
412
413
414

415
416
417
420
4at

422
423
424

'APE NU"~EH 345116

EJE
Tl:iT

SA DCR

CHECK DtCREMENT WITH SUYTRACT
ENTER ACCUMULATOR WITH N, STONE N IN Y
SUBTRACT 1 AND DECREMENT Y CUNTINUOUSLY
JUMP WHEN ACCUMULATOR ZERO
If STOP OCCURS
1. i-RE; ISTER 15 10
l, DESIQNATOR IS 1
J. CHECK ACCUMULATOR 101 'MOULD liE liRO
CHECK LOCATION 5263 SHOULD 8E ZERO
IV NOT ZERO OCR D06S NOT WOAK

".

05134
"U5
"136
05U7
O!U40
05141
05142
05143
05144

32 0 367
37 0 263
20 0
D1 0
11 0
24 0
32 0
20 0
24 0

141

26.5
364
135
263
144

303

TEST8UENL
STL
ZJP
OCR
~UB

JMP
ENL
ZJP
JMP

J1776'

TEMP
L·4
TEMP
l'
L-J

TEMP
TESTQ9
ERROlO

lUi

ll2l1n.

TIME 11/JO!21

4n
416

A.M.

PAGE 12

EJE
TUT 09

427

4.11
4.u
432
4,u
4U
4;n
436
4J7
440
4"
442

nl

JTEST091~NL

,hn n

2..
15.

J

...,

• 'lJl

2U

n,

11154

451

UU'
01157
0'160
05Ul

44~

444

441
4.7

412
4U

w
I

I:\:)

"'"

4'4

0514'

3Z

nUl

17

n

11151
11152

31
17
11
ZO
24

"111

nu'

It
01
20

24

261
264
264
it'
UI
263

10000.

STL INDU

IENL 20"0 •
SlL UM'
J"P09A ENL TEM'
ilL TiM'A
iUa YI"'A
1.1' L,.Z
IIIU11
OCR TEM"

.I"'

266

OCR INDiA

161
UO

lJP TUTU
J"P J"POU

iTL

SA"E AS YEST 01 ONLY MORE EXHAUSTIVi
T~S~S 10000 NUM8EMS
Ir STOP OCCURS
1. S~REGISTER 15 J71
2. DESIGNATOR IS J7
1. CHECK ACCU"ULATOR 101 SHOULD B& ZERO
4, CHECK LOCATIONS 526J 5264 SHOULD BE EQUAL
Ir NOT EQUAL stL DOiS NOT WORK

DATE

312216!J.

TIME 11/30/23

A.~,

PAGE 13

OROJECr NO. '30053 PROGRAMMER J,E. PHILLfPP, TAPE NUM8ER 345116
45'

6JE

4"
4'7

TEST 10

460

4'.1
462

463

464

:I

en

472
47.1

014
415
4'.
471

900
'01

'oz

"113

,.,
,..
504

'17
'It
'11
'12
'13

51.
'15

,.

05162
05163
0'164
0'165
05166
05167
05170
05171

0 201
06 0 a6l
12 0 262
11 0 26.1
20 0 167
2" D 311
36 D 214
36 0 201

05172
05173
05174
05175
05176
05177
05200

07262
0262
o 263
o 176
1 147
0 214
0 U7

32
11

20
24
16
24

TESTlO RJP At

J

SDR
ENL
SUB
lJP
.IMP
HJP
RJP

SAVe
SAVE
TEMP
L·a
ERR060

'MHE
ENL
SUB
ZJP
J"P
ItJP
.IMP

7" 262
SAVe
TEMP
L·2
ERR070
102
TEST11

iDR

ENTER DESIGNATOR WITH N-37-30,17-1D (ZEAO INDICATOR)
l:AO JUMP TO STORE D56IQNATOA IN Y
ENTER ACCUMULATOR WrTH Y. iUBTRACr N, ZEAO JUM'
IF STOP OCCURS
1. S-R&GI5TER IS 201
DESIGNATOR 1S 20
CHECK INrTIALIZER 5346 SHOULD BE 31
CHECK COUNTERS 5362 IS 2
5J75 IS 10
N LOCATION 5263 HAS RANGE U-iO, 11-10
THIS IS ZERO INDICATOR (ilT 3)
2. S-R&GISTER IS 60
DESIGfUTOA IS 6
CHiiCK LOCATIONS 5262 !iau SHOULD BE EQUAL
I' NOT EQUAL SDR DOES NOT wORK

A2

A1

SDR

C7)

DAT£

~12216!1.

NClJIECT

.0.

A."'.

TIME 11/30127

530053

PAOGA'MMER·J.~.

5~6

517
520

5ft
522
521

'24

525
526

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05201
05202
05203
05284
0521'
05206
05107
05210
05211
05212
05213
05214
05215
05216
05217
05228
05221
05222
05223

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o 346
37 o 263
32 o 362
37 o 261
32 o 315
37 o 261
05 o au
32

20 0212

2" r; 314
24 1 201
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01

o a63

01 0 267
20 0 rUG
24 8 201
J2 0 263
11 0 375
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At

J

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01
20
24
24

0 261
0 226
0 205
1 214

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TEMP
2.
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TEMP
INDEXA.JMP10C.JMP10B
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TEMP
INDEXB.ATN.JMP10A
OCR 'NDEU
ZJP RTN
JMP JMPlOA
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DSK

05224
15225
05226
05227

37'

lATE

II221U.

PIIO.lECl NO.

TIME 11/10/30

'300~3

PROGRAMMER

A.".
J.~.

9"

PAGi 15

PH1LlIPPI TAPE NUMBER 345116
EJE

~43

TEST 11

944
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~

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0.246

2. 0 246

"247

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32 0 213

11 0 343
J7 0 263

TESTll iDR
.,JP
J
8ENL
lHL
J
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JJMP1U ENL
STL
JMPlla EDR
PJP
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DSK
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.,2,2

01 0 261
20 1 342
24 0 235

STL
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115230

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1152U
UU4

,"con

'~IU6
'~5U7

1111240
1111241

111242

15241

05253

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27 0 322

12 0 345
37 0
12 0
17 0
n 0
37 0
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27 0
24 0
01 0

263

344
261
J4J

267

263
242

311
263

01 0 267

24 0 U7

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ERA210

77 ,

TEMP
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INDUB

4'INDEU

TiMP
L .2

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TiMP
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INDEU
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TliMP

5UB 4'

J

DESIGNATOR NITM POSITIVE INDICATORS AND PJP
IF" iTOP OCCURS DESIGNATOR IS i7
1. S-REGISTER IS 270
INITIAL CMEC~ - ENTER D'51aNATOR WITM ZERO
A~D POSITIYf JUMP TO STOP
CMECK LOCATION 5373 SHOULD BE ZERO
If ZiRO. PJP OCCURS WITHOUT PROPER INDICATOR
2. i-R&aISTER IS 271
CH~CK INITIALllER
5345 SHOULD BE 77
CHE~K COUNTERS
5JU IS 7 ~U~ IS 4
POSITIVE INDICATOR (81T 2) 51163
H' III T 2 ON PJP DOEi NOT WORK

TiM'
INDElB.TEST12.JMP11A
INDElS
T&STU
J"P1U

nnE

3n2l6~.

TIME 11/30/34

PROJftT NO, 530053

P R OGFUMI1ER

,U
'OJ
'16
607

610

05 0 340
00 0 320
24 0 024

0'27.
05277
05300

00 0 110
24 0 OJ4

05301
05302
.5303

05 0 346
00 0 370
24 0 041

au
au
au

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05305
IS.l06

05 0 364
00 0 010
24 0 144

q4
614

.

05307
.5310
05311

05 0 346
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24 0 161

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6a5

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(JJ

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05273
01274
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616
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617

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611
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621

613

614
614

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61.3
614

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EJ~

05255
05256
05257
05260
05261
05262
05263
05264
05265
05266
05267

61t

",

J.E. PHILLtPPI

... 2

IDJ

..

J

8ElJH

36'
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IUN

INDEXB OCT 0
SAVE
OCT 0
TEMP
OCT 0
TEMPA OCT 0
TE"'PB OCT 0
INDEX OCT 0
I NDEXA OCT 0
ERR2008ERA 20,.200.TEST04
EDR 20)
STP 200
J"P TESTO"
ERR3208ERA 32,.J20.TE6T06
J
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iTP 320
J"P TEST06
ERR1108EMR 11),110.TE5T07
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EDR 11)
STP 110
J"P TESTOl
ERRJ70BERP. 37)'HO.TiliT7A
EDR J1)
STP 370
J"P T6STH
ERROlOBERA i),lO.TEST09
EDR i)
STP 10
J"P TESTg9
ERRH11ERA U) .J71,TESTlO
EDR .17)
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.I"P TESTlO
ERR060l£MR 6).6U.TESTU
J
EDR 6'
STP 60

345116

DATE

3/22/U.

i--HOJI!CT NO.
6i5

TIME 11/30 / 38

626
626
627
627
627
627

630
630
630

no

c:.J
I
[~

co

631
631
631
631

PROGRAMMER J.E. PIo41LLIPPI UPE

Cli5314

24 0 227

Q15315
nU6
nU7

00 0 201
24 0 227

015320
0>5321
05322

05 0 335
00 0 211
24 1 342

05323
05324
05J25

05 0 335
00 0 270
24 1 Hi

05326
05327
05330

05 0 334
00 () 330
24 0 Oil!4

05331
053J2
05333
05334
05335
05336
05317
05340
05341
05342
05343
05344
05345

05 0 337
00 0 111
24 o 144
00033
00027
00006
00011
OOU2
OOU6
05421
00004
00007

0~346

OS341
,USO

00031
05416
20010

05352
05353
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05410

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12525

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U356

05415

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1

Ol§

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374

632
632

6Ja
632

PAGE 17

~IJ005J

626
626

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oust

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uno

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.IMP TESTll
ERA4!018EHR 20.,;lOl,TEST1!.
tOR CUI

STP 201
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&RR2708ERR "l),270,TEST12
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ERRJ308ERR 3J),.uO,TESTD6
J
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ERRl118ERR l1,.111.TEST09
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IIIHD
.. HO
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0,371
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0,362
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0,364

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OOOOi
'i.7:" !6
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16301
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18

DATE

312216~,

•

TIME 11/30/ ••

A."'.

PROJECT NO, !iJO,J'iJ PROGRA"'''Ii::-! .) . i •
633
633
633
633
634

0'400
U5.01
1,5.02

05 0 377
00 0 1 i i
2. 1 3;,;

634

I)540J

634
634

1)IH\l4
1)54U5

05 0 ,317
00 0 113
24 1 316

635
635

635
635
636
6J6

w
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PAGE 19
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:rp 112
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ERRl1.3~f"Q

0'H10

05 0 3/7
00 0 1104

2. 1 376

636

ID5411
ID5412

636

'D'>413

637
6J7

aSH4

637
637

05415
05416

00; 0 ~n
00 0 116
2. 1 376

640
640
640
640

05417
05420
05421

05 0 375
00 0 070
24 1 3H

05 0 317
00 0 115
24 1 376

NUM8ER J4§116

ERRlll&j;:r'H 11) .112,l6ST09
UIR 11>

!:.1'\.i
5"11'
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116

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ERR0708l:RR 07),Q70.TESTl1
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DATI:

J/U/65.

PROJECT NU. SJ005J

PAGE 20
PR~GRAMM~~

J.~.

PHI_~IPPI

641
642
643
64 ..

'APl NUM8ER 345116

E:JE
H:ST 12

ENTER ACCUMULATOR WITH NUMBER N (2DOOO-1J
SET MOST SIQNI~ICANT 81T or H, POSITIVE JUMP
Ir STOP OCCURS
1. S-REGISTER IS JO

645

646
647

650
651

652
653
65 ..
65'S

656
6!J7
660
661

662
662
662
662

---I

[,..;,

5MB

05412

32 0 37J

JTEST128~NL

054lJ
05424
D54l'5
05426
05427
054.10

37 1 372

J

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"J"P12A

!»T .. INDEX

cNL TEMP

J

!i"S Ace

05431
D!li4J2
05433

37 1 371
J2 1 372

03 1 310
27 0 267

01 1 370C
01 1 371

20 0 u.s
24 0 024

PJP
DCR
DSf(
DCR
ZJP
J"P

20000)

2.

DESIGIUTO~

oS •

CHECK AC,UMULATOR 101 SWOULD BE NEGATIVE
I~ POSITIVE SM8 DOES NOT WORK

TEMP

ERRO.tO
TEMP
IHDEX,TEST13,J"P12A
INDEX
TEST13
J"P12A

15 J

DAr E

J I 22/65 •

PAGE 21

~~3

l::JE

66.

Ti:ST 13

i\.;!,';

'~66

;H2
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..

e75

616

.'-

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617
700
701

7D2
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"0.
705

106
707
'10
111
'12
113
11J
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113

I

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611
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MOST 51 GN I r 1 CANT BIT or rqUM8ER N. IF" pas IT J \IE STOP
HOST SiG~I"CANT ~Il V O N, paSnl~E JUMP
i i sorO., OCCURS
1. lit-REGISTER IS J1
DI:SJ(HUTOA IS l
CHECK ~:CATION " ') OU. .} SHOUL.D tJf NEGH J VE
IF" POSiT:VE 5MB DD~c, W., .. WO~Y.,
"
2. S-RfGISTEA IS 211
DESIGIUTOA IS 2
CHECK 1.0CATION 5~6J SHOULD ~E POSITIVE
If NECIA Tl ~E CMS 001:5 HOi WORK

S~

--6'
t) 70

CMB

05434
,5435
0543$
15437
"440
O§441
05442
05443
0§444
05445

J2 0 361
37 1 372
32 0 37J
J7 1 J71
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27 0 275
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05447
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TEMP

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.3 / 2o.!/65.

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530053

11nO/5~

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PH\LI.IPPI TAPE

150
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757
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76l

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765
166
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0,504
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05507
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0'517
0,520
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32 0 36"
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20
24
27
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2.5

DATE

3/20065

~

I",;: :.:./!C

·~9

PROJECT NO. IjJQ05J IJwOGR.lI1"1I:f'

~

w.

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,..

PAGE 2.
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1003

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345116

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1004

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1006
1007
1010
10::.
1012
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10:.~

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1017

1020
1121
1022

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1024
1025
1026
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10.1
1042
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J!l6
:'44

.52

24 ~ 'l"'''
"
.
0 0 ~4~
32 0 36':
10 0 3~"
20 0 !.)~

.

24 •

r

32
10
20
24
2'
32
10

;!:'4

ADO -0)

ERROR

·0

·0

·0

100

·0

-0

-0

101

-0

·0

-0

102

-0

-0

-11

1D~

·N

-~

-0

104

-N

·N

-0

105

!JP 1.·2

J"'P ERM101
"'.:P 1.-1
~N_ -D)
ADO O!

lJ" \.·2
.,iMP E~R1U2
~;:'

~-1

t:1\j~

-0)

AUD '0 :

.

D :')0

0 ,!~~
C Hi
0 l~b
1 361
0 1!>~
0 36':
0 36J
21) 0 u.s
24 1 3&0
27 0 162

RESU\."

~·2
E~loIl00

i."' 0 ~ -~.:
,
0 _..;u

~4

y

.;

:

t.;tI L.·2
J~p

"'..:'"
8tN~
ur;c

~~IHUJ

L.-l
12~2"
2;2;~)

tJ., 1.·2
J

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I:AA104

"'.:P 1.-1
6~~_

2525it:

6ADJ 1252"
J

,';10' ~·2
.;f"o ERA1U5
~..:p

1.-1

DA TE

3.'22/6';

PROJECT NO,
1047
1050
10H
:.052
1053
1054
1055

~J005J P~JGRAMM~R

~"E.

P~lLLIPPI

'APE NUM8iR 345116

eJi:
1)5565

0'·11;

Uc'!

TABLE
TEST 15" ADD
ADDER TEST

lOS6

1057
:'060

11)01
1062
1063
1064

1065
w
I

~

-.:!

1IJU

1067
107(\
1011
1072
10"73

",';0:-:

~2

O'~6"

J7 0

1).,~7(j

107-4

II ~ :;71

1075
1076
1077
1100
1101
1102

II'~

??

I)~)!J

,,'J'P.
O,5;~

11,576
1))577

un

1»)600

1104

1'~601

1105

1'~60l
1,)6U J

1106
1107
1110

1,5604
1'~605

C

:

J2 0 J~ :
1 J "'1
1 n4

37
Jl
01
10

0

·''!1SB

i) ";

J

0 214
1 3:'1
0 171

8'
INDEX

~O~

~A8"

JlJP L·2
JMP L·2

0 2U1
0 20l
3~6

r
TAB

JI'1P15C tNL T4B. 1
DCH TAB
ADD U9.1
OCR '!AB

n4

1J 1 ~l.
27 0 200
1

~NL

~lL.

1 214
01 0 214

24
20
24
01
01
21

~NL

!tTL

c~4

lJP L·2

J

J"P ERR106
UCW TAd
OCR INDEX
JlJP J"PUC

00000 • 31776 • 317"'
12525 • 12525 = 25252
00001 ·31777 • OOOih
l~2'2 • 2'252 = 12515
J7H5 • 00000 • 3717~
00002 • DOOO1 = 0000.s
P7i7 • 00002 • 00002
377'6 • 37775 • 37774
If ~TOP OCCURS
1, S-REGISTER IS 102
2, DESIGNnUR l~ 10
J. LOCATION 56~4 IS ADDAE~S A or SUM
".2 AND A.1 "!olE THE NUI'1&EkS ADDED
CHECK LISTING rOA COk~~C~ VALUES
4, Ir VALUES ARt NIG"T, ADD DOES NOr WOR~

DATE

PAGE 26

3122165.

1111
1112

~JE

Ti:ST 16

1113

E~TeR

1114
1115

c:.l

I

~

00

DESICNATOA MITM CAARY INDICATORS AND CARRY JUMP

H STOP OCCURS DESIGNATOR IS 25

1116

1.

1117
1120
1121
tU2
U23
1124
1125
1126
1127

2.

U.lO
U31

1132
1133
1114
1135
1116
l1J7
1140
1141
1142
1143
1143
1143
1143
1144

CJP

0560&
O!j607
O!j610
0,611
0561~

O!j6ll
15614

05 0 366
1 J~'
J2 0 3;4
37 1 37l
,52 0 J;.)

.25

H 1 311
0" 1 3ll

0~61~

25 0

OS6U

24 1 J,;)l

O~617

01 1 J!l

0!j620
0562'.
O;6~2

O'64!J
o.,o;t4

2:'b

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rES r 16 E:Dt1

0'
CJP EMMZ,O
nNL 77 »
~TL TEMP
J
E:NL J2,
~'L INDEl
J"P16A EDN TEMP
CJP L·2

"

.i"P

E:.Uf2~1

utA

I~DEx

lieN TEMP
lieN TEMP
II !,.( INDEx.Tisr17.J"'l.'

T...

lJP TiSll7
JMP
OCT 0

,Ift'1.'

I~

251

CMECIC INITIALll~A "54 SHOULD IE 71
CHECK COUNTEN 5753 i~OULD IE J2
CARAY IHDIClTON (liT 0' 5263
IF lilT 0 IS UN CJP OOES NOT WOAK

J
J

01 1 312

01 1 371
20 0 2;£ 4
24 o 21.J
00000

IS lSO
INIT,AL C"ECK • E~TEH DESIGNATOR WITH lENO
AND CAMAY JU"P TU ENMON 5TOP
CHECIC LOCATION ,7.6 SHOULD IE ZEAO
IF lEMO, CJP oeCUMS WITHOUT PHOP~R INDICATOR
$·AE~ISTEA

PAGE 27

1145
1141'>

H:ST 17

LSH

114-'
11511
1151
11!;2

1153
11''''
115~'

1156

11'H
1160

CI~6l5

1161

37
01'62"
01,62]
32
CI)63D ) J7
01,6J1
14

.Pl

CI~bJ'"

~.sC

1162
1163
1164
1165
11611

~1"6J~

1170

(,,6;.1.
(1)6J,

1171

(1~6J6

1167,

32 0
1
0
1
1
2~ 0
32 1
11 0
20 0
2. 1

J~l

3bl

Jll

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STI.. INDEX
81:NL 2525l)
S1L 1E"F

JHP17. LSH TE"P

3n
lll.
Jbl
2Jb
3,U

('JP J"Pl7A

tN ... TE"P
tlSUS l5252)

J

tJP ... ·2
J"P ERR140

L~rT SHirT NUMB~~ ~. N-252,2. E~D AROUND CARRY JU"P TU
LEr T SHlfT N, N.l~525. ~ESULT IS 25252
If STOP OCCURS
1. S-A~~lSTER IS 140
2. DESIGN"U~ l~ 14
J. CHECK :.t1 G4TION 5762 SHOULD BE 25252
4. CHEC~ k '263 SHOULD ~E 25252
If NOT LSH DOES NOT WOHK

:lATE

l/UIt::' ,

. ;

"'RDJECT NO, SJOO"J

M~

! :. . J •

.

..

">~Uu" l'" .~-:.f

PAGE ltt
~

1172

..

p ..'\ ••

IPPI TAPt-

NUM~EI'(

.}45116

l: Ji::

TEST 17&

1173

1174

L.S" (14'
y

1175
1176

c.,)

I
~

0

1117

0~6J7

J2 0 36.,

1200
1201
1202
1203
1204
1205
1206
1207
1210
1211
1212
1213
1214
1215
1216
1217
1220

'~640

14
20
24
27

12~1

1222
1223
1224
1225
1226
1227
1230

12.J1
12.J1
lU1
1231

0:J641
0~64l

0!>64.\
05644

0

~4l

1 341
0

J

241

0'64~

32 0 3M)
14 1 3/0

0:J646
0:J647

20 0
24 1

O~6!;O

0 2'>1
24 0 246

0~6
24 1 34.,
21 0 'l':J1

'v

0 l62

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20 1 .\4.s
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J"P t:,fHl,l
I'JP L-l
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0'666
.,'667

141

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·0

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151

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152

fRR142

4!4 o l':J4
32 o 36i

0~6'S
0'6~ft

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0='657
0,660

1I:J6!t4

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TST17y ENL 0'
8MNE 15.1.370
ZJtJ L·2
J
J"' t:I1Rl~1
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8"Nt 1!),1.370
t.JP L.·l

32 o 0$66

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~~R141

TE~T

O'6~2
0'6~.\

RESULT

I~DEl.TEST'8,JMP11A

lICH INDEl(
.l.JP TeS T 18
.IMP J"4Pl7A.

(15)

,

DATE

.1/22/65,

PROJ~C'

v:>
I
.;:...

......

NO.

12.12
12.13
12.13
12.13
1233
12.14
12.14
12J4
12.14
12J5
12.15
12.15
lU5
1216
12.)6
1236
1236
12.17
1237
12.17
1217
1240
1240
1240
1240
1241
1241
1241
1241
1242
1242
1242
1242
1243
1243
1243

rIME 11.' J! I: -.

5JBO~J

PROG~~"~E~

~,M

J _E.

PAGE 29
PHLL. .. 1PPI

TAPE: NUMYER <345116

l:Je:

3),30.TESTll
l:DH J)
l:IiP 30
..I"P TESTU
EARO~08t:MR 2).20,TSll4A
J
EDR 2)
!Ii'!P 20
J"P TST1U
EAROJ18l:NH J).Jl.l'5T14A
l:DA 3)
STP .u
J"P TUlU
EAR1208l:MA 12 ),120. TST15A
J
l:DR 12)
!»TP 120
J"P TST1~A
EAf<1218t:MR 12).121,TST15A
i:DR 12)
STP 121
J"P TST1!)A
ERR1228t;MR 12' .122. TSll5'
i:DR 12)
STP 122
.IMP TST15A
ERR1238i:RR 121.12J.TST15A
EDR 12)
STP 12.1
J"P TST15A
E~Rl.s08l:MR 13) .1.s0. TillSA
J
EDIl lJ)
STP 1.50
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ENk 1J18l:NR 1$) .lJie TST15A
t;OR loS)
STP lH
.IMP ~Sa)A
t:IHnJ28t;HR lJ).U2.TSTUA
ERkOJ08t;N~

0~670

0~671

0)672
0!i67J
0)674

05 0 J4l
00 0 030
24 o OJJ

0~675

05 0 341
00 0 04!O
24 0 O~O

0)67"
0)671
0)7011

05 0 34l
00 0 OJl
24 0 O~O

0)701
O!)702
0570J

05 0 340
00 0 14!O
24 0 1~5

0)704

05 0 340
00 0 121
24 0 1~'

0~705

05706
0)707
0)711

05 0 340
00 0 I I I
24 0 1~'

0)712
05713
OSH4

05 0 340
00 0 l:iJ
24 0 H,

OSH!>
0'716
0'717

U~

O)UO
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0~710

0 3J7
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1243

O)7U

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00 0 lJl
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1244
1244

O!l7 co .~

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1244

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0 .."'> l

J

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!t:..,

1.$2

~kUJf.CT

,..'

1244
124.,
1245
1245
1245
1246
1246
1246
1246
1247
1247
1;.!47
1247

<;jOQ'>j PRUGHA"''''E:R

}

t

•

PH l'~ L

I"'''' I :.IJf-

0571~

24 0 101'''

JM>' r :i T 1 :- •
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057C!b
0,727
0;7JO

0') 0 3J I
00 0 lJJ
24 0 1~'

E:O~

H<~l

057J1
O~73l

0,7Jj
057J4
0,7J5
O~)7Jb

0,7J7
05740
05741
0574~

05743
05744
05745
O!>746
05747
05750
0,7,1
05752
0,75J
0;754
0,7,5
0;756
0;7,7
0;760
0,761
0;762
0576"s
0'764
0;765
0:>766
0,76 7
0:>770
0,771

05 0 357
00 0 100
24 0 16'
0') j) 35 ,
00 0 lUl
24 0 165
0001J
00012

'JOOOl
DOOOJ
0604J
060;t7
0604!4
06011
06016
06040
11)000
060Jt
00040
00077
060Jo;
0601J
00010
06010
0600,
l525t

!>T~

13)
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101

J"P

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WHO
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.. HD
WHD
WHO
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low

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OA TE

l/21/65.

PAGE J1

O~71l

0526J

D'71.s
0'714
ID~ 71!>

lOOOO
05U7
DOOr: .,

.. 1010

fj';776

O~l44

1)')711

00011

"1010

""'
0
wHO
1111010

""0

DATE

l/n/6'.

TIME ll/Hltb

PROJECT NO. 530053

~

I

,j::o.
,j::o.

1250
1250
1250
1250
1251
1251
1251
1251
1252
1252
12S2
1252
1253
1253
1253
1253
1254
1254
1254
1254
1255
1255
1255
1255
1256
1256
1256
1256
1257
1257
1257
1257
1260
1160
1260
1260
1261
1261
1261
1261

PROGR'M~~~

A.

J. E •

PAGE 32

"
':>~I_L.!pol

I::RRU2ME:w~

06000
06001
06002

05 0 371
00 0 102
24 1 371>

0600J
06004
06005

05 a 377
00 0 10J
24 1 376

06006
06007
06010

05 0 377
00 0 104
24 1 376

060U
06012
060U

05 1 377
00 0 102
24 1 376

06014
06015
06016

05 0 371
00 0 106
24 1 374

06017
06020
06021

05 0 37J
00 0 141
24 1 372

06022
0602J
06024

05 0 31J
00 0 142
24 1 312

06025
06026
06027

05 0 371
00 0 151
24 0 04J

J

I::J~

'

,

1 J ) • 1" : '''''15B
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tOl
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060.53
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14) .l~:'. -"T173
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15).151,lEST18
15'
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05 0 311
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24 !) 04j

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J

ERR10~~tRR

060.10
06011
06nl2

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'51

.IMP Tt:S T17

j"~1H

DAre

3122165,

T J"f 11/31/JU

PA&E lJ

A.!'4,

PROJECT NO, 530053 PROGRAMER J,E, PHILLIPPI TAPE NU"BER 345U6
ERR2508ERH 25) • l50, TEST17

1262

1262

0lU36

12~2

OI~037

1262
1263

U040

05 0 370
00 0 250
24 1 J67

126l
1263
1263

U041
01.042
06043

05 8 37J
to 0 140
24 l' 04.1

i:OR 25)
~TP 250
J"P TEST17
ERR14081:NR 14),140.TESTlI
i:DR 14)

SfP 140

J"P TESTlI

DATE

3122165,

~ROJH.r

NJ,

T ; "~

1 t ,- , ~ .' .' ..

5JOOl).,j PR~'J;"''''''E''

': •
~.~

.......

r:

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1264
1265

f: :. r

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12~6

iHFT NUMBeR N. Na25252, (3252~' L.ErT iHlrT
1.:.<'!53), LOGICAL AND WITW 37176 (252Sln, SU8TIUCT

1267
1270

~lu"'T

1271

P

1,

~·WE(iISTEA

1273

i,.

I)ESll;'UTO~

1274
1275
1276

,-

1300
1301
1302
130l
1304
1305
U06
1307
1310
UU
1312
I
~

en

OCCURS

1272

1277

c,.)

~r(J~

1313

1314
1315
1315
1315
1315

06044
06045
06046
06047
0&050
060~H

06052
06053
060S4
0&055
060)6
06057
06060
06061
0&062

32 0 366
37 1 36?

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32
37
16
14
32
12

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J

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..

1~OEX4

164

/

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0 3C1J
1 362

J
J

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I~OEJlt:!
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1

1 36l
1 36l

0 361

11 0 36J

20 0 0,7
24 0 2'"

01 1 365
20 0 062
24 0 050

J

TEMP
TEMP
I.~H TE"P
i:NL. TE"P
BAND 37716)
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JHP184

1 362

IS 160
IS 16
J, CHECK L.OCATlu~ 6J6J SHOUL.D -E 2!J252
4. CH~CK LOCAl ION 6J61
SHOUI.D BE 3777t>
CHECI' L.OCAl ION )416,) ~HOULO liE 2525J
ACCU~ULATOR SHOULD ~E UNO
6- RSH DOES NOT WUAK

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8~U8

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tJP
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L·2
ERRlbO

[lSI(

INOE~A,JMP188,JMP18A

DCR JNOEXA
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N

PAGE

1.116

C.:I
I

~

...;J

1317
1320
1321
1322
1323
132C
1325
1.326
13417
1.130
1.531
13J2
1.3.13
lJ.J4
1335
1.136
1&.11

E: JE
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HlliHT SHIrt N.

IF" STOP
1:

.
3l 0 300
;p. 1 36~
16 1 30l
14 1 ;S~£
32 1 .io~
13 0 J':JI
11 0 3t:O
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,

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161

l.OCA·ION bJ6U
oS, l:HE:CK :..OCl'rlON C).s~7
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lCCU"UL.ATON ~HOULD ~~
HS~ DOES NO'! WORK
2.

ObObl
06064
OtJ065
U066
06007
OU70
Ib011
OU72
0607J

N&1252';

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,.

CHt;::I'.

SHOULD BE: 12525
SwOULD 8E 1
SHOULD Wi:: 1252iEQO

3~

DATE

3/U/65.

T U4E I1/H/J7

PROJECT NO, 5J095J ?H0GRAMHtk

J. f .

1340
1341
1342
134J

1355

c;.,
I

II'>-

6

1
0
0
C 0
24 0
32 0
16 1
20 0
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27 U
24 0
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'=~~l~l

J

... ..,~ l·2

HI
0,'6

Jt1D

~~2

.3., ;'

~NL

1)

J.,6

k:'1'1

lU-:

L .;P l·,
JHf' t:KR1oJ
".;P L·2

llf?

101

104
3'),
3"0
11J
2»).
ill
361
3)0
120
2')-;

27 0 117

JI'W
J

Ace

L'2

I:Nl -Ill
k~H

Ace

l.';P L·2
JI1P E~IU64

I'JP l-1
tNl -1)
ICSH ACC

t.JP l·2
J"P E~Rlb')
J'JP L-1

DATE

3/2U6~;.

PROJ6CT NO.

w
I

~

co

1373
1374
1375
1376
1377
1400
1401
1402
1413
1404
1415
1406
1417
1410
1411
1412
1413
1414
1415
1416
1417
1420
1421
1422
1423
1424
1425
1426
1426
1416
1426

TIME 11/J1/40

~3005J

A.M.

PAfii 17

PROGRAMMER J.E. PHIL.L.lPPI TAPE NUMBER 145116
f:JE

TeST laa

RSN (17)
y

Gi6t22

32 o 375

G~123

17756
o 12~
o 260
o 121
o 124
o 3~7
17756
o 13J
o 263

.,6124
GI6125
.,6126
GI6127
.,6131
16131
nU2
06133
06lS4
06135
06136
06137
16140
'6141
06142
86143
06144
16145
16146
16147

20
24
27 o 135
24 o 132
32 o 355
17756
20 o 141
24 o 266
27 o 140
32 o 361
17756
20 o 146
24 o 211
27 o 145

16150
16151
16152

11 1 364
20 0 U2
24 0 064

20
24
27
24
32

TSHSa ENL
8"NE
ZJP
J"P
"JP
J"P
f:NL
a"NE
lJP
J"P
"JP
J"P
ENL
8"NE
lJP
","P
JlJP
f:NL

ERROR

0)
17,1,J5t
L.Z
ERR171
L.2
L-2
I'
17,lt356
L.Z
EAR172
L.Z
L-Z
-0)
17,1,356
L.2
ERR11J
L-1

·0

·0

171

+1

+,

172

-0

-,

113

-1)

-1

-I

174

'"NE 17,I.J56
lJP
J"P
PoJp
OSK
OCR
ZJP
J"P

RESULT

L.Z
ERR174
L-l

INDEX8,TEST1',~"'I'C

INDEIS

TiSTl9

J"PlIC

DATE

PAGE 31t

J12U65.

142:14.l0
1431

~

.IE

TE:ST 19

fN'!l:ioI D~~i~N.TOR WJT~ EYEN
H· ~ H:i-> OCCURS DESIGNATOR

1432
14JJ

1 . S-REGISTER IS 210
; f. ; ,. i A... CH E: CK - ENTE~ DESIGNATOR WITH lEWO

1436
1"37
1440
1441

AND EYEN JUMP TO ERROR STOP
rHECK ~OCATION 6375 SHOU~D BE ZERO
! r Zl:"O. EJP OCCURS wITHOUT PROPER INDICATOR
2, S-REGISTE~ IS 211
CPO!!!:" 1H IT lAL.lZER 6J~2 SHOULD BE J7
CHECK COUNTER 6354
IS U
HEN INO I CATOR (BIT 4) 5263
I f 91T 4 ON EJP DOES NOT WORK

1--42

1443
1444
1445
144#\
lU7

~~

0

INDICATORS AND EYEN JUMP
IS ~1

143.

l·n.,

,

fJP

1450
1451
·1452
1453
1454
1455
1456
1457
1460
1460
1460
1460

0615J
06154
061S5
06156
06157
06160
06161
06162
OU6.}
06164
06165
06166
16167

TESTi9

05 0 3/"

21 0 3D:.?
32
37
32
37
05

U 3>4
1 3"J

./

3,L'

J

0
1
1
21 0
24 0
01 1

362
362
1(),s

30;
362

01 1 35J
20 0 161
24 0 160

J

l:DH D)

l:JP
f;NL
STL
Bl:HL

ERR210
16'

IIItDEX

37)

TEMP
TEMP
L·2
ERR211
TEMP
INDEx.1ST19A.JMPI9A
OCR INDEX
lJP TST19A
J"P JMPIVA
~TL.

JMP19A I:DR
l:JP
J"P
OCH
USK

>ROJECT NO, 5J0053

PROG9A~~ER

J~.

1461
1462
146J

PHl~lIP?I

TAPE NUMBER 345116

t: JE

aST 194 OJP

1464
1465
1466
1467
1470

1471
1472
1473
1474
1475
1476
1417
1500
1501
1502
1503
1504
1'05
1!J06
1507
1510

016170
01&171
016112
D&173
0 6174

or;

'!S'"'19A EOR 0)
UJP E~R2C10

0 375

26 0 310
.12 0 J 17
37 1 lb4

06204
0620S

27 0 111

PJP J"PlVC

06206

32 1 36l

1'21

06211
D6211

11
37
II
27

tNL TeMP
~UIt 2)

1521

D6237
D6?1O

062U

24 1

06176
06177

0&200

1511

06201

1512

06202

UU

1'14
1515

1'16
1517

1522
1523

06203

J,l
36l
3H
36,
J6l

(1)

:'-l II\IOEX~
8tNL 31)

0
1
0
1
1
26 0
24 0
11 1
11 1

1

06175

.12
37
.12
J7
05

~Ni.

20l
313
l6l

J!)'

SiL

J";I1P19B fNL.
!t ~ l
":MP19C E!>A
UJP
J"P
DCR
UCR

0 3'1
1 362
1 l6.
0 17~
J~O

~-;L

~E"P

2)
iNDEU
TEMP
L..2
EAR261

"'E"P
iNDEXA

T&"P

OCR ltlDEXIt
PJP .".PIVIt
J

J"'

TES~lO

ENTER DESIGNATOR WITW OVER~lOW INDICATOR AND OJP
if STOP OCCURS DESIGNATOR IS 26
1. S·RE~:STt~ IS l60
INI""lL CHECK - EN·E~ DESIGNATOR WITH ZEAO
AND UVER~LOW JU"~ TO ERROR 5'OP
CHECK L.OCATiON 6J75 SHOULD HE ZEAO
If lERO, OJP OCCUMS WITHO~T PROPER INDICATOR
2. S~ijE&ISTEW IS 261
CHeCK INIT.ALIZEA 6J~2 ~NOULD BE 37
CHE~K COUN·fHS
6J17 IS e
6351 IS 2
OVE~rLO~ I~OICATO~
'.11 1) 5263
If 81 T 1 ON OJP DOES NOT WORK

DATE

1122161).

t: ':l

1524
lS25

T~ST

1526

CHECK

1527

1543

w

,n
I

l\:)

IS

SETTINQS BY

LE~T

SHlf? ALTEPN,TE

~ET

HOT iH
NOT SET
If CARRY THEN ALSO pos 1 Tin SfT OR NOT SE"
Ir STOP OCCUAS
CHECK ~OC,TION 6363 SHOUL-V tiE 252 .. i
~nN
Z~RO

1531

15U
1545
1'46
1547
1550
1551
1552
1553
1'53
1553
1'53

D~SJGN,TOR

OnMrLOw

1530
153?
1533
1534
1'53'5
1536
1537
1540
1541
1'42

24

0621<4
06n5
0.21&
0621:'
06220
0&221
06222
062lJ
0624t4
06225
06U6
06227
062JO
06231
06232
U23J

T'ES;248t:H~

32 0 J6"
37 1 :, '> .~
36 1

;3 i.'

32 0 J6J
14 1 ~"6
20 0 i..: .. "

24 0

Jli

21 0 3tl
20 0 316
25 0 Ub

24 0 2.s0
21 0 2.s0
24 0 324
01 1 .J5J

20 0 2,u
24 0 211

S~L

J

lOOOO)

INDEl
RJP DSl&CK
IENI. 2S2!)l'
J"P24A LSM Ace
UJP 1.·2
J"P ERf'14J
I:JP ENR1.4
lJP ERR145
tJP L.2
J"P L.J
t'JP ... 2
J"P EARl46
DSK INDE •• TE5T2~,J"P24A
OCR INDEX
I.JP TEST;t5
J"P J"P2U

ONE>

PAGE 41
PROJECT NO. SJ005J
1554
1555
1'55.
1557
1560
1561
1562
1'5'3
1564
1'5'5
1'"
1'5.7
1570
1571
15'72
1'73
w
I

01
W

PROG~'"MER

J.E. PHILLIPPI TAPE NUMBER J4511.
t:JE
H:~T

S~~

H

062.14
06235
0&2.16
0&U7
06240
06241
06242
06243
06244

32 0 346
37 t 3~.s
22 0 2.57
24
23
24
01

JTES~25

JMP2'j&

0 Hl

S~l

INDEX

~LJ

L·2

J"t'

0 241
0 3J)

1 3),s

27 0 2J)
24 1 345

Ull oS)

.lEND

ClJ
JMP
DCR
t'JP
J"P

EMR2~1

L·2
ERA2J1
I~DEX

JMP2)A
TEST08

25

CLJ-SLJ

LOCKOUT AND JUMP, CLEAN LOCKOUT AND JUMP
OCCURS JUMPS DID NOT OCCUR
1, S-kEG!STER IS ~21
~LJ ODeS NOT WORK
2. S-R~GISTEM IS 2Jl
CLJ DOES NOT WORK

~TOP

lATE

J/2U6':>

P~U~~AMM~~

1574
1515
1515
1,75
1515
1516
1516
1576

00245
00246
00247

05 0 344
00 u tel
24 0 l~~

002:;0
0(2)1

l.S}6

062~2

0:> 0 344
00 0 16J
24 0 152

1577
1517
1577

062,4

1577
1600
1600
1600
1600
1601
1611
1601
1601
1612
1602
1602
1602
1603
1603
1603
1603
1614
160"
1604
1604
1605
1605
1605
1605
1606
1606
1606

PAGE 42

A .....
j

,I::: •

PHILLI~PI

l:Jt
i:Hk1628l:jo(R

Ob2~3

06255

0" 0 344
00 0 164
24 0 l~l

06260

05 0 344
00 0 16';
24 0 1:>~

06261
06262
06263

05 0 343
00 0 1/1
24 0 1,l

06264
06265
06266

05 0 343
00 0 172
24 0 1,l

06267
0&270
06271

05 0 J4~
00 0 17J
24 0 152

06272
0627.J
06274

05 0 343
00 0 114
24 0 152

Ob275
Ob277

0'> 0 344
00 0 IbO
24 0 l~l

06300
063U1

05 0 344
00 0 161

06256
06257

06276

J

TAPE II/uMBEjo( J45116

16),162.TE~T'19

l:UR 16 )

STP
JMP
ERlo(l63'Jl:HR
l:DR
STP
JMP
ERln648l:HR
t:DR
STP
J"P
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EDR
~TP

J"P
ERR 1718t:HR
t:DR
J
STP
J"P
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I:DR
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J"P
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l:DR
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J"P
ERR1148l:HR
i:OR
STP
J"P
ERR1608t:RR
EDR
STP
J"P
ERR1618ERR
EDR
STP

162
TEST19
16L16J,TE~T19

16 )

163
TEST19
1O),164.TEST19
16)
164
TEST19
16).165.TEST19
16)

16,
TEST19
17).171,iEST19
17)
171
TEST19
11),172,TESTl9
11)
172
TEST19
17).17J,TEST19
17)
173
TEST19
17) .17 4. TEST i9
17>
174
TESi19
16).160.TEST19
16 )
160
TEST19
16).161,TEST19
16)
161

DHE

l/2U65,

P~OJEC~

TIME ll/J2IOO

1606

04~302

24 0

1~2

CJl
CJl

1611
1.11
1611
1612
1612
1612
1612
1613
161l
1613
1613
1614
1·14
1614
1614
1615
1615
1615
1615

J"P TEST19
EAH2108i:HR

04UOJ
04~304
04~305

'4~306
14~307

'4~311

15 0 342
10 0 210
24 0 1&7
15 0 342
10 0 211
24 0 161

1·11

I

PAGE 43

NO. 5.S00'jJ PROGIU""ER J.E. PHILLIPPI "4PE ItUHBER 345116

1607
1607
1&07
1607
1610
1&10
1610
1610

w

A.I'I.

14~311

'4~312
14~313

15 0 341
10 0 260
24 1 350

'4~316

15 0 341
10 0 261
24 1 350

04U17
14U20
14U21

15 0 37l
I I 0 14~
24 I 213

'4~314
04~315

11.322
'IU2l
IIU24

15 0 31.1
10 0 144
24 0 2.n

0lU25
Olbl26
OlUi7

15 0 37,s
10 0 146
24 0 2.13

1616

OIU~O

1616

Ilbl,sl
'IU,sl

15 0 37.1
10 0 14.1
24
23.1

./

1617
1617

OIr.,s,sJ
OlbJ,s ..

1617
1620

Ol'.s,s~

15
340
00 0 221
24 0 24.1

.,Ia,s;Jt:

2·

O,blJ1

o

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J"P

TEST~O

Jftp

TEST~5

EAR2611ERR 26),~61.TEST20
EDR 26)
STP 261
.IMP TESTitO
ERR1451ERR 14),145,T&5T25
EDR 14)
SIp 145
EAA1441i:AR 14',144,T&ST25
t:DR 14)
51P 144
J"P TiST;t5
ERR1468EHA 14),146.TE5T25
EDA 14,
STp 146
.IMP TESTit5
EMR1438E~R

•
•

21).~10,TST19A

SfP 210
J"P TSl'19A
~AR2118I::HR 211 ,211. T5T19.
EDA 211
Sfp 211
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ERA2608EAR 26).260.TI:ST20
t:DR 4!6)
J
Sfp 260

1616

1616
1617

E:DR

14).14J.1~ST25

I:DR 14)
STp 143

JMP
ERRll18ENR
J

TEST2~

22.r4!21.~ND

I::IJR l i t
57p 221

.I"P END
E:Ak2318E:WR ~l).4!Jl,END

371

!tKP

OOO:t.s

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3/22165

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06,561
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5~!OU?.)

PQ 0{,Io i11E~

1620
1620
1620
1621
1621

Ot;400
oe,401
Ot'4U2

05 0 ,:\ ,,
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05 0 3·;

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1611

!Jb4U4

00 0

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1621
16il2
1622
1622
1622

O~... O~

24 0

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1623
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164!3
16114
1624
1624
1624
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01,413

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05 0 314
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04~421

1626
1626

01~4ll

1626
1626
1627

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Ol!l4l4

1627

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345116

45

DATE

J/U/6S

~ Po!h

:»ROJECi NO, r;3005j
1632
1632
1632
1633
1633
1633
16J3
1634
1634
163'
163"
1635
1'30;
1635
1'35
1636
16J6

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05 a 371
00 U at4
24 1 J7J

Db .....
06 .... 5
06446

16J6

1643
1b44

'11

ERPU2~8t:~R

1636
1637
1637
1637
1637
1640
1640
1640
1640
1641
1641
1641
1641
1642
1642
1(.42
1642
1643
1"3
164~

~:/~.

ll).J~3.T~ST~4

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46

JATE

3122165.

Tl"E llnV16

... M_

'>ROJECT NO, 5J005,5 PROGlhP1MEH J E
lU4
1644
1644
1645
1645
1645
1645
1646
164"
1646

w

1646
1647
1647
1647
1647
1650

01

1l~50

I

co

1650
1650
1651
1651
16S1
1651
1652
1652
1652
1652

1653
1653
1653
1653
1654
1654

1654
1654

06414
06476

05 0 367
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24 1 3H

06477
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06501

05 0 367
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tON lJ)
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345116

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NO,

T

~jOU~j

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11/

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CMECK

1666
1667
1670

06534

1671
1672

06535
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13 0 360
37 1 3~1

20)
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375

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204
364
36J
362
361

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J
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J
J
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1673

1702
c,.,
I
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0

1703
1704
1705
1706
1707
1710
1711
1712
1713
1714
1715
1716
1716
1716
1716

DESIGNATO~

I~STRUCTION

Jl 0
31 0
32 0
31 1
32 0
37 1

1674
1675
1676
1677
1700
1701

NUM&E" 345116

TE:ST 20

06540
065.sa
065.st
065.sl
065.s.J

166~

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t JE

1655

16>6
16S7
1660
1661
1662
1663
1664

PA;';~

.,1'1

'-I

06537
06540
06541
06542
0654.5
06544
06545
OCl54~

06547
065~O

065St
065!;l
065SJ
065'4
06555
065,6
06~,7

06561)

36 0 200;
32 1 361
J6 0 216
11 1
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11 1 3,7
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36 0 24'
01 1 361
36 0 J01
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36 0 3~O

J.,"

01 1 363
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JMP20A HJP DSIGCt<
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WJP J20UA
SUB TEMP"
HJP J20UB
SU8 TEMPY
HJP J2024!C
HJP J20UD
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RJP

"

DSIGCK CLEARS THE DESIGNATOR AND CHECKS THe JUMPS
TEMPA ALWAYS POSITIVE 1" 1J-5~'3
TEMPB ALWAYS NEGATIVE - COMPUMEN~ or TEMPA
TEMFA • TEMPB • POSIT J VE
TEHP~ • NEGATIVE'

J202~E

ENL "EMP,
etOR 377711
HJP J202lF'
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J"P J"P2UA

.-

48

DATE

3/22/65,

Tl f4E 111 3U;? 3

PROJECT NO, 530053

P~Ub~~"MEW

A.M,
J

1117

t:

PAGE

PHl!..l:HI TAPE NUM8ER l45116
l:JE

1720
1721
1722

T~ST

CHECK DESIGNATOR SETTINGS ArT~R ilECUTION or ~ACW
IhS!RUCTIUN IN THE SEQU~NC~ rOLLowlNG JMP22A
R~TU~N JUMP TO TH~ CW~CK HOUTINES

1123

1724
1725
1726
1727
11.s0
17.s1
1732

C..:I
I

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17.13
1734
1135
1736
1737
1740
1741
1742
1743
1144
1745
1746
1741
1150
1750
1750
1750

06561

32

0656~

204
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06567
06570
06511
06572
06,5H
06>574
06>575
O«!,516
DfI,517
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36 0 205
32 1 354
36 0 216
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JMPl2A kJP OSlGCK
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01 1 36.S
20 1 3!;j
24 0 166

UCR INDEX
lJP TEST~3
.IMP JMP 2 ileA

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DSIGCK CLEARS THE DESIGNATOR AND CHECKS THE JUMPS
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7777·,"-!)J
TEMP • TEMP. POSl·'YE • • TEMP. NEGATIVE'

I~CEX.TE:ST~3.JMP22A

4~

DATE

3/22165.

TIME

PROJECT NO. 5J005J
1751
1752
1753
1754
1755
17~6

17S7
1760
1761
1762
1763
1764

11/Jl:2b

A

J.E

PRUG~A~~fR

PAGE 50

1'1

PHILL!PPI IAPE NU"SEH 345116

TEST

t: JE
OCT

06604

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06605

00000
o 21.,
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DSIGCK , : '.
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27 1 3.,0
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24 1 20';.
OOOUO

Io'JP EttA210
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26
20

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J
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rOLlOWING ARE SUBROuTINES rOR TESTS 20. 22
Ehl POSITIYE NUMBEH

1765

c",

I
0)
~

1766
1767
1770
1771
1772
1773
1774
1775
1176
1777
aooo
2001
2002
2003
Z004
2005
Z006
Z007
2010
201:'
2012
2013
2014
2015
2016
2017
20C!0

0(611)
06617
06610
0661lt
0661ll
0662.5
Ob6l4

06625
066ll)

06627
066JO
066.5t
066.52
066.5·'
066.54
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066..s~

OU,57

06640
06641
00642
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00644
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CLEARS rHE DESIGNATOR AND CHECKS THE JUMPS

00000

26
20
25
27
24
24

o
o
o

J202lA

':

.

~

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OJP EilRJi&!1
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tJP l:tlRJ4!.J
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013

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26 1 346
20 1 34.,
25 o 0~4
27 o 2.sl
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21 o 2J4
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26 o 240
24 1 34S
V a 00i!:
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l5 0

OJP
iJP
(:JP
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I:JP
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RESULT

POSIT lYE

ADD/SUa.

flOS/NEG •

RESULT

NiGAT J YE

EIIA3UO
ERA301
ERR30l
L·2
t:RR30J
L·Z
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J20~2C

OJP L·Z
J"P EMRl07
t-JP EI1A110
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t.:I
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2021
2023

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ut

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014 0 OJ'>

2014

06651
066,l
066,.S
066,4
066,5

27 0 2'> ~
20 0 040
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12 0 34J

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;';6

2025
2026
2027
2030
aOJ1
2032
2033
2U4
2035
2036
2037
2040
2041
aO / 2
2043
2044
2045
2046
2047
2050
2051
2052
2053
2054
2155
2056
2057
2060
2161

2062
2063
2064

2065

06657
06660
06661
0666l
06665
06664
06665
06666
0&667
06670
06671

oun

0667J
06614
0667.,
0667#1
06671
0670(1
067Ul
067Ut
O&lUoS
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067Uo;
06706
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PAGE 51

JP1P
t.JP

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CJP
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2072
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2074
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2100
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2102
2103
2104
2105
2105

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PAGE '52

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067050
067.51
067J1
067Jo5
06734
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Ob7J6
067057
00740
0674106742
067405
06744
06745
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06747
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26
24
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MHO
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MHO
wHD
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.. HD
"HO

!lATE

3/2V65.

TIME 11/3i13y

J..'"

PAGE 53

PROJECT NO, 530053 PROGRAI'1"'ER J,E, PHILLIPPI TAPE NUMBER 345116
06762
0676J
06764
06765
'D6766
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2120
2120
2120
2121
2121
2121
2121
2122
2122
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2122
2123
2123
2123
2123
2124
2124
2124
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2125
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2126
2126
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PAGE 55

PHILLIPPI tAPE

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NO, 5.50053 P"U(j'iAM"Iti<'

2131
2131
2132
2132
2132
2132
2133
2133
2133
2133
213"
2134
213c
213"
2135
2135
2135
2135
11J6
2136
2136
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21.57
2137
2137
2137
2140
2140
2140
2140
2141
2141
2141
2141
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2142
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lJ),j63.T~ST24

I:D" 13 )

STP
..iMP
ERRJ628i: .... R
1:0R
STP
JI'1P
ERR1'3at:HH
J
EUH
STP
JI1P
ERR1548E:HR
EOR
5Tp
JI'1P
ERR155al:kR
E:DR
STP
JI1P
ERR156at:HR
I:O~

f,TP
JMP
EIHI157at:HR
t:UR
STP
JI1P
ERRJ5,at:RR
J
E:DR
STP
J"P

J63
TESTe 4
13),.562,TEST24
1$)

362
TE5T24
16).153,TEST24
16)
153
TESTe4
16),154,TEST24
16)
15"
TESTe4
16).155,TEST24
16)
155
TESTjl4
16),156.TEST24
16 )

156
TESTe"
16).157,TI:5T24
16)
15~

-

TESTe"
12),.555.TI:5T24
12 )
.5'5
TES Te4
~:J~.5'68t:H" 12),J56,TEST24
EOR 12 )
STP .5'6
JI1P TES?~4
ERR.s7.58t:RI-( 37> J73,rEST2"
I:OR J1)

~6

li"TE

3/2U6~

FicOJE~

; NJ. 5.:; :10" ~ P"')G~A"'''~R J ,E. j)"llLJ I"P Z fAPt: NU"ti':N
34~116

214]
l!41
4tU·
2144
jt144
it144
it.. 4'
U4S
2145
214~

.

c,.:)

I

CD
CO

":Me

p';e 57

o '~1J·.

..

E~ICJ748t:NM

Ol'J4

~/)

015 0 3&t

t lJit

J7)

!P1J';
O)'lJI)

01 0 "s' ..

~!~

l4 1

.114

Oll.tl

0/1 J7

oltC"

!trp 313
","P !':STjt4

0 J'lJ

l4 1 3H

.,
00

J."

0 3&1

" 37;

ol141

24 1 j64

Oi'14l

15 0 361

it146
2146

• i"t: !41JU'>J

U46

O;'i.4~

it14.

DO

Ol144

24 1

0 3H
';64

.I""

• .s14. H:S'24

TEsr,,4

Etf'U:'58e:tCi( J1) t.t75.1EST24
t !)tt ..s1)
~T;J

c~~,)

J7S

"PIP T!::STl4
76:H:tCif

37).,,76.1':5T24

tON ,,1)
!.TP 376
J"P TESTl4

ATE

3/22/65,

~aJECT

NO, 530053

2147
2150
2151
2152
2153
2154
2155
2156
2151
2160
2161
2162
2163
2164
2165
2166
2167
2170
2171
2172
c,.:)

I
-J

0

TIME 11/Jt/5'J

2173
2174
2175
2176
2177
2200
2201
2202
2203
2204
2205
2206
2207
2210
2210
2210
2210

A,r1

J.E,

PROGR."'~ER

PAGE 58
PH [L'-.!IJP[

rAPE

NUM~E~

j45116

tJE
leST <.'1
CHEC~

OESIGN.TO~

IN
RcTUkN JUMP TO
INST~UCTION

071"5
01146
07147
07150
07151
07152
C11~J

07154

32 0 3'J S
j7

1

3.,..,

32 0 3.,1
37 1 3"0
32 0 347
J7 1 346
13 0 345
.P 1 344

SETTINu5

EXECUTION or EAC~
JMP21A
ROUTINES
.rl~R

T~E

SEUU~NCE

T~E

C~ECK

~OLLOWING

.JTESTl18ENL 211
~TL TEST
J
J
8ENL 252<4)
J
STL INDEX
8E:NL 32524)
.J
~TL TEMPA
J
J
8EOR 37777>
J

~TL

TEMP~

DSIGCK CLEARS THE DESIGNATOR AND CHECKS THE JUMPS
TEM~A ALWAYS NEGATIVE
J2524 • JOOOO
TEMPA ALWAYS POSITIVE - COMP~EMENT TEMPA
TE"~A - TEMPS s NEGATIVE. - TiMPS • POSITIVE'
07155
07156
07157

36 1 343

07160

11 1 344
36 0 2JO
11 1 344

07161
0716l
07163
07164
07165
07166
07167

36 0 222

0 241

07110

36
36
01
36
32
13

07171
07172
0717J

37 1 344
36 0 317

0717 ..
07175
07176

J

32 1 346

0

2~2

1 346

0 302
1 346

0 345
36 0 311

01 1

3~O

20 1 342
2<4 0 154

J

JM"21A RJP OSIG(';K
ENL TEMP.
NJP J213AA
~ue TEMPtI
t(JP J21J1:i8
SUB TEMPtJ
kJP J213CC
NJP J213DD
OCR TEMPA
HJP J213EE
ENL TEMPA
8EOH 31777 )
HJP J213H
~TL

TEMP~

NJ ..
DSK
OCR
UP
..IMP

J21JGG
1"DEX.TEST22.JMP21A
'"DEX
TEST22
JMP2U

DATE

312£/65,

·IHE llIJV59

A,H,

PAGE !i9

PROJECT NO, 530053 PROGRAHMEH J.E. PHILLIPPI TAPE NUMBEH 345116

c.:l
I
-;J

......

2211
2212
2213
221"
2215
2216
2217
2220
2221
2222
2223
222"
2225
2226
2227
2230
2231
2232
2233
223 ..
2235
2236
2237
2240
2241
2242
2242
2242
2242

EJE
TES T 23

07177
07200
07201
07202
07203
07204

32
37
32
37
32
37

0 341
1

3~l

0 3~1
1 3!>0
0 3H
1 340

JTEST238ENl 23,
STl TeST
8ENl 2524'
~Tl INDEX
8ENl 32524)
J
STl TE"P

CHECK DESIGNATOR SiTTINGS ArTER EXECUTION Dr EACH
IhSTRUCTION IN THE SEQU~NCE rOLlOWINg J"PUA
RETURN JUMP TO THE CHECK ROUTINES

DSJGCK CLEARS THE DESIGNATOR AND CH&CKi THi JUMPS

07205
07206
07207
07210
07211
07212
07213
0721"
07215
07216

36 1 3043
32 1 340
36 0 n2
10 1 340
36 0 230
10 1 340
36 0 241
36 0 252
01 1 340
36 0 302

07217
07220
07221

01 1 350
20 1 364
24 0 20"

TEMP ALWAYS NEGATIVE J2§24 - JII.O
T~"P • TEMP. NEGATIVE • • TE"P • POilTIVE •

J"P2JA RJP DSIGCK
ENL TEMP
RJP J2llU
AOD TEMP
RJP J21398
AOD TEMP
AJP J21JCC
HJP J2UDD
DCA TEMP
RJP J21JEE
DSK INDEX.TEST24,JMP2JA
OCR INDEX
ZJP TEST24
J"P JMPiJA

urE

3/7<:'/65.

~.o.JEC

r

NO.

T I P1 E Il/JJ/OI

5J005J

PRCuRAMME~

PAGE 60

t.. I"
~

E:

p~:~~:pp:

TAPE NUI'I8Ek 345116

tJt:

22'3
2244

FULLO"dNG ARE SIJBROUTI~ES
ENL NEGATIVE.

n45
22<1-6

2247
2250
2251
2252
ZZ53
zn4
2255
2256
~7

2Z6D
2261
2262
2'Z~J

2264
2M~

CI.:)

I
..:J

~

2'266
U.7
ZZ7Ct
2271
2212
221.3

2274
UIS

2276
2271
2~0

2311
23'2
2 • .3
2~U4

2l0S
2.116
2307
2310
23t1
2312

07222
072O!!3
07224
01225

o7n6
072V

07230
072;51
072.52
0723.3
072J4
07235
07236
07237
07240
07241
07242
07243
07244
07245
07246
07247
07250
07251
07252
07253
07254

o125 Ii

07256
07257
07260
07261
07262
01263
07264

00000
26
25
20
27
24

0 OJ4
0 OJ:'
1 2U

26
27
25
24
20
21
24
24

00000
o 050
o 067
o 234
o 064
o 0~6
o 2J7
o on
1 230

26
24
27

24
20
25
24
24
OJ
26
l4
27
20
;t5

12
26
24
27

:;JP

1 3J7

o

255

1
o
o
a
o
o
1
o

3J6
007
001
004
335
263
334
122

t:~R3j4

(';JIoI E~R3J'
UP EHRlJ6
!-JP E~RJJ7

OJ!

00000
o 243
o 042
a 24~
o 04S
o O~J
o 250
o 061
1 241
00000

TESTS 21. 2.3

...;2134A

0 O;{tI

a

FO~

k

9

1\1
ADD/SU~

NEG/POS •

RESULT NEGA r : VE

ADD/SU8

NEG/POS ,

RESULT POSITIVE

J21JBR
OJP ERIUOO
ERAJ05
CJP L·2
J"p E.. AJ06
lJP EHRJOl
~JP L·2
J"P ~ARJ04
WTN
~JP

J213CC " ,
OJP
JI'IP
I-'JP
JI'IP
lJP
CJP
JMP
WTN
J21JDD
5MB
J
OJP
.,IMP
J

1.·2
EAA307
1.·2
ERR31J
ERR3.11
L·2
EARl14

I. , Ace

~JP

J

J

lJP
CJP
BAND
OJP
.IMP
PJP

l·2
I:AROJJ
Ii:~ROJ6

ERAOH
~RROJ5

37774,
1.·2
ERAJ50
I:~RJ55

ilATE

3/22161j ,

'l~E

11.'JJlOb

PROJECT NO, 5,s0053 PROGR;'H'1ER J,E
2313
2314
2315
2316
2317
2320
2321
2322
2323
232"
2325

c,.,
I
~

c,.,

2326
23U
2330
2331
2332
2333
2334
2335
2336
2337
2340
2341
2342
2343
2344
234,
2346
2347
2351
2351
2352
2153
2154
23"
2356
235'

07265

07266
01267
OlVO

07211
07272
0727,5
07274
07215
D7276
07217

07300
07301

24 1 252
26
20
25
24

00000
o 010;
1 330
o J06
1 3~7

27

Ole

o

24 1 JOl

07311
01312
07313
01314
0731!i
07316

26
27
24
20
24 1 Ul

07317
17310
17321
.7322
17323
17324
17325

0000f)
o 020
o 1056
o 133
o n4
o Oll
1 317

07326
.7327
073JO

00000
o 100
o 314
o 07~
1 J~6

26
25
20
27
24
24

oJ

HS~

PJP
CJP
OJP
J"P
f:JP
tJP

0 111

0 117
05 1 331

06510
06501
06504

NUI'1~ER

345116

ZJP ERA35l
CJP ~·2
Jl1p t:RRJ51
EJP ERRl;6

0 ?7S
0 114

26
24
21
20

07302
o 7.S0 3
07304
01305
07306
073117
07310

PHII.L1PPt TAPE

20

1 3J3
2<; 0 20!
24 1 JJ2
21 0 1l'>
16 1 331
'i.7 0 10~
25 0 10J

,.,£

A ,1'1,

"

~I)R

;

"
J213GG

EHR1~J

L·2

ERRIS6
~RA155

EARl)7
ZERO

kTH

J21JEE ,
UJP
lJP
J
CJP
J
J"P
PJP
NTH
J2UH

4ee

ERRlS.

DCA HEGAT I ¥E •

~

ERR012
ERROl4
L·l
ERROl"
ERROll
COMPLEMENT

HE&A'IY~

•••
OJP ERAJ62
.,JP L+2
J"P ERR36l
lJP ERR361
NTH
t

" ,

OJP ERA312
CJP ERRn5
lJP EAA314
PJP L·2
J"P t:AAl11
ICTH
&I:H
WHD
WHD
WHO

sn.

POSITIVE'

•

61

UTe

:,nU61j ,

"'CT NO,

~

I

..;J

"""

T1"E 111 JJ/l 0

~,)OO53

073.11
0133l
07333
07334
01335
073;56
01337
01340
07341
07342
0134J
11344
01345
01346
,7147
07151
07351
,7352
,735.1
.7354
"355
17356
01357
11360
17161
,7362
.7363
'71'4

PROGRA""ER

'AGE 62

A.".
..! ~ i: •

PH1"'L..I?folj

0661'>
064,>7

WHO

064~4

WHO

064S1
J7114
06n6
00101

.. NU
WHO

O!ll2c.J

DDDlJ
06!160
0660'>
'~2c.5

31711
15264
325:i4

05266
125:i4
16614
1":i1
10012
11016

ooou

10110
101.t2
IOU7
11001
01003
1621.t

.. HD
WHO

wHD

wHO
wRO
wRO
MHU
MNO
MNO
MNO
MRO
MHO
WNO
MNO
MHO
MNO
MHO
MNU
NHO
.. HO
WNO
NNO
.. RO
MNO

lAPE

~U"BER

345116

OATE

3/2216 '; •

PROJECT NO.
2360
2361
2362

2363
...;J

en

2364
2365

j /

lJ

PAGE 63

' : 14,

';JOU';J PROGR'I1"E~ .: : f; •

PH!L:"lPPI rAPE

NU"~EH

345116

ADDER TEST TULE
107365
,07366
1073b7
01310
07.171
07372
07373
07374
0737~

C.:I
I

- H1E 111 J

01376
07377
07400
01401
01402
01403
07404
01405
07406
07407
07410
07411
07412
07413
01414

OC':' 37774.J7775.J7776

H7'4

3777':>
37776

DODO!

OCT 0000J,0000l.00002.12525.25252.25252.25252.1i525.12525.00002

00001
00002
12~~~

252~l

l,2,l
252,l

12!)jt,
12525
OOOOl
00002
37171
H77"
00000
H77,
00001

OCT OOOOi.J7777.J7775.00000.J7775.00001.37777,OOOOl.J777.,3771,

37777

00001
37776
37776
00000
05001

TABLE

OCT 00000
(:ND TESTUl

DATE

3/22'65.

PROJECT NO. 53005J PROGRAM"EH

J.~.

J/22/6~.11/26/00
A.M,
STARTED
COMPLETED J/l2/6~.11/33/16 A.".
~UM8iR Of INPUT H~COADS
1~69.
~UMBER 0' OUTPUT HECORDS 1886,
NUMBER 0' BINAAY RECORDS 1295.

PHl~LIPPI

TAPE NUM8ER 345116

CORE CROSSTALK TEST (OlOA)
I.

Purpose of Test
To clear any half-set cores and to check core for crosstalk interference.

n.

Description of Test
The test is divided into two parts:
In part one the following sequence is executed:
core location.)

(TOPL~C

Store positive zero at location T~PWC, check,
at location T~PLOC, check, store positive zero
repeat this procedure for locations T~PL~C-l,
where LAST W (1528) is the last location of the

= highest numbered

store negative zero «377778)
at location T~PWC, check;
T~PLOC-2, ••• , LASTL~ .. l,
core crosstalk program.

In part two the following sequence is executed:
Store negative zero (377778) in location T~PL~ for an arbitrary number of
times, check to see that all core locations in the same bay as this location
are positive zero; repeat this procedure for locations T~PL~C-l, T~PL~-2,
... , LASTL~+1.
Provision has been made to vary the highest core location (T~PWC) from the end
of the crosstalk test (LASTL~+1 ::: 1538) up to and including 37777 8• Errors will
occur if T~PL~C is a number for which no core bay exists. Since the program
does not communicate with any I/O devices it needs no interrupts. Thus the program is to be run under lockout.
The first part of the program unsets any half-set cores that may have occurred
before testing. After this part is finished, part two checks for crosstalk Interference. The number of cycles of this test may be varied from 1 to 8191 times,
or if desired, the test may be run continuously.
III.

Operation of Test
A.

Read in the binary tape of the Core CrosstAlk test using the bootstrapped binary loader.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Usirg the probe, load the X-Register with the startlftglocation of the
binary loader (X7602); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape reader.

5.

Turn the reader on.

6.

Depress the Start button.

4-1

B.

Bnter the test parameters.
1.

Put machine In WRlTB mode; depress the Master Clear button.

2.

Using the probe, load the S-Reglster with the parameter location.

3.

USing the probe, load the X-Register with the parameter constant; depress the Start button.

4.

Repeat 2 and 3 unttl all the following parameters have been entered.
I.ocatlon
1388

Tc,JPI4C

1378

N~CYCL

Preset
375778
0

Descrlptton
Highest core location to be tested.
Number of cycles to be done.

C. Start the test.
1.

Put machine In WRITE mode; depress the Master Clear button.

2.

USing the probe, load the X-Register with the starting location of the
test (08)' depress the Start button.

3.

Put machine In RUN mode; depress the Master Clear button.

4.

Depress the Start button.

D. If an error Is encountered, the test will stop with the S-Reglster set as follows:
Part One Error:
S-Register (0-7)
001
002
003
004
005
006

Description
First poslttve zero stored or read incorrectly.
First positive zero stored or read al negative
number.
Negative zero stored or read incorrectly.
Negative zero stored or read al positive number.
Second pOsitive zero stored or read Incorrectly.
Second positive zero stored or read as negative
number.

Location ADORES (1408) wtll contain the addrels of the error. Thul contents
of the contents of ADORES may be Inspected if half-let cores are not SUlpected.
Part Two Error:
S-Register (0-7)
007

Description
Disturbed location not zero.

LDcation ADORES (1408) contains the address of the location where storage
actually took place; location I4CND'X (1418) contains the address of the disturbed location.
4-2

To continue testing. depress the Start button.
E.

If the number of cycles becomes equal to N(.4CYC L, the program Is terminated

with the S-Reglster (bits 7-0) containing 0108. If N(.4CYCL equals
zero, the program runs continuously.

IV.

8

positive

F.

Proper operation of the core is verified by the absence of computer stops
(except, of course, stop 010).

G.

The program may be restarted by pushing the Start button.

Storage
Number of locations used:

152 8 (1-1528).

4-3

DATE

3/2U65.

TAPE NU"BEM 345045
1
2
3

CONE CROSSTALK

PNOGH," LIBRARY
PROQRA" NO. P-50 D18A

4

5
6
1
10
11
12
13

37577

00000

14
:1.5
11

10001
1.002
OD003

2.
21

10004
IOD05

16

22
23
24

25

00006

10007
00010
00011

26

00012

27

00013
00014
00015
10016
000:'7

10
11

32
13
14
35
16
11
40
41
-2

43

4,.4

STAAT

1~6

PANTl

32 0

37 0 140
11 0
37 0
32 0
37 1
321
20 0
00 0
24 0
27 0

152
142
1~1

140
140
014
001
016
016

32 0 l!iO

37 1 140
32 1 140

.OO~?
"O~i
IOO~"

00

00015

a
0
a

IO{l~:'

32 1 140

o.s.

46

'O!I.;)~

20 0

,,,,.~3

10 0 00;

10 . .) ,

lOceT

,,20CCT

24 0 • .s6

PC.l
NOC.CL
CNiR
TOPLOC
ADDRi;S
END
COUNl
.0)
'DDR~S.I

ADDRES.I
UCCT
1

JMP 20CCT
PJP 20cel
~TP 2
l:NL-o)
STL ADORES ••
ENL ADORES. I
PJP lDec)
lJP 40CCI
STP J

OU.s

.00.0
OOO.)i)

ORG
ENL
STL
ENL
SlL
SUB
5TL
ENL
5TL
ENL
ZJP
~TP

27 a 025
20 0 Ol6

24
O~6
00
004
32 0 1'1
37 1 140

'OO~b

"LOOP1

DO 0 Oait

.002:

lOO~O

TME fOLLO~.NG ARE PROGRAM PARAMETERS'
37577
MIGHEST ADDHESf
TO BE CHECKED
TIMES 8EOU a
NO Of CYCLES '0 ~~ COMPLErED

HIADAS8~OU

00001
32 0 117
3i 0 14.s

47

'0

TES~

.soceT

.. ocel

J"P 40CCT
STP.
ENL .0)
sn. ADORES. 1
~NL ADCfcES:1
ZJP 'OCC'

51P,
J"P tocc:

NOTE WELLI TMIS PROGRAM MUST SKIP I ' TN' ACC.
PROGRAM IS TO BE RUN UNDER LOCKOUT
RESET NO. or CYCLES COUN~ER
UNSET MALfSET CORES TEST
STORE ADDRESS INDEl
STORE NUMBER

or

ADDRESSES INDEl

WRITE POSe ZERO IN -ITM CORE LOCATION
READ -ITM CORE LOCATION
NOT ZERO, STOP 1
PROCEED
NOT POSe ZEMO. STOP2
WRITE NEG. ZERO IN -ITM CORE LOCATION
READ -ITM CORE LOCArlOH
NOT NEG IfRO,

&TO~

NOT NEQ, NU"BER.

J

~!OP

4

WRITE POS; ZERO IN -ITH COME LOCATION
READ -I'M CORE LOCATION
lOT ZERO, 5'0' ,
PROCEED

DATE

1/2216~;

'ROJECT NO.
51
52
51
5.

"'6

~

I
C11

•

TlME

10/46/02

A.M,

'AGE

~nOO5l

PAOGRAHI'\ER t:.E. O."ARE

IU035
1110036
1D0037
ID0040
D0041
00042

00
01
01
20
24

27 0 036
0 006
0 140
0 142
0 0.2
0 006

~OCCT

fi'JP

APE NUP'I&EI4

ucel

5Tp 6
6()CC'

~45045

UCR ADDR~S
DCA COUNT
ZJP eCTAlK

","P lOOPl

NOT POSt ZiMO. STu~ 6
DECREMENT ADDRESS INDEX
DECREMENT COUNT
CHECK CROiSTAl-1e
WRITE-ReAD TE5T N~XT CORE LOCATION

2

DAYe

3/22165.

T I"E lO/46/0J

PROJEC'!' NO. 5300505 PRUGRA""'EM
51
U

61
62
63
64
65
66
.7
70
71
72
73
74
75
76
77
~

I

~

110
lOt
102
103
104
105

lO6

107
110
111
112
113
114

115
116
117
120
121
122
123

00043
00044
00045
00046
08047
00050
00051

32 0 136
J7 0 140
32 0 141

OOO~l

047

00053
00054
00055
a0056
00057
00060
00061
00062
00063
00064
00065
00066
00067
00070
00071
00012
0001.5
00074

GOon

000'76

00077

00100
081Ul

37 0 14l

32 0
J7 1
01 0
27 0

150
140
14l

32 0 140
1l 0 1.16

12
20
32
12
13
37
12
20
32
24
32
11
24
32
37
12
06

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

146
011
140
146
145
141
14~

066
14.,
1l)J

145
l~i

104

:.""
141

146
14l

.52 0 lJ6

12 0 14')
24 0 tol
COGIG

o

00102

05

OOUl

20 D 061
10 D ~.4
37 n :'4Z

10104
00105

14l

A.".
~:E:.

'A8E

O.t4ARE

TAPE NUHBEH 345045

EJE
C:TALK ENL TOPL,UC
5TL ADORtS
JPlHT2 ENL. 1O0l
~TL COUNT
klfL -0)
STL 'DDR~S.a
'OCC~
UCA COUNT
PJP 70CC!
ENL
EUR
SAND
J
ZJP
ENL
I'NO
IEOR
J
STL
lAND
lJP
UNL
J"P
80ceT UNL
90CC T SUB
"HP
100ec' ENL
STL
""D
50R
E"L
aANU
J"P
OCT
tOJCCT EUR
lJP
JlI~CCT AUD
110eeT S L

3

CRossrALK TES'
STORE lDDRESS INDEI

WRITE NE; ZERO 11. TIMES (A~BITRA.Y YlL"E J
TO SET UP rAYOMAYLE CONDITrONS FOR
CROSSTALK iETW&EN CORE LO~A:!ONS

'ODR~S

!OPLUC
.10000)
100ceT
ADORES
30000)
7177)
LoeNDX
30000)
aocer
n77)

105CCT
7177)
END
l10eCl
TO'LOC
LDeNUX
30000'
COUNT
TOP!.OC
7777)
Ulccr

•••

COUN"T
90ceT
11
C:OUN

'IND COMMON 8"

ilTS

ADDRESS AND TO'Loe IN S,HE 81'
ADDRESS IS IN A LUMER 8A' Tt4AN TO'Loe
SET LOCNDX TO HICiHES' 8A y ,-O:A TJ ON If("
WMICN ADDRESS IS IN
LoeNDI IS IN lAY lERO
LOCNDI IS NOT IN 8AY ZERO. SET COUN! "0
4096 DECI"AL (ONE 8AY)
SET COUN' ~o 409' "INUS
INSTRUCTION IN TEST

~O

cr

SET LOCATION INDEX TO TOP LOc,TIOit
STORE 8A' lERO INDICATOR
SE' COU~T TO TO'LOC, I' Nor III lAY Z=MO
SKI" PAS! ACCU"ULATOM LueA~ION
aCCU"ULA!OR LOCATIU..
TO' LOCATION iN lA, lERU. SET ~Cv.T TO
TOPLOC "'MUS NO. or '115. J .. TEIT
STORE NO; OF

MORD~

TO Ii

c~cCKED

DATE

3/22165.

TIME 10/46/0li

PROJECT NO, 5l005J

PROGRA"~ER

II

PAliE

".

E E.

124

O.HARE

TAPE NUMBER J45045

i:JE

U~

126
1.50
Ul

132

133
1.54
135
136
lU

140

TI"E •

141

I

...;a

142
'43
144
14'
146
147
150
15,

(,6'·C4.'US,·t4096'·NONORDS
"INUTES/CYCLE

If NOMORDS IS 16&841
TIME. 7•• , MIN/CYCLE
THIS TIME rUHMULA MAY BE USED TO OBTAIN
A ROUGH lPPHO)I"ATION or !HE LENGTH or
A CYCLI. SINCE SIMPLIfiCATIONS "AYE IE&N
"ADE TO OBTAIN SAID rORMULA.

154
155

162
163
16.

HAS OCCURRED

lr HOWORDS IS 40961
TIME. 19,2 MIN/CYCLE

1~3

161

CRO~STALK

TIME. .DOU-NOWORDS

152

156
157
160

CHECK WHETHER

tLOOP2J IS THE DUMINANT LOOP IN THAT THE
TI"E TO EXECUrE ALL ·HE OTHER INSTRUCTIONS
15 NEGLIGIBLE CO"~ARED TO THIS LOOP: THE
TOTAL NUMBEH or MACHINE CYCLE~ IS 16. If
A "AXIMUM or 4096 WOADS AAE CHECKED CIT IS
ASSUMED THAT THERE IS NO CROSSTALK BETWEEN
lAYS' rOR EACH BAY. THEN THE MAXIMUM TIME
rOR ONE COMPLETE CYCLE TO CHECK ALL THAT
WAS REQUESTED WOULD lEI

127

,;..

4

OUlD6
00107
00110
00111

00112.
00113

lOt 0 150
10 ! 1'1
2$ 0 130
vl 0 141

01 a 142
'I' II 101'1

iNL -0)
ADD LOCNDl(.J
C.1P l40CCT
120CCT 1>l:N LIlCNPX
lIeH COUNT
flJP LOOP;t

LOOP2

INITIALIZE rOA CAMAY JUMf'
CNE(;K LatA TI ON
LOCATION HA~ CHANGED, NO· POS, ZEAO
LOCATION OKAY
eNECK NEXT LOCATION

DATE

1/22/6>.

'"E

T

10/46/1.\

A.M.

PAGE

PROJECT NO. 5J005J ilROGRAM"EA E,E. O,HARE
16~

32 0 151
37 1 140
at 0 140
32 0 140
11 0 152
20 a 122
24 0 044

i:JE
i:NL.
5TL
OCR
ENL
SUB
lJP
..IMP

00123
00124
00125
00126
00127
00130

32

a 14.1
20 0 002
U1 0 143
27 0 002
00 a 010
24 a 000

UOCCT i:NL
l.JP
OCR
J'JP
STP
..IMP

CNTR
PARTl
CNTR
PARTl

32

au
all

10131
10132
10133
10134
10135

a 140
a 141

UOCCT ENL
ltUB
lJP
STP
J"P

ADORES
LOCNDX
120CCT
7
l20CCT

!1~

00116

III

.12
113
II..
It'

216

~

I
00

TAPE NUM"ER 345045

00114
00115
00116
00117
00120
00121
00122

166
16'
171
171
172
173
174
17'
176
177
'11

110
112
113
a14
216
117
121
III

122
223
124

11

20 0 110
00 a 007
24 0 110

IUU"/

37577
00000

00140
10141
ID142
10143

oooou
00000
ooouo

00000

00144

OCT
OCT
OCT
OCT
laa:N
.. ..cO
·..cD
.. ..cO
.. ..cO

n~!1

"HD

1 .. 144
10145
10:46
IU147
10150

.soouo

101~1

DUO:lO

00001
011! ,

RESET AND SETUP rOR NElT
·0'

ADDfH:S,l
ADDA~S

-"0

CMOSSTAL~

TRY

RESTORE CONTENTS OF TRIED CROSSTALK ADRiSS
DECREMENT ADDRESS

ADDR~S

END
l.JOCCT
PAATZ

8

ShAT

ALL ADDRESSES HAVE BEEN TESTED
TRY NEXT ADDRESS fOR CROSSTAL~
REPEAT TEST CONTINUOUSLY
REPEAT TEST FOM NU"BER or CYCLES
TEST fiNISHED. NO. or CYCLES COMPLETED
"EPcAT PROGMA"

ERROR OK". CHECK WAS ON ADDRESS
CROSSTALK EMRON. CH~CK ADDRESS AND
LOCHDX, AND CONTINU.: IF DESIRED

THE f OLL ~"1 NG "A' BE PAOGAAM INPurs:
TOPLDC OCT ~ lADH~
TOP LOCATION
NOCYCL OCT ·l"ES
NUMIER OF rYCLES
ADORES
LOCNOX
COUNT
CNTlt

,

DATE

J/221l,5.

!IHF 10/46/17

PAGE

A." •

PROJECT NO. 5J005J ?ROGRAI1I1ER t:.f:, O.HARE
225
226

221

00152

00152
00152
00000

~APE

OCT LlS!LO
E~D
LAS1LO SYN L.-l
t:ND

NUM8eR 345045
LAST LOCATION

6

•• TE

3/22i 65.

TIM~

lO/46/1b

A,~,

3/2216~.10/45/0u
•• ~,
SUR TED
COMPLETED J/~2/6~.10/46/18
151.
NUMBER or INPUT H~CO~DS

A.".

"""SER

"U"BER

or OUTPUT

or

RECORDS

1~7,

BINARY HECOHDS

1U9,

WORST CASE CORE PATTERN TEST (DllA)
I.

Purpose of Test
To generate the worst case core pattern in all specified bays of core, and to check
that this pattern has been successfully generated.

n.

Description of Test
The program stores the desired pattern throughout core, from the highest location
specified (HIADR) down to the lowest location specified (L~ADR). I4ADR may
vary from the end of the worst case core program (3718) to the physical end of
core (77778 for 4K core, 377778 for 16K core, etc.). HIADR may vary from
L~ADR to the physical end of core. The pattern has been derived from the manufacturer's specifications of the core any may be deducted from the program listing. Provision has also been made to store the complement (plus zero for minus
:tero and vice versa) of the worst case core pattern if so desired.
Once the pattern has been stored, each core location between HIADR and WADR
is checked to verify that it is either plus or minus zero. Core locations are
checked from the highest to the lowest core location. One pass through this limit
is deSignated as a cycle. The number of cycles may be varied from 1 to 8191, or
if desired, the test may run continuously.
If an error occurs, that is, a core location does not contain plus or minus zero,

the core location and the contents of that particular location are printed out on
the ASR typewriter. The correct value is then attempted to be stored in this location and the checking proceeds. A control on the number of errors printed may
be changed from 1 to 8191 lines.
All interrupts are ignored except the one corresponding to the ASR typewriter.
The interrupt location and the channel number of the ASR typewriter must be
changed to correspond wi th the existing hardware setup.
In.

Operation of Test
A.

Read in the binary tape of the Worst Case Core Pattern test using the bootstrapped binary loader.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe, load the X-Register with the starting location of the
binary loader (X7602); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape reader.

5.

Turn the reader on.

6.

Depress the Start button.

5-1

B.

Enter the test parameters.

1.

Put machine tn WRITE mode; depress the Master Clear button.

2.

Using the probe, load the S-Regtster with the parameter location.

3.

Using the probe. load the X-Register with the parameter constant; depress the Start button.

4.

RepeRt 2 and 3 until all the followtng parameters have been entered.
Location
317 8

3208

:1 21 8
322 8

323 8
324 8

325 8

C.

D.

Preset
ASRCHA
INTLQC
lND
tnAnR
J4ADR

N~CYCL

PRTCNT

1

118
0
375778

371 8
0
1000 10

Description
ASR typewrttnr channel
ASR Interrupt lOCAtion
If non-zero, complement pattern
Highest corA location to be tested
Lowefllt mre location to be tested
Number of cycle" to eXAcute
Number of error printouts allowed

Start the Test
1.

Put machine In WRITE modo; depress the Master Clear button.

2.

Using the probe. load the X-&glster with the Rtarttr.1r location of the
tE'!st (l018): depreRs the Start button.

3.

Put machine in RUN mode; deprNIA the Master Clear button.

4.

DepreRs thp Start buttlln.

Anv "Trors p.f,I'ounterert will
of l'1l11'h il printout Is:
27753

~

prtntpd on l ~'" :\SR hP"Wr:'PT. An eXAmple

:l;7'i~

Thus location 277538 has dropped hit two. The ASR set IR turned on at the
start of cn(~h printout find off At thp rnd of ft.
If the number of nrror printouts hPcomes equal tfl PRTr.NT. thE" program Is
terminated with the S-Reglster (bits 7-0) contninlng two (2).

IV.

E.

If the number of cycles becomes equal to NQCYCL. the program is terminated
with thf' S-Register (bUR 7-0) containing onp (1). If NQCYCL equals a positive
zero. the program runs continuously.

F.

Proppr operation of the core Is verlftPd by the RbRonne of printout on the ASR
typewriter.

G.

The program may be restarted by pushing the StArt button.

Storage
Number of locations user!:

2678 (102 - 371).

5-2

E

3/221'!J.

TIME

11/12/57

A.~.

E.~.

JICT MO. '.1.,53 PR05RAft"ER

....

O.kARE

TAPE

1
2
I

~~aER

1

345066

MOR5 T CASE CDIE P,TTS" TSIT

"OGH,. Lla.,..,
PROGR," 10. '·5, "1'

4

,5
7

10
11
12
13

01150
00000

lSHOLOIEUU
EUU
iflADRSIEQU
MOLINe EUU
T I MI:S IEUU

0010e'

ONG
JWCCOHEnNL

OG011

t>. HPE

00000

14

ll577

15
16
17

2.
21

THE rOllOM ••• ARE PROIRAM PARAMETEISI
,SR OUTPUT CHAMNEL
11
,SR OUTPUT INTERRUPT CO"PlETION LOCA'.ON
0
P,TTiAN TYPfJ NORMAL_" COMPLiNE.TiD..... '
375 ~7
HIGHEST CORE ADORE'S TO BE •• CLUDED •• TST
1000
MAXIMUM HU"8ER or L.NES
IE 'II.TED
0
NUMBER or TEST CYCES REQUESTEDt.'8.I'J.,TE

ASROtH fUU 1

00001

UIIL

T.

Ace·l

22

GOt02

2l

00103
00lO4
IOU5

32 ~ 3:'0
37 0 3J4
32 0 367
37 1 3J4

DIU?

01 I 334
21 0 114

PJP

l~2

32 0 312
37 0 JJJ

~NL

HUDft

ST\. PSEUUP

~4

2~

27
3.
31
J2

.n
34

15

16
.17
40

41
42
43
~4

4-;
4b

,.U,
oouo
OOUl
00U2
"U3
.1114
00115
'0116
10117
00120
'0121
"122

11123
•• 124
11125

"12'
18127

11
10
31
32

I
•
0
0

32J
366
3Jl
317

10 0 36S
37 0 314

100)

STL TE"Pl
J

~TL

~UB

T~"Pl.1

LOADM

A&JD l '
STL COUNT
i:NL ASRCI1A

J

or

MORST CASE CORE PR08R'"-IIITILI!.

8L"'L. 2J4D:lJ

DCA TEMPI

J

ilART

.1'

STORE IIIORE INTERRUPTS 'CLJ
ALL THE INTERRUPT LOC'T.'"

'I

~6EUDO-PROGR'"

COUITIR .1011.

NO. Of LOCATIONS TO IE UI&D ,. T.lt

SADD 34000)

STL OUTe,","

COMPUfE 'NO STORE OUTPUT CONMAID

17 0 201

STL

32 0 356

~NL

srORE TRANSfER VECTOR TO

32 •

3~4

37 1 3~O
J2 0 124

17 0 126

n

0 321)

~7

1 327

i:NL CLKOU'"

~YEC·N

1"':'INS
STL I,.':":"OC.I

£;NL NOC':'CL

CTRi
I:NL PM ChY
~TL

9

"YL crR2

CLi'" LOCKOUt

STORE INTERMUPT ,ISTIUCTI . .
~E:STORl:

COiJliITEMS

•

3.'22165.

&JEC- NO. 5J005l PQUGRAP1Ml~ t.E. O.HARE

'AP~

NUHYEW 345066

51
52

TEST a-PART or "ATMIX!

53
54
55
56

STORED IN THE LOC. NON IEiNS CONSIDERED

60
61

62
63
64
65

NOMENCLATURE
l • O. 1. 2. 3. 4, , . t. OR 7
Y • D. 1. 2. OR J
r • rOUR OR riVE
S • 511 OR SEVEN
DUD • ODD
• EVEN
ODD • EVF" • 000
EVEN • EVEN • EYEN

..
67
70
71
72
73
I

~

If A

74
75
16
100
101

J~

102

lO6
107

0013"
00131
00112
0013l
00U4

110

111

OUl15
00136

112

00131

lU

00140
00141
00142
OO14J
00144

114
U5
116
U7
120

LJCA~IO~

IS EYEN IN THE SENSE USED 8~L.OM AND IND. O.
ALL ONES ~1L.l BE STONED IN THE LOCATION,

Ir A LOCl?IDN IS JDD I~ THE SENSE USED BELOW AND IND. O.
ALL ZEROS ~lLL BE STORED IN ~HE LOCATION,

71

103
184
105

IE

THE ALGORITHM BY WHICH THli IS DONE
IS 8RIEflY DESCRIBED 8Y THE REMARKS
THAT rOLL.Ow

57

C1I

81'~ 00-05
~O SH~ULD

DE!ER"INE WHETHEN A .0 OR

32 0 340;
oS7 0 3Jl
32 0 34!1

20 0 ~JC
01 0 l.U
12 0 U.s
12 0 340
20 0 140
01 0 3J1
n 0 3JJ
12 0 341
lO 0 144
01 11 .};il

TESTll

~NL

JNO

002DiJO

"L. CHKLUC
E:"L IND
!JP L·Z
DeN CI4I(lOC
EN~

AND

PSEUUP
000010

lJP l·2
DCR CHKLOC
eNL PSEUO!t)
AND OaOOlO
ZJP L·2
OCR C"KlUC

!~ ~~.

lERD, THE REYERSE Dr THE l80VE IS TRUe

'E

3122165:

PAGE
TAPE NUMBER

121
III
123
114

125
126

127

lJO
1Jl
132
133

114
135
136

en
I
en

3

~45066

XXOX. XXlx, XX4X. aND XX1X ARE EYEN
XXlX. XX2X. XISX. AND XX6X ARE ODD
0(1145
0(1146
0(1147
0(1150
0(1151
0:'152
01115.1
0'.1 !)4

32 0
12 0
20 0
24 0
J2 0
:'2 0

33.1
3J7

no

154
3JJ
336

20 0 1~4
01 a 3,31

PSEUDP
AND 000004
ZJP &..2
JM, tESTy
EN&. PSEUDP
EN&.

AND 000002
ZJP TE~n

OCR CMKLUC
XXXD. XXX16 xxx •• XXX§. xxx •• AND XXX1 AAE EVEN
•• 12 AND XXll ARE ODD

. DATe

3/2U65.

PROJECT

NO.

TIME 11;0.5/21

A.".

5J0053 PROGtUI1"'ER E . E. O.HARE

137

UD
\41

" 15')
O •.o1~!)

142

0011j1

1.J

OIJH>3

14.
145
146

OOHl
00162
OHtd
OiH64

147

CTI
I
Q)

32 0 JJJ

OOIU

00161

01 0 3Jt

153
1S4
1S5

00170

32 0 33,J

00171
00172
01173

12 0 ]45
20 0 17J

1"
165
166
\67

01 0 3Jl

llOtE

~UH8EH

l45066

TEif ¥·PAAT

l: JE
E /\It. P 'iEUU~
A~i;

~FJ!HD:

L ~I~

h:~l'~~!i

Of ",rRIII 91 fS 06-U

P5Hi().1
AND 0002U,I
LJP I. -2

~N~

0 lJt
0 BJ
0 344
0 167

01
32
12
20

oous

151
160
161
'62
163

~:STY

11 0 34 j
2\) 0 l~l
J2 tl JJS
12 0 34!
20 0 16J

150
151
152

156

PlfiE

DCtf Cr4KlU:.
E~~L g.;~lJu ...

NonHs

AND

O·~10li"

lJP
OCR
Ettl
AND
lJP
OCR

l·2
CHl\lUC
PSEUOP
00200;)

DONE

CHKLOC
OUX, lYlClC , 4YXX. AN!) S YH ARE ElfiN
21Xl, 3UX, 61l(X. ANa 7 'tn lRE ODD

orXI,

n- x.c, 4FU
1r_.
ARE EVEN

\5 .. # 2iU,

5SX •• 6S-)(.

AND

osn, IFXX ,
5'-X., 6FX.,

2FXl, 3SU, 4511(,
AND Iii I ARE ODD

•

DATE

3122165,;

PROJECT HO.

TIME

11/03/30

A,M

~ •• OO5J

PROGRAMMER 1::, £

011174
011175
011176
011177
011200
011201
011202
011203
01)204
01»205
01»206
01'207

32 0 3.S5
01 0 331
21 0 177
32 0 346
37 1 3J3
00000

I

170

171
172
173

174
175
176
177
200
201
202
213
204

PAGE
Ool'1ARI::

TAPE NUM8ER 34'066

~JE

01

01
:iO
24
32
37

o

333

o 332
o 205
o ll7
o l5S
o 201

DONE:

ZERO
DCR CHKLOC
EJP L·2
ENL MZERO
~TL PSEUDP.l
!VECTR OCT ••
lJCR PSEUDP
OCR COUNT
lJP L·2
JMP TEST)(
ENL CONJMP
STL TVECTR
EN~

5

STORE WORST CASE CORE "TTiRN
TESTING or LOCATION IS DONI
STORE .0 OR -0 IN TNe LOCATION BEING
TESTED AS DETERMINED BY THE T5ST. AND
TESTY ROUTINES
rF ALL LOCS NAVE 8EEN TEITED. ao TO CONTIN
Jf NOT. COME NERE AND OCR PSEUDO.' INDEX
DECREMENT COUNT
TEST NEXT LOCATION
REPLACE TRANsrER VECTOR WITH CONTlNUE JUMP

DATE

3122165.

PROJe~T

en

I ME 1110 j 13 2

A.M.

PAGE

NO, '505005J PRUGRAMr1ER E.l:. a,t1ARE

205
206
207
210
211
212
213
214
215
216
217
220
221
222
223
224
225
226
227
I
00

!

no

231
232
233
234

I"

216
237

241

l.n

CHECI<

t:JE
ENL
STL
SUB
ADD
STL

TAPE NU"BER 345066
CHECK WOAST CASE CORE PATTiAN

00210
00211
00212
OU2U
00214

32
37
11
10
37

0
0
0
0
0

00215
00216
00217
00220
00221
OU222
00223

32
20
36
01
27
00
24

1
0
0
0
0
0
0

00224
00225
00226
00227

01 0 332

20 0 2V
24 0 214

CaNTIN DCR PSeUDP
DCA COUNT
ZJP CHKCYL
JMP CNKLOP

00230
00231
00232
00233

32 0 326
20 0 2JJ
01 0 326
24 0 207

CHKCYL ENL
lJP
DCA
JMP

00234
00235
00236

27 0 207
00 0 001
24 0 101

CI NF" IT PJP CHECK
STP 1
JMP WCCORE

305J
3lJ
366
332
JJJ
213
237
327
127
~Ol

101

01 0 333

CHKlOP l:NL
ZJP
RJP
DCR
PJP
STP
J"P

6

HIAnH
PSEUUP
LOADH

INITIALIZE PSEUDO-PROGRAM COUNTER INDEX

1)

COUNT

INITULIZE NO: Of LOCATIONS COUNT

PSEUDP, I
CONTIN
PATERR
CTR2
TESTX

CHECK LOCATION

2

MCCORE

CTRl
CINF' IT
eTRl
CHECK

LOCATION IN ERROR, NOT ., OR -I
DECREM~N' PRINT COUN'
RESTORE THIS LOCATION PROPERLY
LINES PRINTED HAVE EXCEEDED LIMIT - ... ·STOP
REPEAT PROGRAM
DECREMEN' PSEUDO-P INDEX
DECREMEN' COUN' 'NOEl
CHECK NEXT LOCATION
BRING NUMBER or CYCL55 YET TO Ie DONE
DECREMENT NUMBER OF CYCL&S
BECIN ANOTHER seRIES or CHiCKS
.0, CHECK CORE INfiNITELY
-I. TIST COMPLETED---ITOP
REPEAT PROal'"

DATE

3/2216':; •

TIME

PROJECT NO, ',30053
C!41
242
243
244

245
246
247
250
251
252
2~3

til
I

to

254
255
256
l57
260
261
262
261
264
265
266
267
270
271

A,I1,

11/0.!/.s~

PROG~HIMFR

~

PAGE

,E. O.HARE

lAPE NUMBER 345066

EJE
ID02J7
'00240
00241
0024C!
00243
00244
00245
00246
0024?
00250
00251
00252
002~J

00254
00255
00256
00257
00260
00261
00262
00263
00264
0026~

00266

OOOUO

32
37

o
o

364

1

PRINT THE ERRON

PRH:~R

J

350

32 o 3~J
36 o 313
01 o 3jO
27 o 24l
32 o J~O
36 0 J
J2 0 347
36 0 31.1
32 0 3J~
36 0 267
32 0 3bj
37 0 3JO
32 0 3~1
36 0 31J
01 0 3JO
27 0 2~6
32 1 33J
36 0 267
32 0 J~2
36 0 :UJ
24 1 237

7

10WCC

ENL
STL
ENL
HJP
OCR
f'JP
E:NL

12)
CNT
ASRON
OUT
C~!

lOWCC
CH
~JP OUT
ENL Lr

(

-~

J

20lilCC

~JP

cur

ENL
HJP
ENL
S"rL
ENL
HJP
OCR
PJP
ENI..
AJP
ENI..
HJP

P!)EUUP
UNPACK

H!N

3,

CNT
SPACE
OUT
CNT
20WCC
PSEUDP, I
UNPACK
ASROH
OUT

NUMBER or TURN ON CHARS TO OUTPUT
TURN ON ASR SE'! IN PRESCRI8ED MANNER

PRINT A

C'R~IAGE

HE TURN

PRINT A LINE reED
UNPACK AND PRINT LOCATION WHICH IS IN EAR

PAINT THREE

SPACE~

UNPACK AND PAINT CONTENTS Or LOCATION
TURN OH' &SR SET

DATE

3,22165.

T'HE 11/ O.j I J &

A.M.,

PAfiE

PROJECT NO. 5J005J PROGIUH"ER E,E, O.HARE
272
273

274
275
216
277
300
301
302
303
304
305
306
307
310
311
312
313

C11

I

I-'

0

314
315
316

317
320

fAPi NUMBER

k:JE

00267

00000

00270
00214
00215
0021b
00277
00300
00301

14 0 101
37 0 3.54
32 0 3b2
37 0 3JO
J2 0 3bl
24 0 301
J2 0 360

00302
00305
00306
003U1
00310
00311
00312

14 0 3.54
12 0 3J4
10 0 357
36 0 u.s
01 0 3,s0
27 0 300
24 1 261

00313
00314
00315
00316

00000
000
000
24 1 31J
34
01

o
o

UNPACK " .,
RII r 4
I.~H

J

C~T

SET DIGIT COUNT

140)
JHP 40.,CC
JJOWCC BI:N.L ]40 ,
40WCC HIo" 3

J

AND
8UD
HJP
OCR
PJP
NTN

UNPACK TME NUMBER AND OUTPUT
SM I F'T NUMYER INTO CORRECT INITIAL POSITION

BEN~

~SH

~4§O66

Ace

STL TEMPI
ENL 5)
ST~

J

8

-:'EMPl
TEMPI
1JOOO'

OUT
CNT
JONCe

OUT
•••
OUTCOH OUT ••
OCR PC
INTRTN HTN

~IRST DIGIT IS EITMER 1·1
OTMER DIGITS ARE 0-7

aET DIGIT ~MOM NUMBER, IN CORRECT POSI!ION
rORM CORRESPONDING ASR OUTPUT CODE
PRINT DIGIT
DECRE"EN· DIGIT COUNT
GET NEXT Dlfil T

OUTPUT CMARACTiR
MAlT rOR INTERRUPT
INTEIIUPT ReTUI ..

D"Tt:

3/U/6~,

rlo/OJEC

T

NO.

,

·1 Mi;

5300~J

11/0,!/41

P~u~HA~~~~

J~l

3n
323
324
ll5
l26
30

lJO
lJ1

c:n
I

~
~

354

355
356
J57
J60
.161

362
J61
364

~

E,

PAGE

O,HA~E

TAP~

b":t

DUll ~.
OIJ320

00121
OHa
OUll!J
00124
00J2~

GOOOl
00011
00000
3 1',"'OCS"'l
00000
017'>0

337.

JJ3
l.H
JJ5
336
lJ7
340
341
342
J43
J44
345
.146
347
350
351
352
JS3

",M,

00326
0030
OOlJO
003.51
OUlJ2

Dons
00lJ4
00lJ5
00336
OOlJ7
00340
00.541
00342
00343
00J44
00345
00346
00347

00000
00000
00000

oonou
00000
00000
00000
001100

DO~O.?

01)004
0001U
OOOlO
00200
00400
01000
02000

37777

003!)4
0035!J
OU!t6

10!JOIJ
10640
ll000
17741
37740
23 0 201
23 0 2~.s
23 0 31'

D03!J7

lJUUO

OUJbO
00]61
00362

00140

OU350
OOJ~l

003!)2

OOlSJ

oouoo;

NUMBER 345066

CONSTANlS AND DATA
THE rOLLowlNG HAY BE HADE PROQIUI1 INPUTS!
I.SRCMA OC':' ASROCH
ASR OUTPUT CHANNEL NUMBER
! I\4TL(~C o:~ ASROLO
ASR INTERHUPT LOCATION
'~D
ocr P4TYPE
COI1PLEP4ENT INDICATOR
W!AUH OC':' HIADHS
HIGHEST CORE ADDRESS TO BE CHECKED
OC':" E:ND
:'uAD~
LOWEST CO~E ADDHt~S TO BE CHECKED
i~()C'(CL oc- T! MES
NO or TeST CYCLES HEOUES!EDI .O'INrINlTE
PHTeNT OCT NOLINE
PHINT COUNTER, 114 XI MUM NO. OF" LINES
CTHl
eNT
CHKLUC
COUNT
PSEUDP

OCT
OCT
OCT
OCT
OCT
OCT

~EMPl

OCT

CTkl

lERU
OOOOOl
000004
000010
000020
OOOlOO
000400
001000
002000
I1lHW

OCT
OCT 2
OCT 4
OCT 10
ocr 20
OCT 200
OCT 400
OCT 1000
OCT 2000
OCT -0
Lf'
OCT 21200/2
CR
UCT 2150012
SPAC~
OCT 24000/2
ASRurr OCT 17741
ASMON OCT 37740
CLKOUT CLJ TVECTH+l
CO~J"P CLJ CONTIN
INTI NS CLJ .'URTH
&~N

OO~'4U

9

.. leO

.,HD
.. UO
.. NO

DATE

3122165,

- "'IE

PROJECT NO. SJOO?J
00363
00364
00365
0036t.
00367
00370

11IUj/~~

PAGE 10

" , f4 ,

PROGHUII1EH t ,I::.

O,HARE

OOUUJ

iii I< 0

00Ol~

"~O
IiIHU

34000
00001

WIC
NUMLIN

Start the test
1.

2.
3.
4.

Put machine in WRITE mode; depress the Master Clear button.
Using the probe, load the X-Register with the starting location of the
test (1018); depress the Start button.
Put machine in RUN mode; depress the MastE"r Clear button.
Depress the Start button.

7-1

IV.

D.

The program will print the number of lines designated by NUMLIM and then
stop with the S-Regilter (bits 7-0) containing a one.

E.

Proper operation is verified by vilualinspectlon of the 735 prlntout with the
sample printout given above.

F.

The program may be restarted by depressing the Start button.

Storage
Number of locations Uled: 1668 (1028 - 2678)

7-2

D4 T!

.f.

'U.l1

'A:iE

1

1

7jS SELECTRIC TY~~WRITER TEST

2
3

PHO'RAM LIBRARY
PRO.RAM NO.
013A

,

~

6
7
10
11

12
13

14
l'
16

17
20
-::J

I

w

It
22

21

24

2'
26

21
10

!1
J2

n

34

n

00102
00103
00104
00i05
D0106
00107
00110
10111
00112
001ll
00114
00U5
• OU6
IOU7
10120

56

0'121

J7
•0
41

• OU2

-I

J31ZS

15

'1126
10121
10158

4J
4.

.,

.6
5.

.0123
'tlU

OJ! H

DOtH

32
37
32

37
01
27

32
10

.n
37

00102
0 267
0 155
0 266
1 t55
a 155
0 104
0 152
0 265
0 140
0 115
.II 164
0 000

~e.4

UNL
ORG
aENL
STL
UNL

J
J

ARE PROGqAM PAAA"ETEASI
735 OUTPUT CHANNEL
735 INTERRUPT LOCATION
NUMBER or LINES TO BE PRINTED
TYPE THE ENTJRE SET

or

CHARS TWICE/LINE

CHR:NT
STORE
THE

IG~ORE

STORE

g~OPE~

I~TERAUPT

I~T~RRUPT

rCLJ
LOCATIONS

.1'

IN ALL

DCA CHACNT
PJP 10n

ENL 715CH.
UDD 34000 1
SlL OJT~O'1
STL l · l

J

fN~

OUT
EH;'
Sf ...

,

D~;'
.I

So.

.a

r Aq T

~

DOP

fNL

,

~

... r n .. D

PUT

- ~ .. ~ : .

DELAY ,-

..

o ~~: :

.,H I !II;
.

~~~

: ~

~

~

.l '

~

C~

~ '4 •

C~AHHEL

TV~~~~)r=~

IN OUTPU· COMMAND

IN LOWER CASE

L~LAf

..

v'

i:"l N'J .... I'-

sal
•

...

~)WER:

UNT:~

0

E' ••

31 0 1 S
SZ 0 2,,1
H 1 1 ••
'2 J 1 ...

AC::·\
100)

2540'>
SlL. CI4RCNT.1

10n

32
3.
32 0 160
.J7 0 1S1
01 ~ l:i7
27 0 117
II 0 161
S1 1 Hl
32 0 154
3; ) 157
32 II

rOLLO~ING

THE
7350CHHEQU 53
7351ATBEQU 13
TIMES eQU 100

00053
00013
00144

~

..

...

",..,'

.

REA5DN ... ,J

.EA~T
~1Wt~

60

"ILLIS~CO-~S
CAi~ J; 'UTP.·
1~'L~RV)f .' IT 1 .. h

LJ"::~

Ca:"f

UTE

."-U65.

MOJiCT

MD.

TIME

6/57/39

530053 PROGRAMMER E.E.
00U4
00135
00136
00U7
00140
00141
00142
10143
00144
00145
00146
.0147
.1150
IOt'1

37 o 155
32 o 162
37 o 136
00000
01 o 136
34 o 000
01 o 000
01 o 155
27 o U5
01 o 156
27 o 131
01 o 157
27 o 125
00 0001
24 o 123

71
73
74

101'2
00153

00053

75

IOU"

0014"

17

0015'
111'6
00157

37777
37717
37777
07641
00071
32 I 262
13 0 141

51
52
53
54
55

56
5'7
h

61
62
63
64
65
66
.7
70

A.M.

DOU3

'AlE

O,~ARE

STL
ENL
STL
BRJN!lC OCT
DCR
OUT COM OUT
DCR
INTRTN DCR
PJP
DCR
PJP
DCR
PJP
ITP
J"P

2

TAPE NUMBER 535441
CIo4RCNT
EIIILTA8
BRINGC

••
BAINGC
••

PC
CHRCNT
IRINCIC
'IELD
NnElD
LINECT
LOOP
1
START

STORE NO. 0' CHARACTEA, TO OUT'UT IN rrELD
STORE CHARACTER BRINa INSTRUCTION
BRING A CHARACTER
DECREMENT CHARACTER 'AINI I NSTAUC TI ON
OUTPUT CHARACTER
WAIT 'OR THE INTERRUPT
lET NEXT CHARACTER
rlElD rINISHED. lET NlIT 'IElD
PRINT NEXT LINE
NO. or LINeS REDUEtTED HAVE IEIN 'II.'ID

'11

..;:J

I

~

76
liD
111
111
lla
114
II'

OOt60

11161
10162
.1163

'OOU

THE 'OlLOWING MAY BE PROGRAM INPUTS.
735CMA OCT 7l50CH
735 OUTPUT CHANNEL
INTLOC OCT 735IRT
735 INTERRUPT lOCATION
NUMLIN OCT TIMES
NO. or liNES TO PRtNT. Ir ZEAO AUN ALM'YS
CHACNT
nElD
llNECT
DELAY
NOC .. RS
ENLTAI
INTINS

OCT
OCT
OCT
DEC
OCT
ENL
CLJ

4DOO
STRTAB-ENDTAI·l
STITAI
INTRTN

DATE

41 • .,'65"

PIOJM:T NO.

TIME

53DD~3

6/57/42

A....

PROGRAMMER E. E •

O.~AI~r

~,.

UI
U3

1'1'
11.'
U6

lt7

tao

121
111
1U
U~
-::J
I

C1l

1"
126
1.27
lSO
III
~II

lSI
114
11'
lSa
il7
l41
141
l4.
l41
144
14'
14a
147

1"

1'1
~'I
1'3

I'.
1"·

TAPE

EJE

735

10'

UI
UI

PAlE

111164
1'165
011166
lIIt67
10170
OU71
11172
IU73
01174
IU75
01176
I'D 1 77
.,208
ID201
. . 202

oun

ooa04
00205
00206
00207
0.210
10211
10212
IIa13
.1214
11215
• 1216
10217
1'220
.la21
,1222
'U23
• 1124
-111225
.1226
U~27

,; ..,~ '1

00164
00010
16000
36400
360~0

35000
32400
35400
00200
31400
02400
11000
06400
34000
05000
lOOOO
32000
34400
00020
06400
17000
16000
nooo
1HOO
02400
04401
00200
32000
30000
3 .... 00
36400
3"000
36000
32400

ENDU9

yrO 6.',3
ECW L

LOWERC 735

.1.

735 28 ••
735 6t ••
735 60 ••
735 58 ••
735 5J ••
735 59 ••
735 .16.
735 61 ••
735 5 ••
735 30 ..

13'

l l ••

l~!tOO

735 56 ••
735 10 ••
735 48. ,
735 52. ,
735 57,.
735 .2,
735 13 ..
735 30 ••
735 28,.
735 10, •
735 26 ..
735
735 9, ,
735 ,16.
735 52 ••
135 48. ,
73, 57,.
735 61 ••
73'5 56 ••
735 60 ••
735 5J.,
73., 5Q .•
711tj '5£: ,

~'

7~

35400
.• t' ..

,,'

..,

.. ,

~UM8~R

515Ul
TABLE

or CODES rOR THE 735 S&LECTRfC

L.OWER CASE
QUOTeS
AMPERSAND
I

•
•UNDER
S

LINE
PLUS OR MINUS
1

DEGREE SIGN
I

CENT SIGN

•

,
(

•
u.e.
I

EXCL1MATION
APOSTROPHE

•
I

,
,
,..•
0

I

3

2
t
,::p Ar;F

1

II .c:

+/ICJ/65.

TIME

A.M.

6/51146

~AIiE

"OJfCT MO. 530053 PROGRAMMER E.E. O.HARE

1"
1'7
1M

161
162
161
1.64
16,
16,
.67
11.
.'1

172

an

1'74
S~
1'7~

-,

.7'1
2 ••

-:J
I
CT)

au
a.3

...
aM

aM

.'7
11.
IU

•• 131
,'232
"233
"234
•• 235
•• 236
"137
•• 240
"141
,'.42
"143
,'.44
••• 45
"146
,'.4'7
"2"
•• 251

"Z'2

"153
•••54
•••'S
"1'6
".'7
,'.6.
, ••61
"262

••161
"H4

"16'
"HI

,'167

Itt

nooo

735
735
735
715
735
735
735
715
735
73'
73,
73,
735
73,
13'
135
735
73,
73,
73,
73S
73S
71,
73'
13,
73,

02000
27410
10000
15400
25400
27000
120.'
16410
.4.10
.6. . .
124 ••
25. . .
174"
224"
24'"

."

.

14. . .
22101
.74"
"4"
16."
16410
244"
2. . . .
144"
..262
"'4'
•••• 3
14'"
ZI4"
. . 1 ••

.....

TAPE NUMtlER 535441

62 ••
4 ••
47 ••
16 ••
27 ..
43 ••
46 ••
20 ••
29 ••
•••
1 •••
21 ••
42 ••
31,.
37 ..
4".
14 ••
14 ••
36 ••
15 ••
11 ••
44 ••
4' ••
41 ••
12 ••
25 ••

S'I',' iQU L-l
CI

73' ,4,

IIID
IIRD
II.D
-D
i-D

,Z
I

at
Y
U
T

S
I
Q
-~

.

0

"
L

I(

J
I
N
II

r

f
D
C

•
A

Cl.lIACE .ETU."

4

DATE

"'.,/65.

Tl~E

6/57/50

A.".
TAPE NUMBER 515441

5/14/64, 6/57/00 A.M.
'1ARTED
A.M.
CDMPLE.TED 5/14/~4. 6/57/49
138.
IlUMBER OF IlIfPlJlT RECORDS
MUMIE" OF" OUTPUT RECORDS 142.
ItUM8F. or BtNARY RECORDS \21.

EXTENDED CORE MEMORY TEST
P50 COMPUTER

1.

PURPOSE OF TEST

To extensively read and write into extended (,flre :lnd 1,\
ence.

n.

D14A

l'ht:CK

for crossta1\., intcrfc'r-

DESCRIPTION OF TEST

The test program reads and writes into extended core locations HIADR (highest
address) through U'>ADR (lowest address) inc1usi\'c.
The test consists of three parts. In the first part, each (,,,tended core location is
written and read individually, starting with location BlAnn.
The pattern is as
follows: 377778 (all ones) is written into HIADR, then HIADH is read and the \':1 lue
checked, thf'n 000008 (all zeros) is written and read, then ~:i2,)2S' and fin:!ll\'
1252fi~.
Foll()wing this, location HIADR-l is written anJ read in the sam*" marmer,
ami tncn the remaining extended core locations, c1(l\\n to Lf),\DR.
The second 11:11't is executed after the first. In this :-w('tion ;tll e.\.-t('nded '':()1'e locations
are written with :!n alternating pattern; then ;dl th.: i<.cations ;1 "l' re:1d ,tn!! (hf'ck('ri.
The pattern is as follo\\s: 37777 8 , OOOOO~, ':37777"" 00000 8 , •• , i... ston·ct in locations HIADR through LOADR, then the locations are react ami checked, :~0n 00000>;.
:37777 8 , OOOOOH' 37777 8 ", i.s stored and check('d; then 232.')2 H • 12:i2::i~, 25252/'1'
12.')25 8 , and finally 125258, 2:i252~. 1252;)H' 2::-.252:-; ••••
In the third part, two location counters are initialized: C~ t(l 111\0I\, \,.. :~ to LOADR
(or one, if LOADR is zero). Positi\'c Ler(} is output to the c v tel1c!.!': l ' d'e location
whose address is contained in ('2; negative zero i~ output to loc,llion C:, Both locati()n~ are then read and their contents verified.
The adrln:::,s 111 (' ~ i" decremented;
the address ir. (':1 is incremented. The test rec\(:]cs, lIsin~ ;1,,/, lI('" .1!1.!l'css until

adclrcFs C3 contains HIADR+l.
After part thrc(' is executed, the kst decI'('ments a -":TT~l F:S ('"unter. If th(, ("Juntcr
is positive or if it is set so the test runs indefinitel\', parts (Inc, 1\\/0, and 1]-,1'cc :1l'C
again executed. If th(' tcst is set to run a fix('ri numl\l'r uf ('\'(:I('s, thc ('1I1~ pllter will
stop when the cycle counter is zero.
U an error occurs during the first OJ' third pal'b, the location ill (,IT/d' :tnd thl' correct pattern are printeri on the pro~r:lmnlt'I"s ('(}nsole ASR Sl't. If an ('1']"\1' ()('cur~
during lhe sccnod part, the ;xlt:t.'l'!l,tl""luL' -;(llr0(\ in IILO\rllO h pl'il11<-ri The ('(.nlputer stops after the error prinl'lut.

All interrupts arc ignored except the one corresponding tn thl' ASR t,rP( \\Titer.

8-1

In.

OPERATION OF TEST
A.

Read In the binary tape of the Extended Core Memory Test usinc the bootstrapped hina.ry loacl('r.
I. Put machine in WRITE mode: depress the Master Clear button.
2. Using the probe. load the X-Register with the starting location of the binary
loader (7602H. 17flO2H. 276028. or 37602R): depress the Start Button.
3. Put ma.chine in RUN mode: depress the Master Clear button.
4. Place the binary tape under the tape reader: turn the reader on.
!).

B.

Depress the Start hutton.

Enter the test parameters.
1. Put machine in WRITE mode: depress the Master Clear button.

2. USing the probe. load the S-Register with the parameter location.
3. USing the probe. load the X-Register with the parameter constant; depress
the Start button.
I.

Repeat Steps 2 and :J until all the following parameters have been entered;
t i "II
----Ii -, -; I . .

\nnCIl

nOoiO

li.i7'-,,,
li'-17 I i,..,
li,-,77 ~

()UTCII

f10t)'j -; ..,

(lOOIi:!

~

OOlllri

~

liliOI S

INTCII
ASROC
INT L
l4 0 116
01 0 20'
16 0 20"
02 IJ 205
32 0 354
.5t'1 I) 2:t'J
J2 I) 35.5
J6 0 20:'J
32 I) 3St!
.56 IJ UJ
.52 () 351
36 0 2lJ

134

EN!.
SUB
STL
EJP
JMP
DC~

HUDH

LOADH
PSEULJP
L+2
L+2
PSEUUP
PSEUUP
PSEUUP
-0 )
S02
+0)
S02
2525c)
S02

HSI1
CMI3
ENL
HJP
ENL
HJP
8E:NL
RJP
SENL 1252~)
HJP S02

ALL ONES--AL!. It::HUS
ALL ZEROS--ALL ONt:S
2~252--12525

ll525-252't!
PA~T

065Jl

J2 0 201

1341

ENL HIADH

T~HH

PAGE

41

EXTENDED CORE MEMORY TEST
171
172
173
1741
175
176
177
200
~Ol

l02
~03

j,!04
l05
~O6

00

~l:7

I

~10

00

~11

~12

~ll

06532
06533
06534
06535
06536
u6537

37 0 263
32 0 202
20 0 135
~4 0 1.s6
.52 0 350
.!d 0 264

U6540
06541
06542
06543
0654141
06545
L'6546
'-'65417
'.'6550

.56
.52

~'65 51
'.)6552
J6553

320
2641
J7
205
.52 0 J5J
.56 I) 3J~
.52 :l 26.5
J7

I)

20~

.52

')
')

J~

:' 33<'

354

J? J 26 4

'11
.52

~~J

'Jb~62

;.'6503

C'6564
06565
u6566
u6567
lJ6570
U6571
L6512
06513

J2
j,!o
01
"-7
00
l3
'l.7
24

1~6554

':6555

~17

~6556

~20

')6557
:..6560
.6561

d21
~~?

P4]

13 :1 201

l24
c ?5

~15

c16

PU

I)
I)

165
~ 26 4
10 0 350
J7 I) 264
Ot ') 26J
J? C' 26J
13 ') 26 4
l!") ') 150
') 1J7
~4

~14

"

}

STI.. C2
E~I.. I..OADH
lJP 1..+2
J"P 1..+2
E~I.. 1>
STI.. C3
HJP
ENL
STI..
ENI..
RJP
ENI.
STL
EN!..
HJP

S05
C3

PSEUUP
+0)
506
C2

PSEUUP
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SO!)

ENI.. C3
t:O~

HIAD~

UP
ENI..
ADD
STI..

P49
C3
1)

C3
DCR C2

~N!.. C2
EOR C3
I.JP PH
JMP P42

~26

"-27
~JO

~11
~l2

el3
cH
e55
<'36
~37

0 206
0 171

P49

206
I) 041"
I) 001
0 04J
I) 04':i
0 165

P5

I)

P6

END
EN\. Cl
IJP PlI
DCR Cl
PJP P12
STP 1
CI..J PU
PJP P12
JMP P5

or

UNE CYCLE
TEST

NO.

rOM

f'a~./NEij.

CYCLE~

COMPLETED

PAGE

5

EXTENDED CORE MEMORY TEST
1140
241
242
il!4J
244
245
246
241
250
251
li!52
253

EJE

06574
06576
06511
066()0
06601
06602
06603

00070
00077
00062
00015
00011
31777
00000
00000

06604
06605
06606
u6601
06610

00000
00000
00000
23 1 202
06716

06~75

25~
00
I

co

ADRCIo4
DUTCH
INTCIo4
ASRoe
INTL.OC
Io4IADR
L.OADR
NTIM6S

OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT

TIo4E FOL.L.ONING MAY IE PROGRAM INPUTS
ADRCHN
OUTCHN
INTCHN
ASROtH
ASRINT
Io4IADRS
L.OADHS
TIMES

255
~56

257
~60

il!61
C!62
il!63

OCT
11
PSEUDP OCT
OCT
Cl
INTltoIS8CLJ 202.1
INTADD OCT INTATN-l

PAQE

6

EXTENDED CORE MEMORY TEST

EJE

11164
11165
~66

267
l70
l71
l72

n3

l74
l75

276
277

06611
06612
\16613
06614
06615
06616
U6617
06620
06621
u6622

00000
37 0 26l
.52 0 205
3' 0 070
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.54 0 077
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001
A02

tOl

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211

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OUT
ENL
OUT
ENL
OUT
IN!
RTN

WHITE/READ ONE L.UCAT ION
PATTHN
PSEUDP
AORCHN
PATTHN
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PSEUUP
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F'AGE

9

EXTENDED CORE MEMORY TEST
06760
06761

00
I

....c,.,

2.5400
00100

WHO
.. HO

PAuE

10

EATENO~O

CD

....I
.,..

440
441
442
443
444
445
446
447
450
451
4;2
453
454
4:;5
456
4.,7
4:'0
4b1

CO~t:

MEMO~Y

TEST
07000

(;70DO
('7001
(;7002

J2 0 061
J6 0 074
C!4 1 157

u7003
:,,7U04
:"700-:;
~71106

J2
J7
J2
J7

4~2

1..700'7
.;7(110
li 7011
:..;7012
.;7013

J6
J2
J7
J6

4~3

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464
465
466
4!17
470
471

7 u15
v7CJ16
u701?

J2 0 Ce,J
J6 0 074

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472

J2

SUHG 7000

~NL, ASR1
WJP 507
JM~ P12

ER~U~~

t:NL,
STL,
I: NL,
l:ITL,
eNL,
HJP
cNL,

J

0 Ob.:!
0

ERRO~l

1J~

0 156
0 07~
1 1':'
0 O~O
0 154
1 1~)j
1 1,l
1 1:>1

4i!4 1 1"0

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PX)(X)I,J(

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P)(Xl(O

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PATTHN
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JMP P4

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t:NL A:iR3
HJP 507
JP4P P41

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u7to~5

07Q;z6
07027
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J?
12
16
02
16
16
16
16

OOOO!)
Q OlJ
0 147
1 146
1 146
1 14b
1 146
1 146
1 140

UNPACI<
S04
l:I7L. 04T1
J

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WSH
eMS
H"'T
HSH

JOOOU)
ACC

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6

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'-DXCi:-

N~M~~"

~U~

~RI~~UU-

~""E

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FJ(T~~DED COt1~

"'EMJ'U TeST

... 1011

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'J1iJJl

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H !) 064
12 0 14~

01015

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16 1 146

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16 1 146

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PAGE

12

EXTENDED CORE "EMORY TEST

00
I

....en

543
544
545
546
547
550
551
552
553
554
555
556
557
560
561
562
563
564
565
566
567
570
571
572
573
574
575
'76
'''7
600
601
602
603
604
605
606
607
610
611
612

useD BY ERRORl AND ERNOH3
07D74
07075
07D76
07077
07100
07101
07102
07103
07104
07105
07106
07107
07110
07111

07112
07113
U7114
07115
il7116
07117
1.17120
:;7121
ii7122
C7U3
1.17124
1.17125
07126
IJ7127
1;71.50
IJ7131
07132
07UJ
v 71.54
071.55

507

00000

37
3Z
37
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36
32
37
J2
36
32

o 132
o 141
o 07l
1 140
o 020
o 156
o on
1 155
o 020
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37 1 15.5
36 1 l!)l
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34600
31000

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00000
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34240
30500
30640

•••

STL OUTBF'-3
~NL LBUF')
STL TBUF'
ENL PSEUDP
RJP 504
ENL PBUF')
STL TBUF'
~NL PATTRN
MJP 504
ENL 20)
STL BUF'e
NJP 503
NTN

OCT
OCT
UCT
OCT
OCT
OCT 31400/2+20000
OCT 2400012+~0000
OCT 2400012·20000
OCT
UC~

PBur

OCT
OCT
OCT
OCT 3Z000/2+20000
OCT 24000/2·20000
OCT 24000/2.20000
UCT

ocr
OUTI:IF'

30500/2+20000
OCT 21200/2·20000
OCT 2150012·20000

PRJNT BurrER

x
x
X
X

x
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S~

S~

X
X
X
X

x

p

SP
SP
1 O~ 2
E

LP
CR

261 1 it6ii!

PAGE

i3

EXTENDED CORE ME"ORY TEST
613

00
I

.....
...::a

614

071.56
07137
07140
07141
0714Z
07143
07144
07145
07146
07147
07150
07151
07152
07153
07154
07155
07156
'07157

33000

oon4

06605
07116
00007
00070
00700
07000
00101

JOOOO

uno

06510
06665
06713
00014
06662
07126
0644,
00000

A&RO

OCT 26000/2+20000
WRD
WRD
wRD
MRD
MRD
WRD
wRD
WRO
WHO
wRD
WHO
WHO

WHD
MRD
.. HD
IIfHD
.. HD
E~D

nooo

ASR PUNCH-READER TEST (D15A)
I.

Purpose of Test
To verify the proper operation of the ASR punch and reader.

II.

Description of Test
The program reads characters in ASCII code through the ASR reader until two
terminating characters (minus sign and rub out) are read. Due to the mechanical
design of the ASR set. the characters being read are also printed and punched at
the same time.
After the terminating characters have been received. the entire character set
that has been read and stored is punched and printed. Thus for both the read
cycle and the punch cycle. a print record is generated. Errors may then be detected by visual inspection of these two print records. Inspection of the tape
records punched may also be done. noting that there are two tape records for the
read cycle (the ASR set punches as it reads) and one tape record for the punch
cycle.
If more than 147 characters are input as a character set. all characters after

the 147th character are ignored until the terminating characters are received.
The number of read/punch cycles may be varied from 1 to 8191 times or the
test may be set to run continuously. At the beginning of the test the ASR set is
turned on in the prescribed manner by the test program, and when the number of
cycles has been completed. the ASR set is turned off.
All interrupts are ignored while the test program is running except the ones
corresponding to the ASR set which is being tested. The interrupts and channel
numbers of the ASR set which are used 10 the test program must correspond with
the existing hardware setup.
The minus sign is the terminating character which actually signals the end of the
character set being read or punched. HoweVf~r. on the read cycle, the rub-out
character (all ones) must follow the minus sign in order to clear the ASR buffer
register for the output to follow.
III.

Description of Operation
A.

Punch an ASCII character set tape on the ASR punch. off-line mode, via the
ASR keyboard. The tape must end with a minus sign and a rub-out character
(all ones). A suggested character set is a carriage return, line feed, followed
by:
ABCDE FGHIJKLMNOPQRSTIlVWXYZ

OI23456789!"*$%& 10*'=:

/;

and terminated by the rub-out character. Turn the ASR punch off and place
the ASR switch in the OFF position after the character set is punched.

B.

Read in the binary tape of the ASR Punch- Reader teat using the bootstrapped
binary loader.
1.
2.

Put machine in WRITE mode; depress the Master Clear button.
Using the probe. load the X-Register with the starting location of the
binary loader (X7602); depress the Start button.
9-1

S.
4.
6.
8.

C.

Put machine In RUN mode; deprel. the Muter Clear buttoD.
Place the binary tape under the tape reader.
Turn the reader on.
Depress the Start button.

Enter the Test Parametera.
1.
2.
3.
4.

Put machine in WRITE mode; depress the Master Clear button.
VllOi the probe. load the S-Reglster with the parameter locatton.
Uatnl the probe. load the X-Reglster with the parameter conat&Dt;
depress the Start button.
Repeat 2 and 3 until all the following parameters have been entered.
Location

213 8
214 8
215 8
216S
21 7S
D.

2.
3.
4.
5.

2.

3.

1

o
100 10

ASR Input Interrupt Location
ASR Output Interrupt Location
ASR Input Channel
ASR Output Channel
Number of cycles to read and punch
(1-S19110, or zero).

Put the beginning of the tape containing the character set from the ASR
punch under the ASR reader and turn the ASR punch on.
Put machine in WRITE modej depress the Master Clear button.
Using the probe, load the X-Register with the starting location of the
test (101S); depress the Start button.
Put machine in RUN mode; depress the Master Clear button.
Depresa the Start button.

The program will print and punch twice the number of recorda deslgnated
by NUMTIM and then atop with the S-Regiater (bits 0-7) contalnlng one
(1). If NUMTIM ia equal to zero, the test will run continuously.
Proper operation is verified by visual inspection of the ASa printout
from the lnttial character set. Note that turning the ASa off and on may
punch a few rub-out characters on the tape. These should be tgnored
while cheoklng the tape.
The program may be reatarted by depreastlll the Muter Clear and Start
buttona.

Error Stop
1.

2.
3.
~V.

lOS

11S

Normal Completion
1.

F.

ASRIL0
ASR0L0
ASRICH
ASR0CH
NUMTIM

Description

Start the Test.
1.

E.

Preset

If blts 0-5 of an input word are non-zero, the prosram will atop with the
S-Rel1ster (bila 0-1) 00Dta1nl1ll a two (2).
The accumulator may be examiDed to ucertaln wbat Ulepl character
was input. (Note: Tbe reader iDpula to hila 6-13 of the accumulator.)
The procram may be rutarted by execu&laIatepa • aDd S in Section

m.

D.

Stor...
Number of locatioDl uaed:

MI. (10Ir.6S.,.
9-2

I, .

DATE

4/27165.

",OJECT NO.

T lIIE

5~1'53

P.M,

2'51/30

"'SE

PROCRl""ER E.E. O,HARE

TAPE NUMBER 512641

1
2
3
4
5

ASR PUNCH-RiADER TeST
PROGRAM LI BRARY
PROGRAM NO,
P-,o

6
1
10

1t
12
11
14

15
16
17
~

I

w

2.
21
22
23

24
25

26

OOU2
OOlOl
OH04
30105
00106
00107
OHiO
00111
D0112
0011l
0011"

00010
00011
00001
00000
00144

T-IE fOLLOwING ARE PROGRA" PAR'HET~A51
ASRIRT8E:JU 10
ASR IN--UT INTERRUPT LOCATION
ASRORT8~JIJ 11
ASR OUTPUT INTERRUPT LOCATION
ASR 1eN E(JU 1
ASR INPUT CHANNEL NUH8EA
ASRoeN EUU !)
ASR OUTPUT CHANNEL NU"BEA
T! MES EQU lJO
NUMBER OF" LINES TO BE READ OR PUIICHED

00102

~SRPRT

l2 0 2t!6
17 0 U7
J? J 215

S Tl Ci-IRSru
BENL. '341))

227
01 J 217
27 0 104

23 0 110

~4

D0116

35

32

36

.0117
00120

37

!)

17

00121

0 232

40

10122
00123
00124
00125
00126
00127
00130
DOUl
OU1ll

"2
.17

10
11

J2
13

41
42
43

.4

45
46
47

50

00115

J2

10
.17

32
10
37

32
37
32
37
32
36

lO;,;~T

l

0 215
0 22-4
0 210
0 216
0 '22J
0 204
0 217

27

UNL
OR::; ACC·l
8EN~ t J 0 )

17

D15A

,
J

230

1 21-\
0 231

1 213
0 222
0 227
0 lJ7

0 2DJ
01 0 227
Z7 0 ill

,
20A5~T

~T,"

:. ~

DC~

:..jRST~

P...IP

104SWT

~:; ~

(.: , I

CLJ L+1

ENL .5 K I ~.I
BAUD jlGOUI
STL INTcU~
ENL 45RO(;~
8AOO HOOOI
STL 'JUTCO"1
ENL NUMT1M
STL COUNT
ENl QUlIN:i
STL ASROLJ.I
ENL PHIN:i
STL ASRILOoi
ENL 12)
STL CYRSTO
ENL T URN~'.
FUP

8~lO~~

iJ:::R
I'JP

c~~STJ

~JASHT

STORe: 1,,"J~~ INTFRAu,rs lCL'J • II 1M ALL
THE I~r]~~u~r l~C1TIONS
CLEAR L:J:KOUT
STORE

PR'~E~

CHANNEL IN INPUT COMtil"D

STORE "R(lPt;R CH4NNEL IN OUfPUT COMNAND
SET

HA~IHU"

NUMBER

or LINES TO

BE AEAD

STORe OUTPUT II!fTeRRUpr INSTRUCTION
STORE INPUT INTERRUPT INSTRUCTION

TURN ON ASR SET IN

PR~SCA18&D

MANNER

1

DlTE

4127165,

r U'E

~/!;7/"5

j:),,,,,

'.IE

PAOJECT NO, 5JO:J53 PROGRAMMER E.i. J.HARE
51
52

53
54
55
56
57

co
I

~

60
61
62
63
64
65
66
61
10
71
12
73
74
75
76
77
100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120

:

TAPE NUMBER 5l2Ul

II:

~V'.

00133
00134
00135
00136
00137
001.40
00141
00142
00143
00144
00145
00146
00141
00150
00151
00152
00153
00154
00155
00156
00151
00160
00161
00162
00163
00164
00165
00166
00167
00170
00171
00172
00173
001U
00175
00176
00117
00200
00201

32
37
36
36
37
12
20
32
00

0

0
0
0

1
0
0
1
0

12 0

37 1
23 0
32 1
11 0
20 0
32 0
U

-

20 0
01 0
24 0
32 0
37 0
32 1
16 0
36 0
32 1
~1 0
20 0
01 0
24 0
32 0
36 0
J2 0
20 0
01 0
21 0
J2 0
36 0
00 0

233
227
207
207
227
221
146
227
002
220
227
147
227
235
156
227
234
135
227
135
233
2:.!7
227
101
203
227
235
170
227
160
237
203
230
132
230
132
236
203
001

So; ()RAG
Sh. CHRSTO
HJP INTONE
INPUT HJP :~TONE
ST~ CHRSTO.J
SAND 77)
J
ZJP CKMINS
EN~ CHRSTO.I
STP 2
BAND 3770U)
J
STL CHRSTO.J
CLJ L·2
CK"lNS Ei.: CHRSTO.I
sur 'rNUS
STAkT

E~~

2. ....

ENL
SUB
ZJP
DCR
J"P
RESET ENL
STL
OUTPUT ENL
HSH
RJP
EN~

SUB
ZJP
DCR
J"P
RUBOUT ENL
RJP
ENL
ZJP
DCR
PJP
ENL
RJP
STP

c::S~T

" tRSTO
LIMIT
INPUT
CHRSTO
INPUT
STORAG
CHRSTO
CHRSTO.l
ACC
OUT ONE
CHRSTO.l
"INUS
RUBOUT
CHRSTO
OUTPUT
TURNON
OUT ONE
COUNT
START
COUNT
START
TURNor
OUTONE
1

SET CHARACTER STORAGE INDel
IGNORE rlRST CHARACTER
INPUT A CHARACTEA
STORE CHAAACTER INPUT
CHECK rOR ILLEGAL BITS SET CD-'.
BRING ILLEBAL CHARACTER TO ACCUMULATOR
STOP WITH S-REGISTER SiT TO A TWO
STRIP orr ILLEGAL BITS
CLEAR LOCKOUT ON A STOP
CHECK rOR A MINUS SIGN
IT IS. EXIT TO OUTPUT

MAXIMUM NUMBER or CMR6 HAYE BEEN INPUT
DECREMENT CHARACTER STORAGE INDEX
RESET CHARACTER STORAGI INDEI
BAtNB CHARACTER AND IHlrT INTO POSITrON
OUTPUT ONE CHARACTER
CHARACTER IS A MINUS SIIN, TEST COUNTER
DECREMENT CHARACTER STOAAGE INDEX
OUTPUT NEXT CHARACTER
OUTPUT A RUBOUT CHARACT&A
Ir COUNT IS ZERO, READ AND ltVNaM CONnNUOI
DECREMENT COUNTER
CONTINUE READING AND PUNCHINI
TURN orr ASR SET AND STOF WUH I·REG • 1

I

DATE

4127/65.

TIME

2157/50

p."',

,.cae

PROJEC T NO. 530053 PROGRAMMER E.E. O,HARE
121
122
123
124
125
126
127
130
131
132
113

co
I

CJ1

o

00202

24

00203
00204
00205
00206

00000
34 a 000
01 a 000
24 1 203

OUT ONE
OUT COM OUT ••
OCR PC
OPTATN ATN

00201
00210
00211
00212

00000
30 o 000
01 o 000
24 1 207

INTONE
INTCO'" INT ••
OCR PC
IPTRTN ATN

101

TAPE NUM8&R 512641

JP1P ASRPRT

...
...

REPEAT
OUTPUT A CWARACTEH
WAIT rOR INTeRRUPT
INTeRRUPT RETURN
INPUT A CHARACTER
WAIT rOR l~TERRUPT
INTERRUPT RETURN

oJ

DATE

4/27/.,.

PROJ5CT NO.

TIRE

,~ •• ,~

2/57/51

P.N,

paoQRAMMER E.i. O.HARE

140
141
142
141
14.
145

TAPE NUM8ER '12641

EJE

1~4

11'
116
1~7

It. . . .

"21~

••214
'121'
•• 216
11217
11121
"221
11112
11221
.1224

"I"
Ma26

00010
00011
00001
00000
00144
~7700

01077
' .. 14

..,..
~4"0

'.101
1141.

ASRJLO
ASROLO
ASlle"
ASAOCH
NUMTIM

OCT
OCT
OCT
OCT
OCT
QEN
WRD
WRD
WAD
WAD
WRD
MRD
MRD

THE rOLLOWING MAY 8E PROQR.M INPUTSASRJRT
ASA INPUT INTERRUPT LOCAT."
ASRORT
ASA OUTPUT INTERRUPT LocaT,,,
ASAICN
ASR INPUT CHANNEL
ASRoeN
A5A OUTPUT C"ANNEL
TIMES
NUMII,R or LINES TO
"I" •

I.

~.

DATE

4/27/65.

TIMi

2157153

p."'.

'~GE

PROJECT NO. 5J[1053 PROGRA"MER E.i. O.HARE

14,
147

151

151
U2
153
154
155
156
157
160

OO:i~27

OO;!!30
00231
00~!32
OU~'3J
OO~~H
OO~!J5

OO:1!36
1D~~37

00000
00000
23 o 211
23 o 205
00463
00240
25500
17741
37740
00240
10000

CHRSTQ
OOUNT
INTINS
OUTINS
STORAG
l.IHIT
"'INUS
TURNor
TURNON
BUHER

OCT
OCT

TAPE NU"8&R 512641

IPTRTN
OPTRTN
DEC BUHER·147
DEC BUHER
OCT 25500
OCT 17741
OCT 37740
SYN L
END
CLJ
CLJ

CHARACfER STORA'E INDEX
COUNTER rOR NU"BER or LIMES
INPUT r~TEARUPT ,NSTRUtTION
OUTPUT I~TERRUPT INSTRUCTION
BEGINNING or BurrER INDEl
END or 8UFrER INDEX
ASR "'INUS SIGN CODE
ASR TURN orr CODE
ASR TUAN ON CODE
8urreR STOAAGE FOR CNARACTERS

!

DATE

4/27/65.

TIME

2/57/55

P.M.

PROJICT NO. 530053 PROCR'""ER E.&. O,HARE

STARTED
4/27/65. 2/57/01 P.N.
COMPLETED 4/27/.'. 2/57/55 P.N.
NUMI,R OF INPUT RECORDS
112.
NUMIIR or OUTPUT RECORDS 119.
NUMIIR or I'NARY RECORDS
97.

,

CP

00

HIGH SPEED PUNCH-READER TEST (D16A)
1.

Purpose of Test
To verify the proper operation of the high speed punch and reader.

II.

Description of Test
The test program begins by pW1ching 12 blank characters (leader) and 255 data
characters. After this paper tape has been punched, it should be placed in the
high speed reader.
The program then reads the paper tape that has been pW1ched and compares each
character to the character used as data. If a character input is not the same as
the data character. a pW1ch or reader error has occurred and the program stops.
After reading the paper tape, the program repeats the pW1ch cycle and the read
cycle W1til both cycles has been performed eight times. (This number can be modified.) After eight times, the program stops.
All interrupts other than the pW1ch and reader interrupts are ignored while the
test is in progress. Interrupts and channel numbers used in the test program
must correspond with the existing hardware setup.

III.

Description of Operation
A. Read in the binary tape of the high speed pW1ch-reader test using the bootstrapped binary loader.
1. Put machine in Write mode; depress the Master Clear button.

2. Using the probe. load the X-Register with the starting location of the binary
loader (76028, 176028. 276028. or 376028); depress the Start button.
3. Put machine in RW1 mode; depress the Master Clear button.
4. Place the binary tape W1der the tape reader.
5. Turn the reader on.

•

6. Depress the Start button.
B. Enter the test parameters.

1. Put machine in Write mode; depress the Master Clear button.

2. Using the probe, load the S-Register with the parameter location.
3. Using the probe, load the X-Register with the parameter value; depress the
Start button.
4. Repeat 2 and 3 W1til all the following parameters have been entered:

10-1

Location:
1748
175 8
1768
1778
2008

NOTE:

c.

Description:

Preut:
PCHL0C
RORLfl)C
PCHCHA
RORCHA
NUMTIM

Punch Interrupt Locatlon
Reader Interrupt Location
Punch Channel
Reader Channel
Number punch-reader cycles

6
228
508
848
108

If zero is entered as the number of punch-reader cycles (location
2008), the test wil1 run continuously.

Start the Test
1. Put machine in Write mode; depress the Master Clear button.
2. Using the probe. load the X-Register with the starting location of the test
(1018); depress the Start button.

:t Put machine in Run mode; depress the Master Clear button.
4. Depress the Start button.
D. Normal Execution
1. After the punch completes one punch cycle. place the paper tape under the

high speed reader; turn the reader on.
2. After the proper number of punch-reader cycles have been completed (location 2008). the machine will stop with the S-Reg1ster (bits 0-7) containing
one (1). If location 2008 is zero. the test runs continuously.
~t

The test may be restarted after a one stop by depressing the Master Clear
and Start buttons.

E. Error Stop
1. If a character is mispunched or misread. the machine will stop with the
S-Register (bits 0-7) containiq two (2).

2. The accumulator (location 1018) may be examined to ascertain what character was Vlput. (Note that the reader inputs to bits 6-13 of the accumulator.)
3. The program may be restarted after a two stop by putting the machine in
the Run mode and depressing the Master Clear and Start buttons.
IV.

Storage
Number of locations used:

V.

5328 (1028 - 6338)

Run Time
Program runs at the speed of the
Recommended Run Time:

hiP speed reader and punch.

25 minutes

10-2

( .

PAGE

1

Hluri SPEEU

~UNCH-READEH

TtST

PHOGHAH NO. "'-50 016A

1

HIGH SPEED PUNCH -READEN TEST

2
J
4

PHOGHAH L. U:lRARY
PHOGHAH NO. P-50 D16A

5

6

7
10

T~E

OOOUb
OUO£2

11

12
......
0
I

I:,.:)

13
14
15
16

OUO~O

01.1064
OU010

11
20
21
22

23
24
25
26
27

.sO
J1
.s2

1.1011.12
UU1UJ
llU1u4
\,;U105
OU106
UU107
(JOllO
OU111
UU112
(JU1l3

Jl

01.1114

34
J5

UOl15
uU116
OU1l7
OU1c!O
OUi.!l

Jb

J7
40
41

4l

00122
OUll3

4J

0Ol~4

44

OUi~5

4,

PCH1HT8E:UU
HDRIRT8tuu
PCHCHN8E!.IU
HDkCHN8E:UU
TIMt:S tUU

OUlttl

J2
.)7
.)2

J7
U1

n

~3

00102
U 217
o 2U.)
U 21b
1 2UJ
0 20J
0 1U4
u 11U

.)2 0 171
10 0 21~
jJ

a

.)2 U
10 0
,)7 0
.)2 0
.)7 U

UN\.
"'NRUTT UHG
8E:NL.
J
:,TL
Bt:N\.
J
10RPT ~TL
UCH
PJP
CLJ
ENL
BAUD
J

14~

~

2UO

t:NL

1'"

ACC·l
100)
tHJHt:R

FT 1M~

t:NL
6AUD
fl.

~lL

J

B

~TL

~TL.

204

~O

64

ENL

1~.)

J2 0 21J
J7 0 2U:>
J2 0 20~
J7 1 17,
.)t! Ll 2U1
J7 1

U

fULLOWING ARE PRUGRAM PAHAMETtHSI
PUNCH INlEHHU"'T LUCAl ION
Rt:AUEH INIEHRU~T LUCATION
PUNCH CHANNEL NU"~Ek
RtAUEk CHANNEL NUMYt:R
NO. OF" CYCLt::S 10 ~E: READ Ok PUNCHED

2J40UI
BUFFt:H,1
t:HJ F" F" t: R
1f)RPl
L+1
HURCHA
JOOOOI
INTCUM
PCHCHA
HOOll )
OUTCUM
NUHT,,.,
COUNI
1)

176
214

J

6

G

STORE IIiNUt4HDl T

OU4UO
OUbJ4
0041~

IoJI'ach point. After pVl'ry
point has been read CYCLES (specified ill inItLtllZ;ttion) times, the results are
printed on the document device. If the sp.tn ;l(liu~tment feature is selected, the
span values are also printed on the dl)Cllment device.
The test can be operated with or without span :uljustmcnt. The last point spec lfied
for each vidar will be taken as the span calihrate point if this option is selected.
This point must he short clrcuited for proper operation of span adjustment. ~p:m
point settings are printed every b re:Hlings if the span print option is selectc·d.
When the test has gone through the numher of scan cycles specified by CYCLE~,
the data collected in the tables is output in the format below.
Col. 1
00100
00100
00100
00100
00100
00100
00100
00100
10007
10010
10006
10011
10005
10007
10006
10005
10010
10011
•lUUUI
"1"'\""''''
10010
10006
10005
10011
00002
00003
00001

Col. 2
00100
00100
00100
00100
00100
00100
00100
00100
00033
00021
00020
00003
00001
00041
00022
00001
00012
00002
nnl\Ac:.

UUU'hJ

00017
00011
00001
00002
00047
00025
00004

Col. 3
00077

ooon
00077
00077

ooon
00077
00077
00077
17457

Col. 4
00077
00077
00077
00077
000/7
00077
00077
00077

oQnOl

The four columns are the span
pOint settings for the 4 vid:lrs
IJ"ing tested. Column 1 is lur
vidar #4, column 2 is for vida r
#:l, column 3 is for vidar #2, and
column 4 is fur vidar #1.

Column 1 contains the reariin!-!,
No conversion is donc :md
the readings are the actual inputs.
t~en.

17457

000112

Column 2 contains the frequency
at which each reading occurred.

17'H;'7
.&.IV..,I

00004

Column 3 contains the word and
channel address together With the
~ain at which the point was read.

17357

00010

Column 4 contains the hit ;J.odress.

11-1

Col.I
10010
10005
10007
10004
10006
10003
IlL

Col. 2
00013
00015
00017
00011
00017
00001

0>1. 4

Col. 3
27257

00020

A11 numbers are octal. When
more than one vidar is being
tested. the readings for the
highest numbered vidar are
printed out first.

Description of Operation
A.

B.

Read in the binary tape of the Analog Statistics Test using the bootstrapped
binary loadar.
1.

Put machine In WRITE mode; depress the Master Clear button.

2.

Using the probe. load the X-Register with the starting location of the
binary loader (76028. 176028. 276028' 376028); depress the start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape reader.

5.

Turn on reader.

6.

Depress the Start button.

Enter the test parameters.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe. load the S-Reglster with the parameter location.

3.

USing the probe. load the X-Register with the parameter constant: depress the Start button.

4.

Repeat 2 and 3 until all the following parameters have been entered.

Location

Preset

4048
405 8
4068
-:i:078
410 8
4118-4278

ANLINT
NUMTST
TYPCHN
ASRINT
VDRADR
CYCLES
CYCTIM
SPNSET
SPNPRT
ADRTBI

4
0
118
14 10
1008
1010
0
0
0

430-446

ADRTB2

0

447-465

ADRTB3

0

466-504

ADRTB4

0

.008
4018

402 8
4038

Description
Analog conversion complete interrupt I..oc.
No. vidars to be tested
Document device output channel
Document device output complete into LOC..
No. points per vidar to be tested
No. cycles before printout
Tenths sec. delay between scans
Zero to adjust span
Zero to print span adjustment
Gain. word. channel select control
words for vldar no. 1
Gain. word. channel select control
words for vidar no. 2
Gain. word, channel select control
words for vidar no. 3
Gain, word. channel select control
words for vtdar no. 4

2

11-2

Description

Preset

Location
505-523

BITAB1

0

524-542

BITAB2

0

543-561

BITAB3

0

562-600

BlTAB4

0

Bit
no.
Bit
no.
Bit
no.
Bit
no.

select
1
select
2
select
3
select
4

control words for vidal'
control words for vici1r
control words for \ 1cl;1 r
control words for vidar

The format for the gain, word, channel select control words is as follows:
Bits 13, 12
Bits 11-6
Bits 5-0

gain
word
channel

Bit 13 = 1

50 mv

Bit 12 = 1 5 volts

The bit select control words contain one bit set.
C.

D.

IV.

Start the test.
l.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe, load the X-register with the starting location of the
(600S); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button; depress the
Start button.

The test runs continuously, reading each point the desired number of times
and printing out the data.

Storage
The program uses 7140S locations (4008-75378),

V.

t(~st

Run Time

Recommended run time: 4 hours.

11-3

PAGE

1

1
2
3
4
5
6
7

PRCG~AH

TIT~~:

P-50 KAWK 11 ANALUb )lATISTICAL reST

(Dl?~-!)

SOURCE COMPU:ER: P-500. SYSTEMS LAB. MeSAP 50/500
OHJEC! CCHPUTEH: P-50 MARK If SERI~S

~O

11

12
13
14
15
16
17
20
21
22
23
~
~

I

~

AdS!KACT: THIS

P~OGRAM

IS A REVISION OF D178. IN D17B-l

rHE ANALOG CONVEHSION COMPLETE luTERRUPT

INITIATES THE INPUT ArTeN ALL VALUES HAYE YEEN
STORED. 1N D118 NO VALUES ARE S~ORED UNTIL
THe ANALOG CONVERSIUN COMPLETE IN!ERRUPT 15
RECEIVED. SEE DESCRIPTION OF SAME CODE N~M9ER
AVAILA~LE FROM C,StD. DRAFTING SECTION.
CODING: NOT STNDHD1 - REVISION or D17A PROGRA""ED ORIGINALLY
PRION TO STNDRD1,

PAGE

2

24
(!5
26

"-7
30
31
32
33
34
35,
36,
~
~

I

tn

cJE ASSEMBLY PARAMETERS
OUUlid
OU:JtJ 4
000'-''''

ouo:.:

ANIl'ti
NUI't.vuf.<

t:1..IL;
t:l.ILJ

~
4

DOCOLJ-bt:l.;~

U

DOClj'-J-~H"J

11

OUUU:

AS~

OO~'JO

OR 1 l:J I I\j h t: ~ ~' 40e

~U~

1

DUu:e

:51'

VDRCH18:::.J~

OU::; .. O

VCRCH,ot"U

1.6
3e>

401
41.

oLl a

000')0

VD~Co-i3t\= J;~

5{\

-'t)

VDRl,;H41:1t:~~

'76

THE tULLOwlNG HAY BE CHAN(iED AT HUN TIME
ANAL.OG COI'4VERSION COMPL.ETE INTERRUPT L.L:CA-:-!ON
MAX I MUM ~O, V!DARS TO BE HSTED
DOCUME:NT DEVICE OUTPUT CHANNEL
DOCUHENT DEVICE OUTPUT COMPLETE IhTE~~0P· LOCATION
THE tOLLOWll'4G MAV NOT BE: CHANGED EXCEPT !iI" "Ii:ASSEM8L.Y
AS~:l TO UU'rPUT ON ASR SET, -0 TO OU·F'L:
')N SELECTR:C
PROGRAM ORIGIN
SPAN AND GAIN AND INPUT CHANNE:L FOR VIIJA~ 1
SPAN AND GAJN AND INPUT CHANNEL. rOR VILt.R 2
SPAN AND (JA!N AND INPUT CHANNEL FUR VIUAR J
Sf>AN AND GAIN AND INPUT CHANNEL. rOR V!UAR 4
9

PAGE

J

P-!JO "ARK II At"AL 018 INPUT STATISTICAL TEST (D178-1)
42

c.JE

43

44
45
46
47
50
~1

52
53

54
S5
56
57

.....
.....
I

en

60
61
e.2
63
64
65
66
67
70
71
72
73

00400
00400
004iJl
00402
OU403
U0404
00405
00406

OOOOl

ANLI~T

00004
00000
00011
00016
00100
00012

NU"~ST

Type"N
ASRINT
YDRADR
CYCLES
CyeTI"

00401
00410

00000
OUOOO

00411

SPNSET
SPNPRT
AORT8l

00000

00430

00000

00447

00000

00466

00000

00505

00000

005~4

00000

74
75

76
77

00543

00000

00562

00000

AORT82
ADRTI:I3
AORTB4
SITAlf1
BITABa

UfifL
OHG OHIGIN
THE rOLLuwl~' ARE I~PUTS AT RUN TIME
OCT AN!N1 A~ALO' CONVERSION CO"PLETE INTERAUPT LOc;n I 0"
ucr NU"YUA NU"8ER or VIDAAS TO BE TESTED
OC· DOCOJT DOCU"ENT DEVICE OUTPUT CHANNEL
OCT DOCIN'! DOCU"ENT DEVICE OUTPUT CO"PLETE INTERRUPT LOCA~:0~
!JEC 14
NU"8ER or POINTS PER VIOAR TO BE READ
OCT lUO
NU"8EA or READINGS PER POINT BEfORE PRINTOUT
u.:c 10
CYCTIM.l/10 SEC. c TI"E DELAY BEfQRE NEl~ HEAUP,,~ OE"
ALL POINTS
OCT
ZERO TO ADJUST SPAN,NON-ZEAO TO SkiP SPAN ADJUS·
UCT
ZERO TO PRINT SPAN,NON-ZERO TO SkiP SPAN PAI .. r
NORD CHANNEL SELECT rOA VIOAN NO. 1
15
OCT
Nt'T 15
NOND CHANNEL SELECT rOR VIOAR NO. 2
ocr
At'· 15
NOAO CHANNEL SELECT rOR VIDAN NO. 3
DC'!
HPi 15
WOAD CHAN~EL SELECT rOR VIOAR NO. 4
OCT
J(PT 15
BIT SELECT rOR YIOAR
t
UCT
BIT SELECT rOR YIOAR
"fiT 15
2

""'1'

"0.
"0.
"0.

3

BIT SELECT rOR VIOAR flO.

4

ocr

BJTAB3 RtI! 15
OCT
BITAB4 APT 15
UCT

BIT SELECT rOR VIOAR

PAGE

~

P-50 I1AHI< I : AlliAL.OG INPUT
100

1(11
102
103
104
105
106
ll17

112

113

.....
.....
I

...;J

1.14
1.15

1.16
1.17
1.20

~D171:1-1'

tJE PHUGr(AH CONTkOL.

UUb01
UU602
U06u3
OUbC4
(JubU5
UUbUI>

a

0 201
1 3ib
J6 0 UJ
16 0 3~l
'c.7 I) 2~6
..)1)

.::4

, L+l
RESTr(T
ANAL.OG H";;,J Uu7ANI
l'I~ri
iNU
::"

J

lSTt,;I'1G

0 ;? 'J b

OUb07
OUbl0

ou6='l

0061.2
U!Jb:,J
OUb14
UU615

3~.s

.)6 1
~2 0

37,

J2

~..:p

r:~s~

JI":O'

~+l

U:'E 4-NUP'lIJDIoI·2

J;,: 0
J~

-~

H";'>

110
111

-I::ST

ST1TISTICA~

~,..

J

...

toIJOJ

3~4

S.1oVE4
STORI:;

I::f>4L SAVE:~

375

t(~tJ

.)2 0

3~6

00016

,)6

3/~

123

UUb.7
00620
OU621

!: f4L SkvE1
I'IJ? S':'CHi:

UJ 0 3:;,l!?
16 0 3~1
't.7 0 202

ll24

OUOin

~4

l.ll
1.~2

1

0 2:.7

-

F"IRST TII1E
IG~OHE INPUT
REPL.ACEABl.E DURING INITIALIZATION
STOHE VALUES READ

t:NL SAVEJ
HJP STORI:

1 31;
0 30;5

,)6 1

SET L.OCI(OUT
INITIALIZE PROGHAH
INPUT DATA.OUTPUT "UL.TIP~EX~R ADDRESS

F'IFcS'!'

SrORl:

::'P'l1:I !NO
ANT
t'lJP ANALU\i
k::'ri

JI'1P L.-2

WA IT F'OM INTERRUPT
RECYC~e

'AGE

5

p.IJO "ARK 11 ANALOG INPUT STATISTICAL

I-'
I-'

,

00

125
126
127
130
131
132
133
134
135
136
137
140
141
142
143
144
14S
146
147
150
151
lS2
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174

~EST

(D178~1)

EJE
THIS SUBROUTINE IS ENTERED AfTER ALL 'REVIOUS
DATA HAS BEEN STOReD AND THE ANAL~Q CONVERSION
CDHPLETE INTERRUPT IS RECEIVED, IT INPUTS DAT.
CURRENTLY ON THE DATA LINES A~D STORES IT IN
~EHPDRARY LOCATIONS rOR EACH VIDAR, IT THEN
OUTPUTS SPAN AND GAIN AND MULTIPLEXER ADDRESS
rOR NEXT POINTS.
OU623
00624
OU625

00000
03 o 351
l4 o 225

OU626
00627
OU630
00631
00632
00633
00634
00635
00636
00637

30 0 076
37 0 353
;SO 0 056
37 0 354
30 0 036
37 0 3~5
~o 0 016
37 0 356
.s2 0 374
24 0 237

OU640
00641
00642
00643
00644
00645
00646
00647
00650
00651
00652
00653
OU6S4
00655
00656

34 0
0
34 0
34 0

~4

32
12
10
37
32
12
10
37
32
12
10

076
056
036
016

0 307
D 373
0 372
0 265
D 311
0 37.1
0 372
0 271
0 31J
0 373
0 37l

DUTANl

;

~

:

=»H8
2NDCHG JHP
DL.E
IN;
S-L
IN:

ANT
L·l
4-NUHVDR.2
VDRCH4
SAvE4
VDRC H3

REPLACEABLE DURING INI TULUATION
INPUT CURRENT DATA AND STORE TEMPORARILY

... VORC 2

~-,

IN7

SAVE~

H

srI. SAVE;t
IN~ YORC"l
571.

SA~El

8ENI. 200)
3RDCHG Jf'!P L·l
OI.E 4-NUHVDR
OU~ VDRe"4
uur VORCH;!
UUT VDRCH2
OUT VORCH1
tiLE 4-NUHVDRe4
ENL LAOR4
./
aAND 377'
IAOD 3200U)
J
S':'L GAIN4
ENL LAUR~
lAND 377)
8ADD 3200U)
S""L GAIN~
ENI. LAOR;t
8'''D 377)
8AUD 3200U)
J

OUTPUT SPAN AND &AIN rOR NEXT POINTS
REPLACABLE DURING INITIALIZATION
RESET IPAN

PICK UP &AIN

PAGE

6

P-50

MARt(
17~;

i71!>
17'7
lOI~

20:1
iO:2

I I ANALOG

I~PU!

STATISTICAL -EST (0178-1)

00657
00660
00661
00662
OU663
OU664

37
32
12
10
37
24

0
0
0
0

00665
00666
00b67
00670
00671
00672
00673
00674
OU675
00676
00677
00700
00701
00702
00703
0070 ..
00705

32
12
10
J4
32
12
10
34
32
12
10
"4
J2
12
10
34

0 066
0 371
1 370
0 076
0 047
0 371
1 367
a 056
0 030
0 371
1 366
0 036
0 011
0 371
1 365
0 016
0 305

275
315
37J
3n
0 301
0 264

20:5
lO,4
~O!5

20,()
c07
211D
211
212
213
214
~

~

I

~

Ill'5

21,6
~17

22D
221
22,2
223
2l"
225

226
227
~30

l31
~32

233
234
235
236
237

~4

00706
00707
00710
00711
00712
00713
00714
00715
00716
00717

32 0 162

34
32
J4
32
J4
32
34
J2
J4

1 Ob6

00720
00721
00722
007,3

j2
10
37
32

0 306
0 36J

240

241
242
243
Z44

0 143
1 047

0 124
1 OJU

0 105
1 011

0 364
0 016

0 30b
0 307

S-L
ENL
8AND
SAUD
SiL
4iHCHG J"P
OLE
GAIN4 ENL.
./
8AND
./
AUD
UU':'
GAIt-IJ ENL
BAND
ADD
./

our

GAIN2
./

GAIN1

ENL
8AND
ADD
0 1'oJ,
''''
E: '~L

GAIN~

L.AOR1
377)
3l00U)
GAINl.
L+1
4-NUI1VDR-4
ADRTt:l4
30000)
SPwRjJ4

REPLACEABLE DURING IN! rIAL III TI ON
OUTPur SPAN ANO uAl~

VDRC~4

AD,Ht:l3
3000U)
SPwRD3
VDRCH3
ADRTt:l2
30000)
SPWRU2
VDRCH2
AUR'!'t:ll
3000U)

8AND
ADD SP~RiJl
OU· VURCHl
5THCHG JP1P L+l
LAE: 4-NU MV UR-2
t:NL tjITAt:l 4
LADH4 UU- ADRid4.l
Et-IL til'!'Atl3
OU~ ADRTt:lJ,l
LAD~3
ENL BlTAtl2
LAlH( 2 OU7 AURTt:ll.1
ENL BIiAt:ll
LADRl OUT AURTt:ll.1
8ENL 400)
J
UUT VDRCI'11
DLE 4-NUMVDR-6
E: r~L LADR4-1
ADD 1 )
.J
::,rL LADR~-l
J

t;N~

L.ADR4

~EPL.ACEABLE DURING
P1ULIIPLEXE~

OUTPUT

INITIALIZATION
ADDHESSeS rOR NeXT POINTS

OUTPUT TO TRIGGER ANAL.OG COhVERSION
UPDATE POINT ADDRESSES

QAGE

7

P-50 "ARK II

~

~

I

I-'

0

245
246
247
250
251
252
4!53
254
255
256
257
260
261
262
263
264
265
266
267
270
271
272
213
i74
275
276
217
300
301
302
;SO~

304
305
.s06

A~ALOG

l~PUT

STATISTICAL 7EST (0178-1)

0(1724
00725
00726
00727
00730
00731
00732
00733
007J4
00735
00736
00737
00740
00741
00742
00743
00744
OU745
00746
00747
00750

10 0 363
37 0 307
32 0 310
10 0 363
37 0 310
32 0 311
10 0 36J
J7 0 311
32 0 312
10 0 363
37 0 312
32 0 313
10 0 363
37 0 313
32 0 31 4
10 0 363
37 0 31 4
32 0 315
10 a 363
37 0 315
24 1 223

00751
00752

00000
00000

ANT
IHD

00753
00754
00755
00756

00000
00000
OUOOO
00000

SAVE4
SAVE3
SAVE2
SAVEl

0
0
0
0

BITF'X4
BJTF'X3
BITF'X2
BJTFXl

00757
00760
00761
00762

32
32
32
32

163
144
125
106

ADD 1>
~TL LADR4
e~L LAOR.)-l
ADD 1)
5TL. LADR~-l
E~L LADR3
ADD 1 )
STL LADR.,
ENL LADA4!-l
ADD 1)
STL LADR2-1
ENL LADA~
ADD 1)
STL LADR~
ENL LAD R1-1
ADD 1)
STL LADR1-1
ENL LADR1
ADD 1)
STL LADRl
HTN

UCT
OCT
OLE
OCT
UCT
UCT
UCT
DLE
ENL
ENL
ENL
ENL

4-HU"VDA

4-NU"VDR

BIT~tt4·1

BIT'83·1
BIT'tt2·1
BnAH1·1

PAGE

8

P-50 "ARK 11 AhALOG

I~PUT

STATISTICAL TeST (0178·1)

~O7

00763
00764
00765
00766
00767
00770
00771
00772
OU713
00774

.....
.....
.....I
.....

00775
00176

EJE
00001
00400
02162
02161
02160
02157
30000
32000
00377
00200
01400
01000

MHO
.,HO
MHO
MHD
MHO
MHO
MHO
WHO
WHO
MHO
MHD
MHD

PAliE

9

P-50 "ARK 11 AIULOG INPuT STATISTICAL TEST (0178-1)
~10

......
......

....I

t.:)

311
"12
313
314
315
316
317
320
321
322
323
324
325
326
127
130
331
312
133
334
335
336
337
340
341
342
343
344
345
146
347
350
.151
352
353
354
3~5

356
357

01000
01000
01001
01002
0100,5
01004
01005
01006
01007
01010
01011
01U12
01013
01014
01015
01016
01017
01020
01021
01022
01023
01U24
01025
01026
01027
01030
Ul031
01032
01033
01014
01035
01U36
01037
01040

"2
10
37
.t2
37
"2
10
10
37
.s2
10
37
32
.s7
"2
10
10
37

01£141

J2

01042
01043
01044

"7
"2

00000
1 370
10 o 307
~7 1 366
.)2 1 365
~2

.)7 0 276
.)2 1 364
,)7 0 27't.
~2 0 J60S

"7
32
"7
01
~7

~3

~7

0 273
0 271
1 273
0 273
0 012
0 016
0 216
0 364!
0 274
0 361
1 274
0 271
0 216
0 36l
1 276
0 27l
0 362
0 274
0 360
1 274
0 270
0 2n
0 3b~
1 2:~'t.
1 3;:'
1 3,0
0 35~
1 354

UHG 0" i G1,,,.256
THIS SUBRUUTINE INITIALIZES THE INTERRUPTS AND
THE TEST PROliRA" TO STAHT OR NESTA"T THE TEST.
WE~TRT •••
ENL TYPC,..N
J
J
8AUD 3400U)
~-L. UUT+ 4
J
INIT I AL lZE DOCU"ENT DEVICE OUTPUT CHANNEL
J
ENL ASHI~T
5·' TVPINT
INIT IALIZE DOCU"ENT DEVICE INTERRUPT LOCATION
J
ENL ANLi"'l
~HL INTLuC
INITIALIZE ANALOG CONVEkSlON CO"PLETE 'NT. LOC.
J
8ENL 100 )
STORE IGNORE INTERRUPTS IN ALL LOcaTIONS
5~L L5iIr.r
~NL CL.JOl
~'!L LSTINT,I
UCR LSilNT
P.JP L-2
CLJ L+l
CLEAR LOCKOUT
ENL TYPINT
STORE TYPER INTERRUPT JU"P LOCATION
ADD 65)
J
S~L RND
ENL INTR1N~1)
J
S'!L RND,1
i:NL CL.JOI
STORE JU"P IN TYPER INTERRUPT LOCATION
ADD TYP!NT
ADD 65)
~rL TYPI"T.I
EffL INrLUC
STORE ANALOG INTERRUPT JUMP LOCATION
AUD 65)
.~

~!L

01

J

"

H"O

i:NL
STL
ENL
AIlD
ADD
!;iL
I:NL

ANLNT)
RND. ,
t1JPINS
l'nLUC

~":"i..

~H70UT

STONE RETURN

·JVftP-1N~"LOG

iflTE..""'T LOC,T,.

b5)

lHTLUC,1
C"CLI:!;

J

t:NL bl

01

S:L SPNCNT

NO. CYCLES BEfORE PRIN':OUT
INITIALIZE CYCLE COUNT fOR 5PAII ADJUIT

PAGE

10

P·50 MARK I 1 A!'IIAlOli
J60
361
362
363
364
J65
366
367
370
371
372
373
374
375

.....
.....
I
.....
~

376
377
400
401
402
403
404
405
4U6
407
410
411
412
413
414
415
416
417
420
421
422
423
424

425
426
427

01045
01046
01047
01050
U1O!)1
01052
010;3
01054
01055
01056
01057
01060
01061
01U62
01063
01064
01U65
01,066

I~pu~

~;ATjSTICAL

J2 1 35J

J7
J2
10
01
t.7
J7

37
J2
01
J7

0
0
1
0
0
1
1
1
1
0

J

2]4
J

351
2H

J

047
J
J

10$ .)2
14 1 362

10
14
14
J7
J2

0 274
1 362
1 36~
1 346
0 35~

01067
01070
01071
01072
01073

37
J7
37
J7
32

01074
01075
01076
Ul077
01100
01101

~7 1 341
37 1 340
37 1 3J7
J7 _1 336
03 1 335
U2 1 3,54

01102
01103
Clll04
01105
01106
011£.1'
01110
01111

J2 1 3:;1
10 0 333
37 0 274
J2 1 3.s~
J7 1 2:'4
j2 1 3~1
10 0 3;Sl
37 0 274

I:Nl NUI'IT:,T
~-:-L

35~

350
347
35J
362
?74

-I:ST (D17H·1J

J

1 345
1 344
1 343

J
J
J

1 342

J

0 275
J

J

""
J
J

l:NL 0)
ADD VllHAUH
UCH HND
t"'JiJ L-2
~;L

TOTA1J~

FINC",T
~NL NUMT:,T
UCR ACC
S~L

~

L~H

Ace

LSH
ADD KI~D
LSI"! Ace
LSH ACC
S7L 20DCk
I:NL

o)

ULE
SiL
S:L
SiL
S-L
ENL
UL.E
&TL

4-NUMVDR
StlAN4
SPANJ

cMe

1 f~D

Er~L YURADH
ADO AlJRTts4)

S-:-L.

Rr~D

ADRTtt4
S7L liND, 1
E:NL Vi.)RALl~

AUD

S-L

INITIALIZE SPAN ADJUST WORDS TO ZERO

SjJAN~

SPANl
S~ 1 N"
4-NUI'IYDM
SPWH1I4
S~L SPWRU3
S7L SPWR1J2
STL SPWHU1
SMa AI~7

t:NL

J

MODlrv CONSTANT 20DCW

... u
Ace

S'7L

OL.E 4-NUMVOR-1O
J

CALCULATE TOTAL NO. POINTS TO YE TESTED

i·(I·~D

B:TA~4}
~ND

SET INITIAL SPAN VALUE

CL.EAR ANALOG INTERRUPT INDICATOR
SET rlRST READ INDICATOR
STORE rlRST POINT AND YIT ADDRESS J'OLLOWING LAST

....
....
....I

~

PAGF

1.1

P-50

~.RI(

430
431
432
433
434
435
436
437
440
441
442
443
444
445
446
447
450
451
452
453
454
455
4'6
457
460
461
462
463
464
465
466
467
470
471
412
473
474
475

476
411

11

A~Ai.)u

01112
01113
01114
01115
01116
01117

INPU'r

Si.~I:.i:Cl,

32 1 332
J7 1 21"

(11121
01122
01123
01124
01125
01126
01127
01130
01131
01132
01133
01134
01135
01136
01137
01140
01141
01142
01143
01144
01145
1i1146
01147
01150
OU51
01152
01153

J2 1 351
10 0 331
37 0 274
32 1 331
~7 1 274
32 1 351
10 0 330
J7 0 274
052 1 330
37 1 214
32 1 351
10 0 3~7
31 0 214
32 1 327
37 1 274
32 1 351
10 0 326
37 0 274
32 1 326
37 1 274
32 1 351
10 0 325
37 0 274
32 1 325
37 1 274
J2 1 351
10 0 324
37 0 274
32 1 3~4
37 1 274
36 1 3~3
"6 1 322

01154
01155
01156
01157
U1160

01
01
01
01
01

011~0

1
1
1
1
1

321
320
317
316
315

...

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£lL.E.4-NU"VDH.2
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OCR L4DR4-1
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AEINITIALIZE TABLE POINTERS
STONE ZEROS IN TABLES

PAGE

12

P·50 MARK J I

......
......
I
......

01

;00
501
502
503
504
505
506
507
'10
511
512
51-3
51 4
515
516
517
520
521
522
523
'24
525
526
527
530
531
'32

'33
'34
535
536

'37

A~ALOG

01161
01162
01163
01164
01165
01166
01167
01170
lI1171
1.11172
01173
Ul174

01175
01176
01177
01200
01£01
01202
01203
01~04

01('05
u1206
U12Q7
01210
lI1£11
01':'2
u1£13
01214
01215
u1216
0!d7
Olau

INPUT STATISTICAL -EST (0178-1)
01
01
01
32
13

1
1
1
1
1
0
1
0
0
0
1

314
313
312
3~3

311
310
36l
307
306

10
14
10
12
10
30~
j7
307
j2 ...1 3~.s
13 1 311
10 0 310
14 1 36~
10 0 304
12 0 306
10 0 3C~
37 1 304
32 1 3,.s
10 0 3:.0
10 0 3U,!
12 il 30e
10 0 30~
37 1 30~
"2 ! 355
13 ... 3 ' •
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14 1 3:1"
14 1 36"
10 Q 31)2
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PAGE

13

'-50 "ARK I I ANAL.OG INPUT STATISTICAL ;EST ( 0178-1>
!)50
551
552
553

01231

~54

01'::35

'55
556
557
560
561
562
563
564
565
566
567
570
'71
572
573
574

~
~

I
~

0)

I
I

01~J2

01233
01~J4

OHJ6
01~J7
01~40

01~41

01242
01243
01244

12
10
.)7
J2
13
10
J7
1"
10

01~45

1"
10
10
12

01e46

10

01247
01250
U1251

01~52
l/1~53
Ul~54

(112;5

~75

01~56

576
577
600
601
602
603
604
605
606
607
610
611
612
613
61 4
615
616
617

01257
01260
01~61

01262
01~63

l/ljt64
01~65

01266
01~67

01270
0~271

01272
01273
01274
01275
01276

057
J2
13
10
37
14
10
10
12
10
057
l4

0 306
0 30~
1 301
1 35J
1 311
0 310
0 274
1 362
0 274
1 364!
0 274
0 300
0 306
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1 300
1 35J
1 311
0 310
0 274
1 36l
0 274
0 277
0 300
0 305
1 277
1 000

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BAUD 2400U>
~TL. 5THC"u
I:NL
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00100
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00100
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6TH C"ANGE - IN ADJ5PN

R'~D

LSH ACC
AUD "NO
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7TH CHANGE - IN ADJSPN

ANAI.OG INTERRUPT ROUTINE

•••

&OR RNO
CHEf AIIIT
I:UH H~O
CI..,: ANLNT,I
kJP

, I

CLJ
OCT
OC;
OCT
OCT
TYPIN"r OCT

.I
M~IN~

100
1110
DOCINT

PAGE

14

P-50 "URK I I

A~ALOG

INPUT STATISTICAL TEST (0178-1)

620

~JE

01277
01300
0131.11
01302
01303
01:'04
01:'05
01306
01307
01~10

~
~

I
~

...::J

01311
01312
01313
01314
01315
01316
01317
01320
(/1321
013~2

U1323
Ulll4
U1325
01326
U1327
U1330
01331
u13J2
li1333

(j13J4
01335
(j1336
(11337
01340
OLS41
01342
01343
01;)44
G134S

OllJ..s

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00664
00637

wt
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10 0 31.)
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...

...

~:L

OHIG&lh512
THIS SUBROUTINE UPDATES THE STATISTICS fABLES
AFTER EACH CONVERSION. IF' PUINTS HAYE SEEN READ
CYCLES TI"ES.PROGRA" GOES TO ~RINT ROUTINE.
!NPSAV

i: I'4L L!IIOPUG.I
~ue OlD
S·L Ht:I1CNT
l:NL LNOkUG.J
~TL HUGC"T
iJP l SiSTH
COMf'AR ~NL INPSAV
~UR

L~EDNG.I

SAVE VALUE READ
NU"BER or READINGS ALREADY STORED

FIRST READING OF A POINT
HAS VALUE ALREADY BEEN STORED 1

~JP

0 01~
0 04:!~

~o

01424
01425
01,426
01417
011t30

STOkE

13 1 31~
i.7 0 O1J

01~14

01~23

OI'CG

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L·2
J"P L·2
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"U1) Li~UHUG. 1
ST.1- Li'40HUG.l
i:NL ONE
AUD LF'"Ew.J
!)~L LF'I\EU.I
l:NL INPSA'I
STL L.tfED~G,1
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L~E[)NIi

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c.. .,

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~

NO HOD" rOR ADDITIONAL VALUES
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INCRE"ENT FREQUENCY
STORE VALUE

ADJUST HEADING TABLE START TO NEXT VIDAR

wt:"'C~~

AUD

..

YES
NO

ADJUST rAEQUENCY TABL.E &TART TO NEXT VIDAR

PAGE

17

P-50 MARK 11 ANALOG INPUT STATISTICAL TEST (D178-1)

....
....
I
N
0

671
672
673
674
675
676
677
700
701
702
7005
704
705
706
707
710
711
712
713
714
715
716

01443
01444
01445
01446
01447
01450
014'1
U1 4 '2
014,3
Cl14,4

U1455
U1456
01451
01460
01461
U1462
01463
01464
01465
01466
01467

01 0 317
01 0 06jc!
27 0 046
~4 0 047
24 1 000
J6 1 3be>
J6 0 ~5!)
J2 0 067
J7 0 Ob~
01 0 064
~7 0 O~b
oJ6 0 070
24 1 000
0002"
00001
00000
OUOOD
00000
00000

oooou

00000

~OROOM

OCR LI'4QRDG
OCR F'INCNT
~JP L.+2
JMP L.+2

NO ROOM rOR ADDITIONAL

~ALUES

"'iN

"

DiI!O
ONE
F'I NCNT
INPSAV
PRTOUT
RDGCNT
REMCNT
TQTADR

t(J? AOJS"'N
~JP RE I NiT
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~rL FINCNT
DCH PHTOUT
PJP L+2
HJP PRINT
kTN
lIl:C 20
OCT 1
OCi
UCT
UCT
OCT
OCT
OCT

RECORD SPAN CALIBRATE POINT READINGS
INJTIALIZE TABLE POINTERS
TOTAL. NUMBER OF POINTS TO BE TESTED

PAGE

18

P-50 MARK II AhALOG INPUT STATISTICAL TEST (D17B-1)

.....
.....
I

~

.....

717
720
721
722
723
724
725
726
727
730
731
732
733
734
735
736
737
740
741
742
743
744
745
746
747
750
751
752
753
754
755
756
757
760
761
762
763
764

E:.JE
THIS SUBRUUTINE PRINTS OUT THE ACCUMULATED DATA
F'ROM THE TABLES.THEN REINITIALIZES PROGRAM.
01470
01471
01472
01473
01474
01475
01476
01477
01500
01501
01502
01503
01504
01505
01506
01507
01510
01511
01512
01513
01514
01~15

{j1!)16
01~17
01~20

Ul~21
01~22

01523
01524

00000
22 o 071
J2 1 365
J1 o 064
J6 1 364
32 1 363
J7 o 254
02 o 251
')2 1 36l
37 o 252
32 o 361
10 o 254
37 o 25J
J2 1 25J
37 o 245
32 o 360
10 o 254
J7 o 25J
32 1 253
oS7 o 246
32 1 317
37 0 1)65
.)2 0 06U
11 1 317
,)7 0 2~D
J2 0 31?
11 1 363
J7 0 31 7
')2 1 31'

76,

01532

766

,)6 1 357
J~ 1 356
')2 1 31,)
')6 1 35:
16 0 251
'0 0 1.s~

01~3J

j6

015ii5
01!:126
(#1527
01~30

01:'31

....

3~4

PRINT
J
J
J

JVIDRD
J

J

PNTHD

•••

SLJ L·l
E~L CYCLES
~TL PRTOUT
HJP CARHTN
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STL VDRCNT
eM8 F'RST
E~L VDRAUR
&1'L SINGeT
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ADD VORCNT
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~NL TEMP.I
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ADD VDRCNT
STL TE"P
ENL TEMP, I
SiL BI'!'
EN:.. LI'40RUG,1
S~L. HIJGCNT

SET LOCKOUT
INITIALIZE CYCLE: COUNT
OUTPUT CARRIAGE RETURN
NUM~ER OF VIDARS BEING TESTED
SET FIRST LINE INDICATOH
NUMBER OF' POINT~/VIDAR ~EING TESTED

~AIH.wOHD,CHANNEL

Of READINGS

BIT or HEADINGS
NUMbER or READINGS AT THIS POINT

t:Ni.. u21l

SU3 LNOROG.l
SiL E"PH
ENL LHCRuG
~UB HUMTST
STL LNO~uG
VALFND ENL L"EDNG.I
k.JP OUTPUT
J
W';P 5"'AC~~
J
t:NL

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kJP OuTPuT
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k.J~

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CARFPN

NUM~ER

OF' UNUSED READING LOCA TI ONS

STARTING LOCAl ION Of NO. OF' READINGS POINTER
VALliE
F'REUUENCY

PAGE

19

P·!SO MARl( 11

....
....
I
t-:I
t-:I

767
770
771
772
773
774
775
776
777
1000
1001
1002
1003
1004
1005
1006
1007
1 0 10
1011
1012
10 13
1014
1 01 5
1016
lU17
1020
1021
1022
1023
1 0 24
1025
1026
1027
1030
1031
1032
1033
10J4
1035
10J6

A~ALOG
(J1~J4

Ul~J5

01536
01537
015.0
015.1
01542
015.3
01544
01545
01546
01547
01550
01551
01552
01553
01554
01555
U1556
01557
01560
01561
61562
"1563
01564
01565
01566
01!1i67
01570
01571
111572
01573
01574
01575
01576
01577
G1600
(11601
(J1602
{llb03

l~PUT

24
36
03
J2
oS6
oS2
36
J6
32
J6
3.2
36
oS6
J2
10
37
oS2
10
oS7

01
01
01
20
~4

J6
32
11
11

oS7
32
11
11

o

SrATISTICA~

15b

1 356
0 2!)1
1 24,
1 357
1 3"
1 354
1 356
1 246
1 357
1 355
1 354
1 364
0 245
0 35~
0 245
0 246
0 35.s
0 246
0 315
0 31J
0 O~
0 163
0 123
1 364
0 315
0 250
0 247
0 315
0 313
0 2,0
0 247
0 31,5
0 251
0 06(!

J7
"2
01
20 0 217
01 0 2~l
~7 0
J6 0

u.s

25~

"1 0 2)4

TEST (017B-1)

J"P NEXT
AORF"NO kJP SPAC':"
SI'I8 F"KST
~N~ AURE:>.I
tc"JP OUTPUT
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./
J
kJP CUT
kJP SPACt:H
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kJP OUTPUT
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"'JP

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GAIN.WORD.CHANNEL

BIT

SPAC~

(juT

kJP CA~rclN
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AUD l '

J

NEXT

CRTN

~T~

AOKE~

ENL
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OCR
OCR
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£lIT
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bIT

LREDNG
LFREIoi
hOGCNT
£J~ CHTN
JP'lP YALFND
HJP CARRH.
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L~eD"G

~lIB

Et1PTY

ADJUST READING TABLE TO NEXT POINT

or

VIDAR

sua 20De"

S!L L~EO"G
ENL LFREw
SUB et1PTY
sua

or

~OOCt\

STL LrREIoi
el'lB F"RST
(JCFt F'lNC~T
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U~t;

ADJUST FREQUENCY TABLE TO NEXT POINT

VuRC!'4T

SET FIRST LINE INDICATOR
OUTPUT FOR ALL VIOARS f"iNISHeD
p"I!'tT DATA FOR NEXT POI_T Of VIDAR
INIT lALlZe VALUE AND FREQUENCY POINTERS

VIDAR

PAGE

20

P-50 HARt< 11 ANALOG INPUT STATISTICAL TEST (017B"1)

......
......
I

J:\:)

c:.:I

lU37
1040
1041
1042
10.3
1044
1045
1046
1047
1050
1051
1052
1053
1054
1055
1056
1057
1060
1061
1062
1063
1064
1065
1066
1067
1010
1071
1072
lU73
1074
1075
1016
1077
1100
1101
1102
1103
1104
1105

(j1604
01b05
u1606
01607
Olbl0
01611
01612
01613

01b35
01636
C1637
01640
01641
01642
01643
01644
01645
1I1646
01647
01650
Cl1b51

00411
00430
00447
00466
00505
00524
0054J
00562
00000

1106

01b52

00000

(,1tI1~

U1615
01b16
Ule17
U1620
01621
01622
016(:'3
OH24
01625
(,1626
01627
01630
01631
u1632
(/lb33

01634

J2 1 36J
11 0

25~

J7
32
11
37
32
14
14
10

25J
317
253
317
253
35(:'

0
0
0
0
0
1
1
0
1
1
0
0

35l

253
354:!
14
35(:'
J1
253
32
315
11 0 25J
J7 0 31~
32 0 31~
11 0 25J
J1 0 313
~4 0 077
J6 0 255
J6 0 320
32 0 067
31 0 062
jr!4 1 070
14

oouoo
00074
ouooo
00000

ENL
SUB
STL
ENL
SUB
~TL

NIJMTST
VORCNT
TEMP
LNOHUG
TEMP
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ACC
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LREOI'4G
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ENL
J
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kJP C!..TAtj
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kTN
ADRTt3

BITAa

ADRES
tlIT
20DCK
EMPTY

lICT
OCT
OCT
\JCT
OCT
OCT
liCT

ADRTtS1
ADRTtS2
ADRhJ
ADRTtl4
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dlhtlJ
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UCT
UCT
LJEC Ni.H1VuR-1-20
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\JeT
SINGeT UCT

INITIALIZE NUMBER or READINGS POINTER

-20
SET READING POINTER FOM NEXT VIDAR
SET FREOUENeY POINTER FOR NEXT VIDAR
PRINT DATA FOR NEXT VIOAR
OUTPUT F'OR ALL VIDlRS FINISHED
CLEAR rRE~UENCY TABLE TO ZERO

PAGE

21

P-50 "ARK II
1107
1110

A~.LJG

I~PUi

SrATISTICA~

00000
00000

TE"'P

TEST (0178-1>

litT

VOK(;'H uC;

PAGE

22

P-50

I1A~f(

II ANALOG INPUT STATISTICAL TEST (017B-l)

1111
1112
1113

l:.JE

111~

1115
1116
1117
1120
1121
1122
1123
112~

1125
1126
1127
1130
1131
1132

~

~

I
~

CJ1

1133
1134
11.35
lU()

I
I
I
I

U1655
01656
01657
01660
01661
01662
01663
il1f\64
01665
01066
iJ1 0 67
01670
01671
01f-·72
u1t>73
Dlt> 74
01b7:;
Ulb76

00000
36 1 3':>1
J2 0 ;S06

J7
J2
J7
.s2
J7
J2
J7
J2
J7
32

1 350
1 347
1 3~6
0 307
1 34~
1 344
1 34,)
0 310
1 34l
1 3~1
J7 1. 340
J2 0 311
.s7 1 337
32 1 336
J7 1 33~
J2 0 llt
J7 0 .51.)
j2 0 314
37 0 317
32 0 316
J7 0 315
l4 1 255

1137
114J
1141
1142
1143
1144
1145
1146
1147
1150
1151
1152
1153
1154
1155
1156

01706
01707
01710
01711
01712
01713

1157

U1714

02605

1160

01715

0260~

'JH77

01,700
u1701
01702
01703
01704
01705

34 1 067
34 1 050
34 1 031
J" 1 Oll

07107
07107

RElhlT

"
J
J

...

TIMEI'(
DLE 4-NUl1VO~·~
EhL AURF"4
STL LADR4
EhL t:llHJl4
~.JP

~'!L

J

THIS SUBROUTINE GOES TO Ti"ER,TH~N REINITIALIZES
PROGRAI1 TO START READIN~ FIRST POINT ON EACH YIDAR.
T IHE DELAY
INITIALIZE OUTPUT COI1MANDS

L~DR~-l

ADRF' Xl
STL LAllR')
EhL b I TF X3
STL L~ORJ-l
E~L ALlRF1l2
S:L L4DR~
ENL EiITrx2
STL L~Dk~-l
ENL ADwF Xl
STL LAOK\.
ENL ~lrF'Xl
~T~ L4JiU-l
t.: ,_ F'~~;IX
E~L

J
J

"

J

J
J

./
./
J

~';'L.

~r;H:1ooI

ENL NO~FIX
STL i,.NQRUG
E~L ROGF" P(
STL L~EDNIi
kTN

OLE 4-NUI1VDR
OUT ADRTtI~·l,1
OUT AURTtt,5·1,1
UUT AOiH~l+l. I
(lUi AORTtfl+1.1
UCT fRQN~Y
UCT FRQNCY
NORrIX uc~ NORUIj
LRfUNG ucr NOHDl;
ADRrl(4
ADRfJ(J
ADRFX2
ADRF Xl
rRQFIX
L.rREi.l

INITIALIZE LJCATION

or

~Mc.UENCY

TABLE

INITIALIZE V1CA'nON IJF NUMBER OF READINGS
INITIALIZE LUCATION OF VALUE TABL.E

PAGE

23

P.50 MARK II AhAlOG INPUT STATISTICAL TEST (0178-1)
1161

11'2

01716
U1117

04746
0474&

ROGFIX ~CT NEOING
LNOhDG OCT REOI~G

PAGE
24
P·50 "ARK I I ANALOG INPUT STATISTICAL TEST (D17tt-1)

........
I

t-:>

-;J

1163
1164
1165
1166
1167
1170
1171
1172
1173
1174
117S
1.176
1177
1200
l~Ol

E:JE
THIS SUBROUTINE CLEARS ALL ENTRIES IN fREQUENCY
TA~LE,VA~UE TABLE,NO. READINGS TABLE TO ZERO.
"1720
01721
017~2
017~J
u17~4

017l,
01726
01717
01730
01731
017.52

00000
32 1 3;)4
J7 1 31J

CLUB
JCLR

ENL If:Hu
~TL

L.FHI::U,I

,s2 0
1.S 1
~o 0
U1 0
24 0
,s2 0
057 0

310

JI'1P

CL.ri

312

I:NL

F~aF'lX

J1,s

l4 1

3~O

STL LFRE:1oI
kTN

I:NL

31$

3JJ

J

LF'HI:U

I:Ut( d-iNTo

J~7

tJP L+j

31J

DCH LF'HE;w

PAGE

25

P-50 "ARK I 1 AhAL.OG INPUT STATISTICAL. TEST (0178-1)

tJE

111!02

.....

,

~

~

00

1.11733
01734
01735
01736
01737
01740
01741
01742
01743
01744
01745
U1746
01747
01750
01751
01752
01753
01754
U1755
01756
01757
01760
01761
01762
01763
01764
01765
01766

OC!47J

.HD

O~467

.. r
EOR ALONi:S
ADD SPAN'i
STL SPAN~
ENL SAVEl
t'JP L+2
SUB 1)
EUR ALONES
ADD SPANl
STL SPAN1
DCR SPNCNT
~JP

Lt2

MiN

"

E~~

SET SPAN ADJUST INDICATOR
ADD READINGS TO SPAN CHECK WORD

6)

ADJUST SPAN EVERY 8 READINGS

PAcae

27

P-SCi MARK J I ANALOG

....
....
I
w
0

1253
lit54
1255
1256
1257
1260
1261
1262
1263
1264
1265
1266
llt67
1270
1271
1272
1273
127.
1275
1276
1277
1.100
1301
1302
1';03
1304
1.s05
1.106
1301
1310
1311
1312
1313
1314
1.115
1316
1317
1320
1.521
1322

02U41
"~"42

"2"43
02044
,,2045
02046
02U47
u2050
"2051
02u52
Oi053
u~05.

0~U55

021156
021157
021.160
02061
02U62
02063
621.164
lI2065
02.,66
"21i67
02070
02"71
02072
112U73
02074
"2075
02U16
02077

ouoo
02101

02102
0210l
02104
O~105

02106

I~PUT

J7 0
jl!4 0

STATISTICAL

l~O

S"'I..

SPNCNT

OLE 4-NU"VDRe7
"~H SPAN4
H:)H SPUI4
HSH S"AN4
HSH SPA~4
HSH SPAN4
lJP l·2
eMS L·2
hSH S"'ANJ
HSH SPANJ

16 0 1'~
20 0 0'1
O~~

16 0 1;05

16
16
16
16

(0178-1)

6THCHG JMP L+1

04~

16 0 1~2
16 0 1!»2
16 0 l , l
16 0 ~5C!
02 0

~EST

0 15J
0 l~J
0 15J

H~H

S~A~J

HS~

SPAhJ
SPANJ
L·2
SIND
SPANit

0 l~J
il!O 0 060
02 0 1~:'
16 0 1'<
16 0 :.5 ft
16 0 154

kSH
lJP
eMs
HSH
kSH
HS~

SPA~~

16
16
itO
02
16
16
16
16
16
itO
02
16

t(~H

SPAN~

~7
~4

0 154
0 1~"
0 Ob:'

0 15~
0 15'

Jic~H

155
076
151
1;1
10:.

SPAh~

SPA~1

HSH SPAN1

0
0
0
0
0 121

l.JP l+2

:"8

SIND
kSIi SIND
J.I.:p L+2

,JI'IP

L1
• •__
j;

32 0 152
10 0 1~7
12 0 17U
J1 0 1!)7
.12 0 15.5

DURING IN J T UL UATION

CHECK rOR SPAN ADJUST ON EACH YIOAR

hSH SPAN~
.:.JP L·2
e"it SIND
HSH SPANl
kSH SPAN1
k:iH SPA~l

0 1!»1
0 155
0 155
0

REP~ACEABlE

J

ENL
ADD
BAND
~~L

I:NL

SOIJ~

4-NUMVUR ...
SPAN ..
SPllfRU4
177)
SPWRU4
SPANJ

CHECK SPAN ADJUST INDICATOR
NO SPAN ADJUSTMENT NEEDED
"ODlry SPAN MOROS

PAGE

28

P-50 "ARK II

1323

021U7

132~

02110

1J25
1326
1327
1330
1331
1332
1333
133~

1 3 35
1336
1337
13~0

......
......
I

c"
......

A~AlOG

13·1
1342
1343
1J~~

1345
1346
1347
1350
1.551
1352
1353
1J54
1J55
1356
1357
lJ60
1361

INPU7 STATISTICAL -EST (0178·1)
160

02111
U2112
02113
(12114
02115

10 0
12 0
,j7 0
32 0
10 0
12 0
3] 0

S9!..

0211~

101

S~Io/RI.J2

32 0

15~

02117
02120
U2121

~N:"

10 0 16l

SPA~l

Ol~C!2

J2 0

02123
02124
u2125
02126
02127
lJ2lJO
U2131
02132
OlU3

02134
02135
02136
02137
02140
02141
02142

02143

1362

021 1 4

1363

02145

1~4

12 C 170

,n 0 16l
1~7

JSOUi

J7 0 152
~7 0 154
37 0 15~

1 DOe
36 1 !b-;
i!4 0 U.s

J

~4

32 C 157
36 l lb4
36 1 16~
32 0 loU
36 1 1~~
36 1 16~
j2 0 161
36 •• 104
.56 • l!>j
j2 0 102

ADD SPIo/RU1
BAND 177)
~ -,
SOWRUl
.
EN~ 0)
u:"E 4·NUI'IVDR
s· . SPAN"
~:L SPAHJ
~'7"!. SPAN2
S~;. SPAN1
ENL SPNPHT
I.';~
L"2

-

'-

37 0 !5S

32 1 a6
20 0 1... "1
w.

SPAN~

AUD SPWRU2
8AND 177)

170

k-~

J

CARHTN
7'!'I-ICHG J!'!~ !..+1
D' ;: 4-NU"'I"DR*3
~N:' SPW RU4
~..:P

--

J
J

I.(Jo

ou:pur

t'I.;P
EN~

SPACER
SPwRU3

RJ;»

OU~?UT

k':P

SPA!;t:R

ENL SFWKU2
kJP QU7Pur
~"IF

SPAC~H

• !64

EN~

SP-.HU1

H.J P

OUTP~T

000

~TN

1364

02146

~6

U2147

~4

1366
136 7
l,J70

"2150
02151

OOOOG

021;)2

ooooe

1371

tN~

161

1365

1371

ADD SPWRUJ
8AND 177)
~r:.. SPwRl)3

17!l
1bU

~

·...

J7"!?!

..

'..)
AL.ONES ,-37777
:.>:.SINU
lJ; .: 4-NUMVDR

SPAN4

--

ue

T

DO NOT PRINT SPAN SETTINGS
REPL.ACEABL.E DURING J NIT 1AL. J ZA TJ ON
PHINT SPAN SETTINGS

PAGE

29

P-50 "ARK 1 1 A"'UOG
1J13
1J14
1J15
1J16
1J17
1 4 00
1401
140l
1 4 03

"2153
021,4
l/~155

O.!156

It~PUT

STATISTICAL

~EST

SPAt.3

UC':'

SPA"'~

UC'!'

00000
OOOOu
00000
00000

SPA,.,l lICT
SP"'Cl>4 T (.IC'!'

00000
00000
OilJOiJ
OUOOO

SP .. kD4
SPWkuJ
SPIoIkl)2
SPWkD!

LlL~

02157
l/~160

O~lbl

l/4!16C!

(lC·
OCT
lICT

lie·

(0178-1)

4-NUI1VDR

PAGE

30

P-50 "ARK 1:1 ANALOG INPUT STATISTICAL TEST (D178-1)
1 4 04

......

......
I

C.:I
C.:I

I:JE

02163
02164
02165
021b6
02167
02170
02171
U2172
02173
02174
02175
l/2176
02177

02451
0242)
02461
00410
00000
00177
00010
007~b

0075j
0075<4
00001
0075J
00407

... HO
.-HD
.. HO
NHO
,.HD
"HD
.. HO
"HO
.. HO
IIII( D
.HD
wHO
WHO

;'A!i~

'::'l

P-5D '14 Rpc; r r

....
....

..

....

Col)

1405
1406
1407
1410
1411
1412
1413
1414
1 4 15
1 4 16
1417
1420
1421
1422
1423
1424
1425
1426
1427
1430
1431
1432

"~"LOG

;,pu·

~TATISTICAL

Ol4DO

·ES T C017a-l>
LJw::; OR 1Gl1hl024

TI-I15 5UttROUTINE IS ENTE~ED BETWEEN SUCCESSIVE
Of THE LIST or POINTS. IT DELAYS
CYCTIM-1/10 SECOND.THEN RETUHNS.

R~ADINGS

02400
00000
02401 ;)2 1 115
02402 ;!O o 01J
02403 37 o 017
02404 .32 o 114
02405 37 o 01b
02406 32 o 016
02407 37 o 01S
02 4 10 01 o 015
02411 27 o 007
02412 01 o 017
02413 27 o 005
U2414 24 1 000
02415
O~416

02417

00000
0764c)
00000

TIMER

•••

J

1:: Nt.
l.JP

CYCTl",
NOTD

~~L

T2

J

tNt. 4000)
STI. Tl
tNI. T1
~rL DCNT
tieR DCNT
PJP 1.-1
OCR T2
PJP '!'NTI-I

TNTH

NOTD

fH~

DCNT
11
T2

tlEe 4000

OCT
OCT

1/10 SECOND DELA'

PAGE

32

P-50 "ARt( J I

A~ALOG

! IIjP\.'':'

~TATISTICAL

-t::Si

(U17~-ll

r: J E:

1433
1~34

1435
14J6
1437
1440
1441
1442
1 4 43
1444
1445
1446
1447
145·0
1451
145·2
I-'
I-'

I

c,..,
C.11

THI!:> SUtlkOUTINE OUTPU"S 1
DOCUMENT DEVICE
02420
02421
02 lt n

~3

1I2"~3

U1

:JU
:1-'

U,,"2"

..

t!."

1

Jt:d

(i

INikTN

CLEAR LOCKOUT
iliA IT rOk INTERRU~l

PC

f'('N

THIS SU8RUUTI~E OUTPUTS THt: j LC"Al. 01<81TS
THE ACCU"ULATOR TO THE DU:" ..I"~
DEvICE BY
USING OUT •••
U~"25

0242b

145·~

ucl+n
04!4130

Ol4J1

Ol432
021135
02434
U243~

024J6

OOOllU

J7
J2
J7
14

\,'

0 074

!>

~NL

0 077
14 0 0'"

.)2 0 on
12 0 OlL!
10 C 07:;
.)7 0 Q16

14e,5

U~4H

14~16

O~442

J2 1
~6 0
14 0
14 0

14ei7
1470
14n
14j'2

Ol443
Ol444

14 0 077
J~ 0 0 7 7

02 .. 45

12 0 07i!.
01 0 074
27 0 0,54
2 .. 1 02:'

02446
OI:!"47
1124:'0

...

:';L. UUTSH

I,

lI;2440

U~431

DUTF-UT

0 J"?7
0 011

14~,4

14;'"

.

LlC~

,J

TO THE

, ,

IJUT LJuC(Jur
CLJ L+1

O~

145,4
145;5
145,6
145;7
14e,o
14e,l
1462
14e,3

14j'~

OUi

DUelOO

J4 0 IlUu

CHA~ACTE~

07e.
Ot!.1J

077
077

14j'5
14/'6
14n
15()0
l~Ol

U2"51

ooouu

1~1)2

0~452

32 C 0:'0

OTLOP

T

I

I~

LSH
LS!'I
ENL.
AND
ADD
STL
ENl
kJP
LSH
lSH

lJ5

eNT
UU'!'SAV
OUT SAY
OUTSAV
2tH Ts
LCODt:

riND CHARACTER OUTPUT

(' u lit

LuOKU~

LOOKUP, I
(JUT
QUTSH
OUTSH
LSH OUTSAV
I:NL uUTS.V
AND 3t:iITS

OUTPUT CHARACTEH

DCR eNT
f'.Jp

kTItJ

.

arlO'"

SPACER , ,
I:N:.. u.5

THl!:> SUBRUUTlNE OUTPUTS ;s SPI.(~tS TO THE
DOCUMENT DEVICE BY USING OU·, "

PAGE

33

peSO "ARK 11 AhALOG INPUT STATISTICAL ;fST ( 0178-1>
1~03

1504
1505
1506
1507
1510
1511
1512
1513
1514
1515
1516

02453
"24,4
02455
02456
02457
02460

J7 0 074

::,TL

J2 0 111

t:NL

SPAC~

J6 0
01 0
"'-7 0
l4 1

Olll

~JP

OUT

OH
05.5

OCR C~T
fJP L-3

051

~TH

02461
02462
U2463

00000
32 o 111.1
.16 o OlU

U~464

.12 0 11l
.16 0 O~O
24 1 061

CARHTN , ,
ENL
ttJP
OLE
E:NL
HJP
NTH

1~17

....
.....
I
c;.,)
Q)

1 5 20
1521
1522
1523
1524
1525
1526
1527
1!J30
1531
1532
1533
1534
15')5
1!J36

02465
02466
02467
02470
02471
02412
02473
U2474
02475
0~476

02417

00000
000 OJ
00005
Ol470
00007
0~516

00000
Ol50U
01l01l0
00000

1~42

1543
1544
1545
1546
1S47
1550
1551
15~4!

1553
1!)54
1!)5S

02~00

U2501
02502
u2503
0250·
02!)05
Ul500

03000
1.5040
ll100
005140
1.5201.1
0.5241)
03300

lIi=>07

1.53~1l

O~:'lO

106411
:l:lOO

U2;,11

C~T

PICK UP CHARACTER OUTPUT CODE
OUTPUT CHARACTEH

THIS SU8ROUTINE OUTPUTS A CARRIAGE RETURN
AND LI~E fEED TO THE DOCUMENT DEVICE,

.

CARRGE
OUT
1-ASH-2
Lf

our

UCT 0
lIec 3
(JEe 5
D5
28ITS &YN D3
lIlTS OCT 7
IGNTH OCT TAIENO
OCT
CHT
LCOOE OCT CODE
LOOKUP UCT
OUTSAV OCT
DLE .5-ASH
CAD
HO 1,l.J.l,5
OLE 1-AS"-11
CODE
CAD O-O.ChO,O
CAD 0.2,6,1,0
CAD 0.2,6.2,0
CAU 0,0.6.3,0
CAD 0.2.6.4,0
CAD 0,0.6,5,0
CAD 0,Or6,6,0
CAu 0.2,6,7,0
CAtiHGE ell!) 0.2.1.5.0
SPACE !,AD 0.2,4.0,0

CARRIAGE RETURN
LINE fEED

ZERO
03

SELECTRIC CODE TAIILE
ASR CODE TABLE

PAGE

34

P-50 "ARK II AhALOG INPUT STATISTICAL ;eS! (0118-1)
1556
1557

Ol~12

0050U

()~513

00000
07640
00406

O~515

t.)
~

tAD 0.0,1.2,0
lai:~

"2~14

....
....I

I..F'

""0
.. NO

""D

PAGE

35

P-50 "ARK J J At-.ALOG INPUT STATISTICAL TEST ( 0178-1>
1560
1561
1562
1563
1564
1565

.....
.....I
c,.)

OD

TA~ENO

02~16

00000
0~60::;

04746
07107
00000

k~T

NUI1VUlh14

ueT
NORDG ~YN L-1
REDING SYN 14·20·NU"VDH+NORDG+l
F'RONCY ~YN 1 4 ·ZU·NUMVDH+REDJNG+l
END

ANALOG INPUT SCANNER TEST (0188)
I.

Purpose of Test
To read a variable number of analog points on up to four vldars and to print each
input point which results in an out-of-Umits reading.

II.

Description of Test
The program reads an analog point on each vidar, then checks to see if the values
are within the allowed tolerance. If a value Is out-of-limits, a message In the
following format will be printed on the ASR set, and the program continues.
READING IS

aaaaa

where

aaaaa
ddddd

bbcc

AT POINT

=
=

bbcc

ddddd

actual reading
analog point
bb is the word
cc is the channel
ddddd is the bit (one bit set).

Bits 0-13 of each word specified at initialization are checked. After all points
have been read CYCLES (specified at initialization) times, the following message
is printed on the ASR set, and the program restarts.
ANALOG SCANNER TEST COMPLETE
III.

Description of Operation
A.

R.

Read in the binary tape of the Analog Scanner Test using the bootstrapped
binary loader.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

USing the probe, load the X-Register with the starting location of the
binary loader (76028, 176028, 276028, or 376028); depress the Start
button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape reader.

5.

Turn on reader.

6.

Depress the Start button.

Enter the test parameters.
1.

Put machine in WRITE mode; depress the Master Ciear button.

2.

Using the probe, load the S-Register with the parameter location.

12-1

3. Using the probe, load the X-Register with the parameter constant; depress the Start button.
4.

Repeat 2 and 3 until all the following parameters have been entered.
Preset

Location
AN LINT

2

6012 8

Analog conversion complete interrupt
location
NUMTST
4
No. vidars to be tested
ASRCHN
0
ASR output channel
ASRINT
118 ASR output complete interrupt location
MAXCHN
778 Last output channel to be used
SPNSEL 201008 Span select and gain
SPNRST
200 8 Span reset
VALUE
0
Desired bit value of points read
DEV
5
Allowable deviation from value
N~PTS
3210 Maximum no. words to be read on any
vidar
CYCLES
1008 No. cycles before end message

7177 8
72008-72378

CTR1
VIDARI

0
0

7240 8
72418-73008
73018
73028-73418
7342 8
73438-74028

CTR2
VIDAR2
CTR3
VIDAR3
CTR4
VIDAR4

0

6 000 8
60018
6002 8
60038
60048
60058
6006 8
60078
6010 8
60118

C.

D.
VI.

Description

0
0

0
0
0

No. words to be read on vidar
Words to be read on vidar 1
Word no. in bits 11-6
No. words to be read on vidar
Words to be read on vidar 2
No. words to be read on vidar
Words to be read on vidar 3
No. words to be read on vidar
Words to be read on vidar 4

2
3
4

Start the test.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe, load the X-Register with the starting location of the
test (60128); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button; depress
the Start button.

The test runs continuously, scanning each point and printing out-of-ltmits
errors.

Storage
The program uses 14038 locations. (60008-74028)

V.

1

Run Time
Recommended run time: 1/2 hour.

12-2

PAGE

~

P-50 MARK II ANALOG INPUT SCANNER TEST (D189)
1

2
J

PROGHAM TITLE: P-50 MARK 11 ANALOG ,-,PUT SCANNER TEST (D188,
DATEI MARCH

1,19~6

~

5

6

SOURCE COMPUTER I P-500. SYSTEMS ~A9.
08JECT COMPUTERI P-50 MARK 11 SEHIES

W~SAP

5D/~OD

7

10

PROGNAMMENI C.YETTER

11
12

AdST~ACTI

13

SEE UESCRIPTION OF SAME CODE NUM8ER
FROM C,S.D. CHIEF DRAFTSMAN.

AYAILA~LE

1~

15
16
~

~

I

~

CODINGI NOT STNDRDl - REYlSlUN OF
PRIOR TO STNDRD1.

D~8A

PROGRAM"ED ORIGINALLY

PAQE

2

'-50 "ARK II ANALOG INPUT SCANNER TEST (0188)
17
20
21
22

23
24
25
26
27
30
31
32
33

EJE ASSEMBLY PARAMETERS
THE

OOOOl
00004
00000
00011

06000
00016
00036
D0056
00076

AT HUN TIME
INTERRUPT LOCATION
MAXIMUM NO. VIOARS TO ~E TESTED
DOCUMENT DeviCE OUTPUT CHANNEL
DOCUMENT DEVICE OUTPUT CO"~LETE INTERRUPT LOCATION
THE FOLLOWING MAY NOT BE CHANGED EXCEPT 8T ~E,SSEMBLY
PROGRAM ORIGIN
ORIGIN8EQU 6000
VDRC H18EQU 16
SPAN AND GAIN AND INPUT CHANNEL rOR VIDlR 1
VDRCH28EQU 36
SPAN AND GAIN AND INPUT CHANN~L FOR VIDA" 2
VDRCHJ8EQU 56
SPAN AND GAIN AND INPUT CHANNEL FDA VIDAR 3
VDRCH48EQU 76
SPAN AND GAIN AND INPUT CHANNEL FOR VIDA" ..
ANINT t:UU 2
NUMVOR HIU 4
Docour eQu 0
DOCINT8EQU 11

fO~LO~lNG

ANA~O~

MAY BE

CONVER~ION

CHAN~EU

CO"~LETE

PAGE

3

P-50 MARK II
,34
35
36
37
40
41
42
43
44
45
46
47
50
51
52

.....
~

I

c.n

A~ALOG

INPUT SCANNER TEST (D18B)
E:JE
UNL

{J6000
UbOOl
06002
06003
06004
06005
U6006
06007
06010
06011
06012

06000

O~G

00002
00004
00000
00011
00077
20100
00200
00000
00005
00040
00100

ANLINT OCT
OCT
ASRCHN OCT
ASRINT OCT
MAXCHN OCT
SPNSEL OCT
SPNRST OCT
VALUE OCT
OCT
DEV
NOPTS DEC
CYCLES OCT
~UMTST

ORIGIN
THE rOLLOWING A~E INPUT~ AT HUN TIME
A1>1 I N1 ANALOG INPUT CONVERSION CO"PLE:TE INTERRUPT LOC.lTIUN
NUMVD~ NUM~E~ or VIDARS TO BE TESTED
DOCOUT A5~ OUTPUT CHANNEL
DOCl~T A~R OUTPUT CO"PLETE I~TERRUPT LOCATION
77
LAST OUTPUT CHANNEL TO dE USED
2010U SPA~ SELECT AND GAIN
200
S~AN RESET
DESIRED BIT VALUE or POINTS READ
5
ALLOWABLE DEVIATION rHOM VALUE
32
MAXIMUM NO, WORDS TO ~E READ ON ANY VIOAR
100
NO, CYCLES BE,ORE PRINTOUT 0, END MESSAGE

PAGE

4-

P-50 MARK 11 ANALOG INPUT SCANNER TEST (0188)

~

t.)

I
CI)

53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
100
101
102
103
104

105

106

E:JE
SE:T

06013
06014
06015
06016
06017
06020
06021
06022
06023
06024
06025
06026
06027
060,)0
06031
060,)2
06033
06034
060ol5
(16036
06037
06040

J7 1

31~

01 0
"l7 0
23 0
J2 0
10 0
oS7 0
13 0
~7 1
')2 0
J7 1
~2 0
10 0
J7 0
13 0
J7 1
J2 0
J7 1

31l
016

06041
06042
06043

J2 0 002
13 0 317
J7 1 37.1

22
32
J7
oS2

0 01.1
0 377
0 311
0 2~4

021

000
376
32l

320
000
37!)
3;U

OOJ

376
3~2

320
OO~

374
32it

S~J

L·1

8ENL 100)
~TL LSTINT
ENL CLJOl
STI. I.STINT,J
DCR I.STINT
PJP 1.-2
CI.J 1.·1
SET! NT ENL ANI.l NT
ADD 65)
J
STL TEMP
=UR RJPX
~1~ AHLINT,I
J
i::NL INTRTN)
~lL TEMP,I
~N~ ASIUNT
AOD 6;)
~TI. TEMP
EUR RJPX
STL ,SRINT,l
J
ENL ASRIN)
51L TEMP,1
J

S~T
SET~HN

J

ENL ASRCHN
EOR OUTX
STL OASR

INTERRUPT~

SET LOCKOUT
STOHE IGNORE INTEHRUPTS IN ALL LOCATIONS

CLEAR LOCKOUT
STOICE ANAI.OG INTERRUPT

SlOHE ASR

ASR CHANNEL

INTERHU~T

PAGE

5

P-50 "ARK II ANAI.OG INPUT SCANNER TEST (0188)

~

~

I

~

107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130

EJE
06044
06045
06046
06047
06050
U6051
06052
06053
06054
06055
06056
06057
06060
06061
06062
06063

32 0 001

13 0 372
10 0 371
10 0 370
12 0 367
10 0 366
J7 0 072
J2 0 001
13 0 31l
10 0 371
14 1 376
14 1 376
10 0 365
12 0 367
10 0 366
37 0 115

SETJP1P t:NI.
J
8EOR
J
ADD
,J
ADD
J
SAND
J
8ADD
STI.
ENL
SEOR
ADD
LSH
LSH
J
ADD
8AND
SADD
STI.

NU"TST
37777)
NU"VOR)
GSPN)

SET JUP1PS
IN PRETEST

377)

24000)
GSPN
NU"T~T

37777)
NU"VDR)
ACC

Ace

OUT1NT)
377)
24000)
OUTINT

IN OUTlNT

PAGE

6

P-50 MARK II

....

~

I
00

131
132
133
134
135
136
137
140
141
142
143
144
145
146
141
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177
il!00

ANA~OG

INPUT SCANNER TEST (018B)
EJE
PRETEST:

06064
06065
06066
06067
06070
06071
06072
06073
06074
06075
06076

J2 0
.U 0
J2 0
01 1
l.7 0
J2 0
l.4 0
J4 0
J4 0
J4 0
J4 0

06077
06100
06101
06102
06103
06104
06105
06106
06107
Ob110
06111
06112
06113
06114

J6
02
03
J2
J7
32
J7
J2
11

06115
06116
06117
061~0

"6121
061Z2
061Z3
061Z4
061Z5
06126
06121

1
0
0
0
0
0
0
0
0
11 0
J7 0
32 0
10 0
J7 0
~4

006
016
364
376
066
OO~

072
076
056
036
016
363
250
240
011
251
01l.

24;
007
010
362
311
007
010
247

0 115

30 0
"7 0
32 0
.t4 1
30 0
37 0
32 0
.54 1
JO 0
J7 0

076
313
2~l
30~

0,6
314
Z22
306
OJ!»
31~

PRETST E;NL SPNRST
OA
OUT VDRCHl
J
ENL 100)
OCR ACC
PJP L-l
ENL SPNSt:L
GSPN
JMP L·l
OB
UUT VDRCH4
OUT VDRCHJ
OC
OUT VORCH2
00
UUT VDRCHl
OE
JAHITST HJP INITL.
SETUP CMB IGNOHE
S"B END
ENL NOPTS
STL INDEX
ENL. CVCL.eS
STL. CVCNT
ENL. VALUt:
SUB DEV
J
SUB 1)
STL L.OLI"
ENL VALUt:
ADD DEy
STL HILIM
OUTINT J"P
INT
U
STL
I:NL.
UUT
INT
IB
STL
ENL.
OUT
INT
IC
STL.

L.·l
VDRCH"
NVAL.4

BIT

,-QC4.1
VDRCHJ
NVAL.)

BIT

LOC3.1
VDRCH2
NVALl.

OUTPUT GAIN AND

~PAN

~E~ECT

REPLACEABLE DURlNG INITIALIZATION

BEGIN TEST
INITIALIZE
SET ~IRST READING INDICATOR
CLEAR END OF CYCLE INDICATOR
STORE NUMBER or POINTS TO BE READ

L.OW L.IMIT
HIGH L.IMIT
OUTPUT - INPUT ROUTINE:
REPLACEABL.E DURING INITIALIZATION

PAGE

7

P-50 "1ARK I 1
201
202
203
204
i05
i06
207
210

A~AL.OG

06130
1161.l1
06132
06133
U6l34
06135
061.l6
06l.l7

INPUT SCANNER TEST \0188)
J2
34
30
37
32
34
.52

0 22l
1 307
0 016
0 316
0 22l
1 310
0 361
.I" 0 016

ID

ENL. BIT
OUT L.OC2,1
INT YORCH1
STL N~ALl

itHL BIT
UUT LCC\,I
JTRIGER8ENL 4GO)

CUT VDReH1

~'QE

8

D·50 MARK 11 ANALOG INPUT SCANNER TEST (0188)
211
212
l13

214
215
~16

l17
220
221
l22

223
224
225
226
227
~30

......

t-:>
I

......
0

231
232
233
234
235
236
237
~40

241
242
~43

244
~45

246
247
250
251
252
253
254
2'5
256
it57
it60

fJE
06140
06141
06142
06143
"6144
(/6145
06146
06147
06150
"61S1
06152
061;3
"'15.
06155
06156
OCt1,7
06160
06161
06162
06163
U6164
06165
06166
U6167
06170
06171
06172
06173
OCt17.
06175
06176
06177
06200
06201

CHECK rOR READING WITHIN LIMITS
"2
27
"2
~7

~2

~7
~2

~7

~2

11
27
24
.52

11
~7

01
01
01
27

0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0

0
0
0

.)2 0

"7 0
,52 0
~7 0

2~O

162
360
3~3
3~7

252
001
244
323
311
153
32.5
323
247
32J
252
323
244
147
310
256
307
2~'

0 306
37 0 2:;4
~2

06203

.52 0 305
0 253
~2 0 222
~7 0 22.5
03 0 2~0
~2 0 246
27 0 207
24 1 3~6
01 0 245
27 0 20.1
02 0 246

06204

.12 0 221

06~02

~7

CKLI" ENL
PJP
fNL
STL
./
ENL
STL
ENL
STL
LIMIT fNL
SUB
PJP
.IMP
ENL
SU8
PJP
DCRLI" OCR
Iij:R
OCR

IGNOHE
ENTLUC
NVAL1)
VAL
I NTPTl )
INT
NU"TlIiT
COUNT
VAL. 1
LOLIPI
L·2
LIMEHR
VAL.I
HILI"
LIMEMR
INT

ENTLOC ENL
STL
ENL
Sll
ENL
STL
fNl
STL
ENL
!aTL
Sft8
eNL
PJP
./
JftP
C8A
DCR

LOC1
I NTPTl
LOC2
INTPTl
LOC3
INTPT3
lOC4
INTPT4

"

IGNORE THESE READINGS

CHECK READING

DECREMENT COUNTERS TO CHECK NEXT VIDAR

VAL.

COUNT

pjp LI"IT

STONE WORD.CHANNEl.HIT FOR llMERR

BIT

BITSV
IGNOME
END
ENDRT
INCAPIT
CYCNT
~JP AiC
Cft8 END

INCMEMENT POINT

NAIT FOM INTENAUPT
A8C

ENL AFLAW

ADDNESS~S

PAGE

9

P-50 MARK I 1

~

N
I
~
~

il!61
262
263
26"
265
l66
267
270
271
272
27J
274
275
276
277
JOO
301
l02
303
304
305
J06
J07
310
,s11
312
J13
J1"
315
316
J17

320
J21

322
J23
324
J25
326
321

oSlO

A~ALOG

INPUT SCANNER TEST (0188)

116205
06206
06207

27 0 20.5
02 0 221
lC 0 114

06210
06211
06212
06213

OJ 0 246
J6 1 3~5
0622'
24 o 076

(.16214
06215
116216
06217
"6220
06221
116222
06223
06224
06225
(.16243
U6244
116245
06246
06~47

" .. 250
U6251
062'2
U6253
06254
06255
06256
06257
06264
06265
(16266
06267
06271
(.16276
06277

PJP L-l
CMB U'"LAu
JP1P OllTINT
E~D

EMDRT

5MB E~D
HJP OTRCU
OCT COMPLT
JMP A/IIITST

00000
o 321
o 221
o 321
1 214

INTRlN

•••

00000
00001
00000
23 1 000
02145
01417
00000
00000
20000
00000
00000
00000
00000
00000
00000
00000
00000

AFLAG
SIT
SITSV
CLJOI
COMPLT

U6
03
05
23

0'12~

06060
00000
00000
00000
0216.5

OUOOO
00000

J

ROUTINE

A'ULOu INTERRUPT RETUHN
SDR SAVE
5MB AF'"LAG
~OR SAVE
CLJ INTRTN.l

COUNT
CYCNT
END
HILI"
IGNORE
INDEX
INT
INTPT4
INTPT3
INTPT2
INTPTl
LIMFOR
H
HI
LOA
HIX
LOX

OCT
OCT
UCT
CLJ
BCD
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
HCD
UCT
OCT
OCT
OCT
tlCD
OCT
OCT

1

•1
14ANALOG SCANNER TEST COMPLETE
1417

20000

05READING IS
6060
,606U
05AT POI .. T
,6060

X

X

PAGE
P·5~

10

"ARK 11
331
JJ2
333
3J4
JJ5
336
3J7
J40
341
342
343
0544
345
346
347
350
351
352

~

t-:)

I
~

t-:)

A~ALOG

CJ6301
06302
U6303
06305
06306
06307
06310
06311
06312
06313
06314
06315
06316
06317
06320

06311
063~2

063~3

INPUT SCANNER TEST (D18t:n
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
34 o 000
36 1 000
00000
00000
00000

HHB
HIS

OCT
OCT
OCT ,1477
LOB
LOC.
OCT
UCT
LOC3
UCT
LOC2
OCT
LOCl
LOLl" OCT
LSTINT UCT
NVAL4 OCT
NVALJ UCT
NVA~2
UCT
NVAL,l OCT
OUT
DUlX
kJP , I
RJPX
OCT
SAVE
TEMP
UCT
VAL
UCT

PAGE

11

P-50 MARl( 11 ANALOG INPUT SCANNER TEST (0188)
J53

EJE

J5~

~

~

I
~

c,.,

355
3;6
357
360
361
362
363
364
365
J66
367
370
371
J72
313
374
315
376
371
400

0632~

06325
06326
06327
06330
06331
06332
06333
06334
06335
06336
06337
06340
06341
06342
06343
06344
06345
06346
06347
06350
06351
"6352
06353
06354
06355
"6356
06357
(16360
&16361
06362
06363
06364
U6365
1»6366
06361
06370
U6371

J2
J6
J7
J6
J7
J2
14

14
12
10

J7
32
36
J7
J6
J7
J2
J6
J7
J6

1 32J
1 35~
0 267
1 353
0 266
0 3~1
1 316
1 376
0 35l
0 3,1
0 265
1 2,2
1 354
0 277
1 353
0 276
0 223
1 354
0 JOJ
1 353
24377
06000
00003
0660J
06510
07000
06~1l

06256
06316
00400
00001
065JO
00144
0611'
24000
00371
0607l
00004

LIMIT ERROR
Ll"ERR ENL VAL. 1
J
HJP CNVTA
::tTL LOA
J
HJP CNVTti
STL HI
~NL SAVE
LSH Ace
LSH Aee
J
AND 3)
J
BAOD 6000)
STL H
~NL PH. I
HJP CNVTA
STL LOX
HJP CNVTti
STL. HJX
ENL BUSv
HJP eNVlA
~TL LOB
HJP CNVltf
~KP

MHO
NHO
MHO
NHD
NHO
NRO
MHO
MHO
NHD
MHO
NHD
MHO
.. HD
MHD
NHD
MNO
MHO

PAGE

12

P-50 MA.'K II ANALOG INPUT SCANNER
&16372
06373
06374
06375
06376
06377

J1777
07041
07056
0621"
00101
00100

TEST (0188)
.. HD
~HD

.HO
~HO
~HD

.. HO

PAGE

13

P-50

MARl<

·01
·02
403
404
405
40t
407
410
411
412

II

A~ALOG

06400
u6.01
06402
06403
06404
06405
06406
06407
06410
116411

INPUT SCANNER TEST (0189)
J7 1 267
J2 1 266
H 1 265

14
12
10
37

1 265
0 264
0 26J
1 262
J6 1 261
06257
4!4 1 260

J
J

J
J
J
J
J

"

STL HIB
ENL SAVE
L,!)H Ace
L.SH Ace
AND 3)
8ADD 6000)
STL HH8
NJP

OTRCU

(,jeT LI P1rUR
JP1P DCRL1P1

PAGE

14

P-50 MARK II

~

t-:I
I

~

C')

413
414
415
416
417
420
421
422
423
424
425
426
427
430
431
432
4JJ
434
435
436
431
440
441
442
443
444
445
446
447
450
451
452
453
454
455
4'6
457
460
461
462

A~ALOG

I~PUT

SCA~NER

TEST (DldB)
~JE

I~CHE"ENT

06412
06413
"6414
06415
"6416
06417
06420
06421
06422
06423
06424
06425
06426
06421
06430
06431
"6432
U6433
06434
06435
064,56
U6437
&6440
06441
06442
06443
06444
06445
06446
06447
06450
06451
06452
06453
116454
06455
06456
06451

"2 0 257
0 233
32 1 2,6
37 1 255
02 0 112
"2 1 254
l.7 0 021
03 0 lill
14 1 254
"2 0 122
l7 1 253
32 1 2,2
11 1 127
lO 0 040
01 0 117
32 1 233
12 0 251
10 1 117
"7 1 2"J
01 0 2,5J
01 1 255
l7 0 0.10
l.4 1 25,5
"2 0 250
0 127
"2 1 255
11 1 256
10 0 241
"1.7 0 054
10 0 247
27 0 06"
10 0 247
27 0 01l
10 0 247
27 0 101
01 • 214
l7 0 .60
;'2 1 246

"7

"7

JINCHMT ENL LOC1)
~TL LOC
ENL NUMTST
J
STL COU~T
CMB ADDR
ENL BIT
J
PJP L·2
~MB ADDA
LSH BIT
ENl ADDR
PJP ABC
J
JINCeHN t:NL MAXCMN
SUB CHNlNO.1
lJP CH3
OCR CHNlNO
CH2
ENl lOC.1
.I
BAND 37100)
ADD CHNlNO.I
STl lOC.1
DCA lOC
DCA COUNT
PJP CH2
JMP AdC
oItH3
ENl CHAN1)
STl CHNlND
INC~AD ENl COUNT
~UB NUMTsT
J
ADD 1)
t'JP R1
ADD U
PJP R2
ADD U
PJP R3
ADC) U
PJP R4
Rl
OCR COUNTl
PJP L.3
ENl CTRl
.I

POINT

ADDRE~S

"

INCMEMENT CHANNEL

INCREMENT WORD

~

t>:>
I

~

-::J

PAGE

15

P-50

I1~RI(

463
464
465
466
467
470
471
472
473
474
475
476
477
500
501
502
~03

504
'05
506
507
'10
511
512
513
514
515
516
517
520
521
522
523
524
525
526
527
530
531
532

II ANALOG INPUT SCANNER TEST (0188)
Ob460
06461
1.16462
06463
06464
06465
lJ6466
06467
06470
06471
06472
06473
1.16474
06475
06476
06477
06500
C6501
OH02
06503
06504
06505
06506
06507
06510
06511
06512
06513
(16514
06515
06516
06517
06520
06521

0 224
32 0 23~
10 0 224
~4 0 107
01 0 223
"-7 0 067
32 1 245
37 0 2lJ
32 0 231
10 0 223
24 0 107
01 0 222
'i.7 0 076
32 1 244
37 0 2~~
32 0 2Ju
10 0 222
l4 0 107
01 0 221
l7 0 105
32 1 24.5
37 0 221
32 0 227
10 0 221
37 0 122
32 1 122
10 1 127
37 1 233
01 0 233
01 1 255
l7 0 042
01 1 242
~7 1 253
~4 1 241

06522
06523
06524

00000
00077
00017
00037
00057

&16525
06526

.j?

R2
J

H3
J

R4

STL
ENL
ADD
JP"IP
DCR
"'JP
ENL
STL
ENL
ADD
JP"IP
OCR
PJP
ENL
::iTL
ENL
ADD
JP"IP
PCR

PJP
J

R5

ENL
STL
t:NL
ADD
STL
ENL.
ADD
STL.
DCA
OCR

PJP
OCR
PJP
JMP

J

J

ADDR
CHAN4
CHANJ

CHAN2

CHANi

COUNTl
LIMl
COUNT!
R5
COUN12

L·3
CTR2
COUNT2
LJI12
COUNT2
R5
COUNTJ

L·J
CTRJ
COUNT3
LlP"I3
COUNTJ
R5
COUNT4
L·3
CTR4
COUNT4
LIM4
COUNT4
AODR
ADDR,1
CHNL.NO.I
LOC"
LOC
COUNT
INCWHD
INDEX
ABC
CBA

OCT
OCT 77
OCT 17
OCT 37
OCT 57

PAr.~

16

P-50

~ARK

11

A~ALOG

06527

INPUT

SC.~NER

00000

TEST (0188)

CHfwL.NO OCT

PAGE

17

P-50 P'lARK I 1

H~ALOu

INPUT

SCANNE~

TEST (018B)

53~

!;35
536
537
540
541
542
543
'4~

545
!;46
5~7

I-'
I:\:)

I
I-'
(.0

550
551
552
553
554
555
556
557
560
561
562
563
564
565
'66
567
570
571

572'
573,
574
575

EJE
06530
06531
06532
06533
06534
06535
06536
06537
06540
06541
06542
06543
06544
06545
£16546
ltb!)47

06550
06551
06552
06553
06554
lI6555
06556
U655?
lI6560
06561
065'62
06563
06564
06565
06566
116567

32
37
.)2

J7
.)2

37
J2
37
J2
37
J2
:J7
10
37
J2
10
J7
01
lO
01
01
l4

32
,)7
32
37
J2
37
32
37
;j!4

00000
1 2!;6
1 2~l
o 240
0 2lb
0 2,7
0 23J
0 250
0 127
0 247
1 2!;4
1 216
0 225
1 225
0 1~i!
1 122
1 117
1 2JJ
1 2~~
0 156
0 226
0 2JJ
0 142
1 246
0 2i!4
1 245
0 22J
1

24~

0 222
1 243
0 221
1 1050

INITIALIZE:
INITL

•• I

ENL
STL
l:NL,
STL

J

11

12

NuMT:;T
INDEX
LlMU
LIM
tNL L,OCi)
STL LaC
tNL CHAN1)
l:ITL CHNLNO
E:NL 1)
STL BIT
I:NL L 1"'.1
STL, CNT
ADO CNT,l
~TL, ADDR
ENL ADDR, I
ADD CHNLNO,I
STL LOCd
OCR INDEX
lJP 12
OCR LIM
OCR 1.0C
JI1P 11
ENL, eTR1
STL CDUNTl
E:NL, CTR2
STL COUNT2
ENL CTRJ
STL COUNTJ
ENL CTR ..
STL COUNT4
tCTN

PAC~

P-50

~

I

~

0

.'

1 f·

t\·RK

57 ..
577
bOO
601
602
603
604
605
606
607
610
611
612
613
61"
615
616
617
620
621
622
623
624
625
626
627
630
631
632
633
63'
635
636
631
~40

641
642
643
644
645

11 ANALOG INPUT SCANNER TEST (D18S)
EJE
CONVERT 2
U657~

06571
06572
06573
0657"
06575
06576
116577
06600
06601
06602

J7

12
J7

J2
12
14
1"
14
10
l4

00000
1 266
o 237
1 236
1 266
o 235
1 265
1 265
1 265
1 236
1 170

eNvTA

•••

~TL

~ow

ORDER DIGITS or

SAVE

BAND 7>

J
J

STL
ENL
BAND
LSH
lSH
LSH
ADD
HTN

J

TEMP
SAVE
70)
Aee
ACC
Aee
TEMP
CONVERT 2 HIGH ORDER DlulTS or

0660~

0660£
06605
06606
0660'
0661:1
06611
06612
0661J
06614
06615
06616
0661'
0662~

06621
0662?
06623
0662 4
0662~

06626
06627
06630
06631
06632
06633

.)2

12
16
16
16
37
J2
12
10
1t
16
16
24

00000
1 266
o 23"
1 265
1 265
1 265
1 2J6
1 266
o 2bl
1 236
1 265
1 265
1 265
1 203
00000
00000
00000
00000
00000
00000
07342
07301
07240
07177
00000

ACCUMU~ATOR

CNVTS

•••

ENL
BAND
HSH
fcSH
RSH
STl
ENL
BAND
ADD
HSH
HSH

SAVE
700)
ACC
Aee
ACC
TEMP
SAVE
7000)
TEMP
Ace
Ace
HSH Aee
NTN

J

COUNU
COUNTJ
eOUNT2
COUNT1
CNT
~IM

I.IM4
LIM3
LIM2
LIM1
LOC

OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
gCT

V1DAH4-1
VIDAHJ-1
VIDAHZ-l
VIDAN1-1

AeeUMU~ATOR

PAGF.

19

P-51J "'ARK 11 ANAL.OG INPUT SCANNER TEST (0188)
646
06634
0~635

~

t\:)

I
t>:)
~

06636
06637
06640
06641
06642
06643
06644
06645
06646
06647
06650
066S1
06652
06653
06654
06655
06656
06657
06660
06661
06662
06663
06664
06665
06666
06667

00700
00070
06322
00007
06632
06200
062S1
07342
07301
07240
07177
00001
06526
37700
06004
0620J
06222
06244
06001
06310
06156
07000
06301
06000
00003
00101
06321
06302

EJE
WHO
IiIRO
WHO
MHO
wRO
WHD
WHO
WHD
WRO
.. HO
WHD
WHO
IiIHO
"'HO
wHO
WRD
WHO
wRO
.. HO
.. HO
WHO
WHO
WHO
.. RO
wRD
.. HD
NHO
WHO

PAGE

20

P-50 "ARK 11 AN'LOG INPUT SCANNER TEST (0188)

I-'

N
I
~
~

647
650
651
652
653
654
655
656
657
660
661
662
663
664
665
666
667
670
671
672
673
674
675
676
677
700
701
702
703
104
,.5
706
707
710
711
712
713
714
71'
716

07000
07001
07002
07003
U7004
07005
07006
07007
07010
07011
07012
07013
07014
07015
07016
07017
07020
07021
07022
07023
07024
0702'
07026
07027
07030
07',1
07032
07033
07034

32
10
37
.52
.57
03
J2
16
27
16
16
16
16
16
16
12
11
20
10
27
.52
36
32
10
16
27
02
l4

01000
00000
o 000
o 076
o 000
1 000
o 065
o 066
1 06~
a 066
o 011
1 075
1 075
1 075
1 075
1 075
1 075
a 014
o 074
1 000
o 074
o 025
o 013
o 03~
o 065
o 076
o 066
0 004
0 066
0 006

01.35
07036
07037
07040
07041
07042
07043
07044
0704'

10
37
32
34
32
27
02
32

00000
o 072
o 063
1 063
o 000
o 064
o 041
o 064
o 063

ONG
OTReD

•••

ENL
J
ADD
STL
ENL
5TL
S"B
OTLOP ENL
HSH
PJP
RSH
J
RSH
RSH
RSH
R:iH
IUiH
JSECND BAND
eSU8
lJP
BADD
PJP
J
ENL
NJP
ENL
ADD
RSH
PJP
C"B
J"'
OTl
J

OASR

•••

ADD
iTl
ENL
OUT
ENl
PJP
C"B
ENL

ORlGIN.~12

PRINT RECORD

TER"lNAT~D

BY 77 CODE

OTRCD
1)

OTRCD
OlRCD,l
OUD5
OTINU
OTAD:',l
OTINU
SECNU
ACC
ACC
ACC
ACC
ACC
ACC
77)
71)
OTRCU.x
77)

L·2
0)
OTl
OTAD5
1)
OTIND
OTlOP-2
OTINO
OTlO'
T8l)
ADS
ADS.I
"FLAW
l-l
"FLAW
ADS

WAIT FOR INTERRUPT

PAGE

21

P-50 "'ARK II ANALOG INPUT SCAHNE~ TEST (D188)

.....

t>J
I

t>J
c,.,:!

717
7Z0
721
722
723
724
725
726
72]
730
731
732
733
734
735
736
737
740
741

07046
07047
07050
07051
07052
07053
07054
07055

11 0 071
lO 0 05l

07056
07057
07060
07061
07062

00000
06 1 067
03 o 064
05 1 067
23 1 056

07063
07064
07065
07066

00000
00000
00000
00000

07067
07070
07071
07072
07073
07074
07075
07076

06321
30500
0711,s
07077
00000
00077
00101
00001

742

32
37
24
32
37

0
0
1
0
0
24 0

073
063
035
070
063
040

J

JLF'D

ASRIN
J

8SUB TBl·14)
lJP LJ:"D
ENL OJ
STl ADS
J"P OT1.1
8ENL 30500)
STl ADS
J"P OT1·4

,

..

SDR SAVE
S"B "F'lAij
EDR SAVE
CLJ ASRIN,l
ADS
"'F'L,AG

OCT
OCT

OTADS
OTIMD

OCT

OCT
GEN
.. RD
WHD
.. RO
.. HO
WHO
MHO
WHO
MRD

ASR INTERRUPT ReTURN

'.'E

22

'·'0 MARK II ANALOG INPUT SCANNER TEST (0188)

..

7.3
744
745

,

'.7
7'0
"1
7'2

~

I:o.j

I
I:o.j

~

7'3
7, ..
7"
7'6
7'7
760
761
762
763
76"
765
766
767
770
771
771
773
774
77'
776
777
1'"
1 •• 1
1 •• 2
1103

.....

1'"
1"6
1"7
1110
1111
1112

07077
01100
07101
07102
07103
07104
0710'
07186
071D7
07111
07111
07112
07113
07114
0711'
07116
07117
07110
07111
07122
.7113
07124
'711'
07126
07117
.7110
1711..
17111
17111
.711.
0711.
.711.
17117
171.0
D71.1
.714.
D7141
'l144

23000
33040
33100
231.0
3.)200
232"0
23300
133.. 0
33"00
23 .... 0
15700
1364D
31641
23'DO
33700
22,40
22'40
2"040
24100
34140
24200
34240
34300
24340
24.00
34440
23740
22700
32441
35'.0
21610
11140
22641
34'01
2.'••
,.680
2.'40

147.,

COD
TIL

yF'D
CUD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COO
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
CDD
COD
COD

TELETYPE MODEL 35 COOE
1,2,.1.3.5
1,0,6,0,
0
00
1.2.6.1.
01
1
1,2,6,2,
02
2
03
1.0,6.3,
J
4
04
1.2,6.4,
5
05
1.0.6.5.
6
06
1.0,6 •••
7
07
1,2,6.7.
8
1.2,7.0,
10
1,0,7.1,
9
11
1,3.~.6,
12
0
1,2.7,',
13
•
1,2.1,5,
CR
14
I
1 •• ,7.2.
15
1,2.7.6,
>
16
1 ...... 1,
e.CLM 17
1.0.5,1.
20
•
A
1.1.0.1.
21
1,1,1.2.
8
22
1.3.0,3.
C
23
1.1,0.4,
0
24
1.3.0.5.
E
25
1,3.0.6.
F'
26
1.1.0.7.
G
27
1.1.1,8.
30
1.3.1.1.
31
I
1.1.7.7.
32
1.D.5.6.
33
•
1.2.5,1.
34
»
35
1.3.'.1.
l
<
1.D.7.4.
36
1,2.4.3.
37
1".5,5,
40
1.1.1.2.
J
.1
It
1.1.1.3.
.2
1.1,1,4.
43
L
1.1.1.,.
.4
45
1.1.1 •••

",
•

...

PAGE

23

P·50 "ARK 11 ANALOG INPUT SCANNER TEST (D188)
1013
1014
1015
1016
1017
1020
1021
1022
1023
1024
1025

~

t'IJ

I
t'IJ
01

1026
1027
1030
1031
1032
1033
1034
1035
1036
1037
1040
1041
1042
1043
1044
1045
1046
1047
1050
1051
10'2
1053
'054
1055
1056
1057
lD60
1061
1062

07145
07146
07147
07150
07151
07152
07153
07154
07155
07156
07157
07160
07161
07162
07163
07164
07165
07166
07167
07170
07171
01172
07173
07174
07175
07176

34740
25000
35040
35100
25740
22200
32500
35644
33540
34000
32000
32740
25140
35200
25240
25300
35340
35400
25440
2'500
32240
32600
22400
32300
25600
20500

07177

00000

07200
07240

00000
00000

07241
07301

00000
00000

073D2
07342

00000
00000

07343

00000
00000

COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD
COD

1,3,1,7,
1.l.It.D,
1,J.~,1.

1,3,c,2.
1.1,ot,7.
1,0,4.4,
1,2.:'.2.
1.3 • .t.5,
1.2.7,;5.
1.3.0,0.
1,2.4,0.
1.2,5.7,
1.1,2.3,
COD 1,J.It ... ,
COD 1.1,~,5.
COD 1.l,It,6.
COD l,3.jl.7,
COD 1.3,3,0,
COD 1.l,J,1.
COD 1.1,3.2.
COD 1.2,4.5,
COD 1.2,5,4.
COD 1,0.',0,
COD 1,2,4.6,
COD 1,1,.1,4,
COD 1.0.1,2,

CTR1
OCT
VIDARl RPT 32
OCT
CTR2
OCT
YIDAR2 ItPT 32
OCT
CTR3
OCT
VIDAR3 RPT 32
OCT
CTA4
OCT
WIDAR4 RPT 32
OCT
END

46
47
Q
50
R
51
52
•
5
53
54
•
55
56
57
SPACE 60
I
61
S
62
T
6J
U
64
V
65
w
66
)(
67
0

p

••

y

70

71
72
73
(
74
75
A"P
\
76
L F'EED77

.

Z

., .

(ONTACT CLOSURE OUTPUT VS. CONTACT CLOSURE INPUT TEST (019A)
I.

Purpose of Test
To test up to eigh~ contact closure output registers against the same number of
contact closure input registers without the use of the P-50 Executives. Various
patterns UP gpt on the registers and the registers are then checked for proper
operation. This test is for multiplexed cel. See V for non-multiplexed modifications.

Tl.

Description of Test
The program assumes that n contact output registers are tied to n contact input
registers (wherf' n ranges from 1 to 8). Various patterns are output to thr. contact outputs; after each change. all the contact inputs are checked to verify that
the desired changes (and no more) took place.
The pattern of output is as follows:
00000.37777 ....... 00000.37777 .(Sequence of 14)
0000l.00002 ....... 10000.20000.(Sequence of 14)
20000.30000, ..... ,37776.37777.(Sequence of 14)
12525.25252 ...... ,12525.25252,(Sequence of 14)

nI.

Description of Operation
A.

B.

Read in the binary tape of the Contact Closure Output vs. Contact Closure
Input test using the bootstrapped binary loader.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe. load the X-Register with the starting location of the
binary lr>ader (X7602); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape reader.

5.

Turn the reader on.

6.

Depress the Start button.

Enter the test parameters.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

USing the probe. load the S-Register wtth the parameter locatton.

3.

USing L'u; probe. load the X-P.egtster with the parameter constant; depress
the Start button.

4.

Repeat 2 and 3 untU all the follOWing parameters have been entered.

13-1

location

C.

Description

60008-60078

C~S

Contact closure output (CCO) control words,
one for each register. Each control word contains the word (bits 13-6) and the set channel
(bits 5-0) for a particular output. The registers
are assigned numbers 0-7 corresponding to locations 60008-60078. ,

60108-60178

IBF

Contact closure Input (CCI) control words, one
for each register. Each control word contains
a one In the bit position corresponding to the
register number. For example, a one In bit 4
(208) of the control word refers to register 4.
Note, one and only one bit of a control word
can be set. The registers are assigned numbers 0-7 corresponding to locations 601086017 8'

6020 8

NCC~

Number of registers to be tested.

6021 8

CCaI

Contact closure output (CCO) completion Interrupt location.

6022 8

aRI

Contact closure Input (CCI) cycle completion
interrupt location.

6023 8

IRI

Contact closure Input (CCI) input request Interrupt location.

6024 8

ASRI

ASR output completion interrupt location.

6025 8

CCIC1UT

Output command to contact closure Input (CCI)
address channel. For example, If the channel
Is 428, the command Is 34042 8 (aUT 428)'

6026 8

CCnNT

Input command from contact closure Input
(CCI) read channel. For example, If the channel
Is 438' the command Is 300438 (INT 438).

6027 8

aUTASR

Output command to ASR output channel. For
example, If the channel Is 448, the command Is
340448 (~UT 448).

Start the test.
1.

Put machine In WRITE mode; depress the Master Clear button.

2.

Using the probe, load the X-Register with the starting location of the test
(60278); depress the Start button.

3.

Put machine In RUN mode; depress the Master Clear button.

4.

Clear the lockout and hit nlp-nop using the probe; depress the Start
button.

13-2

D.

Test runs continuously, printtng out a completion message on the ASR set
after five runs.
CC<'-CCI TEST COMPLETED

E.

When an error occurs a message Is printed out on the ASR set, and the test
continues. The error message format Is:
CC(2j-CCI REGISTER

a SHOULD BE bbbb BUT IS cccC.

where
a = Register number
bbbb = Pattern that should be there
cccc = Pattern which Is there
IV.

Storage
Number of locations used:

V.

10528 (600°8-70518)'

Non-Multiplexed CCI Modification to D19A
It should be pointed out here that CCI can be multiplexed or non-multiplexed. The
program listed in D19A is for multiplexed CeI; if non-multiplexed Cel's are used,
the program must be modified as follows:

Location

Initial Contents

6635
6636

32631
10342

New Content
300 XX23631

-Input channel number
VI.

Test Cables
A.

Multiplexed CCI Vs. CC.,
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DATE

4/14/65.

PROJECT NO.

TlME

5~005j

A,I1,

214UJ~

PROGRAMMER 0,

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TAPE NUMBER 447514

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CONTACT CLOSUR& OUT'UT CONTROL WORDS

CONTACT CLOSURI

CCO
eCI
CCI
AS"
CCI

I~PUT

COMPLETE
OUTPUT RIG
INPUT REG
COMPLETE
ADDNESS CHAN
cel DATA
ASR OUTPUT CHAN

CONTROL WORDS

1

DATE

4/14/65.

PROJECT NO.

ilME

5J005~

21

~rL

057
140
0 0!;7
1 0,7
0 116
0 137
0 111
1 117
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DATE

4/14:6~.

TIME

2I4J/41

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PRO.lfiCT NO. 530053 PHOGRA""ER D. HEYlf>4!i
360
J61
362
363
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DUE

4/14/65.

PROJ~CT

NO.

372
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374
375
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177
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412
413
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TIME

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06542
06543
06544
06545
06546
06547
06550
06551
06552
06553
06554
.6555
06556
06557
06560
06561
06562
06563
06564
06565
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06573
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06575
06576
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06601
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06604
06605
06606
06607

2/43/43

P,;I ,

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TAPE NUH8EH 447S14

ROUTINES rOH SBO AND SBZ
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DATe

4/14'65.

TIME

PROJECT NO. 5J0053
442
443

444
445

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TAPE NUMBER 447514

DATE

4/14l65.

PROJECT NO '.

446
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DATE

4/14/65,

Tl~f-

PHO':ECT NO. IjJ005J
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D6714
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MRD
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DATE

4/14/6S.

oAOJECT NO.
557
560
561
562
5n
564
565
'66
567
570
571
572
571
57.2

"2
"2
.....

C..:I
I
C..:I
~

'72

.72

"2

572 '
513
"3
513

"3 .
"3
'13

'73

'71-

51J
'74
"4
574
574
574
514
574
"4
574

",
",

T ute

~J0051

A.".

214J/59

PROGRAMMER D,
COD
CDe

TBL
06752
16753
16754
.6755
0675.
16757
86760
06761

33000
33040
33100
3.S140
33200
33240
33300
J3340

06762
16763
16764
16765
16766
16767
t6770
16771

33400
33440
35700
33640
30640
33500
33100
32040

06712
16713
06774
06715
06776
06717
,71.0
07001

.12540
34040
34100
.54140
"4200
34240
34300
34340

"002

344.0

P.. QIi 19

'APE NUMBER 447514

~EYr~G

vrD
MAC
COD
COD
COD
COD
COD
COD
COD
COD
TEA
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COD
COD
COD
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1.260.
1.261.
1.262.
1.263.
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270.271.336.275.215.272.27,.241
1.270.
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1.276.
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1.30!t.
1.306.
1.307.
31.'''11.277.25 •• a~1.333.274.243
1.310.

•• f~

4/14/'6\ •

TIME

2/44/03

~J5

• '0005

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,7 •• 7

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34600
34640
34150
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COD 1.2S6.
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caD 1."1.
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COD 1,111.
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COD 1.152.
caD 1.'I~ •
C.. 1.171.
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1.a.~

•

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DATE

4/1,/65.

PAOJECT NO.
601
601

'01

'02

TlME

S,sOO5,s

0704'
'7050
17051

~ROGIU~"'EH
J~30;)

PA&E 23

A,"',

~/.4/07

0,

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:APE

\;OC 1.246,
COD !.,s.J4,

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1.21~.

NUMt:tEW 44 7H4

TAPE NUM8EN 441514
STAR!ED

lDJ10/6~.

2/~2/00

A,M.

COMPLETED 4/14/65. 2/44/u7 A.M.
l86.
""MBEA or IHPUT H~CORDS
JWIt8,A or OUT~UT ~~CO~DS bl0;

....'R or 8INARY

RECONDS

S6J,

CONTACT CLOSURE OUTPUT VS. PROCESS INTERRUPT TEST(D20.
L

Purpose of Test
To check up to four words of process interrupts by connecting them to the same
number of contact closure output words.

IL

Description of Test
The program consists of four parts.
In part one. initialization. all contacts are opened and the corresponding interrupt
images are cleared to positive zero.
In part two. the folloWing sequence is executed: close a contact. check for an
interrupt (one and only one interrupt should occur); open the same contact, check
for an interrupt (no interrupt should occur). All contacts are tested.
In part three the following sequence is executed: close a contact. check for an
interrupt (one and only one interrupt should oocur); repeat until all contacts are
closed.
In part four the following sequence is executed: open a contact check for an interrupt (no interrupt should occur); close a contact. check for an interrupt (one
and only one interrupt should occur). All contacts are tested.

Ill.

Description of Operation
A.

Read in the binary tape of the Contact Closure Output vs. Process Interrupt
test using the bootstrapped binary loader.
1.
2.
3.
4.
5.
6.

B.

Put machine in WRITE mode; depress the Master Clear button.
Using the probe. load the X-Register with the starting location of the
b~.nary loader (X7602); depress the Start button.
Put machine in RUN mode; depress the Master Clear button.
Place the binary tape under the tape reader.
Turn the reader on.
Depress the Start button.

Enter the test parameters.
1.
2.
3.

4.

Put machine in WRITE mode; depress the Master Clear button.
Using the probe, load the S-Register with the parameter location.
Using the probe, load the X-Register with the parameter constant: depress the Start button.
Repeat 2 and 2 until all the following parameters have been entered.
Description

Location
5400 8

CC0

Contact closure output (CC0) completion interrupt
location.

5401 8

ASR

ASR output completion interrupt location

5402 8

ASRCHN ASR output channel number

14-1

Location

C.

54038

C0N

Number of contacts which are connected to procesl
interrupti; the maximum number il 5810. Bit 0
of first CC0 word il connected to first process interrupt, Bit 1 to second, etc.

54048

PRI

Location of first process interrupt which is connected to a contact closure output (CC0). The
prooess interrupts are alsigned sequentlally to
the CCQJ's.

54058 54108

CWDS

Contact clolure output (CC0) control words. one
for each relliter. Each control word contains the
word (bUI 13-8) and the set channel (bits 5-0) for
a particular output.

Start the test
Put machine in WRITE mode; deprels the Master Clear button.
Using the probe. load the X-Register with the starting location of the
test (54108); depress the Start button.
Put machine in RUN mode; depress the Master Clear button.
Clear lockout and hit fUp-flops using the probe; deprels the Start button.

1.
2.
3.
4.

D.

Delcrlption

Test runs continuously. printing out the following completion message on the
set after ten runs (one cycle).

ASR

CCQJ-PRI TEST COMPLETE
E.

When an error OCCllrs a message is printed out on the ASR set, and the test
continues. The error message format is:

CC01NT IS aa SHOULD BE bb
where
aa
bb

=interrupt. which occurred (octal number)
=interrupt * which should have occurred
(octal number)

h'.

Storage
Number of locations used: 20528 (54008 - 74518)

"..

CC¢ vs. Interrupt Test Cable
Drawing 775A054 shows the connections for the CC0 vs. Interrupt Test Cable.
Note;

This test will not check interrupt. 0-17 (core location 1-20).

• The interrupt numbers alsiped lequentlally, bePnnlq with one, to the prooess interrupts used for the telt. That II, the flrat procels Interrupt uaed II one (01), the
BPcond is two (02). etc.

14-2

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DATE

4127/65,

P~~CT

TI~E

P.M,

2/30/07

P.tGE

NO, 530053 PROGRAMMER J,E, PHILLIPPI

TAPE NUMBER 512606

ceo vs

1

2

:5

PROCESS J NTERRUPT TEST

PROGRAM

.

LIBRARY

PROGRAM NO,

5

P-50

00101<

6

?

05400

10
11

STe

l~

14
15

**I
ell

MAC
f:NL L-l
STL CONTAT

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I-'

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TER
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H
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21
22
23

;,,~,:
••

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I

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24

OCR TAelE-N
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25

C~..;

26

TER

27

05~00

OCOCO

30
31
32

05401
05402
05403
0:'404

0;;000

33

ccaou
Cl' Cl:VI

no aD!;

34

35

eGO
A.:: F:
A5RCH~
'''f''.
"" .... ,...

P')

::

05405

OvOOO

05406
05407

00000

05~l.O

00000

OCJOO

"

L.

cco

OCT

OCT
OCT

ASR

OC';"

'JS

RP~

OCT

!.:TE~IWflT

: i\

~'

c; f: P UFT

N'..'MSFrNU"lBF~

HR C':HlNEL. NUMBER
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F-rr,!£,:-

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1

DATE

"/27/65,

TIME

2130/.7

P,M.

PA(lE

PROJECT NO, 530053 PROGRAMMER J,E, PHILLIPPI hPE NUMElER 512606

~

~

I

(j)

36
37
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74

75
76
77
100
101
102
103
104
105

05411
05"12
05H3
05414
05415
05H6
05417
05420
05421
05422
05423
05424
05425
05426
05421
05430
05431
05432
05433
05434
05435
05436
05437
05440
05441
05442
05443
05444
05445
05446
05447
05450
05451
05452
05453
05454
05"55
05456
05457

32
13
37
32
10
37
13
37
32
37
32
10
37
13
37
32
37
32
10
37
32
37
32
37
10
37
1.5
37
32
37
01
01
01
01
01
32
10
01
27

0 002
0 364
1 363

SETuP
J

8~OR

34000)

./

STL
ENL
ADD
STL
8E OR
STL
ENL
!:iTL
ENL
ADD
STL

OUT
ASR

0 001

0
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0

0
0
0

1
1
1

1
1
1

1
1
0
1
0

0

362
255
361
001
360
255
000
362
255
361
000
357
255
003
356
255
355
354
004
253
362
254
361
253
354
254
354
354
35.
354
35"
253
356
255
037

EJE
ENL ASRCH"4

J
./

./

8~OR

STL
ENL
STL
START ENL
ADD
J
STL
ENL
J
./
STL
ENL
STL
AA
8AUD
STL
8ElIR
STL
ENL
STL
OCR
OCR
fJCR
OCR
./

65)

TEMP
36400)

ASR,l
ASRIN)
TEMP,I

cco

65)

TEMP
36400)

eeO,1
INTCCO)
TEMP, I
CON
SSl
TEMP
LASUD)
LAST
PRI
INDEX
101)

JUMP

36400)

INDEX, 1
LAST
JUMP,J
LAST
LAST
LAST
LAST
DC~ LAST
ENL INDEX
AUD SS1
DC~ TEMP
~JP AA

2

OAff

41')7.'flr;.,

P'iOJfCT NO.

106

lH

ao

TIME

VJO/52

111

112
I I ,~

11.4

11S
116

.....

.;>.
I

-::J

116
116
117
.i..2C

121
1?~

-<-

123
12·1
125

126
127

F:.GE

5SQ[:":i3

PROGRAMMER J. E. PHj ... lIPPI lA=E

05460
05461
0!l462

32 0 3~.s
.31 1 352
36 0 267

.ICC
J

111

111

P.M.

O!j463
05464
05465
05466
05467
05470

J2 0 2:'6
37 0 010
32 0 ?56
37 G on
36 1 J!:I!
00000

05471
05472
05473
05474
05475
C!;476
Q5477
05500
05501
05502
05503

32 0 07D
37 0

32 ... 3:=3
01 1 3f>;?
27 0 073
32 1 347
3;- 1 257
3:'1 1 346
01 il 257
01 1 345
27 0 062

~JD

IN£H.x

~TC

SIHC

~!';L CQNTA.T
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STC
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S-,

25.:.

r

Be

fooL 10)
STl eTR

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kJP ICRCUN

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OCR 1r.JDEXX

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NUMj;:Iior;

"..... L

~ _

G~~~

J

DATE

'127/65.

TIME

2130/54

PAGE

P,"",

PROJECT NO. 530053 PROGRAMER J,E. PHILLIPPI UPE

.....

t

8

P.M.

PAGE

'ROJECT NO. 530053 i-lROGRAP4MER J.E. PHILLIPPI TAPE NUHBEA 512606
167
170

0505.5

171
171
171

172

173

05546
05547
055'0
05551

32 ~ :;'56
31 0 151
36 1 344
00000

05552
05553
05554
05555
05556
05557
05560
05561
05562
0556·3
05564
05565
05566
05567
05570
05571

32
37
32
01
27
32

174

......

~

I

~

174
174
175
176
177
200

201
202
203
204
205
206
207
210
211
212

EJE
.16 0 267

10
37

27
24
36
36
36
01
01
27

TEST2

5802

IotJP

HTC
ENL
STL
HJP
OCT

INI H.X
5802
CONTAf
5802·1

SBO

src

0 l'jt

~NL

0 256
0 350
1 362
a 154
1 257
1 3,6
1 257
0 163
0 164
0 240
a 277
1 346
0 257
1 345
0 145

5TL
WA I TC 8ENL
DCR
to' JP
t:NL
ADD

L-1

CONTU
10000)

ACC
L-l
ITABXd

Sst

STL lTABXd
I"JP L·2
JI1P

L·2

kJP ERR1
kJP ZINTCK
kJP lCRCO~
OCR (HBl(
OCR lNOEll(
~JP TEST2·1

5

DUE

.~

127/65.

TI"E

lIll/00

p.".

PAil!

PRO-IECT NO. 530053 PROGRA""ER J.E. PHILLIPPI

......
~

I

......
0

213
214
215
215
215
216
216
216
211
220
221
221
221
222
223
224
225
226
227
230
231
232
233
234
235
2J6
237
240
241
242
243

244
24'
246
247
2~0

251
252
253
254

05572

36 0 267

05573
05.74

32 0 256
37 0 214

TESTJ

E:JE
k JP INITLX
~lC

05575
05576
05577
0'600

32 0 256
31 0 200
36 1 351
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05601
0'602
0'603
0,6U4
0'605
05606
05607
0;610
0;611
05612
0;613
05614
05615
0;616
0;617
0;620
0;621
05622
05623
05624
05625
01[,626
D5627
05630
0;6J1
056"2
0,6.53
05634
05635

32
31
32
01
21
32
20
36
03
30
36

HPE NUI'1I:lER 512606

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6

)ATE

4/27/65,

TIME

2131104

p."'.

" .. :Ae

'ROJEC T NI) • 530053 PROGRAMMER J.E. PHILLIPPI TAPE NUMBER 512006
255
256
257
260
261
262
263
264
265
266
267

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271
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1 340
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32
11
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7

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".'27/65.

'ROJECT NO.

.....

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t..l

301
302
303
304
305
306
307
310
311
312
313
314
315
316
317
320
321
322
323
324
325
326
327
330
331
332

333
334
335
136
337
340
341
342
343
344
345
346
347
350

TIME

~J0053

2131101

P,M,

PAiiE

PROGRA""ER J.E. PHILLIPPI

TAPE NU"BEH 512&06

E:JE
05661
05662
05663
05664
05665
05666
05667
05670
05611
05672
05673
05674
05675
05676
05677
05700
05701
05782
05703
05704
05705
05706
05701
05710
05711
05712
05713
t5714
05715
t5716
.5717
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05721
05722
05723
05724
05725
t5726
t5727

32
37
32
37
24
32
37
32
37
32
37
24
36
32
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2/31/11

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06022
06023
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405
405
405
405
406
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406
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406
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407
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407
407
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410
410
410
410
411
411

411
411
411

411
412
412
412
412
412
412
413
413
413
413
413

06215
06216
06217
06220
06221

06
01
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.

TAPE NUM8ER 512606

:,DR TEMP""
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06222
06223
06224
06225
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06 o 172
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06 0172
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06235
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06241
86242
06243
06244
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06246
06247
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06251
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06254
06255
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06 o 012
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14

DATE

4/27/05.

TIME

2131/33

p.",

DAliE

PflOJECi NC, 530053 PROGRAMMER J.E. PHILLIPPI TAPE NUMBER 512606

.....
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4l.3
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06257

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06260
06261
06262
06263
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06266
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06270
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06
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41.4
41.4
41.5
41.5
41.5
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41.6
41.6
41.6
42.6
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420
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421
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06273
06274
06275
06276
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06304
06305
06306
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PROJECT NO, 530053 PROGRU.,,4ER

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423
423
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424
424
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425
425
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425
425
425
426
426
426
426
426
426
427
427
427
427
427
427
430
430
430
430
430
430
431

06320
06321
06322

01 o 035
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06323
06324
06325
06326
06327

06
01
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23

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06330
06331
06332
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06335
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06342
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06354
06355
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PAGE

P,"'.
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PHILLIPPI TAPE
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25

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4/27/65.

TIME

2131/4\

P,M,

P,\(;E 17

NO..JECT NO. 530053 PROGRAMMER J.E. PHILLIPPI TAPE NUMBER 512606
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06362
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06414
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T I"E

2131/53

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PAGE 20

PAOJECT NO. 530053 PADGRA""ER J,E. PHILLIPPI TAPE NUMBER 512606
455
456
457
460
461
462
463
464
465
466
467
470

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06525
06526
06527
06530
06531
06532
065.13
06534
06535
06536
06537
06540
06541
06542
06543
06544
06545
06546
06547
06550
06551
06552
06553
06554
06555
06556
06557
06560
06561
06562
06563
06564
06565
06566

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37 1 144
12 o 14.1
37 1 142
32 1 144
12 o 141
14 1 140
14 1 140
14 1 140
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24 1 125
00101
00070
05655
00007
07354
06067
06066
06065
06064
06063
06062
06061
06060
06057
06056
06055
06054
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06052
06051
06050
06041
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4127/65.

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501
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2131/57

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471,

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TIME

504
50'5
506

507
510
511
512
513
514
515

516
517
52'0
52~1

522
525
54~4

525
54!6
527
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01000
07001
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07003
07004
07005
07006
07001
07010
07011
07012
07013
07014
07015
07016
07011
07020
07021
07022
07023
07024
07025
Q7026
07QV
07()Ju

07031
070J2
0"033
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070J5
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52 o 000
10 0 342
37 o O()O
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27 a 017
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16 1 341
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16 1 341
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11 o 340
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,

T IP~E

2132100

P,M.

PAGE

'ROJEC, NO. 530053 PROGRAf"I1ER J.E. PHILLIPPI TAPE NUH8EH 512606
531
532
533
534
5J5

536
537
540
541
5~2

543
'544
545
546
547
550
S51
552
553
554
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07040
07041
01042
01043
07044
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07046
07047
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01052
07053
07054
07055
07056
07057
07060
07061

10
37
32
34
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1 061
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DATE

4127/61!1,

TIME

2132102

P,M,

PAGE 2

PROJECT NO, 530053 PROGRAMMER J,E, PHILltPPI TAPE NUMB&R 512606
55i5
556
55i7
5EIO
5EIl
562
563

EJE
COD

coe

5~14

5115
5~,6

St"
5j~0

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07062
07063
0706 6
070~:

33000
33040

33100
33140

07J6~

l~200

07067
0701C
07071

5'240
i3300
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07072
07073

H4\lO
31440
15700
11640
l()64Q
33500
33700
32040

5'72

';'72
5'72

572
572
572

572
572
572
573
573
573
573
573
573
57,;
573

"3

514

...

07074

07075
07076
07077
07100
07101
07102
07103
07104
07105
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07107
07110
07111

32540
14040
34100
34140
3\200
34240
34300
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VF'D 1,8,5

MAC
COD
COO
COD
COD
COD
COD
COD
COD
TER
BCDE
COO
COD
COD
COD
COD
COD
COD
COD
aCDE
COO
COO
COO
COD
COD

COD

COD
COD
8CDE
COD
COD
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COD
COD
COD
COD
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1.262.
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1.267.
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L.270.
1.271.
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1,275,
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1,272,
1.276.
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1.302.
1,303,
1.304.
1.305.
1.306.
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J10.Jll.271,256.l51,lJl.274.243

DATE

4/27/65,

TIME

2132106

p,"".

PAGE 2-

PROJECT NO, 530053 PROGRAMI1ER J, E • PHILLIPPI TAPE NUMBER 512606

....

~

I

N
00

574
574
574
574
574
574
'74
574
575
"5
575
515
575
575
575
575
575
576
516
'76
516
576
576
576
576
576
577

'77

577
'77
577
577
577
577
577
600
600
600
600
600

07112
07113
07114
07115
07116
07117
07120
07121

34400
34440
33740
32700
32440
35540
33600
32140

01122
01123
07124
01125
07126
07127
01130
07131

32640
34500
34540
34600
34640
34700
34740
35000

07132
07133
07134
07135
07tJ6
07137
07140
07141

35040
35100
35740
32200
32500
35640
33540
34000

07142
01143
07144
01145
07146
07147
01150
07151

32000
32740
35140
l5200
35240
35300
35340
35400

01152
07153
01154
07155

35440
35500
l2240
32600

COD
COD
COD
COD
COD
COD
COD
COD
8CDE
COD
COD
COD
COD
COD
COD
COD
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COD
COD
COD
COD
COD
COD
COD
COD
8CDE
COD
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COD
COD
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COD
COD
COD
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COD
COD

1.310.
1.311.
1.277.
1.256.
1.251.
1.333.
1.274.
1.243,
255.312,313.314.31'.3,'.317,320
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1.313.
1.314.
1.315.
1.316.
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1.321.
1.322,
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1.244,
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1.325.
1.326.
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OA1E

4/27/65,

Tl~E

PROJECT NO, 530053

2/32!10

~~UGHAf~E~

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P.M,
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PHILLIPPI TAPE

600
600

07156
07157

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512606

DATE

4/21165.

T I ME

2132111

p".e

P.M.

PROJECi NO. 530053 PROGRAMMER J.E. PHILLIPP 1 TAPE

EJE

60~

602
603
604
605
606
607
610
611
612
613

614

~

~

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615
616
617
620
621
622
613
624
615
626
627
630
631
'32
613
634
635
636
637
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641
642
641
'.4
645
646
641
6~0

NU"~ER ~12606

01162
87163

81164
07165
07166
07167
07170
07171
07172
07173
07114
07175
07116
01117
.7280
07201
07212
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07204
07205
07206
07287
07210
D7211
01212
.7213
07214
.7215
07216
07211
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.7221
.7222
.7223
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07225
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37
32
10
37

32
37
10

37
32
37
32
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32
37
32
37
34
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32
20
01
20
01
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1 222
o 223
o 221
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o 224
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AC .. R

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2/32/15

p.~.

PaDJECT NO, 5J0053 PROGRAMMER J,E. PHILLIPPI T.PE NUMBfR 512606
07227
07230
07231
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PAGE 27

DATI:

;127/65.

NO~T

~

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C-"

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T I ME

j'O, 5.50053

651
652
653
654
655
656
657
660
661
662
663
664
665
666
667
670
671
672
673
674
675
676
677
700
701
702
703
104
705
706
701
710
111
112
713
714
715
716
111
720

21JU16

p. ,...

J.E.

PROGRAM~ER

PAIiE 2.

PHILLIPPI

TAPE NUMI:iER 512606

i:JE

07236
07237
07240
01241
01242
07243
07244
01245
07246
01247
01250
07251
01252
01253
07254
07255
07256
07257
07260
07261
07262
07263
07264
07265
07266
01267
07270
07211
07212
01213
07274
07275
07276
07277
07300
07301
07302
01303

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32 o 3olO
37 o 305
32 o 236
24 o 246
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32 o 3.57
37 o 305
32 o 243
10 o 342
37 o 243
32 1 24.5
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37 o 306
32 1 243
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16 1 341
16 1 341
16 1 341
37 o 217
10 o 332
37 o 307
32 o 306
10 o 326
37 o 306
32 1 306
37 o 306
32 o 305
27 o 300
13 o 306
12 1 30 7
13 o 306
36 a 162
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DATE

4/'27'6';,

P~OJECT

NO. 530053 PROGRAHHER J.E.

721

07304

722
123
724
725

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......

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07307
07310
07311
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07323
07324
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00001
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00004
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00040
00100
00200
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01000
02000
04000
10000
20000

07326
07327
07330
07331
01332
07333
07334
07335
07336
07337
07340
07341
07342

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37777
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30500
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07062
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00077
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726

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BIT
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MAST

P~lLLIPPI

TAPE NUMBER 512606

JI1P ACwC
OCT
OCT
OCT
OCT 1.2,4.10.20,40.100,200,400,1000,2000,4000,1000D,20000

GEN

NRO
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07355
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07362
07363
073604
07365
07366
07367
07370
07371
07312
07373
07374
07375
07376
07377
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01401
07402
01403
074004
07405
01406
07407

00000
00000
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00002
00015
00017
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02323
04631
04563
06031
06260
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06060
06230
04664
0<4324
06022
02560
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02323
0"6040
04751
03160
06325
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551
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15
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4/'27/65,

TIME

21J21Zb

p ,1'1.

PAGE 31

P'ROJECT Nel , 530053 PROGRAMMER J, E. PHILLIPPI TAPE NUMBER 512606

~

~

I

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751
752
753
754
755
756
757
760
761
762
763
764
765
766
767
770
771
172
773
714
775

176
177

100'

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07411
07412
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07414
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07432
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1 044
1 043
1 042
1 041
1 040
1 037
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f,; MU L is not zero; multiplexed eel
registers are tested if MLTPLX is not zero. (j\;c:bN MUL and ML TPLX are input
parameters. )
When a register is read, if the contents are :l€' ro, the test contmues. If the contents are nonzero, the bit pattern output to select the register (multiplexed) or the
input channel (non-multiplexed) and the reading are printed in binary; the test continues.

Ill.

Description of Operation
A.

Read in the binary tape of the test using the bootstrapped binary loader.
1.

2.
3.
4.
5.
6.
B.

Put machine in WRITE mode; depress the Master Clear button.
Using the probe, load the X-Hegister with the starting location of the
binary loader (76028, 176028, 276028, or 376028); depress the Start button.
Put machine in RUN mode; depress the Master Clear button.
Place the binary tape under the tape reader.
Turn the reader on.
Depress the Start button.

Enter the test parameters
1.

2.
3.
4.

Put machine in WHITE mode; depress the MaRter Clear button.
Using the probe, load the S-Register with the parameter location.
Using the probe, load the X-Hegister with the parameter constant; depress
the Start button.
Repeat steps 2 and 3 until all parameters needed ha 'e been entered.

15-1

Location

Description

Parameter

~008 ------N0NMUL.---- Number of non-multiplexed eCI regis-

ters to be tested (0-1410).
2018 - - - - - - M L T P L X - - - - Number of multiplexed eCI registers
to be tested (0-1410).
202 8
Bit to output to select register 168
2038
One'blt
Bit to output to select register 158
set

1

216 8
Bit to output to select register 28
2178 _ _ _ _ _ _ _ _...:_1---"'_ _ _ _ _ _ Bit to output to select register 18
2208

--------.....,.r------- Input channel, non-multiplexed register
I

221 8

Input
Channel

234 8

1

168

Input channel, non-multiplexed register
158

~npllt

channel, non-multiplexed register

2358 _ _ _ _ _ _ _ _...._1--_ _ _ _ _ Input channel, non-multiplexed register
1

2658 _ _ _ _ _ _ _ 340XX _ _ _ _ _ XX is multiplexed CCI address select

channel
2708 _ _ _ _ _ _ _ 300XX _---'_ _ _ XX is multiplexed CCI input channel
242768

Transfer for multiplexed
request interrupt

cel

input

;1 eel cycle cotnplete interrupt

24271 8

Transfer for multiplexed
complete interrupt

cel

cycle

A logger
interrupt

247348

uf CCI input

request interrupt

Transfer for ASR or Selectric completion interrupt
3358 _ _ _ _ _ _ 340XX _ _ _ _ _ XX is ASR or Selectric output channel
(Load following only if Selectric logger is used; do not load if
ASR set is used for printout.)
Location

Parameter

337 8

374108

Selectric code for" 1"

340 8

054008

U sed to get code for "0"

341 8

00110 8

Selectric code for space

342 8

000508

Selectric code for carriage return

343 8

00110 8

Selectric code for space

Description

15-2

C.

Start the Test
1.

2.
3.
4.
D.

Put machine 1n WRITE mode; depress the Master Clear button.
Using the probe. load the X-Register with the starting location of the test
(2378); depress the Start button.
Put machine in RUN mode; depress the Master Clear button.
Depress the Start button.

The test runs continuously. When a register is read and the contents are not
zero, the following printout occurs:
~yyyyyyyyyyyyyy

where x. .. x is the bit pattern output (for a multiplexed eel register) or x ... X
is the input channel (for a non-multiplexed eel register) and y... y is the register contents.
IV.

Storage
Number of locations used: 1618 (2008-3608)

15-3

PA(lE

1

P-5. eel

T~ST ~ITMOUT CA8LES
T~STS ~ULTIPLEXEC AND/U~

1
l

J

80tC~

P-50 037'
NON-MULTIPLEXED eCI

200

4
~

_Uft.E~ .O.-HU~rIPLEIED CCI RE~lSTERS TO BE TESTED
UP TO 14 -ON ftULT(PL£IEO REGISTERS pER RUN CAN BE
TESTED

uDt-OO

6
7

10
11

ti0201

00000

lJO~O?

00000
00000
agOOI

MLTPLI

~~e

RUlTIPlEIEO eel H~G1STEHS TO BE TESTED
UP TO 14 WULllPLEJED REGISTEH~ PER RUN CAN BE TESTED

.U"8~R

12

loS
14

"PT 14
lJO~OJ

lIQitQ4

"lid,
OQ206
"0~07

"0~10

U0211
lJO:i12
Ul1213

a.ao ••

lOGOI
.0800

oaooo
IUDDO
auooo
DOeGo

UU~14

00600

lJU4t'15

QUOaD

lJO~16

00000

UOC!17

00000

15

veT

00217

MULliS

~'N

L-l

16
17
2U

21
22
23
24

ItPT 14
U0220
U0221
OOC!22
UO~~3

U0224
"0~l5
UO~2.

U02l7

•••• 0

•••••
.00.'
•• ,,9
otooo
oaooo

00000
00000

OCT

TMIS LO'ATJOH Co~rAIN~ THE 81T NUMBER Of THE
fiRST "~l'IPleleD eel MEGISTkH TO SE READ.
81T
NU"8ERS ru~ SUCCEEDING ~ULlIPLEXED eCI REGISTERS
AME PLACED IN SEQUEftrl'~LT D~SCkNDING ~OCATIO~S.
ALL RULTIPLEXED AEGISTE~S MUST BE ON THE SAME CHANNEL

PAGE

2

P-50 "ULTIPL~XED AND NON-MULTIPLEXED CCI TEST WITHOUT CABLES
(10230
00231
00232
00233
U0234
002,55

25
26
27
30
31

00000
00000
00000

OUOOO
00000
00000
0023~

NONTAB

5TN L-l

THIS LOCATION CONTAIN~ THE IN~UT CHANNEL NUMBER O~ THe
rlHST NON-MULTIPLEXED eel HEGISTEH TO BE TESTED.
CHANNEL NUMBE~S rOR SUCCEEDING NON-MULTIPLEXED
eCI REGISTERS ARE PLACED IN SEQUENTIALLY DESCENDING
LOCAl IONS.

PAGE

3

P-50 MUl T I PL.B.ED AND NON-MUL.TIPL.EXED CCI TEST WITHOUT CA8L.ES
32

~JE

33

~

C11
I

CI')

34
35
36
37
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56

OO~36

OOe37
OO~40

UO~41
(JU~42

OO~43

110244
Oli~45

U0246
110247
UO~50

00251
UO~52

00253
00£54

00255
UOt:56

.\2 0 23~
~o 0 000

INSl
ENL NONTAS
BL.KJNT INT ••

32 0
~O 0
~7 0
~2 0
01 0
37 G
10 0
37 0
30 0
~o 0
36 0
U1 0
27 0
32 0
37 0

NONSTR

200
256
353
23'
24$

3,6
237
250
000
25l

303
353
242
236

243

~NL NONMUL
lJP MULSTR
STLo NONCNT
RESTRl ~fIIL. NONTA8
UCR L.-l
STL PHTLUC
ADD BLKINT
STL. L.·l
INT ••
lJP N
RJP PRINT
N
DCR NONCNT
PJP RESTHl
~NL INS1
~TL RESTHl

NON-MULTIPLEXED START L.OCATION

••

IS NON-MULTIPL.EXED INPUT CHANNEL.

PAGE

4

P-50 MUL Tl 'PL~XED AND NON-MULTIPLEXED eCI TEST liCITHOUT

57

i:JE

60

61

~

en
I

~

CABL~S

BEGINNING OF' MULTIPLEXED CCI TEST,

62

00(:57

63

OO~.o

~2 0 201
20 0 237

6~

OO~'l

~7

65
66

00262

67
70
71
72
73
74
75
76
71
100
101

UOe:64

.)2 0 217
01 0 26l
J7 0 3~6
J4 0 000
~3 0 266
01 0 000
~o 0 000

1J0~6J
LJO~65
tJO~66
UO~67

UO£70

0

J,~

uO;;-71
LJOe::72

~4

1.10273

C!O

(iU~74

~6 0 30J
01 0 3,4

(Ju,'75

,)7

0 265
0 3~5
0 274

IJOC:'76

~7

OOC: 77

.)2 0 :SOl

106

00302

lJU~Ol

M

,)1

0 2f:1C!
2oS7
052 0 217
~4

",-TPL.X
NONSTH
"LTCNT
MUlTAB
L-1
PRTLUC

0

INS2

STAHT or MULTIPLEX TEST

••

••

.4

••

L·1
PC

"

IS MULTIPLEX ADDRESS SELECT CHANNEL

1S MUL TJ PlEXED INPUT CHANN~L NU"BER
OUTINT IS ADDkES$ CO"PLETE INTEkRUPT ENTRY

INWATE
STl PRTLUC-l
lJP
HJP PRINT
UCR "LTCNT
f'.Jp RESTH2
ENL 11'452
STL RE5TH2
J"P NONSTH
I:NL MUL US
..I"P

INI~T

0 261

102

103
104
105

U0300

MULSTR ENL.
lJP
S'!l
~ESTR2 ENL
OCR
SlL
UUT
INwATE CLJ
OCR
DUTINT INT

PAGE
P-50

~

c:n
I

00

5
HIJLTl~U:XE:D

107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156

A~D

NON-MULTIPLEXED CCI TEST

~ITHOUT

CABLES

I::JE
U0303
1.10304
U0305
U0306
UU.s07
IJU310
IJU311
U0312
UOJ13
00;)14
00315
U0316
OOJ17
U0320
U0321
'"'0322
"0323
00324
1I03l5
lJO~26

110327
OlJ330
00331
"u332
00333
00,s.14
(,0335
liU336
U0337
00340
(,0341
00342
U0343
003,..
OU345
00346

P~INl

00000
J7
J2
J7
J2
J7
J2
37
J2
14
l5

a

3~~

0
0
0
0
0
0
0
0
0

344
357
34)
31 4
346
360
3J7
356

PRINT

I

SUb~OUTINE

I

~TL PRTLUC-l
I::NL T"O

~TL

L2
L1
R2

~H6

11 0 340

,s6
01
27
01
J2
.16
01
27
,s2
,s6
,s2
J6
l4

0 3,s4
0 360
0 312
0 314
0 34J
0 3.14
0 357
0 310
0 34l
0 3,s4
0 341
0 334
1 30,s
00000
,s4 o 000
24 o 2b~
1J040
00040
10500
10640
ll000
00002
14 o 356
ODOlf»
0035J
00354

I

OUT

ENL
:;TL
EIIIL
STL
I::IIIL
L:'H
CJP
SUB
HJP
DCA
PJP
DCR
ENL
HJP
OCR
PJP
ENL
tocJP

1~2

R2
F"ORH:N
CNT2
ONECH~

PHTLUC
L·2
FORTy
OUT
CNT2
Ll
Rl
SPACt:
OUT
CNTl
L2
CARfHiE
OUT
~NL LF'
FcJP OuT
NTN

••• ••

OUT
JP1P
ONECI'fR OCT
F'ORTY OCT
OCT
Lr
CARRGE UCT
SPACE OCT
TwO
OCT
IH2

CNTl

INNATE
1J040
40
10500
10640
12000
2

LSH PRTLUC

rORTEN DEC 14
NONCHT ~YN L+4
HLTCNT SYN NONCNT+l

ASR OR LOGGEH CHANNEL. NO.
rOR
rOR
rOF<
rOR
rOR

SELECTRIC
SELE:CTRIC
SELECTRIC
SEU::CTR I C
SELECTRIC

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

USI::
USE:
USE:
USE:
USE:

OcT
ocT
ocT
OCT
OcT

37410
5400
110
50
110

157
.It;,u
1 ~"

162

003r;,b
C; ;.: ~': ..> 1
00.".\6C
e> , j II

PRT!_OC SYN HlTCIIIT+2
:)ilN PfCTli,H':. <
CNTl
SH! C!l!~1·1
CNT2

E:NO

INTERRUPT TEST WITHOUT CABLES Ol8A
1.

Purpose of Test
To perform a simple "go-ne go" test on one to sixteen lnterrdpts.

II.

Description of Test
Up to sixteen interrupts may be
interrupt locations.

te~ted

by storing transfer commands

Il1

sixteen

The test prints the relative interrupt number in binary when ai~ interrupt occurs.
The printout format is "OOOOOOOOOXXXXX". where XXXXX is UOOOL - 100002.
III.

Description of Operation
A.

B.

Read in the binary tape of the test using the Ilootstrappect binary loader.

1.

Put machine in WRITE mode; depress the :Vlaster Clear button.

2.

Using the probe. load the X-Register with the starting location of the
binary loader (76028. 176028. 276028. or 376028); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape readel

5.

Turn the reader on.

6.

Depress the Start button.

Enter the test parameters
1.

Put machine in WHITE mude; deprc:-,s the i\1a..,t{:r t'il'dr

2.

Using the probe, load the

3.

USing the prohe, load the X-Hcg-ister with trw parameter constant; depress
the Start button.

4.

Hepeat steps 2 and 3 until all parameters needed have been entered.
Location
vI ist mterrupt

0:
of
of
of
of
of
of
of
v1
of
of

2nd ir.tern./1t
3rd interrupt
4th Il1terrupt
5th interrupt
6th interrupt
7th interrupt
8th interru;>l
9th interrup:.
lOti interrupt
11th interrupt
12th lr.terrupt

S-negi~~ter

Parameter
36
36
36
36

2S';'

264
271

276
36 303
'<&:'<1(1
u.&.v

uv

36 315
36 322
36 327
36 334
36 341
36 346

iHlltOli.

with the paramder iocatlUn.

Descnption
Transfer for 1::;t interrupt
Transfer for 2nd mterrupt
Transfer for ;~rd interrupt
Transfer for 4th lI1terrupt
Transfer for 5th interrupt
Tra.'1sfer for 6th interrupt
Transfer for 7th interrupt
Transfer for Rth interrupt
Transfer for ~th interrupt
Transfer for 10th interrupt
Transfer for 11 th interrupt
Transfer for 12th interrupt

16-1

••

Location

Parameter

of 13th interrupt
of 14th interrupt
of 15th interrupt
of 16th interrupt
of logger interrupt
240 8

36353
36360
36365
36 372
24 637
340XX

Description
Transfer for 13th interrupt
Transfer for 14th interrupt
Transfer for 15th interrupt
Transfer for 16th interrupt
Transfer for ASR or Selectric logger
ASR or Selectric output channel

(Load following only if Selectric logger is used; do not load if ASR set is
used for printout.)
244 8
245 8
246 8
247 8
2508
C.

D.
IV.

374108
054008
000508
0011 08
00110 8

Output
Output
Output
Output
Output

Code for" 1"
Code for" 0"
Code for carriage return
Code for space
Code for space

start the test
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe, load the X-Register with the starting location of the test
(2038); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Depress the Start button.

The test runs continuously, printing the relative number (1-1610) of any interrupt which occurs.

Storage
Number of locations used:

1778 (2008 - 3768)

16-2

PAGE

1

P-50 INTEfHWPT TEST WITHOUT C.S\.ES
1
2
3
4
5

00200
00200

OJ 000

00201
U0202
00203
00204
00205
00206
u0207
00210

01 0 243
37 1 243
23 1 200
32 a 256
11 0 243
20 0 233
32 1 245
27 0 214
J2 0 24J
10 0 255
37 0 24J
22 0 2Q3
J7 0 .::':>3
03 1 to" j
J2 0 2:>4
37 0 '377
32 0 244

80~iI

SAVE

P-50 INTERRUPT TEST wITHOUT CAYLES
200

TH 1 S ROUTl NE IS ENTERED wITH A NU"BER IDENTH'UNG THE
INTERRUPT IN THE ACCU"ULATOR.THIS NU"BER IS P~INTcD
ON EITHER ASR OR SELECTRIC TT~ER.

•••

6

7
10
11
12
13

14

.....
0':>
I

v:>

15
16
17
20
21
22
23
24
.5
l~

27
30
31
32
33
34
35
36
37
40
41
42
43
44
45
46
47
~:J

OO~l1

00212
00213
00214
0021S
00216
00217
00i120
00221
00222
liOi2l
00£2.
00225

OO~33

00234

23

OO~26

00227
00230
U0231
00232
00~35

J2

"0~36

~2

OO:i!37
U0240

.14

OO~41

23

OO~42

01

EN~

T.BI.~)

SUB

MA~I(~R

lJP DON!:
eN",
PJ;)

e r~L

HA~o(i:~,l

F'~r"~c
"'~~I(~ol

lDO 1 )

J

~TL.
)~J

r'llD..JN;

;)T~

"l~II-="

,.iT"

.

.,P'ltt .1_ "
~

,

::rt.

O'~

~~H

a 224

TAtJ~~

CJP

I..~

1.1

sua

0 245

.;

::: "1 R

ZER:.;:';

kJP OUT
OCR CNT
PJP L.l

0 231

0 377
0 220

0 246
0 2oS?
0 250
0 237
0 2J4
a 2~6
o 200S
00000
a 000
o 241
o 000

~

14

.,. .....
,

,:,"'~

2~3

14 0

l5
11
36
01
27
32
J6
32
36

DCR "ARKER
STI. HARKE:R,I
CL.J SAVE.I
"START

EN!. CARRIIE

RJP OUT
t"'l. L.r

DONE

RJP OUT
CLJ 1.·1

ENI. TAIlLE)
SL.J START

OUT

,,

P·50 03eA

. ••

OUT
CLJ L·1
DCR PC

TYPER OUTPUT CHANNEL

PAGE

2

P·50 IHTERhUPT TEST wITtiOUT CABLES
51
52
5~

5"
55
56
57
60
61
62
63

002 .. 3
002 ....
002 .. 5
002 .. 6
OO~47

00250
U0251
00252
00253
00254
002"
00256

00253
1JO"0
000 .. 0
106"0
12000
10500
20000
200B-D
20000
00377
00016
00001
00253

"ARKER
ONECHR
ZERCHR
CARRGE
SPACE
Lr

OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT

TA8LE
lJ040
.. 0
10'''0
12000
10500
20000
20000
TABLE
20000
IEQU 377
CNT
GEN
MltD

tiRO
tlRD

rOR
F'OR
rOR
rOA
F'OA

SELECTRIC
SELECTRIC
SELECTRIC
SELECTRIC
SELECTRIC

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

USE OCl 37410
USE OCT 5"00
USE OCl 50
USE oct 110
USE oct 110

PAGE

J

P-50 INTERRUf'l TEST WITHOUT
64
65
66
67

00~60

70
71,

00261
00262

7'2'

UO~63

00257

C.8~ES

F"IRST INTERRUPT SUBROUTINE

00000
32 a 26J
.s6 o 200
l4 1 257
00001

liNT

ONE

ENI.. ONE
~JP SAVE
F

225

-;J

l26
227
230
231
232
233

I

l34

235
l36
Z37
240
~41

242
243
244

THIRTEENTH INTERRUIPT SUBROUTINE

ENL. THRTEN
RJP SAVE
RTN
THRTEN DEC 13

t!20
~21

.

, ,

,,

.

INTERRUPT NUMBER
FOURTEENTH INTERRUPT SUIIROUT1NE

ENL. FORTEN
RJP SAYE
RTN
F'ORTEN DEC 14
INTERRUPT NUMBER
FIFTEENTH INTERRUPT

SU~ROUTINE

•••

ENL rlFTEN
HJP SAVE
HTN
F'lrTEN DEC 15
INTERRUPT NUMBER
SIXTEENTH INTERRUP'T SUBHOUTl NE:

•••

ENL SIXTEN
f(JP SAVE
RTN
SlXTEN DEC 16
INTERRUPT NUMBER
END

P-50 CC~ TEST WITHOUT CABLES D39A
I.

Purpose of Test
To perform a simple "go-no go" test on one to sixty-three

II.

cc0

registers.

Description of Test
All contacts are set to one; then, the program delays one second, and all contacts
are set to zero. After another delay of one second the cycle is repeated.
Contacts are set to one by an output of 377778 on each multiplexer address with
set channel. Contacts are set to zero by an output of 377778 on each multiplexer
address with reset channel. Time delays are program loops.

III.

Description of Operation
A.

B.

Read in the binary tape of the test using the bootstrapped binary loader.
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe, load the X-Register with the starting location of the
binary loader (76028, 176028, 276028, or 376028); depress the Start button.

3.

Put machine in RUN mode; depress the Master Clear button.

4.

Place the binary tape under the tape reader.

5.

Turn the reader on.

6.

Depress the Start button.

Enter the test parameters
1.

Put machine in WRITE mode; depress the Master Clear button.

2.

Using the probe, load the S- Register with the parameter location.

3.

Using the probe, load the X-Register with the parameter constant; depress
the Start button.

4.

Repeat steps 2 and 3 Wltil all parameters needed have been entered.
Description

Location

Parameter

of CC0 completion interrupt

243118

200 8

N

Number of CC0 registers is N (1-778)

277 8

Multiplexer
Addresses

The multiplexer addresses for the
CC¢ registers to be tested start in
location 2778 and are ~tored sequen ..
tially in descending locations. The
lowest location is 2018. A multiplexer address contains the set channel in bits 0-5 and the word in bits
6-11. The reset channel is assumed
to be one less than the set channel.

277-N+1
17-1

Transfer for CC¢ interrupt

C.

D.
1\·.

Start the Test
1.

Put machine in WRITE modei depress the Master Clear button.

2.

Using the probe, load the X-Register witil the starting location of the test
(2778)i depress the Start button.

3.

Put machine in RUN modej depress the Master Clear button.

4.

Depress the Start button.

The test runs continuously.

Storage
Numher of locations used:

1618 (2008-3608)

17-2

PAGE
P-50

1

ceo

'fEST

~lTHOUT

CABLES

1

P-50 CCO TEST WITHOUT

2

3
4
S
6

~

-.;J

I
~

00200
U0201
U0202
OOt:03
U0204
U0205
u0206
U0207
U0210
U0211
U0212
00213
u0214
00215
U0216
OO~17

U0220
1I0~21

u0222
"O~23

u0224
u0225
1I0~26

00227
00230
(10231
U0232
(j0~33
1J0~34

00£~5
f
i

00£36
U0237
u0240

u02"1
00~42

J

lJ02~3

00200
00000

80HG 2ilO
NUI1REG uEC
. ONE: SECOND.
THEN SETS ALL CONTACT OUTPUTS TO lENO AND RESTARTS
OO~OO

00301
U0302
00303
OOJ04
00305
UO..s06
U0307
U0310
UOJ11
UU312
UO;)13
Oo~n4

U0315
U0316
U0317
UO;)20
U0321
UOJl2
U0323

\JOJl4
UOll5
uUJ26
UOJ27
003~O

UO~J1

uOJJ2

65

uOj,53

66,
67'

ilO-SJ4
U0335
00.)36

701
71

UU.,),S7

J2
37
J2
J7
J2
J7
J2
J4
l3
01

01
U1
27
J2
01
'l.4
l4

0 3,1
0 357
0 3,3
0 307
0 200
0 356
0 3,0
1 277
0 310
0 000
0 307
0 356
0 300
0 3jl
0 101
a 317
0 3~0

~4 0 321
l4 0 3ll
l4 0 32.5
i4 0 324

'l.7
J2
J7
J2
J7
01
'/.7
J2
10
J7
01

0 31'
0 200
0 3jb
0 3"

0 360
0 3j'
0 34l
1 .soU
0 3~4
1 3bU

0 3bO

STAHT

E::NL T.. O
~TL RESET
lLOP
E:NL OuT IT
STL OTCOM
ENL NuHRt:G
~TL REGCNT
E:NL MINU~
OTCOM OUT ADOR,l
CLJ L+1
DCR pc
I NHcPT OCR OTeOM
DCR REGCNT
PJP OTCOM
':NL TIMCNT
DCR
OCR ACC
J"P L+l
..IMP L+l
J"P L+l
J"P L+l
J"P L+1
..I"P L+l
t"JP OCR
t:NL N\JMRt:G
STL kElieNT
ENL tjEGAUH
~TL

FIX"U~

DCH Rt::SEl
jJJP

LOPl

CLEAk

t:NL FIXAUH,l

"DO O,'4E
~TL

FlXAU~,l

OCR F I XAUK

INTERRUPT RETURN
NEG AFTER LAST HE&iISTEH IS OUTPUT
ONE SECOND TIME DELAY

PAGE
p-§o

ceo

"

72
73
74

75
76
77

100
101

I-'
-.:J
I
C)

102
103
104
105
106
107
110
111
112
113
114
115
116

TEST "ITHOUT CA8LES

00J40
00341
00342
U0343
00344
U0345
U8;)46
00347
U8l50
110351
00352
UOoS53
00354
U0355

01 0 J56
~7
~4

01
01
01
l7
~4

,54

0 3JJ
0 277
1 360
0 360
0 3~b
0 34l
o 301
31777
00002
17717
1 277
00001
00277

003~6

00357
00360
00000

OCR REGCNT
"'JP LOP2
",,"P STAAT

CLEAR

DCR r I XAOH.1
DCR F'IXAOR
OCR REGCNT
~JP L-3
J"P 1L.OP
"INUS OCT 37777
TWO
OCT 2
TI"CNT OCT 17777
OUTIT OUT AODR.I
ONE
OCT 1
BEGAOR OCT ADDR

REGCNT ~YN aEGAUH+l
RESET ~YN REGCNT+l
F'IXADR SYN RESET·1
i:ND

IJl.

lntroduction .. -- -~- ...... _____ ..
~~
Console ProgliILo:,..y .---.------------ •• -- 5
F. Octal Drnap ------------ .. ------------- .. ----~-------------- 6
1. Octal Dump from Main Hc:mol'Y .. - ........ ------------------- 6
2. Odal Dump from ExLended 1.:<.:ri1ory ._----- .. -..,-------- .. --- ..• 6
G. Run on Hach:ine -------- .. -- .. ---------------------------- .•• 7
H

Dr.

Tv.

V.

_ _ _ _ . . _ _ _ _ ~ _ _ ~ _ _ •• _ _ _ _ . . ". _ _ _ _ . . _ _ _ _ _ _ .. _

.. _

• • ~_

Key to Error Printouts --- .. --------- .... ---------------- •.• --- .. - 7

A8C:JJ~DC]) Code Table ---- ... - - --_ .. - .. - .. - - .... - --- ----- .... -- .. -~, •. -~.
Binary TdI'~' Format - .. --- .. - .. ------.,--.,-----~.,- ... - .. -- .. --.~--.---- ...

18-1

8
8

I.

Jni.rocl.uct.ion
~1e

p:COe;l'Ctk!Jlcr' r. COl1s(lle ]JrOe;:rRliIB fucilitat(~ COln:.1U!licntj.on lllth tho P-50
CO)!lpntcr ~ The pJ.cJcaec provides a menus of l03.clinG ]Jrograms J executing
proGrams J lODcling com;b.nts or inf:)tru.c,tions J and dumpine areas of main
and. cxtcncl.od core mernory. Core locations may be dumped in binary OIl
tal)~"' 01' in oct,alon the ],eybo2.rd.
The proc,Tu, .. ,'!lcr'f} (;ol1Gole oJX;l'atC:1J "trit.h:ln the priority structure of

the X50F <.:xccutive r.yr>tem for all of its functions, and its calling
priority is estnblir;hud for a particular SyctClll when tho execut:J.ve
Sy:.;i;(;!lll iG initic,lizcd. Note that thiE: proGrmLlrll~r's connole is 1ncluQed
l.,Hh standa:cd cxecutive syGtem X50F only.,
BoToro initlatincs a. progr8mmer's concolc function, the ASR :punch and
render should be turned off, '17.1C11 , to cain the computer's £Lttontion, the
Attent:ton J'nt.cl":rupt But.ton is deJ):t8Sset1., Ti1c attention interrupt will
have anyone of two or four effects depondine.; upon tho initialization
of n-eCOP1'
the.: messaGe vriter option for the progranllller'e com,ole.
a)

If' nc:i.ther the progralliIher If; console n01' the device 0 proeram
is ::urrcntly runninu;, thE~ p:roc;ra.irl!lJCr' s console programs
will bo put into the bJd(linc ct.otc,

b)

:rf the programmer's console in not currently running but the
device 0 proeram is runninG, t.he flee PCFLG will be se;:t and
the proGrp..mmer' s cons ole programs will be sus ponded,

c)

If the progrnmmrncr' E console is currently running and the'
device 0 proeram is not running; the progr&mmer's conEole
proGrams will exit to TOPLOP ane. the ASRset ,.,ill be turned
off,

d)

If the programmer's cone ole is sUi31xmdcd and the devj.ce 0
program is running, the flag PC'FLG will be cleared and the
pro[p'nmmer's console progralllf> l1ill be turned off.

\'lhcn the prozrc= mmer I D console programs are permitted to run by the
executive Systclil, the ASR Eet will be tU1:ncu on and input from the
ASR set will be requested. Input consists of a two-letter mnemonic
folJm"cd either by a space and up to four constants or by a return. If
morE: than tvo letters p:cecede the space (or the return), only the last
two ",Hl be considered, Tne resulting t.To-letter mnemonic is then
comr<3.red to the de fined mnemonics. If it is not fow1d equal to any,
"ERR 1" will be printed and the programmer's console "Till exit to 'IOPLOP
and the ASR E;et ,,,ill be turned off.
If th.: t".,o-lettcr m.ncmoic is found equal to a defined mnemonic, a transf'er
to the proli2r program will be set up, and if a space followed the mnemonic
code, any constants preceding the return will be input, '!he number
of constant.s will depend on the function being initiated. Const~nts
must be entel'cd in octal or deCimal; a plus or minus Sign at the begjnning of a constant specifies it to be a decimal number; unSigned integers a:t'e
18-3

- 2 CC)l!sjcl('rccl to b~ :i.n octal. C()!!wlt~nt~ a)~t' t(~1"m:tnr~tcd by a. slaf'3h (/) n:·
by ~~ lc:turll~ n~(~il;"\l Etnli. octnl C()(IGi.L'!nh: I!lL:y bcrch nr)pc.:ra· on th(:l:~:Jrl(!
liu("! of in"t1ul.. 1:," u c'ba:£'nt!te:t j (3 inj;J\lt ()tbt~r than en oct.al or QEdm:tl
conHtallt tt:~;n(." ,r1D. 1)(;: prInted antlt.hc PJ.:()((,:C<:lul!'ner' S com;ole w11l (;AH
to ~·OPJ·JOP dI1d the /\.HI< set "rill b8 tuned. off.

If the corJ.:8ct.:loll c:hnrncter left TJO.rcntb'.:1uls
follouln~ the lEll3t 131D.[jh 01; tl.c, ~Pi\CL~

digit,(-J

It ( "

E:lI'~

is encountE:red,. all
ignored.

If Tilore thml fonr const.nntEl f4,re U]t.'.~·r,:J. 1'(:i'o:l.'e fl. r(1turn .• "ERn f''' '\-Till
be )?r:intuCl. uJt::'d.f1cc1 th2.n are requ:l.r~a. by the :f.'uuC'tion bein~ :lni tiCl.t~d, "EHI< ~~"
wD 1 aleo be ))1' in t~:d anC'l the p:coGl'a1r,!llcc)."' H conGole will be turned off.
When u rctm"ll hU£l b8l!n 1nJ!llt to tllc prO[!;.l·r.;·Ii.li1t~r' EI com:olc, the troor:lfcr
to the requ~~;tcd. prOc;ratllll1Cr f S corJ801e P:rOlSl'c.m if:: -put into effect with
the nllLibor of constants in the a C(:unlulFl to:..' (zuro vhE'l1 a return 1'0110'\0;;:'.:1.
the hmemonic ~oae) nnd with the cons te.nts r tared in tbe order tliEl t they
"rel'e ill}Ylit in c:rl~J, 0", q1N'L I • A line :f,:t;r} ml?ly p:re('e~lc the retuTn; this
ch:::rac:ter is fl.hTay~~ j gnorcQ on :i Ylput. \-I1iU1 the progr.").ulli1&r' H cou£ij],e
prclC;r'tl.ln cUllplctc.:s tho activity rcqu:co,:;SlC::ll) fultht~r conBtants W:ly 10
required. ~J'h~:4C: are entered in tl'ie r:Urtl,:: IllUnl1(;r nn the j.nit:lftl COl1stanth
that; iO, in decinlF.J.l 0:1.' octal, 8CpEtrutE:J "uy slashGs, and terminat8d ·H!t.ll

a -

a retun ••

Th:if; proc;:r'A.luYfi('l" £l console ~ncJ~I:1C:l' contains eleven dcfln~d fUl1et:tonr.:
Binary L('l~t·J., l):lnHry l\lJ1ch f:rom l'/J."L:i.Ii l'\I~mol'Y, H:i.na)~y PUrl(;h f.r()ln E:.d,en\1Pll
Memory, Check '1.'alx~, Set Lim.its I'or llInin Meillory, Set Limits fo:1' Exlir:md.l"(l
M~rr ~ry, NllJ1J(Jr:tc.

LC'lad. into Mn:1.n ~1~rl\OrY1 Numeric Load into Extcllu.cd Mr",:a(':L'Y,.
Oct.al Dunil) from M:1.1n Memory, Octal l)ur.1p from E,r,tencled. Mi:'mc;>ry, nun on
Ml'ldd.nc. :P-rov1o:ton for more :pr()g:r-~me to fit s)?ec1f1c installatiol1':l l~H~.
b~c-rl lo!:\dr; :Ln Ulat there io room fnr ten mor~ mnl'!lnonj.cB to be defj nr.~d C!1a.
ten more trf-Il1r.f.er locations to be insertc?:u.

'l'he definecl

:proB1·I.lnllnC~r's

conGole functions are aesc):'ibc(l bel.ow.

:(n iu:pu.t

cJ(~.mJJ1('8, '-" rq)rescmts space anl;' I~ rcp:!'escl'.Itr. rG tm:n.

Hnerllonj~
Numb~r

code:

on constants:

BL
zero

When this runC' r.:i.on j~ i.n~tiutcd, a binary· tape in the fjti).~1dard P-50
binery for'T!.::lt wlll b2 loaded through t.he 1)rogrmnrn0r's consolE:! tap'.J l'e~c'.(~T
int.o ·rnain or extended core. The bi.no.TY load i'unction ig controlled
by control "'ords on the binary t.OPe: so that no constants nre input. {SI::e

sect.ion on BinF.lry TolP:: ForilJat).

18-5

- 3 If any conotants arc input, the mensage "ERR 2" will be printed and. the
prognllmner 'n t;onr,olc "rill be turned off. If a character w1 th even ~rlty
is dctecte:o on the binary tape, "ERR 4" vill be printed; if the checl~~
sum on the tr.p~ does not com:pnl'c t.o thl"! sum of the words on the top.) J
"ERR 5" Vlill be printed. If e i thor 01' these errors occurs, the ASH 8et
will be turnt~d off following the printinfl of the apI)Topriatc messaGe.

1.

Binary Punch from Main l-krr.ory
Mnemonic code:
Number on constants:

2.

BP

0, 1, 2

Binary Punch from Extended Memory
Mnemon:i.c code:
Number of const.ants:

XP
0, 1, 2

The mnemonic code determines whether main memory (BP) or extended memory
(xp) will be referenced. Each is a separate: funcUon.

Depending upon the ntllrlber of constants which are inr)'ut, 8 core area or
core locatj on, n transfer code 1 or a stop code 'v'ill bcpum:hcd in binary
by the programmer's console punch. Two constants designate' a core ar€!a
or loca tiol',); one cons tant specifies a transfer code and the main memory
transfer location, no constant results in a stop code.
If two constants are input and the first is not less than or equal to the
second, "ERR 3" "'ill be printed and the programmer's console will be
turned off.
When using this function with a high speed. punch, the turning on and off
of the punch "ill be done via proaratnmj.ng.
When the punch on the ASR set is used, it r.lUst be turned on and otf manually.
Since input from tbc keybom:'d. will be punched on tape if the punch is turned
on, in addition to the binary output requested, the following procedure
is recommended:

1.
2.

3.

4.

5.

6.
7.

8.

Turn punch off.
D2press Attent"ton Interrupt Button.
Type on keyboard: BP..,xx/xxl 01 XPwXJ:./xxJ.
Turn punch on--1eader will be punched folloHed by requested area
in binary.
Turn 'Punch off.
T,ype ~n keyboard: (XX/XXII.. (another area), or (XXtl (transfer code) or
(.2 (stop code). Ahrays begin with the correction character" (".
Turn punch on--1cader Hill be punched follovred by an area in binary,
or a transfer code or stop code.
Turn punch off and continup..

18-7

- 4 .Ji~)C~lmples :
To obtain a bina~y t..n))c of 0 program curJ'(mt.J v loea'lied in
mfiin memory locc.t.:Lons 600B
72;:;8 and of another ;progi."ar:t in location
101210 - 12h 1110 Elnd to put a traw3:f'er to locatioll 6108 at the end of
the tape, the 'f'ollmfing should be cxe(;uted:
M

BR..6001'(2 3J
( +1012/ +l211h J.

(610:1

'1'0 obtain 0 binary tq)C' contelillg the contents of cxtemlcd core

loe~'t,j.or!::;

600A - 72 38 and 1012 10 ~ 124h lO ' and tel'TJilnClted 1o1ith a stop coo.o , tho
folYo\iing should bE, executed:

:t

xp~6oo /7? 3
(+ 10.1 2/+121f}j ~
1)

Mnemonic code:
Number of const.r.mts:

OT
zero

A b:l.nary t6.}.\~: in the f'tHndard P"50 binnry fOJ'mat wiD be compared, word
by ,,;'ord, to the content.~~ of tLe prope')" area of eithe-T m9.in or extended
core. If any discrepancies occur, the C01'1: 1()cation, the contents of the
tape and the contents of core will be printed in the octal dump format.
An "A" "'ill precede an extended core address. The process will contin'~c
until the end of the tape. The tape will be p::lrity checked and chncksum checked at the Sc,rrl0 t:ilne.

If any conskmt;j al'C ilJput foJ.]owbg the function code.:, "1"RR 2" will be
prJnted und the programmer's console ",n1 be turned off. If a parity
error is d,~tcct(d, "ERR 5" will be printed
'l'Ilese errors both turn off
the programmer' [. console p.rograms and the ASR set.
I

Example:
CT~

762
1102

23200
1

~66

377'(7

A202l5

20001

A

32301
37777
37775

20133

The first word folloving the location is the contents of the tape; the
second is the contents of core.
When the programmer I s console reader is used for this function rather
than a hiGh speed reader, the pl'intine of one d'lscrepancy will alter the
I/O sequence emel fm'ther input will be incorrect. Thus, this function
should be used "'ith the ASR reader only to verify that a tape has been
punched correctly.

18-9

- 5D. Set Limits
1.

Set Limits for Main Memory
Mnemonic code:
Number 'or constants:

2..

LM

2.

Set Limits for l!.'xtended I>fernory
Nnemonic cod~:
Number of coastants:

XM
2.

vfuen either of the s~t limit functions is called for, two constants should
be entered prior to the fjrst return. T.nesc constants define the core
area or location usable by the numeric load functions.

If the first or both cOllstantu arc zero (0) the limits are set to ~ero
and the,entire core is protected. (1:'he lim~ts are initially sot to
zero). If the fi~st constant is not less than or equal to the second
constant, "ERR 3" will be printed and the pro~raml11er's consOle will be
turned off.
EXElI:)plc El :
To set limits in Main Memory to the core area 100008 through 1010°8 1 the
followine should be executed:
LM...lOOOO/IOI0p~

To set lilili ts in extended nLclllory to one location 700°8' the following
should be executed:
XMv7000/7000~

E.

~ic

1.

Load

~umeric

Load into lJIain Memory
Mnemonic code:
Number of constants:

2..

NL
zero

Numeric Load into Extended Hemory
Mnemonic code:
Number of constants:

18-11

XL
zero

- 6When either of the n:wllcrlc load funct.ion8. is called for, no constants
should be entered prior to the first return', Successive constants sCpAl'o.tcd
by l'cturnc des:ignated the locations to be modified and octal or decimal
data, Both functions are terminl1ted by the right parenthesis ")".
If an attempt is mno.c to enter data '\o'ithout first spec:l.fy1ng the beginning
loca tion, "ERR 3 11 • will be printed and the pl'ogrammer I s console and ASR
set will be turned off.
If Em attempt is made to enter data into n location outside the core
limits, IIER~ 7 11 vill be printed end the proerum.fner ',s con'sole and ASR
set will be turned off.

Input:

Location:

Contents:

NL~ or XLll

::: 1022~
24026,2
+17t1
+27,l
21d.

1022
1023
1024
1025
1026

24026
00021
00033
00021
00033

1130
'1131
J
379(37073~ 1132

10073

33~

=+600tl
10073J

37073

)

COlTlJnent:

CalLing Sequence' for 1.11'\in or Extended Memory Loading
Origln in octal
JMP instruction entered in octal
Ded.mo.l Da ta
Decimal Datn.
Octal Data
Octal Data
New Orie;in in decimal
ADD instruction entered in octal
Do not change this location
SlrL im; truction entered in octal,
correction character used
Terminal character

The correction character" (" may be used with this fUllction, Howcv~r,
if an error occurs' uhen ty:ping the origin, note that the equals 'character
which vas input is not ignored.

F.

Error:

::::10782

Correct:
Incorrect:

=10782(10772
=10782 (:=;10'772

Oc tal Dump
1.

Octal Dump from

~1a in

Hcmory

Mnemonic code:
Number of constants:
2.

Octal Dump fran Extended

¢D
1, 2

~1emory

Mnemonic code:
Number of constants:

18-13

XD
1, 2

- 1 De:p:::nding U]XA1 the number of const~;.Llt8 ~:'bic:h arc specified, these pj:'og=rams
will :prill t tbe contents of El core areEl. or a location in octal. !f tuo

copst.ants aI'\;! given, the contents of the cere area so def:ined wil1 bu
output. 8 "T01'd.::: 1,81' linE: "T:i. th the addrcsB of the first i.fOrd at the bog:ltming
of each lj.ne. An "A" precedes the address of the first i-lord for extenued
core dumps. If one const~llt j.B specified, the ad.dress ~.J'hich was input
and the contents of the location will be pr:i.nted. A return alone (no
constantz) sign:tfies the end of request.
If bJ'O constants are spec:i.f:icd and the Hrst is not less than or cq'u~l
t.o the sQcond, "ERR 3" will be printed and th~ IJrogl'amI:18l' I s console E<.n.d
ASH £let w'11l be turnod off.
Examples:
OD..:.+210/ +220~
322 32015 11(n4
2~r2l6
20216
332
h65/~72l~'
1012
465
1053

a

XD +503/+51~!1
A ~r6'r
201'77
A .7Tr
1777

2,(216
3

20371

3201)

1061t

33

14

62

10100
16553

10267

21031
37221+

1072
2030

1047~

A 1047

27212

32014

10777

16000

30010

32602

sl

Mnemonic code:
Number of constants:

RH
1

~:n:ls function transfers control to the loct:.tion specified.
If exactly
one constant is not input, "1.1111 2" will be printed and the programmer's
console and ASH set w11l be turned off.

The pror;ran thus initiated can be terminated manually de:preasing the att.ent:f.oli
interrupt button or turned off by having it exit to EXIT in the att~ntion
interrupt routine. !lTote that all refE::rences to the running sublevel il'l this
program must be for the progrEunmer's console sublevel.

TIl.

Key to Error Printouts
ERR 1
ERR 2

ERR. 3

ERR 4.
ERR 5

ERn 6
ERR 7

Mnemonic error
Constant error
Format error
Parity error
Checksum error
Illegal character
Out of limits

18-15

.. 8 -

BCD

C1wracie:r

ASCII

AGCII

oo------o-----·--()(;O---01
02
03

1

261

2

04·
05

II-

----110·--·------::-·-----

---055

41
!12

J
K

312
11.3

1/3

L
M

314
115
116

06

5
6

262
063
264
065
066

11

9

0'(1

51

R

322

12
13

t

~16

(-

137

r:

52
53

111

Rf.3turn

3

44
lf5
}~ 6

N

¢

317

.f1.l ____ .--:.r_ . _. ______..R6'( ____ ____4~L __ _ _-L_____J:~O
10
8
2'(0
50
Q
321

275
.215
072
2'r6

15
16
>
11_.________ .~ ____________Olt 1__
20
1053
21
A
101

_

$

*
J

Go

Spa.ce

61
62
63
64
6)
GG

I

B

102

D

303
104

E
F

306

67

X

30

H

D.O

'(0

Y

31

I

311

71

Z

32

?

0'(7

r{o

33
34
35
36

•
)
(

056
251
333
074
2lt 3

72
73

22

23

~:h
2)

26
2'

3'(

c

305

_._CL___ ~07 __

<

II

011.1,

252
~)5
335
)6
;
273
__ ...5 ~L __ .____f!P________:iQQ.
Jll

74
75
76
'(7

S

2110
257
123

T

32l~

U

125
126
327
330
131
132

V
W

,

(

245
254
050

\

246
134.

Line F(;!ec1

012

&

On a bina-ry tare, one word conGi[;ts of three charActers. Each charact.er
cont8im; ej ght levels; lew·1s one through six contain o.a.ta unless the
word is a control word. Each character is punched in odd parity and the
pari ty bi t ,.,hen prt~set Elppea:cs :i.n the eight level.

50 ..rord in core COT! tains III b:l!cs; the correspondence betlTeen a
core w'ord e.nd a lrord on the b ina:ry tape :i s as fo11m?s:

A Prodac

Bits 12-13
Bits 6-11
Bit.s 0-5

18-17

~Jaracter 11 levels 1-2
Character 21 levelS 1-6
Charecter 3, levels 1-6

- 9A :punc:h in the seventh level
tbat 'the wOl'd. 10 checksU!D.

elf

thE; fiI'l'3t c:haracter of a '\-TOrd 1ndice.te&

Levels 3-4 'of the :fhflt charcwter of a \'To.eel a r<:: ahioYf3 zero; they arc
1.6nored. Lc:vclG 5-6 (lefjn~ u control \vo:['~l--the f'i:rst ',ford on a binary
tape alld the first word follCl'ling tl checksum arc control words.
The follmring clescr.ibcs tbe d:1 f:['l.>ren~e3 f'tlU.:'nc; the contI'ol wordd and
their eff8ct:; 'dhcn londed throne;h t'hc binar;y loader:

A.

IJoa<'l Unin n(~mol'Y iVora. Zeros j.n the fifth and sixth levels of the
first charactel' of a corn;.rol 'tvord define a load main memory word.
£il1bsequ~nt. (lata 'l-rill be stoTed <'Uroctly int.o successive locations
in m!'lin r.l~~1;10I'Y start:l.ng ~,t tbe location specified by the data in
character 1, levels 1-2, and chf)Y.'{4et.ers 2 and 3, l(!vels ~ .. 6.

B.

Loatl Ex tended. Hemery Word. A zero in level six and a Ol'le in level
five of the first character dei'in(' a load extended rr.emory word. Sub ..
sequent. du La ,.,U1 be sto:J'ed directly .1.nto succeflsi'. (. locations in
extendt:'cl core s1...Hrt:ln(,; at the lr)catiml spcci:{'j.cd by the data in
charE1ct{'r lJ l<.~vels 1-2, ancl chaTHctE'X'f~ 2 and 3, lcv~~ls 1 .. 6.

C.

Transfer Cont.rol \lora.., A OM )Jltnched in level s:!x a.nd a. zero in level
five of the fj rat ch~racter of R control wO.t'd defi]'~('! a transfer control
'Word. Machiric! control 'I-'ill be tran6f~rred to ~he J.ocation spec:tfiea
in the remaining a.ate. levels (not all ones).

D.

IJ()ad Stop Hord. This control word consists of a :ptn1ch in level six
of the f:!.rst chawl.ctcr" z!.ro in level 5, and all OnfJE; :punched in the
rema:l.nine; un toa lcvcle. Uaddne control is transi'errod to the :priority
cxecut:l.ve, thus tenn1nating the lORding process.

18-19

APRIL, 1969

p-so
PRINTED CIRCUIT
CARD DESCRIPTIONS
HAGAN/CSD
TRAINING DEPARTMENT

Westinghouse Eieciiic Corporation

TAllLE OF

SECTION I

CONT.ENT~

MAIN FRAME
Page

Title

1-1

Automatic Reset 1AR3 . . • .
Bit Card 2BC1

2BC2

Core Pulser 2CP1

3BC1

2-1

4BC1 .•

3-1

3CP1

Designator Card 2DC1 .

4-1

External Interrupt 3EI2

5-1

External Pulser 1EP3 - 2EP1 .

6-1

Half Select Card 2HS2

7-1

Interrupt Scan Control 2IC1

8-1

Interrupt Filter Module 4IF1 - 4IF2 .

9-1

Isolated Interrupt Filter Module 5IFI - 5IF2

10-1

Inhibit Paddle Module 31Pl. . .

11-1

Instruction Register Card 2IRI

12-1

3ml.

Low Voltage Sensor 3LV2 . . .

· . 13-1

Memory Diode Boards 2MAI - 2MB1

· . 14-1

Memory Enable Board 2ME2 . .

15-1

Peripheral Driver Board 2PDl

16-1

Pull-Up Resistor Board IPU1 .

17-1

Sense Amplifier Card 1SA2

ISA3

2SAI

2SA2

. 18-1

Sequence Control Card ISC2 . .

· • 19-1

S Register Data Transfer 2ST2

· . 20-1

Timing Card 4TCl . . . . .

21-1

Z - X Transfer Card 1ZX3.

22-1

TABLE OF CONTENTS (Continued)
SECTION II

INPUT/OUTPUT
Page

Title
Analog Control Module 3AC4 . .

• • . • •

10/11 Bit Analog Output Module 1A01

1A03 • • . •

1-1
2-1

5 Bit Reversible Analog Output Module 1A02

3-1

High Speed Analog Output 4A01. . . . • • •

4-1

Analog Point Selection Module 4AP1

4AP2

Analog Word and Channel Trap 2AT1

2AT3

.•.•

5-1

ISR1

6-1

Contact Input Buffer Module 2CB4 thru 2CBS

7-1

Channel Driver 4CDl . .

8-1

Calibrator Module 5CLl

9-1

Contact Input Multiplexer Module 3CM2 3CM3

10-1

Contact Output Module 2C01

11-1

2C02

Counter Module 4CTI. . . .

12-1

Document Channel Driver 4DEl

13-1

Phase Locked Oscillator 1 PL4

1 PL5

14-1

Power Supply Switch Module 2PSl

15-1

Reader Buffer Module 2RB3

16-1

Span and Gain W /Input Buffer 3SBl

17-1

Sequence of Events Interrupt Card 3SI1

3S12

18-1

Selectric Interface Module 2SLl . . .

19-1

Model 35 Teletype Input Module 2TN1

20-1

Model 35 Teletype Data Buffer Module 4T01. •

21-1

Tape Punch Amplifier and Control 1 TPI .•

22-1

Model 35 Teletype Control Card 3TSl

23-1

Word Driver Module 1WD4 . . • . • •

24-1

AUTOMATIC RESET lAR3
A.

GENERAL DESCRIPTION

The Automatic Restart Card contains circuits to provide the following functions:

B.

1.

Dptpd whpther the ccntral processor was running or stopped when the low voltage
sensor applied a clamp to the memory suhsystem.

2.

Automntically rc'sta;--t the central processor upon resumption of power if the machine
hnrl stopped prior to the clamping of the memory.

CIRCUIT OPERATION

Drawing 74JA346 elhows the run detection circuit. Pin L3 goes to the final tap of the delay
lilw timing chain. \Vith the central processor running, pulses periodically appear at this point
:lnd are filtf'red to provide hase arive for transistor T5-1, T5-1 conducts turning on the lamp
ill (Ill' "start" pllshhutton and [.Iso removing the base drive from transistor T5-2. With T5-2
,'utpff, gate' drive is provided to the SCR, SI-I, which serves as the run detector.
If the power supply fault contacts close providing +26 to pin L14, while SI-1 has gate drive, a
is ci rClllated in the set coil of the histable relay M2-1, The setting of M3-1 signifies
thnt the central Vroc(:ssor was nut stopped when the fault1ccurrect. Upon power ~esumption
auto restart is inhihited by the N~ contacts of relay M3-1 and the auto restart fault lamp
:\121-1 will he on. M3-1 is reset by manual sbrting.
,~urrcnt

If. ho\V('ye r. in l'espons~ to the power supply failure interrupt, the central processor comI)lpthl its tnsks and stopped prior to the closing of the powel' supply fault contacts, base drive
would he removpd from T5-1 which in turn would cause T5-2 to conduct, turning on the stop
lamp.
This removes the gate drive from S1-1, Now when +26 is applied to pin L14 by the power
supplv fault contact, SI-1 does not conduct and relay M3-1 is not set. The Master Clear relay
is pickec!, kCf'pir.g the processor in a cleared state as power is removed.
The auto restarting circuit is also located on the automatic reset card. As power is resumed
after an outage, the low voltage contacts are still in the power supply fal;lt pOSition and the
posith'e supply is connecteci to pin L14. This in turn holds the central processor in the
mnstel' cleared sbte until a voltage sufficient for running is obtained. Then the low voltage
contacts trat~sfer to the PS~K state - applying the positive supply to pin H10. This energizes
relay 1\17-1 which provides a shprt time delay. When the contacts of relay M7-1 close, a positivE' step is applied to the capacitor C2-1, provided that the auto restart fault relay M3-1 had
not been set. This step is differentiated to provide base drive for transistor T5-3. T5-3
conducts for a short period of time starting the central processor by grounding pin H16.

1-1

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"This Page Intentlonally Blank"

1-4

BIT CARD 2BC1
2BC2
A.

3BC1
48C1

GENERAL DESCRIPTION

Thp hit ca rd contains the Z, X, and S registers, and adder circuitry for one of 14 bits. In addition the hit card provitles:
l.

Core sense amplifying gate

2.

Peripheral input gate

3.

S -_Z gate

4.

X __ Z gate

5.

-

Z-X gate

6.

Z ---X gate

7.

Z __ X gate

R.

Adder to S gate

9.

Adder to inhibit timing

10.

Output buffer

Figure 3-8 is a block diagram of the card as used.
R.

CIHCUTT OPEHATION

f)u:ll \J AND A is connected as a flip-flop and is used as the S register; in like manner Dual
C is used in the Z register, and Dual NAND 0 is used in the X register.

~A\J[)

The adder circuitry is composed of Dual'NAND's E, F, H, and K.

Hll :md "11 form the carry chain (C-Ol1T).
~A!\I)'s

H5 and K5 form the Sum of Z and X when EOR and AND inputs are logical "one's".

:-";,\\'[)'s H5 and K5 form the AND of Z and X when AND is a "zero" and EOR is a "one".
H5 and K5 form the Exclusive OR of Z and X when AND is a "one".
Diodes 01-2 and DI-3 form decode for Sum equal to a Positive Zero.
S to Z Gate consists of modified NAND Bll which is used as an inverter.
X to Z Gate consists of modified NAND B12 which is used as an inverter •

...Z to X Gate consists of modified NAND J12 and an input from Z register.
2-1

Z to X Gate consists of modified NAND 012 and an Input from the Z regllter.
Z to X Gate consists of modified NAND GS and a complemented input from the Z register.
Adder to S Gate consists of NAND FS; this allows the sum of X and Z to be gated to the S
register.
Adder to Inhibit Timing consists of NAND Fll. Diode 01-6 forms a decode for SUM equal to
Negative Zero.
Output Buffer consists of modified NAND Jll; this is used to buffer X register output data to
peripheral driver cards.
Refer to the circuit In the upper left hand corner of schematic 743A300.
This circuit accommodates inputs from core memory (pins L18 and L17) and from other Inputs on pin L1S.
Transistor T8-1 is usually biased off. When the sense preamp output voltage exceeds 0.5
volt, T8-1 conducts. This provides base drive for T1-1 to set the Z register nip-flop If
strobe is a "one".
This circuit is also used to accommodate input data (pin L1S).
An Input voltage of 4.S volts minimum from anyone of the digital buffer cards causes the Z
register flip-flop to be set by turning on transistor T1-1 If input strobe is a "one".
Lamp Driver: The 3 volts, 15 rna indicators are driven from a saturating tranSistor which
drives the lamp through a high impedance to ltmit Inrush current and Improve bulb Ilfe.

2-2

INPUT LINE

- - - ADDER--S

I

FROM CORE SENSE

CLRS,

PREAM~

STR~BE----l
_lNPUT GATE

s

-I..

X

• Z

CLR

- ----

IN
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-

~

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-

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z

----~

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I

1

TO
DESI GNATOR

-=-~~l-

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LOGIC

z
_L_~ _____ _

INHIBIT
TIMrNG
TO INHIBIT
PUlSERS

X

OUTPUT
AMP

OUTPUT LI NE
Figure 3-8.

2-3

•

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l..".

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~W:.~"'\'()II.'>

"This Page Intentionally Blank"

2-8

CORE PULSER CARD 2CPl - 3CPl
:\.

GENERAL DESCRIPTION

This cnrd is lIsed to provide pulse amplifiers driving the X and Y half-select lines or to drive
the inhihit line's of the core stack. (See Figure 3-9).

Inhibit
Paddle

Adder
2r: p 1
3CPl

Stack
Select

t
Diode

"P:
Timing

Card

Board

VI

Figure 3-9.

n.

C1RCllIT OPERATION

1. The card contnins six pulsers and one stack select amplifier. Four of the gix pulsers
are inhihit pulsers, one is a Read (or Inhihit) pulser, the other a Write (or Inhihit) pulser.

2. The circuit diagram of the core pulser card is shown on schematic 743A3l5. The card
receives inputs from the adder and timer cards. Its outputs nre used to provide pulse amplification to inhihit lines on to the half-select Hnes.
Since this board has six identical pulser circuits, the circuit in the upper left of schematic
743A3l5, will be discussed here.
Signals will he defined as a "1" (positive voltage) or a "0" (zero voltage).
If both the stack select (SEL) and input pulse (pin L3) are Itt a "1" level, transistor Tl-l \\111
conduct and this will hlock transistors T6-l and T2-1.
If now the input goes to ground ("0" level), aud the output transistor (Tl-8) of the stack select
amplifier is conducting, transistor Tl-l will he hlocked for a maximum duration determined
by capacitor C4-1 and resistors R26-l, R34-l, and R26-2. Under normal operating conditions, the actual duration is determined hy the length of the Input or Stack Select pulse.

3-1

If a stack select pulse (SEL) is not present (logical "1") and there 18 an Input pulse (logical
"0"), enough current will be suppUed through resistor R52-1 to keep transistor Tl-l con-

ducting.
Should a stack select pulse saturate (drive into heavy conduction) the output transistor (Tl-8
of the stack select amplifier) sufficient base drive will be provided through rest_tor R34-1 to
keep T1-1 conducting.
When transistor T2-1 is not blocked, it acts as a current source. The current I_ determined
by zener diode Z2-1, resistor R51-1 and the setting of potentiometer Mll-1. The cathode of
diode 04-1 Is connected to a 22 volt zener (Z6-1) to limit any excessive Inductive feedback.
Capacitor C4-1 determines the maximum output pulse under fault oondltions (that ts with no
Input Pulse or Stack Select Pulse).
Capacitor C17-1 controls the rate of rise of the current in the output stage to reduce inductive
overshoot and feedback.
The potentiometers on the card are used to adjust currents through a 300 to 400 mtlUampere
range.
The location of the potentiometer on the card are as shown on the module layout drawing.

3-2

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DESIGNATOR CARD 20Cl
.\.

GENERAL DESCHIPTION

The 2DC 1 card is used to provide the following functions.
A five bit designator register
:\ gating designator decode logic for setting designator
3. A gate for designator to the Z register bits 0-4
4. :\ gate for bits 0-4 of the Z register to the designator
5. .\ dCl'one for non-conditional jumps and designator jump
6. :\ decode for return jump instructions
Des j g-log -.
... Des
D -+ Z
- ig

1.

2.

ZO-4
Adder _

X Req.
Z Req.

Decode
Designator
Des i gnator ~------I Register
logic

-

Jump

Decode
Z --- D

Clr D

---P

1

RJP

----I

Decode -

Figure 3-10.
B.

CIRCl'IT OPERATION
1.

Five Bit DeSignator Register - This consists of NAND circuits A, B, C, D, E and
five indicator driver circuits. The register is cleared to "zeroes" (the lights off)
before gating the deSignator logiC. The Overflow Designator is not cleared except by
master clear or Enter DeSignator instruction. The register is cleared to "ones" (all
lights on) before gating the Z Register~

2.

DeSignator Decode Logic Gate - This consists of NAND circuits F, G, H, J, K, and US.
a) F11 (output of F NAND, pin 11) sets the Even DeSignator when the A~er Output
is Positive and Even.

4-1

b)
c)
d)
e)
f)
g)
h)
i)

F5, G5, Gll set the Even Designator when the Adder Output is Negative and Even.
(In reality Bit 13 and Bit 0 are compared, if they are the same, the number is
even.)
H5 sets the Zero Designator (lL4) when the Adder Output is a negative zero.
Hll Sets the Zero Designator when the Adder Output is Positive Zero. The
Decode Diodes of the NAND are located on the Bit Carda.
J5 Sets the Positive Designator when the Adder Output is Positive.
K11 Sets the Overflow Designator when X and Z are positive and Sum is Negative.
It is inhibited on an EOR Instruction.
J 11 Sets the Overflow DeSignator when X and Z are negative and the Sum is Positive. It is inhibited on an EOR Instruction.
KS Sets the End Around Carry Designator when there is a Carry-Out on Bit Thirteen.
US Sets the End Around Carry DeSignator when a "One" is Shifted Off on a RSH
Instruction.

3.

DeSignator to Z Register Gate
ConSists of NAND L11. M11. Nll, P11, R11
Setting of Z register is accomplished by clamping the Output of the compliment
side of the Flip- Flops.

4.

Z Register to DeSignator Gate
ConSists of NAND LS, MS, N5, P5. R5
Setting of the DeSignators is accomplished by clearing them to "One's" and setting
"Zero's" from the compliment side of the Z Register.

S.

Jump permissive Decode
Consists of NAND S. T, Ull, V. W
a) S11 decodes EJP InstrUction and Even DeSignator
b) Wll decodes ZJP Instruction and Zero DeSignator
c) Tll decodes PJP Instruction and Positive DeSignator
d) Vll decodes OJP Instruction and Overflow Designator
e) W5 decodes CJP Instruction and End Around Carry DeSignator
f) T5 decodes SLJ or CLJ Instruction
g) S5 decodes J MP Instruction
h) U11 decodes RJP Instruction
i) V5 is used as a Logie Inverter

6.

Return Jump Decode
ConSists of NAND Ull.
This also forms part of Jump Permissive Decode

4-2

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Figure 3-11. Application of EI Interrupt Card
The EI accepts up to 16 interrupt inputs. A maximum of four El cards can be used per system.
Either a filtered contact closure from the process or a high-speed transistor-driven signal
from peripheral units and/or other computers can set interrupts. An interrupt core is set
when the input voltage exceeds the threshold level of the interrupt circuit and a synchronizing
probe pulse is present from an external pulser card. This probe pulse is generated each instruction Sequence III and is inhibited during interrupt scan to prevent simultaneous setting
and resetting of interrupt cores. A hit pulse occurs when a core is set and indicates that an
interrupt scan should begin if lockout is not set. During interrupt scan, eight X subrow line
and two X subcolumn lines from the HS half-select cards route interrogate pulses sequentially
to each interrupt core. When an interrogate pulse is passed through a core which has been
set, a response voltage called a sense pulse occurs. The address in the S register when the
sense pulse occurs indicates the core memory location containing the next instruction.

5-1

B.

CIRCUIT OPERATION

1.

Circuit Specification
I

Interrupts are to be set from filtered contact closures to 48 volts 2:10%. The filtered in~rrupt
rate is 20 per second. Interrupts can be set from a transistor-driven circuit powered fr.om the
unregulated (26 volt :t 4 volt) main frame power supply.
Probe pulses occurring once per instruction are typically 4 microseconds in duration. The
maximum rate would be 4 microseconds every 9 microseconds. Probe pulse amplitude variation is 14.5 to 17.2 volts worse case.
Interrogate pulses occur every 1.5 microseconds with a 0.9 microsecond duration. Peak current is 0.4 ampere and is supplied through the half-select matrix.
The hit and sense pulse load on the EI card is 150 ohms. Amplitude should exceed 1.5 volts for
at least 150 nanoseconds.
All circuits should be capable of floating with respect to central processor ground.
2.

Circuit Description
Card Block Diagram (Figure 3-12)

This module contains 16 interrupt input circuits. There are five commons available. making
three groups of four circuits and two groups of two circuits.
The basic interrupt circuit is shown in Figure 3-13.
An input voltage charges the 0.5 microfarad capacitor. The voltage on the low side of the 0.05
microfarad coupling capaCitor follows if the input voltage rise is sufficiently fast. When a
threshold determined by the zener breakdown voltage of the Z10 zener and the base emitter
drop of the TIG transistor is exceeded at a level of 17.6 to 19.4 volts. the transistor turns on
and allows the next probe pulse to be applied across the Shockley diode (S3). The sum of the
probe voltage and the voltage on the input capaCitor appears across the S3 Shockley diode and
should be sufficient to cause the Shockley to fire. The Shockley's firing dumps charge from
the input capaCitor through the core and saturates it in one direction. This firing path for the
Shockley. which is initially through the probe transformer. transfers to the D4 diode. which is
a low impedance to ground.
The response voltage when the core is set is the hit pulse. When the core is interrogated. the
response voltage called the sense pulse is generated.
To guarantee that the core will be set once and only once for each contact closure (or applied
input voltage). the 0.05 microfarad capacitor is charged. It is selected to be one-tenth the
filter capaCitor so that the input will not be reset to a point where the input voltage can once
again produce a voltage excursion sufficient to set the core.
The method chosen for applying the probe pulse only when the input voltage exceeds a threshold
minimizes the possibility of the Shockley's undergoing rate firing at too Iowan input voltage
level. Circuit waveforms are shown in Figure 3-14.

5-2

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5-4

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5-10

EXTERNAL PULSER CARD lEP3/2EPl
A.

GENERAL DESCRIPTION

This card is used to perform a number of operations. namely. Channel. Word, Probe. and Interrogate pulse generation. Two of these operations are performed on each card.
See Figure 3-17 for Block Diagram. The External Pulser receives logic levels and timing pulses
from the main-frame control circuitry cards. Pulse energy is supplied to the:
a)

b)
c)
d)

External Interrupt pulse transformers.
External Interrupt Interrogate matrix.
Word peripheral matrix. and
Channel peripheral matrix.

B.

CIHCllIT OI'EHATION

1.

Circuit Specifications

Logic levels are intended to feed pins H15, H17, and H13. These signals ground to select outputs and hold down 1.4 ma maximum. The "one" signal will be clamped at 2 volts maximum.
The timing Signals are brought in through capacitive coupled inputs H14 and HI6 and also
ground to select the outputs. They must hold down 7.7 ma max. and block 7.15 volts in the "one"
state. The timing Signals are capacitive coupled to guarantee the outputs will not be full "on"
continuously in case the inputs are held at ground. The output signal level is intended to be a
regulated 18 volt pulse with 400 rna of current limit.
2.

Circuit Description

The card block diagram of Figure 3-18 shows the two applications of the External Pulser card.
There are two pulser circuits on each card and there are two external pulser cards in the system. The first card contains the interrogate pulser and four of its eight associated half-select
transformers. The second card contains the remaining four half-select transformers for the
interrogate pulser, the probe pulser, and the channel pulser with all eight of its half-select
transformers.
Each pulser circuit consists of an OR gate and an inverting stage which drives the output transistor.
The schematic of the external pulser is shown on Drawing 74"3A308. The circuit operates in
the following way. When all input diodes have a "1" Signal. transistor TI-1 is saturated providing base drive for transistor T14-1. Transistor T2-1 is, therefore. blocked. When all input
diodes are grounded. transistors T1-1 andTl4-1blockand the output transistor T2-1 conducts.
The base VOltage of T2-1 is clamped, which prevents the transistor from saturating. TranSistor
T2-1 therefore acts as a current source, the current being adjustable by potentiometer MU-l.
The output voltage at the collector is determined by the 18 V zener diode Z13-1 and 04-3 in
series with it. Zener diode Z 12-1 serves to clamp any inductive flyback voltage. The maximum
time duration for which the output transistor can conduct is limited by the time const~tnt of the
capacitive coupled input circuit. Any number of input circuits can be connected to the pulser.
There are two input circuits for the probe and interrogate pulsers. The word and chnnnel
pulsers have three input circuits each.

6-1

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6-3

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3.

Timing

Waveforms in Figure 3-19 show the input to output delay for a 1 microsecond current puis.,
typical of the interrogate pulse used in the interrogate scan. Also shown Is the delay for a
four microsecond voltage pulse as is used in the Word. Channel and Probe puls. appltoatlona.

Output Current Rtae Time
Input Voltage 2V 10m
Output Current 100 mA/om
o·l,.,.s/om

Output Current Fall Time
Input Voltap 2V 10m
Output Current 100 mA/om
0'1 tJ. s/om
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Input Voltage 2V 10m
Output Voltap (between
colleotor aDd poouDd) BV 10m
0.1 ,.,.s/om

Output Voltap Ria. Time
Input Voltage 2V 10m
Output Voltap (between
oolleotor and poouDd) BV 10m
0'1

Figure 3-19.

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HALF SELECT CARD 2HS2
A.

GENERAL DESCRIPTION

This circuit card is required to provide four subrow and four subcolumn half-select switches.
The half-select switches arf' time-shared by the core memory subsystem., the interrupt subsystem and the input-output subsystem. The subrow half-select switches and the subcolumn
half-select switches complete the current paths for the primary and secondary. windings of the
half-select transformers respectively.
The relationship of the half-select switches to the system is shown in the block diagrams (Figures 3-20, 3-21 and 3-22) that follow.
B.

CIRCUIT OPERATION

1.

Circuit Specifications

The input to the half-select switches is obtained by decoding the S-register outputs. The decoding is done by means of modified NAND modules. The output state of the subrow half-select switch has to handle 350 rnA inductive load plus the transformer losses and damping current across the primary winding of the half-select transformers. The subcolumn half-select
switch has to carry a 350 rnA inductive load.
2.

Circuit Description

This card contains 4 sub row and 4 subcolumn half-select switches. One pair of half-select
switches have OR type inputs to allow direct access to core locations assigned to the Accumulator and Program Counter.
a)

Sub row Description- Figure 3-23

Signals will be defined as a "1" (positive voltage) and a "0" (zero voltage).
When all four inputs to the circuit are logical "one" 's the output of the NAND gate is a logical
"zero". Base drive is therefore provided for transistor TS-l through resistor R24-1. Transistor TS-1 saturates, providing base drive for transistor T2-1. Transistor T2-1 conducts
but is prevented from saturating.
When T2-1 is conducting, a current path is provided for the pulser circuit and therefore current flows through the half-select transformer. Switching delays through the subrow half-select switches are minimized by using a nonsaturating switch as the output stage. Diode DS-1
helps to reverse bias transistor TS-l. Diode 04-1 limits the flyback voltage across the transformer thereby protecting tra.!lsistor t2-1 from destruction. Diode D7-2 prevents turn-on of
transistor T2 when the flyback pulse occurs.
b)

Subcolumn Description-Figure 3-24

When all four inputs to the circuit are logical "one" 's the output of the NAND gate is a logical
"zero". Transistor T6-1 is, therefore, blocked, transistors TS-2 and T12-1 are conducting.

7-1

Diodes 04-8.04-9. 04-X. 04-Y. 04-10. 04-11 and transistor T12-1 form an a-c switch. so
that when transistor T12-1 is conducting. current can now through the half-select transformer
in either direction. When point B is negative with respect to point A. conduction takes place
through D4-Y. 04-10. 04-11. T12-1 and 04-9. When point A is negative with respect to B.
conduction takes place through 04-10. Tl2-1. 04-8 and 04-X.
Diode 04-7 is needed for limiting the nyback voltage. Diode 04-5 serves to facilitate fast
turn-off of transistor T12-1. Diode 04-6 provides a path for discharging Une capacitance.
The capacitor C3-1 is neec:ted to delay the turn-off of the subcolumn output transistor until the
primary current through the half-select transformer decreases. This is necessary to prevent
magnetizing current buildup.
3.

Timing

The half-select switches are selected for a duration of 4.2 microseconds; and are unselected
for 0.3 microseconds.

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PRODAC Half-Select Scheme, Typical Partial View for Least-Significant
Half-Address of One Stack

7-3

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Figure 3-21. PRODAC Half-Select Scheme, Least Significant Half-Address, "X-Axis"

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7-4

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8-6

INTERRUPT FILTER MODULE 41Fl/41F2
A.

GENERAL DESCRIPTION

This module contains eight filters
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B.

CIRCUIT DESCRIPTION

The card contains 14 inhibit input circuits, two logic gates and zener diode power supply. The
inhibit input circuit (Figure 3-29) consists of a damp-resistor across the inhibit winding and a
diode in series with the inhibit winding. The primary purpose of this diode is to offer protection to the inhibit winding under accidental over-current conditions. Should the current

11-1

become exces.ive, the diode should fail before the winding. In addition to this safety feature
the diodes also insure that current will not circulate through the Inhibit winding in the opposite
direction.
+26v~------~~~------~

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Winding

To Pulser

Figure 3-29. Inhibit Input Circuit
The logic elements on this board are two NAND gates in a dual NAND package. One NAND
gate Is used to decode the last two bits of the S-register together with the memory enable Signal. The output of this NAND gate provides the "stack select" signal for the pulser card. The
additional NAND gate is provided to enable additional logic operations where more than one
stack Is used.

11-2

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12-6

LOW VOLTAGE SENSOR
A.

3LV2

GENERAL DESCRIPTION

The Low Voltage Sensor card contains three separate circuits which perform the following
functions:
1.

The Low Voltage Detection circuit detects excursions of the +26 voltage bus below
safe operating levels and provides a signal to the Central Processor if this happens.

2.

The Synchronizer Interrupt circuit acts as a real time clock for program timekeeping purposes.

3.

The Dead Computer Switch circuit monitors operation of certain hardware and software functions, and provides contacts available for alarm and control purposes in
the event of certain classes of computer malfunction.

B.

CIRCUIT OPEHATION

1.

Circuit Description - Low Voltage Circuit

Drawing 743A340 shows the low voltage detection circuit in the upper center. Input to the
circuit is the +26VDC to PSC (Le., unregulated + 26V bus voltage) appearing between x30 and
x1S-x20. M12-1 is adjusted to turn TS-1 on when the bus voltage drops to 23.6V. TS-1 then
turns on T5-2 which grounds the base of T5-3 turning T5-3 OFF. The collector of T5-3 is
raised to bus voltage by R53-1, and an external interrupt, PF AL INT, is generated. Also,
T5-4 is now turned ON thus grounding the base of T5-3 and holding it OFF. Approximately 6
milliseconds later, relay M7-1 which has been held energized by capacitor C26-1 drops out,
and the NC contacts are closed as indicated.
M19-1 is used to precisely set time delay from start of power supply failure interrupt until
closing of power supply fault relay contact. This time delay is set between 7.2 and S.O ms and
compensates for variations in parameters such as relay M7-1 dropout time and current, capacitor C26-1 value, and resistor R52-3 value.
When the relay armature transfers to the NC side, base drive is removed from T5-4 and this
transistor turns OFF. This removes the ground from the base of T5-3 and enables the circuit
to respond to a +26 voltage bus level above +22.9 volts. R30-1 is a feedback resistor which
provides approximately 1.2 volts of hysteresis. Thus TS-l turns OFF when the +26 voltage
bus reaches about 24VDC.
2.

Circuit Description - Synchronizer Interrupt

The Synchronizer Interrupt circuit is also located on the Low Voltage Sensor card diagram
upper left hand corner. T5-1 is turned ON and OFF 60 times each second by the 6.3VAC
60CPS voltage applied to the transistor's base through R23-1 and D7-1. Since the collector of
T5-1 is returned to +26V through R52-2, the collector is alternately at near PSC potential and
then + 26VDC generating an external interrupt (labeled SYNC INT) used by computer programs
for internal timekeeping functions.

13-1

R23-1 limits current into the base of T5-1, and diode 07-1 prevents the base-emltter Junction
from being stressed by a high reverse voltage during negative alternations of the input voltap.
Under certain condltions, it is desirable to have a synchronizer interrupt rate of 120 pulses
per second. To achieve this, the 60CPS voltage is rectified in a bridge circuit amd the pulse
D.C. output is appUed to the base of T5-1 for a 120 PPS interrupt rate.
3.

Circuit Description - Dead Computer Switch

The third functional circuit located on the Low Voltage Sensor card is the Dead Computer
Switch. This circuit's output depends on the state of the two relays, M7-2 and M7-3. The relays are single side stable and arranged such that if either relay is in the de-energized state,
continuity exists between the POWER connection and the ALARM connection. When both relays are energized, the POWER connection is coupled to the CONTROL output. Power input is
furnished by an external source and ALARM and CONTROL functions are determined by the
computer user. (Relay contact ratings are identical to CC~ ratings, namely 500 volts maximum, 2 amperes maximum or 100VA maximum. However, large inductive loads must be
shunted by suppression diodes.)
+48VDC is appUed to the relays alternately by a contact output. Each relay has an external
capacitor in parallel with it. This capacitor charges up and holds the relay energized while
the CC~ is applying power to the other relay-capacitor combination. If for some reason the
Dead Computer Switch CC~ does not return to the other side at the end of the switching internal, the relay will "time out" and close the ALARM circuit.
M14-1 and M14-2 are voltage dividers used to adjust the charge-discharge cycle of the capaCitors. This determines what the period of the CC~ switching cycle must be. (Maximum
period is 2 seconds or 1 second between contact transfers, and minimum period is 1 second
or 0.5 second between contact transfers.) Diode 08-1 is an isolating diode that makes it possible to take an externaltnterrupt from the anode of 08-1 if desired. C7-1 and R12-1, and
C7-2 and R12-2 are filters across the relay contacts. These are for contact protection, although as noted above these filters are not adequate protection against large inductive loads.
Relay M7 is a single side stable relay with a coil resistance of 675 ohms. "Must operate"
voltage is 8.6VDC.

13-2

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These two bO:1rds :1re required to contain the blocking diodes and the trnnsformers for the
hnlf-select mntrix.
The relationshin of the diode honrds to the system is shown in Figure 3-31.

n.

CmCnT ()PEHATInr-.;

1.

Circuit Specifications

The primar~' windings of the half-select transformers are driven hy the rulsers and the suhrow half-select switches. The seconrlary windings together with the suhcolumn half-select
switches pro\-idc :1 current path through the core windings. A damping resistor is placed
:IC1'OS5 the sccondnry of the transformer to prevent excessive inductive flyback. The suhcolumn diode matrix is connected directly to the core stack in the manner shown on the drawing. The primary consideration in the grouping of the core windings is the geometry of the
printed circuit layout.
2.

Circuit Description

The ('nrd hlock dingr[lm is shown in Figure 3-32. Each half-select transformer drives 8 core
half-select lines. The subcolumn diodes are connected in groups of eight on each diode board
and then connectC'd to the eight suhcolumn half-select switches.
3.

Diode Identification

Figures 3-33 and 3-34 show the layout of the MA and MB boards which identify the diodes
with respect to the X matrix or Y matrix. For example. looking at the MA schematic,
the diodes marked X36 are tied to @03C/JW and 0~3C/JR. On Figure 3-33, these can be
physically located at the upper right hand side of the drawing (and the board itself) by
noting the number (36) shown between two lines (these indicate the diodes), and whether
it is the read or write diode by the R or W identification.
The figure is hroken down into an X matrix or Y matrix by the solid line extending (in stair('[lse f[lshion) across the board.

14-1

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14-10

MEMORY ENABLE BOARD
A.

2ME2

GENERAL DESCRIPTION

The ME bo3.rd performs or provides several important functions: memory enahle decode :md
drive, select accumulator decode and drive, select program counter decode and drive, select
S register decode and drive, inversion of returniump instruction decode, interrogate pulser
timin~ and core strobe gate drive. (Figure 3-35).

Time
emory Enable

SEQ

INST

Select Accumulator Enable

Select Program Counter Enable

Select S Register Enable

Return Jump Decode Inversion

In terrogate Pulser Timing

Co re Memory Strobe Gate Driver

Figure 3-35. Memory Enable Board

15-1

B.

CIRCUIT DESCRIPTION

Memorl Enable Decode Drive: Consists of NAND B-11, E5 and Ell. B-11 disables memory
during equence VI of an output instruction. E5 disables memory during an external interrupt
8can. Ell disables memory during Sequence V of an input instruction.
Select Accumulator Decode Drive: (SEL A) Consists of NAND J and L5. Jll selects accumulator during Sequence V of OUT and ST L instructions. J5 selects accumulator during Sequence
VI of ADD, AND, INP. SUB. EOR. and ENL Instructions. L5 is a logic inverter.
Select Program Counter Decode Drive: (SEL P) Consists of NAND A. D. and C5. All selects
P (program counter) during Sequence Vof an RJP instruction. A5 selects P during Sequence
VII. 011 selects P during Sequence II. 05 is a logic inverter. C5 Inhibits the selecting of P
during an interrupt scan.
Select S Register Decode Drive: (SEL S) Consists of NAND Cll. F. Hand K5. Cll and F5
select S during Sequence V of all instructions except OUT. R.TP. and STL. F11 selects S during Sequence VI ofLSH, RSH, OUT. R.TP, and STL instructions. H11 selects S during Sequence
III. K5 selects S during an external interrupt scan. H5 Is a power logic inverter.
Return Jump InverSion: B5 is a logic inverter.
Interrogate Pulser Timing: Consists of NAND K5. This NAND (K5) also is used to time the
external interrupt interrogate pulser.
Core Strobe Gate Driver: Consists of NAND G, Kll and Lll. Gll inhibits strobe during Sequence VI of INP, STL, OlIT, RJP, and STL instructions. K11inhibits strobe during Sequence
VI of SDR, LSH. RJP, and STL instructions. Lll is a decoding delay line tap amplifier which
inhibits strobe when memory is disabled. G5 has extra base drive in order to drive many addltlonal outputs.

15-2

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A.

2PDl

GENERAL DESCRIPTION

The circuits on this card provide isolation between the subcolumn half-select switches and
the peripheral equipment. In the ahsence of the peripheral drivers, cahle capacitances would
present low impedance paths to the currents in the high speed half-select systems and would
cause excessive ringing. Since both the current amplitude and current rise time are critical
in the central processor half-select applications, it is desirable to isolate the peripheral
cables from the half-select switches. In I/O applications neither the amplitudes nor the rise
times of the volt:lge waveforms are critical.
The relationship of the Peripheral Drivers to the rest of the system is shown in Figure 3-36.
The inputs to the Peripheral Drivers are the output lines of the subcolumn half-select lines.
The SEL pulse from the timing card and the Word and Channel Pulser timing pulse together
enable the peripheral driver circuits. The Peripheral Drivers and the Suhrow half-select
switches form the input-output half-select matrix.

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Figure 3-36.

16-1

B.

CIRCUIT OPERATION

1.

Circuit SpeclftcaUon

The inputs to the Peripheral Drivers are obtained at the common collector output stage of the
subcolumn half-select switches. The SEL and WD " CHN pulser timing inputs are logic levels.

NPN
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Figure 3-37.
16-2

16 PERI PHERAL
COLUMN HALF
SELECT LINES

2.

Circuit Description

The Card block diagram is shown in Figure 3-37. Corresponding to the 16 subcolumn half-select
switches there are 16 Peripheral Driver circuits on the card. Each circuit consists of an output transistor (PNP) that is driven by an NPN stage. The Peripheral Driver circuits are
gated by means of a gating transistor that provides th~itter currents for the NPN stages.
This gating transistor is driven by the logical sum of SEL and the External Pulser timing
pulse - \YO & CH.
+26 V

INPUT
R58

OUTPUT

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04-1

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SEL

ON

Z2 6.B V

A

R25 3.01 K

WO &CHAN.
(PUlSER TIMING)

ON

Cl 0.0005 MFD

A

.......

~-

Figure 3-38. Circuit Diagram
The peripheral driver circuit (shown in Figure 3-38) operates in the following manner: When the
SE Land pulser timing pulses are both zeros, transistor T6 is conducting, so that if there is

an input, transistor T12 conducts, saturating transistor T13. Zener diode Z2 limits the base
\·oltage of transistor T6 to ensure operation as a current source initially. Capacitor C1 limits
the rate of rise of the emitter current for transistor T6. This is necessary for limiting the
rate at which transistor T13 turns on by limiting the rate of rise of its base current. The
reason for limiting the turn-on speed of transistor T13 is to avoid loosing signal through cahle
capaci tance.
Diodes 04-13 and 04-18 help to keep transistor T12 blocked when the subcolumn half-select
switch feeding the circuit is not conducting. With the subcolumn half-select switch blocked,
the input is two diode drops and one collector saturation drop above ground.
16-3

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16-6

PULL-UP RESISTOR CARD
:~.

GENERAL

lPUl

nESCRIPTIO~

Resistors are prtwided for use as additional collector loads for NAND's or modified NAND's
where it is desi red to impro\'e speed or noise immunity.
B.

CIRCnT OESCRIPTIOr--;

This card contains 34 resistors haYing a 3.01K value, connected to 6.8-volt supplies on the
card. Each resistor adds an equivalent loading of one NAND input to the collector to which it
is tied.

17-1

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17-4

SENSE AMPLIFIER CARD lSA2
2SAl
A.

lSA3
2SA2

GENERAL DESCRIPTION

The circuits on this card are required to provide amplification for the outputs of the core
memory sense lines. The amplifiers must have good common mode rejection at high freCjL!encies. ~ote: There are two sense amplifier card configurations, one for core stacks 0
and 3, the other for 1 and 4. Essentially these are to accommodate left and right hand wiring
to the core stacks. Circuits are identical. (Figure 3-39).

Core
Stack

---

Sense
Amp1 ifiers

......

Z

Register

Figure 3-39.
The Sense Amplifier is electrically situated between the sense windings of the core-stack and
the input of the Z register. The amplitudes of the sense outputs are too small to set the flipflops of the Z register. The sense amplifiers provide the necessary amplification.
R.

CIRCtTIT OPEnATION

1.

Circuit SpeCifications

The sense windings of the core stack are shunted by a 100 ohm damping resistor and connected
directly to the input of the sense amplifier. The output of the sense amplifier is transformer
coupled to a level discriminator on the bit card. The transformer passes the amplified normal
mode signal while rejecting the common mode signa1.
2.

Circuit Description

The sense amplifier card contains 14 amplifier circuits as well as transformer outputs and
rectifying circuits, as shown in the card block diagram, Figure 3-40.
Refer to Figure 3-41 and drawing 743A3I4. The sense amplifier is a two stage, a-c, balanced
amplifier. The first stage, consisting of transistors T14-I and T14-2, provides all the voltage gain of the amplifier. The second stage, consisting of transistors T15-1 and T15-2 acts
as a buffer amplifier with unity voltage gain. The output is obtained between the emitters of
transistors T15-1 and T15-2. The blocking capacitors CU-1 and CU-15 isolate the d-c emitter currents of T14-1 and T14-2 and T15-1 and T15-2 respectively. This ensures that under
quiescent conditions none of the transistors will be blocked, thereby eliminating the need for
matching the transistor pairs for base-emitter voltage drop.

18-1

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W15

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Bit II

Bit 12

Bit 13

Figure 3-40.

18-2

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Power
Supply

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24 V

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R26-2
4.32 K

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4.32 K

10 V

R21-2

24 V

+10 V

R21-1

1 K

1 K

T14-1

R7G-2
62

Cll-l
R27-2

R27-1

4.99 K

4.99 K

R14-1
100il.

W1

W2

Figure 3-41.

18-3

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18-6

SE~UENCE

A.

CONTROL CARD

15(2

GENERAL DESCRIPTION

This card provides a three-bit sequence advance register, a three-bit sequence half-advance
register, a sequence half -advance to sequence advance gate, a decoding gate to set hnlfadvance register, a decode of Sequence V, and clamping for manual read core and manual
write core.
Figure 3-42 shows in block diagram form the uses of this card.
B.

CIRCliIT DESCRIPTION

Block diagram Figure 3-42 is helpful in connection with study of the following block description
and also drawing 743A302.
The SequencE' Acivance Register: Consists of NAND's 0, E and F. These have double-base
drh'e for high fanout.
The Sequence Half-Advance Register: Consists of NAND's A, Band C. These also have
double-base drive for high fanout.
Sequence Half-Advance to Sequence Register Gate: Consists of NAND's J t K and L. It transfers both sides of the register, thus avoiding clearing before transfer.
Sequence Half-Advance Decoding Gate: Consists of NAND's Gt H, Nt P and R. (See the sequence flowchart located at the bottom of schematic for sequence rotation.)
Rll sets SequencE' III from Sequence II. H5 sets Sequence IV from Sequence IlIon a non-jllmp
instruction. Hll sets Sequence IV from Sequence III when a jump is to be taken. Pll sets Sequence V from Sequence III. Nll sets Sequence VII from Sequence III. P5 sets Sequence V
from Sequence IV. G5 sets Sequence VII from Sequence IV. GIl sets Sequence VI from Sequence V. N5 sets Sequence VII from Sequence VI. R5 decodes a non-jump instruction.
Decode Sequence V: Consists of NAND M. MIl decodes Sequence V. M5 inverts Sequence V.
Manual Read Core Decode: Consists of R25-14 and 07-2 to 07-6. Switch grounding clamps
Sequence V of the ENL (Enter Lower) instruction.
Manual Write Core Decode: Consists of R25-13 and 07-1 and 07-7. Switch grounding clamps
Sequence VI of the ST L (Store Lower) instruction.

19-1

~

Set HA
Decode
& Gate

...

-

HA
FF
(3 Bits)

SA

Gate

t--_ _ _

[
SEQ 17

---~I

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Set

-

SA

FF
(3 Bits)

Clamps Outputs For
Manual Read Core

Outputs For
Manual Write Core

~-----Clamps

Decode

t-1---1l

Figure 3-42.

19-2

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A.

GE!\EHAL

DESCRIPTIO~

This card is used to provide:
1.

2.
3.
4.
5.
6.

7.

Adder to S gate drive
Clear S to "one" gate drive
Clear X to "zero" gate drive
Input data strobe gate drive
Input and output decode for Word and Channel pulsers
Instruction step decode
Inhibit pulser timing signal

Figure 3-43 shows in block diagram form the uses of this card.
B.

CIRCUIT DESCRIPTION

ADD -80-7 consists of NANOs E5 and All. E5 is used as a decoding delay line tap amplifier,
All is used as an inverter.
ADD- S8-1~ consists of NANOs Ell and A5. Ell is used as a decoding delay line tap amplifier, A5 is used as an inverter.

CLR S/0-7,1

consists of NAND G5 which is used as a decoding delay line tap amplifier.

CLIl S/S-13.1

consists of NAND Gll which is used as a decoding delay line tap amplifier.

CLR

X, consists of NAND F5 and diode 01-4. F5 is used as a double drive decoding delay lint>
tap amplifier, 01-4 is used to clamp the output of CLR X bus for master clearing the X rcgistel".
Of special note here, observe that the VI logic signal on pin 3 is not diode isolated.

Input Strobe - consists of NAND Fll and 05. Fll is used as a decoding delay line tap amplifiel',
05 is used as a double base drive inverter. R21-1 is used as pull-up which helps to improve the
rise time of the strobe pulse.
WO and Ch. Pulser Timing - consists of NAN Os 011 and Bll. 011 is used to decode the Input
instruction and sequence V. Bll decodes the Output instruction and sequence VI.
Inst Step - consists of NAN 0 B5 which decodes the cleared, Half Advance at the end of a sequence which indicates the next sequence will be I or II.
Inhibit Pulser Timing - consists of NAND C5 and Cll. C5 is used as a decoding delay line tap
amplifier except two taps, L2 and L3 are decoded. It provides a zero output over the dUration
of two delay line tap periods. Cll is used as a double drive decoding gate driver. ell output
signal is similar to the W signal except that it occurs one delay line tap earlier.

20-1

SEQ

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TIMING

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TI MI NG

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INPUT INS:

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R

0-7)

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(BITS

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CLR

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.

=1'-------J)>--~L.

(BITS

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ADD-S

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(BITS

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CLR X

I NPUT STROBE

--1
I----WORD & CHANNEL PULSER TIMING

OUTPUT INST & SEQ]1---i

-------'

LAST SEQ OF INSTRUCTION-j
TIMI NG

-ia..___

I NST STEP

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Figure 3-43.

20-2

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TIMING CARD 4TC1

A.

GENERAL DESCRIPTION

The timing card generates the clock pulses. It provides a delay line timing chain, a two bit
register, core read timing, core write timing, the half-select selection timing, a clear Z gate
drive, clear and set sequence half-advance gate time, a stop relay, and a master clear relay.
Figure 3-44 is a block diagram of the use of this card in the system.
B.

CIRCUIT OPERA TION

1.

Circuit Specifications

The delay line has a total delay of 1. 5 microseconds, three passes are made through the delay
line to achieve the basic 4.5 microsecond cycle time.
2.

Circuit Description

The delay line is started by a "zero" signal at pin 1 of NAND P flip-flop. This flip-flop is used
to prevent contact bounce from the start (external to the board) button from restarting the delay
line.
Capacitor C3-1 and resistor R2l-7 differentiate the output of P5 to set dual NAND flip-flop N.
This provides base drive to transistor T7-l which drives the delay line directly.
The delay line will sustain itself via dual NAND Gl2 which acts as a hold off clamp to insure
that no multiple pulses occur down the line.
NAND M5 provides restart from the last tap of the delay line.
The delay line may be stopped with a "zero" on the STP input on pin 2 of dual NAND M.
This STP occurs as a result of a STOP instruction or by depressing the stop (externally
mounted) button.
Transistor T7-l is used as a emitter follower circuit to provide a twelve volt, 300 nanosecond
pulse. The pulse width is determined by the first tap of the delay line which generates a level
to turn off T7-1. Tap vOltages greater than five volts cause switching of the tap amplifiers.
The timing register consists of NAND flip-flops Band C and NAND gates Hand J. This register is used to count the cycles and will be TO·Tl; TO·Tl; and TO·Tl.
The core read pulser timing consists of NAND flip-flop D and NAND gates K. The Read pulse
(R) is set by TO and L 1 and stays set tmtil the following L 1 time when TO clears the pulse.
The core write pulser timing consists of NAND flip-flop E and gates NAND L. The Write
pulse (W) is set by TO·Tl and L3 pulse and stays set until the next L3 time when Tl clears the
pulse.

21-1

Half-Select selection timing consists of NAND F and is set by the first LO pulse and stays set
until the third L3 time when Tl clears W and Sel at the same time.
Clear Z gate driver consists of NAND Mll. Mll is used as a decoding delay line tap amplifier!
R21-5. R21-6. C6-3 and 01-16 provide a pulse to clear Z when Master Clear (external to the
board) is depressed.
Clear sequence half advance gate driver consists of modified NAND Gll which is used as a decoding delay line tap amplifier.
Set sequence half advance gate driver consists of NAND A5 which is used as a logic signal inverter.
Set sequence advance gate driver consists of NAND All which is used as a logic signal inverter.
The Stop circuit consists of relay 1\11-2 and aSSOCiated components; with this relay closed. the
computer will transfer from" run" to "instruction step".
The Master Clear circuit consists of relay Ml-1 and associated components; with this relay
closed. the computer will stop then master clear the register to preset condition. that is. it
will clamp Self reset flip-flop P; clamp Clr HA. clamp W. clamp R. set Tl. set TO and clear Z.

21-2

TO
START-E
FF

B~~~~N

-----

---

PULSE
FORMER 1----

,---

--"

-

PULSER

FF

BOUNCE- PROOF
SWIT CH

FROM STOP CKTS--

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TIMING
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TIMING

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TIMING

WR I TE
PUL SER
TIM INC

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CLR Z

)

CLR HA

TIMING

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SET HA

TIMING

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SET SA

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TII11NG

TO MA STER
CLEAR P .B.

TO STOP P.B.

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Figure 3 -44.

21-3

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21-6

Z TO X TRANSFER CARD lZX3
.\.

GE1\EH.\L DESCHJPTI()\

This card provides these gate drives:

Z--x

z-·x

z--x
7.--f

Z - --lJ
I)--Z

The 1ZX3 card also provides gate drives for designator logic to designator gate, clear designator to "Zero" gate, clear deSignator to "One" gate; and Sequence VI decode.
Figure 3-45 shows the area of the computer which this card provides.
B.

CIHCLIT

l)ESCRIJlTIO~

The ~lccompanyillg block diagram is helpful in study of the following description of the blocks
composing this ca rd.
Z ---X Gate Drive.: Consists of I\AND B, C. R59-1, 01-3. C5 enables Z---X gate drive in
Sequence Y. 1311 inhibits Z - - X gate drive in Sequence V during a SU B or OCR instruction.
C 11 inhibits Z- - • X gate drive in Sequence \' during a RSH instruction. B5 is used in a gate
driYe circuit.

7: - - X Gate Drive: Consists of 1\.\1\0 Kll. Lll. G5, R59-2, 01-2. Kll enables Z - - X
gate drive in Sequence \. of OCR instruction. Lll enables Z - - X gate drive in Sequence V
of StIR instruction. G5 is used in a gate drive circuit.
; - - X G~'lt~ Drive: Consists of NAt\D F, R59-3 and 01-1. Fll enables
in Sequence \ of RSH instruction. F5 is used in a gate drive circuit.

Z- X

gate drive

Z - F Gate Drive: Consists of NAND K5 and L5. K5 enables Z - F gate drive in Sequence
III.

L5 is a logic inverter.

Z0 Gate Drive: Consists of l\AND A. All enables Z - - 0 gate in Sequence V of an EDR
instruction. A5 is a logiC inverter.
0 - - Z Gate Drive: Consists of NAND J. J 11 enables D - Z gate drive in Sequence V of
an SDR instruction. J5 is a logic inverter.
DeSignator Logic to DeSignator Gate Drive: Consists of NAND D. E5. E5 enables the deSignator iogic to desIgnator -gate-In Sequenc-e Vi of an instruction which terminates in Sequence
n. 05 is a logic inverter.

22-1

Clear D to "Zero" Gate: Consists of NAND 811. 811 clears designator to "Zero" prior to
desilllator logic gatlDl. Muter Clear a180 clamps this gate drive.
Clear D to "One" Gate: Consists of NAND Ell. Ell clears designator to "One" prior to
Z Register to designators in EDR instruction.

gatl~

Sequence VI Decode: ConsiSts of NAND GU.
All Instructions
Except SUB, OCR,
RSH
Seq 'll

Now Jump

Timing
OCR Or

SUB Inst

Seq II

j

Z ~x

Now Jump

Insts~

'--_~_

Timing

RSH Inst
Seq Y
Timing

>>-

~~~~ --J
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Seq 1f
TImIng

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. Tlmi ng

KOR Inst3

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Tlml ng

Z --"F

EOR Inst

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Seq Y Timing

>-

Seq
Z

~O

'-_..J

Figure 3-45.

22-2

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3AC4 - ANALOG CONTROL MODULE
• The power supply switch output to the word and
channel drivers is normally held to PSC. When the
power supply switch triggers this signal goes to + 26V
(diode coupled) for 1. 8 ms.

GENERAL DESCRIPTION
This module is used in the Analog Input subsystem to
provide proper gating of the output(s) of the voltage-tofrequencv converter(s) into the counter(s) (CT module).
In addition, the :lAC-1 module contains a power supply
switch, usedto reset the word and channel driver SCR' s,
and an input b\' which the Analog Trap (AT module) can
open the s\lpph switch. The connection of the :lAC4
module to the .\nalog Input subsystem is shown in Figure 1.

--,

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3AC4

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A/llALDG
TRAP
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ItIOClJLES

Before discussing the overall operation of the Analog
Control circuit, the operation of the following special
circuits is described.

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CIRCUIT DESCRIPTION

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Power con-

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COUNT# ,

READ TRIG.

Connection to + 26V and PSC is required.
sumption is approximately 350 rnA.

I

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R£SET#3

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Power Requirements

--.

RESET #2

120 PPS

r-----'

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RESET # I

• The interrupt signal goes from positive (+ 26V)
to near zero to positive and is approximately 1. 8 rns
in duration.

L

PRDC INT
110

NOTE

~

The following description is for a 60 Hz
power line frequency environment. For 50
Hz power line frequency the circuit operation is identical to 60 rlz operation, except
the timing pulses are at 100 PPS instead of
120 PPS.

I
I

.J

FIGURE 1. APPLICA TION BLOCK DIAGRAM

CIRCUIT SPECIFICATIONS
Input Requirements

Inte~rated

• The 1~0 PPS input requires a 15V, pk-pk, 50'}b
duty cycle. square wave input which is in phase lock
with the 60 liz power line frequency, For 50 Hz power
line frequency, the input requirement is 100 PPS instead of 120 PPS. The read trigger input requires
-1 J.l.S zero going pulse.

Circuit Dual NAND - W2

Fefer to Figure :2 for schematic and symbol diagrams.

0

12

I

5

2

• The VIF (voltage-to-frequency converter) signal requires a logic level positive pulses with a maximum pulse rate of 1 MHz. The power supply switch
O\'erride input requires a zero voltage level.

SYMBOL

Uiiipui Capabiiiiies
FIGURE 2. IC SCHEMA TIC AHD SYMBOL

• Provides logic level "zero" pulse to reset the
counters.
• The count signals to the counters are logic level
pulses, the frequency and shape is the same as the output of the VIF converter.

The output transistor can conduct ("zero" state) only if
all inputs are high ("one" state) to permit base drive to
the output transistor. This is illustrated by the following truth table.

1-1

r----------- ---------l
110

Pin No.
INPUTS

I

12 or 6

lor 7
0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1

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1
1
1
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FIGURE ... HO. J DELI.Y CIRCUIT DII.GRI.M

l20 PPS Tlmlne pull"

The function of this stage Is to provide a minimum time

Refer to the circuit diagram shown in Figure 3.

dela" between the READ TRlGGER pulse and the first
120 PPS timing pulse used to start the integration perioJ.
;.,'1r:1QL:" the output of nip ·fhlp '1/::-.'\5 Is a "zero".
Translator 1'1-] is blocklr.~ since the cathode of zener
(!io.iC Z1-1 is near ground, Diode Dl-13 Is a base
drive ~lamp for transistor Tl-1. It permits Tl-l to
c()n;!cI~t only at :l 120 PPS timing pulse. provided there
Is base drive through Z7-1,

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I

I

~o PPS

I

IWING

0

r1'--~rl~

----------.1

I

Ol,l'?U; I

FIGURE J.

120 PPS TiMING CIRCU/;

T'-'

0

EARLIEST

~].~{.<04

1'ransiswr 1'5-3 is nonnally ('onAND W2- BS. The capacitor C5-1 causes this circuit to differentiate thE' 120
Hz square wave from the Phase Lock oscillator (PL)
module entering Pin Hl6. The result of differentiation
1s an approximately 60 "'S wide. logical "one" pulse at
the output of T5-3 and the complementary pulse at the
output of W2-BS. This 120 PPS pulse train Is used to
sequence the Analog Control module.

0.11, Clrcllit Mum •• r On.

I r-

i

~J

!-"

TYPI~'- :
I

I
I

N:S£T
Of
1V2-& I
"1N 7
0

---------------4L

FIGURE S. NO. I DELAY CIRCU!T TlM/HG

"'&

The 4
READ TJUGGER pulse starts the time delay by
setting fllp-flvr-- W2-AS to a "one". This removes the
clamp on capacitor C26-1 which then charges toward
the 15V zener supply (Z4-1 and R56-1) through D1-12.
R24-1, aDd M12-1. PotentIometer M12-1 is used to
adjust the time delay.
CAUTION

Refer to Figure 4 for the circuit diagram and Fiaure 5
for the circuit timing.

Do not readjust this time delay.

1-2

during the delay period. This changes to a "one" at the
trailing edge of the timing pulse which enables the ring
counter stages. At the next 120 PPS timing pulse transistor TI-2 conducts. thus shifting the "one" to the next
stage. Flip-flop W2-C is reset by a "zero" from the
next stage at the trailing edge of the timing pulse.

This adjustment is made at the factory and should be
readjusted only at the factory due to the difficulties of
setup. When the voltage on C26-1 reaches the threshold
voltage zener Z7 -1 conducts and makes base drive
available to transistor Tl-l. However, transistor
Tl-l continues to block until a 120 PPS timing pulse
(a "one" pulse) removes the base drive clamp through
diode Dl-13. Thus. transistor Tl-l conducts for the
duration of the timing pulse.

Ill--

READ
TRIGGER
W2-CI 0

The delay circuit is reset by a "zero" pulse from the
next stage at reset Pin 7 of flip-flop W2-A. Resistor
R21-2 is a current limiting resistor for C26-1; it discharges through the output transistor of W2-AS.

11
fL
0--- . . .-----------,

120PPS I
TIMING.

•

I

I
I
I

Slnlll Stili of Rln, Countlr
Refer to Figure 6 for the circuit diagram and Figure 7
for the circuit timing.

FLI P-FLOP I
W2-CII

0---

J

I

I
I
I
I

I

I

L
I

I
I
120 PPS
TllollNG PULSE

------------,I

I
I
I
I

+HV

I
I

I
I

OUTPUT I
TI-2
0

------------------------------~LJI
I
I

OUTM'

I

I

I
I

I

I

I

~-~
I
___________ .JI

RESET
W2-C2

'------------------------------~L'
0

IiII\I£RTEO OUTPUT
OF DELAY CIRCUIT

FLIP-FLOP

FIGURE 7. RING COUNTER SINGLE STAGE TIMING

FIGURE 6. RING COUNTER SINGLE STAGE SCHEMATIC

Delay Circuit Number Two

The function of the ring counter single stage is to time
~ cvcle of the power line frequcncy (or one period of
the l~O PPS timing pulses) bv shifting in a "one" at one
liming pulse and shiftin~ the "one" out at the next timing pulse_

Refer to Figure b for the ci rcuit diagram and Figure 9
for the circuit timing.

15 VOLT

ZENER

SUPPLY

W2-C is the memory flip-flop for the timing pulse.
Transistor TI-2 and its diodes form a ;";AND gate
which prevents the output of the flip-flop (Pin 11 of
W2-C) from setting the next stage when W2-C flip-flop
is initially set. Circuit operation is as follows:

-t--------------~

READ

TRIGGER

INPUT

Flip-flop W2-C is preset to "zero" (Pin 11) at the be..;inning of a conversion by the READ TRIGGER pulse.
It is set to a "one" bva "zero" at the input (Pin 7) from
the previous stage. This input 'A'ill occur at a timing
pulse and the flip-flop W2-C will change state on the
leading edge of the timing pulse. Diode DI-17 is connected to the input. When the input is a "zero" this
blocks Tl-2. Diode Dl-l!) is connected to the inverted
output of the delay circuit flip-flop. which is a "zero"

OUTPUT - - - - - - - -.....

I
I

C24-1

i ",J=,
I
t t..3:

L _______ .£.~Y~~'!2....J

FIGURE 8. NO.2 DELAY CIRCUIT DIAGRAM

1-3

The function of this circuit is to generate, upon pulle
command, an output for a fixed time delay.

READ
ILJ--TRIGGER

W2-GI

INPUT

0

I

I

------,

~

W2·G7 0

,

Tra~lltor TI-4 is blockiDi. Upon a "zero" pulse input (Pin 7) W2-Gll changel ltate to an output of "one".
This removel the clamp on capacitor C24-1 and permits
it to charge toward the 15V zener supply through DI-32,
R21-8, and M73-1. Potentiometer M73-1is used to
adjust the time delay. (ThiS adjustment is made at the
factory.) When the voltage on C24-1 reaches the zener
Z2-2 plus the Tl-4 base-emitter voltage, zener Z2-2
conducts and transistor TI-4 is turned on. This action
resets nip-flop W2-Gll to a "zero". Reliltor R21-3
current limits the discharge of C24-1 through the output transistor of W2-G11.

I
I

Pow.r Slipply Switch" Anlll, Compl.tlln Int.rrllpt
Refer to Figure 10 for the circuit diagram and Figure
11 for the circuit timing.
FIGURE 9

NO.2 DELi ( CIRCUIT TIMING

The memon flJ;J"fl'l' WL-G .:, l~'j"PR(, t «! ~h\~ beginning
of a con\'f.:rsi()1\ b. th> READ THIGllEH pulse ("zero"
pulse). The IJUt-pLt ',:f W2-C 11 IS tllerefr)rt! a "zero",

The function of this circuit is to supply a ~round path
for the Word Drivers (WDPSS0) and the Channel Driver (CDPSS0), and to generate the Analog Completion
Interrupt at the end of the conversion cycle.
WORD DRIVER

SCR

r-;;v',
I

'
d

CHANNEL
DRIVER

9

POWER SUPPLY

I
I
I

-<~

I

SWITCH OUTPUT

~
X9

____

"'--M--.-4--< <_Wj>~S§.~

OUTPUT OF

X8

DELAY CI"lCUIT 11'2

Lj!~~~
08-2

[)j.55 ®,:.6.2

...
I

P-.....- I.......-II,.,~

fT~.8

I
I

A26

'1

I LOAD
I R
-..I -~

I

I

I

'-'+f-I---,

It:
'-'
L

II

I.J

__________-~J

c·

f

I

,

II

j

l

:::
I

n n __________

ANALOG
COMPLEnON
INTERRUPT

+26V

~~:1- -

J

t-.-t............M--. .-

EXTERNAL
INTERRUPT
INPUT CIRCUIT

r----'

01-56 R28-5
.............+-lm...

+----':-.~, -I ~ - :
I....L

I

IT
I
I ?___ ...JI
L

.1

0;-53

I

X21

I
+2f,/

r-~~-,
+26V

I

"'6-'

INVERTED OU1PUT OF
SECOND RING COUNTER STAGE

R26-14

PSS OVERIDE
FROM
----...::;;;.....::.;.;:;..:.==-----------«
~ ANALOG
X7
TRAP

FIGURE 10. PS SWITCH & I.HI.LOG COMPL. IHTERRUPT CIRCUIT

1-4

1.Jl

I20PPS
TIMING 0

I

I

S8:OND STAGE

If only the 120 PPS Signal is present, It can be seen that
no matter what state the flip-flop. were In to ltart, the
Analog Control circuitry will come to a
This occurs when the output of all flip-flop' il "zero".
In this steady state condition, all flip-flops are reset,
which is the same state that exists following the completion of each analog input sequence.

_ _ _ _ _ _ _ _ _ _ _ _ _ __

.tand-.tm.

I
I

I I
I I

I

I

jo!- -_ _ _ _ _ _ _ _ _ _ __

RING COUNTER
: I
W2-E5
O--.!..J
I
I

DELAY C,RCUIT I
NUMSER TWO
W2-GII
0

J

!

I
I

The timing sequence of the Analog Control module is
shown in Figure 12.
The sequence begins with the 4 1-£s READ TRIGGER signal from the span and gain (SB) module, which sets the
DELAY CIRCUIT NUMBER ONE-FF via transformer
X1-1 and transistor T5-1 and resets all other flip-flops.
The DE LA Y CIRCUIT NUMBER Ot-.'E-FF resets all
counter modules via transistor T5-2 and times out
DELAY CIRCUIT NUMBER ONE for 8 ms to permit
sufficient settling time for the point, bus, and guard
relays selected and the V/F converter.

I

F"CHfER SUPPlY

I

,.1_ _ _ _ _ _ _.....,

I

SWITCH OLITPUT

H-I

O-....J

1
I

I

ANALOG
,
COMPLETiON
~~6ERRUPT 0

I
I
I
I

"I

CAFlllCITIVE
LOAD
~
CHARGE UP
INTERRUPT
CORE SET

The timing sequence (Figure 12) shows three conditions
for the READ TRIGGER pulse:
A. For the latest possible READ

FIGURE) 1. PS SWITCH & ANALOG COMPL. INTERRUPT TH,lfNG

Xo rn1J. 11 v . (under steady state conditions). mteg-rated
circuit X,-\:\D W2-F5 is a "one". thus, transistor T5-H
is conducting and supplying a large base drive to the
power supply sWItch transistor 1'7-1. Transistor T7-1
is, therefore, normally conducting and providing a
ground path to the word and channel drivers. Transistor T5-10 is normally blocking.

B.

For the earliest possible READ

C. For a READ which was too late for maximum
scan rate (4 ms before timing pulse).
At the next 120 PPS timing pulse leading edge, following
the 8.0 ms delay, the first stage ring counter flip-flop
W2-Cll is set, which stops the reset of all counters and
raises the output of NAND W2-D5 to a "one". The trailing edge of the 120 PPS timing pulse resets the DELAY
CIRCUIT NUMBER ONE-FF, which also disables the
counter reset and raises the final isolating gate input's
to a "one" to enable all isolation g'a tes.

When the end of an integ-i-ation period occurs, the inverted output of the second \'lng' counter stage becomes
a "one". Then, for the duration of the "one" output of
the dehl CIrCUit number two, the output of W2-F5 is a
·'zero". Therdore, transistor TS-R and T7-1 are
hlockmg for this period of timp. There is sufficient
time for the word and channel driver SCR' s to turnoff.
DUring this time transistor 1'5-10 pulls the interrupt
sipul to ground,

Each V/F converter output is transformer decoupled
and isolated from the analog control circuitry via transformers X1-2, XI-3, X1-4, and Xl-5. The outputs of
the isolating gates to the counters IS via transistors
Tl-1-l, TH-2, TH-3, and T14-4 for V/F converters
numbers 4, :1, 2, and 1 respectively. The isolating
gates are enabled for one cycle of the power line frequency.

\\ihen the output of the dela\' cirCUit number two returns
a "ICI'''·'. transistor 1'7-1 returns to the conducting
statl'. ThiS actIOn returns transistor T5-10 to the
bloCKlllg state. thus rdurning the interrupt signal to
~ti\·.
This positil'e going pulse is recognized by the
process interrupt 1/0.
10

At the leading edge of the next 120 PPS timing pulse, the
second stage ring counter flip-flop W2-Ell is set, which
maintains the "one" output of NAND W2-D5. The trailing
edge of the 120 PPS timing pulse resets the first stage
ring counter flip-flop W2-Cl1.

The PSS OVERRIDE connection (Pin X7) from the Analog Trap (AT) module is provided so that upon detection
of a multiple point selection. the Analog- Trap circuitry
can open the power supply switch. A "zero" sig-nal on
Pin X7 will open the power supply switch and, therefore. stop the multiple point seiection.

At the leading edge of the next 120 PPS timing pulse the
DELAY CIRCUIT NUMBER TWO-FF is set and the time
delay is started. The trailing edge of the timing pulse
resets flip-flops W2-Ell and COincidently closes the
isolation gates blocking the VIF output signals and
opening the power supply switch.

AC Module Operation
Refer to the 3AC.J, schematic, ~; dwg. H3A343·
(Fig. 11).

1-5

analol oompletion interrupt i . . .t. With thy, the .M101 oonvereion cycle il oompleted.

During the two 120 PPS timtnl period. the V/F output
i.olating pte. were open for one cycle of the power line
frequency. Thul giving the Analog-to-Dig1tal IYltem
ita noise integration capab1l1ty.

Note that lufficient time il allured between the opening
of the power supply .witch and the earUelt pOllible output of the new Analog Input addrellel (approximately
1001<11 following the letting of the analog completion
interrupt) for the prev10Ul relay. to drop out before the
newly add relied relaYI piok up •

The power supply Iwitch i. opened for 1.8 ms to drop
out the Analog Input relay. lelected. Typioally, 0.8
ms following the closing of the power supply Iwitch, the

.I
I

""\

INTa"ATION

,1ItIOD

r\

120 ,,,.

.J

L..
,-

r\

-,

INTlGlATION

""101)

Y'\

I

I

I

I

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I

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I

r

1

Y'\
I

/\

I

INTIOIlATlON

""100

r-L..

/\:

~
I

I
I

I

HII

I

120 ",.

Ta-!

0

IIlAO
'1'11110111

XlO

I

0

I

I

IJI
o

I" 'UNI

COUNTI"
•• -ell

a...

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Aitr.'~

I

:Ii

II II
I

0

II
II
II
!I

II
II
II
II

il

!I
II

I
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IIIN'

OOUNTlIl
. . ·111
DI~y

0

~

.. a"

.-tll

IIO~ATIN' Ul'1

0
I

blAlLi . . . .
ANI) . .·AII

0

0
,.., XII

0
ANAL.DG
COMII INT.
1110

II
II
II
II

II

"lIlT L.?

0

II
II

~

~'-

"GURf 12. AHAL.OG COHTIfOL. TIMlHG SlQUIHCf

1-6

~I
II

~

FIGURE 13. 3AC4 ASSEMBLY (REF. OWG. 143A343, SUB 181

sua·'

,.~

:..--~~-~.~)'H~

------1~~----l""'-;,---l'--!Il-<.o>----l~~-~---..Ir.;~:----+----rQ ~ z
-:

~

•

4

:r

~ 11 >-

~...----+----------.-~ ~,~

>-

~r------------:;'~l>--

-<)

~---+-+----+-4-~~~~----~+---------------~x'>­
---~)(l>'-

-<1~(------~-------~----~~-----4-------4----~~~~

I

--C),,~~~--~------~~-------*--------~------~~.--------~---------~------~~--------~---

L

---'18
845A313 G03

FIGURE 10_ 10403 ASSEMBLY (REF_ DWG_ 84504313, SUB J)

-

l~

i

i

[i

li

L

[~

.'

I~

~L~
J

.

~~

•

-

~-

-

--

7

C~

,

--

J

J

J

~~

-<)["3-

:I

r

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~~

:::

:I

~~

f'

..,

1~

-----

--

--Lt-'

-"

i

2

j'

I1 ;

---

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I~! 1

7 l.

-~HI>

5·81T REVERSIBLE ANALOG OUTPUT MODULE

lA02
GENERAL DESCRIPTION

This card is used to convert binary digitd information
into a current or voltage level. A typical load is a low
resistance, electrically isolated, magnetic amplifier
control winding, Using a 25V power supply, two nominal output ranges are available, 10-0-10 mA and bO-O80 rnA.
The card contains 7 mercury-wetted contact, bistable
relays, 5 of which switch resistors in a digital potentiometer while the other 2 reverse the polarity of the
load. With 5-bit accuracy, 32 linear output levels are
available in either direction. With zero output being
included for each polarity, 63 discrete output levels
are possible. The impedance seen b~' the load will be
constant, regardless of level. This card ~an be plugged
into a contact closure output slot and an~-pair cable.
MIlO (originally used with the CB card) will connect its
output to 1 terminal block on the "half sheils". The
same cable used with the CCO' s may be used, connecting to suitable terminals on the half shell terminal
blocks.

POWER
Sl ) PPLY

6.8mA(28A.T. Nominal)

Muat Release:

6.8 rnA

Max vOltage at 35°C:

35V

Max di8sipation at 35°C;

1. 75W

COli rise:

14°C per watt

Current (rnA):

12.7

18.7

30.5

54.2

1.6

1.4

1.3

1.2

approx. 0.7V

or about 11 rnA, which is the output with zero load (including line) resistance.

BISTABLE
RELAY
COILS

DIGITAL
POTENTI0

Must Operate:

28
(256 + 2470)

(1142 for

.

4220

Komlnal Input voltage is 28V dc. Any change in input
voltage causes the sarr.e percentage change in the output
current. The maximum current drawn from the power
supply When using the 80-0-80 rnA range occurs at fullscale output and is 28V/ (326 + RL) where RL is the
load resistance including line resistance. If RL = 0,
the current is 85.4 rnA, which is also the maximum output current. To go to the 10-0-10 rnA range, additional
resistance is inserted in series with the load and the
maximum current is drawn from the supply when the output i8 about 55% of the full-scale, and is about 31 rnA,
assuming a short circuited load. Beyond 55%, the current decreases again until at full-scale it i8

These coils are normally pulsed USing word drivers,
channel drivers and a power supply switch under program control. If they are switched otherwise the followin~ data can be used:

DIGITAL
INFORl'vlATION

10% at 25°C

Resistor :-';etwork

Relav Coils

;;~;l5

Turns:

Series diode drop:

Input Requlrlmlnts

Clare HGSM
reversing)

675

Operate time (msec);

CIRCUIT SPECIFICATION

Type'

n!

Resistance:

REVERSING
CONTACTS

o ME-E1 it

FIGURE I. BLOCK DIAGRAM

3-1

LIMITING
RESISTORS

f--+

TO
LO,. 1~D

Output Rillulrtmilltl
For the 80-0-80 mA range, the load is connected to X3
(+) and X2 (-). Two, 350 current limiting resi8tors
on the card are in series with the load to avoid damage
in case of connection errors. If the power supply has
negligible internal impedance, the switched resistors
can be considered connected in parallel when calculating the resistance as seen by the load. Thus, the load,
which may be a magnetic amplifier winding, will see a
constant resistance regardless of the output level. All
the switched reSistors in parallel equal about 256 O.
The total resistance as seen by the load is 256 + 2x35 =
326 O.
To use the 10-0-10 rnA ran~c, additional rcsistancc (21200 0) is inserted in series with the load when connecting to the 10-0-10 rnA output terminals X9 (,) and
X7 (-). This raises total resistance seen by' the load
to about :n:lO ll.
Note the output is linea r, that is the steps arc <,ven. regardless of load. Also note that a single power supply
is used and reversed polarity output is obtained by
switching the load leads. This requires the load to be
electrically isolated. If it is not, indiVIdual isolated
power supplies would be needed to supply reversedpolarity output to loads connected to a common.
Other ranges could be achieved by varying the input
voltage, adding aeries load resistance, or connecting
the load across X3 and X7 sO that only one 1200 0 resistor would be in series with the load. This would
give a looking in resistance of 1491 fl.

On the 80-0-80 range, the voltage needed may be determined as the full load current times (326 + R L ) where
RL is the load resistance. On the 10-0-10 range, use
2656 instead of 326. Nominal voltage i8 28V.
Changes in input voltage are reflected directly as output
changes. The supply regulation should be as good as. or
better than. the desired output stability. With 3% steps.
a 1 % supply is recommended.

CIRCUIT DESCRIPTION
Five reSistors. whose conductanr.e is proportional to the
binary bit they represent. are connected to the output bus.
Their other ends are switched by relay contacts to either
the positive or negative supply terminal which can be considered the output common. The open circuit output voltage is proportional to the conductance switched to pOSitive. Two other relays reverse the load on the output
terminals to provide negative output. Two 35 0 resistors limit the current in the load cirCUIt in case voltage
gets connected to it by mistake. Two 1200 n resistors
limit the output if the nominal 10-0-10 output range is
desired.
Note that in outputting binary information to this card.
the magnitude of the step must be output to bits 0-4 (711) and i8 always handled as a positive number. Bit 6
(13) can be considered as the sign bit (0 is + and 1 is -).
while bit 5 (12) will be its complement. The bit pattern
for a positive step 3 is 0100011 while a negative step 3
requires 100001l.

•••

Contact protection is furnished across the reversing
contacts which are the bridging type.

power Requirements
Input and output are generally limited by heating in the
500 0 resistor which is rated 5W. However, the dissipation must be limited to less than thit; to avoid board
damage. With 120 rnA output on the r-0-O-80 range, the
dissipation would be about 1. 8W which has been found
safe. If higher outputs are needed, they should be
checked experimentally.

3-2

M23-1

M23-2

M23-3

U U

M23-4

M23-5

M3-1

I
I
I
I
M3-2 I
I
I
I
I

H

r-~18

W
I
W

I

L

a::

1
o

o
845A31] G02

FleURE 2. 'A02 ASSEMBLY (REF. Dwe. 845AllJ. SUB 3)

r---~18

c."
I

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:3

1..

1~.

~

r

~

I~.....
~

1.,

l~

r

~

..,j

;..

l:

l:

-.

J

11.91.-1
J1

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--

)(7)-

y."

T

-;-

11.85-1

~

'C'
ITI

...
~
~

-lCt>-

4AOI . HIGH SPEED ANALOG OUTPUT
GENERAL DESCRIPTION

Addr... lnl

The High Speed Analog Output subsystem is comprised
of one or more 4A01 cards. Each card contains two
analog output circuits, and can be used in slots 1 thru
14 of a D-Panel. Each card provides high speed conversion of the digital input from the computer to an analog output. An appHcation block diagram is shown in
Figure 1.

• The program would address the cards using the
normal direct channel output instruction.

Accuracy
•

0.78% of full scale.

Sp..d
The time conatant of the output amplifier is
50 j.&sec. The response 1s 50 j.&sec + time delay due to
programming.

] NO.1
OUTPUT

Cr1ANNEL
HALF SELECT

CARD EDGE MNEMONIC BREAKDOWN
HIGH SPEED
ANALOG OUTPUT
MODULE 4AOI
OUTPUT
DATA

BITS

0-13

Mnemonic
Control Winding (Pos) of
Mag-neUc Amplifier No. I

~ OUTPUT
NO.2

35 Pin ELCO

Xl

Control Winding (Neg) of
Magnetic Amplifier No. I

X2

Feedback (Connect to Xl)

X5

SPECIFICATIONS

Test Point

X6

Input Requirement.

Ground

XIO

+ 10V Return

Xl2

-15V Return

Xl4

liD INTERFACE

FIGURE 7. APPLICA TION BLOCK DIAGRAM

• The half-select input, 00 (n) 0 and 66tJ (n), requires a minimum 11. OV, 4 !-Isec pulse.
• The data input (OD13 etc. ) require logic level
signals of "zero" (l. IV max) and "one" (4. 4V min).

+

Output Requirement.
• The load resistance should be less than 20 ohms
for current output.

P"wer Requirements

O'itput

27V. + 10% - 15%. 230 rnA

•

+

•

+ lOY, ~o.

•

- 15V, ,:0.01%, 80 rnA

01%. 30 rnA

IOV

Xl6

Control Winding (Neg) of
Magnetic Amplifier No. 2

X21

-15V

X24

Test Point

X33

Feedback (Connect to X35)

X34

Control Winding (Pos) of
Magnetic Amplifier No. 2

X35

CIRCUIT DESCRIPTION

Ranc.

Each analog output card has two output circuits; where
bits 0-6 provide one analog signal (A0 No.2), and bits
7-13 provide another analog signal (A0 No.1). The
digital-to-analog conversion for one circuit is as follows

• -10 to 0 to + 9. 844mA. using 6 bits for magnitude (64 steps) and 1 bit for polarity (bit 13 for A0 No.
1, and bit 6 for A0 No 2).

4-1

Aaalog Output (mA)

Digital Input

-10
-7.5
-5.0
-2.5

1000000
1010000
1100000
1110000
0000000
0010000
0100000
0110000
111111

1°

(bit 13 or
bit 6)

CHANNEL
HALF SELECT

OUTPUT
DATA

o

r----~---- -~----,

+2.5
+5.0
+7.5
+9.844

REGISTER

,
(bit 7 or
bit 0)

The entire output characteristic curve is shown in Filure 2.
DIGITAL TO
ANALOG
CONVERTER

Oil 1111
0111100
0111000
0110100
0110000
0101100
0101000

r
DIGITAL
INPUT

01001 00
0100000
0011100
001 1000
0010100
0010000-

CURRENT
PUMP

1

=

1

l£!R~I!..

-10_

I

I

I
I
__________ ..JI
OUTPUT

I

I

I

110 II 00

I
I
I

FIGURE J. OUTPUT CIRCUIT FUHCTIOHAL. DIAGRAM

1101000
1100100

I

I 100000

I
I
I

10 I I 100
10 I 1000
1010100
1010000
1001100
1001000
1000100
1000000

I
I
I
I

I

DIGITAL
INPlIT

FIGURE 2. OUTPUT CHARACTERISTIC CURVE

Each of the two output circuits can be separated into
functional elements as shown in Figure 3

RI,lstlr Circuit
In the register circuitry (see Fig. 4) a logical "one"
is defined as 14. 3V and a logical "zero" is + 7. 5V .
Under normal steady-state conditions. no...!ol~es are
included in the transformers and signals ~O. 01. and
SAMPLE are logical "one's". The NAND nip-nops
may be in any state.

When a 4 ",sec half-select pulse is applied to terminal
L2. transformer XIS is pulsed and capacitor C20 begins
charging. thus saturating transistor Q (in a NANO) for
the first part (nominal.) of the 4lJsec. This grounds
s.!(nal SAMPLE. tending to turn all the flip-flops off
(BO and Bl go to "one·s"). Meanwhile. transformers
Xl and X2 are being pulsed. If data line 0000 has~
zero on it. winding 1-2 will be shorted and signal DO
will not deviate far from + 14. 3V. remaining a logical
"one". Therefore. SAMPLE going to + 7 . 5V will determine the final state of the flip-flop (0).
If. however. data line 0000 has a "one" on it during
the 4 ",sec half-select time. a voltage will be induced
in winding 5-6 caUSing signal DO to be driven in a negative direction until diode 01-15 conducts. clamping
DO 1 diode drop below+7.5V.which is a logical "zero".
Flip-nop output BO is at a "one" as well as BO. However. 8ignal SAMPLE will retum to-#l "one" sooner
than 00 (8ince XIS is capacitively coupled to Q) allowing

4-2

04-2

2

+26V

A2H5

R21-1

R21-2

~{~: -+J~:

/

r--------,
"1-+_--,1

04T4 SWITC'iES
iN COMPUTER

04-1

I
I

01-1

I
I

+ 14.3V

I
I
1
1
+7.5V

1

L - _, ____ _

I

I OF 2 SAMPLE GENERATING
CIRCUITS FOR 4 13 BIT
REGISTER

H3
_ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _._ _ _ _......>--_ _ _ _ _ _ _ _ _ _--,S=A:::M:..:.P.!:.L:.....E_ _ _ _ _ _ _~

FIGURE 4. REGISTER CIRCUIT

BO to go to zero and leaving the flip-flop in the ""nl""
state. The basic criteria is that SAl\JPLE must ~o_!:,'
zero Inn" enough to switch the flip-flop off and the D
signals. if they switch, must remain at zero lon~ enough
after SAMPLE returns to a "one" to Insure the flipflop staying on.

Oigifal-fo-Analog
Each
•
•
•

Conve~fer

djgltal-t()-anaJo~

i'nnt..1.ins four, isolated PNP inverter stages which operate from comm0n emitter and collector supply voltages.
\ ...·hl'n Clsed WIth a positive emitter supply, it can drive
:)()th plus and minus current to a ladder switch network.

Ladder Switch Network

Circuit

converter

(\\'5)

The ladder sWItch network, shown in Figure 6, consists
of four, clouble-throw analog switches. It is intended to
drive the cligital-to-analog resistor network. The inputs
of the ladder network switch either to + lOY or to ground.
It IS deSIgned to be drive"! frorn a plus and minus signal
input such as the huffer amplifier.

cuntall1s'

one J-blt huff~'r amplifIer
nne i-bit ladder switch
one ·J-bit ladd"r network

The buffer amplifier network. shown in Figure 5,

14.3V

OUTPUT

TO
LADDER

NETWORK

OUTPUT

3.31< TO
LADOER

INPUT

.....--------......--- - - - ---

SWITCH

FIGURE 6. LADDER SWITCH HETWORK
FIGURE 5. BUF'FER AMPLIFIER NETWORK

4-3

4-Blt Lldder Nlt••1t
The ladder network, shown in Figure 7, is a precision
resistor network intended for digital-to-analog conversion. Inputs A. B, C and D are connected to the ladder
switch which is switching either to + 10V or to ground.
The open circu1t output voltage is 1/2 the voltage at input A, plus 1/4 the voltage at B, plus 1/8 the voltage at
C, and so forth. Thus, the resulting open circuit output voltage is a properly weighted sum of the individual
binary bits.

MNTt~

y

b t

TO

TO
LAOOER

L.S.

SWITCH

2R

R

R
v.

R

~.

a-

fr;J;f!»

t:'

.

TO
L.s.

Rt,ias can be adjuated for zero offset 80 that when i 1 =
200 ~A. 12 = O. R3 can be adjusted for full scale so
that when i l = O. i2 = -lOmA.
A curve showing the complete input/output current relationship of the current pump is shown in Figure 9.

1
.5
.RI

FIGURE 7. LADDER HETWORIC

Curr.nt Pump

~~~----------~----------~
o
200
400

The current pump, shown in Figure 8. consists of an
operational amplifier. a current booster circuit (B).
and three resistors. It IS defligned to operate as follows:

Illn ~

FIGURE 9. CURREHT PUMP IHPUTIOUTPUT CURVE

•••
INPUT

c

FIGURE B. CURREHT PUMP DIAGRAM

when

il

0,

i2

-lOrnA:

when

11
i2

200 !-lA,
0:

when

il
i2

400 !-IA.

+ lOrnA

4-4

rB

5AOI

Q73-1

I

~·~~_~I

.... -_-.. ....

8

~--

35
H

.----~18

x

O!

°

~ 06

L

° XI-140110 XI-13 °

o

°

60

10

jT-~_
If

-i.
r

FIGURE 10. 4AOI ASSEMBLY (REF. DWG. 845A338, SUB Z)

I

R56-1
R56-~

18

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0002
Bil 2

=-

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Bit 12

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HI

0011
Bit 11

0010

OD08
Bit 8

~
Bit 10

lBill

Bit 7

Eill- OD07

Bit 6

0006

Bit 5

ODOS

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~1 -j-"'-':'---11-;'4. ~'1 ..
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-1_"

4APl/4AP2 - ANALOG POINT SELECTION MODULE
GENERAL DESCRIPTION

Output R,"ulr.m.llts

The Analog Point selection module contains 14 identical relay circuits and one bus-guard relay circuit
whlch are used to connect a selected analog input
pOint to the voltage-to-frequency converter. The 4AP2
card differs from 4AP1 card by having a high output
impedance voltage source connected across the PLUS
and ;\U:-;US busses used for open input circuit detection.
An application block diagram of the Analog Point selection card is shown in Figure 1.

The PLUS, MI:-;US and GUARD outputs are physically
connected to the selected analog input. These are to
be connected through the analog bus to the input of the
voltage-to-frequency converter.

A~OG

I,..PUT
TERWI""ATlOhS

I
0:

.,

!i

~



z

~

i

r--------

VI

3

Go

(7Tl«R
AI' CNIOS

:
L

---1'

»/

___

",o-I!

~~--I

I

--)>1

1I0()-16

"""'=<---11--1- - - ---)

VlF

COIIV[II'TEA

I

I

IIlo~e1..,., ! I
I

5

--j

I

I I

~
I

FIGURE 1. APPLICA TlOH BLOCK DIAGRAM

CIRCUIT SPECIFICATIONS
Input Requirements
Th.· \\(.]'(i drin'r input \\TI (n) rpquires a conducting
path tn the - 10 V power 3uppl\ if the \Iord is selected.
The' channel driver Input CD (n) requires a conducting
path to PSC if the channel is selected, otherwise it is
- 26 \.

The ch.1nnel driver bit inputs, CD (n) bits 0 through 13.
requlre a conducting path to PSC if a bit is selected,
othenllse there are - 2£ V. The analog inputs are
D. C. \'oltages either in the 0-50 mV range or in the
0-;; \. range.
The guard is to be connected to the shield of the analog
l11put signal.

FIGURE 2. BUS, GUARD AND INPUT RELA Y CIRCUIT

5-1

When channel CH (n) is selected, the channel driver
seR's are turned on (only one bit should be selected
out of the 14) which now provide current to PSC through
the power supply switch for the guard relay (MIO-I6)
and one of the point relays (MIO-I). The guard relay
contact. after a small time delay, will then energize
the bus relay (MIO-IS).
Since all the point relays, bus relays and guard relaY8
are mercury-wetted contact type, the input point relay
contacts and guard relay contacts will close first, then
the bus relay contacts. When the power supply switch
opens the SCR' s cut off and the relays drop out. The
time sequence of operation is shown in Figure 3.

The 4AP2 module containl exactly the I&me circuits as
the 4APl module, except that a high output impedance
voltage lource 11 connected acroll the PLUS and MINUS
bU8lel. This voltage lource generates a-50 mV signal
which i8 recognized by the computer as an open circuit
indication.
The voltap 80urce itself (ref. 4AP2 module schematic)
co08ilts of an oscillator which 18 energized by the + 26
Vdc lupply. Thil o8cillator 18 tranlformer coupled to
a rectifier circuit, which il produCing the required
50 mVdc lipl.

•••

",,'s

n... on

--'-I

o

j

'-,

_100 COHTIeT CURD

•

0

,I

""

. . . COOiTIC'T CUJS(D

FIGURE 3. SEQUENCE OF

OPER~ TION

5-2

4j~PI

I

r-

~

MIO-3

35 ....-

Mro-4

MIO-5

1110-6

M10-7

MIO-16

•

MIO-2
MK>-I

--D!:I}-1151-1 ...
c:.n

~
~

-II 06-6 ...

-nBI-

-a

51-It~
~ -t!oe-141-

-t!!:!!J-

-1-- 13 t-

-m!!:!n-

-tu.-Dt-

-m!!J-

18

-{]ED-

I

I

c:..:l

Mf~8

-

-[
....-

M10-9

,.UO-IO

~

-tmEiD-

MIO-II

M10-12

M10-13

M10-14

~

-DD6;zt ..

M10-15

-m:n-L2!:!!J}-

145A3I3-GOI

-GED-

-{]HID-

-II
..
-oBI}~Q!:ul'" -IRI::~I'" ~

-UtiiII-

FIGURE 4. 4APJ ASSEMBLY (REF. DWG. 74U1U, SUB 2)

"'IEZI~

-I DEllI-

~•

18

10 -JolDGo c .... ~_~ OAIVIUl
r -____________________________________________
____________________________________________
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.

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s. .. ,~~O

~rl·------------------------------------------------------------------------------------~c:;--~~>
MIIO·'b

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-

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FIGURE S. 4AP' SCHEMATIC (REF. DWG. 74JAJIJ. SUB 2'

2
0

i

!!

!i

~

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i

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~

i"

~
il
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9

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.... t.i

SI

I

4AP2
I
~

35

r'

M19-3

----'

..-

M10-4

M10-5

M10-6

M10-16

M10-7

·H •

Ml0-2
MIO-I
...[]E!}-

-«l!ID-

"x"

-D

pi-I

t-

-m:::n-aBJ)-m:D-

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1I!7-1 t-

~I

-t

R9-1

.t- 8

M10-8

- [:

MIO-9

MIO-IO

MIO-II

M10-12

M10-13

~

-Em-

M10-14

MIO-15

-ImEm

-11126-11 ~

18

I

~•

I~

---'

-im!:1D-

~

743A313-G02

-iQiJD
-{]!D-

~

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-Em-m::zm- -I15I-B I-

-m:an-

-lQEDD-

FIGURE 6. 4AP2 ASSEMBLY (REF. DWG. 74JAJIJ. SUB 2J

-I Di-:mB-

I

,

TO ",,,"'l.QG. C .... ~~'- DRIVER

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FIGURE 7. 4AP2 SCHEMA TIC (REF. Dwe. 7431.313. SUB 2)

Y

XII

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Y Y Y Y Y Y

2AT3/2AT1/1SRl - WORD AND CHANNEL TRAP
GENERAL DESCRIPTION

detector output signal. This circuit then drives an SCR
relay puller that forms a sort of last line of defense by
the "KILLER RELAY" which physically interrupts the
matrix input current by opening series, normally-closed
contacts upon failure detection. Reset of this circuit
can occur only upon manual removal of either the 2A T3
card or the AC card, or upon normal power supply
switch operation on the AC card.

The basic principle of operation is to sense (as an analog voltage) the state of each word and channel driver.
It is expected that one (or less) channel driver and one
(or less) word driver per V/F converter, will be conducting at any time. Thus, five detector circuits
measure the analog summation of voltages produced
by these drivers. Should the expected summations be
exceeded. multiplexer disabling and fault interrupt
results.

Normally, failure detection cause,; a mono-stable multivibrator (on 2AT3) to trip, causin!l; a fault interrupt
signal to be initiated and Simultaneously generate the
power supply switch override signal to the analog control (AC) module. For nominal AC card behavior this
signal will disable the power supply switch, again
cancelling existing word and channel driver activity.

CIRCUIT DESCRIPTION
The only difference between the 2AT3 and 2ATI is the
value of resistors R26-3 and R53-2. However, circuit
operation is identical. Resistor-diode summing circuits (ISRI card) are provided for connection to the
respective driver SCR's. This configuration is shown
in Figure 1.

--

su~"'- T

Since this action is faster than either the pomt relays
or the "KILLER RELAY", all relays are prevented from
picking up. However, if the power supply switeh is not
nominal, the "KILLER RELAY" will operate as described previously.

..,...

SwrrCH

'''C)

The estimated maximum tolerable time from trip until
Fault Interrupt action (I. e .. setting of the corresponding ckt. core) is approximately 1/! ms.
NOTE
No contact protection is prOl ided for the
"KILLER RELAY" and for th;lt reason, because point relay damage ~' have been
sustained whenever the fault was cleared
solely by "KILLER RELAY" operation, it
is recommended that these contacts be carefully inspected prior to restarting under such
conditions. This wdl be recognized as a
complete disabling of the analog multiplexer
with the "KILLE R RE LA Y" eontmuously
picked-up.

,AT

I

i

\

:

t~·~

I'SRll

~--+--- .. ~

. ..• t

f;~v7':i 1- .,.
(SCA S.

.

~

TO ~fA SuPPlY ~ITC" "
(THfJofCI ~ PO'M£III SUPP', 'f'
VIA

'Ul.[R

RELAY

LARO

ca.e)

lAl

The effect of either of the modes of failure behavior
discussed previously is, unfortunately, related closely
to the type of failure and when it occurred in the cycle.
It is doubtful If this failure can be adequately predicted.
Accordingly, the analog input programs should expect,
upon receiving an analog Fault Interrupt, that the previous converted input quantities are suspect, as are
subsequent quantities. It is pOSSible for more than one
seemingly valid analog completion interrupt to occur
incorrectly. It is at this point that the programs should
abort current scan operation and, after a delay of more
than 35 ms, scanning can be reinitialized.

FIGURE 1. WORD AHD CHAHHEL TRAP COHFIGURATIOH

The detcctors (on 2AT3) monitor current provided by
the summing resistor networks, that causes. a reaction
when any of the five possible currents (channel, word
group #], word group #2, word group #3, or word
group iH) excecd a level greater than was expected to
be produced bv a sJngle conductive SCR. The detectors
are emitter-coupled differential amplifiers with paralleled outputs.
Noise rejection is aided by, a zener diode threshold
followed by a filter and a common emitter switch amplifier, which further processes and amplifies the

***

6-1

2AT3

35:[

MIO-I

1

R52-4

~ ~ ~ @~® ~~,C22-1 ~ ~I~

-..,

______ IS

®~®®® ~ e eeeeeeeeS8

x

H

~
~I
iL

8~0 ~0 ~

• I

~~~ ~ , ~

---J

~I

L

_____ 18
745&394-GOI

*NOTE: FOR UTI CARD, R26-3 IS R2I,
AND R53-2 IS ~.

FIGURE 2. 2~Tl/2~TI ~SSEMBLY (REF. OWG. 74J~J94, SUB 6)

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Dl It
--wer supply voltages and switching arrangements.
2CB4
2CB5
2CB6
2CB7
2CB8
13.

48 Volt, standard filter

26 Volt, non-filtered
125 Volt, standard filter
48 Volt, low energy filter
26 Volt, data link filter

Circuit Specifications
1.

I nput Requirements
a. I nputs from contacts or switches
The inputs to the module from the contacts or switches are either a d.c. voltage
level or zero volts. The presence of the voltage produces a "one" input to the
input interface while zero volts produces a "zero" input to the input interface.

7-1

The nomina 1 magnitude of the input voltage level at the module and the inrush resistance of each bit of the modules are:
~0dule

Nominal
Voltage

Type

2CB4
2CB5
2CB6
2CB7
2CB8

Inrush resistance/bit

48

13K

26

125
48

43K
65K

26

511

b. I nputs from Channel Half Selects
The half select winding (Row HS and Col HS) require a minimum 11 volt, 4 microsecond pulse.
2.

Output
a. Output to I/O interface ( input data)
The data output is a minimum 6 volt, 4 microsecond pulse to the I/O interface.
b. Output to power supply switch trigger
The output is clamped at approximately at a one volt level until the power supply
switch is reset.

3.

Power
The only p:>wer connection required by this card is the negative side of the 48 or 125
volt power supply.

C.

Circuit Description
1.

Data (2CB4, 2CB6 and 2CB7 modules)
Figure 2 illustrates one bit of the 14 bit data buffer register.
Transformer:
Winding 5-6 is primary, N turns
Winding 3-4 is secondary, N turns
Winding 1-2 is tertiary, 2N turns
Filter

lw

2CB4
2CB6
2CB7

RA

R.B
5K
5K
25K

13K
43K
65K

7-2

CA

Tmfd
.5 mfd
.1 mfd

SUB COLUMN HALF SELECTS
(~H~.)

r - - - - - -- --I
+v

RA

-1

I

REMOTE
CONTACT

!:;

DATA
I

!:;

I

RB

i:

DA

CAl
I

~

0

I

,:2

RETURN
L -

- - FILTER

-

- __J

DATA COMMON

TRANSFORMER
-

SUBROW HALF SELECT

(.4'~)

Figure 2
When the remote contact closes, a voltage across capacitor CA will build up as determined by the component values of RA, RB, CA. When the remote contact opens,
the voltage across capacitor CA will decay as determined by the component values
of RE and CA.
When the channel ha If select circuits are energized, the transformer primary winding and series lK resistor will have an applied pulse of about 4 microseconds duration and 12 volts magnitude. The energy available from the primary winding will be
"auctioneered" to either the secondary or tertiary windings, depending upon their
relative impedances. I f the capacitor CA is charged, the tertiary winding appears
as a high impedance and most of the pulse energy is available at the secondary winding to supply an output pulse. When the capacitor CA is discharged and acts like a
short circuit across the tertiary winding, the pulse energy will be transferred to
the tertiary winding and absorbed in charging the capacitor. There will now be
sufficient voltage across the secondary winding to produce a "one" signal to the
pulse output circuit. The lK resistor in series with the primary winding provides
current limiting. The diode DB prevents a negative pulse output on inductive flyback.
2.

Data (2CBS Module)
Figure 3 illustrates the input portion of one bit of the 14 bit data buffer register.
The transformer primary and secondary circuits are the same as shown in Figure
2.
Thp operation is similar to that described for the 2CB4, 2CB6 and 2CB7 modules
except that the impedance on the tertiary winding is dependent upon the state of SCR.
\llhen the SCR is blocked, diode D .~ is reversed biased, the tertiary winding appears
as a high impedance, and an output pulse is generated. If the SCR is conducting,
the tertiary winding is essentially shorted and no output pt.llse is generated.

7-3

+26v
1- - - .- -'-

.-------<
.. - - 0 - -..........
Remote
I""I1II
SCR
Circuit

5

I

1
•

DA

TRANSFORMER
. TERTIARY
WINDING

•

2C85

2
I

L ____ _

--..--PSC
Figure 3
3.

Data (2CBS Module)
Figure 4 illustrates the input portion of one bit of the 14 bit data buffer register_
The transformer primnry and secondary circuits are the same as shown in Figure
2.

+26v
Rl000n
(Noml nal)

RA

OA

'I---

:::)
Q.

z

Circuit
~

PSC

1

•

511
I-

r- -

r\

TRANSFORMER
TERTIARY
WI NOI NG

HFO

2~

2CB8

L _ ._ . __ .

Figure 4

The operation is similar to that described for the 2CB4, 2CB6, and 2CB7 modules.
The difference is that the voltage across capacitor CA is controlled by the state of
SCR. The time constant for charging the capacitor is influenced by the va lue of the
externa 1 resistor R.
4.

Control
The module conta ins a transformer isolated SCR used for detection of se lection of
the module channel half select circuits. When the transformer primary windings
are pulsed, the detector SCR turns on. The SCR must be turned off by remote
circuits_
Note that all of the 14 data transformer primary windings and the SCR transformer
primary windings are pulsed at the same time.
The schelllatic diagrams for the 2CB series are included with this description.

7-4

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4CDl - CHANNEL DRIVER MODULE
GENERAL DESCRIPTION

INPUT

+2IIIV

r----------- ------ -- -

This module (CD) is used to provide a 1~ bit channel
drlvl'r output to the I/o subsystems. It contains 1~
id,'ntlc;ti sen circuits and one gate triggering circuit.
:\n application block diagram is shown in Figure 1.

04-1

0013

.

I
I

R22-1

R1~1

I
I

01-1

I
~

6

•

I

I

I
I
I
I
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2

eee(n)~-----...J

OUTPUT

L.. _ _ _ _ _ _ _ _ _ _

813

PS.C
CHANNEL
DRIVER
4COI

BITS
0-13

POWER
SUPPLY
SWITCH

Thp gatp circuit c()nSlsts ()f lener diml£' Z7-1 in S('I'If'S
with the S('c"lld:l1'l Ilinding (::-01) (If ttll' triggl'r tl~lI\;';
former. The tr'l'tLtl'l \llrHling (I-:~) of the triggPI' tran;.;former is {'()nnt'cted throu~h diode 1)7 -I, When th" 111put is a logical "on"" diod" D7-1 is re\'ers('d hiaSt'd
which open circuits thl' tCI1.iarv winding. If th(' input
is a logical "zero
D7-J is grounded which shorUj liut
thf' t('rtial'l winding.

(n), require

It call 1)(' seen that Ilhen a pulsc (channel half-sPlect
litlli (n) ) appears across thf' [wiman
II tndmg (.'i-Ii) thl' Il)gi(' 1('\'('1 of th,' Input tine II III determine the I'oltagc on the sccondan (;1-·1).

Output Requirements

(n)

~Il (n)" and

zero"

With the input a logical "one". the Sf'concla l'\' (:1-1) \I ill
have a voltag(' induced in it which triggers Sl-J and
drives its output to a logical "zero". This occurs 1)('cause" 26 V tied to R22-1 will conduct through the
power supplv swiU'h to P5C.

nwn is normal!\ tied to PSC through the
P' ,1\(,1' supph switch. to reset the SCR circuits, this
!lHlst 1)(' oJlened for a minimum of 150 Ils.
('(1111

Power Requirements
,2(; \'

ONE CHANNEL SCR CIRCUIT

Initially the output tmnsistor of the power supph' s\litt-h
is saturated (conducting he:l\'ilq so that if a positi\'('
trigger pulse is applied lH'twpen thp gate and the C:I thod,'
of 51-1, the SCI{ will e(lncit!('t.

Th,' data inputs (ODl3. etc.) require lo~i(' le\'('I signals
"f "zero" (I. I \' max.) alld "one" (.!, ~ \' min.),

c [)

\.._.1 __

r-"

Input Requirements

rh" drin'r output (CD (n) HI:). etc.) requtres a
t(lr selpctcd hit and a "one" for unselected bits.

..,"

ps.c

CIRCUIT SPECIFICATIONS

t'!.,

, - ' , PC7tV£R Sl.PPl Y
, I \ SWITCH

',~'"

APPLICA TION BLOCK DIAGRAM

The half-sPicct inputs. ,,~ (n) ~ :ll1d.,
:t minimum II \', .! iJ.S pulse.

"

\

FIGURE 2.

FIGURE 1.

,

I

TRIGGER

--,

With the input a Inglcal "z"ro". no \'oltage will he induced in the secondan·. tht' sen II ill not conduct and
therefore the output will remain a I(~glcal "one".

is l'l'quircd for card operation.

CIRCUIT DESCRIPTIOH

The zener diode in the gate circuit is needed since the
tertiary winding is never completeii' short circuited.
Losses' in diode drop and transistor saturation drop account for a smail pulse across the secondan' \1 :!1dil1~
when the input is a logical "zero". When the input ,s a
logical "one" and the pal'ticuiar- channel is selected. th,
SCR's will be triggered in response to the half-select
pulse. The 5CR will remain in the conduction state
until the power supply switch turns it off.

E,tch "f the I~ bits of the channel driver consists of an
'-Tn II ith a 7,'n('1' diode threshold in the gate circuit and
:t thn'" winding gate trigger transformer.
In addition.
ri1t"rl' is ~nother SeR on the card \\ihich senses the 5el-

('ction of the channel and sends a trigger to the power
suppll slI'itch (CD (n) TRIG). Fi!{Ure 2 shows the dia~ra"l "f one channel 5CR and associated circuitn-. The
I "Ilnccti{)ns to the power supply switch are ShO\ll1 in
dottcd lines.

* • •

The operation of the circuit is explained as follows.

8-1

4CDI

-1 R22-14
-1 R22-13

35

:l

~

e~
-m::!D-

8~
~

B~o"-,,
~
XI-13

-tRI9-14

B~o,o-"
~
XI-II

-1 R22-11

Sl-II~
J- 8~

-1 R22-10

~

B~~H
~
XI-9

-1
-1 R22

8

~

-1 R22

7

~

-1R22

IS

~

R22-6

~

~

. , R22-S

~

~~
SI-IO~

51-9

~

-m=D--

B~

SI-8~

51-7

~

~
-11EJ}--@TI~

--illTI-

~

-11EJ}--

-I R22-4

~

-I R22-3
-1 R22-2

r
r

-{ 1t22-1

~

~

8-ITEill-SI-3

~

C4-3

~-Uill-il!::UISI-2~
C4-2
Sl-I~

C4-t

~

~

-m=:!!D--

51-12
-1 R22-12 J- 8~
-m:n-

R22 - 9

X

~

-1RI9-12

~

~

--m::ill}-

-1 R19-10

l-

~~

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B1 ~
B1
8 1 r
XI- 7

+-

-1 R19-8

--m=:I:D-

I-

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0

XI-5

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XI-3

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XI-I

°'0-'

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8

~ RI9 -1

4

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B
B
B

XI-14

XI-12

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H

XI-IO

EJ
EJ
EJ
EJ
XI-8

XI-6

18

~

XI-4

L

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-IO'H.
~B
-1 Z7 - IS IXI-IS
-m::!il-

FIGURE 3. 4(DI ASSEMBLY (REF. DWG. 743A391. SUB 3J

18

~~----.

----- -----------,--

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C.:>

FIGURE 4. 4(DI SCHEMATIC (REF. DWG, 743A39J, SUB 3)

SCll - CALIBRATOR MODULE
GENERAL DESCRIPTION

Power Requirements

This module is used in the analog input subsystem to
provIde accurate voltage references for system calibration, RTD measuring circuits for measurement of
the thermocouple cold junction temperature, and a
power supply switch circuit used in conjunction with
the span driver circuits (sec S8 module). An application block dl:.q:;ram is shown in Figure 1.

Connections to + 26 V and PSC are required.

CIRCUIT DESCRIPTION
Since the 5C L module contains 3 functionally independent
CIrcuits, each of these are described separately.

Volta,e Reference Circuit

~._._

I

~P!.JT

The circuit diagram of the voltage reference circuit is
shown in Figure 2.

r-------,

r--:.u:";;[l""76-'
_ , 'ELECT

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_______
JI

C.t.lIBRATION
110

INTERFACt::

~Cll

r------- L
RTO'~ I~

I

:

L

JU~~ ~~BOX

_

--,

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L - ..----

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v,

I

I

I
I
I
I
I
I
I
I

A13-1

82 511

TP(+)

LOAD r:F

RID

FIGURE I. APPLICATION BLOCK DIAGRAM

R72-1
22KotOOI%

BRIDGE
ClRCLITS

CIRCUIT SPECIFICATIONS

~~OOI%

Input Requirements

1
r

L---iS & ",II!
S1:r ll!

The channel I r, half-select input requires a minimum
II \. cf!-LS pulst'.

20111f'!)
CIO-2
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CLCARO
- - - - ________________
.JI

~~

TO ANAlDG INPlJT CARD

Bit -: input requIres a logical "one" if selected ami a
logical "zero" if not selccted.

FIGURE 2, VOLTAGE REFERENCE CIRCUIT

The RTD Inputs require a 100 ohm, :.; wire RTD conncction.

The in~oming power supplv voltage (t 26 V) is fed to a
voltage regulator, M36-J, which is a voltage clipping
ci rcuit containing zener diodes. Since the voltage reference divider circuit. R72-1, R72-2 and R86-1, and the
load of the RTD bridge circuits constitute a constant
load, the voltage V (measured between test points TP
(~) and TP (-) will 9,e a stable reference voltage. This
voltage is adjusted by potentiometer M18-1 to 8. 813RV
us ing a standard cell.

Output Capabilities
The refl'rence vllitage outputs provide analog voltage
signa\::; of:

v
\'

'J

1

O. O:l ~).., 7

0.01';;

cf.12G>i

O,Ol7r,

The reference voltages. determined by the resistance
values of R72-l. R7:.!-2 and R86-l, are VI = 4,4268V,
V 2 = 0.03987V.

The RTD bridge outputs arc 0-50 mV analog signals.
The' pO\\cr
PSc.

suppl~'

switch output is normally clamped to

These voltages are used to check the accuracy of the
V / F cnnve rter.

The rnaximum current th:1t C:l.n be carried by tht· s\vitch
is >i;'i() mAo After the trigger signal the switch opens
for a pcriod of 100 !-Ls. In the non-conducting state the
output is at ~ 26 V.

RTD Bridge Circuits
There are four, identical RTD bridge circuits on the

9-1

5CL card. These circuits are used to measure the temperature of the thermocouple cold junction boxes. Since
each cold junction box contains 2 RTD's, the 5CL card
provides for measurement of 2 cold junction boxes.
The circuit diagram of one RTD bridge circuit is shown
in Figure 3.
~-----------------~
III[F
VOLT!.) Vo
I

place of the RTD. The output of the RTD bridge is connected as an analog input. The bridge output depends on
the resistance value of the RTD. For example:
at RTD
at RTD

=

138 ohms, E out
188 ohms, E out

OV
50mV

Powlr SIIIIPly Switch
This circuit is a simplified power supply switch for the
span driver circuits on the SB card.

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The same voltage (V) :lh u~cd for tlie '!Oltaw~ rderences
is used as supply voJtagt' to th(~ RTf) br,rjges. Since rt 5i5tors R7:J-! and R7:l-2 are much grt:~~(:r thar, the RTD
resistanrt', the BTD re~lhtanc(' var13110n has J. rwgl 11.;1ble effect on the brld;;e load. ,,' .cn!-,:.!r, b,~ :''ll:-'IGt'rI'cj
constant. If a bridge ClrCUI! I" not. reqUired tor HTIJ
measurement, a dummy load lU;,-l is connected in

[:E:!J +26V

Figure 4 shows a simplified schematic of the power supply switch transistor and is normally turned on as long
as bit 7 of the span data word is a "zero". Winding 1-2
of Xl-I is shorted and no coupl ing can occ<.lr to winding
5-6 when the channel driver II> pulbed. rJnder these
conditions T6-I is turned off and held ofi by the clamp at
point "A", and T6-2 and T7-1 are turned on. 82-1 at
this time will be turned off.
If bit '7 is a "::me" and Xl·] iii lnte(r()~tcd. point 5 01
Xl-1 will go positive and rurn on T6-1 When Tfl-1 1s
turned on, the base of T6-2 forced ta ground. T6-2
and T7-1 will tum off lind the clamp at pOint "A" is
removed. At the same time, C4 begins to chaq;e, and
when it charges sufficientl\', S~-l turns on and forces
th(' base of T6-2 Ii) a positive valu(' ,>0 that T(;' 2 and
17-1 :1.gain wrn on. As s(oon at-; T6-~ turns on, point
',-\" I~ Ilgalr. clarnpt'ri \<. grlHlfid and Tfi-l :oi tUl'n"d off.
T~e p(:wer supply 1l\~Ill'h T7 -] tunl:; "rf for a pl'rlOd of
lime .Ietermmed lJy lhe chargl: tm,,: nt C4.

• * •

--------

~
CHANNEL
16 HALF BiT 7
SELECT

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4

2

PSC
'::'

FIGURE 4. POWfR SUPPLY SWITCH CIRCUIT

9-2

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FICURE 4. sell ASSEMBLY (RH. Dwe. 743A379, SUB 9)

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FIGURE 2. 3C*42 '3CM3 .SSEMBLY (REF. DWG . 743.361, SUB 9)

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CONTACT OUTPUT MODULE

2COl/2C02
GENERAL DESCRIPTION

TIll' 2C()1 module holds the contact output relays us('d
III the CCO suhs\stem. Each card holds 7 relavs. so
~ cards arf' requir('d for each II-hit relay register.
The card also has 7 suppression diodes, one for each

NORMALLY
OPEN

~

37.5n

n>(a\ and I isolation diodes. FiJ.,rure 1 shows how contact output Illodules al'e used in the CCO suhsystcm.

ARMATURE

;~

fO,1 MFD

NORMALLY
CLOSED

CUSTOMER
CONNECTIONS

~

WORD
DRIVER

t

t

2COI
2C02
7 RELAYS

2COI
2C02
7 RELAYS

FIGURE 2. RELAY CONTAC T SUPPRESSION NETWORK

At fiO liz the leakage imped:1nce is apprOXimately 2f), :JII(J
ohms. At higher frequpncies the impedance may he calculated usinp; thp follOWing formula:

Z (Oll\b) ,

CD
RESET CHANNEL

FIGURE 1

CIRCUIT

2

'Ii,:) ohm ...

CD
SET CHANNEL DRIVER

POWER
SUPPLY
SWITCH

~(...L)
,,,C

('1

I'

Frl
frpquency

DRIVER
Note that ('\'l'n in a de circilit the RC nptwork will p['pSl'nt a Inw imped:1nce to high frequencv components
which ma v be caused hI' noisp.

APPL/CA TION BLOCK DIAGRAM

OPERATION

I'll( r, hI S (II! til(' contact ()utput Tl1oduit- .1 J"l' le>ll~ life
1){)Ulwe' fn'('
hl~h spced mercul'l wf'tted t'lle,
The\'
:tn' m:lgllf'tlCalll lJiasf'd for bi-stable opf'r:ltion anri
hal(' r:"rl11 D (I1nk(' heforr hreak) contacts IIltha
Itl'idglllg tll1'>! of ,lpproximatl'1I IOOI-lS('l',

rill' rebls

,tl'('

cOlllposed of a hrrml'lic:till scall'd, ll1crt

,~:l"

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:'

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FIGURE 7. 2C02 SCHEMATIC (REF. DWG. 743A321. SUB 9)

XIZ

XII

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4CTl - COUNTER MODULE
In addition to the counter and buffer stages the card
contains zener diode power supplies for the NAND gates
in the modified NAND circuits and clamping voltages for
the coupling network circuits. In addition to these zener
diode supplies. a 6 V unregulated potential divider supply
is provided for the NAND gates within the slow NA!\D
packages.

GENERAL DESCRIPTION
This module is used to provide a 14 bit binary counter
\1 lth output buffer stages for counting the voltage_tofrpquency converter output pulses in the analog input
subsvstem. The module contains 14 identical counter
dements. each being connected to an output buffer. An
application block diagram is shown in Figure 1.

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FIGURE 1. APPLICATION BLOCK DIAGRAM

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CIRCUIT SPECIFICATIONS
Input Requirements
The input to the counter requires a 0 Pulse (PSC) for
advanc mg the counter. The maximum pulse rate is 1
:'Imz. The reset Input requires a logical "zero" (PSC)
iur resetting the counte r.

Output Capabilities
The output provides a conducting path to PSC for bits
IIhich are "zero" and a blocked path to PSC for bits
\\'hich a rE' "one".

Power Requirements
'26\',

+

4V, 450 mA max.

CIRCUIT DESCRIPTION

FIGURE 2. COUNTER CIRCUIT - SINGLE STAGE

The circuit diagrnm of a single staRe of the counter IS
shown in Figure 2. Assume that trnnsistor 1'14-1 IS
conducting and transistor 1'14-2 is blocked. Because
of the flip-flop connection. the base of trnnsistor 1'14-2
is pulled to ground (PSC). The bast' of trnnsistor
1'14-1 is at a positive potential, determined by the
voltage drop on resistor R4-1. as the current path
from + 6V (Pin 4) to PSC will be through R3-1, Dl-S,
Dl-6 and R4-1.
Capacitor C 1-2 will be charged so that its term inal
toward the base of trnnsistor 1'14-1 will be negative
with respect to the terminal facing the input to the
counter.

Each counter stage consists of two :\A:-.1D gates connected in a flip-flop fashion and a capacitive couplinF;
nct\\ork (CC). The complement of the output is obLlineci at Pin 11 of the modified r-.;A!\D package and is
connected to the output buffer stage which is a !\A:-ID
"nte contained in a slow :\A:\D package. The feed-for\\urd signal is obtained at Pin 12 of the modified NAND
packag-e and it is fed to the input of the following stage.
The i ilput to a counter stage is at Pin 3 of the coupling
circuit (CC'). The output of the buffer stage goes to the
cathode of a coupling diode.

•••

12-1

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35r--

-

R56-1

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743A364GOI

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Z2-2

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C6-2

~

~

R56-2

~ ~

I I r::;l ~

..

r:;:l
L...::....:J

MN-AA

~

--18

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--18

Figure 3 .

.fen

Assembly (Ief. Dwg. 743A364, Sub 13)

~

Figure 4. 4CTJ Schematic IRel. Dwg. 743A364, Sub J3)

____ ~_ CC L

~

DOCUMENT CHANNEL DRIVER

4DEl
GENERAL DESCRIPTION

Output Clllibilities

The -tDE 1 document channel driver card is used as the
data buffer between the I/O interface and the paper tape
punch interface panel. The module contains nine buffer
circuits to hold computer output data and nine current
amplifiers to drive the tape punch solenoids. The cont t'ol circuit on the module synchronizes the transfer of
the nine storeo data bits to the punch solenoids.
The
block dia~ram in Figure 1 shows the application of the
IDE 1 card in relation to its associated eqUipment.

• Interrupt to computer of + 28V dip to OV for a
minimum of 180 jJsec.

CIRCUIT SPECIFICATIONS

• Data to tape punch solenoids via a lA nominal
current which energizes the solenoids.
•

Motor control via a 28V return signal.

po •• r Rlllliremen.s
The tDE) card receives power from the + 28Vdc, 7A
power supply in the punch interface panel.

Input Req uirements

CARD EDGE MNEMONIC BREAKDOWN
• Data ('utput from I/O interface; a logIC "zero"
of 1. 1 V maximum, and a logic "one" of -1. OV minimum.
Channt'i splpct pulse of 11. OV minimum for

•
I

Mnemonic
Bit
Bit
Bit
Bit
Bit

il SP(' ,

•

Punch feedback

trig~er

pulse of H. OV minimum

ppak -tn-peak.

35 Pin ELCO

S
6
7

XIS
X14
X13
X12
XlI

8
9

----------l

I

I

I

CHANNEL
SELECT

TELETVPE
BRPEII PAPER
TAPE PUNCH

I

I

I
I
I

I

DATA
OUTPUT

INTERRUPT
INPUT

-

I
I
I
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I

•

DATA
3DEI
DOCUMENT
CHANNEL
DRIVER

MOTOR CCt-lTROL
PUNCH FEEDBACK

-

-

~

,

BRPEII
INTERFACE
PANEL

r

115Voc,

I

I

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________ -1

FIGURE 1. I.PPLICI. r/ON BLOCK Oll.GRI.M

13-1

Mnemonic

35 Pin ELCO

Bit 10
Bit 11
Bit 12
Bit 13
TRIG.
TRIG. RTN.
INT.
INT. RTN.
MOTOR ON
+28V
28V RTN

XI0
X9
X8
X7
X34
X32
X17
X18
X35
X6
X20

A second function of this circuit i8 to prevent data loss
by ignoring "trigger input" pulses until the tape punch
motor is up to approximately 75 percent speed. Since
the minimum voltage Input to saturate transistor T24-12
is 3. OV. and the voltage amplitude of the "trigger Input"
is dependant on the tape motor speed. the circuit acts as
a voltage tachometer whose output is zero below 75 percent motor speed and full current above 75 percent
motor speed.

r-----.-----~----~----~~~----+2ev
0-16
TO eASE
OF T24·11

For descriptive purposes the schematic has been divided into 3 circuits which are shown in Figures 2, 3 and
4. The complete schematic (dwg. 845A331, sh. 8) is
included as part of this document.
The ci rcuit in Figure 2 contains a pulse shaping network
and one memory element. Transistor T24-12 and its
base circuitry is the pulse shaping network (network 1)
while SCR 81-10, with its gate and cathode circuitry,
make up the memory cell. The input to network 1 is
the feedback pulse from the tape punch magnetic pickup
coil; the output is a current pulse from the collector of
transistor T24-12. The inputs to the memory cell are:
the current pulse output of network 1. SCR SI-9' s gate
drivE!, and transistor T7 -I' s base drive. The memory
cell output is SCR SI-10' s anode current.

TO
SOLENOID

DRIVER

MOTOR ON

CONTROl

The quiescent conditions of the circuit in Figure 2 are:
1. SCR SI-9 and SCR SI-10 are in the non-conducting mode.

2.

Transistor T7-1 is saturated.

The sequence of events for activating this circuit are:
1. Computer output data sets SCR SI-9 by applying gate drive.

2. "Trigger Input" arrives and sets SCR 51-10 by
applying gate drive through transistor T24-12.
3. Transistor T7-1 is switched from saturation
to cut off by depriving T7 -1 of base drive.
4. SCR SI-9 and 5CR SI-10 are switched off by
interruption of their current path to ground (T7 -1 is
cu: off for 180 ~sec).
During periods when the circuit is not cycled by computer output data, it will ignore incom ing "trigger input" pulses.

FIGURE 2. PULSE SHAPING NETWORK .I , MEMORY CELL

Figure 3 shows a unijunction tranSistor timing circuit
used in a time delay configuration. The input to this
circuit is current through resistors R66-14 and RI9-24;
the output is a ground potential on transistor T5-1' s
collector for approximately 180 ~sec.
The quiescent conditions of this circuit are:
1.

Transistor T24-11 is cut off.

2.

UniJunction transistor S2-1 is non-conducting.

3. Transistor T5-1 is cut off.
The sequence of events for activating this circuit are:
1. Transistor T24-11 is switched from cut off to
saturation by base drive current in resistors R66-14
and RI9-24.

13-2

:l. After a time delay of 4.5 msec, unijunction
ransistor S2-1 saturates for approximately 180 101 sec ,
thus biasing transistor T5-1 into conduction for the
same time period.

The quiescent conditions of this circuit are:

l

3. Transistor T24-11 is deprived of its base drive
and is cut off.
4. The delay time of 4.5 msec between the input
and output is controlled by the RC time constant of
capacitor C:12-1. resistor R66-12 and potentiometer
:'1112-1. Resistor &10-1. resistor R27-1 and diode
D-14 Insure that all time delays between input and
()utput are of equal value. Resistors R52-1 and R12-1
prm'ide the correct impedance for the 180 IoIsec interl'up1 input sIgnal to the computer. R82 provides a path
for the leakage current of T24 during cutoff.

1.

Transistor T24-10 is saturated.

2.

Transistor T7 -1 is saturated.

3.

SCR SI-1 is non-conducting.

4.

Transistor T24-1 is cut off.

The sequence of events for activating this circuit arc'
1.

Computer output data sets SCR S1-1.

2.

Transistor T24-10 is cut off.

3. Transistor T24-1 is saturated and pulls current
through the tape punch solenoids.
4. Transistor T7-1 is cut off interrupting the current path to reset SCR SI-1 and cut off the current to the
punch solenoids.

_-_-+28V

1>-21

+28V
-10

-

1>-01
I
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FIGURE 3. UNIJUNCT/ON TIMINING CIRCUIT

The circuit in Figure 4 consists of three current switches and a data bl.ffer. The circuit holds computer output data, current amplifies it and outputs this data to
the tape punch solenoids. Inputs are: a positive 28V
on the anode of diode D-21, a ground potential on the
anode of diode D-IO. and an open circuit across terminals H9 and Ll accompanied by an 11.0V, 4.0 IoIsec
pulse across terminals L2 and H3.

FIGURE 4. CURRENT SWITCHES & DJ. TA BUFFER

•••

13-3

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M12-1
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FIGURE 6 . .jDEI SCHEMATIC (REF. DWG. BJ5A33I, SUB 31

,

j

~:;
~~

IPL4/1PL5 - PHASE LOCKED OSCILLATOR
GENERAL DESCRIPTION
The phasc lockcd oscillator card is used in the analog
input subsystem. Its purpose is to provide a stable 120
c~'cle square wave output which is locked in phase with
the 60 cycle power line frequency. When energized. the
phase locked osc illator attains a stable frequency in
about 1 min. and fo1l0ws long term line frequency variations of 5K to 1i2 liz (4R to i>~ Ill. for IPL5). The IPL4
card if; used for 60 Hz linc frcquency. and the I PL5
for 50 Hz. An application hlock diagram is shown in
Fip,urc 1.

These circuit elements are interconnected in a feedback configuration which attempts to maintain the output in a fixed frequency and phase relationship with the
60 Hz input.

I

I
I

I POWER
IFREQ
I INPUT

IPL4
I--_ _.... (AC MODULE)
PHASE LOCKED
120 CYCLEI
OSCILLATOR
SQUARE
~____________--JWAVE
II ANALOG
OUTPUT
INPUT
I INTERFACES

I
I

I

POWER I
SUPPLYI

FIGURE 2. PHASE LOCKED OSCILLA TOR BLOCK DIAGRAM

The operation of the circuit clements is described in
the following

UniJunction T,anslltor Olclllato' and Bina" Scalers

FIGURE I, APPLICA TlON BLOCK DIAGRAM

The circuit diagram of thp oscillator and scaler cin'uit
is shown in FJgure a.

CIRCUIT SPECIFICATIONS

The oscillator circuit uses a unijunction transistor oscillator. The output frequencl' is dependent on the cont rol input voltage, An adjustment is p rnvided (potentiometer l\1l3-2) for initial calibration nfthc osci!iatl)f to
240 Hz. (At control input voltage of 7. '>V. )

Input Requirements
Thc power frequency input requIres a 6. 3V, ' 15(;;
sine wavc ac volta~(' input.

Output Capabilities

The 240 Hz oscillator output is scalcd bv a binarv
scaler which basicallv is a binan' counter stage (flipflop ci rcuit with capac itive input coupling). The output of this scaler is a 120 Hz squa r(' wave signal which
is used in the analo~ input s\'sl<-m for timing.

The 120 Hz square wave output provides zero volts
(PSe) for the negative portion of the pulse and approximately + 15 V for the positive portion of the pulse.
The length of the positive portlon is equal to the negative portion. The output frequencv is phase locked
with the power line frequenc,V input.

The complement of the output is used to trigger th('
second binary scaler which further reduces the frequency to 60 Hz. This signal is used as a feedback
signal to the frequency equa litv and phase detectors.

Power Requirements
Power input is

t

26 V.

+

15r; dc, ;)7 rnA max.

The circuits of the two binary scalers are somewhat
different, since the first is triggered by the positive
going pulse of the oscillator, while the second is triggered by the negative going transistion of the first
scaier.

CIRCUIT DESCRIPTION
The phase locked oscillator circuit can be separated
into the functional elements as shown in Figure 2.

14-1

+26V

60 Hz
SQUARE
WAVE
OUTPUT

120 Hz
SQUARE
WAVE
OUTPUT

+15V
R15-1

,.,

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R14-1

~~Z4-1

C:~

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C4 5
-

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PSC

FIGURE 3. OSCILLATOR AND BINARY SCALERS CIRCUIT

PhlSe and FrequencJ EqualilJ D.tectors
The circuit diagram of these circuits is sh()\\n in Figure
-1.

+I~V

r--------

FftfDLVCY EOUAUT '(

PHASE OfT£C1'OII':
r---------,

"38-1

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01-~ I

R30-2

R30-1

030·'

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T.~O~-+~~4_------------~~~~
L
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"'26-1

C9-1

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R)(H!!I

H,

60

HI
SQUARE WAII(

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f"MlM OSCILL.ATQA

(LINE F'JlEQl.t:.NCY)

These two squa re \\':1 VPS a re used b\' both the phase and
Ihe frequenc\, ('a:: ,..,0a:: Na::
a:: a:: '"

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ON CARD PL5. R35-4 IS R84-I,
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FIGURE 6.

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IPL4 IPLS ASSEMBLY (REF. OWG. 743A333. SUB 14)

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711·Z ifRic A I'oII4TCJ- - - - -

-.t--------'
3SB MODULE

The data input from the counter requires diode-coupled
logic-level signal, "zero" (0' PSC) for unselected and
"one" (= transistor is blocked) for selected bits.

FIGURE 2. ONE INPUT BUFFER CIRCUIT

17-1

I

The circuit operates in the following way. When the
transistor represenUngthe output buffer stage of the
counter is blocked, diode D7-l is reversed biased.
Most of the primary pulse energy, supplied by the
channel half-select ct rcuit (;;;N), (;flN;) is transferred to the secondary winding of the transformer
and a pulse is provided to the I/o interface (IDOO).
When the counter output transistor is saturated, diode
D7-l is grounded (to counter ground) and the tertiary
winding of the transformer is short-circuited. Most
of the primary pulse energy is now transferred to the
tertiary circuit and dissipated in the winding resistance,
diode D7 -I, and the counter output transistor. The
voltage appearing across the secondary winding is not
sufficient to provide enough energy to be detected by
the I/o interface. Resistor R85-1 proVides current
limiting and diode D7-11 clamps any inductive flyback
voltage.

511" Driver
The span selection conSists of seven identical circuits.
Each of these circuits consists of an SCR with a zener
diode threshold in the gate circuit and a three winding
trigger transformer. The circuit diagram of one bit
of the span driver is shown in Figure 3.

*

+v---rr-l

1/0

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HlnUI

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11111-1

CHANN[L

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I PIIIIl
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I __4
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It can be seen that when a pulse (channel half-select

fl; (n) ; and ;;,; (n) ) appears across the primary winding (3-4) the logic level of the input line will determine
the voltage on the secondary (5-6).
With the input a logical "one", the secondary (5-6) will
have a voltage induced in it which triggers 81-1 and
drives its output to a logical "zero". This occurs because the + 26 V tied to R53-1 will conduct through the
power 8upply switch to PSC. With the input a logical
"zero", no voltage will be induced in the secondary,
the SCR will not conduct and therefore the output w1ll
remain a logical "one".
The zener diode in the gate circuit is needed since the
tertiary winding is never completely short circuited.
Losses in diode drop and tranSistor saturation drop account for a small pulse across the secondary winding
when the input is a logical "zero". When the input is a
logical "one" and the particular channel is selected, the
SCR's will be triggered in response to the half-select
pulse. The SCR will remain in the conducting state until the power supply switch turns it off.
The output of the span driver is used to energize the
span relays in the voltage-to-frequency converter.

R.... Trlllir

.. ~D7-1

J~'I-I

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.IN VI'"'LAY

L.--f

+MV

000

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a logical "one", diode D7-l1s reversed biased, which
open circuits the tertiary Winding. If the input is a
logical "zero", D7-lis grounded which shorts out the
tertiary winding.

~

,

....

Bit 8 (8D8) of the I/o output data is used to generate the
read trigger signal. This is accomplished with the circuit shown in Figure 4.
MAO

(110 OUTPUT DATAl

,I

INPUT

C4-1;::"

T"IGG(R

,

r--------eOit

___ .J

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I

sse
POIIDt

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klH Cl. .... ~
1IOQUI.f)
I'tC

It2I-I
D7-2!1

04-11

00(n)e

I
I

FIGURE J_ ONE BIT OF SPAN DRIVER CIRCUIT

The operation of the circuit is identical to that of a
channel driver circuit. Initially the output transistor
of the power supply switch is saturated so that if a
positive trigger pulse is applied between the gate and
the cathode of 81-1. the 8CR will conduct. The gate
circuit consists of zener diode Zl-1 in series with the
secondary winding (5-6) of the trigger transformer.
The tertiary winding (1-2) of the trigger transformer
is connected through diode D7 -1. When the output is

I

I
I
CHANNEL
HALF

SELECT

I
I
I
I
I

~ee(n)1

1121-1

r----I
I
I

4

2

•
•
I
I ____________
3
L
J51

-------------------~
FIGURE 4. RUD TRIGGER CIRCUIT

17-2

Like the span driver circuit, a pulse will be generated
in the secondary winding of the transformer (5-6) by the
channel half-select pulse if the input is a logical "one".
This pulse will saturate the base to emitter junction of
transistor T5-1 and thus, the READ-TRIGGER output
will be grounded for approx. the duration of the channel
half-select pulse (4I-1s).
The zener diode threshold serves the same purpose as
described in the span driver description.
Capacitor C4-11 and resistor R26-1 are needed for
filtering out noise which may propagate due to the
zener capacitance.

Assume that transistor T6-2 is conducting. Point 1 is
grounded and no base drive is provided to transistor
T6-1. But as transistor T6-1 is blocked, base drive is
provided to transistor T6-2 through R25-2, Dl-8, Dl-6,
and DI-5. Also + 26 V is provided to the gain relay
through R25-~ and DI-9. The 50mV range is selected.
If a channel half-select pulse now appears on 000 (n)
and 0t1 (n) 0 and bit 12 (0 D12) is a logical "one", a
positive pulse will appear on the secondary winding
(5-6) of transformer Xl-8 which will turn on transistor
T6-1, which in turn will cause T6-2 to be blocked. In
this case, no voltage will be provided to the gain relay
output. The 5V range is selected.

Gain Select
Bits 12 and 13 of the I/o output data (0D12 and 0D13)
are used for selection of gain of the voltage to frequency
converter. For this purpose, the ci rcuit on the 3SB
module consists of two, transistor-diode circuits connected in a flip-flop configuration, coupled to two 3winding transformers. The circuit diagram is shown
in Figure 5.

INPUT
DATA

The flip-flop will change its state again Similarly if,
on the next half-select pulse, bit 13 (0DI3) is a logical
"one".
The flip-flop will not change its state if both bit 12 and
bit 13 are logical "zeros".

***
INPUT
DATA

r----- ----------------------- ----,
0013

00(n)01

(110 OUTPUT DATA)

0012

04-1

I

I

+26V

+Z6V

R25-1

R25-2

1
I

R39-!

07-9

I
I
1

07-8

CD

I
CHANNELl
HALF
I
SELECT

01-8

01-7

I

I

I
I

I
I

TO GAIN
'--_____+-_.... RELAy

I

1
000(n)1L ______________________________

~~

FIGURE 5.

GAIN SELECT CIRCUIT

17-3

+5V
RANGE

---,
e)_i....
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-t
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R26-1

C"'-,~}

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'r::l

XI··"
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L_._.J !....
.
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l"-'4!BF1

143.6358- 3S8

FIGURE 5. UBI ~SSEMBLY (REF. DWG. 74J~358. SUB 7)

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T~~'

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n~ J]J
Tg

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g

~ u~~~

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l

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001.1.

---.--~

FIGURE 6. 3SBI SCHEMATIC (REF. Dwe. 7.J3A358, SUB

7)

3511/3512 - SEQUENCE OF EVENTS INTERRUPT CARD
GENERAL DESCRIPTION

OI'P.' CI'I~IIIt1..

The 81 card generates a single interrupt when anyone
of a number of CCI' s change state; either from closed
to open. or open to closed. The card suffix denotes
the following:

Output is to a power supply switch trigger.
The output is clamped at approximately one volt until the
power supply switch is reset.

P.w.r Rillulr.m.n••

Card

The negative side of the 48/I25V power supply should be
connected to the 48/125 RET (X2). The nominal inrush
current/bit is 16.5 rnA for 48V or 21. 2 rnA for I25V.
A minimum of 6V is required on the anode of the silicon
controlled rectifier (XI8). The negative side of the plant
power supply must be connected to P8C.

48V. make or break int.
125V. make or break into

38Il
3812

A block diagram showing a typical application of the 81
card and power supply switches is shown in Figure 1.

CIRCUIT SPECIFICATIONS
CIRCUIT DESCRIPTION
Inpu' R'lIulr.m.n',
Inputs must take the form of a switched dc voltage from
relay contacts or switches. The presence of a voltage
produces a "one" input while zero volts produces a
"zero" input.

Figure 2 illustrates one bit of the 14 bits on the 3SIl and
3812 cards.
Input resistance for each card is:

The nominal magnitude of the input voltage level and inrush resistance of each bit are:
Module
Type

Nominal
Voltage

Inrush
Resistance/bit

48
125

2.9k
5.9k

38Il
3812

(+)

/

M41 Coil Res.

1. 5k
4.5k

1. 425k
1. 425k

When the contacts for bit (n) close or open. the relay
coil (M41) is energized or de-energized respectively.
The coil will not be operated at a frequency greater than
60 Hz. The M41 contacts will momentarily open because

.

DATA

CB
14 POINTS

I

PLANT ~ONTACT
(ONE OF 14)

3811
3812

Ra

T,M
OR

(-)

V-I

PANELS

I

_.

I

PSS(N)T

I

I

~~__1_4_P_~_~_N_TS__~__~~~(~N)~~~~___I_/4__P_S__~
FIGURE 1. APPLICATION BLOCIC DIAGRAM

18-1

I~T

they have "break before make" feature. Therefore the
SCR. 81-1 will be triggered and start conducting. 81-1
wUl be triggered when bit (n) is opened or closed. It
will remain conducting until reset by the power supply
switch card.

+"

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M41-7

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0

10441-5

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0

"41-4

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0

0

"41-3

®

000

3512 MODEL, R63-1 TO 14 ARE REPLACED BY R64 -I TO 14.

FIGURE 3. 3511 13S12 ASSEMBLY (REF. DWG. 743A396, SUB 3)

10441- 2

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ON 3512 MODULE R63-1 THRU 14,
ARE REPLACED BY R64-1 THRU 14.

FIGURE 4. HIIIJSI2 SCHEMATIC (REF. DWG. 743A396, SUB 3)

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2SLI - 735 SELECTRIC INTERFACE MODULE
GENERAL DESCRIPTION

Power R'lIuir.ments

The 2SLI printed circuit module serves as a buffer between the Central Processing Unit. and the interface
package of the 735 Selectric typewriter. It contains a
data buffer register and control circuitry. An application block diagram is shown in Figure 1.

2SLI module receives + 28V through terminal Xl.

CIRCUIT SPECIFICATIONS

Figure 2 shows one bit ofthe 14-Bit data buffer register.
The Selectric magnet is energized when 4!-lsec halfselect pulse unloads the data line through the pulse
transformer into the associated SCR. When the SCR
conducts. the magnet is ene rgized. and the 735 Selectric cycles. This causes the reset contact in the
Selectric to close, thus generating a RESET signal. The
RESET signal controls the Power Supply Switch located
on the SL card. When open. the Power Supply Switch
causes the SCR to block and the Selectric magnets to be
de-energized.

Siena I Requirements
I/O Interface
• Data: logic "zero" - 1. IV maximum; logic
"onE" - 4. OV minimum.
•

I/O Selection: 4.0 /-Isee pulse. 11V minimum.

• Interrupt Input: nominally 28V tied to a lk pull
up resistor.

+

Oat, Buff.r Reelster

The outputs of the SCR' s which drive the magnets are
filtered to prevent rate-of-rise firing of the SCR' s. The
filter is also used to drop the dc voltage to the magnets
from 2HVdc to 24 Vdc (their normal operating voltage).

735 Interface Package
• Data: zero volts (magnet energized).
(magnet de-energized).

CIRCUIT DESCRIPTION

28V

Power Supply Switch Control and Interrupt Circuit

• Reset: contact closure. +28V causes reset to
occur.

Refer to Figure :l for the follOWing description.

----------,
CHANNEL
HALF
SELECT

IBM 735
SELECTRIC

(14 BIT)

DATA
OUTPUT

2SLI
PRINTED
CIRCUIT
BOARD

~ I_NT_j_:_I~_U_P_T ~14~r-______~~__________~
__

____

__

CP~

___

J
FIGURE I. APPLICA TlOH BLOCK DIAGRAM

19-1

DATA
RESET

INTERFACE
PACKAGE

DATA COM

BUS

INT TO

CPU
NOTE:
I. THE RESISTORS INDICATED
ARE REMOVED FOR BITS
Z AND 5 THRU 13.

735

CABLE

Sfl.ECTRIC

RESET
POWER
SUPPLY '------~~..I.-~I»---4II---~
SWITCH
I
CONTACT
I

I
I

~--------------~~---"»---O ~-~
I

28 VOLT
DC SUPPLY

FIGURE 2. ONE lJlT OF DA U lJUFFER REGISTER

TO SCR

INT

REGISTER
+28'1
BUS

TO CPU

--------~>>-~~~~---------_1~~~~-----------~

CIO-I
~PS~C~

____~)~______~________4-____~__________~~______-+____~

FIGURE 3. POWER SUPPLY SWITCH CONTROL AND INTERRUPT CIRCUIT

Transistor T9-1 is the controlling transistor in the
Power Supply Switch which delivers current to the
printer magnets if their SCR' s are SWitched on. When
this transistor blocks. the SCR' s are switched off.
and the magnets are de-energized.
In the quiescent state. transistor T9-1 is conducting
and transistor TS-l is normally blocked. The base
of T5-1 is controlled by the completion contacts in
the printer. Normally these contacts are open, however, when the Selectric cycles. these contacts close
and cause transistor T5-1 to conduct. The transistor

conducts as long as the completion contact in the Selectric is closed. With TS-l conducting, T6-1 blocks. thus
blocking T9-l. This switches off all the SCR's which
were on, thereby clearing the 14-Bit register.
Transistor T5-1 blocks when the completion contacts
open. The output of transistor T5-1 is used to interrupt the computer to ask for another character of output. The interrupt occurs when this output has a positive going tranSition.

•••
19-2

8

2SLI

~

-1 R52-2

-t R21-1 r

r

-iR21-2

U

35

--i

R26- I

-f

x

~
~

a::

I

RII-12

.....

r

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J- -i
J- -t
I- -i

RII-13

r

RII-IIA r

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~ -4RII-IIB
a:: --i RII-IIC

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-4 RII-148

-t

RII-14A r

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-f RII-II IRI1-10B I-i RII-IOA }-tRIl-IOC I- -f RII-IO ~
-i RII-SA I- -f RII-B
r
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-I----.tRII-IA _

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FIGURE 4. 2SL I ASSEMBLY (REF. DWG. 845A335 • SUB J}

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MODEL 35 TELETYPE INPUT MODULE

2TNI
GENERAL DESCRIPTION

Model 35 Interface

The 2TN1 module is used for control of data transfer
between the Model 35 Teletype equipment and the I/o
interface. This card contains data input pulse transformers and control circuitry. An application block
diagram is shown in Figure 1.

• Mercury Relay Contact used to control tape
reader ON/OFF.
•

Mercury Relay used to monitor input line cur-

rent.

Power Requirements

--------,

The 2TN1 module receives power from the + 26V
interface power supply.

INPUT LOAD

4TOI

I

I
I
I
I
I

CIRCUIT DESCRIPTION

S£QlENC[R
OUTP\JTS

2TNI

I/o

2TNI card contains the following items:
• The 8 input pulse transformers whose outputs
a re tied to the I/o inte rface data input register. The
transformer inputs are tied to the 8-bit SCR register on
the TO card.

3TSI

'-..---'~

TO TAPE
R£A~R

m

MODEL
INTfRFA(E

• Line relay used for monitoring serial data from
Model :35.

~,

CQNTR()L

• "Input load" signal used for setting SCR' sin
data register, (,nOl).

FIGURE'. APPLICA TlON BLOCK DIAGRAM

CIRCUIT SPECIFICATIONS
Input Requirements
read

•

Tape reader ON/OFF control relay.

•

infJut interrupt circuit requesting input data be

by I/o interface.

I/o Interface
• I/o Selection -

• "Acknowledge" pulse transformer indicating
Interface has taken previous character.

.t. () IAsec pulse, llV mini-

I/o

mum.
•

Data Input -

"one" - 6V minimum, ..1. 0 /lsec

pulse.
• Interrupt Input - Interrupt signal is nominally
26V tied to a lk pull up resistor.

Figure 2 shows one of the eight pulse transformers used
for reading data from the 4T01 SCR data register to the
I/o interface. If the SCR is conducting, winding 1-2 will
appear as a short circuit and a small voltage will result
across winding 5-6 when the 4.0 /lsec channel half-select pulse occurs, this is a logic "zero" to the I/o interface. However, if the SCR is blocked. D1 will be blocked

4T01 Signals
CHANNEL
HALF SELECT

• Data - Logic "zero" - 1. 1 V maximum,
Logic "one" - 4. OV minimum.
•

Input Load 200 /lsec pulse will set selected SCR.

3TSl Signals
SCR DATA
REGISTER IN
4TOI MODULE

• Sequencer outputs - zero volts implies logic
"zero", positive voltage implies logic "one".
•

Control signals - covered in circuit descrip-

tion.

20-1

FIGURE 2.

PULSE TRANSFORMER CIRCUIT

when channel half-select pulse occurs and a voltage will
appear across winding 5-6 and D2 will conduct. This is
a logic "one" to the I/o interface.

START
INPUT

,.., r-' ,..---

CLOS(

I
I

AELAY

CONTACT

OPEN

Figure 3 shows the input mode selection. When the
line relay M9-1 is de-energized as a result of a
"start" impulse (open line) from the Model 35, SCR
51-1 is set. The relay contacts open and the gate
of the SCR is pulsed, turning it on. When 51-1
turns on. transistor T8-1 conducts and generates
signals "u" and "Y" which indicate input mode. The
signals are + 26V.
Figure ~ shows the timing associated with setting the
input SCR (SI-I) as a result of "start". Transistor
T5-2 remains blocked since "N" is ground at all times
other than step 8 of the sequencp (STOP). When step 8
of the sequence occurs "N" goes positive. T5-2 conducts. This shunts the 51-1 holding current and the
5CR blocks. T8-1 rpmains on. however. since T5-2
provides th(' basI' eu r rent to TH-\. Signal pulse "R"
occurs about 1. S ms('c after "N" and causes TS-2 to
block. This genprates the interrupt pOSitive transition.
Also TH-I will block and "u" and "Y" siJ.~nals arc inhibited. The same sequence of events will occur when
the next "start" occurs.

51-1

LINE

RELAY
M9-1

r-----------------~--~~--~~}~
4.32K
R

+26V

,.-~~~~------.IN

INTERRUPT

I
I

I
I

I
I

I
I

'3'4',','7

CONDUCT

L

TI-I

aocICID

"Nil
SIGNAL

+v
STEP

ov
~-2

INT
INPUT

al
9

+2t5V

ov
CONDUCT

51-1
, SCR

IILOCK
+11
"II"

...j ~IS"'''C
---------------------------,=tJ=~~MC

all
FIGURE 4. CIRCUIT TIMING CHART

The input load signal generation is shown in Figure 5.
Input load is the output of transistor T5-5 and is used to
set the selected SCR on the 4TOI card. The input load
timing is related to PI and P2 pulse inputs as shown in
Figure 6. Capacitor C23-1 is held discharged by UJT
inhibit when the sequencer is not running. When the sequencer is reset and UJT goes positive. C23-1 will be
allowed to charge through R28-5 and adjustable potentiometer M17-1. Either PI or P2 will also discharge
C23-1. The charging of C23-1 is shown in Figure 6.
Note that PI occurs first and discharges C23-1, through
TS-3. then C23-1 is allowed to charge. When it reaches
the required voltage, 52-1 will fire and T5-4 will turn
on. This time is adjusted to 6.:l msec after PI or P2
pulses. At P2 time, C23-1 will again be discharged.
When T5-4 turns on, T5-5 blocks since its base current
is shunted away by T5-4. The collector of T5-5 will be
allowed to go positive if the M-9 mcrcury contact is
opened. If it is closed. then T5-5 will be held at ground
and the input load signal will be suppressed.
Figure 7 shows the control of the Tape Reader Relay
Contact and the acknowledge Signal from the I/o interface as a result of an input interrupt.
Relay M3-I is a bistable relay which controls the tape
reader advance in the Model 35 equipment. Transistor
T5-I will reset or open the tape reader contact while
transistor TS-l is used to set the relay contact closed.

FIGURE J. INPUT MODE SELECTION CIRCUIT

When an input is done on the selected input channel,

20-2

-< __
X34

~

X35

-<

M17-1
R28-5

r·

P2

C23-1
M

07-40

UJT INHIBIT

-<

07-47

R16-2

R28-3

~<--~~'---~~M"~--------------

X4

-<

"

07-45

X30

-<

R16-1

-I

07-46
X29

R21-9

~-4~~~

R12-2

__

35.7

INPUT LOAD
+26V

06-4

-<3:J
XI

LINE P

-<

R28-4
R12-3

R52-3

(+1

X2
07-48

SET INPUT

MODE SCR

FIGURE 5. INPUT LOAD SIGNAL GENERA TlON
transformer XI-9 is pulsed with the 4.0 ).lsec pulse.
Since the winding 1-2 is an open circuit. then a positive
pulse will be generated fl'om winding 5-/i. This pulse
will tum on Tfi-l and the tape reader contact will be
closed. The tape reader will advance and a character
will be read. T6-1 conducting shunts base current
away from T6-2 and it blocks. This causes T6-1 to be
held on via R26-12 and D7-26.
The output of T6-2 is si~al "Q" which. when it goes
positive, will cause the register reset to occur and Signal "R" is generated. Therefore. about 100 J.lsec
after inputting the data. the register is cleared. Also.
signal "R" is generated about 1.5 msec after the input
command. Si~al "R" will shullt the base current of
T6-1 and cause it tn block. When T6-1 blocks. TG-2
turns on and holds T6-1 off. Signal "Q" goes to ground.

I-

IS. ISms ----+j

---InL..__

PI----.n'----_ _

---Jn. . ____n. . __

19.09ms
P2 _ _ _

1

6 3ms
.

I-

l-

INPUT _ _ _~nL.._~nL.._~nL.._--,fLLDAD

C23-1

FiGURE 6.

iNPUT LOAD TiMiNG

2TMI Potentiometer Adjustment For Input Load Signal
The tape contact is now closed and a new character may
be read beginning with Start which enables the sequencer.
At step D· C of the sequence. the tape reade r contact is
reset and the reader will stop. When the data is read,
the contact is again closed and the data register
cleared.

1. PI and P2 pulses from TS Card should be connected to TN Card on pins X34 and X35.

2. Connect scope to TN Card at junction of C2:J-l
and M17-1 and adjust potentiometer to obtain 6.3 msec
ramp as shown in Figure 6.

* * ..
20-3

RD ON

......----.

-<~~-

R12-1

+28V
A

M3-1

NC

RO ON R

~~~------~------~

(+ )

+26V

( -)

06-1

R26-1
R~2-1

R52-2

06-3

+26V
R26-4

07-~

CHAN
SELECT
INPUT

+26V
R26-12

07-28
07-27
~~~---.~~----~--~~~~~--~~

-<~~

TO T5-2
INTERRUPT
INPUT TRANSISTOR

FIGURE 7. RELAY CONUCT CONTROL CIRCUIT

20-4

.,

I

.,

35

-

'"

"

...,I

~ ~'r~-r
~~Q~~X~~~
66
a:a:O
00

l.-r---II

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-{

XII

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';'

I

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H

f-..J!

R53-2

-i

-l R26-12

!L

R26-6

f-

o
I

-i
I

I

N

I

...,

en

,...

I

:E

u

N

a:

00

2TNI

I

743A339 (2TN)

t-

~

~

--{lQEffi-

R26-7

R12-1
C6-1

a:
N

f-

I--

-

-~

RESET

~ir

Wz
CI:WCI:
zw

CI:

W

~
Vt- t
CI:~

z

->

~CI:

g

~:":0

~

U

W

DATA

~ ~u

=>

t iii!
3TSI

FIGURE 1

APPLICA TlON BLOCK DIAGRAM

21-1

2TNI

CIRCUIT DISCRIPTIOI
The "TOI card contalna the follow",,:
• The 8-bit data relilter which .tore. the 8 bitl
of data either AI output from the computer or a. input
from the Model 35 equipment.
• Pul.e tranaformer. which are connected to the
OUtput Data rep.ter.
• Sequencer decod1nl for the input and output of
.erial data.
• Output "mode" SCR. signal M. which indicate.
output mode of operation.
• Motor on/off bi.table. which control. motor
on/off relay (Signal L).
Figure 2 illustn.tes a typical Data Bit of the 8-bit Buffer
register. This data bit may be set by output from the
I/o interface or by input from the Model 35 equipment.

.et.

ICR wtll be
The SCR aaode i. returned to + 26V
throulh Nli.tor R1. ThiI providel holdiDl( current for
the SCRo
Diode Inputl Aand B lerve to select the SCR d~ring
put. Aand Bare .equencer outputl and act al a lopcal
"AND" I allowinl point "8" to JO politive. Sipl "I" II
the input load lipl and i. normally at Il'ound. If thi •
• 1pl JOB po.illve when A and Bare .elected. then the
SCR 1•• et tbrouib diode D-3.
Diode Inputl A and Bare allo uled to lelect the SCR
duriDl( output. Inputl A and B and diode D-4 act &8 an
"AND" gate
that if the SCR Is let. point "s" will be
held at + 2V. If the SCR 1. blocked. point "s" will be allowed to go more positive. Diode D-5 il the output of
thil "AND" gate and It Is "ORed" together with the other
7 data bitl to drive the relay driver circuit.

.0

The anode of the SCR is also connected to pulse transformers for inputting data to the I/o interface. If the
SCR is conducting it will appear as a .hort circuit across
winding 1-2. If the SCR i. blocked it wlll appear as an
open circuit across winding 1-2 of the input transformer.
When the input channel is selected and pulsed. a logical
"1" will be stored if the SCR is blocked, and a logical
"0" will be stored if the SCR is conducting.

R'''I Swllel!
The outputs of the 8 SCR's which make up the buffer register are connected through holding resi.tors to a "reset" SWitch. This switch is a transistor which is blocked
as shown in Figure 2. When Tl conducts it will ".hunt"
the SCR holding current since the voltage drop across
the transi.tor to ground is less than the voltage across
the SCR and the 3 series diodes.

FIGURE 2. ONE BIT CIRCUIT OF 8-BIT DA U REGISTER

If Bit!). for example. is a logical "0" from the I/o interface. this will cause terminal 1 of the winding 1-2
to be grounded. Since terminal 2 is tied to ground.
this winding will appear as a short circuit. If Bit 5 is
a logical "1". winding 1-2 will appear to be an open
circuit since the series diode is back bia.ed.

I/o interface selects the channel with a 4.0 J'sec pulse
across winding 3-4 and if winding 1-2 appears as a
short circuit. a small voltage will be generated across
winding 5-6 and the diode. D-2. will not conduct and the
SCR will not be set. H. however. winding 1-2 appears
as an open circuit (logical "1"), then. when the channel
pulse occurs. sufficient voltage will appear acro'l
winding 5-6 so that diode. D-2. will conduct and the

Figure 3 .hows the motor ON/OFF bistable which is
controlled by Bit 13 and Bit O. If Bit 13 is a logical
"one", then a positive pulse will appear across winding
5-6 and the transi.tor T6-1 will be turned on. This
transistor is held on by transistor TS-2 being blocked.
Transistor TS-2 will conduct if Bit 0 is a logic "one".
When this transistor conducts, it shunts the base current to transistor T6-1 and T6-1 wi 11 block. Transistor
T6-2 is held on Since T6-1 has blocked and the base current to T6-2 is no longer shunted.
The output of TS-l, signal L, drives the mercury wetted
motor "ON" relay. This relay is mounted on the TS
card.
Also shown in Figure 3 is the "Output Mode" SCR which
is set each time the channel is addressed. Note that
winding 1-2 is not cOMected, and as such, will appear
as an open circuit when the 4 J'.ec channel pulse occurs,
cauling the SCR to be set. Signal "M" is u.ed to indicate
that the computer has performed an output.

•••
21-2

~

A
X2

BIT 13

::I

......
I
c.n

."

::

II "

~~--------~~~ "



~--CIRCUITS

I

MAGNETIC
PICK-UP
ON PUNCH~_...

.......-<

.,,-~---

X~

TO POWER

SUPPLY SWITCH
ON DE CARD

FIGURE 2.

TYPlC~L

BIT

M~PLIFIER ~ND

•••

22-2

CONTROL CIRCUIT

~

~

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c,.,

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~B

0
0
0
0

@G@

~
~
~
~
06-11

-1
-1
-i
1R~ -1
06-12

06-13

06-14

@G@
@G@

~

C23-2

r
r

C23-3

C23-4

-i

-1
-1
-i

R67-11

r-

C23-5

R52 2 j-

~~

-f

Z2-1

-1

R~
06-i6

-1

_
C23 6

-1

RiJJ=

-1

C23-7

-1R~

-1

C23- 81-

~

-i

C23-9

06-17

06-18

06-19

~

r-

r

lTPl ASSEMBLY (REF . OWG. 743A376. SUB S1

r-

R67-13

~

R67-14

r -1 ~r-

~ R67-15 ~
D.H

-1 R26-1

~
R67-1

l-

~

-f R67-2 t~

-1 R67-3 tR67-4

~

-l R67~5
,

....

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to

a:::

N

a:::

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u-

"-i R67-16 \-

@
N

-

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-i R67-6

t-

-f

t-

-1 R67-/7 t- ~
-i R67-7 l-1 R67-/8 ~ -€3-1 R67-8 I-1 R67-/9 ~ ~

743-'376 -ITP GOI

FIGURE 3.

r -I

R67- 12

!!l
~ w@ ®®T8:~-2 T5_,R~~
06-i5

--l

~

-1 C23-1

R67-9

MODEL 35 TELETYPE CONTROL CARD

3TSI

•

GENERAL DESCRIPTION
The 3TSI module is used as control between the Model
equipment and the -lTOl buffer card. This
C:l rd contains control and sequence ci rcuitry.
An application block diagram is shown in Figure 1.

Model 35 Interface

;;:i Telet~'Pe

...,

I

!NTE"~RUPT

I

MCJT~

DRIVER

to

rNTTRFA.CE

CONTROL

r*

I
I
I
I

5(OUENCER

r*

(»NTAOL

TO I'OW£R

J

CONTACT

R[I-4Y TO

TLIIN MOTOR
ON "-

XI'

--~I¥~------+---~~~>-

v,.

FIGURE 2. 5-STAGE COUHTER CIRCUIT

Figure 5 shows the relay driver circuits which control
relay M9-1. The normaU\' closed contacts a re in series
with the line signal to the Model 35 equipment, If the
signal "K" is allowed to go more positive than the zener
breakdown voltage of Z2-1. then transistor T5-6 will
conduct and the relay will be picked up and the line contact will open. The return path for the emitter of TS-6
is through slow NAND SN-H-S to PSC. This slow NAND
will conduct if TR-t conducts. since TS-t provides base
current to SN-H-S. The input to TS-I is signal "M"
which implies output mode when it is + 26V. Therefore.
only when "M" is + 2V (output mode) will, the relay driver
circuit TS-6 be enabled.
Signal "X" implies output mode when it is a + 26V because TS-I is conducting.

23-2

Heset transistor T5-6 will be pulsed if either "X" or
"U" will go to positive 26V during
the input mode. At the beginning of a data transfer, a
reset puisI' is g(,lle rated , and is used to reset the 5stage counter.

"u" goes positive.

Hela~' 1\19-2 will conduct if signal "L" goes to zero volts.
The normally open contact will close. This contact is
used for turning the Model 3;') motor on and off.

Figur(' 6 shows some additional control and timing required for the Model :15 l'quipment. In the quiescent
s tate the 5-stage counter is stopped in the D· E state so
that signal "1''' is positive. This causes slow NAND
S:\-H-I0 to conduct and tJFT to be zero volts. This
signal ll1hibits the Unijllllction oscillator as mentioned
previously.

--11

~~

n

n

"...__......In
n

______________

n
n

-+26V

12-1

n...___

n

RESETJ
-1 1:"6.0""_
_
_
_
,NPUT LOAD
..I~I-......lL-.....l'---'L
A---,~
~

Signal "R" wi~ he generated (zero volts) each time sequencer step D· E occurs either in the input mode or the
output mode. Transistor T5-1 is driven by unijunction
transistor 52-1. This transistor has two timing circuits associated with it; one for input (X) and one for
input (Y). When D' E occurs the base circuit of S2-1 is
allowed to go positive depending on which RC timing path
is enabled. For the output mode the unijunction 52-1
uses R28-1, M 1 7 -1, and C22-1; for the input mode it is
R30 and C21-1. For output, "R" will conduct for 100
J-Isec about 20 msec after D· E, while for input, this
pulse occurs about 1.5 msec after D· E.

..

f'L.
"

..

"" ........ ' - " " " ' " -

LINE
CONTACT

C21-5
K----------~._--~~IT

A---.J
B---........,
~~_4~-------------w

9---...1

D'---------~
F!53-1

~~--~~--------------------x

MW~t--+f

5-------------~

R26-2

E---------------~

R2&-3

uo-------------~~~~~~~-.--.-~~
~E'ill'i·~~TE l'
STEP" - E A (RESET)
I) - A· R

BIT ((II'TP1:T MODE)

"START"

R28·2

BIT (INPUT MODE)

"START"

I - B ('
~ _ l7:. I)

\ - nr:

; - F '\

:, fi -

7 " -

~

ii

Be

c. D
D· E

9

'.

10
II

II
12

12

10

"STOP"

+26V

,-=1

13

"STOP"

FIGURE 4. INPUT OUTPUT SCAN SEQUENCE

MOTOR
NrT
1" I

ON/OFF

.CONTROL

FIGURE 5. RELAY DRIVER CIRCUIT

The output of 5N-G-:) IS the output interrupt signal and
thls slow :\Al"D circuit is enabled only in the output
mode. i.e., "X" is positive 26V.
The register reset Signal will go to zero volts if either
signal "Q" or 5:"oi-G-10 goes positive. When this happens
T5-;) will conduct and the 5CR register on the 4TOI card
will be reset.

23-3

Refer to Figure 7 which indicates the timing of the control circuitr\' during the output mode. "N" (D· E) is at
a positive voltage in the quiescent state. When an output occurs. the sequencer is reset to step 9 and the UJT
inhibit signal goes positive enabling the sequencer Signal "X" to j:(0 to 26V. When step 8 of sequencer occurs,
unijunction oscillator is inhibited and 5N-G-5 output
goes to zero volts. This resets the "M" SCR; however,

"X" i••till + 28V, .ince SN-G-5 act. to bold in the "X"
tran.i.tor T8-1. Stnce "N" i. permitted to 10 po.itive,
the 20 maec time delay will be enabled, after which the
100l'sec "R" aignal will occur. This signal blocu
SN-G-5, causing "X" (T8-1) to open. Since the Ilow
NAND SN-G-5 blocks. thil polmve transition caule.
the interrupt to the I/o interface. Also while SN-G-S
il conducting. this causes the Register Reset signal
(T5-5).

•

Connector letup - 2 SylvanJa aDd 1 Elco with

p1Da made available.
Ad1ultment of PI and P2 on T8 Card

1. Connect T8 card to Elco and Sylvania connectors.
2. Connect -V to pin Lion Sylvania.
3. Connect + V to pin HI on Sylvania.

The Input mode is similar to the Output mode except that
the selected RC network for S2-1 has a time constant of
1. S msec; I. e •• 1. 5 msec after step 8 occurs. 82-1 will
conduct. causing "R". "R" is now routed to the 2TN1
card which results in an Input interrupt to the I/o interface. When the Input occurs Signal "Q" goes pOSitive and the SCR register is cleared and another "R"
signal is generated. This reseta "Q" to zero volta.

Connect -V to pins 14 and 8 on Elco connector.

4.

5. Connect one chaMel of scope to Elco X23-(Pl).
Connect other channel to Elco X24-(P2).

6.

7. DI8play PI and P2 trace on scop••
+M

04·1

X \OUTOVT 1IlOO( I

lilA·,

04·Z
04·'

9. Sync scope on P2 and adjust other adjacent pot
to obtain PI occurring 9. 1 msec after P2. shown In "A"
of Figure B.

10. Observe output of "F" NAND on TS card to be
9.1 Insec square wave.

STtPI·Di-+V

au. (1IM(1I
D·f-av

8. Adjust one of two adjacent pots to obtain P2
occurring 9. 1 msec after Pl.

ST("·
CLlHtfNT
UM,TI",

11. Observe sequencer outputs "A" through "E" to
be /iure all NANDS are operating.
12. Observe "Reset" and Eleo pin X2S.
+11

•...... 0·[
CN

UJT
I... HlliT

II--_----Jr.t

0

I

2

3 4

e

1

7 • (~

w
0

tV
S~·G-5

(I-m:_l

OV
-21'"

"x"

(OUTPJT
fIIIOOEl

0

~

~:9~1«i
FIGURE 6. COHTROL. AHD TlMIHG CIRCUIT

..

Plflnll"'lter UJ..... llt

~

.

26V to 29V power supply.

+V
0

EqUipment Required
•

L-______________J.

CIIIICU,T

IIEIIISTDI
IIl.T
(T!!-!!)

• Dual beam scope.

w
r:N

u

FIGURE 7. OUTPUT MODE TIMIHG CHART

23-4

a.~

20 msec Delay (ramp) on TS Card

•.• "'. ------i

~

_ _ _ _...Jn"",__ p,
1.01---1
___
"" _____
I ____~n~____________ 'n

J1,-:;;;;::==+:=,;:o;~nL.1--1.09

...

___
I ___
"'_'__~n~

",..

1.

Remove connection XI:! to -V.

2.

Connect X13. X14. X26. and X34 to XIS (-V).

3. Connect scope to junction of C22-1 and M17-1
and trigger scope positive.
4. Adjust lowest pot (M17-1) on TS card for 20
msec ramp shown in "B" of Figure S.
o

***
"e"

FIGURE B. POTENTIOMETER ADJUSTMEHT T/MIHG CHART

23-5

-

I

CD

10

Ir

H

-----'18

x

~~

C22-2
C22-1
L
M9-2

M9-1

;C 0000
--tI

N

U

N

U

-----'18

MI7 - I
7414342 3TS

FIGURE 9. 3TH ASSEMBLY (REF. DWG. 743A342, SUB 14)

p,
---~--------

R(sET

~DI'"
·111l.~
oI-

~

K

~

~'J

uJT

0' "

1>,10"£ ".:..
I PIN

v"")

2.

'o~

"'ll
~~c.

TO
<

~

SLo....J N ....... OS
(ll)

A~~
~lO""
"'lANe., ~Nl To .1",
£A.l(Ti
.,.j"'(O ':TT .... Q._\~I'_
PI/\I'.J

.,

»

.flo. ...

FIGURE 10_ 3TS1 SCHEMATIC (REF. DWG. 741.4342. SUB 14)

I

1ruo4

V\I\r f2IIrI
~

01-14

lWD4 - WORD DRIVER MODULE
GENERAL DESCRIPTION

CIRCUIT DESCRIPTION

This module IS used to pn)\'lde:! II; bit output to the
I/O subsystem. Each hit ()f lh£' ()utput is designated
:IS a "\\',,~d". Th" "word" outputs :In' used in the I/O
fillilSlst<'Ill(ll f"I'1lI a sdect 11m Ill:!t rix with the channel
drin?l'(s). An applIeatioll block dla~I'am IS sho\\ll in
Fi~un' 1.

Each "wonl" of the word driver circuit consists of an
SCR with a zener diode threshold In the gate cirCUit
and a tW()~\\'Ill(hng gatl' trigger transformer. Each
card contains Hi identical SCR circuits.

Figure 2 shows thc' schematic diagram of a word SC R
and assOCiated circuitry. Dotted lines show the connection to the power supply switch.
ROW
HALF
SELECT

COLUMN
HALF
SELECT

(n)0"''''

12 LINES

B LlNE.S

WORD
DRIVER
IWD4

+IOV WHEN USED
IN ANALOG SYSTEM_
+26V WHEN USE~
ON 1/0 DRIVER PANEL

r------------I
I
I

f-16

OUTPUTS

I

~'Sl-I

-c.
l""

I
I

]

I

1
1
1

jSCR LATCHING
CURRENT PATH

--l

07

I
I
I

I
I
I

I

±C4

L-_ _ _ _ _~_~.----_+---..!...-WDln)

I

POWER
SUPPLY
SWITCH

I

R221

I

~- -

----- -

el(n)0el

I

-

:;"
... ,

/

-

-

-

R22-17

-:-

Co~NECHD

ONLY
IF USED AS A 10V
WORD DRIVER

POWER
ri----SUPPLY

\

FIGURE 1. APPLICATION BLOCK DIAGRAM

OUTPUT

I

/11

'I' ....

SWITCH

I

IPse

CIRCUIT SPECIFICATIONS
Input Requirements

FIGURE 2, WORD SCR SCHEMA TIC

T1H' h,lir~seIeI'i IIlPllt (11) tlIlrl :iIld rl (n)
mlT1ll11UIl1 II \', IlL; I'lilse.

i\f\ fl'4ul[,('

Initially. thl' ()utput transistor of the p<>w['r suppiv
switch is satuI'ated so that if a positive pulse appears betwecll lh(' h~te and the cathode of the SC R
(Sl-I), the SCR ean conduct, since it has sufficient
latching eurr('nt through resistor R22-1 (or R~~~ 1
and R22-17 parallplll'd if used as a 10 V driver) and
the pow['r suppl\' SWitch.

,I

Output Capabilities
Th,' "II (Ii'll

(lutput \\'Il(Il) jll'ol'ld"s :J "Olll'" tOI':J Sl'l~
,11lt!:1 ' /('1',," fllr ullsel('ctcd \\'o]'(ls.

('('kive traming. cond\lcted by professional Westinghouse computer instructors, natur:Llly ennches and glve:-; added meaning to the printed text. The computer maintenance man,
lldlowmg Instruction that includes solving a variety of computer" malfunctions" thoughtfully
plannpd by his instructor to test his new skill and knowledge, will find the book helpful for refresher study or review.

(Such r~Vlew, when the student is home again and responsible for the smooth operation of the
P-50 1:-; Important for a reason that one might overlook: The P-50 is designed for great rellahi Ii ty. and malfunctions can be expected rarely. The maintenance man, accordingly. could
easIly get "rusty" on details of computer construction and operation; how can a man keep "up"
un maintenance procedures if he is not called upon for months on end, to concern himself with
the computer's operation 7)

:\1, \ 1:-'" '1',\ I \. ,\I~I LI TY

Hecallse thiS book is likely to be used as a maintenance reference, an added word on the subJed of mamtalnability is appropriate here for the new computer student. Maintainability has
been designeci into the P-50 in several ways. Careful selection of components is an important
factll!'. ,\nother is wide-tolerance circuit design. A third is success in observing a statistical
!)rmclple: the fewer the components, the less chance for malfunction. Also important, silicon
c;emIC'onductors are used exclusively in this system. which makes it possible for the P-50 to
r,)lerate the temperaturps and humidity of just about any industrial environment in which men
thern:-;elves can work.
t:~t"'e uC l11.1intenance is a feature of the P-50. The circuit cards are large, easy to insert and
to plug firmly into place. easy to remove; and the cards are widely separated, and cooled by
f()rceri \'pntIiatlOn .

.-\ ~iven Clfnut card contains functionally related circuits, which Simplifies trouble-shooting .
.\::; an example. one "bit" or binary digit of each register, data path and adder are on a SIngle
('ani. If trouble should develop in processing of data, you need to determine only which bit is
In error in order to locate the defective clrcuit. You then simply replace that circuit card
wi th a spare.

The checking of "symptoms" is made easy by the fact that all flip-flops have indicators on the
ends of their cards.
These and other design features give the P-50 calculated availability of 99.9 per cent.
FIELD SERVICE AND SUPPORT
Through a good many decades. Westinghouse has earned a reputation for efficient. expert electric field service. And the engineers of the Electric Service Division have enhanced this reputation with each new technological change. including atomic reactors. space vehicles. solar engines -- and computers for process control. Throughout the U. S•• depending on computer
customers' needs and the terms of their orders or contracts. Westinghouse is prepared to
supply complete field service for its computer systems -- including installation. startup.
checkout. and if necessary maintenance service. The last-named can be on an on-call basis.
or part-time. or full-time.
Westinghouse computer training includes general orientation and review of process control
computer systems; programming. and maintenance.

'.

GENERAL DESCRIPTION - CENTRAL PROCESSOR
The P-50 central processor consists, functionally speaking, of a control section, an
arithmetic section, an input-output (I/O) section, and a core memory section.
It is impossible, however, to identify anyone group of logic circuits as comprising one
of these sections; a logical portion of one section may also function as parts of other
sections. The Z register is an example: It serves as the input-output register for the
memory scction, one of the inputs to the arithmetic section, and as the input register
for the I/O section.

The four sections work together to execute the basic instructions. An understanding of
llw oper.'ltion of e.'lch section gives one.'ln adequate idea of how the central processor
works, and serves as the basis for going on to learn the detailed operation of the P-50
,;entr::11 processor.
C('ntrai Proc('ssor Characteristics - The P-50 employs a core memory with a capacity
The
so\'d size is 1-1 "bits" (binary digits). Cycle time is 4.5 microseconds.

IIi -iK (409(; "words") that is expandable through addition of 4K modules, up to 16K.

fhe arithmetic used is fixed-paint parallel binary, one's complement, negative number.
\dd time (single word length) is 4 cycles, or 18 microseconds; for indirect addressing,
,-) c\cies or 22.5 microseconds.
There are 25 one-word, single-address instructions in the basic repertoi re, all either
directly or indirectly addressable.
The system provides 64 levels of interrupts, with a minimum of 16 lines and increases
in IG-line modules.
(~l()ck

rate is 3.3 megahertz.

rhe first step in learning any specific computer system is to become thoroughly famil:1 r "'ith the block diagram and its inform.'ltion flow.
Before learning the information
i In\\ 'l and the next core plane to the 22 position and so forth. The inhibit winding for the
top plane would get its information from the 20 position of the adder*, the next one
dO\'ll the 21 pOSition, and so forth. When we drive a particular X and Y line, we will
ga1e the entire word in parallel into the Z register, then on the write cycle (not to be
eo ,fused with clock cycle) we will turn on the inhibit lines for each bit plane correspondIll: to zeros at the output of the adder.

*The P-50 uses the output of the adder instead of Z to determine inhibits.

2-2

FlUX

•

o STATE

/

+lM/

FU Ll SE lECT
DRIVE

~--~~-4-------+---H-~-lF--J~-;----~-+CUOENT

SELECT

d L-------;el
_

WRITE

1 STATE

READ & INHIBIT-

Figure 1-3. Typical Hysteresis Loop

2-3

X HALF SELECT

SENSE WINDING

Y HALF SELECT LINE

~=-=::::::IIIl:=-

INHIBIT LINE

Figure 1-4. Core Windings

X
READ

X SENSE X
READ WIRE READ

t

1

X
READ

!

t
Y WRITE

YREAD INHIBIT -

Y READ

Y WRITE

Y READ

Y WRITE

Y WRITE

READ INHIBIT -

X
WRITE

X
WRITE

X

X

WRITE

WRITE

Figure 1-5. Core Plane Wiring

2-4

Xl DRIVE WIRE
X64 DRIVE WIRE
Yl DRIVE WIRE

Y 64 DRIVE.,-:W..;..:...:..;IR=E+---+-+------e--/l+-----,

Y 1 DRIVE W.:. ,:I:,:.:R=-E-+---~--.,~--+-....._ _ _ I l r - - - - - - J

Y64 DRIVE WIRE

X 1 DRIVE WI RE

Figure 1-6. Core Stack Drive Wire Configuration

2-5

Let us look at a typical read-write cycle. A typical read-write cycle would be to select a particular X and Y line (address select) determined by the translation of the S
register. We gate the information from the selected core memory address into the Z
register. If we decide to restore the information into the core unchanged, we leave the
other input to the adder (the X register) set the zeros. Then we take the output of the
adder which would be Z+o, or just Z, and transmit this via the inhibit lines back into
the core memory. If we should desire to write new information into core, we select
an X and Y line, read the core memory, inhibit the reading of the information into the
Z register, place new information into the X register, and transmit the output of the
adder, which would then be X+O, or new information plus zero, into the core memory.
It can be seen that the difference between a read and a write cycle is what we do with
the X and the Z registers. As far as the core memory itself is concerned, there is no
difference.
The PRODAC 50 uses 64 X lines, 64 Y lines and 14 bit planes in its core memory, but
the basic principle is still the same.

2-6

- .i[1

I
I

I

MEMORY
SELECT

I

ENABLE
<,

rr

A-

I

lii

~

r

S REGI STER
UPPER
2 BI TS

I

&

I

FROM S REG I STER
LOWER 12 BITS

I
--~

I

HALF
SELECT
DECODE

I
L_

I
---~

[--STAC~P - I,

L,

DECODE

_~

I , __:t"_ ,--_-t----- - - - - - I - - - . - - - - + - - - - . - I - - - t - - t - t - -

II
I
I

PU~SER

READ

&

r----"L-,

""
"B
Y

DECODE

DECODE
'-w----~ I

L WRITE

L-~J_

TO THRESHOLD
AND STROBE CKTRY
AND INPUT TO
Z REG

ADDER OUTPUT

Y

X

PULSER
READ ,
WR I TE

_ _ - L . _ C_P_

r----'----,-,

--~--------~
--_........-

I

' - -_ _..oJ

I

CP

8 K CORE
__
12_K_CO_R_E_

----

I

4 K CORE

16 K CORE

--.J

I

I

=~_
~JI
~

Figure 1-10.
:'ome locations in core have special Significance. Location 00000 is used as the Program.
Counter and is directly accessible via the half-selects by the SEL P signal. Location 00101 is
used as the Accumulator and is accessible by the SEL A signal. At all other times SEL S is
used as the timing signal which gates the S register contents to the Half-Select Decode.

2-7

.\ DlJHESSI:\G
Half-Selects
The inputs to the half-select switches are the lower 12 bits of the S register and the SEL S
sigml, or the SEL P, or SEL :\ signals. The function of the half-select switches is to route
current through the core stacks, the Interrupt buffer cores, or the I/O subsystem. The pulse
ener~y IS derived from the X Read, X Write, Y Read or Y Write pulsers associated with the
selected stacks. (In the case of Interrupt scan selection or I/O subsystem selection, separate
pulsers are used). The means whereby the half-select decode operates is the simultaneous
selection of a subrow and subcolumn half-select switch. The subrow switch completes the
path to the positive supply from the pulser through a half-select transformer. The three X
(or Y) subrow bits are the lowest three bits of the X (or Y) part of the address. These bits
are decoded to select one of eight X (or Y) half-select transformers. The remaining three X
(or Y) bits are associated with the eight subcolumn half-select switches. The eight subcolumn
h:1lf-select switches connect up to eight loads on any of the eight half-select transformer secondaries. Thus by way of the three subrow bits and three subcolumn bits up to 64 paths can be
s('lcctecl. In the case of the core stack the 64 paths are the 64 half-select lines for X or Y.
The liS carel cont:lins four subrow half-select switches and four subcolumn half-select switches.
luur liS clrds an: used in the main frame to provide eight subrow switches for X and eight for
Y. ;lllci eip;ht subcolumn sWitches for X and eight for Y.

In urder to route currents through the selected half-select lines, parallel unselected paths
must be blocked by blocking diodes. Each path needs two blocking diodes. This is because
p;lth~ must be blocked lor the two directions of current flow corresponding to Head and Write.
ThiS means that the 6-1 X half-select lines and 64 Y half-select lines require 256 diodes. These
dIOdes :\re mounted on two diode boards, the MA and MB, which are attached to either side of a
stack. :\ Iso mounted on the two diode boards are the 16 half-select transformers and damping
rl.'sistors :\ssociated with the stack.
Pulsers
I'll,' Jk.ld, Write, :tnd Inhibit pulsers are associated with a 4096-word stack.

The same circuit
IS llSl'd tur each of these current pulsers with six circuits located on each CP card. This high\llmer current pulse source is intended to produce stable currents even when operated from an
UIll'l'guLtted supply. Potentiometers for adjusting currents through a 300 milliampere to a 400
III ililanipere range are provided.
The rise times of the current pulses are controlled to give
:1 (). '.I microsecond 10'/( to 90% rise.
The fall is not controlled but drops at nearly the same
1'.1 te.

The pulsers are the means by which a particular stack is selected. Addressing is a continuing
p rucedure involving the half-select switches, but only that stack will be energized, and theretot'" selected, whose pulsers are selected. The Stack Select Signal is derived from the Inhibit
\'.lddle cards where :\:\:\Os decode the upper two bits of the S Register.
\nhll)it Paddle Card
Th., II' Inhibit Paddle Card contains damping resistors for the Inhibit lines. Also on this card
11'(' two :\:\:\Os which are used to decode the upper two bits of the S register and generate
Such. Select signals for the various stacks.

2-8

DA TA CIRCUITS
Sense Amplifier
An S.-\ Sense Amplifier is associated with each core stack. There are 14 amplifiers on a card
corresponding to the 14 sense line pairs. The line itself is terminated in 100 ohms. The amplifier is a balanced differential type with a normal mode gain of about 60 to 5 mc and a common mode rejection at 1 mc of 60 db. Since response voltage signals can be of either polarity.
an output transformer and rectifiers are used to created unipolar signals at a new voltage level
on the output of each amplifier. The outputs of amplifiers from up to four stacks are paralleled
and tied to the bit card where the threshold detector and strobe circuits are located.
Inhibit
The Inhibit pulsers are located on the CP card. Fourteen pulsers are used per core stack.
The outputs of the Adder gated by the W timing signal are always feeding the data inputs of all
the Inhibit pulsers. Only the Inhibit pulsers which are selected by the Stack Select Signal will
drive Inhibit lines to determine whether a zero or one is restored to a core location.
TI:\IIi\G CHART
The important signals associated with the Core Memory Subsystem are the Select, Read, Strobe.
Write, and Inhibit timing Signals. Another time is the gap between Strobe and Write which is
allotted to Adder propagation time. The signals for a core sequence are shown in Figure 1-11.
All signals are determined by fixed timing taps except Strobe, which can be adjusted over a
range of five selectable 50-nanosecond taps. Select P and Select A are not shown but have the
same extension as the Select S signal.

D[LAy L'N[ TA'S

~
LO

~

~
L,

LZ

lJ

l....

LO.

L,

lZ

l).

l....

LO

'II

''''H.
SEL

Figure 1-11. Core Memory Subsystem Timing Chart

2-9

"This Page Intentionally Blank"

2-10

REPERTOIRE OF INSTRUCTIONS
COMMAND STRUCTURE
All P-50 instructions may be either directly or indirectly addressed. The bit configuration
for each address mode is as follows:
Instruction, Direct Address Mode
13 12 11 10 9 8 7 6 5 432 1 0
Function
Code

0

Bit

Relative
Address

Content

In the direct address mode, the 14-bit operand address required to reference a memory cell
is generated by the six most significant bits of the program address register and the low-order
eight bits of the instruction (the relative address). This imposes the requirement that all instructions which are directly addressed have their operand in the same block of 256 words in
which the instruction is located.
Instruction, Indirect Address Mode
13 12 11 10 9 8 765 432 1 0
Function
Code

1

Bit

Relative
Address

Content

Address Defined by P Register and Relative Address
13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Operand Address

Content

In the indirect address mode, the operand address is defined by the contents of the location
specified by the six most significant bits of the P Register and the low-order eight bits of the
instruction (the relative address).
.
Input/Output instructions vary slightly from this pattern.
Input/Output Instruction, Direct Address Mode
13

12

11

10

4

3

......

1

Bit

1

Function
Code

Channel
Number

Content

In the direct address mode, used primarily for input, the low-order six bits of the instruction
designate the 1/0 channel.

3-1

Input/Output Instruction, Indirect Address Mode

13 12 11 10 9 8 7 654 321 0
Function
Code

1

Bit
Content

Relative
Address

Address Defined by P Register and Relation Address

13 12 11 10 9 8 7 6 543210

Bit

Not
Used

Content

Word
Select

Channel
Number

In the indirect address mode, used mainly for output, the six most significant bits of the program address register and the low-order eight bits of the instruction specify the location of
the I/O data word. The I/O data word contains the channel number in the low-order six bits
(5-0) and the word number relative to the channel in bits 11-6.
TIMING
The execution of an instruction in the indirect mode occupies 4.5 microseconds more than when
the instruction is executed in the direct mode.
DESCRIPTION OF OPERATION
REMARKS

MNE

CODE

DES

:\ + (Y) - - A
:\ - (Y) - - - A

ADD
SUB

SET
SET

ADD
SUBTRACT

(Y) - - - A

ENL

10
11
32

SET

LOAD A

:\ - - (Y)

A
(Y)--A
L (A)(Y) - - - A

STL
EOR
AND

SET
SET
SET

STORE A
SEL. COMPL.
LOGICAL PRODUCT OF (A) & (Y)

(Y) R1 ---- (Y)

RSH

SET

END off - SIGN EXT_

(Y) L 1 - - (Y)

LSH

SET

(Y) - 1 - - (Y)

DCR
5MB
CMB
EDR

SET
SET
SET

END - AROUND
DECREMENT
SET MOST SIG. BIT
CLR MOST SIG. BIT
LOAD DESIGNATORS

K

STORE DESIGNATORS

SET

INPUT

SET

OUTPUT

K
K
K

JUMP
SET LOCKOUT
CLR LOCKOUT

INST.

e

SET (Y)13
CLR (Y>l:,
(Y 4-0) - -

DES

DES - - - (Y4-0)

SDR

I/O ---P,

INT

l' ----

I/O

Y-P
Y-P
Y-P

lOUT

I JMP

I

SLJ
CLJ

33

37
13

12
16
17

14
15
01
03
02
05
06
07

30
31
34
35
24
22
23

3-2

INST.

REMARKS

MNE

CODE

DES

ZJP

20

K

JUMP ON ZERO

PJP

27

K

JUMP ON POSe

y---p

if 0 DESIG SET
y-p

if POS DESIG SET
y-p

EJP

21

K

JUMP ON EVEN

y-p
if EAC DES SET
y---p

CJP

25

K

JUMP ON END AROUND CARR\

if OVERFL DES SET
(P) - - - y, Y - - - P

OJP
RJP

26
36

K
K

JUMP ON OVERFLOW
RETURN JUMP

STP

00
04

K

STOP

if EVEN DESIG SET

STOP

REPERTOIRE OF INSTRUCTIONS
Mnemonic Code
Octal Code
STP

Description

STOP

00,04

Execution time:

9 microseconds

2

The computer comes to a stop with the contents of bits 13-8 of the P Register in
bits 13-8 of the S Register and the contents of bits 7-0 of the stop instruction in
bits 7-0 of the S Register. The mode bit is disregarded and the designators are
unchanged.
DCR
01

DECREMENT
Execution time:

13.5 microseconds

A negative one is added to the operand. The appropriate designators are set if an
overflow, end-around carry, zero, positive number, and/or even number results;
otherwise, all the designators are cleared except the overflow designator.
Cl\iB

CLEAR MOST SIGNIFICANT BIT

02

Execution time:

13.5 microseconds

The sign bit (bit 13) of the operand is cleared to zero and the positive designator
is set. The zero and even deSignators are set or cleared depending on the resultant
contents of the operand. The end-around carry designator is cleared, and the overflow designator is unchanged.
5MB

SET MOST SIGNIFICANT BIT

03

Execution time:

13.5 microseconds

The sign bit (bit 13) of the operand is set to one. The even and zero deSignators
are set or cleared depending on the reSUltant contents of the operand. The positive
and end-around carry designators are cleared, and the overflow designator is unchanged.

3-3

EDR

ENTER DESIGNATORS

05

I)

Execution time:

13.5 microseconds

Bits 0-4 of the operand replace the contents of the five designators in the following manner:
Bit
Bit
Bit
Bit
Bi t

4 - - - Even designator
3 - - Zero designator
2 - - - Positive designator
1 - - - Overflow designator
0 - - End-around carry designator

Only this instruction can clear the overflow designator once it has been set.
~TORE

SDR

QESIGNATOgS

06,Oi

?

Execution time:

13.5 microseconds

The five designators are stored in bits 0-4 of the operand. The designators are
not changed as a result of this instruction. The storage is as follows:
.. Bit 4
Even deSignator
Zero deSignator
.. Bit 3
Positive designator ------.. Bit 2
Overflow deSignator - - Bit 1
End-around carry deSignator - B i t 0
(Y)S-13 are cleared to zero
ADD
10
vj

ADD ACCUMULATOR
Execution time:

18.0 microseconds

The operand is added to the contents of the accumulator and the result is left in
the accumulator. The result is positive zero only if the initial contents of the accumulator and of the operand were both positive zero. The even, zero, positive,
and end-around carry deSignators are set or cleared by the execution of this instruction. The overflow designator will be set if an overflow occurs; otherwise
it is unchanged.

SuB
11

SUBTRACT ACCUMULATOR

'1

Execution time:

18.0 microseconds

The operand is complemented and added to the contents of the accumulator (a subtraction, in effect); the result is left in the accumulator. The difference is positive zero only if the initial contents of the accumulator were positive zero and the
operand was negative zero. The even, zero, positive, and end-around carry designators are set or cleared by the execution of this instruction. The overflow designator will be set if an overflow occurs; otherwise, it is unchanged.

3-4

AND

LOGICAL AND

12
Execution time:

lS.0 microseconds

For any bit position of the operand which contains a zero, the corresponding bit
position of the accumulator is unconditionally set to zero; all other bit positions
of the accumulator remain undisturbed. The effect of this instruction is to compute the bit-by-bit or logical product of the contents of the accumulator and the
operand, leaving the result in the accumulator. The even, zero, and positive designators are set or cleared depending on the result in the accumulator. The endaround carry designator is set; the overflow designator is unchanged.
Example:

Initially:
After execution of AND instruction:
(Positive designator is set to one;
even and zero designators are cleared
to zero, and the EAC is set to one.)

(Accumulator)

(Operand)

01011
00001

00101
00101

EXCLUSIVE OR

EOR
13

Execution time:

IS. a microseconds

For any bit position of the operand which contains a one, the corresponding bit of
the accumulator is complemented; all other bit positions of the accumulator remain undisturbed. The even, zero, and positive deSignators are set or cleared
depending on the result in the accumulator. The end-around carry designator is
cleared, and the overflow deSignator is unchanged.
Example:

Initially:
After execution of EOR instruction:
(Even and positive deSignators are set
to one; end-around carry and zero
designators are cleared to zero.)

(Operand)

01011
01110

00101
00101

LEFT SHIFT

LSH
14,15

(Accumulator)

11

Execution time:

1S.0 microseconds

Shift the operand to the left one bit position; the high-order bit replaces the loworder bit of the operand. The even, zero, end-around carry, and positive designators are set or cleared depending on the result. The overflow deSignator is set
if the sign of the operand changed as a result of the left shift; otherwise it is unchanged.
10 -' I

'

For example, the operand = 24505. After LSH, the operand = 11213 with the positive, end-around carry, and overflow deSignators set to one, all other designators
cleared to zero.

3-5

RIGHT SHIFT

RSH

16,1 i

1

Execution time:

18.0 microseconds
.i"

Shift the operand to the right one bit positionj the high-order bit is replaced by
the original bit. Note that this is an end-off shift and that the low-order bit enter.
the end-aroWld carry designator. The zero, even, and positive designators are
set or cleared depending on the result. The overflow designator is Wlchanged.
,

' ('(

'

,

'

. ('

For example, the oper~d\~ 24505. After RSH, the operand = 32242 with endaround carry designator set to one, the positive, zero, and even designators
cleared to zero.
·ZERO JUMP

ZJP
20

')

-

-

-

Execution time:

13.5 microseconds if jump, 9.0 microseconds if no jump.

If the zero deSignator is set, transfer the operand address to the P Register.
Otherwise, take the next instruction. Note that the zero deSignator will be set by
negati ve zero (all ones) or by positive zero (all zeros). The designators are not
changed as a result of this instruction. Interrupt is inhibited immediately following the execution of this instruction.

EJP
21

·EVE~

"7

-

JUMP
-

Execution time:

13.5 microseconds if jump, 9.0 microseconds if no jump.

If the even deSignator is set, transfer the operand address to the P Register.
Otherwise, take the next instruction. Note that the even deSignator is set whenever bit 13 and bit 0 of a referenced location are equal. The deSignators are not
changed as a result of this instruction. Interrupt is inhibited immediately follow109 the execution of this instruction.

SLJ
22

?

·SET
LOCKOUT AND -JUMP
Execution time:

13.5 microseconds

Lock out all interrupts and transfer the operand address to the P Register. The
deSignators are not changed as a result of this instruction.
CLJ
23

~

·CLEAR
LOCKOUT AND -JUMP
Execution time:

13.5 microseconds

Remove the interrupt lockout and transfer the operand address to the P Register.
The deSignators are not changed as a result of this instruction. Interrupt is inhibited inunediately following execution of this instruction.

* Note

that when an operand address is transferred to the P Register, the instruction at location
operand address plus one is the next instruction to be executed.

3-6

JMP
24

*JUMP
Execution time:

13.5 microseconds

Unconditionally transfer the operand address to the P Register. The designators
are not changed as a result of this instruction. Interrupt is inhibited inunediately
following the execution of this instruction.
CJP

*END-AROUND CARRY JUMP

?

25
Execution time:

13.5 microseconds if jump. 9.0 microseconds if no jump.

If the end-around carry designator is set. transfer the operand address to the P
Register. Otherwise. take the next instruction. The designators are not changed
as a result of this instruction. Interrupt is inhibited immediately following the
execution of this instruction.

OJP
26

*OVERFLOW JUMP
Execution time:

13.5 microseconds if jump. 9.0 microseconds if no jump.

If the overflow designator is set. transfer the operand address to the P Register.

Otherwise. take the next instruction. The designators are not changed as a result
of this instruction. Interrupt is inhibited immediately following the execution of
this instruction.
PJP
27

* POSITIVE JU MP
Execution time:

13.5 microseconds if jump. 9.0 microseconds if no jump.

If the positive designator is set. transfer the operand address to the P Register.

Otherwise, take the next instruction. The designators are not changed as a result
of this instruction. Interrupt is inhibited inul1ediately following the execution of
this instruction.
INT

INPUT TO COMPUTER

30,31

Execution time:

18.0 microseconds

In the direct mode, data on the input channel specified by bits 0-5 of the instruction
are input into the accumulator. In the indirect mode, bits 0-5 of the I/O data word
select the input channel and bits 6-11 the word address. The indirect mode should
be used with utmost caution; otherwise, conflict with other peripheral devices may
occur. The deSignators are set, cleared, or unchanged as in the ENL instruction.
E~L

ENTER ACCUMULATOR

32,33

Execution time:

18.0 microseconds

Clear the accumulator, then transmi t the operand to the accumulator. The even,
zero, and positive designators are set or cleared depending on the resuitant contents of the accumulator. The end-around carry designator is cleared to zero,
and the overflow deSignator is unchanged.
'" Note that when an operand address is transferred to the P Register, the instruction at location operand address plus one is the next instruction to be executed.

3-7

OUT
34,35

OUTPUT FROM COMPUTER
Execution time:

1B.0 microseconds

If indirectly addressed, the contents of the accumulator are output on the channel
selected by bits 0-5 of the 1/0 data word and the word selected by bits 6-11. In
the direct mode, the contents of the accumulator are output on the channel selected
by bits 0-5 of the instruction. The designators are set, cleared, or Wlchanged as
in the STL instruction.
RJP
36

·RETURN JUMP

"

")

Execution time:

22.5 microseconds

Store the contents of the P Register in the operand; transfer the operand address
to the P Register. The designators are not changed as a result of this instruction.
Interrupt is inhibited immediately following the execution of this instruction.
STL
37

STORE ACCUMULATOR
~

Execution time:

1B.0 microseconds

Store the contents of the accumulator in the operand. The even, zero, and positive
designators are set or cleared, depending on the contents of the accumulator. The
end-aroWld carry designator is cleared to zero, and the overflow designator is
unchanged.
THE

DESIG~ATORS

Even Designator
The even designator is affected (set or cleared) by the execution of the following instructions:
OCR, CMB, 5MB, EDR, ADD, SUB, AND, EOR, LSH, RSH, INT, ENL, OUT, STL.
When the even designator is set by the execution of an instruction other than EDR, it implies
that bits 0 and 13 of the resultOf the instruction are both zero or both one.
Zero Designator
T~e zero designator is affected (set or cleared) by the execution of the following instructions:
DCR, CMB, 5MB, EDR, ADD, SUB, AND, EOR, LSH, RSH, INT, ENL, OUT. STL.

\Vhen the zero designator is set by the execution of an instruction other than EDR, it implies
that the result of the instruction is 00000 or 37777.
Positive Designator
The positive designator is affected (set or cleared) by the execution of the following instructions:
(JI"t{, EDR, ADD, SUB, AND, EOR, LSH, RSH, INT. ENL, OUT. STL. The positive designator
is always set by the execution of the CMB instruction, always cleared by the execution of the
SMll instruction.
\Vhen the positive designator is set by the execution of an instruction other than EDR, it implies
that bit 13 of the result of the instruction is zero•
.

-

~.

*Note that when an operand address is transferred to the P Register, the instruction at location
operand address plus one is the next instruction to be executed.
3-8

End-Around Carry Designator
The end-around carry designator is affected (set or cleared) by the execution of the following
Instructions: OCR, EDH, ADD, SUB, LSH, RSH. The end-around carry designator is always
cleared when C:\IB, S:\IB, EOn, INT, ENL, OUT, and STL instructions are executed. EAC is
always set with execution of .-\!\D.
\\·hen the end-around carry designator is set by the execution of a DCR, ADD, SUB or LSH in~truction. it implies that an end-around carry has occurred. When the end-around carry des19nator 1S set by the execution of a RSH instruction. it means that the low-order bit of the operand which"is shifted off is a one.
Overflow Designator
The overflow designator 1S set whenever two pos1ttve numbers are summed and the result is
negative. or two negative numbers are summed and the result is positive. The overflow des19nator can t)e set by the execution of the following instructions: DCR, ADD, SlJB, LSH. The
EDH instruction only can be used to clear the overflow deSignator.
DeSignators When Clear
The designators. when clear. indicate the following:
Odd (Even deSignator)
~on-zero (Zero designator)
:\egaUve (Positive deSignator)
~o end-arllund carry (End-around carry deSignator)
:\0 overflow (Overflow designator)

3-9

"This Page Intentlonally Blank"

3-10

COMMAND TIMING
Command timing is a list of all commands required to perform a given instruction with
respect to order of occurrence.
Before delving into the heart of command timing several things should be established.
It is expected that one is familiar with the block diagram including all registers, the
various parts of the control section diagram as to why they exist and what they do, and

the repertoire of instructions.
Along the left hand margin of command timing is the computer timing with respect to
the master clock. The three sets of LO - L5 which are listed correspond to cycle 0, 1,
and 2. The top of the page prior to cycle 0, LO gives the sequence number and the conditions which must be met for this sequence to be done.
Tracing an instruction through command timing to determine the sequences performed
is done as follows. Assume an add instruction is to be done (octal code 10). Start with
sequence II. (All instructions start with sequence II.) No conditions are stated for its
entrance, therefore we can say and rightfully so that all instructions do sequence II.
After an ADD goes through sequence II the computer turns the page to sequence III. No
conditions here either so it does sequence III. It then looks at sequence IV. It is not
an unsatisfied jump (it is not a jump at all) so the computer says "is the mode bit equal
to one?", if yes do sequence IV if not skip sequence IV. After making the decision and
either doing or not doing sequence IV the page is turned. Here sequence V is found, but
it says this page is only done on an octal code 01, so we turn the page. Can't do this
one either. Once past sequence IV we look for the first page with the octal code of the
instruction being performed. We finally get to an ADD octal code 10 sequence V. This
one we do. Then turn the page and find ADD octal code 10 sequence VI, we do it also.
After turning the page again we find SUB octal code 11. As one would find out after
turning the balance of the pages all octal codes are placed together in numerical order
and in the order performed. That is, because ADD sequence V page is before ADD sequence VI then sequence V must occur before sequence VI. When no more pages can be
found for this instruction the computer returns to sequence II to obtain the next instruction.
Prior to looking into the command timing itself some of the terms will be defined. Some
of these terms are listed on page 4-7. The following is a more detailed explanation of
these and other terms found in the text.
SET READ
The SET READ signal will initiate the reading of the core memory address specified by
the select. Remember the core memory location selected is determined by a SELECT
S, SELECT P, or SELECT A signal. The reading of a core memory location clears
the cores at that address and places their state on the sense winding where it mayor
may not be gated into the Z register by the READ STROBE command.

4-1

The CLEAR READ signal serves only to terminate the read part of the core memory
cycle. Because the read operation is a destructive readout the selected memory
address will be cleared to zero by the time the clear read command occurs. This location will remain zero until the write operation replaces the original contents or writes
new information. If the READ STROBE signal does not occur the information originally
in core dies on the sense lines and is lost.
SET WRITE
The SET WRITE signal writes the output of the adder (Z register plus X register) into
the memory location determined by the select. This may be the original information
in the Z register with the X register cleared. This type of memory cycle is called
"read restore". It may be new information in the X register with the Z register
cleared (because of no READ STROBE). This type of memory cycle is called "clear
write". Or it m.ly be the original information in the Z register and new information in
the X register. In which case I don't have the slightest idea what the core memory
cycle is called.
READ STROBE
The READ STROBE signal gates the contents of the specified core memory address into
the Z register. Contrary to popular belief this is all it does- it does not clear the memory location being read. That is the function of the read and is done whether the READ
STROBE is done or not. The READ STROBE is timed to occur at the proper instant
to gate this information. It occurs sometime between LA and L5. For SimpliCity it is
shown to occur at L5. This in no way affects the operation or understanding of command
timing.
SET CLAMP
SET CLAMP means to force the specified point to a logical zero. Because the command
says SET CLAMP and not just CLAMP it implies that the point is forced to a logical zero
and held there. This is exactly what happens. The clamp remains until a CLEAR CLAMP
signal occurs. The specified point for the clamp will be one side of a flip-flop (either the
cleared or set side). Forcing the cleared side of a flip-flop to a logical zero will set the
flip-flop and forcing the set side of a flip-flop to a logical zero will clear it. (re; page 1-43).
Remember that just because the clamp is removed or cleared does not mean that the
flip-flop will be changed back in its state. For instance wh~a SET CLAMP XO signal
occurs the XO flip-flop will set. When the CLEAR CLAMP XO signal occurs the flipflop will not be cleared; it will only stop being held set.
CLEAR CLAMP
As the above states a CLEAR CLAMP signal removes the forced logical zero from the
specified pOint.

4-2

DL
Designator logic::; (DL) are the logics used to examine the Z register, X register, and
adder output when the designators are being set. The command DL - DESIGNA TORS
means exami,ne these and set the designators accordingly.
IL
Interrupt lockout (IL) is a flip-flop which will prevent the recognition and processing of
The command SET SET IL may sound like a stuttering
typewriter but is stated that way for a purpose. If the command were labeled SET IL
it \,'ould mean that the command occurred only during the tap time specified. But this
is not the case; the SET SET IL signal means that the IL flip-flop is held set from that
time until the SET IL signal is removed by a CLEAR SET IL. It may be asked now ~f we set the IL flip-flo.Q..and hold it set for a period of time why n~use SET CLAMP
IL and CLEAR CLAMP IL". The not so obvious reason is that the IL pOint is not
clamped. That is the cleared side of the IL flip-flop is not held to a logical zero directly, The flip-flop is held set by fully enabling the input gates to the set side for
this period of time. Operating in the same manner one will find a SET CLEAR IL and
a CLEAR CLEAR IL. The clearing of the CLEAR IL signal does not set the IL flip-flop,
and the dearing of the SET IL signal does not clear the IL flip-flop.
any interrupt while it is set.

HA, SA
These stand for sequence half advance (HA) and sequence advance (SA). HA and SA are
flip-flop registers (three each) which are used to handle the advancing form one sequence
to another. HA, in basic terms, tells the computer which sequence will be done next
and SA tells the computer what sequence is being done now.
Assume the computer is doing sequence II. At cycle 0, LO HA and SA both contain the
\':liue for sequence II. At cycle 2, L 1 HI\. is cleared in preparation for cycle 2, L3
setting it to the next sequence to be done. (Sequence III). The computer now knows
that it is doing sequence II (by SA) and that it will do sequence III next (by HA). At
cyde~, L:J SET SA causes HA to be transferred to SA, and the computer now does se4uence III. Because of the L5, LO overlap this time can also be considered cycle O. LO
of t he next sequence (III). Now one may look at HA and say that since HA is still set to
sequencc III the computer thinks it will do sequence III next. The statement made before that HA tells the computer what sequence will be done next is still true if we real1 ze that the computer only asks during cycle 2, L5 when it wishes to advance SA.
SET I/O PULSE
Thi::; :-,ignal t"au::;es the drive currents to be routed through the input output addressing

::;cction ()f the computer not the core memory section. This is necessary because the
same S register and translating circuitry is used for both input output and the core
memory.
Note page -l-8.
This page is drawn in an altogether different manner than the
llthers. This \vas done by mistake and has not been changed because it is a very good

4-3

way to remind one that sequence I is totally different from the rest. This is about all
that will be mentioned about sequence I at this time. It will be covered in detail in the
section on interrupts.
Reference sequence m cycle 2, lA. The subscript 0-7 means that only bits 0 through
7 of the S register will be affected, bits 8 through 13 will not be changed. The arrow
after ADDER means "is transferred to". ( ) means the contents of the specified
register.
Refer to ZJP instruction octal code 20 sequence VII, cycle 0, Ll. The (S) means just
what it implies. The actual contents of the S register is transferred to the Z register
not the contents of the memory location specified by the S register.
Hefer to EDR instruction octal code 05, sequence V, cycle I, L5. The CLEAR DESIGNA TOR TO "1 "s command means that all the designator flip-flops will be in the one
or set state as a result of this command. This is not the only register which is set to
all ones prior to entering, but in this case the computer may stop (if in cycle step re;
page 1-71) after the clearing and before the entering. It could be confusing and lead
one astray if it said CLEAR DESIGNATORS and all the lights were lit in the designator
register. In the other case the computer cannot stop before entering. Therefore only
the end result could be seen and could not be confUSing.
Figure page 4-6 shows the opposite view of command timing from the sequential list
based on the instructions. In this chart the commands and sequences are shown along
the left, and three cycles of time along the top. The black bar in the main body of the
chart shows that the command or condition exists at the time shown directly above.

4-4

Command Sequencing (Timing)
The description that follows contains details of command sequencing of the P-50 computing control system.
Set read-

Initiate the reading of the core memory address specified by the
select.

Set write-

Write the output of the adder into the core memory address specified by the select.

Head strobe-

Gate the contents of the core memory address specified by the
select. into the Z register.

Set clamp-

Force the specified point to a logical zero until a clear cl:tmp
signal is received.

Clear clamp-

Hemove the forced logical zero from the specified point.

01.-

Designator logics

IL-

Interrupt lockout

H.\-

Sequence half-advance flip-flops

S.\-

Sequcnce advance flip-flops

Set I/O pulse-

Turn on the ch:1nncl and word drives in the peripheral equipment.

4-7

CLOCK
TIME

CYCLE 1

CYCLE 0

lO

SET SEl S, CLAMP lfO' ClR Z,
AMD X

II

SET READ, ClR F
IMTERR PULSE

S -Z,

l2
~

I
CD

l3

ClR READ, ClR S
SEl, ClR CLAMP lfO

III

ADDER~S

lS

, ClR

I

CYCLE 2

I
I

rIl

[q

£)

c::
[q
Z

(')

...
[q

SEQUENCE II
LO

CLEAR Z AND X, SET SELECT "P", SET CLAMP X"O

Ll

CLEAR F, SET READ

L2
L3
L4

L5

READ STROBE

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4

L5
LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT "P", CLEAR S, CLEAR CLAMP XO, CLEAR WRITE

L4

ADDER ---. S

L5

SET SA

4-9

SEQUENCE 111

LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ

L2
L3
L4
L5

READ STROBE

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
L5
LO
Ll

CLEAR HA. (Z)S-13 • F

L2
L3

SET HA, CLEAR SELECT "S", CLEAR SO_7' CLEAR WRITE

L4

ADDER~ SO-7

L5

SET SA
IF F = 22 OR 23 INTERRUPT LOCKOUT WILL BE SET OR CLEARED DURING
L3 AND L4 TIME OF CYCLE 2 IF THE MODE BIT = O.

4-10

SEQUENCE IV
(NOTE: This sequence takes place only if the mode bit = 1 and there 1s no unsatisfied jump.)
LO

CLEAR Z AND X, SET SELECT "5"

Ll

SET READ

L2
L3
L4
LS

READ STROBE

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
LS
LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT "S", CLEAR "S", CLEAR WRITE
ADDER-...... S

LS

SET SA
IF F = 22 OR 23 INTERRUPT LOCKOUT WILL BE SET OR CLEARED DURING
L3 AND L4 TIME OF CYCLE 2.

4-11

DCR
OCTAL CODE: 01
SEQUENCE V
LO

CLEAR Z AND X. SET SELECT "S" NOTE: CLAMP Xo SET BY PREVIOUS LS

Ll

SET READ, (Z)

• X

L2

L3
L4

LS

READ STROBE, CLEAR DESIGNATOR

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4

LS

DL - - + DESIGNATOR

LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)---.... X

L4

LS

SET SA, CLEAR CLAMP Xo

4-12

CMB
OCTAL CODE: 02
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S" NOTE: CLAMP Z13 SET BY PREVIOUS L5

Ll

SET READ

L2

L3

L4
LS

READ STROBE, CLEAR DESIGNATOR

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4
LS

DL --+ DESIGNATOR

LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)

L4
LS

SET SA, CLEAR CLAMP Z13

4-13

~x

8MB
orAL CODE: 03
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ

NOTE: CLAMP Z13 SET BY PREVIOUS LS

L2
L3

L4
LS

READ .STROBE, CLEAR DESIGN ATOR

LO
L1

CLEAR READ

L2
L3

SET WRITE

L4

LS

DL----.~ DESIGNATOR

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)
L4

L5

SET SA, CLEAR CLAMP Z13

4-14

.. X

EDR
OCTAL CODE: 05
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ

L2
L3

L4
LS

READ STROBE, CLEAR DESIGNATOR

LO
L1

CLEAR READ

L2
L3

SET WRITE

L4
LS

CLEAR DESIGNATOR TO

"1" S

LO
Ll

CLEAR HA

L2
SET HA CLEAR SELECT "S" CLEAR WRITE (Z)----. DESIGNATOR
,
,
'(Z)~X

SET SA

4-15

SDR
OCTAL CODE: 06, 07
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ, SET

DESIGNATOR-"""~ZO_4

L2
L3

L4
L5

LO
Ll

CLEAR READ, CLEAR

DESIGNATOR~

ZO_4

L2
L3

SET WRITE

L4

I

L5

LO
Ll

CLEAR HA

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)-....;.~ X

4-16

.

ADD
OCTAL CODE: 10
SEQUENCE V

I

/ljI:1' ,

LO

CLEAR Z AND X. SET SELECT "S"

Ll

SET READ

L2
L3
L4
LS

READ STROBE, CLEAR DESIGNATORS

La
Ll

CLEAR READ

L2
L3

SET WRITE

L4
LS
La
Ll

CLEAR HA

L2
L

3

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)

L4
LS

SET SA

4-17

~x

f' ,1 (

If'

\.

ADD
OCTAL CODE: 10
SEQUENCE VI
LO

CLEAR Z, SET SELECT "A"

L1

SET READ

L2
L3
L4

L5

READ STROBE

LO
L1

CLEAR READ

L2
L3

SET WRITE

L4

L5

DL ----... DESIGNATOR

LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT A, CLEAR WRITE

4-18

SUB
OCTAL CODE: 11
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ

L2

L3
L4
L5

READ STROBE, CLEAR DESIGNATORS

LO
L1

CLEAR READ

L2

L3

SET WRITE

L4

L5
LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "S", (Z)--". X, CLEAR WRITE

4-19

SUB
OCTAL CODE: 11
SEQUENCE VI
La

CLEAR Z, SET SELECT "A"

L \

SET RE;\D

L2
1,3

L~

L~

:)

READ S'l{UBE

L,.

L1

CLEAR READ

L2

L3

SET WRITE

Li
DL-~~

DESIGNATOR

LO
L,
L

L3

CLEAR HA

SET HA, CLEAR SELECT "A", CLEAR WRITE

L'l

L.;)

SET SA

4-20

AND
OCTAL CODE: 12
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ

L2

L3
L4

LS

READ STROBE, CLEAR DESIGNATORS

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4
LS
LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "S", CLEAR WRITE.

4-21

(Z)-~
.. X

AND
OCTAL CODE: 12
SEQUENCE VI
La

CLEAR Z, SF.;T SELECT "A", SET AND

Ll

SET READ

L2

L3
L4
L5

READ STROBE

La
L1

CLEAR READ

L2

L3

SET WRITE

L4
L5

i.

DL --+. DESIGNA TOR

La
Ll

CLEAR HA

L2
La

SET HA, CLEAR SELECT "A", CLEAR WRITE

L4
L5

SET SA, CLEAR AND

4-22

EOR
OCTAL CODE: lS
SEQUENCE V
LO

CLEAR Z AND X. SET SELECT "S"

Ll

SET READ

L2

LS
L4

L5

READ STROBE, CLEAR DESIGNATORS

LO
L1

CLEAR READ

L2

La

SET WRITE

L4

L5
LO
Ll

CLEAR HA

L2

La

SET HA. CLEAR SELECT "S". (Z) --l~~x. CLEAR WRITE

4-23

EOR
OCTAL CODE: 13
SEQUENCE VI
La

CLEAR Z, SET SELECT "A", SET EOR

L1

SET READ

L2

L3
L4
LS

READ STROBE

La
L1

CLEAR READ

L2

L3

SET WRITE

L4
LS

DL-.....,~~

DESIGNATOR

La
L1

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "A". CLEAR WRITE

L4
L5

SET SA. CLEAR EOR

,.-24

LSH
OCTAL CODE: 14, 15
SEQUENCE V
LO

CLEAR Z AND

L1

SET READ

X. SET SELECT "S"

L2
L3
L4
LS

READ STROBE, CLEAR DESIGNATORS

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
LS
LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)--+. X

4-25

LSH
OCTAL CODE: 14, 15
SEQUENCE VI
La

CLEAR Z, SET SELECT

Ll

SET READ

"s"

L2
L3
L4
L5

READ STROBE

La
L1

CLEAR READ

L2
L3

SET WRITE

L4
L5

DL -.....,~~ DESIGNATOR

La
Ll

CLEAR HA

L2
L3

SET HA. CLEAR SELECT "S", CLEAR WRITE

L4
L5

SET SA

4-26

RSH
OCTAL CODE: 16, 17
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

L1

SET READ

L2
L3
L4
L5

READ STROBE, CLEAR DESIGNATORS

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
L5
LO
Ll

CLEAR HA

-

L2

SET HA, CLEAR SELECT "S" .. CLEAR WRITE, (Z)-......
~X

4-27

RSH
OCTAL CODE: 16. 17
SEQUENCE VI
LO

CLEAR Z. SET SELECT "S"

L1

SET READ

L2

L3
L4

LS
LO
L1

CLEAR READ

L2

L3

SET WRITE

L4

LS

DL-.....,·~DESIGNATOR

LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "S", CLEAR WRITE

L4

LS

SET SA

4-28

ZJP

OCTAL CODE: 20
SEQUENCE VII
LO

CLEAR Z AND X. SET SELECT "P"

Ll

SET READ (S) ---. Z

L2

L3
L4

L5
LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4

L5
LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "P", CLEAR WRITE

L4

L5

SET SA

4-29

EJP
OCTAL CODE: 21
SEQUENCE VII
LO

CLEAR Z AND

Ll

SET READ

X. SET SELECT liP\!

(S)--~~

Z

L2
L3

L4
LS
LO

Ll

CLEAR READ

L2
L3

SET WRITE

L4
LS
LO

Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT lip", CLEAR WRITE

L4
LS

SET SA

4-30

SLJ
OCTAL CODE: 22
SEQUENCE VII
LO

CLEAR Z AND X, SET SELECT "P"

Ll

SET READ, (S) ---... Z

L2
L3
L4

L5

SET SET IL

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4

L5
LO
Ll

CLEAR HA, CLEAR SET IL

L2
SET HA, CLEAR SELECT.
"P",
CLEAR. WRITE
.

4-31

CLJ
OCTAL CODE: 23
SEQUENCE VIl
La

CLEAR Z AND X, SET SELECT "P"

Ll

SET READ, (8) --+ Z

L2

La
L4

L5

SET CLEAR IL

La
Ll

CLEAR READ

L2

La

SET WRITE

L4

L5
La
Ll

CLEAR HA, CLEAR CLEAR IL

L2

La

SET HA, CLEAR SELECT

"p".

CLEAR WRITE

L4

L5

SET SA

4-32

JMP

OCTAL CODE: 24
SEQUENCE VII
La

CLEAR Z AND X. SET SELECT "P"

Ll

SET READ,

(S)-~~

Z

L2
L3
L4
L5

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4
L5
La
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "P", CLEAR WRITE

L4
L5

SET SA

4-33

CJP
OCTAL CODE: 25
SEQUENCE VII
LO

CLEAR Z AND X. SET SELECT "P"

Ll

SET READ, (S) -

.......~ Z

L2

L3

L4
LS
LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4
LS
LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "P", CLEAR WRITE

L4
LS

SET SA

4-34

OJP

OCTAL CODE: 26
SEQUENCE VII
LO

CLEAR Z AND X, SET SELECT "P"

Ll

SET READ, (S)-......
~ Z

L2
L3
L4

L5
LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4

L5
LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT~"P";'CLEAR WRITE

L4

L5

SET SA

4-35

PJP
OCTAL CODE: 27
SEQUENCE

LO

CLEAR Z AND X. SET SELECT "P"

Ll

SET READ, (8)

VU

• Z

L2
L3
L4
LS

LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
L5

LO
Ll

CLEAR HA

L2
La

SET HA, CLEAR SELECT

"~PIt,

CLEAR WRITE

L4
L5

SET SA

4-36

INT
OCTAL CODE: 30
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S", SET I/O PULSE

Ll

SET READ

L2

L3
L4
L5

CLEAR DESIGNATORS

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4

INPUT STROBE

L5
LO
Ll

CLR HA

L2

L3

SET HA CLEAR SELECT "S", (Z)--+X, CLEAR I/O PULSE, CLEAR WRITE

L4
L5

SET SA

4-37

INT
OCTAL CODE: 30
SEQUENCE VI

LO

CLEAR Z, SET SELECT "A"

Ll

SET READ

L2
L3
L4
LS
LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
LS

DL ----. DESIGNATOR

LO
Ll

CLEAR HA

L2
L3

SET HA. CLEAR SELECT "A". CLEAR WRITE

L4
LS

SET SA

4-38

ENL
OCTAL CODE: 32, 33
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "S"

Ll

SET READ

L2
L3
L4
L5

READ STROBE, CLEAR DESIGNATORS

LO
L1

CLEAR READ

L2
L3

SET WRITE

L4
L5

LO
Ll

CLEAR HA

L2

SET HA, CLEAR SELECT "S", CLEAR WRITE, (Z)---... X

4-39

ENL
OCTAL CODE: 32, 33
SEQUENCE VI
LO

CLEAR Z, SET SELECT "A"

Ll

SET READ

L2
L3
L4

LS
LO
Ll

CLEAR READ

L2
L3

SET WRITE
I

i .

L4

LS

DL---:~~DESIGNA TOR

LO
Ll

CLEAR HA

L2
L3
L

SET HA, CLEAR SELECT "A", CLEAR WRITE

4

LS

SET SA

4-40

OUT
OCTAL CODE: 34
SEQUENCE V
LO

CLEAR Z AND X. SET SELECT "A"

Ll

SET READ

L2

L3
L4

LS

READ STROBE, CLEAR DESIGNATORS

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4

LS
LO
Ll

CLEAR HA

L2

SET HA, CLEAR SELECT "A", CLEAR WRITE, Z

4-41

OUT
OCTAL CODE: 34
SEQUENCE VI
LO

CLEAR Z. SET SELECT "S". SET I/O PULSE

Ll

SET READ

L2

L3
L4

L5

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4

L5

DL~

DESIGNATOR

LO
CLR HA

SET HA C LEAR I/O PULSE, CLEAR SELECT "S", CLEAR WRITE

4-42

RJP

OCTAL CODE: 36
SEQUENCE V
LO

CLEAR Z AND X, SET SELECT "P"

Ll

SET READ

L2
L3
L4

L

S

READ STROBE

LO
L1

CLEAR READ

L2
L3

SET WRITE

L4

LS
LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT "P", CLEAR WRITE,

4-43

(Z)I--~.X

RJP

OCTAL CODE: 36
SEQUENCE VI

•

LO

CLEAR Z. SET SELECT "S"

Ll

SET READ

L2
La
L4
LS
LO
Ll

CLEAR READ

L2
La

SET WRITE

L4
LS
LO
Ll

CLEAR HA

L2
La

SET HA. CLEAR SELECT "S". CLEAR WRITE

L4
LS

SET SA

4-44

RJP

OCTAL CODE: 36
SEQUENCE VII

LO

CLEAR Z AND X, SET SELECT "P"

Ll

SET READ, (S) -.....;~~ Z

L2
L3
L

4

L5
LO
L1

CLEAR READ

L2
L3

SET WRITE

L4

L5
LO

Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT "P", CLEAR WRITE

L4

L5

SET SA

4-45

STL
OCTAL CODE: 37
SEQUENCE V

LO

CLEAR Z AND X. SET SELECT "A"

Ll

SET READ

L2

L3
L4
L5

READ STROBE, CLEAR DESIGNATORS

LO
Ll

CLEAR READ

L2

L3

SET WRITE

L4
L5

LO
Ll

CLEAR HA

L2

L3

SET HA, CLEAR SELECT "A", CLEAR WRITE, (Z)

4-46

~X

STL
OCTAL CODE: 37
SEQUENCE VI
LO

CLEAR Z, SET SELECT "S"

Ll

SET READ

L2
L3

L4
L5
LO
Ll

CLEAR READ

L2
L3

SET WRITE

L4
LS

DL----+ DESIGNATOR

LO
Ll

CLEAR HA

L2
L3

SET HA, CLEAR SELECT "S", CLEAR WRITE

L4
L5

SET SA

4-47

''This Page Intentionally Blank"

4-48

DUAL NAND
The dual NAND consists of two NAND circuits which are identical except for the number of input pins (see Figure 1-12). The two NANDS will be designated by the output
pin numbers 5 and 11. Side 11 will be discussed and related to side 5 later.
There are three types of inputs. Pins G, 7 and 8 are internal diode inputs, pin 9 is an
external diode input, and pin 4 is a special input which is normally connected to +6V.
As many input diodes as desired may be added to pin 9 to increase input capabilities.
If a logical one is applied to all used inputs the output on pin 11 will be a logical zero,
and conversely if a logical zero is applied to any input pin the output will be a logical
one.
The output of the NAND as described has current capabilities of driving a maximum of
ten inputs. If it is desired to drive more than this but less than 21, the current capabilities can be increased by adding a resistor from pin 9 to +6V. This in no way changes
the previously described operation; it only increases the fan out capability of the circuit.
Some of the circuits require one of the inputs to be from the master clock. Since the
master clock taps are +12V instead of +6V, it is necessary to connect this tap through
a dropping resistor to pin 9. When this is done pin 4 must be grounded. Since pin 4 is
common to both NAND circuits this ground puts a logical zero on the input of circuit 5.
To compensate for this a resistor must be placed from pin 3 to +6V. If it is desired to
enable both NANDS with the same master clock tap it can be done by connecting a resistor from pin 4 to this tap. Pin 4 would not be connected to +6V in this case. The
logical operation of circuit 5 is identical to the operation of circuit 11, except for the
change of pin numbers and the lack of the additional internal input diode.
MODIFIED DUAL NAND
The modified dual NAND is similar in operation to the NAND with the exception of a few
points (see Figure 1-13). Pins 11 and 12 are the outputs for their respective circuits.
Pins 1, 3, 6, and 7 are internal diode inputs and pins 2 and 8 are external diode inputs
for their circuits. Pin 13 is used for an additional group of inputs. To accomplish this,
an additional circuit, similar to the one between the base of the transistor and the input
pins 1, 2, 3, and 4 is connected to pin 13. The operation of pin 9 is the same. Pins 4
and 5 serve the same function as pin 4 in the non-modified dual NAND.

The only difference between the modified dual NAND and the slow NAND (Figure 1-14) is
the rise time of the circuit. As the name implies the slow NAND has a slower rise time
than the modified dual NAND. Otherwise its logic function is identical. Pin numbers
di ffer in the follOWing manner. Pin 1 of the slow NAND corresponds to pin 10 of the
modified NAND. 2 to 4, 3 to 2, 4 to 1 & 3, 5 to 12, 6 to 13, 7 to 5, 8 to 6 & 7, 9 to 8,
10 to 11 and pin 11 of the slow NAND to 9 of the modified NAND.

5-1

FLIP-FLOP
The logical operation of a flip-flop is as follows: Refer to Figure 1-15. We will start
by stating that neither of the B NANOS have all ones in. Therefore, both B NANOS will
have a logical one out. Note at this time that the output of All is fed back to the input
of A5 and the output of A5 to the input of All. This hookup makes it a flip-flop. We
can now see that if pin 2 of A5 and pin 7 of All are ones that the logical signal on AS
cannot equal the logical signal on All. Let's try and see why. If we assume both to
be a one, this means that All is a one. All is connected to AS pin 1, which would
also be a one. If AS pin 1 is a one and, as we stated, AS pin 2 was a one, this means
that all inputs to AS are logical ones and the output is then a zero. Also, if we assume
both AS and A 11 outputs to be zeros, then the zero on A 11 output would be connected to
A5 pin 1. which would cause a one at the output of AS. Now that we have seen that AS
and A 11 outputs cannot be the same, we can arbitrarily assume some logical signals on
them. We will assume AS output is a zero and All output is a one. The one from All
output is connected to the input pin 1 of A5 which in conjunction with pin 2 will hold the
zero at the output of A5, which is connected to input 6 of All, which holds the one on the
output of All, etc. We can now say that the flip-flop A is in a stable state.
There are only two ways to affect the state of this flip-flop. The first to be discussed
is to place a zero on one of the inputs of the side with the logical zero out. If we look
at Figure 1-1S again, this means we must put a logical zero on pin 2 of AS in order to
affect the flip-flop. This zero on pin 2 of AS will cause the output of AS to go to a
logical one. This logical one is then applied to pin 6 of All and in conjunction with the
one on pin 7 will cause a logical zero out of All. This zero at the output of All is then
applied to the input pin 1 of A5 holding the one at the output of A5. Now the input on pin
2 of A5 can go back to a logical one because pin 1 is now taking over. This entire flipping or changing state of the flip-flop from the zero appearing on pin 2 of AS until it is
stable in the flipped state took less than. 1usec.
The second method by which the flip-flop can be affected is by placing a ground or logical zero on the output of the side which is a logical one .. As one can see from the
schematics of the NAND circuit, a logical zero is created by grounding a point through
a transistor and it can also be seen that if a logical one and a zero attempt to appear on
the same point at the same time, the zero will be the resultant signal. Now, if we have
the flip-flop in our original state where A 11 output was a logical one and we put a zero
at this point, the zero is the resultant. This zero is applied to the input pin 1 of AS and
the circuit will flip as explained above because we have placed a zero on one input of
the side which has a zero output.
One of the stable states of the flip-flop will be called the set state and one the cleared
state. We will say that the set state is when AS output is a one. This means that the
cleared state is when All output is a one. This is just an arbitrary choice of the designer. Either state could be called set or cleared. It can now be seen that if we set
the flip-flop that AS output will be a one and A 11 output will be a zero, ami if We \,;I.ldd.£
the flip-flop that AS output will be a zero and All output will be a one. M~ny fHp .. fk;s
in the system have names such as the R flip-flop, SEL flip-flop, HIT flip-flop, etc,. Let
us call ours the CAT flip-flop. We will label the output lines of this flip-flop to give an

5-2

indication of the flip-flop's state. The label CA T means that this line will be a logical
one when the CAT flip-flop is set and the signal CAT will mean that this line will be a
logical one when the CAT flip-flop is not set or CAT means zero implies CAT flip-flop
set. This is because CAT and CAT must always be opposite.
As we mentioned before, pin 2 of A5 and pin 7 of All was one and was to control the
state of the CAT flip-flop. Again, referring to Figure 1-15, let us look at B5 and B1l.
It can be seen that the outputs of these NANDS will determine the state of the CAT flipflop. A zero on the output of B5 will insure that the CAT flip-flop is set and a zero on
the output of Bll will insure that the CAT flip-flop is cleared. Ones at their outputs
have no effect. Let us consider what it takes to get a zero at the output of a NAND.
The answer is all ones in. Now let us look at the input to B5. Pin 1 will be one when
the R flip-flop is set; pin 2 will be a one when the HIT flip-flop is not set (is cleared);
and pin 3 will be a one when the SEL flip-flop is set. Thus, we can tell what will set
the CAT flip-flop without looking any further than its input gating circuitry. Now let's
see what will clear it. The inputs to Bll are as follows: Pin 6 will be a one when the
W flip-flop is set; pin 7 will be a logical one during sequence VII; and pin 9 will be a one
if a jump condition has been met and we are doing a jump instruction. Of course, I know
these last two were not obvious but they do at least point out that a logical label can be
of a great assistance and that a logical label does not have to refer to a flip-flop state.

5-3

REGISTER TRANSFERS
Figure 1-16 shows two registers of three flip-flops each and associated gating circuitry.
Flip-flops A, B, and C are drawn as 3 flip-flops of the X register- bits 2, I, and 0 respectively. Flip-flops D, E, and Fare drawn as 3 flip-flops of the Z register- bits 2,
I, and 0 respectively. NANDS H, J, K, L, and M are the input gating circuitry for the
X register. A normal transfer from the Z register to the X register consists of first
clearing the X register (putting all the flip-flops in a predetermined state, in our case
the cleared state) and then setting those flip-flo~ith one input gate fully enabled.
Therefore the method used here will be for the CLR X signal to go to a logical zero and
then one of the signals (Z - X, Z - X, or Z - X) will go to a logical one. For this discussion we will assume that the Z register is set as follows. Flip-f!2P F set, flip-flop
E cleared, and flip-flop D set. This may also be expressed as Z2, Z I, and ZO being a
logical one. The first part of the transfer will be the clearing of the X register. This
is done by putting a logica 1 zero on the C LR X line. This logical zero is placed on one
'!!!puL£.f the clear side of each fl!Q,:flop iUhe X register. The X register is then in the
X2. Xl, XO state. That is X2, Xl, and XO are logical ones. Then one of the transfer
signals will go to a logical one. First we will assume that a direct Z - X transfer will
be done. This means that the Z - X line will go to a logical one. The others must remain a logical zero and the CLR X must have gone back to a logical one. The logical
one from Z - X will be presented to one input of each NAND Hll, JU, and Kll. Now
let's look at the other inputs to those NANDS. Hll has its other input a logical one because we originally stated that Z2 was set. Jll has its other input a logical zero and
Kll has its other input a logical one. These are also because of the original state of
the Z register. Hll and Kll have all used inputs a logical one and therefore their outputs will go to a logical zero. * The output of Hll and Kll going to a logical zero will
cause A and C flip-flops to set. (One may also find a flip-flop named for one of its
sides. That is the A flip-flop could also be called the X2 flip-flop no matter what its
state. One may see it said "the X2 flip-flop cleared or the X2 flip-flop set".) We now
have the X2 and XO flip-flops set. How about the Xl flip-flop. Remember we said that
Jll had one input a logical zero because of the Z register. This means that the output
of JU will be a logical one no matter what the other input does. The Xl flip-flop therefore could not be set. We now have the X register in the following state X2, Xl, and
XO a logical one. This is identical to the corresponding bits of the Z register. We
have therefore copied into or transferred into the X register the original contents of the
Z register. It is important to note that the transfer from one register to another does
not change the source register. The Z register being the source register still has its
original contents. Review this operation and make sure that you understand it as this
is one more of the basic building blocks in understanding the PRODAC 50 computer system.

*Remember that a logical one is +6V and a logical zero is OV or ground. If a logical
one and a logical zero are placed at the same point at the same time, the logical zero
will be the end result by grounding out the logical one.

5-4

Now we will call upon the knowledge gained in th~ip-flop and basic transfer writeups. Again assume the Z register is in the Z2, ~nd ZO state, with the Z - X
transfer signal back to a logical zero. Make the CLR X signal go to a logical zero
then back to a logical one. Now let the Z - X signal go from a logical zero to a logical one and back to a logical zero. While this signal was a logical one note the operation of NANDS H5, J5, and K5. J5 is the only one fully enabled, therefore Xl is the
only flip-flop to be set. Note that wherever a flip-flop of Z was set that the corresponding flip-flop of X is cleared and wherever a flip-flop of Z was cleared that the
corresponding flip-floQ. of X is set. This means that we have taken the complement of
Z to X. A s the name Z - X implies, transfer the cleared side of Z to the set side of
X or made the set s ide of X the same as the cleared side Z. Review this operation,
when it is fully understood, continue on.
Again assume the Z register in the Z2, ZI, ZO state-:. Let the CLR X signal go to a
logical zero then back to a logical one. Now let the Z - X signal (Z right shifted to X)
go to a logical one and back to a logical zero. Note the end result in the X register.
XO contains what ZI did. Xl contains what Z2 did. The line labeled "from Z3" means
that it comes from the set side of the Z3 flip-flop. (The word "from" will not appear in
the logics, it is used now for clarity.) This means that X2 will contain what Z3 did. As
an end result the Z register was transferred to the X register displaced one place to the
right or right shifted one place. Note that the ZO flip-flop in this figure goes no place.
If you can recall the RSH instruction the state of the ZO flip-flop will be transferred to
the "end around carry designator" flip-flop.

5-5

------------,

r-----

I

I

I

I
I
I

I
I

I

I

I

I

I

I
I
I
I
IL _______________ _

1
2

3

4T

Figure 1-12. Dual NAND

5-6

-----.

,----I

I

I

L _____________ _

I
I
J
10 G N O - - - - - - - - - - - -

1
13
-

1

3
2
4

T

Figure 1-13. Modified Dual NAND

5-7

5

21------.

,..-----( 7

3)------'

'------c 9

6}-----,.j

'---------4

GND

4

3

SN

'~6

L..-.

Figure 1-14. Slow NAND

5·8

11

R

1

CAT

B

2
SEL

3

__________
~6~-----W
VII

7

JUMP PERM

8

B

CAT
11,-----_.J

Figure 1-15.

5-9

CIix
FROM Z3

Db ....

~

o

Z2

H

~Z2
V"'"

tD-

~

L

E~

J

CD-

J

~
\..:..!I

L

~

~

~

~

F

~
~

Zo
K

...

F

~
~

0-

K ~
~

~

2--- X
Z_X

...

Z--- X
Figure 1-16.

5-10

M

X2

~

~X2
V
"'"

~

B~

if

Xl

8~
V

~

~

C~
:>c::'

Zo

....

~X,

-biZ,

E~

~

~

-

Zl

A

A

H ~
Q

r---

k"'\

0-_1

C

Xo

;J. Xo
~

"This Page Intentionally Blank"

5-11

1-15. CAPACITOR VALUE CODES
Voltage

Cl
C2
C3
C4
C5
C6
C7
C8
C9
CIO
Cll
Cl2
Cl3
Cl4
CIS
Cl6
C17
CIS
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43

. OOOS j.lF
. OOlS j.lF
.003 "F
.01"F
.02" F
.1 j.lF
.1 j.lF

SOV
SOOV
200V
100V
100V
100V
600V

742A976HOI
742A976H02
742A976H03
742A976H04
742A976H05
742A976H06
742A976H07

. 5 "F
2.0 "F
. 1 "F
. OS j.lF

200V
100V
50V
200V

742A976H31
742A976H09
742A976HIO
742A976Hll

---

---

3" F
IS j.lF
2S0 "F
100 "j.lF
820 j.lIjF
200 j.lIjF
300 j.lj.lF
.1 "F
2 "F
. Sj.lF
.33/-1F
.001 j.lF
S"F
10/-IF
2000 "F
500 j.lIjF
10 "F

100V
100V
40V
SOOV
100V
SOOV
200V
100V
100V
200V
200V
50V
100V
IOOV
50V
IkV
200V

742A976Hl2
742A976Hl3
742A976Hl4
742A976HIS
742A976H16
742A976Hl7
742A976Hl8
742A976H06
742A976H09
742A976H08
742A976Hl9
742A976H20
742A976H21
742A976H22
742A976H23
669A076HOI
743A035H04

---

---

1. 0 j.lF

200V
30V
200V
200V
IkV
25V
125V
250V
1kV
500V
35V
50V

669A077H08
669A093H02
669A077H05
743A035H03
669A076H02
669A094HOl
669AI03HOl
742A976H25
669A076H05
742A976H26
775A436H03
742A976H29

---

---

30 "F
0.1 j.lF
30/.lF
200 "/.IF
0.22/lF
200/.lF
IOO/lF
200/.lF
50 j.lIjF
27 "F
250 "F

r
,

Westinghouse Part No.

Capacitance

---

Capacitance

C44
C45
C46
C47
C48
C49
C50
C51
C52
C53

10 !AI' F
4.7/.1 F
0.4 7 /lF
10.0 ",F
O. 001 ",F
0.01 J.&F
0.05 ",F
0.1 ",F
0.5 ",F
22/.1F

Voltage
100V
35V
35V
50V
ZOOV
ZOOV
ZOO V
ZOOV
ZOOV
15V

Westinghouse Part No.
742A976H30
775A436H04
775A436H05
742A976H32
742A976H33
74ZA976H34
74ZA976H35
74ZA976H36
742A976H08
742A976H37

1-16. RESISTOR VALUE CODES

Code

---

Code

,'I

,

i
I
I

I
!i

i

---

(.

,
I

i\

,

i

!
,

(
I

I

,

1
I

I

i

I

1
I

(
f
,

i
I

I1

j
I

/
i

5-12

Code
Rl
R2
R3
R4
R5
R6
R7
R8
R9
RIO
Rll
R12
R13
R14
RI5
R16
R17
RI8
RI9
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
&11
R32
R33
R34
R35
R36
&17
R38
R39
R40
R41
R42
R43

Westinghouse Part No.

Ohms

Watts

Ik

30HZ
511n
68In
lk
1. Sk
2k
2.43k
3.01k
4.32k
4.99k
10k
13k
22.1k
15k
150n
18.2k
8.2Sk
lOOk
499k
1. 24M
2.49M
750n
12. lk

1/10
1/10
1/10
1/10
1/10
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2

---

---

22M
13.7k

1/2
1/2

742A97IH72
742A971H44

1. 5k

3.0Ik
4.32k
200
7.68k
432n
S1. In
6.19k
20n
100
35.7n
82.5n
loon
140n
200n
26HZ

---

742A969H02
742A969H03
742A969H04
742A969H05
742A969HOI
742A971H39
742A971Hll
742A97IH15
742A971H37
74ZA971H02
742A971HOI
742A971H03
742A971H04
742A97IH05
742A97IH06
742A97IHOA
742A971HO\)
742A971HI0
742A971H12
742A97IHI3
H2A97IH30
742A97IH31
742A971H32
742A971H33
742A971H34
742A971H3S
742A971H36
742A97IH41
742A971H43
742A971H47
742A97IH45
742A97lH07
742A971H46
742A97lH40
742A971H48
742A971H49
742A97IH70
742A971H7l
742A971H14
742A971H42

I

Code

Ohms

Watts

Westinghouse Part No.

R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87

510
lOOn
lk
7.5k
1000
Ion
400n
Ion
1k
2k
50n
1500
3000
400n
5000
7000
1800
250
200
1. 5k
4.5k
1000
2500
1500
5000

2
2
1/2
1/2
1
3
3
3
3
3
5
5
5
5
5
5
10
50
5
5
5
5
5
3
3

743A04lHOl
743A04lH02
742A971H30
742A971H38
742A972H01
742A973H01
742A973H03
742A973H02
742A973H04
742A973H05
742A974H01
742A974H03
742A974H04
742A974H05
742A974H06
742A974H07
742A975H01

R88

R89
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
RIot

---

---

1/4
400
1/4
1380
1/4
2.2k
1/4
8.66k
1/10
51.lk
1/10
lOOk
1/2
6.190
1/2
2.74k
1/2
51. 1k
1/2
43.2k
249k
1/-2
1/2
64.9k
1/2
24.9k
1/2
32.4k
1/2
121k
1/2
1. 21k
200,2PPMCo, + .01%
1/220k
1/2
40.2k
1/2
80.6k
3
6500
1/2
6040
1/2
1210
3
10, .05%
3
10,1.0%
3
33n
3
350
3
600
3
90n
1/2
49.9k
1/2
45.3k

I

--742A974H08
742A974H10
742A974Hll
742A974H02
742A974H09
742A973H06
742A973H07

--742A970H01
742A970H02
742A970H03
742A970H04
742A960H06
742A969H07
742A97IH16
742A971H50
742A97IH51
742A971H52
742A971H53
742A971H81
742A971H82
742A971H83
742A971H84
742A971H85
651A1l7H03
742A971H54
742A97IH55
742A971H56
742A973H10
742A971H17
742A971H18
",.,..."1'11."'""'1'11

Code
RlOl
RlO2
RlO3
RlO4
Rl05
R106
RlO7
R108
Rl09
RllO
RIll
Rll2
R1l3
Rl14
Rll5
RU6
R1l7
Rll8
R1l9
R120
R121
R122
R123
R124
R125
R126
R127
R128
R129
R130
R13l
R132
R133
R134
R135
R136
R137
R138
R139
R140
R14l
R142
R143
R144
R145
R146
R147
R148
R149
n"tl::n

.oi:t:u.t\.::J'un~.1

n.L~V

742A973H12
742A973H13
742A973H22
742A973H15
742A973H16
742A97lH19
742A97lH20

R15l
R152
R153
R154
R155
R156
R157

5-13

Ohms

Watts

30.lk
42.2k
56.2k
511k
2.0M
4.99k
10k
1k
1k
10k
12.lk
1. 5k
30k
470
68k
200k
4.7k
15k
lOOk
5.lk
120k
1.0M
2400
51k
27k
390k
150k
22k
2.1k
2.87k
249k
4700
200k
lk
1.0M
499k
lOOk
10M
24k
62k
1.1k
39k
20k
10k
40.2k
20k
4.42k
27.4k
300k

1/2
1/2
1/2
1/2
1
1/2
1/2
2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
10
1/2
1/2
3
1/2
1/2

.,,., .,1.
.1.~.

,LI\.

49.9~

2k
162k
150k
500
4.02k
8.06k

Westinghouse Part No.
742A971H21
742A971H22
742A971H23
742A971H24
742A972H02
742A971H36
742A971H41
743A041H04
669A007H02
669A007H03
669A007H04
669A007H05
669A007H06
669A007H07
669A007H08
669A007H09
669A007H10
669A007Hll
669A007H12
669A007H13
669A007H14
669A007H15
669A007H16
669A007H17
669A007H18
669A007H19
669A007H20
669A007H21
742A971H25
742A97IH26
742A971H27
669A007H22
742A971H28
742A97IH30
742A971H29
742A971H49
742A971H48
669A040HOI
669A007H23
669A007H24
669A007H25
669A007H26
669A007H27
669A007H03
742A971H55
742A971H54
742A97IH57
742A97IH58
669A007H28
742A971H42
742A971H19
742A975H04
742A97IH86
742A97IH87
742A973H14
742A971H59
742A971H60

Code

Ohms

Watts

R158
R159
R160
R1Bl
R162
R163
R164
R165
R166
R167
R168
R169
R170
Rl71
R172
R173
Rl74

16k
32.4k
255k
l27k
63.4k
32k
16k
8k
4k
2k
lk
500n
255k
l27k
63.4k
32k
16k

1/2
1/2
1/2
1/2
1/2
5
5
5
5
5
5
5
1/2
1/2
1/2
5

5

We8tinghouae Part No.
669A007H30
742A971H61
651A1l4H38
65IA1l4H37
65IA114H35
65IA1l6H12
651A116Hll
651A1l6HIO
65lA116H09
65lA1l6H08
65lA116H07
651A1l6H04
65IA1l4H38
65lA114H37
65lA114H35
65lA116H12
65lA1l6Hll

5-14

1-11. ZEIER DIODE YALUE CODES
Code.
Zl
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
ZIO
Zll
Z12
Zl3
Zl4
Zl5
Z16
Z17

Volts
4.3V

Westinghouse Part N;;-.-

8.2V
15V
16V
22V
2.7V
20V

743A004HOl
743AOO5HOl
743A006HOI
743AOO7HOI
743AOO8HOl
743AOO9HOl
743AOIOHOI
743AOllHOI

18V
lOV
5.6V
laV,50W
1.5V
24V
16V
7.5V

742A980HOI
743AOO2HOI
775A057HOI
743A087HOI
669A1l9HOI
669A089HOI
669A088HOI
669A302HOI

B.BV

---

---

P50
LOGIC DIAGRAMS

6-1

"This Page Intentionally Blank"

6-2

LIST OF DRAWINGS
Title

Dwg. No.

Page No.

867C217

PRODAC "50" Series - "M" Panel Card Listing &
Term Block Assignment

4-3

867C218

PRODAC "50" Series - "M" Panel (2PD) Peripheral
Drive Logic Schematic Diagram

4-4

867C219

PRODAC "50" Series - "M" Panel (1PU) Pull-Up
Resistor Logic Schematic Diagram

4-5

PRODAC "50" Series - "M" Panel (1AR) Automatic
Reset Logic Schematic

4-6

867C220
867C221
867C222
867C223
867C224
867C225
867C226
867C227
867C228
867C229
867C230
867C231
867C232
867C233
867C234

PRODAC 50 Bit 0 (2BC)

"M"

Panel Bit Card Logic Schematic
4-7

PRODAC 50 - I'M" Panel Bit Card Logic Schematic
Bit 1 (2BC)

4-8

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 2 (2BC)

4-9

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 3 (2BC)

4-10

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 4 (2BC)

4-11

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 5 (2BC)

4-12

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 6 (2BC)

4-13

PRODAC 50 Bit 7 (2BC)

"M" Panel

PRODAC 50 Bit 8 (2BC)

"M"

Bit Card Logic Schematic
4-14

Panel Bit Card Logic Schematic
4-15

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 9 (2BC)

4-16

PRODAC 50 - "M" Panel Bit Card Logic Schematic
Bit 10 (2BC)

4-17

PRODAC 50 Bit 11 (2BC)

"M"

PRODAC 50 Bit 12 (2BC)

"M" Panel

PRODAC 50 Bit 13 (2BC)

"M"

Panel Bit Card Logic Schematic
4-18
Bit Card Logic Schematic
4-19
Panel Bit Card Logic Schematic
4-20

6-3

LIST OF DRAWINGS (Cont)
Dwg. No.

.:!:ill!.

Page No •

867C235

PRODAC 50 Series - "M" Panel S Reg. Data
Transfer Logic Scheme (2ST)

4-21

867C236

PRODAC "50" Series Z - X Data Transfer Logic
Schematic (1ZX)

4-22

PRODAC "50" Series ''M'' Panel Timing Card
Logic Schematic (3TC)

4-23

PRODAC "50" Series - "M" Panel Designator
Card Logic Schematic (2DC)

4-24

PRODAC "50" Series - "M" Panel Sequence
Control - Card Logic Schematic (1SC)

4-25

PRODAC "50" Series - "M" Panel Instruction
Register Logic Schematic (2m)

4-26

PRODAC "50" Series - "M" Panel Int. Scan
Control Logic Schematic (2IC)

4-27

PRODAC "50" Series - "M" Panel Memory
Enable Logic Schematic (2ME)

4-28

PRODAC "50" Series - "M" Panel X-Even OneHalf Select-Logic Schematic (2HS)

4-29

PRODAC "50" Series - "M" Panel X-Odd OneHalf Select-Logic Schematic (2HS)

4-30

PRODAC "50" Series - "M" Panel Y-Even OneHalf Select-Logic Schematic (2HS)

4-31

PRODAC "50" Series - "M" Panel Y -Odd OneHalf Select-Logic Schematic (2HS)

4-32

PRODAC "50" Series - "M" Panel External Pulser
Logic Schematic (1EP)

4-33

PRODAC "50" Series - "M" Panel External Pulser
Logic Schematic (1EP)

4-34

PRODAC 50 Series "M" Panel (3EI) External
Interrupts 00 - 17 Logic Schematic

4-35

PRODAC 50 Series "M" Panel (3EI) External
Interrupts 20 - 37 Logic Schematic

4-36

PRODAC 50 Series "M" Panel (3EI) External
Interrupts 40 - 57 Logic Schematic

4-37

PRODAC 50 Series "M" Panel (3EI) External
Interrupts 60 - 77 Logic Schematic

4-38

867C237
867C238
867C239
867C240
867C241
867C242
867C243
867C244
867C245
867C246
867C247
867C248
867C249
867C250
867C251
867C252

6-4

LIST OF DRAWINGS (Cont)
Title

Dwg. No.

Page No.

867C253

PRODAC "50" Series - "M" Panel Stack 0
Memory Diode Logic Schematic (2MB)

4-39

867C254

PRODAC "50" Series "M" Panel Stack 0 Inhibit
Paddle Logic Diagram (3IP)

4-40

PRODAC "50" Series "M" Panel Stack 0 Memory
Diode Logic Schematic (2MA)

4-41

PRODAC 50 Series "M" Panel Stack 0 Sense
Amplifier Logic Schematic (1SA)

4-42

PRODAC "50" Series "M" Panel Stack 0 Core
Pulser Logic Schematic Diag. (2CP)

4-43

PRODAC "50" Series "M" Panel Stack 0 Core
Pulser Logic Schematic Diag. (2CP)

4-44

PRODAC "50" Series "M" Panel Stack 0 Core
Pulser Logic Schematic Diag. (2CP)

4-45

PRODAC "50" Series "M" Panel Stack 1 Core
Pulser Logic Schematic Diag. (2CP)

4-46

867C261

PRODAC "50" Series "M" Panel Stack 1 Core
Pulser Logic Schematic Diag. (2CP)

4-47

867C262

PRODAC "50" Series "M" Panel Stack 1 Core
Pulser Logic Schematic Diag. (2CP)

4-48

867C263

PRODAC 50 Series Stack 1 Sense Amplifier Logic
Schematic - ''M'' Panel (1SA)

4-49

867C264

PRODAC "50" Series "M" Panel Stack 1 Memory
Diode Logic Schematic (2MB)

4-50

PRODAC "50" Series "M" Panel Stack 1 Inhibit
Paddle Logic Diagram (3IP)

4-51

PRODAC "50" Series "M" Panel Stack 1 Memory
Diode Logic Schematic (2MA)

4-52

PRODAC "50" Series "M" Panel Stack 2 Memory
Diode Logic Schematic (2MB)

4-53

PRODAC !l50" Series - "M" Panel Stack 2 Inhibit
Paddle Logic Diagram (3IP)

4-54

867C255
867C256
867C257
867C258
867C259
867C260

867C265
867C266
867C267
867C268
867C269

PRODAC "50" Series

"M" Panel Stack 2 Memory

ninrlo .&.,J""OA.'-'
T .nrrin ..........
Qr,ho,"",,,,+i,..
I ')1\,{ A \
I..I. .........u,u. ........... \"'-I.UU""'1..1

't-OO

PRODAC 50 Series Stack 2 Sense Amplifier Logic
Schematic "M" Panel (1SA)

4-56

4,.11. _ _ _

867C270

6-5

A

......

LIST OF DRAWINGS (Cont)
Dwg. No.
867C271
867C272
867C273
867C274
867C275
867C276
867C277
867C278
867C279
867C280

Title

Page No.

PRODAC "50" Series "M" Panel Stack 2 Core
Pulser Logic Schematic Diag. (2CP)

4-57

PRODAC "50" Series "M" Panel Stack 2 Core
Pulser Logic Schematic Diag. (2CP)

4-58

PRODAC "50" Series "M" Panel Stack 2 Core
Pulser Logic Schematic Diag. (2CP)

4-59

PRODAC "50" Series "M" Panel Stack 3 Core
Pulser Logic Schematic Diag. (2CP)

4-60

PRODAC "50" Series ''M'' Panel Stack 3 Core
Pulser Logic Schematic Diag. (2CP)

4-61

PRODAC "50" Series "M" Panel Stack 3 Core
Pulser Logic Schematic Diag. (2CP)

4-62

PRODAC 50 Series Stack 3 Sense Amplifier
Logic Schematic "M" Panel (lSA)

4-63

PRODAC "50" Series "M" Panel Stack 3 Memory
Diode Logic Schematic (2MB)

4-64

PRODAC "50" Series "M" Panel Stack 3 Inhibit
Paddle Logic Diagram (3IP)

4-65

PRODAC "50" Series "M" Panel Stack 3 Memory
Diode Logic Schematic (2MA)

4-66

6-6

The following notes define the majority of the symbology used with the logic diagrams.
(See Figure 4-1.)
NOTE 1.

Indicates a connection on this card to another point labeled with the same
mnemonic. This signal originates on this card.

NOTE 2.

Indicates a connection on this card to another point labeled with the same
mnemonic. This signal originates off this card.

NOTE 3.

Indicates the operation which takes place when this point is a logical one.

NOTE 4.

Indicates the card to which the point goes or from which it comes.

NOTE 5.

Indicates the connector and pin to which the point goes or from which it
comes.

NOTE 6.

Indicates the number of points to which this point is connected.

NOTE 7.

Indicates connector and pin. (Connector A12, pin J.)

NOTE 8.

Indicates twisted pair cable.

NOTE 9.

Indicates the tab number on the wiring side of the board. The tabs are on
the outside edge of the board, are equally spaced and labeled 1-7 starting
at the bottom.

NOTE 10.

Indicates the tab number on the component side of the board.

NOTE 11.

Indicates to which indicator logic circuit the point is connected. A logical
one at this point turns the indicator on. The indicators are on the outside
edge of the board, are equally spaced and are labeled 1-6 starting at the
bottom.

NOTE 12.

Indicates the connector and pin on this board.

6-7

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MEMORY DIODE LOGIC ::SCHEMATIC (2 MA)
Reference 867 C 280 - E 16

THE INTERRUPT SUBSYSTEM
GE~ERAL

CHARACTERISTICS

Interrupt Defined
The Interrupt subsystem is the means by which a plant contact, a peripheral unit, or an external
signal can call up directly a program in core. The subsystem is organized on a priority basis
so that more important Interrupt inputs are scanned more frequently.
Interrupt Circuit
The Interrupt subsystem uses a saturating core buffer storage element for each interrupt input.
Sixteen of these storage elements are located on each EI card.
A maximum of four cards can be used to bring the system up to its full capacity of 64 interrupts.
Operation of Interrupt Subsystem
Operation of the subsystem is as follows: Each sequence III the computer generates a probe
pulse which checks the state of the interrupt input contact closures or signals. If a contact
closure is present and the Interrupt core has not been previously set, a four-layer diode is
triggered, and energy is dumped from a capaCitor through a winding on the saturating core .
.\s the core switches a signal is supported on a secondary winding called a "Hit" signal. The
Hit signJI sets a flip-flop. If the computer is not rW1ning wlder lockout, it completes its current instruction, then enters sequence 1, which is the Interrupt scan. Successively the computer routes a pulse through each of the Interrupt cores until a response voltage is generated,
and the lockout flip-flop is set. The computer then goes to the location identified with the particular core last scanned and does the instruction in that location.
After the particular program called out has been run, the program will clear the lockout flipflop and the Interrupt scan will once again begin to find lower priority inputs or other high
priority interrupts which may have been set while the computer was running under lockout.
When the scan is completed without finding a core previously set and able to trigger the Lockout flip-flop, the computer will execute the next instruction as indicated by the program counter.
Block Diagram
A block diagram showing the Interrupt Subsystem is given in Figure 1-20. An interrupt is brought
into the computer in two steps. First, the input voltage must rise to a sufficient level so that
the Interrupt core can be set during probe time. When the core is set, a pulse is generated
which sets the Hit flip-flop. Second. the computer must scan the Interrupt cores until a response voltage sets the Lockout flip-flop. The computer will then execute the instruction in
the location associated with the last core to be interrogated.

7-1

------...,

....

CONTACT
CLOSURES..

-

I
16
FILTERS

uNFILTERED
INPUTS

I
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CONTACT
CLOSURES..

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FILTERS

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60-77

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40-57

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PROBE
EXTERNAL
PULSER
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INTERROGATE
EXTERNAL
PULSER
EP

Figure 1-20. Interrupt Subsystem Block Diagram

7-2

SEQt;EI"CE I DETAILS
Description of Sequence I
A flow diagram of Sequence I is shown in Figure 1-22. At the end of each instruction the Interrupt
Lockout flip-flop is tested. If Lockout is set. the machine immediately proceeds to Sequence II.
If lockout is not set. the Hit flip-flop is tested. If there has been no hit, the computer moves
into Sequence II. If there has been a hit. the S register is cleared, and Sequence I is entered.
Before the end of each Sequence I. the S register is incremented. and the Interrupt is checked.
If Interrupt Lockout has been set by the response voltage from an interrogate pulse, Sequence

III will be entered. and the core location will be accessed as determined by the contents of the
S register. If the Interrupt Lockout is not set. a check will be made to determine whether the
scan has completed interrogation of 64 cores. If not, Sequence I will repeat.
An interrupt occurs in the central processor when the "Hit" flip-flop is set. An interrogate
inte rrupt address scan is initiated and proceeds at a rate of 1. 5 microseconds per address.
The scan always starts interrogation with address 01 and proceeds to interrogate addresses
02. 03. 04 . . . . n. where n is the address of the interrupt input which has occurred. When n is
identified the scanning stops. the memory device containing n is reset, no other interrupts are
permitted. and the central processor is caused to execute an instruction in the core memory
location corresponding to n (64 core locations, one for each interrupt input address).
Generally the instructions so executed will be a Return Jump, which stores the location of the
last instruction of the interrupted program, and initiates a new program. Thus any of 64 new
programs may be initiated without losing track of the interrupted program.
It is important to note here that the interrupt unit is locked out when interrupt input address
scan is initiated. It is necessary to clear interrupt lockout to recognize concurrent and future

interrupt inputs. Figure 1-21 shows the interrogate interrupt input scan timing. Note that the
"Hit" flip-flop remains set (scan continues) until last available address is interrogated.

START INTERRUPT
INTERROGATE SCAN
1 .5~S
HIT

I

1-

t1

tct14

t I

13 . 5.;USEC..401 02 03 04 S
MINIMUM

r-

CLEAR
HIT

••••

CHt

#~

Figure 1-21. Timing - Interrupt Interrogate

7-3

START

IS tL
SET?

NO
HAS THERE BEEN
A
HIT?

yES

CLR S

DO SEQ I
(A RESPONSE
VOLTAGE SETS IL)

IS IL
SET?

NO

I S SCAN
COMPLETE?

YES
CLR HIT

NO

Figure 1-22. Interrupt Scan Flow Diagram

7-4

USE OF

I~TEHRL'PT

Ir-;PUTS

As previously noted. interrupt inputs are used to obtain central processor attention. In the
absence of interrupt input signals. the central processor proceeds completely unaware of the
'peripheral equipment associated with these input; consequently programming time normally
required for monitoring purposes is reduced. In contrast. however. half the available interrupt
inputs. on the average, must be scanned to locate an active one; therefore it is desirable to
keep the number of interrupt inputs provided small. Average scan times are 36, 72, 108, and
144 microseconds, corresponding to the quantity of interrupts optionally available: 16. 32, 48,
and 64. Examples follow of how interrupt inputs are used.
I/O Hequest
There is a finite time necessary for the peripheral system to react to a function given it by a
central processor. If the function is to output. prerequisite to that output is knowledge that the
peripheral system is not busy. hence ready to accept the output. If the function is an input,
prerequisite to the input is data preparation and presentation for input. An interrupt input may
be used in each case (output request. input request) to notify the central processor that the
peripheral system is ready and can be committed to function.
Process Events
In application. whether for monitoring or for monitoring and controlling a process. an interrupt
input may be used to define a particular time in the process which is critical to It. This time
may be an incremental gate for the error signal to the computer as a direct digital controller,
it may be a Emit detector for temperature or level alarms, or it may define sequence in open
loop control.
A void Over Use
In considering particular system interrupt input number and repetItion rate requirements, both
"hardware" and "software" restraints must be taken into account. The hardware presents an
absolute maximum system capahlllty (i.e., 64 inputs per maximum system). The address mterrogation scan always starts with address 01 and proceeds to interrogate addresses 02, 03,
.... n, where n is the address of the interrupt which has occurred; consequently, there is a
pri( lrity of interrupt input assignment to be considered.
Pre gramming limits the interrupt input repetition rate because some programmed routines
are executed under interrupt lockout. When interrupt lockout is set, the central processor
wil not accept additional interrupts. It will store any interrupts that occur during lockout,
and will accept them after lockout is cleared. However, if two or more interrupts occur on
anyone input during a continuous lockout. the central processor will recognize them as a single interrupt.
Filtering :\ vailable
Several interrupt input filter modules are available to provide interface between plant signals
and the central processor interrupt input module. Sixteen inputs are provided for on one module. Interrupt rates, exclusive of programming constraints (charge and discharge time constants consideration). range from 15 interrupts per second to 200 interrupts per second.

7-5

USE OF MEMORY

Program Origins
The 64 interrupts access core location 00001 through 00100. The highest priority interrupt
instruction should be entered in 00001; the lowest, in 00100.
Automatic Selection of Origin
The computer responds to an interrupt and immediately accesses the corresponding core location, and does the instruction in that location without modifying P.
:\ voidance of P
The program counter location is not disturbed during an Interrupt scan.
Use of RJP. Y. I
H.eturn Jump Indirect is typically stored in the Interrupt location to transfer control to a predetermined location and to save the P register contents. These predetermined locations are
contained in addresses 00102 to 00201. For example, the P register is saved in the location
that is in 00102 when the Interrupt comes into location 00001. The computer jumps to the next
instruction called out by the 00102 address.
Shown below is a typical program accessed by interrupts showing Return Jump Indirect to a
"link" location, storing of P, DeSignator and Accumulator, running of program, retrieving of
Accumulator and Designator information of interrupted program, and CLJ Indirect to location
containing P to end lockout operation and return to interrupted program:
LOC.
1

102

INSTR.

FUNCTION

RJP 101+1, I

Transfer to predetermined location and store program

5000

Transfer address for interrupt 10
Storage location for contents of P Register at time of interrupt

5000
SDR A

Save registers for restart
STL B
Execution of function requested by this interrupt
ENL B
Reload registers for restart
EDRA
CLJ 5000,1

Release lockout and transfer control to interrupted program

Use of CLJ, 0, I and CLJ
Clear Lockout Jump Indirect to P (CLJ, 0, I) stored in an Interrupt location to ignore an interrupt and return to the program that was interrupted.
Clear Lockout Jump (CLJ) is used any time the programmer wishes to end operation under
lockout.

7-6

ADDING INTERRUPTS IN THE FIELD
Location of Cards
The EI Interrupt cards are located in slots CI3, CI4, C15, and C16. When using only one card
in a system, the 3EI card should be located in slot C 13. When adding cards to the system, the
cards should be located in slots CH, C15, and C16 in that order.
:\lodification of Scan Termination
When only one EI card is used, the scan should end after 16 cores are terminated. When four
EI cards are used, the termination should be altered to include 64 cores In the scan. Instructions for altering the termination are given on the IC Interrupt Scan Control Logic schematic.
Options
Options of 16, 32, 48, and 64 interrupt inputs are available in the system. The unit may expand
in groups of 16 inputs. Required to add a group is;
1.
2.

3.
4.

One central processor interrupt input module
One or two interrupt filter modules for each type of filter required
One cable to connect central processor interrupt input module to the interrupt filter
module
One cable to connect each interrupt filter module to standard termination areas.
These cables will contain necessary terminal hardware to complete the assembly.

Interrupt Assignments - Standard
The following interrupts will execute out-of-sequence the instruction in the corresponding core
location for any P-50 series computer. Of course these are only suggested as standard; each
system is designed to the user's specifications.
Interrupt
Number

o
I
2

3
4

5
6

7
10
11

12

Interrupt
Power Supply Failure
Analog Conversion Complete
Real Time Clock (Sync.)
Contact Closure Input Read
Contact Closure Input Complete
High Speed Punch Complete
High Speed Reader Complete
ASR Input Complete
ASR Output Complete
Contact Closure Output Complete
Logger Complete.

Core
Location
01
02
03
04
05
06
07
10
11
12
13

Other interrupts such as extra loggers, punches, readers. and process interrupts will follow
the above in a preferred order.

7-7

TIMING CHART
The timing chart for Sequence I, which is the Interrupt scan Interrogate cycle, is shown in
Figure 1-23.

o

.3

.6

1.2

J

1.5 0

I

f4- La

L1

~

L.

L2

L3

I--Lo f--.

L4 ...
~

1st Time
Only
CLR S (0)
CLR S (1)
CLRX
I

CLR Z

I

CLR FB - F13

I

SELS
Response Voltage
CLAMP XO

I

I

EI PULSE
ADD-+SO - S7
ADD ..... SB - S13
S ..... Z
INH READ" WRITE
PULSERS

,
,
---[
~

T

I

Figure 1-23. Sequence I Timing Chart

7-8

LS-'

I/~

DRIVER PANEL

D PANEL

1~02

GENERAL DESCRIPTION
The I/~ driver panel has card slot capability for translating half select lines and
1/0 data lines originating on the P-50 main frames or P-550 "T" panels to word
and channel drive lines for either CCO or CCI multiplex xchemes. It also has
channel driver capability for l/cJ devices such as the high speed reader, punch,
ASR, and Selectric typewriter.
CIRCUIT OPERATION
Circuit operation is best explained by defining the back panel wiring layout in conjunction with the data lines from the computer main frame.
Each slot of the I/O driver panel from slot 1 to 14 is buss wired with I/O data Input
and Output lines brought in on connector 21 or 23. Each slot then has an individual
half select line brought in from connector 22 or 24 which serves as its own channel
address. With the wiring so commoned any card which requires any of the above
data can be interchanged and used in any of the 14 slots. The following is a list of
the cards that can be used:
RB, DE, SL, TS, TN, TO, 4IF, PSS, CD, CB
The two slots 15-16 are wired for word drivers with 16 half select lines per slot.
A specific addressing scheme exists and is shown on the attached block diagram.
There are a total of 4 "D" panels with addressing as shown. No word driver
capability is available on D3 and D4 but the slots are wired for power.
There are two cards which can be used in any slot of the panel and these are the 4IF
and the PSS. The reason is that they require no back panel wiring in the case of the
41F or only power in the case of the PSS.
Interrupt wiring needed on many of the cards used in this panel is made on card edge
connectors with separate cables and have no connection to the panel.
The 56 pin EIco connectors 21 and 23 are wired exactly alike and act as termination
point from the computer or T-panel and is a transfer point to other "D" or "A"
panels. The same is true of connectors 22 and 24.

8-1

MULTIPLEX
ADDRESSING

(")

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WORD

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ONLY

60-77

20-37

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40-51

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13

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72

52

32

12

CHN

71

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31

11

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50

30

10

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67

47

27

7

CHN

66

46

26

6

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65

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5

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6-1

44

24

4

CHN

63

43

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3

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62

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NON-MULTIPLEXED CONTACT CLOSURE INPUT SUBSYSTEM

I.

GENERAL DESCRIPTION
A.

Non-multiplexed contact closure inputs (CCI) provide a fast means of entering 14
bits of data simultaneously into the computer. This is done by means of a Cnntact Buffer (Cn) card located in a D panel. There is a maximum of 14 CB carcl~
allowed per panel with a maximum of four panels assigned to a central processor
interface unit.
Figure 1 is a hlock diagram of the non-multiplexed CCI sub-system.

-

48/125V

+

rio
DATA
E
HALF
SELECT

INTERRUPTS

I

TERM I NAL
BLOCKS

01

I
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D3

14 PLANT CONTACTS OR
OTHER ON-OFF DEVICES
PER CB MODULE
14 CB PER PANEL

I
L __04.-1
1/0

INTERFACE

o PNL
UP TO 4 PANELS

l'\(JN-MULTIPLEXED CCI
Figure 1

B.

Non-multiplexed eCI may be used in a variety of applications such as detecting
process contact closures, computer-to-computer communication, sequence -of-

9-1

("'cnts recording and telemetry data collection. The first application above is the
more general one, and win be discussed below. The latter three functions are
similar, but for special applications.
Il.

~PF.ITFTCATIONS

Tni111t nequirements
('1\ cards to monitor process contact closures operate with inputs of 48 VDC or 125VDC.
A -t >\\'nC source is supplied with the computer. 125VDC may be supplied with the
.systf'm or it may be supplied by the computer user. The supply should not vary more

than! 101';; the capacity of the supply depends on the number of CCl's being driven, and
othC'r loads on the supply.
ndcrcnce CB printed circuit card description for voltages required on the different
cn en reis.
JII.

em n TIT

OPE M TION

In the general application of detecting the status of process contacts, the nonmultiplexed eCl circuits are operated in the open-loop mode. No timing adjustmC'nts are required.

eel scan frequency is a function of (1) filter charge-discharge times and (2) programming. On both the 2CB4 (48V) and the 2CB6 (125V) cards, the charge time
for the filter is approximately 0.80 milliseconds, and the discharge time for the
filter capacitor is approximately 4.!'iO milliseconds. Both of these values are
worst case figures for must-operate conditions. These charge-discharge periods
indicate the maximum rate at which the inputs will follow the change in status of
plant contacts. Software then initiates scanning of the inputs at appropriate interVJls as required by the process. 14 bits of data (corresponding to the 14 process
contacts tied to one CB card) are taken into the computer on the execution of an
input command. The channel is addressed with the low order six bits of the instruction word specifying the channel number.
n.

Circuit Description
Figure 2 is a simplified portion of a non-multiplexed CCl subsystem. It is one of
fourteen stages on a CR card. The channel address shown for this card is channel
:17, and the input data hit is number 13. If the plant contact, PC. is closed and
the voltage V, is impressed across X19 and X3 charging capacitor C, input data
hit l:l will present a "1" to the l/g interface when an input command is transmitted
over channel 37. If the plant contact is open, capacitor C will be discharged
through resistor R. Then when transformer Xl is pulsed through the action of the

9-2

r---------:L3
I/O
DATA
A12*
AIO**

~

I

I

AAAi

X2 X 1 X19'

I

,I
~

I
c,.,

-V

I
1

HALF
SELECTS
AIO*
AI2**

,

PLANT
CONTACT
(PC)

I

X4 X3

YY

I/O
ASSUME CHAN
INTERFACE
ADDRESS 37
.:: 1'50 CONNECTOR INPUT DATA BIT 13
:'c:,:p 550 CONN ECTO R

I
I

I
CB
I
L - - _ _ _ _ _ _ _ -.-l

V WILL BE 48 OR 125 V
DEPENDING UPON
CB MODULE USED.

SIMPLIFIED SCHEMA TIC RE PRESENTA TIVE OF 1-1 SThIILAR STAGES ON CB CARD.
PLANT CONTACT IS SHOWN
ADDRESS IS CHANNEL 37. INPl1T DA TA BIT 13.

Figure 2

half-select circuits. capacitor C w111 short out the transfnrmp.r. and a "0" will be
presented to the rio interface on the input data lines.

9-4

v.

CONNECTORS & TERMINATIONS
A.

Connector Breakdown I/O Interface Data
Note: This breakdown applies to the P50 Interface plug A12 or the P550
Interface plug Al O.

56 PIN ELCO
A.

B
C
D
E
F
H
J

K
L
M
N
P
R
S
T
U

V
W
X
Y

Z

a
b

c
d

e
f

56 PIN ELCO

DESIGNATION

h
j
k
1

IDO
IDRO
IDI
IDRI
I D2
IDR2
I D6
I D3
IDR3
ID4
IDR4
I D5
IDR5
ID7
IDR7
IDRD
I D8
IDR8
ID9
IDR9
I D1 0
IDR10
I Dll
IDR11
ID12
IDR12
I D13
ODR13

m
n
P
r

s
t
u

v
w
x
Y

z
AA
BB
CC
DD
EE
FF
HH
JJ

KK
LL
MM
NN

9-5

DESIGNATION
IOR13
0013
ODR12
0012
OOR 11
ODll
ODRI0
ODI0
ODR 9
OD 9
ODR 8
OD 8
ODR 6
ODR 7
00 7

ODR
OD
ODR
OD
ODR
OD
OD
ODR
OD
ODR
OD
ODR
OD

5
5
4
4

3
3
6
2
2
1
1
0
0

n.

Cnnnector Breakdown T/O Interface Half Select
~ntc:

Thi s breakdo\\l'l applies to the P!iO interface plug A 10 or the P550 interface
plug A12.

56 PIN ELCO
A
B
C
D
E
F
H
,J
L
M

56 PIN ElCO

DESIGNATION

0rarao

v

ra~01

I'i

IHl0 2
0003
0000
0010

x

7"""
6"""
50"0

Y

4{1 {I {I

z

AA

BB
CC
EE
FF
HH

~020

0030
"004
0~05

N
P

0006
0007

JJ

R

0~40
005~

KK
lL

0060
0070

MM

S
T
u

C.

DESIGNATION

NN

"7""
1!l6QJ0
05"0
04""
3"000
200"
UHl0
0000

o3(U

0200
010 0
00"0

Terminations
Drawing fi098977 sheets 1 and 2 define the terminations available for the nonmultiplexed CCI system.
Connectors J. K. Land M are the Curtis Terminal Blocks. this is the most
commonly used type. however. these can be Rowan blocks which have the same
terminal markings or they can be Elco connectors as shown in the drawing.

9-6

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LI----·:

CONTACT CLOS{:RE O{'TP{:T SUBSYSTEM

I.

GENERA L DESCRIPTION

The contact closur£' output CC(») suh-svstem provides comput£'r cnntrol\cn clcctri(,:lll\' isolatcn relav contacts for the control of equipment ann ncvices locatcd external
to the computer. A few examples of the manv uses for ('ontact closure outputs are
listen below:
1.

ceo's may he used singly or in groups to communicate with operating
personnel by means of lights, buzzers, alarm horns, and digital displays.

2.

ceo's may be used to initiate the action of plant or process devices such as
motors and valve positioners.

3.

ceo's may be used to sequence a number of plant or process devices by
initiating actions in a particular order and for specific times.

-t.

CC0's may he used in combination with stepping motors or resistance networks to provide the computer with an analog output capability.

Owing to the wide range of possible applications, power for the operation of devices
from ceo's must always be supplied externally to the ceo sub-system.
The contact closure output sUb-system consists of ceo point relay cards which are
located on one or more X-panels, along with word and channel drive circuitry which
resides on printed circuit cards located in aD-panel. CCa point relays are bistable
(latching), so both set and reset drive circuitry is required.
Figure 1a is a block rJiagram of a CC~ sub-system containing 224 individual point relays. One word driver printed circuit card and two channel driver printed circuit
cards are required to select and energize the proper relays. One power supply
switch printed circuit card is required for timing. A single CC0 point card contains
seven relays, so that one full X-panel of CCa cards will contain 16 x 7" 112 CCa
point relays. By adding a second X-panel a total of 224 points can be obtained withput additional drive circuitry.
To expand a system to have between 225 and 448 ceo point relays, an additional word
driver must be added, as weB as additional X-panels. Refer to Figure Ib for the
block diagram of a 448 point system.
By adding two channel drivers. up to 896 ceo point relays may be used.
figure lc for the block diagram of an 896 point system.

Refer to

The greatest number of ceo points available as a catalog standard is 896, although
larger numbers can be obtained as a special item.

10-1

Connections To Plur.t
D-Panel
Channel
And
Word
Sel ect i on
(Hal f-Sel ects)
~

~

......
o
I

Output
Data

~

I:\:)

~

L,.

Interrupts

I/O
Inlerface

t

1

Termi na L
Or
Connection

Termi nah
Or .
Connections

-

CD Set Channel
Driver Printed
Circuit Card

--

--

CD Reset Channel
Driver Printed
Circuil Card
WD Word Driver
Printed Circuit
Card

-..

l

PS Power Supply
Swi tch Pri nted
Circuit Card

Driver
Panel

CC~ SUB-8YSTEM OF 224 POINTS

Ftpre 1.

--First
X-Panel
112 CC9
Point
Relays

--

Second
X-Pane I
112 CC~

Point
Relay~

~

t

D-P.nel
Chllnnel
And
Word
Sel4Ktion
(Hal f··Selects)

.
~

.....
o

CO Set Ch.nnel
Driver Printed
Cir~ult Card

~

CD Reset Channel
Driver Printed
Clr~ult Card

~

~

WI) Word Driver
Printed CI r~ul t
C.rd

~

Interrupts
110
I nterf.~e

Driver
P.nel

Terminals
Or

Conne~tors

Conne~tors

--eo
First
X-Panel

Se~ond

------

X-Panel

Thi rd
X-Panel

"2 CC.

"2 cCf

r

fe

~~

Word Drl ver
Printed Clr~uit
C.rd
PS Power Supply
Swl tch Printed
Ci r~ul t Card

I.e

t

t

Teminals
Or

Tertlln."
Or
Connectors

WI)

~

Devl~e5

•
112 CC'

~

To Pl.nt Or Process

j

Tenlln."
Or
Connectors

I
C.:J

Output
IDau

Conne~tlons

ceo SUB-SYSTEM OF 448
Figure Ib

POINTS

~

r----

Fourth
X-Panel
112 CC.

r-

,

Connections To Plant Or Process Devices

•

f
o-Penel

,.

Channel
And
Word
Selection
(Hal'-5elecu)

CD Set Chennel
Driver Printed
CI rcul t Cerd

Output
Det •

CD Reset Chennel
Driver Printed
Circuit Card

~

WI) Word Drl ver
Printed Circuit

~

WD Word Driver
Printed Circuit

Termlnels
Dr
Connectors

Terminals
Or
Connectors

2nd
X-Penel

)rd
X-Penel

112 CC.

f----

cct

112 CC'

•

Terminals
Or
Connectors
~

~

1st
X-Penel

~

....
o

Termlnels
Dr
c.......... tors

112

4th
X-Penel

---

112 CC.

1

....r

!

~

CD Set Chennel
Driver Printed
Circuit Card

~

CD Reset Channel
Driver Printed
Circuit Cerd

5th
X-Penel

~

112

112 CC.

Interrupts

110

Interfac:e

'-

PS Power Supply
Swl tdl Prj nted
CI rcul t Card

6th
X-Penel

•

Terml nels
Or
Connectors

•

I--

8th
X-Panel

ttz cct

112 CC'

I--

,

Termlnels
Or
Connectors

Connections To Plant Or Process Devices

SUB-SYSTEM OF 896 POINTS

FIgure Ie

X-Panel

~

Driver
P..,el

ceo

cct

r--TeMIIlnal s
Or
Connectors

~

7th

Termi nels
Or
Connectors

l

n.

SPECIFICATIONS
A.

Input Requirements - As with all other sub-systems, the CC0 sub-system interface with the computer central processor itself is via computer word and channel
selection circuitry. The only inP!lts to the ceO subsystem are from these computer I/0 interface circuits.

B.

Contact Specifications - All outputs from the CC0 subsystem are via electrically
isolated mercury wetted relay cootacts. Each relay contact is a bounce free,
form D, "make-before4reak" type having a normally open contact (N0), a
normally closed contact (NC) and an armature (A). The open contact will close
before the closed contact opens. The "bridging" time, or time during which both
contacts are closed, is approximately O. 1 milliseconds.
Each individual relay cootact in the CC0 sub-system is provided with an R-C
contact protection circuit. Figure 2 illustrates the range of safe operating loads
which can be tolerated without additional contact protection external to the CC(2j
sub-system. Reliable, long-life operation will result provided that the current
through the contacts just prior to opening and the peak voltage across the coota.cts
as they open both lie within the shaded area of Figure 2. Switching of inductive
loads such as small low energy relay coils (10 volt-amperes or less) at supply
voltages in the 24 to 120 volt D. C. or A. C. RMS range will not generally result in
transient voltages exceeding that of Figure 2. However, larger inductive loads
must have additional remote protective circuits for limiting the inductive energy
to the relay cmtacts. Diode clamps arOlmd all D. C. inductive loads are recommended as good general practice.
When using contact outputs to control AC devices. it must be remembered that
a small amount of leakage current due to the R-C suppressor circuit will be present when the contacts are open. Refer to 2C(2j printed circuit module description
for more details concerning the leakage current.

10-5

....o

- .SA
>
o
ex:>

Ul

.!!Q)
c: ~
o 0-

Us

.... <
<
.... c:

>

o
o

"'"

c:-

Q)

I

-.3A

r..
r..

::I

U

Vol tage Across

Contact~

At Rupture In Val

t~

CCO RElAY CONTACT RATINGS
Figure 2
C.

Output rates and timing - Contact closure output relays are grouped Into registers
of fourteen. Outputs occur under program control one register at a time, so that
the states of all fourteen relays within a given register can be changed simultaneously. Once set, a relay will remain set until another output causes it to be
cleared. Within a given register, one or more relays may be set, cleared, or remain unchanged when an output occurs. Five milliseconds must elapse between
outputs of individual registers to allow for relay settling times and program response time. Thus, outputs can occur at a maximum rate of 200 registers per
second, and since one register contains fourteen relays this is equivalent to 2800
individual contact output points per second. This speCification holds provided no
attempt is made to change the state of any particular one of the relays more often
than once every ten milliseconds.
In actual practice, output rates will vary and will be dependent upon program con-

trol.
HI.

CIRCUIT OPERA TION
A.

Functional Description
Contact closure output relays are combined in groups of fourteen, with each group
of fourteen being referred to as a contact output "register". Outputs occur one

10-6

regiRter at a time. so that the state of all fourteen relays within a register can he
changed simultaneously. Each register has a word arlrtrcss and a channel address.
or more precisely a SET channel address and a RESET channel address. Thus. a
particular register is uniquely defined bv the specification of two numhers. a
word and a channel address. Any output on a computer channel must he accompanied bv a fourteen bit "data word". Corresponding to each bit of the output
data is one of the fourteen relays within the CC(I') register. Thus a particular
CC() relay is uniquely defined by the specification of three numbers. a word and
a channel and a bit.
The following example shows the state of a relay register before and after an output. along with the data word which caused the change. Note that for each bit of
the data word which is a one, a corresponding relay is set. and for each bit which
is a zero. a relay is reset. The final state of the CC~ relay register does not
depend on its initial state, but depends only on the output data. When both ones
and zeros are transferred, it is said that the data word is "copied" into the register. The "copy word" transfer is equivalent to a "copy ones" transfer followed
by a "copy zero's" transfer.

BIT 13 12 11 10

9

8

7

6

5

4

3

2

0

INITIA L STA TE
OF REGISTER

l~s~l-s~l~s~l~s~l~s-l~s~ls~I~R~I-R~I-R~IR~IR~I-R~I-R~IR=RESETRELAY

DATA WORD

10101010101010

FINAL STATE
OF REGISTER

Is

S=SET RELAY

I R I SiR I SiR

lsI R

I SiR

I SiR

I SiR I

In order to copy a data word into a CC~ register, two outputs are actually required. Each CC() relay has a set coil and a reset coil. a set channel and a reset channel. The data is first output on the set channel. then complemented
(i. e. replace ones by zeros and zeros by ones) and output on the reset channel.
For each "one" output on the set channel a relay is set. while for each "one" output on the reset channel a relay is reset. The two outputs occur under hardware
lockout and are always done very close together in time (18 microseconds).

1. Data word is output on set channel.

2. Data word is complemented.
3. Complemented data word is output on reset channel.

10-7

BIT
INITIA L STATE
OF REGISTER

13

12

11

10

9

8

7

6

5

4

3

1

0

ISiS I I SiS I SiS IR IR IR IR I R I R I R I
S

DATA OUTPUT
SET CHANNEL

1

0

1

0

1

0

1

0

1

0

DA1A OUTPUT
RESET CHANNEL

0

1

0

1

0

1

0

1

0

1 0

fiNAL STATE
CF REGISTER

2

I

SiR

I

1

0 1

0

0

1

1

S= SET RELAY
R= RESET RELAY

S I RI SIRISIRIS IRISIRISIRI

For convenience, the reset channe I is always chosen adjacent to and one less than
the set channel.
After a four millisecond time delay to allow for delay setting times, an interrupt
is generated to request another output. Within 5 milliseconds the second register
will be output by the computer.
Figure 3 is an illustration of the three dimensional nature of the CC(j address
matrix. All of the relays in a given fourteen bit register have the same word
address. In addition, the set and reset coils of a relay will always have the same
word and bit address, but their channel addresses will differ by one.
Circuit Description
Refer to 867C560 which is a diagram of the circuitry required to set and reset one
particular CC(j relay. The address of the relay pictured is word 0, set channel
15 (reset 14), bit O. For simplicity only one relay and its associated driver are
shown, so the following points are listed to place the diagram in its proper perspective:
l.

One relay is shown but there are thirteen other relays in the same register
which can all change state simultaneously along with the one shown. There
may also be many other registers.

2.

One set and one reset channel driver circuits are shown, but there are
thirteen set and thirteen reset channel driver circuits not shown.

3.

Only one word driver circuit is shown, but there are as many word
drivers required as there are relay registers.

4.

The power supply switch shown is the only one required no matter how
large the total number of relays.

10-8

'">-

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cco MULTIPLEXER ADDHESS nUILDUP
Figure 3

~(e"'c,

~C"(o

~ou

It is l'e~om''1 n.kd f'1.1f I.he reader refer to the description of the W';J, Cu, CtJ,
ancl P3 tlrinted circuit m,',dules before attempting to understand how they w0rk

together as in %7C5()O,
The w')rd and channel drivers 'lse silicon controlled rectifier (SCR's) to "route"
CUITent to the particular relay being add)'essed. An Seils ~jmply a "switch"
which IS pither clos~d to .:>ass current, or open to hloe!, current. Once set, or
turned on, an SCH ·....ill remain closed and p.lSS current until something in s~ries
with it "opens up" and stops the current flow. CPlce the flow of current through
the sca stops, no more c'Jrrent will flow until it is again s~t, or turned on.
To pick a relay, one word SCR :md one channel SCR :lre turned on. C~rrent will
flow from the positive voltage supply through the word SCR, through the relay
coil, thr now.
When
it opens momentarily, CUl'i'ent flow will ceasE' and cause the SC~'S to t,lrn off.
Having discussed the circuitry which causes current to flow throuJh a pa;o-i:ic1l1ar
relay coli, the circuitry concerned with timing can be discussed. As W'H :;ecn,
all relay current flows to grountl through a power supply switch whose function is
to open up the current path at the proper time once the relay coil has been energized. The output of the power supply switch, pin X9, is normally at ground
potential, while the trigger Input, pin X!2, ts normally at +26 volts. If the
trilgcr lTlput pin Is ~rollnded, a time delay will expire, and at the end of the time
delay the p()Ner sllpply Bwitch output will mOllH:'ntarily open up. The output remhins UpCTl for about 110 microseconds, just bng ~nough to cause the SCR's to reset. The time delay between the grounding of the input and the opening of the output is arfjustable by means of a potentiometer on the power supply switch printed
circuit module. Also, when the time delay ~)(pires, an interrupt is generated at
pin Xi6.

10-10

The trigger input to the power supply switch is grnundcd each time an output to a
This l'litiates the time delay which expires, :1'1(1 the'l
interrupts the computer to reqll~st that another output he done. Each Cha!l~el
driver has :1 trigger SCR which turns I)n every timc an output is done on that
cha:1Ilcl. The function of this SCR is to ground 1'lc tri~ger input o~ the power f;1JIlp~v tiwitch. In 8G7C560, the trigger Sell '::'m'lccts from pin X!A of the channel
driver !o pin X12 I)f the power S1lpply switch.
CC0 register is d:me.

Following is

:1

brief summary of the above:

1. The computer does an output which causes a ''v')rd sen and a channel bit
to turn·on. TJ-.is a~~ows Gurrent to flow through a relay coil.
2. S;muitaneously, a trigger SCR is
the pClw~r SUiJP'V switch.

turn~d

on whi::h

~rounds

Sell

the trigger input of

3. F.:>ur millis~conds later, t~e pNler supply switch o~ns up and caus~s a'l sca's
to be reset. At the same time, an interrupt is generated to inform the computer that another output 'nav be done.

C.

Adjustment
There is only one a11'13tment in the contact closure OUtpllt suh-s~';-~' ,'-n. tt is the
adjustment of the time delay between an output and the ocr.urrence of the CC~
completion interrupt. The adju stment is made by means I)f a p!)tentiome~r located on the PS power suPil1y switch printed circuit module.
The adjustment should be made such that the time hetwee'l the computer output
and the generation of the completion interrupi. equals 4.0 milliseconds.
The adjustment can be made using an osci1loscop~ by observing that the interrupt
is generated 4.0 milliseconds after the power suPilly switch tri~Ger is ~rounded.
If no oscilloscope is available it is possible to use the computer itself as a tool
to accomplish the adjustment. This may be done by doing an output, and then
incrementing a counter within the computer memory, with a stClP c'-Jmmand in
the interrupt location. When the computer is started an output will occur and
then the computer will stop when the interrupt is received. The accumulated
count will then be proportional to the time delay between the output and the interrupt.

The oscilloscl)pe method is generally preferred since it can be done "on-line"
without disturbing existing programs or tempm-drily shuttir.g down the system.

10-11

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ANALOG OUTPUT SUBSYSTEM
1.

GENERAL DESCRIPTION
The AQ$ Subsystem uses special contact closure outputs to switch resistors in
a digital potentiometer to convert a digital input to an analog output.

Two main

categories exist:
1.

Cards with 7 relays where the cards can be used in place of a Ce,3
card.

2.

Cards with more than 7 relays where an X panel with space for 16
analog outputs (16 words) replace 2 - X panels of Ce,3 cards driven
by the same word driver with 2 cards per word.

Figures 1, 2 and 3 show typical AQ$ and Ae,3/CCO subsystems in block diagram
form.
II.

SPECIFICATIONS
A.

Input Requirements - As with all other subsystems, the AO subsystem
interface with the computer central processor itself is via computer word
and channel selection circuitry.

The only inputs to thC' AO subsystf'm are

from these computer I/e,3 interface circuits.
B.

Contact Specifications - All contacts for analog outputs are mercurywetted, non-bridging (except for reversing) and are bounce free.

They

switch resistors which draw current in the milliampere range and have no
R-C contact protection, except for reversing.
C.

Output Rates and Timing - 1A02 cards (5-bit reversible) are grouped in
twos to form registers of fourteen.

Each 1A01 or 1A03 (10 or 11 bit)

cards will serve as a fourteen bit register but will not furnish the 4 or 3
high order bit relays.
Outputs occur under program control one register at a time

11-1

I

Connections to Plant or
Process Devices

D-Panel
Channe I
And
Word
Selection
(Hal f-Sel ects)

t t t t

.

TERMINALS

~

CD Set Channe I
Driver Printec
Circuit Card

First X Panel

~

Output
Data

~

~

Interrupts

I/O
I nlerface

CD Reset Channel
Driver Printed
Circuil Card

--

16-10 Bit

Analog Outputs

WD Word Driver
Printed Circuit
Card

P S PO'.-Jer Supp I y
Svli tch Pri nted
Circuit Card

Driver
Panel

AcJ SUBSYSTEM OF 16-10 BIT OUTPUTS

Figure 1

I

Connections To
D-PAnel

t

Chelnnel
lInd
'lord

t

TerminAls

TermiNlls
Or
Connectors

Sel,~ction

(Hal f··Sel ects)

rtI

~

Output
Data

~

CD Set ChAnnel
Driver Printed
Circuit Card
CD Reset Channel
Driver Printed
Circuit Card
WI) Word Dri ver
Printed Circuit
Cud

r-f-

t-I-

~

t-

~

~

Word Dri ver
Printed Circuit
WI)

~

First
X-Panel
16-5 Bit
Reversible
Analog
Outputs

PI~nt

r---

Second
X-Panel
112 CC.

r

Or Process Devi ces

t

t
TERMINALS

Third
X-Panel
16-10 Bit Analog Outputs

,

4

C~rd

Interrupts

1/0

&

PS Power Suppl y
Swi tch Prj nted
Circuit Card
Driver

I nt.erface

A~

'-

P~nel

CC~ SUBSYSTEM OF 112 CC~ POINTS

& 16-5 BIT REVERSIBLE & 16-10 BIT ANALOG OUTPUTS

Figure 2

Connections To Plant Or Process Devices

t
D-Panel
Channel
And
Word
Selection
(Hal f-Selects)

r-

CD Se t Channe I
Dri ver Pri nted
Ci rcui t Card

~

CD Reset Channel
Driver Printed
Circuit Card

~

Output
Data

.

Terminals
Or
Connectors

f---

~

1st
X-Panel

2nd
X-Panel
112

112 CC.

TERMINALS

cct

3rd
X-Panel
16-10 Bit
Analog Outputs

~

WI) Word Driver
Printed Circuit

~

~

CD Reset Channel
Dri ver Pri nted
Circuit Card
PS Power Supply
Swi tch Pri nted
Circuit Card

5th
X- Panel
6th
f----- 16-5 Bit
ReversX-Panel
ible
112 CCcj
Analog
Outputs ~

r--

4th
X-Panel
16-10 Bit
Analog Outputs

Interrupts

Terminals
Or
Connectors

TERMINALS

t

t

•

Connections To Plant Or Process Devices
I/O
Interface

•

WO Word Driver
Printed Ci rcui t

CD Set Channel
Dri ver Pri nted
Circuit Card

"-

•

t

Terminals
Or
. Connectors

Termi nals
Or
Connectors

•

Driver
Panel

Acj & CCcj SUBSYSTEM OF 336 CCcj POINfS & 16-5 BIT REVERSIBLE & 32-10 BIT ANALOG OUTPUTS
Figure 3

states of all relays within a given register can be changed simultaneously.
Once set, a relay will remain set until another output causes it to be
cleared. Within a given register, one or more relays may be set, cleared,
or remain unchanged when an output occurs.

Five milliseconds must

elapse between outputs of individual registers to allow for relay setting
times and program response time.

Thus, outputs can occur at a maximum

rate of 200 registers per second. This specification holds provided no
attempt is made to change the state of any particular one of the relays
more often than once every ten milliseconds.
In actual practice, output rates will vary and will be dependent upon program control.

m.

CmCUIT DESCRIPTION
A.

Functional Description
Analog output relays are combined in groups of up to 1 or 2 cards per
word, with each group being referred to as an analog output "register".
Outputs occur one register at a time, so that the state of all fourteen relays
within a register can be changed Simultaneously.

Each register has a word

address and a channel address, or more precisely a SET channel address
and a RESET channel address.

Thus, a particular register is uniquely

defined by the speCification of two numbers, a word and a channel address.
Any output on a computer channel must be accompanied by a fourteen bit
"data word".

Corresponding to each bit of the output data is one of the

fourteen relays within the AcJ register.

Thus a particular A(J relay is

uniquely defined by the specification of three numbers, a word, a channel,
and a bit.
The following example shows the state of a relay register before and after
an output, along with the data word which caused the change. Note that for
each bit of the data word which is a one, a corresponding relay is set, and
for each bit which is a zero, a relay is reset. The final state of the A(/J
relay register does not depend on its initial state t but depends only on the

output data. When both ones and zeros are transferred, it is said that the

11-5

data word is "copied" into the register.

The "copy word" transfer is

equivalent to a "copy ones" transfer followed by a "copy zero's" transfer.
BIT

9

7

13

12

11

10

INITIAL STATE
OF REGISTER

S

S

S

S

S Is I S

DATA WORD

1

0

1

0

1

FINAL STATE
OF REGISTER

S

R

8

1

0

I I

S

R

R IR
0

I I

1

I I

SiR

S

R

R IR

0

1

R"I SiR

1

2

3

4

5

6

0

I I I
R

R

1

0

0

S=SET
RELAY

I I
SiR

R=RESET
RELAY

SiR]

In order to copy a data word into a Af/J register, two outputs are actually
required.

Each Af/J relay has a set coil and a reset coil, a set channel

and a reset channel. The data is first output on the set channel, then
complemented (i. e. , replace ones by zeros and zeros by ones) and output
on the reset channel.

For each "one" output on the set channel a relay is

set, while for each "one" output on the reset channel a relay is reset.
The two outputs occur under hardware lockout and are always done very
close together in time (18 microseconds).
1. Data word is output on set channel.
2.
3.

BIT
INITIA L STATE
OF REGISTER

Data word is complemented.
Complemented data word is output on reset channel.
13

12 11

Is I S Is

10

I

9

8

6

7

S Is Is I S

5

4

3

1

2

0

I R I R I R I R I R I R IR I

DATA OUTPUT
SET CHANNEL

1

0

1

0

1

0

1

0

1

0

1

0

1

0

DATA OUTPUT
RESET CHANNEL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R I

S I R I SiR

FINAL STATE
OF REGISTER

S IRlslRlslRI S

I

11-6

I

S

IR

R=RESET
RELAY
S=SET
RELAY

I

For convenience, the reset channel is always chosen adjacent to and one
less than the set channel.
After a four millisecond time delay to allow for delay setting times, an
interrupt is generated to request another output.

Within 5 milliseconds the

second register will be output by the computer.
Figure 4 is an illustration of the three dimensional nature of the AO
address matrix. All of the relays in a given fourteen bit register have the
same word address.

In addition, the set and reset coils of a relay will

always have the same word and bit address, but their channel addresses
will differ by one.
B.

Circuit Operation
Refer to 867C560 which is a diagram of the circuitry required to set and
reset one particular

ceo relay,

of the AeJ coil circuits.

the coil circuits of which are a duplicate

The address of the relay pictured is word 0, set

channel 15 (reset 14), but O.

For simplicity only one relay and its asso-

ciated driver are shown, so the following points are listed to place the
diagram in its proper perspective:
1.

One relay is shown but there are up to thirteen other relays in the same
register which can ali change state simultaneously along with the one
shown. There may also be many other registers.

2.

One set and one reset channel driver circuit is shown, but there are
thirteen set and thirteen reset channel driver circuits not shown.

3.

Only one word driver circuit is shown, but there are as many word
drivers required as there are relay registers per channel.

4.

The power supply switch shown is the only one required no matter how
large the total number of relays, including both AC and CCO relays.

It is recommended that the reader refer to the description of the WD, CD,

AO, and PS printed circuit modules before attempting to understand how
they work together as in 867C560.

11-7

-»
en

CIS

cu

-»
en

.!9

cu

p:::

p:::

~

~

til

"0
~

CIS

'<:to

-

U

til

lS

~

~

~

"0

as

C\J

<

U

.....

C\J

~

lS

I
00

~

C\J

«
~

A(j MULTIPLEXER ADDRESS BUILDUP

Figure 4

The word and channel drivers use silicon controlled rectifier (SCR's) to
"route" current to the particular relay being addressed.

An SCR is simply

a "switch" which is either closed to pass current, or open to block current.
Once set, or turned on, an SCR will remain closed and pass current until
something in series with it "opens up" and stops the current flow.

Once the

flow of current through the SCR stops, no more current will flow until it is
again set, or turned on.
To pick a relay, onC' word SCR and one channel SCR are turned on.

Current

will flow from the positive voltage supply through the word SCR, through the
relay coil, through the channel SCR and through the power supply switch to
ground.

Current will continue to flow until the power supply switch "opens

up", at which time current flow will cease and cause the SCR's to turn off.
Suppose that the relay pictured is in a reset state, and it is desired to set
it.

The computer will output bit 0 on channel 15 with word 0 selected.

This

will cause thC' word 0 SCR and the channel 15 bit 0 SCR to turn on and con-

duct current.
out pin X34.

Current will flow from pin HI through the word 0 SCR and
From X34 current flows through a cable which connects to the

X-panel and through back-of-panel wiring to pin H17. Only one relay is
shown but up to 14 relays are connected to pin H17. The particular
relay selected, and whether set or reset coil, depends on which channel
bit SCR is turned on.

In our example the channel 15 bit 0 SCR is turned

on, so current will flow through the set coil, out pin LIB, and back to the
D-panel through the interpanel cable and into pin X35.
flows through the SCR and out pin Xl.

From X35, current

Tracing through the card edge

jumper wiring, current flows into pin X9 of the power supply switch.

The

power supply switch transistor is conducting and completes the path to
ground. As long as the power supply switch transistor remains ON, current
will continue to flow.

When it opens momentarily, current flow will cease

and cause the SCR's to turn off.
Having discussed the circuitry which causes current to flow through a
particuiar rday coii, the circuitry concerned with timing can be discussed.

11-9

As was seen, all relay current flows to ground through a power supply
switch whose function is to open up the current path at the proper time
once the relay coil has been energized.

The output of the power supply

switch, pin X9, is normally at ground potential, while the trigger input,
pin XI2, is normally at +26 volts. If the trigger input pin is grounded, a
time delay will expire, and at the end of the time delay the power supply
switch output will momentarily open up.

The output remains open for about

110 microseconds, just long enough to cause the SCR's to reset.

The time

delay between the grounding of the input and the opening of the output is
adjustable by means of a potentiometer on the power supply switch printed
circuit module. Also, when the time delay expires, an interrupt is generated at pin X16.
The trigger input to the power supply switch is grounded each time an output
to a CCO or Aej register is done.

This initiates the time delay which

expires, and then interrupts the computer to request that another output be
done.

Each channel driver has a trigger SCR which turns on every time an

output is done on that channel.

The function of this SCR is to ground the

trigger input of the power supply switch.

In 867C!)60, the trigger SCR

connects from pin X18 of the channel driver to pin XI2 of the power supply
switch.
Following is a brief summary of the above:
1.

The computer does an output which causes a word SCR and a channel
bit SCR to turn on.

2.

This allows current to flow through a relay coil.

Simultaneously, a trigger SCR is turned on which grounds the trigger
input of the power supply switch.

3.

Four milliseconds later, the power supply switch opens up and causes
all SCR's to be reset. At the same time, an interrupt is generated to
inform the computer that another output may be done.

C.

Adjustment
Timing
There is only one timing adjustment in the analog output subsystem. It

11-10

is the adjustment of the time delay between an output and the occurrence
of the

ceo or

AO completion interrupt. The adjustment is made by means

of a potentiometer located on the PS pOWf'r supply switch printed circuit
module.
The adjustment should be made such that the time between the computer
output and the generation of the completion interrupt equals 4.0 milliseconds.
The adjustment can be made llsing an oscilloscope by observing that the
interrupt is generated 4.0 milliseconds after the power supply sWitch trigger
is grounded.
If no oscilloscope is available it is possible to use the computer itself as

a tool to accomplish the adjustment.

This may be done by doing an output,

and then incrementing a computer within the computer memory, with a
stop command in the interrupt location. When the computer is started an
output will occur and then the computer will stop when the interrupt is
received.

The accumulated count will then be proportional to the time

delay between the output and the interrupt.
The oscilloscope method is generally preferred since it can be done "online" without disturbing existing programs or temporarily shutting down
the system.
Voltage
The output supply voltage must be set as described under the card descriptions.
Also, series dropping resistors and zero suppression resistors may be added
as described.

The remote sensing feature aV'd.ilable on some power supplies

may be used to regulate the voltage at the taper pin busses rather than at the
power supply terminals.

11-11

MULTIPLEXED CONTACT CLOSURE
INPUT SYSTEM

I.

GENERA L DESCRIPTION

The multiplexed Contact Closure Inputs (MPLX Cel) are used to interrogate the
status of process contacts. The multiplexing provides a low cost method of interrogating a large number of plant (or process) contacts.
Figure #1 is a functinll:t1 diagram of a multiplexed CCI system that can accommodate
a maximum of 7k I ('nnt:1ctS. Each pair of CM relays are wired to two sets of 14 plant
contacts. One rh~nnt'l Driver (CD) card can drive 14 pairs of CM relays. The other
side of the plant contacts are tied together to provide two final sets of 14 data lines.
Each set of 14 data lines is wired to an individual Contact Buffer (CB) card.

FROM CB MODULES

It-;PUT
OJTPUT
DATA

HS TO CB MODULES

.

'-

-H

52

HALF
SELECT

14 BITS

.....-

TB
D
PANEL

56E
..::t

-

---'

&1

r-

CD a:l

Ct1

PANEL

SbE
..::t

-

I--

INT

PNL
( 14)

1 CD

Plant
Contacts

392

,

-

a:l

l

--

X

PNL
( 14)

-V

--t

196
-V

tV TB

_r-o

"vi
r-

196

~

Z

TB

X

en
_ _ _ _ _ -J

-

g

ID {~

OD

Plant
Contacts

392

CB
3

_
lq6

CB
2

lq6

CB
1

T~v

W

CB
4

CM
-V

I

.-

~~~ l
n :»

H.S.

I--

HS4

-

HS3

~

CD TRIG
PS
OUT

P55-L
P 55-2
I/O
INTERfACE

i--J CB TRIG

1.T.B.ARE OPT I ONAl

P55- 3
PSS-4

2. lOCI\TION Of MODULES I S

POWER SUP .sw
Figure 1

12-1

OPTIONAL

3. + V CAN BE 48/125V

to

II.

SPECIFICATIONS
A.

Input Requirements
Input is via +48 or +125 VDC being presented to the CB card by customer'l procell
contacts being closed.
A minimum of 10 milliseconds settling time Is required for multiplextDg and filtering. This 10 milliseconds Is required for eaoh group of 28 contacts in any block
of 392 contact inputs. The maximum scan rate is therefore 2800 CCI/seoond per
mUltiplexed CCI panel. Sinoe It il possible to pt 2 multiplexed CCI panell, the
maximum system scan rate 11 5600 CCI/second.

B.

Power Requirements
The +48 or +125 volts dc can be supplied with the system or may be provided by
the user. The voltage should he no more than :!:10% of nominal value. The capacity of the supply will be dependent upon the total number of inputs to be suppUed.

III. CIRCUIT OPERA TION
A.

General Instruction Format
The selection of a particular 14 bit contact input word is organized on a one word
per bit basis. For each bit in the CCI address word, there is a corresponding 14
bit CCI data word.
To bring contact inputs into the computer, a sequence of two instructions is required, an output followed by an input. The output instruction which must be
executed in the direct mode contains in bits 0-7 of the instruction word, the CCI
channel address. The output data register must contain the CCI address word.
Caution is required on the output command since selection of more than one output bit will cause more than one process contact regi~ter to present itself to the
input (Cn module) register.
As mentioned before, an input instruction is part of the sequence of instructions
required to sample plant contact input status. The execution of an input instruction in the direct mode with the low order bits of the instruction word specifying
the input channel number will result in input data to the computer of the contact
input data word addressed by the previous output instruction.

B.

Interrupts
If more than 392 process contacts are being used, a second multiplexed CCI

system, wired independent of the first, is used.

12-2

However, since only the first system will generate input request and output request interrupts, the second group of 392 process contacts must be called for
first, then the first group.
C.

Circuit Description
Drawing 867C601 is a flow diagram of the multiplexed CCI system.

cn

If we assume that channel 40 is used to select the
module, the CD module
three winding transformer will be pulsed on pins L2 and H3, now if bit 13 was
selected as the output bit, the SCR, Sl-l will be triggered thus allowing the CM
relay, l'V1A:-l to be picked. At the same time, the channel driver trigger circuit
will be turned on and allows the power supply switch (PSS-l) to start its action
(see 2PSI description for details) and to provide an input request interrupt in six
milliseconds. The ~ix milliseconds is the time delay set in the power supply
switch circuit (PSS-I) to insure C'M relay contact closure/open and CB module
filter charge/dischargf' time.

With l\1A-I closed, its rontacts \\i11 close to a specific group of 14 process contacts. These process contacts will have either +48 or 125 volts on them depending
upon the system.
The isolation diodes on the ('1\1 module prevent sneak paths to non-associated input bits.
The statuf; of the contacts \\!ill determine whether or not this voltage is impressed
across the ('11 module mtcr.
If the voltage is presented to the CB module and if the input instruction is called

for (Channel :l7. in ollr example) the information will be presented to the input data
lines (here Bit 1~: IDD and IDR13).
At the same time the information is sent to the input data lines, the CB trigger
circuit will cause its SCR to be turned on. This will cause PSS-2 to turn on and
one millisecond later, an output request interrupt will be initiated to the I/O
interface.
When the PSS-I and PSS-2 switches supply the interrupts, this also allows the CD
trigger sen and CB trigger scn to be reset. See 2PSI card description for details.
D.

Panel Configuration
Drawing 867C944 is a block diagram of the Panel Configuration.
The maximum number of multiplexed CCI per X (or Q) panel, is 392. As

12-3

mentioned previously, a second group of 392 CCI is available. This will be
located on a second X (or Q) panel.
The X or Q panels will contain the CM modules, with the CB modules, the CO
module and PS module usually located on a 0 panel.
To use 392 CCI, it is necessary to have 14 CM modules, I-C~ module, 2-CB
modules and 1 power supply switch. For the second group of 392 CCI, a duplicate complement of modules as used in the first group, except for the Power
Supply switch.
As noted previously. only the first group of 392 eCI will cause an interrupt.

12-4

A 15 AND A18

A 15 AND AlB
56 PIN ELCO

A
B
C
D
E
F

J
K

L
M

N
P
R
S
U
V

W
X
Y

Z

a
b

c
d

DES IGNATION
INT
INTR
INTR
INT
INT
INTR

20
20
21
21
22
22

INTR
INT
INT
INTR
INTR
INT
INT
INTR

23
23
24
24
25
25
26
26

INTR
INT
INT
INTR
INTR
INT
INT
INTR
INTR
INT

27
27
40
40
41
41
42
42
43
43

56 PIN ELCO
k

1
m
n
P
r

s
t
u
v

x
Y
z

AA
BB
CC
DD
EE
HH
JJ

KK
LL
MM
NN

12-5

DESIGNATION
INT
INTR
INTR
INT
INT
INTR
INTR
INT
INT
INTR

44
44
45
45
46
46
47
47
30
30

INTR
INT
INT
INTR
INTR
INT
INT
INTR

31
31
32
32
33
33
34
34

INTR
INT
INT
INTR
INTR
INT

35
35
36
36
37

37

A16 AND A19
56 PIN ELeO
A

B
e
0

E
F

J

K
L
M
N
P
R
S
U
V
W

X
y

Z

a
b

c
d

E.

A16 AND A19

DESIGNATION
INT
INTR
INTR
INT
INT
INTR

50
50
51
51
52
52

INTR
INT
INT
INTI<
INTR
INT
INT
INTR

53
53
54
54
55
55
56
56

INTR
INT
INT
INTR
INTR
INT
INT
INTR
INTR
INT

57
57
70
70
71
71
72
72
73

56 PIN ELeo
k

1
m
n

P
r
s
t
u
V

x
Y

z
AA
BB
ee
DO
EE
HH
JJ

KK
LL
MM
NN

73

DESIGNATION
INT
INTR
INTR
INT
INT
INTR
INTR
INT
INT
INTR

74
74
75
75
76
76
77
77
60
60

INTR
INT
INT
INTR
INTR
INT
INT
INTR

61
61
62
62
63
63
64
64

INTR
INT
INT
INTR
INTR
INT

65
65
66
66
67
67

Terminations
Drawing 609B976 sheets 1 and 2 define the terminations available for the multiplexed CCI system.
Connectors J, K, Land M are the Curtis Terminal Blocks, this is the most
commonly used type, however. these can be Rowan blocks whIch have the same
terminal markings or they can be Elco connectors as shown in the drawing.

12-6

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AIOI - ANALOG INPUT SUBSYSTEM
GENERAL DESCRIPTION

Input Impedance

The Analog Input subs:,'stem provides for selection and
sampling of analog signals and for conversion of the
analog signals to digital form in order to be entered
into the central processor.

•

5 Megohms on 50 mV range.

•

1000 Megohms/volt on 5V ~nge.

System Accuracy
The selection of an analog input is accomplished by a
relay type multiplexer which connects the selected input to the analog-to-digital conversion circuits. The
system is fail-safe against muitiplp analog point selection to anyone analog-tn-digital conversion circuit
through the usc of the analog trap and detection circuitry.

•

O. 1% of full scale on both ranges,

Max. ND. Df V/F CDnverters
•

4 (per "A" panel).

Modularity
The analog signal is first converted into a frequencY'
proportional to its instantaneous value by a voltage to'
frequency (V /F) converter. The output of the V / F converter is then counted for a period equal to one cycle
of the power line frequency. By this method the nois!'
components relatcd to the pO\\'pr line frpquency (which
is the predominant noise) arc integrated tn zero and,
thus, eliminated. The tllJC of modules used in the
Analog Input subsystem, and thPi rink [,(·onnection.
are Shown on drawing K67C567 (Fig, 7).

•

14 inputs per AP module.

•

224 inputs per "X" panel.

Max. ND. of Inputs
•

Not limited (determined by the number of word
and channel drivers used).

Multiple Selection PrDtection
The modules are mounte'd in the Analog Input Driver
Panel CA" pane'l) with the exception of the input multiplexer modules (AP) whl('h are mounted in multiplexer
panels ("X" panels),

•

PRINTED CIRCUIT CARD REFERENCE

The system shown on Rfi7C Sr;7 is the maximum svstem
which can be provided with one "A" panel.

3AC4
4API/4AP2
2AT3/2ATI/1SRl
4CDI
5CLl
4CTl
IPL-!/JPL5
35B1

In actual application the size of the svstem is determined bv the number of analog points and bv the numher of V/F converters lls(~d.

SYSTEM SPECIFICATIONS
Maximum Sampling Rate
•

:10 points/ see/V / F converte I'S llspd (in 60 evc I ('
environment) ,

•

25 points/sec/V / F converters used (in 50 eyc h>
environment).

An analog trap circuit prevents the selection of
more than one analog input at a time, per V /F
converter,

l\\D-!

Analog Control Card
Analog Point Selection Card
Word & Channel Trap
Channel Driver Card
Calibrator Card
Counter Module
Phase Locked Oscillator Card
Span & Gain Card with Digital
Input Buffer
Word Driver Card

CIRCUIT OPERATION
General

tftput Signa I Range
•

O-SOmV full scale (with -JO()'); to' 200T overrange).

•

O-SV full scale (with -100': to ' 120'i; overrange).

The selection of analog inputs, the selection of gain
and span connection, and the starting of the anaiog-todigital conversion cycle is under program control.
The analog input address is formed by a word, channel
and bit, Note that only one bit should be set for each

13-1

A deviation of more than 0.05% can be corrected.

analog address. If more than one bit Is set. this will
caUSe more than one analog input connected to the V/F
converter to be selected. which results in erroneous
reading. Also note that if more than one input i8 selected (2. 3 or 4 V/F converters are used) the addresses should have the same channel and bit numbers.

Bit 7 is used to reset the Span drivers. Bits 0-6 are
used to select the required span. The span values corresponding to each bit are shown below:
Bit
Bit
Bit
Bit

The words normally used for the analog input selection
are words 40 to 77. The channels normally used for the
input selection are channels 17. 37 and 57 (channel 77
is also available if less than four V/F converters are
used).

This gives a total range of -3.2% to + 3. 15%.

-LnJ?ut .Data (octal)

Bits 12 and 13 are used to select the gain. in the manner
shown below:

30000
:17777
00000
07777
17777

200

0.8%
l. 6%
3.2%
Reset

4
5
6
7

Data Word=0001l010=span of l.3% +
(-3.2%) or -l. 9% overall.

The AlIalu~-tu-lJi!!.ital Cunverter (ADe) bit pattern is
as shown below:

+

Bit
Bit
Bit
Bit

Data Word= 01000000 is a span of 3.2% +
(-3.2%) or 0% overall.

For inputting the digitized analog value to the central
processor. channels 16. 36. 5h and 76 are used (corresponding to Vii" COIlV. #1, ~:!. #:l and #4).

-0
'0
r 100

0.05%
0.1%
0.2%
0.4%

Since the V/F converter is offset 3.2% in the negative
direction. any span bits set are added to this value.
For example:

The analog addresses are assigned to the V/F converters as shown in Table 1.

-100

0
1
2
3

The same channels 16. 36. 56 and 76 In output mode
are used to set the span and gain to the V/F converters.

Bit 13

Bit 12

Relay

Range

o

0

No
Change

No
Change

o

1

Energized

0-5 V

De-energized

0-50 mV

0
To compensate for absolute deviation of line frequency
from 60 Hz, the system has the capability of adjusting
"span" (frequency to voltage ratio). If. for example.
the line frequency were to drop, the counter would be
enabled for a longer period of time and the count would
be too high. In this case the span must be decreased
in order to correct the count. The span adjustment in
effect decreases the slope of the VIF ratio line as
shown in Figure 1. To check for frequency shift, a
reference voltage from a calibrator card (CL) is read
'.Jnder program control and the deviation is calculated.

Not Used

1

Note that both the span and gain can be output in the
same data word.
The output of Bit A on Channel 16 is used to generate
the READ TRIGGER signal which starts off the analogto-digital conversion cycle. The analog-to-digital conversion cycle is automatic. controlled by the analog
control (AC) module.

TABLE 1. ANALOG ADDRESSES FOR V/F CONVERTERS
Analog Worfls
77-74
73-70
67-64
63-60
57-54
53-50
47-44
43-40

One V/F Conv.

Two V/F Conv.

1
1

1
2
1
2
1
2
1
2

1
1
1
1
1

13-2

Three V/F Conv.

Four V/F Conv.

1
2
3
1

1
2
3
4

2

3
1

2

2
3
4

Upon completion of the conversion cvcle, an intC'rrupt
is gener:ltf'd (\\hich is rl'cognized hv the prngram) to indicate that the information is rf'ad\' and a
new cycle can he sta rted. The instruction sNluC'ncf'
should be as follows:

7(;:12
:; voit

si~1al

7(1)()
(Jon

1~IIl~I

:\0

:.;

1. Read analog input value of previous output
(Input on Ch. 16, 3n, 56, 76).

i():12

7000
nno
:iO

;)OrnV

range

.)

NOTE

If more than one output is selected (2. ::
or -4 v/F c()nVl'rt\>I's used). the addres!'l's
should have the same channel and hit nlll1)bers.
If n'setlln~

spall

Output read

trig~l'l'

(( JUtput Ch. Iii

Kil

-43.750
,L fiR7
0.293
. 02~
-li'j.7;'-4 Millivol ts

CIRCUIT DESCRIPTION

(I

The now diagr;111 "f the Analog Input suhsystem for UIl(;
,lnalog- Il1put P01l1t is' shown on dl":I\\'ing .,\f;7C'i()H (Fig. H).
f!s,,)~ \\lIrd -;i
channel 17 bit 0 for an;t1og- pOint address
and channel It, f()r input and for sJJan-g-ain control, the
I'fJL'l'atItJf1 <.t' tl'L' cln'lJll is explallwd as follows.

Jllt-

1. Output sf-ian and ~aill it l"l'4l1ired «JUli'"i "JI
Ch. lfi :lfi, 5(i. 7fi).

5,

4.37;'0
O. I()H7
0.0293
0.0024
4.87'14 Volts

or octal printout:

:.;, Output new analo~ input add ress and hit number (Output on Ch. 17 01' 37 or ;:'7, Output word(f;) ),

:1. Outvut span l'('sd onl\
pllt Ch. 16. Bit 7).

-

When ""I'd 71

;i('il-ckd, the 1 iJ.s puIsI' of 7t1t1f'l and

I",

67t1~ \Iill tl'i~,,"1 thl' "")I'd driver SCR, This will appl\
In
to the- ('(,mmon l('g- of the relay coils on the AP

v

~).

card.
ri.

Wait for mterrupt.

7.

Reptat steps I t(l fi.

When bit 0 (()J)IJ(IJ IS a 'nne" and channel 17 is selected,
(MIt'! and tHltl7). t)oth SCR' s shO\\11 on the CD card will
he turned on \\hich will energize the point rela\' (1)
:Ind the guard reJa,' (Co) on the AP card. The guard r(l1:1\ c"ntart tlll'11 picks lip the bus rela\' (13).

Converting tile Octal Printout to Decimal
T'lble 2 allows the user to C()I",\'ert octal P'tllL,'dl:,1
the analog subsystem to decimal values. Con\'ers('l\
a known decimal value can be converted to octal for
comparison with the printout. The arrow ( • ) in tre
table indicates the decimal point position.

The analoJ!; point is now connected tn the V/F converter
thp analog hilS.

Via

The "'; I, (",,~,c,,·ter ~('Ilcrat('s an output pulse with a
fn'qllcnc\ pl'nportiona; to the analog volugc signal. as
shown In Fig'lIl'(' 1.

For cxample. t.'lke oC!.:ll printout:

TABLE 2. OCTAL TO DECIMAL CONVERSION TABLE
nC'TAL

\'Cl LT .-\(; E

10000

,,. ot
.) \'

701H)

r,000
:,000
,1000
:1000
2000
1000

J

:1

.,

0

:)0 mV
000
:i
7'iO
'iOO
7
250
1
uoo
5
s i °,0
;;00
2
250
6

OCTAL

\'nIT-\(;E

7()0

II.

.)

11

t

0

:l

II

II

..

.,

()
()

fI

lr,;)
hM7
!JOn
I ~:,
:: 1~
:,(J2
7H I

13-3

\'()LTAGE

,-,

;)Orn\'

.J \

600
500
-too
:100
200
100

OCT,\L

10
fill
50
10
:lO
20
10

OCTAL

:,0 111 v

\'

Il • \ I •

0

0

"

0

(i~,l
-)

""(;

.j >< ><

VOLTAGE
5v 30mV

i
i;

II • 0.

0><;)

0

0

07 ;~

0

0
Il

Ofil
0,1;)
O:i7
02-4
012

IJ

I)

:~ <)

I

()

II

I)

:2 0:~

0

I)

()

0

0

I)

0

1 !I C)
O!J/<

0
0

0

NOTE

timing sequence of AC module). the analog control
circuit generates a RESET signal to the counter (CT
module). and limes out a delay to permit settlinr; time
for both the point. guard, and bus relays of the analog
point (AP) module and the v/F converter. Then it opens
the gate for the' V/F signal enabling the COUNT pulses
to the CT module, The gate is kept open for two cycles
of the 120 rps Signal. which is equal to one cycle of the
power line frequency.

TIl(' \'alues used in Fip;1lrc 1 arc for flO liz
operation. At 50 Hz opcration the following
valucs appl\',
20-1.8 kHz
1Il!1. (l

kHz

1I1l.1 kH7

~

Zero = -1096 pulses per
cycle
Fullscale
Twice fullscait.'

Upon closing the gate, the analog control circuit r;cnerates a trigger signal to the power supply switch on the
AC module. The power supply switch then opens to turn
off the analog POInt selection word and channel driver
SCR's.

NOTE: 245,76kHz
=4096 PULSES
PER CYCLE

The power supply switch delays clOSing to permit the
analog point selection relays to dropout. Then, the
power supplY switch generates an interrupt signal informing the central processor that the analog value
(output of the counter CT module) is ready to he read,
To inrut the contents of the counter, the digital input
huffpr circuit on the SB module is used.

-100

a

+100

+200

FIGURE I. ANALOG SIGNAL PERCENT OF FULL SCALE

Thc Sf'tt inr; of thf' sra il and thf' gain of thf' V IF conve rIel' is accomplished throur;h the SB module.
If hit 7
1()!lO~) is a "()ne" and chann!'! If) (thiI0, 6666) is inter1'''h'7lINl. thl' P"\I(')' supph switch on the CL module is
trlr;e-,'I,,'t! \\hl('h II til turn otf the ;;pan driver SCR';;
on the SB moduli'. The status of hits 0-6 (ODOO through
Ollil", Uplill Illt('IT()~atin~ channel 16 will determinf'
1111)('h span <1)')\'('1' sen's \\illlJe turned on. The sen's
\\hl<'h ('''nriul'l \\ ill then l'nerr;lze the span relays in the
V/F com'('rter.
The status tl! Ilits I~ and I:; (ODI2 and ODl:lj, upon
channel 1(;, will prOVide signals to turn
"il "I' "rf the f,!'.lin Ilip-flop on the SB module. If the
flip-flop is lurned "on", the output of the flip-flop is
'il" (PSe) \lhlCh prtl\'ides a current path for the gain
n'l.t\ ('oil In Ihe \'/ F C('il\'('rter.

interrogating channel 16, the signals on the input data
lines (!DOn through ID13) will be dependent on the output of the counter (ICTBOO through lCTBl:3). The interrogating I ilS pulse is transmitted to an input data
line only if the corresponding counter output line is a
Ilone".

Ref('l'('nce voltag('s from the CL module can be connf'ctcd
analog inputs for unft correction purposes,

as

Th(' C L module also accommodates four RTD hridge
CIrcuits (onl\' one shown on drawing flf)7C56H) which .. an
he used for measuring the cold junction hox temperatures.
The outputs of the bridges have to be connected as ana lng
inputs.

Analog Signal Conditioners

lillerro~tln~

To obtain the analog signals in the required range of
the analog-to-digital converter range (0-50m V or 0-5V),
or to eliminate other than line frequency component
noise, the following signal conditioners are used in the
analog input systems.

Outputting hit ~ (ODO~) ()n channel 16 (SB card) wil.
pI'(\\'ide at ilS puls(' (READ TRIGGER signal) to the
:lila lo~ cII1l1 rIll motiulf' (,-\C) , which initiates the analog
IIlIHII S(''1Ul'IH'l',

RTD Br'dges (Using 15 volt power supply for RTDt S)
RTD Resistance Span

1'h(' timilli' "I~na.l I'llI' the analog control circuit (AC
module) I;; "htailll,d from the phase lock oscillator
1l100U!e (Pl.) in the form of a 120 pps square wave.
\1 hich IS phase locked with the 60 Hz power line fre'1uenn. :'\ote that a ;-)0 Hz oscillator module is also
a\,aibblc (rdcr to PL card document).

2-7
2 - 12
2 - 22
7 - 12
12 - 17
12 - 22
12 - 32
17 - 22

Ill1ml'tii:Ilch followlIlr; the READ TRIGGER pulse (see

13-4

ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms

~~J

Part No.

610B249
610B249
610B249
610B249
610B249
610B249
610B249
610B249

G05
GO:l
G01
G06
G07
G04
G02
GOH

Low Voltage Fillc" (Time constant
MV signal. 1,~>No. 6R2B61'5GOl.)

RTD Bridges cont'd.

®

RTD Resistance Span
~o

- 70

-

120
220
120
170
220

682B4~0

G05
GO:1

~GNAL

GO~

I
I
I
I
I

Volugc Fil!~ (Tim(' cntlstalll
signal. ® No. 682B686GOl.)

PS.

~

I
I

I

(-)

_..J

Current to Voltage Converter (For 5 volts fullscale
fnr the following current ranges:)

1-[)
~-10

rna
rna
rna
ma

'+-20
10-50
200-1000 n~a
O. 2~7-1. LlCi ma
O. :l:3:l-I. 1)65 ma

ohms
ohms
ohms
ohms
ohms
ohms
ohms

61082':6
6108246
610B2411
610B246
610824r.
6108246
61082t6

I SIGNAL TO

I

I

ANALOG

I INPUT

HIGH YOLTAGE FILTEf? SCHEMATIC

ANALOG SUBSYSTEM LOGIC PRINTS

Dropping Resistor (!) Part ;~~
1000
500
250
100
5
HOO
3000

()-(i \ '

Each signal cIJnriitionpr ;s an mdi\·ldll:.;lh l'n('apsululpd
block and mnu:1tcd on thp :lnalng ;npllt half-shC'lIs
adjacent tn the terminal strips. F.l('h anal"g i'lplll
requiring special conditloniflg is l'quippcd Ilith th(
appropriate block.

-BLACK

FIGURE 2. RTD BRIDGE SCHEMATIC

Current Range

s I(,r

_______ .I______ ~

FIGURE 6

TO

+ RED

:I~,

I FILTERED

I

I
NOISY
SIGNAL I
I
IN

15VOLT

I

ANALOG
INPUT

I.

(2)--~AJV-----~----------~+

I

L_

I ANALOG

I INPUT

~h

I

I
I

RTD

I

FILTERED

SIGNAL TO

FIGURE 5. LOW VOLTAGE FILTER SCHEMATIC

-----,

2

,

~-------------------~

6H2 RL':O GO~
6R2B420 GO"

I

I
T'
T

:
I

GOI)
G07
G04

r------------9(+)
~-----

1.:12 s for O-JOO

Part No.

6828420
6828420
61:l2B420
6828420
6828420

ohms
ohms
ohms
ohms
ohms
ohms
~:W - no ohms
170 - 220 ohms

20
20
70
120
120

~

The follOWing prints are IncludC'd at the end of this dO('I1ment to show the logic connections of thC' c.II·ds usc(i in
lhe A-panf'l. Thf' nllmhf'r in thl-' llflflf'r right hand ('ornc'r
designates the location of that card in the A-Panel. Also
included arc thf' \nalog ll'ap cards which can bl' located
in any' panel.

GI':J
G94
Gr 1
G02
GO:,
GOI)
G07

T~ese prints arC' shnwn for:1 maximum (I cnnvcI·ters)
system. Less c:'lrds may be used for smaller svslcms.

2~----------~~----------~+

I

IN

Figur~

VOLTAGE
TO A~ALOG
INPUT

I
CURRENT I

I
I
3~----------~----------~

FIGURE 3. CURRENT· TO·VOL TAGE CONVERTER SCHEMA TIC
\'()lla~nividers - To r('duce voltages greater than 5V to
tile;) V range in the following ratios: 2: 1 (
682 86R3GO 1),
I I (~()~2B6tl3GO~), ;l:I(®GR286R3G03), 161 «(~

®

6~286R:IG(4).

~-----------------,

2

+
DIVIDED
VOLTAGE
TO ANALOG
INPUT

HIGH
VOLTAGE
IN

3~----------~------------~
FIGURE 4. VOL TAGE DIVIDER SCHEMA TIC

13-5

17
11'
19
20
::!l
22
23
24
25
26

!'io.

Drawing j\;n.
/ir;7C2!l1
",r.7C~!J2

,..G7('29::
";67C2!l-l
I'7C29~

~7

''',7C300
"Hi7ClOl

21'<
29
30
31
:12
33
34

8G7C303
1i67C30 I
H67C30S
1'67C30f1
1if17C994
kl)7C995

~f>7C:Jn2

i ..oglc Descr...!£!.io,!

Phase' LocI-; Os(' ilia In r
Analog Control Cal'd
Caliill':ltnr Card
III Span & Gain \\/ Buffer
~l COlillter Card
112 Span & Gain wi Buffer
#2 Counter Card
II:: Span & Gain \~/ Buffer
11:; Counter Card
#-1 Span & Gain wi Buffer
#4 CnuntC'r Card
Channd Driver (17)
Channel Driver (37)
Channel Dri\'er (57)
Word Driver 140-;'7)
Word Driver (60-r,7)
Analog Trap
Summing Resistors.

CONNECTORS AND TERMINATIONS

Plug 25 is wired as below'

A-Panll Connlctors

56 Pin
ELCO

Dra wing 77 4A 717 sheets 1 and 2 show the connector
breakdown on plugs A21-23 and A22-24 (Fig. 9 and 10).

X-Panll Connlctor Breakdown - AP Optlln

fi6 Pin

ELCO

MNEMONIC

:1S - :ll
:::! - :!2
:ll - :10

Z

AIR;]

29 - 2R

a

2:> - ~4
~:l - :t!

\Ii

11:1

X

111

y

II:>
H6
117
II~

c

IPI

d

AIRt
-\IR"
.\IRfj
AIR7

11111

k

:\ III S

m

.-\IRB
AIHIO
AIHll

h

III I
1112
III :1
III I
III :>
11 I r,

To :1:; Pin El.CO
on Chan. Driver
on A-Panel"

AIRO
,\IHI
AIR2

JI~

n
P

:\IIlI~

r

AIRI:l
BlISR'\'

1"
II
12 - II
I () - 'I
c
"

.

,

I."

]I; -

Back Panel
\\Inn~

I;

HI7
1117
HI7
HI7
H17
HI7

7

1117

s

H17
H17
H17
1117
H17
H17
H17
H17
H17

,

:,~,

!J

10
II
!~

1:1

II
l:i

1/;

A
C
E

H
L
1"
H
f'N

LL

.JJ
FF
CC

AA
Y

W
T

MNEMONIC
WD60.40
\\'061. .Jl
WD62.42
\\'063,43
WD64.44
\\<'065,45
\\<'066,46
\\'067,47
\\'070,50
WD71,51
\\'072,52
\\'073,53
\\'074,54
\\<'075,55
\\'076,56
WD77,57

:IS Pin E LCO
WD Card
35 - :l!
:1I - :!fl
27
23
15
11
7
3
33
29
25
21
13
9
5
1

L2
L3
L4
L2
L3
L4

Figure No.

Drawing No.

1:1

1l82BfiK,j

J.l
15

682B6H7
6R2B6HR
IlR2 B6!)O

III

\ \ PC:.ndL

Pin

L4

Slots
Slots
SIot8
Slots
Slots
Slots
Slots
Slots
Slots
Slots
Slots
Slots

1

;,
:)
;.
!.'
!)
!)

1:1
I')"
I::

-

"

"

- 12
- 12
- I~
- Ifi
- I"
- I r,

The following drawinf:(s show the recommended anal()~1
input termination schemes for each type of analof:( inpu

Plugs 22 and 2·1 are wired in parailel as below:

S6 Pin
ELCO

i.,2
... 1
IA
L2
L3

Drawing 682BIl89 sheets 1 to :1 show the analo~ inplll
standa rd term ination scheme used when the re is I1Il
T.le (Fi!-:. 12a - !') .

K-

I -

E
F
H
L
M
N
R
S
T

(n)
(n)
(n)
(n)
(n)
(n)
(n)
(n)
(n)
(n)
(n)
(n)

Drawing fi0939-:"~) sheets 1 and 2 show the analof:( Inpll~
standard termination scheme used on TJC (Thermal
Junction Box-Cold) (Fif:(. 11a - h),

21 - 20

Ii -

(AP Carrl)

Terminations

27 - 26

·Could he slot A12. 1:1 or 14
depending upon channel to be used,

(';Il'd
Slot

Plus
l\linus
Guard
Plus
Minus
Guard
Plus
Minus
Guard
Plus
Minus
Guard

A
B
C

Plugs 21 and 23 are wired in parallel as below.
Hack Panel
Wi ring
(.-\P Card)

Des~jn[,t in!l

IVTNEMO~IC

-

26
22
16
12
K

ol
:12
28
20l
20
J.t

10
6
2

The \\'0 card is in the A-panel slot
A16 for words 60 to 77 and in
slot A15 for words olO to 57,

13-6

.

..

Type ()f_~1
Th"l'l1""">l'I,I,'
RTD
Voltaf:(e S('nso rCurrent Sens() r

S(""5C
50 "AT.: elF
.?AD D,Q,Io'C."

.. 0 - 5"

,

", I
'I

"

~I

.

.

~

--

1 ....: ""

c,

-

-+f----

r'~rOI,r/04'''_r_

~~~--

KlllL~

A.t ... ","(
~ C

~" ... T"C. T,)

0"" ".,,.

C .. ao

NOTES:

1f
6

So O'S

FIGURE 7. A;I SUBSYSTEM BLO(K OIAGRAM (REF.

(100 "D'S

~o.

SO '-"S

srsTf.,.

A5~I~NAotlNT of THE AlNALOC; S'~NA'I
~ / , Auss(s, R,l.'IW
TO SrST"€MS
D(SCIt.I""'."" "AJtT 3lr ..
FoR.

To

owe. 867(567,

THt

SUB 31

r. )

,.,
((. •••01-,>-1-+-----------'0-

'TO C" ' l
T.. au ,.,.

•

,-----

T~""'''SJ'ORMUl

NOTE:

Pl (,.,rt (4)A.'!!3C.01'
fOR

~O

THE

~u-r'uT

(f:'

LINE

FtI:{Q

WL>..l

BE

\~

- - - - - - - - - - - -ll

w5El'

I

T,,'-I('(Fr)~t

I

.eo PP5.

,"C cy

t; -ltwt

PIIQ
',qq~r~-t!'.'~~~

f.••

_ ~----..I~'SO
."S
1'~lO~~----s~~~~
SEQuENC[R.

L __

p
_______ 0~W~'.l._L_

.O!>

--.I .. ~v£ L.. _ _ _ _ _ _ _ _ _ I

FIGURE 8. A I SUBSYSTEM FLOW D/~Iji\AM (REF. DWG. 867(568, SUB 3)

56 - PIN
ELCO
CONNECTOR

DATA
LINE

A

100

B

DATA
RETURN

I

56 - PIN
ELCO
CONNECTOR

DATA
LINE

h

IDRIl

DATA
RETURN

IDR13
OD13

J
I

C

101

D
E

lOR 1

J

L

N

R

.....
ILl
ILl

:z:

0011

V>

r....:

p

103

r
tOJl~

OORlO

I

I

IOR4

v
IOR5

107

...«

OOR9
009

u

105

.....

.....
.....

0010

~

104

P

OORll

n

106

M

0012

m
IOR2

K

OORl2

I

102

F

H

k

OORB
OOB

w

OOR6

~

OORl

:z
~
o
Q
~

«

IDRl

S

IOR6

I

IORIO

OD3

FF

006

HH

1011
10Rll

JJ

IOR12

LL

. _ . III

OORl3

II
13-9

NN

001
nnDn
v.., .. "

ODD

LI

..J
ILl

ODRI

mm

.....

LI
ILl

002

.. II

IUU

OOR4

:z
:z
o

OOR2

KK

1012

o

OOR3

EE

Q::

OOR5

OD4

DO

1010

d

e

CC
IOR9

b

c

Q::

DDS

BB

109

Z

a

A:IDRB

X

Y

I

lOB

V
W

ILl

ODl

II)

...
U

Y

:z
«

0...

«

-

...

...

n

...

.

n
Q

N

-<

><

~

<

c:

-I

en

:.0:1

~

Z

~

r

~

Co.

:z:

~

rn

CI

n

a2

~

zrn;':
Zrl
rnn

~Q~

CI
:III

Z

:z:

~n

a
a
.....
a

a
a
'"a

a
a
I.ft
a

a
a
....
a

a
a
a.....

a
a
a

'"

a
a
eI.ft

a
a
....a

a
a
'-'
a

a
a
IV
a

a
a
a

a
a
0
a

a
a
ew

a
a
eN

a
a
a

-

r:z:

en.

a
e
a

,..~

rn z
rrn

0

~r
-I

z

......

Z

~
~

r
r

~

~

Co.
Co.

:z:
:z:

~
~

1ft
1ft

CI
CI

n

n

IJ:I
IJ:I

~

....

'<

~

.

n
:IE

<

c

-

'"

-

'C

:>

3

~

I

-

... -.

CI

::r

2m::
Zrl

'"n

~Q~
CI
:III

......

o

e0
a
a

a
a
a

a
a
a

IV

aW
a
e

0

a
a
a

a
a
a

IV

a
a
a

a....
a
a

W

a
a
a

a
a
a

I.ft

a

'"aa

a
.....
a
a

....
a
a
a

I.ft

a
a
a

'"aa

a

Z

:z:
~
r
"a:
enQ
'rQ
" :III
n

.....

a
a
a

'"
-I

e 9 00(!)C0
0(!)®(h)0G)
r;--. 0 00 f'b\ IS' If\

~
@\:Y8\V0~

VV@'U@'-VG)

e e 0 0 t;;\ 0 G) 0 G) ®0
eeO@'V0\!!!JCD0\V@'-V0"-V@
Q

t;\

G

G)

fu\

0

CD 0

I'j\

0

FIGURE 10. A-PANEL CONNECTOR BREAKDOWN - A22-24 (REF. DWG. 774A7I7, SHEET 2)

J

Nf)TfS (TWO CABlHJG OPrIOtI5)
I CARD EPC;E 10 lERMINAL BLOCK

FIGURE 710.

TERMINATION SCHEME· THERMAL JUNCTION BOX·COLD (I?EF. nWG

6098979, .~HEET'

SIJ8~)

ONLY

CARD EOGE(35 PIN ELCO) CONNECTOR

FRONT VIEW OF PANEL
Iilifj

a)
CONN.
PANEL
LOCATION

~
A

~~ 1(01:8
Q.

~

<

56E

'"

3
LOCAT ·0'15 .:., "
H, AND F, ARE
RESERVED FOR
PARALLEL
C(J\jN. PANEL

f;;---, r---H
B

I I

J

I l

1,4

3

N
./

-

/

~

'"
'"
:2

TERMINAL TERMi" '-IN EL(X) CON~n: ToR ~PPIM7 RESI5TO;f;' YOLTACE
[l'YIOER NETIfOf'K /II1T AvAILAllLE I/IIYEV TillS CA8L E _oPIOY t/sED

RlFUl.A'lll

DR.AWINr.S

FOR

lUSTOMl·'. CONNE.C TION5·

&Bl8!.BB-RlCO"'''''l',OE.D IIN.,OG
VOLTAGE. SE.NSOR

!NP~T

(,e2Bio90 ·RE.CO"""'~"'O~D ANALOG INPUT
CL>"'RtN~

SE.~SoR

FIGURE 120. STANDARD TERMINATION SCHEME WITHOUT TJC (REF. DWG. 6828689, SHEET 11

TERMINATION

SCHeME.

~E..R.MINATION

.-c.t-'lE.

T'f/S JUMPER 15 P4RT e]C
CUSTOMER - =-<'M/NAL IVIRIIvG

AjL7~~~~t£QillJ:i£f~~J M
(,UARD SHIELD 8US
cQR )NGIl)lJN/)E~
... :. r j , . ,L
41(,:) 8115 II'" ,AS "I" r
FOR ,JRO{)N£JE£J NPyT 0,,', ;lC? J":'UI',;£) vuARf) 8::5 ~'LAbINET

RTD PS 1<1-"

,II

NOTES:
I, GROUNDED AIVD ljNGROuNuED ~TD5 ,4"1 NOT BE i5t,CcJ
'"E
SAME ANALOG Il\I'f'tIT :;ARD.
2 "'HE TWO ."A8uNG OPTIONS ARE:
/ CARO E£JGE TO TERMINAL BLC.ICk C:-NLL
2 PAIi',4LLEL CABLlI\I'G eMD E'XE TO ~E~M/NAL 6. ~J< -lND
8LOC/( ro % "'N £1,°(1 C(WA'ECT{)R,

c· )
DR.A."" ,.c,
COQ
.JS'OM£''''
1.>826",87' RE-CO""ME"~EO AN.\.O(,

RE.~LRlNcL

';C>

I~ ~~
~l~ l~ -;::.
~

II ~
J

~
~

.

5"~?::. t p~:;l:5'ir :"'AB~ w ~ PAIf',-ILLEL

~

~

~

'c'AT,vN f-

PA.tc". h)

.:J4R4LLEL

~cRM ,V)

,j] c

l,WEI;.;

~A8 1'J

-- - - ,

P4K"_J:..5.o
GEYEP4L
,Oh'
I)

ttl

_'ON"

02.!G U(JKI4)APT

n}4P/l)(r)

cJ4RA .. ~L

-----~---,-

TyP IC4L
Ji03PI3 OR ....~R.l16

(7)7>)

ASS

'y

cr OT>'{ER

TYA!"

"iT;

E

\
tl:,/("r-\

L

HA,:r

')"'1'E .-...:.

REAR OF CA8.

FIGURE 12e. STANDARD TERMINATION SCHEME WITHOUT TJC (REF.

u :) 8

n

y?

4r-121JIi

5 .-C T

ORDER

5/

4-YD PNL

PAI\IE L 8UILD,up

owe.

7 i 's

END OF
CA8LE

l: 1~ =-5.L' :' #LI: .3.!.1' '2. .L' - j:': IO: .Jc: 9:. . L5"""'v
B,-,-,~:. . L' ' ' ->/v~-v
).l.5' -6L:041LJ~A~1,

\.. fltl'cti
Is.r ""NL j

PREFERREO A4I\1FL -TERM ASSIG"'.

--~-

ELCO.h.:rwN'aA'T

tUXATlO'l-

COV;\'

h- ,''':'

~'Cl'YV

T' r"'RM~'Y4L rANL Y

C'11\i

;::nu~--.'!~

<>.,

'AtiL

-~~----

ryPICAL

,,){n)(») (.I)J,

,.1
OJ)

LaC A TIOtl!

-'C"?MI,1,Ai ,_J.lALF SH~ '=_ /'OF/VT

r--

r-

tCAR~ W;;;;.~%N~ 7;$%E

LOCATiON (IF' OT-'fEK END OF CA8LE
CABLE ASS Y tyPE

£JANEL

t'::::P,-t:c

)

'CO

F

4,1,':4

,t.. " ~. ~\ t~
'"

•,

S':OT

J.4 Pc:"- ~AP~' 75

("J

CENFR"h

','

~

CA~D

~

"

,)

~

,h)E",

CABLE .; CO tN

PA'<'EL

~

~,

'"

~

l

"" - ~'
r~ r- r- r-- t-- f',, r-~

" '?'," f'< '"i" " " ,;::""

,~

~ ~Ii; ~

'
,,~,

WC ArO\5AJ.Nt
;\> 4RE RESERY'€D
COR P," S

THIS ::JiER(l'.CI:;.
SHffT 1- GROuNDe') loT SEtJSOR,
A SINGLE APCARD/HALF SHELL.
I>,OVIDUALLY SHIEL OED ~IR LEADS
I. 00 NOT MIX GROUt.DED A,ND
UNGROUNDED -, Ie .
GROUt.DED \f'~ 'w\El.L....
2. DO riOT MUL,IPLE ~uND AllY
SHEET 2' GROUNC1:0 AI SENSOR,
SHIELD ORA I NOR c:Er lSOR
MULTIPLE PAIP SHIELDED lEADS
WIRE.
SHEET 3-GROUNDED IN PLANT t\JEAR
3 ALL -,Ie AND Sl'iI ELD DRAIN
SENSOR AND,.Q;! MULTIPLE R>.lR
SHIELDED LEADS
WIRES OF1l!IS GROUP(14) MUST
BE GROuNDED It. PLANT ~O
SHEET 4 - UNGROU~IDE!) Itj PLAN!.
INDIViDUAllY SHIELDED PAIR LEADS
Lcx:ATIONS WITHIN"3V DC/RMS.
SHEET 5-UNGROuNDEDN PLANT,
4 CONNECT ONLY ONE SHIELD
MULTIPLE PAIR SHIELDED LEADS.
DRAIN WIRE TO THE GUARD
"'ELO(lERMINALS J)J,6~",) ~

""'J50'"

.~

~

. -""'D5

·~R(~D

IN WELL
r - ....

-- SEE

~' ..

"-,-

!i'l
ex

;;i

zl

°1
f-

:)1

21

4

~I

(YI
~I
~I
~I

19

o

t

u

cD

-L

If)

0

r.

lO

'"

_'C-

~

f-

)(

Ii>

IfI'i

-r
0

o

~~

Ii>

iO

N

r

~

O~l'r-

J'

r-6

(ij

~2 i\J~

'11+'J

-) J

+

\

-, J

\

\

\

I '.

~ in ~~ ~1:1
Xx:x.xX>t;

,} ,1' l' l' l' l'

~s~ ~
DIN

I

, ELCOI

PA~LLE~ j -"
OPT"lol\,

FIGURE 13"

,=r:,."OCOUf'LE INPUT CONNECTIONS (REF DWG

6828684, SHEET' 1)

THF PMOCOUf-'L[

"F?nUtJDED

~r

Nor - SHEETI CF n-IIS DRAWING ARE

SENSOh

MIJLTIPLf PAIR SH1t:LDEO LEADS

IN ORDER OF PREFERENCE.
SHEET 1- GROUNDED A' SENSOR,

TIC (C,ROUNDEO

INDIVIDUALLY SHIELDED >=AIR [.fADS

'NELL

__ SEf

~ECAUiION

I

NO 3

SHEET 2-GROUNDEDAT SENSOR,
MULlIPLE R>\IR SHIELDED LEADS.

---

J UNCTION BOX

(IF USED)

MULilPLE

I>-

o

PAIR SHIELDED LEADS.

\D

\()

o

N

o

o

t-

t-

t-

fjjj

o

ell

iD

It)

~

W1RE.
ALL itt AND SHIEll) ORAIN
WIRES OFTHI5 GFnJP(\4) MUST

BE GROUNDED 11>.1 R..ANT TO
LOCATIONS WITHIN 3 V. DC./RM5
4 c:x»JNa:T ONLY ~ SHIELD
~IN WIRE TO THE '~UARD
SHIELD(TERMINA,LS 19 JI6 tK9-1<16

o
o

fjjj

NLMBERS
AN ALOG

p().j-

\fl'

<

X

<;;'
X

l' l' l' 1'1' 1'1'
f¥..RALLEL
OPTION

FIGURE Ilb.

Tic.

2 00 NOT MULTIPLE GR()JND MY
SHIELD DR .... IN OR SENSOR

SI.lEET 3-GROUNDEO IN PLANT NEAR
SENSOR ANlWR MULTIPLE PAIR
SHIELDED LEADS
SHEET 4-UNGRouNDED IN PLANT,
INDIVIDUALLY SHIELDED R6-IR LEADS.
SHEET 5-UNGROUNDED IN PLANT,

SEE PRECAUTION 1>.104

00 NOT MIX GROUNC£O ",NO

UNGROUNDED

GROUNDED :N WELL.

THERMOCOUPLE INPUT CONNECTIONS (REF. DWG. 6828684, SHEET 2)

THERIV'()::X)UPLE GROUNDED ;11 PLANT NEAR

AND/OR MUL,IPLE

.JOT - Sl-IfE""'"S .::'~ THIS JRMilNG ARE
IN ORDER 'Y WE~RE'JCE.

~nJs:::,q

I'¥IIR SHIELDED LEADS

~;:::CH-:-:E='E:::T=-':':-:":G=::R:"'O~U-N-=DEC=C'::-':A~T:O-:-=-SE~rJ~SO:-=Rc-,-~ A SIf\.GLE AP CARtVHALF SHELL.
INDIVIDUALLY ;HIE~DED ~R LEADS
GROUNDED IN WEL~
S~EE, 2'GROUNDED "', SENSOR,
MULlIPLE PAIR SHIELDED LEADS.
SHEE' 3-(R.)utJDED IN PLANT f-le-AR
SENSOR AND/OR MULTIR..E PA!R
SHIELDED LEADS.
SHEET 4- uNGRoUNDED IN PLAN"
INDIVIDUALLY SHIElDED RAIR LEADS
SHEET 5- JNGRO..NOED IN PLANT,
MULTIPLE PAIR SHIELDED LEADS.

~
zl
ill

m

~I

ALTERNATE GRD IF CLOSeWELL(SEE PRECAUTION N:). 3)
DO NOT GROUND OR JUMPER

Zl

l-_...l,-,f-t-- 5EE PRECAlJ1O.l ~ 4BOX
AT HEAD AND BOX
:: _::::.:~ _ _..--J

01

~I
~I

; APPLY O'-JLY 10 A

GR~O~U=p~CF~a'N~PlJ15(''')'''SSIGNED m

I DO NOT MIX GROUNDED AND
UNGROUNDED ,Ie
2 00 NOT MULIIA..E GROUND AN'(
SHIELD DRAIN CF SENSCR WIRE
3.~ TiC AND SHIELD DRAIN
WIRES OF THIS (R)Jp(14) MUST
BE GROLINDED IN PLANT 10
LOCAIiONS WITHIN 3V OC/RMS.
4CONNECT ONLY ~ SHIELD
DRAIN WIRE m THE GUARD
SIHELDtTERMINALS J9-JIGtI<9-i<16

~I



;>

WI

0-

~I

0

tnl
:::>1

il>

0

~
t:

CO

.!l...L-

.:

pC)

(\J

0

0

0

0

t--

r

CO

CD

'ell=

f-

t:

lJ")

0

as

HALF 5 lEU
TERMINAL

SCREtJ
NUMBERS

\

\

FIGURE 13e.

THERMOCOUPLE INPUT CONNECTIONS (REF. DWG. 6828684, SHEET 3)

(l)

0

c
t

II)

~J

CI!,P~E UNGROUNCE;:: '''< PLANT
INDI jllWAL, Y SHIELDf" "'''R LFADS

SHEEIS CF THIS DR "WING .... RE PRI:c.PoUTa6:1 APPLY ONLY TO A
(,R0i..f=> CF INAJ1S(!4) ASSl6NED 10
NORDER CF Pl(EFFRENCE.
SHEET 1- GROUNDED AT SENSOR,
A SINGLE AP CARD/HALF SHELL.
, DO NOT MIX GI<'OUNDED AND
INO!\ilDUAu...Y SHIELDED PAIR LEADS
GROUNOffi IN WELL
UNGROUNDED ,Ie
2 00 NOT MULTIR..f ~D ANY
SHEET '2 -GROUNDED AT SEN~.
MULilPLE qA.IR SHIELDED LEADS
SHIELD DRAIN OR SENSOR
SHEET 3-GROUNDED IN PLANT NEAR
WIRE.
SENSOR AND,oR MULIIPLE PAIR
3 00 NOT GROUND Tic. OR DRAIN
WlR£S IP\J PLANT.
SHIELDED ~EAD5
4 CONNEC, ALL TIC AND
SHEET-4-UNGROU'JOED IP\J PLANT,
'NDIVID'..JA~~Y SHIELDED PAIR L£A03
SHIELD DRAIN WIRES TO ,HE
'JHEEI s~ ur,SRJuNOCD IN PLANT,
GUARD SHIELD(TtRMINALS
J'3-JIf, ¢ 1<9-1(16)
MUL'TIPLE R<\IR SHIELDED LFADS

1 HfR""CX

-;r
~I
~I

PRE! ERED
'=CNNC~':JN

,Ir

"E A,O

,)~fD)

31
~I

8,)X

"I

(

a.~I

......
W
I

......

c.o

I~ IljE:';)

.{I

0:1

~I
~I

3RGUND
5.-- '"Tko

c,
----w

-

Cio

o

COMPUTER

8::ABI~jET

l'

~

'v
()

t£ll

III

~

r0

f::

::D

~[[~l

f

N

o
l-

ii)

o

o
I-

o

(D

r-

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'[illl)
l' r"'tf~ ;, ~
~

!~,

- 'v
,

x

tL

,J--

H

X

><

"')K

0u,......,
"-.J rv
~
"<

"t"" Ul

('v

X

[\.1

><

")0<

'><

:...:.

lo(

t~~~" ::'::~~~,::

(,IJARD SHIELD

FIGURE 13d.

..-<.

Aa.D

"C,~_·.

:[30)( AND SE'Rv'ES.-NE AP CARD OF 14 INFV'rS(BITS O-I~:

THERMOCOUPLE INPUT CONNECTIONS (REF. DWG. 6828684, SHEET 41

P'\RALLEL

OPTION

T~ERMOCOlJPLE

LNGROUNDEO IN PLANT
SHIELDED LEADS

SHEETS OF Tl4IS DRAWlNG ARE
ORDER OF PREFERENCE.
SHEET 1- GRCl'.»JDED AT SENSOR.
INDIVID~LLY SHIELDED AIIIR LEADS

NOTE
IN

~IR

MUL,.IPLE

G~NDED IN WELL.
5I-4EET 2-GQOUNDED AT SENSOR.

~
cr

HEAD
COMPUTER
CABINET

8

~ROUND

:::;

UNGRaJNDED T,t.
2.00 NOT MUl:tlRE GRO.»ID /J.NY

R:

«
(}'

~

\u
~

(l\

~

0

~

rC

ID

0

t
Ql

~

1/1

0
~

Ii'l

~

(jl

t

t-:

m

.iiI

'"0

0

Iii

II)

r

~ALF~ELL
TE~IW.L

SCREW
NuMBERS
ANALOG
POI/IIT

CARD PIN
NUMBERS

\
"' •

\

\
.n,l)

\
"-II)

flo. SINGLE AP CA~AALF SWELL.
I. DO NOT MIX ~OED AND

MULTIPLE R'IR 91IELDED LEADS.
SHIELD DRAIN ~ SENSCR IH~
SHEET 3-GROUNDED IN !=LANT NEAR 3 00 NOT GA()t.,t.I() Tit. OR CRAIN
SENSOR ANO,bR MU01PLE PAIR
WIRES IN PLANT.
S~IELOED LEAI13.
4 CONNECT ALL T/C AND SHIELD
SHEET 4-UNGROUNDED IN PlANT,
~AIN WIRES TO THE GIARD
INDIVIDUALLY 94tElDED ~IR LEADS.
SHELD(TER'.UNALSJ9-JI6~
S~ET 5·UN~ IN PlANT.
MULTIPLE ~tR SHIELDED LEADS.

~

z
o

APPLY ONLY TO A

~~~~~I~N~=~"')ASSIGNED TO

mQ

lII(lo()o(.)oC.~X)<)(

ttttt1tt

FIGURE 13 •. THERMOCOUPLE INPUT CONNECTIONS (REF. DWG. 6828684, SHEET 5)

~

NOTE ~5I1EE73 Jr r",o iX'AWI,\.G A~ A«'ECAU77CW5 :/,#RY iWLY m A
IN ORDER OF PREFERENCE.
OF .wA:Irr(;'#A5S/~tzI
SHEEr /. GROUNDED IN PLANr.
A SINGLE AP CARD/HALF SHELL
INDIW£VAUYSIllELDE£) R'fIR LE£l5 "'ND A COMAt:W PrO RJIfEil? St/P/PLY.
54E:ET £' GI A";'",'
""IRE
MULTIPLE ""IIR SNIELlfD LEADS
3 Au -'tANT ....,ULNas :J~ hiS
WTE BJ- 1fT[) <"W/~ 5 AKlilNTED
';!?OuP(i4j 1.1(.,5/ BE fi/ITh'IN .3 v.
~}\ 4~~· .54CLL 4NO WIRED Z'7
A,'AfS/oc ,I? TI£/) 77J ~ S>t~E
TERMIVA. ~,'R£K. /41 ~A(70RY,
JROUND eLl;!, .I

Ia.avo

GROUND WIRE

"10 STRANDED
(jROt/VO

4 C:ONVEC T EAOI CABLE ~ WWE
ro f73 SE,V50R ~n:wo.
.::: -< WNECT ,WL} !WE ('ABLE ORA",\,
I~J"': TO TilE CUARD V"ELj)
(TERMINAi.S A-/! *2)

i

L

-~-

----

m

~~--

-

.-

OD/ICW

FIGURE 140. RTD INPUT CONNECTIONS (REF, DWG. 6828687, SHEET 11

RTD GIitJUNDE1J IN PLANT, ,ffU77PLE rW~

S'/lIELDEO L£ALJ.9

NOTE A SflEE73 ~ 7iY1.S MAW/At> A,fE' &£CAlI77~: ,m:ty CWLY 7t) A
IN ORDER OF Pl<'EFEREI\f:E.
OF 1AR/TS(/-I)IISSI(;N£L) 7lJ
S/iE"Er I. GROLINLlED .w PLANT,
A SIMUE AP tJlfRQ/NALF SHELL

CROUND WIRE
-;0 STRANDED

MINIMf/M SIZE RUN
IN SAME CtlNDtIIT
MIN 8tWlJC.E WI77I

LOCAL JUNCTION
BOy(IF lISEJ))

ALL RTO LEAPS •

I

I

~:
~I

~ I

~~I
~~I

~"I

~

IND/Vla/ALLYSIIIEl..DE.{) PflR LEAlli AN/) A CO.4IAtiV RTlJ RJJIEl? 3:lAPLVI. f» M?r AllY G/lOlIAf)El) AN/)
l!IV(;~OlIVCED SEN.st:M'5.
2 txJ NtJr MtLT/PLE (j,W}(tNl) ANY
SIIIELD DRAIN OR SE~ L£AI)
£IIEET4.UN(]ROfN)ED IN tt:N.?;"
W/~E.
MUL71Pt.E RflR SlltE~ LEADS
3. ALL PLANT GWCAn5 O~ ililS

SHEET R ~~ IN RMn';
MilLllPLE /14IR ~/EL£ED i.£A/)S.
SIIEEr~. ~ROl.N~D
PUfNT,
INDlVlbUALLY S!lIELLED.cJ41R f£AlJ5.

*

M:JTE 8 -

KTl)

Mla;E IS MOtwlED

.:IoRObIP(?.,r)Mt6/ EIE Wm.vN .3//.
RAtS/DC af' T/tlJ 77J II SltY(J,t.E

OV !lALF S!lELL .4IVD WIRE£) 7lJ
TERMINAL SCREWS IN FAClrJRY.

t}lViJNb A1INT.

" CONVECT EACII CABLE Lle4W WIfE
7lJ n:5 S~ ~D.
5CLWNR:r CWLY !!Y§ t!A&.E /If?AIN

~I

~I

f

WI!?E TZJ r!lE ~ S/#EL./)
(rERAfINAiS kl (' KZ).

I

!HLF SlELL

\

't- - - - ., R4RALL E'L
t-'i> AlN I

L ~t;!?-..J

FIGURE 14b. RTO INPUT CONNECTIONS (REF. OWe. 6828687, SHEET 2)

OPTION

NOTE IIkHEE73 ::JF TAIlS MAWlA-G A~
IN ORDER QF PREqREM::E.
5HErr /. GROUNDED IN PLANT,
IND/Vla/ALLYSHlE2!JEL) R'IIR LEAll$
5HEET 2 :;mkV~D 1# A:A-\I7;'
M!JLTIPLE PIIR SMELa"D /..£ALJ5.
SHEET 5 UNJR{lUVOEO IN PLANT;
INO//IIOUALLY :;IIIEiLED I14IP :.fAD'i
'SHEET 4. UNGRuUNOEO IN fL.it'vT;
MULTIPLE #lIR SHIEL.£El) LEADS
WTE B J - R7ZJ BRIDGE /5 ~U,yrE0
yV 41.F SHELL 1NO WIREO TO
TERMWAL 5c'R£J16 IIY ~AC7ORY.

PRECAU77QfVS:IAfR-V LWLY 7l) A

~ OF~(/~t95S/~ m
A SINGLE ~ CARD/HALF SIIELL.
,lrND A COMAtl1/ RTD RJJ(£R $PPLY.
/. [XJ NOT AllY (].ROUND£[)

AND
UNGROI..Nt:£D SEIVSlWS.
2 (XJ NOT MtlLTIPLE MOUN£) ANY
SHIELO fJRAIN OQ S£M'M LEAD
~/RE

3·.otJ Alt1T C.RCt-W.o C4i3LE
,OJZ4;IY5' /N

"~ANT

1{'uA'NECT EAcH C4&~ /)1<.4/#
/IIiA£ TO ITS RTO

.5 ('C1tNECT

ONL y O,"?, C4f3;.£
:7R4 t' #IIi'E 7[? 7HE. CUI'tAO

SHIE.O CTn?MJN/l..s J('/ <;' k'2)
6J//YIf'EI? KI Tu .(;2..
'--

-------

-

-----

,.

1 yAHALL

15tCJ ,L)/Io/ I

I ~LCcJ_)

FIGURE 14c. RTD INPUT CONNECTIONS (REF. DWG. 6B2B6B7, SHEET 3)

<"-

NOTE AkHEE7S OC 7ifIJ5 L>l'AWIM7 ARE M"CAumws:/NRl" t:WlY 7D If
IN ORDER OF Pl?Eq"REM::E.
I G.«VP tJF~(/#ASSI(JIJEZ) "1lJ
SHEET /. GRO(M)ED IN PLANT;
A S/~ AP CAIll¥N.4V SHE"-

INDIVIa/AUYSHIEUJEi) R4/R IEAUi AN/) A COMAOV RTf} RJIIER ~v.
SHEET 2 GI 3

-r

Tf,I,.:,

~AMIYC'(4:

~.!'''E~EI\C'::.

f!'E_;lJ<701\iS:IAfPLY OA/lY rc; A

cor ItYHJ:rs-(4)A5Y();YEf) m
5.,EET,' ';,.,¥)ONff/J A;" SEN~<.H,
A 9N~ >{PCARL'/IIALF ,HELL.
\~";v"!,[A':;' ~,..,;£~ m1R1£405
I.£V /lOT MI.\' c.,fitXtNLJELJ AND
~4EET 2 JR.JUND£) 119' -,-.;::~~
LW]f:'OUMJE2 ~;1/SJk'5 .
MD/OR ~"TlPi.E /;4IftIEdJED P OJ NOT Milt TIPLE !JI{[)S.

(;ROUP

SHIELIJ D04;N OR SENSoR LEAD

:5HEET .3 ~ I1!G'AfXWiJE£

I,

PLANT.

WiRE,

',Ln.. Q A,,':) >'fIE! .'5) -:4lk'Lb4iJ5. 3 ALL .-""L4NF ~VJ\/D5 OF THIS
SJI&C'T -1 ~NuR<}GNff.? /1, PLA;V;.
GRouP!'"',~
~<'
3 V,fMS/L/C OR TiED TO A

~LL(ln~ ~A~_ -'HkL~ I.fA~.
'Vc'TE Et-'J/pli _U',u T ,c.,1,_{5 A,t=
.,. ·V'..-'Ef:. ,: ~/U:1AL nt.W 3£ .. ,;"

..-, !E~'5 A/f)SYS~,,*1 RANGE.
) -",4" .' ';"'70,,,E4" £M~VD
~t

~-J.•

j ..

TE RIW/,1-1L

OL 4M IFff':; r~
: ' . 'RF~' IN ~A~' lGU) •

~----------"

SJNGLE CROUND /l:?'J\/r
4CONVECT EliCH C4BLf' OMIIV
WI"i'E

TO iTS

'o~,,,,
'}-':"D

SENsoR GROUND

0rr C48i.E
wlr?E ro r#E @-L"!RD
,r.cR'1',VAC; XI'; K2)

5 C!}/v..vECT

O/vLy

--- -----_.-._- ------

FIGURE ISo. VOLTAGE SENSOR INPUT CONNECTIONS (REF. DWG. 6828688, SHEET I)

VOL ;ACE SEM'CW

NOrE J11SfrEElS X TfllS f)l.'~MM A,(£ !1i'ECAUnO,4Q:jARltY ~y m If
GROUP OF J;VR/TSf/+)A551aNEP fl)
IN OliVE*, Y
rlf'.FrEREM:E.
A .9N~ IfP CA/U)/ HAlf .:iHELL •
5HEET 1 ':;,«JUVf.lI:O ~r SE/I'5
LElfOS .
SNEEr 1. uVC!n'lNf)Ef) II\. PL.M'f.
WIRE.
INLI'V/WALL; ~/ELOEJ) ;1//R LB4LJ5. 3 ALL ?4'M'r &?A'M';f09 OFT-,/Ig
O!;Jup (/~) ""f/gr 8E JIIlrlfiN
SJIEE7 "" UVG~a:O 1-1/ PLAIr'T,
3Y ~tX iJ/f T7£LJ rt? A
MUT!PLE PlflA' 5,4(IEL£8) LEAOS.
!3/,A/(J1£ ClliWINO ~llVr
NOTE
SIGNAL CUVMKWE6 ME
4,
(JONIIEtT EACII CAI3J-£ awN
PROW£l:O I; SlGilAL nitW SEI1&W
WlAE 7'0 /15 SB'ISOA (jI?()tI/vO
DCEEeS AI£) SY-SlB1 RANCE.
S. CtWNEcr o#£!' ONE eA~E
SIGNAL CCWorrltWER IS Mcr.J4l7FD
~P.AIII/ J+"/A£ TOT-#E {ll./AI?/}
ON HAu SHELL AAt m'~j) 'T()
SIffIE/.L) (ff/VWII'AJS KI'; K.2).
TERM/N4L SCREII6 IN FAcTCJRY.
S/fEET!? :1-WUNO&:? NEAR*N.,X:)('

I
I

I

Ai rclVl-frE ()AOVNO. IF'

~:

/CIQS£ W SE.It(9OI'? (S££ ~
~~L-J_, ,P~CAtJ77"N'#. 3. 00 ~:
;1/oT tJliClV-1I".:J AT Sf$C!1i
-:- A#013C!J..

1-

BT

.-

/tALr SNELL

'1~rMN4' ~ •
sr::£EHI ~

\

\

'5~R-N '1 ntRALLEL O"'TICl1I
:_____
EL('tJ JI

FIGURE 1 Sb. VOLTAGE SENSOR INPUT CONNECTIONS (REF, DWG. 6828688, SHEET 2)

V:;i rACE ~orA65P y, ·vG~Ji.u1; -:, ~ A
' ..4: r
//jI{Pf//£!kA",.:. y' g/l/E~.EO ,PA//f' .L.EAOg

....... )I..}A:

JJt_'?7J1/

B,)X (1'£ "S~~/

,.l~--,.~"=-E'"5 _,c TH,:; ~"'IYIM> .:~ If =>'"v170;1,;.i : /,4q'a ONLY ro A
//,O;l:j)Ek ;.r MOF~E~:M:E.
''jRQUP
IIVR/iT(4)A:'5ICIVEO ro
,4 91\1ULf -"P CAI.'£'/HAU SHELL •
:oI-fE.E:- , JA¥)6Wa:L~ ..:- ,;EIl-'5.J"- ,
I f)J ;lOT ;'yfiX G)~/fEE75 X' THIS fWAMMJ ,Iff
II, O,k~k Y
~:"E*F/tC-,,-.
SHEEr, ;'"I10WtieC .. -;- SEN:;,JA' ,
.N[)NI[)~Ail' s..,IE~ Rtlf' LEA05
sliEEr,? J,.q}UND&7 !r'EAI? SEN~'
M'OPR 41t1LT!PiE PAII2 S"IEd)€O
LE.,(f}S.
SIIFEr.5' LM]Rl'lND£D II\. PLANT,
.wLJ'V/~i4LLr .'¥'IIELO& ?AIR LE41J5.
sllEE7 4 LNG&vva=o f1! PLANT,
MU-TIPLE PA~ S#IELfEi) /.fAIJS.
NOTE 8~ S/~L CtWL)lr,tAIVE6 HE
~OVlNO IF S'GYAL ~ S8~
£rc!EH5 A/£)SY-S"T7M RANCE.
SlJ/'vAL ,"CWt¥TltWER C MtJt.W7F£J
ON /fAu SHELL AAt-' VI?'~f) 7V
TERMINAL SCREM IN F.4CTCJR>.

NOTE

-1-

LOCAL ....v/I.-CTiOV

BOX (/F VSEtJj

ffE::AUT70Ms-l,lfPLY Ok'LY iU A
GROUP C¥" ,wR:lrr{;+)ASSIOIVE~ W
A SW~ ,fP CA;;~/HALF SH'Eli •
I
loOT MIX O~NDEC AN£>

m

LWOPOUII[)ED

~NSaR5

.

2 aJ NO T MJ/ TlPLE GROUNLJ ,M!Y
SHIEL£! £¥?Allf Ok SEN'::-oR LEA£)
WIRe •
.3 aJ NOT GROl/lfO CA/II.E MJ41/V
WIRES IN PLANT.
4-. L'tWNE~T EAeII CABLE I.J(>AIN

JiWRc TZI t7S .2-1160k •
'- CtlNN£(7 ALL ('ABLE £)I•.'AI/v
n-vRES TZJ (Jl/AkOSIIIELO
(rEA-'MliYAL k2 (TFRMIMUS M(
N WHEN f)S'EC).

U:WOI1i'aI\IER •

HALF SIIELi

"fCt'MWAL ~

~~--'~_l~~

I

SCA'EW' .\()(
/It'M'~

\ \

\ \

\

\

,,

\

's-t ~ - :
I

L

FIGURE ISd.

VOLTAGE SENSOR INPUT CONNECTIONS (REF. DWC. 6828688, SHEET 4)

I

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SEE NOTE B.
SEE ~C4U77a..v M? , •
.REFER ru tJmJ. 61oB2-k..

FIGURE 160.

CURRENT SENSOR INPUT CONNECTIONS (REF. DWG. 6828690, SHEET I)

;WLIST BE ~.om LEA-/).

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FIGURE 16b. CURRENT SENSOR INPUT CO"''''CTIONS (REF. DWG. 6828690, SHE ET 2)

CURRENT SENSOR C/,.fICIi'(JV4tJEll /11 q:,4.J/T
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FIGURE 160. CURRENT SENSOR INPUT CO- -'rTIONS (REF OWG. 6828690. SHEET ~)

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FIGURE 33. ANALOG TRAP LOGIC (REF. OWG. 867C994, SUB 2)

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TELETYPE "CX" TAPE READER SYSTEM

I.

GENERAL DESCRIPTION

The Teletype "CX" Tape Reader is used as a high speed tape input device that provides
outputs corresponding to the intelligence recorded on fully perforated or chadless tape.
The system operates asynchronously at rates up to 60 characters per second. The system contains a Teletype "CX" tape reader, an interface assembly, a channel buffer
module (2RB3) and associated cables.
A block diagram of the reader system is shown in Figure 1. Table 1 indicates the actual
terminations referenced in Figure 1.

TERHlNAl0

,,

- - - - - - - - - - - 'I

BLOCK
I:"wan

Hooa

I
I
I

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TAPE
INPUT

CABLE tt

TELETYPE .. CX..
READER
114

INTERFACE
ASSEMBLY

"
2R83

MODULE

115VAC

Vo

VOLTAGE

OUTPUT _______

I

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Figure 1

(!)

Terminal block type and placement is optional

(2)

Channel Slot is optional

®
CD
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Interrupt assignment is optional
Extender cable is optional
Quick disconnect cable is optional

14-1

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35 Pin Elco

MNEMONIC
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Read Adv.
CLR Reg.
-28V Ext.
U Contact
+28V

35E
X22
X23
X24
X25
X26
X27
X28
X29
Xll
X12
X20
X2
X9

Extension
Cable

I/O Processor
Termination
CURTIS ROWAN
K1
K2
10
K4
K5
K6
K7
K8
KI0
not used
K12
K16
K13

CX Tape Reader
Interface

56E
A
B
C
D
E
F
H
J
T

56E
A
B
C
D
E
F
H
J
T

V

V

Z

Z

W

W

Table 1
ll.

SPECIFICATIONS
A.

Mechanical Specifications
1. An outline drawing of the Tape Reader Interface Package is shown in drawing

794C807.
2. A!l signal cables between the interface package and buffer card should use AWG
f18 stranded wire. A signal distribution panel is available for screwdown type
terminations which will accomodate all standard sizes up to AWG f16 wire.
3. The reader may be located at distances up to 1000 feet from the computer. A
three foot pigtail cable is provided at the interface package so that the extension
cable may be connected.
B.

Environmental Specifications - Tape Reader
1. Temperature 50 0 to 85 0 F
2. Humidity

20 to 80% Relative

3. The Teletype CX Tape Reader should be checked visually every two weeks to insure that the code contacts are clean and the unit is properly lubricated. See
section 5.1 in the Teletype CX Manual Bulletin 267B for detailed lubrication
instructions.
C.

Power Requirements - CX Tape Reader
Voltage
Frequency
Power Consumption
Input Current

-

115V AC t 10% single phase
60 cps t 0.75%
75 watts
Starting - 4.0 amps
Full Load - 1.25 amps

14-2

D.

Reference Drawings
1. CX Tape Reader Package
a) Outline and Assembly 794C807
b) Schematic
794C956
2. Tape Reader Flow. Diagram 867C553
3. Cables
a) Refer To Master Cable List for specific job.
b) Extender Cable - Ml14 for use up to 1000 feet
c) 35E to Rowan M008
d) 35E to 56E
M009
e) 35E to Curtis M019
4. Printed Circuit Card
a) Reader Buffer Card 743A337

m.

CIRCUIT DESCRIPTION
The Teletype CX Tape Reader is an electro-mechanical device with operate magnets and
a code contact mechanism complete with leaf contacts. Perforated tape is the transmission medium for the system.
Drawing 867C553 serves as an interconnection diagram for the tape reader system. In
addition to the forementioned features of the tape reader, a tight-tape mechanism (Start!
stop contact) and a tape-out mechanism (tape-out contact) are used to disable the operating coils and serve to inhibit reader advance when either condition occurs.
The power switch mounted on the tape reader unit has been rendered inoperative. The
power switch mounted on the interface package assembly serves to distribute a-c power
to the reader motor and the 28 VDC operating coils supply contained within the interface
package assembly.
The interface package also contains a three foot pigtail cable which can be connected
to an extension cable to allow the reader to operate up to 1000 feet from the computer.
The transfer of control and data signals between the interface package and the channel
buffer module is described in terms of an impedance from PSC (Power Supply Common
for the computer system). A signal is present means PSC is presented through a very
low impedance, hereafter referred to as a logical "0". When a signal is not present
(present), it is presented through a high impedance, it will be referred to as a logical "1".
A.

Eight Tape Level Data Signals to the buffer module. Logical "0" is present on any
level when a perforation on the tape exists.

B.

"U" Contaci Signai to the buffer module. The "U" contact input is the "Universal"
contact in the reader which closes every time a character is read. It is interpreted
as a "Strobe Tape Level Data" command :u1d a "Stop Reader Advance" command by
the Reader Buffer Module.

C.

Reader Advance Signal to the interface package assembly. This signal triggers the
magnetic drive circuit.

14-3

,'"

I..
1

"I

1.1"

r .....

~

c

...._ _ _ '-.00

It.1&

D

10

~
Il'I

~

I

I

-1.-·

D"TIlI C.lllrALa

1•• 1~

La"Cit'T"

~

F.... 8",.",,...

% PtN E.Lco C- .. LC ...... : (FENM.E)
E LCO P-. ...... 00-80" ·0"'· 000-01:4

f-"
~

I

~

.

I~
0
>l'I

,0

L

•

. , _ UNIT
TY..

,,.PUT '4OLTMR

FIt.4.

c...c.

c.",,","
...... ING c.uAlftln - - I.U. AM"

..I

UNn

~

~

A

"NC""ONOVS
I\'!! y~ •• ,,".
50
- - - .. ,. II....

I'!I.~I

............
.-n .... .,

11O.t.

H. ".

ta

TIT\..

PMOM.~. ~"M-

-..-.-,*".
II

•

••

to,1

••.• ,.

:t0l

1010

~n)'.

.0:

--

MIU"

H.P.

WBftJJlnOWlIUCnIC COIIfOU,1IOII

.. -.

__ 11&.&...,.., ..... .-

.,r.WAT~

eTY/W6t.

•

TAN. A •• _

XtcJftes', \

Three additional signals are required to complete the repertoire:
A.

An Interrupt Input Signal to the I/O Interface is generated by the module in response
to the "U" contact signal.

B.

A Channel Read Signal (Channel half-select) must be programmed into the Central
ProcesSor as a: response to the interrupt input, that is the program must read the
data on a particular channel.

C.

A Clear Data Register (CDR) Signal is processed within the module cirCUitry.

The sequence of events is described in detail in Section IV, "Printed Circuit Card
Description." In general terms, the events are chronologically listed as follows:
A.

Channel Read (Channel Half-Select):
1. Input Data
2. Initiate Reader Advance Signal
3. Initiate Clear Data Register

B,

"U" Contact closes:

1.

Turn Off Reader Advance Signal

2.

Turn Off Clear Data Register Signal

3.

Initiate Interrupt Input (Data Available)

When convenient, the Central Processor responds to Initiate Interrupt Input by initiating
Channel Read, hence giving asynchronous operation. Data is interpreted as a "1" when
the module data register bit output is in a posltive voltage, and a "0" when the bit output
is zero voltage. The eight tape levels are transmitted via the input data lines to the central processor core memory, bits 13 to 6 as shown in Figure 2.
Refer to the 2RB schematic and the Teletype Model CX Interface Schematic 794C956.
Transistor Q 1 on 794C956 will conduct each time S1-1 (on the 2RB card) is turned on.
This causes the operate coils in the reader to be energized, provided the start switch
closed and there is tape in the reader. Each time the operate coils are energized, the
reader advances and will read o~e character, then the "U" contacts close, which cause
an interrupt and blocks SCR, Sl-1, which deenergizes the operate coils. When an acknowledgment is received, Sl-l gets set, the reader will read another character.
Refer to Programmers Reference Manual for information relative to input data from
external devices.

14-5

i i i
I
I

INPUT DATA LINES

t

i

i
I

DIRECTION

1

OF FEED

I

I

I

I

I

0

:

I
I'

6 6 6 6 6~6
6 6
0
FEED HOLE
READ BY 11\1' CONTACT

0
0
0

Figure 2

14-6

HOLE = 11111

L-________

!'_._________ ~. ____~

2

------- - - - - - - - 35 ,LCD

D

CIC.

'TAPE

RU.
001UO/I!

"SS' Y

REAO£.R

D"';CO.

79'K;807
- 1050 Z.Z.41

-

""~I"w DIAG.-IOS02.Z,".

S~H~ .... ATI~ 79"'C'95~1

_ ---"1.--------

-

~~'~I,.mo<'

~A115 V

(M"LE.)

I ~

C;uPPLY

•

-

-

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..,~

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DO M7J ICotU ....
_ _ 'Il1. . . . . IDIII

to
7

I

•

•

I

--

Tln.a

'0: TAPE. ~E.ADf~

tte_

,

'HT~IlCOHNECTION

KJU••

COIil'Vft1l IYeTl... DIY""",

I

DOlfi"A""

SU •. 1

\

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I

........ &

7

•

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II

2

o

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,

IA.

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- _____

.
•

II

,

TELETYPE

1.

BRPE

TAPE

PUNCH SYSTEM

GENERA L DESCRIPTION
The Teletype BRPE Punch is used as a high speed remotely-located paper tape punch.
The tape punch system consists of the Teletype BPRE type punch, an interface package
includin~ automatic motor on/off control, cables and a channel card, IDE3. The system
is capable of punching 8 lpvel tape at speeds up to 63 characters per second. A block
diagram of the tape punch system is shown in Figure 1.

II.

SPECIFICATIONS
A.

Mechanical Specifications
1. An outline drawing of the tape punch and interface package is shown in drawing
794C762. The tape punch may be mounted in a standard console or it may be set
on a desk or table top.
2. All signal cables between interface package and I/Q processor should use AWG
#18 stranded wire. A Signal distribution panel is available for screwdown type
terminations which will accommodate all standard sizes up to AWG #16 stranded
wire.
3. The tape punch may be located at distances up to 1000 feet from the IIQ interface.
A 3 foot pigtail cable is provided at the punch interface to which an extension cable
may be connected. Table 1 indicates the actual terminations shown in Figure 1.

B.

Environmental Specifications
1. Temperature - 50 to 110 0 F

2. Humidity

- 40 to 80 Ir;. Relative

3. The BRPE tape punch should he lubricated at regular intervals as needed. The
lubrication interval should not be more than 160 hours or one month of service,
whichever occurs first. The maintenance time required is approximately 2 hours.
Maintenance and lubrication instructions are found in Teletype Technical
Manual - Bulletin 215B.
C.

Power Requirements
l. Voltage 115 VAC

!

10% single phase

2. Frequency 60 cps !.75 11JJ (50 cycle units also available)
3. Current 9 amp starting - Punch Motor
2 amp running - Punch Motor
2 amp (DC power supply)
D.

Reference Drawings.

15-1

1---

--------,
'U~lCll

INTi.l:F.\C

l'ACfv\G
- TP
CAR [J & 'IOTO:,

DC

ON/OFF CONTROL

56E----t
CHANNEL CAl: [)
(~LOT A[)URCS~

J

K
AC

OPTIONAL)

T[LCTYPE

I NT£1U:UPT
INPUT

BRP[
___

-\~ r-:-1_L.:...r.:.:.B::...:..-..::C;;:U~R.::.T.::.I~=--_r;...;..::.B~'J

CURTIS/I:CJrJAN

TAPE
PUNCH

122

r.B.

111' I'P-OCt::S501:

TAPE uUOCH

SYSrl:l-1
I

___ ..J

L ____ _

1- __ _
, Rowan ferll in al

CUSTONLR
AC ooIRIK;

, Curt is rprl'1in:11

115V

BLOCK DIAGRAM OF TELETYPE TAPE PUNCH SYSTEM

Figure 1

1. Teletype BRPE Punch and Interface Package

a) Outline-Punch-794C762
b) Schematic-105D279
2. System Cables (Refer to Table 1)
a) 35 pin card edge to 56E - 743A498

Ref. only·

b) 35 pin card edge to ROWAN - 774A886

Ref. only·

c) 56E to 56E extension cable - 743A492

Ref. only·

d) 56E to 56E block extension cable

M114 250 feet or less
{ M1l6 up to 1000 feet

e) Curtis block to Curtis/Rowan
{ M121 250 feet or less
Note: M numbers refer to cable numbers, M122 up to 1000 feet
refer to Master Cable List for
particular job.
3. Tape Punch Interconnection Diagram - 867C54l
4. Tape Punch Channel Card
Tape Punch Amplifier Card

- 743A328 (DE)
- 743A376 (TP)

.Table 1 is a composite listing of the information on these 3 Drawings.

15-3

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F"-7I'~EiiE=M==-==o=--'....JL.....--_-.-..

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..

Card Edge

(35 Pin Elco)

MNEMONIC

35E

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

13
12
11
10
9
8
7
6
5

X7
X8
X9
XIO
Xll
X12
X13
XI4
X15
X16

a

-28V Ext
t28V Ext
Trigger
-28V Ext
-28V Ext
-28V Ext
-28V Ext
-28V Ext
-28V Ext

X20
X6

Xl

I/(il Processor
Terminations
ROWAN
CURTIS
K1
K2
K3
K4
K5
K6
K7
K8
Kg
KlO
Kll
K12
KI3
K14
K15
K16
Jl
J2
J3
J4
J5
J6
J7
J8
J9
JI0
Jll

JI2
JI3
J14
J15
J16

56E

Extension Cable

Teletype Tape Punch
Interface
Terminations
5SE

A

A

B
C
D
E
F

B
C
0
E
F

H

H

J
K
T
U
V
W

J
K
T
V
W

X
Y
Z
L
M

Z
L
M

N
P
R
c

u

N
P
R
S

AA

BB
CC
DO
EE
FF
HH

JJ
KK
LL

CURTIS
K1
K2
K3
K4
K5
K6
K7
K8
K9
KIO
Kll
KI2
KI3
KI4
K15
KI6
J1
J2
J3
.14
J5
J6
J7
J8
.J9
JIO
Jll
J12
J13
JI4
JI5
JI6

NN(shield)
Table I
III.

CIRCUIT DESCRIPTION

The Teletype BRPE tape punch requifi'!s 10 bits of information for punching tape and
motor ON/OFF control. The punch motor is turned on and off under computer control
to prevent excessive wear on the punch parts if the punch is inadvertently left idling.
A character on tape is made up of 8 channels corresponding to 8 bits of data and a
feed hole. One bit controls the feed hole magnet which is energized for every character. Also this blt is used to turn on the punch motor and d.c. power. Another bit

15-5

of t he output word is used to turn off the punch motor and d.c. powrr to the punch magllf'tS. Therf'fore, the punch output character includes 10 hits, R hits of data and 2 fl)r
cont rol.
The timinj! of the punch control circuitry is derived from a magnetic pickup mounted
on the punch. This pickup generJ.tes a pulse indicatinj! that the punch magnets may be
energized. From this pulse, the control circuitry enahlcs the maj:!net drivers for a
period of 4.5 milliseconds. At the end of this period of time, the control circuitry inhihits the magnet drivers and generates an interrupt puls(' which is sent to the comPllt f'r asking for another character of output.
nrawin~ 867C541 1s an inconnection diagram of the tape punch system and indicates
thf' maior components required.

The d.c. power supply located in the interface package supplies the required power
for the tape punch system. The nej:!ative side of this 28 volt power supply is tied to,
and common with, the negative side of the 26 volt I/() interface suppl\,.
The following Signals are required betwef>n the punch interface package and the channel
huffer module, IDE3.
1. Ten Data and Control signals from the huffer module to the punch interface package. Zero voltage implies the corresponding punch magnet will he energized.
2. Reset Signal from the punch interface packagE' to the huffer module. This sif:!;nal
occurs each time the computer outputs a character and the magnetic pickup pulse
has been generated. This pulse is used to clear th(' SCR buffer register and initiate an interrupt.
Thf' following signals are required hetw(,f>n the JIG interface and the buffer module.
1. An Interrupt Input Signal to the I/O interface indicating that the character has been
punched and requests more output.
2. A Channel Output Signal addressing the selected channel and
buffer with a data word.

loadin~

the SCR

Therefore, in order to punch tape, it is necessary to addrf'ss the selected channel
which will load data into the SCR buffer register. The Punch motor will turn on
and the corresponding magnets in the tape punch will he enerp:ized through intermediate power amplifiers; the punch will cycle; a reset pulse will reset the SCR
huffer register and generate an interrupt. The computer may then output another
data word at its convenience.
The 10 bit code used with the punch is shown in Figure 2.
B.

Punch Motor and Power Control
As mentioned previously, the punch may be turned ON and OFF under computer
control. Both the punch motor and the d.c. powf'r to the punch magnets are turned
on and off by the computer as shown in Figure 3. A Struthers-Dunn relay (K2) is
used since the switching contacts must he able to switch 9 amperes of starting current to the punch motor and carry 9 amperes of d.c. current to the punch magnets.

15-6

-----'-- ----'

-

--

-

---,

-~-

---'--

-1--·::; -

-

.• !

~~ =~o-

---

.... :.!..;", •• -

~--

.,
(

l

-,

•

D

l

-----~-

I

r

PIIl-'--'T~

l __

,

~~,

-

/

,
I

-

,,...._a..~

i

r"

.....a.c .....

".'''(.C_..-.c''."~,,. I~

:~

f.~ \

l

®
--lL..-._

'

/

'/

\
\

:::.~.;. . ~

a.~-a...... _._
........ _-...r.

' ' ' ....

... "...
l ,.......-,......- ......~,...,...-.rT'
P__

~.· I~ . . . . l _

I

1

'!nor y,p'"

:::..:~~

The following signals are required between the interface package and the buffer module.
1.

Eleven Data Signals {rom the buffer module, zero voltage implies the corresponding
magnet will be energized.

2.

Reset Sibrnal from the interface package to the buffer module. This signal occurs
every time the printer cycles and is used to reset the buffer register.

The following signals are required between the computer I/O Interface and the buffer
module.
1.

An Interrupt Input signal to the I/O Interface indicating the function has been
completed and requesting more output.

2.

A Channel Output signal addressing the selected channel for loading the buffer with
a data word.

Therefore, in order to output to the printer, it is necessary to address the selected
channel which loads data into the buffer register (1SL3). The corresponding magnets in
the printer will be energized; the printer will cycle; a reset signal will reset the buffer
and generate an interrupt and the computer may output another data word at its
convenience.
The eleven bit code required to print alphanumeric information is shown in Table 2.
MOTOR ON/OFF CONTROL
The Selectric motor will turn on when the computer outputs a character to the logging
printer. As long as the computer continues to log or print data, the motor will remain
on. If the computer stops outputting characters, the motor will turn off after a period of
approximately 3 to 4 seconds.
The a.c. voltage to the printer motor is controlled by relay Kl contacts as shown in
Drawing 867C505. Outputting any character as found in Table 2 will cause this relay to
be energized and the printer motor will turn on.
The switch S1 is used to pick relay Kl if it is desired to operate the printer in the offline mode. One pole of the switch is in series with the d.c. supply, so that when the
printer is in the "MAN" mode the computer may not print on the logger. It is therefore
necessary to place the switch S1 in the "AUTO" condition so that the computer has
complete control of turning the printer on and off.
When the printer is not being used by the computer, K1 relay is de-energized and the
5000 f1 f capacitor, C3, will charge up through normally closed contacts (pins 5 and 6) and
the 20 ohm resistor to the positive side of the power supply. When K1 is picked, the
relay contacts transfer the charged capacitor to the relay coil. As long as the computer
continues to output to the printer, K1 will remain energized and the capacitor will
remain charged.
When the computer discontinues outputting to the printer, the capacitor will discharge
through relay Kl. The relay will remain energized until the capacitor voltage drops
helow the holding voltage for the relay. This is approximately 3 seconds. When the
relay drops out, the capaCitor will be recharged through the 20-ohm resistor.

16-6

In order for the computer to have complete control of the printer motor, it is necessary
to bypass the ON/OFF switch mounted on the Selectric. This is done by disconnecting
wires at the switch and crimping them together.
Another modification which is required for the Selectric is to disable the "Shift- Up Lock"
on the keyboard. This must be done since it is possible to lock the shift mechanically at
the keyboard. It may damage the printer "shift-up" solenoid since a completion signal
will not be given when a shift-up command is given and therefore the shift-up magnet
will remain energized.
OPTIONS
Several options are available and are indicated in Table 1. These include Tab, Keyboard
Lock, Color Shift, Index and Back Space. The control of these options must be done
using standard contact closure outputs. There is no standard feedback for these options;
therefore they must receive their control through programming.
These options are brought back to the computer through the standard Selectric cables;
however, the wiring to the CCO unit must be taken care of for each specific system.
Both Color Shift and Keyboard Lock require level-type Signals, while Index, Back Space
and Tab require a pulse for a single actuation of the magnet. Note that when these
functions are performed, an interrupt from the 15L3 card will occur. This can be used
to open the CCO which initiated the function. There will be no interrupt for Color Shift
and Keyboard Lock.
INTERFACE POWEF SUPPLY
The power supply used in the interface package is an unregulated plug-in power supply
which fits into a standard 8 pin octal socket.
The nominal output voltage of this supply is 40 volts.
This power supply is identified as PSI on 867C505.

16-7

,
Table 2 shows the code required for the IBM 735 Printer
PRINT
FUNCTION
A

B
C
0
E
F

13

12

0
1
1
1

1
0
0
0
0
0
0
0
1
0
0
0

1

G
H
I

0
0
1

J

0
0

K
L
M

1
0

1

N
0
P
Q
R

S
T
U
V
W

X

Y
Z
1±

2@
3#
4$

5%
6

~

7 &

8 *

9 (

o)
=+
!

0

/ ?
,
"

1

Bit*
11

10

9

1
0
1

0
0
0

0
0
0
0
0
1
1
0
0
1
0
0
1

1
1
1
1

0
1
1

1
0
1

1

0

1

0
0
0
0
0
1

1
0

0
1
1

1

0
0
1
0
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0

0
1
1
0
0
1
1

0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0

1
0
1
1
1

0
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1

1

1
0
1
1
0
1
0
1

1
0

1

1
1
0
1
0
1
0
0

0

0
0
0
0
0
1
1
1
0

1

1

1

0
1

1
1
O·

1
1

1
0

0
1
1
0
1
0
0
1
0
1
1
0
0
1
1

0
0

0
0
0
0
1
1
0
1
0
0
0

*When Bit 7 is a "I", the machine prints a dash (-).
Table 2

16-8

8
1

0
1
1
0
1

1
0
0
0
0
1

1
0
1

0
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1

Space" 1" in Bit 6
Carr. Ret. "1" in Bit 5
Shift up "1" in Bit 4
Shift down "1" in Bit 3

-.

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16-14

TELETYPE

I.

MODEL 35 INPUT/OUTPUT SYSTEM

GENERAL DESCRIPTION
The Teletype Model 35 equipment is used as a low speed Input/Output to the I/~ processor. The equipment uses the" American Standard Code for Information Interchange"
and operates at a speed of 10 characters per second. When used for Input/Output the
equipment may be a Model 35 ASR (punch, reader, keyboard and printer) or a Model 35
KSR (keyboard and printer). An Output only, the Model 35 RO is also available (printer
only). The Model 35 Input/Output System is shown in Figure 1, and consists of the
Model 35 (ASH, KSH, RO), an Interface package with automatic motor ON/OFF control.
cables, and 3 channel cards. (2TNl, 4T01, 3TSl) The 2 TNI channel card is not
required when the Model 35 RO is used.

II.

SPECIFICATIONS
A.

Mechanical Specifications
1. An outline drawing of the Model 35 ASR is shown in Drawing 1050069. Drawing
105D371 is an outline drawing of the Model 35 KSR and RO. The interface package
and motor ON/OFF control is mounted in the stand of the equipment.

2. All signal cables between interface package and 1/(3 processor should use at least
AWG #22 stranded wire. A signal distribution panel is available for screwdown
type terminations which will accommodate all standard sizes up to AWG #16
stranded wire.
3. The Model 35 equipment may be located up to 1 mile from the I/as processor
using standard extension cables. However since this equipment is compatible
with Dataphone and standard TWX, its location is effectively unlimited. A 3 foot
pigtail cable is provided at the interface to which an extension cable may be
connected. Table 1 indicates the actual terminations shown in Figure 1.
B.

Environmental Specifications
1. Temperature

- 50 0 to 1100 F.

2. Humidity

- 40% to 80% Relative

3. The Model 35 equipment should be lubricated at regular intervals as needed. The
lubrication interval should not be more than 1500 hours or 6 months whichever
occurs first. The maintenance time required is apprOXimately 3 hours. Maintenance and Lubrication instructions are found in Teletype Technical Manual 280B
(ASR) and 281B (KSR and RO).
C.

Power Requirements
1. Voltage

- 115 Volt AC ± 10% single phase

2. Frequency

- 60 ± 0.5 cycles (50 cycle equipment available)

3. Current

- 3 amperes

17-1

INl'ERRUPT INPUT

2TNl

TELF:l'YPE
HODEL 35
ASR or
KSR or
RO
INTERFACE
PACKAGE &

t-l105**
M006*

4TOl
f

~-1J

HareR ON/
CONTROL

I-I
'--

3TSl

I

:'-[]
j

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f

INl'mRUPT INPUT

I
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CurtislRowan I
'-

T .B.
I/O PROCESSeR

1

I

1

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I

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** RO MODEL
ASR or KSR MODEL

'

JB

L___

l1SV

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Figure 1

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MODEL 35 KSR and BO ASSEMBLY
(Ref. @ DWI. 105D371, tub 4)

17-4

ASR
KSR

Card Edge
MNEMONIC

(35 Pin Elco)
35E

Line P(I/Gj)
Line M
+72V
MOTOR ON
+ 48/125V
CR INT
48R
ACK LAMP

TNX2
TSXll
TSXIO
TSX3

125R
+ 48/125V
ATTN.INT
RD. ON
{ Not USed}
RD. ON R on KSR

I/(2j Processor
Terminations
ROWAN 56E Extension
CURTIS
Cable
Kl
K2
K5
K6

TNX21
TNX31

K13
K14

TSXl1
TSXlO
TSX3

K2
K5
K6

TSX4

K16

Te letype Mode 1 35
Interface Terminations
56E
CURTIS

A
B
C

A
B
C

0

0

E
F
H
J
K
V
W
X
Y
Z

E
F
H
J
K
V
W
X
Y
Z

I

RO

Line M
+72V
MOTOR ON
+48/125V
CR INT
LINE P (OUTPUT)

Table 1

17-5

B
C

D
E
F
K

B
C
D
E

F
K

D.

Reference Drawings
1. Model 35 Equipment and Interface

Outline
1050369
1050371
1050371

Model 35 ASR
Model 35 KSR
Model 35 RO

Schematic
1050372
1050373
1050374

2. System Cables (Refer to Drawings 867C573, 867C574)

a) 35 pin card edge to 56E
b) 35 pin card edges to ROWAN
c) 56E to 56E Extension
q) 35 Ein card ec!Ke to CURTIS

Mode 1 35 KSR, 35 ASR, 35 RO
M006
M006 M105
M104
MOO5
MOO5
M114
M114 M114
MOO4
MOO4 M103

3. Channel Cards

2TN1

4TOl
3TS1
III.

- 743A339
- 743A327
- 743A342

CIRCUIT DESCRIPTION
A.

General
To feed blank tape on the Model 35 ASR, it is necessary to depress the "control,
shift, "P" and "Repeat" keys in that order. This will feed blank tape as long as the
"Repeat" key is held depressed.
The mode switch on the Model 35 ASR is used to select different modes of Input/
Output when the equipment is ON-LINE.
Position "K"

- The keyboard and printer are connected to the computer.

Position "KT"

- The keyboard, printer, tape reader, and tape punch are connected
to the computer. When the tape reader is transmitting, the
message is copied by the printer and a duplicate tape is punched.
The keyboard should not be operated when the tape reader is
reading. When the keyboard is transmitting, the message is
copied by the printer and a tape is punched.

Position "T"

- The tape reader and printer are connected to the computer. The
printer copies what is being transmitted by the tape reader or
received from the computer. The keyboard and tape punch are
left in an OFF- LINE condition and tape may be prepared locally
from the keyboard while transmitting to and from the computer.

Position "TTS" - The tape reader reads binary tapes with no printing occurring.
The keyboard and tape punch may be used to prepare tape without
interference to the tape reader.

17-6

Position "TTR" - The. tape punch is connected to the computer and may be used to
punch binary tapes. The tape reader, printer and keyboard are
disconnected. (This mode has no apparent use at present.)
The Model 35 KSR has no MODE switch and the keyboard and printer are always
connected to the computer when the KSR set is ON-LINE.
When punching binary tapes using the programmer's console programs (BP) the
operator should set the mode select switch to the KT position so that the limits of
punching are not punched in the binary output tape. When the "trigger" character,
return, is given, a 10 second program delay will occur to allow the operator to
switch the mode select switch from KT mode to TTR mode. Binary punching will
then occur. Any additional binary output requires switching to the KT mode, typing
in the limits, and then switching back to the TTR mode.
Teletype Model 35 send-receive equipment uses an 8-level code (standard ASCII
code) as shown in Table 2. An additional two bits of data are required for turning
the motor on and off under computer control so that the total output character is
made up of 10 bits while input data is 8 bits. Current on the line is defined to be
60 milliamperes for marking and 0 milliamperes for spacing. In addition to the
intelligence portion of the code, control is required; since transmission is serial,
a "start" and "stop" pulse must be generated. The start pulse precedes the first
intelligence pulse of each character and is always a spacing pulse (open line), while
the stop pulse follows the last intelligence pulse and is always a marking pulse
(current in line).
The "start" pulse has the same duration as each of the character pulses, while the
"stop" pulse has a duration of twice that of the others. If each character pulse is
given a unit time duration, the total time required to transmit any character is 11.0
units. A transmission rate of 10 characters per second requires a rate of ItO units
per second. Therefore, one unit of time is equal to 9.09 milliseconds. This is the
basic unit of time for the Teletype serial transmission equipment.
The above general description indicates how a two wire teletype transmission
system operates. In order to be compatible, so as to transmit serial data, it is
necessary to open and close the line at the required rate. In order to receive serial
data it is necessary to monitor the line, sychronized with the start pulse, and detect
when there is current and when there is no current. This is done by using a
mercury relay contact for output and a mercury relay coil for input, both of these
being in series with the line as shown in Figure 2.
B.

Information Transfer
Figure 2 indicates in block diagram form, the major components which make up the
control of data transfer between the I/O interface and the Model 35 equipment.
These components make up the 3 channel cards mounted in the I/O interface; 4TOl,
3TS1, and 2TN1 cards.
In order to provide the necessary timing required by the Model 35 equipment, a
five-stage counter is used. This counter is stepped along by alternate pulses, PI
and P2. The timing of this counter is shown in Figure 3. PI and P2 pulses are
derived from a unijunction oscillator circuit and are timed to occur alternatively
every 9.09 milliseconds, the basic unit of time of the 35 equipment. The five-sta~e
counter can give 10 different states. These are shown in Figure 3. Note that state
E' A is equivalent to the "start" for the 35 equipment. The eight succeeding states

17-7

Level
Character 8 7 6 5 4 Feedhole 3 2 1 Octal
@

A
B
C
D
E
F

I

I

G
H
I
J
K

L
M
N
::)
I

1 1
1
1
1 1
1
1 1
1 1
1
1
1 1
1 1
1
1 1
1
1
111

1

Q
It

1 !1
1 11

~ 1
:1
,1

11
T
1 1
I
U
1
V
1
W
1 1
X
1 1
1
Y
Z
1
1 1
L
1
1 1
--.J
1 1
,I,
1
i SPACE I 1
1
I
!
1
I
"
1
#
1
1
1
$
C"
1 /1
c
1 11
&
,
1
I
(
1
i
)
1
1
~

I

1
1
1
1
1
1
1
1

il

r

1
1
1
1
1
1
1
1
1
1
1
1

I

:
I

I

1
1
1
1
1
1
1
1

I

I

•

1

P

,-

3UO
101
1
102
1 1 303
104
1
1
1 305
1 1
306
1 1 1 107
110
1 311
1
312
1 1 113
1
314
1
1 l15
1 1
116
1 1 1 317
120
I
1 321
/
322
II !1
il 1 123
1
324
1
1 125
126
1 1
1 1 1 327
330
1 131
1
132
1 1 333
1
134
1
1 335
1 1
336
1 1 1 137
240
1 041
042
1
1 1 243
044
1
1 245
1
246
1 1
1 1 1 047
050
1 251

Level
Character 8 7 6 5 4 Feedhole 3 2 1 Octal

1
1

1

+

,

1

/

1

~
1
2
3
4
5
6
7
8
9

1

,

1

=

1
1

1
1

1
1

?

EOT
WRU
RU
BELL
TAB
LINE}
FEED
VT
FORM
RETURN
X ON
TAPE
X OFF
TAPE
ACK
ALT }
MODE
RUB t
OUT (

1

1
1
1 1
1

252
053
254
055
056
257
060
261
262
063
264
065
066
267
270
071
072
273
074
275
276
077
204
005
006
207
011

1

1

012

1 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1 1
1
1
1 1
1 1 1
1

1
1
1 1
1
1
1
1 1
1 1 1
1
1
1
1
1
1
1
1

1

1

1
1
1 1
1
1
1
1
1
1
1
1

1
1
1 1

1
1
1
1
1
1 1 1 1 1
1 1 1 1

1
1
1

1

213
014
215
021
022
223
024
374
175

1 1 1 1 1

1 1 1

377

1
1

Ascn TELETYPE CODE
Table 2

17-8

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1

1
1

1
1
1
1 1

INTERRUPT B
r - - - ' p 1& .----'1.--_ (OUTPUT)

P~E

CLOCK

P2)

10 STATE

F_~_=_=~=;====~~------~
"START"

SEQUENCER

Z
SCR
STORAGE
REGI STER

I

I NPlrr
TRANSFORMERS

: (SET)
INPUT
AMPL.

INPUT
DATA
REGI STER
IN
COMPUTER

CHAN
PUlSE A

~

-;J

INHIBIT

I

'"

SET OUT. MODE

CHAN

1/0
CHANNEL
SELECTION

PUlSE B
INPUT
MODE
INHI BIT
Kl
TWO WIR
COHHUN I (J\T I ON
TO t10DEL
35 EQUII'MEN

LI NE RELAY

K2
LINE
CONTACT

OUTPUT
TPA'ISFORMERS

-+ 60KA

Figure 2

X
OUTPUT
DATA
REG I STER
OF
COMPUTER

represent the 8 bits of data for the Model 35 code. "Stop" is represented by state
D·E of the sequencer and at this time an 18.18 millisecond delay is generated since
"stop" is twice as long as the other states. This sequencer is used to serialize
data during output and also for sequentially storing the serial data during input.
Figure 4 shows generally how data is transferred between the Model 35 equipment
and the control logic. An SCR is used to buffer each of the eight bits which make up
the 35 code. Eac.h SCR may be set from the computer using the I/O processor data
outputs and addressing the channel or it may be set as a result of inputting data
from the Model 35 reader or keyboard.
As shown in Figure 4 the "line" is closed to the 35 equipment and may be opened by
opening the Kl contacts (output) or by opening it within the 35 equipment (input),
either by striking a key on the keyboard or by reading a character from tape.
1. Output Mode

To output a character it is necessary to start the sequencer. This will happen
when a character is loaded into the eight bit SCR buffer from the c.omputer. The
sequencer is resd to step E'A and a start pulse is given which occurs as a result
of Kl relay being energized. Note that a "start" pulse will occur with every
eh:nacter that 1S 10.i11ed mto the register during output.
ThL' not step in thE sequence A'B will select Bit 5 of the SCR register. Point
"5" (select) will go positive it the SCR has not been set (0) and will be clamped
to ground if the SCR has been set (1). This output "S" is then OR'ed into the Kl
driver so that if the SCR was set (1) the relay will not be energized and the "line"
will remain closed. However, if the SCR was not set then the K1 driver will con-

duct and the relay contacts will open, opening the line. The next SCR, Bit 6, will
be selected by the B'C state of the sequencer and the line will be opened or closed
depending on the state of the SCR. Each of the SCR's up to Bit 12 will be
examined by the sequencer and the line will be opened or closed. Once the 8 bit
code has been transmitted a "stop" pulse is given. This requires that the "line"
be left closed for at least two units of time, 18.18 milliseconds. After this period
of time a new character may be processed. The stop code occurs when state D· E
occurs and is generated by a unijunction time delay circuit covered later in the
description of operation.
After each output character is processed the register is cleared and an interrupt
is given to the computer asking for another character.
2. Input Mode
When a key is struck on the keyboard or a character is read from tape, the
sequencer is reset and starts to step along in synchronism with the ASR set. A
signal called "input load" is generated when the Input Mode is selected. This
signal, shO\l'n in Figure 4, is used to strobe the condition of the "line" for each of
the data bits. The input load Signal occurs approximately 6.3 milliseconds after
the beginning of each step of the sequencer.
The "input load" Signal pulses the "gate" of the selected SCR. When this gate is
allowed to go positive the SCR will be turned on. As shown in Figure 4, if the
SCR is turned on when the input channel is selected the data input to the computer
will be a logic "0" since the SCR shorts windings 1 and 2 of the pulse transformer.
A logic "1" will be sent to the computer if the SCR is in the blocked state.

17-10

P1 __~n
P2

RESET

Ll

-.1g~~9

n~

n

____~n~______~n~______~n~______

n

n

n

J1

~

I NPUT LOAD -..----'
A---'

L--_-'

A---'
B

~~--------------~

B------I

c-------.. .
c _______

.....J

0-----------,
D=~~

_ _ _ _ _ _- - - i

E

-E ____________________

~

SEQUENCE ~TEI'

BIT (OUTPUT NODE)

BIT (INPUT MODE)

"STAnT"

"START"

STEP-9--- E'A (RESET)

o-

A·B
1 - B'C
C.D
2
3
4
5
6
7
8

- D.E
A.S
- B.C

(feedho1e)

~;'A

-

- C'D

-

D~E

...

5
6
7
8
9
10
11
12

"STOP"

ASH INPUT/OUTPUT SCAN SEQUENCE
Figure 3

17-11

6

7
8
9

10
11
12
13
"STOP"

"1"

"0"

CUlliU:NT ON TIl L LlNL

NO CUI:I" U,l ,)N TilL LINe

. - - - - + - 0 LINE
INPUT
STROBE

)

-.....--i

60 rna

2:'.5 JI... ~ " / ". "

K2

o-~_~jro ~~DEL

POWER
SUPPLY

EQUIPMENT

(7Z V)

)

PULSE

E • A (START)

... VOLTAGE

A--411__-----.
SEQUENCE DECODE
B

DATA

(+)

---~----..

II $I I

HALF

(X REG.) SElECT

aIr,

"ORII
GATE

+V

INPUT
LOAD

'---------=--.;--...,.

CHAN. SELECT DATA
INPUT
HOLDING
Z REG.
RESI STaR
OUTPUT
HODE

SCR

1.

3.

2

4

5

3

5

2 4

6

INFORMATION TRANSFER
Figure 4

Thereforc, to transmit a lo~ic "1" to the computer from the data reJ,!ister it is
necessary to suppress the input load signal so that the SCR will remain bloc.kC'd.
This is done by using the contacts of a mercury relay as shown in Fi~urc 4.
The coil of the relay is in series with the line and is energized when the line is
closed (1). Thc normally open contacts of this relay suppress the input load
signal when the line is closed, a logic "1" condition. When the contacts open the
input load Signal is permitted to go positive. The contacts will open if the relay
is de-eneq~ized, Le., the line is open.
It is, th£·reforc. possible to monitor the condition of the "line" and sequentially

set the ECR data register. Since both the sequencer and the ASR set are in
synchronism. it is possible to store the serial code in the buffer rc~ister. At
step A'B of the sequence point "S" is positive and if the "line" is open the input
load pulse will not lJe ir.hibited and the SCR gate will he pulsed, setting the SCR.
A logic "0" will he transmitted. If, however, when step A·a occurs the "line" is
closed the relay contacts will be closed and the "input load" si~nal will he
suppressf'd and tllP SCR will not be set. A logic "}" will he transmiU£'ri to the
computer, As each step of the sequence occurs the line contact wi 11 I>£' monilnrerl
and the corre:"ponding SCR will be turned on or left blocked.
When step D·E occurs, the "stop" code is generated and an input interrupt is
given, and the computer may then read the buffer register by addressing the
particular channel.
3. Signal Requirements
The following si~nals are rcquired between the Model 35 equipment interface
package and the channel modules 2TNl, 4TOl,and 3TSl.
a) Two Signal wi r£' communication link with the capahility of opening- ami c losin~
the line for output; and the capability of monitoring the line openinJ,.'; and closinp:
tor input.
h) A reader control Signal for start/stop control of Reader unit in Model 35 ASH.
c) Motor ON/OFF control Signal for turning Model 35 equipment on and off under

computer control.
The following Signals are required between the I/O processor and the channel
modules 2TNl, 4TOl, 3TSl.
a) Two Interrupt Input

Si~nals

1) INPUT (2TNl) - indicating character is ready for transfer to L 0 interfacc.

2) OUTPUT (3TSl) - indicating character has heen processed hy Model 35.
Il) Two channel half se