Atmel AVR XMEGA E Manual
Atmel-XMEGA-E_Manual
User Manual:
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Page Count: 447 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- 1. About the Manual
- 2. Overview
- 3. Atmel AVR CPU
- 3.1 Features
- 3.2 Overview
- 3.3 Architectural Overview
- 3.4 ALU - Arithmetic Logic Unit
- 3.5 Program Flow
- 3.6 Instruction Execution Timing
- 3.7 Status Register
- 3.8 Stack and Stack Pointer
- 3.9 Register File
- 3.10 RAMP and Extended Indirect Registers
- 3.11 Accessing 16-bit Registers
- 3.12 Configuration Change Protection
- 3.13 Fuse Lock
- 3.14 Register Descriptions
- 3.14.1 CCP – Configuration Change Protection Register
- 3.14.2 RAMPD – Extended Direct Addressing Register
- 3.14.3 RAMPX – Extended X-Pointer Register
- 3.14.4 RAMPY – Extended Y-Pointer Register
- 3.14.5 RAMPZ – Extended Z-Pointer Register
- 3.14.6 EIND – Extended Indirect Register
- 3.14.7 SPL – Stack Pointer Register Low
- 3.14.8 SPH – Stack Pointer Register High
- 3.14.9 SREG – Status Register
- 3.15 Register Summary
- 4. Memories
- 4.1 Features
- 4.2 Overview
- 4.3 Flash Program Memory
- 4.4 Fuses and Lockbits
- 4.5 Data Memory
- 4.6 Internal SRAM
- 4.7 EEPROM
- 4.8 I/O Memory
- 4.9 Data Memory and Bus Arbitration
- 4.10 Memory Timing
- 4.11 Device ID and Revision
- 4.12 I/O Memory Protection
- 4.13 Register Description – NVM Controller
- 4.13.1 ADDR0 – Address Register 0
- 4.13.2 ADDR1 – Address Register 1
- 4.13.3 ADDR2 – Address Register 2
- 4.13.4 DATA0 – Data Register 0
- 4.13.5 DATA1 – Data Register 1
- 4.13.6 DATA2 – Data Register 2
- 4.13.7 CMD – Command Register
- 4.13.8 CTRLA – Control Register A
- 4.13.9 CTRLB – Control Register B
- 4.13.10 INTCTRL – Interrupt Control Register
- 4.13.11 STATUS – Status Register
- 4.13.12 LOCKBITS – Lock Bit Register
- 4.14 Register Descriptions – Fuses and Lock Bits
- 4.15 Register Description – Production Signature Row
- 4.15.1 RCOSC8M – Internal 8MHz Oscillator Calibration Register
- 4.15.2 RCOSC32K – Internal 32.768kHz Oscillator Calibration Register
- 4.15.3 RCOSC32M – Internal 32MHz Oscillator Calibration Register
- 4.15.4 RCOSC32MA – Internal 32MHz RC Oscillator Calibration Register
- 4.15.5 LOTNUM0 – Lot Number Register 0
- 4.15.6 LOTNUM1 – Lot Number Register 1
- 4.15.7 LOTNUM2 – Lot Number Register 2
- 4.15.8 LOTNUM3- Lot Number Register 3
- 4.15.9 LOTNUM4 – Lot Number Register 4
- 4.15.10 LOTNUM5 – Lot Number Register 5
- 4.15.11 WAFNUM – Wafer Number Register
- 4.15.12 COORDX0 – Wafer Coordinate X Register 0
- 4.15.13 COORDX1 – Wafer Coordinate X Register 1
- 4.15.14 COORDY0 – Wafer Coordinate Y Register 0
- 4.15.15 COORDY1 – Wafer Coordinate Y Register 1
- 4.15.16 ROOMTEMP – Room Temperature Register
- 4.15.17 HOTTEMP – Hot Temperature Register
- 4.15.18 ADCACAL0 – ADCA Calibration Register 0
- 4.15.19 ADCACAL1 – ADCA Calibration Register 1
- 4.15.20 ACACURRCAL – ACA Current Calibration Register
- 4.15.21 TEMPSENSE2 – Temperature Sensor Calibration Register 2
- 4.15.22 TEMPSENSE3 – Temperature Sensor Calibration Register 3
- 4.15.23 TEMPSENSE0 – Temperature Sensor Calibration Register 0
- 4.15.24 TEMPSENSE1 – Temperature Sensor Calibration Register 1
- 4.15.25 DACA0OFFCAL – DACA Offset Calibration Register
- 4.15.26 DACA0GAINCAL – DACA Gain Calibration Register
- 4.15.27 DACA1OFFCAL – DACA Offset Calibration Register
- 4.15.28 DACA1GAINCAL – DACA Gain Calibration Register
- 4.16 Register Description – General Purpose I/O Memory
- 4.17 Register Descriptions – MCU Control
- 4.17.1 DEVID0 – Device ID Register 0
- 4.17.2 DEVID1 – Device ID Register 1
- 4.17.3 DEVID2 – Device ID Register 2
- 4.17.4 REVID – Revision ID
- 4.17.5 ANAINIT – Analog Initialization Register
- 4.17.6 EVSYSLOCK – Event System Lock Register
- 4.17.7 WEXLOCK – Waveform Extension Lock Register
- 4.17.8 FAULTLOCK – Fault Extension Lock Register
- 4.18 Register Summary – NVM Controller
- 4.19 Register Summary – Fuses and Lockbits
- 4.20 Register Summary – Production Signature Row
- 4.21 Register Summary – General Purpose I/O Registers
- 4.22 Register Summary – MCU Control
- 4.23 Interrupt Vector Summary
- 5. EDMA – Enhanced Direct Memory Access
- 5.1 Features
- 5.2 Overview
- 5.3 EDMA Transaction
- 5.4 Transfer Triggers
- 5.5 Addressing and Transfer Count
- 5.6 Priority Between Channels
- 5.7 Double Buffering
- 5.8 Data Processing
- 5.9 Error Detection
- 5.10 Software Reset
- 5.11 Protection
- 5.12 Interrupts
- 5.13 Register Description – EDMA Controller
- 5.14 Register Description – Peripheral Channel
- 5.15 Register Description – Standard Channel
- 5.15.1 CTRLA – Control Register A
- 5.15.2 CTRLB – Control Register B
- 5.15.3 SRCADDCTRL – Source Address Control Register
- 5.15.4 DESTADDCTRL – Destination Address Control Register
- 5.15.5 TRIGSRC – Trigger Source Register
- 5.15.6 TRFCNTL – Block Transfer Count Register Low
- 5.15.7 TRFCNTH – Block Transfer Count Register High
- 5.15.8 SRCADDRL – Source Address Register Low
- 5.15.9 SRCADDRH – Source Address Register High
- 5.15.10 DESTADDRL – Destination Address Register Low
- 5.15.11 DESTADDRH – Destination Address Register High
- 5.16 Register Summary – EDMA Controller in PER0123 Configuration
- 5.17 Register Summary – EDMA Controller in STD0 Configuration
- 5.18 Register Summary – EDMA Controller in STD2 Configuration
- 5.19 Register Summary – EDMA Controller in STD02 Configuration
- 5.20 Register Summary – EDMA Peripheral Channel
- 5.21 Register Summary – EDMA Standard Channel
- 5.22 Interrupt Vector Summary
- 6. Event System
- 7. System Clock and Clock Options
- 7.1 Features
- 7.2 Overview
- 7.3 Clock Distribution
- 7.4 Clock Sources
- 7.5 System Clock Selection and Prescalers
- 7.6 PLL with 1x-31x Multiplication Factor
- 7.7 DFLL 32MHz
- 7.8 PLL and External Clock Source Failure Monitor
- 7.9 Register Description – Clock
- 7.10 Register Description – Oscillator
- 7.10.1 CTRL – Oscillator Control Register
- 7.10.2 STATUS – Oscillator Status Register
- 7.10.3 XOSCCTRL – XOSC Control Register
- 7.10.4 XOSCFAIL – XOSC Failure Detection Register
- 7.10.5 RC32KCAL – 32kHz Oscillator Calibration Register
- 7.10.6 PLLCTRL – PLL Control Register
- 7.10.7 DFLLCTRL – DFLL Control Register
- 7.10.8 RC8MCAL – 8MHz Internal Oscillator Calibration Register
- 7.11 Register Description – DFLL32M
- 7.12 Register Summary - Clock
- 7.13 Register Summary - Oscillator
- 7.14 Register Summary – DFLL32M
- 7.15 Interrupt Vector Summary
- 8. Power Management and Sleep Modes
- 9. Reset System
- 10. WDT – Watchdog Timer
- 11. PMIC – Interrupts and Programmable Multilevel Interrupt Controller
- 12. I/O Ports
- 12.1 Features
- 12.2 Overview
- 12.3 I/O Pin use and Configuration
- 12.4 Reading the Pin Value
- 12.5 Input Sense Configuration
- 12.6 Port Interrupt
- 12.7 Port Event
- 12.8 Alternate Port Functions
- 12.9 Slew Rate Control
- 12.10 Clock and Event Output
- 12.11 Multi-pin Configuration
- 12.12 Virtual Ports
- 12.13 Register Descriptions – Ports
- 12.13.1 DIR – Data Direction Register
- 12.13.2 DIRSET – Data Direction Set Register
- 12.13.3 DIRCLR – Data Direction Clear Register
- 12.13.4 DIRTGL – Data Direction Toggle Register
- 12.13.5 OUT – Data Output Value Register
- 12.13.6 OUTSET – Data Output Value Set Register
- 12.13.7 OUTCLR – Data Output Value Clear Register
- 12.13.8 OUTTGL – Data Output Value Toggle Register
- 12.13.9 IN – Data Input Value Register
- 12.13.10 INTCTRL – Interrupt Control Register
- 12.13.11 INTMASK – Interrupt Mask Register
- 12.13.12 INTFLAGS – Interrupt Flag Register
- 12.13.13 REMAP – Pin Remap Register
- 12.13.14 PINnCTRL – Pin n Control Register
- 12.14 Register Descriptions – Port Configuration
- 12.15 Register Descriptions – Virtual Port
- 12.16 Register Summary – Ports
- 12.17 Register Summary – Port Configuration
- 12.18 Register Summary – Virtual Ports
- 12.19 Interrupt Vector Summary – Ports
- 13. TC4/5 – 16-bit Timer/Counter Type 4 and 5
- 13.1 Features
- 13.2 Overview
- 13.3 Block Diagram
- 13.4 Clock and Event Sources
- 13.5 Double Buffering
- 13.6 Counter Operation
- 13.7 Capture Channel
- 13.8 Compare Channel
- 13.9 Interrupts and Events
- 13.10 EDMA Support
- 13.11 Timer/Counter Commands
- 13.12 Register Description – Standard Configuration
- 13.12.1 CTRLA – Control Register A
- 13.12.2 CTRLB – Control Register B
- 13.12.3 CTRLC – Control Register C
- 13.12.4 CTRLD – Control Register D
- 13.12.5 CTRLE – Control Register E
- 13.12.6 INTCTRLA – Interrupt Control Register A
- 13.12.7 INTCTRLB – Interrupt Control Register B
- 13.12.8 CTRLGCLR/CTRLGSET – Control Register G Clear/Set
- 13.12.9 CTRLHCLR/CTRLHSET – Control Register H Clear/Set
- 13.12.10 INTFLAGS – Interrupt Flags Register
- 13.12.11 TEMP – Temporary Register for 16-bit Access
- 13.12.12 CNTL – Counter Register Low
- 13.12.13 CNTH – Counter Register High
- 13.12.14 PERL – Period Register Low
- 13.12.15 PERH – Period Register High
- 13.12.16 CCxL – Compare or Capture x Register Low
- 13.12.17 CCxH – Compare or Capture x Register High
- 13.12.18 PERBUFL – Period Buffer Register Low
- 13.12.19 PERBUFH – Period Buffer High
- 13.12.20 CCxBUFL – Compare or Capture x Buffer Register Low
- 13.12.21 CCxBUFH – Compare or Capture x Buffer Register H
- 13.13 Register Description – Byte Mode Configuration
- 13.13.1 CTRLA – Control Register A
- 13.13.2 CTRLB – Control Register B
- 13.13.3 CTRLC – Control Register C
- 13.13.4 CTRLD – Control Register D
- 13.13.5 CTRLE – Control Register E
- 13.13.6 CTRLF – Control Register F
- 13.13.7 INTCTRLA – Interrupt Control Register A
- 13.13.8 INTCTRLB – Interrupt Control Register B
- 13.13.9 CTRLGCLR/CTRLGSET – Control Register G Clear/Set
- 13.13.10 CTRLHCLR/CTRLHSET – Control Register H Clear/Set
- 13.13.11 INTFLAGS – Interrupt Flags Register
- 13.13.12 LCNT – Low Counter Register
- 13.13.13 LPER – Low Period Register
- 13.13.14 LCCx – Low Channel Compare or Capture x Register
- 13.13.15 HCCx – High-Channel Compare or Capture x Register
- 13.13.16 LPERBUF – Low Period Buffer Register
- 13.13.17 LCCxBUF – Low Channel Compare or Capture x Buffer Register
- 13.13.18 HCCxBUF – High Channel Compare or Capture x Buffer Register
- 13.14 Register Summary – Standard Configuration
- 13.15 Interrupt Vector Summary – Standard Configuration
- 13.16 Register Summary – Byte Configuration
- 13.17 Interrupt Vector Summary – Byte Configuration
- 14. WeX – Waveform Extension
- 14.1 Features
- 14.2 Overview
- 14.3 Port Override
- 14.4 Output Matrix
- 14.5 Dead-time Generator
- 14.6 Pattern Generator
- 14.7 Change Protection
- 14.8 Register Description
- 14.8.1 CTRL – Control Register
- 14.8.2 DTBOTH – Dead-Time Concurrent Write to Both Sides Register
- 14.8.3 DTLS – Dead-Time Low Side Register
- 14.8.4 DTHS – Dead-Time High Side Register
- 14.8.5 STATUSCLR/STATUSSET – Status Clear/Set Register
- 14.8.6 SWAP – Swap Register
- 14.8.7 PGO – Pattern Generation Override Register
- 14.8.8 PGV – Pattern Generation Value Register
- 14.8.9 SWAPBUF – Swap Buffer Register
- 14.8.10 PGOBUF – Pattern Generation Overwrite Buffer Register
- 14.8.11 PGVBUF – Pattern Generation Value Buffer Register
- 14.8.12 OUTOVDIS – Output Override Disable Register
- 14.9 Register Summary
- 15. Hi-Res – High-Resolution Extension
- 16. Fault Extension
- 17. RTC – Real Time Counter
- 17.1 Features
- 17.2 Overview
- 17.3 Clock Domains
- 17.4 Interrupts and Events
- 17.5 Correction
- 17.6 Register Description
- 17.6.1 CTRL – Control Register
- 17.6.2 STATUS - Status Register
- 17.6.3 INTCTRL - Interrupt Control Register
- 17.6.4 INTFLAGS – Interrupt Flag Register
- 17.6.5 TEMP - Temporary Register
- 17.6.6 CALIB – Calibration Register
- 17.6.7 CNTL – Count Register Low
- 17.6.8 CNTH – Count Register High
- 17.6.9 PERL – Period Register Low
- 17.6.10 PERH - Period Register High
- 17.6.11 COMPL – Compare Register Low
- 17.6.12 COMPH – Compare Register High
- 17.7 Register Summary
- 17.8 Interrupt Vector Summary
- 18. TWI – Two-Wire Interface
- 18.1 Features
- 18.2 Overview
- 18.3 General TWI Bus Concepts
- 18.4 TWI Bus State Logic
- 18.5 TWI Master Operation
- 18.6 TWI Slave Operation
- 18.7 Enabling External Driver Interface
- 18.8 Bridge Mode
- 18.9 SMBUS L1 Compliance
- 18.10 Register Description – TWI
- 18.11 Register Description – TWI master
- 18.12 Register Description – TWI Slave
- 18.13 Register Description – TWI Timeout
- 18.14 Register Summary - TWI
- 18.15 Register Summary - TWI Master
- 18.16 Register Summary - TWI Slave
- 18.17 Register Summary – TWI Timeout
- 18.18 Interrupt Vector Summary
- 19. TWI SMBUS L1 Compliance
- 19.1 Features
- 19.2 TWI SMBUS L1 Compliance
- 19.3 Overview
- 19.4 Operation
- 19.5 Register Description – TWI Master
- 19.6 Register Description – TWI Slave
- 19.7 Register Description – TWI Timeout
- 19.8 Register Summary – TWI
- 19.9 Register Summary – TWI Master
- 19.10 Register Summary – TWI Slave
- 19.11 Register Summary – TWI Timeout
- 20. SPI – Serial Peripheral Interface
- 21. USART
- 21.1 Features
- 21.2 Overview
- 21.3 Clock Generation
- 21.4 Frame Formats
- 21.5 USART Full-duplex Initialization
- 21.6 USART One-wire Initialization
- 21.7 Data Transmission - The USART Transmitter
- 21.8 Data Reception - The USART Receiver
- 21.9 Asynchronous Data Reception
- 21.10 Fractional Baud Rate Generation
- 21.11 USART in Master SPI mode
- 21.12 USART SPI vs. SPI
- 21.13 Multiprocessor Communication Mode
- 21.14 One-wire Mode
- 21.15 Data Encoding/Decoding
- 21.16 IRCOM Mode of Operation
- 21.17 EDMA Support
- 21.18 Register Description
- 21.19 Register Summary
- 21.20 Interrupt Vector Summary – USART
- 22. IRCOM – IR Communication Module
- 23. XCL – XMEGA Custom Logic
- 23.1 Features
- 23.2 Overview
- 23.3 Timer/counter Configuration
- 23.4 Timer/counter Operation
- 23.5 Glue Logic
- 23.6 Interrupts and Events
- 23.7 Register Description
- 23.7.1 CTRLA – Control Register A
- 23.7.2 CTRLB – Control Register B
- 23.7.3 CTRLC – Control Register C
- 23.7.4 CTRLD – Control Register D
- 23.7.5 CTRLE – Control Register E
- 23.7.6 CTRLF – Control Register F
- 23.7.7 CTRLG – Control register G
- 23.7.8 INTCTRL – Interrupt Control Register
- 23.7.9 INTFLAGS – Interrupt Flag Register
- 23.7.10 PLC – Peripheral Length Control Register
- 23.7.11 CNTL – Count Register Low
- 23.7.12 CNTH – Count Register High
- 23.7.13 CMPL – Compare Register Low
- 23.7.14 CMPH – Compare Register High
- 23.7.15 PERCAPTL – Period and Capture Register Low
- 23.7.16 PERCAPTH – Period and Capture Register High
- 23.8 Register Summary
- 23.8.1 Register Summary – One 16-bit T/C (TC16)
- 23.8.2 Register Summary – One 8-bit T/C (BTC0)
- 23.8.3 Register Summary – Two 8-bit T/C (BTC01)
- 23.8.4 Register Summary – One 8-bit T/C and one 8-bit Tx PEC (BTC0PEC1)
- 23.8.5 Register Summary – One 8-bit T/C and One 8-bit Rx PEC (PEC0BTC1)
- 23.8.6 Register Summary – Two 8-bit Tx/Rx PEC (PEC01)
- 23.8.7 Register Summary – One 8-bit T/C and Two 4-bit Tx/Rx PEC (BTC0PEC2)
- 23.8.8 T/C in PWM Modes with Programmable Period (PWM or SSPWM)
- 23.9 Interrupt Vector Summary
- 23.10 T/C and PEC Register Summary vs. Configuration and Mode
- 24. CRC – Cyclic Redundancy Check Generator
- 25. ADC – Analog to Digital Converter
- 25.1 Features
- 25.2 Overview
- 25.3 Input Sources
- 25.4 Sampling Time Control
- 25.5 Voltage Reference Selection
- 25.6 Conversion Result
- 25.7 Calibration and Correction
- 25.8 Starting a Conversion
- 25.9 ADC Clock and Conversion Timing
- 25.10 ADC Input Model
- 25.11 EDMA Transfer
- 25.12 Interrupts and Events
- 25.13 Synchronous Sampling
- 25.14 Register Description – ADC
- 25.14.1 CTRLA – Control Register A
- 25.14.2 CTRLB – Control Register B
- 25.14.3 REFCTRL – Reference Control Register
- 25.14.4 EVCTRL – Event Control Register
- 25.14.5 PRESCALER – Clock Prescaler Register
- 25.14.6 INTFLAGS – Interrupt Flags Register
- 25.14.7 TEMP – Temporary Register
- 25.14.8 SAMPCTRL – Sampling Time Control Register
- 25.14.9 CALL – Calibration Register Low
- 25.14.10 CH0RESL – Channel 0 Result Register Low
- 25.14.11 CH0RESH – Channel 0 Result Register High
- 25.14.12 CMPL – Compare Register Low
- 25.14.13 CMPH – Compare Register High
- 25.15 Register Description - ADC Channel
- 25.15.1 CTRL – Control Register
- 25.15.2 MUXCTRL – MUX Control Register
- 25.15.3 INTCTRL – Interrupt Control Register
- 25.15.4 INTFLAGS – Interrupt Flags Register
- 25.15.5 RESL – Result Register Low
- 25.15.6 RESH – Result Register High
- 25.15.7 SCAN – Scan Register
- 25.15.8 CORRCTRL - Correction Control Register
- 25.15.9 OFFSETCORR0 – Offset Correction Register 0
- 25.15.10 OFFSETCORR1 – Offset Correction Register 1
- 25.15.11 GAINCORR0 – Gain Correction Register 0
- 25.15.12 GAINCORR1 – Gain Correction Register 1
- 25.15.13 AVGCTRL – Average Control Register
- 25.16 Register Summary – ADC
- 25.17 Register Summary – ADC Channel
- 25.18 Interrupt Vector Summary
- 26. DAC – Digital to Analog Converter
- 26.1 Features
- 26.2 Overview
- 26.3 Voltage Reference Selection
- 26.4 Starting a Conversion
- 26.5 Output and Output Channels
- 26.6 DAC Output Model
- 26.7 DAC Clock
- 26.8 Low Power Mode
- 26.9 Calibration
- 26.10 Register Description
- 26.10.1 CTRLA – Control Register A
- 26.10.2 CTRLB – Control Register B
- 26.10.3 CTRLC – Control Register C
- 26.10.4 EVCTRL – Event Control Register
- 26.10.5 STATUS – Status Register
- 26.10.6 CH0GAINCAL – Gain Calibration Register
- 26.10.7 CH0OFFSETCAL – Offset Calibration Register
- 26.10.8 CH1GAINCAL – Gain Calibration Register
- 26.10.9 CH1OFFSETCAL – Offset Calibration Register
- 26.10.10 CH0DATAH – Channel 0 Data Register High
- 26.10.11 CH0DATAL – Channel 0 Data Register Low
- 26.10.12 CH1DATAH – Channel 1 Data Register High
- 26.10.13 CH1DATAL – Channel 1 Data Register Low
- 26.11 Register Summary
- 27. AC – Analog Comparator
- 27.1 Features
- 27.2 Overview
- 27.3 Input Sources
- 27.4 Signal Compare
- 27.5 Interrupts and Events
- 27.6 Window Mode
- 27.7 Input Hysteresis
- 27.8 Register Description
- 27.8.1 ACnCTRL – Analog Comparator n Control Register
- 27.8.2 ACnMUXCTRL – Analog Comparator n MUX Control Register
- 27.8.3 CTRLA – Control Register A
- 27.8.4 CTRLB – Control Register B
- 27.8.5 WINCTRL – Window Function Control Register
- 27.8.6 STATUS – Status Register
- 27.8.7 CURRCTRL – Current Source Control Register
- 27.8.8 CURRCALIB – Current Source Calibration Register
- 27.9 Register Summary
- 27.10 Interrupt Vector Summary
- 28. PDI – Program and Debug Interface
- 28.1 Features
- 28.2 Overview
- 28.3 PDI Physical
- 28.4 PDI Controller
- 28.4.1 Accessing Internal Interfaces
- 28.4.2 NVM Programming Key
- 28.4.3 Exception Handling
- 28.4.4 Reset Signalling
- 28.4.5 Instruction Set
- 28.4.5.1 LDS - Load Data from PDIBUS Data Space using Direct Addressing
- 28.4.5.2 STS - Store Data to PDIBUS Data Space using Direct Addressing
- 28.4.5.3 LD - Load Data from PDIBUS Data Space using Indirect Addressing
- 28.4.5.4 ST - Store Data to PDIBUS Data Space using Indirect Addressing
- 28.4.5.5 LDCS - Load Data from PDI Control and Status Register Space
- 28.4.5.6 STCS - Store Data to PDI Control and Status Register Space
- 28.4.5.7 KEY - Set Activation Key
- 28.4.5.8 REPEAT - Set Instruction Repeat Counter
- 28.4.6 Instruction Set Summary
- 28.5 Register Description – PDI Instruction and Addressing Registers
- 28.6 Register Description – PDI Control and Status Registers
- 28.7 Register Summary
- 29. Memory Programming
- 29.1 Features
- 29.2 Overview
- 29.3 NVM Controller
- 29.4 NVM Commands
- 29.5 NVM Controller Busy Status
- 29.6 Flash and EEPROM Page Buffers
- 29.7 Flash and EEPROM Programming Sequences
- 29.8 Protection of NVM
- 29.9 Preventing NVM Corruption
- 29.10 CRC Functionality
- 29.11 Self-programming and Boot Loader Support
- 29.11.1 Flash Programming
- 29.11.2 NVM Flash Commands
- 29.11.2.1 Read Flash
- 29.11.2.2 Erase Flash Page Buffer
- 29.11.2.3 Load Flash Page Buffer
- 29.11.2.4 Erase Flash Page
- 29.11.2.5 Write Flash Page
- 29.11.2.6 Flash Range CRC
- 29.11.2.7 Erase Application Section / Boot Loader Section Page
- 29.11.2.8 Application Section / Boot Loader Section Page Write
- 29.11.2.9 Erase and Write Application Section / Boot Loader Section Page
- 29.11.2.10 Application Section / Boot Loader Section CRC
- 29.11.2.11 Erase User Signature Row
- 29.11.2.12 Write User Signature Row
- 29.11.2.13 Read User Signature Row / Production Signature Row
- 29.11.3 NVM Fuse and Lock Bit Commands
- 29.11.4 EEPROM Programming
- 29.11.5 NVM EEPROM Commands
- 29.12 External Programming
- 29.12.1 Enabling External Programming Interface
- 29.12.2 NVM Programming
- 29.12.3 NVM Commands
- 29.12.3.1 Chip Erase
- 29.12.3.2 Read NVM
- 29.12.3.3 Erase Page Buffer
- 29.12.3.4 Load Page Buffer
- 29.12.3.5 Erase Page
- 29.12.3.6 Write Page
- 29.12.3.7 Erase and Write Page
- 29.12.3.8 Erase Application / Boot Loader/ EEPROM Section
- 29.12.3.9 Application / Boot Section CRC
- 29.12.3.10 Flash CRC
- 29.12.3.11 Write Fuse / Lock Bit
- 29.13 Register Description
- 29.14 Register Summary
- 30. Peripheral Module Address Map
- 31. Instruction Set Summary
- 32. Revision History
- Table of Contents