Xtensa Instruction Set Architecture (ISA) Reference Manual ASSEMBLER GUIDE
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- Xtensa® Instruction Set Architecture (ISA)
- Contents
- List of Figures
- List of Tables
- Preface
- Changes from the Previous Version
- 1. Introduction
- 2. Notation
- 3. Core Architecture
- 4. Architectural Options
- 4.1 Overview of Options
- 4.2 Core Architecture
- 4.3 Options for Additional Instructions
- 4.3.1 Code Density Option
- 4.3.2 Loop Option
- 4.3.3 Extended L32R Option
- 4.3.4 16-bit Integer Multiply Option
- 4.3.5 32-bit Integer Multiply Option
- 4.3.6 32-bit Integer Divide Option
- 4.3.7 MAC16 Option
- 4.3.8 Miscellaneous Operations Option
- 4.3.9 Coprocessor Option
- 4.3.10 Boolean Option
- 4.3.11 Floating-Point Coprocessor Option
- 4.3.12 Multiprocessor Synchronization Option
- 4.3.13 Conditional Store Option
- 4.4 Options for Interrupts and Exceptions
- 4.4.1 Exception Option
- 4.4.1.1 Exception Option Architectural Additions
- 4.4.1.2 Exception Causes under the Exception Option
- 4.4.1.3 The Miscellaneous Program State Register (PS) under the Exception Option
- 4.4.1.4 Value of Variables under the Exception Option
- 4.4.1.5 The Exception Cause Register (EXCCAUSE) under the Exception Option
- 4.4.1.6 The Exception Virtual Address Register (EXCVADDR) under the Exception Option
- 4.4.1.7 The Exception Program Counter (EPC) under the Exception Option
- 4.4.1.8 The Double Exception Program Counter (DEPC) under the Exception Option
- 4.4.1.9 The Exception Save Register (EXCSAVE) under the Exception Option
- 4.4.1.10 Handling of Exceptional Conditions under the Exception Option
- 4.4.1.11 Exception Priority under the Exception Option
- 4.4.2 Relocatable Vector Option
- 4.4.3 Unaligned Exception Option
- 4.4.4 Interrupt Option
- 4.4.5 High-Priority Interrupt Option
- 4.4.6 Timer Interrupt Option
- 4.4.1 Exception Option
- 4.5 Options for Local Memory
- 4.5.1 General Cache Option Features
- 4.5.2 Instruction Cache Option
- 4.5.3 Instruction Cache Test Option
- 4.5.4 Instruction Cache Index Lock Option
- 4.5.5 Data Cache Option
- 4.5.6 Data Cache Test Option
- 4.5.7 Data Cache Index Lock Option
- 4.5.8 General RAM/ROM Option Features
- 4.5.9 Instruction RAM Option
- 4.5.10 Instruction ROM Option
- 4.5.11 Data RAM Option
- 4.5.12 Data ROM Option
- 4.5.13 XLMI Option
- 4.5.14 Hardware Alignment Option
- 4.5.15 Memory ECC/Parity Option
- 4.6 Options for Memory Protection and Translation
- 4.6.1 Overview of Memory Management Concepts
- 4.6.2 The Memory Access Process
- 4.6.3 Region Protection Option
- 4.6.4 Region Translation Option
- 4.6.5 MMU Option
- 4.6.5.1 MMU Option Architectural Additions
- 4.6.5.2 MMU Option Register Formats
- 4.6.5.3 The Structure of the MMU Option TLBs
- 4.6.5.4 The MMU Option Memory Map
- 4.6.5.5 Formats for Writing MMU Option TLB Entries
- 4.6.5.6 Formats for Reading MMU Option TLB Entries
- 4.6.5.7 Formats for Probing MMU Option TLB Entries
- 4.6.5.8 Format for Invalidating MMU Option TLB Entries
- 4.6.5.9 MMU Option Auto-Refill TLB Ways and PTE Format
- 4.6.5.10 MMU Option Memory Attributes
- 4.6.5.11 MMU Option Operation Semantics
- 4.7 Options for Other Purposes
- 5. Processor State
- 5.1 General Registers
- 5.2 Program Counter
- 5.3 Special Registers
- 5.3.1 Reading and Writing Special Registers
- 5.3.2 LOOP Special Registers
- 5.3.3 MAC16 Special Registers
- 5.3.4 Other Unprivileged Special Registers
- 5.3.5 Processor Status Special Register
- 5.3.6 Windowed Register Option Special Registers
- 5.3.7 Memory Management Special Registers
- 5.3.8 Exception Support Special Registers
- 5.3.9 Exception State Special Registers
- 5.3.10 Interrupt Special Registers
- 5.3.11 Timing Special Registers
- 5.3.12 Breakpoint Special Registers
- 5.3.13 Other Privileged Special Registers
- 5.4 User Registers
- 5.5 TLB Entries
- 5.6 Additional Register Files
- 5.7 Caches and Local Memories
- 6. Instruction Descriptions
- ABS ar, at
- ABS.S fr, fs
- ADD ar, as, at
- ADD.N ar, as, at
- ADD.S fr, fs, ft
- ADDI at, as, -128..127
- ADDI.N ar, as, imm
- ADDMI at, as, -32768..32512
- ADDX2 ar, as, at
- ADDX4 ar, as, at
- ADDX8 ar, as, at
- ALL4 bt, bs
- ALL8 bt, bs
- AND ar, as, at
- ANDB br, bs, bt
- ANDBC br, bs, bt
- ANY4 bt, bs
- ANY8 bt, bs
- BALL as, at, label
- BANY as, at, label
- BBC as, at, label
- BBCI as, 0..31, label
- BBCI.L as, 0..31, label
- BBS as, at, label
- BBSI as, 0..31, label
- BBSI.L as, 0..31, label
- BEQ as, at, label
- BEQI as, imm, label
- BEQZ as, label
- BEQZ.N as, label
- BF bs, label
- BGE as, at, label
- BGEI as, imm, label
- BGEU as, at, label
- BGEUI as, imm, label
- BGEZ as, label
- BLT as, at, label
- BLTI as, imm, label
- BLTU as, at, label
- BLTUI as, imm, label
- BLTZ as, label
- BNALL as, at, label
- BNE as, at, label
- BNEI as, imm, label
- BNEZ as, label
- BNEZ.N as, label
- BNONE as, at, label
- BREAK 0..15, 0..15
- BREAK.N 0..15
- BT bs, label
- CALL0 label
- CALL4 label
- CALL8 label
- CALL12 label
- CALLX0 as
- CALLX4 as
- CALLX8 as
- CALLX12 as
- CEIL.S ar, fs, 0..15
- CLAMPS ar, as, 7..22
- DHI as, 0..1020
- DHU as, 0..240
- DHWB as, 0..1020
- DHWBI as, 0..1020
- DII as, 0..1020
- DIU as, 0..240
- DIWB as, 0..240
- DIWBI as, 0..240
- DPFL as, 0..240
- DPFR as, 0..1020
- DPFRO as, 0..1020
- DPFW as, 0..1020
- DPFWO as, 0..1020
- DSYNC
- ENTRY as, 0..32760
- ESYNC
- EXCW
- EXTUI ar, at, shiftimm, maskimm
- EXTW
- FLOAT.S fr, as, 0..15
- FLOOR.S ar, fs, 0..15
- IDTLB as
- IHI as, 0..1020
- IHU as, 0..240
- III as, 0..1020
- IITLB as
- IIU as, 0..240
- ILL
- ILL.N
- IPF as, 0..1020
- IPFL as, 0..240
- ISYNC
- J label
- J.L label, an
- JX as
- L8UI at, as, 0..255
- L16SI at, as, 0..510
- L16UI at, as, 0..510
- L32AI at, as, 0..1020
- L32E at, as, -64..-4
- L32I at, as, 0..1020
- L32I.N at, as, 0..60
- L32R at, label
- LDCT at, as
- LDDEC mw, as
- LDINC mw, as
- LICT at, as
- LICW at, as
- LOOP as, label
- LOOPGTZ as, label
- LOOPNEZ as, label
- LSI ft, as, 0..1020
- LSIU ft, as, 0..1020
- LSX fr, as, at
- LSXU fr, as, at
- MADD.S fr, fs, ft
- MAX ar, as, at
- MAXU ar, as, at
- MEMW
- MIN ar, as, at
- MINU ar, as, at
- MOV ar, as
- MOV.N at, as
- MOV.S fr, fs
- MOVEQZ ar, as, at
- MOVEQZ.S fr, fs, at
- MOVF ar, as, bt
- MOVF.S fr, fs, bt
- MOVGEZ ar, as, at
- MOVGEZ.S fr, fs, at
- MOVI at, -2048..2047
- MOVI.N as, -32..95
- MOVLTZ ar, as, at
- MOVLTZ.S fr, fs, at
- MOVNEZ ar, as, at
- MOVNEZ.S fr, fs, at
- MOVSP at, as
- MOVT ar, as, bt
- MOVT.S fr, fs, bt
- MSUB.S fr, fs, ft
- MUL.AA.* as, at
- MUL.AD.* as, my
- MUL.DA.* mx, at
- MUL.DD.* mx, my
- MUL.S fr, fs, ft
- MUL16S ar, as, at
- MUL16U ar, as, at
- MULA.AA.* as, at
- MULA.AD.* as, my
- MULA.DA.* mx, at
- MULA.DA.*.LDDEC mw, as, mx, at
- MULA.DA.*.LDINC mw, as, mx, at
- MULA.DD.* mx, my
- MULA.DD.*.LDDEC mw, as, mx, my
- MULA.DD.*.LDINC mw, as, mx, my
- MULL ar, as, at
- MULS.AA.* as, at
- MULS.AD.* as, my
- MULS.DA.* mx, at
- MULS.DD.* mx, my
- MULSH ar, as, at
- MULUH ar, as, at
- NEG ar, at
- NEG.S fr, fs
- NOP
- NOP.N
- NSA at, as
- NSAU at, as
- OEQ.S br, fs, ft
- OLE.S br, fs, ft
- OLT.S br, fs, ft
- OR ar, as, at
- ORB br, bs, bt
- ORBC br, bs, bt
- PDTLB at, as
- PITLB at, as
- QUOS ar, as, at
- QUOU ar, as, at
- RDTLB0 at, as
- RDTLB1 at, as
- REMS ar, as, at
- REMU ar, as, at
- RER at, as
- RET
- RET.N
- RETW
- RETW.N
- RFDD
- RFDE
- RFDO
- RFE
- RFI 0..15
- RFME
- RFR ar, fs
- RFUE
- RFWO
- RFWU
- RITLB0 at, as
- RITLB1 at, as
- ROTW -8..7
- ROUND.S ar, fs, 0..15
- RSIL at, 0..15
- RSR.* at
- RSR at, *
- RSR at, 0..255
- RSYNC
- RUR.* ar
- RUR ar, *
- S8I at, as, 0..255
- S16I at, as, 0..510
- S32C1I at, as, 0..1020
- S32E at, as, -64..-4
- S32I at, as, 0..1020
- S32I.N at, as, 0..60
- S32RI at, as, 0..1020
- SDCT at, as
- SEXT ar, as, 7..22
- SICT at, as
- SICW at, as
- SIMCALL
- SLL ar, as
- SLLI ar, as, 1..31
- SRA ar, at
- SRAI ar, at, 0..31
- SRC ar, as, at
- SRL ar, at
- SRLI ar, at, 0..15
- SSA8B as
- SSA8L as
- SSAI 0..31
- SSI ft, as, 0..1020
- SSIU ft, as, 0..1020
- SSL as
- SSR as
- SSX fr, as, at
- SSXU fr, as, at
- SUB ar, as, at
- SUB.S fr, fs, ft
- SUBX2 ar, as, at
- SUBX4 ar, as, at
- SUBX8 ar, as, at
- SYSCALL
- TRUNC.S ar, fs, 0..15
- UEQ.S br, fs, ft
- UFLOAT.S fr, as, 0..15
- ULE.S br, fs, ft
- ULT.S br, fs, ft
- UMUL.AA.* as, at
- UN.S br, fs, ft
- UTRUNC.S ar, fs, 0..15
- WAITI 0..15
- WDTLB at, as
- WER at, as
- WFR fr, as
- WITLB at, as
- WSR.* at
- WSR at, *
- WSR at, 0..255
- WUR.* at
- WUR at,*
- XOR ar, as, at
- XORB br, bs, bt
- XSR.* at
- XSR at, *
- XSR at, 0..255
- 7. Instruction Formats and Opcodes
- 8. Using the Xtensa Architecture
- A. Differences Between Old and Current Hardware
- Index