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EPSON pe AX
TECHNICAL MANUAL

Seiko Epson Corporation
Nagano,Japan
Y12699900201

Fce eOMPLIANCE STATEMENT

This equlpment uses and generates radio trequency energy and It not installed and used properly.
that Is In strlct accordance wlth the manutacture's Instructlons, may cause Interference to radio
and television receptlon.
It has been type tested and tound to comply wlth limits tor a Class B computlng devlce In
accordance wlth Sub- part J of Part 15 of FCC Rules, whlch are designed to provlde reasonable
protectlon agalnst such Interference in aresldential installation. However, there Is no guarantee
that Interference will not occur In a partlcular Installation. It thls equlpment dose causa
Interference to radio or television receptlon, whIch can be determlned by turnlng the equlpment
on and off, the user Is encouraged to try to correct the interference by one or more of the
tollowing measures:
reorlent the receivlng antenna
relocate the computer wlth respect to the receiver
move .the computer away tram the receiver
plug the computer into a different outtet so that the computer and receiver are on
different branch clrcults
It necessary, the user should consult the dealer or an experienced radio/television technician tor
additional suggestions. The user may tind the tollowing booklet, prepared by the Federal
Communicatlons Commlssion, helptul:
"How to Identity and Resoive Radio - TV interference Problems. ''This booklet Is avaiiable trom
the U.S. Government Printlng Office. Washington. D.C., 20402, Stock No. 044 - 000 - 00345 - 4.
You can determine whether your computer Is causing interference by turning It off. It the
Interference stops, it was probably caused by the computer or Its perlpheral devlces. To further
lsolate the problem. disconnect elther the perlpheral device or its 1/0 cable.
These devices usually require shielded cable. For Epson peripheral devices, you can obtaln the
proper shlelded cable trom your dealer. For non - Epson devlces. contact the manufacturer or
dealer tor asslstance.

Seiko Epson Corporatlon,

©

Nagano, Japan

1988 by Seiko Epson Corporation
All r1ghts reserved.
Prlnted In Japan

No portion of thls document may be reproduced, stored In a retrleval system, or transmitted In
any torm or by any means, electrlc. mechanlcal, photocopylng. recordlng, or otherwlse, wlthout
the written permission of Selko Epson Corporatlon. No patent liablllty Is assumed wlth respect
to use of the Information contalned herein, nor Is any liablllty assumed tor damages resultlng
trom usa cf thls text. Whlle every precautlon has been taken In the preparatlon cf thls bock,
the publlsher assumes no lIablllty tor errors or omisslons.
EPSON ® is a reglstered trademark of Seiko Epson Corporatlon.
EPSON PC AX ™ Is trademark of Selko Epson Corporatlon.
IBM ®
is a reglstered trademark ot International Business Machlnes Corporation.

PRECAUTIONS
Precautlonary notations throughout the text are categorlzed relative to 1) personalinjury and 2)
darnage to equlpment.
DANGER

Signals a precautlon whlch, If ignored, could result In serlous or fatal
personalinjury. Great caution should be exercised in performlng procedures
preceded by DANGER Headlngs.

WARNING

Signals a precaution whlch, If ignored, could result In damage to equlpment.

The precautlonary measures Itemlzed below should always be observed when performlng repalr/
rnalntenance procedures.

DANGER
1.

ALWAYS DISCONNECT THE PRODUCT FROM BOTH THE POWER
SOURCE AND PERIPHERAL DEVICES PERFORMING ANY
MAINTENANCE OR REPAIR PROCEDURE.

2.

NO WORD SHOULD BE PERFORMED ON THE UNIT BY PERSONS
UNFAMILIAR WITH BASIC SAFETY MEASURES AS DICTATED
FOR ALL ELECTRONICS TECHNICIANS IN THEIR L1NE OF WORK.

3.

WHEN PERFORMING TESTING AS DICTATED WITHIN THIS
MANUAL, 00 NOT CONNECT THE UNIT TO APOWER SOURCE
UNTIL INSTRUCTED TO 00 SO. WHEN THE POWER SUPPLY
CABLE MUST BE CONNECTED, USE EXTREME CAUTION IN
WORKING ON POWER SUPPLY AND OTHER ELECTRONIC COMPONENTS.

WARNING
1.

Repalrs on Epson product should be performed only by an Epsan
certlfled repair techniclan.

2.

Make certeln that the source voltage is the same as the rated
voltage, Iisted on the serial number/rating plate. If the Epson
product has a primary AC rating different from avallable power
saurce, do not connect It to the power source.

3.

Always verlfy that the Epson product has been disconnected from
the power source before removlng or replaclng prlnted circult
boards and/or Individual chips.

4.

In order to protect sensitive microprocessors and clrcultry, use
static discharge equlpment, such as antl- static wrist straps, when
accesslng Internal components.

5.

Replace rnalfunctlonlng components only wlth those components by
the manufacture; introductlon of second - source ICs or other nonapproved components may damage the product and vold any
applicable Epson warranty.

REVISION

ISSUE DATE

REV.A

December

REV.B

September 1988

1986

REVISION PAGE

1-7, 2-2, 2-6, 2-7, 2-10,
2-15, 2-25, 2-33, 2-36,
2-39, 2-40, 2-42, 2-51,
2-73
Chapter 8 added

PREFACE
Thls manual descrlbes the theory of operation of the EPSON PC AX microcomputer system, and
Includes troubleshootlng, repair, and malntenance procedures for servlng system subassemblles.
Thls text Is dlvlded into eight chapters:

CHAPTER 1.

CHAPTER 2.

PRODUCT DESCRIPTION ... Descrlbesthe features and speclflcatlons of
the computer, lIIustrates system components. and IIsts the loglc conflguratlon
of the prlmary clrcult board.
PRINCIPLES OF OPERATION. " Details the functional organizatlon cf the
loglc clrcultry.
configuratlons.

Thls

chapter

also

Illustrates

the

gate

array

pln

CHAPTER 3.

OPTIONS . "

CHAPTER 4.

TROUBLESHOOTING . " ProvIdes Instructions for isolating computer mal-

Descrlbes option card speciflcatlons and the operating prlnclpies of the options.

functlons.

CHAPTER 5.

DISASSEMBLY AND ASSEMBLY . .. Descrlbes system dlsassembly for
replacement of malfunctlonlng subassemblles.

CHAPTER 6.

ADJUSTMENT AND MAINTENANCE ... Usts the necessary adjustments for
unlt assembly and servlclng.

CHAPTER 7.

DIAGRAMS AND REFERENCE MATERIALS ... Descrlbes jumper settings
and connector pln asslgnments. Thls chapter also provldes expIoded clrcult
board layout and schematlc dIagrams for use In conjunctlon wIth the text.

CHAPTER 8.

DIFFERENCES BETWEEN 1OMHz AND 12 MHz ... Descrlbes between the
EPSON PC AX 10MHz and the 12MHz, and includes the schematics for use In
conJunctlon with the the 12MHz.

SUbsequent product modlflcatlons will be brought to your attention via Service Bulletins; please revlse
the text as bulletins are recelved.

Thls document Is subJect to change without notice.

TABLE OF CONTENTS

CHAPTER 1.

PRODUCT DESCRIPTION. . . . . . . . . . . . . . . 1 - 1

CHAPTER 2.

PRINCIPLES OF OPERATION

CHAPTER 3.

OPTIONS........................ 3 - 1

CHAPTER 4.

TROUBLESHOOTING................. 4 - 1

CHAPTER 5.

DISSEMBLY AND ASSEMBLY

CHAPTER 6.

ADJUSTMENT AND MAINTENACE . . . . . . . . . 6 - 1

CHAPTER 7.

DIAGRAMS AND REFERENCE MATERIALS . . . . 7 - 1

CHAPTER 8.

DIFFERENCES BETWEEN 10MHz AND 12MHz .. 8-1

2-1

5-1

CHAPTER
1

PRODOCT DESCRIPTION

TAßLE OF CONTENTS

Section

Title

Page

1.1

FEATU RES ......••.......••........••.........•............

1-1

1.2
1. 2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6

SPEC I FICATIONS ..........................•.•..............
t1ain System Unit Specifications .••......•...•......•...
Keyboard Specifications •..........••••.•.....•.........
FD1155C Floppy Disk Drive Specifications .... .... .••....
t1D5501-61 Floppy Disk Drive Specifications ....•.•......
D5146H Hard Disk Drive Specifications ..•........ .••. ...
Hr,1D-720 Hard Disk Drive Specifications .•.•.•.... ..•....

1-3
1-4
1-4
1-4
1-5
1-6
1-7

1.3
1.3.1
1.3.2

HARDWARE CONFIGURATION ............•......................
Main System Unit Components ..........•...•.••..........
Keyboard Components ............••..................••..

1-8
1-8
1-12

LIST OF FIGURES

Fi gure
1-1-1
1-3-1
1-3-2
1-3-3
1-3-4
1-3-5
1-3-6
1-3-7

Title

Page

Major Components

1-1
1-8
1-9
1-10
1-11
1-11
1-12
1-12

ANTA Boa rd ..........•..•........•.••........•.•..........

ANT- Rtl Boa rd ......••••...........••.......•.•.•..........
SPFG Board ......•.•......•••••.•.......•.••.......•••..••

ATRPS Unit ..............................•.••...........••
WHDC Boa rd •...••.•.........••..•.•.•..•.....•..•.••.•.•.•

Floppy Disk Drive Component ..••.•.......•.•...........••.
Keyboard Component ........•.........•••...........•......
LIST OF TAßLES

Table
1-3-1
1-3-2
1-3-3
1-3-4

Title
ANTA Board Component Descripti on .......•••.........••.•..
ANT- Rt,1 Boa rd Compon en t Descri pt ion ......•.••.............
SPFG Board Component Description •.••.•.....•.••..........
ATRPS Un i t Outputs .........•..............•........•..••.

Page
1-8
1-9
1-10
1-11

REV .A

1 .1

PROnUCT DESCRIPTIOR

FEATURES

The EQU1TY IlI+ / EPSON pe P\f.. computer system inc1udes two major elements; a
main system unit and a keyboard.

FIGURE 1-1-1. MAJOR. COMPORKRTS
The EQU1TY II1+ / EPSON PC P\f.. hardware configuration has
compatibility with the IBM AT and the new AT.

Cl

high degree of

System Performance
EQU1TY 111+ / EP SON pe P\f.. has three CPU execution speeds, these are the IBN AT
speed (6 MHz), the new AT speed (8 MHz) and a fast er speed (10 l'fiIz). Speed is
selected by setting a three-position switch easily accessed from the front.
The user can see the selected execution speed by the color of a 1ED.

Wait Cycles
EQUITY IlI+ / EPSON PC P\f.. uses several types of internal devices, such as RAM,
ROM, 16-bit extension memory, 16-bit 1/0 device, 8-bit extensi on memory anel
r,-bit 1/0 device at every CPU speed.
In the case of 6 MHz or 8 MHz, the
number of wait cycles is the same as the AT or the new AT.

1-1

PRODUCT DESCRIPTION

REV.A

WX Clock
The clock input
according to the
MHz and the new
(divided by three
the system board.

to
NPX
AT
in

the numerical processor extension (NPX) may be changed
version.
The standard clock input is 8 MHz (AT uses 4
uses 5.33 MHz).
Other clock-inputs, 20, 16, or 12 MHz
the NPX) may be selected by set t ing jumper connectors on

Mass Memory
EQU11Y 111+ / EPSON PC AX supports 4 types of built-in mass memory.
Hass Memory Slots
EQUITY 111+
are several
drives, (2)
drive and 2

/ EPSON PC AX has 5 half-height slots for FDD's and
ways to install the drives in these slots: (1)
3 half-height drives and a full-height drive, (3)
full-height drives. A maximum of four drives can be

IIDD's. There
4 half-height
a half-height
installed.

Power Supply
EQUITY 11I+ / EPSON PC AX has an IBM AT compatible power unit.
Hs
specification is world wide, using 115 V /220 V, switch selected, UL/CSA and
TUV standard, and FCC/FTZ standard. The number of power cables is 4.
Multi-function Card
The multi-function carc in the EPSON proprietary slot provides the serial
communication port, parallel printer port and floppy disk controller.
Hard Disk Controller
The hard disk controller contained in the prorietary slot will control two
hard disks.
Packaging
All switches and controls are easily accessible.
Switches control the
processor execution speed, and the type of the display, color or monochrome.
1t is easy to connect the keyboard, control the volume, push the reset button,
turn the power on or off, and lock or unlock the main unit. When the unit i8
locked, the system does not accept key input and ignores the reset button.
Exterior
The unit is designed in line with the EQU1TY / EPSON PC series, which visually
distinguishes it from the numerous compatibles.

1-2

REV.A

1.2

PRODUCT DESCRIPTION

SPECIFICATION

The following sections describe detail specifications by major subassembly.
POWER SUPPLY

Hax.
4 A
Min. 92 V
Max. 132 V
2.5 A
Hax.
230 VAC
Min. 196 V
Max. 265 V
F requency
. 49 - 61Hz
230 VAC approx. 60W
Power Consumption .....••••. 115 VAC:
Surge Current •......•.•.... 42 A O-P (0.5 sec. more)
Input

115 VAC

INSOLATION STRKRG'l'H

115 VAC: AC 1.25 kV (l min.) (AC-FG, ACSecondary)
230 VAC: AC 1.25 kV (1 min.) (AC-FG)
AC 3.75 kV (1 min.) (AC-Secondary)

INSOLATION RESISTANCE

25 MOhm more (500 VDC) (AC-FG,AC-Secondary)
1 MOhm more (250 VDC) (SG-FG) (DIC short
jumper not installed)

ElNIRONMENT CONDITIONS
OPERATING

NON-OPERATING

5~ to 35~

° to 60°C
- 20'C

Humidity
20% to 80%
(non-condensing)
Maximum wet bulb
29 deg.

10% to 90%

5% to 95%

40 deg.

45 deg.

Temperature

Vibration
Shock (non-HDD)
Shock

(HDD)

Alti tude (HDD)

0.2 G
1 G (less than
10ms)
1 G (less than
25mm 0-60Hz)
o to 3000 m. ASL

1 G (non-HDD)
0.5 G (HDD)
3 G (less than
10ms)
3 G (less than
25mm 0-60Hz)
-300 to 3600 m. ASL

STORAGE

3 G (non-HDD)
0.5 G (FIDD)
30 G (less than
(lOms)

20 G (less than
25mm 0-60Hz)
-300 to 3600 m.
ASL

1-3

PRODUCT DESCRlP TION

1.2.1

REV.A

Main System Unit Specifications

PROCESSOR ••.•.•..•..•.•••
CO-PROCESSOR •••••.••.••..
ROM •..•.•••.••••....•.•••
RAM ••..••......•.•..•.•..
MASS MEMORy
MASS MEMORY SLOTS ••••.•.•
CPU CLüCK ••••.••..•.•...•
HAlT CYCLES ...•.•••......
DIMENSIONS (W x D x R) ••.
WEICHT ••.•.•..•.••.•..••.
1.2.2

Keyboard Specifications

LAYOUT ..••••••••....•..••
CORD ..•••.••.••.••.•.•..•
DIMENSIONS (W x D x H) ....
lmICHT .•••.••.••.••..•...

1.2.3

80286-10
80287-8
64KB (27256 x 2)
640KB is standard
5 1/4" 1.2MB FDD is standard
6 16-bit 1/0 expansion slots
3 8-bit 1/0 expansion slots
6 }lliz, 8 }lliz, 10 }lliz
(Switch selectable)
Selectable
498.5 x 442 x 169 mm
14.5 Kg (Standard model - 1FDD)

New AT compatible
App rox. 2 met ers
490 x 197.5 x 47.7 mm
1.8 Kg

FD1155C Floppy Disk Drive Specification
High Density Mode

Capacity (KBytes)
Unformatted
Formatted
Transfer Rate (K-bits/sec)
Number of Tracks
Recording Density (BPI max.)

1-4

(MFM
1670
1065
1229
1311
500
160
9870

/ FM)
/ 830
/ 532 (256 byte x 26 sector)
/ 614 (512 byte x 15 sector)
/ 655 (1024 byte x 8 sector)
/ 250
(80 tracks x 2 sides)

PRODUCT DESCRIPTIOH

REV.A

Normal Density Mode
Capacity (KBytes)
Unformatted
Formatted
Transfer Rate
Number of Tracks
Recording Density (HPI max. )
Seek Speed (1 track)
Seek Settling Time
Head Loading Time
Disk Speed
Track Density
Recording Method
Power Consumption x 2

1.2.4

(MFM
1000
655
300
160
5922

/ FM)
/ 500
/ 328 (256 byte x 16 sector)
/ 150
(80 tracks x 2 sides)

3 ms
15 ms
35 ms
360 RPM
96 TPI
HFtl/FM
4.8 w

MD5501-61 Floppy Disk Drive Specification
Normal Density Mode

Capacity (KBytes)
Unformatted
Formatted (IBM
format)

TP I

Lf8

500
327.7
(8 sector)

Transfer Rate (Kbits/sec.)
300
Access Time (track-track)(ms) 10
Recording Density (BPI)
5876
Number of Tracks (p.er side)
40
Seek Settling Time
Disk Speed
Recording Mode
Power Consumption

96 TPI
1000
655.4
(16 sector)

300

High Density Mode
96 TPI

1667
1065
(26 sector)
500

5

3

5922
80

9870
80

15 ms
360 RPH
HFN
3.0

\v

1-5

PRODUCT DFßCRIPTION

1.2.5

REV.A

D5146H Hard Disk Drive Specification

Capacity
Unformatted
51.24
per Cylinder
83,328
per Track
10,416
Formatted
40.30
per Cylinder
65,536
per Track
8,192
per Sector
256
Number of Cylinders
615
Sectors per Track
32
Bytes per Sector
256
lf
Number of Disks
Number of Heads
8
Transfer Rate
Access Time
Track-Track
Average Seek
Max. Seek
Disk Speed
Start Time
Stop Time
Recording Methoc1
Recording Density
Track Density

MBytes
bytes
bytes
MBytes
bytes
bytes
bytes

625 KB/sec
8
40
75
3600
25
30
MFH
9000
700

ms
ms
ms
RPH

sec.
sec.
BPI
'!PI

Environment Conditions
Operatin$
Temperature
5~ - 4)C
Humidity
8% - 80%

Storage

-4dt - 6&

( 29°c)

Vibration
Shock
Altitude
Power Consumption

1-6

o

0.2 G
2.0 G
- 3000 m
3.0 w

0.5 G (0-60Hz, less than 25 nun)
20.0 G
-300 - 3600 m

REV.B

1.2.6

PRODueT DESCRIPTION

BMD-720 Hard Disk Drive Specification

Capacity
25.5
Unformatted
10,416
per Track
20.0
Formatted
8,192
per Track
256
per Sector
615
Number of Cylinders
2460
Number of Tracks
32
Sectors per Track
256
Bytes per Sector
2
Number of Disks
4
Number of Heads
Transfer Rate
Access Time
Track-Track
Average Seek
Max. Seek
Disk Speed
Recording Method
Recording Density
Track Density
Interface

MBytes
bytes
MBytes
bytes
bytes

5 Mbits/sec
18
69
150
3528

ms
ms
ms
RPH +/ -1%

MFM
12900 BPI
910 '!PI
ST-506/412

Environment Conditions
Operatin&
5°C - 50C
Temperature
8% - 80%
Humidity
(26C)
3000 m
Altitude
Shock-Vibration
No Soft Errors
Vibration
Shock
No Hard Errors
Vibration
Shock
PmJer Consumption

Storage
-40°C - 6.fC
8% - 85%
( 30C)

10000 m

0.4 G, 36-500 Hz
8 G, 10 os
2 G, 14-500 Hz
20 G, 10 ms

3 G, 12-500 Hz
40 G, 10 ms

8.0 w

1-7

PRODUCT DESCRlPTION

1.3

HEV.A

HARDWARE CONFIGURATION

1.3.1

Hain System Unit Components
TABLE 1-3-1. ANTA BOARD COMPONENT DESCRlPTION

NAHE

MODEL

Qty

80286-10
80287-8
8237 A-5

CPU
NPX
DMAC
INTC
TIMER
REAL TIME
KEYBOARD I/F
GAATAB

8254-2
146818
8042
E01085CB

1
1
2
2
1
1
1
1

GAATCB

E01086CA

1

GAA'IDB

E01068CA

1

GAATCK

E01068CA

1

GAATRF

E01069BB

1

GAATIO

E01092EA

1

8259A

FUNCTION

16 bit CPU
Co-processor (socket only)
DMA control
Interrupt control
Support 3 clock channels
System clock t calender and CUOS RAM
Interface between 80286 and keyboard
Controls CPU address bus (A16-0) t system
addtess bus (5A16-0) and internal address
bus (XA16-0). Generates refresh address.
Control bus (1/0 write pulset 1/0 read
pu lse t memory wri te pulse, memory read
pulse) and 7 MSB of address bus (A23-17) and
bus high enable signal.
Control CPU bus (D15-0), system data bus
(SD1S-0) and memory data bus (}ID15-0)
Clock generator, bus controller and shut
dOvrn circuit.
Controls D-RAM refresh, DHA transfer t 16-B
data bit conversioD t and wait state
insertion.
Address decoder for 1/0 space and r/o
registers.

FIGURE 1-3-1. ANTA BOARD

1-8

PRODUCT DESCRIPTION

HEV.A

TABLE 1-3-2. ABT-RH BOARD COMPONENT DESCRIPTION
NAME

MODEL

ROH
GAATH1

MB81256-10Z
MB81464-12P
uPD4164-12
27256
EOI090BA

GAATM2

E01091EA

Qty

18
4
2
2
1
1

FUNCTION

256Kbit dynamic RAM (Parity check RAH)
64KB x 4 dynamic RAM
Parity check RAM
BIaS ROM
Address decoder for memory space and parity
checker / generator for system D-RA}I.
Generates D-RAM address (MA8-0) and D-RAM
access signals (RAS, CAS and WE)

FIGURE 1-3-2. ABT-RH BOARD

1-9

PRODUCT DESCRIPTION

HEV.A

TABU 1-3-3. SPFG BOARD COMPONENT DESCRIPTION

MODEL

Q'ty

FDC
GAATSP

uPD765A
E01093BA

1

GAATFD

E01094BA

Q

16450

1

SERIAL
CONTROLLER

1

FUNcnON

Controls FDD's.
Parallel port and address decoder for serial
port.
Controls 360KB and 1.2MB diskette drives.
Includes FDOR (Floppy digital output
register), FCR (Floppy control register) and
write precornpensation circuit.
Controls serial data transfer.

FIGURE 1-3-3. SPFG BOARD

1-10

PRODUCT DESCRIPTION

REV.A

TABLE 1-3-4. ATRPS UNIT OU1PUTS
WMINAL
LOAD CURREBT
MIN. [A]
OU1PUT [VDC]

2.5
0

+5
-5
+12
-12

0
0

*

LOAD CURREBT
HAX. [A]

REGULATION
TOLERANCE

20
0.3
4.8 (7.0)
0.3

*

+- 4%
+-10%
+- 5%
+-10%

OVERLOAD
PROTECTION [A]

35
3
16
3

10 sec.

FIGURE 1-3-4.

ATRP S UNIT

FIGURE 1-3-5. WHDC BOARD

1-11

PRODUCT DESCRIPTION

REV.A

FIGURE 1-3-6.

FLOPPY DISK DRIVE COMPONENTS

Refer to Chapter 3 for the Floppy disk drive components.

1.3.2

Keyboard Components

The new IBM AT
marked) •

compatible keyboard

(with

'horne'

posHion keys F, J

FIGURE 1-3-7. KEYßOARD COMPONENT

1-12

and 5

CHAPTER
2

PRINCIPLES OF OPERATION

TABLE OF CONTENTS
Section

Title

2.1

MAIN SYSTEM UNIT COMPONENTS

2.2
2.2.1
2.2.1.1
2.2.1.2

ATRPS POWER SUPPLY UNIT
Primary Oscillation Circuit

2.2.1.3
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.2
2.3.2.1
2.3.3
2.3.3.1
2.3.3.2
2.3.3.3
2.3.3.4
2.3.4
2.3.4.1
2.3.4.2
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
2.3.7
2.3.7.1
2.3.7.2
2.3.8

Page
2-1
.
.

Power Supply Circuit

.

Overcurrent Prevention Circuit of the MOS-FET
On-Off Control Circuit
Inrush Current Prevention Circuit

.
.

Secon da ry Ci rcu it

.

-5V and -12V Circuit

.

+12V Supply Circuit
+5V Supply Circuit

.
.

Overheating Prevention Circuit
Power Good Signal Generation Circuit

.
.

ANTA MAIN CONTROL BOARD OPERATION
System Clock Generation Circuit
Select CPU Operation Speed
LED Indications
Select NPX (80287) Operation Speed
Ose; 11 ator

System Reset Signal Generation Circuit
System Reset Circuit
Internal Memory Control Circuit

.
.
.
.
.
.

.
.
.

RAM Chip Type ••.•...•...•..••...•.•.....••••..••..••..
RAf\1 Chip Addresses ...•....•...••..••......••......••..

Jumper Connector Function
.
Operation of ~~emory Control Circuit .•.................
Byte/Word Access & 16-8 Bit Data Conversion
.
Data Bus Control Signal on GAATDB
.
Circuit Operation of Data Conversion
.
.
1/0 Device Access Circuit
OMA Contral Circuit
.
Page Register Setting Circuit
.
8-bit DNA {Internal memory -- 1/0)
.
8-bit DMA (Internal memory -- Internal memory)
.
16-bit DMA (Internal memory -- 1/0)
.
Ready Signal Control Circuit
.
Insertion flore Wait Cycle
.
Zero Wait Cycl e Request
.
Command Delay Signal Control Circuit
.

2-2
2-2
2-2
2-4
2-5
2-6
2-6
2-7
2-10
2-13
2-13
2-19
2-21
2-21
2-21
2-22
2-23
2-25
2-26
2-28
2-28
2-29
2-29
2-29
2-32
2-32
2-33
2-41
2-42
2-42
2-43
2-43
2-43
2-48
2-49
2-49
2-51

2.3.9
2.3.10
2.3.10.1
2.3.11
2.3.12
2.3.13
2.3.14
2.3.14.1
2.3.14.2
2.3.14.3
2.3.14.4
2.3.14.5
2.3.14.6
2.3. 15

Interrupt Control Circuit
RO~~

Access Circuit

Available ROM Types
D- RÄf'1 Refre sh Ci rcu i t
RAM Parity Check Circuit
Speaker Control Circuit
Keyboard Interface Circuit & Other Circuit
Keyboard Interface

.
.

.
.
.
.
.
.

RAr-.1 Si ze Rea d; n9 .•••••••••••••..•.•...•.••......•...••

Setting Reading
.
Disabling Keyboard Scan Codes
.
Software Reset Signal Generation
.
Address A20 Signal Control
.
1/0 Slot Access Signal .•...............................
~1onitor

2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.1.3
2.4.2
2.4.2.1
2.4.2.2
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.3.4
2.4.3.5

MULTI-FUNCTION ADAPTER (SPFG BOARD) OPERATION
Serial Interface
16540 Chip Select Circuit

2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.3
2.5.3.1
2.5.3.2
2.5.3.3
2.5.3.4
2.5.3.5
2.5.4
2.5.5
2.5.6
2.5.6.1
2.5.6.2
2.5.6.3
2.5.6.4
2.5.6.5
2.5.6.6
2.5.6.7
2.5.7
2.5.7.1
2.5.7.2

KEYBOARD ••••••••••••••.••••••.•••••••••••••••••••••••••••

Interface Signal

Data Buffer Direction Control Signal
Parallel Data Control Circuit
1/0 Address Selection
Parallel Data Control Circuit Functions
FDD Contral Circuit

.
.
.
.

.
.
.
.
.

FDD Control Register Access Circuit
Interrupt Signal and DMA Request Signal from FDC
FDD Con t ro1 Si gn als
Read/Wri te Ci rcu i t

.
.
.
.

Other Functions

.

Block Diagram

.

Interface Signal

.

AT t,1ode •......••••....••.........•.••.••.••...•.•••••.
XT Mode .............................................•.

Description of Interface Signals (AT Mode)

.

Clock

.

Data

.

Keyboa rd Data Output (AT t1ode) ........•...............
Keyboa rd Data Input (AT t1ode)
.
Data Transmission Method and Data Format
.
Interface Circuit Specification
.
Connector Pin Explanation
.
Function Specifications ...............•................
Strake Characteristics .••...••••.•••...•..•••..••••.•.
Typematic Function
Keyboa rd Buffer

.
.

Power On Reset (AT ~1ode)
.
Initializing (XT Mode) .....•..........................
Data Wait Function (XT Mode)
.
Mode Indicator (3 LED's) Display (XT ~1ode)
.
Key Scan Code

Key Code Output (AT Mode)
Key Code Output (XT tlode)

.

.
.

2-53
2-54
2-54
2-56
2-58
2-60
2-61
2-61
2-61
2-61
2-61
2-61
2-62
2-64
2-65
2-65
2-65
2-65
2-66
2-66
2-66
2-66
2-70
2-70
2-70
2-70
2-71
2-74
2-77
2-77
2-78
2-78
2-79
2-79
2-79
2-79
2-79
2-80
2-80
2-82
2-82
2-83
2-83
2-83
2-84
2-84
2-85
2-85
2-86
2-87
2-87
2-91

2.5.8
2.5.8.1
2.5.8.2

Commands (AT t10de)
Commands From the Host Side
Commands To the Host Si de

2-91
2-91
2-96

LIST OF FIGI RES
Fi gu re
2-1-1
2-2-1
2-2-2
2-2-3
2-2-4
2-2-5
2-2-6
2-2-7
2-2-8
2-2-9
2-2-10
2-2-11
2-2-12
2-2-13
2-2-14
2-2-15
2-2-16
2-2-17
2-2-18
2-2-19
2-2-20
2-2-21
2-2-22
2-2-23
2-3-1
2-3-2
2-3-3
2-3-4
2-3-5
2-3-6
2-3-7
2-3-8
2-3-9
2-3-10
2-3-11
2-3-12
2-3-13

Title
Logic Block Diagram
.
Basic Operation Circuit ...............•..................
Switching Oscillation Circuit I
.
Switching Oacillation Circuit 11 ......•..................
Overcurrent Prevention Circuit I
.
Overcurrent Prevention Circuit 11
.
Inrush Current Prevention Circuit
.
Functions of Resistor R5 and R6
.
-5V and -12V Supply Circuit ...........•..................
+12V Supply Circuit
.
+12V Stabilization Circuit
.
Voltage Stabilization Circuit 11
.
Characterize of Z3
.
Fan Revolution Speed Control Circuit
.
.
Overcurrent Prevention Circuit
+5V Supply Circuit
.
+5 V VoHa ge Sta bil i ty Ci rcu it
.
Output Current of Photocoupler
.
Output Signal Waveform
.
Overvoltage Prevention Circuit .........•.................
Overheating Prevention Circuit
.
Power Good Signal Generation Circuit I
.
Power Good Signal Generation Circuit II
.
Timing Chart of Power Good Signal ...•....................
Internal Circuit Configuration
.
System Clock Supply Circuit
..
Clock Speed Change Circuit
.
System Reset Circuit
.
Internal Memory Control Circuit
.
Byte/Word Access & 16-8 Bit Data Conversion
.
Data Transmission to 16 Bit Device
.
(Byte Transmission of Even Address)
Data Transmission to 16 Bit Device
(Byte Transmission of Odd Address)
.
Data Transmission to 16 Bit Device
(Word Transmission of Even Address)
.
Data Transmission to 8 Bit Device
(Byte Transmission of Even Address)
.
Data Transmission to 8 Bit Device -- Read Mode
(Byte Transmission of Odd Address)
.
Data Transmission to 8 Bit Device -- Write Mode
(Byte Transmission of Odd Address)
.
Data Transmission to 8 Bit Device -- Read Mode
(Word Transmission of Even Address)
.

Page
2-1
2-2
2-3
2-3
2-4
2-4
2-5
2-6
2-6
2-7
2-7
2-8
2-8
2-9
2-9
2-10
2-10

2-11
2-11
2-12
2-13
2-14
2-15
2-16
2-19
2-24
2-24
2-27
2-31
2-35
2-36
2-36
2-37
2-37
2-38
2-38
2-39

2-3-14
2-3-15
2-3-16
2-3-17
2-3-18
2-3-19
2-3-20
2-3-21
2-3-22
2-3-23
2-3-24
2-3-25
2-3-26
2-3-27
2-3-28
2-3-29
2-3-30
2-4-1
2-4-2
2-4-3
2-4-4
2-4-5
2-4-6
2-4-7
2-4-8
2-4-9
2-4-10
2-4-11
2-4-12
2-4-13
2-4-14
2-4-15
2-4-16
2-4-17
2-4-18
2-5-1
2-5-2
2-5-3
2-5-4
2-5-5
2-5-6
2-5-7
2-5-8
2-5-9
2-5-10

Data Transmission to 8 Bit Device -- Write Mode
(Word Transmission of Even Address)
1/0 Device Access Circuit
m~A Control Circuit I (Setting of Page Register)
Dt~A Control Circuit II (Internal memory -- 1/0, 8bit)
DMA Control Circuit 111 (Internal memory -- 1/0, 8bit)
DMA Control Circuit IV (Internal memory -- 1/0, 16bit)
Ready Signal Control Circuit
Timing bet\'/een Address Signal and Read/Write Signal
Command Delay Signal Control Circuit
Interrupt Control Circuit

.
.
.
.
.
.
.
.
.
.

ROr1 Access Circuit

.

D-RAM Refresh Circuit
RAt,' Parity Check Circuit (Data Write ~lode)
RAt1 Parity Check Clrcuit (Data Read Mode)
Speaker Control Circuit
Keyboard Interface and Other Function Circuit
1/0 Slot Access Signal
16450 Chip Select Circuit

.
.
.
.
.
.
.

1/0 Address Sel ecti on

.

Data Output (Printer Data Register Circuit)
Outpu t Data Rea d Ci rcu it
Printer Control Signal Output Circuit
Printer Control Signal Read Circuit
Printer Status Signal Read Circuit
Interrupt Signal Control Circuit
FDD Control Circuit I (FDD -- CPU)
Interrupt Signal and D~'A Request Signal from FDC
FDD Data Write Circuit
FDD Data Read Circuit

.
.
.
.
.
.
.
.
.
.

VFO Window Circuit

.

FDD Terminator Function

.

FDD Cab le Setting

.

Drive Select and Motor On Signal Supply Circuit
FDD Special Signal Cable

.
.

Hard Disk Drive Signal Cable •••..•.••••.•..•••..•••••..•.

Keyboard
Keyboard
Keyboard
Keyboard

Unit
Data
Data
Data

Block Diagram
Output (AT Mode)
Input (AT t1ode)
Output (XT Mode)

.
.
.
.

2-40
2-41
2-44
2-45
2-46
2-47
2-50
2-51
2-52
2-53
2-55
2-57
2-58
2-59
2-60
2-63
2-64
2-65
2-66
2-67
2-67
2-67
2-68
2-68
2-68
2-70
2-70
2-71
2-72
2-73
2-74
2-74
2-75
2-75
2-76
2-77

2-80
2-81
2-81

Interface Circuit

.

2-82

Keyboard Connector Pin Locations
Stroke Characteristics

.
.

2-82

Typernatic Function

.

Basic Operation of Mode Indicator Display
Special Functions of Mode Indicator Display

.
.

2-83

2-83
2-86
2-86

LIST OF TABlES

Table
2-2-1
2-2-2
2-2-3
2-3-1
2-3-2
2-3-3
2-3-4
2-3-5
2-3-6
2-3-7
2-3-8
2-3-9
2-3-10
2-3-11
2-3-12
2-3-13
2-3-14
2-3-15
2-4-1
2-4-2
2-5-1
2-5-2
2-5-3
2-5-4
2-5-5
2-5-6
2-5-7
2-5-8
2-5-9
2-5-10
2-5-11
2-5-12
2-5-13
2-5-14
2-5-15
2-5-16
2-5-17
2-5-18
2-5-19
2-5-20
2-5-21
2-5-22

Title
Function of Prevention Circuit ............•......•...•...
Specification of DC Max Current ......•..•.....••....•....
Power Down Signal Specification ....••...•.•............••
Memory r·1ap •••••••••••••••••••••••••••••••••••••••••••••••

LED Indications ..•.......•...•...............•....•.....•
NPX Operation Speed .........•...•....•.•.•....•........••
Oscillator Clock Signal Flow
.
Reset Signal Generation Methods .....•..••......•......•..
Function of RAfl1 Chips ...•....•..........................•
Jumper Connector Function ..................•........••...
CPU Data Access Modes .•..................................
Functions of Control Signal on GAATDB ...•...........•....
Explanation of LS612 .•...•..........•....•.........•...••
Wait Cycles ..........•..................................•
Wai t Cycl eSel ecti on ...........................•........•
Condition of The CDLY Signal Output ......•...............
Ava i 1ab 1e ROt,1 Types .•...•............•.......•.....•...•.
A20 Signal Control by GAATRF ..•.........•....•....•......
Jumper J9 Setting ..•......•..•.............•....•....•...
Difference Between 1.2 MB FDD of SD-581L
.
and FD1155C/t1D5501
Interface Control ~1ode ..•...•..••........................
Data COJTlllunication r,1ode (AT t1ode)
..
Data Comnunication t10de (XT Mode)
..
Data Transmission Method and Data Format •......••..••....
Keyboard Connector Pin Function .....•.•...••....•.•.••...
Transmission Intervals •..•......•................•.....•.
Ove rrun Code s .........••..•..................••....•.....
Key Code Make Up ..•...•..•...•...•..•..••..........•....•
Condition for Setting and Releasing Numeric Lock .•....•..
Key Stroke Condition ..............•......................
Extension Left and Right Shift Codes •...•.....••....•...•
Transmission Sequence of Left and Right Codes Key ....•...
Transmitted Code of F16 (break) Key
..
Transmitted Code of F14 (Sys Rq) Key
.
Keyboard Comnands (AT mode)
..
Typemati c Rate/Del ay .•.......••..••.....•....•..•.....•..
Opti on Regi ster for Keyboard .........•••..•.....••..•...•
Key Code t10de Status .......•...•............•............
Key Code t10de on Option Data
.
..
All Key Typemati c Control
Commands to The Host Si de .•...•...•..•••.......•••..•..••
Key Scan Code List .........••...•.................•..•...

Page
2-16
2-17
2-18
2-20
2-22
2-22
2-23
2-25
2-28
2-29
2-32
2-32
2-42
2-48
2-49
2-51
2-54
2-62
2-65
2-69
2-78
2-78
2-79
2-80
2-82
2-84
2-84
2-87
2-88
2-88
2-89
2-89
2-90
2-90
2-91
2-92
2-94
2-95
2-95
2-96
2-96
2-97

PRINCIPLES OF OPERATION

REV.A

2.1 HAIN SYSTEM UNIT COMPONENTS
The following
EPSON pe ÄX.

diagram

sho~JS

a functional

1\11 interface c.ircuit except key board
option slot.

block diagram of the EQUITY III+ /

interface

should

ANT-RM board

6_E~_g_~_~

_ ...I

instaIIed

on a

ANTA board
CPU
80286

DMAC
8237x2

,--_M

be

ANT RM board
connecJ-t_o_r_....__c_on-t".1f1

-

:~

I

RTC

TI~ER

146818

8254-2
KEYBOARD
controller
8042(8742)

INTC
8259x2

+5

+12

keyboard

-5
-12
slots

1

ATRPS unH
Power
supply
unit

AC outlet

SPFG board
WHDC board

Monitor
adapter

Floppy
disk
interface
~

CRT

FDD

FIGURE 2-1-1.

Parallel
Printer
interface

Serial
communication
interface

Hard disk
controller

RS-232C

HDD

,
PRINTER

LOGIC BLOCK DIAGRAM

2-1

REV.B

PRINCIPLES OF OPERATION

2.2 ATRPS POWER SUPPLY UNIT
ATRPS Unit is available in both 115-volt supply and 230-volt supply.
Switch
S1
selects
either
115-volt
supply or 230-v01t supply,
simultaneously switches a fuse.

and

Basic Operation
ATRPS Unit uses the Forward Converter Switching Regulation way.

+

1__Ff'
FIGURE 2-2-1.

2.2.1

BASIC OPERATION CIRCUIT

Primary Oscillation Circuit

The HA16654 controls the MOS-FET.
flows in the liOS-FET.
2.2.1.1

MOS FET

By supplying power to

the HA16654, current

Power supply circuit

Power supply circuit for the HA16654 is explained by the following 2 steps:
1. From power on till the transformer for switching oscillates correctly.
2. After the transformer for switching has oscillated correctly.
1. From POWER ON till the transformer for switching oscillates correctly.
The power supply circuit is shown in Figure 2-2-2.
Zenor Diode D10 and Dll works so as not to supply the HA16654 with a vol tage
until the input voltage V reaches the fixed-level voltage.

2-2

REV .A

PRINCIPLES OF OPERATION

1
V

D10
D11

~
~
Q2

4

7

VI N

+

1

HA16654
6 GND

FIGURE 2-2-2.

SWITCHING OSCILLATION CIRCUIT I

2. After the transformer for switching has oscillated correctly.
No current is present in RIl t DIO t DII t and DI9 because the voltage supplied
from DI2 and RIS is higher than the voltage supplied from Rl1 t DIO t Dl1 and
D19. This causes the increase of efficiency of the ATRPS Unit.

Tl

.....
I

R11

I

'D10
I
I D11
'D19

t
V

.J

7

4

+

HA16654
9

FIGURE 2-2-3.

VIN

6

GND

SWITCHING OSCILLATION CIRCUIT 11

2-3

PRINCIPLES OF OPERATION

2.2.1.2

REV.A

Overcurrent Prevention Circuit of the MOS-FET On-Off Contro! Circuit

The circuit which consists of the transistor Q4 and Q5 works as foliows:

*

If the input voltage is higher than the standard voltage t the Q5 collector
current flows instead of the Q4 collector current.

FET

05

R11

Q1

Vin

R12 e

t

Q2

5

OUT

HA16654

OB
VRef

7

< I - -....-~-.-....----.-~~-,

R2
R15

R17
510

R6
R3
GND

FIGURE 2-2-4.

OVERCURRENT PREVENTION CIRCUIT I

vce O-----.l---.....-...,
5.1K

10 K
GN0

FIGURE 2-2-5.

2-4

0""'"-------'

OVERCURRENT PREVENTION CIRCUIT 11

REV.A

PRINCIPLES OF OPERATION

1)

If the current flowing in the MOS-FET increases, the induced voltage (e2)
increases.

2)

If the voltage which is distributed at R15 and R16 is higher than the
standard voltage at R10 and R11, the Q5 collector current flows.

3)

If positive voltage is applied between base and emitter of
then the collector current flows.

4)

If the voltage at the DB terminal in the HA16654 increases, and the pulse
width is reduced, then the current decreases.

2.2.1.3

transistor Q3,

Inrush Current Prevention Circuit

The inrush prevention circuit protects diode bridge DBI and subsequent
components from being damaged by excessive
current flow in C12 and C13 at
power-up.
R3 limits the current to RC1 when power is applied; when the
switching oscillator operates normally, voltage from Tl activates TRIAC CRl,
permitting current flow to RC1.

T2

eR1

~O

T1

R3

FIGURE 2-2-6.

INRUSH CURRENT PREVENTION CIRCUIT

2-5

REV.B

PRINCIPLES OF OPERATION

(Reference)
Resistor R5 and R6 have two following functions
1)
2)

To be equal the voltage of the resistor R5 in e12 to that of the resistor
R6 in C13.
To use up the electric charge as soon as the switch is turned off.

FIGURE 2-2-7.
2.2.2
2.2.2.1

RS

C12

30K

C13

R6
30K

FUNCTIONS OF RESISTOR RS AND R6

Secondary circuit
-SV and -12V Circuit

When an electromotive force which is in the direction of 1 is produced in the
transformer Tl, tbe series voltage regulator 21 and 22 are supplied with the
power reference through RC2 and L4.
When an electromotive force which is in the direction of 2 was produced at the
transformer Tl, the power reference is supplied from L4.

*
*

R17 is for capacitor discharge.
D14 and D13 is for series voltage regulator protection.

014

)JPC7812H
or HA17812P

+
C23
2SV

100

013

AN 79MOS

,..........-.,
~, 00
~~

- S VO.3A

C37

~l~
47

R 17

lW
200

•

- 12 V0.3 A -1 2 V

GNO

2-6

630V

J; 0.01

06'="C--I~"':'::'-'-4'--""'::"'=-+-"

(2) 8

FIGURE 2-2-8.

-sv

-SV AND -12V SUPPLY CIRCUIT

REV . B

2.2.2.2

PRINCIPLES OF OPERATION

+12V Supply Circuit

a) Basic Circuit
+12V supply circuit is shown in Figure 2-2-9. The function of the +12V supply
circuit is same as the -sv supply circuit and -12V supply circuit.

L 6

T 1

.............---.4.---0

+ 12 V

28

- -.....- - - -.....-----...--4----0
FIGURE 2-2-9.

G ND

+12V SUPPLY CIRCUIT

b) Voltage stabilization circuit
b)-l. Basic Function
When a control signal Is high level, an electric power through the transformer
L5 is decreased. This function control the 12 volts voltage.
T 1

Vo ltage
stabilization
ci rcuit
Control signal

FIGURE 2-2-10.

+12V STABILIZATION CIRCUIT

b)-2. Voltage Stabilization Circuit
The 23 i8 designed so that when the voltage of reference terminal reaches
fixed level, a current flows from cathode to anode.
This function is described in figure 2-2-11.

2-7

KEV.A

PRINCIPLES OF OPERATION

VIN

L5
O>-----.W

VOUT

10

2.2 K

Q3

100
51K

10

cathode
Z3

anode

RV2

470n

GN 0

GND

FIGURE 2-2-11.

VOLTAGE STABILIZATION CIRCUIT 11

If the Vout voltage
rises, the Vref voltage rises and then the cathode
current increases. After that the Q3 collector current increases, and the
Vout voltage decreases ---- Function 1
If the Vout voltage decrease, the Vref voltage decreases and
the cathode
current decreases. After that the Q3 collector current decreases and the Vout
voltage rises -_._.- Function 2

CATHOOE
CURRENT

[A]

REFERENCE
VOLTAGE

FIGURE 2-2-12.

2-8

[V]

CHARACTERIZE OF Z3

PRINCIPLES OF OPERATION

REV.A

A voltage stabilization circuit repeats the above functions and stabilizes the
12V line.
If a stable Vout voltage is lo\/er than +12 volts, let down a RV2 resistor
value.
If let down a resistor value, the Vref voltage decreases and the
cathode current decreases. After that, the Q3 collector current decreases and
the Vout voltage rises.
In the same way, if a stable Vout voltage is higher than +12 volts, let up the
resistor value of volume RV2.

c) Fan Revolution Speed Control Circuit
12V - - - - - . . . - - - - ,

When temperature increases,

~ value of resistance decreases.
TH1

FAN

GN D- - - - -....-------<:)------'

FIGURE 2-2-130

FAN REVOLUTION SPEED CONTROL CIRCUIT

d) Overcurrent Prevention Circuit
If a current is supplied more than a fixed current to +12V circuit,
operational amplifier outputs high level signal and a transistor is turned on.
Next, the DB terminal voltage rises, and it causes the voltage of the output
terminal of the HA16654 not to output a pulse.
When the overcurrent
prevention comes to such a condition, SCR of PC1 keeps working. To return to
the former condition, turn ON the power switch, then OFF after thirty seconds.

current
R22

R38

+
R26

FIGURE 2-2-140

OVERCURRENT PREVENTION CIRCUIT

2-9

PRINCIPLES OF OPERATION

2.2.2.3

REV.B

+sV Supply Circuit

a) Basic Circuit
The +sV circuit is shown in Figure 2-2-15.
The function of the +5 volts circuit is same as -SV circuit and -12V circuit.

L7

+

+

'--.. . . .- --.. . . .-------------.----0

Tl

FIGURE 2-2-15.

G ND

+5V SUPPLY CIRCUIT

b) Voltage Stability Circuit
\------"4....----------0

+5

\ - - - - + - - - - - . - - - - - ( J G ND
5

OUT
HAI6654
EI

If

e

RVl
2.2 K

R7

Re
GND

Z4

R32

910

FIGURE 2-2-16.

2-10

+5V VOLTAGE STABILITY CIRCUIT

HEV.A

PRINCIPLES OF OPERATION

Characteristics of Photo Coupler PC2
In the photo coupler, the output current (IC)
current flowing in the LED (IF).

increases in

proportion to the

If

FIGURE 2-2-17.

OUTPUT CURRENT OF PHOTOCOUPLER

Characteristics of HA16654
The 8th-pin error input terminal
HA16654 have the following relation.

*

and

the

5th-pin output terminal of the

If the voltage of ERROR INPUT terminal rise, the pulse width of the
terminal is reduced.

output

ERROR INPUT

DEAD BAN 0 --+-+-~~--t-~-""'~""'--

I
eT11

11

11

11

OUTPUT _ .......

FIGURE 2-2-18.

"-'---~

OUTPUT SIGNAL WAVEFORM

Characteristics of 24
When the reference vo1tage of the IC24 reaches a fixed voltage, current flows
from cathode to anode shown in Figure 2-2-17.

2-11

PRINCIPLES OF OPERATION

HEV.A

Description of circuit
The voltage stabilization circuit of the +5V supply circuit utilizes above
three elements.
The vicinity of fixed voltage is applied to the reference terminal. As the
voltage of +5V line increases, current flows in Z4 increases, and then the
8th-pin terminal voltage of the HA16654 increases.
Then a pulse width of the
output terminal is reduced and a output voltage of the secondary oscillation
circuit decreases.
If the voltage of +5V line decrease, the voltage of the error input terminal
of the HA16654 decreases and a pulse width of the output terminal widen.
Therefore the output voltage of the secondary oscillation circuit increases.
If the voltage of the stable +5 volts line is lower than +5 volts, enlarge the
resistor value of volume RVl. Then the terminal voltage of R32 decreases and
the current flowing in Z4 decreases. The voltage of the ERROR INPUT terminal
of the HA16654 decreases and it causes the pulse width of the output terminal
to widen and the +5V line voltage to increase.
When a voltage of the stable +5 volts line is higher than +5 volts, let dO\m
the resistor value of the volumn RVI because of the same reason as above.

*

The base resistor of the photo coupler is for gaining the switching speed.

c) Overcurrent Prevention Circuit
Function of the overcurrent prevention circuit is same as +12V supply circuit.

d) Overvoltage Prevention Circuit

+5

Vline

R28

08

FIGURE 2-2-19.

2-12

OVERVOLTAGE PREVENTION CIRCUIT

PRINCIPLES OF OPERATION

RKV.A

2.2.2.4 Overheating Prevention Circuit
When the temperature rises to a fixed level, switch TH2 is turned on.
With
switch TH2 turned on switch TH2, a comparator generates a high level signal
and it results in no pulse output of the output terminal of the HA166654.

+5V

~""---GND

82

7.5K

I

TH2

GND

15Kfi

-12V

FIGURE 2-2-20.

2.2.2.5

OVERHEATING PREVENTION CIRCUIT

Power Good Signal Generation Circuit

The pOvler good signal generation circuit monitors the +5V line, +12V line ,12V line and -5V line of the secondary oscillation circuit.
If there is an abnormality (low voltage) in these lines, the power good signal
changes to low level signal.
Also, it monitors a primary voltage proportion circuit.
If there is an
abnormality (low voltage) in the input AC adapter, power good signal changes
to low level signal.
The primary voltage proportion circuit is equipped with
CR circuit controls timing of the power good signal.

the CR

circuit.

The

2-13

PRINCIPLES OF OPERATION

REV.A

+,~
R38

T1

+

lOOK
017

,-------,
R34

I

I

R36

27

R35

26
I

L

FIGURE 2-2-21.

,

I

...J

POWER GOOD SIGNAL GENERATION CIRCUIT I
(Primary voltage proportion circuit)

2-14

REV.B

PRINCIPLES OF OPERATION

-12V
line

+5
line

+12

R38
A~-"'"

+12
line

R39

R40

R 41

R 42

09

010

FIGURE 2-2-22.

POWER GOOD SIGNAL GENERATION CIRCUIT 11

2-15

REV.A

PRINCIPLES OF OPERATION

more
(When ACl00V)

20 msec

I Osec.more

AC

I

1

I

I
I

I . .,
I I

OC

I -~
I

I

P.G.

I
I

I

I

I

I

I

more

Power OFF

FIGURE 2-2-23.

TABLE 2-2-1.

TIMING CHART OF POWER GOOD SIGNAL

FUNCTION OF PREVENTION CIRCUIT
Detecting voltage or
Detecting current

SV

5.5 volts - 7.0 volts

+12V
-12V
- SV

Overcurrent + SV
prevention +12V
-12V
circuit
- SV

2-16

'\ 1msec

I

Power ON

+

\

I
I

I
I
I

Overvoltage
detector

,

3sA
16A

3A
3A

Condition after
detecting
Cut all output off.
To recuperate
condition, turn off
AC, then on after
30 seconds.
Cut all output off.
To recuperate
condition, turn off
AC, then on after 30
seconds.

REV.A

PRINCIPLES OF OPERATION

TABLE 2-2-2 SPECIFICATION OF DC MAX CURRENT
+5V
Output current
Max (Min)

+12V

-12V

4.8A *
(OA)
* 7A within
10 seconds
after power
on.

20A
(2.5A)

O.3A
(OA)

-5V
O.3A
(OA)

Current
consurnption
ANTA BOARD

1.23A
(effective
value)

OA

ANT-RM BOAHD

O.50A
(effective
value)

OA

SPFG BOARD

O.54A
(effective
value)

OA

WHDC BOARD

O.53A
(effective
value)

OA

HRS-MO BOARD

O.27A
(effective
value)

OA

MRS-CR BOARD

O.50A
(effective
value)

FD1l55C

O.46A

O.21A
O.39A

(TYP)
(po~ler

on)

MD5501

o.1lA

HMD-720

O.2A (TYP)

2.0A (power on)
O.58A (TYP)

D5146 (40M HDD)

l.OA (MAX)

3.0A (power on)
2.0A (seek)
1.2A ( read/write)

(TYP)

o.24A (TYP)
1.66A (peak)

2-17

PRINCIPLES OF OPERATION

TAßLE 2-2-3.

REV .A

POWER DOWN SIGNAL SPECIFICATION
Power down signal
11\

,I,

11SV MODE

/1\

7SV

...

75 80

,

AC

Power down signal
I

"

230V MODE

2-18

lSOV

1\

...

150 160

,

AC

I

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\Q

I-'

ARTA MAHl CONTROL BOARD OP ERATIONS

<

~

CPU

FIGURE 2-3-1.

GAATDB

n

GAATCK

ARTA BOARD

GAATJO

I

II

'

I

GAATM2

GAATMI

I

I

I

I

1NTERlIAL C1RCU1T CONFIGURATION

,

!
I

GAATRF

><

equivalent

0'

MB81256

equivalent

0'

MB81256

>

0'

eQuivalenl

jJPD4164

0'

eCluivaient

~PD4164

ART-RM BOARD

This section describes the principles of the ANTA board operation by using the diagrams
which shows an internal circuit of the EQUITY 111+/ EPSON PC AX computer system.
There
are several blocks in the diagram for each circuit operations.

2 .3

I

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CI)

~

~

~

I"d

~

.>~

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64 KB ROM on system board
Maximum memory 15 MB
64 KB reserved on system
64 KB ROM on system board

100000 to FDFFFF

FEOOOO to FEFFFF

FFOOOO to FFFFFF

to
to
to
to

OFOOOO to üFFFFF

000000
OAOOOO
OCOOOO
OEOOOO

640 KB system memory
128 KB video RAM
128 KB r/o EXPANSION ROM
64 KB reserved on system

NAME

FUNCnOB
System memory
Reserved for graphics display buffer.
Reserved for ROM on 1/0 adapters.
Duplicated code assignment at address
FEOOOO.
Duplicated code assignment at address
FFOOOO.
1/0 channel memory - memory expansion
option.
Duplicated code assignment at address
OEOOOO.
Duplicated code assignment at address
OFOOOO.

MEMORY KAP

09FFFF
OBFFFF
ODFFFF
OEFFFF

ADDRESS

TABLE 2-3-1.

Table 2-3-1 shows the memory map for the EQUITY lll+/EPSON pe AX computer system.

~

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~

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System Clock Generation Circuit

CPU clock (12 MHz, 16MHz, 20MHz)
NPX c10ck (mfilz)
DMA clock (3MHz, 4~frlz, 5~rnz)
Timer counter c10ck (1.19MHz)
Keyboard controller clock (6~rnz)
OSC clock (for option slot: 14.31818Mllz)
SCLK signal (System clock for option slot: 6}filz, 8MHz, 10}lHz)

LED Indications

There are two LEDs on the clock speed change circuit.

2.3.1.2

These LEDs indicate the CPU

The EQUITY III+/EPSON PC AX has three kinds of CPU operation speeds. One is 6MHz, the
same as IBM AT, 8MHz is the same as IBM NEW AT, and 1Ot1Hz is faster operation speed
than IBM AT or NEW AT.
We can select these CPU operation speeds by slide switch (SW2) . .Also, the GAATCK
includes clock speed select circuit.

Select CPU Operation Speed

Clock speed -------- Input or output clock signal speed
Operation speed ---- Internal clock speed

Please be careful with difference between 'clock speed' and 'operation speed'.
The CPU and the NPX divide an input clock signal by one's internal circuit. (NPX
does not divide the input clock signal in 8}filz mode. Please refer to Section 22-3.)
This means there are some cases that the input clock speed is not
identical with the operation speed. This manual defines these words as below.

< REKARK >

1)
2)
3)
4)
5)
6)
7)

All clock signals are supplied from the gate array (GAATCK) except the RTC (146818)
clock signal. The GAATCK generates the following clocks.

2.3.1.1

2.3.1

~

~

~

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o

~

~
~
~

Jod

>

~.

I

l'.)

l'.)
l'.)

Select NPX (80287) Operation Speed

(6NHz, SMHz, 1OHHz)

( 1000mz)

( SHHz)

(~nlz)

(CPU OPERATION SPEED)
4HHz
5.3HHz
6. lNHz
8MHz

OPERATION SPEED

NPX OPERATION SPEED

NPX divides the CPU clock into three in the CPU clock mode.
In CPU CLOCK MODE, the NPX divides the CPU clock into three. But 8}1Hz mode, the
NPX does not divide SMHz clock.

< REKARK >

A selection is performed by setting of jumper connector Jl and J2 on the ANTA board
(Main circuit board). Jumper connector setting of Jl and J2 are listed in CHAPTER 7.

2) 8MHz MODE

1) CPU CLOCK MODE

NPX OPERATION SPEED MODES

TADLE 2-3-3.

The EQUITY III+i EPSON PC AX has two kinds of NPX operation speed modes.

2.3.1.3

Jumper connector J1 is inhibitted to change setting. (Always connect betvJeen A to C )

< REKARK >

6HHz
SHHz
10MHz

RED
ORANGE
GREEN

LED IRDICATIONS

CPD OPERATION SPEED

TADLE 2-3-2.

LED INDICATIONS

operation speed.

.>~

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t"'J

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o

loz:I

o

~

~

""d

~
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Oscillator

20MHz
14 .31818MHz

48lvlliz

OSC CLOCK SPEED

The GAATCK inputs these signals

1/3
1/4
1/6
1/8
1/1
1/1
1/12

GAATCK OU1PUTS;

16MHz
12MHz
8MHz
6MHz
20HHz
14.31818MHz
1.19l-1Hz

'l'BE CLOCK IN'l'O;

GAATCK DIVIDE

KEYBOARD CONTROLLER
CPU
OPTION SLOT
TIMER COUNTER

NPX

CPU
CPU

CONNECT 'l'O;
(MAJOR CHIP)

TABLE 2-3-4. OSCILLA'l'OR CLOCK SIGNAL FLOW

There are three oscillators on the ANTA board.
and produces the following clock signals.

2.3.1.4

Z

o

t-I

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~
to:j

ol'Zj

~
cn

~
~
~

~

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~.

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FIGURE 2-3-2.

SYSTEM CWCK SllPPLY CIRCUIT

FIGURE 2-3-3.

J1

er

~

Green

CN3

1SOn

ft

~

GAATCK

CSPD'

CSPD 0

CLOCK SPEED CBAI«;E CIRCUIT

Red

1S01\

L~~~~L~:I-----i-t---'1

r1;--;;-ilO:4-----t-+-......::.~

+S

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!2:

~

~

~

~

~

cn

~
o

~

~

"tl

\Jl

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2.3.2

Reset switch is pushed.
Reset switch is pushed.

4) Shut down cycle is executed.

The software reset command (RC goes active) resets only the CPU.
When gate array GAATCK receives the RC signal, it generates the RSCPU signal.

< REMARK >

INTERNAL CIRCUIT RESET SIGNAL
OPTION SLOT REST SIGNAL

1) PWGD signal goes low.
2) Reset switch is pushed.

CPU RESET SIGNAL

3) Re signal goes active.(Software reset)

METHODS

RESET SIGNAL

TABLE 2-3-5. RESET SIGNAL GENERATION METHODS

There are three kinds of reset signal on the EQUITY III+/EPSON PC AX computer system
below. The gate array GAATCK generates these signals.
1) CPU RESET SIGNAL
2) INTERNAL CIRCUIT RESET SIGNAL
3) OPTION SLOT RESET SIGNAL
To generate the above reset signals> there are the following methods.

System Reset Signal Generator Circuit

i

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otod

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o

~

~
~
~

tod

t:P

<:

trJ

;:0

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2.3.2.1

4) Shut down cycle
A Shut down cycle is a kind of CPU execution cycle. When the CPU executes
this cycle, it means that the CPU detects a fatal software error with which
the CPU can not continue its current operation. CPU indicates this cycle with
SO, S1, M/lO, COD/lNTA signals.
The shut down circui t of the GAATCK is searching for the shut down cycle
whenever power is on and if it detects the shut down cycle, it generates an
active RSCPU signal.

3) RC signal
A RC signal is sent from P20 pin of the keyboard controller (8042) which can
be controlled by software.
A RSCPU signal becomes active by the active RC signal.
(Refer to the remark in section 2-4.)

2) Reset switch (SW3)
When the reset switch SW3 is pushed, the GAATCK generates a RSN signal, a
RSDN signal and a RSCPU signal. This computer system can disable the reset
switch signal by locking the key cylinder on the front panel. When the key
cylinder is locked, the key cylinder switch becomes on.
When the key
cylinder switch is on, the GAATCK does not output any reset signals.

1) PWGD signal
The power supply unit (ATRPS unit) gene rates a signal. When the power supply
unit has some problems, the PWGD signal becomes low. Normally, this signal
keeps high level.
When the gate array GAATCK receives the PWGD signal, it generates a RSN
signal, a RSDN signal and a RSCPU signal.

System Reset Circuit

&.

~

iZl

o

~H

~
tzj

"":l

o

~

~

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N

L+j RESET

RESET

!ill!:!

I-

GAATDB

GAATCB

GAATAB

,

i

BltO. 1. 2 Ind
Ire el..red

i

31

SYSTEM RESET CIRCUIT

PRSI-

GAATIO

=

RSTNi

J;.R 5T0I---

GAATRF

~RST_

r

,------:

I

---..../K.y Cyliod. r ,.......

~:et----d ~Sw1tch

:rol---rol:l;;!.....- Ol

CN3~--·"'-"

flJ5

FIGDRE 2-3-4.

P201---

Illml-

8042

~II

SWON

~

~=~

10 the fo11owl"9 eondltlon.
thls slgnel _ . leth••
(1) PIIGO sl9O.l _ . 10w
(2) ReHt SW ls pushed
(3) RC .19011 _ s leth.
(4) Shut down eycl.

_.r

llheo the res.t SW 1$
PIlshed. thls .19011
_.low.
10 cu. of k.ylockl09.
thl. s19011 ls 11.lys
h19h
the
res.t SII ls PUShed.

SW3

~Hls~

+5·5

(j

i

GAATM2

GAATlo41

_

DMA2
8237A-5

RESET

DMAl
8237A-5

L..,..jRESET

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Internal Memory Control Circuit

16
4
2
2

RAH Chip addresses

1bit
4bit
1bit
1bit

256K-word
64K-word
256K-word
64 K-vlO rd

by
by
by
by

Q'TY
System
System
Parity
Pari ty

memory (512KB)
memory (128KB)
check
check

FUNCTION

TABLE 2-3-6. FUNCTION OF RAH CHIPS

board, there are three kinds of RAM chips. (Refer to Table 2-3-6)

RAH CHIP TYPE

ANT-P~

000000

07FFFF

080000

09FFFF

RAH CHIP ADDRESSES OF SYSTEM MEMORY

-------------------------------------------

256K-word by 1bit RAM chips

64K-word by 4bit RAM chips

------------------------------------------

The system memory RAM chips are located in the following address.

2.3.3.2.

On the

RAH Chip type

All system memory
chips are integrated on the ANT-RM board.
If the EQUITY
III+/EPSON pe AX computer system has problem that system does not boot up, you
should better to replace the ANT-RM board first because you can determine if the
problem is caused by RAM chips or the other circuit.

2.3.3.1

2.3.3

.5>

Z

~

~

t:z:l

~

~

o

~
tI:l

~
~
~

I'd

ID

t-,)

I

t-,)

Jumper Connector Function

AVAILABLE AREA

B-C

B-C

2.3.3.4

NONE

(

OKB)

03FFFF TO 000000 (256KB)

07FFFF TO 000000 (512KB)

09FFFF TO 000000 (640KB)

DESCRIP TION

1

>

2

>

A20 signal.

SAO signal on the GAATAB is not used by memory control circuit in RAM read/
write mode. But it will used in the D-RAM refresh mode.

< REKARK

The GAATRF controls

< REKARK

1) ADDRESS SIGNAL
The CPU outputs address signal (AO to A23).
Next, the GAATM2 (Memory
control gate array 2 ) receives from Al signal to A18 signal to make RM1
chip address signal. Also, the GAATM1 (Memory control gate array 1 )
receives from A17 signal to A23 signal and AO signal to make a RAS signal,
a CAS signal and etc.

Operations of Memory Contro! Circuit

AV AILABLE AREA

AVAILABLE AREA

A-C

B-C

B-C

AV AILABLE AREA

A-C

A-C

A-C

J2

J1

J3

TABLE 2-3-7. JUMPER CONNEC'IDR FUNCTION

We can disable the system memory by setting of the jumper connectors J1,J2 and J3.

2.3.3.3

Z

o

H

~

t:o:I

~

l'Zj

r.n
o

~

~

~
~

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5) D-RAM REFRESH CONTROL ClRCUlT
Refer to Section 2.3.11.

4) RAM CHIP CONTROL SIGNALS
All D-PJlli control signals are sent from GMTM2.

3) READ/WRITE CONTROL SIGNAL
CPU outputs SO, SI, M/lO signals. GAATCK receives these signals and makes
MEMRN and MEMWN signals. GAATM2 receives MEMR and MEMW signals to control
RAS and CAS signals. Also, GAATM2 recei ves XMWN (MEMWN) signal which has
flowed through GAATCB to make WE signal of the RAM chips. GAATMI receives
XMRN (MEMRN) signal which has flowed through GMTCB to make RAS, CAS
signals.

2) DATA SIGNAL
GAATDB controls data bus by its internal data bus buffer.

>

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t:r:l

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cn

~

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GAATCK

FIGURE 2-3-5.

GAATAB

(

BUS

C~

TO
FRO"" RA""
RA"" CHIP
CHIP

INTERNAL MEMORY COBTROL CIRCUIT

OA TA

GAATRF

Used for address sel.ct1ng

:~d ~8' RA1. CAH. CAL

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~
~

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7)

EVEN
ODD
EVEN
ODD

EVEN
ODD
EVEN
ODn
ADDRESS
ADDRESS
ADDRESS
ADDRESS

ADDRESS
ADDRESS
ADDRESS
ADDRESS
8-BIT
8-BIT
8-BIT
8-BIT

16-BIT
16-BIT
16-BIT
16-BIT
DEVICE
DEVICE
DEVICE
DEVICE

DEVICE
DEVICE
DEVICE
DEVICE
Figure 2-3-10
Figure 2-3-11
16-8 BIT DATA CONVERSION
Figure 2-3-12

Figure 2-3-7
Figure 2-3-8
Figure 2-3-9

REFERENCE

GHDHN, GMDLN, DHD
GDHN, GDLN, DD
CBA, SBA

D245, G245

SIGNAL NAME

Controls data bus conversion (High byte --> low byte)
(Low byte --> High byte)
Controls Memory data (Disabling, Direction control)
Controls CPU data (Disabling, Direction control)
Controls data latching (With 16-8 bit data conversion)

DESCRIP TION

TABLE 2-3-9. FUNCTIONS OF CONTROL SIGNAL ON GAA'IDB.

The GAATDB includes five 8-bit buffers. This buffer needs a gate control signal and
a direction control signal. The following table describes gate control signals and
direction signals.

2.3.4.1

8)

OF
OF
OF
OF

OF
OF
OF
OF

DATA TRANSMISSION 1'0;

Data Bus Control Signal on GAA'IDB

TRANSHISSION
TRANSMISSION
TRANSMISSION
TRANSMISSION

BYTE
BYTE
WORD
WORD

5)

6)

TRANSHISSION
TRANSMISSION
TRANSMISSION
TRANSMISSION

BYTE
BYTE
WORD
WORD

MODE

TABLE 2-3-8. CPU DATA ACCESS MODES

The CPU has the following data access modes.
16-8 bit data conversion means word transmission of even address (8 bit device).

Byte/Word Access & 16-8 Bit Data Conversion

1)
2)
3)
4)

ID.

2.3.4

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Circuit Operation of Data Conversion

COFF SIGNAL
The GAATRF outputs this signal. The GA.ATCK recei ves this signal to make two
8-bit device read/write signals.
Also, the GAATDB receives this signal to
catch a low byte data by the internal buffer LS646.
* Hhile the GAATCK req'.ives an active COFF signal, a read/write signal of the
Q~TCK will be inactive.

7) WORD TR~\jSM1SSION OF EVCN ADDRESS (8-B1T DEV1CE) : 16-8 bit data conversion
Figure 2-3-13 and Figure 2-3-14 show the GAATDB internal circuit operations.
(Read mode --- Figure 2-3-13, Hrite mode --- Figure 2-3-14).
In this section, there are two important signals. One is a COFF signal, the
other is a XAO signal.

6) BllE TR~NSHISSION OF ODD ADDRESS (8-BIT DFYICE)
Figure 2-3-11 and Figure 2-3-12 show the GA~TDB internal c rcuit operations.
(Read mode --- Figure 2-3-11, Write mode --- Figure 2-3-12

5) BYTE TR;\;\JSMISSION OF EVEN ADDRESS (8-BIT DEVICE)
Figure 2-3-10 shows the GAATIlB internal circui t operat,ion.

The CPU operatrs as folIows. First, the CPU executes the BYTE TRANSHISSION OF
ODD ADDRESS (16-BIT DEVICE). Next, the CPU executes the BYTE TRANS~lISSION OF
EVEN ADDRESS (16-BIT DEVICE). When a software programrner instructs t,he CPU to
do the WORD 'fRANSMISSION OF ODD ADDRESS (16-BIT DEVICE), the CPU executes the
instruction 'vi th the above steps automatically.

4) WORD TRANSHISSION OF ODD ADDRESS (16-BIT DEVICE)

3) WORD TRAT\fSHISSION OF EVEN ADDRESS (1(";-BIT DEVICE)
Figure 2-3-9 shows the GMTDB internal circui t opera.ti on.

2) BYTE TRA1\JSMISSION OF ODD ADDRESS (1 G-BIT DEVICE)
Figure 2-3-8 shows the GAATDB internal circuit operation.

1) BYTE TRANSMISSION OF EVEN ADDRESS (16-BIT DEVICE)
Figure 2-3-7 shows the GAATDB internal circuit operation.

2.3.4.2

i

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GAJ\TI~F

The GAL\TRF outputs this signal.
In the 16-8 bit data conversion mode, the
does not use a CPU AO signal to make a LSAO signal. (This means, the
internal circuit of the GAATRF generates the LSAO signal but not in the
conversion mode, the GAL\TRF uses the CPU AO signal to make LSAO signal.) The
internal buffer LS646 of the GAATDB inputs this signal (XAO signal) to send the
catched data to t,he CPU.
Also, the 8-bit device receive this signal to
determine address. 'Ifuile a 16-8 bit data conversion, this signal changes
status as low to high.

LSAO SIGNAL (XAO SIGNAL)

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024S
024s.

-

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BBM-tt
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FIGURE 2-3-6.

lAO

~

GMDHN
GMDlN

G245

D245

GAATDB

BHE

:;.E..
Si~
'''~i:.1l.,l
.....

GAATCB

Ils i 9n.ls

-

rrr-

-

D245 }liiise
oro
tputsignals
by decordlng
G24SN XAll.nd XIIllE slgn.ls

,J

be_n 16 .nd 8bit J
clrcult

~

~ C:~''''10n

IAO
XlHE

AO

lSAO

I>AAHIF

GAATCK ree:oiv.s an aeUv. ClFF signal.

.1

GAATMI

GAATIO

output by
decoding OTR
l5AO .nd IM
51'7'815.

signals are,

i~DH~h
GDlN

A

~

BYTE/WORD ACCESS &
16-8 BIT DATA CONVKRSION

....

DU

GAATMZ

r--- DMD

the road/write signal of GAATCK goss inecUve.

[~

r-- CDFF ...

~

..--

~~"';~1~

CB'"
SBA t - -

GDlN
DD

Equl•• l.nt DMD
Inte.....1
Circult GDHN

~

GAATAB

tt'"

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---------- 8 bit D.t. bus

k~
2

--

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TD OPTION SLOT

S4Ul0'.

&
111111

. OU_

IHE

iiüllü

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J},I

TC CPU
.

CPU

C~~:ill

signals beeane disabled.

MENR. MEMW. OR .nd IOW
~"'~'
"~""1

_r"O,...._ ..
GAATCK

H

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tzi

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l

1401

FIGURE 2-3-7.

A

i:

DIA

4
5

><

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f--------

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u ugu.fl

S01", SOO

l

~~gr~ I :~~)

0140

0245
G245N H

GOlN l
C8A
S8A lAD)

MAD

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DATA TRANSMISSION 1'0 16 BIT DEVICE
(BYTE TRANSMISSION OF EVEN ADDRESS)

OPTION SlOT

B

2

BkA

.

~~~~~~~~

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FIGURE 2-3-8.

'"'08

2

14015

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t ••• REAO

lOIA){ H ... IIRIIE

H

G,",OlN (AO) ,H

0'"'0

G,",OHN I 8HE I l

0245
l
G245N l

SBA (AO)

GOlN l,H
GOHN
CU I COFF)
l
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DATA TRANAMISSION 1'0 16 BIT DEVICE
(BYTE TRANSMISSION OF ODD ADDRESS)

OPTION SlOT

5015"" S08

1=================
,

4
5

A

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B

2

Bk

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01- 00

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CPU

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FIGDRE 2-3-9.

C

l

H WRIT[

l READ

DMD'

1! - - - - - - - - G M D l N

DATA TRANSMISSION TO 16 BIT DEVICE
(WORD TRANSMISSION OF EVEN ADDRESS)

(BHE I l
(1001 l

"""""ry thls slgno' goes hIgh.

'Only .hen reedtng t:-'" internal

GUSN H

DUS

dote
When the SM goes hIgh, th.
doto latched by th. eR" s Igno'
Is output.

buffer. At the

I:' '~~~h~:~'

OS 0

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Operotes

SBIo (1001

1-------- GMDHN

I

507'" 500

OPTION SlOr

SOlS"" SOl

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DIR

B'5

2

Bk I.

,

l@j~-~~~~~~

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5

DIR

C

Io~B

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DIR

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FIGDRE 2-3-10.

a

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tB

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11 blt

507'" 500

DMD

DUS

GZASN H

I--------------~=gr~I:~~' r

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CU

READ
WRlrE

DATA TRANSMISSION TO 8 BIT DEVICE
(BYTE TRANSMISSION OF EVEN ADDRESS)

C

DIR

5

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k
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8

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GDHN H
GDlN l

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FIGURE 2-3-11.

DIA

r;

A , B

S
2

At B

DIA

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5

A , B

2

s

At B

-

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Shit DEVlC[

OMO

1------- g~gr~ : :~il ~

I

0245
H
G24SN l

DATA TRANSMISSION TO 8 BIT DEVICE
READ MODE
(BYTE TRANSMISSION OF OnD ADDRESS)

Dlet

I I

GDHN l
H

(DIAll

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00

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rA I,~~~~~~~~~~~

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-

5

5

FIGURE 2-3-12.

.!UL.

l:

A , 8

S
2

dB

~

L!!.!!....

r--.'

OMO
GMDHN (8HEll
GMOlN (AOI H

Only.wh@n refldtng the tnternef
h'9h
1••• 1
......ryy. thts S'9•• 1

DUS
l
GUSN l

00
(DIAIH
GOHN l
GOlN H
CBA
l
58A (AOI H

DATA TRANSMISSION TO 8 BIT DEVICE
WRITE MODE
(BYTE TRANSMISSION OF ODD ADDRESS)

L..-Ji

DIA

5

~ B~A

,..-,.-

L..,/8IA

A

A , B

,I

01

B

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....--.--

-

,

OIS~

11
"'-../
Al~2'5Ai
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i C i i ~S6':
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8
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8
8

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FIGURE 2-3-13.

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01.
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GUS" H

OU5

Gili~~;-GAATRF-cl,anges

t"';J

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1

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l

tiMt lJ(yrCE

,

(Vft

DU!
GUSH H

GNOtfN (eH!' l
DNO
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l

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LSAO signal from 1... La high
level.

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7/

Gfltl! IlrUY GAATRF output
lh. SI9"1'I1. ll)WHht,h_'ow
f,..,. th. WH bMltft81.

DATA TRANSMISSION TO 8 BIT DEVICE
(WORD TRANSMISSION OF EVEN ADDRESS)
16-8 BIT DATA CONVERSION
- - READ MODE

J

Bhtt O(V'C(

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=======:::""

1,~

00

----GOHN

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CPU

I These signal are changed by cha~i~
the LSAO status from 1"", level to
high level.

r

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~g~: t

"Dill

The htcMd date fs
I
otItput on thts d.te 001.

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The 8 bit device reads Data 1.

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DATA TRANSMISSION TO 8 BIT DEVICE
(WORD TRANSMISSION OF EVEN ADDRESS)
16-8 BIT DATA CONVERSION
- - WRITE MODE

0'.l:

5

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CPU

The 8 bit device reads Data 2.

FIGURE 2-3-14.

OMO
GMDHN ll
GMOlN l

OUS
G'''5N H

C..
se...

GONN l
GOlN l

OO

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'I I'

015- 01

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"hit DUltl

,

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DMO
GMb ... "

blU

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GUSN l

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GDlN H
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1/0 Device Access Circuit

DO

(

015

GAATCK

l,SA.\...

FIGURE 2-3-15.

GAATOB

DOWN

110''''

IO~A

~Io-

0'"

GAAICB

DIA}

GAATAB

deV1C'

.,

..

I[

CSDIII

cso..c

"'OS

T. 8blt 1/0 devlce

CSUN

IlCSN

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CS"'''

eS'lII

CI.t.

GAATIO

~~

8254-2

~

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825"-2

L-'

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4237A-5

.. .... ~

I ,

1/0 DEV1CE ACCESS C1RCUIT

110

I LSAO

GAATAF

rff
AS

A/Vi

146818

NPS2

NP51

NIIWrl

~

eMD!

eMOO

80287

POWER

~r-SUPPLY
SIGNAl.

The GAATrO makes r/o device chip select signals by decording address signal.
An ALS245 is used in the data transmission between the CPU and the r/o device.

10 GAATRF

2.3.5

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!'lAO thru !'lA3
MAO thru HO 11

-es

-STROBE

R/-w

RSO thru RS3

DO thru Dll

PIN NA!'lE

1/0 connections to data and control bus used for reading from and hTi ting
to the map register seleeted by RSO-RS3 \vhen -es i s 10w. ~lode eontrolled
by R/-W.
Register seleet inputs for 1/0 operations.
Read 01' \vri te eontrol used in 1/0 operations to seleet the eondi tion of
the data bus. \~hen high, the data bus outputs are active for reading the
register. w'hen lOH, the data bus is used to wri te into the register.
Strobe input used to enter data into the selected map regist.er during 1/0
operations.
Chip seleet input. A loh' input level selects the memory mapper (assuming
more than on used) for an 1/0 operation.
!'lap address inputs to select one of 16 map registers h'hen in map mode.
!'1ap outputs.
Present. the map register cont.ents tu the system memeory
address bus in the map mode.
In tbe pass mode, these outputs provide the map address data on NOS-HOll
and low levels on 0'100-0'107.
!'lap enable for the map outputs.
A low level allows the outputs to be
aetive while a high input level puts the outputs at high impedanee.

HJ\fCTIONAL DESCR1PTION

TABLE 2-3-10. EXPLANATION OF LS612

The GAATIO ineludes a page register. The funetion of the page register is identieal
with T1L IC LS612. Table 2-3-10 deseribes about the function of LS612.

Page Register Setting Circuit

There are two DM controller on the main board (ANTA BOARD). A DMA1 (Ioeation: 2F)
eontrols an 8-bit data transmission. A DMA2 (loeation: 2E) eontrols a 16-bit data
transmission. It requires a page register to output address signal from A16 to A23.
The page register is ineluded in the GAATIO.
This seetion deseribes the following items.
1) Page register setting eireuit
2) 8-bit DMA (Internal memory -- 1/0)
3) 8-bit DMA (Internal memory -- Internal memory)
4) 16-bit D}1A (Internal memory -- 1/0)

DMA Contral Circuit

2.3.6.1

2.3.6

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8-bit DMA (Interna! Memory -

1/0)

8-bit DMA (Interna! Memory -

Interna! Memory)

16-bit DMA (Interna! Memory -

1/0)

Figure 2-3-19 shows the 16-bit DMA (Internal memory -- 1/0) operation.
A DMA2 controls the 16-bit DMA. In this mode, the GAATRF outputs AO signal and
BHE signal. Both AO and BHE signal statuses are always low.
The DMA2' s AO signal is not connected to address bus bit O.
Because the AO
signal is output from the GAATRF.

2.3.6.4

Figure 2-3-18 shows the 8-bit DMA (Internal memory -- Internal memory) operation.
First, the DMA controller stores memory data. Next, the DMA cont ro ller changes
address signal and writes the stored data to the memory.

2.3.6.3

Figure 2-3-17 shows the 8-bit DMA (Internal memory -- 1/0 ) operation.
In the DMA mode, a MEMRN, a MEMWN, a IORN and an IOWN signal are output signals.
(When CPU control mode, these signals are input signals.)

2.3.6.2

The LS612 has sixteen 12-bit registers. The R/\~ signal and the STB signal is used
as a read/write signal with pair. The RSO to the RS3 is used as a select signal of
registers when data setting.
The MAü to the NA3 is used as a select signal of
registers when output data written. When setting mode, data is sent or received
from "DO TO D7" pin. w'hen output mode, data is sent from "HDO to HD7" pin.
When the ME signal is active, data written will be sent from "HDO to MD7" pin.

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(SETnNG OF PAGE REGISTER)

DHA CONTROL CIRCUIT I

for 1/0 de.l.e
leeess ci rcutt

I I

_s

Thl' '19na1
low
when the 1/0 addre..
80H through 9FH are
,eleetad.

J: 11_

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I IIl

I
Refer to the ,eet1on

G.... rOB

XIORN

XIQWN

• Refer to the seetl0.
for 110 de.l ce
aeee.. elrcult

G.... TCB

FIGURE 2-3-16.

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G.... UB

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HRQ~

HLOA I--

CPU

GAATCK

10 GAATM21

......---/,....1_

GAATRF

To

A15

S

A8

AODRESS

1nter-nl 1
RA'"

FIGURE 2-3-17.

GAATOB

,
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OACK3

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In OMAI ope"t10n
llMA2 1nh1b1ts output
s 1gools I.elpt HRO
0;9nol.

~

DACKOI--

OMA2

HRQ

H~OAt-

OACKO

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AOSTS

OMAI
8237A -5

DHA CONTROL CIRCUIT II
(INTERNAL MEMORY ( - ) I/O)
- - 8 BIT DHA

-_.. _._ ..

I

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ino OMA 1llOd. XAD ';9 no1
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usec!
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FIGURE 2-3-18.

... L5245

CPU

GAATCK

MOO

)

.Mll7

I

GAATIO

To lnternal llAM

I

GAATRF

I
I

DHA CONTROL CIRCUIT 111
(IRTERNAL MEMORY ( - ) IRTERNAL MEMORY)
8 BIT DHA

500

)

507

GAATDB

GAATCB

GAATAB

)

00

07

OMA1
8237A-5

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OPTION StOT

CPU

GAATCK

{

SDD

f \

SD15

{TC

\

-

N011

WIe

SAn'

GAATDB

MIlO

~

MDIS

-0-IlOl1

r

=00:

....

\

lAI

\.-1&0

10

Inta~a1

I

GAATM'

RAH

AddNSS (A8_A15)

GAATRF

o~~

to output .y.n

o.

add~ess

IADSTB

DMA'

8237A5
AEN

}

s...

OIltlon
Slot

os 8blt
_ .llMA
_~atlon

t:=:!

j31--<' Dj7 }

to

DA(1I~DAD5

- - 16 BIT DHA

(IRTEBNAL MEMORY (-) 1/0)

1I kapt

_ r y tha addNSS "AO" 119ft.1

• In

DHA COBTROL CIRCUlT IV

~

@

; ,refresh lIOde.

GAATCB

.... i
AI'

,

dll!"&9aMiad. ,..,
exc.pt D-lIAM'

:~

~".

SAI611•

SAO

FIGURE 2-3-19.

OPTION StOT

@

GAATM'

GAATAB

I-!

Z

o

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~

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o

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8-bit memory on r/o channel
(16-bit bus operation)

8-bit

r/o

on

r/o
channel

10 [12]

4 [6]

10 [12]

8-bit memory on r/o channel
(8-bit bus operation)

8-bit r/o on r/o channel
(8-bit bus operation)

4 [6]

channel
(Other range)

1 [3]

1 [3]

r/o

16-bit r/o on r/o channel
(16-bit bus operation)

1 [3]

1 [3]

(OEOOOO to OFFFFF &
FEOOOO to FFFFFF)

~M

16-bit memory (16-bit bus operation)
DRAM (System memory)
(00000 to 9FFFF)

NOTE 1

18 [20]

8 [10]

3 [5]

18 [20]

8 [10]

*

1, 2, 3 or 4
[3, 4, 5 or 6]

NOTE 1

1 or 2 [3 or 4]

*

1 [3]

WAIT CYCLES ['IDTAL CYCLES]
6MHzI 8MHz
lOMHz

The GAi\TRF controls a wai t cycle insertion. The ,,,ai t cycle is executed to allow
adeguate timing margin for internal chips and external chips.
Ta reguest. wai t
cycle, the GAi\TRF sends an ARDYN (Ready) signal and an AREN-.N (R.eady enable) signal.
The number of wai t cycles is fixed except for a 16-bit ROH and a 16-1:ü t 1/0 channcl
device.
You ean select wait cyeles for the 16-bit RUri and the 16-bit, 1/0 channel
device by using jumper connectors ,]4, ,]5 and J6.
But t.he seleetion is available
onJ y for lOt-lHz use.
TABLE 2-3-11. WAIT CYCLES

Ready Signal Control Circuit

DEVICE 'ID BE ACCESSED

2.3.7

;.
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~

o

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~

~

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1

2

*
*
*
*

B-C
A-C

*
*
*
*

Insertion More Wait Cycle

EPROM

4

2
3
4

*
*1

16-BIT EX'I'ERNAL DEVICE

low when active.

cycle, a OWS signal is provided on the option slot. This signal is

Zero Wait Cycle Request

To insf'rt no wait

2.3.7.2

you want to insert more wait cycles, Please control the IOCHRDY (1/0 channel
Ready) signal. When the IOCHRDY signal is high, a wait cycle will be inserted.

\~hen

2.3.7.1

Ignored

A-C
B-C
A-C

B-C
A-C
A-C

* ---

*
*B-C

*
*B-C

WAIT CYCLE SELECTION

NUMBER OF WAIT CYCLES

TABLE 2-3-12.

NOTE1: A jumper connector can select wait cycles. Please refer to Table 2-3-12.

JUMPER NOMBER
6
5

*

(16-bit bus operation)

~

H

~

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H

~

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READV

CPU

FIGDRE 2-3-20.

GAATDB

GAATCB

GAATAB

GAATM 2

GAATMl

READY SIGNAL CONTROL CIRCUIT

• lilien the low aethe OlIS .1911a1 1. ~t f ..... tho OpUon .lot. tho .alt
eycll 1S not ln,"rtod. (No .alt eycll)

GAATIO

GAATRF
,

0 OWS

OPT ION)
SLOT

!

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o

~

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~
~
~

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~

\Jl

2.3.8

CONDITION OF TRE CDLY SIGNAL OU"JPUT

1NTA mode
1/0 read Iwrite mode
8-bit memory read/write

w.

1
2
3

CONDITION OF TRE CDLY SIGNAL OU"JPUT

\/

~

------v'.

READ/WRITE
SIGNAL

SIGNAL

ADDRESS

TIMING BETWEKN ADDRESS SIGNAL AND READ/WRITE SIGNAL

TABLE 2-3-13.

FIGURE 2-3-21.

Some devices can not allow the standard following time (T) because it is tao
short. The command delay signal control circuit makes adequate timing margin for
these devices.
To execute command delay function, it is necessary to send a CDLY (Command
delay) signal to the GAATCK. The GAATRF outputs a CDLY signal when it detects
the following mode listed in Table 2-3-13 automaticaly.

Command Delay Signal Control Circuit

i

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~

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trJ

?j

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IoI/11l

50

, I I 151

CPU

GAATDB

GAATCB

GAATIO

mrcßY~

o~

I .......,.

Wl"lte

GAATM 2

Wl"lte

e bit __ )

(Onlye bit d••l •• )

(3) .......,. ....d

(16 bit

(2) IID ....d. lID

(1) INTA _ .

TC

TC

Ts

CIoIDLY

_
READy~.r----

ISulp~~(
~""_--1,......

(~Bdl

TS
Sl.50~

CXlItWlD DELAY slgn.1

~

READY

1,-----

\

\

CXlItWlD

READY

COMKAND DELAY SIGNAL CONTROL CIRCUIT

Stltus .nd
{
Control
slgn.ls

FIGDRE 2-3-22.

i

Thes. slgn.15.re
.ontroll.d by COLY
slgn.1 .nd output
.ft.~ 1 O~ 2 • lock
d.1.y fo~ tIIe CPIJ
Input clock "CLK".

GAATAB

(R.f
n•• )
Dlff
n•• bet_n READY slgn.1 .nd COItlAND DELAY
slgn.1

"'tl

5.

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Inter rupt Contr ol Circu it

CPU

M/~

DTR
DEN

t

,

re~.r

InteM"Vllt ••etor

f ..... the I..er 7b1ts
of the date bus.

.,.. ,...d

~

INT..H

GAATC

I

,

others••• L

HLOA••• H
MSTR... H

I

I

I

~

l

SDO

I

002"

Al.S245

lIUSf

.0217 EAItO't

I

146818

IRQ

@"

lINTA

INTERRUPT CONTROL CIRCU IT

..

v»)))J

CAS2
CASI
CASO

INTA

\
00

If the da ta is s.t to tha outout
date bus buffe. regi ste. of the

~/!Ii

~I

"

H

..

H

.

)
)
)
)

)

)

H

H

L: SLAVE IClDE

IRl4 (1/0 s lot )
)
..
IRl5 (

)
H

(1/0 s lot )
IRIO (
IRll (
IRl2 (

1119

, H: MASTER IClDE

+,5

(
(
(
(

( 110 slot )

8254 OUTO
8042 (8742) P24
TRJ
IR4
IR5
~ IR6
IR'

act1ve

l8042(8742). thls signal go..

I-

~/rN

IRO
IRI
IR2
IRJ
IR4
IR5
IR6
IR'

8259 A-2
INT

@4 Yli/JA 0'

When the IHTA s1gnal 1s aeth.,
thls s1gnal go.. 1...

@

_IR1JI_~-

VI

{VD

GAATIO

NE'"' \f
....

~IR

FIGDRE 2-3-2 3.

G.... TDB

GAAT

"'U

Most"r

rt 15 level inter rupts .
This circu it includ es two interr upt contr ollers to suppo
mode.
de
Two INTCs are conne cted by a casca
Figur e 2-3-23 shows interr upt contr ol circu it opera tion.

2.3.9

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~

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~

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ROM Access Circuit

Available ROM Types

B-C

200ns or more higher

27256

B-C

A-C
A-C

J5

J4

JUMP ER. SEl'TIRGS

200ns or more higher

RECOMKENDED ACCESS SPEED

AVAILABLE ROM TYPES

27128, 2764

ROM TYPE

TABLE 2-3-14.

You can install the following type of ROM chips.

2.3.10.1

There are two pairs of ROM sockets. One is used by BIOS ROM. The others are free
sockets for user. We can select ROM socket and ROM size by setting of the jumper
connectors J4, JS, J6 and J7. Functional description of each jumper connector is
explained in CHAPTER 7.

2.3.10

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TOGur...B

lOG......T... '

... ,

... 16

..."m

5'
50

00

015

READY

CPU

50-N
5J-N

... 10

ROYN

CP

.)'

o

._.

-

OF7FFF
FF7FFF
OE7FFF
FE7FFF

OFoooo
FFoooo
OEoooo
FEoooo

OFFFFF
FFFFFF
OEFFFF
FEFFFF

OF8OOO
FF8000
OE8OOO
FE8000

-

OEoooo - OEFFFF
FEoooo - FEFFFF

OFoooo - OFFFFF
FFoooo - FFFFFF

ROM ACCESS CIRCUIT

XAJ-XA15

es

GAATMI

,dd
••••••••••.
eSFN Ind CSEN 5la.ll lethe
eSFN
CSEN

READY

CONTIlOL
eIRCUlT

GAATRF

XAJ-XA16

ARENN
... REYN

FIGDRE 2-3-24.

GAATDB

~

XAI

GAATCB

LA~CIl

OXA

?f~i~

GATE

AI6

GAATAB

+5

"'OlS-~

-\V

~

~
i

~

":0:1

o

~

"tl

~
~
~

5.

0\

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2.3.11

A timer counter (8254-2) controls refresh interval time. The refresh address is
sent from
a 8-bi t binary counter in GAATAB.
During D-RAM refresh, the CPU
executes a bus hold cycle.
The RFNO (Refresh output) signal is an important signal. From this signal, the
GAATM1 makes a RAD and a RA1 signal (RAS signal).
The GAATM2 controls the
refresh address by using this RFNO signal. And more, this signal is used by the
8-bit binary counten as a count-up signal.
Figure 2-3-25 shows the D-RAM refresh control circuit operation.

D-RAM Refresh Circuit

>

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VI

HRQ

HLDA

C PU

®

GAATOB

L"'E"'RN

~:::N

GAA TCB

110<

,...

C"O

GWONI..

I

FIGURE 2-3-25.

GAAT"'2

CD<

\

G

$"~Q

Counter

abil bln.~

l5590

GAATAB

RSN I =-=v=:;. 1115_

GAATCK

I

AlN

61H bit'

10PTlON

Ifmlrnj

1/0 reg1St.r

Por +2 B

1/

±:

GAA T10

SLOT)

GAAT""

D-RAM REFRESH CIRCUIT

I

GAATRF

WE

AAM Chip

RA'"

RA'"

These signals always
kept low.

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RAH Parity Check Circuit

~

CPU
@
GAATM2

MPll

GAATMI

(DATA WRlTE MODE)

RAH P ARlTY CHECK ClRCUIT

llillQ

GAATRF

FIGURE 2-3-26.

MOO

M015~@

~

~

~

.,

MB81256

equivalent

equivQ'.nt

"P04164

.'

01

01

.'

"P04164
equivaient

0'

MS81256
I'qui'#Glent

01

In a D-RAM write mode, the GAATM1 generates a parity data. When in D-RAM read
mode, the GAATM1 calculates the memory read data and the parity read data. If a
parity error has occurred, the GAATM1 outputs a PCKN signal. The GAATIO receives
a PCKN signal and makes a NMI (Non maskable interrupt) signal.
Figure 2-3-26 and Figure 2-3-27 show the RAM parity check circuit operation.

2.3.12

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CPU

NMl ~

- _.... -~

n

'---

r

r--

•

•

GAA TM2

-.!).o.'OO

'rni..~

J

@

r
bo r

DI

01

~ko'

...21-

~ ,,~
~~~1S
Ii; "

~CKN

I .....

GAATMI

RAH P ARITY CHECK CIRCUIT
(DATA READ KODE)

I

IN'.

!'Cu

110 Raoi,te'

N""I

lc. -

GUTtO

G AATRF

FIGURE 2-3-27.

GAATDB

GAATCB

-

.,
eQuivolent

or

""811256

00

or la
eQu;volent

""811256

-

@

t

®

f-

.2

00

1

03

eQuivolent

or

""811464

00

I

03

~

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""811464
or .2

0'
~uivQlftlt

eQuivalet

}IP04164

0'

00

""'11256

~ 00

0'

eQUivolent

J'P04164

00

0'

L

L

equivOlent

""811256

~ 00

@

~

~

H

~

l:z:I

~

o"Oj

cn

~

Iod

~
~

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Speaker Control Circult

GAA TCB

CPU

FIGURE 2-3-28.

(Speake~/OFF

GAATRF

i

i

Speike,

C~KZ

EH;]

* ~,&ede~c;":cg::lg~~:rt.

IOUTZ

_!GATEZ

8254-2

Figure 2-3-28 shows the speaker control

SPEAKER CONTROL CIRCUIT

8ltl 01 1/0 addreSl 61H
contra I bl t
O••• OFF 1••• 0Il

GAATDB

8ltO 01 l/O aeldreSl 61H
(Ti.... "g.UZ" OIlIOFF
contra I blt)

GAATAB

GAATCK

The timer counter controls the speaker.
circuit operaton.

2.3.13

5>

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~
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2.3.14.5

2.3.14.4

2.3.14.3

"d

The 8042 outputs software reset signal from P20 p1n.

E
i

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o

~

~

~
~

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Software Reset Signal Generation

The P17 pin of 8042 inputs the condition of the key cylinder switch. When P17
pin is low, keyboard scan code will be disabled by the 8042 internal circuit.

Disabling Keyboard Scan Codes

The 8042 reads the condition of slide switch SW1 on the ANTA board.

Monitor Setting Reading

The 8042 reads the condition of jumper connector J2 on the ANT-RM board.

RAM Size Reading

When receiving keyboard data, the 8042 receives keyboard data from test 1 pin.
~en sending a keyboard control command, the 8042 sends command da ta from P27
p1n.
When the 8042 receives keyboard data, it sends an interrupt request signal from
P24 pin. P26 pin of 8042 outputs control signal of keyboard data transmission.
In detail, (Refer to section 2.2)

Keyboard Interface

A Keyboard controller (8042 or 8742) includes the following functions.
1) Keyboard interface
2) RAM size reading
3) Monitor setting reading
4) Disabling keyboard scan codes
5) Software reset signal generation
6) Address A20 signal control

Keyboard Interface Circuit & Other Circuit

2.3.14.2

2.3.14.1

2.3.14

~
N

N

Address A20 Signal Control

* ----

DON'! CARE

A20G

A20 SIGNAL CONTROL BY GAATRF
A20

0 1 0
1 1 1
*
0
0

~O

TABLE 2-3-15.

The 8042 outputs A20 control signal (gate) signal to GAATRF.
GAATRF controls A20 signal as below.

2.3.14.6

>

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KID CLK
KID DATA

~

PI'

Pl1

I-- ~

fI+-+-

P'Zl

l

I+-I PZO I+-

PZ'

PZ&

PU

YQ~

GAATOB

r- Y I

.--

GAATCB

GAATAB

AZOG_

-=

r~

GAATlO

AZO_- AZO

~

CAZO_ :;

f1

GAATRF

~

o-r-

0

AMT-RM bCICI'cl
JZ

GAATMZ

JRAL

GAATMI
"" ........ ,...

KEYBOARD INTERFACE AND O'l'1lER FUNCTION CIRCUIT

TESTO
TESTl

PI'

Key Cylinde. Swltch

ro:::tJi

~!y~!y

~

8042(8742)

FIGURE 2-3-29.

r

SWI

..... AZO

CPU

RC

GAATCK

i

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I........ ........ I........

CPU

PWGO

es

GAATCB

SAI&

~

SAO

SOO

)

SOlS

GAATOB

cgNOl1
NOIZ
NOQ
saHEN

LA23

r

~
::

l-@

L

~

f-ol

I+-

-

~.

J'

2'

,

}

1/:15'

12

I

IR3
7,
9

IHTC

EOP

:-.

r--

ORQS, ~

OACK 5,

OMAC2

EOP

ORQO

,.

3

i

OACKy.

OMACl

1/0 SLOT ACCESS SIGNAL

GAATIO

Ml&N

lOl&N

~

WSON~
IROY

GAATRF

r/o slot access signals.

FIGDRE 2-3-30.

t.....

MEMRN
MEMWN

I

LAI7

SA"

\

~ lORN,lOWNSA17

~

RTC(145818l

~

~l
.

w

AEN
MSTR
HLOA
RSON
OSC
IOWN.IORN
SCLK I - MEMRN
MEMWN

SROYN
aALE

cer

GAATCK

GAATAB

2-3-30 shows the

1/0 Slot Access Signal

Figure

2.3.15

1
1

I

CLK

SMEMW
SMEHR

-IOCS1&
-MEMCSI5
©--+oLAI7-Z3
-MASTER
, - - . 0 saHE
, - POWER GOOO

~-MEMW

SOO-15
IRQ J.4,5.5 .7.9 .10, 11.12.14.15
-MEMR

~SAO-19
a

~IOW

ows;
&ALE
10CHROY;
AEN;
RESET ORW:
OSC;
ORQO.1.2.3.S.5.7
T/C
- OACKO.1.2.3.5.5,7
lOR

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~
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REV.A

2.4

PRINCIPLES OF OPERATION

MULTI-FUBCTION ADAPTER (SPFG BOARD) OPERATION

2.4.1

Serial Interface

A 16450 is used as aserial data controller.
The XTAL1 terminal receives
1.8432 llilz clock generated by the OSC terminal in the gate array GAATSP.
2.4.1.1

16450 Chip Select Circuit

Chip select signal CS2 for activating the 16450 is applied from the gate array
GAATSP (SCSN signal). There are two kinds of 1/0 addresses which SCSN signal
activates. They are selected by jumper pin J5 and J6. Setting of J5 and J6
are listed in CHAPTER 7.
Ir-------I-~ es 2

SCSN

8

SIFO~--oQ_

B

SIF 1 t-------I500

5LCTlN
INIT
~t-1I--4P------o

AU T0 FOx T

~t-1t-1I--4.-----O

5 TROBE

5LN
INI
ATF..-----'
5 TB ! 4 - - - - - '

FIGURE 2-4-6.

PRINTER CONTROL SIGNAL READ CIRCUIT

Printer Status Read Circuit
GAATSP
S07

S07 -

l
S

S06 -

2
4
4

SOS -

\

S04 -

S03

S03 -

I

G

•

ADORESS

lJECOOER

BUSV

t-BSY
II-

ACK
EOP.

-

ACK
PE

t-Sl P

SlCT

t - ERR

ERROR

I

FIGURE 2-4-7. PRINTER STATUS READ CIRCUIT
Interrupt Signal Control Circuit
-------------~---~.-.~.

JRS

...

....--

JR7

-

___ A

--

J 10

B

C

>'
OJRE

I

",I RE')
bit"

GAATSP

FIGURE 2-4-8.

2-68

IlITERRUPT SIGNAL CONTROL CIRCUIT

ACK

REV.A

PRINCIPLES OF OPERATION

1.2 MB PDD
EQUITY II / EPSON PC+' s 1.2MB FDD (SD-581L) can not be installed on EQUITY
111+ / EPSON PC AX. Because FDD control signals are different between EQUITY
II / EPSON PC+'s 1.2MB FDD and EQUITY III+ / EPSON pe AX's 1.2MB FDD.
(Refer to Table 2-4-2)

TABLE 2-4-2.

DIFFERENCE BETWEEN 1.2MB PDD OF SD-581L AN» FDl155C/MD5501
SD-58lL(*1)

PIN NO.
2

4
6
8
10
12
14
16
18
20

22 (*3)
24
26
28

30 (*3)
32
34

OTHER PIN

NOTE

(*1)
(*2)

(*3)

FDl155C/MD5501(*2)

MODE SELECT
DISK CHANGE
DRIVE SELECT 3
INDEX
DRIVE SELECT 0
DRIVE SELECT 1
DRIVE SELECT 2
MOTOR ON
DIRECTION
STEP
WRITE DATA
WRITE GATE
TRACK 00
WRITE PROTECT
READ DATA
SIDE SELECT
READY
GND

MODE SELECT
(NOT USED)
DRIVE SELECT 3
INDEX
DRIVE SELECT 0
DRIVE SELECT 1
DRIVE SELECT 2
MOTOR ON
DIRECTION
STEP
WRITE DATA
WRITE GATE
TRACK 00
WRITE PROTECT
READ DATA
SIDE SELECT
DISK CHANGE
GND

SD-581L is used in the EQUITY II/EPSON PC+.
FD1l55C and MD5501 are used in the EQUITY III+/EPSON PC AX.
The difference of read/write data between SD-581L and FD1155C/
MD5501 are shown in below.

U1J
I...

T

'>~.

U

1. 5T

L

+~2_T~

(NORMAL DENSITY MODE)
SD-581L ....•..... T
FD1155C/MD5501 ... T

4 us
3.33 us

(HIGH DENSITY MODE)
SD-581L
FDl155C/MD5501

2 us
2 us

T
T

2-69

PRINCIPLES OF OPERATION

2.4.3

REV .A

FDD Control Circuit

FDe

GAATFD

°S7
00

Cl

FO 11

0
.....
H

FOIO

~

es

3F4,3FS
(3T/4.375)

B

A

FCSN

WR

A J2

rq
C

AOORESS

RO

OECOOER

IOW IOR
BOIR
ALS245

DIR

FIGDRE 2-4-9.
2.4.3.1

FDD CONTROL CIRCUIT I (FDD (-) CPU)

FDD Control Register Access Circuit

There are three kinds of r/o addresses on the FDD control register access
circuit. They are selected by jumper pins J2 and J1. Setting of J2 and J1 are
listed in CHAPTER 7.

2.4.3.2

Interrupt Signal and DHA Request Signal from FDC

,--------------

FOC (765)

IRQ'

VQ

IH1

I

ORQ

bit]

"'OfF

I

OQ.OY

0ACii I+-

CIJICU[T

,--

,~ .,

ORa
'CAH-a-

ORGZ

~

T

CAKH CR!!H
GM1FO

CA( KZ

---,------,-----------------------------FIGURE 2-4-10. INTERRlPT SIGNAL AND DHA REQUEST SIGNAL FROH FDC
2.4.3.3

FDD Control Signals

MFM/FM signal of FDC is not used.

MFM/FM is se1ected by a software command.

Disk Change Signal
\V"hen 1/0 address 3F7H or 377H is accessed, low level signal output i8
generated from the 3X7N terminal in the gate array GAATFD, and the disk change
signal from FDD 18 applied to SD7 signal.

2-70

REV.A

PRINCIPLES OF OPERATION

2.4.3.4

Read/Write Circuit

Write circuit

Figure 2-4-11 shows the FDD data write circuit.

FDC(765)
ClK

ClK

WClK

WClK

a..OCK
CIRCUIT

AODRESS
DECODER FOl1

ClK
WOATA
PS1
PSO
WE

FWO
PS1
PSO
WE

wo

00

J 2

WRT
OATA
(FOO

GAATFD

FIGURE 2-4-11.

FDD DATA WRITE CIRCUIT

*

FDD register of the SPFG board can select PC/ AX mode and PC/ AT mode by
jumper switch (J2).
In case of the pe/XT mode, CLK and WCLK output generated in the gate array
GAATFD is fixed.
Note: When jumper connectors J1 and J2 are set to
to access the FDD register.

0,0, it is impossible

2-71

)

PRINCIPLES OF OPERATION

REV.A

Read circuit

The VFO circuit has the following modes.
Data transmission speed
1. SOOK bps mode
2. 300K bps mode
3. 2S0K bps mode
These modes are selected by

AO~ DO~ D1~

VFO

FDC(765)

WINOOW
RO OATA

WR and 3XVN signals.

WINOOW

-

.

SYNC

C

{=:

~---.

RAW RO

RO
SYNC
AO
00
01

----. WR

3XVN

WClK

I'

3XVN

WClK

GAATFD

FIGDRE 2-4-12.

2-72

FOD DATA READ CIRCUIT

REAO OATA

REV.B

PRINCIPLES OF OPERATION

VFO circuit

The VFO circui t inputs a RAWRD signal and generates a WINDOW signal which
synchronizes a REWRD signal.
When FDD is not in read operation, VFO circuit synchronizes a WCLK signal.
The VFO circuit will synchronize, whether a weLK signal or RAWRD signal is
selected by SYNC signal.
(Whether the VFO circuit is synchronized \vith lJCLK signal or RAWTD signal is
selected by SYNC signal.)
. When 500Kbps
or 250Kbps,
this signal
becomes active •

.

EI

f

-,

IIIlen JOOo

+5V

1'20~~
TE"'INATOR~
OFF
330

FIGURE 2-4-18.

2-76

HARD DI8K DRIVE SIGNAL CABLE

REV .A

2.5

PRINCIPLES OF OPERATION

KEYBOARD

The keyboard unit has two operation modes.
One 1S AT mode, the other
mode.
In the AT mode, there are three kinds of key code output mode.
Mode selection is performed by software.

1S

XT

Key code output mode (a)

~ Key code output mode (b)

AT mode
Keyboard u n i t <

Key code output mode (c)

XT mode
The EQUITY 111+ / EPSON
mode.
2.5.1

pe

AX system uses the key code output mode of the AT

Block Diagram

The following diagrarn shows keyboard unit block diagram.

:> CLOCK

<
<

:> DATA

-,

DRIVER

LED

CPU
,

KEY
MATRIX
/

....

MULTIPLEXIER
FIGURE 2-5-1.

KEYBOARD UNlT BlOCK DIAGKAM

2-77

PRINCIPLES OF OPERATION

2.5.2.
2.5.2.1

REV.A

Interface Signal
AT mode

The Keyboard data (sent from keyboard) or the keyboard control data (sent from
Host side) are communicatedby using the clock pin and the data signa].
There are two modes in the keyboard interface circuit.
One is interface
control mode, the other is data communication mode.
In the interface cont rol mode, the host controls operation mode of the
keyboard to the host or from the host to the keyboard.
At this mode, the
keyboard sends clock signal to synchronize between the keyboard operation 2nd
the host side operation.
TABLE 2-5-1.
CLOCK

INTERFACE CORTROL MODE

DATA

II
L
L
H

FURcnON

Keyboard
Keyboard
Keyboard
Keyboard

H
H
L
L

can send Data to Host side
can't send Data to Host side
prepares receiving Data
starts inputting Data

HaST SIDE

KEYBOARD
CLOCK ........DATA

TABLE 2-5-2.
CLOCK
DATA

CLOCK
DATA

.....

DATA COMMUNICAnON MODE (AT MODE)

Keyboard sends clock signal to synchronize
keyboard operation and Host side operation.
(1) Keyboard sends Data.
(2) Host sends Data.

HaST SIDE

KEYBOARD
CLOCK
DATA ....
J

2-78

. CLOCK
. DATA

,

between

REV.A

PRINCIPLES OF OPERATION

2.5.2.2

XT mode
TABLE 2-5-3.

DATA COMKUNICATION MODE (XT MODE)
Keyboard initializing signal (low active)
Clock signal

XT
DATA

2.5.3

Keyboard Data wait signal (low active)
Data signal from keyboard.

Description of Interface Signals (AT mode)

2.5.3.1

Clock

*

Synchronous clock for transmitting and receiving keyboard data.

*

The clock is generated from the keyboard.

*

The transmission of data cannot take place even if the keyboard is ready
to transmit when there is a low level signal (data wait) in the clock
line. (data will be saved in the keyboard buffer)
The keyboard checks the clock line during transmission of data and will
stop transmission when it detects there is a 10w level signal.

2.5.3.2

Data

*

Keyboard transmission (keyboard scan code, command code), reception code
(command code) data.

*

This is also the transmission request signal from the host. Once a 10w
level signal is detected in the data line, the keyboard is ready for
reception.

2.5.3.3

Keyboard Data Output (AT mode)

When the keyboard is ready to transmit data, it checks the c10ck and data
lines for data wait or transmission request. If there are high level signals
in both the clock and da ta lines, the keyboard determines that transmission is
possib1e and starts transmitting.
It checks the c10ck 1ine during
transmission and stops data transmission as soon as it detects a low level
signal.

2-79

PRINCIPLES OF OPERATION

2.5.3.4

REV.A

Keyboard Data Input (AT mode)

When the keyboard detects a low level signal 1n the data line it becomes ready
to receive.
Then the signal in the host clock line drops to a low level below 60 us, which
will stop keyboard transmission.
When the keyboard detects a high level in the clock line, da ta reception is
performed (counts off each group of 11 bits). After receiving the 10th bit,
the keyboard changes the signal in the data line to low level and receives one
more bit (the stop bit). The low level signal of the 11th bit teIls the host
that the data has been received.
2.5.3.5

Data Transmission Method and Data Format

TADLE 2-5-4.

DATA TRANSMISSION ME'l1IOD AND DATA FORMAT

(1) Transmission method

Transmission rate
Start bit
Stop bit
Data length
( 6) Parity
(2)
( 3)
( 4)
(5 )

Synchronous serial
transmission
9600 BPS

Synchronous serial
transmission
'=. 9600 BPS

1
1

1
1

8 bit
Odd parity

8 bit
None

CLOCK

OATA

I

START

I

00

0

01
Tl

T2
T3
T4
FIGURE 2-5-2.

2-80

~~
104
20
20
35

Op
us
us
us
us

STOP

+20%
Min
Min

+20%

KEYBOARD DATA OU'IPUT - AT MODE

REV .A

PRINCIPLES OF OPERATION

T6

~

~

CLOCK
c T5 ~

L

OATA ----,......

START

1

00

60 us Min ( Host data output ready time)

T5

T6
FIGURE 2-5-3.

01

.&..-_ _.....

5 us Min

KEYßOARD DATA IWUT - AT MODE

...

T4

T2

~

CLOCK

DATA

f....]

START

1__D_0

0_l_......._0_2_
Tl
T2
T3
T4

FIGURE 2-5-4.

100 - 250 us (Oata output possibility
104 us +20% check time)
10 us Min
10 us Min

KEYBOARD DATA OU'JPUT - XT MODE

2-81

PRINCIPLES OF OPERATION

2.5.4

HEV.A

Interface Circuit Specification

sv
2.2K
-----< t-------4..------+-----DATA(
CLOCK)

~S6P
74LS125

equ;valent

FIGURH 2-5-5.
2.5.5

IRTERFACE CIRCUIT

Connector P in Explanation

DIN connector

FIGURH 2-5-6. KEYBORAD CORRKCTOR PIK LOCATIOKS
TABLE 2-5-5.
PIK NOMBER.

2-82

KEYBOARD CONNECTOR P IN FUNCTION
SIGNAL NAME

1

Clock

2
3
4
5

Data
N.C.

Ground
+5V DC
Ground

REV .A

PRINCIPLES OF OPERATION

2.5.6

Function Specifications

2.5.6.1

Strake Characteristics

At N key rollover (with diode)

ON

OFF

Keyl--r----------,----------

Key2 - - - - - - -....
Key3 - - - - - - - - - - -...

Data---48}o---e---G--<

30ffX 20ff)--

STROKE CHARACTERISTlCS

Typematic Function

A key scan code i8 transmitted as long as a key is depressed.
(Transmission
intervals for all keys except the F16 (P ause) key depend on the typematic
rate/delay (command assignment).
When any of the other keys are pressed, it
enters a new typematic cycle.

Keyl--Key2--------------

Data

--0(

<

Tl

> < T2 '>

FIGURE 2-5-8.

<

Tl

TYPEMATlC FUHCTlON

2-83

PRINCIPLES OF OPERATION

REV.A

TABLE 2-5-6.

TRANSMISSION INTERVALS

AT MODE

Tl

TZ

XT MODE

500 ms
92 ms

250 - 1000 ms (default)
1/2 - 1/3 sec (default)

The typematic function will be disabled when a clock line is low level.
2.5.6.3

Keyboard Buffer

When a key is pressed (released) before the code of a key pressed earlier has
been transmitted during tbe key data out phase t the code of the no
transmitted key is saved in this buffer until it is transmitted.
The buffer can save codes for 16 keys (16 make or break data).
The 17th code will be substituted by an overrun code.
However t no substitution will take place if there ts an overrun code in the
buffer.
Break codes and make codes when a key is depressed will not be lost even
during an overrun.
Hmlever t they will be cancelled by a buffer clear command.
The overrun code is different between mode and mode below.
TABLE 2-5-7.

OVERRUN CODES

KEY CODE OU1PUT MODE

AT mode
XT mode

2.5.6.4

tUl~ed

Following the power on reset

"AAR"

2-84

FF

00
FF

00

t

a self-test program is performed.

self-test program
self-test program

After the test t the keyboard turns off the mode indicator display (3
LED's) and transmits the end code of the self-test program.

"FeH"
(3)

(c)

on the keyboard logie performs a power on reset.

ROM check sum
. RAH check
(2)

(b)

Power On Reset (AT mode)

When the power is
(1)

(a)

operated correctly
operated abnormally (scanning
transmission of the end code.)

is

stopped

after

When the operation normal end code (.AAH) has been transrnitted and
the keyboard detects a low level signal longer than 10 us in the
da ta line 5 us after from following edge of the stop bit t the
keyboard enters the XT mode.

PRINCIPLES OF OPERATION

REV.A

(4)

In AT mode, the typematic rate/delay time and key code output mode
will be set according to mode (b).
Rate
Delay

2.5.6.5.

10 .9 CP S (92 ms)
500 ms

Default
Default

Initializing (XT mode)

The clock Une is checked in 10 ms cyc1es by keyboard and initializing is
performed as soon as a low level signal is detected.
(1)

Key scan memory clear

(2)

Buffer (FIFO) clear

(3)

Self-test program performed
. ROM sum check
. RAM check

(4)

Transmission of self-test program end code
" A.AlI"

"FeH"

2.5.6.6

self-test program
self-test program

Operated correctly
Operated abnormally (scanning
transmission of the end code.)

is

stopped

after

Data Wait Function (XT mode)

When the start bit is set, the data line is checked by the keyboard and if a
low level signal (longer than 250 us) is detected in the data 1 ine, data
transmission will not take place.

2-85

PRINCIPLES OF OPERATION

2.5.6.7

REV.A

Mode Indicator (3 LEnis) Display (XT mode)

Basic Operation
(1)

By pressing the Scroll Lock, Numeric Lock and Gaps Lock keys each
indicator are displayed alternatively (performed after the end of
key code transmission).

(2)

All displays are turned off during power on reset and initializing.

(3)

The alternative operation
(Gtrl) key is pressed.

does

not

take place when

the

control

Typematic Out
~

:·°1
I
I

Lock Key
(Data Out)

I

I

I

I

. ."
ON

I

Ctrl Key - - - - - - - - - - - Indication.J

FIGURE 2-5-9.

ON

.....

I I

~-----O-N------I ...__

BASIC OPERATION OF MODE IlIDICA'l'OR DISPLAY

Special Operations (For Germany and French)
By pressing the Gaps key, Gaps Lock indicator becomes on (light).
the shift key, Gaps Lock indicator becomes off (Not light).

By pressing

·:·,......: ]

Typematic Out

....· ... -- ---

Caps Key

Shift Key

Ctrl Key

Caps indication

~

ON

-------_I
L
L
ON

FIGURE 2-5-10'. SPECIAL FURCTIONS OF MODE IlIDICA'l'OR DISPLAY

2-86

PRINCIPLES OF OPERATION

HEV.A

Key Scan Code

2.5.7

key Code Output (AT Mode)

2.5.7.1

In AT mode, there are three output modes

(a),(b) and (c)

Key code output in mode (a) and (b)
(1)

Key code make up
The table below shows the codes allocatted to each key.
TABLE 2-5-8.

TITLE

KEY POSITION

General
Keys

Other
A09,B20,AI2

KEY CODE KAKE lJP

MAKE CODE (*1)
MODE (h) MODE (a)

x
EO + x

x
EO + x

Extension A,D,EI4 - E16
Key -1
BI5

EO + x

EO + x

Extension E18
Key -2

EO + x

EO + x

Extension Fl4
Key -3

EO + x

EO + x

x

x

Shift
Key

BOO ,Bll

Special
Key

FI6(Pause)

M>TE

(*1)
(*2)

Note 1
Note 2

8 bytes

6 bytes

BREAK CODE (*2)
MODE (h) MODE (a)

Make code
is
substituted
by "FO + x"

"80" is added
to make code
"x" (OR)

No key code output

Make code (When key is depressed)
Break code (When key is released)
The "x" code indicates scan code data. (Refer to Table 25-22)
The F14 and 16 keys can generate other codes if used in
combination with other keys. (Refer to section 2.5.7.1)

2-87

PRINCIPLES OF OPERATION

(2)

REV.A

Shift function
a) Numeric lock
The table below shows the conditions for setting and releasing
the numeric lock.
TABLE 2-5-9. CONDITION FOR SETTING AND RELEASING NUMERIC LOCK

Setting

. Released

Note 1

When the
has been
lit by a
released

E17 (Num lock) is pressed and the make code
transmitted or when the NUM Lock LED been
host command while the numeric lock is in
status .

When the E17 key (Num lock) is pressed and the make
code has been transmitted or when the Num Lock LED
has been turned off by a host command while the
numeric lock is in set status.

When the AOO or the A12 key (Ctrl) are pressed, it is not
possible to perform setting or releasing with the Numlock
key.
(Setting and releasing cannot be performed even if
the Ctrl key is released first.)

b) Extension Left and Right shift key code transmission
i) The table below shows the key stroke conditions
transmission of extension left and right shift codes.
TABLE 2-5-10.

N-LOCK

NOT N.LOCK

N.LOCK

2-88

for

KEY STROKE CONDITION

EXTENSION SHIFT SETTING

EXTENSION SHIFT RELEASE

Extension shift off code is
transmitted when extension key-l
(or extension key-2) is pressed
after the shift key has been
pressed.
In case of pressing extension
key-2, same operation is
performed even though N.LOCK
mode.

(1) Extension shift on code
is transmited when extension
key-l (or extension key-2)
is released.
(2) Extension shift on code
is transmitted when other
keys are pressed.

Extension Left shift on code is
transmitted when extension key-l
(or extension key-3) is pressed
after the shift key has been
pressed.
In case of pressing extension
key-3, same operation is
performed even though NOT
N.LOCK mode.

(1) Extension Left shift
off code is transmitted
when extension key-l (or
extension key-3) is released
(2) Extension Left shift
off code is transmitted
when other keys are
pressed.

PRINCIPLES OF OPERATION

REV.A

ii) Extension left and right shift codes are as folIows.
TABLE 2-5-11.

EXTENSION LEFT ABO RIGBT SBIFT CODES
MODE (b)

MODE (a)

Extension Left
Shift on code

EO + 12

EO + 2A

Extension Left
Shift off code

Eü + FO + 12

EO + AA

Extension Right
Shift on code

EO + 59

EO + 36

TYPE

Eü + Fü + 59

Extension Right
Shift off code

iii) Transmission
folIows.
TABLE 2-5-12.

sequence

left

and

right

codes

are as

TRANSMISSION SEQUENCE OF LEFT ABO RIGBT CODES KEY
CONDITION

Extension Shift Setting
Hhen extension
Shift setting
key is OFF

Extension
Shift
Release

When other keys
are ON
Note

of

Eü + B6

"x"

"EXS" :

TRANSMISSION SEQUENCE

EXS

x

EXS

----)

x

----) EXS
----)

x

Key data
Extension Left and right shift codes

2-89

HEV.A

PRINCIPLES OF OPERATION

(3)

Special operations generated by a combination of keys
a) The codes shown in the table below are transmitted when the F16
(Break) key is pressed while either the Aaa (left Ctrl) or the
A12 (right Ctrl) key is also pressed.
TABLE 2-5-13. TRANSMITTED CODE OF F16(BREAK) KEY
MODE (b)

EO + 7E + EO + FO + 7E

MODE (a)

EO + 46 + EO + C6

Note

(4)

No code below are transmitted when the F14 (Sys Rq) key is
pressed ~lhile the [A01 (left Alt) ~ the A09 (right Alt)]
and the [AOa (left Ctrl)~ A12 (right Ctrl)] key or the BOO
(Left shift) and BII (right shift) keys.

Key code output du ring typernatic operation
All keys except the F16 (pause) key are typematic keys whose make
codes are transmitted at specified intervals.

TABLE 2-5-14. TRANSMITTED CODE OF F14(Sys Rq) KEY

WIIEN AOO, A12 KEY OR
BOO, Bll KEYS ARE DEPRKSSED

WIIEN A01, A09 KEYS ARE
DEPRKSSES

MODE
HAKE

BREAK

HAKE

BREAK

FO + 84

(b)

EO + 7C

EO + FO + 7C

84

(a)

EO + 37

EO + B7

54

2-90

D4

PRINCIPLES OF OPERATION

REV.A

Key Code Output in Mode (c)
(1)

Transmission of make codes (when keys are pressed)
A one byte make code is transmitted when a key is pressed (refer to
scan code table).

(2)

Transmission of break codes (when keys are released)
The AOO (left Ctrl), the AOI (left Alt), the BOO (1eft shift), the
Bll (right shift) and the COO (Caps) keys transmit break codes when
a key is released. The break code is "FO + make code".

(3)

Key code output during typematic operation
The A04, A14-A16, BOI-BIO, BIS, COl-C12, DOO-D14, EOO-E13, D20,E13',
C12', Bll', BOO' and D20' keys are typematic keys whose make codes
are transmitted at specified intervals when pressed repeatedly.

(4)

The break code transmission keys in (2) and the typematic keys in
(3) above are set during default and all keys can be set with the
commands described below.

2.5.7.2

Key Code Output (XT Mode)

The Key code outputs are performed according to the same conditions that
prevail in key code mode (a) during AT mode (inc1uding shift function).
2.5.8

COMMANDS (AT mode)

2.5.8.1

Commands From the Rost Side

These are commands received by the keyboard which it responds to within 20 ms.
TABLE 2-5-15.
COMMAND
RESET
RESEND
TYPEMATIC KEY RESET 1,2
TYPEMATIC KEY SET
ALL KEY TYPEMATIC CONTROL
SET DEFAULT
DEFAULT DISABLE
ENABLE
SET TYPEMATIC RATE/DELAY
READ KEYBOARD ID
SET/READ KEY CODE MODE
ECHO
SET/RESET MODE INDICATORS

KEYBOARD COMMANDS (AT MODE)

DATA (HEX)
FF
FE
FC,FD
FB
FA-F7
F6
FS
F4
F3
F2
FO
EE
ED

BUFFER CLR

LID SET

0
0
0
0
0
0
0

0
0

2-91

PRINCIPLES OF OPERATION

REV.A

(1)

Reset
The keyboard reeognizes this eornmand with the aeknowledge (ACK)
eommand.
When reeept ion of the ACK command has been eon f i rmed
(eonfirmation is mode when both the eloek and data line signals
exeeed 500 us high) a reeset operation indentieal with the pmler on
reset is performed. (Exeept for XT mode switching operation)

(2)

Resend
The keyboard repeats the transmission of end data transmitted when
reeives aresend eommand.

(3)

Set default
The keyboard responds with an ACK eommand and eontinues seanning
after the output buffer has been cleared and the default condition
has been set.

(4)

Default disable
The keyboaed stops seanning and exeept that i t waits for a eommand
it behaves as during a set default command.

(5)

Enable
The keyboard aeknowledges to the host side with and ACK eommand and
clears the output buffer. Then starts seanning.

(6)

Set typematic Rate/Delay
This command is made up of a 2-byte command and parameter.
The keyboard responds to the ACK command, stops scanning and waits
for the parameter. Then the keyboard responds to the parameter with
an ACK command, sets the rate and delay shown in the figure below
and starts scanning (when proceeded as an Enable). If a cornmand is
received instead of a parameter, the eurrent rate remains unchanged
and keyboard stops this command operation, then the new eommand is
performed and scanning starts.
TABLE 2-5-16.

MSB

TYPEKATIC RATE/DKLAY

LSB

RATE
DELAY

2-92

PRINCIPLES OF OPERATION

REV.A

1) DELAY

BIT

DELAY

6

5

0
0
1
1

0
1
0

(ms)

250
500
750
1000

1

2) RATE

RATE

BIT
4

3

2

1

0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1

1

(cps)
30.0
26.7
24.0
21.8
20.0
18.5
17.1
16.0
15.0
13.3
12.0
10.9
10.0
9.2
8.6
8.0

BIT

RATE

4

3

2

1

0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

0
0
1
1
C
0
1
1
0
0
1
1
0
0
1

1

1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1

1
1
1

1
1
1

(cps)
7.5
6.7
6.0
5.5
5.0
4.6
4.3
4.0
3.7
3.3
3.0
2.7
2.5
2.3
2.1
2.0

2-93

HEV.A

PRINCIPLES OF OPERATION

(7)

Echo
The keyboard transmits a code "EE" response and continues scanning
(when preceeded as an Enable).

(8)

Set/Reset mode indicators
This command is made up of a 2-byte cornmand and an option.
The
keyboard responds to the host side with and ACK command and waits
for sending of the option.
Then keyboard responds to the option,
sets the indicator and starts scanning (when proceeded as an
Enable).
If it receives another command instead of the option, the
indicator condition remains unchanged and the keyboard stops, this
command operation.
Then proceeds the new command and starts
scanning.
TABLE 2-5-17.

MSB

OPTION REGISTER FüR KEYBOARD

LSB

SCROLL LOCK
INDICATOR
NUMERIC LOCK
INDICATOR
CAPS LOCK
INDICATOR

(9)

2-94

Read Keyboard ID
The keyboard responds with the ACK cornmand, transmits a 2-byte data
; "AB" + "83"

REV .A

PRINCIPLES OF OPERATION

(10) Set/Read key code mode
This command is made up of a 2-byte command an option. The keyboard
responds to the host side with an ACK command stops scanning and
waits for the option. When keyboard inputs option, it responds to
the host side with an ACK command, starts scanning after setting key
code mode or transmission status.
(When proceeded as an Enable.)
If it receives another command instead of the option, processing of
this command is cancelled, the new command is proceeded and scanning
starts.
i) Read key code mode starts (option data "00")
The keyboard transmits the current keycode mode status. (1
byte)
TABLE 2-5-18. K.EY CODE MODE STATUS

K.EY CODE MODE
(a)
(b)
(c)

TRANSMITTING DATA

01
02

03

ii) Set key code mode (option data : "01"-"03")

The keyboard is set to specified key code mode depending on
the option data.
TABLE 2-5-19.
OP TION DATA

01

K.EY CODE MODE ON OPTION DATA
K.EY CODE MODE

(a)

02

(b)

03

(c)

(11) Typematic key set
This command is made up of a eommand and an option (Max 4 or 5
bytes). The keyboard responds to this command with an ACK command,
stops scanning and responds to the option with an ACK command. In
the key code mode (c), this command sets the typematic function and
cancels break code transmission for keys waiting for the key scan
codes that correspond to the option data. When the command has been
proceeded, scanning stops and remains in that condition.
(12) Typematic key reset 1 ("FC")
This command releases the typematic function and sets transmission
of the break code for keys waiting for key scan codes corresponding
to option data. Other details are the same as described in the ease
of typematic key set above.

2-95

PRINCIPLES OF OPERATION

REV.A

(13) Typematic key reset 2 ("FD")
This command releases the typematic function and cancels
transmission of the break code for keys waiting for key scan codes
corresponding to the option data.
Other details are the same as
described in the case of Typematic key set above.
(14) All key typematic control

The keyboard responds to this command with an ACK command cancels 01'
sets the typematic function and break code transmission and
continues scanning (when proceeded as an Enable.)
TABLE 2-5-20.
COMMAND DATA

FA
F9

TYPEMATIC FURCTION

BREAK CODE TRANSMISSION

Setting
Cancel
Cancel
Setting

F8

F7
2.5.8.2

ALL KEY TYPEMATIC CONTROL

Setting
Cancel
Setting
Cancel

REMARKS

Applied for
only key
code mode
(c) •

Commands To Host Side

These are commands transmitted to the host side by the keyboard.
TABLE 2-5-21. COMMANDS 1'0 'l'HE BOST SIDE
COMMAND

Resend
ACK
Overrun
Break Code Prefix
BAT Completion
Echo Response
Read Keyboard ID
Read Key Code Hode

**

2-96

DATA (HEX)

FE
FA

**
FO
AA

EE
AB + 83

Hode (a) + 01
Hode (b) + 02
Hode (c) + 03

Key Code Hode (a) •...•• FF
Key Code Hode (b),(c) .. 00

(1)

Resend
The keyboard generates aresend command when it receives an invalid
input 01' invalid parity input.

(2)

ACK
The keyboard outputs an ACK response for valid inputs that do not
generate echo 01' resend commands. If an interrupt is issued to the
keyboard when an ACK command is being transmitted, transmission i8
terminated and the ne~l command is responded to.

PRINCIPLES OF OPERATION

REV.A

(3)

Break code prefix
This cornmand announces that a key has been released and sends the
first byte of a 2-byte message.
(Corresponds to key code mode (b)
and (c).)

(4)

Overrun
The overrun character is in the 17th position of the keyboard buffer
and when the buffer becomes full, the character is stacked on the
last code. When this code comes first in the buffer it is output as
an overrun error.

(5)

Bat completion code
When BAT is completed normally, the keyboard outputs an "M"
response.
"FC" or other code indicates that the keyboard
microprocessor is malfunctioning.

(6)

Echo response
This command is transmitted in response to an echo command from the
host side.

(7)

Read keyboard ID
This command is transmitted in response to an equipment ID data read
cornmand from the host side.

(8)

Read key code mode
This command transmits current keycode mode status in response to a
key code mode read cornmand from the host side.
TABLE 2-5-22.

KEYNO.
FOO
F02
F03
F04
F05
F06
F07
F08
F09
FI0
F11
F12
F13
F14
F15
F16
EOO
EOI
E02
E03
E04

MODE(a)

MODE(b)

01
3B
34
3D
3E
3F
40
41
42
43
44
57
58
EO,37
46

76
05
06
04
OC
03
OB
83
OA
01
09
78
07
EO,7C
7E

**

**
OE

29
02
03
04
05

16
lE
26
25

MODE(c)
08
07
OF
17
IF
27
2F
37
3F
47
4F
56
5E
57
5F
62
OE
16
lE
26
25

KEY SCAN CODE LIST
KEY NO.
EI3(*2)
E14
E15
E16
E17
E18
E19
E20
DOO
DOl
D02
D03
D04
D05
D06
D07
D08
D09
DI0
DU
D12

MODE(a)

MODE(b)

7D
EO,52
EO,47
EO,49
45
EO,35
37
4A
OF
10
11
12
13
14
15
16
17
18
19
lA
IB

6A
EO,70
EO,6C
EO,7D
77

EO,4A
7C
7B
OD
15
ID
24
2D
2C
35
3C
43
44
4D
54
5R

MODE(c)
5D
67
6E
6F
76
77

7E
84
OD
15
ID
24
2D
2C
35
3C
43
44
4D
54
5B

2-97

REV.A

PRINCIPLES OF OPERATION

E05
E06
E07
E08
E09
EIO
Ell
E12
El3
COO
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
Cll
C12
C12' (*1)
C17
C18
C19
BOO
BOO' (*1)
BOl
B02
B03
B04
B05

06
07
08
09
OA
OB
OC
OD
OE
3A
1E
IF
20
21
22
23
24
25
26
27
28
IC
2B
4B
4C
4D
2A
56
2C
2D
2E
2F
30

2E
36
3D
3E
46
45
4E
55
66
58
1C
1B
23
2B
34
33
3B
42
4B
4C
52
5A
5D
6B
73
74
12
61
1A
22
21
2A
32

2E
36
3D
3E
46
45
4E
55
66
14
1C
1B
23
2B
34
33
3B
42
4B
4C
52
5A
53
6B
73
74
12
13
1A
22
21
2A
32

Dl3(*3)
2B
D14
EO,53
DIS
EO,4F
D16
EO,51
D17
47
D18
48
D19
49
D20
4E
D20'
7E
B06
31
B07
32
B08
33
B09
34
B10
35
Bll
36
Bll'(*2) 73
B15
EO,48
B17
4F
B18
50
B19
51
B20
EO,lC
B20' (*2) 78
AOO
1D
A01
38
A05
39
A09
EO,38
A12
BO ,1D
A14
EO,4B
EO,50
A15
A16
EO,4D
A17
52
A17' (*2) 7e
A19
53

** F16key code mode (a) ; E1,lD,45,E1,9D,C5
mode (b) ; E1,14,77,E1,FO,14,FO,77
For U.S.1\.
For Europe

2-98

(*1) keys and (*2) keys are not installIed.
(*2) keys and (*3) key are not installed.

5D
EO,71
EO,69
EO,7A
6C
75
7D
79
6D
31
3A
41
49
4A
59
51
EO,75
69

5C
64
65
6D
6C
75
7D
7C
7B
31
3A
41
49
4A
59
51
63
69

72

72

7A
EO,5A
63
14

7A
79
78

II

19
29
39
58
61
60
6A

29
EO,ll
EO ,14
EO,6B
EO.72
EO,74
70
68
71

II

70

68
71

CHAPTER

3
OPTIONS

TAßlE OF CONTENTS

Section

Title

Page

CHAPTER
4

TROUBLESHOOTING

TABLE OF CONTENTS

Section

Title

Page

............................................

4.1

SERVICE TOOLS

4.2
4.2.1
4.2.2

TROUBLESHOOTING
How to use the POD (Power On Diagnostics)
How to use the MFG Board

4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.4

RESPONSE AND

INFOR~1ATION

4-2
4-2
4-2

FOR ERRORS

Outl ine

e.. •

•

•

•

•

•

•

4-1

4-5
•

• •

•

•

•

• •

•

•

•

•

• •

• •

•

• •

•

•

•

•

4-5

POD Funct ion s

4-5

Explanation of POD Functions
Specific Pattern in 34H to 3DH
Response and Information of Errors

4-5
4-6
4-6

LIST OF FIGURES

Fi gu re
4-1-1

Page

Title
Connection of Service Tools

4-1

LIST OF TABLES

Table
4-1-1
4-3-1

Title
Service Tool Listing
Responses and Information for Errors

Page
4-1
4-7

TROUBLESHOOTIBG

REV.A

4.1

Service Tools

Recornmended service tools are lis ted in Table 4-1-1 with corresponding EP SON
part numbers; these are also cornmercially available.

ATRPS UNIT

BOARD

FIGURE 4-1-1. CONNECTION OF SERVICE TOOLS
TAßLE 4-1-1.
TOOLS NO.

P ART NO.

SERVICE TOOL LISTING
DESCRIP TrON

ANT-MAC BOARD

B778601601

Expansion board for the main control board.

MFG BOARD

B77860170I

Bus status check board.

CABLE IIE207

B77860I80I

Expansion for CN3 of the ATRPS unit •

CABLE IIE208

B77860200I

Expansion for CN4 of the ATRPS unit.

CABLE IIE2I0

B77860200I

Expansion for DCI of the ATRPS unit.

CABLE IIE2II

B778602I0I

Expansion for DC2 of the ATRPS unit.

CABLE IIE2I2

B778602201

Expansion for CN3 of the ANTA board.

4-1

TROUBLESBOOTIBG

4.2

REV.A

TROUBLESHOOTING

The BIOS ROMs in the EQUITY 111+ / EPSON PC AX computer system are including a
diagnostic program which will perform the check for internal computer system
automatically.
We call the test program "POD" (Power On Diagnostics).
The POD will output ERROR MESSAGE to the CRT screen or eight LEDs on the MFG
Board if error is occurred in the EQUITY 111+ / EPSON PC AX computer system.
The error message will be useful at repair
probable cause by using this error message.
4.2.1

How to Use the

pon

because

we

can

determine the

(Power on diagnostics)

1. Connect a monitor and a MFG Board to the EQUITY 111+ / EPSON PC AX computer
system.
2. Turn the power switch of the EQUITY 111+ / EPSON PC AX. The POD will start
automatically and check internal circuits step by step automatically.
3. When error is occurred, the error message will appair on the monitor screen
or LEDs of the MFG board.
(The POD does not show good message when no error)
4. Search the 'RESPONSE AND INFORMATION FOR ERRORS' and find the corresponding
probable cause yourself.
4.2.2

How to Use the MFG Board

1. Function of the MFG board.
The MFG board is a service tool which can display data status (data bus
bit 0 to bit 7) on the eight LEDs.
This board can display data status of 1/0 address OOO(H) to FFF(H).
We can select the 1/0 address by using DIP switch.
2. How to set the DIP switch
Each switches of the DIP switch are corresponding
All as follows.

DIP
SWITCH
CORRESPONDING
ADDRESS

*

4-2

to address

SW2
8

7

All A10

bus AO to

SW1

6

5

4

3

2

1

4

3

2

1

A9

A8

A7

A6

A5

A4

A3

A2

Al

AO

When setting the DIP switch, please use following instance.

TROUBLESHOOTING

RKV.A

INSTANCE 1

DIP
SWITCH
CORRESPONDING
ADDRESS

In case of setting the DIP switch to 1/0 address 80H.

SWl

SW2
8

7

All A10

6

5

4

3

2

1

4

3

2

1

A9

A8

A7

A6

A5

A4

A3

A2

Al

AO

ON

ON

OFF ON

ON

ON

ON

ON

ON

ON

1

0

0

o

0

0

0

SETTING OF
THE DIP SW

ON

ON

VALUE OF
ADDRESS BUS

o

000

INSTANCE 2

DIP
SWITCH
CORRESPONDING
ADDRESS

0
(8)

( 0)

=080H

(0)

In case of setting the DIP switch to 1/0 address l77H.

SW2
8

7

All A10

5

4

3

2

1

4

3

2

1

A9

A8

A7

A6

A5

A4

A3

A2

Al

AO

ON

OFF ON

OFF OFF OFF

ON

OFF OFF OFF

1

o

1

SETTING OF
THE DIP SW

ON

VALUE OF
ADDRESS BUS

000

ON

(1)

SWl

6

1

o

1
(7)

1

1
(7)

1

=l77H

4-3

TROUBLESBOOn}l;

REV.A

3. How to use the MFG board
Instail the MFG board
system.

to

an

option

slot connector of the computer

4. Meaning of the LEDs

*

When the LED Iight t corresponding data bus is high status.

MFG BOARD

LED NO.
LED
LED
LED
LED
LED
LED
LED
LED

4-4

1
2
3
4
5
6
7
8

MEANING
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA

BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

7
6
5
4
3
2
1
0

TROUBLESHOOTIBG

REV.A

4.3
4.3.1

RESPONSE AND INFORMATION FOR ERRORS
Outline

The power on diagnostics (called POD) of EQUITY 111+ / EPSON PC AX ROM BIOS
diagnoses the system status held when EQUITY 111+ / EPSON PC AX is initiated
and takes action according to the status.
4.3.2

POD Functions

POD has the following four functions:
1; POD halts the system to disable initiation if
while checking system hardware.

POD detects

a serious error

2; If POD detects an error that is not fatal to the system, POD displays the
error message on the CRT screen and 1/0 address 80H. Then makes the system
wait for initiation until a specific key is pressed.
3; If a serious error occurs (refer to function 1), POD displays an error
message on the CRT screen in addition to 1/0 address 80H.
4; In reference to a non fatal error (function 2), POD skips the
input wait status.

4.3.3

specific key

Explanation of the POD Functions

1; Checking system hardware (serious error)
See the table 4-2. (Responses and information for errors)
2; Checking system hardware (not fatal)
See the table 4-2. (Responses and information for errors)
The specific key is the F1 key.
3; Displaying an error message on the CRT screen and 1/0 address 80H.
See the table 4-2.

(Responses and information for errors)

4; Skipping specific key input wait status
The key input wait request for an error specified in CMOS RAM 3EH and 3FH is
skipped if a specific pattern is defined in CMOS RAM 34H to 3DH.

4-5

TROUBLESBOOTING

4.3.4

HEV.A

Specific Pattern in 34H to 3DH

Pattern
Specification in 3EH and 3FH
Each bit has the meaning listed below. Input-wait operation
bit is O. Input-wait operation is allowed if a bit is 1.

is skipped

if a

- Meaning of each bit
Bit 0
Bit 1
Bit 2
Bit
Bit
Bit
Bit
Bit

3
4
5
6
7

RAM check error
CPU VIRTUAL test error (not occur in BIOS ROM Ver.1.02)
RTC error (corresponds to an error other than '163-time and date not
set')
RTC time error (corresponds to '163-time and date not set')
CRT DIP switch setting error or controller error
Keyboard error
FDD error
HDD error

- CMOS 3FH
Bit 0: X287 setting error (corresponds to '162-time system options not set')
Bit 1 : Key locked status
Others : Reserved (set to 1)
4.3.4

Response and Information of Errors

The table shows response and information related to errors detected by POD.
value is stored at 1/0 address 80H if continue is indicated for
operation.

An unfixed

4-6

t

*
*

*

Remove then reinsert or replace
BIOS ROM

Replace GAATIO

Replace RTC

Replace 8254

BIOS ROM

GAATIO

146818
(RTC)

8254
(Timer
counter)

04H

05H

06H

07H

08H

or

EXPLANATION

TIMER COUNTER CHECK (Refresh
function)
An error occurred during timer
counter 1.
-For 07H
(1 is written in each bit for of
the count register and counting
is started)
An error occurred when checking
that the all upper four bits of
the down counter become zero.

RTC REGISTER CHECK (Changing from
protect mode to real mode check)
An error occurred during RTC C-MOS
RAM area OFH check operation.
Checking is performed by setting
and verifying each bit
sequentially.
* RTC C-MOS RAM OF(H):
Shut down status byte

DMA PAGE REGISTER CHECK
An error occurred during DMa page
register check operation.

* BIOS ROM CHECK
An error occurred in BIOS ROM
check sum

* CPU CHECK
The protection enable (PF) bit in
the CPU machine status
ward (MSW) was 1 instead of o.
(MSW should be 0)

Remove then reinsert or replace
CPU

CPU

01H

80

SOLUTION

PROBABLE
CAUSE

RESPONSE MilD INFORMATION FOR ERRORS

PORT

TABLE 4-3-1.

None

None

None

None

None

ERROR MESSAGE
OUTPUT TO CRT

HALT

HALT

HALT

HALT

HALT

OPERATION

NEXT

~

§

I

>

t

11H
and
error
bit
pattern

OCH

or

OBH

OAR

or

09H

RAM

8237A5
(DMAC)

GAATrO

Replace RAM

Replace 8237 A5

Replace GAATI0

CHECK
during checking
RAM.
following data

(2) Error bit pattern (1 second)
(Upper byte)

(1) 11h(1 second)

* RAM (Base 64KB)
An error occurred
the base 64K-byte
LED indicates the
repeatedly.

DMA REGrSTER CHECK
-For OBH
An error occurred during
checking the DMA controller 1
register.
-For OCH
An error occurred du ring
checking the DMA controller 2
register.

*

REFRESH DEFECT BIT (r/o PORT)
CHECK
-For 09H
1/0 port 61H bit4 could not be
set to O.
-For OAR
r/o port 61H bit4 could not be
set to 1.
* r/o port 61H:
Refresh detect bit (Half of the
refresh signal frequency is
indicated by this bit)

*

HALT

HALT

Error bit pattern

000000 xxxx 201 HALT

None

None

----------------------------------------------------------------------------------------------------------

-For 08H
(0 is written in each bit of the
count register and counting is
started)
An error occurred when checking
that the upper four bits of the
down counter become 1.

>

g

~
~

~

~

~

t

xxxx

201

Error bit pattern

000000

In this case, the error bit
pattern is not indicated.
(Note)
An error message is also
displayed on the CRT screen. The
faulty RAM is detemined as folIows:

(3) OOR (1 second)

(2) OOR (1 second)

(1) llR (1 second)

(Example)
When Upper byte 00000000
Lower byte 00001000,
RAM corresponding to bit3 at
location ISA is faulty (When
ANT-RM circuit board unit number
Y12620300000 is used.)
If no error is detected during RAM
check but an error is detected
during parity check, LED indicated
error message as folIows:

DETEMING THE FAULTY RAM LOCATION.
The RAM corresponding to the bit
of which LED is on is faulty.

*

(3) Error bit pattern (1 second)
(lower byte)

~

§

~

~

~

>

;•

0

~

I

~

B
1101
C
1100

D
1110

HALT

None

Replace 8042 (8742)

8042
(8742)

18H

* DATA TRANSMISSION CHECK BETWEEN
KEYBOARD CONOROLLER AND CPU
The IBF bit in the 8042 (8742)
status register was not cleared
even though a fixed time elapsed
after a command was sent to the
8042 (8742) data bus buffer.
* The IBF bit in the 8042 (8742)
status register is on when the

HALT

None

Replace8042 (8742)* KEYBOARD CONTROLLER SELF-CHECK
The normal termination code (55H)
was not returned when the keyboard
controller seIftest program was
executed.
(Note)
The keyboard controller seIftest
differs from the keyboard unit
seIftest.

8042
(8742)

HALT

17H

None

Replace 8042 (8742)* KEYBOARD CONTROLLER REGISTER CHECK
The IBF bit in the 8042 (8742)
status register was not cleared
even after a fixed time elapsed.
* If the IBF bit is on, the 8042
(8742) data bus buffer contains
data. This IBF bit is automatically
cleared by the 8042 (8742)
internal probram.

8042
(8742)

16H

RAMs corresponding to bits 1, 2,
3,6,7,8,10, ll, 13 and 15 are
faulty.

A
1010

(Example)
When the error bit pattern is ADCE:

.>~

~
~

~

Cf)

~

t-'

tt-'

25H

I
I

23H

22H

8259

GAATIO

Rep lace 8259

Replace GAATIO

INTERRUP CONTROLLER AND INTERRUP T
MASKING CHECK
For 23H:
An error was detected in the
interrupt mask register of the
master interrupt controller.
Checking is done writing and
verifying 00 and FF in the
interrupt mask register.
For 24H:
An error was detected in the
interrupt mask register of the
slave interrupt controller.
Checking is the same as the
explained for 23H.

*

101-System
board error

* DMA PAGE REGISTOR CHECK
106-System
An error was detected while
board error
checking the access to DMA page
register (83, 84H)
Folling two check operations are
performed:
(1) 55AAH is written as data in
above port.(83,84H) The data is
read by and the written data with
read data.
(2) 55AAH is written in avobe (83,84H)
port byte mode.
Then written data is read, and the
written data is compared with the
read data.
This error is indicated if the
written data was not equal to the
read data.

data bus buffer contains command
or data.
The IBF bit is
automatically cleared by the 8042
(8742) internal program.

HALT

HALT

i

~

~

~

~

5>

m

N

~

I

~

28H

8254-2
8259A-2

8259A-2

or

27H

8254-2

26H

Rep1ace 8254-2 or
8259A-2

8259A-2

Rep1ace 8254-2 or

TIMER COUNTER INTERRUPT CHECK
This error is indicated if a
counter 0 interrupt set by the
operation exp1ained for 27H does
not occur at 200usec or after
200usec.

*

* TlMER SPEED CHECK
An error was detected in timer
controller counter O.
For 26H:
It is set so that interrupt
occurs after 60usec from the
start of counter.
This error is indicated if an
interrupt does not occur during
the 90usec from the start of
counter.
For 27H:
It is set so that an interrupt
occurs after 200usec from the
start of counter.
This error is indicated if an
interrupt occurs du ring the 150
usec from the start of counter.

For 25H:
An interrupt occurred even though
all bits in the interupt mask
register were on.
Checking is done in the fo110wing
order:
-FFH is set in the interrupt
mask registers of the master and
slave interrupt controllers.
-Whether an interrupt is
ckecked by software STI command.

103-System
board error

102-System
board error

HALT

HALT

~

&.

~

~

~
~

t

'w"'"

Replace 8042 (8742)

Replace the RAM,
GAATIO, or option
board

Replace 8254

KEYBOARD CONTOLLER STATUS
REGISTER CHECK
The IBF bit in the 8042 (8742)
status register was not cleared
even after a fixed time elapsed.
* Checking is done in the same way
as l6H.

*

* NMI CIRCUIT CHECK
This error is indicated if an NMI
occurs during the next 400us after
NMI is allowed.
During the 400usec, CPU does not
access to RAM. So, if this error
is occured NMI circuit has problem.
(Ref) NMI occurs under one of the
following conditions:
(1) A RAM parity check error occurs.
(2) An 1/0 channel error occurs.

TIMER COUNTER 2 CHECK
55AAH is written in timer
controller counter 2, the counter
is read, and the written data is
compared with the read data.
This error is indicated if the
written data is not equal to the
read data.

*

lOS-System
board error

lOS-System
board error

108-System
board error

HALT

HALT

HALT

CPU

Remove them reinsert or replace
CPU

* ADDRESS LINE (A19 TO A23) CHECK
The protection enable (PE) bit in
THE CPU MACHlNE STATUS WARD (MSW)
REGISTER WAS TURNED ON BUT THE BIT
WAS OFF WHEN VERIFIED.

None

HALT

----------------------------------------------------------------------------------------------------------

2EH,
36H,
OR
3BH

----------------------------------------------------------------------------------------------------------

8042
(8742)

RAM,
GAATIO
option
board

2BH

2CH

8254-2

2AH

~

G
§

~

>

;•

~

~

....I

( 38H)
Unfixed
value

32H

or

31H

RAM

GAATM1
GAATM2

Replace RAM

REPLACE GAATM1 OR
GAATM2

None

202-Momory
* RAM SIZE CHECK
One of the following errors was
address error
detected during the checking of
the RAM size:
(1) Bad RAM
(2) A parity error
* An error address and error bit
pattern are displayed on the CRT
screen.
(1) If a bad RAM is detected:
An error address and an
error bit pattern are displayed
on the CRT screen as folIows:
xxxxxx **** 202-Memory address error
xxxxxx Error address

(2) OOOOH is written in the
following addresses:
080000
100000
200000
400000
800000
(3) When the data stored in
address 000000 is FFFFH, address
lines A19 to A23 are detemined as
normal.
If value of address 000000 is not FFFFH,
address line (A19 to A20) has problem.

000000

* ADDRESS LINE (A19 TO A23) CHECK
An error occurred while checking
address lines 19 to 23.
*Checking address lines method.
(1) FFFFH is written in address

CONTINUE

HALT

.>~

~

§

~

~

~

t

I.n

(3AH)

Unfixed
value

* ADDRESS LINE (A16 TO A23) CHECK
One of the folowing errors was
detected during checking the
address line:
(1) Address line (A16 to A23) error
(2) Parity error

203-Memory
address error

--- Parity check 1 or 2
1: RAM parity error (Internal circuit)
2: 1/0 channel parity error
(Extension Memory card)
xxxxxx ---- Error address
0000 ---- All zeros are displayed

(Address)
If an address from OOOOOOH to
07FFFFH is indicated, there is an
error in the 256K-bit RAM on the
ANT-RM circuit board.
If an address from 080000H to
09FFFFH is indicated, there is an
error in the 64K-bit RAM on the
ANT-RM circuit board.
If an address from 100000H to
FDFFFFH is indicated, there is an
error in the RAM on the option
slot.
(Pattern)
This is same as the one
explained for 11H.
Please see "Note" in the item 11H.
(2) For a parity error
Data is indicated on the CRT
screen as foliows:
xxxxxx 0000 202-Memory address error

CONTINUE

~

~

§

~

~

>

~.

0'1

tI-'

(3FH)

keyboard unit or
8042 (8742)

Replace the

Keyboard
Replace the
unit,
Keyboard,
8042(8742),8042(8742), or
or ANTA
ANTA circuit board
circuit
board

(3EH) Keyboard
Unfixed unit or
value 8042
(8742 )

Checking address lines

304-keyboard
or System
Unit error

* KEYBOARD INTERFACE CIRCUIT CHECK
30 I-KEYBOARD
Before this check, the POD execute
error
keyboard unit self-test. Next, the
POD execute keyboard interface circuit
check. When keyboard interface circuit
has no error, this error will indicate.

* KEYBOARD CLOCK CHECK
The TO bit (indicating the clock
sent from the keyboard) of the
test input port in 8042 (8742) was
not turned low.

a) Check data is written in the RAM
specified at the start address of
block (64K bytes) as shown in the
above figure.
b) The written data is verified
after the data is written in all
of the blocks.
c) This error is indicated if an
error is detected du ring
verfication explained in b.
* An error address and read data are
displayed on the CRT screen.
* Error message explantion
(1) Address line error
xxxxxx **** 203-Memory address error
xxxxxx ---- Error address
**** ---- Read data (Not accordant data)
xxxxxx **** 203-Memory address error
-- Parity check 1 or 2
1: RAM parity error (Internal circuit)
2: 1/0 channel parity error (Extension
Memory card)

*

CONTINUE

CONTINUE

.s
>

!

~

!
~
§

.....

,...I

.t:'-

(42H) DJP
Unfixed switch
value setting

Set the DIP
switch correctly.

8042
Rep lace 8042
(3FH)
Unfixed (8742)
(8742)
value

* CRT SLIDE SWITCH SETTING CHECK
The slide for setting the monitor
did not match with the mounted
video card.
If 40l-CRT error is displayed on
the CRT screen t the monochrome
monitor was set by the switch but
the video card indicated the color
monitor.
If SOl-CRT error is displayed on
the CRT screen t the color monitor
was set by the switch but the
video card indicated the
monochrome monitor.

40l-CRT error
or
SOl-CRT error

INTERFACE CIRCUIT CHECK
303-CRT error
This error is indicated if a
or System unit
response to the interface line
error
test command output du ring keyboard
interface circuit check (explained in
the previous section) is not returned
or the response indicates an error.

* KEYBOARD

SOt when this error message is indicated.
In this case t the code output repeatedly
is displayed on the CRT screen.
This error is also indicated if a
code is output repeatedly from the
keyboard.

CONTINUE

CONTINUE

~

I

~
~

>

~

....00t
CONTlNUE

161-System
CONTlNUE
options not set

101-System

Replace RTC
(146818)

(42H) RTC
Unfixed (146818)
value

TIME AND DATE CHECK
This error is indicated if the RTC
control register was read but
processing did not enter update in
progress status, or updqte in
progress status could not be
cleared.

*

* RAM SIZE CHECK
This error is indicated if the
value in the mounted RAM differs
from RTC setting.

CONTINUE

CONTINUE

163-Time & Data CONTlNUE
not set

164-Memory
size error

* FDD CHECK
601-Diskette
(1) An error was returned when FDC
1) Replace FDD
error
was reset (INT 13H reset
2) Mount one or
both of the SPFG
function).
and WHDC circuit (2) FDD was normally reset (as a
result of the above checking) but
boards if it was
not mounted.
an error was returned during head
seek test (only drive A was
3) Replace the
checked).
SPFG or WHDC
circuit board
(3) A card equivalent to IBM COMBO
card did not install(the error
and perform 'setoccurs if SPFG or WHDC circuit
up'
board is missing).

P ref orm set t ing
correctly

(43H) FDD,
Unfixed SPFG
value circuit
board,
or WHDC
circuit
board

* RTC POWER FAlLURE CHECK
RTC power failure was detected.
This error is indicated if the VRT
bit in RTC (146818) control
register D is O.

* RTC SETTING CHECK AND RTC CHECK-SUM CHECK
An error occurred in RTC check sum
162-System
CONTINUE
Replace or
correctly set RTC
or the RTC contents did not match
options not set
with the mounted hardware.
(146818)
and perform 'set-up'

Replace the
lithium battery
and perform
'set-up'

(42H) Setting
Unfixed error
value

(42H) RTC
Unfixed (146818)
value setting
error

(42H) Lithium
Unfixed battery
value

>

;

~
§
~

~

t\C

I

ol:l-

Replace the HDD
or WHDC circuit
board

(45H) HDD or
Unfixed WHDC
value circuit
board

HDD CHECK
The hard disk could not be recalibated.
* lf 1780-disk 0 failure is
displayed on the CRT screen, the
CMOS data in RTC is rewritten and
IPL from HDD is disabled.45H

*

* HDC SELF TEST CHECK
An abnormal code was returned
during hard disk controller
selftest.
1780-Disk 0
failure
1781-Disk 1
failure

1782-disk
controller
failure
CONTINUE

CONRINUE

P erf orm set t ing
correctly

CYLINDER, MAX HEAD, MAX SECTOR
1790-Disk 0
READ CHECK
error
This error is indicated if the POD
1791-Disk 1
can not read the Max. sector of the
error
Max.track which is determined by CMOS.

* MAX

CONTINUE

Rep lace ROM chip

First ; long beep
Second ; short beep

BEEP

* 1/0 ROM CHECK
xxxxO ROM
When the POD detect a 1/0 ROM ID,
error
the POD execute check-sum for the
1/0 ROM.
This error message will be indicated
on the screen of the CRT.
 23
Minutes > 59
seconds > 59

----------------------------------------------------------------------------------------------------------

.~>

~

~

~
~

I

.p-

""'"

N

Pari ty check 1
80000
(S)
(S) Segment
A parity error occurred in the
segment placed at address 80000
or later.

~

§

~

~
~

&.

;

CHAPTER

5
DISASSEMBLY AHD ASSEMBLY

TAßLE OF CONTENTS
Section

5.1
5.1.1
5.1. 2
5.1.3
5.1.4
5.1.5
5.1.6
5.1. 7
5.1.8
5.1.9
5.1.10
5.1.11
5.1. 12
5.1.13
5.1. 14
5.1. 15
5.1.16
5.1.17
5.1.18
5.1. 19
5.1. 20

~1AIN

Title

Page

UNIT DIASSEt1BLY AND ASSH1BLY

5-1
5-1
5-1

Upper Case Removal ................•....................
Upper Case Rep 1acement •••••••••••••••••••••••••••••••••
Front Panel Removal ••••••••••••••••••••••••••••••••••••
Front Panel Replacement
..
Power Supply Unit (ATRPS Unit) Removal •••••••••••••••••
Power Supply Unit (ATRPS Unit) Replacement
.
Optional Circuit Board Removal •••••••••••••••••••••••••
Optional Circuit Board Replacement •••••••••••••••••••••
Disk Drive (HDD or FDD) Removal ••••••••••••••••••••••••
Disk Drive (HDD or FDD) Replacement ••••••••••••••••••••
ANT-~1 Circuit Board Removal •••••••••••••••••••••••••••
ANT-RM Circuit Board Repl acement
..
~1ain (ANTA) Circuit Board Removal
.
t1ain (ANTA) Circuit Board Replacement ••••••••••••••••••
ANT-tn Circuit Board Removal
..
ANT-HT Circuit Board Replacement
..
ANT-LS Circuit Board Removal •••••••••••••••••••••••••••
ANT-LS Circuit Board Replacement
..

5-2
5-2
5-3
5-3
5-4
5-4

5-5

Speaker Replacement ••••••••••••••••••••••••••••••••••••

5-5
5-6
5-6
5-7
5-7
5-8
5-8
5-9
5-9
5-10
5-10

5.2
5.2.1
5.2.2

KEYBOARD UNIT DISASSD1BLY AND ASSEMBLY •••••••••••••••••••
Key Cyl inder Unit Removal
Key Cylinder Unit Replacement ••••••••••••••••••••••••••

5-11
5-11
5-11

5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6

POWER SUPPLY UNIT (ATRPS) DISASSEt1BLY AND ASSn1BLY .......
Secondary-side Circuit Board Removal •••••••••••••••••••
Secondary-side Circuit Board Replacement •••••••••••••••

5-12
5-12
5-13

Speaker Removal

.

Fan Unit Removal

5-14

Fan Unit Replacement •••••••••••••••••••••••••••••••••••
Primary-side Circuit Board Removal •••••••••••••••••••••
Primary-side Circuit Board Replacement •••••••••••••••••

5-14
5-15
5-15

LIST OF FIGURES

Fi gure
5-1-1
5-1-2
5-1-3
5-1-4
5-1-5
5-1-6
5-1-7
5-1-8
5-1-9
5-1-10
5-2-1
5-3-1
5-3-2
5-3-3

Title
Upper Case Rernoval/Replacement
Front Panel Removal/Replacement
Power Supply Unit Removal /Repl acement
Optional Circuit Board Removal/Replacement
Disk Drive Removal/Replacement
ANT-ro1 Circuit Board Removal/Replacement
ANTA Circuit Board Removal/Replacement
ANT-t1T Circuit Board Removal/Replacement
ANT-LS Circuit Board Removal/Replacement
Speaker Removal/Replacement ..........•...................
Key Cylinder Unit Removal/Replacement
Secondary-side Circuit Board Removal/Replacement
Fan Unit Removal/Replacement
Primary-side Circuit Board Removal/Replacement

Page
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-14
5-15

RHV .A

MAn, URIT DISASSEMBLY Alm ASSEMBLY

5.1
5.1.1

1.
2.
3.
4.

DIASSEHBLY AHn ASSEHBLY

Upper Case Removal

Unlock the key (B) to remove the upper case (A).
Remove the four screws (C) from the rear.
Slide the upper case forward.
Remove the upper case by opening the side section (1) in the direction
indicated by the arrows.

(A)
(B)

FIGURE 5-1-1.
5.1.2

1.
2.
3.
5.

-)

lPP ER CASE Rml>VALlREPLACEMENT

Upper Case Replacement

Fit the upper case over the Iower case.
Slide the upper case to the rear.
Replace the four screws (C) at the back.
Lock the upper case if required.

5-1

DIASSEMBLY AND ASSEMBLY

5.1.3

HEV.A

Front Panel Removal

1. Remove the upper case.
2. Remove the four screws (A) to remove the front panel.

(Al

(B)

FIGURE 5-1-2.

5.1.4

FRORT PAREL REMOVAL/RFPLACEMERT

Front Panel Replacement

1. Replace the front panel by attaching the four screws (A).
2. Replace the upper case.

5-2

RKV .A

5.1.5

DIASSEMBLY AND ASSEMBLY

Power Supply Unlt (ATRPS UBIT) Removal

1. Remove the upper ease.
2. Remove the two ANT-MT Board eonneetors (B), and the FDD and HDD power
suppIy eonneetors.
4. Remove the four serews (C) from the rear.
5. Slide the power suppIy unit (D) about 6 em towards the front to elear the
hold-down tabs and remove the unit.

FIGDRE 5-1-3.

5.1.6

POWER ·SUPPLY UBIT REtIlVAL/REPLACEMEBT

Power Supply Unit (ATRPS UBIT) Replacement

1. RepIaee the power suppIy unit by sliding it toward the rear over the holddown tabs on the Iower ease.
2. Fasten the power suppIy unit with the four sere~lS (C).
3. Replaee the two ANT-MT Board conneetors (B), and the FDD and HDD power
suppIy eonneetors.
4. Replaee the upper ease.

5-3

DIASSEMBLY AND ASSEMBLY

5.1.7
1.
2.
3.
4.

REV.A

Optiona! Circuit Board Remova!

Remove the upper case.
Disconnect the cab1es attached to the optional circuit board, if required.
Remove screw (A) which holds the board to the Iower case.
Remove the board by firmIy grasping the edge at both ends and pulling
directIy upwards.

(Al

F'IGURE 5-1-4.

5.1.8
1.
2.
3.
4.

5-4

OP TIONAL CIRCUIT BOARD REMOVALlREPLACEMENT

Optiona! Circuit Board Rep!acement

Insert the optional circuit board into the ANT-MT Board connector slot (B).
Fasten the board with screw (A).
Replace the cable connections.
Replace the upper ease.

REV .A

5.1.9
1.
2.
3.
4.

DIASSEKBLY AND ASSEKBLY

Disk Drive (HOD or FOD) Removal

Remove the
Disconnect
Remove the
Remove the
case.

upper case.
the signal and power supply cables on the rear of the unit.
two side screws (A) fastening the drive.
drive unit by sliding it carefully out the front of the lower

(B)

(A

FIGDRE 5-1-5.
5.1.10

DISK DRIVE REMOVAL/REPLACEMERT

DISK DRIVE (HOD or FOD) Replacement

1. Place the slider (B) at the left (to mount the drive horizontally) or at
the bottom (to mount the drive vertically) and attach the drive to the
lower case.
2. Fasten the drive with the two screws (A).
3. Connect the signal and power supply cables to the drive.
4. Replace the upper case.
(Note 1)

Arrange the signal and power supply cables, then fasten the
cables with the clamp attached to the po\'ler supply unH.

5-5

DIASSKMBLY AN» ASSKMBLY

5.1.11

HEV.A

ART-RH Circuit Board Removal

1. Remove the upper ease.
2. Remove the serew (B) fastening the ANT-RH board (A) to the Iower ease.
3. Remove the ANT-R}[ board by grasping the edge at both sides and pulling
direetIy upwards.

A

FIGURE 5-1-6.
5.1.12

B

ART-RH CIRCUIT BOARD REHOV ALlREPLACEMENT

ART-RH Circuit Board Replacement

1. Insert the ANT-RM board in the ANTA board eonnector slot (C).
2. Fasten the ANT-R}! board to the IO\ler ease w,ith the sereu (B).
3. Replaee the upper ease.

5-6

REV .A

5.1.13

DIASSEMBLY AND ASSEHBLY

Hain (ARTA.) Cireuit Board Removal

1.
2.
3.
4.
5.

Remove the upper case.
Remove the ANT-ml circuit board.
Remove the foul' screws (D) fastening the ANTA board (C) to the lower case.
Disconnect the ANTA board connector (F).
Open the tabs (E) of the ANTA board towards the sides and slide the ANTA
board out 7 01' 8 cm towards the front.
6. Disconnectg the ANTA board connector (G).
7. Pull the ANTA board out all the way to remove it.

(F)

(B)

(H)

--

FIGURE 5-1-7.

5 .1.14

(El

-

ANTA CIRCUIT BOARD REt«>V ALlREPLACEMENT

Hain (ANTA) Cireuit Board Replacement

1. Hold the ANTA circuit board (C) level and slide it horizontally toward the
real' until about 8 cm of clearance remains.
2. Replace the connector (G) on th~ ANTA board.
3. Slide the ANTA board horizontally to firmly seat i t into the ANT-l1T board
connector (H).
Note: Make sure that no cables are held between the ANTA and AJ1T-MT boards.
4. Replace the ANTA board connector (F).
5. Replace the ANT-m: board.
7. Replace the upper case.

5-7

DISASSEMBLY AND ASSEMBLY

5.1.15
1.
2.
3.
4.
5.
6.

REV.A

ART-MT Circuit Board Removal

Remove the
Remove all
Remove the
Remove the
Diseonneet
Remove the
and remove

upper ease.
optional eireuit boards.
ANT-mt board.
ANTA board.
the two eonneetors (A).
five serews (C) fastening the ANT-MT board (B) to the lower ease
the ANT-MT board.
(C)

(B

FIGURE 5-1-8.

5.1.16
1.
2.
3.
4.
5.
6.

5-8

ART-MT CIRCUIT BOARD REKOV ALlREPLACEMENT

ART-MT Circuit Board Replacement

Replaee
Connect
Replaee
Replaee
Replaee
Replaee

the
the
the
the
the
the

ANT-MT board and fasten with the five serews (C).
two eonnectors (A).
ANTA board.
ANT-r~ board.
optional eireuit boards.
upper ease.

DISASSEMBLY AHn ASSEMBLY

REV .A

5.1.17

ANT-LS (LKD) Circuit Board Removal

1. Remove the upper case.
2. Disconnect connector CN6 on the WHDC circuit board.
3. Remove the ANT-HM board and disconnect the connector (A) from the ANTA
circuit board.
4. Disconnect the connector (B) from the speaker cable.
s. Disconnect the connector (D) from the case lock switch cable (C).
6. Remove the screws (F) fastening the ANT-LS circuit board (E).
7. Remove the ANT-LS board.

(G) (D)
(F)

(Al
(C)

FIGURE 5-1-9.
5.1.18

(El

(B)

ANT-LS CIRCUIT BOARD REMOVAL/REPLACEMENT

ANT-LS Circuit Board Replacement

1. Replace the ANT-LS board (E) and fasten with the screws (F).
2. Pass the cable for the connector (A) through the hole (G) toward the main
ci rcuit board.
3. Connect the connector (A).
4. Connect the connectors (B) and (D).
S. Replace the ANTA and ANT-IDI boards.
6. Connect connector CN6 of the WHDC circuit board.
7. Replace the upper case.

5-9

REV.A

DISASSEKBLY ABO ASSEKBLY

5.1.19
1.
2.
3.
4.

Speaker Removal

Remove
Remove
Remove
Remove

the
the
the
the

upper ease.
speaker eonneetor (A) frorn the ANT-LS board.
serew (C) fastening the speaker to the mounting board.
speaker.

Cl
(Al

FIGUBE 5-1-10.
5.1.20

SPEAKER REMOVAL/REPLACEMENT

Speaker Replacement

1. Replaee the speaker on the mounting board tdth the serew (C).
2. Conneet the speaker eable to the eonneetor (A) on the ANT-LS board.
3. Replaee the upper ease.

5-10

RKV .A

5 .2

KEYBOARD UNIT DISASSEMBLY AND ASSEMBLY

5.2.1

1.
2.
3.
4.

DISASSEMBLY AND ASSEMBLY

Key Cylinder Unit Removal

Remove the
Disconnect
Remove the
Remove the

upper case.
the connector (B) from the case lock switch cable (A).
screws fastening the key cylinder unit mounting plate.
key cylinder unit mounting plate.

(Bl

(Al

FIGURE 5-2-1.

5.2.2

KEY CYLINDER UNIT REMOVALlREPLACEMENT

Key Cylinder Unit Replacement

1. Fasten the key cylinder rnounting plate with the screws.
4. Connect the connector (B) to the ANT-LS board.
5. Replace the upper case.

5-11

DISASSEMBLY AND ASSEMBLY

5.3

REV.A

POWER SllPPLY UHIT (ATRPS) DISASSEMBLY ARD ASSEMBLY

5.3.1.

Secondary-side Circuit Board Removal

1. Remove the five screws (A) to remove the cover (B).
2. Remove the four screws (C).
3. Pull up the secondary-side circuit board (D) 5 cm and disconnect the fan
connector (E).
4. Remove the cable clamp (F) in the following order:
(1) Hold the cable clamp (F) and rotate the clamp so that the cut
section of clamp 1S mated with the cut section of the power supply
case.
(2) Remove the cut section of the cable clamp.
(3) Remove the cable clamp.
5. Remove the cables (G) along the cut section of the power supply case to
remove the secondary-side circuit board.
(Bl

(Al

(0)

(F

FIGDRE 5-3-1.

5-12

SECONDARY SIDE CIRCUIT BOARD RKKOVAL/REPLACKMKRT

REV .A

5.3.2

DISASSKMBLY AND ASSKMBLY

Secondary-side Circuit Board Replacement

1. Replace the cable clamp (F) on the cable (G).
Hold the cut section of the cable clamp so that it will not come off.
2. Insert the thinner section of the cable clamp in the hole on the power
supply case.
3. Connect the connector (E) to the secondary-side circuit board CD).
4. Fasten the secondary-side circuit board with the four screws (C).
5. Fasten the cover (B) with five screws (A).

5-13

DISASSEMBLY AND ASSEMBLY

5.3.3

REV.A

Fan Unit Removal

1. Remove the secondary-side circuit board.
2. Rernove the four screws (A) to rernove the fan unit.
(A)

FIGURE 5-3-2.

5.3.4

FAN UNIT REMOVALlREPLACEMENT

Fan Unit Replacement

1. Fasten the fan unit (B) with the four screws (A).
2. Replace the secondary-side ci.rcuit board.

5-14

RKV .A

5.3.5

DIASSEMBLY AND ASSEMBLY

Primary-side Circuit Board Removal

1.
2.
3.
4.

Remove the secondary-side circuit board.
Remove the fan unit.
Remove the t~lO connectors (D).
Remove the five screws (C) fastening the primary-side circuit board and
remove the screws (E) fastening the two cables connecting the AC outlet.
5. Slide the primary-side board horizontally to remove the board.

(E)

(A)

(C)

FlGUKE 5-3-3.
5.3.6

PRIHARY-SIDE CIRCUIT BOARD REMOVAL/RPPLACEKENT

Primary-side Circuit Board Replacement

1. Replace the primary-side circuit board by sliding in horizontally.
2. Fasten the primary-side board with the five screws (C).
3. Fasten the two cables connecting the AC out let to the primary-side board
with the screws (E).
4. Connect the two connectors (D).
5. Replace the fan unit.
6. Replace the secondary-side circuit board.

5-15

CHAPTER

6
ADJUSTMENT AHD MAINTENANCE

TAßLE OF CONTENTS

Section

Title

Page

CHAPTER

7
DIAGRAMS AHD REFERENCE MATERIALS

TAßlE OF CONTENTS

Section

Title

Page

7.1
7.1.1
7.1.2

SLIDE SWITCH & JUMPER CONNECTOR SETTINGS
Slide Switch Settings ....•.............................
Jumper Connector Settings •....................•........

7-1
7-1
7-2

7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8

GATE ARRAY DESC RIPTION

7-6
7-6
7-8

7.2.9
7.2.10

.

GAATAB .•...•..•••...•.•.••..•..••.••.••....•••.•.•.••••
GAATCB .....•..•••..••...•.••..•....••••..••••••......••
GAATDB ••••..••••..••••••••.••••••••••.••••••••••••.••••
GAATCK •••••••.••••.•.••••••••••••••.•••••.•••••••••••••
GAATM2 ..•.•..•.•...•.••...•....•..•...•...••••...•••.••

GAATIO •..••....••....••...•....•••....•....•.•..•....••
GAATMl •••.•..............•.•...•••..•••.•..••••..•.••.•
GAATRF .• •.•.••...••..•.•.•......•••..•••.•....••••••..•.
GAATSP .••.•••.•••••••••.•••••.•••••••••••.•••••••••••••

GAATFD •...•.••••...•...••..••....••••...•••...•..••••.•

DIAGNOSTICS PROGRAf.1

7-10
7-12
7-15
7-16
7-18
7-21
7-24
7-26
7-28

LIST OF FIGURES

Figure
7-1-1
7-1-2
7-1-3

Title

Page

Slide Switch Setting
Va1ume Adj ustmen t
Jumper Connectars

7-1

7- 1
7-2

LIST OF TAßlES

Table
7-1-1
7-1-2
7-1-3
7-1-4
7-1-5
7-1-6
7-1-7

Title

Page

Hain (ANTA) Board Jumper Connections
7-2
Factory Settings (Main ANTA Board)
7-3
System Memory (ANT-RM) Board Jumper Connetions
7-3
Factory Settings (ANT-~1 Board)
7-4
HDD Controller (WHCD) Board Jumper Connections
7-4
Factory Settings (WHDC Board)
7-4
~1ulti -Function Adapter (SPFG) Board Jumper Connections..
7-5

7-1-8
7-2-1
7-2-2
7-2-3
7-2-4
7-2-5
7-2-6
7-2-7
7-2-8
7-2-9
7-2-10
7-2-11
7-2-12
7-2-13
7-2-14

Factory Settings (SPFG Board) ...........................
GAATAB Pin Arrangement · .................................
GAATAB Pin Description ·.................................
GAATCB Pin Arran gemen t ·.................................
GAATCB Pin Description · .................................
GAATDB Pin Arrangement ·.................................
GAATDB Pin Description ·.................................
GAATCK Pin Arrangement ·.................................
GAATCK Pin Description ·.................................
GAAH12 Pin Description ·.................................
GAATIO Pin Description ·.................................
GAATM1 Pin Description ·.................................
GAATRF Pin Description · .................................
GAATSP Pin Description ·.................................
GAATFD Pin Description ·.................................

7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-15
7-16
7-18
7-21
7-24
7-26

REV .A

7.1

DIAGRAMS AND REFERENCE MATERIALS

SLIDE SWITCH & JUMPER CORRECTOR SETTINGS

Slide Switch Settings

7.1.1

Monitor Select Switch
MONO : Monochrome Monitor
COLOR: Color Monitor

(Factory setting)

CPU Speed Select Switch
6
8

10

6 r-filz

8 MHz
10 MHz

(Factory setting)

OFF

ON

I

I

1-=11 1c.=J1

MONO COLOR
MONITOR SELECT

FIGURE 7-1-1.

LLJ
6

8

10

CPU SPEED

SLIDE SWITCH SETTINGS

Volume Adjustment
Turn clockwise to increase the volume.
Turn counter-clockwise to decrease the volume.

/~
VOLUME

FIGURE 7-1-2.

VOLUME ADJUSTMENT

7-1

REV.A

DIAGRAMS AND REFERENCE MATERIALS

7.1.2

JUMPER CONNEC'l'OR SETnNGS

Jumper Connectors
Jumper connectors provide a means to make a semi-permanent selection of a
particular operational function, for instance, the 'A' or 'B' function in Fig.
7-1-3 (1), where 'c' is the common terminal. If a jumper connection i8 called
'A-C', the jumper 1s connected as in configuration '2' in Fig. 7-1-3.
If a
jumper connection is called 'B-C', the jumper is connected as in configuration
'3' in Fig. 7-1-3.

FIGURE ]-1-3.

JUMPER CONNEC'l'ORS

Hain (ANTA) Board Jumper Connections
TABLE ]-1-1.

J6

Jumper
J5 J4

*
*
*
*
*
*
*
*
A-C

*
*
*
*
*
*
*
*
A-C

A-C B-C
E-C A-C
B-C B-C

* *
* *
* A-C
* A-C
* B-C
* B-C
A-C *
B-C *
* *
* *
* *
* *

Legend:

7-2

Number
J3 J2

*
**

*
*
A-C
B-C
A-C
B-C

*
*
*
*
*
*

MAllf (ANTA) BOARD JUMPER CONNECnONS

Function
Jl
A-C
E-C

*
*
*
*
*
*
*
*
*
*

Set CPU clock mode 6/8/10
Inhibit
Inhibit
Input CPU clock as NPX clock (1/3)
Input 8 MHz as NPX dock
Inhibit
2 wait cycles for EPROM access **
1 wait cycle for EPROM access **
4 ,..ait cycles for ext. 16-bit device
3 wait cycles for ext. 16-bit device
2 wait cycles for ext. 16-bit device
1 wait cycle for ext. 16-bit device

Not Applicable
Hait cycles available at 10 MHz operation

access
access
access
access

**
**
**
**

DIAGRAMS AN» REFERENCE MATERIALS

REV.A

Factory Settings (Main ARTA Board)
TABLE 7-1-2.
Jumper
Number

FACIDRY SETTINGS

Factory
Setting

]"-C
A-C.
B-C
A-C)
]"-C
A-C

J1
J2
J3
J4
J5
J6

(MAlB ARTA BOARD)

Function

>
>
>
>

Input CPU clock as
NPX clock
2 wait cycles for EPROM access
4 vlait cycles for external
16-bit device access

System Memory (ART-RH)
TABLE 7-1-3.

SYSTEM MEMORY (ART-RH) BOARD JUMPER CONNECTIONS

J7

Jumper
Number
J6 J5 J4 J3 J2

*
*
*
*
*
*
*
*
*
*
*
*
A-C

*
*
*
*
*
*
*
*
*
*
*
*
A-C

*
*
*
*
*
*
*
*
A-C

*
*
*
*
*
*
*
*
A-C

A-C B-C
B-C A-C
B-C B-C

*
*
*
*

*
*
*
*

Legend:

+

A-C B-C
B-C A-C
B-C B-C

=

J1

Function

640KB Memory
512KB Memory

A-C
A-C
A-C
A-C
B-C
B-C
B-C
B-C

A-G
A-C
B-C
B-C
A-C
A-C
B-C
B-C

A-C
B-C
A-C
B-C
A-C
B-C
A-C
B-C

*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*

256KB Memory

OOOKB (disable all RAM)
27128
27256 EPROM size
Select ROM pair 24].. and 24B
Select ROM pair 23A and 23B

Not Applicable
Inhibited

7-3

DIAGRAKS AHn REFERENCE MATERIALS

Factory Settings

HEV.A

(ANT-RH Board)
TABLE 7-1-4.

Jumper
Number

Factory
Setting

J1
J2
J3
J4
J5
J6
J7

A-C
A-C
A-C
B-C
B-C
A-C
A-C

FACTORY SETTINGS (ANT-RH BOARD)

Function

>
>
>
>
>
>
>

64üKB
Memory
Size
27256 EPROM
Memory Size
Select ROM socket
pair 24A and 24B

Hard Disk Controller (WHDC)
TABLE 7-1-5.

HOD CONTROLLER (WHDC) BOARD JUMPER CONNECTIONS

Jumper Number
J3
J2
J1

*
*
*
*
B-C

*
*
B-C
A-C

A-C

*
*

Factory Settings

Function

B-C
A-C

Select primary address sets
Select secondary address sets
Non-latched status (LED)
Latched status (LED)
WAR mode
WA2 mode

*
*
*
*

(WHDC Board)
TABLE 7-1-6.

7-4

Jumper
Number

Factory
Setting

J1
J2
J3

f.,-C

B-C
B-C

FACTORY SETTINGS (WHDC BOARD)

Function

Secondary address sets
Non-latched status
\1AR mode

DIAGRAMS AND REFERENCE MATERIALS

REV.A

Multi-function Adapter (SPFG)

TABLE 7-1-7.

J8

J7

*
*
*
*
*
*
*

*
*
*
*
*
*
*

*
*
*
*
*
*
*
A-C
B-C

J6

MULTI-FUBCTIOR ADAPTER. (SPFG) BOARD JUMPER CONRECTIORS

Jumper
J5 J4

*
*
*
*
*
*
*
* *
* A-C
B-C
* A-C
* B-C
*
A-C *
B-C *
* *
* *

*
*
*
*
*
*
*
*
A-C
A-C
B-C
B-C

*
*
*
*

Factory Settings

Number
J3 J2

*
*
*
*
A-C

*
*
*
*
A-C

Jl

JI0 J9

Function

A-C
A-C
B-C
B-C

A-C
B-C
A-C
B-C

*
*
*
*
*
*
*
*
*
*
*
*

*
*
*

*
*
*
*
A-C

Primary register set (3FO-3F7) AT:FDC
Secondary regis. set (370-377) AT:FDC
PC register set (3FO-3F7) : FDC
Disable FDC register set
Primary parallel I/F (378-37F) :IRQ 7
Secondary paral. I/F (278-27F):IRQ 5
Parallel I/F on video adapter
( 3BC-3BF) : IRQ 7
Disable parallel I/F
Primary serial I/F (3F8-3FF) : IRQ 4
Secondary serial I/F (2F8-2FF):IRQ 3
Disable serial I/F
Disable serial I/F
AT drive I/F
EQUITY-3 drive I/F
Standard configuration
Test mode of VCO

B-C A-C
A-C B-C
B-C B-C

*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*

J1
J2
J3
J4
J10
J5
J6
J9
J7
J8

*
*
*
*
*
*
*
*
*

*

A-C
B-C

*
*
*
*
*
*

(SPFG Board)
TABLE 7-1-8.

Jumper
Number

*
*
*
*
*
*
*
*
*

B-C
A-C

*
*
*
*
*
*
*

FACTORY SETTIRGS (SPFG BOARD)

Factory
Setting

A-C
A-C
A-C
A-C
A-C
A-C
A-C
A-C
A-C
A-C

Function

>
>
>
>
>
>
>
>

Primary register
set of AT
Primary
parallel
I/F
IRQ 7
Primary
serial
I/F : IRQ 4
AT drive I/F
Standard configuration

7-5

DIAGRAMS AND REFERENCE MATERIALS

7.2

REV.A

GATE ARRAY DESCRIP TION

7.2.1

GAATAB

GAATAB controls the CPU address bus, system address bus and the internal
address bus. I t has an 8-bit refresh counter.
TABLE 7-2-1.
SIGNAL
NAME
1/0*

TESTN
ALP.
Al
AZ
A3
XAO
XAl
LSAO
XAZ
XA3
SAO
SA1
SA2
SA3
SM
GNDA
GNDB
SAS
SA6
SA7
SA8
XA4
XAS
XA6
OP.-N
XA7
A4
A5
A6
A7
A8
Vcc

*

7-6

Legend:

I
I
I
I
I
Tri
Tri
I
Tri
Tri
Tri
Tri
Tri
Tri
Tri.
Tri
Tri
Tri
Tri
Tri
Tri
Tri
I
Tri
I
I
I
I

I
0
Tri

J

PIN
NO.

1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

GAATAB P IN ARRANGEMENT
PIK
NO.

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1/0*

I
I
I

I
Tri
Tri
T

Tri
Tri
Tri.
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
I
Tri
I
I
I
I
I
I

SIGNAL
NAME

Vcc
A16
Al5
A14
Al3
XA16
XA15
DXA
XA14
XA13
XA12
SA16
SA15
SA14
SAl3
GNDB
GNDA
SA12
SAH
SA10
SA9
XAll
XA10
XA9
R590N
XA8
A12
All
A10
A9
G590N
C590

Input P in
Output P in
Tri-state Pin (Input, Output, High-impedance)

REV .A

DIAGRAMS AND REFERENCE MATERIALS

TABLE ]-2-2.
SYMBOL

1/0*

A16-1

I

LSAO

I

SA16-0

Tri

XA16-0

Tri

I

63-60,38-35,
31-27,5-3
8
53-50,47-44
21-18, 15-11
59,58,56-54,
43-41,39,26,
24-22,10,9,
7,6
2
25

I

DXA

I

57

C590

I

33

G590N

I

34

R590N

I

40

TESTN

I

1

*

NAME AND FUNCTION

PIN NO.

ALE
OEN

Legend:

I

o
Tri

GAATAB PIN DESCRIPTION

CPU address bus.
Converted address O.
It is identical to CPU
address 0 (AO), except when word to byte
conversion is being performed.
System address bus.
Internal address bus.

Address latch enable. A16-1 are latched by ALE.
Enable control of latched address (A16-1). When
low, LSAO and latched A16-1 are enabled.
Direction control of internal address bus(XA160) buffer. When high XA16-0 are driven by SA160, and when low SA16-0 are driven by XA16-0.
Clock of refresh counter.
Refresh counter
increments at C590 rising edge.
Outpu t enable of refresh counter.
When low,
refresh address is placed on SA7-0.
Reset on refresh counter.
When low, refresh
counter is cleared.
Test input. Should be pulled up.

Input Pin
Output P in
Tri-state Pin (Input, Output, High Impedance)

7-7

REV.A

DIAGRAHS AND REFERENCE MATERIALS

7.2.2

GüTeB

GAATCB controls the CPU control bus and the most significant 7 bits of the
address bus. Contains one inverter, one NOR gate and one NANO gate.
TABLE 7-2-3.
SIGNAL
NAME

1/0*

GSA-N
I
DLA
I
ALE
I
OE-N
I
RFMRN
I
RFC-N
I
BHE
I
I
MIO
SBHE
Tri
SMIO O&H-Z
XBHE
Tri
(NC)
Tri
LA17
LA18
Tri
LA19
Tri
GOOA
GOOB
LA20
Tri
LA21
Tri
LA22
Tri
LA23
Tri
A17
Tri
Tri
A18
Tri
A19
(NC)
A20
Tri
Tri
A21
(NC)
Tri
A22
Tri
A23
(NC)
Vcc

*

Legend:

I

o
Tri
O&H-Z

PIN
NO.

GAATeB PIN ARRANGEMENT
PIN
NO.

1/0*

1

64

2

63

I

3
4

62
61
60

o

59
58

o

5
6

7
8
9

10
11

12
13

57
56
55
54
53

52
51

14
15
16
17
18
19
20
21
22
23

43
42

24

41

25
26
27
28
29
30
31
32

40
39
38

50

I
I
I
I

000

I
I

DXR\~

Tri
Tri
Tri
Tri

49
47

45

44

O&H-Z
O&H-Z
O&H-Z
O&H-Z
O&H-Z

GSRWN
IOW-N
IOR-N
MEMRN
MEMWN
GNDB
GOOA
8A17
SA18
8A19
SMR-N
SMW-N
(NC)
(NC)
(NC)
(NC)

Tri

XIO\m

Tri
Tri
Tri

XIORN

37
36
35
34
33

Vcc
Vi
VO
NRI2
NDl1
NRO
NDIZ
OOll

o

48

46

SIGNAL
NAME

(NC)
XMW-N
XMR-N
(NC)

Input P in
Output P in
Tri-state Pin (Input, Output, High-impedance)
Output & High-impedance Pin

----....;;...---~-~---------------

7-8

DIAGRAMS AHn REFERENCE MATERIALS

REV .A

TABLE 7-2-4.

SYMBOL

1/0*

A23-17

Tri

PIB NO.

30,29,27,26,
24-22
SA19-17 O&H-Z 45-47
LA23-17
l
21-18,15-13
BHE
SBHE
XBHE
MIO
SHIO
IOWN
lORN
MEMHN
MEHRN
XIOWN
XlORN
XMWN
XMRN
SMWN
SHRN
DLA

I

Tri
Tri

7
9

I

11
8

O&H-Z
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
O&H-Z
O&H-Z

10
53
52
50
51
38
36
35
34
43
44

I

2

GSAN

I

1

ALE

I

3

OEN

I

4

DXRW

I

55

GSRWN

I

54

RFMRN

I

5

RFCN

I

6

VI

I
T
l
I

VO

NDIl
NDI2
NDO
NDIl

o
I

63
62
57
58
56
60

GAATCB PIB DESCRIPTIOB

NAKE AND FUBCTIOB

CPU address bus.
System address bus. (8-bit connector).
Unlatched system address bus.
(16-bit
connector).
CPU bus high enable signal.
System bus high enable signal. (16-bit
connector).
Internal bus high enable signal.
CPU memory / 1/0 signal.
Buffered memory / 1/0 signal.
System 1/0 write signal. (8-bit connector).
System 1/0 read signal. (8-bit connector).
System memory write signal (16-bit connector).
System memory read signal (16-bit connector).
Internal 1/0 write signal.
Internal 1/0 read signal.
Internal memory write signal.
Internal memory read signal.
System memory write signal (8-bit connector).
System memory read signal (8-bit connector).
Direction control of CPU address bus (A23-17)
buffer. When high, LA23-17 are driven by A2317. And when low A23-17 are driven by LA23-17.
Enable control of address bus (SAI9-17) buffer.
When low, SA19-17 are driven by AI9-17.
Address latch enable.
A19-17 and MIO and BHE
are latched by ALE.
Enable control of latched address (A19-17), MIO
and BHE. When low, SA19-17 are driven by latched
A19-17.
When low, SMIO and SBHE are driven by
latched MIO and BHE, respectively.
Direction control of CPU control bus.
When
high, XIOWN, XIORN, XNWN and XNRN are driven by
IOWN, IORN, MEMWN, and HE}ffiN respectively. When
low, IOWN, TORN, MEMWN and MEMRN are driven by
XIOWN, XIORN, XMWN, and XHRN respectively.
Enable control of SMWN and SMRN. When 10\., SHWN
and SMRN are enabled.
Memory read pulse of refresh cycle.
RFMRN is
used in conjunction with RFCN signal.
Refresh enable. When low, MEMRN, XMRN and SMRN
are driven by RFMRN.
Input of inverter.
Output of inverter.
Input of NAND gate.
Input of NAND gate.
Output of NAND gate.
Input of NOR gate.

7-9

DIAGRAMS AND REFERENCE MATERIALS

NDI2
NOR

I

61
59

0

*

Legend:

Input of NOR gate.
Output of NOR gate.
Input P in
Ouput P in
Tri-state Pin (Input, Output, High-impedance)
Output and High-impedance P in

I
0

=

Tri
O&H-Z
7.2.3

REV.A

GAAmB

GAATDB has two data bus buffers (system data bus buffer and memDry data bus
buffer) and a low to high byte conversion buffer.
TABLE 7-2-5.
SIGNAL
NAME

DO
D1
D2
D3
MDO
MD1
DMD
GMDHN
GMDLN
MD2
MD3
SDO
SD1
SD2
SD3
GNDA
GNDB
SD4
SD5
SD6
SD7
MD4
MD5
MD6
D245
G245N
MD7
D4
D5
D6
D7
Vcc

*

Legend:

I

o
Tri

7-10

1/0*

Tri
Tri
Tri
Tri
Tri
Tri
I
I
I
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
I
I
Tri
Tri
Tri
Tri
Tri

GAAmB PIN ARRANGEMENT

PlIi

PIN

11).

11) •

1
2
3
4
5
6
7
8
9
10

11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1/0*

Tri
Tri
Tri
Tri
Tri
I
I
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
I
I
I
Tri
Tri
Tri
Tri
Tri
Tri

SIGNAL
NAME

Vcc
D15
D14
Dl3
D12
MD15
CBA
SBA
MD14
~1Dl3

MD12
SD15
SD14
SDl3
SD12
GNDB
GNDA
SDll
SD10
SD9
SD8
MD 11
HDlO
DD
GDH-N
GDL-N
MD9
MD8
Dll
DlO
D9
D8

Input P in
Output P in
Tri-state Pin (Input, Output, High-impedance)

REV .A

DIAGRAMS AHn REFERENCE MATERIALS

TADLE 7-2-6.
SYMBOL

1/0*

D15-0

Tri

MD15-0

Tri

SD15-0

Tri

PllI

NAME AND FUBCTIOB

!K).

DD

I

63-60,31-28
4-1,33-36
59,56-54,43,
42,38,37,27,
24,23,22,11,
10,6,5
53-50,47-44
21-18,15-12
41

GDHN

I

40

GDLN

I

39

CBA

I

58

SBA

I

57

DMD

I

7

GMDHN

I

8

GMDLN

I

9

D245

I

25

G245N

I

26

*

Legend:

I

o
Tri

GAA'IDB PIB DESCRIPTIOB

CPU data bus.
Memory data bus.

System data bus.
Direction control of CPU data bus(D15-0) buffer.
When low, CPU reads data from MD15-0 or SD15-0.
Enable control of CPU data bus high byte (D15-8)
buffer. When low, it enables high byte.
Enable control of CPU data bus low byte (D7-0)
buffer. When low, it enables low byte.
Read data latch. SD7-0 are latched at CBA rising
edge.
SBA selects latched or un-latched data. When
high, latched data are selected. SBA is used in
conjunction with CBA signal.
Direction control of Memory data bus (HD15-0)
buffer. When high Memory data is read.
Enable control of Hemory data high byte (MD15-8)
buffer. When low, it enables high byte. GMDEN
is used in conjunction with D~ID signal.
Enable control of Hemory data low byte (MD7-0)
buffer. When low, it enables low byte. GHDLN is
used in conjunction with DMD signal.
Direction control of low to high byte conversion
buffer. When low, it indicates high to low byte
conversion during data transfers to 8-bit
peripherals (write). When high, it indicates low
to high byte conversion during data transfers
from 8-bit peripherals (read).
Enable control of low to high byte conversion
buffer. It is active low signal and is used in
conjunction with D245 signal.

= Input P in
= Output P in

Tri-state Pin (Input, Output, High-impedance)

7-11

DIAGRAMS AND REFERENCE MATERIALS

7.2.4

REV.A

GAATCK

GAATCK includes following functional blocks.
(1) Clock generator
CPU dock, 80287 dock, System clock,
DMA clock, 8042 dock,
8254 dock,
NTSC dock (14.31818 MHz)
(2) Ready circuit
(3) Reset circuit
(4) Bus controller
HEMR, MEMW, lOR, lOW, lNTA, ALE, DTR, DEN
(5) Shut down circuit
TABLE 7-2-7.
SIGNAL
NAME

1/0*
,..•

_,_..

C14M
I
HLDA
I
Al
I
RSWN
I
RSWP
I
PWGD
I
(NC)
(NC)
(NC)
ENAS
0
DTR
0
ACKN
0
EALE
0
RSDV
0
CLKO
0
GNDA
GNDB
MEHR O&lI-Z
MEMW O&H-Z
ALE
0
lNTA O&H-Z
DCLK
0
RDY
0
(NC)
(NC)
RC
I
HSTR
I
HlO
I
Sl
I
SO
I
C20M
I
Vcc

*

7-12

Legend:

GAATCK PIR ARRANGEMENT

PIR

PIR

JIiI) •

JIiI) •

_~--_.~._--,.

1
2
3
4
5
6
7
8
9
10
11

12
13

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

-----.

--._.-.~.,,---

..

SIGNAL
1/0*

----.----.._._.-

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

I
I
I
I
I

0
0
0
0
0
0
0
0
O&H-Z
O&lI-Z
0
0
0
0

I

I
I

I
I

Input Pin
I
0
= Output Pin
O&H-Z
Output & High-impedance P in

NAME

Vcc
C48H
COFF
CDLY
CSPDO
CSPD1
(NC)
(NC)
RSN
C1M
EMEMR
DEN
BALE
AEN
SCLK
GNDB
GNDA
OSC
lOR
IOW
PCLKP
PCLKN
RSCPU
C8H
(NC)
(NC)
(NC)
SRDY
ARDY
AREN
TEST
CLKI

REV .A

DIAGRAMS AHn REFERENCE MATERIALS

TABLE 7-2-8.

SYMBOL

C48M
C20M
C14M
PCLKP
PCLKN
OSC
CIM
C8M
DCLK
SCLK
CLKO
CLKl
CSPDI
CSPDO

1/0*

NAME AND FUNCTION

PU NO.

I
I
I

63

o
o
o
o
o
o
o
o

44
43
47
55
41
22
50
15

I

33

I
I

59
60

Clock input. 48 MHz.
Clock input. 20 MHz.
Clock input. 14.31818 MHz.
(+) KB controller (8042) clock. 6 MHz.
(-) KB controller (8042) clock. 6 MHz.
Clock output. 14.31818 MHz. (for option slot)
Clock output. 1.19 MHz. (for 8254)
Clock output. 8 MHz, duty 33%. (for 80287)
DMA CLOCK
System clock.
CPU clock output.
CPU clock input. CLKl should be connected to
CLKO externally.
CPU clock select.
CPU clock select.

31
1

CSPDI CSPDO

o
1
1

o
pweD

I

6

RSWN

I

4

RSWP

I

5

RSN
RSDV
AREN

o
o
I

56
14
35

ARDY

I

36

SRDY

I

37

RDY
MIO

o

23
28

SI
SO

I
I

I

30

o
o
o

SI
0
0

1
1

o
o

SCLK
6 MHz
8 MHz
10 HHz
12 MHz

CLKO
12 MHz
16 MHz
20 HHz
24 MHz

CLKl
12 MHz
16 MHz
20 MHz
24 MHz

DCLK
3 MHz
4 MHz
5 MHz
6 MHz

Power good. When low, it indidates that power is
not good and reset signals (RSN, RSDV, RSCPU)
are activated.
(-) Reset switch activation signal. RSWN becomes
low.
(+) Reset switch activation signal. RSWP be comes
low.
(-) Reset signal. (for internal circuit)
(+) Reset signal. (for option slot)
(-) Asynchronous ready and synchronous ready
enable.
(-) Asynchronous ready input. It is used in
conjunction with AREN signal.
(-) Synchronous ready input. It is used in
conjunction with AREN signal.
(-) Ready output.
Memory or 1/0 select. When low, the current bus
cycle is in the r/o space.
Bus cycle status.
Bus cycle status.

29

MIO

GAATCK PIN DESCRIPTION

so
o
1

1

o

o

1

1

1

0

o

Type of bus cycle
INTA
10 READ
10 WRITE
NONE, IDLE
HALT OR SHUT DOWN

7-13

DIAGRAHS AHn REFERENCE MATERIALS

1
1

o
1

o

1

1

1

I

62

CDLY

I

61

HLDA

I

2

ALE
DEN
DTR

o
o
o

MEHR

O&H-Z
O&H-Z
O&H-Z
O&H-Z
O&Il-Z

MEMW

IOR
IO\-l

INTA
EHEHR
EALE
BALE
MSTR

o
o
o

20
11

18

19
46
45

21
54
13

52
27

ACKN

o

12
51
3

AEN

o

Al

I
I

RSCPU

o

26
42

ENAS

o

10

TEST

I

34

*

(+) Control off. When high, command and DEN
signal are forced inactive.
Command delay. When high, the start of command
output is delayed.
Hold acknowledge. When high, command output
becomes 3-state off.
Address latch enable.
Data bus enable.
Data transmit/receive. "!hen high, this control
output indicates that a write bus cycle is being
performed.
(-) Hemory read command.
(-) Hemory write command.
(-) 1/0 read command.
(-) 1/0 write command.
(-) Interrrupt acknowledge.
(-) Early memory read signal.
Early address latch enable.
Buffered address latch enable.
(-) Haster. A processor or DHA controller on the
1/0 channel may pull this signal low.
(-) Acknowledge. \l.Then low, mtA controller (or
refresh controller) has control of the address
bus, data bus and control bus.
(+) Address enable.
Address 1.
(-) Reset CPU input from 8042.
(+) Reset CPU output. When high, CPU is reset.
RSCPU becomes active when:
(1) P~?GD is low·.
(2) Reset switch is activated.
(3) 8042 pulls RC signal low.
(4) CPU executes shutdown cycle.
(-) Enable control of RTCAS (RTC address strobe)
signal.
(-) Test input. TEST should be pulled high.

53

I

Re

MEHORY READ
MEMORY WRI TE
NONE, IDLE

1

COFF

Legend:

0
I

O&H-Z

7-14

REV.A

Output
Input
Output & High-impedance Pin

REV .A

7.2.5

DIAGRAMS AND REFERENCE MATERIALS

GAA'l'M2

GAATM2 generates memory address and RAS, CAS, WE signals used witb GAATM1 and
tbe delay line to control DRAM.
TADLE 7-2-9.

SYMBOL

1/0*

PIX NO.

SA18-0

I

MA8-0

o

HEMR
HEMW
EMRN
XMWN
RFHN
D40
D80
D160
D200
RA1
RAO
CAR
CAL
RAS1
RAS0
CASH

I
I
I
I
I
I
I
I
I
I
I
I
I

o
o
o

3,5,6,13-16,
18,20-24,
27-32
44,43,41,40,
9-7 ,12,11
61
62
46
63
64
52
50
48
47
35
37
38
39
59
60
56

CASL

o

55

WE
RAS

o
o

45
53

TEST

I

54

* Legend:

GAA'l'M2 PIN DESCRIPTION
NAME AND FUNCTION

System address bus.
DRAM address bus.
(-) System memory read signal.
(-) System memory write signal.
(-) Early memory read signal.
(-) Internal memory write signal.
(-) Refresb signal.
40 ns delayed signal from RAS.
80 ns delayed signal from RAS.
160 ns delayed signal from RAS.
200 ns delayed signal from RAS.
(+) RA1 signal is used to generate RAS1 signal.
(+) RAO signal is used to generate RASO signal.
(+) CAR signal is used to generate CASH signal.
(+) CAL signal is used to generate CASL signal.
(-) Row address strobe for DRAM (80000H-9FFFFH).
(-) Row address strobe for DRAM (OH-7FFFFH)
(-) Column address strobe for DRAM (OH-9FFFFH,
odd byte).
(-) Column address strobe for DRAM (OH-9FFFFH,
even byte).
(-) Write enable signal for DRAM.
(+) RAS is generated from logical OR of MEMR and
HEMW.
This output is used to generate delay
signals (D40, D80, D160, D200)
(-) Test input. TEST should be pulled up.

I = Input Pin
Ouput Pin

o

7-15

DIAGRAMS AN» REFERENCE MATERIALS

7.2.6

REV.A

GAATIO

GAATIO includes following functional blocks.
(1) Address decoder of 1/0 space.
(2) D~~ page register (741S612 compatible)
(3) Port B.
(4) ~~I enable register.
(5) Address latch for D~.
(6) Interface circuit between NP (80287) and CPU (80286).
(7) General purpose gates.
--- 1 inverter, 1 NANO gate, two 3-state buffers.
TABU 7-2-10.

SYMBOL

1/0*

XD7-0
A23-17

Tri
O&H-Z

XA16-10 O&H-Z
XA9-8
XA7-1
XAO
XIWN
XIRN
RSTN
DK7N
DK6N
DK4N
DK3N
DK2N
DKON
DAK4

Tri
I
I

I
I
I
I
I
I
I

RFHN

I
I
I
I

ACKN

I

STB2

I

STB1

I

AEN2
AEN1
AE02

I
I
0

AE01

0

MSTN

I

7-16

PIB NO.

GAATIO PIN DESCRIPTION

NAME AND FUNCTION

38-31
Internal data bus.
66,68,70,72, CPU address bus.
74,76,80
77,75,73,71, >
69,67 ,64
>
62,63
> Internal address bus.
61-55
>
52
>
12
(-) Internal 1/0 write signal. (= -XIOW)
(-) Internal 1/0 read signal. (= -XIOR)
11
30
(-) Reset.
-DACK7. D~~ acknowledge 7.
21
20
-DACK6. D~~ acknowledge 6.
19
-DACK4. D~~ acknowledge 4.
18
-DACK3, D~ acknowledge 3.
17
-DACK2. D~ acknowledge 2.
16
-DACKO. D~ acknowledge O.
14
+DACK4. This signal is output.
85
(-) Refresh signal.
(-) D~ acknowledge. ACKN is active when DMA or
86
refresh cycle is being performed.
26
(+) DHAC-N02 (16-bit D~ controller) address
strobe signal.
27
(+) DMAC-N01 (8-bit DMA controller) address
strobe signal.
22
(+) Address enable signal of D~C-N02.
23
(+) Address enable signal of DMAC-N01.
96
(-) AE02 is active when D~~C-N02 has control of
the system.
97
(-) AE01 is active when D~C-N01 has control of
the system.
87
-t~STER. When low, it indicates that the master
on the option slot (DMAC or CPU on the slot) has
the control of the system.

DIAGRAMS AND REFERENCE MATERIALS

REV.A

ITAN
SMIO
NERN
NBSN
Q1
ENAS
CD2N
CD1N
CI2N
CIlN
CTMN
CKBN
RTRW
RTDS
RTAS

100
88

I
I
I
I
I
I

8
7

89
98
24
25
42
41
47
99
44
45
46

DXD

o
o
o
o
o
o
o
o
o
o
o
o
o
o

43
39

NMI
SPEK
TM2G

o
o
o

10
51
48

ENPR
IOEN
OUT2

o
o

81
92
49

PCKN
VI
VO
NA II
NAZI
NAnO
TS20
TSI
TSO
TSVI
TSVO

I
I

NPRS

NCSN
CBSN
IR13

6

5
9

I

o

82
84
83
95
94
93

O&II-Z

91

o
I
I

1

I

O&H-Z
I

2
13

O&H-Z

50

*

-INTA. Interrupt acknowledge.
Memory or 1/0 select.
(-) NP (80287) error.
(-) NP (80287) busy.
Q1 is a timing signal to generate RTAS signal.
(-) Enable control ot RTAS signal.
(-) Chip select of D~~C2 (8237).
(-) Chip select of DMAC1 (8237).
(-) Chip select of INTC2 (8259).
(-) Chip select of INTC1 (8259).
(-) Chip select of system TIMER (8254).
(-) Chip select of keyboard controller (8042).
(-) Write signal of real time clock (HD146818).
(-) Read signal of RTC (HD146818)
(+) ALE signal of RTC (HD146818).
(+) NP (80287) reset signal.
(-) Chip select ~w (80287).
(-) CPU (80286) busy signal.
(+) Interrupt request 13.
Direction control of 8 bit internal data bus
(XD7-0) buffer.
(+) Non-maskable interrupt request.
Output signal for speaker.
Time r CH2 gate. This signal is connected to
channel 2 gate input of timer LSI (8254).
(+) Enable RAM parity check.
1/0 channel error (option slot).
Timer CH2 output. This signal is connected to
channel 2 output of timer LSI (8254).
(-) Parity check error.
Input of inverter.
Output of inverter.
Input of NAND gate.
Input of NAND gate.
Output of NAND gate.
Output of 3-state buffer.
Enable control (active low) of 3-state buffer.
Output of 3-state buffer.
Enable control (active low) of 3-state buffer.
Output of 3-state buffer.

Legend:

I

o
Tri
O&l1-Z

Input P in
Ouput Pin
Tri-state Pin (Input, Output, High-impedance)
Output & High-impedance P in

7-17

REV.A

D1AGRAKS AND REFERENCE MATERIALS

7.2.7

GAATMI

GAATM1 includes the following functional blocks.
1. Address decoder for ROM and DRAM
2. Parity checker / generator
3. Additional circuitry for the memory expansion card
(This circuit is not used in EQUITY 111+ / EPSON PC AX.)
TABLE 7-2-11.

SYMBOL

A23-17
RFHN
XAJ

1/0*
I
I
I

PIN No.

3-9
17
2

ALE

I

HI1)A

I

XMRN
XBHE
XAO

I
I
I

JRAH

J

15
16
14
18
19
60

JRAL

I

59

JEFN

I

56

JEO

I

57

JROM

I

55

J1MN

I

28

GAATMI P1N DESCRIPTION

NAME AND FUNCTION

CPU address bus.
(-) Refresh signal.
ROM address select. XA16 or XA15
connected to XAJ. ROM address range:

XAJ

X.A16

XAJ

XA15

should be

CSFN

CSEN

OFOOOO-OFFFFF
FFOOOO-FFFFFF

OEOOOO-OEFFFF
FEOOOO-FEFFFF

OFOOOO-OF7FFF
OF8000-0FFFFF
FFOOOO-FF7FFF
FF8000-FFFFFF
(OE8000-0EFFFF) (OEOOOO-OE7FFF)
(FE8000-FEFFFF) (FEOOOO-FE7FFF)

(+) Address latch enable.
(+) Hold acknowledge.
(-) Internal memory read signal.
Internal bus high enable signal.
Internal address bus o.
(+) Enable control of RAM from 080000H to
09FFFFH.
(+) Enable control of RAM from 040000H to
07FFFFH.
(-) RAM address select. When low t RAM address is
assigned from FOOOOOH to F9FFFFH. Th is input
should be high or open in EQUITY 111+ / EPSON PC
AX.

(+) RAM address select. When high t RAM address
is assigned from OOOOOOH to 09FFFFH. This input
should be high or open in EQUITY 111+ / EPSON PC
AX •

7-18

(+) Enable control of ROM. When high t ROM is
enabled. This input should be high or open in
EQUITY III+ / EPSON PC AX.
(-) Chip select input for memory expansion card
which uses 1Mbit RAM chips. This input should be
high or open in EQUITY 111+ / EPSON PC AX.

DIAGRAMS AND REFERENCE MATERIALS

REV.A

JKN

I

25

RA23

I

23

D40

I

24

LMGN

0

10

CRON

0

CRAN

0

CSFN
CSEN
RA1

0
0
0

12
11
53
54
64

RAO

0

63

CAR

0

62

CAL

0

61

RS3N

0

31

RS2N

0

30

DHD
MA9

0

0

13
29

DM15-0
HP01

I
I

48-33
50

MPOO

I

52

MPIl

0

49

HPIO

0

51

EPR1

I

21

EPR2

I

22

PCKN

0

20

ERON

O&I1-Z

32

(-) Chip select input for memory expansion card
which uses 256Kbit RAH chips. This signal should
be high or open in EQUITY 111+ / EPSON PC AX.
(+) Timing input for RS3N and RS2N. (When GAATMl
is used in memory expansion card.) This signal
is not used in EQUITY III+ / EPSON PC AX, and
should be high or open.
40 ns delayed signal from RAS. (When GAATM1 is
used in memory expansion card.) This signal is
not used in EQUITY III+ / EPSON PC AX, and
should be high or open.
(-) Chip select of low order 1Hbyte memory
space. LMGN is active when memory space from
OOOOOOH to OFFFFFH is accessed.
(-) ROM chip select.
RAM chip select.
(-) Read signal of BIaS ROM.
(-) Read signal of reserved ROM.
(+) RA1 signal is used to generate RAS1 signal
in GAATM2.
(+) RAO signal is used to generate RASO signal
in GAATM2.
(+) CAR signal is used to generate CASH signal
in GAATM2.
(+) CAL signal is used to generate CASL signal
in GAATM2.
(-) Row address strobe for DRAM. (When GAATM1 1s
used in memory expansion card.) This signal is
not used in EQUITY 111+ / EPSON PC AX.
(-RAS2) Row address strobe for DRAM. (When
GAATM1 is used in memory expansion card.) This
signal is not used in EQUITY 111+ / EPSON PC AX.
Direction control of memory data bus buffer.
Dynamic RAM address 9. (When GMTM1 is used in
memory expansion card.) This signal is not used
in EQUITY III+ / EPSON PC AX.
Memory data bus.
Parity bit of odd address byte. MP01 is paritychecked with MD15-8 in memory read cycle.
Parity bit of even address byte. MPOO is paritychecked with }ID7-0 in memory read cycle.
Parity bit of odd address byte. MPIl is
generated from ~ID15-8 in memory write cycle.
Parity bit of even address byte. MPIO is
generated from MD7-0 in memory write cycle.
(+) Enable RAM parity check. When high, parity
check circuit is enabled. And when low, parity
check circuit is cleared.
(-) Enable RAM parity check. This signal 1s not
used in EQUITY 111+ / EPSON PC AX, and should be
pullec1 down.
(-) Parity error signal. When low, it indicates
that parity error has occurred.
(-) Parity error signal. 3-state output. This
signal is not used in EQUITY III+ / EPSON pe /IX.

7-19

DIAGRAMS AHn REFERENCE MATERIALS

*

Legend:

I

o
O&H-Z

HEV.A

Input P in
Output Pin
Output & High-impedance Pin

In EQUITY 111+ / EPSON pe AX the following signals are not used.
INPUT
JEFN JEO JROM JIMN JKN RA23 D40
high or open
EPR2
low
OUTPUT
RS3N RS2N MA9 ERON
no connection

]-20

DIAGRAMS AND REFERENCE MATERIALS

REV.A

7.2.8

GAATRF

GAATRF includes the following functional blocks.
1. DRAM refresh control circuit.
2. DHA control circuit.
3. 16 <--> 8 data conversion circuit.
4. Wait states insertion circuit.
5. Command delay control circuit.
6. XAO, XBHE control circuit.

TABLE 7-2-12.

SYMBOL

1/0*

PIN NO.

~.,rSO

I

15

WS1

I

40

GAATRF PIN DESCRIPTION

NAME AND FUNCTION

Zero wait insertion. When low, wait state is not
inserted. -OWS signal of option slot is
connected to this pin.
Wait states control of BIOS-ROM access.
The number of wait states of BIOS-ROM (OEOOOOOFFFFF, FEOOOO-FFFFFF) is controlled by WS1.
CSPD

WS1

0 (10 MHz)
0
0 (10 HHz)
1
1 (6 or 8 MHz)

*

WS2

I

39

WS3

I

38

Wait states
2
1
1
(* : don' t care)

WaU states control of 16-bit memory devices on
the option card which activates -MEMCS16 signal.
CSPD
0
0
0
0

(10 ~mz)
(10 MHz)
(10 MHz)

~VS3

WS2

0
0

0

4

1

1
1

0

3
2
1
1

(10 MHz)
1 (6 or 8 MHz) *

1

* (*

Wait states

don't care)

I

44

CPU address bus O.

I
I
I
I

11
7
8
9

I
I

10
12

I

48

CSRO

I

47

M16

I

17

(+) Address latch enables.
(-) System memory read signal.
(-) System memory write signal.
(-) System 1/0 read signal.
(-) System 1/0 write signal.
(-) Interrupt acknowledge.
(-) Chip select signal of internal DRAM (009FFFF) •
(-) Chip select signal of internal ROM (OEOOOO--OFFFFF, FEOOOO-FFFFFF).
(-) Chip select signal of 16-bit memory devices
on the option siot. (-MEMCS16 signal of option
siot is connected to this pin.)

AO
ALE
MEMR
MEMW
IOR
IOW
INTA
CSRA

7-21

DIAGRAMS AN» REFERENCE MATERIALS

1016

I

18

IRDY

1

61

NPCS

1

45

CSPD

1

52

REV.A

(-) Chip select signal of 16-bit 1/0 devices on
the option slot. (-10CS16 signal of option slot
is connected to this pin.)
(+) 1/0 channe] ready signal. (+10CHRDY signa]
of option slot is connected to this pin.)
(-) Chip select signal of numeri cal processor
(80287) •
CPU speed select.
CSPD

o
1

Q1

o

2

ARFY

o
o
o

25
16
60

AREN
COFF

LSAO
AEN1
AEN2
DAEN
XAO
XBHE

o

23

1
1

43

o

42
32

Tri
Tri

49
35

CPU speed
10 MHz
6 or 8 MHz

(+) Q1 signal is active from phase 2 of first Tc
cycle to phase 1 of last Tc cycle.
(-) Asynchronous ready.
(-) Asynchronous ready enable.
(+) Control off. This signal becornes active
during 16 <--) 8 conversion. Hhile COFF is
active, control signals (-}1ENR, -MEMW, -IOR,lOH) are disabled.
Latched and converted address O.
(-) DNA channel 1 (8-bit DMA) address enahle.
(-) D~ffi channel 2 (16-bit D~~) adress enable.
(-) mffi enable. (channel 1 and channel 2)
Internal address bus O.
Bus high enable.
- AEN1
1

DEN
DTR

1
1

4

GDL

o

57

GDH

o

56

G245

o

54

D245

o

55

MI0

1

14

CDLY

o

59

5

- AEN2
XAO
XBHE
1
input
input
o
1
input
-XAO (output)
1
0
0 (output)
o (output)
(+) Data bus enable.
Data transmit ot receive. \lIhen high, data is
transmitted from CPU to memory or 1/0.
(-) Enable control of CPU data hus low byte
buffer (in GAATDB).
(-) Enable control of CPU data bus high byte
buffer (in GAATDB).
(-) Enahle control of 16 <--) 8 conversion
buffer (in GAATDB).
Direction control of 16 <--) 8 conversion buffer
(in GAATDB).
Memory or 1/0 select. CPU M/-IO signal is
connected to this pin. Hhen high, memory cycle
is being executed.
(+) Command delay. While acti ve, the start of
commands (-NE~m, -MEMH, -lOR, -lOH) are delayed.

o
o

CSPD

(10 MHz)
(10 MHz)
1 (6,8 HHz)
1 (6,8 ~rnz)

7-22

AREA
16-bit memory
other
16-bH memory
other

Command delay

o
1

o
0.5

DIAGRAMS AND REFERENCE MATERIALS

REV.A

OUT1
HRQ1
XHW
HRQ
HLDA
HAK1
RFNO

o
o

RFNI
RFPO

o

63
24

RFlD

o

37

RF2D

o

36

DMMR

I
I

41
50
29

XIOR

I
I
I

21
22

o

30
3
31
28

46

I

I

DRDY

o

XMR
CA20

O&H-Z

64

I

34

A20G

I

33

O&H-Z

62

A20

OUT1 signal of 8254 (Timer LSI)
(+) Hold request input from 8237 (D}~C LSI).
(-) Internal memory write signal.
(+) Hold request output to CPU.
(+) Hold acknowledge input from CPU.
(+) Hold acknowledge output to 8237 (DMAC LSI).
(-) Refresh signal. This signal is generated in
GAATRF.
(-) Refresh signal input.
(+) Refresh signal.
(-) Refresh signal which is delayed by one DMA
clock cyc1e from RFNI signal.
(-) Refresh signal which is delayed by two DMA
clock cycles from RFNI signal.
(-) D}~ memory read signal.
(-) Internal 1/0 read signal.
(+) D~~ ready signal.
(-) Internal memory read signal.
CPU address bus 20. A20 signal of CPU is
connected to this pin.
(+) Gate signal of A20. P21 signal of 8042 (one
chip CPU) is connected to this pin.
System address bus 20.
CA20

CLK
SCLK
DCLK

I
I
I

51

1

1

*

o

o

I

*

13

20
19
53
Legend:

(*

don' t care)

Processor clock.
System clock.
DMA c1ock.

6

8

I

o

1

~rnz

10 MHz

o

A20

1

CPU speed
6 HHz

RST
RSTO
TEST

A20G

o

CLK
12 HHz
16 MHz
20 MHz

SCLK
6 HHz
8 MHz
10 }ffiz

DCLK
3 MHz
4 tffiz
5 HHz

(-) Reset input.
(+) Reset output.
(-) Test input.
I

o
Tri
O&H-Z

Input Pin
Output P in
Tri-state Pin (Input, Output, High-impedance)
Output & High-impedance P in

7-23

DIAGRAMS AND REFERENCE MATERIALS

7.2.9

HEV.A

GAATSP

GMTSP includes the follo\ving functional blocks.
1. Address decoder for serial port (DART, 16450 or 8250)
2. Parallel port. (PTDR: printer data register,
PTSR: printer status register,
PTCR: printer control register)
3. Oscillator for DART. (1.8432 MHz output)
4. General purpose 3-state gate.
GAATSP PIN DESCRIPTION

TABLE 7-2-13.

SYMBOL

1/0*

SA9-0
SD7-0

Tri

1

IOWN
IORN
AEN

I
I
I

RES
PIFI
PIFO

I
1

lS

PIN NO.
13-4
22,24,29,31
54,56,61,63
17
16
14
32
20
21

NAHE AND FDNCTION
Address bus
Data bus
(-) 1/0 write pulse.
(-) 1/0 read pulse.
(+) Address enable. This signal becornes high,
when DMA cycle is being executed.
(+) Reset.
Address select pin for parallel port.
Address select pin for parallel port.
PIFI

1

1

o

o

o
SIFI
SIFO

I
I

18
19

1

o

o

OSLI
OINl
OATF

7-24

o
I
I

O&II-Z

o
o
o
o

51
50
52
48
49
47
23,25,28,30
55,57,60,62
41
43

1

o

parallel port address
378, 379, 37A
278, 279, 27A
3BC, 3BD, 3BE
disable

Address select pin for serial port.
Address select pin for serial port.
SIFI
1

XTl
XT2
OSC
TSA
TSC
TSY
OD7-0

PIFO

1

SIFO
1

o
1

o

serial port address
3F8 --_. 3FF
2F8 --- 2FF
disable
disable

Crystal input. (3.6864 MHz)
Crystal input. (3.6864 }ffiZ)
1.8432 MHz clock output.
Data input of 3-state buffer.
Control input of 3-state buffer.
Output of 3-state buffer.
Printer data bit 7-0.
(-) Printer select.
(-) Printer initialize.
(-) Auto feed.

REV.A

OSTB
SLN
INI

ATF
STB
BSY
ACK
EOP
SLP

ERR

IRQ
OIRE

ACKP
SCSN
DDIR

DIAGRAMS AN» REFERENCE MATERIALS

o

45

I
I
I
I
I
I
I
I
I
O&II-Z

38
40

o
o
o
o

*

(-)
(-)
(-)
(-)
(-)

Printer data strobe pulse.
Printer select.
Printer initialize.
Auto feed.
Printer data strobe pulse.
(+) Printer busy.
(-) Acknowledge.
(+) End of paper.
(+) Printer select.
(-) Printer error.
(+) Interrupt request. IRQ becomes active, when
-ACK signal becomes low and interrupt request is
enabled.
(-) Interrupt request enable.
(+) Acknowledge.
(-) Chip select signal of serial port.
(-) Direction control of data buffer. This
signal is active while serial port or parallel
port are being read.

44
46
34

33

35
36

37
15
3
2

53
64

Legend:

Input P in
Output P in
Tri
Tri-state Pin (Input, Output, High-impedance)
0&11-2 = Output & High-impedance Pin
I

o

7-25

REV.A

DIAGRAMS AND REFERENCE MATERIALS

7 .2 .10

GAATFD

GMTFD includes the following functional blocks.
1. Address decoder for FDC(765) and 1/0 registers.
2. 1/0 register.
FDOR : Floppy digital output register.
FCR : Floppy control register.
3. Write precompensation circuit.
4. Clock ci.rcuit
5. DMA request circuit.
TABLE 7-2-14.

SYMBOL

1/0*

GAATFD PIK DESCRIPTIOK

PIK 1«>.

BA9-0
BD5-0
IOWN
IORN
AEN

I
I
I
I
I

8-2,64-62
14-19

RSE
FDIl
FDIO

I
I
I

52
46
45

11

10
9

NAME AND FUNCTION

Address bus.
Data bus.
(-) 1/0 write pulse.
(-) 1/0 read pulse.
(+) Address enable. This signal becomes high,
when DMA cycle is being executed.
(+) Reset.
Address select pin for FDC.
Address select pin for FDC.
FDIl
1
1
0
0

FDIO
1
0

1
0

FDC address
3F7
3FO
370
377
3F7
3FO
disable

(When FDll, FDIO = 0, 1
can not be accessed.)

3X7N

o
o
o
o
o
o
o

30
29
25
24
49
23
32

3XVN

o

47

FCSN
BDIR

o
o

44
59

MOT2
MOTI
DS2
DSI
FRES
RlvC

7-26

AT/XT
AT portI
AT port2
XT

Floppy control register

(+) Motor enable 2. (DRIVE B)
(+) Motor enable 1. (DRIVE A)
(+) Drive select 2. (DRIVE B)
(+) Drive select 1. (DRIVE A)
(+) FDC (765) reset signal.
(+) Reduced write current.
(-) Read 3X7 signal. This signal becomes active
while 1/0 address 3X7 is read. X means F (when
FDIO=I) or 7 (when FDIO=O)
(-) Chip select of 3X6 and 3X7. This signal
becomes active while 1/0 address 3X6 or 3X7 are
accessed.
(-) Chip select of FDC (765).
(~) Direction control of data
buffer. This
signal is active whiJe FDC (765) is being read.
(CPU access or DMA transfer)

DIAGRAMS AND REFERENCE MATERIALS

REV.A

DREN
DAKN
FDAN
BTC
FTC
FDRQ
DRQ
FWD
WB

PSI
PSü
WD
C48
TEST
MIN
OSC
CLK
WCLK
PINT
SYNC
VDRQ
SIDE
HS

INV
INVN
SEEK
DTKO
TRKO

o
I

o

60
12
50

I

13

o

o

42
40
61
35
36
33
34
28
55
38
48
57
54
56
41
43
53
51
22
20
21
37
31
39

*

Legend:

I

o
I
I
I
I

o
I
I

o
o
o
o
I
I

o
I

o
I

o
I
I

(-) Enable DMA and interrupt.
(-) D~~ acknowledge. (input frorn 8237)
(-) DMA acknowledge. (output to 765)
(+) Terminal count. (input frorn 8237)
(+) Terminal count. (output to 765)
(+) D~~ request. (input from 765)
(+) D}~ request. (output to 8237)
(+) Write data. (input from 765)
(+) Write enable. (input from 765)
Peak shift. (input from 765)
Peak shift. (input from 765)
(+) Write data. (output to FDD)
48 MHz clock input.
(-) Test pin.
Mini/Standard. (for SED9420)
16/9.6 MHz clock output. (for SED9420)
FDC dock. (8/4.8/4 ~rnz)
FDC write clock. (IM/600K/500K Hz)
(+) Interrupt request of FDC. (input frorn 765)
VFO synchronize. (input frorn 765)
(+) VFO DREQ. (for SED9420)
(+) Side select. (Head select, input frorn 765)
(+) Head select. (output to FDD)
Input of inverter.
Output of inverter.
(+) Seek. (input from 765)
(+) Track O. (input from FDD)
(+) Track O. (output to 765)
I = Input P in
Output P in

o

7-27

REV.A

DIAGRAMS AHn REFERENCE MATERIALS

DIAGNOSTICS PROGRAM
CONTENTS

1. System Board Check

7-28

.•••..•••.•.....•••••.••

7-29

2. f';1emory Check...............................

7-38

3. Keyboard Check

7-41

4. Monochrome Display Adapter and CRT Check

7-46

5. Color Graphics Adapter and CRT Check

7-52

6. Floppy Disk Drives and Controller Check ••..

7-64

7. Math Coprocessor (80287) Check •••••....••..

7-70

9. Parallel Port (Printer Interface) Check ..••

7-75

11. Serial Port (RS-232C) Check ••••••••.....•..

7-78

12. Alternate Serial Port Check................

7-82

14. Dot-matrix Printer Check

7-83

17. Hard Disk Drives and Controller Check •••.•.

7-85

21. Alternate Parallel Port Check..............

7-90

REV .A

1.

DIAGRAMS AND REFERENCE MATERIALS

System Board Check
This module checks the operation of each IC contained in the
systemboard. The checking operation is performed in the following
order,and the program displays an error message when some error is
detected.If noerror is detected, the program displays no error
message.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.

80286 Processor check
146818 CMOS shutdown byte check
27256 ROM checksum check
8254
Timer Counter check
8237
DMA Controller check
SN74LS612 DMA Page resister check
8237
Memory reflesh check
8042
Keyboard Controller check
80286 instruction check
146818 CMOS checksum and battery check
8259
Interrupt Controller check
8254
Timer Counter speed check
80286 protect mode check

When the system board check is started, the program displays
following message.

+-----------------------------------------------------------------+
I

I

I

I

:

SYSTEM BOARD CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
The remainder of this section describes the procedures for
each checking operation.
1)

80286 Processor Check

The 80286 Processor check performs writing and reading checks
on the 80286 flags and segment registers.
a.

"Offh" is stored (safh) into the 8080 flag, then re-loaded
(lahf). The flags are checked and it is considered an error
i f any of the below flags are not set (if the flag = 0):
CF
ZF
PF
SF
AF

(Carry Flag)
(Zero Flag)
(Parity Flag)
(Sign Flag)
(Auxiliary Carry-BCD)

7-29

DIAGRAMS AND REFERENCE MATERIALS

REV.A

The error message is as folIows:

+-----------------------------------------------------------------+
I
I

I
I

:

Error code = 101
80286 CPU ERROR

l

I
I

l
l
I
I

+-----------------------------------------------------------------+
b.

"OOh" is stored (safh) into the 8080 flag, then re-loaded
(lahf). The flags are checked and the program displays an
error message if any of the flags listed in Item a. above are
not reset (if the flag = 1).
The error message is identical to that of Item a.

c.

"Oaa55h" is sequentially written to and read from Registers
es, ds, and ss, then their values are checked. The program
displays an error message if the results do not match the
initial values.
The error message is identical to that of Item a.

d.

Using "055aah" as the test data, acheck identical to that
described in Item c. is conducted.
The error message is identical to that of Item a.

2)

146818 CMOS Shutdown Byte Check

The 146818 CMOS shutdown byte check performs a WRlTE/READ
check on the shutdown byte of the 146818 CMOS.
a.

The shutdown byte of offset 8fh of the CMOS is selected, "01"
is written and read, and the value is checked. The program
displays an error message if the result does not match the
initial value.

+-----------------------------------------------------------------+
I
I

I
I

:
:

Error code = 110
146818 CMOS SHUTDOWN BYTE ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+

7-30

b.

The test data of Item a. above is shifted to the left, then a
check identical to that described in Item a. is performed for
a11 eight bit s.
The error message is identical to that of Item a.

c.

Using "Oaah" as the test data, acheck identical to that
described in Item a. is performed.
The error message is identical to that of Item a.

d.

Using "055h" as the test data, acheck identical to that
described in Item a. is performed.
The error message is identical to that of Item a.

REV.A

DIAGRAMS AND REFERENCE MATERIALS

e.
3)

"OOh" is written to the shutdown byte, then this operation is
terminated.
27256 ROM Checksum Check

The 27256 ROM checksum check performs a check on the sum total
of all 27256 ROM data in byte units, then confirms whether or not
that sum equa1s "OOh". The program displays an error message if the
sum does notequal "OOh".

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 102
27256 ROM CHECKSUM ERROR

I
I

I
:
I
I

+-----------------------------------------------------------------+
4)

8254 Timer Counter Check

The 8254 Timer Counter check performs acheck of the setting
and reading operation of the counter register of the 8254 Timer
Counter.
Count "0" of the 8254 Timer Counter is 1atched and the count
va1ue is checked. Next, acheck is repeated1y performed to confirm
that all 16 bits have the va1ue of "1". The program displays an
error message if any bit of the count va1ue of "1" cannot be read.

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 103
8254 TIMER COUNTER REGISTER ERROR

:

l

1

I

I

I

+-----------------------------------------------------------------+
5)

8237 DMA Controller Check

The 8237 DMA Controller check performs a WRITE/READ check on
the eight registers (Port Nos. OOh to 07h) of the first 8237 DMA
Controller and on the eight registers (Port Nos. COh, C2h to CEh)
of the second 8237 DMA Controller.
The test data is used in the sequence of "OOOOh", "5555h",
"Oaaaah", and "Offffh". If an error is detected, the fo11owing
message will be disp1ayed:

+-----------------------------------------------------------------+
I
I

:
:
I
I

I
I

Error code = 105
8237 DMA CONTROLLER REGISTER ERROR

I
:
I
I

+-----------------------------------------------------------------+

7-31

DIAGRAMS AND REFERENCE MATERIALS

6)

REV.A

SN74LS612 DMA Page Register Check

The SN74LS612 DMA Page register check performs a WRITE/READ
check on the 15 registers (Port Nos. 81h to 8Fh) of the SN74LS612
Page Register.
The test data is used in the sequence of "OOh", "SSh", "Oaah",
and "Offh". If an error is detected, the following message will be
displayed:

+-----------------------------------------------------------------+
I
I

I
I

Error code = 106
612 DMA PAGE REGISTER ERROR

:
:
1

:

l
I

I

I

+-----------------------------------------------------------------+
7)

8237 Memory Refresh Check

The 8237 Memory refresh check performs a repeated check on the
refresh detect bit of Port No. 61h, and checks if its status makes
a change.
The program displyas an error message if the status does not
change.

+-----------------------------------------------------------------+
1

I

I

I

Error code = 105
8237 DMA REFRESH ERROR

:
:
I
I

:

l

I
1

+-----------------------------------------------------------------+
8)

8042 Keyboard Controller Check

The 8042 Keyboard Controller check performs a check on the
operating status of the Keyboard Controller.
a.

The status of the Keyboard Controller is repeatedly checked,
and the program displays an error message if its input buffer
is not empty.

+-----------------------------------------------------------------+
I

1

I

I

:
:

Error code = 107
8042 TIME OUT ERROR

I
I

I
:
I
I

+-----------------------------------------------------------------+
b.

7-32

The Self-test command is output to the Keyboard Controller so
that it will execute a self-diagnostic test. If an error is
detected, the following message will be displayed:

DIAGRAHS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I
I

Error code = 108
8042 SELF DIAGNOSTIC ERROR

:
:

I
I

:
:

I

I

I

I

+-----------------------------------------------------------------+
c.

The Read Input Code command is output to the Keyboard
Controller, and the program displays an error message if it
does not assume the "Input buffer empty" status.
The error message is identical to that of Item a. above.

d.

The Write Keyboard Controller's Command Byte command is
output tothe Keyboard Controller, and the program displays
an error messageif it does not assume the "Input buffer empty
status.
The error message is as foliows:

+-----------------------------------------------------------------+
I
I

I
I

Error code = 108
8042 WRI TE COMMAND ERROR

:
:

:
:

I

I

I

I

+-----------------------------------------------------------------+
e.

The mode of the Keyboard Controller is reset to the following
modes and this operation is terminated.
PC Compatible Mode
Disable Keyboard
Inhibit Override
System flag
Enable Output-Buffer-Full Interrupt

9)

80826 Instruction Check

The 80826 Instruction check performs a WRITE/READ test on the
System Table Registers IDTR and GDTR as weIl as a SET/RESET test on
the direction flag and interrupt enable flag of the CPU flags.
a.

The test data "Oaaaah" is written to and read from IDTR and
GDTR, then their values are checked. The program displays an
error message if the results do not match the initial values.

+-----------------------------------------------------------------+
I
I

I
I

Error code = 113
80286 INSTRUCTION ERROR

:

l
I
I

l
:
I
I

+-----------------------------------------------------------------+
b.

Using the test data "5555h" and "OOOOh", an identical check
is performed.
The error message is identical to that of Item a. above.

7-33

REV.A

DIAGRAMS AND REFERENCE MATERIALS

c.

"Offffh" is set at IDTR.

d.

The direction flag and interrupt enable flag are set using the
STD and STI instructions, and the status of the CPD flags is
checked. It is considered an error if the direction flag and
interrupt enable flag are not set.
The error message is identical to that of Item a.

e.

Similarly, the direction flag and interrupt enable flag are
reset using the CLD and CLI instructions, and the status of
the CPD flags is checked.
The error message is identical to that of Item a.

10) 146818 CMOS Checksum and Battery Check
The 146818 CMOS checksum and battery check performs a check on
the battery status of the CMOS and the checksum.
a.

The CMOS battery status is read to check if the battery is all
right. If not, the program displys following error message.

+-----------------------------------------------------------------+
I
I

I
I

:
:

Error code = 111
146818 CMOS BATTERY ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
b.

The CMOS shutdown byte is read to check i f i t is in "Shutdown
OK" status. If so, this operation is terminated here; if not,
execution proceeds to the checking of the checksum.

c.

The total sum of the data from CMOS offset 90h to Oadh is
calculated, and the program displys an error message if the
resulting value equals zero.

+-----------------------------------------------------------------+
I
I

I
I

Error code = 112
146818 CMOS CHECKSUM ERROR

:
:
I
I

:
:
I
I

+-----------------------------------------------------------------+
d.

The total sum of the data from CMOS offset 90h to Oadh is
compared with the checksum value (CMOS offset Oaeh and Oafh),
and the program disp1ys an error message if they do not match.
The error message is identical to that of Item c.

11) 8259 Interrupt Controller Check
The 8259 Interrupt Controller check performs the following
checks on 8259.

7-34

BEY .A

DIAGRAHS AND REFERENCE MATERIALS

a.

The masking of all interrupts is reset, then a READ check is
performed on the mask register.

b.

The masking of all interrupts is set, then a READ check is
performed on the mask register.

c.

Interrupt state of the CPU is enabled in a status where all
interrupts are masked, and the program displays an error
message if an interrupt occurs.

If an error is detected during the above checks, the program
displays following error message:

+-----------------------------------------------------------------+
I
I

Error code = 109
8259 INTERRUPT CONTROLLER ERROR

:
:
I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
12) 8254 Timer Counter Speed Check
The 8254 Timer Counter speed check confirms if the timer is
interrupted within the proper interval.
The interrupt processing routine of 8259A is set to the special
setting, only the Count "0" output of the timer is placed into the
interrupt enable status, and the Count "0" value is checked.
a.

Starting with a Count value of 50, it is checked whether an
interrupt occurs during 3memoryrefresh intervals. The
program displays an error message if no interrupt occurs.

+-----------------------------------------------------------------+
I
I

Error code = 104
8254 TIMER COUNTER ERROR

:
:
I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
b.

Starting with a Count value of 250, it is checked whether an
interrupt does not occur during 4 memory refresh intervals,
then it is checked whether an interrupt occurs during 6
intervals. If an error detected, the program displays an
error message identical to that of Item a.

13) 80286 Protect Mode Check
The 80286 protect mode check performs a WRITE/READ check on the
80286 protect mode register as weIl as a check on the execution
status of the instructions during protect mode.

7-35

DIAGRAMS AND REFERENCE MATERIALS

a.

REV.A

The transition into protect mode is checked. The Global
Descriptor table and Interrupt Descriptor table are prepared,
then execution shifts from real mode to protect mode. At this
point, the program displays an error message if the PE bit of
the Machine Status Word does not become "1".

+-----------------------------------------------------------------+
I
I

I
I

:
:

Error code = 115
80286 PROTECT MODE ERROR 2

I
I

:
:
I
I

+-----------------------------------------------------------------+

7-36

b.

The interruption of protect mode is checked. The program
displays an error message if the interrupt processing routine
set at the Interrupt Descriptor table in protect mode is not
executed within the prescribed time.
The error message is identical to that of Item a.

c.

A WRITE/READ check is performed on LDTR (Local Descriptor
table register), and the program displays an error message if
the va lues do not match.
The error message is identical to that of Item a.

d.

A WRITE/READ check is performed on TR (Task register), and the
program displays an error message if the values do not match.
The error message is identical to that of Item a.

e.

A SET/RESET check is performed on DF (Direction flag), and the
program displays an error message if the set status and the DF
flag of the CPU do not match.
The error message is identical to that of Item a.

f.

A boundary check is performed using the BOUND instruction,
then the absence of an out-of-boundary interrupt (INT 5) is
confirmed by checking the data within boundaries and the
occurrence of an out-of-boundary interrupt is confirmed by
checking the out-of-boundary data.
The error message is identical to that of Item a.

g.

The operation of the PUSHA and POPA instructions is checked.
The register values are changed after execution of PUSH A,
POPA is executed, then it is checked whether the register
values prior to PUSHA execution match the respective register
values.
The error message is identical to that of Item a.

h.

The operation of the VERR and VERW instructions is checked.
The setting of the Writable bit of the access right byte to
the Descriptor table is checked using the VERR and VERW
instructions, then it is checked whether testing of the
reading access right byte and writing access right byte of
the segments can be properly performed.
The error message is identical to that of Item a.

REV.A

DIAGRAMS AND REFERENCE MATERIALS

i.

j.

The operation of the ARPL instruction is checked. Using the
ARPL instruction, the operation is checked for the case where
the requested privi1ege level is adjustab1e and the case where
it is not adjustab1e.
The error message is identica1 to that of Item a.
The operation of the LAR instruction is checked. The access
right byte is loaded using the LAR instruction and is checked
for being the prescribed va1ue. The program displays an error
message if the access right bytecannot be read or if it is
not the prescribed va1ue.
The error message is identica1 to that of Item a.

k.

The operation of the LSL instruction is checked. The segment
limit is loaded using the LSL instruction and is checked for
being the prescribed va1ue. The program displays an error
message if the segment limit cannot be read or if it is not
the prescribed va1ue.
The error message is identica1 to that of Item a.

1.

A WRITE check is performed on the test data whi1e changing
the segment se1ector. The program displays an error message
if the segment se1ector has not proper1y changed.

+-----------------------------------------------------------------+
I
I

I
I

:
:

Error code = 114
80286 P ROTECT MODE ERROR 1

I
I

:
:
I
I

+-----------------------------------------------------------------+
m.

The system is returned to real mode by system reset. The stack
segment and stack pointer are reset, then this checking
operation is terminated.

7-37

DIAGRAMS ARD REFERENCE MATERIALS

2•

REV.A

Memory Check

This module performs a WRITE/READ check on the Ramdom Access
Memory (RAM) in block units (1 block = 64 KB). The remainder of
this section describes the procedures for each checking operation.
1)

64 KB Check of "OOOOOh" - "OFFFFh"
a.

The contents of "OOOOOh" - "OFFFFh" are evacuated to
"20000h" - "2FFFFh".

b.

The test data, "55aah", is written to the entire 64KB area,
the 1/0 check and RAM Parity check are enabled, then a VERIFY
check and parity check are performed.
If an error is detected, the program displays following error
message:

+-----------------------------------------------------------------+
I
I

I
I

Error code = 201
xxxxx yyyy zzzzzz ERROR

:
:
I
I

:
:
I
I

+-----------------------------------------------------------------+
(xxxxx represents the absolute address where the error detected,
yyyy represents the error data [any bit that is not "I"], and
zzzzzz is either "PARITY" in case of a parity error or "MEMORY" in
case ofa VERIFY error.)

7-38

c.

Using "Oaa55h" as the test data, acheck identical to that of
Item b. is performed.

d.

Using "010Ih" as the test data, acheck identical to that of
Item b. is performed.

e.

The test data, "5555h" and "Oaaaah", is written sequentially
to the entire 64 KB area, then a parity check is performed.
Next, the test data is read and a VERIFY check is performed.
The test data "OOOOh" is written and a parity check is
concurrently performed.

f.

The test data "OFFFFh" is written to the leading and trailing
words of the 64 KB block and test data "OOOOh" is written to
the other words. Next, the test data is read, then a VERIFY
check and parity check are performed.

g.

If the check of the 64 KB block is normally terminated, the
contents of "20000h" - "2FFFFh" are re-written to "OOOOOh" "OFFFFh".

h.

Next, a message indicating the completion of the first 64 KB
block check is displayed on the screen.

HEV.A

DIAGRAMS AND REFERENCE MATERIALS

+---------------------------------_._---------------------~--------+
I
I

:

I
I

000064 KB OK

:

I
I

I
I

+-----------------------------------------------------------------+
2)

64 KB Check of "10000h" - "1FFFFh"
a.

The contents of "10000h" - "1FFFFh" are evacuated to "30000h"
- "3FFFFh".

b. to f.

A RAM check identical to that of Item 1) is performed.

g.

If the check of the 64 KB block is normally terminated, the
contents of "30000h" - "3FFFFh" are re-written to "10000h" "1FFFFh".

h.

Next, a message indicating the completion of the second 64 KB
block check is displayed on the screen.

+-----------------------------------------------------------------+
I
I

I
I

:

000128 KB OK

:

I
I

I
I

+-----------------------------------------------------------------+
3)

64 KB Check of "20000h" - "2FFFFh"
a.

The contents of "20000h" - "2FFFFh" are evacuated to "30000h"
- "3FFFFh".

b. to f.

A RAM check identical to that of Item 1) is performed.

g.

If the check of the 64 KB block is normally terminated, the
contents of "30000h" - "3FFFFh" are re-written to "20000h" "2FFFFh".

h.

Next, a message indicating the completion of the third 64 KB
block check is displayed on the screen.

+-----------------------------------------------------------------+
I

I

I

:

I

000192 KB OK

:

I

I

I

I

+-----------------------------------------------------------------+
4)

64 KB Block Check of Address "30000h" and Onward

The CMOS settings
calculated, then a RAM
64 KB units up to that
Each time a 64 KB
following message.

are read, the highest RAM address is
check identical to Item 1) is performed in
highest address.
check is completed, the program displays

7-39

DIAGRAHS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I
I

I
I

:

XXXXXX KB OK

I
I

:
I
I

+-----------------------------------------------------------------+
(The XXXXXX represents the total size of the checked memory block.)
5)

Lastly, a parity check is performed by word unit. Each time a
64 KB check is completed, the program displays following message.

+-----------------------------------------------------------------+
I
I

:
I
I

I
I

XXXXXX KB OK

:
I
I

+-----------------------------------------------------------------+
(The XXXXXX represents the total size of the checked memory block.)
NOTE:The base memorysize is checkedusing int 12h.The expansion
memory size is checked by reading CMOS offset 30h and 31h.
In case an expanded memory is installed, the memory check is
performed in protect mode of 80286.

7-40

REV .A

3.

DIAGRAKS AND REFERENCE MATERIALS

Keyboard Check

This module checks the operating status of the keyboard as well
as the input of each key. The remainder of this section describes
the checking procedures.
(In case of test multiple times, only keyboard function check is
performed.)
1)

Keyboard Function Check
a.

The keyboard is read without pressing any keys, and the
program displays an error message if the input status is not
empty.

+-----------------------------------------------------------------+
I
I

I
I

Error code = 301
8042 ERROR

:
:
I
I

l
:
I
I

+-----------------------------------------------------------------+
b.

The self-test command is output to the keyboard. The program
displays an error message if the Normal Termination code is
not returned.

+-----------------------------------------------------------------+
I

I

I

I

Error code = 301
8042 ERROR

:
:
I
I

:
:
I
I

+-----------------------------------------------------------------+
c.

The interface test command is output to the keyboard. The
program displays an error message if the Normal Termination
code is not returned.

+-----------------------------------------------------------------+
I
I

I
I

:
:

Error code = 301
KEYBOARD ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
d.

The keyboard functions are disabled, then the response from
the keyboard is checked. The program displays an error
message if the keyboard is in data ON status with the keyboard
clock in OFF status. The error message is identical to that
of Item c.

7-41

DIAGRAMS AND REFERENCE MATERIALS

e.

2)

HEV.A

The keyboard functions are enabled, then the reset command is
output to the keyboard. The program displays an error message
in case there is no ACK response or in case the resetting
generates a BAT Completion code. The error message is
identical to that of Item c.
Keyboard Lock Check

a.

First, determine whether or not to check the keyboard lock.

+-----------------------------------------------------------------+
I
I

I
I

:

Do you wish to check the keyboard lock (Y/N)?

:

I

I

I

I

+-----------------------------------------------------------------+
When "Y" is input after the prompt, the keyboard lock check is
executed. When "N" is input, the keyboard lock check is not
performed.
b.

When the keyboard lock check is begun, the following message
is displayed, so insert the key into the front panel and turn
it to lock the keyboard.

+-----------------------------------------------------------------+
I

I

I

I

:

Lock the keyboard using the front-panel key

I
I

:
I
I

+-----------------------------------------------------------------+
The program displays an error message if the keyboard is not
locked within the prescribed time.

+-----------------------------------------------------------------+
I

I

I

I

l

Error code = 303
KEYBOARD LOCKING ERROR

:
I
I

:
:
I
I

+-----------------------------------------------------------------+
c.

When the keyboard becomes locked, the following message is
displayed, so turn the front-panel key to unlock the keyboard.

+-----------------------------------------------------------------+
I
I

:

I
I

Unlock the keyboard

I
I

:
I
I

+-----------------------------------------------------------------+
The program displays an error message if the keyboard is not
unlocked within the prescribed time. The error message is
identical to that of Item b.

7-42

DIAGRAMS AND REFERENCE MATERIALS

REV.A

3)

Keyboard Input Check
First of all, select the keyboard type according to country.

+-----------------------------------------------------------------+
KEYBOARD SELECT MENU
1
2
3
4
5
6

-

o-

US ASCII
United Kingdom
French
German
Italian
Spanish
Exit

Enter selection number:

+-----------------------------------------------------------------+
When the keyboard type is selected, the OF2h command code is
output to the connected keyboard, and the keyboard is judged as
being of old type (89 keys) or new type (101 or 102 keys) by its
response.

+------------------+-------------------------------+

I

Response

I

Keyboard Type

:

+------------------+-------------------------------+
:
:

only ACK
ACK, ABh, 41h

I
I

Old type (89 keys)
New type (101 or 102 keys)

:
:

+------------------+-------------------------------+
The keyboard layout corresponding to the judged keyboard type
is displayed. By pressing an arbitrary key, the character
corresponding to the pressed key top will be displayed on the
screen.
When "y" and ENTER is input, the check is normally terminated.
If "N" and ENTER is input in the case that the pressed key top and
the displayed character are different, the program displays
following message:

+-----------------------------------------------------------------+
KEYBOARD CHECK
Error code = 302
KEYBOARD IS NON-STANDARD, OR
KEYBOARD IS DEFECTIVE.

+-----------------------------------------------------------------+

7-43

DIAGRAMS AND REFERENCE MATERIALS

REMARK:

a.

During the keyboard input check, the interrupt vector of
keyboard input is rewritten, the scan code of the keyboard
is directly read, then the corresponding character is
displayed.

Layout of old-type keyboard

+-----------------------------------------------------------------+
KEYBOARD CHECK
Press Y followed by ENTER to exit.
Press N followed by ENTER if screen andkeyboard do not match.

+-----------------------------------------------------------------+
b.

Layout of new-type (lOl-key) keyboard

+-----------------------------------------------------------------+
KEYBOARD CHECK
Press Y followed by ENTER to exit.
Press N followed by ENTER if screen andkeyboard do not match.

+-----------------------------------------------------------------+
7-44

HEV.A

REV .A

c.

DIAGRAMS AN» REFERENCE MATERIALS

Layout of new-type (102-key) keyboard

+-----------------------------------------------------------------+
KEYBOARD CHECK
Press Y followed by ENTER to exit.
Press N followed by ENTER if screen andkeyboard do not match.

+-----------------------------------------------------------------+

7-45

DIAGRAKS AND REFERENCE MATERIALS

4.

HEV.A

Monochrome Display Adapter and CRT Check

This module checks the monochrome display and its adapter.
First, select which check to perform from the menu.

+-----------------------------------------------------------------+
MONOCHROME ADAP TER AND CRT CHECK MENU
1
2
3
4
5
6

-

o-

Monochrome adapter check
Attribute check
Character set check
Video check
Sync check
Run all above checks
Exit

Enter selection number:

+-----------------------------------------------------------------+
(In case of test multiple times, only the monochrome adapter check
is performed.)
The remainder of this section describes each of the checking
procedures.
1)

Monochrome Adapter Check

When the monochrome adapter check is selected, the program
displays following message:

+-----------------------------------------------------------------+
I
I

I
I

:

MONOCHROME ADAP TER CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
a.
i)

7-46

A WRlTE/READ check is performed on the VRAM area used for the
monochrome display.
The Video Enable signal of the monochrome monitor is set to
OFF. Next, the test data "OOh" is written to and read from
the entire VRAM area ("BOOOOH" - "BOFAOH"), and a comparison
check is performed.
If the compared data do not match, the program displays
the address generating the mismatch, the written data, and
the read data.

DIAGRAMS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I
I

I
I

Error code = 401
V-RAM ERROR address
write data YY

:
:
:

:
:
:

BOOOH:XXXX
read data ZZ

I
I

I
I

+-----------------------------------------------------------------+
(XXXX represents the VRAM off set address that generated the
mismatch, YY represents the written data, and ZZ represents the
read data.)
ii)

Next, using the test data "55h" , an identical check is
performed.

iii)

Next, using the test data "Oaah", an identical check is
performed.

iv)

Next, using the test data "Offh", an identical check is
performed.
Lastly, "OOh" is written to the entire VRAM area.

b.

Black/White mode check of CRT status port
The Video Enable signal of the monochrome monitor is set to
ON status, then the program displays following message:

+-----------------------------------------------------------------+
I
I

:

I
I

MONOCHROME ADAPTER CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
Next, "Offh" is written to the latter half of the VRAM area
("B07DOH" - "BOFAOH") for the monochrome display, and the CRT
status port of 6845 is checked.
A Black/White Video signal that changes to "1" from "0" is
normal. The program displaysfollowing error message if the
Black/White Video signal remains "0" (LOW) or "1" (HIGH):

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 402
VIDEO SIGNAL ALWAYS LOW

I
I

:
:
I
I

+-----------------------------------------------------------------+
or

+-----------------------------------------------------------------+
I
I

:
:
I
I

I
I

Error code = 402
VIDEO SIGNAL ALWAYS HIGH

:
:
I
I

+-----------------------------------------------------------------+

7-47

REV.A

DIAGRAMS AND REFERENCE MATERIALS

Lastly, "OOh" is written to the latter half C"B07DOH" "BOFAOH") of the VRAM area and this check is terminated.
2)

Attribute Check

When the attribute check is selected, the various types of
attributes that can be displayed are shown on the monochrome
display using characters.

+-----------------------------------------------------------------+
ATTRIBUTE CHECK
NORMAL INTENSITY
HIGH INTENSITY
BLINKING
REVERSE
UNDERLINED
Is the display correct CY/N)?

I
I
I
I
I
I
I
I
I

+-----------------------------------------------------------------+
Confirm whether each attribute is accurately displayed, then
input the answer.
If "N" is input, the program displays an errormessage.

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 403
ATTRIBUTE ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
3)

Character Set Check

When the character set check is selected, the entire character
set from "OOh" to "Offh" is displayed on the screen.
Confirm whether the character set is accurately displayed, then
input the answer.

7-48

DIAGRAHS AN» REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
CHARACTER SET CHECK

( All character set )

1s the display correct (Y/N)?

+-----------------------------------------------------------------+
1f "N" is input, an error message is displayed.

+-----------------------------------------------------------------+
I
I

:

i

I
I

Error code = 404
CHARACTER SET ERROR

I
I

i
:
I
I

+-----------------------------------------------------------------+
4)

Video Check
When the video check is selected, the following screen is
initially displayed with a high-intensity foreground color and a
black background color:

7-49

DIAGRAMS AND REFERENCE MATERIALS

HEV.A

+-----------------------------------------------------------------+

BLACK

+-----------------------------------------------------------------+
When any key is pressed, the following screen is displayed
with a black foreground color and a high-intensity background color:

+-----------------------------------------------------------------+

INTENSIFIED WHITE

+-----------------------------------------------------------------+
Pressing any key terminates this operation.

7-50

REV .A

5)

DIAGRAMS AND REFERENCE MATERIALS

Sync Check
When the sync check is selected, the following screen is
displayed. Check this screen for any discrepancies in the
synchronization of all lines.

+-----------------------------------------------------------------+

+-----------------------------------------------------------------+
6)

Run All Above Checks
When "Run all above checks" is selected, the checks described
in Items 1) to 5) are consecutively executed.

7-51

DIAGRAMS AB» REFERENCE MATERIALS

5.

REV.A

Color Graphics Adapter and CRT Check

This module checks the color display and its adapter.
First, select which check to perform from the menu.

+-----------------------------------------------------------------+
I
I

COLOR GRAPHICS ADAPTER AND CRT CHECK MENU
1
2
3
4
5
6

-

7 8
9
10
11

I
I
I
I
I
I
I
I
I
I
I

-

o-

Color graphics adapter check
Attribute check
Character set check
40-column character set check
320X200 graphics mode check
640X200 graphics mode check
Screen paging check
Light pen check
Color video check
Sync check
Run all above checks
Exit

Enter selection number:

+-----------------------------------------------------------------+
(In case of test multiple times, only the color graphics adapter
check is performed.)
The remainder of this section describes each of the checking
procedures.
1)

Color Graphics Adapter Check

When the color graphics adapter check is selected, the program
displays following message:

+-----------------------------------------------------------------+
I
I

I
I

:

COLOR ADAP TER CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
At this point, a WRITE/READ check is performed on the VRAM
area used for color graphics.
a.

7-52

The Video Enable signal of color graphics is set to OFF. Next,
the test data "OOh" is written to and read from the entire
VRAM area ("B8000H" - "B9F3FH" and "BAOOOH" - "BBF3FH") used
for color graphics, and a comparison check is performed.
If the compared data does not match, the program displays the
address generating the mismatch, the written data, and read

DlAGRAHS AHn REFERENCE MATERIALS

REV.A

data.

+-----------------------------------------------------------------+
I
I

Error code = 501
V-RAM ERROR address B800H:XXXX
write data YY
read data ZZ

:
:
:
I
I

I
I

:
:
:
I
I

+-----------------------------------------------------------------+
(XXXX represents the address generating the mismatch, YY represents
the written data, and ZZ represents the read data.)
b.

Next, using the test data "SSh", an identical check is
performed.

c.

Next, using the test data "Oaah", an identical check is
performed.

d.

Next, using the test data "Offh", an identical check is
performed.

Lastly, "OOh" is written to the entire VRAM area, the Video
Enable signal is set to ON, and this check is terminated.

7-53

DIAGRAMS AN» REFERENCE MATERIALS

REV.A

2)

Attribute Check
When the attribute check is selected, the various types of
attributes that can be displayed using color graphics are shown
using characters. (40 x 25 character mode)

+-----------------------------------------------------------------+
I

ATTRIBUTE CHECK

HIDRHAINTElIßJlnTY
BLINKING
BLACK
BLUE
GREEN
CYAN
RED
MAGENTA
BROWN
WHITE
GRAY
LIGHT BLUE
LIGHT GREEN
LIGHT CYAN
LIGHT RED
LIGHT MAGENTA
YELLO\'1
WHITE (High intensity)
Is the display correct (Y/N)?

+-----------------------------------------------------------------+
Confirm whether each attribute is accurately displayed, then
input the result. (The display has returned to the 80 x 25
character mode.)
If "N" is input, the program displays an error message.

+-----------------------------------------------------------------+
I
I

:
:

Error code = 503
ATTRIBUTE ERROR

I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
3)

Character Set Check

When the character set check is selected, the entire character
set from "OOh" to "Offh" is displayed on the screen.
Confirm whether the character set is accurately displayed,
then input the answer.

7-54

DIAGRAMS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
CHARACTER SET CHECK

( All character set )

1s the display correct (Y/N)?

+-----------------------------------------------------------------+
1f "N" is input, the program displays an error message.

+-----------------------------------------------------------------+
I
I

:
:

Error code = 504
CHARACTER SET ERROR

I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
4)

40-Column Character Set Check

When the 40-column character set check is selected, the entire
character set from "OOh" to "Offh" is displayed on the screen in
40-column mode.

7-55

DIAGRAMS AN» REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
40-COLUMN CHARACTER SET CHECK

I
I
I
I
I
I
I
I
I
I
I
I
I
I

( All character set in 40-column mode )

I
I
I
I

,
I
I

1s the display correct (Y/N)?

I
I

I
I

+-----------------------------------------------------------------+
1f "N" is input, the program displays an error message.

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 505
40-COLUMN CHARACTER SET ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
5)

320 x 200 Graphics Mode Check

When the 320 x 200 graphics mode check is selected, the
following image pattern is displayed on the screen.This screen
has been created by writing directly to VRAM. (Color setting = "0")

7-56

DIAGRAMS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
320X200 GRAPH1CS MODE CHECK
COLOR SET 0

+----------------+

+-----------------+

I

I
I
I
I
I
I
I
I
I
I

I

I
I
I
I
I
I
I
I

GREEN

RED

+-----------------+
--------------+

+------------BROWN

I
I
I
I
I
I
I
I
I

+-----------------+

CYAN

1s the display correct (Y/N)?

+-----------------------------------------------------------------+
Confirm whether the pattern is accurately displayed, then
input the answer.
1f "N" is input, the program displays an error message.

+-----------------------------------------------------------------+
I
I

:
:
I
I

I
I

Error code = 506
320X200 GRAPHICS MODE ERROR

:
:
I
I

+-----------------------------------------------------------------+

7-57

DIAGRAMS AND REFERENCE MATERIALS

HEV.A

Next, change the color setting to "1" to display the same
image pattern on the screen.

+-----------------------------------------------------------------+
320X200 GRAPH1CS MODE CHECK
COLOR SET 1

+----------------+

+-----------------+

I
I
I

CYAN

I
I
I

I

I

I
I
I

I
I
I

I

I

I
I

MAGENTA

I
I

+-----------------+
+-------------

--------------+
WHITE

+-----------------+

RED

1s the display correct (Y/N)?

I
I
I
I
I
I

+-----------------------------------------------------------------+
Confirm whether the pattern is accurately displayed, then
input the answer.
1f "N" is input, the program displays an error message.

+-----------------------------------------------------------------+
I
I

Error code = 506
320X200 GRAPH1CS MODE ERROR

:
:
I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
6)

640 x 200 Graphics Mode Check

When the 640 x 200 graphics mode check is selected, the
following image pattern is displayed on the screen. This screen
has been created by writing directly to VRAM. (High-resolution mode)

7-58

DIAGRAMS AHn REFERENCE

REV.A

MATERIAL~

+-----------------------------------------------------------------+
640X200 GRAPH1CS MODE CHECK

+----------------+

+-----------------+

I
I
I
I
I
I
I
I
I
I

(a)

I
I
I
I
I
I
I
I
I
I

(b)

+-----------------+
+-------------

--------------+
(c)

+-----------------+
1s the display correct (Y/N)?

+-----------------------------------------------------------------+
(a)

Coarse stripes

(b)

Fine stripes

(c)

Completely filled

Confirm whether the pattern is accurately displayed t then input
the answer.
1f "N" is input t the program displays an error message.

+-----------------------------------------------------------------+
I
I

:

l

I
I

Error code

=

507

640X200 GRAPH1CS MODE ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
7)

Screen Page Check

When the screen page check is selected t the characters "0" "7" are respectively written to Pages 0 - 7 t then the screen paging
according to the changing of pages is checked.

7-59

DIAGRAMS AND REFERENCE MATERIALS

+-----------------------------------------------------------------+
SCREEN PAG1NG CHECK

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
(a)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Press any key for next page

+-----------------------------------------------------------------+
(a)

The numeral corresponding to each page no. is displayed.

After completing the check up to Page 7, confirm wh ether the
screen paging was accurately displayed, then input the answer.

+-----------------------------------------------------------------+
SCREEN P AG1NG CHECK

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
(a)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
1s the display correct (Y/N)?

+-----------------------------------------------------------------+
1f "N" is input, the program displays an error message.

7-60

REV.A

HEV.A

DIAGRAMS AND REFERENCE MATERIALS

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 508
SCREEN P AGING ERROR

:

l

I

I

I

I

+-----------------------------------------------------------------+
8)

Light P en Check

When the light pen check is selected, you must next specify
whether or not to actually perform the check.

+-----------------------------------------------------------------+
I
I

:
:

l

I
I

l

LIGHT P EN CHECK
Enter Y to start light pen check.
Enter N to return to the menu.

:
:

I
I

I
I

+-----------------------------------------------------------------+
Next, a white block is displayed on the the screen, so press
the light pen on the center of each block. The address that is
read from light pen is checked.

+-----------------------------------------------------------------+
+---+
: c i
+---+
+---+

l

b

i

+---+
+---+
: a :

+---+
PLACE LIGHT PEN ON CENTER OF WHITE BLOCK

+-----------------------------------------------------------------+
Check the three blocks in the order of a - b - c.

The program displays an error message if the position where the
block is displayed and the light pen position do not match.

7-61

DIAGRAMS AN» REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 509
LIGHT PEN ERROR

:
:

I
I

I
I

+-----------------------------------------------------------------+
9)

Color Video Check

When the color video check is selected, the display of the
background color is changed in the sequence below:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

Black
Blue
Green
Cyan
Red
Magenta
Brown
White
Gray
Light blue
Light green
Light cyan
Light red
Light magenta
Yellow
White (high intensity)

After all of the background colors are displayed, confirm
whether they have been accurately displayed then input the ans wer.

+-----------------------------------------------------------------+
I
I

:

I
I

Is the display correct (Y/N)?

I
I

:
I
I

+-----------------------------------------------------------------+
If "N" is input, the program displays an error message.

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 510
COLOR VIDEO ERROR

I
I

l
:
I
I

+-----------------------------------------------------------------+
10) Sync Check
When the sync check is selected, the following screen is
displayed. Check this screen for any discrepancies in the
synchronization of all lines.

7-62

DIAGRAMS AN» REFERENCE MATERIALS

HEV.A

+-----------------------------------------------------------------+

I
I
I
I
I
I

+-----------------------------------------------------------------+
11) Run All Above Checks
When "Run all above checks" is selected, the checks described
in Items 1) to 10) are consecutively executed.

7-63

DIAGRAMS AND REFERENCE MATERIALS

6.

KEV.A

Floppy Disk Drives and Controller Check

This module checks the floppy disks and floppy disk drives.
First, select which check to perform from the menu.

+-----------------------------------------------------------------+
I
I

FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK MENU
1 - Sequential seek check
2 - Random seek check
3 - Write, read check
4 - Speed check
5 - Disk change check
6 - Run all above checks

o-

I
I
I
I
I
I
I
I

Exit

Enter selection number:

I
I
I

+-----------------------------------------------------------------+
(In case of test multiple times, the following checks are
consecuti vely performed.)

+-----------------------------------------------------------------+
I
I

:
:
:

I
I

1 - Sequencial seek check
2 - Random seek check
3 - Write, read check

I
I

:
:
:
I
I

+-----------------------------------------------------------------+
The remainder of this section describes each of the checking
procedures.
1)

Sequential Seek Check

Initially, the number of floppy disk drives installedis
checked by using Equipment Determination (int 11h). The program
displays following message if two drives are installed, so input
the name of the drive to be checked:

+-----------------------------------------------------------------+
I
I

:
I
I

I
I

Check which drive (AlB)?

:
I
I

+-----------------------------------------------------------------+
The sequential seek check sequentially searches from the
cylinder position of the innermost periphery to that of the outermost
periphery for the head, then checks the seek operation. This check
is performed with respect to Head "0" and "1".

7-64

REV.A

DIAGRAMS ARD REFERENCE MATERIALS

+-----------------------------------------------------------------+
I
I

:

I
I

SEQUENTIAL SEEK CHECK

I
I

:

:
I
I

Current track is xxxx

I
I

:
I
I

+-----------------------------------------------------------------+
(The xxxx represents the number of the sought cylinder.)

The program displays an error message if the Floppy Disk
Controller (FDC) assumes one of the following status es:
1. The FDC main status remains BUSY.
2. The FDC is not in Output Ready status when the program
going to output a command.
3. The FDC is not in Input Ready status when the program going
to input status.

+-----------------------------------------------------------------+
I
I

:
:
:

I
I

FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 601
FLOPPY DISK CONTROLLER ERROR

I
I

:
:
:
I
I

+-----------------------------------------------------------------+
The program displays an errormessage also when the seek
operation of the FDC after performing head seek is not normally
terminated.

+-----------------------------------------------------------------+
FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 602
SEQUENTIAL SEEK ERROR
TRACK -- xx
SIDE --- Y

+-----------------------------------------------------------------+
(xx represents the error cylinder number and y representsthe error
head number.)
2)

Random Seek Check

The random seek checking procedure is identical to that of
Item 1), except for the procedure that the seek operation is
performed in randominstead of sequentially.
The messages are also identical except that "SEQUENTIAL SEEK"
is replaced by "RANDOM SEEK". (Error code = 603)

7-65

DIAGRAHS AND REFERENCE MATERIALS

3)

REV.A

WRITE/READ Check

When a drive is
The drive is selected as in Item 1).
selected, precautions pertaining to the start of the check
operation are displayed.

+-----------------------------------------------------------------+
Use only a formatted blank diskette for this test.
Any data present may be erased.
If using drive A, remove your Diagnostic Disk.
Enter Y to start this check.
Enter N to return to the menu.

+-----------------------------------------------------------------+
The WRITE/READ ;heck is performed by writing and reading Head
Nos. "0" and "1", alternately, to and from for all sectors of each
cylinder, from the innermost cylinder to the outermost cylinder [0].
The check data is "6db6h".

+-----------------------------------------------------------------+
I
I

:

I
1

WRI TE, READ CHECK

I
I

:

:
I
I

Current track is xx

:

I

I

I

1

+-----------------------------------------------------------------+
(The xx represents the number of the checked cylinder.)

If an error is detected du ring the writing or reading of data,
the program displays following message:

+-----------------------------------------------------------------+
FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 604
WRITE ERROR
TRACK
xx
SECTOR - Y
SIDE --- z

+-----------------------------------------------------------------+
(xx represents the error cylinder number, y represents the error
sector number, and z represents the error head number.)

7-66

DIAGRAMS ARD REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I

FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 605
READ ERROR
TRACK -- xx
SECTOR - Y
SIDE --- z

+-----------------------------------------------------------------+
(xx represents the error cylinder number, y represents the error
sector number, and z represents the error head number.)
4)

Speed Check

The drive is selected as in Item 1). The speed check performs
60 times one-sector reading operationsof Sector 1 of Cylinder
No.32, Head No. 0, and the program measuresthe time for this
operation using the Channel 0 of 8254.
Measurement is performed by counting the 8254 interrupt, which
occurs every 1/18 second, and correcting by adding the number of
the final Timer Count value. Finally the program displays the
revolution speed in rpm (revolution per minutes).
expression:
(60 [times])/(interrupt count)*(18 [sec/times])*(60 [sec])

+-----------------------------------------------------------------+
The disk rotation speed should be more than xxx.x rpm and
less than yyy.y rpm
The disk rotation speed is now zzz.z rpm

Press any key to return to the menu

+-----------------------------------------------------------------+
(xxx.x represents the lower-limit revolution value, yyy.y represents
the upper-limit revolution value, and zzz.z represents the current
revolution value.)
The lower-limit revolution value is 294.0 for 360 KB drive and
720 KB (3.5"), 352.8 for 1.2 MB. (Normal revolution value - 2%.)
And the upper-limit revolution value is 306.0 for 360 KB drive and
720 KB (3.5"), 367.2 for 1.2 MB. (Normal revolution value + 2%.)

7-67

HEV.A

DIAGRAHS AND REFERENCE MATERIALS

If a floppy disk is not installed or a read error is detected,
the program displays following message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Disk is defective or not installed properly.
Press ENTER to return to the menu.

I
I

:
:
I
I

+-----------------------------------------------------------------+
5)

Disk Change Check

The drive selection is identical to that of Item 1). The disk
change check can only be performed for 1.2 MB and 720 KB drives.
The program performs read DASD type command of int 13h to confirm
whether the specified drive is change line available or not.
Ifthedriveisno change line available,theprogram
displays following message, allowing you to return to the menu.

+-----------------------------------------------------------------+
Drive X is no change line available.
DISK CHANGE is not allowed with this drive.
Press ENTER to return to the menu.

+-----------------------------------------------------------------+
(The X represents the drive name of the specified floppy disk.)
If the drive is change line available, the program displays
following message, then remove the disk from the drive:

+-----------------------------------------------------------------+
I

I

I

:

I

Remove the disk from drive X.

I
I

:
I
I

+-----------------------------------------------------------------+
(The X represents the drive name of the specified floppy disk.)
If the floppy disk is not removed within the prescribed time,
the program displays following error message:

+-----------------------------------------------------------------+
I
I

:
:
:
I
I

I
I

Error code = 606
DISK CHANGE CHECK
REMOVE ERROR

:
:
:
I
I

+-----------------------------------------------------------------+
When the floppy disk is removed, the program displays following
message, then re-insert the disk into the drive:

7-68

DIAGRAMS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I
I

:

I
I

Re-insert the disk into drive X.

:

I

I

I

I

+-----------------------------------------------------------------+
(The X represents the drive name of the specified floppy diskJ
If the floppy disk is not re-inserted within the prescribed
time, the program displays following error message:

+-----------------------------------------------------------------+
I
I

:
:
:

I
I

Error code = 607
DISK CHANGE CHECK
INSERT ERROR

I
:
:

I

I

I

I

+-----------------------------------------------------------------+
REMARKS:

The disk change check reads the Digital Input Register of
the FDC, then checks the disk change flag of Bit 7.

6)

Run All Above Checks
When "Run all above checks" is selected, the checks described
in Items 1) through 5) are consecutively executed.

7-69

DIAGRAHS AND REFERENCE MATERIALS

7.

REV.A

Katb Coprocessor Check (80287)

This module checks the mathematic coprocessor (80287).
When this module is called, the following message is displayed:

+-----------------------------------------------------------------+
I
I

I
I

:

80287 COPROCESSOR TEST

I
I

:
I
I

+-----------------------------------------------------------------+
1)

Coprocessor Installation Check
a.

CMOS RAM Setting Check
First, Equipment Determination of int Ilh is called to check
whether or not the coprocessor is installed.
If the the coprocessor not installed, the program displays
following error message:

+-----------------------------------------------------------------+
I

I

I

I

Error code = 701
COPROCESSOR NOT INSTALLED

:
:
I
I

:
:
I
I

+-----------------------------------------------------------------+
b.

Check by Initialization
The Initialize instruction (finit) is output to the
coprocessor, then the status word of the coprocessor is read
(fstsw) to check the installation status.
If all error bits are not read as "0", the program displays
following error message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 701
COPROCESSOR NOT INSTALLED

I
I

:
:
I
I

+-----------------------------------------------------------------+
2)

Initialization Check of Coprocessor

The Initialize instruction (finit) is output to the
coprocessor, then the status word of the coprocessor is read (fstsw)
to check the initialization status.
If the all error bits are not read as "0" with BUSY = "0" and
ST = "0", the program displays fo11owing error message:

7-70

REV.A

DIAGRAMS AND REFERENCE MATERIALS

+-----------------------------------------------------------------+
I
I

:
:

Error code = 702
COPROCESSOR INITIALIZE ERROR

I
I

:
:

I
I

I
I

+-----------------------------------------------------------------+
3)

Invalid Operation Mask Check (1)

All exceptional interrupts of the coprocessor are masked, then
operation is performed with an empty register to generate a stack
underflow.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 703
COP ROCESSOR INVALID OPERATION MASK ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
4)

Invalid Operation Mask Check after Clearing of Exceptional Bits

All exceptional bits are cleared (fclex), then processing
identical to that of Item 3) is performed.
At this time, if the IR bit of the status word of the
coprocessor is "1", the program displays following error message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 703
COPROCESSOR INVALID OPERATION MASK ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
5)

ST Field Check

Two items of integer data are loaded (fild) and added (fadd).
At this time, if the ST field value of the status word of the
coprocessor is "6", the program displays following error message:

+-----------------------------------------------------------------+
I
I

:
:
I
I

I
I

Error code = 704
COPROCESSOR ST FIELD ERROR

:
:
I
I

+-----------------------------------------------------------------+

7-71

DIAGRAMS AN» REFERENCE MATERIALS

6)

HEV.A

Exceptional Data Comparison Check (1)

The data from the stack underflow status of Item 3) is compared
with"l"(fcom), iftheydo notmatch, theprogramdisplays
following error message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 705
COPROCESSOR COMP ARISON ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
7)

Zero Division Mask Check

All exceptional interrupts of the coprocessor are masked, then
"1" is di vided by "0" to generate a zero di vide exception.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 706
COPROCESSOR ZERO DIVIDE MASK ERROR

I
I

:
:
I
I

+----------------------------------------~------------------------+

8)

Exceptional Data Addition Check

The data items from Item 7) that resulted in zero division are
added together.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 707
COPROCESSOR ADDITION ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
9)

Exceptional Data Subtraction Check

The data items from Item 7) that resulted in zero division are
subtracted from each other.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:

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DIAGRAMS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I

I
I

I

:
:

Error code = 708
COP ROCESSOR SUBTRACTION ERROR

:
:

I
I

I
I

+-----------------------------------------------------------------+
10) Exceptional Data Multiplication Check
The data from Item 7) that resulted in zero division is
multiplied by "0".
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "I", the program displays following error
message:

+-----------------------------------------------------------------+
I
I

:
:

Error code = 709
COPROCESSOR MULTIPLICATION ERROR

I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
11) Invalid Operation Mask Check (2)
All exceptional interrupts of the coprocessor are masked, then
"0" is di vided by "0" to generate an invalid operation exception.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 703
COPROCESSOR INVALID OPERATION MASK ERROR

:
:

I

I

I

I

+-----------------------------------------------------------------+
12) Exceptional Data Comparison Check (2)
The data from Item 7) that resulted in zero division is
compared with "0" (fcom), and the program displays an error message
if they do not match:

+-----------------------------------------------------------------+
I
I

:
:
I
I

I
I

Error code = 705
COPROCESSOR COMP ARISON ERROR

I
:
I
I

+-----------------------------------------------------------------+

7-73

DIAGRAMS AN» REFERENCE MATERIALS

REV.A

13) Mathematic Function Check
Addition, subtraction, multiplication, division, and the square
root operation are performed, then the precision is checked.
The program displays an error message if the mathematic result
is incorrect.

+-----------------------------------------------------------------+
I
I

I
I

:

Error code = 710

:

:

COPROCESSOR PRECISION ERROR

:

I
I

I
~

+-----------------------------------------------------------------+

7-74

DIAGRAMS AHn REFERENCE MATERIALS

REV .A

9.

Parallel Port (Printer Interface) Check

This module performs a loop-back check on the parallel port
(printer interface).
Before starting this check, attach the loop-back connector to
the parallel port. The pin connection of the loop-back connection
shoud be as folIows:

+----------------+------------+------------+----------------------+
:
Signal Name : PIN Number : PIN Number :
Signal Name
:
+----------------+------------+------------+----------------------+
:
:
:
:
:

Strobe
:
Data Bit 0
:
Auto Feed
:
Init. Printer:
Select Input
:

1
2
14
16
17

<-----)

<-----)
<-----)

<-----)
<-----)

13
15
12
10
11

:
:
:
:
:

Select
:
Error
:
P •END (out of paper) :
Acknowledge
:
Busy
:

+----------------+-------------------------+----------------------+
(Output signal)

(Input signal)

After attaching the loop-back connector to the parallel port,
issue the instruction to start the check.

+-----------------------------------------------------------------+
PARALLEL PORT CHECK
Attach loop-back connector to parallel port.
Enter Y to start this check when connector is attached, or
Enter N to return to the menu.

+-----------------------------------------------------------------+
The procedures for checking the parallel port are as folIows:
1)

WRITE/READ Check of Data Output Port
a.

The test data "Oaah" is output to the data output port (378),
then compared with the input from the same port. The
configuration of the data output port is as folIows:

+----------+----------+---------------------------+
: Bit no. : PIN no. :
Signal Name
l
+----------+----------+---------------------------+
o
2
1 3
2 4
3 5
4 6
5 7
6 8
7 9

Data Bit 0
1
2
3
4
5
6
7

+----------+----------+---------------------------+

7-75

DIAGRAMS AN» REFERENCE MATERIALS

HEV.A

If an unmatching bit is detected after performing the
comparison, the corresponding pin number is displayed in an
error message.

+-----------------------------------------------------------------+
I
I

I
I

:
:
:

PARALLEL PORT CHECK
Error code = 901
ERROR PIN xx

:
:
:

I
I

I
I

+-----------------------------------------------------------------+
(The xx represents the pin number corresponding to the unmatching
bit. )
b.

Next, using the test data "SS h" , an identical check is
performed.
WRITE/READ Check of Control Port

2)

a.

The test data "Oah" is output to the control port (37 A), then
compared with the input from the same port. The configuration
of the control port is as folIows:

+----------+----------+---------------------------+
: Bit no. : PIN no. :
Signal Name
:
+----------+----------+---------------------------+
o

1
2
3
4
5
6
7

1
14
16
17
IRQ Enable
not use
not use
not use

Strobe
Auto Feed
Ietialize Printer
Select Input

:
:
:

l
:

l
:
:

+----------+----------+---------------------------+
If an unmatching bit is detected after performing the
comparison, the corresponding pin number is displayed in an
error message. The error message is identical to that of
Item 1).
b.
3)

Loop-back Check of Control Signal
a.

7-76

Next, using the test data "05h" , an identical check is
performed.

The test data "Oah" is output to the control port (37A) and
the test data "Olh" is output to the data output port (378).
Next, input from the status port (379); the result is OK if
Bits 7, 4, and 3 are "I" and Bits 6 and 5 are "0". The
configuration of the status port is as folIows:

DIAGRAKS AN» REFERENCE MATERIALS

HEV.A

+----------+----------+---------------------------+
: Bit no. : PIN no. :
Signal Name
:
+----------+----------+---------------------------+
:
:
:
:
:

l
:

l

0
1
2
3
4
5
6
7

not use
not use
not use
15
13
12
10
11

Error
Se1ect
P.END (out of paper)
Acknow1edge
Busy

+----------+----------+---------------------------+
If an error is detected, the error message that identica1 to
that of Item 1) is disp1ayed.
b.

The test data "05h" is output to the contro1 port (37~ and
the test data "OOh" is output to the data output port (378).
Next, input from the status port (379); the resu1t is OK if
Bits 7, 4, and 3 are "0" and Bits 6 and 5 are "1".
If an error is detected, the error message that identica1 to
that of Item 1) is diap1ayed.

c.

Test data is output to the contro1 port and data output port
so that each signal of the status port go es ON, then the
resu1ts are checked.
If an error is detected, the error message that identica1 to
that of Item 1) is disp1ayed.

7-77

DIAGRAMS AND REFERENCE MATERIALS

11.

HEV.A

Serial Port (RS-232C) Check
This module performs a loop-back check of the serial port (RS232C port).
Before starting this check, attach the loop-back connector to
the serial port.
The pin connection of the 9 pins loop-back connector is as
folIows:

+---------------------+----------+----------+-----------------+
l
Signal Name
lPIN NumberlPIN Number:
Signal Name
l
+---------------------+----------+----------+-----------------+
: Transmit Data
:
:
: Request To Send
: Data Terminal Ready :

3 <------) 2
7 <------) 8
4 <------) 6

l
:
:

Receive Data
:
Clear To Send :
Data Set Ready :

+---------------------+----------+----------+-----------------+
(Output Signal)

(Input Signal)

After attaching the loop-back connector to the serial port,
issue the instruction to start this check.

+-----------------------------------------------------------------+
SERIAL PORT CHECK
Attach loop-back connector to serial port.
Enter Y to start this check when connector is attached, or
Enter N to return to the menu.

+-----------------------------------------------------------------+
The procedures for checking the serial port are as folIows:
1)

Input/Output Check of MODEL Control Signal
a.

Data Terminal Ready (DTR) = 0 and Request to Send (RTS) = 0
are output, then the Data Set Ready (DSR) and Clear to Send
(CTS) signals are input.
The results are OK if both DSR and CTS equal "0". An error
message is displayed i f either signal equals "I".
When DSR

=

1:

+-----------------------------------------------------------------+
I
I

:
:
I
I

I
I

Error code = 1101
ERROR DTR DSR, DSR ALWAYS HIGH

:
:
I
I

+-----------------------------------------------------------------+

7-78

DIAGRAMS AND REFERENCE MATERIALS

HEV.A

When CTS = 1:

+-----------------------------------------------------------------+
I
I

Error code = 1101
ERROR RTS CTS, CTS ALWAYS HIGH

:
:
I
I

I
I

:
:
I
I

+-----------------------------------------------------------------+
b.

DTR = 1 and RTS = 1 are output, then DSR and CTS are input.
The results are OK if both DSR and CTS equal "I". An error
message is displayed i f either signal equals "0".
When DSR = 0:

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 1101
ERROR DTR DSR, DSR ALWAYS LOW

I
I

:
:
I
I

+-----------------------------------------------------------------+
When CTS

=

0:

+-----------------------------------------------------------------+
I

I

:
:

I

Error code = 1101
ERROR RTS CTS, CTS ALWAYS LOW

I
I

I

I
:
I
I

+-----------------------------------------------------------------+
2)

Data Transfer Check using Various Baud Rates

The setting is fixed to even parity, two stop bits, and an
eight-bit data length. The check data is "00" - "FFh".
A timeout check during data transmission and reception and a
comparison check of the sent data and received data is performed.
The baud rates for performing the checks are used in the order
below:

+------------+
:
:
:
:
:
:
:
:
:

75
110
150
300
600
1200
2400
4800
9600

bps
bps
bps
bps
bps
bps
bps
bps
bps

+------------+

7-79

DIAGlU\MS AND REFERENCE MATERIALS

HEV.A

When the check is started, the following message appears:

+-----------------------------------------------------------------+
I
I

SERIAL PORT CHECK
RS232C echo back check
at various baud rates
Current baud rate is xxxx
Current test data is yy

I
I

I
I
I
I
I
I
I
I

+-----------------------------------------------------------------+
(xxxx represents the baud rate used for the current check, and yy
represents the test data.)
The program displays an error message if either the TX Shift
Register Empty status is not assumed during data transmission or
the Data Ready status is not assumed during data reception.

+-----------------------------------------------------------------+
I
I

:
:

I
I

Error code = 1102
TIME OUT ERROR

:
:

I
I

I
I

+-----------------------------------------------------------------+
Thesent data and received data is compared,and theprogram
displays an error message if they do not match.

+-----------------------------------------------------------------+
I
I
I
I
I
I
I
I
I
I
I
I

Error code = 1103
VERIFY ERROR
xx
Sent da ta
Redeived data
yy

+-----------------------------------------------------------------+
(xx represents the sent data and yy representes the received data.)
3)

Data Transfer Check using Various Data Lengths, Stop Bits, and
Parity

The baud rate is fixed to 9600 bps. The scope of the check
data varies according to the data length.

+-------------------+-------------------+
:

data length

:

check data

:

+-------------------+-------------------+
:
:
:
:

8
7
6
5

bits
bits
bits
bits

:
:
:
:

00
00
00
00

-

FFh
7Fh
3Fh
IFh

:
:
:
:

+-------------------+-------------------+

7-80

DIAGRAMS AND REFERENCE MATERIALS

REV.A

A timeout check during data transmission and reception and a
comparison check of the sent data and received data is performed.
The data transfer conditions to be checked consist of the
following combinations:

+-----------------------------------------------------------------+
No parity --\
Odd parity --\
Even parity
Parity 0 ----I
Parity 1 ---I

--+-+--

1--

--+-+---

Stop bit 1
\- Stop bit 1.5 -I
or 2

\-\-

Data length

5 bits
6 bits
7 bits
8 bits

I
I
I
I
I
I
I
I
I
I
I
I
I
I

+-----------------------------------------------------------------+
When the check is started, the following message appreas:

+-----------------------------------------------------------------+
I
I
I
I
I
I
I
I
I
I
I
I
I
I

SERIAL PORT CHECK
RS232C echo back check -- with various data format
Current data format: w data bits, x stop bits, parity - yyyy
Current test data is zz

+-----------------------------------------------------------------+

(w represents the data length of the current check, x represents
the stop bits, yyyy represents the parity bit setting of NONE, ODD,
EVEN, SP ACED or MARKED, and zz represents the test data.)

In case of a timeout error detected du ring data transfer or
mismatching of sent data and received data, the error message
identical to that of Item 2) is displayed.

7-81

DIAGRAMS AN» REFERENCE MATERIALS

REV.A

12. Alternate Serial Port Check

This module performs a loop-back check of the alternate serial
port (alternate RS-232C port).
Before starting this check, attach the loop-back connector to
the alternate serial port, then issue the instruction to start the
check.

+-----------------------------------------------------------------+
ALTERNATE SERIAL PORT CHECK
Attach loop-back connector to alternate serial port.
Enter Y to start this check when connector is attachd, or
Enter N to return to the menu.

+-----------------------------------------------------------------+
Since the checking procedure for the alternate serial port is
identical to that for the serial port, its checking procedure is
omitted here.
Only the differences are in port numbers and in the message
titles:

+-----------------------------------------------------------------+
I
I

:
:
:

Error code = 1201
ERROR DTR DSR, DSR ALWAYS HIGH (or LOW)
ERROR RTS CTS, CTS ALWAYS HIGH (or LOW)

I
I

I
I

:
:
:
I
I

+-----------------------------------------------------------------+
+-----------------------------------------------------------------+
I

I

I

I

:
:

Error code = 1202
TIME OUT ERROR

I
I

:
:
I
I

+-----------------------------------------------------------------+
+-----------------------------------------------------------------+
Error code = 1203
VERIFY ERROR
Sent data
xx
Received data
yy

+-----------------------------------------------------------------+
(xx represents the sent data and yy represents the received data.)

7-82

REV .A

14.

DIAGRAMS AND REFERENCE MATERIALS

Dot-Matrix Printer Check

This module performs a printing check of the printer's with
ASCII characters and bit images data.
Before starting this check, connect the printer to the parallel
port, then issue the instruction to start.

+-----------------------------------------------------------------+
I
I

:

I
I

DOT-MATRIX PRINTER CHECK

I

:

:
I
I

I

Is dot-matrix printer on-line (Y/N)?

I
I

:
I
I

+-----------------------------------------------------------------+
The procedures for checking the printer are as foliows:
(In case of test multiple times, only the printer connection check
is performed.)
1)

Printer Connection Status Check

A NULL code is output to the printer and the printer status is
checked. If an error is detected, the corresponding error message
is displayed.

+-----------------------------------------------------------------+
DOT-MATRIX PRINTER CHECK
Error code = 1401
Status
Time out error
Status
1/0 error
Status
Not on-line
Status
Acknowledge error
Status
Busy
Status
Out of paper

+-----------------------------------------------------------------+
2)

Printing Check of Printer

ASCII characters and bit images are printed repeatedly by the
printer, then you can check the printing results:

+-----------------------------------------------------------------+
Print test data
Text data
(20H-7FH,AOH-FFH)
Bit-image data (OOH-FFH)
Press any key to return to the menu.

+-----------------------------------------------------------------+

7-83

DIAGRAMS AND REFERENCE MATERIALS

a.

REV.A

Printing Check of ASCII Characters
The ASCII characters "20H"-"7FH" and "AOH"-"FFH" are printed
by the printer. The data is printed after printing the
following title:

+---------------------------------------------~-------------------+
I
I

I
I

:

Text data (20H-7FH,AOH-FFH)

I
I

:
I
I

+-----------------------------------------------------------------+
Printing is performed at 80 columns per line. If an error is
detected du ring printing, an error message is displayed that
is identical to that of Item 1).
b.

Printing Check of Bit Images data
The bit images data of "OOH"-"FFH" are printed by the printer.
The data is printed after printing the following message:

+-----------------------------------------------------------------+
I

I

I

:

I

Bit-image data (OOH-FFH)

:

I

I

I

I

+-----------------------------------------------------------------+
The control code for bit-image printing is "ESC K n1 n2"
(specification of single-density bit images). If an error is
detected during printing, an error message is displayed that
is identical to that of Item 1).

7-84

REV .A

17.

DIAGRAMS AND REFERENCE MATERIALS

Hard Disk Drives and Controller Check

This module checks the hard disks and the hard disk drives.
First of all, select which check is to be performed from the menu.
+--------------------------------------~-------------------------+

HARn DISK DRIVE(S) AND CONTROLLER CHECK MENU
1 - Seek check
2 - Write, read check
3 - Head select check
4 - Error detection and correction check
5 - Read, verify check
6 - Run all above checks

oI
I
I

Exit

Enter selection number:

+-----------------------------------------------------------------+
(In case of test multiple times, the following checks are
consecuti vely execu ted in the order listed.)

+-----------------------------------------------------------------+
1
2
3
4

-

Seek check
Write, read check
Head select check
Error detection and correction check

+-----------------------------------------------------------------+
Each of the checking procedures are described as foliows:
1)

Seek Check

The
function
two hard
you wish

quantity of installed hard disk drives is first set using
8 of int 13. The following message is displayed in case
disk drives are installed, so input the name of the drive
to check.

+-----------------------------------------------------------------+
I
I

:
I
I

I
I

Check which drive (C/D)?

:
I
I

+-----------------------------------------------------------------+
The seek check performs a sequential check on all heads
simultaneously from the innermost cylinder position to the outermost
cylinder position, then checks the seek operation.

7-85

DIAGRAMS AND REFERENCE MATERIALS

HEV.A

+-----------------------------------------------------------------+
I
I

:

I
I

SEEK CHECK

:

I
I

:

I
I

Current cylinder is xxx

:

I
I

I
I

+-----------------------------------------------------------------+
(The xxx represents the number of the cylinder being sought.)

If an error is detected in the seek operation t the following
message is displayed:

+-----------------------------------------------------------------+
I
I
I
I
I
I
I
I
I
I
I
I
I
I

HARD DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1701
SEEK ERROR
CYLINDER
xxx
HEAD
y

+-----------------------------------------------------------------+
(xxx represents the number of the cylinder detected the error and
y represents the head number.)

2)

WRITE/READ Check

Drive selection is identical to that of Item 1).
precaution is displayed when this check is started.

Next t a

+-----------------------------------------------------------------+
I
I

The data on the highest physical cylinder may be destroyed
l
by this check.:
I
Enter Y to start this check.
I
I
Enter N to return to the menu.
I
I
I

+-----------------------------------------------------------------+
The WRITE/READ check performs a WRITE/READ check for all
sectors of all heads of the innermost cylinder (highest cylinder).
The check data is "6db6h".

+-----------------------------------------------------------------+
I
I

:

I
I

WRITE t READ CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
If an error is deteced during the writing or reading of data t
the following message is displayed.

7-86

DIAGRAMS AND REFERENCE MATERIALS

REV.A

In case of write error:

+-----------------------------------------------------------------+
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

HARD DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1702
WRITE ERROR
xxx
CYLINDER
y
HEAD
SECTOR
zz

+-----------------------------------------------------------------+
(xxx represents the number of the cylinder detected the error, y
represents the head number, and zz represents the sector number.)
In case of read error:

+-----------------------------------------------------------------+
HARD DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1703
READ ERROR
xxx
CYLINDER
y
HEAD
SECTOR
zz

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

+-----------------------------------------------------------------+
(xxx represents the number of the cylinder detected the error, y
represents the head number, and zz represents the sector number.)
3)

Head Selection Check

Drive selection is identical to Item 1). The head selection
check makes each head seek the maximum cylinder position, then
checks the head selection status.

+-----------------------------------------------------------------+
I
I

:

I

I

HEAD SELECT CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
If the head is not properly selected, the following message is
displayed:

+-----------------------------------------------------------------+
I
I
I
I
I
I
I
I
I
I
I
I

HARD pISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1704
HEAD ERROR
HEAD
x

+-----------------------------------------------------------------+
(The x represents the number of the head detected the error.)

7-87

REV.A

DIAGRAMS AND REFERENCE MATERIALS

4)

Error Detection/Correction Check

The procedure is identical to that of Item 2) up to the
display of the precaution.

+-----------------------------------------------------------------+
I
I

I
I

:

ERROR DETECTION AND CORRECTION CHECK

I
I

:
I
I

+-----------------------------------------------------------------+
a.

In the error detection check, the test data "6db6h" is
prepared in the buffer then is written to the hard disk using
the normal "write" instruction. Writing and reading are
performed at Sector number 1 of the highest head of the
highest cylinder.
Next, the data is read using "read long", its leading byte
is destroyed (= "2ah"), then re-written it using write long".
If a READ or WRITE error occurs up to this point, an error
message identical to that of Item 2) is displayed.
The data is then read using the normal "read" instrucion, and
the the following message is displayed if no error has been
detected:

+-----------------------------------------------------------------+
I
I

I
I

:
:
:

HARD DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1705
ERROR DETECTION ERROR

I
I

:
:
:
I
1

+-----------------------------------------------------------------+
b.

7-88

In the error correction check, the test data "6db6h" is
prepared in the buffer then is written to the hard disk using
the normal write instrucion. Writing and reading are
performed at Sector number 1 of the highest head of the
highest cylinder.
Next the data is read using "read long", its leading byte is
destroyed (= "6eh"), then re-written using "write long".
(5 bits error.)
If a READ or WRITE error occurs up to this point, a error
message identical to that of Item 2) is displayed.
The data is then read using the normal "read" instruction,
and the read data and the test data are compared. An error
message is displayed if the read data and test data do not
match. Concurrently, detection of ERROR CORRECTION is also
checked.

DIAGRAKS AND REFERENCE MATERIALS

REV.A

+-----------------------------------------------------------------+
I
I

:
:
:

I
I

HARD DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1706
ERROR CORRECTION ERROR

I
I

:
:
:
I
I

+--------_._-------------------------------------------------------+
5)

READ/VERIFY Check

Drive selection is identical to Item 1). In the READ/VERIFY
check, all heads from the highest cylinder to Cylinder No. 0 are
read in track units, and the read statuses that detected bad sector
or any other READ error are preserved.

+-----------------------------------------------------------------+
I

I

I

:

I

READ, VERIFY CHECK

I
I

:

:
I
I

Current cylinder is xxx

I
I

:
I
I

+-----------------------------------------------------------------+
(The xxx represents the number of the cylinder being read.)
When the reading of all cylinders up to Cylinder No. 0 is
completed, the results are displayed:

+-----------------------------------------------------------------+
I
I

:

I
I

READ, VERIFY CHECK

I
I

:
:
:

I
I

BAD TRACKS •.•...•.•..••...•. xxxx
READ ERROR TRACKS ..•.••.••.. yyyy
GOOD TRACKS ..•••••..•••••••• zzz z

I
I

:

:
:
:
:
I
I

Press ENTER to return to the menu

I
I

:
I
I

+-----------------------------------------------------------------+
(xxxx represents the total number of bad tracks, yyyy represents
the total number of tracks detecting a READ error, zzzz represents
total number of normal tracks.)
6)

Run All Above Checks

When "Run all above checks" is selected, the preceding checks
described in Items 1) to 5) are consecutively executed.

7-89

DIAGRAMS ABO REFERENCE MATERIALS

21.

REV.A

Alternate Parallel Port Check

This module performs a loop-back check of the alternate
parallel port.
Before starting this check, attach the loop-back connector to
the alternate parallel port, then issue the instruction to start
the check.

+-----------------------------------------------------------------+
I
I

ALTERNATE PARALLEL PORT CHECK
Attach loop-back connector to alternate parallel port.
Enter Y to start this check when connector is attached, or
Enter N to return to the menu.

,
,
I

I
I
I
I
I
I
I

+-----------------------------------------------------------------+
Since the checking procedure for the alternate parallel port
is identical to that for the parallel port, its checking procedure
is omitted here.
Only the differences are port numbers and the error message
titles.
Data output port
Status port
Controll port

278h
279h
27ah

+-----------------------------------------------------------------+
I
I

:
:
:

I
I

ALTERNATE PARALLEL PORT CHECK
Error code = 2101
ERROR
PIN xx

:
:
:

I

I

I

I

+-----------------------------------------------------------------+
(The xx represents the pin number corresponding to bit number which
is detected as an error.)

7-90

CHAPTER
8

DIFFERENCE ßETWEEN 10MHz AND 12MHz

TAßLE OF CONTENTS
Section

Title

Page

8.1
8.1.1

MAJOR PARTS
Excluding P.C.B. Units

8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5

COMPONENT PARTS .••••.....••...........•..•.••.•.••••••••••.
ANTA Board Unit
.
ANT-RM Board Unit
.
ANT-RMA Board Unit
.
ANT-MT Board Unit
.
SPFG Board Unit
.

8-9

8.3
8.3.1
8.3.2
8.3.3
8.3.4

JUMPER SETTINGS
ANTA Board Jumper Settings
ANT-RM/RMA Board Jumper Settings
SPFG Board Jumper Settings
WHDC Board Jumper Settings

8-10
8-10
8-11
8-12
8-13

8.4

COMPATIBILITY LIST

8-14

8.4.1
8.4.2

Major Unit
P.C.8. Unit

8-1
. 8-1
8-3
8-3
8-6
8-7
8-8

8-14
8-15

(abbreviated)

I

...

Q)

Addition of
the Monitor
Conneetor
Cable

Monitor
Conneetor
Cable

2 Modification of the
ROM type

~1~ New Ver.

ROM BIOS

Version 2.00
ATR-B5 ~Y126814004~
ATR-C5 Y126815004
ROM type: 27128-15
Cable set 1f5EM
(Y126311000)

No Monitor Conneetor Cable
is used.

SPFG board unit
(Y12720110000)

Version 1.02
ATR-B3 ~Y126814002~
ATR-C3 Y126815002
ROM type: 27256-15

SPFG Board Cireuit design SPFG board unit
(Y12720100001)
modification

Code Label Modifieation
of the Code
Label
(abbreviated)

Cost reduetion
(ROM type: 27256 ->
27128)
Countermeasure for FCC

2

~1~ New version

To solve the format
error with the 360KB or
720KB FDD at 12MHz.

(abbreviated)

NA

No

No

No

Alphabet "A" is prefixed No
to the serial number.
[Old~ 010001 --New A010001 --

Serial Number Plate 03
(Y126025251)

Serial Number Plate B06
(Y126041651)

Modifieation
of the Serial
Number Plate

No

Hard Disk Cables for 12
MHz version should be
longer than the 10MHz's
beeause the loeation of
the option slot eonneetor is ehanged.

Cable set 1f5DY
(Y127300300§
Cable set 11 DZ
(Y127300400)

Cable set ff5BX
(Y126306000§
Cable set If BY
(Y126310000)

Hard Disk Modification
Cable of the Hard
Disk Cables

Serial
Number
Plate

NA

Earth Plate C is installed Countermeasure for FCC
(Y126039251)

No

No Earth Plate C is
installed.

Beeause the CPU eloek
sBeed is inereased from
1 MHz to 12MHz.

Substitution
Possible

Addition of
Earth
Plate C the Earth
Plate C

12MHz

Reason for Modifieation

Switeh Panel Label B01
(Y126042051)

Modifieation
the deseription of
the eloek
speed

Switeh
Panel
Label

10MHz

Modifieation

Switch Panel Label 01
(Y126027051)
or
Switeh Panel Label 02
(Y126027151)

Deseription

Excluding P.C.B. Units

MAJOR PARTS

Unit Name

8.1.1

8.1

N

:I:

3:

N

...Cl

~

N

:I:

3:

o

......

Z

m
m

~

CJ

m

(')

Z

m
:c
m

Q
."
."

CJ

~

:c

(1) Countermeasure for
FCC
(2) To allow to use a
full len~th Hard
Disk Con roller
To keep constant parts
supply

(1) To increase CPU
speed
(2) Countermeasure for
FCC
~3~ Cost reduction
4 Countermeasure for
the genius problem
(5) To im~rove the
execu ion s~eed of
the keyboar controller

ANT-MT board unit
(Y12620800000)

ANT-RMA board unit
(Y12620900000)
* This is an alternative
unit for the ANT-RM board
unit.
ANTA board unit
(Y12620600000)

~1)

Cable set ANT-MT board unit
/'5BT addition (Y12620200000)
(2) Modification of the
location of
the option
slot connector

ANT-RMA board
unit newly'
authorizea

ANT-MT
Board

ANT-RMA
Board

ANTA Board Circuit design ANTA board unit
(Y12620500000)
modification

No ANT-RMA board unit is
used.

(1) To improve RAM
access speed
(2) T9 ~djust signal
tlmlng

12MHz
ANT-RM board unit
(Y12620700000)

10MHz

No

No

No

No

Substitution
possible
Reason for Modification

Circuit design ANT-RM board unit
(Y12620300000)
modification

Description

Modification

ANT-RM
Board

Unit Name

I'\)

I

0)

~

1XI

::D

N

::I:

s:::

I'\)

C
......

»
Z

N

::I:

s:::

o

......

z

m

~

1XI

m

()

Z

m

::D

m

=n
'"Tl

c

(,,)

I

Q)

Y12620600000

-->

ANTA Board 1(1) Addition
of a filter
Y12620500000 circuit

Description

ANTA Board Unit

COMPONENT PARTS

Unit

8.2.1

8.2

(3C)

SCLK

GAATCK
50

6
GAATRF

(3B)

SCLK

R39
330hm

10MHz

CN1
34b

CLK
B3
2uH

50
C40 1.
47PF-l-

,
~A~,

.

R39
560hm

12MHz

,
GAATRF

CN1
34b
0 CLK

I

(3F)

TESTO

-----j

-l-39 TE ST1

C16
47pF

I

8042
1

m

47pF

lr C15

B2
2uH..1-

l'"VV'o.

B1
2uH

I

(1) Additional parts
C41 (X221221213)
C42 (
"
)
(2) Parts modification
B1 (X506000029)->(Y130202002)
B2 (
"
)->(
"
)

li
m

1

J-

C42
120pF

L...--...J

2 I

1 I

~

CN5

SCLK
(1) Additional parts
6
B3
(Y130202002)
(3B)
C40 (X221224703)
(2) Parts modification
R39 : 330hm ----> 560hm
(X154413302)
(X154415602)

OC)

SCLK

GAATCK

Modification

Countermeasure for FCC

Countermeasure for FCC

N

I

.....
I\)
s:::

o

»
Z

N

I

.....
o
s:::

Z

~

m

m

m

()

Z

m

::D

m

"TI
"TI

Q

Cl

~

::D

Unit

ANTA Board

~

I

Q)

To improve DMAC clock
speed capability.

Cost reduction

Location : 2E and 2F
Part
: FUJITSU
MB89237A-P
(X400892370)
* 6MHz version
Location : 3E
Part
: INTEL
8254
(X400082540)
or
INTEL
8254-2
(X400082541)
or

Location : 2E and 2F
: NEC uPD8237AC-5
Part
(X400082374)
or
NEC uPD8237AC-2
(X400082371)

Location : 3E
: INTEL
Part
8254-2
(X400082541)

(5) Modification of the
timer/counter

P82C54-2
(X400825401)

AMD

P82C54
(X400825400)
or

AMD

Front panel

I

-- CN6
(X600720220)

(4) Modification of the
DMA controller

I

0

Countermeasure for FCC

Connector CN6 is installed.
ANTA board unit

No connector CN6 is installed.

(3) . C<;mnector
addltlon

Reason for Modification

12MHz

Modification
10MHz

Description

OJ

~

:::c

:r:
N

3:

I\)

--.

C

~

:r:
N

o
3:

Z
--.

m

m

~

m

Z
C1

m

:::c

c
=H
m

C11

I

00

ANTA Board

Unit
10MHz

C10
~PF

(8) Deletion
of the 20MHz
asc circuit

RM14-2
20K

~ RM14-8

I
CN1
41b

IRQ7
CN1
37a

I

0 IRQ9

o

(10) New Key- I Location : 3F
board controlley Part
: C42051KA
version
(Y126813000)

(1E)

~19
I R 1 ·? 20K

8259A-2

~

(9) Deletion of 8259A-2
the resistors
~25
IR7

~

H~ 1

CR2TI R16 IX201
20M 0
<: 510K
(4B)
11
AhA
X20a
R42
C9
5600hm
15pF

12 GAATCX

Location : 2A
Part
: LCC type
(X6301l6802)

R80L286-10/C2H
(X402802868)

AMD

Location : 2A
Part
: SAB80286-1-R
*LCC type (X400802861)
or
INTEL
80286-10
(X401802861)
or

I

(7) Modification of the
CPU socket

(6) Modification of the
CPU

Description
I

12MHz

I

0

0

IRQ9
CN1
41b

IRQ7
CN1
37a

JX201
(4B)
11
open
X20a

GAATCX

Location : 3F
Part
: C42051KB
(Y126813001)

(1 E)

8259A-2
,.--,
IR1 19

(1 F)

IR7
~~5

-JOT

12 i

Location : 2A
Part
: PLCC type
(X630115820)

Location : 2A
Part
AMD
jrpLCC type N80L286-12/C2H
(X402802868)
or
INTEL
N80286-12
(X402802868)

Modification

I

To improve the execution
speed of the keyboard
controller.

Countermeasure for
genius problem.

This circuit is not
necessary because the
computer system does
not use 10MHz.

Cost reduction

(1) To improve CPU clock
speed.
(2) Cost reduction
(LCC -> PLCC)

IReason for Modification

m

N

J:

s:::

I\)

.....

C

~

N

J:

s:::

o

.....

Z

m

~

m

(')

Z

:D

""m

Q

1lI

~

:D

Y12620700000

(3) Modification of the
P-ROM
272S~-1S to~e

VerSl0n 1.

Location : 24A and 24B
Part
: ATR-BS ~Y126814004~
ATR-CS Y12681S004
27128-15 toBe
Version 2.

Location : RL1
Part
: 1S0ns to~e
(XS1000 90)

Location : RL1
(2) ModifiPart
cation of the
: 200ns to~e
(XS1000 20)
delay line chip

Location : 24A and 24B
Part
: ATR-B3 ~Y126814002~
ATR-C3 Y12681S002

Location : 21A and 22A
Part
: NEC
uPD4164C-10
(X400141646)

Location : 21A and 22A
Part
: NEC
uPD4164C-12
(X40014164S)
or
MATSUSHITA
MN4164P-12
(X400041643)

ANT-RM Board (1) Modification of the
Y12620300000 D-RAM chips

--->

12MHz
Location : 19B to 22B
FUJITSU
MB81464-10P
(X400S84643)
or
NEC
uPD41464C-10
(X400414641)

10MHz

Modification

Location : 19B to 22B
Part
: FUJITSU
MB81464-12P
(X400S84641)
or
NEC
uPD41464C-12
(X400414642)
or
HITACHI
HMS0464-12
(X400S04641)

Description

ANT-RM Board Unit

Unit

m
8.2.2

I

~

2

~1~

Cost reduction
New version

To adjust signal timing

To improve RAM access
speed.

Reason for Modification

"Tl
"Tl

~

OJ

:tJ

~

N

I

s:::

I\)

....

o

»
Z

N

I

s:::

....o

z

m
m

OJ

m

()

Z

m
:tJ
m

Q

"'-l



ANT-MT Board (1) Addition
of the eable
Y12620200000 set #5BT

Unit

CN~

1

6
7

8

11

11

11

11

11
11

~ ~ ~ ~ ~ ~ ~ ~

5

CN~

4

1

3

12MHz

3
4

5

6
7

8
9

11

11
11

11

11

11

~ ~ ~ ~ ~ ~ ~ ~

2

Installed
Part: Cable set #5BT
(Y126303000)
9

2

Not installed

10MHz

Modifieation

To allow a full length
Hard Disk Controller to
be installed in
eonneetor CN8.

Countermeasure for FCC

Reason for Modifieation

m
m

~
...oZ

m

~

:tJ

N

I

3:

I\)

...

C

~

N

I

3:

m
m

m

om

Z

:tJ

8.2.4

ANT-MT Board Unit

2

"'Tl
"'Tl

00
I
00

(1) Addition of
a delay circuit

SPFG Board

co

I

(Xl

Y12720110000

--->

Y12720100001

Description

SPFG Board Unit

Unit

8.2.5

1=

B
I

uPD765A-2

GAATFD

10MHz

IV

<-

I'>.-n>

">

J~

12MHz

Additional Parts:
R57 ~X154414720~
R58
"

FDAN

GAATFD

Modification

TI

uPD765A-2 To solve the format
error with the 360KB or
720KB FDD at 12MHz.

Reason for Modification

N

J:

3:

N

......

~
o

N

J:

o
3:

......

Z

m

~

OJ

m

C1

Z

:c

m
m

."
."

g

OJ

~

:c

-

A B A B -

A
A
B
B

-

4
3
2
1

11

11

6MHz

I
11

8MHz

11

(factory setting : 8MHz)

MONO

<--'-

: Not applicable
: Same as 10MHz

31

10MHz

I

COLOR

during 12MHz.

during 10MHz.

during 10MHz.
during 12MHz.

I

cycles ~note
cycles note 3
cycles note 3
cycle
note 3

10MHz

wait
walt
wait
wait

j
12MHz

11

11

6MHz

I

11

8MHz

11

(factory setting : 8MHz)

MONO

(factory setting : MONO)

<--<--- rote
note 44
<--- note 4
<--- note 4

2 wait cycles for EPROM (note 1) <--- ~note 2~
1 wait cycle for EPROM (note 1) <--- note 2

(factory setting : MONO)

-

-

-

<--<--<--<---

Prohibited
Use CPU clock for NPX clock
Use 8MHz clock for NPX clock
Prohibited

12MHz
Prohibited
Set CPU clock (6/8/12MHz)

Function
Set CPU clock (6/8/10MHz)
Prohibited

10MHz

note 1 : These selectable wait cycles are available
note 2 : These selectable wait crc1es are available
note 3 : Wait cycles for externa. 16-bit devices.
These selectable wait crc1es are available
note 4 : Wait cycles for externa. 16-bit devices.
These selectable wait cycles are available

CPU speed select switch

Monitor select switch

Slide Switch

-

-

A B A B -

A
A
B
B

A
B

-

-

A B -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Slide switch settings

ANTA
Board

J6 J5 J4 J3 J2 J1

Jumper

ANTA Board Jumper Settings

JUMPER SETTINGS

Unit

8.3.1

8.3

o

~

I

CXl

12MHz

I

I

COLOR

J6: A

J5: A

J4: A

J3: B

J2: A

J1: A

10MHz

<---

<---

<---

J1: B

12MHz

Factory Settings

=H

~

OJ

:D

N

I

s:::

I\)

~

~
o

N

I

s:::

~

o

Z

m
m

~

OJ

m

(')

Z

:D

m
m

o

.....
.....

I

co

<- .

Same as 10MHz

- : Not applicable

-

-

-

-

-

-

A
B
A
B

A
A
B
B

-

-

-

-

-

A B A B -

A
A
B
B

-

-

-

-

-

-

-

-

-

-

-

-

-

A
B
A
B
A
B
A
B

A
A
B
B
A
A
B
B

A
A
A
A
B
B
B
B

-

-

-

-

-

-

-

-

-

J7 J6 J5 J4 J3 J2 J1

Jumper

ANT-RM/RMA Board Jumper Settings

ANT-RM /
ANT-RMA
Board

Unit

8.3.2

<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<---

RAM size 640KB
512KB (Disable upper 128KB)
Prohib1ted
256KB (Disable upper 384KB)
Prohib1ted
Prohibited
Prohibited
OKB (Disable upper 640KB)
128KB ROM size (27128)
Prohibited
Prohibited
256KB ROM size (27256)
Select ROM sockets 24A & 24B
Prohibited
Prohibited
Select ROM sockets 23A & 23B

10MHz

Function
12MHz

31: A

J6: A

J5: B

J4: B

31: A

J2: A

J1: A

10MHz

<---

J5: A

J4: A

<---

12MHz

Factory Settings

~

N

I

s:::

I\)

.....

o

»
Z

N

I

s:::

o

.....

Z

m
m

~

m

()

Z

::Il

m
m

"Tl
"Tl

!2

iJ:J

::Il

-

A -

-

-

-

-

B

-

-

<- .

-

-

-

B

-

Same as 10MHz

-

-

-

-

-

-

-

-

-

-

-

-

-

-

A
-

-

-

B

A

B

-

-

-

B

-

B

-

A A A B B A -

A A B A A B -

-

-

A A
B A
A B
B B

-

-

-

-

-

-

- : Not applicable

B

A

-

-

-

-

-

-

-

-

-

-

<--<---

Primary parallel I/F: IR~7
Secondary 7arallel I/F: RQ5
Parallel I F on video adapter:
Disable parallel I/F

-

- AT com~atible FDD I/F
- EPSON C AX FDD I/F
<--<---

<--<---

A Primary serial I/F: IR~4
RQ3
B Secondary serial I/F:
Disable serial I/F
Disable serial I/F

- Standard settins
- Test mode of VC

<--<--<--<---

<---

IRQ7

<--<--<--<---

Primary register set (AT FDC)
Secondary register set ("
)
PC re~ister set (FDC)
Disab e FDC register set

10MHz

Function
-

J8 J7 J6 J5 J4 J3 J2 J1 J10 J9

Jumper

SPFG Board Jumper Settings

SPFG
Board

Unit

8.3.3

I\)

....I

CD

<---

12MHz

<----

12MHz

J8 : A <----

J7 : A <----

J5 : A
J6 : A <---J9 : A

J3 : A
J4 : A <---J10: A

J2 : A

J1 :A

10MHz

Factory Settings

OJ

~

::D

N

:I:

3:

I\)

....

o

»
Z

N

:I:

3:

....
o

Z

m
m

~

m

(')

Z

m
::D
m

=H

o

CI)

....

I

co

Same as 10MHz

: Not applicable

<- :

-

B A -

-

WAH mode
WA2 mode
<--<---

<--<---

Non-latched status
Latched status

B A -

-

-

<--<---

Select primary address sets
Select secondary address sets

-

-

B
A

10MHz

Function

J3 J2 J1

Jumper

WHDC Board Jumper Settings

Board

WHDC

Unit

8.3.4

12MHz

12MHz

J3: B <---

J2: B <---

J1: A <---

10MHz

Factory Settings

N

::I:

:!:

I\)

....

>
Z
o

N

::I:

:!:

....o

Z

m

~m

m

(')

Z

m
:::D
m

"Tl
"Tl

Q

b:1

!;g

:::D

~

~

I

~

~'(1)

OK (See *1)

OK (See
OK
OK
OK (See

MRS-MO Board

MRS- CR Board
MGA Board
EGA Board

*2 : Unit code Y12720400001 ---- Code view problem may occur.
Unit code Y12720400002 ---- Code view problem is solved on this verSlon.

*1 : Unit code Y14420620000 should be used.

Descriptions:

Color
~'(2)

OK
OK
OK

OK
OK
OK

FD1155C
FD1157C
MD5501-61

1.2MB

FDD
Unit

~'(2)

OK
OK

OK
OK

MD5201-57
-58

360KB

K.B.
Unit

OK
OK
OK (See

OK

OK

--------

-----

Display Mono
Adapter

OK
OK

OK
OK

ATRPS
ANPS

12MHz

10MHz

Power
Supply

Unit

Major Unit

COMPATIBILITY LIST

Main
Unit

8.4.1

8.4

c

OJ

~

::D

N

:I:

s:::

I\)

~

C

~

N

:I:

s:::

o

~

Z

m

~m

CJ

m

(")

Z

m

::D

m

'TI

:;;

Y12720300000
Y12720310000
Y12720300001
Y12720310001

WHDC Board

01

....I

(Xl

)'(a
*b
*c
*d

:
:
:
:

Should be "OK" but an additional compatibility check is required.
The location of the option-slot connectors are different.
XENIX problem may occur.
This board may not satisfy FCC standard.

Descriptions:

NG
NG
OK

OK
OK
(See ''(a)

Y12720100000
Y12720100001
Y12720110000

SPFG Board

(See ,',c & ''(d)
(See )'(c)
(See ''(d)
OK

(See ''(b)
(See ''(b)
OK

OK
OK
(See "'b)

Y12620200000
Y12620200001
Y12620800000

ANT-MT Board

(See ''(c & "'d)
(See "'c)
(See ''(d)
OK

OK

(See ''(a)

Y12620900000

ANT-RMA Board

NG
NG
NG
NG
NG
NG
OK

(See *d)
(See *d)
(See j'd)
OK
OK
OK
NG
NG
OK

Y12620300000
Y12620700000

ANT-RM Board

12MHz

10MHz

OK
(See ''(a)

Y12620100000
Y12620100001
Y12620100002
Y12620100003
Y12620100004
Y12620S00000
Y12620600000

Board

P.C.B Unit

ANTA Board

8.4.2

N

J:

:i:

I\)

....

o

Z

:>

N

J:

:i:

....o

Z

m

~m

ClJ

m

(")

Z

m

::Il

m

""Tl
""Tl

g

ClJ

::Il

~

LIST OF DIAGRAMS

UNIT NAME

V-CODE

PAGE

ANTA Board Unit

Y12620100000 •.•......•.••••.••..••
Y12620100001 .....•...•..•......•••
Y12620100002 ...•..•..••..••..••.••
Y12620100002A ....••.••.•••..•..••.
Y12620100003 ....•..•..••..•••••..•
Y12620100004 ...•..........•••....•
Y12620500000 ..•..•..••.••......••.
Y12620600000 ••..•.....•••••••••..•

A-l
A-2
A-3
A-4
A-5
A-6
A-7
A-8

ANT-RM Board Unit

Y12620300000 · . . . . . . . . . . . . . . . . . . . .. A-9
Y12620700000 · . . . . . . . . . . . . . . . . . . . .. A-IO
Y12620900000 · . . . . . . . . . . . . . . . . . . . .. A-IO

ANT-RMA Board Unit
ANT-MT Board Unit

Yl2620200000 · . . . . . . . . . . . . . . . . . . . .. A-l1
A-ll
Yl2620200001
A-ll
Yl2620800000

ATRPS Unit (Major Circuit)
(THIC-35 Board)
(Major Ci rcuit)
(THIC-35 Board)

Y126501000

· . . . . . . . . . . . . . . . . . . . ..
· . . . . . . . . . . . . . . . . . . . ..
Yl2650100001 · . . . . . . . . . . . . . . . . . . . ..
· . . . . . . . . . . . . . . . . . . . ..

A-12
A-13
A-12
A-13

ANPS Unit

Yl26509000

· . . . . . . . . . . . . . . . . . . . .. A-14

SPFG Board Unit (Sheet
(Sheet
(Sheet
(Sheet
(Sheet
(Sheet

1/2)
2/2)
1/2)
2/2)
1/2)
2/2)

Yl2720100000 · . . . . . . . . . . . . . . . . . . . .. A-15
· . . . . . . . . . . . . . . . . . . . .. A-17

Yl2720100001 · . . . . . . . . . . . . . . . . . . . .. A-15
· . . . . . . . . . . . . . . . . . . . .. A-17

Yl2720110000 · . . . . . . . . . . . . . . . . . . . .. A-16
A-17

WHDC Board Un it

Y12720300000 ...................••. A-18
Y12720310000 ...........•..•...•.•. A-18
Y12720300001 .......•..•...•....... A-18
Y12720310001
A-18

MGA Board Unit

Y12720400001

kEYBOARD

A-19
A-20

FD1155C (1.2MB FDD) Unit (Sheet 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-21
A-22
(Sheet 2/2)

...................................

HMD-720 (3.5 Inch HDD) Main Board

A-23

MFG Board Unit

A-24

Exploded Diagram (Sheet 1/2)
(Sheet 2/2)

A-25
A-26

A
+5
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1

5.~~,

f

60 CSPOO
59 CSPOI

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4

+5 3 Rl!Sl!1 Button
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RH10.1
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10- 6

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up

Pass Condensers ....• O.I}1F x 5

Addrus : C40 10 C44
(nol Iraced on obovl! diagram )

JeN<

TO J 1 ON
ANT-MT BOARD

TO BATTERY .B.'9.9
l
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....
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6V "I Z
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ORQO
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MEMR
MEMW
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Slave
Interrupt Controller

6 .... s 4E

....

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RMI
LA23...... 22 ......
21 ......
20 ......

GAATDB

CD

•

5P/EN 1

5

4(

o

IRQ9

LC32
2
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30K lOK

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.---,'3,-,7'-1CLK2B6 03
4 g~
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6
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DMA Controller

I

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g~o
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7b

4

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Processor E xt.
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A6

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READY

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02
01
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SMIO
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4

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C19

AI7

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RESET ORV
OSC
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+5

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DIS

VCC 31.1

A2
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DIS 51
014 47
013

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1

:A20
A2Z
A21

A6

AI.

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CLK
A20G

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ALE

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HLOA

1

f

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WS3N(U)
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AMI6·S
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53 20K
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XAO

1

I

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SA16

GAATABXxXA:9~

I

+5
20K x 4

IROVlu 6\
OROY 29

RSTO
WSON(u)
OCLK
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CSPOO
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00
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SA121-i4H7.......-.,.,'i'AA7-,:~2-----_-----.I

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I

C
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A16
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~~~
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14

m w:
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ENAS
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C9
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TC10+S
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43 PCLKN
5

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4

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A

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34
3 C OSC 47
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EQUITY m+/ EPSON pe AX
ANTA BOARD
UNIT NO. Y12620100000
A-1

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A19
A18

SA19
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L

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08

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03
02
04

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5
+
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L

1.3

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NC 29
HC 28
NC 27
NC I

10K.2
+5
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,

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31b
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430

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C20M ::~~ 18 2ALE XAI XAII2 ~n~=3X~A~lll~~~====}-;:±==d~~X:A:O=B=::j~ 7lTL---~it1it1ltttt-;::::~+t=f:====12~SOE-II S4 XAI32 XAO ~~ ~4E I~~: 4S ~::: RM~~: PCLKII ROYII 23 330 OU G24ll11 I~::: IR - ~~ceM 024S SI-II 29 ALE I PCSN b"33oft.----t-----......., 4S HLOA ~A RC ~~==~A~1 13aAI r RSCPU CLK 7:cl..11 48 48 rlr IEMWII j!!= GIIDA 1Bi:::1 IORII a.M1I XIDftIl 41 11171411 XMWII 41 140 ~OOWII R ,_ =: 13 C HAKI 31 AEII I RF20N ~ 1423 g:: ~f.4"'7,-_~0113<__.II 4~ f:.-:.-:.~ ~I:t-:.-:.~ 1~§I~~lAI17~~~~22i:~:~f~~~::::~:~~47i==!::~I:~[::==~====±~j RBTI ~I 1421 10 1422 013 AIS I SAIS~~~m====l====l:t;1 4 COFF RFIDII p;;---, "'"m&20 AIS :~~ 01214iS~~0112~~ 1420 0 LAI7 R g:~ ~__~A21 : t:::.~'-_!"~:_--_+----+_fo,J ~ I ~J" I I ::~1414AIS 17 :::All::~ D6~ ~!-~~_..... ;~~ ~ ~LA2L:,_~l:~'I~~~~~~$~~~~m ~!-~'!---"'" rt-1f-t+-H......,f-=......,H~':~ ~~-" 0.047_ ~9 .S 3 VSS PEREQ 10 VSS VSS 68-Pln Jr ~~CAP c~_ 80286 0.047_ RM4, ... 5 "'" CPU 02 ~"~t:~~OS !.~.:IIMr-'1 07D6 Num.rle.1 Proc....rExl. ~7~t:~oeOA OIS 6SOlS I-13 0lS E SOlS IS .. ~ 010 014 014 0 ::: SI 1013 ":::!":"'N.,.-'1g:~340-PIn 0 g::11 I~ • g:~ I 1012 .sos010 47 1011 __ Oll 870 1011 0os10 1412 a ~ 81OI4 S 01010 _ ALS245 7 • R40 07 I 07 A 107 ~'--'SDI~,--.+t----1H--!-lA7 17 I. 20K 12BI D6 oa Boa ~~;I~~l~~~j IS Ir01=:37.: .j CLK216 :g:oe I 6 :g: 14112011. y-+_t-_....__. 02oeg:OS ""'C 102 " ::114IS 4 803 3 :: 0100 2223 0001 20100 0 100 SOl !-~I"~ J3 ~ .1~ 32 '-~2tt==l=t~:~ :~ 111 L.~I-+_t-je_IMH--"f;o1 05 CLK 2 MOlS C" OIR 4 l~E~li~~~il~~:;N ::: ~ '-J28e::;J!IAC ~~4NeCKM COO/~~:~~ INT' 00 MOl HLOA GOU MOl i2 1I::::MDl:::m 13 NC ERROR GDHl I MOl O 05 R:~~ 2S _ W!..~: =~i F F .S R37 ~IOY ""'4:::0-----t---+-t-'~1l cl. .~ ~ ........ GMDLN Moa BlOQ vcc RER.. ~ tl ~-.l__+:t::j~+:::t~ GMDHN MOS ~-...JllIIL 1 C23 . . . VCC M04 20K_4 i C vcc OBI M03 0.047_ ~ ~:: g=g~i~~~~A~~~t+--~~~t~~.t.~~J~i rII a=~MD!I~j Ä-~E5lX 1J.lm GAATOB ."r.IIPWR~ =- ~ ~AATIO TM2G ~ ;5 H: .-.....--""'1 ~ T ,~. SOI"' L- := ~ r- I ~~ 7 = 2 MOl! 4E ~ 00 K.ybo.rd Int.rf.c. Ol.OII PIS 0201 * ~WI 43 PI4 CN5 IOK 5plK.ynbo«d OIN C.nn.c'.r NCNC 2PI3 PI2 PU P2700 l:ll.:::: 31 R30 · ' I OK . S ~ Pli ~ .~...('ij~l-...-=i~~=~.~5~KID=~C~L~K;_:_-..:N::C~1PIO P25 I •• NC ~:g ~~~A k~~- . "[\ OAn 39 i~:i~ ~:: 24Ne KEY .S ~40 VCC P22 ::Ne A20G GND 43•h 514." .5-jfl!EIS 1~ 47P VCC iTl PlVOOI P21 TO KEY UNIT BOARD '.Jr I. .1.. CI4 C38 PROG SYNC!2. C.11 47P F... FI ,.....!R~3~I-'\I\fIr::.:...;~ 81 7'i 08F KID [ K ~ JJ" 2 .... ,~_ 3 S • 1110.... ~ • S . .0-l;--7_t-_ Il4~~t~~~tI]I;~lt~~~~~i~~J~J~1~r,.....J~ g~ :~: ",_\0---1 0'7 A~~ ..., ~ ~27b POWER GOOO ·&RMI2 G~-fOP 22 91_ H .l.. 7 'XAJ.I. 10 0." & ... MD! AS 4E ~ T/C ...... ~=::;.l;:~ ,........{y-( L XD3 11'---I'f~l"ij'~~~~~~~I;~XI017~~~I~;IX07 --.f'ZO REift RMI2-' 2OK' !l! RMII-S 05 ~~ ~l~~i~~=l~I~~~~ll~:~~~~~~~~ ~~ I __ lLl~~~~~,,~1~4~E~I~~1~;~~~'5t~3~X[T~A~L~2--10~7~IIS~=~±=~±b=~i~XmO~7~==~I~I 1407 l -- ".. . "10 C XTALI 0611Ie~~~I~~~~~~IIXID6~~~~1011A~06 140 OS 17 X05 .:g: 3 21 3PI6 (3FI g::1 1403 A 8 r-- I I HIlQHlO' ...L XD8 311 ~ 7 EIIPR 13 6 '"AT _. .'55VOC VOC BALE 10CHROY AEN ORV RESET OSC OR03 ORQ2 ORQI -DACK3 -DACK2 -OACKI -10R -IOW CLK GNO GNO GNO GNO GNO SAI9 SAl B 5AI7 5AI6 5AI5 5AI4 5AI3 5AI2 SAII SAIO 5A9 SAB 5A7 5A6 5A5 SA4 SA3 SA2 5AI 5AO SD7 S06 505 S04 503 502 501 500 IR07 IR06 IRQ5 IRQ4 IR03 -5MEMR -5MEMW IR09 -REFRE5H -I/OR07 OCHCK DR06 OR05 -OACK7 ·-OACK5 OACKS ORQO .-DACKO M-MEMW EMR (,NO -IOC51S -MEMC516 50154 SOl 5013 5012 5011 5010 509 50e LA23 LA22 LA21 LA20 LAI9e LAi LAI7 -MASTER IRQIS IRQI4 IROl 2 IROII IRQIO 5BHE n lr~1~~~~~tt~~1~~t~~~~~~~~ H ~i~l~j~~~~~~~~~~II'SS-6I'~I~·-.11'2OI(1031111111111111132b= 5 L 12 "':0'.MJI.-/I 20K :~: --1 "r-- ~36=- L..- ' ~ 1 1- z" 1---"....... iiif •• '----",;100..i."lAINE02TAN AEN2 AENI 23 '----"!30~RSTN MlAEOI T~1 A4 CI7 .5 32 VCCGAATCK~ BCA .&00 GAATRF rfr 1A-+TofJm~~:i:~8:~~ C17 r::":-r ATAB XAI I ... _ ~ C8-BIlI 0.1_ ;T;. ALE '""" GA ::~0IFI4~2 __~XAl~IO XDa D& 40-Pln 04 XAI2 XAII XAO ~ XDI D2D3 ~-& C20II ~ IIlTAIl 18 XAII 13 XAII XA I XAO c~lJll~E~!IXD~'~"iD4 ~2ALE ColG XAI3 RF~O 2KR7 .,J,. R8 -&............. O.C r2 HIIQ ~ 4_= 10WIl 40 41 :: ::::H ~= RIII.-& -,I,- 2K 'l. .& XD~ ~ I -=:f~~~~~~g~3~ c't.:c~ XAII 111 GDLIl TEITIl ~&I3~~2OK:=~=.~O~ t_th L-tt-----,-=....lP"t---i c:. ~ t---< Ci HLDA I DXA :::- I::: EI t=jt~lU1LJ~~~:~:~:JI~R~:2~~~FS~W~02~·=I~:.~t-;n:;;;witii~$~$~~~~=~~~~~~~==$~ r-- f.ior;' ~ ~ - I 11-11 t~n~ : ;:03_R_4 --1t-1!"-rt-., Irr'='1;::==-:~A~~1~3ßAI A c: IlPCIN 1141&~~~~§~~~~l rf===1==:::2=K=~=13:;1tR=IIB1B~$a!at:~$n=~~9I'"A-EIl---DRQO-"~ 4 :CPU HLDA AD8TB DACKO . . .coc..I .0 m GIlDA ~ 7~ ~ 4B -,h;'#I . READY ~ GIlDA ,48 m - 41 4+-~-.:!4-a~ AO AO _I CLK EOP tr.3I=- .... -.l!!!!.+~==B~~":::O~ . ~:T HAI C I HLDA PIIl5 (l& 8A22 DI4 41 DI4 A18 0 lAll 1 t AEIlI -RF_ ~ I~:::t:~t!=:; ~1. VCC 31 I .a A21 DIIDI02 1A19 AI 10 A20 f~Aj23E~7aA23 r++-t---!!-ClRlTIl [~::j:IM;::~:: DIDI3 & 1474&1 D 1~~~~~'A!17~~~~I2IAI7AllA20A21 E80 'AI7~417~~11A117~~~~~~~~E81 DI2 LAI7 r-+++-+--"' 4 !' 1COFF RFIDII I)f,--, 12E I A18 All DI I r++-lr+t--,---izHI~J" I [,,A3 OMA2 - -'- 0.C331. ,&17 AlB DIO ::~ ~ t~!.!lo!!!c--!"~:----+----""'N 1 RI ~ =- :~"m;~~~7A ::: 17 ::: ; r-t+-+t+++_.a=:-:I:-i~;-:~ I I 1 -<1I .a 201<004 r == C8II ~O.l. t---< 21 = ALE CIl3 17~~~~~ I... :;I~~~4l =-!I~~~~~~jt~~~~~i~it~~~;;;;~;;;;;;~Jkf~ttt~tt~rtt~tt~I~~~~I~~ A20 I I I LAII~'-~~----+----""'N OUTI ....' - - - - - - - - ' c-- [,,- AI ~llCD7 ~ IIr ~I .2Oll._~ H 1,--,7_S _& 1074~ ~....... 18 3. .. 20K ~ I J R T~ 5 =- k 54 '----I~ClCl30~~;~N SI; • g;DO Nurnerlc., Proc...or Exl. DIO & Dio - .1 Dio 101& 4 E DI2 40-PIn g:: DI2 I DI2 0I ::::: 1011 • c{ g:? g:; "T BI! g:~ 12 g:~ g ::::~ &1t::1013I~ 201<.10 R40 g;oe ~ .i7.-. ::::IDo:O~ '-~ h~-:-~'ff{rffffff~~ :Do t= 201< DiDI o 12BI = A.IID,"114I:Z 04 D4 6 lD4 '-~&4 :: 1 1 +-I-+_~.-_....;.37.,CLJ(211 DIDI 103 ~:k ~ 2DID2D3 4S 101 ~ f. ~ L+}...../!~~grT.a:e312 PEIlEQ 14 DO L..f++++-r---;::1 11II10 '-- ~~2tt:~:ii!l 14 ..:~ DIR 1 ~:~ ~31 PUCK ~ L..f---1I+t+-t+---;;1DOGD2244~U- 11I11I1 I 1III1111141 §I§ B 134 iiiiöli HLDA '-+--tlH-i++----'.l~1IllUl L-~ft:t~h;;::P,~_Y CIA 11II10 4,--1III~10 .a RE~ 2 .~ ",' ~ ,lWL:::; ~~---E==~7~~ .0 SlR37OCl +__ 11II0 ~ h C23 _ 9VCC RE~~yp::4",0 2'OK.. .-t:+'II" ~ '"i ~o:i cif~'-----=gfil"--~~-~~~ lIBl :: 0-047. 10 CIIDI ~~~XA:2~~t+ __~~~t~~"~J·.L _A 11II2 ~ I.. . . . :::::m ~: ;;. ~ tos ~lll J,. GAATDB~ ~!:==~~t:~ 7"80287-8 "oe ~ :~ I~A~LrS:2J4i511~1;1111;1~1~1~~IXAI4 XD& lCD3 :g; ..... w---' L D2 22 \,J DO DO lD2 '-- IDO - A3 R 11 111 llD( P 7 ~t gj~~Hlf 5 g~ IIFl ~~:~~~~j'IRRIQQ4'3sj~~~~~~~LU~===2OI<=·=&==d~~""H-+--....:!:'-":"'34----o~Z :=~ 20 IRQ2 1012 18. D2 '7 VDO "llAI.I. llC llC IIDI .5 "'-- 4_ U ~ IIlT ~::~ Ht-2. INTA SPlCAIO't'11~2-c:;Hh OU -& ~ RD EN llL- I VCC ~• XDO34ClllllktJ!~ 8259A-2IRI I~ .a+: :_" 1XDO WR~:028-Plnvcc GIlD ~11r0.1 I Ci C3I " VII ~ I IMosterl 14 :~ ~ ::~ TO~ 2 I:: XAI. _ VII ~03.7lU.; .. C VII .so. 0-1.. llC _ :~: 24. 23. ~: 23b 22b 21b 36b 37b 25. ~x ~ BD3g~~ CAS2IR3:=~ 212~1 1 ~IO ""i ,~". ~ ~:~~1!2JiijjL:~~ CI7 ..11 ~IIlT RII y~ 0..-{2'~.. 1. ~~ UD 20 ~ VCC CIl3 L-U~==:j~; 8259A-2 ~CI2.a ~~tl!~j12~'E . . ~~~c;1-;::fg1 28-P'In I~/EII VII 14I. 0.1. R2!' &... CI j1._ .~n'IPEAKERINI~l •&TO JI 470Q"'2 ITI I ~ 4 ~-.tr7ON80ARDAIlT-LS ISlovel " IntIrrupt Controller H ' 3 ~ 8 L... 100P C +5._~~_::> 10V1.~~t ~220JJ I IOK " ..L GIlD 38lI RII12-1 _ RMII-6 201<~ .a IOK.~ ~l~~ii. lil;li~*ilil~ ~i~I~~~I~J~1~~~~l~·UI~· 111~1'~~~~:~~~ * ~ 4E 11 •• I. '.. _ a" I "'7'R21~ ~m~~~~~:~~~~·~!s~!~!!!~~~!·m~~~I~~I~~~~~~~~~~~~~~.~~!!m.B~~m=m~~~J~i~.~mm~ I~~~~ o'4El I K.ybo.rd Int"f.c. 1 -I G6 -x ~-lLJ~~~~~"~""~~I§J.~ ~~··i31~~:f--[m=~i~~i~=~~~txJ!j17~==~1I AD7 I . . . · 4 D 4D R EHA1S~~iiDE JIIII MII 11 III1I1MMMIIIIIIM IIX XXXX X XXXXXXXXX XX LX SS5 SS 5555 III151S1 ISAAA AA AA 11116 G 6G6X ..... A l AGil OICI:g I.2 dI KOK 28D EKR RFDEAO I23 4567 89101234& IIII 0I234 S6789 01234S6~E 111 I EH 01234 &6789 1II IIIII78.0 I23 R W M M DDDD D R38 HD~ CR;~~. " CI212~3 FIlLLCSSEIIIIRDDDDDDDDDDDDDDODAAAAAAAAAAAAAAAAAII8AAAAA AAAAAAAUUAA1112122 ~~~~~~~~~rr~~~~~ 1• 21 cOLOR 3AO:i:t~ 04D&~11"7~~~I~~I~~~llXXXII!!!~~~~11AD1~ X04 2AI D:A ~~: ~II 0123411678 WRCCCCC 3 ~:>-':":":"--+-D~:: 13Fl g: I",,~ :: o:g~~~::g 14 -;J;32.~':' ;];27P ~ ~ S IWI L.! DI AGI.- CKOUVDD1:::IZ41 IIA19_S 2_ .V J2 CIl4 C CNSDIN IlC:' -I DO ...... / P27 ~3I ~ I. . 1 ~ , ..0 GND I \ R All '01( : ~112 11 I R Q CKFI ...... RIS DI D2 K.yIlo.rd Co_ct.r 12opJC2 •• 2~II P2. .0 1I CI RRT r.... 25B808 Q2 IO ~2o .a .' ~ (301 PI.-- CIIIK _0 olR2.K ~ CN2 TO CNI ON ANT-RM BOARD ~: ~~~A 3•. ~ I<,~C4~I_~~"~!:±;RIOf;:~I'*==.a=~_I:~CL~K~:;~IlC:]~1 ry .... DATA I' ~i~:i? ~:; 2423 ow i~"'" Ir"l- ~~W24-Pln R24 L _C416V 10_ KEY ';: ...: J!:1~10 .a P22 1 0 . . 4 VII ~ 0.0047. [ -VCC S,4: : ~~&A .a l;J, ~40 VCC DO ~21 146818 R2& *0-m47P r ' . ~~ A20G ~" IOK 01lOK EQUITY m+/ EPSOf\J Pe AX 74ACOO 4069V8P 7407 0.1. t i ~:s40-PIn ls _11.1,:; J. 8042 ~17 ANTA BOARD All RDW.:..J.. • L.. - • .. I 40 AD4 ~14 llC 'I llC Spln 8 Ir, " ".. ro~~ 71=~ llC n llC 1lC 1lC 22 l I I I I C3I 22P ••• • .•-• , ,-, r I 0 T 7tr IOK. AB 7 ~ ~ ~~_~~II~~~~~~:::-~~U~ij~~~C~M~O~S~~R~I~O~I~T~~~e~C~I~O~~~~~~7i~~~~~~~~~'~~~~~~~~~!~tLJ T/C IOK TCI~ .-"o\fr-_--Q27b POWER 600D Y..-- ::17 tj t:: 1OK.7 IlIQII OWS -SVDC -SVOC .-SVDC SVDC -SVOC BALE IOCHROY AEN ORV RESET OSC OR03 DR02 ORQI -OACK3 -DACK2 ·OOR ACKI ··IIOW CLK 6NO GNO GNO GNO GNO SAI9 SAI8 SAI7 SAI6 SAIS SAI4 SAI3 SAI2 SAII SAIO SA9 SA8 SA7 SA6 SAS SA4 SA3 SA2 SAI SAO S07 S06 sos S04 SD3 S02 so, SOO IR07 IRQ6 IRQS IRQ4 IRQ3 -SMEMR -SMEMW IRQ9 -REFRESH .1I0CHCK ORQ7 ORQ6 ORQS -DACK7 ·-OACKS OACK6 ORQO ·-MEMR D_MEMW ACKO GNO -IOCSI6 -MEMCSI6 SOlS4 SOl SOl 32 SOl SOl i SOlO S09 S08 LA23 LA22 LA21 LA20 LAI9 LAI8 LAI7 MASTER IRQIS IRQI4 IRQI2 IRQII IRQIO S8HE R2I l. 22 :~: .a 410Q RI7 .a .a RIIII LA23 8 = = :: .. 17 JW....-.... ~:: ~ L-- o:~ SDI& ._I R..,M,•..-.... 1413 1t:~~~ _0 20K"s:~ -&~ _....-.... RMI 3~ 109 34 .. .. ..,,....-.-.... 8 220K" ~-.-.... 3o. 8 DC XDI x: Uill 7XAI&12Cl ~ ~14:Q;;::::;-t1l = ~~. 38. 39. .- 3 II~IXID7~14IiD7r:~1IR~7~liOIIR!lI'I'II~~t~~~~~~_J :: ~ =lIEI :::IR. 24 IRQ..:" :::: CII2Il : In RTAS ;41 R~ ~l~~§i~iU1U~M=d~wl-, RTRW XD2 11 CKII COD/iifi" 7 .., B 3 . _ CU< oll lIERIl RFHIl : 013 . . . ~t~~ -;}- oun OUTI ::;:In T1mer :~: IIITRII ITII 41 ACKIl E 0UT2 :"'0;-1::0 EIlAI 0I g:: DAKOI ::?l '--+-----11 I C_ 9DAKIIl 0DAK41l •&Il-CINI 2DAK71l E A 10EN XAO AI7 ~IIJI ~~-::::"1XA3 A20 XA4 00 ::: All ::..f., XA7 IRII v::=-="XAI ~CKIl .l~~!i:lXAI ~~~:1"X:'W CIDIIl ~ 1-"~~::7:1:::: c:= ~= ':~47 .1 6 t; mir13El t..t+~~g 2 l=a ~4 ~:~g~ Illilllllllllllliliil~i~~~~~tJP:JjC!LK!2~;~ ~ ~;; .~-. D2 ': ~ 1 I LI! QIGAATIO TII2G VCC llIIY" HL':: 1:lt-S·lI:;;;;;;;==~=~=++W __"'"1 62~ vcc IöCii 0.047. IVII PEREQ ~. .0 VII .-.....-=.=10V$I 68-PIn J,.. ~ c~ft 80286 0.047.~CAP RM4.S ~r",,=-----------J CPU j.o.e CI9 += I. ~ ....... 1 g 4 ,- 18b 1J!~~~IIII~!:2OI<0311113b 21 ~~AI ;:19b §l1D1D73:==~§20b o~ ~ 20K &. 40. 41. ~?: 41b rRII""7.;I~;:,-:'W,If-.- ... -& fiiii"Yr'+.a 4.7K 32b 42b :~: 42. :~. 48: 48. 11''1'1- 7.a ._ .---t1HIII9 >L1W._ .a so. In -yyy ...;.. 4 V-- RII7 H R DO 13 -;;&j;0~2OI<~~~,.zo~~~2=1'j~~t~..,I~~~~i~~~~I!: .a J W.... w+ ~ I- 2~ ~ :~: 9 f 2001101 1.....-- 27. 11I....Jofo'lr--&N ~ 49. 12 1A1.:b :~ 3 1A1& 8b7b 1A14 8 _ 1A.2:: :4·~:!Eij SAl 7,~1A1 8 lAllO 4b13. 12. ~t:~p&!j rr-- 1A7 :~~ ...... 3~11 rr-9. .&",12 -& CIIWI A20 I I' 34. l~~;;;;=====8 33. R4 ~:~: 47b 35. 045. 0:~: ~~~~ ~ ~_,~~e:.. ._'.. _'. ~_' Il = - - 0 Ib .a~~ ..r. OE-II lIEIIRtI 03Sb .& ....a 49b ~ 32. IK 1~~~~~~~'IIII-III'I!!~~~~I'~~3Ii88ll;~~~~~136. .. R1I8-4 34b ~:: M:3 lAll _ I I .. ".. IB. I-I 71T"E 26. IC-I 1 3 p 1~~i~;,~~~~~iii~;;ii~;;::~;~~~~~~~~~III~~'~~~~II~~;!~~~~~~~~~~~'!IIII!!~~~~~~~~~~~~~~~~~~I~!t]~~!!!!!!!!!!!!!!!!!!!~!!!!!!!!!!!!!!!!!!!!!!!!!!!I~~~~Rj3~2;4:7'0Cl11~~~~:~~5:~:~~ ~-17 (rR~~~~~~~~~~~~~~~~~~~~~i~~~~~~~~~~~~~~~~~~~~~~~~~f~]~~~~~~~f~~b:~; ~~~: 4,.m3 t-=" o N M (12MHz) Unit No. Y12620600000 A-8 +5VOC GNO o 0: « z u o m I- , :::E I- z « z o z u o I- I T F E G H .... ."3 MD 111 o c B A I" 13 12 • 11 10 9 • , IID7 •• 11 IID7 • 11 " 3 2 1 0 •• 0 vcc 2 .a;.0.1' - .a O-.I~,VCC 2A JRAII~_o4~---------------------------nr~~~~~~~~~~~~~~~~~l~=l=+-.., I ~ä<.-U olKMlI _ _ _ 3 5 RR ""EE" UU.... u 504. 60 CUM4 :~ =: ,201ß • , IßIO Iß, :: :: A .&V~ :~~ .IIV .&V 0 0 lD Z a 1111 127 VDO'l'rq .......~.L'•• IIV ~::: o-..~_.,.. ... ~ 1144 = :: ::-~~"" .11. _ L> L-- 3 r;==::::il~::,,•• .----LI 11" fIl iM 1-' 112 ~:g ~::K .. 0 02" 027 0411 C Cl : :: 11 0 L 0 0 0 0 0 I 0- 0 0 9 EII:~RO-:-~=22--------_nmtt_-___tttt__;::::::============~8::J1"~.J2 Ci' ~ ~ J3 11 ., ..14 XA 13 I1 11 0.1" 11• • 10 I ~ D7 • I i • I 4 •4 6 : !FI 1 I °II!f: I ~ 0 I 0 .. C • I 0- I Ol 0 lJ.~ IJ9 l!J ? 8~ C~ 11 I~:> ......-Il i 15 ~~ 0 h DO DI I-Dl 1I DO .. 1T"1 ...... t==:::;::j'~ 11 ~ DI ~ 0 ''=-'I ~ tfI Dll!-1.....~iil~....!DO~lf"-1I2 • 4 • • 6 4 : 4 :> , 3 ° ~ ~ VCC 20B " Iil?~: GM) M • A7 e 11 : OE 3 : I ~ I ~ B ~ °0 H-I-~ I.ClIlASii:i ~W ~'~V:CC==Ne~~ ~~ _21A .. 1.-+-1----1-.1-.1.1..., 8 ~§~~~15° .. r..-4-I-~L..10111 ~ • 0 4 7J D~HMD ~W 10.1 c I 4 5 ...--H-.f0!!...,;I5l' b-!!.. 0I 0.1 11 A7G I f- =~~~...., Be c.v--~"""*'l. I ...--' 13 B I-- :.h 19B OE M 3 DI~ 12 DO ~-4--------==1 -M 0 14 f- vcc 9A m f~~~§~~ 3 ~ ~L~i~~~=======::::;_, L-1+-If-Hf---------1f-+t-+-+-----------=-=-----!..:---I-iJI 11 DO 50 VCC ~ I- DI~ - Icl./ " Dil!- - l----~'*l; ~ l----~_!l'_l 2 I 01'-'- a° 111 I D7611D ~I­ f- 6A - ~ f1.lIt2~ ~ !.ME~~~Et~==============t::t:ii--------l:---r-t1 11 YCC .a D.I"FlVCC eA 1 , IID I 5 6 & 4 4 4 3 3 lEI 2 2 ~ CIEN ~.: ~ 7 r;:::i 111° ~·~t===========.;==l=+=+=+=l==;:;:::::=:;~:;-l r-~ 11 11 C C XAo:' : 4 .&/)(.. 15 6 10 I I I • 0.1" 11 Y! DI DO .a0-,,, ~:VCC 7A ii :: 24A ;"1- 0.1" ~ ~ tti ,• i l.---J l.---J .,~I"~9~~~~~~~~~~~~~~gfl~~~~~~~~~~~~~~~~~~~~~L J Z 5 2! 1ß3 GND Cl Cl IZ Cl X.. 142. . .14 13 12 :: GND a: .S/XAI 64FLAT eJIllII' (TSUCHIYAIIIII M;';,~::~ .0,1110 . . 0020 4 " ::: EOIO~OBA ~ ~ CSiiiii"!-!a9~~~~~~~~~~~~~~~~~~~~~~~~CIlANXiiiiiiiuI ~ aIRlir ~ - ~~ 4 23A 0.1" Iß. M .a .& :::~ - 4A .11- 5A - 0.1" .a 1ß13 G .13 • ..2 3 o : . ; ; r - - - - - - - - - - - - - - - - - - - - - - - ..... _ . .a IID 111 ......J-III.G .... 20. ~_ EIION ~Ne..!._ 112BI ~~ D.I,,!'1 VCC NEC GB LIIEGCIO" -,._IO _ II 1I,3N .... 01'0 HL N 11 D40U !!- 1lA2Kl1 ~~I m E . .III 'i- A I1I2N J J J J J " _ IA I 6 4 ~4D12-­ I DO 114_ ,aura 4 .-+-... ~~IIRii 0 A~ ~~ '" Z L> 1_ 0 I- lfEY.9j' a&1Zi::::;l~~::::::~=============~_W-.uJ... :~R~: 022 9 18' RE9 'Rmr b2" IlI'HNIß llIIWIIu 549 '"' y :: G 171ß :::: :~ 6 1 11 14 I~ 8 22 ~ 2 5 1I...; 2 ~ SI j!1O I , 91R eur Jmr ., .a .a _~ vrr .. "''I ~ VCC 33.34.31.41.51 ~W.I" 1 ~44~~~~~~I~I~i 40 .. ~~ KlI11" DU... , ~ ° ~ g wr ~ u X A ~ :~ 16BI 0 D D D 4. 1 2 I 11 33G eIß I!III UII IIß 1111.. 3 !J.'-4.1.,.I' Ne x A 114' fILIICI I>-' A T M I:: = ~ ::: lfff 0.1" A48 111 TVI' :::: EOI091EA IIIß 64FLAT 141ß ITSUCHlY 2 AI :: ~ ~ v,. ~ loH L :11" YDD Cf-l&L-..:..--G~===============~~....JJ,,,,eiß .AI8I~:ii-----lH---------------------II. 17 . . .... FUJITSU MB674 8 74108 XIIEJIIW ~ 021 Jion, "3 411 r-----;II:=:II~C~C~EL:.:--;V;jjDDD1~2&~_1~.&V ALE - oll II~~~~~~~~~~~~~~~~~~~~~~ ~"r XA ~ 23B .a In I Il 4 3 .~ lcu f "~ 5 4 3 MD 10 7 ~ i D7• •4 •5 6 I • 4 : !FI 3 2 I I I I ° ° ° ° ~ III ~: VCC lifi _ 6 10 I ' I 11 ·7 iI D7, :• 6 4 : lEI ~ 11 6 10 I. , I 11 ., 24B 7 ..14 13 ~ 12 I VPP VCC o~~x; 2 MD ~f 111 17 22B M ..7B 11 5 • r •4 46 : 4 I • 00 1 m ~ir O D3b7 2 I I o 2 I L.-_-.....I 3tlll. "y..y.. .,4_ ~·~21 7 O.loy In. TOKO 201 JHT 2006P lTOK AOL-200SI XiHf uo;t13,......_ _..... XAO I 2 3 ," 11 7 • 9 10 11 8 1 12 13 '" " 111 XA XA EQUITYID+/EPSON pe AX ANT -RM BOARD UNIT NO.Y 12620300000 A-9 T c B A D F E G H I..... III)IIS 14 13 12 11 10 9 8 ~.3· "'.3& MD7 MD7 • 6 IS 4 3 2 I 0 unD ... , •• l vcc 2 .0 0.1_ 4 GND IA 2A JRAM I IICI ~iic _tU1 IICI olKlWI IICI D40tU1 RA E ER .EIl8 RAM RCK O; · 7 r - - - - - - - - - - - - - - ~ .8 NEC ...I·:L...I'EI.IlL .. 065006 ~ • LMEGCS o.:..I:..:O'-- 0.1" ~:: ~~.,..'A~ ~=~: Ne.l.IICI E1'112lD1 3 .8! ~:IICI I IICI MA' R.IN AA 0 F 0 IICIQt:" RA234111 E . .RI 0.1" J J J J J .Il!.d,ft 0.1" MOllS .5 tiiGii 4 b2 b23 b44 ~V O-"~>--1zfz.:.,:..--I~.. ~fIF.lS. o a: ~::: «U GNO lIIZ tZ r-t- GND « o .IS R2 R A A Z o - ~ ~ J3 R A F 16 .lStRI .20K R M L o-:b:.::2=2-----------------ttlitll----tlit--;:=============~::::J nmiI( R AOOOOOO ° ° 8 « 5 R A M '1°0-000 I HJ2 ? .1 .23 .24 .27 .45 bl b41S GND 20K A e B J 4 o~ A A I IS IS 1 ~~8~ OD - I 8 ~ 7 AI4 ~ 13 ~ 12 11 6 10 I I 8 2 7 8 • MD I 6 4 4 3 IE) 2 I 0 4 3 2 I 0 la Oll ~ III I 6 4 4 : IF) I 0 1 I . ,........z - -er D~;1ii 8 I 4 18 ~~8 0f!.!-2-' 'llr ~ A8 I----' l . - - -........--!-!,~ 1 i Dt~ 3 ~fh 6 ~~ RESH ~ IB b24 B 74S08 X_ o·A1d!lIL_ _ 6 .... R R ce A A A A RFHNIIl lOH L G===============~~....uJ .... G llIilWIiIIl vss VS9 vss 8 0.1" ! oS 3 I I V lt XIHf o,a3g::=~~ XAO Oi I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 80 eDR 11 CIJ[" ft" 147 ~~ o~ 10A VCC 4 12A ,t.tI- 13A VCC 14A X A I 5 0.1" X A I VCC MD .8 6 ~ 0.1" .... ~ ~I I • 8 7 8 8 4 3 T -l D3ti'77 ~ VPP VCC _ 238 0.1" oS 1x.. ,A' 2 AI47 13 ~ 12 11 6 10 I. • I 8 7 8 8 8 I 6 4 4 31E) 2 1 0 er 'llr MO 2 D7 8 8 4 3 1 I 0 7 1 ' I o YPP VCC ~- 248 7 AI4 ~ "2 23 12 5 11 6 10 I 14 ' I 4 ~ ~ I I 8 6 4 4 ~" : IFI I 0 ~ ~ 'llr 4 VCC " ~. ilf 7 I 8 4 D7 I 8 4 3 1 I 0 o _ lI.1 228 M A7 8 8 8 8 4 3 2 I 4 6 4 0 o I ~ 1WI CAB 1 • 0 "H 1 ~ 1 1 WE I 11Y'i1Y'i. N 0.1/1 1IDr :Jr ii5ih.b21 D31!Hk .ISV MAe 44 7 13 I 41 8 10 4 3 2 I 0 ° gg m O.l~VCC 3311 ~W.14 ](Dll I VCC o.l"ii:_ ~w A A 33.34.38.49.51 EER DD D D ltul MIIA 48 I 2 0111_, ~ 7 I 13 VCC _ IIA 1 Ne ~4.17.1' ~ 2IJI ~ 1.3.. ~ o I 8 0.1" oS tul TR'r ~tNCl 4tU1 2 VS9 ~ .-+-+-,+oIiü.. 0 r----;=::W DO t!!....-~......-----I 0.1" FUJITSU M8674 48 549 SM 8tUI 3 1 M R NlUI A SAI8 b43 A 8 SAIIIlUI 17 ;1142 17tul T 11111 16 ~HI M IBM 15 ;}fü" 2 141U1 14 r---+-I--------------------~ 13M 13 IftJI EOI091EA 12 1 11 11111 64FLAT 10 1= ITSUCHIY Al 9 22 IIlUI 8 (681 7M ~ ~ 8 E 1 I 4 6 D3iMD 4 10 ~ t=~=~~~ ° Dtth .8 21 YOD VOD ~ 8 4 3 M 8 8 . NE oe M !.ME 48 a!l II 8 4 3 I I-- oS ALE OE A7 DO ..,1'-4.l.._------'I""'1 l.-_ _...IL-!,;14~ ~ l.---....5.--!-!'~ 4 L,.----.L-J.!LI 7 L,.----.Il-.,J,.I I ~; D1.!..... 8 8 I 2 5 ...., MD 0.1 "" VCC "~ _198 ---:.:I2~ - vcc 9A -M Z U o h OlL OD f!!2......1>-- ° ~~ 14 01 13 DOIL..---~::., (\j t- D1h 24A ,,,. D7 r;::J r-~ VCC "'GND .OIXAIO I 0 4 3 2" I a.2 044 ~h-w - :u ~~~ 0.1/1 23A AI4 13 12 11 I 10 I 9 I 0 8 3 7 0 :~~ GND 2 7 2 5 6 .O/XAI XAI4 D1~- DO !':'1 VCC Ei- 5A .0 ~~:'" ce 0.1/1 .ISV .ISV 4A 6A 504. 60 11281 4 _ ;Ihci 4.1 1 00210 • 000 74_ O"lay In" ADL-Ie05 ~ RLI .8V~"'7 0.1" .Ir X' . ,.... ,.... EaUITY 111 + /EPSON pe AX (12MHz) ANT - RM/RMA BOARD UNIT NO. Y12620700000/y12620900000 A-10 PG ~ CNI CN2 .5V r.N~ CNIO TO POWER SUPPlY UNIT CNII l OW GOOD .5V .12V -12V GND GND GND GND -5V .5V .5V .5V ~I ~3 ~4 C6 Cu.bJo; Set NO CONNECT +5V GND GND .12V :::: C4 ~ !~3~F ti 33/lF~ ~4 fi o-L-. o-L.. o-L.. '16V _7 • CI "I,. + - -. 33/lF • 16V ~6 CN6 CNa .12V + _l C2 f,- AI 2 3 4 5 6 7 B 9 10 -5V 11 12 13 14 15 16 17 IB 19 2 21 2 23 2 2 2 2 2 29 3 31 BI 2 3 4 5 6 7 B 9 10 .5V 33/lF 16V C3 x3 '-'+5V 0 J~ ICN9 -12V I .5V 1CN7 r; 16V C5 _5 71r GND - ~2 -* +5V .4~bl 1CN4 1CN5 :sRTl ~+5V -- 11 12 13 14 111 16 17 IB 11 20 21 22 23 2 2 2 2 2 2 3 31 CI 2 3 4 11 6 7 B 9 10 3 ij...I2Y ~ - '-- - - - '--- -5V -12V b46 b311 +12V a22 a a a a a b 11 L..-.- RESET ORV h.' _IROI b 12 13 14 111 16 17 IB 01 2 3 4 !I 6 7 B I 10 a 12 13 14 Itl 16 17 IB POW GOOO IOCHCK S07 S06 S05 S04 S03 S02 SOl SOO 10CHROY AEN SAII SAlB SAI7 SAI6 SAlli SAI4 SA13 SAI2 SAII SAIO SAI SAB SA7 SA6 SA5 SA4 SA3 SA2 SAI SAO .3. _ a36 _ 11 } _lIV OR02 OWS -SMEMW -SMEMR -IOW -IOR -OACK3 OR03 -OACKI OROI REFRESH CLK IR07 IR06 IROli IR04 IR03 -OACK2 T/C BAlE ~E 71r r"" TO CNI ON ANTA BOARD OSC SBHE lA23 lA22 lA21 lA20 lAll lAIB lAI7 -MEMR -MEMW SO B SO I SOlO SOli SOl2 SOl3 SOl4 SOIlI -MEMCSI6 -IOCSI6 IROIO IROII IROl2 IROlli IROl4 -OACKO OROO -OACK5 OR05 -OACK6 OR06 -OACK7 OR07 b21 -MASTER a,:........ a~ CNI2 DESCRIPfI()IIS Gable set #5BT is not installed on the Y12620200001. cPtion slot locations 8 bit-bus connector Unit Code 16 bit-bus connector Y12620200000 CN1, CN7, CN8 CN2, CN3, CN4, CN5, CN6, CN9 Y12620200001 CN1, CN7, CN8 CN2, CN3, CN4, CN5, CN6, CN9 Y12620aooooo CN1, CN7, CN9 CN2, CN3, CN4, CN5, CN6, CN8 EQUITY 111 + /EPSON pe AX ANT - MT BOARD UNIT NO. Y12620200000/y12620200001/ YI2620800000 A-11 2 4 7 9 102718 8 24 23 22 : • R21 7.5K. • C8 R2C 11< I .,pCI ~ ~ 6 HA GNO Vret RT 2 16654 A RI 0.1 R3 1000P D8 Il RI5 47 I--< I JooK I',.r:-- D4 ~ RD4.3 8 8 ~ R32 ~ 910 ~2" .. IK R27 5.IK 47K RI7 510 200 PRECISION ADJUSTABLE SHUNT REGULATOR R3~ 100 - _I- 24 -,.. 0.1 rc;;)- ~ , 13K 012 .I ". 151588 R44 4.7K • 4.7K 013 100~1---'" ~ K ~ , R40 : R45 I 43 _. ~ 2SCI213A DI Z~_ Q8 ~ 1-4.........c~~ 151588 ~ R35 lOK : ~ l,R42 C13...J.51588 ; 4.7K 10..1 T R41 4.7K R37 ~ 3.61<. 2SC 1213A R39 3K 09 151588 ~ - 7 5.IK - ...- : R36 2K • R......... (2] ~*) R R31 <1- IK K ~ 2~Z~ ~ --~~I 0.0 RD5.1 R34 lOK R33 3.3K • Q3 C5 C4 .. 151588 5 100 C2 RD l5.1 --I ....pell 151581 R28 lOK 7.5K R4 56K R30 100 .. 8 7 R2 2.2/l Hr- ~8 R25 150 .. 750 25C~ 121 ~D3 OT CT I CI4 ~ D5 151588 ~",r151588 (Deo d Band) (Error Input) 3 C9 D4 2 OUT VIN ZI _:~.... 5 4 CI 0.1 R23 IK ~~, Q,~ ., ..10.1 .D7- R28 620 ':~ OJf At 5;il2~ K ' R24' " 20 2629 28 25 R22 lOK H~~ ~ 19 15 16 21 17 TL- CI2 0.1 151588 R46 .~ 6.8K PHOTO COUPLER (P C 2) (~~~t) (P Cl) PHOTO SCR COUPLER EQUIY 111 + /EPSON PC AX ATRPS UNIT (THIC - 35 BOARD) UNIT NO. Y126501000/y12650100001 A-13 ® OUTPUT SOCKET RIII CI06 O.OI/lF IKV 10 ~W LI CRI02 RI12 22 2W N t---------, RI 330K 2w FG CRIOI 5 CxlOI IIlF 260Y 4.7K '14 w C,IOI 'IOOOPF 5A 250V RII7 NTCIOI FLIOI FIOI SWI CI07 O.OI/lF IKV CRI02 RIOI 47K 2W CIOI + 1000 200V " 110 y. C,102 1000PF 250V RI13 1000/l 200V 0103 CI09 2200/lF 25V RI09 TL431C Vref -2.44V2.55V CI08 C/30 I..,: + CI12 2200/lF 25V SO" '14 w GP L3 +5 0101 RI2 CI03 + CII7 40 5W +,2. 2.4K RI20 L2 RIIO 40 '14 w CIII 0.047/lF 100V RI07 27 5W RI03 CI05 RII8 9.1K RI16 10 ~W 0106 RI02 47K 2W • NTCI02 + + T.rrn;MI EMI FIL TER 0111 BUZIIA 0106 5W 3300PF 3.9 O.OI/lF IKV ~W CII3 CIIS RI05 CII8 4700/lF 10V + 4700/lF 10V GL RI23 CII6 CI19 + 470/l RI24 IK + + CI20 1000/lF 16V '14 w 35V CI21 RI25 IK 1000 /lF 16Y '14 w -12 0102 A }40-------' -5 L4 0107 r---------- -------- 4 -, 3 I I I I I I I I I 102W JI05 IL I I _ RI6 I I I I I I I I R5 lOK 20 R26 560 'laW SM494 YeW 1YeW RI9 470 'leW 27K ~W 'lew 1 1 I I I I I I I L RI4 470 'leW R9 01 4.71l F 35V + YeW C7 11.74VZ02 12.35V 'leW C4 10/lF 3SV R24 47 O.OI/lF 02 R22 50V RII ~W 0 RIO S.6K C6 CI3 O.OO~~1 RI2 'law VR2 IK "~~ RI3 3.3K 'law __ .~tv YeW oCS.OIIIF sov~ ~~ Zol 4.94V5.20V I lfew + C9 I/lF 50 v RI48 lOK V4 W ®0 0112 V4 W ® I RI29 1 5 r--_*----+-..-...... 12V II ......-I~____1~-.o--..,..._p +5 V I 03 R23 510 RI28 lOK I r - - - - - - -.......9~ RI7 1.8K + CI28 8 I 100 '1.W I : RIS RI8 R6 lOK ICI03 CI22 16V CI29 '14 w RI27 +5v 00 1V4 W 0110 I RI37 6.8K 12 + ~ CI24 4.7/lF 35V II I I h I ~ '14 w RI34 RI46 4.7/lF CI3135V + 5K RI43 RI39 4.7K 750 '14 w 1V4 W 0113 0114 RI36 5 ~.8K V4 W ICIQ4 10 11 CI26 >-+--~-vPG RI45 6.8K '14 w RI40 RI41 lOOK 1·2K V4 W V4 W '14 w RI42 2 4 1/4VV 471lF 2~Y RI44 6.8K IK • '14 w • R/47 lOOK 1/4W EQUITY III+/EPSON pe AX ANPS UNIT (ALTERNATE POWER SUPPLY) UNIT NO. Y126509000 A-14 -----A T B D C S,•• 7407 liiCi'" "'8 826 v 827 Ir 8215 8 C •15 R .15 ~ : 823 R34.7K sauT RESETDRV ~ CSOUT DIllS 82 Ne 33 . cO:! ~ ~ 13811 7 11 3 24 NC 23 NC 2S NC ", 4 32 iOW Tmf EIA DA TA TERMtiAL READlY ::0 EIA REQUEST TO SEND o o ~ 6 CN4 SIG GND 8 2 c z n l> -l Ci Z EIA DA TA SET READY • EIA CLEAR TO SEND EIA RtiG INDICATOR EIA RX DATA o o zz ", o -l o ::0 SA7 SA6 SA15 SA4 SA3 SA2 SAI SAO \l l> ::0 ...... ... l> ", SD7 SD6 SD15 SD4 SD3 SD2 SOl SDO 4 ...i> il: il: EIA TXDATA EIA CARRER DETECT AEN SAS SA8 3 LSII' 11581 VI tiTIf RTS 2 LSI215 13DI f'tl,0 C A 821 • 71518 18FI ... 12 ·4 824 H G F DATA7 6 15 4 3 2 I 4 0 ---.l!..... 0 ST~08~ AU 0 0 TIITT t- 0 o o il: il: c CN3 l> -l Ci Z XT o o ~ ...J z n z z CJ) ", Z 0 ~ a.. I" 12 Z u 11)0( 115 0 5 o o .SLCT .PE -l RR" ::0 ~ 0 t- 6 CN2 -l o "Tl o o 7 81 810 831 GND ~ 8 1 4·~407 +40~ '!~:; 4.,"$ L._ _6"o<'IlL1~5:<....-'1,!<" --::!. 51 • '<. 3 E h.!2. ~- 7407 6 15 R 4 3 7C 7407 LSI215A LSIS 7438 SPFG BOARD SHEET Unit No. YI2720110000 c B A E D T H G F r---------------------------------------------, I r-.....t------...... _-_-_-_._-_-_-_--..------1:-::2-=0-=Q----:R:::3:-:4~f------.f-----C28 R 17 + .....- - - - - - - - - - -.......--lio 0.1# +58 05 ISSI38 R 18 VCI LG 80th 74574 s are in the 82P 15-90PF CIO ~ 12 2Cext same package. The MPQ6700 is a quad PNP INPN complementary pair transistor. VCC IFC 2FC D2 VCCO 2 L5629 RNGI RNG2 (IG) GNOO 6 EI E2 GND 9 (VCO) (2.0M) (204M) IY 2Y 3 ICext GND ! RI5 1.74K 1% TPI WINDOW RD '" 4 One Point Earth 5 CI5 IOOP 15-90 PF VC2 GROUND PLANE ---------1--------- ALSI13A 4 +: RI4 3.48K WINDOW RD _____ ...1 3 ,......-.-------..---+-------.----4l----J~ 4.1 4.7K 2SAIOl5Y 02 RAW RO 5 RI3 3.3K +5 RI RII 2SAIOl5Y 01 R4 R8 SYNC WCLK 6 Spare VCOFB TL081 7 00 DI 00 AO 3XVN WR 4 -DL Y21500kbps) 3F 6 -OL Y 11300kbps) 3F VCOSEL .-:....;",. ..:....:....._...:.;:13~ 12 -DL YOl250kbps) LS74A 8 _l 3F 13 RES 4E 12 .a.LS27 EQUITY 1II + /EPSON pe AX SPFG BOARD (SHEET 2/2) UNIT NO. Y12720100000/Y12720100001/ Y12720110000 A-17 loc~g~ 3 2 1 3 ca 22p 4 ~ f 6 7 8 01r + 10CHRDY AEN 1 SAU 1& 17 16 1~ 14 13 12 11 I- o...J l/l Z~ Oz i=u o a. 2 o I- 10 11 12 13 J 7_ Rf041 IU XTAL2 L::r: XTAL 1 P20 21 22 23 24 0 +~5 SA9 l..ft- ~ 0""~39 R26[ " 7 EA 4~ 6 7 CI6 ! C>---?-,.----+-+l---~-------------H___1~--------+~+U-----4==t4~ ~ :~ KEY(Plnremovedl C 5C 11 (INDEX) ~ 7~ ~ 10 .A_ 12 17 21 1 11 13 CN3 TO HDD H51 INDEX A B 4J B 1 4 l,-_......;4;.;',.-I S07 I ~ DIR ~ ~I 4 I~ ~ ~ 0-;98-~~l-+-Ih I~ -J I I I I I mr 4 DRUN :~:~~ A WSHIFTIU YCOIN 6 4 3 2 1 H &ALE' 1 Cl:: 0.1" t-1 ... 1F GND 38 4 ~o '0 TEARLY 7 TNOf04HW ~~ t~~ 2~Y ~t:6~l PUf04PI-2"'~'---_ ...... :~ .\'.'iK,. :'-=.Y,.:. TDRUN C3 4700P WD10 C2OA VALOR P (Wf04Ff04) 4 CI815Y JJ... ",x r1/:rJ..:l.. 3 ,,,;,~. ~...!..>a--- 2 CI815Y 2f~ t------ Ql 4.7,,~t23 ~~~. ~ R23 1/4:'1'5YQ'3 ,'55138 01 3.6~K 1% .---I-- 11 XTALOUT 22PTcH ~1oI. 11 I I XTALI N 10f04Hz I L 1 r -- - - -, t~y. - • t~% 1 g f- I I J ~~ J2W r},-, J1 :~y I 11 1 ~ i 7438 Test Post 74LS08 < 00 ) < U) JI 74LS132 74LS19 Open Oral n I nterna( Pull up Schmitt Trigger Input I......· a RESEAYED KEY( Pin removl!d) NC NC :S~Sf+ 7 r I 100. ~% 'NC 1/4W 19 I 3486 Y2 I NC Rf04Ff042+ liiifM2 HDD2 DATA +~ C17 0.1" nrrns~ , WD11COOC - 22 DSEN " +~ ll9 2211\.1% 6 R20 33ll\.l% l!~ 11~ ~ EQUITY 11+/111+, EPSON PC AX/AX2 WHDC BOARD UNIT NO. Y12720300000jY1272031 0000/ Y12720300001 jY1272031 0001 NOTE: CN5 TO HDD 1 8 16 L:f~...J 74LS20 SPARE "'--""ll0 I I J1R~~ HA~ 8 9 10 ~; ~cl'7 RIO~ TO J 1 ON ANT-LS BOARD '--~7'O 16 6 4 I .... -(Jx>- ~ 3487 :~ RESERVED .....--i~"O RESERVED 1 'Vl I I ll.C.S Rll ~ 2 I :0- HDD1 DATA ., I t-I_-,I'4-,.-I 3C> 13 L__ =:[Jr- ::[)- CN4 TO HDD I r-- WAUP ~C 6 WAUPL !-L"---~-"'~ ... I ~ 7 8 9 3487 RESERVED SPARE 16 1 I GRDUND PLANE I ...J 1 Rf04Ff04I-'-"4:.-4 - - - - - - - - - - - - 13 I ,. "l 10 '11 ~~ ~ ~ I ~ C6 I Dne Point Earth: Wf04Ff04I!-'""6!....-4------~ (Rf04Ff04) Ir> ' l Il ; : ] 3. rf~lgi~~~DEX 69 ~I~-~-~~'0-K~I~~~11~3C:NI3C I J3 ii'i7i 1-T~i-2-+--+--0 DCHG STEP ~ J2 t--t-++-I+I-I+---!.!....IOSRC IDCS16 ~~~ Rll I ~6 _'~H~ 1-f;2s;-1 HRST +5 +5 12K YCCI f-U... ~% m • YCC2 f-i'L1/4W CORRD C32 ERR 0.1" ALE GNDI I-#GND2 f....U- ~R~24:..~R2~ Rl 5 Y. t---'\Mr-. - II l.lK I 1 C~ 1/4W,.. • ...... D2 20Y. P.::~ B R6~ r~iF ADJUSTI-''----+,...I-%--'Rv.~1I._t ~~OP ~~PI ~VCCJNA''0K.'101,ADLYDRl r61~ ~~Kf04VAf04I09 1/1 0/1 Rll f-__..... --._---1 487 1.2K R17 HK R18 1~ S~ S% 1/4W 1/4W 1/4W I9 ~ NC I 11 1~~~4 SAU 5 - 7/1 71 36Pi n Card Edge 1 4.7"HH 1% 36.~K ~ iöi row 17 11 - Delay L1ne 1 --ll WDCS H1il 'mj HAI 5 - - I :(W:ATEl +12 R7 3 6F - - 12 Y a I 4 - ~: =~~~A vcog~~I_fh-H_--------- 4 1• 11 II GND ~ O. HD7 10 ~ 7 41 31 2/1 ~ - - .:.C~12:....:I.~.~..:0~.I~":..-:~.:.OV:.....:t:.:2c:0.::Y.c-... ~ (RCLKl e---t (RGATE) I (WDATA) I 61 4 :~1~ Fi5CS t:>~: NC LNCIi P NC töMri P:~ NC u 4 B 12 - _;(~~:~~~~~:1Ij~~'~i;I~111111111119WICLIK~~W;~iT~E'3H I +~ GND .... I ~'A:" ~ l:f!-- jA 01 3 DACK6 .-_ _ - : HDO~ 18 B . A : D~~~' DRQ7 - I 4:: 1'7 ~ - I ~ 1 Il .f-_-_-_---::.C-~7 --;O;OP~~~ - HDD CONTROL FERRITE BEAD - I r l LI I 1 g 100 1% sc WG TRKOO WHT 4 II 14 R 21 HS2 a,t:2=:i=~ I 10 11 1~ 6 r- 5 10 0 : 1 1 I ' A ~ IRQ10 11 4 DRDY I Jlr! Oz j:u ~ ""-'" 8 r-----------.-.~5~ 0.1" 1~ D~~~~ DRQl iiffiiW 4 Ho "!9:::~~~~~5~09='..:3C--------------~------...:5+j4~3 ~2+6+-:t-.~-y,_·---J==~'~H53 /RWC 4. + 12 3 ZN WF BDRQ SOHLE i~.~7~~~I~*================~:=:~==~F==j2~1~~R wr es 62P in Card Edge l/l GND WD2010B OACK2 26 T/C 27 BA LE o---k~8:--I---I--I-l--l-. B~~g o-~3~0~+-+f--I+l---- + ~ GND ~ I- ·c 3 Hl--+--I-J OE 6 ~~ r - - - - - - - - -__ l~~~'~m3~3~ B~DY: I~mSC~33~l~7-~'~~~g~f~~~~~~~~~~~~~~~~~~~~~~~~~~~~~q+==;l:7~A~'===i+ij~~===~~~~~ ~ L_~4_"3L-.....jf++_+-I-I-----t:=::ti~ H:~==!:t1 4 ~~_..;4--1h1 t2 i 2201\x~ _"f +~ ~H!QJ.D7_Jjl~~DO:~7--"V:;:CMC~Cl9 7 wn7 ADRlg~~~~~ i 6C A~.~ W1l 07 100" 16Y 7_ .R[ ~ 4~, Eg~i~ +5 14 Ht--uTKIlJ'nn",,---, +~ 15 32 NC 1633NC lR15 17 ~4 NC • 4.7K TEm Pi-LJ--....----++++-+----c WAUP ~% : 1/0 VCC U Pg~~~4'7~KX2 100 +~ +~YDC Tl GND 21 NC 22 NC NC is NC RA10 ~~27 I-~t7t:jc~clfREA~D~l>=t==:l 4H 40 YCC 26 VDD C20 7 ~Si 8:~~!~:;~~:t:::±tlCl~f o...J H +5 i~~ ~1oI !I~~!;~~~~~:;6f'~-!J:~ ~6~ ~ ~ ~S~A2~:~1~ ~ G ~10f04HZ 1~ ~ OAm F :;= CRI 16 17 18 19 20 ~l IRQ9 -~YDC DRQ2 -12YDC OWS + 12 VDC E ~~ '4 1~ GND RESET DRV o COHA2l-1_ _----. 6 ~ 4 c B A Y12720300000 and Y12720310000 uses WD1015PL- 27 in location "4H". Y12720300001 and Y12720310001 uses WD1015PL-27B in location "4H". A-18 c B A ---------1 D 117 1 II .D lSI25 3 16HI , '" ~ I I I I 8 I 9 8 20 I I I DIR~ 9 8 7 6 5 4 3 2 1 I:!'I 11 10 --------1-- -I & 6 E T SAO ~ 9 ~39 ~~ 4~ : IIR :~ 21 1'--~2-i::t2 23 24 2D : IG 2 RSTN l 7lT C E 0 C E D A E ~~ 4 3 2 1 ..•.• c d \J DD ...4 D3 Si: 48 • .-' m D ....r.4;-;2:- _ WELI ';..46 fA!!:!. ~1;':;4~7;-------------------. CASL f . > : = - - - - - - - - - - - - -........ J,. ....r 6;,..;;6 S 4 3 GD7 6 5 T E S T N N N N D D D D 4 3 2 I R R R R AAAA 321 0 87 188 91 fl ~ 7 4 3 19 D7 18 6 17 5 93 6 QI' 94 92 o l8i 2 7 _CE OE 6 4 d GND •• lf Id h d~ ~ r:i'" r< ~3 k 3 2 0 12 12 4 3 rij" 2 r-T4 IVG CAS WE 1 S C E L rr-- '----i1--'3iL.1 SAoT K +~S~D SDIS i:m i~ C E 0 E E C II~ I 4. _ _ _--l,...~iIi:. 2 8 G A M Y V Y .......-+_~7-=1! IDCK ~ DCLK MALT 78 MPX L.-_~I--_.uq L.-_--I--I-__~..lJII HSEL 8 ~t!!=:: 5 41....4 ;..-.3 :...2 L......I 6~ o ~ ....-+v-t-+ MI6 ...2:,::8'--_ _+_--I ~~ C8M ......... 32=----~....J 31 B2 WA IT p.::-'----+------===------' G8HE f..h.)-.3_0_ _-t 29 MONOt-- - - . R R ---I-+_~1~9::.{) A A I 11' I 'll n 11) 2 olo 3 2 I ID o 19R:~ 10R I +5 A 76~43210 G o A M Y V 70172 42 N C ~ WR --....: RS 1...30 T C G G E G N N S S D D T L IIlsc1a_ V V C C C C ss~ (SC) L8 ~v L7 -,J!,!!; 1~ VIDEO ~; .S RM4 ". .. :: IJ, RA3 2 I 0 8 9 3 2 2 o:~go ~ CLK 21 I 8 Riff h-2 ,- HV8GR I I 1 sTe12 I 1~411111 11 t<1IG 15AI ~2G lS244 A y 1.'.IS78 CNS ~I 2 -oR 4 ~O IJß 6 8 L.-----~~D V 10 ~H 12 :L b 1-13 ~ +5 V .I ,R - . Ir n A Y I' C-CMCL 6 G ~B 1 H --- ---- - - - - - I lS86 V GND FG 9PIN D-SHEll 1 1 . :16C H eONNECTOR .J ;''r ~ & B~ {~ ~ la: DSEN 1& CUDS HSYN in VSYN G 5~ B ~~ 9~ GVII ~ M 8 RS " CS 26 GD7 ~_-----..§!!I D7 9'7 6 t!!~I-----~L.1 -!>Il 6 5~+-1f_._----~ 5 --..ci 4~"+-11_+.....- - - . . g q 4 30 3 3~~H__Hlt__--~ 31 2~~H_~1__..--..2!..I 2 32 1 I 33 OF+-1rl-+-t-+-+-4I--=-I 0 GND 98 76 D_" 32 es (E02055EBI C C 14 16 M M - WRF.~ 8 M 0 N I ~ I : MAI2 I 11 I 10 I 9 1 8 8 8 I 7 0 7 I 6 6~,........-----....LlItI S~~------OI.I S 4~'-------~ 4 3pi!1~------.LI 3 2 2 47 5 I I 46 4 o r<----------=q 0 !>:'l RD h27 RD RSET 3 2 1 4_ R ---.w~ A2~ 61"\ .JU!. L6 4~ 3 I]~ 2 CN3 L9 ;;;:;;: L4~ U'I ~WE5~ D3 t-::17++-fEllnt::m;:++H;.17ir-1D3 2 120P 47P L3~- 3'" I L..- MAI2 t:2~9 11 31 10 34 9 36 (48) -n'.::: S2 21 SI 20 SO 8HE t----"'Il.....l ADIS 14 13 12 11 10 9 8 7 .J 6 S 4 UI 0: , V A 0 ---+-I-_~24:.:'-rlWAIT 1 ose 0:0: 0: I V ~!! CPSL ....---+-+_-II~C8M S2~ 4 C\I" It)~ IIJI RAS A7 ~ CAS 6 ~ rrrrrrr 41544 'O~E 9 4 14F) ".' , 11.7" 13~ '~ 1111 ~ j..iaelt<1. 17 1 ADIS~ 14~ Y ~2.147 .-.I---lC~7-1 I 12~ -+-: 10 9 A A lS244 '"--- MB81416-IOx8 A D I. 411'7 16AI 6 f--2---, 5 ~ 4 ~ 3:---.. 2 '---.. 0 I ......,,=__ 0;...1 ~S ~ O::~~O ~ 18 I. M 1 iG ~ 2G IC~S A7~ Irr R S k BGRI [ff[J 10 IIHI RASh.S. A7 lJji' 6 CAS"", Pt: 1"21. 11 ~ 17 i 17 D3 D3 HI~6++4H-+-H+H~I,ri I) 2 ~SWE4 ~ VH I 5,. RAS IIF11 r--t ~20 '71,. 4 3 2 I 0 ,n ITQ] 4 : :=: I:~ 3.3Kx6 F la o IIEI RAS ~ A7 CASh.16 7 6 ~ l.---j S WE r,...~-+-h 3 ~ IID1 RAS A7 ~ CAS 6 S~ ~ WE 4~ 1j17 D3 3 IS ~ 2 2 3 I I ~ 0 I-'-'---, 0 ~ S Q 4 ~ Dill o _11 6 ,D c c ~ ~ ~ 0 ~ 6 .. RAS IIB) CAS A7 6 WE D 4 17 D3 3 IS 2 2 3 I I ~ o 0 a a RAS t,-J.0 110 A7 6 CAS I.---' S WE 4 17 3 03 15 2 2 ~ I 1 3 ~ 0 ~ t:::::!t12 _ 1·7~6~-__='~';';""----, CAI2 t2 AI2 8S " !> 11 79 10 t-I8=:;:3=---~!>. 10 (28) Vcc V,.,.~ 9 81 2D 9 7 8 77 3 8 PGM fJ'""" 7 41 7 (E02052EAI ~ B -- .-~~:-----------------..., RAS ~ ~ ~ A7 6 CAS D WE 4 17 3 03 16 2 2 3 I I I~ o 0 D 3 nr------------------, o IlAJ RAl IIIJ WEHI t::-r.,4 V G GG G 111 4 Je rl ft[öJ;;:?T,i ....- - - - - - - - - - - - - - - . Y 0 I? C) D6 2-RM2 3-RM2 4-RM2 6-RM2 9-RM2 8-RM2 7-RM2 7-RMI 8-RMI 9-RMI 6-RMI S-RMI 4-RMI 3-RMI 2-RMI WEHö~ '---++--'-=;31=-1 MALT rl--+-----'=:+-! DCLK ,..........!!. CCLK ~ DSEN ~ 34 CUDS ~ HSYN Ir-ü- VSYN NNN DDD ~4 o G A M HSEL r_--+-+_---!2~9~ 30 MPX G G G b 3 [SI 27 MI6fD:.:,I--+--+--.......J : 8 ~-RM2 il) -----+-+-----lIL""-1 RSET r C8M .--_ _-+-+-_.....;2~6;.1CSEL MONO ""D.::;.2_+----. M 12E) f:1...)-4:.:9~t_----f---J-Jr"1l-~----~~~-=.-=--=-~t1===J:14~~WAIT EXT 131 Ir-- a VDIS 64 14 63 13 1Iii: 12 IRI 11 S9 f 10 S8 a 9 S7 n 8HE 4~ S2 5" SI 7 SO (E02055BAI A 14 13 12 11 10 9 8 13 o :48 ~IOW 10 11 I!> ~ A ADIS ~ [;-6 .5 Iso. 16 A 9 I~ I ...D ~34 32~ ++-1-__-+_--.J!>:I.I AEN ++-1-__-+_ _.1!2l BAlE R S r-----I--------- J;; ..u ~~ o CNI ~ 117l1'7ll MCCIRG8HV V MM AC 8 S L L 96 VV VV ~ AI9 C C C C 97 CC CC ...::.!. 18 17 10 10 ID 14 ~ .... 11 11 I I CN2 13 12 G A M Y V X 15 14 13 12 1,.------';:;..1 t'D~O:...- 14~ ISH) 2D:-I SAI9 .;-_;: 1,.--_~'4~ 18 1.--_.,314 17 1,.---'1''''-116 I 2 MSA ADI5 21 ,20 19 18 17 • , t"\..(,>;;A;;I... 1 r.q.::8:=2:.8 - IOO~S S lA23 22 , AEN BAlE NC 11 111I DD DD MCSI6 Ne t!m.r---e I"'.....' NC NC vv 2 1',i9JI ....!!c ,1---------...l6~0~,.OCN r'!< -G 7fT + 27ta;] 1-=-----. RM3 IRG. I' 60 L S 2 4 c:::Lr, !!4 ~I!>G ,'17 tilr8-=~w......., 680 3 IS I '14 15 7 RI9 :i:::: ~ 2K r - 3K RI2 IK 7S0 ~ao ' .... n QI NC NC I"'l 83 RIO 20 130 >- RI3 RII • ""-- 95 77- no CN4 (ö) eOMPOSITE t2.~IDEO b..-------4I Jr 2SCI815 VCC 20L. .S lOK. 7~ _&30 MGA BOARD .5 .5 UNIT NO.: Y12720400001 GND GND GND 10_/ 0.1_ /IOV A-19 01 * ~ +5V I -r R2 J27K ,,;I: '--- MPU8 M5 ,_ 2 + ~ CI "'J +5V T :;J;. 47p LS14 r--_I~ M3~3~ 19 C21. IOOP~ XT2 ~1...:;,8_"""--I C3 ~ ...;;1_2"'INTO IOOP 13 Jumper-2 6 XTI 31 EA -+-~2 4 9 RST/VPO ~···V ~ 6MHz - .b INTI 5 .,~ +SV LS125 PI7 ~P35 AIS EI4 PCJ-9 AI6 PI6 ~ ~ EI6 FI4 EI8 8 PCJ-II PI4 5 EI7 013 EI9 E20 PCJ-12 ~ g:p ~ 7 rr T(r ,.....;:8~_.- 9 ~ .!!,KT ,..-:.1.:.,.1_ ......_ _+-_--+_--.1rl--_-.::::::....-_ _-()<) PIN4 10 PCJ-IO BOO R4 M5 ~ 7 ~ AOI 13 CLOCK --!.2KT R5 +-__l__r_-----_o_o PIN2 C5 .l.. DATA T _ L-.(g)l-----1 LS125 +5V 56P:m ~ 012 019 ~ CIO CII CI8 CI9 020 PCJ-13 C02 C03 C06 C07 C08 PCJ-14 - PINI ~ o N.C ~ B02 B03 B06 B07 9 B08 PCJ-15 ~ ~ BIO F02 A05 F03 BI7 F06 P 11 t-2 PCJ-16 BI8 BI9 F07 F08 PCJ-21 ~ PIO ~ F09 FIO FI3 PCJ-20 FI5 FI6 E07 PCJ-19 ...., PCJ-18 009 EOI E02 E05 E06 E09 EIO EI3 008 001 002 8 --+_10~ _ ...., R7 180 CNI --.. PCJ-24 12 13 '- 11 ~180 _ " rD---.()-....,--r"'----'~----rl(. I__------:...;;-l_-_-_..,I PCJ-25 1 OPIN6 N.C L3 Seroll +5V T P 13 ...4 - - ...., -u-n- AKO PCJ-26 +5V -,...- PIN5 BCN _0 +5V 1 ~ I~ sv .... I-:> 14 M3 -M5 7 -~ M2 8 _~O C7 == - MI O.lp C9 =~O.lp w - '- Cx 1000P * 1 ~ 22# ,... ...., PIN3 GNO ljr MI 8051 C6 .... '20 2 ~P34 + FGI 0 Jr 0 FG KEYBOARD CIRCUIT A-20 A c B T D PKG E USE I 4CI DSX I I 4tl , I WRITE PROTECT SENSOR H G F R46 330 2' I RDlE~ '" 1>--.....'/""1 DISPLA Y LAMP LEDI DISK 11 SENSOR 390 RI7 47K r 2 CI9 R45 = O.l~ +5F TP& R43 IOK INDEX SENSOR 11 ;SX:~: ~:P XL RU ---, ~5 RI9 ' 330 ~ R20' ... 0 ,.. ~)($!."'_~,>USE I ...'" ! 0 )( Q II > II > R93 lOK TP7 I i W SPFI ':IZ~HI 1>------"''"1 DRIVE SELECT 3 ...... HDM 1>-....----'-'"1 SPINDLE MOTOR R44 2 0 LAMO CJ :: 330P DRIVE SELECT 2 P3 43 41 12 & 50 3 24 49 I 19 U2 JBL 1006 P --, : STEPPING I MOTOR I 11 10 4 HLFO r::::, 4 17 47 PH41 46 PH31 4& PH21 42 PHII HLDI 4 HDE2 I 7HI RII 12K 3 IOK .&F 3 21 I 2 I 27 __ JI 11 DI HEAD LOAD SOLENOD FII41 HEAD LOAD / IN USE IS2837"" liDO MOTOR ON TKOO R77 WRITE GATE 5 R71 3K R70 3K RIO NRITE DATA PRn RDTO I TRACK 00 41 3K READ DATA R91 DIRECTION 3K 3K 3K I.lK IOK ""'_l--+_+_--l----D WGTO 12 SHI EGTO ~&::&=-----------<"'--+-+_--l----D EGTD 12 6HN WDT2 62 WDTO 12 &HI SWFI ~6::1 ....;,.I.!..rO-' WENO~5::6=--- RII RI RI4 .&F RI3 lOK MIGH/NORMAL DENSITY READY/DISK CHANGE R47 R41 R49 R50 R&I "11 IK 6 RDY I I lAI .&SF -+----<~__.-+-__. STEP SIDE SELECT WRITE PROTECT 9 7 RDYO 1----f">RDY 0 I 7AI 39 DCGO &.6K INDEX DI4 40 19AI 3K 5.6K lOK LAM2 I RI& C32 O.l~ L:"1 I O.lO:,-.....-+----I'""> SWFI 12 2PI 12 4HI SWF3~6::.:0=-----~2.;..' O:~ lOK L_ ... ~J 1fT ~SF~S!.._ LSSO 1_5:::4::..... +_---.f"> iWOSHI =- HDEOI-3 .J ,..---------------r>.&F 31 PsvOl---------------~':> ,..-------o·&S 7 DC .5V R91 .&F 2Lu~ --w,....-+---.=.r lOK .5F .&S L LSI 4 - - - - - - - - - l DEN 62 .... - - - ...--------f>.12S 1 DC .12V L-.....--D : I' .12SF 9 3 I I ~ R&9 lOOK =,: R60 FD 1155C (1.2MB FDD UNIT) CIRCUIT DIAGRAM Sheet 1/2 JP m IIQI!--'.---t.> rD1~1 I 181 R56 FG SG 4.7K .....--------<~---I> <>-~...---------- ~::.J .I~ R54 lOK 1 1 '---I I LSI4 C30 TPI C31~: GND 8 SV2C:lI PSV R&I I rC-~~--w.-- .5F I lOK '--_-OO·5SF GND r HDE4 12 IHI 12 &HI A-21 A T c B ..-- --rr_-=-011--012_'-:~ F E G --, 100~-:-I-------, . - - - - - - - ' - 1-05 60-;.1-----, ,..------:-1-03 40--:-1 7 8 't:L[:) I I 2 ---""11 Ra ll~L. .J-'-+-''''~1fIIIl7l----<~JW'r1 .. 0_.... 35 :::= , '2A ~~C66 Voo ~fr°·IIIF VSS DBO 12A '5 46 DBI RH nOllJ n R79 IKJ 45 DB2 C48 -DRIVE SELI 26 r ----, ~ D-iH-+-l-+'-10 I ~o-':~"'Nvi 28 1 17 18 D-iH-+-l-+;...10 ~ I 2~ 30 '15 16 1 ..0:. -DRIVE SEL2 -DRIVE SEL3 2 -DRIVE SEL4 - IRESERVEDI ' f, -DIR JI IN -STEP -Wo GATE o DB5 24 RI08 220DJ 6 RI09 220DJ -SEEK COMP 3 -READY -W.FAULT -TRACKOOO -INDEX ~ ! ~F 01 +_...:6~01 _i~ MB8~~~6Lr::___W_ -SKCOMP 3. V ~~ WR, GNO 10,10. GN 111123 le ~ C53 5 555 ~J~ 8 1614 5 13 12 9 7 2 ~~~ ~ 5.6 IIH) '-< R71 C50 I DACLE P. TRACKO ~. ~5 .5 CS WRFAL T 1C2~ Jo ~ ~!l8 IKF 4.7 150VI .5 6 Vcc MA ...1;.;;5-+-_ _---'-10 IC9 PBL 3717 >+1-+--f'°"lC I 2 Ph E G' GIGIG410 I' TMBI-'-+---O ~ 'C..... 11I72 51. 11 Vm' Vml VR 4 g~:F R73 8.2KF 33 ~O '_ICII '5 1000 PF L.. ---2 2 T GII) C57 180PF ~ R715 '2KF 4 314 LII 393A 81-- R74 ~ 3 ~ ICI 3 _ IL.J" L..-. C55 O.l"F R77 5.IKJ I ICI3 ClIB O.lIlF - B 24 A!1 "" 20 l2 uU ~'CI ~ I '5*IuVJ '5 MRDWR ICI -READY IC~ 23 8 >4~"""'~'-II, V;r. o 13 ~ 34 r! I 14 -C5 ..! XFER..:! Ir-~H_-+++-t-iH----- ....+ + - + - H H - + - - - - - - - - - -....+_+-HH-+-+--1--I3 2 07 ~ •5 • 1 C1I2 ~ MB47082PF A9 EN 26 IC;-'" 10 3 1C7 .... y4 RIOO IKJ ~ci:J AB 2 .AI 10 '2: 8 ~ - ....... V,el.!. ~: ST EP 0 D-=--1-++-+--H-+-+-1r----, CMP IC2 12 MR47 35BPF OAC~~:2 +_+--,5 O. 4 '-----~f--+-+--j--------- .....- + - - f - + - - - - - - - - - - - - - -....-f--f-+---1-I6 00"4 A I~ 22 ~ ICI2 ++---------++-+---------------- 17 -WRGATE 6~ 22 .. DB7 P::-' 2 SN74LS07N5 8 '-- + 5 ' - - - - -....+ + + _ H - - - - - - - + + - - H H - + - - - - - - - - - - - - . - H H H - + - - ' 1 " ' - I DB6 -STEP .... L - -_ _++- Gl~ CMP 34 ~ -RADOPT 1- 5 552 RI07 220DJ ~ DB4 1 9 100,..:1_-, 11 rl3q I _~_ J o -DSELI -DIRIN I_I 4 IRESERVED) y8 D-iH-+-l-+-0 3 O-C,:-'I'I ,..-(J 1 ,13 14 I 10 32 , ~ I D-iH-+-l-+-,",Oll 4102"",--''' r----------,l ~_~-----~~---------W-+------~ ~ .SV .SV RETURN .... t J3 j 12A C8 / f l2C o---------+----4HIKNJIr-_" TRII g~:F i-=-=-t-t....- - + - - - - - - - - 1 - - - ! t - - - - - - - - - O HV 1-=-=44.....- - + - - - - - - _ + - - - \ - - - - - - - - - 0 HV- J-C40 HAI3426 21 TO.OI.llF S HV F4-+.....- - + - - - - - - _ + - _ + - - - - - - - - - - o HV. "'2Sft62 R45 5.1K IC6 T 10~ O.OI"F 20 8 23 HW. HU. ' - j~fJ,,~ - W 14 CPO v L--w..~--,4"'XTAL C31 1000PF HW- HU- R50 56KG "-.... ~ R46 R41 5.6K R44 2KJ HW .1 C39 12 .....-.....----'-iCPI TR9 25A 15SIBI R32 470G 12 1B t-c::-t-t....- - + - - - - - - - - \ - - - 1 t - - - - - - - - -0 19 R39 IKJ R37 IKG 3 HW ~VOO "Ir C64 I 5VSP Vcc IJ RI03 2K R47 20KJ TRB 25AI162 12V RlIB IKDJ 8 ....._ _-' 2SATI~~~ ~ ~ ...J 4 GNO R34 470G ,---,1-,"1_-, I ~ I ~ I o--!-,-6_ _-, I I RELAY RYI R48 6.2KJ I I C32 O.I"F .,J.r 10 VFLTB 1 ~.l CI4 36PF W V,.f 10,),. C65 1000PF L3 1 11 3 R31 3.3KJ IlJ ~ llOO t--.....-+-t-JW'r--r 0.01" V5 O·!f ,FBI ~"I-F...,11--2-0-G-+_+--..., 25AI022 :.1. 1 CIO.I.II r;=t==::t==I==t==l==:t:======::..J1 331'F ~;IODJ RI2 ......... ~750J 100D CIO TPI C51 11 IC5 TC 3 509 4 P AG 1.51'H 150PF IBOG 12B ' 5 " R23 12B 2KJ 11 R20 R2~ 33KJ IK RB r---il--+--I---""M--L TR3 I.BKD .....--++t-+--+-+--..---=--:...-. 100DG "" >-- ~ ~ g~CZ3eiIC71 0.111 RI5 ~ t-- 1.8KG 19 ITC C28 .. g~JI. 10Rtige;; 0.1" 18~F ~ L....-j-f-1--+-+-+----"""t0E SSI 540-2 R9 R7 I.BKD .BKD 12B LI 22" 7 .12V RETURN := C26 C52 12B TRI~ 25A1I82,......rR6 1.8KD L2 22" TR2 2SC2712 I 6 5 4 3 16 15 14 13 18 2 CI< 07 01 01 04010.0, 00 Vcc OIFOIN- OUT- G. GIN. ~=0:'lIN~.~~~O.,Ur-T,.;.:--~'I"='IIN--..., ...... ~~C~2~4-~R~2~1~B~~~~~76 ~~hG Brush '5 • 12C OIF. "'T_"'T" W_R_T_. 12B .12V ::151C025 R30 IC3 1.!!.. - WRITE DATA 14 ~o----",,~ R5 '-------------t--+-------------+H-+---~ S.G ...._ . C27 17 ;T; 12B .....JP4 0--0 '00 ::!: CI9 1/7 0.1" 31 10 RI02 10KJ RESET SERVO I ~ .5 R82 3.3KJ 19 DRDWR -(; -(; SERV02 I 13 1 IC74 32 .--++C 0: X 0 0: , 0 Z <.!) Cf) oCf) J: J: It) > 0: c N N I~ <.!) > > Q: Z " ''------------------;- J7 >C 0: HMD - 720 MAIN CIRCUIT DIAGRAM X C 0: ---.J1 J4 A-23 J6 .5 N LS688 SAII 10 9 B 7 6 5 4 AEN SA3 2 1 o S07 6 5 4 3 2 I o I I ;. '~:,~ '.~' >:.. 26 27 11 A2B I 0 ~,3:~ PI PO Ci P=Q Q7 29 P3 ~ P2 ~ 9 ..... 6 - t'---- ~ .... ~ -- ~ ~ ~~ 5 r. 7 '? ~~~ ~. :~ '. '.. I r~ t-++-~u'r' ,.......... 1. I :'.. IKx4 SWI PI PO Q3 6 n--------=+-oiiLf OB 07 I x.,.. ....... T.T Q2~ QI ~ --9.9 fu--< B130~----___i~I:JCi P=Q PL" nT IIC31 r. T LS04 ~r---A-L-S-5-6-3-""" 3 4 5 6 7 B SW2 I Q6 ~~+----4lf-+-hI--....;j~.rv-(~y./o--......, 11 P5 C Q51-!,~-+-----iH-+----'2HJ~ ~ I P4 I Q4 9 ....... U - - - - - - - - - : - ii fP6 30 31 A2 ';. IKxB QI --9.9 ~ LS688 P7 N ~ 17... P7 A200--------n Q7 118 21 I P6 Q6 16 22 I P5 I Q5 14 23 I P4 C Q4 t-::1~2--24 P3 2 Q3 25 P2 Q2 ~ -IOW ::E. Ir. +5 't.~r:;~~ ,J, 1J1'l I I I I I I 200g \l WxB N ~. =::~ '. :: 4 I~LEOI QB~~- .... r......"I-'".~'--,--,2=--' Q7~~---'-IoII"''7-00,.J I Q6Pf:~---'·""'...;.lfIIIIL"""~3~ 05 C Q5~~---""-,-lill L.......... 4'-:-'_ ......... 5 04 4 Q4~~------II""'IIII--L...... l.oIIIl 6 7 03 Q3P!-:~------~:.I ,02 Q2P!-c!~------_ .....-=M .....~1Ii B 06 • 01 LL C ~ QI ocpL, ,m LEOxB .... .5V GNO MFG BOARD A-24 132 126 134 500 \ --- ~I 103 /~'~300 Exploded Diagram For EQUITY m+, EPSON PC/AX ( 2/2 ) A-25 231 241 230 / 108 ( , ./ 100 201 125 Exploded Diagram For EQUITY m+, EPSON PC/AX ( 1/2 ) A-26 EPSON OVERSEAS MARKETING LOCATIONS -- EPSON AMERlCA, INC. Bulldlng #6 23610 Telo Ave., Torrance CA. 90505 U.S.A Phone: 213 - 534 - 4234 Telex: 910- 344 - 7390 EPSON DEUTSCHLAND GmbH Zulplcher Strasse 6 4000 Dusseldorf 11 F.R. Germany Phone: 0211 - 56030 Telex: 8584786 EPSON UK LTD. Dorland House, 388 High Road, Wembley, Middlesex, HA9 6UH, U.K. Phone: 01- 902- 8892 Telex: 8814169 EPSON FRANCE S.A. Evolic C - 201, 86/156, avenue Louis Roche, 92230 Genneviliers Phone: 1 - 4792 - 0113 Telex: 614966 EPSON ITAUA S.p.A. Via Timavo, 12 20124 Milano Phone: 02 - 6709136 Telex: 315132 SEGI I EPSON - STI S.A. Paris, 152 08036 Barcelona - Spain Phone: 250 - 3400 Telex: 50129 - STTK EPSON AUSTRAUA PTY. LTD. Unit 3, 17 Rodborogh Road, Frenchs Forest, NSW 2086, Australla Phone: 02 - 452 - 5222 Telex: 75052 EPSON ELECTRONICS (SINGAPORE) PTE, LTD. No.1 Raffles Place #26 - 00 Oub Centre Singapore 0104 Phone: 5330477 Telex: RS 39536 EPSONS EPSON ELECTRONICS TRADING LTD. 25/F Harbour Centre, 25 Harbour Road, Wanchai, Hong Kong Phone: 5- 8314€OO Telex: 65542 EPSON HX EPSON ELECTRONICS TRADING LTD. (TAIWAN BRANCH) 10F, No.287. Nanking E. Road, Sec.3, Taipei, Taiwan Phone: 2-7160855 Telex: 24444 EPSOf'J TB SEIKO EPSON CORPORATION 80 Hirooka Shiojiri - shi, Nagano 399 - 07, Japan Phone: 0263 - 52 - 2552 Telex: 3342 - 214 EPSON Printed in Ja[BIl 88.10-1.5

Source Exif Data:
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c321 44.398116, Tue Aug 04 2009 14:24:39
Create Date                     : 2012:02:10 17:07:44+01:00
Creator Tool                    : pdfsam-console (Ver. 2.4.0e)
Modify Date                     : 2012:02:10 18:39:47+01:00
Metadata Date                   : 2012:02:10 18:39:47+01:00
Producer                        : Adobe Acrobat 8.31 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:1692de58-ab64-4268-9a97-16eb7a4d9cb4
Instance ID                     : uuid:4a2ad773-4353-417a-a5f3-cf1da7c16d90
Has XFA                         : No
Page Count                      : 312
Creator                         : pdfsam-console (Ver. 2.4.0e)
EXIF Metadata provided by EXIF.tools

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