Z33 1021 0_2020_Processing_Unit_FETOM_May68 0 2020 Processing Unit FETOM May68

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User Manual: Z33-1021-0_2020_Processing_Unit_FETOM_May68

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ll) g5~

Field Engineering
Theory of Operation

IBM Confidential

~ @~ @ Processing

Unit

System/360 Model 20
(Machines with serial no. 50,000 and above)

Z33-1021-0

Preface

This manual describes the IBM 2020 Central Processing
Unit for the IBM System/360 Model 20 (Machines with
serial no. 50,000 and above). It also defines the relationship
of the 2020 Processing Unit to the System/360 Model 20 and
to the input/output devices to which it may be connected.
Field Engineering Maintenance Diagrams manual, 2020
Processing Unit, System/360 Model 20 (Machines with
serial no. 50,000 and above), Form Z33-1024-O is
complementary to this manual and is referenced in the
text as "FEMDM".

First Edition
This manual contains preliminary information and is subject to change without further notice.

A form is provided at the back of this publication for reader's comments. If the form has been removed, comments may be
addressed to IBM Corporation, 112 East Post Road, White Plains, N.Y. 10601, for the attention of Publishing Operations.

Contents

Chapter 1. Introduction
IBM System/360 Model 20
Input/Output Devices .
2501 Card Reader, Models AI, A2
2560 Multi·Function Card Machine
2520 Card Read Punch.
1442 Card Punch, ModelS
2203 Printer, Model Al
1403 Printer, Models 2,7, Nl .
2152 Printer ·Keyboard
2415 Magnetic Tape Unit . .
2311 Disk Storage Drive
Binary Synchronous Communications Adapter (BSCA)
1419 Magnetic Character Reader •
1259 Magnetic Character Reader
Programming
Data Formats
Fixed Point Data
Decimal Data
Logical Data .
Sign Standardization
Machine Instruction Formats
RR Format
RX Format
SI Format
SS Format
Indexing.
Data Transfer Principles CPU· I/O Devices
Burst Mode .
Time Sharing Mode •
Overlap Mode

1-17

IBM 2020 Central Processing Unit (CPU)
Operating Principles
Micro- Instruction Operating Principles
CPU Basic Operations .
Micro-Opemtions
Local Store .
Micro-Instruction Formats.
I/O Micro-Instructions .
Circuit Controlled Manual Operations (MANOP's)
Storage Alter/Fill
Storage Display IS can
Storage Test .
LS Register Alter/Display
ICPL .
CPU Login .
Cycle Steal Operations
I/O Interference.
I/O Service Phases .
Program Levels .
Program Level Switching
Program Trapping
Cycle Stealing
CPU Data Flow .
Internal Data FOLmats
Main Storage
Storage Address Register (SAR)
Storage Data Register (SDR) .
Inhibit Switch
Operation Register (OP REG) .
Operation Control Unit (OCU)
Program Level Control (PL Control)

1-19
1-19
1·19
1·22
1-22
1-22
1-23
1-26
1-27
1-27
1·27
1-28
1·28
1·28
1·28
1-29
1-29
1-29
1-29
1-30
1-31
1·31
1-31
1·31
1-31
1·33
1-34
1·34
1-34
1·34
1-35

1- 1
1- 1
1- 3
1- 3
1· 4
1- 4
1- 4
1- 5
1- 5
1- 5
1- 6
1- 6
1- 7
1- 7
1- 7
1· 7
1- 7
1·10
1-10
1·11
1-11
1-11
1·12
1-13
1-13
1-14
1-16
1·16
1·17
1-17

Local Store (LS)
Modify Address·Register (MAR)
Modifier .
Logical Unit .
Shift Unit (SU)
Invert Switch
Arithmetic·Logic Unit (ALU)
I/O Bus Out and In .
CPU Cycle Steal Control

Chapter 2. Functional Units
CPU Basic Timing
Oscillator
Short Time Clock
Run Control .
CPU Start
CPU Start by Power On
CPU Start by Operating Start Key
Continuously Alter or Display.
CPU Start by Operating the Control Program Load Key
CPU Start by Operating the System Reset or the Load
Key
CPU Stops
Common CPU Stops
Normal CPU Stops .
CPU Check Stops
CPU Stops for CE Operations .
Normal CE CPU Stops
CE Check Stop
CPU Reset
Core Storage.
Magnetic Core Theory
Writing into Core
Reading out of Core
Adlilressing .
Eight· K Addressing
Four· K Addressing
Module Selection
Addressing· Auxiliary Storage
Core Storage Arrays
Two usec and Four usec Core Storage Arrays
Eight· K Array .
Four· K Array .
Drive Current Generation· Four·usec Storage
Drive Current Generation· Two-usec Storage
Inhibit/Sense· Four·usec Storage.
Inhibit Driver
Sense Amplifier.
Inhibit/Sense· Two-usec Storage
Inhibit Driver
Sense Amplifier.
Timing· Four·usec Storage
Four·usec Storage Clock
Timing· Two·usec Storage.
Storage Address Register
SAR Input Control .
LS to SAR
ALUto SAR.
SAR Output.
SAR Powering
SAR Check .
SAR Display.

1-35
1-35
1·36
1·36
1-36
1·37
1-37
1-38
1-38

2· 1
2222·
22222-

1
1
1
5
5
5
7
7
7

2-12
2·12
2-12
2-14
2-14
2-15
2-15
2-16
2-16
2-18
2-18
2-19
2-19
2-19
2-20
2-20
2-21
2-21
2-21
2-23
2·23
2-25
2-28
2·30
2-31
2-32
2-32
2-32
2-32
2-33
2-33
2-35
2-35
2-37
2-37
2-38
2-38
2-38
2-38
2-38
2-39

iii

Storage Data Register
SDR Parity .
SDR Output.
SDR Display.
Inhibit Switch
Normal Inhibit Operations.
SDR to Inhibit .
ALU to Inhibit .
Mixed ALU/SDR to Inhibit
Inhibit Cycle Steal
Inhibit Check
Inhibit LOG •
Operation Control
OP Register •
.
OP REG Input
OP REG Input for MANOP
OP REG Output.
OP REG Decode
OP REG Bits 4 to 7 .
OP REG Bits 8 to 15
OP REG Display
Cycle Control
Cycle Control Circuits. . . . . . . .
Cycle Control for Operations with Automatic Length
Count. . . . . . . . . . . . . . . .
Move Binary Arithmetic, and Logical Instructions with
ALC .
End OP ALC .
.....
Packed Decimal Instructions with ALC
Length Count Latches
CLC with ALC .
EndOp
SENS or CTRL with ALC
SENS with ALC .
CTRL with ALC
Cycle Control for MANOP's
ICPL .
Storage Scan or Fill .
Storage Test .
Invert Parity Latch .
Long Time Clock
Long Time Clock Latches
Long Time Clock Start and Stop
Reset Clock .
Normal Stop.
Check Stop .
. . . .
Single Cycle or Single Micro- Instruction Stop
Manual Reset Clock.
Clock Functions for Cycle Stealing
Local Store .
. . .
Local Store and Local Store Control .
Local Store •
LS Addressing
LS Input Control
Data forced during CPU LOG in
LS Ou tpu t Control .
LS Zone Selection .
• . . . . .
Zone Selection depending upon Program Level •
PL REG.
NewPL .
Allow PL Switching .
..
Changing of Old PL..
Alternating Use of Old and New PL
Old/New PL during CPU Log in
Zone Selection for Cycle Stealing.
CE Zone Selection .
LS Register Selection .
Variable ~Addresses
Fixed X-Addresses .
Fixed X-Address 0
Fixe:d X-Address 1
Fixed X-Address 2
Fixed X-Address 3

2-39
2·39
2-39
2-39
2-39
2-40
2-40
2-40
2-40
2-41
2-41
2-42
2-43
2-43
2-43
2-43
2-43
2-44
2-44
2-44
2-45
2-45
2-45
2-46
2-47
2-47
2-48
2-48
2-48
2-49
2-49
2-50
2-50
2-50
2-50
2-51
2-52
2-53
2-53
2-54
2-54
2-55
2-55
2-55
2-55
2-56
2-56
2-57
2-57
2-57
2-57
2-57
2-57
2-58
2-58
2-58
2-59
2-59
2-60
2-60
2-60
2-61
2-61
2-61
2-62
2-62
2-63
2-63
2-63
2-63
2-63

Fixed X-Address 4
Fixed X-Address 5
Fixed X-Address 6
Fixed X-Address 7
LS Write.
MAR and Modifier .
MAR.
MAR Inpu t Control.
Branch Go
Test for MAR zero
Test for MAR minus
Test for MAR plus .
Test for Address Check.
Address and Halfword Boundary Check
Modifier .
Modifier Control
Modifier Circuits
Modifier Parity Correction.
Modifier Check .
Logical Unit .
FDR and Invert Switch.
FDR Set.
LS to FDR
ALUto FDR
•
I/O Bus to FDR .
FDR Parity Correction.
Invert Switch
Invert Switch Parity
•
TRBS Invert Switch Parity.
Invert Switch Display
TDR and Shift Unit.
TDR . •
Eight Shift
Eight Shift Parity
Shift Unit
Shift by 2 or 4 .
No Shift Control for ADD!
Normalize Sign .
Suppress .
Test Sign.
Test Packed Byte
Data Bus Output
Shift U nit Parity
Arithmetic - Logic Unit
Six Correction Circuits .
•.
ALU Parity Prediction and Correction
...
Correction of the Predicted Parity if Six Correction
Condition Code Latches
Set CC and Carry
Allow CC Setting
I/O Bus Out and In .
I/O Bus Out .
Address Bus Out
OP REG to Address Bus
I/O Display Address Out
Data Bus Out
Data Bus Parity .
...
Control Strobes for SENSE and CTRL • •
SENSE Strobe and SENSE Control Strobe
Sense Reset and CTRL Strobe.
I/O Display . .
I/O Bu s Powering
I/O Bus In
Bus in Control
CPU SENSE.
I/O SENSE •
Special Purpose Latches
Detailed LOG Request Latch
ASCII Latch .
Interrupt Control
CPU Cycle Steal Control
Cycle Steal Interface

2-63
2-63
2-63
2-63
2-63
2-65
2-65
2-65
2-65
2-65
2-66
2-66
2-66
2-66
2-67
2-67
2-68
2-68
2-68
2-70
2-70
2-70
2-71
2-71
2-71
2-71
2-72
2-72
2-73
2-73
2-74
2-74
2-74
2-75
2-75
2-76
2-76
2-77
2-78
2-78
2-78
2-79
2-79
2·80
2-83
2-83
2-86
2-88
2-88
2-88
2-90

2-92
2-95
2-96
2-96
2-96
2-96
2-98
2-99
2-99
2-99
2-99
2-100
2-100

CS Request
Any CS Request.
Cycle Steal Latch
Device Selection
CS Control
CS Read/CS Write
CS Halfword/CS Byte
CS lncrement/CS Decrement
CS Data In
CS Data Out .
CS Modifier Control
Data Address Updating during CS
Field Length Updating during CS .
CS Counter Zero
CS Counter Carry
CS Modified SAR Bit 15
Checks during CS Operations
CS Address Check
CS Inhibit Check
CS Interface Check .
CS Test

2-102
2-102
2-103
2-103
2-104
2-104
2-104
2-104
2-106
2-106
2-107
2-107
2-109

Chapter 3. Principles of Operation
Basic CPU Operations
Micro-Instruction Operations .
Micro-Instruction Flow and Timing Charts General
Flow-Chart
Timing Chart
Examples of Micro-Instruction Operations
Load Byte Immediate - LBI
ADD Packed Byte - AP, XX - Type
Circuit Controlled Manual Operations (MANOPS)
Cycle Steal Operations .
Micro-Program Operations .

3333333-

Chapter 4. Features

4- 1

Chapter S. Power Supplies and Control
Power Supply and Power Distribution
Power On/Off Sequences
Emergency Power Off
Power Failures
line Failures.
Circuit Overload.
Undervoltage
Overtemperature
S14 Power Switch
S12 Power Control .

SS555555555-

Chapter 6. Console and Maintenance Features
Customer Console
Keys
Power On Key
Power Off Key
Start Key.
Stop Key.
System Reset Key
Load Key
I/O Check Reset Key
Switches.
Mode Switch.
Process
Address Stop (ADR STOP)
Instruction Step (INSN STEP)
Storage Display (STOR DPL Y)
Storage Alter (STOR ALTER)

6- 1
6- 1
6- 1
6- 1
6- 1
6- 1
6- 2
6- 2
6- 3
6- 4
6-4
6-4
6-4
6- 4
6- 4
6- 4
6- 5

2-109
2-109

2-110
1
1
1
2
2
2
2

3- 9
3- 9
3- 9

1
1
2
2
2
2
3
3
3
3
4

Display Register (DPL Y REG)
Alter Register (ALTER REG) .
Storage Scan (STOR SCAN)
Storage Fill (STOR FILL) .
Control Program Load (CPL)
Register Data or Address Switches
Data Switches
Time Sharing Switch
Lamp Test Switch
Emergency Power-Off Switch (EPO)
Meter Lock - Switch
Indicators
P, I, U, L Display
E, S, T, R Display
Attention Indicators
Process
line Failure
Power.
Thermal
Printer
SIOC •
Card I/O 1
Card I/O 2
Card I/O 3
2152 •
STCTRL •
IDC
CE Console
Switches.
CE Mode Switch
Single Cycle Switch .
Single Micro-Instruction Switch
Compare Equal Stop Switch
Storage Test Switch.
Initial Load Loop Switch
Invert Parity Switch
Process Check Override Switch
CPU Check Reset Key .
CPU Reset Key
Lamps Switch
Block Feed Check Switch
1403 and BSCA CE Switches
Display/Compare Select Switch
I/O Display
CE Select Switches •
Indicators
CE Mode Indicator (Red)
CPU Check Indicators (Red)
MOD
SU
ALU
BUS
SAR
INH
Delta Cycle Indicators
Cycle Indicators.
Any I/O Busy Indicator
Any Feed Cell Dark Indicator .
LS Zone Indicators .
CE Display Bits PO to 15 - Indicators
Miscellaneous CE Console Components
CPU Remote Control Socket
Missing Phase Button
Maintenance Features
CPUChecks .
CPU login
CE Volt Meter

6- 5
6- 6
6- 6
6- 6
6- 7
6- 7
6- 8
6- 8
6- 8
6- 8
6- 8
6- 8
6- 8
6- 8
6- 9
6- 9
6- 9
6-9
6- 9
6- 9
6- 9
6-10
6-10
6-10
6-10
6-10
6-10
6-11
6-11
6-11
6-11
6-11
6-11
6-11
6-12
6-12
6-12
6-12
6-12
6-13
6-13
6-13
6-13
6-13
6-14
6-14
6-14
6-14
6-14
6-14
6-15
6-15
6-15
6-15
6-15
6-15
6-15
6-15
6-15
6-16
6-16
6-16
6-16
6-17
6-17
6-17
6-18

Illustrations

1- 1

1- 5
1- 6
1- 7
1- 8
1- 9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23
1-24
1-25
1-26

System/360 Model 20 Layout (Maximum System
Configuration)
Machine Instructions
Byte Layout .
Extended Binary-Coded-Decimal Interchange
Code (EBCDIC) .
Hexadecimal Values
Binary Numbers
Zoned FOlI'1at
Packed Format
Logical Data
Sign Standardization
RR Format
RR-Type Instructions
RX Instruction
RX-Type Instructions
SI Instruction
Test I/O and Branch Instruction
Control I/O Instruction
SI-Type Instructions
SS Format
Transfer Instruction
SS-Type Instructions
Indexing.
CPU Principles
Address Checking
Program Level Control
Internal Data Formats

1- 9
1-10
1-10
1-10
1-11
1-11
1-11
1-12
1-13
1-13
1-13
1-13
1-14
1-14
1-14
1-15
1-15
1-15
1-16
1-20
1-25
1-30
1-32

2- 1
2- 2
2- 3

CPU Basic Timing
Short Time Clock Switching
CPU Start Sequences

2- 2
2- 3
2- 6

1- 2
1- 3
1- 4

1- 1
1- 2
1- 8

2- 4
2- 5
2- 6
2- 7
2- 8
2- 9
2-10
2-11
2-12
2-13

2-24
2-25
2-26
2-27
2-28

Continuously Alter or Display Start-Stop Control
ICPL Start and Restart Sequence
ICPL Start-Stop Timing
CPU Stop Conditions
CPU Reset
Hysteresis Curve of Magnetic Core
Core Store Write and Read (4 us Storage)
Two-Microsecond Core Storage Oock
Core Storage Module Selection
X and Y Address Lines for Location 0000, 8-K
Array .
Inhibit/Sense Lines for Bit 0, 8-K Array .
X and Y Address Lines for Local 0000, 4-K Array
Inhibit/Sense Lines for Bit 0 and 2, 4-K Array
Four-Microsecond Core Storage Oock
Time Delay Circuit, Four Microsecond Storage
Oock.
ALU Cell Carry Conditions
• . . .
Output Bus Lines
Assignment of the Highorder Device Address
Qigit
Device Address/201 Functions during ICPL
Control
Principles of Data Bus Parity Changing during
I/O Sense.
CPU Input Bus Lines
CS Interface .
CS Data Address and Field Length Registers
CS Select.
Update CS Data Address and Field Length

2-94
2-97
2-101
2-103
2-105
2-108

6- 1
6- 2

Display Switching during CPU Log in
First CPU Log in Halfword (Log Cycle 0)

6-18
6-19

2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23

.........

......

2- 8
2-10
2-11
2-13
2-17
2-18
2-19
2-22
2-23
2-25
2-26
2-27
2-29
2-34
2-36
2-85
2-89
2-91
2-93

ABBREVIATIONS

AC
ALe
ALU

Mltn
BSCA
\.s;

Address Check
Automatic Length Count
Arithmetic Logic Unit
American Standard Code for Information Interchange
Binary Synchronous Communications
Adapter

CC
CIO
CPL
cpm
CPU
CS
CY

Condition Code
Control Input/Output
Control Program Load
cards per minute
Central Processing Unit
Cycle Steal
Cycle

DA
DR

Device Address
Data Register

EBCDIC
E-phase

Extended Binary-Coded-Decimal
Interchange Code
Execution-phase

FDR
FL
FS

From-Data Hegister
Flip Latch
Function Specification

Hertz

IAR
ICPL
INH

Instruction Address Register
Initial Control Program Load
Inhibit

INT
I/O
IOC
I-phase

Internal, Integrator
Input/Output
Input/Output Channel
Instruction Phase

LC
LS
LSA

Length Count (latches)
Local Store
Local Store Addressing Check, Line
Sense Amplifier

MAR
MANOP
MFCM

Modify Address-Register
(Circuit Controlled) Manual Operation
Multi-Function Card Machine

NSI

Next Sequential Instruction

OCU
Op code
OP REG

Operation Control Unit
Operation code
Operation Register

PL
PSW

Program Level
Program Status Word

SA
SAR
SDn
SIOC
SU

Sense Amplifier
Storage Address Register
Storage Data Register
Serial Input/Output Channel
Shift Unit

TDR
TIOB

To-Data Register
Test Input/Output and Branch

XIO

Transfer Input/Output

vii

lRM CONFIDENTIAL

CHAPTER 1 INTRODUC TION

which accommodates I/O units, such as the

IBM SYSTEM /360 MODEL 20

IBM 1419 Magnetic Ink Character Reader
or the IBM 1259 Magnetic Ink Character
Reader, that use 1400 serial languages.
The IBM System /360 Model 20 Data Pro-

The system may also be equipped with an

cessing System (Figure 1_1) consists of the

I/O channel which serves I/O devices such

IBM 2020 Processing Unit, the IBM 1403

asthe IBM 2415 Magnetic Tape Unit and

Printer or IBM 2203 Printer, the IBM

Control, or with a storage control feature

1442 Card Punch Model 5, the IBM 2501

to control the IBM 2311 Disk Storage Drive.

Card Reader and either the IBM 2560 Multi-

A Binary Synchronous Communications

Function Card Machine (MFCM) or the IBM

Adapter (BSCA) allows transmitting and

2520 Card Read Punch. The system can be

receiving of data from another source via

equipped with a Serial I/O Channel (SIOC)

telephone lines.

2501
Model Al/A2

1442-5

TAU
for

2415

I/O
Channel

ssC.A

2020 Processor

Custom..... .5tor.,9'=;
~

K, 8 K, U

co,,+>-ol

K,.L'K,2~",32K b>jte$

Storo.~;

SIOC

"";,,,,41<; - """".....1.6 K b~les

~.t~

Im~ 1------~~~-EXCIUSiV.

:------""7

OR _ _

2..1. 52..
Figure 1-1. System/360 Model 20 Layout
(Maximum System Configuration)

2020 FETOM

(5/68)

1-1

IBM CONFIDENTIAL

The system configuration depends on the

available customer area of the main stor-

wishes of the customer, with four excep-

age.

tions:

Either the 2560 Multi-Function Card

The Model 20 can perform 36 different

Machine or the 2520 Card Read Punch

machine operations (instructions). Everyone

or Card Punch can be used, but not

of the 36 machine instructions (Fig. 1-2)

both.

may be used to build the machine (customer's)

Either but not both of the two printers

program.

(IBM 1403 and IBM 2203) can be used.

Only one of the 2520 machines can

The machine instructions have different

be used on the system.

formats; that is, they are either two, four
or six bytes long.

Either but not both of the two magnetic ink character readers (IBM
1419 or IBM 1259) can be used on the
system.

The first byte contains

the operation code (op code) which specifies
the operation that is to be performed (add,
subtract, compare, and so on).

The fol-

lowing bytes contain the addresses of one
or two operands or data itself (immediate

The CPU housing contains the logic circuits of the CPU, as well as the logic
circuits of the I/O attachments, channels
and control features.

The CPU has three

data).

The instructions which use operands

that are greater than two bytes also contain a field length code that specifies the
size of the operand.

console panels: one for the opera tor, another (which is normally covered) for the

NAME

MNEMONIC

FORMAT

customer engineer and a third for operating
the BSCA.

Data and machine instructions (customer)
are entered into the system by means of a
card reader (2501, 2560 or 2520), and
placed into the customer s area of the main
storage (core storage) as logical data.

The basic format of the logical data is a
byte. One byte consists of a parity bit and
eight data bits.

The addressing system allows selection
of any byte or group of bytes within the
1-2

(5/68)

BRANCH ON CONDITION
BRANCH AND STORE
ADD
SUBTRACT
STORE HALFWORD
BRANCH ON CONDITION
LOAD HALFWORD

COMPARE HALFWORD
ADD HALFWORD
SUBTRACT HAL'FWORD
BRANCH AND STORE
SET PSW
TEST UNDER MASK
MOVE
AND
COM:J>ARE
OR
HALT AND PROCEED
TEST lIO AND BRANCH
CONTROL lIo
TRANSFER lIO
MOVE NUMERICAL
MOVE CHARACTERS
MOVE ZONE
COMPARE
TRANSLATE
EDIT
MOVE WITH OFFSET
PACK
UNPACK
ZERO AND ADD
COMPARE DECIMAL
ADD DECIMAL
SUBTRACT DECIMAL
MULTIPLY DECIMAL
DMDE DECIMAL

fj'.\~re J.-~

BCR
BASR
AR
SR
STH
BC
LH
CH
AH
SH
BAS
SPSW
TM
MVI
NI
CLI

HPR
TIOB
CIO
XIO
MVN
MVC
MVZ
CLC
TR

ED
MVO
PACK
UNPK
ZAP
CP
AP
SP
MP
DP

OP
CODE

RR
RR
RR
RR
RX
RX
RX
RX
RX
RX
RX
SI
SI
SI
SI
SI
SI
SI
SI
SI

07
OD
1A
1B
40
47
48
49

ss
ss
sa
ss
ss
ss
sa
ss
ss
ss
ss
ss
ss
ss
ss
ss

DO
Dl
1>2

4B
4D
81
91
92
94
95
96
99
9A
9B

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IBM CONFIDENTIAL

Instructions are normally stored in con-

In the Model 20, the machine program is

secutive main storage locations and are

automatically interrupted when all required

executed sequentially.

data of an I/O operation are transferred.

However, the se-

quence of operations may be altered at any

This interrupt causes a branch in the machine

point in the program by conditional branch

program.

instructions.

by the programmer and may start a program

Conditional branch instruc-

The branch address is defined

tions make logical decisions by performing

routine which performs operations necess-

tests on indicators set by the machine as

ary when a data transmission to or from an

a result of other operations (such as a

I/O device is terminated.

comparison of two operands or a forms

interrupt can be disabled under program

skip after print).

control.

The Model 20 uses the System /360 machine

The execution of the 36 machine instruction

language that is able to process data of

is the task of the Control Program (micro-

fixed length (fixed-point data) as well as

program). The control program is a CPU

a string of data the number of which is

internal sub-program, to which the cust-

defined by a field length (variable -length

omer has no access.

data).

is stored in the control area of the main
storage.

However, this

The control program

The capacity of the control area

The CPU controls the functions of all I/O

depends upon the Storage capacity rented

devices attached to it.

by the customer.

However, I/O

operations are initiated, halted, or tested
by program instructions which select the

The control program consists of micro-

desired unit and determine the operation

instructions which are combined to exe-

it must perform (read, punch, and so on).

cute the functions indicated by a machine
instruction.

The micro-instructions direct-

The CPU is available for processing during

ly control the circuits in the CPU and in

each I/O operation, even though several

the attachments. 44 different micro-in-

I/O devices may be functioning simultan-

structions are available.

eously.

This overlap of I/O operations

and CPU processing is called time sharing
or read/write compute overlap. These
modes are accomplished by allowing the

INPUT/OUTPUT DEVICES

CPU to cmtinue with the machine program
after data transmission to or from the spe-

2501 Card Reader, Models AI, A2

cified I/O unit, while this unit is still completing the mechanical aspects of reading,

The 2501 Card Reader provides punched-

punching, printing and so on.

card input to the Model 20.

Cards are read

2020 FETOM

(5/68)

1-3

at a :maxi:mu:m rate of 600 cp:m in the Model
Al and up to I, 000 cp:m in the Model A2.

2520 Card Read Punch
The 2520 Card Read Punch provides punched- card input/output for the Model 20.

Card reading is acco:mplished by solar
cells and the validity of the data is veriCards are read, read and punched, or
fied as each colu:mn is read.

Each card
punched at the rate of 300 or 500 cards

is also checked for off-register punching
per :minute (cp:m) according to the :model.
and for incorrect positioning in the read
station.
Model
The 2501 functions under control of the
Model 20 progra:m.

Speed
500 cp:m

Operation
Read only, punch only,
or read and punch si:m-

Lights and switches

provide the operator with infor:mation on

ultaneously, as directed

operating conditions and with control of

by the Model 20 progra:m.

start, stop and card run-out.

2560 Multi-Function Card Machine

500 cp:m

Punch

300 cp:m

Punch

Card feeding is in parallel fro:m the hopper,
serially through the read station and in

The 2560 Multi _Function Card Machine

parallel through the punch station.

affords the Model 20 full card-file :main-

are ejected into radial stackers.

tenance abilities plus two, four or six linccs

Model 20 progra:m can ·select which of the

of card printing.

two stackers receives each card.

The 2560 consists of

Cards
The

If no

two hoppers, a solar-cell read station,

s election is made, the card goes into

a co:m:mon punching station, an optional

stacker 1.

printing station and five selective stackers.

The 2520 has lights and switches to pro-

Cards fro:m both the pri:mary and secondary

vide the operator wi th infor:mation on oper-

hoppers can be read, punched and selected

ating conditions, and control of start, stop

into anyone of the five stackers, regard-

and card run-out.

less of the hopper of origin.

trol of the Model 20 progra:m during all

The unit re-

The 2520 is under con-

cord functions of reproducing, gang-pun-

phases of reading, punching. stacker se-

ching, su:m:mary punching, collating, de-

lection, and data checking.

collating and sorting can be perfor:med on
the MFCM under control of the Model 20
progra:m.

1442 Card Punch, Model 5

With the optional docu:ment

printing feature, the MFCM functions in-

The 1442 Card Punch Model 5 provides

clude those of an interpreter and a pun-

punched-card output for the Model 20.

ching, co:mparing, card docu:ment printer.

The 1442, Model 5 has a card hopper. a

1-4

(5/68)

serial punch station and a radial stacker.

The dual-feed carriage special feature

Card punching is done serially at a max-

permits independent and simultaneous

imum rate of 160 columns per second.

control of two sets of forms.

Punching accuracy in the 1442, Model 5
is verified by comparing a signal, generated as each hole is punched, with
data in the CPU core storage.

Control

1403 Printer, Models 2, 7, N1

of the 1442 is by the CPU stored progThe 1403 Printer provides output for the

ram.

Model 20 at a rate of 600 lines per minute.
The Model 2 has a capacity of 132 printing
positions and the Model 7 can print 120
2203 Printer, Model

positions.

The Model N1 prints 1,100

lines per minute on 132 positions.
The 2203 Printer provides output for the

Single, double and triple spacing of lines,

Model 20 at up to 750 lines per minute.

plus skipping to a predetermined point,

Interchangeable type bars allow the oper-

are performed by the tape-controlled car-

ator to select a type style and character

riage, under control of the CPU stored

set for a specific printing job.

program.

The printing speed for anyone application

carriage that permits high-speed skipping.

depends on the total number of lines printed, the amount of processing required for
each printed line and the character set

The Model 2 has a dual- speed

Each printing position can print 48 different
characters and the printing format is. controlled by the stored program of the system.

used.
As each character is printed, checking
circuits are set up to ensure that the characSingle, double and triple spacing of lines,

ter printed is correct.

plus skipping to a predetermined point, are

made to ensure that only valid characters

performed by the tape-controlled carriage,

are printed and that overprinting does not

directed by the CPU.

occur.

The sequence and

Checks are also

If an error is detected, the m.achine

arrangement of data printed are also con-

stops and the associated check light comes

trolled by the stored program; a line to be

on.

printed is assembled in core storage ln
exactly the same sequence in which it is
to appear as output.

To ensure accuracy

2152 Printer - Keyboard

of output, each character is checked with
the corresponding position in core storage

The 2152 Printer-Keyboard consists of a

before being printed.

table mounted typewriter that is cab1e2020 FETOM

(5/68)

1-5

IBM CONF!DENTIAL

connected to its attachment in the CPU.

Six models of the 2415 Magnetic Tape Unit

The 2152 is used mainly as an inquiry

are available.

station which allows the operator to re_

unit is a cabinet containing two tape drives,

trieve information (e. g., from a disk

the tape control unit and the power supply.

file), and to print this informations.

The additional tape drives required for the

Inquiries via the Printer-Keyboard are

bigger models are housed in cabinets bolted

especially advantageous when jabs are

to the basic unit.

being run sequentially and there is a need

All models are equipped with two-gap read/

to know the current working status.

write heads which permit immediate read-

The Printer-Keyboard can also be used to

back after writing, for error_detection pur-

change information or data in a just

poses.

running program.

mm) per second in each case, and all mo-

In all models, the basic

The tape speed is 18.75 " (476,25

dels can read backwards.
Beside the above mentioned functions, the
2152 may be used as a secondary, low

The 2415 is attached to the CPU via the

speed printer, so that two separate reports

Input/Output Channel

may be produced by the same program.

gulates the flow of data' to and from the
system.

(roc).

The IOC re-

Input and output are controlled

The 2152 has a 125-character print line.

by the stored program, which initiates

The machine prints at 15.5 characters

operations by pas sing instructions to the

per second, producing one original print

channel.

and a maximum of four copies.

by the tape control in the 2415 operating

Printable

are 88 characters of the standard System

These commands are accepted

the tape drives.

/360 layout.
Vertical spacing of three or six lines per
inch can be manually selected by the
operator.

Selectable spacing of four or

eight lines is optional.

2311 Disk Storage Drive
The models 11 or 12 can be attached to the
system.

A significant increase in data

storage capacity for the System/360 Mod 20
is provided by the IBM 2311 Disk Storage
2415 Magnetic Tape Units

Drive.

The amount of information that

can be stored is virtually unlimited since
The 2415 Magnetic Tape Unit is used as
mass storage.

The machine functions as

an input and output device entering data

the disk pack holding the data is easily removed and stored on a shelf.

Thus, an

entire library can be kept off-line.

into the system, and recording data gen-

The 2311 is connected to the CPU via the

erated by the system.

Storage Control feature.

1-6

(5/68)

IBM CONFtr

The Storage Control feature accommodates

.AL

1419 Magnetic Character Reader

two 2311' s of the same model (models 11
and 12 cannot be intermixed on the same

The 1419 Magnetic Character Reader can

system). Since both models use the same

be attached to a Model 20 through the

disk pack, the data format is the same,

serial input/output channel device. The

that is, a fixed length of 270 bytes.

1419 reads into the system the magnetically inscribed information on checks and
other banking documents, at speeds as
high as 1,600 documents per minute. Do-

Binary Synchronous Communications Adap-

cuments can be sorted into as many as

ter

13 clas sifications as they are read.

(BSCA)

The BSCA is a fully program-controlled
communications adapter offering teleprocessing at accelerated speeds to the

The SIOC and, in turn, the 1419 operate
under the control of the Model 20
program.

System /360 Model 20. The BSCA can
communicate in point-to-point or in
multipoint fashion.

1259 Magnetic Character Reader

In the first case, data

exchange is between only two stations at a
time; in the second case, a master station
consisting of a larger model of the System
/360 can select or poll one of several
Model 20 slave stations interconnected on
a leased or private line.

The 1259 is a medium-speed machine
capable of reading and sorting magneticink-inscribed banking documents of inter_
mixed sizes and paper weights at speeds
up to 600 documents per minute.

The

machine is connected to the Serial I/O
Channel (SIOC) to operate under control
of the machine program in the CPU, or

The BSCA can tran.smit and receive all
characters of the EBCDI or ASCII Code,
whichever code is specified, since these
are used directly as line codes.

it can operate off-line as a sorter under
the control of its own circuitry and the
operator's panel on the 1259.

Eleven

control characters provide for specific
data link functions, which the program can

PROGRAMMING

use to control the data exchange in many
ways.

Thus, more operational flexibility

Data Formats

is introduced, since almost all controlling

The basic data format is the byte (Fig.

power is given to the program.

1-3).

The byte consists of eight data bits

2020 FETOM

(5/68)

1-7

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00

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CD
Total 255
qg

Tol-c~l

S;v\CW-j VCl/ucS(f-IQ~ b:tte) Total L5 . IV! hekaaec(lMal"'/F/
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11 12 15 16 1920
31 32 3536
47

~:S~~:~~ioJ Op Code I
o

6 Bytes

0]/1

15161920

D/O

B2
31323536

Figure 1 - . SS Fonnat

eight bits in size.

This length code refers

to operand 1 only.
The length code may specify operand 1 sizes
from 0 to 255 bytes to the left of the units
byte, equaling operand sizes from 1 to
256 bytes.

l,q.

the leftmo st byte of operand 2 (Figure 1-19).

Among the 55 instructions is the third I/O
instruction.

The length of operan d 1 is specified by the
Ll field in the instruction.

The length of

operand 2 is given in the L2 field.

The Ll/

This instruction has a some-

what different internal structure as shown
in Figure 1-20.

The Transfer I/O (XIO)

instruction causes a data transfer from an

L2 fields have four bits each and the maxi-

I/O device to the lTIain storage, or vice

mum number that can be represented is

versa.

15.

number in these fields is actually

a field length code because it specifies the
number of bytes that extend to the left of the
units byte of an operand. Thus, the true
length of every operand is always one byte
longer than indicated by the field length

The DA field specifies the particular

I/O device (printer, card reader, and so
on) and the F5 field specifies the particular
function in the addressed device (for example,
punch secondary).

The Bl/Dl field is the

address of the leftmost byte of the input or
output field in the main storage.
may be altered via indexing.

code.

This address

The B2/D2

field, which may also be indexed, is true
field length. Although this field length contains
16 bits, the field length is limited to 4,095
This field length specification is used to

bytes for other reasons. Also, the field

obtain a carry frolTI a length counter when the
units byte is reached.

Also, it is possible
op Code

to obtain the units byte address by simply
adding the length code to the address of the
leftmost byte of an operand.

The 55 format instructions that handle
logical data have only one length of code field,

14
10 - - - - - - 6 Bytes

---------1

IOp Code I DA I FS I Bl I
o

Figure 1 - .

ttl·

B2 ....l-!::.I
D(
D) L.:/l---1-=.

11 12 15 16 1920
Transfer Instruction

31323536

Mnemonic

Type of Doto Condi ti on Code

Processed

Influenced?

Move with Offset

MVO

Any

Pack

PACK

Any

Unpack

UNPK

Any

Zero and Add

ZAP

Decimal

yes

Compare Decimal

Decimal

yes

Add Decimal

Decimal

yes

Subtract Decimal

Decimal

yes

Multiply Decimal

Decimal

Divide Decimal

Decimal

Move Numerics

MVN

Any

Move Characters

MVC

Any

Move Zones

MVZ

Any

Compare Logical

CLC

Any

Edit

Dec/Logic

yes

Translate

Any

XIO

Any

DC
47

Name

in Hex

DO
Figure

1-.

Transfer I/O

SS- Type Instructions

2020 FETOM

(5/68)

1-15

ISM CONF!DE~mAL

length must not be zero or else an error

D-part.

will occur.

one solid field, that is, the total binary

Figure 1_21 shows the 55-type instructions.

value of the 14 low-order B/D bits repre-

Normally, both parts are used as

sents the operand address.
direct addressing.

This is called

It is possible to generate

another address, however, from the same
Indexing

BID field without changing anything in the
instruction.

•

Indexing is a method of address
generation.

The Bfield is not only part of the direct
address, but may also become the address

•

The B field and the D field of an in-

of a general register.

struction are used to generate a new

registers in the protected area have binary

address.

addresses from 8 to 15.

The eight general

As the B field

consists of four bits, it can address such a

•

The B field addresses one of the eight

general register as soon as it contains eight

general registers in the protected area

or more.

to read out the bas e addr e s s.

content of a general register (the base address)

Thus, the B field reads out the

and this content is then added to the D field

•

The base address is added to the D

(the displacement) of the instruction.

The

field (displacement) and the result is

result of this add operation represents the

the new address.

new address.

This is called effective ad-

dressing or indexing.

Indexing is performed by the micro-program

All instructions that process data located

which automatically checks the 8 bit in the

in main storage have an address field for
each operand, to be able to fetch the operand
data from

main storage (Figure 1-22).

The

address field is divided into a B-part and a

B field to find out whether indexing is required.

If an 8 bit is found, the indexing

routine is performed.

Indexing is ineffective

when the addressed general register contains
zero.

It is also ineffective when the D

field is zero.

DATA TRANSFER PRINCIPLES
CPU - I/O DEVICES

•

Input data is read into CPU via I/O
devices.

mM CONFIDENTIAL

•

Input data is being processed in the

Time Sharing Mode

CPU and the resultant data is subsequently transferred to an I/O device that produces

•

the output.

Time sharing mode is active when the
Time Sharing switch on the customer
console is in position on.

•

Data transfer between CPU and

r/o

devices (or vice versa) is a very
substantial part of all processing

•

customer instruction as soon as the

operations.

•

Time Sharing allows the issue of a new

previous one has been accepted.

Data transfer can be performed in either

•

The continued customer program is

r/o

burst mode, time sharing mode, or

interrupted by

overlap mode.

indicate that a data unit has to be

requests which

transferred.

•

During burst mode operations, the total

•

The

devices can operate at the

r/o

requests of the running

devices are satisfied depending upon

instruction (field length) is transferred

a fixed priority scheme if more than

in one single continuous flow.

one request is active at the same time.

The flow stops when all specified data

•

Operating in time sharing mode, the
CPU uses the time between subsequential

r/o

requests (e. g. , between two

card columns to be read) to perform
During burst mode operations, the
any other operations including data
customer program is completely intransfer from or to
active (no new instruction is sued).

•

r/o

amount of data specified in the I/O

units have been transferred.

•

r/o

same time.

Burst Mode

•

Several

The termirlation of burst mode operations
is indicated by condition code settings
(Tape, Disk, etc.)

or by requests

r/o

devices.

Overlap Mode

•

Overlap Mode can be considered as
time sharing for

r/o

devices with a

for interrupt (card I/O devices not

high data transmission rate (Disk,

operating in time sharing .rpode).

Tape, BSCA).

2020 FETOM

(5/68)

1-17

IBM CONFIDENT!AL

•

The request of these high speed I/O
devices are of highest priority.

•

Contrary to tim.e sharing operations,
which require a control program routine (service phase) to transfer a data
unit, the overlap mode data transfer
is performed within one process (CPU)
cycle only.

•

Overlap operations can transfer two
data units (bytes) at a time.

1-18

(5/68)

IBM CONFIDENTIAL

IBM

2020 CENTRAL PROCESSING UNIT
( CPU)

sists of micro-instructions arranged in
logical sequence necessary to execute the
operation called for by the machine language
instruction.

•

The CPU is main control unit of the
whole system.

The micro-program is also stored in main
storage, but in an area not accessible to the

•

The CPU processes data and controls

customer.

This restricted area is called

input/output (I/O) operations.

control area and is physically a part of the
core storage array which also contains the

•

For I/O operations the CPU activates

customer's area.

the control units (attachments, channels,

The control storage area is specified by

control features)

addresses higher than the highest possible

of the I/O devices.

customer's address (depends upon the custorner's storage size)

OPERATING PRINCIPLES

Micro-Instruction Operating Principles

•

Machine language instructions are

instruction Op code.

executed by micro-program.

•

The micro-program consists of micro-

•

The principles are shown in figure 1-23.

•

mode.

machine language instructions are linked

machine program is loaded and stored in

Only one processing period is executed
when operating in CE Single Cycle

In order to solve a customer's problem,

to build a program (Figure 1-23). This

Micro-operations require one to
four processing periods.

instructions linked in a logical sequence

•

Micro-operations are defined by the

•

A processing period exists of delta
cycle and cycle.

main storage. Machine language instructions are performed in series.
•

The timing pulses 'delta cycle and cycle'
are provided by the Long Time Clock.

Machine language instructions are investigated (instruction phase, I-phase) and their

•

During a proces sing period 13 steps

specified operations are executed (execute

are performed, which are defined

phase, E-phase) by a sub-program, called

by the T-pulses of the Short Time

Micro-Program.

Clock.

This micro-program con-

2020 FETOM

(5/68)

1-19

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XIO

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I
I

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Ila! I Ihl~J1_1T~SI_~I~~!JA ~Of\_~':!_l.~!~~[!3_J
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MAIN STORAGE

_______ ,

PRocE"SSJ.NG PERIOb

(;"'cI....d.;.,3 Au)(j liQY!,( Stora~~ )

-i

SHoRT TIHEC/.OCI<

(l3C\s;cnm;"1l)

LON6 TIME CLOCk (c'.1c1e (ollltroL)

»r

IBM

•

(,~NFIDENTIAL

The Short Time Clock generates the

start of delta cycle, while the delta cycle

pulses TI

information is accepted by the cycle latches

T8 continuously after

power on.

at start of process cycle.

Micro-Instructions are always one halfword
(two bytes) in length.

Their functions are

specified by an operation code (Op code) in
the highorder part of the instruction.

The two delta cycle and cycle latches switch
binary and provide delta cycles and cycles

o to

3 (processing periods 0 to 3).

The

loworder part provides immediate data

Each of the four processing periods is

and/or register addresses.

assigned to a fixed purpose which depends
upon the one possible main storage access:

For execution, the micro-instructions are

Processing period 0: Read out micro-

read out from the ITlain storage and set into
the operation register (OP REG).

instruction.

Reading

of micro-instructions and placing them

Processin~

Eeriod 1·

Read out second
(From) operand.

into OP REG is controlled by circuits functioning during instruction start only.

Processin~

:eeriod 2:

operand.

The bit pattern of the micro-instruction in
OP REG activates decode circuits which
generate control signals.

Read out first (To)

Processing :eeriod 3·

Store result.

These signals

directly control the CPU circuits to per-

For example, a micro-instruction with both

form the specified micro - operation (Op

operands

code) .

processing periods in sequence when the

in main storage,requires all four

operation result has to be stored. However,

One micro-operation requires up to four
processing periods.

During every pro-

cessing period only one main storage access
is possible. Thus, the number of processing

a micro-instruction with both operands in
CPU registers, outside main storage

only,

requires processing period 0 (read out
micro-instruction, one storage access).

periods during a micro-operation depends
upon the number of required storage accesses.

Micro-instructions with either the from or

A processing period is defined by a delta

to operand in main storage require besides

cycle and process cycle.

processing period 0 , either processing

Delta cycle and

process cycle are timing pulses provided

period 1 or processing periods 2 and 3.

by a latch ring.

To execute only the required processing

This latch ring is advanced

by specified basic timing pulses generated

periods. the Long Time Clock can be ad-

in the Short Time Clock.

vanced out of sequence by control signals.

The· latch ring,

defined as Long Time Clock, consists of

These control signals are generated in a

two delta cycle latches and two cycle latches.

circuit, called Cycle Control.

The delta cycle latches are advanced at each

eration depends on the micro-instruction

Their gen-

2020 FETOM

(5/68)

1-21

IBM CONFIDENTIAL

Op code and information where the operands

•

-are located (main storage or CPU register).

CPU basic operations directly control
CPU circuits.

A processing period is divided in 13 steps.
These steps are defined by timing pulses

•

The available logical CPU circuits

(T-pulses) of the CPU basic timing. The

determine the number of basic

T-pulses are generated by a latch ring called

operations which can be performed.

Short Time Clock.

Pulses A and B, gener-

ated by a crystal oscillator, advance the

Micro - Operations

Short Time Clock. T-pulses are numbered
from 1 to S.

Eight T-pulses define the

process cycle period (T1 to TS). The required 13 steps of a processing period are
achieved by overlapping processing periods
in which the delta cycle consists of T4
through TS plus T1 through T3.

Micro-operations are specified by microinstructions. The micro-instruction bit
pattern in OP REG directly controls the
Logical CPU circuits by generating main

control signals.

These main control signals

are timed by delta cycles and cycles, and by
pulses T1 to TS.
The 43 available micro-instructions are

A micro-operation is performed in functional
given in FEMDM, 2020 CPU, figure 5-0.

steps such as moving data from one register
into another. The functional steps to be
executed are requested either unconditionally

Micro-operations process data available
in main storage or in a work storage device
called Local Store (LS).

by circuits or by the micro-instruction Op
code and are timed by processing periods
(delta cycles and cycles) and T-pulses.
Example:

The micro-instruction address

Local Store

has to be moved into the main storage address
register (SAR) during processing period 0
(delta

C YO) at T 5.

Thi s functional step

is requested by circuits.

The LS contains 64 halfword registers. For
addressing a single LS register, the LS is
divided into eight zones (0 to 7). Each zone
contains eight registers (0 to 7).

Functional steps can be performed simultaneously, if they use separate CPU circuits.

Each zone is assigned to one of eight
possible program levels (PL's). PL's
to 7 are caused by I/O requests.

PL 7

indicates the highest priority I/O request.
CPU BASIC

OPERATIONS

PL 0 is the CPU operating level which is
active when no I/O request has to be served.

•

1-22

Basic operations are: Micro-operations,

The registers 0 to 6 in a zone are general

circuit controlled manual operations

purpose registers.

(MANOP's), and cycle steal operations.

the To- or From-Reg fields in the micro-

(5/68)

They are addressed by

instructions.

Address Register (IAR). During microoperations the IAR contents are incremented

The RI format allows data transfer and

by 2 to obtain the address of the next se-

logical operations between a register and

quential micro-instruction (NSI).

an immediate data byte in the instruction.

For

branching the IAR contents are changed.

The data transfer or operation takes place

Not that changing the PL by a I/O request

between the specified To-REG and the im_

(addressing another zone) causes a branch

mediate data byte.

to the address in IAR of the new zone.

in the To-REG.

The

The result is stored

IAR (LS register 7) is only addressable in
store-type micro-instructions.

Load-type

The RD format provides a displacement

instructions, addressing the IAR, are

address one byte in length.

treated as No Operations to prevent erroneous-

ment address is used as the loworder byte

ly changing of the instruction sequence.

of a halfword address.

For FF or I/O format instructions the con-

of this address is the highorder byte of the

tents of the register specified in the To-

IAR (block address).

or From-Reg fields are used as data if

The To-Reg field specifies the LS register,

the highorder bit of the field is off (direct

the content of which is tested to decide

addressing) or as main storage operand

whether branching is perfonned or not.

This displace-

The highorder byte

addresses if the bit is on (indirect addressing).
Instruction bit 15 on (indirect addressing)
For FF and I/O format instructions the
operand address is automatically updated

indicates that the combined address is
used to read out the final branch address.

(incremented or decremented) according to
the processed data format (byte or half-

Exceptions:

word).

LH. With this instruction the specified LS
register is loaded with the contents of the
addressed halfword.

Micro-Instruction Formats
The three basic instruction formats are:

STH. With this instruction the contents of

Immediate instruction fonnat (RI
fonnat)

addressed halfword.

~ I/O instructions are a special

case of the RI fonnat.

the specified LS register is stored in the

(See

"I/o Micro-

For both instruction indirect addressing
is performed if bit 15 is on.

Instruction Fonnats". )
The FF format allows data transfer and

Instruction format with displacement

logical or arithmetic operations between

addressing (RD format)

two registers or data fields in core ad-

2020 FETOM

(5/68)

1-23

IBM CONFIDENT!,'\L

dressed by the contents of these registers.

PL's, the check is not effective, but the

There exist four different types:

addresses can be checked by means of a

Both registers are used as data

BAC-instruction.

registers

in PL's 1 to 7, the instruction is executed

(DD type)

For address checks

with the deviations indicated in Figure 1-24.
2.

One register is used as data register

For odd halfword addresses, the next lower

and the other is used as address re-.

even address is used.

gister specifying a

FROM ADDRESS' .

Automatic length count (ALC) is available

(DX type)

for several FF format instructions of the
3.

One register is used as data register

xx-type.

This feature allows a string of

and the other is used as address

halfwords/bytes to be processed by one

instruction. The automatic length count is

(DX type)

activated when LS Register 3 is used as
To-operand, and LS Register 5 as From-

Both registers are used as address

operand.

registers specifying a 'FROM AD-

length - codes (L1/L2), the LS registers

DRESS' and a

are used.

TO ADDRESS' (XX

For operations which need two

Operations with one length count

(L) use the contents of LS Register 1. The

type).

content of a length count register indicates
The operand address of the most FF format

the number of bytes to be processed minus

instruction are checked when the AC bit

one (or two for halfword operations).

is on.

The ALC operation ends when the field
lengths are decreased below zero (registers contain /FFFF / for byte operations

Address checking involves:

Checking of halfword boundaries
(error: odd address, effective only

or /FFFE/ for halfword operations.
~

Besides the FF format instructions,

ALC is also available for I/O instructions

for halfword operations).

when the To-Reg field address LS register
2.

Checking of available customer's

7 and indirect addreSSing is specified.

storage (error: exceeds highest

The setting of condition cod e for the binary

possible customer's address).

and logical instructions is programmable
(bit 6 of the instruction).

Checking for protected area (error:
address within the first 144 bytes)

The decimal in_

structions will always set a condition code.
For the binary instructions AR, SR, ARSC

An address check causes PL 2 by request

and SRSC and for the logical instructions,

if the CPU is working in PL O.

AND, OR, EOR and CLC when used in

1-24

(5/68)

In higher

IBM CONFIDENTIAL

Program
Level

Customer Storage
Address
Store
Checking I Fetch
Operation
specified Operation

yes
yes
no

0"
0, "0"'

X:
R:
0:

N:
T:

I
I

I~
jX

RT
R

Control Storage
Not existent St.
Fetch
Storl!!
i Fetch
Store
Operation Operation! Operation, Oper.

!
,

NT
N
N

CT
0
0

Data are fetched/stored
Storagedata are regenerated, i. e. storage data are not destroyed.
Zeros are used instead of storage data.
Data are not stqred but lost.

p,-

$""'t'~ck:lII~ ;s

pev-ft>II"c.-.eci •

XX format with auto length count and setting

The overflow latch of the condition code lat-

of condition code specified (bit 6 of the in-

ches can also be forced on if:

struction), these instructions should be preceeded by a CTRL-instruction, which sets
the condition code to zero (1000).

With an AP instruction in XX format
the carry latch is on at the end of

The decimal instructions, AP, SP, ZAP

the operation.

and PPC should always be preceeded by a
CTRL instruction.
2,

By all decimal instruction, AP, SP,

For AP and ZAP this CTRL instruction sets

ZAP, PPC in XX format with auto-

the condition code to zero (1000) and the

length count when LI

carry latch off.

ceeding positions of the second operand

L2 and the ex-

are not zero,
For SP and PPC this CTRL instruction sets
the condition code to zero (1000) and the

Binary instructions:

AH, AHSC, SH, SHSC

carry latch on.

Condition Code:

1000

Result is zero

0100

Result is less
than zero

For all these instructions with auto-length
count the setting of the condition code is

0010

than zero

inhibited after a setting of the condition
code other than zero is detected.

Result is greater

xxxI

overflow

2020 FETOM

(5/68)

1-25

Logical instructions:

AND, OR, EOR

Condition Code:

1000

Result is zero

0100

Result not zero

I/O Micro-Instructions

The two I/O micro-instructions are Sense
I/o and Control I/O.

Logical instruction:

CLC

Condition Code:

1000

The Sense I/O instruc-

tion fetches data or information from the

0100

0010

Operand 1 equals

attachments, while the Control I/O instruc-

Operand 2

tion sends data or control information from

Operand 1 is smal-

the CPU to the attachments.

ler than Operand 2

The attachment point to be sensed or controlled

Operand 1 is greate' is speCified by the device address field in
than Operand 2

the instruction.

Since this field is one byte

in length, 256 different attachment points
Decimal instructions: AP,
Condition Code:

SP, ZAP, PPC

1000

Result is zero

0100

Result is not
zero

xxOl

Overflow

can be specified.
Note:

CPU is considered as an additional

attachment.

Normally the device address

is expres s ed by two hexadecimal digits.
The To-Reg field in the instruction defines
any LS register from

During arithmetical operations a carry out
of the loworder byte (byte operations) or
out of the highorder byte (halfword operations) turns on the Carry Latch.

In addition, the carry latch can be set, together with the condition code, by a CTRLinstruction.

The contents of the specified

a to

6 and the high-

order bit of. the To-Reg field decides whether
the specified LS register is used as data
register (direct addressing) or as address
register (indirect addressing).

Both instructions are executed with ALC
when the To-Reg field contains 7 and indirect
addressing is specified.
LS register 1 contains the field length of the
ALC operation. LS register 6 contains the
address, addressing the storage location
where I/O data is to be stored for SENS

In all PL's other than PL 0, where the microprogram can set/reset condition code or

or where the I/O data is available for
CTRL.

carry latch, the value of the condition code

The length count is decremented by 1 for

and carry latch mU:st be saved by a SENS-

each transferred byte.

instruction. Before leaving the Program
Level, the original value of the condition

The operation ends when the LS register 1

code and carry latch should be restored by

is decremented below zero (contains

means of a CTRL-Instruction.

/FFFF/).

1-26

(5/68)

1 CONFIDENTIAL

The contents of address register 6 is in-

circuit controlled manual operations (MANOP's)

cremented by 1 for each transferred byte.

can be considered as basic operations similar
to micro-instructions.
MANOP's are also performed in processing
periods.

Within the processing periods

Circuit Controlled Manual Operations

functional steps are performed as during

(MANOP's)

micro-operations.

The main signals, necess-

ary to control the CPU circuits, are generated
Generally, manual operations are selected

depending upon turned on MANOP control

by the mode switch on the customer console.

latches and switch positions.

The s electable manual operations can be
MANOP's, processing strings of data, op-

divided into two groups:

erate in a way similar to ALC micro-in-

Manual operations performed by
micro-program.

struction.

These operations

are Instruction Step, Address Stop,
Display Register, and Alter Register

Storage Alter/Fill

(see micro-program flowcharts
FEMDM, 2020 CPU, Appendix B).

The byte, set up in the two data switches,
is moved into an addressed main storage
position.

For Storage Alter, only the main

Circuit controlled manual operations.

storage address set up by the four address

These manual operations are:

switches is affected.

Storage Fill can be

Storage Alter

considered as Storage Alter operating in

Storage Fill

ALC mode.

Storage Display

the address switches, is incremented during

Storage Scan

every byte movement.

Storage Test

possible halfword address is exceeded

The start address, provided by

After the highest

( /FFFF/ +1 ). storage Fill continues with
LS Register Alter

address /0000/.

LS Register Display

Storage Fill ends when the Stop key is operated.

Initial Control Program Load
(ICPL)
CPU LOG in

Storage Display/Scan
An addressed byte is displayed in the data

With the exception that the Op code is simulated

by switch settings or key operation, these

operation performed is similar to Alter/

2020 FETOM

(5/68)

1-27

Fill with the exception that the byte set up

Note:

in the data switches is not moved into main

LS halfword is read out again and compared

storage.

against the origin halfword in the CE Select

Storage Scan can be considered as

For LS register alter, the just loaded

Storage Display operating in ALC mode.

switches.

Scan investigates the main storage contents

Check occurs without any other CPU check

for correct parity.

indic ation.

Incorrect parity is re-

If the compare is unequal

Process

cognized by the Shift Unit Check.

ICPL
Storage Test

ICPL can be considered as a complete card
Storage Test can be considered as a .modi-

read XIO instruction (machine language) in-

fied Storage Fill operation (mode swi~ch to

cluding service phases. ICPL controls the

Storage Fill and CE Storage Test switch on).

CPU circuits to read the control program

Storage Test is performed by four different

loader card into main storage. After the

runs.

loader card has been read, CPU operates

A run covers the main storage addresses

/0000/ to /FFFF /.

During runs 1 and 2

each core storage halfword position is loaded

under control of the micro-instructions
previously read in from the loader card.

with its address and the address is read
out again for compare.

Runs 3 and 4 per-

form the similar functions but loading and
comparing is performed inverted.

CPU LOGin
CPU LOG operates like a four cycle microinstruction.

This operation stores four half-

words of CPU status informations into a
LS Register Alter/Display

The mode switch is set to Alter or Display
Register and the CE mode switch has to be

defined main storage area. CPU La. uses

separate circuits so that the LOG information can be saved even if the normal CPU
circuits fail to operate.

turned on.
The LS register, defined by data switch 2 of
the LS zone specified by data switch 1, is
altered by the halfword set up in the CE

CPU LOG in is always performed before
System Reset.
The System Reset routine (micro-program)
is performed for Power-on, System Reset

Select switches and displayed in DR _ P,

key operated (after Check), and for Load
I, U, L.

For LS register Display altering

is suppressed.

1-28

(5/68)

key operated.

IBM CONFIDENTIAL

Cycle Steal Operations

has to be established between Service
Phases in order to avoid Data Overrun when

Cycle Steal Operations can be considered as

different devices request service siITlul-

circuit controlled service phases during which

taneously.

I/O data is directly transferred frOITl ITlain

should be interruptable for the benefit of

storage to the requesting attachITlent or vice

others of a higher priority.

Also, SOITle Service Phas es

versa.
Cycle Steal operations, requested by the
Cycle Steal devices, interrupt

any current

This is accoITlplished by grouping Service
Phases into PrograITl Levels.

Service

ITlicro-instruction for one processing period

Phases in the saITle PrograITl Level cannot

(cycle).

interrupt each other, those in different

Four different Cycle Steal devices

can be attached.

The cy cle steal requests

PrograITl Levels can.

froITl these four devices are served depending
upon a priority sequence.

PrograITl Levels
I/O INTERFERENCE
The CPU proper can ronceptually be con-

•

There are two types of I/O interference:

sidered to consist of eight sub-processors

I/O Service Phases

which share tiITle and circuits aITlong theITl

Cycle Stealing

in a fixed priority scheITle.

These sub-

processors are called PrograITl Levels
(PL).
7.
I/O Service Phases

They are nUITlbered froITl 0 through

The higher nUITlber indicates the higher

priority.

To each PL, a local storage zone

is assigned.

Thus, each PL is controlled by

Service Phases are ITlicro-prograITl routines,

its own IAR.

PL 0

which handle the I/O interference caused by

to the CPU in its processing state, (CPU,

I/O devices with a relative low data trans-

executing ITlachine level instructions).

fer rate.

I/O Service Phases are assigned to PL

An I/O service phase is a part of

(LS zone O) is assigned

the execution phase of a ITlachine language

through to 7

I/O instruction and is

Service Phases will share one PL.

initiated by I/O ser-

(I/O levels).

In general, several

vice request generated in the attachITlents.
I/O Service Phases interrupt the execution

More than one PL ITlay be on at any tiITle

of ITlachine level instructions.

but only one ITlay be active, i. e., executing
ITlicro-instructions by using its associated

Because there are I/O devices covering a

zone of Local Storage.

The PLs being on

wide range of data rates, SOITle priority

but not active are called pending PL's.
2020 FETOM

(5/68)

1-29

IBM CONFIDENTIAL

,.....Sd___-<:.Trap Request LiVles 1 tOT (rom I/O Q1to.ci-)mev,t.s

5et

C"u1 r.,L
I

~--~r---.---~_---r---+'--~----r-~
I
I

t
¥l.¢
(act-; ve

i( Pt. 1 to 7 0((J

A pending PL will become active if all higher

quest lines from the attachments to the

levels are switched off.

CPU, one for each PL (1 to 7.) There

Otherwise, a

presently active PL may become pending

is no trap request line for PL O.

(that is processing in this level stops) when
a higher priority level is switched on.

If coincidence occurs, a trap request over-

rides an attempt to reset a PL by a PLTo control the Program Levels, the CPU

CTRL. Note that a PL can never be reset

contains a seven position PL register. A

by trap-requests.

priority circuit selects the highest active
level out of all which may be on at a given
time (figure 1-25).
PL 0 (CPU level) is active when all PL
register positions are off.

Any PL is switched off by a reset-PL instruction, which is a CTRL micro-instruction with a device address from /01/ to
/07/.

The device address indicates the

PL to be reset.
Program Level Switching

Any PL is switched on by a CTRL with a
device address from /09/ to /OF /.

The

Any PL is switched on by a trap request

three loworder bits of the device address

(I/O request).

define the PL to be switched on.

1-30

(5/68)

There are seven trap re-

IBM CONFIDENTIAL

PrograITl Trapping

such as ITlagnetic tapes and ITlagnetic disk
drives.

If as a consequence of PL switching an-

other PL becoITles active, the CPU selects
another LS zone.

This is called PrograITl

Trapping.

Cycle Stealing consists in sharing

the core memory and part of the local
storage between the I/O device and CPU
control program.

Two LS registers (data

address and field length) are used by a de-

The trap ITlay be upward(higher PL is

vice at a tiITle.

switched on) or downward in priority.
When all service phases for the currently

One ITleITlory cycle is exe-

cuted at the next possible tiITle.

Thus,

Cycle Steal requests have the highest prior-

active PL have been served, the correspon-

ity for ITleITlory utilization and ITlay even

ding trap request latch in the attachITlent

interrupt the cycle sequence of ITlicro-

is turned off by suitable CTRL-instruction.

instructions.

The PL itself is reset by a reset PLCTRL.
Trapping takes place at end of the current
ITlic ro - instruction or at the end of the

CPU DATA FLOW

current 'loop-cycle' of an ALC instruction but ITlay be delayed by intervening
Cycle Steal requests.

•

Thus, excepting

The CPU data flow is shown in FEMDM,
2020 CPU, figure 3-2.

Cycle Stealing, a Trap is never delayed
by ITlore than four cycles after PL-switch-

•

ing occurs.

The CPU data flow handles halfword
data.

LS registers 0 to 7 of any zone, de-selected by trapping, are left unchanged.

The

•

Byte handling is perforITled by cOITlplet-

IAR points to the instruction which would

ing the data byte to a halfword either

have been executed next if no Trap occurs.

by zeros or by a data byte froITl an-

For Traps after branch-type instructions

other source.

the IAR will point to the branch-address.
For ALC instructions interrupted by a

Internal Data ForITlats

Trap, the LAR pOints to the same instruction.

These instructions are re-entrant

pOints after each loop-cycle.

•

The internal data forITlats are shown
in figure 1-26.

Cycle Stealing
Main Storage

Cycle Stealing handles I/O devices with high
data transfer rates (above 5 K bytes/sec)

•

The ITlain storage contains the custoITler's
area as well as the control area.
2020 FETOM

(5/68)

1-31

....

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CPU

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IBM CONFIr

•

The available storage types are SJ 4

nJ'

Storage Address Register (SAR)

and SJ 2.
•

•

The SAR is a halfword register. which

During each core storage cycle one

saves Inain storage addresses to be

read and one write operation is per-

available for read/write tiIne.

forIned (read or write cannot be per-

•

forIned separately).

The addresses in SAR define bytes or
halfwords.

•

A core storage cycle is divided into
eight T-pulses. Four T_pulses for
read and four for write.

•

For byte handling the unit bit (SAR
bit 15) defines the required byte in the
halfword read out or to be stored.

•

A core storage cycle lasts 3.6 microsec (SJ 4) or 2 micro sec (SJ 2).

•

The core storage cycle time defines

•

The SAR is parity checked.

•

The auxiliary storage areas (512 bytes
for each 4 K halfwords) are part of the

the CPU cycle time, however, both
cycles are not aligned.

•
•

Each addressable storage position

•

SJ 4 and SJ 2 are available as 4 K and

Aux storage addresses are specified
by the SAR bits 0 and 1 on (byte ad-

contains one halfword.

8 K halfword arrays (8 K or 16 K bytes).

•

control area.

(See Figure 1-23).

dresses above 48 K ).

•

For Inain storages sInaller than 48 K
bytes. there is an addressing gap between the highest storage address and

The InaxiInuIn storage size is 24 K

the first Aux storage address (/COOO/).

halfwords (48 K bytes custoIner's and
control area; three arrays on three
boards).

•

Addressing of not available storage
positions {gap positions or not available Aux storage positions up to 64 K

•

The third board is defined as exten-

cause

'read out of blanks'

sion (additional circuits for sensed
data and inhibit).
•

For' reading of blanks'

the parity

bits are forced on (in SDR) to provide
a valid halfwords containing zeros.

2020 FETOM

(5/68)

1-33

IBM CO; DENTIAL

•

For CPU LOG in, main storage addresses

•

checked.

are forced by circuits.

•

SAR can be displayed on the CE console.

The halfword to be stored is parity

•

During CPU LOG in, the parity check
circuit is used to test the LOG informations at read time.

Storage Data Register (SDR)

•

The SDR is a halfword register set

Operation Register (OP REG)

by the main storage sense bits 0 to 17.

•

During processing period 0, the

Sense bits 0 to 15 are the data bits,

REG accepts the SDR halfword (micro-

while bits 16 and 17 are the parity

instruction) .

bits PO

(highorder byte) and PI (low-

order byte), respectively.

•

The micro-instruction in

op REG

remains during its execution until

•

The sense bits occur during read time

the next instruction is read in.

of the core storage cycle.
•

•

For I/O micro-instructions, the low-

The SDR provides data to the CPU

order byte containing the device address

data flow, to the Cycle Steal data bus

activates the I/O Address Bus.

(bytes or halfwords), and to the Inhibit
Switch (bytes or halfwords for regeneration during write time).

•

The OP REG output feeds the Operation
Control Unit and the LS addressing
circuits (register selection, X-ad-

•

SDR can be displayed on the CE console.

dresses).

•
Inhibit Switch

•

The

op REG can be displayed on the

CE console.

The Inhibit switch selects sources which
provide data (bytes or halfwords) to be

Operation Control Unit (OCU)

stored.
•

•
1-34

The OC U is an imaginary unit con-

Data to be stored is provided by the

sidered to generate the CPU control

SDR (regeneration), ALU, or by the

signals and to provide all necessary

Cycle Steal data bus.

timings.

(5/68)

IBM CONFIf")FN"

•

Some control conditions can be dis-

•

Each zone contains eight registers
(0 to 7) defined by X-address.

played on the CE console (OCU 1 and

2 ).
•

LS register 7 in each zone contains
the Instruction Address Register

Program Level Control (PL Control)

(IAR) which provides the address of the
micro-instruction performed as the

•

The PL Control consists of PL Reg,

next.

Priority Decision, and Current PL
Reg.

•

Writing into LS is controlled by the
LS Write signal, while reading is

•

The PL control is activated by Trap

controlled by the sense amplifier

request from the I/O attachments or by

gate

(SA gate).

CTRL micro-instructions.
•

•

The PL control defines the current work

LS writing and reading is performed
within one T -pulse period.

zone in the Local Store (Y -addresses).

•

The PL Reg can be displayed on the
CE console (OCU 2).

Modify Address - Register
•

•

The Local Store Address Check (LSA

(MAR)

The MAR is a halfword register which
is set by LS data only.

check) tests that always one X- and
Y - address is active at a time.

•

The LS data may be addresses or field
lengths which have to be updated by
the Modifier.

Local Store (LS)
•

•

The LS consists of 64 halfword re-

The MAR can be displayed on the CE
console.

gisters separately addressable.
•

•

Reading of a LS register does not
destroy its content.

The MAR output feeds the Modifier
as well as test circuits which investigates the MAR contents for being
zero, minus, plus, or being an invalid

•

The LS registers are arranged in eight

address (Address Check, outside cust-

zones (0 to 7) specified by the PL con-

orner's area).

trol (Y-addresses 0 to 7).
2020 FETOM

(5/68)

1-35

Modifier

•

TDR, FDR, and the ALU result can be
displayed on the CE console.

•

The Modifier is capable of incrementing
or decrementing halfwords by one or two.

•

Apart from being incremented or
decremented, data can flow through the

Shift Unit (SU)

•

groups able to modify the To-operand:

Modifier unchanged.

•

Eight Shift (shift left/right by 8,
byte shift)

The Modifier output is parity checked.

The output parity is predicted depen-

•

Shift Unit (shift left/right by 2 or 4)

Suppress Unit

TDR halfwords are fed through the

shifted (byte exchange).

the operation to be performed.

The Modifier result can be placed

Eight Shift either direct or cross-

ding upon the input parity (MAR) and

•

The SU is divided into three functional

•

Both Eight Shift circuit operations are
controlled by signals.

back into LS only.

•

The Eight Shift sets a TDR byte to zero
(parity is corrected) when no control
signal for the corresponding byte is

Logical Unit

generated.
•

The Logical Unit is a triple combination
consisting of Shift Unit (SU), Invert

•

The resulting Eight Shift halfword
(INTernal SU Bits) are parity checked

Switch and Arithmetic-Logic Unit (ALU).

(SU Check).
•

The ALU connects two halfword operands,
provided by SU and Invert Switch either

•

from main storage (SDR- TDR-Eight

arithmetically (ADD) or logically (AND,

Shift).

OR, OE).

•

1-36

To-Data Register (TDR) and From-

The qU check tests the data read out

•

The Loworder byte after Eight Shift

Data Register (FDR) save the input

is set onto the I/O Data Bus to be used

operands to be available until the ALU

as control data for CTRL micro-in-

result is stored.

structions (CPU data to attachments).

(5/68)

IBM CONFIDENTIAL

•

The Shift Unit handles the INT SU
halfword either for shifting left/

•

Si:multaneous true and invert control
forces zeros.

right by 2 or 4 bits or for no shifting.
•

•

No shift left/right and not no shift con-

Si:multaneous no true and no invert
control forces ones.

trol forces the affected byte to zero.
•

•

The halfword at Invert Switch out is

The Shift Unit contains circuits for

displayed in DR's - E, S, T, Ron

nor:malizing packed deci:mal signs

custo:mer console.

according to ASCII or EBCDI code
(as selected).

•

The Shift Unit provides test circuits,

Arith:metic-Logic Unit (ALU)

which investigate packed deci:mal data

•

for being valid.

SU and Invert Switch halfwords are
used as ALU input operands

•

The Suppress Unit suppresses the
SU halfword partially

(in defined

•

bit groups) or co:mpletely.

The ALU connects the input operands
either by ADD, AND, OR, or Exclusive OR (OE).

•

The output of the Suppress Unit, which
provides the :modified TDR halfword
to the ALU, is displayed in DR's P, I,

•

ADD, AND, and OR functions are controlled by ALU gates, while the OE

U, L on custo:mer console.

function is always perfor:med when no
ALU gate is active.

Invert Switch

•

The ALU provides Six Correction circuits used to generate valid packed
deci:mal digits (ALU loworder byte

•

The Invert Switch trans:mits the FDR

only).

halfword either true or inverted

•

The two bytes can be controlled
separately.

•

A carry latch recognizes the carry out
of the highorder AL U byte (halfword
operations) or carry out of the loworder
byte (byte operations).

•

The true and invert functions are controlled by signals.

2020 FETOM

(5/68)

1-37

IBM CONFIDENTIAL

•

The ALU result condition sets four
Condition Code latches respectively

•

The Address and Data Bus are line
loops which leave CPU (device ad-

(micro-program condition code).

dresses SENS or CTRL from OP REG
loworder byte; CTRL data from low-

•
•

•

The ALU output is parity checked

order byte after Eight Shift) and enter

(ALU Check).

CPU by setting into FDR.

The ALU parity (highorder and low-

•

order byte) is predicted depending

the corresponding attachment by data

upon the parity of the input operands

provided by a source which is selec-

and the performed ALU function.

ted according to the device address.

The ALU result can be saved in LS,
used for addressing (branch), or

•

Either the complete result halfword,

•

or the loworder byte is stored.

•

For storing a byte only, the Inhibit

'For CPU internal SENS' s the sensed
information is directly set into FDR.

stored into main storage.

•

For SENS, the Data Bus is activated in

CPU SENS data are either of byte or
halfword format.

•

Switch halfword is completed by a

The Data Bus entry is parity checked
(Bus Check).

SDR byte (regeneration).

CPU Cycle Steal Control
I/O Bus Out and In
•

•

The CPU Cycle Steal Control is acti-

The CPU communicates with the I/O

vated by four Cycle Steal requests

attachments via the I/O Bus only.

generated in the Cycle Steal devices
(part of the attachments).

•

The I/O Bus consists of an Address
Bus and a Data Bus.

•

All control information necessary to
execute cycle stealing is provided

•

Besides Address and Data Bus, able

by the Cycle Steal devices.

to transport one byte at a time, a
small number of control bus lines
is provided.

1-38

(5/68)

•

Status information of the executed
cycle steal operations returns to the

IBM

•

CONI='I")I=~'T' ~ ,

Cycle Steal devices (e. g.• a CS Inhibit Check does not stop CPU. but
the information is saved in the CS
device).

•

Cycle Stealing stops all current CPU
operations for one cycle.

•

The CPU Cycle Steal Controls data
transfer (byte or hal£word) from or to
CPU via the Cycle Steal (CS) Data Bus.

2020 FETOM

(5/68)

1-39

IBM CONFIDENTIAL
CHAPTER 2.

CPU BASIC TIMING

FUNCTIONAL UNITS

storage type, SJ2 or SJ4, the oscillator frequency
is either 4.000 MHz (SJ2) or 2.222 MHz (SJ4);

•

The CPU Basic Timing circuits and a

thus, an oscillating period lasts either 250 nano-

corresponding timing chart are shown

seconds (SJ2) or 450 nanoseconds (SJ 4).

in FEMDM, 2020 CPU, figures 4-30

oscillator circuits contain two potentiometers which

and 4-31.

allow Pulse A and B adjustments (Figure 2-1).

The

Potentiometer 1 adjusts the distance between the
raising slopes of Pulse A and Pulse B.

Potentio-

meter 2 adjusts the duration of Pulse A and B.
OSCILLATOR

The

+ Oscillate

pulses control the Storage

Select signals (SJ2 only) and the latch ring

•

The oscillator provides the pulses A

of the four Binary Latches which provide

and B and the Oscillate pulse.

the I/O Clock Pulses 1 and 2.
To generate the Storage Select signal at

•

Depending upon the used core storage

the correct time (within T2 or T6), the

type, SJ2 or SJ4, the oscillator frequen-

+ Oscillate

cy is either 4 or 2.2 MHz.

late) by a delay line which is adjustable

pulse is delayed (delayed Oscil-

from 0 to 125 nanoseconds by changing tabs.

•

Pulses A and B are adjustable.

Pulse A and Pulse B control several internal CPU functions, which are executed

•

The Oscillate pulse controls the gener/

within one T-pulse period.

ation of the two I/O Clock pulses (1,2)
and the Storage select signal.

•

Storage Select is us ed for SJ2 only.

The oscillator consists of a crystal oscill-

SHORT TIME CLOCK

ator and pulse former stages which provide
three different pulses at the oscillator output. These pulses, Pulse A, Pulse Band

•

The Short Time Clock provides the
timing pulses Tlthrough T8

Oscillate, define the basic CPU operating

•

timing.

This clock is continuously running, con-

The crystal oscillator produces pulses of a con-

trolled by pulses A and B, when System

stant frequency.

power is applied.

Depending upon the used core

2020 FETOM

(5/68)

2-1

N
I

SJIf '" .2..ll~MH1.

EJ@l
Pot 1

~
Pot~

...r

h
fJ

+ PULSE Ar

+ PULSE

I
T

'-', ,.:,:-

T'D
If-JtS"rcc

25¢nsec

I
r
~:~~:=:::~-:'--T
.
--1 ________ _
L'

~~;;:)(~~;~
"

:,.f-"_ __

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.. ,

.-J

~~--------~L_

~----.....,
..

________~r-

____~
FI=~-~~=~~~--~--------:
----------- --- --- ...-

........J _______ _

·1

.1~..,scc:

+ Pulse A

c1e14~

I--:....---~

()

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19l ns«.

-n

~fbt2)

:125:-~
~

I ----....

115n....
_ - - - - rr.-l~~lI'Isec--J
(Potl)

+ Pl.Ilse.

Pt..lseA

+ htlse B
+ Osc. i lIate.

"'sec

+Clod< AdvQ\"Ice

5]2.

¢-lU_

OSIILLAToR CARl>

- sIlt

j -t-OSCiL.LATE

'---,

+ Osc:ill~te

...r\

T])

+Pulse A

om
Z

'f!!

Pulse.

SJ.2. J 4.0~¢NHz.

SJ4

2.222. MH~

IBM ('I)NF1DENT1AL

•

For SJ2 the Clock Advance Pulse A is

These periods are:

adjustable to move pulse B as far as

Read Cycle SJ4

possible to the end of a T-pulse period.

= T6

- Tl

Write Cycle SJ4 = T2 - T5

The Short Time Clock consists of the Short

CS LS Select Time

Time Latches and the decoder circuits. The

Time T8 - T3

decoder circuits provide eight timing pulses

Time T4 - T7

T5 - T2

numbered from 1 to 8 (Tl to T8).
The pulses Tl to T8 are generated depending upon the switching sequence (figure

The delta Short Time Latches 1, 2 and 3 switch in

2-2) of the Short Time Latches 1, 2 and 3.

the same sequence as the Short Time Latches.

These latches are advanced by each Clock

Since the delta latches are advanced by the Pulse

Advance Pulse A. The output

B, their switching is delayed for a half T-pulse

of the latches

are also used to define processing periods

period (half of an oscillator period). This allows

which are longer than one single T-pulse.

generation of the delta T8 pulse and especially

Clock Advu\l1ce.

Pu lse A
5J4

s~o~t

off

l.-

E
I

.'if

T
T
I

•

R
E

1--n

tiTS'

P-

E
A
D

T2.

T3
T4

U.T~

S
l-

sJ2,.

Time(.atclt\es

W
R
I

P-

T
E

~~
FL2.

NaHlloy~otF/..3

2020 FETOM

(5/68)

2-3

IBM CONFIDENTIAL

for SJ2 shifting of the Read and Write Cycle for a
half of aT-pulse.

The source of the Clock Advance Pulse
A (defines the start of the T-pulses) is
different for SJ2 and SJ4.

For SJ4 the

Pulse A is di rectly used as Clock Advance pulse.

For SJ2 the Clock Advance

Pulse A is generated by the delayed Pulse
B.

The delay is adjustable from 0 to 125
nanoseconds.

If the rnaximurn delay is

selected,the delayed Pulse B occurs at
the same tirne as Pulse A.

2-4

(5/68)

IBM CONFIDENTIAL

RUN

CONTROL

I/O operation even if the CPU has been
stopped before.

The Initial Control Program Load (rCPL,

•

The Run Control contains all circuits

circuit control reading of the control

necessary to start or stop the CPU,

program loader card) is performed by a

as well as the circuits to generate

sequence of start-stop operations (restarts

all reset signals.

by Trap requests 5).

The CPU is started when one of the
following keys is operated
Power On key

CPU START

Start key

The CPU operates when the delta Process

System Reset key

latch and the Process latch are turned on.

Load key

Thus, CPU start can be considered as a
switching sequence (figure 2- 3) of several

The Run Control circuits control CPU start and
CPU stop.

Besides the start-stop control, the

start latches which results in turning on the
two process latches.

circuits provide the necessary reset signals. Run
Control operations are initiated by operating the
keys on the customer console or on the remote
control box which is connected to the socket on the
CPU Start by Power On

CE console.

The remote control box attached

blocks the function of the console start key (Block
•

Normal Start). The CPU is started by:

Power On starts CPU to perform the system
reset routine.

DUring power on the logical voltages reach their
1.

Power On (to perform System Reset).

Operating the Start Key (remote control box or console; Normal Start).

operating levels at different times. This causes
undefined activating of CPU control components
(latches, registers). To ensure a defined CPU

Operating the System Reset Key.

start Situation, the System Reset Routine is per-

Operating the Load Key.

formed.

However, performing the System Reset

Routine (micro-program) requires the CPU to be
When the CP U is stopped while any I/O

started.

device is still operating, the CPU is restarted either by UNEQUAL PL (Trap re-

Figure 4-41 in the FEMDM is a timing

quest) or by ANY

chart of the run control action during

CS REQUEST.

This

restarting allows com.pletion of the current

power on.
2020 FETOM

(5/68)

2-5

IV
I

'"
1-<:E5TART

CPU

operates

0;
VlO

..
< StopA",,:!
Cov."j,f.OIV---.....

L-._ _ _ _ _ _ _

yes

8z
o"

m
Z
~
j>

IBM CONFIDENTIAL
CPU Start by

Operatin~

Start Key

lock Latch. Thus, the start latch cannot
be turned off.

•

Operating the Start key starts CPU

The continuous operation ends when the

to execute the micro-program or

Start key is released.

manual operations.
When the Single Micro-Instruction switch
Operating the Start key on either the

is on, only one Alter or Display operation

customer console or the remote control

is performed.

box initiates the action shown in Figure

For CE Single Cycle operations the CPU

4-42 in the FEMDM.

stops after each of the four cycles.

CPU Start by Operating the Control
Program Load Key
Continuously Alter or Display

•

Operating the CPL key initiates ICPL.

•

ICPL controls reading of the control

Storage or local Store Alter or Display is repeated as long as the start
key is operated when the Single Cycle

program loader card by circuits.

Switch and the Single Micro-Instruction switch are both turned off(normal).

•

After the loader card has been read
the further control program is loaded

Storage or CE Local Store Alter or Display are manual

operations

under control of the micro-program.

which are

performed by four cycles (cycles 0 to 3).

CPU operations, except manual operations

These operations are initiated by pressing

(MANOP's) , are performed under control

the Start Key after the mode switch on

of the micro-program.

the customer's console and the CE mode

program is stored in the Main storage,only

switch on the CE console have been set

circuit controlled CPU operations like

accordingly.

MANOP's can be performed.

The start sequence is performed as des-

When the no micro-

One of these

circuit controlled operations is Initial Con-

cribed in

CPU start by Operating

trol Program Load (ICPL). The ICPL oper-

Start Key.

ation performs all necessary controls to

The stop condition which deactivates the

read one punched card by an I/O device

Hold Run Condition occurs at Alter or

which is specified by set up CE Address

Display cycle 3 (figure 2-4). However,

switches.

when the Start Key is continuously pressed,

The ICPL operation consists of four cyc-

the Allow Continuous Alter or Display con-

les (0 to 3).

dition occurs, which resets the Start Inter-

formed for each card column being read

The cycles 2 and 3 are per-

2020 FETOM

(5/68)

2-7

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IBM CONFIDENTIAL

Request Line 5 active).

cycles (0 to 3) to be performed as soon

For each Trap Request 5, the sense and

as the delta Process and Process latch

store cycles (cycles 2 and 3) are executed

are turned on.

until the field length, updated during each

start address of the System Reset Routine

character transfer, is decreased below

/C002/ is set by circuits into IAR of the

zero (Decrement Carry 0).

Local Store zone 7.

Then the

During LOG cycle 3 the

After LOG cycle 3

End Op Latch is turned on (cycle 3) which

the LOG latch turns off and during the follow-

activates the Hold Run Condition con-

ing delta cycle and cycle 0 the first micro-

tinuouslyand causes the Long Time Clock

instruction of the System Reset Routine

to advance to delta cycle and cycle 0

is read out from Main Storage. At the

The active End Op Latch indicates that the

end of the System Reset Routine the Load

circuit controlled ICPL operation is ter-

Latch is checked for being on by a SENSE

minated and the CPU starts to execute

instruction.

the micro-program placed into Main

micro-program to branch to the load

storage.

routine while load latch off (System Reset)

Load latch on causes the

causes a CPU stop by a HALT microinstruction.

CPU Start by Operating the System Reset
Key or the Load Key
CPU STOPS
•

System Reset and Load start with the
System Reset Routine.

The CPU stops when the delta Process
latch and the Process latch are turned off

•

Operating the Load key turns on the

by dropping the Hold Run Condition.

Load latch.

An overall picture of all possible CPU
stop conditions is given in figure 2.7.

•

For System Reset the CPU stops

Details about stop circuits are shown

after the System Reset Routine while

in figure 4.40 in the FEMDM.

the active Load Latch forces a branch
to the Load routine.

CPU start by operating the System Reset

Common CPU Stops

or the Load Key on the customer console
is performed similar.

Common Stops are those, which can occur

Operating one of the keys initiates the

during customer t s use of the system as

action shown in figure 4.45 in the FEMDM.

well as during CE operations.

'The active LOG latch forces the four LOG

The common stops are divided in normal

2-12

(5/68)

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ICPL,C:t(e2., o.V\~ I/o Erv-oV",I.Vt.eVl.

1/\(9+

.
'lA;ho.l Load Loop $1,J.Or V10t ~roccss Clnoc.k Ovet"y;cle SI.V.OVl,

o
~E
STOPS

""L

~to\'"o..~e. Test
Check

...'"
/

S+cnQ.'1e.

feSt,

EV)d

t-u.I/\.2

0..",0/

llAvell'r 'Pc.~; h:r Sw.

stop I.

yes

RESET PIALS

RESET cI.OCK.

RESE:r PULSE

MANUAL RESET CLOCK

s top

I--_,,",

SI-op

5YSTEM RESET

Pow", 0 " ke..:J.-_-+"cu.."",'-'-'-"f"-'-J..i.~"'+:...u;.,;.u;-,"-"-+,-,,-,-,-.:.:;.;,;.,,"-!

St",.! ke
~Pi. he"

~~'ie~~~~~t£~~_~~~~~~~L4'_______+-____~

~sl k e~_~ _ _.-Lw..L.-L-'-'-.J-<.-U-<'----~

...
I

.....,

rePL
Reser

l1uLSE.

l.OG
FL

foyce CPU LOG

IBM tONFI~ENTJAl
CORE STORAGE

One

C
I
I

i WRITE+
!
Current
....-.:-I::;.m~-+-~___I-_...:;_-I-_-'-_(Plus

"'READ

I
I

•

The core storage unit, 4K or SK, is

Current
(Minus
Direction)

+Im

Direction)

selfcontained on a single SLT board.

•

There are two core storage units
available:

•
•

4usec and 2usec.

MDM page SDOII is a block diagram
of the 4usec core storage.

Figure 2-t Hysteresis Curve of Magnetic Core

flux in a negative direction, and at point D
a residual flux in the positive direction.
These two directions can be arbitrarily

MDM page SAOII is a block diagram
as signed as binary' zero' and binary' one' ,
of the 2usec core storage.
respectively.
1m is the amount of current necessary to change
the state of the core. Plus 1m i. the amount

MAGNETIC CORE THEORY

of current required to 'flip' the core from

A magnetic core is a small. doughnut- shaped

binary zero to binary one. Minus 1m is the

ring that is uniformly constructed of ferrite

same amount of current in the opposite

particles bonded together by a ceramic mater-

direction required to flip/the core from

ial. The ferrite particles have good magnetic

binary one to binary zero.

properties and the core has a high retentivity

On the hysteresis curve, it can be observed

of the magnetic flux lines after the magnetiz-

that a magnetizing current of plus 1m will

ing force is removed. It is this property of

change the magnetism of the core from

retentivity that makes a magnetic core use-

point A, a binary zero, to a value in the

ful as a storage device.

positive direction at point C. When the

The operation of a magnetic core can best

current is removed, the total amount of

be described by reference to its hysteresis

magnetization drops back to point D (binary

curve, Figure 2_". This curve is a plot of

one). If, instead of the full magnetizing

the relationship between a magnetizing current

current 1m ,a current of Im/2 were applied,

and the flux dens,ity of the core.

the flux would change only-the small amount

A magnetic core is capable of maintaining

from point A to point B on the curve, and

indefinitely one of two stable magnetic states,

when the current returned to zero, the flux

either at point A or at point D on the hyster-

would return to its original value.

esis curve. Because the core has two stable

A reverse current, minus 1m , develops flux

states, it can be used asa binary storage

of opposite polarity and, if the core is in

device. At point A the core has a residual

the 'one' state, changes the magnetic state

2-18

(5/68)

,aM C.ONADENTIAl
of core from point D to point F. When the
driving current is removed, the magnetization drops back to point A {binary zero}.

Writing Into Core
Write Select and Inhibit

The magnetic properties of the core make
it ideally suited for use in a storage matrix
employing X and Y drive lines. Each core
of the matrix is threaded by three windings
{Figure 2_it}. One winding is an X drive
line .that carries a current 1m/2 and one
winding is a Y drive line that carries a current
1m /2 in the same direction. A coincidence
of current in these two windings occurs at
one core storage position {18 cores} thereby
I

selectingl that word.

The third winding is the inhibit/sense winding.
When writing into a core storage position,
each core that is not to receive a lone l bit
is inhibited by a current 1m/2 flowing in its
inhibit/sense winding in a direction opposite
that flowing in the X and Y drive lines. The
magnetic field produced by the inhibit/sense

•

winding effectively cancels half the field produced by the X and Y drive lines. The re-

Combined Functions

Figure 2-'" Core Storage Write and Read (4-usec Storage)

sulting magnetic field is insufficient to flip

used instead to detect the change in state of

the core to the lone l state.

the magnetic flux. The sensed bits are set
into the corresponding positions of the B
Reading Out of Core

When information is to be read out of a core

storage position, the currents 1m /2 in the X
and Y windings are reversed {Figure 2-1IIt}.
Each core that flips from a 'one' to a 'zero'

ADDRESSING

state induces a pulse into its inhibit/sense

•

One X drive line and

OIleY

drive line

winding. The inhibit/sense winding at each

are activated by selecting both ends

core does not carry inhibit current and is

of the lines.
2020 FETOM

(5/68)

2-19

JBM CONFIDENTIAL

•

Each active drive line carries half-

array, one line in each group of eight is

select current.

activated by a decode of Address Register
bits 6, 7, and 8. Thus, a single X line is

•

The two drive lines intersect at one

activated and carries half-select current .

core in each bit plane {18 cores} to

At side B, the 128 Y lines which run through

provide full select current at that

all planes, are divided into eight groups of

one halfword.

16 lines each. One group of 16 lines is activated by a decode of Address Register bits

Eight-K Addressing

9,10, and 11. At sideD, actually the other

The magnetic cores are arranged in ma-

end of the array, one line in each group of

trices of 128 x 64 cores, called planes.

16 is activated by a decode of Address Re-

(Each plane is actually 128 x 68, pro-

gister bits 12, 13, 14 and 15. A single Y

viding 512 po s itions of auxiliary storage

line is thereby activated and carries half-

that are not program addressable and are

select current.

described in another section.) The 8K

In each plane, the core at the intersection

array consists of 18 of these planes with

of the active X and Y drive lines receiw,s

each plane assigned to one bit position of

full-current and is the only core in the

a core storage halfword. Corresponding

plane that is selected.

core positions in each plane are addressed
simultaneously by the X and Y drive lines
to select one 18-bit halfword. Since there

Four -K Addressing

are 8192 cores in each plane, the 8K array

One plane of the four-usee core storage 4K array

has a capacity of 8192 halfwords.

is shown in MDM page SD042.

The 128 x 64 matrix in MDM page SD041

for the two-usee core storage is shown in MDM

represents one plane of the four-usec core

page SA042.

storage, 8K array. Eight-K addressing for

same area of the SLT board.

the two-usee core storage is shown in MDM

used in the 4K array are identical to those used

page SA 041. It differs from the four-usec

in the 8K array but only nine planes are us"ed.

core storage only in the drive circuits which

addressing purposes, each 128 x 64 plane is divi-

are described in another section. The one

ded into two 128 x 32 half-planes.

core that is shown is selected by the address

haIf-planes is assigned to one bit position of the

represented by Address Register bits 3 to

core storage word.

15.

Since there are 4,096 cores in each halfplane,

At side A, the 64 X drive lines, which run

the 4K array has a capacity of 4,096 half-

through all planes, are divided into eight

words. (An auxiliary storage of 256 half-

groups of eight lines each. One group is

words is actually part of the 4K array: it

activated by a decode of Address Register

is described in another section. ) The 32 X

bits 3, 4, and 5. At the other end of the

drive lines are divided into four groups of

2-20

(5/68)

Four-K addressing

The 4K and 8K arrays occupy the
The core planes

For

Each of the 18

IBM CONFIDENTIAL

eight lines each (one-half as many groups

address-register-bit-l and - 2 lines. These

as in the 8K array). The X lines run through

lines connect from the SAR Power output

the nine B halfplanes, then loop back through
the nine D halfplanes. One group is acti -

to the core storage circuits through wired
.L2.
logic. Figure 2-8 shows the combinations

vated by a decode of Address Register bits

required to activate each module.

4 and 5 (bit 3 is not used with 4K core storage).
At the other end of the X lines, one line in
each group is activated by a decode of Address
Register bits 6, 7, and 8. A single X line is

ADDRESSING - AUXILIARY STORAGE

thereby activated and carries half-select
current. The 128 Y drive lines are divided

•

Within 2020 CPU's with a serial number

50,000 and above the auxiliary storage

into eight groups of 16 lines each, as in the

areas are part of the control storage.

8K array, and run through all nine planes.
One group of 16 lines is activated by a decode

Auxiliary storage is selected by the auxiliary

of Address Register bits 9, 10, and 11. At

read-driver and auxiliary-read-gate circuits.

the other end of the array, one line in each

These two circuits are activated by the address-

group of 16 is activated by a decode of

Address Register.bits 12, 13, 14, and IS.

by SAR Power depending upon SAR bit 0

This active Y line intersects the active X

and I active.

line at two cores in each plane; therefore,
nine planes provide 18 bits for each of

4096 halfwords.
CORE STORAGE ARRAYS

MODULE SELECTION
•

•

One module (one SLT board) of core

Core storage arrays are available in
two sizes, 4096 (4K) halfwords and

storage can contain a 4096 - or 8192-

8192 (8K) halfwords.

core array.

•

Each halfword consists of 18 bits.

•

Both arrays consist of core planes

Address register bit I and bit 2 lines
select the module.

in a 168 x 68 matrix (168 x 64 prog-

•

Module selection lines are connected
J,J.
through wired-logic (Figure 2-.).

The circuits that activate the core storage

ram-addressable).

•

The 8K array contains 18 physical

clock and timing circuit, and therefore select

planes, each of which contains one

the unit, require a specific combination of

bit_position for each halfword.
2020 FETOM

(5/68)

2-21

+ Read

(Modul. SeI.ctTon)

'"'"

XW,ite

Gate

+ R.ad Cycl.
+ Add< Reg Bit 2

Time

_ long Time
X Reoe!
Lr---=------r-......,f.-......J~~.!I----- Driver Time

-8

YWrite
Gote Time
Y Reod
Driver Time

- long Time

- Addr Reg alt 2

+5_
Select

+ WrIte

----;=+=++=====:j::==:ill!ill

+ long Time

+Wrtfe Cy
... long Time

Cycl.

X Read Gate Time
X Reod Source Time

... StCllOg8 U..e
+A4K)

in an 8K array.

•

X read gates and drivers are conditioned at TO (CPU T6) time for a
duration of approximately one usec.

Inhibit current flow is from ground, through
2048 cores, through the inhibit driver that
is conditioned, to -V Inhibit (V z).

V z is

•

X write gates and drivers are con-

a temperature responsive voltage that ranges

ditioned at T4 (CPU T2) time for a

from -9 to -12 volts.

duration of approximately one usec.

•
Sense Amplifier
As in the four-usec storage, the two-usec

The conditioning of Y read and write
gates and drivers is delayed to allow
X drive line noise to subside.

storage sense amplifier has a differential
input from the two ends of the inhibit/sense

Four-usee storage

timi~g-pulse

geh-

eration is initiated by the transition
line for 4096 cores. The center point of this
of the CPU read/write cycle.
line connects to the corresponding inhibit
driver.

J.'1

Figure

2-"

represents the four-usec storage

'clock' and timing circuits. The CPU provides
The first stage collectors contain a trans_
former circuit that eliminates any dc unbalance to provide an equal detectionthreshold for both polarities of signal.
This stage does not require the emitter
strobe that the four-usec s:ense amplifier
requires. The 0.8 volts at the emitter of the
second stage keeps the first stage out of
saturation.

the following signals to1the storage timing
circuits:

read cycle, ~rite cycle, storage

select, and the Address Register 3 line.
The following timing pulses are generated
by the' clock' circuit:

long time, short

time, and strobe. Combinations of the CPU
signals and the generated timing pulses provide read and write gate and driver control,
strobe pulses for less than and greater than

The sense - strobe pulse gates the output

4K, emitter strobe pulse, and inhibit pulses

of the second stage to the final stage. A

for less than and greater than 4K.

negative pulse output of the final stage
results when a 'one' bit pulse is conducted

Note in the timing chart (MOM SO 031) that

from the array to the sense amplifier

Y write current and Y read current rise

input.

after X read current and X write current.

2020 FETOM

(5/68)

2-33

N
I

"'"

Write Cycle

Read Cycle

Not M Re

Strobe "" 4K

0;
'0\

.2;

M Reg 03

Strobe" 4K

Write Cycle
Long Time

fnhibit Time < 4K

Inhibit Time > 4K

long Time
Storage Use

Emitter Strobe

Storage Use
Write Cycle

Not M Reg 03
M Reg

CPU 1i~
~fo.,.... f':! Ti;"'c.

X Write Driver Control

long Time

---- b

'Ii rJ.
T2

Tit
1'6

x Write Gate Control

IT,
TO

Read Cycle

X Reod Driver Control

-.J

Read Cyde

...,

Write Cycle

X Reod Sink
X Write Sink

:!l

Sl>:>rt Time

Write Cycle
Short Time

X R.od Current

--1

Y Read Current

Y Write Driver Control

Y Write Gate Control

X W.lt& Cu",,"1
Y Write Current

Inhibit Time

Figure

2~
J.~

'LR@ d D1J.1tt C~n!ffiJ

,---,

---.II

Strobe

0
Z

--1

l.ong Time

~
()

Four-Microsecond Core Storage Clock

Y Read Sink

Y Write Sink

0
m
Z

....

»
r-

IBM CONFJDENtlAL
The delay of the Y currents minimizes the

When read cycle and write cycle change levels

effect of excess noise at the rise of the X

(at TO and T4 time), the input points reflect

current pulse. This noise is caused by the

the respective levels for one usec then ba-

discharge of array capacitance.

lance again. The same effect is evident at
the taps (points 3 and 4) except for a shorter duration.

Four - usec Storage Clock
•

A time delay' clock' circuit develops
the necessary timing pulses for addressing, reading from, and writing
into core storage.

Timing - Two-usec Storage

•

MDM page SA 031 shows the timing
pulses for the two-usee storage .

•

Long time: a time delay circuit
provides a one usec pulse at TO (CPU

•

shows the two-usec

circuits.

write cycle).

Short time: a latch provides a pulse

•

approximately 750 nsec.

and ends with the fall of long time.

Strobe: a single shot, activated by

X read gates and drivers are con-

ditioned at TO (CPU T6) time for

that begins after the rise of long time

•

.1.

2-l~

storage' clock' and pulse generation

T6, read cycle) and at T4 (CPU T2,

•

Figure

•

X write gates and drivers are con-

ditioned at T4 (CPU T2) time for

short time, provides a pulse that is

approximately 750 nsec.

ANDed with read cycle and an address
line.
•
•

Y read drivers and write gates are
conditioned at the same time as the

Inhibit time: long time and write

X drivers and gates.

cycle are ANDed to develop inhibit
time.

It
Time Delay CircWt (Figure 2-_). Read

•

The conditioning of Y read gates and

cycle and write cycle are connected to

write drivers is delayed 100 nsec

opposite ends of a one usee delay line. The

after the X drivers and gates to allow

low resistance of the delay line causes the

X drive line noise to subside.

levels at the inputs (points 1 and 2) to balance. For example, if read cycle is 0 volts
and write cycle is +3 volts, points 1 and 2
balance at +1. 5 volts.

The two-usec

clock' consists of a time delay

circuit three latches, and two single-shots.
The timing pulse generation is initiated

2020 FETOM

(5/68)

2-35

IBM CONFlDE"NTfAL

Read Cycle

----~~Rr_~~~~

~+,...._____________-.:;:S~et'----I

. -Set

Time

r---------------~--Lo-t~ch~~

Short Time

-OR I--~

Delay

flsec.

Write Cycle

R 1-_+-__-+_..=;.__--1

Long Time
Storage Use

.ReadCy~

O.Ov---

Write Cycle
+3.0v---·-1

+1.5v

+3.0v

o.~

0
L

IL-___

Long Time

Short Time

Figure

2-*"

J.8

-.J

Time Delay Circuit, Four-Microsecond Storage Clock

by the storage select pulse from the CPU.

input of a time delay circuit for the following;

Storage-select, which is a IOO-nsec pulse

the IOO-nsec delayed output turns on the

at TO and T4 or XO and X4, turns on the

short-time latch, the 600-nsec output turns

long-tinle latch and the inhibit-time latch.

off long-time and short-time, and the 650-

Storage-select is also connected to the

nsee output turns off inhibit - time.

2-36

(5/68)

IBM CONFIDENTIAL
The timing chart shows theoretical and ac-

chart. Inhibit-timing is ANDed with the

tual timing for each signal. It shows long time

data lines and address-register-bit_3 or

corning up soon after TO time, falling at the

not-address-register_bit_3 (not .shown in

7S0-nsec point, rising again soon after T4

the diagram) to activate the inhibit drivers

time, and falling 7S0 nsec later. The inhibit-

for less than and greater thiiln 4K.

time latch is turned on at the same time
that long-time is but the timing shown is
inhibit-timing, after it has been ANDed

STORAGE ADDRESS REGISTER

with write cycle.
Short-time rises 100 nsec after long-time

•

for Read and Write.

and falls at the same '.ime. Strobe is a 330nsec pulse generated by two single-shots
that are started by short-time.
Long-time and short-time are ANDed, in

The SAR saves Main storage addresses

•
•

The addresses are of halfword formats
Addresses are provided either by LS or
ALU output.

various combinations, with read-cycle and
The Storage Address Register (SAR, Fig.
write-cycle to produce X and Y gate/driver
4-S3 FEMDM 2020 CPU) saves the current
circuits are conditioned by long-time. The
Main storage address to be available for the
Y read driver and write gate is also conwhole core storage cycle (Read/Write)
ditioned by long-time; but, the Y read gate
The SAR, able to hold addresses one hal£word
and write driver are conditioned by shorttime.

in length, consists of 18 latches numbered
PO to IS. Only the bits 0 to IS are used for

Strobe is ANDed with not-inhibit-timing and

addres sing.

address-register-bit-3 to produce sense-

The addresses may arrive either from the

strobe-8K ; not-address-register-bit-3 is

local store (LS) or from the ALU output (Sum

used to produce sense-strobe -4K.

Bits).

In the timing chart, the Y current (low order
end) shows a pulse at TO and T4 time. This
pulse is present, due to the initial charging
of array capacitance, although the X line
is not conditioned at the other end at this
time. The Y read current (high order end)

SAR Input Control
•

and Y write current (high order end) begins
at short time, when both ends of the line
are conditioned.

The SAR Input is controlled by LS to SAR
or ALU to SAR.

•
•

The SAR is reset/set at TS.
ALU to SAR is only performed for TRBS/

Inhibit-time is ANDed with write-cycle to

TRBL and the RD format micro-instruc_

produce inhibit-timing, shown in the timing

tions (cycle 0 or "1).

2020 FETOM

(5/68)

2-37

IBM CONFIDENTIAL
LS to SAR

bytes. Halfword addressing is achieved by

This is the common signal. It is active when
the Delta Process latch is on without any CPU
check. However, ALU to SAR prevents LS to

using the even part of the byte address (SAR
bits 0-14) only.
The unit bit (SAR bit 15) is used to specify
the left PO-7) or right (PI-IS) byte of the

SAR.

halfword, which is read out from storage
ALUto SAR

or will be written into storage.

This signal is necessary to place the ALU
output into SAR. It can only occur when the
Process latch is active and no CPU check is
turned on. For Cycle Stealing, the ALU to

•

powering of the address bit lines.

SAR signal is suppressed (LS to SAR active).
ALU to SAR is only forced by a small number

•

of micro-instructions.
These micro-instructions are
TRBS/TRBL

SAR Powering provides the necessary

After SAR Powering the SAR bits are
defined as Address Register bits.

•

Aux storage areas are addressed when
SAR bits 0 and 1 are both on.

LH/STH
BZ/BM

•

are forced by circuits.

BP/BAC
B (unconditional)

The storage addresses for CPU LOG

SAR

bits 0-14 are fed to SAR Powering.

These instructions have one common function,

The SAR powering circuits provide dri ver

viz. , to change addresses either by branching

circuits for powering the address lines (to

or using a displacement address.

main storage) as well as logical circuits to

ALU to SAR can only occur during cycles

force addresses for CPU LOG in, and to de-

o and

code Auxiliary storage addresses.

The bit outputs of the SAR powering circuits
are defined as Address Register bits to be

•

Addresses in SAR define bytes

•

Since the core storage operates on a two

compatible with the line definition of the core
storage circuits.

byte (halfword) basis only the SAR bits

o to

•

14 (even) are used for storage ad-

dressing.

SAR Check

SAR bit 15 defines the byte in the half-

•

word addressed by SAR bits 0 to 14.

The SAR is checked for correct parity.

The SAR contents are checked for proper parity

The Main Storage is addressed on a halfword

(odd). SAR Check causes Process Check and

basis. However, the addresses in SAR define

the CPU stops at the end of the current cycle.

2-38

(5/68)

lRM CONFIDENTIAL
The erroneous address in SAR remains un-

If Storage Use is prevented, all core stqrage

changed.

functions are suppressed and no Sense Bits
are provided. Thus, SDR would be blank (no
data bits, no parity bits) after read time.
However, SDR can be transferred to other

SAR Display
The SAR contents are displayed on the CE
console when the CE Display Select switch

CPU components even if Storage Use
is prevented. This would cause any parity
check.

is set to SAR.

Thus, no Storage Use condition

forces SDR bits PO and PI to provide correct parity_
Invert Parity condition, caused either by
STORAGE DATA REGISTER

Storage Test operations or by operations with
the Invert Parity switch (CE Console) turned

•

The SDR is set directly by the core
sense pulses at T8

on, prevents forcing of PO and PI, because
even parity (Inverted parity) is required in
this special case.

•

The SDR is reset when a core storage
cycle starts (T 6).
SDR Output

The Storage Data Register (SDR, Figure

4-54 FEMDM 2020 CPU)

is a halfword

•

The SDR data is provided to : OP REG,
TDR, Inhibit and as CS data out bits

to the active CS device

It is set by the halfword corning from the

core storage sense amplifiers.
The Sense Bits are numbered from 1 to

17.

The bits 16 and 17 are the parity

bits PO

(16) and PI

(17).

The SDR output is fed to the Op Register
(micro-instructions), to the To-Data Register
(Data), to the Inhibit Switch {for regeneration),
or to the Cycle Steal Unit (CS Data out).

The SDR is reset at each T6 (Start of
Read time)

when the Delta Process

latch is on.

SDR Display
The SDR contents are displayed on the CE
console when the CE Display switch is set
to SDR.

SDR Parity
INHIBIT SWITCH

•

No Storage Use (no sense bits)
forces SDR bits PO and Pl.

•

The Inhibit Switch selects the store data
sources.

2020 FETOM

(5/68)

2-39

IBM ¢ONFIOENTI\t\l
o

The Inhibit Switch processes always
one halfword at a time.

The Inhibit switch (Figure 4-55, FEMDM

•

or Address Check occurs.

•

can provide data to be stored. The sources
for normal operations are SDR and ALU output. For Cycle Stealing, the data sources
are the Cycle Steal buffer s in the IOC, Stor-

Only for Storage Test the result is
stored during cycle 2.

2020 CPU) contains the control circuits necessary to select the different sources, which

ALU to Inhibit is prevented when a SAR

The ALU output provides the final result, which
shall be stored into core storage, during cycle 3.
Only a few numbersof micro-instructions provide a final result of one halfword in length.
These instructions are:

age Control Feature, or in the BSCA.

STH

CPU LOG in uses special circuits and the

SLM/SRM

normal operation circuits.

MVH
AH/AHSC
SH/SHSC

) yormal Inhibit 9,perations
During cycle 3 of these instructions, the comSDR to Inhibit

•
•

plete ALU output (halfword) is transferred
to Inhibit. However, transferring is suppressed

The SDR data is regenerated.

in case of SAR or Address check (regeneration,

SDR to Inhibit is forced for SAR or

see SDR to Inhibit). Especially for Storage

Address Check.

Test (Store Runs 1 or 3), the halfword to be
stored is already present at ALU output during

The data movement from SDR to Inhibit

cycle 2. Thus, transferring to Inhibit is per-

is defined as regeneraUon , because the

formed during cycle 2.

data read out during read time are immediately stored back into the origin

Mixed ALU/SDR to Inhibit

storage position (Address in SAR is the
same for Read and Write).

•

When the ALU result is one byte in length,
the second Invert Switch byte derives
directly from SDR (regeneration).

•

SAR Bit 15 defines the Invert Switch
byte into which the

ALU to Inhibit

reSl..~t

byte is in-

serted.

•

The ALU output is stored
during cycle 3.

•
2-40

•

The byte result is always provided by
Sum bits PI to 15 (ALU loworder byte)

The result can be a halfword or a byte

For micro-instructions ,which provides a final

in length.

result (cycle 3), only one byte in length, the

(5/68)

IBM CONFIDENTIAL

second byte of the halfword to be stored is

or Pl-15 are gated to Inhibit. The second byte

provided by the SDR (regenerate the byte not

of the halfword to be stored is provided from

affected). SAR Bit 15 (odd or even byte address

SDR, controlled by either CS Force Regen

in SAR) defines into which byte of the halfword

SDR 0-7 or CS Force Regen 8-15.

the result byte has to be placed. The result

Both CS Force Regen signals are active for

byte is always provided by the right half

CS Write operations (regeneration of the half-

(Sum bits PI-15) of the ALU output. Thus,

words read out and transferred to the CS de-

there is a control to transfer ALU 8-15 either

vices).

to Inhibit 0- 7 or 8-15.
The byte to Inhibit movement is suppressed
in case of SAR or Address Check (regenerate
SDR).
For Storage Alter or Fill the byte move-

Inhibit Check

•

Incorrect (even) parity in either the high:"
order or loworder Inhibit byte causes

ment occurs during cycle 2.
Inhibit Check (indicator on GE console).

Inhibit Cycle Steal

•

CS Inhibit control functions only for CS
Read.

•

CS Inhibit data are provided either as
halfword or as byte.

•

For CS byte transfer SAR bit 15 decides
whether the highorder or loworder byte

•

Inhibit Check stops the CPU after the
current cycle.

•

The CPU stops after the current cycle.

•

CS Inhibit Check does not stop the CPU
immediately.

•

Inhibit Check does not prevent writing
of the faulty data.

of the Inhibit Switch halfword is used.

•

The Invert Switch halfword is completed
by a SDR byte (CS Force Regen SDR).

An Inhibit Check occurs if either the inhibit

During Cycle Steal (CS) operations the normal

bits PO - 7 or the inhibit bits Pl-15 are of in-

inhibit control circuits are blocked. The CS

correct parity. The inhibit check turns on the

Inhibit control functions only for CS Read

Inhibit Check latch, when operating normally,

operations (data is written into core storage).

or the CS Inhibit Check latch, when operating

Data is transferred from the CS devices to the

in cycle steal mode.

Inhibit either in halfword or byte format.

The Inhibit Check latch signals the check condition via interface lines to the CS devices.
An Inhibit check during normal operations
stops the CPU after the current cycle. The

For byte transfer (CS HalfwordFL off), SAR

erroneous data is written into the addressed

Bit 15 decides whether CS Data in bits PO-7

core storage position.

2020 FETOM

(5/68)

2-41

'8M CONFIDENtIAL

Inhibit LOG

The LOG inhibit control has two different func-

•

tions. During the LOG cycles 0, I and 3 , the

Inhibit LOG provides circuits able to test
the contents of Data or Address registers
for correct parity.

LOG_in informations deriving from the CE
Display Bits are gated to the inhibit.
The second function is performed during cycle

•

The bytes of the tested register are
forced to ones (/FF /) or zeros (/00/)
depending upon the found parity.

•

•
•

data or address register which could cause
the check is investigated for its parity. The

The correct byte is set to /00/, while

byte with the wrong parity is forced to /FF /

the byte with wrong parity is forced

(all bits on) while the correct byte is set to

to /FF/.

zero. During Write time the halfword is stored.

Testing is performed during LOG cycle 2.

The halfword does not show the real bit pattern
of the register, but the forced ones or zeros

During cycle 0, land 3 the CE Display
bits are selected as LOG information.

2-42

2 only. During this cycle the contents of the

(5/68)

allow to define in which byte of the register
the error has occured.

.8M ¢Ot'r/FIQENTI.t
OPERA TION CONTROL

•

For LS Display OP REG bits 8 to 11
(Data sw. 1) defines the LS zone, while
the bits 12 to 15 define the LS register
(Data sw.2).

OP REGISTER

At Tl of Delta cycle 1, the SDR is gated into
OP REG as for micro-instruction handling.

The OP Register (OP REG, Figure 4-60,
FEMDM 2020 CPU) is a halfword register
used to save micro-instructions during
their execution.

HQwever, Storage Use is prevented and SDR
contains zeros (correct parity). Thus, the
OP REG is set to zero. At T2, the two hexadecimal values set up in the data switches
are placed into OP REG bits 8-15 (without
parity). The values are used as device address
and specify the I/O which is used to read cards

OP REG Input

for initial control (micro) program load (ICPL).
For LS display or alter the value provided

•

The SDR is set into OP REG at T 1,
delta cycle 0 (reset/set).

by data switch I (OP REG bits 8-11) specifies the LS zone (RI Decode) while the value
in data switch 2 selects one of the eight LS

•

During CPU LOG in, changing of OP

registers (R2 Decode).

REG contents is pr evented (- LOG),
because the contents is used as LOG
in information (LOG in cycle 2, se-

OP REG Output

cond halfword).
•

The OP REG bits 0 to 3 define the OP
REG Decode signals

OP REG Input for MANOP

•

/0/ to /F /.

The OP REG Decode signals are the
main part of micro-instruction OP
code.

•

For ICPL the Data switches 1 and 2
are set into OP REG bits 8 to 15 at

•

The OP REG bits 4 to 7 are either part
of the OP code or, for Rl, RD and I/O

T2, delta cycle O.

format instructions, the Rl-field.

•

After T2 OP REG bit 8 to 15 contains the

•

codes.

device address (8 -11) and function specification (12-15) to read the initial loader
card.

The OP REG is tested for Invalid OP

•

OPREG bits 8 to 15 provide either the
Rl and R2 field (FF -format) or the device

2020 FETOM

(5/68)

2-43

J8M CONFJ{JeNllAl

•

address and function specification (1/0-

immediately after cycle 0 (End Op CY 0, no

format)

execution) .

OP REG bits 4, 8, 12 or 15 can define
direct or indirect operand addressing.

OP REG Bits 8 to 15

The OP REG parity bits do not affect the

For micro-instructions of Rl or DA format

decoding.

these bits carry the immediate data byte or

OP REG bit PI (sets FDR bit PO) allows
parity checking of the Address Bus.

the displacement address, which are not needed
to control the operation.
For RR-format micro-instructions the bits

The bit pattern in the OP REG represents the
micro-instruction to be executed. This bit

8 to 15 provide the addresses of the To-and
From-register. The bits 8 and 12 are used

pattern remains unchanged until the next
micro-instruction is entered in (T 1 of next
delta cycle 0).

The importance of the Op

to indicate whether the adjacent three bits
(9-11 or 13 to 15) specify a LS register
which accepts or provides data (direct ad ...
dressing) or the specified register is used to
address Main storage positions (indirect
addressing).
The bits 8 to 11 are defined as Rl-field (1.

OP REG Decode

operand) while the bits 12 to 15 are defined
as R2-field (2. operand). For Rl-, DA- and

The OP REG Decode circuits investigate the
four OP REG bits 0 to 3 (upper part of OP
code). These decode circuits (AND combinations) provide control signals, called OP REG
Decode 0 to F, according to the hexadecimal
value in bits 0 to 3. The OP REG Decode signals are active during the whole execution time
of the micro-instruction.

I/O - formats, the Rl-field is in bits 5 to 7

(4 to 7 if I/O).
The three address bits (5 to 7, 8 to 11, or
13 to 15), able to represent the values from

o to

7, are decoded. The resulting signals

are called either Rl or R2 Decode 0 to 7 in
respect to the source field.
The switching between the two Rl fields is
performed by investigating the Op code. OP
REG bit 0 on (OP REG Decode 8-F) and not

OP REG Bits 4 to 7

B, SENSE or CTRL defines the RR format

The OP REG bits 4 to 7 are either additional

instructions. Thus, the bits 8 to 11 are used.

OP REG Decode informations or register

All other instructions use the bits 5 to 7 as

addresses (Rl, To-register) Invalid OP code.

the Rl field.

The OP REG bits 0 to 7 and 8 or 12 are checked

For LS display or alter (MANOP), the bits

for invalid OP code. The resulting control sig-

9 to 11, set according to Data switch 1, are

nal (Invalid OP code) forces end of operation

used for Rl Decode (selects the LS zone).

2-44

(5/68)

lBt-l CONFIDENTIAL

The micro-instructions SENSE and CTRL as

•

The cycle sequence can be changed,

well as ICPL use the bits 8 to 15 as device

depending upon the micro-instruction

addresses and function specifications (SENSE

to be executed.

and CTRL numbers), which are sent to the
attachments (channels, control feature, BSCA)
via the address bus.

•

The provided cycle control signals are:
End Op Cycle 0, 1 or 2, Skip ahead,

The parity bit PI is directly set into FDR bit

and Skip to repetition.

PO for parity checking of the returning address
Depending upon the micro-instruction Op code

bus.
Especially for MVHS, the three bit- address
provided by the Rl field is inc!emented by
one to provide the address'-of the second register
for splitting (Rl A, during cycle 2).
The Rl field address is incremented by forcing
the unit bit. Thus, incrementing is only possible
if the Rl address is even. If Rl is odd, no

higher adjacent register can be specified and
splitting cannot be executed.

and the bits indicating direct or indirect addressing (OP REG) the cycle control circuits
(Figure 4_61, FEMDM 2020 CPU), generate
signals to switch the Long Time Clock.
The Long Time Clock fixes operating periodes
called cycles and delta cycles.
Normally the Long Time Clock steps from
cycle (delta cycle) 0 to 3 and starts again with
cycle O. However, depending on format and
type (direct or indirect addressing), a microinstruction can end after any cycle (End Op)

OP REG Display

or can skip cycles (e. g., skip from cycle 0
immediately to cycle 3).

The OP REG contents are not parity checked,
but can be displayed on the CE console, when the
CE Display Select switch is set to OP REG.
Cycle Control Circuits

CYCLE CONTROL

•

The instruction bit pattern in OP REG
controls the cycle control circuits.

•

The Cycle Control switches the Long
Time Clock.

•

The End Op signals cause advancing
of the Long Time Clock to cycle

The Long Time Clock defines the delta
(delta cycle)

cycle and cycle periods.

•

Normally the Long Time Clock provides

•

The Skip ahead and Skip to repetition

the cycles (delta cycles) 0 to 3 in se-

signals switch the Long Time Clock

quence.

to any cycle (delta cycle), except

2020 FETOM

(5/68)

2-45

IBM CONFIDENTIAL

LS register 1 contains the field length.

The CLC, XX type, compares on byte basis.
The compare result sets the condition code
latches (CCO,

cc 1,

setting a new condition code. During cycle 1
of this additional repetition, the End Op latch
iss et.

CC2) when the CC bit

(bit 6) in the micro-instruction is on. The
result may be EQUAL (CCO) or UNEQUAL
(CC 1 or CC2). The cycle sequence for CLC,
XX type, starts with cycle 0 and continues
with function cycles 1 and 2. For ALC, the
function cycles are repeated (Skip to repetition; Skip CY 2 to CY 1) until an End Op

Field Length below zero:

When the compared

bytes are equal until the last repetition, a
Decrement Carry 0 occurs when the field
length in LS register 1 is decremented by 1
(T8 to T3) during cycle 1. This Decrement
Carry 0 sets the End Op Latch (End Op gate,
cycle l, from T 1 to T3).

condition occurs. The field length is decremented by one and the data addresses (LS reg.
3 and 5) are incremented by one, each time

Note that the compare result may be UNEQUAL

the function cycles are performed.

for the last repetition and the CC latches are
set accordingly.

End Op

The active End Op latch prevents the Skip to

The CLC with ALC ends when the End Op

repetition (Skip CY 2 to CY 1) and forces End

latch turns on. The End Op latch can be turned

Op cycle 2 ( skip to cycle 0). Thus, the Long

on at T3 during cycle 1 by two different con-

Time Clock is set to cycle 0 after cycle 2 and

ditions.

the next micro-instruction starts.

Result Unequal: Since the CLC with ALC compares two strings of bytes only two compare
results, EQUAL or UNEQUAL, are possible.

SENSE or C TRL with ALC

During each repetition two bytes are compared

The I/O format instructions SENSE and CTRL

and the compare result sets the condition

operate with ALC when indirect addressing

code latches. As long as the compare result

(bit 4 on) is specified and Rl field addresses

is EQUAL (CCO), the comparing must be con-

LS register 7 (IAR, bits 5 to 7 on). The Rl

tinued. However, if result is UNEQUAL (CCl

field is not used for addressing. It is part of

or CC2) , no further comparing is necessary,

the Op code (defines ALC). The data address

because this is the final result for the complete

is in LS register 7, while the field length is

string of bytes.

in LS register 1. The data address is incre-

The compare result, setting of the CC latches,

mented by one while the field length is decre-

is provided at the end of cycle 2

mented by one, each time a byte is transferred.

too late to

terminate the operation immediately. Thus,

Note that bytes are transferred depending on

an additional repetition is performed without

cycle time.

2020 FETOM

(5/68)

2-49

SENSE with ALC

After cycle 1 , the End Op CY 1 condition

After cycle 0 the Long Time Clock is ad-

(skip to cycle 0) ends the operation and

vancpd to cycle 3 (Skip ahead; Skip CYO to

starts thE' next micro-instruction.

CY 3). Cycle 3 is the function cycle (store
cycle) during which the sense data enters
CYCLE CONTROL FOR MANOP'S

t]1(' CPU and is stored into Main storage.
The storage position is defined by the address

•

in LS register 6.
After cycle 3 the Long Time Clock is

~et

sequence, no End Op and Skip ahead sig-

nals are generated.

repeat the fu,nction cycle (Skip to repetition;
Skip CY 3 to CY 3). The Decrement Carry 0,

Since MANOP'S use the cycles 0 to 3 in

•

ICPL, Storage Scan or Fill, and Storage

which occurs when the field length is counted

Test repeat functions, similar

below zero (cycle 3), sets the End Op latch.

instruction with ALC, by Skip to repe-

The active End Op latch prevents Skip to re-

tition signals.

petition and forces a Skip CY 3 to CY 1.
During cycle 1 the micro-instruction address
(JAR) is updated. For ALC operations the
IAR updating during start cycle (cycle 0) is
prevented to allow recalling of the instruction
in case of trap request interruption. The End
Op CY 1 condition (skip to cycle 0) ends the

micro-

The MANOP'S usethe cycles 0 to 3insequence
Thus, no special cycle control for Skip ahead
and End Op is necessary. All operations end
with cycle 3. However, MANOP'S which must
operate strings of data need repetitions of
function cycles like micro-instructions with
ALC. These MANOP'S are:

operation and starts the next micro-instruction.

CTRL with ALC

ICPL

Storage Scan or Fill

Storage Test

After cycle 0, the Long Time Clock is advanced
to cycle 2 (Skip ahead; Skip CY 0 to CY 2).
Cycle 2 is the function cycle (read and operand 1)
during which the control data is read out from
Main storage and set on the data bus. After
cycle 2 the Long Time Clock is set to repeat

ICPL

•

rCPL loads the CPL Loader card.
ICPL ends when the loader card is read
(field lE'ngth decreased below zero) and

the function cycle (Skip to repetition, Skip

the CPU starts execution of Load Control

CY 2 to CY 2). The Decrement Carry 0, in-

Program (micro-program routine).

dicating that the field length is below zero
(cycle 2), turns on the End Op latch.

•

The active End Op latch prevents skip to
repetition and forces a Skip CY 2 to CY 1.
During cycle 1 , the IAR is updated.
2-50

(5/68)

•

During ICPL, the CPU stops after cycle

o when

any r/o is working.

ICPL continues with cycle l, when any
I/O working drops

IBM CONFIDENTIAL

•
•

The CPU stops again after cycle 1 until

tition signal Skip CY 3 to CY 2, which sets

a read request occurs.

the Long Time Clock accordingly each time

The read request starts the CPU again
and cycles 2 and 3 are executed.

•

the CPU is started again by a trap request.
The Skip CY 3 to CY 2 is prevented by the

After cycle 2 the CPU stops and starts

active End Op Latch, which turns on when the

again with cycle 2 (Skip to repetition),

Decrement Carry 0 during cycle 3 (T8 to T3)

when the next read request occurs.

indicates that the field length is decreased

Operating the ICPL key starts the CPU. Processing starts (cycle 0) when the Delta Process
latch and process latch are active.
After cycle 0 the CPU stops when any I/O is

below zero. Thus, the Long Time Clock advances to cycle 0 during which the first microinstruction starts which has just before read
in by ICPL.

working. The Long Time Check is not advanced.
When the any I/O working condition drops,
the CPU starts again and the Long Time Clock
advances to cycle 1. During cycle 1 the specified read device is started. After this cycle
the CPU stops again. As for cycle 0, the Long

Storage Scan or Fill

•

Storage Scan or Fill repeats the function
cycles 1 to 3.

Time Check still contains cycle 1 after CPU
stopping.
Now the CPU waits for the trap request which

•

Storage Scan or Fill ends (End Op condition)
when the CPU Stop Key is operated.

indicates that a character has been read, which

Storage Scan and Fill differ in data handling.

has to be transferred into Main storage.

During Storage Scan the data are read out for

The trap request starts the CPU and the Long

parity checking and stored back unchanged,

Time Clock advances to cycle 2 and 3. During

while during Storage Fill a byte set up in the

these cycles, the character enters the CPU

data switches is stored into each Main storage

and is stored into its specified Main storage

position within the customer area.

position.

Storage Fill or Scan operations start with

After cycle 3, the CPU stops until the next

cycle 0 and the Long Time Clock advances

trap request (next character) becomes active.

in sequence until after cycle 3. The repe-

The Long Time Clock still contains cycle 3.

tition of the function cycle s 1, 2, and 3 is

Each time a character is transferred, the

forced by the skip to repetition signal Skip

field length in LS register 4 is decremented

CY 3 to CY 1. For Scan or Fill, no field

by one, while the data address in LS register

length is necessary. The End Op latch tUrns

o is

on during cycle 3 when the CPU Stop key is

incremented by one. To store characters,

the number which is specified by the field

operated ( Stop latch on). The active End Op

length, cycles 2 and 3 must be repeated. The

latch prevents further repetitions and drops the

repetitions are controlled by the Skip to repe-

Hold Run condition to stop CPU.
2020 FETOM

(5/68)

2-51

IBM CONFIDENTIAL

Storage Test
•

largest address which can be kept in a half-

The St orage Test is perforlTIed by four

by 2.

runs.

•

Each run starts with address 0000 (protected
The Length Count (LC) latches are used
as run counter.

•
•

word (/FFFE/ = 65,434) when increlTIenting

area) and a four cycle operation (cycle 0, I,

2, 3). For the following addresses up to

During Storage Test the core storage

/FFFF /, the function cycles I to 3 are re-

halfwords are loaded with their own

peated forced by the skip to repetition signal

address.

Skip CY 3 to CY 1.

Run I and 2 load and cOlTIpare the addresses
true while Run 3 and 4 load and cOlTIpare
the inverted addresses.

A run ends when.the End

Op latch turns on at T 3, cycle 3, by an IncrelTIent Carry O. The active End Op latch
prevents the skip to repetition. Since the CPU
is kept running (Process relTIains active), the

•
•
•

During each run, the addresses are in-

Long TilTIe Clock advances to cycle 0 , and

crelTIented by 2 frolTI /0000/ up to

the next run is initiated by a four cycle opera-

/FFFE/.

tion.

End Op condition (run end) is caused by

The End Op latch active at the end of each

an IncrelTIent Carry (address).

run frOlTI T 3, cycle 3, until T 3, cycle 0,

For each address the function cycles I
to 3 are repeated.

advances the Length count (LC) latches.
At start Storage Test, the LC latch latches
are all off indicating that Run I (Store run)

•

Storage Test is terlTIinated after Run 2,

has to be perforlTIed. The End Op latch turns

when th'e CPU Stop key is operated,

on (T3 to T3) at the end of Run I and sets the

The Storage Test perforlTIs four different

LC 2 latch (T7, cycle 3, not AUX LCI).

runs. The Length Count latches keep the in-

The active LC 2 latch forces COlTIpare Run 2.

forlTIation which run is in process.

Run 2 starts and runs silTIilar to Run I, but

The four runs are:

with compare functions.

Run I

Store Run

Run 2

COlTIpare Run

Run 3

Store Invert Run

Run 4 =

COlTIpare Invert Run.

The End Op gate, (cycle 3, TI to T3) caused
by IncrelTIent Carry 0 at the end of Run 2,
allows setting of End Op latch and A UX LC I
latch (LC 2 latch on) at T3.
The active End Op latch stops repetitions

A run ends when the End Op latch turns on
during cycle 3 by an IncrelTIent Carry 0,
which occurs when the highest possible
address is exceeded.

within Run 2 and the Long Time Clock advances to cycle O.
The AUX LC I latch, active frolTI T3, cycle 3,
until T3, cycle 0 (reset), resets LC 2 latch

This address is not the highest Main storage

(End Op latch on) and turns on LC I latch

address (including control area), but the

(End Op and not Invert Parity latch) at T7.

2-52

(5/68)

IBM CONFIDENTIAL

The LC I latch indicates the invert runs (re-

Test it is activated for Storage Fill or Scan

mains active for Run 3 and 4) while the LC 2

if the Invert Parity switch on the CE console

indicates the compare runs (Run 2 and 4,

is turned on. Thus, the s can or fill operation

normal and inverted).

is executed with the incorrect parity and all

The active LC 1 latch turns on the Invert

CPU check latches have to turn on. Only the

Parity latch (Run 3, cycle 0, T3). This latch

Process Check latch remains off, but it is

remains on during Run 3 and 4 (LC 1 active).

set (Attention indicator on) when not all CPU

At the end of the Store Invert run (Run 3,

checks are turned on.

End Op) LC 2 latch turns on again, while LC 1

Thus, Process Check during inverted parity

latch remains active. LC 2 and LC 1 latches

operations paints either to lost data bits or

on indicate Run 4 (Compare Invert run).

failing CPU checks.

At the end of Run 4, the AUX LC 1 latch is
active (cycle 3, T3, to cycle 0, T3), and
resets LC 1 and LC 2. The droppe-l LC 1 latch

LONG TIME CLOCK

allows resetting of the Invert Parity latch
(cycle 0, T 3). Thus, after Run 4 all LC
latches are reset and Storage Test starts
again with Run 1.
The Storage Test ends after Run 2, when the

•

The core storage Read/Write time defines
the CPU cycle time.

•

The Read/Write time is devided into eight
Timing (T) pulses.

Stop key is operated. This provides correct
parity in Main Storage.

•

A core storage cycle lasts from T6 to
T5, while CPU (data floW) cycle runs
from T 1 to T8.

•
Invert Parity Latch

•

The complete CPU processing period
(delta cycle and cycle) to T8 (end cycle).

The Invert Parity Latch is active during

The period the core storage needs for a read

Storage Test or when the Invert Parity

and write operation is a cycle. Thus, the

switch (CE) is turned on.

cycle time depends on the core storage pro-

Invert Parity latch on cause CPU operations with even parity.

cessing speed.
Each core storage cycle (Figure 4-65 FEM
DM 2020 CPU) is devided into eight time seg-

•

Operating with inverted parity turns on
all CPU check latches, but a Process
Check (CPU stop) occurs only if a check
latch fails to turn on.

ments named timing (T) pulses (four Tpulses for Read and four T-pulses for Write).
Thus, a core storage operation is performed
by eight steps. However, the basic period

The Invert Parity latch allows CE operations

necessary to process data in the CPU (Data

with inverted (even) parity. Beside Storage

Flow), requires 13 steps. The additional

2020 FETOM

(5/68)

2-53

IBM CONFIDENTIAL
five steps are provided by overlapping the
d~ta

The cycles 1 to 3 are defined as function cycles.

flow processing periods. Thus, a pro-

cessing period starts before the preceding
one is terminated.
The period during which processing overlaps

Long Time Clock Latches

•

cycle latches (1 and 2) and two cycle

with the preceding processing period is called

latches.

delta cycle. During delta cycle all those operations are performed, which do not influence

The Long Time Clock consists of two delta

•

The delta cycle latches are controlled

the data handling of the preceding processing

by the End Op, Skip ahead, and Skip to

period. The delta cycle lasts as long as a cycle

repetition signals at T4 (start delta cycle).

(eight T pulses). After the fifth 't.pulse of a
delta cycle, the cycle (also eight T-pulses)

•

The cycle latches (1 and 2) accept the

starts. Thus, the basic CPU processing period

delta cycle latch settings at T 1

lasts from start of delta cycle until end of

(start cycle).

cycle (13 T-pulses).
'When the CPU operates in Single Cycle Mode

•

No End OP, Skip ahead, or Skip to
repetition signal causes that the Long

(CE), the period from start delta cycle to end of

Time Clock advances automatically

cycle is the actual processing time.

at each T4 pulse from 0 to 3 and starting

CPU processing is a sequence of delta cycles

again with O.

and cycles (processing periods) to perform
functions specified by micro-instructions or

•

MANOP's.

The delta cycle and cycle numbering
depends on the binary value expressed

During one delta cycle and cycle only one

by the latches (display CE c.onsole).

access to the core storage is possible. Thus,
micro-instructions or MANOP's, which require more than one storage access, also

•

The Reset Clock signal turns of all
clock latch to define the start con-

require more than one delta cycle and cycle.

dition (cycle 0).
Note:

Since delta cycle and cycle are al-

ways considered together, the term CYCLE
will be us ed to cover both.

•

Figure 4-64 in the FEMDM shows
the advancing of the long time clock.

Micro-instructions and MANOP's use up to
four cycles. These cycles are numbered from

o to

3. Each cycle performs a basic function:

Long Time Clock Start and Stop

Cycle 0 = Read out micro-instruction.
Cycle I

Read out second operand.

Cycle 2

Read out first operand.

Cycle 3 = Store result or .data.
2-54

(5/68)

•

Timed by the active Start latch, the
Reset Clock signal occurs for Power
on, system reset, ICPL or Load.

IBM CONFIDENTIAL

•

The Long Time Clock advances for the

Normal Stop

first time at T4 after delta cycle 0
(Process latch active).

•

Normally the CPU is stopped by a 'Halt and

Normally the CPU stops by a "Halt and
Display" micro-instruction.

•

Long Time Clock is prepared (delta cycle
0) for the next start.

•

(HALT)

micro-instruction. This

instruction requires only one cycle (cycle 0)
and forces the End Op CY 0 signal. At the

Since the "Halt and Display" instruction
causes the End Op CY 0 signal, the

•

Display'

end of delta cycle 0 (T4) Delta Process
drops. However, the delta cycle latches are
advanced once more by the End Op CY 0
signal, since Process is still active until Tl.

After CPU check stop, the Long Time

The acception of the cycle latches is per-

Clock contains either the error cycle

formed, since this function is gated by Delta

information or the information of the

Process.

cycle after the error cycle.

Thus, for a normal stop the same clock con-

For single cycling the delta cycle latches

ditions (prepared to start cycle 0) exist as

contain the condition of the next cycle

after Clock Reset. When the Start Key is

(delta) while the cycle latches show the

pressed, the clock starts as described for

last performed cycle.

Clock Reset, but without resetting.

The clock can be manually reset after
check stop or single cycling when the

Check Stop

Single Micro-Instruction switch (CE)

Any CPU check stops the CPU either im-

is on and the Stop Key is operated.

mediately after the cycle in process or after
the next cycle.

During CS operations, the Long Time
After check stop the delta cycle latches are
Clock is not affective.
already set according to the next delta cycle,

The Long Time Clock advances at each T4

while the cycle latches still contain the last

when the CPU is running (Delta Process

cycle performed.

and Process latch on).

This fact has to be remembered when identifying the error cycle, if an CPU check has
occured, using the cycle display on the CE

Reset Clock

console.

For Start of Power on, ICPL, System Reset,
or Load (customer's program) the Long Time

Single Cycle or Single Micro-Instruction Stop

Clock is reset by the Reset Clock signal.

After this stop the delta cycle latches are

The reset Clock signal is active as long as

already set according to the next delta cycle

the Start Latch is on (T8 to

while the cycle latches still identify the last

The clock is reset to cycle O.

T8).

cycle performed (displayed on CE console).
2020 FETOM

(5/68)

2-55

IBM CONFIDENTIAL

Manual Reset Clock

console) on, while the CPU stops.

Resetting clock (cycle 0) either after check

Reset Clock signals are provided at T4 until

stop or Single Cycle or Single Micro-Instruction can be achieved by operating the Systern
Reset key, the ICPL key, or the Load key.
However, operating one of these keys destroy.!
valuable inforrnation

the Single Micro-Instruction switch is turned
off or CPU is started again (Stop latch turns
off).
Clock Functions for Cycle Stealing

(register content, in-

dicators,and so on), since the systern reset
routine is perforrned.

During the Cycle Steal cycle (T6 to T 5,

To allow MANOP1s (Alter, Display, Scan,

Cycle Steal latch on), advancing of the Long

Fill, Test) without resetting inforrnation.

Tirne Clock is prevented. The cycle condi-

The clock can be reset rnanually.

tion of the clock is ineffective. Since the clock

Manual Reset Clock is perforrned when the

is not advanced, norrnal processing starts

Stop key is operated (Stop Latch turns on)

again at that point where it was interrupted

with the Single Micro-Instruction switch (CE

by cycle stealing.

2-56

(5/68)

IBM CONRDENTIAL
LOCAL STORE

The zones as well as the registers within
a zone are numbered from ~ to 7.

The zones are defined by Select LS Y (~-7)
LOCAL STORE AND LOCAL STORE CONTROL

signals, while the X-addresses (~-7) specify
the registers.

Local Store
LS Input Control
•

The LS, mounted on two cards, consists
of 64 halfword registers.

•

To write a halfword or a byte into a LS
WRITE signal must be active.

•

Each of the 64 LS registers can be
separately addressed.

•

Halfwords which shall be stored into LS
are provided either by the ALU or by the
Modifier.

The Local Store (LS) is an internal storage
device able to store 64 halfwords.
•

During direct addressed I/O SENSE's the

The LS (Figure 4-70 , FEMDM 2020 CPU)

byte provided by the Data Bus is directly

consists of 64 halfword registers (LS re-

set into the specified LS register low

gister) which can be separately addressed.

order byte, while the high order byte is
is filled with zero.

Each LS register consists of 18 bit cells,
which are considered to be latches.

• ALU to LS is performed at T5 or T8, while

Thus, a LS register consists of 18 latches

the MAR to LS condition is present for

numbered from PO to 15.

all other T-pulses.

The Local Store is mounted on two cards.

•

I/O Bus to LS occurs only at T8 and
overrides ALU to LS.

One card provides the latches PO-7 of all
64 registers, while the other card provides the latches PI to 15.

•

During CPU LOG the start address
/C 000/ of the system reset routine
is forced by the input circuits and is

LS AddreSSing

•

set into IAR of zone 7.

A LS register is selected by a Select
LS .. Y signal and a X-address.

The LS registers are arranged in eight
zones. Each zone contains eight registers
(8· times 8 equals 64).

Data forced during CPU LOG in

•

The LS input timing depends on the
LS Write signal.

Only this signal

active allows storing of data into LS.
2020 FETOM

(5/68)

2-57

IBM CONFIDENTIAL
LS Write is generated by circuits

Zone Selection depending upon Program
Level

depending upon the micro-instruction
in the OP REG.
•

•

LS New PL and LS Old PL zone gate
alternating generates the select LS

For details see figure 4-70 in the

Y signals depending upon the present

FEMDM.

New and Old PL.

•

The New PL is active according to
the highest priority request saved in

LS Output Control

•

The halfword of an addressed register

the PL REG.

•

The Old PL is provided by the Old
PL REG.

is provided at the LS output (LS Sense
bits) when the SA gate is active.

•

New and Old PL are different when a
trap request occurs (accepted by PL

The SA gate is active from end of pulse

REG) forcing a New PL until this

A to end of pulse B when LS to TDR,

New PL is set into Old PL REG.
LS to FDR, LS to MAR or LS to SAR
is active.

•

For details see fig. 4- 70 in the FEMDM.

•

During the different PL period

two

different LS zones are selected timed by
the Old and New PL zone gates.

LS ZONE SELECTION

A trap request set into the PL REG forces a

New PL according to its priority. When the

•

The LS zones are selected by the

New PL is different to the Old PL (Old PL

Select LS Y signals 0 - 7.

REG). the unequal PL condition activates the

Old PL Control and the New PL is transferred

•

The LS Addressing (LSA) check turns

into the Old PL REG.

on when none or more than one Select
LS Y signal is active at the same time.

Controlled by the LS New PL Zone gate and
the LS Old PL Zone gate the Select LS Y

•

2-58

The Select LS Y signals (Figure 4- 71,

signals are generated depending on the New

FEMDM 2020 CPU) are activated as

or Old PL. Two different PL"S are present

defined by :

from setting the trap request into PL REG (T3)

the Old or New Program Level

until the New PL is transferred into the Old

(PL),

PL REG (TI). During this period (T 3 to T 1)

Cycle Steal (CS) LS Select, or

Select LS Y signals are generated depending

CE LS Select.

on the Old PL.

(5/68)

IBM CONFIDENTIAL

After the New PL has been transferred into

when the CE display select switch is

the Old PL REG (Tl), both PL's are the saIne

set to OCU 2.

until the New PL changes either by a higher

The Reset PL REG signal forces PL REG

priority request or by resetting the PL REG.

latch 7 (highest priority) and resets the
latches I to 6.

The Reset PL REG signal

PL REG

is generated by the active ICPL reset latch,

•

The PL REG consists of 7 latches

which is set when operating the ICPL key

(1 to 7)

and is reset by CTRL 10 after the loader
card has been read.

•

The PL REG latches are nUInbered
according to the request priority

The Reset PL REG signal can be displayed
(CE console, laInp 0) when the CE display

•

The PL REG latches can be set by
trap requests and CTRL's /09/ to

/OF /.

It can only be reset by

select switch is set to OCU 2 (also display
PL REG). The laInp 0 is off when the signal is active (negative potential).

CTRL's /01/ to /07/.

•

The Reset PL Reg signals occurs
during ICPL and sets PL REG 7,

New PL

•

while the latches 1 to 6 are reset.

The PL REG consists of seven latches
nUInbered froIn 1 to 7.

0-7.

•

These latches are

/OF/

ANew PL is specified by the turned
on PL REG latch having the highest

set at T3 either by trap requests 1 to 7
or by CTRL's /09/ to

The New PL's are nUInbered £rOIn

priority.

T3,

however, only when the corresponding

•

trap request line is inactive.

The trap requests are reset during the
service phases. These service phases

New PL 0 (CPU PL) is operational
if no PL REG latch is active.

•

MANOP's force New PL 7 without
setting the PL Reg.

end with a CTRL resetting the corresponding PL REG latch.

The trap request

line active at the service phase end indicates that the saIne trap request has
been set again.

Thus, the service phase

starts again.

The output of the PL REG feeds circuits,
which allow, that only that trap request is
active, which has the highest priority.
The output of these circuits provide the
New PL.

Thus, the New PL (1 to 7)

The contents of the PL REG are dis -

agrees with the highest latch turned on

placed on the CE console (laInps 1 to 7)

in the PL REG.
2020 FETOM

(5/68)

2-59

IBM CONFIDENTIAL

Changing of Old PL

Allow PL Switching

•

Trap request
only

wh~n

is set into PL REG

•

Unequal New PL and Old PL moves the

•

Unequal PL condition turns on the Change PL

New PL into the Old PL REG.

the Sense Trap Request

Line signal is active.

latch which controls setting of the Old PL REG.

•

Sense Trap Request Lines occur when
PL Switching is allowed (Figure 4-72,

•

New and Old PL are identical until the
priority in PL REG changes either by a

FEMDM 2020 CPU)

higher priority request or by resetting the

•

current PL.

Allow PL Switching defines the cycle
at which changing of the PL does not
influence the current basic operation.

For details see figure 4-71 in the FEMDM.

The trap requests provided by the active
trap request bus lines are gated into the
PL REG by the Sense Trap Request Lines
signal.

Alternating Use of Old and New PL

This signal is active at T3 when

the Allow PL Switching allows setting of
PL REG and, conditioned by the new con-

•

PL depends upon the Old and New

tents of PL REG, changing of the New PL.

Since changing of the New PL immediately

Alternating Use of the Old and New

PL zone gate.

•

Alternating Use of both PL's allows

influences the zone addressing (LS New PL

completing the' old'

Zone gate), Allow PL Switching defines the

tion, while the 'new' instruction is

moment at which the LS zone addressing can

already initiated using the IAR of the

be switched without affecting the current
operation.

New zone.

Generally Allow PL Switching occurs during
the last cycle of a basic operation, which is
either cycle 3 or the cycle during which the
corresponding End Op signal becomes affective.

•

micro-instruc-

The functions which are already performed using the zone infor·mation of
the New PL are:

IAR to SAR (TS),

IAR to MAR (T6), IAR to FDR (TI).

For ALC operations Allow PL Switching occurs
in the last cycle before performing the skip to
repetition.

The Old and New PL are alternating used to
generate the Select LS Y signals controlled

Allow PL Switching and Unequal PL set

by the LS Old PL Zone gate and the LS New

the Long Tin:e Clock to delta cycle ~ at T4.

PL Zone gate.

2-60

(5/68)

IBM CONFIDENTIAL

According to the gate timing the Old PL is

the present Old PL are used alternating

used at T3, T4, T7, T8, T2, while the New

during the four LOG cycles.

PL is used at T5, T6 and T2.

The LOG cycles

a to

2 perform function

without using the LS.
The following functions are performed by using
the New PL :

During delta cycle 3

the IAR of the zone defined by the Old PL
is read out at T7 (LS Old PL Zone gate),
while the start address of the system reset
routine ( /000/, forced by circuits) is set

IAR to SAR at T 5 :

into IAR of the zone specified by New PL.

This function places the micro-instruction
During LOG PL REG latch 7 is forced on
address into SAR. Since the micro-instruction
by Reset PL REG. The Reset PL REG sigread out as the next is already the first
nal is generated by the ICPL Reset latch.
instruction of the service phase, the IAR of
This latch turns on by the Reset Pulse which
the zone defined by New PL has to be used.
occurs during CPU start, when the System
Thus. at T 5 the LS New PL Zone gate is active.
Reset key is operated.
IAR to MAR at T 6 :

Thus, the New PL 7 condition re.mains on,

This function places the IAR into the MAR for

even if MANOP drops at the end of LOG in.

updating the micro-instruction address. Thus, the

The System reset routine operates in PL 7.

new zone has to be used.

IAR to FDR at T 1 :

Zone Selection for Cycle Stealing

This function places the IAR of the new zone

Caused by Any CS request and depending

into FDR for branch type instructions.

on the active CS Request latch (device I,
2, 3, or 4) two LS zones can be selected
at CS LS Select time.

Old/New PL during CPU LOG in

The CS Request latch device 1 or 2 forces
selection of zone 7 (Select LS Y 7), while the

•

CPU LOG in forces New PL 7

•

Since Old PL REG is saved during LOG

CS Request latch device 3 or 4 selects zone 1
(Select LS Y 1) Any CS Request is active from

two different PL - s address

LS zones

i""

T3 to T2. The CS LS Select time lasts from
TS to T2.

depending upon the zone gates.
CE Zone Selection
During LOG,the MANOP signal forces New
PL 7.

The New PL 7 cannot be transferred

•

For LS Disalter the zone is selected by

into Old PL REG since LOG prevents reset/

setting Data switch 1 to a value from

set of Old PL REG. Thus, New PL 7 and

¢ to 7.
2020 FETOM

(5/68)

2-61

•

For LR or STR the instruction bits 9 to 11

Variable X-Addresses

(R1-field) define the LS zone.
•
For MANOP LS Disalter the zone is selected

Variable X-addresses are provided by the
R1 or R2 field in the micro-instruction

by setting Data switch 1 (Customer console)
to a value

to 7. The value set up in the Data

•

switch 1 is placed into OPREG bits 9 to 11. These

The R1 or R2 Select signal defines which
field is used for addressing.

bits feed the R1 Decode circuits.
The R1 Decode signals ~ to 7 generate the
corresponding Select LS Y signals.
For LR and STR micro instructions the R1
field (bits 9 to 11) specifies the zone, LS register I
of which is used as first operand. The value
in the RI field forces the R1 Decode signals
~

to 7. The R1 Decode signals are used

during cycle

either at T3 (LR) or at T8

(STR) to generate the corresponding Select
LS Y signal.

•

If Rt (To-operand) is 7 (IAR addressed)

LS WRITE is suppressed.
According to the RI and R2 field of the mi.cro
instruction placed in the op REG (TI cycleO)
the RI and R2 Decode signals 0 to 7 are
generated.
cycle 0

These signals are active from

T I (set instruction into op REG)

to the next cycle 0, TI (change op REG
by setting the next instruction).
The RI Select and R2 Select signals (Fig.
4-73 and 4-74, FEMDM 2020 CPU) gen-

LS REGISTER SELECTION

erated at specified T-pulses depending upon
the present micro-instruction (op Code),

•

The X-Addresses, which select any register
in a specified LS zone, can be fixed or
variable.

define which decode signals (RI or R2) have
to be used as X-addresses at which time.
When the RI field specifies the LS register
7 (IAR, RI Decode 7) writing data into LS

•

X-Addresses are checked that not more or

at T8 (store result) is prevented.

less than one address is active at a time
(LSA Check).

Note: For LR and STR, RI Decode 7 do not
prevent LS Write, since for these

•

2-62

When none

more than one X-address

instructions the RI field specifies a

is active at the same time, the LSA

zone.

check latch turns on (indicator on CE

allowed.

console).

specified in the R2 field.

(5/68)

For STR writing into IAR is
The LS register 7 is then

IBM CONFIDENTIAL

Fixed X-Address 3

Fixed X-Addresses
Fixed X-addresses (Figure 4-7.5, FEMDM
2020 CPU) are provided which select LS
registers containing additional processing

The LS register 3 contains the field length
for CS operations forced by device 2 or 4 requests.

informations (e. g. , field length).

Fixed X-Address 4
Fixed X-Address ~
BST:
Packed Decimal instructions with ALC:
For these instructions LS register ~ contains
the field length of the second operand.

After BST, LS register 4 contains the address
of the Main storage halfword into which the BST
instruction address (IAR) incremented by 2 has
been stored.

MANOP's:
For MANOP's LS register ~ contains the data

ICPL:
For ICPL LS register 4 contains the field

address.

length (defines the number of columns to be
CS operations, request device 1 or 3:

read from the loader card).

During CS operations, forced by device 1 or 3
requests, LS register

contains the data address.

No X-address 5 is forced by circuits.

Fixed X-Address 1

Note: Fixed X address 1 for other than ALC or
CS operations is a

Fixed X-Address 5

'Don't

Fixed X-Address 6

Care'

function.

For SENSE or CTRL with ALC

LS register 6

contains the data address.
All ALC instructions:
LS register 1 contains either the field length

Fixed A-Address 7

or the field length of the first operand
(Packed Decimal).

LS register 7 always contains the IAR.

CS operations, request device 1 or 3:
LS register 1 contains the field length for
the CS operations.
Fixed X-Address 2

LS WRITE

The LS Write signal active allows setting of
data provided by A LU or Modifier output or

The LS register 2 contains the data address

by the data bus input (sense data) into the

for CS operation forced by device 2 or 4 requests.

specified LS register (specified either by
2020 FETOM

(5/68)

2-63

IBM CONFIDENTIAL
variable or fixed addresses). The signal (Figure
4-76, FEMDM 2020 CPU) is generated either
depending on the micro-instruction or forced
by circuits (MANOP or CS).

2-64

(5/68)

IBM CONFIDENTIAL
MAR AND MODIFIER

•

Branching is performed unconditional
(TRBS, TRBL, B) or conditional (BZ, BM,
BP, BAC).

The MAR and the associated circuits are shown

•

Branching is performed when the Branch Go
latch turns on.

in Figure 4-80, FEMDM 2fl2fl CPU.
•

MAR

For conditional branch instructions, the
halfword to be tested is set into MAR.

The MAR is a halfword register. The 18 MAR
latches are numbered P fl to 15. The MAR can

At T3, during cycle fl, of the branch micro-

only be set by data received from the LS . The

instructions BZ (zero), BM (minus), BP (plus,

MAR output is provided to the Modifier, the

but not zero), BAC (address check) the contents

test circuits, and the Address check circuits.

of a specified Rl) LS register is placed into MAR.

The MAR contents are displayed on the CE

The MAR output feeds test circuits, the output

console, when the CE Display Select switch is

of which is gated by the corresponding mioro-

set to MAR.

instructions (OP REG Decode, OP REG bits).
If the MAR contents match with the branch

The MAR is not parity checked.

condition the Set Branch Go signal is activated,
which turns on the Branch Go latch at T4 (reset/

MAR Input Control

set), cycle fl. The active Branch Go latch forces
The LS Sense Bits P fl to 15, provided by the

branching (Branch address to SAR and to IAR

LS output from end of pulse A until end of pulse B

at T5).

(SA gate), are accepted by MAR at pulse B

The Branch Go latch is turned on unconditionally

(reset/set), when the LS to MAR signal is active.

for B, TRBS and TRBL. The Branch Go latch

The LS to MAR signal can occur at T3, T5, T6
and T8.
MAR setting at pulse B ensures that the LS

is reset at T4 (reset/set) during cycle ~ of the
next following micro-instruction.
CS operations block Branch Go.

Sense bits are stable at LS output (end of
SA gate).

Branch Go

Test for 1:IAR zero

•

For branching the branch address (ALU

For BZ the Set Branch Go signal is activated

output) is set into IAR and SAR.

if the MAR bits ~ to 15 are all zero.

2020 FETOM

(5/68)

2-65

IBM CONFIDENTIAL

Test for MAR minus

Address Check

Low~

/0000 / to /008 F /
For BM, only the MAR bit ~ is investigated
for being on, since this bit is the sign bit for
a binary number placed in MAR.

The protected area addresses

are not directly accessible to

the customer.
Thus, addresses. programmed within the
customer program cause an address check
low if they are below /0090/.

Test for MAR plus
The address check low ciTcuit investigates
For BP, MAR bit ~ is investigated for being off.
However, in addition any other MAR bit must be
on (not zero).

decimal values).
4-80 in the

Test for Address Check

•

the MAR bits 0 to 11 (three high order hexaFor details see figure

FE~DM.

For CS operation, MAR bits 0 to 13 zero
forces the corresponding signal which is

Address Check is caused either by addressing
the protected area (/ ~~~~ / to / ~~8F / )

sent as Counter Zero interface signal to
the CS devices (attachments).

or by an address which exceeds the customer's
Main storage area.
Address and Halfword Boundary Check

•

Since the customer's storage area is variable
in size, the 'address check circuits
must be prepared by plugging jumpers

•

instructions, are checked for being in the

according to the rented storage capac,ity.

For CS operations, MAR bits 0-13
zero force the CS interface signal

The operand addresses, used during micro-

customer's area when the AC bit (bit 7) is on.

•

Either the Upper or Lower Address Check

•

Halfword operand addresses are unconditionally
checked to be even (bit 15 off).

•

An odd halfword address turns on the Halfword

•

Any of the three check latches turned on

Latch turns on.

Counter zero.

When an address is set into MAR; it can
be checked, that it does not exceed the
available customer's area (Address check
high) :or specify the protected area (address

Boundary Latch.

check low).

Address Che<:~ .. ~~~h.: Depending upon the avail'able

cu~omer storage,

the high order MAR bit

o to 3 are investigated. See figure 4-80 in the
FEMDM.
2-66

(5/68)

forces Trap Request 2.

•

The three latches are sensed and reset by
a SENSE /16/.

IBM CONFIDENTIAL
Besides checking an address, currently present

During this routine a SENSE /16/ can be

in a LS register, by a BAC micro-instruction

used to decide which check caused the trap

the addresses used within a micro-instruction

request 2.

are checked for validity when the AC bit (bit 7)
in the micro-instruction is on.

The check latches are reset either at T8

During halfword micro-instruction, like
MVH, MVHS, AH, AHSC, SH.

and SHSC,

the used addresses are checked to be for
halfword boundaries (even addresses, MAR

during SENSE /16/ or when the CPU is
stopped (not Process, end Storage Alter).
For Storage Fill or Alter the High and Low
address check latches are reset each time
at T6 during delta cycle 1. 2, or 3.

bit 15 off).
The three check conditions. address check high .

low. and boundary check. turn on latches
named accordingly. Setting of the latches is

MODIFIER

prevented when any CS request occurs or when
Storage Use drops (addressing of not available
storage positions. including control area).

•

The Modifier increments or decrements
LS halfword by 1 or 2.

Setting of the latches is timed by T6 during
delta cycles 1, 2 and 3. Since during these

•

For parity checking the Modifier parity
(PO, PI) is predicted.

delta cycles operands are processed, only
the operand addresses are checked. Note that
the addresses are already placed into SAR at T5.

The Modifier can increment or decrement
data by one or two.

The result returns to

The upper or lower Address Check latch active

LS register.

forces Regen Halfword.

Modifier unchanged (start address from

This signal causes that

During ICPL data pass the

the halfword read out by the faulty address is re-

Address switches in LS Reg 0 moves to

generated.

IAR, zone 7).

During Storage Fill or Alter (not CE mode switch

The Modifier output is parity checked. The

on) the procedure allows the customer to display

Modifier parity bits P

the control area but not to alter any data in it.

according to the parity in MAR. the function

and PI are predicted

to be performed, and bit pattern in MAR.
Any address check latch on forces trap request 2
(not affective during MANOP Storage Alter or Fill,
Modifier Control
PL 7 is forced).
This allows servicing the address check by a
special micro-program routine.

•

Increment by 1 and Decrement by 1 or 2
are control signals generated depending

2020 FETOM

(5/68)

2-67

upon the operation to be performed.

•

The carry out of the Modifier halfword is
defined as Increment or Decrement Carry ~.

•

Increment by 2 is· active when no other
Increment or Decrement signal is generated.

The Modifier is mounted on two si milar cards.
One card contains the Modifier circuits for the
loworder byte (P1 to 15), while the Modifier

•

During CS operations the Modifier is controlled

circuits for the highorder byte (P

by the CPU CS unit.

on the second card.

to 7 ) are

The carry information from the loworder byte
The Modifier control circuits provide the Increment
or Decrement by 1 or 2 signals (Figure 4-81,

to the highorder byte is provided either by the
Increment Carry 8 or Decrement Carry 8 signal.

FEMDM 2~2~ CPU). The signals are generated
depending upon the basic operation to be executed
and are timed by delta cycles (T4 to T3) or half

An overrun out of both bytes is indicated either
by the Increment or Decrement Carry ~.

delta cycles (T4 to T7 or T8 to T3). Increment

The Carry 8 is a internal Modifier signal, while

by 1 and Decrement by 1 or 2 are controlled

the Carry ~ is used as CPU control signal.

signals, while Increment by 2 is forced if no

For details of the modifier circuits see fig.

other Modifier control signal is active. Thus,

4-80 in the FEMDM.

Increment by 2 is active generally. To move
data through the Modifier unchanged , this

Modifier Parity Correction

common control signal is suppressed (no
Increment or Decrement).
During Cycle Stealing all four Increment and

•

MAR bits PO and PI predict the

•

The predicted parity is changed when

Modifier parity.

Decrement possibilities are controlled by the
CS Modifier Control. The result is present at
Modifier output only as long as the corres-

a defined MAR bit pattern indicates

ponding Increment or Decrement signal is

that the Modifier operation changes

active.

the status (on to off, off to on) of an
odd number of MAR bits.

Modifier Circuits

•

The Modifier consists of two seperate

Modifier Check

circuits, able to process one byte.
•
•

2-68

Even parity in either the highorder or

The low order byte provides a carry

loworder Modifier byte turns on the

(Increment or Decrement Carry 8) to the

Modifier Check Latch (indicator on

high order byte.

CE console).

(5/68)

IBM CONFIDENTIAL

The Modifier output is parity checked. An
even number of bits (including parity bit)
either in the highorder or loworder byte turns
on the Modifier

Check latch (indicator on

the CE-console).

2020 FETOM

(5/68)

2-69

IBM CONFIDENTIAL

FDR data are fed through the Invert Switch

LOGICAL UNIT

before entering

th~

ALU.

The Invert Switch can be controlled,

so that FDR data passes unchanged (True) or
•

The Logical Unit consists of FDR-Invert
SWitch, TDR-Shift Unit. and ALU.

inverted. If the True and Invert control signals
are active at the same time the Invert Switch
forces the FDR data to zero, while at a time.
when both signals are absent, the output of the

The ALU is able to perform logical
as well as arithmetical operations using

Invert Switch is fixed to ones.
op~rands

provided by FDR and TDR. The logical operations
are ANDing. ORing and Exclusive ORing.
ADDing is the only arithmetical function which

FDR Set

can be executed.
Before the operands. provided by FDR or TDR

•

LS to FDR, ALU to FDR or I/O Bus to

enter the ALU. they can be modified either by

FD:R, selects the halfword which is set into

the Invert Switch (FDR operands) or by the

FDR.

Shift and Suppress Unit (TDR operands).
•
FDR AND INVERT SWITCH

ALU to FDR causes the Reset FDR signal
(T6), while the other conditions reset/set
the FDR.

•

FDR keeps one operand during ALU
operations until the result is saved.

•

Retain FDR¢-7 causes that during TRBS or
TRBL. cycle ¢. LS to FDR only se~ the
loworder FDR byte. The highorder byte is

•

The Invert Switch provides FDR bits to the

retained.

ALU either true or inverted.
•
•

For I/O Bus to FDR the Address Bus parity

The Invert Switch can force zeros or

bit (OP REG bit PI) directly sets the FDR bit

ones.

p¢ (Address Bus to FDR bits ¢-7).

FUR 'and Invert Switch are shown in figure
4-9¢. FEMDM 2¢2¢ CPU. The FDR is a

•

Sense data of CPU SENSE /14/ or
/15/ are one halfword in length.

short time 'storing device, which save one
operand during ALU operations. This operand

•

For CPU SENSEI s parity checking is

is provided either by LS, ALU output (preceding

inhibited since CPU sense data are

result) or by sensed data from the I/O Bus.

provided without parity bits.

2-70

(5/68)

IBM CONFIDENTIAL
LS to FDR

signal is active, is set into FDR at T4
(cycle 0 or 1).

Since CPU st:'nse data is

LS to FDR signal generated at Tl, T3, T4,

provided without parity the Prevent ALU

and T7 depending upon basic operations allows

and SU Check signal is generated.

the LS Sense Bits PO to 15 to enter the FDR.

For TRBS and TRBL, T3, cycle 0, the
Retain FDR signal is activated.

The active

.FDH Parity correction

Retain FDR signal prevents resetting of
FDR bits PO to 7 and blocks the FDR input
for the LS Sense Bits PO to 7.

•

To correct FDR parity bits for CPU sense
data the signals Force or Turn off PI or

Thus, only

the LS Sense Blts PI to 15 are placed into

are generated by the ALU parity correction

circuits.

FDR while the FDR bits PO to 7 remain unchanged.

•

For parity correction the FDH bits 8-11 are
moved to the Shift Unit (lNT SU bits 4-7)
during TRBS. cycle

ALU to FDR

When thl' ALU to FDR gate is active, the
ALU to FDR signal gates PO to 15 from ALU
into FDR.

The FDR was reset at T6 by the

Reset FDR signal.

only.

The FDH contains IS latches numbered

15. The latches are reset when new data shall

be placed in (reset/set). The FDH contents are
displayed
, on the CE console when the CE Displav
.
Select switch is set to FDR.
To proyide correct parity for CPU sense data
the parity latches P0 and P I can be set or turned

r/o

Bus to FDR

off controlled by the ALU Parit,v Correction
circuits which generatt' the CPl: sense data

The I/O Bus to FDR signal s<'ts the Sense

parity when the PreH'nl ALl] :ll1d flU Check

Bits 0 to 7 and PI to 15 into FDR. The

condition exi s ts . 130th pa rity bits a re affected

parity bit PO derives directly from tht' OP

SillCt' CPU sense data m:JY be

REG bit Pl.

haltword in length

The bits 0 to 7 are prov ided

by the Address Bus while the bits PI to 15

ForTHBS. CY 0. the FDR bits

are the sensed data byte provided on the

lrallsterred to the Shit! l;nit (lJecomes I1\:T SlJ

Data Bus.

iJits 4 to 7). Transferring these bits to the

to 11 are

SU saves the parit~· infornwlion since the IJUs

CPU sense data, which art' provided either

are forced to icro

when performing a CPU SENSE, an TCPL

(THBS only). If an odd Ilurnj,er of hits is

SENSE, or when the MANOP inbus to FDR

forced to lero the FUn parity l.dt P J is wrong

1).\'

the Invert Switch

2020 FETOM

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2-71

IBM CONFIDENTIAL
for the Invert Switch output. This would also

An active FDR Invert signal causes the

cause wrong parity PI of the ALU result. However,

corresponding FDR bits to be inverted at

the saved parity information inSU can tell. that

the Invert Switch output.

either an even or odd number of bits has been
forced to zero and a Change Parity (PI) signal

Beside the true or invert function, the In-

is generated accordingly within the ALU Parity

vert Switch is able to force zeros or ones

Correction circuits.

at the output.

Invert Switch

To force zeros the FDR True and all three
FDR InVert signals must be active at the

•

The Invert Switch is controlled by FDR

same time.

True or FDR Invert.
It is possible to force either the FDR bits

•

FDR True affects the complete FDR half-

o to

word, while three FDR Invert signals

only one of the three Invert signals is active.

(¢ - 7.

The other FDR bits remain unchanged.

8 - 11,

12 - 15) can affect bit

7, 8 to 11 , or 1 2 to 15 to zero when

groups.
The Invert Switch output is forced to ones
•

•

True and Invert force the FDR bits to

when both control signals (True and Invert)

zeros (parity bits on).

are absent at the same time.

Not True and not Invert force ones (parity

The Invert Switch Control provides the True

bits on).

and Invert signals generated depending on the
basic operation in process.

•

Possible control combinations are: True and
Force zeros or Invert and Force ones.

The Invert Switch consists of AND-OR combi-

Invert Switch Parity

nations which are activated by the invert switch
control signals 'FDR True' or 'FDR Invert'

•

(Figure 4-91, FEMDM 2¢2¢ CPU). When the

Invert Switch functions are normally performed
on byte boundaries.

FDR True signal is active the FDR bits P¢
to 15 run through the Invert Switch and become

•

the Invert Switch bits P,Ill - 15 (Invert Switch
output) unchanged

True or Invert on byte format does not
influence the parity.

(true).

For invert operations the FDR bits 0 to 7,

•

Forcing a byte to zeros or ones always results

8 to 11 and 12 to 15 can be selected by

in even parity and. thus. the parity bit has to

separate FDR Invert signals.

be turned on.

2-72

(5/68)

IBM CONFIDENTIAa.
The Invert Switch functions are performed

During cycle ¢ the bits 8 to 11 are forced to

either on halfword or byte boundaries,

zeros while the bits 12 to 15 as well as the

except during TRBS when the bits

bits ¢ to 7 are transferred true.

8 to 11 are forced to zero and the bits 12 to 15
are transferred true.

Since the bits 8 to 11 are forced to zeros the
parity of the loworder byte at the Invert Switch

When a byte moves true (unchanged) through the

output (Invert Switch bit P1) is undefined. The

Invert Switch, the FDR parity becomes the Invert

FDR bit P1 becomes Invert Switch bit P1

Switch parity.
For FDR Invert on byte boundary the FDR
parity also becomes Invert Switch parity since
the number of turned on bits is not changed by
inverting.

The Invert Switch parity bits are used for
ALU parity prediction. Thus, an information
is needed which tells wether the Invert Switch
bit P1 is correct or not. In case of incorrectness
the P1 information must be changed to get

When a byte is forced to zeros or ones, the

correct ALU parity.

corresponding parity bit is turned on at

Invert Switch bit P1 is incorrect when the

the Invert Switch output. However, during

FDT bits 8 to 11 (forced to zeros) provide

operation with Invert Parity mode (Invert

an odd number of turned on bits.

parity latch on) setting of the parity bit of

During TRBS cycle ¢ the FDR bits 8 to 11

a byte forced to zeros or ones is inhibited
are transferred to the INT SU bits 4 to 7.
to provide even (incorrect) parity.

The Shift Unit parity circuits generate the
signal

'Odd SU Bits 4 to 7' if the number

of turned on bits is odd. The active Odd SU
Bits 4 to 7 signal causes changing of the
TRBS - Invert Switch Parity

•

ALU parity P1 which is predicted depending
upon the Invert Switch bit P1 (can be incorrect)

Two different Invert Switch functions

and the INT SU bit Plo

in a byt e cau s e undefined parity.

•

The Invert Switch parity bits are used

Invert Switch Display

to predict the ALU parity bits and the
prediction is corrected if an odd num-

The Invert Switch output is displayed on

ber of turned on bits (8 to 11) is forced

the customer console in Data Register

to zeros.

(DR) display E (PO,
T

a to

(PI, 8 to 11), and R

3), S (4 to 7),
(11 to 15).

TRBS is the only basic operation during
which Invert Switch operations are not

During TRBS the byte displayed in DR-T

performed on byte boundaries.

and R may show incorrect parity (PI),
2020 FETOM

(5/68)

2-73

IBM CONFIDENTIAL
since the change parity function (bits 8

The TDR can ·be entered from the SDR or

to 11 forced to zeros) affects only the

the LS always one halfword in length.

parity of the ALU output (result).
The TDR is. not parity checked.

Eight Shift
TDR AND SHIFT UNIT
The TDR output directly feeds the eight
TDR and Shift Unit (Figure 4.100, FEMDM

2020 CPU) represent the second input of the
Logical Unit.

The TDR is set by data which

shift circuits.

After the eight shift cir-

cuits the bits are defined as Internal
(INT) SU bits PO to 15.

derives either from the LS or from the SDR.
Four eight shift functions are possible:
The TDR data enters the ALU via the Shift
Unit (SU).
The SU can shift TDR data by eight, four

Cross Shift

or two bits to left or to right. The SU can

Eight Shift Left or Right

also suppress (set to zero) the complete

No Shift Halfword

TDR halfword or selectable bit groups of

No Shift Byte,

the TDR halfword.
The SU contains circuits to perform sign
or packed byte testing and circuits which are

The four shift functions are controlled by
four eight shift control signals:

able to normalize signs according to the
No Shift - TDR 8-15 to SU 8.15

EBCDIC or ASCII standard.

TDR 0 - 7 to SU 0.7
For CTRL' s, TDR data is provided to the

Shift

• TDR 0-7 to SU 8.15 (right shift
by eight)

Data Bus after the eight shift circuits.

TDR 8.15 to SU 0.7 (left shift
by eight)
The Eight Shift output is parity checked
TDR
(SU Check).
The TDR is a halfword register consisting
of 18 latches numbered PO to 15.

The TDR

Cross Shift:

contents is dis)?layed on the CE console

Cross Shifting, exchange of highorder and

when the CE Display Select switch is set

loworder byte,' is performed when both shift

to TDR.

signals (TDR

The TDR contents is changed only

when new data i~ set (Reset/Set):
2-74

(5/68)

~-7

to SU 8-15, TDR 8-15 to

BU 0-7) are active during the same cycle,

IBM CONFIDENTIAL

Eight Shift Right or Left:

to provide odd parity. However, for inverted

Only one shift signal, TDR ~-7 to SU 8-15

operations (Invert Parity Latch active) forcing

or TDR 8-15 to SU ~-7 is active. The not

of the parity bit is suppressed (even parity).

affected INT SU bits (~ to 7 or 8 to 15)

Incorrect parity (even) of the INT SU bits

are set to zeros.

(highorder or loworderbyte) activates the
SU Check latch and the corresponding indicator

No Shift Halfword:

on the CE console turns on. The check is

When the two No Shift signals, TDR ~-7 to

inhibited during CPU Senses (Prevent ALU

~-7

and TDR 8-15 to SU 8-15, are active

and SU Check).

at the same time, the halfword in TDR is
moved to the INT SU bits (P~ to 15) without

Shift Unit

shifting.
•

The internal (INT) SU bits, provided by

No Shift Byte:

the Eight Shift, can be shifted by 2 or 4

Only the No shift signal TDR 8-15 to SU

bits to the left or to the right.

8-15 is active. The loworder byte in TDR
(P1 to 15) is moved to the INT SU bits

•

Shift is performed on halfword basis.

•

The SU output bits can be suppressed

P1 to 15. The highorder byte (INT SU bits
P~

to 7) is set to zeros (TDR remains).

in groups of 4 (highorder byte) or 2
(loworder byte) bit groups.

No Shift Halfword and Cross Shift are the basic
function of the Eight Shift circuits. No Shift Byte
and Eight Shift Right or Left are sub-functions

•

Normalize Sign allows standardization
of the packed decimal signs (

which are achieved by additionally controlling the

IF I

No Shift Halfword or Cross Shift control signals.

IAI

valid) according to the required

standard code (ASCII or EBCDIC).
For details of shift control signal generation refer
to figure 4-101 in the FEMDM.

•

The SU output is displayed in Data
Register display P, I, U, and L.

Eight Shift Parity

The internal (INT) SU bits (PO to 15) provided by the Eight Shift circuits are used

Eight Shift functions do not affect the parity.

as input data for the Shift Unit (SU).

Thus, the TDR parity bits are transferred

Data is fed through the SU either shifted

with the corresponding byte and become the

by 2 or 4 bits to the left or to the right, or

INT SU parity bits.

unshifted.

The parity bit of a byte set to zero by not

Bits shifted out of the halfword are lost,

No Shift and not Shift is forced on by circuits

while the additional bits are set to zeros.

Data is shifted on halfword basis.

2020 FETOM

(5/68)

2-75

IBM CONFIDENTIAl.

The output of the SU provides data to one
ALU entry.

for SLM, SRM, or MVHS (1, 2, 3).

The output of the SU can be

suppressed (set to zero) either partially

For SLM and SRM, the shift which shall be

or completeiy controlled by the Suppress

performed is specified in the micro.instruc.

circuits.

tion bits 5, 6, and 7 (OP REG bits 5, 6, or

Also circuits are provided to

standardize signs to test for correct sign

7).

Bit 5 on activates the Eight Shift control.

bit pattern and to test for packed decimal data.
The output of the SU is

Details of shift control signal generation

constantly displayed in the Data Register

are shown in fig. 4.101 in the FEMDM.

display (Customer console) E (P~ to 3),
S (4 to 7), T (PI to 11), and R (12 to 15).

For example the MVHS 1 causes generation
of the Shift Right by 4 signal during cycle 2.

Shift by 2 or 4
No Shift Control for ADDI
•

Shift by 2 or 4 is performed during SLM,
SRM and MVHS only.

•

Suppressing the No Shift 0.7 signal
causes forcing of ones into the high.

•

order SU byte.

A shift by any amount of bits to the left
has the effect that the respective binary

•

The highorder SU byte forced to ones

high order bits are lost and an equal number

allows extension of a negative imme.

of free binary low order bit positions are created.

diate data byte to a negative binary

These low order positions are set to zero.

halfword number.

A reverse situation occurs with the right shift.

•

A positive immediate data byte causes
suppressing of the highorder byte set

Shifting by 2 or 4 bits left or right is performed

to ones.

by AND switch combinations which are activated by
one of the four shift control signals (Figure
4-1~1,

FEMDM 2~2~ CPU):

For ADD! the control signal 'No Shift ~
to Tis suppressed. Since also no Shift by

Shift Left

by 2

Shift Left

by 4

2 or 4 signal is active during ADDI no control
signal affects the bits ¢ to 7. This condition

Shift Right by 2
Shift Right by 4

forces turning on the bits ¢ to 7 (hexadecimal
IFF/).

Only one of these signals is active at a time.

The SU bits ~ to 7 (highorder byte) forced

However, the shift by 2 or 4 can be com.
to ones extend the immediate data byte (lowbined with shift by 8, since Eight Shift and
order) to a negative binary number one halfSU operate independently.
word in length (IFF .. I)'L Since for ADD! the
The shift control signals are only generated
2-76

(5/68)

highorder byte in SU is -generally forced to

IBM CONFIDENTIAL

ones the suppress circuits are controlled

IDI

is accepted as a negative sign.

according to the sign bit (OP REG bitS) of
the immediate data byte. Sign bit off. indicating

Standard Sign

a positive binary value, causes suppressing

of SU bits 10 to 7. Since suppressed bits are
set to zeros the immediate data byte is extended

EBCDIC:

Standard Sign

ASCII:

by zeros which is true for a positive binary

- =

number.

Ici (111010)
IDI (11101)
I AI (1010)
IBI (11011)

Sign bit on. indicating a negative binary value,

The three highorder bits of a standardized

allows that the bits 10 to 7 (forced to ones)

sign are similar for minus or plus. Thus,

are provided to the ALU. The immediate

for standardization the three highorder bits

data byte extended by ones

(IFF I)

represents

(SU bits 12, 13, 14) can be forced directly

a negative binary number one halfword in

depending upon the selected standard code

length. Addition of a negative value is similar

(EBCDIC =

to a subtraction.

selected code is defined by the ASCII latch

1110. ;

ASCII = 101.). The

turned on (ASCII) or off (EBCDIC). See
Normalize Sign

•

figure 4-100 in the FEMDM.

During SDS the packed decimal sign

(/AI

IF I)

provided by bits 12 to 15

The

10worder bit (SU bit 15) has to be

turned on or off to define a negative or

of the loworder INT SU byte is standardized

positive sign.

according to the selected code (ASCII or

The turning on or off of the loworder sign

EBCDIC).

bit is controlled by the Normalize Sign Bit
15 signal, which is active (negative) when the
sign is negative.

The NorITIalize Sign circuits are used to convert a packed deciITIal sign provided by the
INT SU bits 12 to 15 into the standard sign

Since all sign representations have the bit 12
turned on, only the bits 13 to 15 have to be
investigated to define the sign

polarity.

according to the selected code (EBCDIC or

The Normalize Sign Bit 15 signal is active

ASCII).

when INT SU bit 15 is present and either the
bit 14

(/DI, 11(01)

or the bit 13

(/B/,

The ciTcuits are active

1(011)

during the SDS micro-instruction (Normalize

characteristics of both negative signs,

Sign signal). Within the CPU the hexadecimal

and

values

IAI

The values
considered

IF I are accepted as valid signs.
IA/, Icl, lEI and IFI are
as positive signs, while IBI or
to

is off. This condition defines the

IDI,

IBI

only. The bit patterns of the positive

signs cannot activate the Normalize Sign Bit 15
signal and, thus, SU bit 15 is set to zero
for standardized positive signs.
2020 FETOM

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2-77

IBM CONFIDENTIAL
Normalizing Signs does not affect 'the parity

Test Sign

(number of turned on bits in the loworder byte)

lEI,.

with the only exception: Normalizing sign
Normalizing the sign

lEI

During SDS the TNT SU, bits 12 to 15 are
tested for representing a sign (/AI to

(three turned on

bits. 111¢) to the positive standard sign
or

•

IAI

•

Ici (two turned on bits, 1¢1¢ or 11¢¢)

An invalid sign (/¢/ to

191)

IF I).

forces trap

request 2 by turning on the Data Error latch,

causes parity changing (PI) in the ALU parity
correction circuits.

•

The Data Error Latch is sensed and reset
by a CPU SENSE

116/.

Note that Normalize Sign forces the SU bits
12 to 15 to ones by preventing the No Shift

During SDS (cycle ¢ if DD type, cycle 1 .

functions (No Shift 8-15 signal active) for

if DX type) the TNT SU Bits 12 to 15 are

these bits. The turned on bits 13 to 15 are

tested for representing a valid sign (any

proVided to AND switches which are controlled

hexadecimal value from

by the Normalize Sign circuits while the turned
on bits 12 (common for all signs) directly

I AI

An invalid sign (any value

to /F I).

I¢I

19/)

prevents

activating the signal Bits 12-15 Sign A to F.

becomes SU bit 12.

This signal inactive during cycle ¢ or cycle 1
if the SDS instruction is in process turns on

Suppress

the Data Error latch at T 6 (delta cycle 1
or 2 overlaps with cycle ¢ or 1).

The SU output can be suppressed in groups of
The active Data Error latch forces a trap

4 .or 2 bits.

request 2. Trap request 2 forces a circuit
These groups are:

controlled branch (change of LS zone addressing)

SU Bits ¢ 1 2 3

to a micro-program routine. During this
456 7

1161

routine a SENSE

8 9

10 11

investigates for the

trap request cause. The active Data Error
12 13
14 15

latch sets the bit 11 in the sensed byte. During
the SENSE

Thus. six suppress signals are available, named
according to the bit groups affected (eg. Suppress
4-7, Suppress 12-13 and so on), Suppressed

1161

the Data Error latch is reset at

T8. Beside SENSE /16/ the Data Error latch
can be reset by stopping the CPU (Process
drops) .

bits (groups) are forced to zeros.
The six suppress signals are provided by the

Test Packed Byte

Suppress Control (Figure 4-1¢1, FEMDM 2¢2¢
CPU). They are generated depending on the

During packed decimal operations (AP, SP,

basic operation to be executed and correspond

ZAP, PPC) the two packed decimal digits

with the cycle periods (Tl to TS).

provided in the loworder byte (INT SU bits

2-78

(5/68)

IBM CONFIDENTIAL

8 to 11 and 12 to 15) are investigated to be
valid (hexadecimal values

IrJI

19/).

If the

SU shift or suppress functions affect only
data bits (rJ to 7, 8 to 15). The SU parity is

two digits are valid the signals Bits 8 to 11

predicted in the ALU parity correction circuits

Sign A - F and Bits 12 to 15 Sign A - F

depending on the executed function (Shift Suppress).

are inactive.

The SU parity is used for SU display (DR - E,

When one of these signals is active during

S, T. R) and to determine the ALU parity.

cycle rJ (DX or XX type), cycle 1 (DD or XD

Remember the general parity rule:

type), or cycle 2 the Data Error latch turns

Changing the status (on to off, off to on) of

on and forces a trap request 2.

an odd number of bits in a byte requires
changing the parity bit.

Data Bus Output

The status of bits can be changed in the SU
either by shifting or by suppressing. For

During a CTRL instruction the INT SU bits
P1 to 15, which derive either from TDR

Normalize Sign operations only) standardizing
the sign

lEI

affects the parity (P1).

highorder byte (after shift by 8) or from
the TDR loworder byte (No shift) are provided
to the Data Bus (P1 to 15). The Data Bus
provides the CTRL data to the attachments,
channels or control features. Note that the
INT SU bits P1 to 15 are provided to the
Data Bus as long as the CTRL instruction is

The INT SU bits prJ to 7 and P1 to 15 (Eight
Shift result) are parity checked to ensure
correct SU input parity. If the INT SU bits
are of correct parity the signals Shift Unit
rJ - 7 odd parity and Shift Unit 8 - 15 odd
parity are active (negative).

placed in the OP REG. (T1, cycle rJ until T1,

Incorrect (even) parity of any INT SU bytes

cycle rJ of the next micro-instruction) .

turns on the SU Check latch except for
CPU SENSE instructions, MANOP's, or

Shift Unit Parity

•

ICFL SENSES.

To ensure correct SU input parity the TNT
SU bits PrJ to 15 are checked (SU check)

The SU Check latch on causes stopping the
CPU one cycle after the cycle in which the
check occured. The active SU Check latch

•

Shift by 2 or 4 and Suppress require changing
of the input parity when an odd number of

illuminates the SU Check indicator on the
CE console.

turned on bits in the highorder or loworder
During TRBS, cycle 0, the signal which

byte are affected.

indicates correct parity for the highorder

•

Standardizing Sign

lEI

(plus) always changes

the parity of the loworder byte.

byte

to 7) is forced to prevent SU check

caused by the transferred FDR bits 8 to 11

2020 FETOM

(5/68)

2-79

•

(forced to zeros by Invert Switch) which are
only needed to correct the Invert Switch parity Pl.

ALU Carry bit 8 indicates a carry for
byte operations, while AL U carry bit 0
indicates a carry for binary halfword

The XOR-Iogic combinations which provide the

operations.

SU check signals (Shift Unit ~ - 7 or 8 - 15
odd parity) also provide signals which define

•

the number of turned on bits of specified bit

An ALU carry turns on the Carry and
AUX Carry latch.

groups.
These signals are:

•

AUX Carry Latch on causes Additional
Carry into the unit bit cell (15) during

highorder INT SU byte
Odd
Odd
Odd
Odd

SU
SU
SU
SU

_-3

Bits
Bits 4-7
Bits 6-7
Bits _-3 x

loworder INT SU byte
Odd
Odd
Odd
Odd

SU
SU
SU
SU

Bits 8-11
Bits 12-15
Bits 8- 9
Bits 4- 7 x

•

Odd SU Bits

is fed back to theUliti position of the

8-7 x
or

A carry out of the high order or loworder byte during logical operations

or 12-15

or 8-11
Odd SU Bits ~-1 x
or ~8- 9

the next Add operation.

corresponding byte for parity correc-

14-15

tion,s only.
This signals are used according to a shift
by 2 or 4 or a suppress function to decide

•

During arithmetic

or logical oper-

ations a odd number of carries out of

wether the parity must be changed (odd number

the bit positions within a byte changes

of turned on bits affected) or not (even numbet

the parity predicted by the SU and In-

of turned on bits affected).

vert Switch parity.

•
ARITHMETIC - LOGIC UNIT

The ALU output (Sum bits) is parity
checked to ensure correct ALU operations.

•

The ALU performs ADD, AND, OR, or XOR
using the SU and invert Switch halfwords.

•

Depending upon the ALU result the
signals ALU Zero or ALU Not Zero
turn

•

on.

XOR is the basic operation the ALU
is prepared for if no Adder, AND, or
OR gate is active.

•

For binary, logical and packed decimal
instructions the four condition code
latches are set according to the ALU

The ALU consists of 16 ALU cells
! ..which

perform the ALU operations for

one bit position.

2-80

(5/68)

result condition.
The Arithmetic-Logic Unit (ALU) can execute four different functions using the half-'

11M CONFIDENTIAL

word operands provided by the SU output

output of a c ell to the carry input of the

and the Invert Switch output.

next highorder cell.

The four functions are:
Adding (Add)

Take into consideration that an ALU cell

ANDing (AND)

can provide a carry also during AND, OR, or

~Ring

(OR)

Exclusive ~Ring (XOR)

XOR, however since the Adder gate is inactive
the next cell does not accept this carry.

The function to be performed is defined

The carries out of a byte or an halfword

by a control gate generated in the ALU

are provided by the carry output

control circuits.

cell 8 or ALU cell 0 respectively. These

of ALU

carries are defined as ALU Carry bits 8
Only three gates, Adder gate, AND gate,

or O. ALU Carry bit 8 is used during packed

and OR gate, are generated depending upon

decimal instructions (AP, SP,

the basic operations to be executed. Ex-

while ALU Carry bit 0 is used during binary

clusive

~Ring

is performed when no gate

ZAP,

PPC),

halfword instructions (AHSC, SHSC).

is active (general condition). The gates are

The ALU Carry bit 8 and 12 are used to

timed by cycle periods (Tl to T8).

control six correct functions, which are

Basically the ALU consists of 16 similar
circuits named ALU Cells 0 to 15. Since
the ALU cells operate similar it is only
necessary to understand the function of
one of them.
An ,ALU cell performs the same functions
(Add, AND, OR, XOR) as the complete
ALU does, but on bit basis.
The three inputs of cell are:
SU bit
Invert Switch bit
Carry

necessary to correct hexadecimal values
(/A/ to /F /) during packed decimal operations to obtain valid packed decimal values

(/0/ to /9/).
The carry input of the ALU Cell
15 is activated by the Additional Carry.
The Additional Carry' occurs as complement
correction (inverted data plus one) during
the subtract operations of SH or CLC (Inject one to ALU) or caused by the active
AUXiliary Carry latch. The AUX Carry
latch turns on at T2 (Reset/Set) during
cycle 0 or 1 when the Carry latch has been

The two outputs of a cell are:
Sum bit
Carry

turned on either by ALU Carry 8 or 0 during
the previous instruction or operation
(repetitions if ALC).

The ALU Cell operating principles for
Add, AND, OR and XOR are shown in figure

During the logical operations (AND, OR,

4_111, 2020 CPU FEMDM.

XOR ; Adder gate inactive), the Additional

The ALU cells are chained to process half_

Carry as well as the Carry into Position

words or bytes by connecting the carry

7 are activated by feeding back the carries
2020 FETOM

(5/68)

2-81

IBM CONFIDENTIAL
(ALU Carry 8 or 0) to the unit position of

active ALU Check latch illuminates the

the loworder or highorder byte. Since the

ALU Check indicator on the CE console and

Adder gate is inactive, the feed back carries

stops the CPU after the next cycle.

do not influence the result (Sum bits) but

During CPU SENSES (provide SENSE data

they are necessary for par.ity correction

without parity) the Prevent ALU and SU

during logical operations.

Check signal is active. This- signal blocks

During the binary arithmetic instructions

the parity bit!!! provided by the correction

(AH, AHSC, SH, SHSC), the carry into

circuits and allows generation of the ALU

the sign position (ALU Carry bit 1) are

bits PO and PI depending upon the Sum

used to recognize a

Bits Even signals only. Thus, the ALU

Binary Overflow. A

Binary Overflow activates Condition Code

operations are not checked, since the

(CC) latch 3.

parity is generated depending upon the

The parity bits PO and Pl of the ALU result

result and the parity is correct even if the

bytes (Sum bits

a to

7 and 8 to 15) are pre-

ALU as well as the SU and Invert Switch

dicted according to the Invert Switch (display

circuits function erroneously. The parity

I, P, U, L) and SU parity (display E, S,

bits of the SENSE data in FDR are correc-

T, R ; INT SU parity changed according

ted retroactive depending on the generated

to the performed SU functions).

parity bits at the ALU output. Corrections

The predicted ALU parity is changed when

are performed by either the signals Force

the signals Change Parity Sum Bits 9 to

FDR bit PO or PI or the signals Turn off

15 or 1 to 7 are active. The signals are

FDR bit PO or PI active.

activated if any ALU operation changes

The complete ALU result is displayed on

the status of an odd number of bits in one

the CE console when the CE Display Select

of the ALU bytes. The status change in-

switch is set to ALU.

formation is provided by the carry output

Depending upon the present ALU result

of the ALU cells. Thus, the carry outputs

the ALU Zero or ALU Not Zero signal is

are connected to a XOR combination

generated.

(one for each byte), the output of which

The halfword at ALU output is provided

provide the Change parity signal if the

to the input of SAR LS, FDR, and Inhibit.

status changes are odd.

The Condition Code latches (CC latches

At the ALU output the signals Sum Bits

a to 3) are set according to the result con-

a to 7 Even and Sum Bits 8 to 15 Even are

dition either unconditional (AP, SP,

activated depending upon the number of

PPC) or controlled by the CC bit (OPREG

turned on bits in the highorder or loworder

bit 6) in the micro instruction.

result byte. The Sum Bits Even signals

(AH, AHSC, SH, SHSC, AND, OR, XOR,

are compared with the corresponding cor-

CLC).

rected parity bits and the ALU Check latch

The condition code is accessible by a SENSE in-

turns on if even parity is recognized. The

struction.

2-82

(5/68)

ZAP,

IBM CONFIDENlfAL
the input bit, the Ioworder bits (15 and 11)

Six Correction Circuits

are not affected by the Six Correction.

•
•

Six Correction effects only the two four-

A performed six correction influences the

bit digits of the loworder ALU result

parity of the Ioworder ALU byte (Change

byte.

Parity Sum Bits 9 to 15).

Six Correction can be considered as
a binary adder which adds the constant '- 6' to the digit to be corrected.

ALU Parity Prediction and Correction
•

•

Six Correction influences the ALU

The ALU result parity is predicted
depending upon the parity of both

parity correction.

ALU input operands.

The Six Correction Circuits are activated
for packed decimal instructions (AP, SP,
ZAP,

•

a change of the predicted parity.

pPC) only if the

Adder gate is active (cycle 2 or 3).

the

number of turned on bits odd, force

PPC), however, for the subtract-

type instructions (SP,

ALU operations which change

The ALU operations ADD, AND, OR, or

XOR affect the data bits 0 to 7 ( highorder
The Six Correction affects the two halfbytes of the loworder ALU byte. E.ach
hali byte is corrected by a separate
circuit.

ber of turned on data bits in both ALU result bytes (Sum bits 0 to 7 and 8 to 15) can
be even or odd. Thus, the Sum bits PO and

The Six Correction circuit can be considered
as a four bit binary adder which adds the
constant

byte) and 8 to 15 (Ioworder byte). The num-

'-6'

to the ALU result (two hexa-

decimal digits of the loworder byte). Six
Correction is performed when no carry
occurs out of the highorder bit of the corresponding halfbyte (No ALU Carry bit
12 or 8).

PI must be turned on or off to provide
always odd byte parity (odd number of turned
on Sum bits including parity bit).
The ALU result bytes are tested for proper
parity. Even parity in the highorder or
Ioworder byte turns on the ALU Check
latch and the CPU stops (Process Check).
To allow testing of ALU operations the
Sum parity bits PO and PI are predicted.

The constant' -6' expressed as a half byte

That means. the parity result is generated accor-

binary number is 1010. This binary number

ding to the parity of the ALU input operands and

is added to the halfbyte value repre-

predetermines the odd or even number of turned

sented by Sum Bits 12 to 15 or 8 to 11.

on data bits in the highorder or loworder result

Since the Ioworder bit of the constant is

byte.

zero and adding of zero does not influence

The predicted Sum parity bits are correct

2020 FETOM

(5/68)

2-83

IBM CONFIOENTIAL

when all turned on bits of the input operands

ever, adding the two turned on bits causes

occur in the ALU result.

a zero in the corresponding result position.

Example:

A carry, which can be assumed as one

1 1 1 1 0 0 0 0 Operand 1

0 0

turned on bit, occurs and turns on the bit

1 1 1 1 Operand 2

in the next higher position. One turned on
1 1 1 1 1 1 1 1 Result if ADD

input bit (odd number) has been lost and

Each operand provides four turned on data

the predicted parity bit (on) has to be changed

bits. To provide odd operand parity) both

(off).

parity bits must be on .. The parity bit on

During Adding a carry provided to an ALU

indicates an even number (four of turned

cell indicates the one input bit has been

on data bits in the corresponding byte.

lost. The predicted parity bit must be

The total number of turned on bits of both

changed when an odd number of bit carries

operand bytes (even or odd) is specified

occurs.

in Table 2-1:

AND

00000100

Since the Sum parity is predicted upon the
total number of input data bits, the predic-

01010100

Result

00000100

tion has to be changed (corrected) when an
The total number of turned on input bits

odd number of turned on data bits is lost
caused by the executed ALU function (Add,

is even (odd plus odd). The predicted parity
bit is on. However, an odd number of turned

AND, OR, XOR)

input bits is lost (three) and the predicted
parity bit has to be changed.

Examples:
ADD

Result

o0
o0

0 0 000 1

0 0 001 0

0 0 000 1

01010100
00000100

Result

01010100

The total number of input data bits is two

The predicted parity bit is on (even num-

(even) ; thus, the predicted parity bit has

ber of input bits). One of the opposite turned

been turned on to provide odd parity. How-

on bits is lost (odd number). The predicted

Table 2-1

Turned On Bits of Even and Odd Operand Bytes

Operand 1

Operand 2

Total of turned on data bits

P=1 (even)

P= 1 (even)

Even (even plus even = even)

P=O (odd)

Even (odd plus odd = even)

P=l (even)

P=O (odd)

Odd (even plus odd = odd)

P=O (odd)

P=l (even)

Odd (odd plus even = odd)

•

2-84

(S/68)

IBM CONFIDENTIAL

parity bit has to be changed.
XOR

to activate the carry output (input of the

100 1 100 1

next cell) even for the logical ALU func-

000 0 100 1

tions (AND, OR), when bits ar e lost. A
logical carry is not accepted by the next

100 1 000 0

Result

ALU cell

The predicted parity bit is on (even num_

For XORing no carry is generated since

ber of turned on input bits).

this function always affects an even number

No change of the predicted parity is re-

of turned on bits and no correction of the

quired since four (even) bits are lost.

predicted parity bits is necessary.

No.te that for XOR the predicted parity is

Figure 2-J,9

always correct since XOR operations affect

of the four possible ALU functions.

only even numbers of turned on input bits.

The predicted parity bit must be corrected

During Add operations changing of the total

when an odd number of bit carries occur

number of input bits is indicated by a carry

within a byte. To detect an odd number of

into the next higher ALU cell. Note that

carries the eight carry inputs within an

a carry into the unit position (cell 15 or 7)

ALU byte are connected to a XOR com-

of one of the ALU bytes (Additional Carry,

b ination.

Carry into Position 7) also affects the num_

The XOR combination provides the Change

ber of turned on bits of the corresponding

Parity signal (Change Parity Sum Bits 9

byte. The ALU cell circuitsare designed

to 15, Change Parity Sum Bits 1 to 7).

ALL/ Cell

.sU

e; t.

J.
.I.

¢
J.

:", :> ...

l .. vert5we~t

shows the carry conditions

(~lrl'~

V
V
/

~
J..
---.

AD])

AN])

OR.

'x'o~

CA~P.Y

C~RR""

--CARR'f
1-------

-----

.J.

CARRY

1..

CARfly

J..

.1.

CA I<~)'

CA~Qy

CA~~'t

._--_._-_ _._-._'-Note: : A QH.'J

HnC\+

always :\lJol;CC\!es

OVlC

;l/lpuJ bit-

h.J.~Vle.4 0'-1
hQS

ioeeV) Los/-,

2020 FETOM

(5/68)

2-85

IBM CONFIDENTIAL
Note that for logical ALU functions (AND,

Change Parity XOR combination of the

OR) the carries out of the highorder ALU

loworder ALU byte.

cell of each byte are fed back to the unit
positions. This feed back is necessary to
recognize the carries of all eight cells for
parity correction.

Condition Code Latches

Correction of the Predicted Parity if Six

•

The Condition Code Latches are set
to reflect the ALU result conditions.

Correction
Six Correction is required for packed de-'
cimaloperations. The constant

1-6 1

•

(1010)

For binary and logical micro-instruction, the condition code is set when the
CC bit in the instruction is on.

is added to the ALU result. Six Correction
affects only the two four bit (hexadecimal)
digits in the loworder byte (8 to 11 and 12

•

The condition code is set uncondition-

to IS).

ally for packed decimal micro-in-

Correction of the predicted parity bit (PI)

structions.

is necessary when the six correction changes
the number of turned on Sum bits uneven.
The total number of turned on Sum bits is
changed from odd to even or even to odd
only when adding the constant 1010 (-6)
to the hexadecimal values /2/, /3/, /A/
and /B/.
Adding the constant 1010 affects only the
three highorder bits of the hexadecimal digit
since the loworder bit of the constant is zero.
Thus, six correction can be considered as
an addition of three bit digits (constant 101).
The three highorder bits of /2/ and /3/
are 001, while the three highorder bits of

The Condition Code (CC) latches are shown
in figure 4-113 , 2020 CPU FEMDM.
The CC Latches are set during Binary,
Logical and Packed Decimal micro-instructions (CC-instructions) according to the
final operation result (ALU result).
The saved result condition can be tested
by SENSE /10/. A turned on CC latch
(0 to 3) turns on the corresponding bit
(8 to 11) in the sensed data byte set into
FDR.
Beside CC-instruction the CC latches are
set by CTRL /10/ controlled by the INT
SU bits 12 to 15 turned on.

/A/ and /B/ are 101.
Both three bit digits show the bit combi-

Set CC and Carry

nation identifies the only hexadecimal

The Set CC and Carry signal, active for

digits which cause an odd change of the

cycle 2, cycle 3, or delta cycle 0, is

number of turned on Sum bits when adding

generated according to the type of the CC-

the constant. Thus, a signal is generated

instruction (DD, DK, XD, XX) and speci-

depending upon 01, which influences the

fies the cycle (delta cycle) during which the

2-86

(5/68)

IBM CONFIDENTIAL

final result is present at ALU output.

the CC bit (bit 6) in the instruction is on (I).
Set CC and Carry and Allow CC Setting

Allow CC Setting

(Latch) active enable turning on the CC

The second condition, necessary to activate

latches at delta T8 (reset/set).

the CC latches, is the Allow CC Setting

Allow CC Setting is prevented for CC-

Latch turned on. This latch is set at T7

instructions with ALC when the final con-

(reset at every T6) either for packed de-

dition is saved in the CC Latches (e. g. ,

cimal micro-instructions (AP, SP,

AP, ALC, result not zero; CCI active)

ZAP,

PPC) or for binary or logical instructions

while the ALC operation is still not term-

(AH, AHSC, SH, SHSC, AND,

inated (field length not decreased below

OR, XOR,

CLC) but for the last instructions only if

zero).

2020 FETOM

(5/68)

2-87

IBM CONFIDENTIAL
I/O BUS OUT AND IN

as an additional attachment in respect to
the bus termination.

•

The I/O Bus connects the CPU with all
present attachments.

I/O BUS OUT
A comprehensive representation of all bus

The I/O control units are attached to the

lines leaving CPU is given in figure 2-1~

CPU by bus lines.

The following sections describe the I/O

The cycle steal control lines, and the bus

Bus output control shown in the FEMDM,

lines are the only way to send or receive

2020 CPU, Figure 4-120. This figure shows

informations from the I/O control units.

the Address and Data Bus control as well
as the generation of the control strobes for

The bus lines can be divided into three ca-

SENSE and CTRL functions. The other

tegories :

control Lines leaving CPU are shown in

Address Bus

the circuits where they are generated.

Data Bus

Control bus lines

There are two types of bus lines specified

Address Bus Out

by the bus termination in the attachments.
Bus lines terminated by a line sense ampli-

•

Address for CTRL or SENSE.

fier (LSA) are defined as type A. Bus lines
type A are used to provide CPU information
to the attachments with a minimum of delay

The Address Bus provides the Device

•

A Device Address can be applied from
the micro-instruction or from switches.

time. This bus type cannot use the sent informations from the attachments to the CPU
(e. g., Address Bus).
Type B bus lines are those which accept

•

For I/O Display the Device Address is
set up in the CE Select switches 1 and 2.

informations either in the attachments or

The Address Bus, consisting of eight single

in the CPU (e. g. , Data Bus). These type

bus lines (bits 8 to 15), provides the Device

B bus lines are terminated by an Inverter-

Addresses to the attachments for SENSE

OR-Inverter Logic which allows activating

and CTRL.

of the bus lines even in the attachments.

A device address consists of two hexadecimal

Since the Inverter - OR - Invert Logics

digits (one byte, eight bits) which are pro-

of all attachments are connected in series

vided either by the device address field in

the bus signal is delayed.

a SENSE or CTRL micro-instruction (OP

The CPU (I/O bus entry) can be considered

REG bits 8 to 15) or, especially during

2-88

(5/68)

I A D])R E5S

Bu ~

(b'lts 8 -1';»

SENSE Strobe.
SENSE Co~trol S~robe

C.fRl

strobe::

Sell)," e. Reser

I/O Clock 'Pulses 1. Q\Ild .t

DATA BuS

Two di«e.-e1lC\
blol.$ te....... ;

lSA

..--

LSA

r---

L5A

~--------------~>
(bits PI-is)

II"

Reser (ond; h'oV\

.5fec,ol Reset COVldih'o,,",
Power OVi Reset

Process Fl
UVtco",di~io\llQI
Pl'"ocess Heter

I
I

I/O Check ReS'e t-

Ch::c:;:.k Stof

I
I

L-alNip fest Sw:tcl.,
TherIoMa I Sw;tc"'l

o
z

::!!

~O--,R ~

m
Z

Reh...... S to cp....
~l--_ _ _ _ _...
y

I - ;""o"cqted

~~~:~:-:~~:;r

0:1

-t

l>
r-

co",d iho~

t- -- - -

cQ .... loec""'slcle r

cdQ..S two

~~~~~~~_ _ _ _ _ _ _ _~~~~~~~~~~~~~~~~~~ _ _ ~-~-----~~~~UW1~st6~~ikd~Q~rs.

L.-~~::.:.I.:::oc.:.:k~F:.li:e==e:!::::d~C=h:..!l~=k~_ _ _ _

CPL.l
N

o
o

"':i

~
N.
I

S;3"'0.1 L;", e to Cll.Y'q I/o

AH"Q.c.~"",-el.4tJ

F.·~\4re ~ -:t,

COIN\IMOIII

o"'l~

IBM CONFIDENTIAL

ICPL, by the values set up in the Data

Bus signal is active. This signal is acti-

switches land 2 on the customer console

vated when either a SENSE or CTRL micro-

(also placed into OP REG 8 to 15).

instruction (OP R Decode E or F) is placed

If no SENSE/CTRL and no ICPL operation

in the OP REG or when the IC PL Latch is

is being processed the Address Bus is

turned on during Initial Control Program

activated according to the values set up

Load.Note that for ICPL the device address

in the CE Select switches 1 and 2.

has to be /20/ and the Data switches must

The device address, consisting of an high-

be set up accordingly.

order and loworder hexadecimal digit can
be interpreted as follows:

I/O Display Address Out

The highorder digit (8 to 11) defines the

The contents of CE Select switches 1 and

called attachment. Since the number of

2 are used as Device Address (gated to the

possible attachments is limited, only the

bus) when the I/O Display Address Out

values /0/ to /A/ are valid.

signal is active. The I/O Display Address

The loworder digit (12 to 15) can vary bet_

Out signal is active during T4 to T7 when

ween /0/ and /F/ without changing the high-

no SENSE or CTRL function is required

order digit. Thus, it can be said, that each

(no OP REG to Address Bus signal active).

highorder digit (attachment) address can

Note that this signal is active even if the

be extended by 16 sub-addresses.

CPU has been stopped and allows the CE

However, each of the 16 addresses (device

to display (CE console) I/O sense inform-

addresses) relating to one attachment allow

ation by selecting any required device address

controlling or sensing .of eight different

using the CE Select switches 1 and 2.

functions or conditions in the specified

Depending upon the timing signal T4 to

attachment (highorder digit) by means of the

T7, the signals I/O Display Address Out

eight Data Bus bits. Thus, each attachment

and OP REG to Address Bus are generated

address (highorder digit) provides the possi-

alternating.

bility to test (SENSE) or to control (CTRL)

address which derives from the OP REG bit

128 (16 times 8) different attachment func-

8 to 15 is ;neffective since the I/O display

tions.

functions are timed by T4 to T7 only.

. . . . . . .Ie!*.

The undefined

The as signment of the pos sible highorder
digits in relation to the attachments is
given in figu;re 2 -

Data Bus Out

,,£.
•

During CTRL operations the Data Bus
carries the control bits.

OP REG to Address Bus
The OP ~EG bits 8 to 15 are gated to the
Address Bus when the OP REG to Address
2-90

(5/68)

•

During all CPU operations other than
CTRL's and during CPU stop the Data
Bus parity bit PI is forced.

H;5L,o"'de.~ dev'·QC,.
aclct~e.~

SENSE

crRL-..

oI,',:t

/~/

Test for TrQlP
Req .....cst S~~e

/ l/

(I/O)

R.eset or SetPL A.E6 (CPLA)

CPU

/~/

Se~;tJtI.

RcadI PlAke"" .1StJJ./~5J.tJ /~S~t1, J.1l1t2.
( CArd I/O Co~o~l

/J/

./52, I.2S~fJJ

Iltl

.J't~J

/2<,J
OJ

::I

/S/

~t::.se,,"'#4

1'1

ztPC

:!!
o
m

oz
Z

-I

III

.ffo,.a3e COIA/yol

11'1
I~/

/A/

N
I

....

'l>

»
,....

~Qf,..,.~

At::.se,..,.~t:/

(/¢ ... .s/)
(If ... iIJ

~fOe 1ttJ;,ilt~

Sloe

BSC,4-

2.1..
h~l4,.e .t -4

AS5'{j"",,,,,~,,,t ell""

J>e..icc !/-ddr-,ess lJ1j,r

Hrjt.()rd~Y

IBM CONFIDENTIAL
The only operations which require to send

CPU (see I/O BUS IN), the forced Data

out data from the CPU to the attachments

Bus bit PI has to be changed according to

are the CTRL micro-instructions and

the parity of the sensed data byte. The prin-

ICPL. However, during ICPL the CTRL

ciples of this parity change is given in

functions are performed during cycle 0

figure 2

-ti.

and 1 only.
The OPR Decode F signal, generated depending upon the four highorder bits of the

Control Strobes for SENSE and CTRL

CTRL instruction in the OP REG, gates
the INT SU bit. 8 to 15 to the Data Bus.

•

During SENSE operations, functions

The parity bit PI is provided by the SU

within the attachments are controlled

Parity Correction circuits and is similar

by the SENSE Strobe (T3) and by the

to that bit PI displayed in Data Register

SENSE Control Strobe (delta T8).

(DR-) U on the customer console.
During ICPL, cycle 0 and 1 (ICPL CTRL)
the Data Bus bits are forced by circuits
as shown in figure

•

within the attachments are controlled

2-21.

Since the Data switches are set to

During C TRL operations, functions

by the Sense Reset pulse (T3) and by

/20/,

the CTRL Strobe (delta T8),

the forced Data Bus bits control the same
attachment functions as for a CTRL

/20/

mic ro- instruction.

Four control signals (strobes) are generated within the CPU w.hich are sent out to the attachments
via bus lines. These signals are timing signals
which control the SENSE or CTRL functions in
the attachments in relation to CPU processing

Data Bus Parity
For CTRL micro-instructions the bus

time.
These four signals are:

parity bit PI is provided by the SU parity
bit PI, which is similar to the INT SU
bit PI, since during CTRL no shift unit
functions are performed.
During ICPL CTRL the parity bit PI is also

Sense Reset

(CTRL only)

CTRL Strobe

(CTRL only)

SENSE Strobe

(SENSE only)

SENSE Control Strobe

(SENSE only)

forced by circuits according to the generated

Th ese control signals are gated to the

bit pattern.

attachments by Pror"IHO not CS (CPU ru.n-

During all other operations (also GPU stop)

ning but not cycle stealing) and the active

the Data Bus bit PI is forced unconditionally

Allow Strobe signal.

to provide always correct parity on the

Allow Strobe is active during SENSE, CTRL,

Data Bus.

and ICPL only. However, Allow Strobe is

Since the Data Bus is also used to transport

prevented during cycle 1 of indirect ad-

sensed data from the attachments to the

dres s ed SENSE or C TRL instruction. During

2-92

(5/68)

l¢
rCR

Col. 13;",}:1...

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Set

Reset/Set

ICPL/Ct¢

L-__

____

__- L________

.13

.1.2. .

________

____

CE Select S... .2 "/~I

rCPL/ CY.L

I
I

Cl>

1...

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I.?¢/ FI.t~h·OLA$G((,Lt;~ rCPt..-crRL.

IBM CONFIDENTIAL

A TTACHHENT

I
t>r':~C:f"4U

of l>QtCl BI.4.S 1UV'1't~ a.~~I""~

d"''':III~ I/O SENSE.

this cycle I the IAR updating of indirect

,SENSE Strobe and SENSE Control Strobe

addressed (ALC) I/O instructions is performed.
In addition, the Allow Strobe condition is
inhibited during indirect addressed CTRL

Both strobes are generated for SENSE and
ICPL

CY 2 (ICPL SENSE) only. The SENSE

instructions when delta CY2 overlaps with

Strobe, generated at T3 after the SENSE

CY O. No Allow Strobe during the overlapping

micro-instruction has been transferred

period prevents the CTRL strobe (delta

into the OP REG (OPR Decode E, CYO,

T8) during CY O. This is necessary since

TI) or at T3 during ICPL SENSE (CY 2),

the control bits are read out and set onto

allows setting/resetting of the Sense Re-

the Data Bus not earlier than during CY 2.

gisters by sense data. The source of the

Thus, the CTRL strobe is prevented and

sense data is defined by the device address

occurs at the end (delta T8) of CY 2 only.

on the Address Bus.

2-94

(5/68)

IBM CONFIDENTIAL
After the Sense Register has been set, the

rio Di.play

sense data is available on the Data Bus

•

and, thus, also at CPU Data Bus Entry.
This sense data is placed into FDR when
the SENSE Control Strobe (delta T8) becomes

rio Display allows to select and display
any SENSE data SOllrce in the attachment
during CPU run as well as during CPU
stop.

active. Beside the Data Bus Entry Control,
the SENSE Control Strobe is used within
the attachments to perform reset functions
(resets latches the conditions of which are

The I/O Display allows the CE to select

just have been sensed).
and display any required rio sense data
The SENSE Strobe affects the Sense Re-

source by a device address set up in the

gisters of all present attachments, but sense

CE Select switches

data is provided to only one of them (Sense

Display functions when the CPU stops as

well as during CPU run, but not during

highorder digit of the device address). All

SENSE or CTRL. The Display Sense Strobe

other Sense registers are set to zero since

generated at T6, activates the SENSE

no sense data is provided.

Strobe which controls the Sense Registers

Sense data remains in the Sense Register

in the attachments.

until the next SENSE or C TRL instruction

Since the Display Sense Strobe occurs for

is executed.

each cycle (T6 to T6) the sense data source

1 and 2. This I/O

is tested in a rate which corresponds with
the CPU processing speed (every 2 or 3.6
microseconds).
Sense Reset and CTRL Strobe

The rio Display Latch, which is only reset
for SENSE, CTRL, rCPL and CPU LOG
in, gates the I/O Bus Entry (Data Bus

Both signals are generated for CTRL and

entry) to the display (PI to 15) on the CE

ICPL CTRL (CY 0 and CY 1) only.

console, but only when the CE Display Se-

The Sense Reset signal, generated at T3,

lect Switch is set to I/O Display.

resets all Sense Registers in the attach-

The sense information, which illuminates

ments to clear the Data Bus for the control

the indicators can also be used to generate

bits.

the Equal Synch signal (Test Hub) or, if the

The CTRL Strobe, generated at delta T8,

CE Compare Stop switch is turned on, to

is the timing signal which controls the

stop CPU depending upon I/O conditions.

functions in the attachment defined by the

For Equal Synch or Compare Stop the sensed

device address and the control bits on the

data byte is compared against the byte

Data Bus.

setup in the CE Select switches 3 and 4.

2020 FETOM

(5/68)

2-95

IBM CONFIDENTIAL
I/O Bus Powering

SENSES (I/O Address 1 x, MANOP Inbus
to FDR) at T4. During I/O SENSES (Device

The bus lines type A (LSA termination) require

Addresses 0 x, 2 x to A x) and all CTRL

additional powering.

operations (CPU, I/O ICPL) the Address

For this powering. the bus

lines enter the CPU and leave it again after power-

Bus is gated into FDR at T4, but the Data

ing.

Bus is accepted at delta T8. The later

This amplification divides the complete bus

into halves. which are identified with the letters A

acceptance of Data Bus in relation to Address Bus

(bus before powering) and B (bus after powering).

(T4) is based on the Data Bus delay caused by the
bus termination type B.
Especially for direct addressed I/O SENSES
the Data Bus is gated simultaneously into
FDR and into the loworder byte of the speci-

I/O BUS IN

fied LS register at delta T8. To provide

A comprehensive representation of all bus

correct parity in the highorder byte of the

lines entering the CPU is given in figure

LS register, the parity bit PO is forced.

-.2,.

The following sections describe

the I/O Bus input shown in the FEMDM,
2020 CPU, figure 4-121. This figure shows
the Data and Address Bus input controls

CPU SENSE

as well as the CPU SENSE circuits.

•

CPU SENSES are specified by Device
Addresses with the highorder hexadecimal digit = /1/.

Bus in Control

•

SENSES /14/ and /15/ are the only
halfword SENSES.

Data and Address Bus are set into
FDR by I/O Bus to FDR signals.
•

•

I/O SENSE, direct addressing, places
the Data Bus Information directly into

CPU SENSE data is applied without
parity bits and, thus, the Prevent
ALU and SU check signal is generated.

the loworder byte of the specified LS

CPU SENSES are identified by Device Ad-

dressec (on Addl~cSS Bu~), the highorder

hexadecimal digit of which is /1/ (Address
Bus bits 8 to 11 = 0001). This condition causes
Address and Data Bus are gated into FDR

the I/O Address 1 x signal.

by the signals I/O Bus to FDR 0-7 (Address

The I/O Address 1 x signal specifies in

Bus) and I/O Bus to FDR 8-15 (Data Bus).

connection with the Address Bus bits 13

These signals are generated for CPU

to 15 any SENSE between /10/ and /16/.

2-96

(5/68)

IBM CONFIDENTIAL

DATA

BUS

-»- - A 1)]) RES,s

au s

PL
T\"Qp Reql.les'tL;Vlesl-1-

>--t-_______________......._____~3~-..!..1_J_-~J.:.:.-7-~

'REG

.1.-1-

ICPL
r-------<~

BUS U\llb"ffe~ I/O Ba.L,~

RUM

COIev;ce l, 2,3,4)

Read

I.o.to.

Out

IGo.-Ie

ouT

f/;-1
C S :J)A TA

I
i

CPU C'fCLE STEt\L

CONTROLJ

1---. _ _ _ _ _ . _ _ .

I
I

--~

+ CS I","';b;t Cned:.

+C.S

-t

I
I

N
t4

a »ATA lJuS

_-+-<--CSl>atq't'I Bits 11-15

CPl,,(

MAIN

Bus

I
I

0:1

3:
()

o
Z

orn
Z

-I

'B~'1

CONFIDENTIAL

The CS Data Bus, able to transport one half-

still present lower priority requests.

word (two bytes including parity bits), con-

During CS operations data address and field

nects the cycle steal units directly with the

length are available in fixed LS registers.

Main Storage output (SDR) or input (Inhibit).

Each CS device has its own data address

The CS Data Bus is used either to provide

and field length register (figure

data from the CPU to the cycle Steal units

These registers are selected by X-addresses

or vice versa. The data direction is con-

and Select LS- Y signals which are generated

trolled by the CS Data Out gates or by the

depending upon the active highest priority

CS store signals. Gates and signals are

CS Request Latch.

2-1.6 ).

generated within the CPU CS control.
Especially for byte transfer from or to the

Any CS Request

CS units the byte not affected is directly
regenerated (Force Regen) by connecting
the SDR to the Inhibit. The CS control bus
lines entering CPU control the CPU CS
control circuit according to the CS operation ordered by the CS unit.

Any active CS Request Latch forces the main
control signal Any CS Request. This signal is active from T3 until the end of T2.
The offset for one T-period between the
active CS Request Latch (T2 to TI) and the

The CS control bus lines leaving CPU in-

Any CS Request signal (T3 to T2) is achieved

form the requesting CS unit about the pre-

by controlling the signal during T2 depen-

sent CPU conditions.

ding upon the Cycle Steal latch. Any MAN0p blocks Any CS Request.

Within the CPU CS control circuits Any
CS REQUEST

CS Request controls resetting and setting

The CS Request Lines Device 1 to 4, ac-

of the control latches.

tivated within the CS units, tUrn on the CS

Within the CPU circuits Any CS Request

Request Latches 1 to 4 gated by the Sense

controls the following main function and

CS Request signal. This signal is identical

signals:

with T2 and is also used to reset the CS

Addressing of fixed CS registers in

Request Latches. Thus, a CS Request latch

Local Store (depending upon requesting

remains active for the period T2 to T1.

device) at T 5 and T7 , TS and T2.

If more than one CS Request is active at

the same time, all corresponding CS Re-

Generation of LS

!"e~d sig~ale

quest latches are set. During the following

to SAR (T5) and LS to MAR (T5, TS)

CS cycle only the highest priority request

as well as the LS Write signal at

is effective and the request source (latch)

T7 and T2.

of the corresponding CS unit is reset. At
next T2 all CS Request latches are reset,
but they are set again depending upon the
2-102

(5/68)

Blocking of delta cycle advancing
(Long Time Clock) at T4.

lS
1
stor.c-+rol J.

IOC.
~~tQ

A<*:ly-

(

6SCA
lo.to. AoIdlBScA

F~tlle1..~+t.

Stor.Co....... 1 t

J>a.to Add I"
SIo~Co ...trol

F~le~

Add ...

s......C4....h-ol.L.

F;e1d I...e~

F.'elcl telAllt'"

I
lAo R.

])o.to.

roc.

tAR

Delta Process not CS Request.

LA~

by dropping the Process not CS and the
Process without Check and CS signals.

Delta Process without Check and
CS Request.

Activating of the Set up Run Condition

DEVICE SELECTION

gate to start CPU if a CS request
during CPU stop.

The Device Selection consists of two latches
(CS Device 3 or 4, CS Device Z or 3) which
are reset/set at T6, according to the highest priority CS request when Any CS Re-

CYCLE STEAL LATCH

quest is active.
The outputs of the two latches, gated by the

The Cycle Steal Latch is active if Any CS

active Cycle Steal Latch, are decoded and

Request occurs from T6 (pulse B) until

generate the CS Select (Device 1, 2, 3, or

T6 (pulse B). This period agrees with the

4) signal, which is sent to the requesting

core storage cycle (stolen cycle) (T6 to

CS unit.

T6) and defines the time at which CS data

The two device selection latches save the

transfer is possible. In main, the Cycle

CS request information of the CS Request

Steal Latch is used to block CPU functions

Latches, which are already reset at the next

2020 FETOM

(5/68)

2-103

IBM

CONFlDENTlJ~L

T2 (Sense CS Request), to be available
during the cycle steal pe~iod (figure

2-.1' ).

A CS operation can either be a read operation or a write operation. Both control
signals active or inactive indicate an error
and cause a CS Interface Check.
The CS Read latch is reset at T6 when Any

CS CONTROL

CS Request is active and it is set again
at T7, but only when CS Read is active.

A CS operation initiated by a CS Request

For CS Write the CS Read Latch remains

is defined in detail by the CS control lines

off.

activated in the requesting CS unit.
The six CS control lines are as follows:

CS Read
CS Write

CS Halfword/CS Byte
The control signal CS Halfword or CS Byte

CS Halfword

defines the data format which is transferred

CS Byte

either during CS Read or CS Write.

CS Increment
CS Decrement

Similar to CS Read/CS Write both control
signals are exclusive and a CS Interface
Check occurs if both signals are on or off

Each CS unit (device) provides its control

simultaneously.

signals via separate bus lines. Only the
six control bus lines of the highest priority

CS· Halfword active turns on the CS Half.

CS unit, causing a CS request, are gated

word latch at T7. The Latch has been reset,

to the CPU CS control circuits.

similar to the CS Read Latch, at T6 before.
The CS Halfword Latch remains off when
CS Byte is active.

CS Read / CS Write

The CS Read or CS Write control signal

CS Increment / CS Decrement

defines the CS data direction. For CS
Read,data is transferred from the CS unit

The control signal CS Increment or CS

to the CPU core storage, while for CS

Decrement define the processing direction

Write,data is transferred from core

of the CS data field in the CPU core stor.

storage to the CS unit. Note that for CS

age.

operations the terms Read and Write re-

Byte, the data address (LS register) is

flect the I/O operations instead the core

either incremented or decremented by 2

storage operations.

or by 1.

2-104

(5/68)

Depending upon CS Halfword or CS

11 T~ I .3 I T'i I ,5 i :r' 1T1 I.g I T.L 1T.2 I T3 I 'T"1i I TS I Tb I <
C S Re9 ....crl{CSuVlit)

fI':'----------- ~t b~

CS Seleet

1.2.

5el'lse. CS Re~l.(est

~tf5ll_-----------A!set/.5cst
Not
: c.s f'1-:
•I es r-L I
:--~-I~............~i..............·'....,
I

l>-_tJ<'~tT" .... be8
~f~·~i......-

C,:!cle S tea.l 1= L
.

CS Select Lo.tcl.,c.$

j::::

= prece~ :ne";cc:._

T',p",lse B

........................

Re~/~t

l&..e

'{re

-=_:,i,J.TWjbr.l'p.... 8......._ . ._ _ _ _ _ _ _. . . . . . . ._ . . . .

IM O';V*SIA ...

t; llole>"'/~H4Ie{ 111

AAe CS lit lAd ih.lf·

________________s.,/ft T2 IAIItJ

Re,~u~.$t

4o."'l!Tb(JI) . .lIIIIiIIIiiilliiil_liIilIlIliillilllliilliliilllilllllllllllllillllilllll_ _ _ _ _
"r~

.Tg -

- T7

"'ot It

a ....d~(B)

7'3

G LS to HAl?
1-

=•• J7

bo.t~
Addrl ___
F.~"
.. s"",
, ..
I __
__
_ _Il"a
_L.eiiiiiil.
___

HA I( cf>I..dew1$
l1oCi/:~r CiJ(.(trll' "t:r'lq Qdcl;~s:~

LI .,_ _ _ _ _ _ __
T~

tl'

te.Set

b~ VI~t

loS to f1~~

:.s;
o

()

...1

J.1 o41'~r CDkf"l

t. s

C.s Coc.< .... f.2r

U .. CS

fele! le ..,ft,

.s .T.6'_____T.3.
T1

t,j,.,'fl!.

~<.eY-(9

Ct>c."spb J /
ctVlcl kAR tl) J);S'f'o.~ CV3 prov;dc

....

#JeV10rlA.

LO& REG BITS

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p
-:;:::;

n
C'

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P¢

(JJ

......

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....
I

til

CUT HERE

__ -.1

Z33-1021-0

....

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....
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:;'

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b

International Business Machines Corporation
Field Engineering Division
112 East Post Road, White Plains, N. Y. 10601

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Z33 1021 0_2020_Processing_Unit_FETOM_May68 0 2020 Processing Unit FETOM May68

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