Z80000 CPU Preliminary Technical Manual Sep84

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Z80,OOOTM CPU

Preliminary
Technical Manual .

September 1984

Z80,OOOTM CPU

Preliminary
Technical Manual

7-i1APW

Zilog

Copyright 1984 by Zilog, Inc. All rights reserved. No part of this
publication may be reproduced withoutthe written permission of
Zilog, Inc.
The information in this publication is subject to change without
notice.

Table of Contents

Chapter 1. Z80,OOO CPU Overview
1.1
1.2

1.3
1.4
1.5
1.6
1.7
1.S

Introduction
Architecture

1-1
1-1

1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7

1-1
1-1
1-2
1-3
1-3
1-3
1-3

Registers
Address Spaces
Memory Management
Addressing Modes
Instruction Set
Normal and System Modes of Operation
Exceptions

Extended Processing Architecture
Cache
External Interface
CPU Internal Organization
ZSOOO Compatibility
Summary

1-4
1-4
1-4
1-5
1-6
1-6

Chapter 2. Data Fonaats and Registers
2.1
2.2
2.3
2.4
2.5

2.6

Introduction
Data Formats
General-Purpose Register File
Program Status Registers
Special-Purpose Control Registers

2-1
2-1
2-1
2-2
2-3

2.5.1 Program Status Area Pointer (PSAP)
2.5.2 Normal Stack Pointer (NSP)
2.5.3 Translation Table Descriptor Registers
2.5.4 Overflow Stack Pointer (OSP) • • • • •
2.5.5 Hardware Interface Control Register (HICR)
2.5.6 System Configuration Control Longword (SCCL)

2-3
2-3
2-4
2-4
2-4
2-4

Reserved Control Sits

2-4

Chapter ,. Address Representation and Modes of Operation
3.1
3.2
3.3

Introduction • • • • • •
Address Representation.
Normal and System Modes

3-1
3-1
3-2

Chapter 4. Address Spaces and tte.ory Management
4.1
4.2

3
4

Introduction
Address Spaces

4-1
4-1

4.2.1
4.2.2
4.2.3

4-1
4-3
4-3

Logical Memory Address Spaces
Logical I/O Address Space
Physical Address Spaces

iii

Table of Contents (Continued)
4.3

Memory Management • • • • •

4-3

4.3.1
4.3.2

Address Translation
Loading the TLB

4-4
4-5

4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4

4-6
4-6
4-7
4-7

4.3.3
4.3.4
4.3.5
4.3.6

Translation Table Descriptor Registers
Level-1 Table Entries
Level-2 Table Entries
Page Table Entries

Access Protection • • • • •
Address Translation Algorithm
Address Translation Exceptions
Memory Management Instructions

4-8
4-B
4-10
4-10

Chapter 5. Addressing Modes a:Id Address Calculations

5.1
5.2

Introduction • • • •
Address Calculations

5-1
5-1

5.2.1 Compact Address Calculations
5.2.2 Segmented Address Calculations
5.2.3 Linear Address Calculations

5-1
5-1
5-3

5.3 Addressing Mode Descriptions
5.3.1

5.3.2

5-4

Compact Mode Descriptions and Examples

5-4

5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
5.3.1.6
5.3.1.7
5.3.1.8
5.3.1.9

5-4
5-4
5-4
5-5
5-5
5-6
5-6
5-7
5-7

Register (R)
Immediate (1M)
Indirect Register (IR)
Direct Address (DA)
Index (X) • • • •
Base Address (BA) •
Base Index (BX) ••
Relative Address (RA)
Relative Index (RX) •

Segmented and Linear Mode Descriptions and Examples

5-7

5.3.2.1
5.3.2.2
5.3.2.3
5.3.2.4
5.3.2.5
5.3.2.6
5.3.2.7
5.3.2.8
5.3.2.9

5-7
5-8
5-8
5-9
5-10
5-11
5-12
5-13
5-14

Register (R)
Immediate (1M)
Indirect Register (IR)
Direct Address (DA)
Index (X)
Base Address (BA)
Base Index (BX)
Relative Address (RA)
Relative Index (RX)

5.4 Extended Addressing Modes
iv

•••

5-15

Chapter 6. Instruction Set

6.1
6.2

6-1
6-1

6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.B
6.2.9
6.2.10
6.2.11

6-1
6-2
6-3
6-4
6-5
6-5
6-6
6-7
6-B
6-B
6-9

Load and Exchange Instructions
Arithmetic Instructions
Logical Instructions
Program Control Instructions
Bit Manipulation Instructions
Bit Field Instructions
Rotate and Shift Instructions
Block Transfer and String Manipulation Instructions
Input/Output Instructions
CPU Control Instructions
Extended Instructions

6.3 Flags and Condition Codes
6.4 Notation and Binary Encoding
6.4.1
6.4.2
6.4.3

6.4.4
6.5
6.6

Introduction •••
Functional Summary

6-9
6-10

Assembler Language Syntax
Instruction Format
Extended Addressing Modes

6-11
6-12
6-13

6.4.3.1
6.4.3.2

6-13
6-13

Compact Mode
Segmented or Linear Mode

Unimplemented Instruction Encodings

ZBO,OOO Instruction Descriptions and Formats
EPA Instruction Templates

6-15
6-16
6-209

Chapter 7. Instruction Execution and Exceptions

7.1
7.2
7.3

7.4

Introduction • • • • •
Operating States •••
Instruction Execution

7-1
7-1
7-2

7.3.1
7.3.2

7-2
7-3

Instruction Ending
•••••••
Effects of the Pipeline on Execution

Exceptions.

7-3

7.4.1 Reset
7.4.2 Bus Error •
7.4.3 Interrupts
7.4.4 Traps •

7-3
7-4
7-4
7-4

7.4.4.1
7.4.4.2
7.4.4.3

Extended Instruction Trap
Privileged Instruction Trap
System Call Trap • • • • • •

7-4
7-4
7-4
v

Table of Contents (Continued)
7.4.4.4 Address Translation Trap
7.4.4.5 Breakpoint Trap
7.4.4.6 Integer Arithmetic Error Trap
7.4.4.7 Conditional Trap • • • •
7.4.4.8 Unimplemented Instruction Trap
7.4.4.9 Odd PC Trap
••••••••
7.4.4.10 Trace Trap • • • • • • • • • •
7.4.5 Changing Program Status
7.4.6 Exception Handlers
7.4.7 Priority of Exceptions

7-4
7-4
7-4
7-4
7-5
7-5
7-5
7-5
7-7
7-8

Chapter 8. External Interface
8.1
8.2
8.3
8.4
8.5
B.6
8.7
B.8

Introduction
Bus Operations
Multiprocessor Configurations
Cache
•••••••••••
Pin Functions
•••••••
Hardware Interface Control Register
Bus Timing
8us Transactions

B-1
8-1
8-2
8-3
8-3
8-5
8-6
8-7

B.8.1
8.8.2

Response
CPU-Memory Transactions

8-8
8-8

8.8.2.1 Single Memory Read and Write Transactions
8.8.2.2 8urst Memory Read and Write Transactions
8.8.2.3 Interlocked Memory Transactions

8-8
8-10
8-11

B.8.3 Input/Output Transactions
8.8.4 EPU Transactions
8.8.4.1 CPU-EPU Instruction Transactions
8.8.4.2 CPU-EPU Data Transactions
8.8.4.3 EPU-Memory Transactions
8.8.5 Interrupt Request and Acknowledge
8.8.6 Internal Operation and Halt Transactions
8.8.7 Bus Retry
8.B.B Bus Error

8-12
8-13
8-16
8-17
8-18
8-20
8-21
8-21
8-21

B.9 Bus Request and Acknowledge
8.10 Reset
••••••

8-22
8-26

Appendix A. ZOOOO C..patibility

A-1

Appendix 8. MeIIory-Mapped I/O

B-1

Appendix C. Cache Control and .....ry TrlKlSactions

C-1

Appendix D. Progr_er' s Quick Reference Guide

0-1

Appendix E. naing foraulae for Perfornlance Evaluation

E-1

Glossary

G-1

Index

1-1

List of Illustrations

figure 1-1.
Figure 1-2.

Memory Mapping
Functional Block Diagram

1-2
1-6

Figure
Figure
Figure
Figure

Data Formats
General-Purpose Registers
Program Status Registers
Special-Purpose Control Registers

2-1
2-2
2-3
2-3

Figure 3-1.

Address Representation

3-2

Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

Address Spaces
Logical Memory Addresses in Compact Mode
Memory Address Space in Segmented Mode
Bytes, Words, and Longwords in Memory
Address Translation Using the TLB •
Logical Address Partition for Address Translation
Automatic Loading of the TLB Using Tables in Memory
Translation Table Descriptor
Translation Table Base Address
Table Entry Formats
Address Translation Trap Identifier Word

4-1
4-2
4-2
4-3
4-4
4-5
4-5
4-6
4-7
4-7
4-10

Figure 5-1.
Figure 5-2.

Addressing Modes
Segmented Addresses

5-2
5-3

Figure 6-1.

Bit Field

6-6

Figure
Figure
Figure
Figure
Figure

7-1.
7-2.
7-3.
7-4.
7-5.

Operating States
Program Status Saved on System Stack
Program Status Area •
Program Status Saved on Overflow Stack
Exception Priority Flowchart

7-1
7-5
7-6
7-7
7-B

Figure
Figure
Figure
Figure
Figure

B-1.
B-2.
B-3.
8-4.
B-5.

B-1
B-2
8-4
B-5

Figure
Figure
Figure
Figure

8-6.
8-7.
8-B.
B-9.

System Configuration
Multiprocessor Configurations
ZBO,OOO Pin Functions •
•
Hardware Interface Control Register
Example of Memory Read Timing Showing Different
Bus Scale Factors
Single Memory Read Timing
Single Memory Read Timing (One Wait State)
Single Memory Write Timing
Burst Transfer Protocol
•

2-1.
2-2.
2-3.
2-4.

4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-B.
4-9.
4-10.
4-11.

B-6
B-B
B-9
8-10
B-11
vii

------~,-

----

Table of Contents (Continued)
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
B-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.

Burst Memory Read Timing (One Wait State)
Burst Memory Write Timing.
I/O Read Timing •
•
EPA Instruction Processing
CPU-EPU Instruction Transfer Timing
CPU-EPU Data Read Timing
CPU-EPU Data Write Timing •
EPU-Memory Single Write Timing
Interrupt Response/Acknowledge Timing
Internal Operation and Halt Timing
Bus Error Identifier Word •
Local Bus Request Acknowledge Timing
Global Bus Request Timing •
•
State Diagram for CPU Bus Request Protocol
Reset Timing

8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-21
8-22
8-23
8-24
8-27

Figure C-1.

Cache Organization

C-1

Figure E-1.
Figure E-2.

Functional Block Diagram
Instruction Pipeline

E-1
E-2

viii

Chapter 1.
Z80,000 CPU Overview
1.1

INTRODUCTION

1 .2.1

Registers

The zao,ooo CPU is an advanced 32-bit microprocessor that integratea the architecture of a
mainframe computer into a single chip. A subset
of the zao,ooo architecture was originally implemented in a 16-bit version, the zaooo~ microprocessor. The zao,ooo bua structure permits the
use of zaooo family peripherals, such as the Za030
SCC and Za036 CIO. While maintaining compatibility with zaooo family software and hardware, the
zao,ooo CPU offers greater power and flexibility
in both its architecture and interface capability. Operating systems and compilers are easily
developed in the zao,ooo CPU's sophisticated
environment, and the hardware interface provides
for connection in a wide variety of system configurations.

The zao,ooo CPU includes sixteen 32-bit generalpurpose registers. The registers can be used as
data accumulators, index values, or memory
pointers. Two of the registers, the Frame Pointer
and Stack Pointer, are used for procedure linkage
with the Call, Enter, Exit, and Return instructions.

Memory management is integrated in the CPU, providing access to more than 4 billion bytes of logical address space without external support components. The zao,ooo CPU also includes a cache
memory, which complements the pipelined design to
achieve high performance with moderate memory
speeds.

1.2.2 Address Spaces

This chapter presents an overview of the features
of the zao,ooo CPU that offer extraordinary
flexibility to microprocessor system designers in
tailoring the power of the CPU to their
specialized applications.
The chapters that
follow describe these features in detail.
1.2 ARCHITECTURE
The CPU features a general-purpose register file
with sixteen 32-bit registers.
The instruction
set offers a regular combination of nine general
addressing modes with operations on numerous data
types, including bits, bit fields, bytes (a bits),
words (16 bits) , long words (32 bits) , and
variable-length strings.
The memory management,
exception handling, and system and normal mode
features support the development of reliable
software systems.

The zao,ooo registers also include the 32-bit Program Counter and 16-bit Flag and Control Word.
These two registers, together called the Program
Status, are automatically saved during trap and
interrupt processing. Nine other special-purpose
registers are used for memory management, system
configuration, and other CPU control.

The CPU uses 32-bit logical addresses, permitting
direct access to 4G bytes of memory. The logical
addresses are translated by the memory management
mechanism to the physical addresses used to access
memory and peripherals.
The CPU supports three modes of address representation--compact, segmented, and linear--selected
by two control bits in the Flag and Control Word
register.
Applications with an address space
smaller than 64K bytes can take advantage of the
dense code and efficient use of base registers
with the 16-bit compact addresses. Although programs executing in compact mode can only manipulate 16-bit addresses, the logical address is
extended to 32 bits by concatenating the 16 mostsignificant bits of the Program Counter register.
Compact mode is equivalent to the laOOO non-segmented mode.
Segmented mode supports two segment sizes--64K
bytes and 16M bytes. Up to 32,76a of the small
segments and 12a of the large segments are available. In segmented mode, address calculations do
not affect the segment number, only the offset

1-1

Z80,000 CPU Overview
wi thin the segment.
Allocating individual
objects such as program modules, stacks, or large
data structures to separate segments allows applications to benefit from the logical structure of a
segmented memory space.
The 32-bit addresses in linear mode provide uniform and unstructured access to 4G bytes of memory. Some applications benefit from the flexibility of linear addressing by allocating objects to
arbitrary positions in the address space.

Memory management provides two valuable functions--address translation and access protection.
Access protection ensures that proprietary portions of memory, or those portions concerned with
operating system functions, are protected from
tampering.
Address translation, the process of
mapping a program's logical addresses to the physical addresses used to access memory, streamlines
system performance, since the operating system can
relocate programs in memory, free from rigid constraints.
By integrating memory management with
the processor in a single chip, the l80, 000 CPU
reduces parts-count and improves memory access
time.
Another memory management function, demand-paged
virtual memory, a !lows programs to execute even
when only a portion of their memory requirements
is available in primary storage. The rest of the
program can be stored in secondary storage, typically on disk.
Thus, virtual memory improves a

The CPU implements a paged translation mechanism
similar to that of most mainframe and super-minicomputers. The operating system creates translation tables in memory, then loads pointers to the
tables in control registers. The CPU automatically
refers to the tables to perform address translation and access protection.
To manage the large logical address space, the
translation scheme divides it into fixed-size, 1Kbyte pages. Similarly, the physical address space
is divided into fixed-size frames, also 1K-bytes
each. The memory management mechanism maps a logical page to an arbitrary physical frame (Figure
1-1).
Since both the pages and frames are of
fixed and equal size, the operating system's memory allocation problem is simplified.
The CPU implements a Translation Lookaside Buffer
(TLB) to store the information needed to translate
the sixteen most recent! y used pages.
When the
information needed to translate a page is missing
from the TLB, the CPU automatically translates the
address using the tables in memory, and then loads
the information into the TLB.
The memory management mechanism can be used to map
logical
memory
addresses
to
physical
I/O
addresses. The use of memory-mapped I/O permits
protected access by application programs to
selected peripheral devices.

LOGICAL ADDRESS SPACE

PHYSICAL ADDRESS SPACE

INVALID

PAGE 3FFFFF"

FRAME 3FFFFF'6

INVALID

PAGE 3FFFFE16

FRAME 3FFFFE'6

PAGE 3FFFFD"

FRAME 3FFFFD'6

INVALID

PAGE 3FFFFC"

FRAME 3FFFFC'6

INVALID

PAGE 4"

PAGE 316

FRAME 316

INVALID

PAGE 216

FRAME 2,6

PAGE 116

FRAME 116

PAGE 016

FRAME 016

Figure 1-1.

1- 2

system's cost/performance by permitting programs
to execute with varying amounts of memory.

"'-try Happing

2324-002

Z80,OOO CPU Overview
1.2._ Addreaaing IbIea

The CPU locetes operands (the data manipulated by
inatructions) in regiaters, memory, peripheral
ports, or in the inatruction. The location of an
operand is specified by one of nine general
addresaing modes: Register, Immediate, Indirect
Register, Direct Address, Index, Baae Addresa,
Base Index, Relative Address, and Relative Index.
Instruction formats provide compact encodinga for
the most frequently used addressing modes.

1.2.5

Inatruction Set

The Z80,OOO CPU supports operations on nine data
types: bit, bit field, aigned integer, unaigned
integer, logical value, address, packed BCD integer, stack, and string.
Integer and logical
values can be byte, word, or longword in size. In
addition, floating-point operations are implemented through the Extended Processing Architecture (EPA) facility by a coproceasor (ZB07D Arithmetic Processing Unit) or by software emulation.
Several instructiona are provided for important
control structures.
Conditional branches and
jumps support "if-then", "while", and "repeat"
constructions. The Decrement and Branch if NonZero instruction can be used for loop control.
Call, Enter, Exit, and Return instructions perform
procedure linkage.
The regular combination of addressing modes,
operations, and data types offers a powerful
instruction set that is well-suited for compilation of high-level languages such as C, Pascal,
and Ada.

1.2.6 NoftIal IDI 51st. Modes of Operation

The CPU has two modes of operation--normal and
system--used to isolate application programs from
senaitive portions of the operating system. The
mode is aelected by a bit in the Flag and Control
Word regiater.
Dnly programs in system mode are privileged to
execute I/O instructions and access control registers. The memory management mechanism allows system mode programs to accesa regions of memory protected from normal mode access. Further protection is provided with separate stacks for system
and normal modes. Application programs use the

System Call instruction and trap to request services from the operating system.
1.2.7 Exceptions

Exceptions are conditions or events that disrupt
the usual sequence of instructions. The Z80,OOO
CPU supports four types of exceptions: reset, bus
error, interrupts, and traps. A reset exception
initializes the CPU state in response to an external request, typically part of a power-on
sequence.
A bus error exception occurs when
external hardware indicates an irrecoverable
error, such as an uncorrectable memory error, on a
bus transaction. An interrupt is an asynchronous
event signalled externally, typically when a
peripheral device needs attention. A trap is a
condition detected by the CPU synChronously with
execution of an instruction.
When an exception occurs, the CPU saves the Program Status registers of the executing process on
the system stack. Then new values for the Program
Status registers are read from a table in memory
(Program Status Area), thus passing control to an
exception handler.
The CPU provides a flexible interrupt structure
that includes three types of interrupts: nonmaskable, vectored, and nonvectored. The nonmaskable
interrupt, which is of highest priority, is typically reserved for the most critical requirements,
such as sudden power failure. Both vectored and
nonvectored interrupts can be separately masked by
bits in the flag and Control Word register. Vectored interrupts allow the CPU to branch to a
specific exception handler selected by a code read
from the peripheral. Nonvectored interrupts use a
common exception handler.
The CPU recognizes several trap conditions, all of
which can be used to improve software reliability.
The System Call trap provides controlled
access for application programs to operating system functions. Traps for integer overflow, subrange out of bounds, and subscript out of bounds
catch common run-time errors. The Address Translation trap allows the operating system to implement access protection and virtual memory. Traps
for breakpoint and single instruction tracing are
used during software development. The Conditional
Trap instruction ia used for software definition
of exception conditions not recognized by the CPU
hardware.

1-3

180,000 CPU Overview

1.' EXTENDED PROCESSING ARCHITECTURE
The Extended Processing Architecture (EPA) fscility allows the operations defined in the 180,000
CPU architecture to be extended by software or
hsrdware. for example, floating-point operations
are supported by the 18070 Aritlvnetic Processing
Unit (APU) or by a software package that emulates
the APU.
When the CPU encounters an EPA instruction, it
checks a control bit in the flag and Control Word
regiater to determine whether the EPA facility is
enabled. If disabled, the CPU traps for software
emulation of the instruction. If enabled, the CPU
sends the instruction across the axternal interface to an Extended Processing Unit (EPU). The
CPU then transfers the operands for the instruction to the EPU.
The data processing operations per formed by the
EPU are transparent to the CPU. In general, ths
EPU sxscutes complex opsrstions such as floatingpoint aritlvnetic, decimal sritlvnetic, or signal
processing with special-purpose hardware.

1 •• CACHE

The 180,000 CPU contains an on-chip cache buffer
to store copies of memory locations that were
recently referred to. Most memory references are
either to a location that was referred to recently
(temporal locality) or to a nearby location
(spatial locality).
Therefore, on most memory
fetches the CPU is able to find the required data
in the cache (a hit), thus avoiding a slower
access to external memory. Whsn the required data
is missing from the csche (a miss), the CPU
fetches the dsta from sxternal memory snd losds a
copy into the cache. The fetched data replaces
the least recently used dats in the cache.
The cache provides significant cost/performance
advantages by allowing the CPU to execute instruc-

1-4

tions at a faster rste than permitted by external
memory alone. The cache can be separately enabled
to store both instructions and data. The effectiveness of the cache is enhanced by storing data
along with instructions, but an spplication can
cache instructions only. Cache replacement on a
misa can also be inhibited. This option can be
used to lock desired locations into the cache for
fast, on-chip access.
1.5 EXTERNAL INTERFACE

The 180,000 CPU offers a number of features for
interfacing to systems that span a wide range of
cost/performance requirements.
The Hardware
Interface Control Register (HICR) specifies certain characteristics of the hardware configuration
surrounding tha CPU, including bua speed, memory
data path width, and number of automatic wait
states.
The system designer can fine-tune performance by
selecting not only the CPU clock rate and bus
speed (1/2 or 114 the CPU clock), but also the
acceaa time and date path width for the memory.
for two independent regions of memory the CPU can
be programmed for both the number of wait states
automatically inserted, and whether the data path
is 16 or 32 bits wide. With these options, a system can essily sccommodate s slow, 16-bit-wide
bootstrap read-only memory (ROM) in one region and
fast, 32-bit-wide rendom access memory (RAM) in
the other.
furthermore, the CPU supports an
optional burst transfer of several memory words
from consecutive locations. 8urst transfers can
increase memory bandwidth for interleaved and
"nibble-mode" memory systems.
The CPU provides support for four types of multiprocessor configurational
coprocessor, slave
processor, tightly-coupled multiple CPUs, and
loosely-coupled multiple CPUs. Coprocessors, such
as the 18070 Arithmetic Processing Unit, work synChronously with the CPU to execute a single
instruction stream using the Extended Processing

Z80,000 CPU Overview
Architecture facility. Slave processors, such as
the Z8016 DMA Transfer Controller, perform dedicated functions asynchronously to the CPU. Tightly-coupled multiple CPUs execute independent
instruction streams and generally communicate
through shared memory on a common bus. Two separate bus request protocols support slave processing and tightly-coupled multiprocessors. Looselycoupled multiple CPUs generally communicate
through a multi-ported peripheral, auch as the
Z8038 fIfO I/O Interface Unit, using the interrupt
and I/O facilities of the Z80,000 CPU.

1.6 CPU INTERNAL ORGANIZATIIIt

registers and another path to the instruction
bus for reading displacementa and direct
addresses. The result of the address calculation is transmitted to the TLB.
•

The register file contains the sixtean generalpurposa longword registers, Program Status
registers, special-purpose control registers,
and several registers used to store values temporarily during instruction execution.
The
regiater file has one path to the address
arithmetic unit and two paths to the execution
arithmetic and logic unit.

•

The execution arithmetic and logical unit calculates the results of instruction execution,
such as add, eXClusive-or, and simple load.
This unit has two paths to the register file on
which two operands csn be read simultaneously
or ona can be written. One of the paths to the
register file is multiplexed with a path from
the memory bus.

•

The instruction decode and control unit decodes
inatructions and controls the operation of the
other functional units. This unit has a path
from the instruction bus and two programmable
logic arrays for separate microcoded control of
the two arithmetic units.
This unit also
controls the exception handling and loading of
the TLB.

figure 1-2 shows a block diagram of the Z80,000
CPU internal organization, including the following
major functional units and data paths:
•

•

The
external
interface
logic
controls
transactions on the bus. Addresses and data
from the internal memory bus are transmitted
through the interface to the Z-BUS. The Z-BUS
is a time-multiplexed, address/data bus that
connects the components of a microprocessor
system.
The cache stores copies of inetruction and data
memory locstione. Instructions are read from
the cache on the instruction bus. Data is read
from or written to the cache on the memory
bus.
The Translation Lookaside Buffer (TLB) translates logical addresses calculated by the
address arithmetic unit to physical addresses
used to access the cache.
The eddress arithmetic unit performs all
address calculations. This unit has a path to
the register file for reading base and index

All of the functional units and data paths listed
abova are 32 bits wide.
The operation of the CPU is highly pipe lined ao
that several instructions are simultaneously in
different stages of execution. Thus, the functional units effectively operate in parallel with
one instruction being fetched while an address is
calculated for another instruction and results are
stored for a third instruction.

1-5

Z80,000 CPU Overview
Z·BUS

-------,

r------

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IL ________________ I
MEMORY BUS

CACHE DATA

CACHE
ADDRESS TAGS

INSTRUCTION REGISTER

PHYSICAL PC

TRANSLATION
LOOKASIDE
BUFFER

INSTRUCTION
DECODE
AND
CONTROL
UNIT

EXECUTION ARITHMETIC
AND LOGIC UNIT

Figure 1-2.

Functional Block Diagr_

1.7 Z8000 COMPATIBILITY

1.B

The 180,000 CPU's instruction set encoding allows
it to directly execute Z8000 family software such
as compilers and the 1RTS~ real-time operating
system.
Z8000 programs must not use the 18000
privileged instructions, address, and control
field encodings i f they are to execute correctly
on the Z80,000 CPU, since the Z80,000 CPU uses
many of these reserved encodings to extend the
register file, address range, and instruction
functionali t y.

The Z80,000 CPU meets and surpasses the requirements of medium and high-end microprocessor systems.
Software program development is easily
accomplished with the CPU's sophisticated architecture.
The highly-pipelined design, on-chip
cache, and external interface support systems
ranging from dedicated controllers to mainframe
computers.

1-6

SlMlARY

8225-001

Chapter 2.
Data Formals and Registen
2.1

2.2 DATA FORMATS

INTRODUCTION

The zao,ooo CPU manipulates data located in registers, memory, and peripherals. The zao,ooo register repertoire consists of the general-purpose
register file, the Program Counter, the Flag and
Control Word, and nine special-purpose control
registers. This chapter describes the format for
data and the use of registers.
Chapter 4
describes the use of memory and peripharals.

The CPU manipulates bits, bytes (a bits), words
(16 bits), longwords (32 bits), and quadwords
(64 bits) of data. Within a byte, word, longword,
or quadword, the bits are numbered from right to
left, from least to most significant (Figure
2-1). This is consistent with the convention that
bit n corresponds to position 2n in the representation of binary numbers. (However, the bit numbering for bit field data, described in Section
6.2.6, is in the opposite direction from
Figure 2-1.)

7&543210

IIIIIIIIIBITSINABYTE
15 14 13 12 11 10 9

& 7

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BITS IN A WORD
313029

11.. . .1.1. . 1_1. .I._ _ _ _ _--I~F_:

210

_____--'-1.....1.........1......1 BITS IN A LONGWORD

636261

210

IL....I.I....I-I...I.I---------I~'F_:--------...I.I....I-I. .1.1.....1 BITS IN AQUADWORD
Figure 2-1.
2.3

GENERAL-ruRPOSE:

The general-purpose register file contains 64
bytes of storage (Figure 2-2). The first 16 bytes
(byte registers RLO, RHO, ••• , RL 7, RH7) can be used
as accumulstors for byte data. The first 16 words
(word registers RO,R1, ••• ,R15) csn be used as
sccumulators for word data, as index registers
(except RO), or for memory addresses in compact
mode (except RO) •
Any long word register
(RRO,RR2, ••• ,RR30) can be used as an accumulator
for longword data and, in segmented or linear
mOde, as an inde)( register (e)(cept RRO) or for
memory addresses (e)(cept RRO). Quadword registers
(RQO,RQ4, ••• , RQ28) can be used as accumulators

8225-002

Data Fomata

for
Multiply,
Divide,
and
ElCtend
Sign
instructions. Within quadword register RQn, RRn
contains the more significant longword. A 4-bit
field in instructions specifies which generalpurpose register to access. The register size is
determined by the instruction opcode.
The unique organization of the register file
allows bytes and words of data to be manipUlated
conveniently while leaving most of the registers
free to hold addresses, counters, or other
values. For example, four bytes in RHO, RLO, RH1,
and RL 1 can be packed into the single longword
register RRD and manipulated independently with
the e)(tensive byte-oriented instructions.

2-1

Data Formats and Registers
Two registers are dedicated for the Stack Pointer
and Frame Pointer used by Call, Enter, Exit, and
Return instructions. The Stack Pointer is also
used in processing exceptions and by the Interrupt
Return instruction.
There are separate Stack
Pointers for system and normal modes of operation.
The registers used for the Stack Pointer and Frame
Pointer depend on the address representation
mode. In compact mode, R15 is the Stack Pointer
and R14 is the Frame Pointer.
In segmented or
linear mode, RR14 is the Stack Pointer and RR12 is
the Frame Pointer.
See Section 3.3 for more
details on modes of operation.

RRO

1 RHO

RR2

1 RH2

RR4
R04\ RR6

1 RH4

ROO

ROB
R012
R01S

R020

R024

R02B

1 RH6

o
o
o
o

1 RL4
1 RL6

o
o
o
o
o
o
o
o

1 RHl

o
o
o

1 RL 1 0

RO, Rl

1 RL3 0

R2, R3

1 RL5 0

R4, R5

1 RH1 0 1 RL1 0

RB, R1

1 RH3
1 RH5

I
I

RRB

RR10

Rl0

RR12

R12

RR14

R14

I RR16

\ RR1B

I RR20

\ RR22

RR24

RR26

RR2B

RR30

I
I

Figure 2-2.

2._

1 RLO
1 RL2

Rll

R13

R15

Half Carry (H) is used in BCD ar i thmetic to convert the result of a previous binary addition or
subtraction to a decimal result.
The C, l, S, and PlY flags can be manipulated
using the Complement Flag and Set Flag instructions.
Section 6.3 provides more information
about the flags.
The Integer Overflow Enable (IV) bit is the mask
for an Integer Over flow trap. While this bit is
1, the Integer Overflow trap is enabled; while 0,
the integer overflow trap is disabled (see Section
7.4.4.6).
The low-order byte of the FCW can be accessed in
normal mode using the load Control Byte
instruction.
The high-order byte of the FCW contains eight control bits:
Extended/Cllllp8Ct Mode (Etc) and linear/5egalented
Mode {lIS} controls the mode of address representation. While E!C is 0, addresses are compact (16
bits). While E/e is 1, addresses are extended (32
bits) and are either segmented (LiS is 0) or
linear (lis is 1).

General-Purpose Registers

PROGRAM STATUS REGISTERS

The Program Status registers are the Program
Counter (PC) and the Flag and Control Word (FCW)
(Figure 2-3). The PC contains the 32-bit address
of the instruction being executed. The 16-bit FCW
indicates operating modes, masks for traps and
interrupts, and flags set according to the result
of instructions.
The low-order byte of the FCW contains six flags,
described below, and the integer overflow mask.
Many instructions modify or use the flags.
Carry (C) indicates a carry out of the high-order
bit position during an operation.
Zero (Z) indicates that the result of an operation
is zero.
Sign (S) indicates whether the
operation is negative or positive.

result

Parity/Overflow (PlY) indicates that the result of
a logical operation has even parity or that
overflow has occurred for arithmetic operations.
2-2

Dec:iJllal-Adjust (D) is used in BCD arithmetic to
indicate whether an addition or subtraction was
last executed.

Syste.tNonial Mode (SIN) controls the operating
mode. While this bit is 1, the CPU is operating
in system mode; while 0, the CPU is operating in
normal mode.
Extended Processor Architecture Mode (EPA) controls the Extended Processing Architecture facility.
While this bit is 1, the CPU processes
extended processing instructions as if the system
contains Extended Processing Units, which serve as
co-processors to assist the CPU in executing
extended processor instructions. While this bit
is 0, the CPU traps extended processor instructions.
Vectored Interrupt Enable (VIE) and Nonvectored
Interrupt Enable (NVIE) determine when the CPU
recognizes vectored and nonvectored interrupts.
Vectored interrupts are enabled when VIE is 1;
nonvectored interrupts are enabled when NVIE is
1. These bits can be manipulated using the Enable
Interrupt and Disable Interrupt instructions.
Trace Pending (TP) and Trace Enable (T) are used
for instruction tracing. While T is 1, instruction tracing is enabled; while 0, instruction
2071·001

Data Formata and Reqisters
tracing is diaabled. TP is used with T to ensure
that exactly one trace trap occurs after each
instruction executed when tracing is enabled (see
Section 7.4.4.10).

can also be loaded using the Interrupt Return and
Load Program Status instructions. The FCW can be
accessed using the Load Control instruction.
2.5

During exception processing, the Program Status
registers are saved on the system stack and new
values for the registers are loaded from the Program Status Area. The Program Status registers
15

IElCIs/NIEPAIVIE~VI~ usl TPI

Tic I z I

SPECIIIL-PURPOSE CONTROl REGISTERS

The CPU includes nine special-purpose longword
registers (Figure 2-4). These are accessed using
the Load Control Long instruction.

IPNI D I H IIV

0 I

INTEGER OVERFLOW ENABLE (IV)
HALF CARRY (H)
DECIMAL-ADJUST (D)
PARITY/OVERFLOW (PlY)
SIGN(S)
ZERO(Z)
CARRY(C)

TRACE (T)

'---

TRACE PENDING (TP)
LlNEARISEGMENTED MODE (US)
NONVECTORED INTERRUPT ENAB LE (NVIE)
VECTORED INTERRUPT ENABLE (VIE)
EXTENDED PROCESSOR ARCHITE CTURE (EPA)
SYSTEM/NORMAL MODE (s/N)
EXTENDED/COMPACT MODE (ElC)

FLAG AND CONTROL WORD (FCW)
31

PROGRAM COUNTER (PC)

Figure 2-3.

Progr_ Status Registers

HARDWARE INTERFACE CONTROL RIIGISTER (HICR)

Figure 2-4.
2.5.1

Special-Purpoae Cootrol Registers

Progr_ Status Area Pointer (PSAP)

The Program Stet us Area Pointer contains the physical, base address of the Program Status Area.
The Program Status Area contains the Program
Status information (PC and FCW) fetched during
exception processing. Refer to Chapter 7 for more
information about the Program Status Area.
The
longword PSAP can be accessed using the Load Control Long instruction; both the low-order word and
high-order word of the PSAP can be accessed using
the Load Control instruction.

207Hl02,003

2.5.2

Nor.al Stack Pointer (NSP)

The Normal Stack Pointer contains the· Stack
Pointer used in normal mode. System mode programs
csn access normal mode register RR14 using the
Load Control Long instruction and normal mode registers R14 and R15 using the Load Control instruction.

2-~

Data Formats and
2.5.'

R~qisters

Tr.-Jalation Tabla Descriptor Registera

The translation table descriptor ragistera--System
Inatruction Translation Table Deacriptor (SITTD),
System Data Translation Table Descriptor (SDTTD),
Normal Inatruction Translation Table Descriptor
(NITTD), and Normal Data Translation Table
Descriptor (NDTTD)--contain the physical addresses
of the translation tables used by the memory management mechanism. These registers also contain
other fields that control the memory management
mechanism (see Section 4.3.2.1).
2.5." Overflow Stack Pointer (OSP)
The Overflow Stack Pointer (OSP) contains the
physical address of the Stack Overflow Area. The
Stack Overflow Area is used when an address translation error occurs during exception processing
(see Section 7.4.5).
2.5.5

Hardware Interface Control Register (HICH)

The Hardware Interface Control register contains
fielda controlling the external interface of the
CPU, including bus speed, data path width, and
automatic wait states. (See Section 8.6).

2.5.6

translation mechanism is enabled for references in
the corresponding apace; while either bit is 0,
the translatIon mechanism is disabled for references in the corresponding spsce.
Cache Replac_t (CH) controls the cache replacement algorithm.
While this bit is 1, the cache
replacement algorithm is enabled; while 0, the
cache replacement algorithm is disabled.
Most
applications leave the replacement algorithm
enabled. Some applications, however, selectively
enable and disable the replacement algorithm to
lock specific locations into the cache. Refer to
Appendix C for more information.
Cache Instruction (CI) .-Jd ClIChe Data (m) control
the cachs mechanism for instruction and data
references. While either of these bits is 1, the
cache mechanism is enabled for the corresponding
references; while either bit is 0, the cache mechanism is disabled for the corresponding references. Refer to Appendix C for more information.
Exception linear/5egEnted
whether linear or segmented
sentation is used during
While this bit is 1, linear
segmented mode is used (see

IIIOde (Xl/S) controls
mode of address repreexception processing.
mode is used; while 0,
Section 7.4.5.)

Syat.. Configuration Control longNDrd

(SCCl)

2.6 RESE:RVm CllfJID. BITS

Ths System Configuration Control Longword contains
control bits for the addresa translation mechanism, cache mechanism, and exception processing.
These bits are as follows:

Some of the bits in the FeW and control register
formats shown in Figures 2-3 and 2-4 are marked
"0". These bits are reserved for future definition.
When the control register is read, these
bits return O.
When ths control register is
written, these bits must be O. Although the CPU
does not check thst the reserved bits written to
the control register are 0, functions may be
defined for these bits in the future.

Syeta. Addreaa Tr_lation (SX) .-Jd Nol'll8l. lIddreaa
Tr_lation (NX) control the address trsnslstion
mechanism for system space snd normsl space references.
While either of these bits is 1, the

2-4

Chapter 3.
Address Bepresentation and
Modes of Operation
3.1

INTRODUCTION

The CPU has three modes of address represent ation--compact, segmented and linear--and two modes
of operation--normal and system.

3.2

IIOORESS REPRESENTATION

As shown in Figure 3-1, the CPU has three modes of
address representation: compact, segmented, and
linear. The mode is selected by two control bits
in the Flag and Control Word register (see Table
3-1).
The Extended/Compact (E!C) bit selects
whether compact addresses ( 16 bits) or extended
addresses (32 bits) are used.
For extended
addresses, the Linear/Segmented (L/S) bit selects
whether linear or segmented addresses are used.
These modes affect only the representation for
logical memory addresses, not logical I/O
addresses.
The Load Address instruction can be used to manipulate addresses in any mode of representation.
The address calculation performed by this instruction is the same as the addressing used to access
an operand.
In compact mode, addresses are 16 bits. Address
calculations using compact addresses involve all
16 bits. Compact mode is more efficient and consumes less program space for applications requiring less than 64K bytes of program and less than
64K bytes of data.
This efficiency is due to
shorter instructions in compact mode, and the fact
that addresses in the register file use word
rather than longword registers.
Applications
requiring more than 64K bytes of either program or
data should use segmented or linear mode.

Table 3-1.

Addr8118

Rep~atioo

Control Bits in FCW

Elf

lIS

o
o

o
1

Compact
Reserved
Segmented
Linear

Segmented mode supports two segment sizes--64K
bytes and 16M bytes. The most-significant bit of
the 32-bit address selects either a 15-bit segment
number with a 16-bit segment offset (MSB = 0) or a
7-bit segment number with 24-bit segment offsat
(MSB = 1).
Thus, the address space includes
32,768 of the smaller segments and 128 of the
larger segments. In segmented mode, address calculations involve only the segment offset; the
segment number is unaffected.
Many applications benefit from the logical structure of segmentation by allocating individual
objects,'such as program modules, stacks, or large
data structures, to separate segments.
In linear mode, addresses are 32 bits. Address
calculations using linear addresses involve all 32
bits.
In linear mode, the address space of 4G
bytes is uniform and unstructured. Some applications benefit from the flexibility of linear
addressing by allocating objects to arbitrary
positions in the address space.
In compact mode, addresses stored in the register
file use word registers; in segmented or linear
mode, addresses use longword registers. When an
address is specified in a register for Indirect,
Base Address, and Base Index addressing modes, or
for the destination of a Load Address instruction,
the address register specified by the instruction
is a word register in compact mode and a long word
register in segmented or linear mode. Similarly,
references to the Program Counter in compact mode
use only the low-order word of the PC, while in
segmented or linear mode, the entire long word PC
is used. In compact mode, tha Stack Pointer is
R15 and the Frame Pointer is R14. In segmented or
linear mode the Stack Pointer is RR14 and the
Frame Pointer is RR12.
Some addressing modes generally available in segmented or linear mode are restricted in compact
mode.
Refer to Chapter 5 for more information
about the effect of the address representation
mode on addressing modes and address calculation.
In compact mode, addresses encoded in instructions
occupy one word; in segmented or linear mode,
addresses in instructions occupy one or two

3-1

Address Representation and Modes of Operation
15

(A) COMPACT ADDRESSES

16 15

SEGMENT

OFFSET

(I) 84K BYTE SEGMENT SIZE
31

24 23

OFFSET

SEGMENT

(II) IBM BYTE SEGMENT SIZE
(B) SEGMENTED ADDRESSES
31

rigure 3-1.

Address Representatioos

words. Refer to Chapter 6 for more information
about the effect of the segmentation mode on
instruction representation and execution.
3.3 NORIW.

AN)

SYSTEM MmES

The CPU has two modes of operation, normal and
system, selected by the SIN bit in the Flag and
Control Word register. System mode (S/N = 1) is
more privileged than normal mode (S/N = 0). These
modes affect CPU operation in three areas: privileged instructions, Stack Pointers, and memory
management.
All inatructions can be executed in system mode.
Some inetructions, such as those performing I/O

operations or accessing control registers, can
only be executed in system mode, and are called
privileged instructions. When a program operating
in normal mode attempts to execute a privileged
instruction, an exception occurs. The privileged
instructions are identified in the instruction set
description in Chapter 6.
The Stack Pointer registers are distinct for normal and system modes. In normal mode, a reference
to the Stack Pointer register accesses the Normal
Stack Pointer. In system moda, a reference to the
Stack Pointer register references the System Stack
Pointer. In compact system mode, referencea to
R14 use normal mode R14. Table 3-2 shows the registers sccessed in the different modes.

Table 3-2. Registers Referenced by Access to R14 and R15
Register
Referenced by
Instructioo

R14
R15
RR14

3-2

Systllll Mode
Segmented
or Linear
System
System
System
System

R14
R15
R14
R15

NorllSl Mode

Compact

Normal
System
Normal
System

R14
R15
R14
R15

Segmented
or Linear
Normal
Normal
Normal
Normal

R14
R15
R14
R15

Compsct

Normal
Normal
Normal
Normal

R14
R15
R14
R15

2071-004

Address Representation and
In normal mode, the System Stack Pointer is not
accessible. In system mode, the Normal Stack
Pointer is accessed using the Load Control or Load
Control Long instruction.
Memory address spaces are distinct for normal and
system modes.
Different translation tables are
used for translating normal and system mode
addresses, although the tables can optionally be
merged.
The access protection performed by the
memory management mechanism allows access by system programs to memory locations that are prohibited from access by normal mode programs.
The CPU can change its operating mode whenever the
feW is loaded by a Load Control instruction, Load

~Modes

of Operation

Program Status instruction, Interrupt Return
instruction, or during exception processing. The
distinction between normal and system modes allows
the construction of a protected operating system.
The operating system kernel runs in system mode to
manage the computer system resources--CPU, memory,
and peripherals. Application programs run in normal mode, where they are prohibited from interfering with other application programs or the operating system. When application programs require a
service that only the operating system can perform, the System Call instruction is executed.
System Call causes a trap to the operating system,
passing an identifier for the particular service
requested.

3-3

Chapter 4.
Address Spaces and Memory
Management
4.1

INTRODUCTION

The CPU refers to memory and peripherals to fetch
instructions, fetch and store operands, process
exceptions, and perform memory management.
The
CPU uses addresses to specify the location for
memory and peripheral references.
Logical
addresses, which are the addresses manipulated by
programs,
are
distinguished
from
physical
addresses, which are the addresses the CPU presents to memory and peripherals.
This chapter
describes the types of logical addresses and the
procedure
for
mapping logical to physical
addresses.
Chapter B describes the way the CPU
refers to memory and peripherals using physical
addresses.

4.2 ADDR£SS SPACES
The CPU supports several distinct spaces for logical and physical addresses (Figure 4-1). Logical

addresses are in one of four memory address spaces
or in I/O address space. Physical addresses are
in memory or I/O address space.

4.2.1

logical Memory Address Spaces

Logical memory addresses are in system instruction
space, system data space, normal instruction
space, or normal data space. When the CPU is in
system mode, one of the two system address spaces
is used for a memory reference. In normal mode,
one of the two normal address spaces is used.
Instruction address space is used for instruction
fetches, immediate mode operand fetches, and
fetches or stores of operands specified using
Relative Address or Relative Index addressing
modes. Data address space is used for references
to fetch or store operands in memory, other than
those specified using Immediate, Relative, or
Relative Index addressing modes. Refer to Chapter
5 for a description of addressing modes.

MEMORY
SYSTEM
INSTRUCTION
SYSTEM
DATA
NORMAL
INSTRUCTION
NORMAL
DATA

1/0

LOGICAL ADDRESS SPACE

TRANSLATION.

PHYSICAL ADDRESS SPACE

r igure 4-1. Address Spaces

8225-003

4-1

Address Spaces and Memory Management
Logical addresses in the memory spaces are 32
bits.
Each address specifies the location of a
byte in memory.
In compact mode, only the loworder 16 bits of the logical address can be
directly manipulated; the high-order 16 bits of
the logical address are the high-order 16 bits of
the PC (Figure 4-2). In segmented mode, the lower
hal f of each address space contains 32,768 small
segments of maximum size 64K bytes, and the upper
half contains 128 large segments of maximum size
16M bytes (Figure 4-3).
Each segment can be
viewed as a contiguous string of bytes at consecutive offsets. In linear mode, the entire address
space is a contiguous str ing of bytes at consecutive addresses.

Words and long words in memory are addressed using
the lowest address of any byte in the word or
longword.
This is the left-most, highest-order,
most-significant byte of the word or longword
(Figure 4-4).
Word and long word operands located in memory can
be at even or odd addresses.
Performance is
improved when word operands are located at even
addresses and longword operands are located at
addresses that are a multiple of four.
Instruction words must be located at even addresses.
When an attempt is made to execute an instruction
at an odd address, an odd PC trap occurs.

PROGRAM COUNTER
31

COMPACT ADDRESS

16 15

~
I

16 15

LOGICAL ADDRESS

figure 11-2.
logical MeIIory Addresses in C. .pact Mode

SMALL SEGMENT 0

31 30

10 I

64K BYTES

16 15
SEGMENT

SMALL SEGMENT 1

64K BYTES

SMALL SEGMENT
32767

64K BYTES

OFFSET

LARGE SEGMENT 0

31 30

111

16M BYTES

2423
SEGMENT

LARGE SEGMENT 1

16M BYTES

LARGE SEGMENT
127

16M BYTES

OFFSET

figure 11-3.
Me.»ry Address Space in 5eg11ented Mode

4-2

8225-004,005

Address Spaces and Memory Management
a

.........I
"!,
L.I....I.....L..~~

•

BYTE

ADDR."n
15

WORD

ADDRElln

ADDRElln+1
0

ADDR."n

ADDRU'n+1

I I I I I
ADDR."n+a

LONGWORD

figure ___ •
Bytes, Worde, .-xl LlJI1!IImrda in tte.ory

_.2.2

Logical I/O Addrees Space

space. The process of translating logical memory
addresses is described in the following section.

Al though logical I/O addresses are 32 bits, only
the 16 low-order bits of a logical I/O address can
be manipulated; the CPU always forces the 16 highorder bits to O.
Unlike logical memory address spaces, logical I/O
address space is not viewed as a string of bytes
at consecutive addresses. Rather, the address is
simply used to locate a byte, word, or longword
peripheral port. The byte port located at address
n does not have to be contiguous with the byte
port located at address n+1, nor must it be the
more significant byte of the word port located at
address n. Logical I/O addresses can be either
even or odd.

Physical addresses are in physical memory space or
physical I/O space.
The two physical address
spaces are distinguished by different status and
timing on the external interface (see Chapter 8).
Also, copies of physical memory locations can be
stored in the cache, but copies of physical I/o
locations cannot.
Physical addresses in both
(Note that the external
spaces are 32 bits.
interface provides information distinguishing
between memory references for instructions and
data, and between system and normal modes. This
information should not be used, however, to separate physical memory addresses into different
spaces when the cache mechanism is enabled,
because the cache does not distinguish separate
physical memory address spaces.)

The CPU featurea a memory management mechanism
that translates logical memory addresses to physical addresses and protecta for execute, read, and
write accesses. The memory msnagement mechanism
serves four functions:
relocation, protection,
sharing, and virtual memory.
Relocation maps a logical address to a potentially
different physicsl address. This allows multiple
processes to use the sarne logical addresses for
distinct physical memory locations. Paged address
translation divides the logical address spaces
into fixed-size units, called pages, and the physical address spaces into fixed-size units, called
frames. A logical page can be mapped to an arbitrary phyaical frame.
Because the pages and
frames are of fixed and equal size, memory allocation is simplified.
Protection limits the type of access a process can
make to a logical address. A segment or individual page can be protected against instruction
fetches, operand fetches, or operand stores in
either normal or system mode. The protection featurea of the CPU provide security for aensitive
data or programs, auch aa proprietary code
modules, that should not be copied or modified.
The CPU also allows protected access by application programs to selected peripherals (memorymapped I/O).
Sharing of phyaical memory by multiple processes

The CPU maps logic a 1 addresses to physical
addresses. Addresses in logical I/O space map to
identical addresses in physical I/O space.
Addresses in logical memory spaces map to
addresses in physical memory space or physical I/O
8225-006

is supported by relocation and protection. Logical addresses for several processes can map to the
same physical address.
The access protection
attributes for each process may differ.

4-3

Address Spaces and Memory ManaQement
Virtual _Dry means that the range of logical
addresses used by a process can be larger than the
allocated physical memory.
When a reference is
made to a logical address that is not mapped to a
physical address, an exception occurs. 'After the
missing page is transferred from secondary storage
to main memory, the process can simply be
restarted.
The CPU provides information about
pages that have been referred to or modified,
thus helping the operating system allocate memory
efficiently.

The memory management mechanism is selectively
controlled for references in system or normal
spaces by two bits in the System Configuration
Control Longword register (SX and NX). When the
memory management mechanism is disabled, the physical address used for the reference, which is in
physical memory space, is identical to the logical
address and all accesses are permitted. The following sections describe address translation and
access protection when the memory management mechanism is enabled.

•• 3.1

(TLB) that stores the translation information for
the 16 most recently used pages in a fully
associative memory.
For each memory reference,
the logical page address is compared wi th the
address tags in the TLB (Figure 4-5). If a matching address tag is found, the corresponding frame
address is read from the TLB and used to complete
the translation.
When information needed to
translate the page is missing from the TLB, the
CPU automatically refers to tables in memory to
perform the translation.
The CPU then loads the
missing translation information into the TLB,
replacing the TLB entry of the least recently
referenced page.

Address Translation

The page size used by the CPU .is 1K bytes. The
translation process involves mapping a logical
page, which is specified by the 22 most-significant bits of the logical address, to a physical
frame, which is specified by the 22 most-significant bits of the physical address. The 10 leastsignificant address bits, which specify the byte
within a page or frame, are identical for the logical and physical address.
A logical page can
generally map to an arbitrary physical frame,
except for a restriction that applies only when
physical memory modules with different data path
widths are used and operands can be located across
consecutive logical pages.
Refer to section 8.6
for more information.

Thus, the TLB acts as a buffer for the most
recently used page descriptors.
This buffer is
automatically maintained by on-chip hardware.*

The CPU contains a Translation Lookaside Buffer
31

LOGICAL ADDRESS

10 9
PAGE ADDRESS

\ PAGE OFFSET I

""" >TRANSL ATION
LOOKA SIDE
BUFFER

LOGICAL PAGE
ADDRESS TAGS

PHYSICA LADDRESS

figure "'5.

~,l.
FRAME ADDRESS

10 9

...

\FRAMEOFFSETI

Address Translatim Using the TLB

The address tags in the TLB are extended from 22
to 24 bits.
The extra bits identify the memory
address space for the page. Thus, references to
pages with the same page number but in different
address spaces are translated differently.
The
frame addresses in the TLBs are also augmented
with
the
access
protection
code
and
the
Non-Cacheable and Modification bits from the page
table entry.

4-4

PHYSICAL
FRAME
ADDRESSES

*The number of entries, degree of associativity,
and replacement algorithm described for the TLB
design in this section are speci fic to the first
implementation of the Z8D,DDD CPU architecture and
may differ in future products implementing the
same architecture. Differences in the characteristics can impact systems performance, but have no
effect on the function of software or the external
interface.

2071-005

Address Spaces and Memory Management
4.'.2

Loading the 11.B

level-1 field (l1), sn B-bit level-2 field (l2), a
6-bit page number field (P), and a 1O-bit page
offset field (P-OFFSET). When loading the TlB,
the l1, l2, and P fields are used as indexes into
the different translation table levels. (Figure

To load the TlB with the information needed to
translate a page address, the CPU automatically
fetches entries from up to three levels of tables
in physical memory.
Figure 4-6 shows the
partition of a logical address into an B-bit
31

24 23

10 8

16 15

,I,

4-7).

,I,

P·OFFSET
,
!
,

Figure 4-6.
Logical Address Partition for Address Tr_Iation

-e--

-$TABLE DESCRIPTOR
REGISTERS

31
LOGICAL A DDRESS

I
L1

PAGE TABLE

LEVEL 2
TABLE

LEVEL 1
TABLE

24 23

16 151109
LO

pip-OFFSET

109
FRAME ADDRESS

0
ATTRIBUTES

TABLE
I PAGE
ENTRY

l
TRANSLATION
LOOKASIDE
BUPPER

LOGICAL PAGE
ADDRESS TAGS

PHYSICAL

FRAME
ADDRESSES

Figure 4-7. Auta.atic Loading of the 11.B
Using Tables in tte.ory

When the address space is not fully used, the
first-level and second-level translation tables
can be selectively skipped to reduce the storage
for tables and the number of memory references
required to autoload the TlB. The level-1 tables
can be akipped when an address space of 16M bytes
is sufficient. The level-2 tables can be skipped
for compatibility with ZBOOO segmented addresses.
Both level-1 and level-2 tables can be skipped for
compact addresses.
When a level of tables is
skipped, the corresponding field of the logical
address is ignored.

8225-007, 2071-006

When the address spaces are not separated, it is
also possible to reduce storage for tables by
loading identical values into the translation
table descriptor registers. The same tables would
then be used to translate addresses in different
spaces. The following sections describe the formats of the translation table descriptors and
entries and explain the translation algorithm.

4-5

Address Spaces and Memory Management
4.J.2.1
Tr_lation Table Descriptor Registers.
There is a translation table descriptor register
for each of the four logical memory address
spaces: System Instruction Translation Table
Descriptor
(SITTD),
System Data Translation
Table Descriptor (SDTTD), Normal Instruction

Translation Table Descriptor (NITTD), and Normal
Data Translation Table Descriptor (NDTTD).
The
translation
table
descriptor
registers
are
accessed using the Load Control Long instruction.
Figure 4-8 shows the format of a translation table
descriptor.

31 30

I I I
I

TABLE FORMAT (TF)
TABLE SIZE (SIZ)
PROTECTION (PROT)
'----------------------

~:~~ tJ~TE~ TABLE
GROWTH DIRECTION (G)

Table Format
(TF)

00
01
10
11

THREE LEVELS
SKIP LEVEL 2 TABLES
SKIP LEVEL 1 TABLES
SKIP LEVEL 1 AND LEVEL 2 TABLES

VALID TABLE ENTRIES
0= 1
0=0

TABLE SIZE
(SIZ)

o TO 63
o TO 127
o TO 191
o TO 255

00
01
10
11

Figure 4-8.
The Table For_t field (TF) specifies the
ture of the translation tables. The table
can be a full three levels, two levels with
level-1 tables or level-2 tables skipped,
level with both level-1 and level-2
skipped.

o TO 255
64 TO 255

128 TO 255
192 TO 255

Translation Table Descriptor
strucformat
either
or one
tables

Next level Table Base (NlTB) specifies 23 bita of
the base address in physical memory of the next
level table. The full 32-bit address is formed by
extending NL TB with one high-order 0 and eight
low-order Os (Figure 4-9).
Growth Direction (G) specifies the growth direction of the next level table from low address to
high address (G=O) or from high address to low
address (G=1). The reverse growth direction (G=1)
is used for downward-growing stacks.

When the next level table is a page table, then
the G and SIZ fields must be 0 because a page
table always has 64 entries.
Protection (PROT) specifies the access protection
code (see Table 4-1).

4.3.2.2 level-l Table Entries. The L1 field of
the logical address selects one of up to 256
entries in the level-1 table. Figure 4-10 shows
the format of a level-1 table entry.
Valid (V) determines the validity of the G, NLTB,
and SIZ fields. If the V bit is 1, the fields are
valid; otherwise, the fields are invalid.
The
PROT field is always valid.
Growth

The Table Size field (SIl), in conjunction with
the Growth Direction fie ld, specifies the valid
portion of the next level table in increments of
256 bytes.
When only part of a table contains
valid entries, storage for many invalid entries
can be eliminated through use of the SIZ field.

4-6

direction (G), Next Level Table Base
Table Size (SIl), and Protection (PROT)
have the same meaning as in the translation table
descriptor registers.
(Nlm) ,

Bit 0 of the level-1 table entry is reserved and
must be O. This bit is ignored by the translation
mechanism.

2071.(J()7

Address Spaces and Memory Management
31 30

NLTB
!

31 30

, ,

Figure __9.

0
,

TRANSLATION TABLE
BASE ADDRESS

•

87
!

Translation Table Base Address

3130

!.!'!!"

TRANSLATION TABLE
DESCRIPTOR OR ENTRY

I /01

-r '--

VALID (V)

L - TABLE SIZE (SIZ)

L-_ _ _ _ _ PROTECTION (PROT)

'--------------------- ~m ~~~TE~

L ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

TABLE
GROWTH DIRECTION (G)

LEVEL 1 TABLE ENTRY
31 30

8
!

' - - VALID (V)
1-_ _ _ _ _ _ PROTECTION (PROT)
' - - - - - - - - - - - - - - - - - - - - - NEXT LEVEL TABLE
BASE (NLTB)

LEVEL 2 TABLE ENTRY
31 30

10 9
!

7
,

II" I

I I I L':: ::.~:~~ ,.
~

MODIFICATION (M)
NONCACHEABLE (NC)
PROTECTION (PROT)

' - - - - - - - - - - UNUSED
' - - - - - - - - - - - - - - - - - - - - - - FRAME ADDRESS (FA)
L---------------------------------IIO

PAGE TABLE ENTRY

figure __10.

Table £ntry forllllts

4.3.2.3 level-2 Table £ntries.
The L2 field of
the logical address selects one of up to 256
entries in the level-2 table. Figure 4-10 shows
the format of a level-2 segment table entry.

4.3.2.4 Page Table Entries. The P field of the
logical address selects one of 64 entries in the
page table. Figure 4-10 shows the format of a
page table entry.

Valid (V) determines the validity of the NUB
field.
If the V bit is 1, the field is valid;
otherwise the field is invalid. The PROT field is
always valid.

Valid (V) determines the validity of the I/O, FA,
Ne, M, and R fields.
If the V bit is 1, the
fields are valid; otherwise, the fields are
invalid. The PROT field is always valid.

Next level Table Base (NlTB) and Protection
(PROT) have the same meaning as in the translation
table descriptor registers.

I/O determines whether the address of the frame is
in physical memory space or physica 1 I/O space.
When I/O is 0, the frame is in memory space; when
1, the frame is in I/O space.

Bits 0, 2, 3 and 31 of the level-2 table entry are
reserved and must be O.

2071-008

4-7

Address Spaces

and~Memory

Management

Fra.e Address (FA) specifies the physical address
of the frame corresponding to the logical page.
The address is formed by appending ten low-order
as to the I/O bit and the FA field.

Table 4-1.
Protection Field Encoding

Non-Cacheable (NC) is used to maintain the integrity of the cache. If the NC bit is 1, copies of
memory locations in this frame cannot be stored in
the cache; otherwise, copies of memory locations
in this page can be stored in the cache.
For
example, the NC bit can be set for a page shared
by multiple processes with write access in a system containing multip Ie CPUs.
The NC bit has
meaning only when the frame is in physical memory;
I/O locations are never stored in the cache. See
Appendix C for more information.
Modification (M) and Reference (R) bits are used
by
software
to
implement
virtual
memory
replacement algorithms. The CPU sets the R bit of
the page table entry when the page is first
referred to, either for fetching or storing
information. The CPU sets the M bit of the page
table entry when an operand is first stored to the
page.
The CPU refers to translation tables in
memory to set the M bit on the first store to the
page, even if the translation information for the
page is present in the TLB because of a previous
fetch from the page.
The CPU uses inter locked
memory references (see Section B.8.2.3) to set the
Rand M bits in the page table entry, allowing
page tables to be shared between tightly-coupled
multiprocessors.

NA R W E Next

Encoding

Systt.

Noral

0000
0001
0010
0011

NA
RE
RE
RE

NA
NA
E
RE

0100
0101
0110
0111

E
E
R
R

NA
E
NA
R

1000
1001
1010
1011

Next
RW
RW
RW

Next
NA
R
RW

1100
1101
1110
1111

RWE
RWE
RWE
RWE

NA
E
RE
RWE

no access is permitted
read access is permitted
write access is permitted
execute access is permitted
- Use the protection field of the
next level translation table; for
page table entries, a PROT field of
1000 indicates no access is permitted.

Protection (PROT) specifies the access protection
code described below.
Bits 8 and 9 of the page table entry are available
for use by software; the bits are ignored by the
translation mechanism.

Dur ing the translation process, a PROT field is
encountered at each level. The first PROT field
with value other than 1000 is selected; the other
PROT fields are ignored. If all PROT fields up to
and including the page table entry are 1000, no
access is permitted.

4.'.' Access Protection
The memory management mechanism enforces access
protection for segments and pages using information encoded in the PROT field of translation
table descriptors and table entries.
The CPU
checks three types of access operations: execute,
read and write.
Execute access is required for
instruction fetches, including Immediate mode
operand fetches.
Read access is required for
operand fetches other than Immediate mode. Write
access is required for operand stores.
The CPU
allows different access rights for normal and
Table 4-1 shows the
system mode programs.
interpretation for the PROT code.

4-8

4.3.4 Address Translation Algorithl
The CPU executes the following ~lgorithm to translate a logical address using the tables in memory
when loading a missing entry into the TL8 or setting the M bit on the first store to a page.
Step 1. Translation Table Descriptor Processing.
One of the four translation table descriptor registers is selected according to the logical
address space.

Address Spaces and Memory Manaqement
If the PROT field of the segment table descriptor
is 1000, the intended access operation is not
checked. Otherwise, if the intended access operation is not permitted by the PROT field, an
Address Translation trap (access protection violation) occurs.
The G, NLTB, and SIZ fields are passed to the next
step of the address translation algorithm.
If the TF field is 00 or 01, then go to Step 2; if
the TF field is 10, then go to Step 3; otherwise,
go to Step 4.
Step 2.
level-1 Table Entry Processing.
The
L1 field of the logical address is checked with
the G and SIZ fields from Step 1. If G is 0 and
L1 is greater then 64 x (SIZ+1) -1 or i f G is 1
and L1 is less then 64 x SIZ, an Address Translation trap (invalid table entry) occurs.

The address of the level-1 table is formed by
extending the NUB fie Id from Step 1 with one
high-order 0 and eight low-order Os. The physical
address of the level-1 table entry is calculated
by adding 4 x L1 to the address of the level-1
table. The addition is a 32-bit unsigned arithmetic operation, ignoring the carry from the mostsignificant bit position.
The selected level-1 table entry is fetched from
memory.
I f the intended access operation was
checked at Step 1 or the PROT field of the table
entry is 1000, the intended access operation is
not checked at this step.
Otherwise, if the
intended access operation is not permitted by the
PROT field, an Address Translation trap (access
protection violation) occurs.
If the V bit of the table entry is 0, an Address

The address of the level-2 table is formed by
extending the NL TB fie ld from the previous step
with one high-order 0 and eight low-order Os. The
physical address of the level-2 table entry is
calculated by adding 4 x L2 to the address of the
level-2 table. The addition is a 32-bit unsigned
arithmetic operation, ignoring the carry from the
most-significant bit position.
The selected level-2 table entry is fetched from
memory.
If the intended access operation was
checked at a previous step or the PROT field of
the table entry is 1000, the intended access
operation is not checked.
Otherwise, if the
intended access operation is not permitted by the
PROT field, an Address Translation trap (access
protection violation) occurs.
the V bit of the table entry is 0, an Address
Translation trap (invalid table entry) occurs.

The NL TB field of the table entry is passed to
Step 4.
The
Page Table Entry Processing.
address of the page table is formed by extending
the NUB field from the previous step with one
high-order 0 and eight low-order Os. The physical
address of the page table entry is calculated by
adding 4 x P to the address of the page table.
The addition is a 32-bit unsigned arithmetic
operation, ignoring the carry from the most-significant bit position.

Step II.

The selected page table entry is fetched from memory.
If the intended access operation was not
checked at a previous step, and the intended
access operation is not permitted by the PROT
field, an Address Translation trap (access protection violation) occurs.

Translation trap (invalid table entry) occurs.
If the V bit of the table entry is 0, an Address

The G, NUB and SIZ fields of the table entry are
passed to the ne.xt step of the address translation
process.
If the TF field of the segment table descriptor is
00, then go to Step 3; otherwise go to Step 4.
The L2 field
level-2 Table Processing.
of the logical address is checked with the G and
SIZ field from the previous step. If G is 0 and
L2 is greater than 64 x (SIZ+1}-1 or if G is 1 and
L2 is less than 64 x SIZ, an Address Translation
trap (invalid table entry) occurs.

Step 3.

Translation trap (invalid table entry) occurs.
If the R bit of the table entry is 0, the CPU sets
R to 1. If the M bit is 0 and the access operation is write, the CPU sets M to 1. If either the
R or M bit changes, the CPU writes the low-order
byte of the table entry back to memory; otherwise,
the table entry is unchanged.
Finally, the I/O, FA, NC, M, and selected PROT
fields are loaded into the TLB, along with the
associated logical page address.

4-9

Address Spaces and Memory Management
address space that caused the trap.
When both
types of address translation exception are
detected, an access protection violation is indicated.

4.'.5 Address Translation Exceptions
The CPU detects two types of address translation
exception conditions: access protection violation
and invalid table entry.
When either of the
exception conditions is detected, the CPU suspends
the instruction being executed and processes an
Address Translation trap. During trap processing
the CPU saves on the system stack the PC, the FCW,
an identifier word, and the logical address that
caused the trap.
The saved PC value is the
address of the first word of the instruction that
caused the trap.
The identifier word (Figure
4-11) indicates the type of exception and the
15

When an Address Translation trap occurs, the CPU
saves the state of registers and memory so the
instruction can simply be restarted.
The
instruction can be successfully completed by
eliminating the exception condition, popping the
violation address from the system stack, and
executing the Interrupt Return instruction. Refer
to Chapter 7 for more information about exception
processing.
3

1 0 ,0,0,0,0,0,0,0,0,0,0,0,01 I

00
01
10
11

NORMAL DATA SPACE
NORMAL INSTRUCTION SPACE
SYSTEM DATA SPACE
SYSTEM INSTRUCTION SPACE

INVALID TABLE ENTRY
ACCESS PROTECTION VIOLATION

Figure 4-11.
Address Translation Trap Identifier Word

4.'.6

~ry

Manageaent Instructions

The CPU provides several privileged instructions
directly concerned with memory management.
The
Load Normal instructions permit system mode programs to refer to normal address spaces.
These
instructions check access rights using system mode
privilege.
The Load Physical address instructions translate a
logical address in any of the memory address
spaces and load the corresponding physical address
into a register. The CPU sets the flag bits in
the FCW to indicate the access rights and whether
the translation is valid. Although the CPU does
not refer to the location of the translated
address, the R bit in the page table entry is set
by this instruction.

4-10

Three types of instructions allow outdated information to be eliminated from the TLB when the memory map is changed by altering one of the translation table descriptor registers or translation
table entries. When a page table entry is altered
(other than setting the R, M, or V bits), then one
of the Purge TLB Entry instructions can be used to
remove the translation information for the page
from the TlB. The Purge TLB Normal instruction
removes all normal space entries from the TLB.
This instruction is used when the normal space
memory map is changed, but the system space memory
map remains the same. For example, the operating
system executes the Purge TLB Normal instruction
when a process switch occurs as long as system and
normal address spaces are separate. The Purge TLB
instruction removes all entries from the TLB.

8225-009

Chapter 5.
Addressing Modes and
Address Calculations
5.1

INTRODUCTION

The CPU locates operands (the data manipulated by
instructions) in registers, memory, peripheral
ports, or in the instruction.
Figure 5-1 shows
the nine addressing modes used to specify the
location of operands.
Although most operations
can use any of the addressing modes, certain
operations, such as Load Control, allow only a
restricted set of addressing modes.
This chapter describes the addressing modes and
the way operand addresses are calculated.
Examples are given for compact, segmented, and linear
modes of address representation. Chapter 6 prov ides details about the encoding of addressing
modes and the addressing modes allowed for each
operation.

5.2 ADDR£SS CALCULATIONS
When an operand is in a logica 1 memory address
space, the "effective address" of the operand is
calculated using a base address, an optional index
value, and an optional displacement.
The base
address is located in a general-purpose register,
the Program Counter (PC), or the instruction. The
index value is located in a word or longword register.
The displacement is located in the
instruction. The following sections describe the
calculations of effective addresses in compact,
segmented and linear modes.
When an operand is in logical I/O space, no
address calculation is necessary.
The 16-bit
address of the I/O port is located in a word register or in the instruction.

5.2.1

CoIIpact Address Calculations

In compact mode, addresses are 16 bits. The base
address for the effective address calculation is
located in either a word register other than RO,
the low-order word of the PC, or a word of the
instruction. When an index value is used, it is
located in a word register other than RD.
The
displacement is encoded in 16 or fewer bits of the
instruction. When the displacement is encoded in
fewer than 16 bits, it is extended to 16 bits for

effective address calculation. Displacements are
generally extended by replicating the sign (mostsignificant) bit in the high-order bit positions,
but for the Decrement and Jump if Not Zero (DJNl)
instruction, the displacement is extended with
Os. In compact mode, it is not possible to specify both an index value and a displacement for
effective address calculation.
The effective address is generally cslculated by
adding the base address to the optional index
value or displacement, but for the Call Relative
(CALR) and DJNZ instructions, the displacement is
subtracted from the base address. Addresses are
calculated using 16-bit arithmetic.
Carry and
overflow from the most-significant bit position
are ignored.
Thus, addresses wraparound with
address 0 appearing to follow address 65,535.
The following example shows an effective address
calculation with base address 123416 and index
value or displacement FEDC16.
The effective
address is 111016

base address

1234

index value or
displacement
effective address

FEDC
1110

5.2.2 Seg.ented Address Calculations
In segmented mode, addresses are 32 bits.
The
base address for the effective address calculation
is located in either a longword register other
than RRO, in the PC, or in one or two words of the
instruction.
(A concise representation of the
32-bit base address using a single instruction
word is available for some addresses.
Refer to
Section 6.4.3.2 for more information.)
When an
index value is used, it is located in a word register other than RO or a longword register other
than RRO. An index value located in a word register is extended to 32 bits for effective address
calculation by replicating the sign (most-significant) bit in the high-order bit positions.
The
displacement in an instruction is encoded in 32 or
fewer bits. When the displacement is encoded in
fewer than 32 bits, it is extended to 32 bits for
effective address calculation. Displacements are
5-1

Addressing Modes and Address Calculations
Addressing Mode

Operand Addressing

In the Instruction

R
Register

Operand Value
In Memory

In a Register

r-.I

The contents of the
register

OPERAND

1M
Immediate

In the instruction

OPERAND

*IR
Indirect
Register

Direct
Address

ADDRESS

r-.[I=A~D~D~R~ES~S=}----__' ·[I~O~P~E~RA~N~DJ

OPERAND

*X
Index

t~~j--=='NDE=X:::::...h~0---Ir-----'
• OPERAND

*BA
Base
Address

I BASE ADDRESS h

t~~~~=~~=====--:'0--1

OPERAND

*BX
REGISTER NUMBER

Base
Index

OPERAND

DISPLACEMENT

RA
Relative
Address

PC ADDRESS

[~D~IS~PL~A~C~EM~E~N~TJ~~=====-. .~~I

OPERAND

*RX

The contents of the
location whose
address is in the
register

The contents of the
location whose
address is in the
instruction

The contents of the
location whose
address is the address
in the instruction, plus
the contents of the
Index Register
The contents of the
location whose
address is the
contents of the Base
register, plus the
displacement in the
instruction
The contents of the
location whose
address is the
contents of the Base
register, plus the
contents of the Index
register, plus the
displacement in the
instruction
The contents of the
location whose
address is the
contents of the
Program Counter, plus
the displacement in
the instruction
The contents of the
location whose
address is the
contents of the
Program Counter, plus
the contents of the
Index register, plus the
displacement in the
instruction

Relative
Index

*RO and RRO cannot be used for Indirect, Base, or Index registers

Figure 5-1.

5-2

Addressing ItJdes

2071·009

Addressing Modes and Address Calculations
generally extended by replicating the sign (mostsignificant) bit in the high-order bit positions,
but for the Decrement and Jump if Not Zero (DJNZ)
instruction, the displacement is extended with
Os.
1615

SEGMENT
(
!
t,

, I,

OFFSET
,

(I) 84K BYTE SEGMENT SIZE
3130

2423
I

Another example shows an effective address calculation for a large segment with base address
«lsH3» 13579B16, index value FFFFFFEO, and displacement OOOOOOOZ.
The effective address is
«lsH3» 13577D16.
segment number
base address
«lsI13»
+ index value
+ displacement
effective address «lsH3»

segment offset
13579B
FF FFFFEO
00 OOOOOZ
13577D

(II) IBM BYTE SEGMENT SIZE

Figure 5-2.

Seglleflted Addresses

In segmented mode, the base address is composed of
a segment number and segment offset. Bit 31 of an
address distinguishes between two segment sizes
(Figure 5-2). When bit 31 of. the address is 0,
the segment number is 15 bits and the segment offset is 16 bits, providing a maximum segment size
of 64K bytes. Addresses for these small segments
are written using the notation «ssH segment number» segment_offset. For example, small segment
number five at offset 231A16 would be written
«ssH5» 231A16. When bit 31 of the address is 1,
the segment number is 7 bits and the segment offset is 24 bits, providing a maximum segment size
of 16M bytes. Addresses for these large segments
are written using the notation «IsH segment number» segment_offset.
The effective address is generally calculated by
adding the base address to the optional index
value and optional displacement, but for CALR and
DJNZ instructions, the displacement is subtracted
from the base address. Only the segment offset is
involved in address arithmetic. The segment size
and segment number of the effective address are
the same as the base address.
The offset
calculation uses 16-bit arithmetic for the small
segments and 24-bit arithmetic for the large
segments.
Carry and overflow from the mostsignificant bit position are ignored.
Thus,
addresses wraparound within a segment. This means
that, for the small segments, offset 0 appears to
follow offset 65,535.
For the large segments,
offset 0 appears to follow offset 16,777,215.
The following example shows an effective address
calculation for a small segment with base address
«ssH2» 5678 16 , index value OOOOBA9B16, and displacement FFFFFFFF 16.
The effective address is
«ssHZ» 110F16.
Segment Number
«ssHZ»
base address
+ index value
+ displacement
effective address «ssHZ»
8225-010

Segment Offset
5678
0000 BA98
FFFF FFFF
110F

5.2.3 linear Address Calculations

In linear mode, adc;lresses are 32 bits. The base
address for the effective address calculation is
located in either a longword register other than
RRO, in the PC, or in one or two words of the
instruction.
(A concise representation of the
32-bit base address using a single instruction
word is available for some addresses.
Refer to
Section 6.4.3. Z for more information.)
When an
index value is used, it is located in a word
register other than RO or a longword register
other than RRO. An index value located in a word
register is extended to 3Z bits for effective
address calculation by replicating the sign
(most-significant) bit in the high-order bit
positions. The displacement in an instruction is
encoded in 32 or fewer bits.
When the
displacement is encoded in fewer than 32 bits, it
is extended to 32 bits for effective address
calculation. Displacements are generally extended
by replicating the sign (most-significant) bit in
the high-order bit positions, but for the
Decrement and Jump if Not Zero (DJNZ) instruction,
the displacement is extended with Os.
The effective address is generally calculated by
adding the base address to the optional index
value and optional displacement, but for CALR
and DJNZ
instructions the displacement is
subtracted from the base address. Addresses are
calculated using 3Z-bit arithmetic.
Carry and
overflow from the most-significant bit position
are ignored.
Thus, addresses wraparound with
address 0 appearing to follow address Z32-1.
The following example shows an effective address
calculation with base address 0100000016' index
value 00000064 16 , and displacement FFFFFF9B16.
The effective addresa is 00FFFFFF16.

base address
+ index val ue
+ displacement
effective address

0100
0000
FFFF
OOFF

0000
0064
FF9B
FFFF
5-3

Addressing Modes and Address Calculations

5.' ADDRESSING MODE DESCRIPTIONS
The following sections describe the nine addressing modes.
Each description explains how the
operand is located, shows the assembler language
syntax used, and works through an example. The
descriptions are grouped into two sections--one
for compact mode and the other for segmented and
linear modes. In the examples, hexadecimal notation is used for memory addresses and the contents
of register and memory locations. The % symbol
5.'.1.1 Register (R).
For Register addressing
mode, the operand is located in the specified general-purpose register. Storing data in a register
allows shorter instructions and faster execution
than storing data in memory.
The register size
(byte, word, long word , or quadword) is specified
by the instruction opcode.

INSTRUCTION
OPERATION

precedes hexadecimal numbers in assembler language
text.
When the examples refer to memory locations, logical addresses are used; the logical
addresses are translated to physical addresses if
memory management is enabled.

5.'.1

COIIpuct Mode Descriptions and Exa8ples

This section describes the addressing modes used
in the compact mode of operation.

Assembler language syntax:
RHn, RLn
Rn
RRn
ROn

Example of R mode:
LOL RR20,RR22

I/Ioad the contents
I/of RR22 into RR20

Before Execution

After Execution

OPERAND'

Byte register
Word register
Longword register
Ouadword register

THE OPERAND VALUE IS THE CONTENTS OF THE REGISTER.

5.'.1.2 I..adiate (1M). For Immediate addressing
mode, the operand is located in the instruction.
Because an immediate operand is part of an
instruction, it is located in one of the instruction memory address spaces.
Small immediate
values are used frequently, so the instruction set
provides several concise encodings for these
cases.

Assembler language syntax:
#data

Example of 1M mode:
LOB RH2,#%55

//load 5516 into RH2

Before Execution

After Execution

RR21671s91121341

RR21ssls91121341

INSTRUCTION

THE OPERAND VALUE IS IN THE INSTRUCTiON.

Indirect Register (IR). For Indirect
5.'.1.'
Register addressing mode, the operand is located
at the address contained in the specified generalpurpose word register.
Any word register other
than RO can be used. Depending on the instruction
opcode, the operand is located in one of the data
memory address spaces or in I/O address space.
Indirect Register mode has a short encoding and
can be used to simulate more complex addressing
modes by computing the address into a register.
INSTRUCTION

OPERATION

ADDRESS

Example of IR mode:
LO R2,@R5

OPERAND

//load R2 with the
I/data addressed
I/by the contents
Ilof R5

Before Execution
Data Memory

1/0 oR
DATA MEMORY

THE OPERAND VALUE IS THE CoNTENTS of THE LOCATiON WHoSE ADDRESS
IS IN THE REGISTER.

5-4

Assembler language syntax:
@Rn

After Execution

Addressing Modes and Address Calculations
5.'.1._ Direct Address (DA). For Direct Addrees
addressing mode, the opersnd is located at the
address specified in the inetruction. Depending
on the instruction opcode, the operand is located
in one of the data memory address spaces or in I/O
address spsce.

OPERAND

Ilload RR30 with the
I/Iongword whose
lIaddress is 5E2316

Before Execution

Data Memory

RR3016789A4381

1/0 OR
DATA MEMORY

Example of DA mode:
LDL RR30, %5E23

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION
WHOSE ADDRESS IS IN THE INSTRUCTION.

After Execution
RR30 1020304051

Assembler language syntax:
address

Either memory or I/O

5.'.1.5 Index (X). For Index addressing mode the
operand is located at the address calculated by
adding the address specified in the instruction to
the index vslue contained in the specified general-purposa word register.
Any word register
other than RO can be used. The operand is located
in one of the data memory address spaces. Index
addressing mode can be used for random access to
tables or other complex data structures where the
address of the base of the table is known, but the
particular element index must be computed by the
program.

Example of X mode:
LDL RR8, %231A(R7) IIload RR8 with the
IIlongword whose
lIaddress is 231A +
lithe value in R7

Before Execution

Data Memory

Address Calculation

Assembler language syntax:

231A
+OlFE
2518

address(Rn)

After Execution

INSTRUCTION

I-----I
It.==~A~D~D~RE~S~S~=j~-~====:~1
~PERATION

INDEX

DATA
MEMORY
OPERAND

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS THE
ADDRESS IN THE INSTRUCTION PLUS THE CONTENTS OF THE REGISTER.

5-5

Addressing Modes snd Address Cslculations
5.}.1.6 Base Addre8a (BA).
For Bass Address
sddressing mode, the operand is locsted at the
address calculated by adding the displacement contained in the instruction to the address contsined
in the specified general-purpose word register.
Any word register other than RO can be used. The
operand is located in one of the data memory
In compact mode, Base Address
eddr-ess spaces.
addressing mode can only be used with Load and
Load Address instructions.
This restriction is
not significant, however, becauee Index and Base
Address addressing modes perform equivalent
functions in compact mode.

Example of BA mode:
LDL R5(%18),RR2

//load RR2 into the
//Iongword whose
/laddress is the base
/laddress in
/lR5 + 1816

Before Execution

Data Memory

Address Calculation
20AA
+0018

Assembler language syntax:

2OC2

Rn (disp)

After Execution

INSTRUCTION

Data Memory

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS THE
CONTENTS OF THE REGISTER PLUS THE DISPLACEMENT IN THE INSTRUCTION.

5.}.1.7
Base Index (BX).
For Base Index
sddressing mode, the operand is located at the
address cslculated by adding the index value contained in the specified general-purpose word index
register to the base address contained in the
specified general-purpose word base register. Any
word register other than RO can be used for the
index register or base register. The operand is
located in one of the data memory address spaces.
Base Index addressing mode can be used to access
tables or other complex data .structures when the
base of the table and particular element index are
not known until the program is executed.
In
compact mode, Base Index addressing mode can only
be used with Load and Load Address instructions.

Example of BX mode:
LDL RR2,R5(R3)

//load RR2 with the
//Iongword. whose
/laddress is the base
/laddress in R5 + the
/lvalue in R3

Before Execution

Data Memory

Address Calculation
1502
+FFFE

1"500
Assembler language syntax:

After Execution

Rn(Rm)

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS THE
CONTENTS OF THE BASE REGISTER PLUS THE CONTENTS OF THE INDEX REGISTER.

5-6

Addressing Modes and Address Calculations
5.'.1.8
Relative Address (RA). for Relative
Address addressing mode, the operand is located at
the address calculated by adding the displacement
contained in the instruction to the low-order word
of the Program Counter. The value used for the PC
is the address of the instruction word following
the displacement. The operand is located in one
of the instruction memory address spaces.
In
compact mode, Relative Address addressing mode can
only be used with Load, Load Address, Call, Jump,
and DJNI instructions.

Because the Program Counter will be
advanced to pOint to the next instruction when
the address calculation is performed, the
displacement in the instruction is actually + 2
(fou r less than the offset given by the
assembler language syntax).
Before Execution

Instruction Memory

-Instruction

0200 31 02 00 02
0204 E8 02 FF FE

Assembler language syntax:

0208 AB CO B001

address
Example of RA mode: (Note that the symbol "$" is used for the address of the first
word of the current instruction.)
LDRL RR24,$ + %6

0204
+0002
0206

IIload RR24 with the
l!Iongword whose
lIaddress is the
lIaddress of the
lIfi rst word of
//the cu rrent
lIinstruction + 6
INSTRUCTION

Address Calculation

After Execution

PC
INSTRUCTION
MEMORY

OPERATION

DISPLACEMENT

OPERAND

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS THE
CONTENTS OF PC PLUS THE DISPLACEMENT IN THE INSTRUCTION.

Relative Index (RX). Relative Index
5.'.1.9
addressing mode cannot be used in compact mode of
operation.

5.'.2

5egEnted and linear Mode Descriptions and

EXllllples

This section describes the addressing modes used
in segmented and linear modes of operation. The
description is identical for the two modes of
address representation except that separate
examples are given for address calculations.

INSTRUCTION

OPERATION

OPERAND

THE OPERAND VALUE IS THE CONTENTS OF THE REGISTER.

Assembler language syntax:
RHn, RLn
Rn
RRn
RQn

Byte register
Word register
Longword register
Quadword register

Example of R mode:
LDL RR20, RR22

IIload the contents of
IIRR22 into RR20

Before Execution

5.'.2.1 Register (R).
for Register addressing
mode, the operand is located in the specified general-purpose register. Storing data in a register
allows shorter instructions and faster execution
than storing data in memory.
The register size
(byte, word, longword, or quadword) is specified
by the instruction opcode.

A fter Execution

5-7

Addressing Modes and Address Calculations
5.}.2.2 I.-ediate (IN). For Immediate addressing
mode, the operand is located in the instruction.
Because an immediate operend is part of en
inetruction, it is located in one of the instruction memory address spaces.
Small immediate
values are used frequently, so the instruction set
provides several concise encodings for these
cases.

Assembler language syntax:
itdata

Example of 1M mode:
LDB RH2 it%55

/lload 5516 into RH2

Before Execution

RR21671s91121341

INSTRUCTION

After Execution

RR21551s91121341
THE OPERAND VALUE IS IN THE INSTRUCTION.

5.}.2.} Indirect Register (IR).
For Indirect
Register addressing mode, the operand is located
at the address contained in the specified generalpurpose register.
Depending on the instruction
opcode, the operand is located in one of the data
memory address spaces or in I/O address space.
INSTRUCTION

OPERATION

UOOR
DATA MEMORY

J--.I

OPERAND

For memory addresses, any longword register other
than RRO can be specified; for I/O addresses any
word register other than RO can be specified.
Indirect Register mode has a short encoding and
can be used to simulate more complex addressing
modes by computing the address into a register.

Assembler language syntax:
1/0 address

@Rn
@RRn

Memory address

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS
IS IN THE REGISTER.

Example of segmented IR mode:

Example of linear IR mode:

LD R2,@RR4

/lload R2 with the
/lword whose address
/lis in RR4

LD R2,@RR4

//load R2 with the
/lword whose address
/lis in RR4

Before Execution

Data Memory

Before Execution

Data Memory

~sslP2~ 170A Aol2310BloE
~sslP2~ 170E 1olD3123145

After Execution

5-8

After Execution

Addressing Modes and Address Calculations

5.'.2..

Direct Addre8B (DA).
For Direct Address
addressing mode, the operand is located at the
address specified in the instruction. Depending
INSTRUCTION
I/O OR
DATA MEMORY

OPERAND

on the instruction opcode, the operand is located
in one of the dsta memory sddress spaces or in I/O
address space.

Assembler language syntax:
address

Either memory or 1/0

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION
WHOSE ADDRESS IS IN THE INSTRUCTION.

Example of segmented DA mode:
LDL RR30,
Example of segmented RA mode:
LDL RR24.<$+6> I/Ioad RR24 with the
I/Iongword whose
I/address is the
I/address of the
lIfi rst word of the
I/current instruction
1/+ 6
Because the Program Counter will be advanced to point to the next instruction when
the address calculation is performed. the
displacement in the instruction is actually + 2
(four less than the offset given by the
assembler language syntax).
Before Execution

Instruction Memory

Example of linear RA mode:
LDL RR24.<$+6>

IIload RR24 with the
IIlongword whose
lIaddress is the
I/address of the
lIfi rst word of
lithe current
lIinstruction + 6

Because the Program Counter will be advanced to point to the next instruction when
the address calculation is performed. the
displacement in the instruction is actually + 2
(four less then the offset given by the
assembler language syntax).
Before Execution

Instruction Memory

Instruction

..--'-..
~ss#O~0202

31 02 0002

~ss#O~0204

E8 02 FF FE

~ss#O~0208

AB CO Be

00000204 E802 FF FE

Address Calculation
~ssfO~0204

00000200 31 02 0002

0002
~ss#O~0206

After Execution

00000208

Address Calculation

AB CO SO 01

0000 0204
+0000 0002
0000 0206

After Execution

«»

Note: Brackets
enclosing the address can be
omitted for CALR, DJNZ, JR, and LDR inatructions.

5-13

Addressing Modes and Address Calculations

5.'.2.9 Relative Index (RX). for Relative Index
addressing mode, the operand is located at the
address calculated by adding the displacement
contained in the instruction to both the index
value contained in the specified general-purpose
register and the Program Counter.
Any word or
long word register other than RO or RRO can be used

for the index register. The value used for PC is
the address of the instruction word following the
disp lacement.
The operand is located in one of
the program memory address spaces. Relative Index
addressing mode can be used to access tables of
constants.

PC
ADDRESS
INSTRUCTION
MEMORY

INDEX

OPERAND

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS THE
CONTENTS OF THE pc, PLUS THE CONTENTS OF THE INDEX REGISTER, PLUS THE
DISPLACEMENT IN THE INSTRUCTION.

Assembler language syntax:

< address> (Rn)

Word index register
Longword index register
Example of segmented RX mode:
LDRL RR26, TABLE(RR28)
!/load RR26 with the
//Iongword whose
//address is TABLE plus
lithe index value in
IIRR28. TABLE is a
Iisymbol for the beginlining of a table of
IIconstants at offset
1110016 in the same
IIsegment as the
lIinstruction

< address> (RRn)

Before Execution

Example of linear RX mode:
LDL RR26, TABLE(RR28)
IIload RR26 with the
//Iongword whose
//address is TABLE plus
lithe index value in
IIRR4. TABLE is a
//symbol for the beginlining of a table of
//constants beginning
//at address 00010100
Before Execution

Instruction Memory

After Execution
After Execution

Note: Brackets enclosing the address «» can be
omitted for CALR, DJNZ, JR, and LDR instructions.

5-14

Instruction Memory

Addressing Modes and Address Calculations
5.~

EXTENDED ADDRESSING MODES

The instruction encodings for several of the
addressing modes use one or more extension words
Because the encoding of
following the opcode.
this group of addressing modes is similar, they
are collectively given the name Extended Addressing Modes (EAM).
The Extended Addressing Modes
for compact and segmented or linear mode are shown
in Table 5-1 below.
Refer to Section 6.4.3 for
more information about Extended Addressing Modes.

Table 5-1.

Extended Addressing Modes

COIIpsct

5egaented or linear

Direct Address
Index

Direct Address
Index
Base Address
Base Index
Relative Address
Relative Index

5-15

Chapter 6.
Instruction Set
6.1

INTRODUCTION

EX
EXB
EXL

dst,src

Exchange

LD
LDB
LDL

dst,src

Load

LDA

dst,src

Load Address

LDAR

dst,src

Load Address Relative

LDK
LDKL

dst,src

Load Constant

6.2 flN:TIONAl SlHfARY

LDM

dst,src,num

Load Multiple

This section presents a functional overview of the
instruction set. The instructions are separated
by function into eleven groups.
Within each
group, the salient features are described, such as
available addressing modes, effect on flags, and
possible exceptions. The eleven functional groups
are:

LDML

mask,src
dst ,mask

Load Multiple Longwords

LDR
LDRB
LDRL

dst,src

Load Relative

POP
POPL

dst,src

Pop

PUSH
PUSHL

dst,src

Push

This chapter describes the instruction set of the
l80,000 CPU. An overview of the instruction set,
separated into functional groups, is presented
first. Next, fl ags and condition codes are discussed.
Finally, a description is provided for
each instruction, including a summary of the operation, addressing modes, effect on flags, possible
exceptions, assembler language syntax, instruction
formats, and simple examples.
The bit patterns
used to encode various instruction fields are also
described.

•
•
•
•
•
•
•
•
•
•
•

Load and Exchange
Arithmetic
Logical
Program Control
Bit Manipulation
Bit Field
Rotate and Shi ft
Block Transfer and String Manipulation
Input/Output
CPU Control
Extended Instructions

6.2.1

load and Exchange Instructions

Instruction

Operand(s)

Na.e of Instruction

CLR
CLRB
CLRL

dst

Clear

CVT

dst,src

Convert

CVTU

dst,src

Convert Unsigned

The load and exchange instructions move data
between registers and memory.
Among these
instructions, onl y Convert and Convert Unsigned
affect the flags.
The Load instructions transfer a byte, word, or
long word of data from the source operand to the
destination operand.
A register can either be
loaded with an operand using any of the addressing
modes or a register or immediate value can be
loaded to a memory location.
The Load Relative
instructions load a register to or from a memory
location specified with the Relative addressing
mode. Special compact encodings are provided for
the following frequent operations:
(1) loading
any constant byte to a register; (2) loading a
small constant (0 to 15) word or long word to a
register (Load Constant); and (3) loading an
immediate value zero to a register or memory
location (Clear).

6-1

lBO,OOO Instruction Descriptions and Formats
The Exchange instructions swap the byte, word, or
longword contents of the source and destination
operands.
The contents of a register can be
swapped with the contents of another register or
memory location.

ADD
ADDB
ADDL

dst,src

Add

CHK
CHKB
CHKL

dst,src

Check

CP
CPB
CPL

dst,src

Compare

DAB

dst

Decimal Adjust

DEC
DECB

dst,src

Decrement

DECI
DECIB
DECL

dst,src

Decrement
Interlocked

The Load Multiple and Load Multiple Longwords
instructions provide efficient saving and restoring of registers. They are most useful for moving
simple data types that are more than four bytes
long and for changing the process context at
interrupts. The Load Multiple instruction allows
any contiguous group of 1 to 16 word registers to
be loaded to or from consecutive memory locations.
The Load Multiple Longwords instruction
allows up to 16 longword registers se lected by a
bit mask to be loaded to or from consecutive
memory locations.

DIV
DIVL

dst,src

Divide

DIVU
DIVUL

dst,src

Divide Unsigned

EXTS
EXTSB
EXTSL

dst

Extend Sign

INC
INCB
INCL

dst,src

Increment

Stack operations for words and long words are supported by the Push and Pop instructions.
Any
general-purpose register other than RO or RRO can
be used as a stack pointer. The stack pointer is
automatically decremented for Push and incremented
for Pop.
The source operand for Push and the
destination operand for Pop can be specified using
any of the addressing modes.

INCI
INCIL

dst,src

Increment
Interlocked

INDEX
INDEXL

dst,sub,src

Index

The Convert and Convert Unsigned instructions are
used to move the byte, word, or longword source
operand to a different-sized destination operand.
The data can be moved in either direction between
a register and another register or memory location.
When the destination is longer than the
source, Convert per forms sign extension and Convert Unsigned performs zero extension.
If the
destination is shorter than the source, the
instructions set the V flag when the lost
information is significant. The Integer Overflow
trap occurs when the IV bit in FCW is 1 and the
Convert instruction sets the V flag.

The Load Address instructions calculate the effective address of the source operand and load the
destination with that address. The destination is
a register and the source is specified with any of
the Extended Addressing Modes (EAM) (see Section
5.4).
These instructions are useful for
manipUlating segmented addresses and managing
complex data structures.

6.2.2 Arithaetic Instructions
Instruction

Operand(s)

N_ of Instruction

ADC
ADCB
ADCL

dst,src

Add with Carry

6-2

MUll
MULTL

' dst,src

Multiply

MULTU
MULTUL

dst,src

Multiply Unsigned

NEG
NEGB
NEGL

dst

Negate

SBC
SBCB
SBCL

dst,src

Subtract with Carry

SUB
SUBB
SUBL

dst,src

Subtract

TESTA
TESTAB
TESTAL

dst

Test Arithmetic

lBO,OOO Instruction Descriptions and Formats
The arithmetic group consists of instructions for
performing integer arithmetic. The basic instructions operate on unsigned binary integers or
signed twos complement binary integers.
Support
is provided for Binary Coded Decimal (BCD) arithmetic and multiple precision arithmetic.
The arithmetic instructions generally affect the
C, Z, S, and V flags.
The byte versions of
these instructions generally affect the D and H
flags as well.
The V flag indicates arithmetic
overflow.
The Integer Overflow Trap occurs when
the IV bit in the FCW is 1 and the V flag is set
after execution of an Add, Decrement, Decrement
Inter locked, Divide, Divide Unsigned, Increment,
Increment
Interlocked,
Negate,
or
Subtract
instruction.
Add,
Subtract, Multiply,
Multiply Unsigned,
Divide, and Divide Unsigned instructions operate
on a destination operand in a register and a
source operand specified by any addressing mode.
The result of the operation is stored in the
destination. Add and Subtract operate on bytes,
words, or longwords.
The Multiply instructions
operate on words or long words and compute a
double-precision product. The Divide instructions
operate
on
words
or
longwords,
using
a
double-precision dividend.
The Increment and Decrement instructions add or
subtract a small constant (1 to 16) to or from the
destination operand. The result is stored in the
destination. The operand may be a byte, word, or
longword specified in a register or memory
location.
Increment Interlocked and Decrement
Interlocked instructions are similar to Increment
and Decrement, but interlock protection is used to
fetch and store the destination operand in
memory.
Interlock protection is important for
implementing critical counters referred to by
multiple processors.

BCD operations are supported with the Decimal
Adjust instruction. The DAB instruction is used
following the binary addition or subtraction of
bytes to adjust the destination operand, specified
in a register, for correct BCD representation.
Multiple precision arithmetic is supported with
the Add with Carry, Subtract with Carry, and
Extend Sign instructions.
These instructions
operate on byte, word, or longword operands stored
only in registers. The Extend Sign instructions
compute a double-precision result.
The Check instructions are used to compare the
signed byte, word, or longword source operand
against lower and upper bounds. The source operand is specified in a register, and the bounds are
specified as immediate values or in consecutive
memory locations. If the source is out of bounds,
a Bounds Check trap occurs.
The Index instruction is used either to compute an
index into a one-dimensional array, or as one step
in computing the index into a multiple-dimensional
array. The signed subscript is compared against
lower and upper bounds. If the subscript is out
of bounds, an Index Error Trap occurs; otherwise,
the lower bound is subtracted from the subscript,
and the difference is added to the destination.
The sum is then multiplied by the scale factor,
and the product is stored back into the destination, which is the calculated array offset. The
source and destination operands are specified in
registers. The bounds and scale factor are specified as immediate values or in consecutive memory
locations. All operands are the same size, either
word or longword.

6.2.l logical Instructions
Instruction

Operand(s)

N_ of Instruction

The Negate instructions perform twos complement on
the destination operand in a register or memory
location.

AND
ANDB
ANDL

dst,src

And

The Compare instructions compare (subtract) the
source and destination operands and set the flags
to reflect the result. The contents of a register
can be compared with an operand specified using
any addressing mode, and the contents of a memory
location can be compared with an immediate value.
The Test Arithmetic instructions are special,
compact encodings for comparing a register or
memory location with zero.

COM
COMB
COML

dst

Complement

OR
ORB
ORL

dst,src

TEST
TESTB
TESTL

dst

Test

6-3

l80,000 Instruction Oescriptions and Formats

XOR
XORB
XORl

dst,src

Exclusive Or

The logical group consists of instructions for
performing logical operations on all bits of byte,
word, or longword operands; the instructions set
the land S flags according to the result. The
byte versions affect the P flag as well, setting
the P flag if the parity of the result is even.
The instructions And, Or, and Exclusive Or operate
on a destination operand in a register and a
source operand specified with any addressing
mode.
The appropriate logical operation is
performed on bits of the operands, and the result
is stored back into the destination.
The Complement instruction complements the bits of
the destination operand; the result is stored back
into the destination. Tha operand is a byte, word
or longword specified in a register or memory
location.
The Test instruction performs a logical Or of the
destination operand and zero, and sets the flags
according to the result. The operand is a byte,
word, or longword specified in a register or
memory location.

6.2.4 Progr_ Control Instructions
Instructioo

OperlDt(s)

BRKPT
CAll

N_ of Inatructioo

Breakpoint
dst

CAlR

Call

The Jump instruction loads the Program Counter
(PC) with the effective address of the destination
operand if the flags satisfy the specified condition. The destination is specified using any of
the memory addressing modes.
The Jump Relative
instr uction is a special, compact encoding used
when the destination is within -254 to 256 bytes
of the instruction location.
The Call instruction is used for calling procedures. The contents of the PC are pushed onto the
processor stack, and the effective address of the
destination operand is loaded into the PC. The
destination operand is specified using any of the
memory addressing modes.
The Call Relative
instruction is a special, compact encoding used
when the destination operand is within -4092 to
4098 bytes of the instruction location.
The Enter instruction is executed at the beginning
of a procedure to establish the procedure's
environment. Enter adjusts the Frame Pointer and
Stack Pointer registers to allocate a new
activation
record,
which
contains
saved
general-purpose registers, the Frame Pointer, the
exception handler address, and local data. The
instruction contains a bit mask indicating which
general-purpose registers to save. The mask and
the value of the Integer Overflow Enable bit in
FCW are also saved in the activation record. The
Call and Enter instructions provide the essential
functions for linking procedures in high-level
languages such as C and Pascal.

Call Relative

DJNl
DBJNl
DLJNl

r,dst

Decrement and Jump if
Not lero

ENTER

mask,siz

Enter

EXIT

Exit

cc,dst

Jump

cc,dst

Jump Relative

RET

Return

src

System Call

TRAP

cc,src

Conditional Trap

6-4

This group consists of instructions that control
program flow for jumps, loops, procedure calls,
and exceptions. The instructions generally do not
affect the flags, except when new Program Status
is loaded for traps.

Corresponding to Call and Enter instructions are
Return and Exit.
Exit releases the activation
record by adjusting the Stack Pointer and restoring the Frame Pointer. Exit also uses the mask
saved by Enter to restore the saved general-purpose registers and Integer Overflow Enable bit.
The Return instruction pops a value from the processor stack into the PC if the flags satisfy the
specified condition.
The Decrement and Jump I f Not lero instructions
are used to control loops, such as those implementing multiple-precision or decimal-string
arithmetic. The specified byte, word, or longword
register is decremented by one, and the result is
stored back into the register. If the result is
not zero, the PC is loaded with the effective
address of the destination. The destination may

lBO,OOO Instruction Descriptions and Formats
be specified using Relative Address addressing
mode, at a location no more than 252 bytes (DJNl,
OBJNZ)
or
250
bytes
(DlJNl)
before
the
instruction.
The Breakpoint, System Call, and Conditional Trap
instructions are all used to generate traps. The
Breakpoint instruction is generally placed by a
debugger at the first word of an instruction where
a breakpoint is desired. The System Call instruction is used by programs operating in normal mode
to request service from the operating system; the
low-order byte of the instruction can be used to
indicate the particular service desired. The Conditional Trap instruction generates a trap if the
flags satisfy the specified condition.
This
instruction can be used for software detection of
run-time errors or other exceptions; a 4-bit field
in the instruction word can be used to identi fy
the cause of the trap. When one of these traps
occurs, the CPU pushes the Program Status registers and instruction word onto the system stack,
and loads new values into the Program Status registers from the Program Status Area. See Chapter
7 for more details about trap processing.

instruction tests the bit of the destination
specified by the source operand, and sets the l
flag to indicate the result.
For "static"* bit
operations, the source operand is specified by an
immediate value and the destination operand may be
in a register or memory location. For "dynamic"
bit operations, the source and destination operands are in registers.
The Test Condition Code instruction sets the
least-significant bit of the byte, word, or longword destination register if the flags satisfy the
speci fied condition.
This instruction is useful
for evaluating Boolean expressions.
The Test and Set instruction tests whether the
destination is negative, then sets all bits in the
destination to 1. Interlock protection is used to
fetch and store the destination operand in memory.
Test and Set is used to access semaphores
protecting critical shared data structures in a
tightly-coupled multiprocessor system.

6.2.6 Bit field Instructions
N_of
Instruction

6.2.5 Bit Manipulation Instructions

Instruction Operand(s)

Instruction

Operand(s)

N_ of Instruction

EXTR
EXTRU

dst, src, pos, siz

Extract field

BIT
BITB
BITl

dst,src

Bit Test
INSRT

dst, src, pos, siz

Insert field

RES
RESB
RESl

dst,src

Reset Bit

SET
SETB
SETl

dst,src

Set Bit

TSET
TSETB
TSETl

dst

Test and Set

TCC
TCCB
TCCl

cc,dst

The instructions in this group are used to insert
and extract bit fields. A bit field is 1 to 32
contiguous bits that can cross byte boundaries.
One version of Extract (EXTR) is used to extract
and sign-extend a field into the destination longword register. Another version of Extract (EXTRU)
extracts and zero-extends the field.
Insert is
used to insert a fie ld from the source long word
register.
A bit field is specified by three operands as follows: (Figure 6-1).

Test Condition Code

The instructions in this group are used to manipulate an individual bit in a byte, word, or longword destination operand. Set Bit is used to set
a bit to 1; Reset Bit clears a bit to O. The bit
of the destination operand specified by the source
operand is set or cleared, and the result is
stored back into the destination.
The Bit Test

•

The origin of the bit string is the most-significant bit of a memory location or longword
register.
The origin is specified by the
source operand for Extract and the destination
operand for Insert.

* The term "static" is used because the bit number
is an immediate value that cannot change.
"Dynamic" means the bit number is specified in
a register and can change.
6-5

zao,ooo Instruction Descriptions and Formats

... I

I I I 1'1'

I ~I' I I~
I

IloRIGIN

... -----

INCREASING

ADDRESS

/-POSITION-/_SIZE-!

Figure 6-1.

•

The position of the field is the unsigned number of bits from the origin to the most-significant bit of the field. Position is messured
in the direction of decreasing significance
from the origin. The position of tha origin is
zero. The position is specified by an immediate
value (0 to 31) or in a word or longword register. In the latter case the position may be
any positive value.

•

The size of the field is the number of bits in
the field, between 0 and 31 inclusive, and
represents fields of 1 to 32 bits. The size is
specified by an immediate value or in a word or
longword register.

A bit field in memory must be contained entirely
within four consecutive bytes (i.e., the position
modulo a plus the size operand must be less than
or equal to 31). A bit field in s long word register must be entirely contsined within the register
(i.e., the position plus the size operand must be
less than or equal to 31).
Note that the direction of increasing bit number
for field position is opposite to Figure 2-1.

6.2.7

Rotate ... Shift Instructions

InstrllCtian

Opersnd(s)

N_ of InstrllCtion

Rl
RlB
Rll

dst,src

Rotate left

RlC
RlCB
RlCl

dst,src

Rotate left through
Carry

RlOB

dst,src

Rotate left Digit

RR
RRB
RRl

dst,src

Rotate Right

RRC
RRCB
RRCl

dst,src

6-6

Rotate Right through
Carry

Bit Field

RRDB

dst,src

Rotate Right Digit

SDA
SDAB
SDAl

dst,src

Shift Dynamic
Arithmetic

SOL
SDlB
SDll

dst,src

Shift Dynamic logical

SlA
SLAB
SlAl

dst,src

Shift left Arithmetic

Sll
Slla
Slll

dst,src

Shift left logical

SRA
SRAB
SRAl

dst,src

Shift Right Arithmetic

SRl
SRlB
SRll

dst,src

Shift Right logical

This group of instructions provides for rotating
and shifting of bytes, words, and longwords of
data located in general-purpose registers.
The
Rotate and Shift instructions sffect the C, Z, S,
and P/V flags.
The Rotate instructions rotate the contente of the
destinstion register left or right by an amount
specified by the source operand. The source is an
immediate value of one or two. Rotation is performed on the destinstion slone or, for mul tiple
precision arithmetic, on both the destination and
Csrry bit.
The digit rot st ion instructions
RlDB snd RRDB are useful for msnipulsting BCD
data.
The Shift instructions shift the contents of the
destinstion register left or right by an amount
specified by the source operand. The value of the
source operand can be any amount between zero and
the number of bits in the destinstion.
For
"static" shift operations, the source is specified

8225-011

IBO,OOO Instruction Descriptions and Formats
by an immediate value; for "dynamic" shift
operations the source is specified in a register.
Both logical and arithmetic shifts are supported.
An Integer Overflow Trap occurs when the IV bit of
FCW is 1 and the V flag is set after execution of
an arithmetic shift instruction.
6.2.8 Block Transfer and String Manipulation
Instrt.K:tions
Instruction

Operand(s)

N_ of Instrt.K:tion

CPD
CPDB
CPDL

dst,src,r,cc

Compare and Decrement

CPDR
CPDRB
CPDRL

dst,src,r,cc

Compare, Decrement
and Repeat

CPI
CPIB
CPIL

dst,src,r,cc

Compare and Increment

CPIR
CPIRB
CPIRL

dst,src,r,cc

Compare, Increment
and Repeat

CPSD
CPSDB
CPSDL

dst,src,r,cc

Compare String
Decrement

CPSDR
CPSDRB
CPSDRL

dst,src,r,cc

Compare String,
Decrement and Repeat

CPSI
CPSIB
CPSIL

dst,src,r,cc

Compare String and
Increment

CPSIR
CPSIRB
CPSIRL

dst,src,r,cc

Compare String,
Increment and Repeat

LDD
LDDB
LDDL

dst,src,r

Load and Decrement

LDDR
LDDRB
LDDRL

dst,src,r

Load, Decrement
Repeat

LDI
LDIB
LDIL

dst,src,r

Load and Increment

LDIR
LDIRB
LDIRL

dst,src,r

Load, Increment
Repeat

and

TRDB

dst,src,r

TRDRB

dst,src,r

TRIB

dst,src,r

TRIRB

dst,src,r

TRTDB

src1,src2,r

TRTDRB

src1,src2,r

TRTIB

src1,src2,r

TRTIRB

src1,src2,r

Translate and
Decrement
Translate, Decrement
and Repeat
Translate and
Increment
Translate, Increment
and Repeat
Translate, Test and
Decrement
Translate, Test,
Decrement, and Repeat
Translate, Test and
Increment
Translate, Test,
Increment and Repeat

This group of instructions provides a full complement of string comparison, string translation, and
block transfer operations. A block can be moved
in memory, a string can be searched for a given
value, and two strings can be compared.
These
instructions manipulate blocks or strings containing up to 65,536 bytes, words, or longwords. In
addition, a string containing up to 65,536 bytes
can be translated according to a table in memory,
or searched for a set of values specified by a
table in memory.
The block and string operands are speci fied using
Indirect Register addressing mode. When a string
is searched for a value, the value is located in a
register.
The length of the block or string
is also located in a register.
All the block transfer and string manipulation
operations can proceed through the data in either
direction.
Furthermore, the operations can be
repeated automatically while decrementing the
length register until it is zero, or they can
operate on a single element with the length register decremented by one and the pointer registers
properly adjusted. The second form can be used
with other instructions in a loop to implement
more complex string operations.
These instructions set the P/V flag to indicate
whether the length register was decremented to
zero. The string Search and Compare instructions
set the C, Z, and S flags to indicate the result
of the comparison.
The Translate and Test
instructions set the Z flag when one of the specified set of values is found. Otherwise, the flags
are unaffected.
The repetitive forms of these instructions are
interruptible after each iteration. Section 7.3.1
provides more information about interruptible
instructions.
6-7

l80,000 Instruction Descriptions and formats

6.2.9

Input/Output Instructions

IN
IN8
INL

dst,src

Input

IND
INDB
INDL

dst,src,r

Input and Decrement

INDR
INDRB
INDRL

dst,src,r

Input,Decrement and
Repeat

The other instructions in the group are used to
transfer a block (up to 65,536 b"ytes, words, or
longwords of data) between a peripheral port and
memory. The port address and memory address are
speci fied using I ndirect Register addressing
mode. The length of the block is located in a
register. These instructions are similar to the
block move instructions described in Section 6.2.7
except that the port address remains unchanged
while the memory address is adjusted.
The p/v
flag is set when the length register is decremented to zero.
The repetitive forms of these
instructions
are
interruptible
after
each
iteration.

INI
INIB
INIL

dst,src,r

Input and Increment

6.2.10 CPU Control Instructions

INIR
INIRB
INIRL

dst,src,r

OlDR
OlDRB
OlDRL

dst,src,r

OTIR
OTIRB
OTIRL

dst,src,r

OUT
OUTB
OUTL

dst,src

OUlD
OUlDB
OUlDL

dst,src,r

OUT!
OUTIB
OUTIL

dst,src,r

Instruction

Operand(s)

N_ of Instruction

Input,
Repeat

Increment

and

Output, Decrement and
Repeat

Output, Increment and
Repeat

Operand(s)

N_ of Instruction

COMFLG

flag

Complement flag

int

Disable Interrupt

int

Enable Interrupt

HALT

Halt

IRET

Interrupt Return
dst,src

Load Control Register

Output

LDCTL
LDCTLB
LDCTLL

dst,src

Load Normal Data

Output and Decrement

LDND
LDNDB
LDNDL

dst,src

Load Normal
Instruction

Output and Increment

LDNI
LDNIB
LDNIL
LDPND
LDPNI
LDPSD
LDPSI

dst,src

Load Physical Address

LDPS

src

Load Program Status

The instructions in this group transfer data
between a peripheral port and a CPU register or
memory. All of these instructions are privileged.
A single byte, word, or longword of data can be
transferred between a peripheral port and a CPU
register with the Input and Output instructions.
The port address is specified using the Direct
Address or Indirect Register addressing modes.
The single transfer instructions do not affect the
flags.

6-8

Instruction

NOP

No Operation

PC ACHE

Purge Cache

PTLB

Purge TLB

ZBO,OOO Instruction Descriptions and Formats
PTLBEND
PTLBENI
PTLBESD
PTLBESI

Purge TLB Entry

fLB.
Individual TLB entries can be invalidated
using the Purge TLB Entry instructions. All the
normal mode TLB entries can be invalidated using
the Purge TLB Normal instruction.

Purge fLB Normal

PfLBN

6.2.11

RESFLG

flag

Reset Flag

SETFLG

flag

Set Flag

The instructions in this group perform privileged
operations necessary for the operating system to
control the CPU; only the No Operation and flag
manipulation (COMFLG, LDCTLB, RESFLG, SETFLG)
instructions can be executed in normal mode. The
only instructions that affect the flags are the
flag manipulation instructions, the instructions
that load the FCW (I RET , LDCTL, LDPS), and the
Load Physical Address instructions.
The Disable Interrupt and Enable Interrupt
instructions control the Vectored Interrupt and
Non-Vectored Interrupt enable bits in FCW. The
enable bits can be separately cleared or set.
The Halt instruction halts the CPU.
The Interrupt Return instruction is used to return
from an interrupt or trap handler.
The Program
Status registers are loaded with values popped
from the system stack.

The ZBO,OOO architecture includes a powerful mechanism for extending the basic instruction set
through the use of coprocessors known as Extended
Processing Units (EPUs).
For example, floatingpoint arithmetic is supported by the ZB070 Arithmetic Processing Unit. When an extended instruction is executed and the EPA bit in the FCW is 1,
the CPU transfers the instruction to the EPU. The
CPU also controls the transfer of data between the
EPU and either memory or the CPU. If the EPA bit
is 0, an Extended Instruction trap occurs to allow
software emulation in systems that lack an EPU.
The CPU supports four types of extended instructions:
EPU internal operations that do not
require any data transfer; transfer of one to sixteen words of data between the EPU and consecutive
word or longword general-purpose registers;
transfer of one byte of data between the EPU and
the flag byte of the FCW; and the transfer of one
to sixteen bytes or words of data between the EPU
and memory. The flags are affected only when the
flag byte is loaded.

6.3

The Load Control instructions move data between a
control register and a general-purpose register.
The Load Program Status instruction loads the Program Status registers (PC, FCW) from memory. The
memory location is specified using the IR or EAM
addressing modes.
Load Normal Data and Load Normal Instruction are
used in system mode to move data between a register and a memory location in either of the normal
mode memory address spaces. The memory location
is specified using the IR or EAM addressing modes.
The Load Physical Address instructions load the
physical address of the source operand to the destination register. The source operand is specified using the IR or EAM addressing modes. These
instructions set the flags to indicate the aCCesS
protection of the logical address and whether the
address translation was valid.

Extended Instructions

fLAGS

AN)

CIJN)ITION COOES

The Program Status includes six processor flags as
follows:
Carry (C), Zero (Z), Sign (S),
Parity/Overflow (P/V), Decimal Adjust (D), and
These flags are affected or
Half Carry (H).
tested by most instructions. Arithmetic, logical,
and other instructions previously described modify
the flags to indicate the resu 1t of the
operation.
Among the instructions that test
whether or not the flags indicate a specified
condition are Jump, Return, and Test Condition
Code.
For example, a Test instruction may be
followed by a Jump:

TEST R1
JR Z, DONE

! sets Z flag if R1 = O!
!go to DONE if Z flag is set!

DONE:
The Purge Cache instruction invalidates the
cache contents. The Purge TLB instruction invalidates all address translation table entries in the

The program branches to DONE if the TEST
sets the Z flag, i.e., if R1 contains zero.

6-9

Z80,000 Instruction Descriptions and Formats
The Carry (C) flag is set to 1 following certain
operations when there ia a carry from or a borrow
into the high-order bit position of the result.
For example, adding the 8-bit numbers 225 and 64
causes a carry out of bit 7 and sets the Carry
flag:

Bit
7

225
64

1
0

289

0
0

0
0
Carry flag

o
0

1
0

The Carry flag is important for implementing
multiple-precision arithmetic (see the ADC, SBC
instructions). It is also involved in the Rotate
Left Through Carry (RLC) and Rotate Right Through
Carry (RRC) instructions. These instructions are
used to implement rotation or shifting of data.
The Zero (Z) flag is set to 1 when the result
of certain operations is zero.
This flag is
useful to determine when a counter reaches zero.
In addition, the block compare instructions use
the Z flag to indicate when the speci fied
comparison condition is satisfied.
The Sign (5) flag is set to 1 when the result of
certain operations
is
negative
(i.e.,
the
most-significant bit is 1).
The Overflow (V) flag is set to 1 when the result
of certain operations cannot be represented as a
twos camp lement number in the same precision as
the destination.
In the example below for 8-bit
numbers, 120 is added to 105.
The result, 225,
cannot be represented in 8 bits; it appears to be
-31. In such a case, the Overflow flag is set and
only the low-order bits of the result are stored
into the destination.

Bit
7
120 0
+ 105 0
225

6-10

II
1
0

2
0
0

0
0

0
0
0
0
Overflow flag set

The Parity (P) flag is set to 1 when the result of
logical operations on bytes has even parity (i.e.,
the number of 1 bits is even). The Overflow and
Parity flags share the same bit in the FCW, hence
the bit is named p/v.
The Decimal Adjust (D) and Half-Carry (H) flags
are used for BCD arithmetic. Following the binary
addition of two bytes, the D flag is set and the H
flag indicates the carry from bit 3.
Following
the binary subtraction of two bytes the 0 flag is
cleared and the H flag indicates the borrow from
bi t 3.
Decimal ar i thmetic on BCD bytes is performed by first adding or subtracting the operands
using binary arithmetic. Afterwards, the Decimal
Adjust instruction adjusts the result for correct
8CD representation.
The C, Z, 5, and p/V flags are also used to control the operation of conditional instructions
such as Jump. The operation of these instructions
depends on whether the four flags satisfy a
specified condition.
Conditional instructions
contain a 4-bit field, called the condition code,
that specifies one of sixteen flag conditions to
test.
Table 6-1 lists the flag condition tested
and the binary encodings for the condition codes.

6.11

NOTATION AND BINARY ENCODING

The rest of this chapter contains detailed
descriptions for each instruction, listed in
alphabetical order.
This section describes the
notational conventions used in the instruction
descriptions and the binary encoding for some
common instruction fields (e.g., register designation fields).
The bit patterns for other
instruction fieldS are shown explicitly in the
instruction format.
An instruction's descr iption begins with the
instruction mnemonic and instruction name in the
top part of the page. Privileged instructions are
also identified as such at the top of the page.
The assembler language syntax is then given in a
general form that covers all the variants of the
instruction and the order of source, destination
and other operands, along with a list of applicable addressing modes.
Example:
AN) dst, src
ANlB
ANll

dst: R
src: R, 1M, IR, EAM

ZBO,OOO Instruction Descriptions and Formata
Table 6-1.
Code

F
T
l

NZ
C
NC
PL
MI
NE
EQ
OV
NOV
PE
PO
GE
LT

GT
LE
UGE
ULT
UGT
ULE

Condition Codes

MaMing

Always false
Always true
Zero
Not zero
Carry
No carry
Plua
Minus
Not equal
Equal
Overflow
No overflow
Parity even
Parity odd
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned leas than
Unsignad greater than
Unsigned leaa than or equal

Flag Setting

Binary

Z
Z =0
C 1
C 0
5 0
5 =
Z =0
Z=
V=
V =0
P 1
P 0
(5 XOR V) = 0
(5 XOR V) = 1
(Z OR (5 XOR V»
(Z OR (5 XOR V»
C =0
C =1
«C = 0) AND (Z
(C OR Z) = 1

0000
1000
0110
1110
0111
1111
1101
0101
1110
0110
0100
1100
0100
1100
1001
0001
1010
0010
1111
0111
1011
0011

0»

Some condition codea correspond to identical flag settings:
Z-EQ, NZ-NE,
C-ULT, NC-UGE, PE-OV, and PO-NOV. If no condition is specified, the default
condition is T (always true).
The operation of the instruction is presented
next, followed by a detailed discussion of the
instruction, including the effect of the instruction on the processor flags. Exceptions that can
Some
occur for the instruction are listed next.
excaptions, such as the Address Translation trap,
can occur for any instruction. Only exceptions
specific to the instruction are listed.
Finally, s table is presented showing the assembler language syntax and instruction format for
each addressing mode and operand size. An aesembIer language example showing the use of the
instruction is also given.

6.4.1

AsaeIIbler Language Syntax

The syntax is shown for each operand size (byte,
word or longword).
The invariant part of the
ayntax is given in upper case and muat appear as
shown.
Lower case characters represent the
variable part of the syntax, for which suitable
values are substituted. The syntax is shown for
the most basic form of the instruction recognized
by the assembler. For example,
ADD Rd,ldata

repreaents a statement of the form ADO R3,135.
The assembler also accepts variations such as ADD
TOTAL, INEW-DELTA where TOTAL, NEW and DELTA have
been previously defined.
When the assembler syntax can be encoded in more
than one format (e.g., LOB RHO, 11), the assembler
generally uses the shortest encoding.
The following notation is used for regiaters:
Rbd,Rbs

a byte register (RHO,RH1, ••• ,RH7,RLO,
RL1, ... ,RL7)

Rd,Rs
RRd,RRs
RQd

a word register (RO,R1, ••• ,R15)
a longword register
(RRO,RR2, ••• ,RR30)
a quad word register
(RQO,RQ4, ••• ,RQ2B)

The ending "s" or "d" for the register notation
indicates either a source or destination operand,
respectively. Addrees registers must be word registers in compact mode and longword registers in
segnented or linear mode, as exp lained in footnotes to applicable instructions.
Several addressing modes are combined together in
a group called Extended Addressing Modes (EAM).
6-11

ZBO,OOO Instruction Descriptions and Formats
The instruction encoding for these addressing
modes requires one or more extension words following the opcode.
In compact mode, the EAMs are
Direct Address and Index (Base Address and Index
addressing modes are equivalent in compact mode.)
In segmented or linear mode, the EAMs are Direct
Address, Index, Base Address, Base Index, Relative
Address, and Relative Index.
Where the symbol
"eam" is found in the assembler syntax, any EAM
can be used.
Refer to Section 5.3 for the
assembler syntax for particular addressing modes.
Conditional instructions specify a condition code,
indicated by "cc" in the assembler syntax.
Table 6-1 lists the assembler mnemonics for condition codes.
The assembler recognizes comments beginning with
and continuing to the end of the line.

"II"

6.4.2

Code

Byte

Word

long

Quad

0000
0001
0010
0011

RHO
RH1
RH2
RH3

RO
R1
R2
R3

RRO
RR16
RR2
RR1B

RQO
RQ16
Unimplemented
Unimplemented

0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RH4
RH5
RH6
RH7
RLO

R4
R5
R6
R7
RB

RL1

RL2

R10
R11
R12

RR4
RR20
RR6
RR22
RRB
RR24
RR10
RR26
RR12
RR2B
RR14
RR30

RQ4
RQ20
Unimplemented
Unimplemented
RQB
RQ24
Unimplemented
Unimplemented
RQ12
RQ2B
Unimplemented
Unimplemented

RL3
RL4
RL5
RL6
RL7

R13
R14
R15

Instruction Foraat

The binary encoding of each instruction is given
as part of the instruction description.
Some
fields in the instruction contain symbols whose
values are described below.
The symbol "W" is used for a single bit that distinguishes between the byte and word versions of
the instruction.
The bit takes the value 0 for
byte versions and 1 for word versions.
Fields specifying registers are identified with
the same symbol (Rs, RRd, etc.) used in the
assembler language syntax. When the field cannot
take the value 0, a notation of the form "Rs;oiO" is
used.
Table 6-2 shows the binary encoding for
register fields.

6-12

Table 6-2.

For bit field instructions, the position and size
operands are specified by a 6-bit field.
The
operands can be immediate values or located in a
word or longword register.
The format of the
field is shown below.

r
r

5-bit immediate value
(0 to 31)
word register
long word register

lBO,OOO Instruction Descriptions and Formats
6.4.' Extended Addressing tbdea (EAM)
The format for instructions using an EAM includes
an opcode word containing a 4-bit field indicated
by "earn", followed by one, two, or three extension
words. An example is shown below.

The following sections describe the various encoding possibilities for EAM.
An EAM format
specifies the three components of an effective
address calculation:
base address, index value,
and displacement. Refer to Section 5.2 for more
information about effective address calculations.

Assembler Language Syntax

ADDL RRd,eam

Instruction Format

o 1 10 1

0 11 0

I earn I RRd

1, 2 or 3 extension words

6.4.'.1
COIIIpsct Mode.
In compact mode, the
[AM format is used for Direct Address or Index
addressing modes.
The opcode is followed by a
single extension word containing the base address

used in effective address calculation.
The eam
field specifies a word index register (eam;lO) or
no index register (eam=O).

Addressing Modes
earn

Mode
DA
X (word index)

6.4.'.2 ~ted or Linear Mode. In segmented
or linear mode, there are six [AM formats used for
Direct Address, Index, Base Address, Base Index,
Relative, and Relative Index addressing modes.
The six formats are distinguished by the encoding
of the most-significant bit and the four leastsignificant bits of the first extension word. The
most frequently used formats require only a single
extension word, but formats with two and three
extension words are provided to access the entire
Addressing Modes
earn

o
*0

Instruction Format

1°:' ! : :
.'

address space.

The formats are described below.

The first format uses a single extension word to
specify Base Address or Relative Address addressing modes.
The earn field specifies the base
address for the effective address calculation in a
longword register (eam;lO) or the Program Counter
(eam=D). The extension word encodes a displacement in the range -B192 to B191 inclusive.

Instruction Format

Mode
RA
SA

6-U

lBO,OOO Instruction Descriptions and Formats
The second format uses a single extension word to
specify Base Address,
Base Index, Relative
Address, or Relative Index addressing modes. The
earn field specifies the base address for the
effecti ve address calculation in a longword
register (eam;llO) or the Program Counter (eam=O).

The x field specifies an index register (x;llo) or
no index register.
When an index register is
specified, the L field determines whether a longword (L=1) or word (L=O) register is used.
The
extension word encodes a displacement in the range
-64 to 63 inclusive.

Addressing Modes
eam

x L
0

°° *0°° 011
*0
*0°
° °1
*0
*0
*0°
*0
*0 °

Instruction Format

Mode
RA
unimplemented
RX (word index)
RX (long index)
SA
unimplemented
SX (word index)
SX (long index)

The third format uses three extension words to
specify Base 'Address,
Base Index,
Relative
Address, or Relative Index addressing modes. The
encoding of the earn, x, and L fields is the same

01 1
11 displacement

0
0

x L

°°
*0°
°0 *0 °
*0
°°
*0
*0
*0°
*0
*0 °
1
1

Mode
RA
unimplemented
RX (word index)
RX (long index)
SA
unimplemented
SX (word index)
SX (long index)

01 1
10000000

Mode

DA
unimplemented
X (word index)
X (long index)

eam

111LI0

displacement (high)
displacement (low)

index register (x ;II 0) or no index register
(x = 0). When an index register is specified, the
L field determines whether a longword (L = 1) or
word (L = 0) register is used. Note that the eam
field must be alIOs in this format.

Addressing Modes

Instruction Format

0000

01\
10000000

address (high)
address (low)

6-14

1 0ILIO

Instruction Format

The fourth format uses three extension words to
specify Direct Address or Index addressing modes.
The base address used in the effective address
calculation is contained in the second and third
extension words.
This format can be used to
speci fy any address.
The x field specifies an

x L

as the previous format, but a 32-bit displacement
is contained in the second and third extension
words.

Addressing Modes
eam

eam

o1\L\0

Z80,000 Instruction Descriptions and formats
The fi fth format uses a single extension word to
speci fy Direct Address or Index sddressing modes.
The base sddress used in the effective address
calculation is encoded in the extension word. In
segmented mode, this format can be used to specify
addresses in a 64K-byte segment with the eight

lesst-significant bits of the segment number and
eight most-significant bits of the offset equel to
O. In linear mode, the CPU similarly decodes the
address in the extension word, but this format is
less useful. The eam field specifies a word index
register (eam ~ 0) or no index register (eam = 0).

Addressing Modes
earn

o
*0

Instruction Format

Mode
DA

01 1

X (word index)

earn 1
segment

offset

Encoded Address
offset
I

The sixth format uses two extension words to
specify Direct Address or Index addressing modes.
The bass addrsss used in the effective addrees
calculation is encoded in the extension words. In
segmented mode, this format can be used to specify
addresses in a 64K byte segment with the eight

least-significant bits of the segment number equal
to O. In linear mode, the CPU similarly decodes
the address in the extension words, but this
format is less often used.
The eam field
specifies a word index register (eam ~ 0) or no
index register (eam = 0).

Addressing Modes
earn

Instruction Format

Mode
DA

01 1

X (word index)

earn 1
segment

0000 0000

offset

Encoded Address
!

6._._ Unillpl-':ed InBtructioo £ncodings

Section 6.5 lists all of the instruction encodings
Any
for which the CPU's' operation is defined.
instruction encodings not listed are unimplemented
and must not be used. for most of the unimplemented instruction encodings, including all those
with first byte 3616 or 8f 16 and certsin Z8000
opcodes descr ibed in Appendix A, an st tempt to
execute the instruction causes an Unimplemented

, , ,

offset
I

Instruction trap to occur.
If a program
erroneously uses an unimplemented instruction thst
does not trap, the CPU's operation is not specified; however, the CPU never performs an operation
thst could not otherwise be performed by executing
a sequence of defined instructions. for example,
a progrsm executing in normal mode cannot gsin
access to privileged control registers or memory
locations by executing en instruction with an
unimplemented encoding.

6-15

6.5

Z80,OOO Instruction Descriptions and For.ats

ADC

Add With Carry

ADC dst, src
ADCB
ADCL
Operation:

dst -

dst

dst: R
src: R

src

The source operand, along with the setting of the C flag, is added to the destination
operand and the sum is stored in the destination. The contents of the source are not
affected. Twos complement addition is performed. In multiple precision arithmetic,
this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.

C: Set if there is a carry from the most-significant bit of the result; cleared

Flags:

otherwise

Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign
and the result is of the opposite sign; cleared otherwise

D: ADC, ADCL-unaffected; ADCB-cleared
H: ADC, ADCL-unaffected; ADCB-set if there is a carry from the most-significant
bit of the low-order four bits of the result; cleared otherwise
Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

ADC Rd, Rs
ADCB Rbd, Rbs
ADCL RRd, RRs

Instruction Format

01111010

1 011 1 0 1 0 1

Example:

6-16

00000010
RRs

RRd

Ouadword addition can be done with the following instruction sequence, assuming
ROO contains one operand and R04 contains the other operand:
/ladd low-order longwords
ADDL RR2,RR6
ADCL RRO,RR4
/ladd carry and high-order longwords
If RRO contains %00000000, RR2 contains % FFFFFFFF, RR4 contains %00004320
and RR6 contains %00000001, then executing the two instructions above leaves the
value %00004321 in RRO and %00000000 in RR2.

ADD
Add

ADD dst, src

dst: R
src: R, 1M, IR, EAM

AD DB
ADDL
Operation:

dst -

dst

src

The source operand is added to the destination operand and the sum is stored in
the destination. The contents of the source are not affected. Twos complement addition is performed.

c: Set if there is a carry from the most-significant bit of the result;

Flags:

cleared
otherwise
Z: Set if the result is zero; cleared otherwise
5: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign
and the result is of the opposite sign; cleared otherwise
D: ADD, ADDL-unaffected; ADDS-cleared
H: ADD, ADDL-unaffected; ADDS-set if there is a carry from the most-significant
bit of the low-order four bits of the result; cleared otherwise

Exceptions:

Integer Overflow trap

Source
Addressing
Mode

Assembler Language
Syntax
ADD Rd, Rs
ADDS Rbd, Rbs
ADDL RRd, RRs

1M:

Instruction Format

ADD Rd, Itdata

11 0

010110

RRs

RRd

o0 I 0 0 0 0 0 1 I0 0 0 0 I

data

ADDS Rbd, Itdata

o0 I 0 0 0 0 0 0

000 0

data

ADDL RRd, Itdata

I Rbd

data

00 0 1 0 1 1 0

I0 000 I RRd

data (high)
data (low)

IR:

ADD Rd, @RS1
ADDS Rbd, @RS1

loolooooolwi Rs""O I

ADDL RRd, @RS1

6-17

Source
Addressing
Mode

Assembler Language
Syntax

EAM:

Instruction Format

ADD Rd, eam
ADDS Rbd, eam

o 1 I0 0 0 0 0 I w I

earn

1, 2, or 3 extension words

o1 I 0 1 0 1 1 0

ADDL RRd, eam

I earn

RRd

1, 2, or 3 extension words

Example:

ADD

R2, %1254

lIadd the word at % 1254 to R2 in compact mode

Before instruction execution:
Memory
1252
1254
1256

Flags

CZS P/v D H
czspdh

After instruction execution:
Memory

1252~
1254

0 6 4 4

Flags

Ie 3

C Z S P/v D H
0010dh

1256

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·18

AND
And
AND dst, src
ANDB
ANDL
Operation:

dst -

dst: R
src: R, 1M, IR, EAM

dst AND src

A logical AND operation is performed between the corresponding bits of the source
and destination operands, and the result is stored in the destination. A 1 bit is stored
wherever the corresponding bits in the two operands are both 1s; otherwise a 0 bit
is stored. The contents of the source are not affected.

Flags:

C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
P: AND, ANDL- unaffected; ANDB - set if parity of the result is even; cleared
otherwise

D: Unaffected
H: Unaffected
Exceptions:
Source
Addressing
Mode

None

Assembler Language
Syntax

Instruction Format

AND Rd, Rs
ANDB Rbd, Rbs
ANDL RRd, RRs

01111010

00000010

RRd

ooj 000111 I0000 I

RRs

10 000111

1M:

AND Rd, #data

data

ANDB Rbd, #data

o0 I 0 0 0 1 1 0

0 00 0

ANDL RRd, #data

I Rbd

data

01111010
001000111

0000 0010

00001 RRd

data (high)
data (low)

6-19

Source
Addressing
Mode
IR:

Assembler Language
Syntax

Instruction Format

AND Rd. @Rs'
AN DB Rbd. @Rs'
ANDL RRd. @Rs'

EAM:

AND Rd. earn
ANDB Rbd. earn

01111010

00000010

001 000111

Rs*O

I RRd

o 1 10 0 0 1 11 W

eam

1,2, or 3 extension words
ANDL RRd. earn

0111101000000010

o 11 0 0 0 1 1 1

eam 1 RRd

1,2, or 3 extension words

Example:

ANDB RL3, II %CE
Before instruction execution:
RL3

Flags

11100111

CZSPNDH
czspdh

After instruction execution:
RL3

Flags

11000110

CZSPNDH
c011dh

Note t: Word register in compact mode. longword register in segmented or linear modes.

6·20

BIT
Bit Test
BIT dst, src
BITB
BITL

dst: R, IR, EAM
src: 1M
or
dst: R
src: R

Operation:

Z-

NOT dst

The specified bit within the destination operand is tested, and the Z flag is set to 1 if
the specified bit is 0; otherwise the Z flag is cleared to O. The contents of the
destination are not affected. The bit number (the source) can be specified either as
an immediate value (static), or as a word register that contains the value (dynamic).
In the dynamic case, the destination operand must be in a register, and the source
operand must be in a word register.
The bit number is a value from 0 to 7 for BITB, 0 to 15 for BIT, or 0 to 31 for BITL
with 0 indicating the least-significant bit. Only the lower three bits of the source
operand are used to specify the bit number for BITB, only the lower four bits are
used for BIT, and only the lower five bits are used for BITL.

Flags:

Unaffected
Z: Set if specified bit is zero; cleared otherwise
S: Unaffected
V: Unaffected
0: Unaffected
H: Unaffected

Exceptions:

None

Bit Test Static
Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

BIT Rd, #b
BITB Rbd, #b

BITL RRd, #b

01111010
101100111b

IR:

RRd

BIT @Rdl, #b
BITB @Rd', #b
BITL @Rdl, #b

01111010
001 1001

EAM:

0000 0010

BIT eam, #b
BITB eam, #b

0000 0010
Rd*O 1

01 11 001 11 Wi eam 1

1, 2,or 3 extension words

6-21

Bit Test Static (Continued)
Addressing
Mode

Assembler Language
Syntax
BITL earn, ffb

Instruction Format
01111010 00000010

o 1110 0 1 1 1beam

1, 2, or 3 extension words

Bit Test Dynamic
Addressing
Mode

Assembler Language
Syntax
BIT Rd, Rs
BITB Rbd, Rs

Instruction Format
001100111 w 0000
00001

BITL RRd, Rs

01111010

0000 0000

0000 0010

0011 001 1 1 0000
00001 RRd

Example:

0000 0000

If register RH2 contains % B2 (10110010), executing the instruction
BITB RH2, #0
leaves the Z flag set to 1.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-22

BRKPT
Breakpoint
BRKPT
Operation:

SP-SP - 6
@sp-ps
SP- SP - 2
@ SP instruction
PS - Breakpoint trap PS
This is a one word instruction that causes a Breakpoint trap. This instruction can be
used by a software debugger to replace the first word of the instruction where a
breakpoint is set.

Flags:

Flags loaded from Program Status Area

Exceptions:

Breakpoint trap

Addressing
Mode

Assembler Language
Syntax
BRKPT

Instruction Format

1011110 10 10000 000 1 1

6-23

CALL
Call

Operation:

CALL dst

dst: IR, EAM

Compact
tmp - EFFECTIVEJDDRESS (dst)
SP -SP - 2
@SP-PC

Segmented or Linear
tmp - EFFECTIVEJDDRESS (dst)
SP-SP - 4
@SP-PC

This instruction transfers control to a procedure or subroutine. The current contents
of the Program Counter (PC) are pushed onto the top of the processor stack. The
Stack Pointer (SP) pushed is R15 in compact mode, or RR14 in segmented or linear
mode. (The PC value used is the address of the first instruction word following the
CALL instruction.) The destination address, which pOints to the first instruction of the
called procedure, is then loaded into the PC. At the end of the called procedure, a
RET instruction can be used to return control to the instruction following CALL. RET
pops the top of the processor stack back into the PC.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

IR:

EAM:

Instruction Format

1001011111
CALL eam

o 11

011111

Rd*O 10 000 1

1eam 10 0 0 0

1,2, or 3 extension words

Example:

In compact mode, if the contents of the PC are % 1000 and the contents of the
Stack Pointer (R15) are % 3002, executing the instruction
CALL %2520
causes the SP to be decremented to % 3000, the value % 1004 (the address following the CALL instruction with Direct Address mode specified) to be loaded into the
word at location %3000, and the PC to be loaded with the value %2520. The PC
now points to the address of the first instruction in the procedure to be executed.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-24

CALR
Call Relative

Operation:

CALR dst

dst: RA

Compact
SP- SP - 2
@SP-PC
PC - PC - (2 X displacement)

Segmented or Linear
SP- SP - 4
@SP-PC
PC - PC - (2 X displacement)

The current contents of the Program Counter (PC) are pushed onto the top of the
processor stack. The Stack Pointer (SP) used is R15 in compact mode, or RR14 in
segmented or linear mode. (The PC value used is the address of the first instruction
word following the CALR instruction.) The destination address, which points to the
first instruction of the called procedure, is calculated and then loaded into the PC.
At the end of the called procedure, a RET instruction can be used to return control
of the instruction following CALR. RET pops the top of the processor stack back into
the PC.
The destination address is calculated by subtracting twice the displacement in the
instruction from the current value of the PC. The displacement is a 12-bit signed
value in the range -2048 to 2047. Thus, the destination address must be in the
range -4092 to 4098 bytes from the start of the CALR instruction. The assembler
automatically calculates the displacement by subtracting the address given by the
programmer from the PC value of the following instruction and dividing the result by
two.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

RA:

CALR address

Example:

Instruction Format

displacement

In linear mode, if the contents of the PC are %00001000 and the contents of the SP
(RR14) are % FFFF3002, executing the instruction
CALR PROC
causes the SP to be decremented to % FFFF3000, the value %00001002 (the address following the CALR instruction) to be loaded into the longword location
% FFFF3000, and the PC to be loaded with the address of the first instruction in procedure PROC.

6-25

CHK
Check
CHK dst, src
CHKB
CHKL

Operation:

dst: R
src: 1M, IR, EAM

tmp - EFFECTIVE._ADDRESS (src)
lower - @tmp
if dst < lower then Bounds Check trap
tmp - tmp + (1 if CHKB; 2 if CHK; 4 if CHKL)
upper - @tmp
if dst > upper then Bounds Check trap
The destination is compared against the bounds specified by the source operand. If
the destination is less than the lower bound or greater than the upper bound, a
Bounds Check trap occurs. The destination and bounds are compared as signed integers. The contents of the source and destination are not affected.
The source specifies the lower bound. The upper bound is located at the next consecutive byte, word, or longword.

Flags:

No flags affected.

Exceptions:

Bounds Check trap

Source
Addressing
Mode
1M:

Assembler Language
Syntax
CHK Rd. #Iower. #upper

Instruction Format

001001101

0000 1 01 0

00001

0000 0000

lower
upper

CHKB Rbd. #Iower. #upper

001 001 1 00 0000 1 01 0
00001 Rbd

CHKL RRd. #Iower. #upper

0000 0000

lower

upper

001001101

0000 1 01 1

00001 RRd

0000 0000

lower (high)
lower (low)
upper (high)
upper (low)

6-26

Source
Addressing
Mode

IR:

Assembler Language
Syntax

Instruction Format

CHK Rd, @RSI
CHKB Rbd, @RSI

001 0 01 10lw Rs*O 1 01 0
o 0 0 0 1 Rd

0000 0000

CHKL RRd, @RSI

EAM:

CHK Rd, earn
CHKB Rbd, earn

001 0011 01

Rs*O 1 01 1

o 0 0 01 RRd

0000 0000

o 1 0 0 1 1 olw
o 0 0 0 1 Rd

eam

1010

0000 0000

1,2, or 3 extension words

CHKL RRd, earn

o1 001101
o000

I RRd

eam

1011

0000 0000

1, 2, or 3 extension words

Example:

If RR2 contains 11, executing the instruction
CHKL RR2, #0, #10
causes a Bounds Check trap because the value in RR2 is greater than the upper
bound of 10.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-27

CLR
Clear
CLR dst
CLRB
CLRL

Operation:

dst: R, IR, EAM

dst-o
The destination is cleared to O.

Flags:

No flags affected.

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

CLR Rd
CLRB Rbd

CLRL RRd

IR:

CLR @Rd 1
CLRB @Rd 1
CLRL @Rd 1

EAM:

CLR eam
CLRB eam

11 01 0 1 1 1 00 1 RRd 10 1 0 0

100 1001 1 0 1wi Rd '" 0 11 000

10 0 0 1 1 1 0 0

Rd '" 0

I0 1 0 0

I
I
I

01100110lwl eam 11000
1, 2, or 3 extension words

CLRL eam

o1 10 1 1 1 0 0 1

eam 10 1 0 0

1, 2, or 3 extension words

Example:

In linear mode, if the longword at location %OOOOABBA contains 13, executing the
instruction
CLRL

%ABBA

leaves the value 0 in the longword at location %OOOOABBA.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-28

COM
Complement
COM dst
COMB
COML
Operation:

dst -

dst: R, IR, EAM

NOT dst

The contents of the destination are complemented (ones complement); all 1 bits are
changed to 0, and vice-versa.

Flags:

C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
P: COM, COML-unaffected; COMB-set if parity of the result is even;
cleared otherwise

D: Unaffected
H: Unaffected

Exceptions:
Destination
Addressing
Mode

None

Assembler Language
Syntax

Instruction Format

COM Rd
COMB Rbd
COML RRd

11 0 I0 1 1 1 0 0 I RRd

10010011 0IwIRd '" 0 100001

IR:

10 0 0 1 1 1 00

EAM:

I0 0 0 01

COM eam
COMB eam

o 110 0 1 1 0 wJ

Rd '" 0 100

earn

001

I0 0 0 0

1, 2, or 3 extension words
COML eam

o1 I0 1 1 1 0 0 I

earn

I0 0 0 0

1,2, or 3 extension words

Example:

If register R1 contains % 2552 (0010010101010010), executing the instruction
COM R1
leaves the value %DAAD (1101101010101101) in R1.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-29

COMFLG
Complement Flag
COMFLG flag
FLAGS < 7:4 > -

Flag: C, Z, S, P, V
FLAGS < 7:4> XOR instruction<7:4>

Operation:

Any combination of the C, Z, S, P or V flags can be complemented (each 1 bit is
changed to 0, and vice-versa). If the bit in the instruction corresponding to a flag is
1, the flag is complemented; if the bit is 0, the flag is unchanged. All other bits in
the Flags register are unaffected. Note that the P and V flags are represented by
the same bit. There can be one, two, three or four operands in the assembly
language statement, in any order.

Flags:

C: Complemented if specified; unaffected otherwise
Z: Complemented if specified; unaffected otherwise
S: Complemented if specified; unaffected otherwise
P/V: Complemented if specified; unaffected otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Assembler Language
Syntax
COMFLG flags

Example:

Instruction Format

10001101

If the C, Z, and S flags are all clear (= 0), and the P flag is set ( = 1), executing the
instruction
COMFLG P, S, Z, C
leaves the C, Z, and S flags set, and the P flag clear.

6-30

Ie Z S PIVI 0 1 0 1 I

CP
Compare
CP dst, src
CPB
CPL

Operation:

dst:
src:
or
dst:
src:

R
R, 1M, IR, EAM
IR, EAM
1M

dst - src
The source operand is compared to (subtracted from) the destination operand, and
the flags are set accordingly. The flags can then be used for arithmetic and logical
conditional jumps. Both operands are unaffected; the only action is the setting of
the flags. Subtraction is performed by adding the twos complement of the source
operand to the destination operand. There are two variants of this instruction: Compare Register compares the contents of a register against an operand specified by
any of the basic addressing modes; Compare Immediate performs a comparison
between an operand in memory and an immediate value.

Flags:

C: Cleared if there is carry from the most-significant bit of the result; set otherwise, indicating a borrow
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of opposite signs
and the sign of the result is the same as the sign of the source; cleared
otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Compare Register
Source
Addressing
Mode

Assembler Language
Syntax
CP Rd, Rs
CPB Rbd, Rbs
CPL RRd, RRs

1M:

Instruction Format

CP Rd, #data

11010100001 RRs

RRd

001 001011100001

data
CPB Rbd, #data

o0 I 0 0 1 0 1 0

0000

data

data
CPL RRd, #data

I Rbd

001 010000

10000 I RRd

data (high)
data (low)

6-31

Source
Addressing
Mode
IR:

Assembler Language
Syntax
CP Rd, @RSl
CPS Rbd, @RSl
CPL RRd, @RSl

EAM:

CP Rd, eam
CPS Rbd, eam

Instruction Format

0 0 10 0 1 0 11 w1 Rs

*0 1

1001010000lRs"ooi RRd

o 110 0 1 0

1wi

eam

1,2, or 3 extension words
CPL RRd, eam

011010000

I eam J

RRd

1, 2, or 3 extension words

Compare Immediate
Destination
Addressing
Mode

Assembler Language
Syntax

IR:

CP @Rdl, #data

Instruction Format

001001101

* oj 0 001

data
CPS @Rd1 , #data

001001100

* oj 0001

data
CPL @Rd1 , #data

data

001001101

Rd"oO

10 0 11

data (high)
data (low)

EAM:

CP eam, #data

eam

011001101

J 0001

1,2, or 3 extension words
data

CPS eam, #data

100

110

01 eam J 0 0 0

1 , 2, or 3 extension words

data

6-32

data

Destination
Addressing
Mode

Assembler Language
Syntax
CPL eam, #data

Instruction Format

o 11

110 11 earn 10 0 1 1

1, 2, or 3 extension words
data (high)
data (low)

Example:

In linear mode, if register RR4 contains %00000400, the byte at location
%00000400 contains 2, and the source operand is the immediate value 3, executing
the instruction
CPS @RR4,#3
leaves the C flag set, indicating a borrow, the S flag set, and the Z and V flags
cleared,
Note 1: Word register in compact mode, longword register in segmented or linear modes,

6-33

CPO

Compare and Decrement
CPO dst, src, r, cc
CPOB
CPOL

Operation:

dst: R
src: IR

dst - src
AUTOOECREMENT src (by 1 if CPOB; by 2 if CPO; by 4 if CPOL)

r- r - 1
This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register
are compared to (subtracted from) the destination operand, and the Z flag is set to 1
if the condition code specified by "cc" is satisfied by the comparison; otherwise the
Z flag is cleared to O. See Section 6.3 for a list of condition codes. Both operands
are unaffected.
The source register is then decremented by one if CPOB, by two if CPO, or by four if
CPOL, thus moving the pOinter to the previous element in the string. The word
register specified by "r" (used as a counter) is then decremented by one. The
source, destination and count registers must be distinct and non-overlapping
registers.

Flags:

C: Cleared if there is a carry from the most-significant bit of the result of the comparison; set otherwise, indicating a borrow
Z: Set if the condition code specified by cc is satisfied by the comparison; cleared
otherwise
S: Set if the result of the comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Source
Addressing
Mode
IR:

Assembler Language
Syntax

Instruction Format

CPD Rd, @Rs', r, cc
CPDB Rbd, @Rs', r, cc

1011101JW Rs * 0 1000

ooooJ
CPDL RRd, @Rsl, r, cc

10111001
00001

Example:

Rs*O

1000

RRd

In linear mode, if register RHO contains % FF, register RR4 contains %00004001,
the byte at location %4001 contains %00, and register R3 contains 5, executing the
instruction
CPOB

RHO, @RR4, R3, EQ

leaves the Z flag cleared since the result of the comparison was not "equal."
Register RR4 contains the value %00004000 and R3 contains 4. In compact mode,
a word register must be used instead of RR4.
Note': Word register in compact mode, longword register in segmented or linear modes.

6-34

CPDR
Compare, Decrement and Repeat
CPDR dst,
CPDRB
CPDRL
Operation:

src, r, cc

dst: R
src: IR

repeat
dst - src
AUTODECREMENT src (by 1 if CPDRB; by 2 if CPDR; by 4 if CPDRL)

r - 1

until cc is satisfied or r = 0
This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register
are compared to (subtracted from) the destination operand, and the Z flag is set to 1
if the condition code specified by "cc" is satisfied by the comparison; otherwise the
Z flag is cleared to O. See Section 6.3 for a list of condition codes. Both operands
are unaffected.
The source register is then decremented by one if CPDRB, by two if CPDR, or by
four if CPDRL, thus moving the pointer to the previous element in the string. The
word register specified by "r" (used as a counter) is then decremented by one. The
entire operation is repeated until either the condition is satisfied or the result of
decrementing r is zero. This instruction can search a string of length 1 to 65,536
data elements. The source, destination, and counter registers must be distinct and
non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation.

C: Cleared if there is a carry from the most-significant bit of the result of the last

Flags:

comparison; set otherwise, indicating a borrow

Z: Set if the condition code specified by cc is satisfied by the last comparison;
cleared otherwise

S: Set if the result of the last comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected
Exceptions:
Source
Addressing
Mode
IR:

None

Assembler Language
Syntax
CPDR Rd, @RS1, r, cc
CPDRB Rbd, @Rsl, r, cc

Instruction Format

10111011w Rs,;. 0

1100

00001

CPDRL RRd, @RS1, r, cc

10111001

00001

Rs,;.O 1100
RRd

6-35

Example:

In compact mode, if the string of words starting at location %2000 contains the
values 0, 2, 4, 6 and 8, register R2 contains % 2008, R3 contains 5, and R8 contains
5, executing the instruction
CPDR R3, @R2, R8, GT
leaves the Z flag set, indicating the condition was satisfied. Register R2 contains the
value %2002, R3 still contains 5, and R8 contains 2. In segmented or linear mode, a
longword register must be used instead of R2.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·36

CPI
Compare and Increment
CPI dst, src, r, cc
CPIB
CPIL
Operation:

dst: R
src: IR

dst - src
AUTOINCREMENT src (by 1 if CPIB; by 2 if CPI; by 4 if CPIL)

r - r-1
This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register
are compared to (subtracted from) the destination operand and the Z flag is set to 1
if the condition code specified by "cc" is satisfied by the comparison; otherwise the
Z flag is cleared to O. See Section 6.3 for a list of condition codes. Both operands
are unaffected.
The source register is then incremented by one if CPIB, by two if CPI or by four if
CPIL, thus moving the pOinter to the next element in the string. The word register
specified by "r" (used as a counter) is then decremented by one. The source,
destination, and counter registers must be distinct and non-overlapping registers.

Flags:

C: Cleared if there is a carry from the most-significant bit of the result of the comparison; set otherwise, indicating a borrow

Z: Set if the condition code specified by cc is satisfied by the comparison; cleared
otherwise

S: Set if the result of the comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise

D: Unaffected
H: Unaffected

Exceptions:

Source
Addressing
Mode
IR:

None

Assembler Language
Syntax

Instruction Format

CPI Rd, @Rsl, r, cc
CPIB Rbd, @Rsl, r, cc

10111011w R8;100 0000
0000

CPIL RRd, @Rsl, r, cc

1 01 1 1 001

Rs;loO 0000

00001

RRd

6-37

Example:

This instruction can be used in a "loop" of instructions that searches a string of
data for an element meeting the specified condition, but an intermediate operation
on each data element is required. In compact mode, executing the following sequence of instructions "scans while numeric," that is, a string is searched until
either an ASCII character outside the range "0" to "9" is found, or the end of the
string is reached. This involves a range check on each character (byte) in the string.
In segmented or linear mode, a longword register must be used instead of R1.
LD
LDA
LDB

R3, HSTRLEN
R1,STRSTART
RLO,H'9'

//initialize counter
//load start address
//largest numeric char

CPB
JR
CPIB
JR
JR

@R1,H'0'
ULT,NONNUMERIC
RLO, @R1, R3, ULE
NZ, NONNUMERIC
NOV, LOOP

IItest char

LOOP:

< '0'

//test char:5 '9'
IIrepeat until counter

DONE:

NONNUMERIC:

IIhandle non-numeric char

Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-38

CPIR
Compare, Increment and Repeat
CPIR dst, src, r, cc
CPIRB
CPIRL
Operation:

dst: R
src: IR

repeat
dst - src
AUTOINCREMENT src (by 1 if CPIRB; by 2 if CPIR; by 4 if CPIRL)
r-r - 1
0
until cc is satisfied or r

This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register
are compared to (subtracted from) the destination operand, and the Z flag is set to 1
if the condition code specified by "cc" is satisfied by the comparison; otherwise the
Z flag is cleared to O. See Section 6.3 for a list of condition codes. Both operands
are unaffected.
The source register is then incremented by one if CPIRB, by two if CPIR, or by four
if CPIRL, thus moving the pointer to the next element in the string. The word register
specified by "r" (used as a counter) is then decremented by one. The entire operation is repeated until either the condition is satisfied or the result of decrementing r
is zero. This instruction can search a string of length 1 to 65,536 data elements. The
source, destination, and counter registers must be distinct and non-overlapping
registers.
This instruction can be interrupted after each execution of the basic operation.

C: Cleared if there is a carry from the most-significant bit of the result of the last

Flags:

comparison; set otherwise, indicating a borrow

Z: Set if the condition code specified by cc is satisfied by the last comparison;
cleared otherwise

S: Set if the result of the last comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Exceptions:

Source
Addressing
Mode
IR:

None

Assembler Language
Syntax

Instruction Format

CPIR Rd, @RSI. r. cc
CPIRB Rbd,@Rsl, r, cc

10111011W R... O 0100
00001

CPIRL RRd, @Rsl, r, cc

1 0111 001
00001

Rs .. O 01 00
RRd

6-39

Example:

The following sequence of instructions (to be executed in compact mode) can be
used to search a string for an ASCII return character. The pOinter to the start of the
string is set, the string length is set, the character (byte) to be searched for is set,
and then the search is accomplished. Testing the Z flag determines whether the
character was found. In segmented or linear mode, a longword register must be
used instead of R1.

LOA

LD
LOB
CPIRB
JR

R1, STRSTART
R3,IISTRLEN
RLD, I %0
RLD, @R1, R3, EQ
Z, FOUND

"hex code for return is 0

Note 1: Word register in compact mode. longword register in segmented or linear modes.

6·40

CPSD
Compare String and Decrement
CPSD dst, src, r, cc
CPSDB
CPSDL

Operation:

dst: IR
src: IR

dst - src
AUTODECREMENT dst and src (by 1 if CPSDB; by 2 if CPSD; by 4 if CPSDL)
r- r - 1
This instruction is used to compare two strings of data in order to test the specified
condition. The contents of the location addressed by the source register are compared to (subtracted from) the contents of the location addressed by the destination
register. The Z flag is set to 1 if the condition code specified by "cc" is satisfied by
the comparison; otherwise the Z flag is cleared to O. See Section 6.3 for a list of
condition codes. Both operands are unaffected.
The source and destination registers are then decremented by one if CPSDB, by two
if CPSD or by four if CPSDL, thus moving the pointers to the previous elements in
the strings. The word register specified by "r" (used as a counter) is then
decremented by one. The source, destination and count register must be distinct,
non-overlapping registers.

Flags:

C: Cleared if there is a carry from the most-significant bit of the result of the comparison; set otherwise, indicating a borrow.
Z: Set if the condition code specified by cc is satisfied by the comparison; cleared
otherwise
S: Set if the result of the comparison is negative; cleared otherwise.
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

IR:

CPSD @Rd 1, @Rsl, r, cc
CPSDB @Rdl, @RS1, r, cc

Instruction Format

10111011W Rs*O 1010
00001

CPSDL @Rdl, @RS1, r, cc

Rd*O

1 01 1 1 001

Rs*O 1 01 0

00001

Rd*O

6-41

Example:

In linear mode, if register RR24 contains %00002000, the byte at location
%00002000 contains % FF, register RR26 contains %00003000, the byte at location %00003000 contains %00, and register R4 contains 1, executing the instruction
CPSDB @RR24, @RR26, R4, UGE
leaves the Z flag set to 1 since the result of the comparison was "unsigned greater
than or equal", and the V flag set to 1 to indicate that the counter R4 now contains
O. RR24 contains %00001 FFF, and RR26 contains %00002FFF. In compact mode,
word registers must be used instead of RR24 and RR26.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-42

CPSDR
Compare String, Decrement and Repeat
CPSDR dst, src,r, cc
CPSDRB
CPSDRL
Operation:

dst: IR
src: IR

repeat
dst - src
AUTODECREMENT dst and src (by 1 if CPSDRB; by 2 if CPSDR; by 4 if CPSDRL)
r- r - 1
until cc is satisfied or r = 0
This instruction is used to compare two strings of data until the specified condition
is true. The contents of the location addressed by the source register are compared
to (subtracted from) the contents of the location addressed by the destination
register. The Z flag is set to 1 if the condition code specified by "cc" is satisfied by
the comparison; otherwise the Z flag is cleared to O. See Section 6.3 for a list of
condition codes. Both operands are unaffected.
The source and destination registers are then decremented by one if CPSDRB, by
two if CPSDR, or by four if CPSDRL, thus moving the pointers to the previous
elements in the strings. The word register specified by "r" (used as a counter) is
then decremented by one. The entire operation is repeated until either the condition
is satisfied or the result of decrementing r is zero. This instruction can compare strings of length 1 to 65,536 data elements. The source, destination, and counter
registers must be distinct and non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation.

Flags:

C: Cleared if there is a carry from the most-significant bit of the result of the last
comparison; set otherwise, indicating a borrow.

Z: Set if the condition code specified by cc is satisfied by the last comparison;
cleared otherwise

5: Set if the result of the last comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise

D: Unaffected
H: Unaffected
Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

IR:

CPSDR @Rdl, @RS1, r,cc
CPSDRB @Rd 1, @RS1, r, cc

Instruction Format
10111011 w Rs*O

CPSDRL @Rd1, @RS1, r, cc

111 0

00001

Rd*O

10111001

Rs*O 1 1 1 0

0000

Rd*O

6-43
___

._.~_~~~.cc.

-,~-~-------,-,

Example:

In compact mode, if the words from location % 1000 to % 1006 contain the values 0,
2,4, and 6, the words from location %2000 to %2006 contain the values 0, 1, 1, 0,
register R13 contains % 1006, register R14 contains % 2006, and register RO contains 4, executing the instruction
CPSDR @R13, @R14, RO, EQ
leaves the Z flag set to 1 since the result of the comparison was "equal" (locations
% 1000 and %2000 both contain the value 0). The V flag is set to 1 indicating RO
was decremented to zero. R13 contains %OFFE, R14 contains % 1FFE, and RO contains O. In segmented or linear mode, longword registers must be used instead of
R13 and R14.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-44

-------

CPSI
Compare String and Increment
CPSI dst, src, r, cc
CPSIB
CPSIL

Operation:

dst: IR
src: IR

dst - src
AUTOINCREMENT dst and src (by 1 if CPSIB; by 2 if CPSI; by 4 if CPSIL)
r- r - 1
This instruction is used to compare two strings of data, in order to test the specified
condition. The contents of the location addressed by the source register are compared to (subtracted from) the contents of the location addressed by the destination
register. The Z flag is set to 1 if the condition code specified by "cc" is satisfied by
the comparison; otherwise the Z flag is cleared to o. See Section 6.3 for a list of
condition codes. Both operands are unaffected.
The source and destination registers are then incremented by one if CPSIB, by two
if CPSI or by four if CPSIL, thus moving the pointers to the next elements in the
strings. The word register specified by "r" (used as a counter) is then decremented
by one. The source, destination and count register must be distinct, non-overlapping
registers.

Flags:

C: Cleared if there is a carry from the most-significant bit of the result of the comparison; set otherwise, indicating a borrow
Z: Set if the condition code specified by cc is satisfied by the comparison;
cleared otherwise
S: Set if the result of the comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

Instruction Format

IR:

CPSI @Rdl,@Rsl,r,cc
CPSIS @Rd1,@Rsl,r, cc

10111011wRa;e.0 0010
00001

CPSIL @Rd1, @Rsl, r, cc

Rd;e.O

1 0 1 1 1 001

Ra;e.O

00 1 0

00001

Rd;e.O

6-45

Example:

This instruction can be used in a "loop" of instructions that compares two strings
until the specified condition is true, but where an intermediate operation on each
data element is required. The following sequence of instructions (executed in compact mode), attempts to match a given source string to the destination string which
is known to contain all upper-case characters. The match should succeed even if
the source string contains some lower-case characters. This involves a forced conversion of the source string to upper-case (only ASCII alphabetic letters are assumed) by resetting bit 5 of each character (byte) to 0 before comparison.
LDA
LDA
LD

R1,SRCSTART
R2,DSTSTART
R3,#STRLEN

IIload start addresses

RESS
CPSIS
JR
JR

@R1,#5
@R1,@R2, R3, NE
Z, NOTEOUAL
NOV, LOOP

DONE:

//force upper-case
IIcompare until not equal
lIexit loop if match fails
IIrepeat until counter = 0
IImatch succeeds

NOTEOUAL:

IImatch fails

lIinitialize counter

LOOP:

In segmented or linear mode, longword registers must be used instead of R1 and
R2.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-46

CPSIR

Compare String, Increment and Repeat
CPSIR dst,src,r,cc
CPSIRB
CPSIRL

Operation:

dst: IR
src: IR

repeat
dst - src
AUTOINCREMENT dst and src (by 1 if CPSIRB, by 2 if CPSIR; by 4 if CPSIRL)
r- r - 1
until cc is satisfied or r
0

This instruction is used to compare two strings of data until the specified condition
is true. The contents of the location addressed by the source register are compared
to (subtracted from) the contents of the location addressed by the destination
register. The Z flag is set to 1 if the condition code specified by "cc" is satisfied by
the comparison; otherwise the Z flag is cleared to O. See Section 6.3 for a list of
condition codes. Both operands are unaffected.
The source and destination registers are then incremented by one if CPSIRB, by two
if CPSIR, or by four if CPSIRL, thus moving the pointers to the next elements in the
strings. The word register specified by "r" (used as a counter) is then decremented
by one. The entire operation is repeated until either the condition is satisfied or the
result of decrementing r is zero. This instruction can compare strings of length 1 to
65,536 data elements. The source, destination, and counter registers must be
distinct and non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation.

Flags:

C: Cleared if there is a carry from the most-significant bit of the result of the last
comparison; set otherwise, indicating a borrow.
Z: Set if the condition code specified by cc is satisfied by the last comparison;
cleared otherwise.
.
S: Set if the result of the last comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

Instruction Format

IR:

CPSIR @Rd 1 ,@Rsl,r,cc
CPSIRB @Rdl,@Rsl,r,cc

10111011W Rs*O 0110
00001

CPSIRL @Rd1 ,@Rsl,r,cc

Rd*O

1 01 1 1 001

Rs*O 01 1 0

0000\

Rd*O

6-47

Example:

The CPSIR instruction can be used to compare text strings for lexicographic order.
(For most common character encodings - for example, ASCII and EBCDIC - lexicographic order is the same as alphabetic order for alphabetic text strings that do
not contain blanks.)
Let S1 and S2 be text strings of lengths L1 and L2. According to lexicographic
ordering, S1 is said to be "less than" or "before" S2 if either of the following is
true:
• At the first character position at which S1
and S2 contain different characters, the
character code for the S1 character is
less than the character code for the S2
character.
• S1 is shorter than S2 and is equal, character for character, to an initial substring
of S2.
For example, using the ASCII character code, the following strings are ascending
lexicographic order:

A
AA
ABC
ABCD
ABD
Assume that the address of S1 is in RR2, the address of S2 is in RR4, the lengths L1
and L2 of S1 and S2 are in RO and R1, and the shorter of L1 and L2 is in R6. The
following sequence of instructions (executed in segmented or linear mode) will
determine whether S1 is less than S2 in lexicographic order:
CPSIRB @RR2, @RR4, R6, NE
IIscan to first unequal character
lithe following flags settings are possible:
Z = 0, V = 1: Strings are equal through L1
character (Z = 0, V = 0 cannot occur).
Z = 1, V = 0 or 1: A character position was
found at which the strings are unequal.
C = 1 (S = 0 or 1): The character in the RR2
string was less (viewed as numbers from 0 to
255, not as numbers from -128 to + 127).
C = 0 (S = 0 or 1): The character in the RR2
string was not less
JR Z,CHALCOMPARE
/lif Z = 1, compare the characters
lIotherwise, compare string lengths
CP RO,R1
JR LT, S1_IS_LESS
JR S1_NOT_LESS
CHALCOMPARE:
IIULT is another name for C= 1
JR ULT, S1_IS_LESS
S1_NOT LESS:

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-48

CVT
Convert
CVTBW dst, src
CVTBL
CVTWB
CVTWL
CVTLB
CVTLW

Operation:

dst -

dst:
src:
or
dst:
src:

R
R, IR, EAM
IR, EAM
R

CONVERSION (src)

The contents of the source are converted to the size of the destination and then
stored into the destination. The contents of the source are not affected.
The source and destination are treated as signed integers. The size of the destination operand is indicated by the fourth letter of the opcode mnemonic (B, W, or L);
the size of the source operand is indicated by the last letter. For CVTWB, CVTLB,
and CVTLW the source is sign-extended to the size of the destination before storing.
For CVTBW, CVTBL, and CVTWL the source is truncated to the size of the destination, keeping the less-significant bits, before storing. If the source cannot be exactly
represented in the destination because of truncation, then the V flag is set to 1;
otherwise the V flag is cleared to O.

Flags:

C:
Z:
S:
V:

Exceptions:

Integer Overflow trap

Cleared
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise.
CVTBW, CVTBL-set if the source is not in the range -128 to 127; cleared
otherwise; CVTWL-set if the source is not in the range - 32768 to 32767;
cleared otherwise; CVTLB, CVTLW-cleared
0: Unaffected
H: Unaffected

Convert Register
Source
Addressing
Mode

Assembler Language
Syntax
CVTBW Rbd, Rs

Instruction Format

0111100000000001
1 0 11 0 0 0 0 1

CVTBL Rbd. RRs

RRs 1 Rbd

0111100000100001
1 011 0 0 0 0 0

CVTWL Rd. RRs

1 Rbd

0111100000000001
10 010100

CVTWB Rd, Rbs

Rbs

0111100000100001

10 010100

RRs

6-49

Source
Addressing
Mode

Assembler Language
Syntax
CVTLB RRd. Rbs

CVTLW RRd. Rs

Instruction Format

01111000

00110001

101100000

Rbs 1 RRd

01111000

00110001

101100001

IR:

CVTBW Rbd. @RS1

CVTWL Rd. @RS1

CVTLB RRd. @RS1

CVTLW RRd. @RS1

EAM:

CVTBW Rbd. eam

Rs*O

I Rbd

01111000 00000011
001010100

CVTWB Rd. @RS1

1 RRd

01111000 00000011
001100001

CVTBL Rbd. @RS1

01111000

RHO

Rbd

00100011
Rd

00J100000

RHO 1

01111000

00100011

0010101 00

RHO 1

01111000 00110011
001100000

Rs*O 1 RRd

01111000

00110011

001100001

RHO 1 RRd

01111000

00000011

011100001

earn 1 Rbd

1, 2, or 3 extension words
CVTBL Rbd. eam

01111000

00000011

011010100

earn 1 Rbd

1, 2, or 3 extension words
CVTWB Rd. eam

01111000 00100011
0111 00000

earn 1

1, 2, or 3 extension words

6-50

Source
Addressing
Mode

Assembler Language
Syntax
CVTWL Rd, eam

Instruction Format

01111000
01J010100

00100011
eam 1

1, 2, or 3 extension words

CVTLB RRd, eam

01111000
011100000

00110011
eam 1

RRd

1,2, or 3 extension words

CVTLW RRd, eam

01111000
01]100001

00110011
eam 1

RRd

1, 2, or 3 extension words

Convert Memory
Destination
Addressing
Mode
IR:

Assembler Language
Syntax
CVTBW @Rdl, Rs

CVTBL @Rd1 , RRs

Instruction Format

01111000

00100101

001101110

Rd*O 1 Rs

01111000
0011 01 1 1 0

CVTWB @Rd 1 , Rbs

CVTWL @Rd 1, RRs

CVTLW @Rdl, Rs

Rd*O

RRs

01111000

0000 0101

001101111

Rd*O 1 Rbs

01111000

00110101

001101111
CVTLB @Rdl, Rbs

00110101

Rd*O 1

RRs

01111000

00000101

001011101

Rd*01 Rbs

01111000

0010 0101

001011101

Rd*Oj

6-51

Destination
Addressing
Mode

Assembler Language
Syntax

EAM:

CVTBW earn, Rs

Instruction Format

0111100000100101

o 1 11 0 1 1 1 il

earn 1

1, 2, or 3 extension words

CVTBL earn, RRs

0111100000110101
0111 01 1 1 0

earn 1 RRs

1, 2, or 3 extension words

CVTWB earn, Rbs

01111000 00000101

o 1 11 0 1 1 1 1

earn 1 Rbs

1, 2, or 3 extension words
CVTWL earn, RRs

01111000 00110101

o 1 11 0 1 1 1 1

earn 1 RRs

1,2, or 3 extension words
CVTLB earn, Rbs

01111000

0000 0101

o 1 10 1 1 1 0 1

earn 1 Rbs

1, 2, or 3 extension words
CVTLW earn, Rs

0111100000100101

o 1 10 1 1 1 0 1

earn 1 Rs

1, 2, or 3 extension words

Example:

If byte register RHO contains the value -100, executing the instruction
CVTLB RR4, RHO
loads - 100 into longword register RR4, The S flag is set and the C, Z, and V flags
are cleared.
Note 1: Word register In compact mode, longword register in segmented or linear modes.

6·52

CVTU
Convert Unsigned
CVTUBW dst, src
CVTUBL
CVTUWB
CVTUWL
CVTULB
CVTULW

Operation:

dst -

dst:
src:
or
dst:
src:

R
R, IR, EAM
IR, EAM
R

UNSIGNED_CONVERSION (src)

The contents of the source are converted to the size of the destination and then
stored into the destination. The contents of the source are not affected.
The source and destination are treated as unsigned integers. The size of the
destination operand is indicated by the fifth letter of the opcode (B, W, or L); the
size of the source operand is indicated by the last letter. For CVTUWB, CVTULB,
and CVTULW the source is zero-extended to the size of the destination before storing. For CVTUBW, CVTUBL, and CVTUWL the source is truncated to the size of the
destination, keeping the less significant bits, before storing. If the source cannot be
exactly represented in the destination because of truncation then the V flag is set to
1; otherwise the V flag is cleared to O.

Flags:

C: Cleared
Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise.
V: CVTUBW, CVTUBL-set if the source is greater than 255; cleared otherwise
CVTUWL-set if the source is greater than 65,535; cleared otherwise
CVTULB,CVTULW-cleared
D: Unaffected
H: Unaffected

Exceptions:

None

Convert Register Unsigned
Source
Addressing
Mode

Assembler Language
Syntax
CVTUBW RbeI, Rs

Instruction Format

01111000 0000 0000
1 0 11 0 0 0 0 1

CVTUBL RbeI, RRs

CVTUWB Rd, Rbs

1 Rbd

o1 1 1 1 0 0 0

0 0 0 00 0 0 0

1 01 0 1 01 00

RRs 1 Rbd

0111100000100000
1 0 11 0 0 0 0 0

CVTUWL Rd, RRs

Rbs

0111100000100000
1 01 0 1 0 1 00

RRs 1 Rd

6-53

Source
Addressing
Mode

Assembler Language
Syntax
CVTU LB RRd, Rbs

Instruction Format

01111000
1 011 0 0 0 0 0

CvrULW RRd, Rs

IR:

CvrUBW Rbd, @RSl

0011

0000

I Rbs T RRd

01111000

0011

1011000011

0000

1 RRd

011110000000 0010

o 0 11 0 0 0 0 1 1 Rs;!o 0 1
CVTUBL Rbd, @RSl

01111000

Rbd

0000 0010

0010101001 Rs;!o01 Rbd

CVTUWB Rd, @RSl

01111000

0010 0010
Rd

00 1 000001 Rs;!oO 1

CvrUWL Rd, @RSl

01111000 0010 0010
Rd

0010101001 Rs;!oO 1

CvrULB RRd, @RSl

01111000

0011 0010

0011000001 Rs;!oO 1 RRd

CvrULW RRd, @RSl

EAM:

CVTUBW Rbd, earn

01111000

0011

0011 00001

I Rs;!oO I

01111000

0010
RRd

0000 0010

O. 1 11 0 0 0 0 1 1 earn 1 Rbd
1,2, or 3 extension words

CVTU BL Rbd, earn

01111000

0000 0010

o 1 I0 1 0 1 0 0 I

earn 1 Rbd

1,2, or 3 extension words

CVTUWB Rd, earn

01111000

0010 0010

o 1 11 0 0 0 0 0 1

eam 1 Rd

1, 2, or 3 extension words

,
6·54

Source
Addressing
Mode

Assembler Language
Syntax
CVTUWL Rd, earn

Instruction Format

01111000
011010100

00100010
Rd

earn j

1, 2, or 3 extension words
CVTU LB RRd, earn

01111000
0111 00000

001 1 001 0
earn

1 RRd

1, 2, or 3 extension words
CVTULW RRd, earn

01111000
01\100001

001 1 0010
earn

RRd

1,2, or 3 extension words

Convert Memory Unsigned
Destination
Addressing
Mode

Assembler Language
Syntax

IR:

CVTU BW @Ad1, Rs

Instruction Format

01111000 0010 0100
001101110

CVTU BL @Rd1, RRs

01111000 00110100
001101110

CVTUWB @Rd1 , Rbs

CVTUWL @Rd1 , RRs

CVTU LB @Rd1 , Rbs

Rd*O 1 RRs

01111000 0000 0100
0011 01 1 1 1

Rd*Oj Rbs

01111000

00110100

0011 01 1 1 1

Rd*Oj RRs

01111000

ooj 0 1 1 1 0 1
CVTULW @Rdl, Rs

Rd*O 1 Rs

01111000
001011101

00000100
Rd*O

1 Rbs

00101100
Rd*O 1 Rs

6-55

Destination
Addressing
Mode
EAM:

Assembler Language
Syntax
CVTU BW eam, Rs

Instruction Format

0111100000100100

o 1 11 0 1 1 1 0

eam

1,2, or 3 !,xtension words
CVTUBL eam, RRs

0111100000110100

o 111

01110

eam 1 RRs

1, 2, or 3 extension words
CVTUWB eam, Rbs

01 1 1 1 000

0000 0 1 00

o 111 0 1 1 1 1

eam 1 Rbs

1, 2, or 3 extension words
CVTUWL eam, RRs

0111100000110100

o 1 11 0 1 1 1 1

eam

I RRs

1,2, or 3 extension words

CVTU LB eam, Rbs

0111100000000100

o 1J

011101

eam 1 Rbs

1, 2, or 3 extension words
CVTU LW eam, Rs

0111100000100100

o1 1 0 1 1 1 0 1

earn 1

1,2, or 3 extension words

Example:

If word register R1 contains the value %DF12, executing the instruction
CVTUBW RLD, R1
loads % 12 into byte register RLD. The V flag is set and the C, Z, and S flags are
cleared.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6·56

DAB
Decimal Adjust
DAB dst
Operation:

dst -

dst: R

DECIMALADJUST (dst)

The destination byte is adjusted to form two 4-bit BCD digits following a binary addition or subtraction operation on two BCD encoded bytes. Following addition (ADDB,
ADCB) or subtraction (SUBB, SBCB), the table below indicates the operation
performed:

Instruction

ADDB
ADCB

SUBB
SBCB

Carry
Before
DAB

Bits 4-7
Value
(Hex)

H Flag
Before
DAB

Bits 0-3
Value
(Hex)

Number
Added
To Byte

Carry
After
DAB

0
0
0
0
0
0
1
1
1

0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3

0
0
1
0
0
1
0
0
1

0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3

00
06
06
60
66
66
60
66
66

0
0
0
1
1
1
1
1
1

0
0
1
1

0-9
0-8
7-F
6-F

0
1
0
1

0-9
6-F
0-9
6-F

00
FA
AO
9A

0
0
1
1

The operation is undefined if the destination byte was not the result of a binary addition or subtraction of BCD digits.

Flags:

C: Set or cleared according to the table above
Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
V: Unaffected
D: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

DAB Rbd

Instruction Format

11 011 1 0 0 0 0

1 Rbd

6-57

Example:

If addition is performed using the BCD values 15 and 27, the result should be 42.
The sum is incorrect, however, when the binary representations are added in the
destination location using standard binary arithmetic. As shown below, adding the
two numbers using binary arithmetic gives a result of %3C, leaving the C and H
flags clear.

0001
0010
0011

0101
0111
1100

% 3C

Executing the DAB instruction adjusts this result so that the correct BCD representation is obtained.

6-58

00111100
0000 0110
0100 0010

DEC
Decrement
DEC dst, src
DECB
DECL
Operation:

dst -

dst - src (src

dst: R, IR, EAM
src: 1M

= 1 to 16)

The source operand (a value from 1 to 16) is subtracted from the destination
operand and the result is stored in the destination. Subtraction is performed by adding the twos complement of the source operand to the destination operand. If the
source operand is omitted from the assembler language statement, the default value
is 1.
The value of the source field in the instruction is one less than the actual value of
the source operand. Thus, the coding in the instruction for the source ranges from 0
to 15, which corresponds to the source values 1 to 16.

Flags:

C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite sign
and the sign of the result is the same as the sign of the source; cleared
otherwise.
D: Unaffected
H: Unaffected

Exceptions:

Integer Overflow trap

Destination
Addressing
Mode

Assembler Language
Syntax
DEC Rd. In
DECB Rbd, In
DECL RRd, In

IR:

DEC @Rdl, In
DECB @Rdl, In
DECL @Rd 1 , In

EAM:

DEC eam, In
DECB eam, In

Instruction Format

1101101011 w

1 n - 11

01111010

0000 0010

101101011

RRd 1 n - 1

1001101011 w Rd*O 1 n -11

01111010

0000 0010

001101011

Rd*O 1 n - 1

01l10101JW

eam 1 n - 1

1,2, or 3 extension words
DECL eam, In

01111010

0000 0010

011101011

eam 1 n - 1

1,2, or 3 extension words

6·59

Example:

If register RR10 contains %0000002A, executing the instruction
DECL RR10
leaves the value %00000029 in RR1O.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-60

DECI
Decrement Interlocked
DECI dst, src
DECIB

Operation:

dst -

dst - src (src

dst: IR, EAM
src: 1M

= 1 to 16)

The source operand (a value from 1 to 16) is subtracted from the destination
operand and the result is stored in the destination. Subtraction is performed by
adding the twos complement of the source operand to the destination operand. If
the source operand is omitted from the assembly language statement, the default
value is 1.
The value of the source field in the instruction is one less than the actual value of
the source operand. Thus, the coding in the instruction for the source ranges from 0
to 15, which corresponds to the source values 1 to 16.
This is an interlocked instruction. No other interlocked accesses are permitted to
the destination memory location between fetching and storing the result.

Flags:

Exceptions:

Integer Overflow trap

Destination
Addressing
Mode

IR:

EAM:

Assembler Language
Syntax
DECI @Rdl, In
DECIB @Rd 1 , In

DECI eam, In
DECIB eam, In

Instruction Format

01111010

0000 0100

001101011w

Rd'*0l n-1

01111010

00000100

a 111 0 1 0 11 W

e8m

1 n- 1

1,2, or 3 extension 'words

Example:

This instruction can be used to allocate or release copies of a system resource in a
multiprocessor environment. For example, several processes running on different
processors can share use of a common page in memory. It is necessary to keep a
reference counter for the number of active processes using the shared page. When
one of these processes terminates, the reference counter is decremented. The DECI
instruction should be used so that one processor completes the fetch and store of
the counter in memory before any other processor accesses the counter.
DECI REFERENCLCOUNTER, #1
IIdecrement reference counter
for shared page
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-61

Privileged Instruction

Disable Interrupt
Ollnt

Operation:

Int: VI, NVI

If instruction = 0 then NVI- 0
If instruction < 1 > = 0 then VI - 0
Any combination of the Vectored Interrupt (VI) or Non-Vectored Interrupt (NVI) control bits in the Flag and Control Word (FCW) are cleared to 0 if the corresponding bit
in the instruction is 0, thus disabling the appropriate type of interrupt. If the corresponding bit in the instruction is 1, the control bit is not affected. All other bits in
the FCW are not affected. There may be zero, one or two operands in the assembly
language statement, in either order, specifying no source operand is equivalent to
specifying both VI and NVI.

Flags:

No flags affected.

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax
DI in!

Example:

Instruction Format

I 01111100

10000001YI~1

If the NVI and VI control bits are set (1) in the FCW, executing the instruction
DI VI
leaves the NVI control bit in the FCW set to 1 and the VI control bit in the FCW
cleared to O.

6-62

DIV
Divide
DIV dst, src
DIVL
Operation:

dst: R
src: R, 1M, IR, EAM

Word: (dst is longword register, src is' word):
dst < 31 :0> is divided by src < 15:0 >
(dst<31:0> = quotient x src<15:0> + remainder)
dst < 15:0> - quotient
dst<31:16> - remainder
Longword: (dst is quadword register, src is longword ):
dst < 63:0 > is divided by src < 31 :0 >
(dst<63:0> = quotient x src<31:0> + remainder)
dst < 31 :0> - quotient
dst < 63:32 > - remainder
The destination operand (dividend) is divided by the source operand (divisor). The
quotient is stored in the low-order half of the destination and the remainder is stored
in the high-order half of the destination. The contents of the source are not affected.
Both operands are treated as signed, twos complement integers. Division is performed so that the remainder is of the same sign as the dividend except when the
remainder is 0 and the quotient sign is the exclusive OR of the signs of the dividend
and divisor except when the quotient is O. For DIV, the destination is a longword
register and the source is a word value; for DIVL, the destination is a quadword
register and the source is a longword value.
For proper instruction execution the "dst field" in the DIVL instruction encoding
must specify a valid code for a quadword register.
There are four possible outcomes of the signed divide instruction.
CASE 1. If the divisor is 0, then the destination register is unmodified, the V and Z
flags are set to 1, and the C and S flags are cleared to O.
CASE 2. If the quotient is less than _(2 16 - 1) or greater than (2 16 - 1) for DIV
or if the quotient is less than - (2 32 - 1) or greater than (2 32 - 1) for DIVL, then
the destination register is unmodified. The V flag is set to 1, and the C, Z, and S
flags are cleared to O.
CASE 3. If the quotient is greater than _(2 15 + 1) and less than (2 15) for DIV or if
the quotient is greater than -(2 31 + 1) and less than (2 31 ) for DIVL, then the quotient and remainder are left in the destination register as defined above. The V and
C flags are cleared to 0 and the Sand Z flags are set according to the value of the
quotient.
CASE 4. If none of the above cases applies, then all of the remainder and all but
the Sign bit of the quotient are left in the destination register. The V and C flags are
set to 1, the Z flag is cleared to 0, and the S flag indicates the sign of the quotient.
In this case, the S flag can be replicated into the high-order half of the destination
to produce the twos complement representation of the quotient with the same precision as the original dividend.

Flags:

c: For CASE 4 set;

cleared otherwise

Z: Set if the quotient or divisor is zero; cleared otherwise
S: For CASE 1 and CASE 2 cleared; for CASE 3 and CASE 4 set if the quotient is
negative; cleared otherwise

V: For CASE 3 cleared; set otherwise
D: Unaffected
H: Unaffected
Exceptions:

Integer Overflow trap
6-63

Source
Addressing
Mode

Assembler Language
Syntax

DIV RRd, Rs

DIVL RQd, RRs

1M:

DIV RRd, #data

Instruction Format

1101 011011

RRd

11010110101 RRs

o0 I 0 1 1 0 1 1

RQd

I 0 0 0 oT

RRd

data
DIVL RQd, #data

001 011010

I00001 RQd

data (high)
data (low)

IR:

DIV RRd, @RS1

DIVL RQd, @RS1

EAM:

DIV RRd, eam

10010110111Rs*01 RRd
10010110101 Rs*O

o1T 0 1 1 0 1 1 I

I RQd

eam 1 RRd

1, 2, or 3 extension words
DIVL RQd, eam

I 01 1 01 0 I eam TRQd
1, 2, or 3 extension words

Example:

If register AAO (composed of word registers AO and A1) contains %00000022 and
register A3 contains 6, executing the instruction
DIV

AAO,A3

leaves the value %00040005 in AAO (A1 contains the quotient 5 and AO contains
the remainder 4).
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-64

DIVU
Divide Unsigned
DIVU dst, src
DIVUL
Operation:

dst: R
src: R, 1M, IR, EAM

Word: (dst is longword register, src is word):
dst < 31 :0> is divided by src < 15:0 >
(dst< 31:0> = quotient x src < 15:0> + remainder)
dst < 15:0> - quotient
dst<31:16> - remainder
Longword: (dst is quadword register, src is longword ):
dst<63:0> is divided by src<31:0>
(dst< 63:0 >
quotient X src < 31 :0> + remainder)
dst < 31 :0 > - quotient
dst<63:32> - remainder

The destination operand (dividend) is divided by the source operand (divisor). The
quotient is stored in the low-order half of the destination and the remainder is stored
in the high-order half of the destination. The contents of the source are not affected.
Both operands are treated as unsigned integers. For DIVU, the destination is a
longword register and the source isa word value; for DIVUL, the destination is a
quadword register and the source is a longword value.
For proper instruction execution the "dst field" in the DIVUL instruction encoding
must specify a valid code for a quadword register.
There are three possible outcomes of the unsigned divide instruction.
CASE 1. If the divisor is 0, then the destination register is unmodified, the V and Z
flags are set to 1, and the C and S flags are cleared to O.
CASE 2. If the quotient is greater than (2 16 - 1) for DIVU or if the quotient is
greater than (2 32 - 1) for DIVUL, then the destination register is unmodified. The V
flag is set to 1, and the C, Z, and S flags are cleared to O.
CASE 3. If the quotient is less than 216 for DIVU, or if the quotient is less than 232
for DIVUL, then the quotient and remainder are left in the destination register as
. defined above. The V and C flags are cleared to 0 and the Sand Z flags are set according to the value of the quotient, as described below.
Flags:

c: Cleared
Z: Set if the quotient or divisor is zero; cleared otherwise
S: For CASE 1 and CASE 2 cleared; for CASE 3 set if the most-significant bit of the
result is set; cleared otherwise

V: For CASE 1 and CASE 2 set; cleared otherwise
0: Unaffected
H: Unaffected
Exceptions:

Integer Overflow trap

6-65

Source
Addressing
Mode

Assembler Language
Syntax

DIVU RRd, Rs

Instruction Format

0111101000000011

1 01 0 1 1 0 1 1
DIVUL ROd, RRs

DIVU RRd, #data

RRd

0111101000000011
1

1M:

oj 0 1 1 0 1 0

RRs

J ROd

0111101000000011

o 01

0 1 1 0 1 1 0 0 0 0 1 RRd
data

DIVUL ROd, #data

0111101000000011

o 0 10 1 1 0 1 0

0 0 0 0 1 ROd

data (high)
data (low)

IR:

DIVU RRd, @RSl

DIVUL ROd, @RSl

EAM:

DIVU RRd, eam

01111010

00000011

001011011

Rs*O 1 RRd

01111010

0000 0011

001011010

Rs*O 1 ROd

01111010

00000011

011011011

eam 1 RRd

1,2, or 3 extension words
DIVUL ROd, eam

0111101000000011

o1 10 1 1 0 1 0

eam

ROd

1,2, or 3 extension words

Example:

If longword register RRO (composed of word registers RO and R1) contains the value
%OOOOOFOO, executing the instruction
DIVU

RRO,#%81

leaves the quotient %001 D in R1 and the remainder %0063 in RO.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-66

DJNZ

Decrement and Jump if Not Zero
DJNZ cnt, dst
DBJNZ
DLJNZ
Operation:

cnt - cnt - 1
If cnt =1= 0 then PC -

cnt: R
dst: RA

PC - (2 x displacement)

The counter ("cnt") is decremented. If the contents of the counter are not zero after
decrementing, the destination address is loaded into the Program Counter (PC).
Otherwise, when the counter reaches zero, control falls through to the instruction
following DJNZ, DBJNZ, or DLJNZ. This instruction provides a simple method of
loop control.
The destination address is calculated by subtracting twice the displacement in the
instruction from the updated value of the PC. The updated PC value is the address
of the instruction word following the DJNZ, DBJNZ, or DLJNZ instruction. The
displacement is a 7-bit positive value in the range 0 to 127. Thus, the destination
address must be in the range -252 to 2 bytes from the start of the DJNZ or DBJNZ
instruction or - 250 to 4 bytes from the start of the DLJNZ instruction. The
assembler automatically calculates the displacement by subtracting the PC value of
the following instruction from the address given by the programmer and dividing the
result by two.
Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

RA:

Assembler Language
Syntax
DJNZ Rcnt. address
DBJNZ Rbcnt. address
DWNZ RRcnt. address

Instruction Format

11 1 1 1

I Rent Iwi

disp

0111101000000010

11111RR ent 111

disp

6-67

Example:

DJNZ, DBJNZ and DLJNZ are typically used to control a "loop" of instructions. In
this example for compact mode, 100 bytes are moved from one buffer area to
another, and the Sign bit of each byte is cleared to o. Register RHO is used as the
counter.
llinitalize counter
RHO,ft100
LDB
IIload start address
R1,ftSRCBUF
LD
R2,ftDSTBUF
LD
LOOP:
RLO,@R1
IIload source byte
LDB
IImask off sign bit
RLO,ft7
RESB
@R2, RLO
IIstore into destination
LDB
lIadvance pointers
R1
INC
R2
INC
IIrepeat until counter
0
DBJNZ
RHO, LOOP
NEXT:

In segmented or linear mode, longword registers must be used instead of R1 and
R2.

6·68

Privileged Instruction

Enable Interrupts
Int: VI, NVI

EI int
Operation:

If instruction < 0> = 0 then NVI - 1
If instruction < 1 > = 0 then VI - 1
Any combination of the Vectored Interrupt (VI) or Non-Vectored Interrupt (NVI) control bits in the Flag and Control Word (FCW) are set to 1 if the corresponding bit in
the instruction is 0, thus enabling the appropriate type of interrupt. If the
corresponding bit in the instruction is 1, the control bit is not affected. No other bits
in the FCW are affected. There may be zero, one or two operands in the assembly
language statement, in either order, specifying no source operand is equivalent to
specifying both VI and NVI.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax
EI in!

Example:

Instruction Format

10111110010000011ylxl

If the NVI control bit is set to 1 in the FCW, and the VI control bit is cleared 0, executing the instruction
EI VI
leaves both the NVI and VI control bits in the FCW set to 1.

6-69

ENTER
Enter

ENTER mask, siz

Operation:

mask: 1M
siz: 1M

tmp1 - mask
if FCW.EtC then n - 13
else n - 14
for i = n down to 8 do
if tmp1 = 1 then push RR [2 X i -16]
for i = 7 down to a do
if tmp1 =1 then push RR [2xi+16]
tmp2 - tmp1
tmp2 <15> - FCW.IV
if FCW.EtC then
push RR12
push tmp2
push a
else
push R14
push tmp2
push a
FP-SP
SP-SP + siz
FCW.IV- tmpl<15>

"segmented or linear mode
"compact mode
"save registers

"segmented or linear mode
"save FP
"save mask word
//initialize exception handler address
"(Iongword)
"compact mode
"save FP
"save mask word
"initialize exception handler address
"(word)
"allocate activation record
"reserve local storage

This instruction is executed upon entering a procedure to allocate and initialize an
activation record on the processor stack. The operation involves saving the
specified general-purpose registers, saving and adjusting the Frame Pointer (FP), initializing the pointer to the procedure's exception handler, saving the current setting
of the Integer Overflow trap enable bit, initializing the Integer Overflow trap enable
bit, and reserving the local storage area.
The bits in the mask word operand (called the Enter Mask) correspond to generalpurpose longword registers, as shown in Figure 6-2. When a mask bit is set to 1, the
corresponding register is saved on the stack. Bit 15 of the Enter Mask corresponds
to the setting of FCW.IV, the Integer Overflow trap enable bit, after the Enter instruction is executed. The Enter Mask is used to construct the Exit Mask, which is
saved on the stack. The bits in the Exit Mask correspond to the longword registers
that have been saved and the setting of FCW.IV before the Enter instruction is executed.
The activation record format in compact mode is shown in Figure 6-3a. After the
saved PC, which has been pushed by the previous CALL or CALR instruction, the
specified general-purpose longword registers are pushed on the stack. Next, the
Frame Pointer (R14) is pushed on the stack, followed by the Exit Mask. Then a word
containing a is pushed on the stack to initialize the pointer to the exception handler
for the entered procedure. Finally, the size operand word is added to SP (R15), and
FP is left pointing to the exception handler address.
The activation record format in segmented or linear mode, shown in Figure 6-3b, is
similar. After the specified general-purpose longword registers are pushed onto the
stack, the Frame Pointer (RR12) is pushed, followed by the Exit Mask. Then a
longword containing a is pushed on the stack to initialize the exception handler
pOinter. Finally, the sign-extended size operand word is added to SP (RR14), and FP
is left pointing to the exception handler address.
6-70

IS
I

SAVE RRII
SAVE RRla
SAVE RRZO
SAVE RR22
SAVE RFI24
SAVE RR2I
SAVE RR2I
SAVE RR30
SAVE RAO
SAVE RRZ
SAVE RR4
SAVE RRI
SAVE RRe
SAVE RRIO
{ SAVE RRIZ (COMPACT MODE)
o (SEGMENTED OR LINEAR MODE)
{ NEW FCW.IV (ENTER MASK)
SAVED FCW.IV (EXIT MASKI

Figure 6·2. Enter Mask and Exit Mask Formats

LOW

ADD::::l~ll
LOCAL
STORAGE
AREA

FP_

LOW

ADD:::!~ll
LOCAL
STO RAGE
AREA

FP-

EXIT_MASK
SAVED FP
SAVED RRle
TO
SAVED RR30
SAVED RRO

NEW
ACTIVATION

EXIT_MASK

SAVED FP (HIGH)

SAVED RRIZ
SAVED PC

FP'_~

HIGH
ADDRESS

SAVED RRla
TO
SAVEDRR30
SAVED RRO
TO

--,

CALLER'S
ACTIVATION
RECORD

SAVED RRIO
SAVED PC (HIGH)

---J

Iword
FP I, the Frame Pointer lUI' ENTER,
SP 10 Iho Stock Pointor ollar ENTER,
FP' 10 tho From. Polnl.r bofo.. ENTER,
SP' 10 tho Siock Polnt.r bolo.. ENTER
and ollor CALL or CALR.

NEW
ACTIVATION

SAVED FP (LOW)

TO
SP'-.p

0
0

SAVED PC (LOW)

FP'_~

HIGH
ADDRESS

J"'
I

CALLER'S
ACTIVATION
RECORD

..J

tword FP 10 th. From. Polntar all.r ENTER,
SP 10 th. Stack PoIntar altar ENTER,
FP' 10 Ih. From. Polntar bofor. ENTER,
SP' 10 th. Stack Polntar bofo.. ENTER
and ollor CALL or CALR.

Figure 6·3a. Activation Record Format
(Compact Mode)

8225·012,013,014

Figure 6·3b. Activation Record Format
(Segmented or Linear Mode)

6·71

Flags:

No flags affected

Exceptions:

None

Addressing
Mode
1M:

Assembler Language
Syntax
ENTER*
enteC.,mask,*siZ

Instruction Format

011110101000010101
enter_mask
siz

Example:

6-72

Executing the instruction
ENTER 1%05,1100
saves registers RR16 and RR20 on the stack, clears
tivation record with 100 bytes of local storage.

Few. IV, and allocates an ac-

EX
Exchange
EX dst,
EXB
EXL
Operation:

src

dst: R
src: R, IR, EAM

tmp - src
src - dst
dst - tmp
The contents of the source operand are exchanged with the contents of the destination operand.

Flags:

No flags affected

Exceptions:

None

Source
Addressing
Mode

Assembler Language
Syntax

EX Rd, Rs
EXB Rbd, Rbs
EXL RRd, RRs

Instruction Format

0111101000000010
1 oj 1 01 1 01

IR:

RRs 1 RRd

EX Rd, @Rs'
EXB Rbd, @Rs'
EXL RRd, @Rs'

0111101000000010
001101101

EAM:

EX Rd, eam
EXB Rbd, eam

Rs*ol RRd

o 1 11 0 1 1 01 W Rs * 0 1 Rd
address

EXL RRd, eam

0111101000000010
o 111 0 1 1 0 1

1 RRd

1, 2, or 3 extension words

Example:

If register RO contains 8 and register R5 contains 9, executing the instruction
EX

RD,R5

leaves the values 9 in RO and 8 in R5.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-73

EXIT

Exit

EXIT
Operation:

if FCW.EtC then
SP - FP+4
pop tmp1
pop RR12

IIsegmented or linear mode
IIskip over exception handler
IIExit Mask
IIrestore FP

n -13
else
SP - FP+2
pop tmp1
pop R14
n-14
for i = 0 to 7 do
if tmp1 = 1 then pop RR
for i = 8 to n do
if tmp1 = 1 then pop RR
FCW.IV - tmp1 < 15>

IIcompact mode
IIskip over exception handler
IIExit Mask
IIrestore FP
[2 x i + 16]
[2 x i - 16]

This instruction removes an activation record created with the ENTER instruction.
(See the description of the ENTER instruction for more detailed Information about
the activation record and Exit Mask formats.)
In compact mode, first the value of the Frame Pointer (R14) is incremented by two
and loaded Into SP (R15), removing the local storage area and exception handler
pointer from the processor stack. Next, the Exit Mask and Frame Pointer are
popped from the stack. Then, the longword registers specified by the Exit Mask are
popped from the stack, and FCW.IV is loaded from bit 15 of the Exit Mask.
In segmented or linear mode, first the value of the Frame Pointer (RR12) is incremented by four and loaded into SP(RR14), removing the local storage area and exception handler pointer from the processor stack. Next, the Exit Mask and Frame
Pointer are popped from the stack. Then, the longword registers specified by the Exit Mask are popped from the stack, and FCW.IV is loaded from bit 15 of the Exit
Mask.

Flags:

No flags affected

Exceptions:

None

Assembler Language
Syntax
EXIT

Example:

Instruction Format

1011110101000001101

At the end of a procedure that has been called using CALL or CALR instructions and
that has been entered using the ENTER instruction, executing the instruction sequence
EXIT
RET
returns control to the caller at the instruction following the CALL and leaves the
caller's activation record on top of the stack.

6-74

EXTR
Extract Field
EXTR dst, src, pos, siz
EXTRU

Operation:

dst -

dst: R
src: R, IR, EAM
pos: 1M, R
siz: 1M, R

src (pos,siz)

This instruction is used to extract a bit field from memory or a longword register and
load it into a longword register. For a description of bit fields see Section 6.2.6.
The bits in the source field are loaded, right-justified, into the least-significant bits of
the destination longword register. For EXTR the remaining bits in the destination are
loaded with the most-significant bit of the field. For EXTRU the remaining bits in the
destination are cleared to O.
The position and size operands can be specified as immediate values in the range 0
to 31 or in a word or longword register. The assembler encodes each operand in a
6-bit field of the instruction with the following format:

n n n n

1 0

1 1

5-bit unsigned immediate value
word register contains value
longword register contains value

c: Cleared

Flags:

Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
V: Cleared
D: Unaffected
H: Unaffected
Exceptions:

Source
Addressing
Mode

None

Assembler Language
Syntax
EXTR RRd,RRs,pos,siz

Instruction Format

1 01 0 1 1 1 0 0 1 RRs 11 0 1 0
RRd 1

EXTRU RRd,RRs,pos,siz

EXTR RRd,@Rsl,pos,siz

pos

siz

pos

o 01 0 1 1 1 0 0 1 Rs .. 0 11
RRd

EXTRU RRd, @Rsl,pos,siz

1 01 0 1 1 1 0 0 1 RRs 11 0 1 1
RRd

IR:

siz

o 01

siz

010

pos

0 1 1 1 0 0 1 Rs .. 0 11 0 1 1

RRd

siz

pos

6-75

Source
Addressing
Mode

Assembler Language
Syntax

EAIIII:

EXTR RRd,eam,pos,siz

Instruction Format

o 1J 0 1 1 1 00 1 earn 11 0 1 0
RRd

siz

pos

1, 2, or 3 extension words
EXTRU RRd,eam,pos,siz

o 11 0 1 1 1 001
RRd 1

siz

earn 11 0 1 1

pos

1, 2, or 3 extension words

Example:

If register RR4 contains %01200000 (00000001 001000000000000000000000),
executing the instruction
EXTR RR6,RR4,#7,#3
extracts the 4-bit field 1001 beginning at the 7th bit from the most-significant bit of
RR4 and leaves the sign-extended value % FFFFFFF9 in RR6. Note that the size
operand (#3) has a value one less than the number of bits in the field (4).
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-76

EXTS
Extend Sign
EXTSB dst
EXTS
EXTSL
Operation:

dst: R

Byte
if dst<7>

Word
if dst< 15>

Longword
if dst< 31>

then dst< 15:8> - 000 ... 000
else dst < 15:8> - 111 ... 111
then
dst<31:16> else
dst < 31 :16 > then
dst< 63:32 > else
dst < 63:32 > -

000 ... 000
111 ... 111

The Sign bit of the low-order half of the destination operand is copied into all bit
positions of the high-order half of the destination. For EXTSB the destination is a
word; for EXTS and EXTSL, the destination is a longword register.
This instruction is useful in multiple precision arithmetic or for conversion of small
signed operands to larger signed operands (for example, before a divide).
Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

EXTSB Rd

EXTS RRd

EXTSL ROd

Example:

Instruction Format

1101110001 1 Rd

10000

110 11 10 0 0 1 1 RRd 1 1010

1101110001 1 RQd

10111

If longword register RR2 (composed of word registers R2 and R3) contains
% 12345678, executing the instruction
EXTS RR2
leaves the value %00005678 in RR2 (because the sign bit of R3 was 0).

6-77

HALT

Privileged Instruction

Halt
HALT
Operation:

The CPU enters halted state (see Section 7.2), in which instruction execution
ceases. Only the occurrence of reset or an enabled interrupt causes the CPU to
leave halted state. After HALT is executed, the address of the instruction following
HALT is in the PC, which will be saved on the system stack during interrupt processing.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax
HALT

6-78

Instruction Format

101111010

00000000

Privileged Instruction

Input
IN dst, src
INB
INL
Operation

dst -

dst: R
src: IR, DA

src

The contents of the source operand, an input port, are loaded into the destination
register. 1/0 port addresses are 16 bits.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Source
Addressing
Mode
IR:

Assembler Language
Syntax
IN Rd, @Rs
INS Rbd, @Rs
INL RRd, @Rs

DA:

Instruction Format

IN Rd, port
INS Rbd, port

INL RRd, port

01111010

00000010

0011 1 1 1 01

Rs*O 1 RRd

001111011W

10100

port

0111101000000010
0011 1 1 0 1 1

RRd 10 1 00

port

Example:

If register R6 contains the 1/0 port address % 0123 and the port %0123 contains
% FF, executing the instruction
INB RH2, @R6
leaves the value % FF in register RH2.

6-79

INC
Increment
INC dst, src
INCB
INCL

Operation:

dst -

dst

+ src (src =

dst: R, IR, EAM
src: 1M

1 to 16)

The source operand (a value from 1 to 16) is added to the destination operand and
the sum is stored in the destination. Twos complement addition is performed. If the
source operand is omitted from the assembler language statement, the default value
is 1.
The value of the source field in the instruction is one less than the actual value of
the source operand. Thus, the coding in the instruction for the source ranges from
o to 15, which corresponds to the source values 1 to 16.

Flags:

C:
Z:
S:
V:

Exceptions:

Integer Overflow trap

Unaffected
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Set if arithmetic overflow occurs, that is, if both operands were of the same sign
and the result is of the opposite sign; cleared otherwise
D: Unaffected
H: Unaffected

Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

INC Rd, #n
INCB Rbd, #n
INCL RRd, #n

0111101000000010
1 0 11 0 1 0 0 1

IR:

INC @Rd 1 , #n
INCB @Rdl, #n
INCL @Rdl, #n

0111101000000010
001101001

EAM:

RRd 1 n - 1

INC earn, #n
INCB earn, #n

Rd*O 1 n - 1

01 11 01 001 w1 eam 1 n - 1
1, 2, or 3 extension words

INCL earn, #n

0111101000000010

o 1 11 0 1 0 0 1

eam 1 n - 1

1,2, or 3 extension words

6-80

Example:

If register RH2 contains %21, executing the instruction
INCB

RH2,#6

leaves the value % 27 in RH2.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-81

INCI
Increment Interlocked
dst: IR, EAM
src: 1M

INCI dst, src
INCIB

Operation:

dst -

dst

+ src (src

= 1 to 16)

The source operand (a value from 1 to 16) is added to the destination operand and
the sum is stored in the destination. Twos complement addition is performed. If the
source operand is missing from the assembler language statement, the default
value is 1.
The value of the source field in the instruction is one less than the actual value of
the source operand. Thus, the coding in the instruction for the source ranges from a
to 15, which corresponds to the source values 1 to 16.
This is an interlocked instruction. No other interlocked accesses are permitted to
the destination memory location between fetching and storing the result.

Flags:

C:
Z:
S:
V:

Exceptions:

Integer Overflow trap

Unaffected
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Set if arithmetic overflow occurs, that is, if both operands were of the same
sign, and the result is of the opposite sign; cleared otherwise
D: Unaffected
H: Unaffected

Destination
Addressing
Mode
IR:

Assembler Language
Syntax
INCI @Rd 1 , ifn
INCIS @Rd 1 , ifn

Instruction Format

01111010

00000100

00j10100\W Rd*O \ n-1

EAM:

INCI eam, ifn
INCIS eam, ifn

0111101000000100
0111 01 001 w

earn 1 n -1

1, 2, or 3 extension words

Example:

This instruction can be used to allocate or release copies of a system resource in a
multiprocessor environment. For example, several processes running on different
processors can share use of a common page in memory. It is necessary to keep a
reference counter for the number of active processes using the shared page. When
a new process requires use of the page the reference counter is incremented. The
INCI instruction should be used so that one processor completes the fetch and store
of the counter in memory before any other processor accesses the counter.
INCI

REFERENCLCOUNTER, #1

//increment reference counter
lIfor shared page

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-82

IND

Privileged Instruction

Input and Decrement
INO dst, src, r
INOB
INOL
Operation:

dst: IR
src: IR

dst - src
AUTOOECREMENT dst (by 1 if INOB; by 2 if INO; by 4 if INOL)
r- r - 1
This instruction is used for block input of strings of data. The contents of the 1/0
port addressed by the source word register are loaded into the memory location addressed by the destination register. 1/0 port addresses are 16 bits. The destination
register is then decremented by one if INOB, by two if INO, or by four if INOL, thus
moving the pointer to the previous element of the string in memory. The word
register specified by "r" (used as a counter) is then decremented by one. The address of the 1/0 port in the source register is unchanged. The source, destination,
and counter registers must be distinct and non-overlapping registers.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected
Exceptions:

Privileged Instruction trap

Addressing
Mode

Assembler Language
Syntax

IR:

INO @Rd 1 @Rs r
INOB @Rdl, @RS, r

INOL @Rdl, @Rs, r

Instruction Format

00111011 w Rs,o 0 1000
00001

Rd,o 0 1000

01111010

0000 001 0

00111011
0000

Example:

Rs,oO 1000
Rd,oO

1000

In linear mode, if register RR24 contains %00004000, register R6 contains the 1/0
port address %0228, the port %0228 contains %05B9, and register RO contains
%0016, executing the instruction
INO @RR24, @R6, RO
leaves the value %05B9 in location %00004000, the value %00003FFE in RR24,
and the value %0015 in RO. The V flag is cleared. Register R6 still contains the
value %0228. In compact mode, a word register must be used instead of RR24.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-83

INDEX
Index
INDEX dst, sub, src
INDEXL

Operation:

dst R
sub: R
src: IM,IR,EAM

tmp - EFFECTIVE_~A.DDRESS (src)
lower- @tmp
if sub < lower then Index Error trap
tmp - tmp + (2 if INDEX; 4 if INDEXL)
upper - @tmp
if sub> upper then Index Error trap
tmp - tmp + (2 if INDEX; 4 if INDEXL)
scale - @tmp
dst - (dst + (sub -lower)) x scale
This instruction is used to check an array subscript and calculate the corresponding
index value. For arrays with multiple dimensions, the instruction performs one step
of the index calculation, accumulating the index value in the destination.
The subscript is compared against the bounds specified by the source operand. If
the subscript is less than the lower bound or greater than the upper bound, then the
destination and flags are unaffected and an Index trap occurs. If the subscript is in
bounds, then the lower bound is subtracted from the subscript, the difference is added to the destination, the sum is multiplied by the scale factor, and the product is
stored into the destination. The subscript, lower bound, upper bound, scale factor,
and destination are all the same size, either word or longword. The operands are
treated as signed integers. The contents of the subscript and source are not affected.
The source operand specifies the lower bound. The upper bound and scale factor
are located at the next two consecutive words or longwords.
When the instruction is used appropriately, an Index trap occurs if the calculated index is outside the array. Hence, overflow is not detected during the index calculation. If overflow does occur during addition, only the less-significant word or
longword of the sum is stored into the destination. If overflow does occur during
multiplication, only the less-significant word or longword of the product is stored.

Flags:

Unaffected if Index Error trap; cleared otherwise

Z: Unaffected if Index Error trap; else set if the result is zero; cleared
otherwise

S: Unaffected if Index Error trap; else set if the most-significant bit of the
result is set; cleared otherwise

V: Unaffected if Index Error trap; cleared otherwise
D: Unaffected
H: Unaffected
Exceptions:

6·84

Index Error trap

Source
Addressing
Mode
1M:

Assembler Language
Syntax
INDEX Rd, Rsub,
Iflower,lfupper,
Ifscale

Instruction Format

001001101

0000 1 1 1 0

00001 Rsub

Rd;OO 0000

lower
upper
scale
INDEXL RRd, RRsub,
Iflower,lfupper,
#Scale

00J001101

0000 1 1 1 1

00001 RRsub RRd;OO 0000
lower (high)
lower (low)
upper (high)
upper (low)
scale (high)
scale (low)

IR:

INDEX Rd, Rsub, @Rs'

INDEXL RRd, RRsub, @Rs'

001 001 1 01

Rs;OO

00001 Rsub

Rd;OO 0000

1110

001001101

Rs;OO 1 1 1 1

00001 RRsub RRd;OO 0000

EAM:

INDEX Rd, Rsub, eam

OiI001101

eam

1110

00001 Rsub

Rd;OO

0000

1, 2, or 3 extension words
INDEXL RRd, RRsub, eam

0 11001101

eam

1111

00001 RRsub RRd;OO 0000
1, 2, or 3 extension words

6-85

Example:

The subscript values for a two-dimensional array of records range from 10 to 20 and
from 1 to 100. Each record in the array is 12 bytes. The base address of the array is
contained in RR2. the first subscript value is contained in RR6. and the second
subscript value is in RR8. Executing the instruction sequence (in segmented or
linear mode)
IIinitialize index register
CLRL RR4
IIcheck and accumulate first
INDEXL RR4.RR6.*10.fI20.*100
IIsubscript
IIcalculate array index
INDEXL RR4.RR8.*1.*100.*12
//load first byte of record
LDB RHO.RR2(RR4)
loads the first byte of the indexed record into RHO.
Note 1: Word register In compact mode. longword register in segmented or linear modes.

6-86

Privileged Instruction
IN DR
Input, Decrement and Repeat
INOR dst, src, r
INORB
INORL

Operation:

dst: IR
src: IR

repeat
dst - src
AUTOOECREMENT dst (by 1 if INORB; by 2 if INOR; by 4 if INORL)

r- r - 1
until r = 0
This instruction is used for block input of strings of data. The contents of the 1/0
port addressed by the source word register are loaded into the memory location addressed by the destination register. 1/0 port addresses are 16 bits. The destination
register is then decremented by one if INORB, by two if INOR, or by 4 if INORL,
thus moving the pointer to the previous element of the string in memory. The word
register specified by "r" (used as a counter) is then decremented by one. The address of the 1/0 port in the source register is unchanged. The entire operation is
repeated until the result of decrementing r is zero. This instruction can input from 1
to 65,536 data elements. The source, destination, and counter registers must be
distinct, non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation.

Flags:

C: Unaffected

Z: Unaffected
5: Unaffected
V: Set
0: Unaffected
H: Unaffected

Exceptions:

Privileged Instruction trap

Addressing
Mode

Assembler Language
Syntax

IR:

IN DR @Rdl, @Rs, r
INDRB @Rdl, @Rs, r

Instruction Format

00001
INDRL @Rdl, @Rs, r

*0
Rd * 0

00111011 w Rs

1000
0000

01111010

0000 0010

00111011

Rs*O

1000

00001

Rd*O

0000

6-87

Example:

In compact mode, if register R1 contains %202A, register R2 contains the 1/0 address %OAFC, and register R3 contains 8, executing the instruction
INDRB @R1, @R2, R3
inputs 8 bytes from the 1/0 port %OAFC and leaves them in descending order from
%202A to %2023. Register R1 contains %2022, and R3 contains O. R2 is not affected. The V flag is set. In segmented or linear mode, a longword register must be
used instead of R1.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-88

INI

Privileged Instruction

Input and Increment
INI dst, src, r
INIB
INIL

Operation:

dst: IR
src: IR

dst - src
AUTOINCREMENT dst (by 1 if INIB; by 2 if INI; by 4 if INIL)
r- r - 1
This instruction is used for block input of strings of data. The contents of the 1/0
port addressed by the source word register are loaded into the memory location addressed by the destination register. 1/0 port addresses are 16 bits. The destination
register is then incremented by one if INIB, by two if INI, or by four if INIL, thus
moving the pointer to the next element of the string in memory. The word register
specified by "r" (used as a counter) is then decremented by one. The address of
the 1/0 port in the source register is unchanged. The source, destination, and
counter registers must be distinct, non-overlapping registers.

Flags:

Unaffected
Z: Unaffected
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Exceptions:

Privileged Instruction trap

Addressing
Mode
IR:

Assembler Language
Syntax
INI @Rd 1 @Rs r
INIB @Rdl, @Rs, r

INIL @Rdl, @Rs, r

Example:

Instruction Format

00111011 w Rs 0 0000
Rd,* 0 1000
00001

01111010

0000 0010

00111011

Rs,*O 0000

00001

Rd,*O 1000

In compact mode, if register R4 contains %4000, register R6 contains the 1/0 port
address %0229, the port %0229 contains %B9, and register RO contains %0016,
executing the instruction
INIB @R4, @R6, RO
leaves the value % B9 in location %4000, the value %4001 in R4, and the value
%0015 in RO. Register R6 still contains the value %0229. The V flag is cleared. In
segmented or linear mode, a longword register must be used instead of R4.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-89

I NI R

Privileged Instruction
Input, Increment and Repeat
INIR dst, src, r
INIRB
INIRL
Operation:

dst: IR
src: IR

repeat
dst - src
AUTOINCREMENT dst (by 1 if INIRB; by 2 if INIR; by 4 if INIRL)
r- r - 1
until r = 0
This instruction is used for block input of strings of data. The contents of the 110
port addressed by the source word register are loaded into the memory location addressed by the destination register. 110 port addresses are 16 bits. The destination
register is then incremented by one if INIRB, by two if INIR, or by four if INIRL, thus
moving the pointer to the next element in the string in memory. The word register
specified by "r" (used as a counter) is then decremented by one. The address of
the 110 port in the source register is unchanged. The entire operation is repeated
until the result of decrementing r is zero. This instruction can input from 1 to 65,536
data elements. The source, destination, and counter registers must be distinct, nonoverlapping registers.
This instruction can be interrupted after each execution of the basic operation.

Flags:

C: Unaffected
Z: Unaffected
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Exceptions:
Addressing
Mode
IR:

Privileged Instruction trap

Assembler Language
Syntax
INIR @Rd1 ,@Rs. r
INIRB @Rd 1 • @Rs. r

Instruction Format
00111011 w Rs * 0 0000

Rd * 0 0000

01111010

0000 0010

0000

00111011
00001

6-90

Rs*O 0000
Rd*O 0000

Example:

In compact mode, if register R1 contains %2023, register R2 contains the 1/0 port
address %0551, and register R3 contains 8, executing the instruction
INIRB @R1,@R2,R3
inputs 8 bytes from port %0551 and leave them in ascending order from %2023 to
%202A. Register R1 contains %202B, and R3 contains O. R2 is not affected. The V
flag is set. In segmented or linear mode, a longword register must be used instead
of R1.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-91

INSRT
Insert Field
INSRT dst, src, pos, siz

Operation:

dst (pos, siz) -

dst: R, IR, EAM
src: R
pos: R, 1M
siz: R, 1M

src

This instruction is used to insert a bit field from a longword register into memory or
a longword register. For a description of bit fields, see Section 6.2.6.
The bits in the destination field are loaded from the least-significant bits of the
source register.
The position and size operands can be specified as immediate values in the range 0
to 31 or in a word or longword register. The assembler encodes each operand in a
6-bit field of the instruction with the following format:

n n n n n
1 0 r r r
1 1 r r r

Flags:

No flags affected

Exceptions:

None

5-bit unsigned immediate value
word register contains value
longword register contains value

Destination
Addressing
Mode

Assembler Language
Syntax

INSRT RRd,RRs,pos,siz

Instruction Format

1 0 10 1 1 1 0
RRs 1

IR:

INSRT @Rd 1 ,RRs,pos,siz

INSRT eam,RRs,pos,siz

siz

RRd 10 1 1 0
1

pos

o 0 I0 1 1 1 0 01 Rd"* 0 10 1 1 0
RRs 1

EAM:

o 11

siz

011100

RRs

siz

pos

I earn I0 1 1 0

pos

1, 2, or 3 extension words

Example:

If register RR2 contains %0101012A (0000 0001 0000000100000001 00101010)
and register RR4 contains % FFFF FFFF, executing the instruction
INSRT RR4,RR2,#4,#6
inserts the 7-bit field 0101010 from the least-significant bits of RR2 into RR4 beginning at the 4th from the most-significant bit, leaving % F55FFFFF
(1111 0101 0101 1111 1111 1111 1111 1111 in RR4. Note that the size operand (#6)
has a value one less than the number of bits in the field (7).
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-92

IRET

Privileged Instruction

Interrupt Return
IRET
Operation:

sp-sp + 2
pop tmp
pop PC
if FCW.T then tmp<9> FCW- tmp

IIpop "identifier"
IIpop FCW
1

This instruction is used at the end of an exception handler routine to return to the
program at the point where the exception occurred. First, an "identifier" word
associated with the exception is popped from the stack. Then, the FCW and PC are
popped from the stack.
After IRET is executed, the Trace Pending bit (FCW.TP) is set if bit 9 is set in the
popped FCW or if the Trace Enable bit (FCW.T) was set before the instruction was
executed. This allows tracing of exception handler routines for single-step debugging. This instruction may be executed in segmented or linear mode only; in compact mode, execution of this instruction is undefined.

Flags:

Loaded from system stack
Z: Loaded from system stack
S: Loaded from system stack
PN: Loaded from system stack
D: Loaded from system stack
H: Loaded from system stack

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax
IRET

Instruction Format

01111011 100000000

6-93

JP
Jump
JP cc, dst
Operation:

dst: IR, EAM

If cc is satisfied, then PC -

EFFECTIVE-ADDRESS (dst)

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

IR:

CC,

@Rd1

EAM:

CC,

eam

Instruction Format

o1 I 0 1 1 1 1 0

I earn I

1,2, or 3 extension words

Example:

If the C flag is set, executing the instruction (in compact mode)
JP

C, %1520

replaces the contents of the PC with % 1520, thus transferring control to that location.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-94

JR
Jump Relative
JR cc, dst
Operation:

dst: RA

if cc is satisfied then PC -

displacement)

A conditional jump transfers program control to the destination address if the condition specified by "cc" is satisfied by the flags in the FCW. See Section 6.3 for a list
of condition codes. If the condition is satisfied, the Program Counter (PC) is loaded
with the destination address; otherwise, the instruction following the JR instruction
is executed. If no condition is specified, the jump is taken regardless of the flag settings.
The destination address is calculated by adding twice the displacement in the instruction to the updated value of the PC. The updated PC value is the address of the
instruction word following the JR instruction. The displacement is an 8-bit signed
value in the range -128 to 127. Thus, the destination address must be in the range
-254 to 256 bytes from the start of the JR instruction. The assembler automatically
calculates the displacement by subtracting the PC value of the following instruction
from the address given by the programmer and dividing the result by two.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

RA:

Example:

Assembler Language
Syntax
JR

ee, address

Instruction Format

11 1 1 0 I

displacement

If the result of the last arithmetic operation executed is negative, the next four instructions (which occupy a total of twelve bytes) are to be skipped. This can be
accomplished with the instruction
JR MI, $ +14
If the S flag is not set, execution continues with the instruction following the JR.
A byte-saving form of a jump to the label LAB is
JR LAB
where LAB must be within the allowed range. The condition code is omitted in this
case, indicating that the jump is always taken.

6-95

LD
Load
LO dst, src
LOB
LOL

Operation:

dst -

dst:
src:
or
dst:
src:
or
dst:
src:

R
R, IR, BA, BX, EAM
IR, BA, BX, EAM

R
R, IR, EAM
1M

src

The contents of the source are loaded into the destination. The contents of the
source are not affected.
There are three versions of the Load instruction: load into a register, load into
memory and load an immediate value .

Flags:

.No flags affected

Exceptions:

None

Load Register
Source
Addressing
Mode

Assembler Language
Syntax
LD Rd, Rs
LDB Rbd, Rbs
LDL RRd, RRs

IR:

LD Rd, @RS1
LDB Rbd, @RS1
LDL RRd, @RS1

BA:

LD Rd, RS1(disp)
LDB Rbd, RS1(disp)

Instruction Format

1101100001 w 1 Rs

11010101001 RRs

RRd

1001100001 w 1 Rso"O 1 Rd
10010101001 Rso"ol RRd

00111 Ooolwi Rso"O

displacement
LDL RRd, RS1(disp)

001 1101 01

I Rso"O I RRd

displacement

BX:

LD Rd, RS1(Rx)
LDB Rbd, RS1(Rx)

LDL RRd, RS1(Rx)

0000

0000 0000

I Rxo"O

01111 01 0 1
0000

6-96

*0 1

o 111 1 0 0 0 1w

I Rxo"O

Rso"O

I RRd

0000 0000

L0 ad Register (Continued)
Source
Addressing
Mode
EAM:

Assembler Language
Syntax
LD Rd, earn
LDB Rbd, earn

Instruction Format

o 1110 0 0 0 1w 1 eam 1 Rd
1, 2, or 3 extension words

LDL RRd, earn

o 11 0 1 0 1 0 0

J eam

1 RRd

1, 2, or 3 extension words

Load Memory
Destination
Addressing
Mode

IR:

Assembler Language
Syntax
LD @Rd1 , Rs
LDB @Rdl, Rbs

Instruction Format

1001101111w1Rd*01

LDL @Rd 1 , RRs

10010111011 Rd*ol RRs

BA:

LD Rd 1(disp), Rs
LDB Rd 1(disp), Rbs

001110011 W Rd*O 1 Rs
displacement

LDL Rd 1(disp), RRs

o 011 1 0 1 1 1

Rd * 0 1 RRs

displacement

BX:

LD Rd 1(Rx), Rs
LDB Rd 1(Rx), Rbs

LDL Rd 1(Rx), RRs

EAM:

LD earn, Rs
LDB earn, Rbs

01110011W Rd*O 1 Rs
00001 Rx*O

00000000

01111 0111

Rd*O 1 RRs

00001 Rx*O

00000000

011101111W

eam 1 Rs

1, 2, or 3 extension words
LDL earn, RRs

o 11 0 1 1 1 0 1

1eam

1 RRs

1, 2, or 3 extension words

6-97

Loa dl mmed"la te Value
Destination
Addressing
Mode
R:

Assembler Language
Syntax
LD Rd, #data

Instruction Format

00 100001100001
data

LDB Rbd, #data2

00 100000

0000

data

11100 I
LDL RRd, #data

I Rbd

data

00001 RRd

001010100

data (high)
data (low)

IR:

LD @Rd 1, #data

o0 I 0 0 1 1 0 1

I Rd * 0 I 0 1 0 1

data

LDB @Rdl, #data

LDL @Rdl, #data

001001100

Rd*O 10101

data

001001101

Rd*O 101 1 1

data (high)
data (low)

EAM:

LD eam, #data

o1 I0 0 1 1 0 1

I earn

!0 1 01

1, 2, or 3 extension words
data

LDB eam, #data

o 11 0 0 1 1 0 0 I

1, 2, or 3 extension words

data

LDL eam, #data

I0 1 0 1

earn

o 1T 001

1 01

data

I earn

101 11

1, 2, or 3 extension words
data (high)
data (low)

6·98

Example:

If register RHO contains %AB, executing the instruction
LD RL7, RHO
loads %AB into RL7.
Note 1: Word register in compact mode, longword register in segmented or linear modes.
Note 2: As shown, the instruction set includes two formats for loading an immediate value into a byte register. The
assembler uses the format with one word.

6-99

LOA
Load Address
LOA dst, src

Operation:

dst .-

EFFECTIV~OORESS

dst: R
src: BA, BX, EAM
(src)

The effective address of the source operand is calculated and loaded into the
destination. The contents of the source are not affected. The address calculation
follows the rules for address arithmetic in the current mode of address representation: compact, segmented or linear. The destination is a word register in compact
mode, and a longword register in segmented or linear mode.

Flags:

No flags affected

Exceptions:

None

Source
Addressing
Mode

Assembler Language
Syntax

BA:

LOA Rd', Rs' (disp)

Instruction Format

0011 01 00

Rs ",,0

displacement

BX:

LOA Rd', Rs' (Rx)

011101 00
0000

EAM:

LOA Rd', eam

I Rx""O

a 1 11 1 0 1 1 a

Rs""O

0000 0000

earn 1 Rd

1,2, or 3 extension words

Examples:

LOA

R4,STRUCT

LOA

RR2,RR4(8)

!lin compact mode, register R4 is loaded
IIwith the compact address of the location
IInamed STRUCT
!lin linear mode, if base register RR4
IIcontains %01000020, then register RR2 is loaded
IIwith the address %01000028

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-100

LDAR
Load Address Relative
LDAR dst, src

Operation:

dst -

dst: R
src: RA

EFFECTIVEjDDRESS (src)

The effective address of the source operand is calculated and loaded into the
destination. The contents of the source are not affected. The destination is a word
register in compact mode, and a longword register in segmented or linear mode.
The destination address is calculated by adding the displacement in the instruction
to the updated value of the Program Counter (PC). The updated PC value is the address of the instruction word following the LDAR instruction. The displacement is a
16-bit signed value in the range -32768 to 32767 in the second word of the instruction. The addition is performed following the rules of address arithmetic in the current mode of address representation: compact, segmented, or linear.
The assembler automatically calculates the displacement by subtracting the PC
value of the following instruction from the address given by the programmer.

Flags:

No flags affected

Exceptions:

None

Source
Addressing
Mode

Assembler Language
Syntax

RA:

LDAR Rdl, address

Instruction Format

00 1 1 0 1 00

I0 00 0 I

displacement

Example:

LDAR RR4, TABLE

/lin segmented mode, register RR4 is
//loaded with the segmented address of TABLE

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-101

LDCTL

Privileged Instruction

Load Control
LOCTL dst, src

Operation:

dst -

dst:
src:
or
dst:
src:

CTLR
R
R
CTLR

src

This instruction loads the contents of a general-purpose word register into a control
register, or loads the contents of a control register into a general-purpose word
register. The control register must be one of the following:
FCW
PSAPSEG
PSAPOFF
NSPSEG
NSPOFF

Flag and Control Word
Program Status Area Pointer-high word
Program Status Area Pointer-low word
Normal Stack Pointer-high word
Normal Stack Pointer-low word

When the destination register is FCW, the Trace Pending bit (FCW.TP) is set if bit 9
of the source operand is set or if the Trace Enable bit (FCW.T) is set before the instruction is executed. This allows tracing of system programs that may load the
FCW mistakenly.

Flags:

No flags affected, except when the destination is the Flag and Control Word (LDCTL
FCW, Rs), in which case all the flags are loaded from the source register.

Exceptions:

Privileged Instruction trap

Load Into Control Register
Assembler Language
Syntax
LDCTL FCW, Rs

LDCTL PSAPSEG, Rs

LDCTL PSAPOFF, Rs

LDCTL NSPSEG, Rs

LDCTL NSPOFF, Rs

6-102

Instruction Format

01111101

Rs 1110 01

01111101

1 1101 1

01111101

1 1110 1

01111101

11 1 1 1 1

1 1010 1

Load From Control Register
Assembler Language
Syntax
LDCTL Rd, FCW

LDCTL Rd, PSAPSEG

LDCTL Rd, PSAPOFF

LDCTL Rd, NSPSEG

LDCTL Rd, NSPOFF

Instruction Format

101111101

I Rd
I Rd
I Rd

101111101

1011111011

Rd
Rd

1 0010 1

1 0100 1

0101

I
I

0110 1
0111 1

6-103

loellB

Load Control Byte
LOCTLB dst, src

Operation:

dst -

dst:
src:
or
dst:
src:

FLAGS
R
R
FLAGS

src

This instruction loads the contents of a general-purpose byte register into the Flags
register, or loads the contents of the Flags register into a general-purpose byte
register. (The Flags register is the low-order byte of the Flag and Control Word
register.) Note that this is not a privileged instruction.

Flags:

When the FLAGS register is the destination, all the flags are loaded from the
source. When the FLAGS register is the source, none of the flags are affected.

Exceptions:

None

Assembler Language
Syntax
LDCTLB FLAGS, Rbs

LDCTLB Rbd, FLAGS

6-104

Instruction Format

10001100

Rbs \10011

10001100

Rbd \ 0 0 0 1 1

Privileged Instruction
LDCTLL
Load Control Longword
LDCTLL dst, src

Operation:

dst -

dst: CTLRL
src: R
or
dst: R
src: CTLRL

src

This instruction loads the contents of a general-purpose longword register into a
control register, or loads the contents of a control register into a general-purpose
longword register. The control register must be one of the following:
SITID
SDTID
NITID
NDTID
SCCL
OSP
HICR
PSAP
NSP

System Instruction Translation Table Descriptor
System Data Translation Table Descriptor
Normal Instruction Translation Table Descriptor
Normal Data Translation Table Descriptor
System Configuration Control Longword
Overflow Stack Pointer
Hardware Interface Control Register
Program Status Area Pointer
Normal Stack Pointer

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Load Into Control Register
Assembler Language
Syntax
LDCTLL SITIO, RRs

LOCTLL SOTIO, RRs

LOCTLL NITIO, RRs

LOCTLL NOTIO, RRs

LOCTLL SCCL, RRs

LOCTLL

asp,

Instruction Format

1100111011 RRs

10000 1

1100111011 RRs

10001 1

1100111011 RRs

10010 1

1100111011 RRs

10011 1

1100111011 RRs

10100 1

RRs

LOCTLL HICR, RRs

1100111011

RRs 1111 0 1

1100111011 RRs 101 1 1 1

6-105
"

.. _...

.~..".--.~.-.~

·"'"·~···-'··E'"=-'"~"=""""'C

Load Into Control Register (Continued)
Assembler Language
Syntax
LDCTLL PSAP. RRs

LDCTLL NSP. RRs

Instruction Format

11 0 0 1 1 1 0 1 1 RRs 11 1 0 0 1

11 0 0 1 1 1 0 1 1 RRs 10 1 1 0 1

Load From Control Register
LDCTLL RRd. SITTD

LDCTLL RRd. SDTTD

LDCTLL RRd. NITTD

LDCTLL RRd. NDTTD

LDCTLL RRd. SCCL

LDCTLL RRd.

asp

LDCTLL RRd. HICR

LDCTLL RRd. PSAP

LDCTLL RRd. NSP

6-106

1100111111 RRd

100001

1100111111 RRd 100011

1100111111 RRd

100101

1100111111 RRd 100111

1100111111 RRd 10100 1

1100111111 RRd 11 1 1 0 1

1100111111 RRd

101 1 11

1100111111 RRd 11 100

1100111111 RRd

10110 1

LDD
Load and Decrement
LDD dst, src, r
LDDB
LDDL
Operation:

dst: IR
src: IR

dst - src
AUTODECREMENT dst and src (by 1 if LDDB; by 2 if LDD; by 4 if LDDL)
r- r - 1
This instruction is used for block transfers of strings of data. The contents of the
location addressed by the source register are loaded into the location addressed by
the destination register. The source and destination registers are then decremented
by one if LDDB, by two if LDD or by four if LDDL, thus moving the pointers to the
previous elements in the strings. The word register specified by "r" (used as a
counter) is then decremented by one. The source destination, and counter registers
must be distinct and non-overlapping registers.
The effect of decrementing the pointers during the transfer is important if the
source and destination strings overlap with the source string starting at a lower
memory address. Placing the pOinters at the highest address of the strings and
decrementing the pointers ensures that the source string will be correctly copied including the overlapping area. However, the destination address must not exceed the
source address by one for LDD, and by one, two, or three for LDDL; otherwise, the
CPU may not recover correctly from address translation exceptions.

Flags:

Unaffected
Unaffected
Unaffected
Set if the result of decrementing r is zero; cleared otherwise
Unaffected
H: Unaffected

Z:
S:
V:
D:
Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

IR:

LDD @Rs\ @Rd\ r
LDDB @Rs\ @Rd 1 , r

Instruction Format

10111011 w Rs;tO

1001

00001

Rd;tO

1000

10111001

Rs;tO

1001

0.0001

Rd;tO

1000

6·107

Example:

In linear mode, if register RR20 contains %0000202A, register RR22 contains
%0000404A, the word at location %0000404A contains % FFFF, and register R3
contains 5, executing the instruction
LDD @RR20, @RR22, R3
leaves the value % FFFF at location %0000202A, the value %00002028 in RR20,
the value %00004048 in RR22, and the value 4 in R3. The V flag is cleared. In compact mode, word registers must be used instead of RR20 and RR22.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-108

LDDR
Load, Decrement and Repeat
LDDR dst, src, r
LDDRB
LDDRL

Operation:

dst: IR
src: IR

repeat
dst - src
AUTODECREMENT dst and src (by 1 if LDDRB; by 2 if LDDR; by 4 if LDDRL)
r- r - 1
until r = 0
This instruction is used for block transfers of strings of data. The contents of the
location addressed by the source register are loaded into the location addressed by
the destination register. The source and destination registers are then decremented
by one if LDDRB, by two if LDD, or by four if LDDL, thus moving the pointers to the
previous elements in the strings. The word register specified by "r" (used as a
counter) is then decremented by one. The entire operation is repeated until the
result of decrementing r is zero. This instruction can move from 1 to 65,536 data
elements. The source, destination, and counter registers must be distinct and nonoverlapping registers.
The effect of decrementing the pointers during the transfer is important if the
source and destination strings overlap with the source string starting at a lower
memory address. Placing the pointers at the highest address of the strings and
decrementing the pOinters ensures that the source string will be correctly copied including the overlapping area. However, the destination address must not exceed the
source address by one for LDDR, and by one, two, or three for LDDRL; otherwise,
the CPU may not recover correctly from address translation exceptions.
This instruction can be interrupted after each execution of the basic operation.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

IR:

LDDR @Rdl, @Rs 1 , r
LDDRB @Rd 1 , @Rsl, r

Instruction Format

10111011w Rs*O

1001

Rd*O

0000

00001

10111001

Rs*O 1001

00001

Rd*O 0000

6-109

Example:

In compact mode, if register R1 contains %202A, register R2 contains %404A, the
words at locations %4040 through %404A all contain % FFFF, and register R3 contains 6, executing the instruction
LDDR @R1, @R2, R3
leaves the value % FFFF in the words at locations % 2020 through % 202A, the
value %201 E in R1, the value %403E in R2, and 0 in R3. The V flag is set. In
segmented or linear mode, longword registers must be used instead of R1 and R2.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-110

LDI
Load and Increment
LOI dst, src, r
LOIB
LOlL
Operation:

dst: IR
src: IR

dst - src
AUTOINCREMENT dst and src (by 1 if LOIS; by 2 if LOI; by 4 if LOlL)
r- r - 1
This instruction is used for block transfers of strings of data. The contents of the
location addressed by the source register are loaded into the location addressed by
the destination register. The source and destination registers are then incremented
by one if LOIS, by two if LOI, or by four if LOlL, thus moving the pointers to the next
elements in the strings. The word register specified by "r" (used as a counter) is
then decremented by one. The source, destination, and counter registers must be
distinct, non-overlapping registers.
The effect of incrementing the pointers during the transfer is important if the source
and destination strings overlap with the source string starting at a higher memory
address. Placing the pointers at the lowest address of the strings and incrementing
the pointers ensures that the source string will be correctly copied including the
overlapping area. However, the destination address must not exceed the source address by one for LOI; and by one, two, or three for LOlL; otherwise, the CPU may
not recover correctly from address translation exceptions.

Flags:

C:
Z:
S:
V:
0:
H:

Unaffected
Unaffected
Unaffected
Set if the result of decrementing r is zero, cleared otherwise
Unaffected
Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

IR:

LDI @Rdl, @RS1, r
LDIB @Rdl, @RS1, r

Instruction Format
10111011 w Rs*O

0001

00001

Rd*O

1000

10111001

Rs*O

0001

Rd*O

1000

000

6-111

Example:

This instruction can be used in a "loop" of instructions which transfers a string of
data from one location to another, but where an intermediate operation on each
data element is required. The following sequence transfers a string of 80 bytes, but
tests for a special value (%OD, an ASCII return character) which terminates the
loop if found. This example assumes compact mode. In segmented or linear mode,
longword registers must be used instead of R1 and R2.
LD
LDA
LDA

R3, #80
R1, DSTSUF
R2,SRCSUF

lIinitialize counter
//load start addresses

@R2, #%OD

IIcheck for return character
lIexit loop if found
/!transfer next byte
IIrepeat until counter = 0

LOOP:

CPS
JR
LDIS
JR

EO,DONE

@R1, @R2, R3
NOV, LOOP

DONE:
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-112

LDIR
Load, Increment and Repeat
LDIR dst, src, r
LDIRB
LDIRL
Operation:

dst: IR
src: IR

repeat
dst - src
AUTOINCREMENT dst and src (by 1 if LOIRB; by 2 if LOIR; by 4 if LOIRL)
r- r - 1
until r = 0
This instruction is used for block transfers of strings of data. The contents of the
location addressed by the source register are loaded into the location addressed by
the destination register. The source and destination registers are then incremented
by one if LOIRB, or by two if LOI, or by four if LOlL, thus moving the pOinters to the
next elements in the strings. The word register specified by "r" (used as a counter)
is then decremented by one. The entire operation is repeated until the result of
decrementing r is zero. This instruction can move from 1 to 65,536 data elements.
The source, destination, and counter registers must be distinct, non-overlapping
registers.
The effect of incrementing the pOinters during the transfer is important if the source
and destination strings overlap with the source string starting at a higher memory
address. Placing the pointers at the lowest address of the strings and incrementing
the pOinters ensures that the source string will be correctly copied including the
overlapping area. However, the destination address must not exceed the source address by one for LOIR, and by one, two, or three for LOIRL; otherwise, the CPU may
not recover correctly from address translation exceptions.
This instruction can be interrupted after each execution of the basic operation.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set
0: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode

Assembler Language
Syntax

I.nstruction Format

IR:

LDIR @Rdl, @Rsl, r
LDIRB @Rd1 , @Rsl, r

10111011W Rs,.O 0001
00001

1 01 11 001
00001

Rd,. 0 0000

Rs,.O

0001

6-113

Example:

The following sequence of instructions can be used in compact mode to copy a buffer of 512 words (1024 bytes) from one area to another. The pointers to the start of
the source and destination are set, the number of words to transfer is set, and then
the transfer takes place.
LOA
LOA
LO
LOIR

R1,OSTBUF
R2,SRCBUF
R3, #512
@R1, @R2, R3

In segmented or linear mode, longword registers must be used instead of R1 and
R2.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·114

LDK
Load Constant
LDK dst, src
LDKL
Operation:

dst -

src (src

dst: R
src: 1M

= 0 to 15)

The source operand, a value from 0 to 15, is loaded into the destination register.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

LDK Rd, #data

LDKL RRd, #data

Example:

Instruction Format

10 111101

0 0111000

I dala

RRd

data

To load register R3 with the constant 9, execute the instruction
LDK

R3,#9

6-115

LDM
Load Multiple
LDM dst, src, n

LDM dst, src

Operation:

dst -

dst:
src:
or
dst:
src:

R
IR, EAM
IR, EAM
R

dst: R
src: 1M

src(n words)

The contents of n (a value from 1 to 16) consecutive source words are loaded into
the destination. The contents of the source are not affected. The instruction can be
used to load multiple word registers either into or from memory. Registers are accessed in increasing order starting with the specified register; RO follows R15.
The value in the instruction field for the number of words loaded ("n") is one less
than the actual number of words. Thus, the coding in the instruction field ranges
from 0 to 15, which corresponds to loading 1 to 16 words.
The starting memory address is calculated once at the start of execution, and incremented by two for each register loaded. If the original address calculation involved a register, the register's value is not affected by incrementing the address
during execution. Similarly, modifying that register during a load from memory does
not affect the address used by this instruction.

Flags:

No flags affected

Exceptions:

None

Load Multiple- Registers From Memory
Source
Addressing
Mode
1M:

Assembler Language
Syntax
LDM Rd, Idatao,
Idata1 .. · .,
Idatan_1

Instruction Format

001011100
00001

0000 0001
0000

n-1

n words data

IR:

LDM Rd, @Rsl, In

001011100
00001

EAM:

LDM Rd, earn, In

011011100
00001

Rs*O

0001

0000

n-1

eam

0001

0000

n-1

1,2, or 3 extension words

6-116

Load Multiple-Memory From Registers
Destination
Addressing
Mode

Assembler Language
Syntax

IR:

LDM @Rd 1 , Rs, Un

EAM:

LDM eam, Rs, Un

Instruction Format

o0 I 0 1 1 1 0 0

o0 0 0 I

0 00 0

n- 1

earn

10 0 1

0 00 0

n- 1

o1 I 0 1 1 1 0 0
o 0 0 0 I Rs

*' 0

1001

1,2, or 3 extension words

Example:

In compact mode, if register R5 contains 5, R6 contains %0100, and R7 contains 7,
executing the instruction
LDM @R6, R5, #3
leaves the values 5, %0100, and 7 at word locations %0100, %0102, and %0104,
respectively; none of the registers is affected. In segmented or linear mode, a
longword register must be used instead of R6.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-117

LDML

Load Multiple Longwords
LDML mask, src

LDML dst, mask

Operation:

src: 1M, IR, EAM
mask: 1M
or
dst: IR, EAM
mask: 1M

Load Multiple Longwords-Registers from Memory
tsrc - EFFECTIV~DDRESS (src)
for i = 0 to 7 do
if mask = 1 then
RR [2 x i + 16]- @tsrc
tsrc - tsrc + 4
for i = 8 to 15 do
if mask = 1 then
RR [2 x i -16]- @tsrc
tsrc - tsrc + 4
Load Multiple Longwords-Memory from Registers
tdst - EFFECTIV~DDRESS (dst)
for i = 0 to 7 do
if mask = 1 then
@tdst- RR [2 x i+ 16]
tdst - ldst + 4
for i = 8 to 15 do
if mask = 1 then
@tdst - RR [2 x i -16];
tdst - tdst + 4
This instruction can be used to load multiple longword registers either into or from
memory. Each bit in the mask operand that is set to 1 corresponds to a longword
register to be loaded. Bits 0 to 7 of the mask operand designate the longword
registers RR16 to RR30 respectively. Bits 8 to 15 of the mask operand designate the
longword registers RRO to RR14 respectively. The format of the mask operand is
shown in Figure 6-4.
15

LOAD RR16
LOAD RR18
LOAD RR20
LOAD RR22
LOAD RR24
LOAD RR26
LOAD RR28
LOAD RR30
LOAD RRO
LOAD RR2
LOAD RR4
LOAD RR6
LOAD RR8
LOAD RR10
LOAD RR12
LOAD RR14

Figure 6·4. Mask Operand Format

6-118

8225-015

The starting memory address is calculated once at the start of execution and incremented by four for each register loaded. If the original address calculation involved a register, the register's value is not affected by incrementing the address
during execution. Similarly, modifying that register during a load from memory does
not affect the address used by this instruction.

Flags:

No flags affected

Exceptions:

None

Load Multiple Longwords- Registers From Memory
Source
Addressing
Mode
1M:

Assembler Language
Syntax
LDML'mask, /ildalao,
/ildala1 ,... ,/ildalan_1

Instruction Format

001 0111001000010101
mask
n longwords data

IR:

LDML /ilmask, @RS1

o 01 0 1 1 1 0 0

1 Rs 0 10 1 0 1

mask

EAM:

LDML, /ilmask, eam

o1 1 0 1 1 1 0 0 1

eam 10 1 0 1

mask

1, 2, or 3 extension words

Load Multiple Longwords-Memory from Registers
Destination
Addressing
Mode

Assembler Language
Syntax

IR:

LDML @Rdl, /ilmask

Instruction Format

o 0 10 1 1 1 0 0

* 0 J1 1 0 1

mask

EAM:

LDML eam, /ilmask

o 1 10 1 1 1 0 0 1

earn 11 1 0 1

mask
1, 2, or 3 extension words

Example:

In linear mode, if base register RR2 contains % 1000 and the longwords at location
% 1000 and % 1002 contain 100 and 150 respectively, executing the instruction
LDML. #5, @RR2
loads 100 into RR16 and 150 into RR20.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·119

LON

Privileged Instruction

Load Normal
LONO dst, src, n
LONOB
LONOL
LON I
LONIB
LONIL
Operation:

dst -

dst:
src:
or
dst:
src:

R
IR, EAM
IR, EAM
R

src

These instructions allow programs executing in system mode to reference information in normal mode data and instruction memory address spaces. This is useful for
accessing system call parameters when system and normal mode address spaces
are separated. The LDND instructions reference normal data space and the LDNI
instructions reference normal instruction space. There are versions of the instructions to load from memory to a register and from a register to memory. When performing the memory reference, the address translation mechanism uses the translation tables for normal data or instruction space, and checks the access permission
for system mode.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Load Register from Normal Space
Source
Addressing
Mode
IR:

Assembler Language
Syntax
LDND Rd, @RS1
LDNDB Rbd, @RS1

LDNDL RRd, @RS1

LDNI Rd, @RS1
LDNIB Rbd, @RS1

Instruction Format

01111010
00110000lw

Rs*O

01111010

0011

01 1 1

001010100

Rs*O

RRd

01111010
00110000lw

LDNIL RRd, @RS1

01111010
001010100

6-120

001 1 01 1 1

0010 01 1 1

Rs*O

0010 01 1 1

Rs*O

RRd

~--

~--~----~-----~

---

Load Register from Normal Space (Continued)
Source
Addressing
Mode

EAM:

Assembler Language
Syntax
LDND Rd, eam
LDNDB Rbd, eam

Instruction Format

0111101000110111
01110000lw

earn

1, 2, or 3 extension words
LDNDL RRd, eam

0111101000110111

o1 10 1 0 1 0 0

earn

RRd

1, 2, or 3 extension words
LDNI Rd, eam
LDNIB Rbd, eam

0111101000100111

o 111 0 0 0 otw

earn

1,2, or 3 extension words
LDNIL RRd, eam

0111101000100111
01101 01 00

earn

RRd

1, 2, or 3 extension words

Load Normal Space from Register
Destination
Addressing
Mode

IR:

Assembler Language
Syntax
LDND @Rdl, Rs
LDNDB @Rd, Rbs

Instruction Format

01111010

001 1

001101111w Rd*O
LDNDL @Rdl, RRs

LDNI @Rdl, Rs
LDNIB @Rdl, Rbs

01111010

001 1 011 1
Rs

001 01 1 1 01

Rd*O

01111010

0010 01 11

00110111jW Rd*O
LDNIL @Rdl, RRs

o 111

01111010

0010 011 1

001 01 1 1 01

Rd*O

RRs

6-121

Load Normal Space from Register (Continued)
Destination
Addressing
Mode

EAM:

Assembler Language
Syntax
LDND eam, Rs
LDNDS eam, Rbs

Instruction Format

01111010
011101111w

001 1 0111
earn

1, 2, or 3 extension words
LDNDL eam, RRs

01111010
011011101

001 1 0111
earn

RRs

1, 2, or 3 extension words
LDNI eam, Rs
LDNIS eam, Rbs

01111010
011101111w

0010 0111

earn

1,2, or 3 extension words
LDNIL eam, RRs

1,2, or 3 extension words

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-122

LDP

Privileged Instruction

Load Physical Address
LDPND dst, src
LDPNI
LDPSI
LDPSD

Operation:

dst -

dst: R
src: IR, EAM

PHYSICAL...ADDRESS (src)

These instructions translate the logical address of the source operand to a physical
address, and store the result into the destination. Four versions of the instruction
are provided, one for each of the logical memory address spaces: normal mode instruction space (LDPNI), normal mode data space (LDPND), system mode instruction space (LDPSI), and system mode data space (LDPSD). The Z flag is set when
the translation is valid, and cleared otherwise.
The V and C flag settings indicate whether or not read and write accesses are permitted to the source byte address. This feature is useful for verifying access rights
for addresses passed as system call parameters from normal to system mode. The
S flag is set when the access information reported in the V and C flags is valid, and
cleared otherwise. (During address translation, the PROT field specifying the access
rights may be valid although one of the translation table entries is invalid.) When address translation is disabled, read and write accesses are permitted to all addresses.

c: LDPND,

Flags:

LDPNI-set if write access is permitted for the source operand in
normal mode; cleared otherwise; LDPSI, LDPSD-set if write access is permitted
for the source operand in system mode; cleared otherwise
Z: Set if the translation is valid; cleared otherwise
S: Set if the protection information in flags C and V is valid; cleared otherwise
V: LDPND, LDPNI-set if read access is permitted for the source operand in
normal mode; cleared otherwise; LDPSI, LDPSD-set if read access is permitted
for the source operand in system mode; cleared otherwise
D: Unaffected
H: Unaffected

Exceptions:

Privileged Instruction trap

Source
Addressing
Mode

Assembler Language
Syntax

IR:

LDPND RRd, @Rs'

LDPNI RRd, @Rs'

LDPSD RRd, @Rs'

LDPSI RRd, @Rs'

Instruction Format

01111010

0011

11 01

001110110

Rs*O

RRd

01111010

0010 11 01

001 11 0110

Rs*O

RRd

01111010

0001

11 01

001110110

Rs*O

RRd

01111010
001110110

0000 11 01

Rs*O

RRd
6-123

Source
Addressing
Mode

Assembler Language
Syntax

EAM:·",

Instruction Format

LDPND RRd, earn

01111010
011110110

001 1 1101
earn

RRd

1, 2, or 3 extension words
LDPNI RRd, earn

01111010
0111 1 01 1 0

0010 1101
earn

RRd

1, 2, or 3 extension words
LDPSD RRd, earn

01111010

0~110110

0001 1101
earn

RRd

1, 2, or 3 extension words
LDPSI RRd, earn

01111010
011110110

0000 1 1 01
earn

RRd

1,2, or 3 extension words

Note 1: Word register' in compact mode, longword register

6-124

I
In

segmented or linear modes.

LOPS

Privileged Instruction

Load Program Status
LOPS src
Operation:

src: IR, EAM

tmp - EFFECTIVEJDDRESS (src)
IIsegmented or linear mode
if FCW.EtC then
tmp 2 - @(tmp1 + 2)
//fetch FCW
PC - @(tmp1 + 4)
//fetch PC (Iongword)
else
IIcompact mode
//fetch FCW
tmp 2 - @tmp1
PC - @(tmp1 + 2)
//fetch PC (low-order word)
if FCW.T then tmp2<9> - 1
FCW- tmp2
The contents of the source operand are loaded into the Program Status (PS)
registers, both the Flag and Control Word (FCW) and the Program Counter (PC). In
compact mode the source operand includes two words: the new FCW and the new
low-order word of PC. The high-order word of PC is unaffected. In segmented or
linear mode, the source operand includes four words: a reserved word (which must
contain 0), the new FCW, and the new PC longword
After LDPS is executed, the Trace Pending bit (FCW.TP) is set if bit 9 is set in the
source operand FCW or if the Trace Enable (FCW.T) bit was set before the instruction was executed. This allows the LDPS instruction to be traced for single-step
debugging.
COMPACT

..OM.NT.D
OR LlN.AR

LOW ADDRESS

FCW

FCW
PCSEG. NO.
PC OFFSET

HIGH ADDRESS

Flags:

All flags are loaded from the source operand.

Exceptions:

Privileged Instruction trap

Source
Addressing
Mode

Assembler Language
Syntax

IR:

LDPS @R S1

EAM:

LDPS earn

Instruction Format

10011110011 Rs*O 100001
o 1J

111001

J earn I0 0 0 0

1,2, or 3 extension words

6-125

Example:

In compact mode, if register R3 contains %5000, location %5000 contains % 1800,
and location %5002 contains % AOOO, executing the instruction
LDPS @R3
leaves the value % AOOO in the PC, and the FCW value is % 1800.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-126

LOR

Load Relative
LOR dst, src
LORB
LORL

Operation:

dst -

dst: R
src: RA
or
dst: RA
src: R

src

The contents of the source operand are loaded into the destination. The contents of
the source are not affected. The effective address is calculated by adding the
displacement in the instruction to the updated value of the program counter (PC).
The updated PC value is the address of the instruction word following the LDR,
LDRB, or LDRL instruction. The displacement is a 16-bit signed value in the range
-32768 to 32767.
The assembler automatically calculates the displacement by subtracting the PC
value of the following instruction from the address given by the programmer.

Flags:

No flags affected

Exceptions:

None

Load Relative Register
Destination
Addressing
Mode
RA:

Assembler Language
Syntax
LOR Rd, address
LORB Rbd, address

Instruction Format

0011000lwl00001

displacement

LORL RRd, address

00110101100001 RRd
displacement

Load Relative Memory
Destination
Addressing
Mode
RA:

Assembler Language
Syntax
LOR address, Rs
LORB address, Rbs

Instruction Format

00110011wlooooi

dlsplacament

LORL address, RRs

00110111100001 RRs
displacement

Example:

LDRR2, DATA

IIregister R2 is loaded with the value in
lithe location named DATA
6-127

MULT
Multiply
MULl dst, src
MULTL

Operation:

dst: R
src: R, 1M, IR, EAM

Word (dst is longword register, src is word)
dst<31:0> - dst<15:0> X src<15:0>
Longword (dst is quadword register, src is longword)
dst<63:0> - dst<31:0> X src<31:0>
The low-order half of the destination operand (multiplicand) is multiplied by the
source operand (multiplier) and the product is stored in the destination. The contents of the source are not affected. Both operands are treated as signed, twos
complement integers. For MULT, the destination is a longword register and the
source is a word value; for MULTL, the destination is a quadword register and the
source is a longword value.
For proper instruction execution, the "dst field" in the MULTL instruction format encoding must specify a valid code for a quadword register. Otherwise, the result is
undefined.
.
The initial contents of the high-order half of the destination register do not affect the
operation of this instruction and are overwritten by the result. The C flag is set to indicate that the upper half of the destination register is required to represent the
result; if the C flag is clear, the product can be correctly represented in the same
precision as the multiplicand, and the upper half of the destination merely holds a
sign extension.

Flags:

Z:
S:
V:
D:
H:

Exceptions:
Source
Addressing
Mode

MULT-set if product is less than _2 15 or greater than or equal to 215 ; cleared
otherwise; MULTL-set if product is less than -2 31 or greater than or equal to
-231 ; cleared otherwise
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Cleared
Unaffected
Unaffected

None

Assembler Language
Syntax
MULT RRd, Rs
MULTL ROd, RRs

1M:

MULT RRd, #data

Instruction Format

11010110011
11 0 1 0 1 1 00 0

o0 I 0 1 1 0 0 1

RRd

Rs
RRs

RQd 1

I0 0 0 0 I RRd

data
MULTL ROd, #data

001 011000100001 RQd
data (high)
data (low)

6-128

Source
Addressing
Mode

Assembler Language
Syntax

IR:

MULT RRd, @Rs'
MULTL ROd, @Rs'

EAM:

MULT RRd, earn

Instruction Format

I
1001011000 I

1001 011001

o 1 I 0 1 1 00 1

Rs*O
Rs*O

I
I

RRd
ROd

I earn I RRd

1, 2, or 3 extension words
MULTL ROd, earn

o 11 0 1 1 000

I earn 1

ROd

1, 2, or 3 extension words

Example:

If register ROO (composed of longword registers RRO and RR2) contains
%2222222200000031 (RR2 contains decimal 49), executing the
instruction
MULT ROO,II10
leaves the value %00000000000001EA (decimal 490) in ROO. The C, Z, S, and V
flags are cleared.
Note': Word register in compact mode, longword register in segmented or linear modes.

6-129

MULTU
Multiply Unsigned
MULTU dst,src
MULTUL
Operation:

dst: R
src: R, 1M, IR, EAM

Word (dst is longword register, src is word)
dst<31:0> - dst<15:0> x src<15:0>
Longword (dst is quadword register, src is longword)
dst<63:0> - dst<31:0> x src<31:0>
The low-order half of the destination operand (multiplicand) is multiplied by the
source operand (multiplier) and the product is stored in the destination. The contents of the source are not affected. Both operands are treated as unsigned integers. For MULTU, the destination is a longword register and the source is a word
value; for MULTUL, the destination is a quadword register and the source is a
longword value.
For proper instruction execution the "dst field" in the MULTUL instruction encoding
must specify a valid code for a quadword register. Otherwise, the result is
undefined.
The initial contents of the high-order half of the destination register do not affect the
operation of this instruction and are overwritten by the result. The C flag is set to indicate that the upper half of the destination register is required to represent the
result; if the C flag is clear, the product can be correctly represented in the same
precision as the multiplicand, and the upper half of the destination merely holds o.

Flags:

Z:
S:
V:
D:
H:

Exceptions:
Source
AddreSSing
Mode

MULTU-set if product is greater than or equal to 216 ; cleared otherwise;
MULTUL-set if product is greater than or equal to 232 ; cleared otherwise
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise
Cleared
Unaffected
Unaffected

None

Assembler Language
Syntax
MULTU RRd, Rs

Instruction Format

0111101000000011

10 011001
MULTUL ROd, RRs

I RRd

0111101000000011
1

6-130

oj 0 1 1 0 0 0

RRs

l RQd

Source
Addressing
Mode

Assembler Language
Syntax

1M:

MULTU RRd, Ifdata

Instruction Format

0111101000000011

o0 \ 0 1 1 0 0 1

0 0 0 0 \ RRd

data
MULTUL ROd, Ifdata

0111101000000011

o0 \ 0 1 1 0 0 0

0 0 0 0 \ RQd

data(high)
data(low)

IR:

MULTU RRd, @Rs'

01111010 0000 0011
00101 1001

MULTUL ROd, @Rs'

EAM:

MULTU RRd, eam

Rs*O

I RRd

01111010

0000 0011

001011000

RS*O\ RQd

01111010 0000 0011
01\011001

earn \ RRd

1, 2, or 3 extension words
MULTUL ROd, eam

0111101000000011

o 1\ 0 1 1 0 0 0

earn \ RQd

1, 2, or 3 extension words

Example:

If register RRO (composed of RO and R1) contains % ABCD FFFF (R1 contains
decimal 65,535), executing the instruction
MULTU

RRO,#16

leaves the value % OOOFFFFO (decimal 1,048,560) in RRO. The C flag is set and the
Z, S, and V flags are cleared.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-131

NEG
Negate
NEG dst
NEGB
NEGL
Operation:

dst -

dst: R, IR, EAM

-dst

The contents of the destination are negated, that is, replaced by twos complement values. Note that %8000 for NEG, %80 for NEGB, and %80000000 for NEGL
are replaced by themselves since in twos complement representation the negative
number with greatest magnitude has no positive counterpart; for these three cases,
the V flag is set.

Flags:

Cleared if the result is zero; set otherwise, which indicates a borrow

Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if the result is %8000 for NEG, %80 for NEGB, or %80000000 for NEGL
cleared otherwise

0: Unaffected
H: Unaffected

Exceptions:
Destination
Addressing
Mode

Integer Overflow trap

Assembler Language
Syntax
NEG Rd
NEGB Rbd
NEGL RRd

IR:

11 0 I 011 1 00

RRd 1001 01

NEG @Rd 1
NEGB @Rd1
NEGL @Rd'

EAM:

Instruction Format

NEG eam
NEGB eam

10 0 0 1 1 1 0 0
01J00110Jw

I Rd *- 0 I0 0 1 01

l eam

10010

1,2, or 3 extension words
NEGL eam

o 1 I0 1 1 1 0 0 I eam

10 0 1 0

1, 2, or 3 extension words

Example:

If register RR8 contains %0000051 F, executing the instruction
NEGL RR8
leaves the value % FFFFFAE1 in RR8.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-132

NOP

No Operation
NOP
Operation:

No operation is performed.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax
NOP

Instruction Format

110001101

00000111

6-133

OR
Or
OR dst, src
ORB
ORL

Operation:

dst -

dst: R
src: R, 1M, IR, EAM

dst OR src

The source operand is logically ORed with the destination operand and the result is
stored in the destination. A 1 bit is stored whenever either of the corresponding bits
in the two operands is 1; otherwise a 0 bit is stored. The contents of the source are
not affected.

Flags:

Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
P: OR, ORL-unaffected; ORB-set if parity of the result is even;
cleared otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Source
Addressing
Mode

4 _ _ _ _ .... 1 __ I

___

__ _

.l"\l:>l:>IC'IIIUIIC'I L.ClII\:IUCI\:I"

Syntax

Instruction Format

ORRd, Rs
ORB Rbd, Rbs
ORL RRd, RRs

0111101000000010

1M:

OR Rd, 'data

I RRd

10 000101

RRs

o0 1 0 0 0 1 0 1

10 0 0 0

-I

data
ORB Rbd, 'data

ORL RRd, 'data

001 000100

0000

data

01111010

0000 0010

001000101

0000

RRd

data (high)
data (low)

IR:

OR Rd, @RS1
ORB Rbd, @RS1
ORL RRd, @Rs'

I0 0 10 0 0 1 0 IwIRH 0 I .Rd
01111010
001000101

6-134

0000 0010
Rs*O

RRd

Source
Addressing
Mode
EAM:

Assembler Language
Syntax
OR Rd, earn
ORB Rbd, earn

Instruction Format

o 1 10 0 0 1 01 w

e8m

1 Rd

1, 2, or 3 extension words
ORL RRd, earn

01111010

o 11

000101

00000010
e8m

RRd

1, 2, or 3 extension words

Example:

If register RL3 contains %C3 (11000011) and the source operand is the immediate
value % 7B (01111011), executing the instruction
ORB RL3,#%7B
leaves the value % FB (11111011) in RL3.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·135

OTOR

Privileged Instruction
Output, Decrement and Repeat
OTOR dst,
OTORB
OTORL
Operation:

src, r

dst: IR
src: IR

repeat
dst - src
AUTODECREMENT src (by 1 if OTDRB; by 2 if OTDR; by 4 if OTDRL)
r - r-1
until r = 0
This instruction is used for block output of strings of data. The contents of the
memory location addressed by the source register are loaded into the 1/0 port addressed by the destination word register. 1/0 port addresses are 16 bits. The source
register is then decremented by one if OTDRB, by two if OTDR , or by four if
OTDRL, thus moving the pointer to the previous element of the string in memory.
The word register specified by "r" (used as a counter) is then decremented by one.
The address of the 1/0 port in the destination register is unchanged. The entire
operation is repeated until the result of decrementing r is zero. This instruction can
output from 1 to 65,536 data elements. The source, destination, and counter
registers must be distinct, non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set
0: Unaffected
H: Unaffected

Exceptions:

Addressing
Mode
IR:

Privileged Instruction trap

Assembler Language
Syntax
OTDR @Rd,@Rsl, r
OTDRB @Rd,@Rs1, r

Instruction Format
00111011 w Rs*O 1010
Rd * 0 0000

00001

01111010 0000 0010
00111011
00001

6-136

Rs*O 1010
Rd*O 0000

Example:

In linear mode, if register R11 contains %OFFF, register RR22 contains
%00008006, and R13 contains 6, executing the instruction
OTDR @R11, @RR22, R13
outputs the string of words from locations %00008006 to %OOOOAFFC (in descending order of address) to port %OFFF. RR22 contains %OOOOAFFA, and R13 contains O. R11 is not affected. The V flag is set. In compact mode, a word register
must be used instead of RR22.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-137

OTI R
Privileged Instruction
Output, Increment and Repeat
OTIR dst, src, r
OTIRB
OTIRL

Operation:

dst: IR
src: IR

repeat
dst - src
AUTOINCREMENT src (by 1 if OTIRB; by 2 if OTIR; by 4 if OTIRl)

r- r - 1
=0

until r

This instruction is used for block output of strings of data. The contents of the
memory location addressed by'the source register are loaded into the 1/0 port addressed by the destination word register. 110 port addresses are 16 bits. The source
register is then incremented by one if OTIRB, by two if OTIR, or by four if OTlRl,
thus moving the pointer to the next element of the string in memory. The word
register specified by "r" (used as a counter) is then decremented by one. The address of the 1/0 port in the destination register is unchanged. The entire operation is
repeated until the result of decrementing r is zero. This instruction can output from
1 to 65,536 data elements. The source, destination, and counter registers must be
distinct, non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Exceptions:

Addressing
Mode
IR:

Privileged Instruction trap

Assembler Language
Syntax
OTIR @Rd, @Rsl, r
OTIRB @Rd, @Rsl, r

Instruction Format

00111011W Rs*O 0010
00001

OTiRL @Rd, @Rsl, r

6-138

01111010

Rd*O 0000

00000010

001 1 1 01 1

Rs*O 001 0

00001

Rd*O 0000

Example:

In compact mode, the following sequence of instructions can be used to output a
string of bytes to the specified 1/0 port. The pointers to the 1/0 port and the start of
the source string are set, the number of bytes to output is set, and then the output
is accomplished.

LO
LOA

R1, #PORT
R2, SRCBUF

RS, #LENGTH

OTIRB

@R1, @R2, R3

In segmented or linear mode, a longword register must be used instead of R2.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-139

OUT

Privileged Instruction

Output
OUT dst, src
OUTB
OUTl
Operation:

dst -

dst IR, DA
src: R

src

The contents of the source register are loaded into the destination, an output port.
I/O port addresses are 16 bits.

Flags:

No flags affected.

Exceptions:
Destination
Addressing
Mode

Privileged Instruction trap

Assembler Language
Syntax

IR:

OUT @Rd, Rs
OUTS @Rd, Rbs
OUTL @Rd,RRs

DA:

Instruction Format

I0 0 1 1 1 1 1 Iw I

*" 0 I

101111010 1000000101
•••••• tlA ... nl tltI~ I
I nnl
v v I . . . . . . I .. - ~ - I .... -

OUT port, Rs
OUTS port, Rbs

o 0 1 1 1 0 1 IW

0110

port
OUTL port, RRs

0111101000000010

o 011

11011
port

Example:

If register R6 contains % 5252, executing the instruction
OUT

% 1120, R6

outputs the value % 5252 to the port % 1120.

6-140

RRs

0110

OUTD

Privileged Instruction

Output and Decrement
OUTO dst, src, r
OUTOB
OUTOL
Operation:

dst: IR
src: IR

dst - src
AUTODECREMENT src (by 1 if OUTDS; by 2 if OUTD; or by 4 if OUTDL)
r- r - 1
This instruction is used for block output of strings of data. The contents of the
memory location addressed by the source register are loaded into the 1/0 port addressed by the destination word register. 110 port addresses are 16 bits. The source
register is then decremented by one if OUTDS, by two if OUTD, or by four if
OUTDL, thus moving the pointer to the previous element of the string in memory.
The word register specified by "r" (used as a counter) is then decremented by one.
The address of the 1/0 port in the destination register is unchanged. The source,
destination, and counter registers must be distinct, non-overlapping registers.

Flags:

C: Unaffected
Z: Unaffected
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Exceptions:

Privileged Instruction trap

Addressing
Mode

Assembler Language
Syntax

IR:

auTO @Rd, @Rsl, r
aUTOB @Rd, @Rsl, r

Instruction Format
00111011 w Rs*O
00001

aUTDL @Rd, @Rsl, r

1010

Rd*O 1000

01111010

0000 0010

00111011

Rs*O 1010

00001

Example:

Rd*O

1000

In linear mode, if register R2 contains the 110 port address %0030, register RR6
contains % 12005552, the word at memory location % 12005552 contains % 1234,
and register RB contains % 1001, executing the instruction
OUTD @R2, @RR6, RB
outputs the value %1234 to port %0030 and leaves the value %12005550 in RR6,
and % 1000 in RB. Register R2 is not affected. The V flag is cleared. In compact
mode, a word register must be used instead of RR6.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-141

OUTI

Privileged Instruction

Output and Increment
OUTI dst, src, r
OUTIB
OUTll
Operation:

dst: IR
src: IR

dst - src
AUTOINCREMENT src (by 1 if OUTIS; by 2 if OUTI; by 4 if OUTIL)
r- r - 1
This instruction is used for block output of strings of data. The contents of the
memory location addressed by the source register are loaded into the 1/0 port addressed by the destination word register. 1/0 port addresses are 16 bits. The source
register is then incremented by one if OUTIS, by two if OUTI, or by four if OUTIL,
thus moving the pOinter to the next element of the string in memory. The word
register specified by "r" (used as a counter) is then decremented by one. The address of the 110 port in the destination register is unchanged. The source, destination, and counter registers must be distinct, non-overlapping registers.

Flags:

Z:
S:
V:
0:
H:

Exceptions:

Addressing
Mode
IR:

Unaffected
Unaffected
Unaffected
Set if the result of decrementing r is zero; cleared otherwise
Unaffected
Unatlected

Privileged Instruction trap

Assembler language
Syntax
OUTI @Rd. @Rsl, r
OUTIS @Rd. @Rsl, r

Instruction Format
00111011 w Rs * 0 0010
0000]

OUTIL @Rd. @Rsl, r

6-142

01111010

Rd * 0 1000

0000 0010

00111011

Rs*O 0010

0000]

Rd*O

1000

Example:

This instruction can be used in a "loop" of instructions that outputs a string of data,
but an intermediate operation on each element is required. The following sequence
outputs a string of 80 ASCII characters (bytes) with the most significant bit of each
byte set or reset to provide even parity for the entire byte. Sit 7 of each character is
initially O. This example assumes compact mode. In segmented or linear mode, a
longword register must be used instead of R2.
LD
R1, #PORT
//load I/O address
//load start of string
LDA
R2,SRCSTART
!!initialize counter
LD
R3, #80
LOOP:
@R2
TESTS
lItest byte parity
JR
PE, EVEN
@R2, #7
//force even parity
SETS
EVEN:
@R1, @R2, R3
lIoutput next byte
OUTIS
JR
NOV, LOOP
IIrepeat until counter
0
DONE:

Note 1: Word register in compact mode. longword register in segmented or linear modes.

6·143

PCACHE

Privileged Instruction

Purge Cache

PCACHE
Operation:

Purge all cache entries
All cache entries are invalidated. This instruction is executed when a memory location that may have been copied into the cache has been modified by another processor. For example, if a slave processor reads from a peripheral port to a memory
location that may be copied in the cache, the cache must be purged.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax
PCACHE

6-144

Instruction Format

1011110101000010001

POP
Pop

POP dst, src
POPL
Operation:

dst: R, IR, EAM
src: IR

dst - src
AUTOINCREMENT src (by 2 if POP, by 4 if POPL)
The contents of the location addressed by the source register (used as a stack
pointer) are loaded into the destination. The source register is then incremented by
two if POP or by four if POPL, thus removing the top element from the stack by
changing the stack pOinter. Any register except RO in compact mode or RRO in
segmented or linear mode can be used as a stack pointer.
If the destination is a register, the source and destination registers must be distinct
and non-overlapping. Similarly, if the destination is in memory, then the source and
destination operands must not overlap. Otherwise, the result of executing the instruction is undefined.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax
POP Rd, @Rs'

POPL RRd, @Rs'

IR:

POP @Rdl, @Rs'

POPL @Rdl, @Rs'

EAM:

POP earn, @Rs'

Instruction Format

11 0 1 0 1 0 1 1 1 1Rs

11 01 0 1 0 1 0 1 1Rs

'* 0 1

0 1 Rd
RRd

1 0 0 1 0 1 0 1 1 1 1 Rs *' 0 1Rd
1001 01 0101

I Rs*,O IRd *,01

011 01 01 11 1 Rs*,O

I eam

1, 2, or 3 extension words
POPL earn, @Rs'

01 01 0101 1 Rs*,O 1 eam
1, 2, or 3 extension words

Example:

In compact mode, if register R12 (used as a stack pointer) contains % 1000, the
word at location % 1000 contains %0055, and register R3 contains %0022, executing the instruction
POP R3, @R12
leaves the value %0055 in R3 and the value %1002 in R12. In segmented or linear
mode, a longword register must be used instead of R12.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-145

PTLB

Privileged Instruction

PurgeTLB
PTLB
Operation:

Purge all TLB entries
All TLB entries are invalidated. This instruction is executed when system and normal
mode address spaces are merged and the operating system changes from executing one user process to another.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax

PTLB

6-146

Instruction Format

Privileged Instruction

PTLBE
Purge TLB Entry

PTLBEND src
PTLBENI
PTLBESD
PTLBESI

Operation:

src:

IR, EAM

Purge the TLB entry for the effective address of src
If any TLB entry corresponds to the logical address of the source operand, that entry is invalidated. Four versions of the instruction are provided, one for each of the
logical memory address spaces: normal data space (PTLBEND), normal instruction
space (PTLBENI), system data space (PTLBESD), and system instruction space
(PTLBESI).
This instruction is executed when information is changed in the translation tables for
a page in one of the current address spaces. If the page is shared by current address spaces (for example, instruction and data spaces are merged), the page must
be purged in each of the address spaces.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Source
Addressing
Mode
IR:

Assembler Language
Syntax
PTLBEND

PTLBENI

PTLBESD

PTLBESI

@RSl

Instruction Format

01111010

001 1 1001

001000000

Rs*O 0000

01111010

0010 1001

001000000

Rs*O 0000

01111010

0001 1 001

001000000

Rs*O 0000

01111010

0000 1001

001000000

Rs*O 0000

6-147

Source
Addressing
Mode

Assembler Language
Syntax

EAM:

PTLBEND eam

Instruction Format

01111010
011000000

0011 1 001

eam

0000

1, 2, or 3 extension words
PTLBENI eam

01111010
011000000

0010 1001

eam

0000

1, 2, or 3 extension words
PTLBESD eam

01111010
011000000

0001 1001

eam

0000

1, 2, or 3 extension words
PTLBESI eam

01111010
011000000

0000 1 001

eam

0000

1, 2, or 3 extension words

Note 1: Wora register in compact mode, longword register

6-148

segmented or linear modes.

PTLB N

Privileged Instruction
Purge TLB Normal Space
PTLBN
Operation:

Purge Normal Space TLB entries
All TLB entries corresponding to pages in normal data or normal instruction address
spaces are invalidated. This instruction is executed when system and normal mode
address spaces are separated and the user operating system changes from one
process executing in normal mode to another.

Flags:

No flags affected

Exceptions:

Privileged Instruction trap

Assembler Language
Syntax
PTLBN

Instruction Format

1011110101000010111

6-149

PUSH
Push
PUSH dst, src
PUSHL
Operation:

dst: IR
src: R, 1M, IR, EAM

AUTODECREMENT dst (by 2 if PUSH, by 4 if PUSHL)
dst - src
The contents of the destination register (used as a stack pointer) are decremented
by two if PUSH or by four if PUSHL. Then the source operand is loaded into the
location addressed by the updated destination register, thus adding a new element
to the top of the stack by changing the stack pOinter. Any register except RO in
compact mode or RRO in segmented or linear mode can be used as a stack pOinter.
If the source is a register, then the source and destination registers must be distinct
and non-overlapping. Similarly, if the source is in memory, the source and destination operands must not overlap. Otherwise, the result of executing the instruction is
undefined.

Flags:

No flags affected

Exceptions:

None

Source
Addressing
Mode

Assembler Language
Syntax
PUSH @Rd', Rs

PUSHL @Rd 1 , RRs

1M:

PUSH @Rd', Udala

Instruction Format

11 0 01 0011

I Rd",O I

11010100011Rd",01 RRs

o0 1 0 0 1 1 0 1

1 Rd '" 0 11 0 0 1

data
PUSHL @Rd', Udala

001010001

I Rd",O 10000

data (high)
data (low)

IR:

PUSH @Rd', @RSl

PUSHL @Rdl, @Rs'

6-150

I I

1001010001

I Rd",O I Rs",O I

00 0 10011

Rd '" 0

Rs '" 0

Source
Addressing
Mode

Assembler Language
Syntax

EAM:

PUSH @Rdl, eam

Instruction Format

0110100111 Rd*O 1 earn
1, 2, or 3 extension words

PUSHL @Rdl, eam

f 010001 1 Rd*O Team
1,2, or 3 extension words

Example:

In compact mode, if register R12 (a stack pointer) contains % 1002, the word at
location % 1000 contains % 0055, and register R3 contains % 0022, executing the
instruction
PUSH @R12, R3
leaves the value %0022 in location % 1000 and the value % 1000 in R12. In
segmented or linear mode, a longword register must be used instead of R12.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6·151
---

---------_._------

RES
Reset Bit
RES dst, src
RESB
RESL

Operation:

dst -

dst:
src:
or
dst:
src:

R, IR, EAM

1M
R
R

This instruction clears the specified bit within the destination operand to 0 without
affecting any other bits in the destination. The bit number (the source) can be
specified either as an immediate value (static), or as a word register that contains
the value (dynamic). In the dynamic case, the destination operand must be in a
register, and the source operand must be in a word register.
The bit number is a value from 0 to 7 for RESB, 0 to 15 for RES, or 0 to 31 for
RESL, with 0 indicating the least-significant bit. Only the lower three bits of the
source operand are used to specify the bit number for RESB, only the lower four
bits are used for RES, and only the lower five bits are used for RESL.

Flags:

No flags affected

Exceptions:

None

Reset Bit Static
Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

RES Rd, #b
RESB Rbd, #b
RESL RRd, #b

0111101000000010
1 011 0 0 0 1 1b

IR:

RES @Rdl, #b
RESB @Rd 1 , #b
RESL @Rd 1 , #b

EAM:

RRd 1

RES eam, #b
RESB eam, #b

0111101000000010
00110001jb Rd*ol

o 1 11 0 0 0 11 w1

eam 1

1,2, or 3 extension words
RESL eam, #b

01111010
01110001-jb

00000010
eam

1,2, or 3 extension words

6-152

Reset Bit Dynamic
Assembler Language
Syntax

RES Rd, Rs
RESB Rbd, Rs

Instruction Format

001100011 w 0000
00001

RESL RRd, Rs

01111010
001100011

0000

Example:

RRd

0000 0000

0000 0010
0000

0000 0000

If register RL3 contains % B2 (10110010), executing the instruction
RESB

RL3, #1

leaves the value % BO (10110000) in RL3.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·153

RESFLG

Reset Flag

RESFLG flag
Operation:

FLAGS < 7:4 > -

flag: C, Z, S, P, V
FLAGS<7:4> AND NOT instruction<7:4>

Any combination of the C, Z, S, P or V flags can be cleared to O. If the bit in the instruction corresponding to a flag is 1, the flag is cleared; if the bit is 0, the flag is
unchanged. All other bits in the FLAGS register are unaffected. Note that the P and
V flags are represented by the same bit. There can be one, two, three, or four
operands in the assembly language statement, in any order.

Flags:

Cleared if specified, unaffected otherwise

Z: Cleared if specified, unaffected otherwise
S: Cleared if specified, unaffected otherwise
PN: Cleared if specified, unaffected otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Assembler Language
Syntax
RESFLG flags

Example:

Instruction Format

11 0 0 0 1 1 0 1

Ie Z sPIVI 0 0 1 1 1

If the C, S, and V flags are set (1) and the Z flag is clear (0), executing the statement
RESFLG C, V
leaves the S flag set (1), and the C, Z, and V flags clear (0).

6-154

RET
Return
RET cc

Operation:

Compact
if cc is satisfied then
PC-@SP
SP- SP + 2

Segmented or linear
if cc is satisfied then
PC- @SP
SP- SP + 4

This instruction is used to return at the end of a procedure called by executing
either a CALL or CALR instruction. If the condition specified by "cc" is satisfied by
the flags in the FCW, then the contents of the top of the processor Stack Pointer
are popped into the Program Counter (PC), thus returning control to the caller. See
Section 6.3 for a list of condition codes. The Stack Pointer used is R15 in compact
mode, or RR14 in segmented or linear mode. If the condition is not satisfied, then
the instruction following the RET instruction is executed. If no condition is specified,
the return is taken regardless of the flag settings.

Flags:

No flags affected

Exceptions:

None

Assembler Language
Syntax
RETcc

Example:

Instruction Format

1101011110100001

In compact mode, if the Program Counter contains %2550, the Stack Pointer (R15)
contains % 3000, location % 3000 contains % 1004, and the Z flag is clear, executing the instruction
RET NZ

leaves the value %3002 in the Stack Pointer, and the Program Counter contains % 1004 (the address of the next instruction to be executed).

6-155

Rotate Left
RL dst, src
RLB
RLL
Operation:

dst: R
src: 1M

for i - 1 to src do
C- dst
for j - msb down to 1 do
dst - dst
dst -C

Longword:

Word:

Byte:

~~31----r.F----..;,0~

0-Y____~~'I-:

___. .!-l
.

~1_5------,0IJ

0~.:.--7----;°IJ

The contents of the destination operand are rotated left one or two bit positions as
specified by the source operand. During rotation, the most-significant bit (msb) of
the destination operand is moved to the bit 0 position and also replaces the C flag.
If the source operand is omitted from the assembler language statement, the default
value is one.

Flags:

Z:
5:
V:
D:
H:

Exceptions:
Destination
Addressing
Mode

Set if the last bit rotated from the most-significant bit position was 1; cleared
otherwise
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise
Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
Unaffected
Unaffected

None

Assembler Language
Syntax

Instruction Format 1

RL Rd, In
RLB Rbd, In
RLL RRd, In

101111010 100000010

l10 11100111

6-156

RRd 1001510

Example:

If register RH5 contains % 88 (10001000), executing the instruction
RLB

RH5

leaves the value % 11 (00010001) in RH5 and sets the C flag to 1.
Note 1: S = 0 for rotation by 1 bit; S = 1 for rotation by 2 bits.

6-157

RLC
Rotate Left through Carry
RLC dst, src
RLCB
RLCL
Operation:

dst: R
src: 1M

for i - 1 to src do
temp- C
C- dst
for j - msb down to 1 do
dst - dst
dst< 0 > - temp

~c3~1________~~______,0~

Longword:

LEJ--I_ _~:;'~_........I-l

Word:

L{iH15

Byte:

LG-1r----.......;,°IJ

°IJ

The contents of the destination operand concatenated with the C flag are rotated
left one or two bit positions as specified by the source operand. During rotation, the
most-significant bit (msb) of the destination operand replaces the C flag and the
previous value of the C flag is moved to the bit 0 position of the destination.
If the source operand is omitted from the assembler language statement, the default
value is one.

Flags:

C: Set if the last bit rotated from the most-significant bit position was 1; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
5: Set if the most-significant bit of the result is set; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
D: Unaffected
H: Unaffected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format1

RLC Rd, Ifn
RLCB Rbd, Ifn
RLCL RRd, Ifn
011110101000000101

1011100111

6-158

RRd

110lsl01

Example:

If the C flag is clear (0) and register RO contains %800F (1000000000001111), executing the instruction
RLC

RO,I2

leaves the value % 003D (0000000000111101) in RO and clears the C flag,
Note 1: S

= 0 for rotation by 1 bit; S = 1 for rotation by 2 bits

6-159

RLDB
Rotate Left Digit
RLDB link, dst

Operation:

link: R
dst: R

temp<3:0> -link<3:0>
Iink<3:0> - dst<7:4>
dst< 7:4 > - dst < 3:0 >
dst<3:0> - temp<3:0>

link

dst

The low digit of the lihk byte register is concatenated to the destination byte
register. The resulting three-digit quantity is rotated to the left by one BCD digit (four
bits). The lower digit of the destination is moved to the upper digit of the destination;
the upper digit of the destination is moved to the lower digit of the link, and the
lower digit of the link is moved to the lower digit of the destination. The upper digit
of the link is unaffected.
In multiple-digit BCD arithmetic, this instruction can be used to shift a string of BCD
digits to the left, thus multiplying it by a power of ten. The link serves to transfer
digits between successive bytes of the string. This is analogous to the use of the C
flag in multiple precision shifting using the RLC instruction.
The destination and link registers must be distinct.

Flags:

Unaffected
Set if the link is zero after the operation; cleared otherwise
Unaffected
Unaffected
Unaffected
H: Unaffected

Z:
S:
V:
D:
Exceptions:
Destination
Addressing
Mode

6-160

None

Assembler Language
Syntax
RLDB Rbi, Rbd

Instruction Format

1101111110 1 Rbd

Rbi

Example:

If location 100 contains the BCD digits 0,1 (00000001), location 101 contains 2,3
(00100011), and location 102 contains 4,5 (01000101)
100

101

102

executing the sequence of instructions in compact mode
LD

R3,'3

LDA
CLRB

R2,102
RH1

"set loop counter for 3 bytes
"(6 digits)
"set pointer to low-order digits
"zero-fill low-order digit

LOOP:
LDB
RL1,@R2
RLDB
RH1 ,RL1
LDB
@R2,RL1
DEC
R2
DJNZ
R3, LOOP
leaves the digits 1,2 (00010010) in location 100, the
101, and the digits 5,0 (01010000) in location 102.
100

101

102

"get next two digits
"shift digits left one position
"replace shifted digits
"advance pointer
"repeat until counter is zero
digits 3,4 (00110100) in location

In segmented or linear mode, a longword register must be used instead of R2.

6-161

Rotate Right
RR dst, src
RRB
RRL

Operation:

for i -

dst: R
src: 1M

1 to src do

C- dst
for j - 1 to msb do
dst - dst
dst - C

L ;1 =~~-f':;r-----,r0
o~

Longword:

Word:

Byte:

Lil~5------.;.,0;1.0

Lr--(-------'1°;l0

The contents of the destination operand are rotated right one or two bit positions as
specified by the source operand. During rotation, the least-significant bit of the
destination operand is moved to the most-significant bit (msb) and also replaces the
C flag.
If the source operand is omitted from the assembly language statement, the default
value is one.

Flags:

Z:
5:
V:
D:
H:

Exceptions:
Destination
Addressing
Mode

Set if the last bit rotated from the least-significant bit position was 1; cleared
otherwise
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise
Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
Unaffected
Unaffected

None

Assembler Language
Syntax

Instruction Format 1

RR Rd, In
RRB Rbd, In
RRL RRd, In

01111010
101110011

6-162

00000010
RRd 1011sl0

Example:

If register RL6 contains %31 (00110001). executing the instruction
RRB RL6
leaves the value % 98 (10011000) in RL6 and sets the C flag to 1.
Note t: S = 0 for rotation by 1 bit;

1 for rotation by 2 bits.

6-163

RRC
Rotate Right through Carry
RRC dst, src
RRCB
RRCL

Operation:

dst: R
src: 1M

for i - 1 to src do
temp- C
C - dskO>
for j - 1 to msb do
dskj-1> - dst
dst < msb > - temp

Longword:

Word:

~1,;;;....-5-----=,o~0J

31
r--I

F--------',o~.c
~

----f.~'f_:

[r--(-----,o~0J

Byte:

The contents of the destination operand concatenated with the C flag are rotated
right one or two bit positions as specified by the source operand. During rotation,
the least-significant bit of the destination operand replaces the C flag and the
previous value of the C flag is moved to the most-significant bit (msb) position of the
destination.
If the source operand is omitted from the assembly language statement, the default
value is one.

Flags:

C: Set if the last bit rotated from the least-significant bit position was 1; cleared
otherwise

Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise

0: Unaffected
H: Unaffected

Exceptions:
Destination
Addressing
Mode

None

Assembler Language
Syntax

Instruction Format1

RRC Rd, {In
RRCB Rbd, {In
RRCL RRd, {In

01111010
101110011

6-164

00000010

RRd

1111sl0

Example:

If the C flag is clear (0) and the register RO contains %OODD (0000000011011101),
executing the instruction
RRC

RO,#2

leaves the value % 8037 (1000000000110111) in RO and clears the C flag.
Note 1: S

0 for rotation by 1 bit; S

1 for rotation by 2 bits

6-165

RRDB
Rotate Right Digit
RRDB link, dst

Operation:

temp <3:0>
link<3:0> dst<3:0> dst<7:4> -

link: R
dst: R

link<3:0>
dst<3:0>
dst<7:4>
temp<3:0>

link:

dst:

The low digit of the link byte register is concatenated to the destination byte
register. The resulting three-digit quantity is rotated to the right by one BCD digit
(four bits). The lower digit of the destination is moved to the lower digit of the link,
the upper digit of the destination is moved to the lower digit of the destination, and
the lower digit of the link is moved to the upper digit of the destination. The upper
digit of the link is unaffected.
In multiple-digit BCD arithmetic, this instruction can be used to shift a string of BCD
digits to the right, thus dividing it by a power of ten. The link serves to transfer digits
between successive bytes of the string. This is analogous to the use of the C flag in
multiple precision shifting using the RRC instruction.
The destination and link registers must be distinct.

Flags:

Unaffected
Set if the link is zero after the operation; cleared otherwise
Unaffected
Unaffected
Unaffected
H: Unaffected

Z:
S:
V:
D:
Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

RRDB Rbi, Rbd

6-166

Instruction Format

11 0 11 1110 0 1 Rbd

Rbi

Example:

If location 100 contains the BCD digits 1,2 (00010010), location 101 contains 3,4
(00110100), and location 102 contains 5,6 (01010110)
100

101

102

executing the sequence of instructions in compact mode
LD
R3,'3
IIset loop counter for 3 bytes (6
digits)
LD
R2,'100
IIset pointer to high-order digits
CLRB
RH1
IIzero-fill high-order digit
LOOP:
LDB
RL 1,@R2
IIget next two digits
RRDB
RH1,RL1
IIshift digits right one position
LDB
@R2,RL1
IIreplace shifted digits
INC
R2
lIadvance pointer
DJNZ
R3,LOOP
IIrepeat until counter is zero
leaves the digits 0,1 (00000001) in location 100, the digits 2,3 (00100011) in location
101, and the digits 4,5 (01000101) in location 102. RH 1 contains 6, the remainder
from dividing the string by 10.
100

101

GEl

102

In segmented or linear mode, a longword register must be used instead of R2.

6-167

SBC
Subtract with Carry
SBC dst, src
SBCB
SBCL
Operation:

dst -

dst: R
src: R

dst - src - C

The source operand, along with the setting of the C flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the
source are not affected. Subtraction is performed by adding the twos complement
of the source operand to the destination operand. In multiple precision arithmetic,
this instruction permits the "borrow" from the subtraction of low-order operands to
be borrowed from the subtraction of high-order operands.

C: Cleared if there is a carry from the most-significant bit of the result; set

Flags:

otherwise, indicating a borrow

Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs
and the sign of the result is the same as the sign of the source; cleared
otherwise
D: SBC, SBCL-unaffected; SBCB-set
H: SBC, SBCL-unaffected; 8BCB-cleared if there is a carry from the mostsignificant bit of the low-order four bits of the result; set otherwise, indicating
a borrow
Exceptions:

Source
Addressing
Mode

None

Assembler Language
Syntax
SBC Rd, Rs
SBCB Rbd, Rbs
SBCL RRd, RRs

Example:

Instruction Format

01111010

00000010

1 011 1 0 1 1 1

RRs 1 RRd

Ouadword subtraction can be done with the following instruction sequence, assuming ROO contains one operand and R04 contains the other operand:
SUBL RR2,RR6
IIsubtract low-order longwords
8BCL RRO,RR4
IIsubtract borrow and high-ord~r longwords
If RRO contains %00000038, RR2 contains %00004000, RR4 contains %OOOOOOOA
and RR6 contains % FFFFFOOO, executing the two instructions above leaves the
value %00000020 in RRO and %00005000 in RR2.

6-168

SC
System Call
SC src

Operation:

src: 1M

SP-SP - 6
@SP-PS
SP- SP - 2
@SP - instruction
PS - System Call PS
This instruction causes a System Call trap for controlled access to operating system
software. The instruction word and the contents of the Program Status registers are
pushed onto the system stack. The source operand, which is contained in the second byte of the instruction, identifies the particular service requested from the
operating system. The source operand must be in the range from 0 to 255.

Flags:

Flags loaded from Program Status Area

Exceptions:

System Call trap

Source
Addressing
Mode

Assembler Language
Syntax

1M:

SC fin

Instruction Format

101111111

6-169

SDA

Shift Dynamic Arithmetic
SDA dst, src
SDAB
SDAL

Operation:

dst: R
src: R

if src <:!: 0
/I left shift
for i - 1 to src do
C-dst
for j - msb down to 1 do
dst - dst
dst - 0
else for i - 1 to -src do
. /I right shift
C-dst
for j - 1 to msb do
dst - dst
Right

Left
7

Byte:

EH
15

Word:

EJ-I

c!J1

r£]

EH
31

Longword:

1"-0

c!J1
c!J1
31

r£]

H!l

The destination operand is shifted left or right arithmetically the number of bit positions specified by the source operand, a word register. For right shifts, the mostsignificant bit is replicated, and the C flag is loaded from the least-significant bit of
the destination. For left shifts, the least-significant bit is filled with 0 and the C flag
is loaded from the most-significant bit of the destination. A shift of zero positions
does not affect the destination; however, the flags are set according to the destination value.
The source operand must be in the range from -8 to 8 for SDAB, from -16 to 16 for
SOA or from -32 to 32 for SOAL. If its value is outside the specified range, the
operation is undefined. The source operand is represented as a 16-bit twos complement value. Positive values specify a left shift, while negative values specify a right
shift.

Flags:

c:
Z:
S:
V:
0:
H:

Exceptions:

6-170

Set if the last bit shifted from the destination was 1; cleared if the last bit
shifted from the destination was 0 or zero shift was specified
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during shifting; cleared otherwise
Unaffected
Unaffected

Integer Overflow trap

Destination
Addressing
Mode

Assembler Language
Syntax

SDA Rd. Rs

Instruction Format

101110011
00001

SDAB Rbd. Rs

101110010
00001

SDAL RRd. Rs

101110011
00001

Example:

11011

00000000
Rbd 11 011
00000000
RRd 11111
00000000

If register R5 contains%C705 (11000111 Q00001 01) and register R1 contains - 2
(% FFFE or 1111111111111110), executing the instruction
SDA

R5,R1

performs an arithmetic right shift of two bit pOSitions, leaves the value % F1 C1
(1111000111000001) in R5, and clears the C flag.

6·171

SOL
Shift Dynamic Logical
SOL dst, src
SOLB
SOLL

Operation:

dst: R
src: R

if src;:: 0
/I left shift
for i - 1 to src do
C-dst
for j - msb down to 1 do
dst - dst
dst <0> - 0
/I right shift
else for i - 1 to -src do
C -dst
for j - 1 to msb do
dst - dst
dst - 0
Left
7

Syte:

E:H
0--1

I~o

;;

0-1
0

E:H
31

Longword:

1- 0

Word:

Right
0

0_1

1--0 0-1

I-EJ

~El

The destination operand is shifted left or right logically the number of bit pOSitions
specified by the source operand, a word register. For right shifts, the mostsignificant bit is filled with 0 and the C flag is loaded from the least-significant bit of
the destination. For left shifts, the least-significant bit is filled with 0 and the C flag
is loaded from the most-significant bit of the destination. A shift of zero pOSitions
does not affect the destination; however, the flags are set according to the destination value.
The source operand must be in the range from -8 to 8 for SOLS, from -16 to 16 for
SOL or from -32 to 32 for SOLL.lf its value is outside the specified range, the
operation is undefined. The source operand is represented as a 16-bit twos complement value. Positive values specify a left shift, while negative values specify a right
shift.

Flags:

c:
Z:
S:
P:
0:
H:

Exceptions:

6-172

Set if the last bit shifted from the destination was 1; cleared if the last bit
shifted from the destination was 0 or zero shift was specified
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise
SOL, SOLL-unaffected; SOLS-set if parity of the result is even; cleared
otherwise
Unaffected
Unaffected

None

Destination
Addressing
Mode

Assembler Language
Syntax
SOL Rd, Rs

Instruction Format

10111 0011
00001

10011

00000000

SOLS Rbd, Rs

101110010
00001

Rbd 10011
00000000

SOLL RRd, Rs

Example:

I011 1

1 011 1 001 1

RRd

o 0 0 01

00 0 0 0 0 0 0

If register AL5 contains % 83 (10110011) and register A1 contains 4
(0000000000000100), executing the instruction
SDL8 AL5,A1
performs a logical left shift of four bit positions, leaves the value %30 (00110000) in
AL5, and sets the C flag.

6·173

SET
Set Bit
SET dst, src
SETB
SETL

Operation:

dst -

dst:
src:
or
dst:
src:

R, IR, EAM
1M
R
R

This instruction sets the specified bit within the destination operand to 1 without
affecting any other bits in the destination. The bit number (the source) can be
specified either as an immediate value (static), or as a word register that contains
the value (dynamic). In the dynamic case, the destination operand must be in a
register, and the source operand must be in a word register.
The bit number is a value from 0 to 7 for SETB, 0 to 15 for SET, or 0 to 31 for SETL
with 0 indicating the least-significant bit. Only the lower three bits of the source
operand are used to specify the bit number for SETB, only the lower four bits are
used for SET, and only the lower five bits are used for SETL.

Flags:

No flags affected

Exceptions:

None

Set Bit Static
Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

SET Rd, #b
SETS Rbd, #b
SETL RRd, #b

0111101000000010
10110010lb

IR:

SET @Rd1, #b
SETS @Rd1 , #b
SETL @Rd1, #b

0111101000000010
0011 001 Olb

EAM:

RRd

SET earn, #b
SETS eam, #b

o 1 11 0 0 1 01 w1

earn 1

1, 2, or 3 extension words

SETL eam, #b

01111010
01110010lb

0000 0010
earn

1, 2, or 3 extension words

6-174

Set Bit Dynamic
Addressing
Mode

Assembler Language
Syntax

SET Rd, Rs
SETB Rbd, Rs

Instruction Format

00110010Iw 0000
0000 I

SETL RRd, Rs

Example:

00000000

01111010 0000 0010
Rs

001100101

0000

00001 RRd

0000 0000

If register AL3 contains %B2 (10110010) and register A2 contains the value 6, executing the instruction
SETB

AL3, A2

leaves the value % F2 (11110010) in AL3.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-175

SETFLG
Set Flag
SETFLG flag

Operation:

FLAGS < 7:4 > -

Flag: C, Z, S, P, V
FLAGS<7:4> OR instruction<7:4>

Any combination of the C, Z, S, P or V flags can be set to 1. If the bit in the instruction corresponding to a flag is 1, the flag is set; if the bit is 0, the flag is unchanged.
All other bits in the Flags register are unaffected. Note that the P and V flags are
represented by the same bit. There can be one, two, three, or four operands in the
assembly language statement, in any order.

Flags:

Set if specified; unaffected otherwise

Z: Set if specified; unaffected otherwise
S: Set if specified; unaffected otherwise
PN: Set if specified; unaffected otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Assembler Language
Syntax
SETFLG flags

Example:

6-176

Instruction Format

110001101

IczsPlV1 0001

If the C, Z, and S flags are all clear (0), and the P flag is set (1), executing the
instruction
SETFLG C
leaves the C and P flags set (1), and the Z and S flags clear (0).

SLA
Shift Left Arithmetic
SLA dst, src
SLAB
SLAL
Operation:

for i -

dst: R
src: 1M

1 to src do

C- dst
for j - msb down to 1 do
dst - dst
dst <0> - 0
7

Byte:

Word:

Longword:

El-1....._____......l-o
~

EJ-IL.________. . .I--o
EJ--I...__---,:,.". ;__---'1--

The destination operand is shifted left arithmetically the number of bit positions
specified by the source operand. The least-significant bit of the destination is filled
with 0 and the C flag is loaded from the most-significant bit of the destination. A
shift of zero position does not affect the destination; however, the flags are set according to the destination value. This operation differs from Shift Left Logical in the
setting of the P/v flag and the detection of an Integer Overflow trap.
The source operand must be in the range from 0 to 8 for SLAB, from 0 to 16 for
SLA, or from 0 to 32 for SLAL. If its value is outside the specified range, the operation is undefined. The source operand is encoded as an 8- or 16-bit twos complement number contained in the second word of the instruction. If the source operand
is omitted from the assembly language statement, the default value is 1.

Flags:

c:
Z:
S:
V:
D:
H:

Exceptions:

Set if the last bit shifted from the destination was 1; cleared if the last bit shifted
from the destination was 0 or zero shift was specified
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during shifting; cleared otherwise
Unaffected
Unaffected

Integer Overflow trap

6-177

Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

SLA Rd, #b

SLAB Rbd, #b

Rbd

o
SLAL RRd, #b

11001
b

10[110011

RRd 111 01

Example:

If longword register RR2 contains % 1234ABCD, executing the instruction

SLAL RR2,#8
leaves the value % 34ABCDOO in RR2 and clears the C flag,

6-178

SLL
Shift Left Logical
SLL dst, src
SLLB
SLLL

Operation:

for i -

dst: R
src: 1M

1 to src do

C- dst
for j - msb down to 1 do
dst - dst
dst <0> - 0
7

Byte:

E:H
Longword: EH

Word:

1--

The destination operand is shifted left logically the number of bit positions specified
by the source operand. The least-significant bit of the destination is filled with 0 and
the C flag is loaded from the most-significant bit of the destination. A shift of zero
position does not affect the destination; however, the flags are set according to the
destination value. This operation differs from Shift Left Arithmetic in the setting of
the PIV flag and the detection of an Integer Overflow trap.
The source operand must be in the range from 0 to 8 for SLLB, from 0 to 16 for
SLL, or from 0 to 32 for SLLL. If its value is outside the specified range, operation is
undefined. The source operand is encoded as an 8- or 16-bit twos complement
number contained in the second word of the instruction. If the source operand is
omitted from the assembly language statement, the default value is one.

Flags:

c:
Z:
S:
P:

0:
H:

Exceptions:

Set if the last bit shifted from the destination was 1; cleared if the last bit
shifted from the destination was 0 or zero shift was specified
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise
SLL, SLLL-unaffected; SLLB-set if parity of the result is even;
cleared otherwise
Unaffected
Unaffected

None

6-179

Destination
Addressing
Mode

Assembler Language
Syntax

SLL Rd, #b

Instruction Format

Rd 10001

101110011

b
SLLB Rbd, ffb

1011 1 0010

Rbdloo01

0
SLLL RRd, #b

RRd 10101

101110011

Example:

If register R3 contains %4321 (0100001100100001), executing the instruction
SLL R3,'1
leaves the value % 8642 (1000011001000010) in R3 and clears the C flag.

6·180

SRA
Shift Right Arithmetic
SRA dst, src
SRAB
SRAL
Operation:

dst: R
src: 1M

for i - 1 to src do
C - dst
for j - 1 to msb do
dst - dst
7

Byte:
15

Word:

c!J,..I-1_ _ _---II~EJ
~

Longword:

The destination operand is shifted right arithmetically the number of bit positions
specified by the source operand. The most-significant bit of the destination is
replicated, and the C flag is loaded from the least-significant bit of the destination.
The source operand must be in the range from 1 to 8 for SRAB, from 1 to 16 for
SRA, or from 1 to 32 for SRAL. If its value is outside the specified range, the operation is undefined. The negative of the source operand is encoded as an 8- or 16-bit
twos complement number contained in the second word of the instruction. If the
source operand is omitted from the assembly language statement, the default value
is one.

Flags:

Set if the last bit shifted from the destination was 1; cleared otherwise
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Cleared
Unaffected
H: Unaffected

Z:
S:
V:
D:
Exceptions:

None

6-181

Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

SRA Rd, #b

SRAB Rbd, #b

101110010

Rbd

o
SRAL RRd, #b

11001

-b

1 0 /1 1 0 0 1 1

RRd

/1 1 0 1

-b

Example:

If register RH6 contains %38 (00111011), executing the instruction
SRAB

RH6,#2

leaves the value % OE (00001110) in RH6 and sets the C flag.

6·182

SRL
Shift Right Logical
dst R

SRL dst, src
SRLB
SRLL
Operation:

src: 1M

for i - 1 to src do
C - dskO>
for j - 1 to msb do
dst - dst
dst - 0
7

o __I~

Byte:
~

Word: o_l~

___________....0

Longword:

____________~~

1 ----:f~.r------'....

0 _....

The destination operand is shifted right logically the number of bit positions
specified by the source operand. The most-significant bit of the destination is filled
with 0 and the C flag is loaded from the least-significant bit of the destination.
The source operand must be in the range from 1 to 8 for SRLB, from 1 to 16 for
SRL, or from 1 to 32 for SRL. If its value is outside the specified range, the operation is undefined. The negative of the source operand is encoded as an 8- or 16-bit
twos complement number contained in the second word of the instruction. If the
source operand is omitted from the assembly language statement, the default value
is one.

Flags:

Set if the last bit shifted from the destination was 1; cleared otherwise

Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is 1; cleared otherwise
P: SRL, SRLL-unaffected; SRLB-set if parity of the result is even;
cleared otherwise

0: Unaffected
H: Unaffected
Exceptions:

None

6-183

Destination
Addressing
Mode

Assembler Language
Syntax

SRL Rd, #b

Instruction Format

11 10 0 1 1

I0 0 0 1

-b
SRLB Rbd, #b

10 11 1 0 0 1 0

Rbd

o
SRLL RRd, #b

10 0 0 1
-b

10 11 10 0 11

RRd

10 1

-b

Example:

If register RO contains % 1111 (0001000100010001), executing the instruction
SRL

RO,#6

leaves the value %0044 (0000000001000100) in RO and clears the C flag.

6-184

SUB
Subtract
SUB dst, src
SUBB
SUBL

Operation:

dst -

dst: A
src: A, 1M, lA, EAM

dst - src

The source operand is subtracted from the destination operand and the result is
stored in the destination. The contents of the source are not affected. Subtraction is
performed by adding the twos complement of the source operand to the destination
operand.

Flags:

Z:
S:
V:
0:
H:

Exceptions:
Source
Addressing
Mode

Cleared if there is a carry from the most-significant bit; set otherwise, indicating
a borrow
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Set if arithmetic overflow occurs, that is, if the operands were of opposite signs
and the sign of the result is the same as the sign of the source;
cleared otherwise
SUB, SUBL-unaffected; SUBB-set
SUB, SUBL-unaffected; SUBB-cleared if there is a carry from the mostsignificant bit of the low-order four bits of the result; set otherwise, indicating a
borrow

Integer Overflow trap

Assembler Language
Syntax
SUB Rd, Rs
SUBB Rbd, Rbs
SUBL RRd, RRs

1M:

Instruction Format

SUB Rd, #data

11 0 0 1 00 1 0

RRs

RRd

001000011100001

data
SUBB Rbd, #data

SUBL RRd, #data

o 0 1 0 000 1 0

0 0 0 0 1 Rbd

data

001010010100001 RRd
data (high)
data (low)

IR:

SUB Rd, @RS1
SUBB Rbd, @RS1
SUBL RRd, @RS1

100100001lwi Rs;cO

100 01 0010

Rs;cO

I
I

Rd
RRd

6-185

Source
Addressing
Mode
EAM:

Assembler Language
Syntax
SUB Rd, earn
SUBB Rbd, earn

Instruction Format

o1 10 0 0 0 11 w1

eam

1,2, or 3 extension words
SUBL RRd, earn

01\ 010010 \ eam \ RRd

1, 2, or 3 extension words

Example:

If register RO contains %0344, executing the instruction
SUB

RO,ft%AA

leaves the value %029A in RO.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-186

Tee

Test Condition Code
TCC cc, dst
TCCB
TCCL

Operation:

dst: R

if cc is satisfied then
dst -1
This instruction is used to create a Boolean data value based on the flags set by a
previous operation. The flags in the FeW are tested to see if the specified condition
is satisfied. If the condition is satisfied, then the least-significant bit of the destination is set. If the condition is not satisfied, bit 0 of the destination is unaffected. All
other bits in the destination are unaffected by this instruction.

Flags:

No flags affected

Exceptions:

None

Destination
Addressing
Mode

Assembler Language
Syntax

Instruction Format

TCC CC, Rd
TCCB CC, Rbd
TCCl,

CC,

RRd

01111010
1 011 0 1 1 1 1

Example:

00000010
RRd

If register R1 contains 0, and the Z flag is set, executing the instruction

Tee EQ,R1
leaves the value 1 in R1.

6-187

TEST
Test
TEST dst
TESTB
TESTL

Operation:

dst: R, IR, EAM

dst OR 0
The destination operand is tested (logically ORed with zero), and the Z, Sand P
flags are set according to the result. This operation differs from Test Arithmetic in
the setting of the C and PN flags. The contents of the destination are not affected.

Flags:

C:
Z:
S:
P:

Exceptions:

None

Unaffected
Set if the result is zero; cleared otherwise
Set if the most-significant bit of the result is set; cleared otherwise
TEST, TESTL-unaffected; TESTB-set if parity of the result is
even; cleared otherwise
D: Unaffected
H: Unaffected

Destination
Addressing
Mode

IR:

Assembler Language
Syntax

Instruction Format

TEST Rd
TESTB Rbd

1101001101wl Rd 101001

TESTL RRd

11 010 1 1 1 00 1 RRd 11 0 0 01

TEST@Rd1
TESTB @Rd1
TESTL@Rd1

EAM:

TEST earn
TESTB earn

1001001101wl Rd*ol01001
1001 0 1 1 1 0 0 1Rd * 0 11 00 0 1
0110011 olwl e8m 10100
1,2, or 3 extension words

TESTL earn

o 1 1 0 1 1 10 0 188m 11 0 00
1, 2, or 3 extension words

Example:

If register R5 contains % FFFF (1111111111111111), executing the instruction
TEST R5
sets the S flag, clears the Z flag, and leaves the other flags unaffected.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-188

TESTA
Test Arithmetic
TI;STA dst
TESTAB
TESTAL
Operation:

dst: R, IR, EAM

dst - 0
Zero is compared to (subtracted from) the destination operand and the flags are set
according to the result. The contents of the destination are not affected. This operation differs from Test in the setting of the C and P/v flags. Test Arithmetic must be
used when an arithmetic condition (such as "greater than") is required.

Flags:

Z:
S:
V:
D:
H:

Exceptions:
Destination
Addressing
Mode

IR:

Cleared
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Cleared
Unaffected
Unaffected

None

Assembler Language
Syntax
TESTA Rd
TESTAB Rbd

11 0 10 0 1 1 01 w 1 Rd

TESTAL RRd

11 01 0 1 1 1 0 0 1 RRd 11 1 0 0 1

TESTA @Rd1
TESTAB @Rd 1

10 01 0 0 1 1 01 w1 Rd '" 0 11 1 0 0 1

TESTAL @Rd1

EAM:

Instruction Format

TESTA eam
TESTAB eam

11 1 0 0 1

10 01 0 1 1 1 0 0 1 Rd '" 0 11 1 0 0 1

o 1100 1 1 0lwl

eam

11 1 00

1, 2, or 3 extension words

TESTAL eam

o 11

0 1 1 1 0 0 1 eam 11 1 0 0

1,2, or 3 extension words

Example:

If register RO contains -1 (%FFFF) executing the ~o instructions
TESTARO
'
JR LE, NEG_OR-2ERO
transfers control to the instruction at label NEG_OR-2ERO. Note that using TEST instead
of TESTA would require two JR instructions for equivalent effect because conditions involving
the V flag cannot be used following TEST
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-189·

TRAP
Conditional Trap
TRAP cc, src

Operation:

src: 1M

if cc is satisfied then
SP- SP-6
@ SP- PS
SP- SP-2
@ SP instruction
PS - Conditional Trap PS
If the condition specified by "cc" is satisfied by the flags in the FCW, this instruction causes a Conditional trap. The instruction and the contents of the Program
Status registers are pushed onto the system stack. The source operand, which is
contained in bits 7 to 4 of the instruction, identifies the particular cause of the trap.
The source operand must be in the range from 0 to 15. This instruction is used for
the generation of exceptions detected by software, such as an overflow on decimal
arithmetic.

Flags:

Flags loaded from Program Status Area

Exceptions:

Conditional trap

Source
Addressing
Mode
1M:

6-190

Assembler Language
Syntax
TRAP ee, #n

Instruction Format

101111110

TROB
Translate and Decrement
TRDB dst, src, r

Operation:

dst: IR
src: IR

dst - src[dstJ
AUTODECREMENT dst by 1
r- r - 1
This instruction is used to translate a string of bytes from one code to another. The
contents of the location addressed by the destination register (the "target byte") are
used as an unsigned index into a translation table whose base address is contained
in the source register. An effective address is calculated by adding the zeroextended target byte to the translation table base address using the rules for address arithmetic in the current mode of address representation: compact,
segmented, or linear. The effective address is the location of the translated value
used to replace the original contents of the target byte.
The destination register is then decremented by one, thus moving the pointer to the
previous element in the string. The word register specified by "r" (used as a
counter) is then decremented by one. The source register is unchanged. The
source, destination, and counter registers must be distinct, non-overlapping
registers. The translation table contains up to 256 bytes, one for each possible value
of the target byte. The size of the translation table may be reduced when it is known
that some target byte values will not occur.

Flags:

Unaffected
Z: Unaffected
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Exceptions:

None

Addressing
Mode
IR:

Example:

Assembler Language
Syntax

Instruction Format

101111000

Rd,*O

1000

00001

Rs,*O

0000

In linear mode, if register RR6 contains %00004001, the byte at location
%00004001 contains 3, register RR20 contains %00001000, the byte at location
%00001003 contains %AA, and register R12 contains 2, executing the instruction
TRDB @RR6, @RR20, R12
leaves the value %AA in location %00004001, the value %00004000 in RR6, and
the value 1 in R12. RR20 is not affected. The V flag is cleared. In compact mode,
word registers must be used instead of RR6 and RR20.
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-191

TRDRB
Translate, Decrement and Repeat
TRDRB dst, src, r

Operation:

dst: IR
src: IR

repeat
dst - src [dst]
AUTODECREMENT dst by 1

r - 1

until r =

This instruction is used to translate a string of bytes from one code to another. The
contents of the location addressed by the destination register (the "target byte") are
used as an unsigned index into a translation table whose base address is contained
in the source register. An effective address is calculated by adding the zeroextended target byte to the translation table base address using the rules for address arithmetic in the current mode of address representation: compact,
segmented, or linear. The effective address is the location of the translated value
used to replace the original contents of the target byte.
The destination register is the decremented by one, thus moving the pointer to the
previous element in the string. The word register specified by "r" (used as a
counter) is then decremented by one. The source register is unchanged. The entire
operation is repeated until the result of decrementing r is zero. This instruction can
translate from 1 to 65,536 bytes. The source, destination, and counter registers
must be distinct and non-overlapping registers. The translation table contains up to
256 bytes, one for each possible value of the target byte. The size of the translation
table may be reduced when it is known that some target byte values will not occur.
This instruction can be interrupted after each execution of the basic operation.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set
0: Unaffected
H: Unaffected

Exceptions:
Addressing
Mode

IR:

None

Assembler Language
Syntax
TRDRB @Rd 1, @Rsl, r

Instruction Format

I111000

0000

6-192

1100

Rs*O

0000

Example:

In compact mode, if register R6 contains %4002, the bytes at locations %4000
through %4002 contain the values %00, %40, %80, respectively, register R9 contains % 1000, the translation table from location % 1000 through % 10FF contains 0,
1, 2, ... , % 7F, 0, 1, 2, ... , % 7F (the second zero is located at % 1080), and register
R12 contains 3, executing the instruction
TRDRB @R6, @R9, R12
leaves the values %00, %40, %00 in byte locations %4000 through %4002,
respectively. Register R6 contains %3FFF, and R12 contains O. R9 is not affected.
The V flag is set. In segmented or linear mode, longword registers must be used instead of R6 and R9.
BEFORE
%1000

00000000

'%4000

%1001

00000001

%4001

%1002

00000010

%4002

AFTER

··
·

%107F

%1080

00000000

1 1 1 1 1 1

%4000

%1081

00000001

%4001

%1082

00000010

%1QFF

%4002

··
·

1 1 1 1 1 1

Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-193

TRIB

Translate and Increment
TRIB dst, src, r

Operation:

dst: IR
src: IR

dst - src[dst]
AUTOINCREMENT dst by 1

r- r - 1
This instruction is used to translate a string of bytes from one code to another. The
contents of the location addressed by the destination register (the "target byte") are
used as an unsigned index into a translation table whose base address is contained
in the source register. An effective address is calculated by adding the zeroextended target byte to the translation table base address using the rules for address arithmetic in the current mode of address representation: compact,
segmented, or linear. The effective address is the location of the translated value
used to replace the original contents of the target byte.
The destination register is then incremented by one, thus moving the pointer to the
next element in the string. The word register specified by "r" (used as a counter) is
then decremented by one. The source register is unchanged. The source, destination, and counter registers must be distinct and non-overlapping registers. The
translation table contains up to 256 bytes, one for each possible value of the target
byte. The size of the translation table may be reduced when it is known that some
target byte values will not occur.

Flags:

Z:
S:
V:
D:
H:

Exceptions:

Unaffected
Unaffected
Unaffected
Set if the result of decrementing r is zero; cleared otherwise
Unaffected
Unaffected

None

Addressing
Mode

Assembler Language
Syntax

IR:

TRIB @Rd', @Rsl, r

6·194

Instruction Format

1 01111 000

Rd""O 0 0 0 0

0000\

Rs""O

0000

Example:

This instruction can be used in a "loop" of instructions that translate a string of
data from one code to another code, but an intermediate operation on each data
element is required. The following sequence translates a string of 1000 bytes to the
same string of bytes, with all ASCII "control characters" (values less than 32)
translated to the "blank" character (value = 32). A test, however, is made for the
special character" return" (value = 13) which terminates the loop. The translation
table contains 256 bytes. The first 33 (0-32) entries all contain the value 32, and all
other entries contain their own index in the table, counting from zero. This example
assumes compact mode. In segmented or linear mode, longword registers must be
used instead of R4 and R5.
LD
LDA
LDA

R3, #1000
R4, STRING
R5, TABLE

lIinitialize counter
IIload start addresses

CPB
JR
TRIB
JR

@R4, #13
EQ,DONE
@R4, @R5, R3
NOV, LOOP

IIcheck for return character
lIexit loop if found
IItranslate next byte
IIrepeat until counter = a

LOOP:

DONE:
TABLE+O

00100000

TABLE + 1

00100000

TABLE + 2

00100000

TABLE+32

00100000

TABLE+33

00100001

TABLE + 34

00100010

TABLE + 255

11111111

··
·
··
·

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-195

TRIRB
Translate, Increment and Repeat
TRIRB dst, src, r

Operation:

dst: IR
src: IR

repeat
dst - src[dst]
AUTOINCREMENT dst by 1

r- r - 1
until r

This instruction is used to translate a string of bytes from one code to another. The
contents of the location addressed by the destination register (the "target byte") are
used as an unsigned index into a translation table whose base address is contained
in the source register. An effective address is calculated by adding the zeroextended target byte to the translation table base address using the rules for address arithmetic in the current mode of address representation: compact,
segmented, or linear. The effective address is the location of the translated value
used to replace the original contents of the target byte.
The destination register is then incremented by one, thus moving the pOinter to the
next byte in the string. The word register specified by "r" (used as a counter) is
then decremented by one. The source register is unchanged. The entire operation is
repeated until the result of decrementing r is zero. This instruction can translate
from 1 to 65,536 bytes. The source, destination, and counter registers must be
distinct and non-overlapping registers. The translation table contains up to 256
bytes, one for each possible value of the target byte. The size of the translation
table may be reduced when it is known that some target byte values will not occur.
This instruction can be interrupted after each execution of the basic operation.

Flags:

Unaffected

Z: Unaffected
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Exceptions:
Addressing
Mode
IR:

None

Assembler Language
Syntax

Instruction Format

1 0 11 1 1 0 0 0
00 0 0

6-196

'* 0
Rs '* 0
Rd

0100
0000

Example:

The following sequence of instructions can be used to translate a string of 80 bytes
from one code to another. The pointers to the string and the translation table are
set, the number of bytes to translate is set, and then the translation is accomplished. After executing the last instruction, the V flag is set. The example assumes
compact mode. In segmented or linear mode, longword registers must be used instead of R4 and R5.
LOA
R4, STRING
LOA
R5, TABLE
LO
R3, H80
TRIRB @R4, @R5, R3
Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-197

TRTDB
Translate, Test and Decrement
TRTOB src1, src2, r

Operation:

src1: IR
src2: IR

RH1 - src2[src1]
AUTODECREMENT src1 by 1

r - 1

This instruction is used to scan a string of bytes, testing for bytes with special
values. The contents of the location addressed by the first source register (the
"target byte") are used as an unsigned index into a translation table whose base ad·
dress is contained in the second source register. An effective address is calculated
by adding the zero·extended target byte to the base address using the current mode
of address representation: compact, segmented, or linear. The effective address is
the location of the translated value that is loaded into register RH 1. The setting of
the Z flag indicates whether or not the translated value is zero.
The first source register is then decremented by one, thus moving the pointer to the
previous byte in the string. The word register specified by "r" (used as a counter) is
then decremented by one. The second source register is unchanged. The source
and counter registers must be distinct, non·overlapping registers. The translation
table contains up to 256 bytes, one for each possible value of the target byte. The
size of the translation table may be reduced when it is known that some target byte
values will not occur.

Flags:

Unaffected

Z: Set if the translated value loaded into RH 1 is zero; cleared otherwise
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected
Exceptions:

Addressing

None

Mode

Assembler Language
Syntax

IR:

TRTDB @Rs1 1 • @Rs21, r

Example:

Instruction Format

1 01111000

Rs1;
dst --1
This instruction tests the most-significant bit of the destination operand, copying its
value into the S flag, then sets the entire destination to all 1 bits. It provides a locking mechanism for synchronizing software processes that require exclusive access
to certain data or instructions at one time. No other interlocked accesses are permitted to the destination memory location between fetching and storing the result.

Unaffected
Unaffected
Set if the most-significant bit of the destination was 1; cleared otherwise
Unaffected
Unaffected
H: Unaffected

Flags:

Z:
S:
V:
D:
Exceptions:

Destination
Addressing
Mode

None

Assembler Language
Syntax

Instruction Format

TSET Rd
TSETB Rbd
TSETL RRd

0111101000000010

1 01 0 0 1 1 0 1

IR:

0110

TSET @Rd1
TSETB @Rd1
TSETL @Rd1

EAM:

RRd

TSET eam
TSETB eam

01111010

0000 0010

001001101

Rd*O 0110

01100110lw

earn

0110

1, 2, or 3 extension words
TSETL eam

0111101000000010

o 11

001101

earn

0110

1, 2, or 3 extension words

6-205

Example:

A simple mutually·exclusive critical region can be implemented by the following
sequence of statements:
ENTER:
TSET
JR

SEMAPHORE
MI,ENTER
IIloop until resource con·
//trolled by SEMAPHORE
/lis available

IIcritical region-only one software process
lIexecutes this code at a time

CLR

SEMAPHORE lire lease resource controlled
IIby SEMAPHORE

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6·206

XOR

Exclusive Or
XOR dst, src
XORB
XORL

Operation:

dst -

dst: R
src: R, 1M, IR, EAM

dst XOR src

A logical XOR operation is performed between the corresponding bits of the source
and destination operands, and the result is stored in the destination. A 1 bit is stored
wherever the corresponding bits in the two operands differ; otherwise a 0 bit is
stored. The contents of the source are not affected.

Flags:

Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most-significant bit of the result is set; cleared otherwise
P: XOR, XORL-unaffected; XORB-set if parity of the result is even;
cleared otherwise
0: Unaffected
H: Unaffected

Source
Addressing
Mode

Assembler Language
Syntax
XOR Rd, Rs
XORB Rbd, Rbs
XORL RRd, RRs

1M:

XOR Rd, #data

Instruction Format

110100100lwl

01111010 0000 0010
1 01 001 001

RRs

RRd

001001001

0000

data
XORB Rbd, #data

001001000

0000

XORL RRd, #data

Rbd

data

0111101000000010
o 01 0 0 1 0 0 1 0 0 0 0

RRd

data (high)
data (low)

6-207

Source
Addressing
Mode
IR:

Assembler Language
Syntax

Instruction Format

XOR Rd, @RS1
XORB Rbd, @RS1
XORL RRd, @RS1

0111101000000010

o 01
EAM:

XOR Rd, eam
XORB Rbd, eam

00100 1

01100100lW

earn

RRd

1, 2, or 3 extension words

XORL RRd, eam

0111101000000010

o 11

00 1 0 0 1

earn

RRd

1,2, or 3 extension words

Example:

If register RL3 contains %C3 (11000011) and the source operand is the immediate
value % 7B (01111011), executing the instruction

XORB

RL3,#% 7B

leaves the value % B8 (10111000) in RL3.
Note 1: Word register in compact mode. longword register in segmented or linear modes.

6-208

6.6 EPA Instruction Teaplates
There are seven templates for EPA instructions.
If the Extended Processing Architecture enable bit
(EPA) in the Flag and Control Word is set when the
CPU encounters one of the instruction templates,
the CPU transfers the instruction and operands to
the EPU. The CPU merely transfers the operands to
the EPU, but does not process them in any way.

that selects one of up to four possible EPUs in
the system. When an EPU detects an exception, it
signals the CPU through one of the interrupt
request pins.
For examples of EPU mnemonics,
opcodes, and exceptions, see the l8070 Floating
Point Processor Technical Manual (lilog document

Each type of EPU has its own mnemonics, opcodes,
and exceptions to represent its particular data
processing operations. The shaded portions of the
instruction template shown below are ignored by
the CPU; they are used by an EPU to specify its
particular operations. The two least-significant
bits of the first word of the instruction templates are reserved to encode an identifier field

The instruction templates shown below correspond
to the data transfer operations performed by the
CPU. Oat a can be transferred between an EPU and
memory, EPU and CPU general-purpose registers, or
between an EPU and the CPU flags byte register.
The last template is for EPU internal operations
that require no data transfers.

03-8226-01).

Extended Instruction
Load Memory from EPU

Operation:

Memory -

EPU (n bytes or words)

The CPU calculates the effective address and generates transactions on the external interface for an EPU to write n words or bytes of data to memory. The value in
the instruction field for the number of words or bytes loaded ("n") is one less than
the actual value of the source operand. Thus, the coding in the instruction field
ranges from 0 to 15, which corresponds to loading 1 to 16 words or bytes.

Flags:

No flags affected.

Exceptions:

Extended Instruction trap

Destination
Addressing
Mode

Operation

IR:

@Rd' -

EAM:

EPU -

Instruction Format

EPU

eam

1, 2, or 3 extension words

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-209

Extended Instruction

Load EPU from Memory
Operation:

EPU -

Memory (n bytes or words)

The CPU calculates the effective address and generates transactions on the external interface to read n words or bytes of data from memory to an EPU. The value in
the instruction field for the number of words or bytes loaded ("n") is one less than
the actual value of the source operand. Thus, the coding in the instruction field
ranges from 0 to 15, which corresponds to loading 1 to 16 words or bytes. When Immediate addressing mode is used for an odd number of bytes, an extra byte containing Os is included at the end of the instruction, making the instruction length an integral number of words.

Flags:

No flags affected.

Exceptions:

Extended Instruction trap

Source
Addressing
Mode

Operation

Instruction Format

*data

1M:

EPU -

IR:

EPU -@Rs1

EAM:

EPU -eam

1, 2, or 3 extension words

Note 1: Word register in compact mode, longword register in segmented or linear modes.

6-210

Extended Instruction
Load CPU from EPU

Operation:

CPU -

EPU registers (n words)

The contents of n words are transferred from an EPU to consecutive CPU registers
starting with the specified destination register. The value in the instruction field for
the number of words loaded ("n") is one less than the actual value of the source
operand. Thus, the coding in the instruction field ranges from D to 15, which corresponds to loading 1 to 16 words.
For the word operand version, the CPU word registers (RD - R15) are loaded. RD
follows R15 in consecutive order.
For the longword operand version, the CPU longword registers (RRD - RR3D) are
loaded. RRD follows RR3D in consecutive order. If the number of loaded words is
odd, then the low-order halt of the last longword register loaded is undefined after
executing this instruction.

Flags:

No flags affected.

Exceptions:

Extended Instruction trap

Destination
Addressing
Mode

Operation

Rd- EPU

RRd -

Instruction Format

EPU

6-211

Extended Instruction
Load EPU from CPU
Operation:

EPU -- CPU registers (n words)
The contents of n words are transferred to an EPU from consecutive CPU registers
starting with the specified source register. The value in the instruction field for the
number of words loaded ("n") is one less than the actual value of the source
operand. Thus, the coding in the instruction field ranges from 0 to 15, which corresponds to loading 1 to 16 words.
For the word operand version, the EPU is loaded from CPU word registers (RO R15). RO follows R15 in consecutive order.
For the longword operand version, the EPU is loaded from CPU longword registers
(RRO - RR30). RRO follows RR30 in consecutive order. If the number of loaded
words is odd, then the low-order word of the last longword register is not involved in
the loading.

Flags:

No flags affected.

Exceptions:

Extended Instruction trap

Source
Addressing
Mode

Operation

EPU -- Rs

EPU -- RRd

6-212

Instruction Format

Extended Instruction
Load FeW from EPU
Operation:

Flags -

EPU

The flags in the CPU's Flag and Control Word are loaded with information from an
EPU. Only the flag bits are loaded; bits a and 1 of the Flag and Control Word are
unaffected.

Flags:
Exceptions:

Flags loaded from EPU.
Extended Instruction trap

Operation

Instruction Format

FCW- EPU

Extended Instruction
Load EPU from FeW
Operation:

EPU -

Extended Instruction
Load EPU from FeW

Flags

The flag byte of the CPU's Flag and Control Word is transferred to an EPU.

Flags:

No flags affected.

Exceptions:

Extended Instruction trap

Operation

EPU -

Instruction Format

FCW

6-213

Extended Instruction

Internal EPU Operation
Operation:

Internal EPU Operation
This template is for an EPU internal operation, one which requires no data transfers.

Flags:

No flags affected.

Exceptions:

Extended Instruction trap

Instruction Format

6-214

Chapter 7.

IlIItractloD Exec:ulioD and
Exceptio..
7.1

INTROOUCTImI

To execute an instruction, the CPU fetches the
instruction whose address is in the Program
Counter (PC), increments the PC by the length of
the inatruction, and per forma the operationa
specified in Chapter 6 for the particular
instruction. Exceptions are conditions or events
thst slter the sequence of inatruction execution.
The CPU recognizea four types of exceptions:
reset, bus error, interrupts, and traps.
A reset exception occurs when the REm line is
activated.
Reset initislizea the CPU.
A bua
error exception occurs when externsl hardware
indicatea en irrecoverable error during s dsts
transfer on the external interfsce. An interrupt
is sn asynchronoua event indiceted when the NMi,
VI, or NVI line is sctivated. Interrupts are
typically caused by periphersl devices that
require attention. A trsp occurs synchronously
when a particular condition, such as integer
overflow, ia detected by the CPU during
instruction execution.
When en exception occurs, the CPU stores the Program Status on the system stack, fetches the new
Program Ststus from the Program ststus Area, end
resumes executing instructions.
This chspter
deacribes inetruction execution and exception
proceasing.

7.2 OPERATING STATES

The CPU is always in one of four possible operating states regarding instruction execution and
exception processing: reset, exception processing, instruction exacuting, or hslted. figure 7-1
shows the four states and the trsnsitions between
them.
The CPU enters the reset state from any other
state when s reset request is signslled on the
RESET line.
When RESET 1s relessed, the CPU
enters exception proceasing state.
The reset
stste is described in more detail in Section 8.10.

8225-016

Figure 7-1.

Operating states

In the exception processing stste, the CPU is
either storing values from the Program Status registers to memory or fetching values from memory
for the Program Stetua regiaters. The storing end
fetching of Program Status is described in Section
7.4.5. from the exception processing state the
CPU normally enters the instruction executing
state; however, s bus error excaption causes a
transition to the halted state.
In the instruction executing state, the CPU executes instructions. When the Halt instruction is
executed, the CPU enters the helted state. If sn
exception other than reset occurs, the CPU enters
the exception processing state.
In the halted state the CPU is halted; it is
neither executing instructions nor processing
When an interrupt occurs, the CPU
exceptions.
enters the exception processing state.

7-1

Instruction Execution and Exceptions
7.3

INSTRUCTIIW EXEaJTIIW

Executing an instruction involves the following
operations:
•
.•
•
•
•

fetch the instruction
Increment PC
fetch operands, if necessary
Cslculate results
store results and flags, if necessary

In concept, the CPU axecutes instructions by performing all the operations listed above in strict
sequence for one instruction, and then beginning
execution of the next instruction. However, the
CPU checks for exceptions at several points during
instruction execution. An exception can alter the
operations for an instruction currently being executed, as well as the sequence from one instruction to the next.
Also, the CPU overlaps the
operations for executing several instructions in a
multiple-stage pipeline. That is, while the CPU
is calculating the results for one instruction, it
can be storing the results for the previous
instruction and fetching the opersnds for the next
instruction. The use of an instruction pipeline,
rather than completely executing each instruction
in strict sequence, enhances the performance of
the CPU.
This section describes the effects of exceptions
and the pipeline on instruction execution.
Section 7.3.1 explains how different exceptions
affect instruction execution, and Section 7.3.2
explains how the pipeline affects instruction
execution.

7.3.1

Instruction £nding

Instruction execution can end in any of five ways:
completion, suspension, suspension with PC modification, termination, or partial completion. Generally, an instruction ends in completion; however,
exceptions
can
csuse
a
different
conclusion. Section 7.4 explains each exception
recognized by the CPU, and refers to the different
types of inatruction endings described here.
When an instruction ends in completion, the CPU
has completely executed the instruction and all
pravious instructions.
Any result operands and
flags modified by the instruction have been
stored, and the PC holds tha addrass of tha next
instruction to execute. If an axception occurs
aftar sn instruction ends in complation, the Program Status saved on ~he systam stack can be
restored using the Interrupt Return (IRET)
instruction. Execution will then resume with the
7-2

next instruction in sequence following the completed instruction.
When an instruction ends in suspension or suspension with PC modification, the CPU has not completely executed the instruction, but all previous
instructions have been completed. Any flags and
destination operands due to be stored by the
instruction may be modified; however, only modifications that allow the instruction to be completed
are possible. Also, an instruction that ends in
suspension or suspension with PC modification will
not have modified any control registers, memory
locations, or peripheral ports that are protected
from access in the current operating mode.
Examples:
1.

An Add (ADDB) instruction modifies the flags,
but does not examine the flags. If an ADDB
instruction ends in suspension because of an
address translation exception, the flags may
be modified.

A Load (LD) instruction can store into a register whoee contents are required for an
effective address calculation, e.g., LDL RR2,
taRR2. I f the LD instruction ends in suspension because of an address translation exception, the register contents are unmodified.

When an instruction ends in suspension, the PC
holds the address of the first word of the
instruction. When an instruction ends in suspension with PC modification, the PC holds the
address of the word following the first word of
the instruction.
An instruction ends in suspension, or suspension
with PC modification, when the CPU detects a trap
condition, such as an address translation exception or unimplemented instruction, before completely executing the instruction. An instruction
ending in suspension can be completed by eliminating the trap condition and restoring the Program
Status saved on the system stack using the IRET
instruction. An instruction ending in suspension
with PC modification can be completed by eliminating the trap condition, decrementing the PC value
stored on the system stack by two using the mode
of address representation in effect for the suspended instruction, and restoring the Program
Status using the IRET instruction.
When an instruction ends in termination, the CPU
has not completely executed the instruction, but
all previous instructions have been completed.
Any flags and destination operands due to be
stored by the instruction msy be modified; the

Instruction Execution and Exceptions
contents of PC are undefined.
A terminated
instruction will not have modified any control
registers, memory locations, or peripheral ports
that are protected from access in the current
operating mode. It is not possible to complete an
instruction that ends in termination. Only reset
and bus error cause instruction termination.
Only interruptible instructions can end in partial
completion.
Interruptible instructions are the
"repeat" versions of block transfer, string manipulation, and input/output instructions (Sections
6.2.8 and 6.2.9). Interruptible instructions are
repeatedly executed until a specified data value
is found for one of the operands, or a counter
held in a register is decremented to zero. While
the CPU is executing an interruptible instruction,
if an Address Translation trap or interrupt
occurs;
the instruction ends in partial
completion.
Any flags and destination operands
due to be stored by the instruction may be
modified; however, the values stored in the
counter
and
address
registers
allow
the
instruction to be completed correctly when the
instruction is re-executed.
The PC holds the
address of the first word of the instruction. An
instruction ending in partial completion can be
completed by eliminating the cause of the
exception and restoring the Program Status saved
on the system stack using the IRET instruction.

7.3.2

Effects of the Pipeline on Execution

The CPU executes several instructions simultaneously in a multiple-stage pipeline.
In most
circumstances, the differences between pipelined
instruction execution and the complete execution
of each instruction in strict sequence cannot be
detected by software or hardware.
However, the
few cases in which the effects of the pipeline can
be detected are described below.
The CPU can prefetch an instruction before completing all previous instructions. Consequently,
if an instruction stores to a location from which
a subsequent instruction is fetched (i.e., the
program modifies itself), the CPU can prefetch the
original contents of the memory location rather
than the modified contents. Thus, self-modifying
programs may not operate as intended.
On the
external interface, instruction prefetching can
have the effect of fetching an instruction that is
not executed (e.g., if the previous instruction
causes a trap) or fetching an instruction before
the operands for a previous instruction are
fetched.
Some privileged instructions (IRET,
LDCTL, LDCTLL, LDPS, PCACHE, PTLB, PTLBE, and
PTL6N) have the effect of serializing instruction

execution.
The ser ializing instruction and all
previous instructions are completely executed,
including storing of all results and flags, before
fetching the next instruction. Thus, when a new
value is loaded into the FCW by a LDCTL
instruction, the address representation mode and
operating mode used to fetch and execute the next
instruction are determined by the new FCW value.
The CPU can also pre fetch an operand for an
instruction
before completing
all
previous
instructions. The effects of operand pre fetching
cannot be detected by software because the CPU
only fetches an operand from a location after completing all previous instructions that modify the
location. On the external interface, operand prefetching can have the effect of fetching an
operand for an instruction that is not executed,
for example, if the previous instruction causes a
trap. Operands in physical I/O space are not prefetched, ensuring that the CPU only fetches data
from an input peripheral port for instructions
that are executed.

7.~

EXCEPTIONS

The CPU recognizes four types of exceptions:
reset, bus error, interrupts, and traps. In processing exceptions other than reset, the CPU saves
the Program Status and an identifier word on the
system stack. For some exceptions, the CPU saves
an additional longword parameter.
Then the CPU
fetches a new Program Status from the Program
Status Area.
The sections below describe the
cause of each exception, CPU response to exceptions, and priority among exceptions.

7.~.1

Reset

Reset occurs when the RESET line is Low. Reset
causes any instruction in execution to end in termination.
At reset the Translation and Cache Enable bits of
the System Configuration Control Longword register
(NX, SX, CI, and CD) are cleared to O.
Some
fields of the Hardware Interface Control register
are initialized as described in Section 6.10.
When the RESET line is driven High, the CPU
fetches the FCW from physical memory address 2 and
the PC from physical memory address 4. Reset also
invalidates all entries in the cache and
the Translation Lookaside Buffer.
After reset,
the contents of all CPU registers other than the
FCW, the PC, and the specified fields of SCCL and
HICR are undefined. Reset should be used to initialize the CPU at power-on.
7-3

Instruction Exscution snd Exceptions
7.4.2 BuB Error
Bus error is indicstsd by s device ,responding to s
dsts trsnsfer transsction on the externsl interface. A bus error ceuses any instruction in execution to end in tsrminstion. Tha idsntifier word
ssved during bua error exception processing
raporta the atate of the CPU pins. The physical
addresa for the trsnsaction ia saved as s parametar on the system stsck. Refer to Section 8.8.8
for more detsils about the bus error exception.

7.4.3 Interrupts
Ths CPU recognizes three kinds of interrupt signslled on separsts pinal non-masksble, vectored,
snd non-vectored.
Non-mssksble interrupts sre
slwsys enabled. Vsctored and non-vectored interrupta can be selectively enabled by bita VIE snd
NVIE in the FCW. Vectored interrupts are enebled
when VIE is 1; non-vectored interrupts are enabled
when NVIE ia 1.
An interrupt occurs when an enabled interrupt
request is signalled on a CPU pin. The CPU generates an interrupt acknowledge trsnsaction on tha
external intarface to fetch the idantifier word,
which is then savad on the system stack. For vectored interrupts, the low-order byte of the identifier word is used to select a pointer to a particular interrupt handler routine. Refer to Section 8.7.5 for more details about interrupt
request and acknowledge.,

7.4.4 Traps
The CPU recognizes ten traps, described below.
7.4.4.1 Extandad Instruction Trap.
This trap
occurs when sn Extended Processing Architecturs
instruction is executed and the EPA bit of the FCW
is O. The instruction ends in auspension with PC
modification. The identifier is the first word of
the instruction.
This trap sllows softwsre to
simulste execution of the EPA instruction when no
EPU is in the system.
7.4.4.2 Privileged Instruction Trap.
This trap
occurs when s program attempts to execute a
privileged instruction in normal mode; the
instruction
ends
in
suspension
with
PC
modificstion. The identifier is the first word of
the instruction.
7.4.4.3 Syat.. Call Trap. This trsp occurs when
a System Csll instruction is executed.
The

7-4

instruction ends in completion; the identifier is
the instruction word. This trsp is used by programs executing in normsl mode to request services
from the opersting system. The low-order byts of
the instruction word indicstes the psrticular service requested.
7.4.4.4
Addrees Tr-ration Trap. This trsp
occurs when sn sddress translstion error is
detected, either sn invalid table entry or sn
sccess protection violstion.
The instruction
ends in suspension. The identifier word reports
the sddress space for the logicsl sddress and the
exception type (see Section 4.3.5 for more informstion).
The logicsl sddress thst csused the
translstion error is ssved ss s psrameter on the
system stack.
7.4.4.5 Breakpoint Trap. This trsp occurs when
the Brsskpoint instruction is executed.
The
instruction ends in completion; the identifier is
the instruction word.
7.4.4.6
Integer Arit'-tic Error Trap.
This
trsp occurs when sny of three error conditions is
detected during execution of integer sritllnetic
instructions.
The error conditions are integer
overflow, bounds check, snd index error. Integer
overflow error is enabled by the IV bit in the
FCW. Integer overflow is detected when the IV bit
is 1 snd the V flag is set by execution of ADD,
DEC, DECI, DIV, DIVU, INC, INCI, NEG, SUB, SDA,
SRA, SLA, CVT, or CVTU instructions. For DIV snd
DIVU instructions, Integer Overflow error includss
the csse of zero divisor. A bounds check error is
detected when s Check instruction is executed snd
the destinstion operend is out of bounds.
An
index error is detected when an Index instruction
is executed snd the subscript is out of bounds.
The instruction ends in completion.
The
identi fier word indicates the type of error, ss
shown in the following table.

Identifier

Error

Integer Overflow
Bounds Check
Index Error

7.4.4.7 Conditional Trap. This trsp occurs when
s Trap instruction is executed snd the tested condition is sstisfied. The instruction ends in completion; the identifier is the instruction word.
This trsp can be used for softwsre detection of
run-time errors.

Instruction Execution and Exceptions
Unillpl_ted Inatruction Trap.
This
trap occurs when a program attempts to execute an
instruction with an unimplemented bit pattern.
The detected bit patterns include certain zaooo
opcodes described in Appendix A and instructions
with first byte 3616, or Bf 16. The instruction
ends 1n suspension with PC modificstion; the
identifier is the first word of the instruction.
7 ••••• 8

The Trace trap handler should set the T bit to 1
and clear the TP bit to 0 in the fCW on the system
stack before executing IRET and returning to the
traced program. Note that the T bit in the fCW on
the system stack can be cleared when an IRET,
LOCTL, or LOPS instruction is traced.

7 ••• 5

This trap occurs befors
execution of an instruction when the PC contains
an odd address. The contents of the identifier
word are undefined.

7 ••••• 9

Dwtging Progr_ status

Odd PC Trap.

7 ••••• 10 Trace Trap. This trap occurs before an
instruction ia executed when the TP bit in the fCW
ia 1. The contents of the identifier word are
undefined.
Instruction tracing is enabled by the T bit in
fCW. Before each instruction is executed, T is
copied to TP.
The use of two bits to control
inatruction tracing enaures that, while tracing is
enabled, exactly one Trace trap is processed after
sach instruction's execution, and after the
servicing of other traps and interrupts. Section
7.4.7 provides more information about the priority
for handling Trace traps and other exceptions.

To process all exceptions other than reset, the
CPU pushes the Progran Status and an identifier
word on the system stack. An Address Translstion
trap and bus error push an additional longword
parameter onto the system stack. The saved value
of the PC depends on the type of instruction ending. As selected by the XL!S bit in the System
Configuration Control Longword (SCCL) register,
the CPU operates in either segmented system mode
(XL/S = 0) or linear system mode (XL!S = 1) while
saving the Program Status and other information;
but the saved value of the fCW indicates the mode
of operation when the exception occurred.
figure 7-2 shows how the information is saved on
the stack.

LOW ADDRESS
SYSTEM SP
AFTER_
EXCEPTION

PARAMETER (HIGH)
PARAMETER (LOW)

SYSTEM SP
AFTER_
EXCEPTION

IDENTIFIER

FCW

PC (HIGH)

PC (LOW)

SYSTEM SP
BEFORE_
EXCEPTION

SYSTEM SP
BEFORE_
EXCEPTION
_

1 WORD_

_ 1 WORD _
HIGH ADDRESS

WITHOUT PARAM.TER

Figure 7-2.

Progr_ status Saved on 51st- St.:k

8225-017

7-5

Instruction Execution snd Exceptions
A new Program status must be fetched from memory
to process any exception. For reset, the FeW is
fetched from physicsl address 2 and the PC is
fetched from physical address 4. Other exceptions
fetch the new Program status from an entry in the
Program status Area (PSA) (Figure 7-3).
Bus
error, non-masksble interrupt, non-vectored interrupt, snd all traps have unique entries in the PSA

from which the new Program status is fetched. For
vectored interrupts, ths new value of the FeW is
loaded from displacement 122 in the PSA. The loworder byte of the identifier word is used to
select the new value of the PC by indexing into a
table of 256 values beginning at displacement 124
in the PSA.

L
PROGRAM STATUS
AREA POINTER

} RESERVED
8

RESERVED

EXTENDED
} INSTRUCTION
TRAP

FCW
PC (HIGHI
PC (LOW)

RESERVED

PRIVILEGED
} INSTRUCTION
TRAP

FCW
PC (HIGH)
PC (LOW)

24-31
32-38
40-47
48-55
66-83
84-71
72·78
80-87

RESERVED

SYSTEM CALL TRAP
ADDRESS TRANSLATION TRAP
BREAKPOINT TRAP
INTEGER ARITHMETIC ERROR TRAP
CONDITIONAL TRAP
UNIMPLEMENTED INSTRUCTION TRAP
ODD PC TRAP
TRACE TRAP

}

FCW

SYSTEM STACK
OVERI'LOW

PC (HIGH)
PC (LOW)

RESERVED

}

FCW

BUS ERROR

PC (HIGH)
PC (LOW)

104

RESERVED

}

FCW

NON·MASKABLE
INTERRUPT

PC (HIGH)
PC (LOW)
112

RESERVED

}

FCW

NON. VECTORED
INTERRUPT

PC (HIGH)
PC (LOW)

120

RESERVED
FCW
PCo(HIGH)
PCo(LOW)

VECTORED
INTERRUPT

PC, (HIGH)
PC, (LOW)
PC. (HIGH)

132

PC. (LOW)

·••
1144

pc... (HIGH)

PC.,,(LOW)

Figure 7-3.

7-6

I
I
Progr_ status Area

8225-018

Instruction Execution and Exceptions
The effective address of an entry in the Program
Status Area is calculated by adding the displacement shown in Figure 7-3 to the physical base
address held in the Program Status Area Pointer
register.
The effective address calculation is
performed in segmented or linear mode, as selected
by the XL/S bit in the SCCL register. The result
is the physical address used to fetch the PSA
entry.
During exception processing, if an address translation error is detected while information is
being saved on the system stack, the System Stack
Pointer is restored to its value before the exception occurred and the overflow stack is used
instead.
The top of the overflow stack is

addressed by the Overflow Stack Pointer register
(OSP). The Program Status, identifier word, and
exception parameter (or an undefined longword i f
there is no exception parameter) are pushed on the
overflow stack.
A word
containing
the
displacement of the exception entry in the PSA is
also pushed onto the overflow stack.
The new
Program Status is fetched from displacement BB in
the PSA.
Since the OSP register contains a
physical address, an Address Translation trap
cannot occur when pushing information on the
overflow stack. The effective address calculation
for pushing onto the overflow stack is performed
in segmented or linear mode, as selected by the
XL/S bit in the SCCL register. Figure 7-4 shows
how information is saved on the overflow stack.
LOW ADDRESS

OSP
AFTER_
EXCEPTION

PSA DISPLACEMENT

OSP
AFTER_
EXCEPTION

PSA DISPLACEMENT

UNDEFINED

PARAMETER (HIGH)

UNDEFINED

PARAMETER (LOW)

IDENTIFIER

FCW

PC (HIGH)

PC (LOW)
OSP
BEFORE_
EXCEPTION

PC (LOW)
OSP
BEFORE~

EXCEPTION

WORD----+-

~1WORD---"

HIGH ADDRESS

WITHOUT PARAMETER

WITH PARAMETER

Figure 7-4.
Progr_ Status Saved on Overflow Stack

7.4.6 Exception Handlers
After the new Program Status has been fetched, the
CPU begins executing instructions of the exception
handler routine whose address was loaded into the
PC.
The new value of the FCW determines the
address representation mode (compact/segmented/
linear), operating mode (system/normal), and the
enabled interrupts and traps for the exception
handler.
An interrupt handler can execute with
interrupts disabled until critical information has
been stored.
The interrupt handler can then
enable interrupts, permitting nested interrupt
servicing.

8225'()19

The exception handler can examine the identifier
word and parameter (only bus error and Address
Translation trap have a parameter) for information
about the cause of the exception. After completing their service, handlers for traps and interrupts execute the Interrupt Return instruction.
The Address Translation trap handler must pop the
long word violation address from the stack before
executing IRET. IRET restores the Program Status
from the system stack so instruction execution can
resume at the point where the exception occurred.
The handlers for Extended Instruction trap,
Privileged Instruction trap, and Unimplemented
Instruction trap must modify the PC value stored
on the stack before executing IRET.

7-7

Instruction Execution and Exceptions

7.4.7 Priority of Exceptions
It is possible for several exceptions to occur
simultaneously.
The CPU checks for particular

exceptions at specific points during instruction
execution. (Figure 7-5.) If multiple exceptions
are detected, the CPU responds to the one with
highest priority.

YES

CW.TPYES

= 1
?

oDDYES
PC

>--.....
YES

FCW.TP .... O

.....

YES

PROCESS
EXCEPTION

Figure 7-5.

7-8

Exception Priority FIOMChart

8225-020

Instruction Execution and Exceptions
Whenever a reset exception is detected, the CPU
responds immediately; any instruction being executed is terminated. Pending bus errors, traps,
and internally latched non-maskable interrupt
requests are eliminated.
If a bus error is detected and reset is not
requested, the CPU responds to the bus error
exception. Any instruction being executed is terminated, and pending traps are eliminated.
Before executing an instruction, the CPU checks
for enabled interrupt requests. The CPU responds
to the highest priority enabled interrupt request,
if any.
The priority of interrupts is, in
descending order, nonmaskable, vectored, and nonvectored. If several devices are requesting the
same interrupt, priority among the devices must be
resolved externally, typically with a daisy
chain or interrupt pr ior it y controller.
After
responding to an interrupt, the new value of FCW
is used to check again for enabled interrupt
requests before executing the first instruction of
the service routine.
If there are no enabled interrupt requests, the

CPU checks the TP bit in the FCW. If TP is set to
1, a Trace trap occurs. Otherwise, the CPU checks
If the
whether the PC contains an odd address.
least-signi ficant bit of PC is 1, an Odd PC trap
occurs. Otherwise, the CPU copies T to TP and
begins executing the instruction.

During instruction execution, one of the following
trap conditions may be detected:
Extended
Instruction trap, Privileged Instruction trap,
Unimplemented
Instruction trap,
or Address
Translation trap.
If one of the conditions is
detected, instruction execution is suspended; TP
is cleared to 0; and the trap is processed.
Otherwise, instruction execution is completed.
After completion of the instruction, one of four
trap conditions may be detected:
System Call
trap, Breakpoint trap, Integer Arithmetic Error
trap, or Conditional trap. If one of these trap
conditions is detected, the corresponding trap is
processed.
For interruptible instructions, the CPU checks for
address translation exceptions during each iteration.
If an address translation exception is
detected, instruction execution ends in partial
completion, TP is cleared to 0, and the trap is
processed.
I f no address translation error has
been detected, the CPU checks for enabled interrupt requests at the end of each iteration except
the last. If an interrupt request is pending, the
CPU clears TP to 0 and responds to the highest
priority request.
An interrupt can occur immediately after
Enable Interrupt instruction is executed
before the next instruction.

the
and

7-9

I
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Chapter 8.

External Interface
8.1

INTRODUCTION

The CPU is only one component in a computer system
containing memory, peripherals, Extended Processing Units (EPUs), DMA controllers, and other CPUs
(Figure B-1).
Zilog has established the Z-BUS
as a convention for the signals and timing used to

interconnect components of a microprocessor system.
The ZBO,OOO CPU is compatible with the
Z-BUS, allowing the CPU to be easily connected
lnto a wide variety of system configurations.
This chapter describes the operation of the CPU
interface with other system components.

PERIPHERALS

U
~
~
zao,ooo
CPU

OTHER
CPU

Figure 8-1. System Configuration
8.2

BUS OPERATIONS

Two kinds of bus operations are defined: trsnsactions and requests. At anyone time, only one
device, known as the msster, has control of the
bus. The master can initiate transactiona on the
bus to transfer data to another device, known as
the responder.
In some transactions, called
flyby, the master controls the transaction, but
another device transfers data with the responder.
The master can also initiate transactions that do
not transfer data. The CPU performs transactions
that transfer data to and from memory, periph-

8225'()21

erals, or EPUs. The CPU controls flyby transactions that transfer data between an EPU and memory. The CPU also performs internal operation and
halt transactions, which do not transfer data.
Only the bus master can initiate transactions;
however, other devices can initiate requests. The
CPU responds to interrupt requests from peripherals by generating an interrupt acknowledge
transaction.
The CPU responds to bus requests
from other potential bus masters, and can initiate
bus requests of its own, ss described in Section
8.9.
In addition, the CPU responds' to reset
requests, which are used to initialize the CPU.

B-1

External Interface

a.3 MUlTIPROCESSQR CONfIGURATIONS

master, using the ~ and
described in Section a.9.

The CPU provides support for interconnection in
four types of multiprocessor configurations
(FIgure a-2):
coprocessor, slave processor,
tightly-coupled multiple CPUs, and loosely-coupled
multiple CPUs.
Coprocessors, such as the Za070 Arithmetic Processing Unit, work synchronously with the CPU to execute a single instruction stream using the
Extended Processing Architecture facility.
The
~ and EPUABORT signals are dedicated for
connection with coprocessors, as described in
Section a.a.4.
Slave processors, such as the Za016 DMA Transfer
Controller, perform dedicated functions asynchronously to the CPU. The CPU and slave processor
share a local bus, of which the CPU is the default

signals, as

Tightly-coupled, multiple CPUs execute independent
instruction streams and communicate through shared
memory located on a cOnlnon (global) bus using the
1:'REtr and GArr signals, as described in Section
a.9. Each CPU is default master of its local bus,
but the global bus master is chosen by sn external
arbiter. The CPU also provides special bus status
information for interlocked memory references
(Test and Set, Increment Interlocked, and Decrement Interlocked instructions), which can be used
with multiple-ported memories.
Loosely-coupled, multiple CPUs generally communicate through a multiple-ported peripheral, such as
the Za03a FlO I/O Interface Unit.
The zao,ooo
CPU's I/O and interrupt facilities can support
loosely-coupled multiprocessing.

LOCAL BUS

(AI COPROCESSOR

(SI SLAVE PROCESSOR

(CI TIGHTLY·COUPLED MULTIPLE CPU

(DI LOOSELY.COUPLED
MULTIPLE CPU

Figure 8-2.
Multiprocessor Configurations

a-2

2071·012

External Interface

8..

CACI£

The CPU implements a cache mechanism that keeps
a copy of recently used memory locations on-chip.
These locations can contain both instructions and
data.
On memory fetches, the CPU examines the
cache to determine if the addressed information is
stored there. If the information is in the cache
(a hit), then the CPU fetches the copy from the
cache, and no transaction is necessary on the
external interface. If the information is not in
the cache (a miss), then the CPU performs a memory
read transaction to fetch the missing information
and stores a copy of the information into the
cache, replacing the least recently used data in
the cache. Thus, the cache serves to reduce the
number of memory read transactions, providing a
substantial boost to performance.
Software can control the cache mechanism in
several ways.
The System Configuration Control
Longword register contains separate control bits
(CI and CD) that enable the cache for instruction
and data references and another bit (CR) that
enables the cache replacement algorithm. In page
table entries, the NC bit can be set to disable
the use of the cache for selected pages.
The
Purge Cache instruction can be executed to invalidate the contents of the cache when a memory location that may have been copied into the cache has
been modified by another processor. For example,
if a slave processor reads from a peripheral port
to a memory location that may be copied in the
cache, the cache must be purged. Similarly, if
two or more tightly-coupled CPUs can alternately
execute one process, the cache must be purged when
the operating system changes from executing one
user-process to another. Appendix C describes the
cache mechanism in more detail, including its
control
and interaction with the external
interface.

8.5 PIN FUNCTIONS
The CPU interface includes 59 signal lines, and
four power supply connections (Figure B-3).
A
summary of the signal pin functions is given
below.
ADo-AD,1.
Address/l)ata (Bidirectional. active
High. :J-state). These 32 lines are time-multi-

plexed to transfer address and data.
At the
beginning of each transaction the lines are driven
with the 32-bit address.
After the address has
been driven, the lines are used to transfer one or
more bytes, words, or longwords of data.

E".

Address Strobe (Output. active low.
:J-state). The rising edge of AS" indicates the

beginning of a transaction and shows that the
address, STO-ST3' R/W, BL/W, BWI[, N/S", and mrnT
are valid.

lIST. Burst (Output. active low, :J-state). A Low
on this line indicates that the CPU is performing
a burst transfer; that is, multiple Data Strobes
following a single Address Strobe.

ETA.

Burst Acknowledge (Input. active low).

Low on this line indicates that the responding
device can support burst transfers.

'IIIJSRrlf.

Bus Request (Input, active low). A Low
on this line indicates that a bus requester has
obtained or is trying to obtain control of the
local bus.

1IIlSD".

Bus Acknowledge (Output, active low).

Low on this line indicates that the CPU has
relinquished control of the local bus in response
to a bus request.
BlN, BW;r.

(Output.:J-stste).

These two lines

specify the data transfer size.
BlN

BW;r Size

High
Low
High
Low

High Byte
High Word
Low Longword
Low Reserved

eLK.

Clock (Input). This line is the clock used
to generate all CPU timing.

M".
~

Data Strobe (Output. active low. :J-state).

is used for timing data transfers.

rPIIISV'.

EPU Busy (Input. active low). A Low on
this line indicates that an EPU is busy. This
line is used to synchronize the operation of the
CPU with an EPU during execution of an EPA
instruction.

EPUABOR1. EPU Abort (Output, active low).

A Low
on this line indicates that the CPU is aborting
execution of an EPA instruction, typically because
an Address Translation trap has occurred.

Global Acknowledge (Input, active low).

Low on this line indicates that the CPU has been
granted control of a global bus.

mIN.

Global

Request

(Output.

active

low.

A Low on this line indicates that the
CPU has obtained or is trying to obtain control of
a global bus.
:J-state).

B-3

External Interface

Ir".

Input Enable (Output, active low, 3-state).

(Input, active low).

A Low on this line

resets the CPU.

A Low on this line can be used to enable buffers
on the AD lines to drive toward the CPU.

Response (Input). These lines encode
the response to transactions initiated by the
CPU. RSPO and RSP1 can be connected together for
Z-BUS
timing.
RSPn-RSP1.

mtr.

Non-Maskable Interrupt (Input, edge acti-

A High-to-Low transition on this line
requests a non-maskable interrupt.

vated).

Non-Vectored Interrupt (Input, active low).

A Low on this line requests a non-vectored interrupt.
N~.

No1'llal/Syst_ Mode (Output, low = Syst_
Mode, 3-state). This line indicates whether the

CPU is operating in normal or system mode.

llr".

Output Enable (Output, active low, 3-state).

STn-ST3·

RSPO

RSP1

Response

High
Low
High
Low

High
High
Low
Low

Ready
Bus Error
Bus Retry
Wait

Status (Output, active High, 3-state).

A Low on this line can be used to enable buffers
on the AD lines to drive away from the CPU.

These lines encode the kind of transaction occurring on the bus. (See Table B-1.)

R/i.

vr.

Read/Write (Output, low = Write, 3-state)

RESET

INTERRUPT
REQUESTS

EXTENDED
PROCESSOR
CONTROL

AD~
NMI

RIW

zao,ooo

BUW

CPU

BWI[

EPUBSY

NIS

CONTROL

BUSACK

BUS STATUS
AND TIMING

STATUS

EPUABORT

RESPONSE

-¥-

OE
IE

GREQ

BUFFER
CONTROL

GACK
BRST
BRSTA

+5 V

Figure 8-3.

8-4

ADDRESS/DATA
BUS

iWi

BUSREQ

_Vi

LOCAL BUS

GLOBAL BUS
CONTROL

Vectored Interrupt (Input, active low).

Low on this line requests a vectored interrupt.

This line indicates the direction of data transfer.

GND

BURST TRANSFER
CONTROL

CLOCK

Z80,OOO Pin Functions

2071-011

External Interface
0.6

HARDWARE INTERfACE CONTROL REGISTER

The Hardware Interface Control register (HICR)
speci fies certain characteristics of the hardware
configuration surrounding the CPU, including bus
speed, memory data path width, and number of automatic wait states.
The physical memory address
space is divided into two sections, t'\) and M1'

selected by bit 30 of the memory address. A typical system would locate slow, 16-bit wide bootstrap ROM in MO and faster, 32-bit wide dynamiC
RAM in M1'
The physical I/O address space is
similarly divided into two sections, 1/00 and
1/01' selected by bit 30 of the port address. The
fields of HICR (Figure 8-4) are described below.

figure 0-4. Hardware Interface Control Register

Speed (S) specifies the frequency of the bus clock
relative to the processor clock. If this bit is
1, the bus clock frequency is 1/2 the processor
clock frequency; otherwise, the bus clock frequency is 1/4 the processor clock frequency. The
value of this bit is determined by hardware at
reset, and cannot be altered by software (see Section 8.10).

H1 Wait Count (M1'W) specifies the number of
wait states automatically inserted by the CPU for
references to M1'
If the value is 0, no wait
states are inserted. If the value is n)O, then n
wait states are automatically inserted for memory
read and n-1 wait states are inserted for memory
write.

EPlI Overlap Hode (EPlIO) and another field in an
EPU control register control the degree of overlap
for CPU and EPU operations. While this bit is 1,
overlap is enabled; otherwise, overlap is disabled. While overlap is disabled, the EPU can use
the signal ~ to stop the CPU from processing
instructions.
There are several degrees of
overlap that affect performance, system debugging
and recovery from exceptions.
Refer to Section
8.8.4 for more information.

MO Wait Count (MO.W) specifies the number of
wait states automatically inserted by the CPU for
references to MO'
If the value is 0, no wail
states are inserted. If the value is n)O, n wait
states are automatically inserted for memory read
and n-1 wait states are inserted for memory write.
Data Path Width ("O.OP) specifies the data
path width for references to MO' While this bit
is 1, the data path width for MO is 16 bits;
otherwise, the data path width for MO is 32 bits.

H1 Data Path Width (M1'OP) specifies the data
path width for references to M1' While this bit
is 1, the data path width for M1 is 16 bits;
otherwise, the data path width for M1 is 32 bits.
1/00 Wait Count (I/OO'W) specifies the number
(0-7) of wait states automatically inserted by the
CPU for references to 1/00'
1/01 Wait Count (1/01'W) specifies the number
(0-7) of wait states automatically inserted by the
CPU for references to 1/01'
Interrupt Acknowledge Wait Count 1 (IACK.W1) specifies the number (0-7) of wait states automatically inserted by the CPU before 1)5 falls during
interrupt acknowledge transactions.
Interrupt Acknowledge Wait Count Z (IACK.WZ) specifies the number (0-7) of wait states automatically inserted by the CPU before 1)5 rises during
interrupt acknowledge transactions.

8225-022

Mini_un Address Strobe Rate (MASH) controls an
option that ensures an Address Strobe is generated
at least once every 16 bus clock cycles. While
this bit is 1, the option is enabled; otherwise,
the option is disabled. While the MASR option is
enabled and the CPU has neither performed any
transactions, granted the local bus, nor requested
a global bus for 16 bus cycles, the CPU performs
an internal operation or halt transaction. If the
CPU is in halted state, a halt transaction is performed; otherwise, an internal operation transaction is performed. This function can be used for
refreshing pseudostatic RAMs.
Also, some Z-8US
peripherals require Address Strobe to generate
interrupt request timing.
Global Enable (GE) and Local Address (LAD) control the use of the global bus request protocol.
Wh.ile GE is 1, the protocol is enabled; otherwise, the protocol is dlsabled.
The LAD field
selects 1 of 16 sectIons of the physical address
spaces used for references to the local bus;
references to other sections use the global bus.
See Section 8.9 for more informatIon.

8-5

External Interface
In systems that combine memories with different
widths, an individusl operand must be located
entirely within physical memory modules of a
single width.
Thus if an operand is located
acrosa consecutive logical pages, including
operands for ENTER, EXIT, lDM, lDMl, and EPA
instructions that may occupy several longwords,
then the two physical frames containing the
operand must both be in 16-bit memory modules or
3Z-bit memory modules.

8.7 8US T1MIfG

The CPU psrforms trsnsactiona on the external
intsrface to trsnsfsr data for fetching instructions,
fetching and storing operands,
processing exceptions, and performing memory
management.
In addition, the CPU performs
internal operation and hslt transactions, which do
not transfer dats. Each transaction occurs during

a sequence of bus clock cycles, named T1' TZ, etc.
The CPU has a single clock line, ClK, used to generate all timing.
Internally, the CPU derives
another clock for bus timing by dividing CLK by.Z
or 4. The scale factor for bus timing (Z or 4) is
selected at reset. In the AC timing characteristics for the CPU (available in a separate data
sheet from Zilogl, input setup and hold times and
output delays are specified with respect to a rising edge of ClK.
When CPU output transitions
occur on different rising clock edges, the time
between the transitions is specified in terms of s
constant delay and a variable number of ClK
cycles. The number of ClK cycles dependa on the
bus timing scale factor, type of transaction, and
number of wait states.
In the logical timing diagrams that follow, the
signal transitions on the bus are shown in relation to the bus clock, BClK. The beginning of a
transaction, signified by a fslling edge of g,

CLK

BCLK

===:x

ADDRESS

}- -

(A) ICLK = CLK

DATA IN } - -

CLK

BLCK

.-J
==:J--------------<\,__

A_DD_R_E_SS
____

...,>-- - - - - -

D_A_T_A_IN_ _

\ _________________________-JI
(I) ICLK = CLK

Exa.ple of Mamry Re.t Tilling
Showing Different Bus Scale ractors

Figure 8-5.

8-6

2071'()13

External Inter face
always occurs on a rising edge of BCLK. The BCLK
signal is derived internally to the CPU as described above, and is not available on the pins.
BCLK can also be derived externally by dividing
CLK by the selected bus timing scale factor.
Section 8.10 discusses synchronization of the
internal and external bus clocks.
The timing
diagrams in Figure 8-5 show example memory read
transactions with one wait state using the different scale factors.

8.8

All bus transactions begin with Address Strobe
(m first asserted" and then negated. On the
rising edge of ~, the lines for status (STO-ST3),
Read/Write (R/W), data transfer size (BW/C, BL/W),
and Normal/System (Nm are valid.
The status
lines indicate the type of transaction being
initiated (Table 8-1). The R/W line indicates
the direction of data transfer. The data transfer
size indicates whether a byte, word, or longword
of data is to be transferred.
The N~ line
indicates the CPU's operating mode. The following
sections describe timing for the different
transactions.

Status Codes

ST,-STO

Definitioo

o0
o0
o0
o0
o1
o1
o1
o1

Internal Operation
CPU-EPU (data)
I/O
Halt
CPU-EPU (Instruction)
mIT" Acknowledge
mY" Acknowledge
vr Acknowledge
Cacheable CPU-Memory (Oata)
Non-Cacheable CPU-Memory
(Data)
Cacheable EPU-Memory
Non-Cacheable EPU-Memory
Cacheable CPU-Memory
(Instruction)
Non-Cacheable CPU-Memory
(I nstruction)
Reserved
Interlocked CPU-Memory (Data)

0 0
0
1
1
0
0
1

1
0
1
0
1
0

1 1

1 000

001

o1 0
o1 1
1 0 0

o1
1 1 0

1 1 1

rnr.)

rnr

BUS TRANSACTIONS

Table 8-1.

On the rising edge of ~, the address on the AD
lines is also valid. Addresses are not required
for internal operation, halt, interrupt acknowledge, and CPU-EPU data transactions; the AD
lines are driven but the address is undefined for
those transactions. The CPU uses Data Strobe (~
to time the data transfer.
(Note that internal
operation and halt transactions do not transfer
data, and thus do not assert
For write operations (R/W = Low), the CPU asserts
when valid
data is on the AD lines. For read operations (R/W
= High), the CPU makes the AD lines 3-state before
asserting
so the addressed dev ice can put its
data on the bus. The CPU samples the data in the
middle of a bus cycle while negating

"In the description of bus transactions, the term
"asserted" means an active signal and "negated"
means an inactive signal.
A signal is either
active when High or when Low, as specified in the
pin function list.

rnr.

The AD lines can be used to transfer bytes, words,
or longwords of data. When reading from memory,
the CPU always reads a word or longword, depending
on the memory data path width, regardless of the
size of the information required.
For read
transactions the three cases are handled as
follows:

•
•

Byte transfers use ADO-AD7; AD8-AD31
ignored.
Word transfers use ADO-AD15; AD16-AD31
ignored.
• Longword transfers use ADo-AD31'

are

For write transactions,
handled as follows:

are

•
•
•

the

three

cases

are

Byte transfers replicate the data on ADO-AD7'
AD8-AD15' AD16-AD23, and AD24-AD31'
Word transfers replicate the data on ADO-AD15
and AD16-AD31'
Longword transfers use ADO-AD31'

The Input Enable (1!) and Output Enable (or)
signals can be used to enable buffers on the
bidirectional AD lines. Ir is asserted when the
buffers are to drive toward the CPU; tit is
asserted when the buffers are to drive away from
the CPU. Whenever the direction for the AD lines
changes, both Ir and tit are negated for at least
one CLK cycle.
To transfer more than one data item, the CPU can
perform burst transactions. The data items are
transferred in the same direction, and are equal
in size.
is used to time each transfer. The
CPU asserts Burst (~ to indicate a burst
transfer.
The responding device asserts Burst
Acknowledge (~ if it is capable of supporting
burst tranfers. If ~ is not asserted, the CPU
transfers only a single data item.

rnr

8-7

External Interface
8.8.1

Response

Any time data is transferred, the responding
device returns a code on the Response lines
(RSPO-RSP1) to indicate ready, wait, bus error, or
bus retry.
The response is sampled at a time
specif1c for each type of transaction, generally
before the AD lines are sampled for reads or OS is
negated for writes, and after automatic wait
states are inserted.
Ready indicates the completion of a successful
transfer.
Wait indicates that the responding device needs
more time to complete the transaction.
The CPU
watts one bus cycle before sampling the response
again to accommodate slow memory or peripherals.
A simple system using only Z-BUS WAIT can be
implemented by connecting wAn to both RSPO and
RSP1·
Bus error indicates that a fatal error has
occurred during the transaction, e.g., bus tImeout
for a nonexistent dev ice.
The CPU treats bus
error as an exception.
Bus retry indicates that the transaction should be
tried again, e.g., a transient parity error was
detected. The CPU negates OS and tries the transaction again.
The CPU can insert wait states automatically under
control of several fields in the Hardware Interface Control register. If an automatic wait state
is programmed for a bus cycle, the CPU ignores the
response and wait is assumed.
Thus, wait states
can be inserted automatically by the CPU or upon
request of the responding device.
It must be
emphasized that the RSPO-RSPl lines are sampled
synchronously. Thus, they must meet the specified
setup and hold times for correct operation.

8.8.2

BCLK

8.8.2.1
Single HeIIory Read and Write Transactions.
Figure B-6 shows timing for a single memory read transaction with no wait states. AS is

=><__

r -®- -C

A_D_D_R_E_SS_--J

v
I
IE

CPU-Memory Transactions

The CPU performs transactions with status 1000,
1001, 1100, 1101, or 1111 to read from and wnte
to memory.
See Appendix C for more information
about the dl fferent status codes.
The transactions involve either a single data transfer or
multiple, burst data transfers.

B-B

asserted during the first half of Tl. The rising
edge of AS lndlcates that the address on ADO-AD31
and control signals STO-ST3' R/W, BW/L, BL/W, and
N/S are valid.
The control signals remain valid
for the duratlon of the transaction.
!iR5T is
negated during the transaction because only a single data item is transferred. At the beginning of
T2, the CPU stops driving the address, asserts 05,
and prepares to receive data from memory. In the
middle of T2, RSPO-RSPl are sampled ready, the
input data is latched, and DS is negated.
The
signal OE is asserted during Tl; however, for twocycle read transactions, IT is not asserted. rr
lS unasserted because there is no bus clock transition between the negation of DE at the end of Tl
and the sampling of data in the middle of T2. The
two-cycle read transactlon is a compatible
extension of the Z-BUS three-cycle read transactlon.
Two-cycle read transactions are intended
for use with fast memories connected dlrectly to
the CPU pins without buffers, such as an external
cache.

STo·STa
NIS
BW/L,BUW

)(

._ _ _ _ _ _ _ _ _ _ _ _ _~.

\
*RSPo-RSP1 and data sampled.

Figure 8-6.

Single Memory Read TDing

2071-014

External Interface
The CPU can insert wait states in the middle of T2
If RSP O-RSP1 are sampled wait or if automatic wait
states are programmed in the appropriate field of
HICR.
The duration of a wait state is one BCLK
cycle.

for a 32-bil: data path, or the aligned word
addressed by AD1-AD31 (ignoring ADD) for a 16-bit
data path.
The CPU selects the required bytes
from the transferred word or longword.
A single memory write transaction (Figure B-B)
begins with ~ to indicate that address and control signals are valid. At the beginning of T2
the CPU stops driving the address and starts drlv.1ng the data.
In the middle of T2, OS is
asserted.
The CPU negates OS in the mIddle of
T3. ij[ is asserted beginning at T1 and continues
for the duration of the transaction. The CPU samples RSPO-RSP1 in the middle of T3.

The timing for a single memory read transaction
with one wait state is shown in Figure B-7. This
is not a true wait state because the CPU asserts
"IT" in the middle of T2 and continues untll the
middle of T3. For memory read transactions longer
than two bus cycles, either because of wait states
or burst transfers, Ir is asserted from the middle
of T2 until the end of data transfer. The signals
~ and Ircan be used to control buffers on the AD
lines.

For memory write transactions, the data transfer
size is less than or equal to the data path width
specified in HICR. Bytes and words can be written
to a 16-bit memory; bytes, words, and longwords
can be written to a 32-bit memory. The CPU writes
bytes to any address, but words and longwords are

For memory read transactions, the data transfer
size is equal to the data path width specified in
HICR.
The memory should transfer the aligned
longword addressed by AD2-AD31 (ignored ADO-AD1)

BCLK

=::J(

ADDRESS

_ _ _ _- 1

/
\~_...J

STO- ST3

MIS
Bwii:, BL/V!

.~____________________________________

BRSTA

*RSPo-RSP1 and data sampled.

Figure 8-7.
Single Memory Read Timing (One Wait State)

2071-015

B-9

External Interface
always written to an aligned address; that is,
words are always written to an even address and
longwords are always written to an address that is
a multiple of four. When a program writes a word
or longword to an unaligned address, the CPU performs two or more wri te transactions to aligned
addresses. For example, if the program writes s
word to an odd address, the CPU first writes the
more significsnt byte to the odd address, then it
writes the less significant byte to the successive
even address.
Singla memory read and write timing are slightly
different from Z-BUS specifications. The minimum
read transaction is two bus cycles, and the
rasponse is sampled at the end of the data transfer. For the Z-BUS, the minimum read transaction
is three cycles, and the response is sampled one
cycle before the end of the data transfer. For
atrict Z-BUS compatibility it is possible to program one automatic wait state for memory read and
to delay the response using an external flipflop.

8.8.2.2
Burst MeIIIory Read and Write TransacBurst memory transactions use multiple
tions.
Data Strobes following a single Address Strobe to
transfer data at consecutive memory addresses.
The IMrr and ~ signals control the burst
transaction. The CPU uses burst transactions to
pre fetch the cache block for a cache miss on an
instruction fetch. The CPU slso uses burst transactions to fetch or store operands when more than
one transfer ia necessary, as with unaligned operands, string instructions, load Multiple instructions, and loading of Program Status.
I f the memor y does not support burst trans fers,
the burst transfer protocol described below
(Figure 8-9) allows ~ to be tied High. The
CPU then separates the burst transaction into a
sequence of single transfers, but only a single
transfer is performed for a cache miss on an
instruction fetch.

BCLK

==:x:

ADDRESS

XI._____

D_A_T_A_O_U_T_ _ _ _ _

\,--_......,f

STo-ST3
NIS
BW/L, BLli!

==:x:

•_________________________________.

RiW~

*RSPO-RSP1 sampled.

Figure 8-8.
8-10

Single Me.ory Write Ti_ing
2071'()16

External Interface
CPU or memory. If memory terminates the transfer
by neg at ing tiIiSTA, the CPU responds by negating
~ when [is" is negated.
(See the example for
burst memory read.) I f the CPU terminates the
transfer by negating mrsT before the falling edge
of ~, memory responds by negating~.
(See
the example for burst memory write.) The CPU terminates the burst transaction when all the
required data .items have been transferred or after
reaching the end of an aligned, 16-byte block.
figure B-10 shows timing for a burst memory read
transaction with one wait state. In this example,
three data items are transferred, after which memory terminates the burst. 'mrST is asserted at the
beginning of T1; otherwise, the timing for the
first transfer is identical to a single memory
read.
In the middle of n, the CPU samples
RSPO-RSP1 ready, latches the data, and samples
~ active.
During T4 the second data item is
transferred, accompanied by~. The time for the
second and subsequent transfers can be extended
with wait states i f RSPO-RSP1 are sampled wait;
the CPU inserts automatic wait states only for the
first transfer. During T5 the third data item is
transferred.
At the same time RSP O-RSP1 are
sampled ready, the data is latched and ~ is
sampled inactive. Memory terminated the burst transfer, and the CPU responds by negating mrsT.

At the beginning of a burst trsnssction, the CPU
asserts ~ along with other control signals. If
the CPU continues to assert mrsT when [is" falls,
this indicates to memory that the CPU can support
another data transfer following the one in
process. If the CPU negates ~ before ~ falls,
this indicates to memory that the current transfer
is the last in the transaction.

Figure B-11 shows timing for a burst memory write
transaction with no wait states. In this example,
two data items are transferred, and the CPU terminates the burst. mrsT is asserted at the beginning of T1; otherwise, the timing for the first
transfer is identical to a single memory write.
In the middle of n, the CPU samples RSPO-RSP1
ready and ~ active. At the beginning of T4,
the CPU negates mrsT, indicating that one more
data transfer will follow. During T4, the second
data item is transferred, accompanied by~. The
time for the second and subsequent transfers can
be extended with wait states if RSPO-RSP1 are sampled wait; the CPU inserts automatic wait states
only for the first transfer. Memory recognizes
that the CPU has terminated the burst transfer,
and responds by negating mTA before the end of
T4. Note that a memory system can be designed to
support burst transfers only for read transactions
through selective enabling of ~.

When ~ is asserted at the time the RSPO-RSP1
lines are sampled ready, this indicates to the CPU
that memory can support another data transfer following the one in process. When ~ is negated
at the time the RSPO-RSP1 lines are sampled ready,
this indicates to the CPU that the current data
transfer is the last in the transaction.
The
burst transaction can be term~nated by either the

8.8.2.'
Interlocked tte.lry Tr_actioos.
In
tightly-coupled multlprocessor configurations, the
CPU must at certain times inhibit other bus masters from referring to shared memory while the CPU
performs two or more interlocked transactions.
The CPU uses interlock protection for data references asaociated with Test and Set, Decrement

Figure 8-9.

2071'()17

Burst Transfer Protocol

B-11

External Interface
3 DATA TRANSFERS, MEMORY TERMINATES BURST

BCLK

==x:

ADDRESS

DATA IN

X,-_D_AT_A_IN_..J>-

--C

\.L-_....II

DE _ _ _

\~--------------~
STO-SIJ.=:X

BwiL", BLly!

NIS
BRST

,~------------------------------------------------------~~____________________________________________________-..J

\~------------~~--------~----~
·RSPo-RSP1,

iFiSTA, and data sampled.
Figure 8-10.

8urst Memory Read Ti.ing (One Wait State)

Interlocked, and Increment Interlocked instructions. The CPU also uses interlock protection for
references to address translation table entries
when loading the Translation Lookaside Buffer.
The CPU indicates interlocked protection for a
sequence of memory references by using status 1111
for any of the memory transactions previously
described. While the CPU indicates status 1111,
the memory system must prevent interlocked references to shared memory by other processors. During a sequence of interlocked memory tranaactions,
the CPU does not acknowledge local bus requests
nor does the CPU generate any bus transactions
with status other than 1111.

B-12

8.8.' Input/Output Transactions
The CPU uses status 0010 to read from and write to
I/O ports. I/O transactions are generated for I/O
instructions and, when address translation is
enabled, by data references to pages with bit 31
of the page table entry set to 1.
The timing for I/O and memory transactions 1S very
similar. The major difference is that DS falls in
the middle of T2 for I/O read timing, compared to
the beginning of T2 for memory read timing. This
allows peripheral dev ices more time for address
decoding.
Another d~ fference is that the data

2071-018

External Interface
2 DATA TRANSFERS, CPU TERMINATES BURST

2-I-

I -T1 - I -T

T3 - I - T "

BCLK

~~__A_DD_R_E_S_S__-,)(~__________D_A_TA__O_UT__________J)(~___D_A_TA__O_UT____~

STo-ST.
HIS
BWIL,BUW

,_________________________________________________,

\ ......_ _ _-.l.\----'/~_ __J7
*RSPo-RSP1. BRSTA sampled.

rigure 8-11.

Burst

trsnsfer size (byte, word, or longword) for I/O
transactions is specified by the instruction, not
by HICR.
The final difference is that the CPU
does not support burst I/O transactions.
Figure
8-12 shows timing for an I/O read transaction.
I/O write timing is the same as a single memory
write (Figure 8-8).

8.8.4 EPU Transactions

The CPU and EPU cooperate in the execution of EPA
instructions (Figure 8-13). When the CPU encounters an EPA instruction and the EPA bit in FCW is
1, the CPU broadcasts the first two words of the

2071-019

~ry

Write Ti.ing

instruction to the EPUs in the system using the
CPU-EPU instruction transfer transaction.
All
EPUs in the system recognize the transaction, but
only one of four possible EPUs is selected by bits
16 and 17 of the EPU instruction. The CPU also
transfers the PC value for the instruction, which
the selected EPU saves for use in exception handling. If data transfers are required to complete
the instruction, the CPU controls the data transfer transactions while the EPU drives or receives
the data.
The ~ signal, output from the EPU, is used to
synchronize the CPU and EPU in executing EPA
instructions. (When multiple EPUs are present in

8-U

External Interface

8eLK

==x

ADDRESS

}- -

DATA IN } - -

-C

I
\_---

STo-STa
NI.
8Wlr,8UW

Xr------------------

________________________________

*RSPo-RSP1 and data •• mpled.

Figure 8-12.

a system, the EJSDm input to the CPU must be
driven by an external AND gate whose inputs are
the EJSDm signals from the EPUs). The CPU must
sample EJSDm inactive before inItisting sn EPU
instruction transfer.
If data transfers are
required, the CPU must ssmple EJSDm inactive
bsfore initisting the first transfer.
While the CPU samples EJSDm active, no transactions are initiated; however, the CPU may grant
the locsl bus.

8-14

I/O Read Ti_ing

EJSDm is also used to control the degree of overIsp between CPU and EPU instruction execution.
Ordinsrily, the CPU can continue processing other
instructiona after performing the data transfers
associated with sn EPA instruction and before the
EPU has completed executing the instruction. To
simplify debugging snd recovery from exceptions,
overlap can be disabled under control of the EPUD
blt in HICR. When overlap is disabled (EPUO = D),
the CPU samples EJSDm in the middle of the bus

2071-020

External Interface

YES

Fi!J.Ire 8-13.

EPA Instruction Processing

cycle during which the last data transfer for an
EPA instruction occurs.
If E'J5IJ'!lSV is asserted,
the CPU ceases processing instructions or interrupts until ~ is sampled inactive in the middle of a bus cycle. When overlap is enabled (EPUO
= 1), the CPU does not sample ~ after the
last data transfer, but only samples ~ before
initiating the next EPU instruction transfer.
While processing an EPA instruction and after the
instruction has been transferred to the selected
EPU, the CPU may detect an address translation
exception.
In such an event, the CPU asserts
EPOABORT, informing the selected EPU to abort
execution of the instruction; at all other times,
the CPU negates EPOABORT. The CPU then saves the
address of the suspended EPA instruction on the
system stack during exception processing.

2071-021

When CPU and EPU instruction processing over lap,
the CPU may complete all data transfers for an EPA
instruction (the queued instruction) before the
EPU completes execution of a previous EPA
instruction. If the EPU then detects an exception
during execution of the previous instruction, the
EPU does not execute the queued instruction. In
such a case, the address of the queued instruction
is in an EPU control register, and the CPU saves
the address of a subsequent instruction on the
system stack.
To simplify system hardware, the CPU and EPU AD
lines should be wired together with no buffers
between them.
I f the AD lines are separated by
buffers, external circuitry must generate
and
timing for CPU-EPU data read and EPU-memory
write transactions.

8-15

Externel Interface

tEPUBSY IImpled. _ _
·RSPo-RSP1 'Impled; EPUBSY 'Impled If EPU Intemll operation.

Figure 8-1 ••
CPII-EPU Instruction Tr_fer Tilling
8.8 ••• 1

CPU-EPU

Instructioo

Tr..actiona.

Figure B-14 shows timing for a CPU-EPU instruction
transfer transaction with status 0100. The rising
edge of ~ indicates that the AD lines and status
are valid. During T1, the AD lines sre used to
transfer the opcode, i.e., the first two words of
the EPA instruction. At the beginning of T2 the
CPU stops driving the opcode, asserts ~, and
starts driving PC on the AD lines. In the middle
of T2, the CPU samples RSPO-RSP1 ready and negates
~. The data transfer size for the transaction is
longword.

B-16

The duration of a CPU-EPU instruction or data
transfer can be extended with wait statea if
RSPO-RSP1 are sampled wait.
The ZB070 APU,
however, does not require wait states, nor does it
drive RSPO-RSP1' Systems using the ZB070 APU must
enaure that RSPO-RSP1 are both High, indicating
ready, during CPU-EPU instruction and dats
transections.

2071-022

External Interface

...JX. .__

....._ _ _D_A_T_A_IN
___

D_A_T_A_I_N_...I}- -

-C

'---_______________________________K

fEPUBSY sampled.
-RSPo-RSP1 and data sampled.

Figure 8-15.

CPU-EPU Data Read Tilling

CPU-EPU Data Transactions.
Transactions
to transfer data between the CPU and EPU use
status 0001. The EPA instruction opcode indicates
the number of words transferred.
One or more
longwords of data are transferred until all words
If the last transfer
have been transferred.
contains a single word, the data is on AD16-AD31.
The CPU does not assert !iR'ST and ignores ti1i'Sfi\.
8.8.4.2

Figure B-15 shows timing for a CPU-EPU data read
transaction. This example has two data transfers;
any number of data transfers between one and eight

2071·023

is possible. The rising edge of ~ indicates that
status and control signals are valid.
The CPU
stops driving the AD lines at the end of T1; the
EPU begins driving them in the middle of T2. At
the beginning of n, the CPU asserts~. In the
middle of T3 the CPU samples RSPO-RSP1 ready,
latches the data, and negates~.
The second
longword of data is transferred during T4. After
the last data transfer the CPU inserts an idle bus
cycle (T5 in the example) during which neither the
CPU nor EPU drive the AD lines.

B-17

External Interface

BCLK

AD _ _ _ _ _ _ _ _ _.J

UNDEFINED

DATA OUT

------'

\
7

R/W

S~o-S!1----------------~

BW/L,BUW
NIB _ _ _ _ _ _ _ _

7
7
tEPUBSY .ampled.

*RSPo-RSP1 'Impled.

Figure 8-16.

CPU-EPU Data Write Tiaing

Figure 8-16 ahows timing for a CPU-EPU data write
tranaaction. This example has three data transfers; any number of data transfers between one and
eight is possible. Timing for the first transfer
is identical to the CPU-EPU instruction transfer
transaction. A second longword of data is transfer red dur ing T3, and the third longword is transfer red during T4.

8-18

8.8.4.' E~ry Tr_actions. The CPU uses
status 1010 or 1011 for the EPU to read from and
write to memory using flyby transactions.
The
timing is identical for EPU-memory read and
CPU-memory read. The EPU monitors the CPU timing
on the bus, and uses the two least significant
address bits on the first transfer, the data
transfer size, and the length of the operand from
the instruction to select the bytes it needs from
the AD lines.

2071-1)24

External Interface

~____________E_P_U_D_A_TA__O_UT____________-J)-- - --~

\...
\'------JI
[
[
~

*EPUBSY sampled:

___________________________________________________________K

+ RSPo-RSP1 sampled; EPUBSY sampled If last transaction.

Figure 8-17. EPU-Hemory Single Write Ti_ing
The timing for an [PU-memory write transaction
differs slightly from a CPU-memory write transaction. Two extra bus cycles sre included to pass
the AD lines from CPU to [PU sfter the sddress
transfer and from [PU back to CPU after the last
data transfer. Figure 8-17 shows an example for a
single [PU-memory write transaction with no wait
states. The CPU stops driving the AD lines at the
end of T1; the [PU begins driving them in the middle of T2. l5S is asserted in the middle of T3,
one bus cycle later than for CPU-memory write

2071-025

timing. The CPU negates l5S in the middle of T4.
The CPU can insert wait states in the middle of
T4. The [PU continues to drive the AD 11nes until
the end of T4. After the last data transfer the
CPU inserts an idle bus cycle (T5 in the example)
during which neither the CPU nor [PU drive the AD
lines.
[PU-memory burst write transactions are
similarly extended by two bus cycles more than
CPU-memory burst write timing.
One cycle is
inserted before the first data transfer, and
another after the last data transfer.

8-19

External Interface

VI,

NYI \

INTERNAL
NMI LATCH

.._ _ _ _ _ _ _ _ __

\'----~"r
AD

r--(I-_____

UNDEFINED

\ ....._--

I
\

...... _ _- J

R/WJ
STO-S'!J.==X

NIS
BW/L, BUV!

_____________________________-.J

• RSPo-RSP1 sampled.

+ RSPo-RSP1 and data sampled.

Figure 8-18.

Interrupt RecplSt/Acknowledge Tilling

8.8.5 Interrupt Request and Acknowledge

The CPU recognizes vectored, nonvectored, and nonrequests.
The decreasing
maskable interrupt
order of priority for interrupts is nonmaskable,
vectored, and nonvectored. ~ is edge sensitive;
when RRr is asserted, an internal latch is
loaded. vr and NVr are level sensitive.
The CPU samples vr, NVr, and the internal ~
latch on the rising edge of ClK. The interrupt
request signals can be asynchronous to ClK; the
CPU synchronIzes them internally.
8-20

After a request for an enabled interrupt is
asserted, the CPU begins an interrupt acknowledge
transaction.
figure 8-18 shows timing for an
interrupt acknowledge transaction, indicated by
status 0101, 0110, or 0111. The timing is similar
to a single I/O read. Wait states (either programmed for automatic insertion or externally generated) can be inserted before [)S" falls in the
middle of T2, and before [)S" rises in the middle of
T3. Inserting wait states before [)S" falls allows
for delay in the interrupt priority daisy chain.

2071-026

External Interface
A word of data is transferred on ADo-AD15' All of
the interrupts save the transferred word on
the system stack for processing the interrupt.
Vectored interrupt uses the low-order byte of the
word to select a unique PC value from the Program
Status Area.

B.B.6 Internal Operatioo InI Halt Tr_-=tioos
Figure 8-19 showa hming for internal operat ion
(atatus = 0000) and halt (status = 0011)
transactions. Unlike other bus transactions, data
is not transferred during these operations.
Nevertheless, the data transfer size for the
transaction indicates longword.
The duration of
the transaction is two bus cycles.

BeLl(

~__................U_N_D_EF_I_N_ED...................~

The CPU generatas an internal operation transaction after the end of a sequence of interlocked
memory transactions.
The CPU generates a halt
trensaction upon entering halted state (Section
7.2). When the Minimum Address Strobe Rate option
is enabled (the MASR bit in HICR is 1), the CPU
maintains a steady rate for Address Strobes by
generating halt traneactions in halted state or
internal operation transactions otherwise.

B.B.7

Bus Ratry

During transactions in which data is transferred,
the responding device can ind.icate bus retry on
RSPO-RSP1 •
When bus retry is sampled, the CPU
terminates the transaction in progre.ss, negating
g and BRS"f, then repeats the same tranaaction.
If bua retry ia indicated during a burat tranafer,
the retry transactIon begins with the address for
the data transfer where bus retry was indicated.
The CPU does not acknowledge interrupts or bus
requests between the retry response and the retry
transaction.

8.B.B Bus Error

c
'C

ITO-I!!

BwiL", B'i!,l

J<................................................_V" ---

During transactions in which data is transferred,
the responding device can indicate a bus error
exception on RSPo-RSP1'
When bus error is sampled, the CPU terminates the transaction in progreaa, negating g and ~. A bus error exception also causes termination of the instruction in
execution. In processing a bus error exception,
the CPU savea the Program Statua, physical address
for the transaction, and a word identifying the
status and control aignals used for the transaction on the system stack, in that order (Figure
8-20). In the identifier word, High aignals are
1, and Low signals are O.
16

'C
Fi9lrB B-ZO.

Bus Error Identifier Word

Figure B-19.
Internal Operatioo InI Halt Tilling

2071-027,8225-023

8-21

External Interface
8.9

BUS REQt£ST AN) ACKNOILEDGE

The CPU can initiate transactions with devicea
located on a global bus shared with other CPUs.
At any time, only one of the CPUs can initiate
transactions on the global bus.
Control of the
global bus is arbitrated by external circuitry.
Before initiating tranaactions on the global bua,
the CPU requeats control of the global bus from
the arbiter using the protocol described below.

The CPU supports two types of bus request/
acknowledge sequences, local and global.
Other
bus masters request the local bus from the CPU
using a handshake of ~ snd~. The CPU
requests a global bus from an external arbiter
using a handshake of ~ and Gm".
To generate transactions on the local bus, a
potential bus master (such as a DMA controller>
must gain control of the bus by making a bus
request (Figure B-21>.
A local bus request is
initiated by asserting~.
Several bus
requestors may be
wired to the ~ signal;
priorities are resolved externally to the CPU,
usually by a priority daisy chain.

The CPU uses two fielda of HICR to distinguish
between local and global bus transactions. The GE
bit enables uae of the global bus. The 4-bit lAD
field specifies one of sixteen sections of the
physical address space uaed for local references.

The CPU samples ~ on the rlslng edge of elK.
can be asynchronous to ClK; the CPU
synchronizes it internally.
After ~ is
asserted, the CPU completes any transaction or
sequence of interlocked transactions in progress,
including possible retries.
Next, the CPU
responds by asserting ~ and placing its
other output signals except EPUABORT in 3-state.
The EPUABORT signal remains valid while the CPU
has granted the local bus, and may be asserted if
an EPA inatruction is in progress.
later, when
~ is negated, the CPU negates '!iirnAEI< and
begins driving all other output signals.

Before every memory and I/O bus transsction
(status codes 0010 and 1000 through 1111), the CPU
compares the lAD field with bits 26 to 29 of the
physical address.
If the comparison is unequal
and GE is 1, then the transaction is a global bus
reference; otherwise the transaction is a local
bus reference.
In a tightly-coupled multiprocessor aystem (Figure B-2c), each of the local
and global memory locations and peripheral ports
can have a unique system address. Each CPU loads
a distinct value into lAD, identifying its local
addresses; the CPUs refer to global addresses and
local addresses of other CPUs using the global bua
request protocol.

J)~'------~~~______________~

BUSACK

AS, OS,
BRST, GiiEQ

________

DE, ii

}-------:fr-----'~

~.~~----J

7 ----"

>
-------------1/

STO-ST3 _____________~-:

BW~W~~~

hF------ilt-f

\.------

..,r--- - -,~

)-_____ -:fr _ -----f~

5:1,..------...#

Figure 8-21.
local Bus Request Acknowledge Ti_ing

B-22

2071.()28

External Interface
figure B-22 shows timing for the global bus
request/ acknowledge protocol. Before init iat ing a
transaction on the global bus, the CPU drives the
address, STO-ST3' mtrr, R/W, N~, BL/W, and BW!L
valtd at the beginning of a bus cycle. Then, in
the m.iddle of the bus cycle, the CPU asserts
~. When the global bus selected by the address
is available to the CPU, the arbiter asserts

ITAEK.

The CPU samples ~ on the rislng edge of
eLK.
ITAEK can be asynchronous to CLK; the CPU
synchronizes it internally. The CPU performs one
or more transactions on the global bus, then
negates GTltQ.
The arbiter responds by negating
'GACl(; the CPU can then in it iate more transacti.ons.

;;

OE\
STo-S!i.
Bwii:. BL/I!
NIS

;

)

8.-

;;

;

)

);

:'J

-IJ

f'i;
;;

,..:
;;

);

:=x
,

BRST

BRSTA

Figure 8-22.

2071'()29

Global Bus Request Timing

B-23

External Interface
waiting for mJ( in state 2.
If BliS'RE[ is
asserted before mJ(, the CPU relinquishes the
globs I bus without performing any transactions.

Figure 8-23 shows a state diagram for the local
and global bus request protocols.
To prevent
deadlock between CPUs referring to esch other I s
local memories, s CPU can be preempted while it is

STATE 0

=
=

ClREQ
H
BUSACK
H
BUS = 2ST

(BUSREQ • L).
(ClACK. H)
A

l:!.ClACK

STATE 1

= H).

ERROR
STATE 2

ClREQ
3ST
BUSACK = L
BUS - 3ST

D
BUSREQ

(BUSREQ
H).(ClACK
(NEED_GBUS
H)

(GACK

ClREQ = L
BUSACK = H
BUS = 2ST

L).(BUSREQ

STATE 3

= H)

(ClACK = L).
(BUSREQ = L)

STATE 4
ClREQ = L
BUSACK = H
BUS
2ST

~!OACK -

GREQ = H
BUSACK = H
BUS
2ST

H
(GACK = L).
[(BUSREQ = L)
+(NEED_ClBUS

= L)]
I

GACK

ERROR

NOTES: Inte"ace algnalo are High (H), Low (L), High or Low (2S1), or 3·otalod (3ST).
NEED_GBUS Is an ocllve High olgnal Intomal to the CPU.

Figure 8-23.

State Diagr_ for CPU Bus

Reqwst Protocol

8-24

2071-030

External Interface
State legend

State 0

The CPU controls the local bus and is
neither requesting nor controlling the
global bus.

Transition legend
A

A local bus request occurs.

The global bus arbiter grants control of
the global bus when no global bus
request is pending. This is an error.
The CPU remains in State O.

The CPU requests the global bus in
response to the internally generated
signal NEEO_GBUS.

The CPU controls the local bus and is
requesting the global bus.

The local bus master relinquishes the
bus.

The CPU cannot perform transactions.

The global bus arbiter grants the global
bus to the CPU while no local bus
request is pending.

The global bus arbiter grants the global
bus to the CPU while a local bus request
is pending. The CPU is preempted.

The global bus arbiter
bal bus before the CPU
global bus.
This is
CPU's response to
undefined.

The CPU relinquishes control of the global bus when it no longer needs the global bus or in response to a local bus
request.

The CPU can perform transactions on the
local bus.
State 1

The CPU has granted the local bus.
The CPU cannot perform transactions.

State 2

State 3

The CPU controls the local and global
buses.
The CPU can perform transactions on the
global bus.

State 4

The CPU controls the local bus and is
relinquishing control of the global bus.
The CPU cannot perform transactions.

reclaims the glorelinquishes the
an error.
The
this error
is

The global bus arbiter reclaims the global bus.

B-25

External Interface
8.10

RESET

Figure 8-24 shows Reset timing.
After ~ is
asserted, the CPU responds as follows.
•

AD lines are turned to input direction

•

~,~,~,~,

•
•
•

negated
STO-ST3 are driven to 1111
BW!L and Bl/W are driven low
N~ andR/W are undefined

or- are

EPOABOR1, rn!E'Q', 'It, and

If ~ is
~, the

asserted while the CPU is asserting
CPU first
negates~, then the
other CPU output lines are removed from 3-state
and driven aa described above.
After I!£'SET is
asserted, external circuitry can detect that the
CPU has responded to the reset request by sensing
BW!L and Bl/W low. At power on, I!£'SET should be
asserted until after power has stabilized.

During reset, bits SX, NX, CI, and CD of the SCCl
control register are cleared, disabling the
address translation and cache mechanisms. Bit GE
of HICR is also cleared, disabling the global bus
request protocol.

8-26

At the rising edge of I!£'SET, the relationship
between bus timing, memory data path, and number
of automatic wait atates is determined. If RSPO
is High at the rising edge of I!£'SET, HICR is
initialized with MD.DP = 1 t MO' W = 7, and S = 1.
This corresponds to a default configuration of
16-bit memory path, seven automatic wait states,
and bus clock scale factor 2. If RSPO is low at
the rising edge of I!£'SET, ADO-AD3 and AD11 are
latched into the corresponding bits of HICR, and
AD15 must be High.

I!£'SET need not be synchronous with elK; however,
the CPU assumes that the last rising edge of ClK
on which I!£'SET is asserted corresponds to a rising
edge of BClK. Thus, if I!£'SET is synchronized with
the rising edge of the external bus clock, the
internal and external bus clocks will be in phase
with respect to ClK. After REm- is negated, the
CPU resds FCW from memory address 2 and PC from
address 4 using status 1101. If ~ is asserted
before I!£'SET is negated, the CPU acknowledges the
bus request before fetching the Program Status.

External Interface

CLK~
BCLK~
RESET

RSPo

'------7,~----------------------------------7~-----------J

----------~hF'----------------------------------{~------~

--------~h~'--------------------------~r------J

)

:
:

- - --f'r{
------{~--~r-------~~----_7~------~
"
)

ADDRESS = 2

' \.....J

)

'",,"
)

)

'--

------~~---7~--------------~~------------~h~'----)

R/W

;'1

Mis

s'l

:,
:~~\~---------------~fl------------~" r==
c=
:
ALL HIGH

STo-ST3

BwiL,
BLfW

11~101

BRST

EPUABORT

::J

----------~o-----~---------------------------;,hF--------------------_i.f;F'-------J

Figure 8-24.

2071-031

Reset Timing

8-27

AppeDdixA.
Z8OO0 Compatibility
The zao,ooo CPU is an upward-compatible extension
of zaooo architecture and bus interface. All zaooo
normal mode software and most zaooo system mode
aoftware executes on the zao,ooo CPU, prov1ded
the software containa no timing dependenciea, does
not modi fy itself, and does not use any of the
zaooo reserved instruction, address, and control
field encodings.
A few of the zaooo privileged instructions ara not
implemented by the zao,ooo CPU. The instructions
are LDCTL (refresh control register), the Mult iMIcro set (MalT, MREQ, MRES, MSET), and the
Special I/O inatruction set (SIN, SINB, SIND,
SINDB, SINDR, SINDRB, SINI, SINIB, SINIR, SINIRB,
SOTDR, SOTDRB, SOTIR, SOTIRB, SOUT, SOUTB, SOUTD,
SOUTDB, SOUTI, and SOUTIB).
An Unimplemented
Instruction trap occurs when a program attempts
to execute one of these instructions.
The portions of a zaooo operating system concerning memory management and initialization of the
Program Status Area (PSA) must be modified to execute on the zao,ooo CPU. The PSA for the zao,ooo
CPU is an extension of the zaooo's PSA, with more
entries for additional exceptions.
Memory management is integrated in the zao,ooo
CPU, while the zaooo CPU implements memory management in peripheral components (Za010 Memory Management Uni t and Za015 Paged Memory Management
Unit). In addition, the zao,ooo CPU does not separate stack and data address spaces as does the
zaooo CPU.
Any inconveniences caused by these

differences can be minimized by following the
gUidelines in the application note "Memory Management and the zao,ooo 32-bit Microprocessor" (Zilog
document number 00-2329-01).
The zao,ooo CPU ia compatible with the signals and
timing of the 16-bit Z-BUS, except for the MultiMicro resource request signals. The global bus
request protocol of the zao,ooo CPU replaces the
Multi-Micro protocol.
The zao,ooo CPU also
improves the Z-BUS sampling of WlITT" and permits
memory read transact ions of two bus cycles duration, though strict Z-BUS compatibUity can be
msintained by programming appropriste fields in
the Hardware Interface Control register.
(For
strict Z-BUS compstibility, HICR fields MQ.DP,
MO.W, M1.DP, M1.W, I/OO.W, and I!01.W are 1;
IACK.W1 is 3; IACK.W2 is 2; and GE is 0.) For the
zao,ooo CPU, EPU-to-memory write transaction timing includes one cycle more than the Z-BUS specification; the additional cyc le prevents a bus
clash between the CPU and EPU.
Aside from the Z-BUS signals and timing described
above,
there are
only
the
following
few
differences between the zao,ooo CPU and zaooo CPU
pin signals. The zao,ooo CPU doea not implement
the zaooo CPU signals R'R'm", mJr, 1IM!Rr, (Za003
and Za004 only), ~ (Za001 only), and mIT" (Za003
only). Additionally, some of the status code
definitions have been changed to accommodate the
cache in the zao,ooo CPU. The zao,ooo CPU does not
aupport refresh transactions.

A-1

Appendix ••
Memory-Mapped 1/0
The CPU's memory management mechanism can map logical memory addresses to physical I/O addresses by
setting bit 31 of a page table entry to 1. Memory-mapped I/O can be used only for references to
the data memory logical address spaces with the
following instructions.

ADO
AND
BIT
CLR
COM
CP (not Immediate)

DEC
EX
INC
LD
NEG
OR

RES
SET
SUB
TEST
TESTA
XOR

Memory-mapped I/O must not be used for instruction
address space references or for data references
with instructions other than those listed above.
I f memory-mapped I/O is used in this prohibited
manner, the CPU may not be able to recover
correctly from an address translation exception
that is detected after the peripheral port has
been accessed, because the state of the peripheral
may have changed. In addition, instructions like
Decrement Inter locked and those for the Extended
Processing Architecture cannot use I/O status on
bus transactions.

B-1

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

i
I
I
I
I
I
I

Appendix C.
Cache Control and
Memory Transactions
The Z80,000 CPU implements e cache mechanism that
keeps copies of frequently used memory locations
on-chip for fast access. The cache mechanism is
selectively enabled for instruction and data
referencea by bita CI and CO in the SCCL register.
The cache replacement algorithm is controlled by the CR bit in the SCCL register. When
the replacement algorithm is enabled, (CR=1), the
cache stores a copy of the moat recently used
memory locations; otherwise, the cache stores a
copy of fixed memory locationa.
The cache contains 16 blocks of storage (Figure
C-1). Each block includes an address tag, which
stores the 28 most-significant bits of the physical memory address corresponding to the block, and
a bit specifying whether the address tag is
valid. Associated with the tsg, the block also
stores eight data words and a bit for each word
specifying whether or not the word contains a
valid copy of the corresponding memory location.
The cache is fully associative, so that any memory
location can be assigned to any block. In all, the
cache provides 256 bytes of data storage.

ADDRESS TAG
CACHE DATA VALIDITY
ASSOCIATIVE
M~--I"I MEMORY
BITS
MEMORY
(lax 128)
(18x B)
(18d8)

TAG
HIT

2B
32
PHYSICAL
ADDRESS

Figure C-1.

DATA

WORD
HIT

ClEhe Org.u.zetion

The Purge Cache (PCACHE) instruction invalidates
all of the address tags and data words.

2071'()10

On memory references for which the cache is
enabled, the cache is examined to determine
whether a copy of the addressed location's contents is stored on-chip. If the cache is not
enabled, the cache is bypsssed. For instruction
fetches (including fetches of operands specified
by Immediate, Relative Address, or Relative Index
addressing mode), the cache is enabled when CI is
set to 1; if memory msnsgement is enabled, the NC
bit of the page table entry must also be O. For
operand fetches, the cache ia enabled when CD is
aet to 1 and the reference is not interlocked
(i.e., not DECI, INCI, and TSET instructions); if
memory management is enabled, the NC bit of the
page table must also be O. For operand stores, the
cache is always enabled. When the CPU fetches from
the Progrsm Status Area during exception
processing or from the translation tables during
address translation, the cache is bypassed.
When the cache is enabled for a reference, bits 4
to 31 of the physical memory address sre compared
to the tags in each cache block. The reference is
called either s "tag hit" if one of the vslid tags
matches the address, or a "tag miss" if none of
the tags matches. When a tag hit occurs, bits 1 to
3 of the address select s data word in the block.
If the data word is valid, the reference is called
a "word hit"; otherwise, it is cslled a "word
miss." For an aligned longword reference, both
the high-order and low-or dar words, along with
their validity bits, sre sccesssd simultaneously.
For instruction fetches, if the reference is s
word hit, the instruction word is simply read from
the csche. If the reference misses and the csche
is enabled for instructions, the instruction word
is fetched from memory using a burst trsnssction.
The CPU continues the burst transaction, reading
successive words as long aa memory acknowledges
the burst or until the end of the block. If the
cache is bypassed, the instruction is fetched
using a single read operation.

C-1

Cache Control and Memory Transactions
For operand fetches, if the reference is a word
hit, the data word is simply read from the cache.
Otherwise, if the reference misses or the cache is
bypassed, the data word is fetched from memory.
Only data fetches that involve more than one
transfer use burst transactions, such as those for
the following instructions: CPI(R), CPSI(R) ,
CHECK, EXIT, INDEX, IRET, LDI(R), LDM, LDML, LDPS,
OUTI (R), TRTI (R)B, and EPA instructions.
Similarly, burst transactions are used for fetching
unaligned operands and longword operands on a
16-bit memory data path.
When an operand is
specified using ReI aU ve Address addressing mode,
the instruction transfer status (11DO or 1101) is
used except for EPA instructions, which use data
transfer status (1010 or 1011).
For operand stores and saving Program Status during exception processing, i f the reference is a
word hit, the data byte or word is written to the
cache; however, the data word is invalidated for
an EPA instruction.
I f the reference is a tag
miss or word miss, the cache is unaffected. The
data is written to memory regardless of whether
the cache hits or misses. This ensures that the
current value for a location is always stored in
memory. The CPU uses burst transactions only for
stores with Load Multiple and Load Multiple
longword registers, Enter, and EPA instructions.
Table C-1 summarizes the activity in the cache and
external interface described above.
The status
codes distinguish cacheable and non-cacheable
references for use with an external cache.
When the CPU fetches from the PSA during exception
processing, a burst transaction wi th status 1101
is used. If the CPU stores to the overflow stack
during exception processing, a transaction with
status 1001 is used. When translation table
entries are fetched or stored (to update the M and
R bits) during address translation, the CPU uses
status 1111.

C-2

In addition to the address tags, data, and
validity bits, the cache contains a stack that
orders the blocks according to how recently they
have been used with the most recently used block
on the top of the stack. Whenever a reference is
a tag hit, the corresponding block moves to the
top of the stack, and the blocks that previous to
the reference had been more recently used move
down the stack. The bottom of the stack identifies
the least recently used (LRU) block.
If the cache replacement algor1thm is enabled, the
contents of the cache change when a cache miss
occurs. For a tag miss, the CPU first replaces the
tag of the LRU block with the missing block's
address, and marks all the data words in the block
1nvalid. For either a tag miss or word miss, the
CPU loads the data fetched from memory into the
selected cache block and marks the corresponding
words valid.
When the cache replacement algorithm is disabled,
copies of fixed memory locat ions can be locked
into the cache for fast, on-chip access. To do
this, the cache .1S first enabled for block
replacement of data references only (CR=1, CD=1,
CI=O). Then the cache is purged and selected
blocks are read into the cache. Afterwards, the
replacement algorithm is disabled, and the cache
is enabled for instruct ion and data references
(CR=O, CD=1, CI=1).
The number of data words per block, number of
blocks, degree of associativity, and replacement
algorithm described for the cache design in this
appendix are specific to the first implementation of the ZBO,OOO CPU architecture and may differ in future products implementing the same
architecture.
Dl fferences in these characteristics can impact on system performance, but have no
effect on the function of software or the external
interface.

Cache Control and Memory Transactions
Table C-l.

Reference

Hit/Miss

Cache and Bus Activity

Cache Activity
Data
lRU

Bus Transaction
(status)

Instruction fetch

Cl°N'C

miss

no change
update

update
update

no
yes (1100)

don't care

no change

yes (1100)

don't care

no change

yes (1101)

hit
miss

no change
update

update
update

no
yes (1000, 1010, or 1100)

don't care

no change

yes (1000, 1010, or 1100)

NCoIlOK

don't care

no change

yes (1001, 1011, or 1101)

IlOK

don't care

no change

yes ( 1111)

hit

update
no change

yes (1000, 1010, or 1100)
yes (1000, 1010, or 1100)

update
no change

yes (1001, 1011, or 1101)
yes (1001, 1011, or 1101)

update
no change

yes ( 1111)
yes (1111)

hit

NC
Operand fetch

Operand Store

miss

NCoIlOK

hit
miss

IlOK

hit
miss

Key:

CD
CI
IlOK
NC

CD in SCCl
CI in SCCl
Interlocked reference required
NC in Page Table Entry

C-3

AppendixD.
Programmer's Quick
Reference Guide
LOWER NIBBLE (HEX), LOWER INSTRUCTION BYTE

EXTEND
INST

EXTEND

ORB

ANDB

AND

XORB

XOR

A -IR

R -IA

R -1M

A -1M

R -1M

R -IR
R -1M

A -IR

A -1M

R _fR
A -1M

ADDL

POP

MULTL

MUll

DIVL

DIV

S••

LDL

CALL

A -IR

IR -IR

R -IR

R -IR
R -1M

A -IR
R -1M

A -IA
A _1M

rlble

IR-R

PC-IR

PUSHL

SUBL

PUSH

LDL

R -IR

IA -IR

R -1M

IR -1M

R -IR
R -1M

IA -IR
IR -1M

R -1M

R -

POPL
IR _IR

R -1M

BIT

INCB

INC

DECB

DEC

EXB

LDB

IA _1M

IR -1M

R-IR

R-lR

IR_R

IR-R

LDA
A - SA
LoAR

LDL
A -SA
LDRL

UNIM

LDL
SA-A
LDRL

LDKL

LDPS
IA

SH
rlbl'
3

INB

OUTB

OUT

rable
3

R-IR

IR-R

R -RA

R-

EXTEND
INST

IA -1M

LDB

LDB
LoRB

LD
SA _A
LOR

AA -R

AA -A

AoDB

LD
A -SA
LDR
A - AA
ADD

R -EAM

SUB
EAM

A -A

ORB

A _EAM

A -EAM

AN DB
R-

EAM

CPL

PUSHL

SUBL
A -EAM

PUSH

LDL

POPL

AoDL

IR -EAM

A -EAM

IA -EAM

R ..... EAM

RESB

RES

SETB

SET

BITB

LDB
R -EAM

R -1M

RA ..... R

R -EAM

A-A

IR -1M

R-

INST

IA -1M

SET

A _A

SUBB

rable

BITB

SETB

IR -1M

A-A

R -EAM

A -1M

A -A

RES

IR -1M

BA -R

R-IR

IR -1M

RESB

R -IR

A -1M

LoRB

A -1M

R -1M

R -IR
R -1M

A-A

R _IR

R -1M

R -RA

S••

SUB
A -lA

R -- BA

()

SH
Table
1

SUBB
A -IR

LDB

w
~

C
CP

ADD
R -IR

CPL

A
CPB

ADDB
A -IA

AND

XORB

A -EAM

R _EAM

POP
IR -

EAM

BIT

XOR
R-

EAM

So.

CPB

R ..... EAM

R -EAM

MULTL

MULT

DIVL

olV

R ..... EAM

R -EAM

INCB

INC

DECB

DEC

R -EAM EAM -1M EAM -1M EAM -1M EAM -1M EAM -1M EAM -1M EAM -1M EAM -1M EAM -1M EAM -1M

S••

rabl,

Tabl,

S••
Table
2

LDL

CALL

EAM-A

PC-EAM

EXB

LDB

R-EAM

EAM-R

EI
DI

S••
Table
7

TRAP

EXTEND
INST.

"a:

Iii

LDB

.
"
e
..
....

;i
w
~

-ex

So.

LDB
-A

LDA

R -EAM

ex -A

LDL

CVT
CVTU

OR
A-A

ANDB
A-A

AND
A -A

XORB
A -A

POPL

ADDL
A-A

POP
R -IR

MULTL
A -A

LDPS

So.

S.
Table
8

Table
7

XOR
A-A

CPB
A-A

CP
A-A

SH
Tabl.
1

S••
Table
1

MULT
A-A

D'VL
A-A

DIV
R-R

S••
rabl.
2

LDCTLL

RET

LoCTLL

CTLRL - A

PC-(SP)

R - CTLRL

DECB

DEC

R -1M

R-IM

EXB
A-A

EX
A-A

TCCB
A

TCC
A

RRDB
A

LDK

RLDB
A

UNIM

R-IM

ADDB
A-A

ADD
A-A

SUBB
A-A

SUB
A-A

ORB
A-A

CPL
R-A

PUSHL

SUIL
A-A

PUSH

IA -A

IR -R

LDL
R-A

R _IR

LDB
A -A

LD
A-A

RESB

RES

SETB

SET

BITB

BIT

INCB

INC

R -1M

R _1M

R -1M

DAB

EXTS
EXTSB
EXTSL
R

S"
rabla

So.

ADCB
R-A

ADC
R-A

SBCB
A-A

SBC
A -A

S••
rable

So.

rable

Tabl.
6

Table
6

S••
Table
6

-ex

LDA

-R

-ex

LDL

rable
7

a:
w

PS -

EAM

a:
w

•

LDB
C

R -1M

PC _RA

CALR

JR
PC -

DJNZ
DBJNZ
PC -RA

Notes:
1) Opcodes marked UNIM are unimplemented and must not be used. Attempting to execute an
unimplemented opcode causes an Ummplemented Instruction trap.

2) The execul!on of an extended Instruction results in an Extended Instruction trap if the EPA bit in
the FCW is 0; otherwise, the CPU sends the instruction to an EPU for execution.

Opcode Hap

D-1

Programmer'a Quick Reference Guide
DC

COMB
IR

COM
IR

COMB

COM
EAM

COMB
R

COM
R

COML

EAM

COML
R

LDCTlB
R-FlGS

SETFLG

lDM

LDM

UNIM

R-IR

R-EAM

EAM

CPB

IR-IM

lA-1M

EAM-IM

R-IM

NEGB
IR
UNIM

NEG
IR

NEGB
EAM

CPL

UNIM

lA-1M

TESTB
IR

EAM

NEGB
R

NEG
R

NEGl
IR

NEGl

'AM

NEGL
R

CPl

UNIM

RESFlG

UNIM

EAM

TESTB
R

TEST
R

ClRL
IR

ClRL

'AM

CLRL
R

UNIM

COMFlG

LDML

LDMl

UNIM

IM-lR
1M-1M

IM-EAM

EAM-IM

TESTB
EAM

TEST

lDB

IR-IM

EAM-IM

TSErB
IR

TSET
IR

TSETB

TSEr

EAM

TSETB
R

TSET
R

t:>

INSRT

IR-R

EAM-A

INSRT
R-R

UNIM

TESTL
IR

TEsn

'AM

TESTL
R

LDM

UNIM

IA-R

EAM-R

a:
UNIM

lDL

UNIM

!.i

lDl

UNIM

NOP

EAM-IA

IR-IM

CLR
IR

ClRB

EAM

ClR
EAM

CLRB
R

CLR
R

UNIM

PUSH
lA-1M

UNIM

lDCTLB
FlGS-R

UNIM

CHKB

CHK

CHKB

R-IM
A-IR

A-1M
R-IA

R-EAM

UNIM

CHKL

UNIM

R-IM

CHK
A-EAM

UNIM

CHKl

UNIM

TESTA
IR

TESTAB

TESTA

EAM

TESTAB
R

TESTA
R

UNIM

D
UNIM

R-IM
R-IA

UNIM

INDEXL
A-1M
R-IR

Table 1.

D-2

INDEX

UNIM

A-EAM

UNIM

INDEXl
A-EAM

Upper Instruction Byte

..
~

Z
a:
w
A

UNIM

A-EAM

TESfAB
IR

INDEX

sf
w

A-IR

UNIM

a:
w

ClRB
IR

!!!

fli
~

w
~

..
Z

TEST
IR

NEG

EXTR

A-IA

A-EAM

EXTR
R-R

EXTRU

R-IR

R-EAM

TESTAL
IR

TESTAL

UNIM

EXTRU
R-R

EAM

TESTAL
R

LDML

lDML

UNIM

lA-1M

EAM-IM

Table 2.

Upper lnal:ructi... Byte

Programmar'a Quick Reference Guide
INIB

31
INI

IR-IA

IR-IR

INIRI

INIR

IR-IA

IA-II~

UNIM

OUTII

OUTI

IA-IA

IR-IA

OTIRI

DTIR

IA_IR

IA-IA

UNIM

INI

A-DA

R-DA

UNIM

RLB

(1 bit)

(I bill
A-1M

A-1M

I.
TRII

IA
CPII

II
CPI

18
CPlL

IA-IA

lA-IF!

IA-fR

IA-IA

UNIM
SLLI

SLL

A-1M

SRLI

SRL

R-IM

A-1M

RLB

UNIM

(2bl\sJ

R_IM

SDLI

SDL

A-1M

RRB

(1 bit)

tiM)

A-1M

UNIM

LDI
IA-IR

IA-IA

LDIR

LDIRL

LDIL

IA-IR

IR-IA

IR-IR

CPBII

CPSI

CPBIL

IR_IR

IA-IA

IR-IA

UNIM

TRIRI

CPIRI

CPIR

CPIRL

IA-IA

R-IA

A-IA

R-IR

UNIM

CPSIRI

CPBIR

CPSIRL

tA-IR

IR-IA

UNIM

CPDI

CPD

CPDL

R-IA

A-IR

A_IA

TRTII
IA-IA

(2bl\sj

R-IM

LDII
IA-IA

LDIRI

SLLL
R-IM

BRLL
OUTI

OUT

DA-A

DA-R

UNIM

A-1M

E
z

RRI

~,.

(2 bits)

(2bIIS)

A-1M

t;
!

UNIM

IND

IR-IA

IA-IR

INDRI

INDR

IA-IA

IA-fR

UNIM

II:

SDLL
R-IM

~
15e
~

..
II:

OUTDI
A

OUTD

IR-IA

IR-IR

OTDRI

OTDR

IR-IA

IA-IA

UNIM

TRTIRI

IA-IA

Ii,.
II:

iii

INDI

RLCB

RLC

(1 bill

(\ bit)

A-1M

R-IM

SLAI

SLA

A-1M

SRAI

8HA

A-1M

RLCI

RLC

(21)119)
A-1M

(2biIS)
A-1M

SDAI

SDA

R-R

A-R

UNIM

I
II:

t;
!

II:

~
15
C.

TRDI
IA-IR

•~

UNIM

Ii
iii

TRTDI
A

IR-IA

~
15e
...
Ii

•

LDDI

Table J.

Upper Inatructioo Byte

RRCI

RRC

(1 bill

R-IM

UNIM

SLAL

IA-IA

CPSD

CPSDL

IA-IA

IR-fR

IA-IR

UNIM

CPDRI

CPDR

CPDRL

A-fR

R-IR

R-IF~

UNIM

CPBDRI

CPBDR

CPSDRL

IA-IA

IR-IA

IA-IR

UNIM

UNIM
D

R-IM

IR-IA

LDDRL

CPBDI

UNIM

IR-IA

LDDL

IA-IA

LDDR

TRDRI
C

LDD

IA-IA

LDDRI

BRAL
R-IM

RRCB

RRC

(2 bits)
R-IM

(2 bits)

R-IM

UNIM

SDAL

TRTDRI
IR-IA

UNIM
R-R

Table 4.
Upper Instruction Byte

Table 5.
Upper Inatructioo Byte

Table 6.
~

Inatructioo Byte

0-3

Programmer's Quick Reference Guide
78

IRET

UNIM

HALT

UNIM

BREAK·
POINT

LDCTL

LONG'

Compact
Direct Address
Index

ESC

UNIM

R-Few

Segmented or Linear
Direct Address
Index
Base Address
Base Index
Relative Address
Relative Index

ESC
UNSIGN'

UNIM

Table 9.

UNIM

ESC
INTERLOCK'

LOCTL

UNIM

RPSAPSEG

..~

ENTER

LDen

UNIM

RPSAPQFF

..~

EXIT

::>

II:

Iii

LONI

!!;

LOCTL

UNIM

z
0
;::

R-NSPSEG

~
on

Locn

UNIM

R-NSPOFF

!!;

~
g

PCACHE

PTLBESI PTLBESO PTLBENI PTLSEND

;;

II:
W

LDND

II:
W

ill

UNIM

>i
w
;;

II:
W

UNIM

ill

PTLS
A
PTLBN

UNIM

II:
W

UNIM

LDCTL

FCW_R

LOPSI

LDPSD

LDPNI

LDPND

D
UNIM

UNIM

LDCTL

UNIM

PSAPSEG

-R
LDCTL

UNIM

PSAPOFF

-R
UNIM

LDCTL
N8PSEG-R

LOCTL

UN 1M

NSPQFF-R

Table 7.
Upper Instruction Byte

D-4

Table 8.

LOMer Instruction Byte

Extended Addressing Modes

AppendixE.
Timing Formulae for
Performance Evaluation
INTROOUCTION
The ZBO,OOO CPU, unlike the ZBOOO and other 16-bit
microprocessors, integrates a highly pipelined
design, cache memory, and memory management into a
single component.
With the ear lier microprocessors it is relatively simple to calculate
exact performance measurements for a benchmark
program or program workload mixture, as follows.
Each instruction (i) in the architecture is
characterized by its execution cycle count (ni)
and number of memory references (ri).
From the
program workload, the frequency of execution for
each instruction (fi) can be determined. If W is
the number of wait states for the memory system,
then the average number of cycles to process an
instruction (Tr) can be determined from the
following formula.
TI

=~fi(ni

+ qW)

through the interface to the Z-BUS. The Z-BUS
is a time-multiplexed, address/data bus that
connects the components of a microprocessor
system.
•

The cache stores copies of instruction and data
memory locations.
Instructions are read from
the cache on the instruction bus. Data is read
from or written to the cache on the memory bus.
The cache also includes a copy of the physical
Program Counter, so that the logical addresses
of instructions are translated only for
branches and when incrementing the Program
Counter across a page boundary.

•

The Translation lookaside Buffer (TlB) translates logical addresses calculated by the
address arithmetic unit to physical addresses
used to access the cache.

•

The address arithmetic unit performs all
address calculations. This unit has a path to
the register file for reading base and index
registers and another path to the instruction
bus for reading displacements and direct
addresses. The result of the address calculation is transmitted to the TlB.

•

The register file contains the sixteen generalpurpose longword registers, Program Status
registers, special-purpose control registers,
and several registers used to store values temporarily during instruction execution.
The
register file has one path to the address
arithmetic unit and two paths to the execution
arithmetic and logic unit.

•

The execution arithmetic and logic unit calculates the results of instruction execution,
such as add, exclusive-or, and simple load.
This unit has two paths to the register file on
which two operands can be read simultaneously
or one can be written. One of the paths to the
register file is multiplexed with a path from
the memory bus.

•

The instruction decoding and control unit
decodes instructions and controls the operation
of the other functional units. This unit has a
path
from the instruction bus and two

And, if Tc is the cycle time of the processor,
then the processor's performance (that is, the
processor's rate of executing instructions) is
given by the formula below.
performance

= (TrTc)-1

Calculating the performance of the ZBO,OOO
processor involves a more complex formulation that
accounts for dependencies between instructions in
the pipeline and misses for the cache and
Translation lookaside Buffer (TlB). This appendix
contains the timing formulae used to analyze the
performance of the ZBO,OOO CPU, and also a
sufficiently
detailed
description
of
the
processor's implementation to calculate timing
parameters for a program workload.

Theory of Operation

Figure E-1 shows a block diagram of the ZBO,OOO
CPU's
internal
organization,
including
the
following major functional units and data paths:
•

The
external
interface
logic
controls
transactions on the bus.
Addresses and data
from the internal memory bus are transmitted

E-1

Timing Formulae for Performance Evaluation
programmable
logic
arrays
for
separate
microcoded control of the two arithmetic
units.
This unit also controls exception
handling and TlB loading.

All of the functional units and dats paths listed
above are 32 bits wide.

Z·BUS

--------,

r-----MEMORY BUS

CACHE
DATA

CACHE
ADDRESS TAGS

INSTRUCTION REGISTER

TRANSLATION
LOOKASIDE
BUFFER

INSTRUCTION
DECODING
AND
CONTROL
UNIT

EXECUTION ARITHMETIC
AND LOGIC UNIT

L ________________
Figure E-1.
INSTRUCTION FETCH
PROGRAM
COUNTER
INCREMENT

CACHE TAG
COMPARE

INSTRUCTION DECODING

CACHE INSTRUCTION

READ
MICROWORD
GENERATION

Functional Block Diegra.

ADDRESS CALCULATIONS

ADDRESS ARITHMETIC
CALCULATION
TLBTAG
COMPARE

TLB DATA READ

Figure E-2.

E-2

OPERAND FETCH

CACHE TAG

COMPARE
CACHE DATA READ

Instruction Pipeline

EXECUTION
REGISTER READ
ALU CALCULATION
REGISTER WRllE

OPERAND STORE

FLAG SETTING

CACHE DATA WRITE
MEMORY WRITE

Timing Formulae for Performance Evaluation
The operation of the CPU is highly pipe lined so
that several instructions are simultaneously in
different stages of execution. Thus, the functional units effectively operate in parallel with
one instruction being fetched while an address is
calculated for another instruction and results are
stored for a third instruction.
Figure E-2 shows the six-stage, synchronous pipeline. Instructions flow through each stage of the
pipeline in sequence. The various pipeline stages
can be working simultaneously on separate instructions or on separate portions of a single complex
instruction. Each pipeline stage operates in one
processor cycle, which is composed of two clock
cycles, called \Il1 and \Il2.
Thus, a processor
cycle is 200 ns with a 10 MHz clock or 80 ns with
a 25 MHz clock.
The instruction-fetch stage increments the Program
Counter and initiates instructions fetched from
the cache.
The instruction-decoding stage
receives and decodes instructions to set up
control of the address-calculation stage.
The address-calculation stage can generally
calculate a memory address in one processor cycle,
except for Base Index, Relative, and Relative
Index addressing modes, which require multiple
cycles. After the logical effective address has
the corresponding physical
been calculated,
address is provided by the TLB. The operand-fetch
stage fetches the data from the cache and latches
it into a holding register.
The execution stage performs data manipulations.
Byte, word, and longword results are generally
calculated in one processor cycle, but certain
instructions, such as multiply and block-move
operations, require multiple cycles. During the
execution stage, results are stored to registers.
Results are stored to the cache and external
memory during the operand-store stage. The flags
are also set during the operand-store stage.
The cache can handle two references during a
processor cycle. Instruction fetches use the \Il2,
clock cycle for tag comparison and 9'>1 for data
access. Either an operand fetch or store can use
\Il1 for tag comparison and \Il2 for data access.
The pipeline allows single instructions, like
register-to-register load and memory-to-register
add, to execute at a rate of one per processor
cycle. Thus, the peak performance of the CPU is
12.5 million instructions per second (MIPS) with a
25 MHz clock. In practice, the actual performance
is reduced to approximately one-third of the peak
because of delays due to the execution of

multiple-cycle instructions, interference between
instructions in the pipeline, and main memory
accesses for cache and TLB misses.
In
order
to
calculate
the
processor's
performance it is helpful to separate the average
processing time for an instruction into four
components: execution delays, pipeline delays,
addressing delays, and memory delays.
The
following sections describe the various delay
components.

Execution Ti_

The first component of instruction processing time
is the basic execution time: the time reqUired to
execute an instruction assuming that there is no
interference from other instructions in the
pipeline and that all memory references hit in the
cache and TLB. An instruction's execution time is
determined by its operation, data type, and
addressing mode.
For most instructions, the execution delay can be
calculated by adding the number of cycles from
Table E-2 corresponding to the operation and data
type to the number of cycles from Table E-1
corresponding to the addressing mode. Use either
the source or destination addressing mode, as
listed with the instruction's format in section
6.5.
For the remaining instructions, Table E-2
gives
the
execution
delays
for
specific
combinations of operations, data types, and
addressing modes. The following example shows how
to use the tables.
An instruction that loads a longword from a
register to a register (e.g., LDL RR4, RR2), has
an execution time of 1 processor cycle: 1 for the
operation and 0 for the addressing mode.
An
instruction that adds a longword immediate value
to a register (e.g., ADDL RRO, #100), has an
execution delay of 2 processor cycles: 1 for the
operation and 1 for the addressing mode.
An
instruction that tests a bit of a byte in memory
specified by IR addressing mode (e.g., BITB ®RR2,
#1), has an execution delay of 3 processor cycles:
the delay is listed in Table E-2 for the specific
operation and addressing mode.

Pipeline Delays

Pipeline delays result from interference between
instructions at different stages of the pipeline.
Pipeline delays occur when instructions contend
for the use of a bus or functional unit, and one
instruction must be delayed.
There are two

E-3

Timing Formulae for Performance Evaluation
sources of pipeline delays:
register inter locks
and cache reference interlocks.

the interlocked address calculation, then the
pipeline delay is 2 processor cycles, otherwise
the inter lock causes a pipeline delay of 1 processor cycle.
Register inter locks are detected
for the use of longword registers. Thus, with the
CPU's register file organization (see Figure 2-2),
if a byte or word within a longword register is
modi fied, then a subsequent address calculation
can be interlocked by using the longword register
itsel f or either of the word registers it
contains.

A register inter lock occurs when an instruction
modifies a register that is required for an
address calculation by either of the two subsequent instructions. In addition, the following
instructions, which may modify more than one
register, cause an interlock for any registers
used in subsequent address calculations: CPD(BL),
CPI(BL) , CPSD(BL), CPSI(BL), DIVL, DIVUL, EXIT,
EXTSL, LDD(BL), LDI(BL) , LDM registers from
memory, LDML registers from memory, MULTL, MULTUL,
and Load CPU from EPU. When the instruction that
modifies the register is followed immediately by

For example, the following instruction sequences
cause register interlock delays when executed (in
linear mode).

I NCL RR2, 114
LDB RHO, ®RR2

//register interlock delay//
//for RR2 is 2 processor cycles//

MULT RR24, #1000
LDL RRO, RR4
ADDL RRO, RR12 (RR24)(16)

//register interlock delay//
//for RR24//
//is 1 processor cycle//

Table E-1.

Execution TiNeS for General Addressing HOdes

Addressing HOde

R
1M

Address Representation
COIIIpact
SegIIIBIlted or Linear
0

0 for

0 for 1 extension word
1 for 2 or 3 extension words

(byte or word)
(longword)

extension word
for 2 or 3 extension words

0 for

for
extension word
2 for 3 extension words

RA
RX

E-4

extension word
for 3 extension words

Not
Available

for

or 3 extension words

2 for

or 3 extension words

Timing Formulae for Performance Evaluation
Table E-2.

Execution U., for Instruction Operations
Addressing

Execution

Data Type

Modes

n.,

B,W

ADD

B,W,L

See Table E-1

AND

B,W

See Table E-1

R,EAM--See Table E-1

Operation

ADC

Bit
(Static)

Notes

B,W

Bit
(Dynamic)

B,W

BRKPT
CALL

See Table E-1

CALR

CHK

B,W,L

See Table E-1

CLR

B,W,L

See Table E-1

IR,EAM--See Table E-1

COM

See Table E-5.

Assumes trap not taken;
E-5 if trap taken.

see table

B,W,L

COMFLG

CP (Register)

B,W,L

See Table E-1

CP (Immediate)

B,W

See Table E-1

CPD

B,W,L

CPDR

B,W,L

5+4n

CPI

B,W,L

CPIR

B,W,L

5+4n

n is number of iterations.

E-5

Timing Formulae for Performance Evaluation
Table E-2.

Execution fi_ for Instruction
Addressing

Execution
fi_

Data Type

Modes

CPSD

B,W,L

CPSDR

8,W,L

4+5n

CPSI

B,W,L

CPSIR

B,W,L

4+5n

CVT (register)

All

See Table E-1

CVT (memory)

All

See Table E-1

CVTU (register)

All

See Table E-1

CVTU (memory)

All

See Table E-1

IR,EAM--See Table E-1

Operation

DEC

~erations-Continued

Notes

n is number of iterations.

B,W

DEcr

B,W

IR,EAM-See Table E-1

See Table E-1

5
25

Case 1
Case 2
Case 3 or 4

See Table E-1

4
6
38

Case 1
Case 2
Case 3 or 4

See Table E-1

6
8
26

Case 1
Case 2
Case 3 or 4

DIV
W

DIVU

See Table E-1

5
See Table E-1

E-6

Cache bypassed for operand fetch,
treat like cache miss.

7
39

Case 1
Case 2
Case 3

Timing Formulae for Performance Evaluation
Table E-2.

Execution

for InstrtEtion

Addressing
Operation

Data Type

Modes

B,W

DJNZ

Notes

Not taken

Taken

Not taken

Taken

15+4n

B,W

See Table E-1

10+n

EXIT

EXTR

R
I R, EAM--See Table E-1
R

EXTRU

IR,EAM--See Table E-1

n is the number of registers
specified in enter mask.

n is the number of the registers
specified in exit mask.

6
11

W,L

HALT
IN

ENTER

EXTS

Execution

~erations...{;ontinued

B,W

Add access time for input port.

INC

B,W

IR,EAM--See Table E-1

See Table E-1

INCI

B,W

Cache bypassed for operand fetch,
treat like cache miss.

E-7

Timing Formulae for Performance Evaluation
Tabla E-2.

Operation
IND

INDEX

INDR

INI

INIR

Execution Ti_ for Instruction Operatlons-Contlnued
Execution

Data Type

Addressing
Modes

B,W

See Table E-1

B,W

3+8n

4+8n

B,W

3+8n

4+Bn

INSRT

TiE

IR,EAM--See Table E-1

Notes
Assumes no I/O wait states--I/O
wsit states must be added.

Assumes trap not taken; see
Table E-5 if trap is taken.

n is number of iterations. Assumes
no I/O wait states--I/O wait states
must be added for each iteration.
Assumes no I/O wait states--I/O
wait states must be added.

n is number of iterations. Assumes
no I/O wait states--I/O wait states
must be added for each iteration.

IRET
JP

Not taken

Taken

Not taken

Taken

See Table E-1

JR
RA

LD (register)

B,W,L

See Table E-1

LD (memory)

B,W,L

See Table E-1

LD (immediate)

B,W,L

See Table E-1

LDA
LDAR

LDCTL
(into Control
register)

LDCTL
(from Control
register)

E-B

3
6

FCW
NSP
PSAP

Timing Formulae for Performance Evaluation
Table E-2.

Operation

Data Type

Execution Time for Instruction Operations-Continued
Addressing

Execution

Modes

Ti_

LOCTLB

LOCTLL
(into Control
register)

5
11
7

LOCTLL
(from Control
register)

LOO

B,W,L

LOOR

B,W,L

4+5n

LOl

B,W,L

LOIR

B,W,L

4+5n

LOK
LOM
(registers from
memory)

LOM
(memory from
registers)

LOML
(registers from
memory)

LOML
(memory from
registers)

LON

Notes

asp,

PSAP
NSP
SITTIO, SOTTO, NITTO, NOT TO, SCCL, NSP

n is number of iterations.

See Table E-1

6+n/2

n is even number of registers.

6+(n+1)/2

n is odd number of registers.

n is even number of registers.
See note 2.

2 + 2n

n is odd number of registers.

See Table E-1

9+n

lR,EAM--See Table E-1

7+n

n is number of registers specified
in mask operand.

See Table E-1

3+4n

n is number of registers specified

in mask operand.
See note 2.
See Table E-1

LOP

See Table E-1

LOPS

See Table E-1

B,W,L

LOR

B,W,L

MUll

See Table E-1

E-9

Timing Formulae for Performance Evaluation
Table E-2.

Operation

MULTU

NEG

Execution

for Instruction

Addressing
Modes

Execution

See Table E-1

B,W,L

IR,EAM--See Table E-1

Data Type

NOP
OR

OTDR

OTIR

Ii-

~erations-Continued

Notes

1
B,W

See Table E-1

B,W

B,W,

B,W

2+4n

3+4n

B,W

2+4n

3+4n

OUT
B,W

OUTD

OUT!

PCACHE
POP

B,W,L

IR,EAM--See Table E-1

PTLB

PTLBE

PTLBN

E-10

n is number of iterations.

Timing Formulae for Performance Evaluation
Table E-2.

Execution Ti.e for Instruction Operations-Continued

Addressing
Operation

Data Type

PUSH

Modes

Execution
Ti.e

IR,EAM--See Table E-1

Notes

B,W,L

RES
(Static)
B,W

RES (Dynamic)

EAM--See Table E-1

B,W

RESFLG

RET

Not taken

Taken

RLC

B,W

2+n

3+n

B,W

2+n

3+n

B,W

2+n

3+n

B,W

2+n

3+n

B,W

RLDB
RR

RRC

RRDB
SBC

= number

of bits rotated.

= number

of bits rotated.

= number

of bits rotated.

= number

of bits rotated.

See Table E-5.

E-11

Timing Formulae for Performance Evaluation
Table E-2.

Operation

SDA

SDL
SET
(Static)

Addressing

Execution

Data Type

Modes

Notes

B,W,L

Right shift

Left shift

B,W,L

B,W

SET
(Dynamic)

Execution Time for Instruction Operations-Continued

EAM--See Table E-1

B,W

SETFLG

SLA

B,W,L

SLL

B,W,L

SRA

B,W,L

SRL

B,W,L

SUB

B,W,L

See Table E-1

Tee

B,W

TEST

B,W,L

See Table E-1

TESTA

B,W,L

See Table E-1

1
4

TRAP

Assumes trap not taken;
trap taken.

see Table E-5

TRDB

TRDRB

4+7n

TRIB

E-12

n is number of iterations.

Timing Formulae for Performance Evaluation
Table E-2.

Execution Ti_ for Instruction

~rations-Continued

Addressing
Hodes

Execution

Data Type

Ti_

Notes

TRIRB

4+7n

n is number of iterations.

TRTDB

TRTDRB

4+7n

TRUB

TRURB

4+7n

B,W

See Table E-1

B,W

See Table E-1

B,W

See Table E-1

Bus-timing scale factor is 2. Cache
bypassed for operand fetch, treat
like cache miss.

Bus-timing scale factor is 4. Cache
bypassed for operand fetch, treat
like cache miss.

Bus-timing scale factor is 2. Add
time to store operand, see memory
delays section.

Bus-timing scale factor is 4. Add
time to store operand, see memory
delays section.

9+(n/2)

Bus-timing scale factor is 2. n is
even number of words transferred.

9+(n+1)/2

Bus-timing scale factor is 2. n is
odd number of words transferred.

15+n

Bus-timing scale factor is 4. n is
even number of words transferred.

16+n

Bus-timing scale factor is 4. n is
odd number of words transferred.

Operation

TSET

XOR

Load EPU from
Memory1

Load Memory
from EPU1

Losd CPU from
EPU1

B,W

W,L

See Table E-1

n is number of iterations.

n is number of iterations.
Cache bypassed for operand fetch,
treat like cache miss.

E-13

Timing Formulae for Performance Evaluation
Table £-2.

Operation
Load EPU from
CPU1

Execution TDe for Instruction

~rations-Continued

Addressing

Execution

Data Type

Hodes

TiE

W,L

8+(n/2)

Bus-timing scale factor is 2. n is
even number of words transferred.

B+(n+1/2)

Bus-timing scale factor is 2. n is
odd number of words transferred.

12+n

Bus-timing scale factor is 4. n is
even number of words transferred.

13+n

Bus-timing scale factor is 4. n is
odd number of words transferred.

Load FCW from
EPU1

Load EPU from
FCW1

Internal EPU
operation 1

Notes

Bus-timing scale factor is 2.

Bus-timing scale factor is 4.

Bus-timing scale factor is 2.

Bus-timing scale factor is 4.

Bus-timing scale factor is 2.

Bus-timing scale factor is 4.

Note 1:

The execution times reported for EPA instructions assume that the EPU does not force the CPU to
wait by asserting EPUBSY.
Refer to the Z8070 APU Technical Manual (Zilog document number
03-B226-01) for more information about execution delays for particular EPA instructions and
consideration of instruction overlap between the CPU and EPU.

Note 2:

Execution time for this instruction is less if burst transfers are supported for storing data
into memory. See memory delays section.

A cache reference inter lock occurs when an
instruction modifies a memory location and either
of the following two instructions fetches an
operand from memory (including immediate mode
operands other thsn those speci fied by special,
compact encodings, like the source operands for
BIT, DEC, and LDK instructions). This inter lock
is caused by contention for both the cache and
memory bus.
When the instruction that modifies
memory is followed immedistely by an instruction
that fetches an operand, the pipeline delsy is 2
processor cycles; otherwise, the pipeline delay is
1 processor cycle.

E-14

For example, the following instruction sequences
cause cache reference interlocks when executed (in
linear mode).
LDL RR12(10), RRO
ADDL RR2, OOR20

//cache reference interlock//
//delay is 2 processor cycles//

LDL RR12(10), RRO
ADDL RR2, RR4
ADDL RR2, @RR20

//cache reference interlock//
//delay is 1 processor cycle//

Timing formulae for Performance Evaluation

Addressing Delays
Addressing delays can occur when instructions or
operands are located across longword or page
bounderies. Unlike memory delays due to cache and
TLB misses, which are described in the next
section, addressing delays can be calculated from
knowledge of the CPU's operation alone, without
considering the memory system's latency and
bandwidth.
An addressing delay of 1 processor cycle occurs
when an operand that crosses a longword boundary
is fetched.
That is, when a longword is fetched
from an address for which the two least
significant bits differ from 00 or a word is
fetched from an address for which the two least
significant bits are 11.
This delay arises
because the CPU must make two memory references on
its 32-bit memory bus.
An addressing delay of 1 cycle also occurs when
the CPU branches to a two-word instruction that is
located at an odd-word address.
Another addressing delay of 3 cycles occurs when the PC is
incremented across a page boundary during sequential instruction processing. The former delay
arises from a gap in filling the instruction
buffer, while the latter delay is caused by the
need to translate the new page address in the PC.

Memory Delays
Memory delays occur when the CPU must wait to
access external memory to service a cache or TLB
miss or to store an operand. The duration of such
delays depends on the memory system's data path
width (16 or 32 bits), its access time, and its
support for burst transfers.
Thus, a microprocessor system designer can trade cost for performance by specifying these memory parameters as
well as the CPU's clock speed and the bus-timing
scale factor.
In the description that follows,
the times for single memory-read and -write transactions are represented by TRand TW processor
cycles, respectively; the bus-timing scale factor
(2 or 4) is represented by S. Burst transfers are
assumed to take the same times (T Rand TW) for
the initial transfer and 1 bus clock cycle for
each subsequent transfer.
The memory delay for both instruction and operand
cache fetch misses is TR• for instruction cache
misses, burst transactions are used as follows:
The CPU reads the missing word or longword (depending on the memory's data path width) and

requests the words or longwords that follow in the
16-byte cache block by signaling a burst transfer.
The burst transfer continues until either
the end of the 16-byte block is reached or the
memory system indicates that it cannot support
further transfers.
for operand fetch cache misses, burst transactions
are used when more than one transfer is anticipated within a 16-byte block. Specifically, burst
transfers are used to fetch operands for the
following instructions:
CPI(R), CPSI(R), CHECK,
EXIT (registers only), INDEX, IRET, LDI(R), LDM,
LDML, LDPS, OUTI(R), TRTI(R)B, and EPA instructions.
Burst transfers are also used to fetch
longword and unaligned word operands from a 16-bit
wide memory, plus unaligned word and longword
operands that cross an aligned longword boundary
for a 32-bit wide memory.
The CPU issues bus
transactions until the entire operand has been
fetched.
I f more than one operand word (for
16-bit memory) or longword (for 32-bit memory)
remains to be transferred, the CPU transfers the
first word or longword and attempts to burst
transfer the remaining words or longwords until
either all transfers are complete, the end of a
16-byte block is reached, or the memory system
indicates that it cannot support further burst
transfers.
for example, assume that the CPU requires seven
longwords from memory location 8 to execute an
LDML instruction, that all the longwords are
missing from the cache, and that the memory system
is 32 bits and supports burst transfers of 16-byte
blocks.
The CPU performs three bus transactions
to fetch the seven longwords.
The first transaction is a burst transfer of the longwords at
locations 8 and 12, the second transaction is a
burst transfer of the four longwords beginning at
location 16, and the final transaction is a single
transfer of the longword at location 32.
for a burst transaction with a bus-timing scale
factor of 2, no memory delay in addition to TR
is incurred for burst transactions except when
other transactions are pending, as described
below.
With a bus-timing scale factor of 4, an
additional memory delay of 1 processor cycle is
incurred for each burst transfer.
The memory delay for a TLB miss depends on the
time to fetch an aligned longword from memory and
the number of translation table levels.
The
formulae in Table E-3 give the number of processor
cycle delays for a TLB miss, where N represents
the number of table levels.

E-15

Timing Formulae for Performance Evaluation
Table E-3.
Me.ary Syst_

16-bit, no burst
16-bit, burst
32-bit

TLB Hiss Delay
TlB Hiss Delay
11 + (5 + 2TR+ 5/2) X N
11 + (5 + TR + 5/2) X N
11 + (5 + TR) X N

For example, assume that the time for a single
memory read transaction is 2 processor cycles, the
memory data path is 32 bits, and 2 levels of
translation tables are used.
Then the memory
delay for a TLB miss is 25 processor cycles (25 =
11 +

Two or three consecutive memory-write transactions
are required for an instruction that stores an
unaligned word or longword and also for an instruction that stores an aligned longword to a
16-bit memory.
The memory delay in processor
cycles is shown for these cases in Table E-4.

(5 + 2) X 2).

Besides cache and TLB misses, the CPU can also
experience memory delays if one bus transaction is
held pending while another is performed. In such
cases of bus contention, the CPU completes the
first transaction, then after 1 bus cycle delay,
initiates the pending transaction.
Thus, additional cycles of delay occur if the servicing of a
cache miss must wait for the completion of a
previous burst memory-read transaction or a
(The servicing of a
memory-write transaction.
cache miss may also be delayed by an EPA instruction transfer for a previous EPU internal operation instruction.) Similar 1y, additional delay
is incurred when the storing of an operand must
wait for the completion of a previous burst-memory
read transaction or a memory-write transaction.
In general, the delays due to bus contention
either between read transactions or between read
and write transactions can be ignored in calculating the CPU's performance; these delays have in
large part been counted by the cache misses and
Delays
cache interlocks previously described.
caused by bus contention between write transactions, though, must be considered, as explained
below.
Because the CPU buffers the data for only one
write transaction at a time, when an instruction
that stores an operand to memory is followed
shortly by another instruction that stores to
memory, the second instruction is delayed. If the
two store instructions are separated by 6. instructions, where the value of 6. for consecutive
instructions is 1, then the CPU is de layed by
Max(O, TW + 5/2 - 6.) processor cycles. For instance, assume that the time for a single memorywrite transaction is 3 processor cycles and the
bus-timing scale factor is 2.
Then the CPU is

E-16

delayed by 3 processor cycles when the second
store instruction immediately follows the first or
by 2 processor cycles if there is one non-store
instruction intervening between the two store instructions. If the store instructions are separated by more than three instructions that do not
store, then there is no delay.

Certain instructions, like LDIR and LDM, store
more than one operand to memory.
The memory
delays for such instructions are included in their
execution times listed in Table E-2 based on the
following assumptions: the operands are aligned,
the memory is 32 bits wide, and TW + 5/2 is four
processor cycles.
If TW + 5/2 exceeds four
processor cycles, then the excess must be counted
as a memory delay for every operand stored by the
instruction. Similarly, if operands are unaligned
or the memory is 16 bits wide, then an additional
memory delay must be counted for every stored
operand, as shown in Table E-4. For example, if
an LDIR instruction stores 3 aligned longwords to
a 16-bit memory, then the instrucion is delayed by
TW + 5/2 processor cycles for each of three
operands, or 3TW + 35/2 processor cycles.
The CPU attempts to use burst-write transactions
to store operands for ENTER (registers only), LDM,
LDML, and EPA instructions. In storing an operand
for these instructions, if the starting address is
not aligned to the size of the memory's width
(either 16 or 32 bits), the CPU issues one or two
single-wr He transactions to store the operand's
initial bytes until an aligned address is
reached.
Then, while one or more operand words
(for 16-bit memory) or longwords (for 32-bit
memory) remain to be transferred, the CPU
transfers the first word or longword and attempts
to burst transfer the remaining words or longwords
until all transfers are complete, the number of
rema1n1ng bytes is smaller than the memory's
width, the end of a 16-byte block is reached, or
the memory indicates that it cannot support
further burst transfera. If any bytes remain to
be stored, the CPU issues one or two single-write
transactions to store the final bytes.

Timing Formulae for Performance Evaluation
Table E-'I.

Me_ry Delays for Storing Word and lortgIIOrd Operanda

Address Bits

A,Ao

Bus Width

Data Type

(bits)

MeIIIory Delay
(Processor Cycles)

Tw + 5/2

2Tw + 5

Tw + 5/2

2Tw + 5

00
L

01
L

10
L

11
L

For example, assume the CPU is storing seven
longwords to memory location 13 to execute an
ENTER instruction and that the memory system is 32
bits and supports burst-write transfers of 16-byte
blocks. Then the CPU performs five transactions
to store the seven longwords:
1.
2.
3.
4.
5.

Store a single byte at location 13.
Store a word at location 14.
Burst transfer four longwords to store at
location 16.
Burst transfer two longwords to store at
location 32.
5tora a single byte at location 40.

that
support
Thus,
using
memory
systems
burst-write transactions, the execution time for
ENTER, LDM, LDML, and EPA instructions are less
than the values shown in Table E-2. To calculate
the appropriate instruction execution time for
such systems, add the number of cycles to perform
the memory references (for LDM, LDML, and EPA
instructions if the last transaction is not a
burst transfer, count only one cycle for it) to 15
for ENTER, 3 for LDM, 6 for LDML, and 4 for EPA
instructions.

E-17

Timing formulae for Performance Evaluation
Perforaance Calculation
In order to determine the CPU's performance for a
program workload, the aversge number of processor
cycles per instruction for execution (T E),
pipeline (Tp), addressing (TA), and memory
(1M) delays can be calculated by measuring the
frequency of occurence for the various delay
causes and using the formulae presented in
previous sections.
The average number of
processor cycles per instruction (TI) can be
estimated by adding the individual delay
components as shown below.

Since two clock cycles are in every processor
cycle, the following formula gives the performance
of a CPU whose clock cycle time is TC'

Because certain details of the CPU's operation
have been omitted to simplify the description and
analysis presented in this appendix, the formula
above gives only an approximate prediction of the
processor's actual performance. In general, the
analysis is conservative;
performance will
typically be better then predicted because the
simultaneous occurence of two or more delay
causes has been ignored. For example, the CPU can
handle a cache miss for one instruction· while
executing another multiple-cycle instruction, like
DIV. But, the time during which the delay causes
are overlapping is counted twice because execution
and memory delays are separately calculated.
Nevertheless, the analysis described above is
extremely useful, though inexact, because it is
much simpler and faster than a register-trans ferlevel simulation necessary for exact performance
calculations.

Performance = (2TITC)-1

Table E-5.
Exception

Processing Delay

Bus Error
Non-maskable interrupt
Vectored interrupt
Non-vectored interrupt
Extended Instruction trap
Privileged Instruction trap
System Cell trap
Address Translation trap

Breakpoint
Integer Overflow trap
Bounds Check trap
Index Error trap
Conditional trap
Unimplemented Instruction trap
PC trap
Trace trap

E-18

Exception Processing Ti_

Notes

21
26
21
23
23
22

22
2D
26
28
26
28
23
23
23
20

Add 11 cycles if sccess protection violation
detected for translation table descriptor
register. Otherwise add number of cycles
given in Table E-3 to access levels of
translation table until exception detected.

Source
Source
Source
Source

operand
operand
operand
operand

below
above
below
above

lower
upper
lower
upper

bound
bound
bound
bound

Note 1:

For all exceptions, add the time to store Program Status registers onto the System
Stack and to load Program Status registers from the Program Status Area in external
memory.

Note 2:

For Bus Error and Address Translation exceptions, also add the time to store the
violation longword address onto the System Stack.

Note 3:

For interrupts, add the time for the Interrupt Acknowledge transaction.

Timing Formulae for Performance Evaluation
Exceptioo Processing Delays

In addition to processing instructions, the CPU
must occasionally process exceptions. Table E-5
lists the delays incurred for processing various
Calculating the delays
types of exception.
involves determining the time to store the Progrsm
Status registers to memory and fetching new values
for the Program Status register from the Program
Status Area. For example, assume that the time
for a single memory-read trensaction is 2 processor cycles and the time for a single memorywrite transaction is 3 processor cycles, the
memory data path is 32 bits, and the bus-timing
scale factor is 2. Then the time to store and
fetch the Program Status is 13 processor cycles:
The 4 memory references require 3 processor cycles
each, and an idle bus cycle follows each of the
first 3 references.
Thus, the delay for processing a System Call trap is 35 processor cycles.

In order to calculate the frequencies of the
various delay components, the programs were
interpreted by a software simulator for the CPU's
instruction set.
The performance was then
determined for systems composed of a 12 MHz CPU
and each of three different memories that varied
in their data path eize and support for burst
transfers.
The execution delay for the workload was
determined from the frequency distribution of
instruction.
Table E-7 shows the ten most
cOlM1onl y
executed
instructions
and
their
frequencies
as
a
percentage
of
total
instructions. The average execution delay is 1.8
processor cycles per instruction.

Table E-7.

Instructioo
Addressing

EXllllple
Opcode

This section describes an example of performance
evaluation for a workload containing fifteen
programs representative of 16-bit microprocessor
applications. The programs are all written in C
and run in normal compact mode under Zilog's ZEUS
version of the UNIX* operating system. Table E-6
lists the programs in the workload, which includes
five million executed instructions.

Table E-6. Progr_ Workload Used for ZIIO,OOO
CPU Perfonance Evalu&tioo
Progr-

C1
C2
C3
C4
CPP
DIFF
ED
GREP
LS
NM
OD
PR
SED
SORT
VI

Moat ~ly

Executed lnatructioos

Use

C compiler parser
C compiler code generator
C compilsr optimizer
C compiler lister
C compiler preprocessor
File comparison
Line editor
Pettern searching
File directory listing
Load module name listing
Octal dumping of core imagea
Format for line printer
Stream editor
Sorting
Screen editor

*UNIX is a trademark of AT&T Bell Laboratories.
Zilog is licensed by AT&T Technologies, Inc.

JR
LD(register)
INC
CP(register)
LD(register)
LDB(register)
DEC
EXTSB
LD(memory)
LD(memory)

Mode

RA
R
R

1M
X
IR
R
R
X
IR

Frequency
(percent)

19.0
10.7
7.9
4.7
4.4
4.1
3.3
3.2
2.1
2.0

The average pipeline delay per instruction is 0.3
processor cycle. A register interlock occurs for
11% of instructions, causing 0.19 processor cycle
delay, and a cache reference inter lock occurs for
6% of instructions, causing 0.11 processor cycle
delay.
Addressing delays are 0.03 processor cycles per
instruction. These delays result almost entirely
from branches to unaligned two-word instructions,
because the compiler positions operands at aligned
addresses and page-crossings rarely occur during
sequential instruction processing.
In calculating memory delays, three memory systems
were considered. The first memory has a 16-bit
data path, a cycle time of 2 processor cycles for
read and 3 processor cycles for write and no burst
transfers.
The second and third memories have
32-bit data paths and cycle times of 2 processor
cycles for read and 3 processor cycles for write,
but the third supports burst transfers whereas the
E-19

Timing Formulae for Performance Evaluation
second does not. All three systems use s bus
clock scaled by s fsctor of 2 from the CPU's
clock.
To determine the svarage delsy caused by cache
misses it is useful to compute the average number
of misses per instruction,~. To calculste ~, it
is necesssry to know the csche hit ratio (h),
which is the fraction of fetched words that are
located in the cache, and the average number of
fetched words per instruction. For this worklosd,
an aversge of 1.4 instruction words snd 0.3 operand .word are fetched per instruction. Therefore,
the everage number of cache misses per instruction
is given by ~ = 1.7 (1-h), snd the average delay
per instruction due to cache misses is 2~. The
values of cache hit ratiO, misses per instruction,
and delays per instruction are shown in Table E-B.
Table [-8. Cache ... TlB Miss Delays
16-8it

Me.ory Syst_

32-8it 32-8it

No Burst No Burat Burst

Cache

Hit rstio
Misses per instruction
Delay per instruction

Perfo~

0.62
0.65
1.3

0.75
0.42
0.B4

O.BB
0.21
0.42

0.99
0.02
0.46

nB Perfor.a1Ce
Hit Ratio
Misses per instruction
Delay per instruction

0.99
0.02
0.57

Table [-9.

MaDry Syst_
16-bit no-burst
32-bit no burst
32-bit burst
32-bit burst,
no translation

In addition, the delay caused by bus contention
amounts to 0.2 procassor cycle per instruction for
all of the memory systems. In general, a 32-bit
memory would exhibit less bus contention then a
16-bit memory, but the memory systems show
negligible difference in bus contention for this
workload, which makes little use of longword
operands. (Fewer than 2~ of memory operands are
longwords. )
The performance of a 25 MHz CPU with each of the
three memory systems is calculated by adding the
various delay components. The reaults, summarized
in Table E-9 show the performance ranges from 3.1
to 5.0 million instructions per second (MIPS).
For short sequences of instructions executed
repeatedly, it is posaible to approach the maximum
performance of 12.5 MIPS.

Proceas1ng Perfontmce

Perfor8alC8
TI = T[ + Tp + TA + TN
Processor cyclea Per Instructioo
(MIPS)"
3.1
3.7
4.2

4.0 = 1.B + 0.3 + 0.0 + 1.9
3.4 1.B + 0.3 + 0.0 + 1.3
3.0 1.B + 0.3 + 0.0 + 0.90

5.0

2.5 = 1.8 + 0.3 + 0.0 + 0.4

* The analysis used in calculating the performance
is conservative; the delays are independently
calculated, but in practice the delays may often
overlap. Consequently the actual performance may
be better than the values shown in the table.
[-20

Cslculating the average delay caused by TLB misses
is similar to cache misses, as described above,
but operand stores as well as fetches can cause
TLB misses. This is because the physical frame
address in the page table entry is needed to atore
an operand. On an average, 0.15 operand word is
stored per instruction. The delay to service a
TLB miss for two-level translation tables can be
derived from the formulae previously given in the
section on memory delays: 31 processor cycles with
the 16-bit memory and 25 processor cycles with the
32-bit memory.
The values of nB hit ratio,
misses per instruction, and delays per instruction
are shown in Table E-B.

Glossary
access protection: A function of memory management that controls read, write and execute access
to memory locations, protecting proprietary or
operating system memory areas from tampering by
unauthorized users. The CPU uses the protection
(PROT) field to determine access rights for a page
or segment.
access protection violation: An incorrect or forbidden attempt to access a memory location; for
example, an attempt to write to a read-only page.
An access violation causes the CPU to generate an
Address Translation trap.
activation record: A data structure containing
the local storage, saved register contents, and
exception handler address associated with the
invocation of a procedure. Activation records are
stored on the processor stack in a linked list. An
activation record is allocated when the Enter
instruction is executed at the beginning of a
procedure. The record is released when the Exit
instruction is executed at the end of a procedure.

addressing mode: The way in which the location of
an operand is specified. There are nine addressing
modes: Register, Immediate, Indirect Register,
Direct Address, Index, Base Address, Base Index,
Relative Address, and Relative Index.
addreas tag: The portion of certain associative
memories that is compared against a referenced
address to determine whether the matching value is
found. The address tag for a Translation Lookaside
Buffer entry is the logical page address; the
address tag for a cache block is the physical
memory address.

The process of mapping logical addresses into physical addresses.

address translation:

An exception that
Address Translation trap:
occurs during address translation when either an
access protection violation or an invalid table
entry is detected. The instruction being executed
is suspended, and the PC, FCW, identifier word,
and the logical address that caused the trap are
saved on the system stack.

An address that is a multiple of
an operand's size in bytes. Aligned word addresses
are a multiple of two; aligned longword addresses
are a multiple of four.

aligned address:

A memory in which data is
accessed by specifying a value rather than a location. The Translation Lookaside Buffer and cache
are associative memories.
associative .e.ory:

The operation of decrementing an
address in a register by the operand's size in
bytes. The decrement amount is one for byte
operands, two for word operands, and four for
longword operands.
autodecr_ent:

The operation of incrementing an
address in a register by the operand's size in
bytes. The increment amount is one for byte
operands, two for word operands, and four for
longword operands.
autoincra.ent:

The address used, along with an
index and/or displacement value, to calculate the
effective address of an operand. The base address
is located in a general-purpose register, the Program Counter, or the instruction.

base address:

In this mode,
the displacement in the instruction is added to
the contents of the base register to obtain the
effective address.

Base Address (RA) addressing .ode:

In this mode,
the contents of the base register and index register are added to the displacement in the instruction to obtain the effective address.

Oase Index (OX) addresaing.ode:

bit field: One to thirty-two contiguous bits that
can cross byte boundaries. A bit field is specified by its byte origin, its bit position from the
origin, and its size in bits. The instruction set
allows bit fields to be extracted from a long word
and inserted into a longword.
burst transaction: The transfer of several consecutive items of data (either words or longwords)
in one memory transaction.

G-1

Glossary
An exception that occurs when external
hardware identifies an irrecoverable error during
a data transfer on the external interface.

bus error:

bus .aster:

The device in control of the bus.

bus retry: A response to a data transfer transaction that indicates the transaction must be tried
again because of some transient error condition.

A data item containing 8 contiguous bits. A
byte is the basic data unit for addressing memory
and peripherals.

byte:

An on-chip buffer that automatically
stores copies of recently used memory locations
(both instructions and data), allowing fast access
on memory fetches.

cache:

A mode of address representation,
usually used for applications with small memory
requirements, in which 16-bit addresses are manipulated; address calculations involve all 16 bits.
The logical address is extended to 32 bits by concatenating the 16 most-significant bits of the
Program Counter.
CCllpset !lOde:

An instruction ending in which the
current instruction has been completely executed.
This is the normal instruction ending, but
exceptions can cause a different ending.

co.pletion:

coprocessor: A processor, such as a Z8070 Arithmetic Processing Unit, that works synchronously
with the CPU to execute a single instruction
stream using the Extended Processing Architecture
(EPA) •
Address (DA) addressing lIIOde:
In this
mode, the effective address is contained in the
instruction.

A condition or event that alters the
usual flow of instruction processing. The Z80,OOO
CPU supports four types of exception: reset, bus
error, interrupts, and traps. When an exception
occurs, the CPU saves the Program Status on the
system stack and fetches a new Program Status from
the Program Status Area.
exception:

A CPU operating state
that results when an exception occurs, during
which the CPU stores values from the Program
Status registers to memory, and fetches values
from memory for the Program Status registers.

exception processing state:

The type of memory access used by
the CPU for fetching instructions and immediate
mode operands.
execute access:

Extended Addressing Mode (EAM):
An addressing
mode in which one or more extension words follow
the opcode. In compact mode, EAMs are Direct
Address and Index. In segmented or linear mode,
EAMs are Direct Address, Index, Base Address, Base
Index, Relative Address and Relative Index.
Processing Architecture (EPA):
A CPU
facility controlled by the EPA bit in the Flag and
Control Word that allows the operations defined in
the architecture to be extended by hardware or
software. If enabled, the CPU transfers EPA
instructions to an Extended Processing Unit (EPU)
for execution; if disabled, the CPU traps EPA
instructions for software emulation.

Extended

Processing Unit (EPU):
An external
device, such as a Z8070 APU, that handles Extended
Processing Architecture instructions (such as
floating-point arithmetic).

Extended

Direct

A constant value located in the
instruction that is used for calculating the
effective address of an operand.

displaceEnt:

A bit manipulation operation
in which the source operand is located in a register and therefore its value is changeable.

dyna.ic operation:

The logical memory address of
an operand, calculated by adding the base address,
an optional index value, and an optional displacement.

effective address:

An EPU-handled operation
that controls EPU operations but does not transfer
data.
EPU internal operation:

G-2

One of the
two Program Status registers, a 16-bit register
that contains the flags and bits that control the
operation of the CPU.
Flag and Control Word (FOI) register:

flyby transaction: A transaction controlled by
the bus master, but in which another device transfers data to the responding device.
fra.e: A 1K-byte physical memory unit used by the
memory management mechanism to map 1K-byte logical
memory pages. A frame is speCified by the 22 mostsignificant bits of the physical address.

The register that points to
the current activation record on the stack. In
compact mode, the FP is a word register, R14; in
segmented or linear mode, a longword register,
RR12.
Frame Pointer (FPh

Glossary
general-purpose registers: The 16 versatile registers that can be used as data accumulators,
index values, or memory pointers.
global bus:
A bus shared by tightly-coupled,
multiple CPUs; the bus master is chosen by an
external arbiter device.
halted state: A CPU operating state that results
when a Halt instruction is executed or a bus error
exception occurs during exception processing.

Hardware Interface Control register (HICR): The
32-bit special-purpose register that specifies
certain characteristics of the hardware configuration incorporating the CPU, such as bus speed,
memory data path width, and number of wait states.
hit: A hit occurs when an associative memory is
searched for a value and a match is found.
identifier word:
A 16-bit code saved on the
system stack during exception processing that
provides information about the cause of the
exception.

lesat recently used (LRU): The CPU records the
order of use for Translation Lookaside Buffer
entries and cache blocks. When a TLB miss or cache
tag miss occurs, the CPU replaces the least
recently used entry or block.
length counter: A register that contains the
value that is the length of a block or string of
data that is manipulated by instructions.
linear !lOde: A mode of address representation in
which 32-bit addresses are manipulated, prov iding
uniform and unstructured access to the 4G bytes of
memory. Address calculations involve all 32 bits.
local bus: The bus controlled by the CPU and
shared with slave processors.
logical address: The address manipulated by the
program. The memory management mechanism translates logical addresses to physical addresses.
longword:
bits.

A data item containing 32 contiguous

addresaing 1IOde: In this mode, the
operand is contained in the instruction.

loosely-coupled OPUs: CPUs that execute independent instruction streams and communicate through a
multi-ported peripheral, such as a Z8038 flO I/O
interface unit.

index: A value located in a register used for
calculating the effective address of an operand.
The index value usually specifies the calculated
offset of an operand from the origin of an array
or other data structure.

_ r y _anag_t:
The process of translating
logical addresses into physical addresses, plus
certain protection functions. In the Z80,000 CPU,
memory management is integrated into the chip.

Index (X) addresaing lIOde: In this mode, the
contents of an index register are added to a base
address contained in the instruction to obtain the
effective address.

_ _ Y-llapped I/O: A memory management feature
that allows logical memory addresses to be mapped
to physical I/O addresses. Memory mapped I/O provides protected access by application programs to
peripherals.

I~iste (1M)

Indirect Register (IR) addresaing!lOde: In this
mode, the effective address is contained in a
register.

_iss:
A miss occurs when an associative memory
is searched for a value and no match is found.

instruction executing atate:
A CPU operating
state in which the CPU executes instructions.

The
interrupt; cannot be disabled.

interrupt: An asynchronous exception that occurs
when the NMI, VI, or NVI line is activated,
usually when a peripheral device needs attention.

nonvectored interrupt:
The lowest priority
interrupt, which does not use an identifier word
as a vector to an interrupt service routine; can
be disabled.

invalid table entry: A cause of an Address Translation trap that is detected during address translation if the CPU fetches a translation table
entry with a Valid bit of O.
large~:
In the segmented mode, one of the
128 segments in the upper half of the memory
address space. Segments are 16M bytes in size or
smaller.

highest

priority

nar.al !lOde:
A CPU mode of operation, generally
used for application programs, in which the SIN
flag in the FCW is O. In this mode, the CPU cannot execute privileged instructions or access protected memory locations.

G-3

Glosssry
Nomal Stack Pointer (NSP):

The Stack Pointer
used while the CPU is in normal mode. System mode
programs can access the NSP with the Load Control
instruction.

Progr_ status registers:
gram Counter and Flag and
tain the Program Status.
automatically saved during

overflow stack: The stack used for saving the
Program Status, identifier word, and exception
parameters when an address translation exception
occurs during exception processing.

Progr_ Status Area (PSA): The area in memory
reserved for storing the Program Status of the
interrupt and trap service routines.

Overflow Stack Pointer (OSP):
The 32-bit register that contains the physical address of the
overflow stack.

The two registers (ProControl Word) that conThe Program Status is
exception processing.

Progr_ Status Area Pointer (PSAP): The 32-bit
register thst contains the physical, base address
of the Program Status Area.
protection: See access protection.

A 1K-byte logicsl memory unit mapped by
the memory management mechanism to a 1K-byte physical memory frame. A page is specified by the 22
most-significant bits of the logical address.
page:

page table:
The third level of translation
tables, containing the physical frame address used
during address translation.

protection (PROT) field: A 4-bit field contained
in the translation table descriptor registers and
translation table entries that specifies access
protection information for s logical address during sddress translation.
quachlOrd:

A data item containing 64 contiguous

bits.
paged translation:
A method of address translation in which the logical and physical address
spsces are divided into fixed, equal-sized units
called pages and frsmes, respectively. During
address translation, a logical page is mapped to
an arbitrary physical frame.
partie! co.pletion: An instruction ending in
which
the
execution
of
an
interruptible
instruction is disrupted before completion by a
trap or interrupt.
physice! address: The 32-bit address required for
accessing memory and peripherals, obtained by the
CPU's address translation hardware.
plpaline: A computer design technique in which an
instruction is executed in a sequence of stages by
different functional units. The functional units
can be operating on several different instructions
simultaneously, similar to an automobile assembly
line.
prefetching: Ability of the CPU to fetch an
instruction or opersnd before the previous
instructions have been completed.
privileged instruction: An instruction that performs I/O operations, accesses control registers,
or performs some other operating system function.
Privileged instructions execute in system mode
only.
Progr_ Coulter (PC): One of the two Program
Status registers, a 32-bit register that contains
the address of the current instruction.

G-4

read access: The type of memory access used by
the CPU for fetching data operands other than
those specified by Immediate mode.
Register (R) addressing.ode: In this mode, the
operand is in a general-purpose register.
Relative Address (RA) addressing.ode: In this
mode, the displacement in the instruction is added
to the contents of the Program Counter to obtain
the effective address.
Relative Index (RX) addressing IMIde: In this
mode, the contents of the Program Counter and
index register are added to the displacement in
the instruction to obtain the effective address.
relocation: The process of mapping a logical
address to a different physical address, so that
multiple processes can use the same logical
address for distinct physical memory locations.

reset: A CPU operating state or exception that
results when a reset request is signaled on the
RESET line. A reset initializes the Program Status
registers.
responder: The device to which bus transactions
transfer data.
result register: The register that holds the
result of an operation.

Glosssry
~ed .ade:
A mode of address rsprssentation
that supports either 64K- or 16M-byte segments
with 32-bit addressss. The most-significant
address bit aelects either a 15-bit segment number
with 16-bit offset, or a 7-bit segment number with
24-bit offset. Calculations affect only the offset
snd not the segment number.

self....adUying progr_: A program that etorss to
a location from which a subsequent instruction is
fetched.
slave proceeaor: A processor, such as a Direct
Memory Accees tranefer controller, that performs
dedicated functions asynchronously to the CPU.

In the segmented mode, one of the
32,768 segments in the lower half of the memory
address space. Segments are 64K bytes or smaller.

A CPU mods of operation, used for
operating system functions, in which the sIN flag
in the FCW is 1. In this mode, the CPU can executed privileged (and all other) instructions.
ayata..ada:

Syat. StlMlk Pointer (SSP): The Stack Pointer
ussd while the CPU is in system mode. Normal mode
programs cannot access the SSP.
tag hit: On a memory reference, a tag hit occurs
when the cache address tags are searched for the
refsrsnced address and a match is found.
tag 8iaa: On a memory rsfsrsnce, s tag miss
occurs when the cache address tags are searched
for the referenced address and no match is found.

a.all~:

spatial locality: The characteristic of program
behavior whereby consecutive memory references
often apply to cloaely located addresses.
speeial-purpoaa control regieters:

Nine registers
used for system configuration, memory management,
Program Status, and CPU control.

stlMlk Pointer (SP): A general-purpose register
indicating the top (lowest address) of the
processor stack used by Call, Enter, Exit, and
Return instructions for linking procedures. The SP
is a word register, R15, in compact mode, and a
longword register, RR14, in linear or segmented
mode. Normal and system modes of operation use
separate stack pointers, the Normal Stack Pointer
(NSP) and System Stack Pointer (SSP).
static operation: A bit manipulation operation in
which the source operand is an immadiate value and
is therefore fixed (static).
l1118p1111Bion: An instruction ending in which the
the current instruction has not been completed
because a trap is detected during instruction
execution. The instruction can be completed by
eliminating the cause of the trap and atarting the
instruction again.
auapension with PC .adification: An instruction
ending similar to suspension, but the Program
Counter saved on the system stack during exception
processing must be decremented by two before
starting the instruction again.

te.poral locality: The chsracteristic of program
behavior whereby memory references often apply to
a location that has been referred to recently.
tanlination: An instruction ending in which the
current instruction has not bsen completed and it
is not possible to complete the instruction by
starting it again.
tightly-coupled CPOs: CPUs that execute independent instruction streams and communicate through
shared memory on a common (globsl) bus.
Tr..J.ation LooIcaai.de Buffer (TLB): An on-chip
memory that automstically stores translation
information for the most rscently used memory
pages.
tr..J.ation table: One of three levels of tables
selectsd by the page descriptor registers during
address translation. Each lsvel corresponds to a
field in the logical page address.
tr..J.ation table descriptor reg1ater: One of
four registers that contain the physical addresses
of the translation tables used by the memory
management mechaniam during address translation.
tr..J.ation table entry: An entry in one of the
three levels of translation tables. Entries in the
first two levels point to another level table.
Entries in the third level (page table) contain
the
physical
frame
addrsss
used
during
translation.
trap: An exception that occurs when certain conditions, such as an access protection violation,
are detected during execution of an instruction.

Syst. Configuration Control longIIord register
(SCCl): The 32-bit special-purpose register that
contains control bits for addrsss translation,
cache, and exception processing.
G-5

Glossary
~I
An addrsas that is not a multipls of an opsrand's sizs in bytss. Odd addressss
ars unaligned for words and longwords; even
addreeses that are not multiples of four sre
unaligned for longwords.

unaligned

An interrupt that uses the
low-order byte of the identifier word as a vector
to an interrupt ssrvice routine; can be diaabled.

wrd:

A data item containing sixteen contiguous

bits.
wrd hit: On a memory reference to the cache, a
tag hit occurs and a valid copy of the word is
atored in the cache.

vacI:ored interrupt:

virtual ...ary: A memory managemant tachniqua in'
which the system's logical memory address spsee is
not necesaarily the same as, and can be much
larger than, the available physical memory.

G-6

wrd .iaa: On a memory reference to the cache, a
tag hit occurs but a valid copy of the word ia not
atored in the cache.

writs acceaa: The type of memory acceas used by
the CPU for storing dsta operands.

Index
-AAccess protection, 1:2, 4:8
Address cslculations, 5:1,3
Addressing delsys, E:15
Addressing modes, 4-14, 5:2
Bsse Address (BA), 5:6,10
Bsse Index (BX), 5:6,11
Direct Address (DA), 5:5,8
Extended, 5:14
Immediste (1M), 5:4,8
Index (X), 5:5,9
Indirect Register (IR), 5:4,8
Relstive Address (RA), 5:7,12
Relative Index (RX), 5:7,13
used in compact mode, 5:4-7
used in segmented and linear modes, 5:7-12
Address representation, 1:1, 3:1-2
Compact mode, 1:1, 3:1-2
Linear mode, 1:2, 3:1-2
Segmented mode, 1:1-2, 3:1-2
Address spaces, 1:1, 4:1-3
Address trsnslation, 1:2, 4:4
Address Translstion trap, 7:4
Architecture, 1:1
Arithmetic instructions, 6:2-3
Assembler language syntex, 6:10-11

-8-

Base Address (BA) sddressing mode, 5:6,10
Bese Index (BX) addressing mode, 5:6,11
Bit field instructions, 6:5-6
Bit Manipulation instructions, 6:5
Block diagram of Z8D,OOO CPU, 1:6
Block Transfer and String Manipulstion
instructions, 6:7
Breakpoint trap, 7:4
Burst Memory Resd snd Write transaction, 8:10-11
Burst Memory Read timing, B:12
Burst Memory Write timing, B:13
Burst transfer protocol, 8:11
Bus acknowledge, B:22-24
Bus error, 7:4, 8:21
Bus operations, 8:1
Bus request, B:22-24
Bus Request Acknowledge timing, 8:22

Bus request protocol, 8:24
Bus retry, 8:21
Bus timing, 8:6-7
Bus transaction response, 8:8
Bus transsctions, 8:7-21
Burst Memory Resd and Write trensaction, 8: 10-11
CPU-EPU Data trsnsactions, 8:17-18
CPU-EPU Instruction transactions, 8:16
CPU-Memory transactions, 8:8-12
EPU-Memory transactions, 8:18-19
EPU transactions, 8:13-15
Input/Output transactions, 8:12-13
Interlocked Memory transsctions, 8:11-12
Single Memory Read and Write trsnsactions,
8:8-10

-CCache, 1:4, 8:3, C:1-3
Compact mode, 1:1, 3:1-2, 6:13
Compatibility with Z8000 CPU, 1:6, A:1
Condition codes, 6:9-10
Conditional trap, 7:4
Coprocessor, 1:4, 8:2
CPU Bus Request Protocol, 8:24
CPU Control instructions, 6:8-9
CPU-EPU Data Read timing, 8:17
CPU-EPU Data transactions, 8:17-18
CPU-EPU Data Write timing, 8:1B
CPU-EPU Instruction transactions, 8:16
CPU-EPU Instruction Transfer timing, 8:16
CPU internal organizatIon, 1: 5-6
CPU-Memory transactions, 8:8-12

-DData formats, 2:1
Demand-paged virtual memory, 1:2
Direct Address (DA) addressing mode, 5:5,8

-EEPA, see Extended Processing Architecture
EPU-Memory Single Write timing, 8:19 EPU-Memory
transactions, 8:18-19

1-1

Index

-E- (Continued)
EPU transactions, 8:13-15
Exception handlera, 7:7
Exception processing delays, E:19-20
Exceptions, 1:3, 7:3-9
8us error, 7:4
Interrupts, 7:4
Priority of, 7:8-9
Reset, 7:3
Traps, 7:4,5
Execution time, E:3
Extended addressing modes, 5:14, 6:13
Extended Instructions, 6:9
Extended Instruction trap, 7:4
Extended Processing Architecture (EPA), 1:3,4
External interface, 1:4, 8:1-27

Flag and Control Word register, 1:1, 2:2-3
Flags, 6:9-10
Floating-point operations, 1:3
Flyby transactions, 8:1
Frame pOinter, 1:1, 2:2

Descriptions and formats, 6:16-214
Extended Instructions, 6:9
Flags and condition codes, 6:9-10
Input/Output instructions, 6:8
load and Exchange inatructions, 6:1-2
logical instructions, 6:3-4
Notation and binary encoding used in, 6:10-12
Program Control instructions, 6:4-5
Integer Arithmetic Error trap, 7:4
Interlocked Memory transactions, 8:11-12
Internal Operation and Halt timing, 8:21
Internal Operation and Halt tranaactions, 8:21
Interrupt Request/Acknowledge timing, 8:20
Interrupt Request and Acknowledge, 8:20-21
Interrupts, 1:3, 7:4
Non-maskable, 1:3
Non-vectored, 1:3
Vectored, 1:3 I/O Read timing, 8:14

linear mode, 1:2, 3:1-2, 6:13-15
load and Exchange instructions, 6:1-2
local Bus Request Acknowledge timing, 8:22
logical instructions, 6:3-4
logical I/O address spacea, 4:3
logical memory address spaces, 4:1
loosely-coupled multiple CPU, 1:5

General-purpose register file, 2:1-2
Global Bus Request timing, 8:23

Hardware Interface Control register (HICR), 2:4,
8:5-6

Memory dslays, E:15-18
Memory management, 1:2, 4:3
Memory-mapped I/O, B:1
Multiprocessor Configurations, 1:4, 8:2
Coprocessor, 1:4 Slave processor, 1:5
Tightly-coupled multiple CPUs, 1:5
loosely-coupled multiple CPUs, 1:5

-1-

Immediate (1M) addressing mode, 5:4,8
Index (X) addressing mode, 5:5,9
Indirect Register (IR) addressing mode, 5:4,8
Input/Output instructions, 6:8
Instruction execution, 7:2-3
Instruction format, 6:12
Instruction Set, 6:16-214
Arithmetic instructions, 6:2-3
Bit Field instructions, 6:5-6
Bit Manipulation instructions, 6:5
Block Transfer and String Manipulation
instructions, 6:7
CPU Control instructions, 6:8-9

Non-maskable
Non-vectored
Normal mode,
Normal Stack

interrupts, 7:4
interrupts, 7:4
1:3, 3:2-3
Pointer, 2:3, 3:2

Odd PC trap, 7:5
Operating states, 7:1
Overflow Stack Pointer (OSP), 2:4

Index
-1-

Physical address space, 4:3
Pin Functions, 8:3-4
Pipeline delays, E:3-4
Pipelined instruction execution, 7:3
Privileged Instruction trap, 7:4
Program Control instructions, 6:4-5
Program Counter, 1:1, 2:3
Program Status, 7:5-7
Program Status Area Pointer (PSAP), 2:3
Program Status registers, 1:1, 2:2-3
Program Counter, 1:1, 2:3
Flag and Control Word register, 1:1, 2:2-3

-RRegister (R) addressing mode, 5:4,7
Relative Address (RA) addressing mode, 5:7,12
Relative Index (RX) addressing mode, 5:7.13
Reserved control bits, 2:4
Reset, 8:26-27

Table entry formats, 4:7
Tightly-coupled multiple CPU, 1:5
Timing formulae, Appendix E
TLB, see Translation Lookaside Buffer
Trace trap, 7:5
Translation Lookaside Buffer (TLB), 1:2, 4:4-5
Translation Table Descriptor registers, 2:4
Traps, 7:4-5
Address Translation trap, 7:4
Breakpoint trap, 7:4
Conditional trap, 7:4
Extended Instruction trap, 7:4
Integer Arithmetic Error trap, 7:4
Odd PC trap, 7:5
Privileged Instruction trap, 7:4
System Call trap, 7:4
Trace trap, 7:5
Unimplemented Instruction trap, 7:5

-tI-

-5-

Segmented mode, 1:1-2, 3:1-2, 6:13-15
Single Memory Read and Write transactions, 8:8-10
Single Memory Read timing, 8:8-9
Single Memory Write timing, 8:10
Slave processor, 1:5, 8:2
Special-purpose control registers, 2:3
Stack POinter, 1:1, 2:2
System Call trap, 7:4
System Configuration Control Longword, 2:4
System mode, 1:3, 3:2-3
System Stack Pointer, 3:2

Unimplemented Instruction trap, 7:5

-y-

Vectored interrupts, 7:4

-zZ8000 CPU, compatibility with, 1:6, A:1
Z8070 Arithmetic Processing Unit, 1:3
Z80,OOO CPU block diagram, 1:6

1-3

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