Z80_Microprocessor_Family_Jan90 Z80 Microprocessor Family Jan90
User Manual: Z80_Microprocessor_Family_Jan90
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Z80 MICROPROCESSOR
FAMILY
1th EDITION
JANUARY 1990
USE IN LIFE SUPPORT DEVICES FOR SYSTEMS MUST BE EXPRESSLY AUTHORIZED
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF SGS-THOMSON
Microelectronics. As used herein:
1. Life support devices or systems are those which (a) are
intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when
properly used in accordance with instructions for use
provided with the product, can be reasonably expected
to result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can reason·
ably be expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
TABLE OF CONTENTS
ALPHANUMERICAL INDEX
PRODUCT GUIDE
zao FAMILY OVERVIEW
CROSS REFERENCE
PART NUMBER IDENTIFICATION
Page
5
7
8
9
10
CMOS FAMILY DATASHEETS
11
NMOS FAMILY DATASHEETS
117
3
ALPHANUMERICAL INDEX
Type
Number
Function
Page
Number
Z84COO
Z80C CPU CMOS Version
13
Z84C10
Z80C DMA CMOS Version .
45
Z84C20
Z80C PIO CMOS Version ....
65
Z84C30
Z80C CTC CMOS Version.
79
Z84C40
Z80C SIO CMOS Version
93
Z84C41
Z80C SIO CMOS Version ......... ..
93
Z84C42
Z80C SIO CMOS Version ....
93
Z8400
Z80 CPU Control Process Unit
119
Z8410
Z80 DMA Direct Memory Access Central.
153
Z8420
Z80 PIO Parallel Input/Output Controller
175
Z8430
Z80 CTC Counter Timer Circuit .....
191
Z8440
Z80 SIO Serial Input/Output Controller .......... ..... .
205
Z8441
Z80 SIO Serial Input/Output Controller ...
205
Z8442
Z80 SIO Serial Input/Output Controller
205
Z8470
Z80 DART Serial Input/Output Controller
225
5
PRODUCT GUIDE
7
zaD FAMILY OVERWIEW
Estabilished as the industry standard, the Z80 CPU
offers many features not found on comparable microprocessors: on chip refresh for dynamic memories, comprehensive bit test, reset instructions,
block transfer and search instructions, two 16 bit
index registers, powerful vectored interrupts and
a dual register bank for fast context switching.
Complementing the power of the CPU is a complete family of versatile peripheral components.
And today, with the introduction of low power
CMOS versions, the Z80 is more than ever the first
choice for 8-bit applications.
Central Processor Unit
The Z80 CPU features 158 instruction, software
compatible whit all the 78 of the 8080A with added
powerfu bit, word and string operations. Three modes of high speed interrupt including a unique vectored interrupt. Dual register sets for context
switching plus two 16-bit index registers for memory
reference.
Counter/Timer Circuit
The Z80 CTC is a programmable component with
four independent channel that provide counting and
timing functions for microcomputer system based
on the Z80 CPU.
The programmer can configure the CTC to operate under various modes to interface with a wide range of devices.
Serial Input/Output
The Z80 SIO is a dual channel multi-function peripheral component designed to satisfy a wide variety of serial data communications requirements
in microcomputer systems.
Its basic function is a serial-to-parallel, parallel-toserial converter/controller but within that role its personality is software configurable so that it can be
optimized for a given serial data communications
application.
Dual Asynchronous Receiver Transmitter
Direct Memory Access
The Z80 DMA performs data transfers and searches in a wide variety of 8-bit CPU environments.
It is unique among DMA's in that it takes full control of the systems address, data and control buses - and is therefore a special purpose processor
- when enabled by the CPU to do so. The DMA also provides complete interfacing to the system bus.
Parallel Input/Output
The Z80 PIO is a programmable two port device
which provides a TTL compatible interface betwe.en
peripheral devices and the Z80 CPU. The programmer can configure the Z80 PIO to interface with a
wide range of peripheral devices with no other external logic required.
8
The Z80 DART is a dual channel multi-function peripheral component that satisfies a wide variety of
serial data communications requirements in microcomputer systems. The Z80 DART is used as a
serial-to-parallel, parallel-ta-serial converter/controller in asynchronous applications.
In addition it also provides modem controls for both
channels.
4 Clock Speeds and 4 Package Types
The NMOS & CMOS family Z80 offers a wide selection of speeds with 2.5, 4, 6 and 8 MHz versions
and come in plastic and ceramic dual-in-line packages as well as leaded plastic quad-in-line
packages.
CROSS REFERENCE
SUFFIX DESCRIPTION
TEMP. SUFFIX
BASE PART
NUMBER
SPEED SUFFIX (MHz)
4.0
2.5
6.0
8.0
PACKAGE SUFFIX
PL FR CE PL LC
~
...
Z84XX
Z084XX
SGS-THOMSON Z84CXX
TOSHIBA
TMPZ84XX
ZILOG
Z084CXX
SHARP
LH508X
NEC
I'PD70008AXX
*
na
na
na
na
na
na
H
08
B
P
F
D
D
C
C
V
na
L
S
A
B
-6
06
na
-6
H
-8
08
na
-8
B
P
P
na
na
D
na
na
D
na
C
na
na
C
T
V
na
na
na
na
L
na
na
na
na
S
na
na
*
-4
*
*
I
+
in
on
6
E
2
M
6
2
na
M
na
na
1
B
06
04
co
....
+
A
04
*
~
+
:g
co
SGS-THOMSON
ZILOG
~
co
on
:::!
I
*
E
*
*
DEVICE TYPE
CPU
DMA
PIO
CTC
SIO
DART
SGS-THOMSON
ZILOG
Z8400
Z08400
Z8410
Z0841 0
Z8420
Z08420
Z8430
Z08430
Z8440/1/2
Z08440/1/2
Z8470
na
SGS-THOMSON
TOSHIBA
ZILOG
SHARP
NEC
Z84COO
TMPZ84COO
Z084COO
LH5080
I'PD70008A
Z84C10
TM PZ84C 10
Z084C10
LH5083
na
Z84C20
TMPZ84C20
Z084C20
LH5081
na
Z84C30
Z84C40/1/2
TMPZ84C30
TMPZ84C40/112
. Z084C4011/2
Z084C30
LH5082
na
na
na
Notes:
na
na
na
na
na
* Standard Version - No suffix required
na: Not Available
9
PART NUMBER IDENTIFICATION
Example:
Z8400
Circuit Designator _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-----'
Speed
No letter
A
B
2.5 MHz
4.0
6.0
8.0
H
Package _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
B Plastic
D Ceramic
F Frit-Seal
C Leaded Plastic - Chip Carrier
Temperature Range _ _ _ _ _ _ _ _ _ _ _ _ _ _,--_ _ _ _ _ _ _ _ _----"
1
6
2
10
0 to + 70°C
-40 to + 85°C
-55 to + 125°C
CMOS FAMILY DATASHEETS
11
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Z84COO
l8DC CPU CMOS VERSION
• THE INSTRUCTION SET CONTAINS 158 INSTRUCTIONS. THE 78 INSTRUCTIONS OF
THE 8080A ARE INCLUDED AS A SUBSET;
8080A AND Z80 SOFTWARE COMPATIBILITY
IS MAINTAINED
• 8 MHz, 6 MHz AND 4 MHz CLOCKS FOR THE
Z80CH, Z80CB AND Z80CA, THE Z80C CPU,
RESULT IN RAPID INSTRUCTION EXECUTION WITH CONSEQUENT HIGH DATA
THROUGHPUT
• THE EXTENSIVE INSTRUCTION SET INCLUDES STRING, BIT, BYTE, AND WORD
OPERATIONS. BLOCK SEARCHES AND
BLOCK TRANSFERS TOGETHER WITH INDEXED AND RELATIVE ADDRESSING RESULT IN THE MOST POWERFUL DATA
HANDLING CAPABILITIES IN THE MICROCOMPUTER INDUSTRY
• THE Z80C MICROPROCESSORS AND ASSOCIATED FAMILY OF PERIPHERAL CONTROLLERS ARE LINKED BY A VECTORED
INTERRUPT SYSTEM. THIS SYSTEM MAY BE
DAISY-CHAINED TO ALLOW IMPLEMENTATION OF A PRIORITY INTERRUPT SCHEME.
LITTLE, IF ANY, ADDITIONAL LOGIC IS REQUIRED FOR DAISY-CHAINING
• DUPLICATE SETS OF BOTH GENERAL-PURPOSE AND FLAG REGISTERS ARE PROVIDED,
EASING
THE
DESIGN
AND
OPERATION OF SYSTEM SOFTWARE
THROUGH SINGLE-CONTEXT SWITCHING,
BACKGROUND-FOREGROUND
PROGRAMMING, AND SINGLE-LEVEL INTERRUPT PROCESSING. IN ADDITION, TWO
16-BIT INDEX REGISTERS FACILITATE PROGRAM PROCESSING OF TABLES AND ARRAYS
• THERE ARE THREE MODES OF HIGH SPEED
INTERRUPT PROCESSING: 8080 SIMILAR,
NON-Z80 PERIPHERAL DEVICE, AND Z80
FAMILY PERIPHERAL WITH OR WITHOUT
DAISY CHAIN
• ON-CHIP DYNAMIC MEMORY REFRESH
COUNTER
• SINGLE 5 V ± 10 % POWER SUPPLY
• LOW POWER CONSUMPTION:
_ 9 mA TYP. AT 4 MHz
_ 15 mA TYP. AT 6 MHz
September 1988
_ 20 mA TYP. AT 8 MHz
_ LESS THAN 10 IlA IN POWER DOWN
MODE
• EXTENDED OPERATING TEMPERATURE
_ 40"C TO + 85 "C
B
o
DIP-40
DIP-40
(Plastic)
(Ceramic)
•
C
PLCC44
(Plastic)
(Ordering Information at the end of the datasheet)
LOGIC FUNCTIONS
._\
CONTROL
iii
Ao
A,
A,
rOi\a
Ro
A,
...
...
w,
A,
.
A,
.~\
CONTROL
CPU {
BUS
CONTROL
HALT
ADDRESS
BUS
A,
Z84COO
A"
Au
A"
Au
A"
0,
0,
- 1
0,
D.
DATA.
BUS
0,
0,_
0,
1/32
13
Z84COO
DESCRIPTION
laO CMOS Family is fabricated using SGS-THOM-
The laOC CPU is third-generation single-chip
microprocessors with exceptional computational
power. They offer higher system throughput and
more efficient memory utilization than comparable
second-and third-generation microprocessors. The
internal registers contain 20a bits of readlwrite
memory that are accessible to the programmer.
These registers include two sets of six general-purpose registers which may be used individually as
either a-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes
either set of main or alternate registers accessible
to the programmer. The alternate set allows operation in foreground-background mode or it may be
reserved for very fast interrupt response.
The laOC also contains a Stack Pointer, Program
Counter, two index registers, a Refresh register
(counter), and an Interrupt register.
The CPU is easy to incorporate into a system since
it requires only a single + 5 V power source, all output signals are fully decoded and timed to control
standard memory or peripheral circuits, and is supported by an extensive family of peripheral controllers. The internal block diagram (figure 3) shows the
primary functions of the laOC processors. Subsequent text provides more detail on the laOC 1/0 controller family, registers, instruction set, interrupts and
daisy chaining, and CPU timing.
Figure 1 : Dual in Line Pin Configuration.
Figure 2 : Chip Carrier Pin Configuration.
SON' CMOS Silicon Gate Technology, which provides low power operation and high performance.
An
A"
An
A"
As
As
Au
A,
A"
As
elK
A,
04
eLK
O.
...
03
A,
0,
A,
0,
A,
Vee
0,
GHO
0,
ftfSH
0"
M1
0,
RESET
!NT
BUSREO
HMI
WAIT
HAll
2/32
14
As
8USACK
MAED
w-
10AO
Ali
u
z
6
., ., ., ., ., ., :r
,
, ,
~
~
J
,I. 4)
7
:;'
1.1
.,
~
"'" "
"
J8
A,
A4
0)
0,
06
N.e
vee
0,
07
00
0,
"
"
"
ZB4COO
,J
"
"
,8
Ii
19
iz
70
"
77
21
I~-4 18cr: I:?0 ~
r
~
-
16 77
]1.
~5
u
~ l~
z
I~
"
I~
5-1I1~
I
Z84COO
Figure 3 : CPU Block Diagram.
Vee __
GND~
CLOCK -..
CPU REGISTERS
Figure 4 shows three groups of registers within the
CPU. The first group consists of duplicate sets of 8-
bit registers: a principal set and an alternate set
(designated by '[prime), e.g., A'). Both sets consist
Figure 4 : CPU Registers.
Main Register Set
Alternate Register Set
A Accumulator
F Flag Register
A' Accumulator
F' Flag Register
B General Purpose
C General Purpose
B' General Purpose
C' General Purpose
D General Purpose
E General Purpose
D' General Purpose
E' General Purpose
H General Purpose
L General Purpose
H' General Purpose
L' General Purpose
< - - - - 8 Bits ----->
16 Bits
<--
--6
IY Index Register
SP Stack Pointer
PC Program Counter
I Interrupt Vector
I
INTERRUPT FLIP-FLOPS STATUS
-->
IX Index Register
~
I
R Memory Refresh
0 = INTERRUPTS DISABLED
1 = INTERRUPTS ENABLED
<----- 8 Bits ----->
STORES IFF1
DURING NMI
SERVICE
INTERRUPT MODE FLIP-FLOPS
IMFa
IMFb
o
o
o
1
o
1
1
1
INTERRUPT MODE 0
NOT USED
INTERRUPT MODE 1
INTERRUPT MODE 2
3/32
15
----_.
-----
Z84COO
of the Accumulator Register, the Flag Register, and
six general-purpose registers. Transfer of data between these duplicate sets of registers is accomplished by use of "Exchange" instructions. The
result is faster response to interrupts and easy, efficient implementation of such versatile programming techniques as background-foreground data
processing. The second set of registers consists of
six registers with assigned functions. These are the
I (Interrupt Register), the R (Refresh Register), the
IX and IV (Index Registers), the SP (Stack Pointer),
and the PC (Program Counter). The third group consists of two interrupt status flip-flops, plus and additional pair of flip-flops which assists in identifying the
interrupt mode at any particular time. Table 1 provides further information on these registers.
INTERRUPTS: GENERAL OPERATION
The Z80C has a single response mode for interrupt
service for the non-maskable interrupt. The maskable interrupt, INT, has three programmable response modes available.
These are:
• Mode 0 - compatible with the 8080 microprocessor.
• Mode 1 - Peripheral Interrupt service, for use with
non-8080/Z80 systems.
• Mode 2 - a vectored interrupt scheme, usually
daisy-chained, for use with Z80 Family and compatible peripheral devices.
The CPU services interrupts by sampling the NMI
and INT signals at the rising edge of the last clock
of an instruction. Further interrupt service processing depends upon the type of interrupt that was detected. Details on interrupt responses are shown in
the CPU Timing Section.
The CPU acc~ two interrupt input signals: NMI
and INT. The NMI is a non-maskable interrupt and
has the highest priority. INT is a lower priority interrupt and it requires that interrupts be enabled in software in order to operate. INT can be connected to
multiple peripheral devices in a wired-OR configuration.
NON-MASKABLE INTERRUPT (NMI)
The non-maskable interrupt cannot be disabled by
program control and therefore will be accepted at all
times by the CPU. NMI is usually reserved for servicing only the highest priority type interrupts, such
as that for orderly shut-down after power failure has
been detected.
Table 1 • CPU Registers
Size (Bits)
Remarks
A, A'
F, F'
B, B'
C, C'
D, D'
E, E'
H, H'
L, L'
Register
Accumulator
Flags
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
8
8
8
8
8
8
8
8
I
Interrupt Register
8
R
Refresh Register
8
IX
IY
SP
Index Register
Index Register
Stack Pointer
16
16
16
PC
IFF1-IFF2
IMFa-IMFb
Program Counter
Interrupt Enable
Interrupt Mode
Stores an Operand or the Results of an Operation
See Instruction Set.
Can be used separately or as a t6-bit register with C.
See B, above.
Can be used separately or as a 16-bit regis1er with E.
See D, above.
Can be used separately or as a 16-bit register with L.
See H, above.
Note: The (B, C), (D, E), and (H, L) sets are combined as
follows:
B-High Byte C-Low Byte
D-High Byte E-Low Byte
H-High Byte L-Low Byte
Stores upper eight bits of memory address for vectored
interrupt processing.
Provides user-transparent dynamic memory refresh. Lower
seven bits are automatically incremented and all eight are
placed on the address bus during each instruction fetch
cycle refresh time.
Used for indexed addressing.
Same as IX, above.
Holds address of the top of the stack. See Push or Pop in
Instruction Set.
Holds address of next instruction.
Set or reset to indicate interrupt status (see figure 4).
Reflect Interrupt Mode (see figure 4).
4/32
16
16
Flip-Flops
Flip-Flops
Z84COO
After recognition of the NMI signal (providing BUSREO is not active), the CPU jumps to restart location 0066H. Normally, software starting at this
address contains the interrupt service routine.
plies the low-order byte of the 2-byte vector, bit 0
(Ao) must be a zero.
MASKABLE INTERRUPT (INT)
The interrupt priority of each peripheral device is
determined by its physical location within a daisychain configuration. Each device in the chain has an
interrupt enable input line (lEI) and an interrupt enable output line (lEO), which is fed to the next lower
priority device. The first device in the daisy chain has
its lEI input hardwired to a High level. The first device has highest priority, while each succeding device has a corresponding lower priority. This
arrangement permits the CPU to select the highest
priority interrupt from several simultaneously interrupting peripherals.
Regardless of the interrupt mode set by the user,
the Z80C response to a maskable interrupt input follows a common timing cycle. After the interrupt has
been detected by the CPU (provided that interrupts
are enabled and BUSREQ is not active) a special
interruQLprocessing cycle begins. This is a special
fetch (MI) cycle in Which IORQ..Qecomes active
rather than MREQ, as in normal M1 cycle.
In addition, this special M1 cycle is automatically extended by two WAIT states, to allow for the time required to acknowledge the interrupt request.
MODE 0 INTERRUPT OPERATION
This mode is similar with the 8080 microprocessor
interrupt service procedures. The interrupting device places an instruction on the data bus.
This is normally a Restart Instruction, which will initiate a call to the selected one of eight restart locations in page zero of memory. Unlike the 8080, the
Z80 CPU responds to the Call instruction with only
one interrupt acknowledge cycle followed by two
memory read cycles.
MODE 1 INTERRUPT OPERATION
Mode 1 operation is very similar to that for the NMI.
The principal difference is that the Mode 1 interrupt
has a restart location of 0038H only.
MODE 2 INTERRUPT OPERATION
This interrupt mode has been designed to utilize
most effectively the capabilities of the Z80C microprocessor and its associated peripheral family. The
interrupting peripheral device selects the starting
address of the interrupt service routine. It does this
by placing an 8-bit vector on the data bus during the
interrupt acknowledge cycle. The CPU forms a
pointer using this byte as the lower 8-bits and the
contents of the I register as the upper 8-bits. This
points to an entry in a table of addresses for interrupt service routines. The CPU then jumps to the
routine at that address. This flexibility in selecting
the interrupt service routine address allows the peripheral device to use several different types of service routines.
These routines may be located at any available location in memory. Since the interrupting device sup-
INTERRUPT PRIORITY (Daisy Chaining and
Nested Interrupts).
The interrupting device disables its lEO line to the
next lower priority peripheral until it has been serviced. After servicing, its lEO line is raised, allowing
lower priority peripherals to demand interruptservicing.
The Z80C CPU will nest (queue) any pending interrupts or interrupts received while a selected peripheral is being serviced.
INTERRUPT ENABLE/DISABLE OPERATION
Two flip-flops, IFF1 and IFF2, referred to in the register description are used to signal the CPU interrupt status. Operation of the two flip-flops is
described in table 2. For more details, refer to the
Z80 CPU Technical Manual.
Table 2_ State of Flip-Flops
Action
IFF2 IFF2
CPU Reset
0
0
DI Instruction
Execution
EI Instruction
Execution
LD A, I Instruction
Execution
LD A, R Instruction
Execution
Accept NMI
0
0
1
1
RETN Instruction
Execution
Comments
Maskable Interrupt
INT Disabled
Maskable Interrupt
INT Disabled
Maskable Interrupt
INT Enabled
IFF2 -7 Parity Flag
IFF2 -7 Parity Flag
0
IFF1
IFF2
.
IFF1 -7IFF2
(maskable
interrupt
INT disabled)
IFF2 -7 IFF1 at
Co~tion of
an NMI Service
Routine.
5/32
17
Z84COO
CPU INTERRUPT SEQUENCE
NO
5ET NMI ftF
5£f INT flf
NON
\ MASKA8L£
INTERRUPT
NO
Notes: 1.
2.
3.
4.
6/32
18
I
MA$KABl.(
INTERRUPT
INT and NMI are always acted on at the end of an instruction.
BUSRQ is acted on at the end of a machine cycle.
_
_
While the CPU is in the DMA MODE, it will not respond to active inputs on INT or NMI.
These three inputs are acted on in the following order of priority.
1) BUSRQ -- highest
2) NMI
3) INT -- lowest.
"001'
Z84COO
INSTRUCTION SET
The Z8DC microprocessor has one of the most
powerful and versatile instruction sets available in
any 8-bit microprocessor. It includes such unique
operations as a block move for fast, efficient data
transfers within memory or between memory and
1/0. It also allows operations on any bit in any location in memory.
•
•
•
•
•
•
16-BIT ARITHMETIC OPERATIONS
ROTATES AND SHIFT
BIT SET, RESET, AND TEST OPERATIONS
JUMPS
CALLS, RETURNS, AND RESTARTS
INPUT AND OUTPUT OPERATIONS
A variety of addressing modes are implemented to
permit efficient and fast data transfer between various registers, memory locations, and input/output
devices. These addressing modes include:
• Immediate
• Immediate extended
• Modified page zero
• Relative
• Extended
• Indexed
• Register
• Register indirect
• Implied
• Bit
The following is a summary of the Z8DC instruction
set and shows the assembly language mnemonic,
the operation, the flag status, and gives comments
on each instruction. The Z80 CPU Technical Manual
and Z80 CPU Programming Manual contain sig nificantly more details for programming use.
The instructions are divided into the following categories:
• 8-BIT LOADS
• 16-BIT LOADS
• EXCHANGES, BLOCK TRANSFERS, AND
SEARCHES
• 8-BIT ARITHMETIC AND LOGIC OPERATIONS
• GENERAL-PURPOSE ARITHMETIC AND CPU
CONTROL
16-BIT ARITHMETIC GROUP
Flags
Opcode
Symbolic
Operation
S Z
H
ADD HL, ss
ADC HL, ss
HL ~ HL + SS
HL ~ HL + ss + CY
t t
X X X
X X X
V
0
0
t
t
SBC HL, ss
HL
t t
X X X
V
1
t
ADD IX, pp
IX
~
+ pp
X X X
0
t
ADD IY, rr
IY
~
IY + rr
X X X
0
t
Symbol
INC ss
INC IX
~
HL + ss - CY
ss~ss+1
IX
~
IX + 1
.
X
X
INC IY
IY
~
IV + 1
X
DEC ss
DEC IX
ss
IX
+->
~
ss - 1
IX - 1
X
X
DEC IY
IY~
IY-l
X
P/V N C 76 543210
X
X
· ··
"
.X · ··
X
X
· ··
.X · ·
00
11
01
11
01
11
01
11
00
00
11
00
11
00
00
11
00
11
00
ssl 001
101 101
ssl 010
101 101
ssO 010
011 101
ppl 001
111 101
rrl 001
ssO 011
011 101
100011
111 101
100011
ssl 011
011 101
101 011
111 101
101 011
Hex
N° of
Bytes
N° of
M
N° of
T
Comments
Cycles States
ED
1
2
4
11
15
ED
2
4
15
DD
2
4
15
FD
2
4
15
1
2
1
2
6
10
3
S5
Reg.
00 BC
01 DE
10 IX
11 SP
pp Reg.
~~-
DD
23
FD
2
2
10
1
2
1
2
6
10
2
2
10
23
DD
2B
FD
00
01
10
11
BC
DE
IX
SP
rr
Reg.
00 Be
01 DE
10 IY
11 SP
2B
Notes: ss is any 6f the register pairs Be, DE, HL, SP.
pp is any of the register pairs Be, DE, IX, SP.
rr is any of the register pairs Be, DE, IY, SP.
7/32
19
Z84COO
INSTRUCTION SET (continued)
8-BIT LOAD GROUP
Symbolic
Operation
Symbol
LD r, r'
LD r, n
Flags
5 Z
r~r'
Opcode
PlY N C
H
76 543210
r'
110
r <- n
X
X
X
X
01
00
<-
LD r, (HL)
LD r, (IX+d)
r <- (HL)
r <- (IX + d)
X
X
X
X
01
r 110
11 011 101
01
r 101
<- d -->
LD r, (IY+d)
r <- (IY + d)
X
X
11 111 101
01
r 110
<- d -->
LD(HL), r
LD(IX+d), r
(HL) <- r
(IX + d) <- r
X
X
X
X
01 110
r
11 011 101
01 110
r
<- d -->
LD(IY+d), r
(IY + d) <- r
X
X
LD(HL), n
(HL) <- n
X
LD(IX+d), n
(IX + d) <- n
LD(IY+d), n
N° of N° of
N° of
M
T
Bytes Cycles
Stales
1
2
1
2
4
7
DD
1
3
2
5
7
19
FD
3
5
19
DD
1
3
2
5
7
19
11 111 101
01 110
r
<- d -->
FD
3
5
19
X
00 110 110
<- n -->
36
2
3
10
X
X
11 011 101
00 110 110
<- d -->
<- n -->
DD
36
4
5
19
(IY + d) <- n
X
X
11 111 101
00 110 110
<- d -->
<- n -->
FD
36
4
5
19
LD A, (Be)
LD A, (DE)
LD A, (nn)
A <- (Be)
A <- (DE)
A <- (nn)
X
X
X
X
X
X
00 001 010
00 011 010
00 111 010
<- n -->
<- n -->
OA
lA
3A
1
1
3
2
2
4
7
7
13
LD(Be), A
LD(DE), A
LD(nn), A
(Be) <- A
(DE <- A
(nn) <- A
X
X
X
X
X
X
00 000 010
00 010 010
00 110 010
<- n -->
<- n -->
02
12
32
1
1
3
2
2
4
7
7
13
11
01
11
01
11
01
11
01
ED
57
ED
5F
ED
47
ED
4F
2
2
9
2
2
9
2
2
9
2
2
9
LD A, I
A <- I
t t
X 0 X
IFF
0
A
X 0 X
IF
0
t
LD A, R
A<-R
LD I, A
I <- A
X
X
LD R, A
R<-A
X
X
y
r
r
n
Hex
101
010
101
011
101
000
101
001
-->
101
111
101
111
101
111
101
111
Comments
r, r' Reg.
--ODD B
001
C
010
D
011
E
100
H
101
L
111
A
Notes: r, r' means any of the registers A, B, e, D, E, H, L.
IFF the content of the interrupt enable flip-flop, (IFF) is copied into the PIV flag.
For an explanation of flag notation and symbols for mnemonic tables, see Symbolic Notation section following tables.
8/32
20
Z84COO
INSTRUCTION SET (continued)
16-BIT LOAD GROUP
Symbol
LD dd, nn
LD IX, nn
LD IV, nn
Symbolic
Operation
Flags
S Z
dd <-- nn
X
IXH <-- (nn + 1)
IXL <-- (nn)
LD IV, (nn)
• X • X
.
IVH<--(nn+1)
IV L <-- (nn)
· ·
.
·
• X • X
LD (nn), HL (nn + 1) <-- H
(nn) <-- L
• X • X
.
·
·
• X • X
LD (nn), dd
(nn + 1) <-- ddH
(nn) <-- ddL
LD (nn), IX
(nn+1)<--IXH
(nn) <-- IXL
• X • X
(nn+1)<--IVH
(nn) <-- IVL
• X • X
LD (nn), IV
.
X • X
·
·
Hex
00 ddO 001
<-- n ~
<-- n ~
X • X
LD HL, (nn) H <-- (nn + 1)
L <-- (nn)
LD IX, (nn)
·
X • X
IV <-- nn
ddH <-- (nn + 1)
ddL <-- (nn)
X
X • X
IX <-- nn
LD dd, (nn)
Opcode
PIV N C 76 543210
H
·
N° of
Bytes
3
N° of
N° of
T
M
Cycles Slates
3
10
dd Pair
--DO
01 DE
10 HL
11 SP
Be
11 011 101
00 100 001
<-- n ~
<-- n ~
DD
11 111 101
00100001
<-- n ~
<-- n ~
FD
00 101 010
<-- n ~
<-- n ~
4
4
14
4
4
14
2A
3
5
16
11 101 101
01 dd1 011
<-- n ~
<-- n ~
ED
4
6
20
11 011 101
01 101 010
<-- n ~
<-- n ~
DD
4
6
20
4
6
20
11 111 101
00 101 010
<-- n ~
<-- n ~
Comments
21
21
2A
FD
2A
00 100 010
<-- n --->
<-- n ~
22
3
5
16
11 101 101
01 ddO 011
<-- n ~
<-- n ~
ED
4
6
20
11 011 101
00100010
<-- n ~
<-- n ~
DD
4
6
20
11 111 101
00 100010
<-- n ~
<-- n ~
FD
4
6
20
22
22
Notes: dd is any of the register pairs BC, DE, HL, SP.
qq is any of the registers pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)c refer to high order and low order eight bits of the register pair respectively,
e.g., BCL = C, AFH = A.
9/32
21
Z84COO
INSTRUCTION SET (continued)
16-BIT LOAD GROUP (continued)
Symbolic
Operation
Symbol
LD SP, HL
LD SP, IX
SPr HL
SPr IX
LD SP, IV
SP r
PUSH qq
(SP - 2) r
(SP - 1) r
IV
(SP - 2) r
(SP -1) r
qqL
qqH
IXL
IXH
SP~SP-2
(SP - 2) r
(SP - 1) r
IVL
IVH
POP qq
qqH r (SP + 1)
qqL r (SP)
SP~SP-2
SP~SP+2
IXH r (SP + 1)
IXL r (SP)
SP~SP+2
POP IV
IVH r (SP + 1)
IVL r (SP)
Opcode
P/V N C 76 543210
·· · · ·· ·· ··
· ··
··
·· · · ··
· ··
·
· ··
·
·
··
· ··
·
·
· ··
F9
DD
F9
FD
F9
• X • X
11 011 101
11 100101
• X • X
11 111 101
11 100101
• X • X
11 qqO 001
• X • X
11 011 101
11 100001
• X • X
11 111 101
11 100001
X
X
11
11
11
11
11
11
111
011
111
111
111
qqO
Hex
001
101
001
101
001
101
X • X
PUSH IV
POP IX
H
X
X
• X • X
SP~SP-2
PUSH IX
Flags
S Z
N° of
Bytes
N° of
N° of
T
Comments
Cycles States
M
1
2
1
2
6
10
2
2
10
1
3
11
DD
E5
2
4
15
FD
E5
2
4
15
1
3
10
DD
El
2
4
14
FD
El
2
4
14
N° of
N° of
M
T
qq
00
01
10
11
Pair
Be
DE
HL
AF
SP~SP+2
Notes: dd is any of the register pairs BC, DE, HL, SP.
qq is any of the registers pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively,
e.g., BCL = C, AFH = A.
EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS
Symbolic
Operation
Symbol
EX DE, HL,
EX AF, AF'
EXX
DE
AF
Be
DE
HL
S Z
H
X • X
X
X
X
X
-
EX (SP), IX
IX H .... (SP + 1)
IXL .... (SP)
EX (SP), IV
IV H .... (SP + 1)
IVL .... (SP)
Opcode
P/V N C 76 543210
·· ·· · ·· ·· ··
·· · · ··
HL,
AF'
.... Be'
.... DE'
+-> HL'
<->
<->
EX (SP), HL H .... (SP + 1)
L .... (SP)
Flags
· · · ··
·· · · ··
· · · ··
22
N° of
Bytes
Comments
Cycles States
11 101 011
00 001 000
11 011 001
EB
08
D9
1
1
1
1
1
1
4
4
4
• X
X
11 100011
E3
1
5
19
X
X
11 011 101
11 100011
DD
E3
2
6
23
X
X
11 111 101
11 100011
FD
E3
2
6
23
Notes: 1. If the result of B-1 is zero the Z flag is set, otherwise it is reset.
2. Z flag is set upon instruction completion only.
10132
Hex
Register
Bank and
Auxiliary
Register
Bank
Exchange
Z84COO
INSTRUCTION SET (continued)
EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS (continued)
Symbol
Symbolic
Operation
Flags
S Z
Opcode
P/V N C 76543210
H
N° of N° of
M
T
Cycles States
Hex
N° of
Bytes
2
4
16
(j)
(DE) <- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
X 0 X
LDIR
(DE) <- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
Repeat Until
BC = 0
X 0 X
LDD
(DE) <- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
X 0 X
LDDR
(DE) <- (HL)
DE <- DE - 1
HL <- HL - 1
BC <- BC - 1
Repeat Until
BC = 0
X 0 X
CPI
A <- (HL)
HL <- HL + 1
BC <- BC - 1
t t
A - (HL)
t t
LDI
t
0
11
10
101 101
100 000
ED
AD
Comments
Load (HL) into (DE),
incremellt the
pointers and
decrement the byte
counter (BC)
(j)
0
0
11
10
101 101
110 000
ED
BO
2
2
5
4
21
16
.,
0
11
10
101 101
101 000
ED
A8
2
4
16
0
11
10
101 101
111 000
ED
B8
2
2
5
4
21
16
1
11
10
101 101
100 001
ED
A1
2
4
16
1
11
101 101
ED
2
5
21
10
110 001
B1
2
4
16
1
11
10
101 101
101 001
ED
A9
2
4
16
1
11
101 101
ED
2
5
21
10
111 001
B9
2
4
16
If BC ~ 0
If BC = 0
(j)
@
X
t
X
X
t
X
t
(j)
@
t
HL <- HL + 1
BC <- BC - 1
Repeat Until
A = (HL) or BC = 0
A - (HL)
HL <- HL + 1
BC <- BC - 1
t t
A - (HL)
t t
X
t
X
X
t
X
HL <- HL + 1
BC <- BC - 1
Repeat Until
A = (HL) or BC
Notes: GJ
cv
t
(j)
@
CPDR
*
If BC 0 and
A ~ (HL)
If BC = 0 or
A = (HL)
(j)
@
CPD
If BC ~ 0
If BC = 0
(j)
@
CPIR
0
t
*
If BC 0 and
A ~ (HL)
If BC = 0 or
A = (HL)
=0
If the result of B-1 is zero the Z flag is set, otherwise it is reset.
Z flag is set upon instruction completion only.
11/32
23
Z84COO
INSTRUCTION SET (continued)
8-BIT ARITHMETIC AND LOGICAL GROUP
Symbol
ADD A, r
ADD A, n
Symbolic
Operation
Flags
PIV N C
H
S Z
Opcode
76
A<-A+r
A<-A+n
t t
t t
X
X
t
t
X
X
V
V
0
0
t
t
10
11
A <- A + (HL)
A <- A + (IX + d)
t t
t +
X
X
t
t
X
X
V
V
0 t
0 ~
10
11
10
110
101
110
7
->
101
110
<
,
0
0
0
ITQQ]
[llQ]
[iQjJ
[jJJJ
!
ITQQ]
ITQQ]
<-
r
110
011
110
d
101
<-
111
110
d
00
00
11
00
11
00
r Reg.
-000 B
001 C
010 D
011 E
100 H
101 L
111 A
-->
[QQIJ
[Q!Q]
[Q1jJ
!
Comments
101
DD
1
1
3
1
3
6
4
11
23
FD
3
6
23
s is any of r, n,
(HL), (IX+d),
(IY+d) as shown
for ADD
instruction. The
indicated bits
replace the
[QQQ] in the
ADD set above.
ITQQ]
->
ITQQ]
-->
[iQjJ
m is any of r,
(HL), (IX+d),
(IY+d) as shown
for INC. DEC
same format
and states as
INC. Replace
ITQQ] with
[iQjJ in opcode.
Z84COO
INSTRUCTION SET (continued)
GENERAL-PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
Symbol
Symbolic
Operation
Flags
t t
DM
Converters acc ;
content into packed
BCD following add or
subtract with packed
BCD operands
CPL
A
00~110
t t x a x pot
RLC (IY + d)
Comments
-
11 111 101 FD
4
6
23
11001011 CB
Reg
000
B
001
C
010
D
all
E
100
H
101
111
A
<-d-->
00~110
RLm
XOXPO'
Instruction format
~
and states are as shown
for RLC's, To form new
m ~ r,(HL),(IX+d),(IY+d)
RRCm
A
A
X
x
P
a
opeode replace ~
~
m ~ r,(HL),(IX+d),(lY+d)
RRm
~
or
RLC's with shown code,
x a x
t
P
m ~ r,(HL),(IX+d),(IY+d)
t x a x pot
SLAm
m ~ r,(HL),(IX+d),(IY+d)
~~XOXPO~
SRAm
m ~ r,(HL),(IX+d),(IY+d)
SRLm
RLD
of--!ru
t
0--17
m ~ r,(HL),(IX+d),(IY+d)
~
~
A
a
~
x a x
P
x a x
PO.
11 101 101 ED
2
5
18
Rotate digit left and
18
accumulator and
(HL)
right between the
01101111 6F
RRD
~
A
HLi
t
X
a x
PO.
11 101 101 ED
01 100 111
67
2
location (HL), The content
of the upper half of
the accumulator is
unaffected,
14/32
26
Z84COO
INSTRUCTION SET (continued)
BIT SET, RESET AND TEST GROUP
Symbolic
Operation
Symbol
BIT b, r
BIT b, (HL)
SET b, r
X
Z <- rb
X
-(IX + d)b
X
t
Z<-(lY+d)b
X
·
Z <-
rb
f-
1
,
Opcode
PIV N C
H
·· X
·· X
(HL)b
BIT b, (IX+d) b Z <-
BIT b, (IY+d)b
Flags
S Z
1 X
X
0
1 X
X
0
X 1 X
X
0
X 1 X
X
0
X
X
76 543210
N° of N° of
N° of
M
T
Bytes Cycles
States
11
01
11
01
11
11
001 011
b
r
001 011
b
110
011 101
001 011
<- d ->
110
01
b
CB
2
2
8
CB
2
3
12
DD
CB
4
5
20
111 101
001 011
<- d ->
110
01
b
FD
CB
4
5
20
11
11
11
[ill
SET b, (HL)
Hex
11
001
b
011
r
CB
2
2
8
001
b
011
110
CB
2
4
15
(HLlb <- 1
X
X
SET b, (IX+d)
(IX +d)b <- 1
X
X
011 101
001 011
<- d ->
[ill b 110
DD
CB
4
6
23
SET b, (IY +d)
(lY + d)b <- 1
X
X
11
111 101
11
001 011
d ->
<[ill b 110
FD
CB
4
6
23
a
X
X
C1Q":1
OJ]
RES b, m
mb f-
m" r, (HL),
(IX + d),
(IY + d)
11
11
Comments
r,
Reg.
--000
B
001
C
010
D
011
E
100
H
101
L
111
A
b Bit Tested
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
To form new
opcode
replace [W
of SET b, S
with
Flags and
Gill.
time states for
SET
instruction.
Notes: The notation mb indicates bit b (0 to 7) of location m.
15/32
27
Z84COO
INSTRUCTION SET (continued)
JUMP GROUP
Symbolic
Operation
Symbol
JP nn
JP cc, nn
Flags
S Z
JR NC, e
JP Z, e
JR NZ, e
N° of
Bytes
C3
3
3
10
3
3
10
Comments
X
X
11 000 011
<- n -->
<- n -->
If condition cc is true
X
X
11 cc 010
<- n -->
<- n -->
X
X
00 011 000
f- e-2 ---t
18
2
3
12
X
X
00 111 000
f- e-2 ~
38
2
2
7
2
3
12
2
2
7
If condition not
met.
If condition is
met.
PC
JR C, e
N° of N° of
M
T
Cycles States
Hex
PC <- nn
f-
nn, otherwise
continue
JR e
Opcode
PIV N C 76543210
H
PC <- PC + e
If C
If C
If C
If C
If Z
If Z
If Z
If Z
= 0, continue
= 1, PC <- PC+e
= 1, continue
= 0, PC <- PC+e
= 0 continue
= 1, PC <- PC+e
= 1, continue
= 0, PC <- PC+e
X
X
00 110 000
t-
X
X
00 101 000
f-
X
X
30
e-2 ---)
e-2
28
2
3
12
2
2
7
2
3
12
2
2
7
2
3
12
~
00 100 000
t- e-2 ----7
20
cc Condition
---000 NZ non-zero
001 Z zero
alaN C non-carry
01 t C carry
tOO PO parity odd
101 PE parity even
110 P sign positive
111 M sign negative
If condition not
met.
If condition is
met.
If condition not
met.
If condition is
met.
If condition not
met.
If condition is
met.
JP (HL)
PC <- HL
X
X
11
101 001
E9
1
1
4
JP (IX)
PC <- IX
X
X
11
11
011 101
101 001
DO
E9
2
2
8
JP (IY)
PC <- IY
X
X
11
11
111 101
101 001
FD
E9
2
2
8
DJNZ, e
8<-8-1
If B = 0, continue
If 8 " 0, PC <- PC+e
X
X
00 010 000
t - e-2 ~
10
2
2
8
If 8
2
3
13
If 8" O.
= O.
Notes: e represents the extension in the relative addressing mode. e is signed two's complement number in the range < - 126, 129 >.
e - 2 in the opcode provides an effective address of pc + e as PC is incremented by 2 prior to the addition of e.
16/32
28
Z84COO
INSTRUCTION SET (continued)
CALL AND RETURN GROUP
Symbol
CALL nn
CALL CC, nn
RET
RET cc
RETI
RETN 1
Symbolic
Operation
Flags
S
Z
Opcode
P/V N C 76 543210
H
Hex
N" of
Bytes
N" of
N" of
M
T
(SP - 1) <- PCH
(SP - 2) <- PC l
PC <- nn
X
If condition cc is
false continue,
otherwise same as
CALL nn
X
PCl <- (SP)
PCH <- (SP + 1)
X
X
If condition cc is
false continue,
otherwise same as
RET
X
X
Return from
interrupt
X
X
11
01
101
001
101
101
ED
4D
2
4
14
Return from
X
X
11
01
101 101
000 101
ED
45
2
4
14
X
X
11
1
3
11
X
11
<
n ->
cc
n
n
100
->
->
11
001
001
11
cc
000
11
<<-
CD
C9
3
5
17
3
3
10
If cc is false.
3
5
17
If cc is true.
1
3
10
1
1
5
1
3
11
interrupt
(SP - 1) <- PCH
(SP - 2) <- PCl
PCH <- 0
PCl <- P
If cc is false.
If cc is true
cc
non~maskable
RSTp
Comments
Cycles States
t
111
Condition
000 NZ Non-zero
Oat Z Zero
a tON C Non-carry
at t C Carry
100 PO Parity Odd
101 P E Parity Even
110 P Sig n Positive
111 M Sign Negative
t_ _p_
000
001
010
011
100
101
110
111
OH
08H
10H
18H
20H
28H
30H
38H
Note: RETN loads IFF2 - IFF,.
17/32
29
Z84COO
INSTRUCTION SET (continued)
INPUT AND OUTPUT GRUP
Symbol
Symbolic
Operation
Flags
S Z
IN A, (n)
A <- (n)
IN r, (C)
r <- (C)
If r = 110 only the flags
will be affected
t t
(HL) <- (C)
B<-B-l
HL <- HL + 1
X
Opcode
P/V N C 76 543 210
H
X
X
t
Hex
N° of N° of
N° of
T
M
Bytes Cycles States
11 all all
<- n ->
DB
2
3
11
Comments
n to Ao _ A7
Ace. to As - A'5
C 10 Ao A7
BID As A'5
X
p
a
11
01
101 101
r 000
ED
2
3
12
X X X
X
1 X
11
10
101 101
100 010
ED
A2
2
4
16
C to Ao _ A7
B to As - A '5
(HL) <- (C)
B<-B-l
HL<-HL+l
Repeat unil B = a
X 1 X X X
X
1 X
11
10
101 101
110 010
ED
B2
2
5
21
C 10 AD _ A7
B to As - A '5
(HL) <- (C)
B<-B-l
HL <- HL - 1
X
(HL) <- (C)
B<-B-l
HL <- HL - 1
Repeat until B = a
X 1 X X X
X
CD
INI
INIR
t
(if B*O)
2
4
16
(if B=O)
.-
CD
IND
INDR
X X X
X
X
1 X
1 X
11
10
101 101
101 010
ED
11
10
101 101
111 010
ED
BA
2
4
16
C to Ao
A7
B to As - A15
5
21
C to Ao - A7
B to As - A '5
AA
2
(if B*O)
2
4
(if B=O)
16
OUT (n), A
(n) <- A
X
X
11 010 all
<- n ->
D3
2
3
11
OUT (C), r
(C) <- r
X
X
11
01
101 101
r 001
ED
2
3
12
4
16
C to AD _ A7
B to As _ A15
5
21
C to Ao _ A7
B to As _ A15
n to Ao - A7
Acc.to As -A15
C to Ao _ A7
B to As - A15
CD
t
OUT I
(C) <- (HL)
B<-B-l
HL <- HL + 1
X
X X X
X
1 X
11
10
101 101
100 all
ED
A3
2
OTIR
(C) <- (HL)
B<-B-l
HL<-HL+l
Repeat until B = a
X 1 X X X
X
1 X
11
10
101 101
110 all
ED
B3
2
aUTO
(C) <- (HL)
B<-B-t
HL <- HL - 1
X •
X X X
X
1 X
11
10
101 101
101 all
ED
AB
2
OTOR
(C) <- (HL)
B<-B-l
HL <- HL + 1
Repeat until B = a
X 1 X X X
X
1 X
11
10
101 101
111 all
ED
2
(if B*O)
2
4
16
(if B=O)
CD
-
4
16
5
21
C 10 AD _ A7
B to As _ A,
CD
Note:
18/32
30
1. If the result of B-1 is zero the Z flag is set, otherwise it is reset.
(if B*O)
2
4
(if B=O)
16
C to Ao _ A7
B to As _ A,
"~4(;UU
SUMMARY OF FLAG OPERATION
Symbol
Operation
S
Z
PN
Sign Flag. S = 1 if the MSB of the result is 1.
Zero Flag. Z = 1 if the result of the operation is O.
Parity or Overflow Flag. Parity (P) and overflow (V) share the same flag. Logical operations affect
this flag with the parity of the result while arithmetic operations affect this flag with the overflow of
the result. If PN holds parity, PN = 1 if the result of the operation is even, PN = 0 if result is odd. If
PN holds overflow, PN = 1 if the result of the operation produced an overflow.
Half-carry Flag. H = 1 if the add or subtract operation produced a carry into or borrow from bit 4 of
the accumulator.
Add/Subtract Flag. N = 1 if the previous operation was a subtract.
Hand N flags are used in conjunction with the decimal adjust instruction (DAA) to properly correct
the result into packed BCD format following addition or subtraction using operands with packed BCD
format.
Carry/Link Flag. C = 1 if the operation produced a carry from the MSB of the operand or result.
The flag is affected according to the result of the operation.
The flag is unchanged by the operation.
The flag is reset by the operation.
The flag is set by the operation.
The flag is a "don't care".
PN flag affected according to the overflow result of the operation.
PN flag affected according to the parity result of the operation.
Anyone of the CPU Registers A, B, C, D, E, H, L.
Any 8-bit location for all the addressing modes allowed for the particular instruction.
Any 16-bit location for all the addressing modes allowed for that instruction.
Anyone of the two Index registers IX or IY.
Refresh Cou nter
8-bit Value in Range < 0.255 >
16-bit Value in Range < 0.65535 >
H
N
H&N
C
1
0
1
X
V
P
r
s
ss
ii
R
n
nn
19/32
31
Z84COO
SYMBOLIC NOTATION
Instruction
07
S Z
Do
PIV N
C
H
t
t
t
t
X
X
t
t
X
X
V
1
t
t
AND s
OR s, XOR s
t
t
X
X
1
0
X
X
P
P
0
0
0
0
INC s
t
t
t
t
t
t
ADD A, s ; ADC A, s
SUB s; SBC A, s ; CP s ;
NEG
V
0
X
t
X
V
0
X
t
X
V
X
X
X
.
1
0
t
X
X
X
V
0
.
t
X
X
X
V
1
X
0
X
RL m ; RLC m ; RR m ;
RRC m ; SLA m
SRAm ;SRLm
t
t
X
0
X
RLD ; RRD
t t
t
X
0
X
t
X
1
X
X
0
X
X
X
X
DEC s
ADD DD, ss
ADC HL, ss
SBC HL, ss
RLA, RLCA, RRA ; RRCA
DAA
CPL
SCF
t
t
A
..
.
v
CCF
IN r (C)
t t
t
Comments
8-bit Add or Add with Carry.
8-Bit subtract, subtract with carry, compare and
negate accumulator.
Logical Operations
8-bit Increment
·t
8-bit Decrement
16-bit Add
16-bit Add with Carry
0
t
t
t
P
0
t
Rotate and Shift Locations.
X
P
0
X
P
.
1
0
0
·t
·
16-bit Subtract with Carry.
Rotate Accumulator.
Rotate Digit Left and Right
Decimal Adjust Accumulator.
Complement Accumulator
1
Set Carry
t
Complement Carry
·
·
·
X
0
X
P
0
1
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
0
0
X
X
t
0
0
0
CPI ; CPIR ; CPD ; CPDR
X
t
X
X
X
t
1
Block Search Instructions. Z = 1 if A =
(HL),otherwise Z = O. PN = 1 if BC '" 0,
otherwise PN = O.
LD A, I; LD A, R
t t
X
0
X
IFF
0
The content of the interrupt enable flip-flop (IFF)
is copied into PN flag.
BIT b, s
X
t
X
1
X
X
0
The state of bit b of location is copied into the Z
flag.
INI, IND, OUTI ; OUTD
INIR ; IN DR ; OTIR ; OTDR
X
X
LDI ; LDD
LDIR ; LDDR
20/32
32
Input Register Indirect
Block Input and Output. Z = 0 if B '" otherwise
Z =0
Block Transfer Instructions. PN = 1 if BC '" 0,
otherwise PN = 0
Z84COO
PIN DESCRIPTIONS
Ao-A15. Address Bus (Output, Active High, 3-state).
Ao-A15 form a 16-bit address bus. The Address Bus
provides the address for memory data bus exchanges (up to 64 K bytes) and for 1/0 device exchanges.
BUSACK. Bus Acknowledge (Output, Active Low).
Bus Acknowledge indicates to the requesting device
that the CPU address bus, data bus, and control signals MREO, 10RO, RD, and WR have entered their
high-impedance states. The external circuitry can
now control these lines.
BUSREO. Bus Request (Input, Active Low). Bus
Request has a higher priority than NMI and is always
recognized at the end of the current machine cycle.
BUSREO forces the CPU addressJ2!!s, dal£.Qus,
and control signals MREO, 10RO, RD, and WR to
go to a high-impedance state so that other devices
can control these lines. BUSREO is normally wireORed and requires an external pullup for these applications. Extended BUSREO periods due to
extensive DMA operations can prevent the CPU
from properly refreshing dynamic RAMs.
00-07. Data Bus (Input/Output), active High, 3state). 00-07 constitute an 8-bit bidirectional data
bus, used for data exchanges with memory and 1/0.
HALT. Halt State (Output, Active Low). HALT indicates that the CPU has executed a Halt instruction
and is awaiting either a non-maskable or a maskable interrupt (with the mask enabled) before operation can be resumed.
While halted, the CPU executes NOPs to maintain
memory refresh.
INT. Interrupt Request (Input, Active Low). Interrupt
Request is generated by 1/0 devices. The CPU honors a request at the end of the current instruction
if the internal software-controlled interrupt enable
flip-flop (IFF) is enabled. INT is normally wire-O~ed
and requires an external pullup for these applications.
IORQ. Input/Output Request (Output, Active Low,
3-state). 10RO indicates that the lower half of the
address bus holds a valid I/O address for an 1/0 read
or write operation.
10RO is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that
an interrupt response vector can be placed on the
data bus.
M1. Machine Cvcle One (Output, Active Low). M 1,
together with MREO, indicates that the curr~nt machine cycle is the opcode fetch cycle of an Instruction execution. M1, together with 10RO, indicates an
interrupt acknowledge cycle.
MREQ. Memory Request (Output, Active Low, 3state). MREO indicates that the address bus holds
a valid address for a memory read or memory write
operation.
NMI. Non-Maskable Interrupt (Input, Negative
NMI has a higher priority than INT.
NMI is always recognized at the end of the current
instruction, independent of the status of the interrupt
enable flip-flop, and automatically forces the CPU
to restart at location 0066H.
~e-triggered).
RD. Read (Output, Active Low, 3-state). RD indicates that the CPU wants to read data from memory or an 1/0 device. The addressed 1/0 device or
memory should use this signal to gate data onto the
CPU data bus.
RESET. Reset (Input, Active Low). RESET initializes the CPU as follows : it resets the interrupt
enable flip-flop, clears the PC and Registers I and
R and sets the interrupt status to Mode O. During
r~set time, the address and data bus go to a highimpedance state, and all control output signals go
to the inactive state.
Note that RESET must be active for a minimum of
three full clock cycles before the reset operation is
complete.
RFSH. Refresh (Output, Active Low). RFSH,
together with MREO, indicates that the lower seven
bits of the system's address bus can be used as a
refresh address to the system's dynamic memories.
WAIT. Wait (Input, Active Low). WAIT indicates to
the CPU that the addressed memory or 1/0 devices
are not ready for a data transfer. The CPU continues
to enter a Wait state as long as this signal is active.
Extended WAIT periods can prevent the CPU from
refreshing dynamic memory properly.
WR. Write (Output, Active Low, (3-state). WR indicates that the CPU data bus holds valid data to be
stored at the addressed memory or 1/0 location.
21/32
33
Z84COO
CPU TIMING
The ZaDC CPU executes instructions by proceeding through a specific sequence of operations:
• Memory read or write
• I/O device read or write
• Interrupt acknowledge
The basic clock period is referred to as a T time or
cycle, and three or more T cycles make up a machine cycle (M1, M2 or M3 for instance). Machine
cycles can be extended either by the CPU automatically inserting one or more Wait states or by the insertion of one or more Wait states by the user.
Counter (PC) on the address bus at the start of the
cycle (figure 5). Approximately one-ha!f..Q!ock cycle
later, MREQgoes active. When active, RD indicates
that the memory data can be enabled onto the CPU
data bus.
The CPU samples the WAIT input with the falling
edge of clock state T2. During clock states T3 and
T4 of an M1 cycle dynamic RAM refresh can occur
while the CPU starts decoding and executing the instruction. When the Refresh Control signal
becomes active, refreshing of dynamic memory can
take place.
INSTRUCTION OPCODE FETCH
The CPU places the contents of the Program
Figure 5 : Instruction Opcode Fetch.
-·1
00-0,
r
~-. -I--@~"~
=-=1---E
~
OPERATION
Do-D 7
,
•
Wii
j
OPERATION
OO-D7 -
:
;
DATA OUT
23132
35
Z84COO
INPUT OR OUTPUT CYCLES
Figure 7 shows the timing for an I/O read or I/O write
operation. During I/O operations, the CPU automati-
cally inserts a single Wait state Tw). This extra Wait
state allows sufficient time for an I/O port to decode
the address from the port address lines.
Figure 7 : Input or Output Cycles.
CLOCK
WAIT
-+---+----1I------..JIo.-.L.-I'~'--'
110 {
READ
OPERATION
--I®I--
WR
WRI~~ {
I~__________~(~__________-J~I-~®~l----®_ _ _ _ _ _~----------I'~---~~~~--~
OPERATION
00-07
Note: Tw* = One Wait cycle automatically inserted by CPU.
24/32
36
~
DATA OUT
Z84COO
INTERRUPT REQUEST/ACKNOWLEDGE
CYCLE
a special M1 cycle is generated.
The CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of any instruction (figure 8). When an interrupt is accepted,
During this M 1 cycle, IORQ becomes active (instead
of MREQ) to indicate that the interrupting device can
place an 8-bit vector on the data bus. The CPU automatically adds two Wait states to this cycle.
Figure 8 : Interrupt Request/Acknowledge Cycle.
TLO
T,
T,
TWA
TWA
TW
T,
CLOCK
AO-A1. ____________4--J~------------~--~----~~,~----~--~-J~---
WAIT ____________~------------------------~----$--J
DO-D7====="'jMD~·2~
1- __--eC.I'=E~
(H(
;
Noles: 1. TL = Last state of previous instruction.
2. Two Wait cycles automatically inserted by CPU (').
~ SGS·THOMSON
..
.,I ~ll©DiI@~~I<©1i'DiI@li\Illl©$
25/32
37
Z84COO
sequent timing is similar to that of a normal instruction fetch except that data put on the bus by the
memory is ignored. The CPU instead executes a
restart (RST) operation and jumps to the NMI service routine located at address 0066H (figure 9).
NON-MASKABLE INTERRUPT REQUEST
CYCLE
NMI is sampled at the same time as the maskable
interrupt input INT bus has higher priority and cannot be disabled under software control. The subFigure 9 : Non-maskable Interrupt Request Operation.
- - - - L A S T MCYCLE
_-----.I~.t--
T,
___________M l l - - - - - - - - - - · 1
T.
T.
T,
AO-A11 _ _ _ _ _ _ _ _ _ _---1t-'.I'-+_---p-C----t-'~------t.-.-F.-.S-H+-----y
IIli
@I
___, /4-
• Although NM I is an asynchronous input, to guarantee its being recognized on the following machine cycle, NMl's falling edge must occur no later than the rising edge of the clock cycle preceding TLAST.
26/32
38
Z84COO
BUS REQUEST/ACKNOWLEDGE CYCLE
to a high-impedance state with the rising edge of the
next clock pulse. At that time, any external device
can take control of these lines, usually to transfer
data between memory and I/O devices.
The CPU samples BUSREQ with the rising edge of
the last clock period of any machine cycle
(figure 10). If BUSREQ is active,Jb? CPU sets its
address, data, and MREQ, 10RQ, RD, and WR lines
Figure 10 : Z-Bus Request/Acknowledge Cycle.
T,
CLOCK
BUSRE.Q _ _ _ _~'--+--..lo.-+-_-fr
-=::::::::::::::::::~:)
...J
___~F~LO~~~
______
__-fr____~F~LO~~~
_______
-=::::::::::::::::::~~_-fr
Ao-A,. _
Do-D7 _
___
t-¢
t-(
®
111
HALT
----------------+-------------------------UNCHANGED
Noles: 1. TL = Last state of any M cycle.
2. Tx = An arbitrary clock cycle used by requesting device.
27/32
39
Z84COO
HALT ACKNOWLEDGE CYCLE
When the CPU receives an Halt instruction it executes.NOP states until either an INT or
input
IS received. When in the Halt state, the HALT output is active and remains so until an interrupt is processed (figure 11).
NMi
for the CPU to properly accept it. As long a RESET
remains active, the address and data buses float.
and the control outputs are inactive. Once RESET
goes inactive, three internal T cycles are consumed
b~fore the CPU resumes normal processing operation. RESET clears the PC register, so the first opcode fetch will be to location 0000 (figure 12).
RESET CYCLE
RESET must be active for at least three clock cycles
Figure 11 : Halt Acknowledge Cycle.
_ _ _ I-TV'
~---------------------
MM.
Note: INT will also force a Halt exit.
, See note, Figure 9.
Figure 12 : Reset Cycle.
CLOCK
A~A1S
____
-===================r=)---(J"---------------------~~=============
-®j----~----~----~
FLOAT
-@-M1 ________________________
....J7
~--------------~r77J~~------;~'l~--------------------~r-------------
.u':i~"K
HALT
28/32
40
IIOW
\'------
Z84COO
When the system clock is supplied to the CPU ClK
terminal, CPU restarts operation continuously from
the state when power down function has been implemented.
POWER DOWN
When the CPU system clock is stopped at either a
high or low level, the CPU stops Its operation and
maintains registers and control signals.
However 1002 Stand-by Supply Current is guaranteed only when the supplied system clock is stopped
at a low level during T 4 state of the following machine cycle (actually that is M1 cycle and executes
NOP instruction) next to OPcode fetch cycle of
HALT instruction. The timing diagram when
POWER DOWN function is implemented by HALT
instruction is shown in figure 13.
This function can be easily realized when a clock
generator controller is connected with the CPU.
RELEASE FROM POWER DOWN STATE
The system clock must be supplied to the CPU to
release power down state.
Note the followings when release from power down
state.
(1) When external oscillator has been stopped to
enter power down state, some warming-up time
may be required to obtain precious and stable
system clock for release from power down state.
(2) When HALT instruction is executed to enter
power down state, the CPU will enter HALT
state. An interrupt signal (NMI or INT) or RESET
signal must be generated after the system clock
is supplied to release power down state. otherwise the CPU is stili in HALT state·even if the
system clock is supplied.
Figure 13 : Timing Diagram of Power Down Function by Halt Instruction.
~
I
~~~o:.E~~~T
'2
ClK
Mi
---l- EXECUTION Of
I NOPCMl CVCl£)
INSTRUCTION eM1CYCLE.
I
12
'J
s--
IL__
...J
...---~IS--
L . . -_ _ _ _ _- l 1 1 - - ';-1096
29132
41
Z84COO
AC CHARACTERISTICS
Parameter
N°
Symbol
1
2
3
TwCh
Clock Pulse Width (high)
TwCI
Clock Pulse Width (low)
4
TfC
Clock Fall Time
5
6
7
8
9
10
11
12
13
14
15
16
17
18*
TrC
Clock Rise Time
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TcC
Clock Cycle Time
TdCr(A)
Clock t to Address Valid Delay
TdA(MREQf)
Address Valid to MREQ J, Delay
TdCf(MREQf)
Clock J, to MREQ J, Delay
TdCr(MREQr)
Clock t to MREQ t Delay
TwMREQh
MREQ Pulse Width (high)
TwMREQI
MREQ Pulse Width (low)
TdCf(MREQr)
Clock J, to MREQ
Clock J, to RD J, Delay
TdCr(RDr)
Clock t to RD t Delay
ThD(RDr)
Data Setup Time to Clock t
Data Hold Time to RD t
TsWAIT(Cf)
WAIT Setup Time to Clock J,
ThWAIT(Cf)
WAIT Hold Time after Clock J,
TdCr(Mlf)
Clock t to MI J, Delay
TdCr(Mlr)
Clock t to MI t Delay
TdCr(RFSHf)
Clock t to RFSH J, Delay
TdCr(RFSHr)
Clock t to RFSH t Delay
TdCf(RDr)
Clock J, to RD t Delay
TdCr(RDf)
Clock t to RD J, Delay
TsD(Cf)
Clock t to IORQ J, Delay
TdCf(IORQr)
Clock J, to IORQ t Delay
TdCf(WRf)
Data Stable Prior to WR J,
TdDf(WRf)
Clock J, to WR J, Delay
WR Pulse Width
TdCf(WRr)
Clock J, to WR t Delay
TdD(WRf)
Data Stable Prior to WR J,
TdCr(WRf)
Clock t to WR J, Delay
TdWRr(D)
Data Stable from WR t
TdCf(HALT)
Clock J, to HALT tor J,
Note: • Not compatible with NMOS Specifications.
30/32
42
DC
165
65
65
DC
DC
DC
30
0
60
10
30
110
75
25
5
70
135
- 55
65
60
- 55
60
55
15
30
300
60
100
70
80
60
55
60
65
70
80
- 10
70
70
95
85
60
60
80
80
110
100
70
70
75
85
220
60
70
60
30
0
50
10
40
80
60
60
70
80
70
100
100
130
120
85
85
DC
45
100
65
135
35
0
70
10
DC
10
10
80
70
70
85
95
85
DC
20
35
110
220
125
55
55
20
20
90
85
85
180
Address Stable Prior to IORQ J,
DC
65
50
TdA(IORQf)
DC
30
30
110
Data Setup to Clock J, during
M 2 , M 3 , M4 or M5 Cycles
TdCr(IORQf)
TwWR
250
110
110
l' Delay
TdCf(RDf)
TsD(Cr)
Z84COOA Z84COOB Z84COOH
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
260
225
Z84COO
~C
CHARACTERISTICS (continued)
Z84COOA Z84COOB
Symbol
N°
37
TwNMI
38
TsBUSREO(Cr)
39* TcBUSUREO(Cr)
40
TdCr(BUSACKf)
41
TdCf(BUSACKr)
42
TdCr(Tz)
43
TdCr(CTz)
Parameter
NMI Pulse Width
1 to
Clock -1 to
Clock 1 to
Clock 1 to
-1
BUSACK 1
BUSACK
80
90
80
90
80
70
80
70
60
Data Float Delay
Clock
MREO I, IORO
Hold Time
Address Float Delay
I,
1 Setup Time
1 Hold Time
46
TsRESET(Cr)
RESET to Clock
47*
ThRESET(Cr)
RESET to Clock
48
TsINTf(Cr)
51
TdCf(IOROf)
52
TdCf(IOROr)
53
TdCf(D)
RD
10
100
Control Ou!2!!,ts Flo~
Delay (MREO. IORO, RD, and WR)
1 to
10
Delay
TdCr(Az)
ThINTr(Cr)
10
60
40
90
TdCTr(A)
TdMlf(IOROf)
1
50
100
44
50
50
Delay
45
49*
1
BUSREO Hold Time after Clock
Clock
70
80
BUSREO Setup Time to Clock
Z84COOH
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
I,
and WR
90
1
to Address
1 Setup Time
INT to Clock 1 Hold Time
MI -1 to IORO -1 Delay
Clock -1 to IORO -1 Delay
Clock 1 to IORO 1 Delay
Clock -1 to Data Valid Delay
INT to Clock
70
80
80
35
20
60
60
45
10
10
10
80
70
55
10
10
10
565
365
270
85
70
85
70
60
60
150
130
115
Note: • Not compatible with NMOS Specification.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Vcc
Vcc Supply Voltage with Respect to Vss
VIN
Input Voltage
PD
TSOLDER
Power Dissipation (T A
= 85°C)
Soldering Temperature (soldering time 10 sec)
Tst9
Storage Temperature
Topr
Operating Temperature
a..,I
~
SCiS·1HOMSON
Unit
- 0.5 to 7
V
- 0.5 to Vcc + 0.5
V
250
mW
260
°C
- 65 to 150
°C
- 40 to 85
°C
31/32
~U©IRI@rn~rn©1rIil@IllU©®
43
Z84COO
DC CHARACTERISTICS
Symbol
Min.
Typ.
Max.
Vile
Clock Input low Voltage
Parameter
Test Conditions
- 0.3
0.6
V
VIHe
Clock Input High Voltage
Vee - 0.6
-
Vee + 0.3
V
V
Unit
Vil
Input low Voltage (except ClK)
- 0.5
-
0.8
VIH
Input High Voltage (except ClK)
2.2
-
Vee
V
VOL
Output low Voltage
IOl ; 2.0 mA
-
-
0.4
V
VOHl
Output High Voltage (1)
IOH;-1.6mA
V
VOH2
Output High Voltage (2)
IOH ; - 250
JlA
III
Input leakage Current
Vss
VIN
S;
Vee
ILO
3·State Output leakage Current in
Float
Vss + 0.4
S;
VOUT
lecl
Operating Supply Current
4 MHz
6 MHz
8 MHz
lee2(1 )
Note:
Stand·by Supply Current
S;
2.4
-
-
Vee - 0.8
-
-
V
10
10
JlA
JlA
-
9
15
20
15
22
25
mA
mA
mA
-
0.5
10
JlA
S;
Vce
Vee; 5 V, VIL ; 0.2 V
VIH ; Vee - 0.2 V
Vee; 5 V
ClK; (1)
Vil ; Vee - 0.2 V
VIH ; 0.2 V
- 10
-
1. Icc2 Stand·by Current is guaranteed only when the supplied clock is stopped at a low level during T4 state of the following
machine cycle (M1) next to OPcode fetch cycle of HALT instruction.
TEST CONDITIONS
TA = - 40 "C to + 85 'c
driven at Vcc - 0.6 V for a logic "1" and 0.6 V for
a logic "0".
• Timing measurements are made at 2.2 V for a
logic "1" and 0.8 V for a logic "0".
Vcc = 5 V ± 10 %
VSS= 0 V
AC test conditions
• Inputs except ClK (clock) are driven at 2.4 V for
a logic "1" and 0.4 V for a logic "0". Clock input is
All AC parameters assume a load capacitance of
100 pF .
ORDERING INFORMATION
Temp.
Clock
Description
Z84COOAB6
Z84COOAD6
Z84COOAD2
Z84COOAC6
Type
DIP-40 (plastic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PlCC44 (plastic chip-carrier)
-40/+ 85°C
-40/+ 85°C
-55/+ 125°C
-40/+ 85°C
4 MHz
Z80C Central
Processing Unit
CMOS Version
Z84COOBB6
Z84COOBD6
Z84COOBD2
Z84COOBC6
DIP-40 (plastic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PlCC44 (plastic chip-carrier)
-40/+ 85°C
-40/+ 85°C
- 55/ + 125°C
-40/+ 85°C
6 MHz
Z84COOHB6
Z84COOHD6
Z84COOHC6
DIP-40 (plastic)
DIP-40 (ceramic)
PlCC44 (plastic chip-carrier)
-40/+ 85°C
-40/+ 85°C
-40/+ 85°C
8 MHz
32132
44
Package
Z84C10
zao DMA CMOS DIRECT MEMORY ACCESS CONTROL
• TRANSFERS, SEARCHES AND SEARCH/
TRANSFERS IN BYTE-AT-A-TIME, BURST OR
CONTINUOUS MODES. CYCLE LENGTH AND
EDGE TIMING CAN BE PROGRAMMED TO
MATCH THE SPEED OF ANY PORT
• DUAL PORT ADDRESSES (sources and destination) GENERATED FOR MEMORY-TO-I/O,
MEMORY-TO-MEMORY,
OR
I/O-TO-I/O
OPERATIONS. ADDRESSES MAY BE FIXED
OR AUTOMATICALLY INCREMENTED/DECREMENTED
• NEXT-OPERATION LOADING WITHOUT DISTURBING CURRENT OPERATIONS VIA BUFFERED STARTING ADDRESS REGISTERS.
AN ENTIRE PREVIOUS SEQUENCE CAN BE
REPEATED AUTOMATICALLY
• EXTENSIVE PROGRAMMABILITY OF FUNCTIONS. CPU CAN READ COMPLETE CHANNEL STATUS
• STANDARD Z80 FAMILY BUS-REQUEST AND
PRIORITIZED INTERRUPT-REQUEST DAISY
CHAINS IMPLEMENTED WITHOUT EXTERNAL LOGIC. SOPHISTICATED, INTERNALLY
MODIFIABLE INTERRUPT VECTORING
• DIRECT INTERFACING TO SYSTEM BUSES
WITHOUT EXTERNAL LOGIC
• SINGLE 5 V ± 10% POWER SUPPLY
• LOW POWER CONSUMPTION:
_ 5 mA TYP. AT 4 MHz
_ 6 mA TYP. AT6 MHz
_ LESS THAN 10 ~A IN POWER DOWN
MODE
• EXTENDED OPERATING TEMPERATURE
_ 40°C TO + 85 °C
o
B
DIP-40
DIP-40
(Plastic)
(CeramiC)
C
PLCC44
(PlastiC)
(Ordering Information at the end of the datasheet)
LOGIC FUNCTIONS
"'~l
0,
'"
"
..
A,
'"
DATA
BU.
"...
"...
SYSTEM
A.DDRESS
BUS
A,
'
BU' {
CONTROL
.
Z84C10
DESCRIPTION
The Z80C DMA (Direct Memory Access) is a powerful and versatile device for controlling and processing transfers of data. Its basic function of managing
CPU-independent transfers between two ports is
augmented by an array of features that optimize
transfer speed and control with little or no external
logic in systems using an 8- or 16-bit data bus and
a 16-bit address bus.
Transfers can be done between any two ports
(source and destination), including memory-to I/O,
September 1988
SYSTEM
CONTROL
BU'
1
__
.,
lORa
UREa
;w
Wi<
'0'
CE.r..vAIT _ _ _
} DMA
CONTROL
.NT/PULSE
E
I I
}
INTERRUPT
CONTROL
Vee
1/20
45
Z84C10
Figure 1 : Dual in Line Pin Configuration.
...,..
A,
A,
Ao
eLK
WR
programmable features, including variable cycle
timing and autorestart, minimize CPU softwarE
overhead. They are especially useful in adaptin(
this special-purpose transfer processor to a broa<
variety of memory, 1/0 and CPU environments .
The laDC DMA is an n-channel silicon-gate deple
tion-Ioad device and uses a single + 5 V power sup
ply and the standard laDC Family single-phasE
clock.
Rli
FUNCTIONAL DESCRIPTION
IiiiiEO
BAll
BAi
BUsAEa
cEiWAiT
A"
Au
Au
Au
An
Figure 2: Chip Carrier Pin Configuration.
6
S
4
]
1
1
41.
to)
~2
1.1
~:;
~5
25
27
26
Z84Cl0
16
19
10
21
NC
~
n
23 :U.
NO CONNECTION
memory-to-memory, and I/O-to-I/O. Dual port addresses are automatically generated for each transaction
and
may
be
either
fixed
or
incrementing/decrementing. In addition, bit-maskable byte searches can be performed either concurrently with transfers or as an operation in itself.
The laDC DMA contains direct interfacing to and independent control of system buses, as well as sophisticated bus and interrupt controls. Many
2/20
46
Classes of Operation. The laDC DMA has threE
basic classes of operation:
• Transfers of data between two ports (memory 01
1/0 peripheral)
• Searches for a particular a-bit maskable byte al
a single port in memory or an 1/0 peripheral
• Combined transfers with simultaneous searc~
between two ports
Figure 4 illustrates the basic functions served b~
these classes of operation.
During a transfer, the DMA assumes control of the
system address and data buses. Data is read from
one addressable port and written to the other addressable port, byte by byte. The ports may be programmed to be either system main memory 01
peripheral 1/0 devices. Thus, a block of data may be
written from one peripheral to another, from one
area of main memory to another, or from a peripheral to main memory and vice versa.
During a search-only operation, data is read from
the source port and compared byte by byte with a
DMA-internal register containing a programmable
match byte. This match byte may optionally be
masked so that only certain bits within the match
byte are compared.
Search rates up to 2 M bytes per second can be obtained with the 4 MHz laDC DMA or 3 M bytes per
second with the 6 MHz laDC DMA.
In combined searches and transfers, data is transferred between two ports while simultaneously
searching for a bit-maskable byte match.
Data transfers or searches can be programmed to
stop or interrupt under various conditions. In addition, CPU-readable status bits can be programmed
to reflect the condition.
MODES OF OPERATION
The DMA can be programmed to operate in one of
three transfer andlor search modes:
• 8yte-at-a-Time: data operations are performed
one byte at a time. Between each byte operation
Z84C10
Figure 3 : Typical l80C Environment.
Figure 4 : Function of the l80 DMA.
SYSTEM
BUSES
zao
OMA
If-!\ ~
,"'"
CPU
.5
!NT
'y---y'
DMA
v
I
-
INT
,-
'"
.SV
T
lEI
,---
.-
lCITO,
CTC
k=J
iNT f----
ZCfT02
block length (cont is N-t where N is the block
length).
I-
COMMANDS AND STATUS
lEa
I
lEI
f--
1. Search memory
2. Transfer memory-to-memory (optional search)
3. Transfer memory-to-IIO (optional search)
4. Search 110
5. Transfer IIO-to-I/O (optional search)
ROY
AltCA
!NT
~ TxCA
lEO
-
f----
I---
~ RI(CB
~ TxCB
I--W/RDY8 I - - -
W/AOYA
-
I
I
J
~
SIO
lEO
-
INT
lEI
ROY
DMA
1Jc---l\
~
I~
~
l
I
I
the system buses are released to the CPU. The
buses are requested again for each succeeding
byte operation.
• Burst: data operations continue until a port's
Ready line to the DMA goes inactive. The DMA
then stops and releases the system buses after
completing its current byte operation.
• Continuous: data operations continue until the
end of the programmed block of data is reached
before the system buses are released. If a port's
Ready line goes inactive before this occurs, the
DMA simply pauses until the Ready line comes
active gain.
In all modes, once a byte of data is read into the
DMA, the operation on the byte will be completed in
an orderly fashion, regardless of the state of other
signals (including a port's Ready line).
Due to the DMA's high-speed buffered method of
reading data, operations on one byte are not completed until the next byte is read in. This means that
total transfer or search block lengths must be two or
more bytes, and that block lengths programmed into
the DMA must be one byte less than the desired
The l80C DMA has several writable control registers and readable status registers available to the
CPU. Control bytes can be written to the DMA whenever the DMA is not controlling the system buses,
but the act of writing a control byte to the DMA disables the DMA until it is again enabled by a specific
command. Status bytes can also be read at any
such time, but writting the Read Status Byte command or the Initial Read Sequence command disables the DMA.
Control bytes to the DMA include those which effect
immediate command actions such as enable, disable, reset, load starting-address buffers, continue,
clear counters, clear status bits and the like. In addition, many mode-setting control bytes can be written, including mode and class of operation, port
configuration, starting addresses, block length, address counting rule, match and match-mask byte,
interrupt conditions, interrupt vector, status-affectsvector condition, pulse counting, auto restart,
Ready-line and Wait-line rules, and read mask.
Readable status registers include a general status
Figure 5 : Variable Cycle Lenght.
eLK
1-.-2.CYClE
t--
3·CYCLE
!...-
4·CYClE
-~EAALY
~~l"!
~
ENOING
FOR CONTROL SIGNALS
t----!
3/20
47
Z84C10
byte reflecting Ready-line, end-of-block, byte-match
and interrupt conditions, as well as 2-byte registers
for the current byte count, Port A address and Port
B address.
VARIABLE CYCLE
The DMA has the unique feature of programmable
operation-cycle length. This is valuable in tailoring
the DMA to the particular requirements of other system components (fast or slow) and maximizes the
data-transfer rate. It also eliminates external logic
for signal conditioning.
There are two aspects to the variable cycle feature.
First, the entire read and write cycles (periods) associated with the source and destination ports can
be independently programmed as 2, 3 or 4 T-cycles
long (more if Wait cycles are used), thereby increasing or decreasing the speed with which all DMA signals change (figure 5).
Second, the four signals in each port specifically associated with transfers of data (1/0 Request, Memory Request, Read, and Write) can each have its
active trailing edge terminated one-half T -cycle
early. This adds a further dimension of flexibility and
speed, allowing such things as shorter-than-normal
Read or Write signals that go inactive before data
starts to change.
ADDRESS GENERATION
Two 16-bit addresses are generated by the Z8DC
DMA for every transfer operation, one address for
the source port and another for the destination port.
Each address can be either variable or fixed. Variable addresses can increment or decrement from
the programmed starting address. The fixed-address capability eliminates the need for separate enabling wires to 1/0 ports.
Port addresses are multiplexed onto the system address bus, depending on whether the DMA is reading the source port or writing to the destination port.
Two readable address counters (2 bytes each) keep
the current address of each port.
AUTO RESTART
The starting addresses of either port can be reloaded automatically at the end of a block. This option is selected by the Auto Restart control bit. The
byte counter is cleared when the addresses are reloaded.
The Auto Restart feature relieves the CPU of software overhead for repetitive operations such as
CRT refresh and many others. Moreover, when the
CPU has access to the buses during byte-at-a-time
or burst transfers, different starting addresses can
4/20
48
be written into buffer registers during transfers,
causing the Auto Restart to begin at a new location.
INTERRUPTS
The Z8DC DMA can be programmed to interrupt the
CPU on three conditions:
• Interrupt on Ready (before requesting bus)
• Interrupt on Match
• Interrupt on End of Block
Any of these interrupts cause an interrupt-pending
status bit to be set, and each of them can optionally
alter the DMA's interrupt vector. Due to the buffered
constraint mentioned under "Modes of Operation",
interrupts on Match at End of Block are caused by
matches to the byte just prior to the last byte in the
block.
The DMA shares the Z8D Family's elaborate interrupt scheme, which provides fast interrupt service
in real-time applications. In a Z8DC CPU environment, the DMA passes its internally modifiable 8-bit
interrupt vector to the CPU, which adds an additional
eight bits to form the memory address of the interrupt routine table. This table contains the address
of the beginning of the interrupt routine itself. In this
process ; CPU control is transferred directly to the
interrupt routine, so that the next instruction executed after an interrupt acknowledge is the first instruction of the interrupt routine itself.
PULSE GENERATION
External devices can keep track of how many bytes
have been transferred by using the DMA's pulse
output, which provides a signal at 256-byte intervals.
The interval sequence may be offset at the beginning by 1 to 255 bytes.
The Interrupt line outputs the pulse signal in a manner that prevents misinterpretation by the CPU as
an interrupt request, since it only appears when the
Bus Request and Bus Acknowledge lines are both
active.
PIN DESCRIPTIONS
AocA15 .System Address Bus (output, 3-state). Addresses generated by the DMA are sent to both
source and destination ports (main memory or I/O
peripherals) on these lines.
BAI.Bus Acknowledge In (input, active Low). Signals that the system buses have been released for
DMA control. In multiple-DMA configurations, the
BAI pin of the highest priority DMA is normally connected to the Bus Acknowledge~n of the CPU.
Lower-priority DMAs have their BAI connected to
the BAO of a higher-priority DMA.
Z84C10
BAO .Bus Acknowledge Out (output, active Low).
In a multiple-DMA configuration, this pin signals that
no other high~riority DMA has requested the system buses. BAI and BAO from daisy chain for
multiple-DMA priority resolution over bus control.
BUSREQ .Bus Request (Bidirectional, active Low,
open drain). As an output, it sends requests for control of the system address bus, data bus and control bus to the CPU. As an input, when multiple
DMAs are strung together in a priority daisy chain
via BAI and BAO, it senses when another DMA has
requested the buses and causes this DMA to refrain
from bus requesting until the other DMA is finished.
Because it is a bidirectional pin, there cannot be any
buffers between this DMA and any other DMA. It
can, however, have a buffer between it and the CPU
because it is unidirectional into the CPU. A pull-up
resistor is connected to this pin
CE/WAIT . Chip Enable and Wait iI!QlJt, active Low).
Normally this functions only as a CE line, but it can
al.§Q.be programmed to serve a WAIT function. As
a CE line from the CPU, it becomes active when WR
and 10RO are active and the I/O port address on
the system address bus is the DMA's address,
thereby allowing a transfer of control or command
bytes from the CPU to the DMA. As a WAIT line from
memory or I/O devices, after the DMA has received
a bus-request acknowledge from the CPU, it causes
wait states to be inserted in the DMA's operation
cycles thereby slowing the DMA to a speed that matches the memory or I/O device.
CLK .System Clock (input). Standard Z80 singlephase clock at 4.0 MHz (Z80CA DMA) or 6.0 MHz
(Z80CB DMA). For slower system clocks, a TTL
gate whith a pullup resistor may be adequate to
meet the timing and voltage level specification. For
higher-speed systems, use a clock driver with an active pullup to meet the VIH specification and risetime
requirements. In all cases there should be a resistive pullup to the power supply of 10K ohms (max)
to ensure proper power when the DMA is reset.
00-07 .System Data Bus (bidirectional, 3-state).
Commands from the CPU, DMA status, and data
from memory or I/O peripherals are transferred on
these lines.
lEI . Interrupt Enable In (input, active High). This is
used with lEO to form a priority daisy chain when
there is more than one interrupt-driven device. A
High on this line indicates that no other device of
higher priority is being serviced by a CPU interrupt
service routine.
lEO .Interrupt Enable Out (output, active High). lEO
is High only if lEI is High and the CPU is not servicing an interrupt from this DMA. Thus, this signal
block lower-priority devices from interrupting while
a higher-priority device is being serviced by its CPU
interrupt service routine.
INT/PULSE .Interrupt Request (output, active Low,
open drain). This requests a CPU interrupt. The
CPU acknowledges the interrupt by pulling its 10RO
output Low during an M1 cycle. It is typically connected to the INT pin of the CPU with a pullup resistor and tied to all other INT pins in the system. This
pin can also be used to generate periodic pulses to
an external device. It can be used this way....QD.]y
when the DMA is bus master (i.e., the CPU's BUSREO and BUSACK lines are both Low and the CPU
cannot see interrupts).
IORQ .Input/Output Request (bidirectional; active
Low, 3-state). As an input, this indicates that the
lower half of the address bus holds a valid I/O port
address for transfer of control or status bytes from
or to the CPU, r~ectively ; thl£...PMA is the addressed port if its CE pin and its WR or RD pins are
simultaneously active. As an output, after the DMA
has taken control of the system buses, it indicates
that the 8-bit or 16-bit address bus holds a valid port
address for another I/O device involved in a DMA
transfer of data. When 10RO and M1 are both active simultaneously, an interrupt acknowledge is indicated.
M1 .Machine Cycle One (input, active Low). Indicates that the current CPU machine cycle is an instruction fetch. It is used by the DMA to decode the
return-from-interrupt instruction (RETI) (ED-4D)
sent b'y"!he CPU. During two-byte instruction fetches, M1 is active as each opcode byte is fetched.
An interrupt acknowledge is indicated when both M1
and 10RO are active.
MREQ .Memory Request (output, active Low, 3state). This indicates that the address bus holds a
valid address for a memory read or write operation.
After the DMA has taken control of the system
buses, it indicates a DMA transfer request from or
to memory.
RO. Read(bidirectional, active Low, 3-state). As an
input, this indicates that the CPU wants to read
status bytes from the DMA's read registers. As an
output, after the DMA has taken control of the system buses, it indicates a DMA-controlled read from
a memory or I/O port address.
ROY. Ready (input, programmable active Low or
High). This is monitored by the DMA to determine
when a peripheral device associated with a DMA
port is ready for a read or write operation. Depending on the mode of DMA operation (Byte, Burst or
Continuous), the RDY line indirectly controls DMA
5/20
49
Z84C10
activity by causing the BUSREQ line to go Low or
High.
WR Write (bidirectional, active Low, 3-state). As and
input, this indicates that the CPU wants to write control or command bytes to the DMA write registers.
As an output, after the DMA has taken control of the
system buses, it indicates a DMA-controlled write to
a memory or I/O port address.
INTERNAL STRUCTURE
zaoc
The internal structure of the
DMA includes
driver and receiver circuitry for interfacing with an
bit system data bus, a 16-bit system address bus,
and system control lines (figure 6). In a
CPU
environment, the DMA can be tied directly to the
analogous pins on the CPU (figure 7) with no additional buffering, except for the CE/WAIT line.
a-
zaoc
The DMA's internal data bus interfaces with the system data bus and seNices all internal logic and registers. Addresses generated from this logic for Ports
A and B (source and destination) of the DMA's single
transfer channel are multiplexed onto the system
address bus.
Specialized logic circuits in the DMA are dedicated
to the various fu nctions of external bus interfacing,
internal bus control, byte matching, byte counting,
periodic pulse generation, CPU interrupts, bus request, and address generation. A set of twenty-one
writable control registers and seven readable status
registers provides the means by which the CPU
governs and monitors the activities of these logic circuits. All registers are eight bits wide, with doublebyte information stored in adjacent registers. The
two address counters (two bytes each) for Ports A
and B are buffered by the two starting addresses.
The 21 writable control register are organized into
seven base-register groups, most of which have
multiple registers. The base registers in each writable group contain both control/command bits and
pointer bits that can be set to address other registers within the group. The seven readable status
registers have no analogous second-level registers.
The registers are designated as follows, according
to their base-register groups:
WRO-WR6 - Write Register groups 0 through 6
(7 base registers plus 14 associated registers)
RRO-RR6 - Read Registers 0 through 6
Writing to a register within a write-register group involves first writing to the base register, with the appropriate pointer bits set, then writing to one or more
of the other register within the group. All seven of
the readable status registers are accessed sequentially according to a programmable mask contained
in one of the writable registers. The section entitled
"Programming" explains this in more detail.
A pipelining scheme is used for reading data in. The
programmed block length is the number of bytes
compared to the byte counter, which increments at
the end of each cycle. In searches, data byte comparisons with the match byte are made during the
Figure 6: Block Diagram.
SYSTEM
OAT A
fL-J-.L......1\
BUS \~......-~.I
18 BIT)
CONTROL \~ _ _~/I
6/20
50
MUX
SYSTEM
ADDRESS
BUS
(16 f'IT)
Z84C10
Figure 7: Multiple-DMA Interconnection to the laO
cpu.
COMMON:
...-------i HUSACK
jNl'
BUSflEQ
M1
CPU
WR
elK
FROM HIGHER·PRIORITY
INTERRUPTING DEVICE
TO LOWER-PRIORITY
INTERRUPTING DEVICE
FROM
I/O
FROM
DEVICE
DEVICE
Write Registers
WRO
WR1
WR2
WR3
WR4
WR5
WR6
Base Register Byte
Port A starting Address (low byte)
Port A starting Address (high byte)
Block Length (low byte)
Block Length (high byte)
Base Register Byte
Port A Variable-timing Byte
Base Register Byte
Port B Variable-timing Byte
Base Register Byte
Mask Byte
Match Byte
Base Register Byte
Port B starting Address (low byte)
Port B starting Address (high byte)
Interrupt Control Byte
Pulse Control Byte
Interrupt Vector
Base Register Byte
Base Register Byte
Read Mask
Read Registers
RRO
RR1
RR2
RR3
RR4
RR5
RR6
Status Byte
Byte Counter (low byte)
Byte Counter (high byte)
Port A Address Counter (low byte)
Port A Address Counter (high byte)
Port B Address Counter (low byte)
Port B Address Counter (high byte)
I/O
read cycle of the next by1e. Matches are, therefore,
discovered only after the next byte is read in.
In multiple-DMA configurations, interrupt request
daisy chains are priorized by the order in which their
lEI and lEO lines are connected. The system bus,
however, may not be pre-empted.
Any DMA that gains access to the system bus keeps
the bus until it is finished.
PROGRAMMING
The laDC DMA has two programmable fundamental states: (1) an enabled state, in which it can gain
control of the system buses and direct the transfer
of data between ports, and (2) a disabled state, in
which it can initiate neither bus requests nor data
transfers. When the DMA is powered up or reset by
any means, it is automatically placed into the disabled state. Program commands can be written to
it by the CPU in either state, but this automatically
puts the DMA in the disabled state, which is maintained until an enable command is issued by the
CPU. The CPU must program the DMA in advance
of any data search or transfer by addressing it as an
I/O port and sending a sequence of control bytes
using an Output instruction (such as OTIR for the
laDC CPU).
WRITING
Control or command by1es are written into one or
more of the Write Register groups (WRO-WR6) by
first writing to the base register byte in that group.
7/20
51
Z84C10
ted registers in a group are sequentially accessed
by first writing a byte to the base register containing
register-group identification and ponter bits (1 's) to
one or more of that base register's associated registers.
This is illustrated in figure 8b. In this figure, the sequence in which associated registers within a group
can be written to is shown by the vertical position of
the associated registers. For example, if a byte written to the DMA contains the bits that identify WRO
(bits DO, 01 and 07), and also contains 1's in the bit
positions that point to the associated "Port A Starting Address (low byte)" and "PortA Starting Address
(high byte)", then the next two byte written to the
DMA will be stored in these two registers, in that
order.
FIXED-ADDRESS PROGRAMMING
A special circumstance arises when programming
a destination port to have a fixed address. The load
command in WR6 only loads a fixed address to a
port selected as the source, not to a port selected
as the destination.
Therefore, a fixed destination address must be
loaded by temporarily declaring it a fixed-source address and subsequently declaring the true source
as such, thereby implicitly making the other a destination.
The following example illustrates the steps in this
procedure, assuming that transfers are to occur
from a variable-address source (Port A) to a fixedaddress destination (Port B) :
READING
The Read Registers (RRO-RR6) are read by the
CPU by addressing the DMA as an I/O port using
an Input instruction (such as INIR for the 280C
CPU). The readable bytes contain DMA status,
byte-counter values, and port addresses since the
last DMA reset. The registers are always read in a
fixed sequence beginning with RRO and ending with
RR6. However, the register read in this sequence is
determined by programming the Read Mask in
WR6. The sequence of reading is initialized by writing an Initiate Read Sequence or Set Read Status
command to WR6. After a Reset DMA, the sequence must be initialized with the Initiate Read Sequence command or a Read Status command. The
sequence of reading all registers that are not excluded by the Read Mask register must be completed before a new Initiate Read Sequence or Read
Status command.
1. Temporarily declare Port B as source in
WRO.
2. Load Port B address in WR6.
3. Declare Port A as source in WRO.
4. Load Port A address in WR6.
5. Enable DMA in WR6.
Figure 9 illustrates a program to transfer data from
memory (Port A) to a peripheral device (Port B). In
this example, the Port A memory starting address is
1050H and the Port B peripheral fixed address is
05H. Note that the data flow is 1001 H bytes - one
more than specified by the clock length. The table
of DMA commands may be stored in consecutive
memory locations and transferred to the DMA with
an output instruction such as the 280 CPU's OTIR
instruction.
Figure Sa : Read Registers.
Read Register 0
0,
( X
0,
~
x f
o~
0] Dz 01
0,
ill
i
[x:
Do
!
I
Read Regis1er 2
I
I
STATUS B'fTE
~ READY
OM' TRANSfER HAS OCCURRED
D
ACTIVE
1
_1L.J1---1.1-L1--LI. .J. . . . L. . J1 BYTE COUNTER (l,OW BYTE)
LI
Read Register 3
:=
o=
o=
o '"
INTERRUPT PENDING
MATCH FOUND
eND OF BLOCK
LI--LI...JILJI--,-I-LI--'-....L...JI PORT A ADDRESS COUNTER !LOW BYTE)
Read Register 4:
.....LI...JI-LI-LI...J1---1.-L--,1 PORT A ADDRESS COUNTER (HIGH BYTE)
Read Register I
LI
"-'--...J:---!'"-L~..l-..L...JI
Reud Regi5ter 5
BYTE COUNTER (HIGH BYTE)
LI-LI...JILll-LI--L1.....L...L....JI PORT B ADDRESS COUNTER (l,OW BYTE)
Read Register 6
...J1L..11-L1-L1.....LI...J........LJI
LI
8/20
52
PORT B ADDRESS COUNTER (HIGH BVTE)
Z84C10
Figure 8b: Write Registers.
WrU.
R~.t ... 0
WrUe Regt.t.T" Group
Group
0, D. 01 O. 0, 0, 0, Do
D,D.D~D.D1DJD\o.
1·1 I I
I I I
10..,.Eo,STE.....
I!!
I)
I
1
00 HOT USE
' ' ' ' TRANSFER
0 - SEARCH
1 _ SEARCHITRANSFEA
I' I
I I I I DI ' 10ASEREO'S'E. Bm
t
am"! I
CONTINUOUS"" 0
BURST", 1
DO NOT PROGRAM", 1
I
0
1
II - PORT B __ PORT A-
I -' PORT It _PORT R
.-r"'-,C"'-!-'-r-'-r-,-,.., PORT A STARTING ADDRESS
L-Y'Ir'-r,-'--'---L-'
LJ.L..Jl ft~~ :~~~RTlNG ADDRESS
'-L....JLJ.,.-lTt.L.L
I I
(lOW BYTE)
.-r"'-,C"'-!"""-r-,--,-, PORT" STARTING ADDRESS
L-Y'T'--'--'--'---L-'
(HIGH bYTE)
r-r'-r-'T--r
....,..,.-,., .LOCK LENG'H
L-"Ir'--'---'-"-'-L..J ClOW
,-,r',-,-,-r,.....,....., BLOCK LENGTH
'-JLJ--l-L-L-.L--'-_l (HIGH BYTE)
101 I I I I, 10 I I
0
= PORTAlS MEMORY
, '" PORTA IS 110
0
1
= PORT A ADDRESS DECREMENTS
'" PORT It ADDRESS INCREMENTS
.~ I'"
E~DS
I
'Ir CYCLE EARLY;;!
1/
AD ENDS Vi CYCLE EARLY", 0
MREQ ENDS Yo CYCLE EARLY;; 0
INTERRUPT ON MATCH
I -' IMURRUPT AT END OF BLOCI(
I ~ PUtSE GENERATED
L-~........l--,I......LI-""I.....l.t--,I
II
VECTOR IS AUTOMATICALLY {D
MOlliFieD AS SHOWN
0
ONLYlf··STATUS
1
AHECTS VECTOR·· BIT IS SET
1
0
1
Q
1
PORT A ADDRESS FIXED
L..J~":0..LC'-'-"-'-L..J PORT A VARIABLE TIMING BYTE
WR
I I !-
I
BASE REGISTER BYTE
II !
o
II
INTERRUPT ON ROY" I
STATUS AFFECTS VECTOR -= 1
'-'-LJ,-t--l-L......I.-' PULSE COHTMOL BYTE
Write Register 1 Group
(), t\ I») 0, 0, OJ D, Dt.
I)
'-"---''":-',.,.,.,.-'--'---' INTERRUPT CONTROL BYTE
BYTE!
! !'"
: INTERRUPT ON AOY
= INTERRUPT ON MATCH
'" INTERRUPT ON END OF BLOCK
= INTERRUPT ON MATCH
AND END OF BLOCK
Write RegiSiler5 Group
0,
CYCLE LENGTH'" 4
I)
1 '" CYCLE LENGTH"" 3
1 0 = CYCLE LENGTH ",:1
1 I=DONOTUSE
0.." lORa ENDS y, CYCLE EARLY
INTERRUPT VECTOR
06 Il, O.
O,D, 0,
11 ; 0 I ! [
'0
Do
i,l I
0
BASE REGISTER BYTe
II I
o "" READY ACTIVE LOW
~ READY ACTIVE HIGH
O-C£ONlY
1 = CElWAlT MULTIPLEXED
o = STOP ON END OF BLOCK
1 '" AUTO RESTART ON END OF BLOCK
Wri.te Regtst... 2 Group
D,DID~D.DJD2Dlo.
l'IIIII·I·I·loASE.EG,S,E.oTTE
II !'" PORTa~"E"ORY
(I
o
~
1 = POR'BISIIO
::: PORT 8 ADDRESS DECREMENTS
'" PORT B ADDRESS INCAEMENTS
CI
1
~
I I
I'"
0,
D~
0,
O, III D,
D.
1, ~ I
IIIII
PORT B ADDRESS FixeD
I I ! !:::
ENOS'" CYCLE EARLY =
(I
o~
1 - CF - LOAD
OJ " CONTINUE
1
1
1
II
1
1
o
~
DO NOT USE
o
IORO ENDS ..... CYCLE EARLY
1
I
Write Register 3 Group
a,
J1
COMMANI) NAME
o=
CYCLE LENGTH", •
1 '" CYCLE LENGTH .. :I
(I,. CYCLE LENGTH ~ 2
(I
HEX
0" C3 "" RESET
1 = C7 = RESET PORT A TlNING
o ~ CB .." RESET PORT 8 TIMING
PORT B VARIABLE TIMING BYTE
!I
08
1 I 1 11 I BASE REGISTER BYTE
,I
! I I I I
WR ENDS Y.o CYCLE EARLY",
MI ENDS 'It CYCLE EARlV - 0
UlItl'l
Write Register 6 Group
1 = AF
Q =" A8
0 = A3
I '" 87
" DISABLE INTERRUPTS
~ ENABLE INTERRUPTS
'" RESET AND DISABLE INTERRUPTS
~
ENA8lE AFTER RETI
1 '" DF .= READ STATUS BYTE
II" 118 '" REINITIAlIZE STATUS BYTE
a
0
I " A7
1
0
0 = 8J "" FORCE READY
I
1
0 '" DB = READ MAS!'; FOLLOWS
~
INITIATE REAO
Se~UENCE
0, p~ D. 0) D, 0, D.
I I I I I !(I! 0 IBASE REGISTER 8YTE
~NA8lE 1 I
1=
OMA
=
INTERRUPT ENABLE - t
STOP ON MATCH
G
( 0:
L-'-"---'T'-""-,--,--,YASk BYTE 10 '" COMPAAE)
I
L-"---'"---,--'-.....l.-L-'--'
MATCH BYTE
1 = 87 '" ENABLE DMA
8l -' DISABLE OMA
o ""
0
1
!
! ! : ! ! I READ MAS": P
IIII
'" ENABl£)
om COUNTER IlOW mEl
I~
~ smusam
BYTE COUNTER (HIGH BYTE)
PORT
POtu
PORT
PORT
A
A
B
B
ADDRESS
ADDRESS
ADDRESS
ADDRESS
(LOW BYTE)
(HIGH BYTE)
(lOW BYTE)
(HIGH 8TlE)
9/20
53
Z84C10
Figure 9 : Sample DMA Program.
07
06
05
04
03
WRO sets DMA to receive
block length. Port A starting
address and temporarily sets
Port B as source.
0
1
Block Length
Upper
Follows
1
Block Length
Lower
Follows
1
Port A
Upper
Address
Follows
1
Port A
Lower
Address
Follows
Port A Address (lower)
0
1
0
1
0
Port A Address (upper)
0
0
0
1
0
Block Length (lower)
0
0
0
0
0
Block Length (upper)
0
0
0
1
0
WR1 defines Port A as memory
with fixed incrementing address.
0
1
Address
Increments
Port is Memory
WR2 defines Port B as
peripheral with fixed address.
0
WR4 sets mode to Burst, sets
DMA to expect Port B address.
1
Comments
0
0
No Timing
Follows
Address
Changes
0
1
Fixed Address
No Timing
Follows
1
0
Burst Mode
0
0
1
Port is
I/O
0
0
No Interrupt
Control Byte
Follows
No Upper
Address
Port B Address (lower)
0
0
0
0
0
WR5 Sets Ready Active High.
1
0
0
0
No Auto
Restart
No Wait
States
1
RDY
Active High
0
0
1
0
0
0
WR6 Loads Port B Address and
Resets Block Counter. *
1
1
WRO Sets Port A as Source. *
0
0
No Address or Block Length Bytes
WR6 Loads Port A Address and
Resets Block Counter.
1
1
0
0
WR6 Enables DMA to start
operation.
1
0
0
0
Note:
10/20
54
The actual number of bytes transferred is one more than specified by the block length.
• These entries are necessary only in the case of a fixed destination address.
1
Z84C10
Figure 9 : Sample DMA Program (continued).
Comments
WRO sets DMA to receive block
length. Port A starting address and
temporarily sets Port B as source.
O2
01
Do
HEX
a
a
1
79
B--7A
Temporary for
Loading B
Address'
WR1 defines Port A as memory with
fixed incrementing address.
1
a
a
a
a
a
WR2 defines Port B as peripheral with
fixed address.
a
1
a
28
WR4 sets mode to Burst, sets DMA to
expect Port B address.
1
Port BLower
Address
Follows
a
1
C5
Port A Address (lower)
Port A Address (upper)
Block Length (lower)
Block Length (upper)
a
a
a
a
Transfer, No Search
a
a
a
a
a
50
10
00
10
14
Port B Address (lower)
1
a
1
05
WR5 Sets Ready Active High.
a
1
a
8A
WR6 Loads Port B Address and
Resets Block Counter. •
1
1
1
CF
a
1
05
WRO Sets Port A as Source .•
1
A--7B
Transfer, No Search
WR6 Loads Port A Address and
Resets Block Counter.
1
1
1
CF
WR6 Enables DMA to start operation.
1
1
1
87
Note: The actual number of bytes transferred is one more than specified by the block length .
• These entries are necessary only in the case of a fixed destination address.
11/20
55
Z84C10
INACTIVE STATE TIMING (DMA as CPU Peripheral).
transactions and four T -cycles for 1/0 transactions,
which include one automatic AN INPUT ANO
THE MASK BIT IS SET TO O.
Figure 8: Interrupt Control Word.
0
0
~~'I--,,-I-'-~ IDENTInESINTE"RUPT
~
10,1 ,1 ll'ID
CONTROL WORD
0, _ 0 NO MASK WORK FOLLOWS
I
1
0, "" 1 MASK WORD fOllOWS
05 == 0 ACTIVE lEVEL IS lOW
-
Os '" 1 ACTIVE lEVEllS HIGH
Os '" 0 INTERRUPT ON OR FUNCTION
r
Figure 10 : Interrupt Disable Word.
[od 0, I0, I0.1 I 1, l' I
[0
0
-~
0
I
IDENTIFIES INTERRUPT
DISABLE WORD
DON'T CARE
06 '" 1 INTERRUPT ON A.ND FUNCTION
D, == 0 INTERRUPT DISABLE
0-, == 1 INTERRUPT ENABLE
5114
69
Z84C20
PIN DESCRIPTIONS
Ao-A7. Port A Bus (Bidirectional, 3-state). This a-bit
bus transfers data, status, or control information between Port A of the PIO and a peripheral device. Ao
is the least significant bit of the Port A data bus.
ARDY. Register A Ready(Output, Active High). The
meaning of this signal depends on the mode of operation selected for Port A as follows:
OUTPUT MODE. This signal goes active to indicate
that the Port A output register has been loaded and
the peripheral data bus is stable and ready for transfer to the peripheral device.
INPUT MODE. This signal is active when the Port A
input register is empty and ready to accept data from
the peripheral device.
BIDIRECTIONAL MODE. This signal is active when
data is available in the Port A output register for
transfer to the peripheral device. In this mode. data
is not placed on the Port A data bus, unless ASTB
is active.
CONTROL MODE. This signal is disabled and
forced to a Low state.
ASTB. Port A Strobe Pulse From Peripheral Device
(Input, Active Low). The meaning of this signal depends on the mode of operation selected for Port A
as follows:
OUTPUT MODE. The positive edge of this strobe is
issued by the peripheral to acknowledge the receipt
of data made available by the PIO.
INPUT MODE. The strobe is issued by the peripheral to load data from the peripheral into the Port A
input register. Data is loaded into the PIO when this
signal is active.
BIDIRECTIONAL MODE. When this signal is active,
data from the Port A output register is gated onto
the Port A bidirectional data bus. The positive edge
of the strobe acknowledges the receipt of the data.
CONTROL MODE. The strobe is inhibited intemally.
Bo-B7. Port B Bus (Bidirectional, 3-state). This a-bit
bus transfers data, status, or control information between Port B and a peripheral device. The Port B
data bus can supply 1.5mA at 1.5V to drive Darlington transistors. Bo is the least significant bit of the
bus.
B/""""A-.-;:;Po-rt-:-:::BC"":O:::Cr-A;-::;S:-e/;-e--:ct (Input, High = B). This pin
defines which port is accessed during a data transfer between the CPU and the PIO. A Low on this pin
selects Port A; a High selects Port B. Often address
bit
from the CPU is used for this selection function.
Ao
6/14
7D
BRDY. RegisterB Ready(Output, Active High). This
signal is similar to ARDY, except that in the Port A
bidirectional mode this signal is High when the Port
A input register is empty and ready to accept data
from the peripheral device.
BSTB. Port B Strobe Pulse From Peripheral Device
(Input, Active Low). This signal is similar to ASTB,
except that in the Port A bidirectional mode this signal strobes data from the peripheral device into the
Po!!..A input register.
C/ D. Control Or Data Select (Input, High = C). This
pin defines the type of data transfer to be performed
between the CPU and the PIO. A High on this pin
during a CPU write to the PIO causes the data bus
to be inteIPreted as a command for the port selected
by the B/A Select line. A Low on this pin means that
the data bus is being used to transfer data between
the CPU and the PIO. Often address bit A1 from the
CPU is used for this function.
CEo Chip Enable (Input, Active Low). A Low on this
pin enables the PIO to accept command or data inputs from the CPU during a write cycle or to transmit data to the CPU during a read cycle. This signal
is generally decoded from four I/O port numbers for
Ports A and B, data, and control.
ClK. System Clock (Input). The ZaDC PIO uses the
standard single-phase ZaDC system clock.
Do-D7. CPU Data Bus (Bidirectional, 3-state). This
bus is used to transfer all data and commands between the CPU and the PIO. Do is the least significant bit.
lEI. Interrupt Enable In (Input, Active High). This signal is used to form a priority-interrupt daisy chain
when more than one interrupt-driven device is being
used. A High level on this pin indicates that no other
devices of higher priority are being serviced by a
CPU interrupt service routine.
lEO. Interrupt Enable Out (Output, Active High). The
lEO signal is the other signal required to form a daisy
chain priority scheme. It is High only if lEI is High
and the CPU is not servicing an interrupt from this
PIO. Thus this signal blocks lower priority devices
from interrupting while a higher priority device is
being serviced by its CPU interrupt service routine.
INT. Interrupt Request (Output, Open Drain, Active
Low). When INT is active the PIO is requesting an
interrupt from the CPU.
lORa. Inp"utiOutput Request (Input from C~, AJd.tive Low). 10RO is used in conjunction with B/A, C/D,
CE, and RD to transfer commands and data be-
Z84C20
tween the CPU and the PIO. When CE, RD, and
10RO are active, the port addressed by BIA transfers datajQJhe CPU (a read operatio!JLConverseIy, when CE and 10RQ are active but RD is not, the
port addressed by BIA is written into from the CPU
with e..!1her data or control information, as specified
by C/D. Also, if 10RO and MI are active simultaneously, the CPU is acknowledging an interrupt; the
interrupting port automatically places its interrupt
vector on the CPU data bus if it is the highest priority
device requesting an interrupt.
MI. Machine Cycle (Input from CPU, Active low).
This signal is used as a sync pulse to contr:QLseveral internal PIO operations. When both the M1 and
RD signals are active, the CPU is fetching anlo.:.
struction frorn memory. Conversely, when both M1
and 10RO are active, the CPU is acknowledging an
interrupt. In addition, M1 has two other functions
within the PI~ it synchronizes the PIO interrupt
~ when M1 occurs without an active RD or
10RO signal, the PIO is reset.
RD. Read Cycle $Jatus (Input from CPU, Active
low). I!BD is active, or C!!J 1/0_oQeration i.§JrLQrogress, RD is used with BIA, CID, CE, and 10RO to
transfer data from the PIO to the CPU.
TIMING
The following timing diagrams show typical timing in
a zaoc CPU environment. For more precise specifications refer to the composite ac timing diagram.
WRITE CYCLE
Figure 11 illustrates the timing for programming the
zaoc PIO or for writing data to one of its ports. No
Wait states are allowed for writing to the PIO other
than the automatically inserted TWA. The PIO does
not receive a specific write signal; it internally generates its own from the lack of an active RD signal.
READ CYCLE
Figure 12 illustrates the timing for reading the data
input from an external device to one of the PIO ports.
No Wait states are allowed for reading the PIO other
than the automatically inserted TWA.
OUTPUT MODE (MODE 0)
An output cycle (figure 13) is always started by the
execution of an output instruction by the CPU. The
WR* pulse from the CPU latches the data from the
CPU data bus into the selected port's output register. The WR* pulse sets the Ready flag after a low-
going edge of ClK, indicating data is available.
Ready stays active until the positive edge of the
strobe line is received, indicating that data was
taken by the peripheral. The positive edge of the
strobe pulse generates an INT if the interrupt enable
flip-flop has been set and if this device has the highest priority.
INPUT MODE (MODE 1)
When STROBE goes low, data is loaded into the
selected port input register (fJill!.re 14). The next rising edge of strobe activates INT, if Interrupt Enable
is set and this is the highest-priority requesting device. The following falling edge of ClK resets Ready
to an inactive state, indicating that the input register
is full and cannot accept any more data until the CPU
completes a rea
RDO
\,-_ _~I
IORQ
Figure 13 : Mode D Output Timing.
eLK
PORT
OUTPUT
_ _ _---J
\--+----j~--f_-
READY
-------~
INT
INTERRUPT ACKNOWLEDGE TIMING
During M1 time, peripheral controllers are inhibited
from changing their interrupt enable status, permitting the Interrupt Enable signal to ripple through the
daisy chain. The peripheral with lEI High and lEO
Low during INTACK places a preprogrammed 8-bit
interrupt vector on the data bus at this time
(figure 17). lEO is held Low until a Return From Interrupt (RETI) instruction is executed by the CPU
while lEI is High. The 2-byte RETI instruction is
decoded internally by the PIO for this purpose.
RETURN FROM INTERRUPT CYCLE
If a Z8DC peripheral has no interrupt pending and is
not under service, then its lEO = lEI. If it has an interrupt under service (I.e., it has already interrupted
and received an interrupt acknowledge) then its lEO
8/14
72
is always Low, inhibiting lower priority devices from
interrupting. If it has an interrupt pending which has
not yet been acknowledged, lEO is Low unless an
"ED" is decoded as the first byte of a 2-byte opcode
(figure 18). In this case, lEO goes High until the next
opcode byte is decoded, whereupon it goes Low
again. If the second byte of the opcode was a "40",
then the opcode was an RETI instruction.
After an "ED" opcode is decoded, only the peripheral device which has interrupted and is currently
under service has its lEI High and its lEO Low. This
device is the highest-priority device in the daisy
chain that has received an interrupt acknowledge.
All other peripherals have lEI = lEO. If the next opcode byte decoded is "40", this peripheral device
resets its "interrupt under service" condition.
Z84C20
Figure 14: Mode 1 Input Timing.
Figure 15 : Mode 2 Bidirectional Timing.
NATA _____________________<=~~~~------__<
DATA BUS
Figure 16 : Mode 3 Bit Mode Timing.
alK
PORT
DATA BUS
INT
X
t
DATA UATCH\
CX::CURS HERE
IORQ
Rij
00- 0 7
DATA WORD 1
X
i'
DATA WORD 2
X
;
DATA IN
)
LOATA WORD 1 PLACED ON BUS
• Timing Diagram Refers to Bit Mode Read.
9/14
73
Z84C20
Figure 17 : Interrupt Acknowledge Timing.
~,;
I I I I I I
T,
T,
T_
T_
T,
±.-l
elK
iOoOANDiii
INDICATE
INTERRUPT
~WLEOQE
INTACK
100
..
Figure 18: Return From Interrupt.
----~~~--------~~~-------
110
10/14
74
1
_ _ _ _ _ _ _ _ _- - - - -.......
Gi
SGS·THOMSON
~I ~~©IiI@~~~ICiI'IiI@Il'l~©iil
Z84C20
AC CHARACTERISTICS
CLOCK
Ci
BlA. elD
RD.IORQ ____________
0.-0,
J
OUT
~--~------~-----------------Jl_------~----------+_------------
--+---..Jr---+-----'--ir-t+-___+_
1 ------------~------Jl------4--------------------'~~----------+_-----------IN
IORQ
iii
lEI
lEO
READY
(ARDY
on BMYI
STROBE
tASTB OR eSTa)
MOOED
MODE 1
MODE 2
llooE3
11/14
75
Z84C20
AC CHARACTERISTICS (continued)
N°
Symbol
Z84C20A Z84C20B
Parameter
Min. Max. Min. Max.
(ns) (ns) (ns) (ns)
1
TcC
Clock Cycle Time
250
165
2
TwCh
Clock Width (high)
105
65
3
TwCI
Clock Width (low)
105
4
TIC
Clock Fall Time
30
5
TrC
Clock Rise Time
30
6
TsCS(RI)
CE, BfA, CfD to RD, IORO,j. Setup Time
7
Th
8
TsRI(C)
9
TdRI(DO)
10
TdRI(DOs)
11
TsDI(C)
12
TdIO(DOI)
13
TsMI(Cr)
MI ,j. to Clock
14
TsMI(Cf)
MI
15
TdMI(IEO)
16
TsIEI(IO)
65
50
Any Hold Times for Specified Setup Time
40
40
i
115
RD, lORa to Clock
Setup Time
RD, lORa ,j. to Data Out Delay
RD, lORa
i
to Data Out Float Delay
Data In to Clock
i
Setup Time
i
50
90
to Clock ,j. Setup Time (MI Cycle)
0
MI ,j. to lEO ,j. Delay (interrupt immediately preceding M I ,j.)
0
190
140
lEI ,j. to lEO ,j. Delay
lEI
19
TcIO(C)
20
TdC(RDYr)
Clock ,j. to READY
Delay
190
21
TdC(RDYf)
Clock ,j. to READY ,j. Delay
140
22
TwSTB
23
TsSTB(C)
i
130
Delay (after ED decode)
lORa i to Clock ,j. Setup Time
(to activate READY on Next Clock Cycle)
i
100
100
TdIEI(IEOf)
to lEO
120
70
TdIEI(IEOr)
i
70
40
160
Setup Time
lEI ,j. to IORO,j. Setup Time (INTACK Cycle)
300
110
IORO,j. to Data Out Delay (INTACK Cycle)
i
70
380
!
18
120
160
200
150
170
170
120
STROBE Pulse Width
150
120
STROBE i to Clock ,j. Setup Time
(to activate READY on Next Clock Cycle)
220
150
i
24
TdIO(PD)
25
TsPD(STB)
PORT DATA to STROBE
26
TdSTB(PD)
STROBE ,j. to PORT DATA Stable (Mode 2),
27
TdSTB(PDr)
STROBE
lORa
to PORT DATA Stable Delay (Mode 0)
i
i
Setup Time (Mode 1)
to PORT DATA Float Delay (Mode 2)
28
TdPD(INT)
PORT DATA Match to INT ,j. Delay (Mode 2)
29
TdSTB(INT)
STROBE
i
to INT ,j. Delay
Note: • Not compatible with NMOS specifications.
76
20
50
17
12114
20
180
230
160
190
210
180
180
160
490
430
440
350
Z84C20
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Vee Supply Voltage with Respect to vss
VIN
Input Voltage
Po
Power Dissipation (T A = 85°C)
Value
Unit
- 0.5 to 7
V
- 0.5 to Vee + 0.5
V
250
mW
Soldering Temperature (soldering time 10 sec)
260
°C
TSTG
Storage Temperature
- 65 to 150
°C
TOPR
Operating Temperature
- 40 to 85
°C
TsoLoER
DC CHARACTERISTICS (1)
Symbol
Min.
Typ.
Max.
Unit
VILe
Clock Input low Voltage
Parameter
Test Conditions
- 0.3
-
0.6
V
VIHe
Clock Input High Voltage
Vee - 0.6
-
Vee + 0.3
V
VIL
Input low Voltage
(except ClK)
- 0.5
-
0.8
V
VIH
Input High Voltage
(except ClK)
2.2
-
Vee
V
Output low Voltage
IOL = 2.0 mA
-
-
0.4
V
VOH1
Output High Voltage (1)
IOH=-1.6mA
2.4
-
-
V
VOH2
Output High Voltage (2)
IOH =- 250 IlA
Vee - 0.8
-
-
V
III
Input leakage Current
Vss :5 VIN :5 Vee
-
-
± 10
!lA
IOL.
3-State Output leakage
Current in Float
Vss + 0.4 :5 VOUT :5 Vee
-
-
± 10
IlA
lee1
Operating Supply Current:
4 MHz
6 MHz
Vee =5 V, ClK =4 MHz
VIH = Vee - 0.2 V, VIL = 0.2 V
-
2
3
5
8
mA
mA
-
0.5
10
!lA
- 1.5
-
- 5.0
mA
VOL
lee2
Stand-by Supply Current
Vee =5 V, ClK =Vee
VIH = Vee - 0.2 V
VIL = 0.2 V
*loHo
Darlington Drive Current
VOH = 1.5 V, RExT = 1.1 kQ
Notes: 1. • Applied to Port B only.
2. Typical value is specified at 25 ·C.
TEST CONDITIONS
T A = - 40°C to + 85 °C
VCC= 5V± 10%
Vss = OV
AC TEST CONDITIONS
• Inputs except ClK (clock) are driven at 2.4V for
a logic "1" and 0.4V for a logic "0". Clock input is
driven at Vcc - 0.6V for a logic "1" and 0.6V for
a logic "0".
• Timing measurements are made at 2.2V for a
logic "1" and 0.8V for a logic "0".
All AC parameters assume a load capacitance of
100pF.
13/14
77
Z84C20
ORDERING INFORMATION
Type
Package
Temp.
Clock
Z84C20AB6
Z84C20AD6
Z84C20AD2
Z84C20AC6
DIP-40 (plastic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
-40/+ 85°C
-40/+ 85°C
-55/+ 125°C
-40/+ 85°C
4 MHz
Z84C20BB6
Z84C20BD6
Z84C20BD2
Z84C20BC6
DIP-40 (plaslic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
-40/+ 85°C
-40/+ 85°C
-55/+ 125°C
-40/+ 85°C
6 MHz
14/14
78
Description
Z80C Parallel I/O
Unit CMOS
Version
Z84C30
Z8DC CTC CMOS VERSION
• FOUR INDEPENDENTLY PROGRAMMABLE
COUNTERITIMER CHANNELS, EACH WITH A
READABLE DOWNCOUNTER AND A SELECTABLE 16 OR 256 PRESCALER. DOWNCOUNTERS
ARE
RELOADED
AUTOMATICALLY AT ZERO COUNT
• THREE CHANNELS HAVE ZERO COUNT/TIMEOUT OUTPUTS CAPABLE OF DRIVING
DARLINGTON TRANSISTORS
• SELECTABLE POSITIVE OR NEGATIVE TRIGGER INITIATES TIMER OPERATION
• STANDARD zaoc FAMILY DAISY-CHAIN INTERRUPT STRUCTURE PROVIDES FULLY·
VECTORED, PRIORITIZED INTERRUPTS
WITHOUT EXTERNAL LOGIC. THE CTC MAY
ALSO BE USED AS AN INTERRUPT CONTROLLER
• INTERFACE DIRECTLY TO THE zaoc CPU
OR-FOR BAUD RATE GENERATION - TO THE
zaocslo
• SINGLE 5 V ± 10% POWER SUPPLY
• LOW POWER CONSUMPTION:
_ 3 mA TYP. AT 4 MHz
_ 4 mA TYP. AT6 MHz
_ LESS THAN 10 ~ IN POWER DOWN
MODE
• EXTENDED OPERATING TEMPERATURE:
_ 40°C TO + as °C
o
B
DIP-28
(Plastic)
Dlp·28
(Ceramic)
C
PLCC44
(Plastic)
(Ordering Information at the end of the datasheet)
LOGIC FUNCTIONS
DESCRIPTION
The zaoc CTC four-channel counter/timer can be
programmed by system software for a broad range
of counting and timing applications. The four independently programmable channels of the CTC satisfy common microcomputer system requirements
for event counting, interrupt and interval timing, and
general clock rate generation.
System design is simplified because the CTC connects directly to both the CPU and the SIO with no
additional logic. In larger systems, address decoders and buffers may be required.
Programming the CTC is straightforward : each
channel is programmed with two bytes ; a third is
necessary when interrupts are enabled. Once
started, the CTC counts down, reloads its time constant automatically, and resumes counting. Software timing loops are completely eliminated.
September 1988
CHANNEL
SIGNALS
DAISY {
CHAIN
INTERRUPT
CONTROL
ze4C30
lEO
iNr
t
eLK
f
t
Vee GND
1/14
79
Z84C30
Interrupt processing is simplified because only one
vector need be specified; the CTC intemally generates a unique vector for each channel.
The Z8DC CTC requires a single + 5 V power supply and the standard Z8DC single-phase system
clock. It is fabricated with n-channel silicon-gate depletion-load technology, and packaged in a 28-pin
plastic or ceramic DIP.
Figure 1 : Dual in Line Pin Configuration.
D.
During operation, the individual counter channel
counts down from the preset time constant value. In
counter mode operation the counter decrements on
each of the CLKlTRG input pulses until zero count
is reached. Each decrement is synchronized by the
system clock. For counts greater than 256, more
than one counter can be cascaded. At zero count,
the down-counter is automatically reset with the time
constant value.
0,
0,
02
D.
0,
0,
Do
GND
Vcc.
RD
CUUTRGo
ZCJTOo
CLKlTRG1
ZClT01
CLKlTRG2
ZCIT02
CLKlTRG3
_ iORQ
es,
lEO
cs"
iNT
RESET
The timer mode determines time interval as small
as 41ls (Z8DCA) without additional logic or software
timing loops. Time intervals are generated by dividing the system clock with a prescaler that decrements a preset down-counter.
CE
eLK
lEI
M1
Figure 2 : Chip Carrier Pin Configuration.
6
'j
(.
J
2
1
lo4
4)
42
41
.too
J9
N.C
lB
N.t.
,
;0
]7
Vee
36
N.C.
N.c.
11
JS
ClK1TRG O
GND
7
N.C.
"0
lCITOO
lCITO,
12
Jl.
N.C.
lCIT02
13
)]
CLKITRGI
lORa
It.
32
CLKITRG Z
31
ClKITRG J
)0
N.C.
Z84C30
N.C.
lEO
)6
N.C.
17
18 n'-,'.,."',,"-,,-",,'-,),-'..,.',15,,-"rTO"n'-,·,.---' 5-1120
'---,n
NC
2/14
8D
~
NO CONNECTION
FUNCTIONAL DESCRIPTION
The Z8DC CTC has four independent counter/timer
channels. Each channel is individually programmed
with two words : a control word and a time-constant
word. The control word selects the operating mode
(counter or timer), enables or disables the channel
interrupt, and selects certain other operating parameters. If the timing mode is selected, the control
word also sets a prescaler, which divides the system clock by either 16 or 256. The time-constant
word is a value from 1 to 256.
Thus, the time interval is an integral multiple of the
clock period, the prescalervalue (16 or 256) and the
time constant that is preset in the down-counter. A
timer is triggered automatically when its time constant value is programmed, or by an external
CLKlTRG input.
Three channels have two outputs that occur at zero
count. The first output is a zero-count/timeout pulse
at the ZC/TO output. The fourth channel (Channel
3) does not have a ZC/TO output; interrupt request
is the only output available from Channel 3.
The second output is Interrupt Request (INT), which
occurs if the channel has its interrupt enabled during programming. When CPU acknowledges Interrupt Request, the CTC places an interrupt vector on
the data bus.
The four channels of the CTC are fully prioritized
and fit into four contiguous slots in a standard Z8DC
daisy-chain interrupt structure. Channel D is the highest priority and Channel 3 the lowest. Interrupts
can be individually enabled (or disabled) for each of
the four channels.
Z84C30
ARCHITECTURE
places a unique interrupt vector on the data bus.
The CTC has four major elements, as shown in
figure 3.
• CPU bus I/O
• Channel control logic
• Interrupt logic
• Counter/timer circuits
If an interrupt is pending, the interrupt logic holds
lEO Low. When the CPU issues a Return From Interrupt (RETI) instruction, each peripheral device
decodes the first byte (ED16). If the device ha~
pending interrupt, it raises lEO (High) for one Ml
cycle. This ensures that all lower priority devices can
decode the entire RETI instruction and reset properly.
CPU BUS I/O
The CPU bus I/O circuit decodes the address inputs,
and interfaces the CPU data and control signals to
the CTC for distribution on the internal bus.
INTERNAL CONTROL LOGIC
The CTC internal control logic controls overall chip
operating functions such as the chip enable, reset,
and read/write logic.
COUNTER/TIMER CIRCUITS
The CTC has four independent counter/timer circuits, each containing the logic shown in figure 4.
CHANNEL CONTROL LOGIC
The interrupt control logic ensures that the CTC interrupts interface properly with the Z80C CPU interrupt system. The logic controls the interrupt priority
of the CTC as a function of the lEI signal. If lEI is
High, the CTC has priority. During interrupt processing, the interrupt logic holds lEO Low, which inhibits
the interrupt operation on Lower priority devices. If
the lEI input goes Low, priority is relinquished and
the interrupt logic drives lEO Low.
The channel control logic receives the 8-bit channel
control word when the counter/tirner channel is prograrnmed. The channel control logic decodes the
control word and sets the following operating conditions:
• Interrupt enable (or disable)
• Operating mode (timer or counter)
• Timer mode prescaler factor (16 or 256)
• Active slope for CLKlTRG input
• Timer mode trigger (automatic or CLKITRG
input)
• Time constant data word to follow
• Software reset
If a channel is programmed to request an interrupt,
the interrupt logic drives lEO Low at the zero count,
and generates an INT signal to the CPU. When the
CPU responds with interrupt acknowledge (Ml and
10RO), then the interrupt logic arbitrates the CTC
internal priorities, and the interrupt control logic
TIME CONSTANT REGISTER
When the counter/timer channel is programmed, the
time constant register receives and stores an 8-bit
time constant value, which can be anywhere from 1
to 256 (0 = 256). This constant is automatically
INTERRUPT LOGIC
Figure 3: Functional Block Diagrarn.
DATA
FROM
{
ZOO CPU
CONTROL
CPU
BUS
INT
~IEI
"0
zcrro
ClKITRG
3/14
81
Z84C30
Figure 4 : Counterl Timer Block Diagram.
PROGRAMMING
zaoc
Each
CTC channel must be programmed
prior to operation.
INTERNAL BUS
ZC/TO
ClKfTRG -----i~1
CLOCK
--1
.RESCALER
~
loaded into the down-counter when the counterltime
channel is initialized, and subsequently after each
zero count.
PRESCALER
The prescaler, which is used only in timer mode
divides the system clock frequency by a factor of
either 16 or 256. The prescaler output clocks the
down-counter during timer operation. The effect of
the prescaler on the down-counter is a multiplication
of the system clock period by 16 or 256. The prescaler factor is programmed by bit 5 of the channel
control word.
DOWN COUNTER
Prior to each count cycle, the down-counter is
loaded with the time constant register contents. The
coun~er is then decremented one of two ways, depending on operating mode:
• By the prescaler output (timer mode)
• By the trigger pulses into the CLKlTRG input
(counter mode)
Without disturbing the down-count, the CPU can
read the count remaining at any time by performing
an 1/0 read operation at the port address assigned
to the CTC channel. When the down-counter
reaches the zero count, the ZC/TO output gener~tes a positive-going pulse. When the interrupt
IS enabled, zero count also triggers an interrupt request signal (INT) from the interrupt logic.
4/14
82
Programming consists of writing two words to the
1/0 port that corresponds to the desired channel.
The first word is a control word that selects the operating mode and other parameters; the second word
is a time constant, which is a binary data word with
a value from 1 to 256. A time constant word must
be preceded by a channel control word.
After initialization, channels may be reprogrammed
at any time. If updated control and time constant
words are written to a channel during the count operation, the count continues to zero before the news
time constant is loaded into the counter.
If the interrupt on any CTC channel is enabled, the
programming procedure should also include an interrupt vector. Only one vector is required for all four
chan~els, because the interrupt logic automatically
modifies the vector for the channel requesting service.
A control word is identified by a 1 in bit O. A 1 in
bit 2 indicates a time constant word is to follow. Interrupt vectors are always addressed to Channel 0,
and identified by a 0 in bit o.
ADDRESSING
During programming, channels are addressed with
the channel select pins CS1 and CS2. A 2-bit binary
code selects the appropriate channel as shown in
the following table
Channel
CS1
CSo
a
a
1
a
a
2
3
1
1
1
a
1
RESET
The CTC has both hardware and software resets.
The hardware reset terminates all down-counts and
disables all CTC interrupts by resetting the interrupt
bits in the control registers. In addition, the ZO/TO
and Interrupt outputs go inactive, lEO reflects lEI,
and 00-07 go to the high-impedance state. All channels must be completely reprogrammed after a
hardware reset.
The software reset is controlled by bit 1 in the channel control word. When a channel receives a soft-
Z84C30
""are reset, it stops counting. When a software reset
IS used, the other bits in the control word also
:hange the contents of the channel control register.
A.fter a software reset a new time constant word
must be written to the same channel.
If the channel control word has both bits 01 and 02
set to 1, the addressed channel stops operating,
pending a new time constant word. The channel is
ready to resume after the new constant is programmed. In timer mode, if 03 = 0, operation is triggered automatically when the time constant word is
loaded.
CHANNEL CONTROL WORD PROGRAMMING
The channel control word is shown in figure 5. It sets
the modes and parameters described below.
Interrupt Enable. D~ables the interrupt, so that
an interrupt output (INT) is generated at zero count.
Interrupts may be programmed in either mode and
may be enabled or disabled at any time.
OPERATING MODE
06 selects either timer or counter mode.
Prescaler factor (Timer Mode Only). 05 selects factor-either 16 or 256.
Trigger slope. 04 selects the active edge or slope of
the CLKlTRG input pulses. Note that reprogramming the CLKlTRG slope during operation is equivalent to issuing an active edge. If the trigger slope is
changed by a control word update while a channel
is pending operation in timer mode, the result is the
same as a CLKITRG pulse and the timer starts.
Similarly, if the channel is in counter mode, the
counter decrements.
Trigger mode (timer mode only). 03 selects the trigger mode for timer operation. When 03 is reset to 0,
the timer is triggered automatically. The time constant word is programmed during an 1/0 write operation, which takes one machine cycle. At the end of
the write operation there is a setup delay of one
clock period. The timer starts automatically (decrements) on the rising edge of the second clock pulse
(T2) of the machine cycle following the write operation. Once started, the timer runs continuously. At
zero count the timer reloads automatically and continues counting without interruption or delay, until
stopped by a reset.
When 03 is set to 1, the timer is triggered externally
through the CLKITRG input. The time constant word
is programmed during an 1/0 write operation, which
takes one machine cycle. The timer is ready for
operation on the rising edge of the second clock
pulse (T2) of the following machine cycle. Note that
the first timer decrement follows the active edge of
the CLKlTRG pulse by a delay time of one clock
cycle if a minimum setup time to the riSing edge of
clock is met. If this minimum is not met, the delay is
extended by another clock period. Consequently,
for immediate triggering, the CLKITRG input must
precede T2 by one clock cycle plus its minimum
setup time. If the minimum time is not met, the timer
will start on the third clock cycle (T 3).
Once started the timer operates continuously, without interruption or delay, until stopped by a reset.
Time constant to follow. A 1 in 02 indicates that the
next word addressed to the selected channel is a
time constant data word for the time constant register. The time constant word may be written at any
time.
A 0 in 02 indicates no time constant word is to follow. This is ordinarily used when the channel is already in operation and the new channel control word
Figure 5 : Channel Control Word ..
1 ENABLES INTERRUPT
INTERRUPT
INTERRUPT
o DISABLES
JJ
J
CONTROL OR VECTOR
VECTOR
1 -:: CONTROL WORD
o :::
MODE
RESET
o SELECTS TIMER MOOE
1 SELECTS COUNTER MODE
o -'
CONTINUED OPERATION
1 .::: SOFTWARE RESET
PRESCAlER VALUE·
1 ~ VALUE OF 256
:= VALUE OF 16
TIME CONSTANT
o
o
ClKITRQ EDOE SELECTION
o SElECTS FAt LING EDGE
1 SELECTS RISING EDGE
1
L..-_ _ _
NO TIME CONSTANT FOLLOWS
= TIME CONSTANT FOLLOWS
=:
TIMER TRIGGER-
a
:= AUTOMATIC TRIGGER WHEN
TIME CONST ANT IS LOADED
1 -= ClK!TAG PUlSf STARTS TIMER
"TIMER MODE ONt Y
5/14
83
Z84C30
is an update. A channel will not operate without a
time constant value. The only way to write a time
constant value is to write a control word with 02 set.
• The time constant (T), which is programmed into
the time constant register.
Control word. Setting Do to 1 identifies the word as
a control word.
Consequently, the time interval is the product of $ x
P x T. The minimum timer resolution is 16 x $ (411s
with a 4 MHz clock). The maximum timer interval is
256 x $ x 256 (16.4 ms with a 4 MHz clock). For
longer intervals timers may be cascaded.
TIME CONSTANT PROGRAMMING
INTERRUPT VECTOR PROGRAMMING
Software reset. Setting 01 to 1 causes a software
reset, which is described in the Reset section.
Before a channel can start counting it must receive
a time constant word from the CPU. During programming or reprogramming, a channel control
word in which bit 2 is set must precede the time constant word to indicate that the next word is a time
constant. The time constant word can be any value
from 1 to 256 (figure 6). Note that 0016 is interpreted
as 256.
In timer mode, the time interval is controlled by three
factors:
• The system clock period ($)
• The prescaler factor (P), which multiplies the interval by either 16 or 256
If the CTC has one or more interrupts enabled, it can
supply interrupt vectors to the CPU. To do so, the
CTC must be pre-programmed with the most-significant five bits of the interrupt vector. Programming
consists Of writing a vector word to the 1/0 port corre·
sponding to the CTC Channel O. Note that Do of the
vector word is always zero, to distinguish the vector
from a channel control word. 01 and 02 are not used
in programming the vector word. These bits are supplied by the interrupt logic to identify the channel requesting interrupt service with a unique interrupt
vector (figure 7). Channel 0 has the highest priority .
PIN DESCRIPTIONS
Figure 6 : Time Constant Word.
10, I0, I0, I0.1 0, 10, I I I
D,
Do
~~~~J ~~~~
Figure 7 : Interrupt Vector Word.
Vl-VJ~
SUPPLIED
BY USER
L
0 '"' INTERRUPT VECTOn. WORD
1 '" CONTROL WORD
CHANNEllDENTtnER
(AUTOMA TlCALL Y INSERTED
BY eTC)
o 0 '" CHANNEL 0
o 1 = CHANNEL 1
1 0 = CHANNEl:2
1 1 = CHANNEL J
CEo Chip Enable (input, active low). When enabled
the CTC accepts control words, interrupt vectors, or
time constant data words from the data bus during
an 1/0 write cycle; or transmits the contents of the
down-counter for the CPU during an 1/0 read cycle.
In most applications this signal is decoded from the
eight least significant bits of the address bus for any
of the four 1/0 port addresses that are mapped to
the four counter-timer channels.
ClK. System Clock (input). Standard singlephase
Z80C system clock.
CLKITRGo-CLKlTRG3. External ClocklTimer Trigger(input, user-selectable active High or low). Four
pins corresponding to the four CTC channels. In
counter mode, every active edge on this pin decrements the down-counter. In timer mode, an active
edge starts the timer.
CSO-CS1. Channel Select (inputs active High). Twobit binary address code selects one of the four CTC
channels for an 1/0 write or read (usually connected
to Ao and A1).
00-07. System Data Bus (bidirectional, 3-state).
Transfers all data and commands between the CPU
and the CTC.
lEI. Interrupt Enable In (input, active High). A high
indicates that no other interrupting devices of higher
priority in the daisy chain are being serviced by the
CPU.
6/14
84
Z84C30
EO. Interrupt Enable Out (output, active High). High
Inly if lEI is High and the CPU is not servicing an inerrupt from any CTC channel. lEO blocks lower
Iriority devices from interrupting while a higher
Iriority interrupting device is being serviced.
NT. Interrupt Request (output, open drain, active
.ow). Low when any CTC channel that has been
Irogrammed to enable interrupts has a zero-count
:ondition in its down-counter.
ORO. Input/Output RequeslJjnput from CPU, acive Low). Used with CE and RD to transfer data and
:hannel control words between the CPU and the
~TC"J2uring a write cycle IORO and CE are active
tnd RD inactive. The CTC does not receive a spe:ific write signal; rather, it internallyJJenerates its
)wn from the inverse of an active RD signal. In a
ead cycle, IORO, CE and RD are active; the conents of the-1!gwn-counter are read by the CPU. If
ORO and M1 are both true, the CPU is acknowedging an interrupt request, and the highest priority
nterrupting channel places its interrupt vector on the
lata bus.
WRITE CYCLE TIMING
Figure 10 shows write cycle timing for loading control, time constant or vector words.
The CTC does not have a write signal ifJQ!dt, so it
generates one internally when the readlBQ) input
is High during h During T2 IORO and CE inputs
are Low. M1 must be High to distinguish a write cycle
from an interrupt acknowledge. A 2-bit binary code
at inputs CS1 and CSa selects the channel to be addressed, and the word being written is placed on the
data bus. The data word is latched into the appropriate register with the rising edge of clock cycle T 3.
TIMER OPERATION
In the timer mode, a CLKlTRG pulse input starts the
timer (figure 11) on the second succeeding rising
Figure 8: A Typical Z80C Environment.
1111. Machine~cle One (input from CPU, active
.ow). When M1 and IORO are active, the CPU is
Icknowledging an interrupt. The CTC then places
tn interrupt vector on the data bus if it has highest
lriority, and if a channel has requested an interrupt
INT).
SYSTEM
BUSES
.5 V
:10. Read Cycle Status (inp~active Low). Used in
;onjunction with IORO and CE to transfer data and
;hannel control words between the CPU and the
CPU
iNT
~TC.
~ESET. Reset (input active Low). Terminates all
Jown-counts and disables all interrupts by resetting
he interrupt bits in all control registers; the ZC/TO
md the Interrupt outputs go inactive; lEO reflects
EI ; DO-D7 go to the high-impedance state.
riMING
'lEAD CYCLE TIMING
=igure 9 shows read cycle timing. This cycle reads
:he contents of a down-counter without disturbing
he count. During clock cycle T2, the CPU initiates a
'ead cycle bYJiriving the following inputs Low: RD,
ORO, and CEo A 2-bit binary code at inllli!.s CS1
3.nd CSa selects the channel to be read. M1 must
)e High to distinguish this cycle from an interrupt ac--
CD--
caD. cs,
IX
1(
1-0-------
~I
.I
~
co
~I
.~
A.AD
.I
~
IORG
1--0-+
CD-I+-I
L
\,
I-<">-
Iiii
~I
DATA
~
"
X
caD. el,
1(
I----
1£0 21
21l
u'" u .............
z
I: I:; I:; i~ ~ f ~ I~ I~ I~ '<1
NC
39
l1)fiO
9
>--
0-
......
U
0
.........
0
~Qu
....
u
RR_OB
PR.ce
pflea
PbOB
P
N.C.
s.-u~
= No Connection.
trois High and disables all interrupts. The control
registers must be rewritten after the SIO is reset and
before data is transmitted or received.
RTSA, RTSB. Request To Send (Outputs, Active
Low). When the RTS bit in Write register 5
(figure 14) is set, the RTS output goes Low. When
the RTS bit is reset in the Asynchronous mode, the
output goes High after the transmitter is empty. In
Synchronous modes, the RTS pin strictly follows the
state of the RTS bit. Both pins can be used as
general-purpose outputs.
SYNCA, SYNCB. Synchronization (Inputs/Outputs,
In the internal synchronization mode (Monosync
and Bisync) these pins act as outputs that are active during the part of the receive clock (RxC) cycle
in which sync characters are recognized. The sync
condition is not latched so these outputs are active
each time a sync pattern in recognized, regardless
of character boundaries.
zaoc
In the
omitted.
S10-2 bonding option, SYNCB is
TxCA, TxCB. Transmitter Clocks (Inputs). In asynchronous modes, the Transmitter Clocks may be 1,
16, 32 or 64 times the data rate; however, the clock
multiplier for the transmitted and the receiver must
be the same. The transmit Clock inputs are Schmitttrigger buffered for relaxed rise- and fall-time requirements (no noise level margin is specified).
zaoc
Transmitter Clocks may be driven by the
CTC
Counter Timer Circuit for programmable baud rate
generation. In the
SIO-O bonding option,
TxCB is bonded together with RxCB.
zaoc
TxOA, TxOB. Transmitt Data (Outputs, Active
High). Serial data at TTL levels. TxD changes from
the falling edge of TxC.
W/ROYA, W/ROYB. Wait/Ready A, Wait/Ready B
(Outputs, Open Drain when Programmed for Wait
Function, Driven High and Low when Programmed
for Ready Function). These dual-purpose outputs
may be programmed as Ready lines for a DMA controller or as Wait lines that synchronize the CPU to
the SIO data rate. The reset state is open drain.
5/24
97
Z84C40-Z84C41-Z84C42
Figure 8 : Block Diagram.
_ } SERIAL DATA
:::=-}
CHANNEL CLOCKS
SYNC
WAlTrnEADi
INTERNAL
CONTROL
tOCIC
-
CHANNEL It
CONTROL
AND
_)
MOOEMOR
OTHER CONTROLS
STATUS
CONTROL
MODEM 01>
OTHER CONTROLS
INTERRUPT
CONTROL
INTERRUPT
=}
CONTROL
lOGIC
\
SERIAL OATA
CHANNEL CLOCKS
SYNC
WAlT'READY
FUNCTIONAL DESCRIPTION
The functional capabilities of the l8DC 810 can be
described from two different points of view : as a
data communication device, it transmits and receives serial data in a wide variety of data-communication protocols ; as a l8DC family peripheral, it
interacts with the l8DC CPU and other peripheral
circuits, sharing the data, address and control
buses, as well as being a part of the l8DC interrupt
structure. As a peripheral to other microprocessors,
the 810 offers valuable features such as non-vectored interrupts, polling and simple handshake capability.
Figure 9 illustrates the conventional devices that the
810 replaces.
The first part of the following discussion covers 810
data-communication capabilities; the second part describes interactions between the CPU and the 810.
Figure 9 : Conventional Devices Replaced by l8DC 810.
.
CHANNEL
CHANN.!L
B
MICROPROCESSOR
INTERFACE
6/24
98
___
.
-
CHANNEL
-
CHANNEL
Z80C
"0
.
Z84C40-Z84C41-Z84C42
DATA COMMUNICATION CAPABILITIES
The SIO provides two independent full-duplex channels that can be programmed for use in any common
asynchronous or synchronous data-communication
protocol. Figure 10 illustrates some of these protocols. The following is a short description of them. A
more detailed explanation of these modes can be
found in the Z8D Family Technical Manual.
ASYNCHRONOUS MOOES
Transmission and reception can be done independently on each channel with five to eight bits per
character, plus optional even or odd parity. The
transmitters can supply one, one-and-a-half or two
stop bits per character and can provide a break output at any time. The receiver break-detection logic
interrupts the CPU both at the start and end of a received break. Reception is protected from spikes by
a transient spikerejection mechanism that checks
the signal one-half a bit time after a Low level is detected on the receive data input (RxOA or RxOB in
figure 6). If the Low does not persist - as in the case
of a transient - the character assembly process is
not started.
Framing errors and overrun errors are detected and
buffered together with the partial character on which
they occurred. Vectored interrupts allow fast servicing of error conditions using dedicated routines. Furthermore, a built-in checking process avoids
interpreting a framing error as a new start bit: a framing error results in the addition of one-half a bit time
to the point at which the search for the next start bit
is begun.
The SIO does not require symmetric transmit and
receive clock signals - a feature that allows it to be
used with a Z80C CTC or many other clock sources. The transitter and receiver can handle data at
a rate of 1, 1/16, 1/32 or 1/64 of the clock rate supplied to the receive and transmit clock inputs.
In asynchronous modes, the SYNC pin may be programmed as an input that can be used for functions
such as monitoring a ring indicator.
SYNCHRONOUS MOOES
The SIO supports both byte-oriented and bit
oriented synchronous communication.
Synchronous byte-oriented protocols can be
handled in several modes that allow character synchronization with an 8-bit sync character (Monosync), any 16-bit sync pattern (Bysinc), or with an
external sync signal. Leading sync characters can
be removed without interrupting the CPU.
Five-, six- or seven-bit sync characters are detected
with 8- or 16-bit patterns in the SIO by overlapping
the larger pattern across multiple in-coming sync
characters, as shown in figure 11 .
CRC checking for synchronous byte-oriented
modes is delayed by one character time so the CPU
may disable CRC checking on specific characters.
This permits implementation of protocols such as
IBM Bisync.
Both CRC-16 (X16 + X15 + X2 + 1) and CCITT (X16
+ X12 + X5 + 1) error checking polynomials are supported. In all non-SOLC modes, the CRC generator
is initialized to O's ; in SOLC modes, it is initialized
to 1 'So The SIO can be used for interfacing to peripherals such as hard-sectored floppy disk, but it cannot generate or check CRC for IBM-compatible
soft-sectored disks. The SIO also provides a feature
that automatically transmits CRC data when no
other data is available for transmissions. This allows
very high-speed transmissions under OMA control
with no need for CPU intervention at the end of a
message. When there is no data or CRC to send in
synchronous modes, the transmitter inserts 8- or
16-bit sync characters regardless of the programmed character length.
The SIO supports synchronous bit-oriented protocols such as SOLC and HOLC by performing automatic flag seding, zero insertion and CRC
generation. A special command can be used to
abort a frame in transmission. At the end of a message the SIO automatically transmits the CRC and
trailing flag when the transmit buffer becomes
empty. If a transmit underrun occurs in the middle
of a message, an external/status interrupt warns the
CPU of this status change so that an abort may be
issued. One to eight bits per character can be sent,
which allows reception of a message with no prior
information about the character structure in the information field of a frame.
The receiver automatically synchronizes on the
leading flag of a frame in SOLC or HOLC, and provides a synchronization signal on the SYNC pin; an
interrupt can also be programmed. The receiver can
be programmed to search for frames addressed by
a single byte to only a specified user-selected address orto aglobal broadcast address. In this mode,
frames that do not match either the user-selected or
broadcast address are ignored. The number of address bytes can be extended under software control. For transmitting data, an interrupt on the first
received character or on every character can be selected. The receiver automatically deletes all zeroes
inserted by the transmitter during character assembly. It also calculates and automatically checks the
CRC to validate frame transmission. At the end of
7/24
99
Z84C40-Z84C41-Z84C42
transmission, the status of a received frame is available in the status registers.
ceived. The CPU then enables the DMA to transfer
the message to memory. The SIO then issues an
end-of-frame interrupt and the CPU can check the
status of the received message. Thus, the CPU is
freed for other service while the message is being
received.
The SIO can be conveniently used under DMA control to provide high-speed reception or transmission.
In reception, for example, the SIO can interrupt the
CPU when the first character of a message is reFigure 10 : Some Z80C SIO Protocols.
!siOP
PARITY
STtR1
M-A-R-K'N-G-l-'NE-~II
DATA
I I'
11r-DA-'-A""Tj""I""'-'11
DATA
II
i
, MARKING UNE
ASYNCHRONOUS
::
DATA
SYNC
I
DATA
CRC,
CRe,
DATA
CRC,
CRC~
DATA
CRC,
CRe,
CRC,
CRC1
MOHOSYHC
SYNC
SYNC
::
DATA
SiGNAL
I
+
BISYNC
~:
DATA
EXTERNAL SYNC
flAG
I
ADDRESS
I
INFO~M;TlON
flAG
SDLC/HDLC/X.25
Figure 11 : Six Bit Sync Character Recognition.
6 BITS
SYN~
---------..
SYNC
~
" _______~~____
8---II
8/24
100
DATA
DATA
DATA
DATA
Z84C40-Z84C41-Z84C42
5T ATU5 FLOW-CHART
Figure 12a : Status Flowchart.
Figure 12b : Status Flowchart.
CIIl-l
CE.IORO_O
RD:O
CID:O
CE.IORO:O
AD=1
DO
D 1
DN
PARtTY BIT
STOP BIT .,"
NO
NO
NO
5-8685
9/24
t01
Z84C40-Z84C41-Z84C42
Figure 12c : Status Change Flowchart.
TRANSMIT INTERRUPTION
1. ADDRESS (00·07)
2. TRANSMIT DATA
(00·07)
NO
-1
CRC (O()'D15)
CLOSE FLAG TRANSFER
(7EH)
~8686
10/24
102
Z84C40-Z84C41-Z84C42
Figure 12d : Status Change Flowchart.
hC INPUT
elD",,1
C~. IORO.O
RO=O
CID=O
CE.IORO"O
AD=1
TRANSMIT INTERRUPTION
-m
01
OO
.
07
NO
NO
CRC (00·015)
SVNCH 1 (0()'07)
SVNCH 2 (00·07)
5-S687
11/24
103
Z84C40·Z84C41·Z84C42
Figure 12e : Status Flowchart.
12/24
104
Z84C40-Z84C41-Z84C42
I/O INTERFACE CAPABILITIES
The SIO offers the choice of polling, interrupt, (vectored or non-vectored) and block-transfers modes
to transfer data, status and control information to
and from the CPU. The block-transfer mode can
also be implemented under DMA control.
POLLING
Two status registers are updated at appropriate
times for each function being performed (for
example, CRC error-status valid at the end of a
message). When the CPU is operated in a polling
fashion, one of the SIO's two status registers is used
to indicate whether the SIO has some data or needs
some data.
Depending on the contents of this register, the CPU
will either write data, read data, or just go on. Two
bits in the register indicate that a data transfer is
needed. In addition, error and other conditions are
indicate. The second status register (special receive
conditions) does not have to be read in a polling
sequence, until a character has been received. All
interrupt modes are disabled when operating the device in a polled environment.
INTERRUPTS
The SIO has an elaborate interrupt scheme to
provide fast interrupt service in real-time applications. A control register and a status register in
Channel B contain the interrupt vector. When programmed to do so, the SIO can modify three bits of
the interrupt vector in the status register so that it
points directly to one of eight interrupt service routines in memory, thereby servicing conditions in both
channels and eliminating most of the needs for a
status-analysis routine.
Transmitt interrupts, receive interrupts and external/status interrupts are the main sources of interrupts. Each interrupt source is enabled under
program control, with Channel A having a higher
priority than Channel B, and with receive, transmit
and external/status interrupts prioritized in that order
within each channel. When the transmit interrupt is
enabled, the CPU is interrupted by the transmit buffer becoming empty. (This implies that the transmitter must have had a data character written into it so
it can become empty). The receiver can interrupt the
CPU in one or two ways:
• Interrupt on first received character
• Interrupt on all received characters
these interrupt modes will also interrupt under special receive conditions on a character or message
basis (end-of-frame interrupt in SDLe, for example).
This means that the special-receive condition can
cause an interrupt only if the interrupt-on-first-received-character or interrupt-on-all-received-characters mode is selected. In interrupt-on-first-receivedcharacter, an interrupt can occur from special-receive
conditions (except parity error) after the first-receivedcharacter interrupt (example: receive-overrun interrupt).
The main function of the external/status interrupt is
to monitor the signal transitions of the ClearTo Send
(CTS), Data Carrier Detect (DCD) and Synchronization (SYNC) pins (figures 1 through 6). In addition, an external/status interrupt is also caused by a
CRC-sending condition or by the detection of a
break sequence (asynchronous mode) or abort sequence (SDLC mode) in the data stream.
The interrupt caused by the break/abort sequence
allows the SIO to interrupt when the break/abort sequence is detected or terminated. This feature facilitates the proper temination of the current message,
Figure 13 : Typical
zaoc Environment.
SYSTEM
BUSES
CPU
For E'ght
Rx
a'I~IC~araCI'!'
READ REGISTER 2'
I~I~I~I~I~I~!~I~I
111111_~. ~!!
V4
VS
V'
V1
IVartable ., "SICltuS AltcCl5
VeetOI" ,s Proglarromed
16/24
108
llNTERRUPT
VECTOR
P'09,alT\med
Z84C40-Z84C41-Z84C42
Figure 16 : Write Register Bit Functions.
WHITE REGISTER 0
WRITE REGISTER 4
1~1~1~1~I~i~I~I~1
I I I
ID,I 0.1 D,I o. i D, ID, loJDOl
I
I
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
, 0,
II I
REGISTER 0
REGISTER I
REGISTER 2
REGISTER 3
REGISTE.R.
REGISTER S
REGISTER Ii
REGISTER T
o
0
0
0
NUll CODE
o
1
SEND ABORT (SOLei
REser EXrtSTATUS INTERRUPTS
CHANNEL RESE J
1
1
,,
1
1
0
0
0
0
ENABLE INT ON NEXT Rli CHARACTER
1
1
1
1
1
RESET h INI PENDING
ER"OR RESET
RETURN FROM INT leH· ... ONLY)
1
•
1
o
0
NUll COOE
o
1
1
,
0
I
RESET All CRe CHECKER
RESET h CRe GENERATOR
RESET fa: UNDERRUNIEOM LATCH
WRITE REGISTER I
o
o
I
,
0
1
0
1
o
o
0
I
1
"
0
I
I
ENj,8~
PARITY
PARITY EV(NtODD
SYNC MOCES ENABLE
1 STOP BITICHARACTER
1 '/, STOP BITSICHARACTER
2 STOP BIfSlCHARACTER
0 4 BIT SYNC CHARACTER
1 16 BIT SYNC CHARACTER
0 SOlC MODE (01111110 FLAC]
I EXTERNAL SYNC MOOE
)(1 CLOCK "ODE
)(16 CLOCK MODE
Xl2 CLOCK MODE
X64 CLOCM MODE
WRITE REGISTER 5
LI
I
EXT tNT ENABLE
11 'NT ENABLE
---STATUS AFFECTS VECTOR
(CH. 8 ONLy)
oo
,
1
0 RI INT DISABLE
}
I R. tNT ON FIRST CHARACTER
OINT ON All nll CHARACTERS (PARITY AFFECTS VECTORJ
•
1 INT ON All R. CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)
L--WAITIREADY ON RlT
L---WATtIREADY FUNCTION
WAIT/READY ENABLE
WRITE REGISTER 2 (CHANNEL B ONL YI
VJ
V4
INTERRUPT
VECTOR
V6
•
V,
.
V1
WRITE REGISTER 3
IIII
0
o
t
I
0
1
1
T. 5 BITS (OR LESS)lCHAAACTER
h 1 BITS/CHARACTER
TJ. 6 BITS/CHARACTER
Tx 8 BITS/CHARACTER
L - - OTA
I~I~I~I~I~I~I~I~I
111~L~~!1
o
WRITE REGISTER 6
III ~I
LL-!~:H:Hl
SYNC BIT 3
•
S'I'NC BI1 ..
SYNC Bll 5
SYNC BI1.'
SYNC BIT 1
WRITE REGISTER 1
I~SYHC
L - R• EH.BlE
CHARACTER lO'O lNH1B"
ADDRESS SEARCH MODE ,SDLe)
AI CRe ENABLE
ENTER HUNl PHASE
AUIO ENAILES
o
o
0 RI 5 BITSICHARACTEA
I AI 1 BtTSICHARACTER
' O R .. & 8ITSICHARACTER
I
I
H&. Ifll StCHA"ACTE"
'For SOle II MuSI Be P'Dqrammed
10 ·01111110 FOI flitU ~ecogl1
'"
iW
NC : No connection.
2/33
::: 2
]
A,
0,
D,
NMI
,
0,
GND
Do
~
°4
0,
D.
.
~1 .;;:
At
"
Mi
RESET
BUSREQ
Z8400
Figure 3 : CPU Block Diagram.
+5V _
GND . . .
CLOCK __
zao
MICROPROCESSOR FAMILY
The Z80, Z80A, Z80B and Z80H microprocessor is
the central element of a comprehensive microprocessor product family. This family works together in
most applications with minimum requirements for
additional logic, facilitating the design of efficient
and cost-effective microcomputer-base systems.
Five components to provide extensive support for
the Z80 microprocessor. These are:
• The CTC (Counter/Timer Circuit) features four
programmable 8-bit counter/timers, each of
which has an 8-bit prescaler. Each of the four
channels may be configurated to operate in
either counter or timer mode.
• The PIO (Parallel Input/Output) operates in both
data-byte I/O transfer mode (with handshaking)
and in bit mode (without handshaking). The PIO
may be configured to interface with standard parallel peripheral devices such as printers, tape
punches, and keyboards.
• The DMA (Direct Memory Access) controller provides dual port data transfer operations and the
ability to terminate data transfer as a result of a
pattern match.
• The SIO (Serial Input/Output) controller offers
two channels. It is capable of operating in a variety of programmable medes for both synchronous and asynchronous communication, including
Bi-Synch and SDLC.
• The DART (Dual Asynchronous ReceiverlTransmitter) device provides low cost asynchronous
serial communication. It has two channels and a
full modem control interface.
zao
CPU REGISTERS
Figure 4 shows three groups of registers within the
Z80 CPU. The first group consists of duplicate sets
of 8-bit registers : a principal set and an alternate
set (designated by' [prime], e.g., A'). Both sets consist of the Accumulator Register, the Flag Register,
and six general-purpose registers. Transfer of data
between these duplicate sets of registers is accomplished by use of "Exchange" instructions. The result is faster response to interrupts and easy,
efficient implementation of such versatile programming techniques as background-foreground
data processing. The second set of registers consists of six registers with assigned functions. These
are the I (Interrupt Register), the R (Refresh Register), the IX and IV (Index Registers), the SP (St~ck
Pointer), and the PC (Program Counter). The third
group consists of two interrupt status flip-flops, plus
and additional pair of flip-flops which assists in identifying the interrupt mode at any particular time. Table
1 provides further information on these registers.
3/33
121
Z8400
Figure 4 : CPU Registers
Main Register Set
Alternate Register Set
A Accumulator
F Flag Register
A' Accumulator
F' Flag Register
B General Purpose
C General Purpose
B' General Purpose
C' General Purpose
D General Purpose
E General Purpose
D' General Purpose
E' General Purpose
H General Purpose
L General Purpose
H' General Purpose
L' General Purpose
f---
8 Bits ------>
INTERRUPT FLIP-FLOPS STATUS
16 B'Its
f-
--->
IX Index Register
IV Index Register
~
SP Stack Pointer
I
PC Program Counter
I Interrupt Vector
f----
I
--6
0 = INTERRUPTS DISABLED
1 = INTERRUPTS ENABLED
6JJ
STORES IFFI
DURING NMI
SERVICE
R Memory Refresh
INTERRUPT MODE FLIP-FLOPS
8 Bits ------>
IMFa
IMFb
o
o
1
o
1
o
1
1
INTERRUPT MODE 0
NOT USED
INTERRUPT MODE 1
INTERRUPT MODE 2
Table 1 . CPU Registers,
Register
A,
F,
B,
C,
D,
E,
H,
L,
A'
F'
B'
C'
D'
E'
H'
L'
Size (Bits)
Accumulator
Flags
General Purpose
General PurpoSe
General Purpose
General Purpose
General Purpose
General Purpose
8
8
8
8
8
8
8
8
I
I nterrupt Register
8
R
Refresh Register
8
IX
IV
SP
Index Register
Index Register
Stack Pointer
16
16
16
PC
IFF1-IFF2
IMFa-IMFb
Program Counter
Interrupt Enable
Interrupt Mode
4/33
122
16
Flip-Flops
Flip-Flops
Remarks
Stores an Operand or the Results of an Operation
See Instruction Set.
Can be used separately or as a 16-bit register with C.
See B, above,
Can be used separately or as a 16-bit register with E.
See D, above,
Can be used separately or as a 16-bit register with L.
See H, above.
Note: The (B, C), (D, E), and (H, L) sets are combined as
follows:
B-High Byte C-Low Byte
D-High Byte E-Low Byte
H-High Byte L-Low Byte
Stores upper eight bits of memory address for vectored
interrupt processing.
Provides user-transparent dynamic memory refresh, Lower
seven bits are automatically incremented and all eight are
placed on the address bus during each instruction fetch
cycle refresh time,
Used for indexed addreSSing,
Same as IX, above.
Holds address of the top of the stack. See Push or Pop in
Instruction Set.
Holds address of next instruction.
Set or reset to indicate interrupt status (see figure 4).
Reflect Interrupt Mode (see figure 4).
Z8400
INTERRUPTS: GENERAL OPERATION
The CPU acc~ two interrupt input signals: NMI
and INT. The NMI is a non-maskable interrupt and
has the highest priority. INT is a lower priority interrupt and it requires that interrupts be enabled in software in order to operate. INT can be connected to
multiple peripheral devices in a wired-OR configuration.
The Z80 has a single response mode for interrupt
service for the non-maskable interrupt. The maskable interrupt, INT. has three programmable
response modes available.
These are:
• Mode 0 - similar with the 8080 microprocessor.
• Mode 1 - Peripheral Interrupt service, for use
with non-8080/Z80 systems.
• Mode 2 - a vectored interrupt scheme, usually
daisy-chained, for use with Z80 Family and compatible peripheral devices.
The CPU services interrupts by sampling the NMI
and INT signals at the rising edge of the last clock
of an instruction. Further interrupt service processing depends upon the type of interrupt that was detected. Details on interrupt responses are shown in
the CPU Timing Section.
NON-MASKABLE INTERRUPT (NMI)
The non-maskable interrupt cannot be disabled by
program control and therefore will be accepted at all
times by the CPU. NMI is usually reserved for servicing only the highest priority type interrupts, such
as that for orderly shut-down after power failure has
been detected.
After recognition of the NMI signal (providing BUSREO is not active), the CPU jumps to restart location 0066H. Normally, software starting at this
address contains the interrupt service routine.
MASKABLE INTERRUPT (INT)
Regardless of the interrupt mode set by the user,
the Z80 response to a maskable interrupt input follows a common timing cycle. After the interrupt has
been detected by the CPU (provided that interrupts
are enabled and BUSREO is not active) a special
interruQ!.processing cycle begins. This is a special
fetch (MI) cycle in which IORQ...Q.ecomes active
rather than MREO, as in normal M1 cycle. In addition, this special M1 cycle is automatically extended
by two WAIT states, to allow for the time required to
acknowledge the interrupt request.
MODE 0 INTERRUPT OPERATION
This mode is similar to the 8080 microprocessor interrupt service procedures. The interrupting device
places an instruction on the data bus. This is normally a Restart Instruction, which will initiate a call
to the selected one of eight restart locations in page
zero of memory. Unlike the 8080, the Z80 CPU
responds to the Call instruction with only one interrupt acknowledge cycle followed by two memory
read cycles.
MODE 1 INTERRUPT OPERATION
Mode 1 operation is very similar to that for the NMI.
The principal difference is that the Mode 1 interrupt
has a restart location of 0038H only.
MODE 2 INTERRUPT OPERATION
This interrupt mode has been designed to utilize
most effectively the capabilities of the Z80 microprocessor and its associated peripheral family. The interrupting peripheral device selects the starting
address of the interrupt service routine. It does this
by placing an 8-bit vector on the data bus during the
interrupt acknowledge cycle. The CPU forms a
pointer using this byte as the lower 8-bits and the
contents of the I register as the upper 8-bits. This
points to an entry in a table of addresses for interrupt service routines. The CPU then jumps to the
routine at that address. This flexibility in selecting
the interrupt service routine address allows the peripheral device to use several different types of service routines. These routines may be located at any
available location in memory. Since the interrupting
device supplies the low-order byte of the 2-byte vector, bit 0 (Ao) must be a zero.
Table 2 : State of Flip-Flops.
Action
IFF2 I FF2
CPU Reset
0
0
DI Instruction
execution
EI Instruction
execution
LD A, I Instruction
execution
LD A, R Instruction
0
0
1
1
.
.
Comments
Maskable Interrupt
INT Disabled
Maskable Interrupt
INT Disabled
Maskable Interrupt
INT Enabled
IFF2 -; Parity Flag
IFF2 -; Parity Flag
executi~
Accept NMI
0
IFF1
IFF1 -; IFF2
interrupt
INT disabled)
~skable
RETN Instruction
execution
IFF2
.
IFF2 -; IFF1 at
ColJ}2)§tion of
an NMI Service
Routine.
5/33
123
Z8400
INTERRUPT PRIORITY (Daisy Chaining and
Nested Interrupts)
1/0. It also allows operations on any bit in any location in memory.
The interrupt priority of each peripheral device is
determined by its physical location within a daisychain configuration. Each device in the chain has an
interrupt enable input line (lEI) and an interrupt enable output line (lEO), which is fed to the next lower
priority device. The first device in the daisy chain has
its lEI input hardwired to a High level. The first device has highest priority, while each succeding device has a corresponding lower priority. This
arrangement permits the CPU to select the highest
priority interrupt from several simultaneously interrupting peripherals.
The following is a summary of the Z80 instruction
set and shows the assembly language mnemonic,
the operation, the flag status, and gives comments
on each instruction. The zao CPU Technical Manual
and zao CPU Programming Manual contain significantly more details for programming use.
The interrupting device disables its lEO line to the
next lower priority peripheral until it has been serviced. After servicing, its lEO line is raised, allowing
lower priority peripherals to demand interrupt servicing.
The Z80 CPU will nest (queue) any pending interrupts or interrupts received while a selected peripheral is being serviced.
INTERRUPT ENABLEIDISABLE OPERATION
Two flip-flops, IFF1 and IFF2, referred to in the register description are used to signal the CPU interrupt status. Operation of the two flip-flops is
described in table 2.
INSTRUCTION SET
The Z80 microprocessor has one of the most powerful and versatile instruction sets available in any 8bit microprocessor. It includes such unique
operations as a block move for fast, efficient data
transfers within memory or between memory and
6/33
124
The instructions are divided into the following categories:
• 8-BIT LOADS
• 16-BIT LOADS
• EXCHANGES, BLOCK TRANSFERS, AND
SEARCHES
• 8-BIT ARITHMETIC AND LOGIC OPERATIONS
• GENERAL-PURPOSE ARITHMETIC AND CPU
CONTROL
• 16-BIT ARITHMETIC OPERATIONS
• ROTATES AND SHIFT
• BIT SET, RESET, AND TEST OPERATIONS
• JUMPS
• CALLS, RETURNS, AND RESTARTS
• INPUT AND OUTPUT OPERATIONS.
A variety of addressing modes are implemented to
permit efficie nt and fast data transfer between various registers, memory locations, and input/output
devices. These addressing modes include:
• IMMEDIATE
• IMMEDIATE EXTENDED
• MODIFIED PAGE ZERO
• RELATIVE
• EXTENDED
• INDEXED
• REGISTER
• REGISTER INDIREDT
• IMPLIED
• BIT
Z8400
INSTRUCTION SET (continued)
8-BIT LOAD GROUP
Symbolic
Operation
Symbol
LD r, r'
LD r, n
Flags
Opcode
Hex
S Z
r~r'
PIV N C 76 543210
H
, <- n
X
X
X
X
01
00
<-
,
r
r'
110
LD r, (HL)
LD " (IX+d)
, <- (HL)
, <- (IX + d)
X
X
X
X
01
110
11 011 101
r 101
01
<- d -->
n
-->
LD " (IY+d)
, <- (IY + d)
X
X
11 111 101
01
110
<- d -->
LD (HL), ,
LD (IX+d), r
(HL) <- r
(IX + d) <- ,
X
X
X
X
01 110
11 011 101
01 110
<- d -->
LD (IY+d), r
(IY + d) <- ,
X
X
LD (HL), n
(HL) <- n
X
LD (IX+d), n
(IX + d) <- n
LD (IY+d), n
N° of
Bytes
N° of N° of
M
T
Cycles Stales
1
2
1
2
4
7
DD
1
3
2
5
7
19
FD
3
5
19
DD
1
3
2
5
7
19
11 111 101
01 110
<- d -->
FD
3
5
19
X
00 110 110
<- n -->
36
2
3
10
X
X
11 011 101
00 110 110
<- d -->
<- n -->
DD
36
4
5
19
(IY + d) <- n
X
X
11 111 101
00 110 110
<- d -->
<- n -->
FD
36
4
5
19
LD A, (BC)
LD A, (DE)
LD A, (nn)
A <- (BC)
A <- (DE)
A <- (nn)
X
X
X
X
X
X
00 001 010
00 011 010
00 111 010
<- n -->
<- n -->
OA
lA
3A
1
1
3
2
2
4
7
7
13
LD (BC), A
LD (DE), A
LD (nn), A
(BC) <- A
(DE <- A
(nn) <- A
X
X
X
X
X
X
00 000 010
00 010 010
00 110 010
<- n -->
<- n -->
02
12
32
1
1
3
2
2
4
7
7
13
11
01
11
01
11
01
11
01
ED
57
ED
5F
ED
47
ED
4F
2
2
9
2
2
9
2
2
9
2
2
9
,
,
,
,
X 0 X
IFF
0
t
,
X 0
X
IFF
0
I <- A
X
X
R<-A
X
X
A <- I
LD A, R
A<-R
LD I, A
LD R, A
,
,
,
,
LD A, I
..
,
101
010
101
011
101
000
101
001
101
111
101
111
101
111
101
111
Comments
r, r' Reg.
--000
B
001
C
010
D
all
E
100
H
101
L
111
A
Notes: " " means any of the ,egisters A, B, C, D, E, H, L. IFF the content of the interrupt enable flip-flop, (IFF) is copied into the PN
flag.
For an explanation of flag notation and symbols for mnemonic tables, see Symbolic Notation section following tables.
7/33
125
Z8400
INSTRUCTION SET (continued)
16-81T LOAD GROUP
Symbolic
Operation
Symbol
LD dd, nn
dd
Hex
Z
P/V N C 76 543210
H
· · · ··
· ·.
nn
f-
X
X
LD IX, nn
IX
f-
nn
LD IY, nn
IY
f-
nn
·
• X • X
LD HL, (nn)
H f- (nn + 1)
L f- (nn)
·
• X • X
LD dd, (nn)
ddH
ddL
(nn + 1)
(nn)
·
• X • X
f-
IXH
IXL
(nn + 1)
(nn)
·
• X • X
f-
IYH
IYL
f-
(nn + 1)
(nn)
·•
LD IX, (nn)
LD IY, (nn)
f-
f-
f-
Opcode
Flags
S
• X • X
X • X
· ·.
· ··
·.
· ·.
· ··
LD (nn), HL (nn + 1) f- H
(nn) f- L
·
• X • X
LD (nn), dd
(nn + 1) f- ddH
(nn) f- ddL
·
• X • X
LD (nn), IX
(nn + 1) f- IXH
(nn) f- IXL
·
• X • X
· ·.
LD (nn), IY
(nn + 1) f- IYH
(nn) f- IYL
·
• X • X
· ·.
· ··
· ·.
N° of
Bytes
3
00 ddO 001
f- n ~
f- n ~
126
3
10
Comments
dd Pair
---
Be
11 011 101
00 100001
f- n ~
f- n ~
DD
21
4
4
14
11 111 101
00 100001
f- n ~
f- n ~
FD
21
4
4
14
00 101 010
f- n ~
f- n ~
2A
3
5
16
11 101 101
01 dd1 011
f- n ~
f- n ~
ED
4
6
20
11 011 101
01 101 010
f- n ~
f- n ~
DD
2A
4
6
20
11 111 101
00 101 010
f- n ~
n ~
~
FD
2A
4
6
20
00 100010
f- n ~
f- n ~
22
3
5
16
11 101 101
01 ddO 011
f- n ~
f- n ~
ED
4
6
20
11 011 101 DD
00 100010 .22
f- n ~
f- n ~
4
6
20
11 111 101 FD
00 100010 22
f- n ~
f- n ~
4
6
20
Notes: dd IS any of the register pairs BC, DE, HL, SP.
qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively,
e.g., BCL = C, AFH = A.
8/33
N° 01 N° 01
M
T
Cycles States
00
01 DE
10 HL
11 SP
Z8400
INSTRUCTION SET (continued)
16-BIT LOAD GROUP (continued)
Symbolic
Operation
Symbol
Flags
Hex
S Z
PIV N C 76 543210
H
LD SP, HL
LD SP, IX
SP <- HL
SP <- IX
X
X
X
X
LD SP, IV
SP <- IV
X
X
PUSH qq
(SP - 2) <- qqL
(SP - 1) <- qqH
SP...,SP-2
(SP - 2) <- IXL
(SP - 1) <- IXH
SP-->SP-2
(SP - 2) <- IVL
(SP - 1) <- IVH
SP...,SP-2
qqH <- (SP + 1)
qqL <- (SP)
SP...,SP+2
IXH <-- (SP + 1)
IXL <-- (SP)
SP-->SP+2
IVH<--(SP+l)
IVL <- (SP)
SP ..., SP + 2
X
X
PUSH IX
PUSH IV
POP qq
POP IX
POP IV
Opcode
tt
tt
11
11
11
11
t1t
Ot t
111
ltl
111
qqO
OOt
tOt
001
101
001
101
N° of
Bytes
N° of N° of
M
T
Cycles States
F9
DD
F9
t
2
1
2
6
to
FD
F9
2
2
10
1
3
11
X
X
11
It
011 101
100 lOt
DD
E5
2
4
15
X
X
11
It
111 101
100 101
FD
E5
2
4
15
X
X
11
qqO 001
1
3
10
X
X
11
11
011 101
100 001
DD
El
2
4
14
X
X
11
11
111 101
100 001
FD
El
2
4
14
Comments
qq Pair
--00 BC
01 DE
10 HL
Notes: dd is any of the register pairs BC, DE, HL, SP.
qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively,
e.g., BCL = C, AFH = A.
EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS
Symbolic
Operation
Symbol
Flags
Opcode
Hex
N° of
Bytes
PIV N C 76 543 210
H
S Z
N° of N° of
M
T
Cycles States
EX DE, HL,
EX AF, AF'
EXX
DE
AF
BC
DE
HL
HL,
AF'
< > BC'
< > DE'
< > HL'
X
X
X
X
X
X
11
00
11
101 all
001 000
all 001
EB
08
D9
1
1
1
1
1
1
4
4
4
EX (SP), HL
H <> (SP + 1)
L <> (SP)
X
X
11
100 011
E3
1
5
19
EX (SP), IX
IXH
IXL
(SP + 1)
(SP)
X
X
11
11
all 101
100 011
DD
E3
2
6
23
H
IVH
IVL
(SP + 1)
(SP)
X
X
11
11
111 101
100 all
FD
E3
2
6
23
H
EX (SP), IV
< >
<>
<->
<>
Comments
Register Bank
and Auxiliary
Register Bank
Exchange
Notes: 1. If the result of B-1 is zero the Z flag is set, otherwise it is reset.
2. Z flag is set upon instruction completion only.
9/33
127
Z8400
INSTRUCTION SET (continued)
EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS (continued)
Symbol
Opcode
Flags
Symbolic
Operation
S Z
Hex
PIV N C 76 543210
H
N° of
Bytes
Wof
N° of
M
T
G)
LDI
(DE) <- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
X
a
X
LDIR
(DE) <- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
Repeat Until
BC ~ a
X
a
X
LDD
(DE) <-- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
X
a
X
LDDR
(DE) <- (HL)
DE <- DE + 1
HL <- HL + 1
BC <- BC - 1
Repeat Until
BC ~ a
X
a
X
a
11
10
101 101
100 000
ED
AO
2
4
6
a a
11
10
101 101
110 000
ED
BO
2
2
5
4
21
16
a
11
10
101 101
101 000
ED
A8
2
4
16
a a
11
10
101 101
111 000
ED
B8
2
2
5
4
21
16
1
11
10
101 101
100 001
ED
Al
2
4
16
1
11
101 101
ED
2
5
21
10
110 001
Bl
2
4
16
1
11
10
101 101
101 001
ED
A9
2
4
16
1
11
101
101
ED
2
5
21
10
111 001
B9
2
4
16
t
Comments
Cycles States
Load (HL)
into (DE),
increment the
pointers and
decrement the
byte cou nter (Be)
G)
If BC
If BC
~
~
a
a
G)
t
@
@
CPI
A <- (HL)
HL <- HL + 1
BC <- BC - 1
t t
A - (HL)
t t
HL <- HL + 1
BC <- BC - 1
Repeat Until
A ~ (HL) or BC
~
t
X
X
t
X
A - (HL)
HL <- HL + 1
BC <- BC - 1
t t
A - (HL)
t t
HL <- HL + 1
BC <- BC - 1
Repeat Until
A ~ (HL) or BC
~
t
t
128
If BC '" a and
A ~ (HL)
If BC ~ a or
A ~ (HL)
G)
X
t
X
X
t
X
t
G)
t
a
Notes: CD. If the result of B-1 is zero the Z flag is set, otherwise it is reset.
Gl. Z flag is set upon instruction completion only.
10/33
a
a
a
@
CPDR
~
G)
@
CPO
~
G)
X
@
CPIR
If BC
If BC
If BC '" a and
A", (HL)
If BC ~ a or
A ~ (HL)
Z8400
INSTRUCTION SET (continued)
8-BIT ARITHMETIC AND LOGICAL GROUP
Symbol
ADD A, r
ADD A, n
ADD A, (HL)
ADD A, (IX+d)
ADD A, (IY +d)
Symbolic
Operalion
A<-A+r
Af-A+n
Flags
Opcode
Hex
S Z
·,
;
H
X
X
,
·, ,,
A <- A + (HL)
A <- A + (IX + d) ,
X ,
X
· ·, ··
· ·, X :
A <- A + (IY + d) ,
76
543
210
[QQQJ
[QQQJ
r
110
-->
X
V
V
a !
a :
10
11
X
X
V
V
a
a
10
11
10
1 X
·· · ·
PIV N C
<-
,
,,
011
[QQQJ
<-
X
V
a I
11
10
INC (IY+d)
DEC
m
; ;
A <- A + s + CY
A<-A-s
A <- A - s - CY
A<-AAs
A<-AVs
A<-AfBs
A-s
r f- r + 1
(HL) <- (HL) + 1
(IX + d) <(IX + d) + 1
··· ··,
(IY + d) <(IY + d) +1
t t
mf-m-1
t I
,
,
,
: ,
:
X
X
X t X
X I X
X 1 X
X a X
X a X
X t X
X t X
X
X
X ; X
·, ·,
t ·,
! I
· ··
t I
·
t 1 ·
,
·
X
··
X
X ,
X
V
V
V
P
p
p
V
V
V
V
V
V
a
1
1
[QQQJ
a
a
a
a
1
d
110
101
110
N° of
N° 01
M
T
4
7
1
1
2
2
1
19
19
DO
3
2
5
FD
3
5
7
-->
101
110
;
:
riOol
UillJ
W1J
[1QQ]
<-
r
110
011
110
d
101
<-
111
110
d
00
00
11
00
11
00
r Reg.
-000
001
010
011
100
101
111
B
C
0
E
H
L
A
-->
[jjQJ
..
Comments
Cycles States
[QQ1J
[Q1Q]
IQ1iJ
,
a a
a a
a a
1
d
111
[1QQ]
-->
UillJ
m is any of r,
(HL), (IX+d),
(IY +d) as shown
for INC. DEC
same format
and states as
INC. Replace
riOol with
i n apcode.
Ii01l
11/33
129
Z8400
INSTRUCTION SET (continued)
GENERAL-PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
Symbol
DAA
Symbolic
Operation
Converters ace content
Flags
S Z
Opcode
PIV N C 76 543210
H
t t X t X
.
P
¥
N° of
Hex Bytes
N° of N° of
M
T
Cycles States
00
100 111
27
1
1
4
Decimal
Adjust
Accumulator.
00
101 111
2F
1
1
4
Complement
Accumulator
(one's
complement)
into packed BCD
following add or
subtract with packed
BCD operands
CPL
A<-A
NEG
A<-O-A
CCF
CY <- Cy
SCF
CY <- 1
X
NOP
HALT
DI'
EI'
1M a
No Operation
CPU Halted
IFF <- a
IFF <- I
Set Interrupt
Mode a
Set Interrupt
Mode 1
Set Interrupt
Mode 2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1M 1
1M2
X 1 X
.
¥
t X
t
1
1
t
11
01
101 101
000 100
ED
44
2
2
8
Negate Ace.
(two's
complement).
X X X
a
~
00
111 111
3F
1
1
4
Complement
Carry Flag.
a
a
1
00
110 111
37
1
1
4
Set Carry
Flag.
00
01
11
11
11
01
11
01
11
01
000
110
110
111
101
000
101
010
101
000
110
00
76
F3
FB
ED
46
ED
56
ED
5E
1
1
1
1
2
1
1
1
1
2
4
4
4
4
2
2
8
2
2
8
X
X
V
Notes: IFF indicates the interrupt enable flip-flop.
CY indicates the carry flip-flop.
* indicates interrupts are not sampled at the end of EI or DI.
12/33
130
Comments
all
all
all
101
110
101
110
101
110
8
Z8400
INSTRUCTION SET (continued)
16-BIT ARITHMETIC GROUP
Symbol
Symbolic
Operation
ADD HL, ss
ADC HL, ss
HL <- HL + SS
HL <- HL + ss + CY
SBC HL, ss
HL <- H L + ss - CY
Opcode
Flags
Hex
S Z
··
··
··
··
PIV N C
H
X X X
X X X
V
a ,I
a
X X X
V
1
ADD IX, pp
IX <- IX + pp
X X X
a
ADD IY. rr
IY<-IY+rr
X X X
a
INC ss
INC IX
SSf----ss+1
IX <- IX + 1
X
X
X
X
INC IY
IY <- IY + 1
X
X
DEC ss
DEC IX
SSf---ss-1
IX <- IX - 1
X
X
X
X
DEC IY
IY<-IY-l
X
X
..
!
76 543210
00
11
01
11
01
11
01
11
00
00
11
00
11
00
00
11
00
11
00
ssl
101
ssl
101
sso
all
ppl
111
rrl
ssO
all
100
111
100
ssl
all
101
111
101
001
101
010
101
010
101
001
101
001
all
101
all
101
all
all
101
all
101
all
N° of
Bytes
N° of
N° of
M
T
Cycles States
ED
1
2
3
4
11
15
ED
2
4
15
DD
2
4
15
FD
2
4
15
1
2
1
2
6
10
2
2
10
1
2
1
2
6
10
2
2
10
DD
23
FD
23
DD
2B
FD
Comments
ss Reg.
--00 BC
01 DE
10 HL
11 SP
pp Reg.
--00 BC
01 DE
10 IX
11 SP
rr
Reg.
-00 BC
01 DE
10 IY
11 SP
2B
Notes: ss is any of lhe register pairs BC, DE, HL, SP.
pp is any of the register pairs BC, DE, IX, SP.
rr is any of the register pairs BC, DE, IY, SP.
13/33
131
28400
INSTRUCTION SET (continued)
ROTATE AND SHIFT GROUP
Mnemonic
Symbolic
Operation
Flags
S
Z
.
RLCA
@3-~L·••3J
X
RLA
4iJ-v~
X
RRCA
~
,
RRA
CE---;-~
·.
·.
,
RLC r
t
X
a
Opcode
PN N C
H
X
·
·
·
No.of No.of MNo.of T
76 543 210 Hex Bytes Cycles States
Comments
._------------------_._-00000 111 07
4
Rotate left circular
accumulator.
00010 111
17
4
Rotate left
accumulator.
00001111
OF
4
Rotate right circular
IF
4
Rotate right
accumulator.
2
8
Rotate left circular
2
4
15
_ _ _ Reg
000
B
4
6
23
001
C
X
X
X
X
·
00011111
X
p
11001011 CB
X
a
accumulator.
oo[~~
RLC (HL)
X
X
P
RLC (IX + d)
X
X
P
a
register r.
r
11001011 CB
00[Oc@110
11011101 DD
11001011 CB
r. (HL), (IX+d), (IY+d)
<-d->
00~110
t
RLC (IY + d)
X
a
X
p
a
t
11 111 101 FD
4
23
11001011 CB
010
D
all
E
100
H
101
L
111
A
f---d~
00[~~Jll0
RLm
C§:::.rc.~
m
~
t
X
X
p
X
p
Instruction format
@.~
and states are as shown
r,(HL),(IX+d),(iY+d)
for RLC's, To form new
~~lc]
RRC.m
a
X
[001]
a
opcode rep lac e
m ~ r,(HL),(IX+d),(iY+d)
·
RRm
[G00l
or
RLC's with shown code,
X
p
a
a
X
p
a
X
a
X
p
a
X
a
X
p
a
X
a
X
p
a
t
X
t
X
[~~1]
m ~ r,(HL),(IX+d),(iY +d)
SLAm
G3--G:::-'--;f-o
t
[~661
m ~ r,(HL),(IX+d),(iY+d)
c5~
SRAm
m ~ r,(HL),(IX+d),(iY+d)
SRLm
0--['-.
m
RLD
RRD
~
I 7-4 I
,
;:]--0
r,(HL),(IX+d),(iY+d)
3211T;]} I
v
:HLi
X
0
X
p
a
.
.
11101101 ED
5
18
Rotate digit left and
18
accumulator and
01 101 111 6F
11 101 101 ED
01 100 111 67
right between the
2
location (HL).
The contentof the upper
half of the accumulator
is unaffected.
14/33
132
Z8400
INSTRUCTION SET (continued)
BIT SET, RESET AND TEST GROUP
Symbolic
Operation
Symbol
BIT b, r
BIT b, (HL)
BIT b, (IX+d)b
Z
~ rb
Z <-
(HL)b
--
Z <- (IX + d)b
Flags
S Z
X
.
Opcode
PIV N C
H
X 1 X
X
0
X
:
X 1 X
X
0
X
t
X 1
X
0
X
76
543 210
11
01
11
01
11
11
001
011
b
r
001
011
110
101
011
b
011
001
<-
01
BIT b, (IV +d)b
Z <- (IV + d)b
X
;
X 1 X
X
a
11
11
111
001
SET b, (HL)
SET b, (IX+d)
rb
f-
1
(HL)b <- 1
(IX' +d)b <- 1
X
X
X
X
X
X
X
X
0
m '" r, (HL),
(IX + d),
(IY + d)
X
X
2
2
8
3
12
DD
CB
4
5
20
101
FD
4
5
20
011
CB
CB
2
2
8
--'>
110
11
001
011
!:iLl
b
r
--'>
110
11
001
2
4
15
b
011
110
CB
WJ
11
11
011
001
101
DD
CB
4
6
23
011
FD
CB
4
6
23
<(IV + d)b <- 1
CB
N° of N° of
M
T
Cycles States
2
01
!:iLl
SET b, (IV+d)
N° 01
Bytes
CB
d
b
110
11
111 101
11 001 011
d --'>
<110
b
WJ
RES b, m
mb f-
Uil
To form new
opcode
replace [1i]
of SET b, s
with
Flags and
time states for
SET
instruction.
UiI.
Note: The notation mb indicates bit b (0 to 7) or location m.
15/33
133
Z8400
INSTRUCTION SET (continued)
JUMP GROUP
Symbolic
Operation
Symbol
JP nn
JP cc, nn
JR e
Flags
Opcode
Hex
S Z
P/V N C 76 543210
H
PC <- nn
X
X
11 000 all
<- n .....
<- n .....
If condition cc is true
PC ~ nn, otherwise
continue
X
X
11 cc
<- n
<- n
PC <- PC + e
X
X
JR C, e
JR NC, e
JP Z, e
JR NZ, e
If C
If C
If C
If C
If Z
If Z
If Z
If Z
~
~
~
~
~
~
~
~
a continue
1 PC <- PC+e
1, continue
0, PC <- PC+e
a continue
1 PC <- PC+e
1, continue
0, PC <- PC+e
X
X
X
X
X
X
X
3
3
10
18
2
3
12
38
2
2
7
2
3
12
2
2
7
2
3
12
2
2
7
2
3
12
2
2
7
2
3
12
cc Condition
----
30
--?
28
e-2 --}
00 100 000
f-
10
e-2 --}
e-2
Comments
000 NZ non-zero
oat Z zero
010 N C non-carry
011 C carry
100 PO parity odd
101 PE parity even
110 P sign positive
111M sign negative
--?
00 lOt 000
f-
T
Cycles States
.....
00 110 000
f-
N° 01
M
3
.....
00 111 000
f-
X
e-2
N° of
J
C3
010
00 all 000
f-
N° of
Bytes
20
e-2 --}
If condition not
met.
If condition is
met.
If condition not
met.
If condition is
met.
If condition not
met.
If condition is
met.
If condition not
met.
If condition is
met.
JP (HL)
PC <- HL
X
X
11
101 001
E9
1
1
4
JP (IX)
PC <- IX
X
X
11
11
all 101
101 001
DD
E9
2
2
8
JP (IY)
PC <- IY
X
X
11
11
111 101
101 001
FD
E9
2
2
8
B<-B-l
If B ~ 0, continue
If B '" 0, PC <- PC+e
X
X
00 010 000
f- e-2 --}
10
2
2
8
If B
2
3
13
If B", O.
DJNZ, e
Notes: e represents the extension in the relative addressing mode.
e is a signed two's complement number in the range <-126,129>.
e - 2 in the opcode provides an effective address of pc + e as PC is incremented
by 2 prior to the addition of e.
16/33
134
~
O.
Z8400
INSTRUCTION SET (continued)
CALL AND RETURN GROUP
Symbol
CALL nn
CALL CC, nn
Flags
Symbolic
Operation
Opcode
Hex
S
Z
P/V N C
H
(SP - 1) <- PCH
(SP - 2) <- PCl
PC <- nn
X
If condition cc is
false continue,
otherwise same as
X
X
76 543 210
11
<<-
X
11
<<-
001 101
n ->
n ->
cc
n
n
CO
N° of
Bytes
N° of
N° of
M
T
Comments
Cycles States
3
5
17
100
3
3
10
If cc is false.
->
->
3
5
17
If cc is true.
1
3
10
1
1
5
1
3
11
CALL nn
RET
RET cc
I
PCl <- (SP)
PCH <- (SP + 1)
X
X
11
001
001
If condition cc is
fase continue,
otherwise same as
X
X
11
cc
000
C9
RET
Return from
interrupt
X
X
11
01
101
001
101
101
ED
40
2
4
14
RETN 1
Return from
X
X
11
01
101 101
000 101
ED
45
2
4
14
X
X
11
1
3
11
non-maskable
interrupt
RSTp
I
Note:
(SP - 1) <- PCH
(SP - 2) <- PCl
PCH <- 0
PCl <- P
1. RETN loads IFF"
If cc is true
cc
RETI
I
If cc is false.
t
111
000
001
01 0
011
100
101
110
111
Condilion
NZ Non-zero
Z Zero
NC Non-carry
C Carry
PO Parily Odd
P E Parily Even
P Sign Posilive
M Sign Negalive
~-----"000
001
010
011
100
101
110
111
DOH
08H
10H
18H
20H
28H
30H
38H
IFF,.
17/33
135
Z8400
INSTRUCTION SET (continued)
INPUT AND OUTPUT GRUP
Symbol
IN A, (n)
Symbolic
Operation
Flags
Opcode
Hex
S Z
A <-- (n)
PIV N C 76 543210
H
X
11
X
<-IN r, (C)
N° of
Bytes
N° of
N° of
M
T
Comments
Cycles States
all 011
n -->
DB
2
3
11
n to Ao _ A7
Ace. to As - A,s
C to Ao _ A7
B to As _ A,s
X
p
a
11
01
101 101
r 000
ED
2
3
12
X X X
X
1 X
It
10
101 101
100 010
ED
A2
2
4
16
C to Ao _ A7
6 to As - A'5
(HL) <-- (C)
6 <-- 6 - 1
HL <- HL + 1
Repeat unil 6 = a
X 1 X X X
X
1 X
11
to
101 101
110 010
ED
62
2
5
21
C to Ao _ A7
6 to As - A'5
(HL) <- (C)
6<-6-1
HL <- HL - 1
X
X X X
X
1 X
11
10
101 101
101 010
ED
AA
2
(HL) <- (C)
6<-B-l
HL <- HL - 1
Repeat until 6 = a
X 1 X X X
X
1 X
11
10
101 101
111 010
ED
6A
2
r <-- (C)
~ r = 110 only the flags
will be affected
t t
(HL) <-- (C)
6 <-- 6 - 1
HL <-- HL + 1
X
X
t
CD
INI
INIR
t
(if 6,,0)
2
4
16
(if 6=0)
CD
IND
INDR
t
4
16
C to Ao _ A7
6 to As - A'5
5
21
C to Ao _ A7
(if 6,,0)
2
4
6 to As - A'5
16
(if 6=0)
n to Ao _ A7
Acc.to As-At5
C to Ao _ A7
6 to As - At5
OUT (n), A
(n) <- A
X
X
11 010 all
<- n -->
D3
2
3
11
OUT (C), r
(C) <- r
X
X
11
01
101 101
r 001
ED
2
3
12
4
16
C to Ao - A7
6 to As - At5
5
21
C to Ao _ A7
6 to As - At5
CD
t
OUTI
(C) <- (HL)
6<-6-1
HL <- HL + 1
X
X X X
X
1 X
11
10
101 101
100 all
ED
A3
2
OTIR
(C) <- (HL)
6<-6-1
HL <- HL + 1
Repeat until 6 = a
X 1 X X X
X
1 X
11
10
101 101
110 all
ED
63
2
OUTO
(C) <- (HL)
6<-6-1
HL <-- HL - 1
X
X X X
X
1 X
11
10
101 101
101 all
ED
A6
2
OTOR
(C) <- (HL)
6<-6-1
HL <-- HL + 1
Repeat until 6 = a
X 1 X X X
X
1 X
11 101 101
10 111 all
ED
2
(if 6,,0)
2
4
16
(if 6=0)
CD
t
4
16
5
21
C to Ao _ A7
6 to As - At5
CD
Note:
18133
136
nn
16-bit Value in Range < 0.65535 >
20/33
138
Operation
= 1 if the MSB of the result is 1.
Z = 1 if the result of the operation
S
Z8400
PIN DESCRIPTIONS
Ao-A15. Address Bus (Output, Active High, 3-state).
Ao-A15 form a 16-bit address bus. The Address Bus
provides the address for memory data bus exchanges (up to 64K bytes) and for I/O device exchanges.
M1. Machine Cycle One (Output, Active Low). M1,
together with MREO, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1, together with 10RO, indicates an
interrupt acknowledge cycle.
BUSACK. Bus Acknowledge (Output, Active Low).
Bus Acknowledge indicates tothe requesting device
that the CPU address bus, data bus, and control signals MREO, 10RO, RD, and WR have entered their
high-impedance states. The external circuitry can
now control these lines.
MREQ. Memory Request (Output, Active Low, 3state). MREO indicates that the address bus holds
a valid address for a memory read or memory write
operation.
BUSREQ. Bus Request (Input, Active Low). Bus
Request has a higher priority than NMI and is always
recognized at the end of the current machine cycle.
BUSREO forces the CPU address bus, data bus,
and control signals MREO, 10RO, RD, and WR to
go to a high-impedance state so that other devices
can control these lines. BUSREO is normally wireORed and requires an external pullup for these applications. Extended BUSREO periods due to
extensive DMA operations can prevent the CPU
from properly refreshing dynamic RAMs.
00-07. Data Bus (Input/Output, Active High, 3state). 00-07 constitute an a-bit bidirectional data
bus, used for data exchanges with memory and I/O.
HALT. Halt State (Output, Active Low). HALT indicates that the CPU has executed a Halt instruction
and is awaiting either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume. While halted, the CPU executes
NOPs to maintain memory refresh.
INT. Interrupt Request (Input, Active Low). Interrupt
Request is generated by I/O devices. The CPU honors a request at the end of the current instruction
if the intemal software-controlled interrupt enable
flip-flop (IFF) is enabled. INT is normallywire-ORed
and requires an extemal pullup for these applications.
IORQ. Input/Output Request (Output, Active Low,
3-state). 10RO indicates that the lower half of the
address bus holds a valid I/O address for an 110 read
or write op'eration. 10RO is also generated concurrently with M1 during an interrupt acknowledge cycle
to indicate that an interrupt response vector can be
placed on the data bus.
NMI. Non-Maskable Interrupt(lnput, negative eQgjt
triggered). NMI has a higher priority than INT. NMI
is always recognized at the end of the current instruction, independent of the status of the interrupt
enable flip-flop, and automatically forces the CPU
to restart at location 0066H.
RD. Read (Output, Active Low, 3-state). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or
memory should use this Signal to gate data onto the
CPU data bus.
RESET. Reset (Input, Active Low). RESET initializes the CPU as follows: it resets the interrupt
enable flip-flop, clears the PC and Registers I and
R, and sets the interrupt status to Mode O. During
reset time, the address and data bus go to a highimpedance state, and all control output signals go
to the inactive state.
Note that RESET must be active for a minimum of
three full clock cycles before the reset operation is
complete.
RFSH. Refresh (Output, Active Low). RFSH,
together with MREO, indicates that the lower seven
bits of the system's address bus can be used as a
refresh address to the system's dynamic memories.
WAIT. Wait (Input, Active Low). WAIT indicates to
the CPU that the addressed memory or I/O devices
are not ready for a data transfer. The CPU continues
to enter a Wait state as long as this signal is active.
Extended WAIT periods can prevent the CPU from
refreshing dynamic memory properly.
WR. Write (Output, Active Low, 3-state). WR indicates that the CPU data bus holds valid data to be
stored at the addressed memory or I/O location.
21/33
139
Z8400
CPU TIMING
The Z80 CPU executes instructions by proceeding
through a specific sequence of operations:
• Memory read or write
• 1/0 device read or write
• Interrupt acknowledge
The basic clock period is referred to as a T time or
cycle, and three or more T cycles make up a machine cycle (M1, M2 or M3 for instance). Machine
cycles can be extended either by the CPU automatically inserting one or more Wait states or by the insertion of one or more Wait states by the user.
Counter (PC) on the address bus at the start of the
cycle (figure 5). Approximately one-ha~ock cycle
later, MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the CPU
data bus.
The CPU samples the WAIT input with the falling
edge of clock state T 2. During clock states T 3 and
T4 of an M1 cycle dynamic RAM refresh can occur
while the CPU starts decoding and executing the instruction. When the Refresh Control signal
becomes active, refreshing of dynamic memory can
take place.
INSTRUCTION OPCODE FETCH
The CPU places the contents of the Program
Figure 5 : Instruction Opcode Fetch.
T,
T,
Tw
T,
CLOCK
Ao-A15
WAIT
_+----J
__+-_____
~-L~,?-J
-Ir
i
00-07
RFSH
~~--+(~«R{--':'';~-)('::;;;::-;::1'-_ _- 4_ _
-------------11.F-,------1--1'_"_0_______.•~r_
Note: Tw-Wait cycle added when necessary for slow ancilliary devices.
22/33
140
Z8400
CPU TIMING (continued)
MEMORY READ OR WRITE CYCLES
Figure 6 shows the timing of memo!Y.lead or write
cycles other than an opcode fetch (M1) cycle. The
MREQ and RD signals function exactly as in the
fetch cycle. In a memory write cycle, MREQ also
becomes active when the address bus is stable. The
WR line is active when the dat~bus is stable, so that
it can be used directly as an RfIN pulse to most semiconductor memories.
Figure 6 : Memory Read or Write Cycles.
T,
OPERA;::
l
T,
Tw
AD
Do- D7
OPER:::~:
1
WR
Do-D7
------,===~::=:~!:====~
23/33
141
Z8400
CPU TIMING (continued)
cally inserts a single Wait state (Tw).
INPUT OR OUTPUT CYCLES
This extra Wait state allows sufficient time for an 1/0
port to decode the address from the port address
lines.
Figure 7 shows the timing for an 1/0 read or 1/0 write
operation. During I/O operations, the CPU automatiFigure 7: Input or Output Cycles.
Tw'
Tw
CLOCK
Ao-A
1
WR
WRI~~
OPl!RATION
Note: Tw'
24/33
142
=
Do-D7
-----~========~~==2!!!!!~==:j
One wait cycle automatically inserted by CPU.
Z8400
CPU TIMING (continued)
INTERRUPT REQUEST/ACKNOWLEDGE
CYCLE
The CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of any in-
struction illQ.ure 8). When an interrupt is accepted,
a special M1 cycle is generated.
During this M1 cycle, IORQ becomes active (instead
of MREQ) to indicate that the interrupting device can
place an 8-bit vector on the data bus. The CPU automatically adds two Wait states to this cycle.
Figure 8: Interrupt Request/Acknowledge Cycle.
~-A'.
+-____
__________~__~__________~P~C__
fiH ________
-+~~
__-H__
~~~
___
~--------------------~~~
Noles: 1. TL = Last state of previous instruction.
2. Two Wait cycles automatically inserted by CPU (0).
Gi
SGS·THOMSON
~I Ii'AIDa:::DI@~w:ITDII@OOD«::$
25133
143
Z8400
CPU TIMING (contiued)
not be disabled under software control. The subsequent timing is similar to that of a normal instruction fetch except that data put on the bus by the
memory is ignored. The CPU instead executes a
restart (RST) operation and jumps to the NMI service routine located at address 0066H (figure 9).
NON-MASKABLE INTERRUPT REQUEST
CYCLE
NMI is sampled at the same time as the maskable
interrupt input INT but has higher priority and can-
Figure 9 : Non-Maskable Interrupt Request Operation.
- - - L A S T M C'tCL£ -~'"''''''''''~-------------M1---------+1
LAST T TIME
T,
T2
T)
T,
'5
CLOCK
Ao .. t\11
--------------~'~--------~
--@-
• Although NMI is an asynchronous input. to guarantee its being recognized on the following machine cycle, NMl's falling edge must
occur no later than the rising edge of the clock cycle preceding TLAST.
26/33
144
Z8400
CPU TIMING (continued)
BUS REQUEST/ACKNOWLEDGE CYCLE
The CPU samples BUSREQ with the rising edge of
the last clock period of any machine cycle (figure
10). If BUSREQ is active, the CPU sets its address,
data, and MREQ, 10RQ,RD, and WR lines to a highimpedance state with the. rising edge of the next
clock pulse. At that time, any external device can
take control of these lines, usually to transfer data
between memory and I/O devices.
Figure 10: Z-Bus Request/Acknowledge Cycle.
CLOCK
Ao-A,S _ _ _ _ _ _ _ _ _~
11'1
-
______________
~
®-~J
_________
t_-----~UK~H.~N.=.D--------
Note: T L = Last state of any M cycle.
Tx = An arbitrary clock cycle used by requesting device.
27/33
145
Z8400
CPU TIMING (continued)
RESET CYCLE
HALT ACKNOWLEDGE CYCLE
RESET must be active for at least three clock cycles
for the CPU to properly accept it. As long as RESET
remains active, the address and data buses float,
and the control outputs are inactive. Once RESET
goes inactive, three internal T cycles are consumed
before the CPU resumes normal processing operation. RESET clears the PC register, so the first opcode fetch will be to location 0000 (figure 12).
When the CPU receives an Halt instruction, it executes NOP states until either an INT or NMI input
is received. When in the Halt state, the HALT output is active and remains so until an interrupt is received (figure 11).
Figure 11 : Halt Acknowledge Cycle.
M1------~~~----------------M1----------------••+I••------------ M'
T,
T2
Nil'
-----------------------~
~-------------------
Note: INT will also force a Halt exit.
• See note, Figure 9.
Figure 12 : Reset Cycle.
CLOCK
Ao-Au
============C~--1~------~~-------t-.t======
0.-0,
-
@
~~_ _ _--,:,',::LO::;AT~_ _ _ _-+________
-------'I
:
----'7 •
Ir. _ _ _ _ _ _ _ _ _ _ _ _
______ . . ......Z2.I. . Z. . .2'.J7
~ 01-
l
,\~I
____
~-------~~rT~~----__1~~(--------~---_r---------
.u~~~
HAiT
28/33
146
~Z
\'--_____
Z8400
AC CHARACTERISTICS
N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Symbol
TcC
Clock Pulse Widlh (high)
TwCI
Clock Pulse Width (low)
TfC
Clock Fall Time
TrC
Clock Rise Time
Clock
i
to Address Valid Delay
TdA (MREOf)
Address Valid to MREO
TdCf (MREOf)
Clock
TdCr (MREOr)
Clock
1 to
i to
MREO
MREO
1
i
1
Delay
400'
180'
180 2000
30
30
145
125'
Delay
MREO Pulse Width (high)
170'
TwMREOI
MREO Pulse Width (low)
360'
Clock
TdCf (RDf)
Clock
TdCr(RDr)
Clock
TsD(Cr)
ThD(RDr)
TsWAIT(Cf)
ThWAIT(Cf)
TdCr(Mlf)
TdCr(Mlr)
TdCr(RFSHf)
TdCr(RFSHr)
TdCf(RDr)
TdCr(RDf)
TsD(Cf)
1 to
1 to
i to
MREO
RD
RD
1
i
i
Delay
Data Hold Time to RD
i
WAIT Hold Time to
i to
i to
i to
i to
1 to
i to
110'
220'
50
i
Z8400H
1
Clock 1
60
45'
100'
30
70
60
70
60
30
0
60
0
100
100
130
120
0
50
0
70
70
95
85
60
60
0
80
80
110
100
70
70
85
85
50
60
60
70
80
70
0
0
130
130
180
150
110
110
1 Delay
Clock
MI i Delay
Clock
RFSH 1 Delay
Clock
RFSH i Delay
Clock
RD i Delay
Clock
RD 1 Delay
Data Setup to Clock 1 during
MI
65'
135'
35
70
70
70
85
95
85
0
WAIT Setup Time to Clock
Clock
85
85
100
130
100
Delay
Delay
Data Setup Time to Clock
Z8400B
250'
165'
125'
65'
110'
55'
110 2000 65 2000 55 2000
30
20
10
30
20
10
110
90
80
65'
35'
20'
100
100
Delay
TwMREOh
TdCf(MREOr)
Z8400A
Min. Max. Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
Clock Cycle Time
TwCh
TdCr(A)
Z8400
Parameter
40
30
M2, M 3 , M4 or M5 Cycles
26
27
28
29
30
31
32
33
34
35
36
37
TdA(IOROf)
Address Stable Prior to IORO
TdCr(IOROf)
Clock
TdCf(IOROr)
TdCf(WRf)
TdDf(WRf)
TwWR
i to
Clock 1 to
1 Delay
IORO i Delay
Data Stable Prior to WR 1
Clock 1 to WR 1 Delay
Clock
TdD(WRf)
Data Stable Prior to WR
TdCr(WRf)
Clock
TdWRr(D)
Data Stable from WR
TdCf(HALT)
TwNMI
Clock
WR
i
TdCf(WRr)
i
to WR
1 to
320'
1
HALT
NMI Pulse Width
180'
90
110
190'
80'
1
i
i or 1
120'
80
60
55'
60
30'
300
80
60
100'
70
65
300
80
5'
- 55'
60'
55
60
70
135'
- 10'
80
Delay
25'
220'
20'
75'
65
70
80
100
Delay
110'
75
85
90
360'
WR Pulse Width
1 to
1
IORO
55
15'
225
260
70
60'
* For clock periods other than the minimums shown in the table, calculate parameters using the expressions in the table on the following page.
All timings are preliminary and subject to change.
29/33
147
Z8400
AC CHARACTERIST!CS (continued)
Z8400
N°
Symbol
38
T5BUSREQ(Cr)
BUSREQ Setup Time to Clock
39
TcBUSREQ(Cr)
BI..J$HEQ Hold Time
40
TdCr(BUSACKI)
Clock
1 to
41
TdCI(BUSACKr)
clock
-l-
42
TdCr(Tz)
Clock
43
TdCr(CTz)
Parameter
(ns)
BUSACK
to BUSACK
1 to
Clock 1 to
1
alter Clock 1
80
-l-
-
Data Float Delay
Control Ou!2.!!.ts Flo~
Delay (MREQ, IORQ, RD, and WR)
1 to
TdCr(Az)
CIOQk
45
TdCTr(A)
MREQ I, IORQ I, RD
to Address Hold Time
46
T5RESET(Cr)
RESET to Clock
47
ThRESET(Cr)
11j:$ET to Clock
48
TsINTI(Cr)
and WR
1 Setup Time
1 Hold Time
INT to
ThINTr(Cr)
50
TdMII(IORQI)
MJ-l-
51
TdCI(IORQI)
Clock
-l-
52
TdCI(IORQr)
Clock
1 to
53
TdCI(D)
Clock
-l-
-l-
to IORQ
IORQ
Z8400H
(n5)
(ns)
(n5)
(n5)
40
50
0
0
0
100
90
110
100
90
80
90
90
80
70
110
80
70
60
160*
90
80*
0
70
20*
45
60
0
80
920*
80
80
35*
60
80
Delay
-l-
Z8400B
120
0
1 Setup Time
Clock 1 Hold Time
to IORQ
1
(ns)
50
90
INTto Clock
49
(ns)
110
Address Float Delay
I,
(ns)
0
Delay
1 Delay
44
Z8400A
Min. Max. Min. Max. Min. Max. Min. Max.
0
0
70
55
0
565*
0
0
365*
270'
Delay
110
85
70
1 Delay
100
85
70
60
230
150
130
115
to Data Valid Delay
60
• For clock periods other than the minimums shown in the table, calculate parameters using the expressions on the following table
All timings are preliminary and subject to change.
FOOTNOTES TO AC CHARACTERISTICS
N°
Symbol
Z8400
Z8400A
Z8400B
1
TcC
TwCh + TwCI + TrC + TIC
TwCh + TwCI + TrC + TIC
TwCh + TwCI + TrC + TIC
2
TwCh
Although static by deSign,
TwCh 01 greater than 200
/-1s is not guaranteed.
Although static by deSign,
TwCh 01 greater than 200
/-1s is not guaranteed.
Although static by design,
TwCh 01 greater than 200
/-1s is not guaranteed.
TwCh + TIC - 50
7
TdA(MREQf)
TwCh + TIC - 75
TwCh + TIC - 65
10
TwMREQh
TwCh + TIC - 30
TwCh + TIC - 20
TwCh + TIC - 20
11
TwMREQI
TcC - 40
TcC - 30
TcC - 30
26
TdA(IORQI)
TcC - 80
TcC - 70
TcC - 55
29
TdD(WRI)
TcC - 210
TcC - 170
TcC - 140
31
TwWR
TcC - 40
TcC - 30
TcC - 30
33
TdD(WRI)
TwCI + TrC - 180
TwCI + TrC - 140
TwCI + TrC - 140
35
TdWRr(D)
TwCI + TrC - 80
TwCI + TrC - 70
TwCI + TrC - 55
45
TdCTr(A)
TwCI + TrC - 40
TwCI + TrC - 50
TwCI + TrC - 50
50
TdMII(IORQI)
2TcC + TwCh + TIC - 80
2TcC + TwCh + TIC - 65
2TcC + TwCh + TIC - 50
AC Test Conditions:
= 2.0 V
VIL = 0.8 V
V,He = Vee - 0.6 V
V,H
30/33
148
Vile = 0.45 V
VOH = 2.0 V
VOL = 0.8 V
FLOAT = ± 0.5 V
Z8400
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
T st9
Storage Temperature Range
TA
Temperature under Bias
VI
Voltages on all Inputs and Outputs with respect to GND
Po
Power Dissipation
Value
Unit
- 65 to + 150
°C
- 0.3 + 7.0
V
__
._-'. '--_..W
Specified Operating Range
1.5
.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Ex·
posure to absolute maximum rating conditions for extended periods may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND (OV). Positive cur·
rent flows into the referenced pin. Available operating temperature ranges are:
• O'C to + 70 'C,
+ 4.75 V ~ Vee 5,+ 5.25 V
• - 40 'c to + 85 'C,
+ 4.75 V ~ Vee ~ + 5.25 V
• -55 'C to + 125 'C,
+ 4.75 V ~ Vee ~ + 5.25 V
load up to a maximum of 200pF for the data bus and
1OOpF for address and control lines.
.ov
All ac parameters assume a load capacitance of
50pF. Add 10ns delay for each 50pF increase in
31/33
149
Z8400
DC' CHARACTERISTICS
Symbol
Test Conditions
Parameter
Min.
Max.
Unit
- 0.3
0.45
V
VILC
Clock Input Low Voltage
VIHC
Clock Input High Voltage
VIL
Input Low Voltage
- 0.3
o.a
V
VIH
Input High Voltage
2.0
Vcc
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage
Icc
Power Supply Current
zao
ZaOA
ZaOB
ZaOH
Vee - 0.6 Vee + 0.3
=2
IOH = -
IOL
mA
250
!IA
= 0 to Vcc
= 0.4 to Vcc
III
Input Leakage Current
VIN
ILO
3·State Output Leakage Current in
Float
VOUT
2.4
V
V
150 '
200 2
200
200
mA
mA
mA
mA
-
10
- 10
10
!IA
!IA
Min.
Max.
Unit
35
pF
5
pF
10
pF
Notes: 1. For military grade parts, Icc is 200 rnA.
2. Typical rate lor Z8400A is 90 rnA.
_
3. A,s·""', 0,.00, MREO, IORO, RO, and WR.
CAPACITANCE
Symbol
Parameter
CCLOCK
Clock Capacitance
CIN
Input Capacitance
COUT
Output Capacitance
TA = 25 'C, 1= 1 MHz.
32/33
150
Note
Unmeasured pins returned to
ground
Z8400
ORDERING INFORMATION
Temp.
Clock
Z8400B1
Z8400F1
Z8400D1
Z8400D6
Z8400D2
Z8400C1
DIP·40 (plastic)
Dlp·40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
- 55/ + 125°C
0/ + 70°C
2.5 MHz
Z8400AB1
Z8400AF1
Z8400AD1
Z8400AD6
Z8400AD2
Z8400AC1
DIP-40 (plastic)
DIP-40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
-55/ + 125°C
0/+ 70°C
4 MHz
Z8400BB1
Z8400BF1
Z8400BD1
Z8400BD6
Z8400BD2
Z8400BC1
DIP-40 (plastic)
DIP-40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
-55/+125°C
0/+ 70°C
6 MHz
Z8400HB1
Z8400HF1
Z8400HD1
Z8400HD6
Z8400HC1
DIP-40 (plastic)
DIP-40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+
0/+
0/+
-40/+
0/+
8 MHz
Type
Package
70°C
70°C
70°C
85°C
70°C
Description
Z80 Central
Processing Unit
33/33
151
Z8410
Z80 DMA DIRECT MEMORY ACCESS CONTROL
• TRANSFERS, SEARCHES AND SEARCH/
TRANSFERS IN BYTE-AT-A-TIME, BURST OR
CONTINUOUS MODES. CYCLE LENGTH AND
EDGE TIMING CAN BE PROGRAMMED TO
MATCH THE SPEED OF ANY PORT.
• DUAL PORT ADDRESSES (sources and destination) GENERATED FOR MEMORY-TO-I/O,
MEMORY-TO-MEMORY,
OR
I/O-TO-I/O
OPERATIONS
ADDRESSES MAY BE FIXED OR AUTOMATICALLY INCREMENTED/DECREMENTED
• NEXT-OPERATION LOADING WITHOUT DISTURBING CURRENT OPERATIONS VIA BUFFERED STARTING ADDRESS REGISTERS.
AN ENTIRE PREVIOUS SEQUENCE CAN BE
REPEATED AUTOMATICALLY
• EXTENSIVE PROGRAMMABILITY OF FUNCTIONS. CPU CAN READ COMPLETE CHANNELSTATUS
• STANDARD
FAMILY BUS-REQUEST AND
PRIORITIZED INTERRUPT-REQUEST DAISY
CHAINS IMPLEMENTED WITHOUT EXTERNAL LOGIC. SOPHISTICATED, INTERNALLY
MODIFIABLE INTERRUPT VECTORING
• DIRECT INTERFACING TO SYSTEM BUSES
WITHOUT EXTERNAL LOGIC
zao
o
B/F
DlP-40
(Plastic and Frit-Seal)
DIP-40
(CeramiC)
C
PLCC44
(Plastic)
(Ordering Information at the end of the datasheet)
LOGIC FUNCTIONS
..,
A,
DESCRIPTION
zao
The
DMA (Direct Memory Access) is a powerful ad versatile device for controlling and processing
transfers of data. Its basic function of managing
CPU-independent transfers between two ports is
augmented by an array of features that optimize
transfer speed and control with little or no external
logic in systems using an
or 16-bit data bus and
a 16-bit address bus.
..'"
.
..
. . -1
A,
DATA
BUS
BUS {
CONTROL
ADDRESS
BUS
A"
28410
a-
Transfers can be done between any two ports
(source and destination), including memory-to-I/O,
memory-to-memory, and I/O-to-I/O. Dual port addresses are automatically generated for each transaction
and
may
be
either
fixed
or
incrementing/decrementing. In addition, bit-maskable byte searches can be performed either concurrently with transfers or as an operation in itself.
SYATI."
A,
Au
A"
Au
Au
A"
··...·1
CONTROL
BUS
RO'
}
CflwAIT
DMA
CONTROL
iiitlPUlSE
}
Vee
OND
INTERRUPT
CONTROL
eLK
zao
The
DMA contains direct interfacing to and independent control of system buses, as well as soph1/22
September 1988
153
- - - - - - - - - - - - - - - - - - --
-------~-----------
----
Z8410
isticated bus and interrupt controls. Many pro,
grammable features, including variable cycle timing
and auto-restart, minimize CPU software overhead.
They are especially useful in adapting this specialpurpose transfer processor to a broad variety of
memory, I/O and CPU environments.
The Z80 DMA is an n-channel silicon-gate depletion-load device packaged in a 40-pin plastic or ceramic DIP. It uses a single + 5 V power supply and
the standard Z80 Family single-phase clock.
Figure 1 : Dual in Line Pin Configuration.
FUNCTIONAL DESCRIPTION
Classes of Operation. The Z80 DMA has three basic
classes of operation:
• Transfers of data between two ports (memory or
I/O peripheral)
• Searches for a particular 8-bit maskable byte at
a single port in memory or an I/O peripheral
• Combined transfers with simultaneous search
between two ports
Figure 4 illustrates the basic functions served by
these classes of operation.
During a transfer, the DMA assumes control of the
system address and data buses. Data is read from
one addressable port and written to the other addressable port, byte by byte. The ports may be
programmed to be either system main memory or
peripheral I/O devices. Thus, a block of data may be
written from one peripheral to another, from one
area of main memory to another, or from a peripheral to main memory and vice versa.
....
..
A,
A,
Vee
fiRm
During a search-only operation, data is read from
the source port and compared byte by byte with a
DMA-intemal register containing a programmable
match byte. This match byte may optionally be
masked so that only certain bits within the match
byte are compared.
Search rates up to 1.25M bytes per second can be
obtained with the 2.5 MHz Z80 DMA or 2M bytes
per second with the 4 MHz Z80 DMA.
In combined searches and transfers, data is transferred between two ports while simultaneously
searching for a bit-maskable byte match.
Data transfers or searches can be programmed to
stop or interrupt under various conditions. In addition, CPU-readable status bits can be programmed
to reflectthe condition.
12
jUSREQ
CElWAlT
Au
Figure 2 : Chip Carrier Pin Configuration.
MODES OF OPERATION
Ii
5
I.
j
2
I
44
43
42
~1
40
39
00
36
0,
37
0]
36 . OJ
35
Z8410
GND
))
Os
32
06
)1
07
)0
MI
29
'---,n"".",,1O,'r'",'.,.',"TT',',"rr"n','.,.','--'
NC
2/22
154
=
NO CONNECTION
04
]l.
N..c.
5-8098
TheZ80 DMAcan be programmed to operate in one
of three transfer and/or search modes:
• Byte-at-a-Time: data operations are performed
one byte at a time. Between each byte operation
the system buses are released to the CPU. The
buses are requested again for each succeeding
byte operation.
• Burst: data operations continue until a port's
Ready line to the DMA goes inactive. The DMA
then stops and releases the system buses after
completing its current byte operation.
• Continuous: data operations continue until the
end of the programmed block of data is reached
before the system buses are releases. If a port's
Ready line goes inactive before this occurs, the
DMA simply pauses until the Ready line comes
active again.
Z8410
Figure 3 : Typical Z80 Environment.
Figure 4 : Function of the Z80 DMA.
SYSTEM
BUSES
Z·80 DIIA
OM ..
CPU
1 . Search memory
2. Transfer memory·to-memory (optional search)
3. Transfer memory·to-I/O (optional search)
4. Search 1/0
5. Transfer 1/0·to-1/0 (optional search)
, . . RDY
lEI
DMA until it is again enabled by a specific command.
Status bytes can also be read at any such time, but
writting the Read Status Byte command or the Initiate Read Sequence command disables the DMA.
Control bytes to the DMA include those which effect
immediate command actions such as enable, disable, reset, load starting-address buffers, continue,
clear counters, clear status bits and the like. In addition, many mode-setting control bytes can be written, including mode and class of operation, port
configuration, starting addresses, block length, address counting rule, match and match-mask byte,
interrupt conditions, interrupt vector, status-affectsvector condition, pulse counting, auto restart,
Ready-line and Wait-line rules, and read mask.
lEO
=r'E'
I
-....RDY
5.0
OM..
~
1'(
7 ........._
.......
In all modes, once a byte of data is read into the
DMA, the operation on the byte will be completed in
an orderly fashion, regardless of the state of other
signals (including a port's Ready line).
Due to the DMA's high-speed buffered method of
reading data, operations on one byte are not comoleted until the next byte is read in. This means that
total transfer or search block lengths must be two or
more bytes, and that block lengths programmed into
the DMA must be one byte less than the desired
olock length (cant is N-1 where N is the block
length).
COMMANDS AND STATUS
The Z80 DMA has several writable control registers
and readable status registers available to the CPU.
Control bytes can be written to the DMA whenever
the DMA is not controlling the system buses, but the
act of writing a control byte to the DMA disables the
~
At."fI
Readable status registers include a general status
byte reflecting Ready-line, end-of-block, byte-match
and interrupt conditions, as well as 2-byte registers
for the current byte count, Port A address and Port
B address.
VARIABLE CYCLE
The Z80 DMA has the unique feature of programmable operation-cycle length. This is valuable in tailoring the DMA to the particular requirements of
other system components (fast or slow) and
maximizes the data-transfer rate. It also eliminates
external logic for signal conditioning.
There are two aspects to the variable cycle feature.
First, the entire read and write cycles (periods) associated with the source and destination ports can
be independently programmed as 2,3 or 4 T-cycles
long (more if Wait cycles are used), thereby increasing or decreasing the speed with which all DMA signals change (figure 5).
SGS·THOMSON
~D©III@lOI!.rn©'irIll@IllD©i!I
3122
155
Z8410
Second, the four signals in each port specifically associated with transfers of data (1/0 Request, Memory Request, Read, and Write) can each have its
active trailing edge terminated one-half T-cycle
early. This adds a further dimension of flexibility and
speed, allowing such things as shorter-than-normal
Read or Write signals that go inactive before data
starts to change.
Figure 5 : Variable Cycle Lenght..
eLI<
E 2.cYCLE~_I
EARL Y ENDING
FOR CONTROL SIGNALS
I
3-CYClE~
ADDRESS GENERATION
Two 16-bit addresses are generated by the lao
DMA for every transfer operation, one address for
the source port and another for the destination port.
Each address can be either variable or fixed. Variable addresses can increment or decrement from
the programmed starting address. The fixed-address capability eliminates the need for separate enabling wires to 1/0 ports.
Port addresses are multiplexed onto the system address bus, depending on whether the DMA is reading the source port or writing to the destination port.
Two readable address counters (2 bytes each) keep
the current address of each port.
AUTO RESTART
The starting addresses of either port can be reloaded automatically at the end of a block. This option is selected by the Auto Restart control bit. The
byte counter is cleared when the addresses are reloaded.
The Auto Restart feature relieves the CPU of software overhead for repetitive operations such as
CRT refresh and many others. Moreover, when the
CPU has access to the buses during byte-at-a-time
or burst transfers, different starting addresses can
be ~ritten into buffer registers during transfers,
causing the Auto Restart to begin at a new location.
INTERRUPTS
The laO DMA can be programmed to interrupt the
CPU on three conditions:
• Interrupt on Ready (before requesting bus)
• Interrupt on Match
• Interrupt on End of Block
Any of t~ese interrupts cause an interrupt-pending
status bit to be set, and each of them can optionally
alter the DMA's interrupt vector. Due to the buffered
?onstraint mentioned under "Modes of Operation",
Interrupts on Match at End of Block are caused by
matches to the byte just prior to the last byte in the
block.
The DMA shares the laO Family's elaborate interrupt scheme, which provides fast interrupt service
in real-time applications. In alaO CPU environment,
4/22
156
4·CYCLE
~
the DMA passes its internally modifiable a-bit interrupt vector to the CPU, which adds an additional
eight bits to form the memory address of the interrupt routine table. This table contains the address
of the beginning of the interrupt routine itself. In this
process ; CPU control is transferred directly to the
interrupt routine, so that the next instruction executed after an interrupt acknowledge is the first instruction of the interrupt routine itself.
PULSE GENERATION
External devices can keep track of how many bytes
have been transferred by using the DMA's pulse
output, which provides asignal at 256-byte intervals.
The interval sequence may be offset at the beginning by 1 to 255 bytes.
The Interrupt line outputs the pulse signal in a manner. that prevents misinterpretation by the CPU as
an Interrupt request, since it only appears when the
Bus Request and Bus Acknowledge lines are both
active.
PIN DESCRIPTIONS
Ao·A15. System Address Bus (Output, 3-state). Addresses generated by the DMA are sent to both
source and destination ports (main memory or 1/0
peripherals) on these lines.
BAl. Bus Acknowledge In (Input, Active Low). Signals that the system buses have been released for
DMA control. In multiple-DMA configurations, the
BAI pin of the highest priority DMA is normally connected to the Bus Acknowledge--2Ln of the CPU.
Lower-priority DMAs have their BAI connected to
the BAO of a higher-priority DMA.
B~s Acknowledge Out (Output, Active Low).
In a multlple-DMA configuration, this pin signals that
non other high~iority DMA has requested the
system buses. BAI and BAO from daisy chain for
multiple-DMA priority resolution over bus control.
BAO.
Z8410
BUSREQ. Bus Request (Bidirectional, Active Low,
Open Drain). As and output, it sends requests for
control of the system address bus, data bus and
control bus to the CPU. As an input, when multiple
DMAs are strung together in a priority daisy chain
via BAI and BAO, it senses when another DMA has
requested the buses and causes this DMA to refrain
from bus requesting until the other DMA is finished.
Because it is a bidirectional pin, there cannot be any
buffers between this DMA and any other DMA. It
can, however, have a buffer between it and the CPU
because it is unidirectional into the CPU. A pull-up
resistor is connected to this pin.
CElWAIT. Chip Enable and Wait (Injllit, Active
Low). Normally this functions only as a CE line, but
it can also be programmed to serve a WAIT func,
tion. As a CE line from the CPU, it becomes active
when WR and 10RO are active and the 1/0 port address on the system address bus is the DMA's address, thereby allowing a transfer of control or
command bytes from the CPU to the DMA. As a
WAIT line from memory or 1/0 devices, after the
DMA has received a bus-request acknowledge from
the CPU, it causes wait states to be inserted in the
DMA's operation cycles thereby slowing the DMA to
a speed that matches the memory or 1/0 device.
ClK. System Clock (Input). Standard zao singlephase clock at 2.5MHz (ZaO DMA) or 4.0MHz (ZaO
DMA). For slower system clocks, a TTL gate with a
pullup resistor may be adeguate to meet the timing
and voltage level specification. For higher-speed
systems, use a clock driver with an active pullup to
meet the VIH specification and risetime requirements. In all cases there should be a resistive pullup to the power supply of 1OKohms (max) to ensure
proper power when the DMA is reset.
00-07. System Data Bus (Bidirectional, 3-state).
Commands from the CPU, DMA status, and data
from memory or 1/0 peripherals are transferred on
these lines.
lEI. Interrupt Enable In (Input, Active High). This is
used with lEO to from a priority daisy chain when
there is more than one interrupt-driven device. A
High on this line indicates that no other device of
higher priority is being serviced by a CPU interrupt
service routine.
lEO. Interrupt Enable Out (Output, Active High). lEO
is High only if lEI is High and the CPU is not servicing an interrupt from this DMA. Thus, this signal
block lower-priority devices from interrupting while
a higher-priority device is being serviced by its CPU
interrupt service routine.
INT/PULSE. Interrupt Request (Output, Active Low,
Open Drain). This requests a CPU interrupt. The
CPU acknowledges the interrupt by pulling its 10RO
output Low during an M1 cycle. It is typically connected to the INT pin of the CPU with a pullup resistor and tied to all other INT pins in the system. This
pin can also be used to generate periodic pulses to
an external device. It can be used this way~
when the DMA is bus master (Le., the CPU's BUSREO and BUSACK lines are both Low and the CPU
cannot see interrupts).
IORQ. Input/Output Request (Bidirectional; Active
Low, 3-state). As an input, this indicates that the
lower half of the address bus holds a valid 1/0 port
address for transfer of control or status bytes from
or to the CPU, r~ectively ; thjLPMA is the addressed port if its CE pin and its WR or RD pins are
simultaneously active. As an output, after the DMA
has taken control of the system buses, it indicates
that the a-bit or 16-bit address bus holds a valid port
address for another 1/0 device involved in a DMA
transfer of data. When 10RO and M1 are both active simultaneously, an interrupt acknowledge is indicated.
M1. Machine Cycle One (Input, Active Low). Indicates that the current CPU machine cycle is an instruction fetch. It is used by the DMA to decode the
return-from-interrupt instruction (RETI) (ED-4D)
sent b.Y...1he CPU. During two-byte instruction fetches, M1 is active as each opcode byte is fetched.
An interrupt acknowledge is indicated when both M1
and 10RO are active.
MREQ. Memory Request (Output, Active Low, 3state). This indicates that the address bus holds a
valid address for a memory read or write operation.
After the DMA has taken control of the system
buses, it indicates a DMA transfer request from or
to memory.
RD. Read (Bidirectional, Active Low, 3-state). As an
input, this indicates that the CPU wants to read
status bytes from the DMA's read registers. As an
output, after the DMA has taken control of the system buses, it indicates a DMA-controlled read from
a memory or 1/0 port address.
ROY. Ready (Input, Programmable Active Low or
High). This is monitored by the DMA to determine
when a peripheral device associated with a DMA
port is ready for a read or write operation. Depending on the mode of DMA operation (Byte, Burst or
Continuous), the RDY line indirectly controls DMA
activity by causing the BUSREO line to go Low or
High.
WR. Write (Bidirectional, Active Low, 3-state). As
and input, this indicates that the CPU wants to write
control or command bytes to the DMA write registers. As an output, after the DMA has taken control
of the system buses, it indicates a DMA-controlled
write to· a memory or 1/0 port address.
5122
157
Z8410
INTERNAL STRUCTURE
The internal structure of the Z80 DMA includes
driver and receiver circuitry for interfacing with an 8bit system data bus, a 16-bit system address bus,
and system control lines (figure 6). In a Z80 CPU
environment, the DMA can be tied directly to the
analogous pins on the CPU (f!ruir.e 7) with no additional buffering, except for the CElWAIT line.
transfer channel are multiplexed onto the system
address bus.
Specialized logic circuits in the DMA are dedicated
to the various functions of external bus interfacing,
internal bus control, byte matching, byte counting,
periodic pulse generation, CPU interrupts, bus request, and address generation. A set of twenty-one
writable control registers and seven readable status
registers provides the means by which the CPU governs and monitors the activities of these logic circuits. All registers are eight bits wide, with
The DMA's internal data bus interfaces with the system data bus and services all internal logic and registers. Addresses generated from this logic for Ports
A and B (source and destination) of the DMA's single
Figure 6: Block Diagram.
SYSTEM
DATA fL--L.....L.~
BUS
(881T)
MUX
\r---r---.--'/
SYSTEM
ADDRESS
BUS
(111 BIT)
CONTROL \r-----,'"
Figure 7: Multiple-DMA Interconnection to the Z80 CPU.
.--------1 BUSACK
M1
CPU
lORD
UREQ
HU
Wli
ClK
Ao-A15
00-7
FROM HIGHER·PRIORITY
TO LOWER·PRIORITY
INTERRUPTING DEVICE
INTERRUPTING DEVICE
FROM
6/22
158
FROM
UO
110
DEVICE
DEVICE
Z8410
double-byte information stored in adjacent registers.
The two address counters (two bytes each) for Ports
A and B are buffered by the two stating addresses.
The 21 writable control register are organized into
seven base-register groups, most of which have
multiple registers. The base registers in each writable group contain both control/command bits and
pointer bits that can be set to address other registers within the group. The seven readable status
registers have no analogous second-level registers.
The registers are designated as follows, according
to their base-register groups:
WRO-WR6 - Write Register groups 0 through 6
(7 base registers plus 14 associated registers)
Write Registers
WRO
WR1
WR2
WR3
WR4
RRO-RR6 - Read Registers 0 through 6
Writing to a register within a write-register group involves first writing to the base register, with the appropriate pointer bits set, then writing to one or more
of the other register within the group. All seven of
the readable status registers are accessed sequentially according to a programmable mask contained
in one of the writable registers. The section entitled
"Programming" explains this in more detail.
A pipelining scheme is used for reading data in. The
programmed block length is the number of bytes
compared to the byte counter, which increments at
the end of each cycle. In searches, data byte comparisons with the match byte are made during the
read cycle of the next byte. Matches are, therefore,
discovered only after the next byte is read in.
In multiple-DMA configurations, interrupt request
daisy chains are priorized by the order in which their
lEI and lEO lines are connected. The system bus,
however, may not be pre-empted.
Any DMA that gains access to the system bus keeps
the bus until it is finished.
PROGRAMMING
The Z80 DMA has two programmable fundamental
states: (1) an enabled state, in which it can gain
:ontrol of the system buses and direct the transfer
Jf data between ports, and (2) a disabled state, in
Nhich it can initiate neither bus requests nor data
:ransfers. When the DMA is powered up or reset by
my means, it is automatically placed into the dis~bled state. Program commands can be written to
t by the CPU in either state, but this automatically
Juts the DMA in the disabled state, which is mainained until an enable command is issued by the
~PU. The CPU must program the DMA in advance
)f any data search or transfer by addressing it as an
/0 port and sending a sequence of control bytes
WR5
WR6
Base Register Byte
Port A starting Address (low byte)
Port A starting Address (high byte)
Block Length (low byte)
Block Length (high byte)
Base Register Byte
Port A Variable-timing Byte
Base Register Byte
Port B Variable-timing Byte
Base Register Byte
Mask Byte
Match Byte
Base Register Byte
Port B starting Address (low byte)
Port B starting Address (high byte)
Interrupt Control Byte
Pulse Control Byte
Interrupt Vector
Base Register Byte
Base Register Byte
Read Mask
Read Registers
RRO
RR1
RR2.
RR3
RR4
RR5
RR6
Status Byte
Byte Counter (low byte)
Byte Counter (high byte)
Port A Address Counter (lOW byte)
Port A Address Counter (high byte)
Port B Address Counter (low byte)
Port B Address Counter (high byte)
using an Output instruction (such as.OTIR for the
Z80 CPU).
WRITING.
Control or command bytes are written into one or
more of the Write Register groups (WRO-WR6) by
first writing to the base register byte in that group.
All groups have base registers and most groups
have additional associated registers. The associated registers in a group are sequentially accessed
by first writing a byte to the base register containing
register-group identification and ponter bits (1 's) to
one or more of that base register's associated registers.
This is illustrated in figure 8b. In this figure, the sequence in which associated registers within a group
can be written to is shown by the vertical position of
the associated registers. For example, if a byte written to the DMA contains the bits that identify WRO
(bits DO, 01 and 07), and also contains 1's in the bit
positions that point to the associated "Port A Starting Address (low byte)" and "Port A Starting Address
(high byte)", then the next two byte written to the
DMA will be stored in these two registers, in that
order.
Gi
SGS·THOMSON
~I ~n©II@[;I!.I<@'ii'IliI@OOn©iI!
7/22
159
Z8410
Figure Sa : Read Registers.
Read Register 0
0, 0,
o~
D. D, Dz 0,
III
_
I
Read Register 2
Dv
1X 1X I 1 1 1xiii
STATUS Bm
L-,0 ""= READY
OMA TRANSFER HAS OCCURRED
ACTIVE
o :=
O:z:
o ::::
LI~1L-lI--l.I-,-I~IL....J.--'-....JI BYTE COUNTER (lOW BYTE)
Read Register :3
INTERRUPT PENDING
1
...._1'----11----.1--,-I-,-I--'-...L.-II PORT A ADDRESS COUNTER (lOW BVTEl
MATCH FOUND
END OF BLOCK
Read Register ..
Read Register 1
LI....Jlo.-ll---L.1~I....JI--l.-'......JI BYTE COUNTER (HIGH BYTE)
LI_1L..lI--l.I-'...1--,--I--'---'--II PORT A ADDRESS COUNTER (HIGH BVTE)
Read Register 5
1
...._1'----11--1.1___I _1'----'--'--'1
PORT B ADDRESS COUNTER (lOW BYTE)
Read RegUler 6
LI_1'----'i--'-I-'-1-J1L....J.--l.....J1
READING
The Read Registers (RRO-RR6) are read by the
CPU by addressing the DMA as an I/O port using
and Input instruction (such as INIR forthe Z80 CPU).
The readable bytes contain DMA status, bytecounter values, and port addresses since the last
DMA reset. The registers are always read in a fixed
sequence beginning with RRO and ending with RR6.
However, the register read in this sequence is determined by programming the Read Mask in WR6. The
sequence of reading is initialized by writing an Initiate Read Sequence or Set Read Status command
to WR6. After a Reset DMA, the sequence must be
initialized with the Initiate Read Sequence command or a Read Status command. The sequence
of reading all registers that are not excluded by the
Read Mask register must be completed before a
new Initiate Read Sequence or Read Status command.
FIXED-ADDRESS PROGRAMMING
A special circumstance arises when programming
a destination port to have a fixed address. The load
command in WR6 only loads a fixed address to a
port selected as the source, not to a port selected
as the destination.
8/22
160
PORT B ADDRESS COUNTER (HIGH . " "
Therefore, a fixed destination address must be
loaded by temporarily declaring it a fixed-source address and subsequently declaring the true sou rce
as such, thereby implicitly making the other a destination.
The following example illustrates the steps in this
procedure, assuming that transfers are to occur
from a variable-address source (Port A) to a fixedaddress destination (Port B) :
• 1. Temporarily declare Port B as source in WRO.
• 2. Load Port B address in WR6.
• 3. Declare Port A as source in WRO.
• 4. Load Port A address in WR6.
• 5. Enable DMA in WR6.
Figure 9 illustrates a program to transfer data from
memory (Port A) to a peripheral device (Port B). In
this example, the Port A memory starting address is
1050H and the Port B peripheral fixed address is
05H. Note that the data flow is 1001 H bytes - one
more than specified by the block length. The table
of DMA commands may be stored in consecutive
memory locations and transferred to the DMA with
an output instruction such as the Z80 CPU's OTIR
instruction.
Z8410
Figure 8b : Write Registers.
Writ. R.gtat... 0 Group
bro.DIO.DJ~D.n.
I· I I I I I I I I..............""
I!!
o
OONOT . . .
1 .. TRAMSF£R
1
D" KARCH
I
1 _ S.£AACHlYMHV"I:R
O-PORTs_POtn"
1_ PORTA_I'ORTI
,r'-r'-"""'-'-r-r-r-, PORT A STARnNO AO()fI;£SS
L-LrLlrLl'~~~~~aw.nQ
,r'-r'-n..,..-r-, PORT A STARTING AOo..ESS
Writ. R~_" Group
0., 0. n., o. 0,0, 0,0.,
I, I I I
'TTE
I 11 I
0
RASE R[CUSTER aYTE
.1 !
CONTrNUOUS _ II
aURST _ 1
00 NOT PROQRAM .. 1
.-..--...--.J.,-L..,-"-r-r-'PORT II STARTING ADDRESS
L-L-~~I~~......J.-L~~OWIYT~
.--..--.~J.,"-r-r-r--' PORT" STARTING
ADDRESS
L-L-~~
l~~--'-~ (HIGH Brr£)
L-LrLr~~~~-l~~H8nQ
.-r'-Ir'-~rr-"--'-.
c:..~--,~~~--,---, INTERRUPT CONTROL I'(TE
.COCK LENGTN
L-LrL-~-i~~-l~OW8nQ
..-.'-*,....,..,,--,-,---, BLOCK LENGTH
'-L....L....L-'---.J.-L-L~ (HIGH IIYTe
I I I I !"'
INTERRUPT ON MATCH
1 "" INTERRUPT AT fND Or: BLOCK
I .. PULSE GENERATED
INTERRUPT ON ROY'"' 1
STATUS AFFECTS VECTOR" 1
'-L-L-y--'~-L~ PULSE CONTROL BYTE
Writ. Register I Group
I
DrD.D~D.D:!OZD,D.
',I I III'I'I'IOASER"OSTER.TTT
l.
1 1
o
0
1
.~
PORT A IS MEMORY
1 -" PORTA IS 110
.. PORT A ADDRESS DECREMENTS
'" PORT A ADDRESS INCREMENTS
I..
Iffi
I I ! !"
!I
CYCLE EAlltY ""
ENDS VII CYCLE EARLY = 0
MREO ENDS Yo CYCLE EARLY
~
II
VECTOR IS AUTOMATICALLY { '
IIIODIFIED AS SHOWN
ONLYIF-sTATUS
AFFECTS VECTOR
n
BrT IS SET
0
1
•
1
0
1
1
'"
"
'"
'"
PORT Ii ADORESS AXED
L-L....'--'-'-:-"-L-,-'--:-' PORT'" VARIABLE nMINO BYTE
iiA ENDS,...
L-L-~I--,I~-,-I-,-I~IINTERRUPT VECTOR
0
0
CYCLE LENGTH ....
1:. CYCLE LENGTH .. J
,
0:. CYCLE LENGTH = 2
,
1 .. 00 HOT USE
ENDS y;, CYClE EARLY
INTERRUPT ON ROY
INTERRUPT ON MATCH
INTERRUPT ON END OF BLOCK
INTERRUPT ON MATCH
AND END OF BLOCK
Wri!e Register 5 Group
0,0,0,0.0,0,0,0.
11 ! D) I I ! 0 11 E
II
o _ K»ia
BASE REGISTER 8YTE
I
o '"
READY ACTIVE LOW
READY ACTIVE HIGH
0= CEONLY
1 -' CElWAIT MUL TlPLEXEO
o STOP ON END OF BLOCK
1 - AUTO ReSTART ON END OF 8LOCK
Write RegUtH 2 Group
o,o.o.,D4~o,D,o.
1-.:
1,1 I II I'I"'IOASERE"""""'TTT
Write Regi:ster 6 Group
11
1.
o
o
0
1
.. PORT B ADDRESS DECREMENTS
'" POAT B AODRESS INCREMENTS
~
~
PORT' IS MEMORY
I=PORTBlSVO
D~
0, D.
It:
I
D.
[
0, 0,
! I i
I I Io I !
1_ PORT 8 AODRISS AXED
Wii
!I
ENOS .... CYCLE £ARL Y =
1
Iff) ENDS Yo CYClE EARLY - 0
ntO ENDS .... CYCLE EARLY", 0
0
= CYCLE LENGTH '" <4
1., CYCLE LENGTH "" 3
,
1
0 _ CYCLE LENQTW _ 2
1
DO NOT USE
1
0
I
0
o
o
o
o
t
1
o '"' lORa ENDS 'h CYCLE EARLY
o
D,D.D~D.~DzD,Do
1,1 I I
OIllA UtAIllE
_!
I
INTERRUPT fNAalE: _ 1
STOP ON MATCH
,
~--'--'-r'-LJ..-L--,"ASK 8YTE (D - COMPARE)
L-~--'--'~-'---'---' MATCH 8'fTE
NA.~
1" CI' - LOAD
0 '" DJ
CONTINUE
1
1 -e AI' '" DISABLE INTERflUPTS
0 --'~ All '" ENABLE INTERRUPTS
0
A3 = R~SH AND DISABLE INTERRUPTS
87 = ENAlllE AFTER RETI
I)
~
I)
t
~
1
1
1 = BF - RI:.AD STATUS BYTE
0 ~ liB -' REINITlALIZE STATUS BYTE
1)
1.., A7 '" INITIATE READ SEQUENCE
B3 "" FORCE READY
I .., 81 = ENABLE OhlIA
I) '" 113
J ..
BASE REGISTER BYTE
HIEX eOMMAND
o () -"
I I· I. JOASEREOISTER.TTE
0.
11 I
1 '" Cl '" RESET PORT A TIMING
0 ~ CB '" RESET PORT II TIMING
o
I! !
1
O"'CJ~RESET
o
'--'-:-'--L......J.-Lc-'-J..-,PORT B V.uUABlE TlMING BYTE
Dt
r-
Ll o !"
1
I)
1
= DISABLE OMA
0 ~ 68 ~
READ
=:==J
:
"'.lSI( f'OllOw~
READ MASK i1
~_
[ III L===
I
x
ENABLEr
:~~i gg~~~~= :~~v:, 8BYyTTE~
S>,,"' BYTE
PORT A ADDRESS (LOW BYTE)
PORT A ADORESS (HIGH aYTEJ
_ _ _ _ _ _ _ _ PORT B ADDRESS (LOW 8YTEI
.
PORT 8 ADDRESS (HIGH BYTE)
9/22
161
Z8410
Figure 9: Sample DMA Program.
Comments
07
06
Os
04
WRO sets DMA to receive
block length. Port A starting
address and temporarily sets
Port B as source.
0
1
1
1
1
Block Length
Upper
Follows
Block Length
Lower
Follows
Port A
Upper
Address
Follows
Port A
Lower
Address
Follows
Port A Address (lower)
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
03
~-
Port A Address (upper)
-----
- - - ---
__
Block Length (lower)
-----_.
.
--
Block Length (upper)
0
0
0
1
0
WR1 defines Port A as memory
with fixed incrementing address.
0
0
No Timing
Follows
0
Address
Changes
1
Address
Increments
0
Port is Memory
WR2 defines Port B as
peripheral with fixed address.
0
0
No Timing
Follows
1
Fixed Address
0
1
Port is
1/0
WR4 sets mode to Burst, sets
DMA to expect Port B address.
1
1
0
0
No Interrupt
Control Byte
Follows
0
No Upper
Address
--.----
Burst Mode
-
Port B Address (lower)
0
0
0
0
0
WR5 Sets Ready Active High.
1
0
0
No Auto
Restart
0
No Wait
States
1
RDY
Active High
WR6 Loads Port B Address and
Resets Block Counter .•
1
1
0
0
1
WRO Sets Port A as Source .•
0
0
0
0
0
No Address or Block Length Bytes
WR6 Loads Port A Address and
Resets Block Counter.
1
1
0
0
WR6 Enables DMA to start
operation.
1
0
0
0
Note: The actual number of bytes transferred is one more than specified by the block length.
* These entries are necessary only in the case of a fixed destination address.
10/22
162
1
Z8410
Figure 9: Sample DMA Program (continued).
Comments
D,
D2
1----.--------- ----.
WRO sets DMA to receive block length. Port A
starting address and temporarily sets Port B as
source.
Do
0
1
0
B->A
--Temporary for
Transfer. No Search
Loading B
Address'
HEX
79
----
__
50
AAddress
_Port
._
- _ .(lower)
.Port A Address (upper)
-_._---_."..-- ._----
0
0
0
0
0
0
10
Block
Length (lower)
c---.
________
.
0
0
0
00
Block
-_.-_
...
Length (upper)
.- ....
_~_._--_.-
---~--.----
--_.
0
10
0
14
0
1
0
28
1
Port BLower
Address
Follows
0
1
C5
WR1 defines Port A as memory with fixed
incrementing address.
1
WR2 defines Port B as peripheral with fixed
address.
WR4 sets mode to Burst. sets DMA to expect
Port B address.
-_ ..
0
0
--
0
, , - - -- -
Port B Address (lower)
1
0
1
05
WR5 Sets Ready Active High.
0
1
0
8A
WR6 Loads Port B Address and Resets Block
Counter. •
1
1
1
CF
0
1
05
----.
WRO Sets Port A as Source .•
1
A~B
Transfer. No Search
WR6 Loads Port A Address and Resets Block
Counter.
1
1
1
CF
WR6 Enables DMA to start operation.
1
1
1
87
Note: Jhe actual number of bytes transferred is one more than specified by the block length.
TllAse entries are necessary Dilly In the case of a fixed destination address.
11/22
163
Z8410
INACTIVE STATE TIMING (DMA as CPU
Figure 10 : CPU-to-DMA Write Cycle
Peripheral).
In its disabled or inactive state, the DMA is addressed by the CPU as an I/O peripheral for write
and read (control and status) operations. Write timing is illustrated in figure 10.
Reading of the DMA's status byte, byte counter or
port address counters is illustrated in figu re 11.
These oRerations re£.ldire less than three T-cycles.
The CE, lORa and RD lines are made active over
two rising edges of ClK, and data appears on the
bus approximately one T-cycle after they become
active.
Figure 11 : CPU-to-DMA Read Cycle.
CLK~
ACTIVE STATE TIME (DMA as Bus Control-
IO~:----'\1
ler).
00-:: ----.-(
DEFAULT READ AND WRITE CYCLES
By default, and after reset, the DMA's timing of read
and write operations is exactly the same as the Z80
CPU's timing of read and write cycles for memory
and I/O peripherals, with one exception: during a
read cycle, data is latched on the falling edge of T3
and held on the data bus across the boundary between read and write cycles, through the end of the
following write cycle.
Memory-to-I/O Transfer.
f----I T,
Ao-A15
READ
I
~
I
-_1-___
TJ
1
110 WRITE
T~
I
--~-I
~
[
TJ
MREa
AD
1
'ORa
-+-+-+-+---t---t-.'-+--+--+--'
'! \ --
164
~
-+"---+-+-I---i""---I--t-t--I----..oA-
O"'Th
TDAt"--
12/22
I
J
l
WROTE
MEMORY READ
Ij ---
The default timing uses three T-cycles for memory
transactions and four T-cycles for I/O transactions,
which include one automati@!!y inserted wait cycle
between T2 and 1i.JLthe CElWAIT line is programmed to act a WAIT line during the DMA's active state, it is sampled on the falling edge of T2 for
memory transactio!l§...and the falling edge of Tw for
I/O transactions. If CE/WAIT is low during this time
another T-cycle is added, during which the
CEIWAIT line will again be sampled. The duration
of transactions can thus be indefinitely extended.
Figure 12 illustrates the timing for memory-to-I/O
port transfers and figure 13 illustrates I/O-to-memory transfers. Memory-to-memory and I/O-to-I/O
transfers timings are simply permutations of these
diagrams.
Figure 12
I~---
Z8410
VARIABLE CYCLE AN EDGE TIMING
The Z80 DMA's default operation-cycle length for
the sou~ce (read) port and destination (write) port
can be Independently programmed. This variablecycle feature allows read or write cycles consisting
of two, three of fou r-T -cycle (more if Wait cycles are
inserted), thereby increasing or decreasing the
speed of all signals generateQ.Qyjhe DMA. In addition, the trailing edges of the 10RO, MREO, RD and
WR signals can be independently terminated onehalf cycle early. Figure 14 illustrates this.
In the variable-cycle mode, unlike default timing,
10RO comes active one-half cycle before MREO,
RD and WR. CE/WAIT can be used to extend only
the 3 or 4 T -cycle variable memory.£Y.,cles and only
the 4-cycle variable I/O cycle. The CE/WAIT line is
sampled at the falling edge of T2 for 3- or 4-cycle
memory cycles, and at the falling edge of T3 for 4cycle I/O cycles.
During transfers, data is latched on the clock edge
causing the rising edge of RD and held through the
end of the write cycle.
BUS REOUESTS
Figure 15 illustrates the bus request and acceptance timing. The ROY line, which may be programmed active High or low, is sampled on every
rising edge of ClK. If it is found to be active, and if
the bus is not in use by any other device, the following rising edge of ClK drives BUSREO low. After
receiving BUS REO the CPU acknowledges on the
BAI input either directly or through a mldlliQle-DMA
daisy chain. When a low is detect on BAI for two
consecutive rising edges of ClK, the DMA will begin
transferring data on the next rising edge of ClK.
BUS RELEASE BYTE-AT-A-TIME
In Byte-at-a-Time mode, BUSREO is brought High
on the rising edge of ClK prior to the end of each
read cycle (search-only) or write cycle (transfer and
transfer/search) as illustrated in figure 16. This is
done regardless of the state of ROY. There is no
possibility of confusion when a Z80 CPU is used
since the CPU cannot begin an operation until the
following T-cycle. Most other CPUs are not bothered
by this either, although note should be taken of it.
The next bus request for the next byte will come after
both BUS REO and BAI have returned High.
BUS RELEASE AT END OF BLOCK
In Burst and Continuous modes, an end of block
causes BUSREO to go High usually on the same
rising edge of ClK in which the DMA completes the
~ransfer of t~e data block (figure 17). The last byte
In the block IS transferred even if ROY goes inactive
before completion of the last byte transfer.
Figure 13: I/O-to-Memory Transfer.
I~'---IIOREAO - - - - 1 - Cut
'ORQ
READ
(
AD
OO-D7
I
"'\
I
I/O DRIVES DATA
_
WR
---- ---f---- f----
]}-
DMA DRIVES DATA 8US
"'
MREQ
WRITE (
II
II
II
I
L
L-r
f--f--
--- --tT It ---- ---1711 --.....,
13/22
165
Z8410
BUS RELEASE AND NOT READY
In Burst mode, when RDY goes inactive it causes
BUSREQ to go High on the next rising edge of CLK
after the completion of its current byte operation
(figure 18). The action on BUSREQ is thus somewhat delayed from action on the RDY line. The DMA
always completes its current byte operation in an orderly fashion before releasing the bus.
By contrast, BUSREQ is not released in Continuous
mode when RDY goes inactive. Instead, the DMA
idles after completing the current byte operation,
awaiting an active RDY again.
BUS RELEASE ON MATCH
If the DMA is programmed to stop on match in Burst
or Continuous modes, a match causes BUSREQ to
go inactive on the next DMA operation, i.e., at the
end of the next read in a search or at the end of the
following write in a transfer (figure 19). Due to the
Figure 14
Variable-Cycle and Edge Timing.
I
T,
T,
I
pipe lining scheme, matches are determined while
the next DMA read or write is being performed.
The RDY line can go inactive after the matching
operation begins without affecting this bus-release
timing.
INTERRUPTS
Timings for interrupt acknowledge and return from
interrupt are the same as timings for these in other
Z80 peripherals.
Interrupt on RDY (interrupt before requesting bus)
does not directly affect the BUSREQ line. Instead,
the interrupt service routine must handle this by issuing the following commands to WR6 :
1. Enable after Return From Interrupt (RETI)
Command - Hex B7
2. Enable DMA - Hex 87
3. A RETI instruction that reset the interrupt
Under Service latch in the Z80 DMA.
Figure 15 : Bus Request and Acceptance.
T.
eLK
CLK
Ao-A .. _-"'_ _ _ _~
IUIJiIlI .. __ ...J
IORO \ \ "_ _ _'iAI ..
_-_-_ -_ -_ -_ -...J.-+-....,1......1
Figure 16
Bus Release (Byte-at-a-Time-Mode).
Figure 17: Bus Release at End of Block (Burst
and Continuous Modes).
CLK~~
.u....
'
1 ....
, _ _ _ _- -
I
i"il
,r-------------!-i:
-r-I
f-'"'
OMA ACTIVE
14/22
166
DMA INACTIVE
ilusRiG
-----a. . --.J,.J
Z8410
Figure 18
Bus Release When Not Ready
(Burst Mode).
Figure 19: Bus Release on Match (Burst and
Continuous Modes).
ifu_1tD
L
[-
-- -
CURRENT IIYTE
OPER"'TI~
------~~--------.r_--~
r----Ni.:,~----'Ir--.- ·;::1~1
I "'.
M~~:.r~U:g
----lfliACTIYE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
TA
Operating Ambient Temperature Under Bias
T5t9
Storage Temperature
VI
Voltage on Any Pin with Respect to ground
Po
Power Dissipation
Value
Unit
- 65 to + 150
'C
As Specified Under
"Order Codes"
- 3 to + 7
V
1.5
W
Stresses greater then those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not im·
plied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (OV). Positive current flows into
the referenced pin. Available operating temperature
ranges are:
• 0 °C to + 70°C,
+ 4.75 Vs Vcc s+ 5.25 V
• - 40°C to + 85 °C,
+ 4.75 Vs Vcc S+ 5.25 V
• - 55°C to + 125°C,
+ 4.75 VsVcc S+ 5.25 V
+,.
2.tl<
All ac parameters assume a load capacitance of
100pF max. Timing references between two output
signals assume a load difference of 50pF max.
15/22
167
Z8410
DC CHARACTERISTICS
Min.
Max.
Unit
VllC
Clock Input Low Voltage
- 0.3
0.45
V
VIHC
Clock Input High Voltage
Vee - 0.6
5.5
V
- 0.3
O.S
V
2.0
5.5
V
0.4
V
Symbol
Vil
Test Conditions
Parameter
Input Low Voltage
VIH
Input High Voltage
Val
Output Low Voltage
10l ~ 3.2 mA for BUSREQ
10l ~ 3.2 mA for all others
VOH
Output High Voltage
10H ~- 250!lA
Icc
Power Supply Current
ZS41 0 Z80 DMA
ZS41 OA ZSOA DMA
2.4
V
150
200
III
Input Leakage Current
VIN ~ 0 to Vee
Ilo
3-State Output Leakage Current in Float
VOUT
Ilo
Data Bus Leakage Current in Input Mode
mA
mA
10
f.lA
-10
10
!lA
0" VIN " Vec
-10
10
!lA
Test Conditions
Min.
Max.
Unit
~
0.4 to Vee
CAPACITANCE
Symbol
Parameter
C
Clock Capacitance
Unmeasured Pins
CIN
Input Capacitance
Returned to Ground
COUT
Output Capacitance
Over specified temperature range; f
16/22
168
=t
MHz.
35
pF
5
pF
10
pF
Z8410
INACTIVE STATE AC CHARACTERISTICS
N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Symbol
Parameter
TcC
Clock Cycle Time
TwCh
Clock Width (high)
TwCI
Clock Width (low)
TrC
Clock Rise Time
TfC
Clock Fall Time
Th
Hold Time for any Specified Setup Time
TsC(Cr)
IORO, ER, CE
J-
J-
to Clock
i Setup
TdDO(RDf)
RD
TsWM(Cr)
Data in to Clock
TdCf(DO)
J- to Data Out Delay (INTA cycle)
i to Data Float Delay (output buffer disable)
lEI J- to IORO J- Setup (INTA cycle)
lEI i to lEO i Delay
lEI J- to lEO J- Delay
MI J- to lEO J- Delay (interrupt just prior to MI J-)
MI J- to Clock i Setup
MI i to Clock J- Setup
RD J- to Clock i Setup (MI cycle)
Interrupt Cause to INT J- Delay (I NT generated
TdRD(Dz)
TsIEI(IORO)
TdIEOr(IElr)
TdIEO(lElf)
TdMI(IEO)
TsMlf(Cr)
TsMlr(Cf)
TsRD(Cr)
Tdl(INT)
Z8410
Max.
(ns)
Min.
(ns)
Max.
(ns)
400
170
170
4000
2000
2000
30
30
250
110
110
4000
2000
2000
30
30
0
280
0
145
500
to Data Output Delay
i Setup (WR or MI)
Z8410A
Min.
(ns)
380
50
50
340
160
IORO
RD
140
160
110
140
210
190
300
210
20
240
160
130
190
90
-10
115
500
500
200
200
150
150
only when DMA is inactive)
20 TdBAlr(BAOr)
21 TdBAIf(BAOf)
22 TsRDY(Cr)
i Delay
J- Delay
RDY Active to Clock i Set up
BAI
BAI
i
J-
to BAO
to BAO
150
100
Note: 1. Negative minimum setup values mean that the first mentioned event can come after the second mentioned event.
17/22
169
Z8410
INACTIVE STATE CHARACTERISTICS (continued).
-,-
.zv
QlflPUl
INPUT
l.GV
2.0'1
"0·
D.IV
0.'"
0.'"
Do-DT
INTERRUPT
CONDITIOIII _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- "
@
18/22
170
Z8410
ACTIVE STATE AC CHARACTERISTICS
N°
Symbol
1
TcC
Z8410
Parameter
Z8410A
Min.
Max.
Min.
Max.
(ns)
(ns)
(ns)
(ns)
Clock Cycle Time
400
250
2
TwCh
Clock Width (high)
180
2000
110
2000
3
TwCI
Clock Width (low)
180
2000
110
2000
4
TrC
Clock Rise Time
30
5
TIC
Clock Fall Time
30
30
6
TdA
Address Output Delay
145
110
7
TdC(Az)
8
TsA(MREO)
9
TsA(IRW)
Address Stable to 10RO, RD, WR
(1/0 cycle)
Clock j to Address Float Delay
J-
Address to MREO
30
110
Setup (memory cycle)
J-
Setup
90
(2)+(5)-75
(2)+(5)-75
(1)-80
(1)-70
'10
TdRW(A)
RD, WR j to Addr. Stable Delay
(3)+(4)-40
(3)+(4)-50
'II
TdRW(Az)
RD, WR j to Addr. Float
(3)+(4)-60
(3)+(4)-45
12
TdCf(DO)
Clock
J-
to data Out Delay
'13
TdCr(Dz)
Clock
l'
to Data Float Delay (write cycle)
14
TsDI(Cr)
Data in to Clock j Setup
(read cycle when rising edge ends read)
50
35
15
TsDI(Cf)
Data in to Clock J- Setup
(read cycle when falling edge ends read)
60
50
'16
TsDO(WfM)
Data out to WR
(1)-210
(1)-170
17
TsDO(Wfl)
Data Out to WR
'18
TdWr(DO)
WR j to Data Out Delay
J- Setup (memory cycle)
J- Setup (1/0 cycle)
230
9
150
90
90
100
100
(3)+(4)-80
(3)+(4)-70
19
Th
20
TdCr(Mf)
Clock
Delay
100
85
21
TdCf(Mr)
Clock j to MREO j Delay
100
85
22
TdCr(Mr)
Clock
to MREO j Delay
100
85
23
TdCf(Mr)
Clock
to MREO j Delay
100
24
TwMI
Hold Time for Any Specified Setup Time
JJJ-
to MREO
J-
0
MREO Low Pulse Width
(1)-40
MREO High Pulse Width
(2)+(5)-30
'25
TwMh
26
TdCf(lf)
Clock
27
TdCr(lf)
Clock j to 10RO
28
TdCr(lr)
Clock
l'
'29
TdCf(lr)
Clock
J-
J-
to 10RO
JJ-
0
85
(1)-30
(2)+(5)-20
Delay
110
Delay
90
75
to 10RO j Delay
100
85
to 10RO j Delay
110
Noles: 1. Numbers In parentheses are other parameter-numbers In this table; their values should be substituted
85
85
In
equations.
2. All equations imply DMA default (standard) timing.
3 Data must be enabled into data bus when RD is active.
4. Asterisk (') before parameter number means the parameter is not illustrated in the AC Timing Diagrams.
19/22
171
Z8410
ACTIVE STATE AC CHARACTERISTICS (continued)
..
Z8410 ..
Z8410A
---
N°
Symbol
30
TdCr(Rf)
Clock
'I to RD J, Delay
100
85
31
TdCf(Rf)
Clock J, to 'RD J, Delay
130
95
32
TdCr(Rr)
Clock
100
85
33
TdCf(Rr)
110
85
34
TdCr(Wf)
'I to RD J, Delay
Clock J- to RD 'I Delay
Clock 'I to W~ 1 Delay
35
TdCf(Wf)
Clock
J-
36
TdCr(Wr)
Clock
'I to WR
37
TdCf(Wr)
38
Parameter
TwWI
- - f---
Max.
(ns)
Min.
(ns)
65
Delay
90
80
Delay
100
80
CI.~ck J, to WR -' Delay
100
80
to WR
JJ-
WR Low Pulse Width
41
TdCr(lz)
Clock
'''~'=-
(1)-30
..
(1)-40
40
..:
70
70
150
-..-r--.
WR
Float Delay
100
.. _ - - - - ........_.... _._ ...........
_-_ __
'I to IORO, MREQ, RD,
--1 - . _ 100
--1 - - -
.....- -..........
..._..
Notes: 1. Numbers in parentheses are other parameter·numbers In this table; their values should be substituted in equations.
~--
2.
3.
4.
20/22
172
All equations imply DMA de!Rult (standard) ti[]1ing.
Data must be enabled Into data bus when RD is active.
Asterisk
before parameter number means the parameter is not illustrated in the AC Timing Diagrams.
n
Max.
(ns)
80
TsWA(Cf)JlAiTto
Clock J- Setup
..
: . _ ' - - - - - - = _....
TdCr(8)
Clock t to 8USREO Delay
39
Min.
(ns)
80. . . -
Z8410
ACTIVE STATE AC CHARACTERISTICS (continued).
eLK
Do-oj
,.PUT
-l---+~~---H---+--+-h. .1.-1----+-+++---",
lovw.T __
-+~~
__
~~
________44________+-____
~J~+-
____
~
__
~-+--J
wi
WR
BUSAEQ
_K
---------------------------------------------~j~,?-------. _ - - - - - - - - - - ...----_._----_.--------------------------'
21/22
173
Z8410
ORDERING INFORMATION
Type
Package
Temp.
Clock
Z8410Bl
Z8410F1
Z8410D1
Z8410D6
Z8410D2
Z8410C1
DIP-40 (plastic)
DIP-40 (trit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
- 55/ + 125°C
01 + 70°C
2.5 MHz
Z8410AB1
Z8410AF1
Z8410AD1
Z8410AD6
Z8410AD2
Z8410AC1
DIP-40 (plastic)
DIP-40 (trit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
- 55/ + 125°C
0/+ 70°C
4 MHz
22/22
174
Description
Z80 Direct
Memory Access
Unit
Z8420
zao PIO PARALLEL INPUT/OUTPUT CONTROLLER
• PROVIDES A DIRECT INTERFACE BETWEEN
MICROCOMPUTER SYSTEMS AND PERIPHERAL DEVICES
• BOTH PORTS HAVE INTERRUPT-DRIVEN
HANDSHAKE FOR FAST RESPONSE
PROGRAMMABLE
OPERATING
• FOUR
MODES: BYTE INPUT, BYTE OUTPUT, BYTE
INPUT/OUTPUT (Port A only), AND BIT
INPUT/OUTPUT
• PROGRAMMABLE INTERRUPTS ON PERIPHERAL STATUS CONDITIONS
FAMILY BUS-REQUEST AND
• STANDARD
PRIORITIZED INTERRUPT-REQUEST DAISY
CHAINS IMPLEMENTED WITHOUT EXTERNALLOGIC
• THE EIGHT PORT B OUTPUTS CAN DRIVE
DARLINGTON TRANSISTORS (1.5 mA at
1.5 V)
zao
B/F
DIP-40
(Plastic and Frit Seal)
0
DIP-40
(Ceramic)
zao
C
PLCC44
(Plastic)
(Ordering Information at the end of the datasheet)
DESCRIPTION
zao
The
PIO Parallel I/O Circuit is a programmable,
dual-port device that provides a TTL'compatible interface between peripheral devices and the
CPU. The CPU configures the
PIO to interface
with a wide range of peripheral devices with no other
external logic. Typical peripheral devices that are
compatible with the
PIO include most keyboards, paper tape readers and punches, printers,
PROM programmers, etc.
zao
zao
LOGIC FUNCTIONS
zao
zao
One characteristic of the
peripheral controllers
that separates them from other interface controllers
is that all data transfer between the peripheral device and the CPU is accomplished under interrupt
control. Thus, the interrupt logic of the PIO permits
full use of the efficient interrupt capabilities of the
CPU during I/O transfers. All logic necessary to
implement a fully nested interrupt structure is included in the PIO.
zao
Another feature of the PIO is the ability to interrupt
the CPU upon occurrence of specified status conditions in the peripheral device. For example, the PIO
can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the time the processor must
spend in polling peripheral status.
m.{
Bue
PORTA
-{
COIrITROL
!'ORT 8
INTBRRUPT {
CONTROL
lEO
zao
The
PIO interfaces to peripherals via two independent general-purpose I/O ports, designated port
September 1988
1/15
175
Z8420
Figure 1 : Dual in Line Pin Configuration.
,.------_._-_._-------.,
(mode 1), byte input/output (mode 2) and bit
input/output (mode 3).
In mode 0, either port A or port B can be prog rammed to output data. Both ports have output registers that are individually addressed by the CPU;
data can be written to either port at any time. When
data is written to a port, an active Ready output indicates to the extemal device that data is available
at the associated port and is ready for transfer to the
external device. After the data transfer, the external
device responds with an active Strobe input, which
generates an interrupt, if enabled.
''""
'"
C"E
"'.
BIA
.
A,
In mode 1, either port A or port B can be configured
in the input mode. Each port has an input register
addressed by the CPU. When the CPU reads data
from a port. the PIO sets the Ready signal, which is
detected by the external device. The external device
then places data on the 1/0 lines and strobes the I/O
port, which latches the data into the Port Input Register, resets Ready, and triggers tile Interrupt Request, if enabled. The CPU can read the input data
at any time, which again sets Ready.
Figure 2 : Chip Carrier pin Configuration.
6
5
4
3
2
I
41. 43 42 .. 1 .. 0
BIA
39
Ro
A1
AS
38
87
37
96
AS
10
36
B&
A4
11
3S
84
Z8420
N.C.
12
J4
83
GNO
13
33
B2
AJ
1.1,
32
9\
AZ
15
31
Bo
A,
16
30
Vee
AO
1?
29
elK
16
19
20
21
22
l
iJ 24 25
16 21
28
wwuwcr
5-6099
I.... -
en \'" > 0 - . .
. 0
l-,...ocao~4t.&.1zl.1J
""
I/)
0::
IX: .z z
_ ..........
C
to
0 INTERRUPT ON OR FUNCTION
D8 "" 1 INTERRUPT ON AND FUNCTION
'-------- :; :~ ::~:::~;~ ~~s::t.~~*
-NOTE: THE PORT IS NOT ENABLED UNTil
THE INTERRUPT ENABLE J5 FOLLOWED
BY AN ACTIVE M1.
INTERRUPT CONTROL WORD. In mode 3, handshake is not used. Interrupts are generated as a
logic function of the input signal levels. The interrupt
control word sets the logic conditions and the logic
levels required for generating an interrupt. Two logic
conditions or functions are available: AND (if all
input bits change to the active level, an interrupt is
triggered), and OR (if anyone of the input bits
changes to the active level, an interrupt is triggered).
Bit D6 sets the logic function, as shown in figure 8.
The active level of the input bits can be set either
High or Low. The active level is controlled by bit D5.
Figure 9 : Mask Control Word.
1071 0.1 Os I0.1 0, 10,1 011 Dol
I
MBo-MB7 MASK BITS. A
BIT IS MONITORED FOR AN
' - - - - - - INTERRUPT IF IT 15
DEFINED AS AN INPUT AND
THE MASK BIT IS SET TO O.
MASK CONTROL WORD. This word sets the mask
control register, allowing any unused bits to be
masked off. If any bits are to be masked, then D4
must be set. When D4 is set, the next word written
to the port must be a mask control word (figure 9).
INTERRUPT DISABLE
There is one other control word which can be used
to enable or disable a port interrupt. It can be used
without changing the rest of the interrupt control
word (figure 10).
Figure 10 : Interrupt Disable Word.
1L
10do.ID,ID.1 0I 01 111 I
L
IDENTIFIES INTERRUPT
DISABLE WORD
DON'T CARE
07 - 0 INTERRUPT DISABLE
1 INTERRUPT ENABLE
Dr
=
5/15
179
Z8420
PIN DESCRIPTIONS
Ao-A7. Port A Bus (Bidirectional, 3-state). This a-bit
bus transfers data, status, or control information between port A of the PIO and a peripheral device. Ao
is the least significant bit of the port A data bus.
ARDY. Register A Ready (Output, Active High). The
meaning of this signal depends on the mode of operation selected for port A as follows:
OUTPUT MODE. This signal goes active to indicate
that the port A output register has been ,loaded and
the peripheral data bus is stable and ready for transfer to the peripheral device.
INPUT MODE. This signal is active when the port A
input register is empty and ready to accept data from
the peripheral device.
BIDIRECTIONAL MODE. This signal is active when
data is available in the port A output register for
transfer to the peripheral device. In this mode, data
is not placed on the port A data bus, unless ASTB
is active.
CONTROL MODE. This signal is disabled and
forced to a low state.
ASTB. Port A Strobe Pulse From Peripheral Device
(Input, Active~ow). The meaning of this signal depends on the mode of operation selected for port A
as follows:
OUTPUT MODE. The positive edge of this strobe is
issued by the peripheral to acknowledge the receipt
of data made available by the PIO.
INPUT MODE. The strobe is issued by the peripheral to load data from the peripheral into the port A
input register. Data is loaded into the PIO when this
signal is active.
BIDIRECTIONAL MODE. When this signal is active,
data from the Port A output register is gated into the
port A bidirectional data bus. The positive edge of
the strobe acknowledges the receipt of the data.
CONTROL MODE. The strobe is inhibited intemally.
Bo-B7. Port B Bus (Bidirectional, 3-state). This a-bit
bus transfers data, status, or control information between port B and a peripheral device. The port B
data bus can supply 1.5 mA at 1.5 V to drive Darlington transistors. Bo is the least significant bit of
the bus.
B/A. Port B Or A Select (Input, High = B). This pin
defines which port is accessed during a data transfer between the CPU and the PIO. A Iowan this pin
selects port A ; a High selects port B. Often address
6/15
lao
bit Ao from the CPU is used for this selection function.
BRDY. RegisterB Ready(Output, Active High). This
signal is similar to AROY, except that in the port A
bidirectional mode this signal is High when the port
A input register is empty and ready to accept data
from the peripheral device.
BSTB. Port B Strobe Pulse From Peripheral Device
(Input, Active low). This signal is similar to ASTB,
except that in the port A bidirectional mode this signal strobes data from the peripheral device into the
pol! A input register.
C/O. Control Or Data Select (Input, High = C). This
pin defines the type of data transfer to be performed
between the CPU and the PIO. A High on this pin
during a CPU write to the PIO causes the zao data
bus to be interpleted as a command for the port selected by the B/A Select line. A Iowan this pin means
that the zao data bus is being used to transfer data
between the CPU and the PIO. Often address bit A1
from the CPU is used for this function.
CEo Chip Enable (Input, Active low). A Iowan this
pin enables the PIO to accept command or data inputs from the CPU during a write cycle or to transmit data to the CPU during a read cycle. This signal
is generally decoded from four I/O port numbers for
ports A and B, data, and control.
elK. System Clock (Input). The zao PIO uses the
standard single-phase zao system clock.
00-07. Z80 CPU Data Bus (Bidirectional, 3-state).
This bus is used to transfer all data and commands
between the zao CPU and the zao PIO. Do is the
least significant bit.
lEI. Interrupt Enable In (Input, Active High). This signal is used to form a priority-interrupt daisy chain
when more than one interrupt-driven device is being
used. A High level on this pin indicates that no other
devices of higher priority are being serviced by a
CPU interrupt service routine.
lEO. Interrupt Enable Out (Output, Active High). The
lEO signal is the other signal required to form a daisy
chain priority scheme. It is High only if lEI is High
and the CPU is not servicing an interrupt from this
PIO. Thus this signal blocks lower priority devices
from interrupting while a higher priority device is
being serviced by its CPU interrupt service routine.
INT. InterruRt Request (Output, Open Drain, Active
low). When INT is active the zao PIO is requesting
an interrupt from the zao CPU.
Z8420
lORa. Input/Output Request (Input from Z80 CP!:,!,
AcJlv~ow).
10RO is used in conjunction with B/A,
C/D, CE, and RD to transfer commands and data
between the Z80 CPU and the Z80 Pia. When Cf;,
RD, and 10RO are active, the port addressed by B/A
transfers data to the CPU (a read operation).
Conversely, when CE and 10R.Q are active but RD
is not, the port addressed by B/A is written into from
the CPU with e..l!her data or control information, as
specified by C/D.
Also, if 10RO and M1 are active simultaneously, the
CPU is acknowledging an interrupt; the interrupting
port automatically places its interrupt vector on the
CPU data bus if it is the highest priority device requesting an interrupt.
M1. Machine Cycle (Input from CPU, Active low).
This signal is used as a sync pulse to contfQLseveral internal Pia operations. When both the M1 and
RD signals are active, the Z80 CPU is fetching an
instruction from memory. Conversely, when both
M1 and 10RO are activeJb..e CPU is acknowledging
an interrupt. In addition, M1 has two other functions
within the Z80 P!Q..: it synchronizes the PIOl!:!1errupt logic; when M1 occurs without an active RD or
10RO signal, the Pia is reset.
RD. Read C~ Status (Input from Z80 CPU, Active low).JLRD is active, or_an 1@QP.eration is in
progress, RD is used with B/A, C/D, CE, and 10RO
to transfer data from the Z80 Pia to the Z80 CPU.
TIMING
The following timing diagrams show typical timing in
a Z80 CPU environment. For more precise specifications refer to the composite ac timing diagram.
WRITE CYCLE
Figure 11 illustrates the timing for programming the
Z80 Pia or for writing data to one of its ports. No
Wait states are allowed for writing to the Pia other
than the automatically inserted TWA. The Pia does
not receive a specific write signal ; it internally generates its own from the lack of an active RD signal.
READ CYCLE
Figure 12 illustrates the timing for reading the data
input from an external device to one of the Z80 Pia
ports. No Wait states are allowed for reading the Pia
other than the automatically inserted TWA.
OUTPUT MODE (mode 0)
An output cycle (figure 13) is always started by the
execution of an output instruction by the CPU. The
WR* pulse from the CPU latches the data from the
CPU data bus into the selected port's output register. The WR* pulse sets the Ready flag after a lowgoing edge of ClK, indicating data is available.
Ready stays active until the positive edge of the
strobe line is received, indicating that data was
taken by the peripheral. The positive edge of the
strobe pulse generates an INT if the interrupt enable
flip-flop has been set and if this device has the highest priority.
INPUT MODE (mode 1)
When STROBE goes low, data is loaded into the
selected port input register (fme 14). The next rising edge of strobe activates INT, if Interrupt Enable
is set and this is the highest-priority requesting device. The following falling edge of ClK resets Ready
to an inactive state, indicating that the input register
is full and cannot accept any more data until the CPU
completes a reaLWhen a read is complete, the
positive edge of RD sets Ready at the next lowgoing transition of ClK. At this time new data can
be loaded into the Pia.
BIDIRECTIONAL MODE (mode 2)
This is a combination of Modes 0 and 1 using all four
handshake lines and the eight Port A I/O lines (figure
15). Port B must be set to the bit mode and its inputs must be masked. The Port A handshake lines
are used for output control and the Port B lines are
used for input control. If interrupts occur, Port A's
vector will be used during port output and Port B's
will be used during port input. Data is allowed out
onto the Port A bus only when ASTB is low. The
rising edge of this strobe can be used to latch the
data into the peripheral.
BIT MODE (mode 3)
The bit mode does not utilize the handshake signals,
and a normal port write or port read can be executed
at any time. When writing, the data is latched into
the output registers with the same timing as the output mode (figure 16).
When reading the Pia, the data returned to the CPU
is composed of output register data from those port
data lines assigned as outputs and input register
data from those port data lines assigned as inputs.
The input register contains data that was present
immediately prior to the falling edge of RD. An interrupt is generated if interrupts from the port are enabled and the data on the port data lines satisfy the
logical equation defined by the 8-bit mask and 2-bit
mask control registers. However, if Port A is programmed in bidirectional mode, Port B does not
issue an interrupt in bit mode and must therefore be
polled.
7/15
181
Z8420
Figure 11 : Write Cycle Timing.
Figure 12 : Read Cycle Timing.
TI
~
~
~
T1
eLK
em, .,i
J"--______><==
elti,BlA
::x________x=
;\\-----';\'-----';-
Ce ~L_ _ _ _ _ _ _ __ J
\'-__.....1;-DATA
--'X
___
IN
x:=
\~____~;---
WR'
'WR : RD.
Figure 13: Mode
CE' Cii'i • IORQ
.ATA
RD'
-------«(...-_-_-;.~::_=_'...J>;OUT
\ ..._ _ _ _...J
'Ro = Ro • CE • Ci5 • IORO
a Output Timing.
eLk
PORT
OUTPUT ----,\---+-----4---!~
READY _ _ _ _ _ _- - f
INTERRUPT ACKNOWLEDGE TIMING
During M1 time, peripheral controllers are inhibited
from changing their interrupt enable status, permitting the Interrupt Enable signal to ripple through the
daisy chain. The peripheral with lEI High and lEO
Low during INTACK places a preprogrammed 8-bit
interrupt vector on the data bus at this time (figure 17). lEO is held Low until a Return From Interrupt
(RETI) instruction is executed by the CPU while lEI
is High. The 2-byte RETI instruction is decoded internally by the PIO for this purpose.
RETURN FROM INTERRUPT CYCLE
If a Z80 peripheral has no interrupt pending and is
not under service, then its lEO = lEI. If it has an interrupt under service (i.e., it has already interrupted
and received an interrupt acknowledge) then its lEO
8/15
182
is always Low, inhibiting lower priority devices from
interrupting. If it has an interrupt pending which has
not yet been acknowledged, lEO is Low unless an
"ED" is decoded as the first byte of a 2-byte opcode
(figure 18). In this case, lEO goes High until the next
opcode byte is decoded, where upon it goes Low
again. If the second byte of the opcode was a "40",
then the opcode was an RETI instruction.
After an "ED" opcode is decoded, only the peripheral device which has interrupted and is currently
under service has its lEI High and its lEO Low. This
device is the highest-priority device in the daisy
chain that has received an interrupt acknowledge.
All other peripherals have lEI = lEO. If the next opcode byte decoded is "40", this peripheral device
resets its "interrupt under service" condition.
Z8420
Figure 14 : Mode 1 Input Timing.
'RD
= RD. CE. C/D .rORQ
Figure 15 : Mode 2 Bidirectional Timing.
CLIl
ARDY
PORTA
DATA BUS
_________________________
-
-<==~~~~----------~
.RDY
• WR
=
RO • CE • C/O, IORQ
Figure 16 : Mode 3 Bit Mode Timing.
elK
PORT
DA.TA BUS
X
X
DATA WORD 1
DATA WORD 2
X'-____________
ATA MAtH\'--------+-1t,/
-D---J
OCCURS HERE-
IORQ
.•
----~__J;,-----( DATA IN )
tOATA WORD 1 PLACED ON BUS
9/15
183
Z8420
Figure 17 : Interrupt Acknowledge Timing.
~..ll
f,
I I I I I
t,
f..
T..
T.
•
L-________________________________________________________
Figure 18 : Return From Interrupt.
To
T,
T,
T,
T,
T.
T,
T,
To
C~K
\
/
I
,. iii ~
I
'---./
Do-D, ------IQ0
G:)
- - - - - -,1'------------.1. -______
-'
M1
\
--------------------~/
10/15
184
~
Z8420
AC CHARACTERISTICS
N°
Symbol
Parameter
Comment
Z8420
Z8420A
Z8420B
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
165
r--(2L
2
TwCh
Clock Width (high)
170 2000 105 2000
65
2000
3
c--.
TwCI
Clock Width (low)
2000
170 2000 105
..
65
2000
1
4
TcC
.-.
---.----TfC
5
Tre
6
TsCS(RI)
"1
Th
Clock Cycle Time
...
_--
-
__Fall Time
. Clock
---~--
TsRI(C)
9
TdRI(OO)
10
TdRI(DOs)
11
TsDI(C)
12
TdIO(DOI)
13
TsMI(Cr)
14
TsMI(Cf)
15
TdMI(IEO)
16
TsIEI(IO)
17
TdIEI(IEOf)
- - -.. -
._-----
30
Clock Rise Time
30
---_.
C~,
B/A, C/O to HO,
lORa 1 Setup Time
(6)
RO, lORa to Clock
t
Data in to Clock
TdIEI(IEOr)
19
TclO(C)
20
TdC(RDYr)
--
MI 1. to Clock t
MI 1 to Clock
cycle)
t
CL = 50 pF
Setup Time
Setup Time
.
1 setup Time (MI
(8)
TdC(RDYf)
22
TwSTB
lEI to 'ORO
cycle)
t
Setup Time (INTACK
(7)
1 to lEO 1 Delay
lEI l' to lEO
ED decode)
23
TsSTB(C)
Noles:
0
0
t
Delay (after
160
110
50
300
70
40
120
160
210
90
70
0
0
0
190
300
140
140
100
100
(5)
50 pF
190
130
120
(5)
210
160
160
(5)
50 pF
170
200
220
1 to READY t Delay
1 to READY 1 Delay
380
340
0
70
115
430
50
I---
=
IORO 1 to Clock 1 Setup Time (to
activate READY on next clock cycle)
Clock
0
(5,7)
CL
21
20
30
50
(3)
MI t to lEO t Delay (i~rrupt
immediately preceding Mil)
Clock
20
30
50
(2)
1. to Data Out Delay (INTACK
f-=----......
lEI
-
(1)
50
115
Setup Time
1 to Data Out Delay
RD, lORa l' to Data Out Float Delay
RD, lORa
lORa
cycle)
250
_._--------_.
Any Hold Times for Specified Setup
Time
CL
18
(1)
..
' - - - - - - -.•.
8
400
---
170
190
200
=
(5)
120
140
150
STROBE Pulse Width
(4)
150
150
120
STROBE'l to Clock 1 Setup Time
(to activate READY on next clock
cycle)
(5)
220
220
150
1 TcC = TwCh + TwCl + TrC + TfC.
Increase TdRi(DO) by IOns for each 50 pF increase in load up to 200 pF max
Increase TdIO(DO) by IOns for each 50 pF increase in loading up to 200 pF max.
For Mode 2 TwSTB > TsPD{STB).
Increase these values by 2 ns for each 10 pF increase in loading up to 100 pF max.
TsCS(RI) may be reduced. However the time subtracted from TsCS(RI) may be added to TdRI(DO).
2.5 TdC > (N·2)TdIEI(lEOf) + TdMI(IEO) + TsIEI(IO) + TTL Buffer Delay if any.
Ml must be active for a minimum of two clock cycles to reset the PIO.
2
3
4
5
6
7
8
11/15
185
Z8420
AC CHARACTERISTICS (continued)
Parameter
Comment
Z8420
Z8420A
Z8420B
N°
Symbol
24
TdlO(PD)
lORa l' to PORT DATA Stable
Delay (mode 0)
25
tsPD(STB)
PORT DATA to STROBE
Time (mode 1)
26
TdSTB(PD)
STROBE J, to PORT DATA Stable
(mode 2)
(5)
230
210
180
27
TdSTB(PDr)
STROBE l' to PORT DATA Float
Delay (mode 2)
CL = 50 pF
200
180
160
28
TdPD(INT)
PORT DATA Match to INT J, Delay
(mode 3)
540
490
430
29
TdSTB(INT)
STROBE
l' to INT l' Delay
490
440
350
Notes:
12/15
186
1
2
3
4
5
6
7
8
nc.
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
(5)
l' Setup
200
260
180
230
TcC = TwCh + TwC1 + TrC +
Increase TdRi(DO) by 10 ns for each 50 pF increase in load up to 200 pF max.
Increase TdIO(DO) by 10 ns for each 50 pF increase in loading up to 200 pF max.
For Mode 2 TwSTB > TsPD(STB).
Increase these values by 2 ns for each 10 pF increase in loading up to 100 pF max.
TsCS(RI) may be reduced. However the time subtracted from TsCS(RI) may be added to TdRI(DO).
2.5 TdC > (N-2)TdIEI(IEOf) + TdMI(IEO) + TsIEI(IO) + TTL Buffer Delay if any.
M1 must be active for a minimum of two clock cycles to reset the PIO.
160
190
Z8420
I).C CHARACTERISTICS (continued)
CLOCK
..._D7joUT
IN
----+------u--+----:....-~r-++---+--
------------+-~--Jl~--~~----------------~_+~--------+_-----------
III
_..
IAllDY\!)W'''D'(1
MODE 0
MODE'
MODEl
MO'"
13/15
187
------.-------
Z8420
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
V,
Voltage on all Input and Outputs with Respect to GND
TA
Operation Ambient Temperature
T stg
Storage Temperature Range
Value
Unit
- 0.3 to + 7.0
V
- 65 to + 150
'c
As Specified in Order Codes
Stresses greater than those listed under Absolute MaXimum Ratings may cause permanent damage to the deVice. This IS a stress
rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (0 V). Positive current flows into
the referenced pin. Available operating temperature
ranges are:
• 0 'e to + 70 'e,
All ac parameters assume a load capacitance of
100pF max.
.,.
<1'
+4.75Vs Vcc s+5.25V
• - 40 'e to + 85 'e,
+ 4.75 V s vee s + 5.25 V
• -55'eto+125'e,
+ 4.75 V s vee s + 5.25 V
DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
- 0.3
0.45
V
V'Le
Clock Input Low Voltage
V'HG
Clock Input High Voltage
V,L
Input Low Voltage
- 0.3
0.8
V,H
Input High Voltage
2.0
Vee
V
VOL
Output Low Voltage
-
0.4
V
VOH
Vee - 0.6 Vcc+0.3
1m ~ 2.0 mA
V
V
Output High Voltage
10H ~ - 250 ~lA
2.4
-
V
III
Input Leakage Current
V,N=OtoVce
-10
10
llA
ILO
3-State Output Leakage Current in Float
VOUT ~ 0.4 V to Vee
- 10
10
~A
Icc
Power Supply Current
VOH=1.5V
Darlington Drive Current
REXT ~ 390 Q
10HD
.
--
100
mA
- 1.5
3.8
mA
Min.
Max.
Unit
Over specified temperature and voltage range.
CAPACITANCE
Symbol
Parameter
C
Clock Capacitance
C 'N
Input Capacitance
COUT
Output Capacitance
Over specified temperature range; f
14/15
188
Test Conditions
Unmeasured pins returned
to ground.
=
1 MHz.
10
pF
5
pF
10
pF
Z8420
ORDERING INFORMATION
Type
Package
Temp.
Clock
Z8420B1
Z8420F1
Z842001
Z842006
Z842002
Z8420C1
Dlp·40 (plastic)
DIP·40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
-55/+ 125°C
0/+ 70°C
2.5 MHz
Z8420AB1
Z8420AF1
Z8420A01
Z8420A06
Z8420A02
Z8420AC1
DIP-40 (plastic)
DIP-40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
-55/+125°C
0/+ 70°C
4 MHz
Z8420BB1
Z8420BF1
Z8420B01
Z8420B06
Z8420B02
Z8420BC1
DIP-40 (plastic)
DIP-40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
- 40/ + 85°C
- 55/+ 125°C
0/+ 70°C
6 MHz
Description
Z80 Parallel
Input/Output Unit
15/15
189
Z8430
Z80 CTC COUNTER TIMER CIRCUIT
• FOUR INDEPENDENTLY PROGRAMMABLE
COUNTERITIMER CHANNELS, EACH WITH A
READABLE DOWNCOUNTER AND A SELECTABLE 16 OR 256 PRESCALER. DOWNCOUNTERS
ARE
RELOADED
AUTOMATICALLY AT ZERO COUNT
• THREE CHANNELS HAVE ZERO COUNTITIMEOUT OUTPUTS CAPABLE OF DRIVING
DARLINGTON TRANSISTORS
• SELECTABLE POSITIVE OR NEGATIVE TRIGGER INITIATES TIMER OPERATION
• STANDARD zao FAMILY DAISY-CHAIN INTERRUPT STRUCTURE PROVIDES FULLY
VECTORED, PRIORITIZED INTERRUPTS
WITHOUT EXTERNAL LOGIC. THE CTC MAY
ALSO BE USED AS AN INTERRUPT CONTROLLER
• INTERFACE DIRECTLY TO THE zao CPU ORFOR BAUD RATE GENERATION - TO THE
zao SIO
o
B/F
DIP-28
Dlp·28
(Plastic and Frit Seal)
(Ceramic)
(;)
C
PLCC44
(Plastic)
(Ordering Information at the end of the datasheet)
DESCRIPTION
The zao CTC four-channel counter/timer can be
programmed by system software for a broad range
of counting and timing applications. The four independently programmable channels of the zao CTC
satisfy common microcomputer system requirements for event counting, interrupt and interval timing, and general clock rate generation.
System design is simplified because the CTC connects directly to both the zao CPU and the zao SIO
with no additional logic. In larger systems, address
decoders and buffers may be required.
Programming the CTC is straightforward : each
channel is programmed with two bytes ; a third is
necessary when interrupts are enabled. Once
started, the CTC counts down, reloads its time constant automatically, and resumes counting. Software timing loops are completely eliminated.
Interrupt processing is simplified because only one
vector need be specified; the CTC internally generates a unique vector for each channel.
The zao CTC requires a single + 5V power supply
and the standard zao single-phase system clock. It
is fabricated with n-channel silicon-gate depletionload technology, and packaged in a 2a-pin plastic
or ceramic DIP.
September 1988
LOGIC FUNCTIONS
0,
CUUTRGo
0,
lCfTOo
0,
CPU
DATA
BUS
ClKfTRG,
zetTo,
i
CHANNEL
SIGNALS
0,
CLKfTRG2
CONT~~~ == ~;
PROM
CPU
ii1
___ IORO
RO
DAISY {
lEI
I"T£~::~~
lEO
CONTROL
INT
Z8430
r
t t
cue: Voc GNO
1/14
191
Z8430
Figure 1 : Dual in Line Pin Configuration.
0,
DJ
0,
D2
O.
0,
0,
Do
Vee
GND
RD
ClKITRGo
ZClTo"
ClKITRG,
ZCITO,
ClKITRG2
ZClT02
ClKITRGJ
IORO
CS,
lEO
CSg
INT
RESET
lEI
CE
Ml
ClK
During operation, the individual counter channel
counts down from the preset time constant value. In
counter mode operation the counter decrements on
each of the CLKlTRG input pulses until zero count
is reached. Each decrement is synchronized by the
system clock. For counts greater than 256, more
than one counter can be cascaded. At zero count,
the down-counter is automatically reset with the time
constant value.
The timer mode determines time intervals as small
as 4 fis (Z80A) or 6.4 fis (Z80) without additional
logic or software timing loops. Time intervals are
generated by dividing the system clock with a prescaler that decrements a preset down-cou nter.
Thus, the time interval is an integral multiple of the
clock period, the prescaler value (16 or 256) and the
time constant that is preset in the down-counter. A
timer is triggered automatically when its time constant value is programmed, or by an external
CLKlTRG input.
Figure 2 : Chip-Carrier Pin Configuration.
6
I)
I,
J
1
I
1,4
.(,J 42
41
40
)9
GNO
H.C.
B
00
zenoo
10
N.C.
11
lenO I
12
ZCIT02
iORQ
N.C
lB
N.C.
17
Vee
36
N.C.
35
ClKITAGO
JIo
N.c.
1J
])
eLK/TRG,
110
J2
ClKIlRG Z
N..C.
15
]1
CLKITRG J
lEO
16
)0
N.c.
17
29
(5,
N.C.
la430
,-,..:."n'..,9..."'.:.,..,.."...,;...""'..:.,','r',. :.25n '-,'.,.'.,.','.,.'-' S-1I00
c,j
I.... U
wIi
:z~z-
It-
~ ::t: I\&J
0
U
zdu~tJz
'"
NC
~
No connection.
FUNCTIONAL DESCRIPTION
The Z80 CTC has four independent counter/timer
channels. Each channel is individually programmed
with two words: a control word and a time-constant
word. The control word selects the operating mode
(counter or timer), enables or disables the channel
interrupt, and selects certain other operating parameters. If the timing mode is selected, the control
word also sets a prescaler, which divides the system clock by either 16 or 256. The time-constant
word is a value from 1 to 256.
2/14
192
Three channels have two outputs that occur at zero
count. The first output is a zero-count/timeout pulse
at the ZC/TO output. The fourth channel (Channel 3) does not have a ZC/TO output; interrupt request is the only output available from Channel 3.
The second output is Interrupt Request (INT), which
occurs if the channel has its interrupt enabled during programming. When the Z80 CPU acknowledges Interrupt Request, the Z80 CTC places an
interrupt vector on the data bus.
The four channels of the Z80 CTC are fully prioritized and fit into four contiguous slots in a standard Z80 daisy-chain interrupt structure. Channel 0
is the highest priority and Channel 3 the lowest. Interrupts can be individually enabled (or disabled) for
each of the four channels.
ARCHITECTURE
The CTC has four major elements, as shown in
figure 3.
• CPU bus I/O
• Channel control logic
• Interrupt logic
• Counter/timer circuits
CPU BUS I/O
The CPU bus 110 circuit decodes the address inputs,
and interfaces the CPU data and control signals to
the CTC for distribution on the internal bus.
Z8430
INTERNAL CONTROL LOGIC
CHANNEL CONTROL LOGIC
The CTC internal control logic controls overall chip
operating functions such as the chip enable. reset.
and read/write logic.
The channel control logic receives the 8-bit channel
control word when the counter/timer channel is programmed. The channel control logic decodes the
control word and sets the following operating conditions:
• Interrupt enable (or disable)
• Operating mode (timer or counter)
• Timer mode prescaler factor (16 or 256)
• Active slope for CLKlTRG input
• Timer mode trigger (automatic or CLKlTRG
input)
• Time constant data word to follow
• Software reset
INTERRUPT LOGIC
The interrupt control logic ensures that the CTC interrupts interface properly with the Z80 CPU interrupt system. The logic controls the interrupt priority
of the CTC as a function of the lEI signal. If lEI is
High. the CTC has priority. During interrupt processing. the interrupt logic holds lEO Low. which inhibits
the interrupt operation on lower priority devices. If
the lEI input goes Low. priority is relinquished and
the interrupt logic drives lEO Low.
If a channel is programmed to request an interrupt.
the interrupt logic drives lEO Low at the zero count.
and generates an INT signal to the Z80 CPU. When
tlliLZ80 CPU responds with interrupt acknowledge
(M1 and IORO). then the interrupt logic arbitrates
the CTC internal priorities. and the interrupt control
logic places a unique interrupt vector on the data
bus.
If an interrupt is pending, the interrupt logic holds
lEO Low. When the Z80 CPU issues a Return From
Interrupt (RETI) instruction. each peripheral device
decodes the first byte (ED16). If the device has a
pending interrupt, it raises lEO (High) for one M1
cycle. This ensures that all lower priority devices can
decode the entire RETI instruction and reset properly.
COUNTERITIMER CIRCUITS
TIME CONSTANT REGISTER
When the counter/timer channel is programmed. the
time constant register receives and stores an 8-bit
time constant value. which can be anywhere from 1
to 256 (0 = 256). This constant is automatically
loaded into the down-counter when the counter/time
channel is initialized. and subsequently after each
zero count.
PRESCALER
The prescaler, which is used only in timer mode,
divides the system clock frequency by a factor of
either 16 or 256.
The prescaler output clocks the down-counter during timer operation. The effect of the prescaler on
the down-counter is a multiplication of the system
clock period by 16 or 256. The prescaler factor is
programmed by bit 5 of the channel control word.
The CTC has four independent counter/timer circuits, each containing the logic shown in figure 4.
Figure 3 : Functional Block Diagram.
DATA
FROM {
Z80 CPU
INT
lEI
CONTROL
lEO
ZCITO
ClK/TRG
3/14
193
Z8430
Figure 4 : CounterlTimer Block Diagram.
cally modifies the vector for the channel requesting
service.
A control word is identified by a 1 in bit O. A 1 in
bit 2 indicates a time constant word is to follow. Interrupt vectors are always addressed to Channel 0,
and identified by a 0 in bit O.
ADDRESSING
INTERNAL BUS
ZClTO
CLK/TRQ
CLOCK
-----I
--1
PRESC.....R
During programming, channels are addressed with
the channel select pins CS, and CS2. A 2-bit binary
code selects the appropriate channel as shown in
the following table.
~
DOWN-COUNTER
Prior to each count cycle, the down-counter is
loaded with the time constant register contents. The
counter is then decremented one of two ways, depending on operating mode:
• By the prescaler output (timer mode)
• By the trigger pulses into the CLKlTRG input
(counter mode)
Without disturbing the down-count, the Z80 CPU
can read the count remaining at any time by performing an I/O read operation at the port address
assigned to the CTC channel. When the downcounter reaches the zero count, the ZC/TO output
generates a positive-going pulse. When the interrupt is enabled, zero count also triggers an interrupt
request signal (INT) from the interrupt logic.
PROGRAMMING
Each Z80 CTC channel must be programmed prior
to operation. Programming consists of writing two
words to the I/O port that corresponds to the desired
channel. The first word is a control word that selects
the operating mode and other parameters; the second word is a time constant, which is a binary data
word with a value from 1 to 256. A time constant
word must be preceded by a channel control word.
After initialization, channels may be reprogrammed
at any time. If updated control and time constant
words are written to a channel during the count operation, the count continues to zero before the new
time constant is loaded into the counter.
If the interrupt on any Z80 CTC channel is enabled,
the programming procedure should also include an
interrupt vector. Only one vector is required for all
four channels, because the interrupt logic automati-
4/14
194
Channel
CS,
CSo
0
1
2
0
0
1
1
0
1
0
1
3
RESET
The CTC has both hardware and software resets.
The hardware reset terminates all down-counts and
disables all CTC interrupts by resetting the interrupt
bits in the control registers. In addition, the ZCITO
and Interrupt outputs go inactive, lEO reflects lEI,
and 00-07 go to the high-impedance state. All channels must be completely reprogrammed after a
hardware reset.
The software reset is controlled by bit 1 in the channel control word. When a channel receives a software reset, it stops counting. When a software
reset is used, the other bits in the control word also
change the contents of the channel control register.
After a software reset a new time constant word
must be written to the same channel.
If the channel control word has both bits 01 and 02
set to 1, the addressed channel stops operating,
pending a new time constant word. The channel is
ready to resume after the new constant is programmed. In timer mode, if 03 = 0, operation is triggered automatically when the time constant word is
loaded.
CHANNEL CONTROL WORD PROGRAMMING
The channel control word is shown in figure 5. It sets
the modes and parameters described below.
INTERRUPT ENABLE. 07 enables the interrupt, so
that an interrupt output (INT) is generated at zero
count. Interrupts may be programmed in either
mode and may be enabled or disabled at any time.
OPERATING MODE. 06 selects either timer or
counter mode.
Z8430
Figure 5 : Channel Control Word.
'NT' •• UPT
t ["'AHLfS INTfRRUPT
o DISABLES
jJ
INTERRUPT
RESET
o ""
1
PAESCALER VALUE·
1 -: VAL UE OF 2S6
o " VALUE OF 16
-
sn rCIS
---.
CONTINUED OP[RATION
- SOFTWARE R(SET
TIME CONSTANT
o
0
NO TIME CONSTANT fOllOWS
1 ~ TlM£ CONSTANT f-OllOW5
----'
o Sf! refS fAlUNG fOGF
1
CONTROL O • • ECTO.
V(CTOR
o· CONTROL WORD
o -'1
MODE
o sHEeTS lIMER MODE
1 SHlCTS COUNTER MODE
CUtlTAQ EDQE SELECTION
lL
RISING EDGE
---~
TIMER TRIOOER·
AUTOMATIC TRIGGER WHEN
TIME CON~TANlIS lOADf'O
1 -0 ClKITRG PULSE STARTS TIMER
o ""
• TIMfR MODE ONl y
PRESCALER FACTOR. (Timer Mode Only). Ds selects factor - either 16 or 256.
setup time. If the minimum time is not met, the timer
will start on the third clock cycle (T3).
TRIGGER SLOPE. D4 selects the active edge or
slope of the CLKITRG input pulses. Note that reprogramming the CLKlTRG slope during operation is
equivalent to issuing an active edge. If the trigger
slope is changed by a control word update while a
channel is pending operation in timer mode, the result is the same as a CLKlTRG pulse and the timer
starts. Similarly, if the channel is in counter mode,
the counter decrements.
Once started the timer operates continuously, without interruption or delay, until stopped by a reset.
TRIGGER MODE. (Timer Mode Only). D3 selects
the trigger mode for timer operation. When D3 is
reset to 0, the timer is triggered automatically. The
time constant word is programmed during an 1/0
write operation, which takes one machine cycle. At
the end of the write operation there is a setup delay
of one clock period. The timer starts automatically
(decrements) on the rising edge of the second clock
pulse (T2) of the machine cycle following the write
operation. Once started, the timer runs continuously. At zero count the timer reloads automatically and
continues counting without interruption or delay,
until stopped by a reset.
When D3 is set to 1 , the timer is triggered externally
through the CLKlTRG input. The time constant word
is programmed during an /10 write operation, which
takes one machine cycle. The timer is ready for
operation on the rising edge of the second clock
pulse (T2) of the following machine cycle. Note that
the first timer decrement follows the active edge of
the CLKITRG pulse by a delay time of one clock
cycle if a minimum setup time to the rising edge of
clock is met. If this minimum is not met, the delay is
extended by another clock period. Consequently,
for immediate triggering, the CLK/TRG input must
precede T2 by one clock cycle plus its minimum
TIME CONSTANT TO FOLLOW. A 1 in D2 indicates
that the next word addressed to the selected channel is a time constant data word for the time constant register. The time constant word may be
written at any time.
A 0 in D2 indicates no time constant word is to follow. This is ordinarily used when the channel is already in operation and the new channel control word
is an update. A channel will not operate without a
time constant value. The only way to write a time
constant value is to write a control word with D2 set.
SOFTWARE RESET. Setting D1 to 1 causes a software reset, which is described in the Reset section.
CONTROL WORD. Setting Do to 1 identifies the
word as a control word.
TIME CONSTANT PROGRAMMING
Before a channel can start counting it must receive
a time constant word from the CPU. During programming or reprogramming, a channel control
word in which bit 2 is set must precede the time constant word to indicate that the next word is a time
constant. The time constant word can be any value
from 1 to 256 (figure 6). Note that 0016 is interpreted
as 256.
In timer mode, the time interval is controlled by three
factors:
• The system clock period (<1»
• The prescaler factor (P), which multiplies the interval by either 16 or 256
• The time constant (T), which is programmed into
the time constant register.
5/14
195
Z8430
Figure 6 : Time Constant Word.
ClK. System Clock (Input). Standard single-phase
l80 system clock.
ClKlTRGo-ClKlTRG3. External Clock/Timer Trigger(lnput, user-selectable Active High or Low). Four
pins corresponding to the four l80 CTC channels.
In counter mode, every active edge on this pin decrements the down-counter. In timer mode, an active edge starts the timer.
Consequently, the time interval is the product of
16 x !\l
(4 iJs with a 4 MHz clock). The maximum timer interval is 256 x !\l x 256 (16.4 ms with a 4 MHz clock).
For longer intervals timers may be cascaded.
!\l x P x T. The minimum timer resolution is
INTERRUPT VECTOR PROGRAMMING
If the l80 CTC has one or more interrupts enabled,
it can supply interrupt vectors to the l80 CPU. To
do so, the l80 CTC must be preprogrammed with
the most-significant five bits of the interrupt vector.
Programming consists of writing a vector word to the
I/O port corresponding to the l80 CTC Channel o.
Note that Do of the vector word is always zero, to
distinguish the vector from a channel control word.
01 and 02 are not used in programming the vector
word. These bits are supplied by the interrupt logic
to identify the channel requesting interrupt service
with a unique interrupt vector (figure 7). Channel 0
has the highest priority.
CSo-CS1. ChannelSelect(lnputs Active High). Twobit binary address code selects one of the four CTC
channels for an I/O write orread (usually connected
to Ao and A1).
00-07. System Data Bus (Bidirectional, 3-state).
Transfers all data and commands between the l80
CPU and the l80 CTC.
lEI. Interrupt Enable In (Input, Active High). A High
indicates that no other interrupting devices of higher
priority in the daisy chain are being serviced by the
l80 CPU.
lEO. Interrupt Enable Out (Output, Active High).
High only if lEI is High and the Z80 CPU is not serFigure 8 : A Typical l80 Environment.
SYSTEM
BUSES
+5V
CPU
Figure 7 : Interrupt Vector Word.
iNT
L
PIO
~
INT
1~1~!~!~I~!~i~:~1
sup:l;eVri
=:r-
lEI
0 == INTERRUPT VECTO" NORD
1 = CONTROL WORD
+.v
T
tlY U::'I::H
CHANNEL IDENTIFIER
(AUTOMATICAll Y INSEt- rEO
BY CTq
0 = CHANNEl 0
o
o
1 "" CHANNEL 1
1
I
0 == CHANNEl 2
1 '" CHANNEl 3
lEI
IC/TO,
CTC
ZCIT!>,
INT
lEO
PIN DESCRIPTION
CEo Chip Enable (Input, Active Low). When enabled
the CTC accepts control words, interrupt vectors, or
time constant data words from the data bus during
an I/O write cycle; or transmits the contents of the
down-counter to the CPU during an I/O read cycle.
In most applications this signal is decoded from the
eight least significant bits of the address bus for any
of the four I/O port addresses that are mapped to
the four counter-timer channels.
6/14
196
WIRDYB
• ,0
!NT
-
lEI
-
ROY
OM ..
Z8430
vicing an interrupt from any Z80 CTC channel. lEO
blocks lower priority devices from interrupting while
a higher priority interrupting device is being serviced.
INT. Interrupt Request (Output, Open Drain, Active
Low). Low when any Z80 CTC channel that has
been programmed to enable interrupts has a zerocount condition in its down-counter.
IORQ. Input/Output Reques1l!nput from CPU, Active Low). Used with CE and RD to transfer data and
channel control words between the Z80 CPU and
the Z80 CTC. During a write cycle, lORa and CE
are active and RD inactive. The Z80 CTC does not
receive a specific write signal; rather, it interng!jy
generates its own from the inverse of an active RD
signal. In a read cycle, lORa, CE and RD are active ; the contents of the down-counter are read by
the Z80 CPU. If lORa and M1 are both true, the
CPU is acknowledging an interrupt request, and the
highest priority interrupting channel places its interrupt vector on the Z80 data bus.
M1. Machin~ycle One (Input from CPU, Active
Low). When M1 and lORa are active, the Z80 CPU
is acknowledging an interrupt. The Z80 CTC then
places an interrupt vector on the data bus if it has
highest priori~, and if a channel has requested an
interrupt (INT).
RD. Read Cycle Status (InpYL,Active Low). Used in
conjunction with lORa and CE to transfer data and
channel control words between the Z80 CPU and
the Z80 CTC.
Figure 9 : Read Cycle Timing.
~
h
~
b
h
CLK~
CSu • CS"
CE
==:x:
CHANNEL ADDRESS
c:=:
_--T----------------------_--T-----------------------
RD
I
_J
Ml
I
_J
DATA _ _ _ _ _ _
~X
IN
X'-____
WRITE CYCLE TIMING
Figure 10 shows write cycle timing for loading control, time constant or vector words.
The CTC does not have a write signal ir.!e!!t, so it
generates one internally when the read (illJ) input
is High during T1. During T2 lORa and CE inputs
are Low: RD, lORa, and CE. A 2-bit binary code at
inputs CS1 and CSO selects the channel to be read.
M1 must be High to distinguish this cycle from an interrupt acknowledge. No additional wait states are
allowed.
Figure 10: Write Cycle Timing.
T.
RESET. Reset (Input Active Low). Terminates all
down-counts and disables all interrupts by resetting
the interrupt bits in all control registers; the ZCITO
and the Interrupt outputs go inactive; lEO reflects
lEI; Do-D7 go to the high-impedance state.
T,
T,
T,
eLK
CHANNEL ADDRESS
\
\
IORG
ZCITOo-ZCITCh. Zero CountITimeout (Output, Active High). Three ZCITO pins corresponding to Z80
CTC channels 2 through 0 (Channel 3 has no ZCITO
pin). In both counter and timer modes the output is
an active High pulse when the down-counter decrements to zero.
x:::=
r--r---
---~----------------------Ml
I
-.I
DATA - - - - - - - - - .
TIMING
READ CYCLE TIMING
Figure 9 shows read cycle timing. This cycle reads
the contents of a down-counter without disturbing
the count. During clock cycle h the Z80 CPU initiates a read cycle by driving the following inputs.
Low. M1 must be High to distinguish a write cycle
from an interrupt acknowledge. A 2-bit binary code
at inputs CS1 and CSo selects the channel to be addressed, and the word being written is placed on the
Z80 data bus. The data word is latched into the appropriate register with the rising edge of clock cycle
T3.
7/14
197
---------
Z8430
TIMER OPERATION
INTERRUPT OPERATION
In the timer mode, a ClKlTRG pulse input starts the
timer (figure 11) on the second succeeding rising
edge of ClK. The trigger pulse is asynchronous and
it must have a minimum width. A minimum lead time
(210 ns) is required between the active edge of the
ClKlTRG and the next rising edge of ClK to enable
the prescaler on the following clock edge. If the
ClKlTRG edge occurs closer than this, the initiation
of the timer function is delayed one clock cycle. This
corresponds to the startup timing discussed in the
programming section. The timer can also be started
automatically if so programmed by the channel control word.
The zao CTC follows the zao system interrupt
protocol for nested priority interrupts and return from
interrupt, wherein the interrupt priority of a peripheral is determined by its location in adaisychain. Two
lines - lEI and lEO - in the CTC connect it to the
system daisy chain. The device closest to the + 5 V
supply has the highest priority (figure 13). For additional information on the zao interrupt structure,
refer to the zao CPU Technical Manual.
Figure 11 : Timer Mode Timing.
CLKITRO
IIIT'ERNAL _ _ _ _ _--J
TIllER
COUNTER OPERATION
In the counter mode, the ClKlTRG pulse input decrements the downcounter. The trigger is asynchronous, but the count is synchronized with ClK.
For the decrement to occur on the next rising edge
of ClK, the trigger edge must precede ClK by a
minimum lead time as shown in figure 12. If the lead
time is less than specified, the count is delayed by
one clock cycle. The trigger pulse must have a minimum width, and the trigger period must be at least
twice the clock period.
The ZC/TO output occurs immediately after zero
count, and follows the rising ClK edge.
Figure 12: Counter Mode Timing.
Within the zao CTC, interrupt priority is predetermined by channel number: Channel 0 has the highest priority, and Channel 3 the lowest. If a device
or channel is being serviced with an interrupt routine, it cannot be interrupted by a device or channel
with lower priority until service is complete. Higher
priority devices or channels may interrupt the servicing of lower priority devices or channels.
A zao CTC channel may be programmed to request
an interrupt every time its down-counter reaches
zero. Note that the CPU must be programmed for
interrupt mode 2. Some time after the interrupt request, the CPU sends an interrupt acknowledge.
The CTC interrupt control logic determines the highest priority channel that is requesting an interrupt.
Then, if the CTC lEI input is High (indicating that it
has priority within the system daisy chain) it places
an a-bit interrupt vector on the system data bus. The
high-order five bits of this vector were written to the
CTC during the programming process; the next two
bits are provided by the CTC interrupt control logic
as a binary code that identifies the highest priority
channel requesting an interrupt; the low-order bit is
always zero.
INTERRUPT ACKNOWLEDGE TIMING
Figure 14 shows interrupt acknowledge timing. After
an interrupt reques.L1he Z~O CPU sends an interrupt acknowledge (M1 and lORa). All channels are
inhibited from changing their interrupt request status
when M1 is active - about two clock cycles earlier
than lORa. RD is High to distinguish this cycle from
an instruction fetch.
Figure 13 : Daisy-Chain Interrupt Priorities.
CLKITRG
INTERNAL
COUNTER
HIGMEST PIlIORITY
DI!VICIE
-----.J/
ZCITO _ _ _- J
8/14
19a
LOWEST ""'OIUT.,
DE vier
Z8430
The eTe interrupt logic determines the highest
priority channel requesting an interrupt. If the eTe
interrupt enable input (lEI) is High, the highest
priority interrupting channel within the eTe places
its interrupt vector on the data bus when IORO goes
Low. Two wait states (TWA) are automatically inserted at this time to allow the daisy chain to stabilize. Additional wait states may be added.
RETURN FROM INTERRUPT TIMING
At the end of an interrupt service routine the RETI
(Return From Interrupt) instruction initializes the
daisy chain enable lines for proper control of nested
priority interrupt handling. The eTe decodes the 2byte RETI code internally and determines whether
it is intended for a channel being serviced.
Figure 15 shows RETI timing.
If several Z80 peripherals are in the daisy chain, lEI
settles active (High) on the chip currently being serviced when the opcode E016 is decoded. If the following opcode is 4016. the peripheral being serviced
is released and its lEO becomes active. Additional
wait states are allowed.
Figure 15 : Return From Interrupt Timing.
Figure 14 : Interrupt Acknowledge Timing.
eLK
---'1
1£0 __________________________
DATA-------------------{
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
V,
Voltages on all Input and Outputs with respect to GND
TA
Operation Ambient Temperature
TSl9
Storage Temperature
- 0.3 to + 7.0
As Specified in Ordering Information
---~--.-.~.--
- 65 to + 150
I
Unit
I V
I
I 'C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This IS a stress rating
only; operation of the device at any condition above those Indicated in the operational sections ot these specificdtiolls is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
9/14
199
Z8430
STANDARD TEST CONDITIONS
The characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (0 V). Positive current flows into
the referenced pin. Available operating temperature
ranges are:
• 0 ·C to + 70 ·C,
+ 4.75 V 5, Vee 5, + 5.25 V
• - 40 ·C to + 85 ·C,
+ 4.75 V 5, Vee 5, + 5.25 V
• - 55 "C to + 125 ·C,
+ 4.75 V 5, Vee 5, + 5.5 V
on
2.1K
DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
- 0.3
0,45
V
VILC
Clock Input low Voltage
VIHC
Clock Input High Voltage
VIL
Input low Voltage
+ 0.3
0.8
V
VIH
Input High Voltage
+ 2.0
Vcc
V
VOL
Output low Voltage
IOL = 2.0 mA
VOH
Output High Voltage
IOH =- 250 ~A
+ 2,4
Vee - 0.6 Vee+O.3
0.4
V
V
V
Icc
Power Supply Current
100
mA
III
Input leakage Current
VIN =0 to Vcc
-10
10
~A
ILO
3-State Output leakage Current in Float
VOUT = 0,4 to Vcc
-10
10
Darlington Drive Current
VO H = 1.5, REXT = 390 Q
- 1.5
IOHD
~A
mA
CAPACITANCE
Symbol
Parameter
ClK
Clock Capacitance
CIN
Input Capacitance
COUT
10/14
200
Output Capacitance
Notes
Unmeasured pins returned
to ground.
Min.
Max.
Unit
20
pF
5
pF
10
pF
Z8430
AC CHARACTERISTICS
N°
Symbol
1
2
TcC
Clock Cycle Time
TwCH
Clock Width (high)
Parameter
Notes
Z8430
Z8430A
Z8430B
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
400 (1 ) 250 (1) 165 (1)
170 2000 105 2000 65 2000
170 2000 105 2000 65 2000
30
30
20
30
30
20
0
0
0
100
250
160
150
100
200
70
250
115
70
240
115
240
130
200
230
110
90
60
50
40
70
210
90
190
130
300
3
TwCI
Clock Width (low)
4
5
6
7
8
9
10
11
12
13
14
15
TIC
Clock Fall Time
TrC
Clock Rise Time
TdMI(IEO)
MI J, to lEO J, Delay (interrupt
immediately preceding MI)
(3)
16
TdIO(DOI)
lORa J, to Data Out Delay
(INTA cycle)
(2)
340
160
110
17
18
TdIEI(IEOf)
lEI J, to lEO J, Delay
TdIEI(IEOr)
lEI i to lEO i Delay
(after ED decode)
(3)
(3)
190
220
130
160
100
110
19
TdC(INT)
20
th
All Hold Times
TdC(DO)
i Setup Time
i Setup Time
lORa J, ot Clock i Setup Time
RD J, to Clock i Setup Time
Clock i to Data Out Delay
tdC(DOz)
Clock J, to Data Out Float Delay
TsCS(C)
TsCE(C)
TsIO(C)
TsRD(C)
CS to Clock
CE to Clock
i Setup Time
i Setup Time
TsDI(C)
Data in to Clock
TsMI(C)
MI to Clock
TdCLK(INT)
Clock
(2)
i to INT J, Delay
CLK/TRG i to INT J,
TsCTR(C) Satisfied
(4)
TcCTR
CLK/TRG Cycle Time
TrCTR
CLK/TRG Rise Time
TfCTR
CLKITRG Fall Time
(TeC
(TeC
+140)
+120)
(19)
+(26)
1
+(19)
+(26)
(19)
+(26)
1
+(19)
+(26)
(19)
+(26)
1
+(19)
+(26)
(5)
TsCTR(C) Not Satisfied
21
22
23
(TeC
+200)
(5)
(2TcC)
(2TcC)
50
50
(2TcC)
50
50
40
40
(A) 2.5 TcC > (n-2) TdIEI(IEOf) + TdMI(IEO) + TsIEI(IO) + TTL buffer delay. if any.
(B) RESET must be active for a minimum of 3 clock cycles.
Notes: t. TcC = TwCh + TwCI + TrC + TfC.
2. Increase delay by to ns for each 50 pF increase in loading 200 pF maximum for data lines, and 100 pF for control lines.
3. Increase delay by 2 ns for each 10 pF increase in loading 100 pF maximum.
4. Timer mode.
5. Counler mode.
6. RESET must be active for a minimum of 3 clock cycles.
11/14
201
.~--~--------~--- ..
-----
~-----.--------~ ..
-
---
Z8430
AC CHARACTERISTICS (continued)
N°
Symbol
24
25
26
TwCTRI
TsCTR(Cs)
CLKJTRG l' 10 Clock
for Immediate Counl
Setup Time
27
TsCTR(CI)
CLKITRG l' 10 Clock l' Selup Time
for enabling of Prescaler on
following Clock l'
28
29
TdC(ZC/TOr)
Clock
l'
10 ZC/TO
l'
Delay
TdC(ZC/TOf)
Clock
J-
10 ZC/TO
J-
Delay
Parameter
Notes
Z8430
(ns)
TwCTRh
78430B
(ns)
(ns)
(ns)
(ns)
(5)
200
200
300
200
200
210
120
120
150
(4)
210
210
150
CLKlTRG Widlh (low)
CLKJTRG Width (high)
l'
Z8430A
Min. Max. Min. Max. Min. Max.
260
190
190
190
(ns)
140
140
(A) 2.5 TcC > (n-2) TdIEI(IEOf) + TdMI(IEO) + TsIEI(IO) + TTL buffer delay, if any.
(8) RESET must be active for a minimum of 3 clock cycles.
Notes: 1. TcC = TwCh + TwCI + TrC + TfC.
2. Increase delay by IOns for each 50 pF increase in loading 200 pF maximum for data lines, and 100 pF for control lines.
3. Increase delay by 2 ns for each 10 pF increase in loading 100 pF maximum.
4. Timer mode.
5. Counter mode.
6. RESET must be active for a minimum of 3 clock cycles.
12/14
202
Z8430
AC CHARACTERISTICS (continued)
CLOCK.
~
~~
.
Hv--Q)-o-
14-
it-
~I
\.
co
\.
10110
1--0-
L
,
I---
INTERNAL STRUCTURE
The internal structure of the device includes a Z80
CPU interface, internal control and interrupt logic,
and two full-duplex channels, Each channel contains its own set of control and status (write and
read) registers, and control and status logic that provides the interface to modems or other external devices,
The registers for each channel are designated as
follows:
WRO-WR7 - Write Registers 0 through 7
RRO-RR2 - Read Register 0 through 2
The register group includes five 8-bit control registers, two sync-character registers and two status
registers, The interrupt vector is written into an additional 8 -bit register (Write Register 2) in Channel B that may be read through another 8-bit register
(Read Register 2) in Channel B, The bit assignment
and functional grouping of each register is configured to simplify and organize the programming
process, Table 1 list the functions assigned to each
read or write register.
The logic for both channels provides formats, synchronization and validation for data transferred to
10/20
214
and from the channel interface, The modem control
inputs, Clear To Send (CTS) and Data Carrier Detect (DCD), are monitored by the external control
and status logic under program control, All external
Read Register Functions
RRO
RR1
RR2
Transmit/Receive Buffer Status, Interrupt
Status and External Status
Special Receive Condition Status
Modified Interrupt Vector (channel B only)
Write Register Functions
WRO
WR1
WR2
WR3
WR4
WR5
WR6
WR7
Register pointers, CRC initialize,
initialization commands for the various
modes, etc,
TransmittiReceive Interrupt and Data
Transfer Mode Definition
Interrupt Vector (channel B only)
Receive Parameters and Control
Transmit/Receive Miscellaneous
Parameters and Modes
Transmit Parameters and Controls
Sync Character or SDLC Address Field
Sync Character or SDLC Flag
Z8440-Z8441-Z8442
control-and-status-Iogic signals are general-purpose in nature and can be used for functions other
than modem control.
routed through one of several paths (data or CRC)
depending on the selected mode and-in asynchronous modes-the character length.
DATA PATH
The transmitter has an 8-bit transmit data buffer register that is loaded from the internal data bus, and a
20-bit transmit shift register that can be loaded from
the sync-character buffers or from the transmit data
register. Depending on the operational mode, outgoing data is routed throught one of four main paths
before it is transmitted from the Transmit Data output (TxD).
The transmit and receive data path illustrated for
Channel A in figure 13 is identical for both channels.
The receiver has three 8-bit buffer registers in a
FIFO arrangement, in addition to the 8-bit receive
shift register. This scheme creates additional time
for the CPU to service an interrupt at the beginning
of a block of high-speed data. Incoming data is
Figure 13 : Transmit and Receive Data Path (channel A).
c"'''''
-§,,"
TOCHANNElB. - - - - - - - - - - - - - - - " ' ' ' ' ' - - - - - - - - - - - - - - EXTEANAl STATUS lOGIC.
CONTROL LOGIC. HC _ _ _ _ _- - , " "_ _ __ _ : ; " " - - - -
R,CA_
RECEIYE
CLOCK
tOGIC
11/20
215
Z8440-Z8441-Z8442
PROGRAMMING
The system program first issues a series of commands that initialize the basic mode of operation
and then other commands that qualify conditions
within the selected mode. For example, the asynchronous mode, character length, clock rate, number of stop bits, even or odd parity might be set
first; then the interrupt mode; and finally, receiver
or transmitter enable.
Both channels contain registers that must be programmed via the system program prior to operation.
The chaQDel-select input (B/A) and the control/data
input (C/O) are the command-structure addressing
controls, and are normally controlled by the CPU address bus. Figures 16 an 17 illustrate the timing relationships for programming the write registers and
transfering data and status.
READ REGISTER
The SIO contains three read registers for Channel B and two read registers for Channel A (RRO-RR2
in figure 14) that can be to obtain the status information ; RR2 contains the internally-modifiable interrupt
vector and is only in the Channel B register set. The
status information includes error conditions, interrupt
vector and standard communications-interface signals.
and contains three bits (00-02) that point to the selected register; the second byte is the actual control word that is written into the register to configure
theSIO.
WRO is a special case in that all of the basic commands can be written to it with a single byte. Reset
(internal or external) initializes the pointer bits 00-02
to point to WRO. This implies that a channel reset
must not be combined with the pointing to any register.
Figure 14 : Read Register Bit Functions.
READ REGISTER 0
1~1~ID5\~I~I~ID\I~1
III
L§~L-R,cHARAcTERAVAILABLE
L.::=
INT PENDING (CH. A ONLY)
~~~UFFER
WRITE REGISTERS
The SIO contains eight write registers for Channel B and seven write registers for Channel A (WROWR7 in figure 15) that are programmed separately
to configure the functional personality of the channels ; WR2 contains the interrupt vector for both
channels and is only in the Channel B register set.
With the exception of WRO, programming the write
registers requires two bytes. The first byte is to WRO
12/20
216
}
*
fit UNDERRUNIEOM
"~EAKIABORT
"Used With External/Status
interrupt Mode
...
READ REGISTER It
,
0101010
10, 10, 10 10,1
1
To read the contents of a selected read register
other than RRO, the system program must first write
the pointer byte to WRO in exactly the same way as
a write register operation. Then, by executing a read
instruction, the contents of the addressed read register can be read by the CPU.
The status bits of RRO and RR1 are carefully
grouped to simplify status monitoring. For example,
when the interrupt vector indicates that a Special
Receive Condition interrupt has occurred, all the appropriate error bits can be read from a single register(RRI).
EMPTY
SYNC/HUNT
ers
L-ALLSENT
III
1
Q
1
Q
1
,
1
1
Q
Q
Q
Q
Q
Q
1
1
Q
1
1
Q
Q
IFI ELO 81TS
I FIELD BITS IN
}
IN PREVIOUS SECOND PREVlOUS
BYTE
BYTe
,
1
Q
Q
3
Q
•
Q
Q
5
.
7
•
,
1
•
L - PARITY ERR~~RROR
'----
R~
OVERAU
L . . - - - ~RCJFRAMI NG ERROR
END OF FRA ME (SOLC)
* Residue Data For Eight
Rx Bits/Character
Programmed
tUsed With Special Receive Condition Mode
READ REGISTER 2*
1~lo,lo,l.I~lo,l~lo,l
IIII1 ~~I'NTERRUPT
V,
.
"
•
Q
Q
V4
V6
VT
tVariable if "Status Affects
Vector" is Programmed
VECTOR
Z8440-Z8441-Z8442
Figure 15 : Write Register Bit Functions.
WR1TE REGISTER 0
WRITE REGISTER 4
I~I~I~I~I~I~I~I~I
I I I
o
0
0
0
1
o
1
0
o
a
1
o
o
o
o
o (}
o
1
1
1
0
1
REGISTER
REGISTER
REGiSteR
REGISTER
0
1
2
3
1
1
0
0 REGISTER 4
1
1
0
REGISTER 5
REGISTER 6
1
1
REGISTER 7
1
1
a
1
0
0
NULL CODe
0
1
1
0
1
0
SEND ABORT (SOLe)
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE tNT ON NEXT RII CHARACTER
,
0
1
RESET TK INT PENDING
ERlloR RESET
1
1
0
1
1
0
1
1
1
o
o
o
o
1
1
RETURN FROM tNT (CH·A ONLY)
0
1
0
1
o
o
0
1
SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1
0
1 Y. STOP BITS/CHARACTER
,
1
2 STOP BITS/CHARACTER
0 CI BIT SYNC CHARACTER
1
1
0
1
1
16 BIT SYNC CHARACTER
SOLC MODE (01111"0 FLAG)
EXTERNAL SYNC MODE
XI CLOCK MODE
XIS CLOCK MODE
X32 CLOCK MODE
XS4 CLOCK MODE
NULL CODE
RESET Rx CRe CHECKER
RESET Til CRe GENERATOR
RESET Tit UNOEARUNIEOM LATCH
WRITE REGISTER 5
WRITE REGISTER I
~
II
o
l
a
L
I
I~I~I~I~I~I~I~I~I
L- EXT INT ENABLE
Til tNT ENABLE
---STATUS AFFECTS VECTOR
(CH B ONLY)
Ax INT DISABLE
1 Rx INT ON FIRST CHARACTER
'OINT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR) }
1 1 tNT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)
,
* Or
on
Special
Condition
WAIT/READY ON RIT
'---~~:~:=~~g~ ~~~~[kON
~
o
II ~:~~~:::~:LE
lJ·~~===!h~E~NABLE
11
o
0
1
1
1
0
1
•
DTR
WRITE REGISTER 21CHANNEL B ONLY)
WRITE REGISTER 6
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
III~I~~~)
~;
V4
V,
INTERRUPT
VECTOR
SEND BREAK
Tx 5 BITS (OR lESS)lCHARACTER
Tx 1 BITS/CHARACTER
flo: S BITS/CHARACTER
Til 8 BITS/CHARACTER
11111.
I
~!~~HiH 1
V6
V7
SYNC
SYNC
SYNC
SYNC
SYNC
BIT 3
BIT 4
BIT 5
BIT.6
BIT 7
•
*Also SDLC Address Field
WRITE REGISTER 7
WRITE REGISTER 3
I~I~I~I~I~I~I~I~I
1III
I;)
o
1
1
0
1
0
1
,ENABLE
I~SYNC
L-R
Ax 5 BITS/CHARACTER
A~ 1 BITS/CHARACTER
Rx 6 BITS/CHARACTER
Rx tI BITS/CHARACTER
CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SOLe)
Rx CRC ENABLE
ENTER HUNT PHASE
AUTO ENABLES
III ~i~~g:i~tl
-SYNC BIT 11
•
ll~~~~~~~~~SYNC BITBIT 1312
SYNC
BIT
SYNC
14
SYNC BIT 15
*For SDLC it Must Be ProQrammed
to "01111110" For Flag Recognition
13/20
217
Z8440-Z8441-Z8442
TIMING
The 810 must have the same clock as the CPU
(same phase and frequency relationship, not
necessarily the same driver).
priority interrupt requestor (the one with lEI High)
places its interrupt vector on the data bus and sets
its internal interrupt-under-service latch.
READ CYCLE
RETURN FROM INTERRUPT CYCLE
The timing signals generated by a Z80 CPU input
instruction to read a data or status byte from the 810
are illustrated in figure 16.
Figure 19 illustrates the return from interrupt cycle.
Normally, the Z80 CPU issues a RETI (Return From
Interrupt) instruction at the end of an interrupt service routine. RETI is a 2-byte opcode (ED-4D) that
resets the interrupt-under-service latch in the 810 to
terminate the interrupt that has just been processed.
This is accomplished by manipulating the daisy
chain in the following way.
WRITE CYCLE
Figure 16 illustrates the timing and data signals
generated by a Z80 CPU output instruction to write
a data or control byte into the 810.
INTERRUPT-ACKNOWLEDGE CYCLE
After receiving an interrupt-request signal from an
810 (INT pulled Low), the Z80 CPU sends an interrupt-acknowledge sequence (M1 Low, and 10RO
Low a few cycles later) as in figure 18.
The 810 contains an internal daisy-chained interrupt
structure for prioritizing nested interrupts forthe various functions of its two channels, and this structure
can be used within an external user-defined daisy
chain that prioritizes several peripheral circuits.
The normal daisy-chain operation can be used to
detect a pending interrupt; however, it cannot distinguish between an interrupt under service and a
pending unacknowledged interrupt of a higher
priority. Whenever "ED" is decoded, the daisy chain
is modified by forcing High the lEO of any interrupt
that has not yet been acknowledged. Thus the daisy
chain identifies the device presently under service
as the only one with an lEI High and an lEO Low. If
the next opcode byte is "4D", the interrupt-underservice latch is reset.
To insure stable conditions in the daisy chain, all interrupt status signals are prevented from changing
while M1 is Low. When 10RO is Low, the highest
The ripple time of the interrupt daisy chain (both the
High-to-Low and the Low-to-High transitions) limits
the number of devices that can be placed in the
daisy chain. Ripple time can be improved with carrylook-ahead, or by extending the interrupt-acknowledge cycle. For further
information
about
tech niques for increasing the number of daisychained devices, refer to the Z80 CPU Data 8heet.
Figure 16 : Read Cycle.
Figure 17 : Write Cycle.
The lEI of the highest-priority device is terminated
High. A device that has an interrupt pending or
under service forces its lEO Low. For devices with
no interrupt pending or under service, lEO = lEI.
"
CLOCK
CE, CIC. Bli.
----~'~----~------~
RD--____________-+_________
RD
Mi-------------+___________
DATA _ _ _ _ _ _ _ _ _ _=:(
14/20
218
~--------------~---------
~_ __
DATA _ _ _ _ _ _ _ _ _ _ _ _ _
Z8440-Z8441-Z8442
Figure 18 : Interrupt Acknowledge Cycle.
T,
T,
T~
T,
Tw
Figure 19: Return from Interrupt Cycle.
T.
CLOCK
CLOCK
:1
0.1\
M1
I
L--Y
lORa
I
I
RO
lEI
=========7
:\_====
lEI
DATA-------------------(~~------
-,.,-----------r------
------.1
lEO - - - - - -____
~--------.....:..-Jr---
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VI
Voltage on all Input and Outputs with Respect to GND
TA
Operating Ambient Temperature
T stg
Storage Temperature
Value
Unit
- 0.3 to + 7.0
V
As Specified in Order Codes
°C
3tresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
mly; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Ex)Osure to absolute maximum rating conditions for extended periods may affect device reliability.
rEST CONDITIONS
rhe characteristics below apply for the following test
:onditions, unless otherwise noted. All voltages are
'eferenced to GND (OV). Positive current flows into
he referenced pin. Available operating temperature
anges are:
• 0 "C to + 70 "C,
+ 4.75V s Vcc s + 5.25V
• - 40 "C to + 85 'C,
+ 4.75V S Vcc s + 5.25V
• - 55 "C to + 125 "C,
+ 4.75V S Vcc s + 5.5V
.5V
21K
-he product number for each operating temperature
ange may be found in the ordering information secion.
~APACITANCE
Symbol
Parameter
C
Clock Capacitance
CIN
Input Capacitance
COUT
Output Capacitance
Iver specified temperature range; f
Note
Unmeasured Pins
Returned to Ground
Min.
Max.
Unit
40
pF
5
pF
10
pF
= 1 MHz.
15/20
219
Z8440-Z8441-Z8442
DC CHARACTERISTICS
Symbol
Test Conditions
Parameter
Min.
Max.
- 0.3
+ 0.45
Unit
VllC
Clock Input Low Voltage
VIHC
Clock Input High Voltage
Vil
Input Low Voltage
- 0.3
+ 0.8
V
VIH
Input High Voltage
2.0
Vee
V
Val
Output Low Voltage
10l = 2.0 mA
-
+ 0.4
V
VOH
Output High Voltage
10H =- 250 ~A
+ 2.4
Input Leakage Current
VIN =0 to Vee
-10
+ 10
~
3-State Output Leakage Current in Float
VOUT = 0.4 to Vee
-10
+ 10
~A
SYNC Pin Leakage Current
o < VIN
- 40
+ 10
~
100
mA
III
10l
lL(sy)
Icc
V
V
Vee - 0.6 Vee + 0.3
< Vee
Power Supply Current
V
Over specified temperature and voltage range.
AC CHARACTERISTICS
Z8440,
1, 2
N°
Symbol
Parameter
Z8440,
1,2A
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
Clock Cycle Time
400 4000 250 4000 165 4000
Clkock Width (high)
170 2000 105 2000
1
TcC
2
TwCh
3
TfC
Clock Fall Time
30
30
4
TrC
Clock Rise Time
30
30
5
TwCI
Clock Width (low)
l' Setup Time
l' Setup Time
CE, C/D, B/A to Clock
160
145
lORa, RD, to Clock
240
115
8
TdC(DO)
Clock
9
TsDI(C)
10
TdRD(DOz)
l' to Data Out Delay
Data in to Clock l' Setup (write or MI cycle)
RD l' to Data Out Float Delay
11
TdIO(DOI)
lORa J, to Data Out Delay (INTACK cycle)
l' Setup Time
12
TsMI(C)
MI to Clock
TsIEI(IO)
lEI to lORa J, Setup Time (INTACK cycle)
14
TdMI(IEO)
MI J, to lEO J, Delay (interrupt before MI)
15
TdIEI(IEOr)
lEI
16
TdIEI(IEOf)
lEI J, to lEO J, Delay
TdC(INT)
18
TdIO(W/RWf)
19
TdC(W/RR)
20
TdC(W/RWz)
21
Th
16/20
220
240
50
50
150
30
230
110
90
340
160
100
90
75
200
140
120
l' to INT J, Delay
2000
60
220
210
l' to lEO l' Delay (after ED decode)
Clock
15
60
TsAD(C)
TsCS(CI)
2000
15
70
6
13
70
170 2000 105 2000
7
17
Z8440,
1,28
300
190
150
100
70
150
100
70
150
160
200
200
lORa J, or CE J, to W/RDY J, Delay (wait mode)
300
210
175
l' to W/RDY J, Delay (ready mode)
120
120
100
Clock
Clock J, to W/RDY Float Delay (wait mode)
Any unspecified hold when setup is specified
150
0
130
0
110
0
28440-28441-28442
AC CHARACTERISTICS (continued)
Z8440,
Parameter
N°
Symbol
22
23
24
25
26
27
28
TwPh
Pulse Width (high)
TwPI
Pulse Width low)
TcTxC
TxC Cycle Time
TwTxCI
TxC Width (low)
TwTxCh
TdTxC(TxD)
TdTxC(W/RRf)
TxC Width (high)
TxC
-1
Clk Periods'
5
TxC J, to INT J, Delay
Clk Periods'
5
400
180
180
0
140
10
10
4
36
37
TdRxC(SYNC)
RxC l' to SYNC J, Delay
(outputs modes)
38
TsSYNC(RxC)
SYNC -1 to RxC l' Setup
(external sync modes)
RxC Cycle Time
TwRxCI
RxC Width (low)
TwRxCh
RxC Width (high)
TsRxD(RxC)
RxD to RxC
ThRxD(RxC)
RxC
TdRxC(INT)
200
200
400
180
180
to TxD Delay (xl mode)
TdRxC(W/RRf)
TcRxC
l'
Setup Time (xl mode)
l'
l'
to RxD Hold Time (xl mode)
l'
to INT
RxC to W/RDY
(ready mode)
RxC
-1
-1
Delay
Delay
Clk Periods'
Clk Periods'
Clk Periods'
Z8440,
1,2A
Z8440,
1,28
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
TxC -1 to W/RDY J, Delay
(ready mode)
29
30
31
32
33
34
35
TdTxC(INT)
Notes
1,2
-100
=
=
=
200
200
400
180
180
400
9
5
13
5
400
180
180
0
140
10
13
7
10
4
9
=
=
=
-100
=
=
=
200
200
330
100
100
=
=
=
300
9
5
220
9
13
5
330
100
100
0
100
10
13
13
7
10
4
13
7
9
=
=
=
9
=
=
=
-100
In all modes, the System Clock rate must be at least five times the maximum data rate RESET must be active a minimum of one complete Clock Cycle .
• System Clock.
17/20
221
Z8440-Z8441-Z8442
AC CHARACTERISTICS
eLk
iOiiQ, liD
--------------~
Do-D7
--------------~----------Y
,.,
1110
W.DY-----------------------------------~~~--~
18/20
222
Z8440-Z8441-Z8442
AC CHARACTERISTICS (continued)
r-€>- --~~\~_--'fl
1-----®---1
TXD
RXc
Gi
SIiS-THOMSON
~I ililU©[ij@~~Ii
---------------V
..
,
•
~DY
___________________________________J
11/14
235
Z8470
AC CHARACTERISTICS (continued)
Z8470,
N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
12/14
236
Symbol
Parameter
TcC
Clock Cycle Time
TwCh
Clock Width (high)
TIC
Clock Fall Time
TrC
Clock Rise Time
TwCI
Clock Width (low)
TsAD(C)
CE, C/D, B/A to Clock
TsCS(C)
IORO, RD, to Clock
TdC(DO)
Clock
TsDI(C)
t
t
Setup Time
Setup Time
to Data Out Delay
Data in to Clock
t
t
t
Setup Time (write or MI cycle)
TdRD(DOz)
RD
to Data Out Float Delay
TdIO(DOI)
IORO J, to Data Out Delay (INTACK cycle)
t
TsMI(C)
MI to Clock
TsIEI(IO)
lEI to IORO J, Setup Time (INTA cycle)
Setup Time
TdMI(IEO)
MI J, to lEO J, Delay (interrupt before MI)
TdIEI(IEOr)
lEI
TdIEI(IEOf)
lEI J, to lEO J, Delay
TdC(INT)
TdIO(W/RWf)
TdC(W/RR)
TdC(W/RWz)
t
Clock
to lEO
t
t
Delay (after ED decode)
to INT J, Delay
IORO J, or CE J, to W/RDY J, Delay (wait mode)
Clock
t
to W/RDY J, Delay (ready mode)
Clock J, to W/RDY Float Delay (wait mode)
Z8470A
Z8470B
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
400 4000 250 4000 165 4000
170 2000 105 2000 70 2000
15
30
30
30
30
15
170 2000 105 2000 70 2000
160
145
60
240
115
60
220
150
240
50
50
30
230
110
90
160
100
340
210
75
90
200
140
120
190
300
160
150
100
70
100
70
150
200
200
150
210
300
175
120
120
100
130
110
150
Z8470
AC CHARACTERISTICS (continued)
~'----
RxO
---_...../
AC CHARACTERISTICS (continued)
Z8470
N°
Symbol
1
2
TwPh
3
4
TcTxC
Parameter
Unit
Z8470A
(ns)
(ns)
(ns)
(ns)
Pulse Width (high)
200
Pulse Width (low)
TxC Cycle Time
200
400
TwTxCI
TxC Width (low)
180
~
180
~
5
TwTxCh
TxC Width (high)
180
~
180
~
6
TdTxC(TxD)
7
TdTxC(W/RRf)
8
TdTxC(INT)
9
TcRxC
RxC Cycle Time
10
11
TwRxCI
TwRxCh
12
TsRxD(RxC)
RxD to RxC
13
14
ThRxD(RxC)
RxD Hold Time (xl mode)
TdRxC(W/RRf)
RxC l' to W/RDY J, Delay
(ready mode)
15
TdRxC(INT)
TwPI
200
~
TxC J, to W/RDY J, Delay
(ready mode)
Clk Periods
5
9
TxC J, to INT J, Delay
Clk Periods
~
RxC Width (low)
5
400
180
RxC Width (high)
180
~
RxC
l' to INT J, Delay
200
400
400
TxC J, to TxD Delay
l' Setup Time (xl mode)
Z8470B
Min. Max. Min. Max. Min. Max.
9
~
0
140
(ns)
~
200
330
100
100
300
5
5
400
180
180
Clk Periods
10
13
0
140
10
Clk Periods
10
13
10
(ns)
200
~
~
~
220
9
5
9
9
5
330
100
~
100
~
~
~
~
9
~
13
0
100
10
13
13
10
13
13/14
237
Z8470
ORDERING INFORMATION
Type
Package
Temp.
Clock
Z8470B1
Z8470F1
Z847001
Z847006
Z847002
Z8444C1
Dlp·40 (plastic)
DIP40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/ + 85°C
-55/ + 125°C
0/+ 70°C
2.5 MHz
Z8470AB1
Z8470AF1
Z8470A01
Z8470A06
Z8470A02
Z8444AC1
DIP-40 (plastic)
DIP40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
-55/ + 125°C
0/+ 70°C
4 MHz
Z8470BB1
Z8470BF1
Z8470B01
Z8470B06
Z8470B02
Z8444BC1
DIP-40 (plastic)
DIP-40 (frit seal)
DIP-40 (ceramic)
DIP-40 (ceramic)
DIP-40 (ceramic)
PLCC44 (plastic chip-carrier)
0/+ 70°C
0/+ 70°C
0/+ 70°C
-40/+ 85°C
-55/+ 125°C
0/ + 70°C
6 MHz
14/14
238
Description
Z80 Dual
Channel
Asynchronous
Receiver
Transmitter
SALES OFFICES
AUSTRALIA
INDIA
SINGAPORE
NSW 2027 EDGECLIFF
Suite 211, Edgecliff centre
203-233, New South Head Road
Tel. (61-2) 327.39.22
Telex: 071 126911 TCAUS
Telefax: (61-2) 327.61.76
NEW DELHI 110 001
Liason Office
c/o Diners Business Services Pvt Ltd
World Trade Tower - First Floor
Barakhamba Lane
Tel. 3314668 - 331 2840
Telex: 031 63421 DBSD IN
Telefax: 331 2830
SINGAPORE 2056
28 Ang Mo Kio - Industrial Park 2
Tel. (65) 4821411
Telex: RS 55201 ESGIES
Telefax: (65) 4820240
BRAZIL
05413 SAO PAULO
R. Henrique Schaumann 286-CJ33
Tel. (55-11) 883-5455
Telex: (39-11) 37988 "UMBR BR"
CANADA
BRAMPTON, ONTARIO
341 Main SI. North
Tel. (416) 455-0505
Telefax: 416-455-2606
CHINA
BEIJING
Beijing NO.5 Semiconductor
Device Factory
14 Wu Lu Tong Road
Da Shang Mau Wai
Tel. (861) 2024378
Telex 222722 STM CH
DENMARK
ITALY
20090 ASSAGO (MI)
V.le Milanoflori - Strada 4 - Palazzo A/4/A
Tel. (39-2) 89213.1 (10 linee)
Telex: 330131 - 330141 SGSAGR
Telefax: (39-2) 8250449
40033 CASALECCHIO 01 RENO (BO)
Via R. Fucini, 12
Borgarfjordsgatan, 13 - Box 1094
Tel.: (46-8) 7939220
Telex: 12078 THSWS
Telefax: (46-8) 7504950
Tel. (39-6) 8443341/2/3/4/5
Telex: 620653 SGSATE I
Telefax: (39-6) 8444474
JAPAN
KOREA
94253 GENTILLY Cedex
SEOUL 121
8th floor Shinwon Building
823-14, Yuksam-Dong
Kang-Nam-Gu
Tel. (82-2) 552-0399
Telex: SGSKOR K29998
Telefax: (82-2) 552-1051
HONG KONG
WANCHAI
22nd Floor - Hopewell centre
183 Queen's Road East
Tel. (852-5) 8615788
Telex: 60955 ESGIES HX
Telefax: (852-5) 8656589
Calle Albacete, 5
Tel. (34-1) 4051615
Telex: 27060 TCCEE
Telefax: (34-1)4031134
00161 ROMA
Via A. Torionia, 15
FRANCE
20, Place des Hailes
Tel. (33) 88.25.49.90
Telex: 870001 F
Telefax: (33) 88.22.29.32
28027 MADRID
SWEDEN
5-16421 KISTA
TOKYO 108
Nisseki - Takanawa Bid. 4F
2-18-10 Takanawa
Minato-Ku
Tel. (81-3) 280-4121
Telefax: (81-3) 280-4131
67000 STRASBURG
~~~~1p~~o~~~~fi>~I~or,
5'" Door
Tel. (34-3) 2022017-2020316
Telefax: (34-3) 2021481
Tel. (39-51) 591914
Telex: 512442
Telefax: (39-51) 591305
2730 HER LEV
Herlev Torv, 4
Tel. (45-2) 94.85.33
Telex: 35411
Telefax: (45-2) 948694
7 - avenue Gallieni - BP. 93
Tel.: (33-1) 47.40.75.75
Telex: 632570 STMHQ
Telefax: (33-1) 47.40.79.10
SPAIN
NETHERLANDS
5612 AM EINDHOVEN
Dillenburgstraat 25
Tel.: (31-40) 550015
Telex: 51186
Telefax: (31-40) 528835
SWITZERLAND
1218 GRAND-SACONNEX (GENEVA)
Chemin Franois-Lehmann, 18/A
Tel. (41-22) 7986462
Telex: 415493 STM CH
Telefax: (41-22) 7984869
TAIWAN
TAIPEI
12th Floor
571, Tun Hua South Road
Tel. (886-2) 755-4111
Telex: 10310 ESGIE TW
Telefax: (886-2) 755-4008
UNITED KINGDOM and EIRE
MARLOW, BUCKS
Planar House, Parkway
Globe Park
Tel.: (44-628) 890800
Telex: 847458
Telefax: (44-628) 890391
SALES OFFICES
NEW JERSEY
Voorhees - (609) 772-6222
U.S.A.
NORTH & SOUTH AMERICAN
MARKETING HEADQUARTERS
1000 East Bell Road
Phoenix, AZ 85022·2699
(1 )·(602) 867·6340
SALES COVERAGE BY STATE
ALABAMA
Huntsville· (205) 533·5995
OREGON
Tigard - (503) 620-5517
TEXAS
Austin - (512) 339-4191
Carrollton - (214) 466-8844
WASHINGTON
Seattle - (206) 524-6421
FOR RF AND MICROWAVE
POWER TRANSISTORS CONTACT
THE FOLLOWING REGIONAL
OFFICES IN THE U.s.A
ARIZONA
Phoenix· (602) 867·6340
CALIFORNIA
Hawthorne - (213) 675-0742
CALIFORNIA
Irvi ne - (714) 250-0455
San Jos - (408) 452-8585
NEW JERSEY
Totowa - (201) 890-0884
COLORADO
Boulder (303) 449-9000
PENNSYLVANIA
Montgomeryville - (215) 362-8500
GEORGIA
Norcross - (404) 242-7444
ILLINOIS
Schaumburg - (708) 517-1890
TEXAS
Carrollton - (214) 466-8844
MARYLAND
Columbia - (301) 995-6952
WEST GERMANY
6000 FRANKFURT
Gutleutstrabe 322
Tel. (49-69) 237492
Telex: 176997689
Telefax: (49-69) 231957
Teletex: 6997689=STVBP
8011 GRASBRUNN
Bretonischer Ring 4
Neukeferloh Technopark
Tel.: (49-89) 460060
Telex: 528211
Telefax: (49-89) 4605454
Teletex: 897107=STDISTR
3000 HANNOVER 1
Eckenerstrasse 5
Tel. (49-511) 634191
Telex 175118418
Teletex: 5118418 csfbeh
Telefax: (49-511) 633552
8500 NORNBERG 20
Erlenstegenstrasse, 72
Tel.: (49-911) 597032
Telex: 626243
Telefax: (49-911) 5980701
5200 SIEGBURG
Frankfurter Str. 22a
Tel. (49-2241) 660 84-86
Telex: 889510
Telefax: (49-2241) 67584
MASSACHUSSETIS
Waltham - (617) 890-6688
7000 STUTIGART
Oberer Kirchhaldenweg 135
Tel. (49-711) 692041
Telex: 721718
Telefax: (49-711) 691408
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS·THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all informations previously supplied.
Cover deSign by Keit & Koppel, Segrate, Italy
Typesetting and layout on Desk Top Publishing
by AZIMUT, Hen;n Bt., France
Printed by Garzanti, Cernusco S'/N., Italy
© 1990 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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