Z8_Family_Design_Handbook_Aug89 Z8 Family Design Handbook Aug89

User Manual: Z8_Family_Design_Handbook_Aug89

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~ZiKG
August 1989

Z8@Family
Design Handbook

, INTRODUCTION·
,,"

,

"

Zilog.was~Qun~jrr1974. and Within its first year
bl'C)Ugl)t tbmari--- PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING-REGISTER GROUP.

--

127

--.

PRE1
T1

-TMR

NOT
IMPLEMENTED

127

--.

-f--.-

GENERAL·PURPOSE
REGISTERS

SPECIFIED WORKING·
REGISTER GROUP

..

f---

THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER.

1--PORTa

P3

,2
1

PORT 2

P2

PORT 1

P1

o

PORTO

PO

Figure 5. Register File

15

'---

f----"---UOPORTs-----

Figure 6. Register Pointer

3

COUNTER/TIMERS
The MCU contains two 8-bit programmable counter/timers
(To and T1), each driven by its own 6-bit programmable
prescaler. The T1 prescaler can be driven by internal or
external clock sources; however, the To prescaler is driven
by the internal clock only.
The 6-bit prescalers can divide the input freqvency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IR0 4 (To) or
IROs (T1)---,is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass

mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode). The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode.
The clock source for T1 is user-definable and can be the
internal microprocessor clock (4 MHz maximum) divided by
four, or an external signal input via Port 3. The Timer Mode
register configures the external timer input as an external
clock (1 MHz maximum), a trigger input that can be
retriggerable or non-retriggerable, or as a gate input for the
internal clock. The counter/timers can be programmably
cascaded by connecting the To output to the input of T1.
Port 3 line P3fi also serves as a timer output (TOUT) through
which To, T 1 or the internal clock can be output.

1/0 PORTS
The MCU has 22 lines dedicated to input and output
grouped in four ports. Under software control, the ports can
be programmed to provide address outputs, timing, status
signals, and parallel I/O. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 0 can be programmed as an I/O port.
Port 1 can be programmed as a byte I/O port.

Port 2 can be programmed independently as input or
output and is always available for I/O operations. In addition,
Port 2 can be configured to provide open-drain outputs.
Port 3 can be configured as I/O or control lines. P3 1 is a
general purpose input or can be used for an external
interrupt request signal (IR02). P3s and P36 are general
purpose outputs. P36 is also used for timer input (TIN) and
output (TOUT) signals.

INTERRUPTS
The MCU allows three different interrupts from three
sources, the Port 3 line P31 and the two counter/timers.
These interrupts are both maskable and prioritized. The
Interrupt Mask register globally or individually enables or
disables the three interrupt requests. When more than one
interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All interrupts are vectored. When an interrupt request is
granted, an interrupt machine cycle is entered. This disables

all subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory vector
locations reserved for that interrupt. This memory location
and the next byte contain the 16-bit address of the interrupt
service routine for that particular interrupt request.
Polled interrupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs
can be masked and the Interrupt Request register polled to
determine which of the interrupt requests needs service.

CLOCK
The on-chip oscillator has a high-gain parallel-resonant
amplifier for connection to a crystal or to any suitable
external clock source (XTAL 1 = Input, XTAL2. = Output).
Crystal source is connected across XTAL 1 and XTAL2 using
the recommended capacitors (C1 ~ 15 pI) from each pin to
ground. The specifioations are as follows:

4

• AT cut, parallel resonant
•

Fundamental type, 8 MHz maximum

• Series resistance, Rs ~ 100n

INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
. as shown in the instruction summary.
IRR

Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Irr
X

DA
RA

1M
R
r

IR
Ir

RR

Symbols. The following symbols are used in describing the
instruction set.
dst

src
cc
@

SP
PC

FLAGS

RP
IMR

Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol "+-': For
example.
dst +- dst + src
indicates that the source data is added to the destination
data and the r~sult is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the following six
flags:
C
Z
S
V

o
H

.
Carry flag
Zero flag
Sign flag
Over'flow flag
Decimal-adjust flag
Half-carry flag

Affected flags are indicated by:

o
1

*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

CONDITION CODES

Value.

Mnemonic

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning.
Always true
Carry
No carry
Zero
Not zero
Plus
Minus

Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set

C= 1
C=O
Z = 1
Z=O
S=O
S= 1
V=l
V=O
Z= 1
Z=O
(S XOR V) = 0
(SXORV) = 1
[ZOR(SXORV)i = 0
[ZOR (SXORVjJ = 1
C =0
C= 1
(C = 0 AND Z = 0) = 1
(CORZ) = 1

5

INSTRUCTION FORMATS

J

OPC
do.

CCF, DI, EI, IRET, NOP,
RCF, RET, SCF
INCr

OPC

One-Byte Instructions

OPC
MODE
del/Ire
OPC
dll

OR

It ••

oldoUlre

lOR I. 1 1 01

I

CLR, CPL, DA, DEC,
DECW, INC, INCW, POP,
PUSH, RL, RLC, RR,
RRC, SRA, SWAP

OPC

MODE
Ire
dol

src
do.

OR 11 1 1 01

do.

OR 1 1 1 0
OR 1 1 1 0

Ire
do.

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM,XOR

JP, CALL (Indlract)
dst'

OPe

MODE
do.
VALUE

SRP

OPC
VALUE

MOD
OPC
do.

MODE
ore

ADC, ADD, AND,
cp, OR, SBC, SUB,
TCM, TM,XOR

MODE

OPC
lreldst

LD, LOC, LDCI

dst/src

OR ••• 0
OR ••• 0

OPC

LD

ore
do.
MODE

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

OPC

LD

dstlsrc

ADDRESS
LD
OR 11 1 1 01

cc

ore

I

do.
OPC
VALUE

,

doUCCR~ OPC

JP

rn

LD

I

OPC
DAu
DAL

DJNZ,JR

CALL

DAu
DAL

Three-Byte Instructions

1\No-Byte Instructions

Figure 7. Instruction Formats

INSTRUCTION SUMMARY

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hex)

Flags Affected
C Z S V 0 H

AddrMode Opcode
Byte
(Hex)
dst src

Flags Affected
CZSVDH

*'

CP dst,src
dSt'- src

(Note 1)

AD,

*'

DAdst
dst-OAdst

R
IR

40
41

*' * *'

-**' 0--

DECdst
dst-dst - 1

R
IR

00
01

-**'*--

06
04

------

,DECWdst
dst-dst - 1

RR
IR

80
81

-***,--

EF

*-----

8F

----,--

rA
r=O-F

------

ADCdst,srQ
dst-dst + src + C

(Note 1)

10

*' *' *' *'

o

ADDdst,src
dst - dst + src

(Note 1)

00

*' *' *' *'

o

ANDdst,src
dst - dst AND src

(Note 1)

50

CALLdst
OA
SP-SP - 2
IRR
@SP - PC; PC - dst
CCF
C-NOTC
CLRdst
dst-O

R
IR

BO
B1

------

COMdst
dst-NOTdst

R
IR

60
61

-**0--

6

Instruction
and Operation

01
IMR(7)-0
DJNZr,dst
RA
r-r-1
if r #"0
PC-PC + dst
Range: +127, -128

*' *' *'

*,--

x--

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

Addr Mode Opcode Flags Affected
Byte
dst src
(Hex) ICZSVDH

EI
IMR(7)-1

INCWdst
dst-dst + 1

rE

r= 0- F

R

20

IR

21

cD
c=O-F

IRR

30

r
R

1m
R

X

C7

r
Ir
r
R
IR

07

1M
1M
R

E6
E7
F5

IR
IR

E5

r
Irr

Irr

C2

LDCI dst,src
dst·- src
r-r + 1; rr-rr + 1

Ir
Irr

Irr
Ir

C3

POPdst
dst-@SP;
SP-SP + 1

R
IR

50

PUSHsrc
SP -SP - 1; @SP":-src

R
IR

(Note 1)

,

1m
(Note 1)

5?

R
I'D'IIR

* * .* *
****-****--

3D
OF

1-----

DO
01

*** 0

31

20
FO
F1

TCM dst,src
(NOT dst) AND src

(Neite 1)

60

TM dst,src
dstANO src

(Note 1)

70

XORdst,src
dst - dst XOR src

(Note 1)

BO

FF

40

****--

X**X--

For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.

03

(Note 1)

ORdst,src
dst - dst OR src

c

CZSVDH

NOTE 1: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expfessed
symbolically by a D in this table, and its value is found in the
following table to the right of the applicable addressing mode
pair.

02

NOP

CO
C1

'IR

LiiJ W'IRR

SWAPdst

E4

LDC dst,src
dst-src

,

SUBdst,src
dst - dst - src

E3
F3

EO

l{ri:ciJ R

SRPsrc
RP-src

r9
0 - F

r

,

SBC dst,src
dst-dst-src-C

SRA dst

rC
r8

X

R

E1

SCF
C-1

cB
c=O-F

r =

rIr
R
R

l[ric lciJ
R
,
,
IR
c

OA

10
11

,

Flags Affected

91

IR

c

RRC dst

******

90

RLCdst~R

RR dst

IR

JRcc,dst
RA
ifcc is true,
PC-PC + dst
Range: + 127, -128
LD dst,src
dst-src

-***--

RR

IRET
BF
FLAGS - @SP; SP - SP + 1
PC-@SP;SP-SP + 2; IMR(7)-1
JPcc,dst
ifcc is true
PC-dst

RLdst c~ R
~IR

9F

INCdst
dst-dst + 1

Addr Mode Opcode
Byte
dst src
(Hex)

Instruction
and Operation

AddrMode
dst

src

R

R

R

IR

Lower
Opcode Nibble

Ir

70
71

RCF
C-O

CF

RET
PC-@SP;SP-SP+ 2

AF

0-----

R

1M

IR

1M

7

REGISTERS (Continued)
R248P01M
PORT 0 AND 1 MODE REGISTER
(F8H; Write Only)

P04-PO, =
MODE
OUTPUT
00
INPUT", 01

~
l~~
~
L

RESERVED

,

R252 FLAGS
FLAG REGISTER
(FCH; Read/Write)

1 LUS~RFLAGF1

PO.-PO,
MODE
00 '" OUTPUT
01, '" INPUT

,

S{A;~N~~~~C;~ON
P10·P17 MODE

lli!~~

~USER flAG F2

.

00 '" BYTE OUTPUT
01 ", BYTe INPUT
11 '" HIGH·IMPEDANCE

II

DON'T CARE

II.

R253 RP
REGISTER POINTER
(FDH; Read/Write)

['NTERRUPT
GROUP
RESERVED",
000 PRIORITY
452 001
524 = 010
542 = 011
245 = 100
425 = 101
254 = 110
RESERVED 111

=

REGISTE'R

POINTER

=

DON'T CARE

R250lRQ
INTERRUPT REQUEST REGISTER
(FAH; Read/Write)

R255SPL
STACK POINTER
(FFH; Read/Write)

I~I~I~I~I~I~I~I~I

RESERVED

==r-

c=

IRQ2 '" P311NPUT (02
IRQ4

= T(I

=IROS)

IRQ5 '" T1

R2511MR
INTERRUPT MASK REGISTER
(FBH; Read/Write)

I'

c=

1 ENABLES IRQo·IR05
(Do::: IROO)

L-------RESERVED

' - - - - - - - - - 1 ENABLES INTERRUPTS

Figure 8. Control Registers (Continued)

8

SIGN FLAG
CARRY FLAG

I~I~I~I~I~I~I~I~I

~_,,:J

OVERFLOW FLAG

ZERO .FLAG

os

R2491PR
INTERRUPT PRIORITY REGISTER
(F9H; Write Only)

DON'T CARE

HALF CARRY FLAG

DECIMAL ADJUST flAG

OPCODEMAP
Lower Nibble (Hex)

7

A

--- _.- _._--

~---6.5
6.5

--

o
121100-

E

6.5

6.5

6S

12110 S

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

LD

JP

INC

R,

IR,

f1 f2

f1·lr2

R2·Rl

IR2·R,

R,.IM

IR,.IM

f1 R2

f;?,R 1

f1 RA

cc RA

fllM

cc DA

r1

6S

6.5

6S

6.S

10.S

10.S

1O.S

1O.S

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR"IM

10.5

lOS

R,

IR,

f1· r2

f1, lr 2

R2,R,

IR2,R,

R,IM

6S

6,S

6,S

6,S

10,S

1O,S

la,S

lO.S

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR"IM

6.5

12110 Q

C

DEC

10.5

10 5

B
-_.-

65

F

6S

c----f----~

4

6

i

e.
J!

,Q
,Q

z

R,

IR,

f1· f 2

f1, lr2

R2,R,

IR2,R,

R"IM

80

6,1

6,5

6,5

10,5

10.5

1O,S

la,S

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

1M

rl J 2

f1, lr2

R2,R,

IR2,R,

IR"IM

8,S

8,S

6,S

6,S

10,S

10,S

R IM
"
1O,S

DA

DA

OR

OR

OR

OR

OR

OR

R,

IR,

f1,f2

f1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

1O,S

10,5

6,S

6,S

10,5

10,5

10,5

1O,S

POP

POP

AND

AND

AND

AND

AND

AND
IR"IM

R,

IR,

f1· f 2

f1, lr2

R2,R,

IR2,R,

R"IM

6,S

6,5

6,5

10,5

10,5

10,5

1O,S

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R,

IR,

f1· r2

f1, lr2

R2·R,

IR2·R,

R,.IM

IR"IM

10112.1

12114,1

6,S

6,5

10,S

10,5

10.5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

f,J2

f1·lr2

R2,R,

IR2,R,

R IM
"

IR"IM

R2

IR2
1O,S

DeCW

DECW

RR,

IR,

6.5

6,S

-----

:;;

0.
0.

::>

A

B

C

o
E

RL

RL

R,

IR,

f---

I
I

H

1O,S

6,S

10,5

r-----

f----

I-------

r-----

r---s;-01

r----6.1
'EI

10,5

1O.S

INCW

INCW

CP

CP

CP

CP

CP

CP

RR,

IR,

f1 J2

f,.lr2

R2,R,

IR2,R,

R,IM

IR"IM

6S

6.5

10.5

10,5

10,S

r-----

lOS

14

°

RET

6,5

6,S

6,S

6,S

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

~I
IRET

R,

IR,

rl J 2

f1·lr2

R2,R ,

IR2,R,

R,.1M

IR IM
"
10,5

r----6.5

LD

RCF

~

6,5

6.5

12,0

18,0

RRC

RRC

LDC

LOCI

R,

IR,

r,.lrr2

Ir1,lrr2

1O.S

10 5

10,5

f, ,x.R2

6,5

6,5

12,0

18,0

20.0

20,0

10,5

SRA

SRA

LDC

LOCI

CALL"

CALL

LD

R,

IR,

f2, lrr 1

Ir2,lrr1

IRR,

DA

'r2,x.R,

6,S

6,5

6,5

10,5

10,5

10 S

1O,S

r----65

RR

RR

LD

LD

LD

LD

LD

CCF

R,

IR,

r" IR 2

R2,R,

IR2·R,

R,.IM

IR"IM

85

8.5

6,S

10,S

SWAP

SWAP

LD

LD

R,

IR,

Ir1·f2

R2·IR,

SCF

~
NOP

'-...- - - -....v ...----""~ ......- - - -....v ...----"".1 . . . - - - - -.. . . . . . .-----""~ "-v--"~
3
Bytes per Instruction

LOWER
OPCODE
NllLE
EXECUTION
CYCLES
UPPER
OPCODE_A
NIBBLE
FIRST
OPERAND

PIPELINE
CYCLES

MNEMONIC

Legend:
R = 8-bit address
r = 4,blt address
Rl or f1 = 05t address
R2 or f2 = Src address
Sequence:
Opcode, First Operand, Second Operand

SECOND
OPERAND

NOTE' The blank areas are not defined

• 2-byte instruction, letch cycle appears as a 3-byte instruction

9

REGISTERS
R241 TMR
TIMER MODE REGISTER
(F1 H; Read/Write)

NOT T,",
USEDMODES
= 00

i~ g~i ~ ~~

~ llS~o

~

1 ::
= NO
LOAD
'"NCTION
To

INTERNAL CLO. CK OUT:: 11
T MODES
EXTERNAL CLOCK tNplOr :: 00
GATE INPUT:: 01

(NON.R1~~~g~:~::~~) =
TRIGGER INPUT

R245PREO
PRESCALER 0 REGISTER
(Ft/H; Write Only)

0::
1 '"
0 ::
1 '"
0 =

,

10

1

DISABLE To COUNT
ENABLE To COUNT
NO FUNCTION
LOAD 11
DISABLE t, COUNT

= ENABLE

~L

COUNTMODE
o=

To SIN. GLE·PASS
1 '" To MODULO·N

RESERVED

PRESCALE'R MODULO
(RANGE: 1-64 DECIMAL

T, COUNT

01-00 HEX)

= 11

(RETRIGGERABLE)

R242 T1
COUNTER TIMER 1 REGISTER
(F2H; Read/Write)

R246P2M
PORT 2 MODE REGISTER
(F6H; Write Only)

1\

T, INITIAL VALUE (WHEN WRITTEN)
'-'----(RANGE 1 256 DECIMAL 01 00 HEX)
T, CURRENT VALUE (WHEN READ)

R243 PRE1
PRESCALER 1 REGISTER
(F3H; Write Only)

~L
.

R247P3M
PORT 3 MODE REGISTER
(F7H;Write Only)

I L
L

~~

COUNTMODE
o ::: T, SINGlE·PASS
1 "" T, MODULO·N
CLOCK SOURCE)
1 :::: T, INTERNAL
0 = .T1 EXTERNAL TIMING INPUT
(TIN) MODE
PRESCALER MOOULO

(RANGE:

1~64

o PORT 2 PULL UPS OPEN DRAIN
1 PORT 2 PULL-UPS ACTIVE
RESERVED
RESERVED
RESERVED

o P31

DECIMAL

01-00 HEX)

'" INPUT (TIN) P36 '" OUTPUT (TOUT)

RESERVED
L-_ _ _ _ _ _ _ _ RESERVED

R244 TO
COUNTER/TIMER 0 REGISTER
(F4H; Read/Write)

To INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1 256 DECIMAL 01 00 HEX)
To CURRENT VALUE (WHEN READ)

Figure 8. Control Registers

10

Figure 9. Timing

AC CHARACTERISTICS
Timing Table

Z8600
Number

?

Symbol

Parameter

Min

Max

TpC

Input Clock Period

125

TrC.TIC

Clock Input Rise and Fall Times

1000
25

Notes'

3

TwC

Input Clock Width

37

1

4

TwTinL

Timer Input Low Width

100

2

5

TwTinH

Timer Input High Width

3TpC

2

6

TpTin

Timer InputPeriod

BTpC

7

TrTin,TfTin

Timer Input Rise and Fall Times

B

TwlL

Interrupt Request Input Low Time

100

2,3

9

TwlH

Interrupt Request Input High Time

3TpC

2.3

2

100

2

NOTES:
1. Clock timing references use3.8Vfor a logic "1" and 0.8Vfor a logic "0':
2. Timing references use 2.0Vfor a logic "1" and 0.8V for a logic "0':
3. Interrupt request via Port 3 (P31·P33)'
• Units in nanoseconds (ns).

11

ABSOLUTE MAXIMUM RATINGS
Voltages On all pins with respect
toGND ......................... -O.3Vto +7.0V
Operating Ambient
Temperature .....
. .. See Ordering Information
Storage Temperature ..
.......... -65°C to + 150°C

Stresses greater than those listed-under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extendep periods may affect
device reliability.

STANDARD TEST CONDITIONS

+5V
2.1K

The DC characte\risticslisted below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are:
•

+4.75V~ Vee~ +5.25V

•

GND =OV
Figure 10. Test Load 1

DC CHARACTERISTICS

Symbol

Parameter

Min

Max

Unit

Condition

3.8

Vee

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

2.0

Vee

V

-0.3

0.8

V

3.8

Vee

V

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

. 2.4

VOL

Output Low Voltage

III

Input Leakage

'OH

Output Drive Current

IOl

Output Leakage

IIR

Reset Input Current

lee

Vee Supply Current

150

mA

VeH

Clock Input HighVoltage

Vel

Clock Input Low Voltage

VIH

Input High Voltage

Vil

Input low Voltage

VRH

Reset Input High Voltage

VRl

12

0.4
-10

10

IOH

V

IOl

= -250,..A
= +2.0 mA

,..A

OV <> VIN <>+ 5.25V

rnA
!LA

VOH
VOH

10

,..A

OV <> VIN <> + 5.25V

-50

,..A

Vee

1.5
2.50
-10

V

=

= +2.4V
= +4'.OV
+ 5.25V, VRl

= OV

~ ZiIill

Product Specification

June 1987

Z860VZ8603

Z861VZ8613 Z8®
2'8601 Single-Chip MCU with 2K ROM
28603 Prototyping Device with 2K EPROM Interface
Z8611 Single-Chip MCU with 4K ROM
Z86l3 Prototyping Device with 4K EPROM Interface

Features

General
Description

• Complete microcomputer, 2K (8601) or 4K
(8611) bytes of ROM, 128 bytes of RAM, 32
I/O lines, and up to 62K (8601) or 60K (8611)
bytes addressable external space each for
program and data memory.

• Full-duplex UART and two programmabla
8-bit counter/timers, each with a 6-bit
programmable prescaler.
• Register Pointer so that short, fast instructions can access any of nine working register
groups in I /LS.

• 144-byte register file, including 124 generalpurpose registers, four I/O port registers,
and 16 status and control registers.

• On-chip oscillator which accepts crystal or
external clock drive.

• Average instruction execution time of 1.5 /LS,
maximum of 1 /LS.

• Single + 5 V power supply-all pins TTL
compatible.

• Vectored, priority interrupts for I/O,
counter/timers, and UART.

• 12.5 MHz.

The 28 microcomputer introduces a new level
of sophistication to single-chip architecture.
Compared to earlier single-chip microcomputers, the 28 offers faster execution; more
efficient use of memory;' more sophisticated
interrupt, input/output and bit-manipulation
capabilities; and easier system expansion.
Under program control, the 28 can be tailored
to the needs of its user. It can be configured as a

PORTO
(NIBBLE
PROGRAMMABLE)
1/0 OR Ae-A15

PORT 1

(BYTE
PROGRAMMABLE)
1/0 OR ADo-AD7

PORT 2
(BIT PRO·
GRAMMABLE) ,
110

PORT 3
SERIAL AND

PARALLEL 110
AND CONTROL

stand-alone microcomputer with 2K or 4K bytes
of internal ROM, a traditional microprocessor
that manages up to 124K bytes of external
memory, or a parallel-processing element in a
system with other processors and peripheral
controllers linked by the 2-BUS® bus. In all
configurations, a large number of pins remain
available for I/O.

+5V

P3,

XTAL2

P3,

XTAL1

P2,

P'37

P2,

P30

P2,

FIESE'f

P2,

R/W

P2,

os

P2,

AS

P2,

P3,

P20

GND

P3,

P3,

P3,

po,
po,

P1,

P1,

-:'02

P1,

po,
po,

P1,

PO,

P1,

po,
po,

P1,

P1,

P1,

Figure 2a. 40-pin Dual-In-Line Package (DIP).
Pin ASSignments

13

Pin
Description

program execution begins from internal
program location OOOCH. '

AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginningofeach machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed in the r.igh-impedance state along with
Ports 0 and 1, Data Strobe and Read/Write.

ROMless. (input, active LOW). This pin is only
available on the 44 pin version of the Z8611,
When connected to GND disables the internal
ROM and forces the part to function as a Z8681
ROM less Z8. When left unconnected or pulled
high to Vcc the part will function normally as a
Z8611.

OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

R/W. Read/Write (output). R/W is Low when
the Z8 is writing to external program or data '
memory.
XTALl. XTAL2. Crystall, Crystal 2 (time-base
input and output). These pins connect a parallel
resonant 12.5 MHz crystal or an external singlephase 12.5 MHz clock to the on-chip clock
oscillator and buffer.

POO-P07' Plo-PI7. P2o-P27' P30-P37' I/O Port
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports
that can be configured under program control
for I/ 0 or external memory interface.

RESET. Reset (input, active Low). RESET initializes the 28. When RESET is deactivated,
'Y.... '::v~

~(j <1,,,. ' <1,'1-'41-" ~ 0"_

-

(Lower Byte)

IRQ5

(Upper Byte)

•

•

IRQ3
IRQ2

zaem=I---------I:Z8611

IRQ2
IHQ1

IH01

NOT ADDRESSABLE

IRQO
IRQO

Figure 4. Pr"gram Memory Map

......
......
......
...
...

LOCATION

261

IDENTIFIERS

STACK POINTER BITS 7-0)

SPL

STACK pOINTER (BITS 15-8)

SPH
RP

REGISTER POINTER
PROGRAM CONTROL FLAGS
INTERRUPT MASK REGISTER
INTERRUPT REQUEST REGISTER

INTERRUPT PRIORITY REGISTER
PORTS 0-1 MODE

247

PORTa MODE

'45
24.

PORT 2 MODE
TO PRESCALER
TIMERICOUNTER 0

'43

.42

...
241

T1 PRESCALER
TtMERICOUNTER 1
nMER MODE
SERIAL UO

FLAGS

IMR
IRQ
IPR
P01M
P3M
P3M
PR..
TO
PRE1
Tl

TMR
SIO

NOT

IMPLEMENTED
127

--{

PORT 1

.,

PORTO

PO

PORT 3
PORT 2

Fig.... 6. The Reglater FUe

PO

PO

r,.r.ri r4

0000

...
...

I'63
~,

The upper nibble of the register tile addl'8S8

>--- provided by the register pointer specllies

-----

the active wortdng.reglster woup.

-----

,.7

The lower
nibble of
the register

r--'
GENERAL·PURPOSE
REGISTERS

16

, Figure 5. Data Memory Map

SPECIFIED WORKING·
REGISTER BROUP

1118_

-I- provided by

the.lns1rUcllon
points to the
specllied

register.

,.
-----.0..;;,;;:;.----- :
Figure 7. The Reglater P"lnt82
2037·004, 005, 006, 007

,divided into nine working-register groups, each
occupying 16 continguous locations (Figure 6).
The Register Pointer addresses the starting
location of the active working-register group.
Stacks. Either the internal register file or the
external data memory can be used for the stack.
Serial
Input/
Output

Port 3 lines P30 and P3z can be programmed as
serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The bit rate
is controlled by CounterlTimer 0, at 12 MHz.
The Z8 automatically adds a start bit and .two
stop bits t6 transmitted data (Figure 8). Odd
parity is also available as an option. Eight data
bits are always transmitted, regardless of parity

A 16-bit Stack Pointer (R254 and R255) is used for
the external stack, which can reside anywhere in
data memory between locations 2048 (8601) or
4096 (8611) and 65535. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides
within the 124 general-purpose'registers
(R4-R127).
selection. If parity is enabled, the eighth bit is
the odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight data
bits and at least one stop b\t. If parity is on, bit 7
of the received data is replaced-by a Piirity error
flag. Received characters generate the IRQ3
interrupt request.

Trcmsmltted Data

Received Data

(No Parity)

(No Parity)
I~I~I .. I.. I.. I.. I.. I.. I.. ISTI
LSTAATBIT

LSTARTBIT

' - - - - - - E l G H T DATA BITS

' - - - - - - e I G H T DATA BITS

TWO STOP BITS

l - - - - - - - - - O N E S T O P BIT

T1'CID8DIltted Data

Received Data

(With Parity)

(With Parity)

Isplspl p1.. 1.,1 •• 1D,I .,I.,! D,I STI
LST"RTBIT

T

1~lpl .. I.. I.. I.. I.. I.. I.. ISTI

,\1<---_L--~

1
' - - - - - S E V E N DATA BITS
L -_ _ _ _ _ _ _ ODDPARITY

-

TWO STOP BITS

LSTARTBIT

_ _ SEVEN DATA BITS

PARITY ERROR FLAG

l - - - - - - - - - O N E S T O P BIT

Figure 8. Serial Data Formate

Counter/
Timers

20~7-009

The Z8 contains two 8-bit programmable
counter/timers (To and Tl), each driven by its
own 6-bit programmable prescaler. The T1
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number from
1 to 64. Each prescaler drives its counter, which
decrements the value (l to 256) that has been
loaded into the counter. When the counter
reaches the end of count, a timer interrupt
request-IRQ4 (to) or IRQ5 (Tl)-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the initial value. The counters can also be programmed to stop upon reaching zero (single-

pass mode) or to automatically reload the initial
value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read any time without disturbing
their value or count mode.
The clock source for T1 is user-definable and
can be the internal microprocessor clock
divided by four, or an external signal input via
Port 3. The Timer Mode register configures the
external timer input as an external clock, a
trigger input that can be retriggerable or nonretriggerable, or as a gate input for the internal
clock. The counter/timers can be programmably
cascaded by connecting the To output to the
input of T1. Port 3 line P36 also serves as a timer
outp~t (TOUT) through which To, Tl or the internal clock can be output.

17

110 Ports

The Z8 has 32 lines dedicated to input and
output. These lines are grouped into four ports of,
eight lines each and are configurable as input,
output or address/data. Under software control,
the ports can be programmed to provide address

outputs, timi.ng, status sig;nals, serial 1/0, and
parallel VO with or without handshake. All ports
have active pull-ups and pull-downs compatible
with TTL loads.

Port 1 can be programmed as a byte 1/0 port
or as an addre~s/data port for interfacing
external memory: When used as an 1/0 port, Port
1 may be placed under handshake contro!. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY I
and DAV I (Ready and Data Available).
Memory.1ocations greater than 2048 (28601) or
4096 (Z86ll) are referenced through Port 1. To
interface external memory, Port 1 must be
programmed for the multiplexed AddresslData
. mode. If more than 256 external locations are
required, Port 0 must output the additional
lines.
Port 1 can be placed in the high-impedance
state along with Port 0, AS, DS and RIW,

allowing the Z8 to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33 as a
Bus Acknowledge input and P34 as a Bus
Request output.

Port 0 can be programmed as a nibble 1/0
port, or as an address port for interfacing
external memory..When used as an 1/0 port,
Port omay be placed under handshake con- ,
tro!. In this configuration, Port 3 lines P32 and
P3s are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the VO direction of the upper riibble
.P04-P07·
For external memory references, Port 0 can
provide address bits As-All (lm'!er nibble) or
As-AIS (lower and upper nibble) depending on
the required address space. If the address range
requires 12 bits or less, the upper nibble of Port 0
can be programmed independently ps 1/0 while

the lower nibble is used for addressing. When
Port 0 nibbles are defined as address bits, they
can be set to the highimpedance state along with
Port 1 and the control signals AS, DS and RIW.

PORT.

(I/O OR ADo-AIl,)

Z8

MCU

Figure

Z8

MCU

Figure 9b. Port 0

Port 2 bits can be programmed independently
as input or output. The port is always available
for 1/0 operations. In addition, Port 2 can be
configured to provide open-drain outputs.
Like Ports 0 and L Port 2 may also be
placed under. handshake control. In this, configuration, Port 3 lines P31 and P36 are used as
the handshake controls lines DAV2 and RDY2.
The handshake signal assignment for Port 3 lines
P3j and P36 is dictated by the direction (input or
output) assigned to bit 7 of Port 2.
Port 3 lines can be configured as 1/0 or
control lines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and'
four output (P34-P37)' For serial 1/0, lines P30
and P~ are programmed as serial in and serial
out respectively.
Port 3 can also provide the follOWing control functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four e~ternal interrupt
request signals (IRQo-IRQ3); ti,mer input and
output signals (T~nd Tour) and Data
Memoty Select (DM):
18

sa. Port I

PORT 2(110)

ZB

MCU
}

HWa~=~~ED~~NTROLS
(pa, AND P3e)

Figure Sc. Port 2

I

Z8

PORTa
(110 OR CONTROL)

MCU

Figure 9d. Port 3

2037·008

Interrupts

The 28 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out. and the two counter/timers.
These interrupts are both maskable and
prioritized. The Interrupt Mask register globally
or individually enables or disables the six interrupt requests. When more than one interrupt i~
pending, priorities are resolved by a pro'
grammable priority encoder that is controlled by
the InterruptPriority register.
All 28 interrupts are vectored: When an interrupt request is granted, an interrupt machine

cycle is entered. This disables all subsequent
interrupts, saves the Program Counter and status
flags, and branches. to the program memory
vector location reserved for that interrupt. This
memory location and the next byte contain the
16-bit address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the
interrupt inputs can be masked and the Interrupt
Request register polled to determine which of the
interrupt requests needs service.

Clock

The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl :, Input, XTAL2 = Output).
The crystal source is connected across XTALl
and XTAL2, using the recommended capacitors

(Cj :$ 15 pF) from each pin to ground. The
specifications for the crystal are as follows:
• AT cut, parallel resonant
• Fundamental type, 12.5 MHz maximum
• Series resistance, Rs :$ 100 n

19

Z860S/IS
Protopack
Emulator

The Z8 Protopack 'is used for prototype
development and preproduction of maskprogrammed applications; The Protopack is a·
ROMless version of the standard 28601 or Z8611
housed in a pin-compatible 40-pin package
(Figure 11).
To provide pin compatibility and interchangeability with the standard maskprogrammed
device, the Protopack carries piggy-back a 24pin socket for a direct interface to program
memory (Figure 1). The 28603 24-pin socket is
equipped with 11 ROM address lines, 8 ROM
data lines and necessary control lines for inter. face to 2716 EPROM for the first 2K bytes of program memory. The 28613 24-pin socket is
.

Figure n. The Z8 Microcomputer Protopack Emulator

Instruction
Set
Notation

AddresSing Modes. The follOWing notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.

IRR
Irr
X

DA
RA
1M
R

m
Ii
RR

Indirect register pair or indirect working-register
\
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Symbols. The follOWing symbols are used in
describing the instruction set.
dst
src
cc
SP

Destination location or contents
Source location or contents
Condition code (see list)
Indire.ct address prefix
Stack pOinter (control registers 254-255)

PC

Program counter

@

FLAGS Flag register (control register 252)
RP
Register pOinter (control register 253)
IMR

20

Interrupt mask register (control register 251)

equipp'ed with 12 ROM address lines, 8 ROM
data lines and necessary control lines lor interface to 2732 EPROM for the first 4K bytes of '
program memory.
Pin compatibility allows the usar to design the
pc board for a final 40-pin maskprogrammed
28, and, at the same time, allows the use of the
Protopack to A > B '" 001
A > B > C = 010
,A>C>B=Dl1

IR03, IRQ5 PRIORITY (GROUP A)
IRQ5 > IR03
1 = IRQ3> IRQ5

o '"

LoON'TCARE

"
REOISTER
POINTER

B>C>A=I00

C > B > A ;;; 101
B > A > C :; 110
RESERVED 0: 111

IROO, IRQ2 PRIORITY (GROUP B)
o = IR02 > IROO
1 '" IROO > IR02
IRQ1, IRQ4 PRIORITY (GROUP C)
IRQ1 > IRQ4
1 '" IRQ4 > IRa1

o '"

R2S0 mQ
Interrupt Request Register
(F AH ; Read/Write)

R2S4 SPH
Stack Pointer
(FEH ; Read/Write)

I~I~I~I~I~I~I~I~I
RESERVED

C==-I~QO

T

IRQ1

IRQ2
IRQ3
IRQ4
IRQS

P32 INPUT (Do

=IRQO)

P331NPUT
P311NPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
T,

R25IIMR
Interrupt Mask Regl.ter
(FBH; Read/Write)

R2SS SPL
Stack Pointer
(FFH; Read/Write)

I~I~I~I~I~I~I~I~I

II

c==-

1 ENABLES IRaO-IRQS
IRaO)

(Do =

' - - - - - - - RESERVED

' - - - - - - - - 1 ENABLES INTERRUPTS

Figure 13. Control Registers (Continued)

24

2037·014

Opcode

Lower Nibble (Hex)

Map

o
o

2

3

•
5

..

e"

~
:!!
:z:
~

'"'"

6

7

8

::>

A

B

C

D

E

F

5

6

7

8

9

A

B

C

D

6,5

6,5

6,5

10,5

10,5

10,5

10,5

6,5

6,5

12/10,5

12/10,0

6,5

12/10,0

6,5

DEC
IR>

ADD

ADD

ADD

LD

JP

Il,H2

Iz,Rl

DJNZ
n,RA

JR

H2,Hl

ADD
IR>,IM

LD

n,Ir2

ADD
R>,IM

LD

Il,12

ADD
IR2,R>

ca,BA

[1, 1M

cc,DA

INC
n

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RLC
R>

RLC
IR>

ADC

ADC

ADC

11,12

Il,IrZ

Hz,Hl

ADC
JR2,R>

ADC
R>,IM

ADC
IR>,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC
R>

INC
IR>

SUB

SUB

SUB

II, [2

II, lr2

SUB
R2,R>

SUB
R>,IM

SUB
IR>,IM

8,0

6,1

6,5

6,5

10,5

10,5

10,5

10,5

IP
IHR>

SRP
1M

SBC

SBC

ll,I2

Il/h2

SBC
R2,R>

SBC
JR2,R>

SBC
R>,IM

SBC
IRl,!M

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA
R>

DA
IR>

OR

OR

II, 12

l1,It2

OR
R2,R>

OR
IR2,R>

OR
R>,IM

OR
IR>,IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP
R>

POP
IR>

AND

AND

Il,12

Il,lIZ

AND
R2,R>

AND
IR2,R>

AND
R>,IM

AND
JRl,!M

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM
R'l

COM
IR>

TCM

TCM

II, I2

TCM
JR2,R>

TCM
R>,IM

TCM
IR>,IM

1R2,Rl

Il1hz

TCM
R2,R>

10/12,1 12/14,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH
R2

PUSH
IR2

TM

TM

11.12

TM
n,Irz

TM
JR2,R>

TM
Rl,!M

TM
IR>, 1M

10,5

10,5

12,0

18,0

OECW DECW LDE
n,Iuz
IR>
HR>
6,5

12,0

R2,R>

r--r--r--r--r--r--6,1

LDE!

01
!"-"-:-

III,IIlZ

18,0

RL
LDE
LDE!
IR>
Irn 1r2,lrn
6,5
10,5
10,5
10,5
6,5
INCW !NCW
CP
CP
CP
n,lz
II,Iu
RR>
R2,R>
JR>
6,5
6,5
6,5
6,5
10,5
CLR
XOR
XOR
XOR
CLR
I1,I2
IR>
Il1 h Z
R2,R>
R>
6,5
6,5
12,0
18,0
RRC
RRC
LDC
LDCI
II, lrrz Irl,IrU
R>
JR>
6,5
6,5
IB,O
20,0
12,0
SRA
SRA
LDC
LDCI CALL*
12,Irn lIZ, hIl IRR>
R>
IR>
6,5
6,5
6,5
10,5
RR
RR
LO
LD
IR>
II,
lr2
R2,R>
R>
8,5
6,5
8,5
SWAP SWAP
LD
IR>
R>
Irl,tz

'I

.,;

-

6,1

RL
R>

V'

F

E

6,5

....
Bytes per
Instruction

•

3

DEC
R>

6,5

9

2

10,5
CP
IR2,R>
10,5
XOR
JR2,R>

10,5
CP
R>,IM

E!
!"-"-:-

10,5

14,0

CP
JR>,IM

10,5

10,5

XOR
R>,IM

XOR
IR>,IM

RET

r--16,0

IRET
'-----

10,5

6,5

LD
II,

RCF

x, Hz

20,0

10,5

r---

CALL
DA

LD
I2, X, HI

SCF

10,5

10,5

10,5

LD
JR2,R>

LD
R>,IM

LD
IR>,IM

6,5

r--6,5

CCF

r----

10,5

6,0

LD
R2,IRf

....

'V"
3

NOP

.I

....'---------~~~--------~.,; ~ ~
2

3

Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode-A
Nibble
First
Operand

••

Pipeline
Cycles

Mnemonic

Second
Operand

Legend:
R = 8-Bit Address
r = 4-Bit Address
RI or II = Dst Address
Rz or 12 = Src Address

Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.

*2-byte instruction; fetch cycle appears as a 3-byte instruction
8085-002

25

Absolute
Maximum
Ratings

Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition ab9ve those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

The DC characteristics listed below apply for
the following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin.
Standard conditions are:

+5V
2.1K

o +4.75 V ~ Vee ~ +5.25 V
= 0 V
o O°C ~ TA ~ +70°C

o GND

Figure 14. Tesl Load 1

DC
Characteristics

26

·Symbol

Parameter

Min

Max

Unit

VeH

Clock Input High Voltage

3.8

Vee

V

Driven by External Clock Generator

VeL

Clock Input Low Voltage

-0.3

0.8

V

Driven by External Clock Generator

VIH

Input High Voltage

2.0

Vee

V

VIL

Input Low Voltage

-0.3

0.8

V

VRH

Reset Input High Voltage

3.8

Vee

V

VRL

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

VOl

Output Low Voltaoe

IlL

Input Leakage

IoL

Output Leakage

IIR
lee

2.4

V

Condition

IoH

= -250 /LA

0.4

VIOL = +2.0 rnA

-10

10

/LA

0 Vs Vms +5.25 V

-10

10

p.A

0 Vs VIN s +5.25 V

Reset Input Current

-50

/LA

Vee

Vee Supply Current

150

rnA

=

+5.25 V, VRL

=0V

AC Characteristics
External I/O
or Memory
Read and
Write Timing

RlW
PORT 0,

6M

PORT 1

I----(Q))---+-I
iii

----------r_------il-------~Q)~---~I~----r_---

(READ)

00-07 OUT

PORT 1

iii
(WRITE)

Figure 15. External I/O or Memory Read/Write

No.

Symbol

Parameter

Min

50
60

TdA(AS)

Address Valid to AS t Delay

2

TdAS(A)

AS t to Address Float Delay

3

TdAS(DR)

AS t to Read Data Required Valid

4

TwAS

AS Low Width

5

TdAz(DS)

Address Float to DS ~

8MHz
Max

12.5 MHz
Min
Max

Notes*to
2,3

35

2,3

45
220

320
80
0

55

1,2,3
1,2,3

0

6-TwDSR

DS (Read) Low Width

250

185

1,2,3

7

TwDSW

DS (Write) Low Width

160

110

1,2,3

8

TdDSR(DR)

DS ~ to Read Data Required Valid

9

ThDR(DS)

Read Data to DS t Hold Time

0

0

10

TdDS(A)

DS t to Address Active Delay

80

45

2,3

11

TdDS(AS)

DS t to 'AS ~ belay

70
50

55

2.3

30

2,3

60
50

35

2,3

35

2,3

80

45

200

12 - TdRIW(AS) - - R/W Valid to AS t Delay
13

TdDS(RIW)

DS t to R/W Not Valid

14

TdDW(DSW)

Write Data Valid to DS (Write)

15

TdDS(DW)

DS t to Write Data Not Valid Delay

16

TdA(DR)

Address Valid to Read Data Required Valid

17

TdAS(DS)'

AS t to DS

~

Delay

~

Delay

130

410
80

1,2,3

2,3
255

55

1,2,3
2,3

NOTES:

1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
$3. See clock cycle time dependent characteristics table.

2194-011

t Test Load 1.
o All timing references use 2.0 V for a logic \II" and 0.8 V for a logic "0".
* All units in nanoseconds (ns).

27

AC Characteristics
Additional
Timing
Table

Figure 16. Additional Timing

8 MHz

No.

Symbol

Parameter

Min

TpC

Input Clock Period

125

2

'IrC,TIC

Clock Input Rise And Fall Times

3
4

TwC
TwTinL

Input Clock Width
Time Input Low Width

1000

80

1000

15
26

1

100

70

2

3TpC
8TpC

2

,

NOTES:
1. Clock timing references uses 3.8 V for a logic "1" and 0.8 V for
a logic "0",

100

2
2

100

3TpC

70
3TpC

3TpC

3TpC

2,3
2.4
2,3

3. Interrupt request Via Port 3 (P31-P33)'
4. Interrupt request vi. Port 3 (P30).
• Units in nanoseconds (ns).

2. Timing reference uses 2.0 V for a logic "1" and 0.8 V for
a logic "0".

X'-'______

-:--AD_DR_ESS_V_AL_'D_ _ _ _ _ _

0~~~~~j~.c

__
- -_
- -_
J T-_-.______

Do-D.,

Notes*

37

5 - TwTinH - - - Timer Input High Width ------~3TpC
TpTin
Timer Input Period
8TpC
'IrTin, TfTin
Timer Input Ris\'! And Fall Times
100
8a
TwIL
Interrupt Reque~t Input Low Time
8b
TwIL
Interrupt Request Input Low Time
Interrupt Request Inp,ut High Time
9
TwIH

Ao-A ••

Min

25

6
7

Memory Port
Timing

12.5 MHz
Max

Max

DON'T CARE

~

k=

~L"

~

DATA IN VALID

Figure 17. Memory Pori Timing

No.

2

Symbol

Parameter

TdA(DI)

Address Valid to Data Input Delay

ThDI(A)

Data In Hold time

NOTES:
I. Test Load 2.
2. This is a Clock-eycle-Dependent parameter. For clock frequencies
other than the maximum, use the following formula: !:} TpC - 95

28

Min

Max

Notes*

320

1,2

o
"'Units are nanoseconds unless otherwise specified.

'2194-012 2037-019

Handshake

..~~ ----------~~-'---~~~,.
~~---------

Timing

" q>' -¢''t'-¢''t' x~ 4'"

ADDRESS/DATA OR 110·
(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

31

ARCHITECTURE
Z8671 architecture is characterized by" a flexible I/O
scheme, an efficient register and address space structure,
and a number of ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O
capabilities. The Z8671 fulfills this with 32 pins dedicated to
input and output. These lines are grouped into four ports of
eight lines each and are configurable under software control
to provide timing, status signals, serial or parallel I/O with or
without handshake, and an address/data bus for interfacing
external memory.
Because the multiplexed address/data bus is merged with
the I/O-oriented ports, the Z8671 can assume many
different memory and· I/O configurations. These
configurations range from a self-contained microcomputer

to a microprocessor that can address 124K bytes of external
memory.
Three basic address spaces are available to support this
wide range of configurations: program memory (internal
and external), data memory (external) and the register file
(internal). The 144-byte random-access register file is
composed of 124 general-purpose registers, four I/O port
registers, and 16 control and status registers:
To unburden the program from coping with real-time
problems such as serial data communication and
counting/timing, an asynchronous receiver/transmitter
(UART) and two counter/timers with a large number of
userselectable modes are offered on-chip. Hardware
support for the UART is minimized because one of the
on-chip timers supplies the bit rate.

PIN DESCRIPTION
AS. Address Strobe (output, active Low). Address Strobe is
pulsed once at the beginning of each machine cycle.
Addresses output via Port 1 for all external program or data
memory transfers are valid at the trailing edge of AS. Under
program control, AS can be placed in the high-impedance
state along with Ports 0 and 1, Data Strobe, and ReadIWrite.
OS. Data Strobe (output, active Low). Data Strobe is
activated once for each external memory transfer.

POO·P07. P10·P17. P20·P27. P30·P37. I/O Port Lines
(input/outputs, TIL-compatible). These 32 lines are .divided
into four 8-bit I/O ports that can be configured under

program control for I/O or external memory interface.

RESET. Reset (input, active Low). RESET initializes the
Z8671. W,hen RESET is deactivated, program execution
begins from internal program location OOOCH.

R/W. ReadlWrite (output). R/W is Low when the Z8671 is
"Yriting to external program or data memory.
XTAL1. XTAL2. Crys'tal 1, Crystal 2 (time-base input and
output). These pins connect a parallel-resonant crystal (8
MHz maximum) or an external single-phase clock (8 MHz
maximum) to the on-chip clock oscillator and buffer.

ADDRESS SPACES
Program Memory. The Z8671's 16-bit program counter
can address 64K bytes of program memory space.
Program memory consists of 2K bytes of internal ROM and
upt062K bytes of external ROM, EPROM, or RAM. The first
12 bytes of program memory are reserved for interrupt
vectors (Figure 4). These locations contain six 16-bit vectors
that correspond to the six available interrupts. The
BASIC/Debug interpreter is located in the 2K bytes of
internal ROM. The interpreter begins at address ·12 and
extends to 2047.

5535
EXTERNAL
ROM OR RAM

2048
2047
ON·CHIP
ROM

Location of
first byte 01

instruction
executed

after reset

Interrupt
Vector

(lower Byte)

Interrupt
Vector
(Upper Byte)

BASICI
}

~ ~-----------11

IRQS

10

IRQS

9

IRQ4

a

IRQ4

7

IRQ3

6

IRQ3

5"

IRQ2

4\#,"

IRQ2

3

IRQ1

2

IRQ1

1

IRQO

0

IROO

Figure 4. Program Memory Map

32

DEBUG

Data Memory. The 28671 can address up to 62K bytes of
external data memory beginning at location 2048 (Figure 5).
External data memory may be included with, or separated
from, the external program memory space. OM, an optional
. I/O function that can be programmed to appear on pin P34,
is used to distinguish data and program memory space.
Register File. The 144-byte register file may be accessed
.by BASIC programs as memory locations 0-127 and
240-255. The register file includes four I/O port registers
(RO-R3), 124 general-purpose registers (R4-R127), and 16
control and status registers (Figure 6).
The BASIC/Debug Interpreter uses many of the generalpurpose registers as pointers, scratch workspace, and
internal variables. Consequently, these registers cannot be
used by a machine language subroutine or other user
programs. On power-up/Reset, BASIClDebug searches for
external RAM memory and checks for an auto start-up
program. In a non-destructive method, memory is tested at
relative location xxFDH. When BASIC/Debug discovers
RAM in the system, it initializes the pointer registers to mark
the boundaries between areas of memory that are assigned
specific uses. The top page of RAM is allocated for the line
buffer, variable storage, and the GOSl,lB stack. Figure 7a

illustrates the, contents of the general-purpose registers in
the 28671 system wi\h external RAM. When BASIC/Debug
tests memory and finds no RAM, it uses an internal stack
and shares register space with the input line buffer and
variables .. Figure 7b illustrates the contents of the
general-purpose registers in the 28671 system without
external RAM.

Stacks. Either the internal 'register file or the external data
memory can be used for the stack. A 16-bit Stack Pointer
(R254 and-R255) is used for the external stack, which can
reside, anywhere in' data memory between location 2048
and 65535. An 8-bit Stack Pointer (R255) is used for the
internal stack that resides within the 124 general-purpose
registers (R4-R127).
Register Addressing. 28671 instructions can directly or
indirectly access registers with an 8-bit address field. The
28671 also allows short 4-bit register addressing using the
Register Pointer, which is one of the control registers. In the
4-bit mode, the register file is divided into nine
working-register groups, each group consisting of 16
contiguous registers (Figure 8). The Register Pointer
addresses the starting location of the active working-register
group.
LOCATION

6553S

EXTERNAL
DATA
MEMORY

IDENTIFIERS

255

STACK POINTER (BITS 7-0)

SPL

254

STACK POINTER (BITS 15-8)

SPH

253

REGISTER POINTER

252
261

PROGRAM CONTROL FLAGS
INTERRUPT MASK REGISTER

250

INTERRUPT REQUEST REGISTER

IMR
IRQ

RP

249

INTERRUPT PRIORITY REGISTER

IPR

246

PORTS 0-1 MODE

POIM

247

PORT 3 MODE

P3M

246

PORT 2 MODE

P2M

245
244

TO PRESCALER
TIMER/COUNTER 0

FLAGS

P~EO

TO

243

TI PRESCALER

242
241

TIMER/COUNTER 1
TIMER MODE

TMR

240

SERIAL UO

SIO

PREI
TI

NOT
IMPLEMENTED

2048
2047
NOT ADDRESSABLE

Figure 5. Data Memory Map

Figure 6. Control and Status Registers

33

127

104
103
86
85
64

63

12 7

SHARED BY EXPRESSION
STACK AND LINE BUFFER

EXPRESSION
EVALUATION
STACK

GOSUB
STACK
SHARED BY GOSUB
AND VARIABLES

4

3

VARIABLES

34
33

FREE, AVAILABLE
FOR USR ROUTINES

32

COUNTER

1

30
29
28
27

FREE
4

3

1

' USED INTERNALLY

TO
CONSTANT BLOCK

8
7

USED INTERNALLY

23

LINE NUMBER

14
13
12
11

21
20
19

ARGUMENT/RESULT FOR
SUBROUTINE CALL

18

ARGUMENT FOR
SUBROUTINE
ARGUMENT/ROUTINE FOR
SUBROUTINE CALL

17
16
5

POINTER TO NEXT
CHARACTER

14
13

POINTER TO LINE
BUFFER

12
11

POINTER TO GOSUB

10
9

LINE NUMBER

22
ARGUMENT FOR
SUBROUTINE CALL

SCRATCH

16
15

POINTER TO
CONSTANT BLOCK

USED INTERNALLY

23

18
17

SCRATCH

9

~OINTER

24

20
19

USED INTERNALLY

0

SCRATCH

24
22
21

COUNTER

32

10
9

POINTER TO BASIC
PROGRAM

SCRATCH
POINTER TO INPUT
LINE BUFFER
POINTER TO END OF
LINE BUFFER
POINTER TO STACK
BOTTOM

ADDRESS OF USER
PROGRAM

POINTER TO GOSUB

POINTER TO GOSUB
STACK

FREE

POINTER TO END
OF PROGRAM

1/0 PORTS

1/0 PORTS

Figure 7a. Gene(8I.Purpose R,egisters with External RAM

Figure 7b. General·Purpose Registers without External RAM
255

--+-(

1-.....:....:....:.....:..._L-_:....:...:...-=----t 253

....____- __- - - - - -..... 240
THE UPPER NIBBLE OF THE REGISTER
FILE ADDRESS PROVIDED BY THE
REGISTER POINTER SPECIFIES THE
ACTIVE WORKING REGISTER GROUP
127

--+--+- {
--+- (

THE LOWER

NIBBLE OF
SPECIFIED WORKINGREGISTER GROUP

1

--+- {
--+-

THE REGISTER
FILE ADDRESS
~- PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER,

{
1

--+- ( f- -

-

-I/OPORTS-- -

-- 3

0

Figure 8. The Register Pointer

34

PROGRAM EXECUTION
Automatic Start-up. The Z8671 has an automatic start-up
capability which allows a program stored in ROM to be
executed without operator intervention. Automatic
execution occurs on power-on or Reset when the program is
stored at address 1020H.
Execution Modes. The Z8671's BASIC/Debug Interpreter
operates .in two execution modes: Run and Immediate.

Programs are edited and interactively debugged in the
Immediate mode. Some BASIC/Debug commands are
used almost exclusively in this mode. The Run mode is
entered from the Immediate mode by entering the
command RUN. If there is a program in RAM, it is executed:
The system returns to the Immediate mode when program
execution is complete or interrupted by an error.

INTERACTIVE DEBUGGING
Interactive debugging is accomplished with the selfcontained line 'editor which operates in the Immediate
mode. In addition to changing program lines, the editor can
correct an immediate command before it is executed. It also
allows the correction aftyping and other errors as a program
is entered.
BASIC/Debug allows interruptions and changes during a

program run to correct errors and ad,d new instructions
without disturbing the sequential execution of the program.
A program run is interrupted with the use of the escape key.
The run is restarted with a GOTO command, followed by the
appropriate line number, after the desired changes are
entered. The same procedure is used to enter corrections
after BASIC/Debug returns an error.

COMMANDS
BASIC/Debug recognizes 15 command keywords. For
detailed instructions of command usage, refer to the

BASIC/Debug Software Reference Manual (#03-3149-02).
FO

The GO command unconditionally branches
to a machine language subroutine. This
statement is similar to the USR function
except that no value is returned by the
assembly language routine.

any values left in the buffer first, theri requests
new data.
LET

LET assigns the value of an expression to a
variable or memory location.

LIST

This command is used in the interactive mode
to generate a listing of program lines stored in
memory on the terminal device.

NEW

The NEW command resets pointer R1 0-11 to
the beginning of user memory, thereby
marking the space as empty and ready to
store a new program~

GOSUB

GOSUB unconditionally branches to a
subroutine at a line number specified by the
user.

GOTO

GOTO unconditionally changes the sequence of program execution (branches to a
line number).

PRINT

PRINT lists its arguments~ which may be text
messages or numerical values, on the output
terminal.

IF/THEN

This command is used for conditional
operations and branches.

REM

This command is used to insert explanatory
messages into the program.

INPUTIIN

These commands request information from
the user with the prompt "?", then read the
input values (which must be separated by
commas) from the keyboard, and store them
in the indicated variables. INPUT discards
any values remaining in the buffer from
previous IN, INPUT, or RUN statements, and
requests new data from the operator. IN uses

RETURN

This command returns control to the line
following a GOSUB statement.

RUN

RUN initiates sequential execution of all
instructions in the current program.

STOP

STOP ends program execution and clears the
GOSUB stack.

35

FUNCTIONS
SASIClt)ebug supports two functions: AN D and USA.
The AND function performs a logical AND. It can be used to
mask, turn off, or isGiate bits. This function is used in the
following format:
AND (expression, expression)
The two expressions are evaluated, and their bit patterns are
ANDed together. If only one value is included in the
parentheses, it is AN Ded with itself. A logical OR can also be
performed by complementing the AND function. This. is
accomplished by subtracting each expression from -1. For
example, the function betow is equivalent to the OR of A
andS.

The USR function calls a machine language subroutine and
returns a value. This is useful for applications in which a
subroutine can be performed more. quickly and efficiently in
machine language than in BASIC/Debug.
The address of the first instruction of the subroutine is the
first argument of the USR function. The address can be
followed by one or two values to be processed 'by the
subroutine. In the following example, BASICIDebug
executes the subroutine located at address 2000 using
values literal 256 and variable C.
USR(%2000,256,C)
The resulting value is stored in Registers 18-19.

-1-AND(-1-A, -1-B)

SERIAL INPUT/OUTPUT
Port 3 Nnes P30 and P37 can be programmed as serial 110
lines for fUll-duplex serial asynchronous receiver/transmitter.
operatiort Thebit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second.·
The Z8671 automatically adds a start bit and two stop bits to
transmitted data (Figure 9). Odd parity is also available as an
option. Eight data bits are always transmitted, regardless of

parity selection. If parity is enabled, the eighth data bit is
used as the odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters..
Received data must have a start bit, eight data bits, and at
least one stop bit. If parity is on, bit 7 of the received data is
replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.

I~I~I~I~I~I~I~I~I~I~I

I

LSTART BIT
' - - - - - - E I G H T !lATA BITS
TWO STOP BITS

- - - - - - - - - O N E STOP BIT

L...

TRANSMITTED DATA
(No Parity)

RECEIVED DATA
(No Parity)

~pl~lpl~I~I~I~I~I~I~I~1

ISP IP I0,1 0 10.1 0,1 0,1 0, IDo IST I

T
I

5

I'-------------

ODD PARITY

I·

TWO STOP BITS

' - - - - - - - - - - ONE STOP BIT

LSTART BIT
---,,---SEVEN DATA BITS

_LSTAilTBIT
' - - - - - - S E V E N DATA BITS

< - - - I

PARITY ERROR FLAG

RECEIVED DATA
(With Parity)

TRANSMITTED DATA
(With Parity)

Figure 9. Serial Data Formats

36

LSTART BIT
' - - - - - - E I G H T DATA BITS

1/0 PORTS
The 28671 has 32 lines dedicated to input and output.
These lines are grouped into four ports of eight lines each
and are configurable as input, output or address/data.
Under software control, the ports can be programmed to
provide address outputs, timing, status signals, serial I/O,
and parallel I/O with or without handshake. All ports have
active pull-ups and pull-downs compatible ~ith TIL loads.

Port 1 can be programmed as a byte I/O port or as an
address/data port for interfacing external memory. When
used as an I/O port, Port 1 may be placed under handshake
control. In this configuration, Port 3 lines P33 and P34 are
used as the handshake controls RDY1 and DAV1 (Ready
and Data Available).
Memory locations greater than 2048 are referenced
through Port 1. To interface external memory, Port 1 must be
programmed for the multiplexed Address/Data mode. If
more than 256 external locations are required, Port must
output the additional lines.

°

Port 1 can be placed in the high-impedance state along with
Port 0, AS, DS and R/IN, allowing the 28671 to share
common resources in multiprocessor and DMA
applications. Data transfers can be controlled by assigning
P33 as a Bus Acknowledge input and P34 as a Bus Request
output.

Port 0 can be programmed as a nibble I/O port, or as an
address port for interfacing external memory. When used as
an 1/0 port, Port may be placed under handshake control.
In this configuration, Port 3 lines P32 and P35 are used as
the handshake controls DAVO and RDYO. Handshake signal
assignment is dictated by the I/O direction of the upper
nibble P04-PO?

°

°

For external memory references, Port can provide address
bits Aa-A11 (lower nibble) or As-A15 (lower and upper nibble)
depending on the required address space. If the address
range requires 12 bits or less, the upper nibble of Port can
be programmed independently as I/O while the lower nibble
is used for addressing. When Port nibbles are defined as
address bits, they can be set to the high-impedance state
along with Port 1 and the control signals AS, DS and R/W

°

°

Port 2 bits can be programmed independently as input or
output. The port is always available for I/O operations. In
addition, Port 2 can be configured to provide open-drain
outputs.

°

and 1, Port 2 may also be placed under
Like Ports
handshake control. In this configuration, Port 3 lines P31
and P36 are used as the handshake controls lines DAV2 and
RDY2. The handshake signal assignment for Port 3 lines
P31 and P36 is dictated by the direction (input or output)
assigned to bit 7 of Port 2.

Port 3 lines can be configured as I/O or control lines. In
either case, the direction of the eight lines is fixed as four
input (P3a-P33) and four output (P3 4-P3?). For serial 110,
lines P3a and P3? are programmed as serial in and serial out
respectively.
Port 3 can also provide the following control functions:
handshake for Ports 0, 1 and 2 (DAV and RDY); four external
interrupt request signals (IROO-IR03); timer input and
output signals (TIN and TOUT) and Data Memory Select
(DM).

--.......

PORT 1
(110 OR ADo-AD7) P1o-P17

Z8G71

Z8G71

Mf;:U

MCU

P20

PORT 2(110)

P2,
}

HANDSHAKE CONTROLS

HANDSHAKE CONTROLS
} DAV2 AND RDY2

DAV1 AND RDV1
(P33 AND P34)

(P13ANDP36)

Figure 10a. Port 1

.}

Figure 10c. Port 2

-

pO.,PO, } PORT 0
POo'PO,
(1/0 OR AS-A15 \

Z8G71

Z8G71

MCU

MCU
_

-

PORTa

(110 OR CONTROL)

} HANDSHAKE CONTROLS

DAVO AND RDVO
(P32 AND P3s)

Figure 10b. Port 0

Figure 10d. Port 3

37

COUNTER/TIMERS
The Z8671 contains two 8-bit programmable counter/timers
(TO and T1), each driven by its own 6-pit programmable
prescaler. The T1 prescaler can be driven by internar or
external clock sources; however, the TO prescaler is driven
by the internal clock only..
The 6-bit prescalers can divide the input frequency of the
clock source by any number from .1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter.. When the counter reaches
the end of count, a timer interrupt reque~t-IRQ4 (To) or
IRQS (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass

mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode) .. The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode.
The clock source for T1 is user-definable; it can be either the
internal microprocessor clock (4 MHz maximum) divided by
four, or an external signal input via Port 3. The Timer Mode
register configures the external timer input as an external
clock, a trigger input that can be retriggerable or
nonretriggerable, or as a gate input for the internal clock.
The counter/timers can be programmably cascaded by
connecting the TO output to the input of T1. Port 3 line P36
also serves as a timer output (TOUT) through which TO, T1 or
the internal clock can be output.

INTERRUPTS
The Z8671 allows six different interrupts from eight sources:
the four Port 3 lines P30-P33, Serial In, Serial Out, and the
two counter/timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or
individually enables or disables the six interrupt requests.
When more than one interrupt is pending, priorities are
resolved by a programmable priority encoder that is
controlled by the Interrupt Priority register.
All Z8671 interrupts are vectored; however, the internal
UART operates in a polling fashion. To accommodate a
polled structure, any or all of the interrupt inputs can be
masked and the Interrupt Request register polled to
determine which of the interrupt requests needs service.
The BASIC/Debug Interpreter does not process interrupts.
Interrupts are vectored through locations in internal ROM
which point to addresses 1000-1011 H. To process

38

interrupts, jump instructions can be entered to the interrupt
handling routines at the appropriate addresses as shown in
Table 1.
Table 1. Interrupt Jump Instructions
Hex

Address
1000-1002
1003-1005
1006-1008
1009-1008
10OC-100E
100F-1011

Contains Jump Instruction and .
S.ubroutine Address for:
IRQO
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5

CLOCK
The on-chip oscillator has a high-gain, parallel-resonant
amplifier for connection to a crystal or to any suitable
external clodk source (XTAL 1 = Input, XTAL2 = Output).
The crystal source is connected across XTAL 1 and XTAL2,
using the recommended capacitance (C L = 15 pf
maximum) from each pin to ground. The specifications for
the crystal are as follows:

• AT cut, parallel resonant
•

Fundamental type, 8 maximum

•

Series resistance, R ..; 100 Q

•

8 MHz maximum

INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used -to
describe the addressing modes and instruction operations
as shown in the instruction summary.

IRR
Irr
X

DA
RA

1M
R
r

IR
Ir

RR

Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Symbols. The following symbols are used in describing the
instruction set.
dst
Sre

cc
@

SP
PC
FLAGS

RP
IMR

Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol "9': For
example,
dst +- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the following six
flags:

C
Z

S
V

o
H

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

Affected flags are indicated by:

o
1

X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

39

CONDITION CODES
Mnemonic

Vallie
1.000
0111

Meenlng

Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
UlT
UGT
ULE

1111
0110
1110
1101
0101
,0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011

Flags Set

0000

C = 1
,C = 0
Z =1
'Z = 0

8=0
8= 1

V=1
V=O
Z= 1
Z=O
(8 XOR V) = 0
(8XORV) = 1
[Z OR (8 XOR V)] = 0
[ZOR (8XOR V)] = 1
C=O
C=1
(C = OANDZ = 0) = 1
(CORl) = 1

INSTRUCTION FORMATS
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF

OPC

ds.

ope

INCr

ONE·BYTE INSTRUCTION

OPC

MODE

dsVsrc

ADC, ADD, AND, CP,
LD, OR, SBC; SUB,
TCM, TM, XOR

CLR, CPL, DA, DEC,
OR 11 1 1 01 dstls.. 1

~~~~' ~~~RL~~:R;OP,
RRC, SRA, SWAP

, 1f-:---'~7-:::~----l1

JP, CALL (Indirect)
OR 11 1 1 01

dst

1-_'==---1

OR

h 1 1 01

ds1

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

SRP

OPC
VALUE

MODE

OPC

MODE

ds'

sre

MODE
dstlsrc

ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR

OR

11

1 1

01

LD

OPC

JP

DAu
DA,
LD

1

DJNZ, JR

dsVCC
OPC
,RA

OPC
DAu
DA,

CALL

THREE·BYTE INSTRUCTION

lWo-Byte Instruction

Figure 11. Instruction formatS

40

LD

LD

cc

src

dst 1 OPC
VALUE

I

f-----':"':--I 6: ~ ~ ~ ~ ::

LD, LDE, LDEI,
LDC, LDCI

OPC
arc/ds' _

ds"are
ope
. src/dst

OPC

I..
III

Jc:

INSTRUCTION SUMMARY

Instruction
and Operation
ADCdst,src
dst - dst + src + C

Addr Mode Opcode
Byte
dst src
(Hex)
(Note 1)

Flags Affected
C Z S V 0 H

JR cC,dst
if cc IS true,

10

ADD dst,src
dst - dst + src

(Note 1)

00

AND dst.src
dst - dst AND src

(Note 1)

50

Addr Mode Opcode
Byte
dst src
(Hex)

Instruction
and Operation

RA
C

06
04

CCF

EF

LD dst,src

1m

dst - src

R
r
X
r
Ir

*-----

C-NOTC

CLR dst

R

BO

dst-O

IR

B1

COMdst
dst- NOTdst

R
IR

60

CP dst,src

(Note 1)

AD

DAdst
dst- OAdst

R
IR

40
41

DECdst
dst -dst - 1

R

00

IR

01

RR

80
81

IR

01
IMR(7)-0
DJNZ r,dst
r-r - 1
,f rif' 0
PC - PC + dst
Range + 127. -128

9F

INCdst
dst - dst + 1

rE
0 - F
20
21

r
IR

=

If

cc IS true
PC -dst

* * * X

R

r
Irr

Irr

Ir
Irr

Irr
Ir

LDE dst,src
dst - src

r
Irr

Irr

LDEI dst,src
dst - src
r - r + 1; rr - rr + 1

Ir
Irr

Irr
Ir

83
93

(Note 1)

40

R
IR

51

DA

IRR

E7
F5

LOCI dst,src
dst - src
r-r + 1;rr-rr + 1

cD
c=O-F

30

C2

02
C3

03
82

92

FF

NOP

OR dst,src
dst - dst OR src
POPdst
dst-@SP;
sp -SP + 1

-***--

SP-SP - 1;@SP-src

RCF

50

R
IR

70
71
CF

0-----

C-O

AO
A1

IRET
BF
FLAGS - @SP; SP - SP + 1
PC -@SP; sp - SP + 2;IMR (7) - 1

JP cC,dst

E3
F3
E4
E5
E6

IR
1M
1M
R

PUSHs~

INCWdst
dst - dst + 1

07

R

dst - src

rA
r= 0 - F

EI
IMR(7)-1

R

r
Ir

R
R
IR
IR

LDC dst,src

8F
RA

X

rC
r8
r9
r= 0 - F
C7

61

dst - src

DECWdst
dst - dst - 1

C Z S V 0 H

cB
= 0 - F

PC -PC + dst
Range: + 127, - 128

R

CALLdst
DA
SP -SP - 2
IRR
@SP - PC: PC - dst

Flags Affected

RET
PC - @SP; SP - SP + 2

AF

RLdst

90
91

* * * * * *
RLCdst~R
C
7
0
IR

10
11

* * * *

lilllciJ IRR

EO
E1

* * '* *

RI'! dst

C

7

0

I

41

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

Addr Mode Opcode
Byte
dst src
(Hex)

C Z S V 0 H

CO

RRCdst~IR

~IR

SBC dst,src

Flags Affected

XORdst,src
dst - dst XOR src

C1

(Note 1)

3D

dst - dst - src - C

SCF

OF

1-----

DO

***0--

C-1
SRA dst

L@]

~ I~

SRP src
RP -src

S

TCM dst,src
(NOT dst) AND src
TM dst,src
dstANO src

42

(Note 1)

01 R
IR
(Note 1)
(Note 1)

* * **
X

60

-* * 0

* *

BO

-** 0 - -

Lower
Opcode Nibble

Ir

II]
[I]

N

oa

GI

...
!oil

R

-**0--

C Z S V 0 H

src

*

X

FO
F1

70

(Note 1)

AddrMode

1

src

Flags Affected

For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.

31

20

dst

Opcode
Byte
(Hex)

NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a D In this table, and ItS value is found In the
follOWing table to the left of the applicable addreSSing mode pair.

dst

SUB dst,src
dst - dst - src
SWAP dst 17

01
1m

AddrMode
Instruction
and Operation

R

R

IR

R

1M

IR

1M

m

IIJ
W

m

I

C"J

CI

REGISTERS

R240SI0
Serial I/O Register

R244 TO
Counter/Timer 0 Register

(FOH; Read/Write)

(F4H; Read/Write)

L -_ _ _ SERIAL DATA (Do '" LSS)

To INITIAL VALUE (WHEN WRITTEN)
L----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)

MODES
NOT To",
useD::
00

~o g~~
INTERNAL CLOcK OUT

:= ~~

R241 TMR
Time Mode Register

R245 PREO
Prescaler 0 Register

(F1 H; Read/Wrrte)

(F5H; Write Only)

j

lW~O

.-J

1 '" ENABLE To COUNT

11

T

MODES
EXTERNAL. CLOCK IN~OT = 00

0 :: DISABLE 1, COUNT

= 10

=

COUNTMODE
o = To SINGlE·PASS
1 = To MODUlO·N

RESERVED (MUST BE 0)

0 :: NO FUNCTION
1 = LOAD T 1

GATE INPUT", 01
TRIGGER INPUT
(NQN.RETRIGGERABLEj
TRIGGER INPUT
(RETRIGGERABLE)

~L

= NO
FUNCTION
1 :::
LOAD
To

0 ;;; DISABL.E To COUNT

PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

1 = ENABLE T COUNT
1

11

R242T1
Counter Timer 1 Register

R246P2M
Port 2 Mode Register

(F2H; Read/Write)

(F6H; Write Only)

1, INITIAL. VALUE (WHEN WRITTEN)
L----(RANGE 1-256 DECIMAL 01-00 HEX)
1, CURRENT VALUE (WHEN READ)

R243 PRE1
Prescaler 1 Register

R247P3M
Port 3 Mode Register

(F3H; Write Only)

(F7H; Write Only)

~L
,

COUNTMODE
1 .= T, MODULO·N
0 "" T\ SINGLE·PASS
CLOCK SOURCE
1 = Tl INTERNAL
T 1 EXTERNAL
TIMING INPUT
(Tn,.) MODE

o"

.

[gE

LO

PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
RESERVED (MUST BE 0)

o P32

= INPUT
P3s '" OUTPUT
1 P32 == liAW/RDYO P3s = RDYO/IlAVO

o 0 P33
~ ri } P33

PRESCAL(:R MODULO
(RANGE: 1·64 DECIMAL
01·00 HEX)

= INPUT

P34 = OUTPUT

= INPUT
RESERVED

11

o P31

P34 =

OM

= INPUT (TIN)

P3G = OUTPUT (TOUT)
1 P31 '" DAV2IRDY2 P3G = RDY2I~

L _______ ~

L __ _____
~

~~ ~ ~N~~lL

IN

:~~ ~ ~~~r,.ULTOUT

~ ~:=:~~ g~F

Figure 12. Control Registers

43

REGISTERS

R248P01M
Port 0 Register
(F8H; Write Only)

(Continued)

po._po,

R252 FLAGS
Flag Register
(FCH; Read/Write)

MODE:]
~-r
~
L po,-po, MODE

EXTERNAL
MEMORY TIMING

NORMAL
*EXTENOED

'

H~~

LUSERFLAG"
LUSER FLAG F2

00 = OUTPUT
01 = INPUT
1X = Aa-A11

OUTPUT 1= 00
INPUT = 01
A'2-A,S = 1X

,

STACK SELECTION
0 = EXTERNAL

=0

•

1 = INTERNAL

= 1

HALF

C~RRY FLAG

DECIMAL-ADJUST FLAG

OVERFLOW FLAG
SIGN FLAG
ZERO FLAG

RESERVED (MUST BE 0)

CARRY FLAG
'ALWAYS EXTENDED TIMING AFTER REseT

R2491PR
Interrupt Priority Register
(F9H; Write Only)

R253 RP
Register Pointer
(FDH; Read/Write)

i
to
to

I~I~I~I~I~I~I~I~I

I I III ......'"- .~m

"_.,,:J

RESERVED:::: 000
> A > B = 001

c

IRQ3, IROS PRIORITY (GROUP A)

o ;:

IROS > IR03
1 '" IRoa > IRQS

A > B :> C :::: 010
A> C :> 8 = 011

IRQ2 ::> IROO

1 '" IROO

':>

POINTER

gB >~ ~A ~ :C ~= ~~~
110

IROO, IRQ2 PRIORITY (Gf\OUP 8)

o ::

~

«
c

LOON'TCARE
REGISTER

::>

IRQ2

RESERVED = 111

IRQ1, IRQ4 PRIORITY (GROUP C)
= IRQ1 ::> IRQ4
1 :::: IRQ4 :> IRQ1

o

R250 IRQ
Interrupt Request Register
(FAH; Read/Write)

R254SPH
Stack Pointer
(FEH; Read/Write)

I~I~I~I~I~I~I~I~I
RESERVED (MUST BE 0)

c=

T

IROO
IRQ1
IRQ2
IRQ3
IRQ4

To, SERIAL OUTPUT

IROS

T,

P30liNPUT (Do "" IROO)
P3J INPUT
P311NPUT

P30 INPUT, SERIAL INPUT

R2511MR
Interrupt Mask Register
(FBH; Read/Write)

. R255SPL
Stack Pointer
(FFH; Read/Write)

1~1~1~1~1~1~1~1~1

I~I~I~I~I~I~I~I~I

I'

c=

1 ENABLES IROO-IAOS
(Do;;; IRQO)

' - - - - - - - - RESERVED (MUST BE 0)

' - - - - - - - - 1 ENABLES INTERRUPTS

Figure 12. Control Registers (Continued)

44

1'-___ :~~~~s~~~~;~R

LOWER

OPCODEMAP
Lower Nibble (Hex)
1,

o

4

6

7

8

9

A

B

C

D

E

10,5

10,5

6,5

6,5

12/10,5

12/10,0

6,5

12/10,0

6,5

6,5

6,5

6,5

6,5

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

LD

JP

INC

R,

IR,

r1.r2

(1. lr2

R2,R,

IR2,R,

R"IM

IR"IM

r"R2

r2,R,

r"RA

cC,RA

r"IM

cC,DA

rl

6,5

' 6,5

6,5

6,5

10,5

10,5

10,5

10,5

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR"IM

RLC

2

4
10,5

10,5

R,

IR,

(1,r2

(1. lr2

R2,R,

IR2,R,

R"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB

r1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

10,5

10,5

10,5

R,

IR,

r1/2

8,0

6,1,

6,5,

SRP'

SBC

SBC

SBC

SBC

SBC

SBC

1M

r1.f2

r1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR

R,

IR,

rl.r2

r1, lr2

R2,R,

IR2,R,

R"IM

JR"IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND'

AND

R,

IR,

r1,r2

r1. lr2

R2,R,

IR2,R,

R"IM

IR"IM

-

r----

r--

10,5

JP
IRR,

F

r---,
~

5

6

i

e.

..
~

7

z

...& 8
:::>

A

B

C

D

E

F

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM,

TCM

R,

IR,

r1,r2

(1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

10/12,1

12/14,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

R2,R,

IR2,R,

R"IM

IR"IM

R2

IR2

r1,r2

(1, lr2

10,5

'0,5

12,0

18,0

DECW

DECW

LDE

LDEI

RR,

IR,

rl, lrr2

Ir1,lrr2

6,5

6,5

12,0

18,0

RL

RL

LDE

LDEI

R,

IR,

r2· lrr 1

Ir2,lrrl

-

~
DI

~
EI

r-----;w

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

INCW

INCW

CP

CP

CP

CP

CP

CP

RR,

IR,

r1.r2

rl, lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R,

IR,

r1· r2

r1, lr2

R2,R,

IR2,Rh

R"IM

IR"IM

,

RET

r---w:o
IRET
~

6,5

6,5

12,0

18,0

RRC

RRC

LDC

LDCI

LD

R,

IR,

r1,lrr2

Irt,lrr2

rl,x,R2

10,5

RCF

6,5

6,5

12,0

18,0

20,0

20,0

10,5

SRA

SRA

LDC

LDCI

CALL'

CALL

LD

R,

IR,

r2: lrr1

Ir2,lrr1

IRR,

DA

f2,X,Rl

6,5

6,5

6,5

10,5

10,5

10,5

RR

RR

LD

LD

LD

LD

R,

IR,

r" IR 2

R2,R,

IR2,R,

R"IM

85

8,5

6,5

SWAP

SWAP

LD

LD

R,

IR,

Ir1.r2

R2,IR,

r----s:s
SCF
r----s:s
CCF

10,5

/ LD
IR"IM

~

'0,5

NOP

'-.. - - - -...."',,----....' '-...- - - -...v,,----....

------v-,,-----..". ~"----v---"

.1 '...

2

2

3

Byte. per Instruction

EXECUTION
CYCLES

PIPELINE
CYCLES

MNEMONIC

Legend:
R - 8·bit address
r = 4-blt address
Rt or'r1 ::: Dstaddress
R2 or r2 "" Src a~dress

Sequence:
Opcode, First Operand, Second Operand

FIRST
OPERAND

SECOND
OPERAND

NOTE: The blank areas Bre not defined

• 2-byte instruction fetch cycle appears as a 3-byte instruction

45

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... - O.3V to + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. -65°Cto +150 oC

Stresses greater than those listed under Absolute Maximum Ratings may
cause pe(manent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.

The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information seCtipn. Refer to the Literature List for
additional documentation.

Standard conditions are:
•

+4.75V~Vee~ +5.25V

•

GND

= OV
+5V
2.1K

'::'

'::'

Figure 13. Test Load 1

DC CHARACTERISTICS
Symbol

Parameter

VeH

Clock Input High Voltage

Vel

Clock Input Low Voltage

VIH

Input High VOltage

Vil

Input Low Voltage

VRH

Reset Input High Voltage

VRL

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

Min

Max

Unit,

Condition

3A

Vee

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

2.0

Vee

V

-0.3

0.8

V

3.8

Vee

V

-0.3

U.8

V
1/

IOH

=

-2S0J-lA

0.4

V

IOl

=

+2.0 rnA

2.4

III

Input Leakage

-10

10

J-IA

OV ~ VIN ~ + 5.25V

IOl

Output Leakage

-10

10

J-IA

OV ~ VIN ~ + 5.25V

IIR

Reset Input Current

-SO

J-IA

Vee

lee

Vee Supply Current

180

rnA

46

=

+ S.2SV, VRl

= OV

)(

RIW

PORT 0,

DM

~

~

--®-I

K=

16
3

)j

PORT 1

AO"-A7

~

-0- - 0 -

~I

1----0--

I----®----J'
X

Os
(READ)

PORT 1

--

.

<

,

0

..

<

.... 01-

~1\

•
CD

)

Do-D,IN

"1
-®-

}(

00-07 OUT

AO-A7

-®-I

I----®---I
J

DS
(WRITE)

y

Figure 16. External 110 or Memory ReadlWrite

AC CHARACTERISTICS
External 110 or Memory Read/Write Timing
No.

Symbol

Parameter

TdA(AS)

Address Valid to AS t Delay
AS t to Address Float Delay
AS t to Read Data Required Valid
AS Low Width

2 TdAS(A)
3 TdAS(DR)
4 TwAS
5 TdAz(DS)
6-TwDSR
7
8
9

Min

Max

Notes*tO

35
45
220
55

2.3
2.3
1.2.3
1.2.3

Address Float to OS ~
o
OS (Read) Low Width - - - - - - - - - - - - - - 1 8 5 - - - - - - - 1 . 2 . 3

TwDSW
TdDSR(DR)
ThDR(DS)

OS (Write) Low Width

TdDS(RIW)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

OS fto RIW Not Valid
Write Data Valid to OS (Write) ~ Delay

110
1.2.3
OS ~ to Read Data Required Valid
130
1.2.3
Read Data to OS 1 Hold Time
o
10 TdDS(A)
OS fto Address Active Delay
45
2.3
11
TdDS(AS)
OS t to AS ~ Delay
55
2.3
12 - TdR!W(AS) - - RIWValid to AS t Delay - - - - - - - - - - - - - - 3 0 - - - - - - - 2.3
13
14
15
16
17

OS t to' Write Data Not Valid Delay

35

2.3

35
45

2.3
2.3
1.2.3
2.3

Address Valid to Read Data Required Valid

AS t to DS~ Delay

255
55

NOTES:
1. When using extended. memory timing add 2 TpC.

2. Timing numbers given are for minimum TpC.
3. See clock cycle time dependent characteristics table.

t Test Load 1.
o All timing references use 2.0 V fora logic "1" and O.S V for a-logic "OH,
.. AU units in nanoseconds (ns).

47

Figure 17. Additional Timing

AC CHARACTERISTICS
Additional Timing

II

aCI
No.

2
3
4

Symbol

Parameter

TpC

Input Clock Period
Clock Input Rise And Fall Times
Input Clock Width
Time Input Low Width

TrC,TfC
TwC
TwTinL

MID

Max

80

1000

Notes·

I

26

I

70

2

NOTES:
.
.
1. Clock timing references uses 3.8 V for a logic "I".ond 0.8 V for
a logic "0".
.
2. Timing referenoe uses 2.0 V for 0 logic "I" and 0.8 V for

100

2
2
2
2,3
2.4
2,3

3. Interrupt request via Port 3 (P3I-P33l.
4. Interrupt request via Port 3 (P30) .
• Units in nanoseconds (ns).

a logic "OH.

AD-.AfD

4;....__________

AD_D_R_ES_S_V_A_LI_D_ _ _ _ _ _ _ _ _

~~

~j.-_._____0___~jr----------------~T~~2-

__
-_- J
DD-DT

~

DgN'T CARE

~

DA!A IN VALID

Figure 18. Memory Port Timing

AC CHARACTERISTICS
Memory Port Timing

No.

Symbol

Parameter

2

TdA(Dl)
ThDI(A)

Address Valid to Data Input Delay
Data In Hold time

NOTES:
1. Test Lood 2.
2. This Is a Clock-Cycle-Dependant parameter. For clock frequencies
other thml the maximum, use the follOWing formula: 5 TpC - 95

48

Min

Max

Notes·

320

1,2

o
*Units are nanoseconds unless otherwise specified..

II

t
C

15

5 - TwTinH - - - Timer Input High Width - - - - - - - - - - - - - - - - 3TpC
6
TpTin
Timer Input Period
8TpC
7
TrTin, TfTin
Timer Input Rise And Fall Times
Sa
TwIL
Interrupt Request Input Low Time
70
8b TwIL
Interrupt Request Input Low Time
3TpC
9
TwIH
Interrupt Request Input High Time
3TpC

..

x

DATA IN VALID

DATA IN

(i)
OAV
(INPUT)

,'--------

ROY
(OUTPUT)

Figure 18a.lnput Handshake

DATA OUT VALID

DATA OUT

OAV
(OUTPUT)

>------10)----1
ROY
(INPUT)

Figure 18b. Output Handshake

AC CHARACTERISTICS
Handshake Timing

No.

Symbol

Parameter

Min

Max

Notes·

TsDI(DAV)
Data In Setup Time
o
ThD!(DAV)
Data In Hold time
160
2
120
3
TwDAV
Data Available Width
4
TdDAVIf(RDY)
DAV • Input to RDY • Delay
120
1,2
5-TdDAVOf(RDY)-- DAV • Output to RDY • D e l a y - - - - - - - - - - - - O - - - - - - - - 1 , 3
6
7
8
9

TdDAVIr(RDY)
TdDAVOr(RDY)
TdDO(DAV)
TdRDY(DAV)

I5XV iInput to RDY t Delay
l)]W't Outputto RDY t Delay
Data Outto DAV • Delay
Rdy. Input to I5XV t Delay

NOTES:
1. Test load 1

120
0
30
0

1,2
1,3

140

• Units in nanoseconds (ns).

2. Input handshake

3. Output handshake
t All timing references use 2.0 V for a logic "1" and 0.8 V for
a logic "0".

CLOCK CYCLE TIME-DEPENDENT CHARACTERISTICS
Number

1
2
3
4
6
7

Symbol

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
8
TdDSR(DR)
10
Td(DS)A
11
TdDS(AS)
TdR/W(AS)
12
* Add 2TpC when using extended memory timing

Z8671-8
Equation

TpC - 75
TpC- 55
4TpC - 140*
TpC - 45
3TpC - 125*
2TpC - 90*
3TpC - 175*
TpC - 55
TpC - 55
TpC - 75

Number

13
14
15
16
17

Symbol

TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

Z8671-8
Equation

TpC - 65
TpC - 75
TpC - 55
5TpC - 215 *
TpC - 45

49

~ ZiIm

Product Specification

Z8681/82 Z8®
ROMless MCU

June 1987

FEATURES
• Complete microcomputer, 24 I/O lines, and up to 64K
bytes of addressable external space each for program
and data memory.

•

Full-duplex UART and two programmable 8-bit
counter/timers, each with a 6-bit programmable
prescaler.

•

•

Register Pointer so that short, fast instructions can
access anyone of the nine working-register groups ..

143-byte register file, including 124 general-purpose
registers, 3 I/O port registers, and 16 status and control
registers.

• Vectored, priority interrupts for I/O, counter/timers, and
UART

• Single + 5V power supply-all I/O pins TTL compatible.

• Z8681/82 available in 8 MHz.
in 12 and 16 MHz.

Z8681 also available

• On-chip oscillator that accepts crystal or external clock
drive.

GENERAL DESCRIPTION
The Z8681 and Z8682 are ROM less versions of the Z8
single-chip microcomputer. The Z8682 is usually more cost
effective. These products differ only slightly and can be
used interchangeably with proper system design to provide
maximum flexibility in meeting price and delivery needs.

PORTO

(NIBBLE
PROGRAMMABLE)
1/0 OR As-A15

PORT 1

(BYTE
PROGRAMMABLE)
ADo-AD?

--

RESET

+5V

R/W

GND

;SV

P3.

XTAL2

P3,

XTAL1

P2,
P2.

Os
AS

XTAL2

P3,

POo

P20

P30

P2,

PO,

P2,

RESET

P2.

XTAL1

po,

P2,

R/W

P2,

PO,

P2,

os

P2,

PO.

P2.

AS

P2,

POs Z8681182 P2s
P'4
MCU
PO.

P3,

P20

GND

P3,

PO,

P2,

P3,

P3.

P'o

P30

POo

P',

P',

P3,

PO,

P',

P',

P3,

P',

P3,

p'.
P',
p'.
P',

P3.
P3,
P3.
P3,

Figure 1. Pin Functions

50

The Z8681/82 offers all the outstanding features of the Z8
family architecture except an on-chip program ROM. Use of
external memory rather than a preprogrammed ROM
enables this 2:8 microcomputer to be used in low volume
applications or where code flexibility is required.

po,
po,
po.
po,
po,
po,

P',

p'.
P',
P',
P',
P'o

Figure 2a. 40-pin Dual-In-Line Package (DIP).
Pin Assignments

The Z8681 182 can provide up to 16 output address lines,
thus permitting an address space of up to 64K bytes of data
or program memory. Eight address outputs (ADo-AD?) are
provided by a multiplexed, 8-bit, AddresslData bus. The
remaining 8 bits can be provided by the software
configuration of Port 0 to output address bits As-A15'

There are 143 bytes of RAM located on-chip and organized
as a register file of 124 general-purpose registers, 16 control
and status registers, and three 1/0 port registers. This
register file can be divided into nine groups of 16 working
registers each. Configuring the register file in this manner
allows the use of short format instructions; in addition, any of
the individual registers can be accessed directly.

Available address space can be doubled (up to 128K bytes
for the Z8681 and 124K bytes for the Z8682) by
programming bit 4 of Port 3 (P34) to act as a data memory
select output (OM). The two states of OM together with the
16 address outputs can define separate data and memory
address spaces of up to 64K/62Kbytes each.

The pin functions and the pin assignments of the
Z8681/82 40- and 44-pin packages are illustrated in
Figures 1 and 2, respectively.

•...,' :vI)..

~v <{~~ q"J'\ +....'11" .¢t:t" x~4.
6

5

4

3

2

1

q"J'O <{':;' q'l-'\ <{I,.ro q'},VJ

«43 42 41 40

REsn

7

3.

NC

R/IN

8

38

P2.

os

•

37

P2,

AS
P3,

10

11

Z8681

36

P2,

35

P2,

3.

P2.

GND

12

P3,

13

33

P3,

PO.

32

P3.

PO,

"
15

31

P1,

PO,

16

30

P1,

NC

17

2.

P1,

MCU

18 19 20 21 22 23 24 25 26 27 28
qf;;)":J qf;;)'iI A > B
A ::> B > C
A> C > B

IR03, IRQS PRIORITY (GROUP A)
o = IRQS > IRQ3
1 = IRQ3 > IRQS

~~

IRao. IRQ2 PRIORITY (GROUP B)

o = IRQ2 > IRao
1 = IRao > IA02

= 000
= 001

= 010
'" 011

REGISTER

POINTER

g~ ~ ~ ~~

{gQJ

LDON'TCARE

B ::> A > C = 110
RESERVED = 111

IRQ1, IRQ4 PRIORITY (GROUP CJ
o = IRQ1 > IRQ4
1 = IRQ4 > IRQi

R254SPH
Stack Pointer
(FEH: Read/Write)

R250lRQ
Interrupt Request Register
(FAH: Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED (MUST BE

O)T

c=

IROO
IRQ1

IRQ2
IRQ3
IRQ4

IRQS

P32 INPUT (Do '" IRoo)
P33INPUT
P311NPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T,

R2511MR
Interrupt Mask Register
(FBH: Read/Write)

___
IIL____c=
.

R255SPL
Stack Pointer
(FFH: Read/Write)

1 ENABLES IRQO-IRQ5

(Do =

IROO)

_ RESERVED (MUST BE 0)

' - - - - - - - - 1 ENABLES I~TERRUPTS

Figure 18. Control Registers (Continued)

64

"-

USER FLAG F2

HALF CARRY FLAG

Z8681182 OPCODE MAP
Lower Nibble (Hex)

o
o

2

3

4

6

i

e.

~

7

:9

z
Ii
Q.

8

Q.

::>

9

A

B

C

D

E

F

2

3

4

5

7

8

9

A

B
12/10,0

C

D

6,5

E

6,5

6,5

6,5

6,5

6,5

12/10,5

12/10,0

6,5

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

. LD

JP

INC

A,

lA,

r1.r2

r1. Ir2

R2,R,

IR2,R,

A"IM

lA, ,1M

r"A2

r2,A,

r"AA

cC,AA

r"IM

cC,DA

rl

6,5

6,5

6,5

6,5

'D,S

10,5

10,5

10,5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IA"IM

10,5

10,5

10,5

10,5

A,

lA,

T1.r2

T1, lr2

A2,A,

IA2,A,

A"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IA,.IM

A,

lA, .

T1,r2

r" lr2'

A2,A,

IR2,A,

A"IM

8,0

6,1.

6,5

6,5

10,5

10,5

10,5

10,5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IAA,

1M

r1,T2

T1, lr2

A2,A,

IA2,A,

A"IM

IA"IM

8,5·

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR
IR"IM

A,

lA,

T1,r2

T1. lr2

A2,A,

IA2,A,

A"IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND
IA"IM

A,

lA,

r1,r2

r1, lr2

A2,A,

IA2,A,

A"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

A,

lA,

T1,T2

T1, lr2

A2,A,

IA2,A,

A"IM

lA, ,1M

10112,1

12114,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

A2,A,

IA2,A,

A"IM

IA"IM

A2

IA2

r1,r2

T1, lr2

10,5

10,5

12,0

18,0

DECW

DECW

LDE

LDEI

AA,

lA,

T,. lrr2

Ir1,lrr2

6,5

6,5

12,0

'---

t-'----

1

.------,-

-

RL

LDE

LDEI

A,

lA,

T2,lrT,

Ir2,lrT1

6,1

DI

---s.;-

18,0

RL

EI

10,5

10,5

6,5

6,5

INCW

INCW

CP

CP

CP

AA,

lA,

T1. T2

T1. lr2

A2,A,

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

A,

IR,

r1,T2

T1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

12,0

18,0

RRC

RRC

LDC

LDCI

LD

A,

IR,

T1,lrr2

Ir1,lrr2

T1. X,R2

12,0

6,5

F

10,5

10,5

10,5

10,5

CP

CP

CP

IA2,R, . A"IM

-

IR"IM

-

6,5

6,5

18,0

20,0

20,0

SRA

LDC

LDCI

CALL"

CALL

LD

R,

IR,

r2, lrT1

Ir2,lrT1

IRA,

DA

T2,x,R1

6:5

10,5

10,5

6,5

6,5

RR

RR

LD

LD

LD

LD

LD

A,

IR,

r" IR 2

R2,R,

IR2,R,

A"IM

IR"IM

8,5

8,5

6,5

10,5

SWAP

SWAP

LD

LD

A,

lA,

Ir1,r2

A2.1R,

10,5

RCF

6:5

10,5

6,5

16,0

IRET

10,5

SRA

14,0

RET

SCF

t--

10,5

6,5

CCF
t-6,0

NOP

-----"# . . . ---_. .v. ..----~J . . -----_'V_..-----~J~~

-....- - - -.....v..
2

3

2

3
Bytes per Instruction

EXECUTION
CYCLES

PIPELINE
CYCLES

MNEMONIC

Legend:
R ~ 8·blt address
r = 4·bit address
R1 or r1
R2 or r2

=
=

Dstaddress
Src address

Sequence:
Opcode, First Operand, Second Operand

SECOND
OPERAND

• 2-byte instruction. fetch cycle appears

NOTE: The blank areas are not defined.

as a 3-byte Instruction

65

ABSOWTE MAXIMUM RATINGS
Voltages on all pins except RESET
with respect to GND ............... - 0.3V to + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

I

STANDARD TEST CONDITIONS
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted.' All
voltages are referenced to GND. Positive current flows into
the referenced pin.

+5V
2.1K

Standard conditions are as folrows:

• +4.75V~Vee~ +5.25V
• GND = OV
• O°C ~TA ~ + 70°C for S (Standard temperature)

-40°C ~ TA ~ + 100°C for E (Extended temperature)

•

Figure 19. Test Load 1

DC'CHARACTERISTICS
Symbol

Parameter

VeH

Clock Input High Voltage

Vel

Clock Input Low Voltage

VIH

Input High Voltage.

Vil

Input Low Voltage

VRH

Reset Input High Voltage

VRl

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

Min

Max

Unit

3.8

Vee
0.8

V

Driven by External Clock Generator

-0.3

V

Driven by External Clock Generator

2.0

Vee

V

-0.3

0.8

V

3.8

Vee

V

-0.3

0.8

V

2.4
0.4.

Condition

See Note

V

IOH = - 250 !-iA

V

IOL = +2.0mA

IlL

Input Leakage

-10

10

Output Leakage

-10

10

!-iA
!-iA

OV .. VIN" + 5.25V

IOL
IIR

Reset Input Current

-so

JAA

Vee = + 5.2SV, VRL = OV

ICC

Vee Supply Current

150

rnA

All outputs and 110 pins floating

OV .. VIN" + S.2SV

'The Reset line (pin 6) is used to place the Z8682 in external memory mode. This is accomplished as shown in Figure 13. .

66

)(

R/iiii

--®--I

-®PORT 0,

)(

)(

OM

16
3

.~

PORT 1

A,,-A,

00-0, IN

~

-

!-cD- -~4:::'~ q'\>'o qt:;'\ q ....a q....... q....~q ....":J q ...."" ~v

Figure 2b. 44·pin Chip Carrier,
Pin Assignments

1/0

(BIT PROGRAMMABLE)

ADDRESS OR 1/0
(NIBBLE PROGRAMMABLE)

ADDRESSIDATA

,--------------~v~----------~--,#
Z·BUS WHEN USED AS
ADDRESS/D~TA BUS

Figure 3. Functional Block Diagram

72

ARCHITECTURE
Z8691 architecture is characterized by a flexible I/O
scheme, an efficient register and address space structure
and a number of ancillary features that are helpful in many
applications.

data memory and the register file (internal). The 143-byte
random-access register file is composed of 124
general-purpose registers, three I/O port registers, and 16
control and status registers.

Microcomputer applications demand powerful I/O
capabilities. The Z8691 fulfills this with 24 pins available for
input and output. These lines are grouped into three ports of
eight lines each and are configurable under software control
to provide timing, status signals, serial or parallel I/O with or
without handshake, and an Address bus for interfacing
external memory.

To unburden the program from coping with real-time
problems such as serial data communication and
counting/timing, an asynchronous receiver/transmitter
(UART) and two counter/timers with a large number of
user-selectable modes are offered on-chip. Hardware
support for the UART is minimized because one of the
on-chip timers .supplies the bit rate. Figure 3 shows the
Z8691 blook diagram.

Three basic address spaces are available: program memory,

PIN DESCRIPTION

AS_ Address Strobe (output, active Low). Address Strobe is
pulsed once at the beginning of each machine cycle.
Addresses output via Port 1 for all external program or data
memory transfers are valid at the trailing edge of AS.

OS- Data Strobe

(output, active Low). Data Strobe is
activated once for each external memory transfer.

P0o-P07. P20·P27. p30·par- //0 Port Unes (input/outputs,
TTL-compatible). These 24 lines are divided into three 8-bit
I/O ports that can be configured under program control for
I/O or external memory interface (Figure 3).
P10-P17- Address/Data Port (bidirectional). Multiplexed

address (Ao-A7) and data (00-07) lines used to interface with
program and data memory.

RESET. Reset (input, active Low). RESET initializes the
Z8691. After RESET the Z8691 is in the extended memory
mode. When RESET is deactivated, program execution
begins from program location OOOCH.

R/W. Read/Write (output). R/iN is Low when the Z8691
is writing to external program or data memory.
XTAL1. XTAL2. Crystal 1, Crystal 2 (time-base input and
output). These pins connect a parallel-resonant crystal to the
on:chip clock oscillator and buffer.

73

ADDRESS SPACES
Program Memory. The Z8691 addresses 64K/62K bytes of
external program memory space (Figure 4).

Z8691 instructions can access registers directly or indirectly
with an 8-bit address field. This also allows short 4-bit
register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the register file is divided
into nine working-register .groups, each occupying 16
contiguous locations (Figure 5). The Register Pointer
addresses the starting location of the active working-register
group (Figure 6).

The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts. Program
execution begins at location OOOCH after a reset.

Data Memory. The Z8691 can address 64K bytes of external
data memory. External data memory may be included with or
separated from the external prbgram memory space. DM,
an optional 110 function that can be programmed to appear
on pin P34, is used to distinguish between data and program
memory space.

Stacks. Either the internal register file or the external data
memory can be used for the stack. A 16-bit Stack Pointer
(R254 and R255) is used for the external stack, which can
reside anywhere in data memory. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides within the
124 general-purpose registers (R4-R127).

Register File. The 143-by1e register file includes three 1/0
port registers (RO, R2, R3), 124 general-purpose registers
(R4-R127) and 16 control and status registers (R240-R255).
These registers are assigned the address locations shown in
Figure 5,
65 .535

PROGRAM
MEMORY

LOCATION OF FIRST
BYTE OF INSTRUCTION
EXECUTED AFTER
RESET

DATA
MEMORY

----~~-

ci .....

:--

INTERRUPT
7
VECTOR
(LOWER BYTE) ......... 6

!~

INTERRUPT
VECTOR --3
2
(UPPER BYTE)

f~f-

lAOS

IRQ4

-

IRoa

-

IRQ2

-

IRQ1

-

IROO

-

Figure 4. Program Memory Map

74

DEC

HEX

IDENTIFIERS

FF

SPL

STACK POINTER (BITS 15-8)

FE

SPH

REGISTER POINTER

FD

RP

252

PROGRAM CONTROL FLAGS

FC

FlAGS

251

INTERRUPT MASK REGISTER

FB

IMR
IRQ

255

STACK POINTER (BITS 7-0)

254
253

250

INTERRUPT REQUEST REGISTER

FA

249

INTERRUPT PRIORITY REGISTER

F9

IPR

248

PORTS 0-1 MODE

F8

P01M

247

PORT 3 MODE

F7

P3M

246

PORT 2 MODE

F6

P2M

245

TO PRESCAlER

FS

PREO

244

TIMER/COUNTER 0

F4

TO

243

T1 PRESCAlER

F3

PRE1

242

TIMER/COUNTER 1

F2

T1

241

TIMER MODE

F1

TMR

240

SERIAL 1/0

FO

510

NOT
IMPLEMENTED

127

- -

-II : :

[ t-1_7l_,,_,s,--,._,,--_o_o_o_o
THE UPPER NIBBLE OF THE REGISTER
FILE ADDRESS PROVIDED BY THE
REGISTER POINTER SPECIFIES THE
ACTIVE WORKING-REGISTER GROUP.

__ I
I

127

--I
-~(

--I

THELQWER
NIBBLE OF
THE REGISTER
FILE ADDRESS

SPECIFIED WORKING·
REGISTER GROUP

1

7F

__ 1
I

PROVIDED BY
- r THE
INSTRUCTION

POINTS TO THE
SPECIFIED
REGISTER.

GENERAL-PURPOSE
REGISTERS

I

--j

04
PORT 3

03

P3

PORT 2

02

PORT 1

01

P2
P1

PORT 0

00

PO

--I

1

t- - -

Figure 5. The Register File

-'IOPORTS- -

-

-- 3
0

Figure 6. The Register Pointer

SERIAL INPUT/OUTPUT
Port 3 lines P30 and P37 can be programmed as serial I/O
lines for full·duplex serial asynchronous receiver /transmitter
operation. The bit rate is controlled by Counter /Timer 0, with
a maximum rate of 62.5K bits/second at 8 MHz or 93.75K
bits / second at 12 M Hz on the Z8691.
The Z8691 automatically adds a start bit and two stop bits to
transmitted data (Figure 7). Odd parity is also available as an
option. Eight data bits are always transmitted, regardless of

parity selection. If parity is enabled, the eighth data bit is
used as the odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight data bits, and at
least one stop bit. If parity is on, bit 7 of the received data is
replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.

1·1~1~1~1~1~1~1~1~lnl
LSTART BIT
' - - - - - - EIGHT DATA BITS
' - - - - - - - - - - - ONE STOP BIT

Transmitted Data
(No Parity)

T

Received Data
(No Parity)

ISplspl P ID,ID5ID.103ID,1 D,IDolsTI

I SP I P I D, I Ds r 0.1 D31 D, I D, I Do 1ST

·L_LSTARTBIT
'-------SEVEN DATA BITS
000 PARITY

TWO STOP BllS

I

II, _~LSTARTBIT
~-----SEVEN

DATA BITS

PARITY ERROR FLAG

L - - - - - - - - - - - - O N E STOP BIT

Received Data
(With Parity)

Transmitted Data
(With Parity)
Figure 7. Serial Data Formats

75

COUNTER/TIMERS
The Z8691 contains two 8-bit programmable counter /timers
(To and T1), each driven by its own 6-bit programmable
prescaler. The T1 prescaler can be driven by internal or
external clock sources; however, the To prescaler is driven
by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IRQ4 (To) or
IRQ5 (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass mode)

or to automatically reload the initial value and continue
counting (modulo-n continuous mode). The counters, but not
the prescalers, can be read any time without disturbing their
value or count mode.
The clock source for T1 is user-definable; it can be either the
internal microprocessor clock divided by four, or an external
signal input via Port 3. The Timer Mode register configures
the external timer input as an external clock, a trigger input
that can be retriggerable or nonretriggerable, or as a gate
input for the internal clock. The counter/timers can be
programmably cascaded by connecting the To output to the
input OfT1. Port 3 line P36 also serves as a timer output (TOUT)
through which To, T1 or the internal clock can be output.

I/O PORTS
The Z8691 has 24 lines available for input and output. These
lines are grouped into three ports of eight lines each and are
configurable as input, output or Ilddress. Under software
control, the ports can be programmed to provide address

outputs, timing, status signals, serial I/O, and parallel I/O
with or without handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
.

Port 1 is a dedicated Z-BUS compatible memory interface.
The operations of Port 1 are supported by the Address Strobe
(AS) and Oata Strobe (OS) lines, and by the Read/Write
(R/W) and Oata Memory (OM) control lines. The low-order
program and data memory addresses (An-A?) are output
through Port 1(Figure 8) and are multiplexed with data in/out
(00-07)' Instruction fetch and data memory read/write
operations are done through this port.

least-significant four bits of Port 0 can be configured to
supply address bits As-A11 for 4K byte addressing or both
nibbles of Port 0 can be configured to supply address bits
As-A15 for 64K byte addressing.
PORT 1

ADO-ADT
TO EXTERNAL

MEMORY

Port 1 cannot be used as a register nor can a handshake
. mode be used with this port.
The Z8691 wakes up with the 8 bits of Port 1 configured as
address outputs for external memory. If more than eight
address lines are required, additional lines can be obtained
by programming Port 0 bits as address bits. The

Port 0 can be programmed as a nibble I/O port, or as an
address port for interfacing external memory (Figure 9).
When used as an I/O port, Port 0 can be placed under
handshake control. In this configuration, Port 3 lines P32 and
P35 are used as the handshake controls OAVo and ROYo.
Handshake signal assignment is dictated by the I/O
direction of the upper nibble P04-P0 7 .
For external memory references, Port 0 can provide address
bits As-A11 (lower nibble) or Aa-A15 (lower and upper nibbles)
depending on the required address space. If the address
range requires 12 bits or less, the upper nibble of Port 0 can
be programmed independently as I/O while the lower nibble
is used for addressing.
Port 0 lines are configured as address lines As-A15 after a
reset. If one or both nibbles are needed for I/O operation,
they must be configured by writing to the Port 0 Mode
register.

76

Figure 8_ Port 1

To permit the use of slow memory, an automatic wait mode of
two oscillator clock cycles is configured for the bus timing of
the Z8691 after each reset. The initialization routine could
include reconfiguration to eliminate this extended timing
mode.

PD.-POT
) POO-P03

_

} PORT 0
(liD OR A8-A'5

\ HA,NDSHAKE CONTROLS

f

OAVo ANO ROYo

(P3, AND P3,)

Figure 9. Port 0

.

Port 2 bits can be programmed independently as input or
output (Figure 10). This port is always available for I/O
operations. In addition, Port 2 can be configured to provide
open-drain outputs.

Port 2 may also be placed under handshake control. In this
configuration, Port 3 lines P31 and P3s are used as the
handshake controls lines OAV2 and ROY2. The handshake
signal assignment for Port 3 lines P~ and P3s is dictated by
the direction (input or output) assigned to bit 7 of Port 2.

_]P20

i

~' ~J
_

PORr 2(110)

P27
\ HANDSHAKE CONTROLS

1~~~~~~~Y2
Figure 10. Port 2

Port 3 lines can be configured as I/O or control lines (Figure
11). In either case, the direction of the eight lines is fixed as
four input (P30-P33) and four output (P34-P37)' For serial I/O,
lines P30 and P37 are programmed as serial in and serial out,
respectively.

~

Z8881

1

PORT 3
OR CONTROL)

J (1/0

MCU

Port 3 can also provide the following control functions:
handshake for Ports 0 and 2 (OAV and ROY); four external
interrupt request signals (IROO-IR03); timer input and output
signals (TIN and TOUT) and Data Memory Select (DM).
Figure 11. Port 3

INTERRUPTS
The Z8691 allows six different interrupts from eight sources:
the four Port 3 lines P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or
individually enables or disables the six interrupt requests.
When more than one interrupt is pending, priorities are
resolved by a programmable priority encoder that is
controlled by the Interrupt Priority register.
All interrupts are vectored through locations in program
memory. When an interrupt request is granted,.an interrupt
machine cycle is entered. This disables all subsequent

interrupts, saves the Program Counter and status flags, and
accesses the program memory vector location reserved for
that interrupt. This memory location and the next byte
contain the 16-bit address of the interrupt service routine for
that particular interrupt request. The Z8691 takes 63
crystal cycles to enter an interrupt subroutine.
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the interrupt
inputs can be masked and the Interrupt Request register
polled to determine which of the interrupt requests needs
service.

CLOCK
The on-chip oscillator has a high-gain, parallel-resonant
amplifier for. connection to a crystal or to any suitable
external clock source (XTAL1 = Input, XTAL2 = Output).

• AT cut, parallel-resonant

.The crystal source is connected across XTAL 1 and XTAL2,
using the recommended capacitance (CL =' 15 pf
maximum) from each pin to ground. The specifications for
the crystal are as follows:

• Series resistance, Rs'" 100 Q

• Fundamental type

• 8 or 12 MHz maximum

77

INSTRUCTION SET NOTATION
Addressing Modes. The following notation is _used to
describe the. addressing modes and instruction operations
as shown in the instruction summary.
IRR

Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Irr
X

DA
RA

1M
R
r
IR
Ir

RR

Symbols. The following symbols are used in describing the
instruction set.
dst
sre
ee
@

SP

PC
FLAGS

RP
IMR

Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pOinter (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol "+-". For
example,
dst ... dst

+ src

indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the following six
flags:
C
Z
S

V

o

H

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

Affected flags are indicated by:

o
1
*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

CONDITION CODES
Value

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

78

Mnemonic

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT

LE
UGE
ULT
UGT
ULE

Meaning

Always true
Carry
No carry
Zero
Not zeroPlus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
UnSigned less than or equal
Never true

Flags Set

C= 1
C=O
Z=1
Z=O
8=0
8= 1
V=1
V=O
Z= 1
Z=O
(8 XOR V) = a
(8XORV) = 1
[ZOR(8XORV)) = O.
[Z OR (8 XOR V)j = 1
C=O
C=1
(C = OANDZ = 0) = 1
(CORZ) = 1

INSTRUCTION FORMATS

CCF, 01, EI, IRET, NOP,
RCF, RET, SCF

OPC

dsl

INCr

OPC

Oae-Byte la.tructlon

I

OR 11 1 1 0 dst/sre

I

OPC
dst

I

CLR, CPL, DA, DEC,
DECW. INC, INew, POP,
PUSH, RL, RLC, RR,
RRC, SRA, SWAP

MODE

OPC
sre

OR
OR

dst

1 1 1 0
1 1 1 0

ADC, ADD, AND, CP,
LD, OR, SSC, SUS,
reM, 1M, XOR
dst

JP, CALL (Indirect)

OR 11 1 1 01

OPC

dst

MODE
ds1

SRP

OPC

OR 11 1 1 01

ADC, ADD, AND, CP,
LD, OR, SSC, SUS,
TCM, TM, XOR

dst

VALUE

VALUE
MODE
OPC

ACe, ADD, AND,
CPt OR, SBC, SUB,
TCM, TM, XOR

MODE

dst

OR

l'

1 1 1 0

sre

OR

1 1 1 0

dst

LD
1 1 01

sre

I

LD
OR

dst

MODE

LD, LDE, LDEI,
LDC, LOCI

dst/src
OPC
src/dst

OPC

sre

OPC

LD

OPC

JP

DAu
DAL

I

dst

LD

OPC

VALUE

I

CALL

OPC
DAu

R~ OPC

DAL

DJNZ, JR

dsl/CC

Three-Byte Instruction

Two-Byte Instruction

Figure 12. Instruction Formats

INSTRUCTION SUMMARY
AddrMode
Instruction
and Operation

Opcode
Byte
(Hex)

Flags Affected
Instruction
and Operation

C Z S V

o

ADCdst,src
dst ~ dst + src + C

(Note 1)

10

* * * *

0

ADDdst,src
dst - dst + src

(Note 1)

DO

* * * *

0

ANDdst,src
dst ~ dst AND src

(Note 1)

50

-** o ---

01

CALLdst
DA
SP ~SP - 2
IRR
@SP ~ PC; PC - dst

D6
D4

------

CCF
C-NOTC

EF

* -----

dst

src

H

Flags Affected
C Z S V 0 H

*

DECdst
dst ~dst - 1

R
IR

00
01

-***--

*

DECWdst
dst - dst - 1

RR
IR

80
81

-***--

IMR(7)~O

8F

------

DJNZ r,dst
RA
r~r - 1
Ifr*O
PC-PC + dst
Range + 127, - 128

-----rA
0 - F

R
IR

BO
B1

------

dst~O

COMdst
dst~ NOTdst

R
IR

60
61

-**

CP dst,src
dst - src

(Note 1)

AD

****--

DAdst
dst - DA dst

R
IR

40
41

***x--

CLRdst

AddrMode Opcode
Byte
dst src
(Hex)

0--

r

~

EI
IMR(7)~

9F

---------

-***--

R
IR

rE
0 - F
20
21

RR
IR

AO
AI

-* **--

1

INCdst
dst ~ dst + 1

INCWdst
dst -dst + 1

r

~

79

INSTRUCTION S.UMMA'RY (Continued)

Instruction

and OPeration

Addr Mode Opcode
Byte
dst src
(Hex)

BF

!RET

FLAGS .... @sp; SP - SP + 1

Flags Affected
CZSVDH

******

PC -@SP;SP-SP + 2; IMR(7)-1

JP cc.dst
ifcc is true
'PC-dst

DA

c
IRR

30

jRcc,dst
RA
if cc is true.
PC-PC + dst
Range: + 127, -128

cB

dst-src

r

R

r

X

X
r

r
Ir

Ir
R,

r

F3

.R

E4
E5

IR

E7

r
Irr

Irr

C2

,LDcldst,src
dst .... $rc
'r;"'r,+ 1; rr-'rr + 1

Ir
Irr

Irr
Ir

LPEds/,sre
dst-src

r
Irr

Irr

LD£I dst,src

Ir
Irr

Irr
Ir

1.00 dst,sre
dst-src

dlrt ... src
r;""r +1;'rr-rr + 1

SRA dst

c:m::::DJ R

CO

.

fR

C1

(Note 1)

3D

C

7

0

l@]

P

R
IR

* **

****

DF

1-----

DO

***0--

D1

1m

31

RP-src
SUBdst,sre
dst - dst - src

S~AP dst 17

E6
F5

C3
D3

55

(Note 1)

01 I~

20

FO
F1

TCMdst,src
(NOT dst) AND src

(Note 1)

60

TMdst,src
dstAND src

(Note 1)

70

XORdst,src
dst - dst XOR src

(Note 1)

BO

NOTE: These Instructions have an identical set of addreSSing modes.
which are encoded for breVity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
.symbolically by a [~ In this table, and its value IS found In the
following table to the left of the applicable addressing mode palf.

82

92

83
93

FF

--, --AfldrMode

(Note 1)

R

dst-@SP;
SP-SP + 1

IR

SP- SP - 1; @SP - src

IR

70
71

CF

0--:----

C-O
.RET

src

R

R

Ir

PUSHsrc
RCF

dst
50
51

R

AF

PC..-@SP;8P-SP + 2

80

0

For example. the opcode of an ADC instruction uSing the
addressing modes r (destination) and Ir (source) is 13.

'POPdst

RLast

*

7

SRPsrc

D2

NOP
ORdst,src
dst - ds! OR src

EO
E1

C-1

E3

1M
1M
R

IR
IR

l@] lIi:::j}J IRR

0

SCF

R

R
R

****--

7

SBCdst,src
dst-dst-src-C

rC
r8
r9
r= 0- F
C7
D7

C Z S V 0 H

c:m::::DJ IRR
C

RRC dst

Flags Affected

10
11

C

c=O-F

1m

LD dst,src

RLC dst
RR dst

cD
= 0'- F

Addr Mode Opcode
Byte
dst src
(Hex)

Instruction
and Operation

90
91

* *.*

*--

R

IR

R

1M

IR

1M

Lower
Opcode Nibble

REGISTERS

R240SI0
Serial 110 Register

R244 TO
Counter/Timer 0 Register

(FOH; Read/Write)

(F4H; Read/Write)

' - - - - S E R I A L DATA (Do '" LSB)

R241 TMR
Time Mode Register

R245PREO
Prescaler 0 Register

(F1 H; Read/Write)

(F5H; Write Only)

MODES
NOT T",,,
USED""
00 ]~

: ~~
INTERNAL CLOCK OUT .. 11
~~ g~~

~~

•
FUNCTION
1•
'" NO
LOAD
To

0 '" DISABLE To COUNT
1 '" ENABLE To COUNT

T MODES
EXTERNAL CLOCK IN~aT ;;; 00
GATE INPUT", 01

0 '" NO FUNCTION
1 '" LOAD T1
0 '" DISABLE 1, COUNT

(NON'R~~k~g~:~~:~~ ""

10
TRIGGER INPUT '" 11
(AETRIGGERABLE)

TIL
,

COUNTMODE

o '" To SINGLE·PASS
1 '" To MOOULO·N

RESERVED (MUST BE 0)
PRESCALER MODULO

1 '" ENABLE T1 COUNT

(RANGE: 1-64 DECIMAL
01-00 HEX)

R242 T1
Counter Timer 1 Register

R246P2M
Port 2 Mode Register

(F2H; Read/Write)

(F6H; Write Only)

R243PREl
Prescaler 1 Register

R247P3M
Port 3 Mode Register

(F3H; Write Only)

(F7H; Write Only)

I~I~I~I~I~I~I~I~I

~L
:

COUNTMODE
1 '" T 1 MODULO·N
0 '" T1 SINGLE·PASS

I

~.
L.

PULl.U. PS.OPEN
1 PORT '.
2 PULL·UPS
ACTIVEDRAIN
RESERVED (MUST BE 0)

CLOCK SOURCE
1 = T1 INTERNAL

o '"

T, EXTERNAL
TIMING INPUT
(T'N) MODE

PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

o P32

= INPUT
P35 '" OUTPUT
1 P32 = DAVOIRDYO P3s = RDYOIDAVO

o0

P33

= INPUT

~6} P33 =
11

L..._ _ _ _ _ _ ~

INPUT
RESERVED

P3.t

c

= OUTPUT

'1'34 = DfI1

~:~ ~ ~VU;R~~~ ~: ~~~~~uTI

'--------~ ;~ ~ ~~~~lIN :~ ~ ~;r,,~TO~T
L..._ _ _ _ _ _ _ _ ~

~!~:~ g~F

Figure 13. Control Registers

81

REGISTERS
(Continued)

R248 P01M
Port 0 Mode Register

R252 FLAGS
Flag Register

(F8H: Write Only)

(FCH: Read/Write)

MODE~
~-r
~
L

PO,-PO, 00
OUTPUT",

EXTERNAL
MEMORY TIMING
NORMAL' := 0
-EXTENDED = 1

H~~
'

Po,-PO,
MODE
00:: OUTPUT

LUSERFLAGF1

LUSER FLAG F2

= INPUT
lX :: As-A"

INPUT ,= 01
A12-AlS :: lX

01

,

STACK SELECTION
0 "" EXTERNAL
, = iNTERNAL

.

HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG

,

ZERO FLAG

RESERveD (MUST BE 0)

CARRY FLAG
'ALWAYS EXTENDED TIMING AFTER RESET

R2491PR
Interrupt Priority Register

R253 RP
Register Pointer

(F9H: Write Only)

(FDH: Read/Write)

I I III m_"" ,~" .~m

I~[~[~[~[~[~[~[~I

,,",",:J

IRQ3, IAQS PRIORITY (GROUP A)

RESERVED := 000
C > A > B :: 001
A > B > C = 010

.

o

= IROS > IRC3
1 = lRQ3 > IROS

.

A

>

C > B

=::

REGISTER
POINTER

011

~ ~ ~ ~ ~ ~ ~~~

IROO, IR02 PRIORITY (GROUP BJ
o = IRQ2 > IROO

B > A > C = 110
RESERVED =:; 111

1 '" IROO > IRQ2
IRQ1, IR04 PRIORITY (GROUP C)
IRQ1 > IRQ4

o=

1 = IRQ4 > IRQ1

R250lRQ
Interrupt Request Register

R254SPH
Stack Pointer

(FAH: Read/Write)

(FEH: Read/Write)

I~[~I~[~[~[~[~[~I
RESERVEO (MUST BE 0)

c=

T

IROO

P32 INPUT (Do = IROO)

IRQ1
IRQ2
IRC3

P331NPUT
P31 INPUT

IRQ4

P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT

IRQS

T,

R2511MR
Interrupt Mask Register

R255SPL
Stack Pointer

(FBH: Read/Write)

(FFH: Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

II

c=

1 ENABLES IRQO-IRQ5
(Do = IROO)

L--_ _ _ _ _ _ RESERVED (MUST BE 0)

'----,------1

ENABLES INTERRUPTS

Figure 13. Control Registers (Continued)

82

1'--___ ~~~~~S~~~~:~R

LOWER

OPCODEMAP
Lower Nibble (Hex)

o

4

i

e.

..,~
z
,a."

7

a.

:::l

9

A

B
C

0

E

F

4

A

B

C

o

6,5
LD
f1,IM

12110.0

6.5

JP
ccDA

INC

6.5

6.5

6.5

6.5

10.5

10.5

10.5

10,5

6,5

6,5

12110,5

12110,0

DEC
R,

DEC
IR,

ADD

ADD

ADD
IR2,R,

ADD
R"IM

ADD
IR"IM

LD

r1. lr2

ADD
R2,R,

LD

r,.r2

fl,R2

r2,R,

DJNZ
fl,RA

JR
cC,RA

6.5

6.5

6.5

6,5

10,5

10,5

10,5

10,5

RLC
R,

RLC
IR,

ADC

ADC

r,.r2

f1, lr2

ADC
R2,R,

ADC
IR2,R,

ADC
R"IM

ADC
IR"IM

6,5

6,5

6,5

6,5

.1D,5

10,5

10,5

10,5

INC
R,

INC
IR,

SUB
f,J2

SUB

SUB
H2,R,

SUB
IR2,R,

SUB
R"IM

SUB
IR"IM

8,0

6,1

6,5

6,5

10,5

10,5

10,5

10.5

JP
IRR,

SRP
1M

SBC

SBC

r"f2

r1, lr2

SBC
R2,R,

SBC
IR2,R,

SBC
R"IM

SBC
IR"IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA
R,

DA
IR,

OR

OR

f,.r2

f1, lr2

OR
R2,R,

OR
IR2,R,

OR
R"IM

OR
IR"IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP
R,

POP
IR,

AND

AND

'1,f2

f1, lr2

AND
R2,R,

AND
IR2,R,

AND
R"IM

AND
IR"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM
R,

COM
IR,

TCM

TCM

f',(2

(1, lr2

TCM
R2,R,

TCM
IR2,R,

TCM
R"IM

TCM
IR"IM

10112,1

12114,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH
R2

PUSH
1R2

TM

TM

r,.r2

".lr2

TM
R2,R,

TM
IR2,R,

TM
R"IM

TM
IR"IM

10,5

10,5

12,0

18,0

DECW
RR,

DECW
IR,

LDE
f1, lrr2

LDEI
Ir1,lrr2

12,0
LDE
r2,lrf,

18,0
LDEI
Ir2,lrr,
6,5
CP
'1, lr2

6,5

6,5

RL
R,

RL
IR,

10,5

10,5

6,5

INCW
RR,

INCW
IR,

'1,f2

CP

f"

lr2

E

r1

F

r---I-----

r---I-----

r---r---I-----

r---6.1
01

~
EI

r---14,0

10,5

10,5

10,5

10,5

CP
R2,R,

CP'
IR2,R,

CP
R"IM

CP
IR"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR
R,

CLR
IR,

XOR
",(2

XOR

XOR
R2,R,

XOR
IR2,R,

XOR
R"IM

XOR
IR"IM

f1, lr2

RET

~
IRET

r---6,5

10,5

6,5

6,5

12,0

18,0

RRC
R,

RRC
IR,

LDC

LOCI

LD

f1, lrr2

Ir1,lrr2

fl,x,R2

RCF

6,5

6,5

12,0

18,0

20,0

20,0

10,5

I----6,5

SRA
R,

SRA
IR,

LDC
f2,lrr,

LOCI

CALL
DA

LD

SCF

Ir2.lrr1

CALL"
IRR,

r2,x,R 1

.

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RR
R,

RR
IR,

LD
r" IR 2

LD
R2,R,

LD
IR2·R,

LD
R"IM

LD
IR"IM

8.5

8,5

6,5

10,5

SWAP
R,

SWAP
IR,

LD
Ir,.f2

LD
R2, IR ,

. . .----...v"'----...

~
CCF

r---6.0
NOP

v"'----.. "'------v...-----...j~'---v--'

j .....- - - -...

j

..

3

3
Bytes per Inslructlon

EXECUTION
CYCLES

PIPELINE
CYCLES

Legend:
R = 8-blt address
r = 4-bit address
R1 or r 1 "" Dst address

MNEMONIC

R2 or f2 "'" Src address

Sequence:
Opcode, First Operand. Second Operand

FIRST
OPERAND

SECOND
OPERAND

NOTE: The blank areas are not defined

~

*2-byte instruction; fetch cycle appears as a 3-byte instructloo

83

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins except RESET
with respect to GND ............... - 0.3V to + 7.0V
Operating Ambient
Temperature ........... , ... See Ordering Information
Storage Temperature .............. ..:. 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
+5V

The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.

2.1K

Standard conditions are as follows:

• + 4.75V <; Vcc <; + 5.25V
• GND == OV
• O°C<; TA <; + 70°C for S (Standard temperature)
•

- 40°C <; TA <;

+ 100°C for E (Extended temperatu(e)

Figure 14. Test Load 1

DC CHARACTERISTICS
Symbol

Parameter

Min

Max

Unit

Condition

VCH

Clock Input High Voltage

3.8

Vcc

V

Driven by External Clock Generator

VCl

Clock Input Low Voltage

-0.3

0.8

V

Driven by External Clock Generator

VIH

Input High Voltage

2.0

Vcc

V

Vil

Input Low Voltage

-0.3

0.8

V

VRH

Reset Input High Voltage

3.8

Vee

V

VRl

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

V

IOH == - 250 fAA

VOL

Output Low Voltage

0.4

V

IOl ==

III

Input Leakage

-10

10

fAA

VIN == OV, 5.25V

IOl

Output Leakage

-10

10

fAA

VIN == OV, 5.25V

IIR

Reset Input Current

-50

fAA

VCC ==

Icc

Vee Supply Current

180

rnA

All outputs and 1/0 pins floating

84

2.4

+ 2.0 mA

+ 5.25V, VRl

== OV

)

}(
~I

.-@PORTO,

bM

)
I

PORT 1

)

Ao-A,

)!

.

16

~

<

•

CD

I--®----i'

(READ)

Ao-A,

PORT 1

•

CD

~I •

1-0-

<

-- ~1\
01...

-le under software control.
Two basic address spaces are available: program memory
and the intemal register file. The register file is composed
of 124 general purpose 8-bit registers, three I/O port registers, and 15 control and status registers.
To unburden the program from coping with real-time
problems two counterltimers with a large number of userselectable modes are offered on-chip.

P2u-P2.,. I/O Port Lines (inputs/outputs, CMOScompatible). The eight lines of Port 2 are programmable as inputs
or outputs on a line by line basis (Figure 3).
P3,-P33 • Input Port Lines (inputs, CMOS compatible).
The three lines of Port 3 are programmable as digital or
analog comparator inputs on a group basis (Figure 3).
XTAL IN, XTAL OUT. Crystal In, Crystal Out (time-base
input and output). These pins connect a parallel-resonant
crystal (12 MHz maximum) or an external single-phase
clock (12 MHz maximum) to the on-chip clock oscillator
and buffer.

ADDRESS SPACES:
Program Memory. The program counter addresses 2K
bytes of program memory space as shown in Figure 4.
The first 12 bytes of program .memory are reserved for the
interrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts.
Register File. The register file includes three VO port registers , 124 general purpose registers (R4 - R127), and 15
control registers (R240 - R255). These
registers are assigned the address locations shown in
Figure 5.

Instructions can access registers directly or indirectly with
an 8-bit address field. The Z86C08 also allows short 4-bit
register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the register file is
divided into eight working register groups, each occupying
16 contiguous locations. The Register Pointer addresses
the starting location of the active working-register group
(Figure 6).
STACKS. An 8-bit Stack Pointer (R255) is used for the
internal stack that resides within the 124 general purpose
registers (R4 - R127).

XTAL

INPUT

110
(BIT PROGRAMMABL.E)

110

Figure 3. Functional Block Diagram

90

COUNTERITIMERS:

110 PORTS:

The Z86COS contains two 8-bit programmable counterl
timers (TO and T1 ). each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by
intemal or extemal clock sources; however. the TO prescaler is driven by the intemal clock only.
The 6-bit prescalers can tfivide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter. which decrement the value (1 to 256) that
has been loaded into the counter. When th$ counter
reaches the end of count. a timer intenupt request - IRQ4
(TO) or IRQ5 (T1) - is generated.
Th$ counters can be started. stopped. restarted to continue. or restarted from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode). The
counters. but not the prescalers. can be read at any time
withollt d'lSturbing their value or count mode.
The clock source for T1 is user-definable and can be
retriggerable or non-retriggerable. or a gate input for the
intemal clock.
'

The Z86C08 has 14 lines dedicated ,to input and output.
These lines are grouped into three ports and are configurable as input or output. All ports have active pull-ups and
pull-downs compatible with CMOS loads.
Port 0 can be programmed on either inputs or outputs. The
configuration is shown in Figure 7.
Port 2 bits can be programmed independently as input or
,output. In addition. Port 2 can be configured to provide
open-drain outputs. The configuration is shown in Figure 8.
Port 3 lines can be configyred as digital inputs. analog
inputs. or control lines. In all cases. the direction of thase
three lines is fixed as inputs.
'
Port 3 can also provide the following control functions:
fourextel11a1 intenupt request signals(IRQO. IRQ1. IRQ2
and IRQ3) or timer input signal (TIN). The configuration of
Port 3 is shown in Figure 9.
.

LOCATION

25'

IDENTIFIERS
STACK POINTER (BITS 7-0)

,PL

RESERVED

253
252

...
..
....
..
,.

,
,
,
,
,
,

'51

247

~r-------------~
ONoCHIP
ROM

LOCATION OF
AAST BYTE OF

INS:;~;J~~:~ ~ _ _ _ _ _ .... _ _ _ _ _
AFTER RESET

12

F-------:::::::------i

11

IRQ5

10

IRQ5

'"
'"

REGISTER POINTER

FLAGS

INTERRUPT REQUEST REGISTER

IMR
IRQ

INTERRUPT PRIORITY REGISTER

IPR

PORTS 0-1 MODE

P3M
P'M

TO PRESCAlER

PREO

THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTtVE WORKINQ.REGISTER GROUP.

1

"

TO

T1 PAESCALER

PRE1

TIMER/COUNTER 1

T'
TMR

TIMER MODE"

1

NOT
IMPLEMENTED

1

IRQ4

1

IRQ4

'RQ3

. INTERRUPT
VECTOR
(LOWER BYTE)

1RQ3

•

INT~:=/3
(UPPER BYTE)

253

P01M

POAT 3 MODE
PORT 2 MODE
TIMER/COUNTER 0

0000

RP

PROORAM CONTROL FLAGS

INTERRUPT MASK REGISTER

GENERAL·PURPO$E

SPECIFIED WORKING·
REGISTER GROUP

..

REGISTERS

THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
PROVIDEDS'f
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGI.STER.

1

IRQ2
IRQ2

1001

PORT 3

P3

1RQ1

PORT2

IRQO

.....RVED

P'
P'
PO

IRQO

Figure 4. Program Memory Map

Figure 4. Program Memory Map

PORTO

Figure 5. Register File

Figure 5. Register File

1
,
1r----.OPORTS---- 3
Figure 6. Register Pointer

Figure 6. Register Pointer

91

INTERRUPTS:
The Z86C08 allows six different interrupts from five
sources: the three Port 3 lines P31 - P33, both. the rising
and falling edge of P32 (AN2), the falling edge of P31
(AN1)·and P32 (REF - Figure 9), and the two counter!
timers. These interrupts are bQth maskable and prioritized. The Interrupt Mask Register globally or individually
enables or disables the six interrupt requests. Whe'1 more .
than one interrupt is pending, priorities are re~olved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All ZB6COB interrupts are vectored through locations in
program memory. When an interrupt request is granted,
an interrupt machine cycle is entered. This disables all
subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory vector
location reserved for that interrupt. This memory location
and the next byte contain the 16-bit address of the interrupt
service routine for that particular interrupt request.
Polled interiupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs
can be masked and the interrupt request register polled to
determine which of the interrupt requests needs service.
Interrupt sources and corresponding interrupts are shown
in Table 2.
'

STANDBY MODE:
The ZB6COB has two standby modes which are entered by
executing either:
• STOP

•

HALT

The STOP instruction stops the internal clock and external
crystal oscination; the HALT instruction stops the. internal
clock but not crystal oscillation.
.
The STOP mode can be released by two methodS. The
first method is a RESET of the de.vice by removing Vcc. The
second method is if P27 is configured as an input line when
the device executes the STOP instruction. A low input
condition on P27 releases the STOP mode. Program execution under both conditions begins at location
%OOOC(HEX). However, when P27 is used to release the
STOP mode the 110 port mode registers are not reconfiguredto their default power-on conditions. This prevents any
110, configured as output when the STOP instruction was
executed, from glitching to
unknown state.
'
The HALT mode is released by an interrupt on Port 3 input,
a time-out in Timer 0 or Timer 1, or by a RESET of the
device. To complete an instruction prior to entering standby
mode,use the instructions:

an

NOP
HALT or STOP
To use the P27 release approach with STOP mode, use the
following instructions:

OR P2,#%80
NOP
STOP
RESET:
Power-On Reset is in the Z86C08. The ZB6COB waits for
10 to 25 rns + 18 crystal clocks (Figure 10) while power is
on, and then jumps to the starting address %OOOC(HEX).
The control Register reset value is listed in Table 1.

.

J. . . . ",

"'----<:'Of--,-------r-...............n~y ON PI?

Figure 7. Z86COB Port 0 Configuration
92

Figure B. ZB6COB Port 2 Configuration

Table 1. Z86C08 Control Registers
86C08 control registers:
P3t DATA

)-__~===:~~=L========;==l=J==:UT~

P:l3DATA
L -______~~~--~----------~~=:L.~

~iI.l.2=~E!XECC1'ECTXOH

ZRQ

3

= FWIJ:N(;; EDGE:

Addr. 'eg.

Reset condition

F1

THR

00000000

F2

T1

UUUUUUUU

F3

PREl

UUUUUUOO

F4

TO

UUUUUUUU

F5

PREO

U U U U U U U 0

F6 •
F7 •

""

P'H

U U U U UU 0 0

F8 •

P01M

U U U 0 UU 0 1

F9

IPR

U U U U UU U U

FA

IRQ

U U 0 0 0 0 0 0

Commments

Inputs after
Reset

11111111

DETtcTION

Figure 9. Z86C08 Port 3 Configuration

IRQ3 is
used for
pos. edge

detection

F8

IHR

oU

FC

FLAGS

UUUUUUUU
00000000

FD

RP

FE

SFH

U U U U U U U U

FF

'PL

U U U U U U U U

*

INT. OSC.

U U UU U U

Not used,
stack always
internal

Not reset after a low on P27 to get out of stop mode

Table 2. Interrupt Types, Sources, and Vectors

XTAL OSC.

CHIP RESET

Vector
location
0,1 External
External
External

Comments

+Edge Trig.
+Edge Trig.

Edge Trig.

Figure 10. Internal Reset Configuration

93

WATCHDOG TIMER (WDT):

WDT: 5F(HEX).

The crystal source is connected across XTAL IN and XTAL
OUT, using the recommended capacitors (CL =15 pF) from
each pin to ground. The specifications for the crystal are
as follows:
-

CLOCK:

-AT cut, parallel resonant

The Watch Dog Timer (WOT) should be refreshed within
15 ms. If not refreshed, then the Z86C08 resets itself.

The 'In-chip oscillator has a high-gain, parallel-resonant
amplifier for connection to a crystal, ceramic resonator, or
to any suitable external clock source (XTAL IN = Input,
XTAL OUT =Output).

- Fundamental type, 12 MHz max
- Series resistance, RS:100 ohm
The oscillator configuration is shown in ~igure 11.

XTAL-IN

1/2 DXVlDER
XTi'L.

CLOCK

SYSTEM CI..OCK

Figure 11 . Z86C08 Crystal Input Config.

PORT 3 CQMPARATORS:

The 86C08's port 3 inputs include two analog comparators
for added interface flexibility. Interrupts are generated on
either edge of comparator 2's output, or on the falling edge
of comparator 1's output. The block diagram is shown in
Figure 9. , Comparator outputs may be used for interrupt
generation, Port 3 data inputs, or Tin in the case of AN1
(P31). Alternatively, the comparators may be disabled,
freeing the reference input (P33) for use as IRQ1 and/or
P33 input.

94

The dual comparator (common inverting terminal) features a single power supply which discontinues power in
stop mode. The common voltage range is 0-4V; the power
supply and common mode rejection ratios are 90db and
60db, respectively. See comparator specifications for details (Page 16).
Typical applications for the on-board comparators include:
zero crossing detection, analog-to-digital conversion, voltage scaling, and threshold detection.

INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
.
Indirect working-register address only
Register pair or working register pair address

IRR
Irr
X

DA
RA

1M
R
r
IR
Ir
RR

Symbols. The following symbols are used in describing the
instruction set.
dst

src
cc
@

SP
PC
FLAGS

RP
IMR

Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol "+-': For
example,
dst +- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of ~ given
location. For example,
dst(7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the following six
flags:
C
Z
S
V

o
H

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

Affected flags are indicated by:

o
1

*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

CONDITION CODES

Value

Mnemonic

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010

C
NC
Z
.NZ
PL
MI
OV
NOV
EQ
NE
GE
LT

0010
1111
0111
1011
0011
0000

GT
LE
UGE
ULT
UGT
ULE

Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equa~
Unsigned greater than or equal
Unsigned less than
UnSigned greater than
UnSigned less than or equal
Never true

Flags Set

C=1
C=O
Z= 1
Z=O
8=0
8 = 1
V= 1
V=O
Z= 1
Z=O
(8XORV) = 0
(8XORV) = 1
[ZOR (8XOR V)] = 0
[ZOR (8XORV)j = 1
C=O
C= 1
(C=OANDZ=O)=1
(CORZ) = 1

95

INSTRUCTION FORMATS
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF

OPC

ope

ds.

INCr

One-Byte Instructions
OPC

MODE

CLR, CPL, DA, DEC,

I

dsYsrc

OR 11 1 1 0 dotlsrc

I

OPC

~~~~' ~~~Rt~?~R."OP,
RRC, SRA, SWAP

r----'O":'d:-=~'--'-II

JP, CALL
OR 11 1 1 01

OR
OR

MODE,
dst'
OR 111101
VALUE

SRP

MODE

dst/src
ope
srelds.

dst

OPC

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

AbC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

LD
OR
OR

MODE

OPC
areldst

sre
ds. '

OPC

ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
MODE
d.U.rc

1110
1 1 1 0

~ndirecI)

dsl

OPC
VALUE

MODE

sre
ds.

1 1 1 0
1 1 10

OPC

src
dot

LD

dst'src

LD, LDC, LDCI

ADDRESS

OR

11

1 1

01

LD

cc

arc

JP

OPC
DAu
D"

I

dsl
OPC
VALUE

LD

I dstiCCR~ OPC

OPC
DAu
DAL

DJNZ, JR

Two-Byte Instructions

CALL

Three-Byte Instructions
Figure 12, Instruction Formats

INSTRUCTION SUMMARY
Instru,ction
and Operat!on

AcIdrMode Opcode
Byte
(Hex)
dst src

Flags Affected
CZSVDH

Instruction
and Operation

'AcIdrMode Opcode
Byte
dst src
(Hex)

ADCdst,src
ds! - dst + src + C

(Note 1)

10

* * * *

o

ADDdst,src
dst - ds! + src

(Note 1)

00

* * * *

o

ANDdst,src
dst - ds! AND srt;

(Note 1)

50

-** 0

DI
IMR(7) -0

CALLdst
DA
SP-SP - 2
IRR
@SP - PC; PC - dst

D6
D4

------

CCF
C-NOTC

EF

*-----

DJNZr,dst
RA
r-r-1
if r" 0
PC-PC + dst
Range: + 127, -128

C Z S V D H

*

DECdst
dst-dst - 1

R
IR

00
01

-** *--

*

DECWdst
dst-dst - 1

RR
IR

80
81

-** *--

8F

------

CLR ds!
dst-O

R
IR

80
81

------

COMdst
ds!-NOTdst

R
IR

60
61

-**O~-

CPdst,src
,dst - src

(Note 1)

AD

* * * *--

DAdst
dst-DAdst

R
IR

40
41

***x--

96

Flags Affected

rA
-----r=O-F

EI
IMR(7)-1

9F

HALT

7F

INCast
dst -dst + 1
R
IR
INCWds!
dst-dst + 1

RR
IR

------

rE
r=O-F
20
21
AO
A1

* * *,

-***--

INSTRUCTION SUMMARY (Continued)
Instruction
and Operation

Addr Mode Opcode
Byte
dst src
(Hex)

IRET

BF

FLAGS - @SP; SP - SP + 1
PC-@SP;SP-SP + 2; IMR(7)-1
JPcc,dst
ifcc is true
PC-dst

OA

cO
c=O-F

IRR

30

JRcc,dst
RA
if cc is true,
PC-PC + dst
Range: + 127, -128

LO dst,src
, dst-src

LOCdst,src
dst-src

LOCI dst,src
dst - src
r - r + 1; rr - rr + 1

r

X

X
r

r
Ir
r

07

R

E4

IR

E5
E6

IR
IR

1M
1M
R

r

Irr

dst-src

Irr

LOEI dst,src

Ir
Irr

dst - src
r-r + 1; rr-rr + 1

***

Irr
Ir

EO

0

****

E1

RRC dst r=--==:=l R

CO
G1

SBCdsl,src
dst ~dst -src-C

3D

(Note 1)

SCF

~IR

SRPsrc
RP-src

'1m

STOP

****--

OF

1-----

00
01

***0--

31
6F

SUBdst,src
dst - dst - src

F3

SWAP dst I'

52

(Notet)

20

R

FO
F1

(Note 1)

60

(Note 1)

70

,,-.,~....:I:-...,..-"I'IIR

TCMdst,src

X

**

X

(NOT dst) AN'O src

E7
F5

TMdst,src
dstANOsrc

C2

WDT

C3
03
82
92

Irr
It

, 83
93

(Note 1)

5F - - - - - -

XORdst,src
dst - dst XOR src

(Note 1)

BO

-

**

0 --

NOTE, These instructions have an identical set of addressing modes,
which are encoded for brevity, The first opcode nibble is found In
the instruction set table above, The second nibble IS expressed
symbolically by a 0 In this table, and ItS value is found In the
following table to the left of the applicable addressing mode pair
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) IS 13,

40

AddrMode
dst

src

Lower
Opcode Nibble

50

R
IR

51
Ir

PUSHsrc
SP - SP - 1; @SP - src

RCF

R

70

IR

71
CF

0-----

C-O

RET

AF

PC - @SP; SP - SP

7

CZSVOH

C-1

FF

POPdst
dst-@SP;
SP-SP + 1

c

~~IR

E3

Irr

NOP
'ORdsl,src
dst - dst OR src

LEI LE::i)J IRR

Flags Affected

02

Irr

LOE dsl,src

RR dst

~

Addr M,ode Opcode
Byte
dst src
(Hex)

SRAdstC0~R
R

Ir
Irr

**

rC
r8
r9
r= 0 - F
C7

r
R

Ir

CZSVOH

Instruction
and Operation

cB
c=O-F

1m

R
R
R

Flags Affected

R

R

R

IR

R

1M

IR

1M

+2

RL dst _ r::=:l R
~IR

90

RLC dst r=-~ R

10

~IR

11

* * * * -,-

9t

****-97

OPCODEMAP
Lower Nibble (Hex)

6

.....
e.

I
;;;

a.
a.

::>

A

B

C

o
E

F

6

7

A

B

C

o

6.5

'2110.5

'2110.0

65

'2110.0

'65

LD

LD

DJNZ

f,.R2

f2· R ,

65

65

6.5

6.5

'05

'0.5

10.5

'0 5

65

DEC
R,

DEC
IR,

ADD
(,.f2

ADD
r,.lr2

ADD
R2· R ,

ADD
IR2·R,

ADD
R,.IM

ADD
IR,IM

65

65

6.5

6.5

10.5

10.5

105

10.5

RLC
R,

RLC
IR,

ADC
r,J2

ADC
f,.lr2

ADC
R2· R,

ADC
IR2 R,

ADC

ADC
IR,.IM

65

6.5

6.5

65

10.5

10.5

10.5

105

INC
R,

INC
IR,

SUB

SUB

"·'2

".lr2

SUB
R2· R,

SUB
IR2·R,

SUB
R,.!M

SUB
IR,.IM

80

6.1

6.5

6.5

10.5

10.5

105

10.5

JP
IRR,

SRP
1M

SBC
(,.f2

SBC

SBC

r,. lr2

SBC
R2· R,

1R2·R,

SBC
R,IM

SBC
IR,.IM

8.5

85

6.5

6.5

10.5

10.5

10.5

10.5

DA
R,

DA
IR,

DR
(,.f2

DR

DR
R2· R,

DR
IR2·Rr

DR
R,.IM

DR
IR,.IM

10.5

10.5

6.5

6,5

10,5

10,5

10,5

10,5

PDP
R,

POP
IR,

AND

AND
f,. lr2

AND
R2· R,

AND
IR2,R,

AND
R,.IM

AND
IR"IM

r,.r2

".lf2

R,IM

65

6.5

6.5

6,5

10,5

10,5

10.5

10.5

COM
R,

COM
IR,

TCM

TCM

TCM

TCM

" r2

".lr2

R2,R,

1R2·R,

TCM
R,IM

TCM
IR"IM

10112.1

12114.1

65

6.5

10.5

10,5

10.5

10,5

PUSH
R2

PUSH
IR2

TM

TM
", lr2

TM
R2,R,

TM
IR2·R,

TM
R"IM

TM
IR"IM

10.5

10,5

DECW
RR,

DECW
IR,

65

6.5

RL
R,

RL
IR,

r,J2

f,

RA

JR

LD

JP

INC

cc RA

(,IM

cc DA

r'

-

!-------

'.0

WOT

I-----

.6,0

t---7,0

HALT

~
01

t---6 ,
EI

10.5

10.5

6.5

6.5

10,5

10,5

10,5

10.5

f-;:;o

INCW
RR,

INCW
IR,

CP

CP
r, Ir2

CP

CP

CP

RET

R2· R ,

IR2 R,

CP
8 1 1M

f'.[2

IR,IM

65

6.5

6,5

6,5

10,5

10,5

10.5

10,5

CLR
R,

CLR
IR,

XOR

XOR
".lr2

XOR
R2,R,

XOR
IR2·R,

XOR
R,IM

XOR
IR,.IM

f'·'2

f--;6o
IRET

65

6,5

12,0

10.5

~

RRC
R,

RRC
IR,

LDC

LOCI

LD

RCF

(, Irr2

Ir,,1rr2

r,.x R2

18,0

6.5

6.5

12,0

18,0

20,0

20,0

10,5

SRA
R,

SRA
IR,

LDC

LOCI
Ir2,lrr,

CALL"
IRR,

CALL

,LD
r2,>< R,

f2·lrr,

DA

6.5

6.5

6,5

10,5

10,5

10,5

10,5

RR
R,

RR
IR,

LD

r,.IR2

LD
R2,R,

LD
IR2,R,

LD
R,.IM

LD
IR"IM

85

8,5

6,5

SWAP
R,

SWAP
IR,

LD

LD

Ir,.r2

R2·IR,

'65
SCF

'65
CCF

t----

10,5

60

NDP

. . . - - - -.. . . ."'----....
.
,1--...- - - -.. . . "'-----',1
..
. . . - - - - -.....v ...------,1~"____'"
Bytes per Instruction

EXECUTION
CYCLES

4

PIPELINE
CYCLES

Legend:
R ;; B-bit address
r ;; 4-bit address

R1 or r1 ;; Ost address
MNEMONIC

R2 or '2 ::::: Src a8dress
Sequence:
Opcocte, First Operand, Second Operand

FIRST
OPERAND

• 2-byte Instrucllon. fetch cycle appears as a 3-byte Instruction

98

SECOND
OPERAND

NOTE: The blank areas are not defined.

R241 TMR
TIMER MODE REGISTER

R245PREO
PRESCALER 0 REGISTER

(F1 H: Read/Write)

(F5H: Write Only)

X
T MODES
EXTERNAL CLOCK INplOr = 00
GATE INPUT = 01
TRIGGER INPUT = 10

(NON-RETRIGGERABLE)
TRIGGER INPUT

j

lS~

~

o = NO FUNCTION

~I

1"" LOAD To

-

0 = DISABLE To COUNT
1 "" ENABLE To COUNT

0 =
1 =
0 =
-1 =

COUNT MODE
0 = To SINGLE PASS
1 = To MOOULO·N

,"'~'. ,~

•

X

NO FUNCTION
LOAD T,
DISABLE T I COUNT
ENABLE T, COUNT

.

,",-

PRESCALER MODULO

01-00 HEX)

= 11

(RETRIGGERABLE)

R242 T1
COUNTER TIMER1 REGISTER

R246P2M
PORT 2 MODE REGISTER

(F2H: Read/Write)

(F6H, Write Only)

I~I~I~I~I~I~I~I~I

L

~

Tl INITIAL VALUE (WHEN WRITTEN)

--(RANGE 1 256 DECIMAL 01 00 HEX)
T, CURRENT VALUE (WHEN READ)

R247P3M
PORT 3 MODE REGISTER

R243 PRE1
PRESCALER 1 REGISTER
(F3H, Write Only)

(F7H; Write Only)

I~I~!~I~I~I~I~I,I

~L

1 PORT 2 PULL·UPS ACTive

1 '" T 1 MQDULO·N

CLOCK SOURCE
1 " T 1 INTERNAL

o '"

"
•

I L ...""~",,.",-..·

COUNTMODE
o = Tl SINGLE-PASS

PORT 3 INTERRUPTS
DIGITAL
1 ANALOG

T, EXTERNAL TIMING INPUT

o

(TIN) MODE
PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

'------X

R244 TO
COUNTER/TIMER 0 REGISTER
(F4H, Read/Write)

To INITIAL VALUE (WHEN WRITTEN)
L---_ _ _ (RANGE 1 256 DECIMAL 01 00 HEX}

To CURRENT VALUE (WHEN READ)

NOTE: All "don't care" bits return a "1" when read.

Figure 16 Control Registers

99

R252 FLAGS
FLAG REGISTER

R248 P01M
PORT 0 AND 1 MODE REGISTER
(!'SH Wflte Only)

(FCH: Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

X TlSLPO&iiP~'~~T":uT
01

=

I

U~~
L

INPUT

X

LUSER

FlAG

F.

USER FLAG F2

HALF CARRY flAG
DECIMAL ADJUST FLAG

OVERFLOW FLAG

SIGN flAG
ZERO FLAG

MUSTBEO

CARRY FLAG

R2491PR
INTERRUPT PRIORITY REGISTER

R253RP
REGI'sTER POINTER

(F9H: Wflte Only)

(FDH: Read/Write)

I~!~!~!~I~:~:~:~I

IIIII"'~""··"'·~'
RESERVED" 000

IRQ,3, IROS

PR~O:IJ~d~~O:Q~),

.:J

1 " IRQ3 > IROS

IROO, IRQ2 PRIORITY (GROUP 8)
o IRQ2 > IROO
_
1 '" IROO > IRQ2

=

~ ~ ~ ~ ~ ~ ~~~

REGISTER

POINTER

A> C > B '" 011
B > C > A = 100
C ;:> B > A '" 101
B > A > C
110

=

'

RESERVED" 111

IRQ1, IRQ4 PRIORITY (GROUP C)

o '"
1

IRQ1

= IFlQ4

>

iFlQ4

> IR01

R250 IRQ
INTERRUPT REQUEST REGISTER

R255 SPL
STACK POINTER

(FAH, Read/Write)

(FFH: Read/Write)

L

I~I~I~I~I~I~I~I~I
RESERVED

T

I~!~I~I~I~I~I~I~I
IRQO. P32INPUT

IRQ! _ P33INPUT
IRQ2 _ P31 INPUT
IROO _ P32iNPUT
IRQ4-TO'

" 1_ _ _ _

IRQ5_ T1

R25l1MR
INTERRUPT MASK REGISTER
(FBH: Read/Wflte)

ID,!D6iDSID4:D)!~101:~1

I'

c=

1 ENABLES IROO-IROS

(Do = IROO)

' - - - - - - - RESERVED

' -_ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

Figure 16 Control Registers (Continued)

100

~~~~7S;~~~;~R

LOWER

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... - 0.3V to + 7.0V
Orerating Ambient
Temperature ..
.See Ordering Information
Storage Temperature.
. .... - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation' of the device at any condition above those Indicated In'the
operational sections of these specifications is not Implied .. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability,

STANDARD TEST CONDITIONS

+5V
2.1K

The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin (Figure 13).
Standard conditions are as follows:

•

+4.5 V <_ Vee <_ +5.5 V

• GND = OV

Figure 13. Test Load 1

vc;c = 3.0 to 5.5V

Z86C0808PSC DC CHARACTERISTICS
Symbol

VeH
VeL
VIH
VIL
VRH
VRL
VOH
V01.1
VOL2

IlL
101.

IIR
Icc
leel
lec2

Parameter

Min

Max Input Voltage
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage

.9V ee

RESET Input High Voltage
RESET Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage

Input Leakage
Output Leakage
RESET Input Current
Supply Current
Standby Current
Standby Current

Note:
1. Iccl
Clock driven on XTAL
Resonator or Crystal

Typ

Vee +0.3
·1Vee
Vee +0.3
.2Vee
Vee +0.3
.2Vc;c

.7V..
-0.3
Vee-O.4

-10
-10
-10

Typ.

Max.

O.3mA
3.0mA

5.0.mA
5.0mA

0

Unit

Max
12.0

-0.3
.7Vc;c
-0.3

OoC to 70 C

V
V
V
V
V

0.4
0.8

V
V
V
V
V

10
10
-SO
15
5
10

uA
uA
uA
rnA
rnA
uA

Condition
liN 2S01JA .
Driven by external CG
Driven by External CG

IOH =-2.0mA
IOL =+4.0mA
IOL =+12mA, 3 pins max.
VIN =OV, Vec
VIN =OV, Vce
Vec = 4.S to S.SV, VRL = OV, P27
All Output & I/O pins float
HALT Model VI" =OV, Vee
STOP Mode VI" = OV, Vee

101

Z86C0808PEC DC CHARACTERISTICS
Symbol

Parameter

Min

VCH
VCl
VIH
Vil

Max Input Voltage
Clock Input High Voltage
Clock Input Low Voltage
Input High' Voltage
Input Low Voltage

VRH
VRl
VOH
VOll
VOL2

RESET Input High Voltage
RESET Input Low Voltage
Output High Voltage
Outpuf Low Voltage
Output Low Voltage

III
IOl
IIR
Icc
Icc,
lec2

Input Leakage
Output Leakage
RESET Input Current
Supply Current
Standby Current
Standby Current

Note:
1. Iccl
Clock driven on XTAL
Resonator or Crystal

Typ

Unit

Max
12.0

.9Vcc
-0.3
0.7Vcc
-0.3

Vcc +0.3
.1Vcc
Vcc +0.3
.2Vcc

.7V""
-0.3
Vcc-0.4

Vee +0.3
.2 V""

-10
-10
-10

Typ.

Max.

O.3mA
3.0mA

5.0mA
5.0mA

0.4
0.8

V
V
V
V
V

10
10
-50
15
5
20

uA
uA
uA
rnA
rnA
uA

Figure 14. Additional Timing

102

V
V
V
V
V

Condition
liN 250J.IA
Driven by external CG
Driven by External GG

IOH = -2.0mA
IOl = +4.0mA
IOL = +12mA, 3 pins max.

VIN = OV, Vec
VIN = OV, Vcc'
Vce = 4.5 to 5.5V, VRl = OV, P27
All Output & 110 pins float
HALT Mode' Vln=OV, Vee
STOP Mode Vln ';' OV, Vee

AC CHARACTERISTICS
Number

1
2
3

4
5

6

7

SA
9

Symbol

Parameter

Min

TpC
TrC, TfC
TwC
TwTinL
TwTinH

Input Clock Period
Clock Input Rise and Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width

125

TpTin
TrTin,TfTin
TwlL
TwlH

Timer Input Period
Timer Input Rise and Fall Times
Int. Resquest Input Low Time
Int. Request Input High Time

STpC

Max

Notes

100,000
25

37
100
3TpC

100
100
3TpC

1
1
2
2

2
2
2,4
2,3

NOTES:
1.
2.
3.
4.

Clock timing references use Vee for a logic "1" and Vssfor logic "0".
Timing references use Vco for a logic "1" and Vss for a logic "0".
Interupt request via P31- P33
.
Interrupt request via P31-P33

'Units in nanoseconds (ns)

PRELIMINARY Z86C08 COMPARATOR SPECIFICATIONS

S

Parameters
Offset
Voltage (mv)
Internal
Delay Time (us)
Overdrive (mv)

CASE 1
·VDD=2.5V
Temp=40C o

-

+50 (est)
15 (max)
-+300

CASE 2
VDD=2.5V
Temp=85Co

-

+50 (est)
15 (max)
-+300

lBi'S (rna)
Power (mw)

0.1 (max)
0.25

0.1 (max)
0.25

Power Down

Yes

Yes

CASE 4
VDD=5.5V
Temp=85Co

CASE 5
VDD=5.0V
Temp=27Co

-+50 (est)

-+50 (est)

-+25 (typ)

1. (max)
-+300

1.0(max)
-+300

O.l(typ)
-+300

1.0 (max
5.5

1.0 (max)
4.125

0.2 (typ)
1. 25

CASE 3
VDD=5.5V
Temp=40Co

Yes

Yes

Yes

103

ORDERING INFORMATION
Z86C08 CMOS Microcontroller
Z86C0808PSC 8MHz·
Z86C0812PSC 12MHz
Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = aoc to + 70°C
E = -40°C to + 85°C
M*= -55°C to +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B
J = JAN 38510 Class B

Example: PS is a plastic DIP, OoC to + 70°C.

PACKAGE DIMENSIONS

18-Pin Plastic Package
NOTE: Package dimensions are glven,lIl Inches. To convert to millimeters, multiply by 25.4

104

,., ZOTrr"'t

V.'-f

ADVANCED INFORMATION

IlJlJlj

Product Specification

Z86COO/C10/C20 CM OS
Z8@MCU

August 1989

FEATURES
• Complete microcomputer, 2K (86COO), 4K (86Cl0), or 8K
(86C20) bytes of ROM, 124 bytes of RAM (256 bytes - Z86C20),
and 22 I/O lines.

• Register Pointer so that short. fast instructions can
access any of nine working-register groups in 1.0
us.

• 144-byte register file, including 124 (238 - Z86C20) generalpurpose registers, four I/O port registers, and 14 status and control
registers.

• On-chip oscillator which accepts crystal. external
clock drive. Le. ceramic resonator.
• Standby modes ~- Halt and Stop.

• Average instruction
maximum of 2.S us.
• Vectored.
priority
counter/timers.

execution

time

of

1.5 us,
• Single +5V power supply -- all
compatible ..

interrupts

for

I/O

and

• Two programmable 'S-bit counter/timers. each with
a' 6-bit programmable prescaler.

pins TTL-

• 8 and 12 MHz
• CMOS process.

GENERAL DESCRIPTION
Z86Cl0/C20 microcomputer (Figures 1 and 2) introduces a·
new level of sophistication to single-chip architecture.
Compared to earlier single-chip microcomputers" the

+5V

~

+5V

P3.

XTAL2

P3,

XTALl

P2,

RESET

P2.

os

P2,

MCU

P3,

P2,

Z86Cl0

GND

P2,

MCU

PO.

P17

PO,

Pl.

PO,

Pl,

XTAL1

~)

XTAL2

ZS6COO

_P2'
........ P22

PORTZ { ___ P2,

Z86Cl0/C200ffers faster execution; more efficient use of
memory; more sophisticated interrupt, input/output and
bit-manipulation capabilities; and easier system expansion.

CLOCK

PORT 3

Z86C20

MCU

PORT 1

PO,

Pl •

PO.

Pl,

......... P2s

PO,

Pl,

....... GND

Pl.

Pl,

.......... P24

Figure 1. Pin Functions

\

Figure 2. Pin Assignments

105

PIN DESCRIPTIONS

os.

RESET. Reset (input, . active LoW). RESET initializes the

Data Strobe (output, active Low). Data Strobe is
activated once for each memory transfer.

MCU. When RESET is deactivated, program execution
begins from internal program location OOOCH.

POo·POs. P10·P17. P21·P2S. P310 P3s. P36. 110 Port lines

XTAL 1. XTAL2. Crystal 1, Crystal 2 (time-base input and
output). These pins connect a parallel-resonant
crystal to the on-chip clock oscillator and buffer.

(bidirectional,' TTL-compatible). These 22 110 lines are
grouped in four ports that can be configured under program
control for 110.

ARCHITECTURE
The MCU's architecture is characterized by a flexible 110
scheme, an efficient register and address space structure,
and a number of ancillary features that are helpful in many
applications. (Figure 3).

Two basic internal address spaces are available to support
this wide range of configurations: program memory and the
register file. The 144-byte random-access register file is
composed of 124 general-purpose registers, four 1/0 port
registers, and 14 control and status registers.

Microcomputer applications demand powerful 1/0
capabilities. The MCU fulfills this with 22 pins dedicated to
input and output. These lines are grouped in four ports and
are configurable under software control to provide timing,
status signals, and parallel 110.

To unburden the program from coping with real-time
. problems such as countingltiming, two counterltimers with
a large number of user-selectable modes are offered
on-chip.

OUTPUT

....;,;.;.;.~;,;.;.;.... (8192 for C20)

110

110

I/O

(BIT PROGRAMMABLE)

(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

STANDBY MODE
The Z86COO/C10/C20's standby modes are:

A reset input releases the standby mode.

• Stop

To complete an instruction prior to entering standby mode,
use the instructions:

• Halt
The Stop instruction stops the internal clock and clock
oscillation; the Halt instruction stops the internal clock but
not clock oscillation.

106

LD TMR, #00
NCP
STOP or HALT

ADDRESS SPACES
Instructions can access registers directly or indirectly with.
an a-bit address field. The MCU also allows short 4-bit
register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the register file is
divided into nine working-reg(ster groups, each occupying
16 contiguous locations (Figure 6). The Register Pointer
addresses the starting location of the active working-register
group.

Program Memory. The 16-bit program counter addresses
4K or ,8K bytes of program memory space as shown in
Figure 4.
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain three 16-bit
vectms that correspond to the three available interrupts.

Register File. The 144-byte register file includes four 1/0
port registers (Ro-R3), 124 general-purpose registers
(R4-R127) and 15 control and status registers (R241-R2SS)'
These registers are assigned the address locations shown in
. Figure 5.

Stacks. An a-bit Stack Pointer (R2SS) is used for the internal
stack that resides within the 124 general-purpose registers
(R4-R127)·

4098
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED
AFTER RESET

INTERRUPT
VECTOR
(\.OWER ~TE)
INTERRUPT
VECTOR
(UPPER BYTE)

ON·CHIP
ROM

~ t-----------11

IRQ5

10

IRQ5

9

IRQ4

8

IRD4

7

RESERVED

8

RESERVED

5)010..

IRQ2

4"'"
3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

IRQ2

Figure 4. Program Memory Map
LOCATION

IDENTIFIERS

255
254

ST",CK POINTER (BITS 7-0)
RESERVED

253

REGISTER POINTER
PROGRAM CONTROL FLAGS

RP
FLAGS

252
251

SPL

INTERRUPT MASK REGISTER

IMR

250
249

INTERRUPT REQUEST REGISTER

IRQ

INTERRUPT PRIORITY REGISTER

IPR

248

PORTS 0-1 MODE

P01M

247

PORT 3 MODE

246
245

242

PORT 2 MODE
TO PRESCALER
TIMER/COUNTER b
Tl PRESCALER
TIMER/COUNTER 1

P3M
P2M
PRE6

241

TIMER "!ODE

244
243

TO
PREl

T1
TMR

--1

L-"':""':"''':'':''''....L.._;;'';;'';:''':'''...I 253

THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING-REGISTER GROUP.
127

---+-+-{~----I

NOT
IMPLEMENTED
127

SPECIFIED WORKING·
REGISTER GROUP

-+-+-

GENERAL·PURPOSE
A,EOISTERS

PORT 3'

P3

PORT 2

P2

PORT 1

Pl

PORTO

PO

Figure 5. Register File

THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER.

15

--..

----------110 PORTS

Figure 6. Register Pointer

107

COUNTER/TIMERS
The MCU contains two 8-bit programmable counter/timers
(To and T1), each driven by its own 6-bit programmable
prescaler, The T1 prescaler can be driven by internal or
external clock sources; however, the To prescaler is driven
by the internal clock only,
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64, Each prescaler
drives its counter, which decrements thevalue (1 to 256) that
has been loaded into the counter, When the counter reaches
the end of count, a timer interrupt request-IRQ4 (To) or
IRQ5 (T1)-is generated,
The counters can be started, stopped, restarted to continue,
or restarted from the initial value, The counters can also be
programmed to stop upon reachin,Q zero (single-pass

mode) or to automatically reload the initial value and
continue counting (modulo-n continoous mode)" The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode,
The clock source for T 1 is user-definable and can be the
internal microprocessor clock
divided by
four, or an external signal input via Port 3, The Timer Mode
register configures the external timer input as an external
, a trigger input that can be
clOck
retriggerable or non-retriggerable, or as a gate input for the
internal clock, The counter/timers can be programmably
cascaded by connecting the To output to the input of T1,
Port 3 line P36 also serves as a timer output (Tour) through
which To, T1 or the internal clock can be output.

I/O PORTS
The MCU has 22 lines dedicated to input and output
grouped in four ports, Under software control, the ports can
be programmed to provide address outputs, timing, status
signals, and parallel I/O, All ports have active pull-ups and
pull-downs compatible w~h TTL loads,
Port 0 can be programmed as an I/O port,
Port 1 can be programmed as a byte I/O port.

Port 2 can be programmed independently as input or
output and is always available for I/O operations, In addition,
Port 2 can be configured to provide open-drain outputs,
Port 3 can be configured as I/O or control lines, P3 1 is a
general purpose input or can be used for an external
interrupt request signal (IRQ2)' P35 and P36 are general
purpose outputs, P36 is also used for timer input (TIN) and
output (Tour) signals,

INTERRUPTS
The MCU allows three different interrupts from three
sources, the Port 3 line P31 and the two counter/timers,
These interrupts are both maskable and prioritized, The
Interrupt Mask register globally or individually enables or
disables the three interrupt requests, When more than one
interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register,
All interrupts are vectored, When an interrupt request is
granted, an interrupt machine cycle is entered, This disables

all subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory vector
locations reserved for that interrupt. This memory location
and the next byte contain the 16-bit address of the interrupt
service routine for that particular interrupt request.
Polled interrupt systems are also supported, To accommodate a polled structure, any or all of the interrupt inputs
can be masked and the InterruplRequest register polled to
determine which ,of the interrupt requests needs service,

CLOCK
The on-chip oscillator has a high-gain parallel-resonant
amplifier for connection to a crystal or to any suitable
external clock source (XTAL 1 ~ Input, XTAL2 = Output),
Crystal source is connected across XTAL 1 and XTAL2 using
the recommended capacitors (C1 ~ 15 pI) from each pin to
ground, The specifications are as follows:

108

• AT cut, parallel resonant

• Fundamental type, 16 MHz maximum_
• Series resistance, Rs ~ 100 n

INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
IRR

Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Irr
X
DA

RA

1M
R
r

IR
Ir
RR

Symbols. The following symbols are used in describing the
instruction set.
dst

src
cc
@

SP

PC
FLAGS

RP
IMR

Destination location or contents
Source location or contents
Condition code (see list)
Indirect apdress prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol "+-': For
example,
dst +- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the following six
flags:
C
Z
S
V
D
H

.
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

Affected flags are indicated by:

o
1

*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

CONDITION CODES

Value

Mnemonic

1000
0111
1111

Meaning

Flags Set

Always true
C
NC

0110

Z

1110
1101

NZ
PL

0101

MI
OV

Carry
No carry

C = 1
C=O

Zero

Z = 1
Z=O

Not zero
Plus
Minus

8=0
8 = 1

0100
1100

NOV

0110
1110
1001
0001
1010

LT

Less than

(8XORV) = 1

GT

Greater than

[Z OR (8 XORV)j = 0

0010

LE

1111
0111

UGE
ULT

Less than or equal
Unsigned greater than or equal
Unsigned less than

C=O
C = 1

1011

UGT

Unsigned greaterthan

0011

ULE

Unsigned less than or equal

0000

V = 1
V=O

EO

Overflow
No overflow
Equal

Z = 1

NE
GE

Not equal
Greater than or equal

Z=O
(8 XOR V) = 0

[ZOR(8XORV)] = 1

(C = 0 AND Z = 0) = 1
(CORZ) = 1

Never true

109

INSTRUCTION FORMATS
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF

OPC

dst

INCt

OPC

One-Byte Instructions

CLR, CPL, DA, DEC,

'---===----'

I

OR " 1 1 0 dsllsrc

I ~~;~' ~~~Rt~~:itOP'
RRC, SRA, SWAP

I

OPC

f----'d~S.:::t---lOR

1---7-'---i

OR

1 1 1 0

8fC
dst

' - - _ = _ - - - ' OR' 1 1 1 0

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

JP, CALL (Indirect)

11 1 1 01

dst

I--:-:=='=---i
OPC
VALUE

OR 11 1 1 0

I

dst

VALUE

SRP

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

LD
ADC, ADD, AND, ,
CP, OR, SBC, SUB,
TCM, TM, XOR
MODE
dstfsrc

OPC
src/dst

dstfsrc

ope

src/dst

MODE
dst/src

LO, LDC, LOCI

OPC

LD

ADDRESS

OR

11

1 1

01

LD

cc

8fC

I

dst
OPC
VALUE

OPC

JP

DAu
DAl
LD

I

dsliCCR~ OPC

OPC
DAu
DAl

DJNZ, JR

Two-Byte Instructions

CALL

Three-Byte Instructions

Figure 7. Instruction Formats

INSTRUCTION SUMMARY
AddrMode
Instruction
and Operation

dst

src

Opcode
Byte
(Hex)

Flags Affected

C Z S V 0 H

Instruction
and Operation

10

* * * * 0 *

CP dst,src

AOCdst,src
dst - dst + src + C

(Note 1)

AOOdst,src
dst - dst + src

(Note 1)

00

* * * *' 0 *

ANl;)dst,src
ds! - dst AND src

(Note 1)

50

CALLdst
DA
SP-SP - 2
IRR
@SP - PC; PC - dst
CCF

dst

src

Opcode
Byte
(Hex)

Flags Affected

C Z S V 0 H

(Note 1)

AD

* * * *

OAdst
dst-DAdst

R
IR

40
41

* * * X

-**0--

OeCdst
dst-dst - 1

R
IR

00
01

-***--

D6
D4

-----""--

OeCWdst
dst-dst - 1

RR
IR

80
81 '

-***--

EF

*-----

IMR(7)-0

8F

------

OJNZ r,dst
r'- r - 1

dst - src

01

C-NOTC
CLRdst
dst-O

R
IR

BO
B1

------

COMdst
dst- NOTdst

R
IR

60
61

-**0--

110

AddrMode

ifr*O
PC -PC + dst
Range: + 127, -128

RA
r=

-----rA
0- F

INSTRUCTION SUMMARY (Continued)
Instruction
and Operation

Addr Mode Opcode
Byte
dst src
(Hex)

Fla~s

Affected

CZSVOH

Addr Mode Opcode
Byte
dst src
(Hex)

Instruction
and Operation

EI
IMR(7)-1

9F

RCF
C-O

CF

HALT

7F

RET
PC +- @SP; SP +- SP + 2

AF

r==l R
L..:..J~IR

90
91

INCdst
dst -dst + 1

rE

r

R
INCWdst
dst - dst + 1

=

IR

21

RR

AO
A1

IR

OA

cD
c=O-F

IRR

30

JRcc,dst
RA
if cc is true,
PC-PC + dst
Range: + 127, -128
LOdst,src
dst-src

r
R

LOCdst,src
dst-src

cB
c =0 - F

*

*

--

RL dst

r;:'l

RLC dst

L::[i)::6J R

10

IR

11

LEi LciJ IRR

E1

c

RR dst
*

*

*

*

*

c

*

,

.'

r

CO
C1

SBCdst,src
dst +- dst +- src - C

30

.~IR

(Note 1)

SCF
C +-1

LEl'':::;:;:=;J R

I

~IR

1m
R

X
r

Ir

r
R
IR

Ir

IR

1M
1M

IR

R

r

Irr

Irr

rC
r8
r9
r=0 - F
C7

07
E3
F3

E4
E5
E6
E7
F5

C2
02

LOCI dst,src
dst - src
r - r + 1; rr - rr + 1

Ir
Irr

Irr
Ir

C3

LOE dst,src
dst - src

r
Irr

Irr

82

'LOEI dst,src
dst - SfC
r - r + 1; rr - rr + 1

Ir
Irf

Irr
Ir

03

92
83

1m

SRPsrc
RP -src

0-----

****--

OF

1-----

DO
01

***0--

31

6F

STOP
(Note 1)

20

R

FO
F1

TCMdst,src
(NOT dst) AND src

(Note 1)

60

TM dst,src
dstANOsrc

(Note 1)

70

XORdst,src
dst +- dst XOR src

(Note 1)

Bo

SUBdst,src
dst - dst - src
SWAPdst

I,

S
.,

.IIR

X

**

X

NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble IS found in
the instruction set table above. The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to the lett of the applicable addreSSing mode pal[
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.

93
AddrMode

FF

NOP

CZSVOH

EO

0

RRC dst I::'-=:==-l R

SRA dst

r
X
r

R
R
R

*

20

IRET
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR (7) - 1
JPcc,dst
ifcc is true
PC-dst

-

0 - F

Flags Affected

ORdst,src
dst - dst OR src

(Note 1)

40

POPdst
dst-@SP;
SP-SP + 1

R
IR

50
51

dst

src

R

R

R

IR

R

1M

IR

1M

Lower
Opcode Nibble

Ir

PUSHsro
SP -SP - 1; @SP-src

R

70

IR

71

111

REGISTERS
R244 TO
COUNTER/TIMER 0 REGISTER
(F4H; Read/Write)

To INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)

R241 TMR
TIMER MODE REGISTER
(F1 H; ReadlWrite)

O",
M0
OD
NOT T
USED'"
0
, ESj

~~ g~~ ~ ~~
INTERflIAL CLOCK OUT

T

0::;

~~O'NOFUNCTION
1 '" LOAD To

0 :: DISABLE To COUNT
1 '" ENABLE To COUNT

11

MODES

EXTERNAL CLOCK IN~UT

0 = NO FUNCTION

= 00

GATE INPUT", 01
10

(NON.R~~~~:~~~~:~~) '"

R245PREO
PRESCALER 0 REGISTER
(F5H; Write Only)

TIl

COUNT MODE
0 "" To SINGLE PASS

-

1 ". To MODULO·N

...

RESERVED

1 '" LOAD T,
_

0 '" DISABLE T1 COUNT
1 :: ENABLE T1 COUNT

.-

PRESCAL.ER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

TRIGGER INPUT = 11
(RETRIGGERABlE)

R242 T1
COUNTER TIMER 1 REGISTER
(F2H; Read/Write)

R246P2M
PORT 2 MODE REGISTER
(F6H; Write Only)

I~I~I~I~I~I~I~I~I

L~

T, INITIAL VALUE (WHEN WRITTEN)

P20-P2 7 110 DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

---(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)

R243 PRE1
PRESCALER 1 REGISTER
(F3H; Write Only)

TIL

R247P3M
PORT 3 MODE REGISTER
(F7H; Write Only)

I~I~I~I~I~I~I~I~I

COUNT MODE

_

0' = 1, SINGLE·PASS

La

PORT 2 PULL·UPS OPEN ,DRAIN

1 PORT 2 PULL·UPS ACTIVe

1 = TI MODUlO·N

CLOCK SOURCE
1 = TI INTERNAL

.

0 '" 11 EXTERNAL TIMING INPUT

(Til,) MODI:
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

'--~----- RESERVED

Figure 11. Control Registers

112

(must be 0)

REGISTERS (Continued)
R252 FLAGS
FLAG REGISTER
(FCH: Read/Write)

R248 P01M
PORT 0 AND 1 MODE REGISTER
(F8H: Write Only)

'
UllliHfU§

MODE~
~-r
~
L Po.,-Po, MODE

po,_po, = 00
OUTPUT

LUSERFLAGF1

00 '" OUTPUT

INPUT:: 01

LUSER FLAG F2

01 '" INPUT

:':~P~:~::E (mu51

RESERVED

-

be = I)

HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG

00 '" BYTe OUTPUT
01 '" BYTE INPUT

,

ZERO FLAG

~~ :} RESERVeD

.

CARRY FLAG

R253RP
REGISTER POINTER
(FDH: Read/Write)

R2491PR
INTERRUPT PRIORITY REGISTER
(F9H: Write Only)

lo,l~I~I~lo,lo,lo,l~1

••

~.:J

I I 111"·"""·~"··~
RESERVED = 000
' , C > A > B == 001
A > B > C '" 010

tRQ3, lAOS PRIORITY (GROUP A)
o = lAOS> IRQ3
, = IRC3 > IRQS

A> C> B = 011

B> C > A
C > B > A
B > A > C
RESERVED

IROO, IRQ2 PRIORITY (GROUP 8)
o = IRQ2 > IRaO
1 = IRaO > IRQ2

= 100
= 101
= 110
= 111

IRQ1, IRQ4 PRIORITY (GROUP C)
o = IRQl > IRQ4
1

= IRQ4 > IRQ1

R250 IRQ
INTERRUPT REQUEST REGISTER
(FAH: Read/Write)

lo,lo,l~lo,lo,lo,lo,l~1

RESERVED

::::r-II

I

IRQ2 = P31 Inpul
IRQ4 = To
IRQS = T,

R2511MR
INTERRUPT MASK REGISTER
(FBH: Read/Write)

R255SPL
STACK POINTER
(FFH: Read/Write)

lo,l~I~I~lo,lo,lo,l~1

I.

1-

c=--

1 ENABLES IRaO_IROS

(Do:: IRCO)

'-------RESERVED

' - -_ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

Figure 11. Control Registers (Continued)

113

OPCODEMAP
Lower Nibble (Hex)

o

o

2

,

4

i

e

I
~

lI:
~

7

8

A

B

C

0

E

F

4

6

8

7

9

A

B
12/10.0

65

65

65

65

6.5

12/105

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

R,

IR,

" f2

Ir2

R2· R,

IR2·R,

R,IM

IR,.IM

f,.R2

'2 Rt

65

65

6.5

6.5

10.5'

10.5

10.5

10.5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR,.IM

f,

105

105

105

10.5

6.5

R,

IR,

r1 '2

f1· lr2

R2·R,

IR2·R,

R,.IM

6.5

6.5

65

65

10.5'

10.5

10.5

10.5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR,.IM

R,

iR,

".f2

r1: lr2

R2· R,

IR2·R,

R,IM

80

61

6.5

6.5

10.5

10.5

10.5

10.5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

1M

",r2

r,. lr2

R2· R,

IR2·R,

R,.IM

IR,.IM

85

8.5

6.?

6.5

10.5

10.5

10.5

10.5

DA

DA

OR

OR

OR

OR

OR

.OR

R2·R,

IR,.IM

IR2·R,

R,. IM

10,5 .

10,5

iO,5

10,5

AND

AND

AND

AND

AND
IR"IM

R,

IR,

'1· f 2

r,. lr2

10.5

10.5

6.5

6,5

POP

POP

AND

R,

IR,

r,.f2

f,.lr2

R2,R,

IR2,R,

R"IM

6.5

65

6.5

6,5

10,5

10.5

10.5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

' IR2,R,

R,

IR,

',.r2

r,.lr2

R2· R,

R"IM

IR"IM

12/14,1

6.5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

'1· r2

r1· lr2

R2,R,

IR2·R,

R,. IM

IR,.IM

R2

IR2

10,5

10.5

DECW

DECW

RR,

IR,

r, RA

C

o

65

E

12/10 0

65

JR

LD

JP

INC

cc.'RA

fllM

ccDA

rl

F

r----

r--

f---'----:
r---

r-I---6,0
STOP

10112,1

6.5
9

3

2

I---7.0
HALT

f------e1
01

I---6.1

6.5

RL

RL

R,

IR,

-

EI

1

10.5

10.5

6.5

6.5

10.5

f----;4:o

INCW

INCW

CP

CP

CP

CP

CP

CP

RET

RR,

IR,

'1· lr2

R2,R,

IR2·R,

R,.IM

IR,.IM

'1·'2

10.5

10.5

10.5

10.5

10.5

10.5

6.5

6.5

6.5

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R,

IR,

',.r2

f,.lr2

R2· R,

IR2·R,

R,.IM

IR,.IM

6.5

6,5

RRC

RRC

LDC

LOCI

LD

R,

IR,

r,. lrr2

Ir1.lrr2

'l.x R2

12.0

18.0

6.5

18.0

20.0

20,0

SRA

LDC

LOCI

CALL"

CALL

LD

R,

IR,

r2· lrr,

Ir2·lrr,

IRR,

DA

r2· x.R,

6.5

6.5

RR

RR

R,

IR,

r,. IR2

LD

10.5

10,5

10.5

'

LD

LD

LD

IR2·R,

R,IM

IR"IM

6.5

~
SCF

-

10.5

LD
R2,R,

I----

RCF

10,5

6.5

6.5

IRET

. 10.5

SRA

12.0

~

10.5

6.5

CLR

6.5

CCF

8.5

8,5

6,5

10,5

6()

SWAP

SWAP

LD'

LD

NOP

R,

IR,

Ir,.r2

R2· IR ,

. . . ----..v. . .------', . . .----...;..'V...-----", . . . .------v. .

------,,~~

2

2

3

3

Bytes per Instruction

LOWER
OPCODE

Nlr

EXECUTION
CYCLES

PIPELINE
CYCLES

MNEMONIC

Legend:
R ~ B·bit address
r = 4·b~ address
R,orr1 = Dstaddress
R2 or r2 = Src address

Sequence:
Opcode. Firsl Operand. Second Operand
FIRST

OPERAND

-2-byte mstructlOn. fetch cycle appears as a 3·byte mstructlon

114

SECOND
OPERAND

NOTE: The blank areas are not defined.

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
toGND ...
..... - 0.3V to + 7.0V
Orerating Ambient
.... See Ordering Information
Temperature
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maxirn1Jm Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS

+5V
2.1K

The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pi n.
Standard conditions are as follows:

• +4.5 ~ Vee ~ +5.5
• GND

= OV
Figure 12. Test Load 1

DC CHARACTERISTICS

Symbol

Parameter

VCH

Clock Input High Voltage

VCl

Clock Input Low Voltage

VIH

Input High Voltage

Vil

Input Low Voltage

VRH

Reset Input High Voltage

VRl

Reset Input Low Voltage

Min

Max

Unit

3.8

Typ

VCC

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

2.0

VCC

V

-0.3

0.8

V

3.8

VCC

V

-0.3

0.8

V

Condition

=

2.4

V

IOH

Vee -100 mV

V

IOH = -100JiA

VOH

Output High Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

III

Input Leakage

-10

IOl

Output Leakage

-10

IIR

Reset Input Current

ICC

Supply Current

ICC1.

Standby Current

ICC2

Standby Current

0.4

IOl

=

-250J.tA
+2.0mA

10

OV'; VIN'; + 5.25V

10

OV'; VIN'; + 5.25V

-50

VCC

=

+ 5.25V, VRl

= OV

50

All outputs and I/O pins floating

10

Stop Mode

5

Halt Mode

NOTE:
Icc2 low power requires loading TMR (%F1)
with any value prior to stop execution.
.
Use sequence:
LD TMR, #%00.
NOP
STOP

115

Figure 14. Additional Timing

AC CHARACTERISTICS
Additional Timing Table

Z86C10

Number

Symbol

Parameter

TpC

Input Clock Period

2

TrC,TlC

Clock Input Rise and Fall Times

3

TwC

Input Clock Width

4

TwTinL

5

TwlL

Max

83

100,000

Notes·

15

Timer Input Low Width

70
70

2

Interrur;>t Request Input Low Time

70

2,3

NarES:
1. Clock timing references use 3.8V for a logic "1" and 0.8V lor a logic "0':
2. Timing references use 2.0V lor a logic "1" and 0.8Vlor a logic "0':
3. Interrupt request via Port 3.
• ·Units in nanoseconds (ns).

116

Min

~ Zilffi

Product Specification

Z86Cll CMOS
Z8® 4K ROM MCU

June 1987

FEATURES
• Complete microcomputer, 4K bytes of ROM, 256 bytes of
RAM, 32 I/O lines, and up to 60K bytes addressable
external space each for program and data memory.

• 256 -byte register file, including 236 general-purpose
registers, four I/O port registers, and 16 status and
.control registers.

• Register Pointer so that short, fast instructions can
,access any of 16 working-register groups in 1.5 lAs.
• On-chip oscillator which accepts crystal or external clock
drive.
• Standby modes-Halt and Stop
• Single  A > 8 :: 001

IRQI. IHOI PRIORITY (GROUP AJ

_:J

0=IROI>,R03

1 = 1RQ3> IAQ6
IROO. IRQ2 PRIORITY (GROUP 8)

~

A>B>C=010
~~g~:~ra:

.

C :> B

~

>A

REGISTER
POINTER

= 101

:~E~;E~: ~~~

IRQt, 1RQ4 PRIORITY (GROUP C)

.

'0 = tROt> tRot

1 = IR04 > IAQ1

R250lRQ
INTERRUPT REQUEST REGISTER
(FAH; ReadIWr~e)
I~I~I
. . . . . .VED

~

R254SPH
STACK POINTER
(FEH; Re~dIWrite)

.. I~I .. I~I~I .. I
C:=,oao
- "".PUT
tRQi • PIa INPUT

(Do. 'ROO)

.HOI • P31INPUT
IR03 • PIa INPUT, SERIAL INPUT

IRot .. To. SERIAL OUTPU'f
lAOS. T1

R2511MR
INTERRUPT MASK REGISTER
(FBH; ReadIWrije)
I~!~!

.1 1

.. !~! .. !~!~! .. I

c:=

1 ENABLES IRQO-IRQ6

,... '0001

'-------AESEAYEO .

L..-_ _ _ _ _ _ 1 ENAI..ESIHTERRUPTS

Figure 11. Control Registers (Continued)

128

R255SPL
STACK POINTER
(FFH; Read/Write)

.. .. 1

IDa~I~I~I~I I~I

IL_ _ _ :~~~s~~~~~R

LOWER

OPCODEMAP
I..ow8r Nibble (Hex)

o

o

i

e

7

1·
B

C

o

6

7

8

9

A

B

10.5

10.5

10.5

6.5

6.5

12/10.5

12/10.0

6.5

DEC

DEC

ADO

ADD

ADO

ADO

ADD

ADD

LO

LO

OJNZ

JR

R,

IR,

'1·'2

'1· lr2

R2. R,

IR2.R,

R,.IM

IR,.IM

f1,R2

r2. R,

r,.RA

cc.RA

6.5

6.5

6.5

6.5

10.5

,0.5

10.5

10.5

RLC

RLC

AOC

ADC

AOC

AOC

AOC

AOC
IR,.IM

R,

IR,

r1,'2

f1:lr2

R2.R,

IR2.R,

R,.IM

6.5

6.5

6.5

6.5

10.5

10.5

10.5

10.5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR,.IM

R,

IR,

'1·'2

IR2.R,

R,.IM

6.1

6.5

". lr2
6.5

R2. R,

8.0

10.5

10.5

10.5

10.5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

1M

r1. f 2

r,. lr2

R2. R,

IR2.R,

R,.IM

IR,.IM

8.5

8.5

6.5

6.5

10.5

10.5

10.5

DA

DA

OR

OR

OR

OR

OR

R,

IR,

'1,f2

'1. lr2

R2. R,

IR2.R,

R,.IM

10.5
OR
Ifl,.IM

10.5

10.5

6.5

10.5

10.5

10.5

10.5

AND

AND

AND

AND
IR,.IM

R,

IR,

r1,f2

6.5
. AND
r,. lr2

R2. R,

IR2.R,

R,.IM

6.5

6.5

6.5

6.5

10.5

10.5

10.5

10.5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R,

IR,

r1·'2

". lr2

R2. R,

iR2.R,

R,.IM

IR,.IM

10112.1

12114.1

10.5

10.5

TM

10.5
1M
R2. R,

10.5

PUSH

6.5
1M

6.5

PUSH

TM

TM

TM

IR2.R,

R,.IM

IRI·IM

pop

pop

AND

o

E

12/10.0

65

LD

JP

INC

r,.IM

cc.DA

r.1

C'

6.5

F

-

f--

r------,---

c-a.o
STOP

I--7.0

HALT

-

R2

IR2

'1,'2

'1.1r2

10.5

10.5

12.0

18.0

r---e:;-

DECW

DECW

LDE

LDEI

01

RR,

IR,

'1. lrf2

Ir1·lrr2

6.5

6.5

12.0

18.0

RL

RL

LDE

LDEI

R,

IR,

f2, lrr1

Ir2.1rr,

r---e.;EI

10.5

6.5

6.5

INew

CP

CP

CP

RR,

IR,

r1,f2

'1.1r2

R2. R,

6.5

6.5

6.5

6.5

CLA

CLA

XOA

XOR

XOR

XOR

XOR

XOR

IRET

Rl

IR,

r1.r2

'1. lr2

R2.R,

IR2.R,

R,.IM

IR,.IM

r--s:s-

10.5

10.5
CP
IR2.R,

10.5
CP
R,.IM.

14.0

10.5

12.0

10.5

I---

INCW

10.5

10.5

18.0

10.5
CP
IR,.IM

6.5

6.5

RRC

LOC

LOCI

LD

R,

IR,

'1.1rr2

Ir1.lrf2

r1,x.~2

18.0

f--;s.o

10.5

6.5

6.5

12.0

SAA

SRA

LOC

LOCI

R,

IR,

'2· lrr 1

Ir2.lrr1

6.5

6.5

RR

RR

LD

LD

LD

LD

LD

R,

IR,

r,. IR2

R2.R,

IR2.R,

R,.IM

IR,.IM

20.0
CALL"
IRR,

6.5

10.5

20.0
CALL
DA
10.5

10.5

RCF

f--6.5
SCF

10.5

LD
r2.x.R,

r--s:s-

10.5

CCF

I---

10.5

8.5

8.5

SWAP

SWAP

LD

LD

R,

IR,

Ir1,r2

R2· IR ,

...

RET

10.5..

ARC

E

F

. 10.5

5

6.5

9

A

4

6.5

4

6

3

6.5

3

5

2

6.5

...

6.0

NOP

---_'V~----,; ---_'V~----.I
2

. . -----.. .

...

'V~----- .I~'---v-2

3

3

Bytea per I....ructlon

LOWER
OPCODE

NlBf
EXECUTION
ClCLES

PIPELINE
ClCLES

Legend:
R = 8-bit address
r

= 4-bit address

R, orr, - Dstaddres.

MNEMONIC

R20rr2 - Src address

Sequence:
Opcode. FirstOperand. Second Operand

SECOND
OPERAND

*2·byte Instruction, fetch cycle appears as a 3-byte instruction

NOTE: The blenk

areas are not Qefined.

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
toGND ......................... -O.3Vto +7.0V
Operating Ambient
'
Temperature . '..............See Ordering Information
Storage Temperature .............. -65°C to + 150°C

Stresses-greater than ihose iisted under Absolute Maximum Ratings may
cause permanent damage to' the device. This is a stress rating only;
operation of the device at any cohd~ion above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliabil~y.

STANDARD TEST CONDITIONS

+5V
2.1K

The DC characteristics listed below apply for the following
standard test coTlditions,' unless otherwise noted. All
voltages are referenced to GND. Positive'current flows into
the referenced pin.
.
Standard conditions are as follows:

• +4.5 ~
• GND

V.CC ~ + 5.5V

= OV

• 0 C $ T A $ +7~, C for S (Standard temperature)

• -40 C $

TA $+100

Figure 12. Test Load 1

C for E (Extended temperature)

DC CHARACTERISTICS
Symbol

Parameter

VCH

Clock Input High Voltage

Vel

Clock Input Low Voltage

V,H

Input High Voltage

V,l

Input Low Voltage

VAH

Reset Input High Voltage

VAL

Aeset ' I1Put Low Voltage

VOH

Output High Voltage

VOH

Outpl,lt High Voltage

Val

.Output Low Voltage

I,l

Input Leakage

-10

IOl

Output Leakage

-10

I'A
ICC

Reset Input Current
Supply Current

I~C1

Standby Current

ICC2

Standby Curre~t

Min

Max

Unit

Driven by External Clock Generator

-0.3

VCC
0.8

V
V

Driven by External Clock Generator

2.0

VCC

V

-0.3

0.8

V

3.8

VCC

V

-0.3

0.8

lYP

3.8

V

2.4

Vee -100mV
0.4
10

Condition

/

=

V

IOH

V

IOH .. -100j.IA .

=

-250,..A

V

IOl

JAA

OV ~ V,N ~ + 5.25V

+2.0mA

10

JAA

OV ~ V,N ~ + 5.25V

-50

,..A

VCC = + 5.25V, VAL

30

mA

All outputs and I/O pins floating, 12 MHz

5
10

mA

Halt Mode

,..A

Stop Mode

lee2 requires loading TMR (%F1) ,with any value prior to STOP execution.

'"

Use the sequence:
LD TMR,#OO
NOP
STOP

1~

= OV

PORT 1

",,,,OUT

iii
(WRITE)

Figure 13. External 110 or Memory Read/Write

AC CHARACTERISTICS
EXternal 110 or Memory Read and Write Timing

"Number

Symbol

Min

Parameter

12MHz
Max

1

TdA(AS)

Address Valid to AS t Delay

35

2

TdAS(A)

AS t to Address Float Delay

45

3

TdAS(DR)

AS t to Head Data Required Valid

4

TwAS

ASLDwWidth

5

TdAz(DS)

Address Float to OS l

6

TwDSR

7

TwDSW

8

TdDSR(DR)

9

ThDR(DS)

10

TdDS(A)

DS (Read) LDw Width
OS (Write) LDw Width
OS l to Read Data Required valid
Read Data to iSS t Hold Time
iSS t to Address Active Delay

11
12

TdDS(AS)

C5S t to AS l

TdRIW(AS)

RiW valid to AS +Delay

13

TdDS(RIW)

14

TdDW(DSW)

15

TdDS(DW)

OS t to RIW Not.valid
Write Data valid to OS (Write) l Delay
OS t to Write Data Not Valid Delay

16
17

TdA(DR)

Address valid to Read Data Required Valid

TdAS(DS)

AS t to OS ~ Delay

NOTES:
,. When using extended memory timing add 2 TpC.
2, Timing numbers given are for minimum TpC.
3, See clock cycle lime dependent characteristics table,

20
30

2.3
2.3

180

220

1.2.3

55
0,

35
0

2.3

185

135
80

1.2.3

110

0
20

0
45

35
35

2.3
2.3
2.3
2.3
2.3

200

255

40

1.2.3
2.3

20
20
20
25
20

35

55

1.2.3

75

130

55
30

Delay

16 MHz
Min
Max Notes*t-

1.2.3
2.3

• All units in nanoseconds (ns):
tlilst Load'
• All timing references use 2.0V for a logic "'" and 0.8V for a logic, "0".

131

'Figure 14. Additional Timing

AC CHARACTE.RISTICS
Additional Timing Table

Min

Max

16 MHz
Min,
Max

83

1000

62.5

12MHz
Number

Symbol

Parameter

1000
10

1

TpC

Input CloCk Period

2

TrC,TfC

Clock Input Rise and Fall Times

3

TwC

Input Clock Width

4

TwTinL

Timer Input Low Width

70
70

21
50

2

5

TwTinH

Timer Input High Width

3TpC

3TpC

2

8TpC

15

1

8TpC

6

TpTIn

Timer Input Period

7

ltTin,Tmn

Timer Input Rise and Fall TImes

8A

lWlL

, Interrupt Request Input Low Time

70

50

2,4

88

TwlL

Interrupt Request Input Low Time

3TpC

2,5

9

TwlH

Interrupt Request Input High Time 3TpC

3TpC
3TpC

2

100

100

NOTES:
" Clock timing references use 3,BV for a logic "," and O.BV for a logic "0",
2. Timing references use 2.0V for a logic "," and O.BV for a logic "0",
3. Interrupt request via Fort 3,
.
4. Interrupt request via Fort 3 (P3,·P33l.
5. Interrupt request via Port 3 (P3o).
• Units in nanoseconds (ns).

DA~~~: ______~_'
___"'~~
...: ~ ~---RDY
(OUTPUT)

Figure 15a. Input Handshake

. DATA OUT

DATA OUT VALID
~
-----~--------------------------------

IOU: ~~1~3

of'"q()" q(;:,10 q'!;)"- 4'<::> q...... IRQ3
1 = IR03 > IAQ5

IRao. IRQ2 PRIORITY (GROUP B)
o '" IA02 > IROO
1 = IRoo > IRQ2

'II"---~
RESERVED = 000
C > A > B '" 001

A>B>C=010
A > C > B = 011
8>C>A=1oo
C > B > A = 101
8 > A > C = 110
RESERVED = 111

REGISTER
POINTER

IR01, IRQ4 PRIORITY (GROUP C)

o = IRQ1

> IRQ4

.

1 = IRQ4 > IRQ1

R250lRQ
INTERRUPT REQUEST REGISTER

R254SPH
STACK POINTER

(FAH; Read/Write)

(FEH; Read/Write)

'~I~I~I~I~I~I~I~'
RESERVED:::r-

c::

'ROO - ..,'NP;'! \00 • 'RQO)
.. P3a INPUf

IRQ1
IRQ2
IRa3
IRQ4
IRas

- PI, INPUT
= P30 INPUT. SERIAL INPUl
- To. SERIAL OUTPUT
=T1

R2511MR
INTERRUPT MASK REGISTER

R255SPL
STACK POINTER

(FBH; Read/Write)

(FFH; Read/Write)

I~I~I~I~I~I~I~I~I

'~I~I~I~I~I~I~I~I

II

c=

1 ENABLES IRaO-IRas

(Do = IRaG)

1'--___ :~~~S~~:~~R

LOWER

L--------RESERVED

1-_ _ _ _ _ _ _ 1 ENA~LES INTERRUPTS

Figure 11. Control Registers (Continued)

147

OPCODEMAP
Lower Nibble (Hex)

2

o

3

4

5

6

9

A

B

C

D

E

F

3

4
10.5

5

6

105

10.5

7
10.5

8

A

B
12110.0

C

D

6.5

65

65

6.5

6.5

6.5

12110.5

12110.0

6.5

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

LD

JP

INC

R,

IR,

',.r2

r,. lr2

R2· A,

IR2·R,

R,IM

IR,.IM

f1·R2

'2· R,

" RA

cc.RA

".1M

ccDA

,1

6.5

65

6.5

6.5

10.5

10,5

10,5

10,5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC .
IR"IM

R,

IR,

"·'2

". lr2

R2,R,

IR2.R,

R"IM

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IA,.IM

R,

IR,

f,.f2

f,.lf?

R2,R,

IA2,R,

A,.IM

8.0

6.1

6,5

6,5

10,5

10,5

10,5

10,5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

,1M

"·(2

(,.lr2

R2,R,

IR2,R,

R"IM

IR"IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA
R,

DA

OR

OR

OR

OR

OR

OR

IR,

'1,(2

". lr2

R2,R,

IR2,R,

R"IM

IR"IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND
IR"IM

R,

IR,

'1,(2

'1, lr2

R2,A,

IR2,A,

R,.IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

,TCM

TCM

TCM

A,

lA,

f1,(2

(,.lr2

A2,R,

IR2,A,

A,.IM

IR"IM

10112,1

12114;1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM
R2,A,

TM

TM

TM

IR2,A,

A,.IM

IA,.IM

A2

IA2

'1,(2 '

10,5

10,5

12,0

DECW

DECW

LDE

LDEI

AA,

lA,

'" lrr2

Ir"lrr2

6,5

6,5

12,0

'1. lr2

f------

-

LDE

LDEI

IR,

(2·lrr,

1'2,lrr,

-

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

INCW

CP

CP

CP

CP

CP

CP

RR,

IR,

'1· r2

". lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

6,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R,

IR,

(,.r2

(,. lr2

6,5

A2,R,

10,5

IR2,R,

10,5

A"IM

10,5

IR"IM

~

DI

~
EI

'14:0

I

RET

r--16,0

-'0,5 ,

6,5

6,5

12,0

18,0

10,5

RRC

RRC

LDC

LDCI

LD

R,

IR,

'1. lrr2

Ir"lrr2

6,5

6,5

12,0

18,0

20,0

20,0

10,5

SRA

SRA

LDC

LDCI

CALL·

CALL

LD

(2· lrr,

7,0

HALT

,

INCW

6,0

STOP

,

18,0

RL

A,

f------

18,0

RL

F'

E

DEC

6.5

6.5

9

IRET

.~
RCF

r,.,x,R2

r-6,5

SCF

R,

IR,

1'2,lrr,

IRR,

'OA

'2,x,R,

6,5

6,5

6,5

10,5

10,5

10,5

10,5

r6,5

RR

RR

LD

LD

LD'

LD

LD

CCF

R,

IR,

", IR2

A2,R,

IR2,R,

A,.IM

'IR"IM

8.5

8.5

6,5

10,5

.SWAP
R,

SWAP

LD

LD

IR,

Ir,.r2

R2,IA,

~
NOP

. . . -----...v,.-----,; . . . -----...v,.----,.;, . . ------v,.------,;~~
2

3

2

3

LOWER
OPCODE

NllLE

EXECUTION

CVCLES
/.

PIPELINE
CVCLES

Lagend:
A = 8-bit address

, = 4-bit address
MNEMONtC

AI'orrl = Os! address
R2 or'2 = 8fC address

Sequence:
Opcode, First Operand, Second Operand

FIRST
OPERAND

·2·byte Instruction: fetch cycle appears as a 3-byte Instruction

148

SECOND
OPERAND

NOTE: The blank areas a,e not defined,

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect'
toGND, ........................ -0.3Vto +7.0V
Operating Ambient
.
Temperature .. : ........... See Ordering Information
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS

+5V
2.1K

The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:

• +4.5!> Vee !> + 5.5V
• GND = OV
• {) . C ~ T A ~ +70 C for S (Standard temperature)

Figure 12. Test Load 1

DC CHARACTERISTICS

Symbol

Parameter

Min

VCH

Clock Input High Voltage

VCl

Clock Input Low Voltage

VIH

Input High Voltage

Vil

Input Low Voltage

VRH

Reset Input High Voltage

VRl

Reset Input Low Voltage

VOH

Output High Voltage

VOH

Output High Voltage

VOL

1YP

Max

Unit
V

Driven by External Clock Generator

V

Driven by External Clock Generator

3.8

VCC

-0.3

0.8

2.0

VCC

.

V

-0.3

0.8

V

3.8

VCC

V

-0.3

0.8

V

2.4.

Vee -100mV
0.4

Output Low Voltage

Condition

V

IOH

V

ICC

V

IOl

= - 250 I'A

= -100JIA
=

+2.0 mA

III

Input Leakage

-10

10

".A

OV" VIN" + 5.25V

IOl

Output Leakage

-10

10

I'A

OV" VIN" + 5.25V

IIR

Reset Input Current

-50

I'A

VCC = + 5.25V, VRl = OV

ICC

Supply Current

mA

All outputs and 1/0 pins floating, 12 MHz

ICC1

Standby Current

ICC2

Standby Current

5
10

mA

Halt Mode

".A

Stop Mode

lee2 requires loading TMR (%F1) with any value prior to STOP execution.
Use the sequence:

LD TMR, #00
NOP
STOP

149

PORT 0,

OM

PORT 1

I-------{(!»----I
______________~__i1--~----~0~--------1r---~---­
Di
(READ)

PORT 1

00-07 OUT

Di ----------------~~--~I·--------{0~-----I~--------­
(WRITE)

Figure 13. External 110 or Memory Read/Write

AC CHARACTERISTICS
External 1/0 or Memory Read and Write Timing

12MHz
16MHz
20MHz
Min Max Min Max Min Max

Number. Symbol

Parameter

1
2
3
4
5

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TdAZ(DS)

Address Valid to AS tOelay
AS tlo Address Floal Delay
ASHo Read Data Req'd Valid
AS Low Width
Address Float to OS +

6
7
8
9
10

TwDSR
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)

OS (Read) Low Width
OS (Write) Low Width
DSHo Read Data Req'd Valid
Read Data to DStHoid Time
OS tlo Address Active Delay

11
12
13
14
15

TdDS(AS)
DStio AS+Delay
TdR!W(AS) RIW Valid to AStDelay
TdDS(RIW) OS tlo RIW Not Valid
TdDW(DSW) Write Data Valid to OS +(Write) Delay
TdDS(DW)
DStio Write Data Not Valid Delay

16
17
18

TdA(DR)
TdAS(DS)
TdDI(DS)

Address Valid to Read Data Req'd Valid
AS tlo OS +Delay
65
75
Data Input Setup to OS t

19

TdDM(AS)

OM Valid to ASWeiay

Notes
1. When using extended memory timing add 2TpC
2. Timing numbers given are for minimum TpC
3. See clock cycle dependent characteristics table
4. 20 MHz timing is preliminary and subject to change

150

35
45
250

185
110

Noles

150

ns
ns
ns
ns
ns

2,3,4
2,3,4
1,2,3,4
2,3,4

55

1,2,3,4
1,2,3,4
1,2,3,4
2,3,4
2,3,4

20
25

25
35

. 55
0

Units

180
40
0

30
0

135
80

105
65

0
65

0
50

0
40

ns
ns
ns
ns
ns

45
33
50
35
55

35
25
35
25
35

25
20
25
20
25

ns
ns
ns
ns
ns

2,3,4
2,3,4
2,3,4
2,3,4
2,3,4

130

50

79

45
60

35
50

ns
ns
ns

1,2,3,4
2,3,4
1,2,3,4

30

20

ns

2,3,4

310

180

230

+ Test Load 1
• All timing references use 2.0V for a
logic "1" and 0.8V for a logic "0"

AC CHARACTERISTICS
Additiomil Timing Table

Symbol'

Parameter

1
2
3

TpC
TrC,TfC
TwC
TwTinL
TwTinH

Input Clock Period
Clock Input Rise & Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width

4
5
6
7
88

9

20 MHz
Min Max
50

37
75
3TpC

62.5 1000
10
21
75
3TpC

15
75
3TpC

1
1
1
2
2

8TpC'
100
70
3TpC
3TpC

8TpC
100
70
3TpC
3TpC

8TpC
100
70
3TpC
3TpC

2
2'
2,4
2,5
2,3

83

TpTin
Timer Input Period
TrTin,TfTin . Timer Input Rise and Fall Times
TwlL
Interrupt Request Input Low Time
TwlL
Interrupt Request Input Low Time
TwlH
Interrupt Request Input High Time

SA

16 MHz
Min Max

12MHz
Min Max

Number

1000
15

Notes

1000
10

Notes:
1. Clock timing references use 3.8 V for a logic "I" and 0.8 V for a logic "0"
2. TIming references use 2.0 V for a logic "I" and 0.8 V for a logic "0"
3. Interrupt references request via, Port 3
4. Interrupt request via Port 3 (PS, - ps.)
5. InterrupBequest via PSO
6. 20 MHz timing Is preHmlnary and subject to change.
Unfts in nanos&C?Onds (ns)

DATAIN

Ii.W

--v:

V-SS -

DATAINVAUD

- - - - ~~A~A-;;;;

-

-

-

-

-

-

~

---f\......;..-------~SS - - - - - - - - - - - - - - -...:..

__ L-5~~;)-IE:.-j-0...,,---

_-k---'-J_r~ ~~~-

-_-.J'-l

ROY

-,

I

,/

DAlAYED ROY

J

,,'----S'S--/- - - - - .J'
Figure 15a. Input Handshake Timing

==><-------------------....155- - - - - - - - - --------,

DATAOUT

DATA OUT VAUD

---------------~55-

NEXT DATA OUT VAUD

Figure 15b. Output Handshake Timing

151

PIO
Pll
PI2
PI3
PI4
7 PI5
PI6
PI7

7

7

POO
POI
P02
P03
P04
P05
P06
P07
R/W

P20
P21
P22
P23
P24
E-< P25
J:£l. P26
;;:s:::
P27
U
0
if.)
P30
,..... P31
C\2 P32
P33
~
CO P34
OJ
P35
N
P36
P37

AO

Eo-<
J:£l
~

U

0

if.)

A9
AIO
All
Al2
27
lK Ohm

20

lK Ohm

22

PGM

06
07

-:t'
CO
r'C\2

0

Eo-<

es

vee
VPP

OE

GNO

XTALI
XTAL2

2

X

lK Ohm

10K Ohm

EXTERNAL
POWER
SUPPLY

I

O.OIUI

RECOMMENDED VOLTAGE: 12.5Vol\.

Z86E21 Z8 OTP Programming Adapter

Figure 14. Additional Timing

152

AC CHARACTERISTICS
Handshake Timing

Number
1
2
3
4
5
6
7

8
9
10
11

Symbol
TsDI(DAV)
ThDI(DAV)
TwDAV
TdDAV(RDy)
' TdDAV(RDY)
TdRDY(DAV)
TdDO(DAV)
TdPAVd(RDy)
TdRDY(DAV)
TwRDY
TdRDY(DAV)

Parameter

Data In Setup Time
Data In Hold Tune
Data Available Width
DAVHo RDYIDeiay
DAVtto RDYtDelay
RDYtto DAVIDelay
Data Out to DAV I Delay
DAVUo RDYIDeiay
RDYUo DAVtDelay
ROY Width
RDYtto DAV~DeI~

12,16,20 MHz
Min Max
0
145
110
115
115
0
TpC
0

Notes (Data Direction)
In
In
In
In
In
In

Out
115

Out
Out
Out

115

Out

110

CLOCK DEPENDENT AC CHARACTERISTICS
External 110 or Memory Read and Write Timing
Number

'Symbol

Equation

1
2
3
4
6
7

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
TdDS(A)
TdDS(AS)
TdRIW(AS)
TdDS(RIW)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)
TsDI(DS)
TdDM(AS)

0.4TpC+0.32
0.59TpC-3.25
2.83TpC+6.14
0.66TpC-1.65
2.33TpC-10.56
1.27TpC+ 1.67
1.97TpC-42.5
0.8TpC
0.59TpC-3.14
O.4TpC
0.8TpC-15
0.4TpC
0.88TpC-19
4TpC-20
0.91TpC-10.7
0.8TpC-10
0.9TpC-26.3

8
10
11
12
13
14
15
16
17
18
19

153

154:

~ZiIm

PRELIMINARY PRODUCT SPECIFICATION

Z86C27 DTC,
Z86C97 DTC
MAY

1989

DIGITAL TELEVISION CONTROLLERS

FEATURES
•

CMOS technology operating over a 3 to 6 volt power
supply range.

•

Complete single-chip microcomputer:

Mask programmable 128 character typeface with
English, Korean, Chinese and Japanese ROM-less
versions available.
.
Programmable color attributes including row
character, row background/fringe, frame
background, and bar graph color change.

8 bit Z8 core processor with 256 byte register file,
Watch Dog Timer, Power On Reset, Brown-out
protection, 43 I/O lines and 2 channel Counterl
Timer.
8K byte internal program ROM (Z86C27) or 64K
byte external program/data memory interface
(Z86C91).
•

On-Screen Display video controller:
20 character by 6 row screen format

Programmable display position and character size
control.
•

13 Pulse Width Modulator outputs for digital to analog
conversion - require a simple external RC low pass
filter.
12 volt open drain outputs
14-,8- and 6-bit resolutions

12 by 15 pixel character cell

GENERAL DESCRIPTION
The Z86C27 and Z86C97 are .CMOS Application Specific
Standard Product microcomputers that integrate specialized peripheral functions (normally provided by external
components) for the control of color television relat,ed
products. Utilizing Zilog's advanced Superintegration""
design methodology, these devices provide an ideal cost,
performance and reliability solution for consume( and
industrial television applications.

The devices have an 8 bit internal data path conlrolled by
a Z8 microcontroller core with 256 bytes of register space.
On-chip peripherals include a two channel Counter/Timer,
an On-Screen Display video controller, .a 13 thannel
Digital-la-Analog converter and comprehensive Input/Output ports. The Z86C27 is the mask-ROM high volume
production device embedded with a custom (customer
supplied) program of up to 8 K bytes in size (Figure 1). The
Z86C97 is the ROM-less version for prototyping and low
volume production (Figure 2).

155

PIN CONFIGURATIONS

PWM5
'PWM4
PWM3
PWM2
PWM1
P35
P36
P34
P31
P30
XTAL1
XTAl2
RESET
P60
Vas
P61
P62
Vee
P63
P64
P65
AFCIN
P50
P51
P52
P53
P54
P55
P56
P57
OSCIN
OSCOUT

2
3
4
5
6
7
8.
9
10
12
13
14
15
16
17
18
19
20

21 .
22
24
25
26
27
28
29
30
31
32

64
63

62
61
60
59
58

57
56
55

54
53
52
51
50
49
48

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
P27
P26
P25
P24
P23
Vas
P22
P21
Vee
P20
P47
P46
P45
P44
P43
P42
P41
P40
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC

Figure 1, Z86C27 mask-ROM Plastic Dip

156

PWM5
PWM4
PWM3
PWM2
PWM1
P35
P36
P34
P31
P30
XTAL1
XTAl2

REsET
AS
Vas

Os
RIW

Vee
SCLK
PSG
P67
AFCIN.
POO
P01
P02
P03
P04
P05
P06
P07
OSCIN
OSCOUT

64

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

63
62
61
60
!?9
58
57
56
55
54
53
52
51
50
49
48

47
46
45
44
43
42

•

41
40
39
38
37
36
35
34
33

PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
P27
P26
P25
P24
P23
Vas
P22
P21
Vee
P20
P17
P16
P15
P14
P13
P12
P11
P10
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC

Figure 2. Z86C97 ROM-less Plastic DIP

PIN IDENTIFICATION
Z86C27 mask-ROM

Z86C97 ROM-less

Pin

Name

Function

Pin

Name

Function

1-5
6,7,8
9, 10
11, 12

PWM5-PWM,
P35 , P36 , P34
P3" P3a
'
XTAL" XTA~

Pulse Width Mbdulator Output
Port 3 Outputs
Port 3 Inputs
Microcontroller Crystal Oscillator

1-5
6, 7, 8
9, 10
11, 12

PWM 5-PWM,
P35 , P36 , P34
P3" P30
XTAL" XTAt.;

Pulse Width Modulator Output
Port 3 Outputs
Port 3 Inputs
Microcontroller Crystal Oscillator

13
RESET(Test1 )
14
P60
15
Vss
16, 17 P6" P62

System Reset (Test1) Input
Port 6 bit 0 Input
Power Supply Ground
Port 6 bits 1 and 2 Input

13
14
15
16

RESET(Test1) ~ystem Reset (Test1) Input
AS
Address Strobe, Output
Power Supply Ground
Data Strobe, Output

~

18
19-21
22
23-30

Voo
P6a-P65
AFC1N
P50-P57

Power Supply Positive
Port 6 bits 3 thru 5 Input
AFC Analog Input'
Port 5 bits 0-7, Output (LED)

17
18
19
20,21

R/W
Voo
SCI.K
P6s ' P~

31,32
33
34
35'

OSCIN,OSCour
HsyNC
Vf!NNC
Vrm

Video Dot Clock Oscillator
Horizontal Sync Input
Vertical Sync Input
Video Red Output

22
23-30
31, 32
33

AFC Analog Input
Port 0 bits 0-7, Output (As-,5 )
OSC1N , OSCour Video Dot Clock Oscillator
Horizontal Sync Input
HSYNC

36
37
38
39-46

VGREEN
VBL~
V8UHt(
P4o-P47

Video Green Output
Video Blue Output
Video Blank Output
Port 4 bits 0-7, Output

34
35
36
37

VSY~
Vrm
VGREEN
VBWE

47
48
49,50
51

P2cj
Voo

Port 2 bit 0, I/O
Power Supply Positive
Port 2 bits 1, and 2, I/O
Power Supply Ground.

38
V8UHt(
39-46 P1 o-P1 7
47
P20
48
Voo

Video Blank Output
Port 1 bits 0-7, Output (AD()'7)
Port 2 bit 0, I/O
Power Supply Positive

49,50
51 .
52-56
57-64

Port 2 bits 1, and 2, I/O
Power Supply Ground
Port 2 bits 3 thru 7, I/O
Pulse Width Modulator Output

P21'P~,

Vss'

Port 2 bits 3 thru 7, I/O
52-56 P2 a-P27
57-64 PWM,s-PWMs Pulse Width Modulator Output

Read/Write, Output
Power Supply Positive
System Clock, Output
Internal AFC Comparator (Out)

AFC IN

POO-P07

Vertical Sync Input
Video Red Output
Video Green Output
Video Blue Output

PIN FUNCTIONS
AFCII. AFC Analog Voltage,(input). Input to two comparators used for AFC voltage analog to digital cohversion. The
comparator outputs are internally connected to P66-7 for
the Z86C27. They are. external outputs for the Z86C97
ROM-less part.
AS. Address Strobe - ZB6C97( output). External addresses
and R/W status are valid at the trailing edge of this strobe.

OS. Data Strobe ~ Z86C97 (output). Read and write data
transactions are controlled by this strobe.

HSYNC• Horizontal Sync(input). HSYNC is an input pin supplying an externally generated Horizontal Sync signal of either
negative or positive polarity.

OSCII' OSCour Video Oscillator (input/output). These
pins connect to the ihternal video dot clock L-C oscillator
circuit.
POO·po7. High Address Bus - Z86C97 (output). The ROMless device uses this port to output the high order address
(As-'6) during an external memory cycle.

157

•

P1 0·P1 7 • Multiplexed Address/Data Bus - ZB6C97. The
ROM-less device uses this port to multiplex low order
address (A0.7 during AS) and data (D0.7 during DS) for an
extemal memory cycle.
P20·P27. Port 2(inpuVoutput). This 8 bit general purpose
port is bit programmable for either input or output. The
output drivers (for bits defined as outputs) are globally
programmable as either push-pull or open-drain.

a

P30 ' Port 3 bit (input): This input may be read directly. A
negative edge event will be latched in IRQ3 to initiate an
IRQ3 vectored interrupt if appropriately enabled. P30 going
high will also initiate a STOP mode recovery if the device
is stopped.

PWM1 . 14bitPWM (output). PWM, is the output of a 14_bit
resolution Pulse Width Modulator or may be programmed
as a general purpose output. In either case, the output
driver is a 12 volt open-drain. PWM 1 is typically used as the
D to A converter for Voltage Synthesis Tuning systems.
PWM2·PWM•. 6-bit PWM's(outputs). Pins PWM 2-8 are out-'
puts of 6-bit resolution Pulse Width Modulator circuits.
PWMo·PWM13• 8-bit PWM's (outputs). Pins PWM9-'3 are
outputs of 8-bit resolution Pulse Width Modulator Circuits or
may be individually programmed as general purpose
outputs. In either case, the output drivers are 12volt opendrain.
R/W. Read/Write Status - Z86C97 (output). A low level
signifies an external memory write cycle.

P31• Port 3 bit 1 (input). This input may be read directly. A
negative edge event will be latched in IRQ2 to initiate an
IRQ2 vectored interrupt if appropriately enabled. It can
also be programmed to serve as the TIN signal to Timer 1.

RESET. System Reset. A low level on RESET forces a cold
restart of the device.

P3•• P3s ' Port 3 bits 4 and 5 (outputs). These pins are
general purpose output bits.

VBLANK • Video Blank (output). Output of the Blank video
signal. May be programmed for either polarity.

P31 • Port 3 bit 6 (output). P36 may be used as a general
purpose output bit or may be programmed to output TOI.JT
(from Timer 1 or Timer 2) or SClJ('

VBLUE' Video Blue (Output). Output of the Blue video signal.
May be programmed for either polarity.

Vee. Vss. Power and Ground. Care must be taken to
P40·P47 • Port 4 - Z86C27(output). Port 4 is an 8-bit output
port.
P50·P57 • Port 5- Z86C27(output). Port 5 is an 8-bitoutput
port with a higher current sink capability - suited for driving
the cathodes of a multiplexed LED display.
P6o·P6s' Port 6 - Z86C27 only(inpu!). port 6 is a 6-bit input
port. Bits 6 and 7 are intemally connected to the outputs of
the AFC comparators.
P61• P67. AFC Comparator Outputs - Z86C97 only. These
pins serve as outputs for the intemal comparators used in
the AFC IN analog to digital converter. They may be connected.to bits 6 and 7 of an extemal Port 6 emulation port
if required.

158

adequately bypass the supplied voltage at the device
power pins. Two bypass capacitors of .1JlF each are reCommended - one on each side of the device located as close
as possible to the pins.
VCREEN ' Video Green (output). Output of the Green video
signal. May be programmed for either polarity.
VRED' Video Red (output). Output of the Red video signal.
May be programmed for either polarity.
VSYNC' Vertical Sync (input). VSYNC is an input pin supplying
an externally generated Vertical Sync signal of either
negative or positive polarity.
XTAL 1 • XTAL2 • Oscillator (input and output). These pins
connect to the internal clock oscillator circuit. XT AL, may
also be used as an external clock input.

XTAL1
XTA12
RESET

8K Byte
Program ROM
Port 2
zacPu
Core

P30
P31
P34
P35
P36
P40( Pl0)
P41( Pll )
P42( P12)
P43( P13)
P44( P14)
P45( P15)
P46(P16 )
P47( P17)
P50( POO)
P51( POl)
P52( P02)
P53( P03)
P54( P04)
P55( P05)
P56( POO)

PWMl
14 bit

PWM2
to
PWM8
6bH

Port4
(Port 1)

PWM9
to
PWM13
8bH

Port 5
(PortO)

P57(P~)

P60(AS)
P61( OS)
P62(RIW)
P63(SCLK)
P64( P66)
P65( P67)
AFCIN

On Screen
Display

Port 6
(Control)

P27
P26
P25
P24
P23
P22
P21
P20

PWMl
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
PWMll
PWM12
PWM13

OSCIN
OSCOlIT
HSYNC
VSYNC
VRED
VGREEN
VBLUE
VBLANK

Figure 3. Z86C27 (Z86C97) Block Diagram

159

INPUT/OUTPUT CIRCUITS
yeo

Mapping Symbolic Pad Types
to Pin Functions
Pin Name

Pad Type

Note
IN

XTALl' OSC IN
XTAL2, OSC OllT

High gain start,
low gain run
amplifier circuit

RESET

8

POO·P07
P1 o·P1 7
P2o·P27
P30·P31

6
4
5
2

P34·P36
P40·P47
P5o·P57
P6o·P65

3
3
2

Z86C27 only
Z86C27 only
Z86C27 only

3
3
9
7

Z86C97 only
Z86C97 only

Z86C97 only
Z86C97 only

Figure 5. Input only, Schmidt Triggered
(Pad Type 2)

3

P6 ·P6

~U? R/IN, SCLK
AFC IN
PWM 1·PWM 13
HSYNC , VSYNC

VAED,Vall);'
VGREEN' VBI.JH(

YOO

PAD

OUT

2
3

Figure 6. Output only (Pad Type 3)
VDO

voo
OEN

IN

Figure 4. Input only (Pad Type 1)

IN

Figure 7. Input/Output 3-state (Pad Type 4)

160

VDD

VDD

OD
OEN

OUT

RESET

A

IN

~------~~------~

Figure 8. Input/Output, 3-state, Open Drain
(Pad Type 5)

Figure 11. Reset Input Circuit (Pad Type 8)

VDD
OEN

VDD

OUT

P67

Figure 9. OUtput only, 3-state (Pad Type 6)

VDO

T,I----N
I

PAD

-e------t

Figure 12. AFC Input Circuit (Pad Type 9)

Figure 10. Output only, 12 volt Open Drain
(Pad Type 7)

161

ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
Parameter@ TA=25"C

Sym

Power supply voltage
Input voltage
Input voltage
Output Voltage

Vee
VI
V0(2)

Output current high. 1 pin
Output current high. all total
Output current low. 1 pin
Output current low. 1 pin

100
100
IQ
IQ(3)

Output current low. all total
Operating temperature
Storage temperature
Power Djssipation

IQ

Min

Max

-O.3V
+7V
-O.3V Vee +O.3V
-O.3V Vee +O.3V
-O.3V Vee +8V

V~l)

-1OmA
-10OmA
10mA
20mA

Note:
(1) Port 2 open drain
(2) PWM open drain outputs
(3) Port 5

200mA
-O"C
-65"C

+ 7O"C
+ 15O"C
2.2W
(Ta=7O"C)

STANDARD tEST CONDITIONS

VDD

Characteristics listed below apply for standard test conditions as noted.

Variance of V

Comment: Exposing the device to stresses' above those
listed in Absolute Maximum Ratings could cause permanent damage. Exposure to absolute maximum rating
conditions for extended periods of time.may effect device
reliability.

RLl

S' RLL and RLH

output Circuit

Vs

Standard CMOS output
+5V
Port 4 high current output
+5V
PWM 12 volt open drain output .+12V

Ru.

RLH

1K
.5K
4K4

2K
2K

RLH

Figure 13. Standard Output Test Load

CAPACITANCE

TA~25°C, Vcp=GND::OV, f=1.0MHz,
Unmeasurea pins to GND.

162

Parameter

Max

Input capacitance
Output capacitance
1/0 capacitance
AFCIN input capacitance

10pF
20pF
25pF
10pF

DC CHARACTERISTICS
TA=OOCto +70°C; Vcc=+4.5Vto +5.5V; Fosc=4inHz
Parameter
Input voltage low
Input voltage high
Reset input current
Schmidt Hysteresis
Output current low

Sym

Min

Vil
VIH

0
.7Vcc

VIf(

·1Vcc

IOL

0.7SmA
3.2mA
1mA
.3Vcc
.5Vcc
.2Vcc

2mA
4mA

TBD

-2mA

10L(1)
10L(2)

AFC Level 01 In
AFC Level 11 In
AFC Tracking
Output current high
Min. supply voltage
Inp.leakage current
Tri-state leakage
Supply current

V~l

VOl_II
VOl-VII
IOH
VioliN
lu
IOL
Icc
Iccl
1CC2

Note:
(1) Port 5
(2) PWM Open Drain

Typ

1.S.

-31JA
-101JA

21JA

Max

Conqition

.2Vcc
Vee
-BOIJA

VAL=OV

TBD
TBD
TBD
SVcc
.7Vcc
.2Vcc

VOL=.4V
. VOL =.4V
VOL ';'·4V

TBD
2.SV
31JA
101JA
20mA
3mA
lOIJA

VOH =Vcc-·4V
0, Vcc
0, Vcc

I

163

AC CHARACTERISTICS ( Z86C27 and Z86C97)

TA::::O°C to 70°C; Vcc=+4.5 V to +5.5V; Fosc=4MHz, Units in nS
8ym

No

Parameter

Min

Max

250

1000nS
15nS

1
2
3
4
5

TpC
TrC,TfC
TwC
TwTinL
TwTinH

Input clock period
Clock input rise and fall
Input clock width
Timer input low width
Timer input high width·

6

TpTin
TrTin,TfTin
TwlL
TwlL
TwlH

Timer input period
Timer input rise and fall
Int req input low (P31)
Int req input low (P30)
Int request input high

7

8A
88

9
10
11
12
13
14

TdPOR
Td LVIREll
TwF\ES
TdHsOI
TdHsOh

Power On Reset delay
Low voltage detect to Internal
Reset minimum width
HSYNC start to Vesc stop
HSYNC end to Vesc start

Notes:
1. Refer to DC Characteristics for details on

70nS
70nS
100
8TpC
- I

R~SET

condition

25mS
200nS
5TpC
2TpV

switching lewis.

AC TIMING DIAGRAM (Z86C27 and Z86C97)

XTAL1

IROn

Figure 14. External Clock

lin

I-----{B }-----4'""i

Figure 15. Counter Timer

164

100nS

70nS
3TpC
3TpC

Figure 16. Interrupt Request

100mS

3TpV
1TpV

Vee

14-----jl0}--~~

Internal RESET

External RESET

_---II
Figure 17. Power On Reset

HSYNC

OSC2

Figure 18. On Screen Display

165

AC CHARACTERISTICS UNIQUE TO Z86C97
TA=OoC to 70oC; VCC=+4.S Vto +S.SV; FOSC=4mHz
No

Sym

Parameter

Min

35
45

1
2
3
4
5

TdIl(AS)
TdAS(AS)
TdAS(DR)
TWAS
TdAZ(DS)

Address valid to AS delay
AS high to Address float delay
AS high to Read Data required
AS low width
Addr float to DS low

6
7
8

DS Read low width
DS Write low width
DS low to Read Data req'd
Read Data to DS high hold
DS high to Address active

185
110

10

TwDSR
Twosw
TdOSR(DR)
ThOR(DS)
TdDS(A)

11
12
13
14
15

TdDS(AS)
TdR}W(AS)
TdDS(RJW)
TdOW(DSW)
TdDS(DW)

DS high to AS low delay
R/W valid to AS high delay
DS high to R/W not valid
Write Data valid to DS low
DS high to Write Data not valid

55
35
55
35
55

16

TdA(DR)

Addre.sS valid to Read Data
required valid

17
18

TdAS(DS)
TdO'(DS)

AS high to DS-Iow delay
Data Input setup to DS high

9

220
55
5

Notes:
1. When using extended memory timing, for parameters 3, 6,7,8,16 and 18 add 2TpC (500 nS@4.0MHz).
2. Min and Max times are in nanoseconds unless otherwise noted.

166

Max

130
5
55

330
65
75

TIMING DIAGRAM (Unique to Z86C97)

,~

SCLK
XTAL1

'1'1

_'4

I

.'F2

_'4

I

I

'fS

.,
I

16

PORTO

RJW

PORT 1

OS
READ

PORT 1

AO-A7

DO-070ut

OS
WRITE

Figure 19. Z86C97 External Memory Read/Write Timing

167

STANDARD CHARACTER SETS

REGISTER SUMMARY

ENGLISH/KOREAN

Refer to the Z8 Technical Manual for standard Z8 register
and port descriptions. Registers shown here are specific
to the Z86C27/97.
.

Port Registers
Port 4

FC30h

17161s14131211101

TTTTTTTT

Output Control
o Logic Level 0
1 Logic Level 1

Figure 21. Port 4 Output Register
PortS

FC31h

17161s14131211101

TTTTTTTT

Output Control
o Logic Level 0
1 Logic Level 1

Figure 22. Port 5 Output Register

Port 6. Input
o Logic Level 0
1 Logic Level 1
AFC Output
00 GND thru V1
01 V1 thru V2
11 V2 thru Vee

Figure 23.. Port 6 Input Register

PWMRegisters
%FC10

PWM MODE

17161s14131211101

TTTTTTTT
876

S

4

3

2

1

Mode Control
OPWM
1 Output Port

Figure 24. PWM Mode Register
%FC11

PWM OUT

17161s14131211101

TTTTTTTT
876

S

4

3

2

1

Output Control
o Logic Level 0
. 1 Logic Level 1

Figure 20. English/Korean
Figure 25. PWM Port Output Register

168

%FC12

%FC19

PWM1 UPPER

IxlxI5141s1211101
1 - 1- - -

IxlxI5141s1211101

1

PWM1 HI Byte

Figure 26. PWM 1 High Value
%FC1S

PWM1 LOWER

Ixlxl5141s1211101

PWM 2 VAL

1'-----

PWM2Value

PWMS VAL

1 - 1- - - -

1

PWMSValue

PWM4 VAL

I x lxl5141s12111 0 1

PWM12 VAL

171615141s12111 0 1

1....._ _ _ _ PWM12Value

PWM5 Value

Figure 38; PWM 12 Value .
%FC1F

PWMs VAL

PWM1SVAL

171615141s12111 0 1

1 X I X 15 14 Is I 2 11 101

11.-.-___

PWM11Value

Figure 37. PWM 11 Value

Figure 31. PWM 5 Value
%FC18

1

1 - 1_ _ _ _

%FC1E

PWM5VAL

1 - 1- - -

PWM11 VAL

1 7 161 5 14 Is 12 11 10
PWM4Value.

Figure 30. PWM 4 Value

%FC17

PWM10 Value

Figure 36. PWM 10 Value'
%FC1D

Ixlxl5141s1211101

1

PWM10VAL

171615141s1211101

Figure 29. PWM 3 Value
%FC1S

PWM9 Value

Figure 35. PWM 9 Value
%FC1C

I x lxl5141sf2111 0 1

1

PWM9 VAL

171615141s1211101

Figure 28. P'WM 2 Value
%FC15

PWM8 Value

Figure 34. PWM 8 Value
%FC1B

Ixlxl5141s1211101

1

PWM8VAL

PWM1 Lo Byte

Figure 27. PWM t Low Value
%FC14

PWM7Value

Figure 33. PMW 7 Value
%FC1A

171s15141s1211101

11.-.-____

PWM7VAL

PWMS Value

Figure 32. PWM 6 Value

1

PWM1SValue

Figure 39. PWM 13 Value Register

169

OSO Registers
ROW SPACE
OSDC CNTRl

Ixlslsl4131211101

"~r=-1

c=---_

-

Retrace Blanking
High Resolution set
olow Res
1 High Res
Pixel Size
OOx 1
x2
x3
11 x4
Sync Polarity
o Positive
1 Negative

01
10

IT "

FCOl h

O-Off
1 -On

Figure 44. OSD Row Space Register
FADE POS

1 - 1_ _-

Vert Position Control
x4HORlines

Figure 41. OSD Venlcal Post ion Register
HOS POS

FCOSh

Ixlslsl41al211101
1..1- - - -

FC02h

BAR CNTnL

FCOSh

J7161sl~lx1211

11 T

101

~

I X 1xis 14 1312 11 10I
I..."--"--

Vertical Index

Figure 45. OSD Fade Position Register

Ixlxlsl4131211101
"

1

Inter Row Space
Fade Direction
0- Fade After
1 - Fade Before
L..-_ _ _ _ _ _ _ _ Fade On-Off

Figure 40. OSD cOntrol Register
VERT POS

FC04h

blslxl4131211101

FCOOh

HOR Position Control
x 4 DOT Clocks

Figure 42. OSD Horizontal PosHlon Register

Row Address
"Bar Color
Blue
Green
Red
Bar Color Enable

Figure 46". OSD Bar Control Register

BAR PeS

FC07h

Ixb,ls14131211101
1
Blue Background
Green Background
Red Background
RGB Polarity
0- Positive
1 --Negative
Fringe On-Off
o-Off
1 - On
eackground On-Off
0- Off
1 - On
Display On-Off
0- Off
1- On

Figure 43. OSD Display Attribute Register

170

Bar Column Position

Figure 47. OSD Bar Position Register

ORDERING INFORMATION
Part Number

Package

ROM

Z86C2708PSCRxxx
Z86C2708PSCRxxx
Z86C9708PSCR314

64-Pin DIP
64-Pin DIP
64-Pin DIP

Custom mask-ROM
Evaluation mask-ROM
Korean/English Char Gen

171

PRELIMINARY PRODUCT SPECIFICATION

~ZiIill

Z86C27EAB
EMULATION ADAPTER BOARD

May 1989

FEATURES
•

Z86C9708PSC 8 MHz ROM-less device.

•

27C64/27C256 EPROM ZIF socket.

•

Full Port 4, Port 5 and Port 6 functional emulation.

•

ICE support with third party analyzer-emulator available
from Orion Instruments.

•

On-board CPU Crystal and Video L-C oscillator circl,Jitsjumper selectable.

•

Z86C27 mask-ROM footprint or cable interface to target
system.

DESCRIPTION
The Z86C27EAB Emulation Adapter Board is specifically
designed to assist in the development of software for
Zilog's Z86C27 mask-ROM DiQital Television Controller.

An EPROM socket is provided to allow validation of I
customer ROM-code before submitting to Zilog for ge
eration of the Z86C27 ROM mask.

The board utilizes a Z86C97 ROM-less device that provides an address and data path (for access to external
memory and I/O) and additional emulation signals. As the
Z86C97 uses Port 4, Port 5 and Port 6 for the external interface, the emulation board simulates true Z86C27 port
functions with additional on-board logic (Figure 1).

In-Circuit Emulation with real time trace capability is sup
ported in conjunction with a "Unilab™" 8620 or 8420 analyzer-emulator available separately from Orion Instruments.
Orion is located at: 702 Marstlall Street. Redwood City, CA
94063 (Ph: 415/361-8883, FAX: 415/361-8970).

...

ADO-7 ...

~

AB/15

...
Z86C97
ROM-Less

;::iXTALJ
;:fL-Cl

-

Common
Signals

ZB6C27
P1P2

~~

A

----"-y
LOGIC

~

...

~J

AO-7 ....

'I"

~

27C641
27C256
ZIF
Socket

-yo

To Orion
"Analyzer"
Connector
P~

To
"Emulator"
Connector

~

Port 4,5,6
Emulation

Control Signals
U1

--

P4

....:
U2

U3

Figure 1. Z86C27EAB Block Diagram

173

PIN ASSIGNMENTS
Target Z86C27 Interface
The Z86C27 EAB can plug directly into the target socket or
may be connected via ribbon cable to the target if access
is difficult. Connectors P1 and P2 are used for the ribbon
cable interface or as test points (Table 1). The supplied
Cable Adapter has a corresponding P1 and P2 - do not
reverse the P1 and P2 assignments.
A ribbon cable connection will degrade signal integrity, so
the length of cable should be kept as short as possible. The
local crystal and L-C oscillator components mounted on
the Emulation Adapter Board should always be used if a
ribbon cable connection is selected.
Note that GND and VCC are both connected to the target
interface. Powerthe EAB board locally if the target system
can not supply sufficient current.

ORION Emulation Interface
Connectors P3 and P4 have signals allocated to allow a
direct connection to the ORION analyzer/emulator (Table
2). Connector P3 connects to the "Emulator" connector
and P4 to the "Analyzer" connector on the ORION. Use the
appropriate cables supplied by ORION.

Miscellaneous Connectors/Jumpers/Test
Points
P5 connects to power and may be used for power supply
connection if the target supply is not used. J1 and J2 allow
isolation of the target oscillator circuits. J3 provides test
pOints for the address decodes of videoram and the
simulated I/O ports (Table 3).

Table 1. Z86C27 Interface - P1, P2
P1

Target Z86C2
PIN
SIGNAL

P2

Target Z86C27
PIN
SIGNAL

1
2
3
4
5

PWM5
PWM4
PWM3
PWM2
PWM1

1
2
3
4
5

1
2
3
4
5

PWM6
PWM7
PWM8
PWM9
PWM10

64
63
62
61
60

6
7
8
9
10

P351
P36 "
P34
P31
P30

6
7
8
9
10

6
7
8
9
10

PWM11
PWM12
PWM13
P27
P26

59
58
57
56
55

11
12
13
14
15,16

XTAL11
XTAL2 1
RESET
P60
GND

11
12
13
14
15

11
12
13
14,15
16

P25
P24
P23
GND
P22

54
53
52
51
50

17
18
19,20
21
22

P61
P62
VCC
P63
P64,

16
17
18
19

20

17
18,19
20
21
22

P21
VCC
P20
P47
P46

49
48
47
46
45

23
24
25
26
27

P65
AFCIN
P50
P51
P52

21
22
23
24
25

23
24
25
26
27

P45
P44
P43
P42
.P41

44
43
42
41
40

28
29
30
31
32

P53
P54
P55
P56
P57

26
27
28
29
30

28
29
30
31
32

P40
VBLANK
VBLUE
VGREEN
VRED

39
38
37
36
35

33
34

OSCIN2
31
OSCOUF 32

33
34

VSYNC
HSYNC

34
33

Notes:
1. XTAL 1 and XTAL2 are connected to P1 via jumper biockJ2 pins 1-2
and 3-4. Leave these jumpers open for local crystal operation.
2. OSCIN and OSCOUT are connected toP1 via jumper block J1 pins 12 and 3-4. Leave these jumpers open for local L-C operation. .

174

Table 2. ORION Interface - P3, P4

EABP3
Pin Sig
1
2
3
4

Orion "Emul"
Pin Sig

A14
A12
A13
A7
A8

1
2
3
4
5

A14E
A12E
A13E
A7E
A8E

A6
A9
A5
All

9
10 A4

6
7
8
9
10

A6E
A9E
A5E
AllE

11 DS
12 A3
13.Al0
14 A2
15 ROMCS
16
17
18
19
20

5

EABP4
Pin Sig
1
.2
3
4
5

P27
P26
P25
P24
P23

Table 3. Misc. ConnectorslJumperslTest Points

·Orion "Anal"
PinSig.
1 M7
2 M6
3 M5
4 M4
5 M3

A4E

6 P22
7 P21
8 . P20
9 GND
10 RESET

6
7
8
9
16

M2
Ml
MO
GND
RES

11
12
13
14
15

OE
A3E
AlOE
A2E
CE

11
12
13
14
15

17
18
19
20
21

NMI
GND
K2
C7
K,l

Al
AO
GND
AD7
AD6

16
17
18
19
20

AlE
AOE
GND
D7E
D6E

16 17 DS
18 19 20-

22
23
24
25
26

C6
WR
C5
RD
C4

21
22
23
24
25

ADO
AD5
ADl
AD4
AD2

21
22
23
24
25

DOE
D5E
D1E
D4E
D2E

21
22
23
24
25

27 A15
28 ALE
NCNCNC-

26
27
28
29

AD3
INTP67
INTP66
P34

26
43
44
45
46

D3E
D15A
D14A
D8A
D13A

26 P30

6

7
8

3031 32 33 -

34-

47 D9A
48 D12A
49 Dl0A
50 DllA

GND
-

R/W
-

A15
-

P35
P36
P31

NC-

Pin

Signal

Comment

P5-l
P5-2
Jl-l,2
Jl-3,4

GND
VCC
OSCIN
OSCOUT

Ground test point or supply
VCC test point or supply
Open isolates OSCIN from target
Open isolates OSCOUT from target

J2-1,2
J2-3,4
J3-1
J3-2

XTALl
XTAL2
VRAM
P6

Open isolates XTAL 1 from target
Open isolates XTAL 1 from target
Test point for Videoram select signal
Test point for port 6 select signal

J3-3
J3-4

P5
P4

Test point for port 5 select signal
Test point for port 4 select signal

Unilab 8620/8420 Analyzer/Emulator Setup
The standard Orion software is distributed to support
either piggy-back or ROM-less versions of generic Z8
microcontroller products, The system must be especially
configured to support the Z86C27EAB development environment
1, Follow Orion instructions for installation and invocation
of standard Orion Z8 distribution software,
'2, Choose the extemal memory version of the l8,
3, From the main menu, press "F8" to select TOOLKIT
ROUTINES,
4, Press "F8" again to select CHANGE DISPLA Y OR
. LOG MODES,
5, Set the window settings as shown:
Disassembler
Symbols
Reset
MiscCollJmn
ContCollJmn
Misc #Ba~e
Paginate
Color
Log to File
Printer
Step-into
Debug

on
off
enabled

on

on
binary
on
on (if color display)
off
off
software
active

175

6. Type "EM-SET" [RETURN]. This command is used
for memory configuration.
7. Enable memory 0-37FF in "EMSEGF." Press "END"
key to save and exit.
8. Type "INTbATA" [RETURN]. This command
configures the stack to be intemal.
9. Type "EXTAAM" [RETURN].
configures the RAM to be extemal.

12. Type "8000 =READ" [RETURN]. This sets the
extemal RAM pointer to address 8000h.
13. Type "SAVE-SYS C27EAB" [RETURN]. This saves
a new system called C27EAB.

This command
14. Type "BYE" [RETURN] to exit from the Orion
environment.

10. Type "PTA =DO" [RETURN]. This command sets the
Orion Debug registers to DOh and D1 h of the Z8 register
file. The user program must not use these registers.

D

11. Type "2001 =OVERLAY" [RETURN]. Thiscommarid
sets the Orion debug overlay area to start at address
2001h.

Now that the system is saved, to re-invoke the Orion
software with the parameters that have been just set-up,
type C27EAB.

@]

34

+

I

P2

COPYRIGHT.ZILOG INC. 1988
MADE IN U.S.A.
Z86C27EM

@]
64

f
0

~

33
C86C97

@]
@]

0

lliJ
34

I

P1

r===J

@]

Figure 2. Z86C27EAB Layout

176

IDD

32

c=J

ELECTRICAL CHARACTERISTICS

ORDERING INFORMATION

Refer to seperate data sheets for individual AC and DC
characteristics ofthe ZB6C970BPSC, ZB6C270BPSC, user
EPROM and Aitera™EP1B10J EPLD. Particularconsideration should be given to characteristic differences between
the ZB6C27 and the EAB board with respect to ports 4, 5
and 6.

Part Number

Comment

ZB6C270BEAB Includes ZB6C970BPSC ROM-less
device (Korean/English character
generator ROM).

Parameters listed in Table 4 are supplemental to the individual device parameters or apply to the EAB as a whole.

Table 4. Supplemental Parameters
Parameter

Sym

Min

Power supply voltage
Power supply current
Input voltage low
Input voltage high

Vcc
Icc
Vill
V1H '

4.Bv

Output current high
Output current low
Output current max
Operating Temp

IOH
IOL
IOHl

,

,
,

Max

Condition

5.2v
100mA
.Bv
0
2.0
VCC

-4mA,
4mA

VOH=2.4v
VOL =.45v
±~OmA

10"C

5O"C

Notes:
1. These parameters apply to Port 4, 5 and 6 and differ from the Z86C27
implementation.

177

178

~ ZiIm

Product Specification

January 1989

Z86C91.CMOS
BOMlep Z8®Mic..ompaler
FEATURES
• Complete microcomputer, 24 I/O lines, and up to 64K
bytes of addressable external space each for program
and data memory.

•

Full-duplex UART and two programmable 8-bit
counter/timers, each with a 6-bit programmable
prescaler.

• 256-byte register file, including 236 general-purpose
registers [S I/O port registers, and 16 status and control
registers.

•

Register Pointer so that short, fast instructions can
access anyone of the sixteen working-register groups.

• Vectored, priority interrupts for I/O, counter/timers, and
UAR1
• On-chip oscillator that accepts crystal or external clock
drive.

• Single

+ 5V power supply-aliI/a pins TIL compatible.

• 12,16, and 20 MHz
• CMOS process
• Two Low-power Standby Modes

GENERAL DESCRIPTION
The Z86C91 is a CMOS ROMless version of the Z8 singlechip microcomputer. It offers all the outstanding features of
the Z8 family architecture except an on-chip program

PORTO
(NIBBLE
PROGRAMMABLEI
1/0 OR Aa-A15

PORT 2
(BIT PRO·
GRAMMABLE)
I/O

PORT 1
(BYTE
PROGRAMMABLE)
ADo-AD7

PORT 3

SERIAL AND
PARALLEL 110
AND CONTROL

Figure 1. Pin Functions

ROM. Use of external memory rather than a preprogrammed ROM enables this Z8 microcomputer to be used
in applications where code flexibility is required.

+5V

P3,

XTAL2

P3,

XTAL1

P2,

P3,

P2,

P30

P2,

RESET

P2.

R/W

P2,

os

P2,

AS

P2,

P3,

P2,

GND

P3,

P3,

P3.

po,
po,
po,
po,
po.
po,
po,
po,

Pl,
Pl,
Pl,
Pl.
Pl,
Pl,
Pl,
Pl,

, Figure 2a. 40-pin Dual-ln·Line Package (DIP),
Pin AsSignments

179

The Z86091 can provide up to, 16 output address lines, thus
permitting an address space of up to 64K bytes of data or
program memory. Eight address outputs (ADo·AD7) are
provided by a multiplexed, 8·bit, Address/Data bus. The
remaining 8 bits can' be provided by the software
configuration of POrt 0 to output address bits Aa,·A15'
Available address space can be doubled (up to 128K bytes)
by programmillgpit 4 of Port 3 (P34) to act as a data memoiy
select 04tput (OM). The two states of OM together with the
16 address outputs can define separate data and memory
address spaces of up to 64K bytes each.

There are 256 bytes of RAM located on-chip and organized '
as a register file of 236 general-purpose registers, 16 control
and status registers, and three 110 port registers. This
register file can be divided into sixteen groups of 16 working
registers each. Configuring the register file in this manner
allows the use of short format instructions; in addition, any of
the individual registers can be accessed directly.
The, pin functions and the pin assignments of the Z86C91
package are illustrated in Figures 1 and 2.

+fJ ,p(f' .¢..~~~ ,p A > B
A > B > C
A > C > B
B > C > A
C > B > A
, B > A > C
. RESERVED

IRQ3, IROS PRIORITY (GROUP A)
o = IROS :;. IRDJ
1 =- IRQJ > IROS

IROO, IRQ2 PRIORITY (GROUP 8)
o
IRQ2:> IRao
1 "- IROO > IRQ2

:0

000

LDON'TCARE

'

= 001
= 010

REGISTER
POINTER

= 011
= 100

= 101

= 110
= 111

IRQt, IRQ4 PRIORITY (GROUP C)
~ IRQt > IRQ4
, " IRQ4 > IRQt

o

R250lRQ
Interrupt Request Register

R254 SPH
Stack Pointer

(FAH; Read/Write)

(FEH; Read/Write)

RESERVED (MUsl BE 0)

T

C='RQO
IR01

P32 INPUT .100 = IROO)
P331NPUT

IRaJ
IRQ4

P3tlNPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT

IROS

T,

IRQ2

R2511MR
Interrupt Mask Register

R255SPL
Stack Pointer

(FBH; Read/Write)

(FFH;,Read/Wrlte)

___
Il____c=

1 ENABLES IROo-tROS
= IROO)

(00

RESERVED (MUST BE 0)

L-_ _ _ _ _ _ _ 1 ENABLES

INTERRUPTS

Figure14. Control Registers (Continued)

191

OPCODEMAP
Lower Nibble (Hex)
A

B

C

o

E

6.5

12110.5

12110.0

65

12110 0

65

DJNZ

F
-------

'6516-5

I

DEC ' DEC

65

6.5

105

105

10.5

105

6.5

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

R,

IR,

(, f2

r1 Ir2

R2 R,

IR2·R,

R,IM

IR,.IM

f,.R2

f2· R ,

65

65

6.5

6.5

10.5

10,5

10.5

10.5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR"IM

f, RA

JR

LD

JP

INC

cc.RA

filM

cc DA

rl
~.----

R,

IR,1

(, ,(2

(,. lr2

R2·R,

IR2,R,

R,.IM

65

65

6,5

6.5

10.5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

-~

A

B

R,

IR,

SUB
f,.r2

(,. lr2

R2,R,

IR2,R,

R,.IM

8.0

6.1

6,5

6.5

10.5

10,5

10,5

IR IM
"
10.5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

1M

f'·(2

(,. lr2

R2·R,

IR2,R,

R,IM

8.5

8.5

6,5

6.5

10.5

10,5

10,5

IR IM
"
10.5

DA

DA

OR

OR

OR

OR

OR

OR
IR,.IM

R,

IR,

(,J2

(, ,lf2

R2,R,

IR2,R,

R"IM

10.5

10,5

6.5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND
IR"IM

o
E

F

-~~

-

R,

IR,

f,J2

(,. lr2

R2,R,

IR2,R,

R,.IM

6.5

6.5

6.5

6,5

' 10.5

10,5

10.5

10.5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R,

IR,

(',[2

f,. lr2

R2,R ,

IR2,R,

R,.IM

IR"IM

10112.1

12114,1

6.5

6,5

10.5

10,5

10.5

10,5

7,0

PUSH

PUSH

TM

TM

TM

TM

TM

TM

HALT

R2

IR2

(',[2

(,. lf2

R2,R,

IR2,R,

R"IM

IR,.IM

10.5

10,5

DECW

DECW

LDE

LDEI

RR,

IR,

(, ,lrr2

Ir,.lrr2

6,5

6,5

12.0

12,0

STOP

-

61
01

-

18,0

RL

LDE

LDEI

R,

IR,

f2 In,

Ir2·lrr,

EI

10,5

10.5

6.5

6,5

INCW

CP

CP

RR,

IR,

f,.r2

6.5

6,5

6.5

6,5

10.5

10,5

10.5

10.5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R,

IR,

('·(2

f,.lr2

R2·R,

IR2·R,

R,IM

f"

61

-

INCW

10.5

lr2

10,5

14.0

CP

CP

CP

CP

RET

R2,R,

IR2·R,

10,.5

R,.IM

10.5

IR"IM

6.5

12.0

18,0

IR IM
"
10.5

, RRC

RRC

LDC

LOCI

LD

R,

IR,

(,. lrf2

Ir"lrr2

f,.x,R2

6.5

65

18,0

20,0

20.0

SRA

SRA

LDC

LOCI

CALL"

CALL

LD

R,

IR'I

r2,lrr,

Ir2,lrr,

IRR,

DA

f2,X.R,

6,5

6.5

6,5

10.5

10.5

10,5

10.5

RR

RR

LD

LD

LD

LD

LD

R,

IR,

r" IR 2

R2·R,

IR2,R,

R,.IM

IR"IM

12.0

6':0

18,0

RL

6,5

C

-

8,5

8.5

6.5

SWAP

SWAP

LD

LD

R,

IR1

Ir,J2

R2,IR,

-

160

IRET

-

65

RCF
~
SCF

10.5

-

65

CCF

6D

10,5

NOP

......- - - -....v..-----# ......- - - -....v ...-----'-"# ......- - - - -....v ...- - - - -....# ~"--v---"
2
Bytes per Instruction

LOWER
OPCODE
NIB!LE
EXECUTION
CYCLES

4

PIPELINE
CYCLES

Legend:
R = 8-bit address
r = 4-bit address

MNEMONIC

R, or (,
R2 or (2

= Dst address
= Src address

Sequence:
Opcode, First Operand, Second Operand

FIRST
OPERAND

*2·byte Instruction, felch cycle appears as a 3-byte instruction

192

SECOND
OPERAND

NOTE: The blank areas are not defmed.

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND , , ' , , , ' , , , , , , , , , , , ' , , , ' , ,- 0.3V to + 7.0V
Operating Ambient
Temperature .... ,
..... See Ordering Information
Storage Temperature.
. ...... , .-65°Cto +150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device This IS a stress rallng only.
operation of the device at any condition above those Indicated In the
operational sections of these speCIfications is not Implied Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability,

STANDARD TEST CONDITIONS

+5V

\

. 2,'K

The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:

•

+ 4.5V ~ Vee ~ +S.5V

• GND = OV
• O°C" TA" + 7Q°C for S (Standard Temperature)

Figure 12. Test Load 1

DC CHARACTERISTICS
Symbol

Parameter

VCH
VOL
VIH
Vll
VRH
VRl
VOH
VOH
Va.
III

Clock Input High VoHage
3.SV
-0.3
Clock Input Low Voltage
Input High Voltage
2.0
Input Low Voltage
-0.3
Reset Input Low Voltage
3.S
-0.3
Reset Input Low Voltage
2.4
Output High Voltage
Vcc-100mV
Output High Voltage
Output Low Voltage
Input Leakage
-10
-10
Output Leakage
Reset Input Current
Supply Current
5
Halt Mode Current
Stop Mode Current

'101.

I'R
Icc
Icc,
1002

Min

Typ

Max

Unit

Condition

V

Driven by Extemal Clock Generator
Driven by Extemal Clock Generator

V

V
0.4
10
10
-SO

V
uA

10

uA

uA

uA
mA
mA

=-2mA
IOH = -100uA
101. = 5mA
VIN =OV,Voc
VIN = OV,Voc »
4.SVs,'vooSS.5V, VRl=OV
All outputs and 110 pins floating
All inputs driven at rail
All inputs driven at rail
10H

193

PORT 0,

DM

PORT 1

....1-- 18

1----(0~----

----~--~·--_r----~_i1.------~0~-------+1r_--~---­

DS
(READ)

PORT 1

OO-D7 OUT

DS ---------------~----_i 1.---~0~---1

}--------

(WRITE)

Figure 13. External 110 or Memory Read/Write

AC CHARACTERISTICS
Extemall/O or Memory read and Write Timing
20M Hz
12MHz
16MHz
Min Max Min Max Min Max . Units

Number Symbol

Parameter

1
2

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TdAZ(DS)

Address Valid to AS tDelay
AS tlo Address Float Delay
AStlo Read Data Req'd Valid
AS Low Width
Address Float to DS ~

35
45
55
0

40
0

30
0

6
7
8
9
. 10

TwDSR
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)

OS (Read)

Low Width
DS (Write) Low Width
DSHo Read Data Req'd Valid
Read Data to DStHoid Time
OS tlo Address Active Delay

185
110

135
80

105
65

0
65

0
50

11
12
13
14
15

TdDS(AS)
TdR/W(AS)
TdDS(RIW)
TdDW(DSW)
TdDS(DW)

DS tlo ASmelay
RIW Valid to AStDelay
DStlo Rm Not Valid
Write Data Valid to DS~(Write) Delay
DStio Write Data Not Valid Delay

45
33
50
35
55

35
25
35
25
35

16
17
18

TdA(DR)
TdAS(DS)
TdDl(DS)

Address Valid to Read Data Req'd Valid
AStio DSmelay
65
Data Input Setup to DS t
75

19

TdDM(AS)

DM Valid to ASmelay

3
4
5

Notes
1. When using extended memory timing add 2TpC
2. Timing numbers given are for minimum TpC
3. See clock cycle dependent characteristics table
4. 20 MHz timing Is preliminary and subject to change

194

20
25

25
35
250

2,3,4
2,3,4
1,2,3,4
2,3,4

55
0
40

ns
ns
ns
ns
ns

1,2,3,4
1,2,3,4
1,2,3,4
2,3,4
2,3,4

25
20
25
20
25

ns
ns
ns
ns
ns

2,3,4
2,3,4
2,3,4
2,3,4
2,3,4

75

180

45
60

35
50

ns
ns
ns

1,2,3,4
2,3,4
1,2,3,4

30

20

ns

2,3,4

310

50

150

ns
ns
ns
ns
ns

180

130

Notes

230

+ Test Load 1
• All timing references use 2.0V for a
logic "I" and O.SV for a logic "0"

CLOCK

T,N

IRQN~'

~

.~~. ~ ~
Figure 14. Additional Timing

AC CHARACTERISTICS
Additional Timing Table
Number

Symbol

Parameter '

1
2
3
5

TpC
TrC,TfC
TwC
TwTinL
TwTinH

Input Clock Period
Clock Input Rise & Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width

6
7
8A
88
9

TpTin
TrTin,Tmn
TwlL
TwlL
TwlH

Timer Input Period
Timer Input Rise and Fall Times
Interrupt Request Input Low Time
Interrupt Request Input Low Time
Interrupt Request Input High Time

4

16 MHz
Min Max

20 MHz
Min Max

50

37
75
3TpC

62.5 1000
10
21
75
3TpC

15
75
3TpC

1
1
1
2
2

8TpC
100
70
3TpC
3TpC

8TpC
100
70
3TpC
3TpC

8TpC
100
70
3TpC
3TpC

2
2
2,4
2,5
2,3

12MHz
Min Max
83

1000
15

1000
10

Notes

Noles:
1. clOck timing references use 3.8 V for a logic "1" and 0.8 V for a logic ''0''
2. l1ming references use 2.0 V for a logic "1" and 0.8 V for a logic ''0''
3. Interrupt references request via Port 3
4. Interrupt request via Port 3 (PS, - P3.)
5. Interrupt request via PSO
6. 20 MHz timing is pranmlnary and subject to change.
Units in nanoseconds (ns)

195

DATAIN

-v

k-,-J

5Aii

V-55 --

DATA INVALID

---./'-.~-------"'---55

b

>1

2

- - - -N;;:~A~A-;:;;; - - - - - - - - - - - - -- - - - - - - -

.

----~~=jn -~~~...::- -- jL,--?>+E-I<_.j"

RDY - - - - - - - - - _
'"

, /

DALAYED RDY

,-,---5'5--.../- - - - - --./

/

Figure 15a. Input Handshake Timing

DATA OUT

==><--------------------55- - - - - -- - DATA OUT VALID
NEXT DATA OUT VALID
-----------.....-----55- - - - - - - - - -

Figure 15b. Output Handshake Timing

AC CHARACTERISTICS
Handshake Timing

Number

Symbol

Parameter

1
2

TsDI(DAV)
ThDI(DAV)
TwDAV
TdDAV(RDY)
TdDAV(RDY)
TdRDY(DAV)
TdDO(DAV)
T dDAVd(RDY)
TdRDY(DAV)
TwRDY
TdRDY(DAV)

Data In Setup Time
Data In Hold Time
Data Available Width
DAV Ho RDY melay
DAVUo RDYtDelay
RDYtio DAWDelay
Data Out to DAV ~ Delay
DAVHo RDymelay
RDYHo DAVfDeiay
RDYWidth
RDYfto DAVWelay

3
4
5
6

7
8
9
10
11~

196

12,16,20 MHz
Min Max
0
145
110
115
115
0
TpC
0
115
110
115

Notes (Data Direction)
In
In
In
In
In
In
Out
Out
Out
Out
Out

CLOCK DEPENDENT AC CHARACTERISTICS
ExtemalllO or Memory Read and Write Timing
Number

1

2
3
4
6
7
8
(O
11
12
13
14
15
16
17
18
19

Symbol
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
. TdDSR(DR)
TdDS(A)
TdDS(AS)
TdRIW(AS)
TdDS(RIW)
TdDW(DSW)
TdDS(DW)
TdA(OR)
TdAS(DS)
TsDI(DS)
TdDM(AS)

Equation
O.4TpC+O.32
O.59TpC-3.25
2.83TpC+6.14
O.66TpC-1.65
2.33TpC-10.56
1.27TpC+1.67
1.97TPC-42.5
O.8TpC
O.59TpC-3.14
OATpC
O.8TpC-15
O.4TpC
O.88TpC-19
4TpC-20
O.91TpC-10.7
O.8TpC-10
O.9TpC-26.3

197

188

~ ZiIm

Application Notes/Technical Articles

AUGUST 1989

Z8 Family
Design Handbook

199

MEMJRY SPACE AND REGISTER

line 4 of the Port 3 (P34) to ,select between
program and data meIOOry for external meIOOry operations.

ORGANIZATION
M3mory Space
The Z8 can address up to l26K bytes of
program and data memory separately from the on
chip registers. The l6-bi t program counter
provides for 64K bytes of program memory, the
first 2K bytes of which are internal to the Z8.
The remaining 62K bytes of program meIOOry are
located externally and can be implemented with
RCf.!, EPRCf.!, or' RAM.
The 62K bytes of data memory are also located external to tne Z8 and begin with location
2048. The two address spaces, program memory
and data memory, are individual~ selected by
the Data Memory Select output (I:M) which is
available from 'Port 3.
The Program Memory Map and the Data M3IOOry
Map are shown in Figure 2.
Program Memory Map
65535

EXTERNAL

....
204'

ROM OR RAM

LOCATION OF FIRST
BYTE OF INSTRUCTION ~

EXECUTED AFTER RESET

,.
12

INTERRUPT VECTOA
CLOWER 8YTE)

INTERRUPT VECTOR
(UPPEA 8YTEj

ON-CHIP

ROM

------------

EXTERNAL
DATA
MEMOAY

IROS
IAQS

••
7

IRQ4
IH03

• r-

IR02
IR02

•

Data Memory Map
• 5535

IRQ4

IRQ3

tR01

...."47

IRol

IROO
IROO

NOT ADDRESSABLE

Figure 2 Program Memory Map And Data Memory Map

Port 0 is used to provide the additlonal
address bits, for external memory beyond the
first 256 locations up to a full l6-bits of
external meIOOry address. It becomes ilTl!lediately
obvious that the first 8-bits of external memory
address from Port 1 must be latched externally
to the Z8 so that program or data may be transferred over the same 8 lines during the external
memory transaction machine cycle. The AS, m,
and R/W control lines simplify the required
interface logic. The tllning for external memory
transactions is given in Figure 3.
Reglsters
The ZS'has 144 8-bit registers including
four Port registers (RD-R3), 124 general purpose
registers (R4-Rl27), and 16 control and status
register (R240-R255). The 144 registers are all
located in the same 8-bit address space to allow
any Z8 instruction to operate on them. The 124
general purpose registers can function as accumulators, address pointers, or index registers •
The registers are read wnen they are referenced
as source registers, and written when they are
referenced as destination registers. Registers
may be addressed directly with an 8-bit address,
or indirectly through another register with an
8-bit address, or Wlth a 4-bit address and Register Pointer.
The entire Z8 register space may be divided
into 16, contiguous Working Register Areas, each
having 16 registers. A control register, called
the Register Pointer, may be loaded with the
most significant nibble of a 'Working Reglster
Area address. The Register POlnter'provides for
the selection of the WorKing Register Area, and
allows registers within that area to be selected
with a 4-bit address.
The Z8 register organization is shown in
Figure 4.
Stacks

External meIOOry access is accomplished by
the 28 through its I/O Ports. When less than
256 bytes of external meIOOry are required, Port
1 is programmed for the multiplexed address/data
IOOde lAD0-AD7). In this configuratlon 8-bits of
address and 8-bits of data are time multiplexed
on the 8 1/0 lines for meIOOry transfers. Tne
memory "nandshake" control lines are provided by
the Address Strobe (AS'), Data Strobe (1lS), and
the Read/Write (R/W) pins on the ZS. If program
and data are included in the external meIOOry
space, the Data Memory Select (m) function may
be programmed into the Port 3 Mode register.
When this is done, the 'IN signal is available on

200

The Z8 provides for stack operations
through the use of a stack pointer, and the
stack may be located ln the internal register'
'space or in the external data meIOOry space. The
"stack selectlon" bit (D2) in the Port 0-1 Mode
control register selects an internal or external
stack. When the stack is located internally,
reglster 255 contains an 8-bit staCK pointer and
register 254 is available as a general purpose
register. If an external stack is USed, register
255 or registers 254 and .255 may be used as the
stack pointer depending on the anticipated
"depth" of the stack. When registers 254 and
255 are both used, the stack pointer is a full
l6-bits wide. The CALL, IRET, RET, PUSH, and

pop instructions are Z8 instructions which include implicit stack operations.
I/O S1RUcruRE
Parallel I/O
The Z8 microcomputer has 32 lines of I/O
arranged as four 8-bit ports. All of the I/O
ports are TTL compatible and are configurable as
input, output, input/output, or address/data.
The handshake control lines for Ports 0, 1; and
2 are bits from Port 3 that have been programmed
through a Mode control register, except for AS,
~, and R/Wwhich are availaole as separate Z8
pins. The I/O ports are accessed as separate
internal registers by the Z8. Ports 0 and 1
share one Mode control register, and Ports 2
and 3 each have a Mode control register for
configuring the port.
Port 0 can be programmed to be an I/O port
or as an a4dress output port. M:>re specifically
Port 0 can be configured to be an 8-bit I/O port
or a 4-bit address output port (AS-All) for
'
external memory and one 4-bit I/O port, or an
8-bit address output port (AS-Al5) for external
memry.

Port 1 can be programmed as an I/O port
(with or without handshake), or an address/data
port (~-AD7) for interfacing with external
memory. If Port 1 is programmed to be an address/data port, it cannot be accessed as a register.
Port 2 can be configured as individual
input or output bits, and Port 3 can be programmed to be parallel I/O bits, and/or serial I/O
bits, and/or handshake control lines for the
other ports. Figure 5 shows the port Mode
registers.
The off chip expansion capability using
Ports 0 and 1 offers the added feature of being
Z-Bus compatible. All Z-Bus compatible peripheral chips that are available now, and will be
available in the future, will interface directly
W1 th the Z8 rultiplexed address/data bus.
Serial I/O
As memtioned in the last section, Port 3

can be PI'9grammed to be a serial I/O port with

bits 0 and 7, the serial input and serial outrespectively. The serial I/O capabilIty proVldes for full duplex asynchronous serial
data at rates up to 62.5K bits per second. The
transmitted format is one start bit, eight data
bits including odd parity lif parity is enab- led), and two stop bits. '!he received data
format is one start bit, eight data bits and at
least one stop bit. If parity is enabled, the
eighth data bit received (bit 7) is replaced by

~ut line~

a parity error flag which indicates a parity
error if it is set to a ONE.
Timer/Count~r TO is the baud rate generator
and runs at It> times the serial data bit rate
The receiver is double duffered and an inte~l
interrupt (IRQ3) is generated when a Character
i~ loaded ~to the :eceive buffer register. A
dIfferent Internal Interrupt (IRq4) is generated
when a character is transmitted.

COUNI'ER/TIMERS
The Z8 has two 8-bit programmable counter/

timers, each of which is driven by a programmable 6-bit prescaler. The TI pres caler can be
driven by internal or externa clock sources,
and the Tn prescaler is driven by the internal
cloCk only. The two prescalers and the two
counters are loaded through four control registers (see Figure 4) and when a counter/timer
reaches the "end of count" a timer interrupt is
generated (IRQ4 for TO' and IRQ5 for T ). The
counter/timers can be programmed to sthp upon
reaching the end of count, or to reload and
continue counting. Since either counter (one at
a time) can have its output available external
to the Z8, and Counter/Timer Tl can have an
external input, the two counters can oe cascaded.
Port 3 can be programmed to provide timer
outputs for external time base generation or
trigger pulses.
INl'ERRUPT S1RUcruRE

The Z8 provides for six interrupts from
eight different sources including four Port 3
lines (P30-P33), serial in, serial out, and two
counter/timers. These interrupts can be masked
and prioritized using the Interrupt Mask Register (register 251) and the Interrupt Priority
Register (register 249). All interrupts can be
<;lisabled with the master interrupt enable bit
In the Interrupt Mask Hegister.
Each of the six interrupts has a 16-bit
interrupt vector that points to its interrupt
service routine. These six 2-byte vectors are
placed in the first twelve locations in the program memory space (see Figure 2).
When siDDJltaneous interrupts occur for
interrupt sources, the Interrupt PriorIty RegIster determines which interrupt is serviced first. The priority is programmable in a
way that 1s described by Figure 6.
~nabled

When an interrupt is recognized by the Z8,
all other interrupts are disabled, the program
counter and program control flags are saved, and
the program counter is loaded with the corresponding interrupt vector. Interrupts must be
re-enabled by the user upon entenng the service

201

A Programmer's Guide to
the ZITI.! Microcomputer

~ZiIm

Application
Note
Doll Freund

October 1980

SECTION

1

Introduction
The 28 is the first microcomputer to offer
both a highly integrated microcomputer on a
single chip and a fully expandable microprocessor for I/O-and memory-intensive applications. The 28 has two timer/counters, a UART,
2K bytes internal ROM, !lnd a 144-byte internal register file including 124 bytes of RAM,
32 bits of I/O, and 16 control and status registers. In addition, the 28 can address up to
124K bytes of external program and data
memory, which can provide full, memorymapped I/O capability.
Acc~ssing

Register Memory
The 28 register space consists of four I/O
ports, 16 control and status registers, and 124
general-purpose registers. The generalpurpose registers are RAM areas typically used
for accumulators, pointers, and stack area.
This section describes these registers and how
they are used. Bit manipulation and stack
operations affecting the register space are
discussed in Sections 4 and 5, respectively.
2.1 Registers and Register Pairs. The 28 supports 8- bit registers and '16- bit register pairs.
A register pair consists of an even-numbered
register concatenated with the next higher
numbered register (%00 and %01, %02 and
%03, ... %7E and %7F, %FO and %Fl, ...
%FE and %FF). A register pair must be
addressed by reference to the even-numbered
register. For example,
%F1 and %F2 is not a valid register pair;
%FO and %F1 is a valid register pair,
addressed by reference to %FO.
Register pairs may be incremented (INCW)
and decremented (DECW) and are useful as
pOinters for accessing program and external
data memory. Section 3 discusses the use of
register pairs for this purpose.

202

This application note describes the important
features of the 28, with software examples that
illustrate its power and ease of use. It is
divided into sections by topic; the reader need
not read each section sequentially, but may
skip around to the sections of current interest.
It is assumed that the reader is familiar with
the 28 and its assembly language, as
described in the following documents:

• Z8 T~chnical Manual (03~3047-02)
• Z8 PLZIASM Assembly Language Programming Manual (03-3023-02)
Any instruction which can reference or
modify an 8-bit register can do so to any of the
144 registers in the 28, regardless of the
inherent nature of that register. Thus, I/O
. ports, control, status, and general-purpose
registers may all be accessed and manipulated
without the need for 'special-purpose instructions. Similarly, instructions which reference
or modify a 16-bit register pair can do so to
any of the valid 72 register pairs. The only
exceptions to this rule are:
• The DJN2 (decrement and jump if non-zero)
instruction may successfully operate on the
g.eneral-purpose RAM registers (%04-%7F)
only.
• Six control registers are write-only registers
and therefore, may be modified'only by
such instructions as LOAD, POP, and
CLEAR. Instructions such as OR and AND
require that the current contents of the
operand be readable and therefore will not
function properly on the write-only
registers. These registers are the following:
the timer/counter prescalerregisters PRED
and PREl, the port mode registers PDlM,
P2M, and P3M, the interrupt priority
register IPR.

2. Accessing
Register
Memory
(Continued)

2.2 Register Pointer, Within the register
addressing modes provided by the 28, a register may be specified by its full 8- bit address
(O-%7F, %FO-%FF) or by a short 4-bit
address. In the latter case, the register is
viewed as one of 16 working registers within a working register group. Such a group
must be aligned on a 16-byte boundary and is
addressed by Register Pointer RP (%FD). As
an example, assume the Register Pointer contains %70, thus pointing to the working register group from %70 to % 7F. The LD instruction may be used to initialize register %76 to
an immediate value in one of two ways:
LD %76,#1 !8-bit register address is given
by instruction (3 byte instruction)!
or
LD R6,#1
!4- bit working register address
is given by instruction; 4-bit
working register group
address is given by Register
Pointer (2 byte instruction)!

The address calc.ulation for the latter case
is illustrated in Figure I. Notice that 4-bit
working-register addressing offers code compactness and fast execution compared to its
8-bit counterpart.
To modify the contents of the Register
Pointer, the 28 provides the instruction
SRP #value
Execu tion of this instruction will load the
upper four bits of the Register Pointer; the
lower four bits are always set to zero. Although,
a load instruction such as
LD RP,#value
could be used to perform the same function,
SRP provides execution speed (six vs. ten
cycles) and code space (two vs. three bytes)
advantages over the LD instruction. The
instruction
SRP #%70
is used to set the Register Pointer for the above
example.

(0000(0001(

Figure I. Address Calculation Using the Register Pointer

2.3 Context Switching. A typical function
performed during an interrupt service routine
is context switching. Context switching refers
to the saving and subsequent restoring of the
program counter, status, and registers of the
interrupted task. During an interrupt machine
cycle, the 28 automatically saves the Program
Counter and status flags on the stack. It is the
responsibility of the interrupt service routine to
preserve the register space. The recommended
means to this end is to allocate a specific portion of the register file for use by the service
routine. The service routine thus preserves the
register sPilce of the interrupted task by avoiding modification of registers not allocated as its
own. The most efficient scheme with which to
implement this function in the 28 is to allocate
a working register group (or portion thereof)' to
the interrupt service routine. In this way, the
preservation of the interrupted task's registers
is solely a malter of saving the Register Pointer
on entry to the service routine, setting the
Register Pointer to its own working register
group, and restoring th~ Register Pointer prior
to exiting the service routine. For example,

assume such a register allocation scheme has
been implemented in which the interrupt service routine for IRQO may access only working
register Group 4 (registers %40-%4F). The
service routine for IRQO should be headed by
the code sequence:
PUSH RP
SRP

Ipreserve Register Pointer of
interrupted task!
#%40 laddress working register
group 4!

Before eXiting, the service routine should
execute the instruction
POP RP
to restore the Register Pointer to its entry
value.
It should be noted that the technique
described above need not be restricted to
interrupt service routines. Such a technique
might prove efficient for use by a subroutine
requiring intermediate registers to produce its
outputs. In this way, the calling task can
assume that its environment is intact upon
return from the subroutine.

203

2. Accessing 2.4 Addressing" Mode. The Z8 provides three
addressing modes for accessing the register "
Register
space: Direct Register, Indirect Register, and
Memory
(Continued)
"Indexed.

2.4.1 Direct Register Addressing. This
addressing mode is used when the target register address is known at assembly time. Both"
long (8-bit) register addressing and short
(4-bit) working register addressing are supported in this mode. Most instructions supporting this mode provide access to single
8-bit.registers. For example:
"
LD %FE,#HI STACK
!load register %FE "(SPH) with
the upper 8-bits of the label
STACK!
AND O,MASKJEG
!AND register 0 with register
named MASKJEG!
OR I,R5 lOR register I with working
register 5!
Increment word (INCW) and decrement
word (DECW) are the only two Z8 instructions
which access 16-bit operands. These instructions are illustrated below for the direct register addressing mode.
INCW RRO !increment working register
pair RO, RI:
RI -- RI +
RO -- RO + carry I
DECW"%7E
!decrement working register
pair %7E, %7F:
%7F .... %7F %7E -- %7E - carry!
Note that the instruction
!NCW RR5
will be flagged as an error by the assembl~r
(RR5 not even-numbered).
2.4.2 Indirect Register Addressing. In this
addressing mode, the operand is pointed to by
the register whose 8-bit register address or
4-bit working register address is given by the
instruction. This mode is used when the target
register address is not known at assembly time
and must be calculated during program execution. For example, assume registers %60-%7F
contain a buIfer for output to the serial line via
repetitive calls to procedure SERIAL_OUT.
SERIAL_OUT expects working register 0 to
hold the output character. The following
instructions illustrate the use of the indirect
addressing mode to accomplish this task:
LD·
Rl,#%20
!working register I is the byte
counter: output %20 bytes!

204

LD

R2,#%60"
!working register 2 is the, buffer pointer register!
out_again:
LD
RQ,@R2
!load into working register 0
the byte pointed to by working
'
register 2!
INC R2
!increment pOinter!
CALL SERIAL_OUT
!output the pytel
DJN2 RI,out _again
!loop till done I
Indirect addressing may also be used for
accessing a 16-bit register pair via the INCW
and DECW instructions. For example,
!NCW @RO !increment the register pair
whose address is contained in
working register O!
" DECW @%7F
!decrement the register pair
whose address is contained in
register %7F!
The contents of. registers RO and %7F should
be even numbers for proper access; when
referencing a register pair,· the least significant
address bit is forced to the appropriate value
by the 28. However, the register used to point
to the register pair need not be an evennumbered register.
Since the indirect addressing mode permits
calculation of a target address prior to the
desired register access, this mode may be used
to simulate other, more complex addressing
modes. For example, the instruction
SUB 4,BASE(R5)
requires the indexed addressing mode which is
not directly supported by the 28 SUBtract
instruction. This instruction can be simulated
as follows:
LD

R6,#BASE
!working register 6 has the
base address!
ADD R6,R5 !calculate the target address!
SUB 4,@R6 !now use indirect addreSSing to
perform the actual subtract I
Any available register or working register
may be used in place of R6 in the
above example.

2.4.3 Indexed Addressing. The indexed
addressipg mode is supported by the load
instruction (LD) for the transference of bytes
between a working register and another register. The effective address of the latter register
is given by the instruction which is offset by
the contents of a deSignated working (index)

2. Accessing
Register
Memory
(Continued)

register.' This addressing mode provides
efficient memory usage when addressing
consecutive bytes in a block of register
memory, such as a table or a buffer. The
working register used as the index in
the effective address calculation can
serve the additional role of counter for
control of a loop's duration.
For example, assume an ASCII character
buffer exists in register memory starting at
address BUF for LENGTH bytes. In order
to determine the logical length of the character string, the buffer should be scanned
backward until the first nonoccurrence of a
blank character. The following code
sequence may be used to accomplish
this task:
LD

RO,#LENGTH
!length of buffer!
!starting at buffer end, look for
1st non-blank!

loop:
LD

Rl ,BUF -l(RO)
Rl,#' ,
ne,found
!found non-blank!
DJNZ RO,loop
,
!look at next!
alL_blanks:
!length = O!
found:

CP
JR

5 instructions
12 bytes
1.5 p,s overhead
10.5 p,s (average) per character tested
At labels "all_blanks" and "found," RO
contains the length of the character
string. These labels may refer to the same
location, but they are shown separately for
an application where special processing is
required for a string of zero length. To perform this task without indexed addressing would require a code sequence
such as:

SECTION

3

Accessing Program and External Data
Memory
In a single instruction, the Z8 can transfer a
byte between register memory and either program or external data memory. Load' Constant
(LDC) and Load Constant and Increment
(LDCl) reference program memory; Load
External (LDE) and Load External and Increment (LDEI) reference external data memory,
These instructions require that a working
register pair contain the address of the byte in
either program or external data memory to be
accessed by the instruction (indirect working
register pair addressing mode). The register
byte operand is specified by using the direct
working register addreSSing mode in LDC and

LD
LD

RL#BUF + LENGTH-l
RO,#LENGTH
!starting at buffer end, look for
1st non-blank!

loopl:
@Rl,#, '
ne,foundl
!found non-blank!
DEC Rl
!dec pOinter!
DJNZ RO,loopl
!are we done?!
all_blanks 1: !length = O!
foundl:
6 instructions
13 bytes
3 p,s overhead
9.5 p,s (average) per character tested

CP
JR

The latter method requires one more byte of
program memory than the former, but is faster
by four execution cycles (l p,s) per character
tested,
As an alternate example, assume a buffer
exists as described above, but it is desired to
scan this buffer forward for the first occurrence of an ASCII carriage return. The following illustrates the code to do this:
LD

next:
LD

RO,# - LENGTH
!starting at buffer star\, look for
1st carriage return (= %OD)!

INC

r 1,BUF + LENGTH(RO)
Rl,#%OD
eq,cr !found it!
RO
!update counterlindex!

JR

nz,next

CP
JR

!tryagain!
cr:
ADD RO,#LENGTH
!RO has length to CR!
7 instructions
16 bytes
1. 5 p,s overhead
12 p,s (average) per character tested
LDE or the indirect working register addressing mode, in LDCI and LDEI. In addition to
performing the designated byte transler, LDCI
and LDEI automatically increment both the
indirect registers speCified by the instruction.
These instructions are therefore efficient for
performing block moves between register and
either program or external data memory. Since
the indirect addreSSing mode is used to specify
the operand address within program or external data memory, more complex addreSSing
modes may be simulated as discussed earlier
in Section 2.4.2. For example, the instruction
LDC

R3,BASE(R2)

requires the indexed addressing mode, where

205

3. Accessing
Program and
External Data
Memory
(Continued)

BASE is the base address of a table in pr~gram
memory and R2 contains the offset from table
start to the desired table entry. The following
code sequence simulates this instruction with
the use of two additional registers (RO and Rl
in this example).
LD
LD
ADD
ADC
LDC

LD

LD

The two bytes following the mode selecJion of
ports 0 and I should not reference external
memory due to pipelining of instructions within
the ZS. Note that the load instruction to P3M
satisfies this requirement (providing that it
resides within the internal 2K bytes of
memory).

RO,#HI BASE
Rl ,#LO BASE
!RRO has table start address!
Rl,R2
RO,#O
!RRO has table entry address!
R3,@RRO
!R3 has the table entry!

3.2 LDC and LDE. To illustrate the use of the
Load Constant (LDC) and Load External (LDE)
instructions, assume there exists a hardware
configuration with external memory and Data
Memory Select enabled. The following module
illustrates a program for tokenizing an ASCII
input buffer. The program assumes there is a
list of delimiters (space, comma, tab, etc.) in
program memory at address DELIM for
COUNT bytes (accessed via LDC) and that an
ASCII input buffer exists in external data
memory (accessed via LDE). The program
scans the input buffer from the current location
and returns the start address of the next token
(i.e. the address of the first nondelimiter
found) and the length of that token (number of
characters from tok~n start to next delimiter).

3.1 Configuring the Z8 for I/O Applications
vs. Memory Intensive Applications. The ZS
offers a high degree of flexibility in memory
and 1/0 intensive applications. Thirty-two port
bits are provided of which 16, 12, eight, or
zero maybe configured as address bits to
external memory. This allows for addressing of
62K, 4K or 256 bytes of external memory,
which can be expanded to 124K, SK, or 512
bytes if the Data Memory Select output (DM) is
used to distinguish between program and data
memory accesses. The following instructions
illustrate the code sequence required to configure the ZS with 12 external addressing lines
and to enable the D?ta Memory Select output.
Z8ASM
LOC

2.0
OBJ CODE

P 0000 20
P 0003 2E

3B
OA

STMT SOURCE STATEMENT

2C
00

1
2
3
4
5
6
7
8

P 0006

206

POIM,#%(2)0001001O
!bit 3-4: enable ADo-AD7;
bit 0-1: enable As-All!
P3M,#%(2)OOOOI000
!bit 3-4: enable DM!

SCAN
MODULE
CONSTANT
COUNT._
6
GLOBAL
$SECTION PROGRAM
DELIM
ARRAY
[COUNT BYTE]
[

•

f

, , , , ,
•••

, .' , %OA"

%00 I

9 scan
PROCEDURE
10 1*****************************************************

P 0006 BO

E2

0008
OOOA
OOOC
OOOF
P 0012

P
P
P
P

82
AO
06
FD
80

30
EO
002E'
0015'
0018'

p

0015 80

0008'

11 Purpose
To find the next token within an
12
ASCII buffer.
13
14 Input
RRO = address of current location
15
within input buffer in external
memory.
16
17
18 Output
RR4
address of start of next token
RRO
19
address of new token's ending
20
delimiter
21
R2
length of token
22
R3 = ending delimiter
23
R6,R7,R8,R9 destroyed
24
25 *****************************************************!
26 ENTRY
cl r
R2
27
!init. length count,er!
DO
28
LDE
R3,@RRO !ge~ byte from input buffer!
29
30
incw
RRO
!increment pointer!
31
call
check
Ilook for non-delimiter!
IF C THEN
32
EXIT
!found token start!
33
FI
34
00
35

P 0018 118
P 001A 58

EO
El

P 001C 2E

p 001D 82

P 001F D6
P 0022 7D
P 0025 8D

30
002E'
0028'
002D'

P 0028 AO
P 002A 8D

EO
001C'

P 002D AF
P 002E
P 002E

P 002E 6C
P 0030 7C

00*
00*

P 0032 8C

06

p

96
E6
93
03
F6

P
P
P
P
P

0034
0036
003&003A
003C
003E

C2
AO
A2
6B
8A
DF

P 003F AF
P 00110

36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86

ld
ld
DO
inc
LDE
call
IF NC
- EXIT

R4, RO
R5, Rl

I RR4

= token

.'l...tarting- addr I

R2
line. length counter I
R3,@RRO Iget next input by tel
check
Ilook for-delimiter!
THEN
Ifound token endl

FI

incw
00

RRO

Ipoint to next by tel

ret
END

scan

check
PROCEDURE
!*** •• ************************* ••• ********************
compare current character with
purpose =
delimiter table until table
end or match found
input

DELIM = start address of table
COUNT = length of that table
R3 = byte to be scrutinized

output

Carry flag = 1 => input byte
is not a delimiter (no match found)
Carry flag = 0 => input byte
is a delimiter (match found)
R6 , R7 , R8 , R9 destroyed

********************************************·*·******1
ENTRY
ld
R6,IIHI DELIMld
R7,IILO DELIM
IRR6 points to
delimiter listl
ld
R8,IICOUNT
IR8 = length of listl
here:
LDC
R9,@RR6
Iget table entryl
RR6
incw
Ipoint to next entryl
cp
R9, R3
IR3 = delimiter?1
jr
eq,bye
Iyes. carry = 01
djnz
R8,here
Inext entryl
scf
Itable done. R3
not a delimiter I
bye':
I'et
END
check
END
SCAN

o ERRORS
ASSEMBLY COMPLETE
27 instructions
58 bytes
Execution time is a function of the number of Jeading delimiters
before token stort (x) and the number of characters in the
token (y): 123 p:; overhead + 59x p:; + l02y p:;
(average) per /ok,m

3.3 LDCI. A common function performed in is
applications is the initialization of the register
space. The most obvious approach to this function is the coding of a sequence of "load
- register with immediate value" instructions
(each occupying three program bytes for a

register or two program bytes for a working
register). This approach is also the most efficient technique for initializing less than eight
consecutive registers or 14 consecutive working registers. For a larger register block, the

207

3. Accessing
Program and
External Data
,Memory
(Continued)

LDCI instruction provides an economical
means of initializing consecutive register~ from
an initialization table in program memory. The
following code excerpt illustrates this tech- '
nique of initializing control registers %F2
through %FF from a 14-byte array (INIT_tab)
in program memory:
SRP
LD
LD
LD
LD

#%00
IRP not %FO!
R6,#HI INIT_tab
R7,#LO INIT_tab
R8,#%F2
!lst reg to be initialized I
R9,#14
llength of register block!

loop:
LDCI @R8,@RR6
!load a register from the
init table!
DJNZ R9,100p
!continue till done!
7 instructions
14 bytes
7.5 itS overhead "
7.5 Its per register initialized

SECTION

4

Bit Manipulations
Support of the test and modification of an
individual bit or group of bits is required by
most software applications suited to the Z8
microcomputer. Initializing\ and modifying the
Z8 control registers, polling interrupt requests,
manipulating port bits for control of or communication with attached devices, and manipulation of software flags for internal control purposes are all examples of the heavy use of bit
manipulation functions. These examples illustrate the need for such functions in all areas ofthe Z8 register space. These functions are supported in the Z8 primarily by six instructions:
• Test under liJask (TM)
• Test Complement under Mask (TCM)
• AND
• OR
• XOR
• Complement (COM)
These instructions may access any Z8 register,
regardless of its inherent type (control, 1/0, or
general purpose), with the exception of the six
write-only control registers (PREO, PREI,
palM, P2M, P3M, IPR) mentioned earlier in
Section 2.1. Table 1 summarizes- the function
performed on the destination byte by each of
the above instructions. All of these instructions, with the exception of COM, require a
mask operand. The "selected" bits referenced
in Table 1 are those bits in the destination
operand for which the corresponding mask bit
is a logic I.

208

3.4 LDEI. The LDEI instruction is useful for
moving blocks of data between external and
register memory since auto-increment is pertormed on'both indirect registers designated
by the instruction. The following code excerpt
illustrates a register buffer being saved at
address %40 through %60 into external
memory at address SAVE:
LD
LD
LD
LD

RlO,#HI SAVE
!external memory!
Rll,#LO SAVE
!address!
R8,#%40
Istarting register I
R9,#%21
lnumber of registers to save in
external data memory I

loop:
LDEI @RRlO,@R8
lini t a register I
DJNZ R9,loop
luntil done!
6 instructions
12 bytes
6 Its overhead
7.5 ItS per register saved
Opcode

Use

TM

To test selected bits for loglc 0

TCM

To test selected bits for logic I

AND

To reset all but selected bits to logic 0

OR

To set selected bits to logic I

XOR

To complement selected bits

COM

To complement all bits

Table I. Bit Manipulation Instruction Usage

The instructions AND, OR, XOR, and COM
have functions common to today's microprocessors and therefore are not described in
depth here. However, examples of the use of
these instructions are laced throughout the
remainder of this document, thus giving an
integrated view of their uses in common functions. Since they are unique to the 28, the
functions of Test under Mask and Test Complement under Mask, are discussed in more detail
next.
4.1 Test under Mask (TM). The Test under
Mask instruction is used to test selected bits for
10gicO. The logical operation performed is
destination AND source
Neither source nor destination operand is
modified; the FLAGS control register is the
only register affected by this'instruction. The
zero flag (2) is set if all selected bits are logic
0; it is reset otherwise. Thus, if the selected
destination bits are either all logic 1 or a combination of Is and as, the zero flag would be
cleared by this instruction. The sign flag (S) is
either set or reset to reflect the result of the

.4. Bit
Manipulations
(Continued)

AND operation; the overflow flag (V) is always
reset. All other flags are unaffected. Table 2
illustrates the flag settings which result from
the TM instruction on a variety of source and
destination operand combinations.. Note that a
given TM instruction will n~ver result in both
the Z and S flags being set.

4.2 Test Complement under Mask. The Test
Complement under Mask instruction is used to
test selected bits for logic 1. The logical operation performed is
(NOT destination) AND source.

SECTlOII

5

Flags

Sourc:e

Destination

As in Test under Mask, the FLAGS control
register is the only register affected by this
operation. The zero flag (Z) is set if all selected
destination bits are 1; it is reset otherwise. The
sign flag (S) is set or reset to reflect the result
of the AND operation; the overflow flag (V) is
always reset. Table 3 illustrates the flag settings which result from the TeM instruction on
a variety of source and destination operand
combinations. As with the TM instruction, a
given TCM instruction will never result in both
the Z and S flags being set.
Destination

Flags

Source

(binary)

(binary)

Z

S

V

(binary)

(binary)

Z

S

l000lloo

OllloooO

1

0

0

loo01l00

01 1l0oo0

0

0

0

01l11l00

011l0oo0

0

O' 0

Oil Il 100

Oil 10000

0

0

loooll00

11l100oo

0

0

lOooll00

1l1l0oo0

0

0

0

III Il 100

11l1ooo0

0

1

0

1111 1100

111looo0

1

0

0

00011000

10100001

1

0

0

00011000

.10100001

0

0

01000000

10100001

0

0

01000000

10100001

0

0

V

Table 2. Effects of the TN Instruction

Table 3. Effects of the TeM Instruction

Stack Operations
The Z8 stack resides within an area of data
memory (internal or external). The current
address in the stack is contained in the stack
pointer, which decrements as bytes are pushed
onto the stack, and increments as bytes are
popped from it. The stack pointer occupies two
control register bytes (O/OFE and O/OFF) in the
Z8 register space and may be manipulated like
any other register. The stack is usefuf for
subroutine calls, interrupt service-routines,
and parameter passing and saving. Figure 2
illustrates the downward growth of a stack as
bytes are pushed onto it.
5.1 Internal vs. External Stack. The location
of the stack in data memory may be selected to
be either internal register memory or external
data memory. Bit 2 of control register POIM
(O/OF8) controls this selection. Register pair
SPH (O/OFEJ. SPL (O/OFF) serves as the stack
pointer for an external stack. Register SPL is
the stack pointer for an internal stack. In the

latter configuration, SPH is available for use as
a data register. The following illustrates a code,
sequence that initializes external stack operations:
LD P01M,#%(2)OOOOOOOO
!bit 2: select external stack!
LD SPH,#HI STACK
LD SPL,#LO STACK
5.2 CALL. A subroutine call causes the current Program Counter (the address of the byte
following the CALL instruction) to be pushed
onto the. stack. The Program Counter is loaded
with the address specified by the CALL
instruction. This address may be a direct
address or an indirect register pair reference.
For example,

xs._§ §

x-1

SP_

x-.

.,

R1

x-a

PC LOW

sP_ PCHIGH

x-4

INITiAL
STATE

FOLLOWING
PUSH R1

LABEL 1: CALL 0/04F98
!direct addressing: PC is
loaded with the hex value
4F98;
address LABEL 1 + 3 is pushed
onto the stack!
LABEL 2: CALL @RR4
!indirect addressing: PC is
loaded with the contents of
working register pair R4, R5;
address LABEL 2 + 2 is pushed
onto the stack!
.

FOLLOWING.
CALL

Figure 2. Growth of a Stack

209

5. Stack
Operations
(Continued)

LABEL 3: CALL @%7E
!indirect addressing: PC is
loaded with the contents of
register pair %7E, %7F;
address LABEL 3 + 2 is pushed
onto the stack!

5.3 RET. The return (RET) instruction causes
the top two bytes to be popped from the stack
and loaded into the Program Counter. Typically, this is the last instruction of a subroutine
and thus restores the PC to the address fallowing the CALL to that subroutine.

5.4 Interrupt Machine Cycle. During an interrupt machine cycle, the PC followed by the
status' flags is pushed onto the stack. (A more
detailed discussion of interrupt processing is
provided in Section 6.)
5.5IRET. The interrupt return (IRET) instruc-,
tion causes the top byte to be popped from the
stack and loaded into the status flag register,
FLAGS (%FC); the next two bytes are then
popped and loaded into the Program Counter.
In this way, status is restored and program '
execution cpntinues where it had left off when
the interrupt was recognized.
5.6 PUSH and POP. The PUSH and POP
instructions allow the transfer of bytes between'

SECTION

6

210

the stack and register memory, thus providing
program access to the stack for saving and
restoring needed values and passing
parameters to subroutines.
Execution of a PUSH instruction causes the
stack pointer to be decremented by I; the
operand byte is then loaded into the location
pointed to by the decremented stack pointer.
ExsGUtion of a POP instruction causes the byte
addressed by the stack pointer to be loaded
into the operand byte; the stack pOinter is then
incremented by 1. In both cases, the operand
byte is designated by either a direct register
address or an indirect 'register reference. For
example:
PUSH RI
!direct address: push working
register 1 onto the stack!
!direct address: pop the top
POP 5
stack byte into register 5!
PUSH @R4 !indirect address: pop the iop
stack byte into the byte
pointed to by working register 4!
PUSH @I7 !indirect address: push onto'
the stack the byte pointed to
by register I7!

Interrupts
The Z8 recognizes six different interrupts
from four internal and four external sources,
including internal timer/counters, seriaI'I/O,
and four Port 3 lines. Interrupts may be indiVidually or globally enabled/disabled via Interrupt Mask Register IMR (%FB) and may be
prioritized for simultaneous interrupt resolution
via Interrupt Priority Register IPR (%F9).
When enabled, interrupt request processing
automatically vectors to the designated service
routine. When disabled, an interrupt request
may be polled to determine when processing is
needed.

instruction. Interrupts that occur while the 28
is in this initial state will not be recognized,
since the corresponding IRQ bit, cannot be set.
The EI instruction is specially decoded by the
28 to enable the IRQ; simply setting bit 7 of
IMR is therefore not sufficient to enable interrupt processing following RESET, However,
subsequent to this initial EI instruction, interrupts may be globally enabled either by the
instruction

6.1 Interrupt Initialization. Before the 28 can
recognize interrupts follOWing RESET, some
initialization tasks must be performed. The initialization routine should configure the 28
interrupt requests to be enabled/disabled, as
required by the target application and
assigned a priority (via IPR) for simultaneous
enabled-interrupt resolution. An interrupt
request is enabled if the corresponding bit in
the IMR is set (= 1) and interrupts are
,
globally enabled (bit 7 of IMR = 1). An interrupt request is disabled if th~ corresponding
bit in the IMR is reset (= 0) or interrupts are
globally disabled (bit 7 of IMR = 0).
A RESET of the 28 causes the contents of the
Interrupt Request Register IRQ (%FA) to be
held to'zero until the execution of an EI

OR
IMR,#%80
To globally disable interrupts, execute the
instruction
DI
!disable interrupts!

!enable interrupts!
EI
or by a register manipulation, instruction
such as

This will cause bit 7 of IMR to be reset.
Interrupts must be globally disabled prior to
any modification of the IMR, IPR or enabled
bits of the IRQ (those corresponding to
enabled interrupt requests). unless it can be
guaranteed that an enabled interrupt will not
occur during the' processing of such instructions. Since interrupts represent the occurrence of events asynchronous to program executiop, it is highly unlikely that such a
guarantee can be made reliably.

6. Interrupts
(Continued)

6.2 Vectored Interrupt Processing. Enabled
interrupt requests are processed in an
automatic vectored mode in which the interrupt service routine address is retrieved from
within the first 12 bytes of program memory.
When an enabled interrupt request is
recognized by the 28, the Program Counter is
pushed onto the stack (low order 8 bits first,
then high-order 8 bits) followed by the FLAGS
register (#%FC). The corresponding interrupt
request bit is reset in IRQ, interrupts are
globally disabled (bit 7 of IMR is reset), and
an indirect jump is taken on the word in location 2x, 2x + I (x = interrupt request number,
o:=; x:=; 5). For e~ample, if the bytes at
addresses %0004 and %0005 contain %05 and
%78 respectively, the interrupt machine cycle
for IRQ2 will cause program execution to continue at address %0578.
When interrupts are sampled, more than one
interrupt may be pending. The Interrupt Priority Register (IPR) controls the selection of the
pending interrupt with highest priority. While
this interrupt is being serviced, a higherpriority interrupt may occur. Such interrupts

may be allowed service within the current
interrupt service routine (nested) or may be
held until the current service routine is complete (non-nested).
To allow nested interrupt processing, interrupts must be selectively enabled upon entry
to an interrupt service routine. Typically, only
higher-priority interrupts would be allowed to
nest within the current interrupt service. To do
this, an interrupt routine must "know" which
interrupts have a higher priority than the current interrupt request. Selection of such nesting priorities is usually a reflection of the
ptfori ties established in the I.nterru pt Priority
Register (IPR). Given this data, the first
instructions executed in the "service routine
should be to save the current Interrupt Mask
Register, mask off all interrupts of lower and
equal priority, and globally enable interrupts
(EI). For example, assume that service of inter·
rupt requests 4 and 5 are nested within the service of interrupt request 3. The follOWing illustrates the code required to enable IRQ4
and IRQ5:

CONSTANT
%(2) 00110000
GLOBAL
IRQ3_seryice
PROCEDURE
ENTRY
!service routine for IRQ3!
PUSH IMR
!save Interrupt Mask Register!
!interrupts were globally disabled during the interrupt
machine cycle - no DI is needed prior to modification of IMR!
!disable all but IRQ4 & 5!
AND IMR,#INT_MASL3
EI
! ... !
!service interrupt!
!interrupts are globally enabled now - must disable them prior to
modification of IMR!

DI
POP IMR
IRET
END IRQ3_service

!restore entry IMR!

Note that IRQ4 and IRQ5 are enabled by the
above sequence only if their respective IMR
bits = 1 on entry toJRQ3_service.
The service routine for an interrupt whose
processing is to be completed without interruption should not allow interrupts to be nested
within it. Therefore, it need not modify the
IMR, since interrupts are disabled automatically during the interrupt machine cycle.
The service routine for an enabled interrupt
is typically concluded with an IRET instruction, which restores the FLAGS register and
Program Counter from the top of the stack and
globally enables interrupts. To return from an
interrupt service routine without re-enabling

interrupts, the following code sequence could
be used:
POP FLAGS
!FLAGS ..- @SP!
RET
!PC ..- @SP!
This accomplishes all the functions of IRET,
except that IMR is not gffected.
6.3 Polled Interrupt Processing Disabled
interrupt reQuests may be processed in a
polled mode, in which the corresponding bits
of the Interrupt Request Register (IRQ) are
examined by the software: When an interrupt
request bit is found to be a logic 1, the interrupt should be processed by the appropriate

211

6. Interrupts
(Continued)

service routine. During such processing, the
interrupt request bit in the IRQ must be
cleared by the software in order for subsequent
interrupts on that line to be distinguished from
the current one. If more than one interrupt
request is to be processed in a polled mod~,
polling should occur in the order of estab-

lished priorities. For example, assume that
IRQO, IRQI, and IRQ4 a~e to be polled and
that established priorities are, from high to
low, IRQ4, IRQO, IRQI. An instruction
sequence like the following should be used to
poll and service the interrupts:

1.
!poll interrupt inputs here!
TCM
IRQ, #%(2)00010000
JR
NZ, TESTO
CALL
IRQ4_service
TESTO:
TCM
IRQ, #%(2)00000001
JR
NZ, TEST!
CALL
IRQO_service
TEST!:
TCM
IRQ, #%(2)00000010
JR
NZ, DONE
CALL
IRQ I_service
DONE:
!. .. !
IRQ4_service
!. .. !
AND
!. .. !
RET
END IRQ4_service

PROCEDURE

IRQO_service
I. .. !
AND

PROCEDURE

!IRQ4 need service?!
!no!
!yes!
!IRQO need service?!
!no!
!yes!
!IRQl need service?!
!no!
!yes!

ENTRY
!c1ear IRQ4!

IRQ, #%(2)11101111

ENTRY

IRQ, #%(2)1l1l1ll0

!clear IRQO!

! ... !

RET
END IRQO_service
IRQ I_service
I. .. !
AND
I. .. !
RET
END IRQ I_service
1. .. !

SECTION

7

PROCEDURE
IRQ, #%(2)1l11ll0l

Timer/Counter Functions
The Z8 provides two 8-bit timer/counters, To
and TI , which are adaptable to a variety of
application needs and thus allow the software
(and external hardware) to be relieved of the
bulk of such tasks. Included in the set of such
uses are:
• Interval delay timer
• Maintenance of a time-of-day clock
• Watch-dog timer
• External event counting
• Variable pulse train' output
• Duration measurement of external event
• A~matic delay following external event
detection

212

ENTRY
!clear IRQ 1!

Each timer/counter is driven by its own 6-bit
prescaler, which is in turn driven by the internal Z8 clock divided by four. For TJ, the internal clock may be gated or triggered by an
external event or may be replaced by an external clock input. Each timet/counter may
operate in either single-pass or continuous
mode where, at end-of-count, either counting
stops or the counter reloads and continues
counting. The counter and pres caler registers
may be altered indiVidually while the timer/
counter is running; {he software controls
whether the new values are loaded immediately or when end-of-count (EOC) is reached.
Although the timer/counter prescaler
registers (PREO and PREI) are write-only,
there is a technique by which the timer/

7. Timer/
Counter
Functions
(Continued)

counters may ,simulate a readable prescaler.
This capability is a requirement for high
resolution measurement of an event's duration.
The basic approach requires that one timer/
counter be initialized with the desired counter
and prescaler values. The second timer/
counter is initialized with a counter equal to
the prescaler of the first timer/counter and a
prescaler of 1. The second timer/counter must
be programmed for continuous mode. With
both timer/counters driven by the internal
clock and started and stopped simultaneously,
they will run synchronous to one another; thus,
the value read from the second counter will
always be eqUivalent to the prescaler of
the first.
,
,
7.1 Time/Count Interval Calculation To
determine the time interval 0) until EOC, the
equation
i=txpxv
characterizes the relation between the
prescaler (p). counter (v), and clock input
period (t); t is given by
1/(XTAlJ8)
where XTAL is the Z8 input clock frequency;
p is in the ,ange 1 - 64; v is in the range
1 - 256. When programming the prescaler and
counter registers, the maximum load value is
truncated to six and eight bits, respectively,
and is therefore programmed as zero. For an
input clock frequency of 8 MHz, the prescaler
and counter register values may be programmed to time an interval in the range
l/Ls xlxlSi'SI/Lsx64 x 256
, 1 /LS Sis 16.384 ms
To determine the count (c) until EOC for TI
with external clock input, the equation

c

=p

x v

characterizes the relation between the TI
prescaler (p) and the TI counter (v). The
divide-by-8 on the input frequency is bypassed
in this mode. The count range is
1 x I s c s 64 x 256
1 s c s 16,384
7.2 TOUT Modes. Port 3, bit 6 (P3s) may be
configured as an output (Tour) which is
dynamically controlled by one of the follOWing:
• To
• TI
.. Internal clock
When driven by To or TI, Tour is reset to a
logic J when the corresonding load bit is set in
timer control register TMR (%Fl) and toggles
on EOC from the corresponding counter.

When Tour is driven by the internal clock,
that clock is directly output on P3s.
While programmed as Tour, P3s is disabled
from being modified by a wdte to port register
%03; however, its current output may be
examined by the Z8 software by a read to port
register %03.
7.3 TIN Modes. Port 3, bit .Wf31) may be conis used in configured as an input (TIN)
junction with TI in one of four modes:

w9

..

• External clock input
• Gate input for internal clOck
• Nonretriggerrable input for internal clock
• Retriggerable input for internal clqck
For the latter two modes, it should be noted
that the existence of a synchronizing circuit
within the Z8 causes a delay of two te three
internal clock periods following an external
trigger before clocking of the counter actually
begins.
Each High-to-Low transition on TIN will
generate interrupt request IRQ2, regardless of
the selected TIN mode or the enabled/disabled
state of h IRQ~ J7lust therefore be masked or
enabled accordmg to the needs of the
application ..
The "external clock input" TIN mode supports the counting of external events, where an
event is seen as a High-to-Low transition on
TIN. Interrupt request IRQ5 is generated on
the nth occurrence (single-pass mode) or on
every nth occurrence (continuous mode) of
that event.
The "gate input for internal clock" TIN mode
provides for duration measurement of an external event. In this mode, the TI prescaler is
driven by the Z8 internal clock, gated by a
High level on TIN. In other words, Tl will
count while TIN is High and stop counting
while TIN is Low. Interrupt request IRQ2 is
generated on the High-to-Low transition on
TIN. Interrupt request IRQ5 is generated on TI
EOC. This mode may be used when the width
of a High-going pulse needs to be measured.
In this mode, IRQ2 is typically the interrupt
request of most importance, since it signals the
end of the pulse being measured. If IRQ5' is
generated prior to IRQ2'in this mode, the
pulse width on TIN is too large for TI to
measure in a single pass .
The "nonretriggerable input" TIN 'mode provides for automatic delay timing following an
external event. In this mode, TI is loaded and
clocked by the Z8 internal clock following th~
first High-to-Lc;>w transition on TIN ,after TI is
enabled. TIN tra,nsltions that occur after this
point do not affect Tl. In singl~-pass mode, the

~

213

7. Timer/
Counter
'Functions
(Continued)

enable bit is reset on EOC; further TIN transitio~s will not cause Tl to load and begin counting until the software sets the enable bit again.
In continuous.mode, EOC does not modify the
enable bit, but the counter is reloaded and
counting continues immediately; IRQ5 is
generated every EOC until software resets the
enable bit. This TIN mode may be \lsed, for
example, to time the line feed delay following
end of line detection on a printer or to delay
data sampling for some length of time followinga sample strobe.
The "retriggerable input" TIN mode will load
and clock Tl with the 28 internal clock on
every occurrence of a High-to-Low transition
on TIN. Tl will time-out and generate interrupt
request IRQ5 when the programmed time
interval (determined by Tl prescaler and load
register values) has elapsed since the last
High-to-Low transition on TIN. In single-pass
mode, the enable bit is reset on EOC; further
TIN transitions will not cause Tl to load and
begin counting until the software sets the
enable bit again. In continuous mode, EOC
does not modify the enable bit, but the counter
is reloaded and counting continues immediZ8ASM
LOC

2.0
OBJ CODE

ately; IRQ5 is generated at every EOC until
the software resets the E\nable bit. This TIN
mode may provide such functions as watch-dog
timer (e.g., interrupt if conveyor belt stopped
qr clock pulse missed), or keyboard time-out
(e.g., interrupt if no input in x ms).
7.4 Examples. Several possible uses of the
timer/counters are given in the following four
examples.
7.4.1 Time of Day Clock. The following
module illustrates the use of T j for
maintenance of a time 01 day clock, which is
kept in binary format in terms of hours,
minutes, seconds, and hundredths of a second.
It is desired that the clock be updated once
every hundredth of a second; therefore, Tl is
programmed in continuous mode to interrupt
100 times a second. Although Tj is used for
.this example, To is equally suited for the task.
The procedure for initializing the timer
(TOD_INIT), the interrupt service routine
(TOD) which updates the clock, and the interrupt vector for Tj end-of-courtt (IRQ_5) are
illustrated below. XTAL = 7.3728 MHz is
assumed.

STMT SOURCE STATEMENT
1 TIMER 1 MODULE
2 CONSTANT

3

4

5
6
7

8
9

10

P 0000 OOOF'

P 0000 E6

F3

93

P 0003 E6

F2

00

46
8F
46
9F
AF

F1

DC

FB

20

P OOOF 70

FD

P
P
P
P
P
P

EF
13
EF

64

EE
OB

3C

P
P
P
P
P

0006
0009
DOD A
0000
OOOE
P OOOF
P OOOF

0011
0013
0014
001'7
0019
001B
rP 001C
001F

214

31
FE
A6

EB

BO
EE
A6
EB

10

..--

.

[TOOl
12
13$REL
14 TOD_INIT
'" PROCEDURE
15 ENTRY
LD,
16
PRE1,U%(2)10010011
17
Ibit 2-7: prescaler = 36;
18
bit 1: internal clock;
bit 0: continuous model
19
20
LD
T1,110
1(256) time-out =
21
1/100 secondl
22
OR
TMR,UIOC !load, enable T11
01
23
24
IMR,II%20 tenable T1 interruptI
OR
25
EI
RET
26
TOO_IN IT
27 END
28
29 TOO
PROCEDURE
30 ENTRY
PUSH
RP
31
32 !Working register file %10 to %1F contains
33 the time of day clockl
SRP
11%10
34
INC
HUND
!1 more .01 sec!
35
CP
HUND,U100
Ifull second yet?!
36
JR
NE,TOD_EXIT
!jump i f no!
37
CLR
HUND
38
INC
SECOND
!1 more secondl
39
Ifull minute yet?!
40
CP
SECOND,U60
41
JR
NE,TOD_EXIT
!jump i f no!
11

P OOOC

R12
HOUR
'.MINUTE . R13
SECOND
R14
HUND
R15
$SECTION PROGRAM
GLOBAL
IIR05 interrupt vector!
$ABS
10
[1 WORD]
IRO_5
ARRAY

7. Timer/
Counter
Functions
(Continued)

P
P
P
P
P
P

0021
0023
0024
0027
0029
002B

BO
DE
A6
EB
BO
CE

P 002C 50
P 002E BF
P 0021'

EE
ED
03
ED

3C

FD

42
CLR
43
INC
44
CP
45
JR
46
CLR
INC
47
48 TOD_ EXIT:
POP
49
50
IRET
TOO
51 END
TIMER1
52 END

SECOND
MINUTE
MINUTE ,1160
NE,TOD_EXIT
MINUTE
HOUR
RP

1 more minute!

full hour yet? I
jump if no I

Irestore entry RPI

o ERRORS
ASSEMBLY COMPLETE
TOD_INIT:
7 instructions
15 bytes
16 p.s

TOD:
17 instruction

32 bytes
19.5 p.s (average) including interrupt response time

7.4.2 Variable Frequency, Variable Pulse
Width Output. The following module
illustrates one possible use of TOUT. Assume it
is necessary to generate a pulse train with a
10% duty cycle, where the output is repetitively high for 1.6 ms and then low for 14.4 ms. To
do this, TOUT is controlled by end-of-count
from T1. although To could alternately be
chosen. This example makes use of the Z8
feature that allows a timer's counter register to
be modified without disturbing the count in
progress. In continuous mode, the newva1ue is
loaded when TI reaches EOC. TI is first
loaded and enabled with values to generate
the short interval. The counter register is then
immediately modified with the value to
generate the long interval; this value is loaded
into the counter automatically on TI EOC. The
prescaler selected value must be the same for
both long and short intervals. Note that the
z8ASM
LOC

2.0
OBJ CODE

initial loading of the T I counter register is
followed by setting the TI load bit of timer control register TMR (%Fl); this action causes
. TOUT to be reset, to a logic I output. Each
subsequent modification of the T I counter
register does not affect the current TOUT level,
since the T I load bit is NOT altered by the
software. The new value is loaded on EOC,
and TOUT will toggle at that time. The TI interrupt service routine should simply modify the
TI counter register with the new value, alternating between the long and short interval
values.
In the example which follows, bit 0 of
register %04 is used as a software flag to indicate which value was loaded last. This module
illustrates the procedure for TI/ToUT initialization (PULSE_IN]T), the TI interrupt service
routine (PULSE), and the interrupt vector for
TI EOC (IRQ_5). XTAL = 8 MHz is assumed.

STMT SOURCE STATEMENT
1

TIMER2

MODULE

2
$SECTION PROGRAM
3 GLOBAL
4 IIRQ5 interrupt vectorl
$ABS
10
5
6 IRQ_5
ARRAY
[1 WORD]
7

P 0000 0017'
P OOOC
P

oboo

E6

F3

03

P
P
P
P
P

0003
0006
0009
OOOA
0000

E6
E6
8F
46
E6

F7
F2

00
19

FB
F1

20
8c

P 0010 E6

F2

E1

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

$REL
PULSE_INIT
ENTRY
LD

LD
LD
D1
OR
LD

: :::

[PULSE]

PROCEDURE
PRE1,H$(2)00000011
Ibit 2-7: prescaler = 64;
bit 1: internal clock;
bit 0: continuous model
Ibit 5: let P36 be Toutl
P3M,II00
T1,H25
Ifor short interval I

1MR,H$(2)00100000 lenable T1 interrupti
TMR,#%(2)10001100
Ibit 6-7: Tout controlled
by T1;
bit 3: enable T1;
bit 2: load T1 !
!Set long interval counter, to be loaded on T1 EOCI
LD
T1,H225
!Clear alternating flag for PULSE!

215

7. Timer/
Counter
FUDctions
(Continued)

P 0013- BO

04

P 0015 9F
P 0016 AF
P 0017
P 0017
P 0017
P OOlA
P 001D
P'001F

E6 F2
B6 04
6B 03
E6 F2

E1
01
19

P 0022 BF
P 0023

27
28'
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

CLR

$04

'
END

EI
RET
.
PULSE_IN IT

PULSE
ENTRY

PROCEDURE

LD
XOR
JR
LD
PULSE_EXIT:
IRET
END
PULSE
TIMER2
END

1= 0
1

T1,II225
$04,111
Z,PULSE_EXIT
T1,II25

25 next;
225 next

Inew load value 1
Iwhich value next?1
Ishould be 2251
Ishould be 251

o ERRORS
ASSEMBLY CO~PLETE
PULSE_lNIT:
10 instructions
23 bytes
23p$

PULSE:
5 instructions
12 bytes
25 p$ (average) including interrupt response time

7.4.3 Cascaded Timer/Counters. For some
applications it may be necessary to measure a
. greater time interval than a sing'le timer/
counter can measure (16.384 ms). In this case,
TIN and TOUT may be used to cascade To and
XTAL

TJ to lunction as a single unit. TOUT, prog'rammed to toggle on To end-ai-count, should be
wired back to TIN, which is selected as the
external clock input lor TJ. With To programmed lor continuous mode, TOUT (and therefore
TIN) goes through a High-to-Low transition
(causing TI to count) on every other To EOC.
Interrupt request IRQ5 is generated when the
programmed time interval has elapsed. Interrupt requests IRQ2 (generated on every TIN
High-to-Low transition) and IRQ4 (generated
on To EOC) are of no importance in this
application and are therefore disabled.
To determine the time interval (i) until EOC,
the equation
i =t x pO x vO x (2 x p I x v I - I)

TO INTERRUPT LOOiIC (IRQ4)

characterizes the relation between the To'
prescaler (pO) and counter (vO), the TI
prescaler (pI) and counter (vI), and the clock
input period (t); t is defined in Section 7.1.
Assuming XTAL = 8 MHz, the measurable
time interval range is
I p.s x I x I x (2 x 1-1) os; i os;
. I p.s x 64 x 256 x (2 x 64 x 256 - I)
I p.s os; i

TO INTERRUPT LOGIC (IRQ6)

Figure 3. Casc:adec:l Timer/Counte..

216

OS;

536.854528 s

Figure 3 illustrates the interconnection
between To and TI. The following module
illustrates the procedure required to initialize
the time~s for a 1.998 second delay interval:

1. Timer/
Counter
Functions
(Continued)

Z8ASM
LOC

2.0
OBJ CODE'

P 0000
P 0000 E6

F3

28

P 0003 E6
P 0006 E6
P 0009 E6

F7
F2
F5

00
64
29

P OOOC E6
P OOOF 8F
P 0010 56

F4

64

FB

2B

P 0013 46
P 0016 9F
P 0017 E6

FB

20

Fl

IIF

P 001A AF
P 001B

STMT SOURCE STATEMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
211
25
26
27
28
29
30
31

TIMER3 MODULE
GLOBAL
TIMER_16
ENTRY
LD

LD
LD
LD
LD
DI
AND
OR
EI
LD

END
END

RET
TIMER_16
TIMER3

PROCEDURE
PRE1,#$(2)00101000
Ibit 2-7: prescaler = 10;
bit 1: external clock;
bit 0: single-pass model
P3M,II00
Ibit 5: let P36 be Toutl
Tl,#100
ITI counter registerl

PREO,#~(2)00101001

TO,#100

Ibit 2-7: prescaler = 10;
bit 0: continuous model
!TO counter register!

IMR,n%(2)00101011
IMR,f%(2)00100000

Idisable IRQ2 (Tin);
and IRQII (TO) I
!enable IRQ5 (Tl)I

TMR,nS(2)01001111
Ibit 6-7: Tout controlled
by TO;
bit 4-5: Tin mode is ext.
clock input;
bit 3 : enable Tl;
bit 2: load Tl;
bit 1: enable TO;
bit 0: load TO I

o ERRORS
ASSEMBLY COMPLETE
11 instructions
27 bytes
26.S""

7.4.4 Clock Monitor. T1 and TIN may be used
to monitor a clock line (in a diskette drive, for
example) and generate an interrupt request
when a clock pulse is missed. To accomplish
this, the clock line to be monitored is wired to'
P31 (TIN)' TIN should be programmed as a
retriggerable input to Tl, such that each falling edge on TIN will cause Tl to reload and
continue counting. If Tl is programmed to
time-out after an interval of one-and-a-half
times the clock period being monitored, Tl
will time-out and generate interrupt request
IRQ5 only if a clock pulse is missed.
Z8ASM
LOC

,p
;'-

2.0
OBJ CODE

The follOWing module illustrates the procedure for initializing Tl and TIN
(MONltOR--1NIT) to monitor a clock with a
period of 2/Ls. XTAL = 8 MHz is assumed.
Note that this example selects single-pass
rather than continuous mode for TI. This is to
prevent a continuous stream of IRQ5 interrupt
requests in the event that the monitored clock
fails completely. Rather, the interrupt service
routine (CLK_ERR) is left with the choice of
whether or not to re-enable the monitoring.
Also shown is the TI interrupt vector (IRQ_5).

STMT SOURCE STATEMENT

0000 0015'

P OOOC
P 0000 E6

F3

04

P 0003 E6
P 0006 £6

F7
F2

00
03

1
2
3
II
5
6'
7
8
9
10
11
12
13
14
15
16
17

TIMER4

MODULE
$SECTION PROGRAM

GLOBAL
IIRQ5 interrupt vectorl
$ABS
10
IRQ_5
ARRAY
[1 WORDl
$REL
MONITOR_INIT
ENTRY
..LD

LD
LD

.-

[CLK_ERRl

PROCEDURE
PRE1,#$(2)00000100
Ibit 2-7: prescaler = 1;
bit 1: external clock;
bit 0: single-pass model
P3M,II00
Ibit 5: let P36 be Toutl
T1,II3
ITl load register,
= 1.5 * 2 usec I

217

7. Timer/
Counter
Functions
(Continued)

P
P
P
P

0009
OOOA
OOOD
0010

8F
56
46
9F

FB
FB

P 0011 E6

Fl

3B
20
38

P 0014 AF
P 0015
P 0015

0015 46

Fl

08

P 0018 BF
P 0019

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

DI
AND
OR

IMR,U%(2)00111011
IMR,U%(2)00100000

!disable IRQ2 (Tin) !
I enable IRQ5 (Tl) !

EI

LD

END

TMR,UI(2)0011,1000
! bit 4-5: Tin mode is
retrig. input;
bit 3: enable Tl !

RET
MONITOR_INIT

CbK_ERR PROCEDU RE
ENTRY
!handle the missed clock!

! ••• !

!if clock monitoring shQuld continu~ ••• !
TMR,UI(2)00001000
OR
I bi t 3: enable Tl
IRET
CLK_ERR
END
TIMER4
END

o ERRORS
ASSEMBLY COMPLETE
MONITOR_INIT:
9 instructions

eLK_ERR:
2 + instructiqns

4 + bytes
18.5 + JJ.S including interrupt response time

21 bytes
21.5 pH

SECTION

8

I/O Functions
The 28 provides 32 110 lines mapped into
registers 0-3 of the internal register file. Each
nibble of port 0 is individually programmable
as input, output, or address/data lines
(Al 5 -Al2, All-As). Port 1 is programmable as
a single entity to provide input, output, or
address/data lines (AD7-ADo). The operating
modes for the bits of Ports 0 and I are selected
by control register POIM (%F8). Selection of
I/O lines as address/dati! lines supports access
to external program and data memory; this is
discussed in Section 3. Each bit of Port 2 is
individually programmable as an input or an
Bit

Function

Handshake

P3)
P32
P33
P34
P35
P36

r

Signal
DAV2/RDY2
r:JAVO/RDYO
DAVlIRDYl
RDYIIDAVl
RDYO/DAVO
RDY2/i5A'V2

P3)
30
P32
P3 3

IRQ3
IRQ2
IRQO
IRQl

Counter/
Timer

1P3)
P36

TIN
TOUT

Data Memory
Select
Status Out

1P34
1P30
P37

Interrupt
Request

Serial I/O

DM
Serial In
Serial Out

Table 4. Port 3 Special Functions

218

output bit. Port 2 bits programmed as outputs
may also be programmed (via bit 0 of P3M) to
all have active pull-ups or all be open-drain
(active pull-ups inhibited). In Port 3, four bits
(P30-P33) are fixed as inputs, and four bits
(P34-P37) are fixed as outputs, but their functions are programmable. Special functions provided by Port 3 bits are listed in Table 4. Use
of the Data Memory select output is discussed
in Section 3; uses of TIN and TOUT are dis- cussed in Section 7.

8.1 Asynchronous Receiver/Transmitter
Operation. Full-duplex, serial asynchronous
receiver/transmitter operation is provided by
the 28 via P37 (output) and P30 (input) in conjunction with control register SIO (%FO),
which is actually two registers: receiver buffer
and transmitter' buffer. Counter/Timer To proVides the clock for control of the bit rate.
The 28 always receives and transmits eight
bits between start and stop bits. However, if
parity is enabled, the eighth bit (D7) is
replaced by the odd-parity bit when transmitted and a parity-error flag (= I if error)
when received. Table 5 illustrates the state of
the parity bit/parity error flag during serial
110 with parity enabled.
Although the 28 directly supports either odd
parity or no parity for serial 110 operation,
even parity may also be provided with additional software support. To receive and
transmit with even parity, the 28 should be
configured for serial I/O with odd parity
disabled. The 28 software must calculate parity

8.1/0

Functions

Character Loaded
Into SIO

Transmitted To
Serial Line

Received From

11000011
11000011
01111000
01111000

01000011
01000011
11111000
11111000

01000011
01000111
11111000
01111000

(Continued)

Serial Line

Char~cter
Transferred To SIO

Note·

OlGOOOll

no error

11000111
01111000
11111000

no error

Table 5. Serial 110 With Odd Parity

and modify the eighth bit prior to the load of a
character into SIO and then modify a parity
error flag following the load of a character
from SIO. All other processing required for
serial 110 (e.g. buffer management, error
handling, etc.) is the same as that for odd
parity operations.
To configure the Z8 for Serial I/O, it is
necessary to:
• Enable P30 and P37 for serial I/O and select
parity,
• Set up To for the desired bit rate,
• Configure IRQ3 and IRQ4 for polled or
automatic interrupt mode,
• Load and enable To.
To enable P30 and P37 for serial I/O, bit 6 of
P3M (R247) is set. To enable odd parity, bit 7
of P3M is set; to disable it, the bit is reset. For
example, the instruction
LD

P3M,#%40

will enable serial I/O, but disable parity. The
instruction
LO

P3M,#%CO

will enable serial I/O, and enable odd parity.
In the following discussions, bit rate refers to
all transmitted bits, including start, stop, and
parity (if enabled). The serial bit rate is given
by the equation:
bit rate =

mput clock frequency

(2 x 4 x TO prescaler x TO counter x 16)

The final divide-by-16 is incurred for serial
communications, since in this mode To runs at
16 times the bit rate in order to synchronize
the data stream. To configure the Z8 for a
specific bit rate, appropriate values must first
be selected for To prescaler and To counter by
the above equation; these values are then programmed into registers To (%F4) and PREO
(%F5) respectively. Note that PREO also controls the continuous vs. single-pass mode for
To; continuous mode should be selected for
serial I/O. For example, given an input clock
frequency of 7.3728 MHz and a selected bit
rate of 9600 bits per second, the equation is

error

• Left-most bit

IS

07

satisfied by To counter
2 and prescaler = 3.
The follOWing code sequence will configure the
To counter and To prescaler registers:
LO
LO

To,#2 !To counter = 2!
PREO,#%(2)OOOOIIOI
!bit 2-7: pres caler = 3; bit 0:
continuous mode!

Interrupt request 3 (IRQ3) is generated
whenever a character is transferred into the
receive buffer; interrupt request 4 (IRQ4) is
generated whenever a character is transferred
out of the transmit buffer. Before accepting
such interr'upt requests', the Interrupt Mask,
Request, and Priority Registers (IMR, IRQ, and
IPR) must be programmed to configure the
mode of interrupt response. The section on
Interrupt Processing provides a discussion of
interrupt configurations.
To load and enable To, set bits 0 and I of
the timer mode register (TMR) via an instruction such as
OR

TMR,#%03

This will cause the To prescaler and counter
registers (PREO and To) to be transferred. to the
To prescaler and counter. In addition, To is
enabled to count, and serial I/O operations
will commence.
Characters to be output to the serial line
should be written to serial I/O register SIO
(%FO). IRQ4 will be generated when all bits
have been transferred out.
Characters input from the serial line may be
read from SIO. IRQ3 will be generated when a
full character has been transferred into SIO.
The follOWing module illustrates the receipt
of a character and its immediate echo back to
the serial line. It is assumed that the Z8 has
been configured for serial I/O as described
above, with IRQ3 (receive) enabled to interrupt,
and IRQ4 (transmit) configured to be polled.
The received character is stored in a Circular
buffer in register memory from address %42 to
%5F. Register %41 contains the address of
the next available buffer position and should
have been initialized by some earlier routine
to #%42.

219

8. 1/0
Functions
(Continued)

z8ASM
LOC

2.0
OBJ CODE

STMT SOURCE STATEMENT

P 0006 0000'
P 0000

P 0000 E4

FO

FO

P 0003 F5
P 0006 20
P 0008 A6

FO
41
41

41
60

P OOOB EB
P OOOD E6

03
41

42

P 0010 66
P 0013" EB

FA
FB

10

P 0015 56
P 0018 BF
P 0019

FA

EF

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

SERIAL_IO
MODULE
CONSTANT
next_addr
%41
%42
start
length
._
%1E
$SECTION PROGRAM
GLOBAL
!IRQ3 vector I
$ABS
6
ARRAY [1 WORD) ._ [GET_CHARACTER)
$REL
GET_CHARACTER

o

PROCEDURE

ENTRY

ISerial 1/0 receive interrupt servicel
!Echo received character and wait for
echo completion I
ld
SIO,SIO
lechol
!save it in circular buffer!

@next_addr,SIO !save in bufferl
next_addr
!point to next position I
next_addr,#start+length
!wrap-around yet?!
jr
ne,echo_wait
Ino.!
ld.
next_addr,#start !yes. point to start!
!now, wait for echo completel
echo_wait:
IRQ, 11% 10
!transmitted yet?1
tcm
jr
nz,echo_wait
Inot yet!
ld

inc

cp

END
END

and
IRQ,II%EF
IRET
GET_CHARACTER
SERIAL_IO

Iclear IRQ4!
!return from interrupti

o ERRORS
ASSEMBLY COMPLETE
10 instructions
25 bytes
35.5 p.s + 5.5 p.s for each additional pass through the echo_wait loop,
including interrupt response time

8.2 Automatic Bit Rate Detection. In a typical
system, where serial communication is
required (e.g. system with a terminal), the
desired bit -rate is either user-selectable via a
switch bank or nonvariable and "hard-coded"
in the software. As an alternate method of bitrate detection, it is possible to automatically
determine the bit rate of serial data received
by measuring the length of a start bit. The
advantage of this method is that it places no
requirements on the hardware design for this
function and provides a convenient (automatic)
operator interface.
In the technique described here, the serial
channel of the 28 is initialized to expect a bit
rate of 19,200 bits per second. The number of
bits (n) received through Port pin P30 for each
bit transmitted is expressed by

n = 19,200/b
where b = transmission bit rate. For example,
if the transmission bit rate were 1200 bits per
second, each incoming bit would appear to the
receiving serial line as 19,200/1200 or 16 bits.
The following example is capable of disting-

220

uishing between the bit rates shown in Table 6
and assumes an input clock frequency of
7.3728 MHz, a To prescaler of 3, and serian/O
enabled with parity disabled. This example
requires that a character with its low order
bit = 1 (such as a carriage return) be sent to
the serial channel. The start bit of this
character can be measured by counting the
number of zero bits collected before the low
order 1 bit. The number of zero bits actually
collected into data bits by the serial channel is
less than n (as given in the above equation),
due to the detection of start and stop bits.
Figure 4 illustrates the collection (at 19,200

j

1 > - - - - - 1 BIT TIME AT 1,200 BITS PER SECOND----+j
..

fool

ST .. START BIT

SP '" STOP BIT

Dn

= DATA BIT n

=

EACH INTERVAL SHOWN
1 BIT TIME
AT 19,200 BITS PER SECOND

Figure 4. Collection of a Start Bit Transmitted at
at 19,200 BPS

8. 110

Number of Bits Received
Per Bit Transmitted

Bit Rate

Functions
(Continued)

19200
9600
4800
2400
1200
600
300
150

Number of 0 Bits Collected"
as Data Bits

I

2
4
8
16
32
64
128

TO Counter

dec

binary

dec

binary

0
I
3
7
13
25
49
97

00000000
00000001
00000011
00000111
00001101
00011001
00110001
01100001

I

00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000

2
4
8

16
32
64

128

Table 6. Inputs to the Automatic Bit Rate Detection "Algorithm

bits per second) of a zero bit transmitted to the
Z8 at 1,200 bits per second. Notice that only 13
of the 16 zero bits received are collected as
data bits.
Once the number of zero bits in the start bit
has been collected and counted, it remains to
translate this count into the appropriate To
counter value and program that value into To
(%F4). The patterns shown in the two binary
columns of Table 6 are utilized in the
algorithm for this translation.
As a final step, if incoming data is to commence immediately, it is advisable to wait until
the remainder of the current "elongated"
Z8ASM
LOC

2.0
OBJ CODE

0000
0001
0004
0007
OOOA
0000

8F
56
56
E6
E6
E6

FB
FA
F7
F4
F5

77
F7
40
01
00

P 0010 BO
P 0012 E6

EO
F1

03

P
P
P
P
.P
P
P
P
P
P
P
P

0015 76
0018 6B
001 A 18
001C 56
001 F 1 E
0020 1 A.
0022 06
0025 8B
0027
0029
002B
002C

EO
7B
OE
8B

FA
FB
Fa
FA
05
EO
EE
El
03
F9

P 002E lC
P 0030 2C
P 0032 90

07
80
EO

P 0034 90

EO

where nand b are as defined above. The
following module illustrates a sample program
for automatic bit rate detection.

STMT SOURCE STATEMENT

P 0000
P
P
P
P
P
P

character has been received, thus "flushing"
the serial line. This can be accomplished
either via a software loop, or by programming
TI to generate an interrupt request after
the appropriate amount of time has elapsed.
Since a character is composed of eight bits
plus a minimum of one stop bit following the
start bit, the length of time to delay may be
expressed as
(9 x n)/b

08
F7
08

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

bit_rate
MODULE
EXTERNAL
DELAY
PROCEDURE
GLOBAL
main
PROCEDURE
ENTRY
di
Idisable interrupts I
IMR,II%77
and
!IRQ3 polled model
and
IRQ,II%F7
I clear IRQ31
Id
P3M,II%40
lenable serial 1/01
Id
TO,111
Id
PREO, II( 3 SHL 2)+1 Ibit rate = 19,200;
continuous count mode!
clr
RO
linit. zero byte counter!
Id
TMR,113
Iload and enable TOI
Icollect input bytes by counting the number of null
characters received. Stop when non-zero byte received I
collect:
TM
IRQ, 11%08
~character received?!
jr
z,collect Inot yet!
Id
R1,SIO
!get the character!
and
IRQ,II%F7
!clear interrupt request!
R1
inc
Icompare to a ••• 1
. R1 , bi tloop I ••• (in 3 bytes of code)!
djnz
RO , 118
add
lupdate count of a bitsl
jr
collect
bitloop:
ladd in zero bits from low
end of 1st non-zero ~yte!
RR
R1
jr
c,count_done
inc
RO
jr
bitloop
IRO has number of zero bits collected I
Itranslate RO to the appropriate TO counter value!
count_done:
IRa has count of zero bits I
Id
R1,117
Id
R2,1I%80
I R2 will have TO counter value I
RL
RO
loop:

RL

RO

221

8. 110
Functions
(Continued)

P 0036 7B
P 0038 EO
P 003A 1A

04
E2
F8

P -003C 29

F4

P 003E D6

0000*

P 0041 56

FA

43
44
45
46
47
48
49
50
51
52
53
54
55

F7

P 0044

jr
RR
djnz

c,done
R2
r1,loop

!load value for detected
bit rate!
!Delay long enough to clear serial line of bit stream!
DELAY
call
_!clear recei v e interrupt request!
IRQ,II%F7
and
TO, R2

done:

ld

END
END

main

bi t_rate

o ERRORS
ASSEMBLY COMPLETE
30 instructions

68 bytes
Execution time is variable based on transmission bit rote.

8.3 Port Handshake. Each of Ports 0, I and 2
may be programmed to function under input or
output handshake control. Table 7 defines the
port bits used for the handshaking and the
mode bit settings required to select handshaking. To input data under handshake control,
the Z8 should read the input port when the
DA V input goes Low (signifying that data is
available from the attached device). To output
data under handshake control, the Z8 should
write the output port when the RDY input goes
Low (signifying that. the previously output data
has been accepted by the attached device).
Interrupt requests IRQO, IRQI, and IRQ2 are
generated by the falling edge of the handshake
Signal input to the Z8 for Port 0, Port I, and
Po~t 2 respectively. Port handshake operations
may therefore be processed under interrupt
control.
Consider a system that requires communication of eight parallel bits of data under handshake control from the 28 to a peripheral
device and that Port 2 is selected as the output
port. The following assembly code illustrates
the proper sequence for initializing Port 2 for
output handshake.'
Port 0

CLR

P2M

!Port 2 mode register: all Port
2 bits are outputs!
OR
%03,#%40
!set DAV2: data not available!
LD
P3M,#%20
!Port 3 mode register: enable
Port 2 handshake!
LD
%02,DATA
!output first data byte; DAV2
will be cleared by the Z8 to
indicate data available to
the peripheral device!
Note that following the initialization of the output sequence, the software outputs the first
data byte without regard to the state of the
RDY2 input; the Z8 will automatically hold
DAV2 High until the RDY2 input is High. The
peripheral device should force the Z8 RDY2
input line Low after it has latched the data in
response to a Low on IJAV2. The Low on RDY2
will cause the Z8 to automatically force DA V2
High until the next byte is output. Subsequent
bytes should be output in response to interrupt
request lRQ2 (caused by the High-to-Low transition on RDY2) in either a polled or an
enabled interrupt mode.
Port 1

Input handshake lines

P33 = TSJf:'J'
P34 = RDY

P31 = lJAV
P36 = RDY

Output handshake lines

P33 = RDY
P34 = lJAV

P31 = RDY
P36 = "'f5A'V

set bit 3 & reset bit 4 of
POIM (program byte as
input)

set bit 7 of P2M
(program high bit as input)

reset bits 6, 7 of POIM
{ (progra,m high nibble as
output)

reset bits 3, 4 of POIM
(program byte as output)

reset bit 7 of P2M
(program high bit as output)

Jset bit 5 of Port 3 (P3s);

set bit 4 6f Port 3 (P34);
set bits 3,4 of P3M ,

set bit 6 of Port 3 (P36);
set bit 5 of P3M

To select input handshake:

To select output handshake:
To enable handshake:

i

set bit 6 & reset bit 7 of
POIM (program high
,
nibble as input)

\setbit20fP3M

,

Table 7. Port Handshake Selection

222

Port 2

SECTION

9

Arithmetic Routines
This section gives examples of the arithmetic
and rotate instructions for use in multiplication, division, conversion, and BCD arithmetic
algorithms.

cessed one nibble at a time from left to right,
beginning with the high-order nibble of the
lower memory address. %30 is added to each
nibble if it is in the range 0 to 9; otherwise
%37 is added. In this way, %0 is converted to
%30, % I to %31. ... %A to %41, ... %F to
%46. Figure 5 illustrates the conversion of RRO
(contents = %F2BE) to its hex ASCII
eqUivalent; the destination buffer is pointed to
by RR4.

9.1 Binary to Hex ASCII. The following
module illustrates the use of the ADD and
SWAP arithmetic instructions in the conversion
of a l6-bit binary number to its hexadecimal
ASCII representation. The 16-bit number is
viewed as a string of four-nibbles and is pro0,

BIT
REGISTER

•

I

3

I

00

0,

• 3

I

RR4-

Do

.3

0,

I

I

0,

.3

Do

I

I

0,

I I
0,

01

0,

I I

.I,

0,

I

0,

.I

,

Do

I

Figure 5. Conversion of (RRO) to Hex ASCII

Z8ASM
LOC

INTERNAL RELEASE
STMT SOURCE STATEMENT

2.99
OBJ CODE

P 0000

P
P
P
P

0000
0002
0004
0006

6C
FO
28
56

04
EO
EO
E2

p

0009
OOOC
OOOF
0011
0014
0016

06
A6
7B
06
92
AO

E2
E2
03
E2
24
E4

30
3A

P 0018 A6
p 001B EB
P 001D 08

E6
02
E1

03

P 001F 6A
P 0021 AF
P 0022

E1

P
P
P
P
P

o

OF

07

1 ARITH
MODULE
2 GLOBAL
3 BINASC PROCEDURE
4 !*****************************************************
To convert a 16-bit binary
5 Purpose
6
number to Hex ASCII
7
RRO
16-bit binary number.
8 Input
RR4 = pOinter to destination
9
10
buffer in external memory.
11
12 Output
Resulting ASCII string (4 bytes)
in destination buffer.
13
14
RR4 incremented by 4 .
RO,R2,R6 destroyed.
"
15
16 *****************************************************!
17 ENTRY
18
R6,11%04 !nibble count!
Id
19
RO
!look at next nibble!
20 again: SWAP
21
R2, RO
ld
R2,#%OF !isolate 4 bits!
22
and
23 !convert to ASCII : R2 + #%30 if RO in range 0 to
24
else R2 + #137 (in range OA to OF)
25
26
ADD
R2,II%30
R2,#13A
27
cp
28
jr
ult, skip
ADD
R2,1I%07
29
!save ASCII in buffer!
@RR4,R2
30 skip:
Ide
!point to next
RR4
incw
31
buffer position!
32
R6,#%03 !time for second byte?!
cp
33
!no.
!
ne,same_byte
jr
34
!2nd byte!
RO, R1
ld
35
36 same_byte:
R6,again
djnz
37
ret
38
BINASC
39 END
40 END
ARITH

errors

Assembly complete
15 instructions

34 bytes
120.5 p.s (average)

223

9. Arithmetic 9.2 BCD Addition. The following module illusRoutines
' trates the use of the add with tarry' (ADC) and
(gc:>?tinued)

significant digit in bits 7"':4. Bytes within a
BCD string are arranged in memory with the
most significant digits stored in the lowest
memory location. Figure 6 illustrates the
representation of 5970 in a 6-digit BCD string,
starting in register %33.

decimal adjust (DA) instructions for the addition of two unsigned BCD strings of equal
length. Within a BCD string, each nibble
represents a decimal digit (0-9). Two such
digits are packed per byte with the most
BIT

REGISTER

'1"

••

Do

1 '"1

..

.,.1

..
..

.,.1

Do

·1

'"1

..
.

.,.1

Do

I

Figure 8. Unsigned BCD, Rep....nlallon

Z8ASM
LOC

2.0
OBJ CODE

STMT SOURCE STATEMENT
1 ARITH

2 CONSTANT

3

4

BCD_SRC • _ Rl
BCD_DST : = RO

5 BCD_LEN := R2
.
6 GLOBAL
7 BCDADD PROCEDURE

P 0000

P 0000 02
P 0002 02
P 0004 CF

12
02

P 0005 00

E1

P 0007 00

EO

P
P
P
P
P

31
30
E3
03
F2

0009
OOOB
OOOD
OOOF
0011

MODULE

E3
13
40
F3
2A

P 0013 AF
P 0014

8 1***********************************.*****************
To add two packed BCD strings of
9 Purpose =
10
equal length.,
11
dst <-- dst + src
12
13 Input
RD
pointer to dst BCD string.
14
Rl
poiQter ~o src BCD string.
15
R2
byte count in BCD string
16
(digit count = (R2)*2 ).
17
18 Output
BCD string pointed to by RO is
19
the sum.
20
Carry FLAG = 1 if overflow.
21
RD , Rl as on entry.
22
R2 = 0
23 *****************************************************1
24 ENTRY
25
26
.add
BCD_SRC,BCD_LEN Istart at least ••• I
add
27
BCD_DST,BCD_LEN Isignificant digits!
28
rcf
Icarry = O!
29 add_again:
30
dec
BCD_SRe
Ipoint to next two
31
src digits!
32
BCD_,DST
'!point to next two
dec
dst digitsl
33
34
ld
R3,@BCD_SRC
Iget src digitsl
35 .
ADC'
R3,@BCD_DST
ladd dst digits I
36
DA
R3
Idecimal adjustl
ld
@BCD_DST,R3
Imove to dstl
37
djnz
38
BCD_LEN,add_again Iloop for next
39
digits I
40
ret
lall done I
41
42 END
BCDADD
ARITH
43 END

o ERRORS
ASSEMBLY COMPLETE
'11 instructions
20 bytes
Execution time is a function of the number of bytes (n) in input BCD string:
20 ps + 12.5 (n - 1) ps
,

224

/

9. Arithmetic: 9.3 Multiply. The following module illustrates
an efficient algorithm for the multiplication of
two unsigned 8-bit values, resulting in a 16-bit
(Continued)
product. The algorithm repetitively shifts the
multiplicand right (using RRC)' with the loworder bit being shifted out (into'the carry flag).
If a one is shifted out, the multiplier is added

to the high-order byte of the partial product.
As the high-order bits of the multiplicand are
vacated by the shift, the resulting partialproduct bits are rotated in. Thus, the multiplicand and the low byte of the product occupy
the same byte, which saves register space,
code, and execution time.

Routines

Z8ASM
LOC

2.99
OBJ CODE

P 0000

P
P
P
P
P
P
P
P
P
P

0000
0002
0004
0005
0007
0009
OOOB
OOOD
OOOF
0010

OC
BO
CF
CO
CO
FB
02
OA
AF

09
E2
E2
E3
02
21
F6

INTERNAL RELEASE
STMT SOURCE STATEMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

ARITH
MODULE
CONSTANT
MULTIPLIER
PRODUCT_LO
PRODU CT_HI
COUNT
GLOBAL
MULT
PROCEDURE

Rl
R3
R2
RO

!*************~***************************************

Purpose
Input

Output

To perform an 8-bit by 8-bit unsigned
binary multiplication.

=
=

Rl = multiplier
R3 = multiplicand
RR2
RO

= product

destroyed

*****************************************************!
ENTRY

LOOP:

NEXT:
END
END

ld
clr
RCF
RRC
RRC
jr
ADD
djnz
ret
MULT
ARITH

COUNT, 119
PRODUCT_HI

18 BITS + 11
IINIT HIGH RESULT BYTEI
!CARRY = O!

PRODUCT_HI
PRODUCT_LO
NC,NEXT
PRODUCT_HI, MULTIPLIER
COUNT, LOOP

o err"ors
Assembly complete
9 instructions
16 bytes
92.5 p.s (average)

9.4 Divide. The following module illustrates
an efficient algorithm for the division of a
16-bit unsigned value by an 8-bit unsigned
value, resulting in an 8-bit unsigned quotient.
The algorithm repetitively shifts the dividend
left (via RLC). If the high-order bit shifted out
is a one or if the resulting high-order dividend
byte is greater than or equal to the divisor, the

divisor is subtracted from the high byte of the
dividend. As the low-order bits of the dividend
are vacated by the shift left, the resulting
partial-quotient bits are rotated in. Thus, the
quotient and the low byte of the dividend
occupy the same byte, which saves register
space, code, and execution time.

225

9. Arithmetic
Routines
(Continued)

Z8ASM
LOC

2.0
OBJ CODE

STMT SOURCE STATEMENT
1 ARITH

2 CONSTANT

MODULE

COUNT
DIVISOR
DIVIDEND_HI
DIVIDEND_LO
GLOBAL
7
8 D+VIDE PROCEDURE
3

4

5
6

P 0000

RO
Rl
R2
R3

9 1*****************************************************

10

Purpose'
To perform a 16-bit by 8-bit unsigned
binary division.
'
12
13 Input =
Rl = 8-bit divisor
14
RR2
16-bit dividend
15
16 Output =
R3
8-bit quotient
17
R2
8-bit remainder
18
Carry flag = 1 if overflow
19
= 0 if no overflow
20 *****************************************************!
ENTRY
.
21
22
ld
COUNT,118
ILOOP COUNTER!
23
24 !CHECK IF RESULT WILL FIT IN 8 BITS!
cp
DIVISOR,DIVIDEND_HI
25
26
jr
UGT,LOOP
!CARRY
o (FOR RLC)!
27 IWON'T FIT. OVERFLOW I
28
SCF
! CARRY
11
29
ret
30
!RESULT WILL FIT. GO AHEAD WITH DIVISION!
31 LOOP:
32
RLC
DIVIDEND_LO
!DIVIDEND * 21
RLC
DIVIDEND_HI
33
34
jr
c,subt
cp
DIVISOR,DIVIDEND_HI
35
36
jr
UGT,next
ICARRY = 01
SUB
DIVIDEND_HI,DIVISOR
37 subt:
SCF
ITO BE SHIFTED INTO RESULT!
38
djnz
COUNT,LOOP
!no flags affected I
39 next:
40
41 !ALL
DONE!
42
RLC
43
I CARRY
0: no overflow!
44
ret
45 END DIVIDE
46 END ARITH
11

P 0000 OC

08

!' 0002 A2
BB

12
02

P 0004

P 0006 DF
P 0007 AF
P
P
P
P
P
P
P
P

0008 10
OOOA 10
oooe 7B
OOOE A2
0010 BE
0012 22
0014 DF
0015 OA

E3
E2
04
12
03
21

P 0017 10

E3

Fl

P 0019 AF
P 001A
o ERRORS
ASSEMBLY COMPLETE
15 instructions

26 bytes
124.5 pB (average)

SECTION

10

226

Conclusion
This Application Note has focused on ways
in which the 28 microcomputer can easily yet
effectively solve various application problems.
In particular, the many sample routines

illustrated in this document should aid the
reader in using the 28 to greater advantage.
The major features of the 28 have been
described so that the user can continue to
expand and explore the 28's repertoire of uses.

·Z8@ SabroaliDe Library
AppllcalioD
Nol8

April 1982
INTRmUCTIIIII

This spplication note deacribes a preprogranmed
Z8601 MCU that contains a bootstrap to external
program memory and a collection of general-purpose
subroutines.
Routines in this application note
can be implemented with a ZB Protopack and a 2716
EPROM programmed with the bootstrap and subroutine
librsry.
In a system, the user's software resides in
external memory beginning at hexidecimal address
OBOO.
This aoftware can use any of the

Table 1.

subroutines in the library wherever appropriate
for a given application. This applicstion example
makes certain asaumptions about the environment;
the reader should exercise caution when copying
theae programs for other cases.
Following· RESET, software within the subroutine
librsry is executed to initislize the control
registers (Table 1).
The controi register
selections csn be subsequently modified by the
user's program (for example, to·use only 12 bits
of Ports 0 and 1 for addresaing external memory).
Following control register' initialization, an EX

Control Register Initialization

Control R!9iater
N.a

Address

Initial Value

Meaning

TMR

F1H

OOH

TO and T1 disabled

P2M

F6H

FFH

P20-P27 : inputs

P3M

F7H

10H

P2 pull-ups open drsin;
P30-P33 inputs;
P3S-P37 outputs;
P34
OM

P01M

FBH

07H

P10-P17
ADO-AD,;
AB-A1S;
POO-P07
normal memory timing;
internal stack

IRQ

FAH

OOH

no interrupt requests

IMR

FBH

OOH

no interrupts· enabled

RP

FDH

OOH

working register file
OOH-OFH

SPL

FFH

6SH

1st byte of stsck is
register 64H

227

instruction is executed to enable interrupt
processing, and a jump instruction is executed to
transfer control to .the user's program at location
OS12 H•
The interrupt vectors for IRQO through
IRQ5 are rerouted to locations OSOOH through
080fH' respectively, in three-byte increments,
allowing enough room for a jump instruction to the
appropriate interrupt service routine.
That is,
IRQO is ,routed to location OSOOH' IRQ1 to
0803H, IRQ2 to0806H' IRQ3 to OB09H' IRQ4 to
080~, and IRQ5 to OBOfH'
figure 1 illustrates the allocati.on of Z8memory as defined by
this application note.
The subro1Jtines' available to the user are referenced by a jump. table beginning at location
001BH. Entry to a subroutine is made via the jump
table. The 32 subroutines provided in the library
are grouped into six functional c lassi·fications.
These classifications are described below, each
with a brief overview of the functions provided by
each category. Table 2 defines one set of entry
addresses for each subroutine in the library.

•

Binary Arithmetic. Multiplication and division
of unsigned 8- and 16-bit quantities.

•

BCD Arithmetic.
Addition and subtraction of
variable-precision floating-point BCD values.

REGISTER
FF

F.

•

Conversion Algorithms. BCD to and from decilnal
ASCII, binary to and from decimal ASCII, binary
to and from hex ASCII.

•

Packs selected bits into
Bit Manipulations.
the low-order bih of a byte, and optionally
uses the result as an index into a jump table.

•

Serial I/O. Inputs bytes under vectored interrupt control, outputs bytes under polled interrupt control. Options provided include:
odd or even parity
BREAK detection
echo
input editing (backspace, delete)
auto line feed

•

Timer/Counter:
Maintains a time-of-day clock
with a variable number of ticks per second,
generates an interrupt after a specified delay,
generates variable width, variable frequency
pulse output.

The listings in the "Canned Subroutine Library"
provide a specification block prior to each subroutine, explain the subroutine's purpose, lists
the input and output parameters, and gives pertinent notes concerning the subroutines. The following notes provide additional information on data
formats and algorithms used by the subroutines.
PROGRAM

FFFF

CONTROL
REGISTERS

FFFF ...-_....:;EX;;.TE:.;R:.;.;N;.;;AL;.;D:.;.;A:.;.;TA;...._.,

EF
UNIMPLEMENTED
80
7F

7,

,.

7A
USER
DEFINED

USER

2.

DEFINED

,E
6D

,.
'4

3.

----------STACK

,

0812
001

USER
DEFINED

08. 0

START
INTERRUPT VECTORS
(3 BYTElIRQx)

07F F

INTERNAL
SUBROUTINES

04

03
110 POATS

0000 ....._ _ _ _ _ _ _.......

00

0000
REGISTERS USED BY SUBROUTINES:

1. USED BV MOST ROUTINES
2. USED BY SERIAL ROUTINES ONLY
3. USED BY TlMEAfCOUNTER ROUTINES ONLY

Figure 1.

228

-Rllness ZS- 5mroutine library tte.ory Usage Map

1.

Although the user is free to modify the conditions selected in the Port 3 Mode register
(P3M, F7H)' P3M is a write-only register.
This subroutine library maintains an image of
P3M in its register P3M __save (7F H).
If
software outside of the subroutine package is
to modify P3M, it should reference and modify
P3M save prior to modification of P3M. For
example, to select P32/P35 for handshake, the
following instruction sequence could be used:

Digits are packed two per byte with the mostsignificant digit in the high-order nibble of
byte 1 and the least-significant digit in the
low-order nibble oi byte n. Byte 0 is organized as two fields:
Bit 7 represents sign:
1 negative;
o = positive.
Bits 0-6 represent post-decimal digit count.

OR

LD

P3M save, 1I04H
P3M:-P3M_save

For example:
byte 0

2.

For many of the subroutines in this library,
the location of the operands (source/destination) is flexible between register memory,
external memory (code/data), and the serial
channel (if enabled). The description of each
parameter in the specification blocks tells
what the location options are.
4.
•

•

3.

The location designation "in reg/ext
memory" implies that the subroutine allows
the operand to exist in register or in
external data memory. The address of such
an operand is contained in the designat~d
register pair.
If the high byte of that
pair is 0; the operand is in register
memory at the address held in the low byte
of the register pair.
Otherwise, the
operand is in external data memory
(accessed via LDE).
The location designation "in reg/ext/ser
memory" implies the same considerations as
above with one enhancement: if both bytes
Qf the register pair are 0, the operand
exists in the serial channel.
In this
case, the register pair is not modified
(updated). For example, rather than storing a destination ASCII string in memory,
it might be desirable to output the string
to the serial line.

The BCD format supported by the following
arithmetic and ,converSion routines allows representation of signed variable-precision BCD
numbers. A BCD number of 2n digits is represented in n+1 consecutive bytes, where the
byte at the lowest memory address (byte 0)
represents the sign and post-dedmal. digit
count, and the bytes in the n higher memory
locations (bytes 1 through n) represent· the
magnitude of the BCD number. The address of
byte 0 and the value n are passed to the subroutines in specified working registers.

positive, with five
decimal digits
negative, with no
BOH
decimal digits
negative, with 16
90 H
decimal digits

05H

post':'
postpost-

The format of the decimal ASCII character
string expected as input to the conversion
routines "dascbcd" and "dascwrd" is defined
as:
( + 1 - ) (  ) 1

in which
Parentheses mean that the enclosed
times or can be omitted.
[ 1 Bracketa denote that the enclosed
element is optional.
( )

Table 3 illustrates how various input strings
are interpreted by the conversion routines.

5.

The format of the decimal ASCII character
string output from the conversion routine
"bcddasc" operating on an input BCD string of
2n digits is
sign of character ( + 1 - )
2n-x pre-decimal digits
1 decimal point if x does not equal 0
x post-decimal digits

6.

The format of the decimal ASCII character
string output from the conversion routine
"wrddassc" is
1 sign character (determined by bit 15 of
input word)
6 pre-decimal digits
no decimal point
no post-decimal digits

229

Table Z.

Subroutine Entry Points
Description

Address
Binary Arithletic Routines
001B
001E
0021
0024

divide
div.16
multiply
mult 16

16/8 unsigned binary division
16/16 unsigned binary division
8x8 unsigned binary multiplication
16x16 unsigned binary multiplication

BID Arithletic Routines
0027
002A

bed add
bcdsub

BCD addition
BCD subtraction

COnversion Routines
002D
0030
0033
0036
0039
003C
003F
0042
0045

bcddasc
dascbcd
bcdwrd
wrdbcd
bythasc
wrdhasc
hascwrd
wrddasc
dascwrd

BCD to decimal ASCII
Decimal ASCII to BCD
BCD to binary word
Binary word to BCD
Binary byte to .hexadecimal ASCII
Binary word to hexadecimal ASCII
Hexadecimal ASCII to binary word
Binary word to decimal ASCII
Decimal ASCII to binary word

Bit Manipulation Routines
0048
004B

clb
tmj

Collect bits in a byte
Table jump under mask

Serial Routines
004E
0051
0054
0057
005A
005D
0060
0063
0066
0069

ser init
ser_input
ser rlin
ser rabs
ser break
ser flush
ser wHn
ser wabs

ser_wbyt
ser disable

Initialize serial I/O
IRQ3 (receive) service
Read line
Read absolute
Transmit BREAK
Flush (clear) input buffer
Write line
Write absolute
Write byte
Disable serial I/O

Tiller/Counter Routines
006C
006F
0072
0075
0078

230

tod i
tod
delay
pulse_i
pulse

Initialize for time-of-day clock
Time-of-day IRQ service
Initialize for delay interval
Initialize for pulse output
Pulse IRQ service

7.

rhe register pair SERhtime, SERltime was
initialized during ser
init to equal the
product of the prescaler and the counter
selected for the baud rate clock. That is,

Procedure name: ser___input
The conclusion of the algorithm for BREAK
detection requires the Ser ial Receive Shift
'register to be cleared of the character
This
currently being collected (if any).
requires
a software wait
loop
of
a
one-character
duration.
The
following
explains the algorithm used (code lines 464
through 472, Part II):
1 character time

SERhtime, SERltime = PREO x TO
The instruction sequence

(128xPREOxTO) sec 10 bit
bit x
char
XTAL,
1280xPREOxTO sec
XTAL
CFiii"r

sec
loop

Solve for n:
(1280 x PREO x TO)
2n
= XTAL
XTAL
640 x PREO

(6 cycles)

lpl:

rSERtmpl, lpl

(12/10 cycles
taken/not taken)

djnz

6 + (52 x 12) + 10 cycles

8.

1 character time = __2_ ~ x n cycle
XTAL cycle
loop

n

rSERtmpl, #53

executes in

A software loop equal to one character time is
needed:

2n
= XTAL

inlop: Id

BREAK detection on the serial input line
requires that the receive interrupt service
routine be entered within a half -a-bit time,
since the routine reads the input line to
detect a true (=1) or false (=0) stop bit.
Since the interrupt request is generated
halfway through reception of the stop bit,
half-a-bit time remains in which to read the
stop bit level.
Interrupt priorities and
interrupt nesting should be established
appropriately to ensure this requirement.

x TO
1/2 bit time

Table J.

Input String

+1234.567,

(128 x PREO x TO)
XTAL x 2

sec

Decwal ASCII Olaracter String Interpretation

Sign

Result
Pre-Decwal
Digits

Post-Decillal
Digits

+

12J4

567
789

+---+. 789+
1234 ••

+

4976-

+

NOTE:

640 cycles

Terainator

+

1234
4976

The terminator can be any ASCII character that is not a valid ASCII string
character.

231

ROMLESS Z8 SUBROUTINE LIBRARY PART I
Z8ASM
LOC

3.02
OBJ CODE

STMT SOURCE STATEMENT
1

2

3 PART I

MODULE

4

5

6 !'ROMLESS Z8'

7

8
9
10

Initialize:

11

12
13
14
15
16
17
18

SUBROUTINE LIBRARY

PART I

a) Port 0 & Port 1 set up to address
64K external memory;
b) internal stack belaw allocated
RAM for subroutines;
c) normal memory timing;
d) IMR, IRQ, TMR, RP cleared;
e) Port 2 inputs open-drain pull-ups;
f) Data Memory select enabled;
g) EI executed to 'unfreeze' IRQ;
h) Jump to %0812.

19

20 Note:
21
22

23
24
25
26
27

28
29
30
31
32
33
34
35
36
37
38
39

40
41
42

232

The user is free to modify the initial
conditions selected for a, b, and c above,
via direct modification of the Port 0 & 1
Mode register (P01M, %F8).
The user is free to modify the conditions
selected in the Port 3 Mode register (P3M, %F7).
However, please note that P3M is a write-only
register. This subroutine library maintains
an image of P3M in its register P3M save (%7F).
If software outside of the subroutine package
is to modify P3M, it should reference and modify
P3M save, prior to modification of P3M. For
example, to select P32/P35 for handshake, use
an instruction sequence such as:
OR
LD

P 3M save, U04
P3M-;-P3M_ save

This is important if the serial and/or timer/
counter subroutines are to be used, since these
routines may modify P3M.

44 IAccess to GLOBAL subroutines in this library should
45 be made via a CALL to the corresponding entry in the
46 jump table which begins at address SOOOF. The jump
47 table should be referenoed rather than a CALL to the
48 ,aotual entry point of the subroutine to avoid future
49 oonfliot in the event suoh entry points ohange in
50 potential future revisions.
51
52 Each GLOBAL subroutine in this listing is headed by a
53 oomment blook specifying its PURPOSE and calling
54 sequence (INPUT and OUTPUT parameters). For many of
55 the subroutines in this library, the location of the
56 operands (souroes/destinations) is quite flexible
57 between register memory, external memory (oode/data),
58 and the serial ohannel (if enabled). The desoription
59 of each parameter speoifies what the looation ohoices
60 are:
61

62
- The location designation 'in reg/ext memory"
63 implies that the subroutine allows that the operand
64 exist in either register or external data memory
65 The address of suoh an operand is oontained
66 ,in the designated register pair. If the high byte of
67 that pair is zero~ the operand is in register memory
68 at the address given by the low byte of the register
69 pair. Otherwise, the operand is in external data
70 memory (aooessed via LDE).
71
72
- The looation designation
73 'in reg/ext/ser memory' impli~s the same
74 oonsiderations as above with one enhancement: if both
75 bytes of the reg. pair are zero, the operand exists
76 in the serial ohannel. In this case, the register
77 pair is not modified (updated). For example, rather
78 than storing a destination ASCII string in memory, it
79 might be desirable to output suoh to the serial line.
80.!

233

82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145

234

CONSTANT
! Register Usag e!
RAM START

·-

~7F

RAM START
P3M save
:=
P3M- save-l
TEM15 3
·: =TEMP-2
TEM"Y 3-1
TEMP-l
TEMP-2-1
:=
TEMP-4
TEMP:l-1
:=
!The following registers are modified/referenced
by the Serial Routines ONLY. They are
available as general registers to the user
who does not intend to make use of the
Serial Routines!
SER char
:=
TEMP 4-1
SER-tmp2
._
SER Char-1
._
SER-tmp2_1
SER-tmp1
SER-put
:=
SER-tmpl-1
SER-len
:=
SER-put-1
._
SER-len-2,
SER-buf
SER-imr
:=
SER-buf-1
SER-cfg
:=
SER-imr-1
! Serial Configuration Data
=1 => odd parity on
bit 7
bit 6 : =1 => even parity on
(bit 6,7 = 11 => undefined)
bit 5
undefined
bit 4
undefined
bit 3
=1 => input editting on
bit 2
=1 => auto line feed enabled
bit 1
=1 => BREAK detection enabled
bit 0 ,: =1 => input echo on
op
ep
ie
al
be
eo
SER get
SER-flg
! Serial
bit7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
!

sd
pe
bd
bo
bne
bf

····· -,
:=

~80
~40

%08
%04
%02
~01

··Flags

SER ofg-l
SER:get-l

Status
=1 => serial IIO disabled
undefined
undefined
=1 => parity error
=1 => BREAK detected
=1 => input buffer overflow
=1 => input buffer not empty
=1 => input buffer full

·:=-

:=
:=

··-

%80
:$10
%08
%04
%02
%,01

RAM TMR

:=

RAM START-%10

SERltime

:=

SER_flg-l

146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

SERhtime

SERltime-1

!The following registers are modified/referenced
by the Timer/Counter Routines ONLY. They are
available as general registers to the user
who does not intend to make use of the
.
Timer/Cou~ter Routinesl
TOD tic
TOD-imr
TOD-hr
TOD-min
TOD-sec
TOD-tt
PLS-1
PLS-tmr
PLS:2'

:=
:=

RAM END
STAl:K

:=

: ::

RAM TMR-2
TOD-tic-1
TOD-imr-1
TODnr-1
TOD-min-1
TOD-sec-1
TOD-tt-1
PLS-1-1
PLS:::tmr-1
PLS 2
RAM-END

IEquivalent working register equates
for above register layoutl
Iregister file
RAM STARTr
rP3Msave
rTEMP 3
rTEMP-2
rTEMP-1
rrTEMP 1
rTEMP lh
rTEMP-1l
rTEMP-4
rSERcllar
rSERtmp2
rSERtmp1
rrSERtmp
rSERtmpl
rSERtmph
rSERput
rSERlen
rrSERbuf
rSERbufh
rSERbufl
rSERimr
rSERc fg
rSERget
rSERflg

~70

._

:=
:=

:=
:=
:=
:=

:=

- S7FI

no

I for SRP!

R15
R14
R13
R12
RR12
R12
R13
R11
R10
R9
R8
RR8
R9
R8
R7
R6
RR4
114
R5
R3
R2
R1
RO

!register file %60 - %6F!
RAM TMRr
%60
rTOll"tic
R13
rTODimr
R12
rTODhr
R11
rTODmin
R10
:=
rTODsec
R9
rTODtt
R8
rPLS 1
:=
R7
rPLS't"mr
R6
:=
rPLS_2
R5

.! for SRPI

(

235

~.
r.

P
P
P
P
P
P

0000
0002
0004
0006
0008
OOOA

0800
0803
0806
0809

oaoc

080F

... .
236

210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242

,

EXTERNAL
ser Inlt
ser-lnput
, ser"'"rlln
ser-rabs
ser-break
ser-flush
ser-wlin
ser-wabs
ser-wbyt
ser-dlsable
ser-get
ser-output
tod-l
tQddelay
pulse_l
pulse

GLOBAL

r

PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE,
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE

'

$SECTION PROGRAM

IInterrupt vectorsl
[ 1 word]
IRQ 0
ARRAY
IRQ-1
ARRAY
[ 1 word]
IRQ-2
[ 1 word]
ARRAY
IRQ-3
ARRAY
[1 word]
I.RQ-4
[ 1 word]
ARRAY
ARRAY
[ 1 word]
IRQ::::5

=
=
=
=
=

a0800]
[S0803]
[S0806]
a0809]
[S080C]
[S080F]

..

P OOOC
P OOOC 80
P OOOF

007B'

P
P
P
P

113
39
5A
IIF

OOOF
0012
0015
0018

28
31
30
IIC

29
38
119
117

P 001B

P 001B 80

0099'

P 001E 80

00B7'

P 0021 80

00E2'

P 00211 80

00F6'

P 0027 80

011A'

P 002A 80

0117'

P 0020 80

0205'

P 0030 80

0363 '

P 0033 80

02811'

p

0036 80

02CD'

P 0039 80

025C'

P 003C 80

0257'

P 003F 80

0319'

P 00112 80

03BE'

P Oell5 80

03110'

P 00118 80

OIlAl '

P OOIlB 80

01lB9'

P OOIlE 80

0000·

21111
2115
2116
2117
2118
2119
250
251
252
253

2511
255
256
257
258
259
260
261
262
263
2611
265
266
267
268
269
270
271
272
273
2711
275
276
277
278
279
280
2111
282
283
2811
285
286
287
288
289
290
291
292
293
2911
295
296
297
298
299
300
301
302
303
3011

GLOBAL
IJump Tablel
ENTER
PROCEDURE
ENTRY
INIT
JP
END
ENTER
copyright ARRAY [. BYTE] := '(C) 1980ZILOG'

ISubroutine Entry Pointsl
PROCEDURE
JUMP
ENTRY
IBinary Arithmetic Routinesl
JP

divide

116/8 unsigned binary

JP

div_16

116/16 unsigned binary

JP

mul tiply

JP

mult_16

divisionl

divisionl
!8x8 unsigned binary
multiplicationt
116x16 unsigned binary
multiplication I

IBCD Arithmetic Routinesl
JP

bcdadd

IBCD addition I

JP

bcdsub

I BCD subtraction I

I Conversion Rou'tinesl
JP

·bcddasc

IBCD to decimal ASCIII

JP

dascbcd

I Decimal ASCII to BCDI

JP

bcdwrd

I BCD to binary wordl

JP

wrdbcd

Ibinary word to BCDI

JP

bythasc

I Bin. byte to Hex ASCIII

JP

wrdhasc

IBin. word to hex ASCII I

JP

hascwrd

I Hex ASCII to bin wordl

JP

wrddasc

IBin. word to dec ASCIII

JP

dascwrd

Idec ASCII to bin wordl

IBit Manipulat10n Routines!
JP

clb

Icollect bits in a by tel

JP

tjm

ITable Jump Under Maskl

ISerial Routinesl
JP

ser init

I initialize serial I/OI

237

P 0051 8D

0000*

P 0054 8D

0000·

P 0057 8D

0000·

P 005A 8D

0000·

P 005D 8D

0000·

P 0060 8D

0000·

P 0063 8D

0000·

P 0066 8D

0000·

P 0069 8D

0000·

P 006C 8D

0000·

P 006F

~D

0000·

P 0072 8D

0000·

P 0075 8D

0000·

P 0078 8D

0000·

P 007B
?

007B

P 007B E6

F8

D7

P 007E E6

7F

10

P
P
P
P
P
P
P
P
P

7F
FF
F1
F6
FA
FB
FD
70

F7
65

0081
0084
0087
0089
D08C
008E
0090
0092
0095

E4
E6
BO
E6
BO
BO
BO
E6
9F

P 0096 8D
P 0099

238

0812

FF

80

305
ser_input
JP
306
307
ser rlin
JP
308
309
ser rabs
JP
310
311
ser break
JP
312
313
ser flush
JP
314
315
ser wlin
JP
316
317
ser wabs
JP
318
319
ser_wbyt
JP
320
321
ser disable
JP
322
323
324 I Timer/Counter Routines!
325
tod_i
JP
326
327
tod
JP
328
329
delay
JP
330
331
pulse i
JP
332
333
pulse
JP
334
335
JUMP
336 END
338
339
340
341
342
343
344
345
346
347
348
349
350
351'
352
353
354
355
356
357
358
359
360
361
362
363
364

!IRQ3 (receive) service!
tread line!
tread absolute!
! transmit BREAK!
! flush (clear)
input bufferl
! write liner
!write absolute!
!write byte!
! disable serial, I/O!

!init for time of dayl
!tod IRQ servicel
!ini1; for delay interval
linit for pulse outputl
!pulse IRQ service!

lIn it ia11 zat ion!
PROCEDURE
INIT
ENTRY
LD

LD

LD
LD
CLR
LD
CLR
CLR
CLR
LD
EI
JP
END

INIT

P01M,#%(2)11010111
!internal stack;
ADO-A15;
normal memory
timing !
P3 M_ save,#%(2)00010000
!P3M is write-only,
so keep a copy in
RAM for later
reference !
P3M, P3M save
! set up Port 3
!stack pointer
Sl'L,IISTACK
TMR
!reset timers!
! all inputs I
P2M,/I%FF
IRQ
!reset into requests!
!disable interrupts I
IMR
RP
Iregister pointer!
!serial disabledl
SER_flg,U80
! globally enable
interrupts I
%0812

Binary Arithmetic Routines

P

00~9

P 0099 A9
P 009B AC

7C
08

P 0090 A2
P 009F BB

BC
02

P 00A1 OF
P OOA2 AF
P 00A3
P 00A5
P 00A7
p 00A9
P OOAB
p OOAD
p OOAF
P OOBO

10
10
7B
A2
BB
22
DF
AA

F1

p 00B2 10

ED

P 00B4 A8

7C

p 00B6 AF

P 00B7

ED
EC
04
BC
03
CB

397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442

CONSTANT
div LEN
DIVIsOR
dividend HI
dividend-LO
=
GLOBAL
divide PROCEDURE

R10
R11
R12
R13

I·····················································
Purpose
To perform a· 16-bit by 8-bit unsigned
binary division.

Input
Output

=
=

R11 = 8-bit divisor
RR12
16-bit dividend
R13 = 8-bit quotient
R12 = 8-bit remainder
Carry flag = 1 if overflow
= 0 if no overflow
R11 unmodified

..................................................... ,
ENTRY

ld
ld

TEMP 1,div LEN
div_rEN,#8-

!save caller's R101

!LOOP COUNTER!

!CHECK IF RESULT WILL FIT IN 8 BITS!
cp
DIVISOR,dividend HI
TCARRY
jr
UGT,LOOP
!overflow!
!CARRY
SCF
ret
LOOP:

subt:
next:
!ALL

o

(FOR RLC)I

11

RLC
RLC
jr
cp
jr
SUB
SCF
djnz

dividend LO
!DIVIDEND • 2!
divide nd: HI ,
c,subt
DIVISOR,dividend_HI
ICARRY = 01
UGT,next
dividend_HI,DIVISOR
!TO BE SHIFTED INTO RESULTI
Ino flags affected I
div_LEN,LOOP

DONEI
RLC

dividend LO

ld
ret
END div ide

div_LEN, TEMP_

!CARRY = 0: no over flow I
Irestore caller's R101

239

P 00B7

P
P
P
P
P
P
P
P
P
P
.P
P
P
P
P
P

P

P
P
P
P
P
P
P

00B7
00B9
OOBB
OOBC
OOBE
OOCO
00C2
00C4
00C6
00C8
OOCA
OOCC
OOCE
0000
0002
0004
0006
0008
0009
OODB
0000
OODF
00E1
00E2

79
7C
CF
BO
BO
10
10
10
10
7B
A2
BB
7B
A2
BB
22
32
OF
7A
10
10
78
AF

7C
10
EA
EB

ED

EC
EB
EA
OA
8A
DB
04
9B
05
B9
A8

E5
ED
EC
7C

P 00E2

P
P
P
P
P
P
P
P
P
P
P
P

OOE2
00E4
00E6
00E8
00E9
OOEB
ODED
OOEF
00F1
00F3
00F5
00F6

240

A9
AC
BO
CF

7C
09
EC

CO
FB
02
AA
A8
AF

ED
02
CB
F6
7C

co EC

444
445
446
447
448
449
450
451
452
453
454
455
1156
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472

473

474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520

CONSTANT
d16 LEN
R7
dvsr hi
R8
dvsr-lo
R9
rem hi
R10
rem-lo
R11
quo! hi
R12
quot-lo
R13
GLOBAL:
div 16 PROCEDURE
I**T**************************************************
'purpose
To perform a 16-bit by 16-bit unsigned
binary divIsion.
Input =
Output

=

RR8 = 16-bit divisor
RR12 = 16-bit dividend
RR12 = 16-bit quotient
RR10 = 16-bit remainder
RR8 unmodified

.*************.*********.***~*****.*** •••• **.********!

ENTRY

Id
Id
rcf
clr
clr
dlp_16: rIc
rIc
rIc
rIc.
jr
cp
jr
jr
cp
jr
subt 16: sub
sbc
scf
skp_16: djnz
rIc
rIc
Id
ret
END div 16

TEMP 1,d16 LEN
d16_LEN,111o
rem hi
rem-lo
quo! 10
quot-hi
rem To
rem-hi
c ,sUbt 16
dvsr hi,rem hi
ugt,skp 16 ult,subt 16
dvsr lo,rem 10
ugt,skp 16rem lo,avsr 10
rem::::hi, dvsr :::hi
d16 LEN,dlp 16
quoT: 10
quot-hi
d16_L:EN,TEMP_1

!save caller's R101
ILOOP COUNTER I
!carry = O!

!no flags affected!

CONSTANT
R11
MULTIPLIER
:=
PRODUCT LO
R13
PRODUCT-HI
R12
mul LENR10
GLOBJrL
multiply
PROCEDURE
1*****************************************************
Purpose
To perform an 8-bit by 8-bit 'unsigned
binary multiplication.
Input

=

R11 = multiplier
R13 = multiplicand'

Output =
RR12 = product
R11 unmodified
*****************************************************!
ENTRY
ld
TEMP 1,muI LEN !save caller's R10!
mul :[EN,119! 8 BITS!
Id
clr
PRODUCT HI
IINIT HIGH RESULT BYTE!
RCF
ICARRY = O!
LOOP1 : RRC
PRODUCT HI
PRODUCT-LO
RRC
NC,NEXTjr
PRODUCT HI,MULTIPLIER
ADD
NEXT:
djnz
mul LEN-:-LOOP1
mul::::LEN,TEMP_1 !restore caller's R10!
Id
ret
multiply
END

P 00F6

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

00F6
00F8
OOFA
OOFC
OOH
OOFF
0101
0103
0105
0107
0109
010B
010D
010F
0111
0113
0116
0117

79
7C
BO
BO
CF
CO
CO
CO
CO
FB
02
12
7A
78
A9
44
AF

7C
11
EA
EB
EA
EB
EC
ED
Oil
B9
A8
FO
7C
7C
EB

7C

522
523
524
525
526
527
528
529
530
531
532
-533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563

CONSTANT
m16 LEN
plier hi
pl1er-lo
prod oi
prod:lo
mult hi
mult-1Q
GLOBAL
mult 16 PROCEDURE

R7
R8
R9
R10
R11
R12
R13

I···T.................................................

To perform an 16-bit by 16-bit unsigned
binary multiplication.

Purpose
Input

Output

=

RR8 = multiplier
RR12 = multiplicand

=

RQ10 = product (R10, R11, R12, R13)
RR8 unmod ified
Zero FLAG = 0 if result> 16 bits
= 1 if result fits in 16
(unsigned) bits (RR12 = result)

·····················································1
ENTRY
Id
Id
clr
clr
rcf
100p16: rrc
rrc
rrc
rrc
jr
add
adc
next16: djnz
Id
Id
or
ret
mult 16
END

TEMP 1,m16 LEN
m16 tEN,/I11
prod hi
prod:lo

Isave caller's R7!
116 BITSI
linit product!
ICARRY = O!

prod_hi
Ibit 0 to carry!
prod 10
mUltni
!multiPficand / 2!
mult-lo
nc,next16
prod lo,plier 10
prodyi, plieryi
m16 LEN,loop16
next bit!
m16-LEN,TEMP 1
restore caller's R7!
TEMP 1, prod hi
test product ..• 1
••• bits 31 - 161
TEMP:1, prod:lo

-

241

BCD Arithmetic Routines
593 IThe BCD format supported by the following arithmetic
594 and conversion routines allows representation
595 of signed magnitude variable precision BCD
596 numbers. A BCD number of 2n digits is
597 represented in n+1 consecutive bytes where
598 the byte at the lowest memory address
599 ('byte 0') represents the sign and post600 decimal digit count, and the bytes in the
601 next n higher memory locations ('byte l'
602 through 'byte n') represent the magnitude
603 of the BCD number. The address of 'byte 0'
604 and the value n are passed to the subroutines
605 in specified working registers. Digits are
606 packed two per byte with the most
607 significant digit in the high order nibble
608 of 'byte l ' and the least significant digit
609 in the low order nillble of 'byte n'. 'Byte 0'
610 is organized as two fields:
611
bit 7 represents sign:
612
= 1 => negative
613
,= 0 => positive
614
bit 6-0 represent post-decimal digit
615
count
616 For example:
617 'byte 0'= %05 => positive, with 5 post-decimal digits
61e
%80 => negative, with no post-decimal digits
619
%90 => negative, with 16 post-decimal digits
620

P 0117

P 0117 B7
P 011A

242

EE

80

622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651

CONSTANT
bcd LEN := R12
bcd-SRC ._ R14
bcd-DST ._ R15
GLOB1iL
bcdsub PROCEDURE

I·····················································
Purpose =
To subtract two packed BCD strings of
.

Input =

equal length.
dst <-- dst - src
R15
R14
R12

Output

address of destination BCD
string (in register memory).
address of source BCD
string (in register memory).
BCD digit count / 2

Destination BCD string contains the
difference.
Source BCD string may be modified.
R12, R14, R15 unmodified if no error
R13 modified.
Carry FLAG = 1 if underflow or format
error •
•• *** ••• ** •• ****.*** ••• ** •••••••••••••••• ** ••••• *****!
ENTRY
xor
Icomplement sign of
SUbtrahend!
!fall into bcdaddl
END
bcdsub

P 011A

POll A E6
P 011D D8
P 011F C9
P 0121 04
P 0124 E5
P 0127 56
P 012A 24
P 012D 7D
P 0130 6B
P 0132 70
P 0134 C7
P 013.7 76
P 013A 50
P 013C EB
P 013E BO
P 0140 D6
P 0143 21
P 0145 4D
P 0148 00
P 014A EB
P 014C D8
P 014E 00
P 0150 EB

7E 02
EE
7B
7B 7B
ED 7D
7D 7F
7D 7B
0203'
lA
EC
CD 01
EC FO
EC
OE
7C
0463 '
ED
0203'
7B
E6
EF
7E
CD

P
P
P
P
P
P
P
P

0152
0154
0157
015A
015D
0160
0162
0164

E3
56
E5
56
A4
70
7B
BB

DF
ED
EE
7D
7D
ED
39
18

P
P
P
P
P
P
P

0166
0168
016A
016C
016E
0170
0173

Dil
E9
F9
20
20
E5
A5

EC
7C
7B
7C
7B
7C
7B

7F
7D
7F
ED

7E
7E

653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716

GLOBAL
bcdadd

PROCEDURE

I··············*··**·**··*·····*·····~···*···*··**·*··
Purpose =
To add two packed BCD strings of
equal length.
dst <-- dst + src

Input

R15

Output =

Destination BCD string contains the sum.
Source BCD string may be modified.
R12, R14, R15 unmodified if no error
R13 modified.
.
Carry FLAG = 1 if overflow or format
error.

address of destination BCD
string (in register memory).
R14
address of source BCD
string (in register memory).
R12 = BCD digit ~ount / 2

·'*'·'*""""*·*"****'**'**""****·****'***'**'·*1

ENTRY
Idelete all leading pre-decimal zeroesl
ld
TEMP 3,#2
ld
R13,bcd SRC
ld
TEMP 4,Dcd LEN
add
TEMP-4,TEMP 4
!total digit count!
!ge~ sign/post dec 01
Id
TEMP-2,@R13!isolate post dec 01
and
TEMP-2,O%7F
Ipre-dec digit cntl
sub
TEMP-4,TEMP 2
jp
ult,oa err I format error I
!no pre-dec. digitsl
jr
z,ba 1push
R12 ! save!
ba 2:
!leading byte!
Id
R12,l (R13)
!test leading digiti
tm
R12,UFO
!restore!
pop
R12
!no more leading O'sl
jr
nz,ba 1
clr
TEMP T
!rotate leftl
call
rdl
!update post dec #1
inc
@R13
loops!
jp
ov,ba err
! dec pre-dec III
dec
TEMP 'If
! loopl
jr
nz,ba 2
Id
R13,bcd DST
ba 1:
dec
TEMP 3 !SRC and DST done?1
jr
nz,b~ 3
!do DSTI
Ileading zero deletion completel
!insure DST is > or =·SRC; exchange if necessary I
Id
R13,@bcd DST
lisolate post dec #1
and
R13,O%7FId
TEMP 2,@bcd SRC
lisolate post dec #!
and
TEMP-2,O%7Fcp
R13,TEMP 2
push
R13
Isavel
jr
ult,ba 4
IDST > SRCI
jr
ugt,ba-5
!DST < SRCI
!decimal points in same position.
must compare magnitudel
Id
R13,bcd LEN
Id
TEMP 1, ocd SRC
Id
TEMP-4,bcd-DST
inc
TEMP-'
ba 6:
inc
TEMP-4
Id
TEMP-3,@TEMP 1 Iget SRC by tel
cp
TEMP=3,@TEMP=4 !compare DST by tel

243

P ,0176
P .0178
P 017A
P 017C

BB
7B
DA
8B

P 017E
P 018.0
P 0181
P'0183
P 0185
P 0187
P 0189
P 018C
P C18F
P 0192
P 0195
P 0197
P 0199
P C19B

08
DE
tl2
02
00
0.0
E5
E5
F5
~5

OA
D8
50
70

P .0190 50
P C19F 24
P 01A2 CC
P 01A4 FB
P
P
P
P

C1A6
C1A8
CtAA
01AC

08
01
BC
06

P C1AF E5
P C1B2 B5
P
P
P
P
P

C1B5
01B7
C1BA
01BC
01BE

D8
24
6B
02
.02

P
P
P
P
P
P
P
P
P
P
P
P

C1CC
C1C1
C1C4
01C7
C1C9
01CC
01CE
.0101
0103
0106
0108
C10A

CF
E5
76
6B
35

P
P
P
P
P
P
P
P

010C
010E
C1DF
01E1
01E3
01E,6
01E8
01EA

08
DE
OA
8B
'17
41
0.0
DA

244

~B

15
110
F5
0.0
0.0
OA

06
23
FO
1F

717
718
719
72.0
721
EC
722
723
ED
7211
FO
725
EE
726
EF
727
EE 7C
728
EF 7B
729
7B EE
730
7C, ,EF
731
EE
732
7D
733
70
7311
ED
735
736
ED
737
738
739
711.0
ED 7D
7111
7D
7112
. 7113
.09
71111
EE
7115
ED
7116
7C
7117
0485'
748
749
EE 7B
75.0
EF 7B
7,51
752
EC
753
7D ED
754
45
755
ED
756
FC
757
758
759
EF 7C
76.0
7B 8.0
761
762
.05
EE 7C
763
764
03
EE 7C
765
7C
766
7C EF
767
EF
768
EE
769
E5
77.0
771
70
772
773
02
774
09
775
EF .0.0
776
EF
777
EF
778
F7
779

!SHC > DSTI
jr
ugt,ba 5
ult,ba-II
jr
ISRC < DSTI'
!loopl
H13,ba-6
djnz
ba II jr
lOST> or = SHCI
Iswap source and destination operands I
Id
R13,bcd LEN
ba_5:
linclude flag/size by tel
R13
inc
add
bcd SHC,H13
bcd-OST,H13
add
bcd-SHC
ba_7:
dec
bcd-OST
dec
TEMP t',@bcd SHC
ld
TEMP-II,@bcdIlST
ld
ld
@bcCSHC,TE'i4P II
@bcd-OST,TEMP-' lone byte swapped I
ld
djnz
R13,lia 7
R13,TERP_2
ld
pop
TEMP 2
R13 push
lexchange completel
Irestorel
pop
R13
ba II:
IR13 = DST post decimal digit count
TEMP 2 = SRC post decimal digit count
R13 =< TEMP 2
sub TEMP 2,R13
TEMP-2
rrc
lalignment offset I
Idigits word alignedl
nc,bi 8
jr
Irotate out least significant SRC post decimal digiti
R13,bcd_SRC
ld
Idec post dec digit #I
dec
@R13
TEMP 1
clr
call
rdr
Idetermine if addition or subtraction!
ba_8:
TEMP 4,@bcd SRC I sign of SHCI
ld
tEMP-4,@bcdIlST I sign of OSTI
xor
!get starting addresf;es I
ld
R13,bcd LEN
sub
R13,TEM1S 2
Idone already I
jr
z,ba_'4 add
bcd SRC,R13
bcd:OST,bcd_LEN
add
Ireadylll
rcf
Icarry = 01
TEMP 1,@bcd DST
ba 11: ld
TEMP-4,
U8Cladd or sub?1
tm
z,ba-9
laddl
jr
sbc
TEMP-',@bcd SRC
ba Hi
jr
TERp 1,@bcd SRC
ba 9:
adc
TEMP-'
,
ba-'0: da
@bcd-OST,TEMP 1
ld
bcd UST
dec
bcd-SRC
dec
djnz
R137ba 11
Ipropagate carry thru ~EMP 2 byte!! of OSTI
ld
R13,TEMP_2inc
!may be zerol
R13
djnz
R"3,ba_'2
jr
ba 13
@bod OST,IC
ba 12: adc
@bcd-DST
da
bcd UST
dec
djnz
R'3-;-ba_'2

(

P 01EC FB

13

P
P
P
P

EF 7C
7C 7F
0203'
7C 10
EF
0485'
EF

p

P
P
P
P

01EE
01Fl
01F4
'01F7
01FA
01FC
01FF
0201
0202

E5
56
60
E6
08
06
01
CF
AF

P 0203 OF
P 02011 AF
P 0205

780
781
782
783
784
785
786
787
788
789
790
791
792
793
7911
795
796

Icarry propagate complete I
ba 13: jr
nc,ba 14
Idonel
IRotate out least significant post decimal OST
digit to make room for carry at high endl
ld
TEMP 1,@bcd OST
TEMP-l,IIS7Fand
Ino post de,c digitsl
z,ba-err
jp
TEMP-l,1II10
ld
ld
, R13,Dcd OST
rdr
call
Idec digit cntl
dec
@bcd_OST
ba 111: rcf
ret
ba err: scf
ret
bcdadd
ENO

245

CQnversion Routines

P 0205

P 0205
P 0208
P 020B
P 0200
P 0210
P 0213
P ,0216
P 0218
P 021A
P 0210
P 021F
P 0221
P 0224
P 0226
P 0229
P 022B
P 022E
P 0230
P 0231
P 0234
P 0236
P 0239
P 023C
P 023F
P 0241
P 0244
P 0247
P 0249
P 024B
'p 02411
P 0250
P 0253
P 0255
P 0256
P 0257

E6
77
EB
E6
E5
56
02
70
24
50
7B
06
7B
A6
6B
76
EB
DE
E5
FO
E4
56
A6
BB
06
06
00
6B
CA
E6
06
8B
OF
AF

7C 20
ED 80
03
7C 2B
ED 7E
7E 7F
CC
EC
7E EC
7E
35
03F4'
30
EC 00
22
7E 01
04
ED 70
70
70 7C
7C OF
7C 09
14
7C 30
03F4 '
7E
OB
DE
7C 2E
03F4'
06

P 0257

P 0257 06
P 025A C8
P 025C

246

025C'
ED

821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
881
882
883
884
885
886
887
888
889
890
891
892
893
894
89'5
896

CONSTANT
boa LEN
:=
boa-SRC
:=
GLOBAL
bcddaso PROCEDURE

R12
R13

I·····························~·······················

Purpose

=

To oonvert a variable length BCD
string to deoimal ASCII. '

Input =

RR14 = address of destination ASCII
'string (in reg/ext/ser memory).
_
R13 = address of souroe BCD
string (in register memory).
R12 = BCD digit ~ount / 2

Output =

ASCII string in designated
destination buffer.
Carry FLAG = 1 if input format error
or serial disabled,
= 0 if no error.
R12, R13, R14, R15 modified.
Input BCD string ummodified.

·····················································1
ENTRY
bod d1:

bod d4:

bod d3:
-

bod_d6:
bod d5:
bod-d2:
END-

ld
tm
jr
ld
ld
and
add
push
sub
pop
jr
oall
jr
op
jr
tm
jr
ino
ld
swap
ld
and
op
jr
add
oall
dec
jr
djnz
ld
oall
jr
sof
ret
boddaso

TEMP_1,1I'-'
@boa SRC,U80
nz,bed d1
TEMP_1-;-1I'+'
TEMP 3,@boa SRC
TEMP-3,U7r
boa LEN,boa LEN
boa-LEN
boa-LEN, TEMP 3
TEM~ 3
ult,bod d2
put des~
o,bed d2
boa L'E:N,IIO
z,bed d6
TEMP j,lIl
nz,bed d3
boa SRl:'
TEMP 2,@boa SRC
TEMP-2
TEMP-l, TEMP 2
TEMP-l,nOr
TEMP-l,1I9
ugt,bod d5
TEMP 1,lJ30
put aest
TEIfP 3
z,bod ,d2
boa LEN, bod d4
TEIfP 1,11'. ,put dest
bod-d4
,

Iminus signl
Isro negative?I
I yesl
I positive signl
lisolate post dec ontl
Itotal digit oountl
Ipre-deo digit ent!
Itotal digit oountl
Iformat errorl
Isign to dest.1
Iserial errorl
lany pre-deo digits?1
Ino. start with '.'1
Ineed ne~t byte?1
Inot yet. I
!update pOinteI'I
Iget next by tel
lisolate digitI
Iverify bodl
Ino goodl
loonvert to ASCIII
Ito destinationl
Idigit oountl
I all donel
Inext digitI
!time for deo. pt.1
Ito destination I
loontinuel
I set error return I

GLOBAL
wrdhaso PROCEDURE

I·····································.···············
Purpose =
To oonvert a binary word to Hex ASCII.
Input =

RR12 = souroe binary word.
RR14 = aadress of destination ASCII
string (in reg/ext/ser memory).

Note =

All other details same as for bythaso.

·······························.·····················1
ENTRY
oall
bythaso
ld
R12,R13
!fall into bythasol
ENDwrdhaso

loonvert R121

P'025C

P 025C BO
P 025E E6·
P 0261 'FO
P 0263 C9
P 0265 56
P 0268 06
P ,026B A6
P 026E 7B
P 0270 DF
p 0271 76
p 02711 EB
P 0276 06
P 0279 D6
.p 027C 7B
p 027E 00
p 0280 EB
p 0282 CF
p 0283 AF
p 02811

7E
7D
EC
7C
7C,
7C
7C
09

02
OF
30
3A

7E 01
OD
7C 07
03FII'
05
7D
DF

898
899
900
901
902
903
9011
905
906
907
908
909
910
911
912
913
9111
915
916
917
918
919
920
921
922
923
9211
925
926
927
928
929
930
931
932
933

CONSTANT
bna SRC
:=
GLOBAL
bythasc PROCEDURE

R12

I·····················································
Purpose =
To convert a 'binary byte to Hex ASCII.
Input =

RR111 = address of destination ASCII
string (1n reg/ext/ser memory).
R12 = Source binary byte.

Output =

ASCII string in designated
destination buffer.
Carry = 1 if error (serial only).
R111, R15 modified.

·····················································1
ENTRY
clr
bca go: ld
bce-g01: SWAP
ld
and
ADD
cp
jr
SCF
'
TM
JR
ADD
skip:
call
jr'
dec
jr
IICF
bca ex: ret
ENDbythasc

MODE
! flag => binary to ASCIII
TEMP 2,112
!look at next nibble I
bna ~RC
TEM" 1,bna SRC
TEMP-1,UOF
lisolate low nibble I
Iconvert to ASCIII
TEMP-1,1I30
TEMP-1,U3A
1>9?1
Inol
ult,Skip
lin case errorl
I input is BCD? I
MODE,'1
Iyes.' error:1
NZ,bca ex
linput
hex. adjustl
TEMP 1-;U07
put dest
Iput byte in destl
lerrorl
c,bea ex
TEMP '2
!loop till donel
nz,bea_s01
Icarry = 0: no errorl
'Idonel

247

P 02811

P
P
P
P
P
P
P
P
P
P
P
P
P

P

P
P
P
P
P

P
P
P

P
P
P
P
P
P
P
P
P

P
P

02811
0286
0288
028B
028E
0290
0293
0295
0298
029B
029C
029F
02A2
02AII
02A6
02A9
02AC
02AE
02BO
02B2
02BII
02B6
02B7
02BA
02BC
02BF
02C1
02C3
02C5
02C8
02Ca
02CC
02CD

248

BO
BO
E5
56
02
211
7B
E5
E6
EE
E5
A6
6B
FO
Ell
06
7B
00
00
EB
8B
OF

76
EB
76
6B
60
60
06
16
CF
AF

EC
ED
EE
7B
FF
7B
37
EE
7E

7B
7F
EF
7B
02

EE 70
EF 00
12
70
70 7C
01l2C'
1E
EF
7E
EB
E2
EC
10
7B
OA
EC
ED
ED
EC

80
80

01
00

935
936
937
938
939
9110
9111
9112
9113
944
9115
9116
947
9118
9119
950
951
952
953
9511
955
956
957
958
959
960
961
962
963
9611
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
9811
985
986
987
988

CONSTANT
::
bcd adr
bcd-cnt
:=
GLOBAL
bcdwrd PROCEDURE

R111
R15

I·····················································
Purpose =
To convert a variable length BCD .
string to a signed binary word. Only
pre-decimal digits are converted.

Input

Output

={

R111 = address of source BCD
string (in register memory).
BCD digit count / 2
R15
RR12 = binary word
Carry FLAG = 1,if input format error
or dest overflow,
= 0 if no error.
R14,R15 modified.
.

·····················································1
ENTRY
·clr
R12
clr
R13
TEMP 1I,@bcd adr
ld
TEMP-II,/lf.7~
and
add
bcd cnt,bcd cnt
bcd-cnt,TEM' II
sub
jr
ult-;bcd w2 TEMP 4,lbcd adr
ld
bcd_w3: ld
TEMP-3,'2 bcd adr .
inc
ld
TEMl' 2,@bcd adr
bcd w1: cp
bcd cnt,'O z,bcd wll
jr
TEMP~.
swap
TEMP-1, TEMP 2
ld
bcd liin
call
c,bcd w2
jr
-bcd cot
dec
dec
TEIfl! 3
nz,bcd w1
jr
bcd_w3jr
bcd wll: scf
R12,U80
tm
nz,bcd w2
jr
bcd_w5: tm
TEMP 1I-;1I~80
z,bca w6
jr
R12 com
com
R13
add
R13,'1
adc
R12,'O
rcf
ret
bcdwrd

linit destination I
iget sign/post length I
lisolate post Tengthl
II bcd digitsT
I' pre-dec digitsl
I format errorl
Iremember signl
Idigits Per by tel
I src addre.ssl
Iget next src by tel
Idigit count = O?!
!conversion complete!
Inext digitI
.
!accumulate in binary!
loverflow or format err!
lupdate digit count!
!next byte?1
Ino. same.1
tnext by tel
I in case!
!result > 15 bits?1
lover flow!
Isource negative?!
!no. done. I
IRR12 two's complementl
!carry = 01

P 02CD

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

02CD
02CF
02D2
02D4
02D7
02D9
02DB
02DE
02E1
02E3
02E5
02E6
02E8
02EA
02ED
02EF
02Fl
02F2
02FII
02F7
02F9
02FB
02FD
02FF

B1
76
6B
117
60
60
06
16
10
10
EE
E9
F9
04
00
B1
EE
FA
E6
70
10
10
E8
F8

P
P
P
P
P
P
P
P
P
P
P
P

0301
0304
0307
0309
030C
030E
0310
0312
0314
0316
0318
0319

E5
15
110
F5
00
FA
50
7B
00
EB
AF

EE
EC
OD
EE
ED
EC
ED
EC
ED
EC
7C
7D
EF
7C
EE
FB
7E
7E
ED
EC
7C
7D
EE
EE
7E
7E
EE
Fl
7E
04
7E
DF

80
80
01
00

7C

OF

7E
7E
EE

990
991
992
993
9911
995
996
997
998
999
1000
1001
1002
1003
10011
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
10211
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043

GLOBAL
wrdbcd

PROCEDURE

I······································~··············

Purpose

To convert a signed binary word
to a variable length BCD string.

Input. =

R111 = address of destination BCD
string (in register memory)
RR12 = source binary word
R15 = BCD digit count / 2

Output =

BCD string in destination buffer
Carry FLAG = 1 if dest overflow
= 0 if no error.
R12,R13,R14,R15 mOdified.

······························.······················1

ENTRY

clr
linit sign/post dec cntl
@bcd adr
lis input word nega~ive?
tm
R12,n80
jr
z,wrd bO
Iset result negativel
@bcd_iidr ,n80
or
com
R13
R12
com
add
R13,'1
IRR12 two's complement I
adc
R12,'0
wrd bO: rlc
R13
Ibit 15 not magnitudel
R12
rlc
inc
bcd adr
lupdate dest pointerl
TEMY_1,
bcd_adr
Id
TEMP 2,bcd cnt Idest byte countl
Id
TEMP:l, bcd:cnt
add
1= bcd end addrl
dec
TEMP 1
@bcd-adr
linitialize destl
wrd bl: clr
inc
bcd adr
bcd:cn~,,.,rd_b1
djnz
Id
Isource bit count I
TEMP 3,'15
TEMP-3
wrd_b3: push
R13 -rlc
1bit 15 to carryl
rlc
R12
Id
bcd adr, TEMP 1 Istart at endl
Id
bcd-cnt,TEMP-2 Idest byte countl
I (dest bcd, string) <-- (dest-bcd string' 2) + carryl
TEMP 3,@bcdadr
wrd b2: Id
TEMP-3,@bcd-adr I' 2 + carryl
adc
TEMP-3
da
@bcd-adr,TEMP 3
Id
bcd adr
- Inext two digits I
dec
bcd-cnt,wrd b2 Iloop for all digits I
djnz
Irestore src bit cntl
TEM'!'" 3
pop
jr
!dest. overflowl
c ,wrd ex
d-ec
TEMP 1
jr
Inextbitl
nz,wrd_b3
wrd ex: ret
ENDwrdbcd

"

249

P 0319

P
P
P
P
P
P
P
P
P
P

0319
031B
0310
031F
0322
0324
0327
0329
032C
032E

BO
BO
BO
06
7B
06'
78
A6
38
26

7E
EC
EO
030A'
28
0400'
22
7C 39
03
7C 37

P
P
P
P
P
P
P
P
P
P
P
P
P

0331
0333
0335
0338
0338
033E
0340
0343'
0346
0349
0348
034C
0340

FO
09
56
56
44
FO
56
56
44
88
CF
AF

EO
70
EO
7C
7C
EC
EC
70
70
04

,

250

FO
OF
EO
FO
OF
EC

1045
1046
,1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
;062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092

GLOBAL
hascwrd PROCEOURE

I···················································.·
Purpose =
To oonvert a variable length Hex
Input =

ASCII string to binary.
'
RR14 = address of source ASCII
string (in reg/ext/ser memory).

Output =

RR12 = binary word (any overflow
high order digits are trunoated
without error).
Carry FLAG = 1 if input error ,
(serial only)
(SER fIg indicates oause)
=-0 if no error
R14, R15 modified

Note =

The ASCII input string prooessing is
terminated with the occurrence of a
non-hex ASCII oharaoter:

·····················································1
ENTRY
olr
TEMP 3
clr
R12 linit outputl
olr
R13
has_ol: oall
get sro
Iget inputl
lerrorl
jr
o,hss ex1
Iverify hex ASCIII
oall
ver aso
lend oonversionl
jr
o,hss ex
cp
TEMP 1,1139
jr
ule,nas c2,'
sub
TEMP 1,1137
!Shift left one nibbTel
IInsert·new nibble in ieast signifioant nibble I
has 02: swap
R13
ld'
TEMP 2,ft13
and
,R13,nFO
and
TEMP 1,nOF
or
R13,TEMP 1
swap
R12
and
R12,IIFO
and
TEMP 2,IIOF
or
R12,~EMP 2
jr
has 01 ~
Iloopl
Ino error I
has ex: rof
has-exl:ret
ENOhasowrd

P 034D

P
P
P
P
P
P
P
P
P
P

034D
034F
0351
0354
0357
0359
035B
035E
0360
0363

CC
DC
04
D6
7B
EC
04
FC
8D

03
08
FD ED
0363'
F3
08
FD EE
03
0284'

1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
i 104
1105
1106
1107
1108
1109
1110
1111
1112
1113
11111
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132

GLOBAL
dascwrd PROCEDURE
! ••••••••• I

•••••••••••••••••••••••••••••••••••••••••••

Purpose

To convert a variable length decimal
ASCII string to signed binary.

Input =

RR14

Output

RR12 = binary word
R8,R9,R10,R11 holds the packed BCD
version of the result.
Carry FLAG = 1 if input error
(serial only)
(SER flg indicates cause)
or dest overflow
= 0 if no error
R14, R15 modified

Note

The ASCII input string processing is
terminated with the occurrence of a
non-decimal ASCII character.
Decimal ASCII string may be no more
than 6 digits in length, else Carry
will be returned.
Post decimal digits are not included
in the binary result.

address of source ASCII
string (in reg/ext/ser memory).

·····················································1
ENTRY
ld
ld
add
call
jr

ld
add
ld
jp

END

dascwrd

R12,H3
R13,II8
R13,RP
dascbcd
c,has ex1
R14,1I"S"
R14,RP
R15,II3
bcdwrd

16 digitsl

I temp addr

=I

! R8 thru R11 I
!convert to bcd!
terror!

!convert to binary!

251

P 0363

1·····*****·*··*·*·.· ............................. *...

P
P
P
P
P
P
P
P
P
P

0363
0365
0367
0369
036A
036C
036E
0370
0372
0375

70
70
B1
DE
CA
B1
50
50
E6
BO

FB
ED
ED
EC
7E
7B

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0377
037A
037C
037F
0382
0384
0387
0389
038C
038E
0391
0393
0395
0398
039A
0390
039F
03A2
03A4
03A7
03AA
03AC
03AF

06
7B
56
76
EB
A6
6B
A6
EB
B7
8B
5B
A6
EB
46
8B
06
7B
46
06
EB
76
6B

03DA'
41
7C 7F
7B 03
OF
7C 2B
EE
7C 20
07
ED 80
E4
OA
7C 2E
05
7B 03
08
0400'
16
7B 01
0463'
09
7B 02
C6

252

1134 CONSTANT
1135 dab LEN
1112
:=
1136 dab-DST
:=
R13
1137 GLOBAL
1138 dascbcd PROCEDURE
1139
1140 Purpose =
To convert a variable length decimal
1141
ASCII string to BCD.
1142
1143 Input =
R13 = address of destination BCD
1144
string (in register memory).
1145
RR14 = address of source ASCII
1146
string (in reg/ext/ser memory).
1147
R12 = BCD digit count / 2
1148
1149 Output
BCD string in designated destination
1150
buffer (any overflow high order
1151
digits are truncated without error).
1152
Carry FLAG = 1 if input error
1153
(serial only)
1154
(SER_flg indicates cause)
,
1155
or overflow
1156
R14, R15 modified.
1157
1158 Note =
The ASCII input string processing is
1159
terminated with the occurrence of a
1160
non-decimal ASCII character .
1161 ••••••••••••••••••••••••••••••••••••••••••••••• * ••••• !
1162 EtlTRY
1163
push
dab LEN
I save!
1164
push
dab-DST
1165 das_g1: clr
ildaii" DST
lini t. destination!
1166
inc
dab "UST
1167
djnz
dab-LEN,das g1
1168
clr
ildao DST
!init.!
1169
pop
dab DST
!restore!
pop
dab-LEN
1170
1171
ld
TEMP 3,111
I for ver asci
1172
clr
TEMP:::4
!bit o => digit seen;
1173
bit 1 => dec pt seen;
1174
bit 7 => overflow I
1175 das_g2: call
get src
!get input byte!
1176
jr
c,dab ex1
!serial error!
1177
and
TEMP 1, U7F
!7-bit ASCII!
1178
tm
TEMP-4,U03
!check status!
1179
jr
nz,das g5
!sign char not valid I
1180
cp
!positive?!
TEMP 1-;-0 '+'
1181
jr
z,das_g2
ryes. no affect!
1182
cp
TEMP 1,11'-'
!negative?!
jr
1183
nz,das g4
!not sign char!
1184
xor
ildab_D"ST,U80. !complement sign!
1185
jr
das g2
!get next input!
1186 das g5: jr
mi,das g6
!dec pt has been seenl
1187 das:::g4: cp
TEMP 1-;-11'.'
lis char dec pt?!
jr
1188
nz,das g6
!nope. !
1189
or
TEMP 4-;-0~03
!dec pt and digit seen!
1190
jr
das_g2
!get next input!
1191 das_g6: call
ver asc
! is bcd digit?!
1192
jr
c,dab_ex
lend conversion.!
1193
or
TEMP 4,U01
!digit seen!
rdl 1194
call
!new digit to dest!
1195
jr
nz,das g7
!overflow!
1196
tm
TEMP 4-;-n02
!post dec digit?!
1197
jr
z,das_g2
Ino. get next input!

EC
ED
ED

01

P
P
P
P

o 3B 1
03B3
03B5
03B8

21 ED
8B C2
46 '7B
8B BD

P 03BA E4
03BD AF
P 03BE

p

7B

80
FC

P 03BE

1198
inc
1199
jr
1200 das_g7: or
1201
jr
1202
1203 dab ex: ld
1204 dab-ex1: ret
1205 ENDdascbcd

@dab DST
das g2
TEMP 4,U80
das_g2

tinc
Iget
I set
Iget

post dec cntl
next input!
overflowl
next inputt

FLAGS,TEMP_4

Icarry

=0

or 11

1207 GLOBAL
1208 wrddasc PROCEDURE
1209
To convert a signed binary word to
1210 Purpose
1211
decimal ASCII
1212
RR12 = source' binary word.
1213 Input =
RR14 = address of dest (in reg/ext/ser
1214
memory) •
1215
121.6
1217 Output
Decimal ASCII in dest buffer.
R8,R9,R10,R11 holds the packed BCD
1218
version of the result.
1219
R12, R13, R14, R15 mod i fied •
1220
1221
1222 ENTRY
push
R14
1223
push
!save dest addr!
R15
1224
ld
1225
R14,#8
R14,RP
1226
add
IR8,9,10 & 11 temp!
!temp byte length!
ld
1227
R15,113
!convert input word!
call
wrdbcd
1228
pop
1229
R15
pop
!restore dest addr!
R14
1230
!length of tempI
ld
R12,#3
1231
R13,#8
ld
1232
add
R13,RP
I addr of tempI
1233
!convert to ASCII!
jp
bcddasc
1234
wrddasc
1235 END

I··············································· .. ····

·····················································1

P
P
P
P
P
P
P
P
P
P
P
P
P

03BE
03CO
03C2
03C4
03C7
03C9
03CC
03CE
03DO
03D2
03D4
03D7
03DA

70
70
EC
04
FC
D6
50
50
CC
DC
04
8D

EE
EF
08
FD EE
03
02CD'
EF
EE
03
08
FD ED
0205'

253

P 03DA

P 03DA CF
P 03DB EE
P 03DC EA
P 03DE FE
P 03DF FA
P 03El 80
P 03E4 70
P 03E6 82
P 03E8 B9
P 03EA 50.
P 03EC AO
P 03EE AF
P 03EF E5
P 03F2 FE
P 03F3 AF
P 03F4
P 03F4

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

03F4
03F5
03F7
03F8
03FA
03FD
03FF
0401
0403
0405
0407
0408
040B
040C
0400

254

EE
EA
FE
FA
80
70
B8
92
50
AO
AF
F5
FE
AF

1237 GLOBAL
Ifor PART II onlyl
1238 get src PROCEDURE
1239 !**T**************************.*********.* •••• *******.
1240 Purpose';:
To get' source byte from
1241
reg/ext/ser memory int? TEMP_l.
1242
-1243 Output =
Carry FLAG = 1 if error (serial)
= 0 if .all ok
1244
TEMP 1 = source byte. '
1245
RR 14-updated.
1246
1247 ****************************~************************!
ENTRY
1248
rcf
!set good return code!
1249
Itest· R14 = 01
inc
R14
1250
djnz
R14,get sl
!src in ext memory!
06
1251
R15
Itest R15 = 01
1252
inc
!src in reg memory!
R15,get s2
OE
1253
djnz
ser
gettsre
in ser memory!
1254
jp
0000*
R11EB
!save
user'sl
1255 get_s1: push
Iget by tel
R11,@RR14
1256
Ide
BE
TEMP 1,Rl1
!move to common I
1257
Id
7C
R11 !restore user'sl
EB
1258
pop
I update src ptr I
EE
RR14
1259
incw
1260
ret
TEMP 1,@R15
Iget by tel
EF 7C 1261 get...;s2: Id
R15 ! update. src ptr I
1262
inc
1263
ret
1264 END
get_src
1265
!for PART I I only!
1266 GLOBAL
PROCEDURE
1267 put dest
1268 I**T****************************'*****'******'********
To store destination byte from TEMP 1
1269 ·Purpose =
into reg/ext/ser memory
1270
1271
RR14. updated.
1272 Output =
1273 *****************************************************1
1274 ENTRY
R14
!test R14 = O!
1275
inc
!dest in ext memoryl
R14,put sl
1276
djnz
06
R15
Itest R15 = 01 .
1277
inc
!dest in reg memory!
R15,put s2
1278
djnz
OE
ser output
!dest in ser memoryl
0000*'
1279
jp
R11Isave user's!
EB
1280 put_s1: push
7C
1281
ld
R11,TEMP 1
@RR14,RlT
BE
1282
Ide
EB
!restore user'sl
1283
pop
R11
RR14
EE
1284
incw
ret
1285
@R15,TEMP
7C EF 1286 put_52: Id
R15
1287
inc
1288
ret
1289 END
put_dest

P 01100

P
P
P
P
P
P
P
P
P
P
P

01100
01110
0413
0415
01118
OlllA
01110
OlllF
01122
01125
01127

56
A6
7B
A6
7B
76
EB
56
A6
7B
A6

7C
7C
16
7C
10
7E
OB
7C
7C
011
7C

7F
30
3A
01
DF
111
117

P 01l2A EF

P 01l2B AF
P 01l2C

P 01l2C

P
P
P
P

l'

P
P
P
P
P
P

P
P
P

P
P
P
P
P
P
P
P

01l2C
01l2F
01132
011311
0436
01138
01l3A
01l3C
01l3E
011110
01142
01144
011116
01148
OllilA
01140
01150
01152
011511
01157
01159
01l5C

56 7,C
A6 7C
BB 20
02 DO
12 CC
7B 27
70 EC
70 ED
02 DO
12 CC
7B 19
02 DO
12 CC
7B13
04 7C
16 EC
7B OB
50 7C
011 7C
50 7C
111 7C
AF

P 01150 50
P 01l5F 50
P 01161 OF
P 01162 AF
P 01163

7C
7C

OF
09

ED
00
ED
EC

1291
1292
1293
-12911
1295
1296
1297
1298
1299
1300
1301
1302
1303
13011
1305
1306
1307
1308
1309
1310
1311
1312
1313
13111
, 1315
1316
1317
1318
1319
1320
1321
1322
13211
1325
1326
1327
1328
1329
1330
1331
1332
1333,
13311
1335
1336
1337
1338
1339
13110
1341
13112
13113
131111
13115
1346
13117
13118
13119
1350
1351
1352
1353
13511
1355
1356
1357
1358
1359
1360
1361

CONSTANT
MODE
:=
char
:=
INTERNAL
ver asc PROCEDURE

TEMP 3
TEMP-l

I··T••••••••••••••••••••••••••••••••••••••••••••••_••••

Purpose

To verify input character as valid
hex or decimal ASCII.

Input =

TEMP 1 = 8-bit input
TEMP:3 = 0 => test for hex,
1 => test for decimal

Output

=

Carry FLAG

=0

if no error
1 if error.

·····················································1
ENTRY
and
cp
jr

cp
jr

tm
jr

and
cp
jr

cp

ver ok:
ver-erc: ccf
ver-err: ret
ENDver asc

17-bit ASCIII
Irange start: '0'1
Ino goodl
char,#'~'+l
Idec range end: '9'1
ult,ver ok
lall's welll
MOOE,#lIdec or hex?!
nz,ver erc
Ino good!
char,#~NOT('a'-'A') linsure upper case!
char,#'A'
Icheck A-F range I
ult,ver err
Ino good!
char,#'~'+l
lend hex range!
char,#~7F

char,#'O'
ult,ver err

Icomplement carry I

INTERNAL
bcd bin PROCEDURE

! ••T ••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To convert next bcd digit to binar'y.

Input =
Output

=

RR12

= RR12

and
cp

TEMP 1,nOF
TEMP-l ,#9 '
ugt,bcd bl
R13,R13R12,R12
c,bcd bl
R12 R13
R13,R13
R12,R12
c ,bcd b2
R13, RT3
R12,R12
c,bcd b2
R13, TEMP
R12,#O c ,bcd b2"
TEMP T
R13,'l'EMP 1
TEMP 1 R12,TEMP_1

• 10 + digit

·····················································1
ENTRY
jr

add
adc
jr

push,
push
add
adc
jr

add
adc
jr

add
adc
jr

pop
add
pop
adc
ret

TEMP 1
bcd b2: pop
TEMP-1
pop
bcd bl: scf
ret
bcd bin
END

., !isolate digit!
!verify validl
lerrorl
12xl
!overflowl

!lIxl
loverflow!
18x!
!overflowl
!8x + d I
!overflowl

110x + dl

Irestore stackl
terror!

255

P 01163

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

01163
01165
01167
0469
01l6C
046F
0472
01175
0478
047B
047D
047F
0118.2
0484
0485

7.0

02
Fl
E5
57
56
115
F5
E4
00
CA
56
50
AF

EC
DC
ED
ED
ED
7C
ED
7C
7D
ED
E8
7C
EC

7D
Fa
OF
7C
ED
7C
OF

P 0485

P
P
P
P
P
P
P
P
P
p
P
P
P

0485
0487
0488
04SA
048D
0490
0493
0496
0499
049C
049E
04AO
04Al

256

70
DE
Fl
E5
57
56
45
F5
E4
CA
50
AF

EC
ED
ED
ED
7C
ED
7C
7E
E9
EC

7E
OF
FO
7C
ED
7C

1363
13611
1365
1366
1367
1368
1369
1370
1371
1372
1373
13711
1375
1376
1377
1378
1379
1380
1381
1382
1383
13811
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
11121
1422
1423
1424
11125
1426
1427
1428

CONSTANT
R12
s len
:=
s-adr
\ :=
R13
INTERNAL
rdl
PROCEDURE
I.··· •• ·······.····.···~····it
Rotate Digit Left
Input

=

Output

.................•.......

R12 = BCD string length
R13 = BCD string address
TEMP_l bit 3-0 = new digit
BCD string rotated left one digit·
new digit inserted in units position.
TEMP 1 bit 3-0 = digit rotated out
of high order digit position
bit 7-11 = 0
Zero FLAG = 1 if TEMP_l <>0
R12, R13 unmodified

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY
push
add
swap
rdl 01:
Id
and
and
or
Id
Id
dec
djnz
and
pop
ret
rdl
END

s len"
s-adr,s len
@s adr TEMP 2,@s adr
@s aar, 0%1='0
TEMP 1,nOF
TEMP-l,@s adr
@s adr, TEMP 1
TEllP_ 1 , TEMP:2
s adr
s-len,rdl 01
Tt:M'P 1,UOF
s len

laddress of units place I
!isolate digit!
!isolate new digitI
Isave new byte!
!back-up pointer!
!loop till donel
fold high order digitI
Irestore R12!

INTERNAL
PROCEDURE
rdr
!** •••••• *** ••• **.*** •••• ** •••••••••••••••• **.**.* ••••
Rotate Digit Right
" Input

=

Output

R12 = BCD string length
R13 = BCD string address
TEMP_l bit 7-11 = new digit
BCD string rotated right one digit;
new digit inserted in high order
position.
R12 unmodified
R13 modified

·····················································1
ENTRY

push
rdr 01: inc
swap
Id
and
and
or
Id
Id
djnz
pop
ret
rdr
END

s len
s-adr
@s adr
,.
TERp 3,@s'adr
@s aar, O%OF
TEMP 1, UFO
TEMP-l,@s adr
@s adr, TEMP 1
TEil'P_1, TEMP:3,
s len,rdr 01
s:len

!isolate digitI
lisolate new digit!
!save new byte!
!loop till done!
!restore R12!

B1t Manipulation Routines
1460 CONSTANT
R12
1461, tjm bits
1462' tjm-mask
R13
1463 GLOBAL
1464 c1b
PROCEDURE
1465 ! •••••••••••••••••••••••••••••••••••••••••••••••••••••
1466 Purpose =
To collect selected bits in a byte
1467
into adjacent bits in the low order
1468
end of the byte. Upper bits in byte
1469
are set to zero.
1470
input byte
1471 Input
R12
1472
R13
mask. Bit = 1 => corresponding
input bit is selected.
1473
1474
R12 = collected bits
1475 Output
1476
For example:
1477 Note =
1478
Input: R12
~(2)01110110
%(2)10000101
R13
1479
1480
1481
Output
R12
~(2)00000010

P 04A 1

1482 •••••••••••••••••••••••••••••••••••••••••••••• ** ••• **!

P 04A1 E6

P
P
P
P

04A4
04A6
QUA8
04AA
P 04AC
P 04AE
P 04BO

BO
90
90
FB
EO
90
10

P 04B2 00
P 04B4 EB
P 04B6 C8
P 04B8 AF
P 04B9

7C
7D
EC
ED
06
EC
EC
7D
7C
FO
7D

08

1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
14911
1495
1496
1497

ENTRY
1d
c1r
next1: rl
r1
jr
rr
r1
r1c
no select:
dec
jr
1d
ret
c1b
END

TEMP 1,118'
TEMP-2
tjm bits
tjm-mask
nc ,no select
tjm blts
tjm-bits
TEMlI" 2
TEMP 1
nz,next1
R12,TEMP_2

!bit countl
!bits collected here!
!bit 7 to bit O!
!bit7 to carry!
!don't use this bit!
!bit 7 to 0 and carry!
!co11ect source bit!
!repeat!

257

P 04B9

P
P
P
P
P

P
P
P
P

04B9
04BC
OUBE
04C1
04C3
04C6
04C8
04CA
04CC

D6
02
16
02
16
C2
AO
C2
E8

P 04CE 30

04A1'
CC
EE 00
FC
EE 00
DE
EE
FE
ED
EE

P 04DO

d errors
Assembly complete

258

1499
1500
1501
1502
1503
1'504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536

CONSTANT
tjm tabh
tjm-tabl
tjm-tab
GLOBAL

tjm

=

R14
R15
RR14

PROCEDURE

1···············*··············***·*··**···*****·*····
Purpose =
To take a jump to a routine address
determined by the state of selected
bits in a source byte. A bit
is 'selected' by a one in the
corresponding position of a mask.
The 'selected' bits are packed into
adjacent bits in the low order end of
the byte. This value is then doubled,
and used as an index into the jump
table.
RR14 = address of jump table in
program memory.
R12 = input data
R13 = mask

Input

··············*······································1
ENTRY
call
add
adc
add
adc
ldc
incw
ldc
Id
jp
END
tjm
END PART I

clb
I collect selected bits I
tjm bits,tjm bits Icollected bits • 21
tjm-tabh,HO lin case carry I
tjm-tabl,tjm bits
tjm-tabh,HO Itjm tab points to ••• 1
tjm-mask,@tjm tab 1.7.table entryl
tjm-tab
,
tjm-tabl,@tjm tab Iget table entry ••. 1
tjm:tabh,tjm_mask I .•. into tjm_tabl'
Ibyel

ROMLESS Z8 SUBROUTINE LIBRARY PART II
Z8ASM
LOC

3.02
OBJ CODE

STMT SOURCE STATEMENT
1

2

3 PART_II MODULE
4

5
6 !' ROMLESS Z8'

7 I

9
10
11
12
13
14
15
16
17
18
19
20
21

SUBROUTINE LIBRARY

PART II

CONSTANT
IRegister Usage!
RAM START

·-

~7F

P3M save
TEMP 3
TEMP-2
TEMP-1
TEMP-4

·: -=

·-

RAM START
P3M - save-1
TEM'P 3-1
TEMP-2-1
TEMP-1-1

·· --

IThe following registers are modified/referenced
by the Serial Routines ONLY. They are
available as general registers to the user
23 who does not intend to make use of the
24 Serial Routines!
25
26 SER char
.TEMP 4-1
._
SER char-1
27 SER-tmp2
28 SER-tmp1
._
SER-tmp2-1
._
SER-tmp1-1
29 SER-put
._
SER-put-1
30 SER-len
._
SER-len-2
31 SER-buf
32 SER-imr
.SER-buf~1
._
SER-imr-1
33 SER-cfg
34 I Serial Configuration Data
=1 => odd parity on
35 bit 7
36 bit 6 : =1 => even parity on
37 (bit 6,7 = .11 => undefined)
38 bit 5
undefined
undefined
39 bit 4
40 bit 3
=1 => input editting on
41 bit 2
=1 => auto line feed enabled
42 bit 1
=1 => BREAK detection enabled
43 bit 0
=1 => input echo on
44 I
45 op
';80
:=
46 ep
';40
:=
47 ie
~08
.1\8 al
~04
:=
49 be
~02
.50 ec
~01
.51 SER get
SER cfg-1
SER- get-1
52 SER-flg
:=
53 !Serial Status Flags
54 bit 7
=1 => serial I/O disabled
undefined
55 bit 6
undefined
56 bit 5
=1 => parity error
5
43
587 bit
bit
=1 => BREAK detected
=1 => input buffer overflow
59 bit 2
60 bit 1
=1 => input buffer not empty
.1 => input buffer full
61 'bit 0
62 !
63 sd
~80
64 pe
~10
65 bd
~08
66 bo
~04
$02
67 bne
68 bf
~01
69
22

·

259

70
71
72
73
711
75
76
77
78
79
80
81
82
83
811
85
86
87
88
89
90
91
92
93
911
95
96
97
98
99
100
101
102
103
1011
105
106
107
108
109
110
111
112
113
,1111
115
116
117
118
119
120
121
122
123
1211
125
l26
127
128
129
130
131
132
, 133
1311
135

260

RAM TMR
SERl time
SERhtime

SER flg-l
SERltime-1

:=

:=

IThe following registers are modified/referenced
by the Timer/Counter Routines ONLY. They are
available as general registers to the user
who does not intend to make use of the
Timer/Counter Routinesl
TOO tic
TOD-imr
TOD-hr
TOD-min
TOD-sec
TOD-tt
PLS""'1
PLS-tmr
PLS-2
RAM END
STA'eK

:=

:=
:=
:=

: =.
:=
:=

:=

:=

I

RAM TMR-2
TOD-Uc-1
TOD-imr-1
TODnr-l
TOD-min-l
TOD-sec-l
'TOD-tt-l
PLS-1-1
PLS::::tmr-l
PLS 2

RA~END

IEquivalent working register equates
for above register layoutl
Iregister file S70 - J7FI
RAM_STARTr
:=
S70
rP3Msave
rTEMP 3
rTEMP-2
rTEMP-l
rrTEMP 1
rTEMP lh
rTEMP-n
rTEMP-1I
rSERcnar
rSERtmp2'
rSERtmp1
rrSERtmp
rSERtmpl
r~ERtmph

rSERput
rSERlen
rrSERbuf
rSERbufh
rSERbufl
rSERimr
rSERcfg
rSERget
rSERflg

:=
:=
:=

:=
:=

:=
:=
:=

:=
:=
:=
:=

:=
:=
:=
:=

:=
:=

:=

:=
::

I for SRPI

R15
R111
R13
R12
RR12
R12
R13
Rl1
Rl0
R9
R8
RR8
R9
R8
R7
R6
RRII
HII
R5
R3
R2
Rl
RO

Iregister file S60 - S6F1
, 160
RAM TMRr
:=
rTO'Dtic
R13
:=
R12
rTODimr
:=
rTODhr
R11
:=
rTODmin
R10
:=
rTODsec
:=
R9
'R8
rTODtt
:=
rPLS 1
R7
:=
rPLStmr
R6
:=
rPLS_2
:=
R5

I for SRPI

Serial Routines
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195'
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216

P 0000

P
P
P
P
P
P
P
P
P'

0000
0001
0003
0005
0007
0009
OOOB
0000
OOOF

EE
EA
EC
FC
BC
DC
C3
DA
56

CONSTANT
si PTR
sCTMPl
sCTMP2
GLO'BAL
ser inlt

RR14
R11
R13

PROCEDURE

I··T••••••••.••••••••••••••••••••••••••••••••••••••••••

serial initialize
Purpose =

To initialize the serial channel and ,
RAM flags for serial I/O. Serial
input occurs under interrupt control.
Serial output occurs in a ,polled mode.

Input

RR14 = address of parameter list in
program memory (if R14 = 0,
use defaults):
byte = Serial Configuration Data
(see definition of SER cfg) ,
byte = IMR ~ask for nestab1e
interrupts
word = address of c,ircu1ar input
buffer (in reg/ext memory)
byte
Length of input buffer
byte
Baud rate counter value
byte = Baud rate presca1er value
(unshHted)

Output =

Serial I/O operations initialized.
R11; R12, R13, R14, R15 modified.

Note' =

Defaults:
Input echo on
Input editting oh
BREAK detection enabled
No parity
Au~o line feed on
Input Buffer Address = SER char
Input buffer length = 1 byte
Baud Rate = 9600 (assuming
XTAL = 7.3728 MHz)
The instruction at ~0809 must result
in a jump to the jump table entry for
ser _input.
If BREAK detection is disabled, and a
BREAK occurs, it will be received as a
continuous string of null characters.
The parameter list is not referenced'
following initialization.

·····················································1

217 ENTRY

04
00'
51'
72
05
BE
FC
73 F7

=

218
219
220
221
222 si 1:
223
2~4 si 2:
225 '
226
227

inc
djnz
1d
,1d
1d
1d
1dci
djnz
and

R14
luse defaults?!
R14,si 1
!no. given by ca11er.1
R14,IHI ser def laddress of defau1t ••• 1
R15,ILO ser-def I ••• parameter list. I
si TMP1, IIsEli cfg
si-TMP2,'5 .
@sT TMP1,@si PTR Iget initia1ization ••• 1
si TMP2,si 2I ••• parametersl
SER_imr,'~F7
linsure no se1f-nestingl

261

P
P
P
P
P
P
P

0012 56
0015 B8
0017 56
001A, 46
0010 56
0020 44
0023'E4

P 0026 BC
P, 0028 C2
P 002A C3
P 002C C2
P 002E 06
, P 0031 C9
P 0033 09,
P003590
P 0037 OF
P 0038 10
P 003A B9
P
P
P
P

003C8F
0030 BO
003F BO
0041 BO

P
P
P
P

0043
0046
0049
004C

F1
72
EB
EB
7F
EB
7F

FC
80
40
3F
7F
F7

F4
DE
BE
BE
0000·
6E
6F
EB
EB
F5
71

77

70

56
56
46
9F

FA
FB
FB

E7
EF
08

P 0040 46
P 0050 AF
P 0051

F1

03

P 0051 OF 00
P 0053 007A 01
P 0056 02 03

228 11n1t1alize Port 3 Hode Reg1ster for ser1al 1/01
THR,H$FC
!d1sable TO!
AND
229
ld
s1 THP1, SER ofg !oonf1gurat1on data!
230
s1-TMP1,#$80
lodd par1ty seleot!
AND
231
OR
s1-TMP1,#$40
IP30/7 = S1n/Sout!
232
AND
P3R
save,H$3F
!mask
off old sett1ngs!
233
OR
P3~save,s1 TMP1 !new seleot1onl
234
LD
P3H~P3M_savi
Ito wr1te-only register!,
235
236
237 ! 1nithlize TOI
ld
s1 TMP1,IITo
238
s1-tMP2,@s1 PTR Isave oounter!
ldo
239
240
ld01
@sI TMP1,@sI PTR !1n1t oounter!
s1 TMP1,@s1 ~TR !get presoalerl
241
ldo
242
mult1ply
!TO x PREO!
oall
SERht1me,R12
!save for BREAK ••• I
ld
243
244
ld .
SERlt1me,R13
1 ••• deteot1on
I
s.1 TMP1
! SHL 11
rl
245
246
sof
!oontinuous mode!
!\SHL 2!
rlo
s1 TMP1
247
248
ld
PRl:0,s1 TMP1
\249 ! 1n1t1alize RAM flags and po1nters!
01
!disable 1nterrupts!
250
!input buffer ••• !
SER get
olr
251
SER-put
olr
252
! ••. emptyl
Ino errors!
olr
SER:flg
253
254
255 !1n1t1al1ze 1nterrupts!
AND
IRQ,#$E7
!olear IRQ3 & 4!
256
!d1sable IRQ4 (xmt)1
and
IMR,#$EF
257
or
IMR,#$08
tenable IRQ3 (rov)!
258
.EI
259
260 !gol
261
or
!load/enable TO!
THR,n03
ret'
262
263 END
ser:...1n1t
264
265
266
267 !Defaults for serial initialization I
268
. 269 ser def RECORD [ofg_, imr_
BYTE
270
271
272
273

262

buf
len , otr_, pre_

WORD
BYTE]

275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320

P 0058

31)1

P 0058 BO
p

P
P
p

P
P

p

P
P

005A
005C
005E
0060
0063
0065
0068
006A
006D

70
70
70
D6
7B
76
6B
76
6B

7E
EE
EF
ED
0170'
118
72 CO
08
7C 80
03

CONSTANT
rli len
GLOBAL
ser r1in

:=

R13

PROCEDURE
I··T .................................................
.

read line
Purpose =

To return input from serial channel
up to 'carriage return' character or
maximum length requested or BREAK.

Input

RR14
R13

= address of destination
(in reg/ext memory)
= maximum length

buffer

Output

Input characters is destination buffer.
RR14 = unmodified
R13 = length returned
Carry Flag = 1 if any error,
= 0 if n9 error.
R12 indicates read status

Note

1. Return will be made to the calling
program only after the requisite
characters have been received from
the serial line.
2. If input editting is enabled, a
'backspace' character will cause
the previous character (if any) in the
the destination buffer to be deleted;
a 'delete' character will cause all
previous characters (if any) in the
destination buffer to be deleted.
3. If parit~ (odd or even) is enabled,
the parity error flag (R14) will be set
if any character returned had a parity
error. (Bit 7 of each character may
then be examined if it is desirable to
know which character(s) had the error).
4. The status flags 'BREAK detected',
'parity error', and 'input buffer
overflow' will be returned
as part of R12, but will be cleared in
SER stat.

322
5. The staus flags: 'input buffer full'
323
and '.input buffer not empty' will be
3:14
updated in SER stat.
325
326 ..............................T······················I
327 ENTRY
clr
!f1ag => read line!
TEMP_3
328
329 ser read:
push
Isave original ••. 1
R111
330
!. .. dest. pointer!
push
R15
331
I ••• and length I
push
rli len
332
Iget input character I
ser-get
333 rli_ 4: call
jr
c ,rli 3
lerrorl
334
SER c?g, flop LOR ep Iparity enabled?!
tm
335
jr
Inol
z,rIi
1
336
!parity error?!
tm
TEMP J,n80
337
jr
z,rlI_1
Inol
338

263

P
P
P
P
P
P
P

006F
0072
0075
0078
007A
007D
0080

46
06
A6
EB
56
76
6B

70 10
0000*
7E 00
31
7C 7F
72 08
21

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0082
0085
0087
008A
008C
008E
0090
0093
0095
0096
0099
009A
009C
009E
OOA 1

A6
6B
A6
EB
50
70
A4
6B
DE
26
EE
EA
8B
36
8B

7C
3E
7C
17
7C
7C
ED
30

P
P
P
P
P
P
P
P
P
P

00A3
00A5
00A8
OOAA
OOAB
OOAD
OOAF
00B2
00B4
00B6

00
A6
6B
DE
DA
50
24
08
C8
56

P
P
P
P
P
P
P

0' read absolute!
ld
TEMP 3,01
jr
ser read
END
ser rabs

P 0002

,I'

E4
70
54
9F
70
31
A8·
76
6B
BO
76
6B
9C
A2
EB
76
EB

FO
70
FO
E2
2F
E9
E2
02
80
A9
22
E8
10

P OOF8 46
P OOFB 76
P OOFE 6B

EO
03
FB

P 0100 70

6E
6F
35
FE
6E

P

P
P
P
P
P
P

P
P
P
P
P
P
P
P
P
P

0002
0005
0007
DaDA
OOOB
0000
OOOF
OOE 1
00E4
00E6
00E8
OOEB
OOEO
OOEF
00F1
00F3
00F6

P 0102 70

P 0104 8C
P 0106 8A
P 0108 80

03
FB
73

78
FB

02
80

01
08
01

406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469

GLOBAL
ser input

PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Interrupt service - Serial Input
Purpose =

To service IRQ3 by inputting current
character into next available position
in circular buffer.

Input =

None.

Output

New character inserted in buffer.
SER stat, SER_put updated.

Note

1. If even parity enabled, the software
replaces the eigth data bit with a
parity error flag.
2. If BREAK detection is enabled, and
the received character is null,
the serial input line is monitored to
detect a potential BREAK condition.
BREAK is defined as a zero start bit
followed by 8 zero data bits and a
zero stop bit.
3. If 'buffer full' on entry, 'input
buffer overflow' is flagged.
4. If input echo is on, the character is
.immediately sent to the output serial
channel.
5. IMR is modified to allow selected
nested interrupts (see ser initIo

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY
ld
push
and
ei
push
srp
ld
tm
jr
clr
tm
jr
ld

SER tmp1,1003
imrimr,SER_imr

!read stop bit levell
! save entry lmr I
! allow nesting!

rp
!save user's!
IIRAM STARTr
rSERchar,SIO
!capture inputl
!break detect enabled?!
r SERc fg ,llbe
!nope.1
z,ser 30
r SERtiiip2
r SERc fg ,lIop
!odd parity enabled?!
!no .1
z,ser 23
rSERtiiip2, U80
rSERchar,rSERtmp2 !8 received bits = O?!
ne,ser 30
!no!
rSERtmp1,'1
!test stop bit!
jr
nZ,ser 30
!not BREAK I
lis BREAK. Wait for markingl
or
rSERflg,lIbd
!set BREAK flag!
ser 24: tm
~03,1I1
!marking yet?1
jr
z,ser 24
!not yetI
!wait 1 char time to 1'lush receive shift register I
push
SERhtime
push
SERI time
! save PREO x TO!
in loop: ld
rSERtmp1,1I53
lpl:
djnz
rSERtmp1,lp1
Idelay 640 cycles!
decw
SERhtime

265

P 010A EB

FS

P
P
P
P

010C
010E
0110
0113

50
50
56
8B

6F
6E
FA
49

P 0115
p 0118
P 011A
P 0110
P 011F
P 0121
P 0124
P 0126
P 0129
p 012C

76
EB
76
6B
A9
66
EB
56
76
6B

EO
4A
E2
OA
FO
FA
FB
FA
E2
14

P
P
P
P
P
P
P
P
P
P
P
P
P

8C
BO
CO
16
SA
56
B2
CO
CO
88
98
02
BE
SA
F3
46
7E
A2
EB
BO
A2
EB
46,
50
8F
50
BF

07
E9
EA
E9
F9
E9
A9
EA
EA
E4
E5
97

p

P
P
P
P
P
P
P

p

P
P
P
P
P

012E
0130
0132
0134
0137
0139
013e
013E
0140
0142
0144
0146
0148
0149
014B
0140
0150
0151
0153
0155
0157
0159
o15B
015E
0160
0161
0163

lE
9A
EO
76
02
E7
71
03
EO
FO

F7
01
01
10
EF
40

00
01

02

01

FB

P 0164 46
p 0167 8B

EO
F5

04

p

E8
A8
DO

00

0169 16
P 016C 92
P 016E 8B
P 0170

266

470
471
472
473
474
475
476
477
478
479
4S0
481
4S2
4113
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
50S
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523

jr

nz ,in_loop

pop
pop
and
jr

SERltime
SERhtime
IRQ,IILNOT %08
ser_i5

!delay (128xl0xPREOxTO)1
I
----------------1
2.
!restore PREO x TO!
!clear int reql
!bye!

ser 30: tm
rSERflg,lIbf
! bu(fer full?!
jr
nz,ser 11
I yes .overflowl
tm
rSERcfg, flec
!echo on?!
Ino'!
jr
z,ser iO
ld
SIO,r"SERchar
lechol
ser i6: tcm
IRQ,Ul0
! poll I
jr
nz,ser i6
! loopl
!clear ir-q bit!
IRQ,IILNOT %10
and
ser iO: tm
rSERcfg ,lIep
I even parity? I
jr
z,ser 22
!no parity!
!calculat.e. parity error flagl
ld
rSERtmpl,1I7
clr
rSERtmp2
!count l' shere!
ser 20: rrc
rSERchar
!bit to carry!
ad'c
rSERtmp2,1I0
lupdate l's countl
djnz
rSERtmpl ,ser _20 !loop till done!
and
rSERtmp2,lIl
11 's count even or odd?!
rSERchar,rSERtmp2
xor
rrc
rSERchar
!parity error flag .•• I
rrc
rSERchar
I. .. to bit 7!
ser_22: ld
rSERtmph,rSERbufh
rSERtmpl,rSERbufl
ld
add
r SERtmpl , r SERput Inext char address!
rSERtmph
inc
!in external memory?1
djnz
rSERtmph,ser 12 lyes.1
@rSERtmpl,rStRchar Istore char in buff
ld
ser i3: or
rSERflg,flbne
Ibuffer not emptyl
inc
rSERput
lupdate put ptr!
cp
rSERput,rSERlen !wrap-around?!
jr
ne,ser i4
!no!
clr
rSERput
!set to start!
ser i4: cp
rSERput,rSERget-lif equal, then full !
jr
ne,ser i5
or
rSERflg,lIbf
ser_i5: pop
rp
Irestore user's!
di
pop
imr
!restore entry imr!
iret
,
ser i 1 : or
jr

rSERflg ,flbo
ser_i5

!buffer overflowl

r SE Rtmph ,110
ser i2: adc
ide
@rrSERtmp,rSERchar I store in bufl
jr
ser_i 3
END
ser_input

P 0170

P
P
P
P

0170
0172
01711
0175

70
31
DF
76

FD
70

P
P
P
P
P
P
P
P
P

0178
017A
017D
017F
0181
0183
01811
0186
0187

EB
76
6B
D8
C8
8F
02
CE
CA

211
EO
F6
E5
Ell

P
P
P
P
P
P
P
P
P
P
P
P
P

0189
018B
018E
OlaF
0191
0193
0195
0197
0199
019C
019D
019E
01AO

E3
56
lE
A2
EB
BO
A2
EB
56
CF
9F
50
AF

CD
EO

FE

16
02
El
17
03
EQ

FD

P
P
P
P

01Al 16
01AlI 82
01A6 8B
01A8

EC
CC
E3

EO

8C

02

Dl
18

FD
00

525
526
527
528
529
530
531
532
533
5311
535
536
537
538
539
5110
5111
5112
5113
51111
5115
5116
5117
5118
5119
550
551
552
553
5511
555
556
557
558
559
560
561
562
563
5611
565
566
567
568
569
570
571
572
573
5711
575
576
577

GLOBAL
I for PART II
ser get PROCEDURE

! •• T ••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

To return one serial input character.

Input =

None.

Output =

Carry FLAG

Note =

This routine will not return control
until a character is available in the
input buffer or an error is detected.

.

if BREAK detected or
serial not enabled
or buffer overflow
= 0 otherwise
TEMP 1 = character

·····················*·*·····························1
ENTRY

push
srp
scf
ser_g1: tm

jr
tm
jr
Id
Id
di
add
inc
djnz
Id
ser_gll: and
inc
cp
jr
clr
ser_g2: cp
jr
and
ser_g5: rcf
ei
ser_g6: pop
ret

rp
IIRAM STARTr

Isave caller's rp!
!point to subr. RAM!
lin case error!
rSERflg, #sd LOR bd LOR bo
!serial disabled or
BREAK detected or
buffer overflow?!
!yes.1
nz,ser_g6
rSERflg ,#bne
I buffer not empty? I
z,ser g1
lempty. waitl
rTEMP-l1,rSERbufl
rTEMP:1h,rSERbufh
!prevent IRQ3 conflict!
rTEMP 11 ,rSERget !next char address!
rTEMP-lh
!input buffer in .•. 1
rTEMP:lh,ser_g3 I ..• external memoryl
! ••. register memory!
rTEMP 1,@rTEMP 11 Iget chari
rSERfIg,#LNOT bf !buffer not full!
r SERget
! update get po'inter I
rSERget, rSERlen !wrap-around?1
ne,ser_g2
!no. !
!yes. set to startl
rSERget
rSERget,rSERput Ibuffer empty if get .•• 1
ne,ser g5
I •.. and put =!
rSERflg,ULNOT bne !buffer empty now!
!set 'good return!
Ire-enable interrupts!
rp
Irestore caller's rp!

ser_g3: adc
! rrTEMPl has char addr!
rTEMP lh, 110
lde
rTEMP:l,@rrTEMP_' !get Char!
jr
ser _gll
!clean up!
ser_get
END

267

P oU8

P 01A8 BO
P 01AA 80
P 01AC EB

FO
EE
FA

P 01AE 80
P 01Bl

0238',

P 01Bl

P 01Bl 8F
P
P
P
P
P
P

01B2
01B4
01B6
01B9
01BA
01BB

268

BO
BO
56
9F
AF

71
77
70

80

579
580
581
582
583
584
585
586
587
588,
.589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613

GLOBAL
ser break

615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640

GLOBAL
ser flush

PROCEDURE

I··T••••••••••••••••••••••••••••••••••••••••••••••••••

break transmission
Purpose =
Input =

'To transmit BREAK on the serial line.
I

RR14 = break length

Output =
Note =

BREAK is defined as:
serial out (P37) = 0 tor
2
x 28 cycles/loop x RR14 loops
XTAL
RR14 should yield at least 1 bit time
so that the last 'clr SIO' will
have been preceded by at least 1 bit
time of spacing. Therefore, RRi4 should
be greater than or equal to
4 x 16 x PREO x TO
28

................................ ··.··················1
E.NTRY
ser_b1:

clr
SIO
decw
RR14
jr
nz,ser bl
!wait 'for last null to~e fully transmitted I
jp
ser 01
END
ser break PROCEDURE

I··T•••••••••••••••••••••••••••••••••••••••••••••• '••••

input flush
Purpose =

To flush (clear) the serial input
buffer of characters.

Input =

None

Output =

Empty input buffer.

Note =

This routine might be useful to clear
all past 1aput after a BREAK has been
detected on the line.

···.·······················~······,··················I
ENTRY
di
Idisable interrupts I
I(to avoid collision with
serial input) t
clr
SER get Ibuffer start I
clr
SER-put 1= buffer endl
and
SER-flg,IS80
Iclear statusl
ei
Ire-enable interrupts I
ret
END
ser flush

P 01BB

P 01BB BO
P 01BD DF
P 01BE 76
P 01C1 EB
P 01C3 70
P 01C5 D6
P 01C8 D6
P 01CB'7B
P 01CD A6
P 01DO EB
P 01D2 56
P 01D5 A6
P 01DB EB
P 01DA 00
P 01DC 76
P 01DF 6B
P 01E1 E6
P 01E4 D6
P 01E7 8B
P 01E9 DA
P 01EB 50
P 01ED 24
P 01FO D8
P,01F2 CF
P 01F3 AF
P 01F4

7E
70 80
30
ED
0000·
020B'
1E
7E 00
17
7C 7F
7C OD
OF
ED
72 04
OA
7C OA
020B'
02
DA
7C
ED ' 7C
7C

642
6113
6411
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
6811
685
686
687
688
689
690
691
692
693
694
695
696

CONSTANT
wli len
GLOBAL
ser wlin .

:=

R13

PROCEDURE

I··y··················································

write line

Purpose =

To output a character string to serial
line, ending with either a 'carriage
return' character or the maximum length
specified.

Input =

RR14 = address of source buffer
(in reg/ext memory)
R13 = length

Output =

RR14 = updated
Carry Flag = 1 if serial not enabled,
= 0 if no error.
R13 = 1 bytes output (not including
auto line feed)

Note =

If auto line feed is enabled, a
line feed character will be output
following each carriage return
(ser wlin only).

....................T································I

ENTRY

write:

wli 4:

wli 5:
wlC2:

wli 1:
END-

=> write line!

clr

Iflag

scf
SER flg; IIsd
tm
jr
nz,wli 1
wli len
push
get-src
call
ser-output
call
jr
c ,wii 2
cp
TEI1P 1,10
jr
nz,wii 5
I
and
TEMP 1;/lS7F
TEMP-1, /lSOD
cp
jr
nz,wI"i 5
dec
wli len
SER-c fg , llal
tm
jr
z,wli 2
TEMP .,., /lSOA
ld
call
ser 'Output
wli-2
jr
wli-len,wli 4
djnz
TEMlf 1
pop
TEMP-1,wli len
sub
wli_I"en,TElJP_1
ld
rcf
ret
ser wlin

lin case errorl
Iserial disabled?1
Iyes. errorl
Iwrite the character I
Iserial disabled!
!write line?!
! no, absolute. I
Imask off parityl
lline done?1
!yes.1
lauto line feed?1
Idisabled!
!output line feed!
Iloopl
loriginal length I
Ireturn output countl
Ino errorl

269

P 01FII

P
P
P
P

01FII E6
01F7 8B
01F9
01F9 ,

7E
CII

01

698
699
700
701
702
703
7011
705
706
707
708
709
710
711
712
713
715
716
717
718
719
720
721
722
723
7211
725

726

GLOBAL
ser wabs

PROCEDURE

I •• T •••••••••••••••••••••••••••••••••••••••••.•••••••••

write absolute
Purpose =

To output a oharaoter string to serial
line for the length speoified. (Output
is not terminated with the output of
a 'oarriage return').

Note =

All other details are as for 'ser wlin' •

•••••••••••••••••••••• ,•••••••••••••••••••••••••••T •••

I

ENTRY

ld
TE~P 3,#1
jr
write
END
ser_wabs
ser wbyt
PROCEDURE

I··T................................................. .

write byte
Purpose =

To output a given ohar,aoter to the
serial line. If the oharaoter is a
oarriage r~turn and auto line feed
is enabled, a line feed will be output
as well.

Input =

R12 = oharaoter to output

727 Note =
,Equivalent to ser wlin with length
728
729 ENTRY
Id
TEMP 1,R12
730
,oall
ser output
731
!output itl
tm
SER-ofg,lal
lauto line feed?1
732
jr
z,ser 05
Inot enabled I
733
op
R12,#IOD
lohar = oar. ret?1
734
,Inopel
jr
nZ,ser 05
735
loutput line feedl
Id
TEMP 1~#SOA
736
737 Ifall into ser outpu~!
ser_wbyt
738 END

= 1.

.................................T···················I

P
P
P
P
P
P
P

01F9
01FB
01FE
0201
0203
0206
0208

P 020B

270

C9
06
76
6B
A6
EB
E6

7C
020B'
72 Oil
3E
EC 00
39
7C OA

P 020B

P
P
P
P
P

020B
020C
020F
0211
0214

DF
76
EB
76
6B

'p

0216
02111
0.21B
021D
021F
0222
0224
0226
0229
022C
022F
0231
0233
0235
0238
023B
023D
0240
0241
0242

70
E6
BO
CO
16
00
EB
56
56
44
CO
CO
50
E4
66
EB
56
CF
AF

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

70
30
72
1F
7E
7E
7D
7C
7D
7E
F7
7D
7C
7D
7C
7C
7E
7C
FA
FB
FA

80
40

07
00
01
FE
7C
FO
10
EF

P 0242

0242 8F
r 0243 46

70

80

r 0246 56

F1

FC

r (1249 56

FB

E7

I'024C 56

7F

BF

I' 024F E4
I' l'.'<;2 9F
\' O.~'i 3 AF

7F

F7

P

\' l'.''i4

740
741
742
743
7411
745
746
747
748
749
750
751
752
753
7511
755
756
757
758
759
760
761
762
763
7611
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779'
780
781
782
783
784
7.85

GLOBAL
ser output

787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811

GLOBAL
ser disable

I for PART II
PROCEDURE

I··T••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To output one oharacter to the serial
line.

Input =

TEMP 1 = character

Output

Carry FLAG = 1 if serial disabled
= 0 otherwise.

Note

1. If even parity is enabled, the eigth
data bit is modified prior to character
output to SIO.
2. IRQ4 is polled to wait for completion
of character transmission before control
returns to the calling program.

·····.··
..... · .. ·.··.································1
ENTRY

scf
tm
SER flg,#sd
jr
nz,ser 05
tm
SER_cfg"ep
jr
z ser 02
Icalculate parity/
push
TEMP 3
ld
TEMP-3,#7
olr
TEMP-2
ser_04: rrc
TEMP-1
adc
TEMP-2,HO
dec
TEMP-3
jr
nz,ser 04
and
TEMP 2~'01
and
TEMP-1,H~FE
or
TEMP-1,TEMP 2
rrc
TEM!'1
rrc
TEMP-1
pop
TEMP-3
ser 02: ld
SIO,TEMP 1
ser-01: tcm,
IRQ,#~10jr
nz,ser 01
and
IRQ,#~~F
rcf
ser 05: ret
ENDser_output

lin case errorl
Iserial disabled?1
Iyes. errorl
leven parity enabled?!
!no. jus~ output I

Icharacter bit to carryl
Icount 1'sl
Inext bitl
11's count odd/evenl
!parity bit in DOl
Iparity bit in D7!
!output character I
!oheck IRQ41
Iwait for completel
Iclear IRQ4!
I all okl

PROCEDURE

I·····················································
d'isable
Purpose =

To disable serial 1/0

Input =

None.

~perations.

Output =
Serial' 1/0 disabled.
.
••••••••••••••••••••••••••••••••••••••••••••••••••••• !
ENTRY

di
or
and
and
and

END

lavoid IRQ3 conflictl
SER flg,Hsd
Iset serial disabledl
TMR,#~FC

Idisable TOI
IMR,'~E7

Idisable IRQ3,41
P3M save,#~BF
IP30/7 normal ilo pins!
P3M,P3M save
-Ire-enable interrupts I

ld
ei
ret
ser disable

271

Tiller/Counter Routines "84,0
8111
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864

P 0254

865

P
P
P
P
P
P

0254
0256
0258
025A
025D
0260

DC
C3
C3
E6
8D

6C
DE
DE
7B 6C
02B2'

CONSTANT
R13
TMP
:=
PTR
RR14
R14
PTRh
:=
GLOBAL
t~d i
PROCEDURE

I··T••••••••••••••••••••••••••••••••••••••••••••••••••

time of day

initialize

Purpose =

To initialize TO or T1 to function as
a time of day clock.

Input =

RR14 = address'of parameter list in
program memory:
byte = IMR mask'for nestable
interrupts
byte = # of ciock ticks per second
byte = counter # : = SF4 => TO
= SF2 => T1
byte = Counter value
byte = Prescaler value (unshifted)
TOD hr, TOD min, TOD sec, TOD tt
inItialized to the starting time of
hours, minutes, seconds, and ticks
respeotively.

866
867 Output =
Selected timer is loaded and
enabled; corresponding interrupt
868
is enabled.
869
R13, R14, R15 mOdified.
870
871
The
cntt and prescaler values provided
872 Note =
are- those values which will generate an
873
87,4
interrupt (tick) the designated # of
times per second.
875
876
For example:
877
for XTAL = 8 MHZ, ontr = 250 and
878
prescaler = 40 yield a .01 sec interval;
879
the-2nd byte of the parameter list
880
should = 100 •
'
881
882
For TO the instruotion at S080C or
883
for T1 the instruction at S080F must
884
result in'a jump'to the jump table entry
885
for 'tod'.
886
887
The
parameter list is not referenced
888
following initialization.
889
890
····························~························I
NTRY'
'
891 E
TMP,ITOD imr
ld
892
limr maskl
@TMP,@PTlf
ldci
893
Itic:ka/secondl
@TMP,@PTR
ldci
894
TEMP
4,ITOD
imr
ld
895
pre_otr
jp
Ictr & prescalerl
896
tod_i
END

8n

\

~72

P 026Q

p 0260 70
p 0262 54

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0265
0266
0268
026A
026B
026D
026F
0271
0272
0275
0277
0279
027A
027D
027F
028"1

9F
70
31
8E
A2
EB
BO
9E
A6
EB
BO
AE
A6
EB
BO
BE

P
P
P
P
P

0282
0284
0285
0287
0288

50
8F
50
BF

FB
6C

FB

FD
60
80
13
E8
E9
OB
E9

3C

EA
03
EA

3C

FD
FB

899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930

GLOBAL
tod

PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Interrupt service - time of day
Purpose

=

To update the time of day clock •

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY

push
and
ei
push
srp
inc
cp
jr
clr
inc
cp
jr
clr
inc
cp
jr
clr
inc

tod ex: pop
di
pop
iret
END
tod

imr
imr,TOD_imr
rp
IIRAM TMRr
rTOD"f:t
rTODtt,rTODtic
ne,tod ex
rTODttrTODsec
rTODsec,II60
ne,tod ex
rTODsec
rTODmin
rTODmin,II60
ne,tod ex
r TODm iii
rTODhr
rp
imr

1save entry" imrl
lallow nested interrupts
lenable interrupts!
!save rp!
!point to our set!
!ticks/second!
!second complete?!
!nope .1
!seconds!
!minute complete?!
!nope.!
!minutes!
! hour complete? 1
!nope .1
Ihours!
!restore rpl
Idisable interrupts 1
!restore entry imr!

273

P 0288

P
P
P
P
P
P
P
P
P
P
P
P

0288
028A
028C
028E
0290
0292
0294
0297
029A
0290
02AO
02A3

DC
C3
C3
C3
80
80
56
56
E4
E6
80

65
DE
DE
DE
EE
EE
F 1 3F
7F OF
7F F7
78 01
0282 '

P 02A3

P 02A3 84
P 02A6 84
P 02A9 B4

65
67
65

67
65
67

P 02AC F5
P 02AF SF
P 0280

67

66

274

932
933
934
935
936
937
938
939
9110
941
942
9113
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
9611
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989

GLOBAL
pulse i PROCEDURE

! ••••1i" •••••• ~ •••••••••••••••••••••••••••

=

Purpose

Input =

*•••••••••••••

To initialize one of the timers
ta geherate a variable frequency/
variable pulse width output.
RR14

= address

byte
byte
byte
byte

of parameter list in
program memory:
cntr value for low interval
counter H : = %F4 => TO
= %F2 => T1
cntr value for high interval
prescaler (unshifted)

Output

Selected timer is loaded and
enabled; corresponding interrupt
is enabled. P36 is enabled as Tout.
R13, R14, R15 modified.

Note

The parameter list is not referenced
following initialization.
.

The value of Pres caler x Counter
must be > 26 (=%lA) for proper
operation.
*** •• ****.** ••• ** •••• ** •• ***.*** ••••••• **** •• **.****.!
ENTRY
TMP,HPLS 2
LD
!low interval cntrl
ldci
@TMP,@PTR
Itimer addr!
@TMP,@PTR
ldci
! high interval cntr!
ldci
@TMP,@PTR
PTR
decw
!back to flag!
decw
PTR
Iwill be modifying TMR!
TMR,1I%3F
and
and
P3M save, nDF
IP36 = Tout!
P3~P3M save
ld
!flag for pre ctrl
ld
TEMP 4,#%1
!set up timerT
jp
pre_ctr
END
pulse ~

GLOBAL
pulse

PROCEDURE

1···················································*·
Purpose =
To modify the counter load value

to continue the pulse output generation.

•••••• *••••• *•••• * ••••••••••••••••••••••••••••••••••• !
ENTRY
lexchange values!
xor
PLS 1,PLS 2
xor
PLS-2,PLS-l
xor
PLS-l,PLS-2
!exchange completelld
@PLS_tmr,PLS_l
iret
END
pulse

Iload new valuel

P 02BO

P 02BO BO

P 02B2

7B

991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
lOll
1012
1013
lQ14
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024

GLOBAL
delay

PROCEDURE

I·····················································
Purpose =
To generate an interrupt after a
designated amount of time.

= address

Input =

RR14

Output =

Selected timer is loaded and
enabled; corresponding interrupt
is enabled.
'
R13, R14, R15 modified.

Note

This routine will initialize the timer
for single-pass or continuous mode
as determined by bit 0 of byte 3 i,n
the parameter list.
The caller is responsible for providing the interrupt service routine.

of parameter list in
program memory:
byte = counter , : = SF4 => TO
= SF2 => Tl
byte = Counter value
byte = Prescaler value and count mode
(to be loaded as is into
PREO or PRE1).

The parameter list is not referenced
fqllowing initialization.

·····················································1

ENTRY

clr
TEMP 4
Ifall into pre ctrt END
delay -

275

P 02B2

P
'P
P
P
P
P
P
P
P
,P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

02B2
02B4
02B6
02B9
02BC
02BF
02C1
02C4
02C7
02C9
02CB
02CE
0200
0201
0203
0204
0206
0209
020B
0200
02EO
02E2
02E5
02E7
02EA
02EB
02EE
02EF
02FO

C2
AO
E6
E6
A6
6B
E6
E6
C3
C2
'A6
6B
OF
10
OF
10
A6
EB
60
54
60
56
F3
44
8F
44
9F
AF

1026 INTERNAL
.
1027 pre ctr PROCEOURE
1028 I··T••••••••••••••••••••••••••••••••••••••••••••••••••
To get counter and prescaler values
1029 'Purpose =
from parameter list and modi·fy control
1030
registers appropriately.
1031
1032
TEMP II = 0 => for 'delay'
1033 Input =
= 1 => f~r 'pulse'
1034
= TOO 1mI' => for 'tod'
1035
1036 •••·••••••••••••••••••••••••••T ••••••••••••••••••••••• !
1037 ENTRY
ITO or T1I
Idc
TMP,@PTR
OE
1038
PTR
incw
EE
1039
! for TMRI
TEMP
2,U8C
1040
Id
70 8C
I for IMRI
TEMP-3,U20
Id
7E 20 1041
cp
TMP,lT1
EO F2 10112
li_s for T11
eq,pre 1
jr
1043
06
I for TMRI
Id
TEMP 2~U1I3
70 43 1044
!
for IMRI
TEMP-3,U10
Id
7E 10 1045
linit counterl
10116 pre_1: Idci
@TMP~@PTR
OE
Iprescaler!
PTRh,@PTR
Idc
EE
1047
Ishift prescaler?!
cp
TEMP 11,/10
7B 00 1048
Inol
eq,pre_2
jr
1049
12
lin·ternal
clock I
scf
1050
PTRh
rIc
EE
1051
Icontinuous model
scf
1052
PTRh
EE,
rIc
1053
TEMP 4,/JIT00 imr
cp
7B 6C 1054
I for 'pulse' I
ne,pre 3
jr
OA
1055
TEMP 3com
1056
7E
linsure no self-nesting!
TOO
I'mr,TEMP
3
and
7E 6C 1057
TEMP 3
com
7E
·1058
!no Tout mode mod!
TEMP-2,nOF
70 OF 1059 pre 2: and
!init prescaler!
@TMP'";"PTRh
OE
1060.pre:3: Id
Unit tmr mode!
TMR,TEMP_2
or
70 F1 1061
di
1062
tenable interrupt!
or
imr,TEMP_3
7E FB 1063
ei
10611
ret
1065
pre ctr
1066 ENO
1067 ENO PART_U-

o errors
Assembly complete

276

A Comparison of
Microcomputer Units

~Zirm

Benchmark Report

May 1981

INTROOUCTlON
The microcomputer industry has recently developed
single-chip microcomputers that incorporate on one
chip functions previously performed by peripherals. These microcomputer units (MCUs) are aimed

at marketa requlrlng a dedicated computer. This
report describes and compares the most powerful
MCUa in today'a market: the Zilog Z8611, the
Intel 8051, and the Motorola MC6B01. Table 1
lists facts that should be considered when comparing these MCUs.

Table 1. Ill! Comparison

,
FEATURES

Zilog
Z8611

Intel
B051

Motorola
11:6801

On-Chip ROM

4KxB

4Kx8

2KxB

General-Purpose
Regiaters

124

12B

12B

16
4

16
4

17
4

32
Four B-bit
Hardware on
three ports

32
Four 8-bit
None

29
Three B-bit,one 5-bit
Hardware on
one port

5
2
5
2 Programmable
orders
5

7,
2
7
Nonprogrammable

Maskable

B
4
6
4B Programmable
orders
6

External
Memory

120K bytes

124K bytes

64K bytes

16-Bit
Ves, uses
8-bits
Ves

B-Bit
Ves

16-Bit
Ves

No

Ves

Special-Function
Registers
Status/Control
I/O ports
I/O
Parallel lines
Ports
Handshake
Interrupts
Source
External source
Vector
Priority

Stack
Stack pointer
Internal stack
External stack

I

6

277

Table 1. MCU COIII{larison
(Continued)

fEATURES

Zilog
ZB611

Intel
B051

Motorola
MC6B01

Counter/
Timers
Counters

Two B-bH

One 16-bi t

Prescalers

Two 6-bit

Two 16-bi t
or two B-bit
No prescale
wi th 16-bits;
5-bit prescale
with B-bits

Addressing
Modes
Register
Indirect Register
Indexed
Direct
Relative
Immediate
Implied

Yes
Ves
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Ves
Yes
Yes
Ves
Yes

No
No
Yes
Yes
Yes
Yes
Yes

124, Any
generalpurpose
register

1,

1, Uses
16-bit index
regi ster

Ves

Ves

Ves

One for each

One for both

One for both

Receiver
62.5K bls
®B MHz
93.5K bls
®12 MHz

Receiver

Transmi tter/Receiver
62.5K b/s

2.2 Usee
1.5 Usee ®12 MHz

1.5 Usee

3.9 Usee

4.25 Usee
2.8 Usee ®12 MHz

4 Usee

10 Usee

Clock frequency

8 and 12

12 MHz

4 MHz

Power Down
Mode

Saves first
124 registers

Saves first
128 registers

Saves first
64 registers

Index
Registers

Serial
Communication
Interface
full duplex
UARr
Interrupts
for transmit
and receive
Registers
Double bu ffe r
Serial Data Rate
,

Speed
Instruct ion
execut Lon average
Longest
instruct ion

Context
Switching

278

MHz

Saves PC
and flaqs

Uses the
accumu lator
for 8-bit
offset

187.5K b/s
®12 MHz

Saves PC;
proqrammer
must save all
registers

None

®4 MHz

Saves PC, PSW,
accumulators,
and Index
register

Table 1. IDl Cllllpariaon
(Contiroed)

fEATURES

Zilog
Z8611

Intel
80S1

Motorola
MC6801

Developlllllnt

40-Pin
Protopack (8613)
64-Pin (8612)
40-Pin ROM less
(Z8681 )

40-Pin (8751)

40- Pin (68701)

[pro.

4K bytes (2732)

4K bytes

2K bytes

2K bytes (2716)
Availability

Now

ARCHITECTURAL OVERVIEW
This section examines three chips: the on-chip
functions and data areas manipulated by the Zilog,
Intel and Motorola MCUs. The three chips have
somewhat similar architectures. There are" however, fundamental differences in design criteri~.
The 8051 and the MC6801 were deaigned to maintain
compatabUity with older products, whereas the
Z8611 design was free from such reatrictions and
could experiment with new ideas. Because of this,
the accumulator architectures of the MC6801 and
the 8051 are not as flexible as that of the Z8611,
which allows any register to be used as an accumulator.
Memory Spaces
T'he Z8611 CPU manipulates data in four memory
spaces:
•
•
•
•

60K bytes of external data memory
60K bytes of external program memory
4K bytes of internal program memory (ROM)
144-byte register file

TBA

Now

required with the MC6801 thatia not necessary
with the Z8611 or the 8051.
On Chip RAM. All three chips use internal RAM aa
registers. These registers are divided into two
categories: general-purpose registers and special
function registers (SFRs).
The 124 general-purpose registers in the ZB611 are
divided into eight groups of 16 regiaters each.
In the first group, the lowest four registera are
ttle I/O port registers. The other registers are
general purpose and can be accessed with an 8-bit
address or a short 4-bit address. Using the 4-bit
address saves bytes and execution time. Four-bit
short addresses are discussed later. The generalpurpose registers can be used as accumulators, address pointers, or Index registers.
The 128 general-purpose registers in the B051 are
grouped into two sets. The lower 32. bytes are
allocated as four 8-register banks, and the upper
registers are uaed for the stack or for general
purpose. The registers cannot be used for indexing or as address pointers.

The'8051 CPU manipulates data in four memory
spacea:
.'64K bytes of external data memory
• 60K bytes of external program memory
• 4K bytes of internal program memory
• 14B-byte register file
The MC6801 manipulates data in three memory
spaces:
• 62K bytes, of external memory
• 2K bytes of internal program memory
• 149-byte regiater file
On-Chip RDM. All three chips have internal ROM
'for program memory. The Z8611 and the 8051 have
4K bytes of internal ROM, and the MC6801 has 2K
bytes. In some cases, external memory may be

The MC6801 also has a 128-byte, general-purpose
register bank, which can be used as a stack or as
address pointers, but not as Index registers.
As pointed out in Table 1, any of the Z8611
general-purpose registers can be used for indexing; the MC6801 and the 8051 cannot,use registers
this way. The Z8611 can use any register as an
accumulator; the MC6801 and the 8051 have fixed
accumulators. The use of registers as memory
pointers is very valuable, and only the Z8611 can
use its registers in this,way.
The number of ,general-purpose regiaters on each
chip is comp~rable. However, because of its
flexible design, the ZB611 clearly has a more
powerful register architecture.

279

The Z8611 has 20 special flKlction registers used
for status, control, and I/O. These registers
include:
• Two registers for a 16-bit Stack Pointer (SPH,
SPL)
• One regis-ter used as Register Pointer for
working registers (RP)
• One register for the status flags (FLAGS)
• One re~ister for interrupt priority (IPR)
• One register for interrupt mask (IMR)
• One register for inte~rupt request (IRQ)
-. Three-mode registers for the four ports-(P01M,
P2M, P3M)
• Serial communications port used like a
register (510)
• Two counter/timer registers (TO, T1)
• One Timer Mode Register (TMR)
• Two prescaler registers (PREO, PRE1l
• Four I/O ports accessed as registers (PORTO,
PORT1, PORT2, PORT3)
The 8051 also lias 20 special function registers
used for status, con~rol, and I/O. They include:
• One register for the Stack Pointer (SP)
• Two accumulators (A,8)
• One register for the Program Status Word
(PSW)
• Two registers for pointing to data memory
(DPH, DPL)
• Four registers that serve as two 16-bit
counter/timers (THO, TH1, TLO, TL1)
• One mode register for the counterYtimers
(TMOD)
• One control register for the- counter/timers
(TCON)
• One register for interrupt enable (IEC)
• One register for interrupt priority (IPC)
• One register for serial communications buffer
(SBUF)

• One register for serial communications control
(SCON)
• Four registers used as the four I/O ports (PO,
P1, P2, P3)
The MC6801 has 21 special function registers used
for status, control, snd I/O. These include:
•
•
•
•
•
•
•
•
•
•
•
•

280

One rsgister for RAM/EROM control
One serial receive register
One serial transmit regiater
One register for aerial control and- status
One serial rate and mode register
One register for status and control of port 3\
One register for status and control of the
timer Two registers for the 16-bit timer
lwo'registers for 16-bit input capture used
with timer
Two registsrs for 16-bit output compare used
'
with timer
Four data direction registsrs associated with
the four I/O ports
Four I/O ports

Ths special flKlction registers in the three chips
seem comparable in number and function. However,
upon clossr examination, the SFRs of the MC6801
prove less sfficisnt than those of the Z8611. The
MC6801 haSfivs registers associated with the I/O
ports, whereas the Z8611'uses only three registers
for the same funct ions. The MC6801 uses four
registers to perform the serisl communication
funct ion, whereas the Z8611 uses only one- register
and part of another.
The 8051 uses two registere for the accumulators; ,
the Z8611 is not limited by this restri~tion. The
8051 also uses two registers for the serial communication interface, whereas the Z8611 accomplishes the same job with one register. Anot_her
two registers in the 8051 are used for data
pointers; these are not necessary in the Z8611
since any register can be used as an address
pointer.
The Z8611 uses registers more efficiently than
_either the MC6801 or the 8051. The registera saved
by this optimal design are used to perform the
functions needed for enhanced interrupt handling
and for register pointing with short addresses.
The Z8611 also supplies the extra register requi red for the external stack. These features are
not available on the 8051 or the MC6801.
External Me.ory. All three chips can access
external memory. The Z8611 and, the 8051 can generate signals used for selecting either program or
data memory. The Data Memory strobe (the signal
used for selecting data or program memory) gives
the Z8611 access to 120K bytes of external memory
(60K bytes in both program and data memory). The
8051 can use 124K bytes of external memory (64K
bytes of external data memory and 60K bytes of
external program memory). The MC6801 can access
only 62K bytes of external memory and does not
distinguish between program and data memory. Thus,
the Z8611 and the 8051 are clearly able to access
more external memory than the MC6801.
On-Chip Peripheral Functions
'In addition to the CPU and memory spaces, all
chips provide an interrupt system and extensive'
I/O facilities including I/O pins, parallel I/O
ports, a bidirectional addres,s/ data bus, and a
serial port for I/O expansion. '
Interrupts. The Z8611 acknowledges interrupts
from eight sources, four are external from pins
IRQO-IRQ3, and four are internal from serial-in,
serisl-out, and the two counter/timers. All
interrupts are maskable, and a wide variety of
priorities are realized with the Interrupt Mask
Register and the Interrupt Priority Registers (see
Table 1). All Z8611 interrupts sre vectored, with
six vectors, located in the on-chip ROM. The
vectors are fixed locations, two bytes long, that
contain the memory address of the service routine.

The 8051 acknowledges interrupts from five
sources: two external sources (from INTO and
INT1) and three internal sources (one from each o(
the internal counters and one from the serial I/O
port). All interrupts can be disabled indi vidually or globally. Each of the five sources can be
assigned one of two priorities: high or low. All
8051 interrupts are vectored. There are five
fixed locations in memory, each eight bytes long,
allocated to servicing the interrupt.
The MC6801 has one e,xternal interrupt, one nonmaskable interrupt, an internal interrupt request,
and a software interrupt. The internal interrupts
are caused by the serial I/O port, timer overflow,
timer output compare, 'and timer input capture.
The priority of each interrupt is preset and cannot be changed. The external interrupt can be
masked in the Condition Code register. The MC6801
vectors the interrupts to seven fixed addresses in
ROM where the 16-bi t address of the service
routine is located.
When an interrupt occurs in the 8051, only the
Program Counter is saved; the user must save the
flags, accumulator, and any registers that the
interrupt service routine might affect. The
MC6B01 saves the Program Counter, acumulators,
Index register, and the PSW; the user must save
all registers that the interrupt service routine
might affect.' The ZB611 saves the Program Counter
and the, Flags register. To save the'16 working
registers, only the Register Pointer register need
be pushed onto the stack and another set of working registers ia used for the service routine.
For more detail on working registers and interrupt
context switching, see the ZB Technical Manual
(03-3047-02).
With regard to interrupts, the ZB611 is clearly
superior. The ZB611 requires only one command to
save all the working registers, which greatly
increases the efficiency of context switching.
I/O Facilities. The ZB611 has 32 lines dedicated
to I/O functions. These lines are grouped into
four ports with eight lines per port. The ports
can be configured individually under software
cont~ol to provide input, output, multiplexed
address/data lines, timing, and status. Input and
output can be serial or parallel, with or without
handshake. One port can be configured for serial
transmission and four ports can be ,configured for
parallel transmission. With parallel transmission, ports 0, 1, and 2 can transmit data with the
handshake provided by port 3.

handshake. The ports provide all the signals
needed to control input and output either serially
or in parallel, with or without mu'ltiplexed
address/data lines. They can be used to interface
with external memory.
The main differences in, I/O f.acilities are the
number of 8-bit ports and the hardware handshake.
The ZB611 and the B051 have four 8-bit ports,
whereas the MC6B01 has three B-bit ports and an
additional 5-bit port. The ZB611 has hardware
handshake on three ports, the MC6B01 has hardware
handshake on only one port, and the B051 has no
hardware handshake.
Counter/timers. The ZB611 has two B-bit counters,
and two 6-bit programmable prescalers. One prescaler can be driven internally or externally; the
other pres caler is driven internally only. Both
timers can interrupt the CPU when counting is
,completed. The counters can operate in one of two
modes: they can count down until interrupted, or
they can count down, reload the initial, value, and
start counting down again (continuously). The
countars for the Z8611 can be used for measuring
time intervals and pulse widths, generating variable pulse widths, counting events, or generating
periodic interrupts.
The B051 has two 16-bit counter/timers for measuring time intervals and pulse widths, generating
pulse widths, counting events, and generating
periodic interrupts. The counter/timers have
several modes of operation. They can' be used as
B-bit counters or timers with two 5-bit programmable prescalers. They, can also be used as 16-bit
counter/timers. Finally, they can be set as 8-bit
modulo-n counters with the reload value held in
the high byte of the 16-bit register. An interrupt
is generated when the counter/timer has completed
counting.
The MC6B01 has one 16-bit counter which can be
used for pulse-width measurement and generation.
The counter/timer actually consists of three
16-bit registers and an 8-bit control/status registe'r. The timer has an input, capture register,
an output compare register, and a frse-running
counter. All three 16-bit registers can generate
interrupts.

The B051 also hss 32 I/O lines grouped together
into four ports of eight lines each. The ports can
be configured under program control for parallel
or serial I/O. The ports can also be configured
for multiplexed address/data lines, timing, and
status. Handshake is provided by user software.

Serial Communications Interface. The ZB611 has a
programmable serial communication interface. The
chip contains a UART for full-duplex, asynchronous, serial receiver/ transmitter operation. The
bit rate is controlled by counter/timer 0 and has
a maximum bit rate of 93.500 b/s. An interrupt is
generated when an assembled character is transferrE1d to the receive buffer.
The transmitted
character generates a separate interrupt., The
receive register is double-buffered. A hardware
'parity generator and detector are optional.

The MC6B01 has 29 lines for I/O (three 8-bit ports'
and one 5-bit port). One port has two lines for

The B051 handles s~rial I/O using one of its
parallel' ports. The B051 bit rate is controlled
281

by counter/timer 1 and has a maximum bit rate of
187,500 b/s. The 8051 generates one interrupt for
both transmission and lJeceipt. The receive register is double-buffered.
The MC6801 contains a full-duplex, asynchronous,
serial communication interface. The bit rate is
controlled by a rate register and by the MCU's
clock or sri external clock. The maximum bit rate
is 62,500 b/s. Both tha transmit and the receive
registars are double-~uffered. Tha MC6801 generatea only one interrupt for both transmit and
receive operations. ,No hardware parity generation
or detecti.;m is available, although it does have
sutomatie detection of framing arrors and overrun
conditions.
,The 8051 and the MC6801 generate only one interrupt for both transmit and receive, whereas the
28611 haa a separate interrupt for each. The
ability to generate aeparate intarrupts great ly
anhances the usa of serial communications, since
separate service routines are often required for
transmitting and recaiving.
Other differences between the 2861" MC6801, and
the 8051 occur in the har!lware parity 'detector,
the double-buffering of registars, framing error
detectors and overrun conditions. The 8051 has a '
faster data rate than either the Z8611 or ,the
MC6801. The MC6801 has the advantage of s hardware framing error detector and automaticdetection of overrun conditions. The MC6801 also has
both its transmit
and
raceive
registers
doub~e-buffered. The 28611 has a hardware parity
detector. for detection o'f framing errors and
overrun conditions, a aimple, low-overhead soft~
ware check is available that uses only two
instructions. Sae Z8600 Software framing Error
Detection Application' Brief (document '617.,18810004).
INSTRUCTION ARCHITECTURE
The architectura of the Z8611 is designed specifically for microcomputer applications. This fact
is msnifest in the instruction composition. The
arduous task of programming the MC6801 and the
8051 starkly contrasts that of programming the
Z861'.
, Addressing Modes
The Z8611 and the 8051 both hava six addrassing
modes: Register, Indirect Register, Indexed,
Direct, Relativa, and Immediate. , The MC6801 hea
five ,addreesing modes: Accumulat6r, Indaxed,
Direct, Relative, and Immediate. A quick comparison of these addressing modes reveals the versatility of the 28611 and the 8051.
The addressing
mOdes of ths MC6801 have several reetrictione, as
shown in'Tabla 1., While the 8051 has all the
addressing modes of the Z86", its use of them is
restricted. The Z8611 allows many more combine-

282

tions of addressing modes per instruction, 'because
any of ita registara can be uSl;!d as an accumuiator. for examp~e, the-instructions to clear,
complement, rotata, and swap nibbles' are all
accumulator orientad in the 8051 and operate on
the accumulator only. These same commands in t!1a
Z8611 can use any register and acc!!ss it either
directly, with register addressing, or with indirect register addressing.
Indexed Addreeeing. All three chips differ in
their handling of indexing.' The Z8611 can use any
register fpr indexing. The 8051 can use only tha
accumulator as an Index regis tar in conjunction
with the data pointer or tha Program Counter. The
MC6801 has one 16-bit Index register. The address
, 'located in 'the second byte of an instruction is
added to the lower byte of the Index register.
The carry is added to the upper byte for the complete address. The MC6801 requires the index
value to be an immediate value.
The MC6801 has only one 16-bit Index register and
an immediate 8-bit value from the second byte of
the instruction. Hence, the Indexed mode of the
MC6801 is much more restrictive than that of the
Z861'. The 8051 must use the accumulator as its
only Index register, loading the accumulator with
the register address each tim,e a reference fa
made. Then, using indexing, the data is moved
into the accumulator, eradicating the previous
index. This forces a stream of data through the
accumulat,or and requirea a 'reload of tha indl!x
before acceas can ba made again. The Z861,1 is
clearly superior to both the MC6801 and the 8051
in the flexibility of its indexed addressing mode.

Short and Lang Addressing. Short addreSSing helps
to optimiza memory space and execution speed. In
sampls applications of ahort regiater addressing,
an eight percant decrease in the ,number of bytes
used was recorded.
All three chips have short addressing modes, but
the 28611 has short addressing for both external
memory and registsrmemory. The 8051 has short
addreesing for the lowest 32 registers 'only.
The 28611 has two' di fferent modea for regiater
,addreesing. The full-byte address can be used to
pro'vide the address, or a 4-bit addresa can be
used with the Register ~ointer. To use the working registera, the Regiater Pointer ill set for a'
particular bank of 16 registers, and then one of
ths 16 ragisters is addressed with four bits.
Another feature for addreasing external memory is
th!! uae of 'a 12-bit, address in place of a full
16-bit address. To use the 12-bit address', one
port sup\llies the eight multiplexed ad!lrass/data
lines and another port s~pplies four bits for the
address. The remaining four bits of the aecond
port can be uaed for ,I/O. Thia feature allows
access to a maximum of 10K bytes of memory.

The 8051 uses short addresses by orgsnizing its
lowest 32 registers into four banks. The bank
select is located in a 2-bit field in the PSW,
with three bits addressing the register in the
bank.
'
The MC6801 uses extended addressing for addressing
external memory. With a special, nonmultiplexed
expansion mode, 256 bytes of external memory can
be accessed without the need for an ,external
address latch. The MC6801 uses one 8-bit port for
the address and another port for the data.
Stacks
The Z8611 snd the MC6801 provide for external
stacks, which require a 16-bit Stack Pointer.
Internal stacks use only an 8-bit Stack Pointer.
The 8051 uses only a limited internal stack requir ing an 8-bit Stack Pointer. Using an external
stack saves the internal RAM registers for
general-purpose uee.

The stack structure of the Z8611 and the MC6801 is
better thsn that of the 8051. In most applications, the 8051' is more flexible and easier to
program than the MC6801. The !8611 is easier to
use, than either the 8051 or the MC6801 because of
its register flexibility and its numerous combinations of addressing modes. The 8051 features a
unique 4.u..n multiply and divide command. 'The
Io1C6801 has a multiply, but it takes 10)(.s to perform it.
In summary, the Z8611 has the most flexible
addresaing modes, the most advanced indexing capa-,
bilities, and superior space- and time-ssving
abilities with respect to short addressing.

with its 8051 family. The 8031 has no internal
ROM and the 8751 has 4K of internal EPROM.,
Motorola offers the MC6801, MC6803, MC6803NR, and
MC68701. These are all similar except the MC68701
has 2K bytes of EPROM and the MC6801 has 2K byt es
of ROM. The MC6803 has no internal ROM and the
MC6803NR has neither ROM nor RAM on board.
The Z8613 ~nd the MC68701 are both available now,
but the 8751 ie still unavailable (as of April
1981).
Software
Development software includes aasemble rs, and
conversion programs. All manufacturera offer some
or all of these features.
Since the MC6801 ie compatible with the 6800,
there is no need for a new assembler. The Z8611
and the 8051 both offer assemblers for their
products. The Zilog PLZ/ASM assembler generates
relocatable and absolute object code. PLZ/ASM
also ,supports high-level control and data statements, such as IF ••• THEN ••• ELSE. Intel offers an
absolute mscroassembler, ASM51, with their
product. They slso offer a program for converting
8048 code to 8051 code.
Modulee
The Z8611 development module has two 64-pin
development versions of the 40-pin, ROM-masked
Z8611. Intel offers the EM-51 emulstion board,
which'contains a modified 8051 and PROM or EPROM
in place of memory. Motorola haa the MEX680~EVM
evaluation board for program development. All
three development boards are available now.

DEVELOPMENT SUPPORT
All three vendors provide development support for
their products. This section discusses the different support features, including development
chips, software, and modules.

ADDITIONAL FEATURES

Chips

Power Down Mode

Zilog offers an entire Jamily of microcomputer
chips for product development and final product.
The Z8611 is a single-chip microcomputer with 4K
bytes ,of mask-programmed ROM. For development, two
other chips are offered. The Z8612 is a 64-pin,
development version with full interface to external memory. The Z8613 ie 'a prototype version
that uses a functional, p'iggy-back, EPROM protopak. The Z86H can use either a 4K EPROM (2732)
or a 2K EPROM (2716). Zilog also offers a ROMless
version in a 40-pin package that has all the featuras of the Z8611 excapt on-board ROM (Z8681).

All three microcomputers offer a Power Down mode.
Ths Z8611 and the 8051 save all of their registers with'an auxilary power supply. The MC6801
uses an auxiliary power supply to save only the
first 64 bytes of its register file.

Intel offers a similar line of development chips

Additional features include Power Down mode, selftesting, and family-compatibility.

The Z8611 uses one of the crystal input pins for
the external power supply to power the registers
in Power Down mode. Since the XTAL2 input must be
used, an external clock generator ia necessary and
ia input via XTAL1. The 8051 and the MC6801 both
have an input reserved for this function. The
MC6801 uses the Vcc standby pin, and the 8051 uses
the Vpd pin.

283

Family Caapatibility

Program Listings

Another strl!ngth of the Z8611 is its expsnsion
bus, which is completely compatible with the Zilog
Z-BUS TM. This means that all Z-BUS peripherals
can be used directly with the Z8611.

80S1

The MC6'801 is fully compatible with all MC6800
family products. The 8051 is software compatible
with the older 8048 series and sll others in that
fsmily;

BENCHMARKS
The following benchmark tests were used in this
report to compare the Z8611, 8051, and MC6801:
• Generate CRC check for 16-bit word.
• Search for a character in a block of memory.
• Execute a computed GOTO - jump to one of eight
locations depending on which of the eight bits
is set.
'
• Shift a 16-word five places to the right.
• Move a 64-byte block of dsta from externsl
memory to the register file.
• Toggle a single bit on a port.
.'Measure the' subroutine overhead time.
These programs were selected betause of their
importance in microcomputer applications. 'Algorithms thst reflect a unique function or feature
were excluded for the sake of comparison. Although programs csn be optimized for s psrticular
chip and for a pal,"ticular sttribute (code density
or speed) these programs were not.
The figures cited in this text, are taken directly
from the vendor's documentation. Therefore, the
cycles given below for the 14::6801 and the 8051 are
in machine cycles and, the Z8611 figures are given'
in clocl~ cycles. The Z8611 clock cycles should be
divided by six to give the instruction time in
microsecohds.
The 8051 and 14::6801 machine cycle
is 1.M.S, and the Z8611 clock cyc Ie is .166 Jf(.s at
12 MHz.
Because of the lack of avsilsbility of the MC6B01
and,the 8051, the benchmark programs listed here
have not ,yet been run. When these products are
readily available, the' programs, will be run and
later ,editions of this document will reflect any
changes in the findings.

284

CRC Generation

MOV
LOOP: MOY
XRL
RLC
MOY
XRL
RLC
MOY
MOY
XRL
RLC
HOY
CLR
HOY
RLC
'HOY
DJNZ

RET

N

INOEX, #8
A, DATA
A" HCHECK
A
A, LCHECK
A, LPOLY
A
LCHECK, A
A,' HCHECK
A, 'HPOLY
A
HCHECK, A
C
A, DATA
A
DATA, A
INDEX, LOOP

= 3+17X8 = 139 cycles
11112 MHz = 139.&s
Instructions = 18
Bytes = 31

MC6801
LDAA #$08
LOOP: STAA COUNT
LDAA HCHECK
EORA DATA
ROLA
LOAD ,POLY
EORA HCHECK
EORB LCHECK
ROLB
ROLA
STAD LCHECK
ASL
DATA
DEC
COUNT
BNE
LOOP
RTS
N = 45X8+7 = 367 cycles_
1114 MHz = 367"",
Instruct ions = 15
Bytes = 28

Machine
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2

Bytes
2
2
2
1
2
2
1
2
2
2
1
2
1
2
1
2
3
1

Machine
Cycles
2
3
3
3
2
4
3
3
2
2
4
6
6
4
5

Bytes
2
2
2
2
1
2
2
2
1
1
2
3
3
2
1

Clack
Cycles
LO
INOEX, '#8
6
R6, DATA
LOOP: LD
6
XOR
R6, HCHECK
6
RLC
R6
6
LCHECK, LPOLY
XOR
6
LCHECK
RLC
6
HCHECK, HPOLY
6
XOR
RLC' HCHECK
6
RCF
6'
RLC
OATA
6
DJNZ INOEX, LOOP
12 or 10
RET
14
N = 20+66X7+64 = 546 cycles
11112 MHz = 91 Jf(.s
Instructions = 12
Bytes = 22

l8611

Bytes
2
2
~

2
2
2
2
2
1
2

2
1

Shift 16-Bit Word to Right 5-Bits

Character Search Through Block of 40 Bytes

8051

Machine
Cycles
1
2
2
2

MOV
INDEX, 1141
MOV DPTR, IITABLE
LOOP1: DJNZ INDEX, LOOP 2
SJMP OUT
LOOP2: MOV A, INDEX
MOVC A, @A+DPTR
2
CJNE A, CHARAC, LOOP1
2
OUT:
N = 3+39X7+4 = 2BO cycles
®12 MHz = 280.l4s
Instruct ions = 7
Bytes = 15

~6801

LDAB
LDAA
LDX
LOOP: CMPA
BEQ
INX
DECB
BNE
OUT: -

11$40
IICHARAC
IITABLE
$0, X
OUT

LOOP

Machine
Cycles
2
2
3
4
4
3
2
4

8051
Bytes
2
3
2
2
2
3

Bytes
2
2
3
2
2
1
2

N = 7+40X17 = 687 cycles
®II MHz = 687 ..... s
Instructions = 8
Bytes = 15

~6801

LDX 115
LDAD WORK
LOOP: LSRD
DEX
BNE LOOP
STAD WORD
N = 10X5+11 = 61 Cycles
®II MHz = 61 Me
Instructions = 6
Bytes = 11

Bytes
2
2

2

Machine
Cycles
6
4
3
3
4
4

2
2
1
2
2

Bytes
3
2

2
2

Z8611

Z8611

Clock
Cycles
LD
INDEX, 1140
6
LOOP: LD
DATA, TABLE (INDEX) 10
DATA, CHARAC
CP
6
JR
Z, OUT
12 or 10
DJNZ INDEX, LOOP
12 or 3D
OUT: -

MOV INDEX 115
LOOP: CLR C
MOV A, WORD + 1
RRC A
MOV WORD + 1, A
MOV A, WORK
RRC 'A
MOV WORD, A
DJNZ INDEX, LOOP
N = 1+9X5 = 46 Cycles
®1 2 MHz = 46418
Instructions = 9
Bytes = 15

Machine
Cycles
1

Bytes
2
3
2
2
2

Clock
Cycles
Bytes
LD
INDEX, 115
6
2
LOOP: CCF
6
RRC WORD + 1
6
2
RRC WORD
6
2
DJNZ INDEX, LOOP
12 or 10
2
N = 6+4X30+28 = 154 Cycles
®12 MHz = 26.1(s
Instructions = 5
Bytes = 9

N = 6+38X40 = 1524 cycles
@12 MHz = 254""s
Instructions = 5
Bytes = 11

285

Computed GOlO

8051
MOV
LOOP: MOV
RLC
JC
. MOV
ADD
MOV
SJMP
OUT: MOV
MOV
JMP
TABLE: LCALL

INDEX, #40
A, DATA
A
OUT
A, INDEX
A, #3
INDEX, A
LOOP
DPTR, #TABLE
A, INDEX
®A+DPTR
ADDR1

Move 64-Byte Block

Machine
Cycles
1

8051
Bytes
2
2

2
1

2
1
2

2
2

2
3

2

MOV
INDEX, #COUNT
LOOP: MOV
DPTR, #ADDR1
MOVX
A, OOPTR
#ADDR1
INC
MOV
®ADDR2,A
ADDR2
INC
DJNZ INDEX, LDOP
N = 1+9X64 = 577 Cycles
®12 MHz = 577~s
Instruct ions = 7
Bytes = 10

MC6801
2

Machine

LDAB #2
LDX
TABLE
LOOP: RORA
BeS
OUT
ABX
JMP
LOOP
OUT: LDX
0, X
JMP
0, X
N = 8X12+14 = 110 Cycles
®4 MHz = 110..u..s
Instruct ions = 8
Bytes = 17

Cycles
2
3
2
4
3
3
5
4

Bytes
2
3

1
2
2
3
3

Clock
Cycles
Bytes
CLR INDEX
6
2
LOOP: INC INDEX
6
1
6
2
RLC DATA
JR NC, LOOP
12 or 10
2
LD ADDR,TABLE 1, (INDEX)
10
3
LD ADDR+1,TABLE 2, (INDEX) 10
3
JP ®ADDR
12
2
N = 6+24X7+54 = 228 Cycles
®12 MHz = 3Bl4s
Instructions = 7
Bytes = 15
ZB611

286

Bytes
2
3

2

3

LCALL ADDRN
N = 1+9X7+11 = 75 Cycles
®12 MHz = 75JJ-.3
Instructions = 12
Bytes = 21

MC6801

Machine
Cycles
1
2
2
1

Machine
Cycles
Z
4
4

LDAB ffCOUNT
LOOP: LDX
ADDR1
LDAA 0, X
INX
STAA ADDR1
LDX
ADDR2
STAA 0, X
INX
ADDRZ
STX
DECB
BNE
LOOP
N = 64X36+Z = 2306 Cycles
®4 MHz =23064s
Instruct ions = 11
Bytes = 21

ZB611

Bytes
2
3
2

3

4
4
4
3

4
2
4

2
3

2
1
2
1
2

Clock
Bytes
Cycles
LD
INDEX, ffCOUNT
6
2
LOOP: LDEI ®ADDR2, ®ADDR1
1B
2
DJNZ INDEX, LOOP
12 or 10
2
N = 6+63X30+2B = 1924 Cycles
®12 MHz = 321~s
Instructions = 3
Bytes = 6

Toggle a Port Bit

8051

Subroutine Call/Return Overhead

Machine
Cycles
PO, #VV
N = 2 Cycles
®12 MHz = 2AS
Instructions
Bytes = 3
XRL

2

LCALL SUBR

Bytes

2

Bytes
3

3

REf
N = 4 Cycles

Machine
Cycles
LDAA
EORA
STAA
N =8

3
2
3

Bytes
2

2
2

MC6801
JSR

SUBR

PORTO, flY V
N = 10 Cycles
®12 MHz = 1.7 48
Instructions = 1
Byte = 2

Machine
Cycles
9

Bytes
2

SUBR: -

3

Z8611

2

®12 MHz = 4&s
Instructions
2
Bytes = 4

RTS

XOR

Machine
Cycles

SUBR: -

MC6801
PORTO
#VV
PORTO
Cycles
®4 MHz = 8AS
Instruct ions
Bytes = 6

8051

Clock
Cycles
10

N = 14 Cycles
®4 MHz = 144/.s
Ins truct ions
2
Bytes = 3

Bytes

5

2

Z8611
CALL ®SUBR

Clock
Cycles
20

Bytes
2

SUBR: RET

N

14

34 Cycles
®12 MHz = 5.7.4ts
Instructions = 2
Bytes = 3

Results
Table 2 summarizes the results of this comparison.
The relative performance column lists the speeds
of the MC6B01 and 8051 divided by the ZB611 speeds
(12 MHz). The overall performance averages the
separate relative performances. The higher the
number, the faster the Z8611 as compared to the
MC6B01 and the B051.
The relative performance figures show that the
ZB611 runs 50 percent faster than the B051 and 250
pe r cent faster than the MC6B01. Although speed is
not necessarily the most important criterion for
selecting a particular product, the Z8611 proves
to be an undeniably superior product when speed is
added to the advantages of programming ease, code
density, and flexibility.

287

Table 2.

HC6801
(4 MHz)
cycles time

Benchmark
Test
CRC
Generation

Benchmark Program Results

Z8
(8 MHz)
cycles time

8051
(12 MHz)
. cycles time

Z8

(12 MHz)
cycles time

Relative Performance
HC6801
8051

367

367

139

139

546

137

546

91

4;03

1.53

Character
Search

687

687

280

280

1524

382

1524

254

2.70

1.10

Computed
GOTO

110

110

75

75

228

57

228

38

2.89

1.97

61

61

46

46

154

38

154

26

2.35

1.78

2306

2306

577

577

1924

481

1924

321

7.18

1.80

14

14

4

4

34

8.5

34

5.7

2.46

0.70

8

8

2

2

10

2.5

10

1.7

4.71

1.18

,

Shift Right
5 Bits
Move
64-byte
block
Subroutine
Overhead
Toggle a
Port Bit

Note:

Overall
Performance

3.76

1.44

-

All times are given in microseconds.

Table 3.

---

Bytes
MC6801 8051

Byte/Instruction/Time Comparison

Z8611

Instructions
1«:6801 8051 Z8611

Time (microseconds)
Z8611
1«:6801 8051

CRC Generation

28

31

22

15

18

12

367

139

91

Character Search

15

15

11

8

7

5

687

280

254

Shift Right 5 Bits,

11

15

9

6

9

5

61

46

26

Computed GO TO

17

21

15

8

12

7

110

75

38

Move 810ck

21

10

6

11

7

3

2306 '

577

321

Toggle Port Bit

6

3

2

3

1

1

8

2

1.7

Subroutine Call

3

4

3

2

2

2

14

4

5.7

288

SUMMARY
The hardware of the three chips compared is very
similar. The ZB611, however, has several advantages, the most important of which is its interrupt structure. It is more advanced than the
interrupt structures of both the B051 and the
MC6B01. Other advantages of the ZB611 over either
the MC6B01 or the B051 include I/O facilities .with
parity detection and hardware handshake and a
larger amount of internal ROM (the MC6B01 has only
2K bytes).

the ZB611 are more flexible than those of either
the MC6B01 or the B051. The ZB611 can use bytesaving addressing with working registers, and it
has short external addresses for saving I/O lines.
It can also provide for an external stack. The
register architecture (as opposed to the accumulator architecture) of the ZB~11 saves execution
time and enhances programming speed by reducing
the byte count.

Substantial differences are apparent with regard
to software architecture. The addressing modes of

The ZB611 microcomputer stands out as the most
powerful chip of the three, and concurrently, it
is the easiest to program and configure.

289

290

Z86XX Interrupt
Request Register

~ZiIill

Application Brief

October 1980

The Interrupt Request Register (IRQ, R250)
stores requests from the six possible Interrupt sources (IRQO_IRQ5) In the Z8600 series
microcomputer. In addition to other functions, a hardware reset to the Z8600 disables
the IRQ register and resets Its request bits.
Before the IRQ wi II register requests, It
must first be enabled by executing an Enable
Interrupts (EI) Instruction. Setting the
Enable Interrupt bit In the Interrupt Mask
Register (IMR, R251) Is not an equivalent
operation for this purpose; to enable the
IRQ, an EI Instruction Is required. The
function of this EI Instruction Is distinct
from Its task of globel Iy enabling the Interrupt system. Even In a pol led system where
IRQ bits are tested In software, it Is
necessary to execute the EI.

The designer must ensure that unexpected and
undesirable Interrupt requests will not occur
after the EI is executed. One method of
doing this is to reset 21.11 interrupt enable
bits in the IMR for levels that are possible
interrupt sources; the EI Instruction may
then be safely executed. Once EI is executed, the program may immediately execute a
Disable Interrupts (01) instruction. The
code necessary to perform these operations is
as follows:
RESET:

LD
EI

IMR, #%XX

ISET INTERRUPT MASK!
IENABLE GLOBAL INTERRUPT, ENABLE IRQ!

where XX has a ~ in 'each bit position corresponding to the interrupt level to be
disabled. If al I IMR bits are to be reset, a
CLR IMR instruction may be used.

EI INSTRUCTION
INTERRUPT REQUEST REG.
(IRQ, R250)

R

Z8600

RESET

F1gure 1 - IRQ Reset Funct10nal Logic Diagram

291

Z8 Family Software
Framing Error ,-Detection

~ZiIm

Application Brief

October 1980
The Zllog Z8600 UART mlcrocanputer Is a hlghperformance. single-chip device that Incorporates on-chip ROM. R~. parallel 1/0.
serla I 1/0. and a baud rate generator. The
UART is capable of full-duplex. asynchronous
serial communication at nine standard
software-selectable baud rates fran 110 to
19.2K baud; other nonstandard rates can also
be obtained under software control. Odd
par i ty generat ion and checkl ng can a Iso be
selected.

I

IL~ I
START
BIT

2

3

Three possible error conditions can occur
during reception of serial data: framing
error. parity error. and overrun error. A
framing error condition occurs when a stop
bit is not received at the proper, time
(Figure 1). This can result fran noise in
the data channel. causing erroneous detection
of the prev lous start bit or Iack of detection of a properly transmitted stop bit. The
Z8600 UART does not Incorporate hardware
framing error detection but,does facilitate a
simple. low-overhead software detection
method.

4

5

6

IM~B I

I

'I
I

L_~

PARllY STOP
(IF
BIT
ENABLED)

DATA BITS (8)

Fig. 1 - Asynchronous Data FOI"IIIIIt
In the middle of the stop bit time. the Z8600
UART automatically posts a serial input
I nterrupt request on IRQ3. The ser'ial Input
can also be tested, by reading Port 3 bit 0
(P30) as shown in Figure 2. Thus. within
the Interrupt service routine or polling
loop. it I,s only necessary to test P3 0 in
order to identify a framing error. If P30 is
Low when IRQ3 goes High. a framing error con-

SERiAL _
DATA IN

ditlon exists and the following code Is used'
to test this:
1M P3. 1%01
JR Z. FERR

The execution time of this framing error test
Is on I y 5.5 "(s at 8 MHz. In the worst case
(19.2K baud). this would result in 1% overhead. Only five program bytes are- required.

P30

Z8600
Fig. 2 - Z8600 Serial Input ConnectIon
Z8 Is

292

a

trademark of Zilog. Inc.'.

I TEST FOR P30 = 1 I
I ELSE FRAMING ERROR I

CONCLUSION

While the Z8600 UART does not Incorporate
hardware framing error detection, this
feature can be Implemented In software with a

maximum penalty of 1% at 19.2K baud using no
additional hardware and only five bytes of
program memory.

Reprinted with permission of Synertek, Inc.

293

294

~ ZiIm

Technical Manual

November 1984

Z8® Microcomputer

295

Table Of Contents
Chapter 1.

Z8 family Overview

I

Introduction
Features

301
301

1.2.1 Instruction Set
1.2.2 Architecture •

301
301

1.3

Microcomputers (ZB601/11)

302

1.4

Development Device (ZB612)

302

1.5

Protopack Emulator (Z8603/13)

304

1.6

BASIC/Debug Interpreter (ZB671)

304

1.7

ROM less Microcomputer (ZB681/B2)

304

1.1
1.2

1.B

. Applications

Chapter 2.
2.1
2.2
2.3

Architectural Overview

Introduction
Address Spaces
Register File •
·2.3.1 Register Pointer
2.3.2 Instruction Set
2.3.3 Data Types
2.3.4 Addressing Modes

2.4

2.5
2.6

304

2
306
306
307
307
307
307
307

I/o Operations

307

2.4.1
2.4.2

307
307

Timers.
Interrupts

Oscillator
Protopack •

308
308

Chapter 3. Address Spaces
3.1
3.2

3

Introduction
CPU Register File

309
309

3.2.1

Error Conditions

310

3.3
CPU Control and Peripheral R~gisters
3.4 . CPU Program Memory
3.5
CPU Data Memory
3.6 CPU Stacks

311
311
313
313

296

Table Of Contenls (Continued)
Chapter 4.

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Introduction • • • • • • • • • •
Register Addressing (R) • • • • •
Indirect Register Addressing (IR)
Indexed Addressing (X)
Oirect Addressing (DA)
Relative Addressing (RA)
Immediate Data Addressing (1M)

Chapter 5.

5.1
,5.2

'5'.3
5.4

5.5
5.6

4
315
315
316
316
317
317
318

5

Instruction Set

Functional Summary,.
Processor Flags.

319
320

5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6

320
320
320
321
321
321

Carry Flag (C)
Zero Flag (Z)
Sign Flag (S)
Overflow Flag (V)
Decimal-Adjust Flag (D)
Half-Carry Flag (H)

Condition Codes • • • • • •
Notation and Binary Encoding

321
321

'5.4.'1 Assembly Language Syntax
5.4.2 Condition Codes and'Flag Settings

322
322

Instruction Summary • • • • • • • • •
Instruction Descriptions and Formats

324
325

Chapter 6.

6.1
'6.2
6.3
6.4
6.5
6.6

Address Modes

6

Extemal Interface (Z8601. Z8611)

Introduction • • • • • ,• • • •
Pin Description • • • • • • • •
Configuring for External Memory
External Stacks
Data Memory •
Bus Operation •
6.6.1 Address Strobe (AS'
'6.6.2 Data Strobe (OS) ••
6.6.3 External Memory Operations

6.7
Shared Bus • • • •
6.8
Extended Bus Timing
6.9
Instructioh Timing
6.10 Reset Conditions •

369
369
370
371
371
371
• 372
• 372
·372
.373
• 374
·375
·378

297

Chapter 7. External Interface (Z8681, Z8682)
7.1
7.2
7.3

Introduction
Pin Descriptions
Configuring Port 0
7.3.1 Z8681 Initialization
7.3.2 Z8682 Initialization
7.3.3 Read/Write Operations

7.4
7.5
7.6

7.7
7.8
7.9
7.10

External Stacks
'Data Memory.
Bus Operation •

7
379
379
380
380

381
382
382
382

383

7.6.1 Address Strobe (AS)
7.6.2 Data Strobe (OS)

383
383

Extended Bus Timing.
Instruction Timing
Z8681 Reset Conditions
Z8682 Reset Conditions

383 .
384
~84

384

Chapter 8. Reset IWId Clock
8.1
8.2
8.3

385
386

8.3.1 Interrupt Testing
8.3.2 ROMless Operation

386
386

Chapter 9.

9.1

9.2

298

386

I/O Ports

9

Introduction

388

9.1.1 Mode Registers
9.1.2 Input and Output Registers

388

Port 0

388

9.2.1
9.2.2

9.3

8

Reset.
•
Clock •.•
Test Mode.

Read/Write Operations
Handshake Operation

388

390
390

Port 1

391

9.3.1 Read/Write Operations
9; 3. 2 Handshake Operation

391
391

Table Of Contents (Continued)
9.4

9.4.1
9.4.2
9.5

10.3
10.4

393
Read/Write Operations
Special Functions

'.

393
394
395
396

Interrupts

10

Introduction
Interrupt Sources

399
399

10.2.1

External Interrupt Sources
Internal Interrupt Sources

399
401

Interrupt Request Register Logic and Timing
Interrupt Initialization • • • • •

401
401

10.4.1 Interrupt Priority Register Initialization
10.4.2 Interrupt Mask Register Initialization
10.4.3 Interrupt Request Register Initialization

402
403
403

10.2~2

10.5 IRQ Software Interrupt Generation
10.6 Vectored Processing • • • • • • •
10.6.1
10.6.2

9

392
392

Port Handshake
I/O Port Reset Conditions

Chapter 10.
10.1
10.2

Read/Write Operations
Handshake Operation

Port 3
9.5.1
9.5.2

9.6
9.7

392

Port 2

Vectored Interrupt Cycle Timing
Nesting of Vectored Interrupts

403
404
404
404

10.7

Polled Processing

404

10.B

Reset Conditions

405

299

cilaPter 11. Counter!TiErs

II
406

11.1 Introduction
11.2 Prescalers and Counter/Timers
11.3 Counter/Timer Operation •

407
408
408
408

11.3.'1 'Load and Enable Count Bits
11.3.2 Prescaler Operations

409
410

11.4 TOUT Modes.
11.5 TIN Modes.
11.5.1
11.5.2
11.5.3
11.5.4

411
411,
413
413

External CIQck Input Mode
Ga,ted Internal Clock Mode
Triggered Input Mode
Retriggerable Input'Mode

11.6 Cascading Counter/Timers.
11.7 Reset Conditions

413
413

,

Chapter 12. Serial I/O

12

12.1 Introduction
12.2 Bit'Rate Generation
12.3 Receiver Operation
12.3.1
12.3.2
12.3.3
12.3.4

415
415
417
417
418
418
418

Receiver Shift Register
Overwrites
Framing Errors
Parity

418

12.4 Transmitter Operation

.

12.4.1 Overwrites
'12.4.2 Parity
•
12.5 Reset Conditions

419
419
420

Appendix A. Pin Descriptions and Functions
A.1
A.2

Developm,ent Device (Z8612)
Protopack Emulator (Z8603/13)

Appendix 8.

Control Registers

Appendix C.

IIpcode Map • • • •

300

422
422

. ,.

427
430

Chapter 1
18 Family Overview
1.1

INTROOUCTII»I

This chspter provides ~n overview of the architecture and features of the Z8 Family of products,
with particular emphasis on those features that
,set this microcomputer apart from earlier microcomputers. Detailed information about the architecture, addres~, spaces and modes, instruction
set, external interfsce, timing, input/output
operations, snd interrupts can be found in subsequent chapters of this manual.

1.2 FEATURES
The Z8 microcomputer introduces a new level of
sophistication to single-chip architecture. Compared to earlier single-chip microcomputers, the
Z8 offers faster execution; more efficient use ofmemory; more sophisticated interrupt, input/output
and bit-manipulation capabilities; and easier system exp~nsion.
Z8 products offer the standard on-chip functions
of earlier microcomputers, including:
•
•
•
•
•
•

2K or 4K bytes of ROM
144 8-bit registers
32 lines of programmable I/O
Clock oscillator
Arithmetic logic unit
Parallel and serial ports

Beyond these basic features, the Z8 Family offers
such advanced characteristics as:
•
•
•
•
•
•
•
•

Two counter/timers
Six vectored interrupts
UART for serial I/O communication
Stack functions
Power-down option
TTL compatibility
Optimizedoinstruction set
BASIC/Debug interpreter

All members of the Z8 Famtly are variations of the
basic Z8 microcomputer, the Z8601/11.
The Z8
Family includes a development device (Z8612), a
ROMless device (Z8681/82), BASIC/Debug Interpreter
(Z8671), a Protopack emulator (Z8603/13), as well

as the basic microcomputer. These products offer
all the parts and development tools necessary for
systems development (both hardwsre and software
prototyping), field trials (pre-production) and
full- production. For prototyping and preproduction, or where code flexibility is important, the
ZB603/13 Protopack, 2K and 4K EPROM-based parts
are the most appropriate. The ROM-based Z8601!11
microcomputers are used in high-volume production
applications after the software has been perfected. For ROM less applications, two versions of
the Z8 microcomputer are available: the 40-pin
Z8681/82 and the 64-pin Z8612. In addition, there
is a military version of the Z8611 4K ROM device,
available in both 40-pin ceramic and 44-pin leadless chip carrier packages.
The ZB671 MCU is a complete microcomputer preprogrammed with a BASIC/Debug Interpreter.
This
device, operating with both external ROM or RAM
and on-chip memory registers, is suitable for most
industrial control applications, or whenever fast
and efficient program development is necessary.
The Z8 microcompute~ is well-suited for dedicated
control -applications in real-tim~ mode.
Since
speed is a key consideration in such applications,
the Z8 Family is available in both 8 and 12 MHz
versions, supported by either of two development
modules: the Development Module (OM) or the
Z-SCAN 8. The Z-SCAN module provides (ICE) incircuit emulation capability.

1.2.1

Instruction Set

The Z8 instruction set, consisting of 43 basic
instructions, is optimized for high-code density
and reduced execution time.
The 47 instruction
types and six addressing modes--together with the
ability to operate on bits, 4-bit words, BCD
digits, 8-bit bytes, and 16-bit words--make for a
code-efficient, flexible microcomputer.

1.2.2 Architecture
Z8 architecture offers more flexibility and p'erformance than previous A/B accumulator designs.
All 12B general-purpose registers,' including

3Q1

dedicated I/O port registers, can be used as
accumulators. This eliminates the bottleneck commonly ,found in A/B devices, particularly in highspeed applications such as disk drives, printers
and terminals. In addition, the registers can be
used as address pOinters for indirect addressing,
as index registers or for implementing an on-chip
stack. Speed of execution and smooth programming
are supported by 11 "working regist.er area"--short
4-bit register addresses.

The Z8 can be a stand-alone microcomputer with
either 2K' bytes! (Z8601). or ilK bytes (Z8611) of
internal ROM, a traditional microprocassor that
can manage up to 124K bytea (Z8601) or 120K bytes
(Z8611) of external memory, or a parallel processing element in a 'system with other processors and
peripheral controllers linked by a Z-BUS. In all
configurations, a large number of, device pins are
available for I/O. Key features of the' Z8601/11
microcomputer include:
•

ROM ZIC-byte (Z8601) or U-byte (Z8611) Progr_
MIIIIory. This ROM is mask-programmed during
production with user..;provid~d programs.

•

144-byte RAM Rag1ater rile.
The internal
register organization of the Z8 microcomputer
centers around a 144-byte file composed of 124
general-purpose registers, 16 status and
control registers, and 4 I/O pOrt registers.
Either an 8-bit or a 4-bit address mode can be
When the
used to access the register file.
4-bit mode is used, the register file, is
divided into 9 groups of 16 wrking registers
each. A Register Pointer uses short-format
instructions to quickly access anyone of the
nine groups. Use of the 4-bit addreSSing mode
decreases access time and improves throughput.

s

•

Progr-mle Cod1ter/TUers. Two 8-bit counter/timer circuits are provided, each driven by
its own prescaler. Both the counter/timers and
their prescaler circuits are programmable.
UART (~iYersal llaynchronoue Receiver' Tr.u.itis provided' to
control serial data communications.' One of the
on-chip counter/timer circuits provides the
required bit rate input' to enable the UART to
operste at a maximum data transfer rate of
,93.7SK bits per second at a crystal ,frequency
of 12 MHz.

tar). . A full-duplex' UART

302

Table 1-1 lists' the, basic characteristics of th'e
members of the ZB Family. ,As shown, the major
differences between the products are in their
physical packsging and the msnner in which address
sp,ace is hsndled. An overall description for each
ZB type is given in the following sections.
Variations within each group are specified where
applicable.

•

I/O lines/Ports. The ZB lllicrocomputer provides
32 input/output lines, arranged as 4 8-bit
ports. Under software control, the I/O ports
(Ports 0, 1, 2, 3) can be programmed as input,
output, or additional address lines. The I/o
ports can also be programmed to provide timing,
status signals, interrupt inputs and serial or
parallel I/O (with or without handshake).

•

Vectored Interrupts. The ZB MPU permits the
use of six different interrupts from any of
eight different sources.
four Port J, lines
(PJO~33)' serial input pin (PJo), the serial
output pin (PJ 7) , and both coimter/timer
circuits may be interrupt sources.
All
interrupts are vectored and are both maskable
and prioritized.

•

Oacillator Circuit. An oscillator circuit that
can be driven from an external clock or crystal
is provided on the Z8 microcomputer.
The
oscillator will accept an input frequency of up
to 12 MHz on the XTAL1 and XTAt2 pins provided.

•

Optional

Poer-Doton reabRe.
This option
permits normal input power to be removed from
the chip without affecting the contents of the
register file.
The power-down' function
requires an external battery backup system.

Pin functions and descriptions for the Z8601/11
microcomputer can be'found in Chapter 6.

1.4 DEVEUI'iENT DEVICE (Z8612)
A development devica allows users to pr,ototype a
system with an actual hardware device and to
develop the code that is eventually, mask-programmed into the on-chip ROM of the ZB601 or ZB611
microcomputer. Development devices are also useful in ~ applications where production volume does
not justify the expenae of a ROM system.
The
ZB612 development d~vice is identical t!J its
equivalent microcomputer, the ZB611, with the following exceptions:

•

No internal ROM is provided, so that code is
developed in an off-chip memory.

•

The normally internal ROM address and data
lines are buffered and brought out to external
pins to interface with the external memory.

•

Control lines are added to
external program memory.

interface

•

The dev ice package is enlarged in order to
accommodate the new control, address, and data
lines.

Pin functions and descriptions for the development
device can be found in the Appendix.

with

Table 1-1.

Z8 fa.ily of Producta

ROM

Part
Pr\Jduct

NtJRber

Capacity
(Bytes)

Progr~le

I/O Pins

Dedicated
I/O Pins

PCB
footprint

C_nts

2K ROM

Z860l

2K

32, 4 ports

8 Power,
Control

40 Pin

Masked ROM part, used
primarily for high volume
production.

2K Protopack

Z8603

0

32, 4 ports

8 Power,
Control
plus
24 EPROM

40 Pin

Piggyback part used where
program flexibility is
required (prototyping).

4K ROM

Z86ll

4K

32, 4 ports

8 Power,
Control

40 Pin

Masked ROM part, used
primarily for high volume
production.

4K Development part

Z86l2

0

32, 4 ports

8 Power,
Control
plus 24
external
memory

64 Pin

ROM less part used primarily
in development systems.

4K Protopack

Z8613

0

32, 4 ports

8 Power,
Control
plus
24 EPROM

40 Pin

Piggyback part used where
program flexibility is
required (prototyping).

BASIC/
Debug

Z8671

2K

32, 4 ports

8 Power,
Control

40 Pin

BASIC/Debug part used in
low volume applications.

ROM less

Z8681/82

0

24, 3 ports

8 Power,
control
plus 8
external
memory

40 Pin

Low cost ROMless production
part with reduced I/O.
Program memory is external.

303

Z8 Family Overview

1.5 PROTOPACK EMULATOR (Z860J/1J)

1.7 ROHlESS MICROCOMPUTER (Z8681/82)

The Protopack emulator devices, l8603 and l8613,
are ROMless versions of their equivalent microcomputers (l8601 and l86l1, respectively). The emulators differ from development devices in two
ways: they use the same pinout as the microcomputers, and an external ROM or EPROM can be
plugged into the top of the package. The emulator
package allows for flexibility of application,
since it can be used in either prototype or final
pc boards, yet still allows for program development.

The l8681,and l8682 ROMless microcomputers provide
virtually all of the functions of the standard l8
microcomputer without the need to mask-program
on-chip ROM. This microcomputer is similar to the
l8601 version except that there is no on-chip 'program memory. Unlike the ROMless development and
Protopack devices the l8681/82 has no additional
address or address control lines nor does it carry
a plug-in piggyback memory module. Use of external memory rather than internal ROM enables this
l8 device to be used in low' volume applications or
where code flexibility is required.
The use of
Ports 0 and 1 to interface external memory leaves
16 to 24 lines for I/O.

When the final program is developed, it can be
mask-programmed into the l8601/11 which then
replaces the emulator. The emulator is also useful in small volume applications where the cost of
mask-programming is prohibitive or where program
flexibi·lit y is desired.
Physical description for the Protopack emulator is
found in the Appendix.

1.6 BASIC/DEBUG INTERPRETER (Z8671)
The l8671 MCU is a complete microcomputer preprogrammed with a 8ASIC/Oebug interpreter. . BASIC/
Debug can directly address the Z8671 , s, internal
registers and all external memory. It can quickly
examine and modify any external memory location or
I/O port. and can call machine language subroutines to increase execution speed.
The l8671 MCU has a combination of software and
hardware that is ideal for most industrial control
applications. Along with the functions mentioned
above, this microcomputer has a self-contained
line editor for interact i ve debugging which further speeds program development. In addition the
BASIC/Debug Interpreter allows program execution
on power-up or reset, without operator intervention.
Two kinds of memory exist in the l8671 device:
on-chip registers and external ROM or RAM.
The
BASIC/Debug interpreter is located in the 2K bytes
of on-chip ROM. Maximum addressing capability is
62K bytes of external program memory and 62K bytes
of data memory. In addition, 32 I/O lines, a 144byte register file, on-board UART and two counter/timers are provided.
Pin descriptions and functions are the same as
those for the l8601/11 basic microcomputer
(Chapter 6)'.

304

Since Port 1 is dedicated as an 8-bit multiplexed
Address/Data bus, and Port 0 lines can be programmed as address bits, the resulting 16-bit
addresses can directly address up to 64K bytes of
memory for the l8681 and 62K bytes for the l8682.
(The l8682 ,MCU cannot address the lower 2K bytes
of memory).
The address capabil ity of the l8681/82 can be
doubled by programming output P34 of Port J as
Data Memory (OM) select signal. The two states of
this signal can be used with the 16-bit addresses
to identify two separate external address spaces,
thus increasing external address space to 128K
. bytes for the l8681 and 124K bytes for the l8682.
Pin functions and descriptions for the l8681/82
microcomputer can be found in Chapter 7.

1.8 APPLICATIONS
l8 microcomputers are most often used in high-performance, dedicated applications. Such specialized functions were previously accomplished wittl
TTL logic, TTL logic plus a low-end MCU, or a
microprocessor and peripherals. Some typical
applications include.:

•
•
•
•
•
•
•
•
•
•
•

Disc drive controller
Printer cQntroller
Terminals
Modems
Industrial controllers
Key telephones
Telephone switching systems
Arcade games and intelligent home games
Process control
Intelligent instrumentation
Automotive mechanisms

Z8 Family Overview
Following are brief descriptions for a few Z8
applications.
Printers. Input data (typically transmitted via a
terminal or computer) can be sent to the Z8 on
either a serial or parallel port.
The ZB then
transfers the data into the external·, RAM buffer
via another parsllel port, where it can operate on
the data before output to the printing mechanism.

Disk operations are read or write, with
input received from either the disk or the computer. Data is tral'1sferred to the buffer memory a
sector (128, 256, 512, 1024 bytes) at a time via
the ZB, operated on as required, and subsequently
output to the disk or computer.
Disk.

Input is received from either the keyboard or a computer. The ZB device must maintain
at least an input buffer and often the screen RAM.

Te~l.

305

~Zim
2.1

'Chapter 2
Architectural Overview

INTIDllICTION

•
•
•

The Z8 is a versatile single-chip microcomputer.
Because its multiplexed address/data bus is merged
with several I/O-oriented ports, the Z8 can function as either an I/O-intensive or a memoryintensive microcomputer.
One key advantage to
this organization is that external memory can be
addressed ,while maintaining many of the' I/O
lines. 'Figure 2-1 shows the Z8 block diagram.

2.2

Program memory (internal and external)
Data memory (external)
Register file (internal)

A maximum of 64K bytes of program memory are
directly addressable.
In the Z8601 and Z8611
microcomputers, internal program memory consists
of a mask-programmed ROM.
The size of this'
internal ROM is 2K bytes for the' Z8601 and 4K
bytes for the Z8611.
In one member of the Z8
family, the Z8681, all of the program memory is
externally addressable.

IIIlORESS SPACES

Oat,a memory space is always external to the Z8
microcomputer and is 62K bytes in size for the
Z8601 and Z8682, and 60K and 64Kbytes in size
respectively for the Z8611 and Z8681.

To provide for both I/O-intensive and memoryintensive applications, the Z8 supports three
basic addrea,s spaces:

OUTPUT

Vce

XTAL

GND

AS

11
UART
FLAGS
TIMERI
COUNTERS
(2)
REG. POINTER

INTERRUPT
CONTROL

II I

I/O
(BIT PROGRAMMABLE)

ADDRESS OR I/O
(NIBBLE PROGRAMMABLE)

Figure 2-1.

306

ze

Block Diagr. .

ADDRESS/DATA OR I/O
(BYTE PROGRAMMABLE)

J

Architectural Overview
2.3

REGISTER FILE

The Z8's register-oriented architecture centers
around an internal register file composed of 124
general-purpose registers, 16 CPU and peripheral
control registers, and 4 I/O port registers. All
registers are eight bits.
Any general-purpose
register can be used as an accumulator, an address
pointer, or an index, data, or stack register.

Logical, Shift, Rotate and Load instructions operate on bytes in the register file. Bytes in data
memory are only affected by Load instructions.
Sixteen-bit arithmetic instructions (Increment
Word and Decrement Word) operate on words in the
register file.

2.3.4 Addressing Modes
2.3.1

The addressing modes of the Z8 CPU are:

Register Pointer

A Register Pointer logically divides the register
file into 9 working register groups of 16 regis-,
ters each, which allows for fast context switching
and shorter instruction formats.

2.3.2

•
•
•
•
•
•

Register
Indirect Register
Immediate
Direct Address
Indexed (with a short 8-bit displacement)
Program Counter Relative

Instruction Set

The Z8 CPU has an instruction set designed for the
large register file. The instruction set provides
a full complement of 8-bit arithmetic and logical
operations. BCD operations are supported using a
deCimal adjustment of binary values, and 16-bit
quantities for addresses and counters can be
incremented and decremented. Bit .manipulation and
Rotate and Shift instructions complete the data
manipulation capabilities of the Z8 system.
No
special I/O instructions are necessary since the
I/O is mapped into the register file.

2.3.3 Data Types

The Z8 CPU supports operations
digits, bytes, and 2-byte words.

on

bits,

BCD

Bits in the register file can be tested, set,
cleared, and complemented. Bits within a byte are
numbered from 0 to 7 with bit 0 being the least
significant (right-most) bit (Figure 2-2).

Figure 2-2.

Bits in Register

Register,
Indirect
Register,
and
Immediate
addressing modes are available for Load, Arithmetic, Logical, Shift, Rotate, and Stack instructions. Conditional Jumps use both Direct Address
and Program Counter Relative, while Jump and Call
instructions use Direct Address and Indirect Register addressing modes.

2.4

The Z8 has 32 pins dedicated to input and output.
These lines are grouped into four ports of eight
lines each.
Ports can be programmed as input,
output, or ,bidirectional. Under software control,
the ports provide timing, status signals, address
outputs, and serial or parallel I/O with or without handshake. Multiprocessor system configurations are also supported.

2.4.1

Tillers

To unburden the program from real-time problems
such as serial data communications and counting/
timing, the Z8 contains an on-chip universal asynchronous receiver/transmitter (UART) and two counter/timers with a large number of user-selectable
modes.
One on-chip timer provides the bit rate
input to the UART during communications.

2.4.2

Manipulation of BCD digits packed two-to-a-byte is
accomplished by a Decimal Adjust instruction and a
Swap instruction. Decimal Adjust is used after a
binary addition or subtraction on BCD digits.

I/O OPERATIONS

Interrupts

I/O operations can be interrupt-driven or polled.
The Z8 supports six vectored interrllpts that can
be masked and prioritized.

307

2.5 OSCILLATOR
The

Z8

offers

2.6 PROTOPACK
an

on-chip

oscillator

and

an

option~l power-down mechanism that can be used to

maintain the contents of the register file with a
low-power battery.

308

The Z8 Protopack allows the user to prototype
system hardware and develop software that is
eventually to be mask-programmed into the on-chip
ROM of the 2K byte (Z8601) or the 4K byte (l8611)
version of the lB.

Chapter 3
Address Spaces
3.1

Three address spaces
microcomputer:
•

.•

DEC

INTRODUCTION
are

available

in the

Z8

The CPU Register File contains addresses for
all general-purpose, peripheral, control, and
I/O port registers.
The CPU Program Memory contains addresses for
all memory locstions having executable code
and/or data.

HEX

IDENTIFIERS

255

STACK POINTER (BITS 7-0)

FF

SPL

254

STACK POINTER (BITS 15-8)

FE

SPH

253
252

REGISTER POINTER

FD

RP

PROGRAM CONTROL FLAGS

FC

FLAGS

251

INTERRUPT MASK REGISTER

FB

IMR

250

INTERRUPT REQUEST REGISTER

FA

IRQ

249

INTERRUPT PRIORITY REGISTER

F9

IPR

248

PORTS 0-1 MODE

F8

P01M

247

PORT 3 MODE

F7

P3M

246

PORT 2 MODE

F6

P2M

245

TO PRESCALER

F5

PREO
TO

244

TIMER/COUNTER 0

F4

The CPU Data Memory contains addresses for all
memory locations that hold data only.

243

11 PRESCALER

F3

PRE1

242

TIMER/COUNTER 1

F2

11

241

TIMER MODE

F1

TMR

These address spaces, are described in detail in
the following sections.

240

SERIAL I/O

FO

SIO

'.

NOT
IMPLEMENTED

'.

3.2

CPU REGISTER fILE

The regiater file totals 256 consecutive bytes, of
which 144 have been implemented. (Unused register
space is. reserved for future expansion.) The regi~ter file consists of 4 I/O ports (RO-R3), 124
general-purpose register.s (R4-R127), 9 peripheral
registers (R240-R248), and 7 control registers
(R249-R255). Figure 3-1 ahowa the layout of the
register file, including register names, locations, and identifiers.
Registers can be accessed as either 8- or 16-bit
registers using Direct, Indirect, or Indexed
addressing.
All 144 registers can be referenced
or modified by any instruction that accesses an
8-bit register, without the need for special
instructions. Registers accessed as 16-bits are
treated as ,even-odd register pairs (there are 72
valid pairs).
In this case, the data's MSB is
stored in the' evelil-numbered register, while the
. LSB goes into the next higher odd-numbered
register (Figure 3-2),

127

7F

GENERAL·PURPOSE
REGISTERS

4

04

3
2

PORT 3

03

P3

PORT 2

02

P2

PORT 1

01

P1

o

PORTO

00

PO

figure l-1.

MSB

LSB

Rn

Rn+1

Figure l-2.

Register file

I

n

=

EVEN ADDRESS

16-Bit Register Addressing

309

Address Spaces
By using logical instructions ,and a lIas,k, individual bits within registers can' be accessed for bit
set, bit clear, bit complement, or bit test operations. ror example, the instruction AND R, MASK
performs a bit clear operation.

e

Regist~rs

R243 end' R245-R249 are write-only
registers. If an attempt is I18de to read these
registera, Sff is returned (~ is a prefix that
indicates hexadecimal notation).

e When register R253 (Register Pointer) is read,
all Os are returned in the least significant
four bits.

When instructions are executed, registers sre read
when defioed ss sources and written when defined
es destinations.
All general-purpose registers
function as accumulators, address pointers, index
registers, stack areas, or scratchpad memory.

ze

instructions can access 8-bit registers and
register pairs (16-bit) using either 4-bit or
a-bit address fields. With 4-bit addressing, the
register file is logically divided into 9 groups
of 16 working registers as shown in rigure 3-3. A
Register Pointer (one of the control registers)
contains the base address of the active working
register group.

~-{

--{

When accessing one of the working registers, the
4-bit address is concatenated with the upper four
bits of the Register Pointer, thus forming an
8-bit address. figure 3-4 illustrates this operation.
Since working registers are typically
specified by short format instructions, there are
fewer bytes of code needed, which reduces execution time. In addition, when processing interrupts
or changing tasks, the Register Pointer speeds
context switching. A special Set Register Pointer
(SRP) instruction sets the contents of the Regis-,
ter Pointer.

3.Z.1

127

--I

--{

The lower
nibble of
the register

file address

{

--{
--{
--{

Error Conditions

Registers must be correctly used becsuse certain
conditions produce inconsistent results and ,should
be avoided:

by
.-t- provided
the instruction

pOints to the
specified
register.

1

t- - -

-1/0PORTS-

-

-

-- 3
0

Hgure 3-3. Working Register Groups

REGISTER R253

I
I

0

R6

0

0

'1

OPC
o

I

I

o 'INSTRUCTION
(INC R6)

o , REGISTER ADDRESS (Rlla)

-Figure 3-4. WorkiR.J Register Addr-iR.J

310

Address Spaces
•

When registers RO and R1 (Ports 0 and 1) are
defined as address outputs, they will return
1s in each address bit location when read.

•

Writing to bits which are defined as address
output, timer output, serial output, or handshake output will have no effect.

•

Instruction OJNZ uses a general register as a
counter.
Only registers R4-R127 can be used
with this instruction.

,., CPU CONTRII.

lIN)

PERIPtERAL REGISTERS

The ZS control registers govern the operation of
the CPU.
Any inetruction that references the
register file can access these control registers.
Available control registers are:
•
•
•
•
•
•
•

Interrupt Priority register (IPR)
Interrupt Mask register
(IMR)
Interrupt Request register (IRQ)
Program Control flags
(FLAGS)
Register Pointer
(RP)
Stack Pointer - high-byte (SPH)
Stack Pointer - low-byte (SPL)

The ZS uses a 16-bit Program Counter (PC) to
determine the sequence of current program instructions. The PC is not an addressable register.
Penpheral registers are used to transfer data,
configure the operating mode, and control the
operation of the on-chip' peripherals.
Any
instruction. that references the register file can
access peripheral registers. The peripheral registers are:
• Serial I/O
(510)
(TMR)
• Timer Mode
• Timer/Counter 0 (TO)
• TO Prescaler
(PREO)
• Timer/Counter 1 (T1)
• T1 Prescaler
(PRE1)
• Port 0-1 Mode (P01M)
• Port 2 Mode
(P2M)
• Port 3 Mode
(P3M)
In addition, the four port registers (PO-P3) are
considered to be peripheral registers.
The functions and applications of control and
peripheral registers are described in subsequent
sections of this manual.

'.4 CPU PROGRAM IEIIIRY

The ZS can accesa 64K bytea of program memory with
the 16-bit Program Counter.
In the ZS601, 'the
lower 2K bytes of the program memory address space
are internal ROM, while in the ZS611 the lower 4K
bytes are internal ROM. In the ZS6S2 the lower 2K
bytes are not accessible.
To access program memory outside the on-board ROM
space, Port 0 and Port 1 can be configured as a
memory interface. For example, Port 1 as a multiplexed Address/Data 'port (AOO-A07) provides
Address lines AO-A7 and Data lines 00-07' Port 0
can be configured for an additional four or eight
address lines (AS-A11 or AS-A15)'
This memory
interface is supported by the control lines AS
(Address Strobe), OS (Data Strobe) and R!W
(Read/Write) •
In the ROMless Z86S1 version, Port 1 is automatically a multiplexed Address/Data port.
Port 0
must be configured for additional address lines as
needed.
The. first 12 bytes of program memory are reserved
for the interrupt vectors. Addresses 0~11 contain
six 16-bit vectors that correspond to the six
available interrupta. Figure 3-5 illustrates the
order of 16-bit data stored in program memory.
85535
EXTERNAL
ROM OR RAM
2048

2047

,

• ON·CHIP
ROM

.'Locltlon
,instruction
rat byte of0

i"ci ~------------

executed

Ifter 1'8881

Interrupt
Vector
(Lower Byte)

Interrupt
Vector
(Upper Byte)

11

IRQ5

10

IRQ5

9

IRQ4

8

IRQ4

7

IRQ3

6

IRQ3

5 ~.

IRQ2

4".

IRQ2

3

IRQ1

2

IRQ1
IRQO

0

Figure 3-58.

IRQO

Z8601 Progr_ MI!IIory Map

311

65535
EXTERNAL
ROM OR RAM

LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED
AFTER RESET

4096
4095
Location of
first byte of
Instruction

executed
after reset

Interrupt
, Vector
{Lower Byte}

(Upper Byte)

~
2066
2065

ON·CHIP
ROM

11

IRQ5

10

IRQ5

9

IRQ4

8

IRQ4

7

IRQ3

~

IRQ2

3

IRQ1

2

IRQ1

IRQ4
JP
IRQ3
IRQ3
JP

IROO
IRQO

0

Figure l-5b.

IRQ5

JP

IRQ2'

4 ",

,,---------IRQ4

IRQ3

6

EXTERNAL
ROM OR RAM

IRQ5

~ ~------------

5
Interrupt
Vector

65535

Z8611 Progr_ MIRIll"Y Map

2056

IRQ2

2055

IRQ2

2054

JP

2053

IRQ1

2052

IRQ1

2051

JP

2050

IRQO

2049

IRQO

2048

JP

2047
NOT ADDRESSABLE

6 5535

Figure l-5d.

EXTERNAL
ROM OR RAM

When an' interrupt occurs, the address stored in
the interrupt's vector location points to a service routine.
This routine assumes program con-

Location of
first byte of
Instruction

executed
after reset

Interrupt

Vector
(Lower Byte)

Interrupt

Vector
(Upper Byte)

trol.

'ci ~-..;..---------11

IRQ5

10

IRQ5

9

IRQ4

8

IRQ4

7

IRQ3

6

IRQ3

5~
4",

IRQ2

3

IRQ1

2

IRQ1

IRQ2

IRQO
0

Figure l-5c.

312

Z8682 Progr. Manory Map

IRQO

Z8681 Progr_ MeIaory Map

The first 2K bytes of program memory are not
addressable
in
the Z8682 ROMless version.
Beginning st address 2048 the first 18 bytes
contain interrupt vectors which are Jump' Direct
instructions. When an interrupt occurs, the Z86BZ
executes the corresponding Jump to interrupt.
The first address available for a user program is
location 12.
This addreas is loaded into the
Program Counter after a hardware reset.
The first address available for a user program in
the ZB6B2 is location 2066 (Hexadecimal 1.:B12).
This address is loaded -into the Program Counter
after a hardware reset.

Address Spaces
3.5

CPU DATA tEIIIRY
85535

r------------,

Up to 64K bytes of external data memory can be
As shown in
accessed in the ZB microcomputer.
Figure 3-6, the origin, and hence, the actual size
of data memory is device-dependent. The origin of
date memory ie the same as ths starting address of
external program memory.
EXTERNAL
DATA
MEMORY
(80KBYTES)

Like external program memory, external data.memory
Address/Data lines are prov ided by Port 1 for
B-bit addresses, and by Ports 0 and 1 for 12-bit
and 16-bit addresses.
External data memory can be included with or separated from the external program memory addressing
space. When data memory is .separated from program
memory, the Data Memory output (OM) is used to
select between data and program memories.

~:t-----------------------i

85535 ...- - - - - - - - - - - , .

NOT ADDRESSABLE
O~

________________

~

Figure J.-6b.. Z8611 Data tt.cn-y Map

EXTERNAL
DATA
MIIMORY
(12K BYTES)

65535 _ - - - - - - - - - - _

~~----------------------i
NOT ADDRESSABLE
O~

________________

EXTERNAL
DATA
MEMORY
'(84K byte.)

~

Figure 3-6&. Z8601 or Z8682 Data MMory Map

O~__________________~

Figure~.

Z8681 Data MMory Map

313

Addr,ess Spaces

J.6 CPU STACKS
Stack operations can oc~ui 'in either the register
file or data memory'.
Under software control,
Port 0 and 1 Mode register (R258) selects stack
location.
The re~ister pair R254 and R255 forms the 16-bit
Stack Pointer (SP) which is used for all stack
operations. The st~ck address is stored with the
MSB in R254 and LSB in R255 (Figure J-7).
R255

1

_ _ _l_O_W_E_R_BY_T_E_ _ _ STACK POINTER lOW
R254

~___U_P_P_E_R_B_YT_'_E_ _....II1 STACK POINTER HIGH

Figure

'-7.

The stack address is decremented prior to s Push
operation and incremented after a Pop operation.
The etack address always points to the data stored
on the top-of-stack.
The Z8 stack is a return
stack for Call instructions and interrupts as'well
as a data stack. During a Call instruction, the
contents of the PC are saved on the atack. The PC
is restored during a Return instruction.
Interrupts cause the contents of the PC and Flag register to be saved on the stack. The IRET instruction restores them (Figure 3-8).
When the Z8 is configured for an internal stack
(i.e., using the register file), register R255
, serves as the Stack ,pointer. The value in R254 is
ignored and can be used as a general~purpose
register. However, an overflow or underflow can
occur when stack address is incremented or
decremented during normal stack operations.

Stack Pointer

TOPOF~

'••.

••
•

PCl

PCl

PCH

PCH

STACK
TOP O F _
STACK

FLAGS

STACK CONTENTS
AFTER A CAll
INSTRUCTION
,

Figure J-8.

314

Stack Operations

STACK CONTENTS
AFTElIAN
INTERRUPT
CYCLE

Chapter 4
Address Modes
4.1

The ZB
modes:
•
•
•
•
•
•

Pointer (R253) with the 4-bit working register
address supplied- by the instruction.

INTROOUCTIIIf
microcomputer

provides

six

addressing
Registers can be
values or memory
be specified as
range 0, 2, •••• ,

Register (R)
Indirect Register (IR)
Indexed (X)
Direct (D)
Relative (RA)
Immediate (1M)

used in pairs to designate 16-bit
addresses. A register pair must
an even-numbered address in the,
14.

Addressing
modes
are
instruction-specific.
Section 5.4 discusses each addressing made as it
corresponds to psrticular instructions.

With the exception of immediate data 'and condition
codes, all operands are expressed as register
f.i)e, program memory, or data memory addresses.
Registers are accessed using B-bit addresses in
the range 0-127 and 240-255.

In the fallowing definitions, the use of
"register" also implies register pair, working
register, or working register pair.

4.2 REGISTER ADDRESSING (R)
Working registers are accessed using 4-bit
addresses in the range 0-15. The address of the
register being accessed is formed by the concatenation of the upper four bits in the Register

PROGRAM MEMORY

•

8·BIT REGISTER
FILE ADDRESS
ONE·OPERAND
INSTRUCTION
E)(!,MPLE

~
L

dst
OPCODE

In the Register addressing made, the operand value
is the contents of the specified register or
register pair (Figures 4-1 and 4-2).

REGISTER FILE

OPERAND

POINTS TO ONE REGISTER
IN REGISTER FILE

-I

/

./

VALUE USED IN
INSTRUCTION EXECUTION

Figure 4-1.

Register Addressing

REGISTER FILE
RP

..

PROGRAM MEMORY

)

4·BIT WORKING
REGISTER \.

dot
TWO·OPERAND
INSTRUCTION
EXAMPLE

~

I
OPCODE

ore

POINTS TO THE
WORKING REGISTER

OPERAND

/

POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP

Figure 4-2. Working-Register Addressing

315

Address Modes
4.'

4.4

Ir,oIRECf REGISTER AOORESSINi (IR)

In the Indirect Register addressing mode, the contents of the specified register is the addresa of
the operand (Figures 4-3 and 4-4).
Depending upon the instruction selected, the
address points to a register, program memory, or
an external data memory' location.

I_XED AOORESSINi 00

The Indexed addressing mode is used only by the
Load (LD) instruction. -An indexed address consists
of a register address offset by the contents of a
designated working register (the Index).
This
offset is added to the register address to obtain
the address of the operand.
Figure 4-5 illuatrates this addresaing convention.
'

When accessing program memory or external data
memory, register pairs or working register pairs
are used to hold the 16-bit addresses.

8-BIT REGISTER
FILE ADDRESS

,

ONE-OPERAND
INSTRUCTION
EXAMPLE /

PROGRAM MEMORY

"...

de'
OPCODE

,

REGISTER FILE

POINTS TO ONE REGISTER
IN REGISTER FILE

#

ADDRESS

#

OPERAND

/

'.

ADDRESS OF
OPERAND USED
BY INSTRUCTION

/
VALUE USED IN
INTRODUCTION
EXEC UTION

figure 4-3.

Indirect Register Addressing to Register File

Figure '4-4. -Indirect Register Addressing to Pro9rBII or Data Mallory

316

Address Modes
4.5

DIRECT !IOORESSIIIC (DA)

The Direct addressing mode, as shown in Figure
4-6, specifies the address of the next instruction
to be executed.
Only the Conditional Jump' (JP)
and Call (CALL) instruct ions use this addressing
mode.

4.6

two's-complement signed displscement in the range
of -128 to +127. This is added to the contents of
the PC to obtain the address of the next
instruction to be executed. The PC (prior to the
add) consists of the address of the instruction
following the Jump Relat ive (JR) or Decrement and
Jump i f Nonzero (DJNZ) instruction. JR and DJNZ
are the only instructions that use this addressing
mode.

RELATIVE ADDRESSIIIC (RA)

In the R~lative addressing mode, illustrated in
Figure
4-7,
the
instruction
specifies
a

RP

PROGRAM MEMORY
TWO·OPERAND

INSTRUCTION-~t:~~~~~~~
__~~NnSTI~~~::~~~~~~~::~
EXAMPLE

POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP

OPERAND

VALUE USED IN
INSTRUCTION

Figure 4-5.

Indexed Addressing

PROGRAM MEMORY

PROGRAM MEMORY
PROGRAM MEMORY
'ADDRESS USED

~

PROGRAM MEMORY
ADDRESS USED

1
LOWER ADDR BYTE
UPPER AD DR BYTE

~J

NEXTOPCODE
DISPLACEMENT
JR OR DJNZ

OPCODE

OPCODE

Figure 4-6.

Dir~t

Addressing

Figure 4-7.

SIGNED
DISPLACEMENT
VALUE

Relative Addressing

317

4.7

IIIEDIATE DATA ADDRESSItii (1M)

Immediate data is corisic;lered an "addressing mode"
for the purposes of this discussion. It is the
only addressing mode that does not indicate a regiater or memory address as the source· operand; the
operand value used by the instruction is the value
supplied in the operand field itsel f. Because an
immediate operand is part of the instruction, it
is always located in the progrsm memory address
space.

318

WORDlS)

-_..

.....

. THE OPERAND VALUE IS IN THE INSTRUCTION.

figure 4-11.

I-mate Data Addressing

Chapter 5
Instruction Set
5.1

FUNCTIONAL

~y

ZB instructions can be divided functionally into
the following eight groups:
•
•
•
•
•
•
•
•

Load
Arithmetic
Logical
Program Control
Bit Manipulation
Block Transfer
Rotate and Shift
CPU Control

Logical Instructiona
MrteIIOI1ic
AND
COM
OR
XOR

Operands
dst,src
dst
dst,src
dst,src

Instruction
Logical And
Complement
Logical Or
Logical Exclusive Or

Program-Control Instructiona

The following summary shows the instructions
belonging to each group and the number of operands
required for each. The source operand is "src",
"dst" is the destination operand, and "cc" is a
condition code.

Mnemonic
CALL
DJNZ
I RET
JP
JR
RET

Operands
dst
r,dst

cc,dst
cc,dst

Instruction
Call Procedure
Decrement and Jump NonO
Interrupt Return
Jump
Jump Relative
Return

Bit-Hanipulation Instructions
Load Instructions
Mnl!llOf1ic
CLR
LD
LDC
LDE
POP
PUSH

Operands
dst
dst,src
dst,src
dst,src
dst
src

Instruction
Clear
Load
Load Constant
Load External
Pop
Push

Mnemonic
TCM
TM
AND
OR
XOR

Operands
dst,src
dst,src
dst,src
dst,sr'c
dst,src

Instruction
Test Complement Under Mask
Test Under Mask
Bit Clear
Bit Set
Bit Complement

Block-Transfer Instructions
Arithmetic Instructions
MneIIOI1ic
ADC
ADD
CP
DA
DEC
DECW
INC
INCW
SBC
SUB

Operands
dst,src
dst,src
dst,src
dst
dst
dst
d~t
dst
dst,src
dst,src

Instruction
Add With Carry
Add
Compare
Decimal Adjust
Decrement

Decrement Word
Increment
Increment Word
Subtract With Carry
Subtract

Mnemonic
LDCI

LDEI

Operands
dst,src

dst,src

Instruction
Load Constant Autoincrement
Load External Autoincrement

Rotate and Shift Instructions
Mnemonic
RL
RLC
RR
RRC
SRA
SWAP

Operands
dst
dst
dst
dst
dst
dst

Instruction
Rotate Left
Rotate Left Through Carry
Rotate Right
Rotate Right Through Carry
Shift Right Arithmetic
Swap Nibbles

319

Instruction Set
CPU Control Instructions
Mnetnonic

Instruction
Complement Carry Flag
Disable Interrupts
Enable Interrupts
No Operation
Reset Carry Flag
Set Carry Flag
Set Register Pointer

Operand

ccr
01

EI
NOP
RCF
SCF
SRP

src

5.2.1

Carry flag (C)

The Garry flag is set to 1 whenever the result of
an arithmetic operation generates a carry out of
or a borrow into the high order bit 7; otherwise,
the Carry flag is cleared to O.
Following Rotate and Shift instructions, the Carry
flag contains the last value shifted out of the
specified register.
An instruct ion can set, reset, or complement the
Carry flag.

5.2 PROCESSOR flAGS
The Flag register (R252) informs the user about
the current status of the Z8. The flags and their
bit positions in tt>e Flag register are shown in
Figure 5-1.

RETI changes the value of the Carry flag when the
saved Flag register is restored.
~

5.2.2 Zero flag (Z)

R252 FLAGS
Flag Register

For arithmetic and logical operations, the Zero
flag is set to-1 if the result is zero; otherwise,
the Zero flag is cleared.

(FCH; Read/Write)

~

I ~~::: :~:~::

L H A L F CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG

If the result of testing bits in a register is 0,
the, Zero flag is set to 1; otherwise the flag is
oleared.
If the result of a Rotate or Shift operation is 0,
the Zero flag is set to 1; otherwise, the flag is
cleared.

' - - - - - - - - S I G N FLAG
' - - - - - - - - - - Z E R O FLAG
L - - - - - - - - - C A R R Y FLAG

figure 5-1.

flag Register

The Z8 Flag register contains six bits of status
information which are set or cleared by CPU operations. Four of the bits (C, V, Z and S) can be
tested for use with conditional Jump instructions. Two flags (H, D) cannot be tested and are
used for BCD arithmetic.
The two remaining bits in the Flag register (F1,
F2) are available to the user, but they must be
set or cleared by instruction and are not usable
with conditional Jumps.
As with bits in the other control registers, Flag
register bits can be set or reset by instructions;
however, only those instructions that do not
affect the flags as an outcome of the execution
should be used (e.g., Load Immediate).

320

RET! changes the value of the Zero flag when the
saved Flag register is restored.

5.2.3 Sign flag (S)
The Sign flag stores the value of the most significant b-it of a result following arithmetic, logi~
cal, Rotate, or Shift operations.
When performing 'arithmetic operations .on signed
numbers, binary two's complement notation is used
to represent and process information. A positive
number is identified by a 0 in the most significant bit position, and therefore, the Sign flag is
also O.
A negative number is identified by a 1 in the most
significant bit pOSition, and therefore, the Sign
flag is alsb 1.
RET! changes the value of the Zero flag when the
saved Flag register is restored.

Instruction Set
5.2.4 Overflow flag (V)
For signed arithmetic, Rotate, and Shift operations, the Overflow flag is seL to 1 when the
result is greater than the maximum possible number
( > 127) or less than the minimum possible number
( < -128) that can be represented in two's compleThe flag is set to 0 if no overflow
ment form.
occurs.
Following logical operations, the Overflow flag is
set to O.
RET! changes the value of the Overflow flag when
the saved Flag register is restored.

encoded in a 4-bit field called the condition code
(CC), which forms bits 4-7 of the conditional
instructions.
Section 5.4.2 lists the condition codes and the
flag settings they represent.

5.4 NOTATION AND BINARV ENCODING
In the detailed instruction descriptions that make
up the rest of this chapter, operands and status
flags are represented by a notational shorthand.
Operands (condition codes and address modes) and
their notations are as follows:
Notation Address Mode

Actual Operand/Range

5.2.5 Decu.al-Adjust flag (D)
The Decimal-adjust 'flag is used for BCD arithmetic.
Since the algorithm for correcting BCD
operations is different for addition and subtraction, this flag specifies what type of instruction
was last executed so that the subsequent Decimal
Adjust (DA) operation can function properly. Normally, the Oecimal-adjust flag cannot be used as a
test condition.
After a subtraction, the Decimal-adjust flag is
set to 1; following an addition it is cleared to
O.

cc

Condit ion Code

See condition code
list below

r

Working register
only

Rn: where n

R

Register or
working register

reg: where reg represents a number in the
range 0-127, 240-255
Rn: where n

RR

RET! changes the value of the Decimal-adjust flag
when the saved Flag register is restored.

Register pair or
working register
pair

0-15

= 0-15

reg: where reg represents an even number
in the range 0-126,
240-254
RRp: where p
2, ••• ,14

5.2.6 Half-Carry flag (H)

0,

The, Hal f-carry flag is set to 1 whenever an, addition generates a carry out of bit 3 (Overflow), or
a subtraction generates a borrow into bit 3. The
Half-carry flag is used by the Decimal Adjust (DA)
instruction to convert the binary result of a previous addition or subtraction into the correct
decimal (BCD) result. As in the case of the
Decimal-adjust flag, the user does not normally
access this flag.

II'

Indirect working
register only

IR

Indirect register @ reg: where reg 1'epresents a number in
or working
the range 0-127,
register
240-255

RETI changes the value of the Half-carry flag when
the saved Flag register is restored.

11'1'

Indirect working
register pair
only

5.3 CONDITION CODES

IRR

Indirect register @ reg: where reg resents an even number'
pair or working
register pair
in the range 0-126,
240-254

Flags C, Z, S, and V control the operation of the
"conditional" Jump instructions.
Sixteen frequently useful functions of the flag settings are

@ Rn: where n

@ Rn: where n

0-15

= 0-15

@ RRp: where p
2, ••• ,14

@ RRp: where p

= 0,

0,

2, ••• ,14

321

Instruction Set
Notation Address Mode

Actual Operand/Range

5.4.1

For proper instruction execution, ZB PLZ/ASM
assembly language syntax requires th'lt "dst, src"
be specified, in that order.
The following
instruction descriptions show the format of the
object code produced by the assembler. This binary
format should be followed by users who prefer
manual program coding or who intend to implement
their own assembler.

x

Indexed

reg'(Rn): where reg
represent a number in
the range 0-127,
240-255 and n = 0-15

DA

Direct Address

addrs: where addrs
represents a number
in the range 0-65,535

RA

Relative Address

addrs: where addrs
represents a number
in the range +127,
-12B which is an
offset relative to
the address of the
next instruction

1M

Immediate

Udata: where data is
a number between
o and 255

Additional symbols used are:
SyRlbol
dst
src
@

Meaning
Destinat ion operand
Source operand
Indirect address prefix

SP
PC
FLAGS
RP
IMR
II

Stack Pointer
Program Counter
Flag register (R252)
Register Pointer (R253)
Interrupt mask register (251)
Immediate operand prefix

""

Hexadecimal number prefix
Opcode

OPC

Assignment of a value is indicated by the symbol
"(_". For example,
dst <- dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location.
The notation "addr(n)" is
used to refer to bit "n" of a given location. For
example,
dst (7)
refers to bit 7 of the destination operand.

322

Assembly language Syntax

Example: If the contents of registers %43 and %OB
are added and the result stored in %43, the
assembly syntax and resulting object cO,de are:
ASM:
OBJ:

ADD
04

%43, 1,OB
DB
43

(ADD dst, src)
(OPC src, dst)

In general, whenever an instruction format
requires an B-bit register address, that address
can speci fy any register location in the range
0-127, 240-255 or a working register RO-R15. If,
in the a,bove example, register 100B is a working
register, the assembly syntax and resulting object
code would be:
ASM:
OBJ:

ADD %43, RB
04 EB
43

(ADD dst src)
(OPC src dst)

For a more complete description of assembler syntax refer to the ZB PLZ/ASM Assembly Language
Manual (publication no. 03-3023-03) and ZSCAN B
User's Tutorial (publication no. 03-B200-01).

5.4.2

Condition Codes and flag Settings

The condition codes and flag settings are summarized in the following tables. Notation for, the
flags and how they are affected are as follows:

C
Z
S

Carry flag
Zero flag
Sign flag

*

V

Overflow flag
Decimal-adjust flag
Half-carry flag

X

D
H

0

Cleared to 0
Set to 1
Set or cleared
according to
operation
Unaffected
Undefined

Conditim Codes
Binary

0000
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001

"'-xlic

F

(blank)
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE

0001
1010 .
0010
1111

GT
LE
UGE

0111
1011
0011

ULT
UGT
ULE

LT

Meaning

flags Settings

Always false
Always true
Carry
No carry
Zero
Not 0
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or
equal
Less than
Greater Than
Less than or equal
Unsigned greater than
or equal
Unsigned less than
Unsigned greater than
Unsigned less than or
equal

C
C
Z
Z=
5
5
V
V

0

0
0
1
1
0
Z 1
Z=0
(5 XOR V)

(5
(Z
(Z
C

0

XOR V)
1
OR (5 XOR V»=O
OR (5 XOR V»=1
0

C
(C=O AND Z=O)
(C OR Z) = 1

323

Opcode Flags Aftected
Byte
(Hex)
CZSVDH

AddrMode

ADC dst,src
dst - dst + src +'C

(Note 1)

10

'It

'It

ADD dst,src
dst - dst + src

(No!e I)

00

'It

* 0 *

AND ds!,src
dst - dst AND src

(Note I)

50

0--

CALL dst
DA
SP-SP-2
IRR
@SP - PC; PC - dst

D6
D4

------

OR dst,src
dst - ds! OR src

(Note I)

40

CCF
C-NOTC

EF

*-----

POP dst
dst - @SP
SP-SP+I

R
IR

50
51

dst

arc

0

'It

Instruction
and Operation

Addr Mode
dBt

src

r
Irr

Irr

82
92

------

LDEI dst,src
Ir
dst .- src
Irr
r - r + 1; rr'- rr + 1

Irr
Ir

83
93

------

LDE dst,src
dst - src

NOP

FF
'It

0 - -

------

CLR dst
dst - 0

R
IR

BO
BI

PUSH src
SP - SP-I; @SP- src

COM dst
dst - NOT dst

R
IR

60
61

RCF
C-O

CF

0-----

CP dst,src
dst - src

(Note I)

RET
PC - @SP; SP - SP + 2

AF

------

OA dst
ds! - DA dst

R
IR

40
41

RL dst

R
IR

90
91

*

OEC dst
dst-dst-I

R
IR

00
01

RLCdst~I~

10
II

OECW dst
dst - dst-I

RR
IR

80
81

~~

EO
EI

RRCds!~I~

CO
CI

SBC ds!,src
dst-dst-src-C

30

01
IMR (7) - 0

DINZ r,dst

AD

8F
RA

rA
r=O-F

r - r - 1

'It

X- -

- * •

RR dst

------

- - - -.-

EI
IMR (7) - I

9F

INC dst
dst-dst+1

INCW dst
dst - dst +

R
IR

rE
r=O-F
20
21

RR
IR

AO
Al

-----_'

'It

* * __

-

'It

'It

'It

__

******

If cc,dst

cD
c=O-F
30

------

cB
c=O-F

------

rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5

------

if cc is true
PC - ds!
IR cc:dst
if co is true
PC-PC+dst
Range: + 127, -128

IRR
RA

I

LD dst,src
dst - src

r
R

r

X
r
Ir
R
R
R
IR
IR

1M
R
X
r
Ir
r
R
IR
1M
1M
R

~I~

SRP src
RP.- src

1m.
(Note I)

SWAPdst ~ R
IR

70
71

Irr

C2
D2

------

LDCI dst,src

Ir

Irr
Ir

C3
D3

------

'It

* * __

* I *

DF

I - - -

DO
DI

* * * 0

31

-,-----

20

'It

'It

* * 1 *

FO
FI

X * * X - -

TCM dst,src
(NOT ds!) AND src

(Note I)

60

- * * 0

TM dst,s'rc

(Note I)

70

-

(Note I)

BO

,- * * 0 - -

* * 0

dst AND src
XOR dst,src
dst - dst XOR src

Nole 1
These instructions have an' Identical set of addressmg
modes, which are ,encoded for breVity. The hrst opcode
nibble 15 found m the lDstructIon sel table above. The
second mbble IS expressed symbolically by a L In thiS
table, and its value IS found In the followmg table to the
left of the apphcable addressing mode pair.
For example, to determine the opcode of an ADC
instruction uSing the addressmg modes r (destmatlon) and
If (source) IS 13.
'

dsl

sre

R
R
R
IR

Ir
R
IR
1M
1M

Lower

Opeode Nibble
I

r
Irr

Irr
dst - src
r-r+l;rr-rr,+l

(Note 1)

Addr Mode

dst - src

LDC dst,src

SRA dst

SUB dst,src
dst - dst - src

IRET
,
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR (7) - 1
DA

1!l..I:DJ

R
IR

IICF
C-I

ifn> 0
PC-PC+dst
Range: + 127, -128

324

Opcode Flags Affected
Byte
(Hex)
CZSVDH

Instruction
and Operation

d.
~f
~

:I
:I.

5.6Z8

ADC

Instruction
Descriptions
and Formats
ADC

Add With Carry

dst,src

Instruction For.at:

I

ope

I

ope

r-

ope

Operatioo :

Cycles

II
II
II
dst

dst

<-- dst

src
src
dst

I
II
II

6

IIPC

Address Mode

dIIt

arc

13

r
r

r
Ir

(Hex)

12

dst

10

14
15

R
R

R
IR

src

10

16
17

R
1R

1M
1M

+ src + c

The source operand, along with the setting of the e flag, is added to the destination
operand and the sum is stored in the destination. The contents of the source are not
affected. Two's complement addition is performed. In multiple precision arithmetic,
this instruction permits the carry from the addition of low-order operands to be
carried into the addition of high-order operands.

Flags:

e:

Set i f there is a carry from the most-significant bit of the result; cleared
otherwise
Set if the result is zero; cleared otherwise
Set if the result is negative; cleared otherwise
Y: Set i f arithmetic overflow occurs, that is, if both operands are of the same sign
and the result is of the opposite sign; cleared otherwise
0: Always cleared
H: Set if there is a carry from the most-significant bit of the low-order four bits
of the result; cleared otherwise

Z:
S:

Example:

If the register named SUM contains %16, the e flag is set to 1, working register 10
contains %20 (32 decimal), and register 32 contains %10, the statement
ADe SUM,IIR10
leaves the value %27 in Register SUM.
cleared.

Note:

The e, Z,

s,

V, 0, and H flags are all

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

src/dst

325

ADD

Add
ADD

dst,src

Instruc:t:ion FoNat:

Cycles

ope

II

ope

II
II

ope

Operation:

dst

' src
src
dst

I
II
II

OPC

Adcireaa Mode

clat

arc

6

02
03

r
r

r
Ir

dst

10

04
05

R
R

R
lR

src

10

06
07

R
lR

1M
1M

(H!tx)

dst <-- dst + src
The source operand is added to the destinstion opersnd snd the sum is stored in the
destination. The contents of the source are not affected. T~ols complement addition
is performed.

Flags:

C:
Z:

V:
S:

H:
D:

[x8lllple:

Set if there was a carry from the most-significant bit of the result; cleared
otherwise
Set if the result is zero; cleared otherwise
Set if arithmetic overflow occurs, that is, if both operands are of the same sign
and the result is of the opposite sign; cleared otherwise
Set if the result is negative; cleared otherwise
Set if a carry from the low-order nibble occurs
Always reset to 0

If the register named SUM contains 1'044 and the register named AUGEND contains 1'011,
the statement
ADD SUM,AUGEND
leaves the value 1'055 in register SUM and leaves all flags cleared.

Note:

When used to ,specify a 4-bit working-register address, address modes R or IR use the
format:
E

326

src/dst

AND
Logical
AN>

dat,arc

Instructian Fmwat:

OPC

ope
ope

Operatian:

Cycles

II
II
II
dat

<--

dat

arc
arc
. dst

I
II
II

6

II'C
(Hex)

52
53

dat

10

54

55

arc

10

56
57

McirllSS Mode
dst
arc

r
r

r
IR

R
R

R
1R

R
IR

1M
1M

dat AND arc

The aource operand is logically ANDed with the. des,tination operand. The reault is
atored in the destination.
The AND operation results in a 1 bit being stored
whenever the correaponding bits in the two operands are both 1s; otherwise a 0 bit is
stored. The contents of the source bit are' not affected.

Flags:

e:

Unaffected

Z: Set if the result is zero; cleared otherwise
Y: Always reset to 0

S: Set if the result bit 7 ia set; cleared otherwise

H: Unaffected
D:

EXSlllple:

Unaffected

If the source operand is the immediste value %76 (01111011) and the register named
TARGET contains %e3 (11000011), the statement
AND TARGET, #%76
leaves the value %43 (01000011) in register TARGET.
cleared.

Note:

The Z, V, and 5 flags are

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

src/dst

327

CALL
Call Procedure
CAlL

dst

Instruction for.at:

~_____O_P_C____~1 I~______________ds_t____________~
~_____o_p_c____~l ~I

Operation:

______

sp <-- sp asp <-- PC
PC <-- dst

d_s_t____

~

Cycles

OPC
(Hex)

Address Mode
dst

20

06

OA

20

04

IRR

2

The current contents of the PC are pushed onto the top of the stack, The PC value
is the address of the first instruction following the CALL instruction,
The
speci fied destinatil'n address is then loaded into the PC and points to the first
instruction of a procedure,
At the end of the procedure a 'RfTurn instruction can be used to return to the
original program flow, RET pops the top of the stack back into the PC,

flags:

No flags affected,

Example:

If the contents of the PC are %1A47 and the contents of the SP (control registers
254-5) are %3002, the statement
CALL %3521
causes the SP to be decremented to %3000, %1A4A (the address following the
instruction) is stored in external data memory %3000-%3001, and the PC is loaded with
~n521,
The PC now points to the address of the first statement in the procedure to
be executed.

Note:

When used to specify a 4-bit working-register pair address, address mode IRR uses the
format:
E

328

dst

CCF
Complement Carry Flag
ccr
Instrucl:ion

r Orllllt:

OPe

Cyclea

Opc

Operation:

6

C

<--

(Hex)

Ef

NOT C

The C flag is complemented; if C

1, it is changed to C

Flags:

c:

EXlIIIIP le :

Tf the C flag contains a U, the statement

0, and vice-versa.

Complemented
No other flags affected

CCf

will change the 0 to 1.

329

CLR
Clear
CLR

dst'

OPC

Addreaa Mode

Cycles

(Hex)

dst

6

60
61

Instruction F01'1l8t:

~_____O_P_C______~1 I~

Operstion:

dst

______

<--

d_s_t__~__~

R

IR

0

The destination location is cleared to O.

flsgs:

No flags affected.

EX8llP1e:

If working register 6 contains

~Ar,

the statement

ClR R6

will leave the value 0 in that register

Note:

When used to specify a 4-bit working-register address, address modes 'R or IR use the
format:
E

330

dst

COM
Complement
COH

dst

Instruction ror.at:
Cycles
L-______
OP_C______

Operation:

~I

ds_t______~

6

LI_ _ _ _ _ _ _

OPC
(Hex)

Address Mode
dst

60
61

R

IR

dst <-- NOT dst
The contents of the destination location are complemented (one's complement); all 1
bits are changed to 0, and vice-versa.

Hags:

C:
Z:
V:
5:
H:

0:

EX8lllple:

Unaffected
Set if the result is zero; cleared otherwise
Always reset to 0
Set if result bit 7 is set; cleared otherwise
Unaffected
Unaffected

If working register '8 contains %24 (00100100), the statement
COM R8
leaves the value %DB (11011011) in that register.
the S flag is set.

Note:

The Z and V flags are cleared and

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

dst

331

CP
Compare
CP

dst,src

Instruction For.at:

OPC
Cycles

OPC
OPC
OPC

Operation:

II
II
II

dst

Brc
src
dst

I
II
II

(lex)

Addresa Mode
dat
arc

6

A2
A3

r
r

r
Ir

dst

10

A4
A5

R
R

R
IR

src

10

A6
A7

R
IR

1M
1M

dst - src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags set accordingly. The contents of both operands are unaffected by
the comparison.

Flags:

C:

Z:
V:
S:

H:
0:

Ex....,le:

Cleared if there is a carry from the most significant bit of the result; set
otherwise, indicating a "borrow'·
Set if the result is zero; cleared otherwise
Set if arithmetic overflow occurs; cleared otherwise
Set if the result is negative; cleared otherwise
Unaffected
Unaffected

If the register named TEST contains %63, working
decimal), and register 48 contains %63, the statement

register

a

contains %30

(48

CP TEST, liRa
sets (only) the Z flag.
jump is taken.

Note:

If this statement is followed by "JP EQ, true_routine", the

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

332

src/dst

DA

Decimal Adjust
DA

dst

Instruction r _ t :

OPe

--J1

~_____O_P_C____

op.ratian:

I~

dst

____,_d_s_t____~

AdcIreu Mode'

Cyel..

(flllx)

det

8

40

R
IR

41

<-- DA dst

The destination operand is adjusted to form two 4-bit BCD digits following a binary
addition or subtrsction operation on BCD encoded bytes. For addition (ADD, ADC), or
aubtraction (SUB, SBC), the following table indicates the o,paration parformed:

Bita 1t-7
Instruction

ADD
ADC

Carry

Value

Before DA

(Hex)

0
0
0

0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3

D

0
0
1
1
1

SUB
S8C

0
0
1
1

0-9
0-8
7-F'
6-F'

Bita

Hnag

0-,

N..ber

Value

Addad

Cerry

Before DA

(flllx)

To Byte

After DA

0
0

0':9
A-F'
0-3
0-9
A-F
0-3
0-9
A-F
0-3

00
06
06
60
66
66
60
66
66

0
0
0

0-9
6-F
0-9
6-F

00
FA

0
0

AD '.

1
1

1

0

b
1

0
0
1

0
1

0
1

9A

1
1
1
1
1
1

If the destination operand is not the reault of a valid addition or aubtraction of
BCD digits, the operation is undefined.

Flags:

C:

Set if ,there is a carry from the most significant bit; cleared otherwise (see
table above)
Z Set if the result is 0; cleared otherwise'
V Undefined
5 Set if the result bit 7 is set; cleared otherwise
H Umiffected
o .Unaffected

333

If addition is performed I!Sing the BOO values 1,5 and 27, the result should' be 42.
The sum is incorrect, 110wever, when the binary representations are added in the
location I!sing standard binary arithmetic.
'

desti~ation

0001 0101
+ 0010 0111'
~ lll!lI'

= "J~

The - DA ststement adj4sts this result eo thst the correct BCD representation is,
obtsined.
0011
+ 0000

1100
0110

lTflm l!!ml' = 42

The C, Z, and 5 flags

Note:

~re

clesred and V is undefined.

When used to specify a ,4-b1t working-register address, address modes R or IR use the
format:
E

334

dst

DEC
Decrement
DEC

dat

Instruction For.at:
Cycle'a

~_____O_P_C____~11~

Operation:

dst

______

<--

d_s_t____

~

6

OPC
(Hex)

Address Mode

00
01

R

dat
IR

dst - 1

The destination operand's contents are decremented by one.

Flags:

C: Unaffected
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurred; clesred otherwise
5:

Set if the result is negative; cleared otherwise

0:

Unaffected

H: Unaffected

EX8llple:

If working register 10 contains \'02A, the statement
DEC R10
leaves the value \'029 in that register.

Note:

The Z, V, and S flags· are cleared.

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

dst

335

DECW
Decrement Word
DECW dst
IllBtructi... r onat:

OPC

Address Mode

Cycles

(Hex)

dat

10

80

RR
IR

~_____O_P_C____~1 I~______d_s_t____~

Qst

<-- dat -

81

1

The contents of the destination location (which IIlJst be an even address) and the
operand following that location are treated as a single 16-bit value which is
decremented by' one.

Flags:

C:

Unaffected

S:

Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise
Y: Set if arithmetic overflow occurred; cleared otherwise

H: Unaffected
D: Unaffected

EXIIIIIP1e:

If working register 0 contains %30 (48 decimal) and registers 48-49 contain the value
%fAF3, the statement
OECW IRO

leaves the value %FAF2 in registers 48 and 49.
is set.

336

The Z and V flags are cleared and S

01
Disable Interrupts
OJ

Instruction For.at:

ope

Operation:

IMR (7)

Cycles

OPC
(Hex)

6

SF

<-- 0

Bit 7 of control register 251 (the Interrupt Mask Register) is reset tQ O.
All
interrupts are disabled, although they remain potentially enabled (i.e., the Global
Interrupt Enable is cleared--not the individual interrupt level enables.)
Flags:

No flags affected

EX8lllple:

If control register 251 contains %8A (10001010, that is, interrupts IRQ1 and IRQ3 are
enabled), the statement
01

sets control register 251 to %OA and disables these interrupts.

337

DJNZ
Decrement and Jump if Nonzero
DJNZ

r,dst

Instruction Format:

OPC

Cycles

~__r__~~_O_p_C__~11~

_______

ds_t______

~

(Hex)

12 if jump taken
10 if jump not taken

rA

Address Mods
dst

RA

r=O to F

Operation:

r

<--

If r

~

r - 1
0, PC

<--

PC + dst

The working register being used as a counter is decremented. If the contents of the
register are not zero after decrementing,' the relative address is added to the
Program Counter (PC) and control passes to the statement whose address is now in the
PC. The range of the relative address is +127, -128, and the original value of the
PC is the address of the instruction byte following the DJNZ statement. When the
working register counter reaches zero, control falls through to the statement
following DJNZ.

Flags:

No flags affected

Example:

DJNZ is typically used to control a "loop" of instructions.
In this example, 12
bytes are moved from one buffer area in the register file to another.
The steps
involved are:
o
o
o

Load 12 into the counter (working register 6)
Set up the loop to perform the moves
End ,the loop with DJNZ

LD R6, 1112
LOOP: LD R9,OLDBUF (R6)
LD NEWBUF (R6),R9
DJNZ R6,LOOP

Note:

338

! Load Counter!
! Move one byte to!
I New location!
!Decrement and !
!Loop until counter

O!

The working register being used as a counter must be one of the registers 04- 7f •
Use of one of the I/O ports, control or peripheral registers will have undefined
results.

EI
Enable Interrupts
El

Instruction r or.at:

Cyclss

ope

Operation:

6

IMR (7)

"c

(lIIIx)

9f

<-- 1

Bit 7 of control register 251 (the Interrupt Mask Register) is set 10 ,to 1.
allows any potentially enabled interrupts to become enabled.

This

Flags:

No flags affected

[,,,..pIe:

If control register 251 contains ~OA (00001010, that is, interrupts IRQ1 and IRQ)
potentially enabled), the statement
EI

sets control register 251 to %8A (10001010) and enables these interrupts.

339

INC
Increment
"INC

dst

Instruction Foraet:
dst

OPC

OPC

L-~____OP_C______~II~

Operation:

dst

_______

<--

ds_t______~

Cycles

(Hex)

6

rE
r=O to r

6

Address Mode
dst

20
21

r
R
IR

dst + 1

The destination operand I s contents are incremented by one.

Hags:

C:

Unaffected

Z: Set if the result is zero; cleared otherwise
V:

S:
H:

D:

Exa...,le:

Set if arithmetic overflow occurred; cleared otherwise
Set if the result is negative; cleared otherwise
Unaffected
Unaffected

If working register 10 contains %2A, the statement
INC R10

leaves the value %26 in that register.

Note:

When used to specify a 4-bit
format:

E

340

The Z, V, and S flags are cleared.

working~register

det

address, address modes R or IR use the

INCW
Increment Word
III:If dst
Instruction fonat:

Cyel..

~_____O_p_c____~1 ~I

Operation :

______

d_s_t____~

10

OPe
(lI8x)

AD
A1

IIddreaa IIode
det

RR
IR

dst <-- dst + 1
The contents of the destination (which must be sn even address) and the byte
following that location are treated as a aingle 16-bit value which ia incremented by
one.

Hags:

c:

Unaffected
Set i f the result is zero; cleared otherwise
Y: Set if arithmetic overflow occurred; clesred otherwise
5: Set if the result is negative; cleared otherwise
H: Unaffected
D: Unaffected
Z:

EX8q)le:

If working-registsr pair 0-1 contains the value

~AF3,

the statement

INCW RRO
lesves the value %FAF4 in working-register pair 0-1.
and 5 is set.

The Z and V flaga are cleared

341

IRET
Intertupt Return
IRET
Instruction Forlllat:

Cycles
16

OPC

Operetion:

OPC
(Hex)
BF

FLAGS <-- liSP
SP <-- SP + 1
PC <-- liSP
SP <-- SP + 2
IMR (7) <-- 1

This instruction is issued at the end of an interrupt service routine. It restores
the Flag reqister (control register 252) and the PC.
It also reensbles any
interrupts that are potentially enabled.

Flegs:

344

All flags are restored to original settings (before interrupt occurred).

JP

Jump
JP

cc,dst

~ructian

forab

Cyclea

Conditionsl

_________
I~___

~_c_c____~_~
__C__~1 I~
Unconditionsl

~___O_PC____~I

Operatian :

d_s_t__________~

12 if jump tsksn
10 if jump not tsksn

d_st____~

B

OPe

Addreea Mode

(Hex)

det

ccO

OA

cc=o to r
JO

IRR

If cc is true, PC <-- dst
A conditionsl jump transfers Progrsm Control to the destination address if the
condition specified by "cc" is true; otherwise, the instruction following the JP
instruction is executed. See Section 6.4 for s list of conditiOn codes.
The unconditionsl jump simply replsces the contents of the Progrsm Co~nter with the
contents of the specified register pair. 'Control then passes to the ststement
eddressed by the PC, decremented by one.

flags:

No flsgs sffected

EXlIIIPle :

If the csrry flsg is set, the statement
JP C,I!&1520
replaces the contents of the Program Counter with "1520 and transfers control to that
locati~n.
Had the carry flag not been set, control would have fallen through to the
ststement following the JP.

Note:

When used to specify a 4-bit working-register pai'r address, addresa mode IRR uses the
format:
E

dat

343

JR
Jump Relative
JR,

cc,dst

Instruction FOrMt:

Cycles

~_c_c__~~_O_p_C__~1 I~

_____

d_s_t______

~

12 If jump taken
10 If jump not taken

OPC

Address Mode

(Hex)

dat

ccB

RA

cc=O to F

Operation:

If cc is true, PC

<-- PC

+ dst

If the condition specified by "cc" is true, the relative address is added to the

PC and control passes to the statement whose address in now in the PC; otherwise, the
instruction following the JR instruction is executed. (See Section 5.3 for a list of
condition codes). The range of the relative address is +127, -12B, and the original
value of the PC is taken to be the address of the first instruction byte following
the JR statement.

Flags:

No flags affected

EXllllple:

If the result of the last arithmetic operation executed is negative, the following
four statements (which occupy a total of seven bytes) are skipped with the statement
JR MI,$+9
If the result is not negative, execution continues with the statement following the
JR. A short form of a jump to label LO is
JR LO
where LO must be within the allowed range.
case, and is assumed to be "always true."

344

The condition code is "blank" in this

LD
Load
LD

dBt,Brc

Instruction For.at:
Cycles
dst

OPC

Brc

6
6

arc

OPC

dat

6

OPC

dBt

src

OPC

Brc

OPC

dst

OPC

Brc

OPC

dst

x

OPC

src

x

I
I
I
I

Addresa Mode
dat
arc

OPe
(Hax)

rC
rB
r9
r=O to f

r
r

1M
R

R*

r

6
6

E3
f3

r
Ir

Ir
r

dat

10
10

E4
E5

R
R

R
IR

arc

10
10

E6
E1

R
IR

1M
1M

dat

10

f5

IR

R

Brc

10

C7

r

X

dst

10

07

X

r

*In this instance only a full B-bit register address can be used.

Operation:

dst

<--

arc

The contents of the lIource are loaded into the destination.
source are not affected.

The contents of the

Flags:

No flags affected

EXlllllple:

If working register 0 contains %08 (11 decimal) and working register 10 contains %BJ,
-the statement
LO 240(RO) ,R10
will load the value %83 into register 251 (240 + 11). Since thiB is the Interrupt
Mask register, the Load statement haa the effect of enabling IRQO and IRQ1.
The
contents of working regillter 10 are unaffected by the load.

Note:

When used to specify a 4-bit working-register address, address modes R Dr IR use the
format:
E

src/det

345

LDC
Load Constant
LDC

dst,src
OPe

lnatructioR Ftll'II8t:
Cycles

opc
ope

Operation:

II
II
dst

dst
src

I
I

(Hex)

Address Mode
clat ' arc

src

12

C2

r

lrr

dst

12

02

Ir·r!

r

<-- src

This instruction is used to losd a byte constant from program memory into a working
register, or vice-versa. The addreas of the program memory location is specified by
a working register pair. The contents of the aource are not affected.

No flags affected

EX8lllPle:

I f the working-register pair 6-7 contains
contains the value ~22, the statement

~}0A2

and program-memory location

~30A2

. LOC R2, IRR6

loads the value ~22 into working register 2.
unchanged by the load.

346

The value of location

~30A2

is

LOCI
Load Constant Autoincrement
LOCI

dst,src

Instruction ronal::
Cycles

OPC
OPC

Operation:

II
II

II'C
(Hex)

Add1'tl8ll Mode
det 8rc

dst

src

18

C3

Ir

Irr

src

dst

18

03

Irr

Ir

<-- src
<-- r + 1
rr <-- rr +

dst
r

This instruction is used for block trsnsfers of dsts between program memory and the
regiater file.
The address of the program-memory location is spec! Hed by a
working-register pair, and the address of the register-file location is apecified by
a working register.
The contents of the aource location are loaded into the
destination locetion.
Both addresses are then incremented automatically.
The
contents of the aource are not affected.

Flags:

No flags affected

Ex8llple:

I f the working-register pair 6-7 contains !1130A2 and program-memory' locations !1130A2
and !1130A3 contain !1122BC, and if working register R2 contains %20 (32 decimal), the
statement
LOCI aR2, aRR6

loads the value !1122

int~

register 32.

A second

LOCI aR2, IIRR6

loads the value %BC into ,register 33.

347

LDE
Load External Data
lDE

dst,erc;

OPC

Instruction For. .t:
Cycles

' -_ _ _
oP_c_ _ _-'

L-______O_P_c______

Operstion:

~1

I
I

dst

<--

(Hex)

Address Mode
dst
src

dst

arc

12

82

r

Irr

src

det

12

92

Irr

r

src

Th~s

instruction is used to load a byte from external data memory into a working
register or vice-versa.
The addreas of the external datll-memory location is
specified by a working-register pair. The contents of the source are not affected.

Flags:

No flags affected

EXIIIIP1e :

If the working-register pair 6-7 containa %404A and working register 2 contains %22,
the statement

LDE IRR6,R2
loads the value %22 into external data-memory location %404A.

348

LDEI
Load External Data Autoincrement
LDEI

dat,arc

Instruction for.at:

Cycles
OPC
OPC

Oparstian:

II
II

OPe
(Hax)

Addreu Mode

dat

arc

dat

src

18 '

83

Ir

Irr

arc

dat

18

93

Irr

Ir

dat <-- arc
r

<--

r + 1

rr <-- rr +

Thia instruction is uaed for block transfera of data between external data memory
and the register file. The addreas of the external data-memory location is specified
by a working-register pair, and the address of the register fUe location is
specified by a working register. The contents of the source location are loaded into
the destination location. Both addresses are then incremented automatically. The
contents of the source are not affected.

flags:

No flsgs sffected

EXllq)le:

If the working-register pair 6-7 contains ~404A, working register 2 contains
decimal), and registers 34-35 contsin ~BC3, the statement

~22

(34

LOEl 8RR6,IR2
loads the value

~B

into external location

~04A.

A eecond

LDEI IRR6,IR2
Note:

loads the value ~C3 into external location ~404B.
When used to specify a 4-bit working-register pair address, address modes RR or IR
uae the format:
E

dst

349

NOP
No Operation

Instruction f orat:
Cycles
o~c

6

Operation:

No action is performed by this instruction.

Flega:

No flags affected

350

OPC,
(Hex)

FF

It is typicslly used for

ti~ng

delays.

OR
Logical Or
DR

det,arc

lnetruction FoNat:

OI'C

Cyelee

ope
ope
ope

Operation:

II
II

II

det

erc
erc
dst

II
II

(lIItx)

Address Mode

dat

ere

r

6
6

42
43

r

r
Ii-

det

10
10

44
45

R
R

R
lR

src

10
10

46
47

R
lR

1M
1M

dst <-- det OR src
The source operand is logicslly ORed with the destination operand and the result is
stored in the destination. The contents of the aource are not affected. The OR
operation reaults in a one bit being atored whenever either of the correaponding bits
in the two operands ia 1; otherwise a 0 bit ia stored.

c:

Flags:

Unaffected
Z: Set if result is zero; cleared otherwiae
V: Always raset to 0
5: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
D: Unaffected

EX8lllPle:

If the source operand is the immediate value !.I7B (01111011) and the register named
TARGET contains !.\C3 (11000011), the statement
OR TARGET,ft7B
leaves the value !.\FB (11'111011) in regieter TARGET.
and S is set.

Note:

The Z and V flaga are cleared

When used to specify a 4-bit working-register address, address modes Rand IR use the
format:
E

src/dst

351

POP
~op
PII'

dst

Instruction For8Bt:
Cycles

~____O_P_C____~11~

______

<-- asp
sp <-..: SP +

OperatiOll :

ds_t____~

10
10

OPe
(Hex)

Address Mode

50

R

51

IR

dst

dst

1

The contents of the location addressed by the 'SP are loaded, into the destination.
The SP is then incremented automatically.

No flags affected

Flags:

If the SP (control registers 254-255) containa' ~1000, external data-memory location
contains ~55, and working register 6 contains ~22 (34 decimal)', the atatement

ExBIIIPle:

~1000

POP aR6
loads the value 1.155 into register 34.
1111001.

Note:

When uaed to specify a 4-bit working-register address, addreas modes R or IR use the
format:

•

352

After the POP operation, the SP contains

E

dst

PUSH
Push
PUSH src
Inatructian fDNBt.:

eyel.

~_____o_p_c____~1 I~

Operatian:

______s_r_c____~

10 Internsl
12 External
12 Internal
14 External

steck
atack
steck
atack

OPC
(IIIIX)

Addr_ MDcIe

70

R

71

IR

ere

SP <-- SP - 1
asp <-- src
The contents of the SP are decremented, then the contente of the source ere loaded
into the location addressed by the decramented SP, thus adding a n~w element to the
top of the steck.

flaga:

No flags affected

.Ex..,le:

If the SP contains

~1n01,

the statement
PUSH fLAGS

stores the contents of the register nsmed fLAGS in location
operation, the SP contains ~1000.

Note:

~1000.

After the PUSH

When used to specify a 4-bit working-register address, addresa modes R or IR use the
format:
E

arc

353

ROP
Reset Carry Flag

Instruction r ol'llBt::

ope

Operation:

C

<--

Cyclea

IJPC
(Hax)

6

cr

0

The C flag is reset to 0, regardless of its previous vslue.,

nags:

354

C:

Reset to 0
No other flegs affected

RET
Return
RET

opt

Instruction For.at:
OPC

Operation:

Cyel..

(Hex)

14

AF

PC <-- asp

sp <-- SP + 2

This instruction is normally used to return to the previously e~ecuted procedure at
the end of a procedure entered by a CALL instruction. The contents of the location
addressed by the SP are popped into the PC. The next statement executed is that
addressed by the new contents of the PC.

Flaga:

No flags affected

EXllllple:

If the PC contains %3584, the SP contains %2000, external data-memory location %2000
contains %18, and location %2001 contains %85, then the statement

RET
leaves the value %2002 in the SP and the PC contains %1885, the address of the next
instruction.

355

RL
Rotate Left
~L

dst

Instruction Foraat:

Cycles

-JI

L -_____o_p_c____

Operation:

IL______d_a_t____~

C <-- dst(7)
dst(O) <-- dat(7)
dst(n + 1) <-- daten) n

6
6

=0

IIPC

Address Mode

(Hex)

dst

90
91

R
IR

- 6

The contents of the destination operand are rotated left one- bit position.
The
initial value of bit 7 is roved to the bit 0 position and also replaces the carry
flag.

Flags:

c:

Set if the bit rotated from'the rost significant bit position was 1; i.e., bit 7
was 1

Z: Set if the result is zero; cleared otherwise.
Y:

S:
H:

D:

EX8lllple:

Set if arithmetic overflow occurred; that is, i f the sign of the destination
changed during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected

If the contents of the register named SHIFTER are %88 (10001000), the statement

RL SHIFTER
leaves the value %11 (00010001) in that register.
1 and the Z flag is cleared.

Note:

When used to specify a 4-bit working-register address, address rodes R or IR use the
format:
E

356

The C flag and V flags are set to

dst

RLC
Rotate Left Through Carry
RLC

dst

ope
Cycles

Address Mode

(Hex)

det

6
6

10
11

R
IR

Instruction For.at:

~_____O_P_C____~1 I~______d_s_t____~

Operation:

dst (0) <-- c
C <-- dst (7)
dst(n + 1) <-- dst(n) n

=0

- 6

The contents of the destination operand with the C flag are rotated left one bit
position. The initial value of bit 7 replaces the C flag; the initial value of the C
flag replaces bit O.

Flags:

Set if the bit rotated from the most significant bit position was 1; i.e., bit 7
was 1
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurs.' that is. if the sign of the destination
changed during rotation; cleared otherwise
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
D: Unaffected

EX8llple:

If the C flag is reset (to 0) and the register named SHIFTER contains
the statement

C:

~8F

(10001111).

RLC SHIFTER
sets the C flag and the V flag to 1 and SHIFTER contains

Note:

~1E

(00011110).

When used to specify a 4-bit working-register address. address modes R or IR use the
format:
E

dst

357

FIR .

Rotate Right
RR

dst

InstruCtion fom&t:

~~___O_p_C____--J1

Operation:

d_s_t____--J

LI_ _ _ _ _ _

C <-- dsi(O)
dst(7) <-- det(O)
det(n) <-- dst(n + 1) n

OPC
(Hex)

Addreaa Mode

Cycles

6
6

EO
E1

R

dat

IR

=0 - 6

The contents of the destination operand are rotat"d right one bit position.
initial value of bit 0 is moved to bit 7 and alao replaces the C flag.

flags:

The

C: Set if the bit rotated from the least significant. bit position was 1; i.e., bit 0
Willi

1

'

Z: Set i f the result is zero; cleared otherwise
V: Set i f arithmetic overflow occurred, that is, if the sign of the destination
, changed during rotation; cleared otherwise
s: Set if the result bit 7 is set; cleared otherwise
HI Unaffected
D: Unaffected

EXlllllple:

If the contents of working register 6 are %31 (00110001), the statement
RR R6

sets the C flag to 1 and leaves the value %98 (10011000) in working register 6.
Since bit 7 now equals 1, the S flag and the V flag are also set.
.

Note:

When used to epecify a 4-bit working-register address, address modes R or IR use the
format:

I

358

E

dst

RRC
Rotate Right Through Carry
RRC

dst

1natructillfl f OrllBt:

~

Cycles

~_____O_P_C____~1 I~

Operatillfl:

_____

d_s_t____~

dst(7) <-- C
C <-- dst(O)
dst(n)" <-- dst(n + 1)

6
6

OPC
(Hex)

Addreas Mode
dat

CO
C1

R

1R

n =0 - 6

The contents of the destination operand with the C flag are rotated right one bit
position. The initial value of bit 0 replaces the C flag; the initial value of the
C flag replaces bit 7.

flags:

C:

Z:
Y:

s:
H:

D:

[xlllllple:

Set if the bit ro'tated from the least significant bit position was 1; i.e., bit 0
was 1
Set if the result is zero; cleared otherwise
Set if arithmetic overflow occurred, that is, the sign of the destination changed
during rotation; cleared otherwise
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected

If the contents of the register named SHIFTER are %DD (11011101) and the Carry flag
is reset to 0, the statement
RRC SHIFTER
sets the C flag and the V flag and leaves the value %6E (01101110) in the register.

Note:

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

dst

359

SBC
Su~tract,With
SIIC

Carry

dst, src

Instruction for. .t:

Cycles
OPC
OPC
oPc

Operation:

II
II

II
dst

dst

src
src
dst

I
II
II

OPC
(Hex)

Address Mode
dst
are

6
6

32
33

r
r

dst

10
10

34
35

R
R

R
IR

arc

10
10

36

R
IR

1M
1M

37

r
' Ir

<-- dst - src - C

The aource operand, along with the setting of the C flag, is subtracted from the
destination ,operand and the result is stored in the destination. The contents of the
source are not affected. Subtraction ia performed by adding the two 'a complement of
the source operand to the destination operand.
In multiple precision arithmetic,
this instruction permits the carry ("borrow") from the subtraction of low-order
operands to be subtracted from the subtraction of high-order operands:

flags:

C:

Z:
\I:
S:

H:
0:

Example:

Cleared if there is a carry from the most significant bit of the result; set
otherwise, indicating a "borrow"
Set if the result is 0; cleared otherwise
Set if arithmetic overflow occurred, that is, if the operands were of opposite
sign and the sign of the result is the same as the sign of the source; reset
otherwise
Set if the result is negative; cleared otherwise
Cleared if there is a carry from the most significant bit of the low-order four
bits of the result; set otherwise indicating a "borrow."
Always set to 1

If the register named MINUEND contains 1016, the Carry flag is set to 1, working
register 10 contains 1020 (32 decimal), and register 32 contains 1005, ,the statement
SSC MINUEND, IR10
leaves the value %10 in reglster MINUEND.
D is set.

Note:

Z, V, Sand H flags are cleared and

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

360

The C,

src/dst

SCF
Set Carry Flag
SCf

Instruction Format:
Cycles
OPC

Operation:

6

C

<--

OPC
(Hex)
OF

1

The C flag is aet to 1, regardless of its previous value.

Flags:

C:

Set to 1
No other flags affected

361

SRA
Shift Right Arithmetic
SRA

dst

Instruction r orllllt:
Cycles

______

~______OP_C______~11.~

Operation:

d_s_t______~

dst(7) <-- dst(7)
C <-- dst(O)
dst(n) <-- dat(n +'1)

6
6

OPe
(Hex)

Address MDde

DO

R

01

IR

dst

n =0 - 6

An arithmetic shift right one bit position is performed on the destinstion operand.
Bit 0 replaces the C flag. Bit 7 (the Sign bit) is unchanged, and its value is al,so
shifted into bit position 6.
7

o

nags:

C: Set if the bit shifted from the le~st significsnt bit position was 1; i.e., bit 0
was 1
Z: Set if the result is zero; cleared otherwise
V: Always reset to 0
S: Set ·if the result is negative; cleared otherwise
H: Unaffected
0: Unaffected

Exa.ple:

If the register named SHIFTER contains

~BB

(10111000), the statement

SRA SHIFTER
resets the C flag to 0 and leaves the value %DC (11011100) in register SHIFTER.
S flag is set to ,1.

Note:

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

362

The

dat

SRP
Set
SRI'

R~gister

Pointer

src

Instruction for.at:

(Hax)

Addresa Mode
arc

6

31

1M

OPC

~______O_P_c______~1 ~I

Operation:

Cyclsa

RP

_______

<--

s_r_c______~

src

The specified value is loaded into bits 4-7 of the Register Pointer (RP) (control
register 253). , Bits 0-3 of the RP are always set to O. The source dah (with bits
0-3 forced to 0) is the starting address of a working-register group.
The
working-register group starting addresses are:
Hex
. %00
%10
%20
%30
%40

Decimal

~70

0
16
32
48
64
80
96
112

%FO

240

%50

%60

(control and peripheral registers)

Values in the range %80-EO are invalid.

flags:

No flags affected

EX9lllple:

Assume the RP currently addresses the control and peripheral register group and the
program has just entered an interrupt service routine. The statement
SRP #%70
saves the contents of the control and peripheral registers by setting the RP to %70
(01110000), or 112 decimal.
Any reference to working registers in the interrupt
routine will point to registers 112-127.

363

SUB
Subtract
SUB

dst,src

OPC

lnatrucUan fonat:

I
I
I

OPC
OPC
oPC

Operation:

II
II
II

dat

arc
arc
dat

I
II
II

Addret18 Mode
dst arc

Cycles

(lIex)

6
6

22
23

r
r

r
Ir

dat

10
10

24
25

R
R

R
IR

arc

10
10

26
27

R
IR

1M
1M

dst. <-- dst - arc
The aource operand ia aubtracted from the destination operand and the result is
atored in the destination. The content a of the source are not affected. Subtraction
ia performed by adding the two's complement of the aource operand to the destination
operand.

flags:

EXlIIIIPle:

C: Cleared i f there is a carry from the most significant bit of the result; set
otherwise, indicating a "borrow"
Z: Set if the result is zero; cleared otherwise
Y: Set i f erithlllf'tic overflow occurred, that is, if the operands were of opposite
aigns and the sign of the result is the same as the sign of the source operand;
cleared otherwise
S: Set if the result is negetive; cleared otherwise
H: Cleared if there is a carry frqm the most significant bit of the low-order four
bita of the result l. set otherwise indicating a "borrow."
D: Always set to 1

If

the register named MINUEND contains ~29, the statement
SUB MINUEND, #%11

will leave the value
D is set.

Note:

~18

in the register.

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

364

The C, Z, V, Sand H flags are cleared and

arc/dat

SWAP
Swap Nibbles
SWAP

dst

Instruction fomat:

Cycles

~_____O_P_C______~II~

Operation:

_______

dst(O - 3)

ds_t______~

<-->

B
B

OPt

Addreaa Mode

(Hex)

d.t

fO
f1

R

IR

dst(4 - 7)

The contents of the lower four bits and upper four bits of the destination opersnd
are swapped.

flags:

C:

Undefined

Z: Set if the result is zero; cleared otherwise
V: Undefined
S:

Set if the result bit 7 is set; cleared otherwise

H: Unaffected
D:

EXlIIIIPle :

Unaffected

Suppose the register named BCD_nperands contains %B3 (10110011).

The statement

SWAP BCD_Operands
will leave the value %3B (00111011) in the register.

Note:

The Z and S flags are cleared.

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

dst

365

TeM
Test Complement Under Mask
TCM

dst,src

Instruction For.st.
ope
ope
ope

Operation.

Cycles

II
II
II

det

src
erc
dst

I
II
II

OPt

(Hex)

Address Mode
dat arc

6
6

62

63

r
r

r
Ir

dst

10
10

64
65

R

R

R

IR

src

10
10

66
67

R
IR

1M
1M

(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical "1"
value. The bits to be tested are specified by setting a 1~ bit in the corresponding
position of the source operand (mask). The TeM statement complements the destination
operand, which is then ANDed with the source mask. The Zero (Z) flag can then be
checked to determine the result. When the TCM operation is complete, the destination
location still contains its original value.

Flags:

C:
Z:
V:
S:
H:
0:

Unaffected
Set if the result is zero; cleared otherwise
Always reset to 0
Set i f the result~ bit 7 is set; cleared otherwise
Unaffected
Unaffected

EXlIIIIPle :

If the register named TESTER contains %F6 (11110110) and the register named MASK
contains %06 (00000110), that is, bits 1 and 2 arB being tested for a 1 value, the
statement
TeM TESTER, MASK
complements TESTER (to 00001001) and then do a logical AND with register MASK,
resulting in %00. A subsequent test of the Z flag,
JP Z,plabel
causes a transfer of program control.
contains %F6.

Note:

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

366

At the end of this sequence, TESTER still

src/dst

TM
Test Under Mask
TM

dst,src

Instruction f orllllt:

OPe

Cycles

I
I
I

ope
ope
ope

Operation:

II
II
II

dst

src
arc
dst

II
II

(Hex)

Address Mode
det arc

6
6

72
73

r
r

r
Ir

dst

10
10

74
75

R
R

R
IR

src

10
10

76

R
IR

1M
1M

77

dst AND src
This instruction tests selected bits in the destination operand for a logical "0"
value. The bits to be tested are specified by setting a 1 bit in the corresponding
position of the source operand (mask), which is ANOed with the destination operand.
The Z flag can be checked to determine the result.
When the TM operation is
complete, the destination location still contains its original value.

flags:

C: Unaffected
Z: Set if the result is zero; cleared otherwise
V: Always reset to 0
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
D: Unaffected

EXBIIPle:

If the register named TESTER contains %F6 (11110110) and the register named MASK
contains %06 (00000110), that is, bits 1 snd 2 are being tested for a 0 value, the
statement
TM TESTER, MASK
results. in the value %06 (00000110).

A subsequent test for nonzero

JP NZ, plabel
causes a transfer of program control. At the end of this sequence, TESTER still
contains %F6. The Z and S flags are cleared.

Note:

When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E

src/dst

367

XOR
Logical Exclusive OR
XOR

dst,src

OPC

Instruction foraat:

Cycles
OPC

II

OPC

II

src

II

dst

OPC

Operation:

dst

dst
src

Address Mode
dat arc

6
6

B2
B3

r
r

r
Ir

10
10

B4

R
R

R
lR

10
10

B6

R
lR

1M
1M

src

II
II

(Hex)

B5
B7

dst <-- dst XOR src
The source operand is logically EXCLUSIVE ORed with the destination operand and the
result stored in the destination. Tbe EXCLUSIVE OR operation results in a one bit
being stored whenever the, corresponding bits in the operands a.re different;
otherwise, a 0 bit is stored.

flags:

EXlllllple:

C:

Unaffected

V:
5:
H:
0:

Always reset to 0
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected

Z: Set if the result is zero; cleared otherwise

If the source operand is the immediate value %78 (011111011) and the register named
TARGET contains %C3 (11000011), the statement
OR TARGET, il%7B
leaves the value %88 (10111000) in the register.

Note:

When used to speci fy a 4-bit working-register address, address modes R or IR use the
format:
E

368

src/dst

Chapter 6
Exteraal Interface
(Za6GI, Za611)
6.1

a high-impedance state along with Ports 0 and 1,
Data Strobe (OS), and R/W.

INTROOUCTION

The ROM versions of the Z8 microcomputer have 40
external pins, of which 32 are programmable I/O
pins. The remaining 8 pins are used for power and
control. Up to 16 I/O pins can be configured as
an external memory interface. This interface
function is the subject of this chapter. The I/O
mode of these pins is described in Chapter 9.

Ds~

Data Strobe (output, active 'Low, 3-atate,
Data Strobe provides the timing for data
movement to or from Port 1 for each external
memory transfer. During a Write cycle, data out
is valid at the leading edge of OS. During a Read
cycle, data in must be valid prior to the trailing
edge of 55. 55 can be placed in a high-impedance
state along with Ports 0 and 1, AS, and R/W.
pin 8).

6.2 PIN DESCRIPTIONS
Address Strobe (output, active Low, ~tate,
pin 9). Address Strobe is pulsed Low once at the
beginning of each machine cycle. The rising edge
of AS indicates that addresses, Read/Write (R/W) ,
and Data Memory (OM) signals, are valid when output for external program or data memory transfers. Under program control, AS can be placed in

AS.

PORTO
(NIBBLE
PROGRAMMABLE)
I/O OR As-A,.

RESET

+5V

RNi

GND

OS
AS

XTAL2

PO.

P20

PO,

P2,

(output, l-state, pin 7) •
R/W. Read/Write.
Read/Write determines the direction of data transfer for e~ternal memory transactions. R/W is Low
when writing to external program or data memory,
'and High for all other transactions. R/W can be
placed in a high-impedance state along with Ports
o and 1, AS, and 55.

+5V

XTAL1

PO,

P2,

PO,

P2,

PO.

P2.

PORT 2
(BIT PRO·
GRAMMABLE)
1/0

PO. Z8601111 P2.
MCU
P20
PO,

PORT 1
(BYTE
PROGRAMMABLE)
I/O OR ADo-AD?

P07

P27

P1.

P30

P1,

P3,

Pt,

P3,

P1,

P3,

P1.

P3.

P1.

P3.

P1.

P30

P1 7

P37

PORT 3
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL 1/0
AND CONTROL

P3.

XTAL2

2

P3,

XTAL1

3

P27

P37

4

P2.

P30

5

!fErn

6

pa-

R/W

7

P2,

DS

8

P2,

AS

9

P2,

P3.

10 Z8601l11

P2.

P2.

MCU

GND

11

P3,

12

PO.
PO,

13

P1 7

14

P1,

PO,

15

P1.

PO,

16

P3,
P3.

P1.

PO.

P1,

PO.

18

23

P1,

PO.

19

22

P1,

21

P1.

P07

Figure 6-2.

Z8601/11 Pin

Assi~s

369

External Interface (lS601,ZS611)
PIlo-P07 , P1 0 -P1 7 , P2o-P27, PJO-P)7.
I/O port
lines
(inputs/outputs,
TTL-compatible;
pins
12-40). These 32 I/O lines are divided into. four
S-bit I/O ports that can be configured under pro\lram control for I/O or external memory interface.
Individual lines ofa 'port are denoted by
the second digit of the port number. For example,
P3 0 refers to bit 0 of Port 3,. Ports 0 and 1 can
be placed in a high-impedance state along with AS,
f55, and R/W.
RESET. Reset (inpUt, active Low, pin 6). RESET
initializes the lB.
When RESET is deactivated,
program execution begins from internal program
location roC. If held low, RESET acts as a register file protect during power-down and power-up
sequences. RESET also enables the ZS Test mode.
XTAL1, XTAL2.
Crystal 1, Crystal 2 (oscillator
input and output, pins 3 and 2). These pins connect a parallel-resonant crystal (12 MHz maximum)
or 'an external source (12 MHz maximum) to the
on-board clock oscillator and buffer.

6.3 CONFIGURING FOR EXTERNAL MEMORY
Sefore interfacing with external memory, the user
must configure Ports 0 and 1 appropriately. The

minimum bus configuration uses Port 1 as a multiplexed Address/Data port (ADO-AD7)' allowing
access to 256 bytes of external memory. In this
configuration, the eight lower order address bits
(AO-A7) are multiplexed with the data (00-07).
Port 0 can be programmed to provide four additional address lines (AS-A11)' which increases the
externally addressable program memory to 4K
bytes. Port 0 can also be programmed to provide
eight additional address lines (AS-A15)' which
increases the externally addressable memory to 62K
bytes for the lS601 or 60K bytes for the ZB611.
Refer to Chapter 3, Figures 3-5 and 3-6, for
external memory maps.
Ports 0 and 1 are configured for external memory
operation by writing the appropriate bits in the
Port 0-1 Mode register (Figure 6-3).
For example, Port 1 can be defined as a multiplexed Address/Data port (ADO-AD7) by setting 04
to 1 and 03 to O. The lower nibble of Port 0 can
be defined as address lines AS-A"., by setting 01
to 1. Similarly, setting 07 to 1 defines the upper
nibble of Port 0 as address lines A12 -A15. Whenever Port 0 is configured to output address lines
A12-A15' AS-A11 must also be selected as address
lines.

R248P01M
Port 0-1 Mode Register
(% F8; Write Only)

PO.-POr MODE
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X

I
-.J

-r
L

POo-PO, MODE
00 = OUTPUT
01 = INPUT
1X = A"-A,,

P1 o-P1, MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD,
11 = HIGH·IMPEDANCE ADo-AD,.
AS. OS. RiW. As-A". A,2-A,5

Figure 6-3.

370

Ports 0 and 1 External Ma.ory Operation

External Interface (Z8601,Z8611)
Once Port 1 is configured as an Address/Data port,
it can no longer be used as a register. Attempting to read Port 1 returns FF; writing has no
effect. Similarly, if Port 0 is configured for
address lines A8-A 15 , it can no longer be used as
a register. However, if only the lower nibble is
defined as address lines A8-A11 , the upper nibble
is still addressable as an I/O register. Reading
Port 0 with ,only t'he lower nibble defined as
address outputs returns XF, where X equals the
data in bits D4-D 7 •
Writing to Port 0 transfers
data to the I/O,nibble only.
An instruction to change the modes of Ports 0 or 1
should not be immediately followed by an instruction that performs a stack operation, because this
may cause indeterminate program flow.
In addition, after setting the modes of Ports 0 and 1 for
external memory, the next three bytes must be
fetched from internal program,memory.

6.5 DATA MEMORY
The two external memory spaces, data and program,
can be addressed as a single memory space or as
two separate spaces of equal size; i.e., 62K bytes
each for the ZB601 and 60K bytes each for the
Z8611.
If the memory spaces are separated,
program memory and 'data memory are logically
selected by the Data Memory select output (OM).
DM is available on Port 3, line 4 (P3 4 ) by setting
bits D4 and D3 in the Port 3 Mode register to 10
or 01 (Figure 6-5). OM is aHive Low during the
execution of the LDE, LDEI instructions. OM is
also active during the execution of CALL, POP,
PUSH, RET and IRET instructions if the stack
resides in external memory.

R247 P3M
Port 3 Mode Register
(% F7; Write Only)

6.. EXTERNAl STACKS
Z8 architecture supports stack operations in
either the register file or data memory. ' A
stack's location is determined by bit D2 in the
Port 0-1 Mode register. For example, if D2 is set
to 1, the stack is in internal data memory
(F igure 6-4).

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

L

STACK SELECTION
o = EXTERNAL
1 = INTERNAL

Figure 6-..

Ports 0 and 1 Stack Selection

The instruction used to change the stack selection
bit should not be immediately followed by the
instructions RET or IRET, because this will cause
indeterminate program flow.

o0

P33 = INPUT
P33 = INPUT
1 0 P33 = INPUT
1 1 P33 = OAV1/ROY1

o1

Figure 6-5.

P3.
P3.
P3.
P3.

= OUTPUT

= ijg
= OM
= ROY1/0AV1

Data MeIIIory Operation

6.6 BUS OPERATION
The timing for typical data transfers between the
Z8 and external memory is illustrated in Figure
6-6. Machine cycles can vary from six to twelve
clock periods depending on the operation being
The notations used to describe the
performed.
basic timing periods of the Z8 are: machine cycles
(Mn), timing states (Tn), and clock periods. All
timing references are made with respect to the
output signals AS and DS. The clock is shown for
clarity only and does not have a specific timing
,relationship with other signals.

371

External Interface ( Z8601 ,Z8611')
MACHINE CYCLE

r

T1

T2

I

T3

'I

CLOCK

PO

X

P1

X

x=

A...A15

Ao~A7

B

)

C

'---I

AS

\

/

,C

7

RlW

X

L

I·

Figure 6-6&.

6.6.1

'-'I

READ CYCLE

External IllIJtruction Fetch, or "-n:y Read Cycle

AcIdr_ Strobe (AS)

6.6.3 External MB.Dry Operations

All transactions start with AS driven Low and then
raised High by the Z8.
The rising edge of AS
indicates that R/W, iiM, and the addresses output
fr'om PortS 0 and 1 are ~alid.
The addresses
output via Port 1 remain valid only during MnT1
and typically need to be latched using AS, whereas
Port 0 address outputs remain stable throughout
the machine ccycle •

Whenever the Z8 is configured for external memory
operation, the addresses of all internal program'
memory references appear on the external bus.
This should havecno effect on the external system
since the bus control lines, 55 and R/W, remain in
their inactive c High state.
OS and R/W become
active only during external memory references.
CAUTION

c

6.6.2 Data StrObe
The Z8 uses 55 to time the actual data transfer.
For Write operations (R/W = Low), a Low on OS
'indicates that valid data is on the Port 1 AO O-A07
lines.
For Read operations, (R/W = High), the
Address/Oata bus is placed in a high-impedance
state before driving OS low so thatcthe addressed
device can put its data on the bus. The Z8 samples this data prior to raising OS High.
C

372

00 not use LOC, LOCI, LOE or LOEI to
write to, internal program memory. The
execution of these instructions causes
the Z8 to assume that an externalcwrite
operation is being performed and tl:lis
will sctivate control signals 55 and
R/W.

External Interface (ZB601,ZB611)
MACHINE CYCLE

I'

T2

Tl

T3

CLOCK

PO

P1

AS

X
X

X
X

As-Au

Ao-A7

X

Do-D7 OUT

'---

\..J
\

OS

R/W

~

OM

X

r=
X

I·

figure 6-6b.

/

·1

WRITE CYCLE

External Meaory Write Cycle

6.7 SHARED IlUS
Port 1, along with AS, 55, R/W, and Port 0 nibbles
configured as address lines, can be placed in a
high-impedance state, allowing the ZB601 or the
ZB611 to share common resources with other bus
masters. This shared bus mode is under software
control and is programmed by setting Port 0-1 Mode
register bits D4 and D3 both to 1 (Figure 6-7).
Data transfers can be controlled by assigning, 'for'
example, P3 3 as a Bus Acknowledge input and P34 as
a Bus Request output.
Bus Request/Acknowledge
control sequences must be software driven.

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

Pl o-Pl, MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD,
11 = HIGH·IMPEDANCE ADo-AD7.
AS. OS. R/W. A8-All. A12-A15

figure 6-7.

Shared Bus Operatioo

373

External Interface (ZBIl01,ZB611).
6.8

EXTENDED

BUs

TIMING

R248 P01M
Port 0-1 Mode Register

The ZB601 and Z8611 can accommodate slow memory
access times by automatically inserting an additional state time (Tx) into the bus cycle.
This
stretches the liS timing by two clock periods,
though· internal memory accesS time is not
affected. Timing is extended by setting ~it 0 5 in
the Port 0-1 Mode register to 1 (F"igure 6-B).
F"igures 6-9a and 6-9b illustrate extended memory
Read and Write cycles.

(% F8; Write Only)

EXTERNAL MEMORY TIMINGJ
NORMAL
0
"EXTENDED = 1

=

·ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682

F"igure 6-8.

Ext~nded

8us TiMing

MACHINE CYCLE

I'

T2

T1

Tx

'1

T3

CLOCK

PO

P1

=x
=x

x=

Aa-A 15

)

Ao-A7

( 00-0 7 IN

>---C

AS~

OM

:J

=x
I,

figure 6-9a.

374

I

\

OS

R/W

'C
READ CYCLE

Extended External Instruction fetch, or MeIIory Read Cycle

x=
'I

External Inter face (ZB601 ,ZI!61J)

6.9 INSTRUCTION TIMING
The high throughput of the ZB is, due, in part, to
the uae of instruction, pipelining, in which the
instruction fetch and execution cycles are overlapped.
During the execution of an instruction,
the opcode of the next inatruction is fetched.
This is illustrated in Figure 6-10.
Figures 6-11 and 6-12 show typical instruction
cycle timing for instructions fetched' from external memory. (It should be noted that all instruc-

tion fetch cycles have the same machine timing
regardless of whether memory, is internal or' external.) For those instructions that raquire execution time longer then that of the overlapped
fetch, or instructions that reference program or
data memory as part of their execution, the pipe
must be flushed. In order to calculate the execution time of a program, the internal clock periods
shown in the cycles column of the instruction formats in Section 5.4 should be added together. The
cycles are equal to 'one-half the crystal or input
clock rate.

~------------------~T--2 MACHINECYCLE-T-X--------------T3------'~1

I'

TI

CLOCK

PO

P1

=x
=x

Ao-A7

X

AS~

\'------~

IlS

R/W

OM

\

=x. I'

I----------,.---WRITE CYCLE ------------1

Figure 6-91».

Extended External "-ary Write Cycle

375

'"

~

x
.....

,.,'"
.,....:::l
....

:::l

.....

M,

M2

M,

M2

M,

M2

'I

',.,....."
~
'"
~
'"~

INTERNAL
CLOCK

N

CD

~

INSTRUCTION
N

INSTRUCTION
FETCH 1

OPERAND
FETCH(ES)

INSTRUCTION
FETCH 2

ALU STORE

EXECUTION CYCLE

INSTRUCTION

INSTRUCTION
FETCH 1

N+1

OPERAND
FETCH(ES)

INSTRUCTION
FETCH 2

ALU STORE

EXECUTION CYCLE

INSTRUCTION

INSTRUCTION
FETCH 1

N+2

I..
I_

EFFECTIVE
EXECUTION TIME

-I"

HIDDEN DELAY
U,NTIL COMPLETION

INSTRUCTION COMPLETION TIME

figure 6-10.

Instruction Pipelining

-I
-

I

INSTRUCTION
FETCH 2

M,

r-

T,

M2

L _Ts __ J

T2

T,

M,

T2

Ts

T,

T2

Ts

CLOCK

PO

_ _ _. - J

X

P1

,,<>-A7

~

)

,,<>A7

>

~

~

~

'-./,---------..'-1

AS

I

OS

\

I

\

\....J
I

I

RIW

.j-

FETCH INSTRUCTION

Figure 6-11.

M,
T2

T,

u

-I

FETCH 1ST BYTE OF NEXT INSTRUCTION

Instrllction Cycle Tboing (One Byte Instructioos)

, -

M2
M,ORM s
T.-T,-T-r;-r==r;-C-r;-r--r,-

I

T.

ul

CLOCK

PO
P1

AS

=::x::
X ,,<>A7

=::x
~

)

X

A.-A,.
,,<>-A7

).

~

A.-A,.
,,<>-A7

)

~

...'"..,x
<>-...- ........ ::~-............-

I

XTAL2
CST~AY =
15 pF MAX

' - - - - - - _ XTAL1

I
Figure 11-5.

CSYRAY =
15 pF MAX

Extemal Clock Interface

387

Chapter 9
1/0 'oris
9.1

INTRODucTION

9.1.2

The Z8 has 32 lines dedicated to input and output.
These lines are grouped into four 8-bit
ports and ar:e configurable as input, output, or
address/data.
Undel,' software control, the ports
can be programmed to provide address/data, timing,
status, serial, and parallel input/output with or
without handshake.
All ports have active pull-ups and pull-downs
compatible with TTL loads.
In addition, the
pull-ups of Port 2 can, be' turned off for
open-drain op~ration.

9.1.1

Mode Registers

Each port has an associated mode register which
determines the port's functions and allows dynamic
change in port functions during program execution.
Ports and mode registers are maPped into
the register file as shown in Figure 9-1.
Because of their close association, ports and mode
registers are treated like any other g,eneral-purpose register. There are no special instructions
for port manipulation; any instruction that
addresses a register can address the ports. Data
can be directly accessed in the port register,
with no extra moves.
DEC

248

HEX IDENTIFIERS

PORTS 0-1 MODE

Fa

247

PORT 3 MODE

F7

P3M

248

PORT 2 MODE

Fe

P2M

3

PORT 3

03

P3

2

PORT 2

02

P2

1

PORT 1

01

P1

o

PORTO

00

PO

04

4

Figure 9-1.

388

P01M

I/O Port and Port Mode Registers

Input and Output Registers

Each bit of Ports 0, 1, and 2 has an input register, an output register, associated buffer, and
control logic. Since there are separate input and
output registers associated with 'each port, writing to bits defined aa inputs stores the data in
the output, register. This data cannot be read as
long as the bits are defined as inputs. However,
i f the bits are reconfigured as output, the data
stored in the output register is reflected on the
output pins and can then be read. This mechanism
allows the user to initialize the outputs prior to
driving their loads.
,Since port inputs are asynchronous to the Z8' s
internal clock, a Read operation could occur
during an input transition.,
In this case, the
logic level might be' uncertain--somewhere between
To eliminate this meta-stable,
a logic 1 and O.
condition, the Z8 latches the input data two clock
periods prior to the execution of the current
instruction.
The input register uses these two
clock periods to stabilize to a I egitimate logic
level before the instruction reads the data.

9.2 ,PORT 0
This section deals only with the I/O operation of
Port O.
Refer to Sections 6.2 and 7.2 for a
description of the port's external memory interface operation.
Port 0 is a general I/O port. Bits within each
nibb Ie can be independently programmed as inputs,
outputs or address lines.
Figure 9-2 shows a
block diagram of Port O.
This diagram also
applies to Ports ,. and 2.

.....

'o
."

o

INPUT REGISTER

1..1

1..1

A
8

~~~~-r---

E

8

""

I

WRITE
PORT

RDY/DAY

t..

t..

8

8

--y

r
OUTPUT ENABLE_

OUTPUT REGISTER

Figure 9-2.

<0

DAy/RDY

HANDSHAKE
LOGIC

8

~

PORT 110
LINES

TIMING

~

INTERNAL BUS

,...

:>r

~I--INTERNAL

HANDSHAKE SELECTED

8

~

.,

8

~

l\f

"....
'"

INPUT BUFFER

OUTPUT BUFFER

Ports 0, 1, a1d 2 Block Diagr. .

I/o Ports
9.2.1

Read/Write Operations

In the nibble I/O mode, Port 0 is accessed as general-purpose register PO (%00). The port is written by specifying PO as an instruction's destination register. Writing the port causes data to be
stored in the port's output register.
The port is read by specifying PO as the source
register of an instruction. When an Qutput nibble
is read, data on the external pins is retu~ned.
Under normal loading conditions this is equivalent
to reading the output register. Reading a nibble
defined as input also returns data on the external
pins. However, input bits under handshake control
return data latched into the input register via
the input strobe.

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

PO.-P07 MODE
OUTPUT = 00
INPUT = 01
A'2-A'5
1X

----r.-J

~
MODE
L PO.-P0
00 = OUTPUT
3

01
1X

'*

Figure 9-3.

= INPUT
= As-A"

Port 0 I/O Operation

R247 P3MPort 3 Mode Register
(% F7; Write Only)

The Port 0-1 Mode register bits 0100 and 0706 are
used to configure Port 0 nibbles (Figure 9-3).
The lower nibble (PO O-P0 3) can be defined as
inputs by setting bits 01 to 0 and 00 to 1, or as
outputs by setting both 01 and 00 to O. likewise,
the upper nibble (P04-P07) can be defined as
inputs by setting bits 07 to 0 and 06 to 1, or as
outputs by setting both 06 and 07 to O.

9.2.2

Handshake Operation

L, '"."'"'
1 P32

Figure 9-4.

When used as an I/O port, Port 0 can be placed
under handshake control by programming the Port 3
Mode register bit 02 to 1 (Figure 9-4). In this
configuration, handshake control lines are OAV O
(P3Z) and ROYO (P3 s ) when Port 0 is an input port,
or ROYO (P3 2) and OAVO (P3 S) when Port 0 is an
output port.
Handshake direction is determined by the configuration (input or output) assigned 'to Port 0' s
upper nibble, P04-P07. The lower nibble must have
the same I/O configuration as the upper nibble to
be under handshake control.
Figure 9-5 illustrates the Port 0 upper and lower nibbles, and the
associated handshake lines of Port 3.
Handshake operation is discussed in detail in Section 9.6.

390

=DAVO/RDVO

P3s
P3s

= OUTPUT
= RDVO/DAVO

Port 0 Handshake Operation

P04- P07 } PORT 0
'
(I/O OR AS-A15)
} POO-P03

_

} HANDSHAKE CONTROLS
DAVo AND RDVo
(P32 AND P3s)

Figure 9-5.

Port 0

I/O Ports
9.3

PORT

9.3.2

This section deals only with the I/O operation of
Port 1 and does not apply to the ZB6B1/B2 ROMless
devices.
Refer to Sections 6.2 and 7.2 for a
description of the port's external memory interface operation.
Port 1 is a general-purpose I/O port that can be
programmed as a byte I/O port with or without
handshake, or as an address/data port for interfacing with external memory. Refer to Figure 9-2
for a block diagram of Port 1.

9.3.1

Handshake Operations

When used as an I/O port, Port 1 can be placed
under handshake control by programming the Port J
Mode register bits 04 and 03 both to 1 (Figure
9-7).
In this configuration, handshake control
lines are DAY1 (PJ 3 ) and ROY 1 (P3 4 ) when Port 1 is
an input port, or ROY1 (PJ 3 ) and DAV 1 (P3 4 ) when
Port 1 is an output port.

R247 P3M
Port 3 Mode Register
(% F7; Write Only)

Read/Write Operations

In byte input or byte output mode, the port is
accessed as general-purpose regIster P1 (%01).
The port is written by specifying P1 as an
instruction's destination register.
Writing the
port causes data to be stored in the port's output
register.
The port is read by specifying P1 as the source
register of an instruction.
When an output is
read, data on the external pins is returned.
Under normal loading conditions, this is equivalent to reading the output register. When Port 1
is defined as an input, reading also returns data
on the external pins. However, inputs under handshake control return data latched into the input
register via the input strobe.
Using the Port 0-1 Mode register, Port 1 is configured as an output port by setting bits D4 and
D3 to Os, or as an input port by setting 04 to 0
and OJ to 1 (Figure 9-6).

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

o 0

o1
1 0
1 1

Figure 9-7.

P33 = INPUT
P33
INPUT
P33
INPUT
P33 = DAV1/RDY1

=
=

P34 = OUTPUT
P34
OM
P34 = OM
P34
RDY1IDAV1

=
=

Port 1 Handshake Operation

Handshake direction is determined by the configuration'(input or output) assigned to Port 1. For
example, if Port 1 is an output port then handshake is defined as output.
Figure 9-B illu3trates the Port 1 lines and the associated handshake lines of Port 3.
Handshake operation is discussed in detail in Section 9.6.

PORT 1
(110 OR ADo-AD7) P1o-P17

HANDSHAKE CONTROLS
} DAV1 AND RDY1
(PSa AN 0 P3.l

P1 o-P1 7 MODE
00 = BYTE OUTPUT
01 = BYTE IN PUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7,
AS, OS, RtW, As-A11o A12-A15

Figure 9-6.

Figure 9-8.

Port 1

Port 1 I/O Operation

391

I/O Ports
9.4 PORT 2

,9.4.2 Handshake Operation

Port 2 is a general-purpose port.
Each of its
lines can be independently programmed as input or
output via the Port 2 Mode register (Figure 9-9).
A.bit set to a 1 in P2M configures the corresponding bit in Port 2 as an iMput, while a bit set to
o determines an output line.

Port 2 can be placed under handshake control by
programming the Port 3 Mode register (figure
9-10).
In this configuration, Port 3 lines P31
and P3 6 are used as the handshake control lines
DAV2 and RDY2 for input handshake, or RDY2 and
OAV2 for output handshake.

R247 P3M
Port 3 Mode Register
(% F7; Write Only)

R246 P2M
Port 2 Mode Register
(%F6; Write Only)

P20-P27 MODE
OUTPUT

L-_ _ _ _ 0

1 INPUT

figure 9-9.

9.4.1

Port 2 I/O Operation

Read/Write Operations

o
1

Port 2 is accessed as general-purpose register P2
(%02). The port is written by specifying P2 as' an
instruction's destination register.
Writing the
port causes data to be stored in the port's output
register, and reflected externally on any bit configured as an output.
The port is read by specifying P2 as the source
register ~f an instruction. When an output bit is
read, data on the external pin is returned. Under
normal loading conditions, this is equivalent to
reading the output register. However, if a bit of
Port 2 is defined as an open-drain output, the
data returned is the value forced on the output
pin by the external system. This may not· be the
same as the data in the output register.

P31
P31

figure 9-10.

=

INPUT (TIN)

= DAV2/RDY2

P36
P36

=

OUTPUT (TOUT)

= RDY2/DAV2

Port) Handshake Operation

Handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port
2. Only those bits with the same configuration as
P27 will be under handshake control. figure 9-11
illustrates Port 2's bit lines and the associated
handshake lines of Port 3.

P20

PORT 2(1/0)

Reading input bits of Port 2 also returns data on
the external pins. However, inputs under handshake control return data latched into the input
register via the input strobe.

P27
HANDSHAKE CONTROLS
} iiAV2 AN D RDY2
(1'31 AND P30l

figure 9-11.

392

Port 2

9.5 PORT 1

Port 2 can also by configured to provide opendrain outputs by programming Port 3 Mode register
(P3M) bit DO to 0 (Figure 9-12).

Port 3 differs structurally from the other three
ports.
Port 3 lines are fixed as, four input
(P30-P33) and four output (P34-P37) and do not
have an input and output register for each bit.
Instead, all the input lines have one input" register, and output lines have an output register.
Under software control, the lines can be configured as input or output, special control lines
for handshake, or as I/O lines for the on-board
serial and timer facilities.
figure 9-13' is a
block diagram of Port 3.

Regardless of the bit input/output configuration,
Port 2 is always written and read as a byte-wide
porh

R247 P3M
Port 3 Mode Register
(% F7; Write Only)

L
Figure 9-12.

Port 3 is accessed aa general-purpose register PJ
(%03). The port is written by specifying P3 as sn
instruction's destination register.
However,

Port 2 Open-DrBin Outputs

INPUT
REGISTER

A

9.5.1 . Readl"rite Operations

0 PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE

INPUT
BUFFER

~~~-

A

...

I

4

4

...

~

...

TO INTERRUPT TIMER, HANDSHAKE LOGIC
OR SERIAL 110

~~~-

A

...

WRITE
PORT

4

--r

OUTPUT
REGISTER

A
OUTPUT
DATA
RETURN
BUFFER

4

PORT
INPUT
LINES
(P3(J-P331

A

K...

4

'rOUTPUT
BUFFER

,

~

~

)

4

...

4

...

I

...

PORT
OUTPUT
LINES
(P34-P37)

FROM TIMER, HANDSHAKE LOGIC
OR SERIAL 1/0

INTERNAL

BUS
Figure 9-11.

Port 1 Block Diagr_

393

I/O Ports
Port 3 outputs,cannot be written if they ~re used
for special functions., When writing to Port 3,
data is stored in the output register.

Table 9.1

Port 3 line functions

function

line

Signal

The port is read by specifying P3 as the source
register of an instruction.
When reading from
Port 3, the data ret~rned is both the data on the
input pins and in the output register.

Input
Output

P30-P33
P34-P37

Input
Output

Handshake
tnputs

9.5.2 Special functions

Handshake
Outputs

P3 1
P32
P33
P34
P35
P36

OAV 2/ RDY2
DAVO/RDYO
DAV 1/ RDY 1
RDY 1/15iiV 1
RDYO/DAVO
RDY2/OJW2

Interrupt
Requests

P30
P31
P32
P33

IRQ3
IRQ2
IRQO
IRQ1

Serial Input
Output

P3 0
P37

51
50

Counter/Timer

P31
P36

Tin
Tout

Status

P34

DM

Special functions for Port 3 are defined by programming the Port 3 Mode register. By writing Os
in 02-D6' lines P30-P37 ar configured in input/
output pairs (Figure 9-14).
Table 9-1 shows
available functions for Port 3.
The special
functions indicated in the table are discussed in
detail in their corresponding sections in this
manual.
Port 3 input lines P30-P33 always function as
interrupt requests regardless of the configuration
specified in the Port 3 Mode register. Unwanted
interrupts must be masked off as described in
Chapter 10.

R247 P3M
Port 3 Mode Register
(% F7; Write Only)
I De I Dsl D41 D31 D.I

L"~-,",",

1 P32 = DAiTO/RDYO

o0

P33 = INPUT
L....._ _ _ _ ~ ~} P3a
INPUT

=

P3... OUTPUT
P35
RDYO/DAiTO

=

P3. ;= OUTPUT

P34 = OM
1 1 P33 = DAV1/RDY1 P34
RDY1/liiW1
L _ _ _ _ _ _--,-_O P31 - INPUT (TIN) PSa .. OUTP~UT)
2
1 P31 = DAV2tRDY2 PSa .. RDY2t

=

,°

L-_ _ _ _ _ _ _ _

figure 9-14.

394

P30 ..
= SERIAL
INP,uT IN
1 P30

P37 = OUTPUT
P37
SERIAL OUT

=

Port 3 I/O Operation

9.6 PORr IfAN>SHAKE
When Ports 0, 1, or 2 sre ,configured for handshske 'operation, a pair of lines from Port. 3 is
used for handshake controls for each port.
The
handshake controls a're interlocked to properly
time· asynchronous data transfers between the ZB
and its peripheral. One control line (DAV n ) functions as a strobe from the sander to indicate to
the receiver that data ia available. The second
control line (ROY n) acknowledges receipt of' the
sender's data, ,and indicates when the receiver is
ready to accept a~other data transfer.
In the ,input mode, data is latched into the port's
input register by the first DAV signal, and is
protected from being overwritten if additional
pulses occur on the DAV line. This overwrite protection is maintained until the port data is
read.
In the output mode, data written to the
port is not protected and can be overwritten by
the Z8 during the handshake sequence.
To avoid
losing data, the software must not overwrite the
port until the corresponding interrupt request
indicates that the external device has latched the
data.

Following is the recommended setup sequence when
configuring a port for handshake operation for
the first time after a reset:
•

Load P01M or P2M to' configure the port for
input/output.

•

Load P3 to set the Output Handshake bit to a
logic 1.

•

Load PJM to select the Handshake mode for the
port.

Once a data transfer begins, the configuration of
the handshake lines should not be changed until
handshake is completed.
Figures 9-15 and 9-16 show detailed operation
for the handshake sequence.
In applications requiring a strobed signal instead
of the interlocked handshake, the ZB can satisfy
this requirement as follows:
•

In the Strobed Input mode, data can be latched
in the port input register using the DAV
input.
The data transfer rate must sllow
enough time for the software to read the port
before strobing in the next character. The ROY
output is ignored.

•

In the Strobed Output mode, the ROY input
should be tied to the OAV output.

The software can always read Port 3 output and
input handshake lines, but cannot write to the
output handshake lines.

DAY

2

3

4

5

(INPUT TO Z8)

RDY
(OUTPUT FROM Z8)

---+--

DATA ON PORT
(INPUT TO Z8)

Sla181. Port 3 Ready output is High. indicating that the Z8 is ready to accept data,
Slale 2. The 1/0 device puts data on the port and then activates the rJlW Input. This causes
the data to be latched into the port input register and generates an interrupt reo
quest.
Slale 3. The Z8 forces the Ready (ROY) output Low, signaling to the 1/0 device that the
data has been latched,
Slale 4. The 1/0 device returns the OAV line High In response to ROY going Low,
Stale 5. The Z8 software must resPQnd to the interrupt request anQ read the contents of
the port in order for the handshake sequence to be completSd, The ROY line goes
High If and only If the port has not been read and rJlW Is High, This returns the in·
terface to Its initial state,

r!gure 9-15.

Z8 Il1JUt Ha1dshaIce

395

I/O Ports
3

2

4

5

ROY
(INPUT TO Z8)

DAV
(OUTPUT FROM Z8)

DATA ON PORT
(OUTPUT FROM Z8)

VALID DATA

~o accept data.
State 2. The Z8 writes to the port register to initiate a data transfer. Writing the port outputs
new data and forces rJl&' Low .if and only if ROY is High.
State 3. The 1/0 device forces ROY Low after latching the data. ROY Low causes an inter·
rupt request to be generated. The Z8 can write new data in response to ROY going
Low; however, the data is not output until State 5.
State 4. The OAV output from the Z8 is driven High in response to ROY going Low.
State 5. After OAV goes High, the 1/0 device is free to raise ROY High thus returning the in·
terface to its initial state.

State 1. RDY input is High indicating that the 1/0 device is ready

Figure 9-16.

Figures 9-17 and 9-18
handshake connections.

illustrate

the

strobed

A

P2o-P27

K,.

1/0

Z8

9.7

I/O PORT RESET CONDITIONS

After a hardware reset, .mode registers P01M, P2M,
and P3M are set as shown in Figures 9-19 - 9-22.
Ports 0, 1 and 2 are configured for input operation o~ all bits, except Port 1 in the Z8681 and
Ports 0 and 1 in the Z8682 as shown.

DEVICE

The pull-ups of Port 2 are set for open-drain. If
active pull-ups are desired for Port 3. outputs,
remember to configure them using P3M (Figure
9-22).

DAV
P31

Figure 9-17.

I,...t Strobed Handshake
using Port 2

~

P2o-P27

r
1/0

Z8

DAV
P3s
P31

DEVICE

~

Figure 9-18.

396

Z8 Output Handshake

Output Strobed Handshake
using Port 2

All special I/O functions of Port 3 are inactive,
with P30-P33 set as inputs and 'P3 4-P3 7 set as
outpuls (Figure 9-23).

I/O Ports

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

PO.-P07 M O D E : ]
OUTPUT = 00 ~
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
.
NORMAL = 0
"EXTENDED = 1

I[

~~~

"]o'!'
01 = INPUT

1X = As-A"
STACK SELECTION
o = EXTERNAL
1 = INTERNAL
P1 o-P1 7 MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7,
AS, OS, R/W, As-A", A'2-A'5

'ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682

Figure 9-19.

Z8601/11 Port 0 and 1 Reset

, R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

~

PO.-P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
"EXTENDED = 1

~
L

POO-P03 MODE
00 = OUTPUT
01 = INPUT
1X = As-A"
STACK SELECTION
o = EXTERNAL
1 = INTERNAL

'ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682

Figure 9-20.

Z8681 Ports 0 and 1 Reset

R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)

~

PO.-P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1

I [ ~~~~~'

STACK SELECTION
0= EXTERNAL
1 = INTERNAL

L-____
Figure 9-21.

P1 o-P1 7 MODE
10 = ADo-AD7

Z8682 Ports 0 and 1 Reset

397

I/o Ports

R246 P2M
Port 2 Mode Register
(% F6; Write Only)

I 1 11 1111 11 11 11 11 I

I

P20-P27 MODE

- - - - 0 OUTPUT

L.

1 INPUT

figure 9-22.

Port 2 Reset

R247 P3M

Port 3 Mode Register
(% F7; Write Only)

1010101010101?lol
II

L, "'.. "",.•", ."'''''''
1 PORT 2 PULL·UPS ACTIVE
RESERVED
o P32
1 P32

= INPUT

= DAVO/RDYO

= INPUT
'------~ ~} P33 = INPUT
o0

P33

1 1 P33
'-_ _ _ _ _ _ _ 0 P3l
1 P3l
o P3D
' - - - - - - - - - - 1 P30
L--_ _ _ _ _ _ _ _ _ ~

figure 9-23.

398

Port 3 Reset

= DAV1/RDYl

P3s
P3s

= OUTPUT

= RDYO/DAVO

= OUTPUT
P34 = DM
P34
P34

= RDY1/DAV1

= INPUT (TIN) P36 = OUTPUT (TOUT)

= DAV2/RDY2

P36

= ROY2IDAV2

= INPUT
P37 = OUTPUT
= SERIAL IN . P30 = SERIAL OUT

~~=:~~ g~F.

Chapter 10
Interrupts
10.1

INTRODUCTION

10.2

The 'l8 microcomputer allows six different interrupt levels from eight sources: the four Port 3
lines P30-P33 make up the external interrupt
sources while serial in. serial out. 'and the two
counter/timers make up the internal sources.
These interrupts can be masked and their priorities set by using the Interrupt Mask and the
Interrupt Priority. registers. All six interrupts
can be globally disabled by resetting the master
Interrupt Enable bit 07 in the Interrupt Mask register with a Disable Interrupt (Ol) instruction.
Interrupts are globally enabled by setting 07 with
'an Enable Interrupt (EI) instruction.
There are three interrupt control registers: the
Interrupt Request register (IRQ). the Interrupt
Mask register (IMR). and the Interrupt Priority
register (IPR). Figure 10-1 shows addresses and
identifiers for the interrupt control registers.
Figure 10-2 is a block diagram showing the
Interrupt Mask and Interrupt Priority logic.

INTERRUPT SOURCES

Table 10-1 presents the interrupt types. sources.
and vectors available in the l8 family of
processors.

10.2.1

External Interrupt Sources

External sources involve interrupts request lines
IRQO-IRQ3'
IRQO' IRQ1' and IRIlZ are always generated by a negative edge signal on the corresponding Port 3 pin (P3Z. P33' P31 correspond to
IRQO. IRQ1. and 1RQZ' respectively). Figure 10-3
is a block diagram for interrupt sources IRQO.
1RQ1' and IRIlZ'
When the Port 3 pin (P3 1 • P3Z' or P33) goes low.
the first flip-flop is set.
The next t.wo flipflops synchronize the request to the internal
clock and delay it by four external clock
periods. The output of the last flip-flop (IRQO'
1R1l1. or IRIl3) goes to the corresponding Interrupt
Request register.

The l8 family supports both vectored and polled
interrupt handling.
Details on vectored and
polled interrupts can be found in Sections 10.6
and 10.7.

DEC , -_ _ _ _ _ _-. HEX

IROO-IROs

IDENTIFIERS

251 ...._IN_T_E_R_R_U_PT
__
M_A_S_K-t FB

IMR

250

INTERRUPT REQUEST

FA

IRQ

249

INTERRUPT PRIORITY

F9

IPR

INTERRUPT
REQUEST

Figure 10-1.

Interrupt Control Registers
VECTOR SELECT

Figure 10-2.

Interrupt Block Diagra.

399

IRQ3 can be generated 'from an external source only
if Serial In is not enabled; otherwise, its source
is internal. The external request is generated by

a negative edge signal on P3 0 as shown in Figure
10-4. Again, the external request is synchronized
and delayed before reaching IRQ.

o

I-_----IS

o

D

D

o

IRO m
m ,= 0,1,2

R

-fl_

CLOCK--~------~

(INTERNAL)

Fi~re 10-~.

Interrupt Sources lIIIo-IRQ2 BlocIc Diagrllli

P~

P3M&

o

D

Ot-......-+--1
IRQ3

(lR03
SERIAL IN)
CLOCK __~---~
IR03 EXTERNAL SOURCE

SERIAL RECEIVER

Figure 10-4.

400

IR03
INTERNAL
SOURCE

Interrupt Source IRQ, BlocIc Diagr_

10.2.2

Requests are sampled internally during the last
cloc~ cycle before an opcode fetch (Figure 10-6).
External requests are sampled two internal clocks
earlier, due to the synchronizing flip-flops shown
in Figures 10-3 and 10-4.

Intemal Interrupt Sources

Internal sources involve interrupt requests
IRQrIRQ5.
If Serial In is enabled, IRQ3 generates an interrupt request whenever the receiver
assembles a complete byte. Interrupt level IRQ4
has two mutually exclusive sources, Counter/Timer
o (TO) and the Serial Out transmitter. If Serial
Out is enabled, an interrupt request is generated
when the transmit buffer is empty. If TO is
enabled, an interrupt request is generated at TO
end-of-count. IRQ5 generates an interrupt request
at Counter/Timer 1's (T1) end-of-count.

At sample time the request is transferred to the
second flip-flop in Figure 10-5, which drives the
interrupt mask and priority logic.
When an
interrupt cycle occurs, this flip-flop will be
reset only for the highest priority level that is
enabled.
The user has direct access to the second flip-flop
by reading and writing the IRQ register. IRQ is
read by specifying it as the source register of an
instruction and written by specifying it as the
destination register.

For more details on the internal interrupt
sources, refer to the chapters describing serial
I/O and the counter/timers.

10.'

INTERRUPT REQUEST (IRQ) REGISTER LOGIC AND
10.4 INTERRUPT INITIALIZATION

TIMING

Figure 10-5 shows the logic diagram for the
Interrupt Request register. The leading edge of
the request will set the first flip-flop, which
will remain set until interrupt requests are
sampled.

'After reset, all interrupts are disabled and must
be initialized before vectored or polled interrupt
processing can begin. The Interrupt Priority register (IPR), Interrupt Mask register (IMR) and
Interrupt Request register (IRQ) must be initialized, in that order, to start the, interrupt
process. However, IPR need not be initialized for
polled processing.

TO MASK
Q

R

SAMPLE
CLOCK

AND
PRIORITY
LOGIC

R

FROM PRIORITY
LOGIC

Figure 10-5.

Figure 10-6.

IRQ Register Logic

Interrupt Request Tilling

401

Interrupts
10.4.1

Interrupt Priority Register (IPR)
Initialization

1RQ3 (SI/P3 0 ) and IRQ5 (T 1)' another group
contains IRQO (P3 2 ) and IRQ2 (P31)' and the third
group contains IRQ1 (P3 3 ) and IRQ4 (SO/TO).

IPR (Figure 10-7) is a write-only register that
sets priorities for the ,!ix levels of vectored
interrupts in order to resolve simultaneous
interrupt requests.
(There are 48 sequence
possibilities for interrupts.) The six interrupt
levels IRQO-IRQ5 are divided into three 'groups of
two interrupt requests each. One group contains

Priorities can be set both within and between
groups as shown in Table 10-2. Bits 1 , 2 , and
05 define the priority of the individual members
within the three groups. Bits 00' 03. and 04 are
encoded to define six priority orders between the
three groups. Bits 06 and 07 are not used.

° °

R2491PR
Interrupt Priority Register
(% F9; Write Only)
/ 0 5 / 0 4 / 0 3 / O2 / 0, / Do

IRQ3, IRQ5 PRIORITY (GROUP AI
o = IRQ5 > IRQ3
1 = IRQ3 > IRQ5

~

I
INTERRUPT GROUP PRIORITY
RESERVED = 000
C>A>B=001
A> B > C = 010
A> C> B = 011
B> C > A = 100
C> B > A = 101
B > A >C = 110
RESERVED = 111

IRQO, IRQ2 PRIORITY (GROUP B)
o = IRQ2 > IRQO - - - - - - - - '
1 = IRQO > IRQ2
IRQ1, IRQ4 PRIORITY (GROUP C)
o = IRQ1 > IRQ4 - - - - - - - - - '
1 = tRQ4 > IRQ1

Figure 10-7.

Interrupt Priority Register

Table 10-2.

Interr~

Priority
Croup Priority
Highest --> lowest

NOT USED
CAB
ABC

ACB
BCA
C BA
BAC
NOT USED

402

Interrupts
SP AND STACK
AFTER INTERRUPT

SPANO STACK

BEFORE INTERRUPT

TOP OF STACK

"I~--~s-p----~~~--------~

SP

~

~----------~

PCl

~----P~C~U----~
FLAGS

Figure 10-10.

Effect of Interrupt on Stack

10.6.1

64K ....- - - - - -.....

Vectored Interrupt Cycle TiBing

Interrupt cycle timing for all Z8 devices except
the Z8681 is diagrammed in Figure 10-12. Timing
for the Z8681 ROMless device is different and is
shown in Figure 10-13.

INTERRUPT
SERVICE
ROUTINE

10.6.2 Nesting of Vectored Interrupts
12~------------~

VECTOR SELECTED BY
PRIORITY LOGIC

Nesting
priority
request.
do the
routine:

of vectored interrupts allows higher
requests to interrupt a lower priority'
To initiate vectored interrupt nesting,
folloWing during the interrupt service

Z8 PROGRAM MEMORY

•
•

Figure 10-11.

Interrupt Vectoring
•
•
'.

10.6 VECTORED PROCESSING
Each Z8 interrupt level has its own vector. When
an interrupt occurs, control passes to the service
routine pointed to by the interrupt's location in
program memory. The sequence of events for vectoredinterrupts is as follows:
,.
•
•
•
•
•

PUSH PC ,lower byte on stack
PUSH PC upper byte on stack
PUSH FLAGS on stack
Fetch upper byte of vector
Fetch lower byte of vector
Branch to service routine spec'i fied by vector

Figures 10-10 and
interrupt operation.

10-11

show

the

vectored

•
•

Push the old IMR on the stack.
Load IMR, with a new mask to disable lower
priority interrupts.
Execute EI instruction.
Proceed with interrup~ processing.
After processing is complete, execute 01
instruction.
Restore the IMR to its original value by
returning the previous mask from the stack.
Execute IRET.

Depending on the application, some simplification
of the above procedure may be possible.

10.7

POLLm PROCESSING

Polled interrupt processing. is supported by
masking off the IRQ levels to be polled. This is
accompUshed by clearing the corresponding bit in
the IMR to O.

403

To initiate polled processing, check the bits of
interest in the IRQ using the Test Under Mask (TM)
instroction. If the bit is set, call or branch to
the' service routine. The service routine services
the request, resets its Request bit in the IRQ,
and branches or returns back to the main program.
An example of a polling routine is as follows:
TM IRQ ,HMASK
JR Z NEXT
CALL SERVICE

! Test for request
!If no request go to NEXT
!If request is there
!then service 'it

NEXT:

SERVICE:

!Process Request

AND IRQ,HMASK_ !Clear Request bit
RET
! Return to next
In this example, i f IRQ2 is being polled, MASK
will be 1~200DD01DO (in binary) and MASK_ will be
%211111011.

404

10.8

REsET ClNHTIONS,

During a reset, all bits in IPR are undefined.
In IMR, bit D7 is 0 and bits DO-05 are undefined.
Bit 06 is not implemented, though reading this bit
returns O.
IRQ bits 00-05 are held at 0 until an EI ,instruction is executed. Bits D6 and D7 are not implemented, but reading these bits returns O.

I_M1_I-M2_I_M3_I_STACKPUSH_I-STACKPUSH-I_STACKPUSH_I~7_I-Mt_I-M2INTERNAL
CLOCK

.-

Os
ADo-AD7 OUT

r····

1

LJ

1---.,

~~FOREXTERNAL EXECUT~ON ONLY-----

o

0

I pC+11
_

ADO-AD7 IN

1!2-----I

I

I

SP-1

pel

I SP-21

pCu

L ___

~

'"--FOR STACK EXTERNAL ONLY

FOR EXTERNAL EXECUTION

SP-31

I

FLAGS

I

FLAGS)

OPCOOE (DISCARDED)
.

VEer

I

FIRST INSTRUCTION OF INTERRUPT
SERVICE ROUTINE

ONLY~

0
-0'

' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....I-FOR STACK EXTERNAL ONLY

AlW

figure 10-12.

ROM Z8 Interrupt Tbling (shrink parts)

- - - - ! - _ - - M s - I _ S T A C K PUSH_14---STACK PUSH_I_STACK

pusH_l--vEc~~TRc~,GH_l-- VEciT~;~ow_I_M1-f_M2-

INTERNAL
CLOCK

Os
ADo-AD7 OUT

ADo-AD7 IN

0

B

o

1.P-1 1

PC,

1.P-2 1

PC,

1.P-3 1

FLAG. -

1

I:::>

EVEN VECTOR ADDRESS

rI-

ODD

VE~DRES-;>

,VECT"

O-OPCODE (DISCARDED)

I

, vECT,1

VEeT

I

O~
VECT+1

0-....

-FIRST INSTRUCTION OF INTERRUPT SERVICE ROUTINE----'

AlW

' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J.-FOR STACK EXTERNAL ONLY

figure 10-13.

~
U1

Z8681 ROMless Z8 Interrupt Tiung

Chapter 11
Counter/Timers
11.1

INTRODUCTION

The Z8 provides two 8-bit counter/timers, 'TO and
ri' each driven by its own 6-bit prescaler, PRE O
and PRE 1 • Both counter/timers are independent of
the processor instruction sequence, which relieves
software from time-critical operations such as
interval timing or event counting.

Each counter/timer operates in either Single-Pass
or Continuous mode. At the end-of-count, counting
either stops or the initial value is reloaded and
counting continues.
Under software control, new
values are loaded immediately or when the end-ofcount is reached. Software also controls counting
mode, how a counter/timer is started or stopped,
and its u'je of I/O lines. Both the counter and
prescaler registers can be altered while the
counter/timer is running.

,-----------,

INTERNAL DATA BUS
r------------~-----

PREO
INITIAL VALUE
REGISTER

TO
INITIAL VALUE
REGISTER

6·BIT
DOWN COUNTER

8·BIT
DOWN COUNTER

TO
CURRENT VALUE
REGISTER

IRQ4
INTERNAL
CLOCK

SERIAL 1/0
CLOCK

TOUT'
P36

EXTERNAL CLOCK

CLOCK
LOGIC

IRQ5
+4

6·BIT
DOWN COUNTER

8·BIT
DOWN COUNTER

PRE1
INITIAL VALUE
REGISTER

11

11

INITIAL VALUE
REGISTER

CURRENT VALUE
REGISTER

INTERNAL CLOCK
GATED CLOCK
TRIGGERED CLOCK

TIN P31

Figure 11-1.

406

COunter/Tiaer Block Diagr..

Counter/Timers
Counter/timers 0 and 1 are driven by a timer clock
generated by dividing the internal clock by four.
The divide-by-four stage, the 6-bit prescaler, and
the 8-bit counter/timer form a synchronous 16-bit
divide chain. Counter/timer 1 can also be driven
by an external input (TIN) via Port 3 line P3 1 •
Port 3 line P3 6 can serve as a timer output
(T OUT) through which TO' Tl' or the internal
clock can be output. The timer output will toggle
at the end-of-count.
Figure 11-1 is a block
diagram of the counter/timers.

regist.er which holds the initial count value, and
a read-only register which holds the current count
value (Figure 11-1). The initial value can range
from 1 to 256 decimal (%01,%02, •• ,%00).
Figure
11-5 illustrates the counter/ti~er registers.

R245 PREO
Prescaler 0 Register
(% F5; Write Only)

The counter/timer, prescaler, and associated mode
registers are mapped into the register file as
shown in Figure 11-2. This allows the software to
treat the counter/timers as general-purpose
registers, and eliminates the need for special
instructions.

11.2 PRESCAlERS AND COUNTER/rIMERS
The prescalers, PRE O (%F5) and PRE 1 (%F3), each
consist of an 8-bit register and a 6-bit
down-counter as shown in Figure 11-1.
The
prescaler registers are write-only registers.
Reading the prescalers returns the value %FF.
Figures 11-3 and 11-4 show the prescaler
registers •
. The six most significant bits (D 2-D7 ) of PRE O or
PRE 1 hold the prescalers count modulo, a value
from 1 to 64 decimal.
The prescaler registers
also contain control bits that speci fy TO and T1
counting modes. These bits also indicate whether
the clock source for T1 is internal or external.
These control bits will be discussed in detail
throughout this chapter.
The counter/timers, TO' (%F4) and T1 (%F 2 ), each
consist of an a-bit down-counter, a write-only

~

o=
1

To SINGLE·PASS

= To MODULO·N

RESERVED (MUST BE 0)
PRESCALER MODULO
'--------(RANGE: 1-64 DECIMAL
1}1-00 HEX)

Figure 11-3.

Prescaler

o Register

R243 PRE1
Prescaler 1 Register
(% F3; Write Only)

C

COUNTMODE
1 = T, MODULO·N
o = T, SINGLE·PASS
CLOCK SOURCE
1 = T, INTERNAL
= T, EXTERNAL(TIN)

o

PRESCALER MODULO
' - - - - - - - (RANGE: 1-64 DECIMAL
01-00 HEX)

Figure 11-4.

Prescaler 1 Register

HEX IDENTIFIERS

DEC

247

COUNTMODE

PORT 3 MODE

F7

P3M

245

TO PRESCALER

F5

PREO

244

TIMER/COUNTER 0

F4

TO

243

T1 PRESCALER

F3

PRE1

242

TIMER/COUNTER 1

F2

11

~41

TIMER MODE

F1

TMR

R242 T1
Counter/Timer 1 Register
(% F2; Read/Write)
R244 TO
Counter/Timer 0 Register
(% F4; Read/Write)

I~I~I~I~I~I~I~I~I

L

INITIAL VALUE WHEN WRITTEN (RANGE 1·256 DECIMAL, 01-()0 HEX)
CURRENT VALUE WHEN READ

407

11.J

CQlNTER/TII£R OPERATION

both

reach their end-of-count, an interrupt
is generated -- IRQ4 for f 0 and 1RQ5 for
Tl' Depending on the counting mode selected, the
counter/timer will either come to r,est with its
value at %00 (Single-Pass mode) or the initial
value will be automatically reloaded and counting
will continue (Continuous mode).
~equest

Under software control, counter/timers are started
and stopped via the Timer Mode register (%F1) bits
°0-03 (Figure 11-6). Each counter/timer is associated with a Load bit and an Enable Count bit.

11.J.1

Load and Enable Count Bits

Setting the Load bit (DO to 1 for TO and 02 to 1
for T1) transfers the initial value in the prescaler and the counter/timer r~gisters into their
respective down-counters. The next internal clock
resets bits 00 and 02 to 0, readying the Load bit
for the next load operation. The initial values
may be loaded into the down-counters at any time.
I f the counter/timer is running, it continues to
do so and starts the count over with the initial
value. Therefore, the Load bit actually functions
as a software re-trigger.

R241 TMR'
Timer Mode Register
(% F1; Read/Write)

L °1 == NO
FUNCTION
LOAD To

~

o=
1

DISABLE To COUNT

= ENABLE To COUNT

o=

NO FUNCTION

= LOADT,
L -_ _ _ _ O = DISABLE T, COUNT
1

1 = ENABLE T, COUNT

The counter/timers remain at rest as long as the
Enable Count bits 01 and OJ are both O. To enable
counting, the Enable Count bit (01 for TO and 03
for T1) must be set to 1.
Counting actually
starts when the Enable Count bit is written by an
instruction.
The first decrement occurs four
internal clock periods after the Enable Count bit
has been set.
The Load and Enable Count bits can be set at the
same time. For example, using the instruction OR
TMR #%03 sets both DO and 01 of n.fR to 1. This
loads the initial values of PRE O and TO into their
respective counters and starts the count after the
M2 f2 machine state after the operand is fetched
(Figure 11-7).

Figure 11-6.

Timer Mode Register

M3

TMR IS WRITTEN
COUNTER/TIMERS
ARE LOADED
1ST DECREMENT
OCCURS FOUR
CLOCKS LATER

figure 11-7.

Starting The Count

11.J.2 Prescaler Operations
During counting, the programmed clock source
drives the prescaler 6-bit counter. The counter
is counted down from the value specified by bits
02-07 of the corresponding prescaler register,
PRE O or PRE 1 (Figure 11-8). When the prescaler
counter reaches its end-of-count, the initial
value is reloaded and counting continues.
The
prescaler never actually reaches O. For example,
if the prescaler is set to di~ide by 3, the ~ount
sequence is:

R243 PRE1'
Prescaler 1 Register
(% F3; Write Only)
R245 PREO
Prescaler 0 Register
(% F5; Write Only)

Lo

COUNT MODE
1 = T, MODULO·N
= T, SINGLE·PASS

3-2-1-3-2-1-3-2 ••••
Each time the prescaler reaches its end-of-count a
carry is generated, which allows the counter/timer
to decrement by one on the next timer clock
inpuL
When the counter/timer and the prescaler

408

Figure 11-8.

Counting Modes

Counter/Timers
The counting modes are controlled by bit DO of
PRE O snd PRE 1 ' with DO cleared to 0 for
Single-pass counting mode or set to
for
Continuous mode.
The counter/timers can be stopped at any time by
setting the Enable Count bit to 0, and restarted
"by setting it back to 1. The counter/timer will
continue its count value at the time it was
stopped. The current value in the counter/timer
(TO or T1 ) can be read at any time without
affecting the counting operation.
New initial values can be written to the prescaler
or the counter/timer registers at any time. These
values will be transferred to their respective
down-counters on the next load operation. If the
counter/timer mode is Continuous, the next load
occurs on the timer clock
following
an
end-of-count.
New initial values should be
written before the desired load operation, since
the prescalers always effectively operate in
Continuous count mode.

register P3M (IIIF7) (Figure 11-9) to configure P3 6
for TOUT operation.
In order for TOUT to
function, P3 6 must be defined as an.output line by
setting P3M bit 0 5 to O. Output is controlled by
one of the counter/timers (TO .or T1 ) or the
internal clock.
The counter/timer to be output is selected by TMR
bits 07 and 06 •
TO is selected to drive the·
TOUT line by setting 07 to
and 06 to 1.
Likewise, T1 is selected by setting 07 and b 6 to 1
and
respectively. The counter/timer TOUT mode
is turned off by setting TMR bits 07 and 0 6 both
to 0, freeing P3 6 to be a data output line.

°

°

TOUT is initialized to a logic 1 whenever the
TMR Load bit (DO for TO or .02 for r1) is set to 1.

R247 P3M
Port 3 Mode Register
(% F7; Write Only)

The time inter vel (i) until end-of-count, is given
by the equstion
i:txpxv
in which t is 8 divided by XTAL frequency, p is
the presc"aler value (1 - 64), and v is the
counter/timer value (1 - 256).
It should be
apparent that the prescaler and counter/timer are
true divide-by-n counters.

11.4 TOUT MODES
The Timer .Mode register TMR (IIIF1) (Figure 11-10)
is used in conjunction with the Port 3 Mode

o
1

P31
P31

=INPUT (TIN)

P38

= OUTPUT (Tour>

= DlV2IRDY2 P38 = RDY2IDlW2

Figure 11-9.
Port :5 Mode Register TOOT Operation

R241 TMR
Timer Mode Register
(% F1; ReadIWrite)

TOUT MODES
TOUT OFF = 00
To OUT = 01
Tl OUT = 10
INTERNAL CLOCK OUT
11

=

I

L

o
1

= NO FUNCTION

o
1

= NO FUNCTION
= LOAD T,

= LOAD To

Figure 11-10. Tiller ~ Register TOOT Operation

409

Counter/Timers
IR04
(TO END-Of-COUNT)

IROS
(T1 END-Of-COUNT)

~TMR

D7-D6

Figure 11-11.

= 10

Counter/Tillers Output Via TOUT

INTERNAL
CLOCK

&

.....+.2_;-.. .--<)"""-..___

TOUT

--r-'\.....J

TMR D6
TMRD7~

Figure 11-12.

Internal Clock Output Via TOUT

At end-oF-count, the interrupt request line (IRQ4
or IRQ5)' clocks a toggle flip-flop. The output
of this flip-flop drives the TOUT line, P3 6 • In
all cases, when the selected counter/timer reaches
its end-oF-count, TOUT toggles to its opposite
state (F igure 11-11) •
If, For example, the
counter/timer is in Continuous counting mode,
TOUT will have a 50% duty cycle output.
This
duty cycle can easily be controlled by varying the
initial values aFter each end-oF-count.
The internal. clock can be selected as output
instead of TO or T1 by setting TMR bits D7 and D6
both to 1. The internal clock (XTAL Frequency/2)
is then direct~y output on P3 6 (Figure 11-12).
While programmed as TOUT' P3 6 cannot be modified
by a write to port register P3. However, the ZB
soFtware can examine P3 6 's current output by
reading the port register.

11.5

TINIDlES

R241 TMR
Timer Mode Register
(% F1; Read/Write)

T'N MODES
EXTERNAL CLOCK INPUT = 00
GATE INPUT = 01
TRIGGER INPUT = 10
(NON-RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)

figure 11-13.

Tiller Mode Register TIN Operation

R243 PRE1
Prescaler 1 Register
(% F3; Write Only)

ID,I

The Timer Mode register TMR (%F1) (Figure 11-13)
is used in conjunction with the Prescaler register
PRE 1 (%F3) (Figure 11-14) to configure P3 1 as
TIN"
TIN is used in conjunction with T1 in
one of Four modes:
•
•
•
•

External clock input
Gated internal clock
Triggered internal clQck
Retriggerable internal clock

410

L

CLOCK SOURCE
1 = T, INTERNAL
EXTERNAL (T,N)

o = T,

figure 11-14.

Prescaler 1 TIN Operation

Counter/Timers
The counter/timer clock source must be configured
for externsl by setting PRE 1 bit 02 to 0. The
Timer Mode register bits 05 snd 04 csn then be
used to select the desired TIN operation.

11.5.1

The TIN External Clock Input mode (TMR bits 05
and 04 both set to 0) supports, counting of
external events, where an event is considered to
be a High-to-Low transition on TIN (Figure
11-15). occurrence (Single-Pess mode) Of on every
nth occurrence (Continuous mode) of that event.

For T1 to start counting ss a result of s TIN
input, the Enable Count bit 03 in TMR must be set
to 1. When using TIN as an external clock or a
gate input, the initial values must be loaded into
the down-counters by setting the Load bit 02 in
TMR to a 1 before counting begins.
In the
,descriptions of TIN that follow, it is assumed
that, the programmer has performed these operations.
Initial, values are automatically loaded
in Trigger and Retrigger'modes so software loading
.is unnecessary.

11.5.2 Gated Internal Clock Mode
The TIN Gated Internal Clock mode (TMR bits D5
and D4 set to 0 and 1 respectively) measures the
duration of an external event. In this mode, the
T1 prescaler is driven by the internal timer
clock, gated by a High 'level on TIN (Figure
T1 counts While TIN is High snd stops
11-16).
counting while TIN is Low.
Interrupt request
IRQ2 is generated on the High-to-Low transition of
TIN' signaling the end of the gate input.
Interrupt request IRQ5 is generated if T1 reaches
its end-of-count.

It is suggested that P3 1 be configured as an input
line by setting P3M bit 05 to 0 although TIN is
still functional i f P3 1 is configured as a handshake input.
'Each High-to-Low transition on TIN' generates
interrupt request IRQ2' regardless of the selected
TIN mode or the enabled/disabled state of Tl '
IRQ2 must therefore be masked or enabled according
to the needs of the application.

TIN
CLOCK

- P31

INTERNAL
CLOCK

External Clock Input Mode

D

D

A

A

t

t

PRe1

T1

r--

IRQ5

IRQ2

Figure 11-15. External Clock Input Mode

PRE1

T1

~

IRQ5

IRQ2

Figure 11-16. Gated Clock Input Mode

411

~

I\)

INTERNAL

CLOCK
TMR

IRQ5

EDGE
TRIGGER

r----l
T,N
TRIGGER

-I

P31

1

D

SL

IRQ2

Figure 11-17.

OSC

PREO

TO

Figure 11-18.

Triggered Clock Mode

P3s

PRE1

T1

IRQ5

Cascaded Counter/TWers

....,

b'

c:

:l_

en
"'.....

.... -

..,3en
Ul

Counter/Timers
11.5.3 Triggered Input Mode
The TIN Triggered Input mode (TMR bits 05 and
04 set to 1 and 0 respectively) causes T1 to start
counting as the result of an external event
(Figure 11-17). T1 is then loaded and clocked by
the internal timer clock following the first HighSubsequent
to-Low transition on the TIN input.
TIN transitions do not affect Tl'
In the Single-Pass mode, the Enable bit is reset whenever T1
reljches its end-of-count.
Further TIN transitions will have no effect on T1 until software
sets the Enable Count bit again.
In Continuous
mode, once T1 is triggered counting continues
until software resets the Enable Count bit.
Interrupt request IRQ5 is generated when T1
reaches its end-of-count.
11.5.. Retriggerable Input Mode
The TIN Retriggerable Input mode (TMR bits 05
and 04 both set to 1) causes T1 to load and start
counting on every occurrence of a High-to-Low
transition on TIN (Figure 11-17).
Interrupt
request IRQ5 will be generated i f the programmed
time interval (determined by T1 prescaler and
counter/timer register initial values) has elapsed
since the last High-to-L9W transition on TIN'
In Single,..Pass mode, the end-of-count resets the
Enable Count bit.
Subsequent TIN transitions
will not cause T1 to load an~ start counting until
software sets the Enable Count bit again. In Continuous mode, counting continues once T1 is triggered until software resets the Enable Count bit.
When 'enabled, each High-to-Low TIN transition
causes T1 to reload and restart counting. Interrupt request IRQ5 is generated on every end-ofcount.

IRQ4 (TO end-of-count) are also generated but are
most likely of no importance in this configuration
and should be disabled.

11.7

RESET CONDITIONS

After a hardware reset, the counter/timers are
disabled and the contents of both the counter/
timer registers and the prescaler modulos are
undefined.
However, the counting modes are
configured for Single-Pass and Tl' s clock source
is set for external.
TIN is set for External
Clock mode, and the TOUT mode is off. Figures
11-19 through 11-22 show the binary reset values
of the Prescaler, Counter/Timer, and Timer Mode
registers.

R24211
Counter/Timer 1 Register
(% F2; Read/Write)

R244 TO
Counter/Timer 0 Register
(% F4; Read/Write)

L

INITIAL VALUE WHEN WRITTEN
(RANGE 1·256 DECIMAL, 01·00 HEX)
CURRENT VALUE WHEN READ

figUre 11-19.

R243 PRE1
Prescaler 1 Register
(% F3; Write Only)

l

11.6 CASCADING COUNTER/TIMERS
For some applications, it may be necessary to measure a time interval greater than a single counter/timer can measure.
In this case, TIN and
TOUT can be used to cascade TO and T1 as a single unit (Figure 11-1B). TO should be configured
to operate in Continuous mode and to drive
TOUT'
TIN should be configured as an external
clock input to T1 and wired back to TOUT'
On
every other TO end-of-count, TOUT undergoes a
High-to-Low transition which causes T1 to count.
T1 can operate in either Single-Pass or Continuous
mode.
Each time Tl' s end-of-count is reached,
interrupt request IRQ 5 is generated.
Interrupt
requests IRQZ (TIN High-to-Low transitions) and

Counter/Tiller Reset

.

COUNTMODE
1 = T, MODULO·N
o = T, SINGLE.P.ASS
CLOCK SOURCE
1 = T, INTERNAL
o = T, EXTERNAL (TIN)

PRESCALER MODULO
'--------(RANGE: 1-64 DECIMAL
01~00 HEX)

Figure 11-20.

Preacaler 1 Register Reset

413

Counter/Timers

R245 PREO
Prescaler 0 Register
(% F5; Write Only)

l

1?1?1?1?1?1?1?lol

C~~Nio ~~~ELE.PASS
1

= To MODULO·N

RESERVED

PRESCALER MODULO
'-------(RANGE: 1-64 DECIMAL
01-00 HEX)

Figure 11-21. ' Prescaler 0 Reset

R241 TMR
Timer Mode Register
(% F1; Read/Write)

I 0 1 0 10 I 0 I 0 I 0 I 0 I 0 I

TOUT MODES
TOUT OFF = 00
To OUT = 01
T, OUT
10
INTERNAL CLOCK OUT = 11

I

L 01 == NO
FUNCTION
LOAD To

~

=

414

1
o
1

IN~OTM~D~S

. EXTERNAL CLOCK
GATE INPUT = 01
TRIGGER INPUT = 10
(NON·RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)

Figure 11-22.

o=

'--_ _ _ 0
1

T~r

=
=
=
=
=

DISABLE To COUNT
ENABLE To COUNT
NO FUNCTION
LOAD T,
DISABLE T, COUNT
ENABLE T, COUNT

Mode Register R,eset

Chapter 12

Serial 1/0
12.1

INTRODUCTION

The Z8 microcomputer
contains
an
on-board
full-duplex receiver/transmitter for asynchronous
data communications.
The receiver/transmitter
consists of a Serial I/O register SIO (%F1) and
its associated control logic (Figure 12-1).
The
SIO is actually two registers--the receiver buffer
and the transmitter buffer--which are used in
conjunction with counter/timer TO and Port 3 I/O
lines P30 (input) and P37 (output). Counter/timer
r0 provides the clock input For control of the
data r'ates.
Configuration of the ser ial I/O is controlled by
the Port 3 Mode register, P3M.
The Z8 always
transmits B bits between the start and stop bits;
that is, 8 data bits or 7 data bits and 1 parity
bit.
Odd parity generation and detection is
supported.

allows the software to access the serial I/O as
general-purpose registers, eliminating the need
for special iAstructions.

12.2 BIT RATE GENERATION
When Port 3 Mode register bit 0 6 is, set to 1, the
serial I/O .is enabled and TO automatically becomes
the bit' rate generator (Figure 12-3). TO'S endof-count signal no longer generates interrupt
request IRQ4; instead, the signal is used as the
input to the divide-by-16 counters (one each for
the receiver and the transmitter) which clock the
dat a stream.
The divide chain that generates the bit rate is
shown'in Figure 12-4. The bit rate is given by
the following equation:
bit rate

The Serial I/O register and its associated Mode'
Control registers are mapped into the register
file as shOwn in Figure 12-2. This organization

f

.-

where p and t are the initial values in the
Prescaler
and
Counter/Timer
registers,
respectively.

INTERNAL DATA BUS

,

SERIAL
IN

f-r-

+START
CLOCK
CONTROL

t

STOP
BIT
DETECT

TRANSFER

RECEIVER
SHIFT
REGISTER

49

I
I

IRQ4

WRITE %FO

1'1

START
BIT
DETECT

rI

frequency/(2 x 4 x p x t x 16)

READ%F~n
RECEIVER
BUFFER

P30

= XTAL

MARK

7-

~

I-

CHAR
DETECT

SHIFT
CLOCK

CHECK

r

TRANSMITTER
SHIFT
REGISTER

t

I-

L.::lD.-

SERIAL
OUT

t-

SHIFT
CLOCK

RESET

+16

PARITY
GEN

IRQ3

+6

STOP

SERIAL
110 CLOCK
(FROM TO)

Figure 12-1.

Serial I/O Block Diagr_

415

· Serial I/O
The final divide-by-16 is required since TO runs
at 16 times the bit rate in order to synchronize
on the incoming data.

HEX IDENTIFIERS

DEC

247

To configure the Z8 for a specific bit rate,
appropriate values as determined by the above
equation must be loaded into registers PREO (%~5)
and TO (%F4).
PREO also controls the counting
mode for TO and should therefore be set to the
Continuous mode (Do set to 1).
For example, given an input clock frequency
(fXTAL) of 11.9808 MHz and a selected bit rate of
1200 bits per second, the equation is sati~fied by
p=39 and t=2. Counter/timer TO should be set to
%02.
With TO in Continuous mode, the value of
PREO becomes %90 CFigure 12-5).

PORT 3 MODE

F7

P3M

245

TO PRESCALER

F5

PREO

244

TIMER/COUNTERO

F4

TO

240

SERIAL I/O

FO

510

Figure 12-2. Serial I/O Register Map

Table 12-1 lists ·several commonly used bit rates
and the values of fXTAL, p, and t required to
derive them.
This list is presented for convenience and is not intended to be exhaustive.

R247 P3M
Port 3 Mode Register
(% F7; Write Only)

The bit rate generator is started by setting the
Timer Mode register TMR (%F1) bits Dl and DO both
to 1 (Figure 12-6). This transfers the contents
of the Prescaler· and Counter /T imer registers to
their corresponding down-counters.
In addition,
counting is enabled so that serial I/O operations
begin.

L, . . . "'"

1 P30 = SERIAL IN

P37
P37

= OUTPUT
= SERIAL OUT

Figure 12-3. Port 3 Mode Register
and Bit Rate Generation

fXTAL

~r::L--r::-L.-r:-L--r:-LI:l-.- ~~TE

~~~CLOCK
PREO

TO

Figure 12-4. Bit Rate Divide Chain

Table 12-1. Bit Rste
7,3728

416

Bit
Rate

p

19200
9600
4800
2400
1200
600
300
150
110

3
3
3
3
3
3
3
3
3

t

7,9872

P
1
2
4
B

16
32
64
128
175

t

-- --, -1
2
4
8
16
32
3 189

13
13
13
13
13
13

9,8304

P
4
4
4
4
4
4
4
4
4

t

11,0592

P
1
2
4

1\

16
32
64
128
175

t

-- -9
9
~

9
9
9
9
5

1
2
4
8
16
32
64
157

11,6736

P

t

11,9808

P

t

-- -- -- --- -- -- -19
1
-- -19
19
19
19
19
4

2
4
8
16
32
207

39
39
39
39
39
17

1
2
4
8
16
50

12,2880

P

t

5
1
2
5
5
4
8
5
16
5
32
.5
64
5
5 128
8 109

Serial I/O
12.3 RECEIVER OPERATION

R245 PREO
Prescaler 0 Register
(% F5; Write Only)

1110101111111 111

L

COUNT MODE
o = To SINGLE·PASS
1 = To MODULO·N

The receiver consists of a, receiver buffer (SID
[%rO]), a serial-in, parallel-out Shift register,
parity checking, and data synchronizing logic.
The receiver block diagram is shown as part ,of
Figure 12~1.

12.3.1

1..-_ _ _ _ _ _ PRESCALER MODULO

0=64

rigure 12-5. Prescaler 0 Register
and Bit Rate Generation

R241 TMR
Timer Mode Register
(% F1; Read/Write)

~o

=
=
=
l' =

0
1

NO FUNCTION
LOAD To
DISABLE To COUNT
ENABLE To COUNT

rigure 12-6. Timer Mode Register
and Bit Rate Generation

Receiver Shift Register

After a hardware reset or after a character has
been received, the Receiver Shift register is
initialized to all 1a and the shift clock is
stopped. Serial data, input through Port 3 pin
P30, is synchronized to the internal clock by two
D-type flip flops before being input to the Shift
register and the start bit detection circuitry.
The start bit detection circuitry monitors the
incoming data stream, looking for a start bit (a
High-to-Low input transition). When a start bit
is detected, the shift clock logic is enabled.
The TO input is divided by 16 and, when the count
equals B, the divider outputs a shift clock. This
clock, shifts the start bit into the Receiver Shift
register at the center of the bit time. Before
the shift actually occurs, the input is rechecked
to ensure that the start bit is valid.
If the
detected start bit is false, the receiver is reset
and the process of looking for a start bit is
repeated. If the start bit is valid, the data is
shifted into the Shift register every sixteen
counts until a full character is assembled (Figure
12-7) •

(RI
RCVR

DATA

SHIFT _ _ _"",
CLOCK
RCVR ___________________________________~______

IRQ3

I

I

I

SHIFT REGISTER CONTENTS
TRANSFERRED TO RECEIVER
BUFFER AND IRQ3 IS
GENERATED

rigure 12-7.

Receiver Tillling

417

Serial I/O
After a full character has been assembled in the
Shift register, the data is transferred to the
receiver's buffer, 510 (%FO), and interrupt
request IRQ3 is generated.
The shift clock is
stopped and the Shift register reset to all 1 s.
The start bit detection circuitry begins monitoring the data input for the next start bit. This
cycle allows the receiver to synchronize on the
center of the bit time for each incoming character.

12.3.2 Overwrites
Although the receiver is buffered, it is not protected from being overwritten, so the software
must read the SID register within one character
time after the interrupt request. The Z8 does not
have a flag to indicate this overrun condition.
If polling is used, the IRQ3 bit in the Interrupt
Request register must be reset by software.

12.3.4 Parity
The data format supported by the receiver must
have a start bit, eight data bits, and at least
one stop bit. If parity is on, bit 0 7 of the data
received will be replaced by a Parity Error flag.
A parity error sets 0 7 to 1; otherwise, 07 is set
to O. Figure 12-8 shows these data formats.
The Z8 hardware supports odd parity only, which is
enabled by setting Port 3 Mode register bit 0 7 to
1 (Figure 12-9). If even parity is required, the
Parity mode should be disabled (i.e. P3M 07 set to
0), and software must calculate the received
data's parity.

12.4

TRANSMITTER OPERATION

The transmitter consists of a transmitter buffer
(SID (%FO», a parity generator, and as,sociated
control logic. The transmitter block diagram is
shown as part of Figure 12-1.

12.3.3· Fraaing Errors
Framing error detection is not supported by the
receiver hardware, but by responding to the interrupt request within one character bit time, the
software can test for a stop bit at P30' Port 3
bits are always readable, which facilitates break
detection. For .example, if a null character is
received, testing P30 results in a 0 being read.

After a hardware reset or a fter a character has
been transmitted, the transmitter is forced to a
marking state (output .always High) until a character is loaded into the transmitter buffer, SID
(%FO).
The transmitter is loaded by specifying
the 510 as the destination register of any
instruction.

Received Data
(No Parity)

I~I~I~I~I~I~I~I~I~I~I

I

LSTART BIT
' - - - - - - - - E I G H T DATA BITS.

'-.- - - - - - - - - - - - - O N E STOP BIT

Received Data
(With Parity)

1~lpl~I~I~I~I~I~I~I~1

II

LSTART BIT'
'-------SEVEN DATA BITS

' - - - - - - - - - - - - - P A R I T Y ERROR FLAG

' - - - - - - - - - - - - - O N E STOP BIT

Figure 12-8.

418

Receiver Data Foraats

R247 P3M
Port 3 Mode Register
(% F7; Write Only)
12.4.1 Overwrites
The user is not protected from overwriting the
transmitter, so it is up to the software to
respond to IRQ4 appropriately.
If polling is
used, the IRQ4 bit in the Interrupt Request register must be reset.

12.4.2 Parity
The data format supported by the transmitter has a
start bit, eight data bits, and at least two stop
bits. If parity is on, bit D7 of the data transmitted will be replaced by an odd parity bit.
Figure 12-10 shows the transmitter data formats.

o pARITY OFF
1 PARITY ON

Figure 12-9. Parity and Part' Mode Register

TO's output drives a divide-by-16 counter which in
turn generates a ahift clock every 16 counts •.
This counter is reset when the tranamitter buffer
is written by an instruction.
This 'reset
synchronizes the shift clock to the software, The
.transmitter then outputs one bit per shift clock,
through Port J pin PJ 7 , until a start bit, the
character written to the buffer, and two stop bits
have been transmitted. ~fter the second stop bit
has been transmitted, the' output is agsin forced
to a marking state.
Interrupt request IRQ4 is

Parity is enabled by setting Port J Mode register
bit D7 to 1.
If even padty is required, the
parity mode should be disabled (i.e. P3M 07 set to
iJ), and software must modify the data to include
.'
.
even parity.
Since the transmitter can be overwritten, the user
is able to generate a break signal. This is done
by writing null characters to the transmitter buffer (510, %FO) at a rate which does not allow the
stop bits to be output. Each time the 510 is
loaded, the di vide-by-16 counter is re-synchronized and a new start bit is' output followed by
data.

TransmItted Data
iNo Parity)

T

LSTARTBIT
L - - - - - - - E I G H T DATA BITS
TWO STOP BITS

TransmItted Data
(With ParIty)

Isplsplpl~I~I~I~I~I~I~I~1

T
I

Figure 12-10.

1~_LsTARTBIT

--

Tranallitter

SEVEN DATA BITS
ODD PARITY
TWO STOP BITS

~ata

Far_s

419

Serial I/O
12.5 RESET CONDITIONS

After a hardware reset, the Serial I/O register
contents are undefined, and serial mode and parity
Bre disabled. Figures 12-11 and 12-1,2 ~how the
binary reset values of the Serial I/O register and
its associated mode register PJM.

R240 SIO
Serial 1/0 Register
(% FO; ReadIWrite)
bl?I?I?I?I?I?ld
I'------SERIAL DATA (Do

Figure 12-11.

= LSB)

Serial I/O Register Reeet

R247 P3M
Port 3 Mode Register
(% F78; Write Only)

1010101010101 101

~

o1 PORT
2 PULL·UPS OPEN DRAIN
PORT 2 PULL·UPS ACTIVE
o P32

= INPUT
P3S = OUTPUT
1 P32 = DAViilRDYO P3S = RDYO/DAVO

o0

P33 = INPUT

P34 = OUTPUT

'------~ ~ } P33 = INPUT

P34 = DM
1 1 P33 = DAlR/RDYl P34 = RDYl/DAVl

'--_ _ _ _ _ _ _ 0 P3l = INPUT (T,N) P36 = OUTPUT (TOUT)
1 P3l = DAV2JRDY2 P36 = RDY2JDAV2

'--~------- ~ ~~g ~ ~N~~rLIN ~~~ ~ ~~~r,.ULTOUT

'--_________
Figure 12-12.

420

~ ~!=:~~ g~F

Port, Register Reeet

A .

421

422

Appendix .I.
Pin Descriptions
and Functions
This appendix co~taina pin information and physical descr iptions for the Z8 development device
(Z8612) and Protopack emu~ator (Z8603/13). Pin
descriptions for the Z8601/11 snd Z8681/82 microcomputers can be found in Chapters 6 and 7,
respectively.

cycle when the first 4K bytes of program memory
are being accessed.
SClK. Syst_ Clock (output). SCLK is the internal clock output through a buffer. The clock rate
is equal to one-half the crystal frequency.
SYNC.

A.1

The pin mnemonics and descriptions presented for
the Z8 microcomputers (Chapter 6) slso spply to
the development device. Additionsl pin descriptions srs ss .follows:

Ap-A11 • Progr_ Me.ory Address (outputs). These
lines are used to sccess the first 4K bytes of the
externsl program memory.

00-07.

Progr_ Data (inputs). Data from the
external program. memory is input through these
pins.

lACK.
High).

Interrupt

Acknowledge

(output,

lOll).

active lOll).

A.2

PROTOPACK EMUlATOR (Z8603/13)

80th the Z8603 and Z8613 devices use a 40-pin
package that also hag a .24-pin "piggy-back" soc-.
keto An EPROM or ROM can be installed on the back
of the emulator's standard 40-pin package via the
socket (Figure A-3). A single +5 V dc power source
is requi~ed. Figure A-4 illustrates the pinout for
the socket carried piggyback. The socket is
designed to accept a 2716 EPROM for the Z8603 and
a.2732 EPROM for the Z8613 device.

active

lACK is driven High in response to sn
interrupt during the interrupt mschine cycle.

11)5.

Instruction Sync (output,

Thia strobe output is forced Low during the internal clock period preceding an opcode fetch.

DEYEUPMENT DEVICE (Z8612)

Progr_ Me.ory Data Strobe (output, active

t4)S is Low during sn instruction fetch

Pin mnemonics and descriptions. are the same as
those for the Z8601/11 microcomputer (Chapter 6).
Descriptions ,ror the additional (24-pin socket)
memory interface lines are the same as those given
for the development devices above.

423

Pin Descriptions-and Functinns

+5V
TIMIN, {
AND
CONTROL.

GND
XTAL1

}

CLOCK

PORTO
(NIBBLE
PROGRAMMABLE)
1/0 OR Aa-AIS

PORT 2
(BIT PROGRAMMABLE)

P10
P11

PORT 1
(BYTE
PROGRAMMABLE)
1/0 OR ADo-AD7

P12
P13
P14

Z8812

PORT 3
SERIAL AND PARALLEL •
1/0 CONTROL

P1s
P1&
P17

Do
01

PROGRAM
. MEMORY
DATA
INPUTS

D2
D3
D4
Ds
D&

PROGRAM MEMORY
ADDRESS OUTPUTS

D7
INTERRUPT ACKNOWLEDGE

lACK

MEMORY DATA STROBE

MDS

INSTRUCTION SYNC

SYNC

SYSTEM CLOCK

SCLK

Figure A-1.

424

All

Z8612 Pin Functions

Vee

84

P38

XTAL2

2

63

P3,

XTAL1

3

82

P27

P37

4

81

P2i1

P3g

5

80

P2s

RESET

8'

59

P2.4

RJW

7

58

P23

D1

8

57

P2z

AS

9

56

P2,

P3S

10

55

P20

P3z

11

54

P33

POo

12

53

P3.

PO,

13

52

P17

POz

14

51

P18

P03

15

'50

P1s

PO.

16

49

P1.

GNO

17

48

P13

POs

18

47

P1z

PO.

19

46

P1,
P10

Z8812

P07

20

45

lACK

21

44

07

SYNC

22

43

08

SCLK

23

42

Os

MOS

24

41

04

00

25

40

Ao

0,

26

39

A,

Oz

27

38

AZ

03

28

37

A3

A"

As
As

29

A4

30

As

31

As

32

A7

425

B

7 .. 1",.

Zilog

426

Appendix B
Conlrol Begislen
Registers

R244 TO
CounterlTlmer 0 Register
(F4H; Read/Write)

8240 SIO
Serial 1/0 Register
(FOH; Read/Write)
I~I~I~I~I~I~I~I~I
L-I_ _ SERIAL DATA (0, _ Lsa)

NOT T.",
USI:OMODES
'" 00

~~ g~~ ~ ~~
INTERNAL CLOCK OUT", 11

To INITIAL VALUE (WHEN WRlnEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)

82U TMR
Timer Mode Register
(FIH; Read/Write)

R245PREO
Preacaler 0 Register
(F5H; Write Only)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~!~I~!~I

j

llli~o

~

- NO
FUNCTION
1 '"
LOAD
To

0

1

T

MODES
EXTERNAL CLOCK IN~aT .. 00
GATE INPUT ... 01
(NON.R~~~:~:~~:~~) = 10

0
1
0
1

=
=
=

=
=
=

DISABLE To COUNT

ENABLE To COUNT

~L

COUNTMODE
o '" To SINGLE·PASS
1 '" To MODULO·N
RESERVED

NO FUNCTION
LOAD T1
DISABLE T1 COUNT
ENABLE T, COUNT

PRES CALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

TRIGGER INPUT = 11
(RETRIBGERABLE)

R242 TI
Counter Timer 1 Register
(F2H; Read/Write)

R246 P2M
Port 2 Mode Register
(F~; Write Only)
I~I~I~I~I~I~I~I~I

,I

T, INITIAL VALUE (WHEN WRITTEN)
I...----(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)

R243 PREI
Prescaler 1 Register
(F3H; Write Only)

R247 P3M
Port 3 Mode Register
(F7H ; Write Only)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

~L
.

COUNTMODE
o = T, SINGlE·PASS
1 = T 1 MODULO·N

CLOCK SOURCE
1 = T1 INTERNAL
== T, EXTERNAL TIMING INPUT

o

(TIN) MODE

PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

E~

O PORT; PULL·UPSOPEN DRAIN

1 PORT 2 PULL·UPS ACTIVE
RESERVED

o P32 " INPUT
P3S ". OUTPUT
1 P32 = aAVOIRDYO P35 '" RDYQJDlVli

o 0 P33 = INPUT

P34 = OUTPUT

~~

jP33'= INPUT
P34 =! D1i
1 1 P33 = DAV1fRDY1 P34 = RDY11DAY1

L-_ _ _ _ _ _ ~

~~~ ~ ~;~~~~

=: : ~~~~~VfUT)

I...-------~~~ ~ ~N~~lLIN ~:~ ~ ~~~~ULTOUT
L-_ _ _ _ _ _~-~ ~:=:j~ g~F

427

Control Registers

Registers

R252 FLAGS
Flag Register

R248 POIM
Port 0 and I Mode Register

(Continued)

(FCH; ReacI/Write)

(F8H ; Write Only)

I~I~I~I~I~I~I~I~I
po,-po,

MODE:]
'~~
~
L po,-po, MODE

OUTPUT;; 00

,

H~~
'

LUSER FLAG F1
LUSER FLAG F2

00 '" OUTPUT

INPUT", 01

01 "" INPUT

A12-A'5 = 1X

~x

'

EXTERNAL MEMORY TIMING
NORMAL = 0

'"

Aa-A11

" STACK SEL.ECTION
0 = EXTERNAL

EXTENDED '" 1

1 '" INTERNAL
"

'

P1 0·P1 r MODE
00 = BYTE OUTPUT
01 = BYTE INPUT

10 = ADo·ACr

'

HALF CARRY FLAG

DECIMAL A,DJUST FLAG

OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
CARRY FLAG

,

11 "" HIGH.IMPEDANCE ADo-ACT,

AS, OS, RM, Aa-A11. A12-A15
IF SELECTED

R253 RP
Register Point9r

R249lPR
Interrupt Priority Register
(F~; Write Only)

, (FDH; Read/Write)

I I III ,~""""-. . . "

I~I~I~I~I~I~I~I~I

"."•• :J

RESERVED '" 000
C > A > B '" 001
A>B>C=010
A> C > B = 011
B > C > A ::: 100
c > B > A '" 101
B > A > C '" 110
RESERVEO
111

IRQ3, IRQS PRIORITY (GROUP A)
O:::IAQ5>IRQ3
,
1 = IR03 > IRQS

IROO, IRQ2 PRIORITY (GROUP B)
o '" IRQ2 > IROO
1
IROO > IR02

=

{::~

LDON'TCARE

=

IR01, IR04 PRIORITY (GROUP C)
o = IRQ1 > IR04
1 '" IR04 > IR01

"-

R250 IRQ
Interrupt Request Register

R254 SPH
Stack Pointer

(FAH ; ReacI/Write)

(FEH; ReacI/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I
RESERVED

c==

T

IROO
IR01
IR02
IRQ3
IRQ<

lAOS

P3:! INPUT (Do "" IROO)
P3:3INPUT
P311NPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T,

R251 1MB
Interrupt Mask Register

R255 SPL
Stack POinter

(FBH ; ReacI/Write)

(FFH; ReacI/Write)

I~I~I~I~I~J~I~I~I

I~I~I~I~I~I~I~I~I
"II

c==

1 ENABLES IROO·IROS
(Do = IROO)

' - - - - - - - RESERVED
' - - - - - - - - - - 1 ENABLES INTERRUPTS

428

REGISTER
POINTER

IL_ _ _ _ ~~~~~s~~~~:~R

LOWER

c

429

Lower Nibble (Hex)

Opcode
Map

o
o

e"

6

G

~

:9
:z:
Ii

2

'"'"
9

A

C

D

E

F

Instruction

D

6,5

6,5

6,5

10,5

10,5

10,5

10,5

6,5

6,5

12110,5

12110,0

6,5

12110,0

6,5

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DINZ

IR

LD

IP

INC

Il,H2

I2,Bl

n,RA

cc,BA

Il,IM

cc,DA

fl

R:

IR:

I1,12

Il,112

H2,Hl

lR2,R:

R:,IM

IR:,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR:,IM

R:

IR:

[1,[2

fl,IrZ

H2,Bl

IR2,R:

R:,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR:,IM

R:

IR:

[1,l2

Il,112

H2,Hl

lR2,R:

R:,IM

8,0

6,1

6,5

6,5

10,5

10,5

10,5

10,5

IP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR:

1M

[1,I2

rl,lrz

Hz,Bl

IRz,Hl

R:,IM

IR:,IM

8,5

8,5

6,5

6,5

10,5

I(),5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR
IR:,IM

R:

IRi

II, [2

[I,IIZ

H2,Hl

IR2,R:

R:,IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

pOP

POP

AND

AND

AND

AND

AND

AND
IR:,IM

R:

IR:

II, [2

II, lIZ

H2,Hl

IR2,R:

R:,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R:

IR:

[I, [2

[1,

Ir Z

Hz,Hl

IHz,Hl

R:,IM

IR:,IM

10112, I 12114, I

6,5

6,5

10,5

10,5

10,5

10,5

PUSH PUSH

TM

TM

TM

TM

TM

TM

H2,BI

IH2,Hl

R:,IM

IR:,IM

R2

IR2

n,I2

r},Ir2

10,5

10,5

12,0

18,0

LDE

LDEI

RR:

IR:

Il,Iuz

Ifl,Irrz

6,5

6,5

12,0

18,0

RL

RL

LDE

LDEI

R:

IR:

I2, hII

lrz,lni

10,5

10,5

6,5

6,5

[NCW [NCW
IR:

10,5

10,5

CP

CP

CP

CP

IH2,Hl

R:,IM

lR:,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R:

IR:

[1,[2

Il,112

Hz,Hl

IR2,R:

R:,IM

IR:,IM

6,5

6,5

12,0

18,0

10,5

RRC

RRC

LDC

LDCI

LD

R:

IR:

Il,Irrz

hI,Irrz

-

6,5

6,5

12,0

18,0

SRA

LDC

LDCI CALL"

20,0

R:

lR:

6,5

6,5

6,5

10,5

RR

RR

LD

LD

R:

IR:

Il,Iu

Hz,Hl

8,5

8,5

6,5

10,5

LD

LD

lIl,[2

H2,IRI

20,0

10,5

CALL

LD

DA

[2, x, Rl

10,5

10,5

10,5

LD

LD

LD

IHz,HI

R:,IM

IR:,IM

IRRI

.....

14,0

RET

16,0

IRET

6,5

Rz

II, X,

SRA

.;

-

10,5

R2,Rl

'V

-

EI
10,5

CLR

"

-

6, I

CP

IR:

-

DI

II/In

SWAP SWAP

-

-

CP

lrn hz, lIn

-

4

6,0

V"

"I

.....

Pipeline
Cycles

Legend:
R = 8-Bit Address
r

Upper
Opcode- A
Nibble
First
Operand

or

[1

= Dst Address

[2

= Src Address

Sequence:
Operand

*2-byte instruction; fetch cycle appears as a 3-byte instruction

430

= 4~ Bit Address

Rz or

Rl

Mnemonic

Second

CCF
NOP

Opcode
Nibble

t

SCF
6,5

3.

Cycles

RCF
6,5

Lower

Execution

-

6, I

II, [2

[2,

F

E

DEC

R:

Bytes per

C

6,5

RR:

B

B

DEC

DECW DECW

::>

A

Opcode, First Operand, Second Operand

Note: The blank areas are not defined.

~ ZiIm

Product Specification

August 1988

Super8™ MCV ROMless,
ROM, and Protot,ping Device
with EPROM Interface
Z8800,Z8801,Z8820,Z8822

FEATURES
•

Improved Z8~ instruction set includes multiply and
divide instructions, Boolean and BCD operations.

• Additional
instructions
support
languages, such as "Forth."
•

threaded-code

Up to 32 bit-programmable and 8 byte-programmable I/O
lines, with 2 handshake channels.

•

Interrupt structure supports:
o 27 interrupt sources
o 16 interrupt vectors (2 reserved for future versions)
o 8 interrupt levels
o Servicing in 600 nsec. (1 level only)

•

Full-duplex UARTwith special features.

325 byte registers, including 272 general-purpose
registers, and 53 mode and control registers.

• Addressing of up to 128K bytes of memory.
• Two register pointers allow use of short and fast
instructions to access register groups within 600 nsec.
•

•

• On-Chip oscillator.
• 20 MHz clock.

Direct Memory Access controller (DMA).

• 8K byte ROM for Z8820

• Two 16-bit counter/timers.

GENERAL DESCRIPTION
The Zilog SuperB single-chip MCU can be used for
development and production. It can be used as 110- or
memory-intensive computers, or configured to address
external memory while still supporting many 110 lines.

NC

,.

9

8

7

6

5

4

3

2

1

~

67

~

~

~

~

~

61

The Super8 features a full-duplex universal asynchronous
receiver /transmitter (UART) with on-Chip baud rate
generator, two programmable counter/timers, a direct
memory access (DMA) controller, and an on-Chip oscillator.
The Super8 is also available as a 48-pin and 68-pin ROMless
microcomputer with four byte-wide 110 ports plus a
byte-wide address/data bus. Additional address bits can be
configured, up to a totalo! 16.

6.

NC

Vee
ROMI.55

11

5.

Ne

12

58

Vee

""

13

57

po,

14

56

po,

15

55

p",

P2,

16

54

P3,

Vee

17

53

AS

52

OS

P17

P06

P24

P07

...
P1,

~ ~ ~ ~ f ~

f

~ ~

f f

0

P16

vee

Vee

,.

51

P4s

XTAL2

2.

5.

P.,

XTAL1

21

4.

GND

P"

22

48

GND

vee

P4s

23

47

P.,

GND

AS

P4s

24

.6

P4,

XTAl.2

os

P47

25

45

R/W

NC

26

44

NC

GND

18

SUPER8

~~~~~~~~~~~~~~~/~

Figura 18_ Pin AsSignments - 68-pin PLCC

P34

P25

P3S

Z8801

XTALI

GND

P47

RIW

P22

'"

~

'"
~

~ ~

S!

~

0

~

~ ~

...~

.

~

431

P"

PO,

P"

PO,

P"

PO,

P"

PO,

P"

PO.

p'.

PO.

P"

PO.

P'7

P07

P2.

P3.

P2S

P3s

+SV

AS

XTAL2

os

XTAL1

P4.

P4.

P4,

P4.

GNO

P4.

P4,

P47

P4,

P2,

RiW

P3,

RESET

P3,

P3.

P2,

P37

P2,

P27

P2,

P2,

P3,

P3.

SUPERB

Figure 2. Pin Functions

Figure 1b. Pin Assignments - 48·pin DIP

+5
A12

+5

A7

A13

A.

A,

As

A,

A4

Al1

A,

DE

A,

AlO

A,

CE

A,

07

0,

O.

Ao..-

+5

0,

Os

0,

D.

GNO

D,

Figure 3. Pin Assignments-28-Pin Piggyback Socket

DATA

PROTOPACK
EPROM
SOCKET

ADDRESS

Figure 4. Pin Functions-28-Pin Piggyback Socket

Protopack

This part functions as an emulator for the basic
microcomputer. It uses the same package and pin-out as
the basic microcomputer but also has a 2S-pin "piggy back"
socket on the top into which a ROM or EPROM can be
installed. The socket is designed to accept a type 2764
EPROM.
This package permits the protopack to be used in prototype
and final PC boards while still permitting user program

432

development. When a final program is developed, it can be
mask-programmed into the production microcomputer
device, directly replacing the emulator. The protopack part
is also useful in situations where the cost of maskprogramming is prohibitive or where program flexibility is·
desired.

ADDRESS
DATA

..

.

I/O
(BIT PROGRAMMABLE)
OR CONTROL

ADDRESS/DATA OR I/O
(BYTE PROGRAMMABLE)

~--------~ ~--------~
Z-BUS WHEN USED'AS
ADDRESS/DATA BUS

Figure 5. Functional Block Diagram

ARCHITECTURE
The Super8 architecture includes 325 byte-wide internal
registers. 272 of these are available for general purpose
use; the remaining 53 provide control and mode functions.
The instruction set is specially designed to deal with this
large register set. It includes a full complement of 8-bit
arithmetic and logical operations, including multiply and
divide instructions and provisions for BCD operations.
Addresses and counters can be incremented and
. decremented as 16-bit quantities. Rotate, shift, and bit
manipulation instructions are provided. Three new
instructions support threaded-code languages.

The UART is a full-function mUltipurpose asynchronous
serial channel with many premium features.
The 16-bit counters can operate independently or be
cascaded to perform 32-bit counting and timing operations.
The DMA controller handles transfers to and frolT) the
register file or memory. DMA can use the UART or one of two
ports with handshake capability.
The architecture appears in the block diagram (Figure 5) .

PIN DESCRIPTIONS
The Super8 connects to external devices via the following
TIL-compatible pins:

AS. Address Strobe (output, active Low). AS is pulsed
Low once at the beginning of each machine cycle. The
rising edge indicates that addresses Riw and OM, when
used, are valid.
OS.Data Strobe (output, active Low). OS provides timing
for data movement between the address/data bus and
external memory. During write cycles, data output is valid at·
the leading edge of OS. During read cycles, data input
must be valid prior to the trailing edge of OS.

POO·P07. P1o·P17. P20·P27. P30·P37. p40·P47' Port 110
Lines (inpuUoutput). These 40 lines are divided into five 8-bit

I/O ports that can be configured under program control for
I/O or external memory interface.
In the ROM less devices, Port.1 is dedicated as a
multiplexed address/data port, and Port 0 pins can be
assigned as additional address lines; Port 0 non-address
pins may be ass'igned as I/O. In the ROM and protopack,
Port 1 can be assigned as input or output, and Port 0 can be
assigned as input or output on a bit by bit basis.

433

it is deactivated, the SuperB begins processing at address
0020H·

Ports 2 and 3 can be assigned on a bit-for-bit basis as
general I/O or interrupt lines. They can also be used as
special-purpose I/O lines to support the UART,
counter/timers, or handshake channels.

ROMless. (input, active High). This input controls the
operation mode of a 6B-pin SuperB. When connected to Vee,
the part will function as a ROM less ZBBOO. When connected
to GND, the part will function as a ZBB20 ROM part.

Port 4 is used for general I/O.
During reset, all port pins are configured as inputs (high
impedance) except for Port 1 and Port 0 in the ROM less
devices. In these, Port 1 is configured as a multiplexed
address/data bus, and Port 0 pins POO-P04 are configured
as address out, while pins POS-P07 are configured as inputs.

R/W. ReadNVrite (output). R/W determines the direction of
data transfer for external memory transactions. It is Low
when writing to program memory or data memory, and High
for everything else.
\

RESET. Reset (input, active Low). Reset initializes and starts
the SuperB. When it is activated, it halts all processing; when'

'XTAL 1, XTAL2. (Crystal oscillator input.) These pins
connect a parallel resonant crystal or an external clock
source to the on-board clock oscillator and buffer.

REGISTERS
The SuperB contains a 256-byte internal register space.
However, by using the upper 64 bytes of the register space
more than once, a total of 325 registers are available.

The uppermost 32 register direct registers (EO to FF) are
further divided into two banks (0 and 1), selected by the
Bank Select bit in the Flag register. When a Register Direct
command accesses a register between EO and FF, it looks at
the Bank Select bit in the Flag register to select one of the
banks.
.

Registers from 00 to BF are used only once. They can be
accessed by any register command. Register addresses CO
to FF contain two separate sets of 64 registers. One set,
called control registers, can only be accessed'by register
direct commands. The other set can only be addressed by
register indirect, indexed, st.ack, and DMA commands.

The register space is shown in Figure 6.

SET ONE

I

SET TWO
FFH ....- - - - - - - . ,

I--r- BANK1
CONT:g~~:~I~TERS

..
(REGISTER ADDRESSING ONLY)

i-r- BANKO
I-

SYSTEM REGISTERS,
STACK, FLAGS, PORTS, ETC.
(REGISTER ADDRESSI~G ONLY)

DATA REGISTERS

(INDIRECT REGISTER, INDEXED,
STACK OR DMA
ACCESS ONlY)

WORKING REGISTERS
(WORKING REGISTER
ADDRESSING ONLY)
COH~

BFH

_______

DATA REGISTERS
(ALL ADDRESSING MODES)

OOH~

_______

Figure 6. SuperS Registers

434

BYTES

192
BYTES

~

~

256

r--------..,

Working Register Window
Control registers R214 and R215 are the register pointers,
RPO and RP1. They each define a moveable, 8-register
section of the register space. The registers within these
spaces are called working registers.
Working registers can be accessed using short 4-bit
addresses. The process, shown in section a of Figure 4,
works as follows:
•

The high-order bit of the 4-bit address selects one of the
two register pointers (0 selects RPO; 1 selects RP1).

• The five high-order bits in the register pointer select an
8-register (contiguous) slice of the register space.

The net effect is to concatenate the five bits from the register
pointer to the three bits from the address to form an 8-bit
address. As long as the address in the register pointer
remains unchanged, the three bits from the address will
always point to an address within the same eight registers.
The register pointers can be moved by changing the five
high bits in control registers R214 for RPO and R215 for RP1.
The working registers can also be accessed by using full
8-bit addressing. When an 8-bit logical address in the range
192 to 207 (CO to CF) is specified, the lower nibble is used
similarly to the 4-bit addressing described above. This is
shown in section b of Figure 7.

• The three low-order bits of the 4-bit address select one of
the eight registers in the slice.

IIIIIIII

I

APO (A214)

IIIIIIII

APl (A21S)

SELECTS

I

APO (A214)

RP1 (R21S)

RPO ORRP1

ADDRESS

SELECTS
RPODRRP1

QPCODE

ADDRESS

,.-----A-----,,~

~

I I I I I I I I I
4·81T ADDRESS PROVIDES 3 LOW-ORDER BITS

REGISTER POINTER PROVIDES
5 HIGH-ORDER BITS

REGISTER POINTER PROVIDES
5 HIGH-ORDER BITS

T-"~."'

----'---~

I I I I
8-BIT PHYSICAL ADDRESS

TOGETHER THEY CREATE
8-BIT REGISTER ADDRESS

a. 4-Bit Addressing

b. a-Bit Addressing
Figure 7. Working Register Window

435

Since any direct access to logical addresses 192 to 207
involves the register pointers, the physical registers 192 to
207 can be accessed only when selected by a register
pointer. After a reset, RPO points to R192 and RP1 points to
R200.

Register List
Table 1 lists the SuperB registers. For more details, see
Figure B.

Table 1. Super-B Registers
Address
Decimal

Hexadecimal

Mnemonic

General-Purpose Registers
000-192.
OO-BF
192·207
CO·CF
192-255
CO-FF
Mode and Control Registers
208
DO
209
01
210
02
211
03
212
04
213
05
214
06
215
07
216
08
'217
09
218
DA
219
DB
220
DC
221
DO
222
DE
224
EO

436

225

E1

226

E2

227

E3

228

E4

229

E5

235
236
237
239
240

EB
EC
EF
FO

241

F1

244
245
246
247
248

F4
F5
F6
F7
F8

ED

BankO
Bank 1
BankO
~ank 1
BankO
Bank 1
BankO
Bank 1
BankO
Bank 1
BankO
Bank 1
BankO
BankO
BankO
BankO
BankO
Bank 1
BankO
Bank 1
BankO
BankO
BankO
BankO
BankO
Bank 1

Function

General purpose (all address modes)
Working register (direct only)
General purpose (indirect only)

PO
P1
P2
P3
P4
FLAGS
RPO
RP1
SPH
SPl
IPH
IPl
IRQ
IMR
SYM
COCT
COM
C1CT
C1M
COCH
CTCH
COCl
CTCl
C1CH
cnCH
C1Cl
cnCl
UTC
URC
UIE
UIO
POM
DCH
PM
DCl
HOC
H1C
P4D
P40D
P2AM
UBGH

Port 0 1/0 bits
Port 1 (1/0 only)
Port 2
Port 3
Port 4
System Flags Register
Register Pointer 0
Register Pointer 1
Stack Pointer High By1e
Stack Pointer low Byte
Instruction Pointer High Byte
Instruction Pointer low Byte
Interrupt Request
Interrupt Mask Register
System Mode
CTR 0 Control
CTRO Mode
CTR 1 Control
CTR 1 Mode
CTR 0 Capture Register, bits 8-15
CTR 0 Timer Constant, bits 8-15
CTR 0 Capture Register, bits 0-7
CTR 0 Time Constant, bits 0-7
CTR 1 Capture Register, bits 8-15
CTR 1 Time Constant, bits 8-15
CTR 1 Capture Register, bits 0-7
CTR 1 Time Constant, bits 0-7
UART Transmit Control
UART Receive Control
UART Interrupt Enable
UARTData
PortO Mode
DMA Count. bits 8-15
Port Mode Register
DMA Count, bits 0-7
Handshake Channel 0 Control
Handshake Channel 1 Control
Port 4 Direction
Port 4 Open Drain
Port 2/3 A Mode
UART Baud Rate Generator, bits 8-15

Table 1 . Super-a Registers (Conti nued)
Address
Decimal

Hexadecimal

Mode and Control Registers (Continued)
F9
Bank 0
249
Bank 1
FA
BankO
250
Bank 1
251
FB
BankO
Bank 1
252
BankO
FC
253
FD
BankO
BankO
254
FE
Bank 1
BankO
FF
255
Bank 1

Mnemonic

Function

P2BM
UBGL
P2CM
UMA
P2DM
UMB
P2AIP
P2BIP
EMT
WUMCH
IPR
WUMSK

Port 2/3 B Mode
UART Baud Rate Generator. bits o· 7
Port 2/3 C Mode
UART Mode A
Port 2/3 D Mode
UARTModeB
Port 2/3 A Interrupt Pending
Port 2/3 B Interrupt Pending
External Memory Timing
Wakeup Match Register
Interrupt Priority Register
Wakeup Mask Register

MODE AND CONTROL REGISTERS
R218 (DA) IPH
INSTRUCTION POINTER HIGH

FLAGgJJ~

ZEROFLAG~

CARRY

'
llli

R213 (05) FLAGS

SYSTEM FLAGS REGISTER

.

SIGN FLAG

L

L BANK ADDRESS

L....----HIGH BYTE (IP8·IP15)

FAST INTERRUPT STATUS

HALF· CARRY FLAG
DECIMAL ADJUST

OVERFLOW FLAG

R219 (DB) IPL
INSTRUCTION POINTER LOW

107 1 061 051 041 0,1 02

I I I
0,

00

R214 (06) RPo
REGISTER POINTER 0

(RP3-RP7)~

L....----LOW BYTE (IPO·IP7)

LNorUSED

R220 (DC) IRQ
INTERRUPT REQUEST (READ ONLY)

I~I~I~I~I~I~J~I~I
R215 (07) AP1
REGISTER POINTER 1

I

071 061 05

I

041 031 021 0,

I I
Do

LNorUSED

~I

LEVEL 7 J { W
lEVEL 6

Uhl~LLEVELO
LEVEL 1

lEVEL 5

lEVEL 2

LEVEL 4

LEVEL 3

R216 (08) SPH
STACK POINTER

R221 (00) IMR
INTERRUPT MASK

1071 0 6 1 Os
L....----HIGH BYTE (SP8·SP15)

R217 (09) SPL
STACK POINTER

L...._ _ _ _

I041 031 021 0, IDo I

LEVEL7{W~
LEVEL6~

l

Uhl
LLEVELO
LLEVEL1

lEVEL,S

LEVEL 2

LEVEL 4

lEVEL 3

lOW BYTE (SPO-SP7)

Figure 8. Mode and Control Registers

437

MODE AND CONTROL REGISTERS (Continued)
R222 (DE) SYM
SYSTEM MODE

TIL

I~I~I~I~I~I~I~I~I

---r

NOT USED

~

1 = GLOBAL INTERRUPT ENABLE

= FAST INTERRUPT ENABLE

1

FAST INTERRUPT SELECT
000 LEVEL 0

001 LEVEL 1
010 LEVEL2
011 LEVEL 3
100

LEVEL 4

101 LEVEL 5
110 LEVEL 6
111 LEVEL7

R224, BANK 0 (EO) COCT
COUNTER 0 CONTROL

JJ~

o = SINGLE CYCLE
I
1 CONTINUOUS ~

=

o

= COUNT DOWN
1 = COU~TUP

~
I

L

L

1 = LOAD COUNTER

= ENABLE COUNTER

1

READ 1 = END OF COUNT
RESET END OF COUNT
WRITE 1

=

1 = ZERO COUNT INTERRUPT ENABLE

1

= SOFTWARE CAPTURE

1 = SOFTWARE TRIGGER

R224 BANK 1 (EO) COM
COUNTER 0 MODE

I L ~:t:.="."'

INPUT PIN ASSIGNMENTS:

07 06 05 04 P27

P2,

o
o

110

o
o
o
o
o
o

I/O
I/O
GATE
GATE
I/O
TRIGGER
GATE
GATE/
TRIGGER
CO OUTPUT
CO OUTPUT
CO OUTPUT
CO OUTPUT
CO OUTPUT

EDGE OF P2Z
10 = BI·VALUE MODE
11 = CAPTURE ON BOTH

TRIGGER
I/O
TRIGGER
CO INPUT
CO INPUT
CO INPUT

EDGESOFP2,
0= EXTERNAL
UP/DOWN CONTROL P27
1 = PROGRAMMED
UP/DOWN CONTROL

Co INPUT
I/O
TRIGGER
GATE
GATE/TRIGGER
CO INPUT

1 = ENABLE RETRIGGER

~- UNDEFINED~­

- - UNDEFINED~- CASCADE COUNTEI'IS -

R225 BANK 0 (EI) CICT
COUNTER 1 CONTROL

J~
I

o = SINGLE CYCLE
1 = CONTINUOUS ~

o = COUNT DOWN
1

=COUNT uP

1 = LOAD COUNTER

,

I

~
L

L

1 = ENABLE COUNTER

READ 1 = END OF COUNT
WRITE 1 RESET END OF COUNT

=

~

= ZERO COUNT INTERRUPT ENABLE

1

= SOFTWARE CAPTURE

1 = SOFTWARE TRIGGER

Figure 8. Mode and Control Registers (Continued)

438

MODE AND CONTROL REGISTERS (Continued)
R225BANK1 (E1)C1M
COUNTER 1 MODE

L

I~I~I~I~I~I~I~I~I
~

INPUT PIN ASSIGNMENTS:

07 08 Os 04 P37

P3.

~0~0~0~0~1~/0~----~1I=0~------

L

----.J

o 0 0 1 1/0
TRIGGER
0010GATE
110
o 0 1 1 GATE
TRIGGER
o 1 0 0 110
CO INPUT
1 0 1 TRIGGER
INPUT
o 1 1 0 GATE
CO INPUT
0111GATEI
TRIGGER
CO INPUT
CO OUTPUT 1/0
OUTPUT TRIGGER
OUTPUT GATE
OUTPUT GATEITRIGGER
OUTPUT COINPUT
- - UNOEFINED-- - UNDEFINED-- - UNDEFINED--

o

co

CAPTURE MODE:
00 = NO CAPTURE
01 = CAPTURE ON RISING
EDGEOFP37 .
10 = B~VAWE MODE
11 • CAPTURE ON BOTH
EDGES OF P37
0= EXTERNAL
UP/DOWN CONTROL P37
1 = PROGRAMMED
UPIDOWN CONTROL

co
co
co
co

1 = ENABLE RETRIGGER

R229 BANK 0 (ES) C1 CL
COUNTER 1 CAPTURE

R226 BANK 0 (E2) COCH
COUNTER 0 CAPTURE

' - - - - - - - - - - - - LOW BYTE (C1 Co-C1 C7)

' - - - - - - - - - - - HIGH BYTE (COCa-Coc,15)

R226 BANK 1 (E2) COTCH
COUNTER 0 TIME CONSTANT

R229 BANK 1 (E5) C1 TCL
COUNTER 1 TIME CONSTANT

'------------ LOW BYTE (C1TCo-C1TC7)

' - - - - - - - - - - - HIGH BYTE (COTC,-COTC15)

R227 BANK 0 (Ea) COCL
COUNTER 0 CAPTURE

UART TRANSMIT CONTROL

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

'-1-----

R235 BANK 0 (EB) UTC

LOW BYTE (COCo-COC7)

J..

TRANSMITDATASELECT:1j
= OUTPUT P3, DATA

o

1

~~L

= OUTPUT TRANSMIT DATA
1 = SEND BREAK

R227 BANK 1 (E3) COTCL
COUNTER 0 TIME CONSTANT

'-1-----------

1 = ZERO COUNT'

STOP BITS:

o • 1 STOP BIT

I~I~I~I~I~I~I~I~I

1 = TRANSMITDMAENABLE

. 1 = TRANSMIT BUFFER EMPTY

1 • TRANSMIT ENABLE

1 = 2 STOP BITS
1 = WAKE-UP ENABLE -----------'
LOW BYTE (COTCo-COTC7)

R228 BANK 0 (E4) C1CH
COUNTER 1 CAPTURE

R236 BANK 0 (EC) URI:

UART RECEIVE CONT.RDL

1

=WAKE_UPDETECT~~
=:..J

1 = CONTROL CHARACTER DETECT
1 = BREAK DETECT
R22808ANK 1 (E4) C1 TCH
COUNTER 1 TIME CONSTANT

1

= FRAMING ERROR

~

- ~

.

= RECEIVE CHARACTER
AVAILABLE
1 = RECEIVE ENABLE
1

1 = PARITY ERROR
1 .. OVERRUN ERROR

1~1~1~1~1~I~t~I~1

1'------------

HIGH BYTE (C1TC,-C1TC15)

Figure 8. Mode and Control Registers (Continued)

439

MODE AND CONTROL REGISTERS (Continued)
R2378ANK 0 (ED) UIE
UART INTERRUPT ENABLE

1

m

WAKE.OP

INTERRUPTENABLE~
J I

1 = CONTROL CHARACTER
INTERRUPT ENABLE
, 1 • BREAK INTERRUPT ENABLE

~

~~
L

.

'

1 = RECEIVE CHARACTER AVAILABLE
INTERRUPT ENABLE
1 = RECEIVE DMA ENABLE
1 = TRANSMIT INTERRUPT ENABLE
1 • ZERO COUNT INTERRUPT ENABLE

1 = RECEIVE ERROR INTERRUPT
ENABLE

R239 BANK 0 (EF) UIO
UART TRANSMIT OATA (WRITE)
UART RECEIVE OATA (READ)

R244 BANK 0 (F4) HOC
HANDSHA~E 0 CONTROL (WRITE ONLY)

I~I~I~I~I~I~I~I~I
' - - - - - - OATA(Do = LSB)

DESKEW COUNTER
(RANGE 1·16)

' 1- .L

~

---=-::J

1 • HANDSHAKE ENABLE

L

PORTSELEC'f.
.
1 = PORT1:0 = PORT 4
DMAENABLE:

1 == ENABLED

Ra'lO BANK 0 (FO) POM
PORTO MODE

O. DISABLED

I~I~I~I~I~I~I~I~I

MODE:
1 = FULLY INTERLOCKED
0= STROIlilD

PD7MODE~~
~I
Po.,MODE~
_

R245 BANK 0 (F5) HIC
HANDSHAKE 1 CONTROL (WRITE ONLY)

LPOOMODE
LP01MODE

PO, M D D E '

Po. MODE

po. MODE

po. MODE

I~I~I~I~I~I~I~I~I
DESKEW COUNTER
(RANGE 1·16)

o = I/Oj 1 = ADDRESS

II.L.--_.

---=-::J

NOT USED

MODE:

1 = FULLY INTERLOCKED
0= STROBED

R2'1O BANK 1 (FO) DCH
DMACOUNT R246 BANK 0 (F6) P4D
PORT 4 DIRECTION
' - - - - - - HIGH BYTE (DC,·DC15)

'------P4o-P47UO DIRECTION
o = OUTPUll 1 = INPUT

R241 BANK 0 (Fl) PM
PORT MODE (WRITE ONLY)

R247 BANK 0 (F7) P40D
PORT 4 OPEN-ORAIN

I~I~I~I~I~I~I~I~I
,

NOTUSED~ llli~

PORT 1 MODE
00 OUTPUT
01 INPUT "
IX ADDRESS/DATA
' .

PORTODIRECnON
0;; OUTPUT
1 = INPUT
OPEN.DRAIN PORT 0
0 = PUSH·PULL
1 .·OPEN·DRAIN
OPEN I1RAIN PORT 1
0 = PUSH-PULL

1

z

LI-----~~~:;~-rt~N

OPEN.DRAIN

R248 BANK 0 (FB) P2AM
PORT 2/3 A MODE (WRITE ONLY)

OPEN·DRAIN

ENABLE DM P35
0= DISABLE
1 == ENABLE
R241 BANK 1 (Fl) DCL
DMACOUNT

I~I~I~I~I~I~I~I~I
1..._ _ _ _ _

LOW BYTE (DC..DC7)

00
01
10
11

INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH·PULL
OUTPUT, OPEN-DRAIN

Figure 8. Mode and COntrol Registers (Continued)

440

MODE AND CONTROL REGISTERS (Continued)
R250 BANK 0 (FAi P2CM
PORT 213 C MODE (WRITE ONLY)

R248 BANK 1 (F8) UBGH
UART BAUD-RATE GENERATOR

I~I~I~I~I~I~I~I~I
1
....- - - - - H I G H BYTE (UBGe·uao,.)

00 INPUT
01 INPUT,INTERRUPT ENABLED
10 OUTPUT, PUSH-PULL
11 OUTPUT,OPEN·DRAIN

A248 BANK 0 (FB) P2BM
PORT 213 B MODE (WRITE ONLY)

I~I~I~I~I~I~I~I~I
P33MODE=oJ
P30 MODE

I

~P22MODE
.

'
llli

R250 BANK 1 (FA) UMA
UARTMODEA

P23 MODE

00 I U
01 INPUT, INTERRUPT ENABLED
10 OUTPUT, PUSH-PULL

CLOCKRATE:J
D7~

11 OUTPUT, OPEN.D.RAIN

0"0 =X1
o 1 _ X16
1 0
1 1

Rr.41 BANK 1 (FI) UBOL
UART BAUD-RATE GENERATOR

=X32

_ X64

L

LTRANSMIT~AKE.UPVAWE
RECEIVE WAKE·UP VAWE ,
1 _ EVEN PARITY
1 _ PARITY ENABLE

I~I~I~I~I~I~I~I~I

BITS PER CHARACTER

0504

"""0""0 - 5 BITS
o

1
...._____ LOW BYTE (UBG..UBGt)

1

=681TS

1 0 _7BITS
1 1 _BBITS

R251 BANK 0 (FB) P20M
PORT 213 0 MODE (WRITE ONLY)

I~I~I~I~I~I~I~I~I

I ,-

P37 MODE =oJ

L

P3. MODE

P2e MODE
P27 MODE

00 INPUT.
01

INPUT. INTERRUPT ENABLED

10 OUTPUT, PUSH-PULL
11 OUTPUT, OPEN·DRAlN

'
E

A251 BANK 1 (FB) UMB
UARTMODEB

CLOCK OUTPUT SELECT

~

0708

"00 =P21 DATA
o

_ SYSTEM CLOCK (XTAU2)

1
1 0

_ BAUD-AATE GENERATOR

1 1

OUTPUT
• TRANSMIT DATA CLOCK
1 _ AUTO-ECHO

L

L

1 - LODPBACKENABLE

1 _ BAUD.RATE GENERATOR ENABLE
BAUD·RATE GENERATOR SOURCE:

o = P20 (EXTERNAL)
1 = INTERNAL (XTAU4)

TRANSMIT CLOCK INPUT SELECT:
0-= P21

1 _ BAUD-AATE GENERATOR OUTPUT

RECEIVE CLOCK INPUT SELECT: _ _-'"_...l
0= P20

1 _ BAUD-RATE GENERATOR
.
OUTPUT

Figure 8. Mode and Control Registers (Continued)

441

MODE AND CONTROL REGISTERS (Continued)
R252 BANK 0 (FC) P2AIP
PORT 2/3 A INTERRUPT PENDING (READ ONLy)

R254 BANK 1 (FE) WUMCH
WAKE·UP MATCH REGISTER

~71~1~1~1~1~1~1~1

I~I~I~I~I~I~I~I~I
L . I_ _ _ _ _ _

THIS BYTE, MINUS MASKED BITS,
IS USED FOR WAKE·UP MATCH

R255 BANK O,{FF) IPR
INTERRUPT PRIORITY REGISTER

GROUP PRIORITY
R253 BANK 0 (FD),P2 BIP
PORT 2/3 B INTERRUPT PENDING (READ ONLY)

I

0704 D1

1
1
1
1

0
0
1
1

0

JL

GROUP A
0.IRQO>IRQ1
1:= IRQ1 >IRQO

"iiOO • UNDEFINED
o 0 1 .B>C>A
o 1 0 =A>B)lC
o 1 1 _B>A>C

, I~I~I~I~I~I~I,I~I

J

' - - - - GROUPB

o • IRQ2> (IRQ3,IRQ4)
1

=C>A>B

= (IRQ3,IRQ4) > IRQ2

SUBGROUPB
0.IRQ3>IRQ4
1.IRQ4>IRQ3

1 =C>B>A
0 =A>C>B
1 • UNDEFINED

GROUPC
o .IRQ5 >(IR08,IRQ7)
1 = (IRQ6,IRQ7) > IRQ5
SUBGRQUPC

o = IRQ6 > IAQ7
1 = IAQ7> IROe

R254 BANKO (FE) EMT
EXTERNAL MEMORY TIMING REGISTER

1",1

R255 BANK 1 (FF) WUMSK
WAKE·UP MASK REGISTER

~ I~t'r r~ :'!'~~

' - - - - - - THESE BITS CORRESPOND TO BITS
IN WAKE.UP MATCH REGISTER; Os
MASK CORRESPONDING MATCH BITS

1 _ DATA MEMORY

STACK SELEC'f.
o _ REGISTER FILE
1 • DATA MEMORY

,

DATA MEMORY AUTOMATIC WAITS
00 _ NO WAITS
01 = 1 WAIT
10 _ 2 WAITS
11 -3WAITS
' - - - - - - - PROGRAM MEMORY AUTOMATIC WAITS
00 _ NO WAITS
01 _ 1 WAIT
10 - 2 WAITS
11 _ 3 WAITS
' - - - - - - - - - SLOW MEMORY TIMING
0= DISABLED
1 _ ENABLED
' - - - - - - - - - - - EXTERNAL WAIT INPUT
o - P3. IS NORMAL 110
1 = P3. IS EXTERNAL WAIT INPUT

Figure 8. Mode and Control Registers (Continued)

1/0 PORTS

Port 1

The Super8 has 40 I/O lines arranged into five 8-bit ports.
These lines are all TTL-compatible, and can be configured
as inputs or outputs. Some can also be configured as
address/data lines.
Each port has an input register, an output register, and a
register address. Data coming into the port is stored in the
input register, and data to be written to a port is stored in the
output register. Reading a port's register address returns the
valqe in the input register; writing a port's register address
loads the value in the output register. If the port is configured
for an output, this value will appear on the external pins.
When the CPU reads the bits configured as outputs, the
data on the external pins is returned. Under normal output
Iqading, this has the same effect as reading the output
register, unless the bits are configured as open-drain
outputs.
The ports can be configured as shown in Table 2.
Table 2. Port Configuration
Port

Configuration Choices

a

Address outputs and/or general I/O
Multiplexed address/data(or I/O, only for ROM
and Proto pack)
Control I/O for UART, handshake channels, and
counter/timers; also general I/O and external
interrupts
General I/O

2and3

4

In the ROMless device, Port 1 is configured as a byte-wide
address/data port. It provides a byte-wide multiplexed
address/data path. Additional address lines can be added
by configuring Port O.
The ROM and Protopack Port 1 can be configured as above
or as an I/O port; it can be a byte-wide input, open-drain
output, or push-pull output. It can be placed under
handshake control or handshake channel O.

Ports 2 and 3
Ports 2 and 3 provide external control inputs and outputs for
the UART, handshake channels, and counter/timers. The
pin assignments appear in Table 3.
Bits not used for control I/O can be configured as
general-purpose I/O lines and/or external interrupt inputs.
Those bits configured for general I/O can be configured
individually for input or output. Those configured for output
can be individually configured for open-drain or push-pull
output.
All Port 2 and 3 input pins are Schmitt-triggered.
The port address for Port 2 is R21 0, and for Port 3 is R211.

Port 0

Port 0 can be configured as an I/O port or an output for
addressing external memory, or it can be divided and used as
both. The bits configured as I/O can be either all outputs or all
inputs; they cannot be mixed. If configured for outputs, they
can be push-pull or open-drain type.
Any bits configured for I/O can be accessed via R208. To write
to the port, specify R208 as the destination (dst) of an
instruction; to read the port, specify R208 as the source (src).
Port 0 bits configured as I/O can be placed under handshake
control of handshake channel 1.
Port 0 bits configured as address outputs cannot be accessed
via the register.

Table 3. Pin Assignments for Ports 2 and 3

Port 2
Bit Function

Port 3
Bit Function

a

a

2
3
4
5
6
7

UART receive clock
UART transmit clock
Reserved
Reserved
Handshake 0 input
Handshake a output
Counter a input
Counter a I/O

2
3
4
5
6
7

UART receive data
UART transmit data
Reserved
Reserved
Handshake 1 input/WAIT
Handshake 1 output/OM
Counter 1 input
Counter 1 I/O

Port 4
Port 4 can be configured as I/O only. Each bit ~an be
configured individually as input or output, with either
push-pull or open-drain outputs. All Port 4 inputs are
Schmitt-triggered.
Port 4 can be placed under handshake control of
handshake channel O. Its register address is R212.

In ROM less devices, initially the four lower bits are configured
as address eight through twelve:

443

UART

Receiver

The UART is a full-duplex asynchronous' channel. It
transmits and receives independently with 5 to a bits per
character, has options for even or odd bit parity, and a
wake-up feature.

The UART begins receive operation when Receive Enable
(URC, bit 0) is set High. After this, a Low on the receive input
pin for longer than half a bit time is interpreted as a start bit.
The UART samples the data on the input pin in the middle of
each clock cycle until a complete byte is assembled. This is
placed in the Receive Data register.

Data can be read into or out of the UART via R239, Bank O.
This single address is able to serve a full-duplex channel
because it contains two complete a-bit registers-one for
the transmitter and the other for the receiver.

Pins
The UART uses the following Port 2 and 3 pins:

Port/Pin

2/0
3/0
2/1
3/1

UART Function
Receive Clock
Receive Data
Transmit Clock
Transmit Data

Transmitter
When the UART's register address is specified as the
destination (dst) of an operation, the data is output on the
UABT, which automatically adds the start bit, the
programmed parity bit, and the programmed number of
stop bits. It can also add a wake-up bit if that option is
selected.

If the 1X clock mode is selected, external bit synchronization
must be provided, and the input data is sampled on the
rising edge of the clock.
For character lengths of less than eight bits, the UART
inserts ones into the unused bits, and, if parity is enabled,
the parity bit is not stripped. The data bits, extra ones, and
the parity bit are placed in the UART Data register (UIO).
While the UART is assembling a byte in its input shift register,
the CPU has time to service an interrupt and manipulate the
data character in UIO.
Once a complete character is assembled, the UART checks
it and performs the following:
• If it is an· ASCII control character, the UART sets the
Control Character status bit.
• It checks the wake-up settings and completes any
indicated action.
•

If parity is enabled, the UART checks to see if the
calculated parity matches the programmed parity bit. If
they do not match, it sets the Parity Error bit in URC
(R236 Bank 0), which remains set until reset by software.

•

It sets the Framing Error bit (URC, bit 4) ifthe character is
assembled without any stop bits. This bit remains set until
cleared by software.

Ifthe UART is programmed for a 5-,6-, or 7-bitcharacter, the
extra bits in R239 are ignored.
Serial data is transmitted at a rate equal to t, 1/16, 1/32 or
1/64 of the transmitter clock rate, depending on the
programmed data rate. All data is sent out on the falling
edge of the clock input.
When the UART has no data to send, it holds the output
marking (High). It may be programmed with the Send Break
command to hold the output Low (Spacing), which it
continues until the command is cleared.

Overrun errors occur when characters are received faster
than they are read. That is, when the UART has assembled a
complete character before the CPU has read the current
character, the UART sets the Overrun Error bit (URC, bit 3),
and the character currently in the receive buffer is lost.
The ove~run bit remains set until cleared by software.

444

ADDRESS SPACE
The Super8 can access 64K bytes of program memory and
64K bytes of data memory. These spaces can be either
combined or separate. If separate, they are controlled by the
OM line (Port P3s), which selects data memory when Low
and program memory when High.
Figure 9 shows the system memory space.
CPU Program Memory
Program memory occupies addresses 0 to 64K. External
program memory, if present, is accessed by configuring
Ports 0 and 1 as a memory interfac~.
The address/data lines are controlled by AS, OS and

RiW.

The first 32. program memory bytes are reserved for
interrupt vectors; the lowest address available for user
programs is 32 (decimal). This value is automatically loaded
into the program counter after a hardware reset.

ROM less

ROM and Proto pack

Port 1 is configured as multiplexed address/data or.as I/O.
When Port 1 is configured as address/data, Port 0 lines can
be used as additional address lines, up to address 15.
External program memory is mapped above internal
program memory; that is, external program memory can
occupy any space beginning at the top of the internal ROM
space up to the 64K (16-bit address) limit.
CPU Data Memory
The external CPU data memory space, if separated from
program memory by the OM optional output, can be
mapped anywhere from 0 to 64K (full 16-bit address space).
Data memory uses the same address/data bus (Port 1) and
additional addresses (chosen from Port 0) as program
memory. Data memory is distinguished from program
memory by the OM pin (P3s), and by the fact that data
memory can begin at address OOOOH. This feature differs
from theZ8.

Port 0 can be configured to provide from 0 to 8 additional
address lines. Port 1 is always used as an 8-bit multiplexed
address/data port.
65535

r--------.

65535

EXTERNAL
PROGRAM
MEMORY

r-------,

EXTERNAL
DATA
MEMORY

THIS BOUNDARY )
MAY BE AT 0, OR

8192

DEPEN:~~~~Z~

1----------1 }

ON-CHIP

t--------I

~~~c:ACK

ROM OR

32

INTERRUPT VECTORS
PROGRAM MEMORY

DATA MEMORY

Figure 9. Program and Data Memory Address Spaces

445

INSTRUCTION SET
The Super8 instruction set is designed to handle its large
register set. The instruction set provides a full complement
of 8-bit arithmetic and logical operations, including multiply
and divide. It supports BCD operations using a decimal
adjustment of binary values, and it supports incrementing
and decrementing 16-bit quantities for addresses and
counters.
It provides extensive bit manipulation, and rotate and shift
operations, and it requires no special I/O instructions-the
I/O ports are mappeq into the register file.

Instruction Pointer
A special register called the Instruction Pointer (IP) provides
hardware support for threaded-code languages. It consists
of register-pair R218 and R219, and it contains memory
addresses. The MSB is R218.

The following paragraphs describe each flag bit:

Bank Address. This bit is used to select one of the register
banks (0 or 1) between (decimal) addresses 224 and 255. It
is cleared by the SBO instruction and set by the SB1
instruction.
Fast Interrupt Status. This bit is set during a fast interrupt
cycle and reset during the IRET following interrupt servicing.
When set, this bit inhibits all interrupts and causes the fast
interrupt return to be executed when the IRET instruction is
fetched.
Half-Carry. This bit is set to 1 whenever an addition
generates a carry out of bit 3, or when a subtraction borrows
out of bit 4 .. This bit is used by the Decimal Adjust (DA)
instruction to convert the binary result of a previous addition
or subtraction into the correct decimal (BCD) result. This
flag, and the Decimal Adjust flag, are not usually accessed
by users.

Threaded-code languages deal with an imaginary
higher-level machine within the existing hardware machine.
The IP acts like the PC for that machine. The command
NEXT passes control to orfrom the hardware machine to the
imaginary machine, an0 the commands ENTER and EXIT
are imaginary machine equivalents of (real machine) CALLS
and RETURNS.

Decimal Adjust. This bit is used to specify what type of
instruction wa~ executed last during BCD operations, so a
subsequent Decimal Adjust oper9tion can funCtion
correctly. This bit is not usually accessible to programmers,
and cannot be used as a test condition.

If the commands NEXT, ENTER, and EXIT are not used, the
IP can be used by the fast interrupt processing, as
described in the Interrupts section.

Overflow Flag. This flag is set to 1 when the result of a
twos-complement operation was greater than 127 or less
than -128. It is also cleared to 0 during logical operations.

Flag Register
The Flag register (FLAGS) contains eight bits that describe
the current status of the Super8. Four of these can be tested
and used with conditional jump instructions: two others are
used for BCD· arithmetic. FLAGS also contains the Bank
Address bit and the Fast Interrupt Status bit.
The flag bits can be set and reset by instructions.

Sign Flag. Following arithmetic, logical, rotate, or shift
operations, this bit identifies the state of the MSB of the
result. A 0 indicates a positive number and a 1 indicates a
negative number.
Zero Flag. For arithmetic and logical operations, this flag is
set to 1 if the result of the operation is zero.
For operations that test bits ina register, the zero bit is set to 1
if the result is zero.
For rotate and shift operations, this bit is set to 1 if the result is
zero.

CAUTION

Carry Flag. This flag is setto 1 if the result from an arithmetic
operation generates a carry out of, or a borrow into, bit 7.

Do not specify FLAGS as the destination of an
instructi'on that normally affects the flag bits or the
result will be unspecified.

After rotate and shift operations, it contains the last value
shifted out of the specified register.
It can be set, cleared, or complemented by instructions.

446

Condition Codes

Addressing Modes

The flags C, Z, S, and V are used to control the operation of
conditional jump instructions.

All operands except for immediate data and condition
codes are expressed as register addresses, program
memory addresses, or data memory addresses. The
addressing modes and their designations are:

The opcode of a conditional jump contains a 4-bit field
called the condition code (cc). This specifies under which
conditions it is to execute the jump. For example, a
conditional jump with the condition code for "equal" after a
compare operation only jumps if the two operands are
equal.
The condition codes and their meanings are given in
Table 4.

Register (R)
Indirect Register (IR)
Indexed (X)
Direct (DA)
Relative (RA)
Immediate (1M)
Indirect (IA)

Table 4. Condition Codes and Meanings
Binary

Mnemonic

0000

F

Flags

Meaning
Always false

1000

Always true

0111 '

C

C=1

1111 '

NC

C=O

No carry

0110'

Z

Z=1

Zero

1110'

NZ

Z=O

Not zero

1101

PL

8=0

Plus

Carry

0101

MI

8=1

Minus

0100

OV

V=1

Overflow

1100

NOV

V=O

No overflow

0110'

EQ

Z=1

Equal

1110'

NE

Z=O

Not equal

1001

GE

(8 XORV)=O

Greater than or equal

0001

LT

(8 XORV)= 1

Less than

1010

GT

(Z OR (8 XORV))=O

Greater than

001'0

LE

(Z OR (8XORV))= 1

Less than or equal

1111 '

UGE

C=O

Unsigned greater than or equal

0111'

ULT

C=1

Unsigned less than

1011

UGT

(C=OANDZ=0)=1

Unsigned greater than

0011

ULE

(CORZ)= 1

Unsigned less than or equal

NOTE: Asterisks (') indicate condition codes that relate to two different mnemonics but test the same flags. For example, Z and EO are both True if the
Zero flag is set, but after an ADD instruction, Z would probably be used, while after a CP instruction, EO WQuid probably be used.

447

Notation and Encoding

Registers can be addressed by an 8-bit address in the range
of 0 to 255. Working registers can also be addressed using
4-bit addresses, where five bits contained in a register
pointer (R218 or R219) are concatenated with three bits
from the 4·bit address to form an 8-bit address.

The instruction set not~tions are described in Table 5.

Functional Summary of Commands
Figure 10 shows the formats followed by a quick reference
guide to the commands.
.

Registers can be used in pairs to generate 16-bit program or
data memory addresses.

Table 5. Instruction Set Notations
Notation

Meaning

Notation

Meaning

cc

Condition code (see Table 4)
Working register (between a and 15)
Bit of working register
Bit a of working register
Register or worki ng register
Register pair or working register pair (Register pairs
always start on an even-number boundary)
Indirect address
Indirect working register
Indirect register or indirect working register
Indirect working register pair
Indirect register pair or indirect working register pair
Indexed
Indexed, short offset
Indexed, long offset

DA
RA
1M
IML
dst
src

#
%

Direct address (between a and 65535)
Relative address
Immediate
Immediate long
Destination operand
Source operand
Indirect address prefix
Stack pointer
Program cou nter
Instruction pointer
Flags register
Register pointer
Immediate operand prefix
Hexadecimal number prefix

OPC

Opcode

rb
rO
R
RR
IA
Ir
IR
Irr
IRR
X
XS
XL

@

SP
PC
IP
FLAGS
RP

One~Byte

dst

lope I

Instructions

INC

Two-Byte Instructions

ope

d5t

ope

5'C

ope

d5t

I ~~~~lg~R~~~R~~~:AI~~LI~,C~;.pc6~r

d5t

I PUSH, SRP, SRPO, SRP1

ope

,

I tg~: tg~D,A;~'sc:c~~u~~~c~~~~~~g~'
I loe, lOCPD, LDCPI, LOE, LDEPD, LDEPI

ope

d5t

ope

d5t

b

10

b /t

BITe, BITR
BITS

lope

d5t

DJNZ

lope

d5t

JR

d5t

lope

",c

lope

LD

d5t

LD

Figure 10. Instruction Formats

448

Three-Byte I structions
ACC, ADD, AND, CP, LO, OR, PUSHUD,
PUSHUI, SBC, SUB, TCM, TM, XOR

dsl

OPC

dsl

OPC

dsl

OPC
OPC

I
I

OPC

I

bioi
bi'l
bioi

BAND, BCP, BOR, BXOR, LOB

dsl

BAND, BOR, BT JRY, BXOR, LOB

dsl

BTJRF

OPC

sre

dsl

RA

CPIJE, CPIJNE

OPC

dsl

I

x

sre

lD, LDC, LOE

I

x

dsl

OPC
OPC

ee

ADC, ADD, AND, CP, DIV, LD, LOW, MULT,
OR, POPUO, POPUI, SBC, SUB, TCM, TM, XOR

IOPCI

LD, LDC, LDE

dsl

CALL

dsl

JP

Four·Byte Instructions
OPC

dst Ix¢Oor1!

sre

sre

LOC. LDE

OPC

src Ix*Oor1

dsl

dsl

LOC, LOE

OPC

dsl

I 0000

sre

sre

LOC'

I 0000

dsl

dsl

LOC

sre

LOE

dsl

dsl

LOE

OPC
OPC

dsl

I 0001

OPC

dsl

I 0001

sre

dsl

OPC

} FOR LOC, x = EVEN
FOR LDE, x ODD

=

LOW

Figure 10. Instruction Formats (Continued)

INSTRUCTION SUMMARY

Instruction
and Operation

AddrMode Opcode
Byte
(Hex)
dst src

ADCdst,src
dst - dst + src + C

(Note 1)

'10

ADD dst,src
dst - dst + src

(Note 1)

00

AND dst,src
dst - dst AND src

(Note 1)

BAND dst,src
dst - dst AND src

rO
Rb

Rb
rO

BCP dst, src
dst - src

rO

Rb

BITCdst
dst-NOldst

Flags Affected
CZSVDH

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hex)

Flags Affected
CZSVDH

* * *-

o

*

BORdst, src
dst - dst OR src

rO
Rb

rB
rO

07

-*OU--

* * * *

o

*

BTJRF
if src = 0, PC

RA
dst

rb

37

------

= PC+

-** 0--

BTJRT
ifsrc = '1, PC

RA

rb

37

------

= PC + dst

67
67

-* 0 U--

BXORdsl, src
dst - dst XOR src

rO
Rb

Rb
rO

27
27

-*OU--

17

-* 0 U--

57

-*OU~-

DA
IRR
IA

F6
F4
04

------

rb

CALLdst
SP-SP - 2
@SP-PC
PC -dst

BITRdst
dst-O

rb

77

------

EF

*-----

BITSdst
dst-1

rb

77

------

BO
B1

------

50

CCF
C = NOTC
CLI~dst

dst-O

R
IR

449

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hell)

Flags Affected
CZSVDH
0--

COMdst
dst +- NOT dst

R
IR

60
61

-**

CPdst,sre
dst - src

(Note 1)

AD

* * **--

'CPIJE
if dst - sre ~ O,then
PC+-PC + RA
Ir+-Ir + 1

Ir

C2

------

CPIJNE
ifdst - sre ~ O,then
PC+-PC + RA
Ir+-Ir + 1

Ir

------

02

R
IR

40
41

* * *u--

DECdst'
dst+-dst - 1

R
IR

00
01

-* **--

RR
' IR

01
SMR(O) +-0
DIVdst, sre
dst + sre
dst (U pper) +Quotient
dst (Lower) +Remainder
DJNZr,dst
r+-r - 1
ifr ~ 0
PC +-PC + dst

80
81

-* **--

8F

------

****--

RR
RR

R
IR

94
95

RR

1M

96

RA

EI
SMR(0)+-1

9F

ENTER
SP +-SP - 2
@SP+-IP
IP+-PC
PC +-@IP
IP,....IP + 2

1F

EXIT
IP+-@SP
SP+-SP + 2
PC+-@IP
IP +-IP + 2

2F

INCdst
dst +- dst + 1

rE

-----F)

(r~OtoF)

20
21

CZSVDH

- *.*

* --,

BF

Restored to
.before interrupt

BF
IRET (Normal)
. FLAGS +- @SP; SP +- SP + 1
PC +- @SP; SP +- SP + 2; SMR (0) +- 1

Restored to
before interrupt

IRET(Fast)
PC-IP
FLAG +- FLAG'
FIS +-0

OA
IRR

JRee,dst
, if ec is true,
PC +-PC + d
LDdst,sre
dst +- sre

------

ceO
(ee~'Oto

F)

30

RA

eeB

------

(ee~OtoF)

r
R

1M
R

rC
r8
r9

------

------

r
IR
R
R
R
IR
IR
r
x

IR
r
R
IR
1M
1M
R
x

,C7
07
E4
E5
E6
06
F5
87
97

LDBdst, sre
dst +- sre

rO
Rb

Rb
rO

47
47

------

LDC/LDE.
dst +- sre

r
Irr

Irr

C3
03
E7
F7
A7
B7
A7
B7

-.---'--

xs
r
x1
r
OA

------

xs
r
x1
r
OA

i

R
IR

450

AO
A1

Flags Affected

(r~Oto F)

rA
(r~Oto

AddrMode Opcode
Byte
(Hex)
etst src
RR
IR

INCWdst
dst +-1 + dst

JPee,dst
if ee is true,
PC +-dst

DAdst
dst+- OA dst

DECWdst
dst +- dst - 1

Instruction
and Operation

------

-***--

LDCD/LDED dst, sre
dst +- sre
rr+-rr - 1

Irr

E2

------

LDEIILDCI dst, sre
dst +-src
rr+-rr + 1

Irr

E3

------

F2

------

LDCPD/LDEPD dst,sre
rr+-rr - 1
Irr
dst +- src

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hex)

LDCPI/LDEPI dst. src
Irr
rr-rr + 1
dst -src
LDWdst. src
dsl - src
MULT dst. src

C Z S V 0 H

F3

------

RR
RR
RR

RR
IR
IMM

C4
C5
C6

------

RR
RR
RR

R
IR
1M

84
85
86

*0**--

OF

------

NEXT
PC-@IP
IP-IP + 2
NOP
OR dst.src
dsl - dsl OR src

Flags Affected

(Nole1)

POPdst
dsl-@SP;
sp-sp + 1

FF

------

40

-**0--

R
IR

50
51

------

POPUD dsl. src
dsl - src
IR-IR-1

R

IR

92

------

POPUI dsl. src
dsl - src
IR-IR + 1

R

IR

93

------

PUSJi src
SP - sp - 1; @SP - src

R
IR

70
71

------

PUSHUD dst. src
IR-IR - 1
dst - src

IR

R

82

------

PUSHUI dst. src
IR-IR+1
dsl - src

IR

R

83

------

Instruction
and Operation

Flags Affected
CZSVDH

RLCdst
dst(O) -C
C -dst(7)
dst (N + 1) - dsl (N)
N = 0106

R
IR

10
11

****--

RRdsl
C -dst(O)
dsl (7) - dsl (0)
dsl (N) - dst (N + 1)
'N=0106

R
IR

EO
E1

****--

RRCdsl
C -dst(O)
dsl(7)-C
dsl (N) - dsl (N + 1)
N = 0106

R
IR

CO
C1

****--

SBO
BANK-O

4F

------

SBl
BANK-1

5F

------

3D

* * * * 1 *

DF

1-----

DO
D1

***0--

SBCdst.src
dst - dsl .,. src - C

(Note 1)

SCF
C-1
SRAdst
dsl (7) - dsl (7)
C-dsl(O)
dst (N) - dsl (N + 1)
N = qt06

R
IR

SRPsrc
RPO-IM
RP1 -I~ + 8

1M

31

------

SRPO
RPO-IM

1M

31

------

1M

31

------

ReF
C-O

CF

0---·--

SRP1
RP1-IM

RET
PC- @SP; SP - SP + 2

AF

------

SUBdst.src
dsl - ,dst - src

RLdsl
C-dsl(i')
dsl (0) - dsl (7)
dsl(N + 1) - dsl(N)
N = Ot06

90
91

****--

R
IR

AddrMode Opcode
Byte
(Hex)
dst src

(Nole1)

20

* *

* ..

1 *

451

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation
SWAPdst
dst (0-3) - dst (4-7)
TCMdst;src
(NOT dst) AND src
TMdst,src
dstANDsrc

AddrMode Opcode
Byte
(Hex)
dst src
R
IR
{Note

(Note

1)
1)

WFI
XORdst,src
dst +- dst XOR S(C

(Note

1)

dst

-**

60

-** 0

src

Lower
Opcode Nibble

Ir

(g]
[II

U--

-**0--

3F

------

SO

-**0--

NOTE 1: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble identifies
the command, and is found in the table above. The second
nibble, represented by aD, defines the addressing mode as
shown in Table 6 ..

452

AddrMode

C Z S V 0 H

FO
F1

70

Table 6. Second Nibble

Flags Affected

III

R

R

R

IR

IKI

R

1M

[§J

For example, to use an opcode represented as xO with an "RR"
addressing mode, use the opcode "x4."

o

*
U

= Cleared to Zero
= Set to One
= Unaffected
= Set or reset, depending on result of operation.
= Undefined

SUPER-B OPCODE MAP
Lower Nibble (Hex) ,

o
o

2

5

6

e

.!!

:8

z.

I

7

8

A

B

C

D

E

A

B

C

b

E

F

6

6

6

10

10

6

12/10

6

14

ADD

ADD

ADD

ADD

BOR'

LD

LD

DJNZ

12/10
JR

12/10

ADD
'1.'2

LD

JP

INC

NEXT

'l, lr2

R2. R,

IR2.R,

R,.IM

rO-Rb

r,.R2

r2. R,

r,:RA

cc.RA

r,.IM

CC;DA

r1

6

10

10

6

6

6

RLC

RLC

ADC

ADC

ADC

ADC

ADC

BCP

R,

IR,

'1,(2

'1, Ir2

R2. R,

IR2.R,

R,.IM

r,.b.R2

10

10

10

6

6

6

6

10

10

10

10

INC

SUB

SUB

SUB

SUB

SUB

BXOR'

R,

IR,

f1,r2

'1,lr2

R2. R,

IR2.R,

R,.IM

rO-Rb

NOTE

JP

NOTE
C

6

6

10

SBC

sac

10

SBC

10

SBC

SBC

'l,r2

r,. lr2

R2. R,

IR2.R,

R,.IM

6

6

6

6

10

10

10

,DA

OR

OR

OR

OR

OR

LDB'

R,

IR,

'l,f2

r,. lr2

R2. R,

IR2.R,

R,.IM

rO-Rb

10

10

6

6

10

10

10

8

POP

POP

AND

AND

AND

AND

AND

BITC

IR2.R,

R,.IM

r,.b

IR,

r,. lr2

'l,f2

R2. R,

---sCOM

6

6

6

10

10

COM

TCM

TCM

TCM

TCM

TCM

BAND'

R,

IR,

'1,f2

r,. lr2

R2. R,

IR2.R,

R,.IM

10112

12114

6

6

10

10

10·

PUSH

PUSH

!M

TM

TM

TM

TM

R2

IR2

'1,'2

",lr2

R2. R,

IR2.R,

R,.IM

10

10

10

10

24

24

24

MULT

MULT

DECW

10

10

DECW PUSHUD PUSHUI MULT
IR,

IR,.R2
10

6

RL

RL

R,

IR,

IR,.R2
10

POPUD POPUI
IR2.R,

IR2.R,

R2. RR , IR2.RR, IM.RR,
28112

28/12

28/12

DIY

DIY

DIY

R2. RR , IR2.RR, IM.RR,
10

10

10

10

INCW

INCW

CP

CP

CP

CP

CP

RR,

IR,

'1.r2

'1, Ir2

R2. R,

IR2.R,

'R,.IM

6

6

6

6

10

10

10

10

6

6

CLR

CLR

XOR'

XOR

XOR

XOR

XOR

R,

IR,

'1. r2

r,.1'2

R2. R,

IR2.R,

R,.IM

6

6

16118

12

RRC

RRC

CPIJE

LDC'

R,

IR,

Ir.r2. RA

'1, lrf2

16118

12

10

10

12

LDW

LDW

LOW

SBI

r---

r--

r---e
DI

r---eEI
~

NOTE

RET

0

~

NOTE

IRET

E

r---eReF

6

LD

RR2.RR , IR2.RR, RR,.IML

f1, lr2

r---

20

10

,6

CALL

LD

LD

SCF

IR,.IM

Ir1,f2

r---e-

'2, lrr 1

lA,

16

16

10

10

10

18

RR

RR

LDCD'

LDCI'

LD

LD

LD

LDC'

R,

.IR,

",lrr2

r"lrr2

R2. R,

IR2.R,

R,.IM

16

16

f"

6

.CCF

lrr2,xs

18

10

18

18

CALL

LD

CALL

LDC'

IRR,

R2. IR,

DA,

f2, lrr l,xs

NOTEB

NOTED,

rs--

10

Ir,.r2.RA

NOTE A

SBO

LD

6

'2,lrr,

~

r2,x,rl

IR,

f2,lfr,

WFI

LD

6

IR,

~

rl,x,f2

R,

R,

EXIT

B

6

8

~

10

SRA

SWAP LDCPD' LDCPI'

ENTER

rO-Rb

6

SWAP

~

NOTE

SRA

CPlJNE LDC'

6

A

DA

4P

6

10

INC

8

F

9

IR,

6

9

8

DEC

RR,

;:)

7

6

R,

i

5

R,

IRR,
4

4

DEC

10,

3

3

NOTEC

rs-NOP

Legend:
r ~ 4-bit address
R = 8-blt address
b = bit number
A1 or" = dst address
R2 or '2 = src address

'Examplee:
BOR rO-R2
IS BOR r,.b.R2
or BOR r2.b.R,
LDCr"lrr2

isLDCr"lrr2 =. program
or lDE '"lrf2 data

=

NOTEE
Sequence:
Opcode. first. second. third operands
NOTE. The blank areas are not defined.

Figure 11. Opcode Map

453

INSTRUCTIONS
Table 7. Super8 Instructions
Mnemonic

Operands

Instruction

Load Instructions
CLR
LD,
LDB
LDC
LDE
LDCD

dst
dst, src
dsi, src
dst, src
dst, src
dst, src

LDED

dst, src

LDCI

dst, src

LDEI
LDCPD

dst, src
dst, src

LDEPD

dst, src

LDCPI

dst, src

LDEPI

dst, src

LDW
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI

dst, src
dst
dst, src
dst, src
src
dst, src
dst, src

Arithmetic Instructions
ADC
ADD
CP
DA
DEC
DECW
DIV
INC
INCW
MULT
SBC
SIJB

dst, src
dst, src
dst, src
dst
dst
dst
dst, src
dst
dst
dst, src
dst, src
dst, src

Clear
Load
Load bit
Load program memory
Load data memory
Load program memory and
decrement
Load data memory and
decrement
Load p~ogram memory and
increment
Load data memory and increment
Load program memory with
pre-decrement
Load data memory with
pre-decrement
Load program memory with
pre-increment
Load data memory with
pre-increment
Load word
Pop stack
Pop user stack (decrement)
Pop user stack (increment)
Push stack
Push user stack (decrement)
Push user stack (increment)

,
Add with carry
Add
Compare
Decimal adjust
Decrement
Decrement word
Divide
Increment
Increment word
Multiply
Subtract with carry
Subtract

Logical Instructions
AND
COM
OR
XOR

454

dst, src
dSt
dst, src
dst, src

LogiclllAND
Complement
Logical OR
Logical exclusive

Mnemonic

Operands

Instruction

Program COr:ltrollnstructions
BTJRT
dst, src
Bit test jump relative on True
BTJRF
dst, src
Bit test jump relative on False
CALL
Call procedure
dst
CPIJE
dst, src
Compare, increment and jump on
equal
CPIJNE
dst, src
Compare, increment and jump on
,non-equal
DJNZ
r,dst
Decrement and jump on non-zero
ENTER
Enter
EXIT
Exit
IRET
Return from interrupt
cc, dst
Jump on condition code
JP
Jump unconditional
JP
dst
JR
cc, dst
Jump relative on con'dition code
JR
dst
Jump relative unconditional
Next
NEXT
RET
Return
WFI
Wait for interrupt
Bit Manipulation Instructions
BAND
dst, src
BitAND
BCP
dst, src
Bit compare
BITC
Bit complement
dst
BITR
Bit reset
dst
BITS
Bit set
dst
dst, src
BitaR (
BaR'
pst, src
BXOR
Bit exclusive OR
TCM
dst, src
Test complement under mask
TM
dst, src
Test under mask
Rotate and Shi" Instructions
RL
Rotate left
dst
RLC
dst
Rotate left through carry
Rotate right
RR
dst
RRC
dst
Rotate right through carry
SRA
dst
Shift right arithmetic
SWAP
dst
Swap nibbles
CPU Control Instructions
CCF
DI
EI
Nap
RCF
SBO
SB1
SCF
src
SRP
SRPO
src
SRP1
src

Complement carry flag
Disable interrupts
Enable interrupts
Do nothing
Reset carry flag
Set bank 0
Set bank 1
Set carry flag
Set register pointers I,
Set register pOinter zero
, Set register pOinter one

INTERRUPTS
The vector number is used to generate the address of a
particular interrupt servicing routine; therefore all interrupts
using the same vector must use the sanie interrupt handling
routine.

The 'SuperS interrupt structl,!re contains S levels of interrupt,
16 vectors, and 27 sources.
Interrupt priority is assigned by level, controlled by the
Interrupt Priority register (IPR). Each level is masked (or
enabled) according to the bits in the Interrupt Mask register
(IMR), and the entire interrupt structure can be disabled by
. clearing a bit in the System Mode regisfer (R222).

Levels
Levels provide the top level of priority assignment. While the
sources and vectors are hardwired within each level, the
priorities of the levels can be changed by using the Interrupt
Priority register (see Figure S for bit details).

The three major components of the interrupt structure are
. sources, vectors, and levels. These are shown in Figure 10
and discussed in the following paragraphs.

If more than one interrupt source is active, the source from
the highest priority level will be serviced first. If both sources
are from the same level, the source with the lowest vector will
have priority. For example, if the UART Receive Data bit and
UART Parity Error bit are both active, the UART Parity Error
bit will be serviced first because it is vector 16, and UART
receive data is vector 20.

Sources
A source is anything that generates an interrupt. This can be
internal or external to the SuperS MCU. Internal sources are
hardwired to a particular vector and level, while external
sources can be assigned to various external events.
External interrupts are falling-edge triggered.

The levels are shown in Figure 12.
Vectors
The 16 vectors are divided unequally among the eight
levels. For example, vector 12 belongs to level 2, while level
3 contains vectors 0, 2, 4, and 6.

INTERRUPT SOURCES
COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P2,)
EXTERNAL INTERRUPT (P27)

Por

VECTORS

--1-

NG

I
COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P3,)
EXTERNAL INTERRUPT (P37)

~:~~~~:~I~~~~~~:~ ~P24) I

EXTERNAL INTERRUPT (P2s)

~:~~~~:LKI~~~~~~:~ (~34) I

EXTERNAL INTERRUPT (P3s)
RESERVED

I
I
II

~

112

IR02

I
I
I
114

IROS

I
I
I

I

IR04

128
I
I

I

I

I

IRQ7

130
I

RESERVED

IR03

EXTERNAL INTERRUPT (P3,)
EXTERNAL INTERRUPT (P2,)
EXTERNAL INTERRUPT (P2,)
EXTERNAL INTERRUPT (P3,)

I~O

UART RECEIVE OVERRUN
UART FRAMING ERROR
UART PARITY ERROR
UART WAKEUP DETECT
UART BREAK DETECT
UART CONTROL CHAR DETECT

16

18

UART RECEIVE DATA
EXTERNAL INTERRUPT (P3.)

20

EXTERNAL INTERRUPT (P2.)

22

UART ZERO COUNT
EXTERNAL INTERRUPT (P21)
UART TRANSMIT DATA
EXTERNAL INTERRUPT (P3,)

IROO

IR06

24

!

26

!

IRQ1
I
I
I
I

Figure 12. Interrupt Levels and Vectors

455

Enables
Interrupts can be enabled or disabled as follows:
•

Interrupt enable/disable. The entire interrupt structure
can be enabled or disabled by setting bit 0 in the System
Mode register (R222).

•

Level enabJe. Each level can be enabled or disabled by
setling the appropriate bit in the Interrupt Mask register
(R221).

•

Level priority. The priority of each level can be controlled
by the values in the Interrupt Priority register (R255, Bank
0).

•

Source enable/disable. Each interrupt source can be
enabled or disabled in the sources' Modeand Control
register.

Two hardware registers support fast interrupts. The
Instruction Pointer (IP) holds the starting address of the
service routine, and saves the PC value when a fast interrupt
occurs. A dedicated register, FLAG', saves the contents of
the FLAGS register when a fast interrupt occurs.
To use this feature, load the address of the service routine in
the Instruction Pointer, load the level number into the Fast
Interrupt Select field, and turn on the Fast Interrupt Enable
bit in the System Mode register.
When an interrupt occurs in the level selected for fast
interrupt processing, the following occurs:
•

The contents of the Instruction Pointer and Program
Counter are swapped.

• The contents of the Flag register are copied into FLAG:
• The Fast Interrupt Status Bit in FLAGS is set.

Service Routines
Before an interrupt request can be granted, a) interrupts
must be enabled, b) the level must be enabled, c) it must be
the highest priority interrupting level, d) it must be enabled at
the interrupting source, and e) it must have the highest
priority within the level.
If all this occurs, an interrupt request is granted.
The SuperB then enters an interrupt machine cycle that
completes the following sequence:
•

It resets the Interrupt Enable bit to disable all subsequent
interrupts.

•

It saves the Program Counter and status flags on the
stack.

•

It branches to the address contained within the vector
location for ihe interrupt.

•

It passes control to the interrupt servicing routine.

When the interrupt servicing routine has serviced the
Interrupt, it should issue an interrupt return (IRET)
instruction. This restores the Program Counter and status
flags and sets the Interrupt Enable bit in the System Mode
register.

Fast Interrupt Processing
The SuperB provides a feature called fast interrupt
processing, which completes the interrupt servicing in 6
clock periods instead of the usual 2,2.

456

•

The interrupt is serviced.

•

When IRET is issued'after the interrupt service outline is
completed, .the Instruction Pointer and Program Counter
are swapped again.

• The contents of FLAG' are copied back into the Flag
register.
• The Fast Interrupt Status bit in FLAGS is cleared.
The interrupt servicing routine selected for fast processing
should be written so that the location after the IRET
instruction is the entry point the next time the (Same) routine
is used.

Level or Edge Triggered
Because internal interrupt requests are levels and interrupt
requests from the outside are (usually) edges, the hardware
for external interrupts uses edge-triggered flip-flops to
convert the edges to levels.
The level-activated system requires that interrupt-serving
software perform some action to remove the interrupting
source. The action involved in serving the interrupt may
remove the source, or the software may have to actually
reset the flip-flops by writing to the corresponding Interrupt
Pending register.

STACK OPERATION
The SuperB architecture supports stack operations in the
register file or in data memory. Bit 1 in the external Memory
Timing register (R254 bank 0) selects between the two.
Register pair 216-217 forms the Stack Pointer used for all
stack operations. R216 is the MSB and R217 is the LSB.
The Stack Pointer always points to data stored on the top of
the stack. The address is decremented prior to a PUSH and
incremented after a POP.
The stack is also used as a return stack for CALLs and
interrupts. During a CALL, the contents of the PC are saved
on the stack, to be restored later. Interrupts cause the
contents of the PC and FLAGS to be saved on the stack, for
recovery by IRET when the interrupt is finished.

be used as a general-purpose register, but its contents will
be changed if an overflow or underflow occurs as the result
of incrementing or decrementing the stack address during
normal stack operations. .

User-Defined Stacks
The SuperB provides for user-defined stacks in both the
register file and program or data memory. These can be
made to increment or decrement on a push by the choice of
opcodes. For example, to implement a stack that grows
from low addresses to high addresses in the register file, use
PUSHUI and POPUD. For a stack that grows from high
addresses to low addresses in data memory, use LDEI for
pop and LDEPD for push.

When the SuperB is configured for an internal stack (using
the register file), R217 contains the Stack Pointer. R216 may

COUNTER/TIMERS
The SuperB has two identical independently programmable
16-bit counter/timers that can be cascaded to produce a
single 32-bit counter. They can be used to count. external
events, or they can obtain their input internally. The internal
input is obtained by dividing the crystal frequency by four.
The counter/timers can be set to count up or down, by
software or external events. They can be set for single or
continuous cycle counting, and they can be set with a
bi-value option, where two preset time constants alternate in
loading the counter each time it reaches zero. This can be
used to produce an output pulse train with a variable duty
cycle.

The counter/timers can also be programmed to capture the
count value at an external event or generate an interrupt
whenever the count reaches zero. They can be turned on
and off in response to external events by using a gate and/or
a trigger option. The gate option enables counts only when
the gate line is Low; the trigger option turns on the counter
after a transient High. The gate and trigger options used
together cause the counter/timer to work in gate mode after
initially being triggered.
The control and status register bits for the counter/timers are
shown in Figure 5.

DMA
The SuperB features an on-chip Direct Memory Access
(DMA) channel to provide high bandwidth data
transmission capabilities. The DMA channel can be used by
the UART receiver, UART transmitter, or handshake channel
O. Data can be transferred between the peripheral and
contiguous locations in either the register file or external

data memory. A 16-bit count register determines the
number of transactions to be performed; an interrupt can be
generated when the count is exhausted. DMA transfers to or
from the register file require six CPU clock cycles; DMA
transfers to or from external memory take ten CPU clock
cycles, excluding wait states.

457

ABSOLUTE MAXIMUM RATINGS
Voltage on all pins with respect
.... - O.3V to + 7.0V
to ground ....
Ambient Operating
.See Ordering Information
Temperature
. . . . . . . - 65°C to + 150°C
Storage Temperature.

Stresses greater than these may cause permanent damage to the device.
This is a stress rating only; operation of the device under conditions more
severe than those listed for operating conditions may cause permanent
damage to the device. Exposure ·to absolute maximum ratings for
extended periods may also cause permanent damage .

STANDARD TEST CONDITIONS

+5V

Figure 14 shows the setup for standard test conditions. All
voltages are referenced to ground, and positive current
flows into the reference pin.

1K

Standard conditions are;
•

+4.75V";; Vcc";; + 5.25V

•

GND

=

OV
TEST LOAD (FOR ALL PINS)

Standard Test Load

DC CHARACTERISTICS

Symbol

Parameter

VCH

Clock Input High Voltage

VCl

Clock Input Low Voltage

VIH

Input High Voltage

Vil

Input Low Voltage

VRH

Reset Input High Voltage

VRl

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

Max

Unit

3.8

Vcc
0.8

V

Driven by External Clock Generator

V

Driven by External Clock Generator

Vcc
0.8

V

Vcc
0.8

V

-0.3

2.2
-03
3.8
-0.3
2.4

0.4

III

Input Leakage

-10

10

IOl

Output Leakage

-10

10

IIR

Reset Input Current

-50

ICC

Vec Supply Current

320

458

Condition

Min

V
V

=-

V

IOH

V

IOl = +4.0 mA

I-'A
I-'A
I-'A
mA

400 I-'A

INPUT HANDSHAKE TIMING

DATAIN~~~

06

. . ."

24

RDYOUT

1'-----.1(
Strobed Mode

Fully Interlocked Mode

AC CHARACTERISTICS (20 MHz)
Input Handshake

Number

symbol

Parameter

1

TsDI(DAV)

Data In to Setup Time

2

TdDAVlf(RDY)

DAV -I Input to RDY -I Delay

3

ThDI(RDY)

Data In Hold Time from RDY-I

4

TwDAV

DiWlnWidth

5

ThDI(DAV)

Data In Hold Time from DAV-I

6

TdDAV(RDY)

DAV t Input to RDY t Delay

7

TdRDYf(DAV)

RDY -I Output to DAV t Delay

Min

Max

Notes**

o
200

o
45
130
100

2

o

NOTES:
1. Standard Test Load
2. This time assumes user program reads data before DAV Input goes high. RDY will not go high before data is read.
Himes given are in ns.
'Times are preliminary and subject to change.

459

OUTPUT HANDSHAKE TIMING
DATAOUT.~,--_ _ _ _ _ _ _ _ _ _ __

~b

DATA OUT

DAVOUT

~~-j-I~.
-6---'l..Y

DAVOUT

RDYIN

Fully Interlocked Mode

Strobed Mode

AC CHARACTERISTICS (12 MHz, 20 MHz)
Output Handshake

Number

Symbol

Parameter

Min

TdDO(DAV)

Data Out to DAV. Delay

2

TdRDYr(DAV)

RDY t Input to DAV. Delay

0

3

TdDAVOf(RDY)

DAV. Output to RDY • Delay

0

4

TdRDYf(DAV)

RDY. Input to DAV t Delay

0

5

TdDAVOr(RDY)

DAV t Output to RDY t Delay

0

6

TwDAVO

DAV Output Width

Max

Notes·:!:
1,2

90

1

110
110

150

2

NOTES:
1. Standard Test Load
2. Time given is for zero value in Deskew Counter. For nonzero value of n where n = 1,2, ... 15 add 2 x n xTpC to the given time.
Himes given are in ns.
'Times are preliminary and subject to change.

AC CHARACTERISTICS (12 MHz)
Read/Write

Number

Symbol

Parameter,

Extended Timing
Min
Max

1

TdA(AS)

Address Valid to AS t Delay

35

115

2

TdAS(A)

AS t to Address Float Delay

65

150

3

TdAS(DR)

AS t to Read Data Required Valid

4

TwAS

AS Low Width

5

TdA(DS)

Address Float to DS •

20

20

6a

TwDS(Read)

DS (Read) Low Width

225

470

130

270

600
150

65

6b

TwDS(Write)

DS (Write) Low Width

7

TdDS(DR)

DS. to Read Data Required Valid

8

ThDS(DR)

Read Data to DS t Hold Time

0

0

295
180

420

9

TdDS(A)

DS t to Address Active Delay

50

135

10

TdDS(AS)

DS t to AS • Delay

60

145

11

TdDO(DS)

Write Data Valid to DS (Write). Delay

35

12

TdAS(W)

AS t to Wait Delay

13

ThDS(W)

DS t to Wait Hold Time

14

TdRW(AS)

R/WValid to AS t Delay

NOTES:
1. WAIT states add 167 ns to these times.
2. Auto-wait states add 167 ns to this time.
~ All times are in ns and are for 12 MHz input frequency.
• Timings are preliminary and subject to change.

460

Normal Timing
Max
Min

115
220

600

0

0

50

135

2

AC CHARACTERISTICS (20 MHz)
Read/Write

Number

Symbol

Parameter

Normal Timing
Min
Max

TdA(AS)

Address Valid to AS t Delay

20

2

TdAS(A)

AS t to Address Float Delay

35

3

TdAS(DR)

AS t to Read Data Required Valid

4

TwAS

AS Low Width

Extended Timing
Min
Max
50
85

150
35

335
85

5

TdA(DS)

Address Float to DS ~

a

a

6a

TwDS(Read)

DS (Read) Low Width

125

275

65

6b

TwDS(Write)

DS (Write) Low Width

7

TdDS(DR)

DS ~ to Read Data Required Valid

, 8

ThDS(DR)

Read Data to DS t Hold Time

165
80

225

a

a

TdDS(A)

DS t to Address Active Delay

20

70

10

TdDS(AS)

DS t to AS ~ Delay

30

80

11

TdDO(DS)

Write Data Valid to DS (Write) ~ Delay

10

12

TdAS(W)

AS t to Wait Delay

13

ThDS(W)

DS t to Wait Hold Time

14

TdRW(AS)

R,W Valid to AS t Delay

9

50
90

335

a

a

20

70

2

NOTES:
1. WAIT states add 100 ns to these times.

2. Auto·wait states add 100 ns to this time.
t All times are in ns and are for 20 MHz input frequency.
* Timings are preliminary and subject to change.

R/W

PORT 0

DM ____

Aa-A15, OM

-J'~------~~----------------------------------~------------------~

PORT 1

1--------{12)--------!r---:J1.
External Memory Read and Write Timing

461

ADDRESS OUT , .

Ao-A,.

'

X

---J~~I-.~-~_-_-_-_-_-_-~0~~~-~-_~-_-_-_-~1~----J ~-------

DATAIN======~==========================~r-.-D-O.D-1-'N~)(:===========
EPROM Read Timing

AC CHARACTERISTICS (20 MHz)
EPROM Read Cycle

Number

Symbol

Parameter

TdA(DR)

Address Valid to Read Data Required
Valid

NOTES:
1. WAIT states add 167 ns to these times.
j:A1I times are in ns and are for 12 MHz input frequency.
·Timings are preliminary and subject to change.

462

Min

Max

170

~ ZiIill

Application Note

August 1987

GETTING STARTED
WITH THE ZILOG SUPERB
by Charles M. Link, II
Any time an engineer switches to a new processor, he
usually begins tl)e time consuming process of learning
the quirks of the new part. This article is the first of a
series of articles written to speed that transition time from
any other processor to the Zilog Super8.
Getting started is the most difficult part of switching to a
strange new processor and development tools. Weeks
can be spent just getting the first lines of initialization
code written and successfully assembled. Testing the
code becomes another problem. The soft, lre from this
article series has been tested and it should be possible
to copy most of the software directly to a user's application. All of the software is available in machine readable
form as noted at the end of the article.
This first article demonstrates the proper initialization of
the Zilog Super8 microcontroller. It sets up a Z8800
ROM LESS for 64K bytes of external program memory,
although most typical applications probably do not require more than maybe 4K or 8K bytes. Ports 2 and 3,
which are bit mappable as inputs or outputs, are set into
the output mode. Port 4,also bit mappable, is set into
the input mode. A hardware schematic has been included as an example.
The hardware schematic shown defines a simple Super8
implementation that was used to test the code in this
series of articles. This example defines a simple evaluation board that contains 32K bytes of programable
EPROM, and up to 32K bytes of RAM. The design contains a simple RS-232 interface that is used in future articles of the series. The entire board, including the
RS-232 interface, is powered from 5 volts. The RAM
battery option allows the software to be downloaded into
the RAM and saved if power fails. Additional logic on the
design allows a user to protect the lower half of RAM
with a simple jumper change. This prevents the processor from destroying executable code if it goes off into
space on a power failure.
Specifically, the ROM LESS SuperS is used as the core.
The Super8 requires a latch to demultiplex the address
from the data bus. A 74LS373 fits nicely here, requiring
only an inverter to correct for the address strobe. The
'LS373 with inverter is preferred here rather than a single
'LS374 because the 'LS373 is a transparent latch and

will present the address earlier than the 'LS374. JU1
selects the EPROM size, correcting for the IPGM pin on
2764 and 27128 EPROMs. It is necessary to use pull
down resistors on the upper 4 bits of the address bus because on reset, the ROMLESS Super8 defines only 12
bits for address; the other 4 are set as inputs. Since LSTTL devices require more current to pull down the inputs,
this pull down trick will only work for MOS and CMOS inputs, hence the requirement for the logic chips in this
design to be HCr type devices.
The remaining logic is required to select the EPROM or
RAM. JU2 selects the half-RAM protect mode. JU3 is
set to determine what size ram to protect. This circuit allows the lower half of CMOS battery backed RAM to be
read only, and removes chip select on any writes to that
address space. Of course, that exact Circuitry and the'
battery is optional, and might be replaced by a power
threshold detector. On the other front, a Maxim MAX
232 provides the RS-232 interface requiring only 5 volts.
To make the software initialization more interesting, a
few other typical initialization tasks are demonstrated.
The entire block of registers (user ram) is cleared to
zero, and one of the counter timer units is initialized,to
provide a periodiC interrupt to form the heart of a real
time clock function.
The program shows the typical pseudo-op usage
demonstrated. This article series uses a cross assembler available from Zilog for either an IBM PC or a
VAX operating under VMS. The program begins by
defining the registers,used as general purpose storage.
This is done so the user does not have to refer to register
numbers,. but may refer to a name equated to the
register.
The first 32 bytes of every program (beginning at OOOOH)
always contain the interrupt vectors for the different sources. USing the Zilog assembler, the. WORD pseudo-op
defines a pair of by1es for each of the 16 sources.
Program execution begins at location 0020H. Since
copyright requirements usually require the notice as
close to the beginning as possible, it becomes necessary
to jump around an ASCII string. The .ASCII pseudo-op
generate~ the necessary string for this notice.

463

The source code describes almost completely, without
further explaination, the entire initialization. Once initialized, the processor loops ina WAIT loop waiting on the
periodic interrupt generated by the counterltimer. The
counter timer interrupts 60 times per second, and the interrupt bumps ram storage locations representing.
seconds, minutes, and hours. Each time a location is
bumped, an external port line is toggled so that those
without emulators can see some activity with anoscilloscope.
One point of notice, is the interrupt service routine for the
timer. One must reset the end of count interrupt bit (the
source of interrupt) before exiting the interrupt service
routine.

.TITLE

In the next artide of this series, we will take the same
basic initialization routine and modify it to support the
serial UART. That article will demonstrate polled serial
communications using tile Zilog Super 8.
[Editors note: The sofware for this series is available on
an IBM PC diskette and is included with the Super 8
Emulator package available from. Creative Technology
Corporation, 5144 Peachtree Road, Suite 301, Atlanta,
GA 30341. (404) ~55-8255. Any Zilog Field Application
engineer should also be able to provide copies of the
software on a user provided·diskette.)

Sample zilog Super 8 Initialization

;===============================-========7==================

;=
;=
;=

;=

INIT.S8
JUNE 17, 1986
TO DEMONSTRATE INITIALIZATION
OF THE ZILOG SUPER 8 USING THE
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II

TITLE:
DATE:
PURPOSE:

1=

:=

PROGRAMMER:

:===========================================================

,

. PAGE

Iset maximum page size to 55 lines

55

:***********************************************************
;*

REGISTER EQUATE TABLE

1*

:*

.

*

*
*

;***********************************************************

period:
second:
minute:
hours':

.equ
.equ
.equ
.equ

o

Iperiod timer
Iseconds timer
;minutes timer
;hours timer

1

2
3

I

: ****** *** ** * * .,** * * * * * ******* ** ** ** ** ** ** **** * * **** * * ** **** *
;*

INTERRUPT VECTOR TABLE

1*

*
*

;*
*
:***********************************************************

INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTRa:
INTR9:
INTR10:
INTRll:
INTR12:
INTR13:
INTR14:
INTR15:

• WORD
• WORD
•WORD
•WORD
• WORD
•WORD
•WORD
• WORD
• WORD
•WORD
•WORD
•WORD
•WORD
•WORD
•WORD
• WORD

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET

Ithis area should always be defined
las it reserves the lower 32 bytes
Ifor the interrupt table. the name
,of the subroutine for each particular
;interrupt service would normally be
;named here.

I

; * ** ********* **** * *** ****** ******* ** * * * * * ** * * * * *.**** ** ** * ***
i*

;*
1*

START OF PROGRAM EXECUTION

*

*

*

;***********************************************************

464

START:

jr
• ASCII

START1: dl
sbO
ld
ld
ld
ld
ld

START1'

;program execution unconditionally
;begins at this location after reset
land power up.
'REL 0 6/16/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
I
;select register bank 0
EMT,I/OOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
land DNA internal
;address
begins at OOOOh, set upper byte
PO,'OOH
POM, #11111111B ;select all lines as address
;enable port 0 as upper 8 bits address
PM,'00110000B
H1C"OOOOOOOOB ;handshake not enabled port 0

;

;port 1 is defined in romless part as address/data.
;here to initialize that port

it is not necessary

;port 2 outputs low
;port 3 outputs low
;p30,31,20,21 as output
;p32,33,22,23 as output
;p34,35,24,25 as output
;p36,37,26,27 as output

ld
ld
ld
ld
ld
ld

P2,1/00H
P3,'00H
P2AM,f10101010B
P2BM,#10101010B
P2CM" #10101010B
P2DM,f10101010B

ld
ld
ld

;clear port 4 register
P4"OOOOOOOOB
P4D, 'l1l1l111B ;set all bits of P4 as inputs
P40D,'OOOOOOOOB ;active push/pull [not necessary since all
; bits are inputs

,

;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld

RPO"OCOH
RP1"OC8H
SPL,'OFFH

;set working register low to lower 8 bytes
;set working Fegister high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bi,ts are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
; storage.

;

;now clear the internal memory and stack area
ZERO:

ld
clr
dec
jr
clr

SPH, #OFFH
@SPH
SPH
nZ"ZERO
@SPH

;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register

;now everything except working registers is cleared
;cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
sb1
ld
ld
ld
sbO
ld

SYM,#OOOOOOOOB
IPR,'00000010B

;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,'00000100B ;enable only, interrupt 2
;select bank 1
COTCH"AHB(50000)
;high byte of time constant
COTCL"ALB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freq, 4 is internal divider
COM,#00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,#10100101B ; continuous, count down, load counter,
;zero count interrupt enable, enable counter

;

;timer is 'initialized, now lets enable interrupts and wait
WAIT:

ei
nop
nop
nop
nop
jr

;enable interrupts

WAIT

;loop back

465

nop
nop
nop
TIMERO: inc
cp
jr

xor
clr
inc
cp
jr

xor
clr
inc
cp
jr

xor
clr
inc
cp
jr

clr
or
naP
nop
INTRET: iret

NOROLL~

.END

466

period
period,#60
ne,NOROLL
P2,ilOOOOOOOlB
period
second
second,#60
ne,NOROLL
P2,ilOOOOOOlOB
second
minute
minute,#60
ne,NOROLL
P2,#OOOOOlOOB
minute
hours
hours,#24
ne,NOROLL
hours
COCT,#OOOOOOlOB

;bump periodic counter (60 hertz)
;one second yet?
;no rollover
;complement the second bit
;start it- over again
;bump the seconds timer
;reached maximum
;no rollover
;complement the minute bit
;start it over again
;bump the minutes timer
;reacheq maximum
;no rollover
;complement the hour bit
;start it over again
;bump the hours timer
;reached maximum
;no rollover
;start it over again
;reset end of count interrupt
;and return from interrupt

~ ZiIm
August 1987

Application Note

POLtED ASYNCHRONOUS
SERIAL OPERATION
WITH THE ZILOG SUPERB
by Charles M. Link, II

The transition from one processor to another often involves many hours of trial-and-error software development
to determine the quirks (manufacturers call it features) of
the part.
.once the real features are discovered,
programming the processor to perform as described can
be hazardous to one's health. This article, the second in
a series of eight, attempts to introduce the Zilog Super8
user to the serial communications port, and its initialization in a polled serial environment.
The universal asynchronous receiverltransmitter (UART)
on the Super8 is a fairly unique implementation among
single Chip microcomputers in that it supports all of the
functions generally available only on chip level UARTs.
The UART is a close approximation of the Z80i DART
device in one channel.
It supports independent
receiver/transmitter clocking, 5 to 8 bits per character,
plus optional odd or even parity, and even an optional
wake-up bit. The UART can serve full duplex communications via polled, interrupt, or DMA modes of
operation. Auto-echo and 'intemal loop back can be
programmed as options. The most unique of the UART
features is the character match and interrUpt option.
The following article describes the initialization and use
of the UART in a polled environment. This software has
been tested and provides several routines that may be
copied into a user's software, Although the demonstration software does not do much, it is fully functional as a
stand-alone program, and may be "burned" into eprom
as atesl.
The basic software is almost the same general purpose
initialization software from the first article in the series.
Routines set-up counterltimer 0 for a real time clock option. Note, however, the change to configuration register
P2AM, It is necessary to configure port 30 as input for
receive data and p31 as output for transmit data.
The UART initialization sequence begins by setting the
functions in the UART MODE A register. Since the UMA
register is in the alternate bank, the instruction SB1 must
be executed to gain access to the following registers.
The loaded data selects a X16 clock, 8 bits per character, no parity, and no wake up values. Note that. the
clock options are X1, X16, X32, and X64. For true
asynchronous operation, a clock multiplier option of at
least XJ6 is required. The X1 mode could be used for
externally syncing the received data to the UART. The
transmitter is not affected.

Next, the baud rate generator must be loaded. The formula for determining the baud rate is shown below:
TIME CONSTANT = (XTAL FREQ / 8 / CLOCK MULT /
DESIRED RATE)-1
where TIME CONSTANT is a 16 bit value, XTAL FREQ
is the crystal lfrequency in hertz, CLOCK MULT is the
clock rate loaded into UART MODE A register (as above
X1, X16, X32, and X64), and DESIRED rate is the
desired bit rate in bits per second. Note that the baud
rate generator may be used as an additional counter,
and may be loaded with any value permitting just about
any crystal frequency to operate the Super8.
The cross-assembler permitted a single 16-bit decimal
number to be loaded into the UART BAUD RATE GENERATOR, high and low byte, without unnecessary figuring using the high/low byte pseudo-op.
The initialization sequence continues, with the UART
MODE B register next. This example sends port 21 data
to the port 21 pin. An option allows different clocks to be
sent out from this pin. It could be used for clocking external logic, or for diagnostic purposes to make sure the
baud rate generator is running.
Auto-echo is not
selected in this application, as that is primarily what the
example software does. The receive and transmit clock
input is the baud rate generator and the generator source
is the intemal clock; the crystal divided by four. Since
the baud rate generator has been loaded, it is enabled,
and the UART is set for normal operation (without loopback). Loopback operation permits transmitting and
receiving data without any external logic in front of the
Super8.
The UART TRANSMIT CONTROL register is initialized
next in the sequence. Select transmit data out on port 31
and transmit enable. The stop bits are optional, and the
DMA and WAKE-UP enables are for features discussed
in future application articles. At this pOint, the transmitter
is operational, and except for housekeeping, is usable.
The housekeeping is in reference to selecting the bank 0
by executing the SBO instruction.
Since polled mode communications are desired, all of the
UART interrupts are disabled by loading the UART INTERRUPT ENABLE with all zeros. Lastly, the receiver
must be enabled by setting bit 0 of the UART RECEIVE
CONTROL register.
467

This program primarily sends a message to the console
and then 'accepts input from the console and ectios it
l,lpon re~iying a carriage return. It is necessary to delay
sending (lata to the console after initialization because
the transmit data line is in'the SPACE,state when idle.
AHernately, ·add a pulFup resistor to the output, and While
idle and before initialized, it would exibit the MARK state,
The transmit character routine "SENDC" monitors the
TRANSMIT BUFFER EMPTY bit of the UART TRANSMIT CONTROL register. When this bit is a "1", the transmit buffer is ernpty and may be loaded with a new
character for transmission. To transmit a character, load
the character into the'UART data register (UIO) .
• TITLE

The receive character routine "GETC" monitors the
RECEIVE CHARACTER AVAILABLE bit of the UART
RECEIVE CONTROL, register. 'When this bit is a "1", a
new character has been received by the UART.
The polled mode of UART 0l¥'ration is simple. Making
the UART operate in an interrupt mode requires a few
minor modifications, and DMA mode requires a few more
modifications. Those modes are the subject of future application articles in this series.

Sample Ziloq Super 8 Serial Port Initialization

;==~-=====-----===~============~--=~=-=-==========-=-

;=

;=

;m

TITLE:
DATE:
PURPOSE:

;,.

;=
;;=
;a===

ASSEMBLER:
PROGRAMMER:

_____________

• PAGE

=

UARTl.S
JULY 17, 1986 '
TO DEMONSTRATE INITIALIZATION
AND USAGE OF SERIAL PORT IN
POLLED MODE.
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, I I

55

============================~====

.*.

;set maximum page size to 55 lines

; ** ********************** ******* * * **** * ** **
:*
;*

********** *,** *

*

GENERAL EQUATES

;*

I

**

';***********************************************************
CR:
LF:

.equ
.equ

;carriage return
;line feed

OdH
OaH

;

:***********************************************************
;*

;*

REGISTER EQUATE TABLE

;*

*

*

*

;***********************************************************

,

periOd: .equ'
0
;period timer
second: .equ
1
;seponds timer
minute: .equ
2
;minutes timer
hours: .equ
3
;hours timer
;working register equates
MPTR:
.equ
RR8
;message pointer for external memory
;

,

;***********************************************************
;*

INTERRUPT VECTOR TABLE
;*

*

**

;***************************************~************* ******

INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTRIO:
INTRl1:
INTR12:

468

• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
_WORD

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERP
INTRET
INTRET
INTRET
INTRET
IN,TRET
INTRET

this area should always be defined
as it reserves the lower 32 bytes
for the interrupt table. the name
of the subroutine for each particular
interrupt service would normally be
named here.

INTR13
INTR14
INTR15

• WORD
• WORD
• WORD

INTRET
INTRET
INTRET

;***********************************************************

:*

*

START OF PROGRAM EXECUTION

**

:*

;***********************************************************

START:

jr
• ASCII

START1: di
sbO
Id
Id
Id
Id
Id

;program execution unconditionally
;begins at ~his location after reset
land power up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
; begin
;select register bank 0
EMT,#OOOOOOOOB ;externa1 memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
land DMA internal
;address begins at OOOOh, set upper byte
PO,#OOH
POM, #11111111B ;select all lines as address
;enable port 0 as upper·S bits address
PM, #00110000B
H1C,#00000000B ;handshake not enabled port 0
STARTl

;port 1 is defined in rom1ess part as address/data.
;here to initialize that port
Id
ld
Id

Id
Id
Id
Id
Id
ld

,

it is not necessary

;port 2 outputs low
P2,#00H
;port 3 outputs low
P3,#00H
P2AM,#10001010B ;p31,20,2l as output,p30 input
lit is necessary here to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM,i/l0101010B ;p32,33,22,23 as output
P2CM,i/10101010B ;p34,35,24,25 as output
P2DM, #10101010B ;p36,37,26,27 as output
;clear port 4 register
P4,#00000000B
P4D, #11l11111B ;set all bits of P4 as inputs
P40D,#00000000B ;active push/pull (not necessary since all
; bits are inputs

;basic Super S I/O is initialized, now internal registers
ld
Id
ld

RPO,#OCOH
RPl,#OCSH
SPL,#OFFH

;set working register low to lower S bytes
;set working register high to upper S bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
; storage.

; now clear the internal memory and stack area
ZERO:

Id
clr
dec
jr
clr

SPH,#OFFH
@SPH
SPH
nz,ZERO
@SPH

;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register

inow everything except working registers is cleared

; cpu and memory now initialized, set up timer for real time clock
Id
Id
Id
sb1
Id
ld
Id

SYM,#OOOOOOOOB
IPR,#00000010B

;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,#OOOOOlOOB ;enable only interrupt 2
;select bank 1
COTCH,#AHB(50000)
;high byte of time constant
COTCL,#ALB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freg, 4 is internal divider
COM,#00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected

469

sbO
ld

,

;select bank 0
COCT,#lOlOOlOlB ;continuous, count down, load counter,
;zero count interrupt enable, enable counter

;timer is set, now lets initialize the UART for polled operation
sb1
ld

ld
ld
ld

sbO
ld
ld
ld

;bank 1
UMA,#01110000B
;time constant = (12,000,000/4/16/9600/2)-1=
;S.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH,#AHB(00009)
;high byte of time constant
UBGL,#ALB(00009)
;low byte of time constant
UMB,#0001ll10B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
lis disabled
;select bank 0
UTC,#10001000B ;select p31 as transmit data out, 1 stop bit
land transmit enable
UIE,#OOOOOOOOB ;disable all interrupts, no DMA
URC,#00000010B ;enable receive

;UART is initialized, enable interrupts for real time clock

,

;enable interrupts

ei

;wait 1 full second for serial line to mark before sending anything
WAIT:

cp
jr

second, #1
ne,WAIT

;wait 1 second

;display the logon message
LOGON:

ldw
call

MPTR,j/MSG
SENDM

; load the address' of MSG into word reg MPTR
;send the message

;logon message displayed, get response from console
land move to upper register memory
GET:
GETN:

,

Id
Id
call
and
call
ld
cp
jr
inc
djnz

r1,j/SO
r2, #SOH'
GETC
rO, #7fH
SENDC
@r2,rO
rO,#CR
eq,EcHO
r2
r1,GETN

;maximum character count
;point to first location in upper register bank
;get input from console
;remove upper parity bit
;echo to console
;move to upper internal ram in SuperS
;was the received character a carriage return
;if so, echo it to console
;bump pointer
;get next character if not done

;if carriage return typed, or SO characters exceeded, echo message
ECHO:

ECH01:

,

ldw
call
Id
Id
Id
call
cp
jr
inc
djnz
jr

MPTR, #MSG1
SENDM
r1,#SO
r2,#SOH
rO,@r2
SENDC
rO,#CR
eq,LOGON
r2
r1,ECH01
LOGON

;load the address of MSG1 in word reg MPTR
;send the message
;maximum character count
;first location of character buffer
;get character from buffer
;send the character to console
icarriage return?
;if so, end message display
;bump pointer
;display next character if not done

; sUbroutines
;send message at MPTR until '$' character found
SENDM: ldci
rO,@MPTR
;get the character
;otherwise send character
call
SENDC
;last character?
cp
ro,#'$'
land loop back to send next one
jr
ne,SENDM
ret

470

:send character in rO
SENDC: tm
UTC,#OOOOOOlOB,
jr
z,SENDC
U10,rO
ld
ret
:get a character from the uart,
GETC:
tm
URC,#OOOOOOOlB
jr
z,GETC
ld
rO,U10
ret

transmit buffer empty yet
if not, wait until it is
load the character into the transmitter
return in rO
:character available
:if not, wait until it is
:get the character from the receiver

;real time interrupt running in background
:bump periodic counter (60 hertz)
lone second yet?
;no rollover
;complemerit the second bit
;start it over again
;bump the seconds timer
;reached maximum
;no j:"ollover
;complement the minute bit
;start it over again
:bump the minutes timer
;reached maximum
;no rollover
;complement the hour bit
;start it over again'
;bump the hours timer
;reached maximum
;no rollover
;start it over again
;reset end of count

T1MERO: inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
clr
NOROLL: or
nop
nop
1NTRET: iret

period
period, #60
ne,NOROLL
P2,#00000001B
period
second
second, #60
ne,NOROLL
P2,#00000010B
second
minute
minute, #60
ne,NOROLL
P2,#00000100B
minute
hours
hours, #24
ne,NOROLL
hours
COCT,#OOOOOOlOB

MSG:

CR,LF,'Super8 Uart test program.',CR,LF
'Enter up to one full line followed by return',CR,LF,'$'
CR,LF,'Echoed back, your line was .•• ',CR,LF, '$'

MSGi:

• ASCII
.ASCII
• ASCII

land return from interrupt

.END

471

472

~ Zirm
- August 19S7

Application Note

USING THE ZILOG SUPERB
IN INTERRUPT DRIVEN
COMMUNICATIONS
by Charles M. Link, II

The power of the Super1J microcomputer lies in its on
board peripherals. One of those peripherals is th~ full
duplex UART. The UART can operate under program
control in polled mode, or under interrupt control, and in
a DMA mode. This article, the third in a se~ies, discusses using the UART in a fully interrupt driven system.
Since it is assumed that the reader has access to the
eariler article discussing the UART and the polled mode
of operation, this article will only discuss the differences.
The Zilog SuperS contains an on board interrupt controller that is tightly -linked to the other on-board peripherals.
The UART, being on-board, can be operated in an interrupt mode permitting very little execution overhead time
while monitoring the UART for incomming characters and
waiting for the UART to send outgoing characters.
Operation of an interrupt driven system demands more
software logic to control the interrupt. Although more
software is present, less time is spent executing it, because most of the overhead is in the setup for interrupt
transfers. Generally, interrupt driven serial VO overlaps
some other process or processes, and therefore enhances total system speed and operation. -Interrupt driven
1/0 has no advantages in a system that must wait on the
serial port. In the example program, no real advantage
has been gained by interrupt operation. The program
displays a simple message to the console, and accepts
input responses and echos them.
For program
simplicity, the main program waits on the interrupt to
complete before starting the next phase of the program.
In any interrupt -driven system, the central processor
must know what to do when an interrupt occurs. The
SuperS is no exeception. An interrupt vector table
directs the processor to begin execution at certain addresses for particular interrupt inputs. The UART can be
the source for up to five different interrupts and therefore
up to five of the sixteen vectors can be designated for it.
This sample program ignores errors and special condition interrupts, and therefore only two vectors_ are used; one for transmit buffer empty and one for receive character available. These vectors are programmed into the
vector table by setting interrupt vector 10 (zero
reference) to the address for the receive data service
routine, and setting interrupt vector 13 to the address for
the transmit data service routine.

The setup of the SuperS is essentially the same as that
of the serial port in a polled mode of operation. The
proper priority for the interrupts are assigned arbitrarily.
The real time clock as highest priority, the receive
character available as second priority, and transmit
character buffer empty as the lowest priority. Generally,
the transmit interrupt should be the lowest in an
asynchronous system because if it does not get serviced
limmediately, no major problems occur. If the real time
interrupt took more time in relationship to the time required to transmit a single character, then maybe the
receive should be put higher. If the receiver is not serviced, that character would be lost.
Enabling the interrupts is a two stage process. First the
mask in the INTERRUPT MASK REGISTER must be
enabled for each level of the interrupts used. Next, it is
necessary to enable the individual transmit and receive
interrupts. In the example program, a character is
loaded into the transmit buffer and then the interrupt is
enabled by setting bit 2 in the UART INTERRUPT
ENABLE (UlE) register. Each successive transmit interrupt indicates an empty buffer, and the next character is
loaded into the buffer. When the last character is loaded
into the buffer, the transmit interrupt is disabled to
prevent further interruptions by clearing bit 2 of the UJE
register.
The receiver interrupt is enabled to allow the processor
• to accept incoming characters by setting bit 0 of the UIE
register. Once set, any received character will cause the
processor to transfer control to the "RXDATI" routine. In
this example, the receive service routine reads, echos,
and stores each received character until a carriage
routine is received. The input is then repeated.
The example program does not fully utilize the interrupt
system, as it waits for each routine to complete before
moving to the next. However, it does however work, and
demonstrates interrupt service routines. Serial interrupt
software is not complex, and could lead to very powerful
user programs. With the addition of the on board DMA to
automaticlly transfer characters, the SuperS can complete many tasks that previously would require complex
hardware and software. The next article in the series
demonstrates using the DMA controller with the serial
port.

473

.TITLE

Sample Zilog. super 8 Serial Interrupt Mode Operation

;=====================================~=====================

:=
:=
;=

UART2.S
JULY 17, 1986
TO DEMONSTRATE INTERRUPT
DRIVEN SERIAL PORT
COMMUNICATIONS
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II

TITLE:
DATE:
PURPOSE:

:=
;=

;=
;=

ASSEMBLER: ,
PROGRAMMER:

;=================================================~=== ======

• PAGE

55

;set maximum page size to 55 lines

;***t************~************************************ ******

:*
;*
:*

GENERAL EQUATES

*

*

*

:***********************************************************

CR:
LF:

.equ
.equ

;carriage return
;line feed

OdH
OaH

:***********************************************************

:*

REGISTER EQUATE TABLE

*

*
*
;***********************************************************

period: .'equ
0
;period timer
second: .equ
1
;seconds timer
minute: .equ
2
;minutes timer
hours: .equ
3
;hours timer
;working register equates
MPTR:
.equ
RR8
;message pointer for external memory

,

:***********************************************************

:*

INTERRUPT VECTOR TABLE

*

*

*

;*

:***********************************************************

INTRO:.
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
.INTR9:
INTR10:
INTRll:
INTR12:
INTR13:
INTR14:
INTR15:

,

• WORD
• WORD
• WORD
. WORD
• WORD
• WORD
'.WORD
. WORD
• WORD
. WORD
• WORD
• WORD
. WORD
• WORD
. WORD
. WORD

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
TXDATI
INTRET
INTRET

;this area should always be defined
las it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.

:***********************************************************

:*
;*

START OF PROGRAM EXECUTION

*
*
*

:***********************************************************
START:

jr
• ASCII

START1: di
sbO

474

START 1

;program execution unconditionally
; beg ins at this location after reset
;and power up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register bank 0

Id

EMT,#OOOOOOOOB

Id
Id
Id
Id

PO,I/OOH
POM,I/11111111B
PM,j00110000B
H1C,#00000000B

external memory timing=no wait input, normal
memory" timing, no wait states, stack internal,
and DNA internal
address begins at OOOOh, set upper byte
select all lines as address
enable port 0 as upper S bits address
handshake not enabled port 0

port 1 is defined in romless part as address/data.
here to initialize that port
Id
Id
Id

Id
Id
Id
Id
Id
Id

,

it is not necessary

;port 2 outputs low
P2,/IOOH
P3,#00H
;port 3 outputs low "
P2AM,#10001010B ;p31,20,21 as output,p30 input
lit is necessary here to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM,#10101010B ;p32,33,22,23 as output
P2CM,#10101010B ;p34,35,24,25 as output
P2DM,#10101010B ;p36,37,26,27 as output
;clear port 4 register
P4,#00000000B
P4D, 'l1111111B ;set all bits of P4 as inputs
P40D,#00000000B ;active push/pull [not necessary since all
; bits are inputs

;basic super S I/O is initialized, now internal registers
Id
Id
Id

RPO,I/OCOH
RP1,#OCSH
SPL,'OFFH

;set working register low to lower S bytes
;set working register high to upper S bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
; storage.

;now clear the internal memory and stack area
ZERO:

Id
clr
dec
jr
clr

SPH,/IOFFH
@SPH
SPH
nz,ZERO
@SPH

;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register

;now everything "except working registers is cleared
;cpu and memory now initialized, set up timer for real time clock
Id
Id

14

sb1
Id
Id
Id
sbO
Id

SYM,#OOOOOOOOB
IPR,'00000010B

;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,#01000110B tenable counter, rx and tx interrupts
;select bank 1
COTCH,I/AHB(50000)
thigh byte of time constant
COTCL,#ALB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freq, 4 is internal divider
COM,1/00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,#10100101B ; continuous, count dOwn, load counter,
;zero count interrup~enable, enable counter

timer is set, now lets initialize the UART for polled operation
sb1
Id

UMA,1/01110000B

Id
ld
Id

time constant
(12,000,000/4/16/9600/2)-1S.76 rounded to 9.
note that a 12 Mhz does not make a very
accurate baud rate source. error is large
UBGH,#AHB(00009)
thigh byte of time constant
UBGL,I/ ALB(00009)
;low byte of time constant
p21=p21data,auto-echo"is off, transmit and
UMB,'0001111011
receive clo.ck is baud rate generator output,
baud rate generator input is system clock / 2,
baud rate generator is "enabled; loopback
is disabled

;bank 1

475

sbO
ld

UTC,#lOOOlOOOB

ld
ld

UIE,'000000008
URC,.OOOOOOlOB

select bank 0
select p31 as transmit data out, 1 stop bit
and transmit enable
no interrupts, no DMA
enable receive

IUART is initialized, enable interrupts for real time clock
ei

I enable. interrupts

I

:wait 1 full second of serial line mark before sending anything
WAI~:

cp
jr

second,'l
ne,WAIT

:display the logon
LOGON:

ldw
call
call

:wait 1 second

m~ssage

MPTR,j/MSG
SENDM
TXWAT

:load the address of MSG into word reg MPTR
Isend the message
Iwait for transmitter to complete

I

:logon message displayed, get response from console
land move to upper register memory
ld
r1, jlSO
;maximum character count
:point to first location in upper register bank
ld
r2,'SOH
di
:stop interrupts
or'
UIE,.000000018 Ireceive character enable
ei
/now wait for input'to be completed
GW:
tm
UIE,'OOOOOOOlB :wait for interrupt to be disabled
nZ,GW
.
:if interrupt still enabled
jr
GET:

I

:if carriage return typed, or SO characters exceeded, echo message
ECHO:

ldw
:load the address of MSG1 in word reg MPTR
MPTR,'MSG1
call
:send the message
SENDM
:
:since messages are interrupt driven, we must wait for message to
;complete before transmitting next message

call
ld
ld
ECH01: ld
. call
cp
jr
inc
djnz
jr

,

TXWAT
/r1,lIsO
r2"SOH
rO,@r2
SENDC
rO,lICR
eq,LOGON
r2
r1,ECH01
LOGON

:wait on transmitter
Imaximum character count
Ifirst location of character buffer
:get character from buffer
Isend the character to console
;carriage return?
lif so, end message display
;bump pointer
.
Idisplay next character if not done

~

; sUbroutines

,

.Isend message at MPTR until '$' character found
SENDM: ldci
rO,@MPTR
;get the character
call
;start UART transmitting
SENDC '
;no interrupts
di
or
tenable
transmit interrupts
UIE,/l00000100B
ei
ret
;send character in rO
SENDC: tm
UTc,II00000010B ;transmit buffer empty yet
;if not, wait until it is
jr
z,SENDC
ld
UIO,rO
;load the character into the transmitter
ret
:trans~it buffer available interrupt
TXDATI: ldci
rO,@MPTR
;get next character to transmit
; lO,ad the character in transmitter
ld
UIo,rO
;last character
cp
ro,t'$'
;if last transmit character
jr
eq,LASTT
iret
LASTT: and
UIE, /1111110118 ;disable transmit interrupts
iret
;ignore it if no character to transmit
; transmitter wait routine
TXWAT: tm,
UIE,#00000100B ;wait until interrupts disabled
jr
;wait if bit set
nz,TXWAT
ret

476

;receive character available interrupt
RXDATI: ld
rO,UIO
;get input from console
;remove upper parity bit
and
rO,#7fH
call
SENDC
;echo to console
ld
@r2,rO
;move to upper internal ram in SuperS
cp
rO,IICR
;was the received character a carriage return
jr
eq,LASTR
;if so, disable interrupts
inc
r2
;bump pointer
djnz
r1,RXR
;exit if not last
LASTR: and
UIE,#11111110B ;disable the receive interrupts
RXR:
iret

,

;real time interrupt running in background
TlMERO: inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
c1r
NOROLL: or
nop
nop
INTRET: iret

MBG:

MSG1:
.END

• ASCII
•ASCII
•ASCII

period
period, #60
ne,NOROLL
P2,1I00000001B
period
second
second, #60
ne,NOROLL
.P2, #00000010B
second
minute
minute,j/60
ne,NOROLL
P2,'00000100B
minute
hours
hours, #24
ne,NOROLL
hours
COCT,#00000010B

;bump periodic counter (60 hertz)
lone second yet?
;no rollover
;complement the second bit
;start it over again
;bump the seconds timer
;reached maximum
;no rollover
;complement the minute bit
;start it over again
;bump the minutes timer
;reached maximum
;no rollover
;complement the hour bit
;start it over again
;bump the hours timer
;reached maximum
;no rollover
;start it over again
;reset end of count
land return from interrupt

CR,LF,'Super8 Uart test program.',CR,LF
'Enter up to one full line followed by return',CR,LF,'$'
CR,LF,'Echoed back, your line was •.• ',CR,LF,'$'

478

~ ZiIill

Application Note

August 1987

USING THE SUPERS
SERIAL PORT WITH DMA
by Charles M. Link, II
With the increasing integration available today,
microprocessor manufacturers are incorporating new
peripherals that typically were off board in previous
products, and sometimes required a large amount of external logic to utilize. The direct memory access function
is a good example. Zilog has incorporated a very powerful DMA in the new Super8 microcontroller. It has the
capability of linking to several on board peripherals, including the serial port, and can control data transfers to
the different memory mediums.
. The SuperS, with its on-board DMA can reduce processor overhead in data transfer tasks. It allows direct
transfer of serial input characters to either intemal
register memory (256 bytes) or extemal ram memory.
For example, this transfer can be set to transfer a
specific number of input characters, then interrupt the
processor. Processor program service overhead is minimal. Serial output characters can be transfered from external EPROM or ram memory, or the internal register
memory.
The required setup for the DMA transfers are much the
same as that of interrupt or polled operation. This
program example uses the DMA to interrupt upon termination of data transfers so that approopriate vectors
and routines are required. Since the program links to the
serial port, the DMA uses the serial port receive and
transmit interrupt vectors 10'and 13, respectively. Upon
completion of a receive DMA transfer, the service routine
defined by the receive vector is executed. Upon completion of the transmit DMA transfer, service routine defined
by the transmit vector is executed.
It is necessary to define the memory source/destination
by·setting the appropriate state of bit 0 in the EXTERNAL
MEMORY TIMING (EMT) register. Initially, the example
program selects external memory as the source/destination. A special note: read the fine print in the technical
manual. Many hours were spent debugging the DMA
mode of operation, with the final realization that intemal
rom does not qualify as external memory. Only that
memory that would be selected if the /DM line was true
would be a valid' source/destination. Since, this article
uses the hardware defined from the first of the series,
and uses a Z8800 with external EPROM, it will work perfectly. ROM and PIGGYBACK or prototype type parts
will not work. Neither will emulators.

This sample uses the DMA mode to transmit a few lines
of ASCII data to a console. The DMA requires a total
byte count to properly transfer the data and terminate.
Be careful to recognize that the ASCIL pseudo-op in the
Zilog assembler, or many other assemblers,. is not an
easy way to generate the byte count. Warning I The
Zilog assembler generates a length for each subgroup,
e.g., "MSG" generates a separate length for each group
separated by commas, not one total length.
Initially, the DMA transfers from EPROM. The address
from which to transfer is CO and C1 as defined by the
working register pOinters. It is necessary to set RPO to
CO to access the register, and it is accessed as RO and
R1 or RRO. The count for the transfer is taken from DMA
COUNT HIGH and DMA COUNT LOW. For each transfer, initialize the address and count values. Upon completion of the DMA transmit process, when the count
goes to -1, a transmit interrupt is generated. The example program disables transmit interrlJpts and DMA,
and returns. The main line program was polling the interrupt enable bit for completion.
Next, the DMA is set up to transfer 25 characters into the
internal register memory. One must select intemal
memory in the EMT register by clearing bit O. The address for transfer requires only one byte, so that working
register 1 (R1), when RPO equals CO, is the address
pOinter. The DMA count must also be loaded, in this
case with 25. For demonstration purposes, the autoecho bit of the UART MODE B register is selected. This
causes any characters received to be automatically
looped back to the transmit port. Finally, the receive interrupt and DMA enable bits (BITS 0 and 1) are set to
enable and begin DMA operation. When 25 characters
have been inpuJ to the Super8, a feceive interrupt will be
generated, and control will be transfered to the "RXDATI"
routine, where interrupts and DMA are disabled.
The last routine in the example software sends another
message from EPROM to the console and then sends
the characters from the internal memory buffer that were
previously entered.
The prime consideration is to
remember to select the source/destination memory in the
EMT register.
In this DMA example, the code is simple for DMA opera-

. . . . . . . . . . . . . . . . . . . . . .tion. It is important to note that this example does not

479

fully utilize the functionality of the DMA transfer. The example purposely waits in a software loop while the DMA
transfer occurs. This prevents the supporting code from
becoming too complex to follow for an example. Normal
operation might have the UART receiving characters
.TITLE

under DMA controls and transmitting characters under
interrupt control with processing occurring somewhere in
the middle.

Sample Zilog Super 8 Serial DMA Mode operation

~===========================================================

:=
;=
;=
;=

TITLE:
DATE:
PURPOSE:

UART3.S
JULY 17, 1986
TO DEMONSTRATE DMA
DRIVEN SERIAL PORT
COMMUNICATIONS
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, I I

j=

;=

:=

ASSEMBLER:
PROGRAMMER:

;==============~====================================== ======

• PAGE

55

;set maximum page size to 55 lines

:***********************************************************

:*
;*

'GENERAL EQUATES

:*

*
*

*

:***********************************************************
CR:
LF:

.equ
.equ

;carriage return
;line feed

OdH
OaH

;***********************************************************
REGISTER EQUATE TABLE

*
*

*

:***********************************************************

,

period: .equ
0
;period timer
second: .equ
1
;seconds timer
minute: .equ
2
;minutes timer
hours:
.equ
3
;hours timer
;working register equates
MPTR:
.equ
RRO
;message pointer for external memory

;***********************************************************

:*

;*

INTERRUPT VECTOR TABLE

;*

*
*
*

;***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
INTRll:
INTR12:
INTR13:
INTR14:
INTR15:

• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
. WORD
. WORD
• WORD
. WORD
• WORD
• WORD
• WORD
. WORD
• WORD
. WORD

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
TXDATI
INTRET
INTRET

;this area should always be defined
las it reserves the lower 3.2 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.

;***********************************************************
START OF PROGRAM EXECUTION

*

*
*
;***********************************************************
START:

480

jr

STARTl

;program execution unconditionally

• ASCII
START1: di
sbO
ld

,

ld
ld
ld
ld

;begins at this location after reset
;and power up.
'REL 0 7/17/86' ;jump around optional ascii string
:containing release info, copyright, etc.
:begin
.
:select register bank 0
EMT,#OOOOOOOlB ;external memory timing=no wait input, normal
:memory timing, no wait states, stack internal,
land DMA external
PO,#OOH
:address begins at OOOOh, set upper byte
POM,#11111111B :select all lines as address
PM, #00110000B
:enable port 0 as upper 8 bits address
H1C,#00000000B :handshake not enabled port 0

:port 1 is defined in romless part as address/data.
;here to initialize that port
ld
ld
ld

ld
ld
ld
ld
ld
ld

it is not necessary

;port 2 outputs low
P2,#00H
:port 3 outputs low
P3,#00H
P2AM,#10001010B ;p31,20,21 as output,p30 input
lit is necessary here to configure p30 as input
:for the receive data, and p31 as output for
;transmit data for UART
P2BM,#10101010B :p32,33,22,23 as output
P2CM,#10101010B ;p34,35,24,25 as output
P2DM,#10101010B ;p36,37,26,27 as output
P4,#00000000B
;clear port 4 register
P4D, #11111111B ;set all bits of P4 as inputs
P40D,#00000000B ;active push/pull [not necessary since all
; bits are inputs

;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld

RPO,#OCOH
RP1, #OC8H'
SPL,#OFFH

;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
;as stack operation. SPH is general purpose
;storage.

; now clear the ·internal memory and stack area
ZERO:

ld
clr
dec
jr
clr

SPH,#OFFH
@SPH
SPH
nZ,ZERO
@SPH

;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register

;now everything except working registers is cleared
;cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
sb1
ld
ld
Id
sbO
ld

SYM,#OOOOOOOOB
IPR,#00000010B

;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,#01000110B ;enable counter, rx and tx interrupts
;select bank I
COTCH,#~HB(50000)
;high byte of time constant
COTCL,#~LB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freq, 4 is internal divider
COM,#00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,#10100101B ; continuous , count down, load counter,
;zero count interrupt enable, enable counter

timer is set, now lets initialize the UART for polled operation
sb1
ld

;bank 1
UMA,#01110000B
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
481

ld
ld
ld

UBGH,#~HB(00009)
UBGL,#~LB(00009)

UMB,#OOOllllOB

sbO
ldUTC,#lOOOlOOOB
ld
ld

UIE,#OOOOOOOOB
URC,#OOOOOOlOB

;high byte of time constant
;low byte of time constant
;p2l=p2ldata,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
lis disabled
;select bank 0
;select p3l as transmit data out, 1 stop bit
land transmit enable
;no interrupts, no DMA
;enable receive

;UART is initialized, enable interrupts for real time clock
ei

;enable interrupts

;because uart was just enabled, allow data line to mark for at least
WAIT:

cP

jr

,

second, #1
ne,WAIT

1

second

;wait 1 second

;display the logon message
LOGON:

ldw
call
call

MPTR, #MSG
SENDM
TXWAT

;load the address of MSG into word reg MPTR
;send the message
;wait for transmitter to complete

;logon message displayed, get response from console
land move to upper register memory
GET:

,

di
ldw
and
sb1
ld
ld
or
sbO
or
ei
call

UIE,#OOOOOOl1B

;no interrupts while setting up for DMA
;first character receive location
;select register file for receiving character
;select bank one
;DMA count high byte
;DMA count low byte
;auto echo enable
;restore to bank zero
;receive character DMA link, interrupt enable

RXWAT

;wait for receiver to complete receiving input

MPTR,#0080H
EMT, # 11111110B
DCH,fO
DCL,#2S
UMB,#00100000B

ireceive characters in buffer, restore Super8 non DMA state
di
sb1
and
sbO
or
ei

UMB,#110111l1B
EMT,#00000001B

;no interrupts while cleaning up
;bank 1
;disable auto echo
; restore bank 0
;select data memory for DMA transfers

;25 characters received via DMA, now display "ECHO" message
ECHO:

ldw
call
call

MPTR, #MSG1
SENDM
TXWAT

;load the address of MSGl in word reg MPTR
;send the message
;wait on transmitter

message sent, now replay typed input
. di
ldw
and
sb1
ld
ld
sbO
or
or
ei
call
di
or
ei

MPTR, #0080H
EMT, # 11111110B

TXWAT

;pointto beginning of buffer
;select register bank for DMA transfer
;select bank 1
;DMA count high byte
;DMA count low byte
;select bank 0
\
;enable transmit interrupts
;transmit DMA enable
;enable interrupts
;wait on transmitter

EMT,#OOOOOOOlB

;select external ,data memory for DMA transfer

DCH,#O
DCL,#2S
UIE,#OOOOOlOOB
UTC,#00000001B

replay complete, loop 'back and do it again
jr

482

LOGON

,
; subroutines
;send message at MPTR for length in first byte
SENDM: ldci
;get the character
r7,@MPTR
;count actually should be n-1 for n bytes
dec
r7
;no interrupts while setting up
di
EMT,#00000001B ;select external data memory for DMA transfer
or
;select bank 1
sb1
;DMA count high byte is 0
ld
DCH,#O
;move the count DMA count low byte
ld
DCL,r7
;select
bank 0
sbO
UIE,#00000100B ;enable transmit interrupts
or
or
UTC,#00000001B ;transmit DMA enable
ei
ret
;transmit DMA complete
TXDATI: and
UIE,#11111011B ;disable transmit interrupts
UTC, #11111110B ,;disable transmit DMA
and
;ignore it if no character to transmit
iret
; transmitter wait routine
TXWAT: tm
UIE,#00000100B ;wait until interrupts disabled
jr
;wait i f bit set
nz,TXWAT
ret
;receive character available interrupt
RXDATI: and
UIE,J/11111100B ;disable the receive interrupts
iret
;receive wait routine
RXWAT: tm
UIE,J/00000001B ;wait until interrupts disabled
;wait if bit still set
jr
nz,RXWAT
ret
;real time interrupt running in background
TIMERO: inc
cp
jr

xor
clr
inc
cp
jr

xor
clr
inc
cp
jr

xor
clr
inc
cp
jr

clr
NOROLL: or
nop
nop
INTRET: iret

MSG:
MSG1:

• BYTE
. ASCII
• ASCII
• BYTE
. ASCII

period
period, #60
ne,NOROLL
P2,#00000001B
period
second
second, #60
ne,NOROLL
P2,J/00000010B
second
minute
minute,J/60
ne,NOROLL
P2,#00000100B
minute
hours
hours,J/24
ne,NOROLL
hours
COCT,J/00000010B

;bump periodic counter (60 hertz)
;one second yet?
;no rollover
;complement the second bit
;start it over again
;bump the seconds timer
;reached maximum
;no rollover
;complement the minute bit
;start it over again
;bump the minutes timer
;reached maximum
;no rollover
;complement the hour bit
;start it over again
;bump the hours timer
;reached maximum
;no rollover
; start' it over again
;reset end of count
;and return from interrupt

56
CR,LF,'Super8 Uart DMA test program.',CR,LF
'Enter 25 characters',CR,LF,'$'
34

CR,LF,'Echoed back, your line was ..• ',CR,LF,'$'

.END

483

484

~ ZiIill

Application Note

August 19S7

GENERATING SINE WAVES
WITH THE ZILOG SUPER8
by Charles M. Link, II
Generally digital microprocessors are thought of as only
being able to generate digital signals ...that is either on or
off. With the simple addition of a digital-ta-analog converter (DAC), more complex waveforms may be
generated. Since the advent of the microprocessor and
the DAC, many methods have been used by hardware
and software designers to generate sine waves, induding some that involve precise instruction and clock cycle
calculations. This example is different.
The Zilog SuperS microcomputer is a single chip device
requiring only a latch and EPROM to operate in its ROMLESS state. Leaving 24 I/O lines for user configuration,
it is extremely easy to interface with peripherals, induding, in this case, the DAC- OS. The hardware in this application example is essentially the same base hardware
as the previous application articles. Since it is assumed
that the reader has access to those articles, detailed explaination of the base will not be made here. Only the
additions to the base will be explained.
The base SuperS microprocessor has ports 2, 3 and 4
available for user connection. For this example, the
DAC-OS is connected to port 4 (P4). The DAC-OS .is tied,
with the least significant bit tied to P40 and the most significant bit tied to P47. The other connections to the
DAC-OS are mostly out of the test circuit description
shown in the data manuals associated with it. The DAC
requires -12 volts for proper operation. The outpuffor
this example is tied to a simple op- amp filter with a
sharp roll off at about 3500 hertz. This type filter might
be quite suitable for telecommunications applications, but
may not be so good for many others. An oscilloscope
displays the resultant waveform.
The software to operate the SuperS is in the original initialization software from eariler in this article series. Initialization is essentially the same. Port 4 must be set up
as output, with active push-pull drivers. The main consideration for this program is the software "sarrlple" rate.
For this example, SOOO samples per second was chosen.
Any other rate may be chosen, and the author has successfully used values up to 16000 samples per second
without timing problems. Higher base clock rates are
possible with the recently introducecd 20 megahertz
SuperS chips available: With the sample method used,
the sample rate does not vary with the different sine
wave frequencies generated.

The sample method requires a sine wave table stored in
ROM or EPROM. This example uses 256 values, although 64, 12S or more values are quite acceptable.
The BASICA program that generated the sine table is included for user modification. Once the values were
generated, they were manually typed into the program.
Using the Zilog macro assembler would have signigicantIy slowed assembling. Note that the comments in the
BASICA program imust be removed before the PC can
execute.
The values generated by the BASICA program are
values ranging from 01 H to OFEH. Since the DAC represents OOH as zero volts and OFFH as 5 volts, this table
will product sine outputs from almost zero to almost five
volts.
The principle of operation requires that a sixteen bit frequency increment be maintained. This increment is
generated by the simple formula
FREQUENCY INCREMENT ~ (TABLESTEP'X 256 X FREQUENCY) I SAMPLE

where FREQUENCY INCREMENT is a sixteen bit value
saved in an increment register, TABLESTEP is the number of values in the sine wave table, FREQUENCY is the
desired frequency of generation in hertz, and SAMPLE is
the number of samples per second. In the example
program, this increment is stored in "FINCR".
A current offset into the sine table is maintained in the
register pair labeled "INCR". At each periodic interrupt,
FINCR must be added to INCR and saved in INCR. This
sixteen bit value remains the offset into the table. The
upper byte of the offset is used to pOint to the value in
the 256 byte sine table that is loaded into the DAC. In
the sample program, the value loaded into the DAC is
generated in the previous interrupt and saved until the
first instruction of the next interrupt. This allows the interrupt to perform some other varying length transactions,
without introducing bit jitter into the sine wave.
Changing the "FINCR" by program control causes different frequencies to be generated. In this case, the sine
wave may be tumed off by disabling the counter 0 interrupt. Depending upon the number of steps in the sine

4S5

, table and the sample, frequency. very accuratl;! sine fre-'
quencies,may be gemiratEld. Calculate the actual error
by using the folloWing'formula:
[ ABS ( REAL FREOI 100=% ERROR

INT~GER

FREOI) I REAL FREOI

1X

I

With th~ addition of a' fiHer with shatp' cutoff just above
the, highest de!!ired frequency, the SuperS serves q4ite
well as a programmable sinE:! wave generator. In addition
to sine waves, complex wavefor:m!! may be easily
generated by the Super8 with the addition of the low-cost
DAC. The next article in this series will describe how to
generate some of these more complex waveforms.

where REAL FREQI, is the actual calculated frequency
increment. INTEGER FREQI is the nearest rounded intElger of the calculated frequency, increment, and the
res\Jlt is the actu~1 per~nt error form the desired value.

• TITLE

Super8 Example Sine Wave Generation

;__---====--==-==aD-===========__==================___
;-

TITLE:
DATE:

i=

PURPOSE:!

~=

;-

ASSEMBLER:
PROGRAMMER:

• PAGE

;set maximum page size to SS lines

;z

;=
1'''

;=

;=

,

=~==

SINE.S
JUNE i7, 1986
TO DEMONST~TE USING SUPER8
TO GENERATE HIGH QUALITY SINE
WAVES.
DAC-08 ON PORT 4
SEE DIAGRAM
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II

HARDWARE:

SS

;***************.****.**************~***************** ******

:*

*

REGISTER EQUATE TABLE

;*

**

:*
;***********************************************************
INCR:
INCRH:
INCRL:
FINCR:
FINCRH:
FINCRL:
POINT:
POINTH:
POINTL:
CVAL:

,

.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ

rrO
rO
r1
rr2
r2
r3
rr4
r4
rS
r6

;current increment in sine table
;high byte of current increment value
;low byte of ' current increment value
;increment'in sine table for frequency
:high byte of frequency increment value
;low byte of frequency increment value
:pointer into sine table
;high byte of sine table pointer
;low byte of sine table pointer
;current value to output to DAC-08

;***********************************************************

:.

GENERAL EQUATES

;*
;*

-

*
**

;***********************************************************
XTAL:
SAMPLE:
CTVAL:
TABSTP:
FREQ:
FREQI:

.equ
.equ
.equ
.equ
.equ
.equ

12000000
;crystal freq in. hertz
8000
;sample frequency in hertz
XTAL/4/SAMPLE
;counter load value
2S6
;number of values in sine table
69?
;desired sine wave frequency
(TABSTP*2S6*FREQ)/SAMPLE

~

:***********************************************************
:*
*
INTERRUPT VECTOR TABLE
;*
*
:*
*
;***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTRS:
INTR6:
INTR7:
486

• WORD
• WORD
•WORD
• WORD
.WQRD
• WORD
• WORD

• WORD

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TlMERO
INTRET

this area should always be defined
as it reserves the lower 32 bytes
for the interrupt table. the name
of the subroutine for each particular
interrupt service would normallY,be
named here.

INTR8:
INTR9:
INTR10
INTR11
INTR12
INTR13
INTR14
INTR15

• WORD
•WORD
• WORD
• WORD
• WORD
• WORD
•WORD
•WORD

INTRET
INTRET
INTRET
INTRET

INTRET
INTRET

INTRET
INTRET

;~***.*****************************************.****** ******

;*

1*

*
*

*

START OF PROGRAM EXECUTION

;*

1***********************************************************

START:

jr
•ASCII

START1: di
sbO
ld
ld
ld
ld
ld

Iprogram execution unconditionally
I~egins at this location after reset
land power up.
'REL 0 6/16/86' Ijump around optional ascii,string
Icontaining release info, copyright, etc.
Ibegin
Iselect register bank' 0
lexternal
memory timing=no wait input, normal
EMT,'OOOOOOOOB
ImemOry timing, no wait states, stack internal,
land DNA internal
laddtess begins at OOOOh, set upper byte
PO"OOH
POM,I11111111B Iselect all lines as address
lenable port 0 as upper 8 bits address
PM,,00110000B
H1C,100000000B Ihandshake not enabled port 0
START1

IPort 1 is defined in romless part as address/data.
Ihere to initialize that port

,

it is not necessary

Iport 2 outputs low
IPort 3 outputs low
Ip30,31,20,21 as output
Ip32,33,22,23 as output
Ip34,35,24,25 as output
Ip36,37,26,27 as output

ld
ld
ld
ld
ld
ld

P2"OOH
P3,/IOOH
P2AM,/I1010l010B
P2BM,#101010;J.OB
P2CM,110101010B
P2DM,/I10101010B

ld
ld
ld

P4,,10000000B
Iset midpoint for DAC inputs
P4D,'00000000B Iset all bits of P4 as output
P40D,/lOOOOOOOOB lactive push/pull

Ibasic Super 8 I/O is initialized, 'now internal registers
ld
ld
ld

RPO,'OCOH
RP1,'OC8H
SPL,'OFFH

Iset working register low to lower 8 bytes
Iset working register high to upper 8 bytes
Iset stack pointer to start at top of set two
Inote here that only lower 8 bits are used
Ifor stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
I storage.

Inow clear the internal memory and stack area
ZERO:

ld
clr
dec
jr
clr

SPH,'OFFH
@SPH
Spa
nz,ZERO
@SPH

IPoint to top of general purpose register
Izero it
Ido it until register set is all cleared
' Izero last register

I

Inow everything except working registers is cleared

,

(CPu and memory now initialized, set up timer for real time clock
ld
ld
ld
sb1
ld
ld
ld
sbO
ld

SYM,'OOOOOOOOB
IPR, '00000010B

Idisable fast interrupt response
:interrupt priority,
IIRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,'OOOOOlOOB lenable only interrupt 2
Iselect bank 1
COTCH"AHB(CTVAL)
Ihigh byte of ti.- constant
COTCL"ALB(CTVAL)
Ilow byte of time constant
COM,'OOOOOlOOB Ip27,37 is I/O, programmed up/down, no capture
Itimer mode is selected
,select bank 0
COCT,#10100101B I continuous, count down, load counter,

487

Izero

co~t

interrupt enable, enable counter

;

;timer is initialized, now lets
ldw
INCR,U
ldw'
FINCR,'FREQI
ldw
POINT,'SINTAB
ld
CVAL,'080H
ei
WAIT:
nop
nop
nop
nop
jr
WAIT

enable interrupts and wait
Istart at the beqinninq of sine table
iload frequency of increment
IPointer points to sine table
linitial value to Prevent qlitch'at start
I enable interrupts '

Iloop back

I

ITimer, interrupt. Occurs SAMPLE times per second
;interrupt outputs value to DAC-08 and then determines value for next
; interrupt. This assures no bit jitter.
TlMERO: ld
ref
add
adc
ld
ldc
or
INTRET: iret

p4,CVAL

;write new value to DAC-08
;clear carry flaq
INCRL,FINCRL
;find next position in sine table
;by addinq frequency offset to last position
INCRH,FINCRH
POINTL,INCRH
;set new pointer into sine table
;upper byte ok since on boundary
CVAL,@POINT
;qet value from sine table
COCT,'00000010B ;reset end of count interrupt
; and return from interrupt '

;

;***********************************************************

:*
;*

SINE WAVE LOOKUP

;*

*
*
*

; ****.************** *** ** ******* *,*********************** ****

;sine table for sine wave qeneration usinq DAC-08. Table based upon
;case of waveform with minumum ~mplititude = O'volts and maximum
;amplititude = 5 volts. DAC-08 input for 0 volts = OOR
;5 volts - OFFH. Table qenerated usinq followinq BASICA proqram,
;then typed into proqram.

;

10 cIs
20 PI-3.141593
30 FOR 1=0 TO 255
40 C=360/256
50 D=C*I
60 E=D*PI/180
70 F-SIN(E)
80 G-F*127
90 H-128+G
100 J=CINT(H)
110 A$=HEX$(J)
120 PRtNT A$
130 LPRINT A$
140 NEXT
150 END

;clear screen
;define PI
;256 total values
;define basic interval value
Ivalue from zero on sine wave
;fiqure sine for interval from 0
;sine ranqe should be from -127 to 127
;make result from 0 to 255
;round to nearest inteqer
;convert to hex
Ion screen
Ion printer
;do next 'inverval

;

;*note-remove comments, BASlCA will not accept ; as comment delimiter
SINTAB: .ORG
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte

488

0400H
;beqin sine table on even byte boundary
080H,083H,086H,089H,08CH,090H,093H,096H,099H,09CH,09FH,OA2H
OA5H,OA8H,OABH,OAEH,OB1H,OB3H,OB6H,OB9H,OBCH,OBFH,OC1H,OC4H
OC7H,OC9H,OCCH,OCEH,OD1H,OD3H,OD5H,OD8H,ODAR,ODCH,ODEH,OEOH
OE2H,OE4H,OE6H,OE8H,OEAR,OEBH,OEDH,OEFH,OFOH,OF1H;OF3H,OF4H
OF5H,.OF6H, OF8H, OF9H, OFAR', OFAR, OFBH, OFCH, OFDH, OFDH, OFEH, OFEH
OFEH, OFFH,'OFFH, OFFH, OFFH, OFFH, OFFH, OFFH, OFEH, OFEH, OFEH, OFDH
OFDH, OFCH, OFBH, OFAiI, OFAR"OF9H, OF8H, OF6H, OF5H, OF4H, OF3H, OF1H
OFOH,OEFH,OEDH,OEBH,OEAR,PE8H,OE6H,OE4H,OE2H,OEOH,ODEH,ODCH
ODAH,OD8H,OD5H,OD3H,OD1H,OCEH,OCCH,OC9H,OC7H,OC4H,OC1H,0BFH
OBCH,OB9H,OB6H,OB3H,OB1H,OAEH,OABH,OA8H,OA5H,OA2H,09FH,09CH

•byte
• byte
•byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte

099H,096H,093H,090H,08CH,089H,086H,083H,080H,07DH,07AH,077H
074H,070H,06DH,06AH,067H,064H,061H,05EH,05BH,058H,055H,052H
04FH,04DH,04AH,047H,044H,041H,03FH,03CH,039H,037H,034H,O32H
02FH,02DH,02BH,028H,026H,024H,022H,020H,OlEH,OlCH,OlAH,018H
016H,015H,013H,OllH,OlOH,OOFH,OODH,OOCH,OOBH,OOAH,008H,007H
006H,006H,005H,004H,003H,003H,002H,002H,002H,OOlH,OOlH,OOlH
OOlH,OOlH,OOlH,OOlH,002H,002H,002H,003H,003H,004H,005H,006H
006H,007H,008H,OOAH,OOBH,OOCH,OODH,OOFH,OlOH,OllH,013H,O15H
016H,018H,OlAH,OlCH,OlEH,020H,022H,024H,026H,028H,02BH,02DH
02FH,032H,034H,037H,039H,03CH,03FH,041H,044H,047H,04AH,O4DH
04FH,052H,055H,058H,05BH,05EH,061H,064H,067H,06AH,06DH,07OH
074H,077H,07AH,07DH
.

• END

~9

490

~ ZiIffi

Application Note

August 1987

GENERATING DTMF TONES
WITH THE ZILOG SUPERB
by Charles M. Link, II
In the previous article, a sine wave generation example
was .demonstrated. Sine waves are great, but, sometimes, more complex waveforms must be generated.
One of the most widely used complex waveforms is the
DTMF tone. The DTMF tone is used on millions of
telephones under the AT&T registered name "TOUCH
TONE". Generally, telecommunications designers purchase one of the many DTMF encoder chips and hang it
beside a microprocessor. This application article contains an example of a DTMF generation scheme that
produces nearly as pure and probably as accurate a tone
as the external chip method.
Generating sine waves requires some type of digital-toanalog converter to interface to the microprocessor. For
this application, a DAC-08 is used. This DAC-08 is tied
to port 4 of the SuperS. Since it is assumed that the
reader has access to the previous article, a detailed
description of the hardware will be left to that article.
Why not use the DTMF generator chip, when it might be
just as inexpensive as the DAC- 08? The answer is that
the DTMF generator chip requires an extemal crystal or
clock, and it might not be convenient to pick a processor
frequency that is a direct multiple of the one required by
the generator. The second and more important reason is
that· the DAC-08 can be used to generate other call
progress tones such as ringback and busy, or any other
complex waveform.
.
Since the previous article discussed the method for
generating sine wave tones, this article will only discuss
how to turn that into the DTMF tone. The DTMF tone is
actually a combination of two tones, hence, the name
DUAL TONE MULTI-FREQUENCY. The tones are arranged such that each row and each column has a corAn
responding single frequency tone assigned.
additional, normally unseen column, contains an eighth
tone frequency. A simple diagram below shows the arrangement.
DTMF TONE ASSIGNMENT

697
770
852
941

1209

1336

1477

1633

1
4

2
5
8

3
6

A
B

9
#

C

7

o

The method used to combine the two tones into one
single complex waveform is simple: add the two individual tones together. Adding the tones together is
usually what happens when analog circuitry produces the
DTMF tone. In fact, most of the DTMF encoder chips
usually add the tones together either internally or externally to produce the single waveform.
Generating the two tones is no task for the Super8
microcomputer. Just set up two current table offset
values and two different frequency increments. At each
periodic interrupt the 16 bit frequency increment is added
to the current table offset producing a new current table
offset. The upper byte of .each current table offset (one
for the row frequency and one for the column) is used as
a pointer into a 256 byte table. The sine values retrieved
from the table are then added together and loaded into
theDAC-OS.
Since the DAC input of OOH corresponds to an output of

o volts and the input of OFFH corresponds to an output of

5 volts, adding two values that could possibly be OFFH
presents a problem. Since two sines must add to no
more 5 volts, the maximum for one Single sine value
must be one half of 5 volts, or SOH. The sine table has
been adjusted so that the 2.5 volt value is mid-range.
The maximum or mimumum for the sine wave is plus or
minus 1.25 volts.
The interrupt service routine is almost exactly the same
as the interrupt routine for the sine wave, except that two
sine waves are calculated. The final values are added
together and stored for the first instruction of the next interrupt. In order to Change tones, or disable the tone
generation, additional software logic could enable or disable the interrupt, and modify the two values "CINCR",
and "RINCR".
.
It is clear from the example, that ringback, busy, MF, and
other signaling tones can be easily generated without additional hardware. Increased sampling rates could be
used to generate tones of much higher frequencies and
accuracies. The accuracy, using the above method and
sampling frequencies, is much less than one percent, totally suitable for telecommunications needs.

D

491

Super8 Example ~F Genera~ion

.TITLE
;=
;;=
;;=
:=
;i--

;=

TITLE:
DATE:
PURPOSE:

ASSEMBLER:
PROGRAMMER:

DTMF.S
JUNE 17, '1986
TO DEMONSTRATE USING SUPER8
TO GENERATE HIGH QUALITY DTMF
WAVES.
DAC-08 ON PORT 4
SEE DIAGRAM
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, I I

• PAGE

;set,maxlmum paqe size to 55 lines

HARDWARE:

;_=c=======_____________________ ============================

55

;

i***************************************************** ******.
1;*

;*

REGISTER EQUATE TABLE

*
*
*

:*
:***********************************************************,
;

;column tone equates
CINCR: .equ
rrO
CINCRH: .equ
rO
CINCRL: .equ
r1
CFINCR: .equ
rr2
CFINCH: .equ
r2
CFINCL: .equ
r3
POINT: .equ
rr4
POINTH: .equ
r4
POINTL: .equ
r5
;row tone equates
RINCR: .equ
rr6
RINCRH: .equ
r6
RINCRL:.equ
r7
RFINCR: .equ
rr8
RFINCH: •equ
r8
RFINCL:.equ
r9
CVAL:
.equ
r10
RVAL:
.equ
rll

;current increment in sine table
;hiqh byte of current increment value
;low byte of current increment value
;increment in sine table for frequency
;hiqh byte of frequency increment ,value
;low byte of frequency increment value
;pointer into sine table
;hiqh byte of sine table pointer
;low byte of sine table pointer
;current increment in sine table
;hiqh byte of current increment value
;low byte of current increment value
;increment in sine,table for frequency
;hiqh byte of frequency increment value
;low byte of frequency increment value
;current value to output to DAC-08
;current row value
.

;

;***********************************************************

*

;*

GENERAL EQUATES
*•
;*
;***********************************************************
XTAL:
.equ
12000000
;crystal t:req in he'rtz
SAMPLE: .equ
8000
;sample frequency in hertz
CTVAL:
.equ
XTAL/4/SAMPLE
;counter load value
TABSTP: .equ
256
;number of values in sine table
CFREQ: .equ
1209
;desired column frequency
RFREQ: .equ
697
;desired row frequency
CFREQI: .equ
(TABSTP*256*CFREQ)/SAMPLE
RFREQI: .equ
(TABSTP*256*RFREQ)/SAMPLE
;note dtmf frequencies are 697,770,852,941,1209,1336,1477,1633
;

;.**********************************************************
;*
*
;*
INTERRUPT VECTOR TABLE
*

*

; * .
,
;~*************************~************************** ******
;

INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR1o.:

492

•WORD
•WORD
•WORD
• WORD ,
•WORD
• WORD
• WORD
• WORD
• WORD
•WORD
• WORD

INTRET
INTRET
INTRET
INTRET
INTRET ,
INTRET
TIMBRO
INTRET
INTRET
JNTRET
INTRET

;this area should always be defined
las it reserves the lower 32 bytes
;for 'the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.

INTR11 :
INTR12:
INTR13:
INTR14:
INTRi5:

• WORD
.WORD
.WORD
.WORD
.WORD

INTRET
INTRET
INTRET
INTRET
INTRET

i***************************************************** ******

*

i*

;*

*

START OF PROGRAM EXECUTION

*

:*

i***************************************************** ******
START:

jr
• ASCII

START1: di
sbO
ld
l.d
ld
ld
ld

;program execution unconditionally
;begins at this location after reset
land power up.
'REL 0 6/16/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register bank 0
EMT,#OOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
land DMA internal
;address begins at OOOOh, set upper byte
PO,/IOOH
POM, #11111111B ;select all lines as ·address
;enable port 0 as upper 8 bits address
PM,#00110000B
H1C,#00000000B ;handshake not enabled port 0
START1

;port 1 is defined in romless part as address/data.
;here to initialize that port

it is not necessary

ld
ld
ld
ld
ld
ld

P2,#00H
P3,#00H
P2AM,#10101010B
P2BM,#10101010B
P2CM, #10101010B
P2DM,#10101010B

;port 2 outputs low
;port 3 outputs low
;p30,31,20,21 as output
;p32,33,22,23 as output
;p34,35,24,25 as output
;p36,37,26,27 as output

ld
ld
ld

P4,#10000000B
;set midpoint for DAC inputs
P4D,#0000DOOOB ;set all bits of P4 as output
P40D,#00000000B ;active push/pull

;

;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld

RPO,/IOCOH
RP1,#OC8H
SPL,#OFFH

;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general .purpose
;storage.

;now clear the internal memory and stack area
ZERO:

ld
clr
dec
jr
clr

SPH, #OFFH
@SPH
SPH
nz,ZERO
@SPH

;point to top of general purpose register
izero it
;do it until register set is all cleared
;zero last register

;now everything except working registers is cleared
;cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
sb1
ld
ld
ld
sbO
ld

SYM,#OOOOOOOOB
IPR, /l00000010B

;disable fast interrupt response
.; interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,#00000100B ;enable only interrupt 2
;select bank 1
COTCH,/lAHB(CTVAL)
;high byte of time constant
COTCL,/lALB(CTVAL)
;low byte of time constant
COM,#00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,#10100101B ; continuous , count down, load counter,
;zero count interrupt enable, enable counter

:timer is initialized, now- lets enable interrupts and wait
Idw
eINeR, #1
;start column at beginning of sine table
Idw
RINCR, '1
;start row at beginning of sine table

493

this example loads the tones for digit 111
user software would, of course have to manipulate these registers for
proper tone control
Idw
Idw
Idw
Id
WAIT:

CFINCR, #CFREQI
RFINCR, #RFREQI
POINT, #SINTAB
CVAL, #080H

; load column frequency increment
'load row frequency increment
;pointer points to sine table
; initial value to prevent glitch ,at star1
; enable interrupts

WAIT

;loop back

ei
nop
nop
nop
nop
jr

;Timer interrupt. Occurs SAMPLE times per second
1interrupt outputs value to OAC-08 and then determines value for next
1 interrupt.
This assures no bit jitter.
;

p4,CVAL

TlMERO: Id

ref

:write new value to OAe-os
;clear carry flag
; find next position in sine table
1by adding' frequency offset to last position
;set 'new, painter into sine table
;ge.t value from sine table
:find next position in sine table
;by adding frequencty offset to last position
;set new pointer into sine table
RVAL,@POINT
;get second value from sine table
<:VAL,RVAL
; f6rm. a complex fWaveform from two sine values
COCT,#OOOOOOlOB ; reset end of count interrupt
; and return from interrupt

CINCRL, CFINCL
CINCRH, CFINCH
POINTL, CINCRH
CVAL, @POINT
RINCRL,RFINCL
RINCRH,RFINCH
'POINTL, RINCRH

add

ade
Id

Ido
add

ade
Id

Ide
add

or
INTRET: iret

; ••••••••• * •• * .**. * * *. * ••• *. * *.* ••••• ** * ••• *. * * * •.• * •••• **. * *

,*

;*

SINE WAVE LOOKUP

;.

*

*

; • * *••• *••• * * •• ** * * * * * *. * ••• * * * * ** ** * * * * **. * ** * * * *. * *. ** ** ••

;sine table fQr DTMF' generation using DAC-08. Table based upon
;case of waveform consisting of two sine waves summed to provide a single
:coIPpl.ex waveform with minumum amplitltude = 0 volts and maximum
:amp:J,.itittlde 3:11 5 volts. OAC-OS input for 0 vo:lts = OOH
:5 volts = OFFH. 80th waves must total no more than OFFH, therefore
;maximum for one wave must be 1/2' 5 volts or 080H.
;Table generated using following BASICA program,
;then typed into program.

,

10
20
30
40
50
60

CLS
PI=3.141593
FOR 1=0 TO 255
C=360/256
O';C*I
E=0*PI/180
79 F=SIN(E)
80 G=F*63
~O

H-64+G

100
110
120
130
140
150

J=CINT(H)
A$=HEX$ (J)
PRINT A$
LPRINT A$
NEXT
END

;clear screen
;define PI
; 2 56 total values
;define basic interval value
;value from zero on sine wave
; figure sine for interval from 0
; sine range should be from -63 to 63
;make result from 0 to 127
; round to nearest integer
; convert to hex
;on screen
ion printer
;do next inverval

;*note':'"'remove comments, BASICA will not accept; as comment delimiter

,

SINTAB:, .ORG

• byte
• byte
• byte
• byte
• byte

• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
. byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• END

494

0400H
;begin sine table on even byte boundary
040H, 042H, 043H, 045H, 046H, 048H, 049H, 048H, 04CH, 04EH, 04FH, 051H
052H, OS4H, 055H, OS7H, 058H, OSAH, 058H, OSCH, 05EH, 05FH, 060H, 062H
~63H, 064H, 066H, 067H, 068H, 069H, 06AH, 06BH, 060H, 06EH, 06FH, 070R
071H, 072H, 073H, 074H, 074H,075H, 076H, 077H, 078R, 078~, 079H, 07AH
07AR, 078H, 078H, 07CH, 07CH, 070H, 070H, 070H, 07EH, 07EH, 07EH, 07FH

07FH, 07FH,07FH, 07FH,07FH,07FH,07FH,07FH,07FH,07FH,07EH ,07EH
07EH,07DH,07DH,07DH,07CH,07CH,07BH,07BH,07AH,07AH,079H,O7SH
07SH,077H,076H,075H,074H,074H,073H,072H,071H,070H,06FH,06EH
06DH,06BH,06AH,069H,06SH,067H,066H,064H,063H,062H,060H,05FH
05EH,05CH,05BH,05AH,05SH,057H,055H,054H,052H,051H,04FH,04EH
04CH,04BH,049H,04SH,046H,045H,043H,042H,040H,03EH,03DH,03BH
03AH,03SH,037H,035H,034H,032H,031H,02FH,02EH,02CH,02BH,029H
02SH,026H,025H,024H,022H,021H,020H,OlEH,OlDH,OlCH,OlAH,019H
OlSH,017H,016H,015H,013H,012H,OllH,OlOH,OOFH,OOEH,OODH,OOCH
OOCH,OOBH,OOAH,009H,OOSH,OOSH,007H,006H,006H,005H,005H,004H
004H,003H,003H,003H,002H,002H,002H,OOlH,OOlH,OOlH,OOlH,OOlH
OOlH,OOlH,OOlH,OOlH,OOlH,OOlH,002H,002H,002H,003H,003H,003H
004H,004H,005H,005H,006H,006H,007H,OOSH,OOSH,009H,OOAH,OOBH
OOCH,OOCH,OODH,OOEH,OOFH,OlOH,OllH,012H,013H,015H,016H,017H
OlSH,019H,OlAH,OlCH,OlDH,OlEH,020H,021H,022H,024H,025H,026H
02SH,029H,02BH,02CH,02EH,02FH,031H,032H,034H,035H,037H,03SH
03AH,03BH,03DH,03EH

~ ZiIm

Application Note

August 1987

A SIMPLE SERIAL TO

PARALLEL CONVERTER
USING THE ZILOG SUPERB
by Charles M. Link, "

The Zilog SuperS has many on-board peripherals that
provide multiple user applications. Earlier articles have
dernc:instrated simple application "stubs" or short test
programs. This article and the next article demonstrate a
useful application for the SuperS. Ahhough it
underutilizes the SuperS's power, the simple serial to
parallel converter in this application and the print buffer in
the next application demonstrate the ease at whiCh
applications are developed with the SuperS.

Hardware for this application is fair1y simple. Port 4 is
buffered and hooked to the data lines, as shown, to
interface to a centronics type printer connector. The
strobe from P25 provides the strobe (pin 1) to the printer.
The acknowledge line from the printer is inverted and.
tied to P24 of the SuperS. The busy signal from the
printer is buffered and tied to P23 of the SuperS. The
. design was tested on an Okidata printer and is not
guaranteed to work on all printers.

The Zilog SuperS has several features that enhance its
use as a communication controller. The interrupt or DMA
driven serial port are helpful, but the handshaking
parallel Pt:'rts finish the job. In the serial to parallel
converter, the 256 byte internal register memory is used
as a small circular queue.

Software is fair1y straightforward. The serial port is
initialized just like it was in the application article on the
interrupt driven serial port. Port 4 must be set-up as
outputs with activj:l push-pull drivers. Port 2, bits 3 and 4,
are set up as input with P24 set to enable interrupts. P25
is set as output and handshake 0 is set in HOC to provide
a strobe of 16 clock periods in length.

• TITLE

Sample Zi10g Super 8 Serial to Parallel Converter

TITLE:
DATE:
PURPOSE:

;;,;=

;;;

.

;;=

;;=
;=

ASSEMBLER:
PROGRAMMER:

SElU'AR.S
JULY 17, 1986
TO DEMONSTRATE INTERRUPT
DRIVEN SERIAL PORT IN A
REALISTIC APPLICATION.
THIS APPLICATION RECEIVES
SIMPLE SERIAL DATA A SENDS IT
OUT THE PARALLEL PORT TO A
PRINTER.
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II

J-================-----------=---==-========================

• PAGE

55

;set maximum page size to 55 lines

;******.~*********************************************~*****

:*

GENERAL EQUATES

;*

;*

'

*

*

*

;***********************************************************,
;
CR:
LF':

.equ
.equ

OdH
OaH

;carriage return
;line feed

,
;***********************************************************
; * '
*
;*
REGISTER EQUATE TABLE
*
i*

*

;***********************************************************
;

;working register equates
INPNT: .equ
R3
;input character pointer
OUTPNT: .equ
R4
;output character pointer
495

MPTR: '.equ
ACKB:
.equ
, ACKBIT: .equ

RR6
RS

o

me~sage pointer for external memory
byte containing acknowledge bit
bit set = no acknowledge yet
bit clear = not. waiting on acknowledge

;*********************.*************************************
;*
*
;*
INTERRUPT VECTOR ,TABLE
*
:*
*
;***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTRS:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
INTR11:
INTR12:
INTR13:
INTR14:
INTR1S:

,

•WORD
• WORD
• WORD
• WORD
• WORD
.,WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
.,WORD
•WORD

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET,
INTRET
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
INTRET
ACKSTB
INTRET

;this area should always be defined
las it reserves the lower 32 bytes
;for the interrupt table. 'the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.

;receive data interrupt

;acknowledge strobe interrupt

:***********************************************************
;*

;*

START OF

PROG~

*

*

EXECUTION

:*
*
;**********************.************************************
START:

jr
•ASCII

START1: di
sbO
ld

,

ld
ld
ld
ld

START1

;program execution unconditionally
;begins at this location after reset
land power up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register' bank 0
,
EMT,/lOOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
land DMA internal
PO,iOOH
;address begins at OOOOh, set upper byte
POM, #11111111B ;select all lines as address
PM,iOO110000B
tenable port 0 as upper 8 bits address
H1C,ilOOOOOOOOB ;handshake not enabled port 0

;port 1 is defined in romless part as address/data.
there to initialize that port
ld
ld
ld

it is not necessary

ld
ld
ld

P2,#00100000B
;port 2 outputs low, except strobe bit
P3,IIOOH
;port 3 outputs low
P2AM,/110001010B ;p31,20,21 as output,p30 input
lit is necessary here to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM,/Il0100010B ;p32,33,22 as output, 23 as input
P2CM,/IIOIOIOOIB ;p34,3S,2S as output, 24 as input, interrupt en
P2DM,/IlOIOIOIOB ;p36,37,26,27 as output

ld
ld
ld
ld

P4,II00000000B
P4D,iOOOOOOOOB
P40D,iOOOOOOOOB
HOC,#l1110001B

;clear port 4 register
;set all bits of P4 as outputs
;active push/pull
;handshake enable for port 4, 16 clock pulse

"
;basic
Super a I/O is initialized, now internal registers
ld
ld
ld

RPO,/IOCOH
RP1,iOC8H
SPL,/IOFFH

;set working register low to lower a bytes
;set working register high to upper a bY,tes
;set stack pointer to start at top of set two
;note here that only lower a,bits are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
; storage.
'

;now clear the internal memory and stack

496

~rea

ZERO:

ld
clr
dec
jr
clr

SPH,#OFFH
@SpH
SPH
nz,ZERO
@SPH

;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register

now everything except working registers is cleared
cpu and memory now initialized, set up timer for real time clock
ld
ld

SYM,#OOOOOOOOB
IPR,1/10111111B

ld

IMR,#OlOlOOOOB

;disable fast interrupt response
;interrupt priority
;IRQ6>IRQ7>IRQ5>IRQ4>IRQ3>IRQ2>IRQ1>IRQO
;rx interrupts, acknowledge strobe

timer is set, now lets initialize the UART for polled operation
sbl
ld

ld
ld
ld

sbO
ld,
ld
ld

;bank 1
UMA,#01110000B
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH,#AHB(00009)
;high byte of time constant
UBGL,#ALB(00009)
;low byte of time constant
UMB,#00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
lis disabled
;select bank 0
UTC,#10001000B ;select p31 as transmit data out, 1 stop bit
land transmit enable
UIE,#OOOOOOOlB ;receive interrupts, no DMA
URC,#00000010B ;enable receiver

UART is initialized, reset' acknowledge bit and begin

WAIT:

WAIT1:

SENDM:

bitr
ld
ei
ldw
call
ld
ld
call
jr

ACKB,#ACKBIT
;reset acknowldege bit if set
P2BIP,#00000001B
;reset interrupt input flip-flop
;enable interrupts
;point to message
MPTR,#MSG
;send the message
SENDM
INPNT,#O
;set input pointer to register 0
;set output 'pointer to register 0
OUTPNT,#O
;send any characters in buffer
SNDBUF
;loop back
WAIT1

tm
jr
btjrt

P2,#00001000B
;printer busy
nz,SENDM
;wait for printer unbusy
SENDM,ACKB,#ACKBIT
;see if the acknowledge has occurred
;from possible last byte
ACKB,#ACKBIT
;set acknowledge bit before writing to output
rO,@MPTR
;get the character
P4,rO
;send to printer
;allow 18 clocks for strobe'

bits
ldci
ld
nop
nop
nop
cp
jr
ret
SNDBUF: cp
jr
ret
sell
tm
jr
btjrt
di
bits
ld
tm

rO,t/'$'
ne,SENDM

;last character?
;loop back for next

INPNT,OUTPNT
ne,SC1

;compare inpointer to outpointer
;send character if any to send,
;otherwise return
P2,#00001000B
;printer busy?
nz,SC1
;if so, wait until it is not busy
SC1,ACKB,#ACKBIT
;see if acknowledge has occurred
;from possible last byte
ACKB,#ACKBIT
P4,@OUTPNT
P2,#00000001B

;set acknowledge bit before writing to output
;send the character

497

HON:

jr
ld
xor
cp
jr
and
nop
inc
ei
ret

z,HON
rO,OUTPNT
1;0,/I10000000B
INPNT,rO
ne,HON
P2, #11111110B

;if host is on
;get the output pointer
;add 128 to it
;turn host back on when 128 bytes left in buf
;otherwise keep sending
;host back on

OUTPNT

;bump pointer
;to make sure pointer not changed

;send character in rO
SENDC: tm
UTC,'00000010B ;transmit buffer empty yet
jr
z,SENDC
;if not, wait until it is
ld
;load the character into the transmitter
UIO,rO
ret
;receive character available interrupt
RXDATI: ld
rO,UIO
;get input from console
;remove upper parity bit
and
ro,#7fH
call
SENDC
;echo to console
ld
t\INPNT,rO
;save th~ character
;bump input pointer
inc
INPNT
cp
INPNT,OUTPNT
;has the input made a complete loop?
jr
ne,RXIT

.

;receive character buffer full, stop sending device

or
INTRET:
RXI'D-:
iret

P2,#00000001B

;raise DTR to stop host sending

ACKSTB: tm
bitr

P2,#00010000B
ACKB,#ACKBIT

;is line low or high now
;reset acknowledge bit in

ACKS1:

tm
jr
ld
iret

P2,#00010000B
;test ack bit
Z,ACKS1
;wait h~re till end of strobe
P2BIP,#00000001B
;reset p24 interrupt pending register
;and return

MSG:

.ASCII
.ASCII

CR,LF,'super8 serial/parallel test program.',CR,LF
'Second line test data',CR,LF,'$'

regist~r

.END

.TITLE

Sample Zilog super 8 Serial to

Parall~l

Converter with XON/XOFF

;===========================================================

;=
;=
;=

TITLE:
DATE:
PURPOSE:

;=

;=

;=
;=

;=
;=
;=
;=
;=

ASSEMBLER:
PROGRAMMER:

SERPARl.S
JULY 17, 1986
TO DEMONSTRATE INTERRUPT
DRIVEN SERIAL PORT IN A
REALISTIC APPLICATION.
THIS APPLICATION RECEIVES
SIMPLE SERIAL DATA A SENDS IT
OUT THE PARALLEL PORT TO A
PRINTER. FLOW CONTROL IS BY
XON/XOFF COMMANDS ON THE BACK
CHANNEL TO THE HOST
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II

;===========================================================

• PAGE
55
;set maximum page size to 55.lines
;***********************************************************

:*
;*

GENERAL EQUATES

;*

*
*

*

;**~************************************************** ******

CR:
LF:

498

.equ
.equ

OdH
OaH

;carriage return
;line feed

XON:
XOFF:

.equ
.equ

11H
13H

:control-Q or DC1
:control-S or DC3

:

:**********************************************-************
:*

;*

*

*
*

REGISTER EQUATE TABLE

:*

:***********************************************************

:
:working reqister equates
,
INJ;>NT: • equ
R3
: input c;:haracter pointer
OUTPNT: .equ
R4
;output character pointe,r
MPTR:
.equ
RR6
:messaqe pointer for external memory
ACKB:
.equ
R5
;byte containinq acknowledqe bit
ACKBIT': .equ
0
;-bit set - no acknowledqe yet
Ibit clear - not waitinq on acknowledqe
XBIT:
.equ
1
;XOFF send to host
;

;****************************************************.******
;*

1*

INTERRUPT

VE~R

*
*

TABLE

*

;*

;*********.***~**** •• ****~**************************** ******

INTRO:
INTRl:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTRIO:
,INTR11:
INTiu2:
INTR13:
INTR14:
INTR15:

• WORD

• WORD
• WORD
• WORD
• WORD
•WORD
• WoRD
• WORD
• WORD
•WORD
• WORD
• WORD
• WORD• WORD
• WORD
•WORD

INTR!T
INTR!T

INTRET
INTR!T

INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
INTRET'
ACKSTB

;this area should always be defined
las it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.

;receive data interrupt

;acknowledqe strobe interrupt

INTR!T

;

,

1***********************************************************
;*
*
1*
START OF PROGRAM EXECUTION
*
1*
*

\

:***********************************************************

START:

di
jr

;for emulation if nothinq else
;proqram execution unconditionally
;beqins at this location after reset
land power up.
•ASCII _ 'REL 0 7/17/86' ;jump around optional ascii strinq
;containing release info, copyriqht, etc.
START1: sbO
;select reqister bank 0
ld
EMT,#OOOOOOOOB ;external memory timinqano wait input, normal
;memory timinq, no wait states, stack internal,
land DNA internal
:address beqins at OOOOh, set upper byte
ld
PO,#OOH
ld
POM, #11111111B ;select all lines as address
;enable port 0 as upper 8 bits address
ld
PM,'OO110000B
ld
H1C,#OOOOOOOOB ;handshake not enabled port 0
START1

;

;port 1 is defined in romless part as address/data.
;here to initialize that port
ld
ld
ld

it is not necessary

ld
ld
ld

;port 2 outputs lOW, except strobe bit
P2,'OO100000B
;port 3 outputs low
P3,'OOH
P2AM,#loOOlOlOB ;p31,20,21,8S output,p30 input
,
lit is necessary here to confiqure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM,110100010B :p32,33,22 as output, 23 as input
P2CM,l10101001B ;p34,35,25 as output, 24 as input, interrupt en
P2DM,110101010B ;p36,37,26,27 as output

ld
1d

P4,#OOOOOOOOB
P4D,'OOOOOOOOB

;clear port 4 reqister
;set all bits of P4 as outputs

499

ld
ld

P400,#00000000B ;active push/pull
HOC,#11110001B ;handshake enable for port 4, 16. clock pulse

basic Super 8 I/O is initialized, now internal registers
ld
ld
ld

RPO,#OCOH
RP1,lIOC8H
SPL, lIOFFH

;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set. two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
;storage.

;now clear the internal memory and stack area
ZERO:

ld
c1r
dec
jr
clr

SPH,#OFFH
@SPH
SPH
nz,ZERO
@SPH

;point to top of general purpose register
Izero it
;do it until register set is all cleared
;zero last register

;now everything except working registers is cleared
;cpu and memory now initialized, set up timer for real time clock
ld
ld

SYM,#OOOOOOOOB
IPR, #10111111B

ld

IMR,#01010000B

;disable fast interrupt response
;interrupt priority
;IRQ6>IRQ7>IRQS>IRQ4>IRQ3>IRQ2>IRQ1>IRQO
;rx interrupts, acknowledge strobe

;

;timer is set, now lets initialize the UART for polled operation
sb1
ld

ld
ld
ld

sbO
ld
ld
ld

;bank 1
UMA, #01110000B
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH, #"HB(00009)
;high byte of ti'me constant
UBGL,#"~B(00009)
;low byte of time constant
UMB,#00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
lis disabled
;select bank 0
uTC,#10001000B ;select p31 as transmit data out, 1 stop bit
land transmit enable
UIE,#Q0000001B ;receive interrupts, no OMA
URC,#00000010B ;enable receiver

UART is initialized, reset acknowledge bit and begin

WAIT:

WAIT1:

SENOM:

bitr
bitr
ld
ei
ldw
call
ld
ld
call
jr

;reset acknowldege bit if set
;reset XON/XOFF bit
P2BIP,#00000001B
;reset interrupt input flip-flop
;enable interrupts
MPTR,#MSG
;point to message
SENOM
;send the message
INPNT,#O
;set input pointer to register 0
OUTPNT,#O
;set output pointer to register 0
SNOBUF
;send any characters in buffer
WAIT1
;loop back

tm

P2,#00001000B
;printer busy
nZ,SENOM
;wait for printer unbusy
SENOM,ACKB,'ACKBIT
;see if the acknowledge has occurr~d
;from possible last byte
;set acknowledge bit before writing to output
ACKB, 'ACKBIT
;get the character
rO,@MPTR
P4,rO
;send to printer
;allow 18 clocks for strobe

jr
btjrt
bits
ldci
ld
nop
nop
nop
cp
jr
ret
500

ACKB,#ACKBIT
AC~B,#XBIT

rO,f'$'
ne,SENOM

;last character?
;loop back for next

,
:timer is initialized, now lets enable interrupts and wait
:start column at beginning of sine table
ldw
CINCR,II1 .
:start row at beginning of sine table
ldw
RINCR,iIl
;this example loads the tones for digit 'I'
:user software would, of course have to manipulate these registers for
:proper tone control

WAIT:

ldw
ldw
ldw
ld
ei
nop
nop
nop
nop
jr

CFINCR,IICFREQI
RFINCR,IIRFREQI
POINT,IISINTAB
CVAL,j/080H

:load column frequency increment
:load row frequency increment
:pointer points to sine table
:initial value to prevent glitch at start
:enable interrupts

:loop back
WAIT
:
:Timer interrupt. Occurs SAMPLE times per second
:interrupt outputs value to DAC-08 and then determines value for next
; interrupt. This assures no bit jitter.
TlMERO: ld
rcf
add
adc
ld
ldc
add
adc
ld
ldc
add
or
INTRET: iret

,

;write new value to DAC-08
;clear carry flag
CINCRL,CFINCL
;find next position in sine table
:by adding frequency offset to last position
CINCRH,CFINCH
;set new pointer into sine table
POINTL,CINCRH
;get value from sine table
CVAL., @POINT
;find next position in sine table
RINCRL,RFINCL
;by adding frequencty offset to last position
RINCRH,RFINCH
;set new pointer into sine table
POINTL,RINCRH
;get second value from sine table
RVAL,@POINT
;form a complex waveform from two sine values
CVAL,RVAL
COCT,1I00000010B ;reset end of count interrupt
land return from interrupt
p4,CVAL

1***********************************************************
i*

;*

SINE WAVE LOOKUP

*

*

*

i*

i***************************************************** ******

;sine table for DTMF generation using DAC-08. Table based upon
:case of waveform consisting of two sine waves summed to provide a single
:complex waveform with minumum amplititude = 0 volts and maximum
;amplititude = 5 volts. DAC-08 input for 0 volts = OOH
;5 volts = OFFH. Both waves must total no more than OFFH, therefore
;maximum for one wave must be 1/2 5 volts or 080H.
;Table generated using following BASlCA program,
;then typed into program.
10 CLS
20 PI=3.141593
30 FOR 1=0 TO 255
40 C=360/256
50 D=C*I
60 E=D*PI/180
70 F=SIN(E)
80 G=F*63
90 H=64+G
100 J=CINT(H)
110 A$=HEX$(J)
·120 PRINT A$
130 LPRINT A$
140 NEXT
150 END

;clear screen
idefine PI
:256 total values
;define basic interval value
;value from zero on sine wave
;figure sine f~r interval from 0
;sine range should be from -63 to 63
;make result from 0 to 127
;round to nearest integer
;convert to hex
ion screen
Ion printer
;do next inverval

;*note-remove comments, BASlCA will not accept ; as comment delimiter
SINTAB: .ORG
• byte
. byte
• byte
• byte
. byte

0400H
;begin sine table on even byte boundary
040H,042H,043H,045H,046H,048H,049H,04BH,04CH,04EH,04FH,051H
052H,054H,055H,057H,058H,05AH,05BH,05CH,05EH,05FH,060H,062H
063H,064H,066H,067H,068H,069H,06AH,06BH,06DH,06EH,06FH,070H
071H,072H,073H,074H,074H,075H,076H,077H,078H,078H,079H,07AH
07AH,07BH,07BH,07CH,07CH,07DH,07DH,07DH,07EH,07EH,07EH,07FH

501

..

SNDBUF::, cP
SC1:

'jr
ret
tm~

jr
btjrt

HON:

di
bits
ld
btjrf
ld
xor
cp
jr
ld
call
bitr
nop
inc
ei
ret

compare inpointer to outpointer
send character if any to send
otherwise return
P2,#00001000B
printer busy?
nZ,SC1
if so, wait until it is not busy
SC1,ACKB,#ACKBIT
;see if acknowledge has occurred
;from possible last byte
INPNT,OUTPNT
ne,SCl

ACKB, #ACKBIT
P4,@OUTPNT
HON,ACKB,#XBIT
rO,QUTPNT
rO,#lOOOOOOOB
INPNT,rO
ne,HON
rO,XON
SENDC
ACKB, #XBIT

;set acknowledge bit before writing to output
;send the Character
;host is still sending
;get the output pointer
;add 128 to it
;turn host back on when 128 bytes left in buf
;otherwise keep sending
';send XON to host to start it sending again

OUTPNT

;bump pointer
Ito make sure pointer not changed

;reset XOFF bit

;

;send character in rO
SENDC: tm
UTC,#OOOOOOlOB ;transmit buffer empty yet
jr
z,SENDC
;if not, wait until it is
ld
UIO,rO
;load the character into the transmitter
ret
;receive character available interrupt
RXDATI: ld
rO,UIO
;get input from console
and,
rO, #7fH
;remove upper parity bit
call
SENDC
;echo to 'console
ld
@INPNT,rO
;save the character
inc
INPNT
;bump input pointer
ld
rO,INPNT
;get the input pointer
add
rO,#5
;allow 5 characters after XOFF
;has the input made a complete loop?
cp
rO,OUTPNT
jr
ne,RXIT
;

;receive character buffer full, stop sending device
ld
call
bits

rO,#XOFF
SENDC
ACKB,#XBIT

;send XOFF to host
;send it
;set the XOFF bit

ACKSTB:'tm
bitr

P2,#00010000B
ACKB,#ACKBIT

lis line low or high now
;reset acknowledge bit in register

ACKS1:

tm
jr
ld
iret

P2,#00010000B
;test ack bit
z,ACKS1
;wait here till end of strobe
P2BIP,#OOOOOOOlB
;reset p24 interrupt pending register
land return

.ASCII
.ASCII

CR,LF,'super8 serial/parallel test program.',CR,LF
'Second line test data',CR,LF,'$'

INTRET:
RXIT:
iret

;

MSG:

• END

502

~ ZiIm

Technical Manual

Super8™ Microcomputer

503

Contents
Olapter 1. Super8 Overview

1.1
1.2
1.3
1.4
1.5

1

Introduction
Features
Basic Microcomputers
Proto pack Microcomputers
ROMless Microcomputers

508
508
508
508
508

D"oapter 2. Architectural Overview

2

2.1 Introduction
2.2 Address Spaces
2.3 Register File •

2.4

2.5

2.6

509
509
510

2.3.1 Register Pointer
2.3.2 Instruction Pointer

510
510 .

Instruction Set •

510

2.4.1 Addressing Modes
2.4.2 Dsta Types

510
510

I/O Operations

511

2.5.1 Interrupts
2.5.2 On-Chip Peripherals

511
511

Oscillator

. .

511

Olapter J. Address Spaces

..

.

3.1 Introduction
3.2 CPU Register File • •
3~3
System Registers and Mode and Control Registers
3.4 Program and Data Memory •
3.5 CPU and User Stacks
3.6 Instruction Pointer (IP)

.. .

3
512
512
515
515
517
518

D"oapter 4. Addressing ItJdes

4.1
4.2
4.3
4.4
4.'5
4.6
4.7
4.8

. . . . . .. ..

Introduction
Register Addressing (R)
Indirect Register Addressing (IR)
Indexed Addressing· (IA)
Direct Addressing CDA)
Indirect Addressing (IA)
Relative Addressing (RA)
Immediate Addressing (1M)

4
519
519
521
521
523
523
523
524

D"oapter 5. l;nstruction Set

5.1 Functional Summary
5.2 Processor Flags •
504

.

5
525
525

Contents (Continued)
5.3 Condition Codes • • • • • • •
5.4 Notation and Binary Encoding

5.5

528
528

5.4.1 Notational Shorthand
5.4.2 flag Settings

530
530

Instruction Descriptions and Formats

532

Chapter 6. Interrupts
6.1

6

Introduction

586

6.1.1
6.1.2
6.1.3
6.1.4
6.1.5

586
586
587
589
589

Sources
Vectors
Levels.
Enables
The Interrupt Routine

6.2 Fast Interrupt Processing • •
6.3 Clearing the Interrupt Source
6.4 Interrupt Control Registers •
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5

590
590
590

System Mode Register
Interrupt Request Registe,r
Interrupt Mask Register
Interrupt Priority Register
Fast Interrupt Status'Bit (FIS of Flags Register)

591
591
592
592
592

Interrupts and the DMA Channel

Chapter 7.

592

7

Reset end Clock

7.1 Reset
7.2 Clock
7.3 Test Mode
Chapter 8.
B.1
B.2
8.3
8.4
8.5
B.6
B.7

8.7.1
8.7.2
B. 7.3

593
599
599

8

I/O Port,s

Introduct ion
General Structure,
Port 0
Port 1
Ports 2 and 3
Port 4
Port Mode and Control Registers
Port Mode Reg ister • • •
Port 0 Mode Register ••
Por t 2/3 Mode Reg isters

5

"

600
600
600
600
601
602
602
602
603
603

505

B.7 •4 Port 2/3 Interrupt Pend ing Reg islers
B.7.5 Port 4 Direction Register
B.7.6 Port 4 Open-Drain Register

604
604

B.B Handshaking Channels

604

B.B.1 Pin Descriptions
B.B.2 Handshake Control Registers
Olapter 9.

9.1

606
606

9

Counter/Tilllers

Introduction

608

9.1.1 Bi-Value Moda
9.1.2 Capture
9.1.3 Extarnal Gate and Trigger

609
609

609

9.2 Counter/Timer tontrol and Mode Registers
9.2.1
9.2.2
9.2.3
9.2.4
Olapter 10.

10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.B
10.9

506

610

.

,

610
611
613
613

UART

10

Introduction
Transmitter •
Receiver
Wake-Up Feature
Auto-Echo/Loopback
Polled Operation
Baud-Rate Generator
UART Interface Pins
UART Control/Mode and Status Registers

614
614
614
615

10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
10.9.7
10.9.B
10.9.9

619
619
619
619
619
621
622
623
624

Dlapter 11.

11.1
11.2
11.3
11.4

Counter/Timer Control Registers
Counter/Timer- Mode Registers
Time Constant Register
Capture Register • • • • ••

UART Data Register (UIOT & UIOR)
Wake-Up Match Register (WUMCH) •
Wake-Up Mask Registar (WUMSK)
UART Receive Control Register (URC)
UART Interrupt Enable Register (UIE)
UART Mode A Register (UMA) ••
UART Transmit Control Register (UTC) •
UART Mode B Register (UMB) • '.
UART Baud-Rate Generator Time Constant Register (UBG)

617

618
618
619
619

11

DMA Olemal

Introduction
OMA Control Registers ••
DMA and the UART Register
DMA and the UART Transmitter

8

604

625
625
626
626

Contents (Continued)
1.1.5 OMA and Handshake Channel 0 • • • • •

626

11.5.1 OMA·Write (Input Handshake 0)
11.5.2 OMA Read (Output Handshake 0).

626
627

11.5.2.1 Fully Interlocked Mode
11.5.2.2 Strobed Mode • • • • •
Dlapter 12.

12.1
12.2
12.3
12.4
12.5
12.6

627
627

External Interface

Introduction • • • • • • •
Pin Descriptions • • • • •
Configuring for External Memory
External Stacks
Oata.Memory •
Bus Operation •

12
628
628
629
630
630
630

..

12.6.1 Address Strobe (AS)
12.6.2 Oata Strobe (OS) ••
12.6.3 External Memory Operations

631
631
631

12.7 Extended Bus Timing • • • • • • •

631

12.7.1 Software Pro·grammable Wait States
12.7.2 Slow Memory Timing.
12.7.3 Hardware Wait States
12.B Instruction Timing
Glossary . . . .

11

..

631
632
632
632
635

507

Chapter 1
SuperS Overview
1.1

INTRODUCTION

The Super8 family consists of basic microcomputers, protopack emulators, and ROMless microcomputers. The various family members differ in the
amount of on-chip ROM and the physical packaging.'
All of the Super8 family members offer a fullduplex universal asynchronous receiver/transmitter
(UART) with an on-chip baud-rate generator, two
16-bit programmable counter/timers, a direct
memory access (DMA) controller, and an on-chip
osci Hator.

1.2 FEATURES

1.' BASIC MICROCOMPUTERS
These parts are the core of the SuperB family of
products.
They have various amounts of maskprogrammable on-chip ROM, are suitable for high
volume applications, and require a single +5 Vdc
power supply.

1.4 PROTOPACK MICROCOMPUTERS
These parts function as emulators for the basic
microcomputer versions. ,They use the same package
and p:i.n-out as the basic microcomputer but a Iso
have a 2B-pin "piggy back" socket on the top into
which a ROM or EPROM can be installed, to replace
the on-chip ROM of the basic microcomputer.

Super8 microprocessor features inc lude:
This package permits th~ protopack to be used in
prototype and final PC boards while sti 11 permitting user program development.
When a final
program is developed, it can be mask-programmed
into the pr'oduction microcomputer device, directly
replacing the emulator.
The protopack parts are
also useful in situations where the cost of maskprogramming is prohibitive or where program flexibility is desired.

•

325 byte-wide registers, including 272 generalpurpose registers and 53 mode and control
registers

•

Full-duplex UART with special features

•

Up to 32 bit-programmable and B byteprogrammable I/O lines, with 2 handshake channels

•

Addressing of up to 128K byes of memory,

1.5 ROMlESS MICROCOMPUTERS

•

An interrupt structure that supports:

The ROMless microcomputers are similar to the
basic microcomputer parts, but have no internal
ROM. Port 1 is dedicated' as an B-bit address/data
bus and POO-P04 are dedicated address lines. Up to
64K bytes of external memory can be addressed by
configuring Port 0 as address bits. The address
capability can be doubled to 12BK bytes by
programming P35 of Port 3 as the Data Memory
select signal TIR. The two states of this signal
can be used with the 16-bit address bus to address
two separate banks of external memory, each with
up to 64K bytes.

•
•
•
•

27 interrupt sources
16 interrupt vectors (2 reserved for f~ture
versions)
8 interrupt levels
Servicing in 6 CPU clock cycles

•

Two Register 'Pointers that allow use of short
and fast instructions to access register groups
within 600 ns.

•

An instruction set that includes multiply and
divide instructions, Boolean and BCD operations

•

Additional instructions that support threadedcode languages, such as Forth

508

Chapter 2
Architectural Overview
2.1

INTROOUCTIIW

The SuperB is a versatile single-chip microcomputer that can be programmed for many different
memory and I/O configurations. This flexibility
has been achieved by merging a multiplexed
address/data bus with several I/O-oriented ports.
This provides the user with large amounts of
external memory while maintaining many I/O lines.
Figure 2-1 shows the SuperB block diagram.

2.2

•
•
•

Program memory (internal snd external)
Data memory (external)
Register file (internal)

A maximum of 64K bytes of program memory is
directly addressable. When present, internal
program memory normally consists of maskThe data memory space is 64K
programmed ROM.
bytes in si ze •
The ease of interfacing with external memory is
enhanced with options for programmable wait states
and half-speed memory timing, as well as an
optional external wait input.

ADDRESS SPACES

To provide for both 1/0 and memory intensive
applications, the SuperB supports three basic
address spaces:
I/O
(BIT PROGRAMMABLE)

I/O
(BIT PROGRAMMABLE)
QRCONTROL

XTAL

AOORESS OR I/O
(BIT PROGRAMMABLE)

AS

os

R/W

RESET

ADDRESS/DATA OR I/O
(BYTE PROGRAMMABLE)

Z-BUS WHEN USED AS
ADDRESS/DATA BUS

Figure 2·1. Functional Block Diagram

509

Architectural Overview
2.3

REGISTER FILE

The SuperB architecture centers around an internal
register file composed of 325 registers.
All
registers are eight bits wide. 'Of, the 272
general-purpose registers, 208 can be used as an
accumulator, 'address pointer, index register, data
~egister,
or stsck register. The 64 remaining
general-purpose registers are limited to Indirect
or Indexed addressing mode functions such as
stacks, data buffers, and look-up tables. Fiftythree registers are dedicated to special control
and status operations.

2.3.1

Register Pointer

The register file is logically divided into 32
working register groups of B registers each when
using 4-bit register addressing. Two groups may
be active at anyone time and the two Register
Pointers (RPO and RP1) contain the base addresses
of these two working register groups. This allows
fast context switching and shorter instruction
formats.

2.4.1

Addressing Mldes

The addressing modes of
Processing Unit (CPU) are:
•
•
•
•
•
•
•

the

SuperB

Central

Register (R)
Indirect Register (IR)
Indirect Address (IA)
Immediate (1M)
Direct Address (DA)
Indexed (X)
Relative Address (RA)

Register,
Indirect
Register,
and
Immediate
addressing modes are available for load, Arithmetic, logical, Shift, Rotate, and Stack instructions •. Conditional jumps support both the Direct
and Relative addressing modes, while Jump and Call
instructions support the Direct, Indirect, and
Indirect Register addressing modes.
Only load
instructions support Indexed sddressing.

2.4.2 Data Types

The SuperB CPU supports operations on bits, bytes,
BCD digits, and 2-byte words.
2.3.2

Instruction Pointer

The SuperB hardware includes features that facilitate the implementation of threaded-code languages
such as Forth.
These include a special 16-bit
register called the Instruction Pointer (IP) and
three special CPU instructions called NEXT, ENTER,
and EXIT. The IP can also be used to support the
fast interrupt prQcessing mode.

2.4' INSTRUCTION SET
The CPU has an instruction set designed for its
large register file. This includes a full complement of B-bit arithmetic and logical operations,
including multiply and divide.
Binary-Coded
Decimal (BCD) operations are supported using a
decimal adjustment of binary values. Incrementing
and decrementing 16-bit quantities for addresses
and counters are also supported.
Extensive bit
manipulation, including Rotate and Shift instructions, round out the data manipulation capabilities of the SuperB. No special I/O instructions
are necessary since I/O is mapped into the register file.

510

Bits in the register file can be set, cleared,
complemented, and tested. Bits within a byte are
numbered from 0 to 7; bit 0 is the least significant (right-most) bit.
Bytes in the register file can be operated on' by
Arithmetic, logical, Shift and Rotate, and load
instructions, Bytes in memory can be operated on
only by load or stack instructions.
Manipulation of BCD digits, packed two to a byte,
is accomplished by a Decimal Adjust instruction
and a Swap instruction. Decimal Adjust is used
after either a binary addition or subtraction on
BCD digits.
Words in the register file can be loaded, incremented, and decremented with the 16-bit load Word,
Increment Word, and Decrement Word instructions.

Architectural Overview

2.5

I/O OPERATIONS

2.5.2

On-Chip Peripherals

The SuperB has I/O lines grouped into five ports
of eight lines each. Ports are configurable as
input, output, or bidirectional. Under software
control, the ports can provide timing, status
signals, address outputs, and I/O ports with or
without handshaking.
Multiprocessor system
configurations are also supported.

To help cope with real-time problems such as
counting/timing, the SuperB contains two counter/
timers with a large number of user selectable
modes.
It also contains an on-chip universal
asynchronous receiver/transmitter (UARr) which has
its own built-in baud-rate generator that can be
used as a counter when not being used to generate
baud rates.

2.5.1

A DMA channel is provided that allows high-speed
data transfers between on-chip peripherals and the
register file or external memory.

Interrupts

I/O operations can be interrupt-driven or polled.
The SuperB supports 16 vectored interrupts on
eight different levels from 27 interrupt sources.
Each level can be masked and prioritized.
Optiona I high-speed interrupt processing can be
used on anyone of the levels for minimum latency.

2.6 OSCILLATOR
In addition to these features, the SuperB offers
an on-chip oscillator requiring only an external
crystal for operation.

511

Chapter 3

Address Spaces
3.1 INTRiDJcnllf
The SuperB microprocessor supports the following
address spaces:
•
•

CPU register file
Program memory
'Ii Data memory

3.2 CPU REGISTER FIlE
Registers within the SuperB CPU I S internal register file are identified with an 8-bit a"dress,
yielding 256 possible register addresses. However,
the upper 64 addresses are used more than once, ss
describsd below. A total of 325 'registers is
availsble', including 272 general-purpose registers
and 53 special control and status registers. Two
of these registers sre Register Pointers.

A total of 325 registers is accessible with 192
registers (OOH-SFH) accessible in all addressing modes.
These csn be used SS accumulators,
working registers, data buffers, internal stack,
snd so Jorth. It is possible to set up s 256-byte
data buffer and still hsve 16 registers remaining
ss accumulstors and working registers.
Figures 3-1 snd 3-2 show lsyouts 'of the register
file sddress space. The upper 64 bytes of the
address space (C~-FFH) contsin two sets of
registers. The first set can be accessed ,only by
the Register addressing mode; the second set can
be accesaed by the Indirect Register and Indexed
addressing modes, stack' operations, and DMA
accesses. The registers in the second set sre
usable as data buffers or as an internal atack
area.

SET ONE
FFH

I
+r-

CONT:g~::~I~TERS

'(REGISTER ADDRESSING ONLy)

DOH
CFH

r--i- BANKO
r--

EO.
DFH

r------..,.---,
SET TWO

SYSTEM REGISTERS:
STACK, FLAGS, PORTS, ETC.
(REGISTER ADDRESSING ONLy)
WORKING REGISTERS
(WORKING REGISTER
ADDRESSING ONLY)

BFH

FFH
BANK1

DATA REGISTERS
(I"DIRECT REGIIITER, INDEXED,
STACK OR DMA
ACCESS ONLY)

COH~

_______

r--------_
DATA REGISTERS
(ALL ADDRESSING MODES)

~

OOH~_ _ _ _ _ _ _ _~

Figure 3·1. SuperB Registers

512

~

256
BYTES

192
BYTES

Address Spaces
SPECIAL PURPOSE
ADDRESS
REGISTERS
_ _ ,,,_ _ _......A'-_ _ _-.,
BANKO

GENERAL PURPOSE REGISTERS

BANKl

FF

- - - - - - ---- ---EO - - - - - - - -

}

CONTROL
REGISTERS

OF~----i-----i

t==,tc::=1 }SYSTEM

g_;; /= ====:JLS_--t!.'--_-----+-=-=-=-=-+------'
07

06

RPl

I

RpO

I

} REGISTER

POINTERS

Each Register Pointer (RP) can Independently point to any of 32
a-byte blocks of set one. The block selected by RPO Is accessed
In address space CO-C7, while the block selected by RP1 Is

accessed In address space C8-CF. Memory space from CO-CF
can only be accessed if pointed to by the RPs.

~----------------07,
00- -

-

---- -

-

---- -- -

-'------'

'"-------------~v,..--------------~
REGISTER ADDRESSING ONLY

'"--_________

!

'----.---'~

ADD:~kSING
MODES

~v,..-------------J

MAY BE POINTED TO BY REGISTER POINTER

INDIRECT REGISTER,
INDEXED,
STACK, OR
DMAMODES

Figure 3-2. Super8 Register File Address Spaces

The first set consists of three subsets of registers.
The bottom sixteen registers (COH-Cf H)
are available for use as accumulators or working
registers.
The middle sixteen registers (OOHOf H) are used for system registers--Stack
Pointer, flag register, I/O ports, and so forth.
The upper 32 ,bytes (EOH-Ff H) consist of two
banks of registers. Each bank is selected by a
bit located in the Flag register called the Bank
Address bit.
These two banks, a total of 64
bytes, are used for Mode and Control registers.
Only 38 of these 64 bytes are currently used. The
remaining 26 bytes are reserv.ed for future
expansion.
Registers can be accessed as either B- or 16-bit'
registers using Register, Indirect Register, or
Indexed addressing modes. for register addresses
COH to FfH' the addressing mode used determines the actual register being accessed.
Registers accessed as 16-bit registers, are treated
as even-odd register pairs, with the most signifi-

cant byte of data stored in the even-numbered
register and the least significant byte stored in
the next higher odd-numbered register (figure
3-3).
MSB

LSB

Rn

Rn+1

I'

n

= EVEN ADDRESS

Figure 3-3. l6·Bit Register Addressing

With few exceptions, all instructions that reference or mOdify a register may do so to any of the
325 B-bit registers or 176 16-bit register pairs,
regardless of the particular register, as long as
the proper addressing mode is used. The instructions operate on I/O ports, system registers, mode
and control registers, and general-purpose registers without the need for special-purpose instructions.
Usage and access are shown in Table 3-1.

513

Address Spaces

Table 3-1.

SuperB Register File

Registers

Usage

kcess

OO-BF

General-purpose registers

Registar, Indirect Register, or
Indexed modes, via on-chip DMA
operations, or as part of internal stack

CO-FF

Set Two

General-purpose registers

Indirect Regiater or Indexed
modes, via on-chip DMA operations, or as part of internal
stack

CO-FF

Set One

Working registers only

Register mode

DO-OF

Set One

System registers

Register mode

Mode and control ragistars

Registar mode

EO-FF . Set One

The instructions can access B-bit registers or
16-bit register pairs using either 4-bit or·B-bit
address fie Ids.
When using 4-bit register
addressing, the register file is logically divided
into 32 groups of 8 working registers, as shown in
Figure 3-4. All the registers in a working register set have the same value for their five mostsignificant address bits.
The two Register
Pointers (RPO and RP1) are system registers that
contain the base addresse·s of two active working
register groups.

111111
RPO

xxxr---xxx~

100000

RP1

GROUP 32

FF
F8

F7

FO

I
I
I
I
I
I
I
I
I

10
F
8

GROUP 1

7

1 1 0

1001010001

ope

Figure 3-5. Working Register Addressing

Working registers are typically specified by short
format instructions; when a working register
destination is used in the instruction, only four
bits of address are needed to specify the register; one) bit selects the appropriate Register
Pointer and three bits provide the least-significant bits of the register address.
The
five most-significant bits of the address come
from the selected Register Pointer and together
they form an B-bit address.
Applications using
working registers require fewer bytes and have a
reduced execution time.

o

Figure 3-4. Working Register Groups

Note that 4-bit register addressing (Figure 3-5)
is a Register addressing mode so that the registers accessible by this mode include the mode and
control registers, system registers, and working
register groups.

514

RP1 (R21S)

o1

The Register Pointer also speeds context SWitching
when processing interrupts or changing tasks. A
special Set Register Pointer (SRP) instruction is
provided for setting the Register Pointer
contents.

Address Spacea
RPO (R214)

01 1 01 ",'",O",O;;;,O;.;;.;,I;;"';"_ _ _
~ELECTS RPI

_

I

,., SYSTEM REGISTERS AM> IIIlE AM>

RPI (R215)

...Jrl~' °°°I

rnrno..

The system registers govern the operation of the
CPU and can be accessed using any of the instructions that reference the register file using
Register addressing mode. These registers csn be
accessed as working registers. Table 3-2 shows
the system registers.

,

R11

1100"0111~
--SPECIFIES WORKINS
REGISTER ADDRESSING

REGISTERS

" ' &oBIT ADDRESS
FROM INSTRUCTioN

L...---------l-----,

The SuperB uses a 16-bit Program Counter (PC) to
control the sequence, of instructions in the
currently executing program. The PC is not an
addressable register.

REGISTER ADDRESS (R1B3) ""';";"';";;''';'''''L..;;.';''';'.l

Figure 3-6. 8·Blt Working Register Addressing

Not all instructions have 4-bit addresaing modes,
but the active working registers can still be
accessed using B-bit addressing without having to
know the contents of the Register Pointers.
Figure 3-6 ,shows bow this works. The 'upper four
bits of the B-bit sddresa contain 1100 to specify
working register addressing. Bit 3 selects Register Pointer 0 or 1, which supplies the upper five'
bits of the final address while the lower three
b~ts come from bits 0-2 of the originsl B-bit
address.

Mode and control registers sre used to transfer
data, configure the mode of operation, and control
the operation of the on-chip peripherala. These
registers are accessed using Register addressing
mode and are shown in Table 3-3. These regiaters
can be accessed as working registers. The current
"bank" is determined by bit DO in the Flag
register (R213).

Any address in the range COH-CFH (R192-R207)
will invoke working register addressing. Therefore the registers physical! y located at these
addresses can only be accessed when selected by a
Register Pointer (see Figure 3-2).

Program memory is memory that can hold code or
data.
Instruction code can be fetched from
program memory, data can be read from program
memory and, if external program memory is implemented in RAM, data or code can be written to
program memory.
Memory addreaaes are 16 bits
long, allowing s maximum of 64K bytes of program

After Reset"the regia tel' pointers will be set to
RPO = COH and RP1 = CBH.
Table J-2.
Daciul
Addraaa

222
221
220
219
21B
217
216 \
215
214
213
212
211
210
209
21lB

Haxadaciul
Addraaa

DE
DD'
DC
DB
DA
D9

D8
D7
D6
D5
D4
D3
D2
D1
DO

J.1i

Syat_

PROGRAM

AN)

DATA lEtlJRy

~ister8

Register tt.e

Syatem Mode
Interrupt Maak'Registar
Interrupt Request Regiater
Instruction Pointer (Bits 7-0)
Instruction Pointer (Bits 15-B)
Stack Pointer (Bits 7-0)
Stack Pointer (Bits 15-8)
Register Pointer 1
Register Pointer 0
Program Control Flags
Port 4
Port 3
Port 2
Port 1
Port 0

ldantifier

SYM
IMR
IRQ
IPL
IPH
SPL
SPH
RP1
RPO
FLAGS
P4
P3
P2
P1
PO

515

Address
Spaces
!
Table 3-3.

Dacmal
AdcIr8aa
Balle

0

255
254
253
252
251
250
249
24B
247
246
245
244
241
240
239
237
236
235
229
228
227
226
225
224

IbIe and Control Registers

ltexadecmal
AdcIr.a

Register NI.a

Identifier

Reg~ra

FF
FE

ro
FC
FB
FA
F9
F8
F7
F6
F5
F4
F1

FO
EF
ED

EC
EB
E5
E4
E3

E2
E1
EO

Interrupt Priority
'Externel Memory Timing
Port 2/3BJInterrupt Pending
Port 2/3A Interrupt Pending
Port 2/30 Mode
Port 2/JC Mode
Port 2/3B Mode
Port 2/3A Mode
Port 4 Open-Drain
Port 4 Direction
Handshake 1 Control
Handshake 0 Control
Port Mode
Port 0 Mode
UART Data
UART Interrupt Enable
UART Receive' Control
UART Transmit Control
Counter 1 Capture Low
Counter 1 Capture High
Counter 0 Capture Low
Counter 0 Capture High
Counter 1 Control
Counter 0 Control

IPR
EMT
P2BIP
P2AIP
P2DM
P2CM
P2BM
P2AM
P40D'
P4D
H1C
HOC
PM
POM
UIO
UIE
URC
UTC
C1CL
C1CH
COCL
COCH
C1CT
COCT

Wake-Up Mask
Wake-Up Metch
UART Mode B
UART Mode A
UART Baud-Rate
UART Baud-Rate
DMA Count Low
DMA Count High
Counter 1 Time
Counter 1 Time
Counter 0 Time
Counter 0 Time
Counter 1 Mode
Counter 0 Mode

WUMSK
WUMCH

Balle 1 Registera

255
254
251
250
249
248
241
240
229
228
227
226
225
224

FF
FE
FB
FA
F9
Fa
F1

FO
E5
E4
E3
E2
E1
EO

,

.

memory. The bottom of program memory lS in the
on-chip ROM; the remaining program memory can be
implemented external to the Sup~rB.
Data memory is memory that can hold only data to
be read or 'written, not instruction code; instruction fetches never reference data memory. Data
memory is always implemented external to the
SuperB.

516

UMB

Generator Low
Generator High

UMA
UBGL
UBGH

DeL
Constant
Constant
Constant
Constant

Low
High
Low
High'

DCH
C1TCL
CHCH
COTCL
COlCH
C1M
COM

External data memory can be incorporated with or
separated from the external program memory address
To implement separate program and data
space.
memory address spaces ext~rnal to the SuperB, a
port output pin (P35) must be defined, as t~ Data
Memory select (mt) output. This output remains
high when fetching instructions ,or accessing data
in the program memory addreas space and goes low
when accessing data in ,the data memory address
space. Thus, this signal can be 'used to segregate

Address Spaces
6 ••3.

r--------.,

6•• 3• . - - - - - - - - . ,

EXTERNAL
PROGRAM
MEMORY

THIS BOUNDARY)

DEP~~~~I~~

1---------1)

32~_------~

EXTERNAL
DATA
MEMORY

ON.CHIP
ROM

INTERRUPT VECTORS

PROGRAM MEMORY

DATA MEMORY

Figure 3-7. Program and Data Memory Address Spaces

the program and data spaces external to the
SuperB_
Separate forms of Load instructions are
used to access the two memory address spaces: the
LDC ,instruction and its derivatives access program
memor y, and the LDE instruction and its der i v atives access data memory.

ing, and general dynamic storage (via the Push and
Pop instructions).
The SuperB prov ides hardware
support for stack operations from either the
register file or data memory.
Stack location
selection is under software control via the
External Memory Timing register (R254, Bank 0).

Program and data memory maps are illustrated in
Figure 3-7.

Register pair RR216 for\lls the 16-bit Stack
Pointer, used for CPU stack operations.
The
address is stored with the most" 'significant byte
'in R216 and least significant in R217 (Figure
3-B) •

To access memory beyond the on-chip ROM, Ports 0
and 1 must be configured as a memory interface.
Port 1 can be configured as a multiplexed
address/data bus ( AD O-AD7)' thus providing address
"lines AO-A7 and data lines DO-D7. Port 0 can be
configured on an individual bit basis for up to
eight additional address lines (A B-A15)'
Both
parts are supported by the control Hnes Address
Strobe (m, Data Strobe (~, and Read/Write
(Rf'iI) •
In the ROM less version, Port 1 is automatically
configured as a multiplexed address/data bus.
Port 0 bits 0-4 will be configured as address bits
AB-A12 at Reset, but any Port 0 bit may be defined
as either I/o or address as needed.
For more details on external memory interface, see
section 12.3.
No matter which version of the SuperB is used, the
first 32 bytes of program memory are reserved for
the interrupt vectors.
Thus the first address
available for a user program is location 32. This
address is automaticall y loaded into the Program
Counter whenever a hardware Rese,t occurs.

3.5 CPU AND USER STACKS
The SuperB
uses a stack for
implementing
subroutine calls and returns, interrupt process-

R217 (09) SPL

1

...._ _L_O_W_E_R_B_y_TE_ _..... STACK POINTER LOW

R216 (08) SPH

I

...._ _ _
UP_P_E_R_B_YT_E_ _.... STACK POINTER HIGH

Figure 3-8. Stack Pointer

The Stack Pointer is decremented before a Push
operation and incremented after a Pop operation.
The stack address always points to the last data
stored on the top-of-stack.
The stack is used to hold the return address for
CALL instructions and interrupts, as well as
data.
The contents of the Program Counter are
saved on the stack during a CALL instruction and
restored during a REf instruction. During interrupts, the contents of the Program Counter and
Flag register are saved on the stack. The IRE f
instruction restores them (Figure 3-9).
When the SuperB is configured to use an internal
stack (the register filel', register R217 serves as
til8 Stack Pointer and register R216 is a generalpurpose register.
However, if an overflow or
underflow condition occurs due to the incrementing

517

Address Spaces
HIGH ADDRESS

~OP
STACK

~

OF --....

Cl

PCl

PCH

PCH
TOPOF-.

FLAGS

STACK

STACK CONTENTS
, AFTER A CAll
INSTRUCTION

STACK CONTENTS
AFTER A NORMAL
INTERRUPT CYCLE

LOW ADDRESS

Figure 3·9. Stack Operations

Table 3-4.

User Stack Operations s..&ary
- - Stack location

Stack Type·

Operation

Register
File

Progra.

Oats

Melmry

MeIIory

Ascending

PUSH to stack
POP from stack

PUSHUI
POPUD

LDCPI
LDCD

LDEPI
LDED

Descending

PUSH to stack
POP from stack

PUSHUO
POPUI

LDCPD
LDCI

lDEPD
LDEI

*

Ascending stack goes from low to high addresses within memory or
register file. Descending stack goes from high to low addresses
within memory or register file.

and decrementing of normal stack operations, the
contents of register R216 are affected.
The SuperB also pro v ides for user-defined stacks
in both the register file and in program or data
memory. These stacks can 'be made to increment or
decrement on Push a,nd Pop. Table 3-4. summarizes
the kinds of stacks and the instructions used.

R21S (OA) IPH
INSTRUCTION POINTER HIGH

I~I~I~I~I~I~I~I~I

cl_____

HIGH BYTE (IPS,IP15)

R2l9 (DB) IPl
INSTRUCTION POINTER LOW

I~I~I~I~I~I~I~I~I
3.6 INSTRUCTION POINTER (IP)
The SuperB provides hardware support for implementation of threaded-code languages such as Forth.
An important part of that support is in the form
of a special register called the Instruction
pointer (IP) (Figure 3-10).
The Instruction
Pointer is made up of register pair RR21B, with
R21B holding the most significant byte of a memory
address and R219 the least significant byte.
A ,threaded-code language may be co~sidered to have
created a higher leve 1 imaginary machine wi thin
the actual hardware machine.
For comparison
purposes, the IP is to the imaginary machine as
the \ Program Counter is to the actual hardware
machine.

518

cl--___

lOW BYTE (IPO·IP7)

Figure 3·10. Instruction Pointer

The IP is used by three special instructions
called NEXT, ENTER, and EXIT.
The instruction
NEXT passes control from the hardware machine to
the imaginary machine, while ENTER and EXlT are
the imaginary machine equivalents of subroutine
CALLS and RETURNs in the hardware machine.
The IP can 'also be used in the fast interrupt
processing mode for special interrupt handling
(see section 6.2)., I t can be used either for
interrupt processing or imaginary machine processing, but not for both ·at the same time.

Chapter 4
Addressing Modes
_.1

INTRODUCTION

Accessing an individusl ragister requires apecifying an B-bit address in the range 0-255 or a
working register's 4-bit address. The most significant bit of the 4-bit working register address
selecta one of two Register Pointers: if this bitis 0, then R214 (RPO) is selected; i f it is 1,
then R215 (RP1) is selected. The address of the
actual register being accessed is formed by the
concatenation of the high order five bits of the
value contained in the selected Register Pointer
with the remaining three bit address supplied by
the instruction.

are stored ss lists of bytes in
progrem memory thst sre fetched vis instruction
fetches using the Progrem Counter. Instructions
will indicste both the action to be performed snd
the dsts to be operated on. The method used to
determine the location of the data operand is
csllsd the addressing mode.
Instr~tions

Operands specified in SuperB instructions are
either condition codes, immediate dsta, or the
deaignation of a register file, program memory, or
data memory location.

A register pair can be used to specify a 16-bit
value or memory address.
The Load Constant
instruction and its derivatives (LOC, LOCO, LOCI,
LOCPO, LOCPI) load data from progrsm memory; the
Load External instruction and its derivatives
(LDE, LOED, LOEI, LDEPO, LDEPl) load from progrem
memory. See the instruction set in Chapter 5 for
further details.

For the SuperB, there are seven explicit addressing modes (i.e. , addressing modes designated by
the programmer):
• Register (R)
• Indirect Register (IR)
• Indexed (X)
• -Direct Address (OA)
• Indirect Addres~ (IA)
• Relative Address (RA)
• Immediate (1M)

_.2 REGISTER 1IOORESS1t BINARY ENCOOING

The following sections describe the symbols used
for oper.ands and status flags, and the flag
settings and their meanings.
Condition Codes

Meaning

Always False
Always True
Carry
No Carry
Zero
Not Zero
Plus
Minus
Overflow
No Overflow
Equal
Not Equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal

Flags Set

C

C

=
0

Z

Z
5

0
0

5

V
V

0

Z

1

Z

0

(5
(5
(Z
(Z
C

C

=

XOR V)
0
XOR V) = 1
OR (5 XOR V»
OR (5 XOR V»

=0
=1

(C = 0 ANO Z = 0)
(C OR Z)

=1

o

=

=

*lndicates condition codes that relate to two different mnemonics but test
the same flags. For example, Z and EQ are both True if the Zero flag is
set, but after an ADD instruction, Z would probably be used, while after a
CP instruction, EQ would probably be usep.

528

Instruction Set
Tabla 5-3.
Notation

cc
r

rb
rO
rr

R

Notation and Binary Encoding

Meaning

Actual Operand/Range

Cond ition code
Working register only
Bit b of working register
Bit 0 of working register
Working register pair
Register or working register

See condition code list (Table 5-2)
Rn: where n = 0-15
Rn Rb: where n = 0-15 and b = 0-7
Rn: where n = 0-15
RRp: where p = 0,2,4, ••• ,14
Reg: where reg represents a number in the range
0-255
Rn: where n = 0-15
Reg Rb: where reg represents a number in the
range 0-255 and b = 0-7
Rn #b: where n = 0~15 and b 0-7
Reg: where reg reprsents an even number in the
range 0-254
RRp: where p = 0,2, ••• ,14
# addrs: where addrs represents an even number
in the range 0-254
@Rn: where n = 0-15
@reg: where reg represents a number in the range
0-255
®Hn: where n '= 0-15
@RRp: where p = 0,2, ••• ,14
@reg: where reg represents an even number in the
range 0-254
@RRp: where p = 0,2, ••• ,14
reg (Rn): where reg represents a number in the
, range 0-255 and n = 0-15
addrs (RRp): where addrs represents a number in
the range -128 to +127 and p = 0,2, ••• ,14
addrs (RRp): where addrs'represents a number in
the range 0-65,535 and p = 0,2, ••• ,14
addrs: where addrs represents a number in the
range 0-65,535
addrs: where addrs represents a number in the
range +127,-128 that is an offset relative to
the address of the next instruction
IIdata: where data is a number between 0 and 255
#data: where data is a number between 0 and
65,535

Rb

Bit b of register or working
register

RR

Register pair or working
register pair

IA

Indirect addreasing mode

Ir
IR

Indirect working register only
Indirect register or working
register

Irr

IRR

Indirect working register only
Indirect register pair or
working register pair

x

Indexed addressing mode

XS

DA

Indexed (Short Offset)
addressing mode
Indexed (Long Offset)
addressing mode
Direct addressing mode

RA

Relative addressing mode

1M
IML

Immediate addressing mode
Immediate (Long)
addressing mode

XL

529

Instruction Set

5.4.1

Notational Shorthand

Operands and status flags are represented by a
notational shorthand in the detailed instruction
descriptions of section 5.5.2. The notation for
operands (condition codes and addressing modes)
and the actual operands they represent are shown
in Table 5-3.

indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr (n)" is
used to refer to bit "n" of a given location. For
example,
dst (7)
refers to bit 7 of the destination operand.

Additional

5~ls

Used:

5.4.2 flag Settings
Meaning

Notation for the flags is shown below.
dst
src

Destination operand
Source operand
Indirect Register address prefix
Stack Pointer (R216 and R217)
Program Counter
Instruction Pointer (R218 and
R219)
Flag register (R213)
Register Pointer 0 (R214)
Register Pointer 1 (R215)
Interrupt Mask register (R221)
Immediate operand or Register
address prefix
Hexadecimal number prefix
Opcode

@

SP
PC
IP
FLAGS
RPO
RP1
IMR
fI

OPC

flag
C
Z
S
V
D
H
0

*
X

Meaning

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-Adj ust flag
Half-Carry flag
Cleared to 0
Set to 1
Set or Cleared according to operation
Unaffected
Undefined

Figure 5-2 provides a quick reference guide to the
Assignment of a value is indicated by the symbol
"<--"; for example,
dst

530

<--

dst + src

cOl1l11ands.

Instruction Set

SUPER8 OPCODE MAP

Lower Nibble (Hex)

o
o

2

5

8

i

e

~
......~
:::>

7

z

8

B

C

D

F

8

9

B

C

6

6

10

10

6

12/10

12/10

6

14

ADD

ADD

ADD

ADD

BOR·

LD

LD

DJNZ

JR

LD

JP

INC

NEXT

'1,r2

rl, lr2

A2,A,

IA2,A,

A"IM

ro-Ab

r"A2

r2,A,

r"AA

cC,AA

r"IM

cc,DA

rl

6

6

6

10

10

RLC

ADC

ADC

ADC

ADC

ADC

BCP

A,

lA,

'1,(2

", lr2

A2,A,

IA2,A,

A"IM

r"b,A2

10

6

6

6

6

10

10

10

10

ItlC

SUB

SUB

SUB

SUB

SUB

BXOR·

Rl

lA,

r1,f2

r" lr2

A2,R,

IR2,R,

R"IM

rO-Rb

NOTE
C

6

6

10

10

,10

SBC

SBC

SBC

SBC

SBC

(1,r2

r1, lr2

A2,R,

IA2,R,

R"IM

ENTER

~
EXIT

r---e

NOTE

WFI

A

I---

6

6

6

6

10

10

10

DA

DA

OR

OR

OR

OR

OR

LDB·

SBO

R,

lA,

'1,(2

r" lr2

A2,R,

IA2,R,

R"IM

rO-Rb

10

10

6

6

10

10

10

8

POP

POP

AND

AND

AND

AND

AND

BITC

r---e

R,

lA,

r" lr2

R2,Al

IR2,A,

A"IM

r"b

'1,r2

10

~

10

INC
JP

6

F

ADD

6

12110

E

D

6

RLC

6

A

IAI

6

6

6

6

10

10

COM

COM

TCM

TCM

TCM

TCM

TCM

BAND·

A,

IR,

".'2

r" lr2

R2,A,

IR2,A,

A"IM

rO-Ab

10

NOTE

'0

10/12

12/14

6

6

10

10

10

PUSH

PUSH

TM

TM

TM

TM

TM

A2

IR2

r',(2

'1, Ir2

A2,R,

IA2,Rl

Rl,IM

10

10

10

10

24

24

DECW

DECW PUSHUD PUSHUI MULT
IR,
6

RL

AL

R,

IR,

IR"A2

IR"A2

10

10

POPUD POPUI
IR2,A,

IA2,A,

A2,RA,
28112

24

LD
'l,x,r2

DIY

DIY

LD

IA2,AA,

IM,AA,

r2,x,rl

,0

INCW

CP

CP

CP

CP

CP

AR,

lA,

'1,r2

'1, lr2

R2,A,

IR2,R,

R"IM

6

6

10

10

10

6

6

6

10

10

10

XOR

XOR,

XOR

XOR

XOR

R,

lA,

'1,r2

'1, lr2

R2,R,

IR2,R,

R"IM

6

6

16/18

12

10

10

12

6'

RRC

RRC

CPIJE

LDC·

LDW

LDW

LDW

LD

R,

IR,

Ir,r2,AA

'1, Irr2

6

6

16118

12

SRA

SRA

R,

IR,
6

'2, lrr1

16

16

RR

R,

IR,

'1, lrr2

8

8

16

SWAP
R,

IR,

'2, lfr1

6

CALL

LD

LD

lA,

IR"IM

Ir1,(2

10

10

18

LD

LD

LDC·

'1, lrr2

R2,R,

A"IM

rl, lrr2,xs

16

18

10

18

CALL

LD

CALL

LDC·

IRR,

R2,IR,

DA,

f2. lrrl,xs

'2,lrr1

r---e

.

SCF

r-e
CCF

r---e

18

NOP

Legend:

NOTE A

NOTEB

NOTE;D

r-e
RCF

,

'1, lr2

10

IR2,R,

SWAP LDCPD· LDCPI·

IRET

E

20

,0

16/6

NOTE

LD

LDCD· LDCI·

RR

RET

I---

CLR

Ir"r2,RA

'14

D

6

CPIJNE LDC·

r-e
EI

NOTE

CLR

AR2,RR, ,IR2,RR, AA"IML

DI

10

DIY
A2,AR,

10

r---e

10

MULT
IM,RA,
28/12

SBI

I--I---

MULT
28/12

6

B

IR2,AR,

INCW

6

E

10

7

DEC

6

A

10

8

6

AR,
9

5

A,

IRR,

4

4

DEC

10

3

3

NOTEC

r - 4-bit address
R = 8-bit address
b = bit number
R, orr, = dst address
R2 or '2 = src address

• Examples:
BORro-R2
is BOR r"b,R2
or BOR r2,b,R,
LDCr"lrr2
isLDCrl,lrr2 = program
or LDE r, ,lrr2 = data

NOTEE
Sequence:
Opcode, first, second, third operands
NOTE: The blank areas are not defined.

Figure 5-2. SuperS Opcode Map

531

5.5

Ace

Instruction
Descriptions
and Formats
ADC

Add With Carry

dst,src

Operation:

dst _- dst + src + c
The source operand, along with the setting of the Carry flag, is added to the destination
operand and the sum is stored in the destination. The contents of the source are u,naffected. Twos-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the
addition of high-order operands.

flags:

C:
Z:
V:

Set if there is a carry from the most significant bit of the result; cleared otherwise.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurs, that is, if both operands are of the sam- sinn and
the result is of the opposite sign; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
D, Always cleared
H: ' Set if there is a carry from the most significant bit of the low-order four bits of the
result; cleared otherwise.

Instruction
format:
Cycles
Opcode

Opcode

Opcode

II
II
II

dst

src

src

dst

II
II

Opcode
(Hex)

Addressing Mode
~
!!E£

6

12
13

r
r

r
Ir

dst

10

14
15*

R
R

R
IR

src

10

16

R

1M

*This format is used in the example.
[x8lllple:
If the register named SUM contains %16, the Carry flag is set to 1, working register 10
contains %20 (32 decimal), and register ,32 contains %10, the statement
~DC

SUM,

~R10

leav,es the value %27 in register' SUM.

532

AND
Logical
AND

dst ,src

Operation:

dst _- dsl AND src
The source operand is logically ANDed with the destination operand. The result is stored in
the destination. The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both 1s; otherwise a 0 bit is stored. The contents of the
source are unaffected.

Flags:

C:
II

V:
S:

H:
0:

Unaffected
Set i f the result is 0; cleared otherwise.
Al ways cleared to O.
Set if the result bit. 7 is set; cleared otherwise.
Unaffect.ed
Unaffected

Instruction
rorooat.
Cycles
Opcode

Opcode

Opcode

II
II
I1

dst

src

src

dst

II
II

Opcode
(Hex)

Addressing Mode
dst
src

6

52
53

r
r

r
Ir

dst

10

54
55

R
R

R
lR

src

10

56*

R

1M

*This format is used in the example.
[xlIlIple.
If the source operand is the immediate value %7B (01111011) and the register named TARGET
contains 1',(3 (11000011), the statement

AND TARGET, R%7B
leaves the value M3 (01000011) in register TARGET.

533

BAND
Bit And
BAND
BAND

dst,src,b
dst,b,src

Operation:

dst(O) _- dst(O) AND src(b)
or
dst(b) .... - dst(b AND srdO)
The specified bit of the source (or the destination) is logically ANDed with bit 0 of the
destination (or source).
The resultant bit is stored in the specified bit of· the
destination. No other bits of the destination are affected. The source is unaffected.

Flags:

C:

Z:
V:

S:

H:

D:

Unaffected
Set if the result is 0; cleared otherwise.
Undefined
0
Unaffected
Unaffected

Instruction
forllat:

Opcode

Cycles

(Hex)

,-_o_p_c_od_e_--,I

Idstl .b

lollc._ _s_rc_ _-,

10

67*

,-_o_p_c_od_e_--,I

I src I

111

10

67

b

c.1_ _
d_st_ _-,

Addressing Mode
d.st
src
rO

ro

*This format is used in the example.

Ex ....pIe:
If the register named BYTE contains %73 (01110011) and working register 3 contains %01, the
statement
BAND R3,BYTE,IJ7 .
leaves the value

534

~mo

in working register 3.

BCP
Bit Compare
BCP

dst,src,b

Operation:

dst(O) - src(b)
The specified bit of the source is compared to (subtracted from) bit 0 of the destination.
The Zero flag is set .if the bits are the same; otherwise it is cleared.
The contents of
both operands are unaffected by the com par ison.
.

flags:

C:

Z:
V:

S:

H:
D:

Unaffected
Set if the two bits are the same; cleared otherwise.
Undefined
0
Unaffected
Unaffected

Instruction
forllBt:
Opcode

Idstl

bioi

I,---s_rc--,

Cycles

Opcode
(Hex)

10

17

Addressing Mode
.!!&
src
rO

Example:
If working register 3 contains %01 and register 64 U'40) contains %FF, the statement

BCP R3,64,1I0
sets the Zero flag bit in Flag register R213.

BITC
Bit Complement
BITC

dst,b

Operation:

dst(b)

~-

NOT dst(b)

This instruct ion complements the specified bit within the destination without affecting any
other bits in the destination.

flags:

C:

Z:
V.

S:

H:

D:

Unaffected
Set if the result is 0; cleared otherwise.
Undefined
0
Unaffected
Unaffected

Instruction
forllBt:
Cycles
Opcode

8

Opcode
(Hex)

Addr"ssing Mode

.!!&

57

If working register 3 contains %FF, the statement
BITC R3,1I7
leaves the value %7F in that register.

535

BITR
Bit Reset
BITR

dst,b

Operation:

dst(b) -+- 0
This instruction clears the specified bit within the destination without affecting any other
bits in the destination.
No flags affected

Flags:
Instruction

for ....t:

Opcode

(Hex)
Opcode

Addressing Mode
dst

77

Ex ....pIe:

If working register 3 contains %80, the statement
8ITR R3,1I7

leaves the value %00 in that register.

BITS
Bit Set
BITS

dst,b

Operation:

dst(b) _- 1
This instruction sets the specified bit within the destination without affecting any other
bits in the destination.

flags:

No flags affected

Instruction
for.at:

,Opcode

Opcode

(x_pIe:
If working register 3 contains %00, the statement

BITS R3,1I7

leaves the value

536

~~80

in t.hat register.

Cycles

(Hex)

8

77

Addressing Mode
~

BOR
BitOR.
BOR
BOR

dst,src,b
dst,b,src

{Jperation :

dst(O)_- dst(O) OR src(b)
or
dst(b) _- dst(b) OR src(O)
The specified bit of the source (or the destination) is logically ORed with bit 0 of the
destination (or the source).
The resultant bit is stored in the specified bit of the
destination. No other bits of the destination are affected. The source is unaffected.

flags:

c:
Z:
V:
5:
H:
D:

Unaffected
Set. if the result is 0; cleared otherwise.
Undefined
0
Unaffected
Unaffected

Instruction
for1l8t:

Opcode
(Hex)

1

,-_o_p_c_o_de_--,I

, dst

,--Opc_od_e--,I

Isrc ,

b

10 1 IL-__s_rc_ _-,

10

07

b

I' 1 <--I_d_st----J

10

07*

Addressing Mode
~
src
ro
ro

*This format is used in the example.
[x_pie:
If register 32

(~~20)

contains %Of and working register 3 contains %01, the statement

BOR 32,lt7,R3
leaves the value %Bf in register 32.

537.

BTJRF
Bit Test a,nd Jump Relative on False
BTJRf

dst,src,b

Operation:

If src(b) is a 0, PC _- PC + dst

The specified bit within the source operand is tested. If it is a 0, the relative address
is added to' the Program Counter and control passes to the statement whose address is now in
the PC; otherwise the instruction' following the BTJRf instruction is executed.
No flags affected

flags:
Instruction
format:

(Hex)

Addressing Mode
~
src

37

RA

Opcode

L....._o_pc_o_d_e_...J1

bi o i

1 src

...
I _ _d_s_t_-,

16/18*

* 18 if jump taken, 16 if not
Example:
I f working register 6 contains %7F, the statement
8TJRF SKIP,R6,117
causes the Program Counter to jump to the memory location pointed to by SKIP.
location must be within the allowed'range of +127,-128.

The memory

BTJRT
Bit Test and Jump Relative on True
BTJRT

dst,src,b

Operation:

If src(b) is a 1, PC _- PC + dst
The specified bit within the source operand is tested. If it is a 1, the relative address
is added to the Program Counter and control passes to the statement whose address is now in
the PC; otherwise the instruction following the BTJRT instruction is executed.

flags:

No flags affected

Inst ruction
format:
Cycles
Opcode

J

1

src

I

bill

_ds_t--"

1-1

16/18*

Opcode
(Hex)
37

Addressing Mode
dst
src
RA

* 18 if jump taken, 16 if not
Ex ....ple:
If working register 6 contains %80, the statement

BTJRT $+8,R6,117
causes the next five bytes in memory to be skipped.
Note:
The $ refers to the address of the first byte of the instruction current~y being executed.

538

BXOR
BitXOR
BXOR dst,src,b
BXOR dst ,b,src
Operation.

dst(O) _- dst(O) XOR src(b)
or
dst(b) _- dst(b) XOR src(O)
The specified bit of the source (or the destination) is logically EXCLUSIVE ORed with bit 0
of the destination (or source). The resultant bit is stored in the specified bit of the
destination. No other bits of the destination are affected. The source is unaffected.

Flags:

C:
Z:
V:

!i:
H.
D:

Unaffected
Set if the result is 0; cleared otherwise.
Undefined
0
Una ffected
Unaffected

Instruction
for_t:

Opcode

1 Idst I

,-_o_p_c_o_de_.......

L-_o_p_co_d_e_.....1

Isrc I

b

10 I I'-_sr_c---,

b.

1'1

IL--d_st---J

Addressing Mode

Cycles

(Hex)

.!!!!.

10

27*

rO

10

27

.!!!:£.

ro

*This format is used in the example.
[x8llple:
If working register 6 contains rofF and working register 7 contains roFO, the statement
BXOR R6,R7,1I4
leavell the value %FE in working register 6.

539

CALL
Call Procedure
CALL

dst

Operation:

SP _- SP liSP _- PCl
SP _- SP - 1
liSP _- PCH
PC _- dst
The current contents of thE! Program Counter are pushed onto the top of the stack. The
Program Counter value used is the address of the first instruction f9110wing the CALL
instruction. The specified destinstion sddress is then loaded into the Program Counter and
pOints.to the first instruction of a procedure.
At the end of the procedure the Return (RET) instruction can be used to return to the
original program flow. RET pops the top of ~he stack back into the Program Counter.
No flags affected

Flags:
Instructioo
fOl"llBt:

Opcode
Opcode
Opcode

II
II
II

Opcode
(Hex)

Addressing Mode

Cycles
18

f6

OA

dst

18

f4

IRR

dst

20

04

IA

dst

~

Ex.-pl.es:
(1 )

I f the contents of the Program Counter are %1 A47 end the contents of the Stack Pointer
(control registers 216-217) are %3002, the statement
CALL %3521
causes the Stack Pointer to be decremented to %3000, %lA4A (the address following the
instruction) to be stored in externsl data memory locations %3000 and %3001 (%4A in %30001,
%lA in %3000), and the Program Counter to be loaded with %3521. The Program Counter now
points to the address of the first statement in the procedure to be executed.
;

(2)

If the contents of the Program Counter and Stack Pointer are the same as in El dst); cleared otherwise.
is 0; cleared otherwise.
overflow occurred, cleared otherwise.
is negative; cleared otherwise.

Instruction

forllat:

Opcode

Opcode

Opcode

Opcode

II
II
II

dst

src

src

dst

II

dst

II

src

Cycles

(Hex)

6

A2
A3

10

10

Addressing Mode

!!!t

!!.£
r

Ir

A4
A5*

R

R'

R

IR

A6

R

1M

*This format is used in the example.
[xallpIe:
If the register named TEST contains %63, working register 0 contains %30 (48 decimal), and
register 48 contains %63, the statement
CP TEST, iRO
sets (only) the Z flag.
will be taken.

544

If this statement is followed by "JP EQ, true_routine," the jump

DA
Decimal Adjust
DA

dst

Operation:

dst -+- DA dst
The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation.
For addition (ADD, AOC) or subtraction (SUB, SBC), the following
table indicates the operation performed:

Instruction

Carry
OA

Befor~

Bits 4-7
Value (Hex)
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2

0

a
a
a
a
a

ADD
ADC

1
1
1

0
0
1

a
a
1
0

a

0-3

a
a

SUB
SBC

H Flag
Before DA

Number Added
To Byte

0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F

1
0
1

Carry
After DA

00
06
06
60
66
66
60
66

0

a
0
1
1
1
1
1

66

0-3

a

0-9
0-8
7-F
6-F

1
1

Bits ~J
Value (Hex)

0-9
6-F
0-9
6-F

00
FA
AO
9A

a

= -00
= -06
= -60
= -66

0
1
1

The operation is undefined i f the destination operand was not the result of a valid addition
or subtract ion of BCO digits.
Flags:

C:

Z:
V:
5:
H:
0:

Set if there was a carry from the most significant bit; cleared otherwise (see table
above) •
Set if the result is 0; cleared otherwise.
Undefined
Set i f the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

Instruction
rorllBt:

~_o_pc_o_d_e__~1 ~I

____

ds_t__

~

6

Opcode
(Hex)

Addressing Hode
dst

40*
41

R
IR

*This format is used in the example.
[x ... pIe:

I f working register RO contains %15 and working register Rl contains %27, the statements

ADD Rl, RO
DAB Rl
leave %42 in wor,king register Rl.
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum
is incorrect, however, when the binary representations are added in the destination location
using standard binary arithmetic.
+

0001
0010

0101
0111

0011

1100 = %3C

The DA statement adjusts this result so that the correct BCD representation is obtained.
+

0011
0000

1100
0110

0100

0010

42

545

CPIJE
Compare Increment and Jump on Equal
CPIJE

dst,src,RA

Operation:

If dst - src = zero, PC
Ir ~- Ir + 1

~-

PC + RA

The source operand is compared to (subt racted from) the
is 0, the relative address is added to the Program
statement whose address is now in the Program Counter;
the CPIJE instruction is executed. In either case the
before the next instruction.
flags:

destination operand. I f the result
Counter and control passes to the
otherwise the instruction following
source pointer is incremented by one

No flags affected

Instruction
rorl1l8t:

Opcode
Cycles
16/18*

Ope ode

(Hex)

Addressing Hode
dst
src

C2

Ir

* 18 if jump taken, 16 if not
Ex .... ple:
If working

register 3 contains %AA, working register 5 contains %10,
contains %AA, the statement

and register

~~10

CPIJE R3,!lR5, $
puts the value

~~11

in working register 5 and then executes the same instruction again.

CPIJNE
Compare Increment and Jump on Non Equal
CPIJNE

dst,src,RA

Operation:

If dst - src ~ zero, PC
Ir ~- Ir + 1

~-

PC + RA

The source operand is compared to (subtracted from) the destination operand. l,f the result
is not 0, the relative address is added to the Program Counter and control passes to the
statement whose address is now in the Program Counter; otherwise the instruction following
the CPIJNE instruction is executed. In either case, the. source pOinter is incremented by
one before the next instruction.
flags:

No flags affected

Instruction
rOrl1l8t:

Opcode
(Hex)

~_o_p_c_od_e__~1

I

src

dst

II'-__

RA_-,

Addressing Hode
dst
!!!£
Ir

D2

* 18 if jump taken, 16 if not
Ex ....ple:
If working ·register

3 contains %AA, working register 5 contains %10,
contains %AA, the statement

and register %10

CPIJNE R3,!lR5, $
puts the value %11 in working register 5 and then executes the next instruction following
this instruction.
Note:

546

The $ refers to the address of the first byte·of the instruction currently being executed.

DEC
Decrement
DEC' dst
dst _- dst - 1

Operation:
"
flags:

The content.s of the destinat ion operand are decremented by one.

C:
Z:

V:
S:
H:

0:

Unaffected
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if result is negative; cleared otherwise.
Unaffected
Unaffected

Instruction
ror.at:

Opcode
(Hele)

L-_o_pc_o_d_e_...J1

1,-_d_S_t._,_...J

00"
01

Addressing Mode
~
R
IR

"This format is used in the example.
Example:
I f working register 10 contains %2A, the st.atement

DEC R10
leaves the value %29 in that register.

547

OECW
Decrement Word
OECW

dst

Operation:

dst _- dst - 1
The cant ents of the dest inat ion locat ion (which must be an even address) and the operand
following that location are treated as a single 16-bit value which is decremented by one.

'Flags:

C:
Z,:

V:
S:
H:
0:

Unaffected
Set i f the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if the result is negative; cleared otherwise.
Unaffected
Unaffected

Instruction
forllat:
Cycles
Opcode

II

Opcode
(Hex)

Addressing Mode
dst

(

10

dst

80

RR

81*

lR

*This format is used in the example.
EX8llple:
If working register 0 contains %30 (48 decimal) and regist.ers 48-49 contain the value
the statement

?~FAF3,

DECW !lRO
leaves the value

?~FAF2

in registers 48 and 49.

01
Disable Interrupts
01
Operation:

SMR (0) _- 0
BIt 0 of control register 222 (the System Mode register) is cleared to O. All interrupts
are disabled; they can still set their respective interrupt status latches, but the CPU will
not directly service them.

Flags:

No flags affected

Instruction
forllat:

Opcode
(Hex)
Opcode

6

8F

Example:
If control register 222 contains ?OO1, that is, interrupts are enabled, the statement

Dl
sets control register 222 to %00, disabling all interrupts.

548

Divide (Unsigned)
DIV

dst,src

Operation:

dst';' src
dst (UPPER) ~- REMAINDER
dst CLOWER) _- QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient
(8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored
in the upper half of the destination. When the quotient is ~28, the numbers stored in the
upper and lower halves of the destination for quotient and remainder are incorrect.
Both
operands are treated as unsigned integers.

flags:

c:
Z:
V:
5:
H:
D:

Set if V is set and quotient is between 28 and 29 - 1; cleared otherwise.
Set if divisor or quotient = 0; cleared otherwise.
Set if quotient is ~ 28 or divisor = 0; cleared otherwise.
Set if M5B of quotient = 1; cleared otherwise.
Unaffected
Unaffected

Instruction
Format:
Cycles
Opcode

II

'"Src

II

dst

28/12*
28/12·
28/12*

Opcode
(Hex)
94**
95

Addressing Hade

!!!!!.
RR
RR
RR

96

!!:£
R
IR
1M

* 12 if divide by zero is attempted
** This format is used in the example
Ex .... ple:
~~10 in register 6 and %03 in register 7,
and working register 4 (divisor) conta-ins ~~40, the statement

If working register pair 6-7 (dividend) contains

DIV RR6,R4
leaves the value
6 (remainder).

1~40

in working register 7 (quotient) and the value

~~03

in working register

549

,DJN~

,

Decrement and Jump if Nonzero
DJNl

r,dst

Operation: '

r _- r -1
If r 'I 0, PC _- PC + dst

The working register being used as a counter is decremented.
I f the contents of the
register are not 0 after decrementing, the, relati ve address is added to the Progr~m Count.er
and control passes to the statement whose address is now in the Program Counter. The range
of the relative address is +127 to -12B, and the original value of,the Program Counter is
taken to be the address of the instruction byte following tlie DJNZ .statement.
When the
working regi~ter counter reaches zero, control falls through to the statement following the
DJNZ statement.

flags:

No flags affected

lnstructioo
Forat:

Opcode

Cycles
r 10pcodei

dst

12 if jump taken

Addreslling Mode

(Hex)

rA
r : 0 to

~

r

RA

10 if jump not taken
EXlaple:
DJNZ is typically used to' control a "loop" of instructions. In this example, 12 bytes are
moved from one buffer area in the register file to another. The steps involved are:
o
o
o

Load 12 into the 'counter (working register 6)
Set up the loop to per form the moves
End the loop with OJNZ

LOOP:

LD R6,1I12
LO R9,OLDBUf (R6)
LD NEWBUf (R6),R9
OJNZ R6,LOOP

!Load Counter!
!Move one byte to!
! New locatio!)!
!Decrement and !
!Loop until counter.: O!

Note:
The working register being used as'a counter must be one of the registers DO-Cf.
of the I/O ports, control or peripheral registers will have undefined results.

550

Using one

EI
Enable Interrupts
EI
SMR (0) _- 1

Operation:

Bit 0 of control register 220 (the System Mode register) is set to 1.
This allows any
interrupts to be serviced when they occur (assuming they have highest priority) or, if their
respecti ve interrupt status latch was prev lousl y enab led by its interrupt, then its
interrupt can also be serviced.

flags:

No flags affected

Instruction
For_t:

Opcode
(Hex)

Opcode

6

9F

Example:

If control register 222 contains

~mo,

(i.e., interrupts are disabled), the statement

EI

sets control register 222 to %01, enabling all interrupts.

ENTER
Enter
ENTER
Operation:

SP
~P

I

IP
PC
IP

-------+-

SP - 2
IP
PC
~IP

IP +

This instruction is useful for the implementation of threaded-code languages. The contents
of the Instruction Pointer are pushed onto the stack. The value in the Program Counter is
then transferred to the Instruct ion Pointer.
The program memory word pointed to by the
Instruction Pointer is loaded lnto the Program Counter.
The Instruction Pointer is then
incremented by two.
flags:

No flags affected

Instruction
Format:

Opcode
(Hex)

Opcode

20

1F

551

ENTER
E'1ter (Continued)
EXllllple:

Before

~--------~-----~. After

Address.-_ _..,' Data

o ENTER

IP 100501

IF

41 Addr H 01}
42 Addr L 10
43 Addr H

PC 100401

(~

_,J,L

Memory

Address

IP~043 40

(::I::::I~"o
o

IPH
IPL

ENTER

41 Addr H
42 Addr L
43 Addr H

~

-----___-+-_21

r---'" Data

R,we,,,,
Memory

00
50

22 Data

Address

Stack

Data
Stack

EXIT
Exit
EXIT

Operation:

IP -+-

~SP

SP -+- SP +
PC _- lIP
IP _- IP .;.
This instruction i.s useful for the implementation of threaded-code languages. The stack is
POPed and lhe Instruction Pointer is loaded.
The program memory word pointed to by the
Instruction Pointer is loaded into the Program Counter.
The Instruction Pointer is then
incremented by two.
Flags:

No flags affected

Instruction
Forll8t:

Opcode

(Hex)

Opcode

552

2F

EXIT
Exit (Continued)
Example:
Before

After

Address ,-_ _-,Data

IP \

0050

PC \

0140

Address ,-_ _...,Data

1~50

PCL old 60}
51 PCH
00

~

140 EXIT

(J:}J ~O}
Address

Memory

50

Stack

0(J5Z

I

pcl

006(J

I~

~6(J

(Io.~" I

2F

old

21 IPL
22 Data

IP\

Data

Address

Stack

Main

,-,>

Data

Note:
The examples for ENTER, EXIT, and NEXT illustrate how these instructions could actually be
used together in a program.

INC
Increment
. INC

dst

(Jperation:

dst _- dst + 1

Flags:

C:

The contents of the destinat ion operand are incremented by one.

Z:
V:
S:

H:
0:

Unaffected
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if the result is negative; cleared otherwise.
Unaffected
Unaffected

Instruction
For...t:

Opcode

Cycles

dst10PcodeI

L-_(J_p_co_d_e_~11~____d_s_t__~

(Hex)

Addressing Mode
dst

6

rE*
r = 0 to F

6

20
21

R
IR

*This format is used in the example.

Example:
I f working register 1(J contains

~'2A,

the statement

INC R10

leaves the value

~'2B

in that register.

553

INCW
Increment Word
INCW

dst

Operation:

dst _- dst + 1
The contents of the dest inat ion (which must be an even address) and the byte following that
locatio\, are treated as a single, 16-bit value which is incremented by one.

Flags:

c:

i:
V:

S:
H:
0:

Unaffected
Set i f the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if the result is negative; cleared otherwise.
Unaffected
Unaffected

Instruction
format:

(Hex)

Addressing Mode
dst

AO*
A1

RR
IR

Opcode

'-_o-'pc_o_d_e_....1

I,_ _ _
d_s_t_--,

10

*This format is used in the example.
If working register pair 0-1 contains the value %FAF3, the statement

INCW RRO
leaves the value 1.FAF4 in working register pair 0-1.

554

IRET
Interrupt Return

Operation:

IRET (Nor...l)

lRET (fast)

Flags _- liSP
SP _- SP + 1
PC _- ti!SP
SP _- SP + 2

PC __ IP

SYM(O)

Flag _- Flag'
FIS _- 0

_- 1

This instruction is issued at the end of an interrupt service routine. It restores the Flag
register and the Program Counter. It also reenables global interrupts.
Normal IRET is executed only i f the fast Interrupt Status bit (r-rS, bit 1 of the Flags
register R213) is cleared.
Fast IRET is execut'!'d if FrS is set, indicating that a fast
interrupt is being serviced.
flags:

All flags are restored to original settings (before interrupt occurred).

Instruction
format:
Cycles

Opcode
(Hex)

Opcode

16

SF

IRET (fast)

Cycles

~

IRET (Nor...l)

Opcode
Opcode

6*

SF

*This format is used in the example.
Example:
In the figure below,

the Instruction Pointer is initially loaded with %100 in the main

program before interrupts are enabled.

When an interrupt occurs,

the Program Counter and

Instruction Pointer 'are swapped. This causes the Program Counter to jump to address %100
and the Instruction Pointer to keep the return address. The last instruction in t.he service
routine normally is a Jump to IRET at address %ff. This causes the Instruct ion Pointer to
be loaded with ~~100 "again", and the Program Counter to jump back to the main, program. Now
the next interrupt can occur and the Instruction Pointer is still correct at %100.
0

Ff IRET
100
Interrupt
Service
Routine
JP~~

to FF

FFFF

Note:
for the fast Interrupt example above, if the last instruction is not a Jump to IRET, then
care must be taken with the order of the last two instructions. The instruction IRET cannot
be immediatel y preceded by a clear of interrupt status (such as a reset of the Interrupt
Pending register).

555

JP
Jump
JP
JP

cc ,dst
dst

Operation:

If cc is true, PC _- dsl
The conditional Jump transfers program control to the destination address if the condition
specified by "cc" is true; otherwise, the instructiqn following the JP instruction is
executed., See section 5.3 for a list of condition codes.
The unconditional Jump simply replaces the contents of the Program Counter with the 'contents
of the specified register pair.
Control then passes to the statement addressed by the
Program Counter.

Flags:

No flags affected

Instruction
ForMat:

Opcode

Cycles
Conditional

Unconditional

cc

I

Opcode

I

~_o_p_co_d_e__~1 ~I

dst

____

d_s_t__

~

10/12*

(Hex)

Addressing Mode
dst

cco**

DA

cc = 0 to F

10

30

IRR

*12 i f jump taken, 10 if not
**This format is used in the example.

[xBllple:
I f the Carry flag is set to 1, the statement
JP C,%1520
replaces the contents of the Program Counter with %1520 and transfers control to that
location.
Had the Carry flag not been set, control would have fallen through to the
statement following the JP.

556

JR
Jump Relative
JR

cc ,dst

Operation:

If cc is true, PC _- PC + dst.
If the condition specified by "cc" is true, the relative address is added to the Pragram
Counter and control passes to the statement whose address is now in the Program Counter;
otherwise, the instruction following the JR instruction is executed. (See section S.' for a
list of condition codes.) The range of the relative address is +127, -128, and the original
value of the Program Count.er is taken to be the address of the first instruct ion byte
following the JR statement.

flags:

No flags affected

Instruction
rorat:
Cycles
cc 10Pcodei

dst

10/12*

Opcode
(Hex)

ccB
cc = 0 to

Addreasing Mode

.!!!l
r

RA

* 12 if jump taken, 10 if not

Ex ....ple:
If the result of the last arithmetic operation executed is negative, then the four following
statements (which occupy a total of seven bytes) are skipped with the statement
JR MI, $+9
If the result is not negative, execution continues with the statement following the JR.
short form of a jump to label LO is

A

JR LO
where LO must be within t.he allowed range. The condition code is "blank" in this case, and
JR has the effect of an unconditional JP instruction.
Note:
The $ refers to the addreslI of the first byte of the instrucUon currently being executed.

557

LO

Load
LD

dst ,src

Operation:

dst _- src
The contents of the source are loaded into the destinat ion.
unaffected.

flags:

The contents of the source are

No flags affected

Instruction
forlll8t:

Opcode

I
I
I
I
II I I
II
II
II
II
src

dstlOPcodel

dst

srclOPcodel
Opcode
Opcode
Opcode
Opcode
Opcode
Opcode

dst

II
II
II

src

Addressing Mode
~
!!!£

Cycles

(Hex)

6
6

rC
r8

6

r9
r=O to F

R

6
6

C7
07

r
Ir

Ir

1M

r

R

src

dst

10
10

E4
E5

R
R

R
IR

dst

src

10
10

E6
06

R
IR

1M
1M

dst

10

F5

IR

R

x'

10

87

x

10

97*

src
dst

src

src

dst

II
II
II

x(r)
x( r)

*This format is used in the example.

[x_pIe:
If working register 0 contains %08, ('11 decimal) and working ,register 10 contains 1.83, the

statement
LO 240(RO) ,R10
loads the value 1.83 into register 251 (240 +11).
unaffected by the load.

558

The contents of working register 10 are

LOB
Load Bit
LD8

LOO

dst,src,b
dst,b,src

Operation:

dst(O) -+- src(b)
or
dst(b) _- src(O)
The specified bit of the source is loaded into bit 0 of the destination, or bit 0 of the
source is loaded into the specified bit of the destination.
No other bits of the
destination are affected. The source is unaffected.

Flags:

No flags affected

Inst ruet ion
format:
Opcode
Opcode

II
II

dst

b

src

b

1°1
111

I
I

Cycles

Opcode
(Hex)

Addressing Mode
~
!!:.£

src

10

47

rO

Rb

dst

10

47

Rb

ro

[x8lllple:
If working register 3 contains

~mo

and working register 5 contains %FF t the statement

lOB R3,R5,H7
leaves the value %01 in working register 3.

559

LDE/LDe
Load Memory
lIlE/lOC

dst, src

Operation:

dst _- src
This instruct ion is used t.o load a byte from program or data memory into a working register
or vice-versa. The contents of the source are unaffected.
No flags affected

flags:
Instruction
format:

Opcode

(Hel<)

src 1

12

C3

1 src

dst I

12

D3**

Irr

r

1 dst

src II'--_xs---II

18

E7

r

xs (rr)

I src

dst II'--_xs---,I

18

F7

xs( rr)

20

A7

1'--_X--'-lH'----I 20

87
A7

,-_o_p_c_od_e_-,II dst
Opcode

Opcode
Opcode
Opcode

Addressing Mode
!!!!!.
src

Cycles

I dst I src* II'--_X--=\o...-....JIIl--X--,-lH'-----i
I src I dst *

1

I

xl L

I

,-_op_c_o_de_....J1 1 dst

00001 1

DA L

I'--__D_A_H_....J 20

,--_o_pc_o_d_e_....J1 I src

00001 I

DA L

1..1

20

87

,--_o_pc_o_d_e_....J1 1 dst

0001 1 1

DA L IL.__D_A-:..;H_...... 20

A7

,-_o_p_co_d_e_....J1 I src

0001 1 1

DA L

L.I__D_A_H_-, 20

B7

~_D_A_H,,-~

Irr

xl( rr)

xHrr)

DA \ Program
Memory
DA

DA

1

Data
Memory

DA

*The src or (rr) cannot use register pair 0-1.
**Thisformat'is used in the example.
[l 255; cleared otherwise.
Set if the result is 0; cleared otherwise.
Cleared
Set if MSB of the result is a 1; cleared otherwise.
Unaffected
Unaffected

Instruction
format:
Cycles
,--_o_pc_o_d_e_-,I

1...._-,s_r_c_.....J1

Opcode
(Hex)

24
24
24
*This format

1....__d_s_t_.....J

Addressing Mode
~
!!£.

84*
RR
R
1R
85
RR
RR
1M
86
is used in the example.

Example:
If working register 6 contains %40 (64 decimal) and working register 4. contains %42 (66
decimal), the statement
MULT RR6, R4
leaves the value %10 in working register 6 and
decimal) •

~~80

in working register 7 (%1080 is 4224

565

NEXT
Next
r£XT
PC _- !UP
IP _- IP + 2

Operation:

This instruction is useful. for t.he implementation of threaded-code languages. The program
memory word pointed to by, the Instruction Point.er is loaded into the Program Counter. The
Instruction Pointer is then incremented by two.
Flags:

No flags affected

Instruction
Forll8t:

Opcode

(Hex)
14

,-_o_p_c_o_de_--,I

OF

Example:
Before

After

Address r-_ _.,Data

Address r----, Oat a

~

43AddrH

01 }
44 Addr L 30
45 Addr H

43 Addr H
44 Addr L
'~45AddrH

IP 0043

IP~

PC~

~~

\...120 NEXT
Memory

130 Routine
Memory

Note':
The examples for ENTER, EXIT, and NEXT illustrate how they could actually be used together
in a program.

566

NOP
No Operation

Operation:
No action is performed by this instruction.
Flags:

It is typically used for liming delays.

No flags affected

Instruction
Forllllt:

Opcode

Cycles
Opcode

6

(Hex)
FF

OR
Logical OR
OR

dst,src

Operation:

dst

~-

dst OR src

T?e source operand is logically ORed with the destination operand and the result is stored
in the destination. The contents of the source are unaffected. The OR operation results in
a 1 bit being stored whenever either of the corresponding bits in the two operands is 1 j
otherwise a 0 bit is stored.
Flags:

C:

Z:

V:
5:
H:
D:

Unaffected
Set i f the result is OJ cleared otherwise.
Always cleared to 0
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

Instruction
For.... t:
Opcode
Opcode
Opcode

II
II
II

dst

src
src
dst

I
II
II

dst
src

Cycles

Opcode
(Hex)

Addressing Mode
dst
!!£

6
6

42
43

10
10

44
45

R

R

R
IR

10

46*

R

1M

r

r
Ir

*This format is used in the example.
[x_pIe:
If the source operand is the immediate value %78 (01111011) and the register named TARGET
contains roc3 (11000011), the statement

OR TARGE T, 11',.78
leaves the value r.FB (11111011) in register TARGET.

567

POP
Pop
pop

dst

Operation:

dst
IilSP
SP _- SP +
The contents of the location addressed by the Stack
destination. The Slack Pointer is then incremented by' one.

Pointer

are

loaded

into

the

No flags affected

Flags:
Instruction
for_t:

Opcode
(Hex)

~_o_pc_o_d~e__~I'L ____ds_t__~

10
10

Addressing Hode
dst
R

50
51 *

IR

*This format is used in the example.
Example:
If the Stack Pointer (control registers 216-217) contains %1000, external data memory
location %1000 contains %55, and working register 6 contains %22 (34 decimal), the statement
POP IilR6
loads the value %55 into register 34.

A fter the POP operation, the Stack Pointer contains

%1001.

POPUD
POp User Stack (Decrementing)
POPIJ)

dst, src

Operation:

dst _- src
IR _- IR This instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user Stack Pointer are loaded into the destination.
The user Stack Pointer is then decremented.

Flags:

No flags affected

Instruction
forlDat:

Opcode

Cycles
Opcode

II

src

II

dsl

10

(Hex)

Addressing Hode
dst
src

92

R

IR

Example:
If the user Stack Pointer (register %42, for example) contains ~'80 and register ~'80 contains
5A, the statement

POPUD R2,1il%42
loads the value %5A into working register 2.
Pointer contains %7F.

568

After the PDP operation,

the user Stack

POPUI
Pop User Stack (Incrementing)
POPUI dst,src
Operation:

dst . - src
IR . - IR + 1
This instruction is used'for user-defined stacks in the register file. The contents of the
negister file location addressed by the user Stack Pointer are loaded into the destination.
The user Stack Pointer is then incremented.

naga:

No flags affected

InstructiQrl
ForEt:

Opcode
Opcode

II

src

II

Addreaaing Mode

Cycles

...!!!!!L

!!!t

!!£

10

93

R

IR

dst

[xa.ple:
If the user Stack Pointer (register %42, for example) contains
,the statement

~BO

and register

~O

contains

~5A,

POPUI R2,Ml42
loads the value ~5A
Pointer contains r,B1.

~nto

working register 2.

After the POP operation, the user Stack

PUSH
Push
PUSH src
'Operation:

SP

asp

_- SP - 1
+- src

The contents of the Stack PO'inter are decremented, then the contents of 'the source are
loaded into the locat ion addressed by the decremented Stack Pointer, thus adding a new
element to the top of the stack.
flags:

No flags affected

Instruction
Forllllt:

Opcode
(Hex)

Cycles
Opcode

II

src

10
12
12
14

Internal
External
Internal
External

stack
stack
stack
stack

Addreaaing Mode
!!!;.

70*

R

71

IR

*This format is used in the example.
[x8llple:
'If the Stack Pointer contains r,1001, the statement
PUSH fLAGS
stores the contents of the register named fLAGS in location
operation, the Stack Pointer contains ~1000.

~1000.

After the PUSH

5S9

PUSHUD
Push User Stack (Decrementing)
PUSHOO dst,src
OperatiOn:

IR _- IR:- 1 '
dst _- src

This instruction is used for user-defined stacks in the register file.
The user Stack
Pointer is decremented, then the' contents of the 'source are loaded into ,the register file
locat ion a,ddressed by the decremented user Stack P,?inter.
No flags affected

Flags:

InstJ:uction
Forllat:

Opcode

(Hex)
,-_o_pc_o_de_-,III-_ _d_s_t_-,I

I-I_ _s_rc_,_",1-

10

82

Addresaing Mode
dst
!!:£
IR

R

,Ex_pIe:
If the user Stack Pointe,r (%42, for example) contains %81, the statement
PUSHlJO i%42,R2
stores the contents of working register 2 in location %80.
user Stack Pointer 'contains %80.

After the PUSH operation, the

PUSHUI
Push User Stack (Incrementing)
Push User Stack (Iocr_hting)
PUSHUI

dst , src

OpersUoOl

IR .. - IR + 1
dst 1'""- src

This instruction is used for user-defined stacks in 'the register file 0
The user Stack
Pointer is incremented, then the contents of the source are loaded into the register file
location addressed by the incremented user Stack Pointer.
Flags:

No flags affected

Instruction
ForMt:

Opcode

,--_o_pc_o_d_e_....J11I-__'_ds_t_--,II,--_s_r_c_--,

,Cycles

(Hex)

10

83

Addressing Mode
~
!!:£
IR

RI

Exa.ple:
If the user Stack Pointer (%42, for example) contains %81, the statement
PUSHUI i%42,R2
stores the contents of working register 2 in location %82:
user Stack Pointer contains %82.

570

After the PUSH operation, the

ReF
Reset Carry Flag
Ref
C _- 0

Operation,

The Carry flag is cleared to 0, regardless of its previous value.
Flags,

C,

Cleared 'to 0
No other flags affected

Instr.uct ion
format,

Opcode
(Hex)

Opcode

Cf

RET
Return
RET
Operation,

PC _- rasp
SP _- SP + 2
This instruction is normally used to return to the previously executing procedure at the end
of a procedure entered by a CALL instruction. The.contents of the location addressed by the
Stack Pointer are popped into the Program Count en
The next statement executed is' that
addressed by the new contents of the Program Counter

Flags:

No flags affected

Instruction
format,

Opcode

Cycles

Opcode
(Hex)

14

AF

Example,

the Program Counter contains %35B4, the Stack Pointer contains %2000, external
data memory location %2000 contains %18, and location %2001 contains ~'B5, then the statement

If

RET
leaves the value ?2002 in the Stack Pointer and %18B5, the address of the next instruction,
in the Program Counter.

571

RL
Rotate Left
Rl

dst

Operation:

C 4-- dst (7)
dst (0) 4-- dst (7)
dst (n + 1) 4-- dst (n) n = 0 - 6
The contents of the destination operand are rotated left one bit position.
value of bit 7 is moved to the bit 0 position and also replaces the Carry flag.

flags:

c:
l:

V:
S:
H:
D:

The initial

Set if the bit rotated from the most significant bit posit ion was 1, i. e., bit 7 was 1.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleated otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

lnat ruction
Format:

Opcode
(Hex)

~_o_Pc_o_.d_e__~1 ~I

___

d_s_t__

~

6
6

Addressing Hode

90"
91

!!.!!!.
R

IR

"This format is used in the example.
Example:
If the contents of the register named SHIFTER are %88 (10001000), the statement
RL SHIFTER
leaves the value
1.

572

~~11

(00010001) in that register and the Carry and OverflQw flags are set to

RLC
Rotate Left Through Carry
RlC

dst

Operation:

dst (0) _- c
C _- dst (7)
dst (n + 1) _- dst (n) n

=0

- 6

The contents of the destination operand with the Carry flag are rotated left one bit
position.
The initial value of bit 7 replaces the Carry flag; the initial value of the
Carry flag replaces bit O.

~_7
flags:

C:
Z:
V:

5:

H:
0:

_p

Set if the bit rotated from the most significant bit posit ion was 1, i.e., bit 7 was 1.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the sign of the destinat ion changed
during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

Instruction
Opcode

romat:

(Hex)

~_o_pc_o_d_e__~1 ~I

____

ds_t__

~

6
6

10*
11

Addressing Hode
~
R
IR

*This format is used in the example.

Ex ....ple:
If the 'Carry flag is cleared to 0 and the register named SHIFTER contains %8F (10001111),
the statement
RLC SHIFTER
sets the Carry and Overflow flags to 1 and leaves the value %lE (00011110) in SHIFTER.

573

RR
Rotate Right
RR

d,st

Operation:

C _- dst (0) •
dst (7) _- dst (0)
dst (n) _- dst (n + 1) n = 0 - 6
The contents of the destinetion operand are rotated right one bit position.
value of bit 0 is moved to bit 7 and also replaces the Carry flag.

flags I

The initial

I

C:

Set if the bit rotated from the least significant bit position was 1, i.e., bit 0 was 1.

V:

Set if arithmetic overflow occurred, that is, if the sign of the destination changed
during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected'

Z: Set if the result is 0; cleared otherwise.

S:
H:
0:
Inst ruction
fortlat:

Cycles
,--_o_p_co_d_e_....1

I....._d_s_t_--'

6
6

Opcode
(Hex)

Addressing Mode

.!!&

EO*'

R

E1

IR

*This format is used in the example.
EXSllple:
If the contents of register 6 are 1.131 (00110001), the statement
RR R6

sets the Carry flag to 1 and leave the value %98 (10011000) in working ,register 6.
bit 7 now equals 1, the Sign and Overflow flags are a1'so set to 1.

574

Since

RRC
Rotate Right Through Carry
RRC

dst

Operation: .

dst (7) _- C
C _- dst (0)
dst (n) _- dst (n + 1) n

=0

- 6

The content.s of the destination operand and the Carry flag are rotated right one bit
position.
The initial value of bit 0 replaces the Carry flag; the initial value of the
Carry flag replaces bit 7.

flags:

C:
Z:
V:

S:

H:

0:

Set i f the bit rotated from t.he least significant bit position was 1, i.e., bit 0 was 1.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the sign of the destination changed
during rotation; cleared otherwise.
.
Set i f the result bit 7 is set; cleared otherwis'1'
Unaffected
Unaffected

Instruction
rorllat:

Opcode

<-_o_p_c_od_e_--,I

I<-__d_st_ _...

Cycles

(Hex)

6
6

CO*
C1

Addressing Mode
dst
R

IR

*This format is used in the example.
EXlMlple:
If the contents of the register named SHIFTER are %DO (11011101), and the Carry flag is
cleared to 0, the statement
RRC SHIFTER
sets the Carry and Overflow flags to 1 and leaves the value %6E (01101110) in the register.

575

SBO
Set BankO
S80

Operation:

BANK _- 0
This instruction causes the Bank Address flag (bit 0) of Flag register 213 td be cleared to
O.

Flags:

No flags affected

Instruction
Format:

Opcode

(Hex)

Opcode

6

4F

SB1
Set Bank 1
581

Operation:

BANK _- 1
This instruct ion causes the Bank Address flag (bit 0) of Flag register 213 to be set to 1.

Flags:

No flags aFFected

Instruction
For_t:

Opcode
(Hex)

Opcode

576

6

5F

SBC
Subtract With Carry

soc

dst,src

Operation:

dst _- dst - src - C
The source operand, along with the setting of the Carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source
are unaffected.
Subtraction is performed by adding the twos complement of the source
operand to the destination operand.
In multiple precision arithmetic, this instruction
permits the carry ("borrow") from the subtraction of low-order operands to be subtracted
from the subtraction of high-order operands.

Flags:

C:
2:
Y:
S:
H:
0:

Set if a borrow occurred (src > dst); cleared otherwise.
Set if the result is 0; cleared otherwise.
,
Set if arithmetic overflow occured, that is, if the operands were of opposite sign and
the sign of the result is the same as the sign of the source; cleared otherwise.
Set if the result is neg at i ve; cleared otherwise.
Cleared if there is a carry from the most significant bit of the low-order four bits of
the result; set otherwise, indicating a "borrow. II
Al ways set to 1.

Inst ruction
format:
Opcode
Ope ode
Opcode

II
II
II

dst

src
src
dst

I
II
II

Cycles

Opcode
(Hex)

Addressing Hode
dat
arc

6
6

32
33*

dst

10
10

34
35

R
R

R
IR

src

10

36

R

1M

r
Ir

"This format is used in the example.
If the register named MINUEND contains %16, the Carry flag is set to 1, working register 10

contains %20 (32 decimal), and register 32 contains %05, the statement

sac MINUEND,
leaves the value

~R10
~~10

in register MINUEND.

577

SCF
Set Carry Flag
SCf
C .. - 1

Operation:

The Carry flag is set to 1, regardless of its previous value.
flags:

c:

Set to 1
No other flags affected

Instruction
format:

Opcode
(Hex)
Opcode

Df

SRA
Shift Right Arithmetic
SRA

dst

Operation:

dst (7) .. - dst (7)
C _- dst (0)
dst (n) _- dst (n' + 1) n = 0 - 6
An arithmetic shift right one bit position is performed on the destination operand. Bit 0
replaces the Carry flag. Bit 7 (the sign bit) is unchanged, and its value is also shifted
inlo bit posit ion 6.
6

ddJl
flags:

C:
Z:

V:
S:
H:

0:

o

~

Set i f the bit shi fted from the least significant bit posi t ion was 1, i. e., bit 0 was 1.
Set if the result is 0; cleared otherwise.
Always cleared to 0
Set if the result is negat i ve; cleared otherwise.
Unaffected
Unaffected

Instruction
format:

Opcode
(Hex)

~_o_p_co_d_e__~11~

____

d_s_t__

~

6
6

DO*
D1

Addressing Hode
~
R
IR

*This format is used in the example.
Example:

If the register named SHIfTER contains %B8 (10111000), the statement
SRA SHIFTER
clears the Carry flag to 0 and leaves the value %DC (11011100) in, the register SHIfTER.
Sign' flag is set to 1.

578

The

SRP/SRPO/SRP1
Set Register Pointer
SRP /SRPO/SRP1

src

Operation:

=1
=0
=0

If src (1)

If src (1)
If src (1)

=0

then:

RPO (3-7)

and src (0)

then:

RP1 (3-7)

and src (0)

0 then:

and src (0)

RPO
RPO
RP1
RP1

4--

src (3-7)
src (3-7)

(4-7) 4-- src (4-7),
(3) 4-- 0
(4-7) 4-- src (4-7),
(3) ..- 1

The source data bits 1 and 0 determine if one or both of the Register Pointers is to be
written.
Bits 3-7 of the selected Register Pointer are written unless both Register
Pointers are selected. Then bit 3 of RPO is forced to a 0 and bit 3 of RP1 is forced to a
1.
Flags:

No flags affected

Instruction
Forllat:

-JI ~I____

~_o_p_c_od_e__

s_r_c__

~

Opcode
(Hex)

Addressing Mode

31

1M

!!:£

Examples:
(1) The statement
SRPO 1/%50
sets Register Pointer 0 (control register 214) to %50.
The assembler produces this code: 31 52.
(2) The statement
SRP1 #%68
sets Register Pointer 1 (control register 215) to %68.
The assembler produces this code: 31 69.
(3) The statement
SRP 11%40
sets Register Pointer 0 to %40 and Register Pointer 1 to %48.
The assembler produces this code: 31 40.

579

SUB
Subtract
SUB

dst,src

Operation:

dst

~-

dst - src

The source operand is subtracted from the destination operand and the result is stored in
the destination. The contents of the source are unaffected. Subtraction is performed by
adding the twos complement of the source operand to the destination operand.
flags:

c:
Z:
V:
S:
H:

0:

Set if a "bor row" occurred; cleared otherwise.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occured, that is, if the operands were of opposite signs and
the sign of the result is the same as the sign of the source operand; cleared otherwise.
,Set if the result is negative; cleared otherwise.
Cleared if there is a carry from the most significant bit of the low-order four bits of
the result; set otherwise indicating a "borrow."
Always set to 1.

Instruction
ForllBt:

Opcode
Opcode
Opcode

II
II
II

dst

src
src
dst

I
II
II

Cycles

Opcode
(Hex)

Addressing Mode
dst
!!:£

6
6

22
23

dst

10
10

24
25

R
R

R
IR

src

10

26"

R

1M

r
Ir

"This format is used in the example.
Example:
If the register named MINUEND contains %29, the statement
SUB MINUEND,. /1%11
leaves the value %1 B in the register.

580

SWAP
Swap Nibbles
liWAP

dst

Operation:

dst (0 - 3) __ dst (4 - 7)
The contents of the lower four bits and upper four bits of the destination operand are
swapped.
7

Flags:

c:
Z:
V:

s:
H:
D:

4 3

o

Undefined
Set i f the result is OJ cleared otherwise.
Undefined
Set i f the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

Instruction
format:

Opcode
(Hex)

,-_o_p_co_d_e_.....1

....
I __
ds_t_--,

Addressing Hode
dst

8
FO*
R
8
F1
IR
*This format is used in the example.

Ex.pIe:
If the register named BCO_Operands contains %B3 (10110011), then the statement

SWAP BOC_Operands
leaves the value %3B (00111011) in the register.

581

reM

Test Complement Under Mask
TCM

dst,src

Operation:

(NOT dst) AND src
This instruction tests selected bits in the destinat ion operand for a logical "1" value.
The bits to be tested are specified by setting a 1 bit in -the corresponding position of the
source operand (mask). The TCM statement complements the destination operand, which is then
ANDed with the source mask. The Zero (Z) flag can then be checked to determine the result.
The destinat ion and source operands are unaffected.

Flags:

C.

Unaffected

Z. Set if the result is 0; cleared otherwise.
Y. Always cleared to o.
5.

Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

H.
D.
Instruction
For....t:

Opcode

Opcode
Opcode
Opcode

II
II
II

dst

src
src
dst

I
II
II

Addressing Mode

Cycles

(Hex)

!!!t

!!:£

6
6

62*
63

r

r
Ir

dst

10
10

64
65

R
R

R
IR

src

10

66

R

1M

*This format is used in the example.

Example:
If the register named TESTER contains %F6 (11110110) and the register named MASK contains
%06 (00000110), that is, bits 1 and 2 are being tested for a 1 value, then the statement

TCM TESTER, MASK
complements TESTER (to 00001001) and then does a logical AND with register MASK, resulting
in %00. A subsequent test of the Z flag
JP Z, label
causes a transfer of program control.
%F6.

582

At the end of this sequence, TESTER still contains

TM
Test Under Mask
TN

dst,src

Operation:

dst AND src
This instruction tests selected bits in the destination operand for a logical "0" value.
The bits to be tested are specified by setting a 1 bit in the corresponding position of the
source operand (mask), which is ANDed with the destination operand. The Zero (Z) flag can
then be checked to determine the result.
The destination and source operands are
unaffected.

Flags:

Unaffected
Set if the result is OJ cleared otherwise.
Always reset to O.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

C:
Z:
V:

s:

H:
0:

Instruction
Format:

Opcode
Opcode
Opcode
Opcode

II
II
II

dst

src
src
dst

I
II
II

dst
src

Addressing Hode
dst
src

Cycles

(Hex)

6
6

72*
73

r
r

r
Ir

10
10

74
75

R
R

R
IR

10

76

R

1M

*This format is used in the example.

Ex ...ple:
If the register named TESTER contains %F6 (11110110) and the register named MASK contains
%06 (00000110), that is, bits 1 and 2 are being tested for a 0 value, then the statement

TM TESTER, MASK
results in the value %06 (00000110).

A subsequent test for nonzero

JP NZ, label
causes a transfer of program control.

At the end of this sequence, TESTER still contains

~~F6.

583

WFI
Wait For Interrupt

wn
Operati'OIl:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers still
take place in the halt state. Either a fast interrupt or normal interrupt can take the CPU
out of the halt state.
Flags:

No flags affected

Instruction
J;ormal:
Opcode

Cycles

Opcode
(Hex)

6n

3f

n

Example:
Main Program

t

EI
\If I

(Enable Global Interrupt)
(Wait for Interrupt)

(next instruction)

-'n~erruPt occurs
Interrupt Serv ice Rout ine

Clear Interrupt flag
IRET

Done with service routine

584

= 1,2,3, •••

XOR
Logical Exclusive OR
XOR

dst,src

Operation:

dst _-' dst XOR src
Tne source operand is logically EXCLUSIVE ORed with the destination operand and the result
is stored in the destination.
The EXCLUSIVE OR operation results in a 1 bit being stored'
whenever the corresponding bits in the operands are different; otherwise, a 0 bit is stored.

Flags:

c:
Z:

Y:
S:
H:
D:

Unaffected
Set if the result is 0; cleared otherwise.
Always reset to O.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected

Instruct ion
rorllat:
Opcode
Opcode
Opcode

II
II
II

dst

src
src
dst

I
II
II

Addressing Mode
~
~

Cycles

Opcode
(Hex)

6
6

82·
83

dst

10
10

84
8'5

R
R

R
IR

src

10

86*

R

1M

r
Ir

*This format is used in the example.
EXaRlpIe:
If the source is the immediate value %78 (01111011) and the register named TARGET contains
%C3 (11000011), the statement
XOR TARGET, 11%78
leaves the value %88 (10111000) in the register.

585

Chapter 6
Interrupts
6.1

INTRODUCTION

The interrupt structure of the SuperB consists of
27 different interrupt sources, 16 vectors, and B
levels (Figure 6-1).
Two of the vectors are
reserved for future members of the SuperB family.

A source is anything that generates an interrupt.
This can be internal or external to the SuperB.
Internal sources are hardwired toa particular vector
and level, while external sources can be assigned to
various external events. External interrupts are
falling edge triggered.

Interrupt priority is assigned by level, which is
controlled' by the Interrupt Priority register
(IPR). Each level is masked (or enabled) according to the bits in the Interrupt Mask register
(IMR), and the entire interrupt structure can be
disabled by clearing bit 0 in the System Mode
register (R222).
The three major components of
the interrupt structure are sources, vectors, and
levels.
INTERRUPT SOURCES

COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P2,)
EXTERNAL INTERRUPT (P2,)
COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P36)
EXTERNAtlNTERRUPT (P37)

6.1.2

Vectors

The vector number is used to generate the address
of a particular interrupt serv1c1ng routine;
therefore all interrupts using the same vector
must use the same interrupt handling routine.

-I'
POLLING

.
l

i

VECTORS

--:-12-

:

LEVELS

~2
I

1

I

I

tlROS
I

114

~:~ft~:tl~~~:~~~i ~P24) I

EXTERNAL INTERRUPT (P2,)

~:~~~;~K,~~~:~~~i ~34) }

EXTERNAL INTERRUPT (P3,)
RESERVED

IRQ3

RESERVED

EXTERNAL INTERRUPT (P32)
EXTERNAL INTERRUPT (P2,)

I
IROO

EXTERNAL INTERRUPT (P2,)

EXTERNAL INTERRUPT (P33)
UART RECEIVE OVERRUN
lfART FRAMING ERROR

UAAT PARITY ERROR
UART WAKEUP DETECT
, UART BREAK DETECT
UART CONTROL CHAR DETECT

UAAT RECEIVE DATA
EXTERNAL INTERRUPT (P30)
EXTERNAL INTERRUPT (P20)

UART ZERO COUNT
EXTERNAL INTERRUPT (P2d
UAAT TRANSMIT DATA
EXTERNAL INTERRUPT (P3d

1 18
IR06

1
I

=:::::j:=:::Jt-------{ 20
122
I
I
I 2'

!

Figure 6·1. Interrupt Structure

586

26

I

IRQ1

Interrupts
When more than one vector shares an interrupt
level, the priorities of the vectors on that level
are fixed. Figure 6-1 lists the vectors within a
level in the order of decreasing priority (i.e.,
the top vector in each level has the highest
priority).
For example, for IRQ6, vector 16
slways has priority over vectors 1B, 20, and 22.

Although it does not cover all possible combinations, the Interrupt Priority register does
provide the capability of assigning 192 different
combinations of priority among the interrupt
levels.
For example, an IPR with the contents
01101011 would have the following priority order
. (Figure 6-3):
If more than one interrupt source is active, the

6.1.3 Levels

source from the highest priority level is serviced
first. If both sources are from the same lev·e I,
the source with the lowest vector number has
priority. For example, if the UART Receive Data
bit and UART Parity Error bit are both active, the
UART Parity Error is serviced first because it is
vector 16 and the UART Receive Data bit is vector
20.

While the sources and vectors are hardwired within,
each level, the priorities of the levels can be
changed by using the Interrupt Priority register
(R255, Bank O) (Figure 6-2).

R255 BANK 0 (FF) IPA

INTERRUPT PRIORITY REGISTER

GROUP PRIORITY

I

I

07 0 401

I Lo =

GAOUPA
1

UNDEFINED

IROO > IRQ1

=IRQ1 >IRao

-----:-- o = IAQ2 > (IAQ3,IAQ")
GROUPS

B>C>A
A>B>C
B>A>C
C>A>B
C>B>A
A>C>B

1

=(IAQ3,IAQ") > IAQ2

SUBGAOUPB
o IA03 > IRQ4

=

1

UNOEFINED

= IRQ4 >IAQ3

GAOUPC
o = IAQS > (IAQ6,IAQ7)
1 (IAQ6,IAQ7) > IAQS

=

SUBGAOUPC

o = IROS > IRQ7
1

= IRQ7> IR06

Figure 6-2. Interrupt Priority Register
EXAMPLE: An IPR with the contents 011 01 011 would have
the following priority order:
HIGHEST
B22
IAQO

IAQ1

IAQ2

IAQ3

IAQ"

C22
IAQS

lAOS

I

UNDEFINED
B>C>A
A>8>C

B>A>C
C>A>B
C>B>A
A>C>B
UNOEFINED

~.
.

A1>A2
A2>A1
1
0 81>82
1 82>81

GROUPS

IRQ? }
IRQ6
IRQ5

GROUpe

IRQ1 }
IRQO

GROUPA

IAQ?

I~I~I~I~I~I~I~I~I
000
001
010
011
100
101
110
111

IRQ2 }
IRQ4
IRQ3

LOWEST

0 821>822
1 822>821 ,
0 C1>C2

1 C2>C1
0 C21>C22
1 C22>c21

Figure 6-3. Interrupt Priority Tree

587

Interrupts
When an interrupt occurs, the software is automatically vectored to one of 16 possible service
routines. If more than one active source shares
that vector, the software must poll the individual
sources connected with that vector to find the
interrupting source or sources. Each interrupt
source has its own Interrupt Enable bit located in
the mode and control registers of the I/O section

Table

6~1.

associated with the source. The software has
complete control over which sources are a,llowed to
cause interrupts. If only one source associated
with a particular vector is enabled, then when an
interrupt occurs that uses that vector, no polling
is required and the software is automatically
vectored to the appropriate service routine.

SuperB Vector Address Table

Vectors

588

(DecDal tt-ory Address)

levels

30,31

IRQ7

P34 External Interrupt or HS1 /
P3 5 External Interrupt

28,29

IRQ4

P24 External Interrupt or HSO /
P25 External Interrupt

26,27

IRQ1

UART Transmit Data /
P3 1 External Interrupt

24,25

IRQ1

UART Zero Count /
P2 1 External Interrupt

22,23

IRQ6

P20 External Interrupt

20,21

IRQ6

UART Receive Data /
P30 External Interrupt.

18,19

IRQ6

16,17

IRQ6

UART Overrun / Framing /
Parity

14,15

IRQ5

Counter 1 Zero Count /
P36 External Interrupt /
P37 External Interrupt

12,13

IRQ2

Counter 0 Zero Count /
P26 External Interrupt /
P27 External Interrupt

10,11

IRQO

P3 3 External Interrupt

8,9

IRQO

P23 External Interrupt

6,7

IRQ3

P2 2 External Interrupt

4,5

IRQ3

P32 External Interrupt

2,3

IRQ3

Reserved

0,1

IRQ3

Reserved

Interrupt SourceS

'UART Break / Control Character /
Wake-Up

Interrupts
6.1.4 Enables

The SuperB then enters an interrupt mechine cycle
thst completes the-following sequence:

Interrupts can be ensbled or disabled as follows:
•

•

Interrupt enable/disable. The entire interrupt
structure can be enabled or disabled by setting
bit 0 in the System Mode register (R222).
level enable. Each level can be enabled or
disabled by setting the sppropriate bit in the
Interrupt Mssk register (R221).

•

level priority. The priority of each level csn
be controlled by the values in the Interrupt
Priority register (R255, Bank 0).

•

Source enable/disable.

Each interrupt source
can be ensbled or disabled in the source's Mode
and Control register.

•

Resets the Interrupt Enable bit to dissble all
subsequent interrupts

•

Ssves the Program Counter and ststus flags on
the stack

•

Branches to the address contained within the
vector location fo~ the interrupt

•

Passes control
routine

to

the

interrupt

servicing

Interrupts can be re-enabled by the interrupt
handling routine (EI instruction), - which allows
interrupt nesting. First, however, the contents
of the Interrupt Mask reg~ster should be saved and
a new mask loaded which disables the present level
being serviced and all lower levels.

6.1.5 The Interrupt Routine
Interrupts are sampled st the end of each instruction., -Before an interrupt request can be granted
s) interrupts must be enabled, b) the level must
be enabled snd must be the highest priority interrupting level, and c) the interrupt request must
be enabled st the interrupting source and must
have the highest priority within the level.
If all this occurs,
grsnted.

an interrupt request is

When the interrupt handling routine is finished,
it should issue an Interrupt Return (IREn
instruction.
This instruction restores the_
Program Counter and status flags from the stack
and sets the Global Interrupt Enable bit.
If
nesting was used, the interrupt handling routine
should first execute s Disable Interrupt (01)
instruction and restore the saved mask before
executing the IRET instruction. Figure 6-4
illuatratea the interrupt cycle process that
occurs when sn interrupt requsst occurs.
P2AIP= %FC
P2SIP=%FD

EI

S

HWRESETOR
POWER-UP RESET

R

1------ :C~NG

QI-_--'........

IN~~~~~ - - - - - - - '

IPR=%FF

INTERRUPT PRIORITY
REGISTER

VEC10R
INTERRUPT
CYCLE

SYM=%OE

SYSTEM MOOE

Figure 6·4. Interrupt Cycle ProceSs

589

Interrupts
6.2 FAST INTERRlPT PftQCES5It«l

The SuperB provides a feature' called fast interrupt processing, which completes the interrupt
servicing in 6 elock periods instead of the usual
22.
Anyone of the eight interrupt levele can be
programmed to use this feature by loading the fast
interrupt select field of the'System,Mode register
(R222) with the le,vel number and !letting the fast
Interrupt Enable bit.

interrupt routine. While fast interrupt processing is snabled, normal interrupt processing still
functions for the unselected levels.
The SuperB eupports both polled and interruptdriven systems or a combination of both.
To
accommodate a. polled structure or a partially
polled structure, sny or all of the interrupt
levels can be masked and the individual bits of
the IRQ register polled.

6.3 ClEARIt«l THE INTERRIJ>T SOURCE

Two hsrdwsre registers sllPport fsst interrupts.
The Instruction Pointer (IP) holds the starting
address of the service routine and ssves the
Program COllnter (PC) value when a fast interrupt
occurs. A dedicated register, flag', saves the
contents of the flag register when a fast interrupt occurs.
To use this feature, softwsre must first set the
Instruction Pointer to the starting location of
the interrupt service routine during initialhation and before interrupts are enabled for the
first time. Then the level number is loaded into
the fast Interrupt Select field and the fast
Interrupt Enable bit in the System Mode register
is turned on.
When an interrupt occurs in the level selected for
fast interrupt processi~g, the following occurs:
•

The contents of the Instruction Pointer and the
Program Counter are swapped.

•

The contents of the flag regieter are copied
into flag'.

•

The Fast I~terrupt Statua bit in the flag
register ie set.

•

The interrupt is serviced.

•

When IRET is issued after the interrupt service
routil]e 'is completed, the Instruction Pointer
and the Program Counter are swapped again.

•

The contente of flag' are copied back into the
Flag register. '

•

The Fast Interrupt Status bit' in the nag
register is cleared.

Internally, the interrupt requests are represented
as levels.' This level-sctivated aystem requires
that the software that services an interrupt'muat
perform some action that removes the interrupting
source before re-enabling that interrupt.
For, ,external interrupt inputs on the Port 2 &nil 3
pins, edge-triggered "interrupt pending" flipflopa are used to convert an edge-triggered input
to a level-activated ·interrupt. Thus, the service
routine must reset the interrupt pending flip-flop
to clear the interrupt request by writing to the
Port 2/3 Interrupt Pending register.
For receive character available interrupts from
the UART receiver, emptying the Receive Data
register
(UlOR)
will
automatically
clear
the interrupt source. for receiver interrupts due
to a receive error, detection of a control character, or detection of the wake-up condition, resetting the appropriate statua bit in the Receive
Control register (URC) will clear the interrupt
aource. For interrupts from the UART transmitter,
filling the Transmit Data register (UlOT) will
automatically clear the interrupt source.
For end-of-count interrupts from the counter/
timers, resetting the Reset/End of COllnt Status,
bit (01) in the Counter Control register' will
clear the interrupt source.
for interrupts from the on-chip DMA channel, loading a non-zero value into the DMA Count register
will clear the interrupt source.

6.4

After the Interrupt Return (IRET) of a fast
interrupt, the Instruction Pointer (IP) will point
to the next byte fo1l9wing the . ..IRET • Before using
the fast interrupt again, the IP ehould be reinitialized to point, to the beginning of the

590

INTERRII'T CONTROl. REGISTERS

The interrupt hardware is controlled by fields in
the System Mode register (R222), the ~nterrupt
Request. register IRQ (R220), the Interrupt Mssk
register IMR (R221) , the Interrupt Priority
. register IPR (R255, Bank 0), and the fast Interrupt Status bit (fIS) of the Flags register
(R21l).

Interrupts

6.4.1

Systa. Mbde Register

rast Interrupt Enable (01)' When this bit is a 1,

The System Mode register (R222) controls the mode
of operation of the interrupt hardware.
The
format of the System Mode register is shown in
Figure 6-5.
The fields in this register
interrupt hardware are:

the fast interrupt processing feature is enabled
for the selected interrupt' level. When this bit is
a 0, fast interrupt processing is disabled. When
fast interrupt processing is used, the Interrupt
Mask Register bit for the selected level must also
be set.

pertaining to the

Fast Interrupt Select (0z-D4).

Global Interrupt Enable (DO)'

When this bit is
set to 1, interrupts are enabled. When this bit
is cleared to 0, all interrupts are disabled
regardless Qf the state of individual interrupt
enable or mask bits. This bit is automatically
cleared during an interrupt machine cycle and can
also be cleared by the DI instruction. It can be
set by using an El or IRET instruction. A hardware reset clears this bit.

The value of this
3-bit field se lects the interrupt level for fast
interrupt processing.
All other levels still
operate in the normal interrupt mode.
(Bit 7 relates to external memory and not to
interrupts.
For more details on bit 7, see
section 12.3.)

R222 (OE) SYM
SYSTEM MODE

TIl

I~I~I~I~I~I~I~I~I
1

=INTERFACE
3-STATE MEMORY

~

NOT USED

L=
1

GLOBALINTERRUPT ENABLE

1 = FAST INTERRUPT ENABLE
FAST INTERRUPT SELECT
000 LEVELO
001 LEVEL 1
010 LEVEL 2
011 LEVEL 3
100 LEVEL4
101 LEVEL 5
110 LEVELS
", LEVEL7

Figure 6-5_ System Mode Register

6.4.2

Interrupt Request Register

The Interrupt Request (IRQ) register (R220)
indicates which interrupt levels have pending
interrupts.
It takes a snapshot once for each
instruction near the end of execution. Each bit in
the register corresponds to one interrupt level.
Software can use the IRQ for polling those levels
that are not using hardware interrupts and have
Even when polling,
been masked off by theiMR.
the software is responsible for removing the
interrupting source when serv icing that source.

Writing to the IRQ has no effect. The interrupt
request must be renewed at the source, such as the
UART or a port.
External interrupts are disabled by a reset and
must be enabled via execution of an El instruction
before bits i~ the Port 2/3 Interrupt Pending
registers can be set and external hardware interrupts can occur.
The format of the Interrupt Request register is
shown in Figure 6-6.

R220 (DC) IRQ
INTERRUPT REQUEST (READ ONLY)

I~I~I~I~I~I~I~I~I
LEVEL

1JJ~

LEVEL 6

=-.J

~ILLEVEL~
L
LEVEL 1

LEVEL 5

LEVEL 2

LEVEL 4

LEVEL 3

Figure 6-6. Interrupt Request Register

591

Interrupts

6.4.' Interrupt Mask Register

6.4.5 Fast Interrupt status Bit (ns of nags
Register)

The Interrupt Mask (lMR) register (R221) is used
to mask individual interrupt levels, thus preventing interrupts at that level. A 1· enables interrupts at that level,
a 0 disables them.
Interrupts should be globally disabled before
writing to this register.
The format of the Interrupt Mask register is shown
in Figure 6-7.

This is a status bit; when it is set to 1, it
indicates that a fast interrupt. has occurred.
This bit determines what type of action is taken
during an lRET. If it is a 1, then an IRET causes
a swap between the Program Counter and the
Instruction Pointer, and the Flags' register to be
written into the Flag register.
If it is a 0,
then IRET causes a normal interrupt return.
A
hardware reset clears this bit to O.

R221 (~O) IMR
INTERRUPT MASK

I

LEVEL6~

LEVEL7gjjJ

~.
I
L

The format of the Flags register is shown in
Figure 5-1, Chapter 5.

LLEVELO
LEVEL 1

LEVEL 5

LEVEL 2

LEVEL 4

LEVEL 3

Figure 6-7. Interrupt Mask Register

6.4.4 Interrupt Priority Register

6.5 INTERRlJ>TS

At«)

THE DNA CHANNEl

When the DMA channel is enabled to work with a
handshake-driven I/O port or the UART, the interrupt request from the specific device. is replaced
by sn interrupt request from the DMA channel when
the specified number of transfers has been completed (see Figure 6-8).

The Interrupt Priority (IPR) register (R255, Bank
0) defines the priority order of the interrupt
levels. The coding of this register is defined in
Figure 6-2.
Interrupts should be globally disabled before writing to this register.

OMA
ENABLE

-I==;:=t:~[)-----

DMA
REQUEST

TO IRQ
REGISTER
END

OFCO~~~

-

----1...../

....

Figure 6-8. Interrupts and the DMA

592

Chapter 7

Reset and Clock
7.1

RESET

A system reset, activated by a low level on the
input, overrides all other operating conditiona and puta the SuperB into a known atate. The
~ input ia internally synchronized with the
internal clock of the SuperB to form the internal
reset line. For a power-up reset operation when
using the on-chip oscillator, the ~ input must
be held low for at least 50 milliseconds after the
power supply is within tolerance to allow the onchip clock oscillator to stabilize. If an external clock oscillator is used or power has been
applied long enough for the on-chip oscillator to
stabilize, then the ~ input must be held low
for at least 1B c lock periods to cause a systsm
~

Resets also result in the following:
•

Interrupts are disabled (the Global Interrupt
Enable bit is cleared and the Interrupt Request
regiater ia disabled)

•

Ports 2, 3, and 4 are placed in input mode

•

In parts with on-chip ROM, Ports 0 and 1 are
placed in input mode; in ROM leas parts, Port 1
is configured as an address/dsta bus to external memory while Port 0 bits 0-4 are configured
as address bits B-12 and bits 5-7 are in input
mode

•

The on-chip peripherals are all disabled

•

The Program Counter is loaded with 0020 H

reset.

Whils ~ is active low, the 1m' output is forced
low while ~ pulses low once every fou~ clock
cycles and R/W remains high.
Z-BUS-compatible
peripherals use the ~ and Im'coincident low state
as a periphersl reset function.

Table. 7-1 shows the reset values of the control
and peripheral registers. Specific reset values
are shown by 1s or Os, while an x indicates bits
whose ststes sre not defined and t ind:rcates not
used.

593

Reset and Clock
Table 7-1.
Register

"'-ie.

Control and Peripheral Register Reset Yall88

rae

DaciRl. Hall

General Registers
Program Control Flags
FLAlOS. R213, D5

x x x x x x 0 0

Bank 0, no faat interrupta

1 00, 0 0 0 0

Working register CO

Ragiater Pointer
RP1, R215, D7

1 100 1 000

Working register CB

Stack Pointer
SP, R216-7, DB-D9

x x x x x x x x

Inatruction Pointer
IP, R21B-9. DA,DB

x x x x x x x x

Interrupt Request
IRQ, R220,DC

o '0 0

Interrupt Mask
IMR, R221, DO

x x x x x x x x

Syatem Mode
SYM. R222, DE

Ott x x x 0 0

Disable interrupta
disable'3-state

External Memory Timing
EMT. R254, 'FE
(Bank 0)

01111100

3 wait states for Program
and Data, Slow memory ,

Interrupt Priority
IPR,' R255, FF
(Bank 0)

x x x x x x x x

Ragister Pointer 0
RPO, R214, D6

0 0 0 D 0

Interrupts disablsd

Port Register.

Port 0
PO, R20B, DO

x x x x x x x x

Port 1
P1, R209, D1

x x x x x x x x

Key

594

1 = Reset value of 1
0= Reset value 'of 0

x = bite whose states are not defined
t = not used

Reset snd Clock
Table 7-1.

Control and Peripheral Register Reset Values (Continued)

Register
Port Registers (Continued)

output register = 1
Value will not be
observable until ports
are configured as output

Port 2
P2, R210, D2

Port 3
P3, R211, 03

1 1 1

output register = 1
Value will not be
observable until ports
are configured as output

Port 4
P4, R212, 04

xxxxxxxx

Handshake 0 Control
HOC, R244, F4

xxxxxOxO

Disable handshake
Ports 1 and 4, disable CHA,
(write only)

Handshake 1 Control
H1C, R245, F5'

x x x x x x x 0

Dieable handshake
Port 0 (write only)

Port 4 Direction
P4D, R246, F6

1 1

Inputs

Port 4 Open-Drain
P40D, R247, n.

o 0 0 0 0 0 0 0

1

1

Port 2/3 Mode
00000000
P2AM, R248-251, F8,F9,FA,FB
(Bank 0)

Push-pull

Inputs (write only)
(P2AM, P2BM, P2CM, P2DM)

Port 2/3 Interrupt
Pending
P2AIP, R252-3, FC,FD

0 0 0 0 0 0 0 0

(Write only) software
reset (P2AIP, P2BIP)

Port 0 Mode
POM, R240, FO
(Bank 0)

0 0 0 0 0 0 0 0
0 0 0 1
1 1 1

With ROM: input/output
ROMless: 1 = Address

Port Mode.
PM, R241, F1
(Bank 0)

t

t

t

t

With ROM: Port 0/1 inPlits
(writa only)
ROMless: Port 0/1 outputs

Kay:

= Reset value of 1
o = Reset value 0 f 0

0

0 0 0
0

0 0 0

x = bits whose states are not defined
t = not used

595

Reset and Clock
Teble 7-1.

Control IPI Peripheral Regieter Reset Vallm8 (Continued)

UIIRT IPI OM Regiatera

UART Transmit Control
UTC, R235, EB

o

0 0·0 0 0 1 0

Diaable tranamitter,
transmit buffer empty,

UART Receive Control
URC, R236, EC

o

0 0 0'0 0 0 0

Disable raceiver
No character received

UART Interru~t Enable
UIE, R237, ED

000 0 0 0

UART Dsta
UIO, R239, EF

X

0

0

Diaable interrupts

x. x x x x x x

UART Baud-Rate Generator x x x x x x x x
UBG, R24B-9, FB,F9
(Bank 1)
UART Mode A
UMA, R250, FA
(Bank 1)

xxxxxxxx

UART Mode B
UMB, R251, FB
(Ban~ 1)

o 0 0 0 0 0 0 0

Wake-Up Hetch
WUHCH, R254, FE
(Bank 1)

x x x x x x x x

Wake-Up Maak
WUHSK, R255,. FF
(Bank 1)

x x x x x x x x

DHA Count
DC, R240-1, FO,F1
(Bank 1)

x x x x x x x x

Disable baud-rate generator

Co....ter Regietera

Counter 0 Control
COCT, R224, EO
(Bank 0)

Key:

596

x x 0 0 0 0 0 0

1 = Reset value of 1
0'= Raset value of 0

Disable counter 0,
interrupte, software
capture

x = bits whose statee are not defined
t = not used

Reset and Clock
Table'7-1. Control and Peripheral Register Reset 'Values (Continued)
Register

c-nta

Counter Registera

(Continued)

Counter 1 Control
C1CT, R225, E1
(Bank 0)

x X 0 0 0 0 0 0

Counter 0 Capture
COC, R226-7, E2,E3
(Bank 0)

X

Counter 1 Cspture
C1C, R22B-9, E4,E5
(Bank 0)

x x x x x x x x

Counter 0 Mode
COM, R224, EO
(Bank 1)

o

Counter 1 Mode
C1M, R225, E1
(sank 1)

0, 0 0

X

X

X

X

X

X

Dissble counter 1,
interrupts, software
cspture

X

x x x x

Port 2 1/0

0 x x x x

Port 3 1/0

0 0 0

Counter 0 Time Constant x x x 'x x x x x
COTC, R226-7, E2,E3
(Bank 1)
Counter 1 Time Constant x x x x x x x x
C1TC, R22B-9, E4,E5
(Bank 1)

Key:

1,

o

Resat value of 1
Reset value of 0

x = bits whose states are not defined
t
not used

597

Reset and Clock
Eight clock cycles after ~ has returned high,
the SuperB starts program execution. The initial
instruction fetch ie from locetion 0020H• The
first program segment executed is typically a

I •I I 3I I I I
2

5

4

6

7

routine to initialize the control regietere to the
required system configuration. Figures 7-1 and 7-2
show the reset timing.

~T1-+-T2-+-T3~'

XTAL1

RESET~

i

i

I

I
I

V

AS

I
I
I

~DDRESS

I
I
I
I

I

1/

\

0020

1

if

DS

i
I

i

... ~T8-+-T9~

'l..n..rLrL.r1r

f/

I

\

I
I

I
I

\

;(F

DATA

V
OPe

Figure 7·1. Reset Timing for ROMless Devices

XTAL1

I,
I

AS

• ADDRESS

DS

!

i
I

)1

-------;--'

i

i

I
I

I

\..Y

V,------\

I
I
I
I
I
I
_ _ _ _ _ _ _.....1/'-_ _

1

• DATA
·Inlemal signals except for protopacks

Figure 7·2. Reset Timing for ROM and Protopack Devices

598

Reset and Clock

7.2 a.OCK
The SuperB derives its timing from on-board clock
circuitry connected to pins XTAL1 and XTAL2. The
clock circuitry consists of an oscillator, a
divide-by-two shaping circuit, and a clock
buffer.
Figure 7-3 illustrates the clock
circuitry.
The oscillator's inputs are XTAL1 and XTAL2, which
can be driven by a crystal, a ceramic resonator,
or an external clock source.
The divide-by-two
circuit can also be driven directly from a TTL
level on the XTAL1 pin.

XTAL1
INTERNAL
CLOCK

+2
XTAL2
BUFFER

Figure 7-3. Super8 Clock Circuit

Crystals and ceramic resonators would be connected
across XTAL1 and XTAL2 and should have the following characteristics to ensure proper osci lIator
operation:

Cut:
tt:lde:

output Frequency:
Resistance :
Capacitance:

AT (crystal only)
Parallel, fundamental
1 MHz-12 MHz
100 ohms maximum
30 pf maximum

When an external frequency source is used, onl y
the XT AL1 input' needs to be dr i ven •
Any TTLcompatible driver can be u!3ed for this function.
The XTAL2 input can be left floating.

ChapterS
110 Ports
8.1

8.3

INTRODUCTION

The SuperS has 40 line~ dedicated to input and
output.
These are grouped into five ports 0 f
eight lines each. All the lines can be configured
as inputs or outputs; some can be configured as
address/data lines.~All ports have TTL-compatible
input and output characteristics and can drive two
standard TTL loads.

8.2

GENERAL STROCTURE

In general, each bit of the five ports has an
associated input register, output register, and
buffer and control logic. When the CPU writes to
a port, it causes data to be stored in the output
register.
Those bits of that port configured as
outputs enable the output buffer, and the output
register contents are present on the external
pin. If those bits configured as outputs are read
by the CPU, the data present on the external pin
is returned. Under normal output loading, this is
the equivalent of reading the output register.
However, i f a bit of the port is configllred as an
open-drain output, the data returned may not be
the value contained in the output register; rather
it is the value forced on the input pins by the
external system.
When a bit .of any port is defined as
reading that bit causes data present on
nal pin to be returned.
Ports that
handshake control are an exception.
handshake-driven input bit returns the
latched into the input register by
strobe.

an input,
the exterare under
Reading a
data last
the input-

Bits configured as inputs can be written to by the
CPU, but in this case, the data is stored in the
output register and cannot be read back because
the output buffer is disabled.
However, if the
input bits are reconfigured as output bits, the
data stored in the output register is then
reflected on the output pins.
This mechanism
allows· the user to initialize outputs prior to
driving their loads.

600

PORT 0

Port 0 (R20S) can be configured as I/O or as an
address output port for addressing external memory
on a bit basis. Those bits selected as I/O can be
configured as all inputs or all outputs.
When
configured as ·outputs, the option exists to select
open-drain outputs.
The open-drain option does
not appl y to those bits configured as address
lines.
Accesses to Port 0 are made by reading and writing
to register R20S (DOH in set one). When a Port
o bit is configured as an address output, it
cannot be accessed as a register (writes have no
effect, reads return the state of the external
pin).
When used as an I/O port, Port 0 may be
placed under handshake control by using the facilities of Handshake Channel 1 (see section S.S).
The following control registers are associated
with configuring Port 0:
•

Port Mode register (RZll1, Bank 0). Controls
direction of I/O lines and selection of opendrain or push-pull outputs.

•

Port 0 Mode register (R21lO, Bank 0).
ures each bit as I/O or address bit.

•

Handshake 1 Control register (R2115, Bank 0).
Controls enabling and configuration of handshake signals.

Config-

8.11 PURr 1
Port 1 (R209) can be configured as an address/data
port for interfacing exterr\al memory or as a byte
I/O port. The configuration is set using the Port
Mode register (R241, Bank 0). (ror a description
of Port 1 as part of the external memory interface, see section 12.3.)
When configured as a
byte output port, there is an option to se lect
open-drain outputs on the entire port.
In the
ROMless parts, Port 1 is always an address/data
bus and cannot be programmably configured.

I/O Ports
When configured as an input or output port,
accesses are made to Port 1 via reads or writes to
register R209 (01 H in set one). When Port 1 is
configured as a multiplexed address/data port, it
cannot be accessed as a register; writes have no
effect and reads return an FF H' When used as an
I/O port, Port 1 can be placed under handshake
control by using the facilities of Handshake
Channel 0 (see section B.B).

•

Port 2/J A Mode register (R2118. B...k 0).
Controls the configuration of bits 0 and 1
(input, input with interrupt enabled, push-pull
input, open-drain output).

•

Port 2/3 B Mode register (R2119. B...k
Controls configuration of bits 2 and 3.

0).

The following control registers are associated
with configuring Port 1:

•

Port 2/3 C Mode register (R250. B...k
Controls configuration of bits 4 and 5.

0).

•

Port 2/3 D Mode register (R251. B...k
Controls configuration of bits 6 and 7.

0).

•

•

Port Mode register (R2111. Bank 0). Controls
Port 1 configuration (input port, output port,
or address/data bus) and selection of opendrain or push-pull outputs.
0 Control register (R2I111. B...k 0).
Controls the enabling and configuration of the
handshake signals.

Handshake

8.5

PORTS 2 AND ,

Ports 2 and 3 (R210 and,R211) are used to provide
the external control inputs and output.s for the
UART, the handshake channels, and the counter/
timers.
The relationship between port pins' and
their control function is shown in Table B-1.
When Port 2 and 3 bits are not used for control
inputs and outputs, they are available for use as
general-purpose I/O lines and/or external interrupt inputs. Each bit is individually configured
as to its function.
When Ports 2 and 3 are used as general-purpose I/O
lines, the direction of each bit can be configured
individually. Each bit selected as an output can
also be configured individually as an open-drain
or push-pull output. All inputs of Ports 2 and 3
are Schmidt-triggered.
Table 8-1.

2
3
4
5
6
7

~

The various control functions are enabled in the
control register for the associated device (Handshake Control register, Counter Mode register,
etc.) • When using Port 2 and 3 pins as control
signals, the Port 2/3 Mode registers must still be
programmed to specify which bits are inputs and
which bits are outputs.
Each bit of Ports 2 and 3 can be used as an external interrupt input. Each bit used as an external
interrupt input must be configured as an input,
but may still be used as an external control input
or as a general-purpose input" line. Each external
interrupt bit has an edge-triggered "interrupt~
pending" flip-flop that captures the external
int.errupt requests. Software can read and reset
the edge-triggered flip-flops without affecting
the normal I/O operation of the bit. Each external
interrupt has its own interrupt enable control
that determines if that bit is allowed to cause an
interrupt.
The edge-triggered flip-flops still
capture edges when the interrupt enable 'control is
disabled. Port 2 is accessed as general register
R210, Port 3 as general register R211.

Ports 2 and J Control Functions

-Port2Bit
Function
0

The following control registers are associated
with configuring Ports 2 and 3:

UART Receive Clock
UART Transmit Clock
Reserved
Reserved
Handshake o InpLlt
Handshake 0 Output
Counter 0 Input
Counte r 0 I/O

Bit
0
1
2
3
4

5
6
7

Port 3 Function
UART Receive Data
UART Transmit Data
Reserved
Reserved
Handshake 1 Inputll'lliIT
Handshake 1 Outputlmi
Counter 1 Input
Counter 1 110

601

I/O Ports
Two pegisters are direcUy al!lsociated with the
interrupt flip-flops:
•

•

Port 2/3 A Interrupt: Pending register (R252,
a...k 0). Controls interrupt flip-flops for
bits 0, 1, 2 and 3 of Ports 2 and 3.
Port 2/J 0 Interrupt: Pending register (R25J,
a...k 0).
Controls interrupt' flip-flops for
bits 4, 5, 6, and 7 of Ports 2 and 3.

These registers can be used, to poll the external
interrupts and to reset the interrupt pending bits
(the flip-flops). Reading these reQisters returns
the state ,of the interrupt pending flip-flop.
When writing to these registers, writing a 1 to a
bit position clears that flip~flop and writing a 0
to a bit position has no effect.
The Interrupt Mask register (R221) and Port 2/3
Mode registers' determine . which interrupts are
enabled.

, 0.7 PORT IDlE

AfI)

alUROl. REGISTERS

The port/l are configured and c,ontrolled by the
following set' of registers:
•
•
•
•
•
•
.,
•
•
•

Port Mode
Port 0 Mode
Port 2/3 A Mode,
Port 2/3 B Mode
Port 2/3 C Mode
Port,2/3 0 Mode
Port 2/3 A Interrupt Pending
Port 2/} B Interrupt Pending
Port 4 Direction
Port 4 Open-Drain

0.7.1 'Port Mode Register
The Port Mode register provides some additional
mode control for Ports 0 and 1.
The fields in
this register are (figure 8-1):
R241 BANK 0 (F1) PM
PORT MODE (WRITE ONLY)

PORT 0\

0.6

Port 4 (R212) is always an I/O port whose direction csn be configured on a bit-by-bit basis.
Each bit configured as an output can be configured
individually as an oP,Bn-drain or push-pull output.
Port 4 I/O lines are accessed via reads and writes
to regiater R212 (O~ in set one).

-

N!lTUSED~

PORT 1 MODE
00 OUTPUT
01 INPUT
1X ADDRESS/DATA

~

llli.

PORTO DIRECTION
0= OU1PUT
1 = INPUT
OPEN·DRAIN PORT 0
PUSH·PULL
1 = OPEN·DRAIN
OPEN DRAIN PORT 1
o = PUSH-PULL
1 = OPEN·DRAIN
ENABLE DM P3,
0= DISABLE
1 = ENABLE

o=

Port 4 can be placed under handshake control by
using the facilities of Handshake Chann!!l 0 (see
section 8.8).

Figure 8·1. Port Mode Register

The following control registers are associated
with configuring POft 4:

Port 0 Directioo (Do). If this bit iB a 1, all
bits of Port 0 configured as I/O will be inputs.
If this bit is a 0, then the I/o lines will be
outputs. A hardwsre reset forces this bit to a 1.

•

Port 0\ Directioo register (R20\6, Oink 0).
Controls direction of each bit of Port 4.

•

Port 0\ Open-Drain register (R20\7, a...k 0).
'Selects open-drain or push-pull for each Port 4
output.

•

Handahalce 0 Control register (R2. ., Oink 0).
Controls the enabling and configuration of the
handshake signals.

602

Open-Drain Port 0 (D1). If this bit is a 1, all
bits of Port 0 configured as outputs will be
open-drain outputs; if 0, they will be push-pull
outputs. This bit has no effect on those bits not
configured as outputs. A hardware reset forces
this bit to a o.
Open-Drain Port 1, (Dt). If Port 1 is configured
as an output port and thia bit is s'1, then all of
the port'will be open-drain outputs. If this bit
is a 0, they will be pueh-pull outputs. This bit
hss no effect i f Port 1 is not _configured as an
output port or A/O O- 7 • A hardware reaet forces
this bit to Ii O.

1/0 Ports
Enable 1R (0,). If this bit is a 1, Port 35 is
configured as Oata Memory output line (1m).
A
hardware reset forces this bit to· a O.
Port 1 Mode (04-05)'
This field selects the
configuration of Port 1 as an output port, input
port, or address/data port as part of the externsl
memory interface. The coding for this field is as
follows:
Field

Output port
Input port
Address/data

Ftn:tioo

Input
Input and interrupt enabled
Output, push-pull drivera
Output, open-drain

A hardware reset forces all
registers to the 0 state.

A hardware reset forces this field to the 01
(input port) state. The ROMless part has this
field forced to 1X.

8.7.2

Field
00
01
10
11

Flnctioo

00
01
1X

of Ports 2 and 3 configures the bit as input or
output. The field a1ao controls whether the bit
is enabled as an external interrupt source and
selects the output as open-drain or push-pull.
The field is coded as follows:

bits of the four

R248 BANK 0 (F8) P2AM
PORT 2/3 A MODE (WRITE ONLY)

Port 0 Mode Register

The Port 0 Mode register programs each bit of Port
an address output (part of an external memory
interface) or as an I/O bit (figure B-2). When a
bit of this register is a 1, the correaponding bit
of Port 0 is defined as an address output. When a
0, the corresponding bit of Port 0 is defined as
an I/O bit. For ROM less parts, 'I hardware reset
forces this register to all 1s for pins POO-P04
and Os for pins P05-P07; for parts with on-chip
ROM, a hardware reset forces all pins to O.

o as

00
01
10
11

INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH-PULL
OUTPUT, OPEN-DRAIN

Figure 8-3. Port 2/3 A Mode Register
R249 BANK 0 (F9) P2BM
PORT 2/3 B MODE (WRITE ONLY)

R240 BANK 0 (FO) POM
PORT 0 MODE

1~1~1~1~1~1~1~1~1

:::~ I I I [g:::
POSMODE~ ~P02MODE

00 INPUT
01 INPUT, INTERRUPT ENABLED
10 OUTPUT, PUSH·PULL
11 OUTPUT, OPEN-DRAIN

Figure 8-4. Port 2/3 B Mode Register

poi MODE

P04 MODE

o =1/0; 1

= ADDRESS

R250 BANK 0 (FA) P2CM

PORT 2/3 C MODE (WRITE ONLY)

Figure 8-2. Port 0 Mode Register

8.7.' Port 2/3 Mode Registers
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C
Mode, and Port 2/3 D Mode registers control the
modes of Ports 2 and 3 (Figures B-3, B-4, B-5, and
8-6). A separate 2-bit field for each of the bits

00
01
10
11

INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH-PULL
OUTPUT, OPEN·DRAIN

Figure 8-5. Port 2/3 C Mode Register

603

1/0 Ports

8.7.5 Port 4 Direction Register

R251 BANK 0 (FB) P20M
PORT 2/3 0 MO.DE (WRITE ONLY)

00
01
10
11

The Port 4 Direction register defines the I/O
direction of Port 4 on a bit basis (Figure 8-9).
If s bit in this register is s 1, the corresponding bit of Port 4 is configured as an input line.
If the bit is a 0, the corresponding bit of Port 4
is configured as an output line. A hardware reset
forces this register to the all 1s state.

INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH.PULL
OUTPUT, OPEN·ORAIN

Figure 8-6, Port 2/3 0 Mode Register

8.7.4 Port 2/3 Interrupt Pending Registers
The. Port 2/3 A Interrupt Pending and Port 2/3 B
Interrupt Pending registers represent the software
interface to the negative edge-triggered flip-flops associated
with extemal interrupt inputs. Each bit of these registers
corresponds to an interrupt generated by an extemal source.
When one of these registers is read, the value of each bit
represents the state of the corresponding interrupt. When
one of these registers is written tO,a 1 in a bit position causes
the corresponding edge-triggered flip-flop to be reset to 0; a
o causes no action.

The software interfaces with these registers to
poll the interrupts and also to reset pending
interrupts as they are processed. The relationship between theae registers and the corresponding
externally generated interrupts is shown in
Figures 8-7 and 8-8. A hardware reset forces all
interrupt edge-triggered flip-flops to the 0
state.

R246 SANK 0 (FB) P40
PORT 4 DIRECTION

1~1~1~1~1~1~1~1~1

L.I_____

P40·P47 1/0 DIRECTION
o OUTPUT; 1 INPUT

=

=

Figure 8-9. Port 4 Direction Register

8.7.6 Port 4 Open-Drain Register
The Port 4 Open-Drain register defines the output
driver type for Port 4 (Figure 8-10). If a bit of
Port 4 has been configured as an output and the
corresponding bit in the Port 4 Open-Drain
register is a 1, then the Port 4 bit will have an
open-drain output driver; i f it is a 0, then the
Port 4 bit will have a push-pull output driver.
If the bit of Port 4 has been configured as an
input, then the corresponding bit in the Port 4
Open-Drain register has no effect. A hardware
reset forces this register to the alIOs state.
R247 SANK 0 (F7) P400
PORT 4 OPEN·DRAIN

I~I~I~I~I~I~I~I~I

L.1-----~"::ti~~~;~L~;Rt~

R252 BANK 0 (Fe) P2AJP
PORT 213 A INTERRUPT PENDING

OPEN.DRAIN

Figure 8-10. Port 4 Open-Drain Register

8.8 HAN>5ltAKING CtWNl.S

Figure 8-7. Port 2/3 A Interrupt Pending Register
R253 BANK 0 (FO) P2 BIP
PORT 2/3 B INTERRUPT PENDING

P3J~
I. ~IL24
P3.~' ~P25
P27'

P34

P26

P3s

Figure 8-8. Port 2/3 B Interrupt Pending Register

604

The Super8 has two handshaking channels. Channel
"0" is associated with Ports 1 or 4; Channel "1"
is associated with Port O. They are identical in
function except Channel 0 also has DMA capability.
There are two basic modes of operation. The first
is the "fully interlocked" or two-wire mode. In
this mode, there is an incoming control wire and
an outgoing control wire.
Each transition on H
control wire must be ans.wered by a transition Oil
the other control wire before the first can make
another transition.
Thus both the sender and
receiver control the data transmission rate.
Figures 8-11 and 8-12 illustrate the operation of
the "fully interlocked handshake."

I/O Ports
DAV
('NPUT TO SUPERB)

(OUTPUT FROM

SUP~~~---+-",

DATA ON PORT
(INPUT TO SUPERB)

State 1. Ready output IS high Indicating that the SuperB is ready to accept data
State 2. The I/O device puts data on the port and then activates the DAV input This causes the
data to be latched into the port Input register and generates an Interrupt or DMA request

State 3. The SuperB forces the Ready (ROY) output low, Signaling to the 1/0 device that the data
has been latched

State 4. The 110 device returns the DAV line high In response to ROY gOing low.

State 5. The SuperB DMA or Interrupt software must respond to the service request and read the contents althe port In order for the handshake sequence to be completed. The ROY line goes high
if, and only if, the port has been read and DAV is high. This returns the interface to its Initial state

Figure 8-11. Super81nput Handshake-Fully Interlocked Mode

ROY
(INPUT TO SUPERB)

DAV
(OUTPUT FROM SUPERB)
SET-UP
oATAONPOAT

VALID DATA

(OUTPUT FROM SUPERB)

State 1. ROY Input is high Indicating that the 1/0 device IS ready to accept data
State 2. The SuperB writes to the port register to initiate a data transfer. Writing the port outputs
new data and forces OAV low If, and only II, ROY IS high and set-up time IS done
State 3. The 1/0 device forces ROY low after latching the data. ROY low causes an interrupt or OMA
request to be generated. The SuperB can write new data In response to ROY going low.
State 4. The OAV output Irom the SuperB IS driven high In response to ROY gOing low.
State 5. After OAV goes high, the I/O device IS free to raise ROY high thus returning the Interface
to Its Initial state

Figure 8-12. Super8 Output Handshake-Fully Interlocked Mode

The second mode is the "strobed" or single-wire
mode. In this mode there is a single control wire
and i t is generated by the sender. Figures 8-13
and 8-14 illustrate· the operation of "strobed"
handshaking.

I

DAV

('NPUT TO SUPERB)

(INPUT TO SUPER8)

I

1\---STROBE_,

SET·UP
DATA ON PORT

Each channel has a 4-bit counter, called the
Deskew Counter, that is used to count processor
clocks.
In the "strobed" mode, this counter is
used to generate the set-up time and strobe width
for the output handshake. In the "full y inter-

"-1-1 1--- HOLD - I

--V
--..I\:
I

VALID DATA

V
.f!\,,_____
I

Figure 8-13. Super81nput Handshake-Strobed Mode

605

I/O Ports

DAV
(OUTPUTFROMSUPER8)

r-~STROBE
------,/U-------,

I-f-SET.UP

--v-

DATA ON PORT
(OUTPUT FROM SUPER8) - - - - ' \_ _ _ _ _ _~_A_L_ID_D_A~_'A_ _ _ _ __
THE SET·UP AND STROBE MINIMUM TIMES ARE DETERMINED
BY THE VAWE IN THE DESKEW COUNTER.

Figure 8-14. Super8 Output Handsha.ke-Strobed Mode

locked" mode, the counter generates the set-up
time.
This set-up time is the delay between
outputting valid data at the port and activating
the Data Available handahake signal. The Deskew
Counter can be loaded with a value from 1 to 16
that represents the minimum number of CPU clock
cycles in the data set-up and strobe times.
The direction of data trsnsfer during handshake is
determined by the selected direction of bit 0 of
the parallel port associated with the handshake
channel.
This also controls the DMA direction
when used.

8.8.1

!leeded by the handshake function. Note that the
open-drain options of Ports 2 and 3 can be applied
to the handshake outputs. Note also that Port 2
and 3 pins used by the handshake channels as
inputs can still be used as external interrupt
pins to drive the handshake service routines.
Handshake Input.
This input provides the l5lW
signal for input handshaking or the RDY signal for
output handshaking.
Handshake output. This output providlls the RDY
signal for input handshaking or the l5lW signal for
output handshaking.

Pin Descriptions
8.8.2

The handshake channels each use two pins of Ports
2 and 3 (bits 4 and 5) for interfacing with the
external world:
Handshake Channel 0 Input
Handshake Channel 0 Output

P24
P25

Handshake Channel 1 Input
Handshake Channel 1 Output

P34·
P3 5

Handshake Control Registers

Each handshake channel is controlled by an B-bit
control register (Figures B-15 and B-16).
Handshake 0 Control register (R244) and Handshake 1
Control register (R245) include the controls for
enabling handshakes, selecting the associated port
(Channel 0 only), selecting the handshake type,
enabling OMA capability (Channel 0 only), and
initializing the Deskew Counter.
The fields in
these registers are:

The individual Port 2 and 3 pins should be configured for the appropriate I/O direction as
R244 SANK 0 (F4) HOC
HANOSHAKE 0 CONTROL (WRITE ONLY)

I~I~I~I~I~I~I~I~I
DESKEW COUNTER
(RANGE 1-16)

~

I

~
L

L

1

= HANDSHAKE ENABLE

PORT SELECT:
1 = PORT1;O = PORT 4
DMAENABLE:

1

= ENABLED

0= DISABLED
MODE:
1 = FULLY INTERLOCKED
0= STROBED

Figure 8-15. Handshake.O Control Register

606

I/O Ports
R245 BANKO (F5) H1C
HANDSHAKE 1 CONTROL (WRITE ONLY)

I~I~I~I~I~I~I~I~I
DESKEW COUNTER
(RANGE 1·16)

~

II

L,""_",",~~
NOJUSED
MODE:

=

1 FULLY INTERLOCKED
0= STROBED

Figure 8-16. Handshake 1 Control Register

Handshake Enable (Do). When this bit is set to 1,
the handshake function is enabled.
Port Select (Channel 0 only)(01) _ This bit
selects which port is controlled by Handshake
Channel O.
When it is set to 1, Port 1. is
se lected and when it is cleared to 0, Port 4 is
selected.
~

Enable (Channel 0 only)(Dz). When this bit is
set to 1, the OMA function is enabled for Handshake Channel O. When it is cleared to 0, the DMA
function is not used by the handshake channel and
may be used by the UART.

Mode (OJ).

When this bit is set to 1, the "fully
inter locked" mode is enabled. When it is cleared
to 0, the "strobed" mode is enabled.

Deskew Counter (04-DJ).

This 4-bit field is used
to select a count value from 1 to 16 (0000-1111).
This value is the number of processor clocks used
to generate the set-up and strobe when using the
"strobed" mode, or the set-up when using the
"fully-interlocked" mode.

607

Chapter 9
Counter/Timers
9.1

INTRmOCTION

The SuperB has two identical 16-bit counter/timers
that can be programmed independently: They can be
cascaded to produce a counter }2 bits in length
and can operate from internal inputs (as timers)
or external inputs (counters).
When used as
timers, the internal input is the internal CPU
clock divided by two, which is the XTAL divided by
four. Figure 9-1 shows the counter/timer block
diagram.

The counter/timers can count up or down.
The
dire~tion can be controlled on, the fly by either
software or an external event.
The counter/timers have the option of single cycle
or continuous counting capability. In the single
cycle mode, the counters count to zero ( up or
down) from the preset time-constant value and then
stop.
In the continuous mode, counting is
continuous and each time the counter reaches zero,
it is reloaded with the preset time-constant value
from the Time Constant register (or the Capture
register in bi-value mode).

o

A
T
A

B
U

S

CPU

CLOCK

Figure 9-1. Counter/Timer Block Diagram

608

Counter/Timers
9.1.1

Bi-Yalue Mode

The external event can be either the r ising edge
of the counter/timer I/O line (P27 for C/TO, P37
for C/T1) or both edges. On the rising edge, the
current count value is loaded into the Capture
register. If capture on both edges is enabled, the
current count value is loaded into the Time
Constant register on the falling edge, overwriting
the initial load value for that counter.

Another option allows either a single or dual
(bi-value) preset time constant value.
In
bi-value mode, both the Time Constant register and
Capture register are used to supply load values to
the counter/ timer. The two registers alternate
in loading the counter/timer each time the
counter/timer makes a transition between a count
of 0 and a count of FFFF H when counting down, or
between a count of FFFfH and 0 when counting up
(assuming continuous mode operation), or when a
trigger causes the counter/timer to be reloaded.
This can be used to produce an output pulse train
with a variable duty cycle. The bi-value feature
is not available when the capture feature is
e~abled
and vice versa.
Upon enabling a
counter/timer in bi-value mode from a previously
disabled condition, the initial load of the
counter/timer is'from the Time Constant register.
9.1.2

The capture feature is not available when the
bi-value counting feature is being used and, vice
versa.
If interrupts are enabled, the interrupt request
ia generated on the transition from a count of 0
to a count of ffFF H or from a count of fffF H
to a count of 0, and/or on an external event. If
configured for an external output, the output pin
toggles at this aame count change.

9.1.3

Capture

External Gate and Trigger

The counter/timers have an external gate capability. When this feature is selected, an external
input line (GATE) is monitored. The counting or
timing operation ia performed only when this line
is low.
The gate facility is illustrated in
Figure 9-2.

Another feature, called "capture on external
event," takes a snapshot of the counter when a
specific event occurs. The external event can be
simulated by software.
When "captured," the
current value in the counter is loaded into a
special
register that can
subsequently
be
read via software. The capture feature is needed
to look at counters on the fly, especially
cascaded counters.

I l...__....

GATE INPUT

a....-;._____

COUNTER OR
TIMER INPUT

Figure 9-2. Gate Facility

TRIGGER INPUT

n

COUNTER OR
TIMER INPUT

,----,

.._ _ _ _.....
'

r1
L---

..
' _.,.........1

A COUNT OCCURS HERE,

Figure 9-3. Trigger Operation
GATE/TRIGGER
INPUT
COUNTER OR TIMER INPUT

Figure 9-4. GatelTrigger Function

609

Counter/Timers
An ex ternal input can be used as a tr igger input
to a counter/timer. When this feature is selected,
an external line ia monitored. A software trigger
is alsa present in a control register.
The
trigger input to the Counter/Timer is an OR of the
software and hardware triggers. Prior to a lowto-high transition on the trigger, the Counter is
disabled. After the low-to-high transition on the
trigger, counting is enabled. Retriggerable or
non-retriggerable'mode can be selected.
Clearing the Counter Enable bit in the Control
register also resets the triggered condition; a
new trigger must be received after the Counter
Enable bit is set again before counting will
resume.
The trigger operation is illustrated in
Figure 9-3.
One input line (GATE/TRIGGER) can be used for both
the gating and the triggering functions.
An
initial low·to-high transition on this line acts
as a trigger and subsequent low signals on this
line function as gate signals (Figure 9-4).

The Mode and Control registers determine the
counter/timer operations.
The Mode register
selects the configuration of the counter/timers
and is generally loaded only at initialization
time, while the Control register handles those
features that are likel y to be dynamicall y
changed.
The Time ,Constant register contains the initialization value for the counter/timer and also holds
the counter value saved on the falling edge of
P27/P3,7 when capture on both edges is enabled.
The Capture register holds the counter value saved
when using the "capture on external event" function. When capture on both edges is enabled, it
holds the value saved on the rising edge of
P27 /P37' It also holds a second initialization
value when using the bi-value counting feature.

9.2.1 Counter/Timer Control Registers
The fields in these registers, as shown in Figures
9-5 and 9-6, are:

9.2 COUNTER/TIMER CONTROL AND

MOO[

REGISTERS

Each counter/timer has an 8-bit Mode register, an
8-bit Control register, a 16-bit Time Constant
register, and a 16-bit Capture register.
R224, BANK 0 (EO) COCT
COUNTER 0 CONTROL

SINGLECYCLE~~

o1== CONTINUOUS ~
o = COUNT DOWN
1

1 = COUNT UP
=LOAD COUNTER

I

~
L

L"

= ENABLE COUNTER

READ 1

= END OF COUNT

WRITE 1 == RESET END OF COUNT
1 = ZEROCOUNTINTERRUPT ENABLE

1

=SOFTWARE CAPTURE

1 = SOFTWARE TRIGGER

Figure 9-5. Counter 0 Control Register
R225 BANK 0 {E1)C1CT

COUNTER 1 CONTROL

SINGLECYCLE~~

o1== CONTINUOUS
o = COUNT DOWN
1

1
1

=COUNT UP

= LOAD COUNTER

I L

~
L

1= ENABLE COUNTER

READ 1 = END OF COUNT
WRITE 1 = RESET END OF COUNT

1 = ZERO COUNT INTERRUPT ENABLE
1 = SOFTWARE CAPTURE

=SOFTWARE TRIGGER
Figure 9-6, Counter 1 Control Register

61b

Counter/Timers
Enable Counter (Do). When this bit is set to 1,
the counter/timer is enabled; operation begins on
the rising edge of the first processor clock
period following the setting of this bit from a
previously cleared value.
Writing a 1 in this
field when the previous value was 1 has no effect
on the operation of the counter/timer. When this
bit is cleared to 0, the counter/timer performs no
operation during the next (and subsequent)
processor clock periods. A hardware reset forces
this bit to O. Both counters are clocked by the rising edge of
the incoming signal on P26 or P36 after the counter is
enabled. The maximum frequency of the extemal clock
signal applied to P36 (P26) equals the maximum Xtal frequency divided by 4. The maximum quaranteed Xtal frequency for the SuperS is 20 MHz, which implies a maximum
counter frequency of 5 MHz.

Reset/End of Count Stetus (01)' This bit is set
to 1 each time the counter reaches O. Writing a 1
to this bit resets it, while writing a 0 has no
effect.
Zero Count Interrupt Enable (Dz). When this bit
is set to 1, the counter/timer generates an interrupt request when it counts to O. A hardware reset
forces this bit to O.
Software Capture (0,). When this bit is set to 1,
the current counter value is loaded into the
capture register.
This bit is automatically
cleared following the capture.
Software Trigger (04)' This bit is effectively
"ORed" with the external using-edge trigger input
and can be used by the soft.ware to force a trigger
signal.
This bit produces a trigger signal
regardless of the setting of the Input Pin Assignment field of the Mode register. This bit is
automatically cleared following the trigger.
Load Counter (05)' The contents of the Time,
Constant register are transferred 'to the Counter
prescaler one clock period after t.his bit is set.

This operation alone does not start the Counter.
This bit is automatically cleared following the
load.
Count ~1bcnIn (06)'

This bit determines the count
direction if internal up/down control is specified
in the Mode register. A 1 indicates up, a 0 down.

Continuous/Single Cycle (D71. When this bit is set to 1
the counter is reloaded with the time-constant value when the
counter reaches the end of the terminal count. The terminal
count for down counting is 0000, while the one for up counting
is FFFF. When this bit is cleared to 0, no reloading occurs.

9.2.2

Counter/Ti~r

Mode Registers

The fields in these registers, as shown in Figure
9-7 and 9-8, are:
Capture Mode (0" Do). This 2-bit held selects
the capture or bi-value count mode. A value of 01
enables capture on the rising edge of the 1/0 pin,
a value of 11 enables capture on both edges of the
I/O pin, a value of 10 enaples the bi~value count
mode and disables capture, and a value of 00
disables both capture and bi-value load.
Progr'~Extemel IJp/OooIn Control (Dz) • A 1
enables programme'd up/down control and a 0 enables
external up/down control. If external up/down is
enabled, a 0 on P27/P37 indicates down and a 1
indicates up.

Enable Retrigger (0,). When this bit is set to 1,
the time-constant value is automatically loaded
into the Counter/Timer register when a trigger

R224 BANK 1 (EO) COM
COUNTER 0 MOOE

~

INPUT PIN ASSIGNMENTS:

07 06 05 04 P27

P26

~O~O~O~O~II~O~---'~II~O~-----

o 0 0 1 110
TRIGGER
0010GATE
1/0
o 0 1
GATE
TRIGGER
o 1 0
110
CO INPUT
o 1 0
TRIGGER
CO INPUT
o 1 1
GATE
CO INPUT
o 1 1
GATE!
TRIGGER
CO INPUT
CO OUTPUT I/O
CO OUTPUT TRIGGER
CO OUTPUT GATE
CO OUTPUT GATEITRIGGER
CO OUTPUT CO INPUT
- - , - UNDEFINED-- - UNDEFINED-- CASCADE COUNTERS -

-----1

I L !i:'lr;,!,,:: """
EOGE OF P2,

10 = BI·VAWE LOAD
11 = CAPTURE ON BOTH

EDGES OF P27
0= EXTERNAL
UP/DOWN CONTROL P27
1 = PROGRAMMEO
UP/DOWN CONTROL
1

=ENABLE RETRIGGER

Figure 9-7. Counter 0 Mode Register

611

Counter/Timers
R225 BANK 1 (E1) C1M
COUNTER 1 MODE

I~I~I~I~I~I~I~I~I
INPUT PIN ASSIGNMENTS,
P3,

o
o

0 0

0 110

1/0
TRIGGER
1/0

0 0 1 110

D010GATE
0011GATE

=::J

I L~:~~::~,~
EDGE OF P37

10 = BI-VAWE MODE
11 = CAPTURE ON BOTH
EDGES OF P3,

TRII1GER
o 1 0 0 I/O
C11NPUT
o 1 0 1 TRIGGER
C11NPUT
01l0GATE
C11NPUT
0111GATEI
TRIGGER
C1 INPUT
C10UTPUT 110
C1 OUTPUT TRIGGER
C1 OUTPUT· GATE
C1 OUTPUT GATE/TRIGGER
C10UTPUT C11NPUT
- - UNDEFINED-- - UNDEFINED-- - UNDEFINED--

0= EXTERNAL

UPIDOWN CONTROL P37

1

=PROGRAMMED

UPIDOWN CONTROL

1 = ENABLE RETRIGGER

"':igure 9·8. Counter 1 Mode Register

input is re'ceived while the counter/timer is
counting (Counter/Timer not equal to 0).
When
this bit is cleared to 0, no reloading occurs.
Input Pin Assigllllellts (04-1)7). This 4-bit field
specifies the functionality of the port lines
associated with the co·unter/timer. It also determines whether the counter/timer will monitor an
external input (counting operation) or use the
scaled internal processor clock (timing operation). The four bits in the field select the
following options: enable output (EO), external
signal or internal clock (C/T), enable gate facility (G), and enable triggering facility (T). The
Table 9-1.

EO

IPA Field
CIT C T

OJ

°6 °5 °4

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0
1

0
0
0
1

0
0

'1

0
0
0
0

0
0

0
0-

0
1
0
1
0
0

612

If 1111 is coded in this field in the Counter 0

Mode register, then the two counter/timers are
linked together as a 32-bit'counter with Counter 0
as the low-order 16 bits and Counter 1 as the
high-order 16 bits. Counter 1 selects the mode
and control options for the 32-bit counter and
external accesses are made through the lines
associated with Counter 1 (P36 and P37)'

IPAField Encoding in Counter MOde Registers

Pin Functionality -Counter/Tiaer I/O
Counter/Ti.er Input
(P27 or P37 )*'
(P26 or P36 )*
I/O
I/O
Gate
Gate
I/O
Trigger
Gate'
Gate/trigger
Output
Output
Output
Output
Output
Undefined
Undefined
Undefined

* Counter/timer 0 - P27 ~nd P26
Counter/timer

selected options determine the functions associated with each external line of the counter/
timer as illustrated in Table 9-1.
A hardware
reset forces these four pins to O.

- P3 7 and P3 6

I/O'
Trigger
I/O
Trigger
Input
Input
Input
Input
I/O
Trigger
Gate
Gate/trigger
Input
Undefined
Undefined
Undefined

Notea
Timer
Timer
Tinier
Timer
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
Counter
Reserved
Reserved
Reserved for Counter 1,
Cascade for Counter 0

Counter/Timers
The counter/timer I/O line (P27 for C/TO, P37 for
C/T1) is also used ss the external capture input
if the capture feature is enabled, and the up/down
control input (O=down, 1=up) if external up/down
control is enabled.

9.2.3

T~

ConatIm: Register

This 16-bit regiater psir holds the value that is
automatically loaded into the counter/timer 1)
when the counter/timer is enabled, 2) in continuous mode, when the count resches zero, or 3) in
re-trigger mode, when the trigger is ssserted. If
capture on both edges is enabled, then this register captures the contents of the counter on the
falling edge of the I/O pin.
The formst of the Time Constant register
illustrated in Figure 9-9.

is

9.2.4 capture Register

This 16-bit register pair is uaed to hold the
counter value saved when uaing the "capture on
external event" function.
This register will
capture at the rising edge of the I/O pin or when
software capture is asserted. When the bi-value
mode of operation is enabled, this register is
used as a second Time Constant register and the
counter is alternately loaded from each.
The format of the Capture Register is shown in
Figure 9-10.
R226 BANK 0 (E2) COCH
COUNTER 0 CAPTURE

I~I~I~I~I~I~I~I~I

..1-----

R226 BANK 1 (E2) COTCH
COUNTER 0 TIME CONSTANT

R227 BANK 0 (E3) COCl
COUNTER 0 CAPTURE

1~1~1~1~I~l~I~I~1

I~I~I~I~I~I~I~I~I

I

L _ _ _ _ _ HIGH SYTE (COTC,-COTC15)

R227 BANK 1 (E3) COTCl
COUNTER 0 TIME CONSTANT

1'------

HIGHBVTE(COC,-COC'5)

LOW BYTE (COCo-COC7)

R228 BANK 0 (E4) C1CH
COUNTER 1 CAPTURE

I~I~I~I~I~I~I~I~I

LI_____ lOW BVTE (COTCo-COTC7)
R228 BANK 1 (E4) C1TCH
COUNTER 1 TIME CONSTANT

R229 BANK 0 (ES) C1 Cl
COUNTER 1 CAPTURE

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

LI_____ HIGH SYTE (C1TC,-C1TC15)
R229 BANK 1 (ES) C1 TCl
COUNTER 1 TIME CONSTANT

LI_____ LOW BYTE (C1Co-C1C7)
Figure 9-10_ Capture Register Format

I~I~I~I~I~I~I~I~I

LI_~___ lOWSYTE(C1TCo-C1TC7)
Figure 9-9. Time Constant Register Format

613

Chapter 10

UART
10.1

INTRODUCTION

The universal asynchronous receiver/transmitter
(UART) is a full-duplex asynchronous channel.
Transmission and reception can be accomplished
independently with 5 to 8 data bits per character,
'plus optional even or odd parity, and an optional
wake-up bit.

The Transmit Data output (P31) line is held marking (high) when the transmitter has no data to
send. If the Send' Break (SE~BRK) bit of the UART
Transmit Control (UTC) register is set to 1, the
Data Output line will be held spacing (low) until
it is cleared.

10.3 RECEIVER
Data can be read into or out of the UART via
R239.
This single address is able to serve a
full-duplex channel because it contains two complete 8-bit registers--one for the transmitter and
the other for the receiver.

10.2 TRANSMITTER
When the UART' s register address is specified as
the destination (dst) of an operation, the data is
output on the UART. The UART automatically adds
the start bit, the progranvned parity bit (odd,
even, or no parity), and the programmed number of
atop bits to the data character to be transmitted. The transmitter can also add a Wake-Up
bit (optional) between the parity bit (or the last
bit in the character if parity is disabled) and
the first stop bit, as shown in Figure 10-1. When
the character is five, six, or seven bits long,
the unused bits in the Transmit Data register
(UIO) are automatically ignored by the UART.
Serial data is shifted from the transmitter at a
rate equal to 1, 1/16th, 1/32nd, or 1/64th of the
clock rate supplied to the transmitter clock input
(as determined by the clock-rate field in,the UMA
register). Serial data is shifted out on the
falling edge of the transmitter clock.

An asynchronous receive operation begins when the
Receive Enable bit (REN8) in the UART Receive
Control register (URC) is set. A low (spacing)
condition on the Receive Data line (P30) indicates
a ,.tart bit. If this low persists for at least
one-half of a bit time, the start bit is assumed
to be valid and the data input is then sampled at
the middle of each bit time until the entire
character, is assembled and placed in the Receive
Data (UIOR) register. This method of detecting a
start bit improves error rejection when noise
spikes exist on an otherwise marking line.
If Xl clock mode is selected, bit synchronization
must be accomplished externally, and the received
data is sampled on the rising edge of the clock
input.
A received character can be read from the 8-bit
Receive Data register (UlOR).
The receiver
inserts ls into the unused bits when a character
length of other than eight bits is used.
-If
parity is enabled, the parity bit is not stripped
from the assembled character for character lengths
less than eight bits; i.e., for lengths less than
eight bits, the receiver assembles a character for
the required number of data bits, plus a parity
bit, wake-up bit, and ls for any unused bits, and
places it in the UART Data register (UlO).
PARITY

PARITY

MARKING LINE

DATA

DATA

* NOTES: 1. Parity, wake.-Up, and second stop bit are optional

2. Data can be anywhere from 5 to 8 bits

Figure 10-1. Async~ronous Transmission Data Format

614

UART
Since the receiver is buffered by one B-bit
register in addition to the Receive Data register,
the CPU has enough time to serv ice an interrupt
and to accept the data character assembled by the
UART. The receiver also has a buffer that stores
error flags for each data character in the receive
buffer. These error flags are loaded at the same
time as the data character.

•

parity is enabled, the P~rity Error bit
(PERR) in the UART Receive Control (URC) register is set to 1 whenever the parity bit of the
character does not match the programmed
par i t y. Once this bit is set, it remains set
until cleared by software.

•

The Framing Error bit (FERR) in the URC register is set to 1 i f the character is assembled
without any stop bits (i.e., a low level is
detected for a stop bit) and it is set with the
character on which it occurs. It stays latched
until cleared by software.

•

If the CPU fails to read a data character when
more than one character has been received, the
Receive Overrun Error bit (OVERR) in the URC is
set to 1. When this occurs, the new character
assembled replaces the previous character in
the Receive Data register. With this arrangement, only the overwriting character is flagged
Like the
with the Receive Overrun Error.
Parity Error bit, this bit can be cleared only
by software command from the CPU.

'After a character is received, it is checked for
the following conditions:
•

•

If the received character is an ASCII control
character, it sets the Control Character Detect
(ceo) bit in the UART Receive Control CURC)
register.
(An ASCII control character is any
character that has bits 5 and 6 cleared to 0.)
It can also cause an interrupt if the Control
Character Interrupt Enable (CCIE) bit in the
UART Interrupt Enable (UIE) register is set to
1. Once this bit is set, it remains set until
cleared by software.
The wake-up settings are checked and any
indicated action is completed.
In wake-up
mode, the CPU can be selectively interrupted on
a match condition that includes all of the
eight bits in the received character and a
Wake-Up bit. The Wake-Up bit match and character match can be enabled simultaneously or
individually. Each bit in this character match
(For more
can also be masked individually.
discussion of this feature, see section 10.4.)
Once this bit is set, it remains set until
cleared by software.

RECEIVER

If

10.. MAKE-UP FEATURE
The SuperB offers a powerful scheme to configure
the UART receiver to interrupt only on certain
special match conditions. Figure 10-2 shows the
logic diagram for the scheme.

rr

~~~~t: ~.-----------VALUE

RECEIVED
WAKE-UP
BIT

Figure 10-2. Logic Diagram for Wake-Up Feature

615

UART
The pattern match logic can be used with or without the Wake-Up bit. The Wake-Up Match register
and Wake-Up Mask register determine the character
or characters that will generate a pattern match
when detected at the receiver. If the Wake-Up bit
is enabled, the pattern match occurs if the
Wake-Up bit in the received character matches a
pre-determined value, and the received character
matches the value(s) specified in the Wake-Up
Match and Wake-Up Mask registers. I f the Wake-Up
bit is disabled, the pattern match depends only on
the character's value.
The Receive
buffer that
received and
by the CPU.
contains the
register is
Case 1:

a)

Data (UIOR) register is the receive
is loaded if a new character is
the previous character has been read
The Wake-Up Match (WUMCH) register
match value. The Wake-Up Mask (WUMSK)
used to mask out any selected bit

IlUENB

positions in the WUMCH register.
The Wake-Up
Enable (WUENB) bit in the UART Transmit Control
(UTC) register is enabled only if a match for the
Wake-Up bit is also desired. If this is disabled,
the scheme can still be used to look for a character match. The Receive Wake-Up Vaiue (RWUVAL) bit
in UART Mode A (UMA) register is the expected
value of the Wake-Up bit; the Received Wake-Up bit
(RWUIN) is the Wake-Up bit value received by the
receiver.
The following cases show how the Wake-Up Detect
(WUD) bit in the UART Receive Control (URC) register can be set by' a match condition. However, the
CPU is interrupted only if the Wake-Up Interrupt
Enable (WUIE) bit in the UART Interrupt Enable
(UIE) register is set to 1.

= 1 (Wake-Up bit is enabled)

If Wake-Up bit match and WUMCH match (all 8 bits) is desired:
Set WUMSK = 1111
WUMCH =

1111 (%FF)
(desired match value)

If WUMCH (bits 7-0) = UIO (bits 7-0) and
RWUVAL = RWUIN
Then Wake-Up Detect (WUD) flag is set.
b)

If Wake-Up bit match and WUMCH match (selected bit, i.e., bits
5, 4, 1, 0) is desired:
Set WUMSK = 0011 0011 (%33)
WUMCH = XX__ XX__ (desired match bits 5, 4, 1, 0)
If WUMCH (bits 5, 4, 1, 0) = UIO (bits 5, 4, 1, 0) and
RWUVAL = RWUIN
Then Wake-Up Detect (WUD) flag is set.

c)

If only a Wake-Up bit match is desired:
Set WUMSK = 0000
WUMCH = XXXX

0000 (%00)
XXXX (don't care)

If RWUVAL = RWUIN
\

Then Wake-Up Detect (WUD) flag is set.

616

UART
Case 2:
a)

1IIlEN8

=0

(Wake-Up bit is ignored)

If a match is desired for WUMCH (all B bita):
Set WUMSK = 1111
WUMCH =

1111 (%ff)
(deaired match value)

If WUMCH (bits 7-0)

= UIO

(bits 7-0)

Then Wake-Up Detect (WUD) flag is set.
b)

If a match is desired on WUMCH (selected bits only, i.e., bits 4, 3, 2):
Set WUMSK
WUMCH

0001

1100 (%1C)

XXX____XX (desired match bits 4, '3, 2)

If WUMCH (bits 4, 3, 2) = UIO (bits 4, 3, 2)
Then Wake-Up Detect (WUD) flag is
c)

s~t.

If a match is always desired:
Set WUMSK = 0000 0000 (%00)
WUMCH
XXX X XXXX (don't care)
If this charecter ia received, the Wake-Up Detect (WUD) flag is alway a
set.
However, this will be ignored if the Wake-Up Interrupt Enable
(WUIE) bit in the UART Interrupt Enable (urE) register is disabled.

,10.5 AUTO-ECIIJ/UJOPBACK

register must be set to 1 for this mode to work
correctly.

As shown in figure 10-3, the UART can be configured to automatically transmit any data coming in at
the Receive Data input pin (P30) RXO. This autoecho mode of operation is enabled by setting the
Auto-Echo (AE) bit in the UART Mode B (UMB) register to 1. In addition, the Transmit Data Select
(TXOTSEL) bit in the UART Transmit Control (UTC)

RECEIVE DATA (RxD)

Similarly, the UART can be set in the local loopback mode by setting the Loopback Enable (LBENB)
bit in the UMB register to 1. In loopback mode,
the output of the trsnsmitter is automatically
routed to the receiver.

r

RECEIVE DATA IN (RxIN)

I

---~.--''-----..

P30 .....------------'---'-------.....

RECEIVER

I

LDDPBACK

AUTOOEC::J

B

ENABLE
(UMB]

~
LOOPBACK

TRANSMIT
DATA SELECT
(UTC]

(TxDTSEL = 1)
TxDATO_TxD
RxD-RxIN
Th:DATO-RxIN
TxDATO-TxD
RxD-RxIN
RxD-TxD
TxDATO RxlN
RxD ------- TxD

Figure 10-3. Auto-Echo/Loopback

617

UART
In auto-echo mode, the transmitter can still be
enabled; however, the transmitter data goes
nowhere unless loopback is also enabled.

The baud-rate, generator consists of two 8-bit Time
Constant registers, a 16-bit downcounter, and a
flip-flop on the counter's output that produces a
square wave.

10.6 POLLED OPERATION

In a polled environment, the Receive Character
Available (RCA) bit in the URC register must be
monitored ao the CPU can decide when to read a
character. This bit is automatically cleared when
the urOR is read.
To prevent ,overwriting data in polled operations,
the transmit buffer status must be checked befone
writing to the trensmit buffer (UrOT).
The
Transmit Buffer Empty (TBE) bit in the UTC is set
to 1 after completing the sending of a chsracter.

10.7 BAW-RATE GENERATOR

The UART has its own on-chip programmable baudrate generator implemented as a 16-bit downcounter. The transmitter can receive its clocking
signal 'from an external source (P21) or the baudrate generator (BRG); the receiver clock can come
from an external source (P20) or the on-Chip
baud-rate generator.

On startup, the flip-flop is set to a high state,
the value in the Time Constant registers is loaded
into the Counter, and the Counter starts counting
down.
The output of the baud-rate generator
toggles on reaching zero, the value in the Time
Constant registers ia again loaded into the
Counter, and the process is repeated. The time
constant can be changed at any' time, but the new
value does not take effect until the next load of
the Counter.
As shown in Figure 10-4, the output of the baudrate generator can be used as the receive clock,
the transmit clock, or both. The transmitter and
receiver can handle data, at a rate of 1, 1/16th,
1/32nd, or 1/64th of the clock rate supplied to
the receive and transmit clock inputs.
If P21 (Port 2, Bit 1) is not used as transmit
clock input, it may be used as an output.
A
multiplexer (MUX) prov ided at P21 can be used to
output various clocks or'P21 data; bits 6 and 7 of
the UMB register determine the function of P2 when
it is used as an output.

If P21 is not used as a Transmit Clock input, it
can be uaed to output the transmit clock, the CPU
clock, the output of the baud-rate generator, or
as an I/O line.

RECEIVE CLOCK SELECT
(UMB)

•

p,. r - -......------------,

TRANSMITTER
CLOCK

TRANSMIT CLOCK SELECT
(UMB)

~

CLOCK OUTPUT SELECT (UMB)

Figure 10-4, Baud-Rate Generator

618

UART
10.8 UART INTERFACE PINS

10.9.2 Wake-Up Match Register (WUMCH)

The UART uses up to four Port 2 and 3 pins for
interfacing with the external world. These are:

Any character up to eight bits can be written into
this register. The receiver detects a match
between the received character and this character.
The format of this register is shown in
Figure 10-6.

Receive Clock
Receive Data
Transmit Clock
Tran!jl1lit Data

10.9

R25' BANK 1 (FE) WUMCH
WAKE-UP MATCH REGISTER

UART CONTROL/MODE AND STATUS REGISTERS

' - - - - - - - THIS BYTE, MINUS MASKED BITS,
IS USED FOR

The following sections and figures describe the
UART Control/Mode and Status registers.

10.9.1

•

UART Data Register (UIOT & UIOR)

MATCH

Figure 10-6. Wake-Up Match Register

10.9.3 Walce-Up Mask Register (WIJ4SI()

Writing to this register automatically writes the
data in the Transmit Data register (UrOT); a read
from this register gets the data from the UART
Receive Data register (UrOR). The format of this
register is shown in Figure 10-5.

Any bit in the WUMCH register can be masked by
writing a 0 into the corresponding bit in this
register. The format of this register is shown in
Figure 10~7.
R255 BANK 1 (FF) WUMSK
WAKE-UP MASK REGISTER

R239 BANK 0 (EF) UIO

UART TRANSMIT DATA (WRITE)
UART RECEIVE DATA (READ)

L-_____

WAKE~UP

I~I~I~I~I~I~I~I~I

IL-_____
DATA (Do

= LSB)

THESE BITS CORRESPOND TO BITS
IN WAKE-UP MATCH REGISTER; Os
MASK CORRESPONDING MATCH BITS

Figure 10-7. Wake-Up Mask Register

Figure 10-5. UART Data Register

this bit to O. A write to this bit position has
no effect. A hardware reset forces this bit to O.

10.9.4 UART Receive Control Register (URC)
The fields in this register (Figure 10-8) are:
RCA. Receive Character Available (DO)' This is a
status bit that is set to a 1 when data is available in the receive buffer (UIOR). When the CPU
reads the receive buffer, it automatically clears

RENB. Receive Enable (01)' When this bit is set
to 1, the receive operation begins. This bit
should be set only after all other receive parameters are established and the receiver is completely initialized. This bit is cleared to a 0 by
a hardware reset, which disables the receiver.

R236 BANK 0 (EC) URC
UART RECEIVE CONTROL

C~NTROL

1=

1

=

WAKE_UPDETECT~gjj

CHARACTER DETECT
1 = BREAK DETECT
1 = FRAMING ERROR

~

IIILL"~"","AA~"_
1 = RECEIVE ENABLE
1

= PARITY ERROR

- 1 = OVERRUN ERROR

Figure 10-8. UART Receive Control Register

619

UART

, PERR. Parity Error (Dt).

This is a status bit:
When parity is enabled, this bit is set to 1 and
buffered with the character whose parity does not
match the programmed parity (even/odd). This bit
is latched so that once an error occurs, it
remains set until it is cleared to 0 by writing a
1 to this bit position.
A hardware reset forces
this bit to O.
OVERR. Overrun Error: (OJ), This status bit indicates that the receive buffer has not been read
and another character has been received. Only the
character that has been written over is flagged
with this error; once set, this bit remains set
until cleared to 0 by writing a 1 to this bit
position. A hardware reset forces this bit to O.

FERR. Fraaing Error (04)'

This is a status bit.
If a framing error occurs (no stop bit where
expected), this bit is set for the receive character in which the framing error occurred. This bit
remains set until cleared to 0 by writing a 1 to
this bit position. A hardware reset forces this
bit to O.
IlRKD.
that
break
stays

Break Detect (05)' This is a status bit
is set at the beginning and the end of a
sequence in the receive data stream. It
set to 1 until cleared to 0 by writing a 1

to this bit position. A hardware reset forces this
bit 'to O.
See note in section 10.9.5 for _more
information.

ceo.

Control Character Detect (06)' This status
bit is set any time an ASCII control character is
received in the receive data stream. It stays set
until cleared to 0 by writing a 1 to this bit
position. (An ASCII control character is any
character that has bits 5 and 6 set to 0.) A hardware reset forces this bit to O.

WUD. Wake-Up Detact (07)'

This status bit is set
any time a valid wake-up condition is detected at
the receiver. It stays set until cleared to 0 by
writing a1 to this bit position.
The wake-up
condition can be satisfied in many possible ways
by the Wake-Up bit, Wake-Up Match register, and
Wake-Up Mask register.
See the Wake-Up Feature
section (section 10.4) for a more detailed explanation. A hardware reset forces this bit to O.

10.9.5

UftRT Interrupt Enable Register (UIE)

This register' contains the individual status and
data interrupt enables (Figure 10-9). The fields
in this register are:

R237 BANK 0 (ED) UIE
UART INTERRUPT ENABLE

1

= WAKE-UP INTERRUPT ENABLE
1 = CONTROL CHARACTER
INTERRUPT ENABLE

J~.
I

~

1 = BREAK INTERRUPT ENABLE
1 = RECEIVE ERROR INTERRUPT
ENJ;\BLE

III

Lh"_,""~~"~U~
=
,

1

,INTERRUPT ENABLE
RECEIVE OMA ENABLE

1 = TRANSMIT INTERRUPT ENABLE

1

= ZERO COUNT INTERRUPT ENABLE

Figure 10-9. UART Interrupt Enable Register

RCAIE. Receive Character Available Interrupt
Enable (Do>. I f this bit is set to 1. then a
Receive Character Available status in the URC
register will cause an interrupt request.
In a
DMA receive operation, i f this bit is set to 1,
then an interrupt request wi 11 be issued onl y i f
an End-of-Process (EOP) of the DMA counter is also
set.
If it is not set, a Receive Character
Available status causes no interrupt. A hardware
reset forces this bit to O.
RIlMAENB. Receive
is set to 1, the
UART receiver.
Available signal
DMA request wi 11
gains control of

620

IJ4A Enabie (0,).

When this bit
DMA function is enabled for the
Whenever a Receive Character
in the URC register is true, a
be made. When the DMA channe I
the bus, it will transfer the

received data to the register file or the external
memory. A hardware reset forces this bit to O.
TIE. Transmit Interrupt Enable (Dt). If this bit
is set to " then a Transmit Buffer Empty signal
ill the UTe register wi 11 cause an interrupt
request. In a DMA 'transmit operation, if this bit
is set to 1, then an interrupt request will be
issued only i f an End-of-Process (EOP) of the DMA
counter is also set. If it is not set, a Transmit
Buffer Empty signal causes no interrupt.
A
hardware reset forces this bit to O.
ZCIE. Zero Count Interrupt Enable (OJ)' I f this
bit is set to 1, a baud-rate generator Zero Count
status in the UTC register will cause an interrupt
request. A hardware reset forces this bit to O.

UART
REIE. R_ive Error Interrupt Enable (D.). If
this bit is set to 1, any receive error condition
will cause an interrupt request. Possible receive
error conditions include parity error, overrun
error, and framing error. A hardware reset forces
this bit to O.
BRKIE. Break Interrupt Enable (D5)' If this bit
is set to 1, a transition in either direction on"
the break signal will cause sn interrupt request.
A hardware reaet forces this bit to O.
Note: A break siqnal is a sequence of Oa
When
all the required bits, parity bit, wake-up
bit, and stop bits are Oa, the receiver
immediately recognizes a break condition (not
a framinq error) and causes Break Detect
(BRKD) to be aet and an interrupt request. At
the end of the break Signal, a zero character
is loaded into the Raceive Data regiater
(UIOR) and Break Detect (BRKD) is set again,
alonq with another interrupt request.
o
•

CCIE. Control Dlaracter Interrupt Enable (D6)' If
this bit is set -to 1, then an ASCII Control
Character Detect signal in the URC register will
cause an interrupt. A hardwa're r~set forcea this
bit to O.
lIUIE. Walce-Up Interrupt Enable (OJ). If this bit
is set to 1, then any of the wake-up conditions
that set the Wake-Up Detect bit (WUD) in the URC
register will cause an interrupt request. A hardware reset forces this bit to O.
10.9.6

IlART

ibis

A Register (IlIA)

This register controls the configurations of the
receiver/transmitter that are not likely to change
on a dynamic basis. The fields in this register
(Figure 10-10) are:

'
Llli

R250 BANK 1 (FA) UMA
UART MODE A

C~KR~E:r

o-,D,

OO=X1

o

1

= X16

1 0
1 1

=X32
= X64

L

L

TRANSMIT WAKE-UP VAWE
RECEIVE WAKE-UP VAWE

1 = EVEN PARITY

1 = PARITY ENABLE

BITS PER CHARACTER
D5 D4

0 0 =SBITS
o

1
1 0
1 1

.. 6BITS
= 7 BITS "
=8BJTS

Figure 10-100 UART Mode A Register

NUVAl. Tr..-it Wake-Up Value (DO)'
I f the
wake-up mode is enabled, then the value in this
bit position is transmitted along with the character at the appropriate time by the transmitter.
RWUVAl. ~ive WaIce-Up Value (01)' If the wakeup mode is enabled, then the receiver expects a
wake-up bit after the parity bit in the incoming
data stream and the value is compared with this
bit value. For further explanation of how this is
used, see the Wake-Up Feature section (Section
10.4) •.
EVNPAR. Even Parity (Dz). This bit determines the
type of parity used by both the receiver and the

transmitter. If this bit is set to 0, odd parity
is uaed; if this bit is set to 1, then even parity
is used. If the Parity Enable (PARENB) bit in this
register is not enabled, then this bi t has no
effect.
PARENB. Parity Enable (0,). When this bit is set
to 1, an additional bit position beyond those
speci fled in the bi ts/ character control is added
to the transmitted data and' is expected in the
received data. Jhe received parity bit is transferred to the CPU as a part of the data unless"
eight bits per character are used. If this bit is
set to 0, the parity feature is disabled.

621

UART
BPC1. B!'CO. Bits Per Character, (D5. D4)' This
, fie ld determines the number of bits per character
for both the, transmit and the receive sections.
The character bits are' right-justified with the
least significant bit transmitted or received
first.
The field is coded as shown in Table
10-1.

Table 10-1. Dlllracter Size F;ield £ncoding
Ct!aracter Size in Bits

o

5

0

ri

CRO. Clock Rate (Iry.' D,).
This field
specifies the multiplier between the clock and the
, data rates. Table 10-2 shows how this field is
coded.
eft1.

Table 10-2.
~ ~

Ibte

0
0
1

1
16
32
64

0
0

6

o

Clock Rete Field £ncoding

x
x
x
x

Deacl'iption
Clock
Clock
Clock
Clock

rate
rate
rate
rate

= 1 x data rate
= 16 x data rate
= 32 x data rste
= 64 x data rate

7
B
R235 BANK 0 (EB) UTC
UART TRANSMIT CONTROL

TRANSMIT DATA SELECT:
o = OUTPUT P3, DATA
1 = OUTPUT TRANSMIT DATA
1

j

I

=SEND BREAK
SlOP BITS:
0= 1 STOP BIT

~
I

" L
,

L

1

=TRANSMIT DMA ENABLE

1 = TRANSMIT BUFFER EMPTY
1 = ZERO COUNT
1 = TRANSMIT ENABLE

1 = 2 STOP BITS
1

= WAKE·UP ENABLE - - - - - '

Figure 10-11. UART Thmsmit Control Register

10.9.7 UART lrana.it Control Register (UTC)
This register contains the status and command bits
needed to control the trsnsmit section of the
• UART. The fields in this register (figure 10-11)
srel

TENB. lr_it Enable (D,>.
Dsta is not
transmitted until this bit is set to 1. When
cleared, to 0, the Transmit Data pin continuously
outputa 1s unless Auto-Echo mode is selected.
This bit should be cleared only after the desired
transmission of data in the buffer is completed.
A hardware reset forces this bit to O.

1DI4AEte. lr~t IlM Enable (00).

When this bit
is set to 1, it ensbles the DMA function for the
UART transmit section. If this bit is set and the
Transmit Buffer Empty signal becomes true, then a
DHA request is made. When the DHA channel gains
con.trol of the bus, it transfers bytes from the
sxternal memory' or the register file to the UART
transmit section. A hardware reset forces this
bit to O.
TIE. lrana.it Buffer ~ty (D1)' This status bit
is set to 1 whenever the transmit buffer is
empty. It is cleared to 0 when a data byte is
written in the transmit buffer. A hardware reset
forces this bit to 1.
ZC. Zero Count (Dz). This status bit ia set to 1
and latched when the Counter in the baud-rate
generator reachea the count of O. This bit can be
cleared to 0 by writing a '1 to this bit poaition.
A hardware reset forces this bit to O.

622

IIIENB. waJce-lJp Enable (D4>' 1f this bit ia set to
1, wake-up mode is enabled for both the transmitter and the receiver. The transmitter adds a bit
beyond those apecified by the bita/character and
the parity. This added bit has the value apecified
in the Transmit Wake-Up Value (TWUVAL) in the 'UMA
regiater.
The, receiver expects a Wake-Up bit
value in the incoming data stream after the par~ty
bit and comparee this value with that specified in
the Received Wake-Up Value (RWUVAL) bit in the UMA
regiater.
The resuUing action depends' on the
configuration of the Wake-Up feature. A more
complete description is given in the Wake-Up
feature section (sectio~ 10.4). A hardware reset
forces this bit to O.
SlPBlS. ~top Bits (D5)' This bit determines the
'number of stop bits added to each character, transmitted from the UART transmit aection. If this bit
is aD, then one stop bit is added. I f this bit,

UART
is a 1, then two' stop bits are sdded."
The
receiver always checks for at least one stop bit.
A hardware reset forces this bit to O.
SENBRK. 'Send Break (06)' When set to 1, this bit
forces the transmit aection to continuously output
Os, beginning with the following transmit clock,
regardless of any data being transmitted at the
This bit functions whether or not the
time.
transmitter is enabled. When this bit is cleared
to 0, the transmit section continues to send the
contents of the Transmit Data register. A hardware reset forces this bit to O.

output. If this bit is set to 1, the serial data
coming out of the transmit section is reflected on
the P31 pin. I f this bit is set to 0, then P31
acts as a normal port and P3 1 data is reflected on
t~e P31 pin.
A hardware reset forces this bit to
O.

10.9.8 UART Mode B Register (!MI)
This register (Figure 10-12) contains the necessary status and command bits for the baud-rate
generator, transmit clock select, auto-echo and
loopback enable. The fields are as follows:

TXDTSEL. Tr __it Data Select (07)' This bit has
an effeet only if port pin P3 1 is confiqured as an

'
E

R251 BANK 1 (FB) UMB
UART MODE B

CLOCK OUTPUT SELECT

==r-

0706
o 0 = P21 DATA
o 1 = SYSTEM CLOCK (XTAL/2)
1 0

= BAUD· RATE GENERATOR

1 1

= TRANSMIT DATA CLOCK

OUTPUT
1

L

L

1 = LOOPBACKENABLE
1

= BAUD-RATE GENERATOR ENABLE

BAUD-RATE GENERATOR SOURCE:

o = P20 (EXTERNAL)
1

= INTERNAL (XTALl4)

TRANSMIT CLOCK INPUT SELECT:
0= P21
1 = BAUD-RATE GENERATOR OUTPUT

= AUTO-ECHO

RECEIVE CLOCK INPUT SELECT: - - - - - - '
0= P20
1 = BAUD-RATE GENERATOR
OUTPUT

Figure 10-12_ UART Mode B Register

LBENB. Loopback Enable (00)' Setting this bit to
1 selects the local loopback mode of operation. In
this mode, the data output from the transmit
section is also routed back to the receive
section. For meaningful results, the frequency of
the transmit and receive clocks must be the same.
A hardware reset forces this bit to O.
BRGENB. Baud-Rate Generator Enable (01)' This bit
controls the operation of the baud-rate generator.
The Counter in the baud-rate generator is
enabled for counting when this bit is set to 1 and
disabled for counting when this bit is set to O.
A hardware reset forces this bit to o.

oItcsRc.

Baud-Rate Generator Source (Dz). This bit
selects the source of the clock for the baud-rate
generator. If this bit is set to 0, the baud-rate
generator clock comes from the receive c lock pin
(P20). If this bit is set to 1, the clock for the
baud-rate generator is the CPU clock divided by
two (XTAL clock divided by four). A hardware reset
forces this bit to O.

TCIS. Tr __it Clock Input sele~t (0,). This bit
selects the source for the transmit section clock
input. If TCIS is cleared to 0, the source is the
transmit, clock pin (P21). If it is set to 1, then
the source is the baud-rate generator output. A
hardware reset forces this bit to O.
ReIS. Receive Clock Input Select (04)' This bit
selects the source for the receive section clock
input. If this bit is cleared ,to 0, the source is
the receive clock pin (P20). If it is set to 1,
then the source is the baud-rate generator output. A hardware reset forces this bit to O.

At.

Auto-Echo (05). Auto-echo mode of operation
is enabled by setting this bit to 1.
In this
mode, the data coming in on the receive data pin
is reflected out on the transmit data pin. The
receive section still listens to the receive data
input; however, the data from the transmit section
goes nowhere. See section 10.6 for a more detailed description of this function. A hardware reset
forces this bit to O.

623

UART

COS1. coso. Cloc:lc OutjM.lt Select (0,4),). ,This
field determines the source that drives the
transmit clock pin i f P21 is configured as an
Table 10-3.

o
o

0

1

0

output.
A hardware reset forces thia field to
00. Table 10-3 shows the coding of this field.

Tr.....tt Clock Source Field £ncoding

P21 Data
Syatem clock (XTAL frequency divided by 2)
Baud-rate generator output
Transmit data rate

1

Register (IIIG)

value does not take effect until tlie next time
constant is loaded into the downcounter.

This register contains the high and low bytes
(Figure 10-13) for the 16-bit time constant, used
to generate the desired baud rate.
The time
constant can be changed at any' time, but the new

The formula for determining the appropriate time
constant for a given baud rate is shown below,
with the desired rate in bits per second and the
baud-rate clock period in a~conds.

10.9.9

lIART Baud-Rate Generator Tille Conatri

time constant: _ _ _ _ _ _ _- - - - - - - - - -_ _ -1
(2 x baud rate x n x BRG input clock period)
where n:l,16,32,or 64 x the clock rate selected in UMA register R250
R24B BANK 1 (FB) UBGH
UART BAUQ.RATE GENERATOR

R249 BANK 1 (F9) UBGL
UART BAUQ.RATE GENERATOR

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

IL--____

HIGH BYTE (USG..USG,s)

, - I_ _ _ _ _

LOW BYTE (UllGo-UBG7)

Figure 10-13. UART Baud-Rate Generator Time Constant Register

P~ ~--~~--------~

RECEIVE CLOCK SELECT
(UMB)
(.1)

RECEIVER
CLOCK

TRANSMITTER
CLOCK

-

(+1)

(~O} PORT 2 DATA

TRANSMIT CLOCK SELECT
(UMB)

(OI) SYSTEM CLOCK

(10)

FigUre 10-14, Baud-Rate Generator

624

Chapter 11
DMAChannel
11.1

INTRmU:TION

The OMA Count registers (R240 and R241 , Bank' 1)
hold the 16-bit count that determines the number
of transactions the OMA channel is to perform. The
count loaded should be n-1 to perform n byte
transfers. An interrupt can be generated when the
c~unt is exhausted.

The SuperB has an on-chip Direct Memory Access
(DMA) channel to provide high bandwidth data
transmission capabilities that can be used by the
UART receive or transmit section or by Handshake
Channel O.

OMA transfers to or from the register file take
six CPU clock cycles; DMA transfers to or from
memory take ten CPU clock cycles, excluding wait
states.

The DMA channel can transfer data between the
peripheral device and contiguous locations in
either the register file or external data memory.

------>

Register file or
data memory

UART Transmitter

<------

Register file or
data memory

Handshake Channel 0

<------

Register file or
data memory

Handshake Channel 0

------>

Register file or
data memory

UART Receiver

11.2 DNA CONTROL REGISTERS
The control bits that link the DMA channel to the
UART or an I/o port are the Transmit OMA Enable
(T~MAENB) bit in the UART Transmit Control (UTC)
register for the transmitter, the Receive DMA
Enable (ROMAENB) bit in the UART Interrupt Enable
(UIE) regiater for the receiver, ,and the OMA
Enable bit (02) in the Handshake 0 Control register for the I/O ports. Only one of these three
enable bits should be .set at' a given time.
If
Handshake Channel 0 is linked to the OMA channel,
the data transfer direction is determined by the
direcqon of the handshake.

Prior to enabling the DMA channel, the starting
register address for the block to be transferred
must be present in register C1H or the starting
memory address must be present in register COH
(high byte) and C1 H (low byte).
Registers COH
and C1 H themselves can only be accessed as part
of the working register group.
The address is
auto-incremented
after
each
DMA-controlled
transfer.

A bit in the External Memory Timing register,
called OMA INT/EXT, controls whether DMA transfers
access the register file or external data memory.
When this bit is cleared to 0, transfers are tot
from the register file. When this bit is set to
1, transfers are to/from external data memory.
See figure 11-1.

R254 (BANKO) EMT
EXTERNAL MEMORY TIMING REGISTER

I~I~I~I~I~I~I~I~I

L

DMA INT/EXT
1

= EXTERNAL MEMORY

o = REGISTER FILE
R240 (BANK1) DCH
DMA COUNT HIGH

R192 (CO) RPO = CO
DMA ADDRESS HIGH

R241 (BANK1) DCl
DMA C6UNT LOW

R193 (Cl) RPO = CO
OMA ADDRESS lOW

Figure 11·1. DMA Control Registers

625

DMA Channel
11.3

DMA AN> THE UART RECEIVER

The Receive DMA Enable bit (RDMAENB) in the UIE
register (RU7) of the UART is first set to 1 to
link the DMA to the UART receiver.
Data received at the UART receiver is handled by
the DMA as soon as the Receive Character Available
(RCA) status bit of the URC register (R236) of the
UART is set to 1.
The DMA reads data from the
U10 register of the, UART and then clears the RCA
bit to prepare the UART receiver to receive new
data.
The data is then atored at the location
whose address is contained in the DMA address register (RRl92). The DMA count at RR240, Bank 1, is
decreased' by 1 and the DMA address register is increased by 1. When the DMA count is negative, an
interrupt request (IRQ6, vector address 20, 21) is
generated at the UART Receive section if the
Receive Character Available Interrupt Enable bit
of the UIE register of the UARr (R237) is set to
1.
The UART continues to receive new data and the DMA
responds to t,he RCA bit as described above until
an interrupt is generated due to a negative DMA
count.
11.4 DMA AN> IHE UART TRANSMITTER
First, the Transmit DMA Enable (TDMAENB) bit of
the UTC register (R235) of the UART is enabled to
link the DMA to the UART transmitter.

Upon transmit, the Transmit Buffer Empty status
bit (TBE) in the UTC register (R2,35) of the UART
is set to 1. The DMA then transfers the data at
the location whose address is contained in the DMA
address register (RR192) to the UIO register
(R239) of the UART.
The TBE bit is then cleared to O. The DMA count
at RR240, Bank 1, is decreased by 1 and the DMA
address register is increased by 1. When the DMA
count is negative, the DMA issues an End-ofProcess (EOP) signal to the UART. The UART grants
an interrupt request (IRQ1, vector address 26, 27)
to the SuperB if the Transmit Interrupt Enable
(TIE) bit of the OlE register (R237) of the UART
is set to 1.
The UART transmitter continues its operation with
the new data in the U10 register and the DMA responds to the TBE bit as described above until an
interrupt is generated due to a negative DMA
count.
11.5

DMA AN> HAN>SHAKE CHANNEL D

The DMA can be configured with Handshake Channel 0
to transfer data from register fi Ie or data memory
to 1/0 devices or vice versa through Port 1 or
Port 4.
Handshake Channe 1 0 can be in either
full y inter locked mode or strobed mode as controlled by the Handshake 0 Control register
(R244). The direction of OMA transfer is' determined by the handshake direction, which is the
direction of the chosen port.
11.5.1

DMA WRITE (INPUT HAN>SHAK[ CHANNEl,D)

The I/O device transfers data to register fHe or
data memory through Handshake Channe 1 0 and the
OMA channe 1.

626

DMA Channel
The Handshake Channel 0 Enable and DMA Enable bits
of the Handshake 0 Control (HOC) register (R244)
should be first set to 1.
When the I/O device
puts data on the port specified in the HOC register and activates ~ to go from high to low as in
figures B-11 and B-13, the DMA transfers data on
the port to the specified address in the DMA
address register (RR192). The DMA count at RR240,
Bank 1, is decreaaed by 1 and the DMA address register is increased by 1. When the DMA count is
negative, the DMA issues an End-of-Process (EOP)
signa I to Handshake Channe I O. Hendshake Channe I
o grants an interrupt request (IRQ4) to the
SuperB.
The handshake output at pin 25 is the
same as described in figures B-11 and B-13 and the
DMA is waiting for the I/O device to put data on
the port and activate the ~ signal again.
11.5.2

IlMA READ (OUTPUT HAt«>SHAKE ClWN:L 0)

Data is transferred from register file or data
memory to the I/O device through the DMA chenne I
and Handshake Channel D.
The Handshake Channe I 0 Enable and DMA Enable bits
of the Handshake 0 Control (HOC) register (R244)
should be first set to 1. The handshake direction
should be set by choosing the direction of the
port specified in the HOC reg,ister.
The DMA sequence should always begin by writing
the first byte of data to the port to start the
DMA. This is an importa~t process, otherwise the
DMA is not activated when Handshake Channel 0 is
not yet activated.
The DMA starting address in
the DMA address register (RR192) should now be set
at the second byte of the data block. The I/O device should then read that fi rst byte of data and
store i t away as in figures B-12 and B-14.
The
DMA is then activated.

11.5.2.1

FILLY INTERLOCKED

MOO[

At State 3 of figure B-12, the DMA reads the data
at the address specified in the DMA address register (RRl92) and transfers it to the port. The DMA
count at RR24D, Bank 1, is decreased by 1 and the
DMA address register is increased by 1. When the
DMA count is negati ve, the DMA issues an End-o fProcess (EOP) signal to Handshake Channel O.
Handshake Channel 0 then grants an interrupt request (IRQ4) to the SuperB.
The DMA and handshake process continues as in
figure B-12 until an interrupt is caused by a
negative DMA count.
11.5.2.2

STROOED IDlE

After the first writing of the first byte of data
to the port as in figure B-14, the DMA is activated at ,the end of strobe time. The DMA reads the
data at the address spec} fied in the DMA address
register (RRl92) and transfers it to the port.
The DMA count at RR240, Bank 1, is decreased by 1
and the DMA address register is increased by 1.
When the DMA count is negative, the DMA issues an
End-of-Process (EOP) signal to Handshake Channel
O. Handshake Channe,! 0 then grants an interrupt
request (IRQ4) to the SuperB.
The handshake operation continues as in figure
B-14 and the DMA transfers new data to the port
only at the end of strobe time.
The DMA stops
when an interrupt is activated by a negative DMA
count.

DMA
ENABLE

--r==;:=tS[)-----

DMA
REQUEST

TO IRQ
REGISTER

ENDOFCO~~;

-

----L-'

.....

Figure 11-2. Interrupts and the DMA

627

Chapter 12
External Interface
. 12.1

INTRODUCTION

The 4B-pin SuperB has 40 programmabla I/O pina,
aome of which are configurable as an external
memory interface. A description of the pina and
their functions follows (see Figure 1~-1).

12.2 PIN DESCRIPTIONS
Address Strobe (output, active low~ l-atste).
is pulaed low once at the beginning of each
machine cycle. For external memory accesses, the
rising edge of 1m' indicates that addresses, RIW',
and DR signals are valid. Under program control,
1m' can be placed in a high impedance state along
with Ports 0 and 1, tm', R/i, and 1m i f uaed.

E.

1m'

M. Dats Strobe (output, active low, l-atate).
~.

provides timing for data movement to or from
Port 1 for each external memory transfer. During a

write cycle, data out is valid at the leading edge
of tm'; during a read cycle, data in ia valid prior
to tha trailing edge of~. ~ can be placed in
high-impedance state along with Ports 0 and 1,
~, R/W; and m:r if used.

a

R/V. Read/Write (output, l-atate). R/i determines the direction of data transfer for external
memory transactions.
R/i is low during write
operations and high duririg all other operations.
R/i can be placed in a high-impedance state along
with Ports 0 and 1, ~, ~, and m:r if used.
P1o-P17, PZg-PZ7. PJo-¥lJ. ~.7· I/O
Port . Linea
(inputs/outputs.
Tn-~patible).
These I/o lines provide five B-bit I/O ports that
can be configured under program control for I/O or
external memory interfacing. Ports a and 1 can be
placed in a high:"impedance state under program
control, along with ~, D'S", R/W, and 1m if uaed.

POo-P07,

PO.

po,
PO.
PO,

po,
po,
PO.

Po.
P3,
P3,

AS

os

SUPERS

P4.
P4,
VSS

P"

P"
RNi
RESET

P3.
P37
P27
P2.
P3.

Figure 12-1: Pin Functions lind Assignments

628

External Interface
~ is used
to initialize the SuperB.
When ~ is
deactivated, program execution ,begins from prQgram
address 0020 H• ~ is also used to enable the
SuperB test mode.

llr!:n". Reset (input, active low).

XTAl1, XTAl2. Crystsl (oacillator input/output).
XJAL 1 and XTAL2 are used to connect a parallel
resonant crystal or external c lock source to the
on-board clock oscillator and buffer.
12.3 CONFIGURING FOR EXTERNAl MEMORY
Before external memory can be referenced in a
ROM-based part, Ports 0 and 1 must be properly
configured.
The minimum bus configuration uses
Port 1 as a multiplexed_ address/data bus (ADO-AD7)
with access to 256 bytes of external memory. In
this configuration, the eight lower order address
bits (AO-A7) are multiplexed with the eight data
bits (DO-D7).
Additional address lines can be output on the Port
pins, where bit 0 of that port corresponds to
AB, bit 1 to A9' and so on. The pins of Port 0
can be defined as memory address lines or I/O
lines on a bit-by-bit basis, via programming of
the port 0 Mode register (R240, Bank 0).
This
ensures the efficient use of the I/O pins, allowing the SuperB to address various sizes of
external memory using no more pins than necessary.
Port 0 pins not configured for address
lines can be used as I/O lines.

Configuring Port 0 for external memory is accomplished in a similar manner, using Port 0 Mode
Registe~, R240 in Bank 0 (Figure 12-3).
Once Port 1 is configured as an address/data port,
it is no longer usable as a general-purpose 1/0
port.
Attempting to read Port 1 returns "FFH";
writing has no effect. Similarly, if Port 0 is
configured for address lines AB-A15' it is no
longer usable as a general-purpose I/O port; however, i f not all of the bits are defined as
address lines, the remalnlng bits are sti 11
accessible as an I/O port.
Reading Port 0 will
return the port data in those positions defined as
I/O. The positions defined as address will return
the value on the external pins which, under normal
loading, will be the address.
After- setting the modes of Ports 0 and 1 for
external memory, the next three bytes must be
fetched from internal memory.
An external memory interface may be 3-stated under
program control by setting bit 7 of the System
.Mode register, R222 (Figure 12-4).

o

Configuring Port 1 for external memory is accomplished by writing the appropriate bits in the
Port Mode register, R241 in Bank 0 (Figure 12-2).
R241 BANKO (F1)PM
PORT MOOE REGISTER

I~I~I~I~I~I~I~I~I

--c

PORT 1 MODE
00 = OUTPUT
01 = INPUT
1X ='ADo-AD7

Figure 12-2. Configuring Port 1 for External Memory
R240 BANKO (FO) POM
PORT 0 MODE REGISTER

' - - - - - - - - PORT 0 MODE
o DEFINES BIT AS I/O
1 DEFINES BIT AS ADDRESS

Figure 12-3. Configuring Port 0 for External Memory

R222 (DE) SYM
SYSTEM MODE REGISTER

I~I~I~I~I~I~I~I~I

T...__________ 3.STATE EXTERNAL MEMORY INTERFACE
Figure 12-4. 3-State External Memory Interface
When this bit is set to 1, the external memory
interface, including AS, OS, R/Wand iiM, is 3·stated.
A hardware reset forces th i s bi t to a O. The externa I
memory interface can but should not be tri -stated in
the ROMless parts.

In SuperB parts with on-chip ROM, a hardware reset
configures, Ports 0 and 1 as if;1put ports and
instruction execution begins at location 0020 H,
which is within the on-chip ROM.
In the ROM less parts, a hardware reset configures
Port 0 pins POO-P04 as address out and pins
P05-P07 as inputs; Port 1 is configured as an
address/data port, allowing access to B Kbytes of
memory. If externa 1 memory greater than B Kbytes
is desired, additional address lines must be
configured in Port O.
Since Port 0 lines are
initially configured as inputs, they will float
and their logic state will be unknown until an
initialization routine is executed that configures
Port O.
This initialization routine must reside
within the first 8 Kbytes of executable code and
must be physically mapped into memory
by
externally forcing the Port 0 address lines to a
known state.

629

External Interface

12.4 EXTERNAL STACKS

12.5 DATA MEMORY

The SuperB architecture supports stack operations·
in.either the register file or in data memory. A
stack's location is determined by setting bit 1 in
the External Memory riming register, R254, Bank 0
(Figure 12-5).

The two external memory spaces, data and program,
can be addressed as a single memory space or as
two separate spaces.
If the memory spaces are
separated, program memory and data memory are
logically selected by the Data Memory select output (15R). 15R is made available on Port 3, line 5
(P35 )by setting bit 03 in the Port Mode register
to 1 (Figure 12-6).

R2S' eANKO (FE) EMT
EXTERNAL MEMORY TIMING

1~1~1~1~1~1~I~j~1

~ STACKSELECTION
o

R241 BANKO (F1) PM
PORT MODE REGISTER

= REGISTER FILE

I~I~I~I~I~I~I~I~I

1 = DATA ME,MORV

T

o = P3s MODE OETERMINED BY PORT 2/3
C MODE REGISTER
1 = P3s
OM OUTPUT

=

Figure 12-5. External Memory Timing

The instruction used to change the stack se lection
bit should not be immediately followed by an
instruction that uses the atack, since this will
cause indeterminate program flow.
Interrupts
should be disabled when changing Jhe stack
se lection bit.

Figure 12-6. Data Memory

12.6 BUS OPERATION

are machine cycles (Mn), timing states (Tn), and
clock periods.
All timing references are made
with respect to the output signals ~ and~. The
clock is shown for clarity only and does not have
specific timing relationships with other signals;
the clock signal shown is the external clock,
which has twice the frequency of the internal CPU
clock.

Typical data transfers between the SuperB and
external memory are illustrated in Figures 12-7
and 12-B.
Machine cycles can vary from six to
twelve external clock periods depending on the
operation being performed. The notations used to
describe the basic timing periods of the SuperB

·~11

1-1"----T-1---- MACHI: E CYCLE----T-3--...
2

EXTERNAL
CLOCK

PO

PI

X
X

x:=

A.-A15

Ao~A70UT

B----C

>

'---I
I

\
R/W

L

I

X
I-

READ CYCLE

Figure 12-7. External Instruction Fetch or Memory Read Cycle

630

'-x:=

~I

External Interface

~I-----T-'---- MACHIN:.CYCLE - - - - - T . - - - I " ,

EXTERNAL
CLOCK

PO

Pl

AS

X
X

x::=
x::=

Aa-A 15

Ao-A7 IN

X

0 0-07 OUT

"-

'---J
I

\

os
R/W

~

OM

X
I-

C

WRITE CYCLE

x::=

-I

Figure 12-8. External Memory Write Cycle

12.6.1

Address Strobe ~

All transactions start with Address Strobe ('lim
being driven low and then raised high by the
SuperB.
The rising edge of AS" indicates that
Read/Write ~(R/W), Data Memory (~), and the
addresses output from Ports 0 and 1 are valid.
The addresses output via Port 1 typically need to
be latched during AS", whereas Port 0 address
outputs, if used, remain stable throughout the
machine cycle.

12.6.2 Data Strobe (U!;)
The SuperB uses Data Strobe (15m to time the
actual data transfer. For write operations (R~ =
low), a low on n"S" indicates that valid data is on
the Port 1 ADO-AD7 lines.
For read operations
(R/W = high), the address/data bus is placed in a
high-impedance state before driving ~ low so that
the addressed device can put its data on the bus.
The SuperB samples this data prior to raising ~
high.

12.6.3 External MeIIory Operations
Whenever the SuperB is configured for external
memory operations, the addresses of all internal

program memory references appear on the external
bus. This should have no effect on the external
system since the bus control line ~ remains in
its inactive high state. ~ becomes active only
during external memory references.

12.7 EXTENDED BUS TIMING
The SuperB can accommodate slow memory access and
cycle times by three different methods that give
the user much flexibility in the types of memory
available.

12.7.1

Software Progr...able Wait States

The SuperB can stretch the Data Strobe (15m timing
automatically, by adding one, two, or three
internal clock periods.
This is under program
control and applies only to external memory
cycles.
Internal memory cycles still operate at
the maximum rate.
The software· has independent
control over stretched Data Strobe for external
memory (i.e., the software can set up one timing
for program memory and a different timing for data
Illemory).
Thus, program and data memory may be
made up of different kinds of hardware chips, each
requiring its own timing.

631

External Interface
12.7.2

Slow Memory Ti.ing

All of the extended bus timing features are
programmed by writing the appropriate bits in the
External Memory Timing register (Figure 12-9).

Another feature of the, SuperS that is useful in
interfacing with slow memories is the Slow Memory
Timing option. When this option is enabled, the
normal external memory timing is slowed by a
factor of two (bus clock = CPU clock divided by
two) •
All memory times for set-up, duration,
hold, and access times are essentially doubled.
This feature can also be used with the programmed
automatic wait states described above. Programmed
wait states can still be used to stretch the Data
Strobe time by one, two, or three internal clock
times (not two, four, or six) when Slow Memory
Timing is enabled.

R254 BANKO (FE) EMT
EXTERNAL MEMORY TIMING REGISTER

L

I~I~I~I~I~I~I~I~I
DATA MEMORY AUTOMATIC WAITS
00 = NO WAITS
01 = 1 WAIT
10 = 2 WAITS
11 = 3 WAITS
PROGRAM MEMORY AUTOMATIC WAITS
00
NO WAITS
01 = 1 WAIT
10
2 WAITS
11
3 WAITS

=
=
=

' - - - - - - - - - - SLOW MEMORY TIMING
0= DISABLED
1 = ENABLED
' - - - - - - - - - - - EXTERNAL WAIT INPUT

o = P34 IS NORMAL 110
1

12.7.3 Hardware Wait States
Still another SuperS feature is an optional external mT input using port pin P34. The mT input
function can be used with either or both of the
above two features.
Thus the Data Strobe width
will have a minimum value determined by the number
of programmed wait states selected and/or by Slow
Memory Tim~ng. The mT input provides the means
to stretch i t even further.
The mT input is
sampled each internal clock time and, if held low,
can stretch the Data Strobe by adding one internal
clock period to the Data Strobe time for an
indefinite period of time.

= P34 IS EXTERNAL WAIT INPUT

Figure 12-9. External Memory Timing Register

12.8 INSTRUCTIONTIMING
The high throughput of the SuperS is due, in part,
to the use of instruction pipelining, where the
instruction fetch and execution cycles are overlapped. During the execution of the current
instruction, the opcode of the next instruction is
fetched, as illustrated in Figure 12-10.

INTERNAL
CLOCK

INSTRUCTION
N

INSTRUCTION
FETCH 1

OPERAND
FETCH(ES)

INSTRUCTiON

FETCH 2

.1'

ALU STORE

EXECUTION CYCLE

INSTRUCTION

INSTRUCTION
FETCH 1

N+1

OPERAND
FETCH(ES)

INSTRUCTION
FETCH 2

ALU STORE

EXECUTION CYCLE

INSTRUCTION

INSTRUCTION

FETCH 1

N+'
I •

1.,----

EFFECTIVE
- - - -...
EXECUTION TIME

HIDDEN DELAY
UNTIL COMPLETION

-I

I . , - - - - - - - - - - I N S T R U C T I O N COMPLETION T I M E - - - - - - - - - -••I

Figure 12-10. Instruction Pipelining

632

INSTRUCTION
FETCH 2

External Interface
internal clock periods shown in the cycles column
of the instruction formats in the Instruction Set
(Chapter 5) should be added. Pipeline cycles are
transparent to the user and should be ignored.
Each cycle represents two cycles of the crystal or
input clock.

figures 12-11 through 12-14 show typical instruction cycle timing for instructions fetched from
external memory.
All instruction .fetch cycles
have the same machine timfng regardless of whether
the memory is internal or eX,ternal except When'
external memory timing is extended. In order to
calculate the execution time of a program, the

M,
• T,

T,

T,

T,

T,

T,

T,

T,

T,

CLOCK
PO _ _ _ _....J 1...._ _ _ _

Aa.. :. .-A. ; ,: :, ____-..J 1...._ _ _ _ _ _ _ _ _ _-..,;.A;:,,.-...A.: 15:. . . __________

Pi _ _ _ _....JXC:A~o~A~,~~-----~::A~o~A~,~»-------------:......----~
IN
IN

\'---~/

\~

______________________-J/

--II

RIW _ _ _

i - F E T C H INSTRUCTION - - \ - - - ' - - - - - F E T C H 1ST BYTE OF NEXT INSTRUCTION------l

Figure 12·11. lYpicallnstruction Cycle Timing (One Byte Instruction)
M,

M,
T,

T,

T,

T,

T,

M,
T,

T,

T,

' T,

CLOCK
PO

X

P1

x::::!iL)

AS

X

As A15

s--<

\........J

An

A,

>

s---<

I

Aa A15

Ao A7

)

G:9-

\

r

\........J

\........J
\

os
RIW

As A15

\

I

I
---1---- FETCH 2ND BYTE---+-FETCH 1ST BYTE OF NEXT INSTRUCTION

\---FETCH 1ST BYTE ;...'

Figure 12·12. Typical Instruction Cycle Timing (Two Byte Instruction)

633

External Interface
M,

~

______

~~

______

M,

~~

____

-J~

____

~~~

__

~~

________

~~

_________

\..

\.....J
''-------~I

''---------'1

''''''______--'1

1

RIW ______- J

I-'--FETCH 1ST BYTE - - - - I - - - - - F E T C H 2ND B Y T E - - - i - - - - - F E T C H 3AO BYTE - - - - - - I

Figure 12"-13. 1Yplcallnstructlon Cycle Timing (Three Byte Instruction)
M,

M,

~

______

~~

______

~~

____

--'~

''-------~I

______

~~

____

-J~

''''''______--11

______

~~

____

--J~

''-~_--'I

______

~~

______

''-__~I

1

RlW ____- - - J

\ - F E T c f i 1ST BYTE - - - - I - - - F E T C H 2ND B y T E - - - ! - - - - FETCH SAD BYTE - - - i - o - - - F E T C H 4TH BYTE ~

Figufe'12-14. 1Yplcallnstruction Cycle Timing (Four Byte InStruction)

634

Glossary
addressing~:
The way in which the location of
an operand is specified. There are seven addressing modes: Register, Indirect Register, Indexed,
Direct Address,
Indirect
Address,
Relative
Address, and Immediate.
auto-echo~:
In this UART mode, the data
coming in on the Receive Data pin is reflected out
on the Transmit Data pin.
The receive section
still listens to the receive data input; however,
the data from the transmit section goes nowhere.

addresa: The address ·used, along with an
index and/or displacement value, to calculate the
effective address of an operand. The base address
is locsted in a general-purpose register, the
Program Counter, or the instruction.
~

The UART has its own on-chip
programmable baud-rate generator that consists of
two B-bi t Time Constant registers that hold the
time constant value, a 16-bit Timer/Counter that
counts down, and a flip-flop at the output
producing a square wave.
baud-rate generator:

bi-value.ode: A SuperB counter/timer operating
mode wherein the Time Constant and Capture
registers alternate in loading the counter.
byte: A data item containing B contiguous bits.
A byte is the basic data unit for addressing
memory and peripherals.

A "capture on external event" feature of
the SuperB that takes a snapshot 0 f the count.er
when a certain event occurs.

capture:

A memory address space that can hold
only dat.a to be read or written, not instruction
code; data memory is always external to the
SuperB.
data _Dry:

A 4-bit counter in each handshaking channel that is used to count processor
clocks between the time that valid data is available at the port and the handshake signal indicates that data is available.

Deskew Coooter:

(OA) addressing 1IIOde:
In this
mode, the effective address is contained in the
instruction.

Direct Addresa

An on-chip channel
that provides high-speed transfers of dsta directly between memory and peripheral devices.

Direct .....ry Acceaa (OMA):

A condition or event that alters the
usual flow of instruction processing. The SuperB
CPU supports two types of exception: reset and
interrupts.
exception:

extended bUB ti.ing: The SuperB has the capability of stretching the Data Strobe timing by 1, 2,
or 3 internal clock periods during external memory
accesses. The software can set up one timing for
program memory and a different timing for data
memory.

interrupt
Fast
fast
interrupt
processing:
processing completes the interrupt servicing in 6
clock periods instead of the usual 2.2.
flag regiater: This register is used to supply
the status of the SuperB CPU at any time.
Flag':
A dedicated register that saves the
contents of the Flag register when a fast interrupt occurs.

The 325 registers that
can' be used as accumulators, address pointers,
index registers, 'data registers, or stack registers.
general-purpoae registers:

handshaking channels: The SuperB has two identical handshaking channels ,which operate in two
modes--"fully interlocked" or two-wire mode, 'and
"strobed" or single-wire mode.
Im.ediate (1M) addressing.ode: In this mode, the
operand is contained in the instruction.
Indexed (X) addressing~: In this mode, the
contents of an index register are added to the
contents of a specified working register or working register pair, which holds the index value
desired.
Indirect Address CIA) addressing.ode: In this
mode, the instruction specifies a pair of memory
locations and this se lected pair, in turn, contains the actusl address of the instruction to be
executed.

635

Glossary
Indirect Register (IR) addr_ing.ooe: In this
'mode, the contents of the specified register or
register pair is the address of the operand.

Register (R) addressing mode: In this mode, the
operand value is the contents of the specified
register or register pair.

Instruction Pointer: A 16-bit register that acts
as Program Counter for a threaded-code language,
such as Forth, or can be used in the fast interrupt processing mode for special interrupt
handling.

register file: One of the three types of address
spaces supported by the SuperB CPU. Register file
address space is an internal register file composed of 325 B-bit wide registers that are logically
div ided into 32 working register groups of ,eight
registers each.

interrupt: An asynchronous ex~eption generated by
a peripheral device that needs attention.
The
interrupt structure of the SuperB contains 27 different interrupt sources, 16 vectors, and B
levels.
interrupt level: Interrupt levels provide the top
level of priority assignment and can be changed by
programming the Interrupt Priority register.
Interrupt Priority register (IPR): This register
assigns 192 different combinations of priority
when more than one interrupt level is pending.
interrupt source: An interrupt source is anything
that generates an interrupt, internal or external'
to the SuperB.
interrupt vector: The vector number is used to
generate the address of a particular interrupt
servicing routine.
locsl loopback.ode: In this mode, the data output from the transmit section of the UART is also
routed back to the receive section.
pipelining: Instruction pipelining is a computer
design technique in which the instruction fetch
and execution cycles are overlapped. Thus, during
the execution of the current instruction, the
opcode of the next instruction is fetched, resulting in high throughput.
Prograa Counter (pc): The 16-bit Program Counter
controls the sequence of instructions in the
currently executing program and is not an addressable register.

progr.. .aaory: A memory address space that can
hold code or data; program memory can be internal
or external to the SuperB.
read access: The type of memory access used by
the CPU for fetching data operands and instructions.

636

Register Pointer (RP):
The two register pointers
are system registers that contain the base address
of the two active working register groups of the
register file.
Relative Addr_ (RA) addressing.ada: In this
mode, the displacement in the instruction is added
to the contents of the Program Counter to obtain
the effective address.
reset: A CPU operating state or exception that
results when a reset request is signaled on the
~ line.
A reset initializes the Program
Status registers.
Slow "-n-y tilling: An optional feature of the
SuperB in which normal external memory timing is
slowed by a factor of two.
Stack Pointer (SP): A 16-bit register pair indicating the top (lowest address) of the processor
stack and used by the Call instruction and
interrupts to hold the return address.
systa. registers: System registers govern the
operation of the CPU and may be accessed using any
of the instructions that reference the register
file using the Direct addressing mode.
lkIiverssl
Asynchronous
Receiver/Tr..-itter
(UART): . A full duplex asynchronous channe 1 that
transmits and receives independently with 5 to B
bits per character, options for even or odd
par it y, and an opt ional wake-up feat~e.
wake-up feature:

A feature of the ,UART wherein
pattern match logic detects a pre-specified data
pattern at the receiver; the pattern can include
both the received character and a special wake-up
bit.
write access: The type of memory access used by
the CPU for storing data operands.

V..... Z"/m
luJlj
~Jt.'

PRELIMINARY INFORMATION

Product Specification

June 1987

Z8®Z8611 MeV
Military Electrical Specification
28603 Prototyping Device with 2K EPROM Interface

Features

microcomputer, 2K (8601) or 4K
• Complete
(8611) bytes of ROM, 128 bytes of RAM, 32
I/O lines, and up to 62K (8601) or 60K (8611)
bytes addressable external space each for
program and data memory.
register file, including 124 general• 144-byte
purpose registers, four I/O port registers,
and 16 status and control registers.
instruction execution time of 1.5
• Average
maximum of
priority interrupts for I/O,
• Vectored,
counter/timers, and UART.

/lB,

l/ls.

General
Description

The Z8 microcomputer introduces a new level
of sophistication to Single-chip architecture.
Compared loearlier single-chip microcomputers, the Z8 offers faster execution; more
efficient use of memory; more sophisticated
interrupt, input/output and bit-manipulation
capabilities; and easier system expansion.
Under program control, the Z8 can be tailored
to the needs of its user. It can be configured as a

PORT 2

PORTO

(NIBBLE
PROGRAMMABLE)

(BIT PRO·
GRAMMABLE)
110

1/0 OR AS-A!s

PORT 3

PORT f

(BYTE
PROGRAMMABLE)

SERIAL AND

PARALLEL 110
AND CONTROL

110 OR ADo-AD7

Figure 1. Pin Functions

UART and two programmable
• Full-duplex
8-bit counter/timers, each with a 6-bit
programmable prescaler.
Pointer so that short, fast instruc• Register
lions can access any of nine working register
groups in I /lS.

•
+ 5 V power supply-all pins TTL
• Single
compatible.
• 12.5 MHz.

On-chip oscillator which accepts crystal or
-external clock drive.

stand-alone microcomputer \\lith 4K bytes
of internal ROM, a traditional microprocessor
that manages up to 124K bytes of external
memory, or a parallel-processing element in a
system with other processors and peripheral
controllers linked by the Z-BUS@bus. In all
configurations, a large number of pins remain
available for I/O.

+Sy

P:Ie

XTAL2

P3,

XTAL1

P2,

P3,

P2e

P30

P2,

RElET

P2.

R/iN

P2.
P2,
P2,

OS
II!
P3,

P2"

GND

P3,

P3,

P3.

Po.

P1,

po,

P1.

Po,

P1,

po,
po,

P1.

PO,

P1,

po.

P1,

PO,

P1.

P1.

Figure 2a. 40-pin Dual-In-Line Package (DIP).
Pin Assignments

637

Pin
Description

AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory translers are valid at the trailing edge
of AS. Under program control. AS can be
placed in the high-impedance state along with
Ports 0 and I, Data Strobe and Read/Write.

DS. Data Strobe (output, active Low). Data
Strobe is activated once lor each external
memory transfer.
POo-PD,. PIa-PI7' P2o-Pz.,. P30-P3,. lIO Port
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports
that can be configured under program control
for I/O or external memory interface.
RESET. Reset (input, active Low). RESET initializes the 28. When RESET is deactivated,

638

program execution begins from internal
program location OOOCH.
ROMIess. (input, active LOW). This pin is only
available on the 44 pin versions of the 28611.
When connected to GND disables the
internal ROM and forces the part to function as a
28681 ROMless 28. When left unconnected or
pulled high to Vee the part will function
normally as a 28611.
R/W. Read/Write (output). R/W is Low when·
the 28 is writing to external program or data
memory.
XTALl. XTAL2. Crysta11, Crystal 2 (time-base
input and output). These pins connect a paralleL
resonant 12.5 MHz crystal or an external singlephase 12.5 MHz clock to the on-chip clock
oscillator and buffer.

Architecture

Z8 architecture is characterized by a flexible
I/O scheme, an efficient register and address
space structure and a number of ancillary
features that are helpful In many applications.
Microcomputer applications demand powerful I/O capabilities. The Z8 fulfills this with 32
pins dedicated to input.and output. These lines
are grouped into four ports of eight lines each
. and are configurable under software control to
provide timing, status Signals, serial or parallel
I/O with or without handshake, and an address!
data bus for interfacing external memory.
Because the multiplexed address/data bus is
merged with the I/O-oriented ports, the Z8 can
assume many different memory and I/O configurations. These configurations range from
a self-contained microcomputer to a microprocessor that can address 124K (Z8601) or 120K
(Z8611) bytes of external memory.

Three basic address spaces-are available to
support this wide range of configurations:
program memory (Internal and external), data
memory (external) and the register file (internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
four I/O port registers, and 16 control and
status registers •
. To unburden the prOgram from coping with
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware
support for the UART is minimized because one
of the on-chip timers supplies the bit rate.

OUTPUT

}
L.._~_-I

110
(BIT PROGRAMMABLEI

ADDRESS OR 110
(NIBBLE PROGRAMMABLEI

2048~BIT
ZB811
40lIl ... BIT

ADDRESSIDATA OR 110
(BYTE PROGRAMMABLE)

Figure S. F1IIICtIoDa1 Block DIagram

2037·003

639

Address
Spaces

Program Memory. The 16-bit program counter
addresses 64K bytes of program memory space.
Program memory can be located in two areps:
one internal and the other external (Figure 4).
The first 4096 (Z8611) bytes consist of on-chip
mask-programmed ROM. At addresses
4096 (Z8611) and great~r, the Z8 executes
external program memory fetches.
• The first 12 bytes of program memory are
reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond
to the six available interrupts.
Data Memory. The Z8 can address 60K (Z8611)
bytes of external data memory beginning at
location 4096 (Z8611) (Figure 5). External data
memory may be inchided with or separated

from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and
'
program memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-RI27) and 16
control and status registers (R240-R255). These
registers are assigned the address locations
shown in Figure 6.
Z8 instructions can access registers directly
or indirectly with an 8-bit address field. The Z8
also allows short 4-bit register addressing using
the Register Pointer (one of the control registers). In the 4-bit mode, the register file is

as53'
EXTERNAL

ZlI811

FlOM OR RAil

....409.

ON·CHIP
OOM

Location of
first byte of

instruction

;, t:----------~--

executed

,.

after reset

11

1004

8

IAQ4

Intenupt
Vector .... 8

IR03

Int8rTUpt

Vector

IRQ3

•
/,•

(Uppeo-Byte)

MEMORY

fRQS

•
,

(Lo_Byte)

EXTERNAL
DATA

lAOS

IA02

1----------1 :ZB811

IR02
IRQ1

2

IR01

•

1000

NOT ADDRESSABLE

1000

Figure', Program Memory Map
LOCATION
255

2S4
253

IDENTIFIERS
STACK POINTER (BITS 7-0)
~TACK

POINTER (BITS 15-8)
REGISTER POINTER

SPL
SPH

OP

252

PROGRAM CONTROL FLAGS

FLAGS

251
250
2<0
2<0

INTERRUPT MASK REGISTER

1M"

INTERRUPT REQUEST REGISTER

loa

INTERRUPT PRIORITY REOISTER

IP"

PORTS 0-1 MODE

P01M

24'

PORT 3 MODE

248

PORT 2 MODE

P'M
P2M

P"eo

248

TO PRESCALER

24.

TIMERICOUNTER 0

24'

T1 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

TMO

240

SERIAL UO

SIO

T.

PRE1

T1

NOT
IMPLEMENTED

12'

--(

PORT 3
PORT 2
PORT 1
PORTO

Figure 8. The Reglat.. File

P3
P2
Pl
PO

'7"'5'.

0000

...

,253
240

The upper nibble 01 the register file ac:tdrna

r--- the
provided by the regl8'er pointer specl''''
active wortdng·reglster group.

-------

rGENERAL·PURPOSE
REGISTERS

640

Figure 5. Data Memory Map

--

127

__
SPECIFIED WORKINQ.
REGISTER GROUP

-

nibble of
thentgister
file address
provldad by -

- the instruction

I.

r---,/o,ooTi----- ~

Figure 7. The Regillter Pomter

points to the
specified
regist....

Serial
Input/
Output

divided into nine working-register groups, each
occupying 16 continguous locations (Figure 6).
The Register Pointer addresses the starting
location of the active working-register group
(Figure 7).
Stacks. Either the internal register file or the
external data memory can be used for the stack.

A 16-bit Stack Pointer (R254 and R255) is used for
the external stack, which can reside anywhere in
data memory between location~ 2048 (8601) or
4096 (86ll) and 65535. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides
within the 124 general-purpose registers
(R4-RI27).

Port 3 lines P30 and P37can be programmed as
serial 110 lines for full-duplex serial asynchronous receiver/transmitter operation. The bit rate
is controlled by Counter/Timer 0, at 12 MHz.

selection. If parity is enabled, the eighth bit is
the odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight data
bits and at least one stop bit. If parity is on, bit 7
of the received data is replaced by a parity error
flag. Received characters generate the IRQ3
interrupt request.

The Z8 automatically adds a start bit and two
stop bits to transmitted data (Figure 8). Odd
parity is also available as an option. Eight data
bits are always transmitted, regardless of parity
TralUlmitted Data

Recel"ed Data

(No Parity)

(No Parity)
1~1~1~1~1~1~1~:~!~lsij

T

L

LSTART BIT
' - - - - - - E I G H T DATA BITS

Recel'l'ed Data

TralUlmitted Data

(With Parity)

(With Parity)

TI
L

.

sTARy BIT

L - - - - - E I G H T DATA BITS

' - - - - - - - - - - O N E STOP BIT

TWO STOP BITS

II

LSTART BIT

_ _ _ _ _ _ _ SEVEN DATA BITS

LSlART BIT
' - - - - - S E V E N DATA BITS

'---------~~~I';~=:~TR FLAG

000 PARITY

TWO STOP BITS

Figure 8. Serial Data Formats

Counter/
Timers

The Z8 contains two 8-bit programmable
counter/timers (To and TI), each driven by its
own 6-bit programmable prescaler. The TI
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number from
1 to 64. Each prescaler drives its counter, which
decrements the value (l to 256) that has been
loaded into the counter. When the counter
reaches the end of count, a timer interrupt
request-IRQ4 (to) or IRQs (TI)-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (single-

pass mode) or to automatically reload the initial
value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read any time without disturbing
their value or count mode.
The clock source for TI is user-definable and
can be -the internal microprocessor clock
divided by four, or an external signal input via
Port 3. The Timer Mode register configures the
external timer input as an external clock, a
trigger input that can be retriggerable or nonretrigg;'rable, or as a gate input for the internal
clock. The counter/timers can be programmably
cascaded by connecting the To output to the
input of T I. Port 3 line P36 also serves as a timer
output (TOUT) through which To, TI or the internal clock can be output.

/

641

1/0 Ports

The Z8 has 32 lines dedicated to input and
output. These lines are grouped into four ports of
eight lines each and are configurable as input,
output or address/data. Under software control,
the ports can be programmed to provide address

outputs, timing, status signals, serial I/O, and
parallel I/O with or without handshake. All ports
have active pull-ups and pull-downs compatible
with TTL loads.

Port 1 can be programmed as a byte I/O port
or as an address/data port for interfacing
external memory. When used as an I/O port, Port
1 may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY 1
and DAVj (Ready and Data Available).
Memory locations greater than 2048 (Z8601) or
4096 (Z8611) are referenced through Port 1. To
interface external memory, Port 1 must be
programmed for the multiplexed Address/Data
mode. If more than 256 external locations are
required, Port must output the additional
lines.
Port 1 can be placed in the high-impedance
state along with Port 0, AS, DS and RIW,

allowing the Z8 to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33 as a
Bus Acknowledge input and P34 as a Bus
Request output.

Portil can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port may be placed under handshake control. In this configuration, Port 3 lines P32 and
P35 are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the I/O direction of the upper nibble
P04-P07·
For external memory references, Port can
provide address bits As-All (lower nibble) or
As-Aj5 {lower and upper nibble) depending on
the required address space. If the address range
requires 12 bits or less, the upper nibble of Port
can be programmed independently as I/O while

the lower nibble is used for addressing. When
Port nibbles are defined as address bits, they
can be set to the highimpedance state along with
Port 1 and the control signals AS, DS and RIW.

.......

(UO OR ADo-AD,)

Z8611

Meu

°

°

Figure k. Port 1

°

I. . ,.·

(110 OR A.-A,s)

°

°

Port 2 bits can be programmed independently
as input or output. The port is always available
for I/O operations. In addition, Port 2 can be
configured to provideopen-drain outputs.
Like Ports and 1, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P3j and P36 are used as
the handshake controls lines DAV2 and RDY2.
The handshake signal assignment for Port 3 lines
P3j and P36 is. dictated by the direction (input or
output) assigned to bit 7 of Port 2.

°

Port :I lines can be configured as I/O or
control lines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37)' For serial I/O, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four external interrupt
request signals (IRQO-IRQ3); timer input and
outpuhignals (T~nd Tour) and Data
Memory Select (DM).

642

Figure 9b. Port 0

Z8611

PORT 2(1/0)

Meu

l 0Ai.i2

HANDSHAKE CONTROLS
AND RDYz
(P3, AND P3e)

Figure 9c:. Port 2

Z8611

PORTa

(110 OR CONTROL)

Meu

Figure 9d. Port 3

Interrupts

The 28 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In,- Serial Out, and the two counter/timers.
These interrupts are both maskable and
prioritized. The Interrupt Mask register globally
or individually enables or disables the six interrupt requests. When more than one interrupt is
pending, priorities are resolved by a programmable priority encoder that is controlled by
the Interrupt Priority register.
All 28 interrupts are vectored. When an interrupt request is granted, an interrupt machine

cycle is entered. This disables all subsequent
interrupts, saves the Program Counter and status
flags, and branches to the program memory
vector location reserved for that interrupt. This
memory location and the next byte contain the
16-bit address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the
interrupt inputs can be masked and the Interrupt
Request register polled to determine which of the
interrupt requests needs service.

Clock

The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALI = Input, XTAL2 = Output).
The crystal source is connected across XTALI
and XTAL2, using the recommended capaCitors

(Cl:S 15pF) from each pin to ground. The
specifications for the crystal are as follows:
• AT cut, parallel resonant
• Fundamental type, 12.5 MHz maximum
• Series resistance, Rs :S 100 n

643

Instruction

Set
Notation

Addressing Modes. The following notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X

.DA
RA
1M
R

IR
I.
RR

Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register

address
Indirect working-register address only
Register pair or worki'ng register pair address

Symbols. The folloWing symbols are used in
describing the instruction set.
dst
src

SP

Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)

PC

Program counter

cc
@

FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)
IMR
Interrupt mask register (control register 251)

644

Assignment of a value is indicated by the symbol
"_". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the folloWing
six flags:

c
z
S
V
D
H

Carry flag
Zero flag
Sign flag
Overflow flag
DeCimal-adjust flag
Half-carry flag

Affected flags are indicated by:

o
*
X

Cleared t'o zero
Set t6 one
Set or cleared according to operation
Unaffected
Undefined

Condition
Codes

Value

M...moDic

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

Flags Set
Always true
Carry
No carry
Zero
Not zero'
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal

C
NC
Z

NZ

PL

MI
OV
NOV
-EQ

NE
GE

LT
GT

LE
UGE

ULT
UGT

ULE

ope
dot

ope

ope

OR

It

1 1

01 dSt/SfC I

lOR b 1 101

dot

C

C = I
(C = 0 AND Z = 0)
= I

(C OR Z)

CCF, 01, EI,IRET, NOP,
RCF, RET, SCF

ope

eLA, CPl, DA. DEC,
DEeW. INC, tNCW, POP,
PUSH, AL, ALe, RR,
RAC, SFlA, SWAP

INCr

OPC

".

MODE

OR
OR

dot

ope

ope

dsUsrc

.relda'

dlt1Src

ope

Ireld.'

I ope

LD, LOE, LOEI,
lOC, LOCI

LO, OR, sac, SUI,
reM, TM, XOR

ADC, ADD, AND, CP,
OR 11 1 101

dot

OR
OR

dot

ope

dot

LO, OR, SIC. SUB.
TeM, TM. XOR

L.
1 1 10

1 1 10

dsUCCR~ ope

MODE
dstlsrc

ope

L.

ADDRESS

OA

It

1 1

01

L.

ope

JP

OA,
OA,
LO

VALUE

I

ADC, ADD, AND, CPo

d.

reM, TM, XOR

MODE

dot

".

MODE

MODE

ADC, ADD, AND,
CPt OR, SBC, SUB,

dot

1 1 10

VALUE

.RP

MODE

1 1 1 0

JP, CALL (Indirect)

dot

d.,
OPC
VALUE

ope

=

=0

Never true

Instruction
Formats

MODE
detllre

= I
=0
= I
=0
=0
=I
=I
=0
= I
= 0
XOR V) = 0
XOR V) = I
[Z OR (5 XOR V)) = 0
[Z OR (5 XOR V)]
I

C
C
Z
Z
5
5
V
V
Z
Z
(5
(5

ope
DJNZ,JA

CALL

OA,
OA,

Tw....Byte _ _

'l'brM-Byte _ _

Figure 12. Instruction Formats

645

-

Iutnu:tloD
cmd Operatloa

Addr~

ADO dat,src
dat-dat+ arc +C

IDlltrucUon
SUQUDary

Opc:ode Flallll MectecI
(~.
ex)

CZSVDH

(Nole I)

ID

*·*~O*

ADD dat,arc
dil - dat + s>:o

(N",- I)

00

•• * • 0 ..

MD dat,src
dsl .- dsl AND arc

(~ote

50

• 0 - -

cbil

I)

------

CALL'dat
DA
SP-SP-2
IRR
@SP - PC; PC - dat

~

CCF

EF

*-----

C - NOTC

ctR dot

R

dsl - 0

IR

SO
Bl

------

COMdat
dat - NOT dat

R
IR

60

• 0 - -

61

CP dat,arc
dsl - arc

(Nole 1)

DA dat
dat - OA dat

R
IR

41

DEC dat
dal-dsl-I

R
IR

00
01

DECW dat
dat-dal-l

'IlR
IR

80
81

40

8F

DJNZ .,dsl
RA
r -. - 1
1fT ¢ 0
PC-PC+dat
Range: + 127, -128

.A
.=O-F

POPdat
dal- @SP
SP-SP+l

R
IR

50
51

------

PUSH erc
SP-SP-l; @SP-src

IR

.E
• =O-F

-***--

BF

-.*.-******

------

cc,dat
If cc Is true
PC - det

DA

cD
c=O-F

IRR

30

JR cc,dsl

RA

cB
c=O-F,

------

rC
r8
19
r=O-F
C7
07
E3
F3
E4
E5
E6

------

1m
R

R

•
•
If
R
R
R
IR
,IR

X
r
Ir
r
R
IR
1m
1m
R

i

Irr

C2
02

Ifr

C3
D3

X

In

LOCI dat,src
If
Irr
dat - arc
• - . + 1; rr - rr + 1

R
IR

70
71

------

RCF
C-O

CF

0-----

RET
PC-@SP; SP-SP + 2

AF

------

RR dat

PC-PC + dst
Range: t 127, -!28

646

-*·0--

-*.*--

------

FLAGS - @SP; SP - SP + I
PC-@SP; SP-SP+2; IMR(7)-1

dal - ere

------

40

RLC

9F

AO
Al

!RET

toe, del,arc

FF

... --

21

RR

•

83
93

-----------

(Note I)

-

20

R
IR

LD dat,arc
dst-src

Irr
I.

NOP

~~
dat Lm-E:::!J.l
R
c
,
•
IR

90

1;mLc:!J-l~
dat cm:::E:]J
R
c
,
•
IR

EO
El

SIC dat,erc
4sl- det-src-C

91
10
11

...

CO
CI

(Note 1)

SCF
SRA dat

DlC dsl
dat-dat+l

if cc Is lrue,

82
92

OR dat,arc
dat - datORarc

RL dat

------

I••

• 1

3D

•

OF

1 - - - - -

DO
01

.... ·0 - -

31

------

C-l

EI
IMR(7) - I

po

•

.. • .. X - -

------

-

AddrMoU 0pc04e Flallll~
cbIt
,(r.)
CZSVDB

LDE dat,arc
Irr
dsl - src
LDEI dat,arc
I.
Irr
dat - src
.-.+I;rr-rr+l

RRC

DI
IMR (7) - 0

!MCW dat
det-dsl+l

AD

Iastructlooa

aad Operatloa

If

Lm~~

,

1m

SRP src
RP - ere
SUI dst,src
dot - dsl- src

(Note 1)

SWAPdat~ R
,
IR

•• 1

20
FO
FI

X

* .. X - -

TCM dat,arc
(NOT datI AND arc

(Note 1)

60

-**0--

TN dsl,arc
del AND arc

(Note 1)

70

-**0--

ZOR del,arc
dat - dat XOR src

(Note I)

BO

-**0--

Note I
These instructlons have an identical set of addressinq
modes, which are encoded for brevity. The firs! opcode
nibble is found in the instruction tel table above. The
second nibble is expressed symbolically by a 0 In this
teble, and ita value is found in the follOWing table to the

right of the applicable addresaing mode pair.
For example, to determine the opcode of a ADC
Instruction use the addressing modea r (aestinatlon) and
Ir (source). The result Is 13.

Adclr Mode

cbIt

IIl'C

E7

Low_
0pc0cIe Nlbbl.

tal

F5

-----------

.

R
R

Ii
IR,

Ir
R
IR
1M
1M

[!)

!II

rn

00III

Registen

R244 TO
Cowater/Tlmer 0 Reglater
(F4}{; Read/Write)

R240 SIO
Ser1a11/0 Reglater
(F~;

Read/Write)

'----:J~:~~
=~~~.:~:~:-r.:~
T.CURAENTVAlUE(WHEN RDDt

' - - - - SERIAL DATA lDo • LSI)

NOT T"",MDDES
USED. 00
TO OUT'" 01
T,OUT -10
INTERNAL CLOCK OUT • 11
T MODES

8241 TMR

R245 PREO

Tl_ Mode Reglater

PrHc:aler 0 Reglater

(FIH; Read/Write)

(F5}{; Write Only)

j

llli~.'

~

1
0
1
0

•
•
...
..

I~D'I"ID'ID'ID'ID'ID~'

I Dl'l COUNTIIDDE

LOADT
o
NO
FUNCT'ON
DISAILE T COUNT

o • To SINGLE·PASS
1 ... To MODULo-N

0

ENABLE To COUNT

RESERVED

GATE INPUT. 01

NO FUNCTION
1 ... LOAD T,
0 .. DISABLE T, COUNT

10

1 .. ENABLE T1 COUNT

(RANGE: 1-84 DECIMAL
01·00 HEX)

EXTERNAL CLOCK IN~DT .. 00

(NON'A~~~:i:~=:~~ •

"'EseALER MODULO

TRIGGER INPUT ... 11
(AETAIGQEAA8LE)

HI. PaM

R242 Tl
Cowater Timer 1 Reglater
(F~; Read/Wrlte)

Port 2 Mode Reglilter
(F~;

R243 PREl

Hl47P3M
Pan 3 Mode Reglater
(F7H; Write Only)

Presc:aler 1 Reglater
(F~; Write Only)

~L
,

Write Only)

CDUNTMDDE
o ... T, SINGLE.PASS
1 ... T, MODULO.N

CLOCK SOUIIIICE

1 '" T,INTERNAL

o = !J EXTERNAL TIMING INPUT
(T.,.)MODE

[SE

LDPORT.PULL.UPSciP.N.....iN
1 PORT 2 PULL·UPS ACTIVE

pas = OUTPUT
PIS

= aIV&RDYo

00 P33:: INPUT

~~} P33

PRESCALE" MODULO

(RANGE: '~14 DECIMAL
01~OO

RESERVED
= INPUT

1 P32

o P32

'" INPUT

= RDYcwaAVt

P34 :: OUTPUT
PM = mil
= ROV1'aAVt

::':l.. ... :::

11 P33 = tiX'RIRDY1 P34

HEX)

~ =~

~fo~

'---------~=:

:: : ~~~:,utsWr)
~~~TOUT

L -_ _ _ _ _ _ _ _ ~;~~g~

Figure 13. Control Registers

647

Registers

R252 FLAGS
Flag Reglst_
(FCH ; Read/Write)

R248 POIM
Port 0 and I Mode Regllt_
(F8H; Write Only)

(Continued)

E-r

10,10.10, I0.1 0,1 0,1 0, i'D, I
po,_po, =MODE:]
OUTPUT
00
INPUT .. 01
A'2·A15 '" 1X

L

EXTERNAL MEMORY TIMING

.

~~~
I

PO,-PO,
MODE
00 .. OUTPUT
STACI( SELECTION

0 = EXTERNAL
1 '" INTERNAL

NORMAL .. 0
EXTENDED a 1

LUSERFLAG·"

LUSER FLAG F2

01 = INPUT
1X .. "a-A1I

HALF CARRY FLAG
DEcrMAL ADJUST FLAG
OVERFLOW FLAG

SIGN FLAG

:y~~EOUTPUT
8O'1=1BYTE
INPUT

P1
01

ZERO FLAG

CARRY FLAG

10'" ADo-AD,
11 "" HIGH·IMPEDANCE ADo-ADT.

AS, OS, RIW, Ae-Au. A12-A15
IF SELECTED

R253 RP
Register Polnt_
(F~; Read/Write)

R2491PR
Interrupt Priority Regllter
(F%; Write Only)

107 105

i Os

i 04 i 0 3 ]02 1..0,

iDol

.••.•:] I I III"~'-"'RESERVED '" 000
C > A :> 8 = 001

tRQ3, IRQS PRIORITY (GROUP AI

o '"

IRQS :> IRQ3

= 010
A:> C > B = 011
B:> C :> A = 100
C :> B :> A = 101
A :> B :> C

.

1 '" IR03 :> IRQS

IRaO, IRQ2 PRIORITY (GROUP B)
o '" IRQ2 :> IROO
1 '" IROO ::> IRQ2

LOON'TeARE
REGISTER
POINTER

B:> A :> C '" 110
RESERVED"" 111

IRQ1, IRQ4 PRIORITY (GROUP C)
o "" IRQ1 ::> IRQ4
1 "" IRQ4 > IR01

R254 SPH
Stack Pointer
(FEH; Read/Write)

R250 IRQ
Interrupt Request Register
(FAH; Read/Write)

10,10,10, io.lo,ID,1 0, !0,1
RESERVED

T

L::

IRoo = P32 INPUT (00 a: IROO)
IRQ1 "" P33 INPUT
IRQ2 "" P31 INPUT
lA03 = P30 INPUT, SERIAL INPUT
IR04 = To, SERIAL OUTPUT
IROS • T1

R255 SPL
Stack Pointer
(FFH; ReadiWrite)

R251 IMR
Interrupt Mask Register
(FBH; Read/Write)

Il____

L::
___ '

ENABLES IROO-IRQS
(Do'" IRoo)
RESERVED

' -_ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

Figure 13. Control Registers (Continued)

648

Opcode

Low.. Nibble (Hex)

Map

o
o

6,5

6,5

2

3

6,5

6,5

10,5

8

7

8

9

10,5

10,5

10,5

6,5

6,5

12/10,5 12/10,0

6,5

LD

LD

OJNZ

JR

LD

JP

INC

r1,Rz

la,R1

1l,RA

cc,RA

f1,IM

cc,DA

II

DEC DEC ADD ADD ADD ADD ADD ADD
fa

112
6,5

Rz,R]

IR.,HI

HI,IM

IRI,IM

10,5

10,5

10,5

10,5

f], f2

1],lt2

Rz,R.

IR.,HI

HI, 1M

IRI,IM

6,5

6,5

10,5

10,5

10,5

10,5

INC

SUI

SUI

SUI

SUB

SUI

SUI

HI
8,0

IRI
6, I

tl. f2

fl, Ira

H.,HI

IR.,HI

HI,IM

IRI,IM

6,5

6,5

10,5

10,5

10,5

10,5

JP

SRP

SIC

SIC

SIC

SIC

SIC

SIC

IRHI

1M

t1, rJ

11,Ir2

H.,HI

IR.,HI

HI,IM

IRI,IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

OJ!.

OJ!.

OR

OR

OR

OR

OR

OR

HI
10,5

IRI
10,5

tl,12

11,Irz

H.,HI

IR., HI

HI,IM

IRI,IM

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

HI
6,5

IRI
6,5

AND
n,la

1],lu

H.,HI

IR.,HI

HI,IM

IRI,IM

6,5

6,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TeM

TCM

HI
IRI
10112, I 12/14, I

n, fa

reM

10,5

11,IrZ

H.,HI

IR.,HI

HI,IM

IRI,IM

6,5

6,5

10,5

10,5

10,5

10,5

PUSH PUSH

TN

TN

TN

TN

TN

TN

fa
12,0

fl,Irz

H.,HI

IRz,R]

HI, 1M

IRI,IM

OECW OECW LDE

LDEI

HI

IRI

6,5

6,5

6,5

HI
6,5

IRI
6,5

INC

tl,

fl.

J!.

5

B

C

D
12110,0

6,5 ,

mc RLC ADC ADC ADC ADC ADC ADC
2

3

,
5

'iC

8

~

•
~
II:

7

!

8

H.
10,5

9

J!.

HHI

IRI

6,5

6,5

RL

RL

HI

IRI

10,5

10,5

C
0

E
F

LDE

6, I

-

LDEI

DI
6, I

EI

6,5

10,5

10,5

10,5

10,5

r-RET

14,0

CP

CP

CP

IR.,HI

HI,IM

IRI,IM

6,5

10,5

10,5

10,5

10,5

r---

XOR

XOR

XOR

XOR

XOR

H.,HI

IR.,HI

H.I,IM

IRI,IM

!BET

HI

IRI

IRI

'----

18,0

CP

XOR

HI

-

H.,HI

6,5

6,5

-

CP

CLR
MC

-

1),lr2

6,5

6,5

r---

CP

CLR

IRI

MC

e---

lIn Ira, lUI

6,5

;--

-

II/Ina Ir1,IrU
12,0
18,0

n,12
6,5

11,Irz
12,0
18,0
LDC LDCI
t.,lrra Ill. lIn
12,0
18,0
LDC LDCI
la. un Irz,. I l l ]
6,5
ll.U

6,5

20,0

20,0

10,5

CALL·

CALL

LD

HI

IRI

IRRI

DA

la, x, HI

6,5

6,5

10,5

M

M

LD

LD

10,5

10,5

10,5

LD

LD

LD

HI

IRI

rt,lrz

Bz,Rl

IR.,HI

HI,IM

IRI,IM

8,5

8,5

6,5

10,5

LD

LD

I'l. fa

H.,IRI

6,5

RCF

-

tl, Z, R2

SRA

IRI

-

LD

6,5

SWAP SWAP

16,0

10,5

SRA

HI

Byt.. per
lnstructloa

11,

INCW INCW
RHI

B

IR.
10,5

F

E

-

6,5

SCF
6,5

CCF
6,0

NOP

~~------~~'-------'; ~~------~~'-------'~ ,'---------~~,----------,; ~
3

2

2

3

. Low..
Opcocle
Nibble
Executioa

Upper

•

PlpeliDe

CYCI"~0~5Cycl..

Opcocle _
Nibble

J!.

CP

MDeIllODlc

Legead.
H

= 8-BII Address

r = 4-BII Addre..
HI or" = Os! Ad_
H. or rz = Src Addreu

H., HI

Sequeac:e.
Firat
Operanc\

S-d
Operanc\

Opcode, First Ope....nd, Second Operand
Note. The blank areas are not defined.

*2·byte instruction; fetch cycle appears as a 3·byte instruction

649

Absolute
Maximum
Ratings

Standard
Test
Conditions

Voltages on all pins
with respect to GND .......... -O.3Vto +7.0V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ '-65°C to + 150°C

Stresses greater than those listed under Absolute Maxi·
mum Ratings may ca.use permanent damage to the device.

This is d stress rating only; operation of the device at any
condition above those indicated. in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may a.ffect

device reliability.

The DC characteristics listed below apply for
the following standard test conditions, unless '
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin.
Standard conditions are:

o
o
o

+5V
2.1K

+4.75 V S Vee S +5.25 V
GND = 0 V
O°C S TA S +70°C
Figure 14. Test Load I

DC
Characteristics

650

Parameter

Min

Max

UDl!

VeH

Clock Input High Voltage

3.8

Vee

V

Driven by External Clock Generator

VeL

Cl09k Input Low Voltage

-0.3

0.8

V

Driven by External Clock Gene'rator

VIH

Input High Voltage

2.0

Vee

V

VIL

Input Low Voltage

-0.3

0.8

V

VRH

V

Symbol

Reset Input High Voltage

3.8

Vee

VRL

Rese! Input Low Voltage

-0.3

0.8

VOH

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

IoL

Output Leakage

IlR
Ice

2.4

ConditlOD

V

= -250,.A ,

V

IoH

0.4

V

IoL = +2.0 rnA

-10

10

I'A

0 V05. VIN 05. +5.25 V

-10

10

I'A

0 V05. VIN 05. +5.25 V

Reset Input Current

-50

I'A

Vee

Vee Supply Current

150

rnA

= +5,25 V, VRL = 0 V

AC Characteristics
External 1/0
or Memory

Read and
Write Timing

00-0, OUT

Figure IS. Exteraal 1/0 or Memory Read/Write

No.

Symbol

Parameter

TdA(AS)

MI~

Address Valid to AS t Delay

35

2
3

TdAS(A)

AS t to Address Float Delay

45

TdAS(DR)

4

TwAS

1m t to Read Data Required Valid
1m Low Width

TdAz(DS)
5
6-TwDSR
7

Max

Notes*to
2,3

220

1,2,3

55

Address Float to i5S ~

2,3
1,2,3

0

i5S (Read) Low Width
i5S (Write) Low Width

185 - - - - - - - 1 , 2 , 3

8

TwDSW
TdDSR(DR)

9

ThDR(DS)

to
11

TdDS(A)

DS t to Address Active Delay

45

TdDS(AS)

i5S t to 1m ~ Delay

55

1,2,3

110

DS ~ to Read Data Required Valid

130

Read Data to DS t Hold Time

1,2,3

0
2,3

2.3
30 - - - - - - - 2 , 3

12 - TdRlW(AS) - - RiW Valid to 1m t Delay
13

TdDS(RIW)

i5S t to RiW Not Valid

14

TdDW(DSW)

Write Data Valid to DS (Write)

15

TdDS(DW)

i5S t to Write Data Not Valid Delay

16

TdA(DR)

Address Valid to Read Data Required Valid

17

TdAS(DS)

1m t to DS ~ Delay

~

Delay

35

2,3

35

2,3

45
255
55

2,3
1,2,3
2,3

NOTES:
1. When using extended memory timing add 2 T pC.

t Test Load 1.

2. Timing numbers given are for minimum TpC.

o All timing references use 2.0 V for d logic "I" and 0.8 V for a logic "0",
• All units innanoaeconds (ns).

3. See clock cycle time dependent cha.racteristics t~ble.

651

AC Characteristics
Additional
Timing
Table

CLOCK

TON

IRQ..

Figure 16. Additional Timing

No.

Symbol

Parameter

1

TpC

Input Clock Period

2

TrC,TIC

Clock Input Rise And Fall Times

3

TwC

Min

Max

80

1000

Not..*

15

Input Clock Width

4
5-

26
1
TwTinL
Time Input Low Width
70
2
TwTinH - - , - Timer Input High Width - - - - - - - - - - - - - - - - 3TpC - - - - - - - - - 2

6

TpTin

Timer Input Period

7

TrTin" TITin

Timer Input Rise And Fall Times

8TpC

2

100

2
2,3

8a

TwIL

8b

TwIL

Interrupt Request Input Low Time
Interrupt Request Input Low Time

70
3TpC

2,4

9

1'wIH

Interrupt Request Input High Time

3TpC

2,3

NOTES:
1. Clock timing references uses 3.8 V fora logic "1" emd 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "}" and O.S V for

3, Interrupt request via Port 3 (P31-P33)'
. 4. Interrupt request via Port 3 (P30)'
* Units in nanoseconds (ns).

a logic "0" . '

Memory Port
Timing

_~:~·:~DON~: ~-'T:~CAJIl=:~=<_0~o~;-~ : :~=_-~:X:,-A-DO-"ES - VA-U-D- -D-A-TA-O-N-VA-L-OD- -~ts=

: : ___

Figure 17. Me;"ory Port Timing

No.

2

Symbol

Parameter

TdA(DI)

Address Valid to Data Input Delay'

ThDI(A)

Data In Hold time

NOTES:
L Test Load 2.
2. This is a Clock-Cycle· Dependent parameter. For clock frequencies
other than the maximum, use the following formula: 5 TpC - 95

652

Min

Max

Not..*

320

1,2

o
·Units are nanoseconds unless otherwise specified.

Handshake
Timing

..;:: ----------_~_'_--,~~---------~
'OUTPUll

Flgurel8a.lDputH~

~'

DATADUT

DATA OUT VALID

s=

------.-~----------------------------------iiAV

jOUTPUTj

RDY

)
---------------J::==3jE==:£i=~
0
~

CI;-

jlNPUn

Figure lib. Outputllcmd8hake

No.

Symbol

MID

Parameter

Max

Not....

1
TsDI(DAV)
Data In Setup Time
o
2
ThDI(DAV)
Data In Hold time
160
3
TwDAV
Data Available Width
120
4
TdDAVIf(RDY)
i5l\V ~ Input to RDY ~ Delay
120
1,2
S--TdDAVOf(R'DY)--i5l\V ~ Output to RDY ~ D e l a y - - - - - - - - - - - - 0 - - - - - - - - 1 , 3
6
TdDAVIr(RDY)
T5AV t Input to RDy'f Delay
120
1,2
7
TdDAVOr(RDY)
i5AV t Output to RDY t Delay
0
1,3
8
TdDO(DAV)
Data Out to DAV ~ Delay
30
9
TdRDY(DAV)
Rdy ~ Input to r5AV t Delay'
0
140
NOTES:
J. Test load 1
2. Input handshake
3. Output handshake
t All timing references use 2.0 V for a logic "I Hand O.S V for
.loqic·O",

*

Units in nanoseconds (ns).

ClockEquation
, Cycle-Time- Number Symbol
Dependent
TdA(AS)
1
TpC-SO
Characteristics
TdAS(A)
2
TpC-4O
TdAS(DR)
3
4TpC-110*
4
TwAS
TpC-30
S--TwDSR-------------3TpC-6S*-----------7
TwDSW
2TpC-SS*
8
TdDSR(DR)
3TpC-120*
10
Td(DS)A
TpC-4O
11
TdDS(AS)
TpC-30
12-TdRIW(AS) - - - - - - - - - - - - T p C - S S - - - - - - - - - : . - - 13
TdDS(RIW)
TpC-50
14
TdDW(DSW)
TpC-50
TdDS(DW)
IS
TpC-4O
TdA(DR)
16
STpC-I60*
TdAS(DS)
17
TpC-30
• Add 2TpC when using extended memory timing.

653

MIL·STD·883 MILITARY PROCESSED PRODUCT
•

Mil-Std-883 establishes uniform methods and procedures for testing microelectronic devices to insure the
electrical, mechanical, and environmental integrity and
reliability that is require~ for military applications.

•

Mil-Std-883 Class 8 is. the industry standard product
assurance level for military ground and aircrafl
applicati,on.

• The total reliability of a system depends upon tests that
are designed to stress specific quality and reliability
concerns that affect microelectronic products.
• The following tables detail the i 00% screening and electrical tests, sample. electrical tests, and Qualificationl
Quality Conformance testing required.

Zllog Military Product Flow
ENVIRONMENTAL SCREENING
• STABILIZATION BAKE
• TEMPERATURE CYCLE
• CENTRIFUGE·

654

Table I
MIL·STD·883 Class B Screening Requirements
Method 5004

Test

MiI·Std·883
Method

Test Condition

Requirement

Internal Visual

2010

Condition B

1000Al

Stabilization Bake

1008

Condition C

1000Al

Temperature Cycle

1010

Condition C

100%

Constant Acceleration (Centrifuge)

2001

Condition E or D(Note 1), Y1 Axis Only

100%

,Zilog Military Electrical Specification
Static/DC Tc = + 25°C

100%

Initial Electrical Tests

Condition D(Note2), 160 hours,
TA = + 125°C

1000Al

Interim Electrical Tests

Zilog Military Electrical Specification
Static/DC Tc = + 25°C

100%

PDA Calculation

PDA = 5%

100%

Final Electrical Tests

Zilog Military Electrical Specification
Static/DC Tc = + 125°C, - 55°C
Functional, Switching/AC Tc = + 25°C

100%

Burn-In

1015

Fine Leak
Gross Leak

1014
1014

Condition A2
ConditionC

1000Al
1000Al

Quality Conformance Inspection (QCI)
Group A
Each Inspection Lot
Group B
Every Week
Group C
Periodically (Note 3)
Group D
Periodically (Note 3)

5005
5005.
5005
'5005

(See Table II)
(See Table III)
(See Table IV)
(See Table V)

Sample
Sample
Sample
Sample

External Visual

2009

QA-Ship

1000Al
100%

NOTES;
1. Applies to larger packages which have an inner seal or cavity perimeter of two inches or more in total length or have a package
mass of ..5 grams.
2. In process of fully implementing of Cond~ion D Burn-In Circu~. Contact factory for copy of specific burn-in circu~ available.
3. Performed periodically as required by Mil-Std-883, paragraph 1.2.1 b(17).

'655

Table" Group A
Sample Electrical Tests
MIL-STD-883 Method 5005

Subgroup

Tests

Temperature (Tc)

LTPD
Max Accept =; 2

Subgroup 1

Static/DC

+25°C

2

Subgroup 2

StaticlDC

+ 125°C

3

Subgroup 3

Static/DC

-55°C

5

Subgroup 7

Functional

+25°C

2

Subgroup 8

Functional

-55°C and + 125°C

5

Subgroup 9

Switching/AC

+25°C

2

Subgroup 10

Switching/AC

+ 125°C

3

Subgroup 11

Switching/AC

-55°C

5

NOTES:
• The specific parameters to be included for tests in each subgroup shall be as specified in the applicable detail electrical specification. Where no
parameters have been identified in a particular subgroup or test within a subgroup, no Group A testing is required for that subgroup or test.
• A single sample may be used for all subgroup testing. Where required size exceeds the lot size, 100% inspection shall be allowed.
• Group A testing by subgroup or within subgroups may be performed in any sequence unless otherwise specified.

656

Table III Group B
Sample Test Performed Every Week to
Test Construction and Insure Integrity of Assembly Process.
MIL-STD-SS3 Method 5005
Subgroup

MII-Std-SS3
Method

'ntst Condition

Quantity or
LTPD/Max Accept

S'i..bgroup1
Physical Dimensions

2016

2/0

Subgroup 2
Resistance to Solvents

2015

4/0

Subgroup 3
Solderability

2003

Subgroup 4
Internal Visual and Mechanical

2014

SubgroupS
Bond Strength

2011

C

15(Note2)

Subgroup 6(Note3)
Internal Water Vapor Content

1018

1000 ppm.
maximum at + 100°C

3/0 or 5/1

Subgroup 7(Note 4)
Seal
7a) Fine Leak
7b) Gross Leak
Subgroup S(Note 5)
Electrostatic Discharge Sensitivity

Solder Temperature
+245°C ± 5°C

15(Note 1)

1/0

5

101.4
7a) A2
7b) C
3015

Zilog Military Electrical
Specification
Static/DC Tc = + 25°C
A = 20-2000V
B = >2000V
Zilog Military Electrical
Specification
Static/DC Tc = +25°C

15/0

NarES:
1. Number of leads inspected selected from a minimum of 3 devices.
2. Number of bond pullaselected from a minimum of 4 devices.
3. Test applicable only If the package contains a dessicant.
4. Test not required if etther 100% or sampl.e seal test is performed between final electrical tests and external visual during Class B screening.
S. Test required for initial qualification and product redesign.

657

Table IV Group C
Sample Test Performed Periodically to Verify Integrity of the Die.
MIL-S'rD-883 Method 5005

Subgroup

Mil-Std-883
Method

Quantity or
LTPD/Max Accept

Test Condition

Subgroup 1
Steady State Operating Life

1005

End Point Electrical Tests

Condition o(Note 1), 1000 hours at
+125°C

5

Zilog Military Electrical Specification
Tc = +25°C, + 125°C, -55°C'

Subgroup 2
Temperature Cycle

1010

Condition C

Constant Acceleration (Centrifuge)

2001

Condition E or

Seal
2a) Fine Leak
2b) Gross Leak .

1014

Visual Examination

10100r1011

End Point Electrical Tests

o(Note 2),

Y1 Axis Only
15

'2a) Condition A2
2b) Condition C

Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C

NOTE:
1. In process of fully implementing Condition D Burn-In Circuits. Contact factory for copy of specific burn-in circuit available.
2. Applies to larger packages which have an Inner seal or cavity perimeter of two inches or more in total length or have a package
.
mass of ;'5 grams.

658

Table V Group 0
Sample Test Performed Periodically to Insure Integrity of the Package.
MIL-STD-883 Method 5005
Subgroup

Mil-Std-883
Method

Test Condition

Subgroup 1
Physical Dimensions

2016

Subgroup 2
Lead tntegrity

2004

Condition 82 or D(Note 1)

Subgroup 3
Thermal Shock

1011

Condition 8 minimum,
15 cycles minimum

Temperature Cycling

1010

Condition C, 100 cycles minimum

Moisture Resistance

1004

Seal
3a) Fine Leak
3b) Gross Leak

1014

Visual Examination

Quantity or
LTPD/Max Accept
15
15

15

3a) Condition A2
3b) Condition C
1004 or 1010

End Point Electrical Tests

Zilog Military Electrical Specification
Tc = +25°C, + 125°C, -55°C

Subgroup 4
Mechanical Shock
Vibration Variable Frequency

2002

Condition 8 minimum

2007

Condition A minimum
Condition E or D(Note2), Y1 Axis Only

Constant Acceleration (Centrifuge)

2001

Seal
4a) Fine Leak
4b) Gross Leak

1014

Visual Examination

10100r1011

15

4a) Condition A2
4b) Condition C

End Point Electrical Tests

SubgroupS
Salt Atmosphere
Seal
Sa) Fine Leak
5b) Gross Leak
Visual Examination

Zilog Military Electrical Specification
. Tc = +25°C, + 125°C, -55°C
1009

Condition A minimum

1014

15
Sa) Condition A2
5b) Condition C

1009

Subgroup 6
Internal Water Vapor Content

1018

Subgroup 7(Note 3)
Adhesion of Lead Finish

2025

15(Note4)

Subgroup 8(Note 5)
Lid Torque

2024

5/0

NOTES:
1. Lead Integrity Condition 0 for leadless chip carriers.
2.

Applies to larger packages which have an inner seal or cavity
perimeterof two inches or more in total length or have a package
mass of ;'5 grams.

5,000 ppm. maximum water
content at + 100°C

3/0 or 5/1

Not applicable to leadless chip carriers.
4. LTPD based on number of leads.
5. Not applicable for solder se~1 packages.
3.

659

660

~ ZiIill

Product Specification

Z8® Z8681 Military
BOMless Microcomputer

June 1987

FEATURES
• Complete microcomputer, 24 I/O lines, and up to 64K
bytes of addressable external space each for program
and data memory.

•

Full-duplex UART and two programmable 8-bit
counter/timers, each with a 6-bit programmable
prescaler.

•

•

Register Pointer so that short, fast instructions can
access anyone of the nine working-register groups.

143-byte register file, including 124 general-purpose
registers, three I/O port registers, and 16 status and
control registers.

• Vectored, priority interrupts for I/O, counter/timers, and
UART.

• Single + 5V power supply-all I/O pins TIL-compatible.
• Available in 8 MHz.

• On-chip oscillator that accepts crystal or external clock
'drive,

GENERAL DESCRIPTION
The 28681 is the ROM less version of the 28 single-chip
microcomputer. The 28681 offers all the outstanding
features of the,28 family architecture except an on-chip
program ROM. Use of external memory rather than a
preprogrammed ROM enables this 28 microcomputer to be
used in low volume applications or where code flexibility is
required.
The 28681 can provide up to 16 output address lines, thus
permitting an address space of up to 64K bytes of data or
program memory. Eight address outputs (ADo-AD7) are
provided by a multiplexed, 8-bit, Address/Data bus. The
remaining 8 bits can be provided by the software
configuration of Port 0 to output address bits Aa-A15.

Available address space can be doubled (up to 128K bytes)
by programming bit 4 of Port 3 (P34) to act as a data memory
select output (OM). The two states of OM together with the
16 address outputs can define, separate ,data and memory
address spaces of up to 64Kbytes each.
There are 143 bytes of RAM located on-chip and organized
as a register file of 124 general-purpose registers, 16 control
and status registers, and three I/O port registers. This
register file can be divided into nine groups of 16 working
registers each. Configuring the register file in this manner
allows the use of short format instruction~; in addition, any of
the individual registers can be accessed directly.

,661

ABSOWTI: MAXIMUM RATINGS
Guaranteed by characterization/design
Voltages on all pins except RESET
with respecttoGND . " ........ ; ... -0.3Vto + 7.0V
Operating Case Temperature ........ - 55°C to + 125°C
Storage Temperature Range ........ - 65°C to + 150°C
Absolute Maximum Power Dissipation ............ 1.7 W

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum: rating conditions for extended periods may affect
device relia~ility.

STANDARD TEST CONDITIONS

+5V
2.1K

The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND (OV). Positive current flows
into the referenced pin.
Military Operating Temperature Range (Te)
- 55°C to + 125°C
Standard Military Test Condition
+4.5';;; Vcc';;; +5.5V

Test Load

DC CHARACTERISTICS
Symbol

Parameter

Min

VCH

Clock Input High Voltage

VCl

Clock Input Low Voltage

VIH

Input High Voltage

Vil

Input Low Voltage

VRH

Reset Input High Voltage

VRl

Reset Input Low Voltage

VOH

Output High Voltage

Val

Output Low Voltage

Max

Unit

Condition

3.S a

Vcc b

V

Driven by External Clock Generator

-O.3 b

o.sa

V

Driven by External Clock Generator

2.0a

Vcc b

V

-O.3 b

o.sa

V

3.S a

Vce b

V

-O.3 b

o.sa

V

2.4a
O.4 a

V

IOH

V

IOl

= -2S01lA
= +2.0mA

III

Input Leakage

-10a

10a

~

VIN '" OV, S.SV

IOl

Output Leakage

-10a

10a

~

VIN

IIR

Reset Input Current

-soa

~

Vcc

Icc

Vce Supply Current

230a

mA

All outputs and I/O pins floating

= OV, S.SV
= MAX, VRl = OV

CAPACITANCE

TA

Symbol

Parameter

Max

Unit

CMAX

Maximum Capacitance

1Sc

pf

= 25°C, f =

1 MHz.

Parameter Test Status:
a Tested
b Guaranteed
, Guaranteed by Characterization/Design

662

)(
PORTO,

)(

DM

K

-@-I

f--®+

)(
16

3

)!

PORT 1

",,-A,

kD+

)

}

Do-D, IN

H>-

-+8

1-0-DS
(READ)

PORT 1

~I

.

CD

~
",,-A,

~y

--®-

X

Do-D, OUT

I--®--I
~

DS
(WRITE)

<

@~1\

_I

7

}(
-®-I

Y

Figure 1. External 110 or Memory ReadlWrite Timing

AC CHARACTERISTICS
External 110 or Memory Read and Write Timing

Z8681
8 MHz
Number

Symbol

Parameter

Min

1

TdA(AS)

Address Valid to AS t Delay

50 a

2

TdAS(A)

AS t to Addr~ss Float Delay

70a

3

TdAS(DR)

AS t to Read Data Required Valid

Max

2,3
2,3
420 a

4

TwAS

AS Low Width

5

TdAz(DS)

Address Float to DS •

Ob

6

TwDSR

DS (Read) Low Width

250 a
160a

Boa

7

TwDSW

DS (Write) Low Width

B

TdDSR(DR)

~ • to Read Data Required Valid

9

ThDR(DS)

Read Data to DS t Hold Time

oa

Notes' •

1,2,3
2,3

1,2,3
1,2,3
200a

1,2,3

10

TdDS(A)

DS t to Address Active Delay

70 a

2,3

11

TdDS(AS)

~ t to AS • Delay

70a

2,3

12

TdRIW(AS)

RfW Valid to AS t Delay

50 a

2,3

13

TdDS(R/W)

DS t to RfW Not Valid

60a

2,3

14

TdDW(DSW)

Write Data Valid to DS (Write) • Delay

50 a

2,3

15

TdDS(DW)

~ t to Write Data Not Valid Delay

60 a

16

TdA(DR)

Address Valid to Read Data Required Valid

17

TdAS(DS)

AStto~. Delay

NOTES;
1. When using extended memory timing add 2 TpC.
TIming numbers given are for minimum TpC.
". See clock cycle time dependent characteristics table.
• All unrts in nanoseconds (ns).
o All timing references use 2.0V for a logic "1" and O.BV fora logic "0':

2,3
410a

Boa

1,2,3
2,3

Parameter Test Status:
a Tested
b Guaranteed
c Guaranteed by Characterization/Design

663

Figure 2. Additional Timing

AC CHARACTERISTICS
Additional Timing Table

Z8681
8MHz
Number

Symbol

Parameter

Min

Max

125a

1000a

1

TpC

Input Clock Period

2

TrC,TfC

Clock Input Rise and Fall Times

3

T'::C

!r:p!..!t C!0ck Width

4

TwTinL

5

25 b
37 b

1

Timer Input Low Width

100b

2

TwTinH

Timer Input High Width

3TpCb

2

6

TpTin

Timer Input Period

8TpCb

7

TrTin,TfTin

Timer Input Rise and Fall Times

8A

TwlL

Interrupt Request Input Low Time

100b

2,3,4

88

TwlL

Interrupt Request Input Low Time

3TpCb

2,3,5

9

TwlH

Interrupt Request Input High Time

3TpCb

2,3

NOTES:
1. Clock timing references use 3.8Vfor a logic "1" and D.8V for a logic "D".
2. Timing references use 2.DVfor a logic "1" and D.8V for a logic "D':
3. Interrupt request via Port 3.
Parameter Test Siatus:
a Tested
b Guaranteed
c Guaranteed by Characterization/Design

664

Notes·

2

100b

4. Interrupt request via Port 3 (P31-P33)
5. Interrupt request via Port 3 (P30)
• Units in nanoseconds (ns).

2

DATA IN

DATA IN VALID

----~~~~~~~~-------DAY--------------------~~----~
~----~~------------------------(INPUTj
RDY

(OUTPUT)

Figure 3a. Input Handshake Timing

DATA OUT

DATA OUT VALID

DAY
(OUTPUT)

RDY
(INPUT)

Figure 3b. Output Handshake Timing

AC CHARACTERISTICS
Handshake Timing
\

Z8681

Number

Symbol

Parameter

Min

1

TsDI(DAV)

Data In Setup Time

2

ThDI(DAV)

Data In Hold Time

230 a

3

TwDAV

Data Available Width

17Sa

4

TdDAVlf(RDY)

S

TdDAVOf(RDy)

f5iW ,Input to RDY, Delay
f5iW, Output to RDY , Delay

6

TdDAVlr(RDY)

DAV t Input to RDY t Delay

7

TdDAVOr(RDY)

f5iW t Output to RDY t Delay

8

TdDO(DAV)

Data Out to DAV , Delay

9

TdRDY(DAV)

Rdy ,Input to DAV t Delay

Max

Notesf*

oa

17Sa

1

2

oa
17Sa

2

oa
soa

Ob

200 a

NOTES:
1. Inpu1 handshake
2. Output handshake
t All timing references use 2.DVlor a logic "1" and D.BVlor a logic "0':
• Units in nanoseconds (ns).
Parameter Test Status:
a Tested
b Guaranteed
c Guaranteed by Characterization/Design

665

PIN DESCRIPTION
AS. Address Strobe (output, active Low). Address Strobe is
pulsed once at the beginning of each machine cycle.
A.ddresses output via Port 1 for all external program or data
memory transfers are valid at the trailing edge of AS.

RESET. Reset (input, active Low). RESET initializes the
Z8681. After RESET the Z8681 is in the extended memory
mode. When RESET is deactivated, program execution begins from program location OOOCH.

OS. Data Strobe (output, active Low). Data Strobe is

RIW. ReadNVrite (output). Rm

activated once for each external memory transfer.

POO·P07. P20·P27. P30·P37' I/O Port Lines (input/outputs,
TIL-compatible). These 24 lines are divided into three 8-bit
I/O ports that can be configured under program control for
I/O or external memory interface.

is Low when the Z8681 is
writing to external program or data memory.

XTAL 1. XTAL2. Crystal 1, Crystal 2 (time-base input and
output). These pins connect a parallel-resonant crystal to the
on-chip clock oScillator and buffer.

P1o·P17' Address/Data Port (bidirectional). Multiplexed
address (Ao-A?) and data (Do-D?) lines used to interface with
program and data memory.

PACKAGE PINOUTS

REm

+SV

+SV

P3.

R/W

GND

XTAL2

P3,

os

XTAL1

XTAL1

P2,

AS

XTAL2

P3,

P2,

(

PO,

P2"

P3,

P2,

I

PO,

P2,

RESET

P2.

PO,

P2,

Rfy/

P23

P03

P23

os

P2,

PO.

P2.

AS

TIMINGf~
AND

CONTROL

PORT 0
(NIBBLE
PROGRAMMABLE,

l

110 OR Ab-A'5

PO,
PO.
PO,

PORT 1
(BYTE

'~M_"'·I
AOr,-AD,

Z8681

MCU

P33

P2.
P2,

P3,

P3,

PO,

Pl,

P3,

Pl,

P3,

po,
po,

P33

P03

Pl,

P3.

Pl,

P3,

po.
po,
po,

P3 7

Po,

Pl,

P3,

Figure 4. Pin Functions

666

P2,
P2,

P25

P3.

Pl,

Pl,
Pl,

Figure 5. 40-pin Dual·ln-Line Package (DIP).
Pin AsSignments

MIL-STD-883 MILITARY PROCESSED PRODUCT
•

Mil-Std-883 establishes uniform methods and procedures for testing microelectronic devices to insure the
electrical, mechanical, and environmental integrity and
reliability that is required for mnitary applications.

•

Mil-Std-883 Class B is the industry standard product
assurance level for military ground and aircraft
application.

• The total reliability of a system depends upon tests that
are designed to stress specific quality and reliability
concerns that affect microelectrqnic products.
• The follOWing tables detail the 100% screening and electrical tests, .sample electrical tests, and Qualificationl
Quality Conformance testing required.

.

Zllog Military PrOduct Flow
ENVIRONMENTAL SCREENING
• STABILIZATION BAKE
• TEMPERATURE CYCLE

• CENTRIFUGE

667·

Table I
MIL·STD·883 Class B Screening Requirements
Method 5004

,

MiI·Std·883
Method

Internal Visual

2010

Condition B

100%

Stabilization Bake

1008

Condition C

100%

Temperature Cycle

1010

Condition C

100%

Constant Acceleration (Centrifuge)

2001

Condition E or D(Npte 1), Yl Axis Only

100%

Zilog Military Electrical Specification
Static/DCTc = +25°C

100%

Condition D(Note 2), 160 hours,
TA = + 125°C

100%

Interim Electri<;:al Tests

Zilog Military Electrical Specification
StaticlDC Tc = + 25°C

100%

PDA Calculation

PDA

Final Electrical Tests

Zildg Military Electrical Specification
StatiC/DCTc = +125°C, -55°C
Functional, Switching/AC Tc = + 25°C

100%

100%
100%

Test

Initial Electrical Tests
Burn-In

1015

Test Condition

= 5%

f'lne Leak
Gross Leak

1014

Condition B
ConditionC

Quality Conformance Inspection (QCI)
Group A
Each Inspection Lot
Group B
Every Week
Group C
Periodically (Note 3)
Group D'
Periodically (Note 3)

5005
5005
5005
5005

(See Table II)
(See Table III)
(See Table IV)
(See Table V)

External Visual

2009

lU14

Requirement

QA-Ship
NOTES:
1. Applies to larger packages which have an inner seal or cavrty perimeter of two inches or more in total length or have a package
mass of ~5 grams.
.
2. In process of fully implementing of Condition 0 Burn-In Circuits. Contact factory for copy of specific burn-in circuit available.
3. Performed periodically as required by Mil-Std-883, paragraph 1.2.1 b(17).

668

100%

Sample
Sample
Sample
Sample
100%
100%

Table II Group A
Sample Electrical Tests
MIL-STD-883 Method 5005
LTPD
Max Accept = 2

Subgroup

Tests

Temperature (Tc)

Subgroup 1

StaticlDC

+25°C

2

Subgroup 2

Static/DC

+125°C

3

Subgroup 3

Static/DC

-55°C

5
2

Subgroup 7

Functional

+2SoC

Subgroup 8

Functional

-55°C and +125°C

5

Subgroup 9

Switching/AC

+25°C

2

Subgroup 10

Switching/AC

+ 125°C

3

Subgroup 11

Switching/AC

-55°C

5

NOTES:
• The specific parameters to be included for tests in each subgroup shall be as specified in the applicable detail electrical specification. Where no
parameters have been identified in a particular subgroup or test within a subgroup, no Group A testing is required for that subgroup or test.
• A single sample may be used for all subgroup testing. Where required size exceeds the lot size, 100% inspection shall be allowed.
• Group A testing by subgroup or ,within subgroups may be performed in any sequence unless otherwise specified.

669

Table III Group B

Sample ~st,Peiform.d Every Week to
Test Construction and In.ure Integrity of Auembly Process.
MIL-STD-883 Method 5005
Subgroup,

MII:-Std-883
MethOd

Test Condition

Quantity or
, LTPD/Max Accept

SubsjrOup1 ,
Physical birrieAsions

2016

2/0

$ubgi'Oup2
Resistance to Solvents .

2015

4/0

$ubgroup3
Solderability

2003

Solder Temperature
+245°C ± 5°C

J5(Note1)

SubgrOup 4
Internal Visual and Mechanical

SubgroupS
Bond Strength

2014

1/0

2011

C

15(Note2)

1018

1000 ppm.
'maximum at + 100°C

3/0 or 5/1

Su~group 6(Note 3)

Internal Water Vapor Content

Subgroup t(Note 4)
Seal
7a) Fine Leak
7b) GroSs Leak
Subgroup s(Note 5)
Electrostatic Discharge Sensitivity

1014

5
7a) B
7b) C

3015

Zilog Military Electrical
Specification
Static/DCTc = +25°C
A = 20·2000V
B = >200QV
Zilog Military Electrical
Specification
Static/DCTc = +25°C

15/0

NOTES:
Number of lea~s inspected selected from a minimum of 3 devices.
Number oi bond pulls selected from a minimum of 4 devices.
lest applicable only if,the package contains a dessicant.
.
lest not required if efher 100% or sample seal test is performed between final electrical tests and external visual during Class B screening.
5. lest required for ihitial qualification and product redesign. .
'

1.
2.
3.
4.

670

Table IV Group C
Sample Test Performed Periodically to Verify Integrity of the Ole.
MIL-STO-883 Method 5005
Subgroup
Subgroup 1
Steady State Operating Life

MII-Std-883
Method
1005

End Point Electrical Tests

Subgroup 2
Temperature Cycle

Test Condition
Condition D(Note 1), 1000 hours at
+125QC

ConditionC

Constant Acceleration (Centrifuge)

2001

Condition E or D(Note 2), Y1 Axis Only

Seal
2a) Fine Leak
2b) Gross Leak

1014

End Point Electrical Tests

5

Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C·
1010

Visual Examination

Quantity or
LTPO/Max Accept

15
2a) .Condition B
2b) Condition C

1010 or 1011
Zilog Military Electrical Specification
Tc = +25°C, + 125°C, -55°C

NOTE:
1. In process of fully implementing Condition D Burn·ln Circuits. Contact factory for copy of specific burn·in Circuit available.
2. Applies to larger packages which have an inner seal or cavity perimeter of two inches or more in total length or have a package
mass of ;'5 grams.

671

Table V Group 0
Sample Test Performed Periodically to In,ure Integrity of the Package.
, MIL-STD-883 Method 5005
Subgroup

Mil-Std-883
Method

Test Condition

Quantity or '
LTPD/Max Accept

Subgroup 1
Physical Dimensions

2016

Subgroup 2
Lead Integrity

2004

Condition 82 or D(Note 1)

15

Subg..oup3
Thermal Shock

1011

Condition 8 minimum,
15 cycles minimum
Condition C, 100 cycles minimum

15

Temperature Cycling

1010

Moisture Resistance

1004

Seal
3a) Fine Leak
3b) Gross Leak

1014

Visual Examination

3a) Condition B
3b) Condition C
1004 or 1010

End Point Electrical Tests
Subgroup 4
Mechanical Shock

Zilog Military Electrical Specification
Tc = +25°C, + 125,oC, ":'55°C

Vibration Variable Frequency

2002
2007

Constant Acceleration (Centrifuge)

2001

Seal
4a) Fine Leak
4b) Gross Leak

1014

Visual Examihation

Seal
5a) Fine Leak
5b) Gross Leak
Visual Examination

Condition 8 minimum
Condition A minimum
Condition E or D(Note 2), Y1 Axis Only

15

4a) Condition B
4b) Condition C
1010 or 1011

End Point EI~trical Tests
Subgroup 5
S.alt Atmosphere

15

Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C
1009
1014

Condition A minimum
15
5a) Condition B
5b) Condition C

1009

Subgroup 6
Internal Water. Vapor Content

1018

Subgroup 7(Note 3)
Adhesion of Lead Finish

2025

15(Note4)

Subgroup 8(Note 5)
Lid Torque

2024

5/0

NOTES:
1, Lead Integrity Condition Dfor leadless chip carriers, ,
2, Applies to larger packages which have an inner seal or cavity
perimeter of two inches or more in total length or have a package
mass of ~5 grams,

672

5,000 ppm. maximum water
content at + 100°C,

Not applicable to leadless chip carriers.
4. LTPD based on number of leads,
5. Not applicable for solder seal packages,

3,

3/0 or 511

PACKAGE INFORMATION

18

18·Pln Ceramic Package

~~J.E:::::::I
0.300
1-0.320-

B
,

0.025
G.ii3ii

-I O.oes~
.001

~0920~'
MAX
--11-0.040

0.130

TT-~Ji~:
, t~125
T
m

+~
~
_ 0.050

0.325
1_ + 025 _I
r- -:015 --,

~

.. .015

I+-I

.-+114-

II

0.100--l
TVP
I

I

MIN

18·Pin Plastic Package
NOTE: Package dimensions are given

I~

inches. To convert to millimeter•• multiply by 25.4

?

673

PACKAGE INFORMATION (Continued)

tt

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TYP

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674

I

PACKAGING INFORMATION

21

40

T

0.510

I~~~r=n=rr=n::::n=;=;=:;::;~;=;=;=l
20

r..--m----1


-~':-----+l·I.,.

1-----

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J

+::~~

'MIN

I---:::~----l

4O-pID Plastic: DIP

.!e!~~4O~-U-LLLLLLLLL~~U-LLLLLL~~~-U-U-LLLL21L,
0.550

~~~~~~~~~~~
,.
20

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0230

0.056

I

Tb~
o",ffi f.--~~fH~~~S ~ I.-:;~ ~L:~!
0.040
::t.02O

4O-pID Cerd1p Package

NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.

675

PACKAGE INFORMATION (Continued)

•••••••••••••••••••

0.1..
t'I -000000000000
J 0.300
0.987 t

10r

T

or /
IDENTIA

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• • • • • • • • • • • ••••
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FlCATION

SOCKET A

,IDENT!

.

II

.

CERAMICLlD\

0.10

1---+----,

EPOXY/GLASS\

4PL

U"--~FILE

I

'1-

PINSTAND-OFF/

SOCKET

0.200 -0.300-1

-0.300

-0.400

4O-p1D Low Profile Protopack

676

1-·

! O'r
f .1.

0.520~

.

1.690
0.100)( 19 = 1.900

2.311

~

..

t--0.3~~

..140

j

PIN 1

0

IDENTIFICATION

,,45 x 0.45 MAX
"

45· x 0.045 MAX",

0.026.l~'.tt!::~~"" !~0'650
I 1

NOMINALT

~====~~ lI"~
••

45· x 0.010 MAX../
3 PLACES

H~
0.023 ± .003
- 0.105 ± .005

I_~

O.174±.OO5

44-pinPCC

.-------~4~°:J[JE:J[J[:J[Jc:J[J[:J[Jc:J[~~~==========~~21~
D D D D D D D D D D D D
1

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D
Ll~DDDDDUDDDDD

~~;D

IDENTIFICA~:~~ ~ .1
SOCKET A / ~ '1_0.050±.020

20

2.020 MAX

•

L--,-_ _ _--,--'

F

'I

1.220 MAX

-t-~_0'530SQ'
I
~~~
MAX
~

~~~

I
-l

U
0.010

.......... -::!::.002

TYP

I_OR~9~~1

O.040J
±.020

1- ,

~I

.

1-+0.050±.015 BOTH ENDS

_

1--0.100 ± .010 TYP

•

,

_11_~·0~t3
TYP

1.900
REF

'
........

1

_0.040 + .007 TYP

-.002

~5
MIN

•

4O-pin Protopaclc

677

PACKAGING INFORMATION (Continued)
48

25

0.062
RADIUS

r1
15"

" ..m."M.m

4

I~~:~~=J

l r-

4 PLACESti

~

~00·.665100-~:~~~

'1-

0.180
MAX

.tt~'

oI]

I

MIN.

0.060

TYP.

11~0'060

0.040

48-Pin Dual-in-Line Package (DIP),
Plastic

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'------
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