Z8_Family_Design_Handbook_Jun88 Z8 Family Design Handbook Jun88
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Zilog
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June 1988
Z8® Family
Design Handbook
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June 1988
Z8® Family
Design Handbook
INTRODUCTION
Zilog was founded in 1974, and within its first year
brought to market the most popular and best selling
microprocessor in the world, the Z80 8~bit
microprocessor.
With the unparalleled success of the Z80 CPU, the
name Zilog became synonomous with quality, design
integrity, and complete company support elements that
remain integral to Zilog today.
Headquartered in Campbell, California, Zilog draws
upon the services and skills of the most talented high
technology minds in the industry. Zilog's Nampa, Idaho
manufacturing facility, and assembly plant in the
Philippines are the best of their size today. They provide
Zilog customers with a total solution, from engineering,
to production, to worldwide on-time delivery of the
growing family of Zilog microprocessor and peripheral
products.
Z8 Family Design Handbook
Table of Contents
Z8 NMOS MCU Microcomputers
Z8600
Z8601111
Z8603/13
Z8671
Z8681 182
Z8691
MCU 2K 28-pin
MCU 2K!4K
MCU Protopak 2K!4K
MCU with Basic/Debug Interpreter
MCU ROMless
MCU ROMless
Page
13
30
50
71
Z8 CMOS MCU Microcomputers
Z86C08
Z86COO/C10/C20
Z86C11/E11
Z86C21 IZ86E21 IC 12
Z86C91
MCU 2K 18-pin
MCU 4K8K 28-pin
MCU4K
MCU 8K!OTP (One lime Programmable MCU)
MCU ROMless
89
105
117
134
153
Z8 Application Notes and Technical Articles
Memory Space and Register Organization App Note
A Programmer's Guide to the Z8 MCU
Z8 Subroutine Ubrary
A Comparison of MCU Units
Z86xx Interrupt Request Registers
Z8 Family Framing
Z8 MCU Technical Manual
171
173
198
248
261
262
264
Super8 MCU Microcomputer
Z8800/01
Z8820
Z8822
MCU ROM less
MCU8K
MCU 8K Protopak
403
403
403
Super8 Application Notes and Technical Articles
Getting Started with the Zilog SuperS
Polled Asynchronous Serial Operation with the SuperS
Using the Super8 Interrupt Driven Communications
Using the SuperS Serial Port with DMA
Generating Sine Waves with Super8
Generating DTMF Tones with Super8
A Simple Serial Parallel Converter Using the Super8
434
438
443
448
453
458
462
SuperS Technical Manual
470
Military Electrical Specifications
Z8611
Z8~81
MCU4K
MCU ROMless
609
632
Packaging Information
645
Ordering Information
651
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June 1937
FEATURES
[J
Complete microcomputer, 2K bytes of ROM, 128 bytes of
RAM, and 221/0 lines.
o Register Pointer so that short, fast instructions can
access anyone of the nine working register groups.
o
144-byte register file, including 124 general-purpose
registers, four I/O port registers, and 14 status and
control registers.
o On-chip oscillator that accepts crystal or external
clade drive.
o
8MHz
o Vectored, priority interrupts for I/O and counter/timers.
o Single + 5 power supply-all pins TTL-compatible.
o Two programmable 8-bit counter/timers, each with a 6-bit
programmable prescaler.
o Average instruction execution time of 2.2 !!S.
minimum 1.5 !!S.
GENERAL DESC~IPTION
The Z8600 microcomputer introduces a new level of
sophistication to single-chip architecture. Compared to
earlier single-chip microcomputers, the Z8600 offers:
o faster execution
o more efficient use of memory
110.
o more sophisticated interrupt, input/output, and bit
manipulation capabilities
TIMING (~ RESET
AND
CONTROL
+5V
os
~~.{~
~mm
po.
po,
po,
po,
po.
po.
XTALl
XTAL2
.....-
-I
CLOCr(
PORT 3
Z8S00
MCU
P2,
P2,
P2,
Pl.
P2.
Pl.
P2.
Pl,
- GND
o easier system expansion
Under progr~m control, the MCU can be tailored to the
needs of its user. It can be configured as a stand-alone
microcomputer with 2K bytes of internal ROM. In all
configurations, a large number of pins remain available for
P17
PORTf
........
-
........
Figure 1. Pin Functions
The MCU is offered in a28 pin Dual-In-Line-Package (DIP)
(Figures 1 and 2).
+5V
P3,
XTAL2
P3,
XTALl
P2.
RESET
P2.
os
P2,
P3.
P2,
GND
P2,
po.
P17
PO,
Pl,
PO,
Pl.
PO,
Pl.
PO•
Pl,
PO.
Pl,
Pl.
Pl,
Figure 2. Pin Assignments
PIN DESCRIPTIONS
RESET. Reset (input. active Low). RESET initializes the
OS. Data Strobe (output. active Low). Data Strobe is
activated once for each memory transfer.
MCU. When RESET is deactivated. program execution
begins from internal program location OOOCH.
POo·PO s • P10·P17. P21·P2S. P310 P3S. P36' liD Port lines
(bidirectional. TTL-compatible). These 22 110 lines are
XTAL 1. XTAL2. Crystal 1, Crystal 2 (time-base input and
output). These pins connect a parallel-resonant 8 MHz
crystal to the on-chip clock oscillator and buffer.
grouped in four ports that can be configured under program
control for 1/0.
ARCHITECTURE
The MCU's architecture is characterized by a flexible I/O
scheme, an efficient register and address space structure.
and a number of ancillary features that are helpful in many
applications. (Figure 3).
Two basic internal address spaces are available to support
this wide range of configurations: program memory and the
register file. The 144-byte random-access register file is
composed of 124 general-purpose registers. four I/O port
registers, and 14 control and status registers.
Microcomputer applications demand powerful I/O
capabilities. The MCU fulfills this with 22 pins dedicated to
input and output. These lines are grouped in four ports and
are configurable under software control to provide timing,
status signals, and parallel I/O.
110
To unburden the program from coping with real-time
problems such as counting/timing, two counter/timers with
a large number of user-selectable modes are offered
on-chip.
I/O
(BIT PROGRAMMABLE)
Figure 3. Functional Block Diagram
2
110
(BYTE PROGRAMMABLE)
ADDRESS SPACES
Program Memory. The 16-bit program counter addresses
Instructions can access registers directly or indirectly with
an 8-bit address field. The MCU also allows short 4-bit
register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the register file is
divided into nine working-register groups, each occupying
16 contiguous locations (Figure 6). The Register Pointer
addresses the starting location of the active working-register
group.
2K bytes of program memory space as shown in Figure 4.
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain three 16-bit
vectors that correspond to the three available interrupts.
Register File. The 144-byte register file includes four I/O
port registers (R o-R3), 124 general-purpose registers
(R4-R127) and 14 control and status'registers (R241-R255)'
These registers are assigned the address locations shown in
Figure 5.
Stacks. An 8-bit Stack Pointer (R255) is used for the internal
stack that resides within the 124 general-purpose registers
(R4-R127)'
.
2047
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED
AFTER RESET
INTERRUPT
VECTOR
(LOWEll BYTE)
ON·CHIP
ROM
~ ~-----------11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
RESERVED
8
RESERVED
IRQ2
5 "'.
INTERRUPT
VECTOR
(UPPER BYTE)
4~
IRQ2·
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
Figure 4. Program Memory Map
IDENTIFIERS
LOCATION
255
STACK POINTER (BITS 7-0)
254
RESERVED
SPL
RP
253
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT REQUEST REGISTER
IRQ
249
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
POIM
247
PORT 3 MODE
P3M
246
PORT 2 MODE
P2M
245
TO PRESCALER
244
TIMER/COUNTER 0
243
T1 PRES CALER
242
TIMER/COUNTER 1
241
TIMER MODE
PREO
TO
- ... { .......;,..;...;...;......L.._;........;..;........ 253
THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING-REGISTER GROUP.
127
--.
--.
PREI
Tl
TMR
--.
-,.
NOT
IMPLEMENTED
127
SPECIFIED WORKING·
REGISTER GROUP
--.
GENERAL·PURPOSE
REGISTERS
THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
-!-- PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER.
--.
·1
o
PORT 3
P3
PORT 2
P2
PORT 1
PI
PORTO
PO
Figure 5. Register File
-
...
15
r---"i/OPORTs----- 3
Figure 6. Register Pointer
3
COUNTER/TIMERS
The MCU contains two a-bit programmable counter/timers
(To and T1), each driven by its own 6-bit programmable
prescaler. The T1 presca,ler can be driven by internal or
external clock sources; however, the To prescaler is driven
by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IR0 4 (To) or
IR05 (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the'initial value. The counters can also be
programmed to stop upon reaching zero (single-pass
mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode). The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode.
The clock source for T1 is user-definable and can be the
internal microprocessor clock (4 MHz maximum) divided by
four, or an external signal input via Port 3, The Timer Mode
register configures the external timer input as an external
clock (1 MHz maximum), a' trigger input that can be
retriggerable or non-retriggerable, or as a gate input for the
internal clock, The counter/timers can be programmably
cascaded by connecting the To output to the input of T1.
Port 3 line P36 also serves as a timer output (TOUT) through
which To, T1 or the internal clock can be output.
I/O PORTS
The MCU has 22 lines dedicated to input and output
grouped in four ports, Under software control, the ports can
be programmed to provide address outputs, timing, status
signals, and parallel I/O. All ports have active pull-ups and
pull-downs compatible with TIL loads.
Port 0 can be programmed as an 110 port.
Port 1 can be programmed as a byte 110 port.
Port 2 can be programmed independently as input or
output and is always available for I/O operations. In addition,
Port 2 can be configured to provide open'drain outputs.
Port 3 can be configured as 110 or control lines. P31 is a
general purpose input or can be used for an external
interrupt request signal (IR02)' P35 and P36 are general
purpose outputs. P36 is also used for timer input (TIN) and
output (TOUT) signals.
INTERRUPTS
The MCU allows three different interrupts from three
sources, the Port 3 line P31 and the two counter/timers.
These interrupts are both. maskable and prioritized. The
Interrupt Mask register globally or individually enables or
disables the three interrupt requests. When more than one
interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All interrupts are vectored. When an interrupt request is
granted, an interrupt machine cycle is entered. This disables
all subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory vector
locations reserved for that interrupt. This memory location
and the next byte contain the 16-bit address of the interrupt
service routine for that particular interrupt request.
Polled interrupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs
can be masked and the Interrupt Request register polled to
determine which of the interrupt requests needs service.
CLOCK
The on-chip oscillator has a high-gain parallel-resonant
amplifier for connection to· a crystal or to any suitable
external clock source (XTAL 1 = Input, XTAL2 = Output).
Crystal source is connected across XTAL 1 and XTAL2 using
the recommended capacitors (C1 ~ 15 pf) from each pin to
ground. The specifications are as follows:
4
m AT cut, parallel resonant
III Fundamental type, a MHz maximum
III Series resistance, Rs ~
10011
INSTRUCTION seT NOTATION
Addressing Modes. The fol/owing notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
IRR
Irr
)(
DA
RA
1M
R
r
IR
Ir
RR
Symbols. The fol/owing symbols are used in describing the
instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "-': For
example,
dst - dst
+ src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst (7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the fol/owing six
flags:
C
Z
S
V
D
H
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:
o
1
*
}(
Cleared to zero
Setto one
Set or cleared according to operation
Unaffected
Undefined
CONDITION CODES
Value
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Mnemonic
Flags Set
Meaning
Always true
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
C= 1
C=O
Z= 1
Z=O
S=O
S= 1
V= 1
V=O
Z= 1
Z=O
(S XOR V) = 0
(SXOR V) = 1
[Z OR (SXOR V)] = 0
[Z OR (S XOR V)] = 1
C=O
C=1
(C = OANDZ = 0) = 1
(CORZ) = 1
Never true
5
INSTRUCTION FORMATS
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF
OPC
dst
OPC
INCr
One-Byte Instructions
MODE
OPC
dstlsrc
OR 11 1 1 01 dsllsre 1
CLR, CPL, DA, DEC,
DECW,INC,INCW, POP,
PUSH, RL, RLC, RR,
RRC, SRA, SWAP
OPC
MODE
sre
dst
1 1 1 0
1 1 1 0
ADC,ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
sre
dst
JP, CALL (Indirect)
OPC
dst
lOR 11 1 101
dst
MODE
dst
VALUE
MODE
MODE
sre
ADC, ADD, AND, cp,
LD, OR, SBC, SUB,
TCM, TM, XOR
OPC
SRP
OPC
VALUE
OPC
dst
OR
OR
dst
OPC
LD
OR
src
dst
ADC, ADD, AND,
CP, OR, SBC, SUB,
TeM, TM, XOR
ORj11101
r:-:....:...+..;::..:'--l
OR L!....:'--'-"-L.~'--I
LD
LD, LDC, LDCI
dst/src
OPC
src/dst
LD
OR 11 1 1 01
ee
sre
OPC
JP
DAu
DAL
I
dsl
OPC
VALUE
I
LD
CALL
R~ OPC
DJNZ, JR
dsUCC
Three-Byte Instructions
Two-Byte Instructions
Figure 7. Instruction Formats
INSTRUCTION SUMMARY
Instruction
and Operation '
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
C ZS V 0 H
ADCdst,src
dst - dst + src + C
(Note 1)
10
* * * * 0 *
ADDdst,src
dst - dst + src
(Note 1)
00
* * * *
AND dst,src
dst - dstANOsrc
(Note 1)
50
CALLdst
OA
SP-SP - 2
IRR
@SP - PC; PC - dst
CCF
C-NOTC
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
CZSVDH
CP dst,src
dst - src
(Note 1)
AD
* * * *--
DAdst
dst-OAdst
R
IR
40
41
* *.*
-** 0--
DECdst
dst-dst - 1
R
IR
00
01
-***--
06
04
------
DECWdst
dst - dst - 1
RR
IR
80
81
-***--
EF
*---;---
8F
------
rA
r=0- F
------
o
*
CLRdst
dst-O
R
IR
BO
B1
------
COMdst
dst .... NOT dst
R
IR
60
61
-**0--
6
Instruction
and Operation
01
IMR(7)-0
DJNZr,dst
RA
r- r - 1
if r;lo 0
PC-PC + dst
Range: +127, -128
X--
INSTRUCTION SUMMARY (Continued)
Instruction
and Operation
Addr Mode Opcode
Byte
dst src
(Hex)
EI
IMR(7)+-1
rE
r==I
RLdst
-
1: 1: 1: - -
R
20
IR
21
RR
IR
AD
A1
10
11
DA
eD
e:'O-F
IRR
30
RR dst
LEI LE:3J IRR
E1
If:ri=!i:3J IRR
CO
C1
,
C
'"
1: 1: - -
RRC dst
C
'* '" '* '*
1: '"
LO dst,sre
dst-sre
r
SRA dst
Lci] @J IRR
Ir
r
R
R
E4
r
X
X
r
r
Ir
R
IR
E5
R
1M
1M
E6
IR
IR
LOCdst,sre
dst ""'sre
LOCI dst,sre
dst-sre
r+-r + 1; rr+-rr + 1
r
R
C2
D2
Ir
Irr
Irr'
Ir
C3
D3
NOP
40
POPdst
dst +- @SP;
SP .... SP + 1
R
IR
50
PUSHsre
SP +- SP - 1; @SP +- sre
R
IR
70
1m
3D
DF
1-----
DO
D1
'It
20
R
FO
F1
TCM dst,sre
(NOT dst) AND sre
(Note 1)
60
TM dst,sre
dstANDsre
(Note 1)
70
XORdst,sre
dst +- dst XOR sre
(Note 1)
SO
SWAPdst
I,
S
"
oliR
'" '"
0
31
(Note 1)
NOTE 1: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to the right of the applicable addressing mode
pair.
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.
FF
(Note 1)
ORdst,sre
dst +- dst OR sre
0
SUBdst,sre
dst +- dst +- sre
E7
F5
Irr
Irr
,
SRPsre
RP +-sre
rC
r8
r9
r= 0 - F
C7
D7
E3
F3
R
(Note 1)
SCF
C+-1
eS
e=O-F
1m
R
0
SBC dst,sre
dst +- dst +- sre +- C
'" '" '" '"
EO
0
,
C
JRee,dst
RA
if ee is true,
PC-PC + dst
Range: + 127, -128
0
,
C Z S V 0 H
91
LE:J+E:iIJ IRR
RLC dst
Flags Affected
90
R
0~IR
c
-
Addr Mode Opcode
Byte
dst src
(Hex)
Instruction
and Operation
r=O-F
IRET
SF
FLAGS +- @SP; SP +- SP + 1
PC +-@SP; SP +- SP + 2; IMR (7) +-1
JPee,dst
ifee is true
PC +- dst
C Z S V 0 H
9F
INCdst
dst+-dst + 1
INCWdst
dst +-dst + 1
Flags Affected
AddrMode
dst
src
Lower
Opcode Nibble
Ir
71
RCF
C+-O
CF
RET
PC +- @SP; SP +- SP + 2
AF
0-----
R
R
R
IR
R
1M
IR
1M
7
REGISTERS (Continued)
R248 P01M
PORT 0 AND 1 MODE REGISTER
(F8H; Write Only)
PO'.PD'MODE~·
--.J ~-r
L
=
OUTPUT"" 00
INPUT
R252 FLAGS
FLAG REGISTER
(FCH; Read/Write)
LUSERFLAGF1
E~l§llli
POo.PO, MODE
00 = OUTPUT
S~A:~N;i~~C:{ON
RESERVED
.
LUSER FLAG F2
01 = INPUT
01
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
P10·P17MODE
=
00
BYTE OUTPUT
01 = BYTe INPUT
11 = HIGH·IMPEDANCE
SIGN FLAG
ZERO FLAG
os
CARRY flAG
R2491PR
INTERRUPT PRIORITY REGISTER
(F9H; Write Only)
R253 RP
REGISTER POINTER
(FDH; Read/Write)
I~I~I~I~I~I~I~I~I
I I III".
"~"'. ~
RESERVED
= 000 PRIORITY
TERRUPT GROUP
452
DON'T CARE
= 001
REGISTER
POINTER
524 :: 010
DON'TeARE
542 = 011
245 = 100
425:: 101
DON'T CARE
254=110
RESERVED = 111
R250lRQ
INTERRUPT REQUEST REGISTER
(FAH; Read/Write)
R255SPL
STACK POINTER
(FFH; Read/Write)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
RESERVED
=r
c=
= P3,INPUT (02 = IROS)
IRO'4 = To
IRQ2
lAOS == T,
R2511MR
INTERRUPT MASK REGISTER
(FBH; Read/Write)
I~I~I~I~I~I~I~I~I
II
c=
1 ENABLES IROo-IROs
(00 = IROO)
'-------RESERVED
' - - - - - - - - 1 ENABLES INTERRUPTS
Figure 8. Control Registers (Continued)
8
~I____ ~~~~~s~~~~:~R
LOWER
OPCODEMAP
Lower Nibble (Hex)
4
3
o
2
4
10,5
7
10,5
8
A
B
12/10.0
C
o
6,5
E
6.5
6.5
6.5
6,5
6,5
'2/10,5
12/10.0
6,5
DEC
DEC
ADD
ADD
ADD
ADD
ADD
ADD
LD
LD
DJNZ
JR
LD
JP
INC
R,
IR,
(1"2
'1. lr 2
R2· R,
IR2,R,
R"IM
IR"IM
rl,R2
r2. Rl
r,.RA
cc.RA
r"IM
ccDA
rl
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
IR"IM
10.5
10.5
R,
IR,
'1,(2
'1, lr2
R2,R,
IR2,R,
R"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR"IM
R,
IR,
'1,(2
'1, lr2
R2,R,
IR2,R,
R"IM
8,0
6,1
6,5
6,5
10,5
10,5
10.5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRR,
1M
'1,r2
'1, lt 2
R2. R,
IR2,R,
R"IM
IR"IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
IR1,IM
R,
IR,
'1,(2
'1, lr2
10,5
OR
R2,R,
IR2,Rl
R"IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
IR"IM
6,5
9
F
-
-
~
5
6
i
e
:;;
"
.c
7
Z
t
c. 8
c.
:::>
9
A
B
C
0
E
F
R,
IR,
'1,'2
'1, lr2
R2,R,
IR2,R,
R"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R,
IR,
'1,(2
'1, lr2
R2,Rl
IR2,R,
R"IM
IR1,IM
10/12,1
12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
'1,'2
'1, lr2
R2,R,
IR2,R,
R"IM
IR"IM
-
R2
IR2
10,5
10,5
-----e:1
DECW
DECW
DI
RR,
IRI
6,5
6,5
RL
RL
Rl
IR,
-
6.1
EI
-
10,5
10,5
6,5
6,5
10,5
10,5
10,5
14.0
INCW
INCW
CP
CP
CP
CP
CP
CP
RET
RR,
IR,
'1,(2
'1. lr2
R2,Rl
10,5
IR2,R,
R"IM
IR"IN!
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
16.0
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
IRET
R2,Rl
IR2,Rl
R"IM
IR"IM
R,
IRI
'1,{2
'1, lr2
6,5
6,5
12,0
18,0
10,5
RRC
RRC
LDC
LOCI
LD
R,
IR,
'1, lrr2
Ir1,lrr2
rj,x,R2
6,5
6,5
12,0
18,0
20,0
20,0
10,5
SRA
SRA
LDC
LOCI
CALL'
CALL
LD
'2, lrr 1
R,
IR,
Ir2.lrr1
IRRI
DA
'2,x,Rl
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
RR
LD
LD
LD
LD
LD
R2,Rl
IR2,R,
R"IM
IR"IM
R,
IR,
rl, IR2
8.5
8,5
6,5
10,5
SWAP
SWAP
LD
LD
R,
IRI
Irl,r2
R2,IR,
-
r---6,5
RCF
I--6.5
SCF
I--6.5
CCF
I--6.0
NOP
----J'-.. ----.. ----J'-.. -----..
'-...- - - -.....v ....
v ...-..;....~--.....#~~
v ....
2
2
3
Bytes per Instruction
LOWER
OPCODE
NllLE
EXECUTION
CYCLES
PIPELINE
CYCLES
MNEMONIC
Legend:
R = 8-bi' address
r = 4-bit address
Rt or'1 = Dst address
R2 or'2 = Src address
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
SECOND
OPERAND
NOTE: The blank areas are not defined.
*2-byte instruction; fetch cycle appears as a 3-byte instruction
9
REGISTERS
R241 TMR
TIMER MODE REGISTER
(F1 H; Read/Write)
NOT To",
USEDMODES
= 00
.
~o g~~
: ~~
INTERNAL CLocK OUT = 11
T
EXTERNAL CLOCK
j
-.J
R245 PREO
PRESCALER 0 REGISTER
(F5H; Write Only)
US~o
NO FUNCTION
1 = LOAD
To
=
DISABLE To COUNT
1 = ENABLE To COUNT
0
~L
0 = DISABLE T, COUNT
1 = ENABLE 11 COUNT
TRIGGER INPUT", 10
(NON·RETRIGGERABLE)
TRIGGER INPUT = 11
o '" To SINGLE·PASS
1 = To MODULO·N
RESERVED
0 = NO FUNCTION
1 = LOAD Tl
MODES
00
IN~OT =
GATE INPUT", 01
caUNTMaDE
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
(RETRIGGERABlE)
R242 T1
COUNTER TIMER 1 REGISTER
(F2H; Read/Write)
R246P2M
PORT 2 MODE REGISTER
(F6H; Write Only)
P21·P2S DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
R243 PRE1
PRESCALER 1 REGISTER
(F3H; Write Only)
R247P3M
PORT 3 MODE REGISTER
(F7H; Write Only)
ID, ID,I D, I D.I D, I D, I D, I D, I
~L
~~~
caUNTMaDE
o = T\ SINGLE·PASS
1 =,1 1 MODUlO·N
CLOCK SOURCE
1 '" Tl INTERNAL
.
0 '" T 1 EXTERNAL TIMING INPUT
(TIN) MODE
opaRT2 PULL·UPsaPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
RESERVED
RESERVED
RESERVED
o P3l = INPUT (TIN)
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
RESERVED
' - - - - - - - - - RESERVED
R244 TO
COUNTER/TIMER 0 REGISTER
(F4H; Read/Write)
Tn INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1 256 DECIMAL 01 00 HEX)
To CURRENT VALUE (WHEN READ)
Figure 8. Control Registers
10
P36", OUTPUT (Tour>
Figure 9. Timing
AC CHARACTERISTICS
Timing Table
,Z8600
Number
Symbol
Parameter
Min
Max
125
1000
25
Notes·
1
2
TpC
Input Clock Period
TrC,TIC
Clock Input Rise and Fall Times
3
TwC
Input Clock Width
4
TwTinL
Timer Input Low Width
100
2
5
TwTinH
Timer Input High Width
3TpC
2
6
TpTin
Timer Input Period
STpC
2
37
100
7
TrTin,TfTin
Timer Input Rise and Fall Times
S
TwlL
Interrupt Request Input Low Time
100
2,3
9
TwlH
Interrupt Request Input High Time
3TpC
2.3
2
NarES:
1. Clock timing references use 3.BVfor a logic "1" and O.BV for a logic "0':
2. Timing references use 2.0Vfor a logic "1" and O.BV for a logic "a':
3. Interrupt request via Port 3 (P31-P33)'
• Units in nanoseconds (ns).
11
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
toGND ....., .................... -0.3Vto +7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect .
device reliability.
STANDARD TEST CONDITIONS
+5V
I
2.1K
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are:
+4.75V~Vee~
•
+5.25V
• GND = OV
Figure 10. Test Load 1
DC CHARACTERISTICS
Symbol
Parameter
VeH
Clock Input High Voltage
Vel
Clock Input Low Voltage
VIH
Input High Voltage
Vil
Input Low Voltage
VRH
Reset Input High Voltage
VRl
Reset Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
III
Input Leakage
IOH
Output Drive Current
Min
Max
3.8
Vee
V
Driven by External Clock Generator
-0.3
0.8
V
Driven by External Clock Generator
2.0
Unit
Condition
Vee
V
-0.3
0.8
V
3.8
Vee
V
-0.3
0.8
V
V
IOH
0.4
V
IOL
,..A
OV ~ VIN ~ + 5.25V
rnA
VOH
VOH
2.4
-10
10
1.5
2.50
~A
= -250,..A
= +2.0mA
= +2.4V
= +4.0V
IOl
Output Leakage
10
,..A
OV ~ VIN ~ + 5.25V
IIR
Reset Input Current
-50
,..A
Vee
lee
Vee Supply Current
150
mA
12
-10
= + 5. 25V, VRl = OV
~
., <
~,~
~
II'
'"
'l' '
f
'X
,H __ "
~
}'" V' , • - "'"
:'''~
~
~."'.
""~!"!
'tN'
,
,
JI
"'1'0
/,
.'.prbdu'~t s,,~Cifica~ion .••...•.'.
Zilo, " .
,
".
".u,
'"
~
\
':;:",
'
,
I
,
'I.;
";
June 1987
Z8601/Z8603
Z86111Z8613 Z8®
2860l Single-Chip MCU with 2K ROM
28603 Prototyping Device with 2K EPROM Interface
28611 Single-Chip MCU with 4K ROM
.
28613 Prototyping Device with 4K EPROM Interface
Features
I!II
!lD
General
Description
Complete microcomputer, 2K (8601) or 4K
(8611) bytes of ROM, 128 bytes of RAM, 32
I/O lines, and up to 62K (8601) or 60K (8611)
bytes addressable external space each for
program and data memory.
144-byte register file, including 124 generalpurpose registers,Jour I/O port registers,
and 16 status and control registers.
iii
Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.
Il:l
Register Pointer so that short, fast instructions can access any of nine working register
groups in 1 /LS.
tllI
On-chip oscillator which accepts crystal or
external clock drive.
II!l
Average instruction execution time of 1.5 /LS,
maximum of 1 /LS.
I!]
II
Vectored, priority interrupts for I/O,
counter/timers, and UART.
1:'1 12.5 MHz.
The 28 microcomputer introduces a new level
of sophistication to single-chip architecture.
Compared to earlier single-chip microcomputers, the 28 offers faster execution; more
efficient use of memory; more sophisticated
interrupt, input/output and bit-manipulation
capabilities; and easier system expansion.
Under program control, the 28 can be tailored
to the needs of its user. It can be configured as a
PORTO
(NIBBLE
PROGRAMMABLE)
I/O OR Aa-A15
PORT 1
(BYTE
PROGRAMMABLE)
110 OR AD,-AD,
PORT 3
SERIAL AND
PARALLEL 110
AND CONTROL
Single + 5 V power supply-all pins TTL
compatible.
stand-alone microcomputer with 2K or 4K bytes
of internal ROM, a traditional-microprocessor
that manages up to 124K bytes of external
memory, or a parallel-processing element in a
system with other processors and peripheral
controllers linked by the 2-BUS® bus. In all
configurations, a large number of pins remain
available for I/O.
+5V
P3,
XTAL2
XTAl1
P3,
P2,
P3,
P2,
P3,
P2s
RESET
P2,
RIW
P2,
os
P2,
AS
P2,
P3s
GND
P20
P3,
P3,
P3,
PO,
P1,
PO,
P1.
PO,
P1,
PO,
P1,
PO,
P1,
POs
P1,
PO,
P1,
PO,
P1,
Figure 2a. 40-pin Dual-In-Line Pacl,age (DIP).
Pin Assignments
2037-001. 002
13
Pin
Description
program execution begins from internal
program location OOOCH.
ROMIess. (input, active LOW). This pin is only
available on the 44 pin versions of the Z8601 and
Z8611. When connected to GND disables the
internal ROM and forces the part to function as a
Z8681 ROMless Z8. When left unconnected or
pulled high to Vee the part will function
normally as a Z8601 or Z8611.
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along with
Ports 0 and 1, Data Strobe and Read/Write.
OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.
R/W. Read/Write (output). R/W is Low when
the Z8 is writing to external program or data
memory.
POO-P07' PIo-PI7' P2o-P27' P3 0 -P3 7. IIOPort
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports
that can be configured under program control
for I/O or external memory interface.
RESET. Reset (input, active Low). RESET initializes the Z8. When RESET is deactivated,
XTALl. XTAL2. Crystall, Crystal2 (time-base
input and output). These pins connect a parallel
resonant 12.5 MHz crystal or an external singlephase 12.5 MHz clock to the on-chip clock
oscillator and buffer.
~... '::!!.-t),
~CJ q"~--- provided by the register pointer specifies
the active worklng·reglster group.
---_.---,...-
GENERAL·PURPOSE
REGISTERS
16
Figure 5. Data Memory Map
--
12
SPECIFIED WORKING·
REGISTER GROUP
The lower
nibble of
the register
file address
- f - provided by
the Instruction
points to the
specified
register.
15
~---'IO"O"TS-----
3
0
Figure 7. The Register Pointer
2037-004.005.006.007
divided into nine working-register groups, each
occupying 16 continguous locations (Figure 6).
The Register Pointer addresses the starting
location of the active working-register group .
Staclts. Either the internal register file or the
external data memory can be used for the stack.
Serial
Input/
Output
Port 3 lines P30 and P37 can be programmed as
serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The bit rate
is controlled by Counter/Timer 0, at 12 MHz.
The 28 automatically adds a start bit and two
stop bits to transmitted data (Figure 8). Odd
parity is also available as an option. Eight data
bits are always transmitted, regardless of parity
A 16-bit Stack Pointer (R254 and R255) is used for
the external stack, which can reside anywhere in
data memory between locations 2048 (8601) or
4096 (86U) and 65535. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides
within the 124 general-purpose registers
(R4-RI27).
selection. If parity is enabled, the eighth bit is
the odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight data
bits and at least one stop bit. If parity is on, bit 7
of the received data is replaced by a parity error
flag. Received characters generate the IRQ3
interrupt request.
Transmitted Data
Received Data
(No Parity)
(No Parity)
Ipl~I~I~I~I~I~I~I~lsij
T
LSTARTBIT
LSTARTBIT
' - - - - - - E I G H T DATA BITS
' - - - - - - E I G H T DATA BITS
TWO STOP BITS
' - - - - - - - - - - O N E STOP BIT
Transmitted Data
Received Data
(With Parity)
(With Parity)
ISplpl pl~I~I~I~I~I~I~lsij
Iplpl~I~I~I~I~I~I~lal
T
I
LSTART BIT
I
' - - - - - S E V E N DATA BITS
' - - - - - - - - - 0 0 0 PARITY
L
_LSTARTBIT
'-------SEVEN OATA BITS
PARITY ERROR FlAG
' - - - - - - - - - - O N E STOP
TWO STOP BITS
BiT
Figure S. Serial Dala Formala
Counter/
Timers
2037-009
The 28 contains two 8-bit programmable
counter/timers (To and Tl), each driven by its
own 6-bit programmable prescaler. The Tl
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number from
I to 64. Each prescaler drives its counter, which
decrements the value (l to 256) that has been
loaded into the counter. When the counter
reaches the end of count, a timer interrupt
request-IRQ4 (to) or IRQ5 (Tl)-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (single-
pass mode) or to automatically reload the initial
value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read any time without disturbing
their value or count mode.
The clock source for T I is user-definable and
can be the internal microprocessor clock
divided by four, or an external signal input via
Port 3. The Timer Mode register configures the
external timer input as an external clock, a
trigger input that can be retriggerable or nonretriggerable, or as a gate input for the internal
clock. The counter/timers can be prog'rammably
cascaded by connecting the To output to the
input of T I. Port 3 line P36 also serves as a timer
output (TOUT) through which To, TI or the internal clock can be output.
17
I/O Ports
The 28 has 32 lines dedicated to input and
output. These lines are grouped into four ports of
eight lines each and are configurable as input,
output or address/data. Under software control,
the ports can be programmed to provide address
outputs, timing, status signals, serial I/O, and
parallel 1/0 with or without handshake. All ports
have active pull-ups and pull-downs compatible
with TTL loads.
Port 1 can be programmed as a byte 1/0 port
or as an addressldata port for interfacing
external memory. When used as an I/O port, Port
I may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY J
and DAV J (Ready and Data Available).
\ Memory locations greater than 2048 (28601) or
4096 (28611) are referenced through Port I. To
interface external memory, Port I must be
programmed for the multiplexed Address/Data
mode. If more than 256 external locations are
required, Port 0 must output the additional
lines.
Port I can be placed in the high-impedance
state along with Port 0, AS, DS and RIW,
allowing the 28 to share common resources in
multiprocessor and,DMA applications. Data
transfers can be controlled by assigning P33 as a
,Bus Acknowledge input and P34 as a Bus
Request output.
Port 0 can be programmed as a nibble 1/0
port, or as an address port for interfacing
external memory. When used as an 1/0 port,
Port 0 may be placed under handshake control. In this configuration, Port 3 lines P32 and
P35 are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the 1/0 direction of the upper nibble
P04-P07·
For external memory references, Port 0 can
provide address bits As-AlJ (lower nibble) or
As-AJ5 (lower and upper nibble) depending on
the required address space. If the address range
requires 12 bits or less, the upper nibble of Port 0
can be prograrvmed independently as 1/0 while
the lower nibble is used for addressing. When
'Port 0 nibbles are defined as address bits , they
can be set to the highimpedance state along with
Port 1 and the control signals AS, DS and RIW.
Port 2 bits can be programmed independently
as input or output. The port is always available
for 1/0 operations, In addition, Port 2 can be
configured to provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P3J and P36 are used as
the handshake controls lines DAV2 and RDY2.
The handshake signal assignment for Port 3 lines
P3 J and P36 is dictated by the direction (input or
output) assigned to bit 7 of Port 2.
Port :3 lines can be configured as 1/0 or
control lines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37)' For serial I/O, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four external interrupt
request signals (IRQO-IRQ3); timer input and
output signals (T~nd TOUT) and Data
Memory Select (DM).
18
PORT 1
(Ito OR ADo-AD 1)
Figure 9a. Pori 1
I
PORT 0
(110 OR A.-A1~
_
} ~:~~~~~~NTROLS
(P32 AND P3S>
Figure 9b. Pori 0
PORT 2(110)
Z8
'Meu
}
HANDSHAKE CONTROLS
DAV2 AND RDYz
(P3l AND P3S>
Figure 9c. Port 2
PORT 3
(UO OR CONTROL)
Figure 9d. Pori 3
2037,008
Interrupts
The 28 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter/timers.
These interrupts are both maskable and
prioritized. The Interrupt Mask register globally
or individually enables or disables the six interrupt requests. When more than one interrupt is
pending, priorities are resolved by a programmable priority encoder that is controlled by
the Interrupt Priority register.
All 28 interrupts are vectored. When an interrupt request is granted, an interrupt machine
cycle is entered. This disables all subsequent
interrupts, saves the Program Counter and status
flags, and branches to the program memory
vector location reserved for that interrupt. This
memory location and the next byte contain the
16-bit address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the
interrupt inputs can be masked and the Interrupt
Request register polled to determine which of the
interrupt requests needs service.
Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across XTALl
and XTAL2, using the recommended capacitors
(Cl s 15 pF) from each pin to ground. The
specifications for the crystal are as follows:
III
III
III
AT cut, parallel resonant
Fundamental type, 12.5 MHz maximum
Series resistance, Rs s 1000
19
Z8603113
Protopack
Emulator
The Z8 Protopack is used for prototype
development and preproduction of maskprogrammed applications. The Protopack is a
ROMless version of the standard Z8601 or Z8611
housed in a pin-compatible 40-pin package
(Figure 11).
To provide pin compatibility and interchangeability with the standard maskprogrammed
device, the Protopack carries piggy-back a 24pin socket for a direct interface to program
memory (Figure 1). The Z8603 24-pin socket is
equipped with 11 ROM address lirtes, 8 ROM
data lines and necessary control lines for interface to 2716 EPROM for the first 2K bytes of program memory. The Z8613 24-pi~ socket is
equipped with 12 ROM address lines, 8 ROM
data lines and necessary control lines for interface to 2732 EPROM for the first 4K bytes of
program memory.
Pin compatibility allows the user to design the
pc board for a final 40-pin maskprogrammed
Z8, and, at the same time, allows the use of the
Protopack to build the prototype and pilot
production units. When the final program is
established, the user can then switch over to the
40-pin mask-programmed Z8 for large volume
production: The Protopack is also useful in
small volume applica tions where masked ROM
setup time, mask charges, etc., are prohibitive
and program flexibility is desired.
Compared to the conventional EPROM
versions of the single-chip microcomputers, the
Protopack approach offers two main
advantages:
III
Ease of developing various programs during
the prototyping stage. For instance, in applications where the same hardware configuration is used with more than one program, the
Protopack allows economical program
storage in separate EPROMs (or PROMs),
whereas the use of separate EPROM-based
single-chip microcomputers is more costly.
II
Elimination of long lead time in procuring
EPROM-based microcomputers.
Figure 11. The Z8 Microcomputer Protopack Emulator
Instruction
Set
Notation
Addressing Modes. The following notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
Indirect register pair or indired working-register
pair address
Indirect working-register pair only
Indexed addr,ess
Direct address
Relative address
Immediate
Register or working-register address
WOI'king-register address only
Flags. Control Register R252 contains the follOWing
six flags:
address
C
Z
Ir
Indirect working-register address only
S
RR
Register pair or working register pair address
IR
Indirect-register or indirect working-register
Symbols. The follOWing symbols are used in
describing the instruction set.
dst
src
cc
Destination location or contents
Source location or cdntents
Condition code (see list)
Indirect address preHx
SP
Stack painter (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register painter (control register 253)
IMR
Interrupt mask register (control register 251)
@
20
Assignment of a value is indicated by the symbol
"-", For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
V
D
H
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half carry flag
Affect<;d flags are indicated by:
o
I,
Cleared to zero
Set to one
*
Set or cleared according to operation
X
Unaffected
Undefined
Condition
Codes
Value
Meaning
Mnemonic
1000
Flags Set
Always true
a III
=I
=a
=I
Z =a
s =a
s =I
V = I
V =0
2 = I
Z =a
Carry
C
NC
2
N2
PL
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
C
C
2
No carry
Zero
Not zero
Plus
MI
Minus
Overflow
OV
NOV
No overflow
EQ
Equal
Nat equal
Greater than ar equal
Less than
Greater than
Less than ar equal
Unsigned greater than ar equal
Unsigned less than
Unsigned greater than
Unsigned less than ar equal
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
(5 XOR V)
(5XOR V)
=a
=I
[2 OR (5 XOR V))
[Z OR (5 XOR V))
=a
=I
C=O
C = I
(C = 0 AND 2
(C OR Z) = I
= 0)
Never true
Instruction
Formats
ope
CCF, 01, El, IRET, NOP,
ReF, RET, SCF
ope
dS!
INCr
One-Byte Instructions
MODE
ope
dstlsrc
eLR, CPL, OA, DEC,
OR
h 1 1 01 dstlsrc I
ope
~="1
MODE
~~~~'~~~Rt~~~ftOP.
RRC, SRA, SWAP
OR
OR
d"
til 0
1 1 1 0
'"
d,'
Ace, ADD, AND, CPt
LO, OR, sac, SUB,
TeM, TM, XOR
JP, CALL (Indirect)
OR
11
1 1
at
ope
dst
Ace, ADD, AND, CP,
MODE
dS!
ope
OR
11
1 1
01
d,'
VALUE
SRP
lO. OR,
sac, SUB,
TeM, TM, XOR
VALUE
MODE
ope
Ace, ADD, AND,
MODE
CP, OR,
d"
sec, SUB,
ope
LO
OR
OR
d"
1 1 1 0
1 1 1 0
d"
reM, TM, XOR
MODe
ope
dsUsrc
src/dst
dstlsrc
ope
srcJdst
dst
lope
LO, LOE, LOEI,
LOC, lDCI
ope
LO
ADDRESS
OR
11
1 1
01
LO
ope
JP
OA,
DA,
LO
VALUE
IdsUCCR~ ope
MODE
dstfsrc
ope
DJNZ, JR
CAll
DA,
DA,
Two.Byte Instructions
Three-Byte Instructions
Figure 12. Instruction Formats
2037·013
21
Instruction
Summary
Instruction
and Operation
Addr Mode
ADC dst,sre
dst- dst + sre + C
(Note 1)
10
ADD dst,sre
(Note I)
00
(Note 1)
50
Opcode Flags Affected
Byte
dst
arc
(Hex)
dst - dst + sre
AND dst,sre
dst ..:. dst AND sre
*
0
*
'" * 0 '"
- '" '" 0
Instruction
and Operation
Addr Mode
LDE dst,sre
dst - sre
Byte
arc
(Hex)
r'
Irr
82
Irr
Ir
83
93
Irr
LDEI dst,sre.
Ir
Irr
dst - sre
Opcode Flags Affected
dst
r-r+ 1; rr-rr+ 1;
FF
NOP
D6
D4
OR dst,sre
dst - dst OR sre
(Note 1)
40
CCF
C - NOTC
EF
POPdst
dst - @SP
SP - SP + I
R
IR
50
51
BO
CLR dst
dst - a
IR
Bl
COM dst
dst - NOT dst
R
60
IR
61
R
(Note I)
R
AD
DA dst
dst - DA dst
IR
DEC dst
dst-dst-l
R
IR
00
DECW dst
dst-dst-I
RR
IR
80
DI
IMR (7) -
40
41
EI
IMR (7) -
* * * X- -
8F
_... - -
RR
IR
AO
Al
-... - -
mET
BF
FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR (7) - 1
••••••
JP ee,dst
if ee is true
PC - dst
IRR
JR ee,dst
RA
DA
I
90
91
~I R
~IR
10
11
RR dst
I'~ I ~ I
R
EO
El
RRC dst
LEl=C3J lJ..
CO
CI
r
R
IR
IR
r
Irr
LDCI dst,sre
Ir
Irr
dst - sre
r - r + I; rr - rr + I
IR
1m
1m
R
Irr
Ir
31
20
****1*
Fa
x**x--
FI
(Note 1)
BO
eB
e=O-F
Nolel
E6
E7
F5
C3
D3
-**0--
These instructions have an identical set of addressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the following table to the
right of the applicable addressing mode pair.
For example, to determine the opcode of a ADC
instruction use the addressing modes r (destination) and
Ir {source}. The result is 13.
Addr Mode
dst
src
Lower
Opcode Nibble
Ir
C2
D2
Irr
~. I~
'" '" '" 0
XOR dst,sre
dst - dst XOR sre
X
R
SWAP dst
(Note I)
DO
Dl
eD
e=O-F
30
r
R
R
SUB dst,sre
dst - dst - sre
1 - - - - -
70
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
r
1m
DF
(Note I)
rC
Ir
1~
• I •
TM dst, sre
dst AND sre
R
r
LEi @
o- - - - -
3D
60
1m
Ir
(Note I)
(Note 1)
r
R
X
~~IR'
TCM dst,sre
(NOT dst) AND sre
PC-PC+dst
Range: + 127, -128
LDC dst,sre
dst - sre
_ r:=:=l R
SRP sre
RP - sre
rE
r=O-F
. 20
21
LD dst,sre
dst - sre
~IR
SM dst
R
IR
if cc is true
RL dst
SCF
C-I
I
INCW dst
dst - dst +
AF
SBC dst,sre
dst - dst-sre-C
rA
r=O-F
9F
INC dst
dst - dst + I
RET
PC - @SP; SP - SP + 2
RLCdstl_
0--
70
71
CF
81
RA
R
IR
RCF
C-O
01
a
DJNZ r,dst
r - r - I
if r ,. 0
PC-PC+dst
Range: + 127, ,128
PUSH sre
SP - SP-I; @SP-sre
- * * 0 - -
CZSVDH
92
CALL dst
DA
SP - SP - 2
IRR
@SP - PC; PC - dst
CP dst,sre
dst - sre
22
C Z S VDH
R
R
R
IR
R
IR
1M
1M
8085-003
Registers
R240 SIO
Serial 110 Register
(FOH ; Read/Write)
R244 TO
Counter/Timer 0 Register
(F4H; Read/Write)
I~I~I~I~I~I~I~I~I
c=_
SERIAL DATA (Do "" LSS)
R241 TMB
Timer Mode Register
(Fl H ; Read/Write)
MODES
NOT To",
useD""
00
f~ g~~
INTERNAL CLOCK OUT
: ~~
= 11
j
~
llli~Lo
.
FUNCTION
1 "" NO
LOAD
To
1
~L
.
0 ::: DISABLE To COUNT
= ENABLE To COUNT
.
=
COUNTMODE
=
0
1
To SINGLE·PASS
= To MonUlO·N
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
1 == ENABLE 1, COUNT
,
-
RESERVED
0 = NO FUNCTION
1 = LOAD Tt
0
DISABLE 1, COUNT
T MODES
eXTERNAL CLOCK IN~UT = 00
GATE INPUT
01
=
(NON.R~~~~g~~~~:~~ = 10
TRIGGER INPUT = 11
R245 PREO
Prescaler 0 Register
(F5H; Write Only)
(RETRIGGERABLE)
R242 TI
Counter Timer 1 Register
(F2H; Read/Write)
R246 P2M
Port 2 Mode Register
(F6H; Write Only)
TtlNITIAL VALUE (WHEN WRITTEN)
'----'--(RANOE 1-256 DECIMAL 01-00 HEX)
P20-P2 7 1/0 DEFINITION
' - - - - 0 DEFINES BIT AS OUTPUT
1 DEFIN ES BIT AS INPUT
T, CURRENT VALUE (WHEN READ)
R247 P3M
Port 3 Mode Register
(F7H; Write Only)
R243 PREI
Prescaler 1 Register
(F3H; Write Only)
~L
.
COUNTMODE
0:::: Tl SINGLE-PASS
Lo1 PORT
PORT 2 PULL·UPS OPEN DRAIN
2 PULL·UPS ACTIVE
E~
1 :: T t MODULQ·N
CLOCK SOURCE
1 = T1 INTERNAL
o=
11 EXTERNAL TIMING INPUT
RESERVED
o P32
= INPUT
P3S = OUTPUT
1 P32 = I5AVO/RDYO P3S = RDYOIDAVO
o 0 P33 = INPUT
~ ~} P33 = INPUT
(TIN) MODE
PRESCALER MODULO
(RANGE: 1~64 DECIMAL
01~OO HEX)
P34
P34
= OUTPUT
= D"M
1 1 P33 = DAVilRDY1 P34 = RDY1/DJWi
'-------~ ~i~ ~ I¥.l¥::R~~1 :~: ~ ~~~~~IIT)
'--------~~~g ~ ~N~~rLIN ~i: ~ ~~~~~TOUT
'-________
~ :!=:~ g~F
Figure 13. Control Registers
2037·014
23
Registers
R248 POIM
Port 0 and I Mode Register
(F8H; Write Only)
(Continued)
-.J
PD.-PO,..MODE:]
OUTPUT
00
INPUT = 01
A12aA15 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED .. 1
~-r
L
'
R252 FLAGS
Flag Register
(FCH; Read/Write)
~m~
1
PO,-PO,
MODE
00" OUTPUT
.
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
Pi a-Pi r MODE
00 = BYTE OUTPUT
01 ... BYTE INPUT
10 = ADD-AD,
11 .. HIGH·IMPEDANCE ADo-ADr.
AS,
LUSER FLAG F"
LUSER FLAG F2
=
01
INPUT
1X ... A,-A n
' STACK SELECTION
0 "" EXTERNAL
1 = INTERNAL
ZEnO FLAG
,
CARRY FLAG
os. RIW, As-A11. A12-A15
IF SELECTED
R2491PR
Interrup,t Priority Register
(F~; Write Only)
R253 RP
Register, Pointer
(FDti; Read/Write)
lo,l~I~I~lo,lo,lo,lo,l
I I III ,.-".~"'~
~.:J
.
IRQ3, IRQS PRIORITY (GROUP A)
o = IRQS > IRQ3
1=IRQ3:>IRQS,
\
IROO, IRQ2 PRIORITY (GROUP 8)
0= IRQ2> lRQO
1
,I
=
=
RESERVED
000
C :> A :> B = 001
A > B :> C
010
A>C>B=D11
B :> C > A = 100
C :> B > A = 101
LDON'TCARE
'
REGISTER
POINTER
B>A>C=110
= IROO :> IRQ2
RESERVED
= 111
IRQ1, IRQ4 PRIORITY (GROUP C)
IRQ1 > IRQ4
1 = IRQ4 > IRQ1
o=
R250mQ
Interrupt Request Register
(FAH ; Read/Write)
RESERVEDT
C='ROO
IRQ1
IRQ2
IRQ3
IRQ4
IRQS
R254 SPH
Stack Pointer
(FEH; Read/Write)
P32 INPUT (Do .. IRQO)
P33INPUT
.
P3-t INPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T,
R255 SPL
Stack Pointer
(FFH ; Read/Write)
R251lMR
Interrupt Mask Register
(F~; Read/Write)
I' I
c=
1 ENABLES IRQO-IRQS
(Do"'" IRQO)
L-------RESERVED
" - - - - ' - - - - - 1 ENABLES INTERRUPTS'
Figure 13_ Control Registers (Continued)
24
2037-014
Opcode
Lowor Nibble (Hex)
Map
o
o
6,5
5
8
i
~
7
:!I
2:
~
i
8
C
E
F
B
6,5
6,5
la,S
la,S
la,S
la,S
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
LD
LD
DJNZ
JR
ID
JP
INC
Il,Rz
la,Rl
IIIRA
ce,RA
1l,IM
ce,DA
II
R.,R,
IR.,R,
R"IM
1R1,IM
6,5
la,S
la,S
la,S
la,S
R1
1R1
1l,IZ
I1,II2
R.,R,
IR.,R,
R"IM
6,5
6,5
6,5
la,S
la,S
la,S
INC
INC
SUB
10.5
IR.,R,
SUB
SUB
r1,II2
R.,R,
SUB
1R1
n,la
SUB
R"IM
IR"IM
8,0
6,1
6,5
6,5
la,S
la,S
la,S
la,S
IP
SBP
1M
SBC
SBC
SBC
SBC
Z'l,IrZ
IR.,R,
SBC
11,Ia
R:i,R,
SBC
R"IM
IR"IM
8,5
8,5
6,5
6,5
la,S
la,S
la,S
la,S
DA
DA
OR
OR
OR
OR
OR
OR
1R1,IM
SUB
u,lra . R.,R,
R1
1R1
II,r2
IR.,R,
R"IM
la,S
6,5
6,5
la,S
la,S
la,S
la,S
POP
POP
AND
AND
Il,l2
R.,R,
IR.,R,
AND
AND
'1R1
AND
R1
AND
n,Ira
R"IM
IR 1, 1M
6,5
6,5
6,5
6,5
la,S
la,S
la,S
la,S
TCM
TCM
TCM
TCM
TCM
TCM
COM COM
ll,Ia
n,lrz
R.,R,
IR.,R,
R"IM
1R1,IM
10/12,1 12/14,1
6,5
6,5
la,S
la,S
la,S
la,S
PUSH PUSH
TM
TN
TN
R.,R,
TN
IR.,R,
TM
TM
R"IM
IR 1, 1M
1R1
R.
IR.
n,la
Il,II2
la,S
la,S
12,0
18,0
DECW DECW LDE
LDEI
IR1
6,5
12,0
Irl,Irrz
18,0
RL
IDE
LDEI
1R1
lIn Ira, lIn
6,5
6,5
r1,IIl2
R,
la,S
la,S
INCW !NCW
F
E
-
1R1
la,S
la,S
la,S
CP
CP
CP
CP
CP
R.,R,
IR.,R,
R"IM
1R1,IM
6,5
6,5
6,5
6,5
la,S
la,S
la,S
la,S
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R.,R,
IR.,R,
R"IM
1R1,IM
1I,la
Il,II2
6,5
12,0
18,0
RRC
RRC
LDC
IDCI
6,5
12,0
18,0
SRA
IDC
IDCI CALL*
R1
1R1
l2,IIIl
20,0
6,5
RR
R1
20,0
CALL
6,5
la,S
la,S
la,S
la,S
RR
LD
LD
LD
ID
LD
1R1
n,Ir2
R.,R,
R"IM
1R1,IM
DA
IR.,R,
6,5
la,S
ID
ID
l2,
~,
______
14,0
-
IRET6,5
RCF
6,5
SCF
x, HI
6,5
CCF
~
,6,0
NOP
~~,
2
EI
- 16,0
'R.,IR,
In,I2
______"
DI
RET
LD
IRR1
~~
~
-
x, Hz
10,5
Ira, III I
6,5
______
-
LD
6,5
1R1
-
II,
SRA
Ii;s
~8,S
SWAP SWAP
-
la,S
n,IrI2 Irl,Irl2
1R1
-
la,S
n,lI2
1R1
-
6,1
CP
R1
-
-
Il,r2
6,5
-
6,1
CLR
~,
D
1R,,1M
la,s
RL
C
BLC ADC ADC ADC ADC ADC ADC
6,5
R1
Byles per
Instruction
A
1l,Iu
R,
D
9
6,5
RR1
B
8
n,Ia
6,5
A
7
6,5
RBI
9
6
1R1
R1
!!!.
5
R1
IRB1
4
4
6,5
R1
3
3
DEC DEC ADD ADD ADD ADD' ADD ADD
BLC
2
6,5
2
3
______
,~
~,
________
~~~
________,J
2
~
~
3
Lower
Opcoc\e
Nibble
Execution
Cycles
_ Opcode
Upper _
Nibble
·2~byte
PlpeUne
Cycles
~O'5
A
Flnl
Operand
•
4
CP
,R2,R,
Mnemonic
Second
Operand
Legend:
R = 8·BII Address
r = 4·BII Address
Rl or rl = Dst Address
R2 or .. = Sro Address
Sequence:
Opcode, First Operand, Second Operand
Nole: The blank areas are not delined.
instruction; fetch cycle appears as a 3-byte instruction
8085·002
25
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The DC characteristics listed below apply for
the following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin.
Standard conditions are:
+5V
2.1K
o +4.75 V :5 Vee :5 +5.25 V
o GND = 0 V
o O°C :5 TA :5 +70°C
Figure 14. Tes! Load I
DC
Characteristics
26
Symbol
Parameter
Min
Max
Unit
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Vee
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VaH
Output !;Iigh Voltage
VOL
Output Low Voltage
IlL
Input Leakage
1m
Output Leakage
IJR
Ice
I
Condition
V
loH
= -250 p.A
0.4
V
loL
= +2.0 rnA
-10
10
p.A
0 Vs VIN s +5.25 V
-10
10
p.A
0 Vs VIN
Reset Input Current
-50
p.A
Vee =' +5.25 V, VRL = 0 V
Vee Supply Current
150
rnA
2.4
S
+5.25 V
AC Characteristics
External I/O
or Memory
Read and
Write Timing
Do-D70UT
Figure IS. External 110 or Memory Read/Wrile
No.
2
3
4
5
Symbol
Parameter
TdA(AS)
TdAS(A)
TdAS(DR)
Address Valid to AS t Delay
35
AS t to Address Float Delay
AS t to Read Data Required Valid
45
AS Low Width
55
TwAS
TdAz(DS)
Min
Max
Notes*tO
2,3
220
Address Float to DS ~
2,3
1,2,3
1,2,3
6-TwDSR
DS (Read) Low Width
0
185 - - - - - - - 1 , 2 , 3
7
TwDSW
TdDSR(DR)
DS (Write) Low Width
110
ThDR(DS)
Read Data to DS t Hold Time
DS t to Address Active Delay
0
45
2,3
DS t to AS ~ Delay
55
2.3
8
9
10
11
12 13
14
15
16
17
TdDS(A)
TdDS(AS)
DS ~ to Read Data Required Valid
.1,2,3
130
TdRJW(AS) - - RIW Valid to AS t Delay
TdDS(RIW)
I5S t to RIW Not Valid
1,2,3
30 - - - - - - - 2 , 3
35
2,3
TdDW(DSW)
Write Data Valid to DS (Write) ~ Delay
35
TdDS(DW)
45
TdA(DR)
DS t, to Write Data Not Valid Delay
Address Valid to Read Data Required Valid
TdAS(DS)
AS t to DS ~ Delay
55
2,3
2,3
255
1,2,3
2,3
NOTES:
I. When using extended memory timing add 2 TpC.
2. Timing numbers given are Jor minimum TpC.
3. See clock cycle time depelldent characteristics table.
2194·011
tTe.rtLoad I.
o All timing references use 2.0 V for a logic" 1" and 0.8 V for a logIc "0".
to All units in nanoseconds (ns).
27
AC Characteristics
Additional
Timing
Table
Figure 16. Additional Timing
No.
Symbol
Min
Parameter
Max
Notes*
1
TpC
Input Clock Period
80
1000
Clock Input Rise And Fall Times
15
TrC.TfC
TwC
Input Clock Width
26
1
3
70
2
Time Input Low Width
4
TwTinL
5-TwTinH--- Timer Input High Width - - - - - - - - - - - - - - - - 3 T p C - - - - - - - - 2
8TpC
2
6
TpTin
Timer Input Period
2
Timer Input Rise And Fall TimEls
100
7
TrTin. TfTin
70
8a TwIL
Interr~pt RequestInput Low Time
2.3
3TpC
Interrupt Request Input Low Time
8b TwIL
2.4
3TpC
Interrupt Request Input High Time
TwIH
9
2.3
2
NOTES:
1. Clock timing referencesuses3.8V for a logic "1" andO.8Vfor
a logic "0",
3. Interrupt request via Port 3 (P3j-P33)'
4. interrupt request via Port 3 (P3Q).
* Units in nanoseconds (ns).
2. Timing reference uses 2.0 V for a logic "1" and 0.8 V for
a 10gio"0".
Memory Port
Timing
AO-A10
~..
__________
A_DD_R_ES_S_VA_L_'D_ _ _ _ _ _ _ _ _
---Jr·
Do-D7
8
DON'T CARE
~.2i~
j
~
-'l~
~
DATA IN VALID
Figure 17. Memory Port Timing
No.
Symbol
Parameter
2
TdA(DI)
ThDI(A)
Address Valid to Data Input Delay
Data In Hold time
NOTES:
I. Test Load 2.
2. This is a Clock-Cycle-Dependent parameter. For clock frequencies
other than the maximum, use the follOWing formula: 5 tpc - 95
28
Min
Max
Notes*
320
1.2
o
*J1nits are n~no5ecortds unl~ss otherwise specified.
2194·012 2037·019
Handshake
Timing
o.: :~ ____________~_.
____~~~--------(OUTPUT)
Figure ISa. Input Handshake
~
DATA OUT
DAV
(OUTPUT)
RDY
(INPUT~
DATA OUT VALJD
=-~--=='~0~
Figure ISb. Output Handshake
No.
Min
Parameter
Symbol
Max
Notes"
o
TsDI(DAV)
Data In Setup Time
160
2
ThDI(DAV)
Data In Hold time
120
3
TwDAV
Data Available Width
4
TdDAVIf(RDY)
DAV Hnputto RDY ~Delay
120
1,2
5-TdDAVOf(RDY)-- DAV ~ Output to RDY ~ Delay - - - - - - - - - - - - - 0 - - - - ' - - - - - 1 ,3
6
7'
8
9
DAV i Input to RDY i Delay
DAV i Output to RDY i Delay
Data Out to DAV ~ Delay
Rdy ~ Input to DAV t Delay
TdDAVIr(RDY)
TdDAVOr(RDY)
TdDO(DAV)
TdRDY(DAV)
120
0
30
0
1,2
1,3
140
NOTES:
* Units in nanoseconds (ns).
1. Test load 1
2. Input handshake
3. Output handshake
t All timing references use 2.0 V for a logic "1" and 0.8 V for
a logic "0",
ClockCycle-Time- Number
Dependent
Characteristics
Symbol
Equation
TdA(AS)
TpC-50
2
TdAS(A)
TpC-40
3
TdAS(DR)
4TpC-llO*
4
TwAS
TpC-30
5--TwDSR--------------3TpC-65*--------------
TwDSW
TdDSR(DR)
10
Td(DS)A
II
TdDS(AS)
12--TdR/W(AS)
2TpC-55*
3TpC-120*
TpC-40
TpC-30
TpC-55------------
13
14
15
TdDS(RIW)
TdDW(DSW)
TdDS(DW)
16
TdA(DR)
TdAS(DS)
TpC-50
TpC-50
TpC-40
5TpC-160*
TpC-30
7
8
17
* Add 2TpC when using extended memory timing.
2194·013
29
'
"
Zilog
Product Specification
I
Z8671, Z8® MCU
with BASIC/Debug
Interpreter
June 1987
FEATURES
• The Z8671 MCU is a complete microcomputer
preprogrammed with a BASIC/Debug interpreter,
Interaction between the interpreter and its user is
provided through an on-board UART
III
BASIC/Debug can directly address the Z8671's internal
registers and all external memory. It provides quick
examination and modification of any external memory
location or I/O port.
III
The BASIC/Debug interpreter can call machine
language subroutines to increase execution speed.
II
The Z8671's auto start-up capability allows a program to
be executed on power-up or Reset without operator
intervention.
II!l
Single + 5V power supply-all I/O pins TIL-compatible.
II
8MHz
GENERAL DESCRIPTION
The Z8671 Single-Chip Microcomputer (MCU) is one of a
line of preprogrammed chips-in this case with a
BASIC/Debug interpreter in ROM-offered by Zilog. As a
member of the Z8 Family of microcomputers, it offers the
same abundance of resources as the other Z8
microcomputers.
TIMING
AND
CONTROL
PORT 0
(NIBBLE
PROGRAMMABLE)
110 or Aa~A15
PORT 1
110 OR ADc-ADl
r ----.
I
RESET
+5V
R/W
GND
os
XTAL1
As
XTAL2
POo
P20
PO,
P2,
po,
P2,
PO,
P2,
PO.
P2.
PO,
Z8671
P2,
PO,
MCU
P2,
PO,
P2,
Pl 0
P30
Pl,
P3,
P12
P3,
Pl,
P3,
Pl.
P3.
Pl,
P3,
Pl,
P3,
Pl,
P3,
Figure 1. Pin Functions
30
Because the BASIClDebug interpreter is already part of the
chip circuit, programming is made much easier. The Z8671
MCU thus offers a combination of software and hardware
that is ideal for many industrial control applications. The
Z8671 MCU allows fast hardware tests and bit-by-bit
examination and modification of memory location, I/O ports,
+5V
PORT 2
(BIT PRO·
GRAMMABLE)
110
P3,
XTAL2
P3,
XTAL1
P2,
P3,
P2,
P30
P2,
RESET
P2.
R/W
P2,
OS
P2,
!i.S
P2,
P3,
P20
GND
P3,
P3,
P3.
POo
AD,
PO,
AD,
PO,
ADs
PO,
AD,
PO,
AD,
PO,
AD,
PO,
AD,
PO,
ADo
Figure 2a. 40-pin Dual-In-Line Package (DIP),
Pin Assignments .
or registers. It also allows bit manipulation and logical
operations. A self-contained line editor supports interactive
debugging, further speeding up program development.
y .... '!v'"
~v (:{'~ q":;\ -¢'~ -¢"~ x~ q":/o <{I:," qtt.'\ 41,'0 q'}/'J
6
The BASICIDebug interpreter, a subset of Dartmouth
BASIC, operates with three kinds of memory: on-chip
registers and external ROM or RAM. The BASIC/Debug
interpreter is located in the 2K bytes of on-chip ROM.
Additional features of the Z8671 MCU include the ability to
call machine language subroutines to increase execution
speed and the ability to have a program execute on
power-up or Reset, without operator intervention.
Maximum memory addressing capabilities include 62K
bytes of external program memor'y and 62K bytes of data
memory with program storage beginning at location 800H.
This provides up to 124K bytes of useable memory space.
Very few 8-bit microcomputers can directly access this
amount of memory.
4
3
2
1 44 43 42 41 40
7
39
NC
R/W
8
38
P24
os
9
37
P23
AS
10
3.
P2,
P3,
11
35
P2,
GNO
12
34
P2.
P3,
13
33
P33
PO.
14
32
P3,
PO,
15
31
P17
PO,
16
30
Pl.
NC
17
29
PI,
Z8671
MCU
18 19 20 21 22 23 24 25 26 27 28
q~~ q~t.. q~" qC:{O qt::)'\ q....<:J q........ q"'l-
A > B = 001
.
lAOS> IRC3
1 = IRCJ > I R O S ,
A > B > C = 010
A> C > B = 011
LOON'TCARE
REGISTER
POINTER
~~ ~~
: ~ ~~~
B > A > C = 110
RESERVED = 111
IROO, IRQ2 PRIORITY (GROUP 5)
o=
IAQ2 > IROO
1 = IROO > IRQ2
IRQ1, IRQ4 PRIORITY (GROUP C)
IRQ1 > IRQ4
1 = IRQ4 > IRQ1
o : :;
-
R250lRQ
Interrupt Request Register
(FAH; Read/Write)
R254SPH
Stack Pointer
(FEH; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED (MUST BE O):::y--
c=
IROO
IRQ1
IRQ2
P32 INPUT (Do :: IRaO)
P331NPUT
P31 INPUT
IRC3
IRQ4
P30 INPUT, SERIAL INPUT
To"SERlAL OUTPUT
lAOS
T,
R2511MR
Interrupt Mask Register
(FBH; Read/Write)
I~I~I~I~!~I~I~I~I
II
c=
1 ENABLES IROO·IROS
(Do = IROO)
' - - - - - - - R E S E R V E D (MUST BE 0)
' - - - - - - - - 1 ENABLES INTERRUPTS
Figure 12. Control Registers (Continued)
44
R255SPL
Stack Pointer
(FFH; Read/Write)
OPCODEMAP
Lower Nibble (Hex)
o
7
8
9
A
B
C
o
E
10,5
ADD
R2,R,
10,5
ADD
IR2,R,
10,5
ADD
R"IM
10,5
ADD
1R"IM
6,5
LD
r"R2
6,5
LD
r2,R ,
12/10,5
DJNZ
r"RA
12/10,0
JR
cC,RA
6,5
LD
r"IM
12/10,0
JP
cC,DA
6,5
INC
r1
10,5
ADC
R2,R,
10,5
ADC
IR2,R,
10,5
ADC
R"IM
10,5
ADC
IR"IM
10,5
SUB
R2,R,
10,5
SUB
IR2,R,
10,5
SUB
R"IM
10,5
SUB
IR"IM
10,5
SBC
R2,R,
10,5
SBC
IR2,R,
10,5
SBC
R"IM
10,5
SBC
IR"IM
10,5
OR
R2,R,
10,5
OR
IR2,R,
10,5
OR
R"IM
10,5
AND
IR2,R,
10,5
AND
R"IM
10,5
OR
IR IM
"
10,5
AND
IR"IM
6,5
DEC
IR,
6,5
ADD
6,5
ADD
(1 J2
(1, lr2
6,5
RLC
R,
6,5
RLC
IR,
6,5
ADC
6,5
ADC
(, ,r2
'l, lr2
6,5
INC
R,
6,5
INC
IR,
6,5
SUB
6,5
SUB
(1·(2
(1. lr2
8,0
JP
IRR,
6,1.
SRP
1M
6,5
SBC
6,5
SBC
r1,r2
r1, lr2
8,5
DA
R,
8,5
DA
IR,
6,5
OR
6,5
OR
(1,r2
r1, lr2
10,5
POP
R,
10,5
POP
IR,
6,5
AND
6,5
AND
(1,(2
r1, lr2
10,5
AND
R2,R,
6,5
COM
R,
6,5
COM
IR,
6,5
TCM
(1,(2
6,5
TCM
r1, lr2
10,5
TCM
R2,R,
10,5
TCM
IR2,R,
10,5
TCM
R"IM
10,5
TCM
IR"IM
10/12,1
PUSH
R2
12/14,1
PUSH
IR2
6,5
TM
6,5
TM
r1,r2
r1, lr2
10,5
TM
R2,R,
10,5
TM
IR2,R,
10,5
TM
R"IM
10,5
TM
IR IM
"
10,5
DECW
RR,
10,5
DECW
IR,
12,0
LDE
rl, Jrr2
18,0
LDEI
Ir1,lrr2
9
6,5
RL
R,
6,5
RL
IR,
12,0
LDE
18,0
LDEI
(2, lrr 1
Ir2,1rr1
A
10,5
INCW
RR,
10,5
INCW
IR,
6,5
CP
6,5
CP
(1·(2
(1,1r2
2
"
6
6,5
DEC
R,
o
i
e.
5
2
7
:;;
.c
Z
OiQ. 8
Q.
:::>
I----
I--
I--
I---..
I--
I----
I----
I-6,1
01
I---6,1
EI
10,5
CP
R2,R,
6,5
CLR
R,
6,5
CLR
IR,
6,5
XOR
6,5
XOR
rl.r2
r1, lr2
C
6,5
RRC
R,
6,5
RRC
IR,
12,0
LDC
(1. lrr2
18,0
LOCI
Ir1.lrr2
0
6,5
SRA
R,
6,5
SRA
IR,
12,0
LDC
18,0
LOCI
(2. lrr1
Ir2,lrr1
20,0
CALL"
IRR,
E
6,5
RR
R,
6,5
RR
IR,
6,5
LD
r" IR 2
10,5
LD
R2,R,
F
8,5
SWAP
R,
8,5
SWAP
IR,
6,5
LD
B
F
10,5
XOR
R2,R,
10,5
CP
IR2,R,
10,5
CP
R"IM
10,5
XOR
IR2,R,
10,5
XOR
R"IM
10,5
LD
1R2,R,
~
10,5
CP
IR"IM
RET
I--
10,5
XOR
IR IM
"
10,5
LD
rl,x,R2
20,0
CALL
DA
10,5
LD
r2,x,Rl
10,5
LD
R IM
"
10,5
LD
IR IM
"
16,0
IRET
I---6,5
RCF
I-6,5
SCF
I-6,5
CCF
rs:o
10,5
LD
R2,IR ,
Ir1.(2
NOP
~'--------~'r~--------~~~'--------~'r~--------~~~'----------~'r~----------~#~~
2
2
3
3
Bytes per Instruction
LOWER
OPCODE
NIBtLE
EXECUTION
CYCLES
4
PIPELINE
CYCLES
MNEMONIC
Legend:
R = 8·bit address
r = 4-bit address
Al or (1 =: Ost address
R20rr2 = Src address
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
SECOND
OPERAND
NOTE: The blank areas are not defined.
• 2·byte InstrucliOn: fetch cycle appears as a 3·byte Instruction
45
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
toGND ......................... -0.3Vto +7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is 'a stress rating only;
operation of the device at ·any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.
Standard conditions are:
.. +4.75V';;Vee';; +5.25V
.. GND = OV
+5V
2.1K
-:
-:
Figure 13. Test Load 1
DC CHARACTERISTICS
Symbol
Parameter
VeH
Clock Input High Voltage
Vel
Clock Input Low Voltage
VIH
VIL
Input High Voltage
VRH
VRl
Condition
Min
Max
Unit
3.8
-0.3
Vee
0.8
V
Driven by External Clock Generator
Driven by External Clock Generator
2.0
-0.3
Vee
0.8
V
V
Reset Input High Voltage
3.8
V
Reset Input Low Voltage
-0.3
Vee
0.8
V
IOH
0.4
V
IOl = +2.0mA
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
2.4
V
V
=
-250/-lA
III
Input Leakage
-10
10
/-lA
OV"; VIN';; + 5.25V
IOL
Output Leakage
-10
10
/-lA
OV ";VIN';; + 5.25V
/-lA
mA
Vee = +5.25V, VRl = OV
IIR
Reset Input Current
-50
lee
Vee Supply Current
180
46
).
--®--I
~
PORT 0,
OM
K=
)(
16
J
PORT 1
)!
Ao-A7
~
<
•
1----0--
0
~I.
Ao-A7
PORT 1
---®--+-
){
'J:"
(WRITE)
~~
~
-®-I
00-07 OUT
I~I
OS
<
~~
~
CD
~~
OS
(READ)
}
-. 01-
-
'
\
Z8681/82 Z8®
ROMless MCU
June 1987
FEATURES
• Complete microcomputer, 24 I/O lines, and up to 64K
bytes of addressable external space each for program
and data memory,
III Full-duplex
•
iii Register Pointer so that short, fast instructions can
143-byte register file, including 124 general-purpose
registers, 3 I/O port registers, and 16 status and control
registers,
• Vectored, priority interrupts for I/O, counter/timers, and
UART.
•
UART and two programmable 8-bit
counter/timers, each with a 6-bit programmable
prescaler,
access ary one of the nine working-register groups,
rn
Single + 5V power supply-all I/O pins TTL compatible,
IS
Z8681/82 available in 8 MHz,
in 12 and 16 MHz.
Z8681 also available
On-chip oscillator that accepts crystal or external clock
drive,
GENERAL DESCRIPTION
The Z8681 and Z8682 are ROM less versions of the Z8
single-chip microcomputer, The Z8682 is usually more cost
effective. These products differ only slightly and can be
used interchangeably with proper system design to provide
maximum flexibility in meeting price and delivery needs,
-PORTO
(NIBBLE
PROGRAMMABLE)
110 OR Aa-A15
PORT 1
(BYTE
PROGRAMMABLE)
ADo-AD?
........
RESET
+5V
+5V
P3,
R/W
GND
XTAL2
P3,
os
XTALl
XTAL1
P2,
AS
XTAL2
P3,
P2,
PO,
,P2"
P3,
P2,
po,
po,
P2,
RESET
P2,
R/W
P2,
PO,
P2,
os
P2,
PO,
P2,
P2,
PORT 2
(BIT PRO,
GRAMMABLE)
110
AS
P2,
PO, Z8681182 P2,
P2,
PO,
MCU
P3,
P2,
GND
P3,
PO,
P2,
P3,
P3,
Pl,
P3,
PO,
Pl,
Pl,
P3,
PO,
Pl,
Pl,
P3,
PO,
Pl,
Pl,
P3,
PORT 3
SERIAL AND
PO,
Pl,
Pl,
P3,
PARALLEL 110
PO,
Pl,
Pl,
P3,
PO,
Pl,
Pl,
P3,
PO,
Pl,
Pl,
P3,
PO,
Pl,
,
Figure 1. Pin Functions
50
The Z8681 /82 offers all the outstanding features of the Z8
family architecture except an on-chip program ROM, Use of
external memory rather than a preprogrammed ROM
enables this Z8 microcomputer to be used in low volume
applications or where code flexibility is required,
AND CONTROL
Figure 2a. 40-pin Dual-In-Line Package (DIP),
Pin ASSignments
The Z8681 /82 can provide up to 16 output address lines,
thus permitting an address space of up to 64K bytes of data
or program memory. Eight address outputs (ADo-AD7) are
provided by a multiplexed, 8-bit, Address/Data bus. The
remaining 8 bits can be provided by the software
configuration of Port 0 to output address bits A s-A 15.
There are 143 bytes of RAM located on-chip and organized
as a register file of 124 general-purpose registers, 16 control
and status registers, and three I/O port registers. This
register file can be divided into nine groups of 16 working
registers each. Configuring the register file in this manner
allows the use of short format instructions; in addition, any of
the individual registers can be accessed directly.
Available address space can be doubled (up to 128K bytes
for the Z8681 and 124K bytes for the Z8682) by
programming bit 4 of Port 3 (P34) to act as a data memory
select output (OM). The two states of OM together with the
16 address outputs can define separate data and memory
address spaces of up to 64K/62Kbytes each.
The pin functions and the pin assignments of the
Z8681/82 40- and 44-pin packages are illustrated in
Figures 1 and 2. respectively.
"v'" ,,'1-
~v q";,~ q~'\.¢-~ .:¢~ x<"~
6
5
4
3
2
1
qfl;,'O
q~"" <:l"'\'\ q,,<;:J q....... q....""q''':J
Z8601/02
PROGRAM
MEMORY
(4K BYTES)
MCU
112 PORT 0 {
-=- ;-=- Figure 10. Port 0 Address Lines Tied to Logic 0
Port 2 bits can be programmed independently as input or
output (Figure 11). This port is always available for 1/0
operations. In addition, Port 2 can be configured to provide
~
open-drain outputs.
Z8681182
Like Port 0, Port 2 may also be placed under handshake
control. In this configuration, Port 3 lines P31 and P36 are
used as the handshake controls lines OAV2 and ROY 2. The
handshake signal assignment for Port 3 lines P31 and P36 is
dictated by the direction (input or output) assigned to bit 7 of
Port 2.
MCU
Port 3 can also provide the following control functions:
handshake for Ports 0 and 2 (OAV and ROY); four external
interrupt request signals (IROO-IR03); timer input and
output signals (TIN and TOUT) and Data Memory Select
(OM).
'This feature differs in the Z8681 and Z8682.
56
~
__
~
P20
PORT 2(110)
P27
-- 1
HANDSHAKE CONTROLS
DAV, AND RDY,
(P3, AND P3,)
Figure 11. Port 2
---
Port 3 lines can be configured as 1/0 or control lines (Figure
12). In either case, the direction of the eight lines is fixed as
four input (P30-P33) and four output (P34'P37). For serial 110,
lines P30 andP37 are programmed as serial in and serial
out, respectively.
----
.......-
Z8681182
PORT 3
(110 OR CONTROL)
MCU
Figure 12. Port 3
INTERRUPTS *
The Z8681/82 allows six different interrupts from eight
sources: the four Port 3 lines P30-P33' Serial In, Serial Out,
and the two counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask register
globally or individually enables or disables the six interrupt
requests: When more than one interrupt is pending,
priorities are resolved by a programmable priority encoder
that is controlled by the Interrupt Priority register.
All Z8681 and Z8682 interrupts are vectored through
locations in program memory. When an· interrupt request is
granted, an interrupt machine cycle is entered. This disables
all subsequent interrupts, saves the Program Counter and
status flags, and accesses the program memory vector
location .reserved for that interrupt. In the Z8681 , this
memory location and the next byte contain the 16-bit
address of the interrupt service routine for that particular
interrupt request. The Z8681 takes 26 system clock cycles
to enter an interrupt subroutine.
The Z8682 has a small internal ROM that contains six 2-byte
interrupt vectors pointing to addresses 2048-2065, where
3-byte jump absolute instructions are located (Figure 4 and
Table 1). These jump instructions each contain a 1-byte
opcode and a 2-byte starting address for the interrupt
service routine. The Z8682 takes 36 system clock cycles to
enter an interrupt subroutine.
Table 1. Z8682 Interrupt Processing
Hex
Contains Jump Instruction and
Address
Subroutine Address For
800-802
IRQO
803-805
IRQ1
806-808
IRQ2
809-80B
IRQ3
80C-80E
IRQ4
80F-811
IRQ5
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the interrupt
inputs can be masked and the Interrupt Request register
polled to determine which of the interrupt requests needs
service.
CLOCK
The on-chip oscillator has a high:gain, parallel-resonant
amplifier for connection to a crystal or to any suitable
external clock source (XTAL 1 = Input, XTAL2 = Output).
The crystal source is connected across XTAL 1 and XTAL2,
using the recommended capacitance (CL = 15 pf
maximum) from each pin to ground. The specifications for
the crystal are as follows: .
[J
AT cut, parallel-resonant
iii
Fundamental type
l1li Series resistance, Rs ~ 100Q
l1li For Z8682, 8 MHz maximum
II For
Z8681-12, 16 MHz maximum
Z8681/Z8682 INTERCHANGEABILITY
Although the Z8681 and Z8682 have minor differences, a
system can be designed for compatibility with both
ROM less versions. To achieve interchangeability, the design
must take into account the special requirements of each
device in the external interface, initialization, and memory
mapping.
External Interface. The Z8682 requires a 7.5V positive
logic level on the RESET pin for at least 6 clock periods
immediately following reset, as shown in Figure 13. The
Z8681 requires a 3.8V or higher positive logic level, but is
compatible with the Z8682 RESET waveform. Figure 14
shows a simple circuit for generating the 7.5V level.
+V
7.35 TO S.O V
VAL _ _ _
....Jlr----T"\-';--S
V--;;-IN------ : : :
4
6
MAX
MIN
.. ~r~~ ..... ~r~~-...
Figure 13. Z8682 RESET Pin Input Waveform
"This feature differs in the Z8681 and Z8682.
} - - -......- - I
7.35 - S.O V
Z8681
OR
RESET
Z8682
OPEN
COLLECTOR
TTL GATE
Figure 14. RESET Circuit
57
Initialization. The Z8681 wakes up after reset with Port 0
configured as an input, which means Port 0 lines are floating
in a high-impedance state. Because of this pullup or
pulldown, resistors must be attached to Port 0 lines to force
them to a valid logic level until Port 0 is configured as an
address port.
Port 0 initialization is discussed in the section on ports. An
example of an initialization routine for Z8681/Z8682
compatibility is shown in Table 2. Only the Z8681 need
execute this program.
Table 2. Initialization Routine
65536
FFFFH
APPLICATION
PROGRAM
2066
A.P. PROG START ADDRESS
2063
JP IR05
2060
JP IR04
2057
JP IR03
2054
JP IR02
2051
JP IR01
2048
JP IROO
Instruction
Z8682 VECTORS
JUMP INSTRUCTIONS
800H
7FFH
2047
Address Opcodes
812H
Comments
NOT USED
OOOC
E6 00 00
LDPO#%OO
Set Aa-A15 to O.
OOOF
E6 F8 96
LD P01M #%96
Configure Port 0 as
As-A15' Eliminate
extended memory
timing.
0012
800812
JP START
ADDRESS
Execute application
program.
21
15H
18
JP %0812
15
LO P01M #%96
12
LD PO #%00
10
IR05
} Z8681
INITIALIZATION
CH
IR04
IR03
Z8681
VECTORS
IR02
IR01
IROO
OH
Figure 15. Z8681/82 Logical Program Memory Mapping
58
Memory Mapping. The Z8681 and Z8682 lower memory
boundaries are located at 0 and 2048, respectively. A single
program ROM can be used with either product if the logical
program memory map shown in Figure 15 is followed. The
Z8681 vectors and initialization routine must be starting at
17FF
address 0 and the Z8682 3-byte vectors Uump instructions)
must be at address 2048 and higher. Addresses in the range
21-2047 are not used. Figure 16 shows practical schemes
for implementing this memory map using 4K and 2K RqMs.
6K
APPLICATION
PROGRAM
1015
1014
NOT USED
1000
FFF
CHIP SELECT
= (Al,
+
A11) . Al3 . A:; . A1s
4K
FFF
APPLICATION
PROGRAM
812
811
812
811
Z8682 VECTORS
800
800
7FF
2K
7FF
NOT USED
15
14
15
14
Z8681 VECTORS
AND INITIALIZATION
0
LOGICAL
MEMORY
PHYSICAL
MEMORY
a. Logical to Physical Memory Mapping for 4K ROM
FFF
APPLICATION
PROGRAM
CHIP SELECT
835
834
NOT USED
Al0
820
81F
As
= A11 . At; . A13 • A14
::::D---
As TO ROM
APPLICATION
PROGRAM
7FF
i-.,..
812
811
Z8682 VECTORS
800
7FF
NOT USED
15
14
Z8681 VECTORS
AND INITIALIZATION
LOGICAL
MEMORY
35
34
r-
r-
--
20
lF
12
11
PHYSICAL
MEMORY
b. Logical to Physical Memory Mapping for 2K ROM
Figure 16. Practical Schemes for Implementing Z8681 and Z8682 Compatible Memory Map
59
INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
IRR
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Symbols. The following symbols are used in describing the
instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "--': For
example,
dst +- dst
+ src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.
Flags. Control.Register R252 contains the following six
flags:
C
Z
S
V
o
H
Carry flag
Zero flag
Sigriflag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:
,0
1
*
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
CONDITION CODES
Value
Mnemonic
1000
Always true
0111
C
1111
NC
0110
1110
Z
1101
Carry
C = 1
No carry
C=O
Zero
Z = 1
NZ
Not zero
Z=O
PL
Plus
8=0
0101
MI
Minus
8 = 1
0100
1100
OV
Overflow
V= 1
NOV
No overflow
V=O
Z = 1
0110
1110
EQ
Equal
NE
Not equal
Z=O
1001
Greater than or equal
(8XORV) = 0
0001
GE
. LT
1010
0010
GT
LE
Less than
(8 XOR V) = 1
[ZOR(8XORV)] = 0
[ZOR(8XORV)] = 1
1111
UGE
Greater than
Less than or equal
Unsigned greater than or equal
0111
ULT
Unsigned less than
C = 1
1011
UGT
Unsigned greater than
(C = 0 AND Z = 0) = 1
0011
ULE
Unsigned less than or equal
(CORZ) = 1
0000
60
Flags Set
Meaning
Never true
C=O
INSTRUCTION fORMATS
-OP"""C---'
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
dst
INC r
'--1
OPC
One-Byte Instruction
CLR, CPL, DA, DEC,
'--"'=-=-----' OR 11 1 1 01 dst/"c 1
g~~~, ~~~R~~~~R:OP'
RRC, SRA, SWAP
I
OPC
I----'::':ds-=t'----lOR 11 1 1 01
Ace, ADD, AND, CP,
LD, OR, SSC, SUS,
TCM, TM, XOR
OR
OR
JP, CALL (Indirect)
dst
OR 111 1 01
ADC, ADD, AND, CP,
LD, OR, SSC, SUS,
TCM, TM, XOR
dst
SRP
OPC
VALUE
MODE
MODE
OPC
dst/src
src/dst
OPC
LD
OR
OR
src
dst
ADC, ADD, AND,
CP, OR, SSC, SUB,
TCM, TM, XOR
1 1 1 0
src
1 1 1 0
dst
LD
LD, LDE, LDEI,
LDC, LOCI
LD
L-""'::="'----' OR 11 1 1 01
cc
src
JP
OPC
DAu
DAL
LD
dst 1 OPC
VALUE
CALL
I
dst/CCR~ OPC
DJNZ, JR
Three-Byte Instruction
Two-Byte Instruction
Figure 17. Instruction Formats
INSTRUCTION SUMMARY
AddrMode
Instruction
and Operation
dst
src
Opcode
Byte
(Hex)
Flags Affected
C Z S V D H
o
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
C Z S V D H
ADC dst,src
dst - dst + src + C
(Note 1)
10
* * .... *
'it
DECdst
dst-dst - 1
R
IR
00
01
-***--
ADD dst,src
dst - dst + src
(Note 1)
00
* * * * 0 *
OECWdst
dst - dst - 1
RR
IR
80
81
-***--
ANDdst,src
dst - dst AND src
(Note 1)
50
-
8F
------
* * 0--
01
IMR(7)-0
CALLdst
DA
sp -sp - 2
IRR
@sp - PC; PC - dst
06
04
------
CCF
C-NOTC
EF
*-----
DJNZ r,dst
r-r - 1
ifrofO
PC - PC + dst
Range: + 127, -128
CLR dst
dst-O
R
IR
BO
B1
------
EI
IMR (7)-1
COMdst
dst - NOTdst
R
IR
60
61
-**0--
INCdst
dst -dst + 1
CPdst,src
dst - src
(Note 1)
AD
****--
DAdst
dst - DAdst
R
IR
40
41
***x--
RA
9F
R
IR
INCWdst
dst - dst + 1
-----rA
r=0 - F
RR
IR
-------
rE
-***-r=0 - F
20
21
AO
-***--
AI
61
INSTRUCTION SUMMARY (Continued)
Instruction
and Operation
Addr Mode Opcode
Byte
dst src
(Hex)
IRET
SF
FLAGS - @SP; SP- SP + 1
PC -@SP;SP-SP + 2; IMR (7)-1
OA
if cc is true
PC -dst
cD
c = 0- F
IRR
30
JR cC,dst
RA
cS
c = 0 - F
if cc is true,
PC-PC + dst
Range: + 127, -128
LD dst,src
dst -src
1m
R
r
X
rC
r8
r9
r= 0 - F
C7
X
r
07
R
E3
F3
E4
E5
E5
, E7
F5
C2
r
R
r
Ir
Ir
r
R
R
R
IR
IR
IR
R
1M
1M
LDCdst,src
dst -src
r
Irr
Irr
LDCI dst,src
dst-src
r-r + 1;rr-rr + 1
Ir
Irr
Irr
Ir
LDEdst,src
dst-src
r
Irr
Irr
LDEI dst,src
dst -src
r - r + 1; rr - rr + 1
Ir
Irr
Irr
Ir
******
RLC dst
L0=ciJ IRR
C
7
RRC dst
EO
E1
*** *
liil=fi:j}J IRR
CO
****
7
0
0
SBC dst,src
dst - dst - src - C
C1
(Note 1)
SCF
C-1
em Lrr'"
~ R
IR
1-----
DO
01
1m
SUBdst,src
dst - dst - src
03
3D
OF
SRPsrc
RP -src
C3
C Z S V D H
R
IR
7
C
SRAdst
Flags Affected
10
11
0
em LciJ
C
02
(Note 1)
31
20
SWAPdst I ~
R
.7~oIIR
FO
F1
TCM dst,src
(NOT dst) AND src
(Note 1)
50
TM dst,src
dstANO src
(Note 1)
70
XORdst,src
dst - dst XOR src
(Note 1)
SO
NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to theleh of the applicable addressing mode pair.
82
92
83
93
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.
FF
NOP
OR dst,src
dst - dst OR src
(Note 1)
POP dst
dst-@SP;
SP-SP + 1
R
IR
AddrMode
40
dst
PUSH src '
SP - SP - 1; @SP - src
RCF
src
50
51
Ir
R
70
IR
71
CF
C-O
RET
PC - @SP; SP - SP + 2
AF
RLdst
90
91
62
C Z S V D H
Instruction
and Operation
RR dst
JP cC,dst
Addr Mode Opcode
Byte
dst src
(Hex)
Flags Affected
0-----
R
R
R
IR
R
1M
IR
1M
Lower
Opcode Nibble
REGISTERS
R240sI0
Serial I/O Register
R244 TO
Counter/Timer 0 Register
(FOH; Read/Write)
(F4H; Read/Write)
L----SERIAL OATA(Oo::: LSB)
R241 TMR
Time Mode Register
R245 PREO
Prescaler 0 Register
(F1 H; Read/Write)
(F5H; Write Only)
-.J
NOl TO"
useDMODES
= 00 ]
~~ g~~
: ~~
INTERNAL CLOCK OUT
11
=
US~o.=
1
1
T MODES
EXTERNAL CLOCK INPnr
00
GATE INPUT = 01
10
=
11
TRIGGER INPUT
=
=
ENABLE To COUNT
~L
COUNTMODE
o = To SINGLE·PASS
1 = To MOOULO·N
RESERVED (MUST BE 0)
0
NO FUNCTION
1 ::: LOAD T,
0
DISABLE T, COUNT
=
(NON.R~~~~gci:~~:~i):::
NOFUNCTION
LOAD To
0 "" DISABLE To COUNT
=
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
1 = ENABLE 1, COUNT
(RETRIGGERABLE)
R242 T1
Counter Timer 1 Register
R246 P2M
Port 2 Mode Register
(F2H; Read/Write)
(F6H; Write Only)
R243PREl
Prescaler 1 Register
R247P3M
Port 3 Mode Register
(F3H; Write Only)
(F7H; Write Only)
~L
E~
COUNTMODE
1 ::: T, MODULO·N
o = T, SINGLE·PASS
CLOCK SOURCE
1 = T,INTERNAL
o=
T, EXTERNAL
TIMING INPUT
(TIN)
O1 PORT
2 PULL·UPS OPEN DRAIN
PORT 2 PULl·UPS ACTIVE
RESERVED (MUST BE 0)
o P32
1 P32
00
MoDe
P33
~~}
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
11
L
L
______~
_______
= INPUT
= ifiWOlRDYO
= INPUT
P33 = INPUT
RESERVED
P34
=
= OUTPUT
P34 =
1m
:~~ ~ ~:VUJR~~~ :~: ~ ~~~~~UT)
~ :~~ ~ ~N~~:l
L ________~
P3s = OUTPUT
P3s
RDYO/DAVO
IN
:~~~. ~~~~~TOUT
::=:~~ g~F
Figure 18. Control Registers
63
REGISTERS
R248 P01M
Port 0 Register
(F8H; Write Only)
(Continued)
-.J
po._po, MODE:]
OUTPUT", 00
INPUT", 01
R252 FLAGS
Flag Register
(FCH; Read/Write)
~-r
L po,-po,
'
~~ll§
MODE
00 "" OUTPUT
1X
EXTERNAl.
MEMORY TIMING
= Aa-All
.
STACK SELECTION
0 = EXTERNAL
=0
"EXTENDED = 1
NORMAL
1
LUSERFLAGF1
LUSER FLAG F2
HALF CARRY flAG
01 '" INPUT
A'2-A'5 = 1X
.
= INTERNAL
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
RESERVED (MUST BE 0)
CARRY FLAG
·ALWAYS EXTENDED TIMING AFTER RESET
R2491PR
Interrupt Priority Register
(F9H; Write Only)
R253 RP
Register Pointer
(FDH; Read/Write)
III . . . ". . ~"M
I~I~I~I~I~I~I~I~I
.~",m:J
II
IR03, IROS PRIORITY (GROUP A ) .
o := IR05 > IR03
, ::; IR03 > IR05
RESERVED
C > A> B
A > B > C
A > C> B
= 000
=
001
= 010
= 011
REGISTER
POINTER
~ ~ ~ ~ ~ ~ ~~~
IRao, IR02 PRIORITY (GROUP 8)
o ::;; IRQ2 > IRao
1 = IRao > IRQ2
B > A > C = 110
RESERVED = 111
IRQ1, IRQ4 PRIORITY (GROUP 0)
= IRQ1 > IRQ4
1 = IRQ4 > IRQ1
o
R250lRQ
Interrupt Request Register
(FAH; Read/Write)
R254SPH
Stack Pointer
(FEH; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED (MUST BE
o)=.r-
c==
= IROO)
IRao
P32 INPUT (Do
IRQ1
P331NPUT
IRQ2
P3, INPUT
P30 INPUT, SERIAL INPUT
IR03
IRQ4
IA05
To. SERIAL OUTPUT
T,
R2511MR
Interrupt Mask Register
(FBH; Read/Write)
R255SPL
Stack Pointer
(FFH; Read/Write)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~IDJ~I~I
II
c==
1 ENABLES IROO-IR05
(Do
= IROO)
' - - - - - - - RESERVED (MUST BE 0)
' - - - - - - - - - 1 ENABLES INTERRUPTS
Figure 18. Control Registers (Continued)
64
~I____ ~~;~~s~~~~~~R
LOWER
Z8681/82 OPCODE MAP
Lower Nibble (Hex)
o
3
4
5
"
e."
.!!
7
4
6,5
12/10,5
12/10,0
6,5
ADD
ADD
ADD
ADD
LD
LD
DJNZ
JR
LD
JP
INC
R1
'1"2
R2,R1
IR2,R1
R1,IM
IR1,IM
r1,R2
r2,R1
r1,RA
cC,RA
r1,IM
cC,DA
r1
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
IR 1,1M
10,5
10,5
R1
IR1
(1,r2
'1, lr2
R2,R1
IR2,R1
R1,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
(1,(2
(1, lr2
R2,R1
IR2,R1
R1,IM
IR1,IM
6,5
6,5
10,5
10,5
10,5
10,5
R1
IR1
8,0
6,1,
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRR1
1M
(1,r2
(1, lr2
R2,R1
IR2,R1
R1,IM
IR 1,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
IR),IM
R1
IR1
(1,r2
(1, lr 2
R2,R1
IR2,R1
R1,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
IR1,IM
R1
IR1
(1/2
'1.1r2
R2,R1
IR2,R1
R1,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R1
IR1
(1"2
'1, lr2
R2,R1
IR2,R1
R1,IM
IR 1,IM
10/12,1
12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
R2,R1
IR2,R1
R1,IM
IR1,IM
18,0
DECW
DECW
LDE
LDEI
RR1
IR1
(1, lrr2
Ir1,lrr2
6,5
6,5
12,0
18,0
RL
RL
LDE
LDEI
R1
IR1
'2,lr(1
Ir2,lfr1
F
10,5
6,5
'---
(1, lr2
E
6,5
6,5
(1, lr2
10,5
F
E
ADD
12,0
0
o
6,5
'1,(2
C
12/10,0
C
ADD
IR2
B
B
IR1
10,5
A
A
6,5
R2
9
9
DEC
10,5
:::l
8
6,5
Z
Do
7
DEC
,Q
,Q
!iDo 8
6
-
6.1
01
-
6,1
EI
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
INCW
INCW
CP
CP
CP
CP
CP
CP
RR1
IR1
(1/2
(1, lr2
R2,R1
IR2,R1
R1,IM
IR1,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R1
IR1
(1,f2
(1, lr2
R2,R1
IR2,R1
R1,IM
1R1,IM
-
~
10,5
6,5
6,5
12,0
18,0
10,5
RRC
RRC
LDC
LOCI
LD
R1
IR1
(1, lrr2
Ir1,lrr2
rl,x,R2
14,0
RET
IRET
-
6,5
RCF
-
6,5
6,5
12,0
18,0
20,0
20,0
10,5
6,5
SRA
SRA
LDC
LOCI
CALL"
CALL
LD
SCF
(2, lrr1
Ir2,1((1
IRR1
DA
'2,x,R,
R1
IR1
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
RR
LD
LD
LD
LD
LD
R2,R1
IR2,R1
R1,IM
IR1,IM
-----e.s
CCF
R1
IR1
r1, IR2
8,5
8,5
6,5
10,5
6,0
SWAP
SWAP
LD
LD
NOP
R1
IR1
1(1,(2
R2, IR 1
-
-----_v-..
......- - - -...v ..-----",1 . . . - - - -...oy-..---_-"J ......
2
------J~"__v____"
3
3
Bytes per Instruction
LOWER
OPCODE
NllLE
EXECUTION
CYCLES
PIPELINE
CYCLES
MNEMONIC
Legend:
R ~ 8-bit address
r = 4-bit address
At or (1 = Dst address
R2 or (2 = Src address
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
SECOND
OPERAND
NOTE: The blank areas are not defined.
'2-byte Instruction; fetch cycle appears as a 3-byte instruction
65
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins except RESET
with respectto GND ............... - 0.3V to + 7.0V
Operating Ambient
Temperature ............... See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
+5V
2.1K
Standard conditions are as follows:
Ell + 4. 75V ~ Vee ~ + 5.25V
iii GND = OV
III
ooe ~ TA ~
III
-40°C ~ TA ~ + 100°C for E (Extended temperature)
+ 70°C for S (Standard temperature)
Figure 19. Test Load 1
DC CHARACTERISTICS
Symbol
Parameter
VeH
Clock Input High Voltage
Vel
Clock Input Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VRH
Reset Input High Voltage
VRl
Reset Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
Min
Max
Unit
3.8
Vee
V
Driven by External Clock Generator
-0.3
0.8.
V
Driven by External Clock Generator
2.0
Vee
V
-0.3
0.8
V
3.8
Vee
V
-0.3
0.8
V
2.4
0.4
Condition
See Note
V
IOH
V
IOl
= - 25O IlA
= +2.0mA
III
Input Leakage
-10
10
IlA
OV .; VIN'; + 5.25V
IOl
Output Leakage
-10
10
Il A
OV .; VIN'; + 5.25V
IIR
Reset Input Current
-50
Il A
Vee
ICC
Vee Supply Current
150
mA
All outputs and I/O pins floating
=
+ 5.25V, VRl
'The Reset line (pin 6) is used to place the Z8682 in external memory mode. This is accomplished as shown in Figure 13.
66
= ov
J(
).
R/W
-®-I
~
PORT 0,
)(
).
DM
16
•
).
PORT 1
0
-<
Ao-A7
J
.... 01-
00-07 IN
-'J qn;,~.¢~ ..¢-trt= x~ qt')'O 4';/' q'l-'I. qt),'O 9.ft,~
5
4
3
2
1 44 43 42 41 40
39
NC
R/W
8
38
P2,
os
9
37
P2,
AS
10
36
P2,
35
P2,
34
P2,
13
33
P3,
14
32
P3,
PO,
15
31
P17
PO,
16
30
Pl,
NC
17
29
Pl,
P3,
11
GND
12
P3,
PO,
Z8691
MCU
18 19 20 21 22 23 24 25 26 27 28
qt::::>~ qt:Jb> A > B == 001
IROJ, IROS PRIORITY (GROUP A)
o ""
A ;. B > C ::;: 010
A > C ;. B = 011
IROS ;. IRQ3
1 = IRQ3 ;. IROS
REGISTER
POINTER
B ;. C ;. A = 100
C > B > A = 101
IRao, IRQ2 PRIORITY (GROUP B)
o '" IRQ2 ;. IROQ
1 ::; IROO;. IR02
B ;. A ;. C = 110
RESERVED = 111
IRQ1. IR04 PRIORITY (GROUP C)
o = IRQ1
> IR04
1 = IR04 > IRQ1
R250lRQ
Interrupt Request Register
R254SPH
Stack Pointer
(FAH; Read/Write)
(FEH; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED (MUST BE 0)
c=
I
IROO
IRQ1
P32 INPUT (Do
P331NPUT
IR02
P31 INPUT
IRQ3
IRQ4
IROS
T,
= IROO)
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
R2511MR
Interrupt Mask Register
R255SPL
Stack Pointer
(FBH; Read/Write)
(FFH; Read/Write)
I~I~I~I~I~I~I~I~I
I'
c==
I~I~I~I~I~I~I~I~I
1 ENABLES IRCO-IROS
(Do
IROO)
=
' - - - - - - - - RESERVED (MUST BE 0)
'---------1
ENABLES INTERRUPTS
Figure 13. Control Registers (Continued)
82
I~___ :~~~'~s~~!~~~R
LOWER
OPCODEMAP
Lower Nibble (Hex)
5
...
e...
6
2
3
4
6,5
10,5
10,5
10,5
6.5
6.5
DEC
DEC
ADD
ADD,
ADD
ADD
ADD
ADD
A,
lA,
'1·(2
(1,1r2
A2,A,
IA2,A,
R"IM
IA"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
AOC
AOC
AOC
AOC
ADC
ADC
IA"IM
A,
lA,
'1,(2
'1, lr2
R2,A,
IA2,A,
R"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR"IM
A,
lA,
'1,(2
'1, lr2
A2,A,
IA2,A,
R"IM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IAA,
1M
'1·(2
'l, lr2
A2,A,
IA2,A,
A"IM
IR"IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
OA
OA
OR
OR
OR
OR
OR
OR
IR"IM
R,
IR,
'1,'2
'1,1(2
A2,R,
IR2,R,
R"IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
R,
lA,
'1,(2
'l, lr2
R2,R,
IR2,R,
A"IM
IR"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R,
IR,
'1·(2
'l, lr2
A2,R,
iR2,R,
R"IM
IR"IM
10/12,1
12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
I
PUSH
PUSH
TM
TM
TM
TM
TM
TM
:;;
.a
A2
IA2
'1,(2
'l, lr2
R2,R,
IR2,R,
R"IM
IR"IM
10,5
10,5
12,0
18,0
~
OECW
OECW
LOE
LOEI
RR,
IR,
'1,lrr2
Ir1,lr(2
6,5
6,5
12,0
18,0
RL
RL
LOE
LDEI
R,
IR,
(2, lrr 1
Ir2.Ifr1
10,5
10,5
6,5
6,5
10,5
10,5'
10,5
10,5
INCW
INCW
CP
CP
CP
CP
CP
CP
RR',
IR,
'1,(2
'1,1(2
R2,R,
IR2,R,
R"IM
IR"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R2,R,
IR2,R,
R"IM
IR"IM
7
Z
a. 8
a.
::>
9
A
B
9
A
B
C
o
E
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
LO
LO
OJNZ
JR
LO
JP
INC
r"A2
r2,A,
r"AA
cC,AA
r"IM
cC,DA
rl
7
10,5
6.5
6,5
F
I--
f---
'----
--'--
-
-
6,1
01
6,1
EI
-
14,0
RET
-
16,0
IRET
R,
IR,
'1,'2
'1,1(2
6,5
6,5
12,0
18,0
10,5
6,5
RRC
RRC
LOC
LOCI
LO
RCF
R,
IR,
'1. lrr2
Ir1,1rr2
6,5
6,5
12,0
18,0
20,0
~
C
0
E
F
fl,X,R2
20,0
10,5
CALL
LO
DA
f2,X,Rl
SRA
SRA
LOC
LOCI
CALL'
R,
IR,
'2,1((1
1'2,lrrl
IRR,
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
RR
LO
LO
LD
LO
LO
A,
IR,
r" IR 2
R2,R,
IR2,R,
R"IM
IR"IM
8,5
8,5
6,5
SWAP
SWAP
R,
IR,
-
6,5
SCF
-
6,5
CCF
-
10,5
6,0
LO
LD
NOP
Ir1"2
R2,IR,
"'.". ----..v. ...-----'''' "'.". ----v-...----'" '-.. -----.. .
y-...- - - - - - " , ;
3
2
~'---....----'"
3
Bytes per Instruction
LOWER
OPCODE
NlllE
EXECUTION
CYCLES
PIPELINE
CYCLES
MNEMONIC
legend:
R = 8-bit address
r = 4·bit address
R1 or r1 = Dst address
R2 or'2 = Src address
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
SECOND
OPERAND
NOTE: The blank areas are not defined.
*2-byte instruction; fetch cycle appears as B 3·byte instruction
83
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins except RESET
with respect to GND ............... -0.3Vto + 7.0V
Operating Ambient
Temperature. , .............See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CON DITIONS
+5V
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
2.1K
Standard conditions are as follows:
•
-+- 4.75V'" Vee'"
1'1 GND
+ 5.25V
= OV
+ 70°C for S (Standard temperature) .
40°C ... TA'" + 100 °C for E (Extended temperature)
• O°C'" TA'"
-
•
Figure 14. Test Load 1
DC CHARACTERISTICS
Symbol
Parameter
VeH
Clock Input High Voltage
Vel
Clock Input Low Voltage
VIH
Min
Max
Unit
Condition
3.8
Vee
V
Driven by External Clock Generator
-0.3
0.8
V
Driven by External Clock Generator
Input High Voltage
2.0
Vee
V
Vil
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRl
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
2.4
0.4
V
IOH = - 250,.,A
V
IOL = +2.0mA
VIN = OV, 5.25V
III
Input Leakage
-10
10
,.,A
IOL
Output Leakage
-10
10
,.,A
VIN = OV,5.25V
IIR
Reset Input Curre~t
-50
,.,A
Vee = + 5.25V, VRL = OV
lee
Vee Supply Current
180
mA
All outputs and 1/0 pins floating
84
R/W
K
X
~I
--®PORT 0,
OM
X
)(
•
PORT 1
)
Ao-AT
16
CD
•
•
I~
PORT 1
~I.
Ao-A7
•
CD
](
00-0, OUT
~I
I---®----I
\t"
(WRITE)
.y
-®--
X
OS
,
~
0
-@------~
(READ)
<
...... 01......
...-(!)- ~
os
}
00-07 IN
)
CD
.,11
Figure 15. Extemall/O Dr Memory Read/Write Timing
AC CHARACTERISTICS
External 1/0 or Memory Read and Write Timing
Number
Symbol
Parameter
8MHz
Min
Max
12MHz
Min
Max
1
TdA(AS)
Address Valid to AS t Delay
50
35
2
TdAS(A)
AS t to Address Float Delay
70
45
3
TdAS(DR)
AS t to Read Data Required Valid
4
TwAS
AS Low Width
80
55
5
TdAz(DS)
Address Float to DS ~
0
0
6
TwDSR
DS (Read) Low Width
250
185,
7
TwDSW
DS (Write) Low Width
160
8
TdDSR(DR)
DS ~ to Read Data Required Valid
360
2,3
2,3
220
1,2,3
2,3
1,2,3
1,2,3
110
130
200
Notes·tO
1,2,3
ThDR(DS)
Read Data to DS t Hold Time
0
0
10
TdDS(A)
DS t to Address Active Delay
70
45
2,3
11
TdDS(AS)
DS t to AS ~ Delay
70
55
2,3
12
TdRIW(AS)
R/W Valid to AS t Delay
50
30
2,3
13
TdDS(R/W)
DS t to RIW Not Valid
60
35
2,3
14
TdDW(DSW)
Write Data Valid to DS (Write) ~ Delay
50
35
2,3
15
TdDS(DW)
DS t to Write Data Not Valid Delay
60
35
16
TdA(DR)
Address Valid to Read Data Required Valid
17
TdAS(DS)
AS t to DS ~ Delay
9
NOTES:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. See clock cycle time dependent characteristics table.
80
2,3
255
410
55
1,2,3
2,3
• All units in nanoseconds (ns).
t Test Load 1
o
All timing references use 2.0V for a logic" 1" and 0.8V for a logic "0".
85
Figure 16. Additional Timing
AC CHARACTERISTICS
Additional Timing Table
8MHz
Number Symbol
Parameter
Min
Max
Min
125
1000
83
TpC
Input Clock Period
2
TrC,TfC
Clock Input Rise and Fall Times
3
TwC
Input Clock Width
25
37
Notes·
1000
15
70
4
TwTinL
Timer Input Low Width
100
70
2
5
TwTinH
Timer Input High Width
3TpC
3TpC
2
6
TpTin
Timer Input Period
8TpC
7
TrTin,TfTin
Timer Input Rise and Fall Times
8A
TwlL
Interrupt Request Input Low Time
100
88
TwlL
Interrup,t Request Input Low Time
9
TwlH
Interrupt Request Input High Time
NOTES:
1. Clock timing references use 3.BV for a logic "1" and O.BV for a logic "0".
2. Timing references use 2.0V for a logic "1" and O.BV for a logic "0".
3. ,Interrupt request via Port 3.
4. Interrupt request via Port 3 (P31·P33)
5. Interrupt request via Port 3 (P30)
• Units in nanoseconds (ns).
86
12MHz
Max
.8TpC
100
2
100
2
70
2,4
3TpC
3TpC
2,5
3TpC
3TpC
2,3
DATA IN
DATA IN VALID
------",'
DAV
(INPUT)
RDY
(OUTPUT)
Figure 17a, Input Handshake Timing
DATA OUT
DATA OUT VALID
DAV
(OUTPUT)
RDY
(INPUT)
Figure 17b', Output Handshake Timing
AC CHARACTERISTICS
Handshake Timing
Number
2
Parameter
M,8MHZ M
M,12 MHz M
In
ax
TsDI(DAV)
Data In Setup Time
ThDI(DAV)
Data In Hold Time
0
230
175
0
160
120
Symbol
3
TwDAV
Data Available Width
4
TdDAVlf(RDY)
DAV ~ Input to RDY ~ Delay
5
TdDAVOf(RDY)
DAV ~ Output to RDY ~ Delay
6
TdDAVlr(RDY)
DAV t Input to RDY t Delay
7
TdDAVOr(RDY)
DAV t Output to RDY t Delay
8
TdDO(DAV)
Data Out to DAV ~ Delay
9
TdRDY(DAV)
Rdy ~ Input to DAV t Delay
In
ax
120
175
175
0
50
0
200
120
0
30
0
1,2
1,3
0
0
Notest*
1,2
1,3
140
NOTES:
1. Test load 1
2. Input handshake
3. Output handshake
,
t All timing references use 2.0V for a logic "1" and O.BV for a logic "0".
* Units in nanoseconds (ns).
87
CLOCK CYCLE TIME·DEPENDENT
CHARACTERISTICS
Symbol
8MHz
Equation
12MHz
Equation
TdA(AS)
TpC-75
TpC-50
2
TdAS(A)
TpC-55
TpC-40
3
TdAS(DR)
4TpC-140*
4TpC-110*
Number
4
TwAS
6
TwDSR
TpC-45
TpC-30
3TpC-125*
3TpC-65*
7
TwDSW
2TpC-90*
2TpC-55*
8
TdDSR(DR)
3TpC-175*
3TpC-120*
10
Td(DS)A
TpC-55
TpC-40
11
TdDS(AS)
TpC-55
TpC-30
12
TdR!W(AS)
TpC-75
TpC-55
TpC-50
13
TdDS(RIW)
TpC-65
14
TdDW(DSW)
TpC-75
TpC-50
15
TdDS(DW)
TpC-55
TpC-40
16
TdA(DR)
5TpC-215*
5TpC-160*
17
TdAS(DS)
TpC-45
TpC-30
* Add 2TpC when using extended memory timing
88
April 1988
Z86C08 CMOS Z8
MICROCONTROllER
FEATURES:
•
Complete microcomputer with 18-pin package, 14
I/O lines, and 2K bytes of on-chip ROM.
e 142-byte register file, including 124 general purpose
8-bit registers, 3 I/O port registers, and 15 status
and control registers.
6)
Two programmable 8-bit counterltimers, each with a
6-bit programmable prescaler.
(') On-chip osillator that accepts a crystal or external
clock drive.
•
Two analog comparators.
•
Register pointer so that short fast instructions
access anyone of the eight working register groups
o
Internal power on reset.
(!)
Standby modes - HALT and STOP.
@
12 MHz
o
CMOS process.
o 2 Volt "BROWN OUT" protection.
GENERAL DESCRIPTION:
The Z86C08 is a 2K ROM version of the Z8 single-qhip
microcomputer housed in an 18-pin DIP. It offers all the
outstanding features of the Z8 family architecture in a
low cost plastic DIP for price and size sensitive designs.
Flexible 1/0 with low power (15mA max, 2mA HALT,
10uA STOP) operation make this an ideal microcompLiter for hand-held and consumer applications. It has Instruction compatibility with the entire Z8 family for easy
software migration.
GND
Vee
P24
P23
18
XTALIN
P20
P25
P22
17
XTALOUT
P21
3
P26
P21
16
P31/Anl
P22
4
P27
P20
15
P32IAn2
P23
5
Vee
GND
14
P33IREF
P24
6
XTALOUT
P02
13
POD
P25
7
XTALIN
POl
12
P01
P26
8
P31/An1
POD
11
P02
P27
9
P32IAn2 P33IREF
10
Figure 1. Pin Functions
Figure 2. Pin Assignments
89
PIN DESCRIPTION:
ARCHITECTURE:
POO-P02 • I/O Port lines (inputs/outputs, CMOS compatible). The three lines of Port 0 are programmable as inputs
or outputs on a group basis (Figure 3).
Z86C08 architecture is characterized by a flexible I/O
scheme, an efficient register and address space structure
and a number of ancillary features that are helpful in many
applications (Rgure 3).
Microcomputer applications demand powerful 110 capabilities. The Z86C08 fulfills this with 14 pins dedicated to
input and output. These lines are grouped into three I/O
ports which are configurable under software control.
Two basic address spaces are available: program memory
and the internal register file. The register file is composed
of 124 general purpose 8-bit registers, three 110 port registers, and 15 control and status registers.
To unburden the program from coping with real-time
problems two counterltimers with a large number of userselectable modes are offered on-chip.
P2u-P~. I/O Port lines (inputs/outputs, CMOS compatible). The eight lines of Port 2 are programmable as inputs
or outputs on a line by line basis (Figure 3).
I
P31-P33 • Input Port lines (inputs, CMOS compatible).
The three lines of Port 3 are programmable as digital or
analog comparator inputs on a group basis (Figure 3).
XTAL IN, XTAL OUT. Crystal In, Crystal Out (time-base
input and output): These pins connect a parallel-resonant
crystal (12 MHz maximum) or an external single-phase
clock (12 MHz maximum) to the on-chip clock oscillator
and buffer.
ADDRESS SPACES:
Program Memory. The program counter addresses 2K
bytes of program memory space as shown in Rgure 4.
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts.
Register File: The register file indudes three 110 port registers , 124 general purpose registers (R4 - R127), and 15
control registers (R240 - R255). These
registers are aSSigned the address locations shown in
Figure 5.
I/O
(BIT PROGRAMMABLE)
Instructions can access registers directly or indirectly with
an 8-bit address field. The Z86C08 also allows short 4-bit
register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the register file is
divided into eight working register groups, each occupying
16 contiguous locations. The Register Pointer addresses
the starting location of the active working-register group
(Figure 6).
STACKS. An 8-bit Stack Pointer (R255) is used for the
internal stack that resides within the 124 general purpose
registers (R4 - R127).
I/O
Figure 3. Functional Block Diagram
90
C.OUNTER/TIMERS:
I/O PORTS:
The ZS6COS contains two S-bit programmable counterl
timers (TO and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by
internal or external clock sources; however, the TO prescaler is driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrementthe value (1 to 256) that
has been loaded into the counter. When the counter
reaches the end of count, a timer interrupt request - IR04
(TO) or IR05 (T1) - is generated.
The counters can be started, stopped, restarted to continue, or restarted from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode). The
counters, but not the prescalers, can be read at any time
without disturbing their value or count mode.
The clock source for T1 is user-definable and can be
retriggerable or non-retriggerable, or a gate input for the
internal clock.
The ZS6COS has 14 lines dedicated to input and output.
These lines are grouped into three ports and are configurable as input or output. All ports have active pull-ups and
pull-downs compatible with CMOS loads.
Port 0 can be programmed on either inputs or outputs. The
configuration is shown in Figure 7.
Port 2 bits can be programmed independently as input or
output. In addition, Port 2 can be configured to provide
open-drain outputs. The configuration is shown in Figure S.
Port 3 lines can be configured as digital inputs, analog
inputs, or control lines. In all cases, the direction of these
three lines is fixed as inputs.
Port 3 can also provide the following control functions:
four external interrupt request signals (IROO, IR01, IR02
and IR03) or timer input signal (TIN). The configuration of
Port 3 is shown in Figure 9.
IDENTIFIERS
LOCATION
20411 . . . . - - - - - - - - - ,
LOCATION Of
FIRST BYTE OF
'Ns::~gJi~~'::-b
AFTER RESET
12
11
ON·CHIP
ROM
255
STACK POINTER (BITS 7-0)
25'
RESERVt;O
'PL
RP
253
REGISTER POINTER
252
251
PROGRAM CONTROL FLAGS
FLAGS
INTERRUPT MASK AEGISTER
IMR
IRa
IPR
250
249
INTERRUPT REQUEST REGISTER
248
247
PORTS 0-1 MODE
P01M
PORT 3 MODE
P3M
246
245
244
PORT 2 MODE
P2M
TO PRESCALER
PREO
INTERRUPT PRIORITY REGISTER
TIMER/COUNTER 0
243
242
TIMER/COUNTER 1
241
TIMER MODE
___________ _
i-=-----::=------I
T1 PRESCAlER
T1
TMR
NOT
127
1----------------1
- -11----------------1
--I
IROS
IRoo
,•
IRoo
THE LOWER
NIBBLE OF
~~i~~C;:~~~~
11--'-PE-CI-FlE-a-w-aR-K-'NG-.--I
\
IRQ4
---1I
GENERAL· PURPOSE
REGISTERS
REGISTER GROUP
~~~r~~~~~~TION
....
1 - - - - - - - - - 1 POINTS TO THE
SPECIFIED
REGISTER.
IR02
'I>-
IRQ2
3
IRa1
IRQl
PORT2
IRoo
RESERVED
P3
P2
P1
PORTO
PO
IROO
Figure 4. Program Memory Map
Fi~ure
I
- - ( 1----------------1
IMPLEMENTED
IR04
INTERRUPT
VECTOR
(UPPER BYTE)
- -
TO
PRE1
IROS
10
INTERRUPT
VECTOR
(LOWER BYTE)
THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING·REGISTER GROUP.
4. Program Memory Map
PORT 3
Figure 5. Register File
Figure 5. Register File
--/1-----1
--I ,----"OPO.'5-----:'
Figure 6. Register Pointer
Figure 6. Register Pointer
91
INTERRUPTS:
The Z86C08 allows six different interrupts from five
sources: the three Port 3 lines P31 - P33, both the rising
and falling edge of P32 (AN2) , the falling edge of P31
(AN1) and P32 (REF - Figure 9), and the two counter!
timers. These interrupts are both maskable and prioritized. The Interrupt Mask Register globally or individually
enables or disables the six interrupt requests. When more
than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All Z86C08 interrupts are vectored through locations in
program memory. When an interrupt request is granted,
an interrupt machine cycle is· entered. This disables all
subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory vector
location reserved for that interrupt. This memory location
and the next byte contain the 16-bit address of the interrupt
service routine for that particular interrupt request.
Polled interrupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs
can be masked and the interrupt request register polled to
determine which of the interrupt requests needs service.
Interrupt sources and corresponding interrupts are shown
in Table 2.
STANDBY MODE:
The Z86C08 has two standby modes which are entered by
executing either:
•
•
STOP
HALT
The STOP instruction stops the internal clock and external
crystal oscillation; theHALT instruction stops the internal
clock but not crystal oscillation.
The STOP mode can be released by two methods. The
first method is a RESET ofthe device by removing Vec. The
second method is if P27 is configured as an input line when
the device executes the STOP instruction. A low input
condition on P27 releases the STOP mode. Program execution under both conditions begins at· location
%OOOC(HEX). However, when P27 is used to release the
STOP mode the I/O port mode registers are not reconfigured to their default power-on conditions. This prevents any
I/O, configured as output when the STOP instruction was
executed, from glitching to an unknown state.
The HALT mode is released by an interrupt on Port 3 input,
a time-out in Timer 0 or Timer 1, or by a RESET of the
device. To complete an instruction prior to entering standby
mode,use the instructions:
NOP
HALT or STOP
To use the P27 release approach with STOP mode, use the
following instructions:
OR P2,#%80
NOP
STOP
RESET:
Power-On Reset is in the Z86C08. The Z86C08 waits for 50
to 150 ms + 18 crystal clocks (Figure 10) while power is on,
and then jumps to the starting address %OOOC(HEX).
The control register Reset value is listed in Table 1.
J
1.S ( - ) 2.3V HYS'TD'ttSD3
.,.---+.......... -U~ ~
:EN
_ _ _-<.I.:7I...._.,....._ _ _ _ _
~L.RTCH
• NO H£S:IK LATO-I ON PZ7
Figure 7. ZS6COS Port 0 Configuration
92
Figure S. ZS6COS Port 2 Configuration
P2?
Table 1. Z86C08 Control Registers
86coa
control registers:
Addr. reg.
mDAT'"
L-------~~~~~r_------~~t_I::L~~
~Q
e,l.a"
:IRQ 3
F"~
EOGt: ~
= RDUNQ EDGE OCTECTION
Figure 9. Z86C08 Port 3 Configuration
Fl
T"R
00000000
F2
T1
UUUUUUUU
F3
PRE!
UUUUUUOO
F4
TO
UUUUUUUU
UUUUUUUO
F5
PREO
F6 •
Pl"
11111111
F7 •
F3M
UUUUUUOO
FB •
POlH
UUUOUU01
F9
IPR
UUUUUUUU
FA
IRQ
UUOOOOOO
OUUUUUUU
FB
'"R
FC
FLAGS
UUUUUUUU
FO
RP
00000000
FE
SPII
UUUUUUUU
FF
SPL
UUUU'UUUU
*
INT.
csc.
XTAL
Reset condition
Commments
Inputs after
Reset
IR03 is
used for
pas. edge
detection
Not used,
stack always
internal
Not reset after a low on P27 to get out of stop mode
Table 2. Interrupt Types, Sources, and Vectors
osc.
!
CHIP RESET
Figure 10. Internal Reset Configuration
Figure 10. Internal Reset Configuration
93
WATCH DOG TIMER (WDT):
WDT: 5F(HEX).
The crystal source is connected across XTAL IN and XTAL
OUT, using the recommended capacitors (Cl =15 pF) from
each pin to ground. The specifications for the crystal are
as follows:
CLOCK:
• AT cut, parallel resonant
The Watch Dog Timer (WDT) should be refreshed within
15 ms. If not refreshed, then the ZS6COS resets itself.
The on-chip oscillator has a high-gain, parallel-resonant
amplifier for connection to a crystal, ceramic resonator, or
to any suitable external clock source (XTAL IN = Input,
XTAL OUT = Output).
• Fundamental type, 12 MHz max
• Series resistance, RS.< 100 ohm
The oscillator configuration is shown in Figure 11.
XTALIN
- 5M Ohm
XTALOUT
1/2 O:IVlDER
XTAL.
CLOCK
SYSTEM CLOCK
Figure 11 . Z86COS Crystal Input Config.
PORT 3 COMPARATORS:
The S6COS's port 3 inputs include two analog comparators
for added interface flexibility. Interrupts are generated on
either edge of comparator 2's output, or on the falling edge
of comparator 1's output. The block diagram is shown in
Figure 9. , Comparator outputs may be used for interrupt
generation, Port 3 data inputs, or Tininthe case of AN1
(P31). Alternatively, the comparators may be disabled,
freeing the reference input (P33) for use as IRQ1 and/or
P33input.
94
The dual comparator (common inverting terminal) features a single power supply which discontinue.s power in
stop mode. The common voltage range is 0-4V; the power
supply and common mode rejection ratios are 90db and
60db, respectively. See comparator specifications for details (Page 16).
Typical applications for the on-board comparators include:
zero crossing detection, analog-to-digital conversion, voltage scaling, and threshold detection.
INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or. indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
IRR
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Symbols. The following symbols are used in describing the
instruction set.
dst
src
cc
@
- SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "+-': For
example,
dst +- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst (7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the following six
flags:
C
Z
S
V
o
H
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
H~lf-carry flag
Affected flags are indicated by:
o
1
..
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
CONDITION CODES
Value
Mnemonic
1000
Meaning
Flags Set
Always true
C
NC
Carry
No carry
C; 1
C;O
0110
Z
Zero
Z; 1
1110
NZ
Not zero
Z;O
1101
PL
Plus
8;0
0111
1111
0101
MI
Minus
0100
OV
Overflow
1100
NOV
0110
EQ
"-
8; 1
V; 1
No overflow
V;O
Equal
Z; 1
1110
NE·
Not equal
Z;O
1001
GE
Greater than or equal
(8XORV); 0
0001
LT
Less than
(8XORV); 1
1010
GT
Greater than
[Z OR (8XOR V)] ; 0
0010
1111
LE
Less than or equal
Unsigned greater than or equal
[Z OR (8 XORV)] ; 1
C;O
C;l
UGE
0111
ULT
Unsigned less than
1011
UGT
Unsigned greater than
(C ; 0 AND Z ; 0) ; 1
0011
ULE
Unsigned less than or equal
(CORZ); 1
0000
Never true
95
INSTRUCTION FORMATS
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC
dsl
OPC
INCr
One-Byte Instructions
CLR, CPL, DA, DEC,
L--=='----'
OR
11
1 1
01 dsl/sre I
~~~~'~~~Rl~~~R~OP,
1---=-----1
OR
L-_~_......J OR
RRC, SRA, SWAP
I
OPC
I--""":::d'--Sl::"""----j OR
11 1 1 0 I
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
1 1 1 0
1 1 1 0
dsl
JP, CALL (Indirect)
dsl
I----:-=",-c::----I OR
It
1 1 0
I
ADC, ADD, AND, CP,
LD, OR: SBC, SUB,
TCM, TM, XOR
dsl
SRP
OPC
VALUE
LD
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
LD
LD, LDC, LOCI
L----=-='---' OR
l'
LD
1 1
01
JP
sre
I
LD
dsl
OPC
VALUE
OPC
DAu
I
dSl/CCR~ OPC
CALL
DJNZ, JR
Three-Byte Instructions
Two-Byte Instructions
Figure 12. Instruction Formats
INSTRUCTION SUMMARY
AddrMode Opcode
Byte
dst src
(Hex)
Instruction
and Operation
Flags Affected
ADCdst,src
dst ~ dst + src + C
(Note 1)
10
* * * *
o
o
ADD dst,src
dst ~ dst + src
(Note 1)
00
* * * *
o
AND dst.src
dst ~ dst AND src
(Note 1)
50
-** 0
06
04
------
CALL dst
SP ~SP - 2
@SP ~ PC; PC
DA
IRR
~
C Z S V
DECdst
dst ~dst - 1
R
IR
00
01
-***--
*
DECWdst
dst ~dst - 1
RR
IR
80
81
-***--
8F
------
*-----
BO
B1
------
dst~O
R
IR
COM dst
dst~ NOTdst
R
IR
60
61
-**0--
(Note 1)
AD
DAdst
dsi~ DAdst
R
IR
40
41
96
01
IMR (7)
~O
DJNZ r,dst
RA
r~r-1
EF
CP dst.src
dst - src
Flags Affected
*
C~NOTC
CLRdst
AddrMode Opcode
Byte
dst src
(Hex)
H
dst
CCF
Instruction
and Operation
rA
r
------
- F
ifri'O
PC ~PC + dst
Range: + 127, -128
EI
9F
------
IMR(7)~1
7F
HALT
rE
INCdst
dst~dst
+ 1
r
R
IR
'" * * '"
***x--
=0
C Z S V 0 H
INCWdst
dst~ dst + 1
RR
IR
=0-
-***-F
20
21
AO
A1
-***--
INSTRUCTION SUMMARY (Continued)
Addr Mode Opcode
Byte
dst src
(Hex)
Instruction
and Operation
IRET
FLAGS <-- @SP; SP <-- SP + 1
PC <-- @SP; SP <-- SP + 2; IMR (7) <-- 1
JP cC,dst
OA
if cc is true
PC <-- dst
IRR
r
R
1m
R
CO
C1
SBC dst,src
dst <-- dst <-- src <-- C
3D
C
Ir
r
R
R
R
IR
R
1M
1M
1
1:0-::;:;::;:::::; R
SRP src
RP <--src
F5
C2
LOCI dst,src
dst <-- src
r <-- r + 1; rr <-- rr + 1
Ir
Irr
Irr
Ir
C3
LOE dst,src
dst <-- src
r
Irr
Irr
82
LOEI dst,src
dst <-- src
r<--r + 1; rr<--rr + 1
Ir
Irr
Irr
Ir
1m
1-----
31
6F
(Note 1)
20
R
FO
F1
TCM dst,src
(NOT dst) AND src
(Note 1)
60
TM dst,src
dstANOsrc
(Note 1)
70
SUB dst,src
dst <-- dst <-- src
SWAP dst I;
52
'C:::J--""-,-.:J'II R
L...
E7
'*
* .,.
DO
01
STOP
E3
C Z S V 0 H
***,*--
OF
~IR
F3
E4
E5
E6
R
(Note 1)
Flags Affected
'*
E1
0
SCF
C<--1
r8
r9
r= 0 - F
C7
Irr
X
**
X
-**0--
02
(Note 1)
5F -- -- -- -- -- -
WDT
03
(Note 1)
XORdst,src
dst <-- dst XOR src
BO
-
**
0 --
93
NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to the left of the applicable addressing mode pair.
FF
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.
92
NOP
83
40
R
50
IR
51
-**0--
AddrMode
dst
src
R
R
Lower
Opcode Nibble
Ir
PUSH src
SP <-- SP - 1; @SP <-- src
R
IR
70
71
RCF
C <-- 0
CF
RET
PC <-- @SP; SP <-- SP + 2
AF
r==I R
L.:..J~IR
90
RLCdst~R
10
r::1
C
RRC dst r=--===:l R
RR dst
rC
r
Irr
RL dst
LEJ L6J IRR
EO
~IR
07
r
Ir
Addr Mode Opcode
Byte
dst src
(Hex)
Instruction
and Operation
SRA dst
LOCdst,src
dst <-- src
POP dst
dst <--@SP;
SP <-- SP + 1
***
cB
X
ORdst,src
dst <-- dst OR src
* * *
c=O-F
x
IR
IR
C Z S V 0 H
cD
c=O-F
30
RA
JR cC,dst
if cc is true,
PC <-- PC + dst
Range: + 127, -128
LOdst,src
dst <-- src
BF
Flags Affected
1
0
IR
91
0-----
R
IR
R
1M
IR
1M
* * * * -.-
11
97
OPCODE.MAP
Lower Nibble (Hex)
-
A
B
C
o
E
F
A
6
B
C
o
_._- -- ----
I
65
6.5
65
DEC
DEC
ADD
1
R,
IR,
f,.r2
6.5
6.5
6.5
RLC
RLC
6.5
12110.5
ADD
ADD
ADD
ADD
LD
LD
DJNZ
JR
LD
JP
INC
Ir2
R2· R,
IR2 R,
R,IM
IR,.IM
f,.R2
f2· R ,
fl·RA
cC.RA
fl·IM
cC.DA
r1
6.5
10.5
10.5
10.5
10.5
ADC
ADC
ADC
ADC
ADC
ACC
IR,.IM
'0.5
105
10.5
6.5
12110 0
6.5
'21'0
O·
6.5
ADD
f,
10.5
E
65
j---- ..
R,
IR,
f,.r2
f,.lf2
R2· R,
IR2·R,
R,.IM
6.5
6.5
6.5
6.5
10.5
10.5
10.5
10.5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR,.IM
R,
IR,
r,.r2
f,.lf2
R2· R,
IR2·R,
R,.IM
8.0
6.1
6.5
6.5
10.5
10.5
10.5
10.5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRR,
1M
f,.r2
f,. lf2
R2· R,
IR2·R,
R,.IM
IR,.IM
8.5
8.5
6.5
6.5
10.5
10.5
10.5
10.5
DA
DA
OR
OR
OR
OR
OR
OR
IR,.IM
R,
IR,
f,.r2
f,. lf2
R2· R,
IR2·R,
R,.IM
10.5
10.5
6.5
6.5
10.5
10.5
10.5
10.5
POP
POP
AND
AND
AND
AND
AND
AND
R,
IR,
".r2
f,.lf2
R2· R,
IR2·R,
R,.IM
IR,.IM
6.5
6.5
6.5
6.5
10.5
'0.5
10.5
'0.5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R,
IR,
f,.f2
".lr2
R2· R,
IR2·R,
R,.IM
IR,.IM
10112.1
12/14.1
6.5
6.5
10.5
10.5
10.5
10.5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
R2
IR2
f,.r2
f,.lf2
R2·R1
IR2·R1
R,.IM
IR,.IM
...
-
I----
I----
I----
I---6.0
WDT
I---6.0
STOP
I---7,0
HALT
I----
10.5
10.5
CECW
DECW
RR,
IR,
6.5
6.5
RL
RL
6.1
01
~
EI
R,
IR,
10.5
10.5
6.5
6.5
10.5
10.5
10.5
10.5
14.0
INCW
INCW
CP
CP
CP
CP
CP
CP
RET
RR,
IR,
f,J2
".lf2
R2· R,
IR2·R,
R,.IM
IR,.IM
6.5
6.5
6.5
6.5
10:5
10.5
10.5
10.5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R1
IR,
f,.f2
f,. lf2
R2· R,
1R2·R,
R,.IM
IR"IM
--,;;-0
IRET
-
6.5
6.5
12.0
10.5
65
RRC
RRC
LDC
LOCI
LD
RCF
R,
IR,
fl·lrr2
Ir,. lrr2
f,.x.R2
6.5
6.5
18.0
20,0
20.0
SRA
SRA
LDC
LOCI
CALL·
CALL
LD
R,
IR,
f2· lfr ,
Ir2·1rr,
IRR,
DA
r2· x.R,
6,5
6.5
6,5
10.5
10.5
10.5
10.5
6.5
RR
RR·
LD
LD
LD
LD
LD
CCF
R,
IR,
rl· IA2
R2· R,
IR2·R,
R,.IM
IR"IM
12.0
18.0
-
~
SCF
10.5
-
-
8.5
8.5
6,5
10.5
60
SWAP
SWAP
LD
LD
NOP
R,
IR,
Jrp2
R2· IR ,
I..
..._ _ _ _.....
'V
...._ _ _ _.;J I....._ _ _ _...'V
...._ _ _ _...J I..
...- - - - -.....
'V
....-----..;J~"____v__"
3
Bytes per Instruction
LOWER
OPCODE
NlrE
EXECUTION
CYCLES
PIPELINE
CYCLES
MNEMONIC
Legend:
R = 8·bit address
r = 4·bit address
Ri or f1 = Dst address
R2 or f2 = Src a8dress
Sequence:
Opcode, Firsl Operand, Second Operand
FIRST
OPERAND
• 2·byte instruction; fetch cycle appears as a 3-byte instruction
98
SECOND
OPERAND
NOTE: The blank areas are not defined.
R241 TMR
TIMER MODE REGISTER
R245PREO
PRESCALER 0 REGISTER
(F1H; Read/Write)
(F5H; Write Only)
X
j
~~
~
TIN M O D E S ,
EXTERNAL CLOCK INPUT
=
00
o = NO FUNCTION
~I
1 = lOAD To
-
0 = DISABLE To COUNT
1 = ENABLE To COUNT
1 '" To MODUlO·N
X
0 : NO FUNCTION
1 - LOAD T,
GATE INPUT = 01
TRIGGER INPUT = 10
(NON·RETRIGGERABLE)
TRIGGER INPUT = 11
(AETRtGqEAABlE)
0 = OISABLE T, COUNT
- , = ENABLE T, COUNT
,
PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
R242 T1
COUNTER TIMER 1 REGISTER
R246P2M
PORT 2 MODE REGISTER
(F2H; Read/Write)
(F6H; Write Only)
Io.ID, I
COUNT MODE
0 = To SINGLE PASS
0,1 D. I D,I 0,1 D, I Dol
L
'
TI INITIAL VALUE (WHEN WRITTEN)
P2 o -P21 110 DEFINITION
' - - - - - - 0 DEFINES BIT AS OUTPUT
---(RANGE 1 256 DECIMAL 01 00 HEX)
1, CURRENT VALUE (WHEN READ)
1 DEFINES Bll AS INPUT
R243 PRE1
PRESCALER 1 REGISTER
R247P3M
PORT 3 MODE REGISTER
(F3H; Write Only)
(F7H; Write Only)
I~I~I~I~I~I~I~I~I
~L
I L. ~." ".".. ~,...'"
COUNTMODE
o=
1 PORT 2 PUll·UPS ACTIVE
T, SINGLE· PASS
1 = 1, MODUlO·N
CLOCK SOURCE
1 '" T, INTERNAL
1, EXTERNAL TIMING INPUT
(T'N) MODE
PORT 3 INTERRUPTS
o '"
o DIGITAL
1 ANALOG
PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
'------X
R244 TO
COUNTER/TIMER 0 REGISTER
(F4H: Read/Write)
To INITIAL VALUE (WHEN WRITTEN)
' - - - - - ( R A N G E ; 1 256 DECIMAL 01 00 HEX)
To CURRENT VALUE (WHEN READ)
NOTE: All "don't care" bits return a "1" when read.
Figure 16 Control Registers
99
R252 FLAGS
FLAG REGISTER
(FCH: Read/Write)
R248 P01M
PORT 0 AND 1 MODE REGISTER
(C8H: Write Only)
I~I~I~I~I~I~I~I~I
X T~L. POgoP~'~,?r~~T
l
U~ug
LUSERFLAGFl
LUSER flAG F2
01 '" INPUT
X
HALF CARRY flAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
,
MUSTBEO
ZERO FLAG
CARRY FLAG
R2491PR
INTERRUPT PRIORITY REGISTER
(F9H: Write Only)
R253 RP
REGISTER POINTER
(FOH: Read/Write)
I~!~!~!~'~:~~~I
• :J
IRC3, IROS PRIORITY (GROUP A)
o = IROS :> IRQ3
1 = IRQ) :> lAOS
IROO, IRQ2 PRIORITY (GROUP B)
= IR02 :> IROO
1 = IROO > IRQ2
I I III '""""'" .~"' . ~
RESERVED
C
-
o
'
:>
A
:>
:=
LOON'TeARE
000
B '" 001
_ A:> B > C =
A :> C :> B =
B ;> C :> A '::
c :> B :> A -
REGISTER
010
POINTER
011
100
101
B-> A :> C "" 110
RESERVED = 111
IRC1,IRQ4 PRIORITY (GROUP C)
o=
IRQl :> IRQ4
1 = IR04 :> IAQl
R250 IRQ
INTERRUPT REQUEST REGISTER
(FAH: Read/Write)
L
R255 SPL
STACK POINTER
(FFH: Read/Write)
1~1~1~1~1~[~1~1~1
I~I~I~I~I~I~I~I~I
RESERVED
T
IROO" P321NPUT
IROI _ P33 INPUT
IR02 _ P31 INPUT
IR03 " P32INPUT
IRQ4_ TO'
LI_ _ _ _
!R05_Tl
R2511MR
INTERRUPT MASK REGISTER
(FBH: Read/Write)
II
c==
1 ENABLES IRCQ-IAOS
(00 "" IROO)
' - - - - - - - - RESERVED
' - -_ _ _ _ _ _ _ 1 ENABLES INTERRUPTS
Figure 16 Control Re!ilisters (Continued)
100
~~;~~s~~~~:~A
LOWER
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... - O.3V to + 7.0V
Orerating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
StrEsses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating condilions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
+5 V
2.1K
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin (Figure 13)
Standard conditions are as follows:
III
+4.5 V <_ Vee <_ +5.5 V
GIl GND = OV
Figure 13 Test Load 1
DC CHARACTERISTICS
Symbol
Vee = 5.0 V +.10%
Parameter
Min
VeH
Vel
VIH
Vll
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Vee-0.2
-0.3
Vee-0.2
-0.3
Vee
Vss+O.2
Vee
Vss+O.2
V
V
V
V
VRH
VRl
VOH
VOl1
VOl2
RESET Input High Voltage
RESET Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Vee-0.2
-0.3
Vee-O.4
Vee
Vss+0.2
V
V
V
V
V
III
IOl
I'R
Icc
Iccl
lee2
Input Leakage
Output leakage
RESET Input Current
Supply Current
Standby Current
Standby Current
Typ
Max
Unit
0.4
0.8
-10
-10
-10
10
10
-50
15
2
10
uA
uA
uA
mA
mA
uA
Condition
Driven by external CG
Driven by External CG
IOH = -2.0mA
IOl =+4.0mA
IOl = + 12mA. 3 pins max.
VIN = OV. Vee
VIN = OV. Vec
Vee = 4.5 to 5.5V. VRl = OV. P27
All Output & 1/0 pins float
HALT Mode Vin= OV. Vcc
STOP Mode Vin = OV. Vee
101
CLOCK
TIN
Figure 14. Additional Timing
AC CHARACTERISTICS
NUmber
Symbol
Parameter
1
TpC
Input Clock Period
2
3
TrC, TfC
TwC
TwTinL
TwTinH
Clock Input Rise and Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width
TpTin
TrTin,Tffin
TwlL
TwlH
Timer Input Period
Timer Input Rise and Fall Times
Int. Resquest Input Low Time
Int. Request Input High Time
4
5
6
7
8A
9
Min
125
1
1
2
2
2
100
1. Clock timing references use Vee for a logic "1" .and Vssfor logic "0".
2. Timing references use Vee for a logic "1" and Vss for a logic "0".
3. Interupt request via P31- P33
4. Interrupt request via P31-P33
102
1
25
8TpC
100
3TpC
Notes
100,000
37
100
3TpC
NOTES:
·Units in nanoseconds (ns)
Max
2
2,4
2,3
PRELIMINARY Z86C08 COMPARATOR SPECIFICATIONS
S
Parameters
Offset
Voltage (mv)
Open. Loop
Gain (db)
CMRR (db)
PSRR (db)
Internal
Delay Time (us)
Overdri ve (mv)
CMR
(+)
CMR
(-)
CASE 1
VDD=2.5V
Temp=40C o
CASE 2
VDD=2.5V
Temp=85Co
CASE 3
VDD=5.5V
Temp=40Co
CASE 4
VDD=5.5V
Temp=85Co
CASE 5
VDD=5.0V
Temp=27Co
,
-+50
_+50 (est)
+25 (typ)
_+50 (est)
_+50 (est)
60 (min)
60 (min)
60 (min)
75 (typ)
60 (est)
60 (est)
60 (est)
60 (est)
70 (typ)
70 (est)
70 (est),
70 (est)
70 (est) I
80 (typ)
(est)
60 (min)
15 (max)
-+300
2.0 (max)
o
(min)
15 (max)
+300
-
1. (max)
+300
-
1.0(max)
-+300
2.0 (max)
4.5 (max)
4.5 (max)
(min)
0 (min)
0 (min)
1. 0 (max
1.0 (max)
4.125
0
I sia • (rna)
Power (mw)
0.1 (max)
0.25
0.1 (max)
0.25
Power Down
Yes
Yes
5.5
Yes
Yes
-
O.I(typ)
_+300
4.0 (max)
o
(min)
0.2 (typ)
1.25
Yes
103
ORDERING INFORMATION
Z86C08 CMOS Microcontroller
Z86C0808PSC 8MHz'
Z86C0812P~C 12MHz
Codes
First letter is for package; second letter is for temperature.
C = Ceramic DIP
P ;= Plastic DIP
L = Ceramic LCC
V = Plastic PCC
R
T
DIP
LCC
PCC
TEMPERATURE
S = OOCto +70°C
E = -40°C to +85°C
M*= -55°C to +125°C
FLOW
=
=
=
=
=
Proto pack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)
B = 883 Class B
J = JAN 38510 Class B
Example: PS is a plastic DIP, OOC to + 70°C.
PACKAGE DIMENSIONS
~:':~~:::::::I
0.300
r-0.320-
-I
B-1
I.'
2.325
.1
r - _.025-,
.015
0.025
11
0.030.
0.065-j]J..
-t--m
0920~
MAX
---l !---0.040
0.130
TTfNiffil¥mlr=
0.009
0
. 0 1 5III
.
•I
O.osa--' I-....-II-- 0.100----1
±.015
I I
0.018 II
TYP
I
0.003'
~
I--,
I
0.125
MIN
18·Pin Plastic Package
NOTE: Package dimensions are giv$n in inches. To convert to millimeters. multiply by 25.4:
104
Z86COO/C10/C20 CM OS
Z8@MCU
June 1987
FEATURES
III
Complete microcomputer, 2K (86COO), 4K (86Cl0), or 8K
(86C20) bytes of ROM, 124 bytes of RAM, and 22110 lines.
I!!I
144-byte register file, including 124 general-purpose
registers, four I/O port registers, and 14 status and
control registers.
Jill
Average instruction
maximum of 2.8 us.
L!J
Vectored,
priority
counter/timers.
execution
time
interrupts
of
for
1.5
I/O
us,
I:J
Register Pointer so that short, fast instructions can
access any of nine wO,rking-register groups in 1.0
us.
o
On-chip oscillator which accepts crystal,' external
clock drive, lC, ceramic resonator.
o
Standby modes - - Halt and Stop.
I1l
Single +5V
compatible.
I!!I
12 MHz.
and
III Two programmable 8-bit counter/timers, each with
a 6-bit programmable prescaler.
power supply
---'
all
pins
TTl-
IIlI CMOS process.
GENERAL DESCRIPTION
Z86C10/C20 microcomputer (Figures 1 and 2) introduces a
new level of sophistication to single-chip architecture.
Compared to earlier single-chip microcomputers, the
TIMING ( - RESET
AND
CONTROL
+5V
os
~M'{~
"M'm.....
XTALI
po.
po,
PO,
P03
XTAL2
Z86COO
MCU
PO.
Z86C10
Pl.
PO.
MCU
PI,
P2,
Z86C20
PI,
P22
MCU
P13
P23
Pl.
P2.
Pl.
P2.
Pl.
GND
P17
-+-
-I
CLOCK
-....
.....
PORT 3
--
PORT 1
......
.....
Figure 1. Pin Functions
Z86C10/C200ffers faster execution; more efficient use of
memory; more sophisticated interrupt, input/output and
bit-manipulation capabilities; and easier system expansion.
+5V
P3.
XTAL2
P3,
XTAU
P2,
RESET
P2.
os
P23
P3.
P2,
GND
P2,
PO•
P'7
PO,
Pl.
P02
P"
P03
Pl.
PO.
P13
PO.
P12
Pl •
PI,
Figure 2. Pin ASSignments
105
PIN DESCRIPTIONS
os. Oata Strobe (output, active Low). Data Strobe is
activated once for each memory transfer.
RESET. Reset (input, active Low). RESET initializes the
MCU. When RESET is deactivated, program execution
begins from internal program location OOOCH.
POo-POs, P1o-P17, P21-P2S, P31, P3s, P36.110 Port lines
(bidirectional, TTL-compatible). These 22 1/0 lines are
grouped in four ports that can be configured under program
control for I/O.
XTAL 1, XTAL2. Crystal 1, Crystal 2 (time-base input and
output). These pins connect a parallel-resonant
crystal to the on-chip .clock oscillator and buffer.
ARCHITECTURE
The MCU's architecture is characterized by a flexible I/O
scheme, an efficient register and address space structure,
and a number of ancillary features that are helpful in many
applications. (Figure 3).
Two basic internal address spaces are available to support
this wide range of configurations: program memoryand the
register file. The 144-byte random-access register file is
composed of 124 general-purpose registers, four I/O port
registers, and 14 control and status registers.
Microcomputer applications demand powerful I/O
capabilities. The MCU fulfills this with 22 pins dedicated to
input and output. These lines are grouped in four ports and
are configurable under software control to provide timing,
status signals, and parallel I/O.
To unburden the program from coping with real-time
problems such as counting/timing, two counter/timers with
a large number of user-selectable modes are offered
on-chip.
OUTPUT
a...~~;;.;;,;~ (8192 lor C20)
110
110
110
(BIT PROGRAMMABLE)
(BYTE PROGRAMMABLE)
Figure 3. Functional Block Diagram
STANDBY MODE
The Z86COO/C10/C20's standby modes are:
A reset input releases the standby mode.
• Stop
To complete an instruction prior to entering standby mode,
use the instructions:
• Halt
The Stop instruction stops the internal clock and clock
oscillation; the Halt instruction stops the internal clock but
not clock oscillation.
106
LD TMR, #00
NCP
STOP or HALT
ADDRESS SPACES
Program Memory. The 16-bit program counter addresses
4K or 8K bytes of program memory space as shown in
Figure 4.
Instructions can access registers directly or indirectly with
an 8-bit address field. The MCU also allows short 4-bit
register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the register file is
cjivided into nine working-register groups, each occupying
16 contiguous locations (Figure 6). The Register Pointer
addresses the starting location of the active working-register
group.
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain three 16-bit
vectors that correspond to the three available interrupts.
Register File. The 144-byte register file includes four I/O
port registers (Ro-R3), 124 general-purpose registers
(R 4-R 127) and 15 control and status registers (R241'R255).
These registers are assigned the address locations shown in
Figure 5.
Stacks. An 8-bit Stack Pointer (R255) is used for the internal
stack that resides within the 124 general-purpose registers
(R4-R127)'
4096
ON·CHIP
ROM
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED
AFTER RESET
:,;;
~------------
11
INTERRUPT
. VECTOR
(LOWER BYTE)
IRQ5
9
IRQ4
8
IRQ4
7
RESERVED
6
RESERVED
5f>'.
INTERRUPT
VECTOR
(UPPER BYTE)
IRQ5
10
4~
IRQ2
IRQ2
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
Figure 4. Program Memory Map
ID~NTIFIERS
LOCATION
255
STACK POINTER (BITS 7-0)
254
RESERVED
SPL
RP
253
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT REQUEST REGISTER
IRQ
249
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
P01M
247
PORT 3 MODE
P3M
246
PORT 2 MODE
P2M
245
TO PRESCALER
PREO
244
TIMER/COUNTER 0
243
T1 PRESCALER
242
TIMER/COUNTER 1
241
TIMER MODE
TO
THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING-REGISTER GROUP.
--I
- ....
PREl
T1
TMR
NOT
IMPLEMENTED
-
127
.... {
{
GENERAL·PURPOSE
REGISTERS
PORT 3
.... {
- .... {
- .... {
SPECIFIED WORKING·
REGISTER GROUP
-+1-
-
P3
PORT 2
P2
PORT 1
Pl
PORT 0
PO
Figure 5. Register File
127
THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER.
1
f----'/OPORTS----- 3
Figure 6. Register Pointer
107
COUNTER/TIMERS
The MCU contains two 8-bit programmable counterltimers
(To and T1), each driven by its own 6-bit programmable
prescaler. The T1 prescaler can be driven by internal or
external clock sources; however, the To prescaler is driven
by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IRQ4 (To) or
IRQ 5 (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass
mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode). The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode.
The clock source for T1 is user-definable and can be the
internal microprocessor clock
divided by
four, or an external signal input via Port 3. The Timer Mode
register configures the external timer input as an external
clock
, a trigger input that can be
retriggerable or non-retriggerable, or as a gate input for the
internal clock. The counterltimers can be programmably
cascaded by connecting the To output to the input of T1.
Port 3 line P36 also serves as a timer output (Tour) through
which To, T1 or the internal clock can be output.
I/O PORTS
The MCU has 22 lines dedicated to input and output
grouped in four ports. Under software control, the ports can
be programmed to provide address outputs, timing, status
signals, and parallel 110. All ports have active'pull-ups and
pull-downs compatible with TTL loads.
Port 0 can be programmed as an 1/0 port.
Port 1 can be programmed as a byte 1/0 port.
Port 2 can be programmed independently as input or
output and is always available for 1/0 operations. In addition,
Port 2 can be configured to provide open-drain outputs.
Port 3 can be configured as 1/0 or control lines. P3 1 is a
general purpose input or can be used for an external
interrupt request signal (IRQ2)' P35 and P36 are general
purpose outputs. P36 is also used for timer input (TIN) and
output (Tour) signals.
INTERRUPTS
The MCU allows three different interrupts from three
sources, the Port 3 line P31 and the two counter/timers.
These interrupts are both maskable and prioritized. The
Interrupt Mask register globally or individually enables or
disables the three interrupt requests. When more than one
interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All interrupts are vectored. When an interrupt request is
granted, an interrupt machine cycle is entered. This disables
all subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory vector
locations reserved for that interrupt. This memory location
and the next byte contain the 16-bit address of the interrupt
service routine for that particular interrupt request.
Polled interrupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs
can be masked and the Interrupt Request register polled to
determine which of the interrupt requests needs service.
CLOCK
The on-chip oscillator has a high-gain parallel-resonant
amplifier for connection to a crystal or to any suitable
external clock source (XTAL 1 = Input, XTAL2 = Output).
Crystal source is connected across XTAL 1 and XTAL2 using
the recommended capacitors (C1 '" 15 pf) from each pin to
ground. The specifications are as follows:
108
III AT cut, parallel resonant
• Fundamental type, 16 MHz maximum.
• Series resistance, Rs", 100 n
INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
IRR
Indirect register pair or indirect working-register
pair address
. Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Symbols. The following symbols are used in describing the
instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "<-': For
example,
dst <- dst
+ src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst (7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the following six
flags:
C
Z
S
V
o
H
Carry flag
Zero flag
Sign flag'
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:
o
1
*
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
CONDITION CODES
Value
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Mnemonic
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Meaning.
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
Flags Set
C= 1
C=O
Z= 1
Z=O
8=0
8= 1
V= 1
V=O
Z= 1
Z=O
(8XORV) = 0
(8 XOR V) = 1
[ZOR (8XOR V)] = 0
[Z OR (8 XOR V)] = 1
C=O
C= 1
(C = 0 AND Z = 0) = 1
(CORZ) = 1
109
INSTRUCTION FORMATS
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF
OPC
dsl
INCr
OPC
One-Byte Instructions
ClR, CPl, DA, DEC,
L--"'="----' OR 11 1 1 0 I dst/sre
I
ADC, ADD, AND, CP,
lD, OR, SBC, SUB,
TCM, TM, XOR
~~~~'~~~Rt~~~R~OP,.
RRC,SRA, SWAP
I
OPC
f---''''dS'':t---l OR 11 1 1 01
JP, CALL (Indirect)
dst
f---,,'::::':':::----l OR 11 1 1 0
I
ADC, ADD, AND, CP,
lD, OR, SBC, SUB,
TCM, TM, XOR
dst
SRP
OPC
VALUE
lD
OPC
dst
MODE
src
1-_-",sr",e_-1 °ORR
dst
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
I-'-'--'--T-='-l
lD
LD, LOC. LOCI
dst/src
ope
sre/dst
lD
OR 11 1 1 01
I
dst
OPC
VALUE
ope
cc
sre
JP
DAu
lD
CAll
I
dst/CCR~ OPC
DJNZ, JR
Two-Byte Instructions
Three-Byte Instructions
Figure 7. Instruction Formats
INSTRUCTION SUMMARY
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
C Z S V 0 H
ADCdst,src
dst - dst + src + C
(Note 1)
10
'It 'It 'It 'It
ADDdst,src
dst -- dst + src
(Note 1)
00
AND dst,src
dst -- dst AND src
(Note 1)
*
Instruction
and Operation
CP dst,src
dst - src
* * * * 0 *
5(:]
CALLdst
DA
SP--SP - 2
IRR
@SP -- PC; PC -- dst
CCF
C--NOTC
Flags Affected
C Z S V 0 H
(Note 1)
AD
****--
DAdst
dst-- DAdst
R
IR
40
41
* *' * X - -
-**0--
DECdst
dst--dst - 1
R
IR
00
01
-***--
D6
D4
------
DECWdst
dst--dst - 1
RR
IR
80
81
-***--
EF
*-----
8F
------
rA
r=O-F
------
0
CLR dst
pst--O
R
IR
BO
B1
------
COMdst
dst-NOTdst
R
IR
60
61
-**0--
110
AddrMode Opcode
Byte
(Hex)
dst src
01
IMR (7) +-: 0
DJNZ [,dst
RA
[-- [- 1
if
0
PC--PC + dst
Range: +127, -128
[*
INSTRUCTION SUMMARY (Continued)
Addr Mode Opcode
Byte
dst src
(Hex)
Instruction
and Operation
Flags Affected
C Z S V 0 H
Addr Mode
Instruction
and Operation
dst
src
Opcode
Byte
(Hex)
Flags Affected
C Z S V0 H
0-----
EI
IMR(7)+-1
9F
RCF
C-O
CF
HALT
7F
RET
PC-@SP;SP-SP + 2
AF
r===l R
L.:..J~IR
90
lci]:ciJ IRR
10
11
****--
LE:::jJ
R
IR
EO
E1
****--
L@:ciJ IRR
CO
C1
****--
INCdst
dst +- dst + 1
rE
r=O-F
RL dst
r::1
20
R
IR
21
RR
AO
A1
RLC dst
INCWdst
dst +- dst + 1
IR
,
RR dst LEi
IRET
SF
FLAGS +- @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR (7) - 1
JP cC,dst
ifcc is true
PC-dst
OA
cD
c=O-F
30
IRR
JRcc,dst
RA
if cc is true,
PC-PC + dst
Range: + 127, -128
cS
c=O-F
1m
R
LO dst,src
dst - src
R
rC
r8
r9
r
X
X
r
Ir
Ir
r
r=O-F
C7
07
E3
F3
R
R
E4
R
IR
E5
R
1M
E6
IR
IR
1M
R
E7
F5
LOCdst,src
dst - src
r
Irr
Irr
C2
LOCI dst,src
dst - src
r - r + 1; rr - rr
Ir
Irr
Irr
Ir
LOE dst,src
dst.,. src
r
Irr
Irr
LOEI dst,src
dst - src
r - r + 1; rr - rr
Ir
Irr
Irr
Ir
+
+
r
02
C3
03
1
82
92
83
C
* * * * '" '"
RRC dst
,
,
C
0
0
,
0
(Note 1)
SBC dst,src
dst -dst - src-C
OF
SRAdstLEi~
R
,
,
0
IR
DO
01
1m
SRP src
RP-src
STOp·
****--
3D
SCF
C-1
1-----
31
6F
(Note 1)
SUB dst,src
dst ..... dst - src
20
FO
F1
.TCM dst,src
(NOT dst) AND src
(Note 1)
60
TM dst,src
dstANO src
(Note 1)
70
XORdst,src
dst - dst XOR src
(Note 1)
SO
-**0--
NOTE: These instructions have an identical set of addressing modes.
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a D in this table. and its value is found in the
following table to the left of the applicable addressing mode pair.
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.
93
AddrMode
1
FF
NOP
91
OR dst,src
dst - dst OR src
(Note 1)
40
POPdst
dst-@SP;
SP-SP + 1
R
50
IR
51
dst
src
Lower
Opcode Nibble
Ir
PUSH src
SP +- SP - 1; @SP +- src
R
IR
70
71
R
R
R
IR
R
1M
IR
1M
111
REGISTERS
R244 TO
COUNTER/TIMER 0 REGISTER
(F4H; Read/Write)
TO INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VAlUE (WHEN READ)
R245PREO
PRESCALER 0 REGISTER
(F5H; Write Only)
R241 TMR
TIMER MODE REGISTER
(F1 H; Read/Write)
MODES
NOT To"
USED",
00
: ~~
INTERNAL CLOCK OUT", 11
j
~~o =~O
~
i~ g~~
FUNCTION
1 = LOAD
To
0 '" DISABLE To COUNT
1 '" ENABLE To COUNT
COUNT MODE
-. 0 = To SINGLE PASS
1 = To MODUlO·N
RESERVED
0 = NO FUNCTION
1 = LOAD T,
0
DISABLE T, COUNT
1 = ENABLE T, COUNT
T MODES
EXTERNAL CLOCK
= 00
GATE INPUT
01
INPOT
~l
=
=
(NON'R~~~g~:~~:~~ =
10 ,
TRIGGER INPUT", 11
.
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
(RETRIGGERABlE)
R242 T1
COUNTER TIMER 1 REGISTER
(F2H; Read/Write)
R246P2M
PORT 2 MODE REGISTER
(F6H; Write Only)
T, INITIAL VALUE (WHEN WRITTEN)
'----tRANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)
R243PRE1
PRES CALER 1 REGISTER
(F3H; Write Only)
R247P3M
PORT 3 MODE REGISTER
(F7H; Write Only)
I~I~!~I~I~I~I~I~I
~L
,
"
COUNTMODE
o = T, SINGLE·PASS
1
=
La
PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
Tl MODULO·N
CLOCK SOURCE
1 = T1 INTERNAL
0 = T, EXTERNAL TIMING INPUT
(TIN) MODE
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
D1~OD HEX)
' - - - - - - - RESERVED (must be 0)
Figure 11. Control Registers
112
REGISTERS (Continued)
R248P01M
PORT 0 AND 1 MODE REGISTER
R252 FLAGS
FLAG REGISTER
(~8H; Write Only)
(FCH; Read/Write)
po•• po, =MODE:]
00 --.J
OUTPUT
INPUT", 01
~~
L po,-po, MODE
1
ll!~~
L
00 '" OUTPUT
= INPUT
01
:':~P~::::E.(must
RESERVED
be
= I)
LUSER FLAG F1
=
10
11
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
00 = DYTE OUTPUT
01
USER FLAG F2
ZERO FLAG
BYTE INPUT
=} RESERVED
=
CARRY FLAG
R2491PR
INTERRUPT PRIORITY REGISTER
R253RP
REGISTER POINTER
(F9H; Write Only)
(FDH; Read/Write)
I~I~I~I~I~I~I~I~I
i :
I I III""""""'--~
LOON'TCARE
RESERVED = 000
IR03, IRCS
PR~O:IJ:d~~O::Q:)
.",om:] .
1 = IR03 > IROS
IRQO, IR02
PRIORITY (GROUP 0)
o = IRQ2 > IROO
1 = IRaQ:::. I R Q 2 '
,
~
~ ~ ~ ~~~
A>
B>
>
B>
C :::. B = 011
C > A = 100
C
REGISTER
POINTER
B > A = 101
A > C = 110
'RESERVED = 111
IRQ1, IRQ4 PRIORITY (GROUP C)
o = IRQ1 > IR04
1
= IRQ4 > IRQ1
R250lRQ
INTERRUPT REQUEST REGISTER
(FAH; Read/Write)
::r-II
I~I~I~I~I~I~I~I~I
RESERVED
I
IRQ2 = P31 Input
IRQ4 = To
IRQ5 = T,
R2511MR
INTERRUPT MASK REGISTER
R255SPL
STACK POINTER
(FBH; Read/Write)
(FFH; Read/Write)
I~I~I~I~I~I~I~I~I
II
c==
L.._ _ _ _ _ _
1 ENABLES lRaO-IROS
(Do
IROO)
=
RESERVED
L.._ _ _ _ _ _ _ 1 ENABLES INTERRUPTS
Figure 11. Control Registers (Continued)
113
OPCODEMAP
Lower Nibble (Hex)
o
DEC
DEC
~IR'
3
4
.
e.
"
".c
:c
6
7
Z
~
Co
Co
8
:>
9
ADD
ADD
r, r2
If,?
r,
ADD
R2· R ,
10.5
10.5
'0.5
6.5
ADD
IR2R,
ADD
R,IM
ADD
IR,IM
f,.R,?
65
6.5
65
105
10.5
10 5
10.5
RLC
IR,
ADC
f,.r2
ADC
,lr2
ADC
R2· R,
ADC
IR2 R,
ADC
R,.IM
ADC
IR,.IM
6.5
6.5
6.5
65
10 5
10.5
10.5
10.5
INC
R,
INC
IR,
SUB
SUB
f,.lr2
SUB
R2· R,
SUB
IR2·R,
SUB
R,.IM
SUB
IR,.IM
8.0
6.1
6.5
6.5
10 5
10.5
10.5
10 5
JP
IRR,
SRP
1M
SBC
f,.f2
SBC
f,. lr2
SBC
R2· R,
SBC
IR2·R,
SBC
R,.IM
SBC
IR,.IM
f, ,[2
f,
8.5
8.5
6.5
6.5
10.5
10.5
10.5
10.5
DA
R,
DA
IR,
OR
OR
f,. lr2
OR
R2· R,
OR
IR2·R,
OR
R,.IM
OR
IR,.IM
10.5
10.5
6.5
6.5
10.5
10.5
10.5
10.5
POP
R,
POP
IR,
AND
AND
f'·(2
f,. lr 2
AND
R2· R,
AND
IR2·R,
AND
R,.IM
AND
IR,.IM
6.5
6.5
6.5
6.5
10.5
10.5
10.5
10.5
COM
R,
COM
IR,
TCM
TCM
f,. lr2
TCM
R2· R,
TCM
IR2·R,
TCM
R,.IM
TCM
IR,.IM
10/12,1
PUSH
R2
12/14.1
PUSH
IR2
6.5
6.5
10.5
10,5
10.5
10.5
TM
TM
f,. lr2
TM
R2,R,
TM
IR2,R,
TM
R,.IM
TM
10.5
10.5
DECW
RR,
DECW
IR,
6.5
6.5
RL
R,
RL
IR,
f,.f2
f,.f2
f, ,r2
f1
C
o
E
12/10 a
65
f
RA
INC
rl
I
JR
LD
JP
Cc RA
f,.IM
cc DA
F
I
!
I
1---
I--------
r-----I--------
I--------
I
6,0
STOP
I-------7,0
HALT
61
01
r~
'EI
10,5
6,5
6.5
10.5
,0.5
10,5
10.5
INCW
IR,
CP
f,.f2
CP
(,. lr2
CP
R2,R,
CP
IR2·R,
CP
R,.IM
CP
IR,.IM
6,5
6,5
6.5
B
CLR
R,
CLR
IR,
XOR
F
DJNZ
a
I--------
10,5
E
-----
12110
IR"IM
INCW
RR,
0
LD
Rt
r,?
,-'-'2/10 5
.-
6.5
RLC
R,
A
C
LD
65
6.5
B
A
.-'65 -~-6:5i6565'105-
f,.f2
65
10 5
10.5
10.5
10.5
XOR
XOR
R2,R,
XOR
IR2,R,
XOR
R IM
"
XOR
IR"IM
f, ,lr2
6.5
6.5
12,0
18,0
RRC
R,
RRC
IR,
LDC
LOCI
Ir,.lrr2
f,.lrr2
I-------14
~
IRET
I-------6,5
10.5
f,
LD
x R2
6,5
6.5
12,0
18,0
20,0
20,0
SRA
R,
SRA
IR,
LDC
f2· lrr1'
LOCI
Ir2·lrr,
CALL'
IRR,
CALL
LD
DA
f2· x ,R,
RCF
~
10.5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
R,
RR
IRI
LD
r,.IR2
LD
R2,R,
LD
IR2·R,
LD
R,.IM
LD
8.5
8.5
6,5
10.5
SWAP
R,
SWAP
IR,
LD
Ir,.f2
LD
R2,IR,
a
RET
SCF
I-------6,5
CCF
IR"IM
---s-o
NOP
v...----.../'-...------v...-------"J~'__v____"
.......- - - -......'V...- - - -....II...
...- - - - - . .
2
3
Bytes per Instruction
LOWER
OPCODE
NI~LE
EXECUTION
CYCLES
UPPER
OPCODE - - i I > A
NIBBLE
PIPELINE
CYCLES
Legend:
R ~ 8·bil address
r = 4-bit address
R, orr,
MNEMONIC
R2
or f2
=
Dstaddress
= Src address
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
-2-byte Instruction. fetch cycle appears as a 3·byte Instruction
114
SECOND
OPERAND
NOTE: The blank areas are not defmed.
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... - 0.3V to + 7.0V
Orerating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
+5V
2.1K
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:
III
+4.5;5; Vee ;5; +5.5
III GND = OV
Figure 12. Test Load 1
DC CHARACTERISTICS
Symbol
Parameter
VCH
Clock Input High Voltage
VCl
Clock Input Low Voltage
VIH
Input High Voltage
Vil
Input Low Voltage
VRH
Reset Input High Voltage
VRl
Reset Input Low Voltage
VOH
Output High Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
Min
Typ
Max
Unit
Condition
3.8
. VCC
V
Driven by External Clock Generator
-0.3
0.8
V
Driven by External Clock Generator
2.0
VCC
V
-0.3
0.8
V
3.8
VCC
V
-0.3
0.8
V
2.4
V
Vee -100 mV
V
IOH
V
IOl = +2.0mA
0.4
IOH = -250/1A
= -1 OOIlA
III
Input Leakage
-10
10
/1 A
OV ~ VIN ~ + 5.25V
IOl
Output Leakage
-10
10
/1 A
OV ~ VIN ~ + 5.25V
IIR
Reset Input Current
-50
/1 A
VCC = + 5.25V, VRl =OV
ICC
Supply Current
2
mA
All outputs and 1/0 pins floating
ICCl
Standby Current
ICC2
Standby Current
5
10
mA
Halt Mode
/1 A
Stop Mode
NOTE:
Icc2 low power requires loading TMR (%F1)
with any value prior to stop execution.
Use sequence:
LD TMR, #01000.
Nap
STOP
115
Figure 14. Additional Timing
AC CHARACTERISTICS
Additional Timing Table
Z86C10
Number
Symbol
Paramete'r
TpC
Input Clock Period
2
TrC,TIC
Clock Input Rise and Fall Times
3
TwC
Input Clock Width
4
TwTinL
5
TwlL
Max
83
100,000
Notes'
15
Timer Input Low Width
70
70
2
Interrupt Request Input Low Time
70
2,3
NOTES:
1. Clock timing references use 3.8V for a logic "1" and O.BV for a logic "0':
2. Timing references use 2.0V for a logic "1" and O.BV for a logic "0':
3. Interrupt request via Port 3 .
• Units in nanoseconds (ns).
116
Min
Z86Cl1 CMOS
Z8® 4K ROM MCU
June 1987
FEATURES
m Complete microcomputer, 4K bytes of ROM, 256 bytes of
RAM, 32 I/O lines, and up to 6DK bytes addressable
external space each for program and data memory.
El Register Pointer so that short, fast instructions can
access any of 16 working-register groups in 1.5 !ls.
I!!)
On-chip oscillator which accepts crystal or external clock
drive.
C'.I
Standby modes-Halt and Stop
II! 256-byte register file, including 236 general-purpose
registers, four I/O port registers, and 16 status and
control registers.
(liJ
Vectored, priority interrupts for 110, counter/timers, and
UART.
I:'!l Full-duplex UART and two programmable 8-bit counter/
o Single + 5V power supply-all pins TIL-compatible.
13
12 MHz, 16 MHz
o CMOS process
timers, each with a 6-bit programmable prescaler.
GENERAL DESCRIPTION
The Z86C11 microcomputer (Figures 1 ~nd 2) introduces a
new level of sophistication to single-chip architecture.
Compared to earlier single-chip microcomputers, the
PORT 0
(NIBBLE
PROGRAMMABLE)
110 OR A 6-A15
!IO OR ADo-AD7
P3.
+5V
RfW
GND
XTAL2
P3,
os
XTAL1
XTAL1
P2,
AS
XTAL2
P3,
P20
PO,
P20
P30'
P2,
po,
po,
P2,
RESET
P2.
P2,
R/W
P2,
PO,
P2,
os
P2,
po.
P2.
AS
P2,
P2,
P3,
P20
P2,
GND
P3,
P2,
P3,
P3.
Pl,
P3,
PO,
Pl,
po,
po,
(BYTE
PROGRAMMABLE)
+5V
RESET
PO,
,PORT 1
Z86C11 offers faster execution; more efficient use of
memory; more sophisticated interrupt, input/output and
bit-manipulation capabilities; and easier system expansion.
Z86C11
MCU
Pl,
P3,
PO,
Pl.
Pl,
P3,
PO,
Pl,
Pl,
P3,
PO,
Pl.
Pl.
P3.
PO.
Pl,
Pl,
P3,
PO,
Pl,
Pl,
P3.
PO,
Pl,
PO,
P'o
Pl,
Figure 2. 40-pin Dual-In-line Package (DIP), Pin ASSignments
117
Under program control, the Z86C11 can be tailored to the
needs of its user. It can be configured as a stand-alone
microcomputer with 4K bytes of internal ROM, a traditional
microprocessor that manages up to 120K bytes of external
memory, or a parallel-processing element in a system with
other processors and peripheral controllers linked by the
Z-BUS® bus. In all configurations, a large number of pins
remain available for I/O.
.FIELD PROGRAMMABLE VERSION
The Z86E11 is a pin compatible "one time
programmable" version of the Z86C11. The Z86C11
contains 4K bytes of EPROM memory in place of the
4K bytes of masked ROM in the Z86C11. The
Z86E 11 also contains a programmable memory
protect feature to provide program security by
disabling all external accesses to the internal EPROM
array. This is preliminary information, and is subject to
change.
ARCHITECTURE
Z86C11 architecture is characterized by a flexible I/O
scheme, an efficient register and address space structure
and a number of ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O
capabilities. The Z86C11 fulfills this with 32 pins dedicated
to input and output. These lines are grouped into four ports
of eight lines each and are configurable under software
control to provide timing, status signals, serial or parallel I/O
with or without handshake, and an address/data bus for
interfacing external memory.
Because the multiplexed address/data bus is merged with
the I/O-oriented ports, the Z86C11 can assume many
different memory and I/O configurations. These configurations range from a self-contained microcomputer to a
110
(BIT PROGRAMMABLE)
microprocessor that can address 120K bytes of external
memory (Figure 3).
Three basic address spaces are available to support this
wide range of configurations: program memory (internal
and external), data memory (external) and the register file
(internal). The 256-byte random-access register file is
composed of 236 general-purpose registers, four I/O port
registers, and 16 control and status registers.
To unburden the program from coping with real-time
problems such as serial data communication and
counting/timing, an asynchronous receiver/transmitter
(UART) and two counter/timers with a large number of
user-selectable modes are offered on-chip. Hardware
support for the UART is minimized because one of the
on-chip timers supplies the bit rate.
ADDRESS OR 110
(NIBBLE PROGRAMMABLE)
Figure 3. Functional Block Diagram
118
ADDRESSIDATA OR 110
(BYTE PROGRAMMABLE)
STANDBY MODE
The Z86C11 's standby modes are:
o Stop
o Halt
The Stop instruction stops the internal clock and clock
oscillation; the Halt instruction stops the internal clock but
not clock oscillation.
A reset input releases the standby mode.
POWER DOWN INSTRUCTIONS
The Z86C91 has two instructions to reduce power
consumption during standby operation. HALT turns off the
processor and UART while the counter/timers and external
interrupts IROO, IR01, and IR02 remain active.
When an interrupt occurs the processor resumes execution
after servicing the interrupt. STOP turns off the clock to the
entire Z86C91 and reduces the standby current to 10
microamps. The stop mode is terminated by reset, which
causes the processor to restart the application program at
address 12.
To complete an instruction prior to entering standby
mode, use the instructions:
lD TMR, #00
NOP
ST()P or HALT
PIN DESCRIPTION
AS. Address Strobe (output, active Low). Address Strobe is
pulsed once at the beginning of each machine cycle.
Addresses output via Port 1 for all external program or data
memory transfers are valid at the trailing edge of AS. Under
program control, AS can be placed in the high·impedance
state along with Ports 0 and 1, Data Strobe and Read/Write.
OS. Data Strobe (output, active Low). Data Strobe is
activated once for each external memory transfer.
POO-po 7, Pl o-Pl 7 , P2 o-P2 7 , P3 q-P3 r
I/0 Port
Lines (input/outputs, TTL-compatible). These 32 lines
are divided into four 8-bit I/0 ports that can be
configured under program control for I/0 or external
memory interface (Figure 3).
RESET. Reset (input, active Low). RESET initializes the
Z86C11. When RESET is deactivated, program execution
begins from internal program location OOOC H .
R/W. ReadlWrite (output). R/Vii is Low when the Z86C11 is
writing to external program or data memory.
XTAL1, XTAL2.
Crystal 1, Crystal 2
input and output).
These pins connect
resonant crystal (12 MHz' maximum) or
single-phase clock (12 MHz maximum) to
clock oscillator and buffer.
(time-base
a parallelan external
the on-chip
ADDRESS SPACE
Program Memory. The 16-bit program counter addresses
64K bytes of program memory space. Program memory
can be located in two areas: one internal and the other
external (Figure 4). The first 4096 bytes consist of on-chip
mask-programmed ROM. At addresses 4096 and greater,
the Z86C11 executes external program memory fetches.
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts.
Data Memory. The Z86C11 can address 60K bytes of
external data memory beginning at location 4096 (Figure 5).
External data memory may be included with or separated
from the external program memory space. OM, an optional
I/O function that can be programmed to appear on pin P34,
is used to distinguish between data and program memory
space.
Register File. The 2S6-byte register file includes four 1/0
port registers (RO-R3), 236 general-purpose registers
(R4-R 239) and 16 control and status registers (R240-R255).
These registers are assigned the address locations shown in
Figure 6.
Z86C11 instructions can access registers directly or
indirectly with an 8-bit address field. The Z86C11 also
allows short 4-bit register addressing using the Register
Pointer (one of the ,control registers)_
In the 4-bit
mode, the register file is divided into 16 working register
groups, each occupying 16 contiguous locations (Figure
6) _ The Register Pointer addresses the starting location
of the active working-register group (Figure 7).
Note: Register Bank EO-EF can only be accessed through
working register and indirect addressing modes.
Stacks. Either the internal register file or the external data
memory can be used for the stack. A 16-bit Stack Pointer
(R254 and R255) is used for the external stack, which can
reside anywhere in data memory between locations 4096
and 65535. An 8-bit Stack Pointer (R255) is used for the
internal stack that resides within the 124 general-purpose
registers (R4-R127).
119
65535.-----------,
5535
EXTERNAL
ROM OR RAM
4096
4095
ON·CHIP
ROM
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED
AFTER RESET :
,""-- ~------------
EXTERNAL
12
INTERRUPT
VECTOR
(LOWER BYTE)
INTERRUPT
VECTOR
(UPPER BYTE)
11
IRQ5
10
IRQ5
9
IR04
8
IRQ4
7
IRQ3
6
IRQ3
5t<-
IRQ2
4i>r"
IR02
3
IRQl
2
IR01
1
IROO
0
IROO
DATA
MEMORY
:g:~t------------I
NOT ADDRESSABLE
Figure 4. Program Memory Map
LOCATION
IDENTIFIERS
255
STACK POINTER (BITS 7-0)
SPL
254
STACK POINTER (BITS 15-8)
SPH
RP
253
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
250
INTERRUPT REOUEST REGISTER
IMR
IRQ
IPR
249
INTERRUPT PRIORITY REGISTER
248
PORTS 0-1 MODE
P01M
247
PORT 3 MODE
P3M
246
PORT 2 MODE
P2M
245
TO PRESCAlER
244
TIMER/COUNTER 0
243
Tl PRESCAlER
PREO
TO
PREl
Tl
242
TIMER/COUNTER 1
241
TIMER MODE
TMR
240
SERIAL 1/0
SIO
239
Figure 5. Data Memory Map
-~II
>--
I
o0
0 0
12 53
2 40
THE UPPER NIBBLE OF THE REGISTER FILE ADD RESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING-REGISTER GROUP.
r--I
···....
-
239
··
- ....
-~
GENERAl·PURPOSE
REGISTERS
255
r7 re rs r.
SPECIFIED WORKING.
REGISTER GROUP
THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
~r PROVIDED BY
THE INSTRUCTION
POINTS TOTHE
SPECIFIED
REGISTER.
-~
PORT_,3
P3
PORT 2
P2
PORT 1
PI
PORTO
PO
Figure 6. The Register File
120
15
-~
r---'/OPORTS----- 3
Figure 7. The Register Pointer
SERIAL INPUT/OUTPUT
Port 3 lines P30 and P37 can be programmed as serial I/O
lines for full-duplex serial asynchronous receiver/transmitter
operation. The bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second for 8 MHz.
The Z86C11 automatically adds a start bit and two stop bits
- to transmitted data (Figure 8). Odd parity is also available as
an option. Eight data bits are always transmitted, regardless
of parity selection. If parity is enabled, the eighth bit is the
odd parity bit. An interrupt request (IRQ4) is generated on all
transmitted characters.
Received data must have a start bit, eight data bits and at
least one stop bit. If parity is on, bit 7 of the received data is
replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.
TRANSMITTED DATA
RECEIVED DATA
(No Parity)
(No Parity)
1~1~1~1~1~1~1~1~1~lsij
T
LSTARTBIT
LSTAATBIT
' - - - - - - - E I G H T OJ\TA BITS
TWO STOP BITS
' - - - - - - E I G H T DATA BITS
L - - - - - - _ - - O N E S T O P BIT
TRANSMITTED DATA
RECEIVED DATA
(With Parity)
(With Parity)
TL
_LSTARTBIT
' - - - - - - S E V E N DATA BITS
ODD PARITY
TWO STOP BITS
IIL_______
LSTART BIT
' - - - - - S E V E N DATA BITS
::~I~~::~: FLAG
Figure 8, Serial Data Formats
COUNTER/TIMERS
The Z86C11 contains two 8-bit programmable counter/
timers (To and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler can be driven by
internal or external clock sources; however, the To prescaler
is driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IRQ4 (To) or
IRQ5 (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass
mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode). The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode.
The clock source for T1 is user-definable and can be
the internal microprocessor clock divided by four, or an
external signal input via Port 3.
The Timer Mode
register configures the external timer input as an
external clock (1 MHz maximum), a trigger input that
can be retriggerable or non-retriggerable, or as a gate
input for the internal clock. The counter/timers can be
programmably cascaded by connecting the TO output to
the input of Tl' Port 3 line P3 6 also serves as a
timer output (TOUT) through which To, Tl or the
internal clock can be output.
121
1/0 PORTS
The Z86C11 has 32 lines dedicated to input and output.
These lines are grouped into four ports of eight lines each
and are configurable as input, output or address/data.
Under software control, the ports can be programmed to
provide address outputs, timing, status signals, serial 110,
and parallel I/O with or without handshake. All ports have
active pull-ups and pull-downs compatible with TTL loads.
Port 1 can be placed in the high-impedance state along with
Port 0, AS, OS and Riw, allowing the Z86C11 to share
common resources in multiprocessor and DMA
applications. Data transfers can be controlled by assigning
P33 as a Bus Acknowledge input, and P34 as a Bus Request
output.
Port 1 can be programmed as a byte I/O port or as an
address/data port for interfacing external memory. When
used as an I/O port, Port 1 may be placed under handshake
control. In this configuration, Port 3 lines P33 and P34 are
used as the handshake controls RDY 1 and DAV1 (Ready
and Data Available).
PORT 1
(110 OR ADo-AD7)
Memory locations greater than 4096 are referenced
through Port 1. To interface external memory, Port 1 must be
programmed for the multiplexed Address/Data mode. If
more than 256 external locations are required, Port 0 must
output the additional lines.
Port 0 can be programmed as a nibble I/O port, or as an
address port for interfacing external memory. When used as
an I/O port, Port 0 may be placed under handshake control.
In this configuration, Port 3 lines P32 and P3s are used as
the handshake controls DAVo and RDYo. Handshake signal
aSSignment is dictated by the I/O direction of the upper
nibble P0 4-P0 7.
.
For external memory references, Port 0 can provide address
bits As-A11 (lower nibble) or As-A1S (lower and upper nibble)
depending on the required address space. If the address
range requires 12 bits or less, the upper nibble,of Port 0 can
be programmed independently as I/O while the lower nibble
Port 2 bits can be programmed independently as input or
output. This port is always available for I/O operations. In
addition, Port 2 can be configured to provide open-drain
outputs.
Like Ports 0 and 1, Port 2 may also be placed under
handshake control. In this configuration, Port 3 lines P31
and P36 are used as the handshake controls lines DAV2 and
ROY2. The handshake signal assignment for Port 3 lines P31
and P36 is dictated by the direction (input or output) assigned
to bit 7 of Port 2.
Port 3 lines can be configured as I/O or control lines. In either
case, the direction of the eight lines is fixed as four input
(P30-P33) and four output (P34-P37). For serial I/O, lines P30
and P37 are programmed as serial in and serial out
respectively.
Port 3 can also provide the following control functions:
handshake for Ports 0, 1 and 2 (DAV and ROY); four external
interrupt request signals (IRQo-IRQ3); timer input and output
signals (TIN and TOUT) and Data Memory Select (OM).
122
Figure 9a. Port 1
is used for addressing. When Port 0 nibbles are defined as
address bits, they can be set to the high-impedance state
along with Port 1 and the control signals AS, OS and RfW.
j
PORT 0
(110 OR A.-A1S)
286Cll
MCU
_
}
~!:~:~~~ED~~NTROLS
(P32 AND P3s)
Figure 9b. Port 0
PORT 2(1/0)
286Cll
MCU
}
HANDSHAKE CONTROLS
5AV2 AND RDY2
(P31 AND P3S>
Figure 9c. Port 2
ZI6CU
PORTa
(110 OR CONTROL)
MCU
Figure 9d. Port 3
INTERRUPTS
The Z86C11 allows six different interrupts from eight sources:
the four Port 3 lines P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or individually
enables or disables the six interrupt requests. When more
than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All Z86C11 interrupts are vectored. When an interrupt
request is granted, an interrupt machine cycle is entered. This
disables all subsequent interrupts, saves the Program
Counter and status flags, and branches to the program
memory vector location reserved for that interrupt. This
memory location and the next byte contain the 16-bit address
of the interrupt service routine for that particular interrupt
request.
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the interrupt
inputs can be masked and the Interrupt Request register
polled to determine which of the interrupt requests needs
service.
CLOCK
The on-chip oscillator has a high-gain, parallel-resonant
amplifier for connection to a crystal or to any suitable external
clock source (XTAL 1 = Input, XTAL2 = Output).
The crystal source is connected across XTAL 1 and XTAL2,
using the recommended capacitors {C 1 ~ 15 pD from each
pin to ground. The specifications for the crystal are as follows:
fl!I
AT cut, parallel resonant
III Fundamental type, 12 MHz maximum
I!!i Series resistance, Rs ~ 100 Q
INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Indirect register pair or indirect working-regisier
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Symbols. The following symbols are used in describing the
instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "+-': For
example,
dst +- dst
+ src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr{n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the following six
flags:
C
Z
S
V
D
H
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:
o
1
*
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
123
CONDITION CODES
Value
Mnemonic
1000
0111
1111
C
NC
0110
1110
Z
NZ
Always true
Carry
No carry
Zero
Not zero
1101
0101
0100
1100
0110
PL
MI
OV
NOV
EQ
Plus
Minus
Overflow
No overflow
Equal
8=0
1110
1001
NE
GE
LT
GT
LE
Not equal
Greater than or equal
Z=O
0001
1010
0010
1111
0111
1011
0011
Meaning
Flags Set
C=1
C=O
Z
8=1
V=1
V=O
Z=1
(8 XOR V) = a
(8 XOR V) = 1
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
UGE
ULT
[ZO~(8XORV)] = 0
[ZOR(8XORV)] = 1
C=O
C =1
Unsigned greater than
Unsigned less than or equal
Never true
UGT
ULE
0000
=1
z=o
(C = 0 AND Z = 0) = 1
(CORZ) = 1
INSTRUCTION FORMATS
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC
dsl
OPC
INCr
One-Byte Instructions
CLR, CPL, DA, DEC,
L---"="'--l OR 11 1 1 01 dsUsrc 1
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
~G~~'~~~Rt~~~R~OP,
RRC, SRA, SWAP
I
OPC
f--'-'dS..:t'-----i OR /11 1 01
JP, CALL (Indirect)
dst
I----:c~:=--I
OR
b 1 1 01
dst
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
SRP
OPC
VALUE
LD
OPC
MODE
dst
src
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
I-_-,:sr",c_-I OR 1 1 1 0
L-_..::ds::!t_--, OR 1 1 1 0
LD
LD, LDE, LDEI,
LDC, LOCI
dstlsrc
ope
sreldst
I
dst
OPC
VALUE
I
dsUCCR~ OPC
LD
OR 11 1 1 01
src
src
dst
cc
OPC
JP
DAu
DAl
LD
DJNZ, JR
OPC
DAu
DAl
CALL
STOP/HALT
Two-Byte Instructions
124
Three-Byte Instructions
INSTRUCTION SUMMARY
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
C Z S V 0 H
AOCdst,src
dst-dst + src + C
(Note 1)
10
'* '* '* '* o '*
AOOdst,src
dst - dst + src
(Note 1)
00
-:: * '* '* o *
50
-,**
CALLdst
OA
SP-SP - 2
IRR
@SP <-- PC; PC - dst
06
04
------
CCF
C-NOTC
EF
*-----
ANOdst,src
dst - dst AND src
(Note 1)
0--
CLRdst
dst-O
R
IR
BO
B1
------
COMdst
dst-NOTdst
R
IR
60
61
-**
CP dst,src
dst - src
(Note 1)
AD
'* '* '* ,*--
OAdst
dst-OAdst
R
IR
40
41
'*
OECdst
dst-dst - 1
R
IR
00
01
-** *--
OECWdst
dst-dst - 1
RR
IR
80
81
-"'* *--
8F
------
01
IMR (7)-0
OJNZr,dst
RA
r- r - 1
it r;O 0
PC-PC + dst
Range: +127, -128
HALT
7F
INCWdst
dst - dst + 1
RR
IR
",X--
AddrMode Opcode
Byte
dst src
(Hex)
IRR
JRcc,dst
RA
it cc is true,
PC-PC + dst
Range: + 127, -128
LO dst,src
dst -src
r
R
1m
R
r
X
X
r
Ir
r
R
IR
1M
1M
R
r
Ir
R
R
R
IR
IR
------
rE
-*1:1:-r= 0 - F
20
21
AO
A1
IRET
BF
FLAGS - @SP; SP - SP + 1
PC ..... @SP; SP ..... SP + 2; IMR (7) ..... 1
-*'" *-1: 1: * * '" *
Flags Affected
C Z S V 0 H
cD
-----c=O-F
30
OA
cB
c=;O-F
------
rC
r8
r9
r= 0 - F
C7
07
E3
F3
E4
E5
E6
E7
F5
------
LOC dst,src
dst - src
r
Irr
Irr
C2
02
------
LOCI dst,src
dst -src
r-r + 1; rr-rr + 1
Ir
Irr
Irr
Ir
C3
03
------
LOE dst,src
dst -src
r
Irr
Irr
82
92
------
LOEI dst,src
dst -src
r - r + 1; rr - rr + 1
Ir
Irr
Irr
Ir
83
93
------
FF
------
OR cfst,src
dst - dst OR src
(Note 1)
40
-**0--
POPdst
dst-@SP;
Sp ..... SP + 1
R
IR
50
51
------
70
71
------
RCF
C ..... O
CF
0-----
RET
PC-@SP;Sp ..... SP + 2
AF
------
RLdst ~~
90
91
****--
NOP
9F
R
IR
JP cC,dst
it cc is true
PC-dst
0--
-----rA
r=O-F
EI
IMR(7)-1
INCdst
dst-dst + 1
*
Instruction
and Operation
PUSH src
SP ..... SP - 1; @SP ..... src
R
IR
R
IR
125
INSTRUCTION SUMMARY (Continued)
Addr Mode Opcode / Flags Affected
Byte
dst src
(Hex)
C Z S V 0 H
Instruction
and Operation
L{"i}:6J R
Instruction
and Operation
AddrMode Opcode
Byte
(Hex)
dst src
Flags Affected
C Z S V 0 H
10
11
TM dst,src
dstANO src
(Note 1)
70
-1<1<
0--
IR
R
IR
EO
E1
XORdst,src
dst +- dst XOR src
(Note 1)
SO
-1<1<
0--
RRCdst~R
IR
CO
C1
(Note 1)
3D
NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to the left of the applicable addressing mode pair.
RLC dst
c
RR dst 4il
c
,
0
LEjjJ
,
0
c
,
0
SBCdst,src
dst +- dst +- src +- C
SCF
C +-1
OF
SRA d s t 4 i l @ R
C
,
0
IR
DO
01
1m
SRPsrc
RP +- src
STOP
I'
(Note 1)
S
.,
TCM dst,src
(NOT dst) AND src
126
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.
Addr Mode
dst
src
R
R
31
Ir
6F
SUBdst,src
dst +- dst +- src
SWAPdst
1-----
R
oliR
(Note 1)
20
1< 1< 1< 1<
1
1t
FO
F1
X
1< 1<
X--
60
-1<1<
0--
R
IR
R
1M
IR
1M
Lower
Opcode Nibble
REGISTERS
R240SI0
SERIAL I/O REGISTER
(FOH; Read/Write)
R244 TO
COUNTERITIMER 0 REGISTER
(F4H; Read/Write)
I~I~I~I~I~I~I~I~I
,-I
- - S E R I A L DATA
to,
=
LSB)
R241 TMR
TIMER MODE REGISTER
(F1H; Read/Write)
NOT To"MaDES
useD = DO
j
~
To OUT:: 01
T, OUT", 10
INTERNAL CLOCK OUT
11.
=
T
EXTERNAL CLOCK
R245PREO
PRESCALER 0 REGISTER
(F5H; Write Only)
~~O =
FUNCTION
1 ;:;: NO
LOAD
To
0 = DISABLE T COUNT
0
1
ENABLE To COUNT
MODES
0
1
INPI~T = 00
GATE INPUT = 01
(NON.R~~~3~~~~:~~ :: 10
TRIGGER INPUT = 11
To INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)
=
= NO FUNCTION
=
~L
=
1
To MODULO·N
RESERVED
LOAD T,
0 = DISABLE T, COUNT
1
caUNTMaDE
0.= To SINGLE·PASS
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
= ENABLE T, COUNT
01-00 HEX)
(RETAIGGERABLE)
R242T1
COUNTER TIMER 1 REGISTER
(F2H; Read/Write)
R246P2M
PORT 2 MODE REGISTER
(F6H; Write Only)
. 10,10.10,10.10,1 0,1 0,10,1
T, INITIAL VALUE (WHEN WRITTEN)
' - - - - ( R A N G E 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)
R243 PRE1
PRESCALER 1 REGISTER
(F3H; Write Only)
~L
R247P3M
PORT 3 MODE REGISTER
(F7H; Write Only)
EE
caUNTMaaE
O PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
o=
T, SINGLE·PASS
1 = T, MODULO-N
CLOCK SOURCE
RESERVED
o P32
1 = T, INTERNAL
o=
1 P32
T, EXTERNAL TIMING INPUT
£TIN) MODE
:=.
INPUT
= DAVO/ROYO
00 P33;= INPUT
P3S = OUTPUT
P3S ::: ROYOIDAVO
P34 ;= OUTPUT
~ ~ }P33
= INPUT
P34 ;= OM
1 1 P33 = D'AViIRDY1 P34 = RDY11DAV'1
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
' -_ _ _ _ _ _ ~
'--------
'-________
~~~ ~ ~N:VUJ~~~~ :~:: ~~~~~UT)
~ ~~~
:
~~R~!L IN ~~~ ~ ~~~r..~TOUT
~ ~:=:~ g~F
Figure 11. Control Registers
127
REGISTERS (Continued)
R252 FLAGS
FLAG REGISTER
(FCH; ReadlWrite)
R248P01M
PORT 0 AND 1 MODE REGISTER
(F8H; Write Only)
PD'.PD'MODE~
~.-r
=
L
=
OUTPUT
00
INPUT
01
'
E~~
STACK SELECTION
0 '" EXTERNAL
1 = INTERNAL
,
LUSERFLAGF.
LUSER FLAG F2
1X = AB-All
. A'2-A15 '" 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1
'
=
PD00
•• PD,MODE
OUTPUT
01 = INPUT
OVERFLOW FLAG
SIGN FLAG
P1 p -P1 , MODE
00 = BYTE OUTPUT
01 "" BYTE INPUT
10 = ADo-AD7
,
HALF CARRY FLAG
DECIMAL ADJUST FLAG
ZERO FLAG
CARRY FLAG
11 "" HIGH·IMPEDANCE ADo-AD,.
As, Os, AM. Aa-A11. A12-A15
IF SELECTED
R253 RP
REGISTER POINTER
(FDH; ReadlWrite)
R2491PR
INTERRUPT PRIORITY REGISTER
(F9H; Write Only)
I I III 0.'''." '-' ~..~
l~t~t~t~t~t~t~I~1
"~",.:J
RESERveD = 000
C > A > B = 001
A > B > C = 010
A:> C > B = 011
B> C > A = 100
C > B > A ::: 101
B > A > C = 110
RESERVED = 111
IR03, IROS PRIORITY (GROUP Al
o=
1
=
IROS > IRQ3
IRQ3 > IROS
IRao, IRQ2 PRIORITY (GROUP B)
o
IRQ2 :> IRao
1
lRao > JRQ2
=
=
LOON'TCARE
REGISTER
POINTER
IRQ1, lRQ4 PRIORITY (GROUP C)
o = IRQ1 > IRQ4
1 = IRQ4 > IRQ1
R250lRQ
INTERRUPT REQUEST REGISTER
(FAH; ReadlWrite)
R254SPH
STACK POINTER
(FEH; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED
~
c==
=
IRQO
P32 INPUT (Do "" IRQO)
IR01 = P33 INPUT
lRQ2 ::: P31 INPUT
IRQ3 ::: PJo INPUT, SERIAL INPUT
IRQ4 = To, SERIAL OUTPUT
IR05 = T1
R2511MR
INTERRUPT MASK REGISTER
(FBH; Read/Write)
II
c==
1 ENABLES IROO-IR05
(Do::: IROO)
1-_ _ _ _ _ _ RESERVED
' - - - - - - - - 1 ENABLES INTERRUPTS
Figure 11. Control Registers (Continued)
128
R255SPL
STACK POINTER
(FFH; ReadlWrite)
OPCODEMAI?
Lower Nibble (Hex)
o
C
B
A
8
4
D
E
F
--~
A
B
C
D
E
F
6.5
6.5
6.5
6.5
10.5
10.5
-6.5
12/10.5
12/10.0
6.5
DEC
DEC
ADD
ADD
ADD
ADD
ADD
ADD
LD
LD
DJNZ
JR
LD
JP
INC
R,
IR,
r1 J 2
f1· lr2
R2·R,
IR2.R,
R,.IM
IR,.IM
rl,R2
r2,R,
r, RA
cC,RA
r,.IM
ccDA
rl
6.5
6.5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
IR"IM
10.5
10.5
R,
IR,
(1,(2
f1.lr2
R2,R,
IR2,R,
R"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR"IM
R,
IR,
(1,(2
(1, lr2
R2,R,
IR2,R,
R,.IM
8_0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRR,
1M
r1. r2
f1.lr2
R2,R,
IR2,R,
R"IM
IR"IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
IR"IM
R,
IR,
(1,r2
'1, lr 2
R2,R,
IR2,R,
R"IM
10.5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
IR"IM
6.5
12/10.0
6.5
i----
I---------i----
i----
i----
R,
IR,
r1·(2
'1,lr2
R2,R ,
IR2,R,
R"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
6,0
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
STOP
R,
IR,
'1.r2
(1.1r2
R2,R,
IR2,R,
R,.IM
IR"IM
10/12,1
12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
R2
IR2
'1J2
'1, lr 2
R2,Rr
IR2,R,
R,.IM
IR"IM
10,5
10,5
12,0
18,0
DECW
DECW
LDE
LDEI
RR,
IR,
6,5
6,5
'" lrr 2
12,0
Ir1,lrr2
RL
RL
LDE
LDEI
R,
IR,
'2,lrr,
Ir2·lrr1
10,5
10.5
6,5
6,5
10,5
10,5
10,5
10,5
14.0
INCW
INCW
CP
CP
CP
CP
CP
CP
RET
RR,
IR,
(1,(2
'1, lr 2
R2,R,
IR2,R,
R,.IM
IR"IM
6,5
6,5
6,5
'6,5 "-
10,5
10,5
10,5
10,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R2,R,
IR2·R,
R,.IM
IR"IM
i----
i---7,0
HALT
I---------61
or
i---6.1
18,0
EI
i----
i---16.0
IRET
R,
IR,
'1,(2
",lr2
6,5
6,5
12,0
18,0
10,5
6.5
RRC
RRC
LDC
LDCI
LD
RCF
R,
IR,
(1· lrr2
Ir1,lrr2
6,5
6,5
12,0
18,0
20,0
20,0
10,5
SRA
SRA
LDC
LDCI
CALL·
CALL
LD
r2. lrr 1
i----
rl.x.R2
-
6.5
SCF
R,
IR,
Ir2,lrr,
IRR,
DA
r2,x,R,
6,5
6,5
6,5
10,5
10,5
10,5
10,5
6.5
RR
RR
LD
LD
LD
LD
LD
CCF
R,
IR,
r" IR 2
R2,R ,
IR2,R,
R,.IM
IR"IM
8,5
8,5
6,5
10,5
SWAP
SWAP
LD
LD
R,
IR,
Ir1,r2
R2.1R,
-
-
6.0
NOP
'-.-..----_-v-""-----".1 ,,'-----V-----~/ '-. .-------v-""--------j '-v-' "---.....----'
2
2
3
Bytes per Instruction
LOWER
OPCODE
NIBBLE
EXECUTION
CYCLES
~
4
PIPELINE
CYCLES
MNEMONIC
Legend:
R = 8-bit address
r "" 4-bit address
Rl or" = Dst address
R2 or'2 = Src address
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
SECOND
OPERAND
NOTE: The blank areas are not defined.
*2-byte Instruction; fetch cycle appears as a 3-byte instruction
129
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... - 0.3V to + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
+5V
2.1K
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:
III
+4.5:S:; Vec :s:; + 5.5V
II GND =
II
0
OV
C:S; TA :s; +70 C for S (Standard temperature)
III -40 C
:s; T A :S;+100
Figure 12. Test Load 1
C for E (Extended temperature)
DC CHARACTERISTICS
Symbol
Parameter
VCH
Clock Input High Voltage
VCl
Clock Input Low Voltage
VIH
Input High Voltage
Vil
Input Low Voltage
VRH
Reset Input High Voltage
VRl
Reset Input Low Voltage
VOH
Output High Voltage
VOH
Output High Voltage
Min
V
Driven by External Clock Generator
0.8
V
Driven by External Clock Generator
2.0
VCC
V
-0.3
0.8
V
3.8
Vcc
V
-0.3
0.8
V
2.4
Vee -100mV
Input Leakage
-10
IOl
Output Leakage
-10
Supply Current
ICC1
Standby Current
ICC2
Standby Current
Condition
Vcc
Output Low Voltage
IIR
Unit
3.8
III
Icc
Max
-0.3
VOL
Reset Input Current
Typ
0.4
10
V
IOH = -250)lA
V
IOH = -100J.lA
V
IOl = +2.0mA
)lA
OV ~ VIN ~ + 5.25V
10
)lA
OV ~ VIN ~ + 5.25V
-50
)lA
Vcc = + 5.25V, VRl = OV
30
mA
All outputs and 110 pins floating, 12 MHz
5
10
mA
Halt Mode
)lA
Stop Mode
Ice2 requires loading TMR (%F1) with any value prior to STOP execution.
Use the sequence:
LD TMR, #00
NOP
STOP
130
RlW
PORT O.
DM
PORT 1
Ao-Al
- q"J' .(l-'\qtl,,'" q"'''
6
5
4
3
2
1 44 43 42 41 40
II!SlT 7
R/W
till
•
.•
10
38
Z86C21
Z86E21
Pl,
Pl,
Pl 0
Figure 2. 40-pin Dual-In-Line
Package (DIP), Pin Assignments
'7
36
NC
P"
P"
3S
P"
P2,
34
P2,
13
33
P3,
P3.
P',
11
GNO
12
P"
MCU
po,
po,
po,
14
3'
15
3'
Ph
"
'0
NC
17
29
P"
P',
18 19 20 21 22 23 24 25 26 27 28
qt::l'>q~.q~"qt:::.b qt:::..... q...Q
q..... q......." ..."q...... ~v
Pl,
Pl,
,.
Figure 2b. 44-pln Chip Carrier,
Pin Assignments
General Purpose Mlcroconlroller
Under program control, the ZB6C21 can be tailored
to the needs of its user. It can be configured as a
stand-alone microcomputer with 8K bytes of
internal ROM, a traditional microprocessor that
manages up to 112K bytes of external memory, or
a parallel-processing element in a system with other
processors and peripheral controllers linked by the
Z-BUS bus. In all configurations, a large number
of pins remain available for I/O.
Field Progrlllmmable "eralon
The Z86E21 is a pin compatible Onetime
Programmable version of the Z86C21. The Z86E21
contains 8K bytes of EPROM memory in place of the
8K bytes of masked ROM on the Z86C21. The
Z86E21 also contains a programmable memory
protect feature to provide program security by
disabling all external accesses to the internal EPROM
array.
ARCHITECTURE
Z86C21 architecture is characterized by a flexible I/O
scheme, an efficient register and address space structure
and a number of ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O
capabilities. The Z86C21 fulfills this with 32 pins dedicated
to input and output. These lines are grouped into four ports
of eight lines each and are configurable under software
control to provide timing, status signals, serial or parallel I/O
with or without handshake, and an address/data bus for
interfacing external memory.
Because the multiplexed address/data bus is merged with
the I/O·oriented ports, the Z86C21 can assume many
different memory and I/O configurations. Jhese configurations range from a self-contained microcomputer to a
110
(BIT PROGRAMMABLE)
microprocessor that can address 120K bytes of external
memory (Figure 3).
Three basic address spaces are available to support this
wide range of configurations: program memory (internal
and external)' data memory (external) and the register
file (internal).
The 256-byte random-access register
file is composed of 236 general-purpose registers, 4 I/O
port registers, and 16 control and status registers.
To unburden the program from coping with real-time
problems such as serial data communication and
counting/timing, an asynchronous receiver/transmitter
(UART) and two counter/timers with a large number of
user-selectable modes are offered on-chip. Hardware
support for the UART is minimized because one of the
on-chip timers supplies the bit rate.
ADDRESS OR I/O
(NIBBLE PROGRAMMABLE)
ADDRESSIDATA OR I/O
(BYTE PROGRAMMABLE)
Figure 3. Functional Block Diagram
135
STANDBY MODE
The Z86C21's standby modes are:
III
Stop
• Halt
The Stop instruction stops the internal clock and clock
oscillation; the Halt instruction stops the internal clock but
not clock oscillation.
A reset input releases the standby mode.
To complete an instruction prior to entering standby mode,
use the instructions:
NOP(FFH) + STOP(6FH)
NOP(FFH) + HALT(7FH)
PIN DESCRIPTION
AS. Address Strobe (output, active Low). Address Strobe is
pulsed once at the beginning of each machine cycle.
Addresses output via Port 1 for all external program·or data
memory transfers are valid at the trailing edge of AS. Under
program control, AS can be placed in the high-impedance
state along with Ports 0 and 1, Data Strobe and Read/Write.
OS. Data Strobe (output, active Low). Data Strobe is
activated once for each external memory transfer.
POo·P07. P10·P17. P20·P27. P30·P37. 110 Port Lines
(inpuUoutputs, TTL-compatible). These 32 lines are divided
into four 8-bit 1/0 ports that can be configured under
program control for 1/0 or external memory interface (Figure 3).
RESET. Reset (input, active Low). RESET initializes the
Z86C21 . When RESET is deactivated, program execution
begins from internal program location OOOCH.
R/W. ReadlWrite (output). RfifJ is Low when the Z86C21 is
writing to external program or data memory.
XTAL1, XTAL2. Crystal 1, Crystal 2 (time-base input
and output).
These pins connect a parallel-resonant
crystal (12 or 20 MHz maximum) or an external singlephase r clock (12 or 20 MHz maximum) to the on-chip
clock oscillator and buffer.
ADDRESS SPACE
Program Memory. The 16-bit program counter addresses
64K bytes of program memory space. Program memory
can be located in two areas: one internal and the other
external (Figure 4). The first 8192 bytes consist of on-chip
mask-programmed ROM. At addresses 8192 and greater,
the Z86C21 executes external program memory fetches.
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts.
Data Memory. The Z86C21 - can address 56K bytes of
external data memory beginning at location 4096 (Figure 5).
External data memory may be included with or separated
from the external program memory space. OM, an optional
1/0 function that can be programmed to appear on pin P34,
is used to distinguish between data and program memory
space.
Register File.
The 256-byte register file includes 4
I/O port registers (RO-R3), 236 general-purpose
registers (R4-R239) and 16 control and status registers
(R240-R255).
136
These registers are assigned the address locations shown in
Figure 6.
Z86C21 instructions can access registers directly or
indirectly with an 8-bit address field. The Z86C21 also
allows short 4-bit register addressing using the Register
Pointer (one of the control registers).
In the 4-bit
mode, the register file is divided into 16 working register
groups, each occupying 16 contiguous locations (Figure'
6). The Register Pointer addresses the starting location
of the active working-register group (Figure 7). Note:
Register Bank EO-EF can only be accessed through
working register and indirect addressing mode.
Stack,s. Either the internal register file or the external data
memory can be used for the stack. A 16-bit Stack Pointer
(R254 and R255) is used for the external stack, which can
reside anywhere in data memory between locations 4096
and 65535. An 8-bit Stack Pointer (R255) is used for the
internal stack that resides within the 124 general-purpose
registers (R4-R127):·
65535 ....- - - - - - - - - - . ,
5535
EXTERNAL
ROM OR RAM
1n
191
ON·CHIP
ROM
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED
AFTER RESET
i2 ~----....,-------
INTERRUPT
VECTOR
(LOWER BYTE)
11
IRQ5
10
IR05
9
IRQ4
8
IR04
7
IR03
6
IRQ3
po...
IR02
41>-
IR02
3
IR01
2
IR01
1
IROO
0
IROO
5
INTERRUPT
VECTOR
(UPPER BYTE)
EXTERNAL
DATA
MEMORY
:~:~I----------;
NOT ADDRESSABLE
Figure 4. Program Memory Map
LOCATION
IDENTIFIERS
255
STACK POINTER (BITS 7-0)
SPL
254
STACK POINTER (BITS 15-8)
SPH
253
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT REQUEST REGISTER
IRQ
249
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
P01M
I_-.-{J:=~J:;::;:=:;::=;::::;:::;:;::=I~::
...
t---'--'--'--'-------I 240
RP
PORT 3 MODE
P3M
246
PORT 2 MODE
P2M
245
TO PRESCALER
PREO
247
Figure 5. Data Memory Map
TO
244
TIMER/COUNTER 0
243
T1 PRESCALER
242
TIMER/COUNTER 1
241
TIMER MODE
TMR
240
SERIAL 110
510
PRE1
11
NOT
IMPLEMENTED
THE UPPER NIBBLE OF THE REGISTER FILE ADDRESS
PROVIDED BY THE REGISTER POINTER SPECIFIES
THE ACTIVE WORKING-REGISTER GROUP.
--I
--I
--I
--I
2_39
SPECIFIED WORKING·
239
REGISTER GROUP
-I-
THELQWER
NIBBLE OF
THE REGISTER
FilE ADDRESS
PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER.
GENERAL·PURPOSE
REGISTERS
PORT 3
P3
PORT 2",
P2
PORT 1
P1
PORT 0
PO
Figure 6. The Register File
- ......
15
I----"O'PO"TS----- 3
Figure 7. The Register Pointer
137
SERIAL INPUT/OUTPUT
Port 3 lines P30 and P37 can be programmed as serial 1/0
lines for full-duplex serial asynchronous receiverltransmitter
operation_ The bit rate is c9ntrolled by CounterlTimer O.
of parity selection. If parity is enabled, the eighth' bit is the
odd parity bit. An interrupt request (IRQ4) is generated on all
transmitted characters.
The Z86C21 automatically adds a start bit and two stop bits
to transmitted data (Figure 8). Odd parity is also available as
an option. Eight data bits are always transmitted, regardless
Received data must have a start bit, eight data bits and at
least one stop bit. If parity is on, bit 7 of the received data is
replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.
TRANSMITTED DATA
RECEIVED DATA
(No Parity)
(No Parity)
I&I~I~I~I~I~I~I~I~I~I
I
LSTART BIT
' - - - - - E I G H T DATA BITS
'---~-----ONE STOP BIT
TRANSMITTED DATA
RECEIVED DATA
(With Parity)
(With Parity)
1&1&1 pl~I~I~I~I~I~I~lsij
TI
LSTART BIT
' - - - - S E V E N DATA BITS
' - - - - - - - 0 0 0 PARITY
TWO STOP BITS
II
LSTART BIT
' - - - - S E V E N DATA BITS
'--------~~~I:~~::~TR FLAG
Figure 8. Serial Data Formats
COUNTER/TIMERS
The Z86C21 contains two 8-bit programmable counterl
timers (To and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler can be driven by
internal or external clock sources; however, the To prescaler
is driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IRQ4 (To) or
IRQ5 (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass
mode) or to automatically reload the initial value and
138
continue counting (modulo-n continuous mode). The
counters, but not the prescalers, can be read any time
without disturbing their value or count mode.
The dock source for T1 is user-definable and can be
the internal microprocessor dock divided by four. or an
external signal input via Port 3.
The Timer Mode
register configures the external timer input as an
external dock (lMHz maximum). a trigger input that
can be retriggerable or non-retriggerable. or as a gate
input for the internal dock. The counter/timers can be
programmably cascaded by connecting the To .output to
the input of T1. Port 3 line P3 6 also serves as a
timer output (TOUT) through· which To. Tl or the
internal dock can be output.
I/O PORTS
The Z86C21 has 32 lines dedicated to input and output.
These lines are grouped into four ports of eight lines each
and are configurable as input, output or address/data.
Under software control, the ports can be programmed to
provide address outputs, timing, status signals, serial I/O,
and parallel I/O with or without handshake. All ports have
active pull-ups and pull-downs compatible with TTL loads.
Port 1 can be programmed as a byte I/O port or as an
address/data port for interfacing external memory. When
used as an I/O port, Port 1 may be placed under handshake
control. In this configuration, Port 3 lines P3 3 and P34 are
used as the handshake controls ROY 1 and OAV1 (Ready
and Data Available).
fylemory locations greater than 8192 are referenced
through Port 1. To interface external memory, Port 1 must be
programmed for the multiplexed AddresslData mode. If
more than 256 external locations are required, Port 0 must
output the additional lines.
Port 0 can be programmed as a nibble I/O port, or as an
address port for interfacing external memory. When used as
an I/O port, Port 0 may be placed under handshake control.
In this configuration, Port 3 lines P32 and P35 are used as
the handshake controls OAVo and ROYo. Handshake signal
assignment is dictated by the I/O direction of the upper
nibble P04-P07.
For external memory references, Port 0 can provide address
bits Aa-A11 (lower nibble) or Aa-A15 (lower and upper nibble)
depending on the required address space. If the address
range requires 12 bits or less, the upper nibble of Port 0 can
be programmed independently as I/O while the lower nibble
Port 1 can be placed in the high-impedance state along with
Port 0, AS, OS and Riw, allowing the Z86C21 to share
common resources in multiprocessor and OMA
applications. Data transfers can be controlled by assigning
. P33 as a Bus Acknowledge input, and P34 as a Bus Request
output.
PORT 1
(110 OR ADo-AD7)
Z86C21
MCU
}
HANDSHAKE CONTROLS
DAV, AND ROY,
(P33 AND P3.)
Figure 9a_ Port 1
is used for addressing. When Port 0 nibbles are defined as
address bits, they can be set to the high-impedance state
along with Port 1 and the control signals AS, OS and R/W.
I
PORTO
(110 OR As-A,s)
_
} ~!~oD~~~KRED~~NTROLS
(P~
AND P3s)
Figure 9b. Port 0
Port 2 bits can be programmed independently as input or
output. This port is always available for I/O operations. In
addition, Port 2 can be configured to provide open-drain
outputs.
Like Ports 0 and 1, Port 2 may also be placed under
handshake control. In this configuration, Port 3 lines P31
and P36 are used as the handshake controls lines OAV2 and
ROY2. The handshake signal assignment for Port 3 lines P31
and P36 is dictated by the direction (input or output) assigned
to bit 7 of Port 2.
Port 3 lines can be configured as I/O or control lines. In either
case, the direction of the eight lines' is fixed as four input
(P30-P33) and four output (P34-P37)' For serial I/O, lines P30
and P37 are programmed as serial in and serial out
respectively.
Port 3 can also provide the following control functions:
handshake for Ports 0, 1 and 2 (OAV and ROY); four external
interrupt request signals (IRQo-IRQ3); timer input and output
signals (TIN and TOUT) and Data Memory Select (OM).
HANDSHAKE CONTROLS
} OAV2 AND RCY2
(P3 1 AND P36)
Figure 9c. Port 2
Z86C21
MCU
=
1..AT3
I
(110 OR CONTROL)
Figure 9d_ Port 3
. 139
INTERRUPTS
The Z86C21 allows six different interrupts from eight sources:
the four Port 3 lines P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are' both maskable and
prioritized. The Interrupt Mask register globally or individually
enables or disables the six interrupt requests. When more
than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the
Interrupt Priority register.
All Z86C21 interrupts are vectored through locations in
program memory. When an interrupt request is granted,
an interrupt machine cycle is entered. This disables all
subsequent interrupts, saves the Program Counter and
status flags, and branches to the program memory
vector location reserved for that interrupt. This memory
location and the next byte contain the 16-bit address
of the interrupt service routine for that particular
interrupt request.
Polled. interrupt systems are also supported. To
accommodate a polled structure, any or all of the interrupt
inputs can be masked and the Interrupt Request register
polled to determine which of the interrupt requests needs
service.
CLOCK
The on-chip oscillator has a high-gain, parallel-resonant
amplifier for connection to a crystal or to any suitable external
clock source (XTAL 1 = Input, XTAL2 = Output).
The crystal source is connected across XTAL 1 and XTAL2,
using the recommended capacitors (C 1 "" 15 pI) from each
pin to ground. The specifications for the crystal are as follows:
e AT cut, parallel resonant
.. Fundamental type, 16 MHz maximum
III
Series resistance, Rs "" 100 Q
GENERAL DESCRIPTION
The Z86C12 development device allows users to prototype a system with an actual hardware device' and to
develop the code. This code is eventually mask-programmed into the on-Chip ROM for any of the 86Cxx
devices (except the 86C91). Development devices are
also useful in emulator appli-cations where the final system configura-tion -- memory configuration, I/O, interrupt inputs, etc."- are unknown.The Z86C12 development
device is identical to its equivalent Z86C21 microcomputer
with the following exceptions:
• No internal ROM is provided, so
that code is
developed in off-chip memory. Rve "size" inputs configure
the memory boundaries.
" The normally internal ROM address and data lines are
buffered and brought out to external pins to interface with
the external memory.
D
Control lines (/MAS and IMDS) are added to interface
with external program memory.
The Timing and Control, I/O ports, and clock pins on
the Z86C 12 are identical in function to those on the
86C21. This section covers those pins that do not
appear on the Z86C21 8K ROM device. The pin
functions and pin aSSignments are shown on figure
00.
Z86C12 PIN DESCRIPTION
DO - 07 (Inputs, TTL compatible) Data bus_
These 8 lines provide the input data bus to access
external memory emulating on the on-Chip ROM.
During read cycles in the internal memory space the
data on these lines is latched in just prior to the rise of
the IMDS data strobe.
/MDS (Output, TTL compatible) Memory Data
Strobe. This is a timing signal used to enable the
external memory to emulate the on-Chip ROM. It is
active only during accesses to the on-Chip ROM
memory space, as selected by the configuration of the
SIZEn pins.
.
AO - A15 (Outpus TTL compatible) Address
bus. During T1 these lines output the current memory
address. All addresses, whether internal or external,
are output.
/SCLK (Output, TTL compatible) System
Clock. This line is teh internal system clock.
IMAS (Output, TTL compatible) Memory
Address Strobe. This line is active during every T1
cyc;:le. The rising edge of this signal may be used to
latch the current memory address on the lines AO A 15. This line is always valid; it is not tri-stated when
lAS is tri-stated.
140
/SYNC (Output TTL, compatible) Sync signal.
This Signal indicates the last clock cycle of the currently
executing instruction.
!lACK (Output TTL, compatible) Interrupt
Acknow-Iedge. This output, when low, indicates
that the Z86C12 is an interrupt cycle.
ISIZEO, ISIZE1, ISIZE2, ISIZE3,
SIZE4
(Inputs, TTL compatible).
The ISIZEn lines
control the emulation mode of the 86C12. Note that
ISIZEO - ISIZE3 are active low, while SIZE4 is active
high. The functions are defined as shown in figure 00.
The 86C12 should be in RESET when the state of
these lines are changed.
NOTE:
The SIZE pins may be configured to make the
memory control signals (/MAS, IMOS, RIW,
lAS, and lOS) look like the Z86C91 ROMless
device, however on power-up or reset ports
o and 1 are configured as inputs, rather than
A15 - A8 and A07 - AOO, respectively.
Table 1. Z86C12 Pin Assignments
NAME
NAME PIN
lAS
lOS
IMAS
IMOS
IRESET
ISIZEO
ISIZE1
ISIZE2
ISIZE3
ISYNC
AD
A1
A10
A11
A12
A13
A14
A15
A2
A3
A4
A5
A6
A7
A8
A9
00
01
02
03
04
05
06
07
lACK
NC
NC
NC
NC
NC
POO
POi
P02
P03
P04
P05
P06
B2
C4
E1
G3
B3
A3
C5
A6
C6
F1
J9
H7
J4
H4
K9
K7
K5
H5
KiO
J8
J7
K6
J6
K8
J5
K4
H3
K2
J3
K3
H8
J10
H9
H10
F2
J2
C3
08
H2
Ki
C1
03
02
01
E3
G1
Hi
NAME
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
PIN
NAME
PIN
J1
G8
G9
G10
F8
010
C10
B10
E9
C9
A10
B9
C8
A9
B8
A8
C7
P36
P37
RIW
SCLK
SIZE4
VCC
VCC1
VCC2
VSS
VSS1
VSS2
VSS3
Xtal1
Xtal2
A7
A5
A1
G2
F10
SIZE4 ISIZE3 ISIZE2 ISIZE1
ISIZEO
MEMORY
B4
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
ROM less
2K ROM
4K ROM
8K ROM
16K ROM
32K ROM
3
4
5
6
7
8
9
10
A •
B
C
0
0
0
0
0
1
B6
F9
F3
E2
H6
E8
B5
A2
B7
C2
09
E10
B1
2
Table 2. Memory Size Configuration
A4
D
E
F
G
H
J
K
·
·
·
·
·
·
·
·
·
TOP
VIEW
141
TIMING
AND
CONTROL
....
IRESET
.. ...
OIl(
STATUS AND
MEMORY CON·
TROL
GROUND
...
...
...
PROGRAM
MEMORY
DATA IN·
PUTS
ROM SIZE
INPUTS
Xtall
Xtal2
POO
POl
P02
P03
P04
P05
P06
P07
PORTO
(NIBBLE
PROGRAM·
MABLE) 1/0
OR A8-A15
PORT 1
(BYTE PRO·
GRAMMABLE)
1/0 OR
ADD-AD7
+5V
GND
R/W
IDS
.
----....
..
P20
P2l
P22
P23
P24
P25
P26
P27
Pl0
Pl1
P12
P13
P14
P15
P16
P17
P30
P3l
P32
P33
P34
P35
P36
P37
DO
01
02
03
04
05
06
07
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
ISIZEO
ISIZEl
ISIZE2
ISIZE3
SIZE4
IIACK
IMAS
IMDS
ISYNC
SCLK
......
...
... ....
...... .......
.. ...
......
.......
......
...
-<
~
PORT 2
(BIT PRO·
GRAMMABLE)
~
.....
PORT 3
SERIAL AND
PARALLEL
1/0 CONTROL
lao
---i>
...
.......
--Joo-
........
lao
PROGRAM
MEMORY
ADDRESS
OUTPUTS
.
...
~
.....
Z86C12 Pin Functions
CLOCK
~
OIl
VCC
VCCl - c E - VCC2
VSS
VSSl
VSS2
Z86C12
142
..
...
POWER
INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
IRR
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Symbols. The following symbols are used in describing the
instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "+--': For
example,
dst <- dst
+ src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the following six
flags:
C
Z
S
V
o
H
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:
o
1
""
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
CONDITION CODES
Value
Mnemonic
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Flags Set
Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
C=1
c=o
Z= 1
Z=O
8=0
8=1
V
=1
V=O
Z=1
Z=O
(8XORV) = 0
(8 XOR V) = 1
[ZOR (8XOR V)] = 0
[ZOR(8XORV)] = 1
C=O
C=1
(C = 0 AND Z
(CORZ) = 1
= 0) = 1
143
INSTRUCTION FORMATS
~
OPC
dst
CCF, 01, El, IRET, NOP,
RCF, RET, SCF
OPC
tNCr
One-Byte Instructions
OPC
MODE
CLR, CPL, DA, DEC,
I
dst'src
g~~~'~~~Rt~?};'R:OP,
1-_';;:'='_--1
RRC, SRA, SWAP
I
OPC
7.7-t ----i OR 11 1 1 0
l----'d
OPC
VALUE
I
OR 11 1 1 0 dot'ore
I
-
MODE
OPC
src/dst
1 1 01
dst
, ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
OPC
LD
OR 1 1 1 0
OR 1 1 1 0
ore
dot
ore
dst
LD
LD, LDE, LDEI,
LDC, LDCI
cc
ore
I
OPC
JP
DAu
DAL
LD
dst
oPy
VALUE
I
OPC
DAu
DAL
DJNZ, JR
dsUCC
OPC
RA
.
FFH
I
It
SRP
LD
6FH
OR
ADC, ADD, AN D, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
JP, CALL (Indirect)
I
l-.-"'=::':""'......J OR 11 1 1 01
I
1-'-',-,-::+--=,-;
dst
ADC, ADD, AN D,
CP, OR, SBC, SUB,
TCM, TM, XOR
MODE
dst/src
OR
CALL
STOP/HALT
7FH
Two-Byte Instructions
Three-Byte Instructions
INSTRUCTION SUMMARY
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
CZSVDH
ADCdst,src
dst-dst + src + C
(Note 1)
10
* * * *
o 1r
ADDdst,src
dst - dst + src
(Note 1)
00
* * * *
o
ANDdst,src
dst - dst AN D src
(Note 1)
50
-** 0--
CALLdst
DA
SP-SP - 2
IRR
@SP - PC; PC - dst
D6
D4
------
CCF
C-NOTC
EF
*-----
R
IR
BO
B1
------
'R
IR
60
61
-**0--
*
Instruction
and Operation
JPcc,dst.
ifcc is true
PC-dst
COMdst
dst-NOTdst
CPdst,src
dst - src
RoOonn,co
144
(Note 1)
AD
1:
***--
DA
IRR
JRcc,dst
if cc is true,
PC-PC + dst
I
CLRdst
dst-O
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
....... ,'~ .....
.L
1')7
I
..... ,
LDdst,src
dst-src
RA
Flags Affected
CZSVDH
cD
c=O-F
30
------
cB
c=O-F
------
rC
r8
r9
r=0- F
C7
D7
E3
F3
E4
E5
E6
E7
F5
------
,--
_ 1?R
I
r
r
R
1m
r
X
X
r
Ir
r
R
IR
r
Ir
R
R
R
IR
IR
R
1M
1M
R
INSTRUCTION SUMMARY (Continued)
Addr Mode Opcode
Byte
dst src
(Hex)
Instruction
and Operation
R
DAdst
dst +- OA dst
IR
DECdst
dst +-dst - 1
IR
R
RR
DECWdst
dst +- dst - 1
DI
IMR(7) <-0
C Z S V D H
src
C2
02
------
00
01
LDCI dst,src
dst +- src
r+-r + 1; rr+-rr + 1
Ir
Irr
Irr
Ir
C3
03
------
LDEdst,src
dst +- src
r
Irr
Irr
82
92
------
LDEI dst,src
dst +- src
r +- r + 1; rr +- rr + 1
Ir
Irr
Irr
Ir
83
93
------
FF
------
-***--
NOP
9F
HALT
7F
rE
-**,~--
r= 0- F
R
20
21
IR
RR
AO
A1
-**w--
IRET
SF
FLAGS +- @SP; SP +- SP + 1
PC +- @SP; SP +- SP + 2; IMR (7) +-1
* ** * * *
IR
CZSVDH
Irr
rA
r=O-F
INCdst
dst +- dst + 1
Flags Affected
r
Irr
EI
IMR(7) +-1
INCWdst
dst +- dst + 1
dst
Opcode
Byte
(Hex)
LDCdst,src
dst +- src
8F
DJNZr,dst
RA
r+- r - 1
ifr*O
PC +-PC + dst
Range: + 127, -128
Instruction
and Operation
40
41
80
81
IR
AddrMode
Flags Affected
OR dst,src
dst +- dst OR src
(Note 1)
40
-**0--
POPdst
dst+-@SP;
SP +-SP + 1
R
IR
50
51
------
70
71
------
RCF
C+-O
CF
0-----
RET
PC +- @SP; SP +- SP + 2
AF
------
R
IR
90
91
****--
PUSH src
SP +- SP - 1; @SP +- src
RLdst
o~
7
0
R
IR
RLCdst~R
"
c , ' IR
10
11
TM dst,src
dstANOsrc
(Note 1)
70
-**
0--
LEJ LDJ IRR
EO
E1
XORdst,src
dst +- dst XOR src
(Note 1)
SO
- '* *
0--
L8-=DJ
R
'IR
CO
C1
NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity, The first opcode nibble is found in
the instruction set table above, The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to the left of the applicable addressing mode pair.
RR dst
RRC dst
c
,
c
,
,
(Note 1)
SBCdst,src
dst +- dst +- src +- C
3D
\
SCF
C +-1
SRA dst
LEJ @
c
,
,
R
IR
1m
SRPsrc
RP +-src
STOP
OF
,1 - - - - -
00
01
***0--
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13,
AddrMode
dst
31
Ir
6F
R
SUBdst,src
dst +- dst +- src
SWAP dst I;
52
(Note 1)
R
-rc=:::t-X...,....::.'II R
1.:..."
TCM dst,src
(NOT dst) ANO src
(Note 1)
src
R
20
FO
F1
x**x--
R
IR
R
1M
IR
1M
Lower
Opcode Nibble
0
0
0
W
[§J
[I]
60
145
REGISTERS
R240SI0
SERIAL 1/0 REGISTER
(FOH; Read/Write)
R244 TO
COUNTERITIMER 0 REGISTER
(F4H; Read/Write)
'------SERIAl. DATA (Do "" LSS)
To INITIAL VALUE(WHEN WRITIEN)
'------(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)
R241 TMR
TIMER MODE REGISTER
(F1 H; Read/Write)
T
' "=, M
ODESj
NOT T
usee
00 ~'
~~ g~~ ~ ~~
INTERNAL CLOCK OUT:::: 11
,
US~o
QLCOUNTMOOE
o = To SINGLE-PASS
1 = T(l MODULO-N
NO FUNCTION
1 = LOAD
To
0
= DISABLE To COUNT
1
=
ENABLE,To COUNT
RESERVED
0 = NO FUNCTION
1 =- lOAD 1,
0
DISABLE T, COUNT
T MODES
EXTERNAL CLOCK INP~T
00
GATE INPUT :c: 01
=
(NON.R~~~~8~:~~:~~) =
R245 PREO
PRES CALER 0 REGISTER
(F5H; Write Only)
=
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
1 = ENABLE T, COUNT
10
TRIGGER INPUT .. 11
(RETRIGGERABLE)
R242 T1
COUNTER TIMER 1 REGISTER
(F2H; Read/Write)
R246 P2M
PORT 2 MODE REGISTER
(F6H; Write Only)
P2 o-P2 7 110 DEFINITION
L -_ _ _ 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
T, INITIAL VALUE (WHEN WRITTEN)
'-----(AANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)
R243PRE1
PRESCALER 1 REGISTER
(F3H; Write Only)
~L
COUNTMODE
o ;; 1, SINGLE·PASS
1 = T, MODULC·N
CLOCK SOURCE
1
.
R247P3M
PORT 3 MODE REGISTER
(F7H; Write Only)
=:
~.~
(TIN) MODE
PRESCALER MODULO,
(RANGE: 1-64 DECIMAL
01-00 HEX)
P34 = OUTPUT
~ ~}P33
= INPUT
P34 = I5"M
1 1 P33 '" IlAVirRDY1 P34 = RDY1rDAVl
L-_ _ _ _ _ _ ~
'--________
146
P33 = INPUT
00
L-_ _ _ _ _ _ _
Figure 11. Control Registers
RESERVED
o P32
:= INPUT
P3S ;= OUTPUT
1 P32 = DA'VOJROYO P3S '" RDYO/DAVO
T, INTERNAL
0 = T, EXTERNAtTtMING INPUT
,
o1 PORT
PORT 2 PULL·UPS ~PEN DRAIN
2 PULL·UPS ACTIVE
~~~ ~ ~N:VU;~~I~~ =;~
: ~~~~~{ifUT)
~=~~ ~ ~N:R~rLIN =~~ ~ ~~~iAULTOUT
~ =~=:~~ g~F
REGISTERS (Continued)
R252 FLAGS
FLAG REGISTER
(FCH; Read/Write)
R248 P01M
PORT 0 AND 1 MODE REGISTER
(F8H; Write Only)
-.J
PD.-PO, MOOE:]
OUTPUT '" 00
INPUT
01
=
E~
L
1
ll!~~
PO,-PO,
MOOE
00 "" OUTPUT
=
01
. AI2-A,s "" 1X
L
INPUT
1X "" A,_A"
EXTERNAL MEMORY TIMING
NORMAL "" 0
1
EXTENDED
STACK SELECTION
0 :c: EXTERNAL
1
INTERNAL
=
=
LUSER FLAG F1
USER FLAG F2
HALF CARRY FLAG
DECIMAL. ADJUST FLAG
OVERFLOW FLAG
SIGN flAG
P1 o-P1 7 MODE
00 = BYTE OUTPUT
ZERO FLAG
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7.
CARRY FLAG
AS, OS, R/W, As-A,,, A,2-A,s
IF SELECTED
R253 RP
REGISTER POINTER
(FDH; Read/Write)
R2491PR
INTERRUPT PRIORITY REGISTER
(F9H; Write Only)
I~I~I~I~I~I~I~I~I
..-~ I I III ,~. ""O~
...~n
RESERVED =; 000
C > A > 8 = 001
IRQ3., IROS PRIORITY (GROUP A)
o " IRQS > IRQ3
1 = IRQ3 > IR05
A > B > C = 010
_
A > C > B =
B> C > A =
c > B > A =
B> A > C =
RESERVED'=
IRaQ, IRQ2 PRIORITY (GROUP B)
= IRQ2 > IROO
1 = IROO > IRQ2
o
LOON'TCARE
REGISTER
POINTER
011
100
101
110
111
IRQt, IRQ4 PRIORITY (GROUP C)
=: IRQ1 > IRQ4
1 =: IRQ4 > IRQ1
o
R250lRQ
INTERRUPT REQUEST REGISTER
(FAH; Read/Write)
R254SPH
STACK POINTER
(FEH; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED
c=-=
I
=
IRoa "" P3z INPUT (00
IRQO)
IRQ1
P331NPUT
IRQ2
P31 INPUT
IRQ3 = P30 INPUT. SERIAL INPUT
IR04 = To. SERIAL OUTPUT
IROS .. T1
=
=
R2511MR
INTERRUPT MASK REGISTER
(FBH; Read/Write)
R255SPL
STACK POINTER
(FFH; Read/Write)
·I~I~I~I~I~I~I~I~I
II
c=-=
1 ENABLES IRQO-IRQS
(00
IROO)
=
L-------RESERVED
L - - - - - - - - - 1 ENABLES INTERRUPTS
Figure 11. Control Registers (Continued)
147
OPCODEMAP
Lower Nibble (Hex)
o
3
5
6
7
8
9
A
C
B
.. _ , - - - -
65
DEC
R,
65
DEC
IR,
6.5
ADD
6.5
RLC
R,
6.5
RLC
'R,
6,5
INC
R,
6,5
INC
IR,
3
8,0
JP
IRR,
6.5
ADD
f" lr 2
10.5
ADD
R2· R,
10.5
ADD
IR2·R,
10.5
ADD
R,.IM
10.5
ADD
IR,.IM
6.5
ADC
6.5
ADC
f,.f2
f,.lr2
10.5
ADC
R2· R,
10.5
ADC
IR2·R,
10.5
ADC
R,.IM
10.5
ADC
IR"IM
6,5
SUB
f,.f2
6,5
SUB
f,. lr2
10,5
SUB
R2,R,
10,5
SUB
IR2,R,
10,5
SUB
R,.IM
10,5
SUB
IR"IM
6,1
SRP
1M
6,5
SBC
6,5
SBC
10,5
SBC
R2,R,
10,5
SBC
IR2,R,
10,5
SBC
R"IM
10,5
SBC
IR"IM
4
8.5
DA
R,
8.5
DA
IR,
6,5
OR
(,.f2
6,5
OR
10,5
OR
R2,R,
10,5
OR
IR2,R,
10,5
OR
R"IM
10,5
OR
IR"IM
5
10,5
POP
R,
10,5
POP
IR,
6.5
AND
T,.f2
6,5
AND
lr2
10,5
AND
R2,R,
10,5
AND
IR2,R,
10,5
AND
R,.IM
10,5
AND
IR,.IM
6
6,5
COM
R,
6,5
COM
IR,
6,5
TCM
6,5
TCM
r,,1r2
10,5
TCM
R2,R,
10,5
TCM
1R2,R,
10,5
TCM
R,.IM
10,5
TCM
IR"IM
10112,1
PUSH
R2
12114,1
PUSH
IR2
6,5
TM
6,5.
TM
lr2
10,5
TM
R2,R,
10,5
TM
IR2,R,
10,5
TM
R,.IM
10,5
TM
IR,.IM
10,5
DECW
RR,
10,5
DECW
IR,
6.5
RL
R,
10,5
INCW
RR,
B
C
o
Ii'
..
:c
~ 7
r
f,.f2
".f2
r,.f2
f"
f,.
12,0
LDE
18,0
LDEI
f,.Irr2
Ir,. lrr2
6,5
RL
12,0
LDE
lA,
f2· lfr ,
18,0
LDEI
Ir2·Jrr,
10,5
INCW
IR,
6,5
CP
".f2
f,. lr2
10,5
CP
R2,R,
10.5
CP
IR2,R,
10,5
CP
R"IM
10,5
CP
IR"IM
6.5
CLR
R,
6,5
CLR
IR,
6,5
XOR
".f2
6,5
XOR
f,.lr2
10,5
XOR
R2,R,
10.5
XOR
IR2,R,
10,5
XOR
R,.IM
10,5
XOR
IR"IM
6,5
RRC
R,
6,5
RRC
IR,
12,0
LDC
f,.Irr2
18,0
LDCI
Ir,.lrr2
6,5
SRA
R,
6,5
SRA
IR,
12,0
LDC
r2· 1rr ,
18,0
LDCI
Ir2.lrr,
20,0
CALL"
IRR,
E
6,5
RR
R,
6,5
RR
IR,
6,5
LD
r" IR2
10,5
LD
R2,R,
f
8,5
SWAP
R,
8,5
SWAP
6,5
LD
Ir,.f2
z
~
f,.tr2
r,.r2
,Q
D.
D.
f,. lr2
8
:::>
9
A
D
lA,
6.5
LD
6.5
LD
f,.R2
r2· R ,
----
12/10.5
12110.0
DJNZ
r,.RA
JR
6.5
LD
cC.RA
r1· IM
E
D
~---
.-~-
12110.0
JP
cc.DA
6.5
INC
rl
r----r----r----r-----
-
r-----
tG,o
STOP
r----7,0
HALT
~
DI
~
EI
6.5
CP
~
RET
'16:0
IRET
~
10,5
LD
f,.x.A2
10,5
LD
IR2·R,
20,0
CALL
DA
r2· x,R,
10,5
LD
R"IM
10,5
LD
IR"IM
RCF
~
10,5
LD
SCF
~
CCF
~
10,5
LD
R2,IA,
NOP
1.. .----.. . .".----.
..
. -----v-".-----.I1.. .
------v-".------.I~"__..,..___'
.1 '....
2
3
3
Bytes per Instruction
LOWER
OPCODE
NllLE
EXECUTION
CYCLES
PIPELINE
CYCLES
Legend:
R = 8-bil address
r = 4-bil address
Rl or = Ost address
R20"2 = Src address
f,
MNEMONIC
Sequence:
Opcode, Firsl Operand, Second Operand
FIRST
OPERAND
'2-byte Instruction; fetch cycle appears as a 3·byte instruction
148
F
---- -
SECOND
OPERAND
NOTE: The blank areas are not defined.
ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... - O.3V to + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65 D to + 150 D
e
e
>
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
+5V
2.1K
The De characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:
+ 4.SV
. III
~
Vee
~
+S.SV
III GND = OV
!II
oDe ~ TA ~ + 70 De for
S (Standard Temperature)
Figure 12. Test Load 1
DC CHARACTERISTICS
Symbol
Parameter
VCH
. Clock Input High Voltage
VCl
Clock Input Low Voltage
Min
Max
Unit
Condition
3.8
VCC
V
Driven by External Clock Generator
-0.3
0.8
V
Driven by External Clock Generator
2.4
VCC
V
-0.3
0.8
V
3.8
VCC
V
-0.3
0.8
V
VIH
Input High Voltage
Vil
Input Low Voltage
VRH
Reset Input High Voltage
VRl ,
Reset Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
III
Input Leakage
-10
IOl
Output Leakage
-10
IIR
Reset Input Current
ICC
Supply Current
ICC1
ICC2
2.4
V
0.4
10
V
IOH =-250"A
IOl = +2.0mA
"A
OV';;; VIN';;; + 5.25V
10
"A
OV';;; VIN';;; + 5.25V
80
50
"A
mA
Vcc = + 5.25V, VRl = OV
Standby Current
3
mA
Halt Mode
Standby Cwent
10
"A
Stop Mode
All outputs and 1/0 pins floating
149
RIW
PORT 0,
0Ni
00-07 IN
PORT 1
AS
.-----~®r----~~I
______~------------~I.~------~®r---------.I}_--~----Os
(READ)
DO-D7 0Ul
PORT 1
Os ------------------~----~I·~----~0r----~~I)~-------
(WAITE)
Figure 13. External I/O or Memory Read/Write
AC CHARACTERISTICS
External 1/0 or Memory Read and Write Timing
12 MHz
NumberSymbol
Parameter
Min
Max
16 MHz
Min
Max
Notes
TdA(AS)
Address Valid to AS iDelay
35
20
2,3
2
TdAS(A)
AS i to Address Roat Delay
45
30
2,3
3
TdAS(DR)
AS i to Read Data Required Valid
4
TwAS
AS Low Width
5
TdAz(DS)
6
7
8
TdDSR(DR),
OS .1. to Read Data Required Valid
9
ThDR(DS)
Read Data to OS i Hold Time
0
0
2,3
10
TdDS(A)
OS i to Address Active Delay
45
35
2,3
11
TdDS(AS)
OS i to AS .1.Delay
55
25
2,3
12
TdRIW(AS)
RIW Valid to AS i Delay
30
20
2,3
13
TdDS(RIW)
OS i to RIW Not Valid
35
25
2,3
14
TdDW(DSW)
Write Data Valid to OS (Write)! Delay
35
25
2,3
15
TdDS(DW)
OS i to Write Data Not Valid Delay
35
25
200
40
1,2,3
2,3
220
180
1,2,3
55
35
Address Roat to OS .1.
0
0
TwDSR
OS (Read) Low Width
185
135
1,2,3
TwDSW
OS (Write) Low Width
110
80
1,2,3
16 TdA(DR)
17 TdAS(OS)
-
130
--
Address Valid to Read Data Required Valid
AS to OS Delay
255
55
2,3
75
1,2,3
2,3
NOTES:
1. Delay times given are for a 16 MHz crystal input frequency. For lower
frequencies, the change in clock periods must be added to the delay
time.
2. Data Strobe Width is given for a 16 MHz' crystal input frequency. For
lower frequencies the change in three clock periods must be added to
obtain the minimum width. The Data Strobe Width varies according to
the instruction being executed.
3. Address Strobe and Data Strobe to Data In Valid delay times represent
memory system access times and are given for a 16 MHz crystal input
frequency. For lower frequencies, the change in four clock periods
must be added to TdAS (01) and the change in three clock periods
added t~_TdDS(DI).
15tJ
• All units in nanoseconds (ns).
t Test Load 1
o All timing references use 2.0V for a logic "1" and O.BV for a logic "0':
Figure 14. Additional Timing
AC CHARACTERISTICS
Additional Timing Table
NumberSymbol
12 MHz
Parameter
TpC
Input Clocl( Period
2
TrC,TIC
Clock Input Rise and Fall Times
3
TwC
Input Clock Width
16 MHz
Min
Max
Min
Max
S3
1000
62.5
1000
15
70
Notes
10
21
4
TwTinl
Timer Input low Width
70
50
2
5
TwTinH
Timer Input High Width
3TpC
3TpC
2
6
TpTin
Timer Input Period
STpC
STpC
2
7
TrTin,Tmn
Timer Input Rise and Fall Times
SA
Twll
Interrupt Request Input low Time
100
70
50
2,4
S8
Twll
Interrupt Request Input low Time
3TpC
3TpC
3TpC
2,5
9
TwlH
Interrupt Request Input High Time
3TpC
3TpC
3TpC
2,3
STpC
100
NOTES:
1, Clock timing references use 3,8V for a logic "1" and 0,8Vfor a logic "0':
2, Timing references use 2,OV for a logic" 1" and 0,8V for a logic "0':
3, Interrupt request via Port 3,
Z8 OTP
• Units in nanoseconds (ns),
28
D7
7
27
D6
6
26
D5
5
25
D4
: 4 24
D3
3
D2
c.. 2 23
Dl
1 22
DO
21
0
a
"I:
15
2
c.. 1
0
7
6
o 5
~ 4
3
2
1
0
£
2
23
21
24
25
3
4
5
6
7
8
9
10
A9
A8
A7
A6
AS
A4
A3
A2
Al
AO
P31
P30
P27
22
20
27
3 XTAl1 P33
30
1
11
1
28
14
6
-
A12
AU
AlO
vee
GND
100
2
2764A Adapter
19
18
17
16
15
13
12
11
39
5
38
~ RESET
,
35
34
33
32
31
20
19
18
17
16
15
14
13
100
07
06
05
04
03
02
01
00
A12
All
AID
A9
A8
A7
A6
AS
A4
A3
A2
Al
Ao
OE
eE
PGM
VPP
vee
GND
Z80TP
Programm ing Adapter
151
o.:::~ ------0£~,
=~-----(OUTPUTI
FIGure 15a.
Input Handshaka Timing
~-
DATA OUT
DATA OUT VALID
--~~----------------
-.~
DA'V
(OUTPUT)
-0""-'
)1'--;
RDY
!INPUT)
Figura iSb.
Output Hondahoke Timing
AC CHARACTERISTICS
Handshake Timing
12 MHz
NumberSymbol
'TsDI(DAV)
Parameter
Min
Data In Setup Time
Max
0
16 MHz
Min
ThDI(DAV)
Data In Hold Time
160
145
3
TwDAV
Data Available Width
120
110
4
TdDAVlf(RDY)
DAV J.. Input to ROY! Delay
5
TdDAVOf(RDY)
DAV.L Output to RDY.L Delay
6
TdDAVlr(RDY)
DAV i Input to ROY
7
TdDAVOr(RDY) DAV i Output to ROY i Delay
8
TdDO(DAV)
Data Out to DAV J.. Delay
9
TdRDY(DAV)
Rdy .L Input to DAV i Delay
NOTES:
1. Test load 1
2. Input handshake
3. Output handshake
t All timing references use 2.0V for a logic "1" and O.BV for a logic "0':
• Units in nanoseconds (ns).
152
120
0
Delay
115
1,2
1,3
0
120
115
0
0
30
30
0
Notes
0
2
i
Max
140
0
1,2
1,3
130
November 1987
(c:MOS
rni@Mll(p;ss !:~® Miiecm€C@rnmpTmier
~16c~n
FEATURES
[J
Complete microcomputer, 24 I/O lines, and up to 64K
bytes of addressable external space each for program
and data rnernory.
l!lI 256-byte register file, including 236 general-purpose
registers, 3 I/O port registers, and 16 status and control
registers.
Cl
Vectored, priority interrupts for I/O, counter/tirners, and
UART.
l:J On-chip oscillator that accepts crystal or external clock
drive.
13 Full-duplex
UART and two programmable 8-bit
counter/timers, each with a 6-bit programmable
prescaler.
[J
Register Pointer so that short, fast instructions can
access anyone of the sixteen working-register groups.
[J
Single
[J
12 and 16 MHz
+ 5V power supply-all I/O pins TIL compatible.
III CMOS process
o Standby modes-Halt and Stop
GENERAL DESCRIPTION
The Z86C91 is a CMOS ROM less version of the Z8
single-chip microcomputer. It offers all the outstanding
features of the Z8 family architecture except an on-chip
program ROM. Use of external mernory rather than a
TI~::
CONTROL
_
1
RESET
+5V
os
XTAL'
AS
XTAL2
P~
PO,
PORTO
(NIBBLE
PROGRAMMABLE)
I/O OR Ae-A15
po,
po,
P2,
PO,
P2,
po,
P2,
POs
po,
po,
P',
P2,
Z86C91
MCU
P2s
P2,
P2,
P3,
P3,
P3,
PORT'
(BYTE
PROGRAMMABLE)
ADo-AD7
+5V
GND
R/VI
P3,
P3,
P3s
P3,
P3,
Figure 1_ Pin Functions
preprogramrned ROM enables this Z8 microcornputer to be
used in low volume applications or where code flexibility is
required.
PORT 2
(BIT PROGRAMMABLE)
110
P3,
XTAL2
P3,
XTAL'
P2,
P3,
P2,
P3,
P2s
RESET
P2,
RIW
P2,
os
P2,
AS
P2,
P3s
P2,
GND
P3,
P3,
P3,
PO,
P',
PO,
P',
PO,
P's
PO,
P',
PO,
P',
PO s
P',
PO,
P',
Pl,
PO,
Figure 2a. 40·pin Dual·ln-Line Package (DIP),
Pin Assignments
153
The Z86C91 can provide up to 16 output address lines, thus
permitting an address space of up to 64K bytes of data or
program memory. Eight address outputs (ADo-AD7) are
provided by a multiplexed, 8-bit, Address/Data bus. The
remaining 8' bits can be provided by the software
configuration of Port 0 to output address bits Aa-A15'
There are 256 bytes of RAM located on-chip and organized
as a register file of 236 general-purpose registers, 16 control
and status registers, and three I/O port registers. This
register file can be divided into sixteen groups of 16 working
registers each. Configuring the register file in this manner
allows the use of short format instructions; in addition, any of
the individual registers can be accessed directly.
Available address space can be doubled (up to 128K bytes)
by programming bit 4 of Port 3 (P34) to act as a data memory
select output (OM). The two states of OM together with the
16 address outputs can define separate data and memory
address spaces of up to 64K bytes each.
6
5
4
3
The pin functions and the pin assignments of the Z86C91
package are illustrated in Figures 1 and 2.
2
1 44 43 42 41 40
Il£SET 7
39
NC
R/W
8
38
P2,
os
9
37
P23
AS
10
36
P2,
35
P2,
34
P2,
P3s
11
GND
12.
P3,
13
33
P33
PO,
14
32
P3,
PO,
15
31
P1T
PO,
16
30
Pl.
NC
17
29
P1s
Z88C91
MCU
18 19 20 21 22 23 24 25 26 27 28
qt:;":1 qt:;~q<:ltt, ~ qt:;'\--
~~I--
IR05
:r-
IRQ4
r-
IR03
-
!~
IR02
-
r-
IR01
-
~r-
IROO
-
INTERRUPT
7
VECTOR
(LOWER BYTE) '-..6
INTERRUPT
VECTOR ....- 3
2
(UPPER BYTE)
-
Figure 4. Z86C91 Program Memory Map
DECIMAL
255
STACK POINTER (BITS 7-0)
HEX
IDENTIFIERS
FF
SPL
SPH
STACK POINTER (BITS 15-8)
FE
253
REGISTER POINTER
FD
RP
252
PROGRAM CONTROL FLAGS
Fe
FLAGS
251
INTERRUPT MASK REGISTER
FB
IMR
250
INTERRUPT REOUEST REGISTER
FA
IRO
249
INTERRUPT PRIORITY REGISTER
F9
IPR
248
PORTS 0-1 MODE
F8
P01M
247
PORT 3 MODE
F7
P3M
246
PORT 2 MODE
F6
P2M
245
TO PRESCALER
F5
PREO
244
TIMER/COUNTER 0
F4
TO
243
T1 PRESCALER
F3
PREl
242
TIMER/COUNTER 1
F2
T1
241
TIMER MODE
Fl
TMR
240
239
SERIAL I/O
FO
SIO
254'
1_-..-{fJ::
. t--=-,-=}_:=:...=.:.. =_~.J..=_=_=_=_=_=_=_=1;:::
~
____________________~240
THE UPPER NIBBLE OF THE REGISTER
FILE ADDRESS PROVIDED BY THE
REGISTER POINTER SPECIFIES THE
ACTIVE WORKING-REGISTER GROUP.
---{
2 39
··
EF
SPECIFIED WORKING·
REGISTER GROUP
GENERAL·PURPOSE
REGISTERS
--+-
04
PORT 3
03
P3
PORT 2
02
P2
PORT 1
01
Pl
PORT 0
00
PO
Figure 5. The Register File
156
--I-
--
--{
1
~---I/OPORTS----- 3
0
Figure 6. The Register POinter
THE LOWER
NIBBLE OF
THE REGISTER
FILE ADDRESS
PROVIDED BY
THE INSTRUCTION
POINTS TO THE
SPECIFIED
REGISTER.
SERIAL INPUT/OUTPUT
Port 3 lines P30 and P37 can be programmed as serial 1/0
lines for full-duplex serial asynchronous receiverltransmitter
operation. The bit rate is controlled by CounterlTimer D, with
a maximum rate of 93.75K bitslsecond at 12 MHz.
The Z86C91 automatically adds a start bit and two stop bits
to transmitted data (Figure 7). Odd parity is also available as
an option. Eight data bits are always transmitted, regardless
of parity selection. If parity is enabled, the eighth data bit is
used as the odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight data bits, and at
least one stop bit. If parity is on, bit 7 of the received data is
replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.
I·I~I~I~I~I~I~I~I~I~I
1
I
LSTART BIT
' - - - - - - E I G H T DATA BITS
I
TWO STOP BITS
- - - - - - - - - O N E STOP BIT
L,
Transmitted Data
(No Parity)
Received Data
(No Parity)
1·1·1 pl~I~I~i~I~I~I~I~1
TL
LSTART BIT
' - - - - - - E I G H T DATA BITS
1·lpl~I~I~I~I~I~I~I~1
II,_ _
_LSTARTBIT
' - - - - - - ' - ' SEVEN DATA BITS
LSTARTBIT
' - - - - - - - S E V E N DATA BITS
ODD PARITY
PARITY ERROR FLAG
TWO STOP BITS
' - - - - - - - - - - - - - - O N E STOP BIT
Received Data
(With Parity)
Transmitted Data
(With Parity)
Figure 7. Serial Data Formats
COUNTERITIMERS
The
Z86C91
contains
two
8-bit
programmable
counterltimers (To and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler can be driven by
internal or external clock sources; however, the To prescaler
is driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256) that
has been loaded into the counter. When the counter reaches
the end of count, a timer interrupt request-IRQ4 (To) or
IRQ5 (T1)-is generated.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. The counters can also be
programmed to stop upon reaching zero (single-pass mode)
or to automatically reload the initial value and continue
counting (modulo-n continuous mode). The counters, but not
the prescalers, can be read any time without disturbing their
value or count mode.
The clock source for T1 is user-definable; it can be either the
internal microprocessor clock divided by four, or an external
signal input via Port 3. The Timer Mode register configures
the external timer input as an external clock, a trigger input
that can be retriggerable or nonretriggerable, or as a gate
input for the internal clock. The counterltimers can be
programmably cascaded by connecting the To output to the
input of T1. Port 3 line P36 also serves as a timer output
(TOUT) through which To, T1 or the internal clock can be
output.
I/O PORTS
The Z86C91 has 24 lines available for input and output.
These lines are grouped into three ports of eight lines each
and are configurable as input, output or address. Under
software control, the ports can be programmed to provide
address outputs, timing, status signals, serial 1/0, and
parallel 1/0 with or without handshake. All ports have active
pull-ups and pull-downs compatible with TIL loads.
157
Port 1 is a dedicated Z-8US® compatible memory
interface. The operations of Port 1 are supported by the
Address Strobe (AS) and Data Strobe (DS) lines, and by
the Read/Write (R/W) and Data Memory (DM) control
lines. The low-order program and data memory addresses
(Ao:A7) are output through Port 1 (Figure 8) and are
multiplexed with data in/out (Do-D7). Instruction fetch and
data memory readlwrite operations are done through this
port.
Port 1 cannot be used as a register nor can a handshake
mode be used with this port.
least-significant four bits of Port 0 can be configured to
supply address bits As-A11 for 4K byte addressing or both
nibbles of Port 0 can be configured to supply address bits
As-A15 for 64K byte addressing.
)----;---\ PORT 1
(I/O OR ADo·AD7)
~
The Z86C91 wakes up with the 8 bits of Port 1 configured
as address outputs for external memory. If more than eight
address lines are required, additional lines can be
obtained by programming Port 0 bits as address bits. The
Port 0 can be programmed as a nibble 1/0 port, or as an
address port for interfacing external memory (Figure 9).
When used as an I/O port, Port 0 can be placed under
handshake control. In this configuration, Port 3 lines P32
and P35 are used as the handshake controls DAVo and
RDY o. Handshake signal assignment is dictated by the 1/0
direction of the upper nibble P04-P07'
For external memory references, Port 0 can provide
address bits Aa-A11 (lower nibble) or Aa-A15 (lower and
upper nibbles) depending on the required address space.
If the address range requires 12 bits or less, the upper
nibble of Port 0 can be programmed independently as 1/0
while the lower nibble is used for addressing.
Figure 8. Port 1
To permit the use of slow memory, an automatic wait'mode
of two oscillator clock cycles is configured for bus timing
after each reset. The initialization routine could include
reconfiguration to eliminate this extended timing mode.
Port 3 can also provide the following control functions:
handshake for Ports 0 and 2 (DAV and RDY); four external
interrupt request signals (IRQO-IRQ3); timer input and
output signals (TIN and TOUT) and Data Memory Select
(DM).
158
} PORT 0
(I/O OR A,-A15)
_ _ } HANDSHAKE CONTROLS
DAV, AND RDYo
(PS, AND P3 s)
Figure 9. Port 0
---
...........
Z86C91
MCU
Like Port 0, Port 2 may also be placed under handshake
control. In this configuration, Port 3 lines P3 1 and P3e are
used as the handshake controls lines DAV 2 and RDY 2.
The handshake signal assignment for Port 3 lines P3 1 and
P3e is dictated by the direction (input or output) assigned
to bit 7 of Port 2.
Port 3 lines can be configured as I/O or control lines
(Figure 11). In either case, the direction of the eight lines is
fixed as four input (P30-P33) and four output (P34-P37)' For
serial I/O, lines P30 and P37 are programmed as serial in
and serial out, respectively.
P04- P07
} POo-POs
Z66C91
MCU
Port 0 lines are configured as address lines As-A15 after a
Reset. If one or both nibbles are needed for I/O operation,
they must be configured by writing to the Port 0 Mode
register.
Port 2 bits can be programmed independently as input or
output (Figure 10). This port is always available for I/O
operations. In addition, Port 2 can be configured to
provide open-drain outputs.
TO EXTERNAL
MEMORY
Z86C91
MCU
...........
-.........
---
P20
PORT 2(1/0)
P27
_ _ ) HANDSHAKE CONTROLS
DAV2 AND RDY2
(P3, AND PS,)
Figure 10. Port 2
Z88C91
MCU
--
...-
PORT 3
(1/0 OR CONTROL)
Figure 11. Port 3
INTERRUPTS
The Z86C91 allows six different interrupts from eight
sources: the four Port 3 lines P30-P33, Serial In, Serial Out,
and the two counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask register
globally or individually enables or disables the six interrupt
requests. When more than one interrupt is pending, priorities
are resolved by a programmable priority encoder that is
controlled by the Interrupt Priority register.
All interrupts are vectored through locations in program
memory. When an interrupt request is granted, an interrupt
machine cycle is entered. This disables all subsequent
interrupts, saves the Program Counter and status flags, and
accesses the program memory vector location reserved for
that interrupt. This memory location and the next byte
contain the 16-bit address of the interrupt service routine for
that particular interrupt request. The Z86C91 takes 26
system clock cycles to enter an interrupt subroutine.
Polled interrupt systems are also supported. To
accommodate a polled structure, any or all of the interrupt
inputs can be masked and the Interrupt Request register
polled to determine which of the interrupt requests needs
service.
CLOCK
The on-chip oscillator has a high-gain, parallel-resonant
amplifier for connection to a crystal or to any suitable
external clock source (XTAL 1
Input, XTAL2
Output).
=
=
The crystal source is connected across XTAL 1 and XTAL2,
using the recommended capacitance (CL
15 pf
maximum) from each pin to ground. The specifications for
the crystal are as follows:
=
I!!J AT cut, parallel-resonant
El Fundamental type
Iii! Series resistance, Rs ~ 100Q
121 16 MHz maximum
159
INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations
as shown in the instruction summary.
IRR
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Symbols. The following symbols are used in describing the
instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol "<-': For
example,
dst <- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the following six
flags:
C
Z
S
V
o
H
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:
o
1
*
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
CONDITION CODES
160
Value
Mnemonic
1000
0111
1111
0110
1110
1101
0.101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
Flags Set
C= 1
C=O
Z= 1
Z=O
8=0
8= 1
V= 1
V=O
Z= 1
Z=O
(8 XOR V) = 0
(8XORV) = 1
[ZOR(8XORV)] = 0
[ZOR(8XORV)] = 1
C;"O
C= 1
(C = 0 AND Z = 0) = 1
(CORZ) = 1
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC
dsl
INC r
OPC
One-Byte Instructions
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
CLR, CPL, DA, DEC,
'----"'=-'-------' OR
I, , , 01 dsllsre 1 ~~~~'~~~Rl~~:R;OP'
RRC, SRA, SWAP
I
OPC
f--::.:dS-','----l OR
I, , ,01
JP, CALL (Indirect)
ds'
f - - - = - - - - 1 OR
I, , ,01
dst
ADC, ADD, AND, cp,
LD, OR, SBC, SUB,
TCM, TM, XOR
SRP
OPC
VALUE
LD
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
LD
LD, LDE, LDEI,
LDC, LOCI
LD
L---==:::':""-.-J OR
I, , '01
JP
sre
LD
ds' 1 OPC
VALUE
CALL
I
DJNZ, JR
dsllCC 1 OPC
,
RA
STOP/HALT
Three-Byte Instructions
Two-Byte Instructions
Figure 12. Instruction Formats
INSTRUCTION SUMMARY
AddrMode
Instruction
and Operation
dst
src
Opcode
Byte
(Hex)
Flags Affected
AddrMode
dst
DECdst
dst ..... dst - 1
R
IR
00
01
-***--
RR
IR
80
81
-***--
1D
'* '* '*
ADDdst,src
dst ..... dst + src
(Note 1)
OD
****0*
DECWdst
dst ..... dst - 1
ANDdst,src
dst ..... dst AN D src
(Note 1)
5D
-**0--
DI
IMR (7) +- 0
+C
Flags Affected
CZSVDH
(Note 1)
ADCdst,src
dst ..... dst + src
Opcode
Byte
(Hex)
Instruction
and Operation
*
0 *
CALLdst
DA
Sp ..... Sp - 2
IRR
@sp +- PC; PC +- dst
D6
D4
------
CCF
C ..... NOTC
EF
*-----
CLRdst
dst ..... O
R
IR
80
81
------
COM'dst
dst +- NOT dst
R
IR
60
61
-**0--
(Note 1)
AD
****--
DAdst
dst ..... DAdst
R
IR
40
41
***x--
rA
r=O-F
EI
IMR(7) ..... 1
9F
HALT
7F
+1
R
IR
INCWdst
dst +-dst + 1
C Z S V D H
8F
DJNZr,dst
RA
r+- r - 1
ifr",O
PC"'" PC + dst
Range: + 127, -128
INCdst
dst ..... dst
CPdst,src
dst - src
src
rE
-***-r= 0 - F
20
21
RR
IR
161
INSTRUCTION SUMMARY (Continued)
Addr Mode
Instruction
and Operation
dst
src
Opcode
Byte
(Hex)
IRET
BF
FLAGS .... @SP; Sp .... SP + 1
PC .... @SP; SP .... Sp + 2; IMR(7) .... 1
JP cC,dst
if cc is true
PC .... dst
DA
Flags Affected
C Z S V D H
******
JR cC,dst
RA
if cc is true,
PC"" PC + dst
Range: + 127, -128
r
cB
1m
R
rC
r8
r9
r
X
X
r
SRA dst
r
Ir
E3
Ir
r
R
F3
IR
1M
1M
F5
LDCI dst,src
dst .... src
r .... r + 1; rr .... rr
1
Ir
Irr
Irr
Ir
C3
Irr
82
92
LDEI dst,src
dst .... src
r .... r + 1; rr <- rr
Ir
Irr
Irr
Ir
83
93
ORdst,src
dst .... dst OR src
(Note 1)
40
POPdst
dst .... @SP;
Sp .... Sp + 1
R
IR
50
IR
-**0--
r-==l
R
(Note 1)
71
90
91
DF
1-----
DO
* * '*
0
31
20
FO
F1
X**X--
60
-**0--
TM dst,src
dstAND src
(Note 1)
70
-**0--
XORdst,src
dst .... dst XOR src
(Note 1)
BO
-**0--
AddrMode
dst
src
Ir
0-----
AF
0~IR
30
For example, the opcode of an ADC instruction using the
addressing modes r (destination) and Ir (source) is 13.
C .... O
+2
****--
NOTE: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above. The second nibble is expressed
symbolically by a 0 in this table, and its value is found in the
following table to the left of the applicable addressing mode pair.
70
CF
CO
(Note 1)
51
R
* * '* *
TCM dst,src
(NOTdst)ANDsrc
FF
NOP
EO
E1
6F
52
+1
RET
PC .... @SP; SP .... SP
1m
D3
r
Irr
****--
D1
D2
LDEdst,src
dst .... src
RCF
R
IR
SWAPdst I'
R
"-."",~-,--,-,-,'IIR
E7
C2
LriJ @
SUBdst,src
dst .... dst .... src
E5
E6
R
PUSH src
Sp .... Sp - 1; @Sp .... src
(Note 1)
C Z S V D H
10
11
C1
STOP
E4
Irr
162
~-~IR
SRPsrc
Rp .... src
C7
D7
r
Irr
RL dst
r=--==:=l R
SCF
LDCdst,src
dst .... src
+
L[ri, LEj]J
R
,
, IR
Flags Affected
C .... 1
r==O-F
IR
IR
RR dst
~IR
SBCdst,src
dst .... dst .... src .... C
c==O-F
R
R
R
R
r-=----=:=-l R
RRC dst
30
IRR
Addr Mode Opcode
Byte
dst src
(Hex)
RLC dst
cD
c==O-F
LDdst,src
dst .... src
Instruction
and Operation
****--
R
R
R
IR
R
1M
IR
1M
Lower
Opcode Nibble
REGISTERS
R240SI0
Serial 110 Register
R244 TO
Counter/Timer 0 Register
(FOH: Read/Write)
(F4H: Read/Write)
L-_ _ _ SERIAL DATA (Do "" lSB)
\
R245 PREO
Prescaler 0 Register
R241 TMR
Time Mode Register
(F1
NOT To"MaDES
USED'" 00
i~ g~i ~ ~~
INTERNAL CLOCK OUT = 11
j
H: Read/Write)
(F5H: Write Only)
llii~o
~
= NOFUNCTION
1 '"
LOAD To
0 '" DISABLE To COUNT
1 = ENABLE To COUNT
T MODES
EXTERNAL CLOCK INPI~T = 00
GATE INPUT = 01
(NON.R~~~~~~~~~:~~) =
TRIGGER INPUT
(RETRIGGERABLE)
~L
o '" To SINGLE·PASS
1 = To MODUlO·N
RESERVED (MUST BE 0)
0 "" NO FUNCTION
1 = LOAD 1,
0 = DISABLE 1, COUNT
10
caUNTMaDE
PAESCAlER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
1 '" ENABLE T, COUNT
= 11
R242 T1
Counter Timer 1 Register
R246 P2M
Port 2 Mode Register
(F2H: Read/Write)
(F6H: Write Only)
I, INITIAL VALUE (WHEN WRITTEN)
' - - - - f R A N G E 1 256 DECIMAL 01 00 HEX)
T, CURRENT VALUE (WHEN READ)
R243 PRE1
Prescaler 1 Register
R247 P3M
Port 3 Mode Register
(F3H: Write Only)
(F7H: Write Only)
~L
caUNTMODE
1 '" 1, MODUlO·N
T! SINGlE·PASS
o=
~L
o
Tl INTERNAL
1, EXTERNAL
TIMING INPUT
. ..• ...
.." .,
(T'N) MODE
"
PRESCAlEA MODULO
01~OO
HEX)
0 PORT 2 PULL UPS OPEN DRA'N
1 PORT 2 PUll UPS ACTIVE
RESERVED (MUST BE 0)
CLOCK SOURCE
1
.
I
~ ~~~ - ~:V~;RDYO ~~~
P33 - INPUT
00
1~}P33=INPUT
~
11
~~~~I~~VO
P34
OUTPUT
P34
OM
RESERVED
o P3,
INPUT (TIN) P36 = OUTPUT {Toud
1 P31 = DAV2/RDY2 P36 = RDY2/Dru
o P30
"' INPUT
1 P30 -- SERIAL IN
P37
P37
OUTPUT
SERIAL OUT
L-_ _ _ _ _ _ _ _ ~ ~:=:i~ g~F
Figure 13. Control Registers
163
R248P01M
Port 0 Mode RegIster
R252 FLAGS
Flag Register
(F8H; Write Only)
(FCH; Read/Wnte)
MODE~ ~----r
L
PO•• PO, = 00
OUTPUT
INPUT = 01
PO,·po,
MODE
00 = OUTPUT
01 = INPUT
AI2 -A ,S = lX
lX = Aa-A\1
EXTERNAL
STACK SELECTION
MEMORY TIMING
NORMAL = 0
*EXTENOEO = 1
0 '" EXTERNAL
1 = INTERNAL
I
~~~
LUSERFLAG"
LUSER FLAG F2
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
RESERVED (MUST BE 0)
CARRY FLAG
·ALWAYS EXTENDED TIMING AFTER RESET
R2491PR
Interrupt Priority Register
R253 RP
Register Pointer
(F9H: Write Only)
(FDH; Read/Write)
l~t~t~t~I~I~t~t~1
"""" ~ I I III '"""""
IRQJ, IROS PRIORITY (GROUP A)
IROS > IRC3
1 "- IRQ3 :;, IROS
o"
IROO, lRQ2 PRIORITY (GROUP B)
= IR02 :> IROO
.
o
1
LOON'TCARE
RESERVED '" 000
C :;, A > B = 001
•
IROO > IR02
.
0_ .."""
A > B > C = 010
A > C > B = 011
B :;, C > A = 100
> B :;, A = 101
B :;, A > C = 110
RESERVED = 111
C
IRQl, IR04 PRIORITY (GROUP C)
o ~ IRQ1 > IRQ4
1 = IRQ4 :> IR01
i
R250lRQ
Interrupt Request Register
R254SPH
Stack Pointer
(FAH; Read/Write)
(FEH; Read/Write)
RESERVED (MUST BE 0)
T
C::='RQO
IRQ1
IR02
IRoa
IR04
lAOS
P32 INPUT (Do '" IRCO)
P331NPUT
P3l INPUT
PJo INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T,
R2511MR
Interrupt Mask Register
R255SPL
Stack Pointer
(FBH; Read/Write)
(FFH; Read/Write)
Il___
C::=
___ 1
ENABLES IRCO-IROS
(00:: IROO)
RESERVED (MUST BE 0)
' - - - - - - - - 1 ENABLES INTERRUPTS
Figure 13. Control Registers (Continued)
164
OPCODEMAP
Lower Nibble (Hex)
o
2
3
A
B
C
o
E
6.5
12/10.5
12/10.0
6.5
12/10.0
6.5
LO
LO
OJNZ
JR
LO
JP
INC
f,.R2
f2·Rl
r"RA
cc,RA
f1·IM
cC.DA
rl
7
2
6.5
10.5
10.5
10.5
10.5
6.5
6.5
6.5
DEC
DEC
ADD
ADD
ADD
ADD
ADD
ADD
R,
IR,
f1· f2
[1.1r2
R2· R,
IR2,R,
R"IM
IR"IM
6,5
6.5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
AOC
AOC
AOC
AOC
AOC
AOC
IR"IM
R,
IR,
'1·'2
[1,1r2
R2,R,
IR2,R,
R"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR"IM
R,
IR,
f1·'2
f1,1r2
R2,R,
IR2,R,
R"IM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRR,
1M
f1.r2
f1.1r2
R2,R,
IR2,R,
R"IM
IR"IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
OA
OA
OR
OR
OR
OR
OR
OR
IR"IM
6.5
F
-
-
-
-~
4
5
.
6
.,
e..
.!!
'"'"z
~
D-
7
8
C.
:::>
9
A
B
C
0
E
F
R,
IR,
'1,(2
f1.lr2
R2,R,
IR2,R,
R"IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
iR"IM
R,
IR,
f1.(2
f1, lr2
RZ,R,
IR2,R,
R"IM
6,5
6,5
6,5
6,5
- 10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
R,
IR,
rl.r2
'1. lr2
A2,R,
IR2,R,
R"IM
IR"IM
10112,1
12114,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
R2,R,
IRZ,R,
R"IM
IR"IM
R2
IR2
(1. r2
f1, lr2
10,5
10,5
12,0
18,0
OECW
OECW
LOE
LOEI
RR,
IR,
f1, lrr2
If1,lrr2
6,5
6,5
12,0
18,0
RL
RL
LOE
LOEI
R,
IR,
'2, lrr 1
Ir2,lrr,
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
INCW
INCW
CP
CP
CP
CP
CP
CP
RR,
IR,
f1,f2
fl.tr2
R2,R,
IR2,R,
R"IM
IR"IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
R,
IR,
'1,(2
(1, lr2
R2,R,
IR2,R,
R"IM
IR"IM
12,0
:----
-
6,0
STOP
7,0
HALT
-
6.1
DI
~
EI
6,5
6,5
RRC
RRC
LOC
LOCI
LO
R,
IR,
'1. lrr2
Ir1.lrr2
18,0
fl,X,R2
-
14,0
RET
---;(3.()
IRET
-
10,5
6,5
RCF
6,5
6,5
18,0
20,0
20,0
10,5
~
SRA
SRA
LOC
LOCI
CALL"
CALL
LO
SCF
R,
iR,
f2. lfr ,
Ir2,lrr,
IRR,
DA
f2,x,Rl
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
RR
LO
LO
LO
LO
LO
R,
IR,
r" IR 2
RZ,R,
IR2,R,
R"IM
IR"IM
8,5
8,5
6,5
10,5
6,0
SWAP
SWAP
LO
LO
NOP
R,
IR,
Ir,.r2
R2,IR,
12,0
-
6,5
CCF
,..----
'....- - - -...v_".---~-",1'....- - - -...
v_".-----",1'-....------v_,.------",1~.~
2
3
2
3
Bytes per Instruction
LOWER
OPCODE
NllLE
EXECUTION
CYCLES
PIPELINE
CYCLES
Legend:
R
r
= 8-bit address
= 4·bit address
= OS! address
R2 or r2 = Src address
R, orr,
MNEMONIC
Sequence:
Opcode, First Operand, Second Operand
FIRST
OPERAND
SECOND
OPERAND
NOfE: The blank areas are not defined,
"2·byte instruction: fetch cycle appears as a 3·byte instruction
165
ABSOLUTE MAxiMUM RATINGS
Voltages on all pins except RESET
with respect to GND ............... - 0.3V to + 7.0V
Operating Ambient
Temperature ...............See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
+5V
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:
•
+4.5V"; Vcc"; +5.5V
Ill!
GND = OV
• O°C"; TA"; + 70°C for S (Standard temperature)
•
-40°C"; TA"; + 100°C for E (Extended temperature)
Figure 14. Test Load 1
DC CHARACTERISTICS
Typ
Symbol
Parameter
VCH
Clock Input High Voltage
3.8
Vcc
V
Driven by External Clock Generator
VCl
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Input Low Voltage
-0.3
VCC
0.8
V
Vil
VRH
Reset Input High Voltage
3.8
Vcc
V
VRl
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
III
Input Leakage
-10
IOl
Output Leakage
-10
IIR
Reset Input Current
ICC
Supply Current
ICCt
Standby Current
ICC2
Standby Current
166
Min
Max
2.4
Vee -100mV
0.4
10
Unit
Condition
V
V
IOH = -250~
V
lee
= -100IlA
V
IOl = +2.0rnA
~
VIN = OV, 5.25V
= OV, 5.25V
10
~
VIN
-50
I1A
Vcc = + 5.25V, VRL = OV
30
mA
All outputs and 1/0 pins floating
5
10
rnA
Halt Mode
~
Stop Mode
).
PORT 0,
)l
DM
~
K
-®-I
I
)(
16
3
)l
PORT 1
AO-A7
~
~I
~
DS
PORT 1
Ao-A7
..
®
DS
.~
--®-
)(
.~
.}(
Do-D7 OUT
....-@-I
-y
I
't
(WRITE)
~1\
•
®
~
(READ)
<
...... 01--
kD+ -I, EPRl:l>I, or RAM.
The 62K bytes of data memory are also located external to tne 28 and begin with location
2048. The two address spaces, program memory
and data memory, are individual.!r. selected by
the Data Memory Select output (IM) which is
available from 'Port 3.
The Program Memory Map and the Data Memory
(>lap are shown in Figure 2.
'
Program Memory Map
Data Memory Map
65535'------,
65535
EXTERNAL
ROM OR RAU
"""
2."
LOCATION OF FIRST
BVTE OF INSTRUCTION
EXECUTED AFTER RESET
ON-CHIP
ROM
~ F.;------------
,.
12
11
INTERRUPT VECTOR
ilOWER BYTE)
,
INTERRUPT VECTOR
(UPPER BYTE
•
•
•
• r,
7
·
2
1
•
EXTERNAL
DATA
UEt.lQRV
IROS
Port 0 is used to provide the addit10nal
address bits for external memory beyond the
first 256 locations up to a full l6-bits of
external memory address. It becomes immediately
obvious that the first 8-bits of external memory
address from Port 1 must be latched externally
to the Z8 so that program or data may be transferred over the same 8 lines during the external
memory transaction machine cycle. The 7iJJ, IlS",
and R/W control lines simplify the required
interface logic. The timing for external memory
transactions is given in Figure 3.
Reg1sters
The Z8 has 144 a-bit registers including
four Port registers (RO-R3), 124 general purpose
registers (R4-R127), and 16 control and status
register (R240-R255). The 144 registers are all
located in the same 8-bit address space to allow
any Z8 instruction to operate on them. The 124
general purpose registers can function as accumulators, address pointers, or index registers.
The registers are read When they are referenced
as source registers, and written when they are
referenced as destination registers. Registers
may be addressed directly with an 8-bit address,
or indirectly through another register with an
8-bit address, or W1th a 4-oit address and Register Pointer.
IROS
IROt
IRO..
IRa3
IRQ3
IRQ2
IRQ2
IROl
IR01
IROO
~:~ 1------.....;
NOT ADDRESSABLE
'ROO
Figure 2 Program Memory Map And Data Memory Map
The entire Z8 register space may be divided
into 16 contiguous Working Register Areas, each
having 16 registers. A control register, called
the Register Pointer, may be loaded with the
most significant nibble of a·Working Register
Area address. The Register P01nter provides for
the selection of the WorKing Register Area, and
allows registers within that area to be selected
with a 4-bit address.
The Z8 register organization is shown in
Figure 4.
Stacks
External memory access is accomplished by
the Z8 through its !f0 Ports. When less than
256 bytes of external memory are required, Port
1 is programmed for the multiplexed address/data
mode LAD0-AD7). In this configurat10n 8-bits qf
address and 8-bits of data are time multiplexed
on the 8 I/O lines for memory transfers. Tne
memory "nandshake" control lines are provided by
tne Address Strobe %J, Data Strobe (US), and
the Read/Wri te (R/W) pins on tne Z8. If program
and data are included in the external memory
space, the Data Memory Select (rn) function may
be programmed into the Port 3 MOde register.
When this is done, the m signal is available on
The Z8 provides for stack operations
through the use of a stack pointer, and the
stack may be located 1n the internal register
space or in the external data memory space. The
"stack select1on" bit (D2) in the Port 0-1 Mode
control register selects an internal or external
stack. When the stack is located internally,
register 255 contains an 8-bit stack pointer and
register 254 is available as a general purpose
register. If an external stack is used, register
255 or registers 254 and 255 may be used as tne
stack pointer depending on the anticipated
"depth" of the stack. When registers 254 and
255 are both used, the stack pointer is a full
16-bits wide. The CALL, lRET, RET, PUSH, and
171
pop instructions are Z8 instructions which include implicit stack operations.
I/O S1RUcruRE
Parallel I/O
The Z8 microcomputer has 32 lines of I/O
arranged as four 8-bit ports. All of the I/O
ports are TTL compatible and are configurab1e as
input, output, input/output, or address/data.
The handshake control lines for Ports 0, 1, and
2 are bits from Port 3 that have been'programmed
through a MOde control register, except for ~,
~, and R/Wwhich are available as separate Z8
pins. The I/O ports are accessed as separate
internal registers by the Z8. Ports 0 and I
share one Mode control register, and Ports 2
and 3 each have a Mode control register for
configuring the port.
Port 0 can be programmed to be an I/O port
or as an ~dress output port. MOre specifically
Port 0 can be configured to be an 8-bit, I/O port,
or a 4-bit address output port (A8-AlI) for
external memory and one 4"bit I/O port, or an
8-bit address output port (A8-Al5) for external
memory.
Port I can be progra/l1lled as an I/O port
(with or without handshake), or an address/data
port (ADI'-AD7) for interfacing with external
memory. If Port I is programmed to be an address/data port, it cannot be accessed as a register.
Port 2 can be configured as individual
input or output bits, and Port 3 can be programmed to be parallel I/O bits, and/or serial I/O
bits, and/or handshake control lines for the
other ports. Figure 5 shows the port Mode
registers.
The off chip expansion capability USing
Ports 0 and 1 offers the added feature of being
Z-Bus compatible. All Z-Bus compatible peripheral chips that are available now, and will be
available in the future, will interface directly;
Wl.th the Z8 multiplexed address/data bus.
Serial I/O
As memtioned in the last section, Port 3
can be programmed to be a serial I/O port with
bits 0 and 7, the serial input and serial out~ut line~ respectively. The serial I/O capabilIty proVldes for full duplex asynchronous serial
data at rates up to 62.5K bits per second. The
transmitted format is one start bit, eight data
bits including odd parity lif parity is enabled), and two stop bits. '!he received data
format is one start bit, eight data bits and at
least one stop bit. If parity is enabled, the
eighth data bit received (bit 7) is replaced by
172
a parity error flag which indicates a parity
error if it is set to a ONE.
Timer/Count~r TO is the baud rate generator
and runs' at lb times the serial data bit rate
The receiver is double duffered and an inte~l
interrupt (IRQ3) is generated when a character
is loaded into the receive buffer register. A
different internal interrupt (IRQ4) is generated
when a character is transmitted.
COUNI'ER/TIMERS
The Z8 has two 8-bit programmable counter/
timers, each of which is driven by a programmable 6-bit prescaler. The T1 pres caler can be
driven by internal or externa clock sources,
and the TO pres caler is driven by the internal
clock only. The two pre scalers and the two
counters ar~ loaded through four control registers (see FIgure 4) and when a counter/timer
reaches the "end of count" a timer, interrupt is
generated (IRQ4 for TO' and IRQ5 for T). The
counter/timers can be programmed to stAp upon
reaching the end of count, or to reload and
continue counting. Since either counter (one at
a time) can have its output available external
to the Z8, and Counter/Timer T 1 can have an
external input, the two counters can be cascaded.
Port 3 can be programmed to provide timer
outputs for external time base generation or
trigger pulses.
INTERRUPT S1RUcruRE
The Z8 provides for six interrupts from
eight different sources including four Port 3
lines (P30-P33), serial in, serial out, and two
counter/timers. These interrupts can be masked
and prioritized using the Interrupt Mask Register (register 251) and the Interrupt Priority
Register (register 249). All interrupts can be
disabled with the master interrupt enable bit
in the Interrupt Mask Hegister.
Each of the six interrupts has a l6-bit
interrupt vector that points to its interrupt
service routine. These six 2-byte vectors are
placed in the first twelve locations in the program memory space (see Figure 2).
When simultaneous interrupts oc= for
enabled interrupt sources, the Interrupt Priore
ity RegIster determines which interrupt is serviced first. The priority is programmable in a
way that is described by Figure 6.
When an interrupt is recognized by the Z8,
all other interrupts are disabled, the program
counter and program control flags are saved, and
the program counter is loaded with the corresponding interrupt vector. Interrupts must be
re-enabled by the user upon enterIng the service
Ii Programmer's Guide 10
the ISTM Microcomputer
~
Application.
Note
Zilog
Doll Freund
October 1980
SECTION
]I.
Introduction
The Z8 is the first microcomputer to offer
both a highly integrated microcomputer on a
single chip and a fully expandable microprocessor for I/O-and memory-intensive applications. The Z8 has two timer/counters, a UART,
2K bytes internal ROM, and a 144-byte internal register file including 124.bytes of RAM,
32 bits of I/O, and 16 control and status registers. In addition, the Z8 can address up to
124K bytes of external program and data
me~ory, which can provide full, memorymapped I/O capability.
This application note describes the important
features of the Z8, with software examples that
illustrate its power and ease of use. It is
divided into sections by topic; the reader need
not read each section sequentially, but may
skip around ti:> the sections of current interest.
It is assumed that the reader is familiar with
the Z8 and its assembly language, as
described in the following documents:
IiiI Z8 Technical Manual (03-3047-02)
Accessing Register Memory
The Z8 register space consists of four I/O
ports, 16 control and status registers, and 124
general-purpose registers. The generalpurpose registers are RAM areas typically used
for accumulators, pointers, and stack area.
This section describes these registers and how
they are used. Bit manipul~tion and stack
operations affecting. the register space are
discussed in Sections 4 and 5, respectively.
2.1 Registers and Register Pairs. The Z8 supports 8-bit registers and 16-bit register pairs.
A register pair consists of an even-numbered
register concatenated with the next higher
numbered register (%00 and %01, %02 and
%03, ... %7E and %7F, %FO and %Fl, ...
%FE and %FF). A register pair must be
addressed by reference to the even-numbered
register. For example,
%Fl and %F2 is ;"ot a valid register pair;
, %FO and %Fl is a valid register pair,
addressed by reference to %FO.
Register pairs may be incremented (INCW)
and decremented (DECW) and are useful as
pOinters for accessing program and external
data memory. Section 3 discusses the use of
register pairs' for this purpose:
Any instruction which can reference or
modify an 8-bit register can do so to any of the
144 registers in the Z8, regardless of the
inherent nature of that register. Thus, I/O
ports, control, status, and general-purpose
registers may all be accessed and manipulated
without the need for special-purpose instruc- '
tions. Similarly, instructions which reference
or modify a 16-bit register pair can do so to
any of the valid 72 register pairs. The only
exceptions to this rule are:
t:J
Z8 PLZlASM Assembly Language Programming Manual (03-3023-02)
III
The DJNZ (decrement and jump if non-zero)
instruction may successfully operate on the
general-purpose RAM registers (%04-%7F)
only.
III
Six control registers are write-only registers
and therefore, may be modified only by
such instructions as LOAD, POP, and
CLEAR. Instructions such as OR and AND
require that the current contents of the
operand be readable and therefore will not
function properly on the write-only
registers. These registers are the following:
the timer/counter pres caler registers PREO
and PRE1, the port mode registers P01M,
P2M, and P3M, the interrupt priority
register IPR.
173
2. Accessing 2.2 Register Pointer. Within the register
Register
addressing modes provided by the Z8, a regisMemory
ter may be specified by its full8-bit address
(Continued) . (O-%7F, %FO-%FF) or by a short 4-bit
address. In the latter case, the register is
viewed as one of 16 working registers within a working register group. Such a group
must be aligned on a 16-byte boundary and is
addressed by Register Pointer RP (%FD). As
an example, assume the Register Pointer contains %70, thus pointing to the working register group from %70to %7F. The LD instruction may be used to initialize register %76 to
an immediate value in one of two ways:
LD %76,#1 !8-bit register 'address is given
by instruction (3 byte instruction)!
or
LD R6,#1
!4-bit working register address
is given by instruction; 4-bit
working register group
address is given by Register
Pointer (2 byte instruction)!
The address calculation for the latter case
is illustrated in Figure 1. Notice that 4-bit
working-register addressing offers code compactness and fast execution compared to its
8-bit counterpart.
To modify the contents of the Register
POinter, the Z8 provides the instruction
SRP #value
Execution of this instruction will load the
upper four bits of the Register Pointer; the
lower four bits are. always set to zero. Although
a load instruction such as
LD RP,#value
could be used to perform the same function,
SRP provides execution speed (six vs. ten'
cycles) and code space (two vs. three bytes)
advantages over the LD instruction. The
instruction
SRP #%70
is used to set the Register Pointer for the above
example.
Figure 1. Address Calculation Using the Register Pointer
2.3 Context Switching. A typical function
performed during an interrupt service routine
is context switching. Context switching refers
to the saving and subsequent restoring of the
program counter, status, and registers of the
interrupted task. During an interrupt machine
cycle, the Z8 automatically saves the Program
Counter. and status flags on the stack. It is the
responsibility of the interrupt service routine to
preserve the register space. The recommended
means to this end is to allocate a specific portion of the register file for 'use by the service
routine. The service routine thus preserves the
register space of the interrupted task by avoiding modification of registers not allocated as its
own. The most efficient scheme with which to
implement this function in the Z8 is to allocate
a working register group (or portion thereof) to
the interrupt service routine. In this way, the
preservation of the interrupted task's registers
Is solely a matter of saving the Register Pointer
on entry to the service routine, setting the
Register Pointer to its own working register
group, and restoring thE! Register Pointer prior
to exiting the service routine. For example,
174
assume such a register allocation scheme has
been implemented in which the interrupt ser"
vice routine for IRQO may access only working
register Group 4 (registers %40-%4F). The
service routine for IRQO should be headed by
the code sequence:
PUSH RP
(preserve Register Pointer of
interrupted task!
SRP #%40 !address working register
group4(
Before exiting, the service routine should
execute the instruction
POP RP
to restore the Register Pointer to its entry
value.
It should be noted that the technique
described above need not be restricted to
interrupt service routines. Such a technique
might prove efficient for use by a subroutine
requiring intermediate registers to produce its
outputs: In this way, the calling task can
assume that its environment is intact upon
return from the subroutine.
2. Accessing
Register
Memory
(Continued)
2.4 Addressing Mode. The Z8 provides three
addressing modes for accessing the register
space: Direct Register, Indirect Register, and
Indexed.
2.4.1 Direct Register Addressing. This
addressing mode is used when the target register address is known at assembly time. Both
long (8-bit) register addressing and short
(4-bit) working register addressing are supported in this mode. Most instructions supporting this mode provide access to single
8-bit registers. For example:
LD
%FE,#HI STACK
!Ioad register %FE (SPH) with
the upper 8-bits of the label
STACK!
AND O,MASKJEG
!AND register 0 with register
named MASKJEG!
OR I,R5 !OR register I with working
register 5!
Increment word (INCW) and decrement
word (DECW) are the only two Z8 instructions
which access 16,bit operands. These instructions are illustrated below for the direct register addressing mode.
INCW RRO !increment working register
pair RO, RI:
RI"- RI +
RO ..- RO + carry!
DECW %7E
!decrement working register
pair %7E, %7F:
%7F <3- %7F
%7E <3- %7E - carry!
Note that the instruction
INCW RR5
will be flagged as an error by the assembler
(RR5 not even-numbered).
2.4.2 Indirect Register Addressing. In this
addressing mode, the operand is pointed to by
the register whose 8-bit register address or
4-bit working register address is given by the
instruction. This mode is used when the target
register address is not known at assembly time
and must be calculated during program execution. For example, assume registers %60-%7F
contain a buffer for output to the serial line via
repetitive calls to procedure SERIAL_OUT.
SERIAL_OUT expects working register 0 to
hold the output character. The following
instructions illustrate the use of the indirect
addressing mode to accomplish this task:
LD
RI,#%20
!working register 1 is the byte
counter: output %20 bytes!
LD
R2,#%60
!working register 2 is the buffer pointer register!
out_again:
LD
RO,@R2
!load into working register 0
the byte pointed to by working
register 2!
INC R2
!increment pOinter!
CALL SERIAL_OUT
!output the byte!
DJNZ Rl,out _again
!loop till done!
Indirect addressing may also be used for
accessing a 16-bit register pair via the INCW
and DECW instructions. For example,
INCW @RO !increment the register pair
whose address is contained in
working register O!
DECW @%7F
!decrement the register pair
whose address is contained in
register %7F!
The contents of registers RO and %7F should
be even numbers for proper access; when
referencing a register pair, the least significant
address bit is forced to the appropriate value
by the Z8. However, the register used to pOint
to the register pair need not be an evennumbered register.
Since the indirect addressing mode permits
calculation of a target address prior to the
desired register access, this mode may be used
to simulate other, more complex addressing
modes. For example, the instruction
SUB 4,BASE(R5)
requires the indexed addressing mode which is
not directly supported by the Z8 SUBtract
instruction. This instruction can be simulated
as follows:
LD
R6,#BASE
!working register 6 has the
base address!
ADD R6,R5 !calculate the target address!
SUB 4,@R6 !now use indirect addressing to
perform the actual subtract!
Any available register or working register
may be used in place of R6 in the
above example.
2.4.3 Indexed Addressing. The indexed
addressing mode is supported by the load
instruction (LD) for the transference of bytes
between a working register and another register. The effective address of the latter register
is given by the instruction which is offset by
the contents of a designated working (index)
175
2. Accessing
Register
Memory
(Continued)
register. This addressing mode provides
efficient memory usage when addressing
consecutive bytes in a block of register
memory, such as a table or a buffer. The
working register used as the index in
the effective address calculation. can
serve the additional role of counter for
control of a ioop's duration.
For example, assume an ASCII character
buffer exists in register memory starting at
address BUF for LENGTH bytes. In order
to determine the logical length of the character string, the buffer should be scanned
backward until the first nonoccurrence of a
blank character. The followin'g code
sequence may be used to accomplish
this task:
LD
RO,#LENGTH
!length of buffer!
!slarting at buffer end, look for
1st non-blank!
loop:
LD
RI,BUF -I(RO)
Rl,#, '
ne,found
!found non-blank!
DJNZ RO,loop
. !look at next!
all_blanks:
!length = O!
found:
5 instructions
12 bytes
1.5 /lS over head
10.5 /lS (average) per character tested
CP
JR.
At labels "all_blanks" and "found," RO
contains the length of the character
string. These labels may refer to the same
location, but they are shown separately for
an application where special processing is
required for a string of zero length. To perform this task without indexed addressing would require a code sequence
such as:
SECTION
3
176
Accessing Program and External Data
Memory
In a single instruction, the Z8 can transfer a
byte between register memory and either program or external data memory. Load Constant
(LDC) and Load Constant and Increment
(LDCI) reference program memory; Load
External (LDE) and Load External and Increment (LDEI) reference external data memory.
These instructions require that a working
register pair contain the address of the byte in
either program or external d<;lta memory to be
accessed by the instruction (indirect working
register pair addressing mode). The register
byte operand is specified by using the direct
working register addressing mode in LDC and
LD
LD
R!,#BUF + LENGTH - I
RO,#LENGTH
!starting at buffer end, look for
1st non-blank!
loop 1:
@Rl,#' ,
ne,foundl
!found non-blank!
DEC Rl
!dec pOinter!
DJNZ RO,loopl
!are we done?!
all_blanksl: !Iength = O!
foundl:
6 instructions
13 bytes
3 /lS over head
9.5 /lS (average) per character tested
CP
JR
The latter method requires one more byte of
program memory than the former, but is faster
by four execution cycles (1 /ls) per character
tested.
As an alternate example, assume a buffer
exists as described above, but it is desired to
scan this buffer forward for the first occurrence of an ASCII carriage return. The following illustrates the code to do this:
LD
RO,#-LENGTH
!starting at buffer start, look for
1st carriage return (= %OD)!
next:
LD
r 1,BUF + LENGTH(RO)
Rl,#%OD
eq,cr !found it!
!update counterlindex!
INC RO
nZ,next
JR
!tryagain!
CP
JR
cr:
ADD RO,#LENGTH
!RO has length to CR!
7 instructions
16 bytes
1.5 /lS overhead
12 /lS (average) per character tested
LDE or the indirect working register addressing mode in LDCI and LDEI. In addition to
performing the designated byte transfer, LDCI
and LDEI automatically increment both the
indirect registers specified by the instruction.
These instructions are therefore efficient for
performing block moves between register and
either program or external data memory. Since
the indirect addressing mode is used to specify
the operand address within program or external data memory, more complex addressing
modes may be simulated as discussed earlier
in Section 2.4.2. For example, the instruction
LDC
R3,BASE(R2)
requires the indexed addressing mode, where
3. Accessing
Program and
External Data
Memory
(Continued)
BASE is the base address of a table in program
memory and R2 contains the offset from table
start to the desired table entry. The following
code sequence simulates this instruction with
the use of two additional registers (RO and RI
in this example).
LD
LD
RO,HHI BASE
RI,HLO BASE
!RRO has table start address!
ADD RI,R2
ADC RO,HO
!RRO has table entry address!
LDC R3,@RRO
!R3 has the table entry!
3.1 Configuring the Z8 for 1/0 Applications
'vs. Memory Intensive Applications. The 28
offers a high degree of flexibility in memory
and I/O intensive applications. Thirty-two port
bits are provided of which 16, 12, eight, or
zero may be configured as address bits to
external memory. This .allows for addressing of
62K, 4K or 256 bytes of external memory,
which can be expanded to 124K, 8K, or 512
bytes if the Data Memory Select output (DM) is
used to distinguish between program and data
memory accesses. The.following instructions
illustrate the code sequence required to configure the 28 with 12 external addressing lines
and to enable the Data Memory Select output.
Z8ASM
LOC
2.0
OBJ CODE
P 0000 20
P 0003 2E
3B
QA
POIM,H'Vo(2)0001001O
!bit 3-4: enable ADo-AD7;
bit 0-1: enable As-All!
LD
P3M,H%(2)00001000
!bit 3-4: enable DM!
The two bytes following the mode selection of
ports 0 and I should not reference external
memory due to pipelining of instructions within
the 28. Note that the load instruction to P3M
satisfies this requirement (providing that it
resides within the internal 2K bytes of
memory).
3.2 LDC and LDE. To illustrate the use of the
Load Constant (LDC) and Load External (LDE)
instructions, assume there exists a hardware
configuration with external memory and Data
Memory Select enabled. The follOWing module
illustrates a program for tokenizing an ASCII
input buffer. The program assumes there is a
list of delimiters (space, comma, tab, etc.) in
program memory at address DE LIM for
COUNT bytes (accessed via LDC) and that an
ASCII input buffer exists in external data'
memory (accessed via LDE). The program
scans the input buffer from the current location
and returns the start address of the next token
(Le. the address of the first nondelimiter
found) and the length of that token (number of
characters from token start to next delimiter).
STMT SOURCE STATEMENT
2C
OD
1
2
3
4
5
6
~,
P 0006
P 0006 BO
E2
P
P
P
P
P
82
AO
D6
FD
8D
30
EO
002E'
0015'
0018'
P 0015 8D
0008'
0008
OOOA
OOOC
OOOF
0012
LD
SCAN
MODULE
CONSTANT
COUNT . _
6
GLOBAL
$SECTION PROGRAM
DELIM
ARRAY
[COUNT BYTE]
[,
r
,
';
I
r
'
I
, .' , %OA , %OD]
PROCEDURE
9 scan
10 !w*************u******************u********** •• ** ••• UH
11
Purpose
To find the next token within an
12
ASCII buffer.
13
14 Input
RRO = address of current location
15
within input buffer in external
16
memory.
17
18 Output
RR4 = address of start of next token
19
RRO
address of new token's ending
20
delimiter
21
R2
length of token
22
R3 = ending delimiter
23
R6,~7,R8,R9 destroyed
24
25 *****************************************************1
26 ENTRY
27
clr
R2
linit. length counterl
28
DO
LDE
R3,@RRO Iget byte from input bufferl
29
30
incw
RRO
lincrement, pointerl
31
call
check
!look fo~ non_delimiter I
IF C THEN
32
EXIT
Ifound token start!
33
34
FI'
OD
35
3. Accessing
Program and
External Data
Memory
(Continued)
P 0018 48
P 001A 58
El
P
P
P
P
P
2E
82
D6
7D
8D
30
002E'
0028'
002D'
P 0028 AO
P 002A 8D
EO
001C'
001C
001D
001F
0022
0025
EO
P 002D AF
P 002E
P 002E
P 002E 6C
P 0030 7C
00'*
00*
P 0032 8c
06
P 0034 C2
P 0036 AO
P 003lt A2
P 003A 6B
P 003C 8A
P 003E DF
96
E6
93
03
F6
P 003F AF
P 0040
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
ld
ld
DO
inc
LDE
call
IF NC
EXIT
FI
incw
R4,RO
R5, R1
!RR4
= token
starting addr!
R2
!inc. length counter!
R3,@RRO !get next input byte!
check
!look for delimiter!
THEN
!found token e~d!
RRO
!point to next byte!
OD
END
ret
scan
check
PROCEDURE
!*****************************************************
Purpose
=
compare current character with
delimiter table until table
end or match found
input
DELIM = start address of table
COUNT = length of that table
R3 = byte to be scrutinized
output
Carry flag = 1 => input byte
is not a delimiter (no match found)
Carry flag = 0 => input byte
is a delimiter (match found)
R6,R7,R8,R9 'destroyed
*****************************************************!
ENTRY
here:
ld
ld
R6,IIHI DELIM
R7,IILO DELIM
ld
R8,IICOUNT
LDC
incw
cp
jr
djnz
scf
R9,@RR6
RR6
R9,R3
eq,bye
R8,here
bye:
END
END
!RR6 points to
delimiter 1 ist!
!R8 = length of list!
!get table entry!
!point to next entry!
!R3 = delimiter?!
ryes. carry = O!
!next entry!
!table done. R3
nO,t a delimiter!
ret
check
SCAN
o ERRORS
ASSEMBLY COMPLETE
27 instructions
58 bytes
Execution time is a function of the number of leading delimiters
before token start (x) and the number of characters in the
taken (y); 123 p:; overhead + 59x p:; + l02y p:;'
(average) per token
3.3 LOCI. A common function performed in 28
applications is the initialization of the register
space. The most obvious approach to this function is the coding of a sequence of "load
register with immediate value" instructions
(each occupying three program bytes for a
178
register or two program bytes for a working
register). This approach is also the most efficient technique for initializing less than eight
consecutive registers or 14 consecutive working registers. For a larger register block, the
3. Accessing
Program and
External Data
Memory
(Continued)
LDCI instruction provides an economical
means of initializing consecutive registers from
an initialization table in program memory. The
folloWing code excerpt ilhistrates -this technique of initialiZing control registers %F2
through %FF from a l4-byte array (INIT_tab)
in program memory:
SRP
LD
LD
LD
LD
#%00
!RP not %FO!
R6,#HI INIT_tab
R7,#LO INIT_tab
R8,#%F2
! 1st reg to be initialized!
R9,#14
!length of register block!
loop:
LDCI @R8,@RR6
!load a register from the
init table!
DJNZ R9,100p
!continue till done!
7 instructions
14 bytes
7.5 /.Is overhead
7.5 /.Is per register initialized
SECTiON
Bit Manipulations
<4
Support of the test and modification of an
individual bit or group of bits is required by
most software applications suited to the Z8
microcomputer. InitialiZing and modifying the
Z8 control registers, polling interrupt requests,
manipulating port bits for control of or communication with attached devices, and manipulation of software flags for internal control purposes are all examples of the heavy use of bit
manipulation functions. These examples illustrate the need for such functions in all areas of
the Z8 register space. These functions are supported in the 28 primarily by six instructions:
I!l
Test under Mask (TM)
15
Test Complement under Mask (TCM)
I!II AND
IiII
OR
m XOR
III Complement (COM)
These instructions may access any 28 register,
regardless of its inherent type (control, 1/0, or
general purpose), with the exception of the six
write-only control registers (PREO, PREI,
POIM, P2M, P3M, IPR) mentioned earlier in
Section 2.1. Table I summarizes the function
performed on the destination byte by each of
the above instructions. All of these instructions, with the exception of COM, require a
mask operand. The "selected" bits referenced
in Table I are those bits in the destination
operand for which the corresponding mask bit
is a logic I.
3.4 LDEI. The LDEI instruction is useful for
moving blocks of data between external and
register memory since auto-increment is performed on both indirect registers designated
by the instruction. The following code excerpt
illustrates a register buffer being saved at
address %40 through %60 into external
memory at address SAVE:
LD
LD
LD
LD
RlO,#HI SAVE
!external memory!
Rll,#LO SAVE
!address!
R8,#%40
lstarting register!
R9,#%21
!number of registers to save in
'external data memory!
loop:
LDEI @RRlO,@R8
linit a register!
DJNZ R9,100p
!until done!
6 instructions
12 bytes
6 /.Is overhead
7.5 /.Is per register saved
Opcode
TM
Use
To test selected bits for logic 0
TCM
To test seh,cted bits for logic I
AND
To reset all but select"J bits to logic 0
OR
To set s.·lected bits to logic I
XOR
To complem.mt selected bits
COM
To complement all bits
Table I. Bit Manipulation Instruction Usage
The instructions AND, OR, XOR, and COM
have functions common to today's microprocessors and therefore are not described in
depth here. However, examples of the use of
these instructions are laced throughout the
remainder of this document, thus giving an
integrated view of their uses in common functions. Since they are unique to the 28, the
functions of Test under Mask and Test Complement under Mask, are discussed in more detail
next.
4.1 Test under Mask (TM). The Test under
Mask instruction is used to test selected bits for
logic O. The logical operation performed is
destination AND source
Neither source nor destination operand is
modified; the FLAGS control register is the
only register affected by this instruction. The
zero flag (2) is set if all selected bits are logic
0; it is reset otherwise. Thus, if the selected
destination bits are either all logic I or a combination of Is and Os, the zero flag would be
cleared by this instruction. The sign flag (S) is
either set or reset to reflect the result of the
179
4. Bit
Manipulations
(Continued)
AND operation; the overflow flag (V) is always
reset. All other flags are unaffected. Table 2
illustrates the flag settings which result from
the TM instruction on a variety of source and
destination operand combinations. Note that a
given TM instruction will never result in both
the Z and S flags being set.
4.2 Test Complement under Mask. The Test
Complement under Mask instruction is used to
test selected bits for logic 1. The logical operation performed is
(NOT destination) AND source.
Destination
SECTION
5
Source
Flags
Destination
Source
Flags
(binary)
(binary)
Z
S
V
(binary)
(binary)
Z
S
10001100
01110000
I
0
0
10001100
01110000
0
0
0
01111100
01110000
0
0
0
011ll1O0
01110000
I
0
0
0
10001100
11110000
0
I
0
11111100
11110000
V
10001100
11110000
0
11111100
11110000
0
00011000
10100001
0
0
00011000
10100001
0
0
01000000
10100001
0
0
01000000
10100001
0
0
0
0
0
0
Table 2. Effects of the TM Instruction
Table 3. Effects of the TeM Instruction
Stack Operations
The Z8 stack resides within an area of data
memory (internal or external). The current
address in the stack is contained in the stack
pointer, which decrements as bytes are pushed
onto the stack, and increments as bytes are
popped from it. The stack pointer occupies two
control register bytes (%FE and %FF) in the
Z8 register space and may be manipulated like
any other register. The stack is useful for
subroutine calls, interrupt service routines,
and parameter passing and saving. Figure 2
illustrates the downward growth of a stack as
bytes are pushed onto it.
latter configuration, SPH is available for use as
a data register. The following illustrates a code
sequence that initializes external stack operations:
5.1 Internal vs. External Stack. The location
of the stack in data memory may be selected to
be either internal register memory or external
data memory. Bit 2 of control register POIM
(%FS) controls this selection. Register pair
SPH (%FE), SPL (%FF) serves as the stack
pointer for an external stack. Register SPL is
the stack pointer for an internal stack; In the
sp_
x-1
x-2
x-3
SP-
x-4
INITIAL
STATE
FOLLOWING
PUSH R1
LD POIM,#%(2)OOOOOOOO
!bit 2: select external stack!
LD SPH,#HI STACK
LD SPL,#LO STACK
5.2 CALL. A subroutine call causes the current Program Counter (the address of the byte
following the CALL instruction) to be pushed
onto the stack. The Program Counter is loaded
with the address specified by the CALL
instruction. This address may be a direct
address or an indirect register pair reference.
For example,
LABEL 1: CALL %4F98
!direct addressing: PC is
loaded with the hex value
4F98;
address LABEL 1 + 3 is pushed
onto the stack!
LABEL 2: CALL @RR4
!indirect addressing: PC is
loaded with the contents of
working register pair R4, R5;
address LABEL 2 + 2 is pushed
onto the stack!
x sp_
FOLLOWING
CALL
Figure 2. Growth of a Stack
180
As in Test under Mask, the FLAGS control
register is the only register affected by this
operation. The zero flag (Z) is set if all selected
destination bits are 1; it is reset otherwise. The
sign flag (S) is set or reset to reflect the result
of the AND operation; the overflow flag (V) is
always reset. Table 3 illustrates the flag settings which result from the TCM instruction on
a variety of source and destination operand
combinations. As with the TM instruction, a
given TCM instruction will never result in both
the Z and S flags being set.
5. Stack
Operations
(Continued)
LABEL 3: CALL @%7E
!indirect addressing: PC is
loaded with the contents of
registerpair %7E, %7F;
address LABEL 3 + 2 is pushed
onto the stack!
5.3 RET. The return (RET) instruction causes
the top two bytes to be popped from the stack
and loaded into the Program Counter. Typically, this is the last instruction of a subroutine
and thus restores the PC to the address following the CALL to that subroutine.
5.4 Interrupt Machine Cycle. During an interrupt machine cycle, the PC followed by the
status flags is pushed onto the stack. (A more
detailed discussion of interrupt processing is
provided in Section 6.)
5.5IRET. The interrupt return (IRET) instruction causes the top byte to be popped from the
stack and loaded into the status flag register,
FLAGS (%FC); the next two bytes are then
popped and loaded into the Program Counter.
In this way, status is restored and program
execution continues where it had left off when
the interrupt was recognized.
5.6 PUSH and POP. The PUSH and POP
instructions allow the transfer of bytes between
Interrupts
The 28 recognizes six different interrupts'
from four internal and four external sources,
including internal timer/counters, serial I/O,
and four Port 3 lines. Interrupts may be individually or globally enabled/disabled via Interrupt Mask Register IMR (%FB) and may be
prioritized for simultaneous interrupt resolution
via Interrupt Priority Register IPR (%F9).
When enabled, interrupt request processing
automatically vectors to the designated service
routine. When disabled, an interrupt request
may be polled to determine when processing is
needed.
6.1 Interrupt Initialization. Before the 28 can
recognize interrupts following RESET, some
initialization tasks must be performed. The initialization routine should configure the 28
interrupt requests to be enabled/disabled, as
'required by the target application and
assigned a priority (via IPR) for simultaneous
enabled-interrupt resolution. An interrupt
request is enabled if the corresponding bit in
the IMR is set (= I) and interrupts are
globally enabled (bit 7 of IMR = I). An interrupt request is disabled if the corresponding
bit in the IMR is reset (= 0) or interrupts are
globally disabled (bit 7 of IMR = 0).
A RESET of the 28 causes the contents of the
Interrupt Request Register IRQ (%FA) to be
held to zero until the execution of an EI
the stack and register memory, thus providing
program access to the stack for saving and
restoring needed values and passing
parameters to subroutines.
Execution of a PUSH instruction causes the
stack pointer to be decremented by 1; the
operand byte is then loaded into the location
pOinted to by the decremented stack pOinter.
Execution of a POP instruction causes the byte
addressed by the stack pointer to be loaded
into the operand byte; the stack pointer is then
incremented by 1. In both cases, the operand
byte is designated by either a direct register
address or an indirect register reference. For
example:
PUSH RI
!direct address: push working
register 1 onto the stack!
POP
5
!direct address: pop the top
stack byte into register 5!
PUSH @R4 !indirect address: pop the top
stack byte into the byte
pointed to by working register 4!
PUSH @17 !indirect address: push onto
the stack the byte pointed to
by register 17!
instruction. Interrupts that occur while the 28
is in this initial state will not be recognized,
since the corresponding IRQ bit cannot be set.
The EI instruction is specially decoded by the
28 to enable the IRQ; simply setting bit 7 of
IMR is therefore not sufficient to enable interrupt processing following RESET. However,
subsequent to this initial EI instruction, interrupts may be globally enabled .either by the
instruction
EI
!enable interrupts!
or by a register manipulation instruction
such as
OR
IMR,#%80
To globally disable interrupts, execute the
instruction
or
!disable interrupts!
This will cause bit 7 of IMR to be reset.
Interrupts must be globally disabled prior to
any modification of the IMR, IPR or enabled
bits of the IRQ (those corresponding to
enabled interrupt requests), unless it can be
guaranteed that an enabled interrupt will not
occur during the processing of such instruc c
lions. Since interrupts represent the occurrence of events asynchronous to program execution, it is highly unlikely that such a
guarantee can be made reliably.
181
6. Interrupts
(Continued)
6.2 Vectored Interrupt Processing. Enabled
interrupt requests are processed in an
automatic vectored mode in which the interrupt service routine address is retrieved from'
within the first 12 bytes of program memory.
When an enabled interrupt request is
recognized by the Z8, the Program Counter is
pushed onto the stack (low order 8 bits first,
then high-order 8 bits) followed by the FLAGS
register (#%FC). The corresponding interrupt
request bit is reset in IRQ, interrupts are
globally disabled (bit 7 of IMR is reset), and
an indirect jump is taken .on the word in location 2x, 2x + 1 (x = interrupt request number,
0~x~5). For example, if the bytes at
addresses %0004 and %0005 contain %05 and
%78 respectively, the interrupt machine cycle
for IRQ2 will cause program execution to continue at address %0578.
When interrupts a're sampled, more than one
interrupt may be pending. The Interrupt Priority Register OPR) controls the selection of the
pending interrupt with highest priority. While
this interrupt is being serviced, a higherpriority interrupt may occur. Such interrupts
may be allowed service within the current
interrupt service routine (nested) or may be
held until the current service routine is complete (non-nested).
To allow nested interrupt processing, interrupts must be selectively enabled upon entry
to an interrupt service routine. Typically, only
higher-priority interrupts would be allowed to
nest within the current interrupt service. To do
this, an interrupt routine must "know" which
interrupts have a higher priority than the current interrupt request. Selection of such nesting priorities is usually a reflection of the
priorities established in the Interrupt Priority
Register (IPR). Given this data, the first
instructions executed in the service routine
should be to save the current Interrupt Mask
Register, mask off all interrupts of lower and
equal priority, and globally enable interrupts
(EI). For example, assume that service of interrupt requests 4 and 5 are nested within the service of interrupt request 3. The follOWing illustrates the code required to enable IRQ4
.
and IRQ5:
CONSTANT
INT_MASL3
%(2) 00110000
GLOBAL
IRQ3_service
PROCEDURE
ENTRY
!service routine for IRQ3!
!save Interrupt Mask Register!
PUSH IMR
!interrupts were globally disabled during the interrupt
machine cycle - no DI is needed prior to modification of IMR!
AND IMR,#INL_MASK_3
!disable all but IRQ4 & 5!
EI
!. .. !
!service interrupt!
!interrupts are globally enabled now - must disable them prior to
modification of IMR!
DI
182
POP IMR
IRET
END IRQ3_service
!restore entry IMR!
Note that IRQ4 and IRQ5 are enabled by the
above sequence only if their respective IMR
bits = 1 on entry to IRQ3_service.
The service routine for an interrupt whose
processing is to be completed without interruption should not allow interrupts to be nested
within it. Therefore, it need not modify the
IMR, since interrupts are disabled automatically during the interrupt machine cycle.
The service routine for an enabled interrupt
is typically concluded with an IRET instruction, which restores the FLAGS register and
Program Counter from the top of the stack and
globally enables interrupts. To return from an
interrupt service routine without re-enabling
interrupts, the following code sequence could
be used:
POP FLAGS
!FLAGS"'- @SP!
RET
!PC ...- @SP!
This accomplishes all the functions of IRET,
except that IMR is not affeded.
6.3 Polled Interrupt Processing Disabled
interrupt requests may be processed in a
polled mode, in which the corresponding bits
of the Interrupt Request Register (IRQ) are
examined by the software. When an interrupt
request bit is found to be a logiC 1. the interrupt should be processed by the appropriate
6. Interrupts
(Continued)
service routine. During such processing, the
interrupt request bit in the IRQ must be
cleared by the software in order for subsequent
interrupts on that line to be distinguished from
the current one. If more than one interrupt
request is to be processed in a polled mode,
polling should occur in the order of estab-
Iished priorities. For example, assume that
IRQO, IRQl, and IRQ4 are to be polled and
that established priorities are, from high to
low, IRQ4, IRQO, IRQl. An instruction
sequence like the following should be used to
poll and service the interrupts:
1. .. I
Ipoll interrupt inputs here I
TCM
IRQ, #%(2)00010000
JR
N2, TESTO
CALL
IRQ4_service
TESTO:
TCM
IRQ, #%(2)00000001
JR
N2, TESTI
CALL
IRQO-J;ervice
TESTl:
TCM
IRQ, #%(2)00000010
JR
N2, DONE
CALL
IRQ I_service
DONE:
1. .. 1
IRQ4_service
1. .. I
AND
1. .. I
RET
END IRQ4_service
SECTION
7
PROCEDURE
IIRQ4 need service?I
Inol
Iyesl
IIRQO need service?I
Inal
Iyesl
IIRQl need service?I
Inal
Iyesl
ENTRY
Iclear IRQ4I
IRQ, #%(2)11101111
IRQO_service
1. .. I
AND
1. .. I
RET
END IRQO_service
PROCEDURE
IRQ I_service
1. .. I
AND
1. .. I
RET
END IRQ I_service
1. .. I
PROCEDURE
ENTRY
Iclear IRQOI
IRQ, #%(2)1111111O
IRQ, #%(2)11111101
Timer/Counter Functions
The 28 provides two 8-bit timer/counters, To
and T1, which are adaptable to a variety of
application needs and thus allow the software
(and external hardware) to be relieved of the
bulk of such tasks. Included in the set of such
uses are:
III
Interval delay timer
iii
Maintenance of a time-of-day clock
m! Watch-dog timer
I!iI
External event counting
III
Variable pulse train output
III
Duration measurement of external event
III
Automatic delay following external event
detection
ENTRY
Iclear IRQI!
Each timer/counter is driven by its. own 6-bit
prescaler, which is in turn driven by the internal 28 clock divided by four. For T1, the internal clock may be gated or triggered by an
external event or may be replaced by an external clock input. Each timer/counter may
operate in either single-pass or continuous
mode where, at end-of-count, either counting
stops or the counter reloads and continues
counting. The counter and prescaler registers
may be altered individually while the timer/
counter is running; the software controls
whether the -new values are loaded immediately or when end-of-count-(EOC) is reached.
Although the timer/counter prescaler
registers (PREO and PREl) are write~only,
there is a technique by which the timer/
183
7. Timer/
Counter
Functions
(Continued)
counters may simulate a readable prescaler.
This capability is a requirement for high
resolution measurement of an event's duration.
The basic approach requires that one timer/
counter be initialized with the desired counter
and prescaler values. The second timer/
counter is initialized with a counter equal to
. the pres caler of the first timer/counter and a
prescalerof I. The second timer/counter must
be programmed for continuous mode. With
both timer/counters driven by the internal
clock and started and stopped simultaneously,
they will run synchronous to one another; thus,
the value read from the second counter will
always be equivalent to the pres caler of
the first.
7.1 Time/Count Interval Calculation To
determine the time interval (i) until EOC, the
equation
i=txpxv
characterizes the relation between the
prescaler (p), counter (v), and clock input
period (t); t is given by
l/(XTAL/8)
where XTAL is the Z8 input clock frequency;
p is in the range 1 - 64; v is in the range
1 - 256. When programming the prescaler and
counter registers, the maximum load value is
truncated to six and eight bits, respectively,
and is therefore programmed as zero. For an
input clock frequency of 8 MHz, the prescaler
and counter register values may be programmed to time an interval in the range
1 p.s
X
1 xl::;; i ::;; 1 p.s
X
64
X
256
1 p.s ::;; i ::;; 16.384 ms
To determine the count (c) until EOC for TI
with external clock input, the equation
c = p X v
characterizes the ,relation between the T I
prescaler (p) and the TI counter (v). The
divide-by-8 on the input frequency is bypassed
in this mode. The count range is
x 1::;; c::;; 64 x 256
1 ::;; c ::;; 16,384
7.2 TOUT Modes. Port 3, bit 6 (P36) may be
configured as an output (TOUT) which is
dynamically controlled by one of the following:
.. To
.. TI
.. Internal clock
When driven by To or TI, TOUT is reset to a
logic 1 when the corresonding load bit is set in
timer control register TMR (%Fl) and toggles
on EOC from the corresponding counter.
184
When TOUT is driven by the internal clock,
that clock is directly output on P36.
While programmed as TouT. P36 is disabled
from being modified by a write to port register
%03; however, its current output may be
examined by the Z8 software by a read to port
register %03.
7.3 TIN Modes. Port 3, bit 1 (P31) may be configured as an input (TIN) which is used in conjunction with TI in one of four modes:
.. External clock input
.. Gate input for internal clock
l1li
Nonretriggerrable input for internal clock
Ell Retriggerable input for internal clock
For the latter two modes, it should be noted
that the l;!xistence of a synchronizing circuit
within the Z8 causes a delay of two to three
internal clock periods folloWing an external
trigger before clocking of the counter actually
begins.
Each High-to-Low transition on TIN will
generate interrupt request IRQ2, regardless of
the selected TIN mode or the enabled/disabled
state of Tj. IRQ2 must therefore be masked or
enabled according to the needs of the
application.
The "external clock input" TIN mode supports the counting of external events, where an
event is seen as a High-to-Low transition on
TIN. Interrupt request IRQ5 is generated on
the nth occurrence (single-pass mode) or on
every nth occurrence (continuous mode) of
that event.
The "gate input for internal clock" TIN mode
provides for duration measurement of an external event. In this mode, the TI prescaler is
driven by the Z8 internal clock, gated by a
High level on TIN. In other words, TI will
count while TIN is High and stop counting
while TIN is Low. Interrupt request IRQ2 is
generated on the High-to-Low transition on
TIN. Interrupt request IRQ5 is generated on TI
EOC. This mode may be used when the width
of a High-going pulse needs to be measured.
In this mode, IRQ2 is typically the interrupt
request of most importance, since it signals the
end of the pulse being measured. If IRQ5 is
generated prior to IRQ2 in this mode, the
pulse width on TIN is too large for TI to
measure in a single pass .
The "nonretriggerable input" TIN mode provides for automatic delay timing following an
external event. In this mode, TI is loaded and
clocked by the Z8 internal clock follOWing the
first High -to-Low transi lion on TIN after T I is
enabled. TIN transiiions that occur after this
point do not affect TI. In single-pass mode, the
7. Timer/
Counter
Functions
(Continued)
enable bit is reset on EOC; further TIN transitions will not cause TI to load and begin counting until the software sets the enable bit again.
In continuous mode, EOC does not modify the
enable bit, but the counter is reloaded and
counting continues immediately; IHQS is
generated every EOC until software resets the
enable bit. This TIN mode may be used, for
example, to time the line feed delay following
end of line detection on a printer or to delay
data sampling for some length of time following a sample strobe.
The "retriggerable input"TIN mode will load
and clock T I with the 28 internal clock on
every occurrence of a High-to-Low transition
on TIN. TI will time-out and generate interrupt
request IRQS when the programmed time
interval (determined by TI pres caler and load
register values) has elapsed since the last
High-to-Low transition on TIN. In single-pass
mode, the enable bit is reset on EOC; further
TIN transitions will not cause TI to load and
begin counting until the software sets the
enable bit again. In continuous mode, EOC
does not modify the enable bit, but the counter
is reloaded and counting continues immediZ8ASM
LOC
2.0
OBJ CODE
P OOOC
F3
93
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TIMER1 MODULE
CONSTANT
R12
HOUR
MINUTE
R13
R14
SECOND
HUND
R15
$SECTION PROGRAM
GLOBAL
IIRQ5 interrupt vectorl
$ABS
10
IRQ_5
[1 WORD)
ARRAY
0_
0-
0_
0_
TOD_INIT
ENTRY
P 0003 E6
F2
00
46
8F
46
9F
AF
F1
DC
FB
20
0006
0009
OOOA
DODD
OOOE
OOOF
P OOOF
P OOOF 70
FD
0011
0013
0014
0017
0019
001B
001C
001F
EF
13
EF
64
EE
DB
3C
P
P
P
P
P
P
P
P
31
FE
A6
EB
BO
EE
A6
EB
10
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
LD
TOD
ENTRY
[TOD)
PROCEDURE
LD
END
.-
$REL
17
P
P
P
P
P
P
7.4 Examples. Several possible uses of the
timer/counters are given in the following four
examples.
7.4.1 Time of Day Clock. The following
module illustrates the use of TI for
maintenance of a time of day clock, which is
kept in binary format in terms of hours,
minutes, seconds, and hundredths of a second.
It is desired that the clock be updated once
every hundredth of a second; therefore, TI is
programmed in continuous mode to interrupt
100 times a second. Although TI is used for
.this example,To is equally suited for the task.
The procedure for initializing the timer
(TOD_INIT), the interrupt service routine
(TOD) which updates the clock, and the interrupt vector for TI end-of-count (IRQ_S) are
illustrated below. XTAL = 7.3728 MHz is
assumed.
STMT SOURCE STATEMENT
P 0000 OOOF'
P 0000 E6
ately; IRQS is generated at every EOC until
the software resets the enable bit. This TIN
mode may provide such functions as watch-dog
timer (e.g., interrupt if conveyor belt stopped
or clock pulse missed), or keyboard time-out
(e:g., interrupt if no input in x ms).
PRE1, 11%(2) 10010011
Ibit 2-7: prescaler = 36;
bit 1: internal clock;
bit 0: continuous model
1(256) time-out =
Tl ,110
1/100 secondl
TMR,II%OC !load, enable T11
OR
DI
IMR,II%20
OR
EI
RET
TOD_ INIT
lenable T1 interrupti
PROCEDURE
PUSH
RP
IWorking register file %10 to %1F contains
the time of day clock I
SRP
11%10
INC
HUND
! 1 more .01 secl
CP
HUND,11100
Ifull second yet?1
JR
NE, TOD_EXIT
I jump i f no I
CLR
HUND
INC
SECOND
! 1 more second I
CP
SECOND,1160
Ifull minute yet?1
NE,TOD_EXIT
Ijump if not
JR
185
'7. Timer/
Counter
Functions
(Continued)
P 0021
P 0023
P 0024
P 0027
P 0029
P 002B
BO
DE
A6
EB
BO
CE
P 002C 50
P 002E BF
P 002F
EE
ED
03
ED
3C
FD
42
CLR
43
INC
44
CP
45
JR
46
CLR
47
INC
48 TOD_EXIT :
POP
49
50
IRET
51 END
TOD
TIMERl
52 END
SECOND
MINUTE
MINUTE,1160
NE,TOD_EXIT
MINUTE
HOUR
11 more minute!
! full hour yet?!
! jump i f no!
RP
Irestore entry RPI
o ERRORS
ASSEMBLY COMPLETE
TOD_INIT:
7 instructions
15 bytes
16 ps
TOD:
17 instruction
32 bytes
19.5 ps (average) including interrupt response time
7.4.2 Variable Frequency, Variable Pulse
Width Output. The following module
illustrates one possible use of TOUT. Assume it
is necessary to generate a pulse train with a
10% duty cycle, where the output is repetitively high for 1.6 ms and then low for 14.4 ms. To
do this, TOUT is controlled by end-of-count
-from II, although To could alternately be
chosen. This ';'xample makes use of the 28
feature that allows a timer's counter register to
be modified without disturbing the count in
progress. In continuous mode, the new value is
loaded when TI reaches EOC. TI is first
loaded and enabled with values to generate
the short interval. The counter register is then
immediately modified with the value to
generate the long interval; this value is loaded
into the counter automatically on TI EOC. The
prescaler selected value must be the same for
both long and short intervals. Note that the
Z8ASM
LOC
2.0
OBJ CODE
STMT SOURCE .STATEMENT
P 0000 0017 '
P OOOC
P 0000 E6
F3
03
0003
0006
0009
OOOA
OOOD
E6
E6
8F
46
E6
F7
F2
00
19
FB
Fl
20
8C
paOlO E6
F2
El
P
P
P
P
P
186
initial loading of the T I counter register is
followed by setting the TIload bit of timer control register TMR (%Fl); this action causes
TOUT to be reset to a logic I output. Each
subsequent modification of the TI counter
register does not affect the current TOUT level,
since the TI load bit is NOT altered by the
software. The new value is loaded on EOC,
and TOUT will toggle at that time. The TI interrupt service routine should simply modify the
T I counter register with the new value, alternating between the long and short interval
values.
In the example which follows, bit 0 of
register %04 is used as a software flag to indicate which value was loaded last. This module
illustrates the procedure for T I/ToUT initialization (PULSE_INIT), the TI interrupt service
routine (PULSE), and the interrupt vector for
TI EOC (IRQ_5). XTAL = 8 MHz is assumed.
1 TIMER2 MODULE
$SECTION PROGRAM
2
3 GLOBAL
4 !IRQ5 interrupt vector!
$ABS
10
5
6
ARRAY
[1 WORD]
[PULSE]
7
8
$REL
PROCEDURE
9 PULSE_INIT
10 ENTRY
PRE1,H%(2)00000011
11'
LD
12
Ibit 2-7: prescaler = 64;
13
bit 1: internal clock;
14
bit 0: continuous model
LD
P3M,HOO
15
Ibit 5: let P36 be Toutl
16
LD
Tl ,1125
Ifor short intervall
DI
17
18
OR
IMR,f%(2)00100000 lenable Tl interrupti.
TMR,H%(2)10001100
LD
19
20
Ibit 6-7: Tout controlled
21
by T1;
22
bit 3: enable Tl;
23
bit 2: load Tl I
24 !Set long interval counter, to be loaded on Tl EOC!
LD
Tl, 11225
25
26 IClear alternating flag" for PULSE!
7. Timer/
Counter
Functions
(Continued)
P 0013 BO
04
P 0015 9F
P 0016 AF
P 0017
P 0017
P 0017
P 001A
P 001D
P'OOlF
E6
B6
6B
E6
f2
04
03
F2
E1
01
19
P 0022 BF
P 0023
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
CLR
END
PULSE
ENTRY
$04
!= 0
1
25 next;
225 next
EI
RET
PULSE_ INIT
PROCEDURE
LD
XOR
JR
LD
PULSE_ EXIT:
IRET
PULSE
END
TIMER2
END
Tl ,11225
%04,111
z, PULSE_EXIT
Tl ,1125
!new load valuel
!which value next?!
!should be 2251
! should be 251
o ERRORS
ASSEMBLY COMPLETE
PULSE_lNIT:
10 instructions
23 bytes
23 p.s
PULSE:
S instructions
12 bytes
25 p.s (average) including inrerrupt response time
7,4.3 Cascaded Timer/Counters, For some
applications it may be necessary to measure a
greater time interval than a single timer/
counter can measure (16,384 ms), In this case,
TIN and TOUT may be used to cascade To and
XTAl
TI to function as a single unit. TOUT. programmed to toggle on To end-of-count, should be
wired back to TIN, which is selected as the
external clock input for T I, With To programmed for continuous mode, TOUT (and therefore
TIN) goes through a High-to-Low transition
(causing TI to count) on every other To EOC,
Interrupt request IRQ5 is generated when the
programmed time interval has elapsed. Interrupt requests IRQ2 (generated on every TIN
High-to-Low transition) and IRQ4 (generated
on To EOC) are of no importance in this
application and are therefore disabled,
To determine the time interval (i) until EOC,
the equation
i=t xpO x va x (2 x pI x vI-I)
TO INTE~RUPT LOGIC (IRQ4)
characterizes the relation between the To
prescaler (pO) and counter (va). the TI
prescaler (pI) and counter (vI), and the 'clock
input period (t); t is defined in Section 7.1.
Assuming XTAL = 8 MHz, the measurable
time interval range is
I I'S X I x 1 x (2 x 1 - 1) :s i :s
I I's x 64
256 x (2 x 64 x 256 - 1)
x
1 I'S :s i :s 536,854528 s
TO INTERRUPT LOGIC (IRQ5)
Figure 3 illustrates the interconnection
between To and TI. The following module
illustrates the procedure required to initialize
the timers for a 1.998 second delay interval:
Figure 3. Cascaded Timer/Counters
187
7. Timer/
Counter
Functions
(Continued)
Z8ASM
LOC
2.0
OBJ CODE
STMT SOURCE STATEMENT
P 0000
P 0000 E6
F3
28
P 0003 E6
P 0006 E6
P 0009 E6
F7
F2
F5
00
64
29
P OOOC E6
P OOOF 8F
P 0010 56
F4
64
FB
2B
p 0013 ~6
P 0016 9F
P 0017 E6
FB
20
Fl
~F
(
P 001A AF
P 001B
1 TIMER3 MODULE
2 GLOBAL
PROCEDURE
3 TIMER_16
~ ENTRY
PRE1,U%(2)00101000
LD
5
6
!bit 2-7: pres caler = 10;
bi t 1: external clock;
7
bit 0: single-pass mode!
8
LD
P3M,1100
Ibit 5: let P36 be Toutl
9
10
LD
T1,11100
! Tl counter register!
11
PREO,#%(2)00101001
LD
12
!bit 2-7: prescaler = 10;
13
bit 0: continuous mode!
14
LD
TO,Ul00
!TO counter register!·
15
DI
16
IMR,#%(2)00101011 !disable IRQ2 (Tin);
AND
17
and IRQ~ (TO) !
18
IMR,U%(2)00100000 ! ena bl e IRQ5 (Tl) !
OR
19
EI
20
LD
TMR,U%(2)01001111
21
Ibit 6-7: Tout controlled
22
by TO;
23
bit ~-5: Tin mode is ext.
24
clock input;
25
bit 3 : enable Tl;
26
bit 2: load Tl;
27
bit 1 : enable TO;
28
bit 0: load TO !
RET
29
TIMER_16
30 END
31 END
TIMER3
o ERRORS
ASSEMBLY COMPLETE
11 instructions
27 bytes
26.5 ps
7.4.4 Clock Monitor. TI and TIN may be used
to monitor a clock line (in a diskette drive, for
example) and generate an interrupt request
when a clock pulse is missed. To accomplish
this, the clock line to be monitored is wired to
P31 (TIN). TIN should be programmed as a
retriggerable input to TI, such that each falling edge on TIN will cause TI to reload and
continue counting. If T I is programmed to
time-out after an interval of one-and-a-half
times the clock period being monitored, T I
will time-out and generate interrupt request
IRQ5 only if a clock pulse is missed.
Z8ASM
LOC
2.0
OBJ CODE
STMT SOURCE STATEMENT
1 TIMER4 MODULE
2
$SECTION PROGRAM
3 GLOBAL
~ !IRQ5 interrupt vectorl
$ABS
10
5
6 IRQ_5
[1 WORD]
[CLK_ERR]
ARRAY
7
8
$REL
PROCEDURE
9 MONITOR_INIT
10 ENTRY
11
PRE1,U%(2)00000100
LD
12
!bit 2-7: prescaler = 1;
13
bit 1 external clock;
14
bit 0 single-pass model
15
LD
P3M,1100
Ibit 5 let P36 be Tout!
16
LD
Tl ,113
Tl load register,
17
I
1.5 * 2 use c
.
P 0000 0015'
P OOOC
188
The following module illustrates the procedure for initializing T I and TIN
(MONITOR_INIT) to monitor a clock with a
period of 2 p.s. XTAL = 8 MHz is assumed.
Note that this example selects single-pass
rather than continuous mode for T I. This is to
prevent a continuous stream of IRQ5 interrupt
requests in the event that the monitored clock
fails completely. Rather, the interrupt service
routine (CLK_ERR) is left with the choice of
whether or not to re-enable the monitoring.
Also shown is the TI .interrupt vector (IRQ_5).
P 0000 E6
F3
O~
P 0003 E6
P 0006 E6
F7
F2
00
03
7. Timer/
Counter
Functions
(Continued)
P
P
P
P
0009
OOOA
OOOD
0010
8F
56
46
9F
FB
FB
3B
20
P 0011 E6
F1
38
P 0014 AF
P 0015
P 0015
P 0015 46
F1
08
r
P 0018 BF
P 0019
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DI
AND
OR
EI
LD
END
IMR,U%(2)00111011
IMR,U%(2)00100000
! di sa bl e IRQ2 (Tin) I
I enable IRQ5 (T1) !
TMR,U%(2)00111000
Ibit 4-5: Tin mode is
retrig. input;
bit 3: enable T1 !
RET
MONITOR_ INIT
CLK_ERR PROCEDURE
ENTRY
! •.. !
!handle the missed clock!
!if clock monitoring should continue ..• !
TMR,U%(2)00001000
OR
!bit 3: enable T1 I
IRET
CLK_ERR
END
END
TIMER4
o ERRORS
ASSEMBLY COMPLETE
MONITOR_INIT:
9 instructions
21 bytes
21.5 p.s
SEC'ii'1I0N
8
eLK_ERR:
2 + instructions
4 + bytes
18.5 +, p.s including interrupt response time
110 Functions
The 28 provides 32 I/O lines mapped inio
registers 0-3 of the internal register file. Each
nibble of port 0 is individually programmable
as input, output, or address/data lines
(Als-AI2, All-As). Port 1 is programmable as
a single entity to provide input, output, or
address/data lines (AD7-ADo). The operating
modes for the bits of Ports 0 and 1 are selected
by control register P01M (%F8). Selection of
I/O lines as address/datCl lines supports access
to external program and data memory; this is
discussed in Section 3. Each bit of Port 2 is
individually programmable as an input or an
Function
Bit
Handshake
P3]
P32
P33
P34
P35
P36
Interrupt
Request
r
Signal
DAV2/RDY2
I5AVO/RDYO
DAVI/RDYI
RDYI/DAVI
RDYO/lSAVO
RDY2/I5AV2
P3]
30
P32
P33
IRQ3
IRQ2
IRQO
IRQ I
Timer
{ P3]
P3 6
TIN
TOUT
Data Memory
Select
Status Out
{ P34
m
Serial 1/0
{ P30
P37
Serial In
Serial Out
Counter!
Table 4. Port 3 Special Functions
output bit. Port 2 bits programmed as outputs
may also be programmed (via bit 0 of P3M) to
all have active pull-ups or all be open-drain
(active pull-ups inhibited). In Port 3, four bits
(P30-P33) are fixed as inputs, and four bits
(P34-P37) are fixed as outputs, but their functions are programmable. Special functions provided by Port 3 bits are listed in Table 4. Use
of the Data Memory select output is discussed
in Section 3; uses of TIN and TOUT are dis- cussed in Section 7.
8.1 Asynchronous Receiver/Transmitter
Operation. Full-duplex, serial asynchronous
receiver/transmitter operation is proVided by
the 28 via P37 (output) and P30 (input) in conjunction with control register SIO (%FO),
which is actually two registers: receiver buffer
and transmitter buffer. Counter/Timer To provides the clock for control of the bit rate.
The 28 always receives and transmits eight
bits between start and stop bits. However, if
parity is enabled, the eighth bit (D7) is
replaced by the odd-parity bit when transmitted and a parity-error flag ( = I if error)
when received. Table 5 illustrates the state of
the parity bit/parity error flag during serial
I/O with parity enabled.
Although the 28 directly supports either odd
parity or no parity for serial I/O operation,
even parity may also be prov;ided with additional software support. To receive and
transmit with even parity, the 28 should be
configured for serial I/O with odd parity
disabled. The 28 software must calculate parity
189
8. I/O
Functions
(Continued)
Character Loaded
Into SIO
Transmitted To
Serial Line
Received From
Serial Line
Character
Transferred To SIO
11000011
11000011
01111000
01111000
01000011
01000011
11111000
11111000
01000011
01000111
11111000
01111000
01000011
11000111
01111000
11111000
Table 5. Serial 1/0 With Odd Parity
and modify the eighth bit prior to the load of a
character into SIC) and then modify a parity
error £lag following the load of a character
from SIO. All other processing required for
serial 110 (e.g. buffer management, error
handling, etc.) is the same as that for odd
parity operations.
To configure the Z8 for Serial 110, it is
necessary to:
ID
Enable P30 and P37 for serial 1/0 and select
parity,
• Set up To for the desired bit rate,
R Configure IRQ3 and IRQ4 for polled or
automatic interrupt mode,
II
Load and enable To.
To enable P30 and P37 for serial 110" bit 6 of
P3M (R247) is set. To enable odd parity, bit 7
of P3M is set; to disable it, the bit is reset. For
example, the instruction
LD
P3M,#%40
will enable serial 110, but disable parity. The
instruction
LD
P3M,#%CO
will enable serial 1/0, and enable odd parity.
In the following discussions, bit rate refers to
all transmitted bits, including start, stop, and
parity (if enabled). The serial bit rate is given
by the equation:
bit rate =
input clock frequency
(2 x 4 x TO prescaler x TO counter x 16)
The final divide-by-16 is incurred for serial
communications, since in this mode To runs at
16 times the bit rate in order to synchronize
the data stream. To configure the Z8 for a
specific bit rate, appropriate values must first
be selected for To prescaler and To counter by
the above equation; these values are then programmed into registers To (%F4) and PREO
(%F5) respectively. Note that PREO also controls the continuous vs. single-pass mode for
To; continuous mode should be selected for
serial 1/0. For example, given an input clock
frequency of 7.3728 MHz and a selected bit
rate of 9600 bits per second, the equation is
190
Note*
no error
error
no error
error
• Left·most bit is 07
satisfied by To counter
2 and prescaler = 3.
The following code sequence will configure the
To counter and To prescaler registers:
LD
LD
To,#2 !To counter = 2!
PREO,#%(2)00001101
!bit 2-7: prescaler = 3; bit 0:
continuous mode!
Interrupt request 3 (IRQ3) is generated
whenever a character is transferred into the
receive buffer; interrupt request 4 (IRQ4) is
generated whenever a character is transferred
out of the transmit buffer. Before accepting
such interrupt requests, the Interrupt Mask,
Request, and Priority Registers (IMR, IRQ, and
IPR) must be programmed to configure the
mode of interrupt response. The section on
Interrupt Processing provides a discussion of
interrupt configurations.
To load arid enable To, set bits 0 and lof
the timer mode register (TMR) via an instruction such as
OR
TMR,#%03
This will cause the To prescaler and counter
registers (PREO and To) to be transferred to the
To prescaler and counter. In addition, To is
enabled to count, and serial 1/0 operations
will commence.
Characters to be output to the serial line
should be written to serial 1/0 register SIO
(%FO). IRQ4 will be generated when all bits
have been transferred out.
Characters input from the serial line may be
read from SIO. IRQ3 will be generated when a
full character has been transferred into SIO.
The following module illustrates the receipt
of a character and its immediate echo back to
the serial line. It is assumed that the Z8 has
been configured for serial 1/0 as described
above, with IRQ3 (receive) enabled to interrupt,
and IRQ4 (transmit) configured to be polled.
The received character is stored in a circular
buffer in register memory from address %42 to
%5F. Register %41 contains the address of
the next available buffer position and should
have been initialized by some earlier routine
to #%42.
8. I/O
Functions
(Continued)
Z8ASM
LOC
2.0
OBJ CODE
STMT SOURCE STATEMENT
1 SERIAL_IO
2 CONSTANT
MODULE
%41
3 next_addr
4 start
%42
._
%1E
5 length
6 $SECTION PROGRAM
7 GLOBAL
8 !IRQ3 vector!
$ABS
6
9
ARRAY [1 WORD] ._ [GET_CHARACTER]
10
P 0006 0000'
11
P 0000
P 0000 E4
FO
FO
P 0003 F5
P 0006 20
P 0008 A6
FO
41
41
41
60
P OOOB EB
P OOOD E6
03
41
42
P 0010 66
P 0013 EB
FA
FB
10
P 0015 56
P 0018 BF
P 0019
FA
EF
12
$REL
o
PROCEDURE
ENTRY
13 GET_CHARACTER
14
15 !Serial 1/0 receive interrupt service!
16 !Echo received character and wait for
17 echo completion!
18
ld
SIO,SIO
!echo!
19
20 !save it in circular buffer!
21
@next_addr,SIO !save in buffer!
ld
22
next_addr
!point to next position!
inc
cp
next_addr,#start+length
23
24
!wrap-around yet?!
ne,echo_wait
!no.!
25
jr
26
next_addr,#start ryes. point to start!
ld
27 !now, wait for echo complete!
28 echo_wait:
!transmitted yet?!
IRQ,#%10
tcm
29
! not yet!
nz, eCho_wai t
30
jr
31
!clear IRQ4!
and
IRQ,#%EF
32
IRET
!return from interrupt!
33
GET_CHARACTER
34 END
SERIAL_IO
35 END
o ERRORS
ASSEMBLY COMPLETE
10 instructions
25 bytes
35.5 Ps +,5.5 Ps for each additional pass through the echo_wait loop,
including interrupt response time
8.2 Automatic Bit Rate Detection. In a typical
system, where serial communication is
required (e.g. system with a terminal), the
desired bit rate is either user-selectable via a
switch bank or nonvariable and "hard-coded"
in the software. As an alternate method of bitrate detection, it is possible to automatically
determine the bit rate of serial data received
by measuring the length of a start bit. The
advantage of this method is that it places no
requirements on the hardware design for this
function and provides a convenient (automatic)
operator interface.
In the technique described here, the serial
channel of the 28 is initialized to expect a bit
rate of 19,200 bits per second. The number of
bits (n) received through Port pin P30 for each
bit transmitted is expressed by
uishing between the bit rates shown in Table 6
and assumes an input clock frequency of
7.3728 MHz, a To prescaler of 3, and serial I/O
enabled with parity disabled. This example
requires that a character with its low order
bit = I (such as a carriage return) be sent to
the serial channel. The start bit of this
character can be measured by counting the
number of zero bits collected before the low
order I bit. The number of zero bits actually
collected into data bits by the serial channel is
less than n (as given in the above equation),
due to the detection of start and stop bits.
Figure 4 illustrates the collection (at 19,200
n = 19,200/b
where b = transmission bit rate. For example,
if the transmission bit rate were 1200 bits per
second, each incoming bit would appear to the
receiving serial line as 19,20011200 or 16 bits.
The following example is capable of disting-
ST
= START BIT
SP
= STOP BIT
On
= DATA BIT n
=
EACH INTERVAL SHOWN
1 BIT TIME
AT 19,200 BITS PER SECOND
Figure 4. Collection of a Start Bit Transmitted at
at 19,200 BPS
191
8. 1/0
Number 01 Bits Received
Per Bit Transmitted
Bit Rate
Functions
Number 01 0 Bits Collected
as Data Bits
(Continued)
19200
9600
4800
2400
1200
600
300
150
1
2
4
8
16
32
64
128
dec
binary
0
1
3
7
13
25
49
97
00000000
00000001
00000011
00000111
00001101
00011001
00110001
01100001
To Counter
dec
1
2
4
8
16
32
64
128
binary
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
Table 6. Inputs to the Automatic Bit Rate Detection·Algorlthm
character has been received, thus "flushing"
the serial line. This can be accomplished
either via a software loop, or by programming
T1 to generate an interrupt request after
the appropriate amount of time has elapsed.
Since a character is composed of eight bits
plus a minimum of one stop bit follOWing the
start bit, the length of time to delay may be
expressed as
(9 x n)/b
bits per second) of a zero bit transmitted to the
28 at 1,200 bits per second. Notice that only 13 '
of the 16 zero bits received are collected as
data bits.
Once the number of zero bits in the start bit
has been collected and counted, it remains to
translate this count into the appropriate To
counter value and program that value into To
(%F4). The patterns shown in the two binary
columns of Table 6 are utilized in the
algorithm for this translation.
As a final step, if incoming data is to commence immediately, it is advisable to wait until
the remainder of the current "elongated"
ZBASM
LOC
2.0
OBJ CODE
STMT SOURCE STATEMENT
P 0000
\ P 0000
p 0001
p 0004
p 0007
P OOOA
P OOOD
BF
56
56
E6
E6
E6
FB
FA
F7
F4
F5
77
F7
40
01
OD
P 0010 BO
P 0012 E6
EO
Fl
03
P
P
P
P
P
P
P
0015 76
0018 6B
001 A 18
001C 56
001 F 1 E
0020 1 A
0022 06
p 0025 BB
P
P
P
P
0027
0029
002B
002C
EO
7B
OE
BB
05
EO
EE
El
03
F9
P 002E lC
0030 2C
0032 90
07
BO
EO
p
EO
p
p
192
FA
FB
FO
FA
0034 90
where nand b are as defined above. The
following module illustrates a sample program
for. automatic bit rate detection.
oB
F7
OB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
lB
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
3B
39
40
41
42
bi t_rate
MODULE
EXTERNAL
DELAY
PROCEDURE
GLOBAL
PROCEDURE
main
ENTRY
di
Idisable interrupts I
and
IMR,II%77
IIRQ3 polled model
and
IRQ,II'foF7
Iclear IRQ3!
Id
P3M,II%40
!enable serial 1/01
Id
TO,lll
Id
PREO, II( 3 SHL 2)+1 Ibit rate = 19,200;
continuous count model
clr
RO
linit. zero byte counter!
.ld
TMR,1I3
Iload and enable TOI
!collect input bytes by counting the number of null
characters received. Stop when non-zero byte received I
collect:
TM
IRQ,II%OB
!character received?1
jr
z,collect Inot yet!
Id
Rl,SIO
'!get the character!
and
IRQ,II'foF7
Iclear interrupt request I
inc
Rl
Icompare to 0 ••• 1
djnz
Rl,bitloop ! ••• (in 3 bytes of code)1
add
RO,118
!update count of 0 bits!
jr
collect.
bitloop:
ladd in zero bits from low
end of 1st non-zero by tel
RR
Rl
jr
c,count_done
inc
RO
jr
bitloop
I RO has number of zero bits collected!
I translate RO to the appropriate TO counter val ue I
count_done:
!RO has count of zero bits!
Id
Rl ,117
R2,II%BO
Id
IR2 will have TO counter value I
RL
RO
loop:
RL
RO
8. 1/0
Functions
(Continued)
P 0036 7B
P 0038 EO
P 003A 1A
04
E2
F8
P 003C 29
F4
P 003E D6
0000l!
P 0041 56
FA
F7
P 0044
43
44
45
46
47
48
49
50
51
52
53
54
55
jr
RR
djnz
c,done
R2
r1,loop
lloa1 value for detected
bit rate!
!Delay long enough to clear serial line of bit stream!
DELAY
call
!clear receive interrupt request!
and
IRQ,II%F7
done:
Id
END
END
main
bit_rate
TO,R2
o ERRORS
ASSEMBLY COMPLETE
30 instructions
68 bytes
Execution time is variable based on transmission bit rate.
8.3 Port Handshake. Each of Ports 0, I and 2
may be programmed to function under input or
output handshake control. Table 7 defines the
port bits used for the handshaking and the
mode bit settings required to select handshaking. To input data under handshake control,
the 28 should read the input port when the
DA V input goes Low (signifying that data is
available from the attached device). To output
data under handshake control, the 28 should
write the output port when the RDY input goes
Low (signifying that the previously output data
has been accepted by the attached device).
Interrupt requests IRQO, IRQI, and IRQ2 are
generated by the falling edge of the handshake
signal input to the 28 for Port 0, Port I, and
Port 2 respectively. Port handshake operations
may therefore be processed under interrupt
control.
Consider a. system that requires communication of eight parallel bits of data under handshake control from the 28 to a peripheral
device and that Port 2 is selected as the output
port. The following assembly code illustrates
the proper sequence for initializing Port 2 for
output handshake.
Pori 0
CLR P2M
!Port 2 mode register: all Port
2 bits are outputs!
OR
%03,#%40
!set DAV2: data not available!
LD
P3M,#%20
!Port 3 mode register: enable
Port 2 handshake!
LD
%02,DATA
!output first data byte; DA V2
will be cleared by the 28 to
indicate data available to
the peripheral device!
Note that following the initialization of the output sequence, the software outputs the first
data byte without regard to the state of the
RDY2 input; the 28 will automatically hold
DAV2 High until the RDY2 input is High. The
peripheral device should force the 28 RDY2
input line Low after it has latched the data in
response to a Low on DAV2. The Low on RDY2
will cause the 28 to automatically force DA V2
High until the next byte is output. Subsequent
bytes should be output in response to interrupt
request IRQ2 (caused by the High-to-Low transition on RDY2) in either a polled or an
enabled interrupt mode.
Pori I
Pori 2
Input handshake lines
{P32 ~ DAY
P3s ~ RDY
P33 ~ row
P34 ~ RDY
Output handshake lines
{P32 ~ RDY
P3s ~ DAY
P33 ~ RDY
P34 ~ IiAV
To select input handshake:
{ set bit 6 & reset bit 7 of
POIM (program high
nibble as input)
set bit 3 & reset bit 4 of
POIM (program byte as
input)
set bit 7 of P2M
(program high bit as input)
To selec! output handshake:
{reset bits 6, 7 of POIM
(program high nibble as
output)
reset bits 3, 4 of POIM
(program byte as output)
reset bit 7 of P2M
(program high bit as output)
To enable handshake:
{set bit 5 of Port 3 (P3S);
set bit 2 of P3M
set bit 4 of Port 3 (P34);
set bits 3, 4 of P3M
set bit 6 of Port 3 (P36);
set bit 5 of P3M
P3] ~ IiAV
P36 ~ RDY
P3] ~ RDY
P36 ~ IiAV
Table 7. Pori Handshake Selection
193
SECTION
9
Arithmetic Routines
This section gives examples of the arithmetic
and rotate instructions for use iI1 multiplication, division, conversion, and BCD arithmetic
algorithms.
cessed one nibble at a time from left to right,
beginning with the high-order nibble of the
lower memory address. %30 is added to each
nibble if it is in the range 0 to 9; otherwise
%37 is added. In this way, %0 is converted to
%30, %1 to %31, ... %A to %41, ... %F to
%46. Figure 5 illustrates the conversion of RRO
(contents = %F2BE) to its hex ASCII
equivalent; the destination buffer is pointed to
by RR4.
9.1 Binary to Hex ASCII. The following
module illustrates the use of the ADD and
SWAP arithmetic instructions in the conversion
of a 16-bit binary number to its hexadecimal
ASCII representation. The 16-bit number is
viewed as a string of four nibbles and is proBIT
0,
I
"1:,
REGISTER
Do
3
4
""'"F"""
0,
I I,
'2;
Do
4 3
::"u,
R'
I<
R1
"
e:
I
4
RR4 -
:
I' , ',2
Figure 5. Conversion of (RRO) to Hex ASCII
Z8ASM
LOC
Dr
1
.
Do
3
',~'
; '5',
:
'"
iNTERNAL RELEASE
STMT SOURCE STATEMENT
2.99
OBJ CODE
1 ARITH
MODULE
2 GLOBAL
3 BINASC PROCEDURE
4 !*****************************************************
To convert a 16-bit binary
5 Purpose
6
number to Hex ASCII
P 0000
7
8
9
P
P
P
P
0000
0002
0004
0006
6C
FO
28
56
04
EO
EO
E2
P
P
P
P
P
P
0009
OOOC
OOOF
0011
0014
0016
06
A6
7B
06
92
AO
E2
E2
03
E2
24
E4
30
3A
P 0018 A6
P 001B EB
P 001D 08
E6
02
El
03
P 001F 6A
P 0021 AF
P 0022
El
OF
07
o errors
Assembly complete
15 instructions
34 bytes
120.5 /lS (average)
194
Do
Input
RRO
16-bit binary number.
RR4 = pointer to destination
buffer in external memory.
10
11
Resulting ASCII string (4 bytes)
12 Output
in desoination buffer.
13
14
RR4 incremented by 4 •
RO,R2,R6 destroyed.
15
16 *****************************************************!
17 ENTRY
18
R6,#104 !nibble count!
ld
19
RO
!look at next nibble!
20 again: SWAP
2'1
R2, RO
Id
R2,IIIOF !isolate 4 bits!
22
and
23 !convert to ASCII :R2 + #%30 if. RO in ranBe 0 to 9
else R2 + #137 (in range OA to OF)
24
25
R2 , 11130
26
ADD
cp
R2, #%3A
27
ul t, skip
28
jr
R2,11107
ADD
29
!save ASCII in buffer!
@RR4, R2
Ide
30 skip:
RR4
!point to next
incw
31
buffer position!
32
R6,II%03 !time for second byte?!
cp
33
ne,same_byte
!no.
!
jr
34
!2nd byte!
RO, Rl
Id
35
36 same_byte:
djnz
R6,again
37
ret
38
BINASC
END
39
40 END
ARITH
I
9. Arithmetic 9.2 BCD Addition. The following module illustrates the use of the add with carry (ADC) and
Routines
(Continued)
significant digit in bits 7-4. Bytes within a
BCD string are arranged in memory with the
most significant digits stored in the lowest
memory location. Figure 6 illustrates the
representation of 5970 in a 6-digit BCD string,
starting in register %33.
decimal adjust (DA) instructions for the addition of two unsigned BCD strings of equal
length. Within a BCD string, each nibble
represents a decimal digit (0-9). Two such
digits are packed per byte with the most
~
BIT
rc'i"o:" ) ]
in which
( )
[ ]
Parentheses mean that the enclosed
times or can be omitted.
Brackets denote that, the enclosed
element is optional.
Table 3 illustrates how various input strings
are interpreted by the conversion routines.
5.
The format of the decimal ASCII character
string output from the conversion routine
'''bcddasc'' operating on an input BCD string of
2n digits is
sign of character ( + 1 - )
2n-x pre-decimal digits
1 decimal point if x does not equal 0
x post-decimal digits
6.
The format of the decimal ASCII character
string output from the conversion routine
"wrddassc" is
1 sign character (determined by bit 15 of
input word)
6 pre-decimal digits
no decimal point
no post-decimal digits '
Table 2.
Address
NIIIIIe
Subroutine Entry Points
Description
Binary Arithmetic Routines
001B
001E
0021
0024
divide
div 16
multiply
mult 16
16/8 unsigned binary division
16/'16 unsigned binary division
8x8 unsigned binary multiplication
16x16 unsigned binary multiplication
BCD Arithmetic Routines
0027
002A
bcdadd
bcdsub
, BCD addition
BCD subtraction
COnversion Routines
0020
0030
0033
0036
0039
003C
003F
0042
0045
bcddasc
dascbcd
bcdwrd
wrdbcd
bythasc
wrdhasc
hascwrd
wrddasc
dascwrd
BCD to decimal ASCII
Decimal ASCII to BCD
BCD to binary word
Binary word to 8CD
Binary byte to hexadecimal ASCII
Binary word to hexadecimal ASCII
Hexadecimal ASCII to binary word
Binary word to decimal ASCII
Decimal ASCII to binary word
Bit Manipulation Routines
0048
004B
clb
tmj
Collect bits in a byte
Table jump under mask
Serial Routines
004E
0051
0054
0057
005A
0050
0060
0063
0066
0069
ser init
ser_input
ser rlin
ser rabs
ser break
ser flush
ser-wlin
ser wabs
ser_wbyt
ser disable
Initialize serial I/O
IRQ3' (receive) service
Read line
Read absolute
Transmit BREAK
Flush (clear) input buffer
Write line
Write absolute
Write byte
Disable serial I/O
Timer/COunter Routines
006C
006F
0072
0075
. 0078
tod i
tod
delay
pulse_i
pulse
Initialize for time-of-day clock
Time-of-day IRQ service
Initialize for delay interval
Initialize for pulse output
Pulse IRQ service
201
7.
The register pair SERhtime, SER1time was
initialized during ser
in it to equal the
'product of the prescaler and the counter
selected for the baud rate clock. That is,
Procedure name: ser___input
The conclusion of the algorithm for BREAK
detection requires the Serial Receive Shift
register to be cleared of the character
currently being collected (if any).
This
requires a software wait
loop of a
one-character duration.
,The following
explains the algorithm used (code lines, 464
through 472, Part II):
1 character time
=
SERhtime, SER1time = PREO x TO
The instruction sequence
inlop: ld
rSERtmpl, 853
(6 cycles)
(12BxPREOxTO) sec 10 ,~
XT AL
bIT x
char
lpl:
rSERtmpl, lpl
(12/10 cycles
taken/not taken)
1280xPREOxTO sec
CiiBr,
XTAL
executes in
6 + (52 x 12) + 10 cycles = 640 cycles
A software loop equal to one character time is
needed:
8.
1 character time =.3... ~ x n cycle
XTAL cycle
loop
2n
= XTAL
sec
loop
Solve for n:
(1280 x PREO x TO)
XTAL
djnz
2n
= Xfii[
BREAK detection on the serial input line
requires that the receive interrupt service
routine be entered within a half-a-bit time,
since the routine reads the, input line, to
detect a true (=1) or false (=0) stop bit.
Since the interrupt request is generated
halfway through reception of the stop bit,
half-a-bit time remains in which to read the
stop bit level.
Interrupt priorities and
interrupt nesting should be established
appropriately to ensure this requirement.
n = 640 x PREO x TO
1/2 bit time =
(128 x PREO x TO)
XTAL x 2
Table ,. Deemsl ASCII Character String Interpretation
Input Stfing
+1234.567,
Sign
Result
Pre-Deciasl
Digits
Post-Deciaal
Digits
+
1234
567
789
+---+.789+
1234 ••
+
4976-
+
NOTE:
202
Terllinstor
+
1234
4976
The terminator can be any ASCII character that is not a valid ASCII string
character.
sec
ROMLESS Z8 SUBROUTINE LIBRARY PART I
Zf\ASM
LOC
3.02
OBJ CODE
STMT SOURCE STATEMENT
1
2
3 PART I
MODULE
II
5
6 !'ROMLESS Z8'
7
8
Initialize:
9
10
11
12
13
111
15
16
17
18
SUBROUTINE LIBRARY
PART I
a) Port 0 & Port 1 set up to address
611K external memory;
b) internal stack below allocated
RAM for subroutines;
c) normal memory timing;
d) IMR, IRQ, TMR, RP cleared;
e) Port 2 inputs open-drain pull-ups;
f) Data Memory select en~bled;
g) EI executed to' 'unfreeze' IRQ;
h) Jump to %0812.
19
20 Note:
21
22
23
211
25
26
27
28
29
30
31
32
33
311
35
36
37
38
39
110
111
112 I
The user is -free to modify the initial
conditions selected for a, b, and c above,
via direct modification of the PortO & 1
Mode register (P01M, %F8).
The user is free to modify the conditions
selected in the Port 3 Mode register (P3M, %F7).
However, please note that P3M is a write-only
register. This subroutine library maintains
an im'lge of P3M in its register P3M_save (%7F).
If software outside of the subroutine package
is to modify P3M, it should reference and modify
P3M save, prior to modification of P3M. For
example, to sel,ect P32/P35 for handshake, use
an instruction sequence such as:
OR
LD
P3M save,UOIi
P311,P3M_save
This is important i f 'the serial and/or timerl
counter subroutines are to be used, since these
routines may modify P3M.
203
44 IAccess to GLOBAL subroutines in this library should
45 be made via a CALL to the corresponding entry in the
46 jump table which begins at address SOOOF. The jump
47 tab~e should be referenced rather than a CALL to the
48 actual entry point of the subroutine to avoid future
49 conflict in the event such entry points change in
50 potential future revisions.
51
52 Each GLOBAL subroutine in this listing is headed by a
53 comment block specifying its PURPOSE .and calling
54 sequence (INPUT and OUTPUT.parameters). For many of
55 the subroutines in this library, the location of the
56 operands (s6urces/destinations) is ~uite flexible
57 between register memory, external memory (code/data),
58 and the serial channel (if enabled). The description
59 of each parameter specifies what th~ location choices
60 are:
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
- The location designation 'in reg/ext memory'
implies that the subroutine allows that the operand
exist in eith.r register or external data memory
The address of such an operand is contained
'
in the designated register pair. If the high byte of
that pair is zero, the operand is in register memory
at the address given by the low byte of the register
pair. Otherwise, the operand is in external data
memory (accessed via LDE).
- The location designation
'in reg/ext/ser memory' implies the same
considerations as above with one enhancement: if both
bytes of the reg. pair are zero, the operand exists
76' in'the serial channel. In this case, the register
77 pair is not modified (updated). For example, rather
78 than storing a destination ASCII string in memory, it
79 might be desirable to output such to the serial line.
80 !
204
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
CONSTANT
! Register Usage!
RAM START
P3M save
TEMP 3
TEMP-2
TEMP-l
TEMP-4
·····--
·-
%7F
RAM START
P3M- save-l
TEM'P' 3-1
TEMP-2-1
TEMP-l-l
!The following registers are modified/referenced
by the Serial Routines ONLY. They are
available as general registers to the user
who does not intend to make use of'the
Serial Routines!
SER char
:=
TEMP 4-1
SER-tmp2
._
SER char-l
SER-tmpl
._
SER-tmp2-1
SER-put
'SER-tmpl-l
SER-len
._
SER-put-l
SER-buf
._
SER-len-2
SER-imr
._
SER-buf-l
SER-cfg
:=
SER-imr-l
! Serial Configuration Data =1 => odd parity on
bit 7
bit 6 : =1 => even parity on
(bit 6,7 = 11 => undefined)
bit 5
undefined
bit 4
undefined
bit 3
=1 => input editting on
=1 => auto line feed enabled
bit 2
bit 1
=1 => BREAK detection enabled
=1 => input echo on
bit 0
op
ep
ie
al
be
ec
SER get
SER-flg
! Serial
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
··-·.'--
··--
%80
%40
%08
%04
%02
%01
·: =-
SER cfg-l
SER=get-l
Status Flags
=1 => serial I/O disabled
undefined
undefined
=1 => parity error
=1 => BREAK detected
=1 => input buffer overflow
=1,=> input buffer not empty
=1 => input buffer full
!
sd
pe
bd
bo
bne
bf
=
=
=
=
=
%80
$10
%08
%04
%02
%01
RAM TMR
:=
RAM_START-%10
SERltime
:=
SER_flg-l
205
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
206
SERhtime
SERltime-l
!The following registers are modified/referenced
by the Timer/Counter Routines ONLY. They are
available as general registers to the user
who does not intend to make use of the
Timer/Counter Routines!
TOD tic
TOD-imr
TOD-hr
TOD-min
TOD-sec
TOD-tt
PLS-l
PLS-tmr
PLS-2
RAM TMR-2
TOD-tic-1
TOD-imr-1
TODnr-1
TOD-min-1
TOD-sec-1
TOD-tt-1
PLS-1-1
PLS-tmr-1
RAM END
STACK
!Equivalent working register equates
for above register layoutl
!register file %70 RAM STARTr
._
rP3Msave
rTEMP 3
rTEMP 2
rTEMP-1
rrTEMP 1
rTEMP1h
rTEMP-ll
rTEMP-4
rSERchar
rSERtmp2
rSERtmp1
rrSERtmp
rSERtmpl
rSERtmph
rSERput
rSERlen .
rrSERbuf
rSERbufh
rSERbufl
rSERimr
rSERcfg
rSERget
rSERflg
:=
:=
:=
:=
:=
:=
:=
:=
~7F!
%70
I for SRPI
R15
R14
R13
R12
RR12
R12
R13
R11
Rl0
R9
R8
RR8
R9
R8
R7
R6
RR4
R4
R5
R3
R2
R1
RO
!register file %60 - %6F!
RAM TMRr
%60
:=
rTOTItic
R13
rTODimr
R12
!=
rTODhr
R11
:=
rTODmin
R10
:=
rTODsec
R9
:=
rTODtt
R8
rPLS 1
:=
R7
rPLStmr
R6
:=
rPLS 2
R5
I for SRPI
P 0000
P 0002
p 0004
P 0006
p 0008
p OOOA
0800
OB03
0806
OB09
080C
080F
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
23B
239
240
241
242
EXTERNAL
ser init
ser-input
ser-rlin
ser-rabs
ser-break
ser-flush
ser-wlin
ser-wabs
ser-wbyt
ser-disable
ser-get
ser-output
tod-i
toddelay
pulse i
pulse -
GLOBAL
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
$.SECTION PROGRAM
!Interrupt vectors!
IRQ 0
ARRAY
[ 1 word]
IRQ-1
ARRAY
[ 1 word]
IRQ-2
ARRAY
[ 1 word]
IRQ-3
ARRAY
[ 1 word]
IRQ-4
ARRAY
[ 1 word]
ARRAY
[ 1 word]
IRQ=5
=
=
=
=
=
=
[~OBOO]
[%0803]
[%0806]
[%OB09]
[%OBOC]
[~080F]
207
P OOOC
P OOOC 80
P OOOF
P
P
P
P
OOOF
0012
0015
0018
28
31
30
4C
007B'
43
39
5A
4F
29
38
49
47
P 001B
P 001B 80
0099'
P 001E 80
00B7'
P 0021 80
00E2'
P 0024 80
00F6'
P 0027 80
011A'
P 002A 80
0117 '
P 0020 80
0205'
P 0030 80
0363'
P 0033 80
0284'
P 0036 80
02CD'
P 0039 80
025C'
P 003C 80
0257'
P 003F 80
0319'
P 0042 80
03BE'
P 0045 80
0340'
P 0048 80
OIlA l'
P OOIlB 80
01lB9'
P
001l~
208
80
0000·
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
3011
GLOBAL
!Jump Table!
ENTER
PROCEDURE
ENTRY
INIT
JP
END
ENTER
copyright ARRAY [* BYTE] : = '(C)1980ZILOG'
!Subroutine Entry Points!
PROCEDURE
JUMP
ENTRY
!Binary Ar i thmet ic Routines!
JP
divide
JP
div 16
JP
multiply
JP
mult 16
!16/8 unsigned binary
division!
!16/16 unsigned binary
division!
!8x8 unsigned binary
multiplication! ,
!16x16 unsigned binary
multiplication!
!BCD Arithmetic Routines!
JP
bcdadd
!BCD addition!
JP
bcdsub
!BCD subtraction!
! Conversion Routines!
JP
bcddasc
JP
dascbcd
! Decimal ASCII to BCD!
JP
bcdwrd
!BCD to binary word!
JP
wrdbcd
!binary word to BCDI
JP
bythasc
IBin. byte to Hex ASCII!
JP
wrdhasc
IBin. word to hex ASCIII
JP
hascwrd
! Hex ASCII to bin wordl
JP
wrddasc
! Bin. word to dec ASCIII
JP
dascwrd
I dec ASCII to bin wordl
!BCD to decimal ASCII!
! Bit Manipulation Routinesl
JP
clb
!collect bits In a by tel
JP
tjm
I Table Jump Under Mask I
!Serial Routines!
JP
ser in it
!initialize serial I/OI
P 0051 80
0000·
p, 0054 80
0000·
P 0057 80
0000·
P 005A 80
0000·
P 0050 80
0000 0
P 0060 80
0000 0
P 0063 80
0000 11
P 0066 PO
0000·
P 0069 80
0000·
P 006C 80
0000·
P 006F PO
0000·
P 0072 80
0000·
P 0075 80
0000 11
P 0078 80
0000·
P 007B
007B
P 007B E6
F8
07
P 007E E6
7F
10
P
P
P
P
P
P
P
P
P
7F
FF
Fl
F6
FA
FB
FO
70
F7
65
0081
0084
0087
0089
008C
008E
0090
0092
0095
E4
E6
BO
E6
BO
BO
BO
E6
9F
P 0096 80
P 0099
0812
FF
80
305
ser _input
JP
306
307
ser rlin
JP
308
309
ser rabs
JP
310
311
ser break
JP
312
313
ser flush
JP
314
315
ser wlin
JP
316
317
ser wabs
JP
318
319
ser_wbyt
JP
320
321
ser disable
JP
322
323
324 1Timer/Counter Routines 1
325
tod i
JP
326
327
tod
JP
328
329
delay
JP
330
331
pulse i
JP
332
333
pulse
JP
334
335
JUMP
336 END
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
!IRQ3 (receive) service!
tread line!
tread absolute!
1transmit BREAK!
! flush (clear)
input buffer!
!write line!
!write absolute!
!write byte!
!disable serial I/O!
!init for time of day!
!tod IRQ service!
!inij; for delay interval
!init for pulse output!
!pulse IRQ servicel
!Initialization!
PROCEDURE
INIT
ENTRY
END
LO
P01M,II~(2)11010111
LO
P3M_save,II~(2)00010000
LO
LO
CLR
LO
CLR
CLR
CLR
LO
EI
P3M,P3M save
SPL,IISTACK
TMR
P2M, II~FF
IRQ
IMR
RP
SER flg, 1I~80
JP
%0812
!internal stack;
AOO-A15;
normal memory
timing ,I
-
!P3M is write-only,
so keep a copy in
'RAM for later
reference !
! set up Port 3
!stack pOinter
!reset timers!
! all inputs 1
!reset into requests!
!disable interrupts 1
!register pointer!
!serial disabled!
!globally enable
interrupts !
INIT
209
Binary Arithmetic RouUnes
P 0099
P 0099 A9
P 009B AC
7C
08
P 009D A2
P 009F BB
BC
02
P OOAl DF
P 00A2 AF
P
P
P
P
P
P
P
P
00A3
OOA5
00A7
00A9
OOAB
OOAD
OOAF
OOBO
10
10
7B
A2
BB
22
DF
AA
Fl
P 00B2 10
ED
P 00B4 A8
P 00B6 AF
P 00B7
7C
210
ED
EC
04
BC
03
CB,
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
1119
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
CONSTANT
div LEN
DIVISOR
dividend HI
dividend-La
GLOBAL
divide PROCEDURE
R10
R11
R12
R13
, ••••••••••••• **** ••••• *•••••••• * ••••••• * •••••••••••••
Purpose
Input
Output
=
=
=
To perform a 16-bit by 8-bit unsigned
binary division.
Rll. = 8-bit divisor
RR12
16-bit dividend
R13 = 8-bit quotient
R12 = 8-bit remainder
Carry flag = 1 if overflow
= 0 if no overflow
R11 unmod ifi ed
••••••••••••••••••••••••••••••••••••••••••••••• **.***!
ENTRY
ld
ld
TEMP 1,div LEN
div_LEN,1/8-
! save caller's R101
ILOOP COUNTER!
ICHECK IF RESULT WILL FIT IN 8 BITS!
cp
DIVISOR,dividend HI
UGT,LOOP
TCARRY
jr
!overflow!
!CARRY
SCF
, ret
LOOP:
subt:
next:
IALL
0 (FOR RLC)!
11
RLC
RLC
jr
cp
jr
SUB
SCF
djnz
dividend LO
!DIVIDEND II 2!
dividend-HI
c,subt
DIVISOR,dividend_HI
UGT,next
!CARRY = 01
dividend_HI,DIVISOR
!TO BE SHIFTED INTO RESULT!
Ino flags affectedl
div_LEN,LOOP
DONEI
RLC
dividend LO
ld
ret
END divide
div_LEN,TEMP_
!CARRY = 0: no overflowl
!restore caller's R101
P 00B7
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
00B7
00B9
OOBB
OOBC
OOBE
OOCO
00C2
OOCII
00C6
00C8
OOCA
OOCC
OOCE
OODO
00D2
OODII
00D6
00D8
00D9
OODB
OODD
OODF
OOEl
00E2
79
7C
CF
BO
BO
10
10
10
10
7B
A2
BB
7B
A2
BB
22
32
DF
7A
10
10
78
AF
7C
10
EA
EB
ED
EC
EB
EA
OA
8A
OB
011
9B
05
B9
A8
E5
ED
EC
7C
P 00E2
P
P
P
P
P
P
P
P
P
P
P
P
00E2
OOEII
00E6
00E8
00E9
OOEB
OOED
OOEF
OOFl
00F3
00F5
00F6
A9
AC
BO
CF
CO
CO
FB
02
AA
A8
AF
7C
09
EC
EC
ED
02
CB
F6
7C
111111
11115
11116
11117
448
449
450
451
452
1153
11511
455
456
457
458
459
460
1161
462
463
464
465
1166
467
468
1169
470
1171
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
CONSTANT
R7
d16 LEN
=
dvsr hi
R8
=
dvsr-lo
R9
Rl0
rem hi
=
Rll
rem-lo
=
quot hi
R12
quot-lo
R13
GLOBAl:
div 16 PROCEDURE
I··T••••••••••••••••••••••••••••••••••••••••••••••••••
Purpose =
To perform a 16-bit by ,16-bit unsigned
binary division.
Input =
RR8 = 16-bit divisor
RR12 = 16-bit dividend
Output =
RR12 = 16-bit quotient
RR10
16-bit remainder
RR8 unmodified
..................
a....... a··························1
ENTRY
ld
ld
rcf
clr
clr
dlp 16: rlc
rlc
rlc
rlc
jr
cp
jr
jr
cp
jr
subt 16: sub
sbc
scf
skp_16: djnz
rlc
rlc
ld
ret
END div_16
TEMP 1,d16 LEN
d16_tEN,fll'O
rem hi
rem-lo
qUOt 10
quot-hi
rem To
rem-hi
c ,siTht 16
dvsr hi,rem hi
ugt,Skp 16 ult,subt ,16,
dvsr lo,rem 10
ugt,skp 16rem lo,avsr 10
rem=hi,dvsr=hi
d16 LEN,dlp 16
quot 10
quot-hi
d16_t:EN,TEMP_l
Isave caller's Rl0!
ILOOP COUNTER!
Icarry = O!
Ino flags affectedl
CONSTANT
,Rll
MULTIPLIER
:=
PRODUCT LO
:=
R13
PRODUCT-HI
R12
:=
mul LEN
Rl0
GLOBl"L
multiply
PROCEDURE
1············a.ou.Duu ••••• D•• U•• UD.UU ••••• uD.D ••• DD.UD
Purpose =
To perform an 8-bit by 8-bit unsigned
binary multiplication.
Input
=
Output =
Rl1 = multiplier
R13 = multiplicand
RR 12 = product
Rl1 unmodified
·····················································1
ENTRY
LOOP1:
NEXT:
END
ld
TEMP 1,mul LEN Isave caller's Rl0f
! 8 BITS!
mul t:EN,fl9ld
clr
PRODUCT HI
IINIT HIGH RESULT BYTE!
RCF
ICARRY = 01
RRC
PRODUCT HI
RRC
PRODUCT-LO
jr
NC,NEXTADD
PRODUCT HI,MULTIPLIER
djnz
mul_LEN~LOOPl
ld
mul LEN,TEMP 1 Irestore caller's Rl01
ret
multiply
211
522 CONSTANT
523 m16 LEN
:=
R7
524 prier hi
R8
:=
525 plier-lo
R9
526 prod lii
R10
527 prod-lo
R11
:=
528 mult-hi
R12
:=
529 mult-lo
R13
:=
530 GLOMI:
531 mult 16 PROCEDURE
532
533 Purpose
To perform an 16-bit by 16-bit unsigned
534
binary multiplication.
535
536 ~nput =
RRe = multiplier
RR12 = multiplicand
537
538
539 Output =
RQ10 = product (R10, R11, R12, R13)
540
RR8 unmodified
541
Zero FLAG = 0 if result> 16 bits
542
= 1 if result fits in 16
543.
(unsigne~) bits (RR12 = result)
544
545 ENTRY
546
ld
TEMP 1,m16 LEN !save calle~'s R71
116 BITSI
m16 1:EN,1I1'T
ld
547
548
clr
prod hi
linit product!
clr
prod:lo
549
rcf
ICARRY = O!
550
prod hi
551 100p16: rrc
prod-lo
Ibit 0 to carry 1
552
rrc
!multiplicand I 21
rrc
multoi
553
mult-lo
554
rrc
nc,next16
555
jr
556
add
prod lo,plier 10
prod~i,plieroi
557
adc
558 next16: djnz
m16 LEN,loop16 Inext bit!
m16-LEN,TEMP 1 Irestore caller's R71
559
ld
560
ld
TEMP 1,prod hi Itest product .•• 1
TEMP:1,prod:lo I ••• bits 31 - 161
or
561
ret
562
mult 16
563 END
I···T.................................................
P 00F6
·····················································1
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
00F6
00F8
OOFA
OOFC
OOFE
OOFF
0101
0103
0105
0107
0109
010B
010D
010F
0111
0113
0116
0117
212
79
7C
BO
BO
CF
CO'
CO
CO
CO
FB
02
12
7A
78
A9
44
AF.
7C
11
EA
EB
EA
EB
EC
ED
04
B9
A8
FO
7C
7C
EB
7C
BCD Arithmetic Routines
593 !The BCD format supported by the following arithmetic
594 and conversion routines allows representation
595 of signed magnitude variable precision BCD
596 numbers. A BCD number of 2n digits is
597 represented in n+1 consecutive bytes where
598 the byte at the lowest memory address
599 ('byte 0') represents the sign and post600 decimal digit count, and the bytes in the
601 next n higher memory locations ('byte l'
602 through 'byte n') represent the magnitude
603 of the BCD number. The address of 'byte 0'
604 and the value n are passed to the subroutines
605 in specified working registers. Digits are
606 packed two per byte with the most
607 significant digit in the high order nibble
608 of 'byte l ' and the least significant digit
609 in the low order nibble of ' byte n'. 'Byte 0'
610 is organized as two fields:
611
bit 7 represents sign:
612
= 1 => negative
613
= 0 => positive
614
bit 6-0 represent post-decimal digit
615
count
616 For example:
617 'byte 0'= 105 => positive, with 5 post-decimal digits
61e
180 => negative, with no post-decimal digits
619
%90 => negative, with 16 post-decimal digits
620
P 0117
P 0117 B7
P 011A
EE
80
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
CONSTANT
bcd LEN := R12
bcd-SRC ._ R14
bcd-DST ._ R15
GLOBAL
bcdsub PROCEDURE
!unu*unnnnunnu*nnftnnnunnnnnunnnuununnnununnuuaununn***
Purpose =
To subtract two packed BCD strings of
equal length.
dst <-- dst - src
Input
R15
address of destination BCD
string (in register memory).
R14 = address of source BCD
string (in register memory).
R12
BCD digit count I 2
Output
Destination BCD string contains the
difference.
Source BCD string may be modified.
R12, R14, R15 unmodified if no error
R13 modified.
Carry FLAG = 1 if underflow or format
error.
*n*******nn*unnn*****u*******u********u**************!
ENTRY
xor
!complement sign of
subtrahend!
!fall into bcdadd!
END
bcdsub
213
P 011A
P011AE6
P 011D D8
P011FC9
P 0121 04
P 0124 E5
P 0127 56
P 012A 24
P 012D 7D
P 0130 6B
P 0132 70
P 0134 C7
P 0137 76
P 013A 50
P 013C EB
P 013E BO
P 0140 D6
P 0143 21
P 0145 4D
P 0148 00
P 014A EB
P 014C D8
P 014E 00
P 0150 EB
7E 02
EE
7B
7B 7B
ED 7D
7D 7F
7D 7B
0203'
1A
EC
CD 01
EC FO
EC
DE
7C
0463 '
ED
0203'
7B
E6
EF
7E
CD
P
P
P
P
P
P
P
P
0152
0154
0157
015A
015D
0160
0162
0164
E3·
56
E5
56
A4
70
7B
BB
DF
ED
EE
7D
7D
ED
39
18
P
.P
P
P
P
P
P
0166
0168
016A
016C
016E
0170
0173
D8
E9
F9
20
20
E5
A5
EC
7C
7B
7C
7B
7C
7B
214
7F
7D
7F
ED
7E
7E
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
7111
715
716
GLOBAL
bcdadd
PROCEDURE
1****************··*···**·*·······**··*·*······.····*·
Purpose =
To add two packed BCD strings of
equal length.
dst <-- dst + src
Input
R15
address of destination BCD
string (in register memory).
R111
address of source BCD
string (in register memory).
R12 = BCD digit count / 2
Output
Destination BCD string contains the sum.
Source BCD string may be modified.
R12, R111, R15 unmodified if no error
R13 modified.
Carry FLAG = 1 if overflow or format
error .
•• ** •••••••• ** •••• *.* •••••••••••••••••••••••••••••• *.!
ENTRY
!delete all leading pre-decimal zeroes!
Id
TEMP 3,#2
Id
R13,~cd SRC
Id
TEMP II,Dcd LEN
add
TEMP-II,TEMP II
!total digit count!
!ge~ sign/post dec #!
Id
TEMP-2,@R13and
TEMP-2,#%7F
!isolate post dec #!
sub
TEMP-4,TEMP 2
!pre-dec digit cnt!
jp
ult,oa err ! format error!
jr
z,ba 1Ino pre-dec. digits!
push
R12 ba 2:
! save!
!leading byte!
Id
R12,1(R13)
!test leading digit!
tm
R12,II%FO
Irestore!
pop
R12
jr
nz,ba 1
Ino more leading O's!
clr
TEMP T
!rotate left!
call
rdl
!update post dec #1
inc
@R13
loops!
jp
ov,ba err
!dec pre-dec II!
dec
TEMP li
! loop!
jr
nz,ba 2
Id
R13,bcd DST
ba 1:
dec
TEMP 3 !SRC and DST done?!
jr
nz,ba 3
!do DST!
!leading zero deletion complete!
!insure DST is > or = SRCj exchange if necessary!
Id
R13,@bcd DST
!isolate post dec #!
and
R13,11%7FId
TEMP 2,@bcd SRC
!isolate post dec #!
and
TEMP-2,#%7Fcp
H13,TEMP 2
push
R13
!save!
jr
ult,ba II
!DST > SHC!
jr
ugt,ba-5
!DST < SRC!
!decimal points in same position.
must compare magnitude!
Id
R13,bcd LEN
Id
TEMP 1,Dcd SHC
Id
TEMP-II,bcd-DST
inc
TEMP-1
inc
TEMP-II
Id
TEMP-3,@TEMP 1 !get SRC byte!
cp
TEM~3,@TEMP=1I !compare DST byte!
P
P
P
P
0176
0178
017A
017C
BB
7B
OA
8B
06
23
FO
1F
P
P
P
P
P
P
P
P
P
P
P
P
P
P
017E
0180
0181
0183
0185
0187
0189
018C
018F
0192
0195
0197
0199
019B
08
OE
02
02
00
00
E5
E5
F5
F5
OA
08
50
70
EC
EO
FO
EE
EF
EE
EF
7B
7C
EE
70
70
EO
P 0190 50
EO
P 019F 24
P 01A2 CO
P 01A4 FB
EO
70
09
P
P
P
P
EE
EO
7C
0485'
01A6
01A8
01AA
01AC
08
01
BO
06
P OlAF E5
P 01B2 B5
EE
EF
P
P
P
P
P
01B5
01B7
01BA
01BC
01BE
08
24
6B
02
02
EC
70
45
EO
FC
P
P
P
P
P
P
P
P
P
P
P
P
01CO
01Cl
01C4
01C7
01C9
01CC
01CE
0101
0103
0106
0108
010A
CF
E5
76
6B
35
BB
15
40
F5
00
00
OA
EF
7B
05
EE
03
EE
7C
7C
EF
EE,
E5
P
P
P
P
P
P
P
P
010C
010E
010F
01El
01E3
01E6
01E8
OlEA
08
OE
OA
8B
17
41
00
OA
7C
7B
EE
EF
70
7B
7B
EO
7C
80
7C
7C
EF
70
02
09
EF
EF
EF
F7
00
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
!SRC > OST!
jr
ugt,ba 5
jr
ult,ba-4
!SRC < OSTI
!loopl
djnz
R13,ba-6
jr
ba 4 lOST > or = SRCI
Iswap source and destination operandsl
ba_5:
ld
R13,bcd LEN
!include flag/size by tel
inc
R13
add
bcd SRC,R13
add
bcd-OST,R13
ba_7:
dec
bcd-SRC
dec
bcd-OST
ld
TEMP 1,@bcd SRC
ld
TEMP-4,@bcd-OST
ld
@bcd-SRC,TEMP 4
ld
@bcd-OST,TEMP-l lone byte swapped!
djnz
R13,oa 7
ld
R13,TENP 2
pop
TEMP 2 R13 push
!exchange complete I
ba 4:
pop
R13
!restorel
IR13 = OST post decimal digit count
TEMP 2 = SRC post decimal digit count
R13 ~< TEMP 2
sub TEMP 2,R13
TEMP-2
rrc
!alignment offset I
!digits word aligned!
nc,ba 8
jr
!rotate out least significant SRC post decimal digitI
R13,bcd SRC
ld
@R13
dec
!dec post dec digit #1
TEMP 1
clr
call
rdr
!determine if addition or subtraction!
TEMP 4,@bcd SRC !sign of SRCI
ba_8:
ld
TEMP-4,@bcd-OST !sign of OSTI
xor
!get starting addresses!
R13,bcd LEN
ld
sub
R13,TEMP 2
z,ba 14 !done already I
jr
add
bcd SRC,R13
bcd:OST,bcd_LEN
add
!ready! I!
!carry = O!
rcf
ba 11: ld
TEMP 1,@bcd OST
tm
TEMP-4,#~80ladd or sub?!
!addl
jr
z,ba-9
sbc
TEMP-l,@bcd SRC
jr
ba 10
adc
TEMP 1,@bcd SRC
ba 9:
ba-l0: da
TEMP-l
ld
@bcd-OST,TEMP 1
dec
bcd UST
dec
bcd-SRC
djnz
R13-;Da 11
Ipropagate carry thru ~EMP 2 bytes of OSTI
ld
R13, TEMP 2inc
R13
!may be zero!
djnz
R13,ba 12
jr
ba 13 @bcd OST,#O
ba 12: adc
da
@bcd-OST
dec
bcd UST
djnz
R13~ba_12
215
P 01EC FB
13
P
P
P
P
P
P
P
P
P
EF 7C
7C 7F
0203'
7C 10
EF
0485'
EF
01EE
01F1
01F4
01F7
01FA
01FC
01FF
0201
0202
E5
56
60
E6
08
06
01
CF
AF
P 0203 OF
P 0204 AF
P 0205
216
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
Icarry propagate completel
ba 13: jr
nc,ba 14
Idonel
IRotate out least significant post decimal OST
digit to make room for carry at high endl
TEMP_1,@bcd_OST
ld
TEMP 1, 11'f,7F
and
z,ba-err
Ino post dec digit~i
jp
ld
TEMP1,11$10
R13,Dcd OST
ld
rdr
call
Idec digit cntl
@bcd_OST
dec
ba 14: rcf
ret
ba err: scf
ret
bcdadd
END
ConverSl.on Routl.nes
P0205
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0205
0208
020B
020D
0210
0213
0216
0218
021A
021D
021F
0221
0224
0226
D229
022B
022E
0230
0231
0234
0236
0239
023C
023F
0241
0244
0247
0249
024B
024D
0250
0253
0255
0256
0257
E6
77
EB
E6
E5
56
02
70
24
50
7B
D6
7B
A6
6B
76
EB
DE
E5
FO
E4
56
A6
BB
06
D6
00
6B
CA
E6
D6
8B
DF
AF
7C 2D
ED 80
03
7C 2B
ED 7E
7E 7F
CC
EC
7E EC
7E
35
03F4 '
30
EC 00
22
7E 01
04
ED 7D
7D
7D 7C
7C OF
7C 09
14
7C 30
03F4 '
7E
OB
DE
7C 2E
03F4'
D6
P 0257
P 0257 D6
P 025A C8
P 025C
025C'
ED
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
CONSTANT
R12
bca LEN
bca-SRC
R13
GLOBAL
bcddasc PROCEDURE
!UUnaUDUUUftUUauuunuunnuuuuuu*.aauuu*.u*uuuuuauuuuuuuuu
Purpose
To convert a variable length BCD
string to decimal ASCII.
Input
RR14 = address of destination ASCII
string (in reg/ext/ser memory).
R13
address of source BCD
string (in register memory).
R12
BCD digit count / 2
Output
ASCII string in designated
destination buffer.
Carry FLAG = 1 if input format error
or serial disabled,
= 0 if no error.
R12, R13, R14, R15 modified.
Input BCD string ummodified.
uuuuanuuuufuuu*unuuu*uHUUuuDuuunnuuu*uuu*u*uuu*uuuUUU!
ENTRY
!minus" sign!
ld
TEMP 1,1/'-'
!src negative?!
@bca-SRC,II%80
tm
jr
ryes!
nz,bed d1
Ipositive sign!
ld
TEMP 1-;-11' +'
TEMP-3,@bca SRC
bcd d1: ld
TEMP-3,1I%7Flisolate post dec cnt!
and
bca LEN, bca LEN !total digit count!
add
bca-LEN
push
bca -LEN, TEMP 3 !pre-dec digit cnt!
sub
TEMP 3
!total digit count!
pop
jr
! format error!
ul t, bcd d2
!sign to dest.!
put dest"
call
jr
c,bed d2
!serial errorl
!any pre-dec digits?!
cp
bca LEN,IIO
jr
z,bed d6
!no. start with '.'!
Ineed next byte?1
bcd d4: tm
TEMP 3,1/1
jr
nz,bcd d3
! not yet.!
! update pointer!
bca SRt"
inc
ld
TEMP 2,@bca SRC !get next byte!
TEMP-2
bcd_d3: swap
TEMP-1,TEMP 2
ld
TEMP-l ,II%OF!isolate digit!
and
TEMP-l,119
cp
Iverify bcd!
Ino good!
jr
ugt,bcd d5
add
TEMP 1,1%30
!convert to ASCII!
put
(fest
Ito
destination!
call
dec
TEMP 3
!digit count!
!all donel
z, bed d2
jr
djnz
bca LEN, bed d4 Inext digitI
!time for dec. pt.!
bcd d6: ld
TEMP 1, II ' • '
call
put (fest
Ito destination!
bcd-d4
!continue!
jr
bcd d5: scf
!set error return!
bcd-d2: ret
ENDbcddasc
GLOBAL
wrdhasc PROCEDURE
!*nuuu*uu***uun*u*uuDuu*D*unn*uuuuftUUuu*uu*uu**nuuuuuu
Purpose =
To convert a binary word to Hex ASCII.
Input =
RR12 = source binary word.
RR14 = address of destination ASCII
string (in reg/ext/ser memory).
All other details same as for bythasc.
Note =
**u***.*u*.*uuuu* •• UUU***H**_***uuu*uuu.* ••••• I·*···*1
ENTRY
!convert R121
call
bythasc
ld
R12,R13
!fall into bythascl
END
wrdhasc
217
P 025C
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
025C
025E
0261
0263
0265
0268
026B
026E
0270
0271
02711
0276
0279
027C
027E
0280
0282
0283
02811
218
BO
E6
FO
C9
56
06
A6
7B
OF
76
EB
06
06
7B
00
EB
CF
AF
7E
70
EC
7C
7C
7C
7C
09
02
OF
30
3A
7E 01
00
7C 07
03FII'
05
70
OF
898
899
.goo
901
902
903
9011
905
906
907
908
909
910
911
912
913
9111
915
916
917
918
919
920
921
922
923
9211
925
926
927
928
929
930
931
932
933
CONSTANT
bna SRC
GLOBAL
bythasc PROCEDURE
.
R12
! •••••••••••••••••••••••••••••••••••••••••••••••••••••
Purpose
To convert a binary byte to Hex ASCII.
Input =
RR111 = address of destination ASCII
string (in reg/ext/ser memory).
R12 = Source binary byte.
Output
ASCII string in designated
destination buffer.
Carry = 1 if error (serial only).
R111, R15 modified.
••••••••••••••••••••••••••••••••••••••••••••••••••••• !
ENTRY
clr
MODE
!flag => binary to ASCII!
TEMP 2,112
bca go: ld
bca:go 1: SWAP - bna SRC
!look at next nibble!
TEMP' 1,bna SRC
ld
TEMP-1 ,II%OF
!isolate low nibble!
and
!convert to ASCII!
ADD
TEMP-1 ,11%30
cp
TEMP-1,II%3A
!>9?!
!no!
ult ,skip
jr
SCF
lin case error!
!inpiJt is BCD?!
TM
MODE,111
JR
NZ,bca ex
! yes. error.!
!input hex. adjust!
ADD
TEMP 1-;11%07
skip:
call
put dest
!put byte in dest!
jr
c,bca ex
terror!
dec
TEMP '2
!loop till done!
jr
nz,bca_g01
RCF
!carry = 0: no error!
!done!
bca ex: ret
ENDbythasc
P 0284
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0284
0286
0288
028B
028E
0290
0293
0295
0298
029B
029C
029F
02A2
02A4
02A6
02A9
02AC
02AE
02BO
02B2
02B4
02B6
02B7
02BA
02BC
02BF
02C 1
02C3
02C5
02C8
02CB
02CC
02CD
BO
BO
E5
56
02
24
7B
E5
E6
EE
E5
A6
6B
FO
E4
D6
7B
00
00
EB
8B
DF
76
EB
76
6B
60
60
06
16
CF
AF
EC
ED
EE
7B
FF
7B
37
EE
7E
7B
7F
EF
7B
02
7D
EF 00
12
7D
7D 7C
042C'
1E
EF
7E
EB
E2
EE
EC
10
7B
OA
EC
ED
ED
EC
80
80
01
00
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
CONSTANT
bcd adr
bcd-cnt
GLOBAL
b'cdwrd PROCEDURE
R14
R15
! •••••••••••••••••••••••••••••••••••••••••••••••••••••
Purpose
=
.
Input
To convert a variable length BCD
string to a signed binary word. Only
pre-decimal digits are converted.
R14
R15
Output
=
address of source BCD
string (in register m~mory).
BCD digit count / 2
RR12 = binary word
Carry FLAG = 1 if input format error
or dest overflow,
= 0 if no error.
R14,R15 modified •
•••••••••••••••••••••••••••••• ** ••••••••••••••••••••• !
ENTRY
clr
clr
ld
and
add
sub
jr
ld
ld
inc
ld
bcd w1: cp
jr
swap
ld
call
jr
dec
dec
jr
jr
bcd,-w4: scf
tm
jr
bcd_w5: tm
jr
com
com
add
adc
bcd w6: rcf
bcd-w2: ret
ENDbcdwrd
R12
R13
TEMP 4,@bcd adr
TEMP-4,1I'/.7Fbcd ent,bcd cnt
bcd-cnt,TEMP 4
ult-;bcd w2 TEMP 4,lbcd adr
TEMP-3,112 bcd adr
TEMP 2,@bcd adr
bcd ent,IIO z,bcd w4
TEMP '2"
TEMP-1, TEMP 2
bcd Din
c ,bed w2
bcd cot
TEMP 3
nz,bcd w1
bcd_W3H12,11'/.80
nz,bcd w2
TEMP 4-;11'/.80
z, bca w6
R12 R13
R13,1I1
R12,110
!init destination 1
Iget sign/post length!
!isolate post Tength!
!II bcd digitsl
!II pre-dec digits!
! format error!
!remember sign!
!digits per byte!
!src address!
!get next src byte!
!digit count = O?!
Iconversion complete!
!next digit!
laccumulate in binaryl
!overflow or format err!
lupdate digit count!
!nextbyte?!
!no. same.!
!next byte!
! in case!
!result > 15 bits?!
!overflow!
!spurce negative?!
!no. done.!
!RR12 two's complement!
!carry = 01
219
P 02CD
990 GLOBAL
991 wrdbcd PROCEDURE
992 ! ••••• ** ••••••••••••••••• *** ••••••••• *** •••• ** ••••••••
To convert a signed binary word
993 ' Purpose
to a variable length BCD string.
9911
995
R111 = address of destination BCD
996 Input =
string (in register memory)
997
RR12 = source binary word
998
R15 = BCD digit count / 2
999
1000
BCD string in destination buffer
1001 Output =
Carry FLAG = 1 if dest overflow
1002
= 0 if no error.
1003
R12,R13,R111,R15 modified.
10011
1005
1006 ENTRY
clr
@bcd adr
linit sign/post dec cntl
1007
lis input word nega~ive?
tm
R12,n80
1008'
jr
z,wrd bO
1009
Iset result negativel
or
@bcd_adr
,11%80
1010
1011
com
R13
com
R12
1012
add
1013
R13,111
IRR12 two's complement I
R12,110
10111
adc
1015 wrd bO: rlc
R13
Ibit 15 not magnitude!
R12
1016
rlc
inc
bcd adr
lupdate dest pointer!
1017
TEMtr_1, bcd_adr
ld
1018
ld
TEMP 2,bcd cnt Idest byte countl
1019
add
TEMP:1 ,bcd:cnt
1020
1021
dec
TEMP 1
1= bcd end addrl
@bcd-adr
!initialize destl
1022 wrd b1: clr
inc
bcd adr
1023
djnz
bcd:cnt,wrd_b1
10211
ld
!source bit count!
1025
TEMP 3,1115
1026 wrd_b3: push
TEMP:3
1'lc
1027
R13
Ibit 15 to carry!
R12
rlc
1028
!start at endl
ld
bcd adr,TEMP
1029
ld
bcd-cnt,TEMP-2
!dest
byte count I
1030
1031 !(dest bcd string) <-- (dest-bcd string. 2) + carry!
TEMP_3 ,@bcd_adr
1032 wrd b2: ld
adc
TEMP 3,@bcd adr !. 2 + carry!
1033
TEMP-3
da
1034
@bcd-adr,TEMP 3
ld
1035
bcd adr
- Inext two digits!
, dec
1036
,djnz
bcd-cnt,wrd b2 Iloop for all digits I
1037
Irestore src bit cntl
pop
TEMP 3
1038
jr
!dest. overflowl
c,wrd ex
1039
dec
TEMP '3"
1040
1041
jr
!next bitl
nz,wrd_b3
1042 wrd ex: ret
10113 ENDwrdbcd
·····················································1
02CD
02CF
02D2
02DII
02D7
02D9
02DB
02DE
02E1
02E3
02E5
02E6
02E8
02EA
02ED
02EF
02F 1
02F2
02FII
02F7
02F9
02FB
02FD
02FF
B1
76
6B
117
60
60
06
16
10
10
EE
E9
F9
011
00
B1
EE
FA
E6
70
10
10
E8
F8
0301
03011
0307
0309
030C
030E
0310
0312
0314
p 0316
P 0318
P 0319
E5
15
40
F5
00
FA
50
7B
00
EB
AF
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
220
EE
EC
OD
EE
ED
EC
ED
EC
ED
EC
7C
7D
EF
7C
EE
FB
7E
7E
ED
EC
7C
7D
EE
EE
7E
7E
EE
F1
7E
04
7E
DF
80
80
01
00
7C
OF
7E
7E
EE
P 0319
P
P
P
P
P
P
P
P
P
P
0319
031B
031D
031F
0322
0324
0327
0329
032C
032E
BO
BO
BO
D6
7B
D6
7B
A6
3B
26
7E
EC
ED
03DA'
28
040D'
22
7C 39
03
7C 37
P
P
P
P
P
P
P
P
0331
0333
0335
0338
033B
033E
0340
0343
0346
0349
034B
034C
034D
FO
D9
56
56
44
FO
56
56
44
8B
CF
AF
ED
7D
ED
7C
7C
EC
EC
7D
7D
D4
p
P
P
P
P
FO
OF
ED
FO
OF
EC
1045
1046
1047
1048
10 119
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066'
1067
1068
1069
1070
1071
'.1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
GLOBAL
hascwrd PROCEDURE
!****I*.**********************.*.**.**o****** ••• ******
Purpose
To convert a variable length Hex
ASCII string to binary.
Input =
RR14
Output
RR12 = binary word (any overflow
high order digits are truncated
without error).
Carry FLAG = 1 if input error
(serial only)
(SER fIg indicates cause)
=-0 if no error
R14, R15 modified
addres& of source ASCII
string (in reg/ext/ser memory) .
Note =
The ASCII input string processing is
terminated with the occurrence of a
non-hex ASCII character.
**************************************I**************!
ENTRY
clr
TEMP_3
clr
R12
linit output!
clr
R13
has c,l: call
get src
!get input!
jr
c ,has_ex 1
terror!
call
ver asc
!verify hex ASCII!
lend conversion!
jr
c,has ex
cp
TEMP",II%39
ule,nas_c2
jr
sub
TEMP 1,11%37
! Shift left one nibbTe!
! In sert new nibble in least significant nibble!
has c2: swap
R13
ld
TEMP 2,R13
and
R13,7J%FO
and
TEMP 1, II'J,OF
R13,'l'EMP_l
or
swap
R12
and
R12, II%FO
and
TEMP 2, II%OF
R12,TEMP_2
or
jr
has cl
!loop!
Ino el'ror!
has ex: rcf
has-exl :ret
ENDhascwrd
221
P 0340
0340
034F
0351
0354
0357
0359
035B
P 035E
P 0360
P 0363
P
P
P
P
P
P
P
222
CC
DC
04
06
7B
EC
04
FC
80
03
08
FD ED
0363'
F3
08
FD EE
03
0284'
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
GLOBAL
dascwrd PROCEDURE
!***********.*.******* •• ***.,.* •••• *******,.** •• ******
Purpose
To convert a variable length decimal
ASCII string to signed binary.
Input =
RR14 = address of source ASCII
string (in reg/ext/ser memory).
Output
RR12 = binary word
R8,R9,R10,R11 holds the packed BCD
version of the result.
Carry FLAG = 1 if input error
(serial only)
(SER flg indicates cause)
or dest overflow
= 0 if no error
R14, R15 modified
Note
The ASCII input string processing is
terminated with tlie occurrence of a
non-decimal ASCII character.
Decimal ASCII string may be no more
than 6 digits in length, else Carry
will be returned.
Post decimal digits are not included
in the binary result.
••• * ••• * •••••••••••• *** •••••••••••••••••••••••••••••• !
ENTRY
END
ld
ld
add
call
jr
ld
add
ld
jp
dascwrd
R12,113
R13,118
R13, RP
dascbcd
c,has ex1
R14, II'S"
R14,RP
R15,113
bcdwrd
!6 digitsl
Itemp addr =!
! R8 thru R11!
!convert to bcd!
!errorl
Iconvert to binary!
P 0363
P
P
P
P
P
P
P
P
P
P
0363
0365
0367
0369
036A
036C
036E
0370
0372
0375
70
70
B1
DE
CA
B1
50
50
E6
BO
FB
ED
ED
EC
7E
7B
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0377
037A
037C
037F
0382
0384
0387
0389
038C
038E
0391
0393
0395
0398
039A
039D
039F
03A2
03A4
03A7
03AA
03AC
03AF
D6
7B
56
76
EB
A6
6B
A6
EB
B7
8B
5B
A6
EB
46
8B
D6
7B
46
D6
EB
76
6B
03DA'
41
7C 7F
7B 03
OF
7C 2B
EE
7C 2D
07
ED 80
E4
OA
7C 2E
05
7B 03
D8
040D'
16
7B 01
0463'
09
7B 02
C6
EC
ED
ED
01
1134 CONSTANT
R12
1135 dab LEN
1136 dab-DST
R13
1137 GLOBAL
1138 dascbcd PROCEDURE
1139 !UUUU*UfUUUUUUHUUUUUUUUUUUUHU****URUU*****************
1140 Purpose
To convert a variable length decimal
1141
ASCII string to BCD.
1142
1143 Input =
R13 = address of destination BCD
1144
string (in register memory).
1145
RR14 = address of source ASCII
1146
string (in reg/ext/ser memory).
1147
R12 = BCD digit count I 2
1148
1149 Output
BCD string in designated destination
1150
buffer (any overflow high order
1151
digits are truncated without error).
1152
Carry FLAG = 1 if input error
1153
(serial only)
1154
(SER fIg indicates cause)
1155
or overflow
1156
R14, R15 modified.
1157
1158 Note =
The ASCII input string processing is
1159
terminated with the occurrence of a
1160
non-decimal ASCII character.
1161 uuuuuuuo*uuuu*uuounuuDuuuuuuauuauunu******DDHDU**D*UO!
1162 ENTRY
1163
.push
dab LEN
! save!
dab-DST
1164
push
1165 das_g1: clr
@dab DST
!init. destination!
1166
inc
dab nST
1167
djnz
dab-LEN,das g1
1168
@dao DST
clr
! init.!
1169
pop
dab OST
!restore!
pop
1170
dab-LEN
1171
ld
TEMP 3,111
! for ver asc!
1172
TEMP-4
clr
!bit 0 => digit seen;
1173
bit 1 => dec pt seen;
1174
bit 7 => overflow!
1175 das_g2: call
get src
!get input byte!
jr
1176
c,dab ex1
!serial error!
and
1177
TEMP 1", 11%7F
!7-bit ASCII!
tm
1178
TEMP-4 ,11%03
'check status!
jr
1179
nz,das g5
sign char not valid!
1180
cp
TEMP 1~/1'+'
positive?!
1181
jr
z,das g2
yes. no affect!
cp
1182
TEMP 1,11'-'
negative? !
1183
jr
nz,das g4
not sign chari
1184
xor
@dab D"ST,II%80
complement sign!
1185
jr
das &2
get next input!
1186 das g5: jr
mi ,das g6
dec pt has been seen!
1187 das=g4: cp
TEMP 1~UI.1
is char dec pt?!
jr
1188
nz,das g6
nope .!
or
1189
TEMP 4~11%03
dec pt and digit seen!
1190
jr
das3"2
get next input!
1191
call
ver asc
is bcd digit?!
jr
c,dab ex
1192
lend conversion.!
1193
or
TEMP 4,11%01
!digit seen!
rdl 1194
call
!new digit to dest!
1195
jr
nz,das g7
!overflow!
1196
tm
TEMP 4~1I%02
!post dec digit?!
1197
jr
z,das_g2
!no. get next input!
223
P
P
P
P
21
8B
46
8B
ED
C2
7B
BD
80
P 03BA E4
P 03BD AF
P 03BE
7B
FC
03B1
03B3
03B5
03B8
P 03BE
P
P
P
P
P
P
P
P
P
P
P
P
P
03BE
03CO
03C2
03C4
03C7
03C9
03CC
03CE
03DO
03D2
03D4
03D7
03DA
224
70
70
EC
04
FC
06
50
50
CC
DC
04
8D
EE
EF
08
FD EE
03
02CD'
EF
EE
03
08
FD ED
0205'
1198
1199
1200
1201
1202
1203
1204
1205
inc
jr
das_g7: or
jr
@dab DST
das g2
TEMP 4,0%80
das_g2
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
GLOBAL
wrddasc PROCEDURE
dab ex: ld
FLAGS,TEMP_4
dab-ex1: ret
ENDdascbcd
1••••••••••• 11 •••
Purpose
=
Iinc
!get
!set
!get
post dec cnt!
next input!
overflow!
next input!
!carry
=0
or 1!
** •••••••••••••••••••••••••••••••••••
To convert a signed binary word to
decimal ASCII
Input
RR12
RR14
source binary word.
of dest (in reg/ext/ser
memory).
Output
Decimal ASCII in dest buffer.
R8,R9,R10,R11 holds the packed BCD
version of the result.
R12, R13, R14, R15 modified.
= address
·····················································1
ENTRY
END
push
push
ld
add
ld
call
pop
pop
ld
ld
add
jp
wrddasc
R14
R15
R14,118
R14,RP
R15,113
wrdbcd
R15
R14
R12,113
R13,118
R13,RP
bcddasc
!save dest addr!
IR8,9,10 & 11 tempI
Itemp byte length I
Iconvert input word!
Irestore dest addr!
Ilength of temp!
laddr of tempI
Iconvert to ASCII I
P 03DA
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
03DA
03DB
03DC
03DE
03DF
03E1
03E4
03E6
03E8
03EA
03EC
03EE
03EF
03F2
03F3
03F4
CF
EE
EA
FE
FA
8D
70
82
B9
50
AO
AF
E5
FE
AF
06
OE
OOOOu
EB
BE
7C
EB,
EE
EF
7C
P 03F4
P 03F4
P 03F5
P 03F7
P 03F8
P 03FA
P 03FD
P 03FF
P 0401
P 0403
P 0405
P 0407
P 0408
P 040B
P040C
P 040D
EE
EA
FE
FA
8D
70
B8
92
50
AO
AF
F5
FE
AF
06
OE
0000·
EB
7C
BE
EB
EE
7C
EF
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
GLOBAL
!for PART II only!
get src PROCEDURE
!~*vu************v*a******
••• *****u****.*.u* •• ****.***
Purpose
To get source byte from
reg/ext/ser memory into TEMP_1.
Output
Carry FLAG = 1 if
=
e~ror
(serial)
0 i f all ok
TEMP 1 = source byte.
RR 14-updated.
uUUUUUUIUUUUUuu*uu*nnuuunuluu*.U*.*uuu*u**u***.***.**!
ENTRY
!set good return code!
rcf
!test R14 = O!
R14
inc
djnz
!src in ext memory!
R14,get s1
R15
!test R15 = O!
inc
!src in reg memory!
djnz
R15,get 52
!src in ser memory!
ser getjp
R11push
!save user's!
!get byte!
R11,@RR14
Ide
Imove to common!
ld
TEMP 1,R11
R11 !restore pser'sl
pop
! update src ptr!
incw
RR14
ret
!get byte!
get_52: ld
TEMP 1,@R15
R15 !update src ptr!
inc
ret
get_src
END
GLOBAL
!for PART II only!
put dest
PROCEDURE
t**T** •• fuuun*n*uuuuuiI*uuuuu* •• *u*****.**u**** •• ****nu
·Purpose =
To store destination byt~ from TEMP 1
into reg/ext/ser memory
Output =
RR14 updated.
UUU***UUilnnu*uunuuu*nnuuanauuuanUUilnuuuunuuu*u***uuu*t
ENTRY
.
inc
R14
Itest R14 = O!
!dest in ext memory!
R14,put 51
djnz
R15
inc
!test R15 = O!
!dest in reg memoryl
djnz
R15,put s2
Idest in ser memory!
jp
ser output
R11!save user's!
push
R11, TEMP 1
ld
@RR14,R1T
Ide
pop
!restore user's!
R11
RR14
incw
ret
@R15,TEMP
put_52: ld
R15
inc
ret
END
put_dest
225
P 040D
P
P
P
P
P
P
P
P
P
P
P
040D
0410
0413
0415
0418
041A
041D
041F
0422
0425
0427
56
A6
7B
A6
7B
76
EB
56
A6
7B
A6
7C
7C
16
7C
10
7E
OB
7C
7C
04
7C
7F
30
3A
01
DF
41
47
P 042A EF
P 042B AF
P 042C
P 042C
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
042C
042F
0432
0434
0436
0438
043A
043C
043E
0440
0442
0444
0446
0448
044A
044D
0450
0452
0454
0457
0459
045C
56
A6
BB
02
12
7B
70
70
02
12
7B
02
12
7B
04
16
7B
50
04
50
14
AF
7C
7C
2D
DD
CC
27
EC
ED
DD
CC
19
DD
CC
13
7C
EC
OB
7C
7C
7C
7C
P 045D
P 04'5F
P 0461
P 0462
P 0463
50
50
DF
AF
7C
7C
226
OF
09
ED
00
ED
EC
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
CONSTANT
MODE
char
INTERNAL
ver asc PROCEDURE
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
INTERNAL
bcd bin PROCEDURE
TEMP 3
TEMP-1
I··T ••••••• ** ••• *•• *, •••••••••••• *** •••••• **.*.* ••••••
Purpose
To verify input character as valid
hex or decimal ASCII.
'TEMP 1
TEMP=3
Input
Output =
8-bit input
= 0 => test for hex,
1 => test for decimal
Carry FLAG
=0
if no error
1 if error.
**** •• *.*.* •• *'*'*.**'* •••••• *.*.' ••• '.*.'** ••• ' •• '.'!
ENTRY
and
ep
jr
ep
jr
tm
jr
and
cp
jr
ep
ver ok:
ver ere: eef
ver-err: ret
ENDver ase
char,U%7F
17-bit ASCII!
char,II'O'
!range start: 'O'!
ult,ver err
!no good!
char,H'9'+1
Idee range end: '9'!
ult,ver ok
fall's weIll
MODE,H1!dec or hex?!
nz,ver ere
!no goodl
char,IILNOT('a'-'A') !insure upper case!
char,H'A'
Icheck A-F range I
ult,ver err
Ino good!
ehar,U'F'+1
lend hex range!
Icomplement carry!
!**T.* •• *.*** ••••••••••• *.** ••••••••••• *••••• *•••• ** ••
Purpose
To convert next bed digit to binary.
Input =
TEMP_1 = digit
Output
=
RR12
= RR12
and
ep
TEMP 1, H%OF
TEMP-1,119
ugt,bcd b1
R13,R13R12,R12
e,bed b1
R12 R13
R13, R13
R12,R12
e,bed b2
R13,RT3
R12, R12
e,bed b2
R13, TEMP
R12,110 e,bed b2
TEMP T
R13,TEMP
TEMP 1 R12,TEMP_1
• 10 + digit
••••••••••••••••••••••••••• *.** •••••••••••••••••• ***.!
ENTRY
jr
add
ade
jr
push
push
add
ade
jr
add
ade
jr
add
ade
jr
pop
add
pop
ade
ret
bed b2: pop
TEMP 1
TEMP-1
pop
bed b1: sef
ret
END
bed bin
!isolate digitI
!verify validl
terror!
12x!
! overflow!
!4xl
!overflow!
!8x!
! overflow!
!8x + dl
!overflowl
! 10x + d!
!restore stack!
terror!
P 0463
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0463
01165
0467
0469
046C
046F
0472
0475
0478
047B
047D
047F
0482
0484
0485
70
02
Fl
E5
57
56
45
F5
E4
00
CA
56
50
AF
EC
DC
ED
ED
ED
7C
ED
7C
7D
ED
E8
7C
EC
7D
FO
OF
7C
ED
7C
OF
P 0485
P
P
P
P
P
P
P
P
P
P
P
P
P
0485
0487
0488
048A
048D
0490
0493
0496
0499
049C
049E
04AO
04A1
70
DE
Fl
E5
57
56
45
F5
E4
CA
50
AF
EC
ED
ED
ED
7C
ED
7C
7E
E9
EC
7E
OF
FO
7C
ED
7C
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
141.0
141.1
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
CONSTANT
R12
s len
s-adr
R13
INTERNAL
rdl
PROCEDURE
!v.*u***un.*.***ua.**a.*uuuau**.*au*uu*.u**.uu*uauaa**
Rotate Digit Left
.
.
Input
=
R12 = BCD string length
R13 = BCD string address
TEMP 1 bit 3-0 = new digit
Output
BCD string rotated left one digiti '
new digit inserted in units positlon.
TEMP 1 bit 3-0 = digit rotated out
of high order digit position
bit 7-4 = 0
Zero FLAG = 1 if TEMP_l <>0
R12, R13 unmodified
**.*.uu*u* ••• *u •• uI.*.ufuau*unuueuuuu*u*u*.* •••• e •• u*1
ENTRY
s len
push
s-adr,s len
add
!address of units place!
@s adr rdl 01: swap
Id
TEMP 2,@s adr
! isolate digiti
@s adr,n:F'O
and
and
!isolate new digit!
TEMP 1, 1110 OF
TEMP-l,@s adr
or
Id
@s adr, TEMP 1
! save new byte I
TERp_1 , TEMP:2
Id
!back-up pointer!
dec
s adr
s-len,rdl 01
djnz
Iloop till donel
and
TEMP 1,1/100F
told high order digitI
Irestore R12!
pop
s len
ret
rdl
END
INTERNAL
rdr
PROCEDURE
!***************u***************************.***e.****
Rotate Digit Right
Input
=
R12 = BCD string length
R13 = BCD string address
TEMP_l bit 7-4 = new digit
Output
BCD string rotated right one digit;
new digit inserted in high order
position.
R12 unmodified
R13 modified
fuuunuuuunuu*.*uu*uuuu**uuuuuuuuuuuuu**uuunnnuuuuuuu*1
ENTRY
push
s len
s-adr
rdr 01: inc
swap
@s adr
Id
TEMP 3,@s adr
!isolate d igi t!
and
@s adr,11100F
and
TEMP 1,111oFO
!isolate new digit!
or
TEMP:1,@s_adr
Id
@s adr,TEMP 1
! save new byte!
TEMP_ 1 , TEMP:3
Id
djnz
s len,rdr 01
!loop till done I
s-len
pop
!restore R12!
ret
rdr
END
227
B~t
Manipulation Routines
P 04A 1
P
P
P
P
P
P
P
P
04Al
04A4
04A6
QUA8
04AA
04AC
04AE
04BO
P
P
P
P
P
04B2
04B4
04B6
04B8
04B9
228
E6
BO
go
90
FB
EO
90
10
00
EB
C8
AF
7C
70
EC
ED
06
EC
EC
70
7C
FO
70
08
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1.486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
CONSTANT
tjm bits
tjm-mask
GLOBAL
clb
PROCEDURE·
R12
R13
!**.** •••• ****~.*** •• *.**.***** •••• *** ••• *•• **.***.***
Purpose
=
To collect selected bits in a byte
into adjacent bits in the low order
end of the byte. Upper bits in byte
are set to zero.
input byte
mask. Bit = 1 => corresponding
input bit is selected.
Input
R12
R13
Output
R12
Note =
For example:
Input; R12
R13
%(2)01110110
%(2)10000101
Output : R12
%(2)00000010
= collected
bits
***************************** ••• *********************!
ENTRY
ld
clr
next 1: rl
rl
jr
rr
rl
rIc
no select:
dec
jr
ld
ret
END
clb
TEMP 1,118
TEMP-2
tjm iii ts
tjm-mask
nc,no select
tjm bTts
tjm-bits
TEM1\" 2
TEMP 1
nz,nextl
R12,TEMP"':2
!bit count!
!bits collected here!
!bit 7 to bit 01
!bit7 to carry!
!don't use this bit!
!bit 7 to 0 and carry!
!collect source bit!
Irepeat!
P 04B9
P
P
P
P
P
P
P
P
P
04B9
04BC
OUBE
04C1
04C3
04C6
04Ce
04CA
04CC
D6
02
16
02
16
C2
AO
C2
E8
P 04CE 30
04A l'
CC
EE 00
FC
EE 00
DE
EE
FE
ED
EE
P 0400
1499 CONSTANT
R14
1500 tjm tabh
1501 tjm-tabl
R15
RR14
1502 tjm-tab
GLOBAL
1503
PROCEDURE
1504 tjrn
1505 !*****n**u********n****uun****u****unu*uu*************
To take a jump to a routine address
1506 Purpose =
determined by the state of selected
1507
bits in a source byte. A bit
1508
is 'selected' by a one in the
1509
corresponding
position of a mask.
1510
The 'selected' bits are packed into
1511
adjacent bits in the low order end of
1512
the byte. This value is then doubled,
1513
and used as an index into the jump
1514
table.
1515
1516
RR14 = address of jump table in
1517 Input
program memory.
1518
R12 = input data
1519
R13 = mask
1520
1521 *****************************************************1
1522 ENTRY
clb
!~ollect select~d bits!
call
1523
tjm bits,tjm bits !collected bits U 21'
add.
1524
tjm-tabh,#O lin case carry!
adc
1525
tjm-tabl,tjm bits
add
1526
tjm-tabh,#O !tjm tab points to .•• !
adc
1527
tjm-mask,@tjm tab !.~.table entry!
ldc
1528
tjm-tab
incw
1529
tjm-tabl,@tjm tab !get table entry ... !
ldc
1530
tjm=tabh,tjm_mask ! ..• into tjm_tab!'
ld
1531
1532,
jp
!byel
1533
1534
tjm
1535 END
1536 END PART I
o er!"ors
Assembly complete
229
ROMLESS Z8 SUBROUTINE LIBRARY
Z8ASM
LOC
3.02
OBJ CODE
P~RT
II
STMT SOURCE STATEMENT
1
2
3 PART II MODULE
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
20
21
!'ROMLESS Z8'
SUBROUTINE LIBRARY
PART II
CONSTANT
!Register Usage!
RAM START
%7F
P3M save
TEMP 3
TEMP-2
TEMP-1
TEMP-4
RAM START
P3M-save-1
TEMP" 3-1
TEMP-2-1
TEMP-1-1
:=
IThe following registers are modified/referenced
by the Serial Routines ONLY. They are
22 available as general registers to the user
23 who does not intend to make use of the
24 Serial Routines!
25
._
TEMP 4-1
26 SER char
._
SER char-1
27 SER tmp2
._
SER-tmp2-1
28 SER-tmp1
._
SER-tmp1-1
29 SER-put
._
SER-put-1
30 SER-len
._
SER-len-2
31 SER-buf
32 SER-imr
._
SER-buf-1
._
SER-imr-1
33 SER-c fg
34 ! Serial Configuration Data
=1 => odd parity on
35 bit 7
36 bit 6 : =1 => even parity on
6,7
= 11 => undefined)
37 (bi t
undefined
38 bit 5
undefined
39 bit 4
40 bit 3
=1 => input editting on
=1 => auto line feed enabled
41 bit 2
42 bit 1
=1 => BREAK detection enabled
43 bit 0
=1 => input echo on
44 I
45
46
47
48
49
50
51
52
53
54
55
56
55 7
8
59
60
61
62
63
64
65
66
67
68
69
230
op
ep
ie
al
be
ec
SER get
SER-flg
!Serial
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:=
%80
%40
%08
%04
%02
%01
Status Flags
=1 => serial I/O disabled
undefined
undefined
=1 => parity error
=1 => BREAK detected
=1 => input buffer overflow
=1 => input buffer not empty
=1 => input buffer full
I
sd
pe
bd
bo
bne
bf
SER cfg-1
SER:=get-1
=
=
=
%80
%10
%08
%04
%02
%01
70 RAM TMR
71
72 SERltime
SER flg-1
73 SERhtime
SERltime-1
:=
711
75 !The following registers are modified/referenced
76 by the Timer/Counter Routines ONLY. They are
77 available as general registers to the user
78 who does not intend to make use of the
79 Timer/Counter Routines!
80
. :=
81 TOD,tic
RAM TMR-2
82 TOD-imr
TOD-tic-1
:=
83 TOD-hr
TOD-imr-1
811 TOD-min
TODnr-1
:=
85 TOD-sec
TOD-min-1
86 TOD-tt
TOD-sec-1
87 PLS-1
TOD-tt-1
88 PLS-tmr
PLS-1-1
89 PLS-2
PLS=:tmr-1
90
91 RAM END
92 STACK
:=
93
911 IEquivalent working register equates
95 for above register layout!
96
97 Iregister file $70 - $7F!
98, RAM STARTr
' :=
$70
! for SRP!
99
100 rP3Msave
R15
101 rTEMP 3
R111
102 rTEMP-2
R13
:=
103 rTEMP-1
R12
1011 rrTEMP 1
RR12
:=
105 rTEMP 1h
R12
106 rTEMP-U
R13
:=
107 rTEMP-1I
R11
108 rSERcnar
R10
:=
109 rSERtmp2
:=
R9
110 rSERtmp 1
R8
111 rrSERtmp
RR8
:=
112 rSERtmpl
:=
R9
113 rSERtmph
R8
:=
,1111 rSERput
R7
:=
115 rSERlen
R6
116 rrSERbuf
RRII
117 rSERbufh
HII
:=
118 rSERbufl
R5
:=
119 rSERimr
R3
120 rSERcfg
R2
:=
121 rSERget
R1
:=
122 rSERflg
RO
:=
123
1211
, 125 Iregister file f60 - $6F!
T26 RAM TMRr
I for SRP!
$60
127 rTO'Utic
:=
R13
128 rTODimr
R12
:=
129 rTODhr
R 11
:=
130 rTODmln
R10
:=
131 rTODsec
R9
132 rTODtt
R8
133 rPLS 1
R7
1311 rPLStmr
R6
!=
135 rPLS_2
R5
231,
Serial Routines
P 0000
P
P
P
P
P
P
P
P
P
0000
0001
0003
0005
0007
0009
OOOB
0000
OOOF
232
EE
EA
EC
FC
BC
DC
C3
DA
56
04
00'
51'
72
05
BE
FC
73 F7
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
. 190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
2111
215
216
217
218
219
220
221
222
223
224
225
226
227
CONSTANT
si PTR
sCTMPl
sCTMP2
GLOBAL
ser init
RR14
R11
R13
=
=
=
PROCEDURE
I"~"""""""""""""""""""""""""
serial initialize
To initialize the serial channel and
Purpose =
RAM fl.ags for serial 1/0. Serial
input occurs under interrupt control.
Serial output occurs in a polled mode.
Input =
RR14
= address
byte
byte
word
byte
byte
byte
of parameter list in
program memory (if R14 = 0,
use defaults):
= Serial Configuration Data
(see definition of SER cfg)
= IMR mask for nestable
interrupts
= address of circular input
buffer (in reglext memory)
Length of input buffer
= Baud rate counter value
= Baud rate prescaler value
(unshifted)
Output =
Serial 1/0 operations initialized.
Rl1, R12, -R13, R14, R15 modified.
Note =
Defaults:
Input echo on
Input editting on
BREAK detection enabled
No parity
Auto line feed on
Input Buffer Address = SER char
Input buffer length = 1 byte
Baud Rate = 9600 (assuming
XTAL = 7.3728 MHz)
The instruction at ~0809 must result
in a jump to the jump table entry for
ser _input.
If BREAK detection is disabled, and a
BREAK occurs, it will be received as a
continuous string of null characters.
The parameter lis·t is not referenced
following initialization.
·····················································1
ENTRY
si_1:
si_2:
inc
djnz
ld
ld
ld
ld
ldci
djnz
and
R14
luse defaults?1
R14,si 1
Ino. given by caller.1
R14,OHI ser def laddress of default ••• 1
R15,DLO ser-def I ••• parameter list. I
si TMP1,OSER cfg
sCTMP2,05 - @S1 TMP1,@si PTR Iget initialization ••• 1
si TMP2,si 2I ••• parametersl
SER_imr,O~F7
linsure no self-nesting I
0012
0015
0017
001A
p 001D
P 0020
P 0023
56
B8
56
116
56
1111
Ell
F1
72
EB
EB
7F
EB
7F
P
P
P
P
P
P
P
P
P
P
P
0026
0028
002A
002C
002E
0031
0033
0035
0037
0038
003A
BC
C2
C3
C2
D6
C9
D9
90
DF
10
B9
FII
DE
BE
BE
0000·
6E
6F
EB
EB
F5
P
P
P
P
003C
003D
003F
00111
8F
BO
BO
BO
70
P
P
P
P
FC
80
110
3F
7F
F7
71
77
P 00113 56
P 00116 56
P 00119 116
P DOIIC 9F
FA
FB
FB
E7
EF
08
P OOIlD 116
P 0050 AF
P 0051
F1
03
P 0051 OF 00
P 0053 007A 01
P 0056 02 03
228
229
230
231
232
233
2311
235
236
237
238
239
2110
2111
2112
2113
21111
2115
2116
2117
2118
2119
250
251
252
253
2511
255
256
257
258
259
260
261
262
263
2611
265
266
267
268
269
270
271
272
273
,!initialize Port 3 Mode Register for serial I/O!
AND
TMR,II~FC
!disable TOI
ld
si TMP1,SER cfg Iconfiguration datal
AND
si-TMP1,H~80
!odd parity select!
OR
sCTMP1 ,H~1I0
IP30/7 = Sin/Soutl
AND
Imask
off old settings I
P3R save, U3F
OR
P3~save,si TMP1 !new selection I
LD
P3M-;P 3M_save
Ito write-only register I
I initialize TOI
ld
ldc
ldci
ldc
call
ld
ld
rl
scf
rlc
ld
I ini tiali ze RAM
DI
clr
clr
clr
si TMP1,HTO
si-TMP2,@si PTR Isave counter I
@sl TMP1,@sl PTR linit counterl
si TMP1,@si ~TR Iget prescalerl
multiply
ITO x PREOI
SERhtime,R12
! save for BREAK ••• I
SERltime,R13
I ••• detection
si TMP1
ISHL 11
Icontinuous model
si TMP1
!SHL 21
PR~O,si TMP1
flags and pointers!
Idisable interrupts!
SER get
I input buffer ••• 1
SER-put
I ••• empty!
I no ~rrorsl
SER=flg
!initialize interrupts!
AND
IRQ,HU7
IMR,UEF
and
or
IMR,HS08
EI
!gol
or
TMR,n03
ret
END
ser init
Iclear IRQ3 &: II!'
!disable IRQII (xmt)1
lenable IRQ3 (rcv)!
Iload/enable TOI
!Defaults for serial initialization!
ser def RECORD
:=
[cfg_, imr
BYTE
-
buf
len=, ctr_, pre_
[ec+al+ie+be,
~OO,
SER_char, 1,
WORD
BYTE]
~02,
~O3]
233
P 0058
P 0058 BO
P
P
P
P
P
P
P
P
P
005A
D05C
005E
0060
0063
0065
0068
006A
006.D
234.
70
70
70
D6
7B
76
6B
76
6B
275
276
277
278
279
280
281
282
283
2811
285
286
287
288
289
290
291
292
293
2911
295
296
297
298
299
300
301
302
303
3011
305
306
307
308
309
310
311
312
313
3111
315
316
317
318
319
320
321
322
323
3211
325
326
327
7E
328
329
EE
330
EF
331
ED
332
0170'
333
118
- 3311
72 CO
335
08
336
7C 80
337
03
338
CONSTANT
rli len
GLOBAL
ser rlin
:=
R13
PROCEDURE
1··. .·······*··········································
read line
Purpose =
To return input from serial channel
up to 'carriage return' character ~r
maximum length requested or BREAK.
Input =
RR111 = address of destination buffer
(in reg/ext memory)
R13 = maximum length
Output
Input charact'ers is destination buffer.
RR111·= unmodified
R13 = length returned
Carry Flag = 1 if any error,
= 0 if no error.
R12 indicates read status
Note =
1. Return will be made to the calling
program only after the requisite
characters have-been received from
the serial line.
2. If input editting is enabled, a
'backspace' character will cause
the previous character (if any) in the
the destination buffer to be deleted;
a 'delete' character will cause all
previous characters (if any) in the
destination buffer to be deleted.
3. If parit~ (odd or even) is enabled,
the parity error flag (R111). will be set
if any character returned had a parity
error. (Bit 7 of each character may
then be examined if it is desirable to
know which character(s) had the error).
II. The status flags 'BREAK detected",
'parity error', and 'input buffer
overflow' will be returned
as part of R12, but will be cleared in
SER_stat.
5. The staus flags: 'input buffer full'
and 'input buffer not empty' will be
updated in SER stat.
.....
ENTRY·· ... ···············*····...······················1
clr
ser read:
push
push
push
rli II: call
jr
tm
jr
tm
jr
TEMP..,:3
!flag => read liner
!save original ••• 1
R111
I ••• dest. pointer!
R15
I ••• and lengthl
rli len
ser-get
Iget input character I
c,rTi 3
lerrorl
SER cTg,fJop LOR ep Iparity enabled?1
z,rli 1
Inol
!parityerror?1
TEMP ." #$80
z,rlT_1
Inol
P
P
P
P
P
P
P
006F
0072
0075
0078
007A
0070
0080
116
06
A6
EB
56
16
6B
P
P
P
.p
P
P
P
P
P
P
P
P
P
P
P
0082
0085
0087
008A
008C
008E
0090
0093
0095
0096
0099
009A
009C
009E
OOAl
A6 7C 1F
6B 3E
A6 1C 08
EB 11
50 1C
10 1C
All ED 1C
6B 30
DE
26 EF 02
EE
EA 02
8B C2
36 EE '00
8B BD
P
P
P
P
P
P
P
P
P
P
00A3
00A5
00A8
OOAA
OOAB
OOAD
OOAF
00B2
OOBII
00B6
00
A6
6B
DE
DA
50
211
08
C8
56
P
P
P
P
P
P
P
00B9
OOBA
OOBD
OOBF
OOCO
00C2
OOCII
CF
16
6B
OF
50
50
AF
P
P
P
P
P
00C5
00C1
00C9
OOCB
OOCD
50
50
50
8B
10 10
0000·
1E 00
31
1C 1F
12 08
21
ED
1C
03
00
B3
1C
ED 1C
7C
10
10 . E3
EC
01
9C
EF
EE
ED
EF
EE
80
339
3110
3111
3112
3113
3114
3115
346 linput
3111
3118
3119
350
351
352
353
3511
355
356
351
358
359
360
361
362
363
364
365
366
361 r11 2:
368 rl():
369
310
371
312
313
3111
315
316
317
318
319
380
381
382 r11 6:
383
3811
385
386 END
or
SER flg,Dpe
call
put-dest
cp
TEMP 3,/10
jr
nz,rTi 2
and
TEMP 1~D~1F
tm
SER efg ,llie
jr
z,rTi 9
edittingl
cp
TEMP 1,/I~1F
jr
z,rlT 6
cp
TEMP 1~D~08
jr
nz,rli 9
pop
TEMP 1push
TEMP-l
cp
TEMP-l,rli len
jr
eq,rTi 6 inc
rli len
sub
R15~/l2
inc
R111
djnz
Rll1,rli 1
jr
rli II Rll1~#O
sbc
jr
r11_11
dec
cp
jr
inc
djnz
pop
sub
Id
Id
and
rcf
tm
jr
scf
pop
·pop
ret
I yes. set error fl ag!
Istore in buffer!
I read line? I
Inol
.
!ignore parity bit!
linput editting on?1
Ino.1
!char = delete?1
Iyesl
Ichar = backspace?1
!no. continue I
Iget original lengthl
lany characters?1
Inonel
lundo last decrement!
!backspace & previous I
Ireg or ext mem?1
lextl
Iregl
rli len
TEMP 1,nOD
z,rlT 3
rli len
r.li-len ,r11 II
TEM]!" 1
TEMP-l, r11 len
.1"11 Ten, TERp 1
R12~SER flg ,-
lin case crt
!carriage return?1
I.end input I
Irestorel
Iloop for max lengthl
loriginal lengthl
!O chars returned I
I tell calle'rl
Ireturn read statusl
SERJlg~#LNOT (pe LOR bd LOR bo)
Ireset for next time!
Igood return codel
R12,/lpe LOR bd LOR bo LOR sd
z,rli_5
Ino error I
!set error returnl
R15
R111
loriginal buffer addr!
pop
rli len
pop
R15R111
pop
jr
ser read
ser rlin
Istart over!
::Sllll uLUtlAL
P OOCD
P OOCD E6
P 0000 8B
P 0002
7E
88
01
389
390
391
392
393
3911
395
396
391
398
399
1100
1101
402
1103
11011
ser rabs
PROCEDURE
I····*·····*··u ••••••• * •••••••••••••••••••••••••••••••
read absolute
Purpose =
To return input from serial channel
of maximum length requested. (Input
is not terminated with the receipt of
a 'carriage return'. BREAK will
termina.te read.)
Note = .
All other details are as for 'ser rlin'.
T···1
•••••••••••••• a •••• a •••••••••••••••••••••••••••••
ENTRY
.
ld
TEMP 3,#1
ser read
ser_rabs
-
Iflag
=> read absolutel
.j!"
END
235
P OOD2
P 00D2
P 00D5
P 00D7
P OODA
P OODB
P OODD
P OODF
P 00E1
P 00E4
P 00E6
P 00E8
P OOEB
P OOED
P·OOEF
P 00F1
P 00F3
P 00F6
E4
70
54
9F
70
31
A8
76
6B
BO
76
6B
9C
A2
EB
76
EB
FD
70
FO
E2
2F
E9
E2
02
80
A9
22
E8
1D
P 00F8 46
P OOFB 76
P OOFE 6B
EO
03
FB
P
P
P
P
P
6E
6F
35
FE
6E
0100
0102
0104
0106
0108
236
70
70
8C
8A
80
03
FB
73
78
FB
02
80
01
08
01
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
GLOBAL
ser input
PROCEDURE
!*****************************.***********************
Interrupt service - Serial Input
Purpose =
To service IRQ3 by inputting current
character into next available position
in circular buffer.
Input =
None.
Output
New character inserted in buffer.
SER_stat , SER_put updated.
Note
1. If even parity enabled, the software
replaces the eigth data bit with a
parity error flag.
2. If BREAK detection is enabled, and
the received character is null,
the serial input line is monitored to
detect a potential BREAK condition.
BREAK is defined as a zero start bit
followed by 8 zero data bits and a
zero stop bit.
3. If 'buffer full' on entry, 'input
buffer overflow' is flagged.
4. If input echo is on, the character is
immediately sent to the output serial
channel.
5. IMR is modified to allow selected
nested interrupts (see ser init).
******************************************V**********I
ENTRY
.
.
ld
push
and
ei
push
srp
ld
tm
jr
clr
tm
jr
ld
SER tmp 1, %03
imrimr ,SER_imr
tread stop bit level!
!save entry imr!
! allow nesting!
rp
!save user's!
IIRAM STARTr
rSERchar,SIO
!capture input!
rSERcfg ,llbe
!break detect enabled?!
z,ser 30
!nope. !
rSERtiiip2
r SERc fg ,llop
todd parity enabled?!
Ino. !
z,ser 23
rSERtiiip2,11%80
rSERchar,rSERtmp2 !8 received bits = O?!
ne,ser 30
!no!
rSERtmp1,1I1
!test stop bit!
jr
nz,ser 30
!not BREAK!
lis BREAK. Wait for marking!
or
rSERflg,lIbd
!set BREAK flag!
ser 24: tm
%03,111
!marking yet?!
jr
z,ser 24
!not yet!
!wait 1 char time to Tlush receive shift register!
push
SERhtime
push
SERltime
! save PREO x TO I
in loop: ld
rSERtmp 1,1153
Ip1:
djnz
rSERtmp1,lp1
!delay 640 cycles!
decw
SERhtime
P 010A EB
F8
P
P
P
P
010C
010E
0110
0113
50
50
56
8B
6F
6E
FA
49
P 0115
P 0118
P 011A
P 011D
P 011F
P 0121
P0124
P 0126
P 0129
P 012C
76
EB
76
6B
A9
66
EB
56
76
6B
EO
4A
E2
OA
FO
FA
FB
FA
E2
14
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
8C
BO
CO
16
8A
56
B2
CO
CO
88
98
02
8E
8A
F3
116
7E
A2
EB
BO
A2
EB
116
50
8F
50
BF
07
E9
EA
E9
F9
E9
012E
0130
0132
0134
0137
0139
013C
013E
01110
0142
01114
0146
0148
01119
0111B
014D
0150
0151
0153
0155
0157
0159
015B
01SE
0160
0161
0,163
F7
01
01
10
EF
40
00
01
Ag',
EA
EA
E4
E5
97
lE
9A
EO
76
02
E7
71
03
EO
FD
02
01
FB
p
0164 46
P 0167 8B
EO
F5
04
P 0169 16
016C 92
016E 8B
0170
E8
A8
DD
00
p
p
p
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
,512
513
514
515
516
517
518
519
520
521
522
523
jr
nz, in_loop
pop
pop
and
jr
SERltime
SERht1me
IRQ,IILNOT
ser_i5
I delay (128x10xPREOxTO)!
I
----------------!
I
2
I
~08
I restore PREO x TOI
' I clear int req I
Ibyel
ser_30: tm
rSERflg,lIbf
I buffer full? I
jr
nz,ser il
I yes .overflowl
tm
r SERc fg , lIec
lecho on?1
Inol
jr
z,ser iO
Id
SIO, r'SERchar
lechol
Ipolll
ser_16,: tcm
IRQ,II~10
jr
nz,ser i6
!loop I
Iclear irq ,bit!
and
IRQ,IILNOT ~10
ser iO: tm
rSERcfg,llep
leven parity?1
jr
z,ser 22
Ino parityl
!calculate parity error flagl
rSERtmpl,117
Id
clr
rSERtmp2
Icount l's herel
ser 20: rrc
rSERchar
!bit to carryl
adc
rSERtmp2,110
lupdate l's count!
djnz
rSERtmp1,ser 20 Iloop till done!
and
rSERtmp2,lIl 11's count even or odd?1
rSERchar,rSERtmp2
xor
rrc
rSERchar
!parity error flag ••• 1
rrci
rSERchar
I ••• to bit 71
ser 22: Id
rSERtmph,rSERbufh
rSERtmpl,rSERbufl
Id
add
rSERtmpl,rSERput Inext char address I
inc
rSERtmph
lin external memory?1
djnz
rSERtmph,ser i2 lyes.1
@rSERtmpl ,rSi:Rchar Istore char in buff
Id
ser_i 3: or
r SERfl g ,lIbne
Ibuffer not emptyl
inc
rSERput
lupdate put ptrl
cp
rSERput,rSERlen !wrap-around?1
jr
ne,ser i4
Inol
clr
rSERput
!set to startl
ser ill: cp
rSERput,rSERget !if equal, then fuli!
jr
ne,ser i5
rSERflg,lIbf
or
pop
ser_i5:
rp
Irestore user's!
qi
pop
imr
Irestore entry imrl
iret
ser 11: or
jr
rSERflg,lIbo
ser _i5
!buffer overflowl
rSERtmph,IIO
ser i2: adc
Ide
@rrSERtmp,rSERchar I store in bufl
jr
ser_i 3
END
ser_input
237
Ifor PART II
525 GLOBAL
526 ser get PROCEDURE
P 0170
527 ! ••T ••••••••••••••••••••••••••••••••••••••••••••••••••
P
P
P
P
0170
0172
01711
0175
70
31
DF
76
FD
70
P
P
P
P
P
P
P
P
P
0178
017A
017D
017F
0181
0183
01811
0186
0187
EB
76
6B
D8
C8
8F
02
CE
CA
211
EO
F6
E5
Ell
P
P
P
P
P
P
P
P
P
P
P
P
P
0189
018B
018E
018F
0191
0193
0195
0197
0199
019C
019D
019E
01AO
E3
56
1E
A2
EB
BO
A2
EB
56
CF
9F
50
AF
CD
EO
FE
16
02
E1
17
03
EO
FD
P
P
P
P
01 A1 16
01AII 82
01A6 8B
01A8
EC
CC
E3
238
EO
8C
02
D1
18
FD
00
528
529
530
531
532
533
5311
535
536
537
538
539
5110
5111
5112
5113
51111
5115
5116
5117
5118
5119
550
551
552
553
5511
555
556
557
558
559
560
561
562
563
5611
565
566
567
568
569
570
571
572
573
5711
575
576
577
Purpose
To return one serial input character.
Input =
None.
Output =
Carry FLAG =
Note =
This routine will not return control
until a character is available in the
input buffer or an error is detected.
if BREAK detected or
serial not enabled
or buffer overflow
o otherwise
TEMP_1 = character
·····················································1
ENTRY
push
srp
scf
ser_g1: tm
jr
tm
jr
ld
ld
di
add
inc
djnz
ld
ser_gll: and
inc
cp
jr
clr
ser_g2: cp
jr
and
ser_g5: rcf
ei
ser _g6: p'op
ret
rp
nRAM_STARTr
Isave caller's rpl
Ipoint to subr. RAMI
lin case errorl
rSERflg,nsd LOR bd LOR bo
Iserial disabled or
BREAK detected or
buffer overflow? I
nZ,ser g6
lyes.1
rSERflg,nbne
Ibuffer not empty? I
z,ser g1
lempty. waitl
rTEMP-1l,rSERbufl
rTEMP-1h,rSERbufh
Iprevent IRQ3 conflict!
rTEMP 1l,rSERget Inext char address I
rTEMP-1h
I input buffer in •.• 1
rTEMP-1h,ser g3 I •. I.external memory!
I ••• register memoryl
rTEMP 1,@rTEMP 11 Iget char!
rSER'fTg,nLNOT of Ibuffer not full!
rSERget
lupdate get pointerl
rSERget,rSERlen Iwrap-around?1
ne,ser g2
Ino.1
Iyes. set to startl
rSERget
rSERget,rSERput Ibuffer empty if get •.• 1
ne,ser g5
I .•• and put =1
rSERfl'g,nLNOT bne Ibuffer empty nowl
Iset good returnl
Ire-enable interrupts I
r.p
Irestore caller's rpl
ser_g3: adc
rTEMP 1h,nO
IrrTEMP 1 has char addr!
Ide
rTEMP-1,@rrTEMP 1 Iget CharI
jr
ser_g4
-I clean upl
END
ser_get
P 01A8
P 01AS BO
P 01AA 80
P 01AC EB
FO
EE
FA
P 01AE 80
P 01Bl
0238'
P 01Bl
579
580
581
582
583
5811
585
586
587
588
589
590
591
592
593
5911
595
596
597
598
599
600
601
602
603
6011
605
606
607
608
609
610
611
612
613
GLOBAL
ser break
PROCEDURE
! •••••••••••••••••••••••••••••••••••••••••••••••••••••
break transmission
Purpose
=
Input
Output =
Note
=
To transmit BREAK, on the serial line.
RR111 = break length
None.
BREAK is defined as:
. serial out (P37) = 0 for
x 28 cycles/loop x RR111 loops
2
XTAL
RR111 should yield at least 1 bit time
so that the last 'clr SIO' will
have been preceded by at least 1 bit
time of spacing. Therefore, RR111 should
be greater than or equal to
II x 16 x PREO x, TO
28
••••••••••••••••••••••••••••••••••••••••••••••••••••• !
ENTRY
ser bl:
clr
SIO
decw
RR111
jr
nZ,ser bl
! wait for last null to~e fully transmitted!
jp
ser 01
ser break
END
615 GLOBAL
PROCEDURE
616 ser flush
617
618 input flush
619
620 Purpose =
To flush (clear) the .serial input
buffer of characters.
621
622
None
623 Input =
6211
Empty input buffer.
625 Output =
626
627 Note =
This routine might be useful to clear
628
all past input after a BREAK has been
detected on the line.
629
630
631 ENTRY
632
di
Idisable interrupts!
633
!(to avoid collision with
6311
serial input) 1
635
clr
SER_get I buffer start I ,
636
clr
SER put I = buffer end!
637'
and
SER-flg,HJ80
!clear statusl
638
ei
Ire-enable interrupts 1
639'
ret
6110 END
ser flush
I············································.···.·· ..
·····················································1
P 01Bl 8F
P
P
P
P
P
P
01B2
01BII
01B6
01B9
01BA
01BB
BO
BO
56
9F
AF
71
77
70
80
239
P 01BB
P 01BB BO
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
01BD
01BE
01C1
01C3
01C5
01C8
01CB
01CD
01DO
0.1D2
01D5
01D8
01DA
01DC
01 DF
01E1
01E4
01E7
01E9
01EB
01ED
01FO
01F2
01F3
01F4
240
DF
76
EB
70
D6
D6
7B
A6
EB
56
A6
EB
00
76
6B
E6
D6
8B
DA
50
24
D8
CF
AF
7E
70 80
30
ED
0000'
020B'
1E
7E 00
17
7C 7F
7C OD
OF
ED
72 04
OA
7C OA
020B'
02
DA
7C
ED 7C
7C
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
CONSTANT
wli len
GLOBAL
ser wlin
:=
R13
PROCEDURE
! ••T ••••••••••••••••••••••••••••••••••••••••••••••••••
write line
Purpose
Input
=
To output a character string to serial
line, ending with either a 'carriage
return' character or the maximum length
specified.
= address of source buffer
(in reg/ext memory)
R13 = length
RR14 = updated
Carry Flag = 1 if serial not enabled,
= 0 if no error.
R13 = U bytes output (not including
RR14
Output
auto line feed)
Note
=
If auto line feed is enabled"a
line feed character will be output
following each carriage return
(ser wlin only).
•••••••••••••••••••••••••••••••••••• **.** •• ****** •••• 1
ENTRY
.
clr
!flag => write line!
write:
wli 4:
wli 1:
END-
scf
SER flg, Iisd
tm
jr
nz,wli 1
wli len
push
get-src
call
ser-output
call
jr
c ,wTi 2
cp
TEMP j,IIO
jr
nz,wlr 5
and
TEMP 1-;-II%7F
TEMP-1,nOD
cp
nz,wli 5
jr
dec
wli len
SER-c fg, Iial
tm
jr
z,wli 2
ld
TEMP",II%OA
call
ser 'Output
wl1-2
jr
wli-len,wli 4
djnz
TEKP 1
pop
TEMP-1,wli len
sub
wli_len,TERP_1
ld
rcf
ret
ser wlin
lin case error!
!serial disabled?!
! yes. error!
!write the character!
!serial disabled!
!write line?!
! no, absolute.!
!mask off parity!
!line done?!
!yes. !
!auto line feed?!
!disabled!
!output line feed!
!loop!
!original length!
!return output count!
!no error!
P 01F4
P 01F4 E6
P 01F7 8B
P 01F9
7E
C4
01
P 01F9
P 01F9 C9
P 01FB D6
P 01FE 76
P 0201 6B
P 0203 A6
P 0206 EB
P 0:?08 E6
P 020B
7C
020B'
72 04
3E
EC OD
39
7C OA
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
GLOBAL
ser wabs
PROCEDURE
!UUV&UUUUUUuuuuuuuu*uuuuuuuuuuuu*u.*uuuuuuuvuuu*nvuuuu
write absolute
Purpose =
Note
=
To output a character string to serial
line for the length specified. (Output
is not terminated with the output of
a 'carriage return').
All other details are as for 'ser wlin'.
uu.~uuu*uuuuuuuuuuuuuuUUUU.UHUUUUUUuuuuu**uunHuuu.uUU!
ENTRY
Id
TEMP 3,#1
jr
write
ser wabs
END
ser wbyt
PROCEDURE.
!UUvuuuuununuuunuuuuuuUHUUHUfUUUUU*UUU*UluuuuunuuRuuuU
write byte
Purpose
In put =
Note
=
=
To output a given character to the
serial line. If the character is a
carriage return and auto line feed
is enabled, a line feed will be output
as well.
R12
= character
to output
Equivalent to ser wlin with length
= 1.
uuuuuuuuuuuuuuuuuuuuuuu*UUUUUHUD~.uuuuuunuuuuU&UUUUHU!
ENTRY
Id
TEMP 1,R12
call
ser output
tm
SER-cfg,IJal
jr
z,ser 05
cp
R12,IJIOD
jr
nZ,ser 05
Id
TEMP l~#~OA
!fall into ser outpu~!
END
ser_wbyt
!output it!
lauto line feed?!
!not enabled!
!char = car. ret?!
Inopel
!output line feed!
241
P 020B
P
P
P
P
P
020B
020C
020F
0211
0214
DF
76
EB
76
6B
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0216
0218
021B
021D
021F
0222
0224
0226
0229
022C
022F
0231
0233
0235
0238
023B
023D
0240
0241
0242
70
E6
BO
CO
16
00
EB
56
56
44
CO
CO
50
E4
66
EB
56
CF
AF
70
30
72
1F
7E
7E
7D
7C
7D
7E
F7
7D
7C
7D
7C
7C
7E
7C
FA
FB
FA
80
40
07
00
01
FE
7C
FO
10
EF
P 0242
P 0242 8F
P 0243 46
70
80
P 0246 56
F1
FC
P 0249 56
FB
E7
P 024C 56
7F
BF
024F E4
0252 9F
0253 AF
0254
7F
F7
P
P
P
P
242
740
741
742
743
7411
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
7611
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
787
788
789
790
791
792
793
7911
795
796
797
798
799
800
801
802
803
8011
805
806
807
808
809
810
811
GLOBAL
!for PART I!
ser output
PROCEDURE
1**T**************************.********** ••• ****.****.
Purpose
To output one character to the serial
line.
= character
FLAG = 1 if serial disabled
= 0 otherwise.
Input =
TEMP 1
Output
Carry
Note
1. If even parity is enabled, the eigth
data bit is modified prior to character
output to SIO.
2. IRQII is polled to wait for completion
of character transmission before control
returns to the calling program.
**********.I*** ••• * •••••••• """"""""""*""*!
ENTRY
lin case errorl
scf
lserial disabled?!
tm,
SER flg,Usd
lyes. errorl
jr
nz,ser 05
leven parity enabled?!
tm
SER cfg,Uep
!no. just output!
jr
z,ser 02
!calculate parityl
TEMP 3
push
ld
TEMP-3,U7
clr
TEMP-2
!character bit to carry!
TEMP-1
ser 04: rrc
adc
TEMP-2,UO
!count 1'sl
dec
TEMP-3
jr
nz,ser 04
!next bit!
!1's count odd/even!
and
TEMP 2~U01
and
TEMP-1,il%FE
!parity bit in DOl
or
TEMP-1,TEMP 2
rrc
TEMP-1
!parity bit in D7!
rrc
TEMP-1
pop
TEMP-3
!output character!
ser 02: ld
SIO,7EMP
ser-01: tcm
IRQ,U%10!check IRQII!
!wait for complete!
jr
nz,ser 01
lclear IRQ4!
and
IRQ,II%t:F
! all ok!
ref
ser 05: ret
ser_output
'ENDGLOBAL
ser disable
PROCEDURE
1··T •••• **.*.* ••••••••• * •• * ••••••••••••••••••••••• * •••
disable '
To disable serial I/O
Purpose
~perations.
None.
=
Output =
Serial I/O disabled .
••••••••••••••••••••••••••••••••••••••••••••••••••••• !
Input
ENTRY
di
or
and
and
and
END
!avoid IRQ3 conflictl
SER flg,Usd
!set serial disabl"edl
TMR, il%FC
!disable TOI
IMR,il%E7
!disable IRQ3,4!
P3M save,U%BF
!P30/7 normal i/o pins!
P3M,P3M save
-Ire-enable interrupts I
ld
ei
ret
ser disable
Timer/Counter Routines
P 0254
P
P
P
P
P
P
0254
0256
0258
025A
0250
0260
DC
C3
C3
E6
80
6C
DE
DE
7B 6C
02B2'
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
CONSTANT
R13
TMP
PTR
RR14
=
R14
PTRh
=
GLOBAL
tod i
PROCEDURE
1**T,*.U._* ••••• *•••••• *,.'u*** ••• **** •• *••• *u ••••••••
time of day
initialize
Purpose =
To initialize TO or Tl to function as
a time of day clock.
Input
RR14
= address of parameter list
program memory:
byte = IMR mask for nestable
in
interrupts
# of clock ticks per second
counter # : = %F4 => TO
= %F2 => T1
byte = Counter value
byte = Prescaler value (unshifted)
byte
byte
TOO hr, TOO min, TOO sec, TOO tt
inItialized to the starting time of
hours,minutes, seconds, and ticks
respectively.
Output
Note
=
=
Selected timer is loaded and
enabled; corresponding interrupt
is enabled .
.R13, R14, R15.modified.
The cntr and prescaler values provided
are those values which will generate an
interrupt (tick) the designated # of
times per second.
For example:
for XTAL = 8 MHZ, cntr = 250 and
prescaler = 40 yield a .01 sec interval;
the 2nd byte of the parameter list
should = 100 •
For TO the instruction at %080C or
for Tl the instruction at %080F must
result in a jump to the jump table entry
for 'tod'.
The parameter list is not referenced
following initialization.
•• UUUuDu*ulnu.*.* •• uuu.unnnuuu.*.IUUIU ••• uooeunuDu •• U!
ENTRY
TMP,IITOD imr
ld
@TMP,@PT~
limr maskl
ldci
@TMP,@PTR
!ticks/second!
ldci
TEMP 4, IITOD ' imr
ld
jp
pre_ctr
Ictr & prescalerl
tod i
END
243
P 0260
0260
0262
0265
0266
0268
026A
026B
026D
026F
0271
0272
0275
0277
0279
D27A
027D
p 027F
P 0281
70
54
9F
70
31
8E
A2
EB
BO
9E
A5
EB
BO
AE
A5
EB
BO
BE
FB
6C
P
P
P
P
P
50
8F
50
BF
FD
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0282
0284
0285
0287
0288
FB
FD
60
8D
13
E8
E9
OB
E9
3C
EA
03
EA
3C
FB
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
GLOBAL
PROCEDURE
tod
!v*****************.****IH*****************R.**** ••• **
Interrupt service - time of day
Purpose
ENTRY
push
and
ei
push
srp
inc
cp
jr
clr
inc
cp
jr
clr
inc
cp
jr
clr
inc
tod ex: pop
di
pop
iret
END
tod
/
244
To update the time of daY'clock.
•• *.*.*.c~a~~*~**~*~e**~~~e~*~~!**~***~**.*~*********!
imr
imr, TOD_ imr
rp
IIRAM TMRr
rTODCt
r TODtt, rTODtic
ne,tod ex
rTODtC
rTODsec
r TODsec ,1160
ne,tod ex
rTODsec
rTODmin
rTODmin ,1160
ne,tod ex
rTODmin
rTODhr
rp
imr
! save entry imr!
! allow nested interrupts
tenable interrupts!
!save rp!
!point to our set!
!ticks/second!
!second complete? !
!nope. !
!seconds!
!minute complete?!
!nope. !
!minutes!
!hour complete?!
!nope.!
! hour s!
restore rp!
disable interrupts!
restore entry imr!
P 0288
P
P
P
P
P
P
P
P
P
P
P
P
0288
028A
028C
028E
0290
0292
0294
0297
029A
029D
02AO
02A3
DC
C3
C3
C3
80
80
56
56
E4
E6
8D
65
DE
DE
DE
EE
EE
F1 3F
7F DF
7F F7
7B 01
02B2'
P 02A3
P 02A3 B4
P 02A6 B4
P 02A9 B4
65
67
65
67
65
67
P 02AC F5
P 02AF BF
P 02BO
67
66
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
GLOBAL
pulse i PROCEDURE
!****************.*u**u*******u.u**.*.**.********u**u*
To initialize one of the timers
.Purpose =
to generate a variable frequency/
variable pulse width output.
Input =
RR14 = address of parameter list in
program memory:
byte
cntr value for low interval
byte
counter 1/ : = %F4 => TO
= %F2 => T1
cntr value for high interval
byte
byte
prescaler (unshifted)
Output
Selected timer is loaded and
enabled; corresponding interrupt
is enabled. P36 is enabled as Tout.
R13, R14, R15 modified.
Note
The parameter list is not referenced
following initialization.
The value of Prescaler x Counter
must be > 26 (=%1A) for proper
operation.
*nnnuunnu*nuunuuuuuuun.nuuunuu.nnuunnn** •• nn ••• nn •••• !
ENTRY
TMP,I/PLS 2
LD
ldci
@TMP,@PTR
!low interval cntr!
!timer addr!
@TMP,@PTR
ldci
!high
interval cntr!
ldci
@TMP,@PTR
PTR
decw
! back to flag!
decw
PTR
!will be modifying TMR!
and
TMR,I/%3F
and
P3M save, I/%DF
!P36 = Tout!
ld
P3M"";P3Msave
! flag for pre ctr!
ld
TEMP 4,0%1
!set up timerT
jp
pre_ctr
END
pulse- i
GLOBAL
pulse
PROCEDURE
! ••• *unnu.unu ••• *n.n****u •• nn •• u.n •• uuuuu •••• u.nAu**.u
To modify the counter load value
Purpose =
to continue the pulse output generation.
u.u ••• u.nuun.u ••• n*uu.n •• uununun.uuun •••••• un •• u•• uUU!
ENTRY
!exchange values!
PLS_1, PLS_2
xor
xor
PLS 2,PLS 1
xor
PLS-1,PLS-2
!exchange complete!!load new value!
@PLS_tmr,PLS_
ld
iret
pulse
END
245
P 02BO
P 02BO BO
P 02B2
246
7B
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
GLOBAL
delay
PROCEDURE
1**********···········································
Purpose =
To generate an interrupt after a
designated amount of time.
=
Input
Output
Note
=
= address of parameter list in
program memory:
byte = counter # : = $F4 => TO
= $F2 => T1
byte = Counter ~alue
byte = Prescaler value and count mode
(to be loaded as is into
PREO or PRE1).
RR14
Selected timer is loaded and
enabled; corresponding interrupt
is enabled.
R13, R14, R15 modified.
This routine will initialize the timer
for single-pass or continuous mode
as determined by bit 0 of byte 3 in
the parameter list.
The caller is responsible for providing the interrupt service routine.
The parameter list is not referenced
following initialization.
·····················································1
ENTRY
clr
TEMP 4
!fall into pre ctrl END
delay -
P 02B2
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
02B2
02B4
02B6
02B9
02BC
02BF
02Cl
02C4
02C7
02C9
02CB
02CE
0200
0201
0203
0204
0206
0209
020B
0200
02EO
02E2
02E5
02E7
02EA
02EB
02EE
02EF
02FO
C2
AD
E6
E6
A6
6B
E6
E6
C3
C2
A6
6B
OF
10
OF
10
A6
EB
60
54
60
56
F3
44
8F
44
9F
AF
DE
EE
70
7E
ED
06
70
7E
DE
EE
7B
12
8C
20
F2
4,
10
00
EE
EE
7B
OA
7E
7E
7E
70
DE
70
Fl
7E
FB
6C
6C
OF
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
INTERNAL
pre ctr PROCEDURE
! •••••• ****§ ••••••••• * •••• u*u •••••••••••••••••••••••••
To get counter and prescaler values
'Purpose =
from parameter list and modify control
registers appropriately.
Input
TEMP 4
= 0 => for 'delay'
= 1 => f for 'tod'
u*uuu •• uu*nnnnu*DnnnDftn&DDnnU~unUnUDnftUUnUnnftnDnUDUUn!
ENTRY
!TO or TlI
TMP,@PTR
ldc
PTR
incw
I for TMRI
TEMP 2,II'f,aC
ld
I for IMR!
TEMP-3,11'f,20
ld
cp
TMP ,7fT 1
!i_s for Tl!
eq,pre 1
jr
! for TMRI
TEMP 2-;11%43
ld
I fOr IMRI
TEMP-3, 11% 10
ld
!init counterl
@TMP-;@PTR
pre 1 : lctcl
!prescaler!
PTRh,@PTR
ldc
!shift prescaler?1
cp
TEMP 4,110
!no!
eq,pre_2
jr
!internal clock!
scf
PTRh
rIc
!continuous mode!
scf
PTRh
rIc
cp
TEMP 4,IITOO imr
! for 'pulse'!
ne,pre 3
jr
TEMP 3com
!insure
no self-nesting!
TOO Tmr,TEMP_3
and
com
TEMP 3
' !no Tout mode mod!
TEMP-2,II'f,OF
pre 2: and
!init prescaler!
@TMP-;PTRh
pre=3: ld
!init tmr mode!
TMR,TEMP_2
or
di
tenable interrupt!
imr,TEMP_3
or
ei
ret
pre ctr
ENO
ENO PART n-
O errors
Assembly complete
247
A Comparison of
Microcomputer Units
Zilog
Benchmark Report
May 1981
INTRODUCTION
The microcomputer industry has recently developed
single-chip microcomputers that incorporate on one
chip functions previously performed by peripherals. These microcomputer units (MCUs) are aimed
at markets requ1r1ng a dedicated computer. This
report describes and compares the most powerful
MCUs in today's market: the Zilog ZB611, the
Intel B051, and the Motorola MC6B01. Table 1
lists facts that should be considered when comparing these MCUs.
Table 1. MCU Comparison
fEATURES
Zilog
ZB611
Intel
B051
Motorola
MC6801
On-Chip ROM
4KxB
4KxB
2KxB
General-Purpose
Registers
124
12B
12B
Special-function
Registers
Status/Control
I/O ports
16
4
16
4
4
32
four B-bit
Hardwar~ on
three ports
32
four B-bit
None
29
Three B-bit,one 5-bit
Hardware on
one port
5
2
5
2 Programmable
orders
5
7
Maskable
B
4
6
4B Programmable
orders
6
External
Memory
120K bytes
124K bytes
64K bytes
16-Bit
Yes, uses
B-bits
Yes
B-Bit
Yes
16-Bit
Yes
No
Yes
I/O
Parallel lines
Ports
Handshake
Interrupts
Source
External source
Vector
Priority
Stack
Stack pointer
Internal stack
External stack
248
17
2
7
Nonprogrammable
6
Table 1. MCU Compariaon
(Continued)
FEATURES
Zilog
Z8611
Intel
8051
Motorola
MC6801
Counter/
Tin:ers
Counters
Two 8-bit
One 16-bit
Prescalers
Two 6-bit
Two 16-bit
or two 8-bit
No prescale
with 16-bits;
5-bit prescale
with 8-bits
Addressing
Modes
Register
Indirect Register
Indexed
Direct
Relative
Immediate
Implied
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
124, Any
generalpurpose
register
1,
Yes
Yes
Yes
One for each
One for both
One for both
Receiver
62.5K b/s
@8 MHz
93.5K b/s
@12 MHz
Receiver
187.5K b/s
®12 MHz
Transmi tter/Receiver
62.5K b/s
@4 MHz
2.2 Usec
1.5 Usec ®12 MHz
1.5 Usec
3.9 Usec
4.25 Usee
2.8 Usee ®12 MHz
4 Usee
10 Usec
12 MHz
4 MHz
Saves first
128 registers
Saves first
64 registers
Index
Registers
Serial
ClJIIlmunication
Interface
Full duplex
UART
Interrupts
for transmit
and receive
Registers
Double buffer
Serial Data Rate
Speed
Ins truct ion
execution average
Longest
instruction
Clock Frequency
8 and 12
Power Down
Mode
Saves first
124 registers
Context
Switching
MHz
Saves PC
and flags
Uses the
accumulator
for 8-bit
offset
Saves PC;
proqrammer
must save all
registers
None
1, Uses
16-bit index
register
Saves PC, PSW,
ae cu mula to rs ,
and Index
register
249
Table 1. HCU Comparison
(Continued)
lilcg
IB611
Intel
B051
Motorola
MC6B01
Development
40-Pin
ProtDpack (B613)
64-Pin (B612)
40-Pin ROM less
(IB6B1 )
40-Pin (B751 )
40- Pin (6B701)
Eprom
4K bytes (2732)
2K bytes (2716)
4K bytes
2K bytes
Availability
NDW
fEATURES
ARCHITECTURAl OVERVIEW
This sectiDn examines three chips: the .on-chip
functiDns and data areas manipulated by the ZilDg,
Intel and MDtDrDla MCUs. The three chips have
sDmewhat similar architectures. There are, hDWever, fundamental differences in design criteria.
The B051 and the MC6B01 were designed tD maintain
cDmpatability with .older prDducts, whereas the
ZB611 design was free frDm such restrictiDns and
cDuld experiment with new ideas. Because .of this,
the accumulatDr architectures .of the MC6B01 and
the B051 are nDt as flexible as that .of the ZB611,
which allDws any register tD be used as an accumulatDr.
Memory Spaces
TBA
NDW
required with the MC6B01 that is nDt necessary
with the ZB611 Dr the B051.
On Chip RAM. All three chips use internal RAM as
registers. These registers are divided intD tWD
catagDries: general-purpDse registers and special
functiDn registers (SFRs).
The 124 general-purpDse registers in the ZB611 are
divided intD eight grDups .of 16 registers each.
In the first grDup, the lDwest fDur registers are
the I/O pDrt registers. The .other registers are
general purpDse and can be accessed with an B-bit
address Dr a shDrt 4-bit address. Using the 4-bit
address saves bytes and executiDn time. FDur-bit
shDrt addresses are discussed later. The generalpurpDse registers can be used as accumulatDrs, address pDinters, Dr Index registers.'
,
The ZB611 CPU manipUlates data in fDur memDry
spaces:
•
•
•
•
60K bytes .of external data memDry
60K bytes Df'external prDgram memDry
4K bytes .of int,ernal program memDry (ROM)
144-byte register file
The 12B general-purpDse registers in the 8051 are
grDuped intD tWD sets. The IDwer 32 bytes are
allDcated as fDur B-register banks, and the upper
registers are used fDr the stack Dr fDr general
purpDse. The registers cannot be used fDr indexing Dr as address pDinters.
The B051, CPU manipUlates data in fDur memDry
spaces:
• 64K bytes .of external data memDry
• 60K bytes .of external prDgram memDry
• 4K bytes .of internal prDgram memDry
~ 14B-byte register file
The MC6B01 manipulates data in three memDry
spaces:
• 62K bytes, .of external memDry
• 2K bytes .of internal prDgram memory
• 149-byte register file
On-Chip ROM. All three chips have internal ROM
fDr prDgram memDry. The ZB611 and the B051 have
4Kbytes .of internal ROM, and the MC6B01 has 2K
bytes. In SDme cases, external memDry may be
250
The MC6B01 alsD has a 12B-byt e, general-purpDse
register bank, which can be used as a stack Dr as
address pDinters, but nDt as Index registers.
As pDinted .out in Table 1, any of the ZB611
general-purpDse registers can be used fDr indexing; the MC6B01 and the 8051 cannDt use registers,
this way. The ZB611 can use any register as an
accumulatDr; the MC6801 and the B051 have fixed
accumulatDrs. The use .of registers as mem.ory
p.ointers is very valuable, and .only the Z8611 can
use its registers in this way.
The number .of general-purp.ose'registers .on each
chip is c.omparable. H.owever, because .of its
flexible design, the ZB611 clearly has a mDre
p.owerful register architecture.
The ZB611 has 20 special function registers used
for status, control, and I/O. These registers
include: '
• Two registers for a 16-bit Stack Pointer (sPH,
SPL)
• One register used as Register Pointer for
working registers (RP)
e One register for the status flags (FLAGS)
III One register for interrupt priority (lPR)
III One register for interrupt mask (IMR)
e One register for interrupt request (IRQ)
• Three'mode registers for the four ports (P01M,
P2M, P3M)
• Serial communications port used like a
register (SID)
• Two couhter/timer registers (TO, Tl)
• One Timer Mode Register (TMR)
• Two prescaler registers (PREO, PRE1)
• Four I/O ports accessed as registers (PORTO,
PORT1, PORT2, PORT3)
The B051 also has 20 special function registers
used for status, control, and I/O. They include:
• One register for the Stack Pointer (SP)
8 Two accumulators (A,B)
• One register for the Program Status Word
(PSW)
III Two registers for pointing to data memory
(DPH, DPL)
Q Four
registers that serve as two 16-bit
counter/timers (THO, TH1, TLO, TL1)
• One mode register for the counter/timers
(TMOD)
8 One control register for the counter/timers
(TCON)
III One register for interrupt enable (lEC)
III One register for interrupt priority (IPC)
III One regi ster for serial communications buffer
(sBUF)
• One register for serial communications control
(sCON)
o Four registers used as the four I/O ports (PO,
P1, P2, P3)
The MC6B01 has 21 special function registers used
for status, control, and I/O. These include:
• One register for RAM/EROM control
o One serial receive register
• One serial transmit register
III One register for serial control and status
III One serial rate and mode register
III One register for status and control of port 3
• One register for status and control of the
timer
III Two registers for the 16-bit timer
III Two registers' for 16-bit input capture used
with timer
III Two registers for 16-bit output compare used
with timer
• Four data direction registers associated with
the four I/O ports
III Four I/O ports
The special function registers in the three chips
seem comparable in number and function. However,
upon closer examination, the sFRs of the p.£6B01
prove less efficient than those of the ZB611. The
MC6B01 has five registers associated with the I/O
ports, whereas the ZB611 uses only three registers
for the same funct ions. The MC6B01 uses four
registers to perform the serial communication
function, whereas the ZB611 uses only one register
and part of another.
The B051 uses two registers for the accumulators;
the ZB611 is not limited by this restriction. The
B051 also uses two registers for the serial communication interface, whereas the ZB611 accomplishes the same job with one register. Another'
two registers in the B051 are used for data
pointers; these are not necessary in the ZB611
since any register can be used as an address
pointer.
The ZB611 uses registers more efficiently than
either the MC6B01 or the B051. The registers saved
by this opt imal design are used to perform the
functions needed for enhanced interrupt handling
and for register pointing with short addresses.
The ZB611 also supplies the extra register required for the external stack. These features are
not available on the B051 or the MC6B01.
External Memory. All three chips can access
external memory. The ZB611 and the B051 can generate signals used for selecting either program or
data memory. The Data Memory st robe (the signal
used for selecting data or program memory) gives
the ZB611 access to 120K bytes of external memory
(60K byt es in both program and data memory). The
B051 can use 124K bytes of external memory (64K
bytes of external dat a memory and 60K bytes of
external program memory). The MC6B01 .can access
only 62K bytes of external memory and does not
distinguish between program and data memory. Thus,
the ZB611 and the B051 are clearly able to access
more external memory than the MC6B01.
On-Chip Peripheral Functions
In addition to the CPU and memory spaces, ail
chips provide an interrupt system and extensive
I/O facilities including I/O pins, parallel I/O
ports, a bidirectional address/ data bus, and a
serial port for I/O expansion.
Interrupts. The Z.B611 acknowledges interrupts
from eight sources, four are external from pins
IRQO-IRQ3, and four are internal from serial-in,
serial-out, and the two counter/timers. All
interrupts are maskable, and a wide variety of
priorities are realized with the Interrupt Mask
Register and the Interrupt Priority Registers (see
,Table 1). All ZB611 interrupts are vectored, with
six vectors located in the on-chip ROM. The
vectors are fixed locations, two bytes long, that
contain the memory address of the service routine.
251
The 8051 acknowledges interrupts from five
sources: two external sources (from INTO and
INT1) and three internal sources (one from each of.
the internal counters and one from the serial I/O
port). All intcrrupts can be disebledindi vidually or globally. Each of the five sources can be
assigned one of two priorities: high or low. All
8051 interrupts are vectored. There are five
fixed locations in memory, each eight bytes long,
allocated to servicing the interrupt.
The MC6801 has one external interrupt, one nonmaskable interrupt, an internal interrupt request,
and a software interrupt. The internal interrupts
are caus~d by the serial I/O port, timer overflow,
timer output compare, and timer input capture.
The pr iori ty of each interrupt is preset and cannot be changed. The external interrupt can be
masked in the Condition Code register. The MC6801
vectors the interrupts to seven fixed addresses in
ROM where the 16-bit address of the service
routine is located.
When an interrupt occurs in the 8051, only the
Program Counter is saved; the user must save the
flags, accumulator, and any registers that the
interrupt service routine might affect. The
MC6801 saves the Program Counter, acumulators,
Index register, and the PSW; the user must save
all registers that the interrupt service routine
might affect. The Z8611 saves the Program Counter
and the Flags register. To save the 16 working
registers, only the Register Pointer register need
be pushed onto the stack and another set of working registers is used for the service routine.
For more detail on working registers and interrupt
context switching, see the Z8 Technical Manual
(03-3047-02).
With regard to interrupts, the Z8611 is clearly
superior. The Z8611 requires only one command to
save all the working registers, which greatly
increases the efficiency of context switching.
I/O Facilities. The Z8611 has 32 lines dedicated
to I/O functions. These lines are grouped into
four ports with eight lines per port. The ports
can be configured individually under software
control to provide input, output, multiplexed
address/data lines, timing, and status. Input and
output can be serial or parallel, with or without
handshake. One port can be configured for serial
transmission and four ports can be configured for
parallel transmission. With parallel transmission, ports 0, 1, and 2 can transmit data with the
handshake provided by port 3.
handshake. The ports provide all the signals
needed to control input and output either serially
or in parallel, with or' without multiplexed
address/data lines. They can be used to interface·
with external memory.
The main differences in I/O facilities are the
number of 8-bit ports and the hardware handshake.
The Z8611 and the B051 have four 8-bit ports,
whereas the MC6801 has three 8-bit ports and an
additional 5-bit port. The Z8611 has hardware
handshake on three ports, the MC6B01 has hardware
handshake on only one port, and the 8051 has no
hardware handshake.
Counter/timers. The Z8611 has two 8-bit counters
and two 6-bit programmable prescalers. One prescaler can be driven internally or externally; the
other prescaler is driven internally only. Both
timers can interrupt the CPU when counting is
completed. The counters can operate in one of two
modes: t hey can count down until interrupted, or
they can count down, reload the initial value, and
start counting down again (continuously). The
counters for the Z8611 can be used for measuring
time intervals and pulse widths, generating variable pulse widths, counting events, or generating
periodic interrupts.
The 8051 has two 16-bit counter/timers for measuring time intervals and pulse widths, generating
pulse widths, counting events, and generating
periodic interrupts. The counter/timers have
several modes of operation. They can be used as
8-bit counters or timers with two 5-bit programmable prescalers. They can also be used as 16-bit
counter/timers. Finally, they can be set. as B-bit
modulo-n counters with the reload value held in
the high byte of the 16-bit register. An interrupt
is generated when the counter/timer has completed
counting.
The MC6801 has one 16-bit counter which can be
used for pulse-width measurement and generation.
The counter/timer actually consists of three
16-bit registers and an 8-bit control/status register. The timer has 'an input capture register,
an output compare register, and a free-running
counter. All three 16-bit registers can generate
interrupts.
The 8051 also has 32 I/O lines grouped together
into four ports of eight lines. each. The ports can
be configured under program control for parallel
or serial I/O. The ports can also be configured
for multiplexed address/data lines, timing, and
status. Handshake· is provided by user software.
Serial Communications Interface. The Z8611 has a
programmable serial communication interface. The
chip contains a UART for full-duplex, asynchronous, serial receiver/ transmitter operation. The
bit rate is controlled by counter/timer 0 and has
a maximum bit rate of 93.500 b/s. An interrupt is
generated when an assembled character is transferred to the receive buffer.
The transmitted
character generates a separate interrupt. The
receive register is do~ble-buffered. A hardware
parity generator and detector are optional.
The MC6B01 has 29 lines for I/O (three 8-bit ports
and one 5-bit port). One port has two lines for
The 8051 handles serial I/O using one of its
parallel ports. The 8051 bit rate is controlled
252
by counter/timer 1 and has a maximum bit rate of
187,500 b/s. The 8051 generates one interrupt for
both transmission and receipt. The receive register is double-buffered.
The MC6801 contains a full-duplex, asynchronous,
serial communication interface. The bit rate is
controlled by a rate register and by the MCU's
clock or an external clock. The maximum bit rate
is 62,500 b/s. Both the transmit and the receive
registers are double-buffered. The MC6B01 generates only one interrupt for both transmit and
receive operations. No hardware parity generation
or detection is available, although it does have
automatic detection of framing errors and overrun
condit ions.
The 8051 and the MC6B01 generate only one interrupt for both transmit and receive, whereas the
ZB611 has a separate interrupt for each. The
ability to generate separate interrupts greatly
enhances the use of serial communications, since
separate service routines are often required for
transmitting and receiving.
Other differences between the lB611, MC6B01, and
the B051 occur in the hardware parity detector,
the double-buffering of registers, framing error
detectors and overrun conditions. The 8051 has a
faster data rate than either the ZB611 or the
MC6B01. The MC6801 has the advantage of a hardware framing error detector and aut omat ic detection of overrun conditions. The MC6B01 also has
both its transmit
and
receive
registers
double-buffered. The ZB611 has a hardware parity
detector. For detection of framing errors and
overrun conditions, a simple, low-overhead software check is available that uses only· two
instructions. See Z8600 Software Framing Error
Detection Application Brief (document #617-1B810004).
INSTRUCTION ARCHITECTURE
The architecture of the ZB611 is designed specifically for microcomputer applications. This fact
is manifest in the instruction composition. The
arduous task of programming the MC6B01 and the
B051 starkly contrasts that of programming the
ZB611.
Addressing Modes
The ZB611 and the B051 both have six addressing
modes: Register, Indirect Register, Indexed,
Direct, Relative, and Immediate. The MC6801 has
five addressing modes: Accumulator, Indexed,
Direct, Relative, and Immediate. A quick comparison of these addressing modes reveals the ve rs atility of the Z8611 and the 8051.
The addressing
modes of the MC6801 have several restrictions, as
shown in Table 1. While the B051 has all the
addressing modes of the Z8611, its use of them is
restricted. The Z8611 allows many more combina-
tions of addressing modes per instruction, because
any of its registers can be used as an accumulator. For example, the instructions to clear,
complement, rotate, and swap nibbles are all
accumulator oriented in the 8051 and operate on
the accumulator only. These same commands in the
Z8611 can use any register and access it either
directly, with register addressing, or with indirect register addressing.
Indexed Addressing. All three chips differ in
their handling of indexing. The Z8611 can use any
register for indexing. The 8051 can use only the
accumulator as an Index register in conjunction
with the data pointer or the Program Counter. The
MC6801 has one 16-bit Index register. The address
located in the second byte of an instruction is
added to the lower byte of the Index register.
The carry is added to the upper byte for the complete address. The MC6801 requires the index
value to be an immediate value.
The MC6B01 has only one 16-bit Index register and
an immediate 8-bit value from the second byte of
the instruction. Hence, the Indexed mode of the
MC6801 is much more restrictive than that of the
Z861" • The 8051 must use the accumulator as its
only Index register, loading the accumulator with
the register address each time a reference is
made. Then, using indexing, the data is moved
into the accumulator, eradicating the previous
index. This forces a stream of data through the
accumulator and requires a reload of the index
before access can be made again. The Z8611 is
clearly superior to both the MC6801 and the 8051
in the flexibility of its indexed addressing mode.
Short and Long Addressing. Short addressing helps
to optimize memory space and execution speed. In
sample applications of short register addressing,
an eight percent decrease in the number of bytes
used was recorded.
All three chips have short addressing modes, but
the ZB611 has short addressing for both external
memory and register memory. The 8051 has short
addressing for the lowest 32 registers only.
The Z8611 has two different modes for register
addressing. The full-byte address can be used to
provide the address, or a 4-bit address can be
used with the Register Pointer. To use the working registers, the Register Pointer is set for a
particular bank of 16 registers, and then one of
the 16 registers is addressed with four bits.
Another feature for addressing external memory is
the use of a 12-bit address in place of a full
16-bit address. To use the 12-bit address, one
port supplies the eight multiplexed address/data
lines and another port supplies four bits for the
address. The remaining four bits of the second
port can be used for I/O. This feature allows
access to a maximum of 10K bytes of memory.
253
The 8051 uses short addresses by organizing its
lowest 32 registers into four banks. The bank
select is located in a 2-bit field in the PSW,
with three bits addressing the register in the
bank.
The MC6801 uses extended addressing for addressing
external memory. With a special, nonmultiplexed
expansion mode, 256 bytes of external memory can
be accessed without the need for an external
address latch. The MC6801 uses one 8-bit port for
the address and another port for the data.
Stacks
The Z8611 and the MC6801 provide for external
stacks, which require a 16-bit Stack Pointer.
Internal stacks use only an 8-bit Stack Pointer.
The 8051 uses only a limited internal stack requiring an 8-bit Stack Pointer. Using an external
stack saves the internal RAM registers for
general-purpose use.
Summary
The stack structure of the Z8611 and the MC6801 is
better than that of the 8051. In most applications, the 8051 is more flexible and easier to
program than the MC6801. The Z8611 is easier to
use than either the 8051 or the MC6801 because of
its register flexibility and its numerous combinations of addressing modes. The 8051 features a
unique 4~n multiply and divide command. The
MC6801 has a multiply, but it takes 10)('s to perform it.
In summary, the Z8611 has the most flexible
addressing modes, the most advanced indexing capabilities, and superior space- and time-saving
abilities with respect to short addressing.
with its 8051 family. The 8031 has no internal
ROM and the 8751 has 4K of internal EPROM.
Motorola offers the MC6801, MC6803, MC6803NR, and
MC68701. These are all similar except the MC68701
has 2K bytes of EPROM and the MC6801 has 2K bytes
of ROM. The MC6803 has no internal ROM and the
MC6803NR has neither ROM nor RAM on board.
The Z8613 and the MC68701 are both available now,
but the 8751 is still unavailable (as of April
1981) •
Software
Development software includes assemblers, and
conversion programs. All manufacturers offer some
or all of these features.
Since the MC6801 is compatible with the 6800,
there is no need for a new assembler. The Z8611
and the 8051 both offer assemblers for their
products. The Zilog PLZ/ASM assembler generates
relocatable and absolute object code. PLZ/ASM
also supports high-level control and data statements, such as IF ••• THEN ••• ELSE. Intel offers an
absolute macroassembler, ASM51 , with their
product. They also offer a program for converting
8048 code to 8051 code.
Modules
The Z8611 development module has two 64-pin
development versions of the 40-pin, ROM-masked
Z8611. Intel offers the EM-51 emulation board,
which contains a modified 8051 and PROM or EPROM
in place of memory. Motorola has the MEX6801EVM
evaluation board for program development. All
three development boards are available now.
DEVELOPMENT SUPPORT
ADDITIONAL FEATURES
All three vendors provide development support for
their products. This section discusses the di fferent support features, including development
chips, software, and modules.
Additional features include Power Down mode, selftesting, and family-compatibility.
Chips
POlfer Down Mode
Zilog offers an entire family of microcomputer
chips for product development and final product.
The Z8611 is a single-chip microcomputer with 4K
bytes of mask-programmed ROM. For development, two
other chips are offered. The Z8612 is a 64-pin,
development version with full interface to external memory. The Z8613 is a prototype version
that uses a functional, piggy-back, EPROM protopak. The Z8613 can use either a 4K EPROM (2732)
or a 2K EPROM (2716). Zilog also offers a ROMless
version in a 40-pin package that has all the features of the Z8611 except on-board ROM (Z8681).
All three microcomputers offer a Power Down mode.
The Z8611 and the 8051 save all of their registers with an auxilary power supply. The MC6801
uSeS an auxiliary power supply to save only the
first 64 bytes of its register file.
Intel offers a similar line of development chips
254
The Z8611 uses one of the crystal input pins for
the external power supply to power the registers
in Power Down mode. Since the XTAL2 input must be
used, an external clock generator is necessary and
is input via XTAL1. The 8051 and the MC6801 both
have an input reserved for this function. The
MC6801 uses the Vcc standby pin, and the 8051 uses
the Vpd pin.
Femily Compatibility
Program Listings
Another strength of the Z8611 is its expansion
bus, which is completely compatible with the Zilog
Z-BUSTM. This means that all Z-BUS peripherals
can be used directly with the Z8611.
8051
The MC6B01 is fully compat ible with all MC6800
family products. The 8051 is software compatible
with the older 804B series and all others in that
family.
BENCH~lARI(S
The following benchmark tests were used in this
report to compare the Z8611, 8051, and MC6801:
o Generate CRC check for 16-bit word.
o Search for a character in a block of memory.
o Execute a computed GOTO - jump to one of eight
locations depending on which of the eight bits
is set.
o Shift a 16-word five places to the right.
o Move a 64-byte block of data from external
memory to the register file.
o Toggle a single bit on a port.
o Measure the subroutine overhead time.
These programs were selected because of their
importance in microcomputer applications. Algorithms that reflect a unique function or feature
were excluded for the sake of comparison. Although programs can be optimized for a particular
chip and for a particular attribute (code density
or speed) these programs were not.
The figures cited in this text are taken directly
from the vendor's documentation. Therefore, the
cycles given below for the MC6801 and the B051 are
in machine cycles and the l8611 figures are gi ven
in clock cycles. The ZB611 clock cycles should be
divided by six to give the instruction time in
microseconds. The 8051 and MC6801 machine cycle
is 1).(.s, and the ZB611 clock cyc Ie is .166,«.s at
12 MHz.
Because of the lack of availability of the MC6801
and the B051, the benchmark programs listed here
have not yet been run. When these products are
readily available, the programs will be run and
later editions of this document will reflect any
changes in the findings.
CRC Generation
Machine
Cycles
MOV
INDEX, 118
LOOP: MDV A, DATA
XRL
A, HCHECK
RLC
A
MOV
A, LCHECK
XRL
A, LPDLY
RLC A
MOV
LCHECK, A
MOV
A, HCHECK
XRL
A, HPOLY
RLC A
MOV
HCHECK, A
CLR
C
MOV
A, DATA
RLC A
MOV DATA, A
DJNl INDEX, LOOP
RET
N
= 3+17XB
= 139 cycles
®12 MHz = 139 As
Instructions = 1B
Bytes = 31
Mt::6B01
LDAA 11$08
LOOP: STAA mUNT
LDAA HCHECK
EORA DATA
RDLA
LOAD POLY
EORA' HCHECK
EORB LCHECK
ROLB
ROLA
STAD LCHECK
ASL
DATA
DEC
COUNT
BNE
LOOP
RTS
N = 45X8+7 = 367 cycles'
®4 MHz = 3674s
Instructions = 15
Bytes = 2B
Bytes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
1
2
Machine
Cycles
2
2
1
2
2
1
2
2
2
1
2
1
2
1
2
Bytes
2
2
3
3
2
2
3
2
4
3
1
2
3
2
2
2
2
2
1
1
4
2
6
6
4
5
3
3
2
1
Clock
Bytes
Cycles
LD
INDEX, #8
6
2
LOOP: LD
R6, DATA
6
2
XOR
R6, HCHECK
6
2
RLC
R6
6
2
XOR
LCHECK, LPOLY
6
2
RLC
LCHECK
6
2
XOR
HCHECK, HPOL Y
6
2
RLC
HCHECK
6
2
RCF
6
1
RLC
DATA
6
2
DJNZ INDEX, LOOP
12 or 10
2
RET
14
1
N = 20+66X7+64 = 546 cycles
®12 MHz = 91 '«'s
Instructions = 12
Bytes = 22
ZB611
255
Shift 16-Bit Word to Right 5-Bits
Character Search Through Block of 40 Bytea
8051
Machine
Cycles
MOV INDEX, 1141
MOV DPTR, flTABLE
LOOP1: DJNZ INDEX, LOOP 2
SJMP OUT
LOOP2: MOV A, INDEX
MOVC A, @A+DPTR
CJNE A, CHARAC, LOOP1
OUT:.
N = 3+39X7+4 = 2BO cycles
®12 ·MHz = 280.u.s
Instructions = 7
Bytes = 15
MC6B01
LDAB
LDAA
LOX
LOOP: CMPA
BEQ
INX
DECB
BNE
OUT: -
11$40
IICHARAC
IITABLE
$0, X
OUT
LOOP
1
2
2
2
2
2
Machine
Cycles
2
2
3
4
4
3
2
4
8051
Bytes
2
3
2
2
2
3
Bytes
2
2
3
2
2
1
2
N = 7+40X17 = 687 cycles
®4 MHz = 687.u..s
Instructions = 8
Bytes = 15
N = 6+38X40 = 1524 cycles
®12 MHz = 2541(..s
Instructions = 5
Bytes = 11
256
MC6801
LOX 115
LOAD WORK
LOOP: LSRD
DEX
BNE LOOP
STAD WORD
N = 10X5+11 = 61 Cycles
®4 MHz = 61_
Instructions = 6
Bytes = 11
Z8611
ZB611
Clock
Cycles
LD
INDEX, 1140
6
LOOP: LD
DATA, TABLE (INDEX) 10
DATA, CHARAC
6
CP
JR
Z, OUT
12 or 10
DJNZ INDEX, LOOP
12 or 30
OUT: -
MOV INDEX 115
LOOP: CLR C
MOV A, WORD + 1
RRC A
MOV WORD + 1, A
MOV A, WORK
RRC A
MOV WORD, A
DJNZ INDEX, LOOP
N = 1+9X5 = 46 Cycles
@12 MHz = 46#8
Instructions = 9
Bytes = 15
Bytes
2
3
2
2
2
Machine
Cycles
1
Bytes
2
2
2
2
2
1
2
2
Machine
Cycles
6
4
3
3
4
4
Bytes
3
2
2
2
Clock
Cycles
Bytes
LD
INOEX, 115
6
2
LOOP: CCF.
6
RRC WORD + 1
6
2
RRC WORD
6
2
DJNZ INDEX, LOOP
12 or 10
2
N = 6+4X30+28 = 154 Cycles
®12 MHz = 264s
Instructions = 5
Bytes = 9
CG:01puted GOTO
B051
MOV
LOOP: MOV
RLC
JC
MOV
ADD
MOV
SJMP
OUT: MOV
MOV
JMP
TABLE: LCALL
INDEX, 1140
A, DATA
A
OUT
A, INDEX
A, #3
INDEX, A
LOOP
DPTR, IITABLE
A, INDEX
®A+DPTR
ADDR1
Hove 64-Byte Block
Hachine
Cycles
1
2
2
2
1
2
B051
Bytes
2
2
1
2
1
2
2
3
1
MOV
INDEX, ilCOUNT
LOOP: MOV
DPTR, #ADDR1
MOVX A, IIDPTR
INC
IIADDR1
MOV
®ADDR2,A
INC
ADDR2
DJNZ INDEX, LOOP
N = 1+9X64 = 577 Cycles
®12 MHz = 577~s
Instructions = 7
Bytes = 10
t·;c6801
LDAB 112
LDX
TABLE
LOOP: RORA
BCS
OUT
ABX
JMP
LOOP
OUT: LDX
0, X
JMP
0, X
N = 8X12+14 = 110' Cycles
®4 MHz. = 110,u.s
Instructions = 8
Bytes = 17
Z8611
1
2
2
Bytes
2
3
2
3
LCALL ADDRN
N = 1+9X7+11 = 75 Cycles
®12 MHz = 75.a.s
Instructions = 12
Bytes = 21
tt.C6B01
Machine
Cycles
~lachine
2
~~::china
Cycles
2
3
2
4
3
3
5
4
Bytes
2
3
2
1
2
3
3
Clock
Cycles
Bytes
CLR INDEX
6
2
LOOP: INC INDEX
6
RLC DATA
6
2
JR NC, LOOP
12 or 10
2
LD ADDR,TABLE 1, (INDEX)
10
3
LD ADDR+1,TABLE 2, (INDEX) 10
3
JP @ADDR
12
2
N = 6+24X7+54 = 22B Cycles
®12 MHz = 38«..s
Instructions = 7
Bytes :: 15
LDAB ilCOUNT
LOOP: LDX
ADDR1
LDAA 0, X
INX
STAA ADDR1
LDX
ADDR2
STAA 0, X
INX
STX
ADDR2
DECB
BNE
.LOOP
N = 64X36+2 = 2306 Cycles
®4 MHz =2306 4s
Instructions = 11
Bytes = 21
Cycles
2
4
4
3
4
4
4
3
4
2
4
Bytes
2
3
2
1
2
3
2
1
2
2
ZB611
Clock
Cycles
Bytes
LD
INDEX, IICOUNT
6
2
LOOP: LDEl ®ADDR2, ®ADDR1
18
2
DJNZ INDEX, LOOP
12 or 10
2
N = 6+63X30+2B = 1924 Cycles
®12 MHz = 321~s
Instructions = 3
Bytes = 6
257
Toggle a Port Bit
Subroutine Call/Return Overhead
Machine
Cycles
8051
PO, I!YY
XRL
N = 2 Cycles
®12 MHz = 2MS
Instruct ions =
Bytes = 3
MC6801
LDAA
EORA
STAA
N= 8
PORTO
I!YY
PORTO
Cycles
®II MHz = 8 ","s
Instructions = 3
Bytes = 6
2
8051
LCALL SUBR
Bytes
Bytes
3
SUBR: -
Machine
Cycles
3
2
3
REf
N 4 Cycles
®12 MHz = 4"'s
Ins truct ions
2
Bytes = 4
Bytes
2
2
MC6801
JSR
2
2
Mschine
Cycles
SUBR
9
Bytes
2
SUBR: RTS
XOR
PORTO, UYY
N = 10 Cycles
®12-MHz = 1.7 4-S
Instructions = 1
Byte = 2
2
3
N
Z8611
Machine
Cycles
Clock
Cycles
10
Bytes
5
14 Cycles
®4 MHz = 14.«.s
Ins truct ions
2
Bytes = 3
2
Z8611
CALL ®SUBR
Clock
Cycles
. 20
Bytes
2
SUBR: REf
N = 34 Cycles
®12 MHz = 5.7 Ms
Ins truct ions = 2
Bytes = 3
14
Results
Table 2 summarizes the results of this comparison.
The relative performance column lists the speeds
of the MC6801 and 8051 divided by the Z8611 speeds
(12 MHz). The overall performance averages the
separate relative performances. The higher the
number, the faster the Z8611 as compared to the
MC6801 and the B051.
The relative performance figures show that the
ZB611 runs 50 percent faster than the 8051 and 250
percent faster than the MC6B01. Although speed is
not necessarily the most important criterion for
select ing a particular product, the ZB611 proves
to be an undeniably superior product when speed is
added to the advantages of programming ease, code
density, and flexibility.
258
Table 2.
Benchmark
Test
MC6801
(414Hz)
cycles time
Benchmark Program Results
8051
(12 MHz)
cycles time
Z8
(8 MHz)
cycles time
Z8
(12 tJjHz)
cycles time
Relative Performance
MC6801
8051
CRC
Generation
367
367
139
139
546
137
546
91
4.03
1.53
Character
Search
687
687
280
280
1524
382
1524
254
2.70
1.10
Computed
GOTO
110
110
75
75
228
57
228
38
2.89
1.97
61
61
46
46
154
38
154
26
2.35
1.78
2306
2306
577
577
1924
481
1924
321
7.18
1.80
14
14
4
4
34
8.5
34
5.7
2.46
0.70
8
8
2
2
10
2.5
10
1.7
4.71
1.18
3.76
1.44
Shift Right
5 Bits
Move
64-byte
block
Subroutine
Overhead
Toggle a
Port Bit
Overall
Performance
Note:
All times are given in microseconds.
Table 3.
Bytes
MC6801 8051
Byte/Instruction/Time Comparison
Z8611
Instructions
MC6801 8051 Z8611
Time (microseconds)
Z8611
MC6B01 8051
CRC Generation
28
31
22
15
18
12
367
139
91
Character Search
15
15
11
8
7
5
687
280
254
Shift Right 5 Bits
11
15
9
6
9
5
61
46
26
Computed GOTO
17
21
15
8
12
7
110
75
38
Move Block
21
10
6
11
7
3'
2306
577
321
Toggle Port Bit
6
3
2
3
1
1
8
2
1.7
Subroutine Call
3
4
3
2
2
2
14
4
5.7
259
SUMMARY
The hardware of the three chips compared is very
similar. The Z8611, however', has several advantages, the most important of which is its interrupt structure. It is more advanced than the
interrupt structures of both the 8051 and the
Me6801. Other advantages of the Z8611 over either
the Me6801 or the 8051 include I/O facilities with
parity detection and hardware handshake and a
larger amount of internal ROM (the Me6801 has only
2K bytes).
the Z8611 are more flexible than those of either
the Me6801 or the 8051. The Z8611 can use bytesaving addressing with working registel'S, and it
has short external addresses for saving I/O lines.
It can also provide for an external stack. The
register architecture (as opposed to the accumulator architecture) of the Z8611 saves execution
time and enhances programming speed by reducing
the byte count.
Substantial differences are apparent with regard
to software architecture. The addressing modes of
The Z8611 microcomputer stands out as the m6st
powerful chip of the three, and concurrently, it
is the easiest to program and configure.
260
Z86 Interrupt
Request Register
~
Zilog
Application Brief
October 1980
The Interrupt Request Register (IRQ, R250)
stores requests from the six possible Interrupt sources ( IRQO_IRQ5) In the Z8600 series
microcomputer. In addition to other functions, a hardware reset to the Z8600 disables
the IRQ register and resets Its request bits.
Before the IRQ will register requests, It
must first be enabled by executing an Enable
Interrupts (EI) Instructl~n. Setting the
Enable Interrupt bit In the Interrupt Mask
Register (IMR, R251) Is not an equivalent
operation for this purpose; to enable the
IRQ, an EI Instruction Is required. The
function of this EI Instruction Is distinct
from Its task ofglobelly enabling the Interrupt system. Even In a pol led system where
IRQ bits are tested In software, It Is
necessary to execute the EI.
The designer must ensure that unexpected and
undesirable Interrupt requests will not occur
after the EI Is executed. One method of
doing this Is to reset all Interrupt enable
bits In the IMRJor levels that are possible
Interrupt sources; the EJ Instruction may
then be safely executed. Once EI Is executed, the program may Immediately execute a
Disable Interrupts (01) Instruction. The
code nec.essary to perform these operations Is
as fol lows:
RESET:
LD
EI
IMR, 6'f,XX
ISET INTERRUPT MASK!
!ENABLE GLOBAL INTERRUPT, ENABLE IRQI
where XX has a ~ In each bit position corresponding to the Interrupt level to be
disabled. If al I IMR bits are to be reset, a
CLR IMR Instruction may be used.
EI INSTRUCTION
INTERRUPT REQUEST REG.
(IRQ, R250)
Z8600
RESET
-~------'
Figure 1 -'IRQ Reset FunctIonal LogIc DIagram
261
18 Family Software
Framing Error Detection
~.
Zilog
Applicaftion Brief
October 1980
I NTROOUcr I ON
The Zllog ZB600 UART mlcrocanputer Is a hlgh- ,
performance, single-chip device that Incorporates on-chip ROM, RPM, parallel I/O,
serial I/O, and a baud rate generator. The
UART Is capable of full-duplex, asynchronous
serial communication at nine standard
software-selectable baud rates fran 110 to
19.2K baud; other nonstandard rates can also
be.obtalned under software control. Odd
parity generation and checking 'lan also be
selected.
START
BIT
Three possible error conditions can occur
during reception of serial data: framing
error, parity error, and overrun error. A
framing error condition occurs when a stop
bit Is not received at the proper time
(Figure I). This can result fran noise In
the data channel, caus Ing erroneous detect ion
of the previous start bit or lack of detection of a properly transmitted stop btt. The
Z8600 UART does not Incorporate hardware
framing error detection but does facilitate a
simple, low-overhead software detection
method.
PARIIY STOP
(IF BIT
ENABLED)
DATA BITS (8)
Fig. 1 - Asynchronous Data Format
In the midd Ie of the stop bit time, the Z8600
UART automatical'y posts a serial Input
Interrupt request on IRQ3. The serial Input
can a I so be teSted by r,ead I ng Port 3 bl t 0
(P30) as shown In Figure 2. Thus, within
,the interrupt service routine or polling
loop, it is only necessary to test P3 0 in
order to Identify a framing error. If P30 Is
Low when IRQ3 goes High, a framing error con-
METHOD
SERIAL _
DATA IN
ditlon exists and the following code Is used
to test this:
P3, 6%01
JR Z, FERR
1M
The execution time of this framing error test,
is only 5.5A(.s at 8 MHz. In the worst case
(19.2K baud), this would result in 1% overhead. Only five program bytes are required.
P3 0
ZB600
'\
Z8 is a·trademark of Zllog, Inc.
262
I TEST FOR P30 = I I
I ELSE FRAMING ERROR I
Fig. 2 - ZB600 Serial Input COnnection
CONCLUSION
While the Z8600 UART does not incorporate
hardware framing error detection, this
feature can be Implemented In software with a
maximum penalty of 1% at 19.2K baud using no
additional hardware and only five bytes of
program memory.
Reprinted with permission of Synertek, Inc.
263
- -
Zilog
•
November 1984
264
•
~
-
---
,
-T'
~,~
-
'"'- '""
Technica,1
_
~
I
...-"~
H'"
-
--.....---to -,-.--,-
~~nual·e.: ", '., ~ '"
_ _~_ ~
L
--
__
,,-..;I,
~_
:
'.;;I,.;_..
-..,......:;..-~-
;; ,
L
.... "'"'.~ •• ~
>'""
~~
......
:~,~.~
~ ;...-o>_.~:LJ.:-,,,,,,~l_' . .:J~~
..
Table Of Contents
Chapter 1.
1.1
1.2
Z8 fanily Overview
Introduction
Features
• 261
• 261
261
261
'1.2.1 Instruction Set
1.2.2 Architecture ••
1.3
Microcomputers (Z8601/11)
1.4
Development Device (Z8612)
262
1.5
Protopack Emulator (Z8603/13)
264
1.6
8ASIC/Debug Interpreter (Z8671) •
264
1.7
ROMless Microcomputer (Z8681/82)
264
1.8
Applications
• 262
..
••••
264
Chapter 2. Architectural Overvi~
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.5
2.6
2
Introduction.
Address Spaces
Register File •
• 266
266
267
267
267
267
267
Register Pointer
Instruction Set
Data Types •••
Addressing Modes
I/O Operations
.267
2.4.1
2.4.2
.267
.267
Timers.
Interrupts
.'
Oscillator,
Protopack.
.268
.268
Chapter 3. Addresa Spaces
3.1
3.2
3.3
3.4
3.5
3.6
3
Introduction ••
CPU Register File
• 269
• 269
3.2.1
.270
CPU
CPU
CPU
CPU
Error Conditions
Control and Peripheral Registers
Program Memory
Data Memory
Stacks • • • •
"
"
.271
·271
.273
.274
265
Table Of Contents (Continued)
Chapter 4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Introduction • •
Register Addressing (R).
•••
Indirect Register Addressing (IR)
Indexed Addressing (X)
Direct Addressing (DA)
Relative Addressing (RA)
Immediate Data Addressing (1M)
Chapter 5.
5.1
5.2
5.3
5.4
5·.5
5.6
5
Instruction Set
279
280
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
280
280
280
281
281
281
Carry Flag (C)
Zero Flag (Z)
Sign Flag (S)
Overflow Flag (V)
Decimal-Adjust Flag (D)
Half-Carry Flag (H)
Condition Codes • • • • • •
Notation and Binary Encoding
281
281
5.4.1 Assembly Language Syntax • • • • •
5.4.2 Condition Codes and Flag Settings
282
282
Instruction Summary • • • • • • • • •
Instruction Descriptions and Formats
284
285
6
External Interface (Z8601. Z8611)
Introduction.· • • • • • • • •
Pin Description • • • • • • • •
Configuring for External Memory
External Stacks
Data Memory •
8us Operation •
329
329
330
331
331
331
6.6.1 Address Strobe (AS)
6.6.2 Data Strobe (OS) • •
6.6.3 External Memory Operations
332
332
332
6.7
Shared Bus ••••
6.8 Extended Bus Timing
6.9
Instructioh· Timing
6.10 Reset Conditions
266
4
275
275
276
276
277
277
278
Functional Summary
Processor Flags.
Chapter 6.
6.1
6.2
6.3
6.4
6.5
6.6
Address Modes
333
334
335
338
Chapter 7. External Interface (Z8681, Z8682)
7.1
7.2
7.3
7.4
7.5
7.6
7
Introduction
Pin Descriptions
Configuring Port 0
339
339
340
7.3.1 ZB6B1 Initialization
7.3.2 ZB6B2 Initialization
7.3.3 Readtnrite Operations
340
341
342
External Stacks
Data Memory.
Bus Operation.
342
342
7.6.1 Address Strobe (AS)
7.6.2 Data Strobe (OS)
343
343
7.7 Extended Bus Timing •
7.B Instruction Timing
7.9 ZB6B1 Reset Conditions
7.10 ZB6B2 Reset Conditions
343
343
344
344
344
Ch;ipter 8. Reset and Clock
B.1
B.2
B.3.
B.4
Reset.
•
••
Clock.
•
Power-down Operation
Test Mode •
•
345
346
347
348
B.4.1 Interrupt Testing
8.4.2 ROMless Operation
349
349
Chapter 9.
9.1
9.2
9.3
I/O Ports
Introduction
•
• 350
9.1.1 Mode Registers
9.1.2 Input and Output Registers
·350
·350
Port 0
.350
9.2.1 Read/Write Operations,
9.2.2 Handshake Operation
.352
352
Port 1
9.3.1 Read/Write Operations
9.3.2 Handshake Operation •
353
• 353
·353
267
Table Of COBlenls (Continued)
9.4
Port 2
9.4.1
9.4.2
9.5
9.6
9.7
Read/'~rite
.355
9.5.1 Read/Write Operations
9.5.2 Special Functions
• 355
356
Port Handshake
••
I/O Port Reset Conditions
357
• 358
'10
Interrupts
Introduction • •
Interrupt Sources
361
361
10.2.1 External Interrupt Sources
10.2.2 Internal Interrupt Sources
361
363
363
363
10.3 Interrupt Request Register Logic and Timing
10.4 Interrupt Initialization • • • • •
10.4.1 , Interrupt Priority Register Initialization
10.4.2 Interrupt Mask Register Initialization •
10.4.3 Interrupt Request Register Initialization
364
365
365
IRQ Software Interrupt Generation
Vectored Processing • • • • • • •
365
366
10.6.1' Vectored Interrupt Cycle Timing
10.6.2 Nesting of Vectored Interrupts
366
366
10.7
Polled Processing
366
10.8
Reset Conditions
10.5
10.6
268
9
.354
.354
Operations
Handshake Operation
Port 3
Chapter 10.
10.1
10.2
• 354
. '.
367
Chapter 11.
Counter/T imers
11
.
11.1 Introduction
11.2 Prescalers and Counter/Timers
11.3 Counter/Timer Operation.
369
370
371
.
11.3.1 Load and Enable Count Bits
11.3.2 Prescaler Operations
371
371
372
373
11.4 TOUT Modes.
11.5 TIN Modes.
11.5.1
11.5.2
11.5.3
11.5.4
External Clock Input Mode
Gated Internal Clock Mode
Triggered Input Mode
Retriggerable Input Mode .,
.
11.6 Cascading Counter/Timers.
11.7 Reset Conditions
374
374
376
376
.
376
376
12.1 Introduction
12.2 Bit Rate Generation
12.3 Receiver Operation
378
378
380
12
Chapter 12. Serial I/O
12.3.1
12.3.2
12.3.3
12.3.4
380
381
381
381
Receiver Shift Register
Overwrites'
Framing Errors
Parity
.
381
12.4 Transmitter Operation
12.4.1 Overwrites
12.4.2 Psrity
.
12.5 Reset Conditions
Appendix A.
A.1
A.2
382
382
383
Pin Descriptions and Functions
Development Device (Z8612)
PIotopack Emulator (Z8603/13)
385
385
Appendix B.
Control Registers
387
Appendix C.
Opcode Hap • • • •
390
269
Chapter I
Z8 Family Overview
1.1
INTROOUCTII:t.I
This chapter provide~ an overview of the architecture and features of the Z8 Fainily of products,
with particular emphasis. on those features that
set this microcomputer apart from earlier microcomputers. Detailed information about the architecture, address spaces and. modes, instruction
set, external interface, timing, input/output
operations, and interrupts can be found in subsequent chapters of this manual.
1.2 FEATURES
The Z8 microcomputer introduces a new level of
sophistication to single-chip architecture. Compared to earlier single-chip microcomputers, the
Z8 offers faster execution; more efficient use of
memory; more sophisticated interrupt, input/output
and bit-manipulation capabilities; and easier. system expansion.
Z8 products offer the standard on-chip functions
of earlier microcomputers, including:
•
•
•
•
•
•
2K or 4K bytes of ROM
144 8-bit registers
3.2 li~es of programmable I/O
Clock oscillator
Arithmetic logic unit
Parallel and serial ports
Beyond these basic features, the Z8 Family offers
such advanced characteristics as:
•
•
•
•
•
•
•
•
Two counter/timers
Six vectored interrupts
UART for serial I/O communication
Stack functions
Power-down option
TTL compatibility
Optimized instruction set
BASIC/Debug interpreter
All members of the Z8 Family are variations of the
basic Z8 microcomputer, the Z8601/11.
The Z8
Family includes a development device (Z8612), a
ROMless device (Z8681/82), BASIC/Debug Interpreter
(Z8671), a Protopack emulator (Z8603/13), as well
270
as the basic microcomputer. These products offer.
all the parts and development tools necessary for
systems development (both hardware and software
prototyping), field trials (pre-production) and
fun production. For prototyping and preproduction, or where code flexibility is important, the
Z8603/13 Protopack, 2K and 4K EPROM-based parts
are the most appropriate. The ROM-bssed Z8601/11
microcomputers are used in high-volume production
applications after the softwsre has been perfected. For ROM less applications, two versions of
the Z8 microcomputer are available: the 40-pin
Z8681/82 and the 64-pin Z8612. In addition, there
is a military version of the Z8611 4K ROM device,
available in both 40-pin ceramic and 44-pin lead- .
less chip carrier packages.
The Z8671 MCU is a complete microcomputer preprogrammed with a BASIC/Debug Interpreter.
This
device, operating with both external ROM or RAM
and on-chip memory registers, is suitsble for most
industrial control applications, or whenever fast
and efficient program development is necessary.
The Z8 microcomputer is' well-suited for dedicated
Since
control applications in real-time mode.
speed is a key consideration in such applications,
the Z8 Family is available in both 8 and 12 MHz
versions, supported by either of two development
modules: the Development Module (OM) or the
Z-SCAN 8. The Z-SCAN module provides (ICE) incircuit emulation capability.
1.2.1
Instruction Set
The Z8 imltruction set, consisting of 43 basic
instructions, is optimized for high-code density
and reduced execution time.
The 47 instruction
types and six addressing modes--togetherwith the
ability to operate on bits, 4-bit words, BCD
digits, 8-bit bytes, and 16-bit .words--make for a
code-efficient, flexible microcomputer.
1.2.2 Architecture
Z8 architecture offers more flexibility and performance than previous A/B accumulator designs.
All 128 general-purpose registers, including
20
dedicated I/O port registers, can be used as
accumulators. This eliminates the bottleneck commonly found in A/B devices, particularly in highspeed applications such as disk dri ves, printers
and terminals. In addition, the registers can be
used as address pointers for indirect addressing,
as index registers or for implementing an on-chip
stack. Speed of execution and smooth programming
are supported by a "working register area"--short
4-bit register addresses.
The za cen be a stand-alone microcomputer with
either 2K bytes (ZB601) or 4K bytes (ZB611)of
internal ROM, a treditional microprocessor that
can manage up to 124K bytes (ZB601) or 120K bytes
(ZB611) of external memory, or a parallel processing element in a system ~Iith other processors and
peripheral controllers linked bya Z-BUS. In all
configurations, a large number of device pins are
available for I/O. Key features of the ZB601/11
microcomputer include:
a
il~
:h1-byto (ZiWl1)
CJr
Table 1-1 lists the basic characteristics of the
members of the Z8 Family.
As shown, the major
differences between the products are in their
physical packaging and the manner in which address
space is handled. An overall description for each
Z8 type is given in the following sections.
Variations within each group are specified where
applicable.
a
H/O lines/Ports. The ZB microcomputer provides
32 input/output lines, arranged as 4 B-bit
ports. Under sofblSre control, the I/O ports
(Ports 0, 1, 2, 3) can be programmed as input,
output, or additional address lines. The I/O
ports can also be programmed to provide timing,
status signals, interrupt inputs and serial or
parallel I/O (with or without handshake).
o
InterrL~B.
The ZB MPU permits the
use of six different interrupts from any of
eight different cources.
Four Port 3 lines
(P30-P 33), serial input pin (P30)' the serial
output pin (P37) end both counter/timer
circuits may be interrupt cources.
All
interrupts are vectored end are both maskable
and prioritized.
C!tc-byto (IB611) \'>lrngro
~ry.
This ROM is mask-progrelmned during
production with user-provided programs.
The internal
register organization of the ZB microcomputer
centers around a 144-byte ·file composed of 124
general-purpose registers, 16 status and
control registers, and 4 I/O port registers.
Either an B-bit or a 4-bit address mode can be
used to access the register file.
tlhen the
4-bit mode is used, the register file is
divided into 9 groups of 16 working registers
.each. A Register Pointer uses short-format
instructions to quickly access anyone of the
nine groups. Use of the 4-bit addreSSing mode
decreases access time and improves throughput.
o
PlrIUJlrEZOEhle Counter/T.ir:::ars. Two B-bit· counter/timer circuits are provided, each driven by
its own preacaler. Both the counter/timers and
their prescaler circuits are programmable.
o
UART (Ilniversal Asym:hranous Receiver TrEn!!lilittor).
A full-duplex UART is provided to
control serial data communications. One of the
on-chip counter/timer circuits provides the
required bit rate input to enable the UART to
operate at a maximum data transfer rate of
93.75K bits per second at a crystal frequency
of 12 MHz.
F~ily Overvie~
Vcmtored
o Occillator C~uit. An oscillator circuit that
csn be driven from an external clock or crystal
is provided on the ZB microcomputer.
The
oscillator will accept an input frequency of up
to 12 MHz on the XTAL1 and XTAt2 pins provided.
o
(lptianal Potrer-Do= Feature.
This option
permits normal input potter to be removed from
the chip without affecting the contents of the
register file.
The power-down function
requires an external battery backup system.
Pin functions and descriptions for the ZB601/11
microcomputer can be found in Chapter 6.
A development device allows users to prototype a
system with an actual hardware device and to
develop the code that is eventually mask-programmed into the on-Chip ROM of the ZB601 or Z8611
microcomputer. Oevelopment devices are also useful in applications where production volume does
The
not justify the expense of a Rot~ system.
ZB612 development device is identical to its
equivalent microcomputer, the ZB611, with the f01lowing exceptions:
271
•
No internal ROM is provided, so that code is
developed in an off-chip memory.
•
The normally internal ROM address and data
lines are buffered and brought out to external
pins to interface with the external memory.
•
o The device package is enlarged in order to
accommodate the new control, address, and data
lines.
Pin functions and descriptions for the development
device can b,e found in the Appendix.
Control lines are added to interface with
external program memory.
Table 1-1. ZS Family of Products
Product
Part
Number
ROM
Capacity
(Bytes)
Progr8lllllable
I/O Pins
Dedicated
I/O Pins
PCB
Footprint
CDlllllBnts
2K ROM
Z8601
2K
32, 4 ports
8 Power,
Control
40 Pin
Masked ROM part, uaed
primarily for high volume
production.
2K Protopack
Z8603
0
32, 4 ports
8 Power,
Control
plus
24 EPROM
40 Pin
Piggyback part used where
program flexibility is
required (prototyping).
4K ROM
Z8611
4K
32, 4 ports
8 Power,
Control
40 Pin
Masked ROM part, used
primarily for high volume
production.
4K Oevelopment part
Z8612.
0
32, 4 ports
8 Power,
Control
plus 24
external
memory
64 Pin
ROlHess part used primarily
in development systems.
4K Protopack
ZB613
0
32, 4 ports
8 Power,
Control
. plus
24 EPROM
40 Pin
Piggyback part used where
program flexibility is
required (prototyping) •
BASIC/
Debug
ZB671
2K
32, 4 ports.
8 Power,
Control
40 Pin
BASIC/Debug part used in
low volume applications.
ROM less
ZB681/82
0
24, 3 ports
8 Power,
Control
plus 8
external
memory
40 Pin
Low cost ROM lees production
part with reduced I/O.
Program memory is external.
272
ZB Family Overview
1.5 PROTOPACK Er.:uLATOR (Z8603/n)
1 .7 Rm.a.ESS MICROCOl-IPUTER (Z8681/82)
The Protopack emulator devices, ZB603 and ZB613,
are ROMl,ess versions of their equivalent microcomputers (ZB601 and ZB611, respectively). The emulators differ from development devices in two
ways: they use the same pinout as the microcomputers, and an external ROM or EPROM can be
plugged into the top of the package. The emulator
package allows for flexibility of application,
since it can be used in either prototype or final
pc boards, yet still allows for program develop,ment.
The ZB6B1 and ZB6B2 ROM less microcomputers provide
virtually all of the functions of the standard ZB
microcomputer without the need to mask-program
on-chip ROM. This microcomputer is similar to the
ZB601 version except that there is no on-chip program memory. Unlike the ROMless development and
Protopack devices the ZB681/B2 has no additional
address or address control lines nor does it ,carry
a plug-in piggyback memory module. Use of external memory rather than internal ROM enables this
ZB device to be used in low volume applications or
where code flexibility is required. The use of
Ports 0 and 1 to interface external memory leaves
16 to 24 lines for I/O.
When the final program is developed, it can be
mask-programmed into the ZB601/11 which then
replaces the emulator. The emulator is also useful in small volume applications where the cost of
mask-programming is prohibitive or where program
flexibility is desired.
Physical description for the Protopack emulator is
found in the Appendix.
1.6 BASIC/DEHUG INTERPRETER (Z8671)
The ZB671 MCU is a complete microcomputer preprogrammed with a BASIC/Debug interpreter.
BASIC/
Debug can directly address the ZB671 , s internal
registers and all external memory. It can quickly
examine and modify any external memory location' or
I/O port, and can call machine language subroutjnes to increase execution speed.
The ZB671 MCU has a combination of software and
hardware that is ideal for most industrial' control
'applications. Along with the functions mentioned
above, this microcomputer has a self-contained
line editor for interactive debugging which further speeds program development. In addition the
BASIC/Debug Interpreter allows program execution
on power-up or reset, without operator intervention.
Two kinds of memory exist in the ZB671 device:
on-chip registers and external ROM or RAM. The
BASIC/Debug interpreter is located in the 2K bytes
of on-chip ROM. Maximum addressing capability is
62K bytes of external program memory and .62K bytes
of data memory. In addition, 32 I/O lines, a 144byte register file, on-board UART and two counter/timers are provided.
Pin descriptions and functions are the same as
those for the ZB601/11 basic microcomputer
(Chapter 6).
Since Port 1 is dedicated as an B-bit multiplexed
Address/Data bus, and Port 0 lines can be programmed as address bits, the resulting' 16-bit
addresses can 'directly address up to' 64K bytes of
memory for the ZB6B1 and 62K bytes for the ZB6B2.
(The ZB6B2 MCU cannot address the, lower 2K bytes
of memory).
The address capabllUy of the ZB6B1/B2 can be
doubled by programming output P3 4 of Port 3 as
Data Memory (OM) se lect signal. The two states of
this signal can be used with the 16-bit addresses
to identify two separate external address spaces,
thus increasing external address space to 12BK
bytes for the ZB6B1 and 124K bytes for the ZB,6B2.
Pin functions and descriptions for the ZB6B1/B2
microcomputer ca~ be found in Chapter 7.
1.8
APPLICATI~~S
ZB microcomputers are most often used in high-performance, dedicated applications. Such specialized functions were previously accomplished with
TTL logic, TTL logic plus a low-end MCU, or a
microprocessor and peripherals. Some typical
applications include:
o Disc drive controller
o Printer controller
II
Terminals
o Modems
o Industrial controllers
o Key telephones
o Telephone switching systems
o Arcade games and intelligent home games
o Process control
a Intelligent instrumentation
o Automotive mechanisms
273
ZB Family Overview
Following are brief descriptions for a few ZA
applications.
Printers. Input data (typically transmitted via a
terminal or computer) can be sent to the Z8 on
either a serial or parallel port.
The ZB then
transfers the data into the external RAM buffer
via another parallel port, where it can operate on
the data before output to the printing mechanism.
274
Disk operations are read or write, with
input recehed from either the disk or the computer. Data is transferred to the buffer memory a
sector (12B, 256, 512, 1024 bytes) at a time via
the ZB, operated on as required, and subsequently
output to the disk or computer.
Disk.
Ter.inal. Input is received from either the keyboard or a computer. The ZB device must maintain
at least an input buffer and often the screen RAM.
©lhltm!p>ft
Q
o
"
0
"
TOPOFSTACK
PCl
PCl
PCH
PCH
TOP O F _
STACK
STACK CONTENTS
AFTER A CAll
INSTRUCTION
Figure3-B.
FLAGS
STACK CONTENTS
AFTER AN
INTERRUPT
CYCLE
Stack Operations
283
Chapter 4
Address Modes
4.1
The Z8
modes:
•
•
•
•
•
•
Pointer (R253) with the 4-bit working register
address supplied by the instruction.
INTRODUCTION
microcomputer
prov ides
six
addressing
Registers can be
values or memory
be specified as
range 0, 2, •••• ,
Register (R)
Indirect Register (IR)
Indexed (X)
Direct (D)
Relative (RA)
Immediate (H1)
used in pairs to designate 16-bit
addresses. A register pair must
an even-numbered address in the
14.
modes
are
instruction-specific.
Addressing
Sect ion 5.4 discusses each addressing mode as it
corresponds to particular instructions.
With the exception of immediate data and condition
codes, all operands are expressed as register
file, program memory, or data memory addresses.
Registers are accessed using 8-bit addresses in
the range 0-127 and 240-255.
In the following definitions,
the use of
"register" also implies register pair, working
register, or working register pair.
4.2 REGISTER ADDRESSING (R)
Working registers are accessed using 4-bit
addresses in the range 0-15. The address of the
register being accessed is formed by the concatenation of the upper four bits in the Register
In the Register "ddres'sing mode, the operand value
is the contents of the specified register or
register pair (Figures 4-1 and 4-2).
REGISTER FILE
PROGRAM MEMORY
8·BIT REGISTER
FILE ADDRESS
"
dst
OPCODE
.;
ONE·OPERAND
INSTRUCTION
EXAMPLE
OPERAND
POINTS TO ONE REGISTER
IN REGISTER FILE
#
/
VALUE USED IN
/
INSTRUCTION EXECUTION
Figure 4-1.
Register Addressing
REGISTER FILE
RP
PROGRAM MEMORY
4·BIT WORKING
REGISTER
,
TWO·OPERAND
INSTRUCTION
EXAMPLE
dst
J
,
I
OPCODE
sre
,
POINTS TO THE
WORKING REGISTER
Figure 4-2.
284
OPERAND
Working-Register Addressing
.
POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP
Address Modes
4.3
4.4
IMlIRECT REGISTER ADDRESSII'£ (IR)
In the Indirect Register addressing mode, the contents of the specified register is the address of
the operand (Figures 4-3 and 4-4).
Depending upon the instruction selected, the
address points to a register, program memory, or
an external data memory location.
IMlEXED ADDRESSING (X)
The Indexed addressing mode is used only by the
Load (LD) instruction. An indexed address consists
of a register address offset by the contents of a
designated working register (the Index).
This
offset is added to the register address to obtain
the address of the operand.
Figure 4-5 illustrates this addressing convention.
When accessing program memory or external data
memory, register pairs or working register pairs
are used to hold the 16-bit addresses.
REGISTER FILE
PROGRAM MEMORY
8·BIT REGISTER
FILE ADDRESS
dst
OPCODE
ONE·OPERAND
INSTRUCTION
EXAMPLE
POINTS TO ONE REGISTER
IN REGISTER FILE
ADDRESS OF
OPERAND USED
BY INSTRUCTION
OPERAND
VALUE USED IN
INTRODUCTION
EXECUTION
Figure 4-3.
Figure 4-4.
Indirect Register Addressing to Register File
Indirect Register Addressing to Program or Data Memory
285
Address Modes
4.5 DIRECT ADDRESSING (DAr
The Direct addressing mode, as shown in Figure
4,..6, specifies the address of the next instruction
to be executed. Only the Conditional Jump (JP)
and Call (CALL) instructions use this addressing
mode.
two's,..complement signed displacement in the range
of -128 to +127. This is added to the contents of
the PC to obtain the address of the next
instruction to be executed. The PC (prior to the
add) consists of the address of the instruction
following the Jump Relative (JR) or Decrement and
Jump if Nonzero (DJNZ) instruction. JR and DJNZ
are the only instructions that use this addressing
mode.
4.6 RELATIVE ADDRESSING (RA)
In the Relative addressing mode, illustrated in
Figure
4-7,
the
instruction
specifies
a
RP
PROGRAM MEMORY
POINTS TO
TWO·OPERAND
INSTRUCTION-~t=~~~~~~~~--~lJK~noON~~~~~t~~~~~==~
EXAMPLE
ORIGIN OF
WORKING
REGISTER
GROUP
OPERAND
VALUE USED IN
INSTRUCTION
Figure 4-5.
Indexed Addressing
PROGRAM MEMORY
PROGRAM MEMORY
PROGRAM MEMORY
ADDRESS USED
PROGRAM MEMORY
ADDRESS USED
NEXT OPCODE
DISPLACEMENT
LOWER ADDR BYTE
JRORDJNZ_
UPPER ADDR BYTE
OPCODE
OPCODE
Figure 4-6.
286
Direct Addressing
Figure 4-7.
SIGNED
DISPLACEMENT
VALUE
Relative Addressing
4.7
IMMEDIATE DATA ADDRESSING (1M)
Immediate data is considered an "addressing mode"
for the purposes of this discussion. It is the
only addressing mode that does not indicate a register or memory address as the source operand; the
operand value used by the instruction is the value
supplied in the operand field itself. Because an
immediate operand is part of the instruction, it
is always located in the program memory address
space.
WORD(S)
THE OPERAND VALUE IS IN THE INSTRUCTION.
figure 4-8.
Immediate Data Addressing
287
Chapter 5
Instruction Set
5.1
fUNCTIONAL SUMMARY
ZB instructions can be divided functionally into
the following eight groups:
•
•
•
•
•
D
•
•
Load
Arithmetic
Logical
Program Control
Bit Manipulation
Block Transfer
Rotate and Shift
CPU Control
Logical Instructions
Mnemonic
AND
COM
OR
XOR
Operands
dst,src
dst
dst,src
dst,src
Ins~ruction
Logical And
Complement
Logical Or
Logical Exclusive Or
Program-Control Instructions
The following summary shows the instructions
belonging to each group and the number of operands
required for each. The source operand is "src",
"dst" is the destination operand, and "cc" is a
condit ion code.
Mnemonic
CALL
DJNZ
IRET
JP
JR
RET
Operands
dst
r,dst
cc,dst
cc,dst
Instruction
Call Procedure
Decrement and Jump NonO
Interrupt Return
Jump
Jump Relative
Return
Bit-Manipulation Instructions
load Instructions
Mnemonic
CLR
LD
LDC
LDE
POP
PUSH
Operands
dst
dst,src
dst,src
dst,src
dst
src
Instruction
Clear
Load
Load Constant
Load External
Pop
Push
Mnemonic
TCM
TM
AND
OR
XDR
Operands
dst,src
dst,src
dst,src
dst,src
dst,src
Instruction
Test Complement Under Mask
Test Under Mask
Bit Clear
Bit Set
Bit Complement
Block-Transfer Instructions
Arithmetic Instructions
Mnemonic
ADC
ADD
CP
DA
DEC
DECW
INC
INCW
SBC
SUB
288
Operands
dst,src
dst,src
dst,src
dst
dst
dst
dst
dst
dst,src
dst,src
Instruction
Add With Carry
Add
Compare
Decimal Adjust
Decrement
Decrement Word
Increment
Increment Word
Subtract With Carry
Subtract
Mnemonic
LOCI
LDEI
Operands
dst,src
dst,src
Instruction
Load Constant Autoincrement
Load External Autoincrement
Rotate and Shi ft Instructions
Mnemonic
RL
RLC
RR
RRC
SRA
SWAP
Operands
dsl
dst
dst
dst
dst
dst
Instruction
Rotate Left
Rotate Left Through Carry
Rotate Right
Rotate Right ThroughCBrry
Shift Right Arithmetic
Swap Nibbles
Instruction Set
CPU Control Instructions
Mnemonic
CCF
DI
EI
NOP
RCF
SCF
SRP
Operand
Instruction
Complement Carry Flag
Disable Interrupts
Enable Interrupts
No Operation
Reset Carry Flag
Set Carry Flag
Set Register Pointer
src
5.2.1
Carry flag (C)
The Carry flag is set to 1 whenever the result of
an arithmet ic operation generates a carry out of
or a borrow into the high order bit 7; otherwise,
the Carry flag is cleared to O.
Following Rotate and Shift instructions, the Carry
flag contains the last value shifted out of the
specified register.
An instruction can set, reset, or complement the
Carry flag.
5.2 PROCESSOR flAGS
The Flag register (R252) informs the user about
the current' status of the ZB. The flags and their
bit positions in the Flag register are shown in
Figure 5-1.
RETI changes the value of the Carry flag when the
saved Flag register is restored.
5.2.2 Zero flag (Z)
R252 FLAGS
Flag Register
For arithmetic an,d logical operations, the Zero
flag is set to 1 if the result is zero; otherwise,
the Zero flag is cleared.
(FCH; Read/Write)
LuSER FLAG F1
l§~
If the result of testing bits in a register is 0,
the Zero flag is set to 1; otherwise the flag is
cleared.
LUSER FLAG F2
,
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
If the result of a Rotate or Shift operation is 0,
the Zero flag is set to 1; otherwise, the flag is
cleared.
L - - - - - - - - S I G N FLAG
~--------ZEROFLAG
~----------CARRYFLAG
Figure 5-1.
Hag Register
The ZB Flag register contains six bits of status
information which are set or cleared by CPU operations. Four of the bit.s (C, V, Z and S) can be
tested for use with conditional Jump instructions. Two flags (H, D) cannot be tested and are
used for BCD arithmetic.
The two remaining bits in the Flag register (F1,
F2) are' available to the user, but they must be
set or cleared by instruction and are not usable
with conditional Jumps.
As with bits in the other control registers, Flag
register bits can be set or reset by instructions;
however, only those instructions that do not
affect the flags as an outcome of the execution,
should be used (e.g., load Immediate).
RET! changes the value of the Zero flag when the
saved Flag register is restored.
5.2.3 Sign flag (S)
The Sign flag stores the value of the most significant bit of a result following arithmetic, logical, Rotate, or Shift operatIons.
When performing arithmet ic ope rat ions ,on signed
numbers, binary two's complement notation is used
to represent and process information. A positive
number is identified by a 0 in the most significant bit positIon, and therefore, the Sign flag is
also O.
A negative number is identified by a 1 in the most
significant bit pO,sition, and therefore, the Sign
flag is also 1.
RETI changes the value of the Zero flag when the
saved Flag register is restored.
289
Instruction Set
5.2.4 Overflow Flag (V)
For signed arithmetic, Rotate, and Shift operations, the Overflow flag is set to 1 when the
result is greater than the maximum possible number
( > 127) or less than the minimum possible number
( < -128) that can be represented in two's complement form.
The flag is set to 0 if no overflow
occurs.
Following logical operations, the Overflow flag is
set to O.
REf I changes the value of the Overflow flag when
the saved Flag register is restored.
encoded in a 4-bit field called the condition code
(CC), which forms bits 4-7 of the conditional
oinstructions.
Section 5.4.2 lists the condition codes and the
flag settings they represent.
5.4 NOTATION AM> BINARY ENCODING
In the detailed instruction descriptions that make
up the rest of this chapter, operands and status
flags are represented by a notational shorthand.
Operands (condition codes and address modes) and
their notations are as follows:
Notation Address Hade
Actual Operand/Range
5.2.5 Decimal-Adjust Flag (D)
The Decimal-adjust flag is used for BCD arithmetic.
Since the algorithm for correcting BCD
operations is different for addition and subtraction, this flag specifies what type of instruction
was last executed so that the subsequent Decimal
Adjust (DA) operation can function properly. Normally, the Decimal-adjust flag cannot be used as a
test condition.
After a subtraction, the Decimal-adjust flag iso
set to 1; following an addition it is cleared to
O.
cc
Condition Code
See condition code
list below
r
Working register
only
Rn: where n
R
Register or
working register
reg: where reg represents a number in the
range 0-127, 240-255
Rn: where n
RR
RETI changes the value of the Decimal-adjust flag
when the saved Flag register is restored.
5.2.6
Register pair or
working register
pair
0-15
= 0-15
reg: where reg represents an even number
in the range 0-126,
240-254
RRp: where p
2, ••• ,14
Half-Carry Flag (H)
0,
The Hal f-carry flag is set to 1 whenever an addition generates a carry out of bit 3 (Overflow), or
a subtraction generates a borrow into bit 3. The
Half-carry flag is used by the Decimal Adjust (DA)
instruction to convert the binary result of a prev ious addit ion Or subtract ion into the correct
decimal (BCD) resul t. As in the case of the
Decimal-adjust flag, the user does not normally
access this flag.
Ir
Indirect working
register only
@ Rn: where n
IR
Indirect register
or working
register
@ reg: where reg re-
RETI changes the value of the Half-carry flag when
the saved Flag register is restored.
Irr
5.3 CONDITION CODES
IRR
0
Flags C, Z, S, and V control the operation of the
"conditional" Jump instructions.
Sixteen frequently useful functions of the flag settings are
presents a number in
the range 0-127"
240-255
@ Rn: where n
Indirect working
register pair
only
0-15
= 0-15
@ RRp: where p
Indirect register ® reg: where reg repair or working
sents an even number
register pair
in the range 0-126,
240-254
® RRp: where p
2, ••• ,14
290
= 0,
2, ••• ,14
0,
Instruction Set
!
Notation Address Mode
Actual Operand/Range
5.4.1
For proper instruction execution, ZB PLZ/ASM
assembly language syntax requires that "dst, src"
be specified, in that order.
The following
instruction descriptions show the format of the
object code produced by the assembler. This binary
format should be followed by users who prefer
manual program coding or who intend to implement
their own assembler.
x
Indexed
reg (Rn): where reg
represent a number in
the range 0-127,
240-255 and n = 0-15
DA
Direct Address
addrs: where addrs
represents a number
in the range 0-65,535
RA
Relative Address
addrs: where addrs
represents a number
in the range +127,
-128 which is an
offset relative to
the address of the
next instruction
1M
Immediate
Iidata: where data is
a number between
o and 255
Additional symbols used are: '
Symbol
dst
src
Meaning
Destination operand
Source operand
Indirect address prefix
®
SP
PC
FLAGS
RP
IMR
II
Stack Pointer
Program Counter
Flag register (R252)
Register Pointer (R253)
Interrupt mask register (251)
Immediate operand prefix
%
OPC
Hexadecimal number prefix
Opcode
Assignment of a value is indicated by the symbol
"<-". For example,
dst
<- dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location.
The notation "addr(n)" is
used to refer to bit "n" of a given location. For
example,
Assembly Language Syntax
Example: If the contents of registers %43 and ~~OB
are added and the result stored in ~~43, the
assembly syntax and resulting object code are:
ASM:
OBJ:
ADD
04
(ADD dst, src)
(OPC src, dst)
%43, %08
08
43
In general, whenever an instruction format
requires an! 8-bit register address, that address
can speci fy any register location in the range
0-127, 240-255 or a working register RD-R15. If,
in the above example, register %08 is a working
register, the assembly syntax and resulting object
code would be:
ASM:
OBJ:
ADD
04
%43, RB
E8
43
(ADD dst src)
(OPC src dst)
For a more complete description of assembler syntax' refer to the Z8 PLZ/ASM Assembly Language
Manual (publication no. 03-3023-03) and ZSCAN B
User's Tutorial (publication no. 03-B200-01).
5.4.2 Condition Codes and Flag Settings
The condition codes and flag settings are summarized in the following tables. Notation for the
flags and how they are affected are as follows:
C
Z
S
Cany flag
Zero flag
Sign flag
V
0
Overflow flag
Decimal-adjust flag
Half-carry flag
H
0
1
*
X
Cleared to 0
Set to 1
Set or cleared
according to
operation
Unaffected
Undefined
dst (7)
refers to bit 7 of the destination operand.
291
Coodition Codes
Binary
0000
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
292
Mnellllllic
F
(blank)
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
0001
1010
0010
1111
LT
GT
LE
UGE
0111
1011
0011
ULT
UGT
LJLE
Meaning
Hags Settings
Always false
Always true
Carry
No carry
Zero
Not iJ
Plus
Minus
Overflow
No overflow
Equal
Not equal
Gre~ter than or
equal
Less than
Greater Than
Less than or equal
Unsigned greater than
or equal
Unsigned less than
Unsigned greater than
Unsigned less than or
equal
C=1
C=0
Z=1
Z=0
S =0
S = "1
V= 1
V=0
Z=1
Z=0
(S XOR V) = 0
(S XORV) = 1
(Z OR (S XOR V»=O
(Z OR (S XOR V»=1
C=0
C= 1
(C=O AND Z=O) =
(C OR Z) = 1
Instruction
and Operation
AddrMode
clst
IIrC
Opcode Flags Affected
Byte
(Hex)
CZSVDH
Instruction
and Operation
Addr Mode
clst
arc
Opcode Flag. Affected
Byte
(Hex)
CZSVDH
(No!e'l)
ID
...... 0 *
LDE ds!,src
dst - src
r
Irr
Irr
82
92
------
(No!e I)
00
.. '" .... 0 *
Irr
Ir
83
93
------
(No!e I)
50
0--
LDEI ds!,src
Ir
dst - src
Irr
r - r + 1; rr-rr+l
CALL ds!
DA
SP-SP-2
IRR
@SP - PC; PC - ds!
D6
D4
------
OR ds!,src
CCF
EF
*-----
POP ds!
ds! - @SP
SP-SP+I
ADC ds!,src
ds! - ds! + src +'C
ADD ds!,src
ds! - dB! + src
AND ds!,Brc
ds! - ds! AND src
C - NOTC
CLR ds!
R
IR
BO
BI
ds! - NOT ds!
R
JR
60
61
CP ds!,src
(No!e I)
AD
ds! - 0
COM ds!
0--
40
41
***x--
DEC ds!
ds! - ds!- I
R
JR
00
OJ
- * * * --
DECW ds!
ds!-ds!-I
RR
IR
80
81
- **
8F
------
*--
IMR (7) - 0
RA
rA
r=O-F
-- --
-.-
------***--
R
IR
rE
r=O-F
20
21
CF
0-----
AF
------
0~ JR
R
90
91
****--
RLCds!~I~
JO
II
lEIlc::::3-1 I~
EO
EI
RRCds!~I~
CO
CI
SBC ds!,src
30
R
JR
RCF
C-O
RL ds!
RR ds!
(No!e I)
.
• I
dst - dst-src-C
RR
JR
AO
AI
1EI~1~
DF
I - - -
DO
DI
.... '" 0
JP cc,ds!
if cc is true
DA
PC - ds!
IRR
RA
31
------
LD ds!,src
r
R
r
X
r
Ir
R
R
R
IR
1M
R
X
r
Ir
r
R
IR
IR
1M
1M
R
r
Irr
Irr
Ir
Irr
r-r+l; rr-rr+ 1
Irr
Ir
(No!e I)
•• I
20
dst - ds! - src
SWAP dst ~ R
,
TCM ds!,src
(NOT dst) AND src
TM ds!,src
FO
FI
X • • X
I)
60
-
• • 0
(Note I)
70
-
• • 0
(Note I)
BO
JR
(Note
dst AND src
cD
c=O-F
30
------
cB
c=O-F
------
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
'E7
F5
------
C2
D2
------
C3
D3
------
XOR'ds!,src
.
• 0 - -
dst - ds! XOR src
Note 1
Thes~ instructions have a'n identical set of addressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
PC-PC+ds!
Range: + 127, - 128
dst - src
1m
RP - src
SUB dst,src
BF
FLAGS -@SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR (7) -I
LDCI ds!,src
dst - src
------
SRP src
mET
LDC ds!,src
ds! - src
70
71
SRA ds!
9F
INC ds!
ds!-ds!+1
if cc is true,
------
SCF
IMR(7) - I
JR cc,dst
50
51
C - I
EI
INCW dst
ds! - cis! +
R
JR
ds! - ds! OR src
PC - @SP; SP - SP + 2
R
IR
r - r- I
ifr ;<0
PC-PC+dst
Range: + 127, -128
-**0--
RET
DA ds!
ds! - DA ds!
DJNZ r,ds!
------
40
PUSH src
SP-SP-I; @SP-src
ds! - src
DI
FF
(No!e I)
NOP
second nibble is expressed symbolically by a
L:
in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, to determine the opcode of an ADC
instruction using the addressing modes r (destination) and
Ir (source) is 13.
Addr Mode
dBt
src
R
R
R
IR
Ir
R
IR
1M
1M
Lower
Opcode Nibble
:,
d:
~
:I
:I
:I
293
5.6 Z8
ADC
Instruction
Descriptions
and Formats
AIlC
Add With Carry
dst,src
OPe
Instruction foraat:
I
I
I
OPC
OPC
OPC
Operation:
Cycles
II
II
II
dst
arc
arc
dst
I
II
II
6
dst
10
arc
10
Address Hode
dst
arc
13
r
r
r
Ir
14
15
R
R
R
IR
16
R
IR
1M
1M,
(Hex)
12
17
dst <-- dst + arc + c
The aource operand, along with the aetting of the C flag, is added to the destination
operand and the sum is stored in the destination. The contents of the source are not
affected. Two's complement addition ia performed. In multiple precision arithmetic,
this instruction permits the carry from the addition of low-order operands to be
carried into the addition of high-order operands.
c:
flags:
Set if there is a carry from the most-significant bit of the result; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign,
and the result is of the opposite sign; cleared otherwise
D: Always cleared
H: Set i f there is a carry from the mo'st-significant bit of the low-order four bits
of the result; cleared otherwise
Example:
If the register named SUM contains %16, the C flag is set to 1, working register 10
contains %20 (32 decimal), and register 32 contains %10, the statement
AOC SUM,aR10
leaves the value %27 in Register SUMo
The C, Z, S, V, 0, and H flags are all
cleared.
Note:
When used to apeci fy a 4-bit working-register address,' address modes R or I R use the
format:
E
294
,src/dst
ADD
Add
ADD
dst,src
Instruction foraat:
I
oPc
I
ope
I
ope
Operation:
II
II
II
dst
src
src
dst
I
II
II
OPc
Address Hade
dst src
Cyclss
(lfex)
6
02
03
r
r
r
Ir
dst
10
04
05
R
R
R
IR
src
10
06
07
R
IR
1M
1M
dst <-- dst + src
The source opersnd is added to the destination operand and the sum is stored in the
destination. The contents of the source are not· sffected. Two's complement addition
is performed.
flsgs:
C:
Z:
V:
S:
H:
0:
EXlIIIIPle :
Set if there was a carry from the most-significant bit of the result; cleared
otherwise
Set if the result is zero; cleared otherwise
Set if arithmetic overflow occurs, that is, if both opersnds are of the same sign
and the result is of the opposite sign; cleared otherwise
Set if the result is negstive; cleared otherwise
Set if a carry from the low-order nibble occurs
Always reset to 0
If the register named SUM contains %44 and the register named AUGEND contains %11,
,the statement
, ADD SUM,AUGEND
leaves the value %55 in register SUM and leaves all flags cleared.
Note:
When used to specify a 4-bit working-registar address, address modes R or IR use the
format:
E
src/dst
295
AND
Logical
AN>
dst,src
Instruction for.at:
III'C
Cycles
OPC
II
OPC
II
II
oPC
Operation:
dst
src
src
dst
I
II
II
(Hex)
Address Mode
dst src
6
52
53
r
r
r
IR
dst
10
54
55
R
R
R
IR
src
10
56
57
R
IR
1M
1M
dst <-- dst AND src
The source operand is logically ANDed with the destination operand. The result is
stored in the destination.
The AND operation results in a 1 bit being stored
whenever the corresponding bits in the two opersnds sre both 1s; otherwise a 0 bit is
stored. The contents of the source bit are not affected.
flags:
C:
Unaffected
Z: Set if the result is zero; cleared 'otherwise
V: Always reset to 0
S:
Set if the result bit 7 is set; cleared otherwise
0:
Unaffected
H: Unaffected
Example:
If the source operand is the immediate value %78 (01111011) and the register named
TARGET contains %C3 (11000011), the statement
AND TARGET, #%78
leaves the value %43 (01000011) in register TARGET.
cleared.
Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
296
The Z, V, and 5 flags are
src/dst
CALL
Call Procedure
CAlL dst
Instruction Format:
OPC
Cycles
_______________
~I______
~
~_____O_P_C______~II~
O_PC______~I
L -_____
Operstion:
d_s_t______________~
d_s_t____
(Hex)
Address Mode
dst
20
06
OA
20
04
IRR
SP <-- SP - 2
SSP <-- PC
PC <-- dst
The current contents of the PC are pushed onto the top of the stack. The PC value
is the address of the first instruction following the CALL instruction.
The
speci fied destination address is then loaded into the PC and points to the first
instruction of a procedure.
At the end of the procedure a RETurn instruction can be used to return to the
original program flow. RET pops the top of the stack back into the PC.
Hags:
No flags sffected.
Example:
If the contents of the PC are %lA47 snd the contents of the SP (control registers
254-5) are %3002, the statement
CALL %3521
causes the SP to be decremented to %3000, %1A4A (the address following the
instruction) is stored in external data memory %3000-%3001, and the PC is loaded with
%3521. The PC now points to the address of the first statement in the procedure to
be executed.
Note:
When used to specify a 4-bit working-register pair address, address mode IRR uses the
format:
E
dst
297
CCF
Complement Carry Flag
CCf
Instruction Fomat:
OPC
Cyclea
OPC
Operation:
6
(Hex)
EF
C <- NOT C
The C flag is cbmplemented; if C = 1, it ia changed to C = 0, and vice-versa.
Flags:
C:
Complemented
No other flags affected
EXlIIIPle:
Tf the C flag contains a, 0, the statement
CCF
will change the 0 to 1.
298
ClR
Clear
CLR
dst
OPC
Instruction Format:
Cycles
-J11
~_____O_p_C____
Operation:
-J
6
L ______d_s_t____
(Hex)
BO
B1
Address I-lode
dst
R
IR
dst <-- 0
The destination location is cleared to O.
Flags:
No flags affected.
EXSlIlple:
If working register 6 contains %AF, the statement
CLR R6
will leave the value 0 in that register
Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
dst
299
COM
Complement
COM
dst
Instruction
r onult:
OPC
Cycles
~_____O_P_C______~I ~I
Operation:
______d_s_t______~
6
(Hex)
Address Mode
dst
60
R
61
IR
. dst <-- NOT dst
The contents of the destination location are complemented (one's complement); all 1
bits are changed to 0, and vice-versa.
nags:
C:
Z:
V:
S:
H:
D:
EXlllllple:
Unaffected
Set if the result is zero; cleared otherwise
Always reset to 0
Set if result bit 7 is set; cleared otherwise
Unaffected
Unaffected
If working register B contains %24 (00100100), the statement
COM RB
leaves the value %DB (11011011) in that register.
the 5 flag is set.
Note:
When used to specify a 4-bit working-register sddress, address modes R or IR use the
format:
E
300
The Z and V flags are cleared and
dst
CP
Compare
CP
dst,src
Instruction Foraat:
OPC
OPC
OPC
Operation:
II'C
II
II
II
dst
src
src
dst
I
II
II
dst
(Hex)
6
A2
A3
r
r
r
Ir
10
A4
R
R
R
IR
R
IR
1M
1M
A5
src
Address Mode
dat arc
Cycles
10
A6
A7
dst - src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags set accordingly. The contents of both operands are unaffected by
the comparison.
Flags:
C:
Z:
V:
S:
H:
0:
Exaq>le:
Cleared i f there is a carry from the most significant bit of the result; set
otherwise, indicating a "borrow"
Set if the result is zero; cleared otherwise
Set if arithmetic overflow o'ccurs; cleared otherwise
Set if the result is negative; cleared otherwise
Unaffected
Unaffected
If the register named TEST contains %63, working register 0 contains %30 (4B
decimal), and register 4B contains %63, the statement
CP TEST, IIIRO
sets (only) the Z flag.
jump is taken.
Note:
If this statement is followed by "JP EQ, true_routine", the
When used to specify a 4-bit working-register addreas, address modes R or IR use the
format:
E
src/dst
301
DA
Decimal Adjust
DA
dst
Instruction forDBt:
~_____O_P_C______~1 I~______d_s_t______~
Operation:
(Hex)
Address Mode
dst
40
R
OPC
Cycles
B
IR
41
dst <-- DA dst
The destination operand is adjusted to form two 4-bit BCD digits following a binary
addition or subtraction operation on BCD encoded bytes. for addition (ADD, ADC), or
subtraction (SUB, SBC), the following table indicates the operation performed:
Instruction
Carry
Before DA
ADD
ADC
0
0
0
0
0
0
1
1
1
SUB
SBC
0
0
1
1
Bits 4-7
Value
(Hex)
H Flag
Before DA
0-9
O-B
0-9
A-f
9-f
A-f
0-2
0-2
0-3
0
0
0-9
O-B
7-F
6-f
0
1
0
0
1
0
0
1
1
0
1
Bits 0-3
Value
(Hex)
NUllber
Added
To Byte
Carry
After DA
0-9
A-f
0-3
0-9
A-f
0-3
0-9
A-f
0-3
00
06
06
60
66
66
60
66
66
0
0
0
0-9
6-f
0-9
6-f
00
fA
AO
9A
0
0
1
1
1
1
1
1
1
1
If the destination operand is not the result of a valid addition or subtrsction of
BCD digits, the operation is undefined.
Flags:
C:
Z
V
S
H
D
302
Set i f there is a carry from the most significant bit; cleared otherwise (see
t able above)
Set if the result is 0; cleared otherwise
Undefined
Set if the result bit 7 is set; cleared .otherwise
Unaffected
Unaffected
EXlllllple:
If addition is performed using the BCD values 15 and 27, the result should be 42.
The sum is incorrect, however, when the binary representations are added in the
destination location using sta~dard·binary arithmetic.
0001
+ 0010
0101
0111
li!fiT IT!lli = \\I3C
The DA statement adjusts this result .ao that the correct BCD representation is
obtained.
0011
+ 0000
1100
0110
lJ'I1m l!U'f'O
42
The C, Z, and 5 flags are cleared and V ia undefined.
I
Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
'dst
303
DEC
Decrement
DEC
dst
Instruction For.st:
~_____O_P_C____~1 ~I
Operation :
oPe
Cycles
(Hax)
6
00
01
______
d_s_t____~
Address Mode
dst
R
IR
dst <-- dst - 1
The destinstion 'operand's contents sre decremented by one.
Flags:
Unsffected
Set if the result is zero; clesred otherwise
Set if arithmetic overflow occurred; cleared otherwise
Set if the result is negative; cleared otherwise
Unaffected
0: Unaffected
EXSllPle,:
If working register 10 contains
C:
Z:
V:
5:
H:
~2A,
the ststement
DEC R10,
leaves the value
Note:
~29
in that register.
When used to specify a 4-bit working-register address, address modes ,R or IR use the
format:
E
304
The Z, V, and S flags are cleared.
dst
IOECW
Decrement Word
DEDI dst
Instruction FOrQat:
~_____O_P_C______~I I~
Operation:
dst
______d_s_t______~
OPC
Addresa Mode
Cycles
(Hex)
dat
10
80
RR
IR
81
<-- dst - 1
The contents of the destination location (which rust be an even address) and the
operand following that location are treated as a single 16-bit value which ia
decremented by one.
Flaga:
C:
Z:
V:
S:
H:
D:
Example:
If working register 0 contains %30 (48 decimal) snd registers 48-49 contain the value
%fAf3, the statement
Unaffected_
Set if the result is zero; cleared otherwise
Set if srithmetic ovsrflow occurred; cleared otherwise
Set if the result is negative; cleared otherwise
Unaffected
Unaffected
OECW ORO
leaves the value %fAf2 in registers 48 and 49.
is set.
The Z and V flags are cleared and S
305
01
Disable Interrupts
DI
Instruction For.at:
Cycles
ope
Operation:
6
IMR (7)
<--
OPC
(Hex)
SF
0
Bit 7 of control register 251 (the Interrupt Mask Register) is reset to O.
All
interrupts are disabled, although they remain potentially enabled (i.e., the Global
Interrupt Enable is cleared--not the individual interrupt level enables.)
Flags:
No flags affected
EXBIIPle:
If control register 251 contains %SA (10001010, that is, interrupts IRQ1 and IRQ3 are
enabled), the statement
DI
sets control register 251 to %OA and disables these interrupts.
306
DJNZ
Decrement and Jump if Nonzero
DJNZ r,dst
OPC
Instruction format:
Cycles
~__r__~~_o_p_C__~1 ~I
______
d_s_t______~
(Hex)
12 if jump taken
10 if jump not taken
rA
Address Mode
dst
RA
r=Oto F
Operation:
r (-- r - 1
If r
F 0,
PC (-- PC + dst
The working register being used as a counter is decremented. If the contents of the
register are not zero after decrementing, the relative address is added to the
Program Counter (PC) and control passes to the statement whose address is now in the
PC. The range of the relative address is +127, -12B, and the original value of the
PC is the address of the instruction byte following the DJNZ statement. When the
working register counter reaches zero, control falls through to the statement
following DJNZ.
flags:
No flags affected
Exemple:
DJNZ is typically used to control a "loop" of instructions. In this example, 12
bytes are moved -from one buffer area in the register file to snother. The steps
involved are:
o load 12 into the counter (working register '6)
o Set up the loop to perform the moves
o End the loop with DJNZ
lD R6, 1112
lOOP: lD R9,OlDBUF (R6)
lD NEWBUF (R6),R9
DJNZ R6, lOOP
Note:
!load Counter!
!Move one byte to!
! New location!
!Decrement and !
!loop until counter
O!
The working register being used as a counter must be one of the registers 04-7F.
Use of one of the I/O ports, control or peripheral registers will have undefined
results.
307
EI
Enable Interrupts
EI
Instruction for.at:
Cycles
6
OPC
Operstion:
IMR (7)
OPC
(Hex)
9F
<-- 1
Bit 7 of control register 251 (the Interrupt Mask Register) is set 10 to 10
allows any potentially enabled interrupts to become enabled.
This
flags:
No flags sffected
EXBllple:
If control register 251 contains \'GOA (00001010, that is, interrupts IRQ1 snd IRQ3
potentislly enabled), the statement
EI
sets control register 251 to \'GSA (10001010) and enables these interrupts.
308
INC
Increment
INC
dst
Instruction Format:
OPC
Cycles
dst
OPC
6
~_____O_P_C______~I ~I
Operation:
______
dst <-- dst
d_s_t______~
6
(Hex)
Address Mode
dst
rE
r=O to F
20
21
r
R
IR
+ 1
The destination operand's contents are incremented by one.
Flags:
C:
Unaffected
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurred; cleared otherwise
5:
H:
0:
[xmmple:
Set if the result is negative; cleared otherwise
Unaffected
Unaffected
If working register 10 contains %2A, the statement
INC R10
leaves the value %29 in that register.
Note:
The Z, V, and S flags are cleared.
When used to specify a 4-bit working-register address, address modes R or IRuse the
format:
E
dst
309
INew
Increment Word
It«:W dst
Instruction format:
OPC
Cycles
~~_op_e__~11~
Operstion:
dst
____
<-- dst
ds_t__~1
(Hex)
AO
10
A1
Address Mode
dst
RR
IR
+
The contents of the destination (which must be an even address) and the byte
following that location are treated as a single 16-bit value which is incremented by
one.
Hsgs:
C:
Z:
V:
S:
H:
0:
EXBqlle:
Unaffected
Set if the reault is zero; cleared otherwise
Set if arithmetic overflow occurred; cleared otherwise
Set if the result is negative; cleared otherwise
Unaffected
Unaffected
If working-register pair 0-1 contains the value %FAF3, the statement
!New RRO
leaves the value %FAF4 in working-register pair 0-1.
and S is set.
310
The Z and V flags are cleared
IRET
Interrupt Return
IRET
Instruction Format:
OPC
Cycles
OPC
Operstion:
16
(Hex)
SF
FLAGS <-- asp
SP
PC
SP
<-- SP + 1
<-- asp
<--
SP + 2
IMR (7) <-- 1
This instruction is issued at the end of an interrupt service routine. It restores
the Flag register (control register 252) and the PC.
It also reenables any
interrupts that are potentially enabled.
Flags:
All flags are restored to original settings (before interrupt occurred).
311
JP
Jump
JP
cc,dst
Instruction For.at:
Cyclea
Conditional
~_c_c__~~_O_p_C__~1 I~
___________
12 if jump taken
10 if jump not taken
d_st__________- J
Addreaa Mode
dat
ccO
OA
cc=O to F
Unconditional
~_____O_P_C______~1 IL______d_s_t______~
Operation:
OPC
(Hex)
If cc is true, PC
<-~
8
30
IRR
dst
A conditional jump transfers Progrsm Control to the destination address i f the
condition specified by "cc" is true; otherwise, the instruction following the JP
instruction is executed. See Section 6.4 for a list of condition codes.
The unconditional jump simply replaces the contents of the Program Counter with the
contents of the specified register pair.
Control then passes to the statement
addressed by the PC, decremented by one.
Flags:
No flags affected
EXBq>le:
If the carry flag is set, the statement
JP C,%1520
replaces the contents of the Program Counter with %1520 and transfers control to that
location. Had the carry flag not been set, control would have fallen through to the
statement following the JP.
Note:
When used to specify a 4-bit working-register pair address, address mode IRR uses the
format:
E
312
dst
JR
Jump Relative
JR
cc,dst
Instruction format:
OPC
Cycles
~_c_c__~___O_p_C__~1 I~
_____
d_s_t______~
(Hex)
12 If jump taken
10 If jump not taken
ccB
, Address Mode
dst
RA
cc=O to F
Operation:
If cc is true, PC
<--
PC + dst
If the condition specified by "cc" is true, the relative address is added to the
PC and control passes to the statement whose address in now in the PC; otherwise, the
instruction following the JR instruction is executed. (See Section 5.3 for a list of
condition codes). The range of the relative address is +127, -12B, and the original
value of the PC is taken to be the address of the first instruction byte following
the JR statement.
flags:
No flags affected
Example:
If the result of the last arithmetic operation executed is negative, the following
four statements (which occupy a total of seven bytes) are skipped with the statement
JR MI,$+9
If the result is not negative, exec~tion continues with the statement following the
A short form of a jump to label LO is
JR.
JR LO
where LO must be within the allowed range.
case, and is assumed to be "always true."
The condition code is "blank" in this
313
LD
Load
LD
dst,src
Instruction fOrlllat:
OPC
Cycles
dst
OPC
arc
OPC
OPC
OPC
OPC
OPC
OPC
OPC
II
II
II
II
II
II
II
II
src
dst
dst
src
src
dst
src
dst
x
src
x
I
I
I
II
II
II
II
II
6
6
6
(Hex)
rC
r8
Addreas Mode
dst
src
r
r
r9
R*
r=O to F
1M
R
r
6
6
E3
F3
r
Ir
Ir
r
dst
10
10
E4
E5
R
R
R
IR
src
10
10
E6
E7
R
IR
1M
1M
dst
10
F5
IR
R
src
10
C7
r
X
dst
10
07
X
r
*In this instance only a full 8-bit register address can be used.
Operation:
dst <-- src
The contents of the source are loaded into the destination.
source are not affected.
The contents of the
flags:
No flags affected
Example:
If working register 0 contains %08 (11 decimal) and working register 10 contains %83,
the statement
LO 240(RO),R10
will load the value %83 into register 251 (240 + 11). Since this is the Interrupt Mask register, the Load statement has the effect of enabling IRQO and IRQ1.
The
contents of working register 10 are unaffected by the load.
Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
314
src/dst
lDC
Load Constant
lDC
dst,src
OPC
Instruction For.at:
Cyclea
(Hex)
Addreaa Mode
dat
arc
~_____O_P_C______~1 I~_d_s_t__~__s_r_c__~
12
C2
r
Irr
~______o_p_c______~1 ~I___s_r_c__~___ds_t__~
12
02
In
r
Operation:
dst <-- src
This instruction is used to load a byte constant from program memory into a working
register, or vice-versa. The address of the program memory location is specified by
a working register pair. The contents of the source are not affected.
Flaga:
No flags affected
Example:
If the working-register pair 6-7 contains %30A2 and program-memory location %30A2
contains the value %22, the statement
LDC R2, IlRR6
loads the value %22 into working reqister 2.
unchanged by the load.
The value of location %30A2 is
315
LOCI
Load Constant Autoincrement
LOCI
dat,arc
Instruction For.at:
OPC
Cycles
OPC
OPC
Operation:
II
II
dst
(Hex)
Addreas Mode
dst
src
dst
arc
18
C3
Ir
Irr
src
dst
.18
03
Irr
Ir
<-- src
r <-- r + 1
rr
<--
rr +
This instruction is used for block tranafera of data between program memory and the
register file.
The address of the program-memory location ia apecified by a
working-register pair, and the address of the register-file location is specified by
The contents of the source location are loaded into the
a working register.
destination location.
Both addresses are then incremented automatically.
The
contents of the source are not affected.
flags:
No flags affected
Exa.ple:
I f the working-register pair 6-7 contains %30A2 and program-memory locations %30A2
and %30A3 contain %228C, and if working register RZ contains %ZO (32 decimal), the
statement
LOCI OR2, IIRR6
loads the value %22 into register 3Z.
A second
LOCI IIRZ, IIRR6
loads the value %BC into register 33.
316
LDE
Load External Data
LDE
dst,src
OPC
Instruction format:
Address Mode
dat arc
Cycles
(He,d
~______O_P_C______-JII~___d~s_t__-L___sr_c__-J
12
82
r
Irr
~______O_P_C______-JI ~I___s_rc__~___d_s_t__-J
12
92
Irr,
r
Operation:
dst <-- src
This instruction is used to load a byte from external data memory into a working
register or vice-versa.
The address of the external data-memory location is
specified by a working-register pair. The contents of the source are not affected.
flags:
No flags affected
EXaElple:
If the working-register pair 6-7 contains %404A and working register 2 contains %22,
the statement
l.DE aRR6,R2
loads the value %22 into external data-memory location %404A.
317
LDEI
Load External Data Autoincrement
LOCI
dst,src
Instruction f anat:
ope
OPC
Operstion:
II
II
Cycles
OPC
(Hex)
Address Mode
dst src
dst
arc
18
83
Ir
Irr
arc
dat
18
93
Irr
Ir
<-- src
<-- r + 1
dst
r
rr <-- rr +
This instruction is used for blo.ck transfers of data between external data memory
and the register file. The address of the external data-memory location is specified
by a working-register pair, and the address of the register file location is
specified by a working register. The contents of the source location are loaded into
the destination location. Both addresses are then incremented automatically. The
contents of the source are not affected.
flags:
No flags affected
Example:
If the working-register pair 6-7 contains %404~, working register 2 contains %22 (34
decimal), and registers 34-35 contain %~BC3, the statement
LOEI flRR6, flR2
loads the value
%~B
into external location
%404~.
~
second
LOEI flRR6,flR2
Note:
loads the value %C3 into external location %404B.
When used to specify a 4-bit working-register pair address, address modes RR or IR
use the format:
E
318
dst
NOP
No Operation
NOP
Instruction foraat:
OPC
Cyclea
ope
6
Operation:
No action is performed by this instruction.
flags:
No flags affected
(Helt)
ff
It ia typically used for timing delays.
319
OR
Logical Or
OR
dst,src
Instruction foraat:
OPC
Cycles
OPC
OPC
OPC
Operation:
II
II
II
dst
src
src
dst
I
II
II
(Hex)
Address Mode
det src
6
6
42
43
r
r
r
Ir
dst
10
10
44
45
R
R
R
lR
src
10
10
46
47
R
lR
1M
1M
dst <-- dst OR src
The source operand is logically ORed with the destination opersnd and the result is
stored in the destinstion.
The contents of the source are not affected. The OR
operation results in a one bit being atored whenever either of the corresponding bits
in the two operands is 1; otherwise a 0 bit is stored.
flags:
C:
Unaffected
Z: Set if result is zero; cleared otherwise
V:
S:
H:
0:
Example:
Always reset to 0
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected
If the source operand is the immediate value %7B (01111011) and the register named
TARGET contains %C3 (11000011), the statement
ORTARGET,fI%7B
leaves the value %FB (11111011) in register TARGET.
and S is set.
Note:
When used to specify a 4-bit working-register address, address modes Rand IR use the
format:
E
320
The Z and V flags are cleared
src/dst
POP
Pop
POP
dst
Instruction format:
Cy~les
~_____O_P_C______~11L~~ d_s~t______~
10
10
__
Oparotion:
OPc
Addreaa Mode
(Hex)
dat
50
51
R
IR
<-- asp
sp <-- sp +
dst
The contents of the location addressed by the SP are loaded into the destination.
The SP is then incremented automatically.
flags:
No flags affected
EXlIIllple:
If the SP (control registers 254-255) contsins %1000, external data-memory location
%1000 contains %55, and working register 6 contains %22 (34 decimal), the statement
POP 3R6
loads the value %55 into register 34.
%1001.
Note:
After the POP operation, the SP contains
\'/hen used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
dst
321
PUSH
Push
PUSH src
OPC
Instruction for.at:
Cycles
~______oP_c______~1 I~
Operstion:
SP
______
<-- SP -
asp <-- src
sr_c______~
10 Internal stack
12 External stack
12 Internal stack
14 External stack
(Hex)
Address Mode
src
70
R
71
IR
1
The contents of the SP are, decremented, then the contents of the source are loaded
into the location addressed by the decremented SP, thus adding a new element to the
top of the stack.
flags:
No flags affected
EXlIIII(lle:
If the SP contains %1 n01, the statement
PUSH FLAGS
stores the contents of the register named FLAGS in location %1000.
operation, the SP contains %1000.
/ Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
322
After the PUSH
src
ReF
Reset Carry Flag
ReF"'
Instruction for.at: ,
OPC
Operation:
C
<--
Cycles
OPC
(Hex)
6
CF
0
The C flag is reset to 0, regardless of its previous value.
Flags:
C:
Reset to 0
No other flags affected
323
RET
Return
RET
Instruction forMSt:
OPC
OPC
Operation:
Cycles
(Hax)
14
Af
PC <-- asp
sp <-- SP + 2
This instruction is normally used to return to the previoualy executed procedure at
the end of a procedure entered by a CAll instruction. The' contents of the location
addreased by the SP are popped into the PC. The next statement executed is that
addressed by the new contents of the PC.
flags:
No flags affected
EXlIIIIPle:
If the PC contains %3564, the SP containa %2000, external data-memorY,location %2000
contains %18, and location %2001 contains %65, then the statement
RET
leaves the value %2002 in the SP and the PC contains %16B5, the address of the next
instruction.
324
RL
Rotate leU
RL
dst
Instruction Format:
~_____O_P_C______~11~_______d_st~____~
Operation:
C <-- dst(7)
dst(O) <-- dst(7)
dst(n + 1) <-- dst(n) n
=0
Cyclea
OPC
(Hex)
Address Mode
dat
6
6
90
91
R
IR
- 6
The contents of the destination operand are rotated left one bit position.
The
initial value of bit 7 is moved to the bit 0 position and also replaces the carry
flag.
Flags:
c:
Z:
V:
5:
H:
D:
Example:
Set i f the bit rotated from the most significant bit position was 1; i.e., bit 7
was 1
..,
Set if the result is zero; cleared otherwise.
Set if arithmetic overflow occurred; that is, i f the sign of the destination
changed during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected
If the contents of the register named SHIFTER are %88 (10001000), the statement
RL SHIFTER
leaves the value %11 (00010001) in that register.
1 and the Z flag is cleared.
Note:
The C flag and V flags are set to
When used to specify a 4-bit working-register address, address modes R or IR Use the
format:
E
dst
325
RLC
Rotate Left Through Carry
RLC
dst
Instruction
Fo~t:
~_____O_P_C____~1 ~I
Operation:
______
dst (0)
d_s_t____~
OPC
Cycles
(Hex)
Address Mode
dst
6
6
10
11
R
IR
<-- C
C <-- dst
(7)
dst(n + 1) <-- dst(n) n = 0 - 6
The contents of the destination operand with the C flag are ·rotated left one bit
position. The initial value of bit 7 replacea the C flag; the initial value of the C
flag replaces bit O.
Flags:
Set if the bit rotated from the most significant bit position was 1; i.e., bit 7
was 1
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination
changed during rotation; cleared otherwise
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
0: Unaffected
Example:
If the C flag is reset (to 0) and the register named SHIFTER contains'%BF (10001111),
the statement
C:
RLC SHIFTER
sets the C flag and the V flag to 1 and SHIFTER contains %1E (00011110).
Note:
When used to specify a 4-pit working-register address, address modes R or IR use the
format:
E
326
dst
RR
Rotate Right
RR
dst
Instruction for.at:
Cycles
~_____O_PC______~1 I~
Operation:
_____
d_st______~
6
6
OPC
(Hex)
Address Hade
dst
EO
R
E1
IR
C <-- dst(O)
dst(7) <-- dst(O)
dst(n) <-- dat(n + 1) n = 0 - 6
The contents of the destination operand are rotated right one bit position.
initial value of bit 0 is moved to bit 7 and also replaces the C flag.
The
flags:
C:
Set if the bit rotated from the least significant bit position was 1; i.e., bit 0
was 1
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurred, that is, if the sign of the destination
changed during rotation; cleared otherwise
5: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
0: Unaffected
Example:
If the contents of working register 6 are %31 (00110001), the statement
RR R6
sets the Cflag to- 1 and leaves the value %98 (10011000) in working register 6.
Since bit 7 now equals 1, the S flag and the V flag are also set.
Note:
When used to specify a 4-bit working-register address, address modes R-or IR use the
format:
E
dst
327
RRC
Rotate Right Through Carry
RRC
dst
oPC
Instruction For.at:
Cycles
~_____o_P_C______~1 ~I
Operation:
______
d_s_t______~
dat(7) <-- C
C <-- dst(o)
daten) <-- dst(n + 1)
6
6
n
=0
(Hex)
Address Mode
dst
CO
R
C1
IR
- 6
The contents of the destination operand with the C flag are rotated right one bit
position. The initial value of bit 0 replaces the C flag; the initisl value of the
C flag replaces bit 7.
Hags:
C:
Z:
Y:
S:
H:
0:
Example:
Set if the bit rotated from the least significant bit position was 1; i.e., bit 0
was 1
Set if the result is zero; cleared otherwise
Set if arithmetic overflow occurred, that is, the sign of the destination changed
during rotation; cleared otherwise
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected
If the contents of the register named SHIFTER are %00 (11011101) and the Carry flag
is reset .to 0, the statement
RRC SHIFTER
sets the C flag and the V flag and leaves the value %6E (01101110) in the register.
Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
328
dst
SBC
Subtract With Carry
sec
dst,src
Instruction Foraat:
OPC
OPC
OPC
Operstion:
OPC
II
II
II
dst
(Hex)
6
6
32
33
r
r
r
Ir
dst
10
10
34
35
R
R
R
IR
src
10
10
36
37
R
IR
1M
1M
src
src
dst
II
II
Address Mode
dst src
Cycles
dst <-- dst - src - C
The source operand, along with the setting of the C flag, is subtracted from the
destination oparand and the rasult ie stored in the destination. The contente of the
source are not affected. Subtraction is performed by adding the two's complement of
the source operand to the destination operand. In multiple precision arithmetic,
this instruction permits the carry ("borrQw") from the subtraction of low -order
operands to be subtracted from the subtraction of high-order operands.
flags:
C:
Z:
V:
S:
H:
D:
Example:
Cleared if there is s carry from the most significsnt bit of the result; set
otherwise, indicating a "borrow"
Set if the result is 0; cleared otherwise
Set if arithmetic overflow occurred, thst is, if the operands were of opposite
sign and the sign of the result is the ssme BS the sign of the source; reset
otherwise
Set if the result is negative; cleared otherwise
Cleared if there is e carry from the most significant bit of the low-order four
bits of the result; set otherwise indicating a "borrow."
Always set to 1
If the register named MINUEND contains %16, the Carry flag is set to 1, working
register 10 contains %20 (32 decimal), and register 32 contains %05, the statement
SBC MINUEND, OR10
leaves the value %10 in register MINUEND.
D is set.
Note:
The C, Z, V, S and H flags are cleared and
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
src/dst
329
SCF
Set Carry Flag
SCf
Instruction Format:
Cycles
oPc
Operation:
6
,c <--
1
The C flag is set to 1, regardless of its previous value.
Flaga:
330
c:
Set to 1
No other flags affected
OPC
(Hex)
OF
'SRA
Shift Right Arithmetic
SRA
dst
Instruction format:
OPC
Cycles
~_____O_P_C______~1 ~I
Operstion:
______
d_a_t______~
<-- dst(7)
dst(O)
dst(n) <-- dat(n + 1)
6
6
(Hex)
Address Mode
dst
DO
R
01
IR
dst(7)
c <--
n
=0
- 6
An arithmetic shift right ~ne bit position is performed on the deatination operand.
Bit 0 replaces the C flag. Bit 7 (the Sign bit) is unchanged, and its value is also
shifted into bit position 6.
7
flags:
C:
Z:
V:
S:
H:
D:
EXsq:lle:
o
Set if the bit shifted from the least significant bit position was 1; i.e., bit 0
was 1
Set if the result is zero; cleared otherwise
Always reset to 0
Set if the result is negative; cleared otherwise
Unaffected
Unaffected
If the register named 'SHIFTER contains
~BB
(10111000), the statement
SRA SHIFTER
resets the C flaq to 0 and leaves .the value IDC (11011100) in register SHIFTER.
S flag is set to 1.
Note:
The
When uaed to specify a 4-bit working-register address, addresa modes R or IR use the
format:
E
dst
331
SRP
Set Register Pointer
SRP
src
Instruction For.at:
Cycles
L-_____O_P_c______
Operation:
~1 IL______s_r_c______~
RP
<--
6
OPC
(Hex)
31
Address Mode
arc
1M
src
The specified, vslue is, losded into bits 4-7 of the Register Pointer (RP) (control
register 253). Bits 0-3 of the RP sre always set to O. The source data (with bits
0-3 forced to 0) is the starting address of a working-register group.
The
working-register group starting addreases are:
Hex
Decimal
~60
~70
0
16
32
48
64
80
96
112
~FO
240
~OO
"110
~20
~30
~40
~50
Values in the range
~80-EO
(control and peripheral registers)
are invalid.
Hags:
No flags affected
EX8lllPle :
Assume the RP currently addresses the ,control and peripheral register group and the
program has just entered an interrupt service routine. The statement
SRP
#~70
saves the contents of the control and peripheral registers by setting the RP to ~70
(01110000), or 112 decimal. Any reference to wO,rking registers in the interrupt
routine will point to registers 112-127.
332
SUB
Subtract
,
SUB
dst,src
Instruction r orllllt:
OPC
Cycles
OPC
II
OPC
II
II
OPC
Operation:
. dst
dst
src
srt;
dst
I
II
II
(Hex) .
Add'reaa Mode
dat
arc
6
6
22
23
r
r
r
Ir
dst
10
10
24
2S
R
R
R
IR
src
10
10
26
27
R
IR
1M
1M
<-- dst - src
The source operand is subtracted from the destination operand and the reault is
stored in the destination. The contents of the source are not affected. Subtraction
is performed by adding the two's complement of the source operand to the destination
operand.
Hags:
C: Cleared i f there is a carry from the most Significant bit of the result; set
otherwise, indicating a "borrow"
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite
signs and the sign of the result is the same as the sign of the source operand;
cleared otherwise
.
·S: Set if the result is negative; cleared otherwise
H: Cleared if there is a carry from the most significant bit of the low-order four
bits of the result; set otherwise indicating a "borrow."
0: Always set to 1
Example:
If
the register named MINUEND contains 11129, the statement
SUB MINUEND, #\\111
will leave the value 11118 in the register.
o is set.
Note:
The C, Z, V, Sand H flags are cleared and
When used to specify a 4-bit working-register address, eddress modes R or IR use the
format:
E
src/dst
333
SWAP
Swap Nibbles
SWAP dst
Instruction For.at:
Cycles
~_____O_P_C____~1 ~I
Operation:
______
d_s_t____~
oPC
Address Mode
(Hax)
dst
B
ro
B
F1
R
IR
dst(O - 3) <--> dst(4 - 7)
The contents of the lower four bits and upper four bits of the destination operand
are swapped.
Flags:
C: Undefined
Z: Set if the result is zero; clesred otherwise
V: Undefined
5: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
D: Unsffected
EXlIIIIPle:
Suppose the register named
BCD~perands
contsins %B3 (10110011).
The ststement
SWAP BCD_Operands
wili leave the vslue %3B (00111011) in·the register.
Note:
When used to specify a 4-bit working-register address, address modes·R or IR use the
format:
E
334
The Z and S flags are cleared.
dst
TeM
Test Complement Under Mask
TCH
dst,src
OPC
Instruction FDl'IIBt:
ope
II
ope
II
II
ope
Operation:
dst
src
src
dst
I
II
II
Address Mode
dst Dre
Cycles
(Hex)
6
6
62
63
r
r
r
lr
dst
10
10
64
65
R
R
R
lR
src
10
10
66
67
R
lR
1M
1M
(NOT dst) AND src
This instruction tests selected bits in the destination operand fo!, a logical "1"
vslue. The bits to be tested are apecified by aetting a 1 bit in the corresponding
p~sition of the aource operand (mask).
The TeM atatement complementa the destination
operand, which ia then ANDed with the source mask. The Zero (Z) flag can then be
checked to determine the result. When the TeM operation is complete, the destination
location still contains its original value.
Flags:
C:
Z:
V:
S:
Unaffected
Set if the result is zero; cleared otherwise
Always reset to 0
Set if the result bit 7 is set; cleared otherwise
H: Unaffected
D: Unaffected
EXlIIIIPle :
If the register named TESTER contsins %f6 (11110110) and the register named MASK
contains %06 (00000110), that is, bits 1 and 2 are being
statement
teste~
for a 1 value, the
TeM TESTER, MASK
complements TESTER (to" 00001001) and then do a logical AND with register MASK,
resulting in %00. A subsequent test of the Z flag,
JP Z,plabel
causes a transfer of program control.
contains %f6.
Note:
At the end of this aequence, TESTER still
When used to specify a "4-bit working-regiater address, address modes R or lR use the
format:
E
src/~st
335
TM
Test Under Mask
TM
dst,src
Instruction For.at:
OPC
Cyclea
ope
ope
ope
Operation:
II
II
II
dst
src
arc
dst
I
II
II
(Hex)
Addreaa Mode
dat arc
6
6
73
r
r
r
Ir
dst
10
10
74
75
R
R
R
lR
src
10
10
76
R
lR
1M
1M
72
77
dst AND src
This instruction tests selected bits in the destination operand for a logical "0"
value. The bits to be tested are specified by setting a 1 bit in the corresponding
position of the source operand (mask), which is ANDed with the destination operand.
The Z flag can be checked to determine the reault.
When the TM operation is
complete, the destination location still contains its original value.
Flags:
C:
Z:
V:
S:
H:
D:
Example:
Unaffected
Set if the result is ~ero; cleared otherwise
Always reset to 0
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected
If the register named TESTER contains %F6 (11110110) and the register 'named MASK
contains %06 (00000110), that is, bits 1 and 2 are being tested for aO value, the
statement
TM TESTER, MASK
results in the value %06 (00000110).
A subsequent test for nonzero
JP NZ, plabel
causes a transfer of program control.
At the end of this sequence, TESTER still
contains %F6. The Z and S flags are cleared.
Note;
When used to specify a 4-bit working-register address, address modes R or lR use the
format:
E
336
src/dst
XOR
logical Exclusive OR
XOR
dBt,Brc
Instruction Foreat:
Cycles
OPC
II
OPC
II
II
OPC
Operation:
dat
arc
src
dBt
I
II
II
OPC
(l!9lC)
Addreas Node
dst' ore
6
6
B2
. B3
r
r
r
Ir
dBt
10
10
B4
B5
R
R
R
IR
arc
10
10
B6
B7
R
IR
1M
1M
dst <-- dst XOR src
The source operand is iogically EXCLUSIVE ORed with the destination operand and the
result' stored in the destination. The EXCLUSIVE OR operation results in a one bit
being stored whenever the corresponding bits in the operands are different;
otherwise, a 0 bit is stored.
Flags:
C:
Z:
V:
5:
H:
0:
Unaffected
Set if the result is zero; cleared otherwise
Always reset to 0
Set if the result bit 7 is set; cleared otherwise
Unaffected
Unaffected
ElC!!::ple:
If the source operand is the immediate value %7B (011111011) and the register named
TARGET contains %C3 (11000011), the statement
OR TARGET, #%7B
leaves the value %BB (10111000) in the register.
Note:
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
src/dst
337'
Chapter 6
External Interface
,'(Z8601, Z8611)
6.1
a high-impedance state along with Ports 0 and 1,
Oata Strobe (DS),'and R/W;
INTRIDUCTHW
The ROM versions of the ZB microcomputer have 40
external pins, of which 32 are programmable I/O
pins. The remaining B pins are_used for power and
control. Up to 16 I/O pins can be configured as
an external memory interface. This interface
function is the subject of this chapter. The I/O
mode of these pins is described in Chapter 9.
os.
Data Strobe (output, active Low, J-state,
pin 8). Data Strobe provides the timi~g for data
movement to or from Port 1 for each external
memory transfer. During a Write cycle, data out,
is valid at the leading edge of 55. During a Read
cycle, data in must be valid prior to the trailing
edge of OS. OS can be placed in a high-impedance
state along with Ports 0 and 1, AS, and R/W.
6.2 PIN DESCRIPTIONS
AS.
Address Strobe (output, active Low, J-state,
pin 9). Address Strobe is pulsed Low'once at the
beginning of each machine cycle. The ~ising edge
of AS indicates that addresses, Read/Write (R/W) ,
and Data Memory (OM) signals, are valid when output for external program or data memory transfers. Under program control, AS can be placed in
PORTO
(NIBBLE
PROGRAMMABLE)
1/0 OR As-A,.
ffiE'i'
+5V
RIW
GND
Os
AS
XTAL2
POo
P20
(output, J-state, pin 7).
R!W. Read/Write.
Read/Write determines the direction of data transfer for external memory transactions. R/W is Low
when writing' to external program or data memory,
and High for all other transactions. R/W can be
placed in a high-impedance state along with Ports
o and 1, AS, and OS.
+5V
XTAL1
PO,
P2,
P~
P2:z
P03
P2a
PO.
P20
PORT 2
(BIT PRO·
GRAMMABLE)
1/0
POs Z8601/11 P2s
POs
PORT 1
(BYTE
PROGRAMMABLE)
1/0 OR ADo-AD7
MCU
P2s
P07
P27
P1 0
P30
P1,
P3,
P1 2
P32
P1 3
P33
P1.
P3,
P1 s
P3s
P1 s
P3a
P1 7
P37
PORTa
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL I/O
AND CONTROL
2
P3,
XTAL1
3
P27
P~
4
P2s
P30
5
P2.
RESET
6
P2.
RIW
7
P23
OS
B
P22
,6;S
9
P3s
10 Z8601/11
P2,
31
MCU
P20
GND
11
P32
12
POo
13
P1 7
PO,
14
P1 6
P02
PO
a
P33
P3.
15
P1 s
16
P1.
PO,
24
P1 3
PO s
23
P1 2
POs
22
P1,
P0 7
Figure 6-2.
338
P3s
XTAL2
P1 0
18601/11 Pin Assignments
External Interface (ZS601,ZS611)
P0o-P07' P10-P17' P20-P27' P3o-P37"
I/O port
lines
(inputs/outputs.
TTL-compatible.
pins
12-40). These 32 I/O lines are divided into four
S-bit I/O ports that can be configured under program control for I/O or external memory interface. Individual lines of a port are denoted by
the second digit of the port number. For example,
P3 0 refers to bit 0 of Port 3. Ports 0 and 1 can
be placed in a high-impedance state along with AS,
155, and R/W.
RESET. Reset (input, active LOIt, pin 6). RESET
initializes the ZS.
When RESET is deact,ivated,
program execution begins from internal program
location %C. If held Low, RESET acts as a register file protect during power-down and power-up
sequences. RESET also enables the ZS Test mode.
XTAL1, XTAL2. Crystal 1, Crystal 2 (oscillator
input and output, pins 3 and 2). These pins connect a parallel-resonant crystal (12 MHz maximum)
or an external source (12 MHz maximum) to the
on-board clock oscillator and buffer.
6.3 CONFIGURING FOR EXTERNAL MEMORY
Before interfacing with external memory, the user
must configure Ports 0 and 1 appropriately,. The
minimum bus configuration uses Port 1 as a multiplexed Address/Oata port (AOO-A07), allowing
access to 256' bytes of external memory. In this
configuration, the eight lower order address bits
(A O-A7) are multiplexed with the data (00-07)'
Port 0 can be programmed to provide four additional address lines (AS-A11)' which increaaes the
externally addressable program memory to 4K
bytes. Port 0 can, also be programmed to provide
eight additional address lines (AS-A 15 ), which
increases the externally addressable memory to 62K
bytes for the ZS601 or 60K bytes for the ZS611.
Refer to Chapter 3, Figures 3-5 and 3-6, for
external memory maps.
Ports 0 and 1 are ,configured for external memory
operation by writing the appropriate bits in the
Port 0-1 Mode register (Figure 6-3).
For example, Port , can be defined as a mult ipIe xed Address/Oata port (AOO-A07) by setting 04
to 1 and 03 to O. The lower nibble of Port O'can
be defined as address lines AS-A11' by setting 01
to 1. Similarly, setting D7 to ,1 defines the upper
nibble of Port 0 as address lines A12 -A15' Whenever' Port 0 is configured to output address ,lines
A12-A15' AS-A11 must also be, selected as address
lines.
R248 P01M
Port 0-1 Mode Register
(% Fa; Write Only)
~04-P07
MODE
OUTPUT
00
INPUT = 01
A'2-A,. = 1X
=
--r-
~
-r
L
POO-P03 MODE
00
OUTPUT
01
INPUT
1X = A.-A"
=
=
P1 0 -P1 7 MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
ADo-AD7
10
11 = HIGH·IMPEDANCE ADo-ADr,
AS, OS, R/W, As-A", A'2-A'5
=
Figure 6-3.
Ports 0 and 1 External HllIIIOry Operation
339
External Interface (ZB601,ZB611)
Once Port 1 is configured as an Address/Data port,
it can no longer be used as a register. Attempting to read Port 1 returns FF; writing has no
effect. Similarly, if Port 0 is configured for
address lines AB-A 15 , it can no longer be used as
a register. However, if only the lower nibble is
defined as address lines AB-A 11 , the upper nibble
is still addressable as an I/O register. Reading
Port 0 with only the lower nibble defined as
address outputs returns XF, where X equals the
data in bits 0 4-0 7 ,
Writing to Port 0 transfers
data to the I/O nibble only.
An instruction to change the modes of Ports 0 or 1
should not be immediately followed by an instruc-.
tion that performs a stack operation, because this
may cause indeterminate program flow.
In addition, after setting the modes of Ports 0 and 1 for
external memory, the next three bytes must be
fetched from internal prog['am memory.
6.5 OATA MEMORY
The two external memory spaces, data and program,
can be addressed as a single memory space or as
two separate spaces of equal size; i.e., 62K bytes
each for the ZB601 and 60K bytes each for the
ZB611.
If the memory spaces are separated,
program memory and data memory are logically
se lected by the Data Memory select output (OM).
OM is available on Port 3, line 4 (P3 4 ) by setting
bits 04 and 0 3 in the Port 3 Mode register to 10
or 01 (Figure 6-5). OM is active Low during the
execution' of the LOE, LDEI instructions. OM is
also adive during the execution of CALL, POP,
PUSH, RET and IRET instructions if the stack
resides in external memory.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
6.4 EXTERNAL STACKS
ZB architecture supports stack operations in
either the register file or data memory.
A
stack I s locat ion is determined by bit O2 in the
Port 0-1 Mode register. For example, if O2 is set
to 1, the stack is in internal data memory
(Figure 6-4).
o0
P33 = INPUT
P33 = INPUT
1 0 P33 = INPUT
1 1 P33 = OAV1/ROY1
o1
P34
P34
P34
P34
=
=
=
=
OUTPUT
OM
OM
ROY1/0AV1
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
Figure 6-5.
L
STACK SELECTION
0= EXTERNAL
1 = INTERNAL
Figure 6-4.
Ports 0 and 1 Stack Selection
The instruction used to change the stack selection
bit should not be immediately followed by the
instructions RET or IRET, because this will cause
indeterminate program flow.
340
Data Memory Operation
6.6 BUS OPERATION
The timing for typical data transfers between the
ZB and external memory is illustrated in Figure
6-6. Machine cycles can vary from six to twelve
clock periods depending on the operation being
performed.
The notations used to describe the
basic timing periods of the ZS are: machine cycles
(Mn), timing states (Tn), and clock periods. All
timii1g references are made with respect to the
output signals AS and OS. The clock is shown for
clarity only and does not have a specific timing
relationship with other signals.
External Interface (ZB601,ZB611)
~1'~----T-l--------MACH::CYCLE--------T-3-----"11
CLOCK
PO
X
P1
X
Aa-A15
Ao-A7
)
(00-07 IN)
'---I
'---
\
/
I
R/W
C
X
14
Figure 6-6a.
6.6.1
X
C
X
READ CYCLE
'1
External Instruction Fetch, or Memory Read Cycle
Address Strobe (AS)
All transactions start with AS driven Low and then
raised High by the ZB.
The rising edge of AS
indicates that R/W, OM, and the addresses output
from Ports 0 and 1 afe valid.
The addresses
output via Port 1 remain valid only during MnT1
and typically need to be latched using AS, whereas
Port 0 address outputs remain stable throughout
the machine cycle.
6.6.3 External Memory Operations
Whenever the ZB is configured for external memory
operation, the addresses of all internal program
memory references appear on the external bus.
This should have no effect on the external system
since the bus control lines, OS and R/W, remain in
their inactive High state.
OS and R/W become
active orily during external memory references.
CAUTION
6.6.2 Data Strobe
The ZB uses OS to time the actual data transfer.
For Write operations (R/W = Low), a Lo~ on OS
indicates that valid data is on the'Port 1 AO O-A0 7
lines.
For Read operations, (R/W = High), the
Address/Data bus is placed in a high-impedance
'state before driving OS Low so that the addressed
device can put its data on the bus. The ZB samples this data prior to raising OS High.
00 not use LOC, LOCI, LOE or LOEI to
wr ite to internal program memory. The
execution of these instructions causes
the Z8 to assume that an external 'write
operation is being performed and this
will activate control signals OS and
R/W.
341
External Interface ( ZB601 ,Z8611)
MACHINE CYCLE
I'
T2
Tl
'I
Ta
CLOCK
X
X
PO
P1
X
X
As-AI5
Ao-A7
X
00-07 OUT
LI
L
\
R/W
/
\
________x___________________ ___
~x
I'",
" ; - - - - - - - - W R I T E CYCLE
Figure 6-6b.
6.7
--------i,1
External Memory Write Cycle
SHARID BUS
Port 1, along with AS, DS, R/W, and Port 0 nibbles
configured as address lines, can be placed in a
high-impedance state, allowing the ZB601 or th~
ZB611 to share common resources with other bus
masters. This shared bus mode is under software
control and is programmed by setting Port 0-1 Mode
register bits D4 and D} both to 1 (Figure 6-7).
Data transfers can be controlled by assigning, for
example, P3} as a Bus Acknowledge input and P34 as
a Bus Request output.
Bus Request/Acknowledge
control sequences must be software driven.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
,
P1 o-P1 7 MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7,
AS,
Figure 6-7.
342
OS,
RiW, As-All. A12-A15
Shared Bus Operation
External Inter face (ZB601, zB61.11
6.8 EXTENDED BUS TIMING
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
The ZB601 and ZB611 can accommodate slow memory
access times by automat ically inserting an additional state time (Tx) into the bus cycle.
'This
stretches the OS timing by two clock periods,
though internal memory access time is not
affected. Timing is extended by setting bit D5 in
the Port 0-1 Mode register to 1 (Figure 6-8).
Figures 6-9a and 6-9b illustrate extended memory
Read and Write cycles.
EXTERNAL MEMORY TIMINGJ
NORMAL
0
,·EXTENDED = 1
=
"ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 6-8.
r
Extended Bus Tilling
MACHINE CYCLE
T2
Tl
Tx
'I
T3
CLOCK
PO
P1
AS
==x
'=x
A 8-A15
DM
( Do-D7 IN
L
\----.I
/
\
DS
R/W
)
Ao-A7
>C
>--C
-.--J
==x
I,'
figure 6-9a.
C
>C
READ CYCLE
'I
Extended External Instruction Fetch, or Memory Read Cycle
343
External Inter face (ZS60.1, ZS.6.U>
6.9 INSTRUCTION TIMING
The high throughput of the ZB is due, in part, to
the use of instruction pipe lining , in which the
instruction fetch and execution cycles are overlapped.
During the execution of an instruction
the opcode of the next instruction is fetched.
This is illustrated in Figure 6-10..
Figures 6-11· and 6-12 show typical instruction
. cycle timing for instructions fetched from external memory. (It should be noted that ·all instruc-
1-----------T-
I'
2
tion fetch cycles have the same machine timing
regardless of whether memory is internal or external. > For those instructions that require execution time longer then that of the overlapped
fetch, or instructions that reference program or
data memory as part of their execution, the pipe
must be flushed. In order·to calculate the execution time of a program, the internal clock periods
shown in the cycles column of the instruction formats in Section·5.4 should be added together. The
cycles are equal to one-half the crystal or input
clock rate.
I
MACHINE CYCLE-- - - - - - - -- - - - - I ·
T3
TX
Tl
C.LOCK
PO
~
P1~
Ao-A7
X
AS.~
\_------
OS
R/W
OM
\
~
I'i - - - - - - - - - - - - W R I T E C Y C L E - - - - - - - - - - . . , . - figure 6-9b.
344
Extended External Memory Write Cycle
f"'1
X
,....
..,
(1)
:l
III
.....
......
,....
:l
..,....,
(1)
Ml
M2
---1-
------M-l- - --
r-
III
M2
Ml
M2
"
(1)
N
CD
'"~
INTERNAL
CLOCK
N
CD
'"
~
INSTRUCTION
N
INSTRUCTION
FETCH 1
OPERAND
FETCH(ES)
INSTRUCTION
FETCH 2
ALU STORE
l-------EXECUTION CYCLE
INSTRUCTION
INSTRUCTION
FETCH 1
N+1
"
OPERAND
FETCH(ES)
INSTRUCTION
FETCH 2
ALU STORE
_-----EXECUTION CYCLE------j
INSTRUCTION
FETCH 1
INSTRUCTION
1\1+2
I 1
~
INSTRUCTION COMPLETION TIME
Figure 6-10.
*
HIDDEN DELAY
UNTIL COMPLETION
Instruction Pipelining
E>
I
INSTRUCTION
FETCH 2
~
en
M,
,- -
--
T,
L_
T2
M2
n_
T3
T,
M,
T2
T3
T,
T2
T3
CLOCK
PO
Pl
X
___J-J
An-A7
--€9---<
)
c=
AS-A'5
An A7
~
}
rn
AS
~
OS
7~
RIW
X
As-A, 5
IN
\..J
\....f
I
\
I
_ _--JI
,.
Figure 6-11.
r -CLOCK
-I'
FETCH INSTRUCTION
)I
M,
T,
AS
os
.,
Instruction Cycle Timing (One Byte Instructions)
M2
T2
T3
T,
M, OR M3
T2
T3
T,
T2
T3
LJUL..nSU'
-----y:-,J -----p·;;=A;5----- PO _ _ _ _ _
Pl
FETCH 1ST BYTE OF NEXT INSTRUCTION
____~x
AD- A7
>-
.
==x
~
-------
~
-----,\..,
X
As-A, 5
AD A7
~
)
A.-A'5
AD A7
)
~
,..,
x
....
..,
CD
'~
/
.,.....
:J
~
\
\
/
/
.....
....
:J
..,
CD
;;;'
R/W
o
_ _--'7
\.
CD
~
FETCH 1ST BYTE
.\.
FETCH 2ND BYTE
.\.
FETCH 3RD BYTE (3·BYTE INSTR.)
FETCH 1ST BYTE (lor 2 BYTE INSTR.)
III
'"~
N
Q)
~
figure 6-12.
Instruction Cycle TiJling (Two and Three Byte Instructions)
....
.
External Interface (Z8601,Z8611)
6.10
RESET CONDITIONS
After a hardware reset, Ports 0 and 1 are confjgured_ as input ports, memory and stack are
internal, extended timing is set and DM is
inactive.
Figure 6-13 shows the binary values
reset into P01M.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
~
PO.-P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
'EXTENDED = 1
I [ ""!,;~~.:;~~,
01 = INPUT
1X = A8-A11
-
.
STACK SELECTION
0 = EXTERNAL
1 = INTERNAL
P1 o-P1 7 MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7,
AS, OS, Riw, As-A", A'2-A'5
'ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 6-13.
Ports 0 and 1 Reset
347
Chapter 7
External Interface
(Z8681, Z8682)
7.1
INTRODUCTION
The ROM less versions of the Z8 microcomputer have
40 external pins, of which 24 are programmable I/O
pins.
Of the remaining 16 pins, 8 form an
Address/Data bus and the others are used fop power
and control. Up to 8 I/O pins can be programmed
as additional address lines to be used for
external memory interface.
Os. Data Strobe (output, active low, pin 8).
Data Strobe provides the timing for data movement
,to or from Port 1 for each memory transfer.
During a Write cycle, data out is valid at the
leading edge of 55. During a Read cycle, data in
must be valid prior to the trailing edge of 55.
7.2 PIN DESCRIPTIONS
AS. Address Strobe (output, active low, pin 9).
Address Strobe is pulsed Low once at the beginning
of each machine cycle.
The rising edge of AS
indicates that addresses, Read/Write (R/W), and
Data Memory (OM) signals are valid when output for
program or data, memory transfers.
PORTO
(NIBBLE
PROGRAMMABLE)
1/0 OR Aa-A,s
RESET
+5V
RiW
GND
OS
AS
XTAL2
POo
P20
PO,
P2,
PO.
P2,
P2,
PO,
P2.
POs Z8681182 P2S
348
P01-P07. Address/Oata Port (inputs/outputs, TTlcOIIIpatible, pins 13-20).
Port 1 is permanently
configured as a multiplexed Address/Data memory
interface. The lower eight address lines (AO-A7)
are multiplexed with data (00-07).
+5V
XTALl
PO,
PO.
R/K.
Readf\olrite. (output, pin 7). Read/Write
determines the direction of data transfer for
memory transactions. R/W is Low when writing to
program or data memory, and High for all other
transactions.
MCU
P20
POT
P2T
Pl 0
P30
Pl,
P3,
Pl.
P3.
PORT 1
Pl,
P3,
ADo-AD7
Pl.
P3.
Pl s
P3s
Pl.
P3.
P1 7
P3 T
PORT 2
(BIT PRO'
GRAMMABLE)
r
PORT 3
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL 110
AND CONTROL
P3.
XTAL2
2
P3,
XTALl
3
P2T
P3T
4
P2.
P30
5
P2s
RESET
6
P2.
RIW
7
P2,
OS
AS
8
P2.
9
P2,
P3 s
10 Z8681182 31
P20
MCU
P3,
GND
11
P3.
12
POo
13
P1 T
PO,
14
Pl.
Pl s
P3.
PO.
15
PO,
16
PO.
17
24
Pl,
PO s
18
23
Pl.
PO.
19
22
Pl,
POT
20
21
Pl 0
Pl.
External Interface (Z8681,ZB6B2)
POO-P07. P20-P27. P30-P~.
I/O Port lines
(inputs/outputs, TTl-compatible).
These 24 I/O
lines are divided into 3 8-bit I/O ports that can
be configured under program control for I/O or
memory interface. Individual lines of a port are
denoted by the second digit of the port number.
for example, P3 0 refers to bit 0 of Port 3.
tion, the eight low order address bits (AO-A7) are
multiplexed with the data (00-07)'
Port 0 can be programmed to provide either four
additional address lines (A B-A11) which increases
the addressable memory to 4K bytes, or eight
additional address lines (AB-A 15) which increases
the addressable memory to 64K bytes for the Z86B1
and 62K bytes for the ZB6B2. Refer to Chapter 3,
figures 3-5 and 3-6, for the memory maps.
RESET. Reset (input. active low. pin 6). RESET
initializes
the
ZB6B1/B2.
When RESET
is
deactivated,
program
execution
begins
from
external program location %C for the ZB6B1 and
location %B12 for the Z86B2.
If held low, RESET
acts as a register file protect during power-down
and power-up sequences.
In the ZB6B1, Port 0 lines intended for use as
address lines are automatically configured as
inputs after a Reset. These lines therefore float
and their logic state remains unknown until an
initialization routine configures Port O. In the
ZB6B2, Port 0 lines are configured as address
lines AB-A 15 following a ReseL
XTAl1. XTAl2.
Crystal 1. Crystal 2 (oscillator
input and output. pins 3 and 2).
These pins
connect a parallel resonant crystal or an. external
source to the on-board clock osci llator, and buffer.
7.3
7.3.1
The initialization routine must reside within the
first 256 bytes of executable code and must be
physically mapped into memory by forcing the port
o address lines to a known state. figures 7-3 and
7-4 illustrate how a 4K byte memory space can be
addressed.
CONfIGURING PORT 0
The minimum bus configuration uses Port 1 as a
multiplexed Address/Data port (AD O-AD 7 ) allowing
access to 256 bytes of memory. In this configura-
PORT1
Z8681
MCU
1/2 PORT 0
<
I
Z8681 Initialization
ADo-AD7
>
As, 05, RlW
POD
As
PROGRAM
MEMORY
POl
Ag
(4K BYTES)
P02
Al0
P03
All
?Vee
The initialization routine is mapped in the top 256 bytes of program memory. Depending on the
application, the interrupt vectors may need to be written in the first 12 byte locations of program
memory by the initialization routine.
figure 7-3. 'Example Z8681/Me.ary Interface
349
A
PORT 1
(
\
ADa-AD7
V
~
AS,OS,RiW
-
POa
Z8681
1/2 PORT O~
-----
POl
P02
P03
~
R/W
T
As
18
lb
Ag
28
2b
LS157
PROGRAM
MEMORY
14K BYTES)
Ala
38
3b
All
48
4b
~TROBE SELECT
R
Q
S
The initialization routine is mapped in the first 256 bytes of program memory. Any memory write
operation will cause the flip-flop to select Port 0 outputs as addresses.
Figure 7-4.
Example Z8681/HeaDry Interface
Port 0 is programmed for memory operation by writing the appropriate bits in the Port 0-1 Mode register (Figure 7-5).
The proper port initialization sequence is:
The lower nibble of Port 0 can be defined as
address lines A8-A11' by setting D1 to 1.
Similarly, setting 07 to 1 defines the upper nibble of Port 0 as address lines A12-A15'
•
Load Port 0 with initial address value.
•
Configure Port
Whenever Port 0 is configured to output address
lines A1Z -A 1 5' A8-A11 must also be selected as
address lines.
=
Fetch the next three bytes without changing the
address in Port O.
(This is necessary due to
instruction pipelining.)
0~1
Mode register.
The Z86B2 must be operated in Test mode only.
Section 8.4 gives a complete description of the
proper technique for entering Test mode.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
PO.-P07 MODE
OUTPUT = 00
INPUT = 01
I"
~
A12 -A 15 = lX
Figure 7-5.
350
-r
L
7.3.2 Z8682 Initialization
POa-PO. MODE
00 = OUTPUT
01 = INPUT
lX = A8-All
Z8681 Port 0 Memory Operation
The user initialization routine must begin at
location %812 and must reside in memory fast
I n the Z8682,
. enough for normal memory timing.
the user is not protected from reconfiguring
Port 1 by writing to R248 (P01M).
Therefore
whenever a write is made to P01M, the value 10
(binary) must be written to bits 04 and D3' Any
other value wi 11 cause complete loss of program
control.
External Interface (ZB6B1,ZB6B2)
The lower nibble of Port 0 can
address lines AB-A11' by setting
larly, setting 07 to 1 defines the
Port 0 as address lines A12-A15'
be defined as
0 1 to 1. Simiupper nibble of
Whenever Port 0 is configured to output address
lines Al2 -A15' AB-A 11 must also by selected as
address lines.
7.3.3 Read/Write Operations
If Port 0 is configured for address lines ArA15'
7.4 EXTERNAL STACKS
The ZB681/B2 architecture supports stack operations in either the register file or data memory.
A stack's location is determined by bit 02 in the
Port 0-1 Mode register. For example, if D2 is set
to 0, the stack is in external data memory
(Figure 7-7).
The instruction used to change the stack selection
bit should not be immediately followed by the
instructions RET or IRET, because this will cause
indeterminate program flow.
it can no longer be used as a register; however,
i f only the lower nibble of Port 0 is defined as
address lines AB-A11' the upper nibble is still
addressable as an I/O register.
When only the
lower nibble is defined as address outputs, reading Port 0 returns XF, where X equals the data in
bits 04-D7. Writing to Port 0 transfers data to
the I/O nibble only.
The instruction used to change the mode of Port 0
should not be immediately followed by an instruction that performs a stack operation, because this
will cause indeterminate program flow. In addition, after setting the mode of Port 0 for memory,
the next three bytes must be fetched without
changing the value of the upper byte of the Program Counter (PC).
7.5 DATA MEMORY
The two memory spaces, data and program, can be
addressed as a single memory space or as two
separate spaces of equal size; i.e. 64K bytes each
for the ZB6B1 and. 62K bytes each for the ZB6B2.
If the memory spaces are separated, program memory
and data memory are logically selected by Data
Memory select output (OM). OM is made available
on Port 3, line 4 (P3 4 ) by setting bits 04 and 03
in the Port 3 Mode register to 10 or 01 (Figure
7-B). OM is active Low during the execution of
the LOE, LOEI instructions. OM is also active Low
during the execution of CALL, POP, PUSH, RET and
IRET instructions if the stack resides in memory.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
PO.- P07 M O D E I
OUTPUT = 00
INPUT = 01
A12 -A '5 = 1X
-rL
POO-P0 3 MODE
00 = OUTPUT
01 = INPUT
1X = A.-A"
' -_ _ _ _ _ P1 o-P1 7 MODE
10 = ADo-AD7
Figure 7-6.
Z8682 Port 0 Memory Operation
351
External Interface (ZB6B1,ZB6B2)
7.6.1
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
L
STACK SELECTION
0= EXTERNAL
1 = INTERNAL.
Address Strobe (AS)
All transactions start with AS driven Low and then
raised High by the ZB6B1/B2. The rising edge of
As indicates that R/W, DM (if used), and the
addresses output from Ports 0 and 1 are valid.
The addresses output via Port 1 remain valid only
during MnT1 and typically need to be latched using
AS, whereas Port 0 address outputs remain stable
. throughout the machine cycle.
7.6.2 Data Strobe (OS)
Figure 7-7.
External Stack Operation
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
The ZB6B1/B2 uses 55 to time the actual data
transfer. For Write operations (R/W = Low), a Low
on 55 indicates that valid data is on the Port 1
ADO-AD7 lines. For Read operations (R/W = High),
the Address/Data bus is placed in a high-impedance
st.ate before driving 55 Low so that the addressed
device can put its data on the bus. The ZB6B1/B2
samples this data prior to raising OS High.
7.7 EXTENDED BUS TIMING
o
o
1
1
figure 7-8.
0
1
0
1
P3a
P3a
P3a
P3a
=' INPUT
= INPUT
= INPUT
= DAV1/RDY1
P34
P34
P34
P34
=
=
=
=
OUTPUT
OM
OM
RDY1/DAV1
Port J Data Met.ory Operation
7.6 BUS OPERATION
Typical data transfers between the ZB6B1/B2 and
memory are illustrated in Figure 6-6.
Machine
cycles can vary from six to twelve clock periods
depending on the operation being performed. The
notations used to describe the basic timing
periods of the ZB6B1/B2 are: machine cycles (Mn),
timing states (Tn), and clock periods. All timing
references are made with, respect to the output
signals AS and 55. The clock is shown for clarity
only and does not have a specific timing relationship with other signals.
The ZB6B1/82 accommodates slow memory access times
by automatically inserting an additional softwarecontrolled state time (Tx). This stretches the 55
timing by two clock periods. Timing is extended
by setting bit D5 in the Port 0-1 Mode register to
1 (Figure 7-9).
Refer to Section 6.7 for other figures pertaining
to extended bus timing.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
EXTERNAL MEMORY TlMINGJ·
NORMAL = 0
"EXTENDED = 1
"ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 7-9.
352
Extended Bus Timing
External Interface (Z8681,Z8682)
7.8
7.9 Z8681 RESET CONDITIONS
INSTRUCTION TIMING
The high throughput of the Z8681/82 is due, in
part, to the use of instruction pipelining, in
which the instruction fetch and execution cycles
are overlapped. During the execution of the current instruction the opcode of the next instruction is fetched as illustrated in Figure 6-10.
Figures 6-11 and 6-12 show typical instruction
cycle timing for instructions fetched from memory.
For those instructions that require execution time longer than that of the overlapped
fetch, or reference program or data memory as part
of their execution, the pipe must be flushed. Inorder to calculate the execution time of _ a program, the internal clock periods shown in the
cycles c,olumn of the instr.uction formats in Section5.6 should be added together. The cycles are
equal to one-half the crystal or input clock rate.
After a hardware reset, Port 0 is configured as
input port, extended timing is set to accommodate
slow memory access during the configuration
routine, DM is inactive, and the stack resides in
the register file. Figure 7-10 shows the binary
values reset into P01M.
7.10 Z8682 RESET mNDITIONS
After a hardware reset, Port .0 is configured as
address lines A8-A15' memory timing is normal, DM
.. is inactive, and the stack resides in the register
file. Figure 7-11 shows the binary values reset
into P01M.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
--l
P04 -P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
"EXTENDED = 1
~
POII-P03 MODE
00 = OUTPUT
01 = INPUT
1X = As-A"
L
STACK SELECTION
0= EXTERNAL
1 = INTERNAL
·ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 7-10.
Z8681 Port 0 and 1 Reset Conditions
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
--l
P04 -P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1
.
I L"'!o':!':.lW.~.
01 = INPUT
1X = As-A"
STACK SELECTION
0= EXTERNAL
1 = INTERNAL
'------
Figure 7-11.
P1 o-P1 7 MODE
10 = ADo-AD7'
Z8682 Porta 0 and 1 Reset Conditions
353
Chapter 8
Reset aDd Clock
8.1
RESET
clock rate (XTAL frequency divided by 2), OS is
forced Low and R/W remains High. (Zilog Z-BUS compatible peripherals use the AS and OS coincident
Low state as a peripheral reset function.)
In
addition, interrupts are disabled, Ports 0, 1, and
2 are put in input mode, and %C is loaded into the
Program Counter.
This section describes ZB reset conditions, reset
timing, and register initialization procedures.
A system 'reset overrides all other operating conditions and puts the ZB int.o a known state. To
initialize the chip's internal logic, the reset
input must be held Low for at least 1B clock
periods.
The hardware Reset initializes the control and
peripheral registers, as shown in Table B.l.
Specific reset values are shown by ls ,or Os, while
bits whose states are unknown a~e indicated by the
While RESEr is Low, AS is output at ,the internal
Table B-1. Control and Peripheral Register Reset Values
Register
D6 ~ D4
0,
Dz
D1
Do
%FO Serial I/O
%fl Timer Mode
undefined
0 0 0 0 0 0 0 0
%f2 Counter/Timer
undefined
%F3 Tl Prescaler
u u u ,u u u 0 0
%f4'Counter/Timer 0
%f5 TO Prescaler
undefined
u u u u u u u 0
%f6 Port 2 Mode
%f7 Port 3 Mode
'1
0 0 0 0 0 0 u 0
%fB Port 0-1 Mode
ZB601/ZB611
o1
%fB Port 0-1 Mode
ZB6B1
o
%fB Port 0-1 Mode
ZB6B2
%f9
%fA
%fB
%fC
%fD
%fE
%ff
354
0.,
Interrupt Priority
Interrupt Request
Interrupt Mask
flags
Register Pointer
Stack Pointer
Stack Pointer
o
o
1
o
o
0
o
o
Counter/Timers stopped
Single Pass count mode,
eKternal clock source
Single Pass count mode
All lines input
Port 2 open-drain
P30-P33 input; P34-P37 outpu,t
Ports 0 and 1 inputs;, internal stack;
eKtended eKternal memory timing
1
Port 0 inputs
Port ,1 Address/Data; internal stack;
e,Ktended eKternal memory timing
o
Port 0 Address
Port 1 Address/Data
internal stack; normal eKternal
memory timing
undefined
,u u 0 0 0 0 0 0
0 u u u u u u u
undefined
undefined
undefined
undefined
Reset all interrupt disabled
Interrupts disabled
Most significant byte
Least significant byte
Reset and Clock
letter u. Registers that are not predictable are
listed as undefined.
Program execution starts four clock cycles after
RESET has returned High. The initial instruction
fetch is from location %C. Figure 8-1 shows reset
timing.
After a reset, the first program executed should
be a routine that initializes the control registers to the required system configuration.
The
Interrupt Request register remains inactive until
an EI instruction is executed. This guarantees
that program execution can proceed free from
interrupts.
RESET is the input of a Schmitt trigger circuit.
To form the internal reset line, the output of the
trigger is synchronized with the internal clock
(xtal frequency divided by 2). The clock must
therefore be running for RESET to function. For a
power-up reset operation, the RESET input must be
held Low for at least 50 ms after the power supply
is within tolerance. This allows the on-board
clock oscillator to stabilize.
An internal
pull-up combined~ with an external capacitor of
1 eF provides enough time to properly reset the Z8
(Figure B-2).
B.2
CLOCK
The ZB derives its timing from on-board clock
circuitry connected to pins XTAL1 and XTAL2. The
clock circuitry consists of an oscillator, a
divide-by-2 shaping circuit, and a clock buffer.
Figure 8-3 illustrates the clock circuitry.
The
oscillator's input is XTAL1; its output is XTAL2.
The clock can be driven by a crystal, a ceramic
resonator, or an external clock source.
Crystals and ceramic resonators should have the
following characteristics to ensure proper oscillator operation:
Cut: AT (crystal only)
Mode: Parallel, Fundamental
Output Frequency:
1 MHz - 12 MHz
Resistance:
100 ohms max
Depending on operation frequency, the oscillator
may require the addition of capacitors C1 and C2
(shown in Figure B-4). The ral')ge of recommended
capacitance values is dependent on crystal specifications but should not exceed 15 pF. The ratio
of the values of C1 to C2 can be adjusted to shift
the operating frequency of the circuit by approximately :1:.005%.
FIRST MACHINE CYCLE
I
I-- FIRST INSTRUCTION FETCH
R/W
I
Figure B-1.
Reset TiJIIing
355
+5V
XTAL1
100
XTAL2
o-i
D--i"___
H
001
KQ
1K
OSC
'
Reset and Cloc k
+2
" ___
••
~INTERNAL
001~ CLOCK
BUFFER
RESET
Figure 8-}.
Z8 Clock Circuit
ZB
figure 8-2.
Pmmr-Up Reset Circuit
When an external frequency source is used, it must
drive both XTAL1 and XTAL2 inputs. This differential drive requirement arises from the loading on
the oscillator output (XTAL2) without the reactive
feedback network of a crystal or resonator.
A
typical clock interface circuit is shown in Figure
Figure 8-4. Crystal/Ceramic Resonator Oscillator
8-5.
The capacitors shown represent the maximum parasitic loading when using a 74LS04 driver.
The
pull-up resistors can be eliminated by using a
74He04 driver.
+5V
+5V
1.5k
74LS04
8.}
PONER-OOWN OPERATION
CLOCK
IN
1.5k
74LS04
:><>-....- ...-DI>O--.....-..-
I
The ZB has a power-down option which can be used
to maintain the contents of the register file with
a low-power battery. The circuitry has its XTAL2
output replaced by a power supply input (V MM ).
VMM powers the general-purpose registers %04 ?7F as well as a portion of the reset logic that
protects the vegister file.
When Vt.l t.1 is maintained at 3 to 5 V, this power-down option preserves the contents of the general-purpose registers whenever Vce is removed.
During normal
operation, VMM provides +5 V along with, Vec'
'--------1r
I
Figure 8-5.
XTAL2
=
15 pF MAX
CSTRAY
XTAL1
CSTRAY
=
15 pF MAX
External Clock Interface
The following sequence is necessary to preserve
data:
•
•
•
Power failure must be externally detected early
enough for a software routine to store the
required data that is not already in the register file.
An interrupt is typically used for
this purpose.
RESET must be held Low after data is saved and
during the removal of Vec'
RESET is a write
protect input to the register file.
356
RESE T must be held Low during the power-up
sequence.
Again, RESET is a wr ite protect
input to the register file.
As
Vec
powers
down,
on-board
circuitry
associated with RESET automatically protects the
general-purpose registers. The circuit shown in
Figure B-2 satisfies the power-up requirement of
holding RESET Low to protect the register file
data.
Reset and Clock
Figure 8-6 shows the recommended circuit configuration for a battery-backed supply system.
Since XTAL2 'is replaced by VMM , an external
clock generator must ,be used to input the Z8 clock
via the XTAL1 input.
+5V
Vee
TRICKLE
CHARGEfi
VMM
-=-.3.6V
Figure 8-6.
Test mode ill a special mode of operation that
facil i.tates testing of Z8 devices containing
on-board 'ROM (Z8601 and Z8611).
Test mode must
also be used to reset the Z8682. When Test mode is
invoked, an additional on-board ROM is mapped into
the first 64 locations of program memory. Figure
8-7 shows the di fference between Normal and Test
modes of operation.
Test mode is entered by driving
a voltage level of VCC + 2.5
Reset cycle (Figure B-B).
absolutely essential for proper
Z8
I
8.4 TEST til)[
the RESET input to
V after a normal
This voltage is
operation.
NiCAD
After entering Test mode, instructions are fetched
from the internal test ROM. Port 1 is configured
for Address/Data operation, followed by a JUMP to
external memory location :\l812 for the ZB601 and
Z8682, or :\l1012 for the Z8611. Once in external
memory, diagnostic routines, invoked via the
Battery-Backed Register Supply
ACCESS NORMAL
ROM ATOOCH
ACCESS TEST
ROMATOOCH
ON·CHIP
PROGRAM
ROM
%3F',,--~----"--------"------~%3F
%OC
USER
ROM
TEST
ROM
. .- - - - % 0 0
%00 ...- - - - - - -
Figure 8-7.
Normal
%OC
and
Test Mode Flow
357
Reset and Clock
Address/Data bus, verify the Z8' s funct ionalit.y.
Since Port 1 is used only in Address/Data mode in
this process, additional routines in the test ROM
verify Port 1's I/O and Handshake modes.
Programs run with lest mode act.ive can use the LDE
instruct ion to access contents of the test ROM.
The' LDC instruction accesses the normal program
ROM.
The Z8 stays in the Test mode until a normal reset
%80C, and %80F; interrupt vectors in the Z8611
point to external memory locations %1000, %1003,
1~1006, %1008. %100C, and %100F.
These interrupt
vectors allow the external program to have a 2- or
3-byte JUMP instruction to each interrupt service
routine.
Programs that are run with Test mode active can
use the LDE instruction for accessing the contents
of the Test ROM. The LDC instruction can be used
for accessing the program ROM as normal.
occurs.
8.4.2 ROHless Operation
8.4.1
Interrupt Testing
To test the interrupt structure, the first twelve
locations of test ROM contain interrupt vectors.
Interrupt vectors in the Z8601 and Z8682 point to
external memory locations %800, %803, %806, %809,
ROMless operation of the Z8601 or Z8611 can be
achieved by always entering Test mode after a
reset. Execution begins at %812 or %1012, respectively. (The Z8682 is a modified Z8601 sold as a
ROMless part.)
Vee + 2 . 5 V - - - - - _ _ _ _ VRH
6
_XTAlClKS_
MIN
RESET PIN
VRL-----
4
_XTAl_
ClKS
MAX
Note the maximum ramp for application of
+ 7.5 VDC to RESET pin. After a minimum of
6 XTAl ClK cycles, the RESET voltage can be
relaxed to VRH.
figure 8-8.
358
Voltage Waveform for Test Mode
Chapter 9
1/0 Ports
9.1
INTRODUCTION
9.1.2 Input and Output. Registers
The ZB has 32 lines dedicated to inpul and output.
These lines are grouped into four B-bit
ports and are configurable as input, output, or
address/data.
Under software control, the ports
can be programmed to provide address/data, timing,
status, serial, and parallel input/output with or
without handshake.
All' ports have active pull-ups and pull-downs
compatible with TTL loads.
In addition, the
pull-ups of Port 2 can be turned off for
open-drain operation.
9.1.1 Mode Registers
Each port has an associated mode register which
determines the port's functions and allows dynamic
change in port functions during program execution.
Ports and mode registers are mapped into
the register file as shown in Figure 9-1.
Because of their close association, ports and mode
registers are treated like any other general-purpos,e register. There are no special instructions
for port manipulation; any instruction that
addresses a register can address the ports. Data
can be directly accessed in the port register,
with no extra moves.
DEC
HEX IDENTIFIERS
PORTS 0-1 MODE
F6 P01M
247
PORT 3 MODE
F7 P3M
246
PORT 2 MODE
F6
248
P2M
Since port inputs are asynchronous to the ZB' s
internal clock, a Read operation could occur
during an input transition.
In this case, the
logic level might be uncertain--somewhere between
To eliminate this ·nieta-stable
a logic 1 and O.
condition, the ZB latches the input data two clock
perioda prior to the execution of the current
instruction.
The input register uses these two
clock periods to stabilize to a legitimate logic
level before the instruction reads the data.
9.2 PORT 0
This section deals only with the I/O operation of
Port O.
Refer to Sections 6.2 and 7.2 for a
description of the port's external' memory' interface ·operation.
Port 0 is a general I/O port. Bits within each
nibble can be independently programmed as inputs,
outputs or address. lines;
Figure 9-2 shows a
block diagram of Port O.
This diagram also
applies to Ports 1 and 2.
04
4
3
PORT 3
03
2
PORT 2
02 P2
P3
1
PORT 1
01
P1
o
PORTO
00
PO
figure 9-1.
Each bit of Ports 0, 1, and 2 has an input register, an output register, associated buffer, and
control logic. Since there are separate input and
output registers associated with each port, writing to bits defined as inputs. stores the data in
the output register. This data cannot be read as
long as the bits are defined as inputs. However,
i f the bits are reconfigured as output, the data
stored in the output register is reflected on the
output pins and can then be read. This mechanism
allows the user to initialize the outputs prior to
driving their loads.
I/O Port and Port Mode Registers
359
....
~
.......
o
....
o
INPUT REGISTER
A
A
8
...
...
8'
./"~
1
HANDSHAKE SELECTED
DAV/RDY
RDY/DAY
~
~
h.
')
8
r
8
r
OUTPUT ENABLE_
INTERNAL BUS
PORT UO
LINES
HANDSHAKE
LOGIC
WRITE
PORT
8
r
INTERNAL
TIMING
EQ-f
-
8
en
~
:1
~
-
("I"
Vi-
8
r-,.
READ
PORT
...
INPUT BUFFER
--------J
OUTPUT REGISTER
Figure 9-2.
-.----
OUTPUT BUFFER
Ports 0, 1, and 2 Block Diagr_
I/O Ports
9.2.1
Re~rite
Operations
In the nibble I/O mode, Port 0 is accessed as general-purpose register PO (%00). The port is written by specifying PO as an instruction's destination register. Writing the port causes data to be
stored in the port's output register.
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
=
The port is read by specifying PO as the source
register of an instruction. When an output nibble
is read, data on the external pins is returned.
Under normal loading conditions this is equivalent
to'reading the output register. Reading a nibble
defined as input also returns data on the external
pins. However, input bits under handshake control
return dilta latched into the input register via
the input strobe.
The Port 0-1 Mode register bits D1DO and D7D6 are
used to configure Port 0 nibbles (Figure 9-3).
The lower nibble (PO O-P0 3) can be defined as
inputs by setting bits D1 to 0 and DO to 1,'or as
outputs by setting both D1 and DO to O. Likewise,
the uppe,r nibble (P04-P07) can be defined as
inputs by setting bits D7 to 0 and D6 to 1, or as
outputs by' setting both D6,and D7 to O.
9.2.2 Handshake Operation
When used as an I/o port, Port 0 can be placed
under handshake control by programming the Port 3
Mode register bitD2 to 1 (Figure 9-4). In this
configuration, handshake control lines are DAVO
(P32) and RDYO (P35) when Port 0 is\an input port,
or RDYO (P32) and DAVO (P35) when Port 0 is an
output port.
Handshake direction is determined by the configuration (input or output) assigned to Port O's
upper nibble, P04-P07. The lower nibble must have
the same I/O configuration as the upper nibble to
be under handshake control.
Figure 9.,.5 illustrates the Port 0 upper and lower nibbles, and the
associated handshake lines of Port 3.
-r
--r.L
PO.-P07 MODE
. OUTPUT
00 ~
INPUT = 01
A'2-A'6 = 1X
POO-P03 MODE
00 = OUTPUT
01 = INPUT
1X = As-A11
figure 9-3. Port 0 I/O Operation
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
I
L, . . . "."
1 P32
figure 9-4.
=DAVO/RDYO
P3s
P3s
= OUTPUT
= RDYO/DAVO
Port 0 Handshake Operation
}
P04-P07
POO-P03
} PORT 0
(UO OR AS-A15)
HANDSHAKE CONTROLS
} DAVo AND RDYo
(pa. AND P3S>
figure 9-5. Port 0
Handshake operation is 'discussed in detail in Section 9.6.
361
I/O Ports
9.3 PORT 1
9.3.2 Handshake Operations
This section deals only with the I/O operation of
Port 1 and does not apply to the Z8681/82 ROMless'
devices. Refer to Sections 6.2 and 7.2 for a
description of the port's external memory interface operation.
When used as an I/O port, Port 1 can be placed
under handshake control by programming the Port 3
Mode register bits 04 and 03 both to 1 (Figure
9-7).
In this configuration, handshake control
lines are OAV 1 (P3 3) and ROY1 (P34 )·when Port 1 is
an input port, or ROY 1 (P3 3) and OAV 1 (P3 4 ) when
Port 1 is an output port.
Port 1 is a general-purpose I/O port that can be
programmed as a byte I/O port with or without
han!fshake, or as an address/data port for interfacing with external memory. Refer to Figure 9-2
for a block diagram of Port 1.
9.3.1
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
Read/Write Operations
In byte input or' byte output mode, the port is
acces.sed as general-purpose register P1 (%01).
The port is written by specifying P1 as an·
instruction's destination register. Writing the
port causes data to be stored in the port's output
register.
The port is' read by specifying P1 as the source
register of an instruction.
When an output is
read, data on, the external pins is returned.
Under normal loading conditions, this is equivalent to reading the output register. When Port 1
is defined as an input, reading also returns data
on the external pins. However, inputs under handshake control return data latched into the input
register via the input strobe.
Using the Port 0-1 Mode register, Port 1 is configured as an ou~put port by setting bits 04 and
03 to Os, or as an input port by setting 04 to 0
and 03 to 1 (Figure 9-6).
o
o
1
1
0
1
0
1
=
=
=
P33
INPUT
P33 = INPUT'
P33
INPUT
P33
DlWi/RDY1
P34 = OUTPUT
P34
OM
P34 = OM
P34 = RDY1/DAVl
=
Figure 9-7. Port 1 Handshake Operation
Handshake direction is determined by the configuration (input or output) assigned to Port 1. For
example, if Port 1 is an output port then handshake is defined as output.
Figure 9-8 illustrates the Port 1 lines and the associated handshake lines of Port 3.
Handshake operation is discussed in detail in Section 9.6.
R248 POiiiJi
Port 0-1 Mode Register
(% F8; Write Only)
PORT 1
(I/O OR ADo-AD7) P1o-P17
HANDSHAKE CONTROLS
} DAV1 AND RDY1
(P3s AND P341
P1 o-P1 7 MODE
00
BYTE OUTPUT
01
BYTE INPUT
10 = AD o-AD711 = HIGH·IMPEDANCE ADo-AD7.
. AS. OS. RtW. As-All. A12-A15
=
=
figure 9-6.
362
Port 1 I/O'Operation
figure 9-8.
Port 1
I/O Ports
9." PORT 2
9.4.2 Handshake Operation
Port 2 is a general-purpose port.
Each of its
lines can be independently programmed as input or
output via the Port 2 Mod~ register (Figure 9-9).
A bit set to a 1 in P2M configures the corresponding bit in Port 2 as an input, while a bit set to
o determines an output line.
Port 2 can be placed under handshake control by
programming the Port 3 Mode register (Figure
9-10). In this configuration, Port 3 lines P31
and P3 6 are used as the handshake control lines
OAV Z and RDY Z for input handshake, or RDY Z and
DAV Z for output handshake.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
R246 P2M
Port 2 Mode Register
(%F6; Write Only)
1~1~1~1~1~1~1~1~1
,1
...._____P20-1''27 MODE
,
0 OUTPUT
1 INPUT
Figure 9-9. Port 2 I/O Operation
9.".1
Read/Write Operations
o
1
Port Z is accessed as general-purpose register PZ,
(%OZ). The port is written by specifying P2 as an
instruction's destination register. Writing the
port causes data to be stored in the port's output
register, and reflected externally on any bit con~
figured as an output.
The port is read by specifying PZ as the source
register of an instruction. When an output bit is
read, data on the external pin is returned. Under
normal loading conditions, this is equivalent to
reading the output register. However, if a bit of
Port Z is defined as an open-drain output, the
data returned is the value' forced on the output
pin by the external system. This may not' be the
same as the data in the output regi~ter.
=
=
P3l
INPUT (TIN) P3s
OUTPUT (TOUT)
P3l = iiAii2JRDY2 P3s = RDY2Im2
Figure 9-10. Port 3 Handshake Operation
Handshake direction is determined by the configuration (input or output) assigned to bit '7 of Port
Z. Only those bits with the same configuration as
PZ7 will be under handshake control. Figure 9-11
illustrates Port Z's bit lines and the associated
handshake lines of Port 3.
P20
PORT 2(1/0)
Reading input bits of Port Z also returns data on
the external pins. However, inputs under handshake control return data latched into the input
register via the input strobe.
P27
'
HANDSHAKE CONTROLS
} DAVz AND RDYz
(P3l AND P3e)
Figure 9-11. Port 2
363
9.5
Port 2 can also by configured to provide opendrain outputs by programming Port 3 Mode register
(P3M) bit DO to 0 (Figure 9-12).
Port J differs structurally from the other three
ports.
Port J lines are fixed as four input
(PJO-P3J) and four output (P34-P37) and do not
have an input and output register for each bit.
Instead, all the input lines have one input r~gis
ter, and output lines have an output register.
Under software control, the lines can be configured as input or output, special control lines
for handshake, or as I/O lines for the o,n-board
serial and timer facilities.
Figure 9-13 is a
block diagram of Port 3.
Regardless of the bit input/output configuration,
Port 2 is always written and read as a byte-wide
port.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
,L
Figure 9-12.
9.5.1
0 PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
READ _
PORT
INPUT
BUFFER
A
'i
I
1\
...
4
,
'i
TO INTERRUPT TIMER, HANDSHAKE LOGIC
OR SERIAL 110
READ _
PORT
A
(
4
'4
PORT
INPUT
LINES
(P30-P3a)
A
4
4
~
Read/Write Operations
Port 3 is accessed as general-purpose register P'
(%03). The port is written by specifying P3 as an
instruction's destination register.
However,
Port 2 IlpeJH)rain Outputs
INPUT
REGISTER
A
PORT'
)
OUTPUT
DATA
RETURN
BUFFER
0r-
OUTPUT
REGISTER
OUTPUT
BUFFER
WRITE ~
PORT
~
4
:)
4
-
~I
FROM TIMER, HANDSHAKE LOGIC
OR SERIAL 1/0
INTERNAL
BUS
Figure 9-13.
364
'",
r
...
Port' Block Oiagran
...
~
4
y
PORT
OUTPUT
LINES
(P34-P37)
I/O Ports
Port 3 outputs cannot be written i f they are used
for special functions.
When writing to Port 3,
data is stored in the output register.
Table 9.1
Port JLine functions
function
Line
Signal
The port is read by specifying P3 as the source
register of an instruction.
When reading from
Port 3, the data returned is both the data on the
input pins and in the output register.
Input
Output
P30-P33
P34-P37
Input
Output
Handshake
Inputs
9.5.2 Special functions
Handshake
Outputs
P3 1
P32
P33
P3 4
P35
P36
OAV 2/ROY Z
OAVO/ROYO
OAV 1/ROY 1
RDY 1/DAV 1
RDYO/DAVO
ROY Z/ crAV 2
P30
P31
P32
P33
IRQ3
IRQZ
IRQO
IRQ1
Special functions for Port 3 are defined by programming the Port 3 Mode register. By writing Os
in 02-06' lines P30-P37 ar configured in input/
output pairs (Figure 9-14).
Table 9-1 shows
available functions for Port 3.
The special
functions indicated in the table are discussed in
detail in their corresponding sections in this
manual.
Port 3 input lines P30-P33 always function as
interrupt requests regardless of the configuration
specified in the Port 3 Mode register. Unwanted
interrupts must be masked 0 ff as described in
Chapter 10.
Interrupt
Requests
Serial Input
Output
51
SO
Counter/Timer
Status
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
I0 10 10.1 0 10 1
6
5
3
2
L," -""
1 P32 = DAVO/RDYO
o 0 P33 = INPUT
'------~ ~}P33
= INPUT
1 1 P33 = DAV1/RDY1
P3s = OUTPUT
P3s = RDYO/DAVO
P34 = OUTPUT
P34 = OM
P34= RDY1/DAV1
o P31 = INPUT (TIN) P3s = OUTPUT (TOUT)
' - - - - - - - - - 1 P31 = OAV2/RDY2 P3s = RDY2IDAV2
o P30 = INPUT
' - - - - - - - - - 1 P30 = SERIAL IN
figure 9-14.
P37 = OUTPUT
P37 = SERIAL OUT
Port J I/O Operation
365
I/O Ports
9.6 PORT HANDSHAKE
When Ports 0, 1, or 2 are configured for handshake operation, a pair of lines from Port 3 is
used for handshake controls for each. port.
The
handshake controls are interlocked to properly
time asynchronous data transfers between the ZS
and its peripheral. One control line (DAV n ) functions as a strobe from the sender to indicate to
the receiver that' data is available.
The second
control line (ROY n ) acknowledges receipt of the
sender's data, and indicates when the receiver is
ready to accept another data transfer.
In the input mode, data is latched into the port's
input register by the first OAV signal, and is
protected from being overwritten if additional
pulses occur on the OAV line. This overwrite protection is maintained until the port data is
read.
In the output mode, data written to the
port is not protected and can be overwritten by
the ZS during the handshake sequence.
To avoid
losing data, the software must not overwri,te the
port until the corresponding interrupt request
indicates that the external device has latched the
data.
Following is the recommended setup sequence when
configuring a port for handshake operation for
the first time after a reset:
•
Load P01M or P2M to configure the port
input/output.
•
Load P3 to set the Output Handshake bit to a
logic 1.
•
Load P3M to se lect the Handshake mode for the
port.
Once a data transfer begins, the configuration of
the handshake lines should not be changed until
handshake is completed.
Figures 9-15 and 9-16 show detailed operation
for the handshake sequence.
In applications requiring a strobed signal instead
of the interlocked handshake, the ZS can satisfy
this requirement as fo 11ows:
•
In the Strobed Input mode, data can be latched
in the port input register using the OAV
input.
The data transfer rate must allow
enough time for the software to read the port
before strobing in the next character. The ROY
output is ignored.
•
In the Strobed Output mode, the
should be tied to the OAV output.
The software can always read Port 3 output. and
input handshake lines, but cannot write to the
output handshake lines.
2
3
4
5
DAV
(INPUT TO Z8)
RDY
(OUTPUT FROM Z8)
--+-,
DATA ON PORT
(INPUT TO Z8)
State 1. Port 3 Ready output is High, indicating that the Z8 is ready to accept data.
State 2. The 1/0 device puts data on the port and then activates the rJlW input. This causes
the data to be latched into the port input register and generates an interrupt reo
quest.
State 3. The Z8 forces th.e Ready (RDY) output Low, Signaling to the 1/0 device that the
data has been latched.
State 4. The 1/0 device returns the DAV line High in response to RDY going Low .
. State 5. The Z8 software must respond to the interrupt request and read the contents of
the port in order for the handshake sequence to be completed. The RDY line goes
High if and only if the port has not been read and rJlW is High. This returns the in·
terface to its initial state.
Figure 9-15.
366
for
Z8 If1Jut Handshake
ROY
input
I/O Ports
2
3
4
5
ROY
(INPUT TO Z8)
DAV
(OUTPUT FROM Z8)
DATA ON PORT
(OUTPUT FROM Z8)
VALID DATA
State 1. ROY input Is High indicating that the 110 device is ready to accept data.
State 2. The Z8 writes to the port register to initiate a data transfer. Writing the port outputs
new data and forces ~ Low if and only if ROY is High.
State 3. The 110 device forces ROY Low after latching the data. ROY Low causes an interrupt request to be generated. The Z8 can write new data in response to ROY going
Low; however. the data is not output until State 5.
State 4. The OAV output from the Z8 is driven High in response to ROY going Low.
State 5. After OAV goes High, the 110 device is free to raise ROY High thus returning the interface to its initial state.
Figure 9-16.
Figures 9-17 and 9-18
handshake connections.
P2o-P27
illustrate
the
strobed
I
~
~
1/0
Z8
Z8 Output Handshake
9.7
I/O PORT RESET CONDITIONS
After a hardware reset, mode registers P01M, P2M,
and P3M are set as shown in Figures 9-19 - 9-22.
Ports 0, 1 and 2 are configured for input operation on all bits, except Port 1 in the Z8681 and
Ports 0 and 1 in the Z86B2 as shown.
DEVICE
The pull-ups of Port 2 are set for open-drain. If
acti ve pull-ups are desired for Port 3 outputs,
remember to configure them using P3M (Figure
9-22) •
DAV
P3l
Figure 9-17.
Input Strobed Handshake
using Port 2
All special I/O functions of Port 3 are inactive,
with P30-P33 set as inputs and P3 4-P3 7 set as
outputs (Figure 9-23) •
....
)
.-
P2o-P27
1/0
Z8
DAV
P3s
P3l
Figure 9-18.
ROY
DEVICE
1
Output Strobed Handshake
using Port 2
367
I/o Ports
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
PO,-P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
"EXTENDED = 1
I [ ,~,~, ~~,'!,~,
01 = INPUT
1X = As-A"
STACK SELECTION
. ~,~ F~J::~:C
P1 o-P1 7 MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH·IMPEDANCE ADo-AD7.
AS. OS. R/W. As-A". A'2-A'5
'ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 9-19.
Z8601/11 Port 0 and 1 Reset
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
PO,-P0 7 M O D E : ]
OUTPUT = 00
INPUT = 01
.
A'2-A'5 = 1X
I
'":;;'~' ~.:;~~,
[
01 = INPUT
1X = As-A"
EXTERNAL MEMORY TIMING
NORMAL = 0
"EXTENDED = 1
STACK SELECTION
0= EXTERNAL
1 = INTERNAL
'ALWAYS EXTENDED TIMING AFTER RESET EXCEPT Z8682
Figure 9-20.
Z8681 Ports 0 and 1 Reset
R248 P01M
Port 0-1 Mode Register
(% F8; Write Only)
PO,-P07 M O D E : ]
OUTPUT = 00
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1
I
[
,
'------
Figure 9-21.
368
"'80~~~~,
01 = INPUT
1X = As-A"
STACK SELECTION
0= EXTERNAL
1 = INTERNAL
P1 o-P1 7 MODE
10 = ADo-AD7
Z8682 Ports 0 and 1 Reset
I/O Ports
R246 P2M
Port 2 Mode Register
(% F6; Write Only)
11111111111111111
I
P2o-P27 MODE
0 OUTPUT
1 INPUT
L . . .- - - -
Figure 9-22.
Port 2 Reset '
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
1 0 10 1 0 1 0 1 0 1 0 1 ? 1 0
1
II L, "'"' """'" 0'''',..."
1 PORT 2 PULL·UPS ACTIVE
RESERVED
=INPUT
o 0 P3a = INPUT
1..--'--_ _ _ ~ ~} P3a = INPUT
= OUTPUT
P34 = OUTPUT
P34 = DM
o P32
1 P~
= DAVO/RDYO P3s = RDYO/DAVii
1 1 P3a
= DAV1/RDY1 P34 = 'RDY1/DAV1
I..-_ _ _ _ _~O
=
P3s
=
P3l
INPUT (TIN) P3s
OUTPUT (Tour)
1 P3l = DAV2IRDY2 P3s = RDY2IDAV2
o PSQ = INPUT
SERIAL IN
'~-------1 P30
'--_________
figure 9-23.
=
P37 = OUTPUT
P30
SERIAL OUT
=
~ ~~=:~~ g~F
Port 3 Reset
369
Chapter 10
. Interrupts
10.1
INTRODUCTION
10.2
The 'Z8 microcomputer allows six different interrupt levels from eight sources: the four Port 3
lines P30-P33 make up the external interrupt
sources while serial in. serial ·out. and the two
counter/timers make up the internal sources.
These interrupts can be masked and their priorities set by using the Interrupt Mask and the
Interrupt Priority registers. All six interrupts
can be globally disabled by resetting the master
Interrupt Enable bit 07 in the Interrupt Mask register with a Disable Interrupt (Dl) instruction.
Interrupts are globally enabled by setting 07 with
an Enable Interrupt (El) instruction.
There are three interrupt control regieters: the
Interrupt Requeat register (IRQ). the Interrupt
Mask. register (lMR). and the Interrupt Priority
register (IPR) • Figure 10-1 shows addresses and
identifiers for the interrupt control registers.
figure 10-2 is a block diagram· showing the
Interrupt Mask and Interrupt Priority logic.
INTERRUPT SOURCES
Table 10-1 presents the interrupt types. sources.
and vectors available in the Z8 family of
processors.
10.2.1
External Interrupt Sources
External sources invol ve interrupts request lines
IRQO-IRQ3- IRQO' IRQ1' and IRQ2 are always generated by a negative edge Signal on the corresponding Port 3 pin (P32' P33. PJ1 correspond to
IRQO' IRQ1. and 1RQ2. respectively). Figure 10-3
is a block. diagram for interrupt sources IRQO.
IRQ1. and IRQZ.
When the ·Port. 3 pin (PJ1 • P32 • or PJ3) goes Low.
the first flip-flop is set.
The next t.wo flipflops synchronize the request to the internal
clock and delay it· by four external clock
periods. The 'output of the last flip-flop (IRQO'
IRQ1. or IRQ3) goes to the corresponding Interrupt
Request register.
The Z8 family' supports both vectored and polled
interrupt handling.
Details on vectored and
polled interrupts can be found in Sections 10.6
and 10.7.
DEC _ - - - - -...... HEX
IRQO-IRQ5
IDENTIFIERS
251
INTERRUPT MASK
FB
IMR
250
INTERRUPT REQUEST
FA
IRQ
249
INTERRUPT PRIORITY
F9
IPR
6
GLOBAL
INTERRUPT
ENABLE
INTERRUPT
REQUEST
figure 10-1.
Interrupt Control Registers
VECTOR SELECT
figure 10-2.
.370
Interrupt Block Diagr_
Table 10-1.
Interrupt Types, Sources, and Vectors
Vector
location
Name
Source
IRQO
DAVO' IRQO
0,1
External ( P3 2)'
t Edge Triggered
IRQ1
DAV1' IRQ1
2,3
External (P33)'
t Edge Triggered
IRQ2
DAV2' IRQz, TIN
4,5
External (P3 1 ),
V Edge
IRQ3
6,7
External ( P30),
t Edge Triggered
Serial In
6,7
Internal
TO
8,9
Internal
Serial Out
8,9
Internal
T1
10,11
Internal
COIIIIIents
IRQ3
Triggered
IRQ4
IRQS
a negative edge signal on P3 0 as shown in Figure
10-4. Again, the external request is synchronized
and delayed before reaching IRQ.
IRQ3 can be generated from an external source only
i f Serial In is not enabled; otherwise, its source
is internal. The external request is generated by
iI--- IR03
1 = IR03 > IR05
~
T
INTERRUPT GROUP PRIORITY
RESERVED = 000
C > A > B 001
A > B > COlO
A > C > BOll
B> C > A
100
C > B> A
101
B> A> C
110
RESERVED
111
L_+-I__
IROO, IR02 PRIORITY (GROUP B)
o = IR02 > IROO
1 = IROO > IR02
IR01, IR04 PRIORITY (GROUP C)
o = IROl > IR04 - - - - - - - -.....
1 = IR04 > IROl
Figure 10-7.
Interrupt Priority Register
Table 10-2.
Priority
Highest
lowest
Group
Bit
C
°1=0
1
B
°Z=O
1
A
Interrupt Priority
°5=0
1
IRQl
IRQ4
IRQ4
IRQl
IRQZ
1RQO
IRQO
IRQZ
IRQS
IRQ 3
IRQ3
1RQS
Bit Pattern
°4
°z
°0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
'1
Group Priority
Highest --> lowest
NOT USED
CAB
ABC
A C 8
BCA
CBA
BAC
NOr USED
373
10.4.2 Interrupt Mask Register (IMR)
Initialization
IMR (Figure 10-B) individually or globa~ly enables
or disables the six interrupt requests. When bits
~O-OS' are set to 1, th,: correspo'nding interrupt
requests are, enabled. 07 is the master enable and
must be set before any of the individual interrupt
requests can be recognized. Resetting 07 globally
disables all of the interrupt requests. 07 is set
and reset by the El and 01 instructions. It is
automatically reset during an interrupt machine
cycle and Bet following the execution of an
'Interrupt Return (IRET) instruction.
NOTE
07 must be reset by the 01 instruction
before the contents of the Interrupt
Mask register or the Interrupt Priority
register are changed except:
•
•
Immediately after a hardware, reset,
or
Immediately after executing an interrupt cycle and before 1MR7 has been
set by any instruction.
10.4.3 Interrupt ,Request (IRQ) Register
Initialization
IRQ (Figure 10-9) is a read/write register that
stores the interrupt requests for both vectored
and polled interrupts. When an interrupt is made
on any of the six levels, the corresponding bit
position in the register is set to 1. Bits 00-05
are assigned to interrupt requests lRQO-IRQ5'
respectively.
R2511MR
Interrupt Mask Register
(% FB; Read/Write)
IRQ is held in a Reset state until an EI instruction is executed. For polled processing, IRQ must
still be initialized by an EI instruction, but IMR
should first be cleared to 0 to individually
inhibit all interrupt requests while interrupts
are globally enabled:
CLR
IMR
El
01
10.5 IRQ SOFTWARE INTERRUPT GENERATION
IRQ can be used to generate software interrupts by
specifying IRQ as the destination of any instruction referencing the register file. These Software Interrupts (SWI) are controlled in the same
manner as hardware-generated requests, i.e., the
IPR and the IMR control the priority and enabling
of each SWI level.
To generate an SWI, the desired request bit in the
IRQ is set as follows:
OR IRQ,HIRQLVL
where the immediate data, IRQLVL, has a 1 in the
bit position corresponding to the level of the SWI
desired.
For example, if an SWI on level 5 is
desired, IRQLVL would have a 1 in the bit 5 position:
OR IRQ ,1/%200100000 '
where the immediate data is preceded by %2 to
indicate a binary constant.
With this instruction, if the interrupt system is globally enabled,
level 5 is enabled, and there are no higher priority pending requests, control is transferred to
the service routine pointed to by the level 5
vector.
R250 IRQ
Interrupt Request Register
(% FA; Read/Write)
1 ENABLES IRQO
1Ds 1D_I D31 D21 D, 1Do I
~
I
1 ENABLES IRQ1
1 ENABLES IRQ2
1 ENABLES IRQ3
L'RQO
L..=IRQ1
1 ENABLES IRQ4
1 ENABLES IRQ5
IRQ3
L-_______
' - - - - -_ _ _ IRQ4
IRQ5
1 ENABLES INTERRUPTS
figure 10-8.
374
Interrupt Hask Register
IRQ2
Figure 10-9.
Interrupt Request Register
Interrupts
SP AND STACK
AFTER INTERRUPT
SPANO STACK
BEFORE INTERRUPT
TOP OF STACK
I
SP
~
PCL
PCu
FLAGS
figure 10-10. Effect of Interrupt on Stack
10.6.1
64Kr-------------~
Vectored Interrupt Cycle Tiaing
Interrupt cycle timing for all ZB devices except
the ZB6B1 is diagrammed in Figure 10-12. Timing
for the Z86B1 ROMless device is different and is
shown in Figure 10-13.
INTERRUPT
SERVICE
ROUTINE
10.6.2 Nesting of Vectored Interrupts
VECTOR SELECTED BY
PRIORITY LOGIC
0------""
Nesting
priority
request.
do the
routine:
of vectored interrupts allows higher
requests to interrupt a lower priority
To initiate vectored interrupt nesting,
following during the interrupt service
Z8 PROGRAM MEMORY
Figure 10-11.
Interrupt Vectoring
10.6 V[CTORED PROCESSING
Each ZB interrupt level has its own vector. When
an interrupt occurs, control passes to the service
routine pointed to by the interrupt's location in
program memory. The sequence of events for vectored interrupts is as follows:
•
•
•
D
•
•
PUSH PC lower byte on stack
PUSH PC upper byte on stack
PUSH FLAGS on stack
Fetch upper byte of vector
Fetch lower byte of vector
Branch to service routine specified by vector
Figures 10-10 and
interrupt operation.
10-11
show
the
vectored
o Push the old IMR on the stack.
• Load IMR with a new mask to disable lower
priority interrupts.
• Execute EI instruction.
• Proceed with interrupt processing.
• After processing is complete, execute DI
instruction.
• Restore the IMR to its original value by
returning the previous mask from the stack.
• Execute IRET.
Depending on the application, some simplification
of the above procedure may be possible.
10.7 Plum PROCESSING
Polled interrupt processing is supported by
masking off the IRQ levels to be polled. This is
accomplished by clearing the corresponding bit in
the IMR to O.
375
Interrupts
To initiate polled processing, check the bits of
interest in the IRQ using the Test Under Mask (TM)
instruction. If the bit is set, call or branch to
the service routine. The service routine services
the request, resets its Request bit in the IRQ,
and branches or returns back to the main program.
An example of a polling routine is'as follows:
TM IRQ,ilMASK
JR Z NEXT
CALL SERV [CE
!Test for request
!If no request go to NEXT
!If request is there
! then service it
NEXT:
SERVICE:
!Process Request
AND IRQ,UMASK_ !Clear Request bit
!Return to next
RET
In this example, i f IRQ2 is being polled, MASK
will be 1~200000100 (in binary) and MASK_ will be
%211111011.
376:
10.8 RESET CONDITIONS
During a reset, all bits in IPR are undefined.
In IMR, bit D7 is 0 and bits DO-D5 are undefined.
Bit D6 is not implemented, though reading this bit
returns O.
IRQ bits DO-D5 are held at 0 until an EI instruction is executed. Bits D6 and D7 are not implc.llented, but reading these bits returns O.
.....
:l
.....
CD
!_Mt_j...----M2_I_
M3_I_STACKPUSH_!-STACKPUSH_I_STACK
PUSH~I~7_l-Ml_I_M2-
INTERNAL
CLOCK
"0
.....
til
L-1
Os
ADO~AD7
OUT
I·· --
(ro"~,"~, ~=~
G
_
LJ.
1_______
..,,~
B
ADO·AD7 IN
1
'r---L.=J
--ro..__.m....L
~I
~
"CJ
~_""" = .....,,"
G'
SP-1 ,
PCL
, SP-2'
PC,
SP-3'
FLAGS
'FLAGS'
OPCODE (DISCARDED)
.
RlW
,
D
VEcd
FIRST INSTRUCTION OF INTERRUPT
SERVICE ROUTINE
_II
L....--I
....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....I-FOA STACK EXTERNAL ONLY
Figure 10-12.
ROM Z8 Interrupt Timing (shrink parts)
I-Ml_I_M2-------+-l-M3_!-STACK PUSH_I_STACK pusH_I_STACK pusH-.I_VEC~~;~IGH_I_VEciTEJ~~ow-.I_Ml~_M2_
INTERNAL
CLOCK
Os
ADo- AD7 OUT
ADO-AD7IN
G
8
o
1 SP-1 1
PCl
1 SP-21
pc,
1 SP-3'
FLAGS
1
1--..
EVEN VECTOR ADDRESS-----
r-1-
ODD
VE~DRES~
'VECT.,
D-OPCODE (DISCARDED)
I VEer I
'VECTL'
D~
VECT+1
D~
FIRST INSTRUCTION OF INTERRUPT SERVICE ROUTINE--'"
RlW
[-----
Figure 10-13.
U)
::j
..,..,c:
I--FOR STACK EXTERNAL ONLY
Z8681 ROHless Z8 Interrupt Tieing
Chapter 11
Counter/Timers
11.1
INTRODUCTION
The Z8 provides two 8-bit counter/timers, TO and
r l' each driven by its own 6-bit prescaler, PRE O
and PRE1 • Both counter/timers are independent of
the processor instruction sequence, which relieves
software from time-critical operations such_ as
interval timing or event counting.
Each counter/timer operates in either Single-Pass
or Continuous mode. At the end-of-count, counting
either stops or the initial value is reloaded and
counting cant inues. Under software control, new
values are loaded immediately or when the end-ofcount is reached. Software also controls counting
mode, how a counter/timer is started or stopped,
and its use of I/O lines. Both the counter and
prescaler registers can be altered while the
counter/timer is running.
INTERNAL DATA BUS
WRr
OSC
~
.,.2
.,.4
-
~1.
WRr
~j..
RErl1
PREO
INITIAL VALUE
REGISTER
TO
INITIAL VALUE
REGISTER
TO
CURRENT VALUE
REGISTER
~
~
f~
6·BIT
DOWN COUNTER
r-
8·BIT
DOWN COUNTER
IRQ4
INTERNAL
CLOCK
SE RIAL 110
CLOCK
To UT
P3s
.,.2
EXTERNAL CLOCK
CLOCK
LOGIC
1\
.,.4
L=D-
IR Q5
6·BIT
DOWN COUNTER
r--
8·BIT _
DOWN COUNTER
_ll
II
~7
PRE1
INITIAL VALUE
REGISTER
T1
INITIAL VALUE
REGISTER
T1
CURRENT VALUE
REGISTER
INTERNAL CLOCK
GATED CLOCK
TRIGGERED CLOCK
TIN P31
WRtE
II
WJTE
II
INTERNAL DATA BUS
r igure 11.,.1. Counter/T ilIIer Block Oiagrllll
378
REt
jJ.
Counter/Timers
Counter/timers 0 and 1 are driven by a timer clock
generated by dividing the internal clock by four.
The divide-by-four stage, the 6-bit prescaler, and
the a-bit counter/timer form a synchronous 16-bit
divide chain. Counter/timer 1 can also be driven
by an external input (TIN) via Port 3 line P3 1 •
Port 3 line P3 6 can serve as a timer output
(TOUT) through which TO' T1 , or the internal
clock can be output. The timer output will toggle
at the end-of-count.
Figure 11-1 is a block
diagram of the counter/timers.
register which holds the initial count value, and
a read-only register which holds the current count
value (Figure 11-1). The initial value can range
from 1 to 256 decimal (%01,%02, •• ,%00).. Figure
11-5 illustrates the counter/timer registers.
R245 PREO
Prescaler 0 Register
(% F5; Write Only)
l
The counter/timer, prescaler, and associated mode
registers are mapped into the register file as
shown in Figure 11-2. This allows the software to
treat the counter/timers as general-purpose
registers, and eliminates the need for special
instructions.
11.2 PRESCAlERS AND COUNTER/TIMERS
The prescalers, PRE O (%F5) and PRE 1 (%F3), each
consist of an a-bit register and a 6-bit
down-counter as shown in Figure 11-1.
The
prescaler registers are write-only registers.
Reading the prescalers returns the value %FF.
Figures 11-3 and 11-4 show the prescaler
registers.
The six most significant bits (02-07) of PRE O or
PRE 1 hold the prescalers count modulo, a value
from 1 to 64 decimal.
The prescaler registers
also contain control bits that specify fO and T1
counting modes. These bUs also indicate whether
the clock source for T1 is internal or external.
These control bits will be discussed in detail
throughout this chapter.
The' counteritimers, TO (%F4) and T1 (%F 2)' each
consist of an a-bit down-counter, a write-only
RESERVED (MUST BE 0)
PRESCALER MODULO
'--------(RANGE: 1-64 DECIMAL
01-00 HEX)
Figure 11-3.
Preacaler 0 Register
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
[
COUNT MODE
1 = T, MODULO·N
o = T, SINGLE·PASS
CLOCK SOURCE
1 = T, INTERNAL
o = T, EXTERNAL (TIN)
PRESCALER MODULO
'-------(RANGE: 1-64 DECIMAL
01-00 HEX)
figure 11-4.
Preacaler 1 Register
HEX IDENTIFIERS
DEC
247
COUNTMODE
0= ToSINGLE·PASS
1 = To MODULO·N
PORT 3 MODE
F7
P3M
245
TO PRESCALER
F5
PREO
244
TIMER/COUNTER 0
F4
TO
243
T1 PRESCALER
F3
PRE1
242
TIMER/COUNTER 1
F2
T1
241
TIMER MODE
F1
TMR
R242 T1
CounterlTimer 1 Register
(% F2; Read/Write)
R244 TO
CounterlTimer 0 Register
(% F4; Read/Write)
I~I~I~I~I~I~I~I~I
L
INITIAL VALUE WHEN WRITIEN
(RANGE 1·256 DECIMAL, OHIO HEX)
CURRENT VALUE WHEN READ
379
Counter /Timer s
11.} aJJN1ER/TII£R OPERATIlfI
Under software control, counter/timers are started
and stopped via the Timer Mode register (%F1) bits
DO-D} (Figure 11-6). Each counter/timer is associated with a Load bit and an Enable Count bit.
11.}.1
load and Enable Count Bits
Setting the Load bit (DO to 1 for TO and'D2 to 1
for T1) transfers the inHial value in the prescaler and the counter/timer registers into their
respective down-counters. The next internal clock
resets bits DO and D2 to 0, readying the Load bit
for the next load operation. The initial values
may be loaded into the down-counters at any time.
IF the counter/timer is running, it continues to
do so and starts the count over with the initial
value. Therefore, the Load bit actually Functions
as a software re-trigger.
The counter/timers remain at rest as long as the
Enable Count bits D1 and D} are both O. To enable
counting, the Enable Count bit (D 1 For TO and D3
for T1) must be set to 1.
Counting actually
starts when the Enable Count bit is written by an
instruction.
The first decrement occurs four
internal clock periods after the Enable Count bit
has been set.
The Load and Enable Count bits can be set at the
same time. For example, using the instruction OR
TMR I!%O} sets both DO and D1 of TMR to 1. This
loads the initial values of PRE O and TO into their
respective counters and starts the count after the
M2T2 machine state after the operand is fetched
(Figure 11-7).
11.}.2 Prescaler Operations
During counting, the programmed clock source
dr i ves the presca ler 6-bit counter. The counter
is counted down from the value specified by bits
D2-D 7 of the corresponding prescaler register,
PRE O or PRE 1 (Figure 11-8). When the prescaler
counter reaches its end-oF-count, the initial
value is reloaded and counting continues.
The
prescaler never actually reaches O. For example,
if the prescaler is set to divide by 3, the ~ount
sequence is:
both reach their end-of-count, an interrupt
request is generated -- IRQ4 for r 0 and IRQ5 For
T1. Depending on the counting mode selected, the
counter/timer will either come to rest with its
value at %00 (Single-Pass mode) or the initial
value will be automatically reloaded and counting
will continue (Continuous mode).
R241 TMR
Timer Mode Register
(% F1; Read/Write)
L 10 == NO
FUNCTION
LOAD To
~
.
o=
NO FUNCTION
1 = LOAD T,
= DISABLE T, COUNT
1 = ENABLE T, COUNT
L.._ _ _ _ 0
Figure 11-6.
Timer Hode Register
TMR IS WRITIEN
COUNTERITIMERS
ARE LOADED
1ST DECREMENT
OCCURS FOUR
CLOCKS LATER
Figure 1;-7.
380
Starting The Count
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
R245 PREO
Prescaler 0 Register
(% F5; Write Only)
L
COUNT MODE
1 = T, MODULO·N
o = T, SINGLE·PASS
3-2-1-3-2-1-3-2 ••••
Each time the prescaler reaches its end-of-count a
carry is generated, which allows the counter/timer
to decrement by one on the next timer clock
input.
When the counter/timer and the prescaler
0 = DISABLE To COUNT
1 = ENABLE To COUNT
Figure 11-8.
Counting Hodes
Counter/Timers
The counting modes are controlled by bit DO of
PRE O and PRE 1 , with DO cleared to 0 for
Single-pass counting mode or set to 1 for
Continuous mode.
The counter/timers can be stopped at any time by
setting the Enable Count bit to 0, and restarted
by setting it back to 1. The counter/timer will
continue its count value at- the time it was
stopped.
The current value in the counter/timer
(TO or T1 ) can be read at any time without
afFecting the counting operation.
New initial values can be written to the prescaler
or the counter/timer registers at any time. These
values will be transferred to their respective
down-counters on the next load operation. IF the
counter/timer mode is Continuous, the next load
occurs
on the
timer
clock
following
an
end-oF-count.
New initial values should be
written beFore the desired load operation, since
the prescalers always effectively operate in
Continuous count mode.
register P3M (%F7) (Figure 11-9) to conFigure P3 6
For TOUT operation.
In order For TOUT to
Function, P3 6 must be deFined as an output line by
setting P3M bit D5 to O. Output is controlled by
one of the counter/timers (TO or T1) or the
internal clock.
The counter/timer to be output is selected by TMR
bits D7 and D6 •
TO is selected to drive the
TOUT line by setting D7 to 0 and D6 to 1.
Likewise, T1 is selected by setting D7 and D6 to 1
and 0 respectively. The counter/timer TOUT mode
is turned oFf by setting TMR bits D7 and D6 both
to 0, freeing P3 6 to be a data output line.
TOUT is initialized to a logic 1 whenever the
TMR Load bit (DO for TO or D2 for T1 ) is set to 1.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
The time interval (i) until end-of-count, is give!)
by the equation
i=txpxv
in which t is 6 divided by XTAL Frequency, p is
the prescaler value (1 - 64), and v is the
counter/timer value (1 - 256).
It should be
apparent that the prescaler and counter /timerare
true divide-by-n counters.
11.4
TOUT HODES
The Timer Mode register TMR (%Fl) (Figure 11-10)
is used in conjunction with the Port 3 Mode
o
1
=
=
P3,
INPUT (TIN) P3&
OUTPUT (TOUT)
P3, = DAV2JRDY2 P3& = RDY2J1iAI12
Figure 11-9.
Port 3 Mode Register TOUT Operation
R241 TMR
Timer Mode Register
, (% F1; Read/Write)
TOUTMODESJ
TOUT OFF = 00
To OUT = 01
Tl OUT = 10
INTERNAL CLOCK OUT = 11
L
0 = NO FUNCTION
1 = LOAD To
o=
NO FUNCTION
1 = LOAD T,
Figure 11-10.
Tiller Hode Register TOOT Operation
381
Counter/Timers
IR04
TMR
(TO ENO·OF·COUNT) - - - - - - . 07-06 = 01
..--",
+2
IROS
(T1 ENO·OF·COUNT)
-.-J
&
TOUT
TMR
07-06 = 10
Figure 11-11. Counter/Tiaers Output Via TOUT
INTERNAL
CLOCK
--r-'\.....J
TMR 06
TMR07~
figure 11-12.
Internal Clock' Output Via TOUT
At end-oF-count, the interrupt request line (IRQ4
or IRQ5)' clocks a toggle flip-flop. The output
of this Flip-Flop drives the TOUT line, P3 6 • In
all cases, when the selected counter/timer reaches
its end-oF-count, TOUT toggles to its opposite
state (Figure 11-11).
If, For example, the
counter/timer is in Continuous counting mode,
TOUT will have a 50% duty cycle output.
This
duty cycle can easily be controlled by varying the
initial values aFter each end-oF-count.
The internal clock can be selected as output
instead of TO or T1 by setting TMR bits D7 and D6
both to 1. The internal clock (XTAL Frequency/2)
is then directly output on P3 6 (Figure 11-12).
While programmed as TOUT> P3 6 cannot be modified
by a writ~ to port register P3. However, the ZB
soFtware can examine P3 6 's current output by
reading the port register.
11.5 TIN tmES
R241 TMR
Timer Mode Register
(% F1; Read/Write)
T'N MODES
EXTERNAL CLOCK INPUT = 00
GATE INPUT = 01
TRIGGER INPUT
10
(NON·RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
=
figure 11-13.
Tilller Mode Register TIN Operation
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
The Timer Mode register TMR (%F1) (Figure 11-13)
is used in conjunction with the Prescaler register
PRE 1 (%F3) (Figure 11-14) to conFigure P3 1 as
TIN.
TIN is used in conjunction with T1 in
one of Four modes:
•
•
•
•
External clock input
Gated internal clock
Triggered internal clock
Retriggerable internal clock
382
L
CLOCK SOURCE
1 = Tl INTERNAL
o = Tl EXTERNAL (TIN)
Figure 11-14.
Prescaler 1 TIN Operation
Counter/Timers
The counter/timer clock source must be configured
for external by setting PRE 1 bit D2 to O. The
Timer Mode register bits D5 and D4 can then be
used to select the desired TIN operation.
11.5.1
External Clock Input Hode
The TIN External Clock Input mode (TMR bits D5
and D4 both set to 0) supports counting of
external events, where an event is considered to
be a High-to-Low transition on TIN (Figure
11-15). occurrence (Single-Pass mode) or on every
nth occurrence (Continuous mode) of that event.
For T1 to start counting as a result of a TIN
input, the Enable Count bit D3 in TMR must be set
to 1. When using TIN as an external clock or a
gate input, the initial values must be loaded into
the down-counters by setting the Load bit D2 in
TMR to a 1 before counting begins.
In the
descriptions of TIN that follow, it is assumed
that the programmer has performed these operations.
Initial values are automatically loaded
in Trigger and Retrigger modes so software loading
is unnecessary.
11.5.2 Gated Internal Clock Mode
The TIN Gated Internal Clock mode (TMR bits D5
and D4 set to 0 and 1 respectively) measures the
duration of an external event. In this mode, the
T1 prescaler is driven by the internal timer
clock, gated by a High level on TIN (Figure
11-16).
T1 counts while TIN is High and stops
counting while TIN is Low.
Interrupt request
IRQ 2 is generated on the High-to-Low transition of
TIN' signaling the end of the gate input.
Interrupt request IRQ5 is generated if T1 reaches
its end-of-count.
It is suggested that P3 1 be configured as an input
line by setting P3M bit D5 to 0 although TIN is
still functional if P3 1 is configured as a handshake input.
Each High-to-Low transition on TIN generates
interrupt request IRQ2' regardless of the selected
TIN mode or the enabled/disabled state of T1.
IRQ2 must therefore be masked or enabled according
to the needs of the application.
TMR
D5-D4
= 00
~~~~
TIN
CLOCK
~~~~
D
D
INTERNAL
CLOCK
PRE1
IRQS
T1
~----------------~IRQ2
figure 11-15.
External Clock Input Hode
INTERNAL
CLOCK
-2
TMR
D5-D4
= 01
-D-
I
..,.4
~I
V
D
I ~
T1
IRQS
IRQ2
D
figure 11-16.
PRE1
Gated Clock Input Mode
383
~
INTERNAL
CLOCK
IRQ5
EOGE
TRIGGER
TIN
TRIGGER -
P31
0
0
J'L
TMR
05-D4 = 11
IRQ2
figure 11-17.
Triggered Clock Mode
I"~I m~
P3s
P31
TOUT TIN
-<~
PRE1
T1
IRQS'
IRQ4
figure 11-18.
Cascaded Counter/Ti.aers
("")
a
-c:
...
::J
,..,(1)
"--I
.....
3
,..,(1)
'"
Counter/Timers
11.5.3
Triggered Input Mode
The TIN Triggered Input mode (TMR bits Os and
04 s~t to 1 and 0 respectively) causes T1 to start
counting as the result of an external event
(Figure 11-17). T1 is then loaded and clocked by
the internal timer clock following the first HighSubsequent
to-Low transition on the TIN input.
TIN transitions do not afFect T1.
In the Single-Pass mode, the Enable bit is reset whenever Tl
reaches its end-oF-count.
Further TIN transitions will have no efFect on T1 until software
sets the Enable Count bit again.
In Continuous
mode, once Tl is triggered counting continues
until software resets the Enable Count bit.
Interrupt request IRQS is generated when T1
reaches its end-of-count.
11.5.4
Retrig~erable
Input MOde
The TIN Retriggerable Input mode (TMR bits Os
and 04 both set to 1) causes Tl to load and start
counting on every occurrence of a High-to-Low
transition on TIN (Figure 11-17).
Interrupt
request IRQS will be generated i f the programmed
time interval (determined by T1 prescaler and
counter/timer register initial values) has elapsed
since the last High-to-L9W transition on TIN.
In Single,..Pass mode, the end-oF-count resets the
Enable Count bit.
Subsequent TIN transitions
will not cause T1 to load an~ start counting until
software sets the Enable Count bit again. In Continuous mode, counting continues once Tl is triggered until software resets the Enable Count bit.
When -enabled, each High-to-Low TIN transition
causes T1 to reload and restart counting. Interrupt request IRQS is generated on every end-oFcount.
IRQ4 (TO end-oF-count) are also generated but are
most likely of no importance in this configuration
and should be disabled.
11.7
RESET CONDITIONS
After a hardware reset, the counter/timers are
disabled and the contents of both the _counter/
timer registers and the pres caler modulos are
undefined.
However, the counting modes are
configured For Single-Pass and TI' s clock source
is set for external.
TIN is set for External
Clock mode, and the TOUT mode is ofF.
Figures
11-19 ttirough 11-22 show the binary reset values
of the Prescaler, Counter/Timer, and Timer Mode
registers.
R242 T1
Counter/Timer 1 Register
(% F2; Read/Write)
R244 TO
Counter/Timer 0 Register
(% F4; Read/Write)
L
INITIAL VALUE WHEN WRITTEN
(RANGE 1·256 DECIMAL, 01·00 HEX)
CURRENT VALUE WHEN READ
Figure 11-19.
Counter/Til;aer Reset
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
11.6 CASCADING COUNTER/TIMERS
For some applications, it may be necessary to measure a time interval greater than a single counter/timer can measure.
In this case, TIN and
TOUT can be used to cascade TO and T1 as a single unit (Figure 11-18). TO should be configured_
to operate in Continuous mode and to drive
TOUT.
TIN should be configured as an external
clock input to -T1 and wired back to TOUT.
On
every other TO end-of-count, TOUT undergoes a
High-to-Low transition which causes T1 to count.
Tt can operate in either Single-Pass or Continuous
mode.
Each time TI' s end-of-count is reached,
interrupt requ~st IRQS is generated.
Interrupt
requests IRQ2 (TIN High-to-Low transitions) and
~
COUNTMODE
1 = T, MODULO·N
T, SINGLE·PASS
o=
CLOCK SOURCE
1 = T, INTERNAL
o = T, EXTERNAL (TIN)
PRESCALER MODULO
'-----.,.---(RANGE: 1-64 DECIMAL
01-00 HEX)
Figure 11-20.
Prescaler 1 Register Reset
385
Counter/Timers
R245 PREO
Prescaler 0 Register
(% F5; Write Only)
1?1?1?1?1?1?1?lol
[
C~~NJo ~~ELE.PASS
1 = To MODULO·N
RESERVED
PRESCALER MODULO
'-------(RANGE: 1-64 DECIMAL
HEX)
01-00
Figure 11-21.
Prescaler 0 Reset
R241 TMR
Timer Mode Register
(% F1; Read/Write)
10101010101010101
TOUT MODES
L 01 == NO
FUNCTION
TOUT OFF = 00
.
LOAD To
To OUT = 01
o = DISABLE To COUNT
T, OUT = 10
1 = ENABLE To COUNT
.
INTERNAL CLOCK OUT = 11
T
T'N MODES
EXTERNAL CLOCK INPUT = 00
GATE INPUT =
TRIGGER INPUT =
(NON·RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
0110
Figure11-22.
386
~
o=
NO FUNCTION
1 = LOADT,
'--_ _ _ 0 = DISABLET, COUNT
1 = ENABLE T, COUNT
Ti8er Mode Register Reset
Chapter 12
Serial 1/0
12.1
INTRIIlUCTIIIN
The
Z8
microcomputer
contains
an
on-board
full-duplex receiver/transmitter for asynchronous
data communications.
The receiver/transmitter
consists of a Serial I/O register SID (%F1) and
its associated control logic (Figure 12-1).
The
SID is actually two registers--the receiver buffer
and the transmitter buffer--which are used in
conjunction with counter/timer TO and Port 3 I/O
lines P30 (input) and P37 (output). Counter/timer
r0 provides the clock input for control of the
data rates.
Configuration of the serial I/O is controlled by
the Port 3 Mode register, P3M.
The Z8 always
transmits 8 bits between the start and stop bits;
that is, 8 data bits or 7 data bits and 1 parity
bit.
Odd parity generation a~d detection is
supported.
allows the software to access the serial I/O as
general-purpose registers, eliminating the need
for special instructions.
12.2
BIT RATE GENERATION
When Port 3· Mode register bit D6 is set to 1, the
serial I/O is enabled and TO automatically becomes
the bit rate generator (Figure 12-3). TO I S endof-count signal no longer generates interrupt
request IRQ4; instead, the Signal is used as the
input to the divide-by-16 counters (one each for
the receiver and the transmitter) which clock the
data stream.
The divide chain that generates the bit rate is
shown in Figure 12-4. The bit rate is given by
the following equation:
bit rate
The Serial I/O register and its associated Mode
Control registers are mapped into the register
file as shown in Figure 12-2. This organization
J
READ%FO~
II
RECEIVER
BUFFER
0-
SERIAL
IN
t-p-oo
RECEIVER
SHIFT
REGISTER
+
-
4
where p and t are the initial values in the
Prescaler
and
Cou~ter/Timer
registers,
respectively.
J
STOP
BIT
DETECT
TRANSFER
MARK
...
I--'"
CHAR
DETEGT
PARITY
CHECK
I-
r
7-
TRANSMITTER
SHIFT
REGISTER
t
t
f----
t--
~D--
SERIAL
OUT
r---
SHIFT
CLOCK
RESET
+16
+START
CLOCK
CONTROL
IR04
WRITE %FO
SHIFT
CLOCK
START
BIT
DETECT
frequency/(2 x 4 x P x t x 16)
INTERNAL DATA BUS
'J
II
P3
= XTAL
PARITY
GEN
IR03
+6
STOP
SERIAL
110 CLOCK
(FROM TO)
Figure 12-1.
Serial I/O Block Diagran
387
Serial I/O
The final divide-by-16 is required since TO runs
at 16 times the bit rate in order to synchronize
on the incoming data.
HEX IDENTIFIERS
DEC
247
To configure the Z8 for a speci fic bit rate,
appropriate values as determined by the above
equation must be loaded into registers PREO (%F5)
and TO (%F4).
PREO also controls the counting
mode for TO and should therefore be set to the
Continuous mode (01 set to 1).
For example, given· an input clock frequency
(fXTAL) of 11.9808 MHz and a selected bit rate of
1200 bits per second, the equation is satisfied by
p=39 and t:2. Counter /timer TO shou ld be set to
%02.
With TO in Continuous mode, the value of
PREO becomes %90 (Figure 12-5).
PORT 3 MODE
F7
P3M
245
TO PRESCALER
F5
PREO
244
TIMER/COUNTERO
F4
TO
240
SERIAL 110
FO
SIO
Figure 12-2. Serial I/O Register Hap
Table 12-1 lists several commonly used bit rates
and the values of fXTAL, p, and t required to
derive them.
This list is presented for convenience and is not intended to be exhaustive.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
The bit rate generator is started by setting the
Timer Mode register TMR (%F1) bits 01 and DO both
to 1 (Figure 12-6).
This transfers the contents
of the Prescaler and Counter/Timer registers to
their corresponding down-counters.
In addition,
counting is enabled so that serial I/O operations
begin.
L.
eo" = "'"
1 P30 = SERIAL IN
P37 = OUTPUT
P37 = SERIAL OUT
Figure 12-3. Port 3 Mode Register
and Bit Rate Generation
fXTAL~r:l.-.--.~
r:-L-~..~ =~TE
~U---~CLOCK
t
+4
PREO
+16.·
TO
Figure 12-4. Bit Rate Divide Chain
Table 12-1. Bit Rate
7,3728
388
Bit
Rate
p
t
19200
9600
4800
2400
1200
600
300
150
110
3
3
3
3
3
3
3
3
3
1
2
4
B
16
32
64
12B
175
7,9872
p
t
-- --- --
13
1
13
2
13
4
13
B
13 16
13 32
3 189
9,8304
P
t
4
4
4
4
4
4
4
4
4
1
2
4
B
16
32
64
12B
175
11,0592
P
t
-- -9
9
9
9
9
9
9
5
1
2
4
B
16
32
64
157
11,6736
11,9808
P
t
---
-- -- --- -- -1
-- --
19
19
19
19
19
19
4
2
4
8
16
32
207
P
39
39
39
39
39
17
t
1
2
4
8
16
50
12,2880
P
5
5
5
5
5
5
5
5
8
t
1
2
4
B
16
32
64
128
109
Serial I/O
12.3 RECE[VER OPERATION
R245 PREO
Prescaler 0 Register
(% F5; Write Only)
1110101111111 111
L=
COUNTMODE
o = To SINGLE·PASS
1
To MODULO·N
The receiver consists of a receiver buffer (510
[%FO]), a serial-in, parallel-out Shift register,
parity checking, and data synchronizing logic.
The receiver block diagram is shown as part of
Figure 12-1.
12.3.1
1..-_ _ _ _ _ _
PRESCALER MODULO
0=64
Figure 12-5. Prescaler 0 Register
and Bit Rate Generatioo
R241 TMR
Timer'Mode Register
(% F1; Read/Write)
~o
0 = NO FUNCTION
1 = LOAD To
,= DISABLE To COUNT
1 = ENABLE To COUNT
Figure 12-6. Timer Made Register
and Bit Rate Generation
Receiver Shift Register
After a hardware reset 'or after a character has
been received, the Receiver ShiFt register is
initialized to all 1s and the shift clock is
stopped.
Serial data, input through Port 3 pin
P30, is synchronized to the internal clock by two
D-type flip flops before being input to the Shift
register and the start bit detection circuitry.
The start bit detection circuitry monitors the
incoming data, stream, looking for a start bit, (a
High-to-Low input transition). When a start bit'
is detected, the shift clock logic is enabled.
The TO input is ~i vided by 16 and, when the count
equals a, the divider outputs a shift clock. This
clock shifts the' start bit into the Receiver Shift
register at the center of the bit time. Before
the shift actually occurs, the input is rechecked
to ensure that the start bit is valid.
I f the
detected start bit is' false, the receiver is reset
and the process of looking for a start bit is
repeated. If the ~tart bit is valid, the data is
shiFted into the Shift register every sixteen
counts until a full character is assembled (Figure
12-7).
(R)
RCVR
DATA
SHIFT
CLO,CI(---"
-
8 TO COUNTS LATER SHIFTING STARTS
RCVR_-----------------------------~
IRQ3
f
SHIFT REGISTER CONTENTS
TRANSFERRED TO RECEIVER
BUFFER AND IRQ3 IS
GENERATED
Figure 12-7.
Receiver Tilling
389
Serial I/O
After a full character has been assembled in the
Shift register, the data is transferred to the
receiver's buffer, S10 (%FO), and interrupt
request 1RQ3 is generated.
The shift clock is
stopped and 'the Shift register reset to all 1s.
The start'bit detection circuitry begins monitoring the data input for the next start bit. This
cycle allows the receiver to synchronize on the
center of the bit time for each incoming character.
12.3.2 Overwrites
Although the receiver is buffered, it is not protected from being overwritten, so the software
must read the SIO register within one character
time after the interrupt request. The ZB does not
have a flag to indicate this overrun condition.
If polling is used, the IRQ3 bit in the Interrupt
Request register'must be reset by software.
12.3.4 Parity
The data format supported by the receiver must
have a start bit, eight data bits, and at least
one stop bit. If parity is on, bit 07 of the data
received will be replaced by a Parity Error flag.
A parity error sets 07 to 1; otherwise, 07 is set
to O. Figure 12-B shows these data formats.
The ZB hardware supports odd parity only, which is
enabled by setting Port 3 Mode register bit 07 to
1 (Figure 12-9). If even parity is required, the
Parity mode should be'disabled (i.e. P3M 07 set to
0), and software must calculate the received
data's parity.
12.4 TRANSMITTER OPERATION
The transmitter consists of a transmitter buffer
(510 (%FO», a parity generator, and associated
control logic. The transmitter block diagram is
shown as part of Figure 12-1.
12.3.3 fraaing Errors,
Framing error detection is not supported by the
receiver hardware, but by responding to the interrupt request within one character bit time, the
software can test for a stop bit at PJO. Port 3
bits are always readable, which facilitates break
detection. For example, if a null character is
received, testing PJO results in a 0 being read.
After a hardware reset or after a character has
been transmitted, the transmitter is forced to a
marking atate (output always High) until a character is loaded into the transmitter buffer, 510
(%FO).
The transmitter is loaded by specifying
the 510 as the destination register of any
instruction.
Received Data
(No Parity)
I~I~I~I~I~I~I~I~I~I&I
LSTARTBIT
L-------EIGHT DATA BITS
L - - - - - - - - - - ' - - - O N E STOP BIT
Received Data
(With Parity)
1~lpl~I~I~I~I~I~I~I&1
IL
_LSTARTBIT
L------SEVEN DATA BITS
PARITY ERROR FLAG
L - - - - - - - - - - - - - O N E STOP BIT
figure 12-8.
390
Receiver Data forats
Serial I/O
generated and this notifies the processor that the
transmitter is ready to accept another character.
R247 P3M
Port 3 Mode Register
(% F7; Write Only)
12.4.1 Overwrites
The user is not protected from overwr iting the
transmitter, so it is up to the software to
respond to IRQ 4 appropriately.
I f polling is
used, the IRQ4 bit in the Interrupt Request register must be reset.
12.4.2 Parity
The data format supported by the transmitter has a
start bit, eight data bits, and ,at least two stop
bits. If parity is on, bit 7 of the data transmitted will be replaced by an odd parity bit.
Figure 12-10 shows the transmitter data formats.
°
o PARITY OFF
1 PARITY ON
Figure 12-9.
Parity and Port 3 Hade Register
TO's output drives a divide-by-16 counter which in
turn generates a shift clock every 16 counts.
This counter is reset when the transmitter buffer
is written by an instruction.
This reset
synchronizes the shift clock to the software. The
transmitter then outputs one bit per shift clock,
through Port 3 pin P3 7 , until a start bit, the
character written to the buffer, and two stop bits
have been transmitted. After,the second stop bit
has been transmitted, the output is again forced
to a marking state. ! Interrupt request IRQ4 is
Parity is enabled by setting Port 3 Mode register
bit 07 to 1.
If even parity is required, the
parity mode should be disabled (i.e. P3M 07 set to
0), and software must modify the data to include
even parity.
Since the transmitter can be overwritten, the user
is able to generate a break signal. This is done
by writing null characters to the transmitter buffer (SID, %FO) at a rate which does not allow the
stop bits to be output.
Each time the SID is
loaded, the divide-by-16 counter is re-synchronized and a new start bit is output followed by
data.
Transmitted Data
(No Parity)
T
LSTART BIT
' - - - - - - - - E I G H T DATA BITS
TWO STOP BITS
Transmitted Data
(With Parity)
T
I
L.
LSTART BIT
_ _ _ _' - -_ _ _ _ _ _ SEVEN
,
Figure 12-10.
DATA BITS
ODD PARITY
TWO STOP BITS
Transmitter Data Formats
391
Serial I/O
12.5 RESEr COtlHTIIINS
R240 SIO
Serial I/O Register
(% FO; Read/Write)
After a hardware reset, the Serial I/O register
contents are undefined, and Serial mode and parity
are disabled. Figures 12-11 and 12-12 show the
binary reset values of the Serial I/O register and
its associated mode register P3M.
I?I?I?I?I?I?I?I?I
I. . _____ SERIAL DATA (Do = LSB)
Figure 12-11. Serial I/O Register Reset
R247 P3M
Port :3 Mode Register
(% F78; Write Only)
1010101010101 /01
L=
00
L-_ _ _ _ ~
0 PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
o P32
= INPUT
P35 = OUTPUT
1 P32 = DAVO/RDYO P35 = RDYOIDAVO
P33 = INPUT
~} P33
P34 = OUTPUT
= INPUT
P34
= OM
1 1 P33 = DlWI/RDY1 P34 = RDY1/DAV1
L-_ _ _ _ _ _ _ O P31
1 P31
L-_ _ _ _ _ _ _ _
= INPUT (T'N)
= DAV2IRDY2
~ ~~~ ~ ~N~~lL
L-_ _ _ _ _ _ _ _ _ ~ ~~=:+~ g~F
Figure 12-12.
392
Port
~
Register Reset
IN
P36
P36
= OUTPUT (Tour)
= RDY2/DAV2
~~~ ~ ~~~iA~TOUT
A
393
Appendix A
Pin Descriptions
and Functions
This appendix contains pin information and physical descriptions for the ZB development device
(ZB612) and Protopack emulator (ZB603/13).
Pin
descriptions for the ZB601/11 and ZB6B1/B2 microcomputers can be found in Chapters 6 and 7,
respectively.
A.1
D£VElOPl£NT DEVICE (Z8612)
The pin mnemonics and descriptions presented for
the ZB microcomputers (Chapter 6) also apply to
the development device. Additional pin descriptions are as follows:
AO-A11 • Progr_ Hellory Address (outputs). These
lines are used to access the first 4K bytes of the
external program memory.
DO~'
Program Data (inputs).
Data from the
external program memory is input through these
pins.
lACK.
Interrupt Acknowledge (output, active
High).
lACK is driven High in response to an
interrupt during the interrupt machine cycle.
HOS.
Low).
394
Progrllll HeIIIory Data Strobe (output, active
MDS is Low during an instruction fetch
cycle when the first 4K bytes of program memory
are being accessed.
SCLK. Systea Clock (output). SCLK is the internal clock output ,through a buffer. The clock rate
is equal to one-half the crystal frequency.
Instruction Sync (output, active Low).
SYNC.
This strobe output is forced Low during the internal clock period preceding an opcode fetch.
A.2
PROTOPACK EMULATOR (Z8603/13)
Both the ZB603 and ZB613 devices use a 40-pin
package that also has a 24-pin "piggy-back" socket. An EPROM or ROM can be installed on the back
of the emulator's standard 40-pin package via the
socket (Figure A-3). A single +5 V dc power source
is required. Figure A-4 illustrates the pinout for
the socket carried piggyback. The socket is
designed to accept a 2716 EPROM for the ZB603 and
a 2732 EPROM for the ZB613 device.
P in mnemonics and descr iptions are the same as
those for the Z8601/11 microcomputer (Chapter 6).
Descriptions for the additional (24-pin socket)
memory interface lines are the same as those given
for the development devices above.
Pin Descriptions and Functions
TIMING {
AND
CONTROL
-
RESET
+5V
RtW
GND
DS
XTAL1
AS
XTAL2
POO
PORTO
(NIBBLE
PROGRAMMABLE)
1/0 OR As-AIS
----......
---
POI
P20
P02
P2l
POs
--
}
CLOCK
---
P04
PORT 2
POS
(BIT PROGRAMMABLE)
POs
P07
P10
P11
PORT oj
P12
(BYTE
PROGRAMMABLE)
1/0 OR ADo-AD7
P1s
P14
P31
28612
PORT 3
SERIAL AND PARALLEL
110 CONTROL
P1s
P1s
P3s
P17
P36
P37
Do
PROGRAM
MEMORY
DATA
INPUTS
INTERRUPT ACKNOWLEDGE
Dl
Ao
D2
Al
Ds
--
D4
Ds
D6
PROGRAM MEMORY
ADDRESS OUTPUTS
D7
lACK
As
MDS
Ag
INSTRUCTION SYNC
SYNC
Al0
SYSTEM CLOCK
SCLK
All
MEMORY DATA STROBE
Figure A-1.
Z8612 Pin functions
395
Vee
64
2
63
P31
XTAL1
3
62
P21
P31
4
61
P2&
_!30
5
60
P2s
RESET
.
6'
59
P24
RIW
7
58
P23
OS
8
57
P22
AS
9
56
P21
P3S
10
55
P20
P32
11
54
P33
,
POO
12
53
P34
POl
13
52
P11
P02
14
51
P1&
P03
15
50
P15
P04
16
49
P14
GNO
17
48
P13
POs
18
47
P12
POs
19
46
P11
20
45
P10
21
44
01
22"
43
06
23
42
05
24
41
04
25
40
Ao
26
39
Al
27
38
A2
28
37
A3
29
36
A4
30
35
A5
31
34
As
32
33
A7
P01
lACK
SYNC
SCLK
01
Ali
Figure A-2.
396
P3S
XTAL2
Z8812
Z8612 Pin Assign.ents
B
397
Appendix B
Control Registers
Registers
R244 TO
Counter/Timer 0 Register
(F4H; ReadlWrite)
R240 SIO
Serial I/O Register
(FOH ; ReadlWrite)
' - - - - - SERIAL DATA (Do = LSD)
NOT To"MODES
useD = 00
R241 TMR
Timer Mode Register
(FlH; ReadlWrite)
R2451'REO
Prescaler 0 Register
(F5H; Write Only)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~J~I~I~I
j
--1
: ~~,
INTERNAL CLOCK OUT = 11
~~ g~~
T
us·
~o.=
=
MODES
EXTERNAL CLOCK IN~~T
00
GATE INPUT = 01
TRIGGER INPUT
=
DISABLE To COUNT
ENABLE To COUNT
=
1
= 11
COUNTMODE
o = To SINGLE·PASS
1 ;:: To MODULO·N
RESERVED
0 ." NO FUNCTION
1 "" LOAD T,
0 :::: DISABLE T, COUNT
(NON.R~~8~~J::~~) = 10
(RETRIGGERABlE)
~L
NO FUNCTION
1 = LOAD
To
0
1
... ...
PRESCALER MODULO
"~.,,
01-00 HEX)
= ENABLE T, COUNT
,"
R246 P2M
Port 2 Mode Register
(F6H; Write Only)
R242 Tl
Counter Timer 1 Register
(F2H ; ReadlWrite)
I~I~I~I~I~I~I~I~I
T,INITIAL VALUE (WHEN WRlnEN)
L-----I(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)
R243 PREI
Prescaler 1 Register
(F3H; Write Only)
R247 P3M
Port 3 Mode Register
(F7H; Write Only)
I~I~I~I~I~I~I~I~I
10, I0.1 0,1 0,1 0,1 0,1 0,10 1
Lo
~L
0
COUNTMODE
,
o = .T., .SINGLE.PASS
1 = T, MODULO·N
CLOCK SOURCE
1 = T,INTERNAl
T, EXTERNAL TIMING INPUT
(TIN') MODE
E~
i
o=
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
PORT 2 PULLOUPSOP.EN DRAIN
1 PORT 2 PUll·UPS ACTIVE
RESERVED
o P32 = INPUT
1 P32
= DAVOIRDYO
00 P33 = INPUT
~
61 P33 = INPUT
=
P34 '" tfM
1 1 P33:::; DAV1IRDY1 P34 = RDY1/DAV1
L.._ _ _ _ _ _ ~ ~~~ ~ ~N:vU~to~1
L.._ _ _ _ _ _ _ ~ ~~g ~ ~N:R~!lIN
L.._ _ _ _ _ _ _ _ ~
398
P3S =- OUTPUT
P3S
ROYO/DiWO
P34 = OUTPUT
~~~:~~ g~F
=;: ~ ~~~~/~~4k\JT)
~~~ ~ ~~~iA~TOUT
Control Registers
Registers
(Continued)
R24B POIM
Port 0 and I Mode Register
R252 FLAGS
Flag Register
(F8H; Write Only)
(FCH ; ReadIWrite)
I~I~I~I~I~I~I~I~I
PD,_PO, MOOE:]
OUTPUT ;::: 00
INPUT:; 01
A'2-A,S
~~
L po,-po, MOOE
ll!m~
1
00:; OUTPUT
01
INPUT
= 1X
1X = Aa-Att
EXTERNAL MEMORY TIMING
NORMAL:; 0
EXTENDED = 1
LUSERFLAGF1
LUSER FLAG F2
=
STACK SELECTION
0 :; EXTERNAL
1
INTERNAL
,
=
As, OS.
OVERFLOW FLAG
SIGN FLAG
P1 o-P1 1 MODE
00 ;::: BYTE OUTPUT
01
BYTe INPUT
10 = ADo-ADT
11
HIGH·IMPEDANCE ADo-ADt.
=
=
HALF CARRY FLAG
DECIMAL ADJUST FLAG
ZERO FLAG
CARRY FLAG
Am, ,\a-A", AI2-A'5
IF SELECTED
R249IPR
Interrupt Priority Register
R253 RP
Register Pointer
(F9H; Write Only)
(FDH; ReadIWrite)
I~I~I~I~I~I~I~I~I
IRQ3, IROS
.,.... :J
PR~O~IJ~d~~o.::ra~)
I I 1[1 ,~"""" .~.."RESERVED::: 000
,
'~ ~
1 = IRQ3 > IROS
:
A > C > B
B > C > A
C > B > A
B > A> C
RESERVED
IRao, IRQ2 PRIORITY (GROUP 8)
o = IRQ2 > IRCO
1 ::: IRCO > IHQ2
LooN'TeARE
~ ~ ~ g~~
= 011
= 100
= 101
= 110
= 111
IRQ1, IRQ4 PRIORITY (GROUP C)
o = IRQ1 > IRQ4
1 = IRQ4 > IRQt
R254 SPH
Stack Pointer
R250 IRQ
Interrupt Request Register
(FAH ; ReadIWrite)
(FEH ; ReadIWrite)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
RESERVEO:::r-
c=
IRQO
IRQt
IRQ2
IRQ3
IRQ4
IROS
P32 INPUT (Do
=IROO)
P331NPUT
P311NPUT
P3g INPUT, SERIAL INPUT
To, SERIAL OUTPUT
"
R251 IMR
Interrupt Mask Register
R255 SPL
Stack Pointer
(FBH; ReadIWrite)
(FFH ; ReadIWrite)
___
Il____c=
1~1~I~t~I~I~I~t~1
1 ENABLES IROO-IROS
(Do
IROO)
=
RESERVED
'---------1
ENABLES INTERRUPTS
399
c
... -,.-~.
',..
4RL.
7;1",..
. Zilog
.
400
Opcode .Mall
Lower Nibble (Hex)
Opcode
Map
o
o
3'
5
6
~
CD
;;
7
z
......~
::>
6
7
9
A
B
C
o
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
DEC
IRI
ADD
ADD
ADD
OJNZ
JR
LO
JP
INC
R2,Rl
ADD
IRI,IM
LD
Il,II:Z
ADD
RI,IM
LO
[1, [2
ADD
IR2, Rl
[l,RA
cc,RA
I:l,IM
cc,DA
fl
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
Rl
RLC
IRI
ADC
ADC
II, [2
II,
ADC
R2,RI
ADC
IR2,RI
ADC
RI,IM
ADC
IRI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
Rl
INC
IRI
SUB
SUB
II, [2
[1, III
SUB
R2,RI
SUB
IR2,RI
SUB
RI,IM
SUB
IRI,IM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
IP
IHHI
SRP
1M
SBC
SBC
II, [2
n,Ir:z
SBC
R2,RI
SBC
IR2, HI
SBC
RI,IM
SBC
IRI,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
OA
HI
OA
IRI
OR
OR
OR
II, [2
I1,Ir2
R2,Rl
OR
IR2, Rl
OR
HI,IM
OR
IRI,IM
10,5
10,5
POP
Rl
POP
IRI
6,5
6,5
6,5
COM
Rl
COM
IRI
6,5
10,5
10,5
10,5
10,5
ANO
ANO
ANO
II, [2
II,
Ir:z
ANO
RI,IM
ANO
IRI,IM
6,5 .
PUSH
R2
PUSH
IR2
10,5
10,5
Ir:z
R2,Rl
ANO
IR2,RI
6,5
10,5
10,5
10,5
10,5
TCM
TCM
[1, [2
[l,II:Z
TCM
R2,RI
TCM
IR2,RI
TCM
RI,IM
TCM
IHI,IM
10,5
10,5
10,5
10,5
TM
RI,IM
TM
IRI,IM
6,5
6,5
TM
TM
II, [2
[l.II:Z
12,
°
18,
°
TM
R2,RI
TM
IR2,HI
I!,
R2
I2,
Rl
A
B
C
o
E
F
6,5
RL
HI
RL
IHI
10,5
10,5
12,0
18,0
LOE
LDEI
I2,
f---
f---.,---
I--I--I--f--6,1
INCW !NCW
RRI
IRI
CP
n,l2
10,5
10,5
10,5
10,5
CP
CP
R2,HI
CP
IR2,RI
CP
RI,IM
CP
IRI,IM
10,5
10,5
10,5
10,5
XOR
R2,RI
XOR
IH2,HI
XOR
RI,IM
XOR
IRI,IM
Ir:z
6,5
II,
6,5
6,5
CLR
HI
CLR
IRI
XOR
XOR
II, [2
Il,112
6,5
6,5
RRC
IRI
EI
6,5
6,5
RRC
Rl
DI
f--6,1
Irn 112. Irq
6,5
12,
°
18,0
LOC
LOCI
II, tIl:Z
In,IIl:Z
12,0
18,0
LOC
LOCI
6,5
6,5
6,5
10,5
RR
Rl
RR
IHI
LO
LO
H2,RI
8,5
8,5
SWAP SWAP
IRI
Rl
\..
Bytes per
Instruction
'v"
20,0
10,5
LD
I2, X, Rl
10,5
10,5
10,5
LO
IR2,RI
LO
RI,IM
LD
IRI,IM
CALL"
hz, Irn IRRI
6,5
10,5
LO
LO
H2,IRI
Irl, [i
,/
RET
f--16,
°
IRET
I--6,5
"
V'
3
RCF
x, H:z
CALL
DA
20,0
6,5
SRA
IRI
Irz
r
LD
6,5
II,
f--14,0
10,5
II,
SRA
Rl
I2, hIl
f---
I---
OECW OECW LOE
LOEI
[l,lrrz Il1.lrr:z
HHI
IHI
6,5
F
E
DEC
Rl
10/12,1 12/14,1
:a:9
4
3
6,5
SCF
6,5
CCF
6,0
NOP
.I
\..
'---------~~~----------~# ~ ~
3
Lowor
Opcode
Nibble
Execution
Cycles
Upper
Opcodo- A
Nibblo
First
Operand
*2-byte
instr~uction;
+
Plpelino
Cycles
Mnomonic
Second
Operand
Logend:
R = 8-Bit Address
r = 4-Bit Address
R 1 or fl =, Dst Address
Hz or [2 = Src Address
Sequenco:
Opcode, First Operand, Second Operand
Noto: The blank areas are not defined.
fetch cycle appears as a 3-byte instruction
401
Zilog
Product Specification
January 1988
Super8™ MCU ROMless,
ROM, and Prototyping Device
with EPROM Interlace
Z8800,Z8801,Z8820,Z8822
FEATURES
• Improved Z8t!) instruction set includes multiply and
divide instructions, Boolean and BCD operations.
• Up to 32 bit-programmable and S byte-programmable 110
lines, with 2 handshake channels.
• Additional
instructions support
languages, such as "Forth."
.• Interrupt structure supports:
o 27 interrupt sources
o 16 interrupt vectors (2 reserved for future versions)
o S interrupt levels
.
o Servicing in 600 nsec. (1 level only)
threaded-code
• 325 byte registers, including 272 general:purpose
registers, and 53 mode and control registers.
• Addressing of up to 12SK bytes of memory.
• Full-duplex UARTwith special features.
• Two register pOinters allow use of short and fast
instructions to access register groups within 600 nsec.
• On-chip oscillator.
• Direct Memory Access con~roller (DMA).
• 20 MHz clock.
• SK byte ROM for ZSS20
• Two 16-bit counter Itimers.
GENERAL DESCRIPTION
The Zilog SuperS single-chip MCU can be used for
development and production. It can be used as I/O- or
memory-intensive computers, or configured to address
external memory while still supporting many I/O lines.
~~~~~~~~~#~~~~~~~
9 8
7 6
5
4
3
2
1 U
~
H
e
U Q H 81
Ne
10
60
Vee
11
59
Ne
ROMIe..
12
. 58
Vee
....
"" I.
57
,."
14
56
po,
P24
15
55
P3<
The SuperS is also available as a 4S-pin and 6S-pin ROM less
microcomputer with four byte-wide 110 ports plus a
byte-wide address/data bus. Additional address bits can be
, configured, up to a total of 16.
o
P20
16
54
P3,
Vee
17
53
AS
GND
18
52
DS
P17
Vee
19
51
P07
20
50
P40
po,
P24
XTAL2
P.!4
XTAU
21
P25
4.
OND
P4<
22
48
OND
vee
P4s 2.
P4e .4
47
po,
GNO
AS
46
P43
lCTAl2
os
N7
25
45
R/W
26
44
Ne
lCTALl
GNO
Ne
P47
RIW
SUPERa
~~~~~~~~~~~~~~~/~
Figure 1a_ Pin Assignments - 68-pln PLCC
402
Ne
The SuperS features a full-duplex universal asynchronous
receiver Itransmitter (UART) with on-chip baud rate
generator, two programmable counter /timers, a direct
memory access (DMA) controller, and an on-chip oscillator.
P1S
vee
POe
Z8801
~~~~~-n-n~~~Tr~
P35
Pl.
PD.
Pl,
PO,
PI,
PO,
P13
P03
PI,
PO,
Pl.
PD.
Pl.
11
+5V
GND
)
3.
13
XTALI _ )
12
XTAL2
P3,
P2.
P3.
37
AS
Os
XTALl
36
P4.
P4,
35
P4,
P4S
34
GND
P4.
33
P4,
P47
32
P43
P2,
31
ANi
P3,
3D
REsET
P33
29
P23
28
P3.
P3,
+5V
SUPER8
XTAL2
P22.1!...
P23~
P07
P2,
38
P2.
27
P27
P2,
26
P2.
P3,
25
P3.
9
+5
+5
+5
A.
A'3
A.
As
A.
A,
An
A3
OE
A,
A,.
A,
CE
A.
D,
D.
D.
D,
D.
D,
D,
GND
D3
Figure 3. Pin Assignments-28-Pin Piggyback Socket
PORT 2
SUPER8
PORT 3
Figure 2. Pin Functions
Figure 1b. Pin Assignments - 48-pin DIP
A"
A7
CLOCK
P20~
P21~
PD.
41
P17
POWER
DATA
PROTOPACK
EPROM
SOCKET
ADDRESS
Figure 4. Pin Functions-28-Pin Piggyback Socket
Protopack
This part functions as an emulator for the basic
microcomputer. It uses the same package and pin-out as
the basic microcomputer but also has a 28-pin "piggy back"
socket on the top into which a ROM or EPROM can be
installed. The socket is designed to accept a type 2764
EPROM.
development. When a final program is developed, it can be
mask-programmed into the production microcomputer
device, directly replacing the emulator. The protopack part
is also useful in situations where the· cost of maskprogramming is prohibitive or where program flexibility is
desired.
This package permits the protopack to be used in prototype
and final. PC boards while still permitting user program
403
110
(BIT PROGRAMMABLE)
UtttUt
PORT4
UART
I
I
ADDRESS
~------------v~-----------110
(BIT PROGRAMMABLE)
OR CONTROL
ADDRESS OR 110
(BIT PROGRAMMABLE)
ADDRESSIDATA OR 110
, (BYTE PROGRAMMABLE)
~------V~-----~
Z·BUS WHEN USED AS
ADDRESSIDATA BUS
Figure 5. Functional Block Diagram
ARCHITECTURE
The SuperS architecture includes 325 byte-wide internal
. registers. 272 of these are available for general purpose
use; the remaining 53 provide control and mode functions.
The instruction set is specially designed to deal with this
large register set. It includes a full complement of 8-bit
arithmetic and logical operations, including multiply and
divide instructions and provisions for BCD operations.
Addresses and counters can be incremented and
decremented as 16-bit quantities. Rotate, shift, and· bit
manipulation instructions are provided. Three new
instructions support threaded-code languages.
The UART is a full-function mUltipurpose asynchronous
serial channel with many premium features .
The 16-bit counters can operate independently or be
cascaded to perform 32·bit counting and timing operations.
The DMA controller handles transfers to and from the
register file or memory. DMA can use the UART or one of two
ports with handshake capability.
The architecture appears in the block diagram (Figure 5).
PIN DESCRIPTIONS
The Super8 connects to external devices via the following
TIL-compatible pins:
AS. Address Strobe (output, active Low). AS is pulsed
Low once~t the beginning of each machine cycle. The
rising edge indicates that addresses Riw and DM, when
used, are valid.
OS. Data Strobe (output, active Low). DS provides timing
for data movement between the address/data bus and
external memory. During write cycles, data output is valid at
the leading edge of DS. During read cycles, data input
must be valid prior to the trailing edge of DS.
POO·P07. P10·P17. P20·P27. P30·P37. P40·P47' Port 110
Lines (input/output). These 40 lines are divided into five 8-bit
I/O ports that can be configured under program control for
I/O or external memory interface.
In the ROMless devices, Port 1 is dedicated as a
multiplexed address/data port, and Port 0 pins can be
assigned as additional address lines; Port 0 non-address
pins may be assigned as I/O. In the ROM and protopack,
Port 1 can be assigned as input or output, and Port 0 can be
assigned as input or output on a bit by bit basis.
------...,-----------_._-_._--404
Ports 2 and 3 can be assigned on a bit-for-bit basis as
general I/O or interrupt lines. They can also be used as
special-purpose I/O lines to support the UART,
counter/timers, or handshake channels.
it is deactivated, the SuperB begins processing at address
0020H·
ROMless. (input, active High). This input controls the
operation mode of a 6B·pin SuperB. When connected to Vee,
the part will function as a ROM less ZBBOO. When connected
to GND, the part will function as a ZBB20 ROM part.
Port 4 is used for general I/O.
During reset, all port pins are configured as inputs (high
impedance) except for Port 1 and Port 0 in the ROM less
devices. In these, Port 1 is configured as a multiplexed
address/data bus, and Port 0 pins POO-P04 are configured
as address out, while pins POS-PO? are configured as inputs.
R/W. Read/Write (output). R/W determines the direction of
data transfer for external memory transactions. It is Low
when writing to program memory or data memory, and High
for everything else.
RESET. Reset (input, active Low). Reset initializes and starts
the SuperB. When it is activated, it halts all processing; when
XTAL 1, XTAL2. (Crystal oscillator input.) These pins
connect a parallel resonant crystal or an external clock
source to the on-board clock oscillator and buffer.
REGISTERS
The SuperB contains a 256-byte internal register space.
However, by using the upper 64 bytes of the register space
more than once, a total of 325 registers are available.
The uppermost 32 register direct registers (EO to FF) are
further divided into two banks (0 and 1), selected by the
Bank Select bit in the Flag register. When a Register Direct
command accesses a register between EO and FF, it looks at
the Bank Select bit in the Flag register to select one of the
banks.
Registers from 00 to BF are used only once. They can be
accessed by any register command. Register addresses CO
to FF contain two separate sets of 64 registers. One set,
called control registers, can only be accessed by register
direct commands. The other set can only be addressed by
register indirect, indexed, stack, and DMA commands.
The register space is shown in Figure 6.
SET ONE
I
SET TWO
FFH _ - - - - - - - - ,
CONT~g~~:~I~TERS
..
(REGISTER ADDRESSING ONLY)
.1-
BANKI
1--1-
BANKO
~
SYSTEM REGISTERS:
STACK, FLAGS, PORTS, ETC.
(REGISTER ADDRESSING ONLY)
WORKING REGISTERS
(WORKING REGISTER
ADDRESSING ONLY)
DATA REGISTERS
(INDIRECT REGISTER, INDEXED,
STACKORDMA
ACCESS ONLY)
COH~
_______
~
256
BYTES
BFH _ - - - - - - - - ,
DATA REGISTERS
(ALL ADDRESSING MODES)
OOH~
_______
192
BYTES
~
Figure 6. SuperS Registers
405
Working Register Window
Controi registers R214 and R215 are the register pOinters,
RPO and RP1. They each define a moveable, 8-register
section of the register space. The registers within these
spaces are called working registers.
Working registers can be accessed using short 4-bit
addresses. The process, shown in section a of Figure 4,
works as follows:
• The high-order bit of the 4-bit address selects one of the
two register pointers (0 selects RPO; 1 selects RP1).
• The five high-order bits in the register pointer select an
8-register (contiguous) slice of the register space.
The net effect is to concatenate the five bits from the register
pointer to the three bits from the address to form an 8-bit
address. As long as the address in the register pointer
remains unchanged, the three bits from the address will
always point to an address within the same eight registers.
The register pointers can be moved by changing the five
high bits in control registers R214 for RPO and R215 for RP1.
The working registers can also be accessed by using full
8-bit addressing. When an 8-bit logical address in the range
192 to 207 (CO to CF) is specified, the lower nibble is used
similarly to the 4-bit addressing described above. This is
shown in section b of Figure 7.
S The three low-order bits of the 4-bit address select one of
the eight registers in the slice.
IIIIIIII
I
RPO(R214)
IIIIIIII
RPl (R215)
SELECTS
RPOORRPl
I
RPO(R214)
RPl (R215)
SELECTS
ADDRESS
RPOORRPl
OPCDDE
ADDRESS
,...----'"---.,~
~
I I I I I I I I I
4·BIT ADDRESS PROVIDES 3 LOW·ORDER BITS
REGISTER POINTER PROVIDES
5 HIGH·ORDER BITS
L----_~-_-_~-
.....: ___ ILOW.ORDERBITS
REGISTER POINTER PROVIDES
5 HIGH·DRDER BITS
~------~~~------~
-------~~~-------...8-BIT PHYSICAL ADDRESS
TOGETHER THEY CREATE
8·BIT REGISTER ADDRESS
a.4-Bit Addressing
b. 8-Bit Addressing
Figure 7. Working Register Window
406
Since any direct access to logical addresses 192 to 207
involves the register pointers, the physical registers 192 to
207 can be accessed only when selected by a register
pointer. After a reset, RPO points to R192 and RP1 points to
R200.
Register List
Table 1 lists the SuperS registers. For more details, see
FigureS.
Table 1. Super-8 Registers
Address
Decimal
Hexadecimal
Mnemonic
Function
General-Purpose Registers
000-192
192-207
192-255
OO-BF
CO-CF
CO-FF
General purpose (all address modes)
Working register (direct only)
General purpose (indirect only)
Mode and Control Registers
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
224
DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
DO
DE
EO
225
EI
226
E2
227
E3
228
E4
229
E5
235
236
237
239
240
EB
EC
ED
EF
FO
241
FI
244
245
246
247
248
F4
F5
F6
F7
F8
BankO
Bank 1
BankO
Bank 1
BankO
Bank 1
BankO
Bank 1
BankO
Bank 1
BankO
Bank 1
BankO
BankO
BankO
BankO
BankO
Bank 1
BankO
Bank 1
BankO
BankO
BankO
BankO
BankO
Bank 1
PO
PI
P2
P3
P4
FLAGS
RPO
RPI
SPH
SPl
IPH
IPl
IRQ
IMR
SYM
COCT
COM
CICT
CIM
COCH
CTCH
COCl
CTCl
CICH
cnCH
CICl
cnCl
UTC
URC
UIE
UIO
POM
DCH
PM
DCl
HOC
HIC
P4D
P40D
P2AM
UB'GH
Port 0 1/0 bits
Port 1 (1/0 only)
Port 2
Port 3
Port 4
System Flags Register
Register Pointer 0
Register Pointer 1
Stack Pointer High Byte
Stack Pointer low Byte
Instruction Pointer High Byte
Instruction Pointer low Byte
Interrupt Request
Interrupt Mask Register
System Mode
CTR 0 Control
CTRO Mode
CTR 1 Control
CTR 1 Mode
CTR 0 Capture Register, bits 8-15
CTR 0 Timer Constant, bits 8-15
CTR 0 Capture Register, bits 0-7
CTR 0 Time Constant, bits 0-7
CTR 1 Capture Register, bits 8-15
CTR 1 Time Constant, bits 8-15
CTR 1 Capture Register, bits 0-7
CTR 1 Time Constant, bits 0-7
UART Transmit Control
UART Receive Control
UART Interrupt Enable
UARTData
PortO Mode
DMA Count, bits 8-15
Port Mode Register
DMA Count, bits 0-7
Handshake Channel 0 Control
Handshake Channell Control
Port 4 Direction
Port 4 Open Drain
Port 2/3 A Mode
UART Baud Rate Generator, bits 8-15
407
Table 1. Super-a Registers (Continued)
Address
Decimal
Hexadecimal
Mode and Control Registers (Continued)
249
F9
BankO
Bank 1
250
FA
BankO
Bank 1
251
FB
BankO
Bank 1
FC
BankO
252
253
FD
BankO
254
FE
BankO
Bank 1
255
FF
BankO
Bank 1
Mnemonic
Function
P2BM
UBGL
P2CM
UMA
P2DM
UMB
P2AIP
P2BIP
EMT
WUMCH
IPR
WUMSK
Port 2/3 B Mode
UART Baud Rate Generator, bits 0-7
Port 2/3 C Mode
UART Mode A
Port 2/3 0 Mode
UART ModeB
Port 2/3 A Interrupt Pending
Port 2/3 B Interrupt Pending
External Memory Timing
Wakeup Match Register
Interrupt Priority Register
Wakeup Mask Register
MODE AND CONTROL REGISTERS
R2l3 (05) FLAGS
SYSTEM FLAGS REGISTER
CARRYFLAGg)J~
ZEROFLAG~
SIGN FLAG
ug
R21S (DA) IPH
INSTRUCTION POINTER HIGH
I~I~I~I~I~I~I~I~I
l L
BANK ADDRESS
L
I ' - - - - - _ H I G H BYTE (IPS.IP15)
FAST INTERRUPT STATUS
HALF-CARRY FLAG
DECIMAL ADJUST
OVERFLOW flAG
R2l9 (DB) IPL
INSTRUCTION POINTER LOW
I~I~I~I~I~I~I~I~I
R2l. (06) RPO
REGISTER POINTER 0
[fr71 0,1 051 041 031 021 0, I
(RP3.RP7)~
Do
IL--_ _ _ _ LOW BYTE (IPO·IP7)
I
LNOTUSEO
R220 (DC) IRQ
INTERRUPT REQUEST (READ ONLY)
I~I~I~I~I~I~I~I~I
R2l5 (07) RPl
REGISTER POINTER 1
LEVEL
7J~
I
LEVEL 6:=....J
(RP3'RP7)~
LNOTUSED
LEVEL 0
LEVEL 1
LEVEL 5
LEVEL 2
LEVEL 3
R221 (DO) IMR
I~I~I~I~I~I~I~I~I
INTERRUPT MASK
I~I~I~I~I~I~I~I~I
HIGH BYTE (SPS.SP15)
LEVEL7~J
=-.J
I
LEVEL 6
Llli'
L
LLEVELO
LEVEL 1
R217 (09) SPL
STACK POINTER
LEVEL 5
LEVEL 2
I~I~I~I~I~I~I~I~I
LEVEL.
LEVEL 3
,-I- - - - _ L O W BYTE (SPO-SP7)
Figure a. Mode and Control Registers
408
L
LEVEL.
R2l6 (OS) SPH
STACK POINTER
1'------
Llli'
L
MODE AND CONTROL REGISTERS (Continued)
R222 (DE) SYM
SYSTEM MODE
TIL
I~I~I~I~I~I~I~I~I
-r
NOT USED
~
L
1 = GLOBALINTER"RUPTENABLE
1
= FAST INTERRUPT ENABLE
FAST INTERRUPT SELECT
000
001
010
011
100
101
110
111
LEVEL 0
LEVEL 1
LEVEL2
LEVEL 3
LEVEL4
LEVELS
LEVEL6
LEVEL 7
R224, BANK 0 (EO) COCT
COUNTER 0 CONTROL
SINGLECYCLE~~
o1== CONTINUOUS ~
o = COUNT DOWN
1
1
1
= COUNT UP
= LOAD COUNTER
I
~
L
L=
1
ENABLE COUNTER
READ 1 = END OF COUNT
WRITE 1 = RESET END OF COUNT
1
= ZERO COUNT INTERRUPT ENABLE
1 = SOFTWARE CA~TURE
"
= SOFTWARE TRIGGER
R224 BANK 1 (EO) COM
COUNTER 0 MODE
I L~!:~Si:"",",
INPUT PIN ASSIGNMENTS:
P2,
o
o
o
o
o
o
o
o
0
0
110
110
110
0
GATE
GATE
110
0
1
1
1
1
EDGE OF P27
10 = BI·VALUE MODE
11 = CAPTURE ON BOTH
EDGES OFP27
TRIGGER
TRIGGER
CO INPUT
CO INPUT
TRIGGER
CO INPUT
GATE
GATE/
CO INPUT
TRIGGER
CO OUTPUT 110
CO OUTPUT TRIGGER
CO OUTPUT GATE
CO OUTPUT GATE/TRIGGER
CO OUTPUT CO INPUT
- - - UNDEFINED - - - - - UNDEFINED - - - CASCADE COUNTERS -
110
0= EXTERNAL
UP/DOWN CONTROL P27
1 = PROGRAMMED
UP/DOWN CONTROL
1 = ENABLE RETRIGGER
R225 BANK 0 (E1) C1CT
COUNTER 1 CONTROL
SINGLECYCL"E~
JJ
o1==
CONTINUOUS
o = COUNT DOWN
1 = COUNT UP
1 = LOAD COUNTER
I L
~
L
1 = ENABLE COUNTER
READ 1 = END OF COUNT
WRITE 1 = RESET END OF COUNT
1 = ZERO COUNT INTERRUPT ENABLE
1 = SOFTWARE CAPTURE
1 = SOFTWARE TRIGGER
Figure 8. Mode and Control Registers (Continued)
409
MODE AND CONTROL REGISTERS (Continued)
R225 BANK 1 (E1) C1M
COUNTER 1 MODE
INPUT PIN ASSIGNMENTS:
I
P3.
00001/0
110
o 0 0 1 1/0
TRIGGER
0010GATE
110
TRIGGER
0011GATE
o 1 0 0 1/0
CO INPUT
o 1 0 1 TRIGGER
COINPUT
0110GATE
CO INPUT
0111GATEI
CO INPUT
TRIGGER
CO OUTPUT 1/0
CO OUTPUT TRIGGER
CO OUTPUT GATE
CO OUTPUT GATEITRIGGER
CO OUTPUT CO INPUT
- - - UNDEFINED - - - - - UNDEFINED - - - - - UNDEFINED - - -
L~;",=="",",
EDGEOFP3, '
10 = BI·VAWE MODE
11 = CAPTURE ON BOTH
EDGES OF P3,
0= EXTERNAL
UP/DOWN CONTROL P3,
1 = PROGRAMMED
UP/DOWN CONTROL
1 = ENABLE RETRIGGER
R226 BANK 0 (E2) COCH
COUNTER 0 CAPTURE
R229 BANKO (E5) C1CL
COUNTER 1 CAPTURE
I~I~I~I~I~I~I~I~I
1...______
L-_ _ _ _ _ HIGH BYTE (COCO.COC,15)
R226 BANK 1 (E2) COTCH
COUNTER 0 TIME CONSTANT
LOW BYTE (C1C.·C1C,)
R229 BANK 1 (E5) CHCL
COUNTER 1 TIME CONSTANT
I~I~I~I~I~I~I~I~I
L-_ _ _ _ _ HIGH BYTE (COTCo.COTC'5)
LI_ _ _ _ _ _
R227 BANK 0 (E3) COCL
COUNTER 0 CAPTURE
R235 BANK 0 (EB) UTC
UART TRANSMIT CONTROL
TRANSMIT DATA SELECT:
o = OUTPUT P3, DATA
1 = OUTPUT TRANSMIT DATA
~
I
1 = SEND BREAK
R227 BANK 1 (E3) COTCL
COUNTER 0 TIME CONSTANT
~
L,
= TRANSMIT DMA ENABLE
1 = TRANSMIT BUFFER EMPTY
1 = ZERO COUNT
1 = TRANSMIT ENABLE
1 = WAKE·UP ENABLE - - - : - - - - '
LOW BYTE (COTC••COTC,)
R22S BANKO (E4) C1CH
COUNTER' CAPTURE
R236 BANK 0 (EC) URC
UART RECEIVE CONTROL
1 =
WAKE'UPDETECT~
JJ ' I
1 = CONTROL CHARACTER DETECT
~
1 = BREAK DETECT
R22SilANK 1 (E4) 'C1TCH
COUNTER 1 TIME CONSTANT
1 = FRAMING ERROR
I~I~I~I~I~I~I~I~I
1..._ _ _ _ _ _ HIGH BYTE (C1TCo·CHC,,)
Figure 8. Mode and Control Registers (Continued)
410
I
L
STOP BITS:
0= 1 STOP BIT
1 = 2 STOP BITS
I~I~I~I~I~I~I~I~I
1'-_____
LOW BYTE (CHC.·CHC,)
~~L
1 = R, ECEIVECHARACTER
AVAILABLE
,
1 = RECEIVE ENABLE
1 = PARITY ERROR
1 = OVERRUN ERROR
MODE AND CONTROL REGISTERS (Continued)
R237 BANK 0 (ED) UIE
UART INTERRUPT ENABLE
1 = WAKE.UP INTERRUPT
ENABLE~
I
JJ
1 = CONTROL CHARACTER
INTERRUPT ENABLE
1 = BREAK INTERRUPT ENABLE
~
II
~
1 = RECEIVE CHARACTER "'.WAILABLE
INTERRUPT ENABLE
1 = RECEIVE DMA ENABLE
1 = TRANSMIT INTERRUPT ENABLE
1 = ZERO COUNT INTERRUPT ENABLE
1 = RECEIVE ERROR INTERRUPT
ENABLE
R239 BANK 0 (EF) UIO
UART TRANSMIT DATA (WRITE)
UART RECEIVE DATA (READ)
R244 BANK 0 (F4) HOC
HANDSHAKE 0 CONTROL (WRITE ONLY)
I~I~I~I~I~I~I~I~I
L _ _ _ _ _ DATA (Do = LSB)
DESKEW COUNTER
(RANGE 1·16)
==:J
II
L
L.. _,"M'~~
PORT SELECT:
1 = PORT1;0 = PORT4
DMAENABLE:
1 = ENABLED
0= DISABLED
R240 BANK 0 (FO) POM
PORTO MODE
P07MDDE~J
I
~
PO, MODE
' - - - - - - MODE:
1 = FULLY INTERLOCKED
0= STROBED
Uhl'
L
POS MODE
PO, MODE
PO. MODE
P03 MODE
o=
R245 BANK 0 (F5) H1C
HANDSHAKE 1 CONTROL (WRITE ONLY)
LpOOMODE
PO, MODE
I~I~I~I~I~I~I~I~I
DESKEW COUNTER
(RANGE '·16)
I/Oj 1 = ADDRESS
II
==:J
L.._,"__ ~
NOT USED
MODE:
1 = FULLY INTERLOCKED
0= STROBED
R240 BANK 1 (FO) DCH
DMACOUNT
R246 BANK 0 (F6) P4D
PORT 4 DIRECTION
' - - - - - - HIGH BYTE (DCS·DC,,)
' - - - - - - P40·P47110 DIRECTION
o = OUTPUT; 1 = INPUT
R241 BANK 0 (F1) PM
PORT MODE (WRITE ONLY)
T ~~PORTODIRECTION
~
NOTUSEDT
R247 BANK 0 (F7) P40D
PORT 4 OPEN·DRAIN
0= OUTPUT
o~~~~'l..~N PORT 0
PORT 1 MODE
00 OUTPUT
01 INPUT
1X ADDRESS/DATA
0 = PUSH·PULL
1 = OPEN·DRAIN
OPEN DRAIN PORT 1
o = PUSH·PULL
1 = OPEN·DRAIN
ENABLE OM P3s
0= DISABLE
1 = ENABLE
R248 BANK 0 (F8) P2AM
PORT 2/3 A MODE (WRITE ONLY)
R241 BANK 1 (F1) DCL
DMACOUNT
' - - - - - - LOW BYTE (DCo·DC7)
00
01
10
11
INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH·PULl
OUTPUT,OPEN·DRAIN
Figure 8. Mode and Control Registers (Continued)
411
MODE AND CONTROL REGISTERS (Continued)
R250 BANK 0 (FA) P2CM
PORT 2/3 C MODE (WRITE ONLY)
R24S BANK 1 (FS) UBGH
UART BAUD-RATE GENERATOR
I~I~I~I~I~I~I~I~I
LI_ _ _ _ _ _
HIGH BYTE (UBG.-UBG15)
00 INPUT
01 INPUT, INTERRUPT ENABLED
10 OUTPUT, PUSH-PULL
11 OUTPUT, OPEN-DRAIN
R249 BANK 0 (F9) P2BM
PORT 2/3 B MODE (WRITE ONLY)
R250 BANK 1 (FA) UMA
UARTMODEA
00
01
10
11
INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH-PULL
OUTPUT, OPEN-DRAIN
CLOCKRATE:J
D7 0 6
DO=Xl
.
o 1 = XIG
.
1 0 = X32
1 1
X64
I L
L
llli.
=
R~49
BANK 1 (F9) UBGL
UART BAUD-RATE GENERATOR
L -_ _ _ _ _
LOW BYTE (UBG,-UBG,)
=5BITS
=GBITS
=7BITS
=SBITS
R251 BANK 0 (FB) P2DM
PORT 2/3 D MODE (WRITE ONLY)
00
01
10
11
INPUT
INPUT, INTERRUPT ENABLED
OUTPUT, PUSH-PULL
OUTPUT, OPEN-DRAIN
'
E
R251 BANK 1 (FB) UMB
UARTMODEB
CLOCK OUTPUT SELECT
==r--
07 D6
o
o
0
1
1 0
1 1
= P2, DATA
= SYSTEM CLOCK (XTALl2)
= BAUD-RATE GENERATOR
OUTPUT
'
= TRANSMIT DATA CLOCK
L
L.
1 = LOOPBACKENABLE
1 = BAUD-RATE GENERATOR ENABLE
BAUD-RATE GENERATOR SOURCE:
o = P2, (EXTERNAL)
1 = INTERNAL (XTAL/4)
TRANSMIT CLOCK INPUT SELECT:
1 = AUTO-ECHO - - - - '
oc
P21
1 " BAUD-RATE GENERATOR OUTPUT
RECEIVE CLOCK INPUT SELECT: - - - - - - '
0= P20
1 = BAUD-RATE GENERATOR
OUTPUT
Figure 8. Mode and Control Registers (Continued)
412
1 = EVEN PARITY
1 = PARITY ENABLE
BITS PER CHARACTER
05 0 4
00
01
1 0
11
TRANSMIT WAKE-UP VAWE
RECEIVE WAKE-UP VALUE
MODE AND CONTROL REGISTERS (Continued)
R252 BANK 0 (FC) P2AIP
PORT 2/3 A INTERRUPT PENDING (READ ONLY)
R254 BANK 1 (FE) WUMCH
WAKE-UP MATCH REGISTER
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
LI_ _ _ _ _ _
THIS BYTE, MINUS MASKED BITS,
IS USED FOR WAKE-UP MATCH
R255 BANK 0 (FF) IPR
INTERRUPT PRIORITY REGISTER
GROUP PRIORITY
R253 BANK 0 (FD) P2 BIP
PORT 2/3 B INTERRUPT PENDING (READ ONLY)
I~I~I~I~I~I~I~I~I
:~~:
P26
I
07 0 4 0 1
= UNDEFINED
=B>C>A
= A>B>C
=B>A>C
:::;:C>A>B
I
I L
o
GROUP A
~ IRQO> IRQ1
1 = IRQ1 > IRQO
GROUPB
IRQ2 > (IRQ3,IRQ4)
1 = (IRQ3,IRQ4) > IRQ2
o=
= C>B>A
SUBGROUPB
o = IRQ3 > IRQ4
= A>C>B
= UNDEFINED
1 = IRQ4 > IRQ3
GROUPC
o = IRQ5 > (IRQ6,IRQ7)
1 = (IRQ6,IRQ7) > IRQS
P3s
SUBGAOUPC
o = IRQS > IRQ7
1
R254 BANKO (FE) EMT
EXTERNAL MEMORY TIMING REGISTER
1+
= IRQ7 > IRQ6
R255 BANK 1 (FF) WUMSK
WAKE-UP MASK REGISTER
I.":.tllli' I~ :':"..~~"~
1 = DATA MEMORY
' - - - - - - THESE BITS CORRESPOND TO BITS
IN WAKE-UP MATCH REGISTER; Os
MASK CORRESPONDING MATCH BITS
STACK SELECT:
o = REGISTER FILE
1 = DATA MEMORY
DATA MEMORY AUTOMATIC WAITS
00 = NO WAITS
01 = 1 WAIT
10 = 2 WAITS
11 = 3 WAITS
' - - - - - - - - PROGRAM MEMORY AUTOMATIC WAITS
'
00 = NO WAITS
01 = 1 WAIT
10 = 2 WAITS
11 = 3 WAITS
' - - - - - - - - - - - SLOW MEMORY TIMING
0= DISABLED
1 = ENABLED
' - - - - - - - - - - - - EXTERNAL WAIT INPUT
o = P341S NORMAL 110
1 = P34 IS EXTERNAL WAIT INPUT
Figure 8_ Mode and Control Registers (Continued)
413
1/0 PORTS
Port 1
The SuperS has 40 I/O lines arranged into five S-bit ports.
These lines are all TTL-compatible, and can be configured
as inputs or outputs. Some can also be configured as
address/data lines.
Each port has an input register, an output register, and a
register address. Data coming into the port is stored in the
input register, and data to be written to a port is stored in the
output register. Reading a port's register address returns the
value in the input register; writing a port's register address
loads the value in the output register. If the port is configured
for an output, this value will appear on the external pins.
When the CPU reads the bits configured as outputs, the
data on the external pins is returned. Under normal output
loading, this has the same effect as reading the output
register, unless the bits are configured as open-drain
outputs.
The ports can be configured as shown in Table 2.
Table 2_ Port Configuration
Port
Configuration Choices
a
Address outputs and/or general I/O
Multiplexed address/data(or I/O, only for ROM
and Proto pack)
Control I/O for UART, handshake channels, and
counter/timers; also general 110 and external
interrupts
General 110
2 and 3
4
The ROM and Protopack Port 1 can be configured as above
or as an I/O port; it can be a byte-wide input, open-drain
output, or push-pull output. It can be placed under
handshake control or handshake channel O.
Ports 2 and 3
Ports 2 and 3 provide external control inputs and outputs for
the UART, handshake channels, and counter/timers. The
pin assignments appear in Table 3.
Bits not used for control I/O can be configured as
general-purpose I/O lines and/or external interrupt inputs.
Those bits configured for general I/O can be configured
individually for input or output. Those configured for output
can be individually configured for open-drain or push-pull
output.
All Port 2 and 3 input pins are Schmitt-triggered.
The port address for Port 2 is R21 0, and for Port 3 is R211.
Port 0
Port 0 can be configured as an I/O port or an output for
addressing external memory, or it can be divided and used as
both. The bits configured as I/O can be either all outputs or all
inputs; they cannot be mixed. If configured for outputs, they
can be push-pull or open-drain type.
Any bits configured for I/O can be accessed via R208. To write
to the port, specify R20S as the destination (dst) of an
instruction; to read the port, specify R208 as the source (src).
Port 0 bits configured as I/O can be placed under handshake
control of handshake channel 1.
Port 0 bits configured as address outputs cannot be accessed
via the register.
In ROM less devices, initially the four lower bits are configured
as address eight through twelve.
414
In the ROM less device, Port 1 is configured as a byte-wide
address/data port. It provides a byte-wide multiplexed
address/data path. Additional address lines can be added
by configuring Port O.
Table 3. Pin Assignments for Ports 2 and 3
Port 2
Bit Function
Port 3
Bit
Function
a
a
UART receive data
UART transmit data
Reserved
Reserved
Handshake 1 input/WAIT
Handshake 1 output/OM
Counter 1 input
Counter 1110
2
3
4
5
6
7
UART receive clock
UART transmit clock
Reserved
Reserved
Handshake a input
Handshake a output
Counter a input
Counter a 110
2
3
4
5
6
7
Port 4
Port 4 can be configured as I/O only. Each bit can be
configured individually as input or output, with either
push-pull or open-drain outputs. All Port 4 inputs are
Schmitt-triggered.
Port 4 can be placed under handshake control of
handshake channel O. Its register address is R212.
UART
Receiver
The UART is a full-duplex asynchronous channel. It
transmits and receives independently with 5 to 8 bits per
character, has options for even or odd bit parity, and a
wake-up feature.
The UART begins receive operation when Receive Enable
(URC, bit 0) is set High. After this, a Low on the receive input
pin for longer than half a bit time is interpreted as a start bit.
The UART samples the data on the input pin in the middle of
each clock cycle until a complete byte is assembled. This is
placed in the Receive Data register.
Data can be read into or out of the UART via R239, Bank O.
This single address is able to serve a full-duplex channel
because it contains two complete 8-bit registers-one for
the transmitter and the other for the receiver.
Pins
The UART uses the following Port 2 and 3 pins:
Port/Pin
2/0
3/0
2/1
3/1
UART Function
Receive Clock
Receive Data
Transmit Clock
Transmit Data
Transmitter
When the UART's register address is specified as the
destination (dst) of an operation, the data is output on the
UART, which automatically adds the start bit, the
programmed parity bit, and the programmed number of
stop bits. It can also add a wake-up bit if that option is
selected.
If the UART is programmed for a 5-, 6-, or 7-bit character, the
extra bits in R239 are ignored.
Serial data is transmitted at a'rate equal to 1, 1/16, 1/32 or
1/64 of the transmitter clock rate, depending. on the
programmed data rate. All data is sent out on the falling
edge of the clock input.
When the UART has no data to send, it holds the output
marking (High). It may be programmed with the Send Break
command to hold the output Low (Spacing), which it
continues until the command is cleared.
Ifthe 1Xclock mode is selected, external bit synchronization
. must be provided, and the input data is sampled on the
rising edge of the clock.
For character lengths of less than eight bits, the UART
inserts ones into the unused bits, and, if parity is enabled,
the parity bit is not stripped. The data bits, extra ones, and
the parity bit are placed in the UART Data register (UIO).
While the UART is assembling a byte in its input shift register,
the CPU has time to service an interrupt and manipulate the
data character in UIO.
Once a complete character is assembled, the UART checks
it and performs the following:
IIil If it is an·ASCIl control character, the UART sets the
Control Character status bit.
Ii! It checks the wake-up settings and completes any
indicated action.
!i:! If parity is enabled, the UART checks to see if the
calculated parity matches the programmed parity bit. If
they do not match, it sets the Parity Error bit in URC
(R236 Bank 0), which remains set until reset by software.
II It sets the Framing Error bit (URC, bit 4) if the character is
assembled without any stop bits. This bit remains set until
cleared by software.
Overrun errors occur when characters are received faster
than they are read. That is, when the UART has assembled a
complete character before the CPU has read the current
character, the UART sets the Overrun Error bit (URC, bit 3),
and the character currently in the receive buffer is lost.
The overrun bit remains set until cleared by software.
415
ADDRESS SPACE
The Super8 can access 64K bytes of program memory and
64K bytes of data memory. These spaces can be either
combined or separate. If separate, they are controlled by the
OM line (Port P3s), which selects data memory when Low
and program memory when High.
Figure 9 shows the system memory space.
CPU Program Memory
Program memory occupies addresses 0 to 64K. External
program memory, if present, is accessed by configuring
Ports 0 and 1 as a memory interface.
The address/data lines are controlled by AS, OS and RiW.
The first 32 program memory bytes are reserved for
interrupt vectors; the lowest address available for user
programs is 32 (deCimal). This value is automatically loaded
into the program counter after a hardware reset.
ROMless
ROM and Proto pack
Port 1 is configured as multiplexed address/data or as I/O.
When Port 1 is configured as address/data, Port 0 lines can
be used as additional address lines, up to address 15.
External program memory is mapped above internal
program memory; that is, external program memory can
occupy any space beginning at the top of the internal ROM
space up to the 64K (16-bit address) limit.
CPU Data Memory
The external CPU data memory space, if separated from
program memory by the OM optional output, can be
mapped anywhere from 0 to 64K (full 16-bit address space).
Data memory uses the same address/data bus (Port 1) and
additional addresses (chosen from Port 0) as program
memory. Data memory is distinguished from program
memory by the OM pin (P3s), and by the fact that data
memory can begin at address OOOOH. This feature differs
from the Z8.
Port 0 can be configured to provide from 0 to 8 additional
address lines. Port 1 is always used as an 8-bit multiplexed
address/data port.
e5535
r-------.,
65535
EXTERNAL
PROGRAM
MEMORY
r------...,
EXTERNAL
DATA
MEMORY
THIS BOUNDARY }
MAY BE AT 0, OR
8192
DEPEN:~~GS~z~
t----------1 }
ON-CHIP
ROMOR
32
t----------1
~~~:ACK
INTERRUPT VECTORS
PROGRAM MEMORY
DATA MEMORY
Figure 9. Program and Data Memory Address Spaces
416
INSTRUCTION SET
The Super8 instruction set is designed to handle its large
register set. The instruction set provides a full complement
of 8-bit arithmetic and logical operations, including multiply
and divide. It supports BCD operations using a decimal
adjustment of binary values, and it supports incrementing
and decrementing 16-bit quantities for addresses and
counters.
It provides extensive bit manipulation, and rotate and shift
operations, and it requires no special 1/0 instructions-the
1/0 ports are mapped into the register file.
Instruction Pointer
A special register called the Instruction Pointer (IP) provides
hardware support for threaded-code languages. It consists
of register-pair R218 and R219, and it contains memory
addresses. The MSB is R218.
The following par~graphs describe each flag bit:
Bank Address_ This bit is used to select one of the register
banks (0 or 1) between (decimal) addresses 224 and 255. It
is cleared by the SBO instruction and set by the SB1
instruction.
Fast Interrupt Status. This bit is set during a fast interrupt
cycle and reset during the IRET following interrupt servicing.
When set, this bit inhibits all interrupts and causes the fast
interrupt return to be executed when the IRET instruction is
fetched.
Half-Carry. This bit is set to 1 whenever an addition
generates a carry out of bit 3, or when a subtraction borrows
out of bit 4. This bit is used by the Decimal Adjust (DA)
instruction to convert the binary result of a previous addition
or subtraction into the correct decimal (BCD) result. This
flag, and the Decimal Adjust flag, are not usually accessed
by users.
Threaded-code languages deal with an imaginary
higher-level machine within the existing hardware machine.
The IP acts like the PC for that machine. The command
NEXT passes control to or from the hardware machine to the
imaginary machine, and the commands ENTER and EXIT
are imaginary machine equivalents of (real machine) CALLS
and RETURNS.
Decimal Adjust. This bit is used to specify what type of
instruction wa!1 executed last during BCD operations, so a
subsequent Decimal Adjust operation can function
correctly. This bit is not usually accessible to programmers,
and cannot be used as a test condition.
If the commands NEXT, ENTER, and EXIT are not used, the
IP can be used by the fast interrupt processing, as
described in the Interrupts section.
Overflow Flag. This flag is set to 1 when the result of a
twos·complement operation was greater than 127 or less
than-128, It is also cleared to 0 during logical operations.
Flag Register
The Flag register (FLAGS) contains eight bits that describe
the current status of the Super8. Four of these can be tested
and used with conditional jump instructions; two others are.
used for BCD· arithmetic. FLAGS also contains the Bank
Address bit and the Fast Interrupt Status bit.
The flag bits can be set and reset by instructions.
Sign Flag. Following arithmetic, logical, rotate, or shift
operations, this bit identifies the state of the MSB of the
result. A 0 indicates a positive number and a 1 indicates a
negative number.
.
Zero Flag. For arithmetic and logical operations, this flag is
set to 1 if the result of the operation is zero.
For operations that test bits in a register, the zero bit is set to 1
if the result is zero.
For rotate and shift operations, this bit is set to 1 if the result is
zero.
CAUTION
·Carry Flag. This flag is set to 1 ifthe result from an arithmetic·
operation generates a carry out of, or a borrow into, bit 7.
Do not specify FLAGS as the destination of an
instruction that normally affects the flag bits or the
result will be unspecified.
After rotate and shift operations, it contains the last value
shifted' out of the specified register.
It can be set, cleared, or complemented by instructions.
417
Condition Codes
Addressing Modes
The flags C, Z, S, and V are used t.o centrel the eperatien .of
cenditienal jump instructiens.
All .operands except fer immediate data and cenditien
cedes are expressed as register addresses, program
memery addresses, .or data memery addresses. The
addressing medes and their designatiens are:
The epcede .of a cenditienal jump centains a 4-bit field
called the cenditien cede (cc). This specifies under which
cenditiens it is te execute the jump. Fer example, a
cenditienal jump with the cenditien cede fer "equal" after a
cempare eperatien .only jumps if the two .operands are
equal.
The cenditien cedes and their meanings are given in
Table 4.
Register (R)
Indirect Register (IR)
Indexed (X)
Direct (DA)
Relative (RA)
Immediate (1M)
Indirect (IA)
Table 4. Condition Codes and Meanings
Binary
Mnemonic
0000
1000
0111'
1111'
0110'
1110'
1101
0101
0100
1100
F
0110'
1110'
1001
0001
1010
OOto
1111'
0111'
1011
0011
Flags
Meaning
Alvvays false
Always true
C
NC
Z
C=1
C=O
Z=1
NZ
PL
MI
OV
NOV
Z=O
8=0
8=1
V=1
V=O
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Z=1
Z=O
(8XORV)=0'
(SXORV)=1
(Z OR(8XORV))=0
(Z OR (8XOR V))= 1
C=O
C=1
(C=OANDZ=O)= 1
Equal
Not equal
Greater than or equal
Less than
Greater than
(CORZ)=1
Unsigned less than or equal
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
NOTE: Asterisks ('J indicate condition codes that relate to two different mnemonics buttestthe same flags. For example, Z and EO are both True ifthe
Zero flag is set, but after an ADD instruction, Z would probably be used, while after a CP instruction, EO would probably be used.
418
Registers can be addressed by an 8-bit address in the range
of 0 to 255. Working registers can also be addressed using
4-bit addresses,. where five bits contained in a register
poi nter (R218 or R219) are concatenated with th ree bits
from the 4-bit address to form an 8-bit address.
Notation and Encoding
The instruction set notations are described in Table 5.
Functional Summary of Commands
Figure 10 shows the formats followed by a quick reference
guide to the commands.
Registers can be used in pairs to generate 16-bit program or
data memory addresses.
Table 5. Instruction Set Notations
Notation
Meaning
Notation
Meaning
cc
Condition code (see Table 4)
Working register (between 0 and 15)
Bit of working register
Bit 0 of working register
Register or working register
Register pair or wqrking register pair (Register pairs
always start on an even-number boundary)
Indirect address
Indirect working register
Indirect register or indirect working register
Indirect working register pair
Indirect register pair or indirect working register pair
Indexed
Indexed, short offset
Indexed, long offset
DA.
RA
1M
IML
dst
src
Direct address (between 0 and 65535)
Relative address
Immediate
Immediate long
Destination operand
Source operand
Indirect address prefix
Stack pointer
Program counter
Instruction pointer
Flags register
Register pointer
Immediate operand prefix
Hexadecimal number prefix
Opcode
rb
rO
R
RR
IA
Ir
IR
Irr
IRR
X
XS
XL
@
SP
PC
IP
FLAGS
RP
#
%
OPC
One-Byte Instructions
dst
I OPC I
INC
lWo-Byte Instructions
OPC
Ace, ADD. AND·, CP, LO, LOCo LOCI. LOCO,
lOE, LOED, OR, sac. SUB, TCM. TM, XOR
dst
OPC
dst
OPC
LOC, LDCPD, LoePI, lOE, LDEPO. tOEPI
CALL. CA, DEC, DECW, INC, INew, JP, POP,
RL, RLe, RR. ARC. SWAP, elR. SRA, COM
dst
OPC
PUSH, SAP, SRPO, $RP1
OPC
dst
b 10
OPC
dst
11
b
BITe, BITR
BITS
loPC
dst
DJNZ
cc loPC
dst
JR
dst
LO
r
dst
loPC
loPC
Figure 10. Instruction Formats
419
Three-Byte I structions
OPC
dsl
sre
OPC
sre
dsl
ADC, ADD, AND, CPo DIV. LO, LOW, MULT,
OR, POPUD,
PO~UI,
sac, SUB, reM, TM.
OPC
dsl
bioi
sre
BAND, BCP, BOR, BXOR, LOB
OPC
sre
bi'l
dsl
BAND, BOR, BTJAT, BXOA, LOB
OPC
sre
bioi
dsl
BTJRF
OPC
sre
dsl
RA
CPIJE, CPIJNE
OPC
dsl
x
src
LD, LOC, LDE
OPC
sre
x
I
I
OPC
ee
ADC, ADD, AND, CP, LD, OR, PUSHUD,
PUSHUI, SBC, SUB, TCM, TM, XOR
loPC
LO,
dsl
L~C,
dsl
CALL
dsl
JP
XOR
LOE
Four-Byte Instructions
OPC
dst IX'i"'Oor11
sre
sre
LOC, LOE
OPC
src Ix*Oor1
dsl
dsl
LOC, LOE
OPC
dsl
src
sre
LOC'
OPC
src
dsl
dsl
LOC
OPC
dsl
sre
sre
LDE
OPC
dsl
dsl
LOE
I 0000
I 0000
I 0001
I 0001
dsl
dsl
OPC
sr
} FOR LOC, x = EVEN
FOR lDE, x = ODD
LOW
Figure 10. Instruction Formats (Continued)
INSTRUCTION SUMMARY
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
C Z 5 V D H
~
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
Flags Affected
CZSVDH
ADCdst,src
dst .... dst + src + C
(Note 1)
10
1r 1r 1r -
a
1r
BORdst, src
dst .... dst OR src
rO
Rb
rB
rO
07
-1r
ADDdst,src
dst - dst + src
(Note 1)
00
1r 1r 1r 1r
a
1r
BTJRF
ifsrc = 0, PC
RA
dst
rb
37
------
= PC +
ANDdst,src
dst .... dst AND src
(Note 1)
BTJRT
if src = '1, PC
RA
dst
rb
37
----....!....-
= PC +
BAND dst,src
dst .... dst AN D src
rO
Rb
Rb
rO
67
67
-1r
a u--
rO
Rb
Rb
rO
27
27
-1rOU--
BCP dst, src
dst - src
rO
Rb
17
-1r
a
------
BITCdst
dst .... NOidst
rb
57
-1rOU--
F6
F4
D4
BITRdst
dst .... O
rb
77
------
CCF
C = NOTC
EF
1r-----
BITSdst
dst .... 1
rb
77
------
CLRdst
dst .... a
BO
B1
------
420
50
-1r1r 0 - -
U--
BXOR dst, src
. dst - dst XOR src
CALLdst
SP-SP - 2
@SP-PC
PC .... dst
DA
IRR
IA
R
IR
a u-"":'
INSTRUCTION SUMMARY (Continued)
Instruction
and Operation
AddrMode Opcode
Byte
(Hex)
dst src
Flags Affected
C Z S V D H
Instruction
and Operation
COMdst
dst- NOTdst
R
IR
60
61
-** 0--
INCWdst
dst-l + dst
CP dst,src
dst - src
(Note 1)
AD
* * * *--
CPIJE
if dst - src = O,then
PC -PC + RA
Ir-Ir, + 1
Ir
C2
------
IRET(Fast)
PC-IP
FLAG-FLAG'
FIS-O
CPIJNE
if dst - src = O,then
PC-PC + RA
Ir-Ir + 1
Ir
02
------
R
IR
40
41
* 'If * U - -
DECdst
dst-dst - 1
R
IR
00
01
-'If * * - -
DECWdst
dst-dst - 1
RR
IR
DI
SMR(O)-O
DIV dst, src
dst ~ src
dst (Upper) Quotient
dst (Lower) Remainder
DJNZ r,dst
r- r - 1
if r = a
PC-PC + dst
80
81
-'If * ' I f - -
8F
------
****--
RR
RR
R
IR
94
95
RR
1M
96
BF
Restored to
before interrupt
BF
IRET (Normal)
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; SMR (0) - 1
Restored to
before interrupt
LD dst,src
dst-src
OA
IRR
RA
r
R
r
IR
R
R
R
IR
IR
1M
'R
IR
r
R
IR
1M
1M
R
x
x
RA
rA
(r= 0 to F)
EI
SMR(0)-1
9F
ENTER
SP-SP - 2
@SP-IP
IP-PC
PC-@IP
IP-IP + 2
1F
EXIT
IP-@SP
SP-SP + 2
PC-@IP
IP-IP + 2
2F
------
------
R
IR
rE
-'If**-(r=OtoF)
20
21
------
ccB
(cc=OtoF)
------
rC
-----r8
r9
(r=Oto F)
C7
07
E4
E5
E6 .
06
F5
87
97
rO
Rb
Rb
rO
47
47
------
LDC/LDE
dst -src
r
Irr
Irr
C3
03
E7
F7
A7
B7
A7
B7
------
xs
r
x1
xs
r
x1
r
OA
OA
INCdst
dst -dst + 1
ccO
(cc=Oto F)
30
LDBds\, src
dst - src
------
------
C Z S V D H
-***--
JRcc,dst
if cc is true,
PC-PC + d
RR
IR
Flags Affected
AO
A1
JPcc,dst
if cc is.true,
PC-dst
DAdst
dst- OAdst
AddrMode Opcode
Byte
dst src
(Hex)
LDCD/LDED ds\, src
dst -src
rr - rr - 1
Irr
E2
------
LDEI/LDCI dst, src
dst- src
r(- rr + 1
Irr
E3
------
F2
------
LDCPD/LDEPD dst,src
Irr
rr - rr - 1
dst -src
421
INSTRUCTION SUMMARY (Continued)
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
LDCPIILDEPI dsl, src
Irr
rr - rr + 1
dsl - src
Flags Affected
C Z S V D H
F3
------
LOW dsl, src
dsl - src
RR
RR
RR
RR
IR
IMM
C4
C5
C6
------
MULT dst, src
RR
RR
RR
R
IR
1M
84
85
86
*0**--
OF
------
NEXT
PC-@IP
IP-IP + 2
FF
------
(Nole 1)
40
-**0--
R
IR
50
51
------
NOP
OR dsl,src
dsl - dsl OR src
POPdsl
dsl-@SP;
SP -SP + 1
POPUD dst, src
dsl-src
IR-IR - 1
R
IR
92
------
POPUI dsl, src
dsl - src
IR-IR + 1
R
IR
93
------
PUSH src
SP-SP - 1;@SP-src
R
IR
70
71
-------
PUSHUO dsl, src
IR-IR - 1
dsl-src
IR
R
82
------
PUSHUI dsl, src
IR-IR + 1
dsl-src
IR
,
R
83
------
Instruction
and Operation
CZSVOH
R
IR
10
11
****--
RRdsl
C-dsl(O)
dsl (7) - dsl (0)
dsl (N) - dsl (N + 1)
N = 0106
R
IR
EO
E1
****--
RRCdsl
. C-dsl(O)
dst(7) -C
dsl (N) - dsl (N + 1)
N = 0106
R
IR
CO
C1
* * *.* - -
SBO
BANK-O
4F
------
SBl
BANK-1
5F
------
30
* * * *
OF
1-----
00
01
***0--
SBCdsl,src
dsl - dsl - src - C
(Nole 1)
SCF
C-1
SRAdsl
dsl (7) - dsl (7)
C-dsl(O)
dsl (N) - dsl(N + 1)
N = 0106
R
IR
1 *
SRP src
RPO-IM
RP1-IM + 8
1M
31
------
SRPO
RPO-IM
1M
31
------
1M
31
------
CF
0-----
SRPl
RP1 +-' 1M
RET
PC-@SP;SP-SP + 2
AF
------
SUB dsl,src
dsl - dsl ;- src
RLdsl
C-dsl(7)
dsl (0) - dsl (7)
dsl (N + 1) - dsl (N)
N = 0106
90
91
****--
422
Flags Affected
RLCdst
dSI(O) -C
C-dsl(7)
dsl (N + 1)- dsl (N)
N = 0106
RCF
C-O
R
IR
AddrMode Opcode
Byte
(Hex)
dst src
(Nole 1)
20
* * * *
1 *
INSTRUCTION SUMMARY (Continued)
Instruction
and Operation
AddrMode Opcode
Byte
dst src
(Hex)
FO
F1
-**
TCMdst,src
(NOT dst) AND src
(Note 1)
60
-** 0 - -
TMdst,src
dstANDsrc
(Note 1)
70
-**
dst (0-3) .... dst (4-7)
WFI
XORdst,src
dst - dst XOR src
(Note 1)
AddrMode
CZSVDH
R
IR
SWAPdst
Table 6. Second Nibble
Flags Affected
dst
U--
src
Lower
Opcode Nibble
rn
R
@]
[II
R
IR
III
1M
[§]
Ir
R
o -'-
3F
------
R
BO
-**0--
For example, to use an opcode represented as xo with an "RR"
addressing mode, use the opcode "x4."
NarE 1: These instructions have an identical set of addressing modes,
,
which are encoded for brevity. The first opcode nibble identifies
the command, and is found in the table above. The second
nibble, represented by a 0, defines the addressing mode as
shown in Table 6.:
o
= Cleared to Zero
Set to One
Unaffected
= Set or reset, depending on result of operation.
= Undefined
=
*
U
=
423
SUPER-80PCODEMAP
Lower Nibble (Hex)
o
6
ADD
rl, lr2
10
ADD
R2,Rl
10
ADD
IR2,Rl
10
ADD
Rl,IM
10
BOR·
rO-Rb
6
RLC
Rl
6
RLC
IRI
6
ADC
'1.'2
6
ADC
rl, lr2
10
ADC
R2,Rl
10
ADC
IR2,Rl
10
ADC
Rl,IM
BCP
rl,b,R2
2
6
INC
Rl
6
INC
IRI
6
SUB
'1,'2
6
SUB
rl, lr2
10
SUB
R2,Rl
10
SUB
IR2,Rl
10
SUB
Rl,IM
10
BXOR·
rO-Rb
3
10
JP
IRRI
NOTE
C
6
SBC
r1,f2
6
SBC
rl, lr2
10
SBC
R2,Rl
10
SBC
IR2,Rl
10
SBC
Rl,IM
NOTE
A
6
OR
6
OR
(1. lr2
10
OR
R2,Rl
10
OR
IR2,Rl
10
OR
Rl,I,M
10
LOB·
rO-Rb
6
AND
rl, lr2
10
. AND
R2,Rl
10
AND
IR2,Rl
10
AND
Rt,IM
8
BITC
rl,b
6
TCM
rl, lr2
10
TCM
R2,Rl
10
TCM
IR2,Rl
10
TCM
Rl,IM
10
BAND·
rO-Rb
6
TM
10
TM
R2,Rl
10
TM
IR2,Rl
10
TM
Rl,IM
NOTE
B
24
MULT
IR2,RRI
24
MULT
IM,RRI
rl,x,r2
DA
Rl
6
DA
IRI
10
POP
Rl
10
POP
IRI
6
AND
6
6
COM
Rl
6
COM
IRI
6
TCM
7
10/12
PUSH
R2
12/14
PUSH
IR2
6
TM
'l,r2
8
10
DECW
RRI
10
10
10
24
DECW PUSHUD PUSHUI MULT
IRI
IR1,R2
IR1,R2 R2,RRI
e.
CD
:c.a
.
Z
CD
D.
D.
::>
'1,'2
'1.'2
(1, lr2
6
RL
IRI
10
POPUD
IR2,Rl
10
POPUI
IR2,Rl
28/12
DIV
R2,RRI
28/12
DIV
IR2,RRI
28/12
DIV
IM,RRI
10
LD
'2,x,rl
A
10
INCW
RRI
-,10
INCW
IRI
6
CP
'1,'2
6
CP
rl, lr2
10
CP
R2,Rl
10
CP
IR2,Rl
10
CP
Rl,IM
NOTE
D
B
6
CLR
Rl
6
CLR
IRI
6
XOR
fl.r2
6
XOR
rl, lr2
10
XOR
R2,Rl
10
XOR
IR2,Rl
10
XOR
.Rl,IM
NOTE
E
6
RRC
Rl
6
C
RRC
IRI
16/18
CPIJE
Ir,r2,RA
12
LDC·
(1, lrr2
0
6
SRA
Rl
6
SRA
IRI
16/18
CPIJNE
Irp2,RA
12
LDC·
'2, Irr1
20
CALL
IAI
E
6
RR
Rl
6
RR
IRI
16
LDCD·
(1. lrr2
16
LDCI·
(1. lrr2
10
LD
R2,Rl
F
8
SWAP
Rl
18
CALL
IRRI
8
16
16
SWAP LDCPD· LDCPI·
(2, lrr1
IRI
'2. lrr 1
12
10
10
LDW
LOW
LDW
RR2,RRI IR2,RRI RR1,IML
F
12/10
JP
cc,DA
6
·INC
r1
14
NEXT
,6
LD
Irl,r2
10
LD
IR2,Rl
10
LD
Rl,IM
18
LDC·
rl. lrr2,xs
10
LD
R2, IR I
18
CALL
DAI
18
LDC·
r2, lrrl,xs
NOTEC
ENTER
WFI
-
6
SBO
~
SBI
-
6
01
~
EI
~
RET
16i6
IRET
~
RCF
~
SCF
~
CCF
~
NOP
Legend:
r ~ 4·bit address
R ~ 8-bit address
b ~ bit number
Rl arrl ~ dst address
R2 or'2 = src address
·Examples:
BOR rO·R2
is BOR rl ,b,R2
or BOR r2,b,Rl
LDCrl,trr2
i.s LOC (1,lrr2
program
or LDE rl,lrr2 = data
Sequence:
Opcode, first. second, third operands
NOTE: The blank areas are not defined.
424
22
EXIT
----:s-
NOTEE
Figure 11. Opcode Map
-----w-
6
LD
rl, lr2
10
LD.
IR1,IM
NOTEB
6
LD
rl,IM
E
10
LD
6
RL
Rl
NOTED
12/10
JR
cc,RA
o
10
9
NOTE A
12/10
DJNZ
rl,RA
8
6
r---
6
LD
r2,Rl
7
ADD
'1,'2
5
6
LD
rl,R2
6
6
(1,(2
B
5
DEC
IRI
6
A
4
6
4
9
3
DEC
Rl
o
'if
2
=
INSTRUCTIONS
Table 7. Super81nstructions
Mnemonic
Operands
Instruction
Load Instructions
CLR
LD
LOB
LDC
LDE
LOCO
dst
dst, src
dst, src
dst, src
dst, src
dst, src
LDED
dst, src
LOCI
dst, src
LDEI
LDCPD
dst, src
dst, src
LDEPD
dst, src
LDCPI
dst, src
LDEPI
dst, src
LOW
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
dst, src
dst
dst, src
dst, src
src
dst, src
dst, src
Clear
Load
Load bit
Load program memory
Load data memory
Load program memory and
decrement
Load data memory and
decrement
Load program memory and
increment
Load data memory and increment
' Load program memory with
pre-decrement
Load data memory with
pre-decrement
Load program m~mory with
pre-increment
Load data memory with
pre-increment
Load word
Pop stack
Pop user stack (decrement)
Pop user stack (increment)
Push stack
Push user stack (decrement)
Push user stack (increment)
Arithmetic Instructions
ADC
ADD
CP
DA
DEC
DECW
DIV
INC
INCW
MULT
SBC
SUB
dst, src
dst, src
dst, src
dst
dst
dst
dst, src
dst
dst
dst, src
dst, src
dst, src
Add with carry
Add
Compare
Decimal adjust
Decrement
Decrement word
Oivide.
Increment
Increment word
Multiply
Subtract with carry
Subtract
Loglcalltlstructions
AND
COM
OR
XOR
dst, src
dst
,ds!. src
dst, src
Logical AND
Complement
Logical OR
Logical exclusive
Mnemonic
Operands
Instruction
Program Control Instructions
BTJRT
dst, src
Bit test jump relative on True
BTJRF
dst, src
Biltest jump relative on False
Call procedure
CALL
dst
CPIJE
dst, src
Compare, increment and jump on
equal
CPIJNE
dst, src
Compare, increment and jump on
non-equal
DJNZ
r, dst
Decrement and jump on non-zero
ENTER
Enter
EXIT
Exit
IRET
Return from interrupt
JP
cc, dst
Jump on condition code
JP
dst
Jump unconditional
JR
cc, dst
Jump relative on condition code
Jump relative unconditional
JR
- dst
Next NEXT
RET
Return
WFI
Wait for interrupt
Bit Manipulation Instructions
dst, src '
BAND
BitAND
BCP
dst, src
Bit compare
BITC
dst
Bit complement
BITR
dst
Bit reset
BITS
dst
Bit set
BOR
dst; src
BitOR
dst, src
Bit exclusive OR
BXOR
TCM
dst, src
Test complement under mask
TM
dst, src
Test under mask
Rotate and Shift Instructions
RL
Rotate left
dst
RLC
dst
Rotate left through carry
RR
dst
Rotate right
RRC
dst
Rotate right through carry
SRA
dst
Shift right arithmetic
SWAP
dst
Swap nibbles
CPU Control Instructions
CCF
01
EI
NOP
RCF
SBO
SB1
SCF
src
SRP
SRPO
src
SRP1
src
Complement carry flag
Disable interrupts
Enable interrupts
Do nothing
Reset carry flag
Set bank 0
Set bank 1
Set carry flag
Set register pointers
Set register pointer zero
Set register pointer one
425
INTERRUPTS
The SuperS interrupt structure contains S levels of interrupt,
16 vectors, and 27 sources.
The vector number is used to generate the address of a
particular interrupt servicing routine; therefore all interrupts
using the same vector must use the same interrupt handling
routine.
Interrupt priority is assigned by level, controlled by the
Interrupt Priority register (IPR). Each level is masked (or
enabled) according to the bits in the Interrupt Mask register
(IMR), and the entire interrupt structure can be disabled by
clearing a bit in the System Mode regisfer (R222).
Levels
Levels provide the top level of priority assignment. While the
sources and vectors are hardwired within each level, the
priorities of the levels can be changed by using the Interrupt
Priority register (see FigureS for bit details).
. The three major components of the interrupt structure are,
sources, vectors, and levels. These are shown in Figure 10
and discussed in the following paragraphs.
If more than one interrupt source is active, the source from
the highest priority level will be serviced first. If both sources
are from the same level, the source with the lowest vector will
have priority. For example, if the UART Receive Data bit and
UART Parity Error bit are both active, the UART Parity Error
bit will be serviced first because it is vector 16, and UART
receive data is vector 20.
Sources
A source is anything that generates an interrupt. This can be
internal or external to the SuperS MCU. Internal sources are
hardwired to a particular vector and level, while external
sources can be assigned to various external events.
Vectors
The levels are shown in Figure 12.
The 16 vectors are divided unequally among the 'eight
levels. For example, vector 12 belongs to level 2, while level
3 contains vectors 0, 2, 4, and 6.
INTERRUPT SOURCES
COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P2.)
EXTERNAL INTERRUPT (P2,)
COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P3,)
EXTERNAL INTERRUPT (P3,)
~:~~~~:~,~~~~~~~~ ?P2 4) I
EXTERNAL INTERRUPT (P2s)
,
~:~~~~:LK,~~~~~~~~ (~341 I
EXTERNAL INTERRUPT (P3s)
RESERVEO
POLLING
--,-
i
I
I
II
I
I
I
VECTORS
--,1'2
I
I
1,4
I
I
I
I
128
I
I
I
130
I
I
I
'0
I
I
I'R07
I
12
RESERVED
'6
I
I
18
EXTERNAL INTERRUPT (P22)
i
EXTERNAL INTERRUPT (P23)
10
EXTERNAL INTERRUPT (P33)
UART RECEIVE OVERRUN
UART FRAMING ERROR
UART PARITY ERROR
UART WAKEUP DETECT
UART BREAK DETECT
UART CONTROL CHAR DETECT
16
UART RECEIVE DATA
EXTERNAL INTERRUPT (P3D)
20'
18
22
EXTERNAL INTERRUPT (P2D)
UART ZERO COUNT
EXTERNAL INTERRUPT (P2,)
UART TRANSMIT DATA
EXTERNAL INTERRUPT (P3,)
IR03
I
1'4
EXTERNAL INTERRUPT (P32)
I
---,C
24
26
I
Figure 12. Interrupt Levels and Vectors
426
LEVELS
-r;;2
I
I
I
I'R05
I
I
I
,'R04
I
I
,'ROO
I
I
I
I
I
I
I
I'R06
I
I
I
I
I
I
I
I
IIROI
I
I
I
I
Enables
, Interrupts can be enabled or disabled as follows:
II Interrupt enable/disable. The entire interrupt structure
can be enabled or disabled by setting bit 0 in the System
.Mode register (R222).
m Level enable. Each level can be enabled or disabled by
setting the appropriate bit in the Interrupt Mask register
(R221).
l:I Level priority. The priority of each level can be controlled
by the values in the Interrupt Priority register (R255, Bank
0).
Two hardware registers support fast interrupts. The
Instruction Pointer (IP) holds the starting address of the
service routine, and saves the PC value when a fast interrupt
occurs. A dedicated register, FLAG', saves the contents of
the FLAGS register when a fast interrupt occurs.
To use this feature, load the address of the service routine in
the Instruction Pointer, load the level number into the Fast
'Interrupt Select field, and turn on the Fast Interrupt Enabl,e
bit in the System Mode register.
When an interrupt occurs in the level selected for fast
interrupt processing, the following occurs:
I!l The contents of the Instruction Pointer and Program
Ei1 Source enable/disable. Each interrupt source. can be
enabled or disabled in the sources' Mode and Control
register.
Counter are swapped.
I1l The contents of the Flag register are copied into FLAG:
III The Fast Interrupt Status Bit in FLAGS is set.
Service Routines
Before an interrupt request can be granted, a) interrupts
must be enabled, b) the level must be enabled, c) it must be
the highest priority interrupting level, d) it must be enabled at
the interrupting source, and e) it must have the highest
priority within the level.
If all this occurs, an interrupt request is granted.
The SuperB then enters an interrupt machine cycle that
completes the following sequence:
[J
It resets the Interrupt Enable bit to disable all subsequent
interrupts.
III The interrupt is serviced.
[J
When IRET is issued after the interrupt service outline is
completed, the Instruction Pointer and Program Counter
.
are swapped again.
&lI The contents of FLAG' are copied back into the Flag
register.
III The Fast Interrupt Status bit in FLAGS is cleared.
The interrupt servicing routine selected for fast processing
should be written so that the location after the IRET
instruction is the entry point the next time the (same) routine
is used.
f! It saves the Program Counter and status flags on the
c
stack.
Level or Edge Triggered
It branches to the address contained within the vector
location for ihe interrupt.
Because internal interrupt requests are levels and interrupt
requests from the outside are (usually) edges, the hardware
for external interrupts uses edge-triggered flip-flops to
convert the edges to levels.
1& It passes control to the interrupt servicing routine.
When the interrupt servicing routine has serviced the
interrupt, it should issue an interrupt return (IRET)
instruction. This restores the Program Counter and status
flags and sets the Interrupt Enable bit in the System Mode
register.
Fast Interrupt Processing
The level-activated system requires that interrupt-serving
software perform some action to remove the interrupting
source. The action involved in serving the interrupt may
remove the source, or the software may have to actually
reset the flip-flops by Writing to the corresponding Interrupt
Pending register.
The SuperB provides a feature' called fast interrupt
processing, which completes the interrupt servicing in 6
clock periods instead of the usual 22.
427
STACK OPERATION
The SuperB architecture supports stack operations in the
register file or in data memory. Bit 1 in the external Memory
Timing register (R254 bank 0) selects between the two.
Register pair 216-217 forms the Stack Pointer used for all
stack operations. R216 is the MSB and R217 is the LSB.
The Stack Pointer always points to data stored on the top of
the stack. The address is decremented prior to a PUSH and
incremented after a POP.
The stack is also used as a returnstack for CALLs and
interrupts. During a CALL, the contents of the PC are saved
on the stack, to be restored later. Interrupts cause the
contents of the PC and FLAGS to be saved on the stack, for
recovery by IRET when the interrupt is finished.
be used as a general-purpose register, but its contents will
be changed if an overflow or underflow occurs as the result
of incrementing or decrementing the stack address during
normal stack operations.
User-Defined Stacks
The SuperB provides for user-defined stacks in both the
register file and program or data memory. These can be
made to increment or decrement on a push by the choice of
opcodes. For example, to implement a stack that grows
from low addresses to high addresses in the register fil~, use
PUSHUI and POPUD. For a stack that grows from high
addresses to low addresses in data memory; use LDEI for
pop and LDEPD for push.
When the SuperB is configured for an internal stack (using
the register file), R217 contains the Stack Pointer. R216 may
COUNTER/TIMERS
The SuperB has two identical independently programmable
16-bit counter/timers that can be cascaded to produce a
single 32-bit counter. They can be used to count external
events, or they can obtain their input internally. The internal
input is obtained by dividing the crystal frequency by four.
The counter/timers can be set to count up or down, by
sqftware or. external events. They can be set for single or
continuous cycle counting, and they can be set with a
, bi-value option, where two preset time constants alternate in
loading the counter each time it reaches zero. This can be
used to produce an output pulse train with a variable duty
cycle.
The counter/timers can also be programmed to capture the
count value at an external event or generate an interrupt
whenever the count reaches zero. They can be turned on
and off in response to external events by using a gate and/or
a trigger option. The gate option enables counts only when
the gate line is Low; the trigger option turns on the counter
after a transient High. The gate and trigger options used
together cause the counter/timer to work in gate mode after
.initially being triggered.
.
The control and status register bits for the counter/timers are
shown in Figure 5.
DMA
The SuperB features an on-chip Direct Memory Access
(DMA) channel to provide high bandwidth data
transmission capabilities. The DMA channel can be used by
the UART receiver, UART transmitter, or handshake channel
O. Data clm be transferred between the peripheral and
contiguous locations in either the register file or external
428
data memory. A 16-bit count register determines the
number oftransactions to be performed; an interrupt can be
generated when the count is exhausted. DMA transfers to or
from the register file require six CPU clock cycles; DMA
transfers to or from external memory take ten CPU clock
cycles, excluding wait states.
ABSOWTE MAXIMUM RATINGS
Voltage on all pins with respect
to ground ....................... -O.3Vto +7.0V
Ambient Operating
. Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than these may cause permanent damage to the device.
This is a stress rating only; operation of the device under conditions more
severe than those listed for operating conditions may cause permanent
damage to the device. Exposure to absolute maximum ratings for
extended periods may also cause permanent damage.
STANDARD TEST CONDITIONS
+5V
Figure 14 shows the setup for standard test conditions. All
voltages are referenced to ground, and positive current
flows into the reference pin.
lK
Standard conditions are:
II + 4. 75V ~ Vec~ + 5.25V
• GND = OV
TEST LOAD (FOR ALL PINS)
Standard Test Load
DC CHARACTERISTICS
Symbol
Parameter-
VeH
Vel
VIH
Vil
VRH
VRl
VOH
VOL
III
IOl
IIR
lee
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Reset Input High Voltage
Reset Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Reset Input Current
Vee Supply Current
Min
Max
Unit
3.8
-0.3
Vee
0.8
2.2
Vee
0.8
V
V
V
V
V
V
V
V
-0.3
3.8
-0.3
2.4
-10
-10
Vee
0.8
0.4
10
10
-50
320
Condition
Driven by External Clock Generator·Driven by External Clock Generator
IOH = -400fJA
IOl =' + 4.0 rnA
JJA
JJA
fJA
rnA
429
INPUT HANDSHAKE TIMING
_'N.
~_~16
.~
RDYOUT
Strobed Mode
Fully Interlocked Mode
AC CHARACTERISTICS (20 MHz)
Input Handshake
Number
Symbol
Parameter
1
TsDI(DAV) .
2
TdDAVIf(RDY)
3
ThDI(RDY)
Data In Hold Time from RDY ~
Data In to Setup Time
Min
4
TwDAV
DAVlnWidth
ThDI(DAV)
Data In Hold Time from DAV ~
6
TdDAV(RDY)
DAV t Input to RDY t Delay
7
TdRDYf(DAV)
RDY ~ Output to DAV t Delay
200
o
45
130
100
o
NOTES:
1. Standard Test Load
2. This time assumes user program reads data before DlW Input goes high. ROY will not go high before data is read.
+Times given are in ns.
"Times are preliminary and subject to change.
430
Notes·;
o
. DAV ~ Input to RDY ~ Delay
5
Max
2·
OUTPUT HANDSHAKE TIMING
DATA OUT
~'--'~--j--1~------6--------------
DAY OUT
-
Fully Interlocked Mode
'k...J'
Strobed Mode
AC CHARACTERISTICS (12 MHz, 20 MHz)
Output Handshake
Number
Symbol
Parameter
TdDO(DAV)
Data Out to DAV +Delay
TdRDYr(DAV)
RDY t Input to DAV +Delay
0
3
TdDAVOf(RDY)
DAV +Output to RDY + Delay
0
4
TdRDYf(DAV)
RDY +Inputto DAV t Delay
0
5
TdDAVOr(RDY)
DAV t Output to RDY t Delay
6
TwDAVO
DAV Output Width
'2
Min
Max
Notes·:!:
90
1,2
110
1
110
0
150
2
NOTES:
1. Standard Test Load
2. Time given is for zero value in Deskew Counter. For nonzero value of n where n = 1, 2, ... 15 add 2 x n x TpC to the given time.
:j:Times given are in ns.
"Times are preliminary and subject to change.
AC CHARACTERISTICS (12 MHz)
Read/Write
Normal Timing
Min
Max
Extended Timing
Min
Max
Number
Symbol
Parameter
TdA(AS)
Address Valid to AS t Delay
35
115
2
TdAS(A)
AS t to Address Float Delay
65
150
3
TdAS(DR)
AS t to Read Data Required Valid
4
TwAS
AS Low Width
270
65
Notest*
600
150
5
TdA(DS)
Address Float to DS +
20
20
6a
TwDS(Read)
DS (Read) Low Width
225
470
6b
TwDS(Write)
DS (Write) Low Width
130
7
TdDS(DR)
DS +to Read Data Required Valid
8
ThDS(DR)
Read Data to DS t Hold Time
295
180
420
0
0
9
TdDS(A)
DS t to Address Active Delay
50
135
10
TdDS(AS)
DS t to AS +Delay
60
145
11
TdDO(DS)
Write Data Valid to DS (Write) + Delay
35
115
12
TdAS(W)
AS t to Wait Delay
13
ThDS(W)
DS t to Wait Hold Time
0
0
14
TdRW(AS)
R,iii Valid to AS t Delay
50
135
220
600
2
NOTES:
1. WAIT states add 167 ns to these times.
2. Auto-wait states add 167 ns to this time.
:I: All times are in ns and are for 12 MHz input frequency.
• Timings are preliminary and subject to change.
431
AC CHARACTERISTICS (20 MHz)
Read/Write
Number
Symbol
Parameter
Normal Timing
Min
Max
1
TdA(AS)
Address Valid to AS t Delay
20
2
TdAS(A)
AS t to Address Float Delay
35
3
TdAS(DR)
AS t to Read Data Required Valid
4
TwAS
AS Low Width
Extended Timing
Min
Max
50
85
150
35
335
85
5
TdA(DS)
Address Float to DS ~
0
0
6a
TwDS(Read)
DS (Read) Low Width
125
275
6b
TwDS(Write)
DS (Write) Low Width
65
7
TdDS(DR)
DS ~ to Read Data Required Valid
8
ThDS(DR)
Read Data to DS t Hold Time
165
80
225
0
0
9
TdDS(A)
DS tto Address Active Delay
20
70
10
TdDS(AS)
DS t to AS ~ Delay
30
80
11
TdDO(DS)
Write Data Valid to DS (Write) ~ Delay
10
12
TdAS(W)
AS t to Wait Delay
13
ThDS(W)
DS t to Wait Hold Time
0
0
14
TdRW(AS)
R/IN Valid to AS t Delay
20
70
50
90
335
2
NOTES:
1. WAIT states add 100 ns to these times.
2. Auto·wait states add 100 ns to this time.
t All times are in ns and are for 20 MHz input frequency.
• Timings are preliminary and subject to change.
PORTO
DM ____
-J~------~----------------------------------------------------~~
PORT 1
....------------------{12)-----~--------_!.11------"']1~
External Memory Read and Write Timing
432
ADDRESS OUT ~___________~~__A_~_A1_3______~______-J)(~__________
---J1~~--------~0r--------~1
DATAIN======~==========================~r--D~-D-7-IN~)(~___________
EPROM Read Timing
AC CHARACTERISTICS (20 MHz)
EPROM Read Cycle
Number
Symbol
Parameter
TdA(DR)
Address Valid to Read Data Required
Valid
Min
Max
170
NOTES:
1. WAIT states add 167 ns to these times.
:j:A1I times are In ns and are for 12 MHz input frequency.
·TImlngs are preliminary and subject to change.
433
Zilog
Application Note
August 1987
GETTING STARTED
WITH THE ZILOG SUPERS
by Charles M. Link, II
a
Any time an engineer switches to new processor, he
usually begins the time consuming process of learning
the quirks of the new part. This article is the first of a
series of articles written to speed that transition time from
any other processor to the Zilog Super8.
Getting started is the most difficult part of switching to a
strange new processor and development tools. Weeks
can be spent just getting the first lines of initialization
code written and successfully assembled. Testing the
code becomes another problem. The soft ,re from this
article series has been tested and it should be possible
to copy most of the software directly to a user's application. All of the software is available in machine readable
form as noted at the end of the article.
This first article demonstrates the proper initialization of
the Zilog Super8 microcontroller. It sets up a Z8800
ROMLESS for 64K,bytes of external program memory,
although most typical applications probably do not require more than maybe 4K or 8K bytes. Ports 2 and 3,
which are bit'mappable as inputs or outputs, are set into
the output mode. Port 4, also bit mappable, is set into
the input mode. A hardware ,schematic has been includedas an example.
The hardware schematic shown defi~es a simple SuperS
implementation that was used to test the code in this
series oj articles. This example defines a simple evaluation board that contains ,32K bytes of programable
EPROM, and up to 32K bytes of RAM. The design contains a simple RS-232 interface that is used in future articles of the series. The entire board, including the
RS-232 interface,is powered from 5 volts. The RAM
battery option allows the software to be downloaded into
the RAM and saved if power fails. Additional logic on the
design allows a user to protect the lower half of RAM
with a simple jumper change. This prevents the processor from destroying executable code if it goes off into
space on a power failure.
Specifically, the ROM LESS SuperS is used as the core.
The Super8 requires a latch to demuHiplex the address
from the data bus. A 74LS373 fits nicely here, requiring
only an inverter to correct for the address strobe. The
'LS373 with inverter is preferred here rather than a single
'LS374 because the 'LS373 is a transparent latch and
434
will present the address earlier than the 'LS374. JU1
selects the EPROM size, correcting for thelPGM pin on
2764 and 27128 EPROMs. It is necessary to use pull
down resistors on the upper 4 bits of the address bus because on reset, the ROMLESS Super8 defines only 12
bits for address; the other 4 are set as inputs. Since LSTIL devices require more current to pull down the inputs,
this pull down trick will only work for MOS and CMOS inputs, hence the requirement for the logic chips in this
design to be HCT type devices.
The remaining logic is required to select the EPROM or
RAM. JU2 selects the half-RAM protect mode. JU3 is
set to determine what size ram to protect. This circuit allows the lower half of CMOS battery backed RAM to be
read only, and removes chip select on any writes to that
address space. Of course, that exact circuitry and the
battery is optional, and might be replaced by a power
threshold detector. On the other front, a Maxim MAX
232 provides the RS-232 interface requiring only 5 volts.
To make the software initialization more interesting, a
few other typical initialization tasks are demonstrated.
The entire block of registers (user ram) is cleared to
zero, and one of the counter timer units is initialized to
provide a periodic interrupt to form the heart of a real
time clock function.
'
The program shows the typical pseudo-op usage
demonstrated. This article series uses a cross assembler available from Zilog for either an IBM PC or a
VAX operating under VMS. The program bElgins by
defining the registers used as general purpose storage.
This is done so the user does not have to refer to register
numbers, but may refer to a name equated to the
register.
The first 32 bytes of every program (beginning at OOOOH)
always contain the interrupt vectors for the different sources. Using the Zilog assembler, the .wORD pseudo-op
defines a pair of bytes for each of the 16 sources.
Program execution begins at location 0020H. Since
copyright requirements usually require the notice as
close to the beginning as possible, it becomes necessary
to jump around an ASCII string. The .ASCII pseudo-op
generates the necessary string for this notice.
The source code describes almost completely, without
further explaination, the entire initialization. Once initialized, the processor loops in a WAIT loop waiting on the
periodic interrupt generated by the counterllimer. .The
counter timer interrupts 60 times per second, and the interrupt bumps ram storage locations representing
seconds, minutes, and hours. Each time a location is
bumped, an external port line is toggled so that those
without emulators can see some activity with an oscIlloscope.
One point of notice, is the interrupt service routine for the
timer. One must reset the end of count interrupt bit (the
source of interrupt) before exiting the interrupt service
routine.
.TITLE
In the next article of this series, we will take the same
basic initialization routine and modify it to support the
serial UART. That article will demonstrate polled serial
communications using the Zilog Super 8.
[Editors note: The sofware for this series is available on
an IBM PC diskette and is included with the Super 8
Emulator package available from Creative Technology
Corporation, 5144 Peachtree Road, Suite 30'1, Atlanta,
GA 30341. (404) 455-8255. Any Zilog Field Application
engineer should also be able to provide copies of the
software on a user provided diskette.]
Sample Zilog super 8 Initialization
;===--=====================================================~=
;=
;=
;=
TITLE:
DATE:
PURPOSE:
INIT.S8
JUNE 17, 1986
TO DEMONSTRATE INITIALIZATION
OF THE ZILOG SUPER 8-USING THE
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II
;=
;=
;=
PROGRAMMER:
;===========================================================
• PAGE
;set maximum page size to 55 lines
55
;***********************************************************
i*
If
REGISTER EQUATE TABLE
*
:*
*
;***********************************************************
,
period:
second:
minute:
hours:
.equ
.equ
.equ
.equ
o
;period timer
,; seconds timer
;minutes timer
;hours timer
1
2
3
; * ***** ********* *** ****** 'A'** ******* .... '* '* ** ** .. *** ** it-... '* *. **.* ..
;*
\
INTERRUPT VECTOR TABLE
:*
'*
*
'*
;***********************************************************
;
INTRO: • WORD
INTR1: • WORD
INTR2: • WORD
INTR3 : ,• WORD
INTR4 : • WORD
INTR5: • WORD
INTR6: • WORD
INTR7: • WORD
INTR8: .WORD
INTR9: .WORD
INTR10: .WORD
INTRll: .WORD
INTR12: .WORD
INTR13: .WORD
INTR14: .• WORD
INTR15: .WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
;this area should always be defined
;as' it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.
;***********************************************************
'*
*
*
'***********************************************************
:*
;*
START OF PROGRAM EXECUTION
435
START:
jr
• ASCII
START1: di
sbO
ld
ld
ld
ld
ld
;program execution unconditionally
;begins at this location after reset
;and power up.
'REL 0 6/16/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
.
;se1ect register bank 0
EMT,I/OOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
;and DMA internal
;address begins at OOOOh, set upper byte
PO,I/OOH
POM, #11111111B ;select all lines as address
;enable port 0 as upper 8 bits address
PM, #00110000B
H1C,1/00000000B ;handshake not enabled port 0
START 1
;port 1 is defined in romless part as address/data.
;here to initialize that port
.
it is not necessary
;port 2 outputs low
;port 3 outputs low
;p30,31,20,21 as output
;p32,33,22,23 as output
;p34,35,24,25 as output
;p36,37,26,27 as output
ld
ld
ld
ld
ld
ld
P2,J/00H
P3,J/00H
P2AM,j/10101010B
P2BM,#10101010B
P2CM,#10101010B
P2DM,#10101010B
ld
ld
ld
;clear port 4 register
P4,#00000000B
P4D, #11111111B ;set all bits of P4 as inputs
NOD,I/OOOOOOOOB ;active push/pull [not necessary since all
; bits are,inputs
;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,#OCOH
RP1,j/OC8H
SPL,J/OFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here ,that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
;as stack operation. SPH is general purpose
;storage.
;now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,J/OFFH
@SPH
SPH
nz,ZERO
@SPH
;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register
;now everything except working registers is cleared
cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
sb1
ld
1d
ld
sbO
ld
SYM,#OOOOOOOOB
IPR, #00000010B
;disable fast interrupt response
; interrupt priority \
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQi
IMR,#00000100B ;enable only interrupt 2
;select bank 1
COTCH,#AHB(50000)
;high byte of time constant
COTCL,I/ALB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freq, 4 is internal divider
COM,1/00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,J/10100101B ;continuous, count down, load counter,
;zero count interrupt enable, enable counter
timer is initialized, now lets enable interrupts and wait
WAIT:
..
436
ei
nop
nop
nop
nop
jr
;enable interrupts
WAIT
;loop back
nop
nop
nop
TIMERO: inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
clr
NOROLL: or
nop
nop
INTRET: iret
period
period, #60
ne,NOROLL
;bump periodic counter (60 hertz)
;one second yet?
;no rollover
P2,#00000001B
;complement the second bit
period
;start it over again
;bump the seconds timer
second
;reached maximum
second, #60
;no
rollover
ne,NOROLL
P2,#00000010B
;complement the minute bit
;start it over again
second
;bump the minutes timer
minute
;reached maximum
minute, #60
;no rollover
ne,NOROLL
P2,i/00000100B
;complement the hour bit
minute
;start it over again
;bump the hours timer
hours
;reached maximum
hours, #24
ne,NOROLL
;no rollover
;start it over again
hours
COCT,#OOOOOOlOB ;reset end of count interrupt
;and return from interrupt
• END
437
•
-
~
Zilog,
-
•
__ ".,1
,_
".' "-'. .- -. ." --
Application Notif
~"
"'
,,,"
-
,
.,
~
August 1987
.
-.
,
<
•
POLLED ASYNCHRONOUS
SERIAL OPERATION
WITH THE ZILOG SUPERB
by Charles M. Link, II
The transition from one processor to another often involves many hours oftrial-and-error software development
to determine the quirks (manufacturers call it features) of
the part.
Once the real features are discovered,
programming the processor to perform as described can
be hazardous to one's health. This article, the second in
a series of eight, attempts to introduce the Zilog Super8
user to the serial communications port, and its initialization in a polled serial environment.
The universal asynchronous receiver/transmitter (UART)
on the Super8 is a fairly unique implementation among
single chip microcomputers in that it supports all of the
functions generally available only on chip level UARTs.
The UART is a close approximation of the Z80 DART
device in one channel.
It supports independent
receiver/transmitter clocking, 5 to 8 bits per character,
plus optional odd or even parity, and even an optional
wake-up bit. ,The UART can serve full duplex communications via polled, interrupt, or DMA modes of
operation. Auto-echo and intemal loopback can be
programmed as options. The most unique of the UART
features is the character match and interrupt option.
The following article describes the initialization and use
of the UART in a polled environment. This software has
been tested and provides several routines that may be
copied into a user's software. Although the demonstration software does not do much, it is fully functional as a
stand~alone program, and may be "burned" into eprom
as a test.
The basic software is almost the same general purpose
initialization software from the first article in the series.
Routines set-up counter/timer 0 for a real time clock option, Note, however, the change to configuration register
P2AM. It is necessary to configure port 30 as input for
receive data and p31 as output for transmit data.
The UART initialization sequence begins by setting the
functions in the UART MODE A register. Since the UMA
register is in the alternate bank, the instruction SB1 must
be executed to gain access to the following registers.
The loaded data selects a X16 clock, 8 bits per character, no parity, and no wake up values. Note that the
clock options are X1, X16, X32, and X64. For true
asynchronous operation, a clock multiplier option of at
least X16 is required. The X1 mode could be used for
externally syncing the received data to the UART. The
transmitter is not affected.
438
Next, the baud rate generator must be loaded. The formula for determining the baud rate is shown below:
TIME CONSTANT = (XTAL FREQ I 8 I CLOCK MULT I
DESIRED RATE) - 1
where TIME CONSTANT is a 16 bit value, XTAL FREQ
is the crystal ifrequency in hertz, CLOCK MULT is the
clock rate loaded into UART MODE A register (as above
X1, X16, X32, and X64), and DESIRED rate is the
desired bit rate in bits per second. Note that the baud
rate generator may be used as an additional counter,
and may be loaded with any value permitting just about
any crystal frequency to operate the Super8.
The cross-assembler permitted a single 16-bit decimal
number to be loaded into the UART BAUD RATE GENERATOR, high and low byte, without unnecessary figuring using the high/low byte pseudo-op.
The initialization sequence continues, with the UART
MODE B register next. This example sends port 21 data
to the port 21 pin. An option allows different clocks to be
sent out from this pin. It could be used for clocking external logic, or for diagnostic purposes to make sure the
baud rate generator is running.
Auto-echo is not
selected in this application, as that is primarily what the
example software does. The receive and transmit clock
input is the baud rate generator and the generator source
is the internal clock;' the crystal divided by four. Since
the baud rate generator has been loaded, it is enabled,
and the UART is set for normal operation (without loopback). Loopback operation permits transmitting and
receiving data without any external logic in front of the
Super8.
The UART TRANSMIT CONTROL register is initialized
next in the sequence. Select transmit data out on port 31
and transmit enable. The stop bits are optional, and the
DMA and WAKE-UP enables are for features discussed
in future application articles. At this point, the transmitter
is operational, and except for housekeeping, is usable.
The housekeeping is in reference to selecting the bank 0
by executing the SBO instruction.
Since polled mode communications are desired, all of the
UART interrupts are disabled by loading the UART INTERRUPT ENABLE with all zeros. Lastly, the receiver
must be enabled by setting bit 0 of the UART RECEIVE
CONTROL register.,
This program primarily sends a message to the console
and then accepts input from the console and echos it
upon receiving a carriage return. It is necessary to delay
sending data to the console after initialization because
the transmit data line is in the SPACE state when idle.
Alternately, add a pull-up resistor to the output, and while
idle and before initialized, it would exibit the MARK state.
The transmit character routine "SENDC" monitors the
TRANSMIT BUFFER EMPTY bit of the UART TRANSMIT CONTROL register. When this bit is a "1", the trqnsmit buffer is empty and may be loaded with a new
character for' transmission. To transmit a character, load
the character into the UART data register (UIO) .
• TITLE
samp~e
The receive character routine "GETC" monitors the
RECEIVE CHARACTER AVAILABLE bit of the UART
RECEIVE CONTROL register. When this bit is a "1", a
new character has been received by the UART.
The polled mode of UART operation is simple. Making
the UART operate in an interrupt mode requires a few
minor modifications, and DMA mode requires a few more
modifications. Those modes are the subject of future application articles in this series.
Zilog super 8 Serial Port Initialization
;===========================================================
j=
j=
j=
ASSEMBLER:
PROGRAMMER:
UARTl.S
JULY 17, 1986
TO DEMONSTRATE INITIALIZATION
AND USAGE OF SERIAL PORT IN
POLLED MODE.
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, I I
• PAGE
;set maximum page size to 55 lines
TITLE:
DATE:
PURPOSE:
;=
j=
j=
;=
j===========================================================
55
;~**.*.*.*~*~*6.**
j*
;'*
•• **.******************************* ******
*
GENERAL EQUATES
i*
*
; 1:********,'ll******************************************* ******
CR:
LF:
.equ
.equ
;carriage return
;line feed
OdH
OaH
,
:***********************************************************
i*
REGISTER EQUATE TABLE
i*
*
'*
*
i***************************************************** ******
,
period: .equ
0
;period timer
second: .equ
1
;seconds timer
minute: .equ
2
;minutes timer
hours:
.equ
3
;hours timer
;working register equates
MPTR:
. equ
RR8
;message pointer for external memory
,
i***************************************************** ******
:*
*
INTERRUPT VECTOR TABLE
*
*
:***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10
INTRll
INTR12
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
. WORD
. WORD
• WORD
• WORD
. WORD
• WORD
. WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMER!!
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
this area should always be defined
as it reserves the lower 32 bytes
for the interrupt table. the name
of the subroutine for each particular
interrupt service would normally be
named here.
439
INTR13
INTR14
INTR15
,
• WORD
• WORD
• WORD
INTRET
INTRET
INTRET
;***********************************************************
;*
;*
*
*
START OF PROGRAM EXECUTION
*
:*
;***********************************************************
START:
jr
• ASCII
START1: di
sbO
ld
,
ld
ld
ld
ld
;program execution unconditionally
;begins at this location after reset
;and power up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register bank 0
EMT,I/OOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
;and DMA internal
;address begins at OOOOh, set upper byte
PO,I/OOH
POM,1/11111111B ;select all lines as address
;enable port 0 as upper 8 bits address
PM,I/00110000B
HIC,#OOOOOOOOB ;handshake not enabled port 0
START 1
;port 1 is defined in romless part as address/data.
;here to initialize that port
ld
ld
ld
ld
ld
ld
ld
ld
ld
,
it is not necessary
;port 2 outputs low
P2,#00H
;port 3 outputs low
P3,#00H
P2AM,#10001010B ;p31,20,21 as output,p30 input
;it is necessary here to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM,#10101010B ;p32,33,22,23 as output
P2CM,#10101010B ;p34,35,24,25 as output
P2DM,#10101010B ;p36,37,26,27 as output
P4,/lOOOOOOOOB
;clear port 4 register
P4D, #11111111B ;set all bits of P4 as inputs
P40D,#00000000B ;active push/pull [not necessary since all
; bits are inputs
;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,#OCOH
RPl,#OC8H
SPL,#OFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
;as stack operation.
; storage.
SPH is general purpose
'
; now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,/IOFFH
@SPH
SPH
nZ,ZERO
@SPH
;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register
; now everything except working registers is cleared
; cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
sbl
ld
ld
ld
440
SYM,#OOOOOOOOB
IPR,/l00000010B
;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR, #00000100B ; enable only interrupt, 2
;select bank 1
COTCH,#AHB(50000)
;high byte of time constant
COTCL,#ALB(50000)
;low byte of time constant
,
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freq, 4 is internal divider
COM,#00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
sbO
ld
COCT,#l0100101B
,
select bank 0
continuous, count down, load counter,
zero count interrupt enable, enable counter
;timer is set, now lets initialize the UART for polled operation
sb1
ld
ld
ld
ld
sbO
ld
ld
ld
;bank 1
UMA,#01110000B
;tim~ constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH,#AHB(00009)
;high byte of time constant
UBGL,#ALB(00009)
;low byte of time constant
UMB,#00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
;is disabled
;select bank 0
UTC,#10001000B ;select p31 as transmit data out, 1 stop bit
;and transmit enable
UIE,#OOOOOOOOB ;disable all interrupts, no OMA
URC,#00000010B ;enable receive
;UART is initialized, enable interrupts for real time clock
,
ei
;enable interrupts
;wait 1 full second for serial line to mark before sending anything
WAIT:
cp
jr
second,#1
ne,WAIT
;wait 1 second
;display the logon message
LOGON:
ldw
call
MPTR,#MSG
SENOM
;load the address of MSG into word reg MPTR
;send the message
;iogon message displayed, get response from console
;and move to upper register memory
GET:
GETN:
,
ld
ld
call
and
call
ld
cp
jr
inc
djnz
r1,#80
r2,#80H
GETC
rO,#7fH
SENOC
@r2,rO
rO, #CR
eq,ECHO
r2
r1,GETN
;maximum character count
;point to first location in upper register bank
;get input from console
;remove upper parity bit
;echo to console
;move to upper internal ram in Super8
;was the received character a carriage return
;if so, echo it to console
;bump pointer
;get next character if not done
;if carriage return typed, or 80 characters exceeded, echo message
ECHO:
ECH01:
,
ldw
call
ld
ld
ld
call
cp
jr
inc
djnz
jr
MPTR, #MSG1
SENOM
r1,#80
r2,#80H
rO,@r2
SENOC
ro, #CR
eq,LOGON
r2
r1,ECH01
LOGON
;load the address of MSG1 in word reg MPTR
;send the message
;maximum character count
;first location of character buffer
;get character from buffer
;send the character to console
;carriage return?
;if so, end message display
;bump pointer
;display next character if not done
; subroutines
,
;send message at MPTR until '$' character found
SENOM: ldci
rO,@MPTR
;get the character
call
SENOC
;otherwise send character
cp
;last character?
rO,#'$'
jr
ne,SENOM
;and loop back to send next one
ret
441
;send character in rO
UTC,#OOOOOOlOB
SENDC: tm
jr
z,SENDC
ld
UIO,rO
ret
;get a character from the uart,
tm
URC,#OOOOOOOlB
GETC:
jr
z,GETC
ld
rO, UIO
ret
transmit buffer empty yet
if not, wait until it is
load the character into the transmitter
return in rO
;character available
;if not, wait until it is
;get the character from the receiver
,
;real time interrupt running in background
TIMERO: inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
clr
NOROLL: or
nop
nop
INTRET: iret
MSG:
MSG1:
• ASCII
• ASCII
• ASCII
.END
442
period
period, #60
ne,NOROLL
P2,#00000001B
. period
second
second,#60
ne,NOROLL
P2,#00000010B
second
minute
minute, #60
ne,NOROLL
P2,#00000100B
minute
hours
hours, #24
ne,NOROLL
hours
COCT,#OOOOOOlOB
ibump periodic counter (60 hertz)
ione second yet?
ino rollover
icomplement the second bit
istart it over again
ibump the seconds timer
ireached maximum
. ino rollover
icomplement the minute bit
istart it over again
ibump the minutes timer
ireached maximum
ino rollover
icomplement the hour bit
istart it over again
ibump the hours timer
ireached maximum
ino rollover
istart it over again
ireset end of count
iand !eturn from interrupt
CR,LF, 'SuperB Uart test program. ',CR,LF
'Enter up to one full line followed by return',CR,LF,'$'
CR,LF,'Echoed back, your line was ••• ',CR,LF,'$'
August 1987
USING THE ZllOG SUPERS
IN INTERRUPT DRIVEN
COMMUNICAT~ONS .
by Charles M. Link, II
The power of the Super8 microcomputer lies in its on
board peripherals. One of those peripherals is the full
duplex UART. The UART can operate under program
control in polled mode, or under interrupt control, and in
a DMA mode. This article, the third in a series, discusses using the UART in a fully interrupt driven system.
Since it is assumed that the reader has access to the
eariler article discussing the UART and the polled mode·
of operation, this article will only discuss the differences.
The Zilog Super8 contains an on board interrupt controller that is tightly linked to the other on-board peripherals.
The UART, being on-board, can be operated in an interrupt mode permitting very little execution overhead time
while monitoring the UART for incomming characters and
waiting for the UART to send outgoing characters.
Operation of an interrupt driven system demands more
software logic to control the interrupt. Although more
software is present, less time is spent executing it, because most of the overhead is in the setup for interrupt
transfers. Generally, interrupt driven serial 1/0 overlaps
some other process or processes, and therefore enhances total system speed and operation. Interrupt driven
1/0 has no advantages in a system that must wait on the
serial port. In the example program, no real advantage
has been gained by interrupt operation. The program
displays a simple message to the console, and accepts
input responses anq echos them.
For program
simplicity, the main program waits on the interrupt to
complete before starting the next phase of the program.
In any interrupt driven system, the central processor
must know what to do when an interrupt occurs. The
SuperS is no exeception. An interrupt vector table
directs the processor to begin execution at certain addresses for particular interrupt inputs. The UART can be
the source for up to five different interrupts and therefore
up to five of the sixteen vectors can be designated for it.
This sample program ignores errors and special condition interrupts, and therefore only two vectors are used;
one for transmit buffer empty and one for receive character available. These vectors are programmed into the
vector table by setting interrupt vector 10 (zero
reference) to the address for the receive data service
routine, and setting interrupt vector 13 to the address for
the transmit data service routine.
The setup of the SuperS is essentially the same as that
of the serial port in a polled mode of operation. The
proper priority for the interrupts are assigned arbitrarily.
The real time clock as highest priority, the receive
character available as second priority, and transmit
character buffer empty as the lowest priority. Generally,
the transmit interrupt should be the lowest in an
asynchronous system because if it does not get serviced
iimmediately, no major problems occur. If the real time
interrupt took more time in relationship to the time required to transmit a single character, then maybe the
receive should be put higher. If the receiver is not serviced, that character would be lost.
Enabling the interrupts is a two stage process. First the
mask in the INTERRUPT MASK REGISTER must be
enabled for each level of the interrupts used. Next, it is
necessary to enable the individual transmit and receive
interrupts. In the example program, a character is
loaded into the transmit buffer and then the interrupt is
enabled by setting bit 2 in the UART INTERRUPT
ENABLE (UIE) register. Each successive transmit interrupt indicates an empty buffer, and the next character is
loaded into the buffer. When the last character is loaded
into the buffer, the transmit interrupt is disabled to
prevent further interruptions by clearing bit 2 of the UIE
register.
The receiver interrupt is enabled to allow the processor
to accept incoming characters by setting bit 0 of the UIE
register. Once set, any received character will cause the
processor to transfer control to the "RXDATI" routine. In
this example, the receive service routine reads, echos,
and stores each received character until a carriage
routine is received. The input is then repeated.
The example program does not fully utilize the interrupt
system, as· it waits for each routine to complete before
moving to the next. However, it does however work, and
demonstrates interrupt. service routines. Serial interrupt
software is not complex, and could lead to very powerful
user programs. With the addition of the on board DMA to
automaticlly transfer characters, the SuperS can complete many tasks that previously would require complex
hardware and software. The next article in the series
demonstrates using the DMA controller with the serial
port.
443
.TITLE
Sample Zilog Super 8 Serial Interrupt Mode Operation
:===========================================================
~=
i=
j=
TITLE:
DATE:
PURPOSE:
UART2.S
JULY 17, 1986
TO DEMONSTRATE INTERRUPT
DRIVEN SERIAL PORT
COMMUNICATIONS
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, I!
i=
;=
;=
i=
ASSEMBLER:
PROGRAMMER:
i===========================================================
• PAGE
55
;set maximum page size to 55 lines
;***********************************************************
i*
;*
GENERAL EQUATES
*
*
*
i*
;***************************~**~********************** ******
CR:
LF:
.equ
.equ
;carriage return
;line feed
OdH
OaH
,
;***********************************************************
i*
;*
REGISTER EQUATE TABLE
*
*
*
i***************************************************** ******
i*
,
period: .equ
0
;period timer
second: • equ
1
; seconds timer
minute: .equ
2
;minutes timer
hours:
.equ
3
;hours ,timer
;working register equates
MPTR:
.equ
RR8
;message pointer for external memory
,
;***********************************************************
i*
INTERRUPT VECTOR TABLE
i*
*
**
;***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
INTRll:
INTR12:
INTR13:
INTR14:
INTR15:
,
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
. WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
TXDATI
INTRET
INTRET
;this area should always be defined
las it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt se~!ice would normally be
;named here.
;***********************************************************
*
:*
;*
START OF PROGRAM EXECUTION
*
;*
*
i***************************************************** ******
START:
jr
• ASCI!
START1: di
sbO
444
START 1
;program execution unconditionally
;begins at this location after reset
land power up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
:select register bank 0
ld
EMT,J/OOOOOOOOB
ld
ld
ld
ld
PO,lIOOH
POM, #11111111B
PM,#00110000B
H1C,#00000000B
;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
;and DMA internal
;address begins at OOOOh, set upper byte
;select all lines as address
;enable port 0 as upper 8 bits address
;handshake not enabled port 0
port 1 is defined in romless part as address/data.
here to initialize that port
ld
ld
ld
ld
ld
ld
.
ld
ld
ld
it is not necessary
;port 2 outputs low
P2,l/00H
;port 3 outputs low
P3,j/00H
P2AM,#10001010B ;p31,20,21 as output,p30 input
;it is necessary here to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM, #10101010B ;p32,33,22,23 as output
P2CM,#10101010B ;p34,35,24,25 as output
P2DM,#10101010B ;p36,37,26,27 as output
P4,j/00000000B
;clear port 4 register
P4D, j/11111111B ;set all bits of P4 as inputs
P40D,j/00000000B ;active push/pull [not necessary since all
; bits are inputs
;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,j/OCOH
RP1,j/OC8H
SPL,j/OFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
;as stack operation. SPH is general purpose
;storage.
;now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,l/OFFH
@SPH
SPH
nz,ZERO
@SPH
;point to top of general purpose register
izera it
;do it until register set is all cleared
;zero last register
inow everything except working registers is cleared
; cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
sb1
ld
ld
ld
sbO
ld
SYM,#OOOOOOOOB
IPR,j/OOOOOOlOB
;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,j/01000110B ;enable counter, rx and tx interrupts
;select bank 1
COTCH,j/ A HB(50000)
;high byte of time constant
COTCL,j/ A LB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 6Q hertz
;12 Mhz is xtal freq, 4 is internal divid~r
COM,j/00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,#10100101B ; continuous, count down, load counter,
;zero count interrupt enable, enable counter
timer is set, now lets initialize the UART for polled operation,
sb1
ld
UMA,j/01110000B
;bank 1
ld
ld
ld
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH,j/ A HB(00009)
;high byte of time constant
UBGL,j/ A LB(00009)
;low byte of time constant
UMB,'00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
;is disabled
445
sbO
ld
UTC,#10001000B
ld
ld
UIE,#OOOOOOOOB
URC,#00000010B
;select bank 0
;select p31 as transmit data out, 1 stop bit
;and transmit enable
;no interrupts, no DMA
;enable receive
;UART is initialized, enable interrupts for real time clock
,
ei
;enable interrupts
;wait 1 full second of serial line mark before sending anything
WAIT:
cp
jr
second,#l
ne,WAIT
;wait 1 second
;display the logon message
LOGON:
,
ldw
call
call
MPTR, #MSG
SENDM
TXWAT
;load the address of MSG into word reg MPTR
;send the message
;wait for transmitter to complete
;logon message displayed, get response from console
;and move to upper register memory
GET:
ld
;maximum character count
r1,#80
;point to first location in upper register bank
ld
r2,j/80H
;stop interrupts
di
or
UIE,#OOOOOOOlB ;receive character enable
ei
inow wait for input to be completed
GW:
tm
UIE,j/00000001B ;wait for interrupt to be disabled
jr
nZ,GW
;if interrupt still enabled
,
;if carriage return typed, or 80 characters exceeded, echo message
ECHO:
ldw
call
MPTR, j/MSG1
SENDM
;load the address of MSGl in word reg MPTR
;send the message
;since messages are interrupt driven, we must wait for message to
;complete before transmitting next message
ECH01:
call
ld
ld
ld
call
cp
jr
inc
djnz
jr
TXWAT
r1,#80
r2,j/80H
rO,@r2
SENDC
rO,#CR
eq,LOGON
r2
r1,ECH01
LOGON
;wait on transmitter
;maximum character count
;first location of- character buffer
;get character from buffer
;send the character to console
;carriage return?
;if so, end message displ?y
;bump pointer
;display next character if not done
; sUbroutines
,
;send message at MPTR until '$' character found
SENDM: ldci
;get the character
rO,@MPTR
call
;start UART transmitting
SENDC
di
;no interrupts
or
UIE,j/00000100B ;enable transmit interrupts
ei
ret
;send character in rO
SENDC: tm
UTC,#00000010B ;transmit buffer empty yet
;if not, wait until it is
jr
z,SENDC
;load the character into the transmitter
ld
Ulo,ro
ret
;transmit buffer available interrupt
TXDATI: ldci
rO,@MPTR
;get next character to transmit
;load the character in transmitter
ld
UIO, rO
;last character
cp
rO,#'$'
;if last transmit character
jr
eq,LASTT
iret
LASTT: and
UIE, #11111011B ;disable transmit interrupts
iret
;ignore it if no character to transmit
; transmitter wait routine
TXWAT: tm
UIE,j/00000100B ;wait until interrupts disabled
jr
;wait if bit set
nz,TXWAT
ret
446
;receive character available interrupt
RXDATI: ld
rO,UIO
;get input from console
;remove upper parity bit
and
rO,#7fH
call
SENDC
;echo to console
ld
@r2,ro
;move to upper internal ram in SuperB
;lvas the received character a carriage return
cp
rO, #CR
;if so, disable interrupts
jr
eq,LASTR
inc
r2
;bump pointer
djnz
rl,RXR
;exit if not last
LASTR: and
UIE,#lllllllOB ;disable the receive interrupts
RXR:
iret
;real time interrupt running in background
;bump periodic counter (60 hertz)
;one second yet?
;no rollover
;complement the second bit
;start it over again
;bump the seconds timer
;reached maximum
;no rollover
;complement the minute bit
;start it over again
;bump the minutes timer
;reached maximum
;no rollover
;complement the hour bit
; start it over again
;bump the hours timer
;reached maximum
;no rollover
; start it over again
;reset end of count
TIMERO: inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
clr
NOROLL: or
nop
nop
INTRET: iret
period
period, #60
ne,NOROLL
P2,#OOOOOOOlB
period
second
second, #60
ne,NOROLL
P2,#OOOOOOlOB
second
minute
minute, #60
ne(NOROLL
P2,#OOOOOlOOB
minute
hours
hours, #24
ne,NOROLL
hours
COCT,#OOOOOOlOB
MSG:
CR,LF, 'SuperB Uart test program.',CR,LF
'Enter up to one full line followed by return',CR,LF, '$'
CR,LF, 'Echoed back, . your line 'vas ••. ' ,CR,LF, '$'
~ISGl:
• ASCII
• ASCII
. ASCII
;and return from interrupt
.END
447
-.Zilog -- , --
Application Note
_ _
August 1987
USING THE SUPERB
SERIAL PORT WITH DMA
by Charles M. Link, II
With the increasing integration available today,
microprocessor manufacturers are incorporating new
peripherals that typically were off board in previous
products, and sometimes required a large amount of externallogic to utilize. The direct memory access function
is a good example. Zilog has incorporated a very powerful DMA in the new Super8 microcontroller. It has the
capability of linking to several on board peripherals, including the serial port, and can control data transfers to
the different memory mediums.
'
The Super8, with its on-board DMA can reduce processor overhead in data transfer tasks. It allows direct
transfer of serial input characters to either intemal
register memory (256 bytes) or external ram memory.
For example, this transfer can be set to transfer a
specific number of input characters, then interrupt the
processor. Processor program service overhead is minimal. Serial output characters can be transfered from external EPROM or ram memory, or the internal register
memory.
The required setup for the DMA transfers are much the
same as that of interrupt or polled operation. This
program example uses the DMA to interrupt upon termination of data transfers so that approopriate vectors
and routines are required. Since the program links to the
serial port, the DMA uses the serial port receive and
transmit interrupt vectors 10 and 13, respectively. Upon
completion of a receive DMA transfer, the service routine
defined by the receive vector is executed. Upon completion of the transmit DMA transfer, service routine defined
by the transmit vector is executed.
It is necessary to define the memory source/destination
by setting the appropriate state of bit 0 in the EXTERNAL
MEMORY TIMING (EMT) register. Initially, the example
program selects external memory as the source/destination. A special note: read the fine print in the technical
manual. Many hours were spent debugging the DMA
mode of operation, with the final realization that internal
rom does not qualify as external memory. Only that
memory that would be selected if the /DM line was true
would be a valid source/destination. Since this article
uses the hardware defined from the first of the series,
and uses a Z8800 with external EPROM, it will work perfectly. ROM and PIGGYBACK or prototype type parts
will not work. Neither will emulators.
This sample uses the DMA mode to transmit a few lines
of ASCII data to a console. The DMA requires a total
byte count to properly transfer the data and terminate.
Be careful to recognize that the ASCIL pseudo-op in the
Zilog assembler, or many other assemblers, is not an
easy way to generate the byte count. Warning! The
Zilog assembler generates a length for each subgroup,
e.g., "MSG" generates a separate length for each group
separated by commas, not one total length.
Initially, the DMA transfers from EPROM. The address
from which to transfer is CO and C1 as defined by the
working register pointers. It is necessary to set RPO to
CO to access the register, and it is accessed as RO and
R1 or RRO. The count for the transfer is taken from DMA
COUNT HIGH and DMA COUNT LOW. For each transfer, initialize the address and count values. Upon completion of the DMA transmit process, when the count
goes to -1, a transmit interrupt is generated. The example program disables transmit interrupts and DMA,
and returns. The main line program was polling the interrupt enable bit for completion.
Next, the DMA is set up to transfer 25 characters into the
internal register memory. One must select internal
memory in the EMT register by clearing bit O. The address for transfer requires only one byte, so that working
register I (RI), when RPO equals CO, is the aooi6ss
pointer. The DMA count must also be loaded, in this
case with 25. For demonstration purposes, the autoecho bit of the UART MODE B register is selected. This
causes any characters received to be automatically
looped back to the transmit port. Finally, the receive interrupt and DMA enable bits (BITS 0 and 1) are set to
enable and begin DMA operation. When 25 characters
have been input to the Super8, a receive interrupt will be
generated, and control will be transfered to the "RXDATI"
routine, where interrupts and DMA are disabled.
----------------448
The last routine in the example software sends another
message from EPROM to the console and then sends
the characters from the internal memory buffer that were
previously entered.
The prime consideration is to
remember to select the source/destination memory in the
EMT register.
In this DMA example, the code is simple for DMA operation. It is important to note that this example does not
fully utilize the functionality of the DMA transfer. The example purposely waits in a software loop while the DMA
transfer occurs. This prevents the supporting code from
becoming too complex to follow for an example. Normal
operation might have the UART receiving characters
.TITLE
under DMA controls and transmitting characters under
interrupt control with processing occurring somewhere in
the middle.
Sample Zilog Super 8 Serial DMA
M~de
operation
;========================================~==================
;=
j=
j=
:=
:=
j=
TITLE:
DATE:
PURPOSE:
UART3.S
JULY 17, 1986
TO DEMONSTRATE DMA
DRIVEN SERIAL PORT
COMMUNICATIONS
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II
ASSEMBLER:
i=
PROGRAMMER:
:===========================================================
• PAGE
55
;set maximum page size to 55 lines
;***********************************************************
'*
i*
GENERAL EQl!ATES
;"1<
i*
*
*
i***************************************************** ******
CR:
LF:
.equ
.equ
;carriage return
;line feed
OdH
OaH
i***************************************************** ******
"I<
REGISTER EQUATE TABLE
i*
"I<
*
i***************************************************** ******
period: .equ
0
;period timer
second: .equ
1
;seconds timer
minute: .equ
2
;minutes timer
hours:
.equ
3
;hours timer
;working register equates
MPTR:
"equ
RRO
;message pointer for external memory
,
;***********.*******************~********************* ******
*
i*
INTERRUPT VECTOR TABLE
;"1<
i*
*
'*
:***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
INTRll:
INTR12:
INTR13:
INTR14:
INTR15:
• WORD
• WORD
. WORD
• WORD
. WORD
• WORD
.WORD
. WORD
• WORD
;WORD
. WORD
. WORD
. WORD
.WORD
• WORD
. WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET'
INTRET
INTRET
RXDATI
INTRET
INTRET
TXDATI
INTRET
INTRET
;this area should always be defined
;as it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here •
~***************************************************** ******
*
*
*
i***************************************************** ******
START OF PROGRAM EXECUTION
START:
jr
STARTl
;program execution unconditionally
449
.ASCII
START1: di
sbO
ld
1d
ld
ld
ld
;begins at this location after reset
;and power up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register bank 0
EMT,#OOOOOOOlB ;external memory timing=no wait input, normal
;memory timing, no \'lait states, stack internal,
;and DMA external
PO,I/OOH
;address begins at OOOOh, set upper byte
POM, #11111111B ;select all lines as address
;enable port 0 as upper 8 bits address
PM,1/00ll0000B
H1C,#00000000B ;handshake not enabled port 0
;port 1 is defined in romless part as address/data.
;here to initialize that port
it is not necessary
ld
ld
ld
P2,1/00H
ld
ld
ld
P2BM,1I10101010B
P2CM,1/10101010B
P2DM,#10101010B
ld
ld
ld
P4,#00000000B
;clear port 4 register
P4D, #11111111B ;set all bits of P4 as inputs
P40D,1/00000000B ;active push/pull [not necessary since all
; bits are inputs
,
P3,1/00H~
P2AM,#10001010B
;port 2 outputs low
;port 3 outputs low
;p31,20,21 as output,p30 input
;it is necessary nere to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
;p32,33,22,23 as output
;p34,35,24,25 as output
;p36,37,26,27 as output
;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,1/0COH
RP1,#OC8H
SPL,#OFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;'for stack pointer. location OFFH is wasted
;as stack operation. SPH is general purpose
;storage.
;now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,1/0FFH
@SPH
SPH
nz,ZERO'
@SPH
;point to top of general purpose register
;zero it
;do it, until register set is all cleared
;zero last register
;now everything except working registers 1s cleared
;cpu and memory now initialized, set up timer for real time clocle
ld
ld
ld
sbl
ld
ld
ld
sbO
ld
SYM,#OOOOOOOOB
IPR,1/00000010B
;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,I/Ol000ll0B ;enable counter, rx and tx interrupts
;select bank 1
COTCH,1/"HB(50000)
;high byte of time constant
COTCL,1/"LB(50000)
;low byte of time constant
;12,000,000 hertz / 4 / 50,000 = 60 hertz
;12 Mhz is xtal freq, 4 is internal divider
COM,#00000100B ;p27,37 is I/O, programmed up/down, no capture
;timer mode is selected
;select bank 0
COCT,1/10100101B ;continuous, count down, load counter,
;zero count interrupt enable, enable counter
;timer is set, now lets initialize the UART for polled operation
sbl
ld
;bank 1
UMA,I/Oll10000B
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
450
ld
ld
ld
sbO
ld
ld
ld
UBGH, #AHB(00009)
;high byte of time constant
UBGL,#ALB(00009)
;10\'1 byte of time constant
UMB,#00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock I 2,
;baud rate generator is enabled, 100pback
;is disabled
;se1ect bank 0
UTC,#10001000B ;select p31 as transmit data out, 1 stop bit
;and transmit enable
UIE,#OOOOOOOOB ;no interrupts, no DMA
URC,#00000010B ;enable receive
;UART is initialized, enable interrupts for real time clock
,
ei
;enable interrupts
;because uart was just enabled, allow data line to mark for at least 1 second
WAIT:
,
cp
jr
second, ill
ne,WAIT
;wait 1 second
;display the logon message
LOGON:
ldw
call
call
MPTR, #MSG
SENDM
TXWAT
;load the address of MSG into word reg MPTR
;send the message
;wait for transmitter to complete
;logon message displayed; get response from console
;and move to upper register memory
GET:
,
di
ldw
and
sb1
ld
ld
or
sbO
or
ei
call
UIE,#OOOOOOl1B
;no interrupts while setting up for DMA
;first character receive location
;select register file for receiving character
;select bank one
;DMA count high byte
;DMA count low byte
;auto echo enable
;restore to bank zero
;receive character DMA link, interrupt enable
RXWAT
;wait for receiver to complete receiving input
MPTR,#OOSOH
EMT, #11111110B
DCH,#O
DCL,#25
UMB,#00100000B
;receive characters in buffer, restore SuperS non
di
sb1
and
sbO
or
ei
UMB,#11011111B
EMT,#OOOOOOOlB
D~~
state
;no interrupts while cleaning up
;bank 1
;disable auto echo
;restore bank 0
;select data memory for DMA transfers
;25 characters received via DMA, now display "ECHO" message
ECHO:
ldw
call
call
MPTR, ilMSG1
SENDM
TXWAT
;load the address of MSG1 in word reg MPTR
;send the message
;wait on transmitter
;message sent, now replay typed input
di
ldw
and
sb1
ld
ld
sbO
or
or
MPTR,#OOSOH
EMT, #11111110B
TXWAT
;point to beginning of buffer
;se1ect register bank for DMA transfer
;select bank 1
;DMA count high byte
;DMA count low byte
;select bank 0
;enable transmit interrupts
;transmit DMA enable
;enable interrupts
;wait on transmitter
EMT,#OOOOOOOlB
;select external data memory for DMA transfer
DCH,#O
DCL,#25
UIE,#00000100B
UTC,#OOOOOOOlB
Eli
call
di
or
ei
replay complete, loop back and do it again
jr
LOGON
451
,
; subroutines
,
;send message at MPTR for length in first byte
SENDM: ldci'
;get the character
r7,@MPTR
;count actually should be n-1 for n 'bytes
dec
r7
;no interrupts while setting up
di
EMT,#00000001B ;select external data memory for DMA transfer
or
sb1
;select bank 1
;DMA count high byte is 0
ld
DCH,#O
;move the count DMA count low byte
ld
DCL,r7
sbO
;select bank 0
UIE,#00000100B ;enable transmit interrupts
or
UTC,#00000001B ;transmit DMA enable
or
ei
ret
;transmit DMA complete
TXDATI: and
UlE, #11111011B ;disable transmit interrupts
and
UTC, #11111110B ;disable transmitDMA
;ignore it if no character to transmit
iret
;transmitter wait routine
TXWAT: tm
UIE,#00000100B ;wait until interrupts disabled
;wait if bit set
jr
nz,TXWAT
ret
;receive character available interrupt
RXDATI: and
UIE,i/11111100B ;disable the receive interrupts
iret
;receive wait routine
RXWAT: tm
UlE,i/00000001B ;wait until interrupts disabled
jr
;wait if bit still set
nz,RXWAT
ret
;real time interrupt running in background
TlMERO: inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
xor
clr
inc
cp
jr
clr
NOROLL: or
nop
nop
lNTRET: iret
period
period, #60
ne,NOROLL
P2,#00000001B
period
second
second, #60
ne,NOROLL
P2,i/00000010B
second
minute
minute,i/60
ne,NOROLL
P2,i/00000100B
minute
hours
hours, #24
ne,NOROLL
hours
COCT,#00000010B
MSG:
56
CR,LF,'Super8 Uart DMA test program.',CR,LF
'Enter 25 characters',CR,LF,'$'
MSG1:
. BYTE
• ASCII
• ASCII
• BYTE
• ASCII
.END
452
;bump periodic counter (60 hertz)
lone second yet?
;no rollover
;complement the second bit
;start it over again
;bump the seconds timer
;reached maximum
;no rollover
;complement the minute bit
;start it over again
;bump the minutes timer
;reached maximum
;no rollover
;complement the hour bit
;start it over again
;bump the hours timer
ireached maximum
;no rollover
; start it over again
; reset· end of count
land return from interrupt
34
CR,LF, 'Echoed back,. your line was ••• ',CR,LF, '$'
August 19S7
GENERATING SINE WAVES
WITH THE ZllOG SUPERS
by Charles M. Link, II
Generally digital microprocessors are thought of as only
being able to generate digital signals ...that is either on or
off. With the simple addition of a digital-to-analog converter (DAC),' more complex waveforms may be
generated. Since the advent of the microprocessor and
the DAC, many methods have been used by hardware
and software designers to generate sine waves, including some that involve precise instruction and clock cyCle
calculations. This example is different.
The Zilog SuperS microcomputer is a single chip device
requiring only a latch and EPROM to operate in its ROMLESS state. Leaving 24 1/0 lines for user configuration,
it is extremely easy to interface with peripherals, including, in this' case, the DAC- OS. The hardware in this application ex~ple is essentially the same base hardware
as the previous application articles. Since it is assumed
that the reader has access to those articles, detailed explaination of the base will not be made here. Only the
additions to the base will be explained.
The base SuperS microprocessor has ports 2, 3 and 4
available for user connection. For this example; the
DAC-OS is connected to port 4 (P4). The DAC-OS is tied,
with the least significant bit tied to P40 and the most significant bit tied to P47. The other connections to the
DAC-OS are mostly out of the test circuit description
shown in the data manuals associated with it. The DAC
requires -12 volts for proper operation. The output for
this example is tied to a simple op- amp filter with a
sharp roll off at about 3500 hertz. This type filter might
be quite suitable for telecommunications applications, but
may not be so good for many others. An oscilloscope
displays the resultant wavefOrm.
The software to operate the SuperS is in the original initialization software from eariler in this article series. Initialization is essentially the same. Port 4 must be set up
as output, with active push-pull drivers. The main consideration for this program is the software "~ample· rate.
For this example, SOOO samples per second was chosen.
Any other rate may be chosen, and the author has successfully used values up to 16000 samples per second
without timing problems. Higher base clock rates are
possible with the recently introducecd 20 megahertz
SuperS chips available. With the sample method used,
the sample rate does not vary with the different sine
wave frequencies generated.
The sample method requires a sine wave table stored in
ROM or EPROM. This example uses 256 values, although 64, 12S or more values are quite acceptable.
The BASICA program that generated the sine table is included for user modification. Once the values were
generated, they were manually typed into the program.
Using the Zilog macro assembler would have signigicantIy slowed assembling. Note that the' comments in the
BASICA program imust be removed before the PC can
execute.
The values generated by the BASICA program are
, values ranging from 01 H to OFEH. Since the DAC represents OOH as zero volts and OFFH as 5 volts, this table
will product sine outputs from almost zero to almost five
volts.
The principle of operation requires that a sixteen bit frequency increment be maintained. This increment is.
generated by the simple formula
FREQUENCY INCREMENT = (TABLESTEP X 256 X FREQUENCY) I SAMPLE
where FREQUENCY INCREMENT is a sixteen bit value
saved in an increment register, TABLESTEP is the number of values in the sine wave table, FREQUENCY is the
. desired frequency of generation in hertz, and SAMPLE is
the number of samples per second. In the example
program, this increment is stored in "FINCR".
A current offset into the sine table is maintained in the
register pair labeled "INCR".At each periodic interrupt,
FINCR must be added to INCR and saved in INCA. This
sixteen bit value remains the offset into the table. The
upper byte of the offset is used to point to the value in
the 256 byte sine table that is loaded into the DAC. In
the sample program, the value, loaded into the DAC is
generated in the previous interrupt and saved until the
first instruction of the next interrupt., This allows the interrupt to perform some other varying length transactions,
'without introducing bit jitter into the sine wave.
Changing the "FINCR" by program control causes different frequencies to be generated. In this case, the sine
wave may be turned off by disabling the counter 0 interrupt. Depending upon the number of steps in the sine
453
table and the sample frequency, very accurate sine frequencies may be generated. Calculate the actual error
by using the following formula:
[ ABS ( REAL FREQI - INTEGER FREQI) I REAL FREQI
100=% ERROR '
IX
With the addition of a filter with sharp cutoff just above
the highest desired frequency, the SuperB serves quite
well as a programmable sine wave generator. In addition
to sine waves, complex waveforms may be easily
generated by the SuperB with the addition of the low-cost
DAC. The next article in this series will describe how to
generate some of these more complex waveforms.
where REAL FREOI is the actual calculated frequency
increment, INTEGER FREOI is the nearest rounded integer of the calculated frequency increment, and the
result is the actual percent error form the desired value.
• TITLE
Super8 Example Sine Wave Generation
;============================~==============================
~=
;=
TITLE:
DATE:
PURPOSE:
:=
;=
:=
:=
HARDWARE:
:=
ASSEMBLER:
PROGRAMMER:
;=
;=
SINE.S
JUNE 17, 1986
TO DEMONSTRATE USING SUPER8
TO GENERATE HIGH QUALITY SINE
WAVES.
DAC-08 ON PORT 4
SEE DIAGRAM
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II
;===========================================================
,
• PAGE
;set maximum page size to 55 lines
55
:*********************~******************************* ******
:*
;.
;.
REGISTER 'EQUATE TABLE
*
•
; •••••••••••••••••••••••••••••••••••••••••••* ••••••••••••••••
,
INCR:
INCRH:
INCRL:
FINCR:
FINCRH:
FINCRL:
POINT:
POINTH:
POINTL:
CVAL:
,
;
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
;current increment in sine table
;high byte of current increment value
;low byte of current increment value
;increment in sine table for frequency
;high byte of frequency increment value
;low byte of frequency increment value
;pointer into sine table
;high byte of sine table pointer
;low byte of sine table painter
;current value to output to DAC-08
rrO
rO
r1
rr2
r2
r3
rr4
r4
r5
r6
...........................................................
i*
;•
GENERAL EQUATES
*
•
*
i*
:***********************************************************
XTAL:
SAMPLE:
CTVAL:
TABSTP:
FREQ:
FREQI:
;
.equ
• equ
.equ
.equ
-.equ
.equ
..........................................•................
;*
;.
;.
;
INTERRUPT VECTOR TABLE
*
•
~
.......................................................... .
INTRO
INTR1
INTR2
INTR3
INTR4
INTR5
INTR6
INTR7
454
12000000
;crystal freq in hertz
8000
;sample frequency in hertz
XTAL/4/SAMPLE
;counter load value
256
,;number of values in sine table
697
;desired sine wave frequency
(TABSTP·256·FREQ)/SAMPLE
• WORD
: WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
this area should always be defined
as it reserves the lower 32 bytes
for the interrupt table. the name
of the subroutine for each particular
interrupt seryice would'normally be
named here.
INTR8:
INTR9:
INTR10:
INTRll:
INTR12:
INTR13:
INTR14:
INTR15:
.
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
•WORD
• WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
;*~*************************************************** ******
;*
*
START OF PROGRAM EXECUTION
*
;*
;************************~**************************** ******
START:
jr
• ASCII
START1: di
.sbO
ld
ld
ld
ld
ld
;program execution unconditionally
;begins at this location after reset
land power up.
'REL 0 6/16/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register bank 0
EMT,1I00000000B ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
land DMA internal
PO,/IOOH
;address begins at OOOOh, set upper byte
POM,'II111ll111B ;select all lines as address
PM,J/OOllOOOOB
;enable porto as upper 8 bits address
H1C,1I00000000B ;handshake not enabled port 0
STARTl
;port 1 is defined in romless part as address/data.
;here to initialize that port
ld
ld
'ld
ld
ld
ld
.
ld
ld
ld
P2,/IOOH
P3,/IOOH
P2AM,1I10101010B
P2BM,1I1010l010B
P2CM,1I10101010B
P2DM,1I10101010B
it is not necessary
;port.2 outputs low
;port 3 outputs low
;p30,31,20,21 as output
;p32,33,22,23 as output
;p34,35,24,~5 as output
;p36,37,26,27 as output
P4,J/IOOOOOOOB
;set midpoint for DAC inputs
P4D,1I00000000B ;set all bits of P4 as output
P40D,1I00000000B ;active push/pull
;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,/IOCOH
RP1,/lOC8H
SPL,IIOFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
las stack operation. SPH is general purpose
; storage.
;now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,i/OFFH
@SPH
SPH
nz,ZERO
@SPH
;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register
; now everything except working registers is cleared
; cpu and memory now initialized, set up timer for real time clock
ld
ld
ld
·sbl.
ld
ld
ld
sbO
ld
SYM,/lOOOOOOOOB
IPR,i/00000010B
;disable fast interrupt response
;interrupt priority
;IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQl
IMR,i/00000100B ;enable only interrupt 2
;select bank 1
COTCH,i/AHB(CTVAL)
;high byte of time constant
COTCL,II ALB(CTVAL)
;low byte of time constant
COM,I/00000100B ;p27,37 is I/O, programmed up/down, no. capture
;timer mode is selected
;select bank 0
COCT,1I10100101B ;continuous, count down, load counter,
455
;zero count interrupt enable, enable counter
,
;timer is initialized, now lets
ldw
INCR,#l
ldw
FINCR,#FREQI
ldw
POINT,#SINTAB
ld
CVAL,#OSOH
ei
WAIT:
nop
nop
nop
nop
jr
WAIT
,
enable interrupts and wait
;start at the beginning of sine table
;load frequency of increment
;pointer points to sine table
;initial value to prevent glitch at start
;enable interrupts
;loop back
;Timer interrupt. Occurs SAMPLE times per second
;interrupt outputs value to DAC-OS and then determines value for next
; interrupt. This assures no bit jitter.
TIMERO: ld
rcf
add
adc
ld
:write new value to DAC-OS
;clear carry flag
:find next position in sine table
;by adding frequency offset to last position
;set new pointer into sine table
;upper byte ok since on boundary
CVAL,@POINT
:get value from sine table
COCT,#00000010B :reset end of count interrupt
land return from interrupt
p4,CVAL
INCRL,FINCRL
INCRH,FINCRH
POINTL,INCRH
ldc
or
INTRET: iret
:
;***********************************************************
:*
;*
*
SINE WAVE LOOKUP
*
:*
*
:***********************************************************
,
:sine table for sine wave generation using DAC-OS. Table based upon
;case of waveform with minumum amplititude = 0 volts and maximum
:amplititude = 5 volts. DAC-OS input for 0 volts = OOH
;5 volts = OFFH. Table generated using following BASICA program,
:then typed into program.
.;
,
10 CLS
20 PI=3.141593
30 FOR 1=0 TO 255
40 C=360/256
50 D=C*I
60 E=D*PI/1S0
70 F=SIN(E)
SO G=F*127
90 H=12S+G
100 J=CINT(H)
110 A$=HEX$(J)
120 PRINT A$
130 LPRINT A$
140 NEXT
150 END
:clear screen
;define PI
;256 total values
;define basic interval value
;value from zero on sine wave
:figure sine for interval from 0
:sine range should be from -127 to 127
;make result from 0 to 255
:round to nearest integer
:convert to hex
Ion screen
Ion printer
;do next inverval
:*note-remove comments, BASICA will not accept ;
SINTAB: .ORG
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
456
a~
comment delimiter
0400H
:begin sine table .on even byte boundary
OSOH,OS3H,OS6H,OS9H,OSCH,090H,093H,096H,099H,09CH,09FH,OA2H
OA5H,OASH,OABH,OAEH,OB1H,OB3H,OB6H,OB9H,OBCH,OBFH,OC1H,OC4H
OC7H,OC9H,OCCH,OCEH,OD1H,OD3H,OD5H,ODSH,ODAH,ODCH,ODEH,OEOH
OE2H,OE4H,OE6H,OESH,OEAH,OEBH,OEDH,OEFH,OFOH,OF1H,OF3H,OF4H
OF5H,OF6H,OFSH,OF9H,OFAH,OFAH,OFBH,OFCH,OFDH,OFDH,OFEH,0FEH
OFEH,OFFH,OFFH,OFFH,OFFH,OFFH,OFFH,OFFH,OFEH,OFEH,OFEH,OFDH
OFDH,OFCH,OFBH,OFAH,OFAH,OF9H,OFSH,OF6H,OF5H,OF4H,OF3H,0F1H
OFOH,OEFH,OEDH,OEBH,OEAH,OESH,OE6H,OE4H,OE2H,OEOH,ODEH,ODCH
ODAH"ODSH, OD5H, OD3H, OD1H, OCEH, OCCH, OC9H, OC7H, OC4H, OC1H, OBFH
OBCH,OB9H,OB6H,OB3H,OB1H,OAEH,OABH,OASH,OA5H,OA2H,09FH,09CH
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
• byte
099H,096H,093H;090H,08CH,089H,086H,083H,080H,07DH,07AH,077H
074H,070H,06DH,06AH,067H,064H,061H,05EH,05BH,058H,055H,052H
04FH,·04DH, 04AH, 047H, 044H, 041H, 03FH, 03CH, 039H, 037H, 034H, 032H
02FH,02DH,02BH,028H,026H,024H,022H,020H,OlEH,OlCH,OlAH,018H
016H,015H,013H,OllH,OlOH,OOFH,OODH,OOCH,OOBH,OOAH,008H,007H
006H,006H,005H,004H,003H,003H,002H,002H,002H,OOlH,OOlH,OOlH
OOlH,OOlH,OOlH,OOlH,002H,002H,002H,003H,003H,004H,005H,006H
006H,007H,008H,OOAH,OOBH,OOCH,OODH,OOFH,OlOH,OllH,013H,015H .
016H,018H,OlAH,OlCH,OlEH,020H,022H,024H,026H,028H,02BH,02DH
02FH,032H,034H,037H,039H,03CH,03FH,041H,044H,047H,04AH,04DH
04FH,052H,055H,058H,05BH,05EH,061H,064H,067H,06AH,06DH,O70H
074H,077H,07AH,07DH
• END
457
..Zilog --,. --', - ------_-Application-Note
•
1
\
~,
."ii
•
~
-
,-
>
August 1987
GENERATING DTMF TONES
WITH THE ZILOG SUPER8
by Charles M. Link, II
In the previous article, a sine wave generation example
was demonstrated. Sine waves are great, but, sometimes, more complex waveforms must be generated.
One of the most widely used complex waveforms is the
DTMF tone. The DTMF tone is used on millions of
telephones under the AT&T registered name "TOUCH
TONE". Generally, telecommunications designers purchase one of the many DTMF encoder chips and hang it
beside a microprocessor. This application article contains an example of a DTMF generation, scheme that
produces nearly as pure and probably as accurate a tone
as the extemal Chip method.
Generating sine waves requires some type of digital-toanalog converter to interface to the microprocessor. For
this application, a DAC-08 is used. This DAC-08 is tied
to port 4 of the SupeRJ. Since it is assumed that the
reader has access to the previous article, a detailed
description of the hardware will be left to that article.
Why not use the DTMF generator chip, when it might be
just as inexpensive as the DAC- 08? The answer is that
the DTMF generator chip requires an external crystal or
clock, and it might not be convenient to pick a processor
frequency that is a direct multiple of the one required by
the generator. The second and more important reason is
that the DAC-08 can be used to generate other call
progress tones such as ringback and busy, or any other
complex waveform.
Since the previous article discussed the method for
generating sine wave tones, this article will only discusshow to turn that into the DTMF tone. The DTMF tone is
actually a combination of two tones, hence, the name
DUAL TONE MULTI-FREQUENCY. ,The tones are arranged such that each row and each column has a corAn
responding single frequency tone assigned.
additional, normally unseen column, contains an eighth
tone frequency. A simple diagram below shows the'arrangement.
DTMF TONE ASSIGNMENT
697
770
852
941
458
1209
1
4
7
1336
2
5
8
o
1477 '
3
6
9
#
1633
A
B
C
D
The method used to combine the two tones into one
single complex waveform is simple: add the two i,ndividual tones together. Adding the tones together is
usually what happens when analog circuitry produces the
DTMF tODe. In fact, most of the DTMF encoder chips
usually add the tones together either internally or externally to produce; the single waveform;
Generating the two tones is no task for the Super8
microcomputer. Just set up two current table offset
values and two different frequency increments. At each
periodic interrupt the 16 bit frequency increment is added
to the current table offset producing a new current table
offset. The upper byte of each current table offset (one
for the row frequency and one for the column) is used as
a pointer into a 256 byte table. The sine values retrieved,
from the table are then added together and loaded into
the DAC-08.
Since the DAC input of OOH corresponds to an output of
o volts and the input of OFFH corresponds to an output of
5 volts, adding two values that could possibly be OFFH
presents a problem. Since two sines must add to, no
, more 5 volts, the maximum for orie single sine value
must be one half of 5 volts, or 80H. The sine table has
been adjusted so that the 2.5 volt value is mid-range.
The maximum or mimumum for the sine wave is plus or
minus 1.25 volts.
The interrupt service routine is almost exactly the same
, as the interrupt routine for the sine wave, except that two
sine waves are calculated. The final values are added
together and stored for the first instruction of the next interrupt. In order to change tones, or disable the tone
generation, additional software logic could enable or disable the interrupt,' and modify the two values "CINCR",
and "RINCR".
It is clear from the example, that ringback, busy, MF, and
other signaling tones can be easily generated without additional hardware. Increased sampling rates could be
used to generate tones of much higher frequencies and
accuracies. The accuracy, using the above m~thod and
sampling frequencies, is much less than one percent, totally suitable for telecommunications needs.
.TITLE
Super8 Example DTMF Generation
i===========================================================
;=
;=
;=
;=
TITLE:
DATE:
PURPOSE:
DTMF.S
JUNE 17, 1986
TO DEMONSTRATE USING SUPER8
TO GENERATE HIGH QUALITY DTMF
WAVES.
DAC-08 ON PORT 4
SEE DIAGRAM
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II
i=
i=
HARDWARE:
;=
i=
;=
ASSEMBLER:
PROGRAMMER:
i===========================================================
,
. PAGE
55
;set maximum page size to 55 lines
i***************************************************** ******
i*
;*
*
REGISTER EQUATE TABLE
*
*
i*
i***************************************************** *.*.*.
,
;column tone equates
CINCR: .equ
rrO
CINCRH: .equ
rO
CINCRL: .equ
r1
CFINCR: .equ
rr2
CFINCH: .equ
r2
CFINCL: .equ
r3
POINT: .equ
rr4
POINTH: .equ
r4
POINTL: .equ
r5
;row tone equates
RINCR: .equ
rr6
RINCRH: .equ
r6
RINCRL: .equ
r7
RFINCR: .equ
rrS
RFINCH: .equ
rS
RFINCL: .equ
r9
CVAL:
.equ
r10
RVAL:
.equ
r11
,
;current increment in sine table
;high byte of current increment value
;low byte of current increment value
;increment in sine table for frequency
;high byte of frequency increment value
;low byte of frequency increment value
;pointer i~to sine table
;high byte of sine table pointer
;low byte of sine table pointer
;current increment in sine table
;high byte of current increment value
; low byte of current incr,ement value
;increment in sine table for frequency
;high byte of frequency increment value
;low byte of frequency increment value
;current value to output to DAC-08
;current row value
;*********************************-******************* ~*****
;*
;*
*
GENERAL EQUATES
*
*
i*
;***********************************************************
XTAL:
.equ
12000000
;crystal freq in hertz
SAMPLE: .equ
8000
;sample frequency in hertz
CTVAL: .equ
XTAL/4/SAMPLE
;counter load value
TABSTP: .equ
256 ,
;number of values in sine table
CFREQ: .equ
1209
;desired column frequency
RFREQ: .equ
697
;desired row frequency
CFREQI: .equ
(TABSTP*256*CFREQ)/SAMPLE
RFREQI: .equ
(TABSTP*256*RFREQ)/SAMPLE
;note dtmf frequencies are 697,770,852,941,1209,1336,1477,1633
,
,
;******************************************************.** ••
;*
*
;*
;*
INTERRUPT VECTOR TABLE
~
*
*
;***********************************************************
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
. WORD
• WORD
.INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
TIMERO
INTRET
INTRET
INTRET
INTRET
;this area should always be defined
;as it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here.
459
INTR11
INTR12
INTR13
INTR14
INTR15
,
• WORD
• WORD
• WORD
•WORD
• WORD
INTRET
INTRET
INTRET
INTRET
INTRET
~***************************************************** ******
;*
:*
START OF PROGRAM EXECUTION
i*
*
, *
*
:***********************************************************
START:
jr
• ASCII
START1: di
sbO
ld
ld
ld
ld
ld
:program execution unconditionally
:begins at this location after reset
:and power up.
'REL 0 6/16/86' :jump around optional ascii string
:containing release info, copyright, etc.
:begin
:select register bank 0
EMT,#OOOOOOOOB :external memory timing=no wait input, normal
:memory timing, no wait states, stack internal,
:and DMA internal
:address begins at OOOOh, set upper byte
PO,#OOH
POM, #11111111B :select all lines as address
:enable port 0 as upper 8 bits address
PM, #00110000B
H1C,#00000000B :handshake not enabled port 0
START1
:port 1 is defined in rouiless part as address/data.
:here to initialize that port
:
it is not necessary
ld
ld
ld
ld
ld
ld
P2,#00H
P3,#00H
P2AM,-#10101010B
P2BM,#10101010B
P2CM,#10101010B
P2DM, /I10101010B
:port 2 outputs low
:port'3 outputs low
:p30,31,20,21 as output
:p32,33,22,23 as output
:p34,35,24,25 as output
:p36,37,26,27 as output
ld
ld
ld
P4,#10000000B
:set midpoint for DAC inputs
P4D,#00000000B :set all bits of P4 as output
P40D,#00000000B :active push/pull
:ba'sic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,#OCOH
RP1,/lOC8H
SPL,#OFFH
:set working register low to lower 8 bytes
:set working register high to upper 8 bytes
:set stack pointer to start at top of set two
:note here that only lower 8 bits are used
:for stack pointer. location OFFH is wasted
:as stack operation. SPH is general purpose
:storage. "
:now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,#OFFH
@SPH
SPH
nz,ZERO
@SPH
:point to top of general purpose register
:zero it
:do it until register set is all cleared,
:zero last register
: now everything except working registers is cleared
: cpu and memory now initialized, set up 'timer for real time clock
ld
ld
ld
sb1
ld
ld
ld
sbO
ld
SYM,#OOOOOOOOB
IPR,#00000010B
:disable fast interrupt response
:interrupt priority
,
:IRQ2>IRQ3>IRQ4>IRQ5>IRQ6>IRQ7>IRQO>IRQ1
IMR,'00000100B :enable only interrupt 2
:select bank 1
COTCH,#AHB(CTVAL)
:high byte of time,constant
COTCL,#ALB(CTVAL),
:low byte of time constant
COM,#00000100B :p27,37 is I/O, programmed up/down, no capture
:timer mode is selected
:select bank 0
COCT,#10100101B :continuous, countdown, load counter,
:zero count interrupt enable, enable counter
;timer is initialized, noW lets enable interrupts and wait ,
ldw
eINCR,ll
;start column at beqinninq of sine table
ldw
RINCR"l
;start ,row at beqinninq of sine table
460
this example.loads the tones for digit I I I
user software would, of course have to manipulate these registers for
proper tone control
WAIT:
ldw
ldw
ldw
ld
ei
nop
nop
nop
nop
CFINCR,#CFREQI
RFINCR,#RFREQI
POINT,#SINTAB
CVAL,#080H
;load column frequency increment
:load row frequency increment
:pointer points to sine tabl~
;initial value to prevent glitch at start
tenable interrupts
jr
WAIT
;loop back
;
;Timer interrupt. Occurs SAMPLE times per second
;interrupt outputs value to CAe-os and then determines value for next
; interrupt. This assures no bit jitter.
TlMERO: ld
rcf
add
adc
ld
ldc
add
adc
·ld
ldc
add
or
INTRET: iret
p4,CVAL
CINCRL,CFINCL
CINCRH,CFINCH
POINTL,CINCRH
CVAL,@POINT
RINCRL,RFINCL
RINCRH,RFINCH
POINTL,RINCRH
RVAL,@POINT
CVAL,RVAL
COCT,#OOOOOOIOB
:write new value to CAe-OS
;clear carry flag
;find next position in sine table
;by adding frequency offset to last position
:set new pointer into sine table
;get value from sine table
;find next position in sine table
;by adding frequencty offset to last position
:set new pointer into sine table
:get second value from sine table
:form a complex Maveform from two sine values
;reset end of count interrupt
land return from interrupt
: *** ** ** * ** * * * ** * * * * * * * * * * ~** *** * * ** * ** * * ** * * * * * *.* * *** *** * * *
*
SINE WAVE LOOKUP
*
:****** •• **.**.*.***.* •••• ******************* •• ***.****** •••
;
;sine table for DTMF generation using DAC-OB. Table based upon
lease of waveform ~onsisting of two sine waves summed to provide a single
:co~plex waveform with minumum amplititude = a volts and maximum
;amplititude = 5 volts. DAC-OB input for 0 volts = OOH
;5 volts = .OFFH. Both waves must total rio more than OFFH, therefore
;maximum for one wave must be 1/2 5 volts or OBOH.
;Table generated using following BASICA program,
;then typed into program.
10 CLS
20 PI=3.141593
30 FOR 1-0 TO 255
40 C,;,360/256
50 D=C*I
60 E-D*PI/180
70 F-SIN(E)
80.G=F*63
90 H=64+G
100 J=CINT(H)
110 A$=HI!X$(J)
120 PRINT A$
130 LPRINT A$
140 NEXT
150 END
:clear screen
;define PI
;256 total values
:define basic interval value
;value from zero on sine wave
; figure sine for interval' from 0
:sine range should be from -63 to 63
;make result from 0 to 127
:round to nearest integer
:convert to hex
ion screen
ion printer
;do next inverval
;
;*note~remove
comments, BASlCA will not accept ; as comment delimiter
SINTAB: .ORG
0400H
;begin sine table on even byte boundary'
• byte ·040H,042H,043H,045H,046H,048H,049H,04BH,04CH,04EH,04FH,051H
• byte
052H,054H,055H,057H,058H,O~AH,05BH,05CH,05EH,05FH,060H,O62H
• byte
063H,064H,066H,067H,068H,069H,06AH,06BH,06DH,06EH,06FH,O70H
• byte. 071H,072H,073H,074H,074H,075H,076H,077H,078H,078H,079H,07AH
• byte
07AH,07BH,07BH,07CH,07CH,07DH,07DH,07DH,07EH,07EH,07EH,07FH
07FH,07FH,07FH,07FH,07FH,07FH,07FH,07FH,07FH,07FH,07EH,07EH
• byte
07EH, 070H, 070H, 070H, 07CH, 07CH,'07BH, 07BH, 07AH, 07AH, 079H, 078H
• byte
• byte
078H,077H,076H,075H,074H,074H,073H,072H,071H,070H,06FH,06EH
• byte
060H,06BH,06AH,069H,068H,067H,066H,064H,063H,062H,060H,05FH
05EH,05CH,05BH,05AH,058H,057H,055H,054H,052H,051H,04FH,04EH
• byte
• byte
04CH,04BH,049H,048H,046H,045H,043H,042H,040H,03EH,030H,03BH
• byte
03AH,038H,037H,035H,034H,032H,031H,02FH,02EH,02CH,02BH,029H
028H,026H,025H,024H,022H,021H,020H,01EH,010H,OlCH,01AH,019H
• byte
018H,017H,016H,015H,013H,012H,011H,010H,00FH,00EH,00DH,OOCH
• byte
00CH,00BH,00AH,009H,008H,008H,007H,006H,006H,005H,005H,004H
• byte
• byte
004H,003H,003H,003H,002H,002H,002H,001H,001H,001H,001H,001H
• byte
001H,001H,001H,001H,001H,001H,002H,002H,002H,003H,003H,003H
004H,004H,005H,005H,006H,006H,007H,008H,008H,009H,OOAH,OOBH
• byte
00CH,00CH,00DH,00EH,00FH,010H,011H,012H,013H,015H,016H,017H
• byte
• byte
018H,019H,01AH,OlCH,01DH,OlEH,020H,021H,022H,024H,025H,026H
• byte
028H,029H,02BH,02CH,02EH,02FH,031H,032H,034H,035H,037H,038H
• byte
03AH,03BH,030H,03EH
.ENO
461
August 19S7
A SIMPLE SERIAL TO
PARALLEL CONVERTER
USING THE ZILOG SUPERS
by Charles M. Link, II
The Zilog SuperS has many on-board peripherals that
provide multiple user applications. Earlier articles have
demonstrated simple application "stubs" or short test
programs. This article and the next article demonstrate a
useful application for the SuperS. Although it
underutilizes the SuperS's power, the simple serial to
parallel converter in this application and the print buffer in
the next application demonstrate the ease at which
applications are developed with the SuperS.
Hardware for this application is fairly simple. Port 4 is
buffered and hooked to the data lines, as shown, to
interface to a centronics type printer connector. The
strobe from P25 provides the strobe (pin 1) to the printer.
The acknowledge line from the printer is inverted and
tied to P24 of the SuperS. The busy signal from the
printer is buffered and tied to P23 of the SuperS. The
design was tested on an Okidata printer and is not
guaranteed to work on all printers.
The Zilog SuperS has several features that enhance its
use as a communication controller. The interrupt or DMA
driven serial port are helpful, but the handshaking
parallel pro Is finish the job. In the serial to parallel
converter, the 256 byte internal register memory is used
as a small.circular queue.
Software is fairly straightforward. The serial port is
initialized just like it was in the application article. on the
interrupt driven serial port. Port 4 must be set-up as
outputs with active push-pull drivers. Port 2, bits 3 and 4,
are set up as input with P24 set to enable interrupts. P25
is set as output and handshake 0 is set in HOC to provide
a strobe of 16 clock periods in length .
• TITLE
Sample Zilog Super 8 Serial to Parallel Converter
;===========================================================
;=
;=
;=
TITLE:
DATE:
PURPOSE:
ASSEMBLER:
PROGRAMMER:
SERPAR.S
JULY 17, 1986
TO DEMONSTRATE INTERRUPT
DRIVEN SERIAL PORT IN A
REALISTIC APPLICATION.
THIS APPLICATION RECEIVES
SIMPLE SERIAL DATA A SENDS IT
OUT THE PARALLEL PORT TO A
PRINTER.
ZILOG ASMS8 ASSEMBLER
CHARLES M. LINK, II
. PAGE
;set maximum,page size to 55 lines
;=
;=
;=
:=
;=
:=
;=
;=
;===========================================================
55
:***********************************************************
i*
GENERAL EQUATES
; 'I<
*
*
*
:***********************************************************
:*
CR:
LF:
.equ
.equ
OdH
OaH
;carriage return
;line feed
,
:***********************************************************
i*
;*
REGISTER EQUATE TABLE
*
*
*
:*
:***********************************************************
,
;working register equates
INPNT:
.equ
R3
;input character poiriter
OUTPNT: .equ
R4
;output character pointer
462
MPTR:
.equ
ACKB:
.equ
ACKBIT: .equ
;message pointer for external memory
;byte containing ackno~lledge bit
;bit set = ~o acknowledge yet
;bit clear = not 11aiting on ackno~lledge
RR6
R5
o
,
i**************·*********·*******·******************** ******
INTERRUPT VECTOR TABLE
*"
i*
i*·*************************************************** ******
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
INTR11:
INTR12:
INTR13:
INTR14:
INTR15:
• WORD
. WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
.WORD
• WORD
• WORD
• WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
INTRET
ACKSTB
INTRET
;this area should always be defined
;as it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
; interrupt service 110uld normally be
;named here.
;receive data interrupt
;acknowle9ge strobe interrupt
i***************************************************** ******
*
i*
;"
START OF PROGRAM EXECUTION
"
;"
i***************************************************** ******
"
START:
jr
•ASCII
START1: di
sbO
ld
ld
ld
1d
1d
;program execution unconditionally
;begins at this location after reset
;and pO~ler up.
'REL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;begin
;select register ban]c 0
EMT,IIOOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no Ivait states, stack internal,
;and DMA internal
;address begins at OOOOh, set upper byte
PO,#OOH
POM, #11l1l1l1B ;select all lines as address
PM,#00110000B
;enable port 0 as upper 8 bits address
H1C,#00000000B ;handsha]ce not enabled port 0
START 1
;port 1 is defined in romless part as address/data.
;here to initialize that port
ld
ld
ld
;port 2 outputs low, except strobe bit
P2,1/00100000B
;port 3 outputs low
P3,1I00H
P2AM,1/l0001010B ;p31,20,21 as output,p30 input
;it is necessary here to configure p30 as input
;for the'receive data, and p31 as output for
;transmit data for UART
P2BM,1/l0100010B ;p32,33,22 as output, 23 as input
P2CM,1/l0101001B ;p34,35,25 as output, 24 as input, interrupt en
P2or~, jl10101010B ;p36,37,26,27 as output
ld
ld
ld
ld
P4,1I00000000B
P4D,i/00000000B
P40D,1I00000000B
HOC, #11110001B
ld
ld
ld
,
it is not necessary
;clear port 4 register
;set all bits of P4 as outputs
;active push/pull
;handshake enable for port 4, 16 clock pulse
;basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,#OCOH
RP1,#OC8H
SPL,ilOFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;set stack pointer to start at top of set two
;note here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
;as stack operation. SPH is general purpose
; storage.
;nOII clear the internal memory and stac]c area
463
ZERO:
ld
clr
dec
jr
clr
SPH, #OFFH
@SPH
SPH
nz,ZERO
@SPH
;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register
;now everything except working registers is cleared
;cpu and memory now initialized, set up timer for real time clock
ld
ld
SYM,#OOOOOOOOB
IPR, #10111111B
ld
IMR,#01010000B
;disable fast interrupt response
;interrupt priority
;IRQ6>IRQ7>IRQ5>IRQ4>IRQ3>IRQ2>IRQ1>IRQO
;rx interrupts, acknowledge strobe
timer is set, now lets initialize the UART for polled operation
sb1
ld
ld
ld
ld
sbO
ld
ld
ld
;bank 1
UMA,#01110000B
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH,#AHB(00009)
;high byte of time constant
UBGL,j/ALB(00009)
;low byte of time constant
UMB,#00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
lis disabled
;select bank 0
UTC,#10001000B ;select p31 as transmit data out, 1 stop bit
land transmit enable
UIE,#OOOOOOOlB ;receive interrupts, no DMA
URC,#00000010B ;enable receiver
UART is initialized, reset acknowledge bit and begin
WAIT:
WAIT1:
SENOM:
bitr
ld
ei
ldw
call
ld
ld
call
jr
ACKB,#ACKBIT
;reset acknowldege bit if set
P2BIP,#00000001B
;reset interrupt input flip-flop
;enable interrupts
;point
to
message
MPTR,#MSG
;send the message
SENOM
;set input pointer to register 0
INPNT, #0
;set output pointer to register 0
OUTPNT,#O
;send any characters in buffer
SNOBUF
;loop back
WAIT1
tm
jr
btjrt
P2,#00001000B
;printer busy
nZ,SENOM
;wait for printer unbusy
SENOM,ACKB,#ACKBIT
;see if the acknowledge has occurred
;from possible last byte
ACKB, #ACKBIT
;set acknowledge bit before writing to output
rO,@MPTR
;get the character
P4, rO
; send to printer
;allow 18 clocks for strobe
bits
ldci
ld
nop
nop
nop
cp
jr
ret
SNOBUF: cp
jr
ret
SC1:
tm
jr
btjrt
di
bit;s
ld
tm
464
rO,#'$'
ne,SENOM
;last character?
;loop back for next
;compare inpointer to outpointer
;send character if any to send
;otherwise return
P2,#00001000B
;printer busy?
nz,SC1
;if so, wait until it is not busy
SC1,ACKB,#ACKBIT
'
;see if acknowledge has occurred
;from possible last byte
INPNT,OUTPNT
ne,SC1
ACKB, #ACKBIT
P4,@OUTPNT
P2, .#OOOOOOOlB
;set acknowledge bit before writing to output
;send the character
HON:
jr
ld
xor
cp
jr
and
nop
inc
ei
ret
z,HON
rO,OUTPNT
rO,UOOOOOOOB
INPNT,rO
ne,HON
P2,1/11111110B
iif host is on
iget the output pointer
iadd 128 to it
iturn host back on when 128 bytes left in buf
iotherwise keep sending
ihost back on
OUTPNT
ibump pointer
ito make sure pointer, not changed
i
isend character in rO
SENDC: tm
UTC,/l00000010B itransmit buffer empty yet
jr
z,SENDC
iif not, wait unt~l it is
ld
UIO,rO
iload the character into the transmitter
ret
ireceivecharacter available interrupt
RXDATI: ld
rO,UIO
iget input from console
and
rO,1/7fH
iremove upper parity bit
call
SENDC
iecho to console
ld
@INPNT,rO
isave the character
inc
INPNT
ibump input pointer
cp
INPNT,OUTPNT
ihas the input made a complete loop?
jr
ne,RXIT
ireceive character buffer full, stop sending device
or
INTRET:
RXIT:
iret
P2,1/0000000lB
iraise DTR to stop host sending
ACKSTB: tm
bitr
P2,i/00010000B
ACKB,I/ACKBIT
iis line low or high now
ireset acknowledge bit in register
ACKSl:
tm
jr
ld
iret
P2,#00010000B
itest ack bit
Z,ACKSl
iwait here till end of strobe
P2BIP,1/00000001B
ireset p24 interrupt pending register
iand return
MSG:
• ASCII
• ASCII
CR,LF,'Super8 serial/parallel test program.',CR,LF
'Second line test data',CR,LF,'$'
• END
.TITLE
Sample zilog Super 8 Serial to Parallel Converter with XON/XOFF
;===========================================================
;=
;=
;=
TITLE:
DATE:
PURPOSE:
;=
i=
;=,
;=
i=
;=
;=
;=
;=
;=
ASSEMBLER:
PROGRAMMER:
SERPARl.S
JULY 17, 1986
TO DEMONSTRATE INTERRUPT
DRIVEN SERIAL PORT IN A
REALISTIC APPLICATION.
THIS APPLICATION RECEIVES
SIMPLE SERIAL DATA A SENDS IT
OUT THE PARALLEL PORT TO A
PRINTER. FLOW CONTROL IS BY
XON/XOFF COMMANDS ON THE BACK
CHANNEL TO THE HOST
ZILOG ASMS8 ASSEMBLER
CHARLES .M. LINK, II
;===========================================================
• PAGE
55
iset maximum page size to 55 lines
i***********************************************************
GENERAL EQUATES
;*
*
**
i***********************************************************
CR:
LF:
.equ
.equ
OdH
OaH
icarriage return
i11ne feed
465
XON:
XOFF:
.equ
.equ
;control-Q or DC1
;control-S or DC3
11H
13H
:**~********************************~***************** ******
;*
..
REGISTER EQUATE TABLE
*
*
:***********************************************************
;working register equates
INPNT: .equ
R3
;input character pointer
OUTPNT: .equ
R4
;output character pointer
-MPTR:
.equ
RR6
;message pointer for external memory
ACKB:
.equ
R5
;byte containing acknowledge bit
ACKBIT: .equ
0
;bit set = no acknowledge yet
;bit clear = not waiting on acknowledge
XBIT:
.equ
1
;XOFF send to host
;***********************************************************
;*
*
*
INTERRUPT VECTOR TABLE
; +.
;*
..
i***************************************************** ******
INTRO:
INTR1:
INTR2:
INTR3:
INTR4:
INTR5:
INTR6:
INTR7:
INTR8:
INTR9:
INTR10:
INTR11:
INTR12:
INTR13:
INTR14:
INTR15:
• WORD
• WORD
. WORD
• WORD
• WORD
•WORD
• WORD
. WORD
• WORD
. WORD
• WORD
• WORD
• WORD
. WORD
• WORD
• WORD
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
INTRET
RXDATI
INTRET
INTRET
INTRET
ACKSTB
INTRET
;this area should always be defined
las it reserves the lower 32 bytes
;for the interrupt table. the name
;of the subroutine for each particular
;interrupt service would normally be
;named here .
;receive data interrupt
;acknowledge strobe interrupt
,
; *** * *** *** .-* * * * .. * * ** .. * .. 'It * ...... * ** .. '* * .. * *** ~ *.. ** .. ** .. '* '* .... 'It .... * *....
:*
;*
START OF PROGRAM EXECUTION
:*
'*
*
..
;~**************************************************** ******
START:
di
jr
• ASCII
START1: sbO
ld
ld
ld
ld
ld
;for emulation if nothing else
;program execution unconditionally
;begins at this location after reset
land power up.
'RBL 0 7/17/86' ;jump around optional ascii string
;containing release info, copyright, etc.
;select register bank 0
EMT,#OOOOOOOOB ;external memory timing=no wait input, normal
;memory timing, no wait states, stack internal,
land DMA internal
;address begins at OOOOh, set upper byte
PO,i/OOH
POM, #l1l1l1l1B ;select all lines as address
PM,#00110000B
;enable port 0 as upper 8 bits address
H1C,#OOOOOOOOB ;handshake not enabled port 0
START 1
;port 1 is defined in romless part as address/data.
;here to initialize that port
ld
ld
ld
466
it is not necessary
ld
ld
ld
P2,i/OO100000B
;port 2 outputs low, except strobe bit
;port 3 outputs low
P3,i/OOH
P2AM,#10001010B ;p31,20,21 as output,p30 input
lit is necessary here to configure p30 as input
;for the receive data, and p31 as output for
;transmit data for UART
P2BM,#10100010B ;p32,33,22 as output, 23 as input
P2CM,#10101001B ;p34,35,25 as output, 24 as input, interrupt en
P2DM,#10101010B ;p36,37,26,27 as output
ld
ld
P4,#OOOOOOOOB
P4D,#OOOOOOOOB
;clear port 4 register
;set all bits of P4 as outputs
ld
ld
P40D,i/00000000B ;active push/pull
HOC,i/1111000IB ;handshake enable for port 4, 16 clock pulse
basic Super 8 I/O is initialized, now internal registers
ld
ld
ld
RPO,i/OCOH
RP1,I/OC8H
SPL,i/OFFH
;set working register low to lower 8 bytes
;set working register high to upper 8 bytes
;'set stack pointer to start at top of set two
;note,here that only lower 8 bits are used
;for stack pointer. location OFFH is wasted
;as stack operation. SPH is general purpose
; storage.
;now clear the internal memory and stack area
ZERO:
ld
clr
dec
jr
clr
SPH,i/OFFH
@SPH
SPH
nZ,ZERO
@SPH
;point to top of general purpose register
;zero it
;do it until register set is all cleared
;zero last register
now everything except working registers is cleared
cpu and memory now initialized, set up timer for real time clock
ld
ld
SYM,ilOOOOOOOOB
IPR, #10111111B
ld
IMR,i/01010000B
;disable fast interrupt response
;interrupt priority
;IRQ6>IRQ7>IRQ5>IRQ4>IRQ3>IRQ2>IRQ1>IRQO
;rx interrupts, acknowledge strobe
timer is set, now lets initialize the UART for polled operation
sb1
ld
ld
ld
ld
sbO
ld
ld
ld
;bank 1
UMA,il01110000B
;time constant = (12,000,000/4/16/9600/2)-1=
;8.76 rounded to 9.
;note that a 12 Mhz does not make a very
;accurate baud rate source. error is large
UBGH,II~HB(00009)
;high byte of time constant
UBGL, #~LB(00009)
;low byte of time constant
UMB,i/00011110B ;p21=p21data,auto-echo is off, transmit and
;receive clock is baud rate generator output,
;baud rate generator input is system clock / 2,
;baud rate generator is enabled, loopback
; is disabled
'
;select bank 0
'UTC,i/1000l000B ;select p31 as transmit data out, 1 stop bit
land transmit enable
UIE,i/00000001B ;receive interrupts, no DMA
URC,i/00000010B ;enable receiver
UART is initialized, reset acknowledge bit and begin
WAIT:
WAITl:
SENDM:
bitr
bitr
ld
ei
ldw
call
ld
ld
call
jr
ACKB,i/ACKBIT
;reset acknowldege bit if set
ACKB,i/XBIT
;reset XON/XOFF bit
P2BIP,i/00000001B
;reset interrupt input flip-flop
;enable interrupts
MPTR,i/MSG
;point to message
SENDM
;send the message
INPNT,i/O
;set input pointer to register 0
OUTPNT,i/O
;set output pointer to register 0
SNDBUF
;send any characters in buffer
WAITl
;loop back
tm
jr
btjrt
P2,i/00001000B
;printer busy
nZ,SENDM
;wait for printer unbusy
SENDM,ACKB,/IACKBIT
;see if the acknowledge has occurred
;from possible last byte
ACKB,#ACKBIT
;set acknowledge bit before writing to output
rO,@MPTR
;get the character
P4,rO
;send to printer
;allow 18 clocks for strobe
bits
ldci
ld
nop
nop
nop
cp
jr
ret
rO,/I'$'
ne,SENDM
;last character?
;loop back for next
467
,
;timer is initialized, now lets enable interrupts and wait
;start column at beginning of sine table
ldw
CINCR, #1
;start row at beginning of sine table
ldw
RINCR, #1
,
;this exa~ple loads the tones for digit '1'
;user software would, of course have to manipulate these registers for
;proper tone control
WAIT:
,
ldw
ldw
ldw
ld
ei
nop
nop
nop
nop
jr
CFINCR,#CFREQI
RFINCR,#RFREQI
POINT,I/SINTAB
CVAL,I/OSOH
;load column frequency increment
;load row frequency increment
;pointer points to sine table
;initial value to prevent glitch at start
;enable interrupts
WAIT
;loop back
;Timer interrupt. Occurs SAMPLE times per second
;interrupt outputs value to DAC-OS and then determines value for next
; interrupt. This assures no bit jitter.'
TIMERO: ld
rcf
add
adc
ld
ldc
add
adc
ld
ldc
add
or
INTRET: iret
p4,CVAL
;write new value to DAC-OS
;clear carry flag
CINCRL,CFINCL
;find next position in sine table
CINCRH,CFINCH
;by adding frequency offset to last position
POINTL,CINCRH
;set new pointer into sine table
;getvalue from sine table
CVAL,@POINT
RINCRL,RFINCL
;find next position in sine table
RINCRH,RFINCH
;by adding frequencty offset to last position
POINTL,RINCRH
;set new pointer into sine table
RVAL,@POINT
;get second value from sine table
CVAL,RVAL
;form a complex waveform from two sine values
COCT,#00000010B ;reset end of count interrupt
land return from interrupt
;***********************************************************
i*
*
SINE WAVE LOOKUP
;*
*
;*
*
i***************************************************** ******
;sine table for DTMF generation using DAC-OS. Table based upon
;case of waveform consisting of two sine waves summed to provide a single
;complex waveform with minumum amplititude = 0 volts and maximum
;amplititude = 5 volts. DAC-OS input for 0 volts = OOH
;5 volts = OFFH. Both waves must total no more than OFFH, therefore
;maximum for one wave must be 1/2 5 volts or .OSOH.
;Tablegenerated using following BASICA program,
;then typed into program.
10 CLS
20 PI=3.141593
30 FOR 1=0 TO 255
40 C=360/256
50 D=C*I
60 E=D*PI/1S0
70 F=SIN(E)
SO G=F*63
90 H=64+G
100 J=CINT(H)
110 A$=HEX${J)
120 PRINT A$
130 LPRINT A$
140 NEXT
150 END
;clear screen
;define PI
;256 total values
;define basic interval value
;value from zero on sine wave
;figure sine for interval from 0
;sine range should be from -63 to 63
;make result from 0 to 127
;round to nearest integer
;convert to hex
ion screen
ion printer
;do next inverval
,
;*note-remove comments, BASICA will not accept ; as comment delimiter
SINTAB: .ORG
• byte
• byte
• byte
• byte
• byte
468
0400H
;begin sine table on even byte boundary
040H,042H,043H,045H,046H,04SH,049H,04BH,04CH,04EH,04FH,051H
052H,054H,055H,057H,058H,05AH,05BH,05CH,05EH,05FH,060H,062H
063H,064H,066H,067H,06SH,069H,06AH,06BH,06DH,06EH,06FH,070H
071H,072H,073H,074H,074H,075H,076H,077H,07SH,07SH,079H,07AH
07AH,07BH,07BH,07CH,07CH,07DH,07DH,07DH,07EH,07EH,07EH,07FH
SNDBUF: cp
jr
ret
SCI:
tm
jr
btjrt
HON:
di
bits
ld
btjrf
ld
xor
cp
jr
ld
call
bitr
nop
inc
ei
ret
INPNT,OUTPNT
ne,SCl
compare inpointer to outpointer
send character if any to send
otherwise return
P2,#OOOOlOOOB
printer busy?
nz,SCl
if so, wait until it is not busy
SCl,ACKB,I/ACKBIT
;see if acknowledge has occurred
;from possible last byte
ACKB,#ACKBIT
P4,@OUTPNT
HON,ACKB,#XBIT
rO,OUTPNT
rO,1I10000000B
INPNT,rO
ne,HoN
rO,XoN
SENDC
ACKB,#XBIT
OUTPNT
;set acknowledge bit before .writing to output
;send the character
;host is still sending
;get the output pointer
;add 128 to it
;turn host back on when 128 bytes left in buf
;otherwise keep sending ,
;send XON to host to start it sending again
;reset XOFF bit
;bump pointer
Ito make sure pointer not changed
;send character in rO
SENDC: tm
UTC,I/OOOOOOlOB ;transmit buffer empty yet
jr
z,SENDC
;if not, wait until it is
ld
UIO,rO
;load the character into the transmitter
ret
;receive character available interrupt
RXDATI: ld
rO,UIO
;get input from console
and
rO, #7fH
;remove upper parity bit
call
SENDC
;echo to console
ld
@INPNT,rO
;save the character
inc
INPNT
;bump input pointer
ld
rO,INPNT
;get the input pointer
add
rO,#5
;allow 5 characters after XOFF
cp
rO,OUTPNT
;has the input made a complete loop?
jr
ne,RXIT
,
;receive character buffer full, stop sending device
ld
call
bits
rO,#XOFF
SENDC
ACKB,#XBIT
;send XOFF to host
;send it
;set the XOFF bit
ACKSTB: tm
bitr
P2,I/OOOlOOOOB
ACKB,I/ACKBIT
lis line low or high now
;reset acknowledge bit in register
ACKSl:
tm
jr
ld
iret
P2,I/OOOlOOOOB
;test ack bit
z,ACKSI
;wait here till end of strobe
P2BIP,#OOOOOOOlB
;reset p24 interrupt pending register
land return
MSG:
.ASCII
.ASCII
CR,LF,'Super8 serial/parallel test program. ' ,CR,LF
'Second line test data',CR,LF,'$'
INTRET:
RXIT:
iret
.END
469
_
~
J_
~
~
., ,,~.,~~~ _.,... ,'~ .. _.,
~~Zil~g"
';.
4\~
~"I;/'~'~ "~,
'Technical Manual
'
SuperS™ Microcomputer
470
'
Contents
Chapter 1. SuperB Overvier1
1.1
1.2
1.3
1.4'
1.5
Introduction
Features
Basic Microcomputers
Protopack Microcomputers
ROMless Microcomputers
465
465
465
465
465
Chapter 2. Architectural Overviet1
2.1
2.2
2.3
2.4
2.5
2.6
Introduction
Address Spaces
Register File •
466
466
467
2.3.1
'2.3.2
467
467
Register Pointer
Instruction Pointer
Instruction Set •
467
2.4.1
2.4.2
467
467
Addressing Modes
Data Types
I/O Operations
468
2.5.1
2.5.2
468
468
Interrupts
On-Chip Peripherals
Oscillator
468
Chapter 3. Address Spaces
3.1
3.2
3.3
3.4
3.5
3.6
Introduction
• • • • •
CPU Register File • •
• • • • •
System Registers and Mode and Control Registers
Program and Data Memory •
CPU and User Stacks
Instruction Pointer (IP)
469
469
472
472
474
475
4
Chapter 4. Addressing 1-1odas
4.1 Introduction • • • • • • • • • •
4.2 Register Addressing (R) • • • • •
4.3 Indirect Register Addressing (IR)
4.4 Indexed Addressing (IA) •
4.5 Direct Addressing (DA)
4.6 Indirect Addressing (IA)
4.7 Relative Addressing (RA)
4.8 Immediate Addressing (1M)
476
476
478
478
480
480
480
481
Chapter 5. Instruction Set
5.1 Functional Summary
5.2 Processor Flags • •
5
482
482
471
Contents (Continued)
5.3 Condition Codes • • • • • • •
5.4 Notation and Binary Encoding
5.5
485
485
5.4.1 Notational Shorthand
5.4.2 Flag Settings
487
487
Instruction Descriptions and Formats
489
Chapter 6. Interrupts
6.1
6
Introduction
543
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
543
543
544
546
546
Sources
Vectors
Levels.
Enables
The Interrupt Routine
6.2 Fast Interrupt Processing ••
6.3 Clearing the Interrupt Source
6.4 Interrupt Control Registers •
6.5
548
548
549
549
549
Interrupts and the DMA Channel
549
Chapter 8.
472
•••••••••••••
7
Reset and Clock
7.1 Reset
7.2 Clock
7.3 Test Mode
8.1
8.2
8.3
8.4
8.5
B.6
8.7
547
547
547
6.4.1 System Mode Register
6.4.2 Interrupt Request Register •
6.4.3 Interrupt Mask Register
6.4.4 Interrupt Priority Register
6.4.5 Fast Interrupt Status Bit (FIS of Flags Register)
Chapter 7.
5
550
556
556
8
I/O Ports
Introduction
General Structure
Port 0
Port 1
Ports 2 and 3
Port 4
Port Mode and Control Registers
557
557
557
557
558
559
559
8.7.1 Port Mode Register •••
8.7.2 Port 0 Mode Register ••
B.7.3 Port 2/3 Mode Registers
559
560
560
.,
8.7.4
8.7.5
B.7.6
B.B
9.2
561
B.B.1
B.B.2
563
563
Pin Descriptions
Handshake Control Registers
565
9.1.1
9.1.2
9.1.3
Bi-Value Mode
Capture
External Gate and Trigger
566
566
566
Counter/Timer Control and Mode Registers
567
9.2.1
9.2.2
9.2.3
9.2.4
567
568
570
570
Counter/Timer Control Registers
Counter/Timer Mode Registers
Time Constant Register
Capture Register • • • • ••
UART
Introduction
Transmitter •
Receiver
Wake-Up Feature
Auto-Echo/Loopback
Polled Operation
Baud-Rate Generator
UART Interface Pins
UART Control/Mode and Status Registers
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
10.9.7
10.9.B
10.9.9
Olapter 11.
10
.. .'
UART Data Register (UIOT & UIOR)
Wake-Up Match Register (WUMCH) •
Wake-Up Mask Register (WUt1SK)
UART Receive Control Register (URC)
UART Interrupt Enable Register (UIE)
UART Mode A Register (UMA) ••
UART Transmit Control Register (UTC)
UART Mode B Register (UMB) ••
UART Baud-Rate Generator Time Constant Register (UBG)
571
571
571
572
574
575
575
576
576
576
576
576
576
576
578
579
580
581
11
DHA Olannel
11.1 Introduction
11.2 DMA Control Registers ••
11.3'DMA and the UART Register
11.4 DMA and the UART Transmitter
8
9
Counter/Timers
Introduction
Olspter 10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.B
10.9
561
561
561
Handshaking Channels
Olapter 9.
9.1
Port 2/3 Interrupt Pending Registers
Port 4 Direction Register
Port 4 Open-Drain Register
582
582
583
583
473
Contents (Continued)
11.5 DMA and Handshake Channel
o•
11.5.1 DMA Write (Input Handshake 0)
11.5.2 DMA Read (Output Handshake 0).
11.5.2.1 Fully Interlocked Mode
11.5.2.2 Strobed Mode
Olapter 12.
12.1
12.2
12.3
12.4
12.5
12.6
584
584
12
Introduction
Pin Descriptions
Configuring for External Memory
External Stacks
Data Memory •
8us Operation.
590
590
591
592
592
592
12.6.1 Address Strobe (AS)
12.6.2 Data Strobe (DS)
12.6.3 External Memory Operations
593
593
593
12.7.1 Software Pro·grammable Wait States
12.7.2 Slow Memory Timing
12.7.3 Hardware Wait States
12.8 Instruction Timing
\ Glossary.
11
583
584
External Interface
12.7 Extended 8us Timing
474
583
593
593
594
594
594
597
ChapteO" 1
Su~eD'8
1.1
INTRODUCTION
The SuperB family consists of basic microcomputers, protopack emulators, and ROM less microcomputers. The various fami Iy members differ in the
amount of on-chip ROM and the physical packaging.
All of the SuperS family members offer a fullduplex universal asynchronous receiver/transmitter
(uART) with an on-r.hip baud-rate generator, t.wo
16-bit programmable counter/timers,
a direct
memory access (DMA) controller, and an on-chip
osci llator.
1.2 fEATURES
Oven/Hew
1.3 BASIC MICROCm.lPUTERS
These parts are the core of the SuperB family of
products.
They have various amounts of maskprogrammable on-chip ROM, are suitable fur high
volume applications, and require a single +5 Vdc
power supply.
1.4 PROTOPACK MICROCOMPUTERS
These parts function as emulators for the basic
microcomputer versions. They use the same package
and pin-out as the basic microcompute r but a Iso
have a 2B-pin "piggy back" socket on the top into
which a ROM or EPROM can be installed, to replace
the on-chip ROM of the basic microcomputer.
SuperS microprocessor features include:
This package permits the protopack to be used in
prototype and final PC boards while sti II permitting user program development.
I1hen a final
program is deve loped, it can be mask-programmed
into the production microcomputer device, directly
replacing the emulator.
The protopack parts are
also useful in situations where the cost of maskprogramming is prohibitive or where program flexibility is desired.
o
325 byte-wide registers, including 272 generalpurpose registers and 53 mode and control
registers
o
Full-duplex UART with special features
II
Up to 32 bit-programmab Ie
and
S byteprogrammable I/O lines, with 2 handshake channels
o
Addressing of up to 128K byes of memory
1.5
o
An interrupt structure that supports:
The ROMless microcomputers are simi lar to the
basic microcomputer parts, but have no interns I
ROM. Port 1 is dedicated as an B-bit address/data
bus and POO-P04 are dedicated address ,lines. Up to
64K bytes of external memory can be addressed by
configuring Port 0 as address bits.
The address
capability can be doubled to 12BK bytes by
programming P35 of Port 3 as the Data Memory
select signal TIM. The two states of this signal
can be used with the 16-bit address bus to address
two separate banks of external memory, each with
up to 64K bytes.
"
"
o
o
27 interrupt sources
16 interrupt vectors (2 reserved for future
versions)
B interrupt levels
Servicing in 6 CPU clock cycles
"
Two Register 'Pointers that allow use of short
and fast instructions to access register groups
within 600 ns.
o
An instruction set that includes multiply and
divide instructions, Boolean and BCD operations
o
Additional instructions that support threadedcode languages, such as Forth
ROi'lLESS
MICROCO:~PUTERS
.Chapter 2
Architectural Overview
2.1
INTROOUCTION
The SuperB is a versatile single-chip microcomputer that can be programmed for many different
memory and I/O configurations. This flexibility
has been achieved by merging a mult iplexed
address/data bus with several I/O-oriented ports.
This provides the user with large amounts of
external memory while maintaining many I/O lines.
Figure 2-1 shows the SuperB block diagram.
2.2
•
•
•
Program memory. (internal and external)
Data memory (external)
Register file (internal)
A maximum of 64K bytes of program memory is
directly addressable. When present, internal
program memory normally consists of maskprogrammed ROM.
The data memory space is 64K
bytes in size.
The ease of interfacing with external memory is
enhanced with options for programmable wait states
and half-speed memory timing, as we 11- as an
optional external wait input.
ADDRESS SPACES
To provide for both I/O and memory intensive
applications, the SuperB supports three basic
address spaces:
110
(BIT PROGRAMMABLE)
XTAL
AS
os
PORT 4
UART
I/O
(BIT PROGRAMMABLE)
OR CONTROL
ADDRESS OR I/O
(BIT PROGRAMMABLE)
ADDRESS/DATA OR I/O
(BYTE PROGRAMMABLE)
Z-BUS WHEN USED AS
ADDRESS/DATA BUS
Figure 2-1_ Functional Block Diagram
476
Architectural Overview
2.3 REGISTER FILE
2.4.1
The SuperB architecture centers around an internal
register file composed of 325 registers.
All
registers are eight bits wide.
Of the 272
general-purpose registers, 20B can be used as an
accumulator", address pointer, index regi'ster, dsta
register, or stack register. The 64 remaining
general-purpose registers sre limited to Indirect
or Indexed addressing mode functions such as
stacks, data buffers, and look-up tables. Fiftythree registers are dedicated to special control
and status operations.
The addressing modes of
Processing Unit (CPU) are:
2.3.1
Register Pointer
The register file is logically div ided into 32
working register groups of B registers each when
using 4-bit register addressing. Two groups may
be active at anyone time and the two Register
Pointers (RPO and RP1) contain the base addresses
of these two working register groups. This allows
fast context switching and shorter instruction
formats.
•
•
•
•
•
•
•
Addressing ItJdes
the
SuperB
Central
Register (R)
Indirect Register (IR)
Indirect Address (IA)
Immediate (1M)
Direct Address (DA)
Indexed (X)
Relative Address (RA)
Register,
Indirect Register,
and
Immediate
addressing modes are available for Load, Arithmetic, Logical, Shift, Rotate, and Stack instructions. Conditional jumps support both the Direct
and Relative addressing modes, while Jump and Call
instructions support the Direct, Indirect, and
Indirect Register addressing modes.
Onl y Load
instructions support Indexed addressing.
2.4.2 Data Types
The SuperB CPU supports operations on bits, bytes,
BCD digits, and 2-byte words.
2.3.2
Instruction Pointer
The SuperB hardware includes features that facilitate the implementation of threaded-code languages
such as Forth.
These include a special 16-bit
register called the Instruction Pointer (Ip) and
three special CPU instructions called NEXT, ENTER,
and EX IT. The IP can also be used to support the
fast interrupt processing mode.
2.4 INSTRUCTION SET
The CPU has an instruction set designed for its
large register file. This includes a full complement of B-bit arithmetic and logical operations,
including multiply and divide. Binary-Coded
Decimal (BCD) operations are supported using a
decimal adjustment of binary values. Incrementing
and decrementing 16-bit quantities for addresses
and counters are also supported.
Extensive bit
manipulation', including Rotate and Shift instructions, round out the data manipulation capabilities of the SuperB. No special I/O instructions
are necessary since I/O is mapped, into the register file.
Bits in the register file can be set, cleared,
complemented, and tested. Bits within a byte are
numbered from 0 to 7; bit 0 is the least significant (right-most) bit.
Bytes in the register file can be operated on by
Arithmetic, Logical, Shift and Rotate, and Load
instructions. Bytes in memory can be operated on
only by load or stack instructions.
Manipulation of BCD digits, packed two to a byte,
is accomplished by a Decimal Adjust instruction
and a Swap instruction. Decimsl Adjust is used
after either a binary addition or subtraction on
BCD digits.
Words in the register file can be loaded, incremented, and decremented with the 16-bit Load Word,
Increment Word, and Decrement Word instructions.
477
Architectural Overview
2.5
I/o OPERATIONS
2.5.2
On-Chip Peripherals
The Super8 has 1/0 lines grouped into five ports
of eight lines each. Ports are configurable as
input, output, or bidirectional.
Under software
control, the ports can provide timing, status
signals, address outputs, and 1/0 ports with or
without
handshaking.
Multiprocessor
system
configurations are also supported.
To help cope with real-time problems such as
counting/timing, the SuperB contains two counter/
timers with a large number of user selectable
modes.
It also contains an on-Chip universal
asynchronous receiver/transmitter (UARf) which has
its own built-in baud-rate generator that can be
used as a counter when not being used to generate
baud rates.
2.5.1
A DMA channel is provided that allows high-speed
data transfers between on-Chip peripherals and the
register file or external memory.
Interrupts
r/o operations can be interrupt-driven or polled.
The SuperB supports 16 vectored interrupts on
eight different levels from 27 interrupt sources.
Each level can be masked and prioritized.
Optiona 1 high-speed interrupt processing can be
used on anyone of the levels for minimum latency.
478
2.6
OSCILLATOR
In addition to these features, the SuperB offers
an on-chip oscillator requiring only an external
crystal for operation.
Chapter 3
Address Spaces
3.1 INTRODUCTION
A total of 325 registers is accessible with 192
registers (OOH-BFH) accessible in all addressing modes.
These can be used as accumulators,
working registers, data buffers, internal stack,
and so forth. It is possible to set up a 256-byte
data buffer and still have 16 registers remaining
as accumulators and working registers.
The SuperB microprocessor supports the following
address spaces:
II
e
II
CPU register file
Program memory
Data memory
Figures 3-1 and 3-2 show layouts of the register
file address space. The upper 64 bytes- of the
address space (COH-FFH) contain. two sets of
registers. The first set can be accessed only by
the Register addressing mode; the second set can
be accessed by the Indirect Register and Indexed
addressing modes, stack operations, and DMA
accesses. The registers in the secdnd set are
usable as data buffers or as an internal stack
area.
3.2 CPU REGISTER fILE
Registers within the SuperB CPU's internal register file are identified with an B-bit address,
yielding 256 possible register addresses. However,
the upper 64 addresses are used more than once, as
described below. A total of 325 registers is
available, including 272 general-purpose registers
and 53 special control and status registers. Two
of these registers are Register Pointers.
SET ONE
I
r-----------.
SET TWO
FFH
.1- BANK1
CONT~g~~:~I~TERS
.(REGISTER ADDRESSING ONLY)
1--1- BANKO
--
DATA REGISTERS
(INDIRECT REGISTER, INDEXED,
STACKORDMA
ACCESS ONLY)
SYSTEM REGISTERS:
STACK, FLAGS, PORTS, ETC.
(REGISTER ADDRESSINGONLY)
WORKING REGISTERS
(WORKING REGISTER
ADDRESSING ONLY)
BFH
,
COHL-_____________-J
r----------,
DATA REGISTERS
(ALL ADDRESSING MODES)
OOH
~
_________
256
BYTES
192
BYTES
~
Figure 3-1. SuperB Registers
8257-001
479
Address Spaces
ADDRESS
SPECIAL PURPOSE
REGISTERS
GENERAL PURPOSE REGISTERS
~-r"'----''''-'''''----'
BANKO
BANK1
: ==== ==== }:;::,~
OF
~
07
06
1==;.==1 }SYSTEM
;;;I ====·~:'~·IL.S--t~~__
-_--+_=_=_=_=--If-___
I
I
RP1
RPO
I}
I
REGISTER
...J
'
POINTERS
Each Register Pointer (RP) can Independently point 10 any of 32
a-byte blocks of set one. The block selected by RPO is accessed
in address space eO-C7, while the block selected by RP1 is
accessed in address space C8-CF. Memory space from CO-CF
can only be accessed if pointed to by the RPs.
08
07
---------------------
00-:--------:--------;
REGISTER ADDRESSING ONLY
~~
ALL
ADDRESSING
MODES
1
. . .------------_r--------------'
~
MAY BE POINTED TO BY REGISTER POINTER
INDIRECT REGISTER,
INDEXED,
STACK, OR
DMAMODES
Figure 3-2. SuperS Register File Address Spaces
The first set consists of three subsets of registers.
The bottom sixteen registers (COH-CFH)
are available for use as accumulators or working
registers.
The middle sixteen registers (DOHDF H) are used for system registers--Stack
Pointer, Flag register, I/O ports, and so forth.
The upper 32 bytes (EOH-FFH) consist of two
banks of registers. Each bank is selected by a
bit located in the Flag register called the Bank
Address bit.
These two banks, a total of 64
bytes, are used for Mode and Control registers.
Only 38 of these 64 bytes are currently used. The
remaining 26 bytes are reserved for future
expansion.
Registers can be accessed as either 8- or 16-bit
registers using Register, Indirect Register, or
Indexed addressing modes. For register addresses
COH to FFH' the addressing mode used determines the
actual register being accessed.
Registers accessed as 16-bit registers are treated
as even-odd register pairs, with the most signifi480
cant byte of data stored in the even-numbered
register and the least significant byte stored in
the next higher odd-numbered register (Figure
3-3).
MSB
LSB
Rn
Rn+1
I
n
= EVEN ADDRESS
Figure 3-3. 16-Bit Register Addressing
With few exceptions, all instructi'ons that reference or modify a register may do so to any of the
325 8-bit registers or 176 16-bit register pairs,
regardless of the particular register, as long as
the proper addressing mode is used. The instructions operate on I/O ports, system registers, mode
and control registers, and general-pu,rpose regis,-1'8 without the need for special-purpose instruct;.ons.
1j'3age and access are shown in Table 3-1.
Address Spaces
Table 3-1.
SuparB Register file
Registers
Usage
Access
OO-BF
General-purpose registers
Register, Indirect Register, or
Indexed modes, via on-chip DMA
operations, or as part of internal stack
CO-FF
Set Two
General-purpose registers
Indirect Register or Indexed
modes, via on-Chip DMA operations, or as part of internal
stack
CO-FF
Set One
Working registers only
Register mode
DO-DF
Set One
System registers
Register mode
EO-FF
Set One
Mode and control registers
Register mode
The instructions can access a-bit registers or
16-bit register pairs using either 4-bit or a-bit
address fields.
When using 4-bit register
addressing, the register file is logically divided
into 32 groups of a working registers, as shown in
Figure 3-4. All the registers in a working register set have the same value for their five rnostsignificant address bits.
The two Register
Pointers (RPO and RP1) are system registers that
contain the base addresses of two active working
register groups.
GROUP32
xxxr-----
111111
RPO
FO
I
I
I
I
I
I
I
I
I
xxx~
100000
RPI
FF
Fa
F7
10
F
a
GROUP 1
7
RPI (R21S)
o1
1 1
a
1001010001
ope
Figure 3-S. Working Register Addressing
Working registers are typically specified by short
format instructions; when a working register
destination is used in the instruction, only four
bits of address are needed to specify the register; one bit selects the appropriate Register
Pointer and three bits provide the least-significant bits of the register address.
The
five most-significant bits of the address come
from the selected Register Pointer and together
they form an a-bit address.
Applications using
working registers require fewer bytes and have a
reduced execution time.
o
Figure 3-4. Working Register Groups
Note that 4-bit register addressing (Figure 3-5)
is a Register addressing mode so that the registers accessible by this mode include the mode and
control registers, system registers, and working
register groups.
The Register Pointer also speeds context switching
when processing interrupts or changing tasks. A
special Set Register Pointer (SRP) instruction is
provided for setting the Register
Pointer
contents.
481
Address Spaces
RPO(R214)
RP1 (R215)
0110110001
1010010001
3.3 SYSTEM REGISTERS AND MODE AND
CONTROL REGISTERS
'---v----"
SELECTSRP1
L!:
1 0 0
I
R11
1 0 1 1
I,
8.BIT ADDRESS ,
FROM INSTRUCTION
SPECIFIES WORKING
REGISTER ADDRESSING '--_ _ _ _"'-_ _ _ _
+ __-,
REGISTER ADDRESS (R163>1
1 0 1 0 0
I
0 1 1
Figure 3-6. a-Bit Working Register Addressing
The system registers govern the operation of the
CPU and can be accessed using any of the instructions that reference the register file using
Register addressing mode. These registers can be
accessed as working registers. Table 3-2 shows
the system registers.
The SuperB uses a 16-bit Program Counter (PC) to
control the sequence of instructions in the
currently executing program.
The PC is not an
addressable register.
Not all instructions have 4-bit addressing modes,
but the active working registers can still be
accessed using B-bit addressing without having to
know the contents of the Register Pointers.
Figure 3-6 shows how this works. The upper four
bits of the B-bit address contain 1100 to specify
working register addressing. Bit 3 selects Register Pointer 0 or 1, which supplies the upper five
bits of the final address while the lower three
bits come from bits 0-2 of the original 8-bit
address.
Mode and control registers are used to transfer
data, configure the mode of operation, and control
the operation of the on-chip peripherals. These
registers are accessed using Register addressing
mode and are shown in Table 3-3. These registers
can be accessed as working registers. The current
"bank" is determined by bit DO in the Flag
register (R213).
Any address in the range COH-CFH (R192-R207)
wi 11 invoke working register addressing.
Therefore the registers physically located at these
addresses can only be accessed when selected by a
Register Pointer (see Figure 3-2).
Program memory is memory that can hold code or
data.
Instruction code can be fetched from
program memory, data can be read from program
memory and,. i f external program memory is implemented in RAM, data or code can be written to
program memory.
Memory addresses are 16 bits
long, allowing a maximum of' 64K bytes of program
After Reset, the register pointers will be set to
RPO = COH and RP1 = CBH.
Table 3-2.
482
Decilllal
Hexadecilllal
Address
Address
222
221
220
219
21B
217
216
215
214
213
212
211
210
209
20B
DE
DD
DC
DB
DA
D9
DB '
D7
D6
D5
D4
D3
D2
D1
DO
3.4 PROGRAM AND DATA MEMORY
Syst_ Registers
Register Name
System Mode
Interrupt Mask Register
Interrupt Request Register
Instruction Pointer (Bits 7-0)
Instruction Pointer (Bits 15-B)
Stack Pointer (Bits 7-0)
Stack Pointer (Bits 15-B)
Register pointer 1
Register Pointer 0
Program Control Flags
Port 4
Port 3
Port 2
Port 1
Port 0
Identifier
SYM
IMR
IRQ
IPl
IPH
SPl
SPH
RP1
RPO
FLAGS
P4
P3
P2
P1
PO
Address Spaces
Table 3-3.
Decimal
Address
Hexadehimal
Address
MOde and COntrol Registers
Register Name
Identifier
Bank 0 Registers
255
254
253
252
251
250
249
24B
247
246
245
244
241
240
239
237
236
235
229
228
227
226
225
224
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
Fti
F1
ro
EF
ED
EC
EB
E5
E4
E3
E2
E1
EO
Interrupt Priority
External Memory Timing
Port 2/3B Interrupt Pending
Port 2/3A Interrupt Pending
Port 2/3D Mode
Port 2/3C Mode
Port ?/3B Mode
Port 2/3A Mode
Port 4 Open-Drain
Port 4 Direction
Handshake 1 Control
Handshake 0 Control
Port Mode
Port 0 Mode
. UART Data
UART Interrupt Enable
UART Receive Control
UART Transmit Control
Counter 1 Capture Low
Counter 1 Capture High
Counter 0 Capture Low
Counter 0 Capture High
Counter 1 Control
Counter 0 Control
IPR
EMT
P2BIP
P2AIP
P2DM
P2CM
P2BM
P2AM
P40D
P4D
H1C
HOC
PM
POM
UIO
UIE
URC
UTC
C1CL
C1CH
COCL
COCH
C1CT
COCT
Bank 1 Registers
255
254
251
250
249
248
241
240
229
228
227
226
225
224
FF
FE
FB
FA
F9
F8
F1
FO
E5
E4
E3
E2
E1
EO
Wake-Up Mask
Wake-Up Match
UART Mode B
UART Mode A
UART Baud-Rate Generator Low
UART Baud-Rate Generator High
DMA Count Low
DMA Count High.
Counter 1 Time Constant Low
Counter 1 Time Constant High
Counter 0 Time Constant Low
Counter 0 Time Constant High
Counter
Mode
Counter 0 Mode
memory. The bottom of program memory is in the
on-chip ROM; the remaining program memory can be
implemented external to the SuperB.
Data memory is .memory that can hold only data 'to
be read or written, not instruction code; instruction fetches never reference data memor y. Data
memory is always implemented external to the
Super8.
WUMSK
WUMCH
UMB
UMA
UBGL
UBGH
DCL
DCH
CHCL
C1TCH
COTCL
COTCH
C1M
COM
Extemal data memory can be incorporated with or
separated from the external program memory ~ddress
space.
To implement separate program and data
memory address spaces external to the Super8, a
port output pin (P35) must be defined as the Data
Memory select (m:!) output. This output remains
high when fetching instructions or accessing data
in the program memory address space and goes low
when accessing data in the data memory address
space. Thus, this signal can be used to segregate
483
Address Spaces
65535
r--------...,
65535
EXTERNAL
PROGRAM
MEMORY
THIS BOUNDARY}
DEP:~~~~~
r--------...,
EXTERNAL
DATA
MEMORY
---------i}
.....
-i
32~_ _ _ _ _ _ _
ON.CHIP
ROM
INTERRUPT VECTORS
PROGRAM MEMORY
DATA MEMORY
Figure 3-7. Program and Data Memory Address Spaces
the program and data spaces external to the
SuperB.
Separate forms of Load instructions are
used to access the two memory address spaces: the
LDC instruction and its derivatives access program
memory, and the LDE instruction and its derivativea access data memory.
ing, and general dynamic storage (via the Push and
The SuperB provides hardware
Pop instructions).
support for stack operations from either the
register file or data memory.
Stack location
selection is under software control via the
External Memory Timing register (R254, Bank O).
Program and data memory maps are illustrated in
Figure 3-7.
Register pair RR216 forms the 16-bit Stack
Pointer, used for CPU stack operations.
The
address is stored with the most significant byte
in R216 and least significant in, R217 (Figure
3-B} •
To access memory beyond the on-Chip ROM, Ports' 0
and 1 must be configured as a memory interface.
Port 1 can be configured as a multiplexed
address/data bus ( AD O-AD7)' thus providing address
lines AO-A7 and data lines DO-D7' Port 0 can be
configured on an individual bit basis for up to
eight additional address lines (AB-A15)'
Both
parts are supported by the control lines Address
Strobe (~ , Data Strobe (~ , and Read/Write
(R/W') •
In the ROM less version, Port 1 is automatically
configured as a multiplexed address/data bus.
Port 0 bits 0-4 will be configured as address bits
AB-A12 at Reset, but any Port 0 bit may be defined
as either 1/0'01' address as needed.
For more details on external memory interface, see
section 12.3.
No matter, which version of the SuperB is used, the
first 32 bytes of program memory are reserved for
the interrupt vectors.
Thus the first address
available for a user program is location 32. This
address is automaticall y loaded into the Program
Counter whenever a hardware Reset occurs.
:J.5
CPU
AN)
USER STACKS
The SuperB
uses a stack for
implementing
subroutine calls and returns, interrupt process-
484
R217 (09) SPL
I
...._ _L_O_W_E_R_B_Y_T_E_ _... STACK POINTER LOW
R216 (DB)SPH
I
...._ _ _
U_PP_E_R_B_Y_T_E_ _... STACK POINTER HIGH
Figure 3-8. Stack Pointer
The Stack Pointer is decremented before a Push
operation and incremented after a Pop operation.
The stack address always points to the last data
stored on the top-of-stack.
The stack is used to hold the return address for
CALL instructions and interrupts, as we 11 as
data.
The contents of the Program Counter are
saved on the stack during a CALL instruction ahd
restored during a RET instruction. During interrupts, the contents of the Program Counter and
Flag register are saved on the stack. The IRE T
instruction restores them (Figure 3-9).
Wilen the SuperB is configured to use an internal
slack (t.he register file), register R217 serves as
t.he Stack Pointer and register R216 is a generalpurpose register.
However, if an overflow or
underflow condition occurs due to the incrementing
Address Spaces
HIGH ADDRESS
CL
~
TOPOFSTACK
PCL
PCH
STACK CONTENTS
AFTER A CALL
INSTRUCTION
PCH
TOP O F _
STACK
FLAGS
STACK CONTENTS
AFTER A NORMAL
INTERRUPT CYCLE
LOW ADDRESS
Figure 3-9. Stack Operations
Table 3-4.
stack Type-
User Stack Operations Sw.ary
Operation
Stack Location --,
Register
Data
ProgrIaory
Iaory
rUe
Ascending
PUSH to stsck
POP from stack
PUSHUI
POPUD
LDCPI
LOCO
LDEPI
LDED
Daecending
PUSH to stack
POP from steck
PUSHUD
POPUI
LDCPD
LDCI
LDEPD
LDEI
*
~scending stack goes from low to high addresses within memory or
register file. ' Descending ateck goes from high to low addresses
within memory or register file.
and decrementing of normal si&ck operations, the
contents of register R216 are affected.
R218 (OA) IPH
INSTRUCTION POINTER HIGH
I~I~I~I~I~I~I~I~I
The SuperB also provides for user-defined stecks
in both the register file and in program or data
memory. Thesestecks can be made to increment or
decrement on Push and Pop. Table 3-4 sl.llMlarizes
the kinds of stacks 'and, t~e instructions used.
IL- - - - - H I G H aVTE(IP8.IP15)
R219 (OS) IPL
INSTRUCTION POINTER LOW
1~1~1~1~1~1~I~f~1
J.6 INSTRUCTION POINmER {IP)
LI_ _ _ _ _ LOW SYTE (IPO·IP7)
The SuperB provides hardware suppod for implementation of threaded-code languagee such ae forth.
An ,important pert of that support is in the form
of a special regieter called the Instruction
Pointer UP) (figure 3-10).
The Instruction
Pointer is made up of register pair RR21B, with
R21B hOlding the most significant byte of a memory
address and R219 the least significant byte.
A threaded-code language may be considered to have
created a higher level imaginary machine within
the actual hardware machine.
for comparison
purposes, the IP is to the imaginary machine as
the Program Counter is to the actual hardware
machine.
8257·008,009
Figure 3-10. Instruction Poln~er
The IP
is used by three special instructions
NEXT, ENTER, and EXIT.
The instruction
NEXT passes control fr,om the hardware machine to
the imaginary machine, while ENTER and EXIT are
the imaginary machine equivalents of subroutine
CALLS and RETURNs in the hardware machine.
c~lled
The, IP can also be used in the fast interrupt
pr~cessing mode for special interrupt handling
(see section 6.2).
It can be used either for
interrupt processing or imaginsry machine processing, but not for both at the same time.
485
Chapter 4
Addressing Modes
4.1
INTROOUCfION
Accessing an individual register requires specifying an B-bit address in the range 0-Z55 or a
working register's 4-bit address. The most significant bit of the 4-bit working register address
selects one of two Register Pointers: if this bit
is 0, then RZ14' (RPO) is, selected; if it is 1,
then RZ15 (RP1) is selected. The address of the
actual register being accessed is formed by the
concatenation of the high order five bits of the
value contained in the selected Register Pointer
with the remaining three bit address supplied by
the instruction.
Instructions are stored as lists of bytes in
program memory that are fetched via instruction
fetches using the Program Counter.
Instructions
will indicate both the action to be performed and
the data to be operated on. The method used to
determine the location of the data operand is
called the addressing mode.
Operands specified in SuperB instructions are
either condition codes, immediate data, or the
designation of a register file, program memory, or
data memory location.
A register pair can be used to specify a 16-bit
value or memory address.
The Load Constant
instruction and its derivatives (LOC, LDCD, LDCI,
LDCPD, LDCPI) load data from program memory; the
Load External instruction and its derivatives
(LDE, LDED, LDEI, LDE~D, LDEPl) load from program
memory. See the instruction set in Chapter 5 for
further details.
For the SuperB, there are seven explicit addressing modes (i.e., addressing modes designated by
the programmer):
•
•
•
•
•
•
•
Register (R)
Indire'ct Register (IR)
Indexed (X)
Direct Address (DA)
Indirect Address (IA)
Relative Address (RA)
Immediate (lM)
4.2
REGISTER ADDRESSING (R)
In the Register addressing mode, the operand value
is the contents of the specified register or
register pair (Figures 4-1 and 4-Z).
Not a 11 modes are avaUable with each instruction
(refer to the individual instruction descriptions
in section 5.5).
Registers
COH-FFH
(set
one)
can
only
accessed with the Register addressing mode.
REGISTER FILE
PROGRAM MEMORY
8·BIT REGISTER
FILE AODRESS
I'
ONE·OPERAND
INSTRUCTION
EXAMPLE
OPERAND,
dst
POINTS TO ONE REGISTER
IN REGISTER FILE
OPCODE
#
/
,/
VALUE USED IN
INSTRUCTION EXECUTION
Figure 4-1. Register Addressing
REGISTER FILE
MSB POINTS TO
RPOORRP1
RPOOR RP1
L
PROGRAM MEMORY
4·BIT WORKING
REGISTER
dst
TWO·OPERAND
INSTRUCTION
EXAMPLE
src
OPCODE
3LSBs
POINT TO THE
WORKING REGISTER
(10F8)
OPERAND
Figure 4-2. Working Register AddreSSing
486
SELECTEDRP
POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP
be
Addressing Modes
PROGRAM MEMORY
REGISTER FILE
a·BIT REGISTER
FILE ADDRESS
~~~:?:UE~T~~~
~~==~d~S~'~==~~~~~~~~ws,fER--·~~~~~~==~
OPCODE
POI~~SR~~~~~RR~~~TER
EXAMPLE
ADDRESS OF
OPERAND USED
BYI'NSTRUCTION~
OPERAND
VAWE USED IN
INSTRUCTION
EXECUTION
Figure 4-3. Indirect Register Addressing to Register File
REGISTER FILE
MSB POINTS T0
RPOOR RPI
RPOORRPI
r--~-
.
I
SELECTEDRP
POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP
I
PROGRAM MEMORY
4·BIT WORKING
REGISTER ADDRESS -flo-
src
ds'
OPCODE
I
I
I
I
__ ..L .2~B!...
I'
-
ADDRESS
POINT TO WORKING
REGISTER (1 OF 8)
~l/
~
VAWEUSEDIN
INSTRUCTION
--
..
r'
,
OPERAND
Figure 4-4. Indirect Working Register Addressing to Register File
REGISTER FILE
EXAMPLE INSTRUCTION
REFERENCES PROGRAM
MEMORY
--
ds.
~
OPCODE
-
REGISTER
PAIR
POINTS TO
REGISTER PAIR
~
1\
PROGRAM MEMORY
VAWEUSEDIN
INSTRUCTION;-- ~
I
lS·BIT
ADDRESS
POINTS TO
PROGRAM
MEMORY
OPERAND
Figure 4-5. Indirect Register Addressing to Program Memory
487
Addressing Modes
4. J
It.DIRECJ REGISTER IIIlDRESSING (IR)
4.4
In the Indirect Register addressing mode, the
content of the specified register or register pair
is the address of the operand (Figures 4-3, 4-il"
4-5, and 4-6). Depending on the instruction used,
the actual address may point to a register,
program memory, or data memory.
It.DEXED ADDRESSING (X)
The Indexed addressing mode involves adding an
offset to a base address during instruction execution to calculate the effective address of ,the
operand. The Indexed addressing mode can be usea
to access registers or memory areas.
For register accesses, an a-bit base address given
in the ins"truction is added to an a-bit offset
given in a working register (Figure 4-7).
General-purpose registers COH-FFH (set two)
can be accessed only with the Indirect Register
and Indexed addressing modes. The LD instruction
is the only instruction that allows Indexed
addressing of the registers!
Any general-purpose byte register can be used to
indirectly ad,dress another register; any generalpurpose register pair can be used to indirectly
address a memory location.
General-purpose' registers COH-FFH (set two)
can be accessed only with the Indirect Register
and Indexed addressing modes.
REGISTER FILE
MSB POINTS TO
RPOORRPI
4·BIT WORKING
REGISTER ADDRESS
,
EXAMPLE
INSTRUCTION
REFERENCES EITHER
PROGRAM MEMORY I'
OR DATA MEMORY
RPOORRPI
~
PROGRAM MEMORY
REGISTER
sre
dst
PAIR
NEXT 2 BITS POINT
TO WORKING REGISTER
PAIR (I OF4)
OPCODE
LSBSELECTS
~
SELECTEORP
POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP
I
~)
16·BIT
ADDRESS
POINTS TO
PROGRAM
OR DATA
MEMORY
PROGRAM MEMORY
OR
DATA MEMORY
OPERAND
VALUE USED I N / A ' - - = = = - - - - i
INSTRUCTION
_
Figure 4·6. Indirect Working Register Addressing to Program or Data Memory
REGISTER FILE
MSB POINTS TO
RPOORRPI
r---I
I
I
I
I
I
I ~~:t:~~~il~~
PROGRAM MEMORY
BASE ADDRESS
TWO·OPERAND
INSTRUCTION _
EXAMPLE
dst/src
,
OPCODE
x
\
....
OPERANO
,~
f/
Y3LSB~~
.L _ _ _
~
_
POINT TO ONE OF
THE WORKING
REGISTERS (I OF 8)
INDEX
,
"
Figure 4·7. Indexed Addressing to Register File
488
..
I'
:/
I
RPOORRPI
SELECTEDRP
POINTS TO
ORIGIN OF
WORKING
REGISTER
GROUP
Addressing Modes
For memory accesses, the base address is held in
the working register pair designated in the
instruction and an 8-bit or 16-bit offset given in
the instruction is added to that base address
(Figures 4-8 and 4-9).
In the short offset
Indexed
treated
+127.
Indexed
addressing mode, the 8-bit displacement is
as a signed integer in the range -128 to
Only the LDC and LDE instructions allow
addressing of memory.
REGISTER FILE
-
MSB POINTS TO
RPOOR RP1
('--
RPOORRP1
...
~
SE LECTEDRP
PO INTSTO
OR IGINOF
WORKING
REGISTER
GR OUP
PROGRAM MEMORY
r--.
OFFSET
4-BIT WORKING
REGISTER ADDRESS
-
~
dst/src
x
PAIR
I ~~~~I~~
I
REGISTER
I rtb~4)
I
."m
16-BIT
ADDRESS
ADDED TO
OFFSET
PROGRAM MEMORY
OR
DATA MEMORY
..... --~
L SBSELECTS
4..
)h
REGISTER
.J!::X~~T~
i-
OPCODE
~'""': ~VALUEUSED
16 BITS
~ININSTRUCTION
'
Figure 4-8_ Indexed Addressing to Program or Data Memory with Short Offset
REGISTER FILE
-
MSB POINTS TO
RPOORRP1
('--
RPOOR RP1
o-~
SE LECTEDRP
PO INTSTO
0 RIGINOF
WORKING
RE GISTER
GROUP
I'
PROGRAM MEMORY
OFFSET
OFFSET
4-BIT WORKING
REGISTER ADDRESS
-
.... dstlsrc
x
t----I-
.J!::X~~T~
I ~~~~I~~
I REGISTER
I PAIR
OPCODE
REGISTER
PAIR
)h
16-BIT
ADDRESS
ADDED TO
OFFSET
"
I
'- -
- --a-.
L SBSELECTS
PROGRAM MEMORY
OR
DATA MEMORY
1';,.."'~:~::::I!~::~""
.
--....
,..,m
Figure 4-9. Indexed Addressing to Program or Data Memory with Long Offset
489
Addressing Modes
,
Only the CALL instruction uses this addressing
mode.
4.5 DIRECT ADDRESSING (DA)
In Direct addressing mode, as seen in Figures 4-10
and 4-11, the 16-bit memory address of the operand
is given in the instruction. This mode is used by
the Jump and Can instructions to specify the
16-bit destination that is loaded into the Program
Counter to implement the Jump or Call. This mode
is also supported by the LDE and LDC instructions
to specify the source or destination memory
address for a.load between a register and a memory
location. Memory loads with LDC and LDE can use
the Direct or Ind!rect Register addressing modes.
PROGRAM MEMORY
~---",~,=,~"~~
LSB MUST BE ZERO
dBt
.~
r--
OPCODE
MEMORY
MEMORY
ADDRESS USED
LOWER ADDR BYTE
UPPER ADDR BYTE
dstlsrc
OPCODE
LSBSELECTS
PROGRAM OR
DATA MEMORY
o = PROGRAM MEMORY
1 = DATA MEMORY
1-
)
,PROGRAM MEMORY
LOCATIONS 0-255
Figure 4-12. Indirect Addressing
4.7 RELATIVE ADDRESSING (RA)
Figure 4-10. Direct Addressing for Load Instructions
PROGRAM MEMORY
NEXTOPCODE
PROGRAM MEMORY
ADDRESS USED
LOWER ADDR BYTE
UPPER ADDR BYTE
In the Relative addressing mode (Figure 4-13), a
twos-complement signed displacement in the range
-128 to +127 is specified in the instruction and
added to the value contained in the Program
Counter. The result is the address of the next
instruction to be executed. Prior to, the add, the
Program Counter contains the address of the
instruction following the current 'inatruction.
The Relative addressing mode is aupported by
several program contro~ type inatructions: BTJRF,
BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
OPCODE
PROGRAM MEMORY
Figure 4-11. Direct Addressing for Call and'
.
Jump Instructions
NEXTOPCODE
4.6 IN)lRECT ADDRESSING(IA)
In the Indirect addressing mode (Figure 4-12), the
instruction specifies a pair of memory locations
found in the lowest 256 bytes of program memory.
The selected pair, in turn, contains the actual
address of the next instruction to be executed.
DISPLACEMENT
INST~~'l:~~~~ --I-_...:o,,-P,;;.CO,;;.D;;,;E"-_-l
SIGNED
DISPLACEMENT
VALUE
Figure 4-13. Relative Addressing
Since the Indirect addressing mode assumes that
the operand is located in the lowest 256 bytes of
memory, only an 8-bit address is supplied in the
instruction; the upper bytes of the destination
address are assumed to be aliOs.
490
Addressing Modes
4.8 IMMEDIATE ADDRESSING (1M)
In the, Immediate addressing mode (Figure 4-14),
the operand value used in the instruction is the
value supplied in the operand field itself. The
operand may be a byte or word in length, depending
on the instruction. The Immediate addressing mode
is useful for loading constant values into
registers.
PROGRAM MEMORY
OPERAND
OPCODE
THE OPERAND VAWE IS IN THE INSTRUCTION
\
Figure 4·14. Immediate Addressing
491
ChapterS
Instruction Set
S.1
FlN:TlONAL SlIItARY
SuperB instr,uctions can be divided functionally
into the following seven groups:
•
•
•
•
•
•
•
Load
Aritl'lnetic
Logical
Program Control
Bit Manipulation
Rotate and Shift
CPU Control
Table 5-1 shows the instructions belonging to each
group and the number of operands required for
each, where "arc" is the source operand, 'idst" is
the destination operand, and _"cc" is the condition
code.
With few exceptiona, all instructions that reference a register may do so to any of the 325 B-bit
registers or 176 16-bit register pairs. Thus, the
same instructions are used to 'operate on I/o
ports, system registers, mode and control registers, and general-purpose registers.
The exceptions to the above are as follo'ws:
•
The Oecrement and Jump Dn Non-Zero (OJNZ)
instruction's register
Dperand must be a
general~purpose byte register.
•
The following control regiaters are write-only
regiatera: Port Mode, Port 2/3 A Mode, Port 2/3
B Mode, PDrt 2/3 C Mode, Port 2/3 0 Mode,
Handahake 0 Control, and Handahake 1 Control.
•
The Flaga register (R213) cannot be the destination for an instruction that alters the flags
as part of its operation.
S.2
PROCESSOR
~
Flag register R213 supplies the status of the
SuPerB CPU at anytime. The flags and their bit
positions are shown in Figure 5-1.
492
'
Llli
R213 (05) FLAGS
SYSTEM FLAG REGISTER
I~I~I~I~I~I~I~I~I
CARRYFLAGJ~~·
ZERDFLAG~
SIGN FLAG.
L
,
BANK ADDRESS
LFAS~INTI'RRUPTSTATUS
HALF-CARRY FLAG
DECIMAL ADJUST
OVERFLOW FLAG
Figure 5-1. Flag Register
This register cDntains eight bits Df status information that are set Dr cleared by CPU operations.
FDur of the bits (C, V, Z, and S) are testable for
use with conditional Jump' instructions.
Two of
the flags (H and D) are not testable and are used
only for BCD aritl'lnetic. All flags are restored to
the pre-interrupt value by a return frDm
interrupt.
Bank Address Flag (BA). This bit selects which of
the two groups of mDde and cDntrol registers is
active.
Carry Flag (C). This" flag is set to 1 whenever
the result of an arithmetic operation generates a
carry-out of or borrow intD the high order bit 7.
It is cleared to 0 whenever an operation' does not
generate a carry or bDrrow condition. This flag
can be set, cleared, and complemented by the Set
Carry Flag (scF) , Reset Carry Flag (RCF) , and
, Complement Carry Flag (CC'F) instructions. '
Deciaal-Adjust Flag (D). The Decimal-Adjust flag
is used for BCD arithmetic.
It 'is set to 1
following a subtraction operation and cleared to 0
following an addition operation.
Since the
algoritl'lns for correcting BCD addition and
subtraction are different, this flag is used to
specify the type of instruction last executed so
that the subsequent Decimal Adjust (DA) operation
can function properly. It is not normally used as
a test flag by the programmer.
Fast Interrupt Status Flag (ns). This bit is set
to 1 during a I:ast Interrupt and cleared to 0
during the Interrupt Return (IRET).
Instruct ion Set
Table 5-1.
thDonic
Operands
Instruction Group
S~ary
Instruction
Load Instructions
CLR
LD
LDB
LDE
LDC
LDED
LDCD
LDEI
LDCI
LDEPD
LDCPD
LDEPI
LDCPI
LDW
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
dst
dst,src
dst,src
dst,src
dst ,src
dst ,src
dst,src
dst,src
dst ,~rc
dst,src
dst ,src
dst,src
dst,src
dst,src
dst
d~st,src
dst,src
src
dst,src
dst,src
Clear
Load
Load Bit
Load Data Memory
Load Program memory
Load Data Memory and Decrement
Load Program Memory and Decrement
Load Data Memory and Increment
Load Program Memory and Increment
Load Data Memory with Pre-Decrement
Load Program Memory with Pre-Decrement
Load Data memory with Pre-Increment
Load Program Memory with Pre-Increment
Load Word
Pop
Pop User Stack (Decrementing)
Pop User Stack (Incrementing)
Push
Push User Stack (Decrementing)
Push User Stack (Incrementing)
Arithaletic Instructions
ADC
ADD
CP
DA
DEC
DECW
DIV
INC
INCW
MULT
SBC
SUB
dst ,src
dst,src
dst,src
dst
dst
dst
dst,src
dst
dst
dst,src
dst,src'
dst,src
Add with Carry
Add
Compare
Decimal Adjust
Decrement
Decrement Word
Divide
Increment
Increment Word
Multiply
Subtract with Carry
Subtract
Logical Instructions
AND
COM
OR
XOR
dst ,src
dst
dst,src
dst,src
L~gical AND
Complement
Logical OR
Logical Exclusive OR
Progr_ Control Instructions
BTJRF
BTJRT
GALL
CPIJE
dst,src
dst,src
dst
dst,src
Bit Test and Jump Relative on False
Bit Test and Jump Relative on True
Call Procedure
Compare, Increment and Jump on Equal
493
Ins
Table 5-1.
It1eaonic
Instruction GroUp Summary (Continued)
Operands
Instruction
Progrmn Control Instructions (Cont inued)
CPIJNE
DJNZ
ENTER
EXIT
IRET
JP
JP
JR
JR
NEXT
RET
WFI
dst,src
r,dst
cc,dst
dst
cc,dst
dst
Compare, Increment and Jump on Non-Equal
Decrement Register and Jump on Non-Zero
Enter
Exit
Interrupt Return
Jump on Condition Code
Jump Unconditional
Jump Relative on Condition Code
Jump Relative Unconditional
Next
Return
Wait for Interrupt
Bit Manipulation Instructions
BAND
BCP
BITC
BITR
BITS
BDR
BXOR
TCM
TM
dst,src
dst,src
dst
dst
dst
dst,src
dst,src
dst,src
dst,src
Bit AND
Bit Compare
Bit Complement
Bit Reset
Bit Set
Bit OR
Bit XOR
Test Complement Under Mask
Test Under Mask
Rotate and Shift Instructions
RL
RLC
RR
RRC
SRA
SWAP
dst
dst
dst
dst
dst
dst
Rotate Left
Rotate Left through Carry
Rotate Right
Rotate Right through Carry
Shift Right Arithmetic
Swap Nibbles
CPU Control Instructions
CCF
01
EI
NOP
RCF
SBO
SB1
SCF
SRP
SRPO
SRP1
494
src
src
src
Complement Carry Flag
Disable Interrupts
Enable Interrupts
No Operation
Reset Carry Flag
Set Bank 0
Set Bank 1
Set Carry Flag
Set Register Pointers
Set Register Pointer 0
Set Register Pointer 1
Instruction Set
Half-Carry flag (H). The Half-Carry flag is set
to ,1 whenever an addition generates a carry-out of
bit 3 or subtraction generates a borrow into bit
3.
The Half-Carry flag is used by the Decimal
Adjust (DA) instruction to convert the binary
result of a previous addition or subtraction into
the correct decimal (BCD) result.
It is not
normally used as a test flag by the programmer.
Zero Flag (Z). During arithmetic and logical
operations, the Zero flag is set to 1 if the
result is zero and cleared to 0 if the result is
non-zero. When testing bits in a register or when
shifting,or rotating, the Zero flag is set to 1 if
the result is zero; if the result is not zero, the
flag is cleared to O.
Overflow Flag (V). This flag is set to 1 dur ing
arithmetic, rotate, or shift operations that
result in a value ,greater than +127 or less than
-128 (the maximum and minimum numbers that can be
represented in twos-complement form); it is
cleared to 0 whenever the result is a value within
these ranges.
This flag is also cleared to 0
following logical operations.
5.3 CONDITION CODES
Sign Flag (S). When performing arithmetic operations on signed numbers, :binary twos-complement
notation is used to represent and process information. A positive number is identified by a 0 in
the most significant bit position; when this
occurs, the Sign flag is also cleared to O. A
negative number is identified by a 1 in the most
significant bit position and therefore the Sign
flag would be set to 1.
Table 5-2.
Binary
Hneaonic
0000
1000
0111*
1111*
0110*
1110*
1101
0101
0100
1100
0110*
1110*
1001
0001
1010
0010
1111 *
0111*
1011
0011
F
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Flags C, Z, 5, 'and V control the operation of the
"condi tional"
Jump
instructions.
Sixteen
frequently used combinations of flag settings
are encoded in a 4-bit field called the condition
code (cc), which forms a part of the conditional
instructions (bits 4-7).
The condition codes and the flag settings they
represent are listed in Table 5-2.
5.4 NOTATION AND BINARY ENCODING
The following sections describe the symbols used
for operands and status flags, and the flag
settings and their meanings.
Condition Codes
Meaning
Always False
Always True
Carry
No Carry
Zero
Not Zero
Plus
Minus
Overflow
No Overflow
Equal
Not Equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
nags Set
C =1
C 0
Z 1
Z 0
5 0
5 =
V
V =0
Z=1
Z 0
(5 XOR V) = 0
(5 XOR V) = 1
(Z OR (5 XOR V»
0
(Z OR (5 XOR V»
C=0
C=1
(C = 0 AND Z = 0) =
(C OR Z) = 1
*Indicates condition' codes that relate to two different mnemonics but test
the same flags.
For example, Z and EQ are both True if the Zero flag is
set, but after an ADD instruction, Z would probably be used, While after a
CP instruction, EQ would probably be used.
495
Instruction Set
Table 5-'.
NOtation
cc
r
rb
rO
rr
R
Meaning
Actual Operand/Range
Condition code
Working register only
Bit b of working register
Bit 0 of working register
Working regi~ter pair
Register or working register
See condition code list (Table 5-2)
Rn: where n = 0-15
Rn Db: where n = 0-15 and b = 0-7
Rn: where n = 0-15
RRp: where p = 0,2,4, ••• ,14
Reg: where reg represents a number in the range
0-255
Rn: where n = 0-15
Reg Db: where reg represents a number in the
range 0-255 and. b = 0-7
Rn Db: where n = 0-15 and b = 0-7
Reg: where reg reprsents an even number in the
range 0-254
RRp: where p = 0,2, ••• ,14
D addrs: where addrs represents an even number
in the range 0-254
®Rn: where n = 0-15
®reg: where reg represents a number in the range
0-255
@Rn: where n = 0-15
®RRp: where p = 0,2, ••• ,14
®reg: where reg represents an even number in the
range 0-254
®RRp: where p = 0,2, •••• 14
reg (Rn): where reg represents a number in the
range 0-255 and n = 0-15
addrs (RRp): where addrs represents a number in
the range -128 to +127 and p = 0,2, ••• ,14
addrs (RRp): where addrs'represents a number in
the range 0-65,535 and p = 0,2, ••• ,14
addrs: where addrs represents a number in the
range 0-65,535
addrs: where addrs represents a number in the
range +127,-128 that is an offset relative to
the address of the next instruction
Ddata: where data is a number between 0 and 255
Ddata: where data is a number between 0 and
65,535
Rb
Bit b of register or working
register
RR
Register pair or working
register pair
IA
Indirect addressing mode
Ir
IR
Indirect working register only
Indirect register or working
register
In
IRR
Indirect working register only
Indirect register pair or
working register pair
x
Indexed addressing mode
XS
DA
Indexed (Short Offset)
addressing mode
Indexed (Long Offset)
addressing mode
Direct addressing mode
RA
Relative addressing mode
1M
Immediate addressing mode
Immediate (Long)
addressing mode
XL
IML
496
NOtation and Binary Encoding
Instruct ion
5.4.1
Se~
Notational Shorthand
Operands and status flags are represented by a
notational shorthand in the detailed instruction
descriptions of section 5.5.2. The notation for
operands (condition codes and addressing modes)
and the actual operands they represent are shown
in Table 5-3.
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr (n)" is
used to refer to bit "n" of a given location. For
example,
dst (7)
refers to bit 7 of the destination operand.
Additional Syrebols Used:
5.4.2 flag Settings
Symbol
Meaning
dst
src
Destination operand
Source operand
Indirect Register address prefix
Stack Pointer (R216 and R217)
Program Counter
Instruction Pointer (R218 and
R219)
Flag register (R213)
Register Pointer 0 (R214)
Register Pointer 1 (R215)
Interrupt Mask register (R221)
Immediate operand or Register
address prefix
Hexadecimal number prefix
Opcode
Notation for the flags is shown below.
@
SP
PC
IP
FLAGS
RPO
RP1
IMR
II
OPC
Assignment of a value is indicated by the symbol
"<--"; for example,
flag
C
Z
S
V
D
H
0
*
X
Meaning
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-Adjust flag
Half-Carry flag
Cleared to 0
Set to 1
Set or Cleared according to operation
Unaffected
Undefined
Figure 5-2 provides a quick reference guide to the
commands.
dst <-- dst + src
497
Instr.uct ion Set
SUPERS OPCODE MAP
Lower Nibble (Hex)
o
o
":E.....
:c
6
7
8
9
A
B
C
o
E
F
10
10
10
10
6
6
12/10
12/10
6
12/10
6
14
NEXT
6
6
DEC
DEC
ADD
ADD
ADD
ADD
ADD
BOR"
LO
LO
OJNZ
JR
LO
JP
INC
Rl
IRI
r1,r2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
ro-Rb
fl,R2
r2,Rl
rl,RA
cc,RA
rl,IM
cc,DA
rl
6
6
6
6
10
10
10
10
RLC
RLC
AOC
AOC
AOC
AOC
AOC
BCP
Rl
IRI
r1,r2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
fl,b,R2
6
6
6
6
10
10
10
10
INC
INC
SUB
SUB
SUB
SUB
SUB
SXOR"
Rl
IRI
'l,r2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
ro-Rb
IRRI
6
5
6
10
5
4
6
JP
4
3
NOTE
C
6
6
10
10
10
SBC
SSC
SSC
SBC
SBC
r1/2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
6
6
10
10
OA
OR
OR
OR
OR
OR
LOB"
IRI
r1,r2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
fo-Rb
10
10
10
10
6
6
10
8
POP
POP
AND
AND
AND
AND
AND
BITC
Rl
IRI
r1,r2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
rl,b
6
10
10
10
10
6
6
6
10
10
COM
COM
TCM
TCM
TCM
TCM
TCM
BAND"
Rl
IRI
r1,f2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
ro-Rb
10/12
12/14
6
6
10
10
10
PUSH
PUSH
TM
TM
TM
TM
TM
.c
R2
IR2
r1,r2
'l, lr2
R2,Rl
IR2,Rl
Rl,IM
:;;
10
10
10
10
24
24
24
10
MULT
MULT
MULT
LO
rl,x,r2
7
Z
Co
Co
8
:>
9
A
S
C
0
E
OECW
IRI
IR1,R2
IR 1,R2
R2,RRl
IR2,RRl
IM,RRj
6
10
10
28/12
28/12
28/12
10
RL
RL
DlV
DlV
OIV
LO
Rl
IRI
R2,RRl
IR2,RRl
IM,RRI
r2,x,rl
IR2,Rl
IR2,Rl
10
10
6
6
10
10
10
INCW
INCW
CP
CP
CP
CP
CP
RRI
IRI
r1,r2
'l, lr2
R2,Rl
IR2,Rl
Rl,IM
6
6
6
CLR
CLR
XOR
XOR
XOR
XOR
XOR
Rl
IRI
r1,r2
r1, lr2
R2,Rl
IR2,Rl
Rl,IM
6
6
6
16/18
12
RRC
RRC
CPIJE
LOC"
Rl
IRI
Ir,f2,RA
r1, lrr2
10
10
10
10
10
12
LOW
LOW
LOW
RR2,RRl IR2,RRl RR1,IML
~
WFI
~
SBO
~
,SBI
r-----------r------------
B
6
POPUO POPUI
EXIT
NOTE
RRI
r---6
01
~
EI
I
t----;4
NOTE
RET
0
~
NOTE
IRET
E
~
6
LO
RCF
'l, lr 2
6
6
16118
12
20
6
SRA
SRA
LOC"
~
CPIJNE
CALL
LO
LO
SCF
Rl
IRI
Irl,r2,RA
r2, lrr1
IAI
IR1,IM
Irl,r2
10
6
6
16
16
10
RR
RR
LOCO"
LOCI"
LO
LO
LO
LOC"
Rl
IRI
r1, lrr2
r1, lrr2
R2,Rl
IR2,Rl
Rl,IM
rl,lrr2,xs
8
16
16
8
F
OECW PUSHUO PUSHUI
~
A
Rl
6
ENTER
NOTE
OA
6
~
I
SWAP
Rl
SWAP LOCPO" LOCPI"
IRI
r2,lrrl
r2, lrr1
10
~
18
18
10
18
18
CALL
LO
CALL
LOC"
IRRI
R2, IR l
DAI
r2,lrrl,x8
NOTEB
NOTE A
10
NOTEC
CCF
~
NOP
Legend:
r := 4-bit address
R
~
8-blt addfess
b = bit number
R1 or'l = dst address
R2 or r2 = src address
NOTED
"Examples:
BOR fo-R2
is BOR fl ,b,R2
or BOR r2,b,Rl
LDCrl,lrr2
is LOC r1 ,lrr2 = program
or LDE fl ,lrf2 = data
NOTEE
Sequence:
Opcode, first, second, third operands
NOTE: The blank areas are not defined.
Figure 5-2. SuperS Opcode Map
498
5.5
Ace
Instruction
Descriptions
and Formats
ADC
Add With Carry
dst,src
Operation:
dst
~-
dst + src
+ C
The source operand ,along with the setting of the Carry flag, is added to the destination
operand and the sum is stored in the destination. The contents of the source are unaffected. Twos-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the
addition of high-order operands.
Flags:
C:
Z:
V:
5:
D:
H:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurs, that is, if both operands are of the sam~ sinn and
the result is of the opposite sign; cleared otherwise.
Set if the result is negative; cleared otherwise.
Always cleared
Set if there is a carry from the most significant bit of the low-order four bits of the
result; cleared otherwise.
Instruction
format:
Cycles
Opcode
Opcode
Opcode
II
II
II
dst
src
src
dst
6
II
II
Opcode
(Hex)
12
Addressing Mode
dst
src
13
r
r
r
Ir
dst
10
14
15*
R
R
R
IR
src
10
16
R
1M
*This format is used in the example.
EXlIlIlple:
I f the register named SUM contains %16, the Carry flag is set to 1, working regi,ster 10
contains %20 (32 decimal), and register 32 contains %10, the statement
ADC SUM,
~R1D
leaves the value %27 in register SUM.
499
AND
Logical
AND
dst ,src
Operation:
dst
~-
dst AND src
The source operand is logically ANDad with the destination operand.
The rCGult is stored in
the destination. The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both 1s; otherwise a 0 bit is stored. The contents of the
source are unaffected.
Flags:
C:
Unaffected
Z: Set if the result is 0; cleared otherwise.
V: Always cleared to O.
5:
H:
D:
Set if the result bit. 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
For_t:
Opcode
Opcode
Opcode
II
II
II
dst
src
Cycles
Opcode
(Hex)
Addressing Mode
dst
src
6
52
53
r
r
r
Ir
src
II
dst
10
54
55
R
R
R
IR
dst
II
src
10
56*
R
1M
*This format is used in the example.
Exallple:
If the source operand is the immediate value %76 (01111011) and the register named TARGET
contains %C3 (11000011), the statement
AND TARGET, #%76
leaves the value 1;43 (01000011) in register TARGET.
500
BAND
Bit And
BAND
BAND
dst,src,b
dst,b,src
Operation:
dst(O)
~-
dst(b)
~-
dst(O) AND src(b)
or
dst(b AND arc(O)
The specified bit of the source (or the destination) is logically ANDed with bit 0 of the
destination (or source).
The resultant bit is stored in the specified bit of the
destination. No other bits of the destination are affected. The source is unaffected.
Flags: ,
C:
Unaffected
Z: Set if the result is 0; cleared otherwise.
V: Undefined
s:
H:
D:
0
Unaffected
Unaffected
Inatruction
for.at:
Opcode
Opcode
Idstl
I I
Isrc
b
b
1°1
I
111
I
Cycles
Opcode
(Hex)
src
10
67*
rO
Rb
dst
10
67
Rb
rO
Addressing Mode
dst
src
*This format is used in the example.
[x_pIe:
I f the register named BYTE contains %73 (01110011) and working register J contains %01, the
statement
BAND RJ,BYTE,117
leaves the value %00 in working register 3.
501
BCP
Bit Compare
BCP dst,src,b
Operation:
dst(O) - src(b)
The specified bit of the source is compared to (subtracted from) bit 0 of the destination.
The Zero flag is set if the bits are the same; otherwise it is cleared. The contents of
both operands are unaffected by the comparison.
Flags:
C:
Z:
V:
5:
H:
0:
Unaffected
Set if the two bits are the same; cleared otherwise.
Undefined
0
Unaffected
Unaffected
Instruction
Forlll3t:
Opcode
(Hex)
Opcode
1dst I
biD
I \.-1_s_rc----'
10
17
Addressing Mode
dst
.!!!:£.
ro
Example:
I f working register 3 contains %01 and register 64 (%40) contains
?~FF,
the statement
BCP R3,64,IIO
sets the Zero flag bit in Flag register R213.
BITC
Bit Complement
BITC dst,b
Operation:
dst(b)
~-
NOT dst(b)
This instruction complements the specified bit within the destination without affecting any
other bits in the destination.
Flags:
C:
Z:
V:
5:
H:
0:
Unaffected
Set if the result is 0; cleared otherwise.
Undefined
0
Unaffected
Unaffected
Instruction
Format:
Opcode
(Hex)
Opcode
B
Example:
If working
~egister
3 contains %FF, the statement
BITC R3,117 ,
leaves the value %7F in that 'register.
502
57
Addressing Mode
dst
BITR
Bit Reset
BITR
dst,b
Operation:
dst (b)
~-
0
This instruction clears the specified bit within the destination without affecting any other
bits in the destination.
Flags:
No flags affected
Instruction
format:
Opcode
(Hex)
--,I
,---Opc_od_e
Idstl
i
bi o
8
Addressing Hode
dst
77
Example:
If working register 3 contains %80, the statement
BITR R3,117
leaves the value %00 in that register.
B~TS
Bit Set
BITS
dst,b
Operation:
dst(b)
~-
1
This instruction sets the specified bit within the destination without affecting any other
bits in the destination.
Flags:
No flags affected
Instruction
format:
Opcode
(Hex)
Addressing Hode
dst
77
Opcode
Example:
If working register 3 contains %00, the statement
BITS R3,117
leaves the value
~~BO
in that register.
503
BOR
Bit OR
BOR
BOR
dst,src,b
dst,b,src
Operation:
dst(O)_- dst(O) OR src(b)
or
dst(b) .. - dst(b) OR src(O)
The specified bit of the source (or the destination) is logically ORed with bit 0 of the
destination (or the source).
The resultant bit is stored in the specified bit of the
destination. No other bits of the destination are affected. The source is unaffected.
Flags:
c:
Z:
V:
5:
Unaffected
Set if the result is 0; cleared otherwise.
Undefined
0
H: Unaffected
0:
Unaffected
Instruction
Format:
Opcode.
(Hex)
,--_o_pc_o_d_e_.....1
I I
,--_o_p_c_o_d_e_.....1
Isrc I b 1111'--_d_Sl---l
dst
b
10 I
I<--_src- - - - I
10
07
10
07*
Addressing Hode
dst
!!!:E.
rO
ro
*This format is used in the example.
Example:
If register 32 (%20) contains %OF and working register 3 contains %01, the statement
BOR 32,117 ,R3
leaves the value %8F in register 32.
504
IBTJRF
Bit Test and Jump Relative on False
BTJRf
dst,src,b
Operation:
If src(b) is a 0, PC
~-
PC + dst
The specified bit within the source operand is tested. If it is a 0, the relative address
is added to the Program Counter and control passes to the statement whose address is now in
the PC; otherwise the instruction following the BTJRF instruction is executed.
No flags affected
flags:
Instruction
Format:
Opcode
(Hex)
,-_o_p_c_o_d_e_-,I
I src
b 10 1 ...l __d_s_t_--,
16/1B*
37
Addressing Mode
dst
src
RA
* 18 if jump taken, 16 if not
Example:
If working register 6 contains %7F,the statement
BTJRF SKIP,R6,U7
causes the Program Counter to jump to the memory location pointed to by SKIP.
location must be within the allowed range of +127,-128.
The memory
STJAT
Bit Test and Jump Relative on True
BTJRT
dst,src,b
Operation:
If src(b) is a 1, PC
~-
PC + dst
The specified bit within the source operand is tested. If it is a 1, the relative address
is added to the Program Counter and control passes to the statement whose address is now in
the PC; otherwise the instruction following the BTJRT instruction is execut.ed.
flags:
No flags affected
Instruction
format:
Cycles
Opcode
JI
src 1 b 111
I
dst
16/18*
Opcode
(Hex)
37
Addressing Mode
dst
src
RA
rb
* 18 if jump taken, 16 if not
Example:
If working register 6 contains %80, the statement
BT JRT $+8 ,R6, /17
causes the next five bytes in memory to be skipped.
Note:
The $ refers to the address of the first byte of the instruction currently being executed.
505
BXOR
BitXOR
BXOR
BXOR
dst,src,b
dst,b,src
Operation:
dst(O)
or
dst(b)
.--
--
dst(O) XOR src(b)
dst(b) XOR src(O)
The specified bit of the source (or the destination) is logically EXCLUSIVE ORed with bit 0
of the destination (or source). The resultant bit is stored in the specified bit of the
destination. No other bits of the destination are affected. The source is unaffected.
Flags:
c:
Z:
Y:
S:
H:
D:
Unaffected
Set if the result is 0; cleared otherwise.
Undefined
°Unaffected
Unaffected
Instruction
Format:
Opcode
(Hex)
Opcode
Opcode
I
I
Idstl
b
Isrcl
b
10 1
I
111
I
src'
10
27*
dst
10
27
Addressing Mode
dst
src
ro
Example:
If working register 6 contains %rF and working register 7 contains %FO, the statement
BXOR R6, R7, 114
leave\; the value roFE in working register 6.
506
ro
*This format is used in the example.
CAll
Call Procedure
CAll
dst
Operation:
SP 4-- SP :!'!SP 4-- PCl
SP _- SP l~SP _- PCH
PC .... - dst
The current contents of the Program Counter are pushed onto the top of the stack.
The
Program Counter value used is the address of the first instruction following the CAll
instruction. The specified destination address is then loaded into the Program Counter and
points to the first instruction of a procedure.
At the end of the procedure the Return (RET) instruction can be used to return to the
original program flow. RET pops the top of the stack back into the Program Counter.
Flags:
No flags affected
Instruction
format:
Opcode
Opcode
Opcode
II
II
II
Cycles
Opcode
(Hex)
Addressing Hode
dst
18
F6
DA
dst
18
F4
IRR
dst
20
D4
IA
dst
Examples:
(1)
I f the contents of the Program Counter are ~~1A47 and the contents of the Stack Pointer
(control registers 216-217) are %3002, the statement
CALL %3521
causes the Stack Pointer to be decremented to %3000, %1A4A (the address following the
instruction) to' be stored in external data memory locations ~~3000 and ?~3001 (%4A in ~~30001,
?~1A in %3000), and the Program Counter to be loaded with %3521.
The Program Counter now
points to the address of the first statement in the procedure to be executed.
(2)
If the content.s of the Program Counter and Stack Pointer are the same as in Example 1,
working register 6 contains %35, and working register 7 contains ?~21, the statement
CALL @RR6
produces the same result as Example 1 except that %49 is stored in external data memory
locat ion ~~3000.
(3)
I f the contents of the Program Counter and Stack Pointer are the same as in Example 1,
address %0040 contains ~~35, and address %0041 contains %21, the st.atement
CALL
11?~40
produces the same result as Example 2.
507
ADD
Add
ADO
dst,src
Operation:
dst
~-
dst + src
The source operand is added to the destination operand and the sum is stored in the
destination.
The contents of the source are unaffected.
Twos-complement addition, is
performed.
flags:
C:
Set if there was a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is 0; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands were of the same sign and
S:
H:
0:
the result is of the opposite sign; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if a carry from the low-order nibble occurred.
Always cleared to O.
Instruction
Format:
Opcode
Opcode
Opcode
II
II
II
dst
src
src
dst
II
II
dst
src
Addressing, Hode
dst
src
Cycles
Opcode
(Hex)
6
02
03
r
r
r
Ir
10
04*
05
R
R
R
06
R
1M
10
IR
*This format is used in the example.
Example:
I f the register named SUM contains %44 and the register named AUGEND contains
statement
ADD SUM, I\UGEND
leaves the value
508
~'55
in Register SUM.
~'11,
the
CCF
Complement Carry Flag
Operation:
C .... - NOT C
The Carry flag is complemented; if C
Flags:
C:
1, it is changed to C
0, and vice-versa.
Complemented
No other flags affected
Instruction
Forlllat:
Opcode
(Hex)
Opcode
6
EF
Ex .... ple:
If the Carry flag contains a 0, the statement
CCF
changes the
a
to 1.
CLR
Clear
CLR dst
Operation:
dst .... -
a
The destination location is cleared to o.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
~_o_pc_o_d_e__~1 I~
__
d_s_t__~
6
80*
81
Addressing Hode
dst
R
IR
*This format is used in the example.
Example:
If working register 6 contains
~~F,
the statement
CLR R6
leaves the value
a
in that register.
509
COM
Complement
COM dst
Operation:
dst
4--
NOT dst
The contents of the destination location are complemented (ones complement); all 1 bits are
changed to 0, and vice-versa.
Flags:
C:
Z:
V:
S:
H:
0:
Unaffected
Set if the result is 0; cleared otherwise.
Always reset to 0
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
Forc:at:
(Hex)
Addressing Mode
dst
60*
R
61
IR
Opcode
Cycles
L-_o_p_c_o_d_e__~1
IL-___d_s_t__~
6
*This format is used in the example.
Example:
If working register B contains %24 (00100100), the statement
COM RB
leaves the value
510
~mB
(11011011) in that register.
CIP
Compare
CP
dst,src
Operation:
dst - src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
compar ison •
flags:
C:
Z:
V:
5:
H:
0:
Set if a "borrow"
Set if the result
Set if arithmetic
Set if the result
Unaffected
Unaffected
occurred (src > dst); cleared otherwise.
is 0; cleared otherwise.
overflow occurred, cleared otherwise.
is negative; cleared otherwise.
Instruction
Format:
Opcode
Opcode
Opcode
II
II
II
dst
src
Cycles
Opcode
(Hex)
Addressing Mode
dst
src
6
A2
A3
r
r
Ir "
src
II
dst
10
A4
A5"
R
R
R
IR
dst
II
src
10
A6
R
1M
"This format is used in the example.
Example:
If the register named TEST contains %63, working register 0 contains %30 (46 decimal), and
register 46 contains %63, the statement
CP TEST, ijRO
sets (only) the Z flag.
will be taken.
If this statement is followed by "JP EQ, true_routine," the jump
511
DA
Decimal Adjust
DA dst
Operation:
dst
4--
DA dst
The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following
table indicates the operation performed:
Instruction
Carry
Before DA
ADO
AOC
SUB
S8C
Bits 4-7
Value (Hex)
H Flag
Before OA
0
0
0
0
0
0
1
1
1
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0
0-3
1
0
0
1
0
0
1
0
0
1
1
0-9
0-8
7-F
6-F
0
1
0
1
0
Bits 0-3
Value (Hex)
Nuntler Added
To Byte
Carry
After DA
00
06
06
60
66
66
60
66
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
0
0
0
1
1
1
1
1
66
00
FA
AD
9A
0-9
6-F
0-9
6-F
0
0
1
1
-00
-06
-60
-66
The operation is undefined if the destination operand was not the result of a valid addition
or subtraction of BCD digits.
Flags:
C:
Z:
V:
S:
H:
0:
Set if there was a carry from the most significant bit; cleared otherwise (see table
above).
Set if the result is 0; cleared otherwise.
Undefined
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
for.at:
Opcode
(Hex)
,-_o_pc_o_d_e_...,1
'<-_d_s_t_--,
6
40*
41
,
Addressing Mode
dst
R
IR
*This format is used in the example.
Example:
If working register RO contains %15 and working register R1 contains %27, the statements
ADD R1, RO
DAB R1
leave 1;42 in working register R1.
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum
is incorrect, however, when the binary representations are added in the destination location
using standard binary arithmetic.
+
0001
0010
0101
0111
0011
1100
= %3C
The DA statement adjU!3~s this result so that the correct BCD r~presentat.ion is obtained.
+
512
0011
0000
1100
0110
0100
0010
42
CPIJE
Compare Increment and Jump on Equal
CPIJE
dst,src,RA
Operation:
If dst - src = zero, PC _- PC + RA
I r ..... - I r + 1
The source operand is compared to (subtracted from) the
is 0, the relative address is added to the Program
statement whose address is now in the Program Counter;
the CPIJE instruction is executed. In either case the
before the next instruction.
destination operand. If the result
Counter and control passes to the
otherwise the instruction following
source pointer is incremented by one
No flags affected
Flags:
Instruction
Format:
,-_D_P_c_o_d_e"'-...J1
! src
dst
I
!L-__R_A_ _-,
Cycles
Opcode
(Hex)
16/18*
C2
Addressing Mode
dst
src
r
Ir
* 18 if jump taken, 16 if not
Example:
If working
contains
register 3 contains %AA, working register 5 contains %10, and register %10
the statement
~,AA,
CPIJE R3,ijR5, $
puts the value %11 in working register 5 and then executes the same instruction again.
CPIJNE
Compare Increment and Jump on Non Equal
CPIJNE
dst,src,RA
Operation:
If dst - src ; zero, PC _- PC + RA
Ir ..... - Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result
is not 0, the relat i ve address is added to the Program Counter and cont rol passes to the
statement whose address is now in the Program Counter; otherwise the instruction following
the CPIJNE instruction is executed. In either case, the source pointer is incremented by
one before the next instruction.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
!.-_o_pc_o_d_e_..J1
I src
dst
I I. I__R_A_--,
16/18* .
Addressing Mode
dst
src
02
Ir
* 18 if jump taken, 16 if not
Exemple:
If working
register 3 contains %M, working register 5 contains %10, and register %10
contains %AA, the statement
CPIJNE R3,@R5,$
puts the value %11 in working register 5 and then executes the next instruction following
this instruction.
Note:
The $ refers to the address of the first byte of the instruction currently being executed.
513
DEC
Decrement
DEC dst
Ope~ation:
dst
40-
dst - 1
The content.s of the destination operand are decremented by one.
flags:
C:
Z:
V:
5:
H:
0:
Unaffected
Set if the result is 0; 'cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if result is negative; cleared otherwise.
Unaffected
'
Unaffected
Inst~uction
ro~
..at:
Opeade
(Hex)
L-_o_pc_o_d_e__~1
I~
__
d_s_t__~
6
00*
01
Add~essing
Mode
dst
R
IR
*This format is used in the example.
Example:
If working register 10 contains
1~2A,
the statement
DEC R10
leaves the value %29 in that register.'
514
DECW
Decrement Word
[)£CII
dst
Operation:
dst .. - dst - 1
The cont.ents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value which is decremented by one.
Flags:
C:
Z:
V:
5:
H:
0:
Unaffected
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if the result is negative; cleared otherwise.
Unaffected
Unaffected
Instruction
Format:
~_o_p_c_o_d_e__~1
I,_____
d_s_t__~
10
Opcode
(Hex)
Addressing Mode
dst
80
RR
1R
81 *
*This format is used in the example.
EX8IIIple:
If working register a contains %30(48 decimal) and registers 48-49 contain the value %FAF3,
the statement
DECW
~RO
leaves the value
~~FAF2
in registers 48 and 49.
DI
Disable Interrupts
01
Operation:
SMR (0) .. -
a
Bit a of control register 222 (the System Mode register) is cleared to O. All interrupts
are disabled; they can still set their respective interrupt status latches, but the CPU will
not directly service them.
>
Flags:
No flags affected
Instruction
ForlQat:
Opcode
(Hex)
Opcode
6
8F
Example:
If control register 222 contains ?m1, that is, interrupts are enabled, the statement
D1
sets control register 222 to laO, disabling all interrupts.
515
Divide (Unsigned)
DIY dst,src
Operation:
dst ... src
dst (UPPER) ~- REMAINDER
dst (LOWER) ~- QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient
(8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored
in the upper half of the destination. When the quotient is~28, the numbers stored in the
upper and lower halves of the destination for quotient and remainder are incorrect. 80th
operands are treated as unsigned integers.
Flags:
C:
Z:
V:
5:
H:
D:
Set if V is set and quotient is between 28 and 29 - 1; cleared otherwise.
Set if divisor or quotient = 0; cleared otherwise.
Set if quotient is ~,28 or divisor = 0; cleared otherwise.
Set if MSB of quotient = 1; cleared otherwise.
Unaffected
Una ffected
Instruction
format:
,Opcode
II
src
II
dst
Cycles
Opcode
(Hex)
28/12*
2B/12*
2B/12* '
94**
95
96
Addressing Mode
dst
!!!:£
RR
RR
RR
R
IR
If~
* 12 if divide by zero is attempted
** This format is used in' the' example
EX8lllple:
I f working register pair 6-7 (dividend') contains %10 in register 6 and %03 in register 7,
and working register 4 (divisor) contains %40, the statement
DIV RR6,R4
leaves the value %40 in working register 7 (quotient) and the value
6 (remainder).
516
~OO3
in working register
DJNZ
Decrement and Jump if Nonzero
DJNZ
r,dst
Operation:
r __ - r -1
If r 'I 0, PC - - PC + dst
The working register being used as a counter is decremented.
If the contents of the
register are not 0 after decrementing, the relative address is added to the Program Counter
and control passes to the statement whose address is now in the Program Counter. The range
of the relative address is +127 to -128, and the original value of the Program Counter is
taken to be the address of the instruction byte following the DJNZ statement.
When the
working register counter reaches zero, control falls through to the statement following the
DJNZ statement.
Flags:
No flags affected
Instruction
Format:
Dpcode
(Hex)
Cycles
r
I
Opcode
I
dst
12 if jump taken
Addressing Mode
dst
rA
r = 0 to F
RA
10 if jump not taken
EXBJllple:
DJNZ is typically used to control a "loop" of instructions. In this example, 12 bytes are
moved from one buffer area in the register file to another. The steps involved are:
a Load 12 into the counter (working register 6)
o Set up the loop to perform the moves
o End the loop with DJNZ
LOOP:
LD R6,1I12
LD R9,OLDBUF (R6)
LD NEWBUF (R6),R9
DJNZ R6,LOOP
!Load Counter!
!Move one byte to!
!New location!
!Decrement and !
!Loop until counter
O!
Note:
The working register being used as a counter must be one of the registers OO-CF.
of the 1/0 ports, control or peripheral registers will have undefined results.
Using one
517
EI
Enable Interrupts
El
Operation:
SMR (O) -+- 1
Bit 0 of control register 220 (the System Mode register) is set to 1. This allows any
interrupts to be serviced when they occur (assuming they have highest priority) or, if their
respective interrupt status latch was previously enabled by its interrupt, then its
interrupt can also be serviced.
Flags:
No flags affected
Instruction
Forllat:
Opcode
(Hex)
Opcode
6
9F
Example:
If control register 222 contains 1~OO, (I.e., interrupts are disabled), the statement
EI
sets control register 222 to
1~01,
enabling all interrupts.
ENTER
Enter
ENTER
Operation:
SP
~SP
IP
PC
IP :
-------
....- SPPCIP -
2
'iiIP
IP + 2
This instruction is useful for the implementation of threaded-code languages. The contents
of the Instruction Pointer are pushed onto the stack. The value in the Program Counter is
then transferred to the Instruction Pointer.
The program memory word painted to by the
Instruction Pointer is loaded into the Program Counter. The Instruction Pointer is then
incremented by two.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
Opcode
518
20
1F
ENTER
Enter (Continued)
EX8IIple:
Before
~----------~---+----------~. After
Address .--____,Dat a
Address .--____-, Data
1F
01}
10
IPI 0050 1
IP~043 40
~
PC 100401
ENTER
41 Addr H
42 Addr l
43 Addr H
S 100221
~~
Memory
20 IPH 00
IPl 50
22 Data
Address
Data
Stack
Address~Data
~------+--21
Stack
EXIT
Exit
EXIT
Operation:
IP
SP
PC
IP
... ... ... .... -
!lSP
SP + 2
IiIIP
IP + 2
This instruction is useful for the implementation of ' threaded-code languages. The stack is
POPed and the Instruction Pointer is loaded. The program memory word pointed t.o, by the
Instruction Pointer is loaded into the Program Counter. The Instruction Pointer is then
incremented by two.
Flags:
No flags affected
Instruction
Format:
Opcode
Cycles
Opcode
(Hex)
22
2F
519
EXIT
Exit (Continued)
Example:
Before
After
Address .-_ _..,Data
IP
I
pcl
Address
I
0050
IP
0140
pcl
~
140 EXIT
00~2
0060
1..-/"
Data
Main
I
2f
Memory
Memory
( 2 0 Dold
} OO}
21 IPL
50
22 Oata
Address
Stack
Oata
Address
Stack
Oata
Note:
The examples for ENTER, EXIT, and NEXT illustrate how these instructions could actually be
used together in a program. '
INC
Increment
INC dst
Operation:
dst _- dst + 1
flags:
C:
Z:
The contents of the destination operand are incremented by one.
Unaffected
Set if the result is 0; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
H: Unaffected
0: Unaffected
Instruction
for_t:
Opcode
Cycles
dstlOPcodel
Opcode
II
_ dst
(Hex)
Addressing Mode
dst
6
rE*
r =,0 to f
r
6
20
21
R
IR
*This format is'used in the axample.
Example:
If working register 10 contains r,2A, the statement
INC R10
leaves the value r,2B in that register.
520
INCW
Increment Word
INC" dsl
Operation:
dst _- dst + 1
The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value which is incremented by one.
Flags:
C:
Z:
V:
S:
H:
D:
Unaffected
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if the result is negative; cleared otherwise.
Unaffected
Unaffected
Instruction
Format:
(Hex)
Addressing Mode
dst
AO*
A1
RR
IR
Opcode
~_o_pc_o_d_e__~1 I~
___
d_s_t__~
10
*This format is used in the example.
If working register pair 0-1 contains the value %FAF3, the statement
INCW RRO
leaves the value %FAF4 in working register pair 0-1.
521
IRET
Interrupt Return
Operation:
IRET (Normal)
IRET (fast)
Flags -+- @SP
SP _- SP + 1
PC _- !!SP
SP _- SP + 2
PC __ IP
Flag _- Flag'
SYM(O)
FIS _- 0
-.- 1
This ,instruction is issued at the end of an interrupt service routine. It restores the Flag
register and t.he Program Counter. It also reenables global interrupts.
Normal IRET is executed only if the Fast Interrupt Status bit (nS, bit 1 of the Flags
register R2Ul is cleared. Fast IRET is executed if FrS is set, indicating that a fast
interrupt is being ser,viced.
flags:
All ,flags are restored to original settings (before interrupt occurred).
Instruction
format:
IRET (Normal)
Cycles
Opcode
(Hex)
Opcode
16
BF
IRET (fast)
Cycles
Opcode
(Hex)
Opcode
6*
BF
*This format is used in the example.
EXalllple:
In the figure below, the Instruct ion Pointer is initially loaded with %100 in the main
program before interrupts are enabled. When an interrupt occurs, the Program Counter and
Instruction Pointer are swapped. This causes the Program Counter to jump to address %100
and the Instruction Pointer to keep the return address. The last instruction in the service
routine normally is a Jump to !RET at address %FF. This causes the Instruction Pointer to
be loaded with %100 "again" and the Program Counter to jump back to t.he main program. Now
the next, interrupt can occur and the Instruction Pointer is still correct at %100.
0
FF IRET
100
Interrupt
Service
Routine
JP1; to FF
FFFF
Note:
for the Fast Interrupt example above, if the last instruction is not a Jump to IRET, then
care must be taken with the order of the last two instructions. The instruction IRET cannot
be immediately preceded by a clear of interrupt status (such as a reset of the Interrupt
Pending register/.
522
JP
Jump
JP
JP
e.e.,dst
dst
Operation:
If e.e. is true, PC
4P-
dst
The e.onditional Jump transfers program e.ontrol to the destination address if the e.ondition
spee.ified by "e.e." is true; otherwise, the instrue.tion following the JP instruction is
exee.uted. See section 5.3 for a list of e.ondition codes.
The unconditional Jump simply replaces the contents of the Program Counter with the contents
of the specified register pair. Control then passes to the statement addressed by the
Program C~unter.
Flags:
No flags affected
Instruction
ForlllBt:
Opc:ode
Cycles
Conditional
Um:onditional
cc
IOpcode I ."I_____ds_t______'
~_o_pc_o_d_e__
_'I ~I___
d_s_t__--,
10/12*
10
(Hex)
Addressing Mode
dst
ccD**
cc = 0 to F
DA
30
IRR
*12 if jump taken, 10 if not
**This format is used in the example.
Example:
If the Carry flag is set to 1, the statement
JP t,:II1520
replaces the contents of the Program Counter with :111520 and transfers control to that
location.
Had the Carry flag not been set, e.ontrol would have fallen through to the
statement following the JP.
523
JR
Jump Relative
JR
cc ,dst
Operation:
If cc is true, PC -+- PC + dst.
If the condition specified by "ee" is true, the relative address is added to the Program
Counter and control passes to t.he statement whose address is now in the Program Counter;
ot.herwise, the instruction following the JR instruction is execut.ed. (See section 5.3 for a
list of condition codes.) The range of the relative address is +127, -12B, and the original
value of the Program Count.er is taken to be the address of the first instruct ion byte
following the JR statement.
Flags:
No flags affected
Instruction
Format:
Opcode
Cycles
cc iOPcodei
dst
10/12"
(Hex)
Addressing Mode
dst
ccB
ee = 0 to F
RA
" 12 if jump taken, 10 if not
EXlllllple:
If the result of the last arithmetic operation executed is negative, then the four following
statements (which occupy a total of seven bytes) are skipped with the statement
JR MI,$+9
If the result is not negative, execution continues with the statement, following the JR.
short form of a jump to label LO is
A
JR LO
where LO must be within t.he allowed range. The condit ion code is "blank" in this case, and
JR has the effect of an unconditional JP instruction.
Note:
The $ refers to the address of the first byte of the instruction currently being executed.
524
lD
Load
LD
dst,src
Operation:
dst _- src
The contents of the source are loaded into the destination.
unaffected.
Flags:
The contents of the source are
No flags affected
Instruction
Format:
Opcode
dst10PcodeI
src
srclOPcodel
dst
Opcode
dst I
~rc
Addressing Mode
src
~
Cycles
(Hex)
6
6
rC
r8
r
r
R
6
r9
r=O to F
R
r
6
6
C7
07
r
lr
lr
1M
Opcode
src
dst
10
10
E4
E5
R
R
R
lR
Opcode
dst
src
10
10
E6
06
R
IR
1M
1M
Opcode
src
dst
10
F5
lR
R
Opcode
dst
src
x
10
87
r
x(r)
Opcode
src
dst
x
10
97*
x(r)
r
*This format is used in the example.
Example:
If working register 0 contains %08 (11 decimal) and working'register 10 contains %83, the
statement
LO 240 (RO),R 10
loads the value %83 into register 251 (240 +11).
unaffected by the load.
The contents of working register 10 are
525
LOB
Load Bit
lOB
LOO
dst,src,b
dst,b,src
Operation:
dst(O)
~-
src(b)
or
dst(b)
~-
src(O)
The specified bit of the source is loaded into bit 0 of the destination, or bit 0 of the
source is loaded into the specified bit of the destination.
No other bits of the
dest'inat ion are affected. The source is unaffected.
Flags:
No flags affected
Instruction
format:
Opcode
Opcode
II
II
dst
b
src
b
1°1
111
I
I
Addressing Mode
Cycles
Opcode
(Hex)
..!!:!!,.
.!!!£
src
10'
47
ro
Rb
dst
10
47
Rb
ro
I f working register '3 contains 1mO and working register 5 contains %rF, the statement
LOB R3,R5,1I7
leaves the value
526
%01
in working register 3.
LDE/LDe
Load Memory
lDE/LDC
dst,src
Operation:
dst ..... - src
This instruction is used t.o load a byt.e from program or data memory into a working register
or vice-versa. The contents of the source are unaffected.
Flags:
No flaqs affected
Instruction
format:
Cycles
Opcode
Opcode
Opcode
Opcode
Opcode
Opcode
Opcode
Opcode
Opcode
Opcode
II
I
I
I
I
I
II
II
II
II
Opcoda
(Hex)
Addressing Marla
dst
src
dst
src
12
C3
r
src
dst
12
03**
Irr
dst
src
xs
18
E7
src
dst
xs
18
F7
I
I
dstl src*
I
srcl dst*
II
I
dst
00001
src
00001
dst
0001 1
src
0001 1
I
I
I
xs( rr)
xs( rr)
xl( rr)
x\
x1 H
20
A7
x1 L
x1 H
20
B7
x1( rr)
DA L
DAH
20
A7
r
OA L
DAH
20
87
DA
DA H
20
A7
DA H
20
L
DA L
Irr
DA
DA \ Proqram
Memory
r
DA \ Data
Memory
B7
DA
*The src or (rr) cannot use register pair 0-1.
**This format is used in the example.
Example:
I f the working register pair 6-7 contains %404A and working register 2 contaills %22, the
statement
LDE
~RR6,R2
will load the value
~~22
into data memory locat ion
~~404A.
Note:
LDE refers to data memory.
LDC refers to program memory.
The assembler makes Irr or rr even for program memory and odd for data memory.
example above, the assembler produces this code: D3 27.
In the
527
LDED/LDCD
Load Memory and Decrement
LDEO/LDCD
dst,src
Operation:
dst ~- src
rr _- rr -1
This instruction is used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working
register pair.
The content.s of the source location are loaded into the destination
location.
The memory address is then decremented.
The contents of the source are
unaffected.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
L-_D_Pc_O_d,-e_..J11 dst
src
16
Addressing Mode
dst
src
E2
Irr
Example:
If working register pair 6-7 contains %3DA3 and data memory locations %30A2 and
contain %22BC, the statement
?~3DA3
lOED R2, ijRR6
loads the value ?mC into working register 2 and the value %30A2 into working register pair
6-7. A second statement
lOED R2, !lRR6
loads the value %22 into working register 2 and the value %30A 1 into working register pair
6-7.
Note:
lOEO refers to data memory.
lOCO refers to program memory.
The assembler makes Irr even for program memory and odd' for data memory.
above, the assembler produces this code: E2 27.
In the example
This instruction is the equivalent of a PDPUD with the stack in memory rather than in the
register file.
528
lDEl/lDCI
Load Memory and Increment
lOEI/lDCI
Operation:
dst,src
dst
~-
src
rr
<1--
rr +
This instruction is used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working
register pair.
The contents of t.he source location are loaded into the destinat ion
location. The memory address is then incremented automatically. The contents of the source
are unaffected.
flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
,--_o_pc_o_d_e_....J1
I
dst
src
16
Addressing Hode
dst
src
Irr
E3
Example:
If working register pair 6-7 contains %30A2 and program memory locations
contain %22BC, the statement
LOCI
~nOA2
and %30A3
R2,~RR6
loads the value %22 into working register 2, and working register pair 6-7 is incremented
to %30A3. A second
lOCI
R2,~RR6
loads the value %BC into register 2, and working register pair 6-7 is incremented to %30A4.
Note:
lOEI refers to data memory.
LOCI refers to program' memory.
The assembler makes Irr even for program memory and odd for data memory.
above, the assembler produces this code: E3 26.
In the example
This instruction is the equivalent of a POPUI with the stack in memory rather than the
register file.
529
LDEPD/LDCPD
Load Memory with Pre-Decrement
lDEPD/LDCPO dst,src
Operation:
rr
~-
rr -
dst +- src
This instruct ion is used for block transfers of data to program or data memory from the
register file.
The address of the memory location is specified by a working regist.er pair
and is first decremented.
The contents of the source location are loaded into the
destination location. The contents of the source are unaffected.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
-JI I I I
~_o_p_c_o_d_e__
src
16
dst
F2
Addressing Hode
dst
src
Irr
Ex .... ple:
If working\ register pair
decimal), the statement
6-7
contains
1~404B
and ,working
register
2 contains %22
(34
LDEPD !lRR6,R2
loads the value %22 into data memory
register pair 6-7.
Iocation%404A and the value %404A into working
Note:
LDEPD refers to data memory.
LDCPD refers to program memory.
The assembler makes Irr even for program memory and odd for data memory.
This instruction is the equivalent of' a PUSHUD with the stack in memory rather t.han the
register file.
530
lDEPUlDCPI
Load Memory with Pre-Increment
LD£PI/lOCPI
Operation:
dst,src
rr
... - rr +
dst .... - src
This instruction is used for block transfers of data to program or data memory from the
register file. The address of the memory location is specified by a working register pair
and is first incremented.
The contents of the source location are loaded into the
destination locat ion. The content.s 'of the source are unaffected.
Flags:
No flags affected
Instruction
format:
Opcode
(Hex)
,-_D_P_c_o_d_e_..J1
I
src
dst
16
F3
Addressing Mode
dst
src
Irr
Example:
I f working register pair 6-7 contains %404A and working
decimal), the statement
LDEP I
~RR6,
register 2 contains
~,22
(34
R2
loads the value ~,22 into external data memory location %4048 and the value
working register pair 6-7.
~,404B
into
Note:
LDEPI refers to data memory.
LDCPI refers to program memory.
The assembler makes Irr even for program memory and odd for data memory.
This instruction is the equivalent of a PUSHUI with the stack in memory rather than the
regist.er file.
531
LOW
Load Word
LDII dst,src
Operation:
dst
-+-
src
The contents of the source (a word) are loaded into the destination.
source are unaffected.
flags:
The contents of the
No flags affected
Instruction
format:
Opcode
Opcode
II
II
src
dst
II
II
Cycles
Opcude
(Hex)
10
10
C4
C5
RR
RR
RR
IR
12
C6*
RR
IHL
dst
I
src
Addressing Hode
dst
.:!!£
*This format is used in the example.
Example:
If the source operand is the immediate value %5AA5, the statement
LDW RR6,11%5AA5
leaves the value %SA in working register 6 and the value %A5 in working register 7.
MUlT
Multiply (Unsigned)
Hl"-T
dst,src
Operation:
dst
~-
dst x src
The 8-bit dest inat ion operand (even register of the register pair) is multiplied by the
source operand (8 bits) and the product (16 bits) is stored in t.he register pair' specified
by the destination address. Both operands are treated as unsigned integers.
flags:
C:
Z:
V:
5:
H:
D:
Set if result is > 255; cleared otherwise.
Set if the result is 0; cleared otherwise.
Cleared
Set if MSB ~f the result is a 1; cleared ,otherwise.
Ul;laffected
Unaffected
Instruction
format:
Cycles
Opcode
II
src
II
dst
Opcode
(Hex)
24
24
24
*This format
Addressing Hode
dst
src
84*
RR
R
85
RR
IR
86
RR
1M
is used in the example.
Example:
If working register 6 contains
decimal), the statement
~,40
(64 decimal) and working register 4 contains %42 (66
MULT RR6, R4
leaves the value %10 in working register 6 and
decimal) •
532
~,80
in working register 7 (%1080 is 4224
NEXT
Next
NEXT
PC . - !:1IP
IP .... - IP + 2
Operation:
This inst ruction is useful for the implement.ation of threaded-code languages. The program
memory word pointed to by the Instruct ion Pointer is loaded into the Program Counter. The
Instruction Pointer is then incremented by two.
No flags affected
Flags:
Instruction
Format:
Opcode
(Hex)
Opcode
14
OF
Example:
BeFore
AFter
Address
Data
Addr H 01 }
44 Addr L 30
45 Addr H
~"
43 Addr H
44 Addr L
Addr H
IP 0043
IP ~45
0045
.
~~
~~
120 NEXT
Memo,y
Data
Address
130 Routine
Memory
Note:
The examples for ENTER, EXIT, and NEXT illustrate how they could actually be used together
in a program.
533
NOP
No Operation
Operation:
No action is performed by this instruction.
flags:
It is typically used for timing delays.
No flags affected
Instruction
Format:
Opcode
(Hex)
Opcode
FF
OR
Logical OR
OR
dst,src
Operation:
dst
~-
dst OR src
Tl),e source opera"nd is logically ORed, with the destination, operand and the result is stored
in the destination.' The contents of the source are unaffected. The OR operation results in
a 1 bit being stored whenever either of the corresponding bits in the two operands is 1;
otherwise a 0 bit is stored.
flags:
C:
Z:
V:
S:
H:
D:
Unaffected
Set if the result is 0; cleared otherwise.
Always cleared to 0
'
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
Format:
Opcode
II
Opcode
II
II
Opcode
dst
src
src
dst
I
II
II
Cycles
Opcode
(Hex)
.!!!!..
~
6
6
42
43
r
r
r
Ir
dst
10
10
44
45
R
R
R
IR
src
10
46*
R
1M
Addressing Mode
*This format is used in the example. '
Exaiaple:
If the source operand is the immediate value 1,;7B (01111011) and the register named TARGET
contains 1,;C3 (11000011), the statement
OR TARGET, !/'If,7B
leaves the value %FB (11111011) in register, TARGET.
534
POI?
Pop
POP
dst
Operation:
dst _- @SP
SP _- SP ...
The contents of the' location addressed by the Stack
destination. The Stack Pointer is then incremented by one.
Pointer
are
loaded
into
the
No flags affected
Flags:
Instruction
Format:
Opcode
,--_o_p_c_o_d_e_....I1
Cycles
(Hex)
10
10
50
51·
''--__d_s_t_--'
Addressing Hade
dst
R
IR
*This format is used in the example.
Example:
I f the Stack Pointer (control registers 216-217) contains ~~1000, external data memory
location %1000 contains %55, and working register 6 cont,ains %22 (34 decimal), the statement
POP @!R6
loads the value
%1001.
?~55
into register 34.
After the POP operation, the Stack Pointer contains
IPOpuro
POp User Stac!{ (Decrementing)
POPIJD
dst,src
Operation:
dst _- src
IR ... - IR This instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user Stack Pointer are loaded into the destination.
The user Stack Pointer is then decremented.
Flags:
No flags affected
Instruction
Format:
Opcode
I,
src
I,
Cycles
Opccde
(Hex)
10
92
dst
Addressing Hode
dst
src
R
IR
Example:
I f the user Stack Pointer (register ~~42, for example) contains ~~80 and register ~~BO contains
5A, the statement
POPUD
R2,~42
loads the value %5A into working register 2.
Pointer contains ~~7F.
After
the POP operation,
the user Stack
535
POPUI
Pop User Stack (Incrementing)
POPUI
dst,src
Operation:
dst .. - src
IR _- IR +
This instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user Stack Pointer are loaded into the destination.
The user Stack Pointer is then incremented.
No flags affected
Flags:
Instruction
Format:
Opcode
Example:
II
src
II
Cycles
Opcode
(Hex)
10
93
dst
Addressing Mode
~
!!!:£
R
IR
If the user Stack Pointer (register 1,42, for example) contains 1,80 and register %80 contains
1,5A, the statement
POPUI
R2,~42
loads the value %5A into working register 2.
Pointer contains %81.
After the POP operation, the user Stack
PUSH
Push
PUSH
src
Operation:
SP
~SP
_- SP - 1
_- src
The contents of the Stack Pointer are decremented, then the contents of the source are
loaded into the locat ion addressed by the decremented Stack Pointer, thus adding a new
element to the top of the stack.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
Cycles
Opcode
II
src
10
12
12
14
Internal
External
Internal
External
stack
stack
stack
stack
Addressing Mode
src
70*
R
71
IR
*This format is used in the example.
Example:
If the Stack Pointer contains %1001, the statement
PUSH FLAGS
stores the contents of the register named FLAGS
operation, the Stack Pointer contains %1000.
536
in location %1000.
After the PUSH
PUSHUD
Push User Stack (Decrementing)
PUSHUD
dst,src
Operation:
IR .... - IR dst _- src
This instruction is used for user-defined stacks in the register file.
The user Stack
Pointer is decremented, then the contents of the source are loaded into the register file
location addressed by the decremented user Stack Pointer.
Flags:
No flags affected
Instruction
format:
Opcode
(Hex)
Opcode
II
dst
II
src
10
82
Addressing Mode
~
src
IR
R
Exa.-:lple:
I f the user Stack Pointer (%42, for example) contains' %81, the statement
PUSHUD 11I%42,R2
stores the contents of working register 2, in location %80.
user Stack Pointer contains %80.
After the PUSH operation, the
PUSHU~'
Push User Stack (Incrementing)
Push User Stack (Incrementing)
PUSHUI
dst,src
Operation:
IR .... - IR + 1
dst _- src
This instruction is used for user-defined stacks in the register file.
The user Stack
Pointer is incremented, then the contents of the source are loaded into the register file
location addressed by the incremented user Stack Pointer.
Flags:
No, flags affected
Instruction
format:
Ope ode
II
dst
II
src
Cycles
Opcode
(Hex)
10
83
Addressing Mode
dst
src
IR
R
Example:
If the user Stack Pointer
PUSHUI
(?~42,
for example) contains
?~81,
the statement
~%42,R2
store~ the contents of working register 2 in location %82.
user Stack Pointer contains %82.
After the PUSH 'operation, the
537
ReF
Reset Carry Flag
ReF"
Operation:
C -+- 0
The Carry flag is cleared to 0, regardless of its previous value.
Flags:
'c:
Cleared to 0
No other flags affected
Instruction
Format:
Opcode
(Hex)
Opcode
6
CF
RET
Return
RET
Operation:
PC 4-- {lSP
SP .... - SP + 2
This instruction is normally used to return to the previously executing procedure at the end
of a procedure entered by a CALL instruction. The contents of the location addressed by the
Stack Pointer are popped 'into the Program Counter.
The next statement executed is that
addressed by the new contents of the Program Counter.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
Opcode
14
AF
Example:
If the Program Counter contains %3584, the Stack Pointer contains %2000, external
data memory location ~'2000 contains %18, and location %2001 contains %85, then the statement
RET
leaves the value %2002 in the Stack Pointer and %1885, the address of the next instruction,
in the Program Counter.
538
RL
Rotate Left
Rl
dst
Operation:
C -+- dst (7)
dst (0) ..... - dst (7)
dst (n + 1) -+- dst (n) n
=0
- 6
The contents of the destination operand are rotated left one bit position.
value of bit 7 is moved to the bit 0 position and also replaces the Carry flag.
Flags:
c:
Z:
V:
5:
H:
D:
The initial
Set if the bit .rotated from the most significant bit position was 1, i.e., bit 7 was 1.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
Format:
~_o_pc_o_d_e__~1 I~___d_s_t__~
6
6
Opcode
(Hex)
Addressing Mode
~
90*
91
R
IR
*This format is used in the example.
Example:
I f the contents of the register named SHIFTER are
~m8
(10001000), the st.atement
RL SHIFTER
leaves the value ?11 (00010001) in that register and the Carry and Overflow flags are set to
1.
539
RLe
Rotate Left Through Carry
RlC
dst
Operation:
dst (0) _- C
C 4 - - dst (7)
dst (n + 1) _- dst (n) n
=0
- 6
The contents of the dest ination operand with the Carry flag are rotated left one bit
position.
The initial value of bit 7 replaces the Carry flag; the initial value of the
Carry flag replaces bit O.
~~7
Flags:
_p
C:
Set if the bit rotated from the most significant bit position was 1, i.e., bit 7 was 1.
V:
Set if arithmetic overflow occurred, that is, if the- sign of the destination changed
during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Z: Set if the result is 0; cleared otherwise.
5:
H:
0:
Instruction
Format:
Opcode
(Hex)
I
Opcode
I 1L.__d_s_t_--l
6
6
10*
11
Addressing Mode
dst
R
IR
*This format is used in the example.
Example:
If the Carry flag is cleared to 0 and the register named SHIfTER contains %8F (10001111),
the statement
RLC SHIFTER
sets the Carry and Overflow flags to 1 and leaves the value %1E (00011110) in SHIFTER.
540
RR
Rotate Right
RR
dst
Operation:
C _- dst (0)
dst (7) .... - dst (0)
dst (n) .... - dst (n + 1) n
=0
- 6
The contents of the destination operand are rotated right one bit position.
value of bit 0 is moved to bit 7 and also replaces the Carry flag.
Flags:
c:
Z:
V:
S:
H:
0:
The initial
Set if the bit rotated from the least significant bit position was 1, i.e., bit 0 was 1.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the sign of the destination changed
during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
format:
Opcode
(Hex)
L-_o_pc_o_d_e__~1
~I
___
d_s_t__~
6
6
Addressing Hode
dst
EO*
R
E1
IR
*This format is used in the example.
Example:
If the contents of register 6 are %31 (00110001), the statement
RR R6
sets the Carry flag to 1 and leave the value %98 (10011000) in working register 6.
bit 7 now equals 1, the Sign and Overflow flags are also set to 1.
Since
541
RRC
Rotate Right Through Carry
RRC
dst
Operation:
dst (7) .... - C
C .... - dst (0)
dst (n) .... - dst (n + 1) n
=0 - 6
The content.s of the destination operand and the Carry flag are rotated right one bit
position.
The initial value of bit 0 replaces the Carry flag; the initial value of the
Carry flag replaces bit 7.
Flags:
C:
Set if the bit rotated from t.he least significant bit position was 1, i.e., bit 0 was 1.
Z: Set if the result is 0; cleared otherwise.
V:
5:
H:
D:
Set if arithmetic overflow occurred, that is, i f the sign of the destination changed
during rotation; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
Format:
Opcode
(Hex)
~_o_pc_o_d_e_....J1
',--_d_s_t_--,
CO*
6
6
C1
Addressing Mode
dst
R
IR
*This format is used in the example.
[xllftlple:
If the content.s of the register named SHIFTER are %OD (11D11101), and the Carry flag is
cleared to 0, the statement
RRC SHIFTER
sets the Carry and Overflow flags to 1 and leaves the value
542
~;6E
(01101110) in the register.
SSO
Set BankO
580
Operation:
BANK -+- 0
This instruction causes the Bank Address flag (bit 0) of Flag register 213 to be cleared to
O.
Flags:
No flags affected
Instruction
Format:
Opcode
(Hex)
Opcode
6
4F
SB1
Set Bank 1
581
Operation:
BANK -+- 1
This instruction causes the Bank Address flag (bit 0) of Flag register 213 to be set to 1.
Flags:
No flags affected
Instruction
format:
Opcode
(Hex)
Opcode
6
SF
543
SSC
Subtract With Carry
soc
dst,src
Operation:
dst
~-
dst - src - C
The source operand, along with the setting of the Carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source
are unaffected.
Subtraction is performed by adding the twos complement of the source
operand to the destination operand.
In multiple precision arithmetic, this instruction
permits the carry ("borrow") from the subtraction of low-order operands to be subtracted
from the subtraction of high-order operands.
Flags:
C:
Z:
V:
S:
H:
D:
Set if a borrow occurred (src > dst); cleared otherwise.
Set if the result is 0; cleared otherwise.
,
Set if arithmetic overflow occured, that is, if the operands were of opposite sign and
the sign of the result is the same as the sign of the source; cleared otherwise.
Set if the result is negative; cleared otherwise.
Cleared if there is a carry from the most. signi ficant bit of the low-order four bits of
the result; set otherwise, indicating a "borrow."
Always set to 1.
Instl'uction
format:
Cycles
Opcode
Opcode
Opcode
II
II
II
dst
src
src
dst
I
II
II
Opcode
(Hex)
Addressing Hode
dst
src
6
6
32
33"
r
r
Ir
dst
10
10
34
35
R
R
R
IR
src
10
36
R
1M
"This format is used in the example.
EX8IIple:
If the register named MINUEND contains %16, the Carry flag is set to 1, working register 10
contains ~;20 (32 decimal), and register 32 contains ~m5, the statement
SBC MINUEND,
leaves the value
544
~R10
~;10
in register MINUEND.
selF
Set Carry Flag
SCf
Operation:
C ..... - 1
The Carry flag is set to 1, regardless of its previous value.
flags:
- C:
Set to 1
No other flags affected
Instruction
forlll8t:
Opcode
(Hex)
Opcode
6
OF
SfRA
Shift Right Arithmetic
SRA dst
Operation:
dst (7) ..... - dst (7)
C ...... - dst (0)
dst (n) ..... - dst (n + 1) n = 0 - 6
An arithmetic shift right one bit position is performed on the destination operand. Bit 0
replaces the Carry flag. Bit 7 (the sign bit) is unchanged, and its value is also shifted
into bit position 6.
7
flags:
C:
6
Set if the bit shifted from the least significant bit position was 1, i.e:, bit 0 was 1.
Z: Set if the result is 0; cleared otherwise.
V:
S:
H:
Always cleared to 0
Set if the result is negative; cleared otherwise.
Unaffected
D:- Unaffected
Instruction
format:
Opcode
(Hex)
~_o_p_co_d_e__~1
d_s_t__~
LI_ _ _
6
6
OO*'
01
Addressing Mode
dst
R
IR
*This format is used in the example.
Example:
If the register named SHIFTER contains %B8 (10111000), the
s~atement
SRA SHIFTER
clears the Carry flag to
Sign flag is set to 1.
0
and leaves the value %OC (11011100) in the register-SHIFTER.
The
545
SRP/SRPO/SRP1
Set Register Pointer
SRP/SRPO/SRP1
src
Operation:
If src (1)
If src (1)
If src (1)
=1
=0
=0
..
..
and src (0)
=0
them
RPO (3-7)
and src (0 )
=1
=0
then:
RP1 0-7)
then:
RPO (4-7) .. - src (4-7),
RPO (3) . .- 0
RP1 (4~7) .. - src (4-7),
RP1 (3) .. - 1
and src (0)
- src 0-7 )
- src (3-7)
The source data bits 1 and 0 determine if one or both of the Register Pointers is to be
written.
Bits 3-7 of the selected Register Pointer are written unless both Register
Pointers are selected. Then bit 3 of RPO is forced to a 0 and bit 3 of RP1 is forced to a
1.
Flags:
No flags affected
Instruction
Format:
~_o_pc_o_d_e__~1 I~
___
s_r_c__
~
6
Examples:
(1) The statement
SRPO
11~~50
sets Register Pointer 0 (control register 214) to ~~50.
The assembler produces this code: 31 52.
(2) The statement
SRP1 11%68
sets Register Pointer 1 (control regist~ 215) to ~~68.
The assembler produces this code: 31 69.
(3) The statement
SRP 11%40
sets Register Pointer 0 to ~~40 and Register Pointer 1 to
The assembler produces this code: 31 40.
546
~~4B.
Opcode
(Hex)
Addressing Mode
src
31
1M
SUB
Subtract
SUB
dst,src
Operation:
dst
~-
dst - src
The source operand is subtracted from the destination operand and the result is st.oreej in
the destination. The contents of the source are unaffected. Subtraction is performed by
add{ng the twos complement of the source operand to the destination operand.
flags:
C:
Z:
V:
5:
H:
0:
Set if ,a "borrow" occurred; cleared otherwise.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occured, that is, if the operands were of opposite signs and
the sign of the result is the same as the sign of the source operand; cleared otherwise.
Set if the result is negative; cleared otherwise.
Cleared if there is a carry 'from the most significant bit of the low-order four bits of
the result; set otherwise indicating a "borrow."
Always set to 1.
Instruction
Format:
Opcode
Opcode
Opcode
II
II
II
dst
src
src
dst,
I
II
II
dst
src
Cycles
Opcode
(Hex)
Addressing Hode
dst
src
6
6
22
23
r
r
r
Ir
10
10
24
25
R
R
R
10
26*
R
1M
IR
*This format is used in the example.
Example:
If the register named MINUEND contains %29, the statement
SUB MINUEND, #%11
leaves the value %18 in the register.
547
SWAP
Swap Nibbles
SlfAP- dst
Operation:
dst (0 - 3)
~~
dst (4 - 7)
The contents of the lower four bits and upper four bits of the destination operand are
swapped.
7
Flags:
4 3
o
c:
Undefined
5:
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Z: Set if the result is 0; cleared otherwise.
V: Undefined
H:
0:
Instruction
Format:
Opcode
(Hex)
~_o_pc_o_d_e__~1 I~
___
d_s_t__~
Addressing Mode
dst
8
FO"
R
8
F1
IR
"This format is used in the example.
Exaaople:
If the register named BCD_Operands co,ntains %B3 (10110011), then t.he statement
SWAP BOC_Operands
leaves the value %3B (00111011) in the
548
r~gister.
TCM
Test Complement Under Mask
TCH
dst,src
Operation:
(NOT dst) ANO' src
This instruct ion tests selected bits in the dest inat ion operand for a logical "1" value.
The bits to be tested are specified by setting a 1 bit in the corresponding position of the
source operand (mask). The TCM statement complements the de,stination operand, which is then
ANDed with the' source mask. The Zero (Z) flag can then be checked to determine the result.
The destination and source operands are unaffected.
Flags:
Unaffected
Set if the result is 0; cleared otherwise.
V: Always cleared to O. '
S:' Set if the result bit 7 is set; cleared otherwise.
H: Unaffected
0: Unaffected
C:
Z:
Instruction
ForllBt:
Opcode
Opcode
Opcode
II
I I'
II
dst
src
src
dst
II
II
dst
src
Cycles
Opcode
(Hex) \
Addressing Mode
~
!!£
6
6
62*
63
r
r
r
Ir
10
10
64
65
R
R
R
IR
10
66
R
1M
*This format is used in the example.
Example:
If the register named TESTER contains ror6 (11110110) and the register named MASK contains
%06 (00000110), that is, bits 1 and 2 are being tested for a 1 value, then the statement
TCM TESIER, MASK
complements TESTER (to 00001001) and then does a logical AND with register MASK, resulting
in %00. A subsequent test of the Z flag
JP Z, label
causes a transfer of program control.
At the end of this sequence, TESTER still contains
%F6.
549
TM
Test Under Mask
1M
dst,src
Operation:
dst ANO src
This instruction tests selected 'bits in the destination operand for a logical "0" value.
The bits to be tested are specified by setting a 1 bit in the corresponding position of the
source operand (mask), which is ANOed with the destination operand. The Zero (Z) flag can
The destination and source operands are
then be checked to determine the result.
unaffected.
Flags:
C:
Z:
V:
5:
H:
D:
Unaffected
Set if the result' is 0; cleared otherwise.
Always reset to O.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Instruction
Format:
Opcode
Opcode
Opcode
II
II
dst
II
src
src
dst
I
II
II
dst
arc
Cycles
Opcode
(Hex)
Addressing Mode
dst
!!£.
6
6
72*
73
r
r
r
Ir
10
10
74
75
R
R
R
10
76
R
1M
IR
*This format is used in the example.
Example:
If the register named TESTER contains r.r6 (11110110) and the register named MASK contains
%06 (00000110), that is, bits 1 and 2 are being tested for a 0 value, then the state,ment
TM TESTER, MASK
results in the value %06 (00000110).
A subsequent test for nonzero
JP NZ, label
causes a,transfer of program control.
,%F6.
550
At the end of this sequence, TESTER still,contains
WFI
Wait For Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers still
take place in the halt state. Either a fast interrupt or normal interrupt can take the CPU
out of the halt state.
Flags:
-No flags affected
Instruction
format:
Opcode
(Hex)
Opcode
6n
n
3F
= 1,2,3, •••
Example:
Main Program
(Enable Global Interrupt)
(Wait for Interrupt)
EI
WFI
(next instruction)
~nterrupt
occurs
Interrupt Service Routine
Clear Interrupt Flag
IRET
serv ice routine
551
XOR
Logical Exclusive OR
XOR
dst,src
Operation:
dst ..-- dst XoR src
The source operand is logically EXCLUSIVE oRed, with t.he destination operand and the result
is stored in the destination. The EXCLUSIVE OR operation results in a 1 bit being stored
whenever the corresponding bits in the operands are different; otherwise, a 0 bit is stored.
Flags:
C:
Unaffected
i f the result is 0; cleared otherwise.
Always reset to o.
Set if the result bit 7 is set; cleared otherwise.
Unaffected
Unaffected
Z: Set
V:
5:
H:
0:
Instruction
Format:
opcode
opcode
opcode
II
II
II
dst
src
src
dst
I
II
II
Cycles
Opcode
(Hex)
Addressing Hode
dst
src
6
6
82
83
r
dst
10
10
84
85
R
R
R
IR
src
10
86"
R
It1
r
Ir
"This format is used in the example.
Example:
If the source is the immediate value %78 (01111011) and the register named TARGET contains
%C3 (11000011), the statement
XoR TARGE T, 1/%78
leaves the value ~m8 (10111000) in the register'.
552
ChapteB' 6
~nteB'B'upts
,6.1
INTRODUCTION
A source is anything that generates an interrupt.
This can be internal or external to the Super8.
Internal sources are hardwired to a particular vector
and level. while external sources can be assigned to
various external events. External interrupts are
flillin9 edge triggered.
The interrupt structure of the, SuperB consists of
27 different interrupt sources, 16 vectors, and B
levels (ri~ure 6-1).
Two of the vectors are
reserved for future members of the SuperB family.
Interrupt priority is assigned by level, which is
controlled by the Interrupt Priority register
(IPR). Each level is masked (or enabled) according to the bits in the Interrupt Mask register
(IMR) , and the entire interrupt structure can be
disabled by clearing bit 0 in the System Mode
register (R222).
The three major components of
the interrupt structure are sources, vectors, and
levels.
INTERRUPT SOURCES
6.1.2
The vector number is used to generate the address
of a particular interrupt serv~c~ng routine;
therefore all interrupts using the same vector
must use the same interrupt handling routine.
POliNG
VECTORS
--,--
LEVELS
! 12
COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P2,)
EXTERNAL INTERRUPT (P27)
I
COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P3,)
EXTERNAL INTEI'IRUPT (P37)
~;~~~::~,~~~~~~~i ?P2,) I
EXTERNAL INTERRUPT (P2s)
HAN'DSHAKE CHANNEL 1
EXTERNAL INTERRUPT (P3,)
EXTERNAL INTERRUPT (P3s)
Vectors
I
RESERVED
I
I
I
I
!,
IRQ2
I
I
1,4
IRQ5
I
I
I
I
IRQ4
128
I
I
I
IRQ7
130
I
!
RESERVED
IRQ3
EXTERNAL INTERRUPT (P3,)
EXTERNAL INTERRUPT (P2,)
EXTERNAL INTERRUPT (P23)
,'RQO
EXTERNAL INTERRUPT (P33)
UART RECEIVE OVERRUN
UART FRAMING ERROR
UART PARITY ERROR
UART WAKEUP DETECT
UART BREAK DETECT
UART CONTROL CHAR DETECT
IRQ6
WlRT RECEIVE DATA
EXTERNAL INTERRUPT (P3D)
EXTERNAL INTERRUPT (P2D)
UART ZERO COUNT
EXTERNAL INTERRUPT (P2,)
UART TRANSMIT DATA
EXTERNAL INTERRUPT (P3,)
I
IRQl
Figure 6-1. Interrupt Structure
553
Interrupts
When more than one vector shares an interrupt
level, the priorities of the vectors on that level
are fixed. Figure 6-1 lists the vectors within a
level in the order of decreasing priority (i.e •. ,
the top vector in each level has the highest
priority).
for example, for IRQ6, vector 16
always 'has priority over vectors 18, 20, and 22.
Although it does not cover all possible combinations, the Interrupt Priority register does
provide the capability of assigning 192 different
combinations of priority among the interrupt
levels.
for example, an IPR with the co1ntents
01101011 would have the following priority order
(Figure 6-3):
If more than one interrupt source is active, the
source from the highest priority level is serviced
first. If both sources are from the same' level,
the source with the lowest vector number has
priority. for example, if the UART Receive Data
bit and UART Parity Error bit are both active, the
UART Parity Error is serviced first because it is
vector 16 and the UART Receive Data bit is vector
20.
6.1.' levels
While the sources and vectors are hardwired within.
each level, the priorities of the levels can be
changed by using the Interrupt Priority register
(R255, Bank 0) (Figure 6-2).
R2SS BANK 0 (FF) IPR
INTERRUPT PRIORITY REGISTER
GROUP PRIORITY
I
I
I L
GROUP A
0= IROO>IROI
1 = IROI > IROO
07 0 4 0 1
UNOEFINEO
B>C>A
A>B>C
B>A>C
GROUPB
o = IR02 > (IR03,IR04)
1 = (IR03,IR04» IR02
C>A>B
SUBGROUPB
0= IR03 > IR04
1 = IR04 > IR03
C>B>A
A>C>B
UNDEFINED
GROUPC
o = IROS > (IR06,IR07)
1 = (IR06,IR07) > IROS
SUBGROUPC
o = IR06 >·IR07
1 = IR07 > IR06
Figure 6-2. Interrupt Priority Register
EXAMPLE: An IPR with thecontents01101011 would have
the following priority order:
GROUP A
AI
A2
Bl
Cl
HIGHEST
B22
IROO
IROI
IR02
IR03
IR04
C22
IROS
IR06
I
UNDEFINED
B>C>A
A>B>C
B>A>C
C>A>B
C>B>A
A>C>B
UNDEFINED
lSI
Al>A2
A2>Al
Bl>B2
B2>Bl
GROUPB
IRO?1
IR06
IROS'
GROUpe
IR01 }
, IROO
GROUPA
IR07
I~I~I~I~I~I~I~I~I
000
001
010
011
100
101
110
111
IR02 }
IR04
IR03
LOWEST
B21>B22
B22>B21
Cl>C2
1 C2>Cl
0 C21>C22
1 C22>C21
Figure 6-3, Interrupt Priority Tree
554
Interrupts
When an interrupt occura, the software is automatically vectored' to one of 16· possible service
routines. If more than one active source ahares
that vector, the software must poll the individual
sources connected with that vector to find the
interrupting source or sources. Each interrupt
source has its own Interrupt Enable bit located in
the mode and control registers of the r/o section
Table 6-1.
~B
associated with the source. The software has
complete control over which sources are allowed to
cause interrupts. If only one source associated
with a particular vector is enabled, then when an
interrupt occurs that uses that vector, no polling
is required and the software is automatically
vectored to the appropriate service routine.
Vector Address Table
Vectors
(Decilllal MeiIory Address)
Levels
30,31
IRQ7
P34 External Interrupt or HS1 /
P35 External Interrupt
28,29
IRQ4
P24 External Interrupt or HSO /
P25 External Interrupt
26,27
IRQ1
UART Transmit Data /
P31 Extern~l Interrupt
24,25
IFiQ1
22,23
IRQ6
P20 External Interrupt
20,21
IRQ6
UART Receive Data /
P30 External Interrupt
18,19
IRQ6
UART Break / Control Character /
Wake-Up
16,17
IRQ6
uAin Overrun / Framing /
Pilrity
14,15
IRQ5
Counter 1 Zero Count /
P36 External Interrupt /
,P37 External Interrupt
12,13
IRQ2
Counter 0 Zero Count /
P26 External Interrupt /
P27 External Interrupt
10,11
IRQO
P3 3 External Interrupt
,
8,9
IRQO
P23 Externsl Interrupt
6,7
IRQ3
P2 2 External Interrupt
4,5
IRQ3
P32 External Interrupt
2,3
IRQ3
Reserved
0,1
IRQ3
Reserved
Interrupt Sources
I
UART Zero Count /
P2 1 External Interrupt
555
Interrupts
6.1.4 Enables
The SuperB then enters an interrupt machine cycle
that completes the following sequence:
Interrupts can be enebled or disabled es follows:
•
•
•
Interrupt enable/disable. The entire interrupt
structure can be enabled or diaabled by aetting
bit 9 in the System Mode register (R222).
level enable. Each level can be enabled or
disabled by setting the appropriate bit in the
Interrupt Mask register (R221).
•
level priority. The priority of each level can
be controlled by the values in the Interrupt
Priority register (R255, BankO).
•
Source enable/disable. Each interrupt source
can be enabled or disabled in the source's Mode
and Control register.
Resets the Interrupt Enable bit to disable all
subsequent interrupts
e Saves the Program Counter and status flags on
the stack
•
Branches to the address contained within the
vector location for the interrupt
•
Passes control
routine
to
the
interrupt
servicing
Interrupts can be re-enabled by the interrupt
handling routine (EI instruction),' which allows
interrupt nesting. First, however, the contents
of the Interrupt Mask register should be saved and
a new mask loaded which disables the present level
being serviced and all lower levels.
6.1.5 The Interrupt Routine
Interrupts are sampled at the end of each instruction. Before an interrupt request can be granted
a) interrupts must be enabled, b) the level must
be enabled and must be the highest priority interrupting level, and c) the interrupt request must
be enabled at the interrupting source and must
have the highest priority within the level.
If all this occurs,
granted.
an
interrupt
reques~
is
When the interrupt handling routine is finished,
it should issue an Interrupt Return (IRET)
instruction.
This instruction restores the
Program Counter and status flags from the stack
and sets the Global Interrupt Enable bit.
If
nesting was used, "the interrupt handling routine
should firat execute a Disable Interrupt (01)
instruction and restore the saved mask before
executing the IRET instruction. Figure 6-4
illustrates the interrupt cycle process that
occurs when an interrupt request occurs.
- P2AIP=%FC
P2BIP= %FO
EI
HW RESET OR
POWER·UP RESET
IPR=%FF
INTERRUPT PRIORITY
REGISTER
VECTOR
INTERRUPT
CYCLE
SYM=%DE
SYSTEMMDDE
Figure 6-4. Interrupt Cycle Process
556
Interrupts
6.2
FAST INTERRIJ'T PROCESSING
The SuperB provides a feature called fast interrupt processing, which completes the interrupt
servicing in 6 clock periods instesd of the usual
22.
Anyone of the eight interrupt levels can be
programmed to use this feature by loading the fast
interrupt select field of the System Mode register
(R222) with the level number and setting the fast
Interrupt Enable bit.
Two hardware regi~ters support fast interrupts.
ThE! Instruction Pointer (IP) holds the starting
address of the service routine and saves the
Program Counter (PC) value when a fast interrupt
occurs. A dedicated register, flag', saves the
contents of the nag register when a fast interrupt occurs.
To use, this feature, software must first set the
Instruction Pointer to the starting location of
the interrupt service routine during initialization and before interrupts are enabled for the
first time. Then the level, number is loaded into
the fast Interrupt Select field and the fast
Interrupt Enable bit in the System Mode register
is turned on.
Nhen an interrupt occurs in the level selected for
fast interrupt processing, the following occurs:
II
-The contents of the Instruction Pointer and the
Program Counter are swapped.
•
The contents' of the Flag register are copied
into Flag'.
II
lhe fast Interrupt Status bit
register is set.
6.3
CLEARING THE INTERRIJ'T SOURCE
Internally, the interrupt requests are ,represented
as levels. This level-activated system requires
that the software that services an interrupt must
perform some action that removes the interrupting
source before re-enabling that interrupt.
for external interrupt inputs on the Port 2 and 3
pins, edge-triggered "interrupt pending" flipflops are used to convert an edge-triggered input
to a level-activated interrupt. Thus, the service
routine must reset the interrupt pending flip-flop
to clear the interrupt request by writing to the
Port 2/3 Interrupt pending register.
for receive character available interrupts from
the UART receiver, emptying the Receive Data
register
CUIOR)
will
automatically
clear
the interrupt aource. for receiver interrupts due
to a receive ,error, detection of a control character, or detection of the wake-up condition, resetting the appropriate status bit in the Receive
Control register CURC) will clear the interrupt
source. for interrupts from the UART transmitter,
filling the Transmit Data register (uroT) wi.ll
automatically clear the interrupt source~
for end-of-count interrupts from the counter/
timers, resetting the Reset/End of Count Status
bit (01) in the Counter Control register will
clear the interrupt source.
The interrupt is serviced.
II
When fRET is issued sfter the interrupt service
routine is completed" the Instruction Pointer
and the Program 'Counter are swapped again. '
The contents of flag' are
flag register.
The SuperB supports both polled and interruptdriven systems or a combination of both.
To
accommodate a polled structure or a partially
polled structure, any or all of the interrupt
levels can be masked and the individual bits of
the IRQ register polled.
in the Flag
•
~opied
back into the
o The fast Interrupt Status bit
register is cleared.
in the flag
•
interrupt routine. While fast interrupt processing is enabled, normal interrupt processing still
functions for the unselected levels.
for interrupts from the on-chip DMA channel, loading a non-zero value into the OMA Count register
will clear the interrupt source.
6.4
After the .Interrupt Return OREn of a fast
interrupt, the Instruction Pointer (IP) will point
to the next byte following the IRET. Before using
the fast interrupt again, the IP ahould be reinitialized to point to the beginning of the
INTERRIJ'T IDITROL REGISTERS
The interrupt hardware is controlled by fields in
the System Mode register (R222), the Interrupt
Request register IRQ (R220), the Interrupt Mask
register IMR (R221), th~ Interrupt Priority
register .IPR (R255, Bank 0), and the f aat Interrupt Status bit (fIS) of the flags register
(R213) •
557
Interrupts
6.4.1
System MOde
Register
The System Mode register (R222) controls the mode
of operation of the interrupt hardware.
The
format of the System Mode register is shown in
Figure 6-5.
The fields in this register pertaining to the
interrupt hardware are:
Global Interrupt Enable (DO)' When this bit is
set to 1, interrupts are enabled. When this bit
is cleared to 0, all interrupts are disabled
regardless of the state of individual interrupt
enable or mask bits. This bit is automatically
cleared during an interrupt machine cycle and can
also be cleared by the 01 instruction. It can be
set by using an EI or IRET instruction. A hardware reset clesrs this bit.
Fast ,Interrupt Enable (D1)' When this bit is a'1,
the fast interrupt processing feature is enabled
for the selected interrupt level. When this bit is
a 0, fast interrupt processing is disabled. When
fast interrupt processing is used, the Interrupt
Mask Register bit for the selected level must alsobe set.
Fast Interrupt Select (Dz-D4)' The value of this,
3-bit field se lects the interrupt level for fast
interrupt processing.
All other levels stilL
operate in the normal interrupt mode.
(Bit 7 relates to external memory and not to
interrupts.
For more details on bit 7, see
section 12.3.)
R222 (DE) SYM
SYSTEM MODE
I~I~I~I~I~I~I~I~I
1 = 3-STATE MEMORY
INTERFACE
NOT USED
~
T I L 1 = GLOBAL INTERRUPT ENABLE
1 = FAST INTERRUPT ENABLE
FAST INTERRUPT SELECT
000 LEVELO
001 LEVEL 1
010 LEVEL2
011 LEVEL3
100 LEVEL4
101 LEVELS
110 LEVEL6
111 LEVEL 7
Figure 6-5. System Mode Register
6.4.2 Interrupt Request Register
The Interrupt Request (IRQ) register (R220)
indicates which interrupt levels have pending
interrupts.
It takes a snapshot once for each
instruction near the end of execution. Each bit in
the register corresponds to one interrupt level.
Software can use the IRQ for polling those levels
that are not using hsrdware interrupts and hsve
been'masked off by the IMR., Even when polling,
the software is responsible for removing the
interrupting source when servicing that source.
Writing to the IRQ has no effect. The interrupt
request must be renewed at the source, such as the
UART or a port.
External interrupts are disabled by a reset and
must be enabled via execution of an EI instruction
before bits in the Port 213 Interrupt Pending
registers can be set and external hardware interrupts can occur.
The format of the Interrupt Request register is
ahown in Figure 6-6.
R220 (DC) IRQ
INTERRUPT REQUEST (READ ONLY)
I~I~I~I~I~I~I~I~I
LEVEL7gJJ~J" ~I'
L
LEVEL 6::::.J
LLEVELO
LEVEL 1
LEVEL 5
LEVEL 2
LEVEL 4
LEVEL 3
Figure 6-6, Interrupt Request Register
558
Interrupts
6.4.3 Interrupt Mask Register
6.4.5 Fast Interrupt Status Bit
Register)
The Interrupt Mask (IMR) register (R221) is used
to mask individual interrupt levels, thus preventing interrupts at that level. A 1 enables interrupts at that level, a 0 disables them.
Interrupts should be globally disabled before
-writing to this register.
The format of the Interrupt Mask register is shown
in Figure 6-7.
R221 (~O) IMR
INTERRUPT MASK
I~I~I~I~I~I~I~I~I
LEVEL 5
LLEVELO
LEVEL 1
.
LEVEL 4
of nags
This is a status bit; when it is set to 1, it
indicates that a fast interrupt has occurred.
This bit determines what type of action is taken
during an IRET. If it is a 1, then an IRET causes
a swap between the Program Counter and the
Instruction Pointer, and the Flags' register to be
written into the Flag register. If it is a 0,
then IRET causes a normal interrupt return.
A
hardware reset clears this bit to.O.
The format of the Flags register is shown in
Figure' 5-1, Chapter 5.
LEVEL7~J
I . ~I
~
L
LEVEL 6
(ns
6.5. INTERRUPTS AND THE DHA CHANNEl
LEVEL 2
LEVEL 3
Figure 6-7. Interrupt Mask Register
6.4.4 Interrupt Priority Register
When the DMA channel is enabled to work with a
handshake-driven I/O port or the UART, the in~er
rupt request from the specific device is replaced
by an interrupt request from the DMA channel when
the specified number of transfers has been completed (see Figure.6-8).
The Interrupt Priority (IPR) register (R255, Bank
0) defines. the priority order of the interrupt
levels. The coding of this register is defined in
Figure 6-2. Interrupts should be globally disabled before writing to this register •.
OMA
ENABLE
-I==;::=r:~[}----- REQUEST
OMA
TO IRQ
REGISTER
END
OFCO~~* -.Q.-----l..J
Figure 6-8. Interrupts and the DMA
559
Chapter 7
Reset and Clock
7.1
Resets also reault in the following:
RESET
A system reset, activated by a low level on the
I!rnn' input, overrides all other operating condi-
•
Interrupts are disabled ( the Global Interrupt
Enable bit is cleared and the Interrupt Request
register is disabled)
•
Ports 2, 3, and 4 are placed in input mode
•
In parts with '~n-chip ROM, Ports' 0 and 1 are
placed in input mode; in ROM leas parts, Port 1
is configured as an address/data bus to external memory whfle Port 0 bits 0-4 are configured
as address' bits B-12 and bits 5-7 are in input
mode
•
The on-Chip peripherals are all disabled
•
The Program Counter is loaded with 0020 H
tions and puts the SuperB into a known state. The
I!rnn' input is internslly synchronized with the
internal clock of the SuperB to form the internal
reset line. ror a power-up reset operation when
using the on-chip oscillator, the ~ input must'
be held low for at least 50 llJilliseconds after the
power supply is within tolerance to allow the onchip clock oacillator to stabilize. If an external clock oscillator is used or power has been
applied long enough for the on-chip oscillator to
stabilize, then the
input must be held low
for at least 1B c lock periods to cause a system
reset.
mrr
While I!rnn' is active low, the ~ output is forced
low while ~ pulses low once every four clock
cycles and R/W' remains high.
Z-BUS-compatible
peripherals use the ~ and ~ coincident low state
as a peripheral reset function.
560
Table 7-1 shows' the reset values of the control
and peripheral registers.
Specific reset values
are ,shown by 1s or Os, while an x indicates bits
whos'e ststes sre not defined snd t indicates not
used.
Reset and Clock
Table 7-1. Control and Peripheral Register Reset Values
Register Na.'Je
Comments
t.:rlecanic. DacitJol. Hall
General Registers
Program Control Flags
FLAGS, R213, D5
x x x x x x 0 0
Bank 0, no fast interrupts
Register Pointer 0
RPO, R214, D6
0 0 0 0 0 0'
Working register CO
Register Pointer
RP1, R215, D7
0 0
~/orking
0 0 0
Stack Pointer
SP, R216-7, D8-D9
x
x
x
x
x
x
x
x
Instruction Pointer
IP, R218-9, DA,D8
x
x
x
x
x x
x
x
Interrupt Request
IRQ, R220, DC
0 0 0 0 0 0 0 0
Interrupt Mask
IMR, R221, DD
l(
l(
System Mode
SYM, R222, DE
0 t
External Memory Timing
EMT, R254, FE
(Bank 0)
0
Interrupt Priority
IPR, R255, FF
(Bank 0)
x
l(
register C8
Interrupts disabled
x
x
x
x
x
t
x
l(
x
0 0
Disable interrupts
disable 3-state
0 0
3 wait states for Program
and Data, Slow memory
x
x
l(
x
x
x
x
Port Registers
Port 0
PO, R208, DO
x x x x x x x x
Port 1
P1, R209, D1
x x x x x x x x
Key
o
Reset value of 1
Reset value of 0
l(
t
bits whose states are not defined
not used
561
Reset and Clock
Table 7-1. Control and Peripheral Register Reset Vslues (Continued)
Register
Co_ants
Port Registers (Continued)
Port 2
P2, R210, 02
1
Output register = 1
Value will not be
observable until ports
are configured as output
Port 3
P~, R211, 03
Port 4
P4, R212, 04
x x x x x x x x
Handshake 0 Control
HOC, R244, F4
x x x ·x x 0 x 0
Disable handshake
Ports 1 and 4, disable DMA,
(write only)
Handshake 1 Control
H1C, R245, F5
x x x x. x x x 0
Disable handshake
Port 0 (write only)
Inputs
Port 4 Direction
P40, R246, F6
o
Port 4 Open-Drain
P400, R247, F7
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Port 2/3 Mode
P2AM, R248-251, F8,F9,FA,FB
(Bank 0)
Push-pull
Inputa (write only)
(P2AM, P2BM, P2CM, P2DM)
Port 2/3 Interrupt
Pending
P2AIP, R252-3, FC,FD
0 0 0 0 0 0 0 0
(Write only) software
reset (P2AIP, P2BIP) ,
Port 0 Mode
POM, R240, FO
(Bank 0)
0 0 0 0 0 0 0 0
0 0 0 1 1 1 1
With ROM: input/output
ROMless: 1 = Address
Port Mode
PM, R241, F1
(Bank 0)
t
t
t
t
Key:
= Reset value of 1
o = Reset
562
Output register = 1
Value will not be
observable until ports
are configured as output
value of 0
0 0 0
0
0 0 0 0
With ROM: Port 0/1, inputs
(write only)
ROMless: Port 0/1 outputs
bits whose states are not defined
t = not used
x
Reset and Clock
Table 7-1.
COntrol and Peripheral Register Reset Values (Continued)
Register
IlART and DHA Registers
UART Transmit Control
UTC, R235, EB
0 0 0 0 001
0
Oisable transmitter,
transmit buffer empty
UART Receive Control
URC, R236, EC
000 0 0 0 0 0
Disable receiver
No character received
UART Interrupt Enable
UIE, R237, ED
000 0 0 0 0 0
Disable interrupts
UART Data
UIO, R239, EF
x x x x x x x x
UART Baud-Rate Generator
UBG, R24B-9, FB,F9
(Bank 1)
x x x x x x x x
UART Mode A
UMA, R250, FA
(Bank 1)
x x x x x x x x
UART Mode B
UMB, R251, FB
(Bank 1)
o 0 0 0 0 0 0 0
\~ake-Up Match
WUMCH, R254, FE
(Bank 1) .
x
Wake-Up Mask
WUMSK, R255, FF
(Bank 1)
x x x x x x x x
DMA Count
DC, R240-1, FO,F1
(Bank 1)
x x x x x x x x
x
x
x
x
x
x
Disable baud-rate generator
x
COunter Registers
Counter 0 Control
COCT, R224, EO
(Bank 0)
Key:
o
x xO 0 0 0 0 0
Reset value of 1
Reset value of 0
x
t
Disable counter 0,
interrupts, software
capture
bits whose states are not defined
not used
563
Reset and Clock
Table 7-1.
COntrol and Peripheral Regiater Reset Values (Continued)
CoaDents
Register
COunter Registers
Disable counter 1,
interrupts, software
capture
Counter 1 Control
C1CT, R225, E1
(Bank 0)
x x 0 0 0 0 0 0
Counter 0 Capture
COC, R226-7, E2,E3
(Bank 0)
x x x x x x x x
Counter 1 Capture
C1C, R22B-9, E4,E5
(Bank 0)
x x x x x x x x
Counter 0 Mode
COM, R224, EO
(Bank 1)
o
0 0 0 x x x x
Port 2 I/O
Counter 1 Mode
C1M, R225, E1
(Bank 1)
o 0 0 0 x x x x
Port 3 I/O
Counter 0 Time Constant
COTC, R226-7, E2,E3
(Bank 1)
x x x x x x x x
Counter 1 Time Constant
C1TC, R22B-9, E4,E5
(Bank 1)
x
= Reset value of 1
Key:
0
564
(Continued)
Reset value of 0
1(
x x x
1(
x x
x = bits whose states are not defined
t
not used
Reset and Clock
Eight clock cycles after ~ has returned high,
the SuperB starts program execution, The initial
instruction fetch is from location 0020 H,
The
first program segment executed is typically a
I
6
1
7
routine to initialize the control registers to the
required system configuration, Figures 7-1 and 7-2
show the reset. timing,
.....--T1~T2~j..-T3~Ml
'"
XTAL1
RESET
AS
--11'------.,--.,--.,....---,----1""""--....,.------1;' f
f
,F-'- - - ' - -.......\
--------------~~
ADDRESS
DS ________________
~
...J'f
__- J
"------1C-'_ _
)./-'
opc
DATA
Figure 7-1, Reset Timing for ROM less Devices
r-- M1
1
1
1
2
13 1
6
4
I f.- ---+-1--7
T1
12
~I--- 13
.r--M2~
11 ~ T2 ~ T3 ---i>1
----.f.-
XTAL1
,i
! )
!
,
,I
,
'ADDRESS
,,
,i
,
\..Y
I
,i
v,..----.. .\
0020
..17
DS _ _ _ _ _ _ _ _ _"""'/_ _
'DATA
.. Internal signals except for proto packs
Figure 7-2. Reset Timing for ROM and Protopack Devices
565
Reset and Clock
7.2 ClOCK
7.' TEST
The SuperB derives its timing from on-board clock
circuitry connected to pins XTAl1 and XTAl2. The
clock circuitry conaists of an oscillator, a
divide-by-two shaping circuit, and ,a clock
buffer.
figure 7-3 illustrates the clock
circuitry.
Test mode is a special mode of operation designed
to facilitate testing of SuperB devices that
contain on-board ROM.
Test mode consists of a
special 12B-byte "shadow" ROM that is mapped into
the first 12B locations of program memory and
accessible only when test mode is invoked.
The oscillator's inputs are XTAl1 and XTAl2, which
can be driven by a crystal, a ceramic resonator,
or an external clock source. The divide-by-two
circuit can also be driven directly from a TTL
level on the XTAl1 pin.
Test mode is entered by driving the ~ input to
a voltage level of VCC + Z.5V upon terminating a
normal reset cycle. The voltage waveform needed
to enter test mode is shown' in figure 7-4 and must
be adhered to for proper operation.
Figure 7-3. SuperB Clock Circuit
Crystals and ceramic resonators would be connected
across XTAL1 and XTAl2 and should have the following characteristics to ensure proper osci llator
operation:
Cut:
ttJde:
output frequency:
Resistance:
Capacitance:
AT (crystal only)
Parallel, fundamental
1 MHz-1Z MHz
100 ohms maximum
30 pf maximum
When an external frequency source is used, only
the XTAL1 input needs to be driven.
Any TTLcompatible driver can be used for this function.
The XTAL2 input can be left floating.
MIl)[
After entering test mode, instructions are fetched
from the internal test ROM and are used to
configure Ports 0 and 1 as an external memory
interface and then jump to external memory
location 4030 H•
Once in external memory,
diagnostic
routines
used
to
verify
the
functionality of the SuperB are invoked by the
test system via the address/data bus. During this
process, Port 1 is used only in its address/data
mode; therefore, additional routines are provided
in the test ROM which the test system uses to
verify the I/O and handshake modes of Port 1.
To support testing the interrupt structure, the
first 32 locations of test ROM contain interrupt
, vectors.
Interrupt vectors point to locations
4000 H for IRQO, 4003H for IRQ1 , 4006H for
IRQZ, and so on in external memory. This allows
the external program to have a Z- or 3-byte jump
instruction for each interrupt service routine.
The SuperB stays in test mode until' a normal reset
occurs.
Vee + 2 . S V - - - - - -
6
_XTAlClKS_
MIN
RESET PIN
VRH-----'
2
....- XTAL---...
ClKS
MAX
Note the maximum ramp for application of + 7.SV de to RESET pin. After a
minimum of 6 XTAL eLK cycles, the RESET voltage can be relaxed to VRM.
Figure 7-4. Voltage Waveform for Test Mode
566
ChapterS
1/0 Ports
B.1
INTRODUCTION
B.3 PORT 0
The Super8 has 40 lines dedicated to input and
output.
These are grouped into five ports of
eight lines each. All the lines can be conf19ured
as inputs or outputs; some can be configured as
address/data lines. All ports have TTL-compatible
input and output characteristics and can drive two
standard TTL loads.
B.2 GENERAL STRUCTURE
In general, each bit of the five ports has an
associated input register, output register, and
buffer and control logic. When the CPU writes to
a port, it causes data to be stored in the output
register.
Those bits of that port configured as
outputs enable the output buffer, and the output
register contents are present on the external
pin. If those bits configured as outputs are read
by the CPU, the data present on the externa I pin
is returned. Under normal output loading, this is
the equivalent of reading the output register.
However, if a bit of the port is configured as an
open-drain output, the data returned may not be
the value contained in the output register; rather
it ,is the value forced on the input pins by the
external system.
When a bit of any port is defined as
reading that bit causes data present on
nal pin to be returned.
Ports that
handshake control are an exception;
handshake-driven input bit returns the
latched into the input register by
strobe.
an input,
the exterare under
Reading a
data last
the input
Bits configured ,as inputs can be written to by the
CPU, but in this case, the data is stored in the
output register and cannot be read back because
the output buffer is disabled.
However, if the
input bits are reconfigured as output bits, the
data stored in the output register is then
reflected on the output pins.
This mechanism
allows the user to initialize outputs prior to
driving their loads.
Port 0 (R208) can be configured as I/O or as an
address output port for addressing external memory
on a bit basis. Those bits selected as 1/0 can be
configured as all inputs or all outputs.
When
configured as outputs, the option exists to select
open-drain outputs.
The open-drain option does
not apply to those bits configured as address
lines.
Accesses to Port 0 are made by reading and writing
to register R208 (DOH in set one). When a Port
o bit is configured as an address output, i t
cannot be accessed as a register (writes have no
~ effect, reads return the state of the external
pin) • When used as an 1/0 port, Port 0 may be
placed under handshake control by using the facilities of Handshake Channell (see section 8.8).
The following control registers
with configuring Port 0:
are associated
D
Port Mode register (RZ41 , Bank 0). Controls
direction of 1/0 lines and selection of opendrain or push-pull outputs.
o
Port 0 Mode register (R240, Bank 0).
ures each bit as I/O or address bit.
D
Handshake 1 Control register (R245, Bank 0).
Controls enabling and configuration of handshake signals.
Config-
B.4 PORr 1
Port 1 (R209) can be configured as an address/data
port for interfacing external memory ~ or as a byte
I/O port. The configuration is set using the Port
I~ode register (R241, 8ank 0).
(For a description
of Port 1 as part of the external memory interface, see section 12.3.)
\~hen configured as a
byte output port, there is an option to se lect
open-drain outputs on the entire port.
In the
ROMless parts, Port' 1 is always an address/data
bus and cannot be programmably configured.
567
I/O Ports
When configured as an input or output port,
accesses are made to Port 1 via reads or writes to
register R209 (D1H in set one). When Port 1 is
configured as a multiplexed address/data port, it
cannot be accessed as a register; writes have no
effect and reads return an ff H' When used as an
I/O port, Port 1 can be placed under handshake
control by using the facilities of Handshake
Channel 0 (see section 8.8).
The following control registers are associated
with configuring Port 1:
D
•
Port Mode register (R241. Bank 0). Controls
Port 1 configuration (input port, output port,
or address/data bus) and selection of opendrain or push-pull outputs.
Handshake 0 Control register (R244. Bank 0).
Controls the enabling and configuration of the
handshake signals.
8.5 PORTS 2 AND 3
Ports 2 and 3 (R210 and R211) are used to provide
the external control inputs and outputs for the
UART, the handshake channels, and the counter/
timers. The relationship between port pins and
their control function is shown in Table 8-1.
When Port 2 and 3 bits are not used for control
inputs and outputs, they are available for use as
general-purpose I/O lines and/or external interrupt inputs. Each bit is individually configured
as to its function.
Wh~n·Ports
2 and 3 are used as general-purpose I/O
lines, the direction of each bit can be configured
indiVidually. Each bit selected as an output can
also be configured individ,ually as an open-drain
or push-pull output. All inputs of Ports 2 and 3
are Schmidt-triggered.
Table 8-1.
-~Port
Bit
0
1
2
3
4
5
6
7
568
The following control registers are associated
with configuring ports 2 and 3:
D
Port 2/3 A Mode register (R248. Bank 0).
Controls the configuration of bits 0 and 1
(input, input with interrupt enabled, push-pull
input, open-drain output).
o Port 2/3 B Mode register (R249. Bank 0).
Controls configuration of bits 2 and 3.
D
Port 2/3 C Mode r~ister (R250. Bank 0).
Controls configuration of bits 4 and ?
•
Port 2/3 0 Mode register (R251. Bank 0).
Controls configuration of bits 6 and 7.
The various control functions are enabled in the
control register for the associated device (Handshake Control register, Counter Mode register,
etc.) • When using Port 2 .and 3 pins as control
signals, the Port 2/3 Mode registers must still be
programmed to specify which bits are inputs and
which bits are outputs.
Each bit of Ports 2 and 3 can be used as an external interrupt input. Each bit used as an external '
interrupt input must be configured as an input,
but may still be used as an external control input
or as a general-purpose input line. Each external
interrupt bit has an edge-tr iggered "interruptpending" flip-flop that captures the external
int.errupt requests. Software can read and reset
t.he edge-triggered flip-flops without affecting
the normal I/O operation of the bit. Each external
interrupt has its own interrupt enable control
that determines i f that bit is allowed to cause an
interrupt.
The edge-triggered flip-flops still
capture edges when the interrupt enable control is
disabled. Port 2 is accessed as general register
R210, Port 3 as general register R211.
Ports 2 and 3 Control functions
2 function
UART Receive Clock
UART Transmit Clock
Reserved
Reserved
Handshake o Input
Handshake o Output
Counter 0 Input
Counter 0 I/O
8it
0
2
3
4
5
6
7
Port 3 -function
UART Receive Data
UART Transmit Data
Reserved
Reserved
Handshake 1 Input!WAYi
'Handshake 1 Output/DM
Counter 1 Input
Counter 1 I/O
I/O Ports
Two registers are directly associated with the
interrupt flip-flops:
a Port 2/3 A Interrupt Pending register (R252 ,
Bank 0). Controls interrupt flip-flops for
bits 0, 1, 2 and 3 of Ports 2 and 3.
8.7 PORT MODE AND CONTROL REGISTERS
The ports" are configured and controlled by the
following set of registers:
III
III
o Port 2/3 B Interrupt Pending register (R253,
Bank 0).
Controls interrl,lpt flip-flops for
bits 4, 5, 6, and 7 of Ports 2 and 3.
0
0
Q
0
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Mode
o Mode
2/3 A Mode
2/3 B Mode
2/3 C Mode
2/3 D Mode
2/3 A Interrupt Pending
2/3 B Interrupt Pending
4 Direction
4 Open-Drain
These registers can be used to poll the external
interrupts and to reset the interrupt pending bits
(the flip-flops). Reading these registers returns
the state of the interrupt pending flip-flop.
When writing to these registers, writing a 1 to a
bit position clears that flip-flop and writing a 0
to a bit position has no effect.
II
The Interrupt Mask register (R221) and Port 2/3
Mode registers determine which interrupts are
enablecj.
The Port Mode register provides some additional
mode control for Ports 0 and 1. The fields in
this register are (Figure B-1):
0
0
D
8."7.1
Port Mode Register
R241 BANKO(F1)PM
PORT MODE (WRITE ONLY)
8.6 PORT 4
Port 4 (R212) is always an I/O port whose direction can be configured on a bit-by-bit basis.
Each bit configured as an output can be configured
individually as an open-drain or push-pull output.
Port 4 I/O lines are accessed via reads and
to register R212 (D4H in set one).
~Irites
NOTUSED:=J
PORT 1 MODE
00 OUTPUT
01 INPUT
1X ADDRESS/DATA
I
~~
PORTO DIRECTION
0= OUTPUT
1
INPUT
OPEN-DRAIN PORT 0
o = PUSH-PULL
1 :::: OPEN-DRAIN
OPEN DRAIN PORT 1
o = PUSH-PULL
1 = OPEN-DRAIN
ENABLE DM P3s
0= DISABLE
1 = ENABLE
=
Port 4 can be placed under handshake control by
using the facilities of Handshake Channel 0 (see
section B.B).
Figure 8-1. Port Mode Register
The following control registers are associated
with configuring Port 4:
Port 0 Direction (DO) • If this bit is a 1, all
bits of Port 0 configured as I/O will be inputs.
If this bit is a 0, then the I/O lines will be
outputs. A hardware reset forces this bit to a 1.
o Port Ii Direction register (R246 , Bank 0).
Controls direction of each bit of Port 4.
0"
Port 4 Open-Drain register (R247. Bank 0).
Selects open-drain or push-pull for each Port 4
output.
CI
Handshake 0 Control register (R244, Bank 0).
Controls the enabling and configuration of the
handshake signals.
Open-Drain Port 0 (01)' If this bit is a 1, all
bits of Port 0 configured as outputs will be
open-drain outputs; if 0, they will be push-pull
outputs. This bit has no effect on those bits not
configured as outputs. A hardware reset forces
this bit to a O.
Open-Drain Port 1 (02) ~ If Port 1 is configured
as an output port and this bit is a 1, then all of
the port-will be open-drain outputs. If this bit
is.a 0, they will be push-pull outputs. This bit
has no effect if Port \ 1 is not configured as an
output port or A/D O- 7 '
A hardware reset forces
this bit to a O.
569
I/O Ports
m
Enable
(0,>. If this bit is a 1, Port 35 is
configured as Data Memory output line (m:f).
A
hardware reset forces this bit to a O.
Port 1 Mode (04-05).
This field selects the
configuration of Port 1 as an output port, input
port, or address/data port as part of the external
memory interface. The coding for this field is as
follows:
field
Output port
Input port
Address/data
function
Input
Input and interrupt enabled
Output, push-pull drivers
,Output, open-drain
A hardwBre reset forces all bits of the four
registers to the 0 state.
A hardware reset forces this field to the 01
(input port) state. The ROMless part has this
field forced to 1X.
8.7.2
field
00
01
10
11
function
00
01
1X
of Ports 2 and 3 configures the bit as input or
output. The field also controls whether the bit
is enabled as an external interrupt source and
selects the output as open-drain or push-pull.
The field is coded as follows:
R248 BANK 0 (F8) P2AM
PORT 2/3 A MODE (WRITE ONLY)
Port 0 Mode Register
The Port 0 Mode reqister programs each bit of Port
o as an address output (part of an external memory
interface) or as an I/O bit (Figure B-2). When a
bit of this reqister is a 1, the correspondinq bit
of Port 0 is defined as an address output. When a
0, the corresponding bit of Port 0 is defined as
an 1/0 bit. For ROMless parts, a hardware reset
forces this reqister to all 1s for pins POO-P04
and Os for pins P05-P07; for parts with on-chip
ROM, a hardware reset forces all pins to O.
00 INPUT
01 INPUT,INTERRUPT ENABLEO
10 OUTPUT, PUSH·PULL
11 OUTPUT, OPEN·DRAIN
Figure 8-3. Port 2/3 A Mode Register
R249 BANK 0 (F9) P2BM
PORT 2/a B MODE (WRITE ONLY)
R240 BANK 0 (FO) POM
PORTOMOOE
::::~I
I I ~::::
P05MODE~
EpOZMOOE
PO, MOOE
00
01
10
11
INPUT
INPUT,INTERRUPT ENABLEO
OUTPUT, PUSH·PULL
OUTPUT,OPEN·DRAIN
Figure 8-4. Port 2/3 B Mode Register
PO, MODE
o =1/0; 1 =ADDRESS
R250 BANK 0 (FA) P2CM
PORT 2/3 C MODE (WRITE ONLY)
Figure 8·2. Port 0 Mode Register
8.7.' Port 2;' Mode Registers
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C
Mode, and Port 2/3 D Mode registers control the
modes of Ports 2 and 3 (Figures 8-3, 8-4, 8-5, and
8-6). A separate 2-bit field for each of the bits
570
00 INPUT
01 INPUT, INTERRUPT ENABLEO
10 OUTPUT, PUSH·PULL
11 OUTPUT, OPEN·DRAIN
Figure 8-5. Port 2/3 C Mode Register
I/O Ports
R251 BANK 0 (FB) P2DM
PORT 2/3 0 MODE (WRITE ONLY)
00 INPUT
01 INPUT, INTERRUPT ENABLED
10 OUTPUT, PUSH-PULL
11 OUTPUT, OPEN-DRAIN
8.7.5
The Port 4 Direction register defines the I/O
direction Df Port 4 Dn a bit basis (Figure 8-9).
If a bit in this register is a 1, the corresponding hit of Port 4 is configured as an input line.
If the bit is a 0, the correspDnding bit Df Port 4
is configured as an output line. A hardware reset
forces this register tD the all 1s state.
R246 BANK 0 (F6) P4D
PORT 4 DIRECTION
Figure 8-6_ Port 2/3 0 Mode Register
8.7.4
Port 2/3 Interrupt Pending Registers
The Port 2/3 A Interrupt Pending and Port 2/3 B
Interrupt Pending registers represent the software
interface
to
the
edge-triggered
flip-flops
associated with external interrupt inputs.
Each
bit of these registers corresponds to an interrupt
generated by an external SDurce.
When one of
these registers is read, the value of each bit
represents the state Df the corresponding interrupt. When Dne of these registers is written tD,
a 1 in a bit position causes the correspDnding
edge-triggered flip-flDp to be reset to 0; a O.
causes no action.
The software interfaces with these registers to
pDIl the interrupts and also tDreset pending
intenupts as they are prDcessed. The relationship between these registers and the correspDnding
externally generated interrupts is shown in
Figures 8-7 and 8-8. A hardware reset fDrces all
interrupt edge-triggered flip-flops tD the 0
state.
Port 4 Direction Register
' - - - - - - - P4,-P47 110 DIRECTlDN
o DUTPUT; 1 INPUT
=
=
Figure 8-9. Port 4 Direction Register
8.7.6
Port 4 Open-Drain Register
The Port 4 Open-Drain register defines the Dutput
driver type for PDrt 4 (Figure 8-10). If a bit of
Port 4 has been cDnfigured as an output and the
correspDnding bit in the PDrt 4 Open-Drain
register is a 1, then the PDrt 4 bit will have an
open-drain output driver; i f it is a 0, 'then the
Port 4 bit will have a push-pull output driver.
If the bit Df Port 4 has been configured as an
input, then the corresponding bit in the Port 4
Open-Drain register has no effect. A hardware
reset forces this register tD the alIOs state.
R247 BANK 0 (F7) P40D
PORT 4 OPEN-DRAIN
I~I~I~I~I~I~I~I~I
LI_ _ _ _ _ _
R252 BANK 0 (FC) P2AIP
PORT 2/3 A INTERRUPT PENDING
~~-~~~~:pE~l~;~A~N
OPEN-DRAIN
Figure S-10. Port 4 Open-Drain Register
8.8
Figure 8-7. Port 2/3 A Interrupt Pending Register
R253 BANK 0 (FD) P2 BIP
PORT 2/3 B INTERRUPT PENDING
Figure 8-S. Port 2/3 B Interrupt Pending Register
8257-041, 042, 043, 044. 045
HANDSHAKING CHANNELS
The SuperB has tWD handshaking channels. Channel
"0" is associated with PDrts 1 or 4; Channel "1"
is associated with Port O. They are identical in
function except Channel 0 also has DMA capability.
There are tWD basic modes Df operatiDn. The first
is the "fully interlocked" or two-wire mode. ,In
this mode. there is an incDming control wire and
Each transition on a
an outgoing cDntrol wire.
control wire must be answered by a transition 011
the other cDntrDl wire befDre the first can make
anDther transition.
Thus both the sender and
receiver control the data transmission rate.
Figures B-11 and 8-12 illustrate the operatiDn Df
the "fully interlDcked handshake."
571
· I/O Ports
DAV
(INPUT TO SUPERB)
(OUTPUT FROM
SUP:~~ ---+-"""
DATA ON PORT
(INPUT TO SUPERB)
State 1. Ready output is high indicating that the SuperB is ready to accept data.
State 2. The 1/0 device puts data on the port and then activates the DAV input. This causes ~he
data to be latched into the port input register and generales an interrupt or DMA request.
State 3. The SuperB forces the Ready (ROY) output low. signaling to the 110 device that the data
has been latched
State 4. The 1/0 device returns the DAV line high in response to ROY going low.
State 5. The SuperB DMA or interrupt software must respond to the service request and read the contents of the port in order for the handshake sequence to be completed. The ROY line goes high
if, and only if, the port has been read and DAV is high. This returns the interface to its initial state.
Figure 8-11. Super81nput Handshake-Fully Interlocked Mode
RDY
(INPUT TO SUPERB)
DAV
(OUTPUT FROM SUPERB)
SET·UP
DATA ON PORT
(OUTPUT FROM SUPERB)
VALID DATA
State 1. ROY input is high indicating that the 1/0 device is ready to accept data.
State 2. The SuperB writes to ~ort register to initiate a data transfer. Writing the port outputs
new data and forces DAY low if, and only if, ROY is high and set·up time is done.
State 3. The 1/0 device.forces ROY low after latching the data. ROY low causes an interrupt or DMA
request to be generated. The SuperB can write new data in response to ROY going low.
State 4. The DAY output from the SuperB is driven high in response to ROY going low
State 5. After DAY goes high, the I/O device is free to raise ROY high thus returning the interface
to its initial state.
Figure 8-12. Super8 Output Handshake-Fully Interlocked Mode
Each channel has a 4-bit counter, called the
Deskew Counter, that is used to count processor
clocks.
In the "strobed" mode, this counter is
used to generate the set-up time and strobe width
for the output handshake. In the "fully inter-
The second mode is the "strobed" or single-wire
mode. In this mode there isa single control wire
and it is generated by the sender. Figures 8-13
and 8-14 illustrate the operation of "strobed"
handshaking.
I
I
DAV - - - - - -" " N . - - S T R O B E _ ,
(INPUT TO SUPERB)
SET·UP
DATA ON PORT
(INPUT TO SUPERB)
-1-1 1--- HOLD - I
--v-A-
VALID DATA
X·
\ -_ _ __
I
Figure 8-13. Super81nput Handshake-Strobed Mode
572
I/O Ports
DAV
(OUTPUT FROM SUPERB)
-----~""\
STROBE
r~I j---------
I
1\...-1
I-f-SET-UP
DATA ON PORT ~
(OUTPUT FROM SUPERB) ---'\;.......;._ _ _._V_A_Ll_D_D_A"_A_ _ _ _ __
THE SET-UP AND STROBE MINIMUM TIMES ARE DETERMINED
BY THE VALUE IN THE DESKEW COUNTER.
Figure 8-14. Super8 Output Handshake-Strobed Mode
locked" mode, the counter generates the set-up
time.
This set-up time is the delay between
outputting valid data at the port and activating
the Data Available handshake signal. The Deskew
Counter can be loaded with a value from 1 to 16
that represents the minimum number of CPU clock
cycles in the data set-up and strobe times.
The direction of data transfer during handshake is
determined by the selected direction of bit 0 of
the paralle 1 port associated with the handshake
channel.
This also controls the DMA direction
when used.
8.8.1
needed by the handshake function.
Note that the
open-drain options of Ports 2 and J can be applied
to the handshake outputs. Note also that Port 2
and J pins used by the handshake channels as
inputs can still be used as external interrupt
pins to drive the handshake service routines.
Handshake Input.
This input provides the IDW
signal for input handshaking or the ROY signal for
output handshaking.
Handshake Output. This output provides the ROY
signal for input handshaking or the IDW signal for
output handshaking.
Pin Descriptions
8.8.2
The handshake channels each use two pins of Ports
2 and 3 (bits 4 and 5) for interfacing \~ith the
external world:
G
Handshake Channel 0 Input
Handshake Channel 0 Output
P24
P2 5
Handshake Channel
Handshake Channel
P34
PJ5
Input
Output
Handshake Control Registers
Each handshake channel is. controlled by an 8-bit
control register (Figures 8-15 and 8-16).
Handshake 0 Control register (R244) and Handshake 1
Control register' (R245) include the controls for
enabling handshakes, selecting the associated port
(Channel 0 only), selecting the handshake type,
enabling DMA capability (Channel 0 only), and
initializing the Deskew Counter.
The fields in
these registers are:
The individual Port 2 and 3 pins should be configured for the appropriate I/O direction as
R244 BANK 0 (F4) HOC
HANDSHAKE 0 CONTROL (WRITE ONLY)
I~I~I~I~I~I~I~I~I
DESKEW COUNTER
(RANGE 1-16)
~
II
L.. ~"~~
PORT SELECT:
1
PORT1;O = PORT 4
=
DMAENABLE:
1 = ENABLED
0= DISABLED
' - - - - - MODE:
1 = FULLY INTERLOCKED
0= STROBED
Figure 8-15. Handshake 0 Control Register
573
I/O Ports
,
R245 BANK 0 (F5) H1C
HANDSHAKE 1 CONTROL (WRITE ONLY)
I~I~I~I~I~I~I~I~I
DESKEW COUNTER
(RANGE 1·16)
==oJ
I
I L,""~,"~,,,",,
NOT USED
MODE:
1 = FULLY INTERLOCKED
0= STROBED
Figure 8-16. Handshake 1 Control Register
Handshake Enable (00). When this bit is set to 1,
the handshake function is enabled.
Port Select (Channel 0 only)(O,).
This bit
selects which port is controlled by Handshake
Channel O.
When it is set to 1, Port 1 is
se lected and when it is cleared to 0, Port 4 is
selected.
DMA Enable (Channel 0 only)(OZ). When this bit is
set to 1, the DMA function is enab led for Handshake Channel O. When it is cleared to 0, the DMA
function is not used by the handshake channel and
may be used by the UART.
574
Mode (03).
When this bit is set to 1, the "fully
interlocked" mode is enabled. When it is cleared
to 0, the "strobed" mode is enabled.
Deskew Counter (04-07).
This 4-bit field is used
to select a count value from 1 to 16 (0000-1111).
This value is the number of processor clocks used
to generate the set-up and strobe when using the
"strobed" mode, or the set-up when using the
"fully-interlocked" mode.
Chapter 9
Counter/Timers
9.1
INTRODUCTION
The SuperS has two identical 16-bit counter/timers
that can be programmed independently. They can be
cascaded to produce a counter 32 bits in length
and can operate from internal inputs (as timers)
or external inputs (counters).
When used as
timers, the internal input is the internal. CPU
clock divided by two, which is the XTAL divided by
four. Figure 9-1 shows the counter/timer block
diagram.
The counter/timers can count up or down.
The
direction can be controlled on the fly by either
software or an external event.
The counter/timers have the option of single cycle
or continuous counting capability. In the single
cycle mode, the counters count to zero (up or
down) from the preset time-constant value and then
stop.
In the continuous mode, counting is
continuous and each time the counter reaches zero,
it is reloaded with the preset time-constant value
from the Time Constant register (or the Capture
register in bi-value mode).
T
o
A
T
A
B
U
5
I
M
E
C
0
N
5
T
¢=;
¢=l
A
N
T
t
CPU
CLOCK
Figure 9-1. Counter/Timer Block Diagram
575
Counter /Timers
9.1.1
Bi-Value MDde
Another option allows either a single or dual
(bi-value) preset time constant value.
In
bi-value mode, both the Time Constant register and
Capture register are used to supply load values to
the counter/ timer. The two registers alternate
in loading the counter/timer each time the
counter/timer makes a transition between a count
of 0 and a count of FFFFH when counting down, or
between a count of FFFFH and 0 when counting up
(assuming continuous mode operation), or when a
trigger causes the ,counter/timer to be reloaded.
This can be used to produce an output pulse train
with a variable duty cycle. The bi-value feature
is not available when the capture feature is
enabled and vice versa.
Upon enabling a
counter/timer in bi-value 'mode from a previously
disabled condition, the initial load of the
counter/timer is from the Time Constant register.
9.1.2
The external event can be either the rising edge
of the counter/timer I/o line (P27 for C/TO, P37
for C/T1) or both edges. On the rising edge, the
current count value is loaded into the Capture
register. If capture on both edges is enabled, the
current count value is loaded into the Time
Constant register on the falling edge, overwriting
the initial load value for that counter.
The capture feature is not available when the
bi-value counting feature is being used and vice
versa.
If interrupts are enabled, the interrupt request
is generated on the transition from a count of 0
to a count of FFFF H or from a count of FFFF H
to a count of 0, and/or on an external event. If
configured for an external output, the output pin
toggles at this same count change.
9.1.3
Capture
Another feature, called "capture on external
event," takes a snapshot of the counter when a
specific event occurs. The external event can be
simulated by software.
When "captured," the
current value in the counter is loaded into a
special
register
that
can
subsequently
be
read via software. The capture feature is needed
to look at counters on the fly, especially
cascaded counters.
External Gate and Trigger
The counter/timers have an external gate capability. When this feature is selected, an external
input line (GATE) is monitored. The counting or
timing operation is performed only when this line
is low.
The gate facility is illustrated in
Figure 9-2.
GATE INPUT
COUNTER OR
TIMER INPUT
A COUNT OCCURS HERE:
Figure 9·2. Gate Facility
TRIGGER INPUT
COUNTER OR
TIMER'INPUT
A COUNT OCCURS HERE:
n
.
-----'.I I.....-JL-'
.....
Figure 9-3. Trigger Operation
GATE/TRIGGER
INPUT
COUNTER OR TIMER INPUT
A COUNT OCCURS HERE:
Figure 9-4. Gate/Trigger Function
576
Counter/Timers
An ex ternal input can be used as a 'tr igger input
to a counter~timer. ~Ihen this feature is selected,
an external line is monitored. A software trigger
is also present in a control register.
The
trigger input to the Counter/Timer is an OR of the
software and hardware triggers. Prior to a lowto-high transition on the ,trigger, the Counter is
disabled. After the low-to-high transition on the
trigger, counting is enabled. Retriggerable or
non-retriggerable mode can be selected.
Clearing the Counter Enable bit in the Control
register also resets the triggered condition; a
new trigger must be received' afte,r the Counter
Enable bit is set again before counting will
resume. The trigger operation is illustrated in
Figure 9-3.
One input line (GATE/TRIGGER) can be used for both
An
the gating and the triggering functions.
initial low-to-high transition, on this line acts
as a trigger and subsequent low signals on this
line function as gate signals (Figure 9,-4).
The Mode and Control registers determine the
counter/timer operations. Th~ Mode register
selects the configuration of the counter/timers
and is generally loaded only at initialization
time, while the Control register handles those
features that are likely to be dynamically
changed.
The Time 'Constant register contains the initialization value for the counter/timer and also holds
the counter value saved on the falling edge of
P27/P37 when capture on both edges is enabled.
The Capture register holds the counter value saved
when using the "capture on external event" function. When capture on both edges is enabled, it
holds' the value saved on the rising edge of
P27/P37. It also holds a second initialization
value when using the bi-value counting feature.
9.2.1. Counter/Ticer Control Registers
The fields in these registers, as shown in Figures
9-5 and 9-6, are:
9.2
cn~ER/TI~ cn~TROL AreD ~nnE
REGISTERS
Each counter/timer has an a-bit Mode register, an
a-bit Control register, a 16-bit Time Constant
register, and a 16-bit Capture register.
'llli'
R224, BANK 0 (EO) COCT
COUNTER 0 CONTROL
SINGLECYCLE'~~
o1== CONTINUOUS
o = COUNT DOWN
1
L L = ENA~LECOUNTER
=
, 1 = ZERO COU~T INTERRUPT ENABLE
= COUNT UP
1 = LOAD COUNTER
1
1
READ 1 = END OF COUNT
WRITE 1
RESET END OF COUNT
1
= SOFTWARE CAPTURE
= SOFTWARE TRIGGER
Figure 9-5. Counter 0 Control Register
'
llli
R225 BANK 0 (El)C1CT
COUNTER 1 CONTROL
SINGLECYCLE~~
o1== CONTINUOUS
o = COUNT DOWN
. 1
1
1
= COUNT UP
= LOAD COUNTER
,
,L
L
1
= ENABLE COUNTER
,
READ 1 = END OF COUNT
WRITE 1 = RESET END OF COUNT
1
= ZERO COUNT INTERRUPT ENABLE
1
= SOFTWARE CAPTURE
= SOFTWARE TRIGGER
Figure 9-6. Counter 1 Control Register
577
Counter/Timers
Enable Counter (Do). When this bit is set to 1,
the counter/timer is enabled; operation begins on
the rising edge of the first processor clock
period following the setting of this bit from a
previously cleared value.
Writing a 1 in this
field when the previous value was 1 has no effect
on the operation of the counter/timer. When this
bit is cleared to 0, the counter/timer performs no
'operation during the next (ard subsequent)
processor clock periods. A hardware reset forces
-this bit to O.
Reset/End of Count Status (01). This bit is set
to 1 each ~ime the counter reaches O. Writing a 1
to this bit resets it, while writing a 0 has no
effect.
,Zero Count Interrupt Enable (Dz). When this bit
is set to 1, the counter/timer generates an interrupt request ,when it counts to o. A hardware reset
forces this bit to O.
Software Capture (0,). When this bit is set to 1,
the current counter value is loaded into the
capture register.
This bit is automatically
cleared following the capture.
Software Trigger (D~). This bit is effectively
"ORed" with the external rising-edge trigger input
and can be used by the software to force a trigger
signal.
This bit produces a trigger signal
regardless of the setting of the Input Pin Assignment 'field of the Mode register. This bit is
automatically cleared following the trigger.
load Counter (05). The contents of the Time
Constant register are transferred to the Counter
prescaler one clock period after this bit is set.
This operation alone does not start the Counter.
This bit is automatically cleared following the
load.
Count Up/bown (06). This bit determines the count
direction if internal up/doWn control is specified
in the Mode register. A 1 indicates up, a 0 down.
ContinllDus/Single Cycle (D7)., When this bit is
set to 1 and the count reaches 0, the countdown
sequence is automatically restarted by loading the
time-constant value into the counter. When this
bit is cleared to 0, no reloading occurs.
9.2.2 Counter/Tiaer Mode Registers
The fields in these registers, as shown in Figure
9-7 and 9-8, are:
Capture Mode (01. DO). This 2-bit field selects
the capture or bi-value count mode. A value of 01
enables capture on the rising edge of the I/O pin,
a value of 11 enables capture on both edges of the
I/O pin, a value of 10 enables the bi-value count
mode and disables capture, and a value of 00
disables both capture and bi-value load.
Programed/External Up/Dowl Control (Dz) • A 1
enables programmed up/down control and a 0 enables
external up/down control. If external up/down is
enabled, a 0 on P27/P37 indicates _down- and a 1
indicates up.
Enable Retrigger (0,). When this bit is set to 1,
the time-constant value is automatically loaded
into the Counter/Timer register when a trigger
R224 BANK 1 (EO) COM
COUNTER 0 MODE
INPUT PIN ASSIGNMENTS:
P2.
00001/0
1/0
o 0 0 1 1/0
TRIGGER
0010GATE
1/0
TRIGGER
0011GATE
o 1 0 0 1/0
CO INPUT
o 1 0 1 TRIGGER
CO INPUT
0110GATE
CO INPUT
0111GATE/
TRIGGER
CO INPUT
CO OUTPUT 1/0
CO OUTPUT TRIGGER
CO OUTPUT GATE
CO OUTPUT GATE/TRIGGER
CO OUTPUT CO INPUT
- - UNDEFINED-- - UNDEFINED-- CASCADE COUNTERS -
I
L~=,_,
EDGE OF P27
10 = BI·VAWE LOAD
11 = CAPTURE ON BOTH
EDGESOFP27
,
' - - - - - - 1 = ENABLE RETRIGGER
Figure 9·1. Counter 0 Mode Register
578
0 = EXTERNAL
UPIDOWN CONTROL P27
1 = PROGRAMMED
UPIDOWN CONTROL
Counter/Timers
R225 BANK 1 (El) C1M
COUNTER 1 MODE
INPUT PIN ASSIGNMENTS:
P3,
o 0 0 0 110
o 0 0 1 110
o 0 1 0 GATE
0011GATE
o 1 0 0 110
o 1 0 1 TRIGGER
110
TRIGGER
110
TRIt;GER
CllNPUT
CllNPUT
CllNPUT
I L ~'1:"5C::".,"
EDGE OF P37
10 = BI-VALUE MODE
11 = CAPTURE ON BOTH
EOGESOFP37
0= EXTERNAL
UP/DOWN CONTROL P37
1 = PROGRAMMED
UP/DOWN CONTROL
all0GATE
0111GATE/
TRIGGER
Cl INPUT
Cl0UTPUT 110
Cl OUTPUT TRIGGER
Cl OUTPUT GATE
Cl OUTPUT GATE/TRIGGER
Cl OUTPUT Cl INPUT
- - UNDEFINED-- - UNDEFINED-- - UNDEFINED--
1 = ENABLE RETRIGGER
Figure 9-8_ Counter 1 Mode Register
input is received while the counter/timer is
counting (Counter/Timer not equal to 0).
When
this bit is cleared to 0, no reloading occurs.
Input Pin Assiglllllents (D4-o7)' This 4-bit field
specifies the functionality of the port lines
associated with the counter/timer. It also determines whether the counter/timer will monitor an
external input (counting operation) or use the
scaled internal processor clock (timing operation). The four bits in the field select the
following options: enab Ie output (EO), external
signal or internal clock (C/T), enable gate facility (G), and enable triggering facility (T). The
Table 9-1.
IPA Field
EO
0.,
0
0
0
0
0
0
0
0
1
'1
CIT
T
D6 D5 D4
0
0
G
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
selected options determine the functions associated with each external line of the counter/
timer as illustrated in Table 9-1.
A hardware
reset forces these four pins to O.
If 1111 is coded in this fie ld in the Counter 0
Mode register, then the two counter/timers are
linked together as a 32-bit counter with Counter 0
as the low-order 16 bits and Counter 1 as the
high-order 16 bits. Counter 1 se lects the mode
and control options for the 32-bit counter and
external accesses are made through the lines
associated with Counter 1 (P36 and P37)'
IPA Field Encoding in Counter Made Registers
Pin Functionality -Counter/Timer I/O
Counter/Tilller Input
(P26 or P36 )i>
(P27 or P~)"
I/O
I/O
Gate
Gate
I/O
Trigger
Gate
Gate/tr igger
Output
Output
Output
Output
Output
Undefined
Undefined
Undefined
I/O
Trigger
I/O
Trigger
Input
Input
Input
Input
I/O
Trigger
Gate
Gate/trigger
Input
Undefined
Undefined
Undefined
Notes
Timer
Timer
Timer
Timer
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
Counter
Reserved
Reserved
Reserved for Counter 1,
Cascade for Counter 0
.. Counter/timer 0 - P27 and P2 6
- P3 7 and P3 6
Counter/timer
8257-059
579
Counter/Timers
The counter/timer I/o line (P27 for C/TO, P37 for
C/T1) is also used as the external capture input
if the capture feature is enabled, and the up/down
control input (O=down, 1=up) if external up/down
control is enabled.
9.2.~
TiDe Constant Register
This 16-bit register pair holds the value that is
automatically loaded into the counter/timer 1)
when the counter/timer is enabled, 2) in continuous mode, when the count reaches zero, or 3) in
re-trigger mode, when the. trigger is asserted. If
capture on both edges is enabled, then this register captures the contents of the counter on the
falling edge of the I/O pin.
The format of the Time Constant
illustrated in Figure 9-9.
register
R226 BANK 1 (E2) COTCH
COUNTER 0 TIME CONSTANT
This 16-bit register pair is used to hold the
counter val ue saved when using the "cBpture on
external event" function.
This register will
capture at the rising edge of the I/O pin or when
software capture is asserted. When the bi-value
mode of operation is enabled, this register is
used as a second Time Constant register and the
counter is. alternately loaded from each.
The format of the Capture Register is shown in
Figure 9-10.
R226 BANK 0 (E2) COCH
COUNTER 0 CAPTURE
I~I~I~I~I~I~I~I~I
LI_ _ _ _ _ _
is
i
HIGH BYTE (COCa-COC,s)
R227 BANK 0 (E3) COCl
COUNTER 0 CAPTURE
I~I~I~I~I~I~I~I~I
1~1~1~1~I~l~I~I~1
L I_ _ _ _ _
9.2.4 Capture Register
HIGH BYTE (COTCa-COTC,s)
R227 BANK 1 (E3) COTCl
COUNTER 0 TIME CONSTANT
L I_ _ _ _ _ _
lOW BYTE (COCo-COC,)
R228 BANK 0 (E4) C1CH
COUNTER 1 CAPTURE
I~I~I~I~I~I~I~I~I
L I_ _ _ _ _
lOW BYTE (COTCo-COTC,)
R22B BANK 1 (E4) CHCH
COUNTER 1 TIME CONSTANT
R229 BANK 0 (ES) Cl Cl
COUNTER 1 CAPTURE
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
1
..._ _ _ _ _
HIGH BYTE (CHCa-CHC,s)
LI_ _ _ _ _ _
lOW BYTE (C1Co-C1C,)
Figure 9-10. Capture Register Format
R229 BANK 1 (ES) CHCl
COUNTER 1 TIME CONSTANT
I~I~I~I~I~I~I~I~I
1----..
lOW BYTE (CHCo-CHC,)
Figure 9~9_ Time Constant Register Format
580
Chapter 10
UART
10.1
INTRODUCTION
The universal asynchronous receiver/transmitter
(UART) is a full-duplex asynchronous channel.
Transmission ahd reception can. be accomplished
independently with 5 to B data bits per character,
plus optional even or odd parity, and an optional
wake-up bit.
The Transmit Data output (P31) ,line is 'held marking (high) when the transmitter has no data to
send. If the Send Break (SENBRK) bit of the UART
Tran~it Control (UTC) register is set to 1, the
Data Output line will, be held spacing (low) until
it is cleared.
10.3 RECEIVER
Data can be read into or out of the UART via
R239.
This single address is able to serve a
full-duplex channel be,cause it contains two complete B-bit registers--one for ,the transmitter and
the other' for the receiver.
10.2 TRANSMITTER
When the UART' s register address is spec i fied as
the destination (dst) of an operation, the data is
output ,on the UART. The UART automatically adds
the start bit, th~, programmed parity bit (odd,
even, or no parity), and the programmed number of
stop bits to the data character to be transmitted. The transmitter can also add a Wake-Up
bit (optional) between the parity bit (or the last
bit in the character if parity is disabled) and
the first stop bit, as shown in Figure 10-1. When
the character is five, six, or seven bits long,
the unused bits in the Transmit Data register
(UIO) are automatically ignored by the UART.
Serial data is shifted from the transmitter at a
rate equal to 1, 1/16th, 1/32nd, or 1/64th of ,the
clock rate supplied to the transmitter clock input
(as determined by the clock-rate field in the UMA
register). Serial data is shifted out on the
falling edge of the transmitter clock.
An asynchronous receive operation begins when the
Receive Enable bit (RENB) in the UART Receive
Control register (URC) is set. A low (spacing)
condition on the Receive Data line (P30) indicate a
a start bit. If this low persists for at least
one-half of a bit time, the start bit is assumed
to be valid and the data input is then'sampled at
the middle of each bit ,time until the entire
character is assembled and placed in the Receive
Data (UIOR) register. This method of detecting a
start bit improves, error rejection when noise
spikes exist on an otherwise marking line.
If X1 clock mode is selected, bit synchronization
must be accomplished externally, and the received'
data is sampled on the rising edge of the clock
input.
A received character can be read from the B-bit
Receive Data register (UIOR).
The receiver
inserts 1s into the unused bits when a character
length of other than eight bits is used.
If
parity is enabled, the parity bit is not stripped
from the assembled charscter for character lengths
less thsn eight bits;'i.e., for lengths less than
eight'bits, the receiver assembles a character for
the required number of data bits, plus a parity
bit, wake-up bit, and 1s for any unused bits, and
places it in the UART Data register (UIO).
PARITY
MARKING LINE
PARITY
DATA
DATA
• NOTES: 1. Parity, wake-uP. and second stop bit are optional
2. Data can be anywhere fro~ 510 8 bits
Figure 10-1. Asynchronous Transmission Data Format
"
581
UART
Since the receiver is buffered by one B-bit
register in addition to the Receive Data register,
the CPU haa enough time to service an interrupt
and to accept the data character aasembled by the
UART. The receiver also has a buffer that stores
error flags for each data character in the receive
buffer. These error flags are loaded at the same
time as the data character.
•
If parity is enabled, the Parity Error bit
(PERR) in the UART Receive Control (~RC) register is set to 1 whenever the parity bit of the
character does not match the programmed
parity. Once ,this bit is set, it remains set
until cleared by software.
•
The framing Error bit (fERR) in the URC register is set to 1 if the character is assembled
without any stop bits (Le., a low level is
detected for a stop bit) and it is set with the
character on which it occurs. It stays latched
until cleared by software.
•
If the CPU fails to read a data character when
more than one character has been received, the
Receive Overrun Error bit (OVERR) in the URC is
set to 1. When this occurs, the new character
assembled raplaces the previous character in
the Receive Data register. 'With this arrangement, only the over.writing charscter is flagged
Like the
with the Receive Overrun Error.
Parity Error bit, this bit can be cleared only
by software command from the C~U.
After a character is received, it is checked for'
the following conditions:
•
•
If the received character is an ASCII control'
character, it sets the Control Character Detect
(ceO) bit in the UART Receive Control (URC)
register. (An ASCII control character is any
character that has bits 5 and 6 cleared to 0.)
It can also cause an interrupt if the Control
Character Interrupt Enable (CCIE) bit in the
UART Interrupt Enable (UIE) register is set to
1. Once this bit is set, it remains set until
, cleared by so ftware.
The wake-up settings are checked and any
indicated action is completed. , In wake-up
mode, the CPU can be selecbvely interrupted on
a match condition that includes all of the
eight bits in the received character and a
Wake-Up bit. The Wake-Up bit match and character match can be enabled sim~ltaneously or
individually. Each bit in this character match
(for more
can also be masked individually.
discussion of this feature, see section 10.4.)
Once this bit is set, it remains set until
cleared by software.
10.4 MAKE-UP FEATURE
The SuperB offers a powerful scheme to configure
the UART receiver to interrupt only on certain
special match conditions. figure 10-2 shows the
logic diagram for the scheme. '
RECEIVER
~~~~i\'~ ~.-----VAWE
RECEIVED
WAKE-UP
BIT
Figure 10-2. Logic Diagram for Wake-Up Feature
582
UART
The pattern match logic can be used with or without the Wake-Up bit. The Wake-Up Match register
and 'Wake-Up Mask register determine the character
or characters that will generate a pattern match
when detected at the receiver. If the Wake-Up bit
is enabled, the pattern match occurs if the
Wake-Up bit in the received character matches a
pre-determined value, and the received character
matches the' value(s) specified in the Wake-Up
Match and ~/ake-Up Mask registers. If the Wake-Up
bit is disabled, the pattern match depends only on
the character's value.
The Receive
buffer that
received and
by the CPU.
contains the
register is
Case 1:
a)
Data (UIOR) regiater is the receive
is loaded i f a new character i.s
the previous character has been read
The Wake-Up Match (WUMCH) register
match value. The Wake-Up Mask (WUMSK)
used to mask out any selected bit
tflJEMI
=1
positions in the WUMCH register.
The Wake-Up
Enable (WUENB) bit in the UART Transmit Control
(UTC) register is enabled only if'a match for the
Wake-Up bit is also desired. If this is disabled,
the scheme can still be used to·look for a character match. The Receive Wake-Up Value (RWUVAL) bit
in UART Mode A (UMA) register is the expected
value of the Wake-Up bit; the Received Wake-Up bit
(RWUIN) is the Wake-Up bit value received by the
receiver.
The following cases sho~1 how the Wake-Up Detect
(~/UD) bit in the UART Receive Control (URC) register can be set by a match condition. However, the
CPU is interrupted only if the Wake-Up Interrupt
Enable (WUIE) bit in the UART Interrupt Enable
(UIE) register is set to 1.
(tlake-Up bit is enabled)
If Wake-Up bit match snd WUMCH match (all 8 bits) is.desirad:
Set WUMSK = 1111
WUMCH =
1111 (%FF)
(desired match value)
If WUMCH (bits 7-0) = UIO (bits 7-0) snd
RWUVAL = R~/UIN
Then Wake-Up Detect (WUD) flag is' set.
b)
If Wske-Up bit match and WUMCH match (selected bit, i.e., bits
5, 4, 1, 0) is desired:
Set WUMSK = 0011 0011 (%33)
WUMCH = XX__ XX__ (desired match bits 5, 4, 1, '0)
If WUMCH (bits_5, 4, 1, 0) = UIO (bits 5, 4, 1, 0) snd
RWUVAL = RWUIN
Then Wake-Up Detect (WUD) flag is set.
c)
If only a Wake-Up bit match is desired:
Set WUMSK = 0000 0000 (%00)
WUMCH =XXXX XXXX (don't csre)
If RWUVAL
= RWUIN
Then I"ake-Up Detect (WUD) flag is set.
583
UART
Case 2:
a)
tlUENB
=0
(Ha!te-Up bit is igllQred)
If a match is desired for WUMCH· (sll 8 bits):
Set WUMSK = 1111 '1111 (%FF)
WUMCH = _ _ _ _ (desired match value)
If WUMCH (bits 7-0) = UfO (bits 7-0)
Then Wake-Up Detect (WUD) flag is set.
b)
If a match is desired on WUMCH (selected bits only, i.e., bits 4, 3, 2):
Set WUMSK
WUMCH
0001
1100 (%1C)
XX~
___XX (desired match bits 4, 3, 2)
If WUMCH (bits 4, 3, 2) = UIO (bits 4, 3, 2)
Then Wake-Up Detect (WUD) flag is set.
c)
If a match is always desired:
Set WUMSK = 0000 0000 (%00)
WUMCH = XXXX XXXX (don't care)
If this character is received, the Wake-Up Detect (WUD) flag is always
set'. However, this will be ignored i f the Wake-Up Interrupt Enable
(WUIE) bit in the UART Interrupt Enable (UIE) register is disabled.
10.5 AUTO-ECHD/LUUl'BACI(
register must be set to 1 for this mode to work
c~rrectly.
As shown in Figure 10-3, the UART can be configured to automatically transmit any data coming in at
the Receive Data input pin (P30) RXD. This autoecho mode of operation is enabled by setting the
Auto-Echo (AE) bit in the UART Mode B (UMB) register to 1. In addition; the Transmit Data Select
(TXDTSEL) bit in the UART Transmit Control (UTC)
Similarly, the UART can ·be set in the local loopback mode by setting the Loopback Enable (LBENB)
bit in the UMB register to 1. In loopback mode,
the output of the transmitter is automatically
routed to the.receiver.
r
RECEIVE DATA (RxD)
RECEIVE DATA IN (RxIN)
-----....:...---'--~-1.,........!'-----;~11
P" ......
LOOPBACK
ENABLE
[UMB[
RECEIVER
I
~
LOOPBAClt
AUTO.EC::J
TRANSMIT
DATA SELECT
E1
P3l
[UTe]
AUTO·ECHD
(AE) iUMBI
' -TRANSMIT DATA (TxD)
0--+--"---1......_ _--11
(TxDTSEL = 1)
RxD_RxIN
TxDATO RxlN
RxD-AxIN
TxDATO RxlN
TxDATO_TxD
TxDATO-TxD
RxD-TxO
RxD-TxO
Figure 10-3. Auto-Echo/Loopbacl(
584
UART
In auto-echo mode, the transmitter can still be
enabled; however, the transmitter data goes
nowhere unles~ loopback is also enabled.
10.6
POLLED OPERATION
In a polled environment, the Receive Character
Available (RCA) bit in the URC register must be
monitored so the CPU can decide ~Ihen to read a
character. This bit is automatically cleared when
the UIOR is read.
To prevent overwriting-data in polled operations,
the transmit buffer status must be checked before
writing to the transmit buffer (UIOT).
The
Transmit Buffer Empty (TBE) bit in the UTC is set
to 1 after completing the sending of a character.
10.7
The baud-rate generator consists of two a-bit Time
Constant registers, a 16-bi t downcounter, and a
flip-flop on the counter's output that produces a
square wave.
BAUD-RATE GENERATOR
The UART has its own on-chip programmable baudrate generator implemented as a 16-bit downcounter. The transmitter can receive its clocking
signal from an external source (P21) or the baudrate generator (BRG); the receiver clock can come
from an external source (P20) or the on-chip
baud-rate generator.
On startup, the flip-flop is set to a high state,
'the value in the Time Constant registers is loaded
into the Counter, and the Counter starts counting
down.
The output of the baud-rate generator
t09\'lles on reaching zero, the value in the Time
Constant registers is again loaded into the
The time
Counter, and the process is repeated.
constant can be changed at any time, but the new
value does not take effect until the next load of
the Counter.
As shown in Figure 10-4, the output of the baudrate generator can be used as -the receive clock,
the transmit clock, or both. The transmitter and
receiver can handle data at a rate of 1, 1/16th,
1/32nd, or 1/64th of the clock rate supplied to
the receive and transmit clock inputs.
(Port 2, Bit 1) is riot used as transmit
clock input, it may be used as an output.
A
multiplexer (MUX) prov ided at P21 can be used to
output various clocks or-P21 data; bits 6 and 7 of
the UMB register determine the function of P2 when
it is used as an output.
If P21
If P21 is not used as a Transmit Clock input, it
can be used to output the transmit clock, the CPU
clock, the output of the baud-rate generator, or
as an I/O line.
RECEIVE CLOCK SELECT
(UMB)
P2o,I---.....- - - - - - - - - - - - ,
TRANSMITTER
CLOCK
TRANSMIT CLOCK SELECT
(UMB)
Figure 10·4. Baud-Rate Generator
585
UART
10.8 lIART INTERfACE PINS
10.9.2 Wake-Up Match Register (MUMCH)
The UART uses up to four Port 2 and 3 pins for
interfacing with the external world. These are:
Any chsracter up to eight bits can be written into
this register. The receiver detects a match
between the received character and this charactel'.
The fDrmat of this register is shown in
Figure 10-6.
P2 0
P30
P21
P31
Receive Clock
Receive Data
Trsnsmit Clock
Transmit Data
R254 BANK 1 (FE) WUMCH
WAKE·UP MATCH REGISTER
I~I~I~I~I~I~I~I~I
10.9
OART CONTROl/MODE AND STATUS REGISTERS
LI_ _ _ _ _ _
The following sections and figures describe the
UART Control/Mode and Ststus registers.
10.9~1
OART Data Register (UIOT & UIOR)
THIS BYTE, MINUS MASKED BITS,
IS USEO FOR WAKE·UP MATCH
Figure 10-S. Wake-Up Match Register,
10.9.' Wake-Up Mask Register (WUMSK)
Writing to this register automatically writes the
data 'in the Transmit Data register (UlOl); a read
from this register gets the data from the UART
Receive 'Data register (UlOR). 'The formst of this
register is shown in Figure 10-5.
Any bit in the WUMCH register can be masked by
writing a 0 into the corresponding bit in this
register. The format of this register is shown in
Figure 10-7.
R255 BANK 1 (FF) WUMSK
WAKE·UP MASK REGISTER
R239 BANK 0 (EF) UIO
UART TRANSMIT DATA (WRITE)
UART RECEIVE OATA (READ)
I~I~I~I~I~I~I~I~I
1 . 1_ _ _ _ _
' - - - - - - DATA (Do = LSB)
THESE BITS CORRESPOND TO BITS
IN WAKE·UP MATCH REGISTER; Os
MASK CORRESPONDING MATCH SITS
Figure 10-7. Wake-Up Mask Register
Figure 10-5. UART Data Register
this bit to O. A write to this bit position has
no effect. A hardware reset forces this bit to O.
10.9.4 lIART Receive Control Register (URC)
The fields in this register (Figure 10-B) are:
RCA. Receive Character Available (DO)' This is a
status bit that is set to a 1 when data is available in the receive buffer (UlOR). When the CPU
reads the receive buffer, it automatically clears
RENO. Receive Enable (01)' When this bit is set
to 1, the receive operation begins.' This bit
should be set only after all other receive parameters are established and the receiver is completely initialized. This bit is cleared to a 0 by
a hardware reset, which disables the receiver.
R236 BANK 0 (EC) URC
UART RECEIVE CONTROL
1=
WAKE.UI'DETECT2J~
~
1 = CONTROL CHARACTER DETECT
1 = BREAK DETECT
,
1 = FRAMING ERROR
,
III
L .. -,,~~"-~
1 = RECEIVE ENASLE
1 = PARITY ERROR
1 = OVERRUN ERROR
Figure 10-8., UART Receive Control Register
586
UART
PERR. Parity Error (Dz). This is a status bit.
When parity is enabled, this bit is set to 1 and
buffered with the character whose parity does not
match the programmed parity (even/odd). This bit
is latched so that once an error occurs, it
remains set until it is cleared to 0 by writing a
1 ,to this bit position. A hardware reset forces
this bit to O.
OVERR. OVerrun Error (0,). This status bit indicatea that the rece i ve buffer has not been read
and another character has been received. Only the
character that has been written over is flagged
with this error; once set, this bit remains set
until cleared to 0 by writing a 1 to this bit '
position. A hardware reset forces this bit to O.
FERR. Fraaing Error (04)' This is a status bit.
If a framing error occurs (no stop bit where
expected), this bit is set for the receive character in which the framing error occurred. This bit
remains set until cleared to 0 by writing a 1 to
this bit position. A hardware reset forces this
bit to O.
IIRICD.
that
break
stays
Break Detect (05)' This is a status bit
is set at the beginning and the end of a
sequence in the receive data stream. It
set to 1 until cleared to 0 by writing a 1
to this bit position. A hardware reset forces this
bit to O. See note in section 10.9.5 for .more
information.
ceo.
Control Character Detect (0,). This status
bit is set any time an ASCII control character is
received in the receive data stream. It stays set
until cleared to 0 by writing a 1 to this bit
position. (An ASCII control character is any
character that has bits 5 and 6 set to, 0.) A hardware reset forces this bit to O.
VUD. Make-Up Detect (07)' This status bit is set
any time a valid wake-up condition is detected at
the receiver. It stays set until cleared to 0 by
writing a 1 to this bit position. The wake-up
condition can be satisfied in many possible ways
by the Wake-Up bit, Wake-Up Match register, and
Wake-Up Mask register. See the Wake-Up Feature
section (section 10.4) for a more detailed explanation. A hardware reset forces this bit to O.
10.9.5 UART Interrupt Enable Register (UIE)
This register contains the individual status and
data interrupt enables (Figure 10-9). The fields
in this register are:
R237 BANK 0 (EO) UIE
UART INTERRUPT ENABLE
1
= WAKE.UP INTERRUPT
1
1
1
=
ENABLE~
JJ I'
= CONTROL CHARACTER
INTERRUPT ENABLE
BREAK INTERRUPT ENABLE
= RECEIVE ERROR INTERRUPT
ENABLE
~
III
'
L,._,~~~
INTERRUPT ENABLE
1
= RECEIVE OMA ENABLE
1
= TRANSMIT INTERRUPT ENABLE
1
= ZERO COUNT INTERRUPT ENABLE
'
Figure 10-9. UART Interrupt Enable Register
RCAIE. Receive Dteracter Available Interrupt
Enable (DO), If this bit is set to 1, then a
Receive Character Available status in the URC
register wi II cause an interrupt request;
In a
DMA receive operation, i f this bit is se,t to 1,
then an interrupt request will be issued only i f
an End-of-Process (EOP) of the DMA counter is also
set.
If it is nol set, ,a Receive Character
Available status causes no interrupt. A hardware
reset forces this bit to O.
ROMAENB. Receive
is set to 1, the
UART receiver.
Available signal
DMA request will
gains control of
DNA Enable (01)' When this bit
DMA function is enabled for the
Whenever a Receive Character
in the URC register is true, a
be made. When the DMA channel
the bus, it will transfer the
received data to the register file or the external
memory. A hardware reset forces this bit to O.
TIE. Transmit InterrUpt Enable (Dz). 'If this bit
is set to 1, then a, Transmit Buffer Empty signal
in the UTC register wi 11 cause an interrupt
request. In a DMA transmit operation, i f this bit
is set to 1, then an inte rrupt request wi II be
issued only i f an End-of-Process (EOP) of the DMA
counter is also set. If it is not set, a Transmit
A
Buffer Empty signal causes no interrupt.
hardware reset forces this bit to O.
/
ZCIE. Zero COla'll; Interrupt Enable (0,). I f this
bit is set to 1, a baud-rate'generator Zero Count
status in the UTC register will cause an interrupt
request. A hardware reset forces this bit to O.
587
UART
REIE. Receive Error Interrupt Enable (O~). If
this bit is set to 1, any receive error condition
will cause an interrupt request. Possible receive
error conditions include parity error, overrun
error, and framing error. A hardware reset forces
this bit to o.
BRKIE. Break Interrupt Enable (OS). If this bit
is set to 1, a transition in either direction on
the break signal will cause an interrupt request.
A hardware reset, forces this bit to o.
Note: A break siqnal is a sequence of Os. When
all the' required bits" parity bit, wake-up
'bit, and stop bits are Os, the receiver
immediately recoqnizes a break condition (not
a framinq error) and causes Break Detect
(BRKD) to be set and an interrupt request. At
the end of the break signal, a zero character
is loaded into the Receive Data reqister
(UIOR) and Break Detect (BRKD) is set again,
alonq with another interrupt request.
CCIE. Control Character Interrupt Enable (06). If
this bit is set to 1, then an ASCII Control
Character Detect signal in the URC register will
cause an interrupt. A hardware reset forces this
bit to O.
VUIE. Make-Up Interrupt Enable (0,). If this bit
is eet to 1, then any of the wake-up conditions
that, set the Wake-Up Detect bit (WOO) in the URC
register will cause an interrupt request. A hardware reset 'forces this bit to O.
10.9.6 UARf Mode A Register (UHA)
'This register controls the configurations of the
receiver/transmitter that are not likely to change
on a dynamic basis. The fields in this register
(Figure 10-10) are:
R250 BANK 1 (FA) UMA
UARTMOOEA
CWCKRME:J
0706
""0"0 = X1
o 1 = X16.
1 0
1 1
= X32
= X64
llli
l L
L
TRANSMITWAKE.UP VA,WI
RECEIVE WAKE·UP VAWE
1 = EVEN PARITY
1 = PARITY ENABLE
BITS PER CHARACTER
0504
o
0
1
1 0
1 1
o
=5BITS·
=6BITS
=7BITS
=8BITS
Figure 10-10. UART Mode A Register
TlllNAL. fr_it Vake-up Value (DO).
If the
wake-up mode is enBbled, then the value in this
bit position is transmitted along with the character at the appropriate time by the transmitter.
RVUVAL. Receive Make-Up Value (D1). If the wakeup mode'is enabled, then the receiver expects a
wake-up bit after the parity bit in the incoming
data stream and the value is compared with this
bit value. For further explanation of how this is
used, see the Wake-Up Feature section (Section
10.4).
EVNPAR. Even,Parity (Dz>. This bit determines the
type of parity used 'by both the receiver and the
588
transmitter. If this bit is set to 0, odd parity
is used; if this bit is set to 1, then even parity
is used. If the Parity Enable (PARENB) bit in this
register is not enabled, then this bit has no
effect.
PARENB. Parity Enable (0,). When this bit is set
to 1, an additional bit position beyond those
specified in the bits/character control is added
to the transmitted data and is expected in the
received data'. The received parity bit is transferred to the CPU as a part of the data unless
eight bits per character are used. If this bit is
set to 0, the parity feature is disabled.
UART
~PC1.
BPCD. Bits Per Character (05. 04)' This
field determines the number of bits per character
for both the. transmit and the receive sections.
The character bits Ilre right-justified with the
least significant bit transmitted or received
first.
The field is coded as shown in Table
10-1.
OR1, CRO. Clock Rate (07. 06)'
This field
specifies the multiplier behleen the clock and the
data rates. Table 10-2 shows how this field is
coded.
Table 10-2.
Clocle Rate Field Encoding
Table 10-1.
Character Size Field Encoding
1>J
06
~de
ilascription
04
Charecter Size in Bits
0
0
1
1
0
5
0
0
1
0
05
1 x
16 x
32x
64 x
Clock
Clock
Clock
Clock
6
0
0
1
rate = 1 x data rate
rate
16 x data rate
rate = 32 x data rate
rate
64 x data rate
7
B
R235 BANK 0 (EB) UTe
UART TRANSMIT CONTROL
TRANSMIT DATA
1
SELECT:~
J
o = OUTPUT P3, DATA
= OUTPUT TRANSMIT DATA
1
= SEND BREAK
1
1
I
STOP BITS:
0= 1 STOP BIT
2 STOP BITS
~
I L
L.
1
= TRANSMITDMA ENABLE
1
= TRANSMIT BUFFER EMPTY
1
= ZERO COUNT
1 = TRANSMIT ENABLE
=
= WAKE·UP ENABLE - - - - - '
Figure 10-11. UART Transmit Control Register
10.9.7 UART
Tr~it
Control Register (UTC)
This register contains the status and command bits
needed to control the transmit section of the
UART. The fields in this register (Figure 10-11)
are:
IDlW:NB. Transait OWl Enebla (DO), Vlhen this bit
is set to 1, it enables the DMA function for the
UART transmit section. If this bit is .set and the
Transmit Buffer Empty signal becomes true, then a
DMA request is made. When .the DMA channel gains
control of the bus, it transfers bytes from the
external memory or the register file to the UART
transmit section.
A hardware reset forces this
bit to O.
TBE. Tr~it Buffer Empty (01)' This status bit
is set to 1 whenever the transmit buffer is
empty. It is ~leared to 0 when a data byte· is
written in the transmit buffer. A hardware re~et
forces thia bit to 1.
IC. Zero Count (Dz>. Thia statua bit is set to 1
and latched when the. Counter in the baud-rate
generator reaches the count of O. This bit can be
cleared to 0 by writing a 1 to this bit poaition.
A hardware reset forces this bit to O.
TErm. TrOlsrnit Enable (0,).
Data is not
transmitted until this bit is set to 1. When
cleared to 0, the Transmit Data pin continuously
outputs 1s unless Auto-Echo mode is selected.
This bit should be cleared only after the desired
transmission of data in the buffer is completed.
A hardware reset forces this bit to O.
taJIll:B. \1elce-Up Enable (04)'
If this bit is set to
1, wake-up mode is enabled for both the transmitter and the receiver. The transmitter adds a bit
beyond those specified by the bits/character and
the parity. This added bit has the value specified
in the Transmit Wake-Up Value (TWUVAL) in the UMA
register.
The receiver expects a Wake-Up bit
value in the incoming data. stream after the parity
bit and compares this value with that specified in
the Received Wake-Up Value (RWUVAL) bit in the UMA
register.
The resulting action depends on the
configuration of the Wake-Up feature. Amore
complete description is given in the Wake-Up
Feature section (section 10.4). A hardware reset
forces this bit to.O.
STPBTS. Stop Bits (05)' This bit determines the
number of stop bits added to each character transmitted f~om the UART transmit section. If this bit
is a 0, then one stop bit is added. If this bit
589
UART
is a 1, then t.wo stop bits are added.
The
receiver always checks for at least one stop bit.
A hardware reset forces this bit to O.
SENBRK. Send Break (06)' When set to 1, this bit
forces the transmit section to continuously output
Os, beginning with the' follo'lling transmit clock,
regardless of any data being transmitted at the
time.
This bit functions whether or not the
transmitter is enabled. When this bit is cleared
to 0, the transmit section continues to send the
contents of the Transmit Oata register. A hardware reset forces this bit to O.
output. If this bit is set to 1, the serial data
coming out of the transmit section is reflected on
the P31 pin. 1f this bit is set to 0, then P31
acts as a normal port and P31 data is reflected on
the P31 pin. A hardware reset forces this bit to
O.
10.9.8. UART Mode B Register (UHB)
This register (Figure 10-12) contains the necessary status and command bits for the baud-rate
generator, transmit clock select, auto-echo and
loopback enable. The fields are as follows:
TlIDJSEL. Transmit Data Select (07)' This bit has
an effect only i f port pin P31 is confiQured as an
'
E
R251 BANK 1 (FB) UMB
UARTMODEB
CLOCK OUTPUT SELECT
~
0706
o 0 = P2, DATA
o 1 = SYSTEM CLOCK (XTALl2)
1 0 = BAUD-RATE GENERATOR
OUTPUT
1 1 = TRANSMIT DATA CLOCK
L
L
1 = LOOPBACKENABLE
1 = BAUD-RATE GENERATOR ENABLE
BAUD-RATE GENERATOR SOURCE:
o = P20 (EXTERNAL)
1 = INTERNAL (XTALl4)
TRANSMIT CLOCK INPUT SELECT:
1 = AUTO-ECHO ------:--'
0= P21
1 = BAUD-RATE GENERATOR OUTPUT
RECEIVE CLOCK INPUT SELECT: - - - - - - - '
0= P20
1 = BAUD-RATE GENERATOR
OUTPUT
Figure 10-12_ UART Mode B Register
LBENB. Loopback Enable (DO), Setting this bit to
1 selects the local loopback mode of operation. In
this mode, the data output from the transmit
section is also routed back to the receive
section. For meaningful 'results, the fr,equency of
the transmit and receive clocks must be the same.
A'hardware reset forces this bit to o.
BRGENB. Baud-Rate Generator Enable (01)' This bit,
controls the operation of ,the baud-rate generator.
The Counter in the baud-rate generator is
enabled for counting when this bit is set to 1 and
disabled for counting when this bit is set to O.
A hardware reset forces this bit to O.
TCIS. Transmit Clock· Input Select (0,), This bit
se lects the source for the t,ransmit section clock
input. If rCIS is'cleared to 0, the source is the
transmit clock pin (P21)' If it is set to 1, then
the source is the baud-rate generator output. A
hardware reset forces this bit to O.
ReIS. Receive Clock Input Select (04)' This bit
selects the source for the receive section clock
input. If this bit is cleared to 0, the source is
the receive clock pin (P20)' If it is set to 1,
then the source is the baud-rate generator output •. A hardware reset forces this bit to O.
Ar. - Auto-Echo (05)' Auto-echo mode of operation
BRGSRC. Baud-Rate Generator Source (~). This bit
selects the source of the clock for the baud-rate
generator •. If this bit is set to 0, the baud-rate
generator clock comes from the receive clock pin
(P20)' If this bit is set to 1, the clock for the
baud-rate generator is the CPU clock divided by
two (XTAL clock divided by four). A hardware reset
forces this bit to O.
590
is enabled by setting this bit to 1.
In this
mode, the: data coming in on the receive data pin
is reflected out on the transmit data pin. The
receive section still listens to .the receive data
input; however, the data from the transmit section
goes nowhere. See section 10.6 for a more detailed description of this function. A hardware reset
forces this bit to O.
UART
COS1, COSO.
Clock Output Select (D,06)' This
field determines the source that drives the
transmit clock pin if P21 is configured as an
Table 10-3.
output.
A hardware reset forces this field to
00. Table 10-3 shows the coding of this field.
Transmit Clock Source field Encoding
I?
D6
Output Sourc:e
0
0
1
0
P21 Data
System clock (XTAL frequency divided by 2)
Baud-rate generator output
Transmit data rate
0
1
10.9.9
UART Baud-Rate Generator Tillle Coootant
Register (UBG)
value does not take effect. until the next time
constant is loaded into the downcounter.
This register contains the high and low bytes
(Figure 10-13) for the 16-bit time constant used
to \lenerate the desired baud rate.
The time
constant can be changed at any time, but the new
The formula for determining the appropriate time
constant for a given baud rate is shown below,
with the desired rate in bits per second and the
baud-rate clock period in seconds.
time constant: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
-1
(2 x baud rate x n x BRG input clock period)
where n:1,16,32,or 64 x the clock rate selected in UMA register R250
R24B BANK 1 (FB) UaGH
UART BAUO-RATE GENERATOR
R249 BANK 1 (F9) UBGL
UAnT BAUD-RATE GENERATOR
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
1'-------
HIGH BYTE (UBG.-UBG15)
L I_ _ _ _ _
LOW BYTE (UBGo-UBG,)
Figure 10-13_ UART Baud-Rate Generator Time Constant Register
8257-074
591
Chapter 11
DMAChannel
11.1
INTRODUCTION
The DMA Count registers (RZ40 and RZ41 , Bank 1)
hold the 16-bit count that determines the number
of transactions the DMA channel is to perform. The
count loaded should be n-1 to perform n byte
transfers. An interrupt can be generated when the
count is eXhausted.
The SuperB has an on-chip Direct Memory Access
(DMA) channel to provide high bandwidth data
transmission capabilities that can be used by the
UART receive or transmit section or by Handshake
Channel O.
DMA transfers to or from the register file take
six CPU clock cycles; DMA transfers to or from
memory take ten CPU clock cycles, excluding wait
states.
The DMA channel can transfer data between the
peripheral device and contiguous locations in
either the register file or external data memory.
UART Receiver
------>
Register file or
data memory
UART Transmitter
<------
Handshake Channel 0
<------
Register file or
data memory
Handshake Channel 0
------>
Register file or
data memory
11.2
DMA CONTROl REGISTERS
The control bits that, link the DMA channel to the
UART or an I/O port are the Transmit OMA Enable
(TOMAENB) bit in the UART Transmit Control (UTC)
register for the transmitter, the Receive DMA
Enable (ROMAENB) bit in the UART Interrupt Enable
(UIE) register for the receiver, and the OMA
Enable bit (OZ) in the Handshake 0 Control register for the I/O ports. Oniy one of these three
enable bits should be set at a given time.
If
Handshake Channel 0 is linked to the DMA channel,
the data transfer direction is determined by the
direction of the handshake.
Register file or
data memory
Prior to enabling the DMA channel, the starting
register address for the block to be transferred
must be present in register C1H or the starting
memory address must be present in register COH
(high' byte) and C1 H (low byte).
Registers COH
and C1 H th~msel ves can only be' accessed as part
of the working register group.
The address is
auto-incremented
after
each
DMA-controlled
transfer.
A bit in the External Memory Timing register,
called OMA INT/EXT, controls whether OMA transfers
access the register file or external data memory.
When this bit is cleared to 0, transfers are to/
from the register file. When this bit is set to
1, transfers are to/from external data memory.
See Figure 11-1.
R254 (aANKO) EMT
EXTERNAL MEMORY TIMING REGISTER
I~I~I~I~I~I~I~I~I
L
OMAINT/EXT
1 = EXTERNAL MEMORY
o = REGISTER FilE
R240 (BANK1) OCH
OMA COUNT HIGH
R192 (CO) RPO = CO
DMA AOORESS HIGH
R241 (BANK1) DCl
DMA COUNT lOW
R193 (Cl) RPO = CO
OMA ADDRESS lOW
Figure 11-1. DMA Control Registers
592
DMA Channel
11.3 Dl.m AND THE UART RECEIVER
The Receive DMA Enable bit (RDMAENB) in the UlE
register (R237) of the UART is first set"to 1 to
link the DMA to the UART receiver.
Data received at the UART receiver is handled by
the DMA as soon'as the Receive Character Available
(RCA) status bit of the URC register (R236) of the
UART is set to 1.
The DMA reads data from the
UIO register of the UART and then clears the RCA
bit to prepare the UART receiver to receive new
data.
The data is then stored at the location
whose address is contained in the DMA address register, (RR192). The DMA count at RR240, Bank 1, is
decreased by 1 and the DMA addreas register is increased by 1. When the DMA count is" negative, an
interrupt request (IRQ6, vector address 20, 21) is
generated at the UART Receive - section if the,
Receive Character Available Interrupt Enable bit
of the UIE register of the UART (R237) is set to
1.
The UART continues to receive new data and the DMA
responds to the RCA bit as described above until
an interrupt is generated due to a negative DMA
count.
11.4
D~
AKD THE UART TRANSMITTER
First, the Transmit DMA Enable (TDMAENB) bit of
the UTC register (R235) of the UART is enabled to
link the DMA to the UART "transmitter.
Upon transmit, the Transmit Buffer Empty status
bit (TBE) in the UTC register (R235) of the UART
is set to 1. The DMA then transfers the date at
the location whose address is contained in the DMA
address register (RR192) to the UIO register
(R239) of the UART.
The TBE bit is then cleared to O. The DMA count
at RR240, Bank 1, is decreased by 1 and the DMA
address register is increased by 1. When the DMA
count is negative, the DMA issues an End-ofProcess (EOP) signal to the UART. The UART grants
an interrupt request (IRQ1, vector address 26, 27)
to the SuperB i f the' Transmit Interrupt Enable
(TIE) bit of the UIE register (R237)of the UART
is set to 1.
The UART transmitter continues its operation with
the new data in the UlD register a,nd the DMA responds to the TBE bit as described above until an
interrupt is generated due to a negative DMA
count.
11.5 I»lA AND IfANDSHAl(E CHANNEL 0
The DMA can be configured with Handshake Channel D
to transfer data frum register fi Ie or data memory
to I/O devices or vice versa through Port 1 or
Port 4.
Handshake Channel 0 can be in either
fully inter locked mode or strobed mode as controlled by the Handshake 0 Control register
(R244).
The direction of DMA transfer is determined by the handshake direction, which is the
direction of the chusen port.
11.5.1
DNA HRITE (INPUT HANDSHAKE CHANNEL 0)
The I/O device transfers data to register file or
data memory thr"ough Handshake Channel 0 and the
DMA channel.
593
DMA Channel
The Handshake, Channe I 0 tnab Ie and OMA Enab Ie bits
of the Handshake 0 Control (HOC) register (R244)
should be first set to 1.
When the 1/0 device
puts data on the port specified in the HOC register and activates TIAV to go from high to low as in
figures 8-11 and 8-13, the OMA transfers data on
the port to the specified address in the DMA
address register (RR192). The OMA count' at RR240,
Bank 1, is decreased by 1 and the OMA address register is increased by 1. When the OMA count is
negative, the DI~A issues an End-of-Process (EOP)
signa I to Handshake Chaillle 1 O. Handshake Channe I
o grants an interrupt request (lRQ4) to the
Super8.
The handshake output at pin 25 is the
same as described in Figures a-11 and 8-13 and the
OMA is waiting for the I/O device to put data on
the port and activate the 151W signal again.
11.5.2 DNA READ (OUTPUT HAN>SHAKE CHANNEL 0)
Data is transferred from register file or data
memory to the I/O device through the DMA channel
and Handshake Channel O.
, The Handshake Channe I 0 Enable and OMA Enable bits
,of the Handshake 0 Control (HOC) register' (R244)
should be first set to 1. The handshake direction
should be set by choosing the direction of the
port specified in the HOC register.
The DMA sequence should always begin by writing
the first byte of data to the port to start the
DMA. This is en important process, otherwise the
OMA \ is not activated when Handshake Channel 0 is
not yet activated.
The DMA starting address in
,the mlA address register (RR192) should now be set
at the second byte of the data block. The I/O device should then read that first byte of data and
store it away as in figures 8-12 and 8-14. The
DMA is then activated.
594
11.5.2.1 FULLY INTERLOCKED MODE
At State 3 of Figure 8-12, the DMA reads the data
at the address specified in the DMA address register (RR192) and transfers it to the port. The DMA
count at RR240, Bank 1, is decreased by 1 and the
DMA address register is increas,ed by ,1. When the
DMA count is negative, the DMA issues an End-ofProcess (EOP) signal to Handshake Channel O.
Handshake Channe I 0 then grants an interrupt request (IRQ4) to the SuperB.
,The DMA and, handshake process continues as in
Figure 8-12 until an interrupt is caused by a
negative DMA count.
11.5.2.2 STROBED MODE
After the first writing of the first byte of data
to the port as ,in Figure B-14, the DMA is'activated at the end of strobe time. The DMA reads the
data at the address specified in the DMA address
register (RR192) and transfers it to the port.
The DMA count at RR240, Bank 1, is decreased by 1
and the DMA address register is increased by 1.
When theDMA count is negative, the DMA issues an
End-of-Process (EOP) signal to Handshake Channel
O. Handshake Channel 0 then grants an interrupt
request (IRQ4) to the SuperB.
The handshake operation continues as in Figure
B-14 and the DMA transfers new data to the port
only at the end of strobe time.
The DMA stops
when an interrupt is activated by a negative DMA
count.
External Interface
12.4 EXTERNAL STACKS
12.5 DATA MEMORY
The SuperB architecture supports stack operations
in either the register file or in data memory. A
stack's location is determined by setting bit 1 in
the External Memory Timing register, R254, Bank 0
(Figure 12-5).
The two external memory spaces, data and program,
can be addressed as a single memory space or as
two separate spaces.
If the memory spaces are
separated, program memory and data memory are
logically selected by the Data Memory select output (mf). 1m" is made available on Port 3, line 5
(P3 5 ) by setting bit D3 in the Port Mode register
to 1 (Figure 12-6).
R254 BANKO (FE) EMT
EXTERNAL MEMORY TIMING
1071 061 051 041 0,1 021 0, I00 I
~ STACK SELECTION
R241 aANKO (Fl) PM
PORT MODE REGISTER
I~I~I~I~I~I~I~I~I
o = REGISTER FILE
1
OATA MEMORY
=
T
= P35 MODE DETERMINED BY PORT 2/3
C MODE REGISTER
1 = P3s = DM OUTPUT
o
Figure 12·5. External Memory Timing
The instruction used to change the stack selection
bit should not be immediately followed by an
instruction that uses the stack, since this will
cause indeterminate program flow.
Interrupts
should be disabled when changing the stack
se lection bit.
Figure 12-6. Data Memory
12.6 BUS OPERATION
are machine cycles (Mn), timing states (Tn), and
clock periods.
All timing references are made
with respect to the output signals ~ and rg. The
clock is shown for clarity only and does not have
speci fic timing re lationships with other signals;
the clock signal shown is the external clock,
which has twice the frequency of the internal CPU
clock.
Typical data transfers between the SuperB and
external memory are illustrated in Figures 12-7
and 12':'B.
Machine cycles can vary from six to
twelve external clock periods depending on the
operation being performed. The notations used to
describe the basic timing periods of the SuperB
EXTERNAL
CLOCK
PO
P1
AS
X
X
'---I
Ao~A70UT
RIW
OM
)
8---C
r
\
os
>C
AE,·A 15
""-
I
XI_
>C
READ CYCLE
-I
Figure 12-7. External Instruction Fetch or Memory Read C~cle
8257-082,083,084
595
External Interface
r. . .--
i-
- , - - - MACHIN: CYCLE----- , - -.....·o-I1
T
T
2
EXTERNAL
CLOCK
X
X
PO
Pl
>C
>C
Aa-A15
Ao·A7IN
X
Do-D, OUT
'--
\J
AS
!
\
OS
r-
~
R/W
~
OM
>C
I-
WRITE CYCLE
-I
Figure 12-B. External Memory Write Cycle
12.6.1
Address Strobe ~
All transactions start with Address Strobe (AS)
being driven low and then raised high by the
SuperB.
The rising edge of m;' indicates that
Read/~Ir ite
(R/IV) , Data Memory
\.J
B---C
Ao- A70UT
I
\
RlW
x=
A.-A1'
C
/
X
I-
READ CYCLE
Figure 12·7. External Instruction Fetch or Memory Read Cycle
602
'---
x=
-,
External Interface
1- " '---T-,----
MACHIN:, CYCLE
~----T3---t·1
EXTERNAL
CLOCK
X
PO
Pl
><
>C
>C
Aa-A15
Ao·A7 IN
)(
0 0-0, OUT
'---I
M
I
\
OS
\
X
R/W
liM
I·
"-
WRITE CYCLE
/
>C
.. I
Agure 12·8. External Memory Write Cycle
12.6.1
~reas
Strahe
(A§)
All transactions start with Address Strobe (7I'!D
being driven low and then raised high by the
SuperB.
The rising edge of ~ indicates that
Read/Write (Rf\iT), Data Memory (1m), and the
addresses output from Ports 0 and 1 are valid.
The addresses output via Port 1 typically need to
be latched during ~, whereas Port 0 address
outputs, if used, remain stable throughout the
machine cycle.
12.6.2
Data Strobe ~
The SuperB uses Data Strobe (mD to time the
actual data transfer. For write operations (R~ =
low), a low on 1'i!r indicates that valid data is on
the Port 1 ADO-AD7 lines.
For read operations
(R/W = high); the address/data bus is placed in a
high-impedance state before driving 1'i!r low so that
the addressed device can put its data on the bus.
The SuperB samples this data prior to raising ~
high.
12.6.1 External
~ory
Operations
Whenever the SuperB is configured for external
memory operations, the addresses of all internal
program memory references appesr on the externsl
bus. This should have no effect on the external
system since the bus control line 1'i!r remains in
its inactive high state. 1'i!r becomes active only
during external memory references.
12~7
ElCTEPIDrD BUS lINING
The SuperB can accommodate slow memory access and
cycle times by three different methods that give
the user much flexibility in the types of memory
available.
12.7.1
Soft~e
Progrs=mable Wait States
The SuperB can stretch the Data Strobe (~ timing
automatically by adding one, two, or three
internal 'clock periods.
This· is under program
control and app 1ies only to external memory
cycles.
Internal memory cycles still operate at
the maximum rate.
The software has independent
control over stretched 'Data Strobe for external
memory (i.e., the software can set up one timing
for program memory and a different timing for data
memory).
Thus, program and data memory may be
made up of different kinds of hardware chips, each
requiring its own timing.
603
External Interface
12.7.2
Slow Meoory Timing
All of the extended bus timing features are
programmed by writing the appropriate bils in the
Externa I Memory Timing register (Figure 12-9).
.
r:=
Another feature of the SuperB that is useful in
interfacing with slow memories is the Slow Memory
Timing option. When this option is enabled, the
normal external memory timing is slowed by a
factor of two (bus clock = CPU. clock divided by
two).
All memory times for set-up, duration,
hold, and access times are essentia11 y doubled.
This feature can also be used with the pr~grammed
automatic wait states described above. Programmed
wai t states can st i 11· be used to stretch the Data
Strobe time by one, two, or three internal clock
times (not two, four, or six) when Slow Memory
Timing is enabled.
A2S. BANKO (FE) EMT
EXTERNAL MEMORY TIMING REGISTER
I~I~I~I~I~I~I~I~I
.-
DATA MEMOAY AUTOMATIC WAITS
00 NO WAITS
01
1 WAIT
10 = 2 WAITS
11
3 WAITS
=
=
=
PROGRAM MEMORY AUTOMATIC WAITS
00 = NO WAITS
01
1 WAIT
10 = 2 WAITS
11
3 WAITS
=
=
' - - - , - - - - - - - - - SLOW MEMORY TIMING
0= DISABLED
1 = ENABLED
' - - - - - - - - - - - EXTEANAL WAIT INPUT
o = P3,IS NOAMAL 110
1 = P34 ,IS EXTERNAL WAIT INPUT
12.7.3 Hardware tlait States
Still another SuperB feature is an optional external VIAfT input using port pin P34' The VIAfT input
function can be used with either or both of the
above two features.
Thus the Data Strobe width
will have a minimum value determined by the number
of programmed wait states selected. and/or by Slow
Memory Timing. The mITT input provides the means
to stretch it even farther.
The VIAfT input is
sampled each internal clock time and, if held low,
can stretch the Data Strobe by adding one internal
clock period to the Data Strobe time for an
indefinite period of time.
Figure 12·9. EKternal Memory Timing Register
12.8
INSTRUCTION TIMING
The high throughput of the SuperB is due, in part,
to the use of instruction pipelining, where the
instruction fetch and execution cycles are overlapped. During the execution of the current
instruction, the opcode of the next instruction is
fetcned, as illuatrated in Figure 12-10.
IHTERftAL
CLOCK
INSTRUCTION
N
INSTRUCTION
"+1
INSTRUCTION
FETCH 1
I
INSTRUCTION
FETCH 2
.
OPERAND
FETCH(ES)
J
ALU STORE
, EXECUTION CYCLE
INSTRUCTION
FETCH 1
.
INSTRUCTION
FETCH 2
INSTRUCTI014
EFFECTIVE
- - - -.... 1 Q
HIDDEN DELAY
.. I
I •.
EXECUTION TIME
UNTIL COMPLETION
1 .......- - - - - - - - - ' N s T R u c T , O N COMPLETION T , M E o - - - - - - - - - -__
,1
Figure 12·10. Instruction Pipelining
ALU STORE
EXECUTION CYCLE
INSTRUCTION
FETCH 1
"+2
604
.
OPERAND
FETCH{ES)
INSTRUCTION
FETCH 2
.
External Interfgce
figures 12-11 through 12-14 show typicel instruction cycle timing for instructions fetched from
external memory.
All instruction fetch cycles
have the seme machine timing regardless of whether
the memory is internal. or external' except when
external memory timing is extended. In order to
calculate the execution time of a program, the
i~ternal clock periods shown in the cycles column
of the instruction formats in the Instruction Sat
(Chapter 5) should be added. Pipeline cycles are
transparent to the user and should be ignored.
Each cycle represents two cycles of the cryatal or
input clock.
M,
T,
M,
T,
T,
T,
T,
T,
T,
T3
CLOCK
PO
-----'
PI ________-JXC~~~A~7~~------~~~--------------------------------~
m
m
\~------~--------------~/
\1-----/
--'1
RtW _ _ _
/---FETCH INSTRUCTION - - - - + - - - - - - - F E T C H 1ST BYTE OF NEXT INSTRUCTlON------!
Figure 12-11. lYplcallnstructlon Cycle Timing (One Byte Instruction)
M,
M,
CLOCK
PO _______
--i~________A~8:..-A..;,::.,
_______ ..._________.;,;A:. .-.;,;A.:.:, ________ ...__________. ;A.: . -_A,: :,__________
~
~
PI ________~~r~A;~~A;7~~------~~~-------~::~~A~7~)--------~~.
\'---~/
\....-----~/
\,-__
~r--
...,,1
RiW _ _ _ _
i--FETCH 1ST BYTE
---+t---- FETCH 2ND BYTE--~+- FETCH 1ST BYTE OF NEXT INSTRUCTION
Figure 12-12. 1\tplcallnstructioi'l Cycle Timing (lWo Byte Instruction)
605
External Interface
PO ______-J~______~~_______"~______~~~______J~_ _ _ _ _ _ _ _~~~_ _ _ _ _ _ _ _~
P1
==~=>____<
\,-_ _~f
\,-_ _~f
\'-_ _--1f
--'7
R/W _ _ _ _
I - - - F E T C H 1ST BYTE - - - - - t - - - F E T C H 2ND BYTE
If-,.~----FETCH 3RD BYTE - - - - -
Figure 12~13. Typical Instruction Cycle Timing (Three Byte Instruction)
M,
M,
M,
PO _ _ _- ' ' - _ _ _--'-''-'''' _ _ __ " ' -_ _ _--''-'-'''--_ _-J'-_---'_-'-''-''--_ __"
P1
'-_ _ _--"'=-_-,-__
==~=>____<
\'-__--'f
os
\'-_ _--1f
\,-_ _~f
\,-_ _~I
--'7
R/W _ _ _ _
I - - - F E T C H 1ST BYTE
- - 1_ _ _ FETCH 2ND B Y T E - - - I - - - - F E T C H 3RD BYTE - - - I - - - - F E T C H 4 T H B Y T E - - I
Figure 12·14. Typical Instruction Cycle Timing (Four Byte Instruction)
606
G~ossary
addressing w~de: The way in which the location of
an operand is specified. There are seven addressing modes: Register, Indirect Register, Indexed,
Direct Address,
Indirect Address,
Relative
Address, and Immediate.
In this UART mode, the data
auto-echo code:
coming in on the Receive Data pin is reflected out
on the Transmit Data pin.
The receive section
still listens to the receive data input; however,
the data from the transmit section goes nowhere.
base address: The address used, along with an
index and/or displacement value, to calculate the
effective address of an operand. The base address
is located in "a general-purpose register, the
Program Counter, or the instruction.
baud-rate generator: The UART has its own on-chip
programmable baud-rate gen~rator that consists of
two B-bit Time Constant registers that hold the
time constant value, a 16-bit Timer/Counter that
counts down, and a flip-flop at the output
producing a square wave.
bi-value code: A SuperB counter/timer operating
mode wherein the Time Constant and Capture
registers alternate in loading the counter.
byte: A data item containing B contiguous bits.
A byte is the basic data unit for addressing
memory and peripherals.
Direct ~ry Access (OMAhAn on-chip channel
that provides high-speed transfers of data directly between memory and peripheral devices.
exception: A condition or event that alters the
usual flow of instruction processing. The SuperB
CPU supports two types" of exception: reset and
interrupts.
extended bus tieing: The SuperB has the capability of stretching the Data Strobe timing by 1, 2,
or 3 internal clock periods during external memory
accesses. The software can set up one timing for
program memory and a different timing for data
memory.
Fast
interrupt
fESt
interrupt processing:
processing completes the interrupt servicing in 6
clock periods instead of the usual 22.
flag register: This register is used to suppl y
the status of the SuperB CPU at any time.
flag':
A dedicated register that saves the
contents of the Flag register when a fast interrupt occurs.
ganeral-purpnse registers: The 325 registers that
can be used as accumulators, address pointers,
index registers, data registers, or stack registers.
handshaking channels: The SuperB has two identihandshaking channels which operate in two
modes--"fuUy interlocked" or two-wire mode, and
"strobed" or single-wire mode.
capture: A "capture on external event" feature of
the SuperB that takes a snapshot of the counter
when a certain event occurs.
cal
data memory: A memory address space that can hold
only data to be read or written, not instruction
code; data memory is always external to the
SuperB.
Im=ediate (1M) addressing mode: In this mode, the
operand is contained in the instruction.
Deskew Counter: A 4-bit counter in each handshaking channel that is used to count processor
clocks between the time that valid data is available at the port and the handshake signal indicates that data is available.
Direct Address (DA) addressin!:/' mode: In this
mode, the effective address is contained in the
instruction.
Indexed (X) addressing !::Ode: In this mode, the
contents of an index register are added to the
contents of a specified working register or working register pair, which holds the index value
desired.
Indirect Address (IA) addressing lOOde: In this
mode, the instruction specifies a pair of memory
locations and this se lected pair, in turn, contains the actual address of the instruction to be
executed.
607
Glossary
Indirect Register (IR) addressing mode: In this
mode, the contents of the specified register or
register pair is the address of the operand.
Register (R) addressing mode: In this mode, the
operand value is the contents of the specified
register or register pair.
Instruction Pointer: A 16-bit register that acts
as Program Counter for a threaded-code language,
such as Forth, or can be used ,in the fast interrupt processing mode for' special interrupt
handling.
register file: One of the three types of address
spaces supported by the SuperB CPU. Register file
address space is an internal register file composed of 325 B-bit wide registers that are logically
div ided into 32 working register groups of eight
registers each.
interrupt: An asynchronous exception generated by
a peripheral device that needs attention.
The
interrupt structure of the SuperB contains 27 different interrupt sources, 16 vectors, and B
levels.
interrupt level: Interrupt levels provide the top
level of priority assignment and can be changed by
programming the Interrupt Priority register.
Interrupt Priority register (IPR): This register
assigns 192 different combinations of priority
when more than one interrupt level is pending.
interrupt source: An interrupt source is anything
that generates an interrupt, internal or external
to the SuperB.
interrupt vector: The vector number is used to
generate the address of a particular, interrupt
servicing routine.
local loopback mode: In this mode, the data output from the transmit section of the UART is also
routed back to the receive section.
pipelining: Instruction pipelining is a c~mputer
design technique in which the inst ruction fetch
and execution cycles are overlapped. ,Thus, duri~g
the execution of the current instruction, the
opcode of the next instruction is fetched, resulting in high throughput.
Program Counter (PC): The 16-bit Program Counter
controls the sequence of instructions in the
currently executing program and is not an addressable register.
progrlllll memory: A memory address space that can
hold code or data; program memory can be internal
or external to the SuperB.
read access: The type of memory access used by
the CPU for fetching data operands and instructions.
608
Register Pointer (RP):
The two register pointers
are system registers that contain t~e base address
of the two active working register groups of the
register file.
Relative Address (RA) addressing IJOde: In this
mode, the displacement in the instruction is added
to the contents of the Program Counter to obtain
the effective address.
reset: A CPU operating state or exception that
results when a reset request is signaled on the
mrr line. A reset initializes the Program
Status registers.
51011 t~emory timing: An optional feature of the
SuperB in which normal external memory timing is
'slowed by a factor of two.
Stack Pointer (SP): A 16-bit register pair indicating the top (lowest address) of the processor
stack and used by the Call instruction and
interrupts to hold the return address.
systec registers: System registers govern the
operation of the CPU and may be accessed using any
of the instructions that reference the register,
file using the Direct addressing mode.
Universal
Asynchronous
Receiver/Transmitter
(UART): A full duplex asynchronous channe 1 that
transmits and receives independently with 5 to B
bits per character, options for even or odd
parity, and an optional wake-up feature.
wake-up feature: A feature of the UART wherein
pattern match logic detects, a pre-sped Hed data
pattern at the receiver; the pattern can include
both the received character and a special wake-up
bit.
write access: The type of memory access used by
the CPU for storing data operands.
."
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June 1987
ZS®ZS611 MeU
Military Electrical Specification
,Z8603 Prototyping Device with 2K EPROM Interface
Features
• Complete microcomputer, 2K (8601) or 4K
(8611) bytes of ROM, 128 bytes of RAM, 32
I/O lines, and up to 62K (8601) or 60K (8611)
bytes addressable external space each for
program and data memory.
144-byte register file, including 124 general-,
purpose registers, four I/O port registers,
and 16 status and control registers.
III Average instruction execution time of 1.5 /Ls,
maximum of 1 /LS.
IiiI Vectored, priority interrupts for I/O,
counter/timers, and UART.
IllI
General
Description
The Z8 microcomputer introduces a new level
of sophistication to single-chip architecture.
Compared to earlier single-chip microcomputers, the Z8 offers faster execution; more
efficient use of memory; more sophisticated
interrupt, input/output and bit-manipulation
capabilities; and easier system expansion.
Under program control, the Z8 can be tailored
to the needs of its user. It can be configured as a
PORT 2
(BITPRc)'
GRAMMABLE)
110
PORT 1
(BYTE
PROGRAMMABLE)
110 OR ADo-AD,
Flguro I. Pin Functiollll
Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.
E:l Register Pointer so that short, fast instructions can access any of nine working register
groups in 1 /LS.
C On-chip oscillator which accepts crystal or
external clock drive.
III Single + 5 V power supply-all pins TTL
compatible.
1\1
13,
12.5 MHz.
stand-alone microcomputer with 4K bytes
of internal ROM, a traditional microprocessor
that manages up to 124K bytes of external
memory, or a parallel-processing element in a
system with other processors and peripheral
controllers linked by the Z-BUSIRQ3
1 = IRQ3 :> IRQ5
1·1
,.g, iD, I
II' '......
RESERVED = 000
. . ._
C :> A :> B M
= 001
A:>8>C=010
A :> C :> B
011
8 :> C :> A ." 100
c :> B > A = 101
B:> A:> C = 110
RESERVED = 111
IRao, IRQ2 PRIORITY (aROUP B)
o = IRQ2
> IRDO
1 '" IROO > IRQ2
IRQ1, IRQ4 PRIORITY (GROUP C)
o .: IRQ1 > IRQ4
1 ::: IRQ4 > IRQ1
=
LDON'TCARE
REGISTER
POINTER
)
,
R254 SPH
Stac:k Pointer
(FEH; ReadIWrite)
R2somQ
Interrupt Request Register
(FAH; ReadIWrite)
l~i~:~i~f~I~I~!~1
RESERVED
:::r-
I '
L=-:
tROO
IRQl
IRQ2
IRQ3
IRQ4
IRQS
~
..
INPUT (00 .. IRQO)
.. P33 INPUT
P31 INPUT
.. P30 INPUT. SERIAL INPUT
.. To. ,SERIAL OUTPUT
.. T1
=
R255 SPL
Stac:k Pointer
(FFH; ReadIWrite)
R251lMR
Interrupt Mask Register
(FBH; ReadIWrlte)
____L=-:
__-,'100·,RCO,
ENABLES IRCO-IRQS
.IILRESERVED
' - - - - - - - - 1 ENABLES INTERRUPTS
Figure 13. Control Registers (Continued)
620
IL--_
STACK POINTER LOWER
BYTE fSPD~SPP)
Opcode
Lowor Nlbblo (Holt)
Map
o
6,5
o
6,5
DEC
5
..
B
0
0
~
:9
z
~
Do
Do
t:)
7
0
C
0
E
F
9
10,5
10,5
10,5
6,5
6,5
LD
LD
[1,R2
I2,Rl
DEC llDD llDD llDD llDD llDD llDD
lR.,Hl
Hl,lM
lRl,lM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
HI
lRl
n,12
II, III
H.,Hl
lR.,Hl
Hl,lM
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
E
C
12110,5
12110,0
6,5
12110,0
6,5
OJNZ
JR
LD
JP
INC
n,RA
cc,HA
n,lM
cc,DA
n
lRl,lM
lRl,lM
Rl
lRl
n,l2
r},Irz
H.,Hl
lR.,Rl
Hl,lM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
lRRl
1M
r:z
Il,Il:Z
R.,Rl
lR.,Hl
Hl,lM
lRl,lM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
OA
OA
OR
OR
OR
OR
OR
OR
lRl,lM
II.
HI
lRl
n.r:
Il,Irz
H.,Hl
lR.,Hl
Hl,lM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
HI
6,5
lRl
6,5
II, [2
ll,Irz
6,5
R.,Hl
lR.,Hl
Hl,lM
lRl,lM
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
HI
lRl
n,I:Z
Il,I12
H.,Hl
lR.,Hl
Hl,lM
lRl,lM
10112,1 12114,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH PUSH
TM
TM
TM
TOO
TOO
TM
H2,Hl
lR.,Hl
Hl,lM
IHl,1M
H.
lR.
II, 12
ll,I12
10,5
10,5
12,0
18,0
OECW OECW LDE
LDEI
lRl
6,5 .
n,IIll
III,rIll
12,0
18,0
RL
RL
LOE
LDEI
HI
lRl
10,5
10,5
F
I---
r--I--'I---
r--r--I---
r--6,1
01
~
6,1
EI
lIn IU/lrr!
6,5
!NCW INCW
lRl
10,5
6,5
10,5
10,5
CP
CP
CP
CP
CP
CP
II,12
Il,Irz
H.,Hl
lR.,Hl
Hl,lM
lRl,lM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
XOR
XOR
XOR
XOR
XOR
XOR
HI
lRl
II, f3
H.,Hl
IR:z.RI
Hl,lM
lRl,lM
6,5
6,5
12,0
Il.lu
18,0
RRC
RRC
LDC
LDCI
HI
lRl
6,5
SM
HI
lRl
20,0
20,0
CALL"
CALL
LD
lRHl
DA
r2,::, HI
6,5
6,5
10,5
RR
RR
LD
LO
10,5
10,5
10,5
LD
LD
LO
HI
lRl
H.,Hl
8,5
8,5
Illlu
6,5
lR.,Hl
Hi,IM
IHl,1M
12. lIn Iu"Irrl
6,5
lRl
--v==
'--6,5
LD
6,5
SWAP SWAP
16,0
IRET
nil:. Rz
SM
LOCI
14,0
RET
I---
10,5
n , b I 2 Irl,Irr2
12,0
18,0
LDC
r---
10,5
CLR
\.
D
D
RLC llDC llDC llDC llDC llDC llDC
6,5
HI
ByloD por
IDIluuctioD
o
H.,Hl
HHI
B
10,5
7
n,Iu
6,5
Ii
6,5
G
II, [2
HHI
9
6,5
5
lRl
3
4
3
HI
RLC
:I
:I
10,5
LD
Ill, 12
H.,lRl
'=
2
'V"
3
RCF
6,5
SCF
6,5
-
10,5
LD
.,
-
CCF
6,0
NOP
..I
"-"'==-~-"'v-"'~~---"';"" - - - :I
3
LowCl'
Opcodo
Nlbblo
E:tOCUliOD
CyclC!l
~
Plpollno
CyclC!l
LagoDd:
R = 8-Blt Addr.so
r = 4-Blt Addre..
Upper
Opcodo-A
Nlbblo
Mnemonic
RI or", = Dst Address
H, or .. = Src Addresa
SequODCO:
Fint
Operand
Opcode, First Operand, Second Operand
Note: The blanlt areas are not defined_
"'2·byte instruction; fetch cycle appears as a 3·byte instruction
621
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150 °C
Standard
Test
Conditions
Stresses greater than those listed under Absolute Maxi·
mum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in tr.e operational sections
of- these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The DC characteristics listed below apply for
the following standard test conditions, unless'
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin.
Standard conditions are:
o +4.75 V :S Vee :S +5.25
o GND = 0 V
o O°C :S TA :S +70°C
+5V
2.11(
V
Figure 14. Test Load 1
DC
Characteristics
622
Symbol
Parametor
Min
Max
Unit
COndition
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
V1H
Input High Voltage
2.0
Vee
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRL
Rese! Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
IOL
Output Leakage
IIR
Icc
V
IoH
= -250 p.A
0.4
V
IoL
= +2.0 rnA
-10
10
p.A
0 V:s VIN
:S
+5.25 V
-10
10
p.A
0 V:s VIN
:S
+5.25 V
Reset Input Current
-50
p.A
Vee
Vee Supply Current
150
rnA
2.4
= +5.25 V, VRL = 0 V
AC Characteristics
External I/O
or Memory
Read and
Write Timing
PORT 0,
DiI
POATi
iii
__~~~~__~~~I~------~0r---~Ir-__+-___
(READ)
Do.. Dr OUT
PORT 1
iii
(WRITE)
Figuro 15. External I/O or Memory Road/Writo
No.
Symbol
Parameter
Min
1
TdA(AS)
Address Valid to AS t Delay
35
2
TdAS(A)
AS t to Address Float Delay
45
3
TdAS(DR)
AS t to Read Data Required Valid
4
TwAS
AS Low Width
5
TdAz(DS)
Address Float to DS ~
Max
Notes..tO
2,3
2,3
220
1,2,3
q,3
55
0
DS (Read) Low Width
185 - - - - - - - 1 , 2 , 3
7
TwDSW
DS (Write) Low Width
110
8
TdDSR(DR)
DS ~ to Read Data Required Valid
9
ThDR(DS)
Read Data to i'5S t Hold Time
10
TdDS(A)
DS t to Address Active Delay
45
2,3
11
TdDS(AS)
DS t to AS ~ Delay
55
2.3
6-TwDSR
1,2,3
130
1,2,3
0
30 - - - - - - - 2 , 3
12 - TdR!W(AS) - - RlWValid to AS t Delay
13 TdDS(RIW)
i'5S t to RIW Not Valid
2,3
35
14
TdDW(DSW)
Write Data Valid to DS (Write) ~ Delay
35
2,3
15
TdDS(DW)
i'5S t. to Write Data Not Valid Delay
45
2,3
16
TdA(DR)
Address Valid to Read Data Required Valid
17
TdAS(DS)
AS t to DS ~ Delay
NOTES:
1. When using extended memory timing add 2 TpC.
2. Tbll:ing numbers given are for minimum TpC,'
3. See' clock cycle time dependent characteristics table.
255
55
1,2,3
2,3
t Test Load I.
• AU timing references use 2.0 V lora logic "I" and 0.8 V fora logic '0".
* All units in nanoseconds (ns).
623
AC Characteristics
Additional
Timing
Table
CLOCK
T,.
IRQN
Figure 16. Additional Timing
No.
2
Symbol
Parameter
TpC
Input Clock Period
TrC,TlC
Clock Input Rise And Fall Times
Min
Max
80
1000
Notes·
15
TwC
Input Clock Width
26
3
4
TwTinL
Time InputLow Width
70
2
5 - TwTinH - - - Timer Input High Width - - - - - - - - - - - - - - - - - 3 T p C - - - - - - - - - 2
6
TpTin
Timer Input Period
7
TrTin,TfTin
Timer Input Rise And Fall Times
8TpC
8a
TwIL
Interrupt Request Input Low Time
70
2,3
8b
9
TwIL
TwIH
Interrupt Request Input Low Time
Interrupt Request Input High Time
3TpC
3TpC
2.4
2,3
NOTES:
1. Clock timing references uses 3.8 V for a logic "1" emd 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "1" dnd 0.8 V for
a logic "0".
2
100
2
3. Interrupt request via Port 3 (P3r-P33).
4. Interrupt request via Port 3 (P30)'
.. Units in nanoseconds (ns).
'
Memory Port
Timing
ADDRESS VALID
DON'T CoUll
DATA IN VALID
Figure 17. Memory Port Timing
No.
Symbol
Parameter
2
TdA(DI)
ThDI(A)
Address Valid to Data Input Delay
Data In Hold time
Min
Max
Notes·
320
1,2
a
NOTES:
1. Test Load 2.
2. This is a Clock-eyde-Dependent parameter. For clock frequencies
other than the maximum, use the following formula: 5 TpC - 95
624
"Units are nanoseconds unless otherwise specified.
Handshalte
Timing
OA~;'~;
__________
~~-'----~-:;;.".:
.~
___________
ROY
'{OUTPUT)
Flguro 18a. IDput Haudshaho
DATA OUT
DAV
(OUTPUT)
ROY
DATA OUT VALID
~
--~~----------------
_ _)!=~0~g~~
(INPUT)
Figure l8b. Output Haudshaho
No.
Parameter
Symbol
Min
Max
Notoa'"
TsDI(DAV)
Data In Setup Time
o
2· ThDI(DAV)
160
Data In Hold time
120
3
TwDAV
Data Available Width
4
TdDAVIf(RDY)
DlW! Input to RDY ! Delay
120
1,2
S-TdDAVOf(RDY)--DAV ! Output to RDY ! D e l a y - - - - - - - - - - - - . 0 - - - - , - - - - - - 1 , 3
6
TdDAVIr(RDY)
DAV tInput 10 RDY i Delay
120
1,2
1,3
7
TdDAVOr(RDY)
o
DAV i Output 19 RDY i Delay
8
TdDO(DAV)
30
Data Out to DAV ! Delay
9
TdRDY(DAV)
o
140
Rdy ! Input to DAV i Delay
NOTES:
I. Test1""d1
2. Input handshake
3. Output handshake
t All timing references use 2.0 V for a logic "I" and O.B V for
a logic "0".
ClockCycle-Time- Number
Dependent
Characteristics
Symbol
.. Units -in nanoseconds (ns).
Equation
TdA(AS)
TpC-SO
TdAS(A)
2
TpC-40
TdAS(DR)
4TpC-110*
3
4
TwAS
TpC-30
S--TwDSR-------------3TpC-6S*-------------
7
TwDSW
8
TdDSR(DR)
10
Td(DS)A
11
TdDS(AS)
12--TdRIW(AS)
13
TdDS(RIW)
TdDW(DSW)
14
TdDS(DW)
IS
TdA(DR)
16
TdAS(DS)
17
2TpC-SS*
3TpC-120*
TpC-40
TpC-30
TpC-SS - - - - - - - - - - . TpC-SO
TpC-SO
TpC-40
STpC-160*
TpC-30,
•Add 2TpC when using extended memory timing.
625
MIL·STD·883 MILITARY PROCESSED PRODUCT
•
Mil-Std-883 establishes uniform methods and procedures for testing microelectronic devices to insure the
electrical, mechanical, and environmental integrity and
reliability that is required for niilitary applications.
•
Mil-Std-883 Class B is the industry standard product
assurance level for military ground and aircraft·
application.
• The total reliability of a system depends upon tests that
are designed to stress specific quality and reliability
concelins that affect microelectronic products.
• The following tables detail the 100% screening and electrical tests, sample electrical tests, and Qualificationl
Quality Conformance testing required.
Zilog Military Product Flow
ENVIRONMENTAL SCREENING
.. STABILIZATION BAKE
• TEMPERATURE CYCLE
D CENTRIFUGE
626
Table I
MIL-STO-883 Class B Screening Requirements
Method 5004
Test
Mil-Std-883
Method
Test Condition
Requirement
2010
Condition B
Stabilization Bake
1008
Condition C
100%
Temperature Cycle
1010
Condition C
100%
Constant Acceleration (Centrifuge)
2001
Condition E or D(Note 1), Y1 Axis Only
100%
Zilog Military Electrical Specification
Static/OC Tc = + 25°C
100%
Condition D(Note 2), 160 hours,
TA = + 125°C
100%
Interim Electrical Tests
Zilog Military Electrical Specification
Static/DC Tc = + 25°C
100%
PDA Calculation
PDA
Final Electrical Tests
Zilog Military Electrical Specification
Static/DC Tc = + 125°C, - 55°C
Functional, Switching/AC Tc = + 25°C
100%
Internal Visual
Initial Electrical Tests
Burn-In
1015
= 5%
100%
100%
Fine Leak
Gross Leak
1014
1014
Condition A2
ConditionC
100%
100%
Quality Conformance Inspection (QCI)
Group A
Each Inspection Lot
Group B
Every Week
Group C
Periodically (Note 3)
Group D
Periodically (Note 3)
5005
5005
5005
5005
(See Table II)
(See Table III)
(See Table IV)
(See Table V)
Sample
Sample
Sample
Sample
External Visual
2009
QA-Ship
100%
100%
NOTES:
1. Applies to larger packages which have an inner seal or cavity perimeter of two inches or more in total length or have a package
mass of ;;>5 grams.
2. In process of fully implementing of Condition D Burn·ln Circuits. Contact factory for copy of specific burn·in circuit available.
3. Performed periodically as required by Mil·Std·883, paragraph 1.2.1 b(17).
627
Table II Group A
Sample Electrical Tests
. MIL-STD-883 Method 5005
~
LTPD
Max Accept = 2
Subgroup
Tests
Temperature (Tc)
Subgroup 1
StaticlDC
+25°C
2
Subgroup 2
StaticlDC
+ 125°C
3
Subgroup 3
StaticlDC
-55°C
5
Subgroup 7
Functional
+25°C
2
Subgroup 8
Functional
-55°C and + 125°C
5
Subgroup 9
SWitching/AC
+25°C
2
Subgroup 10
Switching/AC
+ 125°C
3
Subgroup 11
Switching/AC
-55°C
5
NOTES:
• The specific parameters to be included for tests in each subgroup shall be as specified in the applicable detail electrical specification. Where no
parameters have been identified in a particular subgroup or test within a subgroup, no Group A testing is required for that subgroup orteS!.
• A single sample may be used for all subgroup testing. Where required size exceeds the lot size, 100% inspection shall'be allowed.
• Group A testing by subgroup or within subgroups may be performed in any sequence unless otherwise specified.
628
Table III Group B
Sample Test Performed Every Week to
Test Construction and Insure Integrity of Assembly Process.
MIL-STD-883 Method 5005
Subgroup
Subgroup 1
Physical Dimensions
Mil-Std-883
Method
Quantity or
Test Condition
LTPD/Max Accep~
2016
2/0
2015
4/0
Subgroup 2
Resistance to Solvents
Subgroup 3
Solderability
2003
Solder Temperature
+ 245°C ± 5°C
15(Note 1)
Subgroup 4
Internal Visual and Mechanical
2014
1/0
Subgroup 5
Bond Strength
2011
C
15(Note2)
Subgroup s(Note 3)
Internal Water Vapor Content
1018
1000 ppm.
maximum at + 100°C
3/0 or 5/1
Subgroup 7(Note 4)
Seal
7a)Fine Leak
, 7b) Gross Leak
Subgroup 8(Note 5)
Electrostatic Discharge Sensitivity
5
1014
7a) A2
7b) C
3015
Zilog Military Electrical
Specification
Static/DC Tc = + 25°C
A = 20-2000V
B = >2000V
Zilog Military Electrical
Specification
Static/DC Tc = + 25°C
15/0
NOTES:
1. Number of leads inspected selected from a minimum of 3 devices.
2. Number of bond pulls selected from a minimum of 4 devices.
3. Test applicable only if the package contains a dessicant.
4. Test not reqUired if either 100% or sample seal test is performed between final electrical tests and external visual during Class B screening.
5. Test required for initial qualification and product red~sign.
.
629
Table IV Group C
Sample Test Performed Periodically to Verify Integrity of the Die.
MIL-STD-883 Method 5005
Subgroup
Subgroup 1
Steady State Operating Life
Mil-Std-883
Method
1005
End Point Electrical Tests
Subgroup 2
Temperature Cycle
Quantity or
Test Condition
Condition o(Note 1), 1000 hours at
+125°C
1010
Condition C
2001
Condition E or o(Note 2), Y1 Axis Only
Seal
2a) Fine Leak
2b) Gross Leak
1014
End Point Electrical Tests
15
2a) Condition A2
2b) Condition C
10100r1011
Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C
NOTE:
1. In process of fully implementing Condition 0 Burn-In Circuits. Contact factory for copy of specific burn-in circuit available.
2. Applies to larger packages which have an inner seal or cavity perimeter of two inches or more in total length or have a package
mass of ;>5 grams.
630
5
Zilog Military Electrical Specification
Tc = +25°~, + 125°C, -55°C'
Constant Acceleration (Centrifuge)
Visual Examination
LTPD/Max Accept
Table V Group D
Sample Test Performed Periodically to Insure Integrity of the Package.
MIL·STD·883 Method 5005
Subgroup
MiI·Std·883
Method
Quantity or
Test Condition
LTPD/Max Accept
Subgroup 1
Physical Dimensions
2016
15
Subgroup 2
Lead Integrity
2004
Condition B2 or D(Note 1)
Subgroup 3
Thermal Shock
1011
Condition B minimum,
15 cycles minimum
Temperature Cycling
1010
Condition C, 100 cycles minimum
Moisture Resistance
1004
Seal
3a) Fine Leak
3b) Gross Leak
1014
Visual Examination
15
3a) Condition A2
3b) Condition C
10040r1010
End Point Electrical Tests
Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C
Subgroup 4
Mechanical Shock
2002
Condition B minimum
Vibration Variable Frequency
2007
Condition A minimum
Constant Acceleration (Centrifuge)
2001
Condition E or D(Note 2), Y1 Axis Only
Seal
4a) Fine Leak
4b) Gross Leak
101.4
Visual Examination
15
\
15
4a) Condition A2
4b) Condition C
1010 or 1011
End Point Electrical Tests
Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C
Subgroup 5
Salt Atmosphere
1009
Seal
5a) Fine Leak
5b) Gross Leak
1014
Visual Examination
1009
Condition A minimum
15
5a) Condition A2
5b) Condition C
Subgroup 6
Internal Water Vapor Content
1018
5,000 ppm. maximum water
content at + 100°C
3/0 or 5/1
Subgroup 7(Note 3)
Adhesion of Lead Finish
2025
15(Note4)
2024
5/0
Subgroup 8(Note 5)
Lid Torque
NOTES:
1. Lead Integrity Condition 0 for leadless chip carriers.
2. Applies to larger packages which have an inner seal or cavity
perimeter of two inches or more in total length or have a package
mass of ;;'5 grams.
3.
4.
5.
Not applicable to leadless chip carriers.
LTPD based on number of leads.
Not applicable for solder seal packages.
631
Z8® Z8681 Military
ROM less Microcomputer
June 1987
FEATURES
III Complete microcomputer, 24 I/O lines, and up to 64K
BI
bytes of addressable external space each for program
and data memory.
I1l 143-byte register file, including 124 general-purpose
I!II Register Pointer so that short, fast instructions can
access anyone of the nine working-register groups.
Ii]
UARl
IJl
UART and two programmable 8-bit
each with a 6-bit programmable
prescaler.
registers, three I/O port registers, and 16 status and
control registers.
E:l Vectored, priority interrupts for I/O, counter/timers, and
Full-duplex
counter/time~s,
Single + 5V power supply-all I/O pins TIL-compatible.
Iii! Available in 8 MHz.
On-Chip oscillator that accepts crystal or external clock
drive.
GENERAL DESCRIPTION
The Z8681 is the ROM less version of the Z8 single-chip
microcomputer. The Z8681 offers all the outstanding
features of the Z8 family architecture except an on-chip
program ROM. Use of external memory rather than a
preprogrammed ROM enables this Z8 microcomputer to be
used in low volume applications or where code flexibility is
reqlJired ..
The Z8681 can provide up to 16 output address lines, thus
permitting an address space of up to 64K bytes of data or
program memory. Eight address outputs (ADo-AD?) are
provided by a multiplexed, 8-bit, Address/Data bus. The
remaining 8 'bits can be provided by the software
configuration of Port a to output address bits A8 -A15.
632
Available address space can be doubled (up to 128K bytes)
by programming bit 4 of Port 3 (P34) to act as a data memory
select output (OM). The two states of OM together with the
16 address outputs can define separate data and memory
address spaces of up to 64Kbytes each.
There are 143 bytes of RAM located on-chip and organized
as a register file of 124 general-purpose registers, 16 control
and status registers, and three I/O port registers. This
register file can be divided into nine groups of 16 working
registers each. Configuring the register file in this manner
allows the use of short format instructions; in addition, any of
the individual registers can be accessed directly.
ABSOLUTE MAXIMUM RATINGS
Guaranteed by characterization/design
Voltages on all pins except RESET
with respecttoGND .. , ...... , ..... -0.3Vto + 7.0V .
Operating Case Temperature ........ - 55°C to + 125°C
Storage Temperature Range ........ - 65°C to + 150°C
Absolute Maximum Power Dissipation. , .......... 1.7 W
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
+5V
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND (OV). Positive current flows
into the referenced pin.
Military Operating Temperature Range (Tc)
-55°Cto +125°C
Standard Military Test Condition
+4.5 ~ VCC ~ +5.5V
Test Load
DC CHARACTERISTICS
Symbol
Parameter
Min
VCH
Clock Input High Voltage
VCl
Clock Input Low Voltage
VIH
Input High Voltage
Vil
Input Low Voltage
VRH
Reset Input High Voltage
VRl
Reset Input Low Voltage
VOH
Output High Voltage
Max
Unit
Condition
3.8 a
VCc b
V
Driven by External Clock Generator
-0.3 b
0.8 a
V
Driven by External Clock Generator
2.0a
VCc b
V
-0.3 b
0.8 a
V
3.8 a
VCc b
V
-0.3 b
0.8 a
V
IIR
Reset Input Current
-50 a
flA
= -250flA
= +2.0mA
VIN = OV, 5.5V
VIN = OV,5.5V
Vce = MAX, VRl = OV
ICC
VCC Supply CUrrent
230 a
mA
All outputs and I/O pins floating
2.4 a
V
O.4 a
VOL
Output Low Voltage
V
III
Input Leakage
-10 a
10a
flA
IOl
Output Leakage
-lO a
10a
flA
IOH
IOl
CAPACITANCE
Symbol
TA
Parameter
Max
Unit
Maximum Capacitance
15c
pi
= 25°C, f = 1 MHz.
Parameter Test Status:
a Tested
b Guaranteed
c Guaranteed by Characterization/Design
'633
x
~I
~
)(
)(
PORT 0,
OM
4
)!
PORT 1
Ao-A,
~
-
16G)
)
<
I--
LTPD
Max Accept = 2
Subgroup
Tests
Temperature (T
Subgroup 1
Static/DC
+25°C
2
Subgroup 2
Static/DC
+125°C
3
Subgroup 3
Static/DC
-55°C
5
Subgroup 7
Functional
+25°C
2
Subgroup 8
. Functional
-55°C and + 125°C
5
Subgroup 9
Switching/AC
+25°C
2
Subgroup 10
Switching/AC
+125°C
3
Subgroup 11
Switching/AC
-55°G
5
NOTES:
• The specific parameters to be included for tests in each subgroup shall be as specified in the applicable detail electrical specification. Where no
parameters have been identified in a particular subgroup or test within asubgroup, no Group A testing is required for that subgroup or test.
• A single sample may be used for all subgroup testing. Where required size exceeds the lot size, 100% inspection shall be allowed.
• Group A testing by subgroup or within subgroups may be performed in any sequence unless otherwise specified.
641
Table III Group B
Sample Test Performed Every Week to
Test Construction and Insure Integrity of Assembly Process.
MIL-STD-883 Method 5005
Subgroup
Subgroup 1
Physical Dimensions
Mil-Std-883
Method
Quantity or
Test Condition
LTPD/Max Accept
2016
2/0
2015
4/0
Subgroup 2
Resistance to Solvents
Subgroup 3
Solderability
2003
Solder Temperature
+245°C ± 5°C
15(Note 1)
Subgroup 4
Internal Visual and Mechanical
2014
1/0
SubgroupS
Bond Strength
2011
C
15(Note 2)
Subgroup s(Note 3)
Internal Water Vapor Content
1018
1000 ppm.
maximum at +100°C
3/0 or 5/1
Subgroup 7(Note 4)
Seal
7a) Fine Leak
7b) Gross Leak
Subgroup 8(Note 5)
Electrostatic Discharge Sensitivity
5
1014
7a) B
7b) C
3015
Zilog Military Electrical
Specification
Static/DC Tc = + 25°C
A = 20-2000V
B = >2000V
Zilog Military Electrical
Specification
StaticlDC Tc = + 25°C
15/0
NOTES:
1. Number of leads inspected selected from a minimum of 3 devices.
2. Number of bond pulls selected from a minimum of 4 devices.
3. Test applicable only if the package contains a dessicant.
4. Test not required if either 100% or sample seal test is performed between final electrical tests and external visual during Class B screening.
5. Test required for initial qualification and product redesign.
642
Table IV Groi.Jp C
Sample Test Performed Periodically to Verify Integrity of the Die.
MIL-STD-883 Method 5005
Subgroup
Subgroup 1
Steady State Operating Life
Mil-Std-SS3
Method
1005
End Point Electrical Tests
Quantity or
Test Condition
LTPD/Max Accept
Condition D(Note 1), 1000 hours at
+ 125°0
5
Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C
Subgroup 2
Temperature Cycle
1010
Condition C
Constant Acceleration (Centrifuge)
2001
Condition E or D(Note 2), Y1 Axis Only
Seal
2a) Fine Leak
2b) Gross Leak
1014
Visual Examination
End Point Electrical Tests
15
2a) Condition B
2b) Condition C
1010or1011
Zilog Military Electrical Specification
Tc = +25°C, +125°C, ...,.55°C
NOTE:
1. In process of fully implementing Condition D Burn-In Circuits. Contact factory for copy of specific burn-in circuit available.
2.. Applies to larger packages which have an inner seal or cavity perimeter of two inches or more in total length or have a package
mass of ~5 grams.
643
Table V Group D
Sample Test Performed Periodically to Insure Integrity of the Package.
MIL-STD~883 Method 5005
Mil-Std-883
Method
Subgroup
Test Condition
Subgroup 1
Physical Dimensions
2016
Subgroup 2
Lead Integrity
2004
Condition
Subgroup 3
Thermal Shock
1011
Condition B minimum,
15 cycles minimum
Condition C, 100 cycles minimum
Temperatur~
Cycling
1010
Moisture Resistance
1004
Seal
3a) Fine Leak
3b) Gross Leak
1014
Visual Examination
1004 or 1010
15
B2
or D(Note 1)
2002
Condition B minimum
2007
Constant Acceleration (Centrifuge)
2001
Condition Aminimum
Condition E or D(Note 2), Y1 Axis Only
Seal
4a) Fine Leak
4b) Gross Leak
1014
15
4a) Condition B
4b) Condi~ion C
1010or1011
End Point Electrical Tests
SubgroupS
Salt Atmosphere
Seal
5a) Fine Leak
5b) Gross Leak
Visual Examination
15
Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55"C
Vibration Variable Frequency
Visual Examination
15
3a) Condition B
3b) Condition C
End Point Electrical Tests
Subgroup 4
Mechanical Shock
Quantity or
LTPD/Max Accept
Zilog Military Electrical Specification
Tc = +25°C, +125°C, -55°C
1009
Condition A minimum
15
1014
5a) Condition B
5b) Condition C
1009
Subgroup 6
Internal Water Vapor Content
1018
Subgroup 7(Note 3)
Adhesion of Lead Finish
2025
15(Note4}
Subgroup 8(Note 5)
Lid Torque
2024
5/0
NarES:
1. Lead Integrity Condition Dfor leadless Chip carriers.
2. Applies to larger packages which have an inner seal or cavity
perimeter of two inches or more in total length or have a package
mass of ~5 grams.
.
644
5,000 ppm. maximum water
content at + 100°C
3. Not applicable to leadless chip carriers.
4. LTPD based on number of leads.
5. Not applicable for solder seal packages.
3/0 or 5/1
PACKAGE INFORMATION
10
18
18·Pin Ceramic Package
!:~~~~'~:::::::I
0.300
1-0.320-
0.025
0.030
-I. 0.065~
B1.
I--~'~~~-i.
-:015'
~0.920~
MAX
~ --11-- 0.040
0.130
if~n'M?l
~I.
0.009
0
.015,
0.050
=.015
r-
:.:1t-
g:g~~
1£
r,
0.100-1
TYP
0.125
MIN
18·Pin Plastic Package
NC?T~:
645
Package dimensions are giv~n il') inches. To convert to millimeters. multiply by 25.4
PACKAGE INFORMATION (Continued)
C-I.4~
MAX
,;:--,
~WJ~
~~
~1.--.....--1
~t "'21 L.·...
~
AEF
I
.007
~~
--I L.m --IL.·02'
6liil
D.OD
MIN
0.010
·
O]ib
SOTH ENDS
~
28·PIIl CeramI. Paaa;.
~=~=L~
~lli-
I~+
0150'
1---......
--'--------1
0121
M'N
,0.040
-
0100MAX
(...iOTH END•
.
....I
(...·m
0.100
';
I
I
I
0.01'
--I(...·m
••020
28-PIIl Cercllp Pae.kap
28-PIIl Plastl. Pae.kap
NOTE: PacltaQe di.meNionl ant qiven In Inebel. To convert to millimeter'll, multiply by 25,4.
646
PACKAGING INFORMATION
40
21
T
0.560
I ~;: :;=r=;= r=r=: ;:=;=;= ;=;=r =n= ;=;= r;: : ;=r=;=;=;=r: :;=;=;=,=n=n=;=:l
20
40-pin Plastic DIP
'~I·
21
~~-n-rrrrTTO"rr"TTTT-n-rrrrrrT,,'-rr"TTTT,-J
'r
20
----~o.:----
0230
0.056
'AAL~
.t Ij
MIN
0.040
±.020
1.-11.\',",ji'oo
'I.-~.~ -4l.-t~!
TYP
TYP
40-pin Cerdip Pacltage
NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.
647
PACKAGE INFORMATION (Continued)
1
0_453
J
0_987.
•••••••••••••••••••
l ' I -6-00000000000
or 1..
11
0.200
j
IT;
IDENTI
F1CA~:~~y
~O.100
SOCKET A
I
1.690
0.100
I
x
19 = 1.9DO
2.311
CERAMICLlD\
P'NSTAND-OFF/
4PL
\-_-+_---,
I
1-
U"-~~F'LE
.
0_200
SOCKET
0_300-1
r-0.30D--O.400
4O-pln Low Profile Protopack
NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.
648
j
x 11"= 1.100 _ _ 0.520 _ _ 0.330_
I
.
G-10
1
0.540
• • • • • • • • • • • • • • • •• •
0000000000 CD
IDENT'F1CATION
EPOXY/GLASS\
1.
PACKAGE INFORMATION (Continued)
PINI
IDENTIFICATION
45· x 0.045MAX"'}9.tt·~~~4Dm
0.026.J...
NOMINALT
7
45° x 0.45 MAX
"
0.650
.·Ii
45. x 0.010MAXJf-C;.,..,===...........::!..=o=!,=-....L
3 PLACES
VIEW TOWARD PC BOARD
"DIMENSION FROM CENTER TO CENTER OF RADU
44-pinPCC
40
21
D
D
~DDDDDDDDDDDD
ffiDDDDDDDDDDDD
o
=.~)
MAX MAX
j
~~1
IDENTIFI CATION
_
SOCKETA
F
.
20
2.020 MAX
1-'.-
0.050 ± .020
1.220 MAX
'1
sa.----!
u~d
1-.
t
O.ra-
r-0.530
MAX
MAX
0.010
-.. -±.002
TYP
I~OR~9~_1
0.04;]"
±.020
-
_
I
I
II 0.016
iO.050±.015 BOTH ENDS. -+I-±.003
1--0.100 ± .010 TYP
TYP
+.________-'-._~~~
.
_
_0.040 + .007 TYP
-.002.
l--r
0.125
MIN
40-pln Pro~opack
649
PACKAGING INFORMATION (Continued)
25
0.062
RADIUS
r-~::~~==J
l r-
IS"
4 PLACESfi
~
=
0.018/D.01SRAD.TYP·1,'(
~
0.180
MAX
11_0.650'~1
0. 015
0.610
'
o.tt~~::;:;::::;:;:::;:;:::::::~~~~;;:::. ::::::::=::::;:;::~
d=
REF
o.lLJ
MIN.
-
_0.090
0.060 ,
0.100
TYP.
_11_0.0119
0.040
48-Pln Dual-In-Line Package (DIP),
'Plastlc
@ @ @ @ @ @ @ @ @ @ @ @ @
©©©©©©©©©©©©©
1.063-1--l-+--+-
@ @ @ @ @ @ @ @ @ @ @ @ @
, ,©©©©©©©©©©©©,
f-/-----0.l00'13=1.300----+I
1--+---------1.830---------1
t----------0.l00x23=2.300-~-------____i
1--'-----------2.470-----------_1
'i'
rrmrru=
~ I,t~[~i~
~~
~ IT~~~
ENCA~rr,;LASS ~~7
'---......w--+---.t;r-.dr-...J
I
~ 0.200
_0.300
~r:FILE
1
I~~~~AND-OFF
_O.400~'
I
I
0.300
4PL
,
------------'--
. -Ij.-0.018DIA
'
TYP.
.
Protopack (T)
NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.
.,
0.126
0.040
48-Pin Low Profile
650
rr
0.06'
0.,197
ORDERING INFORMATION
ZO MCU, 2K ROM, 0 MHz
20-pin DIP
Z8 MCU, 4K ROM,
12 MHz
40-pinDIP
Z0860008PSCRXX
Z0860000PECRXX
Z8 MCU, 4K ROM,
16 MHz
4D-pin DIP
Z86C1112PECRXXX Z86C1116PSCRXXX
44-pinPLCC
ZOMCU
40-pin DIP
44-pin PCC
2KROM
Z0860112PSCRXXX Z0860112VSCRXXX
Z0860112DSERXXX
Z0860112PECRXXX
Z0860112DEERXXX
4KROM
Z0861112PSCRXXX Z0861112VSCRXXX
Z0861112PECRXXX
Z0861112DSERXXX
40-pin Protopak
44-pinPLCC
Z86C1112VECRXXX Z86C1116VSCRXXX
2KXROM
Z0860312TSF
Z8 MCU, OK ROM
40-pin DIP
Z86C2112PECRXXX
Z86C2116PSCRXXX
Z86C2112CEARXXX
4KXROM
Z0861312TSF
ZO MCU wit" BASIC/Debug Interpreter, 0 MHz
40-pin DIP
ZO MCU, OK PROM
40-pln DIP
Z86E2112PEC
Z86E2116PSC
Z86E2112CEA
44-pin PLCC
Z86C2112VECRXXX
Z86C2116VSCRXXX
44-pln'PLCC
Z0867108PSCR002
Z0867108PECR002
Z86E2112VEC
Z86E2116VSC
Z0601 ROMless MCU
44-pin PCC
. 4D-pin DIP
o MHz
Z0868108PSC
Z0868100DSE
Z0868108PEC
Z0868108DEE
12 MHz
Z08f)8112PEC
Z0868112PSC
Z0868112DSE
Z0868112DEE
16 MHz
Z0868116PSC
Z0868108VSC
Z8 ROMless MCU
4D-pin DIP
44-pln PCC
Z86C9112PEC
Z86C9116PSC
Z86C9112VEC
Z86C9116VSC
ZO 4K ROM MCU, 12 MHz
Z0861112CMBRXXX
Z0868112VSC
Z0868112VEC
Z8 ROMless MCU, 8 MHz
4D-pin DIP
Z0868108CMB
Z0868116VSC
Low Cost ROMless MCU, 8 MHz
Z0868208PSC
Z0868408PSC
Low Power ROM less MC·U, 0 MHz
4D-pin DIP
44-pin PCC
Z8 MCU, 4K ROM, 12 MHz
28-pin DIP
Z86C1012PSC
.ZO MCU, OK flOM, 12 MHz
20-pin DIP
Z86C2012PSC
Z0869108PSC
ZO ROMless MCU,
4D-pin DIP
Z0869112PSC
Z0869112PEC
Z0869108VSC
12 MHz
44-pin PCC
Z0869112VSC
ZO ROMless MCU, 16 MHz
40-pin DIP
44-pln PCC
Z0869116PSC
Z0869116VSC
651
Codes
PACKAGE
Preferred
D = Cerdip
P = Plastic
V = Plastic Chip Carrier
ENVIRONMENTAL
Preferred
C = Plastic Standard
E = Hermetic Standard
F = Protopack Standard
Longer Lead Time
C = Ceramic
F = Plastic Quad Flat Pack
G = Ceramic PGA (Pin Grid Array)
L = Ceramic LCC
Q =Ceramic Quad-in-Line
R = Protopack
T = Low Profile Protopack
Longer Lead Time
A = Hermetic Stressed
B =833 Class B Military
D = Plastic Stressed
J =JAN 38510 Military
TEMPERATURE
Preferred
S = O°C to +70°C
Longer Lead Time
E = -40°C to +85°C
M = -55°C to + 125°C
Example:
Z0869112PSC is a 12 MHz 8691 (ROMless Z8) in a plastc DIP, 0° C to +700 C, Standard
Flow.
RXXX
08691 12
P
S
C
Z
I
\ 1L - - - -_ L
652:
ROM Mask Number
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
ZiLOG DOMESTiC SALES OFFICES AND
TECHNICAL CENTERS
INTERNATIONAL SALES OFFICES
CALIFORNIA
Agoura ...................................................... 818-707-2160
Campbell .................................................. 408-370-8120
TU51in ...................................................... 714-838-7800
CANADA
Toronto .: ................................................ 416-673-0634
COLORADO
Boulder .................................................... 303-494-2905
FLORIDA
Largo ...................................... ,................. 813~585-2533
GEORGIA
Norcross ...................... :........................... 404-923-8500
ILLINOIS
Schaumburg ............................... :............ 312-885-8080
NEW HAMPSHIRE
Nashua .................................................... 603-888-8590
MINNESOTA
Edina ........................................................ 612-831-7611
NEW JERSEY
Hasbrouck Hts. ........................................ 201-288-3737
OHIO
Seven Hills .............................................. 216-447-1480
PENNSYLVANIA
Ambler ...................................................... 215-653-0230
TEXAS
Richardson .............................................. 214-231-9090
1988 by Zilog, Inc. All rights reserved. no part of this
publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Zilog.
The information contained herein is subject to change
without notice. Zilog assumes no responsibility for the
use of any circuitry embodied in a Zilog prOduct. No other
circuit patent licenses are implied.
All specifications (parameters) are subject to change
without notice. The applicable Zilog test documentation
will specify which parameters are tested.
Zilog, Inc. 210 Hacienda.,Ave., Campbell, CA 95008-6609
Telephone (408) 370-8000 TWX 910-338-7621
03·8275~2
Printed in USA
GERMANY
Munich .................................................... 49-89-672-045
JAPAN
Tokyo ...................................................... 81-3-5870528
HONG KONG
Kowloon......... ........ ............................... 852-3-7238979
R.O.C.
Taiwan .................................................. 886-2-7312420
UNITED KINGDOM
Maidenhead................... ......................... 44-628-39200
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