Z8_Microcomputer_Family_3ed_May86 Z8 Microcomputer Family 3ed May86

User Manual: Z8_Microcomputer_Family_3ed_May86

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ZS MICROCOMPUTER
FAMILY

The Z8 2K ROM single chip
microcomputer produced
by SGS using NMOS technology

Automatic electrical
test of a VLSI device
in the SGS Agrate facility

Application board
using Z8671 tiny
Basic microcomputer

CODleDls'

Page
SGS: an introduction

3

Overview..................................................................

7

Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

Part Number Identification ...................................................

9

Datasheets .................................................................

13

NMOS Family
- Z8601lL ................. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 286111L ........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 286211L ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
-28671 ...................................................................
- 286811L ..................................................................
- 28682/L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- Z8684/L .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 286Ell ..................................................................
- 286E21 ..................................................................

13
35
57
79
103
103
103
129
155

Packages

183

Reliability Informations ..................................................... 187
Development Products ...................................................... 199

- General Purpose Fundation Module for MCU Emulation ....................... 199
- 28 Emulation and Development Package ..................................... 203
- 28 Emulation and Development Package for IBM compatible Personal Computers . 207
Technical and Application Notes . ........................................... 213

- Double Layer P-Vapox and SI3N4 Glass Passivation ...........................
- PM28: Z8681 in Single Board Computer Application ..........................
- Single Board Computer Using Z8671 ........................................
- Z8 in Electronic Private Automated Branch Exchange (EPABX 2 Ext./8 Int. Lines)
- Using 28 MCU in Keyboard Controller ......................................
-'- Z8 MCU in Dynamic Keyboard .............................................
- Comparison of 28611, 8051 and MC6801 Microcomputer .......................
- A Programmer's Guide to the 28 Microcomputer .............................

213
215
219
227
237
241
251
265

Identity
Late in 1957, SGS was founded around a
team of researchers who were already
carrying out pioneer work in the field of
semiconductors. From that small nucleus, the
company has evolved into a Group of
Companies, operating on a worldwide basis
as a broad range semiconductor producer,
with billings over 300 million dollars and
employing over 9500 people.
The SGS Group of Companies has now
reached a total of 11 subsidiaries, located in
Brazil, France, Germany, Italy, Malta,
Malaysia, Singapore, Sweden, Switzerland,
United Kingdom and the USA.
To go with its logo, the company takes the
motto \\T echnology and Service", under lining
the accent given to the development of stateof-the-art technologies and the corporate
commitment to offer customers the best
quality and service in the industry.

3

50s Locations · Europe

* HEADQUARTERS
A FACTORIES

• SALES OFFICES
• DESIGN CENTERS

4

5GS LocatioDs • North America

.

WALTHAM (MAl

....,......

__T"'""""o_POUGHKE~NY)
HAUPPAUGE (NY)

FT .LAUDERDALE (FLI

* HEADQUARTERS
• SALES OFFICES
• DESIGN CENTERS

5

SGSLocatioDs • Asia/Pacific

* HEADQUARTERS
A

FACTORIES

• SALES OFFICES
• DESIGN CENTERS

6

Overview
Z8* Family
The Z8 microcomputer family offers the
most sophisticated processing capability
available on a single chip. As an extension
of earlier generations of microcomputers, the
Z8 family provides standard on-chip
functions, such as:
• 2K, 4K or 8K bytes of ROM
• 144 or 256 8-bit registers
• 32 lines of programmable I/O
• Clock oscillator
In addition, the Z8 Family offers advanced
on-chip features, including:

Optimized Instruction Set. The instruction
set of the Z8 family is optimized for highcode density and reduced execution time.
This feature is supported by a "working
register area" concept that uses short (4-bit)
register addresses. The general-purpose
registers can be used as accumulators, as
address pointers for indirect addressing, as
index registers, or for implementing an onchip stack.
The 47 instruction types and six addressing
modes-together with the ability to operate
on bits, 4-bit BCD digits, 8-bit bytes, and
16-bit words-offer unique programming
capability and flexibility.

• Two counter/timers
• Six vectored interrupts
• UART for serial I/O communication
• Stack functions
• Power-down option
• TTL compatibility
The Z8 microcomputer family is
expandable off-chip to provide an additional
62K bytes of program memory and 62K bytes
of data memory for the 2K-byte ROM
version, an additional 60K bytes of program
memory and 60K bytes of data memory for
the 4K-byte ROM version and an additional
56K bytes of program memory and 56K bytes
of data memory for the 8K-byte ROM
version. The interface to external memory is
accomplished through one, one and onehalf, or two of the 8-bit I/O ports, depending
on the number of address bits required for
the external functions. The
Z-BUS* protocol allows easy interface to
external functions including peripheral
chips.
The Z8 family challenges the "multi-chip
solution" design currently implemented by
general- purpose microprocessors. Designs
based on Z8 family microcomputers offer a
minimum chip-count configuration that can
easily be expanded to meet requirements for
enhancement options and for future
improvements.

Growing Family. The Z8 microcomputer
family is growing to meet the needs of more
complex designs. The 8K ROM version,
Z8621 completed developed by SGS, offers
all the features of the Z8 Family, plus 8K
bytes of on-chip ROM and 256-byte register
file. The increased ROM and bytes register
file allows the designer to take advantage of
the code optimization inherent in the Z8
instruction set when using between 2K and
8K bytes at program memory.
The ROMless microcomputers provide an
alternative for designers seeking to take
advantage of the on-chip features of the
Z8681, Z8682 and Z8684 in applications that
require external program memory. A Z8681
microcomputer can be used to control a
system that addresses up to 128K bytes of onchip memory, a Z8682 up to 124K bytes and
Z8684 up to 120K bytes.
Newly in the Z8 family the 4K and 8K
bytes on-chip Eprom Z86Ell and Z86E21,
that perform different programming modes,
like: Eprom-like, using standard eprom
programmer; Self-programming, during
normal microcomputer operation and timeefficient self-program facility; and integrated
programmable Eprom read-out protection.
For there characteristics the Z86Ell and
Z86E21 can be considered as low cost
development tools for the Z8 microcomputer
family.

7

Low Power version 80mA current
consumption, on all the family will be
available.

• Arcade games and intelligent home
games

Expanded Applications. The Z8
microcomputer family is finding its way into
increasingly sophisticated designs. In
addition to the low-end capability
applications commonly used with
microcomputers, the Z8 family can be used
effectively in such applications as:

• Intelligent instrumentation

• Process control

• Computer peripheral controllers
• Smart terminals

• Automotive mechanisms
An example of how a Z8 might be used in
the design of an intelligent terminal is shown
in Figure 1. The features of such a terminal
depend on its specific requirements, but it is
clear that the Z8 microcomputers offer
unprecedented capability and flexibility to
the microcomputer designer.

• Dumb terminals
• Telephone switching systems

Z8
MICROCOMPUTER
SERIAL
COMMUNICATIONS

Figure 1. Z8 Based Intelligent Terminal

8

Z8 Cross Reference
SUFFIX DESCRIPTION
BASE PART
NUMBER

ISGS
ZILOG

SPEED SUFFIX (MHz)

Z86XX
Z86XX

TEMP. SUFFIX

PACKAGE SUFFIX

~

~

8.0

12.0

PL

FR

*

A
A

B

F

P

na

*

CER PLCC LCC
D
C

K

C
V

Q

~

~

~

1
S

6
E

I

DEVICE TYPE

I

SGS
ZILOG

2KROM

4K ROM

8KROM

Z8601
Z8601

Z8611
Z8611

Z8621
-

TINY
BASIC

ROMLESS

Z8671
Z867 I

Z868112/4
Z868 112/4

4K
EPROM

8K
EPROM

Z86Ell

Z86E21

,-

-

2KPIGGYBACK

4K PIGGY
BACK

-

-

Z8603RS

Z8613RS

Notes: * Standard Version no suffix required
na: Not Available

SGS Part Number Identification
example:

Z8621

Circuit Designator _________________--'1

IrA

Speed ____________________________________________

~

No letter
8.0 MHz
12.0
A
ROM Content where requests _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

Package _____________________________

~

B Plastic
D Ceramic
F Frit-Seal
C Plastic Leaded Chip Carrier
K Ceramic Leadless Chip Carrier
TeDlperature Range __________________________~

1
6

0 to +
-40 to +

70°C
85°C

9

Dalasheels

aB.
Z8 2K ROM Microcompater
• Complete microcomputer, 2K bytes of
ROM, 128 bytes of RAM, 32 I/O lines,
and up to 62K bytes addressable external
space each for program and data
memory.
•

144-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.

• Minimum instruction execution time
at 12 MHz.

/ls,

• Vectored, priority interrupts for I/O,
counter/timers, and UART.
• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.

• Register Pointer so that short, fast
instructions can access any of nine
working register groups in I /lS.
• On-chip oscillator that accepts crystal or
external clock drive.
• Low-power standby option which retains
contents of general-purpose registers.
• Single + 5 V power supply-all pins TTLcompatible.
• Low Power version (28601L):
- Available 8 MHz
- Current consumption 80 rnA
• Available in 8 and 12 MHz versions.

General Description
The 28601 microcomputer introduces a
new level of sophistication to single-chip
architecture. Compared to earlier single-chip
microcomputers, the 28601 offers faster
execution; more efficient use of memory;
more sophisticated interrupt, input/output
and bit-manipulation capabilities; and easier
system expansion.
Under program control, the 28601 can be

tailored to the needs of its user. It can be
configured as a stand-alone microcomputer
with 2K bytes of internal ROM, a traditional
microprocessor that manages up to 124K
bytes of external memory, or a parallelprocessing element in a system with other
processors and peripheral controllers linked
by the Z-BUS. In all configurations, a large
number of pins remain available for I/O.

PORT 0
(NIBBLE
PROGRAMMABLE)

110 or As-A1S

PORT 3
PORT 1
(BYTE
PROGRAMMABLE)

110 or ADO"AD7

(FOUR INPUT;
FOU R OUTPUT)
SE81AL ANO
PARALLEL 110
AND CONTROL

Figure 1. Logic Functions

13

,.A
~,' ", "", ;' ;:'
"

~

,

,

")

,
=

y

'\i

'

'

j }

Z

'

,,~1~

7

2

V;

;

General Description (Continued)

Vee

P3,

VUMIXTAL2

P3,

XTAL1

P2,

P3,

P2,

P3,

P2,

II3ET
RI'W

P2,

os

P2,

AS

P2,

P3,

P2,

GND

P3,

P2,

P3,

P3,

po,
po,
po,
po,
po,
po,
po,
po,

P1,
P1,
P1,
P1,

6

5

4

3

2

1 "" 43 42 41

40

REsET

39

R/W

38

P24

Os

37

P23

36

P2Z

.is

10

P3S

11

GIIID

12

35

Z8601

NoC.

P2,

34

P20

33

P33

PDo

32

P34

PO,
PO,

31

PI7

30

PiS

29

PIS

P3Z

N.C.

13

17
18 19

20 21

22 23 24 25

26 27

2S

P1,
P1,
P1,
P1,

Figure 2. Pin Configuration

N.C._NO CONNECTION

Figure 2a. Chip Carrier Pin Configuration

Architecture
Z8601 architecture is characterized by a
flexible 1/0 scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications,
Microcomputer applications demand
powerful I/O capabilities. The Z8601 fulfills
this with 32 pins dedicated to input and
output. These lines are grouped into four
ports of eight lines each and are
configurable under software control to
provide timing, status signals, serial or
parallel I/O with or without handshake, and
an address/data bus for interfacing external
memory.
Because the multiplexed address/data bus
is merged with the I/O-oriented ports, the
Z8601 can assume many different memory
and I/O configurations. These configurations
range from a self-contained microcomputer

14

to a microprocessor that can address 124K
bytes of external memory.
Three basic address spaces are available to
support this wide range of configurations:
program memory (internal and external),
data memory (external) and the register file
(internal). The 144-byte random-access
register file is composed of 124 generalpurpose registers, four I/O port registers,
and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.

Architecture (Continued)

AS

OUTPUT

FLAGS

REG. POINTER

!tt!!!!!

I/O
(BIT PROGRAMMABLE)

ADDRESS OR 110
(NIBBLE PROGRAMMABLE)

ADDRESSIDATA OR 110
(BYTE PROGRAMMABLE)

Figure 3. Block Diagram

Pin Description

AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the
beginning of each machine cycle. Addresses
output via Port 1 for all external program or
data memory transfers are valid at the
trailing edge of AS. Under program control,
AS can be placed in the high-impedance
state along with Ports a and 1, Data Strobe
and ReadIWrite.

OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.
POO-P7. I/O Port Lines (input/output, TTL
compatible). 8 lines Nibble Programmabl~
that can be confIgured under program
control for I/O or external memory interface.

P1o-P17. I/O Port Lines (input/output, TTL
compatible). 8 lines Byte Programmable that
can be configured under program control for
I/O or multiplexed address (Ao-A7) and data
(Do-D7) lines used to interface with
program/data memory.
P2o-P27' I/O Port Lines (input/output, TTL
compatible). 8 lines Bit Programmable. In
addition they can be configured to provide
open-drain outputs.
P30-P3,. Input Port Lines (TTL compatible).
They can also configured as control lines.
P3s-P37' Output Port Lines (TTL compatible).
They can also configured as control lines.

15

Pin Descriptions (Continued)
RESET. Reset (input, active Low). RESET
initializes the Z8601. When RESET is
deactivated, program execution begins from
internal program location OOOCH.
R/W. Read/Write (output). R/W is Low when
the Z8601 is writing to external program or
data memory.

XTALI. XTAL2. Crystal 1, Crystal 2 (timebase input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz
maximum) or an extern'al single-phase clock
(8 or 12 MHz maximum) to the on-chip clock
oscillator and buffer.

Address Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program'
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 2048
bytes consist of on-chip mask-programmed
ROM. At addresses 2048 and greater, the
Z8601 executes external program memory
fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These
locations contain six 16-bit vectors that
correspond to the six available interrupts.
Data Memory. The Z860 I can address 62K
bytes of external data memory beginning at
locations 2048 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124

16

general-purpose registers (R4-RI27) and 16
control and status registers (R240-R255).
These registers are assigned the address
locations shown in Figure 6.
Z8601 instructions can access registers
directly or indirectly with an 8-bit address
field. The Z8601 also allows short 4-bit
register addressing using the Register
Pointer (one of the control registers). In the
4-bit mode, the register file is divided into
nine working-register groups, each
occupying 16 contiguous locations (Figure
7). The Register Pointer addresses the
starting location of the active workingregister group.

Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which
can reside anywhere in data memory
between locations 2048 and 65535. An 8-bit
Stack Pointer (R255) is used for the internal
stack that resides within the 124 generalpurpose registers (R4-RI27).

Address Spaces (Continued)
5535

65535

r-----------,

EXTERNAL
ROM OR RAM

2048
2047

ON·CHIP
ROM

Location 0I

UT" byte 0I
Instruction
executed

.lter reae

~~ ~-----------11

,,

Veeto
(Lower ByteI

Interrupt
Vector
(Upper Byte)

DATA
MEMORY

lAOS

10

Interrup

EXTERNAL

IR05

•

IRQ4

8

IRQ4

7

IR03

6

IR03

51--

IRQ2

41-0-

IR02

3

IRQ1

2

IR01

1

IROO

0

IROO

~g:: 1 - - - - - - - - - - - - - 1
NOT ADDRESSABLE

Figure 4. Program Memory Map
IDENTIFIERS

LOCATION

255

254

STACK POINTER (BITS

7~O)

STACK POINTER (BITS 15-8)

SPL
SPH

RP

253

REGISTER POINTER

252

PROGRAM CONTROL FLAGS

FLAGS

251

INTERRUPT MASK REGISTER

IMR

250

INTERRUPT' REQUEST REGISTER

IRQ

IPR

249

INTERRUPT PRIORITY REGISTER

248

PORTS 0-1 MODE

247

PORT 3 MODE

P3M

246

PORT 2 MODE

P2M

245

TO PRESCAlER

244

TIMER/COUNTER 0

Figure 5. Data Memory Map

__ II

r, r, r, r.

'I

o0

I:::

0 0

-240
The upper nibble of the register lIIe address
_provided by the r'9lster pOinter specifies
the active wor1dng·regisler group.

12

P01M

-+-

PREO
TO

-+-

PRE1

243

T1 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

TMR

-+-

240

SERIAL 110

SIO

---

Tl

NOT

IMPLEMENTED
127

GENERAL·PURPOSE
REGISTERS

PORT 3

P3

PORT 2

P2

PORT 1

PI

PORT 0

PO

Figure 6. The Register File

The lower

SPECIFIED WORKING·
REGISTER GROUP

nibble of
the regjs~er
file address
provided by

-f- theln.truetlon
points to the
specified
r &glster.

15

----i/OPORTS-----

3

Figure 7. The Register Pointer

17

Serial Input/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for fullduplex serial asynchronous receiver/
transmitter operation. The bit rate is
controlled by Counter/Timer 0, with a
maximum rate of 62.5K bits/second for 8
MHz and 94.8K bits/second for 12 MHz.
The Z8601 automatically adds a start bit
and two stop bits to transmitted data (Figure
8). Odd parity is also available as an option.

Eight data bits are always transmitted,
regardless of parity selection. If parity is
enabled, the eighth bit is the odd parity bit.
An interrupt request (IRQ4) is generated on
all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by
a parity error flag. Received characters
generate the IRQ3 interrupt request.
Received Data
(No Parity)

Transmitted Data
(No Parity)

lul~I~I~I~I~I~I~I~lnl
LSTART BIT
' - - - - - - - E I G H T DATA BITS
TWO STOP BITS

I

IL.._ _ _ _ _
L_START

_

Transmitted Data
(With Parity)

T
I
L

Received Data
(With Parity)

lulpl~I~I~I~I~I~I~lnl
LSTART BIT

_ _ _ _ _ _ _ _ SEVEN DATA BITS

.

BIT

EIGHT DATA BITS

' - - - - - - - - - - - O N E STOP BIT

L

_LSTARTBIT
' - - - - - - S E V E N DATA BITS

ODD PARITY

I

TWO STOP BITS

' - - - - - - - - - - - O N E STOP BIT

PARITY ERROR FlAG

Figure 8. Serial Data Formata

Counter/Timers
The Z8601 contains two 8-bit
programmable counter/timers (To and TI),
each driven by its own 6-bit programmble
prescaler. The TI prescaler can be driven by
internal or external clock sources; however,
the To pres caler is driven by the internal
clock only.
The 6-bit prescalers can divide the input
frequency of the clock source by any number
from 1 to 64. Each prescaler drives its
counter, which decrements the value (l to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request-IRQ4 (To) or IRQ5
(TI)-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be
programmed to stop upon reaching zero
(single-pass mode) or to automatically reload
18

the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the pre scalers , can be read any time
without disturbing their value or count mode.
The clock source for T I is user-definable
and can be the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and
6 MHz maximum for the 12 MHz device)
divided by four, or an external signal input
via Port 3. The Timer Mode register
configures the external timer input as an
external clock (l MHz maximum), a trigger
input that can be retriggerable or nonretriggerable, or as a gate input for the
internal clock. The counter/timers can be
porogrammably cascaded by connecting the
To output to the input of T I. Port 3 line P36
also serves as a timer output (Tour) through
which To, TI or the internal clock can be
output.

110 Ports

The Z8601 has 32 lines dedicated to input
and output. These lines are grouped into
four ports of eight lines each and are
configurable as input, output or
address/data. Under software control, the
ports can be programmed to provide address
outputs, timing, status signals, serial 1/0,
and parallel 1/0 with or without handshake.
All ports have active pull-ups and pulldowns compatible with TTL loads.
Port 1 can be programmed as a byte 1/0
port or as an addressldata port for
interfacing external memory. When used as
an I/O port, Port 1 may be placed under
handshake control. In this configuration,
Port 3 lines P33 and P34 are used as the
handshake contois RDY 1 and DAV 1 (Ready
and Data Available).
Memory locations greater than 2048 are
referenced through Port L To interface
external memory, Port 1 must be
programmed for the multiplexed
Address/Data mode. If more than 256
external locations are required, Port 0 must
output the additional lines.
Port 1 can be placed in the highimpedance state along with Port 0, AS, DS
· and RIW, allowing the Z8601 to share
, common resources in multiprocessor and
, DMA applications. Data transfers can be
· controlled by assigning P33 as a Bus
Acknowledge input and P34 as a Bus
· Request output.

PORT 1
(1/0 OR ADo-ADr)

Port 0 may be placed under handshake
control. In this configuration, Port 3 lines
P32 and P35 are used as the handshake
controls DAVo and RDYo. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0
can provide address bits As-All (lower
nibble) or As-AIS (lower and upper nibble)
depending on the required address space. If
the address range requires 12 bits or less,
the upper nibble of Port 0 can be
programmed independently as I/O while the
lower nibble is used for addressing. When
Port 0 nibbles are defined as address bits,
they can be set to the high-impedance state
along with Port 1 and the control signals AS,
DS and R/W.

I

PORTO
(110 OR Ae-A 1,)

Figure 9b. Pori 0

Port 2 bits can be programmed
independently as input or output. The port is
always available for 1/0 operations. In
addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this
configuration, Port 3 lines P31 and P36 are

HANDSHAKE CONTROLS
} DAV1 AND RDY1
(pa, AND P3~

PORT 2(1/0)

Figure 9a. Pori 1
}

Port 0 can be programmed as a nibble 1/0

port, or as an address port for interfacing
external memory. When used as an I/O port,

HANDSHAKE CONTROLS
DAV2 AND RDY2

(P3, AND P3,1

Figure 9c. Pori 2

19

1/0 Ports (Continued)
used as the handshake controls lines DAV2
and RDY2. The handshake signal assignment
for Port 3 lines P3] and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

Port 3 lines can be configured as I/O or
control lines. In either case, the direction of
the eight lines is fixed as four input (P30-P33)
and four output (P34-P37). For serial 1/0,
lines P30 and P37 are programmed as serial
in and serial out respectively.
Port 3 can also provide the following
control functions: handshake for Ports 0,
and 2 (DA V and RDY); four external

interrupt request signals (IRQO-IRQ3); timer
input and output signals (TIN and Tour) and
Data Memory Select (DM).

PORT 3
(1/0 OR CONTROL)

Figure 9d. Port 3

Interrupts
The Z8601 allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or individually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z8601 interrupts are vectored. When
an interrupt request is granted, and interrupt
machine cycle is entered. This disables all

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended

20

subsequent interrupts, saves the Program
Counter and status flags, and branches to
the program memory vector location
reserved for that interrupt. This memory
location and the next byte contain the 16-bit
address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also
supported. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

capacitors (C] :5 15 pF) from each pin to
ground. The specifications for the crystal are
as follows:
• AT cut, parallel resonant
• Fundamental types, 8/12 MHz maximum
• Series resistance, Rs :5 100 Q.

.I

Power Down Standby Option
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input.
This necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 10 shows the recommended circuit for
a battery back-up supply system.

+5

v O------~---I

Voo

TRICKLE

Z8601

CHARGE(r-.JY\I"v---1Cf:

J
Figure 10. Recommended Driver Circuit
for Power Down Operation

Instruction Set Notation
Addressing Modes. The following notation is
used to describe the addressing modes and
instruction operations as shown in the
instruction summary.
IRR
In

X
DA
RA
1M
R

Indirect register pair or indirect workingregister pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only

IR

Indirect-register or indirect working-register

Ir
RR

address
Indirect working-register address only
Register pair or working register pair address

Assignment of a value is indicated by the
symbol "<-". For example,
dst <- dst + src
indicates that the source data is added to the
destination data and the result is stored in
the destination location. The notation
"addr(n)" is used to refer to bit "n" of a
given location. For example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the
following six flags:
C
Z
S

Symbols. The following symbols are used in
describing the instruction set.

V

dst

H

Destination location or contents
src
Source location or contents
cc
Condition code (see list)
@
Indirect address prelix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register painter (control register 253)
IMR
Interrupt mask register (control register 251)

o

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal·adjust flag
Half-carry flag

b7

bo

[c [z [s [v [D [H [F2[Fl[
Fl
F2

J user flags

Affected flags are indicated by:

o
*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

21

Condition Codes

22

Value

Mneomonic

1000
Olll
III I
0110
1110
1101
0101
0100
llOO
OliO
1110
1001
0001
1010
0010
III I
Olll
lOll
0011
0000

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning

Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater thaN
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set

C=I
C=O
Z=I
Z=O
3=0
3=1
V= I
V=O
Z=I
z=o
(3 XOR V)=O
(3 XOR V)= I
[Z OR (3 XOR V)] =0
[Z OR (3 XOR V)] = I
C=O
C= I
(C=O AND 2=0)= I
(C OR Z)=I

Instruction Formats
ope

CCF. 01, El, IRET, NOP,

Ref. RET, SCF
d51

ope

INC r

One-Byte Instructions

ope

MODE

dsl/src

OR

[TT1yTdStiSf¢]

ClR, CPl, OAt DEC,
DECW. INC, INeW, POP,
PUSH, Rl., RLC, RR,

ope

ope

I

d,1

OR

11 1101

ADC, ADD, AND, CP,

MODE

OR
OR

dsl

ARC, SRA t SWAP

1 1 1 0
1 1 1 0

sre

LOt OR, sec, SUB,
reM, TM, XOR

dsl

JP, CALL (Indirect)

ope

dst

MODE

dsl

ope

AOe, ADD, AND, CP,
OR "

VALUE

SRP

1 1

01

dsl

LO, OR,

sec, SUB,

reM, TM, XOR

VALUE

MODE

ope

MODE

dst

sre

MODE

ope

dst/src

src/dst

ADC, ADD. AND.
CPt OR, sac, SUB,

ope

~_--""'---_-I OR
dst
OR

LD

1 1 1 0
1 1 1 0

dst

reM, TM. XOR

lO, lDE, LOEI,
LOC, LOCI

MODE
dst/src

ope

LD

ADDRESS

ope
dst/src
src/dst

1 ope

dst

OR

11 11 01

LD

R~ ope

dstfCC

JP

DAu
DA,
LD

VALUE

I

ope

s IRoa
1 "" IRoa > IROS

I1 ,

INTERRUPT GROUP PRIORITY
RESERVED = 000

IROO, IRQ2 PR~O:I~:ci~~O~Q~) _ _ _ _ _--"
1 = IROO

> IRQ2

C>A>B=001
A > B > C = 010
A > C > B = 011
B > C > A '" 100
C > B > A = 101
B > A > C = 110
RESERVED = 111

C=OON'T CARE
REGISTER
POINTER

IR01, IRQ4 PRIORITY (GROUP C)
o = IRQ1 > IRQ4 - - -_ _ _---"
1 = IRQ4 > IRQi

R250 IRQ
Interrupt Request Register
(FAH: Read/Write)

R254 SPH
Stack Pointer
(FEH; Read/Write)

1~1~1~1~1~1~1~1~1

RESERVED

==.r-

c=

1~1~1~1~1~1~1~1~1
Pl2 INPUT (Do
IROO)
P33 INPUT
P3l INPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT

IRQS

T,

R2511MR
Interrupt Mask Register
(FBH; Read/Write)

I'

c=

L ______

L ___

=

IRQO
IRQ1
IRQ2
IRoa
IR04

STACK POINTER UPPER
BYTE (SPS-SPls)

R255 SPL
Stack Pointer
(FFH; ReadlWrite)

1 ENABLES IROO-IROS
(00 '" IROO)

RESERVED

' -_ _ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

Figure 12_ Control Registers (Continued)

27

Opcode Map

o

6,5

B.

11,5

B.

6,5

6,5

10,5

la,S

n,fa

fl,Ira

Ra.R1

IRa.RI

6,5

6,5

6,5

10,5

10,5

10,5

10,5

B.,IM IB.,IM
10,5

n,ta

R2,R1

IRa/RI

6,5

6,5

la,S

10,5

10,5

10,5

INC

INC

SUB
n,fa

SUB

n,lra

SUB

SUB

SUB

112,81

IRZ,Rl

SUB

B,O

6,1

6,5

6,5

10,5

la,S

JP

SRP
1M

SBC

SBC

SBC

lB.

ll,ra

II.

Ira

tl,It2

SBC

8a,Rl
10,5

IRa,Rl

6,5

E

12/10,0

5,5

LD

LD

DJNZ

JR

LD

JP

INC

HIRa

ta,Rl

n,RA

cc,RA

n,1M

cc,DA

OR

OR

10,5

SBC

10,5

10,5

6,5

6,5

6,5

OR
n,ra

OR
n,Ita

10,5

6,5

6,5

10,5

10,5

10,5

10,5

AND

AND

AND

AND

AND

Ra.Rl
10,5

lRa,R!
10,5

Rl,IM

IRl,lM

10,5

10,5

Ra,Rl

la,S

r--

OR
OR
lRa,RI B.,IM lB., 1M

B.

lB.

n,f.a

AND
n,lra

6,5

6,5

6,5

6,5

CON
B.

CON
lB.

TeN

teN

teN

fl. fa

teN
n,ha

Ra,R1

IRa,RI

10112,1 12114,1

6,5

6,5

la,S

la,S

la,S

10,5

PUSH PUSH
Ba
lBa

TN

TN

TN

TN

TN

nita

TN
n,l l 2

Ra,lh

lRa,RI

RJ,IM

1R1,IM

12,0

1B,O

10,5

f---

10,5

SBC

DA
lB.

pop

r--

f---

f--

TCN TCN
B.,IM lB., 1M

r-f--6,1

DECW DECW LDE LDEI
M.
lB.
n,lrra Irl,Irra

•
A

6,5

6,5

RL
R.

RL
lB.

10;5

10,5

12,0

1B,O

LDE

LDEI

DI
f--6,1

EI

fa,lrtl lr2. Irn
6,5
6,5

INCW INCW
M.
lB.

CP
n,ta

10,5

la,S

10,5

CP

CP

CP

tl,lra

Ba,R)

lRa,R!
10,5

6,5

6,5

6,5

CLR
lB.

XOR

XOR

XOR

n,ta

XOR

XOR

XOR

n,ba

Ra,Rl

lRa,R!

Rl.IM

1R1,IM

6,5

6,5

12,0

18,0

C

RRC
B,

RRC
lB.

E

F

Bytes per

_loa

10,5

6,5

Jb

LOC LOCI CALL"
ta, btl Ira.lrn IRB.

1B,O

6,5

6,5

6,5

10,5

RR
B.

RR
iR.

LD

LD
R2.R1

IRa,RI

B,5

B.5

n, Ira
6,5

20,0

6,5

RCF

20,0

la,S

CALL

LD

DA

fa, x, 81

10,5

10,5

10,5

LD

LD

LD
lB., 1M

RI,IN

f--6,5

SCF

f--6,5

CCF

f---

10,5

LD

6,0

LD

Iu,ra

'"

16,0

IRET
f---

LD

BRA
lB.

V
2

10,5

10,5

6,5

BWAP SWAP
R.
lB.

RET

f--

tl,x,Ra

BRA

"

la,S

LOC LDCl
n.lrra In, bra
12,0

14,0

CP
CP
B.,IM lB., 1M

CLR
B.

6,5

f--

10,5

•
D

NOP

Ba,IRl

....

V'
3

Lo_

.I

"'---------~~~---------'''' ~ ~
2

3

Opc:ode

Nlbbl.
ExecuIIOD

eye-

Legend.

~

R = B·BIt Addno..
r = 4-Bit Address

Rl or rl = Drt Address
R2 or 12 = Src Addresa

U_

Opc:ode _ A

..........D1c

Nibble
FInI
()per(mc\

28

F

" r--

B.,IM lB., 1M

B,5

10,5

12/10,0

D

B.,IM lB., 1M

DA
B.
la,S

12/10,5

C

B.,IM lB., 1M

lB.

pop

6,5

B

la,S

6,5

IBB.

6,5

A

RLe me me me me me me

6,5

B.

7

6,5

lB.

DEC DEC ADD ADD ADD ADD ADD ADD

RLC

8

,

Secoac\
Opercmd

SaqueDC8.
Opcode, First Operand, Second Operand

Not.. The blank areas are not defined.

Absolute Maximum Ratings
Voltages on all pins
with respect to GND ........ - 0.3 V to + 7.0 V
Operating Ambient
Temperature ....................... ooe to + 70°C
Storage Temperature ....... - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; operation of the device at any condition

above those indicated in the operational sections of these
speCifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability,

Standard Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the
reference pin. Standard conditions are as
follows:

o
o

+4.75 V ::; Vee::; +5.25 V

GND=O V

o ooe ::;

TA ::; +70°C

+5V

+5V

+5V
2.1K

+5V

18K

1.Sk

1.Sk
7;::'504

CL~CK

74LS04

---e
.,>o---~.....--l~I>:>-""'--t,-- XTAL2

!
I

Cl = 15pF MAX

'-----~- XTAL1

t
I

I

Figure 13. Test Load I

Figure 14. Test Load 2

Cl = 15pF MAX

Figure 15. External Clock Interface Circuit
(Both the clock and complement are required)

29

DC Characteristics
Symbol

Parameter

Min

Max

Unit

3.8

Vee

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

VeH

Clock Input High Voltage

VeL

Clock Input Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

VRH

Reset Input High Voltage

VRL

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

10L

Output Leakage

1m

Reset Input Current

-50

lee

Vee Supply Current

120
80'

rnA

IMM

VMM Supply Current

10

rnA

Vee

V

Backup Supply Voltage
VMM
• This value is for 28601 only.

30

2.0

Vee

V

-0.3

0.8

V

3.8

Vee

V

-0.3

0.8

V

2.4

Condition

V

10H= -250 "A

0.4

V

10L= +2.0 rnA

-10

10

"A

-10

10

"A

o V$,
o V$,

"A

Vee = +5.25 V, VRL=O V

3

VIN $, +5.25 V
VIN $, +5.25 V

Power Down Mode
Power Down

External 110 or Memory Read and Write Timing
.I

No

Symbol

Paramter

Min

Z860llL
Max

Z860lA
Min

Max Notes*t

TdA(AS)
Address Valid to AS i Delay
50
1,2,3
35
AS i 10 Address Float Dealy
2
TdAS(A)
70
1,2,3
45
AS i '0 Read Data Required Valid
220 1,2,3,4
3
TdAS(DR)
360
55
1,2,3
4
TwAS
AS Lew Width
80
5
TdAz(DS)
Address Float to [is !
0
o
1
6--TwDSR----DS (Read) Low Width
250 - - - - - - 1 8 5 - - - - - 1 , 2 , 3 , 4
7
TwDSW
DS (Write) Low Width
110
1,2,3,4
160
8
TdDSR(DR)
DS ! to Read Dat" Required Valid
200
130 1,2,3,4
9
ThDR(DS)
Read Data to DS l' Hold Time
0
o
I
10
TdDS(A)
DS i to Address Active Delay
70
1,2,3
45
11
TdDS(AS)
DS i to AS! Delay
1,2,3
70
55
12-TdRIW(AS)--R/W Valid to AS i Delay - - - - - - -50 - - - - - 3 0 - - - - 1,2,3
1,2,3
13
TdDS(RIW)
DS i to RIW Not Valid
60
35
14
TdDW(DSW) Write Data Valid to DS (Write) ! Delay
1,2,3
50
35
15
TdDS(DW)
DS i to Write Data Not Valid Delay
1,2,3
70
45
16
TdA(DR)
Address Valid to Read Data Required Valid
255 1,2,3,4
410
17
TdAS(DS)
AS i to DS ! Delay
1,2,3
80
55
NOTES:
1.
2.
3.
4.

5. All timing reference use 2.0 V for a logic «1» and 0.8 V for a

Test Load 1
Timing numbers given are for minimum TpC.
Also see clock cycle time dependent characteristics table.
When using extended memory timing add 2 TpC.

t

logic ({Q».
All units in nanoseconds (ns),
Timings are preliminary and subject to change.

PORT 0 ,

DM
16

PORT 1

11---~0r---~~1

iii

__________~----__~I.-----40r---~~I~----~---

(READ)

PORT 1

Do-D7 OUT

iii
(WRITE)

Figure 16. External I/O or Memory Read/Write

31

Additional Timing Table
No

Symbol

Paramter

Min

TpC
Input Clock Period
2
TrC, TIC
Clock Input Rise And Fall Times
3
TwC
Input Clock Width
TwTinL
Timer Input Low Width
4
5--TwTinH---Timer Input High Width
TpTin
6
Timer Input Period
TrTin, TfTin
7
Timer Input Rise And Fall Times
Interrupt Request Input Low Time
Sa
TwIL
Sb
TwIL
Interrupt Request Input Low Time
Interrupt Request Input High Time
9
TwIH

Z860IlL
Max

125

1000
25

37
100
3TpC
STpC

Z8601A
Min
S3

1000
15

26
70
3TpC
STpC
100

100
3TpC
3TpC

Max Notes"t

100
70
3TpC
3TpC

NOTES:
1. Clock timing references uses 3.8 V for a logic "I" and 0.8 V
for a logic "0".

2. Timing reference uses 2.0 V for a logic "I" and 0.8 V for a
logic "0",

3. Interrupt request via Port 3 (P31-P33)'

4. Interrupt request via Port 3 (P30).
* Units in nanoseconds (ns).
t Timings are preliminary and subject to change.

Figure 17. Additional Timing

32

2
2
2
2
2,3
2,4
2,3

,

~II'~~~
'~

~~

"

~"

'"

'"

<

"
'

"

~ ~
"

~

•

,

",

Handshake Timing
No Symbol

Paramter

Min

]
TsDl(DAV)
Data In Setup Time
ThDl(DAV)
Data In Hold Time
2
TwDAV
Data Available Width
3
TdDAVIf(RDY)
DAV ! Input to RDY ! Delay
4
5-TdDAVOf(RDY)-DAV! Output to RDY! Delay
TdDAVIr(RDY)
DAV Input to RDY Delay
6
DAV Output to RDY Delay
TdDAVOr(RDY)
7
Data Out to DAV ! Delay
TdDO(DAV)
8
TdRDY(DAV)
Rdy ! Input to DAV Delay
9

r
r

r

Z8601lL
Max

Z860lA
Min
0
160
120

0
230
175

]20

175
0

0
120

175

r

0
50
0

r

Max Notes*t

200

0
30
0

],2
],3
],2
],3
I

140

NOTES:
1. Test Load]
2. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "]" and 0.8 V for a logic "0" .
• Units in nanoseconds (ns).
t Timings are preliminary and subject to change .

~

..

-"

CD_~ ~~~:-T-A~'~~-----------

______________ _____

~

....

Figure 18. Input Handshake

DATA OUT

i5AV

(OUTPUT)

ROY
(INPUT)

~
DATA OUT VALID
-----~--------------------------------

_~1~®~~=F1=
Figure 19. Output Handshake

33

Clock-Cycle-Time-Dependent Characteristics
Number

Symbol

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdRIW(AS)
TdDS(RIW)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

I
2
3
4
6
7
8
10

II
12
13
14
15
16
17

Z860l/L
Equation

Z860IA
Equation

TpC-75
TpC-55
4TpC-140'
TpC-45
3TpC-125'
2TpC-90'
3TpC-175*
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215'
TpC-45

TpC-50
TpC-40
4TpC-IIO'
TpC-30
3TpC-65,
2TpC-55'
3TpC-120'
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160*
TpC-30

* Add 2TpC when using extended memory timing

Ordering hdormation
Type

Package

Temp.

Clock

BI
B6
Dl
D6
Cl
C6
KI
K6

Plastic
Plastic
Ceramic
Ceramic
Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

0/+ 70°C
-40/+85°C
0/+70°C
-40/+85°C
0/+70°C
-40/+85°C
0/+70°C
-40/+85°C

8 MHz

28601A BI
28601A B6
28601A Dl
2860lA D6
28601ACl
28601AC6
28601A Kl
2860lA K6

Plastic
Plastic
Ceramic
Ceramic
Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

0/+70°C
-40/+85°C
0/+70°C
-40/+85°C
0/+70°C
-40/+85°C
0/+70°C
-40/+85°C

12 MHz

28601L Bl
28601L B6
2860lL Dl
28601L D6
28601L Cl
Z8601L C6
Z8601LKI
Z8601L K6

Plastic
Plastic
Ceramic
Ceramic
Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

0/+70°C
-40/+ 85°C
0/+70°C
-40/+85°C
0/+70°C
-40/+85°C
0/+ 70°C
-40/ +85°C

Z8601
Z8601
Z8601
28601
28601
Z8601
28601
2860l

34

Description

2K ROM Microcomputer

2K ROM Microcomputer
Low Power version
8 MHz

aB.
Z8 4K ROM Microcomputer
• Complete microcomputer, 4K bytes of
ROM, 128 bytes of RAM, 32 I/O lines,
and up to 60K bytes addressable external
space each for program and data
memory.
•

144-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.

• Minimum instruction execution time
at 12 MHz.

fiB

• Vectored, priority interrupts for I/O,
counter/timers, and UART.
• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.

• Register Pointer so that short, fast
instructions can access any of nine
working register groups in 1 /lS.
• On-chip oscillator which accepts crystal
or external clock drive.
• Low-power standby option that retains
contents of general-purpose registers.
• Single + 5 V power supply-all pins TTLcompatible.
• Low Power version (Z8611L):
Available 8 MHz
- Current consumption 80 mA
• Available in 8 and 12 MHz versions.

General Description
The Z8611 microcomputer introduces a
new level of sophistication to single-chip
architecture. Compared to earlier single-chip
microcomputers, the Z8611 offers faster
execution; more efficient use of memory;
more sophisticated interrupt, input/output
and bit-manipulation capabilities; and easier
system expansion.
Under program control, the Z8611 can be

tailored to the needs of its user. It can be
configured as a stand-alone microcomputer
with 4K bytes of internal ROM, a traditional
microprocessor that manages up to 120K
bytes of external memory, or a parallelprocessing element in a system with other
processors and peripheral controllers linked
by the Z-BUS. In all configurations, a large
number of pins remain available for I/O.

PORTO
(NIBBLE
PROGRAMMABLE)
110 or Ae-A1S

PORTa

(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND

PARALLEL 110
AND CONTROL

Figure 1. Logic Functions

35

General gescription (Continued)

Vee

P3,

VMM/XTAL2

P3,

XTAL1

P2,

P3,

P2,

P3,

P2,

RESET

39

N.C.

P2,

R/W

3S

P24

RIW

P2,

os

Os

P2,

AS

36

P22

=

6

Ij

4

3

7.

1

1,4

43 42 41

40

P',
10

AS

P2,

P3 5

11

35

P2 1

P3,

P2,

uNO

12

34

P20

GND

P3,

P32

13

33

P33

P3,

P3,

POo

14

32

P34

po,
po,
po,
po,
po,
po,
po,
po,

P1,

PO,

31

P1,

P1,

PO,

30

P16

29

P1s

P1,
P1,

N,C,

Z86ll

17
16 19

20

21

22

23 24 25

26 27

ZB

5-1101

P1,
P1,
P1,
P1,
N.C ... NO CONNECTION

Figure 2. Pin Configuration

Figure 2a. Chip Carrier Pin Configuration

Architecture
Z8611 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand
powerful I/O capabilities. The Z8611 fulfills
this with 32 pins dedicated to input and
output. These lines are grouped into four
ports of eight lines each and are
configurable under software control to
provide timing, status signals, serial or
parallel I/O with or without handshake, and
an address/data bus for interfacing external
memory.
Because the multiplexed address/data bus
is merged with the I/O-oriented ports, the
Z8611 can assume many different memory
and I/O configurations. These configurations

36

range from a self-contained microcomputer
to a microprocessor that can address l20K
bytes of external memory (Figure 3).
Three basic address spaces are available to
support this wide range of configurations:
program memory (internal and external),
data memory (external) and the register file
(internal). The l44-byte random-access
register file is composed of 124 generalpurpose registers, four I/O port registers,
and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.

Architecture (Continued)
OUTPUT

110

ADDRESS OR 110

(BIT PROGRAMMABLE)

(NIBBLE PROGRAMMABLE)

ADDRESS/DATA OR 1/0
(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

Pin Description

AS. Address Strobe (output, active Low).

P10-P17' I/O Port Lines (input/output, TTL

Address Strobe is pulsed once at the
beginning of each machine cycle. Addresses
output via Port I for all external program or
data memory transfers are valid at the
trailing edge of AS. Under program control,
AS can be placed in the high-impedance
state along with Ports 0 and 1, Data Strobe
and Read/Write.

compatible). 8 lines Byte Programmable that
can be configured under program control for
I/O or multiplexed address (Ao-A7) and data
(Do- D7) lines used to interface with
program/data memory.

OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

POO-P07' I/O Port Lines (input/output, TTL
compatible). 8 lines Nibble Programmable
that can be configured under program
control for I/O or external memory interface.

P2o-P27' I/O Port Lines (input/output, TTL
compatible). 8 lines Bit Programmable. In
addition they can be configured to provide
open-drain output.

P30-P3,. Input Port Lines (TTL compatible).
They can also configured as control lines.
P3s-P37' Output Port Lines (TTL compatible).
They can also configured as control lines.

37
. - . - - - - . - - -..

~-------

Pin Description (Continued)
RESET. Reset (input, active Low). RESET
initializes the 28611. When RESET is
deactivated, program execution begins from
internal program location OOOCH.
R/W. Read/Write (output). RIW is Low when
the 28611 is writing to external program or
data memory.

Address Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 4096
bytes consist of on-chip mask-programmed
ROM. At addresses 4096 and greater, the
28611 executes external program memory
fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These
locations contain six 16-bit vectors that
correspond to the six available interrupts.
Data Memory. The 28611 can address 60K
bytes of external data memory beginning at
location 4096 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional 1/0 function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124

38

XTALL XTAL2. Crystal], Crystal 2 (timebase input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz
maximum) or an external single-phase clock
(8 or 12 MHz maximum) to the on-chip clock
oscillator and buffer.

general-purpose registers (R4-RI27) and 16
control and status registers (R240-R255).
These registers are assigned the address
locations shown in Figure 6.
28611 instructions can access registers
directly or indirectly with an 8-bit address
field. The 28611 also allows short 4-bit
register addressing using the Register
Pointer (one of the control registers). In the
4-bit mode, the register file is divided into
nine working-register groups, each
occupying 16 contiguous locations (Figure
7). The Register Pointer addresses the
starting location of the active workingregister group.

Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which
can reside anywhere in data memory
between locations 4096 and 65535. An 8-bit
Stack Pointer (R255) is used for the internal
stack that resides within the 124 generalpurpose registers (R4-RI27).

~

~

II
G""

'"

:

~&

'~~

"

'" ~

~"~

,,:;::"

'

,

~

"

,,'

'"

>'

i~ =

"

'

Address Spaces (Continued)
65535 , . . . - - - - - - - - - - ,

5535
EXTERNAL
ROM OR RAM

4096
4095
ON·CHIP

ROM

Location 01

Urat byllol
Instruction
executed

Ifterrese'

'ci ~-----------11

Interrupt
Vector

(Low.rByle)

Interrupt
Vector
(Upper Byte)

EXTERNAL

DATA
MEMORY

IRQS

10

IRQS

9

IRQ4

8

IRQ4

7

IR03

6

IR03

5i't-

IRQ2

4i-'

IRQ2

3

IRQ1

2

IRQi

1

IROO

°

IRCO

::~~------------------~
NOT ADDRf.SSABLE

Figure 4. Program Memory Map
LOCATION
211
214

247
241
245
244
243

STACK POINTER BITl7·Dl
STACK POINTER (BITl11·1)
REGISTER POINTER
PROGRAM CONTROL FLAGS
INTERRUPT MASK REGISTER
INTERRUPT REQUEST REGISTER
INTERRUPT PRIORITV REGISTER
PORTS 0·1 MODE
PORT 3 MODE
PORT 2 MODE
TO PRESCALER
TIMER/COUNTER 0
T1 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE
SERIAL I/O

213
H2
211
210

241
241

240

IDENTIFIERS
BPL
SPK
RP
FLAGS
IMR
IRQ
IPR
P01M
paM
P2M
PREO
TO
PRE1
T1
TMR
510

NOT

IMPLEMENTED

127

Figure 5. Data Memory Map

r----r~~:;I:~~~~:;~::~2~
_ _ { ~_'.:.'...:'.:.....;:'._';:..__,---,0:...,:.0.;0....0:.-..... 253
~------------------~24O

The upper nibble of the register lIIe acidress

provided by thtt register polnlerspecifi••
the a.;;tlve worklng.re'lliater'llroup.

127

--

{
{

Thllower
nibble 0'
thlrag'stlr

SPECIFIED WORKING·
REGISTER GROUP

-r:

III.ddress

provided by

helnltroctlon

points to tba

lpaclfled
ree'lier.

GENERAl·PURPOSE
REGISTERS

PORT 3

pa
P2

PORT 1

.,

PORT

PO

PORT 2

°

Figure 6. The Register File

--

15

t----'/OPORTS-----

3

Figure 7. The Register Pointer

39

Seriallnput/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for fullduplex serial asynchronous receiver/
transmitter operation. The bit rate is
controlled by Counter/Timer 0, with a
maximum rate of 62.5K bits/second for 8.
The Z8611 automatically adds a start bit
and two stop bits to transmitted data (Figure
8). Odd parity is also available as an option.
Eight data bits are always transmitted,

regardless of parity selection. If parity is
enabled, the eighth bit is the odd parity bit.
An interrupt request (IRQ4) is generated on
all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by
a parity error flag. Received characters
generate the IRQ3 interrupt request.

Transmitted Data

Received Data

(No Parity)

(No Parity)

~pISpl~I~I~I~I~I~I~I~IS~

T

1~1~1~1~1~1~1~1~1~lsij

I

LSTARTBIT
' - - - - - - E I G H T DATA BITS

LSTART BIT
' - - - - - - EIGHT DATA BITS

- - - - - - - - - O N E STOP BIT

TWO STOP BITS

1...

Transmitted Data

Received Data

(With Parity)

(With Parity)

ISplspl pl~I~I~I~I~I~I~ls~

11

1~lpl~I~I~I~I~I~I~I~1

I

jl. _ _

LSTART BIT
....- - - - S E V E N DATA BITS

LSTARTBIT
' - - - - - - S E V E N DATA BITS

ODD PARITY

PARITY ERROR FLAG

TWO STOP BITS

' - - - - - - - - - - - O N E STOP BIT

Figure 8. Serial Data Formats

Counter ITimers
The Z8611 contains two 8-bit
programmable counter/timers (To and TI),
each driven by its own 6-bit programmable
prescaler. The TI prescaler can be driven by
internal ox external clock sources; however,
the TO prescaler is driven by the internal
clock only.
The 6-bit prescalers can divide the input
frequency of the clock source by any number
from 1 to 64. Each prescaler drives its
counter, which decrements the value (l to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request-IRQ4 (TO) or IRQs
(TI)-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
, initial value. The counters can also be
; programmed to stop upon reaching zero
(single-pass mode) or to automatically reload

40

the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the prescalers, can be read any time
without disturbing their value or count Mode.
The clock source for T I is user-definable
and can be the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and
a 6 MHz maximum for the 12 MHz device)
divided by four, or an external signal input
via Port 3. The Timer Mode register
configures the external timer input as an
external clock (1 MHz maximum), a trigger
input that can be retriggerable or nonretriggerable, or as a gate input for the
internal clock. The counter/timers can be
programmably cascaded by connecting the
To output to the input of T I. Port 3 line P36
also serves as a timer output (TOUT) through
which To, TI or the internal clock can be
output.

110 Ports
The Z8611 has 32 lines dedicated to input
and output. These lines are grouped into
four ports of eight lines each and are
configurable as input, output or
address/data. Under software control, the
ports can be programmed to provide address
output~, timing, status signals, serial I/O,
and parallel I/O with or without handshake.
All ports have active pull-ups and pulldowns compatible with TTL loads.

Port 1 can be programmed as a byte I/O
port or as an address/data port for
interfacing external memory. When used as
an I/O port, Port 1 may be placed under
handshake control. In this configuration, Port
3 lines P33 and P34 are used as the
handshake contois RDY 1 and DAV 1 (Ready
and Data Available).
Memory locations greater than 4096 are
referenced through Port 1. To interface
external memory, Port 1 must be
programmed for the multiplexed Address/
Data mode. If more than 256 external
locations are required, Port 0 must output
the additional lines.
Port 1 can be placed in the highimpedance state along with Port 0, AS, DS
and R/W, allowing the Z8611 to share
common resources in multiprocessor and
DMA applications. Data transfers can be
controlled by assigning P33 as a Bus
Acknowledge input and P34 as a Bus
Request output.
PORT 1
(110 OR Ao,-Ao,)

P32 and P35 are used as the handshake
controls DAVo and RDYo. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0
can provide address bits As-All (lower
nibble) or As-A]5 (lower and upper nibble)
depending on the required address space. If
the address range requires 12 bits or less,
the upper nibble of Port 0 can be
programmed independently as I/O while the
lower nibble is used for addressing. When
Port 0 nibbles are defined as address bits,
they can be set to the high-impedance sta~
along with Port 1 and the control signals AS,
DS and RIW.

j

PORT 0
(1/0 OR Aa-A,sl

_

) HANDSHAKE CONTROl$

DAVo AND RDYo
(P32 AND P3S>

Figure 9b. Port 0

Port 2 bits can be programmed
independently as input or output. The port is
always available for I/O operations. In
addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this
configuration, Port 3 lines P3] and P36 are
used as the handshake controls lines DAV2
and RDY2. The handshake signal assignment
for Port 3 lines P3] and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

HANDSHA1IE CONTROLS
} DAV1 AND RDY1
(P3, AND P'~

IJtORT2(I/O)

Figure 9a. Port 1

Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port 0 may be placed under handshake
control. In this configuration, Port 3 lines

~}

HANDSHAKE CONTROLS

DAV2 AND RDY2
(P3, AND P3S>

Figure 9c. Port 2

41

II

~

~:,;

0i:c

,~

,

,
"

~

"'

""0

x '/ x
j

J:

J

I/O Ports (Continued)
Port 3 lines can be configured as I/O or
control lines. In either case, the direction of
the eight lines is fixed as four input (P30-P33)
and four output (P34-P37). For serial I/O,
lines P30 and P37 are programmed as serial
in and serial out respectively.
Port 3 can also provide the following
control functions: handshake for Ports 0,
and 2 (DAV and RDY); four external
interrupt request signals (IRQO-IRQ3); timer
input and output signals (TIN and Tour) and
Data Memory Select (DM).

POAT3
(110 OR CONTROL)

Figure 9d. Port 3

Interrupts
The Z8611 allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or individually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z8611 interrupts are vectored. When
an interrupt request is granted, and interrupt
machine cycle is entered. This disables all

subsequent interrupts, saves the Program
Counter and status flags, and branches to
the program memory vector location
reserved for that interrupt. This memory
location and the next byte contain the 16-bit
address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also
supported. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended

42

capacitors (Cl :S 15 pF) from each pin to
ground. The speCifications for the crystal are
as follows:
• AT cut, parallel resonant
• Fundamental types, 8112 MHz maximum
• Series resistance, Rs :S 100 O.

Power Down Standby Option
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to .the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input.
This necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 10 shows the recommended circuit for
a battery back-up supply system.

+5 V

0------.---; Voo
Z8S11

Figure 10. Recommended Driver Circuit
for Power Down Operation

Instruction Set Notation
Addressing Modes. The following notation is
used to describe the addressing modes and
instruction operations as shown in the
instruction summary.
IRR
Irr
X

DA
RA

1M

R
IR
Ir
RR

Indirect register pair or indirect workingregister pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Symbols. The following symbols are used in
describing the instruction set.
dst

Destination location or contents
Source location or contents
ore
Condition code (see list)
cc
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register painter (control register 253)

IMR

Interrupt mask register (control register 251)

Assignment of a value is indicated by the
symbol "+--". For example,
dst+--dst + src
indicates that the source data is added to the
destination data and the result is stored in
the destination location. The notation
"addr(n)" is used to refer to bit "n" of a
given location. For example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the
following six flags:
C

Z
S
V
D
H

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

b7

bo

Ie IzIsIv ID IH IF21FlI
FI
F2

user flags

Affected flags are indicated by:

o
I

*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

43

Condition Codes

44

Value

Mneomonic

1000
0111
Illl
OllO
IllO
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
I III
0111
1011
0011
0000

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning

Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater thaN
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set
C~I

C~O
Z~l
Z~O
S~O

S~I
V~l
V~O
Z~I

Z~O

(S
(S
[Z
[Z

XOR V)~O
XOR V)~I
OR (S XOR V)]~O
OR (S XOR V)] ~ I

C~O
C~I
(C~O

(C OR

AND

Z~O)~I

Z)~I

Instruction Formats
OPC

d"

CCF, 01, EI, lRET, NOP,
ReF, RET, SCF
INC r

OPC

One-Byte Instruction

ope

MODe

dstlsrc

CLR, CPl, CA, DEC,
OR

11

1

OPC

101 dstlsrc I ~~~~'~~~R~~~~R,POP,

E1[J

."

OR

ds'

RRC, SRA, SWAP

Ace, ADD, AND, CP,
lD, OR, SSC, SU8,
TeM, TM, XOR

MODE

OR

1 1 1 0
1 1 1 0

d"

OR

11 1101

dS!

JP, CALL (IndlreC.I)

OR

h 1 1 01

MODE

OPC

dst

dot

OPC

VALUE

SRP

Ace, ADO, AND, CP,
LD, OR, sac, SUB,
reM, TM, XOR

VALUE

MOCE

ope

MODE

ADe, ADD, AND,
CP, OR, sec, SUB,

ds.

LD
OR
OR

1 1 1 0
1 1 1 0

ds.

reM, TM, XOR

MODE

ope

dst/src

srcJdst

dst/src

ope

srcJdst

dst

OPC

dS!

lope

LD, LDE, lDEI,
LOC, LOCI

OPC

LD

ADDRESS
LD

OR

OPC

1,-,'-,'_',-0",1-"",--,

JP

OA,
OA,
LO

VALUE

IdStlCCR~ ope

MODE
dst/src

OPC
OJNZ, JR

CAll

OA,
DA,

Two-Byte Instruction

Three-Byte Instruction
Figure 11. Instruction Formats

45

Instruction Summary
Instruction
and Operation

Addr Mode
arc

ADC ds!,src (
ds! - ds! + src'+ C

(No!e 1)

ADD ds!,src
ds! - ds! + src

(No!e 1)

AND dS!,src
ds! - ds! AND src

Opcode Flags Allected
Byte

dat

(No!e 1)

(Hex)· C Z S V D H
10

00
50

CALL ds!
DA
SP - SP - 2
IRR
@SP - PC; PC - ds!

D6

CCF
C - NOT C

EF
R

BO
BI

R

IR

60
. 61

CP ds!,src
ds! - src

(No!e 1)

AD

DA ds!
ds! - DA ds!

R
IR

40

DEC ds!
ds! - ds! - 1

R

IR

00
01

COM ds!
, ds! - NOT ds!

DECW ds!
ds!-ds!-I

RR
IR

DJNZ r,ds!

RA

.. .. * X

41

80

81

- * *

- * *

* - * - -

rA
r~O-F

EI
IMR(7) - 1

9F

INC ds!
ds!-ds!+1

rE

X

X

r

r

Ir

C7
D7
E3

r

F3

R

R
IR

E4
E5

R
IR

1m
1m

E6

IR

R

F5

r

Irr

C2
D2

LOCI dsLsrc
Ir
Irr
ds! - src
r-r+ 1; rr-rr+ 1

Irr
Ir

C3
D3

LDE ds!,src
ds! - src

r
Irr

Irr

82

LDEI ds!,src
ds! - src

Ir
Irr

Irr
Ir

83
93

r - r

+ 1;

rr - rr

- * * * - -

IR

21

RR

AD
Al

DA

cD
c~O-F

Cl

IRR
RA

30

cB
c~O-F

C Z S VDH

r~O-F

Irr

E7

92

+1

NOP

FF

OR ds!,src
ds! - ds! OR src

(No!e I)

pop ds!
ds! - @SP
SP - SP +

R
IR

40

- .. .. 0

'50
51

R
IR

70
71

RCF

CF

RET

AF

0-- - - -

90

RL ds!

91

20

!RET .
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR (7) - 1

46

r

R

C-O

r~O-F

IR

if cc is true,
PC-PC+ds!
Range: + 127, -128

rC
r8
r9

R

PC - @ SP; SP - SP + 2
R

JR cC,ds!

1m

r

PUSH src
SP-SP-I; @SP-src

0
PC-PC+ds!
Range: + 127, -128

JP cc,ds!
if cc is true
PC - ds!

r

LD ds!,src
dst - src

LDC ds!,src
ds! - src

r ;0

INCW ds!
ds! - ds! +

(Hex)

Ir
R

8F

r - r - 1

if

Byte
arc

• • 0

.. .. 0 - -

Opcode Flags Affected

dst

.. * 0 ..

Dl
IMR (7) - 0

Addr Mode

D4

IR

CLR ds!
ds! - 0

.. .. .. .. 0 *

Instruction
and Operation

--*.--

RLCds!

I~ ~I R
~IR

10
11

RRds!

~,
'tJ~

EO
EI

RRC ds!

R
IR

lci:I=ci I~

SBC ds!,src
ds! - ds!- sr" - C

(No!e 1)

SCF
C-I
SRA ds!

LEi @

I~

CO
CI
3D

• 1 •

DF

1 - - - - -

DO

***0--

DI

Instruction Summary (Continued)

Il18truclioD
oDd OperolioD

Addr Mod.
dot

SRP src
RP - src
SUB dst,src
dst - dst - src

IrC

1m
(Note I)

SWAPdst~ R
IR

Opcod. Fiogi Aflect.d
Byt.
(H.x)
CZSVDH
31

------

20

•

FO
FI

X

'II

....

1

.

.. * X - -

Not.l

Il18truclioD
oDd OperolioD

Addr Mod.' Opcod. Fiogi Allected
Byt.
dot
Ire
(H.x)
CZSVDH

lCM dst,src
(NOT dst) AND src

(Note I)

60

- * .. 0

TN dst, src
dst AND src

(Note I)

70

- ..... 0

XOR dst,src
dst - dst XOR src

(Note I)

BO

-**0--

Addr Mod.
dot

IrC

R
R
R
IR

Ir
R
IR
1M
1M

These instructions have an identical set of addressing

modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, to determine the opcode of an ADC
instruction using the addressing modes r (destination) and
Ir (source).i. 13.

Lo.er
Opcod. Klbbl.
~

m
rn
[]]

rID

rn

47

Registers
R240 SIO
Serial 1/0 Register
(FOH; Read/Write)

R244 TO
Counter ITimer 0 Register
(F4H; Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

IL- - - - S E R I A l . DATA (Do = LSS)

To", MODES
= 00
: ~~
INTERNAL CLOCK OUT", 11
NOT useD

i~ g~i

To INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)

R241 TMR
Timer Mode Register
(FIH; Read/Write)

R245 PREO
Pres caler 0 Register
(F5H; Write Only)

[OJii'JD, ID.I D, ID, ID, ID. I

I~I~I~I~I~I~I~I~I

j

US~o = NO FUNCTION
1 '" LOAO To

0 "" DISABLE To COUNT
1 = ENAB~E To COUNT

COUNTMODE
o = To SINGLE·PASS

~L

1 ::: To MODUlD·N

RESERVED

0 = NO FUNCTION
1 "" LOAD T1
0 = DISABLE T, COUNT

T MODES
EXTERNAL CLOCK INP~T = 00
GATE INPUT"" 01

(NON'R~~~~g~:~~:~~) '"

PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

1 = ENABLE T, COUNT

10
TRIGGER INPUT = 11
(RETRIGGERABLE)

R242 Tl
Counter Timer I Register
(F2H; ReadlWrite)

R246 P2M
Port 2 Mode Register
(F6H; Write Only)

I~I~I~I~I~I~I~I~I

1~1~1~I~i~I~I~I~1

L

T, INITIAL VALUE (WHEN WRITTEN)

P2 0-P2 7 110 DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

---(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)

R247 P3M
Port 3 Mode Register
(F7H; Write Only)

R243 PREI
Prescaler 1 Register
(F3H; Write Only)

1~1~1~1~!~I~I~i~1

I~I~I~I~I~I~I~I~I

~L

· 0 PORT 2 PULL·UPSOPEN DRAIN

E~

COUNTMODE
o '" T, SINGlE·PASS
1 "" T, MOOUlO·N

CLOCK SOURCE
1 = TjlNTERNAL

o '"

Tl EXTERNAL TIMING INPUT

RESERVED

o P32

"" INPUT
P3S
1 P32 ::: DAVOIRDYO P35

00 P33

(T1W MODE
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

1 PORT 2 PULL·UPS ACTIVE

~~}P33

=:

INPUT

~
=:

OUTPUT
ROYO/IDW'O

=:

OUTPUT

INPUT
P34 = OM
1 1 P33::: DAV1/RDY1 P34 = RDY11DAV1
0;;

'-------~ ~~~ ~ ~NJ~;~~~~ ~:

'-------- ~ ~;g ~ ~~~lL
'---------~ ~!=:i~ g~F

Figure 12. Control Registers

48

P34

IN

: ~~~~~~_fUT)

~;i ~ ~~~iA~TOUT

Registers (Continued)
R248 POIM
Port 0 and 1 Mode Register

R252 FLAGS
Flag Register

(FBH; Write Only)

(FCH; ReadlWrite)

I~I~I~I~I~I~I~I~I

l~f~I~I~I~I~I~I~1

PO'_PO'MOOE~
~-r
=
L PO.-~MODE
=
=
=

OUTPUT
INPUT
A'2-A'5

00
01

'

00
01
1X

= 1X

EXTERNAL MEMORY T I M I N G .
NORMAL

EXTENDED

=

ll!~~
1

OUTPUT
INPUT

STACK SELECTION

= EXTERNAL
1 = INTERNAL

0

0

=1

LUSER FLAG F1

LUSER FLAG F2

= Aa-AH

P1 a-P1 7 MODE

=

ZERO FLAG

BYTE INPUT

10 = ADo-ADl
11

=

DECIMAL ADJUST FLAG
OVERFLOW FLAG

SIGN FLAG

00 .. BYTE OUTPUT
01

HALF CARRY FL.AG

CARRY FLAG

HIGH·IMPEDANCE ADo-ADJ.
AS, OS, RIW, Aa-A11. A12-AHi

IF SELECTED

R2491PR
Interrupt Priority Register

R253 RP
Register Pointer

(F9H; Write Only)

(FDH; Read/Write)

I~I~I~I~I~I~I~I~I
RESERVED

IT

:oJ

IRQ3, IROS PRIORITY (GROUP A)
o == IROS :> IRQ3

1

= IR03

[INTERRUPT GROUP PRIORITY

RESERVED = 000
C > A > B = 001
A > B > C = 010

> C '> A = 100
> B > A = 101
B :> A :> C = 110
RESERVED = 111
8

IROO, IR02 PRIORITY (GROUP 8)

o = IRQ2
1 = IRoo

REGISTER
POINTER

A> C > B = 011

> IROS

C

> IROO
> IRQ2

IRQ1, .RQ4 PR~O~lr~J~~O~Q~) _ _ _ _ _ _- - l
1

=

IRQ4

>

IRQ1

R250 ffiQ
Interrupt Request Register

R254 SPH
Stack Pointer

(FAH; ReadlWrite)

(FEH; ReadlWrite)

I~I~I~I~I~I~I~I~I

RESERVED

::::r-

c==

I~I~!~I~I~I~I~I~I
IROO •

po, INPUT IDo

• IRQO)

IRQ1 = P3a INPUT
IRQ2 == P3, INPUT

1
..._ _ _ _

:~~~~S~~=~!~ UPPER

=

IR03
P30 INPUT. SERIAL INPUT
IR04 • To. SERIAL OUTPUT
IROS. T,

R251lMR
Interrupt Mask Register

R255 SPL
Stack Pointer

(FBH; ReadlWrite)

(FFH; ReadlWrite)§

I~I~I~I~I~I~I~I~I

I. I

c==

L-_ _ _ _ _ _

I~I~I~I~I~I~I~I~I
1 ENABLES IROO-IRQ'
IROO)
RESERVED

(Do

=

1.1_ _ _ _

:~~~~s:~~::~R

LOWER

L _ _ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

Figure 12a. Control Registers (Continued)

49

Opcode Map
6,5

6,5

DEC

DEC

Tl, f2

ll,Irl

R2,n}

IH2,Hl

HI,IM

IRI,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RLC

RLC

ADC

ADC

ADC ADC

ADC

ADC

fl,l2

ll,hz

82,Hl

Hl,IM

IRI,IM

H,

H,

f.!

z:
~

0.
0.

JR,

6',5

6,5

10,5

10,5

10,5

la,S

SUB

SUB

SUB

SUB

SUB

fl, I:Z

Il, ll 2

81,Rl

1H z, HI

HI,IM

rRt/IM

JR,

8,0

6, I

6,5

6,5

10,5

10,5

10,5

10,5

IP

SRP

SBC

SBC

SBC

SBC

SBC

SBe

rl,l:Z

1M

fl,lr2

82, ftl

IR2,Rl

HI,IM

rHl,IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

fl, f2

II, III

82,RI

IHz,HJ

OR
RI11M

IH,
10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

AND

ANP

AND

AND

AND

AND

l1,l2

ll,Ir:z

R2,Hl

IR:z,Rl

Hl,lM

IRJ,IM

JR,

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

H,

IH,

IBI,IM

lJ,l2

TCM
ll,Ir:z

R2,HI

IR2,HI

TCM
Hl,IM

10/12,1 12/14,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

H,

IR,

ll,l2

ll,lr:z

Hz,Hl

IR2,Rl

Rl,IM

IRI,IM

10,5

10,5

12,0

18,0

LDE

LDEI

11,lrr2

Irl,Irr:z

C

D

F

12,0

RL

LDE

LDEI

JR,

I;Z,IUI

lrl,hfl

10,5
INCW
HH,

10,5

6,5

6,5

10,5

10,5

CP

CP

CP

CP

CP

II,hz

Hz,HI

IHz,Rl

HI,IM

IRI,IM

6,5

6,5

6,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

H,

IH,

11,IZ

II,hz

H2,RI

IHz,Hl

RI,IM

IRLIM

6,5

10,5

10,5

10,5

6,5

6,5

RRC

LPC

LDCI

LD

H,

IH,

11,IIIZ

IrI,Irrz

II, x, Hz

18,0

6,5

6,5

18,0

2fJ,0

20,0

SRA

LDC

LOCI

JR,

CALL"

CALL

LD

H,

IZ,Ir!l

hZ,IrI!

IRRI

DA

IZ, x, HI

6,5

6,7

6,7

I",

10,5

LD
Irz

LD

LD

LD

LD

R2,Rl

IH2,RI

HI,IM

IHI,IM

10,5

6,5

JR,

10,5

LD

DINZ

IR

LD

IP

INC

f2,RI

rt,RA

ee, RA

!I,IM

cc,DA

"

"

f--------

r------I--r-----

f--------

f-------Dl
~

f-------6,1

I--14,0

RET

f-------16,0

IRET

f-------6,5

RCF

f-------6,5

SCF

I---

10,5

6,5

CCF

I--6,0

LD
R2,IR}

V'

F

I---

10,5

LD
111,IZ

I",

V'

NOP
.I

I",

'---------~~~----------," ~ ~

Lower
Opcode
Nlbbl.
Execution
Cycle.

t

Pipeline
Cycl..

Upper

Opcode -----. A
Nlbbl.
Fint
Operand

Mnemonic

Second
Operand

·2·byte inslrucllon; fetch cycle appears as a 3-byte Instruction

50

LD

10,5

6,5
11,

SWAP SWAP

6,5

10,5

SRA

RR

E

IG,5

RRC

JR,

D
12/10,0

10,5

CP

R,

6,5

EI
10,5

11,IZ

RR

C

6,1

IH,

12,0

B
12/10,0

I

INCW

12,0

A
12/10,5

rl,R:z

18,0

H,

H,

Byte. per
Instruction

6,5

RL

6,5

E

JR,

6,5

6,5

IRI,IM

10,5

POP

6,5

B

IR2,Rl

SUB

HH,

A

10,5

ADD ADD ADD ADD ADD ADD

IH,

DECW PECW

::>

10,5

6,5

H,

A

10,5

INC

H,

.

10,5

6,5

6,5

IRRl

;;

6,5

INC
H,

..•

Lower Nibble (Hex)

Legend:
R = 8- Bit Address
r = 4-Bit Address
R I or r J == Dsl Address
RJ or r2 == Src Address

Sequence:
Opcode, First Operand. Second Operilnd
Note: The blank areas are not defined

Absolute Maximum Ratings
Voltages on all pins
with respect to GND ........ - 0.3 V to + 7.0 V
Operating Ambient
Temperature ....................... O°C to + 70°C
Storage Temperature ....... - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; operation of the device at any condition

above those indicated in the operational sections of these
specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Standard Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the
reference pin. Standard conditions are as
follows:

+5V

o
o
o

+4.75 V ::; Vee::; +5.25 V
GND=O V
O°C ::; TA ::; +70°C

+5V

+5V
2.1K

+5V

18'
1.Sk

1.Sk
74LS04

74LS04

Cl,~C' - - ito...o-~>-,...i)
)
to...o-~>-,..._
...
...

!

XTAl2

I

CL

= 15pF MAX

L _ _ _ _,..._ XTAL1

1
I

CL = 15pF MAX

Figure 13. Test Load I

Figure 14. Test Load 2

Figure 15. External Clock Interface Circuit
(Both the clock and its complement are required)

51

DC Characteristics
Symbol

Parameter

Min

Max

Unit

3.S

Vee

V

Driven by External Clock Generator

-0.3

O.S

V

Driven by External Clock Generator

VeH

Clock Input High Voltage

VeL

Clock Input Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

VRH

Reset Input High Voltage

VRL

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

IOL

Output Leakage

IJR

Reset Input Current

-50

lee

Vee Supply Current

120
SO'

IMM

VM M Supply Current

Backup Supply Voltage
VMM
• This value is for ZS611L only

52

Condition

2.0

Vee

V

-0.3

O.S

V

3.S

Vee

V

-0.3

O.S

V

0.4

V

-10

10

",A

-10

10

",A
",A
rnA

Vee = +5.25 V, VRL=O V

10

rnA

Power Down Mode

Vee

V

2.4

3

V

IOH= -250 ",A
IOL= +2.0 rnA

o V",
o V",

VIN
VIN

'"
'"

Power Down

+5.25 V
+5.25 V

External 1/0 or Memory Read and Write Timing
Z8611/L

No

Symbol

Paramter

Min

TeIA(AS)
Address Valid to AS t Delay
1
TdAS(A)
AS t to Address Float Dealy
2
TdAS(DR)
3
AS t to Read Data Required Valid
4
TwAS
AS Low Width
TelAz(DS)
Address Float to DS t
5
6-TwDSR---DS (Read) Low Width
DS (Write) Low Width
7
TwDSW
TdDSR(DR)
DS t to Read Data Required Valid
8
ThDR(DS)
Read Data to DS t Hold Time
9
TdDS(A)
DS t to Address Active Delay
10
11
TdDS(AS)
DS t to AS t Delay
12-TdRlW(AS)--RiW Valid to AS t Delay
TdDS(RIW)
DS t to RiW Not Valid
13
TdDW(DSW) Write Data Valid to DS (Write) t Delay
14
TdDS(DW)
DS t to Write Data Not Valid Delay
15
TeIA(DR)
16
Address Valid to Read Data Required Valid
TelAS(DS)
17
AS t to DS t Delay

Z8611A

Max

50
70

Min

Max Notes*t
360

45
360

80
0
250
160

220
55
0
185
110

200
0
70
70
50
60
50
70

130
0
45
55
30
35
35
45

410
80

255
55

1,2,3
1,2,3
1,2,3,4
1,2,3
1
1,2,3,4
1,2,3,4
1,2,3,4
1
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3

NOTES:

I. Tes! Load I
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.

4. When using extended memory timing add 2 TpC.

5. All timing reference use 2.0 V for a logic "I" and 0.8 V for a
logic "0".
* All units in nanoseconds (ns),

t

Timings are preliminary and subject to change.

PORT 0,
DM

PORT 1

__________;-______~1~----~0~--------·1~----;_---Dli
(READ)

PORT 1

Do-D, OUT

Dli
(WRITE)

Figure 16. Extemal 110 or Memory Read/Write

53

Additional Timing Table
Z8611/L

No

Symbol

Paramter

TpC
Input Clock Period
Clock Input Rise And Fall Times
TrC, TfC
TwC
Input Clock Width
TwTinL
Timer Input Low Width
4
5--TwTinH---Timer Input High Width
TpTin
Timer Input Period
6
TrTin, TfTin
Timer Input Rise And Fall Times
7
TwIL
Interrupt Request Input Low Time
Sa
Interrupt Request Input Low Time
Sb
TwIL
Interrupt Request Input High Time
9
TwlH
I

2
3

NOTES:
1. Clock timing rf'Aerences uses 3.8 V for a logic "I" and 0.8 V
for a logic "0".
2. Timing referance uses 2.0 V for a logic "I" and 0.8 V for a
logic "0".

Max

Min

125

1000
25

S3

37
100
3TpC
STpC

Max Notes*t
1000
15

26
70
3TpC
STpC
100

100
100
3TpC
3TpC

70
3TpC
3TpC

3. Interrupt request via Port 3 (P31 -P33)"

4. Interrupt request via Port 3 (P30).
*

Units in nanoseconds (ns).

t Timings are preliminary and subject to change.

Figure 17. Additional Timing

54

Z8611A

Min

2
2
2
2
2,3
2,4
2,3

Handshake Timing
No

Paramter

Symbol

Min

Z8611/L
Max

1

TsDI(DAV)
Data In Setup Time
0
ThDI(DAV)
Data In Hold Time
230
3
TwDAV
Data Available Width
175
4
TdDAVIf(RDY)
DAV t Input to RDY t Delay
5-TdDAVOf(RDY)-DAV t Output to RDY t D e l a y - - - - - - 0
6
TdDAVIr(RDY)
DAV i Input to RDY i Delay
7
TdDAVOr(RDY)
DAV i Output to RDY i Delay
0
8
TdDO(DAV)
Data Out to DAV t Delay
50
9
TdRDY(DAV)
Rdy t Input to DAV i Delay
0

Z8611A
Min

Max Notes*t

0
160
120

2

175

120
0

175

200

120
0
30
0

1,2
1,3
1,2
1,3
1

140

NOTES:

1. Test Load I

4. All timing regerences use 2.0 V for a logic "1" and 0.8 V for
a logic "0".

2. Input handshake

3. Output handshake

Units in nanoseconds (ns).

t Timings are preliminary and subject to change.

DATA IN

DAV
(INPUT)

ROY
(OUTPUT)

Figure 18a. Input Handshake

DATA OUT

r-

DATA OUT VALID

-F1I=

---~----------------DAV
(OUTPUT)

ROY
(INPUT)

_ _---=)l\--,
-=:::.-=::l.-®~-~~

Figure 18b. Output Handshake

55

Clock-Cycle-Time-Dependent Characteristics
Number

Symbol
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdRIW(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

2
3
4
6
7
8
10
II
12
13
14
15
16
17
*

Z8611/L

Z8611A

Equation

Equation

TpC-75
TpC-55
4TpC-140'
TpC-45
3TpC-125'
2TpC-90'
3TpC-175'
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215'
TpC-45

TpC-50
TpC-40
4TpC-II0'
TpC-30
3TpC-65'
2TpC-55'
3TpC-120'
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160'
TpC-30

Add 2TpC when using extended memory timing.

Ordering Information
Type
Z8611
Z8611
Z8611
Z8611
Z8611
Z8611
Z8611
Z8611

Package
BI
B6
DI
D6
CI
C6
KI
K6

Plastic
Plastic
Ceramic

Ceramic

Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

Z8611A BI
Z8611A B6
Z8611A Dl
Z8611A D6
Z8611ACI
Z8611A C6
Z8611A KI
Z8611A K6

Plastic
Plastic
Ceramic

Z8611L
Z8611L
Z8611L
Z8611L
Z8611L
Z8611L
Z8611L
Z8611L

Plastic
Plastic

56

BI
B6
Dl
D6
CI
C6
KI
K6

Ceramic

Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

Ceramic
Ceramic

Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

Temp.

Clock

01 + 70°C
-401+85°C
01 + 70°C
-401+85°C
01 + 70°C
-401 +85°C
01 + 70°C
-401 +85°C

8 MHz

01 + 70°C
-401+85°C
01 +70°C
-401 +85°C
01 + 70°C
-401+85°C
01 + 70°C
-401+85°C

12 MHz

01 + 70°C
-401 + 85°C
01 + 70°C
-401 + 85°C
01 + 70°C
-401+ 85°C
01 + 70°C
-401+85°C

Description
4K ROM Microcomputer

4K ROM Microcomputer
Low Power version

8 MHz

aB.
Z8 8K ROM Microcomputer
• Complete microcomputer, 8K bytes of
ROM, 240 bytes of RAM, 32 IIO lines,
and up to 56K bytes addressable external
space each for program and data
memory.

• Register Pointer so that short, fast
instructions can access any of nine
working register groups in 1 flS.

• 256-byte register file, including 236
general-purpose registers, four I/O port
registers, and 16 status and control
registers.

• Low-power standby option that retains
contents of general-purpose registers.

• Minimum instruction execution time
at 12 MHz.

fls

• On-chip oscillator that accepts crystal or
external clock drive.

•

Single + 5 V power supply~all pins TTLcompatible.

• Vectored, priority interrupts for IIO,
counter/timers, and UART.

• Low Power version (28621L):
- Available 8 MHz
- Current consumption 80 rnA

• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.

• Available in 8 and 12 MHz versions.

General Description
The 28621 microcomputer introduces a
new level of sophistication to single-chip
architecture. Compared to earlier single-chip
microcomputers, the 28621 offers faster
execution; more efficient use of memory;
more sophisticated interrupt, input/output
and bit-manipulation capabilities; and easier
system expansion.
Under program control, the 28621 can be

tailored to the needs of its user. It can be
configured as a stand-alone microcomputer
with 8K bytes of internal ROM, a traditional
microprocessor that manages up to 112K
bytes of external memory, or a parallelproceSSing element in a system with other
processors and peripheral controllers linked
by the 2-BUS. In all configurations, a large
number of pins remain available for I/O.

PORTO
(NIBI!!ILE
PROGRAMMABLE) ,
I{O or Ae-A15

PORT 2

(BIT PRO·
GRAMMABLE)
I/O

PORT'
(BYTE

PROGRAMMABLE) I
110 or ADO-AD7

Figure I. Logic Functions

57

General Description (Continued)

Vee

P3,

VMM/XTAl2

P3,

XTAL1

P2,

P3,

P2,

P3.

P2,

=

P2.

AIW

P2,

os

P2,

AS

P2,

P3,

P2.

GND

P3,

P3,

P3.

po.
po,
po,
po,
po.
po,
po,
po,

P1,

6

~

"

3

2

1

44 43 t.2 10'

40

RESET

39

N.C.

R/W

38

P2 4

os
A5

10

37

P2 3

36

P22

P35

11

35

P2 1

GNO

12

31,

P20

P32

13

33

P3 3

POe

14

32

P34

31

P1?

Z8621

PO,

P1,

POl

16

30

P16

P1,

N,C.

17

29

P15

P1,

HI

19

20

21

22

23 24 75

26 27

2&

5 8991

P1,
P1,
P1,
P1,

Figure 2. Pin Configuration

N.C.zNO CONNECTlON

Figure 2a. Chip Carrier Pin Configuration

Architecture
Z8621 architecture is characterized by a
flexible I/O scheme, an effiCient register and
address space structure and a number of
anCillary features that are helpful in many
applications.
Microcomputer applications demand
powerful I/O capabilities. The Z8621 fulfills
this with 32 pins dedicated to input and
output. These lines are grouped into four
ports of eight lines each and are
configurable under software control to
provide timing, status signals, serial or
parallel I/O with or without handshake, and
an address/data bus for interfacing external
memory.
Because the multiplexed address/data bus
is merged with the I/O-oriented ports, the
Z8621 can assume many different memory
and I/O configurations. These configurations
range from a self-contained microcomputer

58

to a microprocessor that can address 112K
bytes of external memory (Figure 3).
Three basic address spaces are available to
support this wide range of configurations:
program memory (internal and external),
data memory (external) and the register file
(internal). The 256-byte random-access
register file is composed of 236 generalpurpose registers, four I/O port registers,
and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.

Architecture (Continued)

OUTPUT

"0
(BIT PROGRAMMABLE)

ADDRESS OR 1/0
(NIBBLE PROGRAMMABLE)

ADDRESS/DATA OR 1/0
(BYTE PROGRAMMABLE)

Figure 3. Block Diagram

Pin Description
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the
beginning of each machine cycle. Addresses
output via Port I for all external program or
data memory transfers are valid at the
trailing edge of AS. Under program control,
AS can be placed in the high-impedance
state along with Ports 0 and 1, Data Strobe
and ReadlWrite.
OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

POO-P07' I/O Port Lines (input/output, TTL
compatible). 8 lines Nibble Programmable
. that can be configured under program
control for I/O or external memory interface.

P1o-PI7' I/O Port Lines (input/output, TTL
compatible). 8 lines Byte Programmable that
can be configured under program control for
I/O or multiplexed address (Ao-A7) and data
(Do-D7) lines used to interface with
program/data memory.

P2o-P27. I/O Port Lines (input/output, TTL
compatible). 8 lines Bit Programmable. In
addition they can be configured to provide
open-drain output.

P30-P34. Input Port Lines (TTL compatible).
They can also configured as control lines.
P3s-P37' Output Port Lines (TTL compatible).
They can also configured as control lines .

59
------------------------------.------~

Pin Description (Continued)
RESET. Reset (input, active Low). RESET
initializes the Z8621. When RESET is
deactivated, program execution begins from
internal program location OOOCH.
R/W. Read/Write (output). RIW is Low when
the Z8621 is writing to external program or
data memory.

XTALL XTAL2. Crystoll, Crystal 2 (timebase input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz
maximum) or an external single-phase clock
(8 or 12 MHz maximum) to the on-chip clock
oscillator and buffer.

Address Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 8192
bytes consist of on-chip mask-programmed
ROM. At addresses 8192 and greater, the
Z8621 executes external program memory
fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These
locations contain six 16-bit vectors that
correspond to the six available interrupts.
Data Memory. The Z8621 can address 56K
bytes of external data memory beginning at
locations 8192 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 256-byte register file
includes four 1/0 port registers (RO-R3), 236

60

general-purpose registers (R4-R238) and 16
control and status registers (R240-R255).
These registers are assigned the address
locations shown in Figure 6.
Z8621 instructions can access registers
directly or indirectly with an 8-bit address
field. The Z8621 also allows short 4-bit
register addressing using the Register
Pointer (one of the control registers). In the
4-bit mode, the register file is divided into
nine working-register groups, each
occupying 16 contiguous locations (Figure
7). The Register Pointer addresses the
starting location of the active workingregister group.

Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which
can reside anywhere in data memory
between locations 8192 and 65535. An 8-bit
Stack Pointer (R255) is used for the internal
stack that resides within the 236 generalpurpose registers (R4-R238).

Address Spaces (Continued)

65535.----------.....,

5535
EXTERNAL
ROM OR RAM

192
191
ON·CHIP

ROM

Location 01

lirstbytaof
Instruction

executed

alter reset

;;-

Interrupt

Vector

(lower Byte)

Interrupt
Vector
(Upper Byte)

EXTERNAL
DATA

~------------

,.

IROS

9

IRQ4

11

MEMORY

IROS

8

IRQ4

7

IR03

6

IR03

4~

IR02

3

IRQ1

2

IR01

1

IROO

•

IROO

5....

lRQ2

:~~~ / - - - - - - - - - - - 1
NOT ADDRESSABLE

Figure 4. Program Memory Map
LOCATION

256
254
253
252

IDENTIFIERS
SPL

STACK POINTER (BITS 7-0)
STACK POINTER (BITS 16-8)
REalSTER POINTER

SPH
RP
FLAOS

PRoaRAM CONTROL FLAas

249

INTERRUPT MASK REalSTER
INTERRUPT REQUEST REOISTER
INTERRUPT PRIORITY REOISTER

249

PORTS 0-1 MODE

261

2aO

IMR
IRQ

247

PORT 3 MODE

IPR
P01M
P3M

248

PORT 2 MODE

P2M
PREO
TO

245

TO PRESCALER

244
243

TIMER/COUNTER 0

242

TIMER/COUNTER 1

241

TIMER MODE

240

SERIAL 110

PRE1

T1 PRESCAlER

T1
TMR
510

239
I

127
GENERAL·PURPOSE
REGISTERS

PORT 3

1__ f~:::;:;::::;::::255

~_ _ _ _- L_ _ _ _~'53

--

L-.---------....I240
Tho I,Ippernlbble of Iherogisterlile address

provided by the reglstorpolnterspeciliu
theactlveworkll1g.reglstergroup.

--I
--I
--I
--I
__ I(
--I
--I

r---------.,127

SPECIFIED WORKING·
REGISTER GROUP

1-------1

P3

PORT 2

P'

PORT 1

Pl

PORT 0

PO

Figure 6. The Register File

Figure 5. Data Memory Map

The lower
l1ibbleol
the register
lUeaddre$5
provided by
thell1struetiOI1
paints to the
specified
register.

~---------~15

I----"OPO"TS----- 3

Figure 7. The Register Pointer

61

Serial Input/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for fullduplex serial asynchronous receiver/
transmitter operation. The bit rate is
controlled by Counter/Timer 0, with a
maximum rate of 62.5K bits/second for 8.
The Z8621 automatically adds a start bit
and two stop bits to transmitted data (Figure
8). Odd parity is also available as an option.
Eight data bits are always transmitted,

regardless of parity selection. If parity is
enabled, the eighth bit is the odd parity bit.
An interrupt request (IRQ4) is generated on
all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by
a parity error flag. Received characters
generate the IRQ3 interrupt request.

Transmitted Data

Received Data

(No Parity)

(No Parity)

lul~I~I~I~I~I~I~I~IHI

I

LSTART 81T
' - - - - - - E I G H T DATA BITS

L

LSTARTBIT
- - - E I G H T DATA BITS

L - - - - - - - - - - O N E STOP 81T

TWO STOP BITS

Transmitted Data

Received Data

(With Parity)

(With Parity)

lululpl~I~I~I~I~I~I~IHI

lulpl~I~I~I~I~I~I~IHI

11

II

IL--..--LsTARTBIT
- S E V E N DATA BITS
ODD PARITY

"

TWO STOP BITS

I

LSTART BIT

L - - . . - - S E V E N DATA BITS
PARITY ERROR FLAG

' - - - - - - - - - - O N E STOP BIT

Figure 8. Serial Data Formata

Counter/Timers
The Z8621 contains two 8-bit
programmable counter/timers (To and T j),
each driven by its own 6-bit programmble
prescaler. The Tj prescaler can be driven by
internal or external clock sources; however,
the To prescaler is driven by the internal
clock only.
The 6-bit prescalers can divide the input
frequency of the clock source by any number
from I to 64. Each prescaler drives its
counter, which decrements the value (I to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request-IRQ4 (To) or IRQ5
(Tj)-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be
programmed to stop upon reaching zero
(single-pass mode) or to automatically reload
62

the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the prescalers, can be read any time
without disturbing their value or count mode.
The clock source for Tj is user-definable
and can be the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and
6 MHz maximum for the 12 MHz device)
divided by four, or an external signal input
via Port 3. The Timer Mode register
configures the external timer input as an
external clock (I MHz maximum), a trigger
input that can be retriggerable or nonretriggerable, or as a gate input for the
internal clock. The counter/timers can be
porogrammably cascaded by connecting the
To output to the input of T j. Port 3 line P36
also serves as a timer output (TOUT) through
which To, Tj or the internal clock can be
output.

110 Ports
The Z8621 has 32 lines dedicated to input
and output. These lines are grouped into
four ports of eight lines each and are
configurable as input, output or
address/data. Under software control, the
ports can be programmed to provide address
outputs, timing, status signals, serial I/O,
and parallel I/O with or without handshake.
All ports have active pull-ups and pulldowns compatible with TTL loads.

Port 1 can be programmed as a byte I/O
port or as an address/data port for
interfacing external memory. When used as
an I/O port, Port 1 may be placed under
handshake controL In this configuration,
Port 3 lines P33 and P34 are used as the
handshake contoIs RDY 1 and DA VI (Ready
and Data Available).
Memory locations greater than 8192 are
referenced through Port 1. To interface
external memory, Port 1 must be
programmed for the multiplexed Address/
Data mode. If more than 256 external
locations are required, Port 0 must output
the additional lines.
Port 1 can be placed in the highimpedance state along with Port 0, AS, DS
and R/W, allowing the Z8621 to share
common resources in multiprocessor and
DMA applications. Data transfers can be
controlled by assigning P33 as a Bus
Acknowledge input and P34 as a Bus
Request output.

PORT 1
1/0 or ADo-AD7

Port 0 may be placed under handshake
control. In this configuration, Port 3 lines
P32 and P35 are used as the handshake
controls DA Vo and RDYo. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0
can provide address bits As-All (lower
nibble) or As-A!5 (lower and upper nibble)
depending on the required address space. If
the address range requires 12 bits or less,
the upper nibble of Port 0 can be
programmed independently as I/O while the
lower nibble is used for addressing. When
Port 0 nibbles are defined as address bits,
they can be set to the high-impedance state
along with Port 1 and the control signals AS,
DS and R/W.

I

PORT 0

(110 OR

A8-At~

Figure 9b. Pori 0

Port 2 bits can be programmed
independently as input or output. The port is
always available for I/O operations. In
addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and I, Port 2 may also be
placed under handshake control. In this
configuration, Port 3 lines P3! and P36 are

\ HAN DSHAKE CONTROLS

I

DAV, AND ROY,
(P3 3 AND P3 4)

PORT 2(110)

Figure 9a. Pori 1
}

Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,

HANDSHAKE CONTROLS

I5AV2 AND RDY2

(P3, AND

p~

Figure 9c. Pori 2

63

1/0 Ports (Continued)
used as the handshake controls lines DAV2
and RDY2. The handshake signal assignment
for Port 3 lines P3] and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

Port 3 lines can be configured as 1/0 or
control lines. In either case, the direction of
the eight lines is fixed as four input (P30-P33)
and four output (P34-P37). For serial 1/0,
lines P30 and P37 are programmed as serial
in and serial out respectively.
Port 3 can also provide the following
control functions: handshake for Ports 0,
and 2 (DAV and RDY); four external

interrupt request signals (IRQO-IRQ3); timer
input and output signals (TIN and TOUT) and
Data Memory Select (DM).

PORT 3
(1/0 OR CONTROL)

Figure 9d. Pori 3

Interrupts
The Z8621 allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or indiVidually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z8621 interrupts are vectored. When
an interrupt request is granted, and interrupt
machine cycle is entered. This disables all

subsequent interrupts, saves the Program
Counter and status flags, and branches to
the program memory vector location
reserved for that interrupt. This memory
location and the next byte contain the 16-bit
address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also
supported. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended

64

capacitors (C] :;; 15 pF) from each pin to
ground. The specifications for the crystal are
as follows:
• AT cut, parallel resonant
• Fundamental types, 8/!2 MHz maximum
• Series resistance, Rs :;; 100 n.

Power Down Standby Option
The low-power standby mode allows power
to be removed without losing the contents of
the 236 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input.
This necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 10 shows the recommended circuit for
a battery back-up supply system.

.5V

O - - - - - ; - - - i v••

TRICKLE

CHARGE(r-.J\I\IV--ii-l:"

Z8621
,

......-1)1----+---/ ~T:;}

J
Figure 10. Recommended Driver Circuit
for Power Down Operation

Instruction Set Notation
Addressing Modes. The following notation is
used to describe the addressing modes and
instruction operations as shown in the
instruction summary.
IRR
Irr
X
DA
RA
1M

R
IR

Ir
RR

Indirect register pair or indirect workingregister pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address

Assignment of a value is indicated by the
symbol '~<-". For example,
dst <- dst + src
indicates that the sourcEjl data is added to the
destination data and the result is stored in
the destination location. The notation
"addr(n)" is used to refer to bit "n" of a
given location. For example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the
following six flags:
C
Z

S

Symbols. The following symbols are used in
describing the instruction set.
dst
src
cc

Destination location or contents
Source location or contents
Condition code (see list)
@
Indirect address prelix
Stack pointer (control registers 254-255)
SP
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)
1MB.
Interrupt mask register (control register 251)

V

D
H

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

b7

bo

IC lzlsIVIDIHIF2IFlI
F1
F2

user flags

Affected flags are indicated by:

o
*
X

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

65

Condition Codes
Value
1000
Olll
lill
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

66

Mneomonic
C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater thaN
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set
C=I
C=O
Z=l
Z=O
5=0
5=1
V=l
V=O
Z=l
Z=O
(5 XOR V)=O
(5 XOR V)= 1
[Z OR (8 XOR V)] =0
[Z OR (5 XOR V)]=l
C=O
C=l
(C=O AND Z=O) = I
(C OR Z)= 1

Instruction Formats
ope
dst

CCF, 01, El, IRET, NOP,
ReF, RET, SCF

ope

INCr

One-Byte Instructions
ope

MODE

CLR, CPL, OA, DEC,

dstlsrc

OR

I

ope
f---'''CdS'''''---------1

11

1 1 o[ dst/src

I

ope
dst

RRC, SRA, SWAP

OR

It , , 0 I

ope

ope

dst

OR

I, , , 01

dst

MODE

SRP

MODE

Ace, ADO, AND,
CP, OR. sac, SUB,

MODE

dst

ADC, ADD, AND, CP,

ope

dst

LO, OR,

sac, SUB,

reM, TM, XOR

LO
OR

1 1 1 0

OR

1 1 1 0

dst

TeM, TM, XOR

MODE

ope

dstJsrc

srcldst

dstlsrc

ope

srcJdst

lope

lD, LDE, LDEI,
LOC, LOCI

MODE

dstlCCR~ ope

OPC

LO

dst/src
ADDRESS

LD
OR

OPC

<.:11...;''-',-",01---,,-,---,

JP

OA u
OA,
LD

VALUE

I

1 1 1 0

VALUE

VALUE

dst

sec,

LO, OR,
SU8,
TeM, TM, XOR

1 1 1 0

OR
OR

JP, CALL (Indirect)
dst

dst

ope

Ace. ADD, AND, CP,

MODE

~~~~'~~~R~~~:R.POP,

OPC

CALL

DAu
DA,

DJNZ. JR

Three-Byte Instructions

Two-Byte Instructions

Figure 11. Instruction Formats

67

Instruction Summqry
Instruction
and Operation

Addr Mode

ADC dst,src
dst - dst + src + C'

(Note 1)

Opcode Flags Affected
Byte

dBt

orc

(Hex)

C Z S VDH
* 0 •

10

ADD dst,src
dst - dst + src

(Note

1)

00

'" * '" * 0

AND dst,src
dst - dst AND src

(Note 1)

50

- * * 0

Instruction
and Operation
LD dst,src
dst - src

Addr Mode

r

r

CALL dst
DA
SP - SP - 2
IRR
@SP - PC; PC - dst

D6
D4

CCF

EF

R
IR

BO
Bl

COM dst
dst - NOT dst

R
IR

60
, 61

LOC dst,src
dst - src

(Note 1)

DA dst
dst - DA dst

R
IR

40
41

• X

DEC dst
dst-dst-l

R
IR

00
01

-***--

DECW ds!
dst-dst-I

RR

80
81

-***--

IR

DI
IMR (7) - 0

8F

DJNZ r,dst
RA
r - r - 1
if r .. 0
PC - PC -+ dst
Range: + 127, -128
EI
IMR(7) - I

rA
r:O-F

R
RR
IR

r
Irr

Irr

C2
D2

LOCI dst,src
Ir
dst - src
Irr
r - r + I; rr - rr + I

Irr
Ir

C3
D3

WE dst,src
dst - src

r
Irr

Irr

82
92

WEI dst,src
Ir
dst - src
Irr
r - r + 1; rr-rr+ 1

Irr
Ir

83
93

(Note I)

POP dst
dst - @SP
SP - SP +

R
IR

,- '"

'it

'"

-

JR

cc,dst

if cc is true,
PC-PC+dst
Range: + 127, -12B

68

'SO
51

R
IR

cD
c:O-F

IRR

30

RA

cB
c=O-F

70
71
CF

RET
PC - @SP; SP - SP + 2

AF

RL dst

90

o- - - - -

91

-***--

RLCdstl~~R
~IR

RRdst

DA

- '" '" 0 - -

-

.
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR(7) - I
A>B=001
A > B > C = 010
A > C > B "" 011
B > C > A = 100
C > B > A = 101
B > A > C ::: 110
RESERVED::: 111

IRQ3, IRQS PRIORITY (GROUP A)

o ""

lAOS> IRQ3

1 '" IRQ3 > IROS

IROO, IAQ2 PRIORITY (GROUP B)
o = IRQ2 > IROO - - - - - - - - '
1 '" IRao > IRQ2

mai, IRQ4 PRIORITY (GROUP C)
~~
~ :=g~

:=g!

LOON'TCARE
REGISTER

POINTER

--------'

R250 IRQ
Interrupt Request Register
(FAH; ReadlWrite)

R254 SPH
Stack Pointer
(FEH; Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

RESERVED

T"

c==

L ___

IROO = P:h INPUT (Do "" IROO)

IR01
IRQ2
IR03
IRQ4
IRa5

= P33 INPUT
= P31 INPUT
:: P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
= T1

=

R251 IMR
Interrupt Mask Register
(FBH; Read/Write)

R255 SPL
Stack Pointer
(FFH; Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

I'

_

c==

STACK POINTER UPPER
BYTE (SPe-SP15)

1 ENABLES IROO-IROS
(Do = IROO)

'--------RESERVED

' - - - - - - - - - 1 ENABLES INTERRUPTS
Figure 12. Control Registers (Continued)

71
-~----~----

Opcode Map

...
e

.!
.Q
:!!

:z:
~

Lower Nibble (Hex)

6,5

6,5

6,5

DEC

::>

A

C

D
E

f

10,5

6,5

10,5

6,5

A

B

c

12110,5

12/10,0

6,5

D

E

12/10,0

6,5

-DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DINZ

IR

LD

IP

[NC

IHI

II,ra

II,Ira

H2,Rl

IR2,Hl

HI,IM

lRI,IM

Il,R2

12, HI

n,RA

cc,RA

fl,IM

cc,DA

6,5

6,5

6,5

10,5

10,5

la,S

10,5

"

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IRI,IM

HI

IHI

fl, I2

Il,Ir2

R2,Rl

IR2,Hl

HI,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB

HI

IHI

n,la

t},lrl

Hz,Rl

IRz,Hl

HI,IM

IRI,IM

8,0

6,1

6,5

6,5

10,5

10,5

10,5

.10,5

IP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRRI

1M

11,12

II,Ira

H2,Rl

IR2,Rl

HI,IM

IR1,IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR
IRI,IM

HI

IHI

Il,12

Il,Ir2

H2,RI

JRiI,HI

HI,IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND

fl,

Ira

H2,Rl

IR2,Hl

HI,IM

IRI,IM

10,5

10,5

10,5

HI

IHI

II, I2

6,5

6,5

6',5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

HI

IHI

II, I2

Il/Irz

R2,Rl

IR2,Hl

Rl,IM

lRl,IM

10/12,1

12114,1

6,5

10,5

10,5

PUSH PUSH

TM

TM

TM

TM

TM

TM

11,12

Il,Ir2

H2,Rl

IRZ,RI

HI,IM

IRI,IM

H,

IH,

10,5

10,5

6,5

6,5

12,0.

18,0

LDE

LDEI

HHI

IHI

II,IIr2

In,IHa

6,5

6,5

12,0

18,0

LDE

LDEI

RL

ilL

HI

IRI

10,5

lO,S

10,5

6,5

IHI

f----J--J--J--6,1

D[
J--6,1

6,5

10,5

10,5

10,5

EI
J---

10,5

CP

CP

CP

CP

CP

CP

II, lr2

1\2,R'1

IRz,RI

HI,IM

IRI,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

XOR

XOR

XOR

XOR

XOR

XOR

HI

IHI

Il,I2

n,Ir2

R2, HI

IRz,RI

HI,IM

IRI,IM

6,5

6,5

RRC

RRC

LDC

LDC[

LD

HI

IHI

II,lrx2

In,lrr2

II. x, H2

6,5

6,5

SRA

HI

IRI

6,5

6,5

18,0

12,0

18,0

20,0

20,0

LOC

LOC[

CALL*

CALL

LD

IRRI

DA

12, x, HI

I2,IIII Ir2, IIII

6,5

10,5

10,5

10,5

LD

LD

LD

LD

LD

Il,Ir2

R2,RI

IR2,RI

RI,IM

IRI,IM

6,7

6,7

6,5

'V'

16,0

[RET

f-----

6,5

SCf
J--6,5

CCf
J---

10,5

6,0

LD

LD

hl,r2

R2,IRI

"

6,5

IICf

f-----

10,5

RR
IHI

IHI

f-----

10,5

HI

SWAP SWAP

14,0

RET

10,5

RR

I",

f-----

10,5

CLR

SRA

I",

'V'

NOP
./

I",.

'---------~~,-----------" ~ ~

Lower
Opcode
Nibb[e
Execution
Cyel..

t

PipeUne
Cycl..

Uppor

Opcode- A

Mnemonic

Legend:
R '= 8-Blt Address
r "" 4·Bit Address
R j or r I = Dst Address
R2 or r2 = Src Address

Nibble
Sequence:

Fint
Operand

Second
Operand

'2-byte instrucllon; fetch cycle appears as a 3-byte instructIOn

72

J---

f-----

10,5

It,I2

12,0

f

f-----

la,Inl Irz,Inl

[NCW [NCW

HI

Bytes per
Instruction

10,5

HI

HHI

B

10,5

6,5

DECW DECW

0.
0.

6,5

Opcode, First Operand, Second O~rand

Note: The blank areas dre not defmed.

Absolute Maximum Ratings
Voltages on all pins
with respect to GND ........ -0.3 V to+7.0 V
Operating Ambient
Temperature ...................... . O°C to + 70°C
Storage Temperature ....... - 6SoC to + ISO°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; operation of the device at any condition
above those indicated in the operational sections of these
specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Standard Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the
reference pin. Standard conditions are as
follows:

o
o
o

+5V

+5V

+4.7SV:$ Vee :$+S.2SV
GND=O V
O°C :$ TA :$ +70°C

+5V

+5V

18K

2.1K

1.Sk

1.Sk

t,,

' - - - - - - . - - XTAl1

Figure 13. Test Load 1

Figure 14. Test Load 2

c, ~

15pF MAX

Figure 15. External Clock Interface Circuit
(Both the clock and complement are required)

73

DC Characteristics
Symbol

Parameter

Min

Condition

Max

Unit

3.8

Vee

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

VeH

Clock Input High Voltage

VeL

Clock Input Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

VRH

Reset Input High Voltage

VRL

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

0.4

V

IOL= +2.0 rnA

IlL

Input Leakage

-10

10

p.A

IOL

Output Leakage

-10

10

p.A

o Vs
o Vs

IJR

Reset Input Current

-50

p.A

Vee = +5.25 V, VRL=O V

Icc

Vee Supply Current

120
80'

rnA

IMM

VMM Supply Current

10

rnA

Vee

V

Backup Supply Voltage
VMM
• This value is for Z8621L only

74

2.0

Vee

V

-0.3

0.8

V

3.8

Vee

V

-0.3

0.8

V

2.4

3

V

IOH= -250 p.A

VIN s

+5.25 V

VIN s

+5.25 V

Power Down Mode
Power Down

External 110 or Memory Read and Write Timing

No

Symbol

Paramter

Min

I
TdA(AS)
Address Valid to AS i Delay
AS i to Address Float Dealy
TdAS(A)
2
AS i to Read Data Required Valid
TdAS(DR)
3
TwAS
AS Low Width
4
TdAz(DS)
Address Float to DS !
5
6--TwDSR---DS (Read) Low Width
DS (Write) Low Width
7
TwDSW
DS ! to Read Data Required Valid
TdDSR(DR)
8
ThDR(DS)
Read Data to DS ! Hold Time
9
TdDS(A)
DS i to Address Active Delay
10
11
TdDS(AS)
DS i to AS ! Delay
12-TdR/W(AS)--RiW Valid to AS i Delay
TdDS(RIW)
13
DS i to RiW Not Valid
14
TdDW(DSW) Write Data Valid to DS (Write) ! Delay
TdDS(DW)
15
DS i to Write Data Not Valid Delay
TdA(DR)
16
Address Valid to Read Data Required Valid
TdAS(DS)
AS i to DS ! Delay
17

Z86211L
Max

50
70

Z8621A
Min

Max Notes*t
360

45
360

80
0
250
160

220
55
0
185
110
130

200
0
70
70
50
60
50
70

0
45
55
30
35
35
45
410

80

255
55

1,2,3
1,2,3
1,2,3,4
1,2,3
1
1,2,3,4
1,2,3,4
1,2,3,4
I
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3

NOTES:
I. Test Load I
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.

5. All timing reference use 2.0 V for a logic "1" and 0.8 V for a

4. When using extended memory timing add 2 TpC.

t

*

logic "0".
All units in nanoseconds (ns).
Timings are preliminary and subject to change.

RlW
PORT 0 ,

OM
16
PORT 1

As

I~-----~@~---------'I}---~-----

OS
(READ)

PORT 1

00-07 OUT

Ao-A1

OS
(WRITE)

Figure 16. External I/O or Memory Read/Write

75
~-~--~-----------~---~----~

~.~-

------

Additional Timing Table
No

Symbol

Paramter

Min

I
TpC
Input Clock Period
TrC, TIC
2
Clock Input Rise And Fall Times
Input Clock Width
3
TwC
4
TwTinL
Timer Input Low Width
5--TwTinH---Timer Input High Width
TpTin
6
Timer Input Period
7
TrTin, TfTin
Timer Input Rise And Fall Times
Interrupt Request Input Low Time
8a
TwIL
8b
TwIL
Interrupt Request Input Low Time
9
TwIH
Interrupt Request Input High Time

Z86211L
Max

125

1000
25

37
100
3TpC
STpC

Z8621A
Min
83

Max Notes*t
1000
15

26
70
3TpC
8TpC
100

100
3TpC
3TpC

I

100
70
3TpC
3TpC

NOTES:
1. Clock timing references uses 3.8 V for a logic "I" and 0.8 V
for a logic "0".

2. Timing reference uses 2.0 V for a logic "I" and 0.8 V for a

3. Interrupt request via Port 3 (P3]-P3 3 ).

4. Interrupt request via Port 3 (P30)'
*

t

logic "0".

Units in nanoseconds (ns).

Timings are preliminary and subject to change.

CLOCK

T,N

IRQN

Figure 17. Additional Timing

76

2
2
2
2
2,3
2,4
2,3

Handshake Timing
No

Paramter

Symbol

Min

TsDI(DAV)
Data In Setup Time
ThDI(DAV)
Data In Hold Time
2
Data Available Width
3
TwDAV
TdDAVIf(RDY)
DAV L Input to RDY L Delay
4
5-TdDAVOf(RDY)-DAV L Output to RDY L Delay
TdDAVIr(RDY)
DA V i Input to RDY i Delay
6
TdDAVOr(RDY)
DAV i Output to RDY i Delay
7
TdDO(DAV)
Data Out to DAV L Delay
8
Rdy L Input to DA V i Delay
TdRDY(DAV)
9

Z8621/L
Max

0
230
175

Z8621A
Min
0
160
120

175
0

120
0

175
0
50
0

Max Notes*t

200

120
0
30
0

1,2
1,3
1,2
1,3
I

140

NOTES:
I. Test Load I
2. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "I" and 0.8 V for a logic "0".
• Units in nanoseconds (ns).
t Timings are preliminary and subject to change.

DATA IN

DAY
(INPUT)

==--=--=-CD_~r:=~~:==TAIN::::aVALlD:s==:::::'[
'---_,_~==

RDY
(OUTPUT)

Figure 18a. Input Handshake

DATA OUT

x---

DATA OUT VAllO

-~----DAY
(OUTPUT)

RDY
(INPUT)

1~~0--~,
'
~

-----=:::=:2===J~

Figure 18b. Output Handshake

77

Clock-Cycle-Time-Dependent Characteristics
Number

Z8621A
Equation

TdA(AS)
TpC-75
TpC-50
TdAS(A)
TpC-55
TpC-40
TdAS(DR)
4TpC-IIO'
4TpC-140'
TpC-45
TpC-30
TwAS
TwDSR- - - - - - - - - - : 3 T p C - 1 2 5 ' - - - - - - 3TpC-65'--2TpC-55'
2TpC-90'
TwDSW
TdDSR(DR)
3TpC-175'
3TpC-120'
Td(DS)A
TpC-55
TpC-40
TdDS(AS)
TpC-55
TpC-30
TpC-55,---TdRIW(AS)- - - - - - - - - T p C - 7 5
TdDS(RIW)
TpC-65
TpC-50
TpC-75
TpC-50
TdDW(DSW)
TdDS(DW)
TpC-55
TpC-40
5TpC-215'
5TpC-160'
TdA(DR)
TdAS(DS)
TpC-45
TpC-30

I
2
3
4
6
7
8
10
II
12
13
14
15
16
17
*

Z8621/L
Equation

Symbol

Add 2TpC when using extended memory timing

Ordering Information
Type

Package

Temp.

Clock

Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

0/+70°C
-40/+85°C
01 +70°C
-40/+85°C
01 + 70°C
-40/+85°C
01 + 70°C
-40/+85°C

8 MHz

Z8621A BI
Z8621A B6
Z8621A DI
Z8621A D6
Z8621A CI
Z8621A C6
Z8621A KI
Z8621A K6

Plastic
Plastic
Ceramic
Ceramic
Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

01 + 70°C
-40/+85°C
01 +70°C
-40/+85°C
01 +70°C
-401 + 85°C
01 +70°C
-40/+85°C

12 MHz

Z8621L
Z8621L
Z8621L
Z8621L
Z8621L
Z8621L
Z8621L
Z8621L

Plastic
Plastic
Ceramic

01 + 70°C
-40/+85°C
01 + 70°C
-40/+85°C
01 +70°C
-40/+85°C
01 + 70°C
-40/+85°C

Z8621
Z8621
Z862 1
Z862 I
Z8621
Z862 1
Z862 1
Z862 1

78

BI
B6
Dl
D6
CI
C6
Kl
K6

BI
B6
Dl
D6
CI
C6
KI
K6

Plastic
Plastic
Ceramic
Ceramic

Ceramic

Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

Description
8K ROM Microcomputer

8K ROM Microcomputer
Low Power version

8 MHz

lB.
Z8 BASIC/Debug Interpreter
• The 28671 MCU is a complete
microcomputer preprogrammed with a
BASIC/Debug interpreter. Interaction
between the interpreter and its user is
provided through an on-board UART.
• BASIC/Debug can directly address the
28671's internal registers and all external
memory. It provides quick examination
and modification of any external memory
location or I/O port.

• The BASIC/Debug interpreter can call
machine language subroutines to increase
execution speed.
• The 28671's auto start-up capability allows
a program to be executed on power-up or
Reset without operator intervention.
•

Single + 5 V power supply - all I/O pins
TTL-compatible.

• Available in 8 MHz version.

General Description
The 28671 Single-Chip Microcomputer
(MCU) is one of a line of preprogrammed
chips - in this case with a BASIC/Debug
interpreter in ROM-offered by SGS. As a
member of the 28 Family of microcomputers,
it offers the same abundance of resources as
the other 28 microcomputers.
Because the BASIC/Debug interpreter is
already part of the chip circuit,
programming is made much easier. The
28671 MCU thus offers a combination of
software and hardware that is ideal for many
industrial applications. The 28671 MCU
allows fast hardware tests and bit-by-bit
examination and modification of memory
location, I/O ports, or registers. It also
allows bit manipulation and logical
operations. A self-contained line editor
supports interactive debugging, further
speeding up program development.
The BASIC/Debug interpreter, a subset of
Dartmouth BASIC, operates with three kinds
of memory: on-chip registers and external
ROM or RAM. The BASIC/Debug interpreter
is located in the 2K bytes of on-chip ROM.
Aditional features of the 28671 MCU
include the ability to call machine language
subrotines to increase execution speed and
the ability to have a program execute on
power-up or Reset, without operator
intervention.
Maximum memory addressing capabilities
include 62K bytes of external PNqrcHn

memory and 62K bytes of data memory with
program storage beginning at location 800
hex. This provides up to 124K bytes of
useable memory space. Very few 8-bit
microcomputers can directly access this
amount of memory.
Each 28671 Microcomputer has 32 I/O
lines, a 144-byte register file, an on-board
UART, and two counter/timers.

TIMING
AND
CONTROL

(-

RESET

Riw

GND

os

XTAL1

AS

VMM/XTAL2

PO,

P20

PO,

P2,

PO,

P2,

(NIBBLE

P03

P23

PROGRAMMABLE)
1/0 or As-A15

PO,

P2,

PORT 0

PO,

PORT 1,
110 or ADO-AD?

Z8671

I

PORT 2
(BIT PRO·
GRAMMABLE)

110

P2,

PO,

P20

P07

P27

Pl,

Pa"

Pl,

P3,

Pl,

po,

P1 3

P33

Pl,

P3,

Pl,

pas

Pl,

P3,

P1 7

P37

PORT 3
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL 110
AND CONTROL

Figure I. Logic Function

79

General Description (Continued)
N

Vee

g

P3,

VMM/XTAL2

P3,

XTAL1

P2,

P3,

P2,

P3,

P2,

I1ESET

P2,

A/W

P2,

os

P2,

As

P',

:::E u

U)

t--

.-

~

N

,

e

40

NC

RESET
R/W

38

P24

DS

"
"

P22

AS

P35

P3,

P',

GND

P3,

GND

P3,

P3,

po,
po,
po,
po,
po,
po,

P1,

P32
PO o

P0 6

P1,

po,

P10

Z8G71

P1,

P2,

34

P20
P33
P3 4

"

A07

"

PO,

P1,

NC

P1,

18

P1,

P23

35

PO,

19

20 21

2'Z 23 24 25

26 27

A06
AD5

28

P1,

Figure 2a. Pin Configuration

OUTPUT

Figure 2b. Chip Carrier Pin Configuration

Vee

GND

XTAl

AS

! !

110
(BIT PROGRAMMABLE)

ADDRESS OR 110
(NIBBLE PROGRAMMABLE)

Figure 3. Functional Block Diagram

80

W

~~~~~~ "-

ADORESSIDATA OR 1/0
(BYTE PROGRAMMABLE)

Architecture
Z8671 architecture is characterized by a
flexible I/O scheme, and efficient register
and address space structure, and a number
of anCillary features that are helpful in many
applications.
Microcomputer applications demand
powerful I/O capabilities. The Z8671 fulfills
this with 32 pins dedicated to input and
output. These lines are grouped into four
ports of eight lines each and are
configurable under software control to
provide timing, status signals, serial or
parallel I/O with or without handshake, and
an address/data bus for interfacing external
memory.
Because the multiplexed address/data bus
is merged with the I/O-oriented ports, the
Z8671 can assume many different memory
and I/O configurations. These configurations
range from a self-contained microcomputer

to a microprocessor that can address 124K
bytes of external memory.
Three basic address spaces are available to
support this wide range of configurations:
program memory (internal and external),
data memory (external) and the register file
(internal). The 144-byte random-access
register file is composed of 124 generalpurpose registers, four I/O port registers,
and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.

Pin Description
AS Address Strobe (output, active Low).
Address Strobe is pulsed once at the
beginning of each machine cycle.
Addressess output via Port 1 for all external
program or data memory transfers are valid
at the trailing edge of AS. Under program
control, AS can be placed in the highimpedance state along with Ports 0 and 1,
Data Strobe and Read/Write.

P2o-P2,. 1/0 Port Lines (input/output, TTL
compatible). 8 lines Bit Programmable. In
addition they can be configured to provide
open-drain outputs.

DS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

RESET. Reset (input, active Low). RESET

P30-P34. Input Port Lines (TTL compatible).
They can also configured as control lines.
P3s-P3,. Output Port Lines (TTL compatible).
They can also configured as control lines.
inizializes the Z8671. When RESET is
deactivated, program execution begins from
internal program location OOOCH.

poo-po,. 1/0 Port Lines (input/output, TTL
compatible). 8 lines Nibble Programmable
that can be configured under program
control for I/O or external memory interface.

R/W. Read/Write (output). R/W is Low when

Plo-PI,. 1/0 Port Lines (input/output, TTL
compatible). 8 lines Byte Programmable that
can be configured under program control for
I/O or multiplexed address (Ao-A7) and data
(Do-D7) lines used to interface with
program/data memory.

XTALI. XTAL2. Crystal L Crystal 2 (timebase input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz
maximum) or an external single - phase
clock (8 or 12 MHz maximum) to the on-chip
clock oscillator and buffer.

the Z8671 is writing to external program or
data memory.

81

Address Spaces
Program Memory. The Z8671's 16-bit
program counter can address 64K bytes of
program memory space. Program memory
consists of 2K bytes of internal ROM and up
to 62K bytes of external ROM, EPROM, or
RAM. The first 12 bytes of program memory
are reserved for interrupt vectors (Figure 4).
These locations contain six 16-bit vectors that
correspond to the six available interrupts.
The BASIC/Debug interpreter is located in
the 2K bytes of intenal ROM. The interpreter
begins at address 12 and extends to 2047.
Data Memory. The Z8671 can address up to
62K bytes of external data memory
beginning at location 2048 (Figure 5).
External data memory may be included with,
or separated from, the external program
memory space. DM, an optional I/O function
that can be programmed to appear on pin
P34, is used to distinguish data and program
memory space.

file includes four I/O port registers (RO-R3),
124 general-purpose registers (R4-R127), and
16 control and status registers (Figure 6).

65535 , . . . . - - - - - - - - - - ,

EXTERNAL
DATA
MEMORY

~!~~------------------~
NOT ADDRESSABLE

Register File. The 144-byte register file may
be accessed by BASIC programs as memory
locations 0-127 and 240-255. The register
Figure 5. Data Memory Map

5535

EXTERNAL
ROM OR RAM

LOCATION

2048
2047

Localion 01
lirstbyl&ol
Instruction

e:teculed
al1erreset

Interrupt
Vector
(Lower Byte)

Interrupt
Vector
(Upper Byte)

ON-CHIP
ROM

;;- t------------

}M."

DEBUG

STACK POINTER (BITS 7-0)

SPL

STACK POINTER (BITS 15-8)

SPH

253

REGISTER POINTER

252

PROGRAM CONTROL FlAGS

251

RP
FLAGS

INTERRUPT MASK REGISTER

IMR

250

INTERRUPT REQUEST REGISTER

IRQ

INTERRUPT PRIORITY REGISTER

IPR

11

IROS

249

10

IROS

248

PORTS 0-1 MODE

9

IRQ4

247

PORT 3 MODE

P3M

8

IRQ4

246

PORT 2 MODE

P2M

7

IR03

245

TO PRESCAl.ER

6

IR03

5r--

IRQ2

4f1':

IR02

3

IRQ1

2

IRQ1

1

IROO

0

IROO

Figure 4. Programm Memory Map

82

IDeNTIFIERS

255
254

P01M

PREO

TO

244

TIMER/COUNTER 0

243

T1 PRESCALER

242

TlMERfCOUNTER 1

241

TIMER MODE

TMR

240

SERIAL 110

510

PRE1

T1

NOT
IMPLEMENTED

Figure 6. Control and Status Registers

Address Spaces (Continued)
The BASIC/Debug Interpreter uses many
of the general-purpose registers as pointers,
scratch workspace, and internal variables.
Consequently, these registers cannot be used
by a machine language subroutine or other
user programs. On power-up/Reset,
BASIC/Debug searches for external RAM
memory and checks for an auto start-up
program. In a non-destructive method,
memory is tested at relative location
xxFD(hex). When BASIC/Debug discovers
RAM in the system, it initializes the pointer
registers to mark the boundaries between

127

127
EXPRESSION
EVALUATION
STACK

64
63

104
103
86
8S
64
63

COUNTER

32

FREE, AVAILABLE
FOR USR ROUTINES

32

COUNTER
USED INTERNALLY

USED INTERNALLY

31

SCRATCH

30

POINTER TO
CONSTANT BLOCK

29

USED INTERNALLY

24
23

22
21
20

,.

18
17

16
lS
14
13
12
11

10

•

SHARED BY GOSUB
AND VARIABLES

33

31

28
27

GOSUB
STACK

34

30

2.

SHARED BY EXPRESSION
STACK AND LINE BUFFER

VARIABLES
FREF

34
33

areas of memory that are assigned specific
uses. The top page of RAM is allocated for
the line buffer, variable storage, and the
GOSUB stack. Figure 7a illustrates the
contents of the general-purpose registers in
the Z8671 system with external RAM. When
BASIC/Debug tests memory and finds no
RAM, it uses an internal stack and shares
register space with the input line buffer and
variables. Figure 7b illustrates the contents
of the general-purpose registers in the Z8671
system without external RAM.

LINE NUMBER
ARGUMENT FOR
SUBROUTINE
ARGUMENT/ROUTINE FOR
SUBROUTINE CALL

28
27

SCRATCH
POINTER TO
CONSTANT BLOCK
USED INTERNALLY

24
23
22
21

,.

20

18
17

SCRATCH

LINE NUMBER
ARGUMENT FOR
SUBROUTINE CALL
ARGUMENTJRESULT FOR
SUBROUTINE CALL
SCRATCH

16
POINTER TO INPUT
LINE BUFFER
POINTER TO END OF
LINE BUFFER
POINTER TO STACK
BOTTOM
ADDRESS OF USER
PROGRAM
POINTER TO GOSUB
STACK

lS
14
13
12
11

POINTER TO NEXT
CHARACTER
POINTER TO LINE
BUFFER
POINTER TO GOSUB

10

•

POINTER TO BASIC
PROGRAM
POINTER TO GOSUB

POINTER TO END
OF PROGRAM

FREE

110 PORTS

110 PORTS

Figure 7a. General-Purpose Registers
with External RAM

Figure 7b. General-Purpose Registers
without External RAM

83

Address Spaces (Continued)
Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which
, can reside anywhere in data memory
between location 2048 and 65535. An 8-bit
Stack Pointer (R255) is used for the internal
stack that resides within the 124 generalpurpose registers (R4-R127).
Register Addressing. Z8671 instructions can
access registers directly or indirectly with an
8-bit address field. The Z8671 also allows
short 4-bit register addressing using the
Register Pointer (one of the control
registers). In the 4-bit mode, the register file
is divided into nine working-register groups,
each group consisting of 16 continguous
registers (Figure 8). The Register Pointer
addresses the starting location of the active
working-register group.

i-rr:=:l::::::;:=:;::=;:;:;::;::::::J
... r
- 1

255

253

~'--------I
L.._ _ _ _ _ _ _ _.....I240

The upper nibble of the register file address
provided by the register pointer specilles
the active working-register group.

-

-

-

..

12

...

.. 1

I

The lower

SPECIFIED WORKING·
REGISTER GROUP

...

nibble 01

the register
lIIe address
provided by
the Instruction
points to the
specified

register.

1
1

----'JOPORTS-----

3

0

Figure 8. The Register Pointer

. Program Execution
Automatic Start-up. The Z8671 has an
automatic start-up capability which allows a
program stored in ROM to be executed
without operator intervention. Automatic
execution occurs on power-on or Reset when
the program is stored at address 1020 (hex).
Execution Modes. The Z8671's BASIC/Debug
Interpreter operates in two execution modes:
Run and Immediate. Programs are edited

84

and interactively debugged in the Immediate
mode. Some BASIC/Debug commands are
used almost exclusively in this mode. The
Run mode is entered from the Immediate
mode by entering the command RUN. If
there is a program in RAM, it is executed.
The system returns to the Immediate mode
when program execution is complete or
interrupted by an error.

Interactive Debugging
Interactive debugging is accomplished
with the self-contained line editor which
operates in the Immediate mode. In addition
to changing program lines, the editor can
correct an immediate command before it is
executed. It also allows the correction of
typing and other errors as a program is
entered.
BASIC/Debug allows interruptions and
changes during a program run to correct

errors and add new instructions without
disturbing the sequential execution of the
program. A program run is interrupted with
the use of the escape key. The run is
restarted with a GOTO command (followed
by the appropriate line number) after the
desired changes are entered. The same
procedure is used to enter corrections after
BASIC/Debug returns an error.

Commands
BASIC/Debug recognizes 15 command
keywords. For detailed instructions of
command usage, refer to the BASIC/Debug
software manual.
GO
The GO command unconditionally
branches to a machine language
subrotine. This statement is similar
to the USR function except that no
value is returned by the assembly
language routine.
GOSUB GOSUB unconditionally branches
to a subroutine at a line number
specified by the user.
GOTO
GOTO unconditionally changes
the sequence of program
execution (branches to a line
number).
IF/THEN This commands is used for
conditional operations and
branches.
INPUT/IN These commands request
information from the user with the
prompt "?", then read the input
values (which must be separated
by commas) from the keyboard,
and store them in the indicated
variables.
INPUT discards any values
remaining in the buffer from
previous IN, INPUT, or RUN
statements, and requests new data

LET

LIST

NEW

PRINT

REM

RETURN

RUN

STOP

from the operator. IN uses any
val ues left in the buffer first, then
requests new data.
LET assigns the value of an
expression to a variable or
memory location.
This command is used in the
interactive mode to generate a
listing of program lines stored in
memory on the terminal device.
The NEW command resets pointer
R 10-11 to the beginning of user
memory, thereby marking the
space as empty and ready to store
a new program.
PRINT lists its arguments, which
may be text messages or
numerical values, on the output
terminal.
This command is used to insert
explanatory messages into the
program.
This command returns control to
the line following a GOSUB
statement.
RUN initiates sequential execution
of all instructions in the current
program.
STOP ends program execution
and clears the GOSUB stack.

85

· Functions
BASIC/Debug supports two functions:
AND and USR.
The AND function performs a logical AND.
It can be used to mask, tUrn off, or isolate
bits. This function is used in the following
format:
AND (expression, expression)
The two expressions are evaluated, and
their bit patterns are ANDed together. If only
one value is included in the parentheses, it
is ANDed with itself. A logical OR can also
be performed by complementing the AND
function. This is accomplished by subtracting
each expression from -I. For example, the
function below is equivalent to the OR of A
and B.
-I-AND(-I-A, -I-B)

The USR function calls a machine
language subroutine and returns a value.
This is useful for applications in wich a
subroutine can be performed more quickly
and efficiently in machine language than in
BASIClDebug.
The address of the first instruction of the
subroutine is the first argument of the USR
function. The address can be followed by
one or two values to be processed by the
subroutine. In the following example,
BASIC/Debug executes the subroutine
located at address 2000 using values literal
256 and variable C.
USR(%2000,256,C)
The resulting value is stored in Registers
18-19.

Serial Input/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for full, duplex serial asynchronous
'. receiver/transmitter operation. The bit rate is
controlled by Counter/Timer 0, with a
maximum rate of 62.5K bit/second for 8MHz,
and a maximum rate of 94.8K bit/second for
12MHz parts.
The Z8671 automatically adds a start bit
, and two stop bits to transmitted data
(Figure 9). Odd parity is also available as an

option. Eight data bits are always
transmitted, regardless of parity selection. If
parity is enabled, the eighth data bit is used
as the odd parity bit. An interrupt request
(IRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight
data bits, and at least one stop bit. If parity
is on, bit 7 of the received data is replaced
by a parity error flag. Received characters
generate the IRQ3 interrupt request.

Transmitted Data
(No Parity)

Received Data
(No Parity)

Isplspl~I~I~I~I~I~I~I~ls~

T

LSTART BIT
' - - - - - - E I G H T DATA BITS
TWO STOP BITS

Transmitted Data
(With Parity)

Received Data
(With Parity)

I~I~I pJ~I~I~I~I~I~I~ls~

1~lpl~I~I~I~I~I~I~I~1

T. .I,

ODD PARITY
TWO STOP BITS

' - - - - - - - - - - - O N E STOP BIT

'-------SEVEN DATA SITS

Figure 9. Serial Data Formats

86

L

I

_ - , - - - L S T A R T lilT

-,--,----LSTART BIT
'-------SEVEN DATil BITS
PARITY ERROR FLAG

1/0 Ports
The Z8671 has 32 lines dedicated to input
and output. These lines are grouped into
four ports of eight lines each and are
configurable as input, output or
address/data. Under software control, the
ports can be programmed to provide address
outputs, timing, status signals, serial I/O,
and parallel I/O with or without handshake.
All ports have active pull-ups and pulldowns compatible with TTL loads.
Port 1 can be programmed as a byte I/O
port or as an address/data port for
interfacing external memory. When used as
an I/O port, Port 1 may be placed under
handshake control. In this configuration,
Port 3 lines P33 and P34 are used as the
handshake controls RDY 1 and DAV 1 (Ready
and Data Available).
Memory locations greater than 2048 are
referenced through Port 1. To interface
external memory, Port 1 must be
programmed for the multiplexed
AddresslData mode. If more than 256
external locations are required, Port must
output the additional lines.
Port 1 can be placed in the highimpedance state along with Port 0, AS, DS
and R/W, allowing the Z8671 to share
common resources in multiprocessor and
DMA applications. Data transfers can be
controlled by assigning P33 as a Bus
Acknowledge input and P34 as a Bus
Request output.

°

PORT 1
(110 OR ADo-AD7)

HANDSHAKE CONTROLS
) DAV, AND RDY1
(pO, AND P3~

Figure lOa. Pori 1

Port 0 can be programmed as a nibble I/O
, port, or as an address port for interfacing
external memory. When used as an I/O port,
Port may be placed under handshake
control. In this configuration, Port 3 lines

°

P32 and P3s are used as the handshake
controls DAV 0 and RDYo. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0
can provide address bits As-All (lower
nibble) or As-A15 (lower and upper nibble)
depending on the required address space. If
the address range requires 12 bits or less,
the upper nibble of Port 0 can be
programmed independently as I/O while the
lower nibble is used for addressing. When
Port 0 nibbles as defined as address bits,
they can be set to the high-impedance state
along with Port 1 and the control signals AS,
DS and R/W.

I

PORT 0
(110 OR As-A ,s)

_

) tlM!PSHAKE CONTROLS

DAVo AND RDYo
(P3 2 AND P3S>

Figure lOb. Port 0

Port 2 bits can be programmed
independently as input or output. The port is
always available for I/O operations. In
addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this
configuration, Port 3 lines P31 and P36 are
used as the handshake controls lines DA V2
and RDY 2 . The handshake signal assignment
for Port 3 lines P31 and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

-

PORT 2(110)

HAN DSHAKE CONTROLS
) DAV2 AND ADY2

(P3, AN 0 P3s)

Figure lOco Port 2

87

I/O Ports (Continued)
Port 3 lines can be configured as I/O or
control lines. In either case, the direction of
the eight lines is fixed as four input (P30-P33)
and four output (P34-P37). For serial I/O,
lines P30 and P37 are programmed as serial
in and serial out respectively.
Port 3 can also provide the following
control functions: handshake for Port 0,
and 2 (DAV and RDY); four external
interrupt request signals (IRQO-IRQ3); timer
input and output signals (TIN and TOUT) and
Data Memory Select (DM).

PORT 3
(110 OR CONTROL)

Figure IOd. Pori 3

Counter /Timers
The Z8671 contains two 8-bit
programmable counter/timers (To and T I ),
each driven by its own 6-bit programmable
prescaler. The TI prescalers can be driven
by internal or external clock sources;
however, the To prescaler is driven by the
nternal clock only.
The 6-bit prescalers can divide the input
. frequency of the clock source by any number
from 1 to 64. Each prescaler drives its
counter, which decrements the value (l to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request - IRQ4 (To) or IRQ5
(TI) - is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be
programmed to stop upon reaching zero
(single-pass mode) or to automatically reload

88

the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the prescalers, can be read any time
without disturbing their value or count
mode.
The clock source for TI is user-definable;
it can be either the internal microprocessor
clock (4 MHz maximum for the 8 MHz device
and 6 MHz maximum for the 12 MHz device)
divided by four, or an external signal input
via Port 3. The Timer Mode register
configures the external timer input as an
external clock, a trigger input that can be
retriggerable or non-retriggerable, or as a
gate input for the internal clock. The
counter/timers can be programmably
cascaded by connecting the To output to the
input of T 1. Port 3 line P36 also serves as a
timer output (TOUT) through which To, TI or
the internal can be output.

Interrupts
The Z8671 allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or individually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z8671 interrupts are vectored;
however, the internal UART operates in a
polling fashion. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

The BASIC/Debug Interpreter does not
process interrupts. Interrupts are vectored
through locations in internal ROM which
point to addresses 1000-1011 (hex). To
process interrupts, jump instructions can be
entered to the interrupt handling routines at
the appropriate addresses as shown in Table I.
Address
(hex)

Contains Jump Instruction and
Sobroutine Address for:

1000-1002
1003-1005
1006-1008
1009-100B
100C-100E
100F-lOll

IRQo
IRQ)
IRQ 2
IRQ3
IRQ 4
IRQ5

Table!. Interrupt Jump instruction

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended

capacitance (CL:::; 15 pF maximum) from
each pin to ground. The specifications for
the crystal are as follows:
• AT cut, parallel resonant
• Fundamental type, 8 MHz maximum
• Series resistance, Rs :5 100 n

89

Instruction Set Notation
Addressing Modes. The following notation is used
to describe the a<;idressing modes and instruction
operations as shown in the instruction summary.
IRR
Indirect register pair or indirect workingregister pair address
Irr
Indirect working-register pair only
X
Indexed address
DA
Direct address
RA
Relative address
1M
Immediate
R
Register or working-register address
r
Working-register address only
IR
Indirect-register or indirect workingregister address
Ir
Indirect working-register address only
RR
Register pair or working register pair address
Symbols. The following symbols are used in
describing the instruction set.
dst
Destination location or contents
src
Source location or contents
cc
Condition code (see list)
@
Indirect address prefix
. SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)

IMR

Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol
" ..... ". For example,
dst ..... dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For
example,
dst (7)
refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the
follOWing six arithmetical falgs plus two user
selectable flags:
C
Carry falg
Z
Zero flag
Ic Iz Is IV ID IH 1F2IF
S
Sign flag
V
Overflow flag
]
D
Decimal-adjust flag
~~ user flags
H
Half-carry flag

If

o

Affected flags are indicated by:

I

*
X

Cia red to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

Conditions Codes
Value
1000
01 JI
III I
0110
1110
JlOI
0101
0100
1100
0110
1110
1001
0001
1010
0010
JIJI
0111
1011
0011
0000

90

Mnemonic

Meaning

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set
C = I
C = 0
I
Z
Z
0
S
0
S
I
V = I
V = 0
Z = I
Z = 0
(S XOR V) = 0
(S XOR V) = I
[Z OR (S XOR V)]
0
[Z OR (S XOR V)]
C = 0
C = I
(C = 0 AND Z
0)
(C OR Z) = I

Instruction Formats

CCF, 01, EI, IRET, NOP,

OPC

ReF, RET, SCF

ds'

INC r

OPC

One-Byte Instructions
ope

MODE

dsl/src

CLR, CPL, OA, DEC,
OR [1 1 1

01 dst/src I

I
f-------'e;,d,-",'----l OR 11 1 101
OPC

OPC

MODE

g~~~·~~~Rt~~~R,POP.
ds'

RRC, SRA, SWAP

1 1 1 0
1 1 1 0

ds'

OR

11 1101

ds.

JP, CALL (Indirect)

dst

OPC

MODE

ds.
OPC

Ace, ADO, AND, CP,

LO, OR, soc, SUB.
reM, TM, XOR

OR
OR

ADC, ADD, AND, CPt
lO, OR,

SRP

sac, SUB,

TeM, TM, XOR

VALUE

VALUE
MODE

ope

ADC, ADD, AND,
CP, OR, sac, SUB,

MODE

ds'

MODE

ope
src/dsl

dst/src

ope

src/dst

ds'

lope

LO, LOE, LOEI,
LOC, lOCI

MODE
dst/src

1 1 1 0
1 1 1 0

ds.

dst/CCR~

ope

OPC

LD

ADDRESS

OR

11

1 1

01

LD

OPC

JP

OA,
OA,
LO

VALUE

I

La
OR
OR

TeM, TM, XOR

dst/src

dst

OPC

OPC
DA,
DA,

DJNZ, JR

Two-Byte instruction

CALL

Three-Byte instruction
Figure 11. Instruction Formats

91

Instruction Summary
Instruction
and Operation
ADC dst,sre

AddrMode
dBt

src

(Note 1)

Opcode Flags Affected
Byte
(Hex~ CZSVDH

·

10

dst - dst + sre + C
ADD dst,sre
dst - dst + sre

(Note 1)

AND dst,sre
dst - dst AND sre

(Note 1)

CALL dst

00
50

OA
IRR
SP - SP - 2
@SP - PC; PC - dst

D6
04

cel'

EF

C - NOT C

-

.

• 0 •
• 0 •

• 0

dst - NOT dst

R
IR

60
61

o- -

CP dst,sre

(Note 1)

dst - DA dst
DEC dst

dst-dst-l

PC - dst

IRR

30

RA

eB

------

rC
r8
r9

------

DECW dst

ds!-dst-l

LDC dst,sre
dst - sra

* * - -

LDCI dst, sre

40
41

R
IR

00
01

-

RR
IR

80
81

-***--

DI

RA

r - r- 1
if r
0
PC-PC+dst
Range: + 127, -128

*

8F

------

rA

------

r~O-F

9F

IMR (7) - 1
rE
r~O-F

dst-dst+l
R
IR

IRET

RR
IR

20
21

AD
Al
BF

FLAGS - @ SP; SP - SP + 1
PC-@SP; SP-SP+2; IMR(7) -1

92

X
r
Ir
r
R
IR
1m
1m
R

C7
07
E3
F3
E4
E5
E6
E7
F5
C2
02

------

Ir
Irr
dst - sre
r - r + 1; rr - rr + 1

Irr
Ir

C3
03

------

LDE dst,sre

r
Irr

Irr

82
92

------

Ir
Irr
dst - sre
r - r + 1; rr - rr + 1

Irr
Ir

83
93

------

LDEI dst,sre

FF

NOP

• 0 - -

(Note 1)

40

R
IR

50
51

------

70
71

------

CF

o- - - - -

AF

------

90
91

* * - -

dst - dst OR sre

INC dst

dst - dst +

r

X

Irr

OR dst,src

EI

INCW ds!

1m
R

r
Irr

dst - sre

DJNZ r,dst

------

e~O-F

r
r
R

r
Ir
R
R
R
IR
IR

.. X - -

R
IR

IMR (7) - 0

cD

c~O-F

r~O-F

AD

.

Opcode Flags Affected
Byte
(Hex)
CZSVDH

JR ee,dst
if cc is true,

dst - sre
DA dst

src

DA

. ----------

dst - 0

dBt

JP ee,dst
if cc is t~ue

LD dst,sre
dst - sre

BO
Bl

COM dst

Addr Mode

PC-PC+dst
Range: + 127, -128

R
IR

CLR dst

Instruction
and Operation

------

···
···
.·· · ..
-

-

- -

-

-

POP dst

dst - @SP
SP - SP + 1
PUSH src

SP - SP - 1; @SP- src
RCF

R
IR

C - 0
RET

PC - @SP; SP - SP + 2
RL ds!

CJJ:6J I~

..

Instruction Summary (Continued)
Instruction
and Operation

Addr Mode
dst

src

Opcode Flags AUected
Byte
(Hex)
CZSVDH

Instruction
and Operation

Addr Mode
dBt

Irc

Opcode Flags AUected
Byte
(Hex)
CZSVDH

RLC dst

~~

10
II

SRP src
RP - src

RR dst

~ 4!:::3J I~

EO
EI

SUB dst,src
dst - dst - src

RRC dst

Lfi"l=E3J
R
, , • IR

CO
CI

SWAPdst~ R
IR

FO
FI

X * * X - -

SBC dst,src
dst - dst- src - C

(Note I)

SCF
C-I
SRA dst

L[iJ@I~

1m
(Note I)

31

20

* I *

3D

* * * * 1 *

TCM dst,src
(NOT dst) AND src

(Note 1)

60

- * *0

DF

I - - -

TM dst, src
dst AND src

(Note I)

70

- * * 0

DO
DI

* * * 0

XOR dst,src
dst - dst XOR src

(Note I)

BO

-**0--

Addr Mode
dst

src

Note I
These instructions have an identical set ot addressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, the opcode of an ADC instruction using
the addressing modes r (destination) and Ir (source) is 13.

Ir

R
R
R
IR

Lower
Opcode Nibble

I1l
III

R
IR

[!]

1M
1M

@l

lID
[2J

93

Registers
R240 SIO
Serial 1/0 Register
(FOH; ReadlWrile)

R244 TO
CounterITimer 0 Register
(F4H; ReadlWrite)

I~I~I~I.I~I~I~I~I
LI_ _ _ _

SERIALDATA(Do '" LSB)

TO INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)

R245 PREO
Prescaler 0 Register
(F5H; Write Only)

R241 TMR
Timer Mode Register
(FlH; ReadlWrite)

NOT T,",
useD'"
MODES
00

: ~~
INTERNAL CLOCK OUT = 11
~o g~~

j

~

I~I~I~I~I~I~I~I~I

'llS~o

1 =
'" NO
LOAD
FUNCTiON
To

0

=

DISABLE To COUNT

1

::I:

ENABLE To COUNT

~L

(NON'R~;~~g~:~~:~~) =

PRESCALER MODULO
(RANGE: 1·64 DECIMAL
01·00 HEX)

1 = ENABLE 1, COUNT

10
TRIGGER INPUT", 11

= To MODULO·N

1

RESERVED (MUST BE 0)

0 = NO FUNCTION
1 = LOAD T,
0 :::: DISABLE T, COUNT

T MODES
EXTERNAL CLOCK IN~OT = 00
GATE INPUT = 01

COUNTMODE
o .. To SINGLE·PASS

(RETRIGGERABLE)

R242 Tl
Counter Timer 1 Register
(F2H; ReadlWrite)

R246 P2M
Port 2 Mode Register
(F6H; Write Only)
I~I~I~I~I~I~I~I~I
P20-P27 1/0 DEFINITION

T, INITIAL VALUE (WHEN WRITTEN)

' - - - - - 0 DEFINES BIT AS OUTPUT

'-----(RANGE 1 256 DECIMAL 01 00 HEX)

1 DEFINES BIT AS INPUT

T, CURRENT VALUE (WHEN READ)

R247 P3M
Port 3 Mode Register
(F7H; Write Only)

R243 PREl
Prescaler 1 Register
(F3H; Write Only)

E.

I~I~I~I.I~I~I~I~I

~L

COUNTMODE
o : : 1, SINGLE·PASS

~o

RESERVED (MUST BE 0)

CLOCK SOURCE:
1

o

PORT' PULL·UPSOPEN.DRAIN

1 PORT 2 PULL·UPS ACTIVF

1 :::: 1, MODULO·N

o P32 :::

T 1 INTERNAL

INPUT

IJ 0

P33 "" INPUT

~~}

PRESCALER MODULO
(RANGE: 1-64 DEOIMAl
01-00 HEX)

11
L -_ _ _ _ _ _ ~
L -_ _ _ _ _ _ _

~

=

Figure 12. Control Registers

P34

P33
INPUT
P34
P33 = DAVl/RDY1 P3.t

= OUTPUT
= OM
= RDY1/DAV1

~:~ ~ ~:.:fol~ :~: ~~~~~OUT)

=:

~ ~~lL IN ~ ~ ~~~~ULTOUT

L -_ _ _ _ _ _ _ _ ~ ~:=:~ g~F

94

P35 ::: OUTPUT

1 P3a::: ti'AVOIRDYO P3& "" HOYOIom

T1 EXTERNAL TIMING INPUT
(TIN) MODe

Registers (Continued)
R248 POIM
Port 0 and I Mode Register
(F8 H ; Write Only)

R252 FLAGS
Flag Register
(FCH; Reacl/Write)

I~I~I~I~I~I~I~I~I

MODE~

PO._PO,
OUTPUT", 00
INPUT::: 01
A,'2-A!5"" lX

EXTERNAL MEMORY TIMING
NORMAL::: 0
EXTENDED::: 1

~

-----r
L poo-po,

I

~~~

MODE
00", OUTPUT
01 ::: INPUT
lX == As-A"

LUSERFLAGFl

LUSER FLAG F2

STACK SELECTION
EXTERNAL
1 = INTERNAL

o :::

FLAG

SIGN FLAG

Pl 0-P1 7 MODe
00 ::: BYTE OUTPUT
01 ::: Byre INPUT
10 '" ADo-ADI
11 -= HIGH·IMPEDANCE ADo-AD7,

AS. OS, R/W, As-A",

HALF CARRY FLAG

~~~~:~~:D:~:~
ZERO FLAG
CARRY FLAG

A,~ -Al~

IF SELECTED

R253 RP
Register Pointer
(FD H ; Reacl/Write)

R2491PR
Interrupt Priority Register
(F9H; Write Only)
I~I~I~I~I~I~I~I~I

."'•• ,~".,,~ I I III ,.'"""..~"".."

L:

RESERVED ::: 000

C > A > B ::: 001
A > B > C = 010
A> C _ B::: all

IRQ3, IROS PRIORITY (GROUP A)
o ::: IROS > IRQ3
1 ::: IRQ3 > IRQS

OON 'T CARE

REGISTER
POINTER

cB >> CB >> AA :::= 100
101

IRQO, IAQ2 PRIORITY (GROUP B)

o :::

IRQ2 > IROO
1 ::: IROO > IRQ2

B > A > C ::: 110
RESERVED::: 111

IRQ1, IRQ4 PRIORITY (GROUP C)
o = IRa1 > IRa4
1 = IRQ4 > IRQ1

R250 IRQ
Interrupt Request Register
(FAH; Read/Write)

R254 SHP
Stack Pointer
(FEH; Read/Write)

I~I~I~I~I~I~I~I~I
RESERVEO (MUST BE 0)

T

c=

IRao
IR01
IR02
IR03
IR04
IR05

p~

=
INPUT (Do '" IRaO)
= P33 INPUT
::
::
::
::

P31 INPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
T1

R2511MR
Interrupt Mask Register
(FB H ; Reacl/Write)

c==
___

____
JIL_

R255 SPL
Stack Pointer
(FF H; Read/Write)
I~I~I~I~I~I~I~I~I

1 ENABLES IROO-IR05
(On = IROO)
RESERVED (MUST BE 0)

L - - - - -___ 1 ENABLES INTERRUPTS

Figure 12. Control Registers (Continued)

95

Lower Nibble (Hex)

Opcode Map

C

A

D

E

F

-_.6,5

DEC
HI

6,5

6,5

RLC

is

...
:9

z
~
0-

A

B

C

D

E

F

Byt•• per

Instruction

10,5

10,5

6,5

LD

LD

IRa,Rl

RdM

D/NZ

R~,RI

IRt/IM

11, R2

la, HI

II,RA

6,5

6,5

10,5

10,5

10,5

10,5

IHI

It,Ira

11,12

10,5

R.~,

HI

IRl,Hi

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

SUB

SUB

SUB

SUB

SUB

11,12

II,

Ira

R2,Rl

8,0

6,1

6,5

6,5

1O,S

IRl/HI
10,5

H),IM

SUB

10,5

10,5

IP

SRP

SBC

SBC

SBC

SBC

IRRI

1M

SBC

SBC

II,la

n,Iu

Rl,RI

IA2,Al

HI,IM

IRI,IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

DA
HI

DA
IRI

n,t2

IRI

OR

OR
ll,

Ira

OR

OR

OR

IR2,Hl

Ht,IM

IHI/IM

10,5

10,5

6,5

POP
IBI

AND

AND

AND

AND

AND

AND

fl,I2

II,Ira

H2,Rl

IR2,Al

HI,IM

IRl,IM

6,5

10,5

la,S

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM
IHI

TCM

TCM

TCM

TCM

TCM

TCM

II, t2

Il,Ila

R2,RI

IR2,HI

HI,IM

IRl,IM

10112,1 12/14,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH
H,

PUSH
JR,

TM

TM

TM

TM

TM

TM

II,la

H2,Rl

IR2,Hl

HI,IM

IRl/IM

10,5

10,5

12,0

18,0

LDE

LDE!

6,5

10,5

10,5

II,

Ira

LDE
12,

INC

"

t-t-t-t-t-'--I--I---

r-6,1

LDEI

6,5

6,5

EI
10,5

10,5

10,5

CP

CP

CP

CP

CP

CP

n,Ita

Ha,RI

lRa,Rl

HI/1M

IBI/IM

6,5

10,5

10,5

10,5

10,5

CLR
HI

CLR
lBI

XOR

XOR

XOR

XOR

XOR

XOR

II, I2

rl,Ir2

R2,Hl

IR2,Rl

Hl,IM

1Rl,IM

12,0

18,0

LOC

LDCI

16,0

IRET

f--6,5

LD

6,5

6,5

SRA
lBI

6,5

6,5

6,5

10,5

RR
BI

RR
lBI

LD

LD

Il,IH2

R2,Rl

8,5

8,5

6,5

10,5

LD

LD

Ill, I2

R2,IRI

12,0

18,0

LDC

LOCI CALL"

20,0

20,0

RCF
I---

Opcode
Nibble

t

Upper
Opcodo- A
Nibble
Flnt
Operand
'2-byte instructlon; fetch cycle appears as a 3-by!e instruction

10,5

CALL

LD

DA

I2, x, Rl

10,5

10,5

10,5

LD

LD

LD

IR;!,R}

R1,1M

IR1,IM

IRRI

"Lower
"

V

RET

t--

II, x, R2

SRA
HI

SWAP SWAP
IHI
HI

14,0

lQ,5

Il,III2 In,lr12

r2,III1 lI2,IIn

I---

10,5

6,5

"

6,5

IP

hn Ira,IIn

11,12

6,5

l2/1O,0

cc,DA

6,1
DI

6,5

RRC
lBI

6,5
LD
[I,IM

Ina Irl, Iru
12,0
18,0

6,5

6,5

RA

II,

INCW INCW
HHI
IHI

RRC
RI

IR
ee,

lO,S

COM
HI

lIL
IRI

12/10,0

10,5

OR
H2,Rl

10,5

RL
HI

12/tO,S

IRl,IM

POP
BI

6,5

6,5

RdM IRI,IM

6,5

Execution
Cycle.

96

10,5

It,lra

ADC ADC ADC ADC ADC ADC

DECW DECW
HHI
JRI

:>

6,5

11,12

INC
HI

.!!

6,5

IHI

RLC
HI

.•

6,5

DEC ADD ADD ADD ADD ADD ADD

6,5

SCF
I--6,5

CCF

f--6,0

-

Pipeline
Cycl••

MnemOnic

Second
Operand

NOP

Lagend:
R '" a-Bit Address
r == 4-Bit Address
HI or rl = Dsl Address
R2 or r2 = Src Address

Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.

Absolute Maximum Ratings
Voltage on all pins
with respect to GND
·-0.3 V to +7.0 V
Operating Ambient
ooe to + 70 0 e
Temperature . . . . . . . .
Storage Temperature .. . - 65°e to + l50 0 e

Stresses greater than those listed under Absolute Maximum
Ratinqs may cause permanet damage to the device. This is a

stress rating only; operation of the device at any condition
above those indicated in the operational sections of these
specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device
reliability.

Standard Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the

reference pin. Standard conditions are as
follows:
• +4.75 V :S Vee :S +5.25 V
• GND = 0 V
• ooe :S + 70 0 e

+5 V

+5

+5V
2.1K

v

+5V

18K

1.Sk
74LS04

1.5k
74LS04

1
I

c,"

15pF MAX

- - - - - , - - XT Al1

I
I

Figure 13. Test Load I

Figure 14. Test Load 2

c, "

15pF MAX

Figure 15. TTL External Clock Interlace Circuit
(Both the clock and its complement are required)

DC Characteristics
Symbol

veH
VeL

VIH
VIL

VRH
VRL
VOH
VOL

IlL

IOL

IJR
lee
IMM
VMM

Parameter

Clock input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Reset Input High Voltage
Reset Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Reset Input Current
Vee Supply Current
VMM Supply Current
Backup Supply Voltage

Min

3.8
-0.3
2.0
-0.3
3.8
-0.3
2.4
-10
-10

3

Max

Unit

Condition

Vee
0.8
Vee
0.8
Vee
0.8

V
V
V
V
V
V
V
V
I"A
I"A
I"A
rnA
rnA
V

Driven by External Clock Generator
Driven by External Clock Generator

0.4
10
10
-50
120
10
Vee

-250l"A
+2.0 rnA
o V"'" VIN "'" + 5.25 V
o V"'" VIN "'" + 5.25 V
Vee = +5.25 V, VHI~
10H =
10L =

0V

Power Down Mode
Power Down

97

External 1/0 or Memory ReadlWrite
ZB671

No.

Symbol

Min

Parameter

TdA(AS)
Address Valid to AS i Delay
1
TdAS(A)
AS i to Address Float Delay
2
TdA(DS)
AS i to Read Data Required Valid
3
4
TwAS
AS Low Width
Address Float to DS L
TdAz(DS)
5
DS (Read) Low Width
6-TwDSR
7
TwDSW
DS (Write) low Width
TdDSR(DR)
DS L to Read Data Required Valid
8
ThDR(DS)
Read Data to DS i Hold Time
9
TdDS(A)
DS i to Address Active Delay
10
11
TdDS(AS)
DS i to AS L Delay
12-TdR/W(AS)--RIW Valid to AS i Delay
TdDS(R/W)
DS i to RIff[ Not Valid
13
TdDW(DSW)
Write Data Valid to DS (Write) L Delay
14
TdDS(DW)
DS i to Write data Not Valid Delay
15
TdA(DR)
Address valid to Read Data Required Valid
16
TdAS(DS)
AS i to DS L Delay
17
NOTES:
1. Test Load I
2. Timing numbers given are for minimum TpC

3. Also see clock cycle time dependent characteristics
table.
4. When using extended memory timing add 2 TpC.

Max

50
70
360
80
0
250
160
200
0
70
70
50
60
50
70
410
80

Notes*t
1,2,3
1,2,3
1,2,3,4
1,2,3
1
1,2,3,4
1,2,3,4
1,2,3,4
1
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3

5. All timing references use 2.0 V for a logic "I" and 0.8 for a
logic "0".
All units in nanoseconds (ns).
All timings are preliminary and subject to change.

RlW
PORT 0,

OM

:
PORT 1

os

__________~~------~I~--------~®~------~~I$----_r-----

(READ)

PORT 1

00-07 OUT

DS
(WRITE)

Figure 15. External 1/0 or Memory Read/Write

98

Additional Timing
No.
1

Z8671

Symbol

TpC
TrC,TlC
2
3
TwC
4
TwTinL
5--TwTinH
TpTin
6
TrTin, TfTin
7
8a
TwIL
TwIL
8b
9
TwIH

Parameter

Min

Input Clock Period
Clock Input Rise And Fall Times
Input Clock Width
Timer Input low Width
Timer Input High Width
Timer Input Period
Timer input Rise And Fall Times
Interrupt Request Input Low Time
Interrupt Request Input Low Time
Interrupt Request Input High Time

125

NOTES:
1. Clock timing references uses 3.8 V for a logic "1" and 0.8 V
for a logic "0"
2. Timing reference uses 2.0 V for a logic "II' and 0.8 V
for a logic "Of'"

Max
1000

Notes't

25
37

100
3TpC--8TpC

100
100
3TpC
3TpC

I
2
2
2
2
2,3
2,4
2,3

~. Interrupt request via Port 3 (P31-P33).
4. Interrupt request via Port 3 (P30l.

*

Units in nanoseconds (ns).

t

All timings are preliminary and sllbject

to change.

C;~OC;K

TIN

IRQN

Figure 16. ,AdditioD!!1 Timing

Memory Port Timing
Z8671

1
2

symbol

Parameter

Min

TdA(DI)
ThDI(A)

Address Valid to Data Input Delay
Da.ta In Hold Time

NOTES:
I. Test Load 2
2. This is a Clock-~ycle-Dependent param~ter.. For clock freQllencies

M\Ix Notes't
460

o

1,2
1

Units ar~ nanC?~cq~ds unless othery.risf;! sp~cifiedi

timin9 are

preliJ'Il.~:p.ary ~nd

supjecl to

cha:p.ge~

other th(~m thE:! maxim'!lm, 1,lse the fo~lowing formula;

Z8671 ; 5 TpG -165; 28611-12 ; 5 TpC -95

.O~A1Q ==>1::::.==:=:r,;§;:::==:::.:r~f~~~
6

.(,

3

2

1

44

43

42

I,

1

40

"
"

Riw
os

NC
P24

,.

P22

"
"
"

P20
P33
P3 4

30

P1s

29

P1s

31

Z868'
Z8682
Z8684

P23
P2,

P'7

18

Figure 2a. DIP Pin Configuration

e

RESET

19

20 21

22 23 24

2S

26 21

28

~...,Lt'l\Dr-O"'NM""U

rr

~

~ ~ ~

a:

0: Q: i

a:: z

5-1859

Figure 2b. Chip Carrier Pin Configuration

Architecture
Z8681/2/4 architecture is characterized by
a flexible I/O scheme, an efficient register
and address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand
powerful I/O capabilities. The Z8681/2/4
fulfills this with 24 pins available for input
and output. These lines are grouped into
three ports of eight lines each and are
configurable under software control to
provide timing, status signals, serial or
parallel I/O with or without handshake, and
an Address bus for interfacing external
memory.

104

Three basic address space are available:
program memory, data memory and the
register file (internal). The 143-byte randomaccess register file is composed of 124
general-purpose registers, three I/O port
registers, and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.

Architecture (Continued)
OUTPUT

Vee

XTAL

GND

As

!!

I/O
(BIT PROGRAMMABLE)

ADDRESS OR 110
(NIBBLE PROGRAMMABLE)

ADDRESS/DATA OR 110
(BYTE PROGRAMMABLE)

~--------------~v~-----------------'
Z·BUS WHEN USED AS
ADDRESS/DATA BUS

Figure 3. Functional Block Diagram

Pin Description
AS Address Strobe (output, active Low).

Address Strobe is pulsed once at the
beginning of each machine cycle. Addresses
output via Port 1 for all external program or
data memory transfers are valid at the
trailing edge of AS.
OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.
POO-P07' 1/0 Port Lines (input/output, TTL
compatible). 8 lines Nibble Programmable
that can be configured under program
control for I/O or external memory interface.
P10-P17. Address/Data Port (bidirectional).
Multiplexed address (Ao-A7) and data
(Do-D7) lines used to interface with program
and data memory.
P2o-P27' 1/0 Port Lines (input/output, TTL
compatible). 8 lines Bit Programmable.

In addition they can be configured to
provide open drain outputs.
P30-P34. Input Port Lines (TTL compatible).
They can also configured as control lines.
P3s-P37. Output Port Lines (TTL compatible)
They can also configured as control lines.
RESET.* Reset (input, active Low). RESET
inizializes the Z8681/2/4. When RESET is
deactivated, program execution begins from
program location OOOCH for the Z8681, 0812H
for the Z8682 and 1012H for the Z8684.
R/W. Read/Write (output). R/W il Low when
the Z8681/2/4 is writing to external program
or data memory.
XTALL XTAL2. Crystal L Crystal 2 (timebase input and output). These pins connect a
parallel-resonant crystal to the on-chip clock
oscillator and buffer.

105

Summary of Z8681. Z8682 and Z8684 Differences
Feature

Z8681

Z8682

Z8684

Address of first instruction

12

2066

4114

0-64K

executed after Reset

Adressable memory space

2K-64K

4K-64K

Address of interrupt vectors O-ll

2048-2065

4096-4]]3

Reset input high voltage

TTL levels'

7.35-8.0 V

7.35-8.0V

Port 0 configuration after
Reset

Input, float after reset
Can be programmed as
Address bits.

Output, configured as
Address bits AS-A 15

Output, configured as
Address bits AS-AI5

External memory timing
start-up configurations

Extended Timing

Normal Timing

Normal Timing

Interrupt vectors

2 byte vectors point
directly to service
routines

2 byte vectors in internal 2 byte vectors in internal
ROM point to 3 byte Jump ROM point to 3 byte Jump
instructions, which point instructions, which point

Interrupt response lime

261'sec

to service routines.

to service routines.

, 8.0 V V IN max.

Address Spaces
Program Memory. * The Z868112/4 addresses
64K/62K/60K bytes of external program
memory space (Figure 4).
F or the Z8681, the first 12 bytes of
program memory are reserved for the
interrupt vectors. These location contain six
16-bit vectors that correspond to the six
available interrupts. Program execution
begins at location OOOCH after a reset.
The Z8682 has six 24-bit interrupt vectors
beginning at address 0800H. The vectors
consist of Jump Absolute instructions. After a
reset, program execution begins at location
0812H for the Z8682.
The Z8684 has six 24 bit interrupt vectors
beginning at address 1000H. The vectors
consists of Jump Absolute' 'instructions. After
a reset, program execution begins at location
10l2H for the Z8684.
Data Memory.* The Z8681/2/4 can address
64K/62K/60K bytes of external data memory.
External data memory may be included with

'This feature differs in the Z8681, Z8682 and Z8684

106

or separated from the external program
memory space. DM, an optional I/O function
that can be programmed to appear on pin
P34, is used to distinguish between data and
program memory space.

Register File. The 143-byte register file
includes three I/O port registers (RO, R2,
R3), 124 general-purpose registers (R4-R127)
and 16 control and status registers
(R240-R255). These registers are assigned the
address locations shown in Figure 5.
Z8681/2/4 instructions can access registers
directly or indirectly with an 8-bit address
field. This also allows short 4- bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16
contiguous locations (Figure 5).
The Register Pointer addresses the starting
location of the active working-register group
(Figure 6).

Address Spaces (Continued)
Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which

Z8681

can reside anywhere in data memory. An
8-bit Stack Pointer (R255) is used for the
internal stack that resides within the 124
general-purpose registers (R4-RI27).

Z8682

65536

Z8684
,.-----...,65536

65536

PROGRAM
MEMORY
PROGRAM
MEMORY

PROGRAM
MEMORY

=
=
=
=
=
=
LOCATION OF FIRST
BYTE OF INSTRUCTION

EXECUTED AFTER
RESET

INTERRUPT
VECTOR
(LOWER BYTE)

INTERRUPT
VECTOR
(UPPER BYTE)

LOCATION OF FIRST
BYTE OF INSTRUCTION
EXECUTED AFTER
RESET

--------

(812H) 2066
2065

IR05

- (811H)

IR04

=
=
=
=
=(

IR03
IR02
IRQ1
IROO

-

3 BYTE INTERRUPT
JUMP INSTRUCTIONS

BODH) 2048
2047

c-------- ,
rrrrrr-

IRQS
IRQ4
IR03
IR02
IR01
IROO

-~

- '8
- '6
- '4

NOT
ADDRESSABLE
NOT
ADDRESSABLE

-'
-'
2

0

Figure 4. Z868112/4 Program Memory Map

107

Address Spaces (Continued)
LOCATION

IDENTIFIERS

255

STACK POINTER (BITS 7-0)

SPL

254

STACK POINTER (BITS 15-8)

SPH

253

REGISTER POINTER

252

PROGRAM CONTROL FLAGS

flAGS

251

INTERRUPT MASK REGISTER

IMR

RP

250

INTERRUPT REQUEST REGISTER"

IRQ

249

INTERRUPT PRIORITY REGISTER

IPR

248

PORTS 0-1 MODE

P01M

247

PORT 3 MODE

P3M

246

PORT 2 MODE

The upper nibble 01 lite reglsler iii. address
provided by the register point.r speclfl••
tIM acUvl working-register "roup.

127

P2M

245

TO PRESCALER

244

TIMER/COUNTER 0

243

Tl PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

TMR

240

SERIAL 1/0

SIO

PREO
TO
PRE1

T1

NOT
IMPLEMENTED

127

--I
--I

The lower
nibble of

(

SPECIFIED WORKING·
REGISTER GROUP

the regi,ter
tile addre.1

.-

provided by
the in.fructlon
points 10 the

--1

GENERAL·PURPOSE
REGISTERS

PORT 3

P3

PORT 2

P2

PORT 0

PO

Figure 5. The Register File

--I
--I

specilled
regl'''lr.

1

----'/OPORTS-----

3
0

Figure 6. The Register Pointer

Serial Input/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for fullduplex serial asynchronous receiver/
transmitter operation. The bit rate is
. controlled by Counter/Timer 0, with a
maximum rate of 62.5K bits/second at 8 MHz
and 93.75K bits/second at 12 MHz.
The Z868112/4 automatically adds a start bit
and two stop bits to transmitted data (Figure
7). Odd parity is also available as an option.

108

Eight data bits are always transmitted,
regardless of parity selection. If parity is
enabled, the eighth data. bit is used as the
odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by
a parity error flag. Received characters
generate the IRQ3 interrupt request.

Seriallnput/Output (Continued)
Transmitted Data
(No Parity)

Received Data
(No Parity)

I~I~I~I~I~I~I~I~I~I~I
LSTAATBIT
' - - - - - - - E I G H T DATA 81TS
TWO STOP 81TS

I

L - - - - - - - - - - O N E STOP 81T

Transmitted Data
(With Parity)

",1

LSTART81T
' - - - - - - E I G H T DATA 81TS

Received Data
(With Parity)

1~lpl~I~I~I~I~I~I~I~1

Ispl~1 pl~I~I~I~I~I~I~lsrl
L_LsTART8IT
' - - - - - - S E V E N DATA 81TS

111

ODD PARITY
TWO STOP 81TS

_ _
LSTART8IT
' - - - - - - S E V E N DATA 81TS
PARITY ERROR FLAG

' - - - - - - - - - - - O N E STOP 81T

Figure 7, Serial Data Formals

Counter ITimers
The Z8681/2/4 contains two 8-bit
programmable counter/timers (To and T)),
each driven by its own 6-bit programmable
prescaler. The T) pres caler can be driven by
: internal or external clock sources; however,
, the To prescaler is driven by the internal
clock only.
The 6-bit prescalers can divide the input
frequency of the clock source by any number
from 1 to 64. Each prescaler drives is
. counter, which decrements the value (1 to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request - IR04 (To) or IR05
(T)) - is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be
programmed to stop upon reaching zero

(single-pass mode) or to automatically reload
the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the prescalers, can be read any time
wifhout disturbing their value or count
mode.
The clock source for T) is user-definable;
it cari be either the internal microprocessor
clock divided by four, or an external signal
input via Port 3. The Timer Mode register
configures the external timer input as an
external clock, a trigger input that can be
retriggerable or non-retriggerable, or as a
gate input for the internal clock. The
counter/timers can be programmably
cascaded by connecting the To output to the
input of T). Port 3 line P36 also serves as a
timer output (Tour) through which To, T) or
the internal clock can be output.

109

I/O Ports
The Z866112/4 has 24 lines available for
input and output. These lines are grouped
into three ports of eight lines each and are
configurable as input, output or address.
Under software control, the ports can be
programmed to provide address outputs,
timing, status signals, serial I/O; and parallel
1/0 with or without handshake. All ports
have active pull-ups and pull-downs
cbmpatibie with TTL loads.

Port 1 is a dedicated Z-BUS compatible
memory interface. The operations of Port 1
are supported by the Address Strobe (AS)
and Data Strobe (DS) lines; and by th~
ReadlWrite (RIW) and Data Memory (DM)
control lines. The low-order program and
data memory addresses (Ao-A7) are output
through Port 1 (Figure 8) and are
multiplexed with data in/out (Do-D7).
Instruction fetch and data memory read/write
operations are done through this port.
Port 1 cannot be used as a register nor
can a handshake mode be used with this
port. ..
.
The Z8681, the Z8682 and the Z8684 wake
up with the 8 bits of Port 1 configured as
address outputs for external memory. If more
than eight address line are required with the
Z868 1, additinal lines can be obtained by
programming Port a bits as address bits. The
least-significant four bits of Port a can be
configured to supply address bits As-All for
4K byte addressing or both nibbles of Port a
can be configured to supply address bits
As-AI5 for 64K byte addressing.

Port 0* can be programmed as a nibble
I/O port, or as an address port for
interfacing external memory (Figure 9).
When used as an I/O port, Port a may be
placed under handshake control. In this
configuration, Port 3 lines P32 and P35 are
used as the handshake controls DAVo and
RDYO. Handshake signal assignment is
dictated by the 1/0 direction of the upper
nubble P04-P07.
For external memory references, Port a
can provide address bits As-All (lower
nibble) or As-AI5 (lower and upper nibbles)
depending on the required address space. If
the address range requires 12 bits or. less,
the upper nibble of Port a can be
programmed independently as I/O while the
lower nibble is used for addressing.
In the Z8681', Port a lines float after reset;
their logic state is unknown until the
execution of an initialization routine that
configures Port O.
Such an initialization routine must reside
within the first 256 bytes of executable code
and must be physically mapped into memory
by forCing the Port a address lines to a
known state. See Figure 10. The proper Port
initialization sequence is:
1. Write initial address (As-AI5) of
initialization routine to Port a address lines.
2. Configure Port a Mode Register to output
As-AI5 (or As-All).
To permit the use of slow memory, an
automatic wait mode of two oscillator clock
cycles is configured for the bus timing of the
Z8681 after each reset. The initialization

POirrt
(i/O OR ADo-AD7

TO EXTERNAL
MEMORV

FigUre It Port I
• Thi' feature differs iil the Z8681, 28682 and Z8684

110

Figure 9. Port il

I/O Ports (Continued)

A
ADo-AC1

PORn
~

As. os, R/W
Z8681 12/4

•
r

.
PROGRAM
MEMORY
(4K BYTES)

112 PORT 0 {

~~~-1
Figure 10. Port 0 Address Lines Tied to Logic 0

routine could include reconfiguration to
eliminate this extended timing mode.
The following example illustrates the
manner in which an initialization routine can
be mapped in a 28681 system with 4K of
memory.
Example. In Figure 10, the initialization
routine is mapped to the first 256 bytes of
program memory. Pull-down resistors
maintain the address lines at a logic 0 level
when these lines are floating. The leakage
· current caused by fanout must be taken into
consideration when selecting the value of the
pulldown resistors. The resistor value must
be large enough to allow the Port 0 output
driver to pull the line to a logic one.
Generally, pulldown resistors are
incompatible with TTL loads. If Port 0 drives
into TTL input loads (ILOW = 1.6 rna) the
external resistors should be tied to Vee and
· the initialization routine put in address space
FFOOwFFFFH·
In the Z8682/4*, Port 0 lines are configured
· as address lines As-A]5 after a Reset. If one
· or both nibbles are needed for I/O
operation, they must be configured by
writing to the Port 0 Mode register. The
28682/4 is in the fast memory timing mode

after Reset, so the initialization routine must
be in fast memory.

Port 2 bits can be programmed
independently as input or output (Figure 11).
This port is always available for I/O
operations. In addition, Port 2 can be
configured to provide open-drain outputs.
Like Port 0, Port 2 may also be placed
under handshake control. In this
configuration, Port 3 lines P3] and P36 are
used as the handshake controls lines DAV2
and RDY2. The handshake signal assignment
for Port 3 linses P3] and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

PORT I(UD)

P27

}

..AltDSHAKE CONTROLS
DAVi AND RDY2
(P3, AND P3,)

Figure 11. Pori 2

• This feature differs in the Z8681, 28682 and 28684

III

I/O Ports (Continued)
Port 3 lines can be configured as I/O or
control lines (Figure 12). In either case, the
direction of the eight lines is fixed as four
input (P30-P33) and four output (P34-P37).
F or serial I/O, lines P30 and P37 are
programmed as serial in and serial out,
respectively.
Port 3 can also provide the following
control functions: handshake for Ports 0 and
2 (DAVand RDY); four external interrupt
request signals (IRQO-IRQ3); timer input and
output signals (TIN and Tour) and Data
. Memory Select (DM) .

....--

PORT 3
(110 OR CONTROL)

Z8681/2/4

Figure 12. Pori 3

• Interrupts*
The Z8681/2/4 allows six different
interrupts from eight sources: the four Port 3
lines P30-P33, Serial In, Serial Out, and the
two counter/timers. These interrupts are both
maskable and prioritized. The interrupt Mask
register globally or individually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z8681, Z8682 and Z8684 interrupts are
vectored through locations in program
memory. When an interrupt request is
granted, an interrupt machine cycle is
entered. This disables all subsequent
interrupts, saves the Program Counter and
status flags, and access the program memory
vector rocation reserved for that interrupt. In
the Z868 I , this memory location and the next
byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request. The Z8681 takes 26 system
clock cycles to enter an interrupt subroutine.
The Z8682/4 have a small internal ROM
that contains six 2-byte interrupt vectors
pointing to addresses 2048-2065/4096-4]]4,

.. This feature differs in the Z8681 and Z8682

112

where 3-byte jump absolute instructions are
located (See Figure 4). These jump
instructions each contain a I-byte opcode
and a 2-byte starting address for the
interrupt service routine. The Z8682/4 take
36 system clock cycles to enter an interrupt
subroutine.

Z8682

Z8684

Address

Address

(Hex)

(Hex)

800-802 1000-1002
803-805 1003-1005
806-808 1006-1008
809-80B 1009-1000
80C-80E lOOC-100E
80F-811 lOOF-1011

Contains Jump Instruction
and
Subroutine Address For
IRQo
IRQ]
IRQ2
IRQ3
IRQ4
IRQ5

Table I. Z868214 Interrupt Processing

Polled interrupt systems are also
supported. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitance (Cu:;;; 15 pF maximum) from
Power Down Standby Option
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available only to the user as a bonding
option whereby pin 2 (normally XTAL2) is
replaced by the VMM (standby) power supply
input. This necessitates the use of an external
clock generator (input = XTALl) rather than
a crystal source.
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 13 shows the recommended circuit for
a battery back-up supply system.
Z868112/4 Interchangeability
Although the Z8681, Z8682 and Z8684 have
minor differences, a system can be designed
for compatibility with both ROM less versions.
To achieve interchangeabi'lity, the design
must take into account the special
requirements of each device in the external
interface, initialization, and memory
mapping.
External Interface. The Z8682/4 requires a
7.5 V positive logic level on the RESET pin
for at least 6 clock periods immediately
following reset, as shown in Figure 14. The
Z8681 requires a 3.8 V or higher positive
logic level, but is compatible with the
Z8682/4 RESET waveform. Figure 15 shows a
simple circuit for generating the 7.5 V level.
Initialization. The Z8681 wakes up after
reset with Port 0 configured as an input,
which means Port 0 lines are floating in a
high-impedance state. Because of this pullup
or pulldow, resistors must be attached to Port
o lines to force them to a valid logic level

each pin to ground. The specifications for
the crystal are as follows:
• AT cut, parallel-resonant
• Series resistance, Rs ~ 100 n
• For Z868112/4, Z868XL 8 MHz maximum
• For Z8681A/2A!4A, 12 MHz maximum

+5

v 0-----_---1

VDD

Z8681 12/4

J
Figure 13. Recommended Driver Circuit for
Power-Down Operation

until Port 0 is configured as an address port.
Port 0 initialization is discussed in the
section on ports. An example of an
initialization routine for Z8681/2/4
compatibility is shown in Table 2. Only the
Z8681 need execute this program.
7.35 TO 1.0 Y

/

;;,;,;.;~,;.;.....{ - - - - -

VRH

\
'-- ----VRH

3.8 V MIN

VRL-----J

Figure 14. Z8682/4 RESET Pin Input Waveform

113

Z8681/2/4 Interchangeability (Continued)
+v

Address Opcodes Instruction

Comments

oooe

E6 00 00 LD PO #OOH
E6 F8 96 LD POIM#96H

Set As-AI5 to 0
Configure Port a as
Ag-A I5 . Eliminate
extended memory

8D 08 12 IP START
ADDRESS

Execute application

GOOF

timing.

0012

program.

Table 2. Initialization Routine

}---~---l

RESET Z8681/2/4

7.35 - 8.0 V
OPEN
COLLECTOR
TTL GATE

Figure 15. RESET Circuit

Memory Mapping. The Z868 1, Z8682 and
Z8684 lower memory boundaries are located
at 0, 2048 and 4076 respectively. A single
program ROM can be used with either
product if the logical program memory map
shown in Figure 16 is followed. The Z8681
vectors and initialization routine must be
starting at address 0 and the Z8682/4 3-byte
vectors (jump instructions) must be at
address 2048/4096 and higher. Addresses in
the range 21-2047/21-4095 are not used.
Figure 17 shows pratical schemes for
implementing this memory map using 4K and
2K ROMs.
65536

65536

APPLICATION
PROGRAM

APPLICATION
PROGRAM

4114

A.P. PROG. START ADDRESS

4111

JP IRQS

JP IRQ4

4110

JP IRQ4

JPIRQ3

4105

JP IRQ3

4102

JP IRQ2

JP IRQl

4099

JP IRQl

JP IRQO

4096
4095

JP IRQO

2066

A.P. PROG START ADDRESS

2063

JPIRQS

2060
2057
2054

JP IRQ2

2051
2048
2047

8

Z8682 VECTORS
JUMP INSTRUCTIONS

1

2:8684 VECTORS
JUMP INSTRUCTIONS

1

NOT USED
21

1

15

JP 0812H
LD POIM #96H

12

LD PO #OOH

18

10

IRQS
H
C

IRQ2
IRQl
IRQO

Z8681
VECTORS

°H

Figure 16a. Z868112 Logical Program Memory
Mapping

114

NOT USED

Z8681
INITIALIZATION

IRQ4
IRQ3

I

5H }

10

IRQS
IRQ4
IRQ3
IRQ2

INTERNAL
VECTORS

IRQl
IRQO

Figure 16b. Z8684 Logical Program Memory
Mapping

Z8681/Z86821Z8684 Interchangeability (Continued)

17FF

OK

APPLICATION
PROGRAM

-

1015
1014

NOT USEe

1000

CHIP SELECT "'"

(A12

A11) . "13 • A4 .i\1s

+

FFF

.K

FFF
APPLICATION
PROGRAM

012

814-

811

811
Z8882 VECTORS

800

2K

7FF
NOT USED

15

14

800

-

7FF

15

"

Z8681 VECTORS

AND INITIALIZATION

0
LOGICAL

PHYSICAL

MEMORY

MEMORY

a. Logical to Physical Memory Mapping for 4K ROM

FFF
APPLICATION

PROGRAM

CHIP SELECT

NOT USED

A'0

835
834
820
81F

A,
APPLICATION
PROGRAM

812
811
Z8682 VECTORS

f--

= A;.i . An . AU • i14 . A1s

:D--

A TO ROM
'

-

7FF

35
34

800
7FF

2.

NOT USED

1F

'--+
12

15

14

Z8881 VECTORS
AND INITIALIZATION
LOGICAL
MEMORY

11

rPHYSICAL
MEMORY

b. Logical to Physical Memory Mapping for 2K ROM

Figure 17. Pratical Schemes for Implementing Z8G81 and Z8682 Compatible Memory Map

115

Instruction Set Notation
Addressing Modes. The following notation is
used to describe the addressing modes and
instruction operations as shown in the
instruction summary.
IRR
Irr
X
DA
RA

1M
R
r
IR
Ir
RR

Indirect register pair or indirect workingregister pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect workingregister address
Indirect working-register address only
Register pair or working register pair address

Symbols. The following symbols are used in
describing the instruction set.
dst
src
cc

Destination location or contents
Source location or contents
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)

IMR

Interrupt mask register (control register 251)

Assignment of a value is indicated by the
symbol "<-". For example,
dst <- dst + src
indicates that the source data is added to the
destination data and the result is stored in
the destination location. The notation
"addr(n)" is used to refer to bit "n" of a
given location. For example,
dst (7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the
following six arithmetic flags plus two user
selectable flags:
C
Z
S
V
D
H

o

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

b7

bO

FI (
F2 j user flags

Affected flags are indicated by:

I

*
X

Clared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

Condition Codes
Value
1000
0111
III 1
0110
Ilia
1101
0101
0100
1100
OlIO
Ilia
1001
0001
1010
0010
III 1
alII
1011
0011
0000

116

Mnemonic

Meaning

C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set
C = I
C = a
Z = 1
Z = a
S = a
S = I
V = I
V = a
Z = 1
Z = a
(S XOR V) = 0
(S XOR V) = I
[Z OR (S XOR V)[
a
[Z OR (S XOR V)[
1
C = a
C = I
0)
(C = a AND Z
(C OR Z) = 1

Instruction Formats
ope

CCF, 01, EI, IRET, NOP,
ReF, RET, SCF

ope

dot

INCr

One-Byte Instruction

ope

elR, CPl, OAt DEC,

MODE

dsilire

OR

I

1 1 0 dltl,re

I

~~i~'~~~R~~~:R.POP,

OR
OR

RAC, SRA, SWAP

I

ope

11

I--"'d''-'''---''' OR

I, , ,01

1 1 1 0
1 1 1 0

d,'

ADe, ADD, AND, CP,
lD, OR. SSC. SUB,
TeM, 1M! XOR

JP, CALL (Indirect)

d.,
OR

ope

I,

1 1

01

ds'

ADe, ADD, AND, CP
lO, OR, SSC, SUB,
TeM, TM, XOR

SRP

VALUE

".

MODE

ope

MODE

d,t

Ite

MODE

ope

dltlarc

.reldl'

ADe, ADD, AND.
CP, OR,

TeM, TM, XOR

LO. lOE, LOEI,
LOC, LOCI

ope

'0
OR
OR

dot

sac. SUB.

1 1 1 0
til 0

do'

ope

MOD

'0

dltl're
ADDRESS

d,tI,rc
ope
.reld,.
dot

lope

LO
DR

11

1 1

01

Ire

d.ueeR~ ope

JP

oAu
OAL

LD

VA'UE

I

ope

cc

ope
DJNZ, JA

CALL

oAu
OAL

Three-Byte Instructio

Two-Byte Instruction
Figure 18. Instruction Formats

117

Instruction Summary
laatructlon
and Operation

Addr Mode

ADO dBt,.re
dBt~dBt + Bre + C

(Note I)

dat

ADD dBt,Bre
dBt

~

~

SP~SP-2
~ PC; PC ~

@SP

(Note I)

00

r
R

(Note I)

50

• 0

X

COM dst
dst

~

NOT dst

CP dst,Bre

-

.

• 0 •

- - - -

80
SI

------

R
IR

60
61

-

.

• 0 - -

AD

dst - Bre

010 dBt
dBt ~ DA dBt

R
IR

40
41

* X- -

DEC dBt

00
01

- * .*-- *

dB!~dBt-1

R
IR

DECW dBt

RR

dBt~dBt-1

80

IR

81

01
IMR (7)

0

DJNZ r,dst

8F
RA

r ~ r - I
if r
0

*

rA
r=O-F

X

...

...

--

------

------

LDCI dst,sre
Ir
dst ~ Brc
Irr
r ~ r + I; rr ~ rr + I

Irr
Ir

C3
D3

------

LDE dst,sre
dst ~ Bre

r
Irr

Irr

82
92

------

LDEI dst,sre
Ir
dst ~ sre
Irr
r - r + 1; rr-rr+l

Irr
Ir

83
93

------

NOP
~

POP dst
dst
SP

~

@SP
SP +

~

@SP

~

------

40

-

R
IR

50
51

------

70
71

------

CF

o- - - - -

AF

------

R
IR

sre

RCF
C~O

EI

9F

IMR (7)

~

I

~

-

• * ... - -

R
IR
RR
IR

AO
Al

-

.

dBt +

UfCW dB!
dB!

~

dBt +

IBET

SF

FLAGS ~ @SP; SP ~ SP + I
PC ~ @SP; SP ~ SP + 2; IMR(7)

JP ce,dB!
if cc is true
PC

JR
if

~

dB!

ce,dBt

cc is true,
PC~PC+dst

Range: + 127, -128

118

.

DA

cD
e=O-F
30

RA

eS
e=O-F

~

@SP; SP

RL dB!

nc

dBt

... * - RR dst

* ... ... • ...

RRC dst

~I

IRR

RET
PC

rE
r=O-F
20
21

UfC dBt
dst

------

------

SP + 2

~I~

90

~~

10
II

~~I~

EO
EI

l!ri=E:3J
R
'
, • IR

CO
CI

SBC dBt,sr"
dBt~

------

~

~

•

(Note I)

30
DF

I

SRA ds!

~~I~

• 0 - -

91

dBt-sre-C

SCF
C

.

FF
(Note I)

dBt OR sre

SP~SPcl;

Range: + 127, -128

----...,-

C2
D2

PUSH Bre

PC~PC+dB!

rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5

Irr

OR dst.sre

------

r
Ir
r
R
IR
1M
1M
R

Op"ode Flag. Affected
Byte
(Hex) CZSVI)H

r
Irr

LDC dBt,Brc
dBt ~ Bre

dst
~

1m
R

r
Ir
R
R
R
IR
IR

D4

.-

Ire

r

R
IR

(Note I)

LD dst,Bre
dBt ~ Bre

D6

EF

C~NOTC

0

dBt

. . ... 0 ...

CCF

~

Addr Mode

·

DA
IRR
dst

CLR dst

Instruction
and Operation

10

dst AND sre

CALL dBt

dst

Opcode Flags Affected
Byte
(Hex) CZSVDH

d.t + Brc

AND dBt,Bre
dBt

arc

DO
Dl

. ....... · .
..
• I

I - - - - • 0

Instruction Summary (Continued)
l ...tructloD
and Operation

Addr Mode
dat

SRP arc
RP - src
SUB dst,src
dst - dst - src

are
1m

(Note I)

SWAPdst~ ~

Opcode Flags Affected
Byte
(Hex)
CZSVDH
31

20
FO
FI

• I
X •• X

Note I
These instructions have an identical set of addressing
modes, which are encod~ for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the following table to the
left of the applicable addresSing mode pair.
For example, to determtne the opcode of an ADC
instruction using the addressing modes r (destination) and
Ir (source) is 13.

Inatructlon
and Operation

Addr Mode
dat

are

Opeode Flags Affected
Byte
(Hex) CZSVDH

TCM dst,src
(NOT dst) AND src

(Note I)

60

- • " 0 - -

TM dst, src
dot AND src

(Note I)

70

- • ·0

XOR dot,src
dst - dst XOR src

(Note I)

BO

- • "0 - -

Addr Mode
dat

are

R
R
R
IR

Ir
R
IR
1M
1M

Lower
Opeode Nibble

IJJ

rn

l!l
[]]

I!I
[1J

119

Registers
R240 SIO
Serial I/O Register

R244 TO
Counter/Timer 0 Register

(FOR; Read/Write)

(F4H; ReadlWrite)

I~I~I~I~I~I~I~!~I

1~lo.lo.lo.l~I~I~lo.l

...
l----SER"'LDATAIO'. LU,

R241 TMR
Timer Mode Register

R245 PREO
Prescaler 0 Register

(FIH; Read/Write)

(F5H; Write Only)

j

1~lo.lo.l~I~I~I~lo.l
~.

~:

INTERNAL CLOC~ OUT • 11
EXTERNAL CLOCK

llli~o

=: ..J

NOT T
ueD
• 00
... MODU

1 • LOAD
r,
NO FUNCTION

0 • DISAILE T. COUNT
1 • ENABLE T, COUNT

IH~T~o.:

~ : ~:OU:'CTION

GATE INPUT· 01

(NON.R~=':~~

LSL

.

1~lo.lo.lo.lo.lo.l~lo.l

o•

To SINGLE·PASS

1 • TD MODULQ.N

RESERVED CMUST IE ~

0 • DllAILE T, COUNT

• ,.

COUNTMODE

PRESCALEA MODULO

1 - ENABLE " COUNT

(RANGE: 1-14 DECIMAL
Of-OO HEX)

TRIGGER INPUT. 11
"'£T.IGO.......'"

R242 Tl
Counter Timer 1 Register

R246 P2M
Port 2 Mode Register

(F2H; ReadlWrite)

(F6H; Write Only)

1~lo.lo.lo.l~I~I~lo.l

R243 PREI
Prescaler 1 Register

R247 P3M
Port 3 Mode Register

(F3R; Write Only)

(F7 H ; Write Only)

1~lo.lo.lo.l~l~l~lo.l

~L

1~lo.lo.!o.!o.!~!~!o.l

CDUNTIIODE
1 • T, MODULC).N
o•

Tt SlNGLE·PASS

I

~Lo

o Pia =

t '" " INTERNAL

, PIa

• = T1 EXTERNAL

TIMING INPUT
(Tool IIODE

INPUT

= _RDYO

o0 Ita, = INPUT
~:l Po, = INPUT

PRESCALER MODULO
(RANGE: 1-14 DECIMAL

O1 .... HElIj

PORT. PULL·UPS OPEN DRAIN
t PORT 2 PULL·UPS ACTIVE
AEHRYED (MUST 8E 0)

CLOCK SOURCE

L..._ _ _ _ _ _ ~

120

OUTPUT

= RDYOIDlIVlI

PI<

= D1I

Pat ::::

RDY1/CiQ1

~ ~ m.J".r.~~ :~

: ~~~~T'

=:: ~ k'f.~IL

~ ~~~TOUT

L......_ _ _ _ _ _ _ _ ~~:=:~g:F

Figure 19. Control Registers

P3a

Ita. = OUTPUT

1 1 P3,;:: am/RDY1

L-_ _ _ _ _ ~

P3t =

IN

::

Registers (Continued)
R248 P01M
Port 0 Register
(FSH; Write Only)

R252 FLAGS
Flag Register
(FCH; Read/Write)

l~t~t~t~t~t~t~t~1

'~I.I~I~I~I~t~I~1

'

E~~

~~
L PO,-PO,MODE

PO._Po,MODE:]

OUTPUT '"' 00

00. OUTPUT

INPUT"" 01
"'2-A'5 = 1X
EXTERNAL
MEMORY TIMING
NORMAL '" 0
• EXTENDED :::: 1

LYSE.FLAGF!

L.:USER FLAG F2

01 ., INPUT
1X ., Ae~""
STACK SELECTION
0 ... EXTERNAL
1 '" INTERNAL

HAl.F CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SION FLAG
ZERO FLAG

RESERVED (MUST BE 0)

CARRY FLAG

"ALWAYS EXTENDED TIMING AFTER RESET

R249IPR
Interrupt Priority Register
(F9B; Write Only)

R253 RP
Register Pointer
(FD H; Read/Write)

III ~-".-""~

l~r~I~I~t~I~I~I~1

lo,t~t~t~t~t~t~t~1

"_,.. :J

IRQ3, IA06 PRIORITY (GROUP A)

o ::

IA05 :> IAQ3
1 = IRQ3 > IRQ6

II

LOON'TCARE

RESERVED = 000

=

C :> A :> B
001
A :> B :> C = 010
A> C > B = 011

REOISTER
POINTER

~ ~ ~ ~ : ~ ~~
8 > A > C = "0
RESERVED = 111

IRao, lR02 PRIORITY (GROUP 8)
o = IR02 > IRQO
1 = IROO > IR02
IRQ1, IRQ4 PRIORITY (GROUP C)
= IRQ1 > IRQ4
1 = IRQ4 :> IRQ1

o

R250 IRQ
Interrupt Request Register
(FA H ; Read/Write)

RESERVED (MUST BE 0)

==r-

R254 SPH
Stack Pointer
(FE H; Read/Write)
'~I~I~I~I~I~I~I~I

c=

IROO
IRQ1
IRQ2
IRQ3
IRa4
IRQ6

""
'"'
""
""
""
""

'32 INPUT (00 "" IROO)
P:t, INPUT
P3, INPUT
'30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T,

R251IMR
Interrupt Mask Register
(FEB; Read/Write)

R255 SPL
Stack Pointer
(FF H; Read/Write)

lo,t~t~t~t~t~t~t~1

'~I~I~I~t~l~t~I~1

c=

I''-.--------1

'.00)

1 ENABLES IRQO·IAOI
I~ •

'--------RESERVED (MUST BE 0)
ENABLES INTERRUPTS

Figure 19. Control Registers (Continued)

121

Opcode Map
6,5
DEC
Hl
6,5
RLC
Hl
6,5
INC
Hl
B,O
IP
IRRI
DA
Hl
10,5

pop
Hl
6,5
COM
Hl

II:

l

C>

A

B

C

D
E

F

10,5

ADD

ADD
IHI,IM

6,5
ADD

6,5
ADD

ADD

11,12

rJ.lra

8a,RI

6,5
RLC
IHl

6,5

6,5

10,5

10,5

10,5

10,5

ACe

ACe

ACe
Ra,Rl
10,5
SUB
Ra.Rl

ACe

ACe

ACe

IH2.Hl
10,5
SUB

HI.1M
10,5
SUB
HI,IM

IH1,IM

6,5
INC
IHl
6,1
SRP
1M

10,5

POP
181
6,5
COM
181

10/12,1 12114,1

.!
..Q
:9

la,s

6,5
DEC
IHl

B,5
DA
181

B,S

;;
=-

Low.r Nibbl. (Hex)

fa

r},Ira

6,5
SUB

6,5
SUB

II.

fl,la

11,Ira

6,5
SBC

6,5
SBC

fi,l"

11,

10,5

10,5

10,5

SBC
HI,IM

SBC
IRI,IM

10,5
OR
IR2,Rl

10,5

10,5
OR
IHI.IM
10,5
AND
IRI,IM

Il,la

IIIIrZ

Ra.Rl

6,5
AND

6,5

AND

lI,ra

11t h Z

10,5
AND
R2,H,

6,5
TCM

6,5
TCM

11,12

11,112

6,5
TM

6,5
TM

By......'

OR
HI.IM

10,5

10,5

AND

AND
HI.IM

IR2,Hl

B

6,5
LD

12/10,5

12110,0

DJNZ

11,Ra

la,R,

II/RA

c

D

E

12/10,0

lR

6,5
LD

JP

6,5
INC

cc,RA

11,IM

cC,DA

'1

10,5

lQ,5

10.5

10,5

TCM
Ha,RI

TCM
IRa,Hl

TCM
HI.IM

TCM

10,5

10.5

la,S

TN

TN

Ha,Rl

IR2.Hl

TM
RI,IM

f-----

cc-

-

lRI.IM

10,5
TN
IRI,IM

6.1

DI

- 6,1
EI
10,5

la,S

la,S

CP

CP

8z,81

lRZ.Rl

CP
HI.1M

10,5

10,5
XOR
IRZ.Rl

10,5
XOR
HI,IM

XOR
8z,81

f-

10,5
CP

14,0

RET
f-

IHl,IM
10,5

16,0

XOR

IRET

- 6,5

IRI.IM
10,5

LD
II,

20,0

20,0

CALL"
IRRl

CALL
DA

10,5

10,5

LD
Ra,RI

[RatHl

LD

10,5
LD
HI,IM

RCF

x, 82

f-

10,5

6,5
SCF

LD
12. J:,

HI

r----6,5

1O,S

LD

CCF

lRl,IM

r-----

10,5

6,0

LD

NOP

82.lRl

Opcode
Nibble

ExecutioD

Cycleo

~

UP...'

Opcode- A
Nibble

Fin!

Opercmc:\
OJ-byte instruction; fetch cycle appears "8 a 3-byte instruction

122

t---

r---

Low..

InstructloJl

F

f--

10,5

10,5

6,5
OR

A
6,5
LD

SUB
IRdM

SBC
IRa,HI

6,5
OR

PUSH PUSH
18,
H2
11,Ia
Il.Ir2
10,5
10,5
12,0
18,0
DECW DECW LDE
LDEI
IRl
RRl
Il,Irra Irl.Ina
6,5
6,5
12,0
18,0
RL
RL
LDE
LDEI
Rl
1R1
la.hn In, lUI
lO,S
10,5
6,5
6,5
INCW INCW
CP
CP
RRl
1ft 1
ll,lll
fl,lrJ
6,5
6,5
6,5
6,5
CLK
CLK
XOR
XOR
Rl
1ft 1
fl, r2
rl,1r2
6,5
12,0
IB,O
6,'
MC
LDC LOCI
MC
A:
1R1
u.Irr2 Irl,hra
6,5
6,5
12,0
18,0
SRA
BRA LOC LOCI
Rl
f2, I~rl lra,lrn
1R1
6,5
6,5
6,5
M
M
LD
Hl
1R1
H,lR2
8,5
8,5
6,5
SWAP SWAP
LD
Ifti
Hl
In,r2

IRa.Rl

RdM

10,5

SBC
Ba.RI
10,5
OR

Ira

10,5
ADD
IRa.Rt

Legend.
R ::: B-Bit Address
r = 4-BIt Address
H\ or r, :: DBt Address
RJ or t2 :c: Src Address

Beque.....
Opcode, First Operand, Second Operand

Not.: The blank areas are not defined.

Absolute Maximum Ratings
Voltage on all pins *
with respect to G ND .
-O.3Vto +7.0V
Operating Ambient
Temperature . . . . . .
O°C to + 70°C
Storage Temperature ... - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a

stress rating only; operation of the device at any condition
above those indicated in the operational sections of these
specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device
reliability.

Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the
reference pin. Standard conditions are as
follows:

• +4.75 V :0; Vee :0; +5.25 V
• GND = 0 V
• O°C :0; TA :0; + 70°C for S (Standard
temperature
• -40°C :0; TA :0; +85°C for E (Extended
temperature
+5V

+5V

+5V

2.1K

1.Sk

1.5k

L-_ _ _ _ _ XTAL1

Figure 20. Test Load I

Figure 21. External Clock Interface Circuit

DC Characteristics
Symbol
VCH
VCl

VIH

VIl
VRH
VRL
VOH
VOL
IlL
10L

IIR
Icc

Parameter

Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Reset Input High Voltage
Reset Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Reset Input Current
Vee Supply Current
VMM Supply Current
Backup Supply Voltage

Min

Max

Unit

Condition

3.8

Vce
0.8
Vee
0.8
Vee
0.8

V
V
V
V
V
V
V
V

Driven by External Clock Generator
Driven by External Clock Generator

-0.3
2.0
-0.3
3.8

-0.3
2.4

0.4

-10
-10

10
10
-50
120
80'

3

I'A
I'A
I'A
rnA

10

rnA

Vee

V

See Note
IOH = - 25O I'A
IOL = +2.0 rnA
OV",VIN'" +5.25 V
o V'" VIN '" +5.25V
Vee = +5.25 V, VRL = 0 V

Power Down Mode
Power Down

NOTE:
The Reset line (pin 6) is used to place the Z8682 in external memory mode. This is accomplished as shown in Figure 14

• This value is for Z8681Ll2L14L only.

123

External 1/0 or Memory Read and Write Timing
Z8681/2/4

No.

Symbol

Z8681L/2L/4L
Min Max

Parameter

Z8681A/2A14A

Min

Max

NOles't

1
TdA(AS)
Address Valid to AS t Delay
50
35
1,2,3
2
TdAS(A)
AS t to Address Float Delay
70
45
1,2,3
3
TdAS(DR)
AS t to Read Data Required Valid
360
220
1,2,3,4
4
TwAS
AS Low Width
80
55
1,2,3
5
TdAz(DS)
Address Float to DS t O O
I
6-TwDSR
DS (Read) Low Width
250----185----1,2,3,4
7
TwDSW
DS (Write) Low Width
160
110
1,2,3,4
8
TdDSR(DR)
DS t to Read Data Required Valid
200
130
1,2,3,4
9
ThDR(DS)
Read Data to DS t Hold Time
0
0
1
10
TdDS(A)
DS t to Address Active Delay
70
45
1,2,3
11
TdDS(AS)
DS t to AS Delay
70
55
1,2,3
12-TdR/W(AS)--RiWValid to AS t Delay
50
3 0 - - - - 1,2,3
13
TdDS(R/W)
DS t to R/W Not Valid
60
35
1,2,3
14
TdDW(DSW)
Write Data Valid to DS (Write) t Delay
50
35
1,2,3
15
TdDS(DW)
DS t to Write Data Not Valid Delay
70
45
1,2,3
Address valid to Read Data Required Valid
410
255
1,2,3,4
16
TdA(DR)
17
TdAS(DS)
AS t to DS t Delay
80
55
1,2,3
NOTES;
1. Test Load 1
2. Timing numbers given are for minimum TpC
3. Also see clock cycle dependent characteristics table.
4. When using extended memory timing add 2 TpC.

5. All timing reference use2.0Vfor logic"l"andO.8Vfor a logic "0".
*

All units in nanoseconds (ns).

t Timings are preliminary and subject to change.

PORT 0,

DM

PORT 1

iii
(READ)

PORT 1

Do-D7 OUT

iii
(WRITE)

Figure 22. External I/O or Memory Read/Write Timing

124

Additional Timing Table
Z868112/4

Z8681A/2A14A

Z8681L/2L/4L
No.

Symbol

TpC
1
2
TrC,TIC
TwC
3
4
TwTinL
5-TwTinH
TpTin
6
7
8
9

TrTin, TlTin
TwIL
TwIH

Parameter
Input Clock
Clock Input
Input Clock
Timer Input
Timer Input
Timer Input

Period
Rise And Fall Times
Width
Low Width
High Width
Period

Timer Input Rise And Fall Times
Interrupt Request Input Low Time
Interrupt Request Input High Time

NOTES;
1. Clock timing references uses 3.8 V for a logic "I" and 0.8 V
for a logic "0"

2. Timing reference uses 2.0 V for a logic "I" and 0.8 V

Min

Max

Min

Max

125

1000
25

83

1000
15

37
100
3TpC
TpC
8

26
70
3TpC
1:pC
8
100

100
3TpC

100
70
3TpC

Notes't
1
1
2
2
2
2
2,3
2,3

3. Interrupt request via Port 3.
Units in nanoseconds (ns),
Timings are preliminary and subject to change.

for a logic "0"

Figure 23. Additional Timing

125

Handshake Timing
Z868112/4 Z868lA/2A/4A
No.

Symbol

Z8681L/2L/4L
Min Max
Min

Parameter

I
TsDI(DAV)
Data In Setup Time
0
2
ThDI(DA V)
Data In Hold Time
230
3
TwDAV
Data Available Width
175
4
TdDAVIf(RDY)
DAV ~ Input to RDY ~ Delay
5-TdDAVO£(RDY)-DAV ~ Output to ROY ~ Delay---- 0
6
TdDAVIr(RDY)
DAV i Input to RDY i Delay
7
TdDAVOrCRDY)
DA V iOutput to ROY i Delay
0
8
TdDO(DAV)
Data Out to DAV ~ Delay
50
9
TdRDY(DAV)
Rdy ~ Input to DAV i Delay
0

Max

Notes't

120

1,2
1,3
1,2
1,3
1

0
160
120
175
0
175

120
0
30
0

200

140

NOTES:

1.
2.
3.
4.

Test load I
Input handshake
Output handshake
All timing references use 2.0 V for a logic "I" and 0.8 V

Units in nanoseconds (ns),
Timings are preliminary and subject to change.

for a logic \\0" .

..:::: ~~~~~~~~~~~~~~CD~~~~~~_~~_~~-4
T_A-,'_N_~_L-ID~:~- - .~ - - -.-'- - - 1- ~ ~ ~ -_-_-_-_-_-_D_:__

___

(OUTPUT)

Figure 24a. Input Handshake Timing

DATA OUT

r----

DATA OUT VALID

------~---DAY
(OUTPUT)

RDY
(INPUT)

1~~G)-----~9.
~

------'=~===J~

Figure 24b. Output Handshake Timing

126

7

.

Clock-Cycle-Time-Dependent
Characteristics
Z8681/2/4
Z8681L/2L/4L
Number

Symbols
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdRIW(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

2
3
4
6
7

8
10
11
12
13
14
15
16
17

Z8681A/2A14A

Equation

Equation

TpC-75
TpC-55
4TpC-140*
TpC-45
3TpC-125*
2TpC-90*
3TpC-175*
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215*
TpC-45

TpC-50
TpC-40
4TpC-110*
TpC-30
3TpC-65*
2TpC-55*
3TpC-120*
TpC-40
. TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160*
TpC-30

" Add 2TpC when using extended memory timing.

Ordering Information
Type

Package

Temp.

Clock

ROMless Microcomputer

Z8681/2/4
Z8681/2/4
Z8681/2/4
Z8681/2/4
Z8681/2/4
Z8681/2/4
Z8681/2/4
Z8681/2/4

Bl
B6
Dl
D6
Cl
C6
Kl
K6

Plastic
Plastic
Ceramic
Ceramic
Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

01 + 70°C
-40/+85°C
01 +70°C
-40/+85°C
01 +70°C
-40/+85°C
0/+70°C
-40/+85°C

8 MHz

Z8681/2/4A
Z8681/2/4A
Z8681 12/4A
Z8681/2/4A
Z8681/2/4A
Z8681 12/4A
Z8681 12/4A
Z8681/2/4A

Bl
B6
Dl
D6
Cl
C6
Kl
K6

Plastic
Plastic

0/+70°C
-40/+85°C
01 +70°C
-40/+85°C
01 +70°C
-40/+85°C
0/+70°C
-40/+85°C

12 MHz

Z8681112114L
Z868 1112114L
Z8681112114L
Z8681112114L
Z8681112114L
Z8681112114L
Z8681112114L
28681112114L

Bl
B6
Dl
D6
Cl
C6
Kl
K6

Ceramic

Ceramic
Plastic Chip Carrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier
Plastic
Plastic
Ceramic
Ceramic

Plastic Chip Catrier
Plastic Chip Carrier
Ceramic Chip Carrier
Ceramic Chip Carrier

01 + 70°C
-40/+85°C
01 +70°C
-40/+85°C
0/+70°C
-40/+85°C
01 + 70°C
-40/+85°C

Description

ROMless Microcomputer
Low Power Version
8 MHz

127

II.

Preliminary Data

Z8 4K EPROM Microcomputer
• Complete microcomputer, 4K bytes of
EPROM, 128 bytes of RAMm 32 I/O lines,
and up to 60K bytes addressable external
space each for program and data
memory. Fully compatible with standard
ROM version.
• 144-byte register file, including 124
general-registers, four I/O port registers,
and 16 status and control registers.
• Minimum instruction execution time 1 p.s,
at 12 MHz.
• Vectored priority interrupts for I/O,
counter/timers, and UART.
• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.
• Register Pointer so that short, fast
instructions can access apy of nine
working-register groups/in 1.5 p.s (8MHz).

• On-chip oscillator which accepts crystal
or external clock drive.
• Low-power standby option which retains
contents of general-purpose registers.
• Single + 5 V power supply - all pins TTL
compatible.
• Two Eprom programming modes:
- Eprom-like, using a standard Eprom
programmer,
- Autoprogram, self-programming during
normal program execution.
- An on-chip ROM provides a Program/
Verify facility to allow a simple and
time-efficient self-program operation.
• Integrated programmable protection
avoids EPROM content read-out.
• Available in 8 and 12 MHz versions.

p'.

Vee

RESEr

GNO

R/W

os

XTAL!

AS

VMM /XTAL2

PO o
PORT 0

PO,
PO,

(NIBBLE
PROGRAMMABLE)

.O-:-A, EPROM MODE

PO.
P0 5
PO.
PO,

PORT 1

I/OorA/Oo-AIO,

(BYTE
PROGRAMMABLE)
'Of 0, EPROM MODE

P'2
P2,

p'.

ZeSEll

P2 5
P2.
P2,

P'O

p~O

P',

P',

P'2
P',

P'2
P',

p'.

XTALI
CLOCK
CLOCK or
STANDBY BATTERY

P20
P2,

PO,
1I0orAs-A15

VMM ,XTAl2

vee

p'.

P'5

P'5

p'.

p'.

PI,"

P',

P3,
P38
R/W

,

55

8

AS

9

P'5
GNO

10

RESET

PORT 2
1I0(BlT PRO-

GRAMMABlE)
AS+ An [PROM MODE

PORT 3

3

•

39

P3,

38
3,

P2,

P2.
3. P25
35 P2.

3' P23/All
33 P2 2 /A 1Q
32 P2, /A g

Ze6Ell

11

31 P2dA.
30 P3 3 /Vpp

EPM/P32

12

29

'3

,.

P3,/CE

AO'Pea
AI/PO,

14

27

P16/0S

Pl,/D,

SERIAL AND

AZ'PO Z 15

2. P1StOS

PARAllEl 110

A3 /P03

16

A" P04

17

AS/PO S

AND CONTROl
(FOR INPUT;

FOR OUTPUT>
EPROM MODE
SELECTIONS

A SiPOS
PROTB/A,'Po,

'5

,.

PI 4 104

'8
19

23

PI 2/OZ

22

P1,10 1

'0

21

Pia IOO'PROTA

P1 310 3

5-8196

Figure 1. Logic Functions

Figure 2. Pin Configuration

129

General Description
The Z86Eli microcomputer is an EPROM
member of the Z8 family; completely
developed by SGS, it maintains the
sophisticated architecture and full
compatibility with the currently available
ROM-based units.
It can be configured as a stand-alone
microcomputer with 4K bytes of internal
EPROM, or as a traditional microcomputer
that manages up to 120K bytes of external
memory, or as a parallel-processing element
in a system with other processors and
peripheral controllers.
The 4K X 8 on-board EPROM can be
programmed in two modes, Eprom-like and
Autoprogram. In Eprom-like, the
programming procedure is similar to that for

a M2732, with the only exception being for
the programming voltage which must be 12.5
V related to the SGS NMOS-E3 used
technology. Autoprogram permits byteprogramming during normal microcomputer
program execution.
An important facility is the programmable
read-out protections which allow the user to
inhibit external access to proprietory
program code by programming 2 nonvolatile transistors. These locks can be reset
only by erasing the entire EPROM array.
For its characteristics, the Z86Eli can be
considered as a low cost development tool
for the Z8 microcomputer family.

Architecture
Z86E11 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
anCillary features that are helpful in many
applications.
Microcomputer applications demand
powerful I/O capabilities. The Z86Ell fulfills
this with 32 pins dedicated to input/output.
These lines are grouped into four ports of
eight lines each and are configurable under
software control to provide timing, status
signals, serial or parallel I/O with or without
handshake, address/data bus for interfacing
external memory, and address, data and
selections in EPROM mode.
Because the multiplexed address/data bus
is merged with the I/O-oriented ports, the
Z86Ell can assume many different memory
and I/O configurations. These configurations
range from a self-contained microcomputer
to a microprocessor that can address 120K
bytes of external memory (Figure 3).
Three basic address spaces are available to
support this wide range of configurations:
program memory (internal and external),
data memory (external) and the register file

130

(internal). The 144-byte random-access
register file is composed of 124 generalpurpose registers, four I/O port registers,
and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.
An autoprogram logic permits Eprom byteprogramming during the normal
microcomputer program execution, using the
STORE constant isntruction.
This permits the microcomputer to look at
the contents of the working register's register
for an external RAM allocated to the
program memory space, addressed using two
of the register file registers. The renamed
external RAM was expressly developed for
the Autoprogram function, thus it is
externally inaccessible.

Architecture (Continued)
XTAl

AS

os

R/Iii

RESET

UART

TIMERI
COUNTERS (2)

INTERRUPT
CONTROL

Ae+An
(EPROM MOCE)

(BIT PROGRAMMABLE)

ADDRESS/DATA or 110
(BYTE PROGRAMMABLE 1

AO+A7
(EPROM MODE)
~-879S

Figure 3. Block Diagram

Pin Description
PDa-PD,. liD Port Lines (input/outputs, TTL
compatible). 8 lines Nibble Programmable
that can be configured under program
control for I/O or external memory interface
and, Ao-A7 in EPROM mode. P07 can be
configured as Read-out protection in memory
expansion mode (PROTB), applying a high
voltage level (10 V)
Plo-Pl,. liD Port Lines (input/outputs, TTL
compatible). 8 lines Byte Programmable that
can be configured under program control for
I/O or multiplexed address (Ao-A7) and data
(Do-D7) lines used to interface with
program/data memory, and 00-07 in EPROM
mode. Plo can be configured as Read-out

protection in Testing-mode and EPROMmode (PROTA), applying a high voltage
level (10 V).
P2o-P2,. liD Port Lines (input/outputs, TTL
compatible). 8 lines Bit Programmable where
the 4 less significant bits can be configured
as As-All in EPROM mode.
P30-P3,. 110 Port Lines (TTL compatible) 4
lines input (P30-P33), 4 lines output P34-P37).
They can also be configured as control lines.
In EPROM mode: P32 becomes EPM (Epromlike) when a high voltage level (~ 7 V)
is applied, P33 becomes Vpp (12.5 V ±
300 m V), P34 becomes CE to perform
program enable/verify.
131

Pin Description (Continued)
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the
beginning of each machine cycle. Addresses
output via Port I for all external program or
data memory transfers are valid at the
trailing edge of AS. Under program control,
AS can be placed in the high-impedance
state along with ports 0 and I, Data Strobe
and ReacllWrite.

OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

initializes the Z86E II. When RESET is
deactivated, program execution begins from
internal program location OOOCH.

R/W. Read/Write (output). RIW is Low when
the Z86E II is writing to external program or
data memory.

XTALl. XTAL2. Crystal L Crystal 2 (timebase input and output). These pins connect a
series-resonant crystal (8 MHz maximum) or
an external single-phase clock (8 MHz
maximum) to the on-chip clock oscillator and
buffer.

RESET. Reset (input, active Low). RESET

Address Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 4096
bytes consist of on-chip EPROM. At
addresses 4096 and greater, the Z86E II
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These
locations contain six 16-bit vectors that
correspond to the six available interrupts.
Data Memory. The Z86Ell can address 60K
bytes of external data memory beginning at
locations 4096 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-RI27) and 16

132

control and status registers (R240-R255).
These registers are assigned the address
locations shown in Figure 6.
Z86EII instructions can access registers
directly or indirectly with an 8-bit address
field. The Z86EII also allows short 4-bit
register addreSSing using the Register
Pointer (one of the control registers). In the
4-bit mode, the register file is divided into
nine working-register groups, each
occupying 16 contiguous locations (Figure
7). The Register Pointer addresses the
starting location of the active workingregister group.

Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which
can reside anywhere in data memory
between locations 4096 and 65535. An 8-bit
Stack Pointer (R255) is used for the internal
stack that resides within the 124 generalpurpose registers (R4-RI27).

Address Spaces (Continued)
5535

85535

r----------,

EXTERNAL
ROM OR RAM

loc.tlon 0 I
Ii'ttbrl, 01
Instruction
Illecut,d
,1I"rn,t

ON-CHIP
EPROM

"

BASICI
} DEBUG

;. 1'-----------11

IROS

'0

•

Interrupt
Vector

(Low,reyt. I

(Upptr Byle,

IRQ4

8

IR04

7

IR03

8

IR03

51"

Inl,rrupt
VIetor

IRQ2

410-

IRQ2

3

IRQ1

2

IRQi

•
0

EXTERNAL
DATA
MEMORY

IRQS

NOT ADDRESSABLE

IROO
IROO

Figure 4. Program Memory Map
IDENTIFIERS

LOCATION

2"

2"
253

STACK POINTER (BITS 7-0)
STACK POINTER (BITS 15-8)

REGISTER POINTER

SPL
SPH

Figure 5. Data Memory Map

1_-_1(-;::1-_=};.=_J:...=.;.=_=;..=_=_;J..=_=_=_=_;_~_=_;_=_=J:::

RP

252

PROGRAM CONTROL FlAGS

FLAGS

251

INTERRUPT MASK REGISTER

IMR

250

INTERRUPT REQUEST REGISTER

IRQ

249

INTERRUPT PRIORITY REGISTER

IPR

248

PORTS 0-1 MODE

POiM

247

PORT 3 MODE

P3M

246

PORT 2 MODE

P2M

245

TO PRESCALER

24.

TIMER/COUNTER 0

243

T1 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

TMR

2.0

SERIAL 110

SIO

~------------------"'2~

The upper nibble of the r-aleter me Iddre..
provided by the rlgilt •• polnt.r e~mee
the lettve worklng.r-aleter group.
~

PREO

TO
PRE1

T.

NOT
IMPLEMENTED

--I

127

(

The tower

SPECIFIED WORKING·
REGISTER GROUP

nibble 0'
the r.gllter
meecklrell

"l-r~:--;~::'ru~~'1H1
pointe lottie
lpeellltd
regllter.

--I

GENERAL·PURPOSE
REGISTERS

PORT 3

P3

PORT 2

P2

PORT 0

PO

Figure 6. The Register File

_ _ _ _ _ _ _ _ _ _"l'27

--

1------------115
r----,/OP~RTS-----

3

~----~~~------"'O

Figure 7. The Register Pointer

133

Serial Input/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for fullduplex serial asynchronous receiver!
transmitter operation. The bit rate is
controlled by Counter/Timer 0, with a
maximum rate of 62.5K bits/second.
The Z86EIl automatically adds a start bit
and two stop bits to transmitted data (Figure
8). Odd parity is also available as an option.
Eight data bits are always transmitted,

regardless of parity selection. If parity is
enabled, the eighth bit is the odd parity bit.
An interrupt request (IRQ4) is generated on
all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by
a parity error flag. Received characters
generate the IRQ3 interrupt request.

Transmitted Data

Received Data

(No Parity)

(No Parity)

ISplspl

0, 10.1 0,10.10,10,10, I001 STI

1

LSTART BIT
' - - - - - - - E I G H T DATA BITS
TWO STOP BITS

Transmitted Data

Received Data

(With Parity)

(With Parity)

1~lpl~I~I~I~I~I~I~lnl

I~I~I pl~I~I~I~I~I~I~lsij

T
I

I,-----

_LSTAATBIT

.

L

ODD PARITY

I

TWO STOP BITS

' - - - - - - - - - - - O N E STOP BIT

SEVEN DATA BITS

_LsTAATBIT
' - - - - - S E V E N DATA BITS
PARITY ERROR FLAG

Figure 8. Serial Data Formats

Counter/Timers
The Z86EII contains two 8-bit
programmable counter/timers (To and T)),
each driven by its own 6-bit programmable
prescaler. The T) prescaler can be driven by
internal ox external clock sources; however,
the To prescaler is driven by the internal
clock only.
The 6-bit prescaler can divide the input
frequency of the clock source by any number
from I to 64. Each prescaler drives its
counter, which decrements the value (l to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request-IRQ4 (TO) or IRQ5
(TJl-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be
programmed to stop upon reaching zero
(single-pass mode) or to automatically reload
134

the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the prescalers, can be read any time
without disturbing their value or count
mode.
The clock source for T) is user-definable
and can· be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (1 MHz
maximum), a trigger input that can be
retriggerable or non-retriggerable, or as a
gate input for the internal clock. The
counter/timers can be programmably
cascated by connecting the To output to the
input of T). Port 3 line P36 also serves as a
timer output (Tour) through which To, T) or
the internal clock can be output.

I/O Ports
The Z86Ell has 32 lines dedicated to input
and output. These lines are grouped into
four ports of eight lines each and are
configurable as input, output or address/
data. Under software control, the ports can
be programmed to provide address outputs,
timing, status signals, serial I/O, and parallel
I/O with or without handshake. All ports
have active pull-ups and pull-downs
compatible with TTL loads.
All the ports assume different configurations
in EPROM mode.

Port 1 can be programmed as a byte I/O
port or as an address/data port for
interfacing external memory. When used as
an I/O port, Port 1 may be placed under
handshake control. In this configuration, Port
3 lines P33 and P34 are used as the
handshake contoIs RDY 1 and DAV 1 (Ready
and Data Available).
Memory locations greater than 4096 are
referenced through Port 1. To interface
external memory, Port 1 must be
programmed for the multiplexed Address/
"Data mode. If more than 256 external
locations are required, Port 0 must output
the additional lines.
Port 1 can be placed in the highimpedance state along with Port 0, AS, DS
and R/W, allowing the Z86E 11 to share
common resources in multiprocessor and
DMA applications. Data transfers can be
controlled by assigning P33 as a Bus
Acknowledge input and P34 as a Bus
Request output.

~

PORT1

I/O Of ADo-AD1

lines P32 and P35 are used as the handshake
controls DAVo and RDYo. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0
can provide address bits As-All (lower
nibble) or As-A15 (lower and upper nibble)
depending on the required address space. If
the address range requires 12 bits or less,
the upper nibble of Port 0 can be
programmed independently as I/O while the
lower nibble is used for addressing. When
Port 0 nibbles are defined as address bits,
they can be set to the high-impedance state
along with Port 1 and the control signals AS,
DS and R/W.

Figure 9b. Port 0

Port 2 bits can be programmed
independently as input or output. This port is
always available for I/O operations. In
addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this
configuration, Port 3 lines P31 and P36 are
used as the handshake controls lines DAV2
and RDY2. The handshake signal assignment
for Port 3 lines P31 and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

HANDSHAKE CONTROLS
) DAV, AND ROY,

(P3 3 AND P3,J

Figure 9a. Port I

Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port 0 may be placed under handshake
control. In this configuration, Port 3 lines

PORT 2(1/0)

l ow,

HANDSHAKE CONTROLS

AND ROY,
CP3, AND P3e)

Figure 9c. Port 2

135

I/O Ports (Continued)

Port 3 lines can be configured as IIO or
control lines. In either case, the direction of
the eight lines is fixed as four input (P30-P33)
and four output (P34-P37). For serial IIO,
lines P30 and P37 are programmed as serial
in and serial out respectively.
Port 3 can also provide the following
control functions: handshake for Ports 0,
and 2 (DAV and RDY); four external
interrupt request signals (IRQO-IRQ3); timer
input and output signals (TIN and Tour) and
Data Memory Select (DM).

PORTa
1110 OR CONTROL)

Figure 9d. Pori 3

Interrupts
The Z86Ell allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or individually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z86EII interrupts are vectored. When
an interrupt request is granted, and interrupt
machine cycle is entered. This disables all

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitors (C] ~ 15 pF) from each pin to

136

subsequent interrupts, saves the Program
Counter and status flags, and branches to
the program memory vector location
reserved for that interrupt. This memory
location and the next byte contain the 16-bit
address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also
supported. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

ground. The specifications for the crystal are
as follows:
• AT cut, series resonant
• Fundamental types, 8112 MHz maximum
• Series resistance, Rs :5 100 Q.

Power Down Standby Option
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input.
This necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 10 shows the recommended circuit for
a battery back-up supply system.

+5V o-----~-_I VDO

ZllEll

J
Figure 10. Recommended Driver Circuit
for Power Down Operation

EPROM Mode
Eprom-like programming. In this mode,
the microcomputer memory is programmed,
using a standard Eprom Programmer, with
the same procedure as for our M2732 (32K
EPROM). This has been made possible by
the following Z86El1 configuration, where
P10-P17 are used as 8-bit I/O data (00-07),
POO-P07 and P20-P23 are used as 12-bit
Addresses (Ao-All); the microcomputer must
be in Reset state, forcing the related pin to
GND, and the clock must be active for the
complete operation.
Three other pins are available for that
purpose: the EPM pin on port P32, which
allows the microcomputer to recognize the
Eprom-like condition when a high voltage
(~ 7 V) is applied; the Vpp pin on port P33,
which is used to furnish programming
voltage fixed on 12.5 V ± 300mV; and the
CE pin on port P34, which is used to perform
program enable/verify.
For a correct microcomputer set-up the
Vee must be applied at least 100 ms before
the programming procedure starting (Figure
11) .
A simple interface board, described in
Figure 12, allows programming to be carried
out through use of a standard Epromprogrammer.

ClK

EPM

CE
100ms

5-8927

Figure II. Set-up Waveforms

STANDARD

100pF

I
5-8928

Figure 12. EPROM Programmer
Interface Board

137

EPROM Mode (Continued)

Autoprogramming. This mode permits
programming one byte of the onechip Eprom
during normal microcomputer program
eXecutiOn. The instruction to be used is the
Load Constant LCD @RRI,R2 (operating
code D2).
This instruction allows the stc:lndard Z8 to
load the contents of the working register to
an external RAM memory allocated in the
program memory space, addressed by a
working register pc:lir. The Z86Ell uses this
instruction also to program the 4K bytes onchip Eprom.
Addressing one of the on-chip Eprom
bytes, using this instruction, the
programming oPeration takes place when an
high voltage level on the Vpp pin (12.5 V ,I::
300mV) is applied.
In this case, both the address and the data
memory are internally stored for the
necessary programming time, where the time
is defined by the execution of 1024 NOP
operations (I NOP operation = 12 clock
pulses). The programming time is contained
between Ims (12 MHz clock) and 12 ms
(I MHz clock).
As just mentioned, during this time, the
CPU is intE;lrnally forced to execute NOP
instructions (operating code FF), while a RET
instruction (operating code AF) is
automatically executed at thE;l E;lnd of
programming.
For a correct program, restart is necessary
to save the address of the Load Constant
(LDC) next instruction in the Stack. This can
bE;l done by loading into the Stack the return
address calling a Subroutine like follow,
where, to permit a correct return to the main
program, it is neCE;lssary to disable the
interrupt before LDC executioI!.
DI
CALL WRITE
EI

WRITE LOC @RRl,R2
RET

Programming Facility. The most flexible
way for on-chip Eprom programming is, as
138

we know, the use of a standard Epromprogrammer, selecting the Eprom-like
facility, c:lnd using an appropriate interface
board (Figure 12).
If, however, the planned operation is only
a particular memory loading into the one chip
Eprom, it is possible to perform this
operation in a much simpler way, using a
board which allows the Z86Ell to read and
load the renc:lmed particular memory, using
the autoloading procedure.
The software required for this operation is
stored in the Z86Ell Test-memory
(inaccessible). Figure 13 shows the
autoloading program flow-chart.
When the microcomputer is forced in Test
mode by applying a high voltage level
(~ 7 V) on the Reset pin, ports PO and PI
are configured as Address/Data to c:lccess the
external memories.
At this point, a test on port P2 is executed
to decide if the on-chip Eprom autoloading is
to be executed. This facility is accessed by
forcing the values 40H or 41H on port P2 to
execute, respectively, the Verify or
Autoloading routine.
Consequently, the registers required for
the operation are initialized, the data to be
COmpared or stored is read, and the routine
chosen is executed.
The Autoloading routine is an intelligent
programming which executes a number of
overwriting cycles equal to three times the
number of programming cycles required to
perform a correct byte programming (up to a
maximum of 25). In this way, the on-chip
Eprom programming time is optimized and
equal to 25 sec. with an 8 MHz clock.
The verify routine is simply a byte-byte
comparison betwE;len the external memory
and the on-chip Eprom.
A possible failure, whether in Autoloading
or Verify, produces a High 10gicallE;lvel
forced on P37. Similarly, when the operation
is finished, the pO;;itive conclu;;ion is
underlined, bringing P35 High. An
Autoloading/V erify Board diagram is shown
in Figure 14, where the Vpp line control is
necessary to not allow high voltage into the
device when it has not yet been supplied.

EPROM Mode (Continued)

AUTOLOADIVER:cIF-,Y_--,-==<

'---r--~

(NO EFFECT
IN VERIFY)

YES

5-8929

Figure 13. Autoloading Flow Chart

139

EPROM Mode (Continued)

POWER
SUPPLY

!12.5V' 0.3)

4.7K/l.
O.K. FLAG
ERROR FLAG
41H (AUTOLOADING)
4DH(VERIFV)

5- 8930

Figure 14. Autoloading/Verify Board

Memory Read-Out Protection. The
protection, once activated, blocks reading
memory content. Such reading can be
carried out in two ways:
1. Entering Test Mode you can execute an
external memory program which allows
the on-chip Eprom reading through LOAD
instructions execution.
2. Entering Eprom-like Mode, using the
Verify facility.
Programming the first protection bit blocks
reading in these two conditions (PROTA on
port Plo).
Another protection bit (PROTB on port
P07) can be activated when the Z86Ell is in
external memory configuration.
This protection prevents software

140

manipulation of the external memory from
who decides to read the on-chip memory
content for a complete understanding of the
user application board.
When the Z86Ell works in external memory
facility the ports PO and PI are configurated
as Address/Data bus, so that the external
memory instructions can be executed during
the normal microcomputer operation. These
instructions can be also an appropriate
routine able to pull out the all on-chip
memory content using LOAD instructions.
When the protection is activated, each
reading attempt of the internal memory
content, using LOAD instructions, is
vainificated because the data out will be
always "FF".

EPROM Mode (Continued)
In consequence this protection activation
inhibit the LOAD instructions execution from
external to internal memory. To overcome
this problem is necessary to call a "READ"
routine written in on on-chip memory space.
The protections are activated by
programming 2 non-volatile transistors
simply forcing 10 V for a time more than
100 ms on the desired pin, on condition that
the microcomputer is in Reset state, the
Clock signal is present and the EPM pin is
not set.
H a complete protection is desired, both
protections must be programmed.
A simple board diagram for read-out
protection activation is shown in Figure 15.

·5V

Vee
GND
XTAL 1

=

Z8GE11
XTAL2
RESET

EPM

.l.

PROTA

?

PROTS

5-8931

Figure 15. Read-out Protection
Activation Diagram

Instruction Set Notation
Addressing Modes. The following notation is

IMR

used to describe the addressing modes and
instruction operations as shown in the
instruction summary.

Assignment of a value is indicated by the
symbol "<--". For example,
dst <-- dst + src
indicates that the source data is added to the
destination data and the result is stored in
the destination location. The notation
"addr(n)" is used to refer to bit "n" of a
given location. For example,
dst (7)
refers to bit 7 of the destination operand.

IRR
Irr

X
DA
RA
1M

R

Indirect register pair or indirect workingregister pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only

IR

Indirect-register or indirect working-register

Ir

address
Indirect working-register address only
Register pair or working register pair address

RR

Flags. Control Register R252 contains the
following six flags:
C
Z
S

Symbols. The following symbols are used in

V

describing the instruction set.

D

dst

Destination location or contents
src
Source location or contents
cc
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)

Interrupt mask register (control register 251)

H

b7
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

bo

lei zIsIv IDIHIF21Fli

Fl} user flags
F2

Affected flags are indicated by:

o
*

x

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

141

Condition Codes

142

Value

Mneomonic

1000
0111
1111
0110
1110
1101
0101
0100
!lOa
0110
1110
1001
0001
1010
0010
1111
a III
1011
0011
0000

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning
Always ttile
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Uhsigned less than or equal
Never true

Flags Set
C= I
C=O
Z=1
Z=O
S=O
S=I
V=I
V=O
Z=I
Z=O
(S XOR V)=O
(S XOR V)= I
[Z OR (S XOR V)j=O
[2 OR (S XOR V)] = I
C=O
C= I
(C =0 AND 2=0) = I
(C OR 2)= I

Instruction Formats
ope

CCF, 01, EI, IRET, NOP,
ReF, RET, SCF

ope

dS!

INC r

One-Byte Instruction

ope

MODE

CLR, CPL, DA, DEC,

dstJsrc

OR

11

ope

I-----'~d.~,'---lOR 11

MODE

01 dst/arc I ~~;~'~~~R~~~:R,POP,

1 1 0

I

1 1 1 0
1 1 1 0

lD, OR. S8C. SUB,
TeM, TM, XOA

d.,

JP, CALL (Indlrac.')

dat

ope

MODE

dll

ope

ADe, ADD, AND, CP,

OR
OR

d.,

RRC, 5RA, SWAP

I

ope

1 1

OR

It

I 1

01

d.,

VALUE

SRP

ADe, ADD, AND, CP,
LO, OR, sac, SU8,
TeM, TM, XOR

VALUE
MODE

ope

MODE

ADC, ADD, AND,

CP, OR.

dll

MODE

ope
sreldlt

dsU,'e

ope

sreldat

lope

lO, lOE, LOEI.
LOC, LOCI

1 1 1 0
1 1 1 0

ds!

dellceR~ ope

MODE

ope

LD

dsllsrc
ADDRESS

OR

11

1 1

01

LD

ope

JP

DA,
DA,
LO

VALUE

I

LD
OR
OR

TeM, TM, XOR

datl.re

dat

sac, SUB.

ope

dsl

ope
OJNZ,JR

CAL.L

DA,
OA,

Two-Byte instruction

Three-Byte instruction

Figure 16_ Instruction Formats

143

, Instruction Summary
Opcode Flo". Affected
Byte
(Hex~ CZSVDH

Instruction
and Operation

Addr Mode

ADC dsLsrc I
dst-dst+src+C

(Note I)

ID

.. .. 0 '*

ADD dst,src

(Note I)

00

.. .. • .. 0 '*

(Note I)

50

- '* * 0 - -

DA
SP-SP-2
IRR
@SP - PC; PC - dst

D6

------

CCF

EF

det

He

Instruction
and Operation

LD dst,src
dst - src

dst - dst + src
AND dst,src

dst - dst AND src
CALL dst

D4

C - NOT C
CLR dst

dst - 0
COM dst

.- - - -

-

DA dst

dst - DA dst
DEC dst

dst-dst-I
DECW dst

dst - dst _. I

00
01

RR
IR

80
81

-

-

...- -

...- -

r
Irr

Irr

82
92

------

Ir
dst - src
Irr
r - r + 1; rr - rr + 1

Irr
Ir

83
93

------

IMR (7) - 0
RA

r - r- I
if n. 0
, _PC - PC + dst
~:ange: + 127, -128

LDEI dst,src

NOP

8F

------

rA
r=O-F

------

pop dst
dst - @SP
SP-SP+I

CF

0-- - - -

AF

------

~I~

90
91

'* '* '* ... - -

RLC dst

~I~

10
II

'* '* .. '* - -

RR dst

Lm~I~
i.m--E:::3-l
R
, , • IR

EO
EI

rE
r=O-F
20
21

- .. '* '* - -

RL dst

R
IR
RR
IR

AO
Al

- '* '" '* - -

BF
FLAGS - @SP; SP - SP + I
PC -' @SP; SP - SP + 2; IMR (7) - I

• '* '* ... • ..

JP cc,dst

cD
c=O-F
30

------

cB
c=O-F

------

dst-dst+1

IRET

DA

if cc is true
PC - dst

IRR

JR cc,dst

RA

144

R
IR

C-O

INC dst

PC-PC+dst
Range: + 127, -128

50
51
------

RET

I

R
IR

• 0 - -

70
71

------

if cc is true

40

PUSH src
SP-SP-I; @SP- src

9F

dst - dst +

(Note I)

RCF

IMR(7) - I

INCW dst

FF

OR dst,src

dst - dst OR src

DI

DJNZ r,dst

LDE dst,src
dst - src

'* X - -

R
IR

R

------

LDCI dst,src

40
41

1m
1m

C3
D3

0--

R
IR

X
r
Ir
r
R
IR

------

Irr
Ir

60
61
AD

r
X
r
Ir
R
R
R
IR
IR

rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5

Ir
dst - src
Irr
r-r+l; rr-rr+l

R

(Note I)

R

------

dst - src

dst - src

1m
r
R

Opcode Flags Affected
Byte
(Hex)
CZSVDH

C2
D2

------

CP dst,src

HC

Irr

BO
BI

IR

det

r
Irr

LDC dst,src

R
IR

dst - NOT dst

Addr Mode

PC-@SP; SP- SP + 2

RRC dst

SBC dst,src

(Note I)

CO
CI
30

dst - dst-src-C
SCF

• I

.

DF

I - - - - -

DO
DI

• '* '* 0 - -

C - I
SRA dst

4ri @l IRR

Instruction Summary (Continued)
IlIIIlructlon
and Operation

Addr Mode
dot

SRP src
RP - src
SUB dst,src
dst - dst - src

He:
1m

(Note 1)

SWAPdst~ R

IR

Ope:ode Flag" Allee:ted
Brte
(Hex)
CZSVDH
31

20
FO
Fl

•• 1

.

x**x--

Instruction
and Operalion

Addr Mode
dot

(Note 1)

60

- * .. 0

TM dst, src
dst AND src

(Note 1)

70

-

XOR dst,src
dst - dst XOR src

(Note 1)

BO

-**0--

dst

are

R
R
R
IR

Ir
R
IR
1M
1M

* .. 0

Lower
Opeode Nibble

rn

Note 1
These instructions have an identical set 01 addressing

Ope:ode Flail" Allee:ted
Brte
(Hex)
CZSVDH

TeM dst,src
(NOT dst) AND src

Addr Mode

modes, which are encoded for brevity. The hrst opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, the opcode of an ADC instruction using
the addressing modes r (destination) and Ir (source) is 13.

He

[l]
[i]
~

I!l
ill

145

Registers
R240 SIO
Serial I/O Register

R244 TO
Counter/Timer 0 Register

(FOH: Read/Write)

(F4H: Read/Write)

1~1~I~i~I~I~I~I~1

10, I0.1 0.1 0.1 0,1 0,1 0.10.1

I...- - - - S E R I A L DATA (Do '" LSB)

To INITIAL VALUE (WHEN WRITTEN)
'-----IRANGE: 1 256 DECIMAL 01-00 HEX)
To CURRENT vALUE (WHEN READ)

R245 PREO
Prescaler 0 Register

R241 TMR
Timer Mode Register

(F5H: Write Only)

(FIH: Read/Write)

NOT To",
useDMODES
= 00

: ~ri
INTERNAL CLoCK OUT = 11
io

g~i

j

l~t~I~I~I~I~I~I~1

lS~o

NO FUNCTlO"
1 =
::;: LOAD
To

0 '" DISABLE To COUNT
1 :;: ENABLE To COUNT

T MODES
EXTERNAL CLOCK IN~~T = 00
GATE INPUT:" 01

(NON.A~~~~g~:~~:~~) =

~L

SINGLE·pASS

1 - To MODUL().N

RESERVED (MUST BE 0)

0 '" NO FUNCTION
1 '" LOAD T,
0 ;; DISABLE TI COUNT

10

COUNTMO.E
OaT0

PRESCALER MODULO
(RANGE: 1 ~84 DECIMAL
o1-Ob HEX)

1 '" ENABLE T 1 COUNT

TRIGGER INPUT = 11
CAETRIGGERABLE)

R246 P2M
Port 2 Mode Register

R242 TI
Counter Timer 1 Register
(F2H: ReadlWrite)

(F6H: Write Only)

10,10.10.10.10,10,10.10,1

(ii;Jii;Jii; Iii. t0, I0, I0, I0.1
P20-P27 1/0 DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

1, INITIAL VALUE (WHEN WRITTEN,
'------IRANGE 1 256 DECIMAL 01 00 HEX)
T. CURRENT VALUE (WHEN READ)

R243 PREI
Prescaler 1 Register

R247 P3M
Port 3 Mode Register

(F3 H : Write Only)

(F7H: Write Only)

1~I~i~I~I~I~I~I~1

~L

[gE

I~I~I~I~I~I~I~I~I

COUNTMOoE
o :: T, SINGLE·PASS
1 :: T, MODULO·N

CLOCK SOURCE:

1

o

1, INTERNAL
1, EXTERNAL TIMING INPUT
(T'N) MODE

LD

PORT 'PULL·UPS OPEN .RAIN.

1 PORT 2 PUlL·UPS ACTIVF
RESERvED (MUST BE 0)

o P:Ii ::

I)

INPUT

P33 '" INPUT

P34 = OUTPUT

~~}

PRESCALER MODULO
(RANGE:. 1-64 DECIMAL
01-00 HEX)

P33 = INPUT
P34 = OM
1 1 P3s = DAYi/RDY1 P34 = RDY1/DAV1

'---------

o P31

:: INPUT (T.,.) P3e = OUTPUT {TOUT)
1 P31 = i5lV2IfiDY2 P3e '" RDV2IfiAY2

~ ~= ~ ~Ne':_~!L IN ::~ ~ ~~~~~TOUT

'--________ ~ ~:::~ g~f=
Figura 17. Control Registeni

146

P35 '" OUTPUT

1 P3z '" DAVOIRDYO P35 '" RDTOIaAVti

0

•
~~~

,

'"

:~"cL~

~

Z"'

c

"~,

%

",,,

=

,

_=

;,

"~~~

"

'

,

"

'

"

~

'1'

If

'Ii
""

'

Registers (Continued)
R248 POIM
Port 0 and 1 Mode Register

R252 FLAGS
Flag Register

(F8H; Write Only)

(FC H; Read/Write)

PO,_PO, MODE:]

= 00

OUTPUT

INPUT::: 01
A12 .A'5 = lX

EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED

=1

~

I

U~~

--rL PO,-PO,= MODE

00
OUTPUT
01 = INPUT

LUSE"FLAGF1

LUSER FLAG F2

1X '" A8 "A 11
STACK SELECTION
= EXTERNAL

o

1 = INTERNAL

·"?

HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG

P1 o
MODE
00 = BYTE OUTPUT

ZERO FLAG

01 = BVTE INPUT

CARRY FLAG

10 ::: ADD-AD,
11 '" HIGH·IMPEDANCE AOO-",,07,

is, Os, AIW. AI-A1'. AI .. Al_
IF SELECTED

R249IPR
Interrupt Priority Register

R253 RP
Register Pointer

(F9H; Write Only)

(FDH; Read/Write)

I I III ,~. ""-""-

I~I~I~I~I~I~I~I~I
RESERYE.D(MU
. . • •A)
•
IR03, lAOS
PRIORITY (GROUP
o = IR05 > IRQ3
1 = IRQ3 > IAQS

~

RESERVED = 000
C > A > B = 001
A > B > C = 010
A > C
B = 011

C=DON'T CARE

RE.GISTER
POINTER

~>C>A=l00

c > B > A "" 101
B > A > C = 110
RESERVED", 111

IRoo, IRQ2 PRIORITY (GROUP BI
o = IR02 > IRoO
1 = IRoo > IRQ2
IRQ1, IRQ4 PRIORITY (GROUP C;)

o '"

IRQl > IRQ4

1 = IRQ4 > IAQl

R250 mQ
Interrupt Request Register

R254 SHP
Stack Pointer

(FAH; ReadlWrite)

(FE H; Read/Write)

RESERVED (MUST BE

O)T

c-== I~QO =

P" INPUT (Do

= '"001

IR01 = P:i3 INPUT
IRQ2 = P3, INPUT
IRQ3 "" P30 INPUT. SERIAL INPUT
IRQ4 = To. SERIAL OUTPUT
IRQ$ = T,

R2511MR
Interrupt Mask Register

R255 SPL
Stack Pointer

(FBH; Read/Write)

(FF H ; Read/Write)

l~i~[~i~i~I~I~I~1

l~t~I~I~I~I~t~I~1

II

c-==

1 ENABLES IRoo-IAOS

.
(0, = 111001
L--_ _ _ _ _ _ RESERVED ("!lUST liSE 0)

L--_ _ _ _ _ _ _ _ 1 E,...ABI,ES INTERRUPTS

Figure 17. Control Registers (Continued)

147

II

.
Lower Nibble (Hexl

Opcode Map

6,5

6,5

DEC

DEC

H,

IH,

6,5

ADD

ADD

II, Ira

Ra,Rl

IRa,HI

81, IM

6,5

10,5

10,5

10-;-5

RLC

ADC
n,la

10,5

SUB

SUB

Il,lra

8a,RI

6,5

10,5

10,5

10,5

IR

LO

IP

INC

ee, RA

rl, IM

cc,DA

"

SUB

SUB

81,IM

IHI/IM

6,1

6,5

JP

SRP

SBC

SBC

SBC

SBC

1M

SBC

11,112

Ha,Rl

IRa,Rl

SBC

Il,Ia

RI,IN

IBI,IM

10,5

10,5

10,5

10,5

OR

OR

OR

IR2.Hl

R1,IM

OR

Ba,RI

8,5

8,5

OA

OA

H,

lR,

6,5

OR
11,12

6,5

6,5

OR

n,IIa

10,5

10,5

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

pop

H,

AND

AND

AND

AND

IR,

AND

AND

II,ra

Il,lra

Ha,R1

IRa,Rl

6,5

6,5

6,5

6,5

10,5

10,5

10,5

IRI/IM
10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

~
.....!I
:9

n,lta

Ra,Rl

IRa,Rl

HI,IM

IRI,IM

10/12,1 12114,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH PUSH

TM

TM

TM

TN

n,lra

Ra,Rl

TM

TM

IRa,HI

HI/1M

IRl,IM

&
::>

R,

II

R,

lR,

11,Ia

10,5

10,5

12,0

18,0

LOE!

RR,

lR,

rl,Iu2

Irl,lru

6,5

6,5

12,0

18,0

RL

'ilL

LOE

LOE!

10,5

B

0

E
F

Byte. per
InetrudloD.

IR,

10,5

INCW INCW

6,5

6,5

E!
10,5

10,5

10,5

CP

CP

CP

CP

CP

Ra,RI

IRa, HI

HI,IM

IRl,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

IR,

XOR

XOR

Il,Ia

n,lra

82.81

IRa,HI

HI,IM

IRl,IM

6,5

6,5

12,0

18,0

10,5

RRC

RRC

toe

LOCI

LO

II, lIra III/Ina

6,5

6,5

12,0

18,0

8RA

toe

LOCI CALL·

6,5

6,5

Ira, 1111
6,5

20,0

IRR,

10.5

20,0

10,5

CALL

LO

DA

la,x,RI

10,5

10,5

RR

LO

R,

IR,

LO

LO

LO

LO

rJ,IRa

Ra.RI

IRa.RI

RI,IM

IRI.IM

8,5

8,5

R,

IRI·

6,5

16,0

IRET

I-6,5

RCF

I-6,5

SCF

I-6,5

CCF

I--

10,5

6,0

LO

LO

Ill. fa

Ra,IRI

"-----v--"---""';

RET
I--

10,5

RR

SWAP SWAP

14,0

II, X, Hz

SRA

12,III}

I--

10,5

11,112

IR,

I--

6,1

CP

R,

I--

Ia,bII In,hII

II,Ia

lR,

I--

01
I--

IR,

H,

f--

6,1

RH,

R,

C

Il,ra

OECW OECW LOE

R,

A

IR,

f--

IRl,IM

10,5

HI,IM

I--

10,5

pop

f--

r----

10,5

SUB
IRa,R,

8,0
IRRI

6,5

OINZ

ADC

F

E

12/10,0

f1.RA

IRI,IM

6,5

6,5

LO

ADC

Il,Ia

o

C

t2,RI

HI,IM

SUB

B
12/10,0

LO

ADC

6,5

A
12/10,5

r1.R2

IRz.HI

INC

6,5

ADD

Ra.Rl

6,5

6,5

lRl,IM

t---to;s

ADC ADC
Il,Ira

INC

IH,

10,5

6,5

RLC

H,

10,5

fl,la

6,5

IH,

10,5

ADD ADD ADD

6,5

H,

6,5

v-..---..~

I.
....- - -..

NOP

\.,-----v-~-----,;

--...- -.-

Lower
Opcode

Nlbbl•
Execution
Cyel..
Upper
Opcode-A
NIbble

•

PIpelIne
Cycl..
Mnemonic

Legend:
R :: a-Bit Address
r = 4-Bit Address
RI or n = Dst Address
R2 or r2 "" Src Address

SequOlllCe:

Fifol

Operand
·2·byte Instruction; fetch cycle appears as a 3·byte instruction

148

Second
Operand

Opcode. First Operand. Second Operand
Note: The blank areas are not defined..

Absolute Maximum Ratings
Voltages on all pins
with respect to GND ........ -0.3 V to+7.0 V
Operating Ambient
Temperature ....................... O°C to + 70°C
Storage Temperature ....... -65°C to+ 150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; operation of the device at any condition
above those indicated in the operational sections of these
specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the
reference pin. Standard conditions are as
follows:

o
o
o

+4.75 V :s; Vee :s; +5.25 V
GND=O V
O°C :s; TA :s; +70°C

+5V

+5Y

+5V

+5Y
1.Sk

2.1K

1.Sk

18K

74LS04

74LS04

CL,~CK --~-t::~-~""'-l>I>o---4-~,--

1

XTAL2

I

CL

= 15pF MAX

L-_ _ _ _.,...._ XTALI

1
I

I

CL = 15pF MAX

Figure lB. Tast Load I

Figure 19. Test Load 2

Figure 20. External Clock Interface Circuit

149

--.,._---------------------

DC Characteristics
Symbol

Parameter

VeH

Clock Input High Voltage

VeL

Clock Input Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

VRH

Reset Input High Voltage

VRL

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

Min

Max

3.8

Vee

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

2.0

Vee

V

-0.3

0.8

V

Vee

V

0.8

V

3.8
-0.3

V

IOH= -250

p.A

0.4

V

IOL= +2.0

rnA

p.A
p.A

o Vo5
o V"5

Vee = +5.25 V, VRL=O V

Power Down Mode

2.4

IlL

Input Leakage

-10

10

-10

10

IOL

Output Leakage

1m

Reset Input Current

-50

lee

Vee Supply Current

120

p.A
rnA

IMM

VMM Supply Current

10

rnA

VMM

Backup Supply Voltage

Vee

V

150

Condition

Unit

3

VIN

$

+ 5.25 V

VIN "5 +5.25 V

Power Down

External I/O or Memory Read and Write Timing
Z86Ell
No

Symbol

Min

Paramter

TdA(AS)
Address Valid to AS i Delay
TdAS(A)
AS i to Address Float Dealy
2
TdAS(DR)
AS i to Read Data Required Valid
3
4
TwAS
AS Low Width
TdAz(DS)
Address Float to DS L
5
6-TwDSR---DS (Read) Low Width
DS (Write) Low Width
7
TwDSW
DS L to Read Data Required Valid
TdDSR(DR)
8
ThDR(DS)
Read Data to DS i Hold Time
9
TdDS(A)
DS i to Address Active Delay
10
TdDS(AS)
DS i to AS L Delay
11
12-TdRIW(AS)--RiW Valid to AS i Delay
TdDS(RIW)
DS i to R/W Not Valid
13
TdDW(DSW) Write Data Valid to DS (Write) L Delay
14
TdDS(DW)
DS i to Write Data Not Valid Delay
15
TdA(DR)
Address Valid to Read Data Required Valid
16
TdAS(DS)
AS i to DS L Delay
17
NOTES:
!. Test Load I
2. Timing numbers given are for minimum TpC.

3. Also see clock cycle time dependent characteristics table.
4. When using extended memory timing add 2 TpC.

Max

50
70

Z86EllA
Min
Max Notes*t

35
45
360

220
55
0
185
110

80
0
250
160
200

0
45
55
30
35
35
45

0
70
70
50
60
50
70
410
80

55

1,2,3
1,2,3
1,2,3.4
1,2,3

l.2;,3.4
l,p.4
130 ).,2,3.4
1
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
255 1,2,3.4
1,2,3

5. All timing references use 2.0 V for a logic "1" and 0.8 V for
a logic "0".
* All units in nanoseconds (ns).
t Timings are preliminary and subject to change.

PORT O.

Dliii

PORT 1

iii

_____-+-___-.1.. 1--------<0>-----.1 10_ _+-__

(R~~D)

PORT 1

Ao-A7

iii
(WRITE)

Figure 21. External I/O or MEoD1ory Read/Write

151

Additional Timing Table
Z86Ell
No

Symbol

Paramter

TpC
Input Clock Period
I
TrC, TIC
Clock Input Rise And Fall Times
2
Input Clock Width
3
TwC
4
TwTinL
Timer Input Low Width
5--TwTinH---Timer Input High Width
TpTin
Timer Input Period
6
TrTin, TfTin
Timer Input Rise And Fall Times
7
TwIL
Interrupt Request Input Low Time
8a
8b
TwIL
Interrupt Request Input Low Time
Interrupt Request Input High Time
9
TwIH
NOTES:
1. Clock timing references uses 3.8 V for a logic "I" and 0.8 V
for a logic "0".

2. Timing reference uses 2.0 V for a logic "I" and 0.8 V for a
logic "0",

Min

Max

125

1000
25

83

100
100
3TpC
3TpC

1000
15

26
70
3TpC
8TpC

37
100
3TpC
8TpC

100
70
3TpC
3TpC

3. Interrupt request via Port 3 (P3j-P33).
4. Interrupt request via Port :.J (P:.JO).
• Units in nanoseconds (ns).
t Timings are preliminary and subject to change.

Figure 22. Additional Timing

152

Z86EllA
Min
Max Notes*t

2
2
2
2
2,3
2,3
2,3

Handshake Timing
Z86Ell
No

Paramter

Symbol

Min

TsDI(DAV)
Data In Setup Time
ThDI(DAV)
Data In Hold Time
2
Data Available Width
3
TwDAV
TdDAVIf(RDY)
DAV l Input to RDY l Delay
4
5-TdDAVOf(RDY)-DAV l Output to RDY l Delay
TdDAVIr(RDY)
DAV i Input to RDY i Delay
6
TdDAVOr(RDY)
DA V i Output to RDY i Delay
7
TdDO(DAV)
Data Out to DAV l Delay
8
Rdy l Input to DAV i Delay
TdRDY(DAV)
9

Max

Z86EllA
Min
Max Notes*t
0
160
120

0
230
175

120

175
0

0
120

175
0
50
0

200

0
30
0

1,2
1,3
1,2
1,3
1

140

NOTES:

4. All timing regerences use 2.0 V for a logic "I" and 0.8 V for

I. Test Load I
2. Input handshake
3. Output handshake

a logic "0",
" Units in nanoseconds (ns),
t Timings are preliminary and subject to change.

DATA IN

DAV
(INPUT)

RDY
(OUTPUT)

Figure 23a. Input Handshake

DATA OUT

x---

DATA OUT VALID

---~----------------DAY
(OUTPUTI

RDY

-~)~®~ij~F;=

(INPUT)

Figure 23b. Output Handshake

153

Clock-Cycle-Time-Dependent Characteristics
Symbol

Number

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdR/W(AS)
TdDS(RIW)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

2
3
4
6
7
8
10
II

12
13
14
15
16
17
*

Z86Ell
Equation

Z86EllA
Equation

TpC-75
TpC-55
4TpC-140'
TpC-45
3TpC-125'
2TpC-90'
3TpC-175'
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215'
TpC-45

TpC-50
TpC-40
4TpC-llO'
TpC-30
3TpC-65,
2TpC-55'
3TpC-120'
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160'
TpC-30

Add 2TpC when using extended memory timing.

Ordering Information
Type

Package

Temp.

Clock

Dl
D6

Ceramic

Ceramic

01 +70°C
-40/+85°C

8 MHz

Z86EllA DI
Z86EIIA D6

Ceramic
Ceramic

01 + 70°C
-401 + 85°C

12 MHz

Z86EIl
Z86EII

154

Description
4K EPROM Microcomputer

II.

Preliminary Data

Z8 8K EPROM Microcomputer
• Complete microcomputer, 4K bytes of
EPROM, 240 bytes of RAMm 32 I/O lines,
and up to 56K bytes addressable external
space each for program and data
memory. Fully compatible with standard
ROM version.
• 256-byte register file, including 236
general-registers, four I/O port registers,
and 16 status and control registers.
• Minimum instruction execution time 1 /lS
at 12 MHz.
• Vectored priority interrupts for I/O,
counter/timers, and DART.
• Full-duplex DART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.
• Register Pointer so that short, fast
instructions can access any of nine
working-register groups in 1.5 /lS (8MHz).

• On-chip oscillator which accepts crystal
or external clock drive.
• Low-power standby option which retains
contents of general-purpose registers.
•

Single + 5 V power supply - all pins TTL
compatible.

• Two Eprom programming modes:
Eprom-like, using a standard Eprom
programmer,
Autoprogram, self-programming during
normal program execution.
An on-chip ROM provides a Program/
Verify facility to allow a simple and
time-efficient self-program operation.
• Integrated programmable protection
avoids EPROM content read-out.
• Available in 8 and 12 MHz versions.

P3 6

TIMING

AND
CONTROL

RESET

Vee

VMM 'XTAL2

I

39

P3,

RfW

GNO

XfALI
P3,

J

3.

P2,

37

P2 6

os

XTAl1

AS

V MM 'XTAL2

P' ,
PI J
P1 4

PORT 0

II0orAB-AIIS
(NIBBLE
PROGRAMMABLE)
AO":A7 EPROM MODE

PORT 1
lIOorA/DO-A/D,
(BYTE
PROGRAMMABLE)

°0.:,°,

EPROM MODE

Z86E21

P1 6
PI,

P'O

P'O

P',

P' ,

P'l

P'l

P'3

P',

P"

P'4

P',

P',

P'6
P',

p'.
P',

36 P2 5

OS
AS

,
,•

P35

'0

GNO

"

RESET
RfW
PORT 2
l!O(Bll PRGGRAMMABLE)

A8.;.A" EPROM MODE

PI,

PO,

,

P3.

PI O
PI,

POD

P0 6

CLOCK
CLOCK or
STANDBY BATTERY

[PM/P32

Z86E21

11

35

P2,

34

P2) /A ll

33

P2 2'A 1O

31

P2,/A g

31

P20/AS

30

P3 3 ,Vpp

19

P3 4 'CE

I.

P',IO,

21

PI6/°e.

15

16

PiS/OS

'6

15
14

PI3/D)

A SiPOS

,.

PI,.'°4

17

13

PlllaZ

A 6' P06

19

II

Pi"a,

PROTB/A,1 Po,

10

11

PIOIOO'PROTA

'0'''%
A,'PO,
PORT 3
SERIAL AND

AZ/POZ

PARALLEL 110

A) /P03
A 4, P04

AND CONTROL
(FOR INPUT;
FOR OUTPUT)
EPROM MODE
SELECTIONS

S·9005

13
14

,

S-9006

Figure 1. Logic Functions

Figure 2. Pin Configuration

155
- - - - ---------

General Description

The Z86E21 microcomputer is an EPROM
member of the Z8 family; completely
developed by SGS, it maintains the
sophisticated architecture and full
compatibility with the currently available
ROM-based units.
i It can be configured as a stand-alone
: microcomputer with 8K bytes of internal
EPROM, or as a traditional microcomputer
, that manages up to 112K bytes of external
· memory, or as a parallel-processing element
; in a system with other processors and
peripheral controllers.
The 8K x 8 on-board EPROM can be
· programmed in two modes, Eprom-like and
Autoprogram. In Eprom-like, the
programming procedure is similar to that for

a M2764, with the only exception being for
the programming voltage which must be 12.5
V related to the SGS NMOS-E3 used
technology. Autoprogram permits byteprogramming during normal microcomputer
program execution.
An important faCility is the programmable
read-out protections which allow the user to
inhibit external access to proprietory
program code by programming 2 nonvolatile transistors. These locks can be reset
only by erasing the entire EPROM array.
For its characteristics, the Z86E21 can be
considered as a low cost development tool
for the Z8 microcomputer family.

Architecture

Z86E21 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
, applications.
Microcomputer applications demand
powerful I/O capabilities. The Z86E21 fulfills
this with 32 pins dedicated to input/output.
These lines are grouped into four ports of
· eight lines each and are configurable under
software control to provide timing, status
signals, serial or parallel I/O with or without
, handshake, address/data bus for interfacing
external memory, and address, data and
selections in EPROM mode.
Because the multiplexed address/data bus
is merged with the I/O-oriented ports, the
, Z86E21 can assume many different memory
and I/O configurations. These configurations
, range from a self-contained microcomputer
to a microprocessor that can address 112K
bytes of external memory (Figure 3).
Three basic address spaces are available to
· support this wide range of configurations:
program memory (internal and external),
data memory (external) and the register file

156

(internal). The 256-byte random-access
register file is composed of 236 generalpurpose registers, four I/O port registers,
and 16 control and status registers.
To unburden the program from coping
with real-time problems such as serial data
communication and counting/timing, an
asynchronous receiver/transmitter (UART)
and two counter/timers with a large number
of user-selectable modes are offered on-chip.
Hardware support for the UART is minimized
because one of the on-chip timers supplies
the bit rate.
An autoprogram logic permits Eprom byteprogramming during the normal
microcomputer program execution, using the
STORE constant isntruction.
This permits the microcomputer to look at
the contents of the working register's register
for an external RAM allocated to the
program memory space, addressed using two
of the register file registers. The renamed
external RAM was expressly developed for
the Autoprogram function, thus it is
externally inaccessible.

Architecture (Continued)
XTAl

AS

os:

RiVi

RESET

Vee GNO

UART

TIMERI
COUNTERS (2)

INTERRUPT
CONTROL

AS ~AI1
(EPROM MODE)

(BIT PROGRAMMABLE)

AOORESSIDATA or lID
(BYTE PROGRAMMABLE)

AO-:- A,
(EPROM MODEl

5-9007

Figure 3. Block Diagram

Pin Description
POO-P07' I/O Port Lines (input/outputs, TTL
compatible). 8 lines Nibble Programmable
that can be configured under program
control for I/O or external memory interface
and, Ao-A7 in EPROM mode. P07 can be
configured as Read-out protection in memory
expansion mode (PROTB), applying a high
voltage level (10 V)
P1o-P17' I/O Port Lines (input/outputs, TTL
compatible). 8 lines Byte Programmable that
can be configured under program control for
I/O or multiplexed address (Ao-A7) and data
(Do-D7) lines used to interface with
program/data memory, and 00-07 in EPROM
mode. Plo can be configured as Read-out

protection in Testing-mode and EPROMmode (PROTA), applying a high voltage
level (10 V).
P2o-P27' I/O Port Lines (input/outputs, TTL
compatible). 8 lines Bit Programmable where
the 4 less significant bits can be configured
as As-All in EPROM mode.
P30-P37' I/O Port Lines (TTL compatible) 4
lines input (P30-P33), 4 lines output P34-P37).
They can also be configured as control lines.
In EPROM mode: P32 becomes EPM (Epromlike) when a high voltage level (~ 7 V)
is applied, P33 becomes Vpp (12.5 V ±
300 m V), P34 becomes CE to perform
program enable/verify.

157

Pin Description (Continued)
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the
beginning of each machine cycle. Addresses
output via Port 1 for all external program or
data memory transfers are valid at the
trailing edge of AS. Under program control,
AS can be placed in the high-impedance
state along with ports 0 and 1, Data Strobe
and ReadlWrite.
OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

initializes the Z86E21. When RESET is
deactivated, program execution begins from
internal program location OOOCH.

R/W. Read/Write (output). R/W is Low when
the Z86E21 is writing to external program or
data memory.

XTALI. XTAL2. Crystal 1, Crystal 2 (timebase input and output). These pins connect a
series-resonant crystal (8 MHz maximum) or
an external single-phase clock (8 MHz
maximum) to the on-chip clock oscillator and
buffer.

RESET. Reset (input, active Low). RESET

Address Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 8192
bytes consist of on-chip EPROM. At
addresses 8192 and greater, the Z86E21
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These
locations contain six 16-bit vectors that
correspond to the six available interrupts.
Data Memory. The Z86E21 can address 56K
bytes of external data memory beginning at
locations 8192 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 256-byte register file
includes four I/O port registers (RO-R3), 236
general-purpose registers (R4-R127) and 16

158

control and status registers (R240-R255).
These registers are assigned the address
locations shown in Figure 6.
Z86E21 instructions can access registers
directly or indirectly with an 8-bit address
field. The Z86E21 also allows short 4-bit
register addressing using the Register
Pointer (one of the control registers). In the
4-bit mode, the register file is divided into
nine working-register groups, each
occupying 16 contiguous locations (Figure
7). The Register Pointer addresses the
starting location of the active workingregister group.

Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and
R255) is used for the external stack, which
can reside anywhere in data memory
between locations 8192 and 65535. An 8-bit
Stack Pointer (R255) is used for the internal
stack that resides within the 236 generalpurpose registers (R4-RI27).

Address Spaces (Continued)
655'5 ~----------,

5535
EXTERNAL
ROM OR RAM

192
191
ON-CHIP
EPROM

Locltion 01
11'11 byte 01

BASICI
)

DeBUG

Inllructlon

.tt" ..... , ~ ~------------

eXTERNAL

"Ruted

11

10

IROS

•
•
•5~
'I!'
,
7

In'lrrupt
"'ICIOI

(Low.r By'I'

'n'lrrupt
Vector

(V..-,Sy'e,

DATA
MEMORY

lAOS
IA04
IAQ4

IR03
IR03
IRQ2

::~~~--------------------i

IA02
IA01

2

IRQ1

1

IROO

0

IROO

NOT ADDRESSABLE

Figure 4_ Program Memory Map
LOCATION

IDENTIFIERS

255

STACK POINTER (BITS 7-0)

SPL

25'
253

STACK POINTER (BITS 15-8)

SPH

REGISTER POINTER
PROGRAM CONTROL FlAGS

FLAGS

251

INTERRUPT MASK REGISTER

1M"

250

INTERRUPT REQUEST REGISTER

IRQ

24.

INTERRUPT PRIORITY REGISTER

24.

PORTS 0-1 MODE

247

PORT 3 MODE

IPR

PORT 2 MODE

P'M
P2M

245

TO PRESCALER

PREO

244

TIMER/COUNTER 0

243
242

T1 PRESCAlEA
TIMER MODE

SERIAL 110

-

PRE1
T1

TMR
SIO

(
(
(

pORl3

P3

PORT 2

P2

Figure 6_ The Register File

127

TO

GENERAL· PURPOSE
REGISTERS

PORT 0

~------------------..I2~
TIM! up~, nibble 01 the regilt., me _dc!,e ..
ptO¥lded b, 1"- regllte' ~nl., 1!'Klf...
tIM .cllve woritl"'ll-.et'''e. g.oup.

P01M

24.

TIMER/COUNTER 1

r-_--~-r(-~~_:_:~:~j~:~:_:~:_:_;~:_:_:_:_~_:_:_:~:_:_!::

RP

252

241
240
239

Figure 5_ Data Memory Map

PO

SPECIFIED WORKING·
REGISTER GROUP

The 10.-••
nlbbl. of
"",.gll'.,
lIIe

- .......

.,

_delre"

the InelrucUon

points 101M

'fMClt....
fIIIl,t.,

1

t----"OPORTs----- ,
0

Figure 7_ The Register Pointer

159

"Serial Input/Output
Port 3 lines P30 and P37 can be
programmed as serial I/O lines for fullduplex serial asynchronous receiver/
transmitter operation. The bit rate is
controlled by Counter/Timer 0, with a
maximum rate of 62.5K bits/second.
The Z86E21 automatically adds a start bit
and two stop bits to transmitted data (Figure
8). Odd parity is also available as an option.
Eight data bits are always transmitted,

regardless of parity selection. If parity is
enabled, the eighth bit is the odd parity bit.
An interrupt request (lRQ4) is generated on
all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by
a parity error flag. Received characters
generate the IRQ3 interrupt request.

Transmitted Data

Received Data

(No Parity)

(No Parity)

1~I~t~I~I~I~I~t~t~tnl
LSTART 81T
' - - - - - - - E I G H T DATA 81TS

TWO STOP BITS

I

LSTAAT BIT
' - - - - - - E I G H T DATA BITS

L.- - - - - - - - - - O N E STOP 81T

Transmitted Data

Received Data

(With Parity)

(With Parity)

l~tpl~l~t~l~t~l~t~lnl

I~I~I pl~l~t~t~t~t~t~tnl

TI
.

,'------.

_ L S ' A " ' BIT
SEVEN OAT A BITS
000 PARITY
TWO STOP BITS

II
.

L
.

LSTART 81T
_ _ _ _ _ _ _ _ _ SEVEN DATA BITS

PARITY ERROR FlAG

' - - - - - - - - - - - O N E STOP BIT

Figure 8. Serial Data Formats

Counter /Timers
The Z86E21 contains two 8-bit
programmable counter/timers (To and Tl),
each driven by its own 6-bit programmable
prescaler. The Tl prescaler can be driven by
internal ox external clock sources; however,
the To prescaler is driven by the internal
clock only.
The 6-bit prescaler can divide the input
frequency of the clock source by any number
from 1 to 64. Each prescaler drives its
counter, which decrements the value (1 to
256) that has been loaded into the counter.
When the counter reaches the end of count,
a timer interrupt request-IRQ4 (To) or IRQ5
(T I )-is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be
programmed to stop upon reaching zero
(single-pass mode) or to automatically reload
160

the initial value and continue counting
(modulo-n continuous mode). The counters,
but not the prescalers, can be read any time
without disturbing their value or count
mode.
The clock source for T I is user-definable
and can be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (I MHz
maximum), a trigger input that can be
retriggerable or non-retriggerable, or as a
gate input for the internal clock. The
counter/timers can be programmably
cascated by connecting the To output to the
input of T I. Port 3 line P36 also serves as a
timer output (TOUT) through which To, TI or
the internal clock can be output.

1/0 Ports
The Z86E21 has 32 lines dedicated to input
and output. These lines are grouped into
four ports of eight lines each and are
configurable as input, output or address/
data. Under software control, the ports can
be programmed to provide address outputs,
timing, status signals, serial I/O, and parallel
I/O with or without handshake. All ports
have active pull-ups and pull-downs
compatible with TTL loads.
All the ports assume different configurations
in EPROM mode.
Port 1 can be programmed as a byte I/O
port or as an address/data port for
interfacing external memory. When used as
an I/O port, Port 1 may be placed under
handshake control. In this configuration, Port
3 lines P33 and P34 are used as the
handshake contoIs RDY] and DAV] (Ready
and Data Available).
Memory locations greater than 4096 are
referenced through Port 1. To interface
external memory, Port 1 must be
programmed for the multiplexed Address/
Data mode. If more than 256 external
locations are required, Port 0 must output
the additional lines.
Port 1 can be placed in the highimpedance state along with Port 0, AS, DS
and R/W, allowing the Z86E21 to share
common resources in multiprocessor and
DMA applications. Data transfers can be
controlled by assigning P33 as a Bus
Acknowledge input and P34 as a Bus
Request output.

~

PORT1

1/0 or ADo-AD,

lines P32 and P35 are used as the handshake
controls DAVo and RDYO. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0
can provide address bits As-All (lower
nibble) or As-A]5 (lower and upper nibble)
depending on the required address space. If
the address range requires 12 bits or less,
the upper nibble of Port 0 can be
programmed independently as I/O while the
lower nibble is used for addressing. When
Port 0 nibbles are defined as address bits,
they can be set to the high-impedance state
along with Port 1 and the control signals AS,
DS and R/W.

I

PORT 0

(110 OR A,-A,s»

Figure 9b. Pori 0

Port 2 bits can be programmed

independently as input or output. This port is
always available for I/O operations. In
addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this
configuration, Port 3 lines P3] and P36 are
used as the handshake controls lines DAV 2
and RDY2. The handshake signal assignment
for Port 3 lines P3] and P36 is dictated by
the direction (input or output) assigned to bit
7 of Port 2.

HANDSHAKE CONTROLS
} DAV, AND RDY,

('3, AND

'3~

Figure 9a. Pori 1

Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port 0 may be placed under handshake
control. In this configuration, Port 3 lines

PORT 2(00)

}

HANDSHAKE CONTROLS

IilVi AND ROY,
(P31 AND P3W

Figure 9c. Pori 2

161

I/O Ports (Continued)
Port 3 lines can be configured as I/O or
control lines. In either case, the direction of
the eight lines is fixed as four input (P30-P33)
and four output (P34-P37). For serial I/O,
lines P30 and P37 are programmed as serial
in and serial out respectively.
Port 3 can also provide the following
control functions: handshake for Ports 0,
and 2 (DA V and RDY); four external
interrupt request signals (IRQO-IRQ3); timer
input and output signals (TIN and TOUT) and
Data Memory Select (DM).

~RT3

(110 OR CONTROL)

Figure 9d. Port 3

Interrupts
The Z86E21 allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or individually enables or
disables the six interrupt requests. When
more than one interrupt is pending, priorities
are resolved by a programmable priority
encoder that is controlled by the Interrupt
Priority register.
All Z85E21 interrupts are vectored. When
an interrupt request is granted, and interrupt
machine cycle is entered. This disables all

subsequent interrupts, saves the Program
Counter and status flags, and branches to
the program memory vector location
reserved for that interrupt. This memory
location and the next byte contain the 16-bit
address of the interrupt service routine for
that particular interrupt request.
Polled interrupt systems are also
supported. To accommodate a polled
structure, any or all of the interrupt inputs
can be masked and the Interrupt Request
register polled to determine which of the
interrupt requests needs service.

Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to
a crystal or to any suitable external clock
source (XTALl == Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitors (Cl ~ 15 pF) from each pin to

152

ground. The speCifications for the crystal are
as follows:
• AT cut, series resonant
• Fundamental types, 8/12 MHz maximum.
• Series resistance, Rs ::; 100 Q.

Power Down Standby Option
The low-power standby mode allows power
to be removed (without losing the contents of
the 236 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input.
This necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 10 shows the recommended circuit for
a battery back-up supply system.

+5V

0-----_--1

Voo

TRICKLE

CHA.OE(r_'W'v_tc

ZB6E21

t--{>I---~--I ~':!)2

Figure 10. Recommended Driver Circuit
for Power Down Operation

EPROM Mode
Eprom-like programming. In this mode,
the microcomputer memory is programmed,
using a standard Eprom Programmer, with
the same procedure as for our M2764 (64K
EPROM). This has been made possible by
the following Z86E21 configuration, where
PIO-P17 are used as 8-bit I/O data (00-07),
POO-P07 and P20-P23 are used as 12-bit
Addresses (Ao-All); the microcomputer must
be in Reset state, forcing the related pin to
GND, and the clock must be active for the
complete operation.
Three other pins are available for that
purpose: the EPM pin on port P32, which
allows the microcomputer to recognize the
Eprom-like condition when a high voltage
(;;a. 7 V) is applied; the Vpp pin on port P33,
which is used to furnish programming
.
voltage fixed on 12.5 V ± 300mV; and the
CE pin on port P34, which is used to perform
program enable/verify.
For a correct microcomputer set-up the
Vee must be applied at least 100 ms before
the programming procedure starting (Figure
11).
A simple interface board, described in
Figure 12, allows programming to be carried
out through use of a standard Epromprogrammer.

elK

EPM

100ms

5-8927

Figure 11. Set-up Wc;lveforms

S-!ilOOB

Figurl!

12. EPROM Programmer
IntedClce Boqrd

1.63

EPROM Mode (Continued)

Autoprogramming. This mode permits
programming one byte of the on-chip Eprom
during normal microcomputer program
execution. The instruction to be used is the
Load Constant LCD @RR1,R2 (operating
code D2).
This instruction allows the standard Z8 to
load the contents of the working register to
an external RAM memory allocated in the
program memory space, addressed by a
working register pair. The Z86E21 uses this
instruction also to program the 4K bytes onchip Eprom.
Addressing one of the on-chip Eprom
bytes, using this instruction, the
programming operation takes place when an
high voltage level on the Vpp pin (12.5 V ±
300mV) is applied.
In this case, both the address and the data
memory are internally stored for the
necessary programming time, where the time
is defined by the execution of 1024 NOP
operations (1 NOP operation = 12 clock
pulses). The programming time is contained
between 1ms (12 MHz clock) and 12 ms
(1 MHz clock).
As just mentioned, during this time, the
CPU is internally forced to execute NOP
instructions (operating code FF), while a RET
instruction (operating code AF) is
automatically executed at the end of
programming.
For a correct program, restart is necessary
to save the address of the Load Constant
(LDC) next instruction in the Stack. This can
be done by loading into the Stack the return
address calling a Subroutine like follow,
where, to permit a correct return to the main
program, it is necessary to disable the
interrupt before LDC execution.
DI
CALL WRITE
EI
WRITE

LDC @RRl,R2
RET

Programming Facility. The most flexible
way for on-chip Eprom programming is, as
164

we know, the use of a standard Epromprogrammer, selecting the Eprom -like
facility, and using an appropriate interface
board (Figure 12).
If, however, the planned operation is only
a particular memory loading into the on-chip
Eprom, it is possible to perform this
operation in a much simpler way, using a
board which allows the Z86E21 to read and
load the renamed particular memory, using
the autoloading procedure.
The software required for this operation is
stored in the Z86E21 Test-memory
(inaccessible). Figure 13 shows the
autoloading program flow-chart.
When the microcomputer is forced in Test
mode by applying a high voltage level
(~ 7 V) on the Reset pin, ports PO and PI
are configured as Address/Data to access the
external memories.
At this point, a test on port P2 is executed
to decide if the on-chip Eprom autoloading is
to be executed. This facility is accessed by
forcing the values 40H or 41H on port P2 to
execute, respectively, the Verify or
Autoloading routine.
Consequently, the registers required for
the operation are initialized, the data to be
compared or stored is read, and the routine
chosen is executed.
The Autoloading routine is an intelligent
programming which executes a number of
overwriting cycles equal to three times the
number of programming cycles required to
perform a correct byte programming (up to a
maximum of 25). In this way, the on-chip
Eprom programming time is optimized and
equal to 25 sec. with an 8 MHz clock.
The verify routine is simply a byte-byte
comparison between the external memory
and the on-chip Eprom.
A possible failure, whether in Autoloading
or Verify, produces a High logical level
forced on P37. Similarly, when the operation
is finished, the positive conclusion is
underlined, bringing P35 High. An
Autoloading/Verify Board diagram is shown
in Figure 14, where the Vpp line control is
necessary to not allow high voltage into the
device when it has not yet been supplied.

EPROM Mode (Continued)

L-...;._,.----'

(NO EFFECT
IN VERIFY)

YES

5-8929

Figure 13. Autoloading Flow Chart

165
-----~~~~~----------

EPROM Mode (Continued)

POWER
SUPPLY
(12.5Vt 0.3)

lDK!l

Be17S

O.K. FLAG
P37

ERROR FLAG
41H (AUTOLOADING)
40H(VERIFV)

8-9009

Figure 14. Autoloading/Verifv Board

Memory Read-Out Protection. The
protection, once activated, blocks reading
memory content. Such reading can be
carried out in two ways:
I. Entering Test Mode you can execute an
external memory program which allows
the on-chip Eprom reading through LOAD
instructions execution.
2. Entering Eprom-like Mode, using the
Verify facility.
Programming the first protection bit blocks
reading in these two conditions (PROTA on
port Plo).
Another protection bit (PROTE on port
P07) can be activated when the Z86E21 is in
external memory configuration.
This protection prevents software

166

manipulation of the external memory from
who decides to read the on-chip memory
content for a complete understanding of the
user application board.
When the Z86E21 works in external memory
facility the ports PO and PI are configurated
as Address/Data bus, so that the external
memory instructions can be executed during
the normal microcomputer operation. These
instructions can be also an appropriate
routine able to pull out the all on-chip
memory content using LOAD instructions.
When the protection is activated, each
reading attempt of the internal memory
content, using LOAD instructions, is
vainificated because the data out will be
always "FF".

EPROM Mode (Continued)
In consequence this protection activation
inhibit the LOAD instructions execution from
external to internal memory. To overcome
this problem is necessary to call a "READ"
routine written in on on-chip memory space.
The protections are activated by
programming 2 non-volatile transistors
simply forcing 10 V for a time more than
100 ms on the desired pin, on condition that
the microcomputer is in Reset state, the
Clock signal is present and the EPM pin is
not set.
H a complete protection is desired, both
protections must be programmed.
A simple board diagram for read-out
protection activation is shown in Figure 15.

• 5V

Vee

GND

20pF

~~cf
-11-

XTAl1

Z86E21
HAll
RESET

EPM
PROTA
PROTe

Figure 15. Read-out Protection
Activation Diagram

Instruction Set Notation
Addressing Modes. The following notation is

IMR

used to describe the addressing modes and
instruction operations as shown in the
instruction summary.

Assignment of a value is indicated by the
symbol «<--». For example,
dst <-- dst + src
indicates that the source data is added to the
destination data and the result is stored in
the destination location. The notation
"addr(n)" is used to refer to bit "n" of a
given location. For example,
dst (7)
refers to bit 7 of the destination operand.

IRR

Indirect register pair or indirect workingregister pair address

Irr
X
DA
RA
1M
R

Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only

IR

Indirect-register or indirect working-register

Ir

address
Indirect working-register address only

RR

Register pair or working register pair address

Flags. Control Register R252 contains the
following six flags:
C
Z
S

Symbols. The following symbols are used in

V

describing the instruction set.

D

dst
src
cc

Destination location or contents
Source location or contents
Condition code (see list)
@
Indired address prefix
Stack pointer (control registers 254-255)
SP
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)

Interrupt mask register (control register 251)

H

b7
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

bo

Ic IzIsIv ID IH 1F2IFlI
FI
F2

} user flags

Affected flags are indicated by:

o
*

x

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

167

Condition Oodes
Value

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111

lOll
0011
0000

168

Mneomonic

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning

Always true
Carry
No carry
Zero
Not zero
Plus
Minus

Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set

C=I

C=O
Z=l
z=o
S=O
S=l
V=I
V=O
Z=l
Z=O
(S XOR V)=O
(S XOR V)= I
[Z OR (S XOR V)]=O
[Z OR (S XOR V)] = I
C=O
C=l
(C =0 AND Z=O) = I
(C OR Z)=I

Instruction Formats

..,

ope

CCF, 01. £1. IRET, NOP,
ReF, RET, SCF

ope

INCr

One-Byte Instruction

ope

eLR, CPl, OA, DEC,

MODE

dltlsre

OR

I

ope

I---':::••'-','---l

11 1 101 dltl,re I

OR "

ope

~~i~'~~~Rt~~:R.POP,
ARC, SA". SWAP
JP, CALL (IndlrK.I)

, , 01

ope

ope

•• ,

..,
..,

MODE

OR
OR

MODE

OR

t 1 1 0

t 1 t 0

11 1 101

VALUE

SRP

.11

..,

ADC, ADD, AND, CP,
LO, OR, S8C, SUB.
TeM, TM, XOA

ADC, ADD. AND, CP,

lO, OR,

sac, SUB,

TeM, TM: XOR

VALUE

..,

MODE

MODE

ope

dlUlrc

"e/da'

dlU'fe

ope

.,.

lreldt'

..,

I

ope

TeM, TM, XOA

dlUCCR~ OPe

MODE

OR
OR

ope

t 1 1 0
t 1 1 0

..,

LD

LD

dsllsrc

ADDRESS

LD

ope

OR 11 1 1 01

JP

DA,
DA,
LD

VALUE

I

.re

ADC, ADD. AND,
CP, OR, S8C. SUB •

lO, lOE, lOEl,
LOC, lDCI

ope

..,

MODE

ope

ope
DJNZ, JR

CALL

DA,
DA,

Two-Byte instruction

Three-Byte instruction
Figure 16. Instruction Formats

169

Instruction Summary
Instruction
and Operation

Addr Mode

Opcode Flag. Affected
Byte

d.t

orc

(Hex",

C Z5 VDH

lnotructlon
and Operation

Addr Mode

Opcode Flag. Affected
Byte

d.t

.rc

(Hex)

1m

rC
r8
r9
r =O-F
C7
D7
E3
F3

C Z S V D H

!

ADC dst,src

(Note 1)

10

LD dst,sre

dst - dst + Ire, + C

dst -

ADD dst,src
dst - dst + 'src

(Note 1)

00

AND dst,src
dst - dst AND sre

(Note 1)

50

src

r

a•

r

CALL dst

DA
C;p - SP - 2
IRR
@SP - PC; PC - dst

D6
D4

cel'

EF

IR

COM dst

R

dst - NOT dst

IR

CP dst,sre

(Note

BO
Bl

R

60
61
1)

a

dst - src

.. X - -

DA dst

R

dst - DA dst

IR

DEC dst
dst - dst - 1

R

00

IR

01

.. -

DECW dst

RR

80

IR

81

- * * • - -

dst - dst - 1

DI
IMR (7) -

a

DINZ r,dst
r - 1
If r
0
PC - PC + dst
Range: + 127, -128

r -

'*

rA
r=O-F

R

E4

R

IR

R
IR
IR

1m
1m
R

E5
E6
E7
F5

r

Irr

C2

Irr
Ir

C3
D3

Irr

LDCI dst,sre

Ir

dst -

Irr

INC dst
dst - dst + 1

r
Irr

Irr

82

LDE! dst,src

Ir

Irr
Ir

83
93

1)

40

dst -

src

r - r

+ 1;

Irf
rr -

rr

- - - - - -

FF

NOP

OR dst,src
dst - dst OR src

(Note

PUSH sre
SP - SP - 1; @ SP - sre

51

R
IR

CF

9F

RET

AF

rE

RL dst

PC - @SP; SP - SP + 2

AD

dst - dst +

IR

Al

90

91
RLC dst

r~--------'

R

10

~IR

II

EO

RR dst

EI

BF

FLAGS - @SP; SP - SP + 1
PC - @ SP; SP - SP + 2; IMR (7) - 1

RRCdst~1

R

IP

SBC dst,sre

(Note

If cc is true
PC - dst

IRR

JR

RA

a

20

RR

DA

70
71

RCF

INCW dst

IRET

- .. . . 0 - -

so

R

IR

r =O-F

R

170

92

+ 1

dst - @SP
SP - SP +

______________IR~_______2~1_____________

cC,dst
if cc is true,
PC - PC + dst
Range: + 127, -128

D2

LDE dst,sre
dst - src

POP dst

1

cC,dst

r

R

C-O

EI
IMR (7) -

-

SF
RA

Ir

r - r + 1; rr - rr + 1

AD

40 .
41

r

r

LDC dst,src
dst - src

src

X

X
Ir

C - NOT C

CLR dst
dst - a

R

R

~IR

cD
c=O-F

cB

Cl
1)

3D

dst - dst - src - C

30
e=O-F

CO

- - - - - -

SCF

DF

C-l

SRA dst

LEi @

I~

DO
Dl

1 - - -

Instruction Summary (Continued)

Instruction
and Operation

Addr Mode

dal

SRP src
RP - src
SUB dst,src
dst - dst - src

arc

Opcode naga Affected
Byte
(Hex)
CZSVDH

1m

31

- - - - -

(Note 1)

20

1

SWAPdst~ R

lR

FO
Fl

.

X • * X - -

In.truction
and Operation

Addr Mode

dat
arc
- - - - - ------- ,----TCM dst,src
(Note 1)
(NOT dst) AND src

Opcode Flaga Affected
Byte
(Hex)
CZSVDH

60

• 0
• 0

TM dst, src
dst AND src

(Note 1)

70

XOR dst,src
dst - dst XOR src

(Note 1)

BO

Add. Mode

dst

src

-

* *

a- -

Lower

Opcode Nibble

Note I
Ir
These instructions have an Identical set ot addressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The

second nibble IS expressed symbolically by a 0 in this
table, and ItS value IS found in the followmg table to the
left of the applicable addreSSing mode pair.

R
R
R
IR

R
IR

1M
1M

For example, the opcode of an ADC instruction using

the addreSSing modes r (destination) and Ir (source) IS 13.

171

Registers
R240SI0
Serial I/O Register

R244 TO
Counter/Timer 0 Register

(FOH; Read/Wrile)

(F4H; Read/Write)

L-_ _ _

SERIAL DATA (Do '" lSB)

R241 TMR
Timer Mode Register

R245 PREO
Prescaler 0 Register

(FI H ; Read/Write)

(F5 H : Write Only)

NOT TO"'
USEDMODES
= 00

~~ g~~ ~ ~~
INTERNAL CLOCK OUT", 11

j

~

I~I~I~I~I~I~I~I~I

llli~

=

0
NO FUNCTION
1 = LOAD
To
0 = DISABLE To COUNT
1
ENABLE To COUNT

=

T

MODES
eXTERNAL CLOCK
00
GATE INPUT", 01
TRIGGER INPUT = 10
(NON.RETRIGGERABLE)
TRIGGER INPUT", 11

0
1
0
1

INP'lh '"

~L

COUNTMODE
o - To SINOL\.PASS
1 • To MODULO·N
RESERVED (MUST 8E 0)

= NO FUNCTION
= LOAD T I
= DISABLE T, COUNT
'" ENABLE T COUNT

PRESCALEA MODULO
(RANGE: 1-&4 DECIMAL
01-00 HEX)

1

(RETAIGGERA8lE)

R242 Tl
Counter Timer 1 Register

R246 P2M
Port 2 Mode Register

(F2H; ReadIWrite)

(F6H: Write Only)

1~!~I~I~I~I~I~I~1

ro;ro;yo. [0,1 0, I0, : D. I0, I

R243 PREI
Prescaler 1 Register

R247 P3M
Port 3 Mode Register

(.3 H : Write Only)

(F7 H : Write Only)

I~I~I~I~I~I~I~I~I

~L

COUNTMODE
o '"
1

~~

T, SINGLE· PASS

= T,

MOOUlO·N

CLOCK SOURCI:
1
TI INTERNAL
o TI EXTERNAL TIMING INPUT
(T'N) MODE

oI PORT
2 PULL·UPS OPEN DR"N
PORT 2 PULL-UPS ACT'VF
RESERVED (MUST BE 0)

o P32
1 Pl2

IJ 0

'" INPUT
P35 =: OUTPUT
I5AVQIRDYO P15 = RDYOIDAV"O

:=

P33 = INPUT

P3. = OUTPUT

~~}P33=INPUT

PRESCAlER MODULO
(RANGE' 1-6" DECIMAL
01-00 HEX)

1 1

P3,,=DIiI
P33 '" GiVl/AOVI P3" '" RDY1IDAV'1

L _ _ _ _ _ _ ~ :~~ ~ :-v~,m~ :~
L

_______ ~

L ________
Figure 11. Control Registers

172

:

~~~~~UT)

;~ ~ ~N:R~lL IN :~~ ~ ~~~~~TOUT

~ ::::~ g~F

Registers (Continued)
R248 POIM
Port 0 aDd 1 Mode Register

R252 FLAGS
Flag Register

(F8H; Write Only)

(FCH; Read/Write)

I~I~I~I~I~I~I~I~I

I~ ~ ~I~I~I~I~I~I

po,.po,

MODE:]
~

OUTPUT", 00
INPUT" 01
A12-A1~

=

1)(

EXTERNAL MEMORY TIMING
NORMAL", 0
EXTENDED" 1

-r
L po,·po, MODE

~

U~~
I

00 = OUTPUT
01 '" INPUT
IX =: Ae-A"

LUSERFLAGF!

LUSER FLAG F2

STACK SELECTION
o " EXTERNAL

1 " INTERNAL

SIGN flAG

Pl o-Pl, MODE
00
01
10
11

"
'"
"
=

BYTE OUTPUT
BYTE INPUT
AOo-AO I
HIGH·IMPEOAN,;E

AS. OS,

HALF CARRY FLAG

~:~~:~~:o:~:~ FlAG
ZERO FLAG
CARRY FLAG

ADo-~DI

RtW. A,-All. A,~ AL

IF SELECTED

R2491PR
IDterrupt Priority Register

R253 RP
Register PoiDter

(F9H; Write Only)

(FDH; Read/Write)

III

I~I~I~I~I~I~I~I~I

_,•• '"'.0.::1 [ [

,",,""~.oo",.".m

LDON'TeARE

RESERVED = 000

C > A ;;. B :: 001
A > B > C = 010
It ;;. C
B =: 011
B ;;. C ;;. A = 100
IROO, IR02 PRIORITY (GROUP l I e ; ; . B ;;. It = 101
o " I"Q2 > IRoo
B > A ;;. C " 110
1 '" IROO ;;. 1"02
RESERVED:: 111

IRQ3, IA05 PRIORITY (GROUP AI
o =- IAQS > IR03
, = IR03 > IAQ5

REGISTER
POINTER

IRQ1, IRQ.. PRIORITY (GROUP C)
o '" IR01 > IR04
1 = IR04 > IR01

R250 IRQ
Interrupt Request Register

R254 SHP
Stack Pointer

(FA H ; Read/Write)

(FEH; Read/Write)

I~I~I~I~I~I~I~I~I
RESERVED (MUST BE 0)

c==

T

IRoo '"
IR01 '"'
IR02 =
IR03::
IRQ4 '"
IROS ""

Pl2 INPUT (Do '" IRoo)
P13 INPUT
P3, INPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T1

R251lMR
Interrupt Mask Register
(FBH; Read/Write)

(FFH; Read/Write)

10, D.: 0, i0,.0, i 0, i 0, 0, I

I~I~I~I~I~I~I~I~I

II
,

R255 SPL
Stack PoiDter

c==

L ______

!

1 ENABLES IRoo-IROS
(Do :: tRoo)
RESERVED (MUST BE 0)

L _ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

Figure 17. Control Registers (Continued)

173

Low.r Nibbl. (Hex)

Opcode Map

A
6,5

6,5

6,5

6,5

DEC

10,5

10,5

10,5

DEC

ADD

ADD

ADD

RI

IRI

ADD

ADD

II,Ia

II,lra

R2, HI

IRa, Al

RI.IM

6,5

6,5

6,5

6,5

10,5

la,S

10,5

RLC

RLC

ADC

ADC

ADC

RI

IRI

ADC

ADC

Il,la

rJ,Ir2

H2,ftl

IRa,HI

AI,IM

ADD
IRI,IM

"!o:5

6,5

6,5

INC

SUB

SUB

SUB

RI
8,0

IRI
6,1

n,ll

II,lra

H2, HI

6,S

6,5

la,S

10,5

10,5

10,5

JP

SRP

SBC

SBC

IRRI

1M

SBC

SBC

SBC

fl,fa

(I,Ira

SBC
H2, HI

IR2,Hl

HI,IM

JRt,IM

8,S

8,5

6,5

6,5

10,5

10,5

10,5

OA

OA

OR

OR

OR

RI

IRI

Il,la

n,1ra

FIa,Rl

10,5

10,5

SUB

IRa, HI

SUB
IRdM

OR

OR

HI,IM

IRI,IM

10, S

6,5

POP

AND

IRI

AND

AND

AND

AND

rl,lra

Ra,Rl

AND

fl,la

IRa,Rl

HI,IM

tRI,IM

6,5

6,5

COM

COM

TCM

TCM

RI

IRI

TCM

TCM

Il,Ia

II,lra

82,Hl

IA2,Hl

.!

10/12,1

12/14,1

:9

R,

IR,

10,5

10,5

15

PUSH PUSH

,Q

z

l

OECW OECW

::>

B

C

0
E

F

6,5

1O,S

10,5

TM
IRI,IM

"

18,0

LOE

I-I-I-I--I---

LOE!

6,1

01

I-6,1

E!

la,lIn Ira,luI

INCW INCW

6,5

6,5

10,5

10,5

10,5

CP

CP

CP

CP

CP

n,la

CP

1ft I

II,Ir2

R2,Rl

IR2,RI

RI,IM

IRI,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,$

CLR

CLR

XOR

XOR

XOR

XOR

XOR

RI

IRI

XOR

H,r2

rl,Ir2

Ib,RI

IR2,RI

Rt.JM

IRI,IM

6,5

6,5

12,0

18,0

RRC

RRC

LOC

LOCI

RI

1ft I

-

LO

6,5

6,5

12,0

18,0

SRA

LOC

LOCI CALL"

RI

IRI

6,5

6,5

6,5

10,5

RR

RR

LO

LO

RI

IRI

rl,IR2

R2,Rl

8,5

8,5

6,5

10,5

to

tD

1r},r2

Ra,IRI

20,0

20,0

10,5

CALL

LO

DA

r2, x, RI

10,5

10,5

10,5

LO

LD

LO

IR2,Rl

RI,IM

lRI,IM

IRRI

______~~~______~J'
, ______~~~__-----'~

Byte. per
Instructloa.

RET

- 16,0

IRET
6,5

RCF

ll, x, R2

SRA

IR,

14,0

10,5

ll,Irr2 Irl,lrr2

SWAP SWAP

I--

10,5

RRI

l2,luI 1r2,lrn

/---

r---

18,0

12,0

~'

INC

10,5

TM
HI,IM

6,5

RI

IP
cc,DA

10,5

TM

6,5

F

TCM

IRa.HI

LOE!

1ft I

to

II,1M

IRI,IM

TM

In,Ina

'ilL

10,5

TCM

RdM

Ra,Rl

LOE

10,5

10,5

TM

12,0

IR
ce, RA

6,5

~-.-

10,5

II, Ira

fI,lu2

RI

la,S

10,5

TM

IRI

10,5

10,5

10,5

rl,I2

RRI

RL
A

6,5

6,5

RA

12 / 10,0

10,5

OR
IRa,Hl

RI
6,5

..

OINZ
II,

£

------,-

6,'

~

10,5

10,5

LO
r2,RI

12110,0

10,5

SUB
HI,IM

POP

6,5

82

o

C

12110,5

ADC

6,5

10,5

LO
II.

6,5

IRI,/M

INC

6,5

6,5

10,5

~

6,5

SCF
~

6,5

CCF
~

6,0

NOP
~,

________~~~__________~J

~

~

Lower

Opeode
Nibble
Executioa.

Cyel..

•

Upper
Opcode- A

Pipella.e

Cyel..

Legend:
R = a-sli Address
4-811 Address
RI or fl = Dst Address
R2 or f2 = Src Address
r =

Mnemonic

Nibble
First

Opercmd
"2·byte Instruction; fetch cycle appears as a 3-byte mstruclJon

174

Second

Opercmd

Sequea.ce:
Opcode, Firs! Oper<'.lnd, Second Operand
Note: The blank areas are not dehned.

Absolute Maximum Ratings
Voltages on all pins
with respect to GND ........ -0.3 V to+7.0 V
Operating Ambient
Temperature ....................... ooe to + 70°C
Storage Temperature ....... - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; operation of the device at any condition

above those indicated in the operational sections of these
specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Test Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced
to GND. Positive current flows into the
reference pin. Standard conditions are as
follows:

o +4.75V::5 Vee ::5+5.25 V
o GND=O V
o ooe ::5 TA ::5 +70 oe

+5V
+SV

+5V

+5V
1.Sk

1.Sk

2.1K

18K

74LS04

7:::"504

Cl~CK --I.pI>O-.....- ....-IvI>O-.....-.,__

I
,

c,

XTAl2

= 15pF MAX

L _ _ _ _....._ _ XlAll

1,,

c,

Figure 18. Test Load 1

Figure 19. Test Load 2

= 15pF MAX

Figure 20. External Clock Interface Circuit

175

DC Characteristics
Symbol

Parameter

VeH

Clock Input High Voltage

VeL

Clock Input Low Voltage

VIH

Input High Voltage

VlL

Input Low Voltage

VRH

Reset Input High Voltage

VRL

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

IOL

Output Leakage

Min

Max

3.8

Vee

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

2.0

Vee

V

-0.3

0.8

V

3.8

Vee

V

-0.3

0.8

V

2.4

V

10H= -250 p.A

0.4

V

10L= +2.0 rnA

-10

10

p.A

-10

10

p.A

o V;5,
o V;5,

Vee = +5.25 V, VRL=O V

1m

Reset Input Current

-50

p.A

lee

Vee Supply Current

120

rnA

IMM

VMM Supply Current

10

rnA

VMM

Backup Supply Voltage

Vee

V

176

Condition

Uni~

3

VIN ;5, +5.25 V
VIN ;5, +5.25 V

Power Down Mode
Power Down

External 1/0 or Memory Read and Write Timing
Z86E2l
No

Symbol

Paramter

Min

TdA(AS)
Address Valid to AS i Delay
TdAS(A)
AS i to Address Float Dealy
2
TdAS(DR)
AS i to Read Data Required Valid
3
AS Low Width
4
TwAS
TdAz(DS)
Address Float to DS t
5
6--TwDSR---DS (Read) Low Width
DS (Write) Low Width
TwDSW
7
TdDSR(DR)
DS t to Read Data Required Valid
8
ThDR(DS)
Read Data to DS i Hold Time
9
TdDS(A)
DS i to Address Active Delay
10
II
TdDS(AS)
DS i to AS t Delay
12-TdR/W(AS)--R/W Valid to AS i Delay
TdDS(R/W)
DS i to R/W Not Valid
13
TdDW(DSW) Write Data Valid to DS (Write) t Delay
14
TdDS(DW)
DS i to Write Data Not Valid Delay
15
TdA(DR)
Address Valid to Read Data Required Valid
16
TdAS(DS)
AS i to DS t Delay
17

Max

50
70

Z86E2lA
Min
Max
35
45

360
80
0
250
160

220
55
0
185
110

200
0
70
70
50
60
50
70

130
0
45
55
30
35
35
45

410
80

255
55

Notes*t
1,2,3
1,2,3
1,2,3,4
1,2,3
I
1,2,3,4
1,2,3,4
1,2,3,4
I
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3

NOTES,

1. Test Load I
3. Also see clock cycle time dependent characteristics table.

5. All timing references use 2.0 V for a logic "l" and 0.8 V for
a logic "0".
* All units in nanoseconds (ns).

4. When using extended memory timing add 2 TpC.

t Timings are preliminary and subject to change.

2. Timing numbers given are for minimum TpC.

RlW

PORT 0,

iiiii
16
PORT 1

As

1 - - - - - - - { ( D } - - - - -..IJr-_ _+-__
OS
(READ)

PORT 1

~-A1

00-07 OUT

OS
(WRITE)

Figure 21. External I/O or Memory Read/Write

177

Additional Timing Table
Z86E21
No

Symbol

Paramler

TpC
Input Clock Period
2
TrC, TIC
Clock Input Rise And Fall Times
Input Clock Width
3
TwC
TwTinL
Timer Input Low Width
4
5--TwTinH---Timer Input High Width
TpTin
Timer Input Period
6
7
TrTin, TfTin
Timer Input Rise And Fall Times
8a
TwIL
Interrupt Request Input Low Time
8b
TwIL
Interrupt Request Input Low Time
Interrupt Request Input High Time
9
TwIH
NOTES:
1. Clock timing references uses 3.8 V for a logic "I" and 0.8 V
for a
"0",

2.
logic

reference uses 2.0 V for a logic "1" and 0.8 V for a

Min

Max

125

1000
25

37
100
3TpC
8TpC

83

Notes*t

1000
15

26
70
3TpC
8TpC
100

]00
3TpC
3TpC

100
70
3TpC
3TpC

3. Interrupt request via Port 3 (P3J -P33)'

4. Interrupt request via Port J (PJO)'
*

t

Units in nanoseconds (ns).

Timings are preliminary and subject to change.

Figure 22. Additional Timing

178

Z86E2lA
Min
Max

2
2
2
2
2,3
2,3
2,3

Handshake Timing
Z86E2l
No

Paramter

Symbol

Min

TsDl(DAV)
Data In Setup Time
ThDl(DAV)
Data In Hold Time
2
Data Available Width
3
TwDAV
TdDAVIf(RDY)
DAV L Input to RDY L Delay
4
5-TdDAVOf(RDY)-DAV j Output to RDY I Delay
DAV i Input to RDY i Delay
TdDA VIr(RDY)
6
TdDAVOr(RDY)
DAV i Output to RDY i Delay
7
TdDO(DAV)
Data Out to DA V I Delay
8
TdRDY(DAV)
Rdy I Input to DA V i Delay
9
NOTES:
1. Test Load 1
2. Input handshake
J. Output handshake

Max

0
230
175

Z86E2lA
Min
Max

175
0

120
0

175
0
50
0
4.

Al~ ti:?~?g

200

120
0
30
0

140

1,2
1,3
1,2
1,3
1
1

reqerences use 2.0 V for a logic "I" and 0.8 V for

0 .

a

IOQ1C

*

Units in nanoseconds (ns).
Timings are preliminary and subject to change.

t

Notes*!"

0
160
120

DATA IN

DAV
(INPUT)

RDY
(OUTPUT)

Figure 23a. Input Handshake

DATA OUT

~

DATA OUT VALID

---~----------------Imi
(OUTPUT)

RDY
(INPUT)

1r--~®--~,
'
~

---=~====J~

Figure 23b. Output Handshake

179

Clock-Cycle-Time-Dependent Characteristics
Symbol

Number

TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)

I
2
3
4
6
7
8
lO
II
12
13
14
15
16
17

TdR/W(AS)

TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

Z86E21
Equation

Z86E21A
Equation

TpC-7S
TpC-55
4TpC-140>
TpC-45
3TpC-125>
2TpC-90>
3TpC-17S>
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215>
TpC-45

TpC-SO
TpC-40
4TpC-llO>
TpC-30
3TpC-65>--2TpC-SS>
3TpC-120>
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160>
TpC-30

* Add 2TpC when using extended memory timing.

Ordering Information
Type

Package

Temp.

Ceramic

Dl
D6

Ceramic

01 + 70°C
- 401 + 85°C

Z86E21A DI
Z86E21A D6

Ceramic
Ceramic

01 + 70°C
-401 + 85°C

Z86E21
Z86E21

180

Clock

}
}

8 MHz

12 MHz

Description

8K EPROM Microcomputer

Packages

Packages
40 - Lead Plastic DIP

40 - Lead Ceramic DIP (Frit-Seal)

40 - Lead Ceramic DIP (Glass lens)

183

Packages
44 - Leaded Plastic Chip Carrier

44 - Leadless Ceramic Chip Carrier
-I

I

~

--+i

184

Reliability Informations

Quality Assurance Organization Chart
Q.A. Manager

,--------L-Incoming and
in-process
Quality Control

Outgoing
Quality
Control

- purchased
good

finished
products

- reliability
tests

- diffusion

customer
returns
management

- new
products
qualification

assembly

Products
Reliability

P.P.M.

New process
Qualifications

new process
qualification
- engineering

en g ineerin g

management

Failure
Analysis
Laboratory

- failure
analysis
engineering

Customer
specifications
and special
Qualification

customers
management

Documentation

and
Standardization

l specifications
management

customer
specifications
management

sp ecial
qualification
management

Handling
SGS has choosen a no-compromise
strategy in MOS ESD protection. From wafer
level to the shipping of finished units, we
fully guarnatee each work station and
processing of the parts. This is achieved
through total adoption of shiedlding and
grounding media. Final shipment is in
antistatic sticks vacuum sealed, in a
conductive shielding bag.
The supplier's best commitment is useless
if the end user does not provide the same
level of protection and care in application.
Here are the the basic static control
protection rules:
A - Handle all components in a static-safe
work area.
B - Transport all components in static
shielding containers.
To comply with the rules the following
procedures must be set up.
1 - Static control wrist strap (from a qualified
source) should be worn and connected
properly.
2- Each wor surface must be protected with
a conductive mat, properly grounded.
3 - Extensive use of conductive floor mats.
4 - Static control shoe straps should be worn
insulative footwear, such as those with crepe
or thick rubber soles is worn.
5 - Ionized air blowers are a necessary part
of the protective system, to neutralize static

charges on conductive items.
6 - Use only the grounded tip variety of
soldering iron.
7 - Single components, tubes, printed circuit
cards should always be contained in static
shielding bags; keep our parts in the original
bags up to the very last possible point in
your opertion line.
8 - If bigger containers (tote box) are used
for in-plant transport of devices op PC
boards they must be electrically conductive,
like the carbon loaded types.
·9 - All tools, persons, testing machines,
which could contact device leads must be
conductive and grounded.
10 - Avoid the usage of high dielectric
materials (like polystyrene) for subassembly
construction, storage, transportation.
11 - Follow a proper power supply sequence
in testing and application. Supply voltage
should be applied before and removed after
input Signals; insertion removal from sockets
should be done with no power applied.
12 - Filtration, noise suppression, slow
voltage surges should be guaranteed on the
supply lines.
13 - Any open (floating) input pin is a
potential hazard to your circuit: ground or
short them to VDD whenever possible.

187
-----------~~

....

MOS fCMOS STD Process Flow-Chart

KEY:

100% OPERATION /SCREENING
AUDIT/MONITOR
GATE INSPECTION (SAMPLE)
1 - MATERIAL ACCEPTANCE
2 - WAFER / MASK FABRICATION
2A- MASK ACCEPTANCE

3-

INPROCESS
EQUIPMENT
ENVIRONMENT

INSPECTION (AUDIT)

4 - ELECTRICAL WAFER SORT
5 - FINISHED WAFER VISUAL ACCEPTANCE
6 - DIE FABRICATION AND VISUAL SCREENING (*)

PLASTIC
PACKAGE

7 - DIE VISUAL ACCEPTANCE
CERAMIC
PACKAGE

PLASTIC
PACKAGE

8 - DIF ATTACH / WIRE BOND
9 - VISUAL AND MECHANICAL CONTROL (MONITOR)
ASSEMBLY AREA ENVIRONMENT & EQUIPMENT (AUDIT)
10 - VISUAL SCREENING (*)
11 - PRE-CAP VISUAL ACCEPTANCE
12 - SEALING / MOLDING
13 - SEALING ATMOSPHERE, SEAL
AND LID TORQUE CONTROL
14 - CROPPING / BENDING

188

(MONITOR)

MOS /CMOS STD Process Flow-Chart (Continued)
CERAMIC
PACKAGE
PLASTIC PACKAGE

15 - VISUAL CONTROL
16 - TINNING ACCEPTANCE
17 - TINNING PLATING ACCEPTANCE

(*) Omitted when intrinsic quality meets the specified quality level.

MOS/CMOS STD & Optional Process Flow-Chart
CERAMIC
PACKAGE

PLASTIC PACKAGE

18 - LEAD TRIMMING
19 - INTERNAL WATER-VAPOR CONTENT (MONITOR)
20 - RAW-LINE ACCEPTANCE
21 - RELIABILITY TESTS STD CLASS
(REAL TIME & GROUP BCD TESTS) (MONITOR-AUDIT)
22 - ELECTRICAL TESTING AND MARKING

23 - VISUAL AND ELECTRICAL FINAL
ACCEPTANCE (SEE PAGE 191)
Sid
23AClasses 0 lional Classes

MECHANICAL (MONITOR)

24 - SCREENING OPTIONS
(TO BE AGREED WITH CUSTOMER)
25 - VISUAL, ELECTRICAL AND RELIABILITY TESTS
FINAL ACCEPTANCE (OPTIONAL CLASSES)
26 - PACKING
27 - PACKING AND DOCUMENTATION ACCEPTANCE
SHIPPING

SHIPPING

189

MOS /CMOS STD Visual and Electrical Final Acceptance

OPTIONAL RELIABILITY TESTS (GROUP BCD TESTS)
(TO BE AGREED WITH CUSTOMER)
ELECTRICAL ACCEPTANCE AT 25°C
(STD CLASSES)
ELECTRICAL ACCEPTANCE LOW AND HIGH TEMPERATURE
(STD CLASSES)
VISUAL ACCEPTANCE (MIL 883 B MTH 2009)
(STD CLASSES)
SOLDERABILITY INSPECTION
RESISTANCE TO SOLVENT
HERMETICITY (FINE AND GROSS)
PH,YSICAL DIMENSIONS

!

(STD CLASS)
(MONITOR)

PACKING AND DOCUMENTATION ACCEPTANCE (STD CLASSES)
CERTIFICATE OF CONFORMITY (ON REQUEST)

SHIPPING

190

FOR TEST CONDITIONS SEE PAGE 191

Production Quality Tests Description and Screenings

Process
Steps
1

2A
3

Descriptions

Tests

MATERIAL ACCEPTANCE

WAFER - MASKS - WIRES - FRAMES - PHOTORESIST CHEMICALS - PREFORMS - RESIN - BONDING TOOLS PLASTIC TUBES - GLAZED CERAMIC PARTS
MULTILAYER CERAMIC PACK - GOLD PLATED CAPS

MASK ACCEPTANCE

VISUAL DIMENSIONS

WAFER FABRICATION
INSPECTION
INPROCESS

PHOSPHORUS CONTENT IN P. VAPOX
GLASSIVATION INTEGRITY (MIL-SID 883C MTH 2021)
S.E.M. INSPECTION (MIL-SID 883C MTH 2018)
VISUAL AND DIMENSIONAL INSPECTION
(MIL SID 883C MTH 2010 CONDo B)

EQUIPMENT

CONTAMINATION
D.1. WATER RESISTIVITY
BACTERIOLOGICAL ANALYSIS OF THE D.1. WATER

5

ENVIRONMENT

DUST COUNT
HUMIDITY
TEMPERATURE

FINISHED WAFERS
VISUAL ACCEPTANCE

MIL-SID 883C MTH 2010 CONDo B

7

DIE VISUAL ACCEPTANCE

MIL-SID 883C MTH 2010 CONDo B

9

DIE ATTACH CONTROL

MIL-SID 883C MTH 2010 CONDo B (INTERNAL VISUAL)
AND MTH 2019 (DIE SHEAR STRENGHT)

BONDING CONTROL

MIL-SID 883C MTH 2010 CONDo B (INTERNAL VISUAL)
AND MTH 2011 CONDo D (BOND STRENGTH)

ASSEMBLY AREA
ENVIRONMENT CONTROL

DUST COUNT
HUMIDITY
TEMPERATURE

EQUIPMENT

D.1. WATER RESISTIVITY

Il

PRECAP ACCEPTANCE

MIL-SID 883C MTH 2010 COND B (INTERNAL VISUAL)

12

SEALING

VACUUM PREBAKE: 2 HRS AT 220°C
HIGH TEMP. FINAL SEAL: 8 MINUTES ABOUT AT 450°C

MOLDING AND
STABILIZATION BAKE

STABILIZATION BAKE: 8 HRS AT 175°C

SEALING
ATMOSPHERE CONTROL

MOISTURE CONTENT: < 200 PPM

SEAL CONTROL

FINE LEAK
MIL-STD 883C MTH 1014 CONDo Al
HELIUM LEAK DETECTOR AFTER PRESSURIZATION
IN HE FOR 2 HRS AT 4 ATM
LIMIT: 5x 10-8 CCIS FOR ICV' < 0.4 CC
2x 10-7 CCIS FOR ICV > 0.4 CC
• (ICV = INTERNAL CAVITY VOLUME)

13

191

Production Quality Tests Description and Screenings

Process
Steps

(Continued)

Descriptions

Tests

GROSS LEAK
MIL-STD 883C MTH 1014 CONDo C (FLUOROCARBON
GROSS LEAK) 5 TORR VACUUM FOR 1 HR EXCEPT FOR
ICV > 0.1 CC FOLLOWED BY PRESSURIZATION IN MINERAL
OIL AT:
4 ATM FOR 2 HRS FOR ICV < 0.1 CC OR
4 ATM FOR 10 H FOR ICV > 0.1 CC
AND SUBSEQUENT IMMERSION IN MINERAL OIL AT
Tamb= 125°C
LID TORQUE CONTROL

CERAMIC PACKAGES ONLY MIL-STD 883C
MTH 2024

15

CROPPING / BENDING
CONTROL

MIL STD 883C MTH 2009

17

TIMING ACCEPTANCE

SOLDERABILITY MIL STD 883C MTH 2003 Tamb = 245+5°C
FOR 5+0.5 SEC. WITH PRECONDITIONING FOR 1 HRABOVE
BOILING DlST. WATER (I.E.C. MTH AVAIL. ON REQUEST)

19

INTERNAL WATER VAPOR
CONTENT CONTROL

DEW POINT MTH MIL-STD 883C MTH 1018 PROCEDURE
3-5000 PPM MAX (DEW POINT TEMPER. LESS THAN - 15°C)

20

RAW LINE ACCEPTANCE

EXTERNAL VISUAL MIL-STD 883C MTH 2009
LID TORQUE TEST: AS PER STEP 13
CONSTANT ACCELERATION
MIL-STD 883C MTH 2001 CONDo E (30,0006)
Yl ORIENTATION ONLr
SEAL CONTROL: AS PER STEP 13

21

RELIABILITY TEST
(REAL TIME AND
GROUP BCD TESTS)

MONITOR ON STD CLASSES, GATE ON REQUEST
(TEST AND SAMPLE SIZE TO BE AGREED WITH CUSTOMER)
AUDIT ON ALL FACTORIES

23

VISUAL AND ELECTRICAL
FINAL ACCEPTANCE
STD CLASS

VISUAL AND MECHANICAL INSPECTION

23 A

27

MECHANICAL

PACKING AND
DOCUMENTATION ACC.ANCE

CUMULATIVE ELECTRICAL AND INOPERATIVE
MECHANICAL FAILURES
SOLDERABILITY INSEPCTION
RESISTANCE TO SOLVENT
HERMETICITY (FINE AND GROSS)
PHYSICAL DIMENSIONS
VISUAL

• 20,000 G FOR PACKAGES WITH CAVITY PERIMETEH OF 5 CM OF MORE AND/OH WITH A MASS OF 5 GRAMS OR MORE

192

Reliability Group B Tests Description
Performed every week or every 3 months on raw line material and/or finished products
MIL-STD-883C
Test
Method

Condition

(1)
SUBGROUP 1
PHYSICAL DIMENSIONS

2016

MAlOR DIMENSIONS ACCORDING TO DATA SHEET

(1)
SUBGROUP 2
RESISTANCE TO SOLVENT

2015

1 MINUTE IMMERSION IN SOLVENT SOLUTION
FOLLOWED BY 10 STROKES WITH A SOFT BRUSH (THE
PROCEDURE SHALL BE REPEATED 3 TIMES) SOLVENT
SOLUTION 2.1a ONLY FOR MOULD. PACK.

(1)
SUBGROUP 3
SOLDERABILITY

2003

SOLDERING TEMPERATURE 245±5°C for 5±0.5 SEC.
WITH PRECONDITIONING FOR 1 HR ABOVE BOILING
DISTILED WATER AND 5 TO 10 SEC. IN ROSIN BASE
FLUX

1005

1000 HRS AT Tamb= 125°C; ACCORDING TO DETAIL
SPECIFICATION

SUBGROUP 4
STEADY STATE AND OPERATING
LIFE TEST
END-POINT ELECTRICAL
PARAMETERS

AS SPECIFIED IN THE APPLICABLE DEVICE SPEC.
MEASUREMENTS AT 0, 168,500, AND 1000 HRS

SUBGRUP 5
(HERMETIC PACKAGES ONLY)
TEMPERATURE CYCLING

1010

TEST CONDITION C (10 CYCLES Tamb= -65°C TO
+ 150°C); 10 MINUTES AT EXTREME TEMPERATURES;
5 MINUTES TRANSFER TIME

CONSTANT ACCELERATION

2001

TEST CONDITION E (30000 G) Yl ORIENTATION ONLY (2)

SEAL
- FINE
- GROSS

(1)

END-POINT ELECTRICAL
PARAMETERS

1014
TEST CONDITION Al (SEE STEP 13 PAGE 191)
TEST CONDITION C
AS SPECIFIED IN THE APPLICABLE DEVICE SPEC.

(1)
SUBGROUP 6
(MOULDED PACKAGES ONLY)
PRESSURE POT

Tamb= 121°C, 2 ATM, 96 HRS

END-POINT ELECTRICAL
PARAMETERS

AS SPECIFIED IN THE APPLICABLE DEVICE SPEC.

1) Performed weekly on finished products.
2) 20000 g for package with cavity perimeter of 5 em or more and/or with a mass of 5 grams or more

193

Reliability Group C Tests Description
Performed every 6 months on raw line material
MIL-STD-883C
Test
SUBGROUP 1
LEAD INTEGRITY

SEAL
(HERMETIC PACKAGES ONLY)
- FINE
- GROSS
SUBGROUP 2
(2)
THERMAL SHOCK
(HERMETIC PACKAGES ONLY)
TEMPERATURE CYCLING

(2)

Method

Condition

2004

TEST CONDITION B2 (LEAD FATIGUE)
- WIRE LEADS: A FORCE OF 0.229±0.0I4 KG FOR
THREE 90±5° ARCS ON EACH LEAD BENDING CYCLE:
2 TO 5 SEC.
- DUAL-IN-LINE MOULDED PACKAGE: THREE LEADS
SHALL BE BENT, 3 TIMES, SIMULTANEOUSLY FOR AT
LEAST 15° PERMANENT BEND, RETURNING THEN TO
THE ORIGINAL POSITION.

1014
TEST CONDITION Al (SEE STEP 13 PAGE 191)
TEST CONDITION C

lOll
1010

MOISTURE RESISTANCE
(HERMETIC PACKAGES ONLY)

1004

SEAL
(HERMETIC PACKAGES ONLY)
- FINE
- GROSS

1014

TEST CONDITION B; 15 CYCLES (Tamb= -55°C TO
+ 125°C) 5 MIN. AT EXTREME TEMPERATURES
TRANSFER TIME :s 10 SEC.
TEST CONDITION C; 100 CYCLES (Tamb = - 65°C TO
+ 150°C) 10 MIN AT EXTREME TEMPERATURES;
TRANSFER TIME 5 MINUTES
10 CYCLES OF 24 HRS; Tamb=25°C TO 65°C
RH = 80% TO 100%
ONE 3 HRS CYCLE AT Tamb= -10°C

TEST CONDITION Al (SEE STEP 13 PAGE 191)
TEST CONDITION C

VISUAL EXAMINATION

PER VISUAL CRITERIA OF METHOD 1004 AND 1010

END-POINT ELECTRICAL
PARAMETERS

AS SPECIFIED IN THE APPLICABLE DEVICE SPEC.

SUBGROUP 3
(HERMETIC PACKAGE ONLY)
MECHANICAL SHOCK

2002

VIBRATION, VARIABLE
FREQUENCY

2007

CONSTANT ACCELERATION (I)
SEAL
- FINE
- GROSS

2001
1014

TEST CONDITION B; 1500 G - 0.5 MSEC. - 5 BLOWS IN
EACH OF THE 6 ORIENTATIONS - NOT OPERATING
TEST CONDITION A; 20 G - 3 ORIENTATIONS F=20 TO
2000 CPS; FOUR 4 MINUTES CYCLES, 48 MINUTES
TOTAL - NOT OPERATING
TEST CONDITION E (30000 G), YI ORIENTATION ONLY
TEST CONDITION Al (SEE STEP 13 PAGE 191)
TEST CONDITION C

VISUAL EXAMINATION

PER VISUAL CRITERIA OF METHOD 1011 OR 1010

END-POINT ELECTRICAL
PARAMETERS

AS SPECIFIED IN THE APPLICABLE DEVICE SPEC.

1) 20000 grams for packages with cavity perimeter of 5 em or more and/or mass or 5 grams or more.
2) Performed weekly.

194

Reliability Group C Tests Description (Continued)
Performed every 6 months on raw line material
MIL-STD-883C
Test
Method

Condition

1009

TEST CONDITION A; 10 TO 50 G OF NaCl PER SQUARE
METER PER DAY FOR 24 HRS Tamb= -35°C

SUBGROUP 4
SALT ATMOSPHERE
SEAL
(HERMETIC PACKAGE ONLY)
- FINE
- GROSS

TEST CONDITION Al (SEE STEP 13 PAGE 191)
TEST CONDITION C

VISUAL EXAMINATION

PER VISUAL CRITERIA OF METHOD 1009

SUBGROUP 5
(MOULDED PACKAGES ONLY)
HUMIDITY TEST

(4)

CECC
9000

END-POINT ELECTRICAL
PARAMETERS

85°C/85% RH WITH BIAS, t= 1000 HRS
ACCORDING TO DETAIL SPECIFICATION
AS SPECIFIED IN THE APPLICABLE DEVICE SPEC.
MEASUREMENTS AT 0, 168,500 AND 1000 HRS

SUBGROUP 6
(HERMETIC PACKAGE ONLY)
INTERNAL WATER-VAPOR CONTENT

1018

DEW POINT METHOD-PROCEDURE 3 (5000 PPM MAX)

2024

(SEE STEP 13 PAG. 191)

3015

R= 1.5KO
C=100pF
V=ACCORDING TO DETAIL SPECIFICATION

SUBGROUP 7
(3)
LID TORQUE
(HERMETIC PACKAGES ONLY)

SUBGROUP 8
ELECTROSTATIC DISCHARGE
SENSITIVITY
END-POINT ELECTRICAL
PARAMETERS

AS SPECIFIED IN THE APPLICABLE DEVICE
SPECIFICATION

3) Lid torque test shall apply only to packages which use a glass-frit-seal to lead frame, lead or package body (Le. wherever frit seal estabilishes
hermeticity or package integrity).

4) Performed monthly.

195

Development Products

-------------

--

----------~---~

- - - - - - - - - - - -------------------------------------

II.
General Purpose Foundation Module for MCU Emulation
• Combined with dedicated personality
packages it allows complete hardware and
software development and debugging for
MCUs
• Emulation memory: 8K bytes of static RAM
• Breakpoint memory: 8K bits of static RAM
allowing up to 8196 breakpoints on
addresses and/or data
• Real time trace memory:
lK x 25 bits of static RAM allowing up to

1024 events to be recorded during
program execution
• Personality module interface: a parallel
interface with an external personality POD
is provided
• Standard double - euro card format fully
compatible with SGS UX8-22
Development System and with the Z8
Emulation and Development package for
IBM compatible Personal Computers

General Description
The UX8-GPFM/2 is a general purpose
foundation module for MCUs emulation. It is
designed to be plugged into a UX8-22
Development System and to interface with an
externally connected POD.
UX8-GPFM/2 gives the user the basic and
general hardware tools in order to carry out
complete debugging and emulation for
MCUs.
In order to set up a complete development
and debugging tool for a specific single-chip
microcomputer it's necessary to integrate the
UX8-GPFM/2 with a specific personality

package. The personality package is
basically composed of a software
package for cross-assembling/linking/
debugging and of an external POD for the
hardware interface with the target
microcomputer (see UX8-EDPZ8 data sheet for
Z8 personality package general features).
The basic features of the UX8-GPFM/2
include: emulation memory, breakpoint
memory, real time trace memory, control
logic, interface with GAMMA-BUS and a
parallel interface for an external POD.

199

Hardware Features

•

•

•

EMULATION MEMORY: the emulation
memory is implemented with 8K bytes of
static RAM.
It is a dual port access memory
connected from one side to the GAMMABUS and to the other to the interface
circuitry with the external POD.
BREAKPOINT MEMORY: the breakpoint
memory is composed of 8K bits of static
RAM. The memory is addressed in
parallel with the emulation memory and
allows some addresses to be defined as
"significant" for breakpoint purposes. Up
to 8192 breakpoints can be
contemporarily active and breakpoint
detection on a specific location can be
specified in read/write/fetch/op code/
generic or preset value mode.
BREAKPOINT COUNTER: an 8 bit event
counter is also proVided to allow easy

implementation of single/multi-step
program execution.
•

REAL TIME TRACE MEMORY: IKx25
bits of static RAM memory is used to
record, during program execution by the
emulated microprocessor, up to 1024
events, including address, data
read/written, type of cycle
(fetch/read/write) and interrupts.

•

GAMMA-BUS INTERFACE: the interface
with UX8-22 resources takes place by
means of 32 contiguous I/O addresses,
therefore the emulator doesn't share or
request memory resources at UX8-22 level.

•

POD INTERFACE: 13 address lines, 8
data lines, 7 control lines and power
supply lines are proVided for interfacing
with an external POD. Physical connection
is made by means of a 50 wire flat cable.

Figure 1 - Block Diagram

L':::==:"====--===~ ~====:::;-;====:::'....':~~:==~E~~RESS

GAMMA

BUS
INTERFACE

200

~===~~~=====~====~======;===~~==~POO

DATA

LINES

Ordering Information
Type

Description

UX8-GPFM/2

General Purpose Foundation Module for Single Chip Emulation

DOCUMENTATION: The complete technical manual with product description, schematics drawings
and component layout is normally supplied with each product. Technical
manuals are also available separately for purchase.

201

fl.
Z8 Emulation and Development Package
• Designed to run on SGS UXS-22
Development System and to interface with
UXS-GPFM/2 board (General Purpose
Foundation Module) for single chip
microprocessor emulation
• Composed of:
- ZS personality POD
- Software development and
debugging package

• ZS personality POD:
hardware interface between GPFM/2
board (installed inside UXS-22
Development System) and ZS based target
• Software development and debugging
package running on UXS-22 Development
System under CP/M' 2.2, for:
- cross assembling
- cross linking
- debugging

General Description
UXS-EDPZS/2 is an advanced hardware
and software emulation and development
package for the ZS single chip
microcomputer.
The package has been expecially designed
for the SGS UXS-22 Development System

and is composed of 2 separate items:
- ZS personality POD
- Software development and debugging
package

203

General Description (Continued)
The EDPZ8/2 package requires as a
prerequisite at UX8-22 level the
UX8-GPFM/2 Module (General Purpose
Foundation Module for MCU Emulation).
The 28 personality POD is the hardware
interface between UX8-GPFM/2 and a Z8
based user target.
The software development and debugging
package is formed by a cross assembler,
linker loader and debugger for 28

microcomputer; it runs on the UX8-22 under
CP/M 2.2 operating system.
Using the EDPZ8/2 package the designer
can develop software programs and carry out
complete hardware and software debugging of
Z8 based systems using the UX8-22 Development
System. A simple but effective command set
is provided in order to access, read and
modify registers, memory and ports. Breakpoint
and real time trace capabilities are also provided.

Main Features
Z8 Personality POD. Z8 Personality POD
contains the 28 development microcomputer
and the interface circuits both with the
GPFW2 (the general purpose emulation
board) and with the Z8 based target system.
Connections take place at both sides by
means of flat cables.
The POD employs the development

microcomputer Z86l2, adequate for the
emulation of Z8 2K ROM (Z8601) and Z8 4K
ROM (Z8611).
The POD is able both to generate
the clock for the development
microcomputer or to use the signal
of an external clock (switch selectable
option).

Software Development and Debugging
Package
The software development and debugging
package is basically composed of MAKZ8, a
program development package and Z8DBG, a
debugging package.

MAKZ8 - Assembler. MAKZ8 is a powerful
disk-based editor/assembler system for Z8
single chip microprocessor program
development.
It includes also all the features necessary
for the creation/modification of assembly
languages programs for Z8 and file handling,
such as:
Executive for handling all input/output
operation.
Text Editor for creation and modification of

204

source program files.
Assembler: a relocating macroassembler with
cross reference generator and linking loader.

Z8DBG " Debugger. Z8DBG is a software tool
allowing complete debugging of previously
assembled programs.
Its main function are:
- Control of the interface and data transfer
among Z8 personality POD, the general
purpose emulator GPFW2 and system
resources.
- handling of debugging session and
execution of debugging comands required by
the user.

Software Development and Debugging
Package (Continued)

Z8DBG Command List
BAse x I 0 I d
Change/select base of numbers
Break [( options)]
Display/set breakpoint
CB [( addr) I (from) (to)] Clear breakpoints
Cmp [(adl) (ad2) [(count) ]Compare memory
DL [(addr) I (from) (to)] Display memory in listing format
DM [(addr) I (from) (to)] Display/change program memory
DR [(n) I (reg)]
Display/change registers
FM (from) (to) (pat)
Fill memory with pattern
Fr (from) (to) (pat)
Fill registers with pattern
Go [(from)]
Start user program execution
Help
Gives this help
HWTEST
Execute Diagnostic test
Load (file) [ / ]
Load memory from a file
Move (from) (to) [(count)] Move memory block
Next [(steps)]
Single/multi step mode
Quit
Abandon the program
REset
Reset CPU
SAve (file) [(from}[(to)]] Save memory into a file
Set address breakpoints
SB (addr) I (from) (to)
SEarch (from) (pat)
Search pattern in memory
SET [( options) ]
Set/Display system options
SR [(n) I (reg) [(value)] ] Set register
Trace [( count)]
Display traced execution
Use (file)
Execute command file
VE
Enter Execute screen mode
VM [(addr)]
Enter Memory screen mode
VR
Enter Register screen mode
WR
Display working register set

Ordering Information
Type

Description

UXS-EDPZS/2

ZS Emulation and Development Package

DOCUMENTA nON: The complete technical manual with product description, schematics drawings
and component layout is normally supplied with each product. Technical
manuals are also available separately for purchase.

205

II.
Z8 Emulation and Development Package for IBM
Compatible Personal Computers
• Designed to run on Personal Computers
IBM-PC parallel bus compatible.
• Composed of:
- GPFM/2 General Purpose Foundation
Module for single chip emulator
- Z8 personality POD
- Bus interface board between GAMMABUS and IBM-BUS
- Power Supplier (l10/220V - 50/60Hz)
• Software Development and Debugging
package running under MS/DOS
operating system for:
- cross assembling
- cross linking
- debugging

• Hardware features are:
- able to emulate Z8 2K and/or 4K ROM
versions
- 4 Kbytes of emulation memory
- 4 Kbytes of break point memory
- 1 Kbyte of time trace memory
- IBM parallel bus interface
- 8 MHz internal clock or up to 12 MHz
switch selectable external clock
- pulse output (TTL compatible) enabled
every time the PC reaches a Break Point
address

General Description
The EMU-Z8PC is an advanced hardware
and software emulation package for the Z8
microcomputer family.
The package has been especially designed
by SGS to run and interface to IBM
compatible personal computers and is
composed of four main parts:
- the single chip emulator box which contains
the GPFM/2 (General Purpose Foundation

Module), the back panel board and the
main power supplier;
- the Z8 personality POD;
- the interface board;
- the Z8 Assembler, Linker and Debugger
software, delivered on a 5 1/4" single side,
single denSity, Floppy Disk.

207

Hardware Features
GPFM/2. The General Purpose Foundation
Module is a double Eurocard format board,
essentially made up of a random-access
memory (RAM) with a twin access port: from
one side (port), it provides the program
memory required by the development
microcomputer, while, on the other, it opens
access to the common memory, both in read
and write, to the IBM PC host computer. For
more detailed explanations, reference should
be made to the previous chapter
(see page 199).

ZS Personality POD. This is a module which
contains the ZS development microcomputer
and the interface circuits both with the
GPFMl2, contained in the emulation box,
and with the Z8-based target system, the
socket to be inserted into the user board in
place of the emulated microcomputer.
Connections take place on both sides by
means of flat cables. The POD employs the
development microcomputer Z8612 adequate
for the emulation of ZS 2K ROM (Z8601) and
Z8 4K ROM (Z8611). The POD is able to
generate the clock for the development
microcomputer or to use the signal of an
external clock (switch selectable option).

Power Supply. A main power supplier for
220V/50Hz and 110V/60Hz is built inside the

single chip emulator box to supply the
GPFM/2 and the personality POD.

Interface Board. This allows electrical
interface between the GPFM/2 board and the
IBM compatible personal computer bus,
converting the GAMMA-BUS running on
GPFM/2 to an IBM parallel bus. This board
is inserted in the internal personal computer
slot with an addressing range dedicated by

208

the IBM personal computer to prototype card
communication.
Minimum System Configuration Required
- 64K bytes system memory
- 1 disk driver
- alphanumeric and monocromatic video

Software Development and Debugging
Package. The software development and
debugging package is basically composed of
XMAC-Z8, a program development package
and ZSDBG, a debugging package.

XMAC-ZS - Assembler. XMAC-Z8 is a
powerful disk-based editor/assembler system
for ZS single chip microcomputer program
development. It includes also all the features
necessary for the creation/modification of
assembly language programs for Z8 and file
handling, such as:
Executive for handling all input/output
operation;
Text Editor for creation and modification of
source program files;
Assembler a relocating macroassembler with
cross reference generator and linking loader.

ZSDBG - Debugger. Z8DBG is a software
too, running under the MS/DOS operating
system, that allows complete debugging of
previously assembled programs.
Its main functions are:
- control of the interface and data transfer
among Z8 personality POD, the general
purpose emulator. GPFMl2 and system
resources.
- handling of debugging session and
execution of debugging commands required
by the user.

Z8DBG Command List
BAse x I 0 I d
Change/select base of numbers
Break [(options) 1
Display/set breakpoint
CB [(addr) I (from) (to) 1 Clear breakpoints
Cmp [(adl) (ad2) [(count)lCompare memory
DL [(addr) I (from) (to) 1 Display memory in listing format
DM [(addr) I (from) (to) 1 Display/change program memory
DR [(n) I (reg) 1
Display/change registers
FM (from) (to) (pat)
Fill memory with pattern
Fr (from) (to) (pat)
Fill registers with pattern
Go [(from) 1
Start user program execution
Help
Gives this help
HWTEST
Execute Diagnostic test
Load (file) [ / 1
Load memory from a file
Move (from) (to) [(count) 1Move memory block
Next [(steps) 1
Single/multi step mode
Quit
Abandon the program
REset
Reset CPU
SAve (file) [(from)[(to)ll Save memory into a file
SB (addr) I (from) (to)
Set address breakpoints
SEarch (from) (pat)
Search pattern in memory
SET [( options) 1
Set/Display system options
SR [(n) I (reg) [(value) 1 1 Set register
Trace [(count) 1
Display traced execution
Use (file)
Execute command file
VE
Enter Execute screen mode
VM [( addr) 1
Enter Memory screen mode
VR
Enter Register screen mode
WR
Display working register set

Ordering Information
Type

Description

EMU-Z8PC

Z8 Emulation and Development Package for
IBM Compatible Personal Computers

DOCUMENTATION: The complete technical manual (User, Hardware and Installation) with product
description, schematics drawings and component layout is normally supplied
with each product. Technical manuals are also available separately for purchase.

209

Technical and
Application Note5

I

I
I
I

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I
I
I

I
I
I

I
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I
I
I

I
I
I

I
I
I

I
I
I
I

I
I
I
I
I

I
I
I

I
I
I

I
I
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I

I
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I

I
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I

Double Layer P-Vapox and Si3N4 Glass Passivation
A. Panchieri Q.A. MOS DIVISION

Newly developed passivation process for NMOS/HS-CMOS
devices gives improved protection to die encapsulated
in plastic packages.

Process Description

Process Flow

The process consists of a two layer film of PVapox (phosphorus doped silicon oxide) and
Si3 N4 (silicon nitride), obtained by two
different masking and etching steps to avoid
defects caused by lack of dieletric integrity.

(After metal mask)
P-Vapox deposition of 4%
phosphorus concentration

The process gives good metal step coverage
together with PECVD (Plasma Enhanced
Chemical Vapox Deposition) to avoid
cracking near metal edge and possible
hillocks defects.
The double layer enables us, by means of an
appropriate oversize either at the boundaries
of the die side or at the bonding pad side, to
ensure full sealing of the underlying P-Vapox
layer.
This prevents the layer from being exposed
to moisture coming from the package. Thus
the probability of metal corrosion on the
bonding pad due to phosphoric acid is
drastically reduced.

Silicon nitride mask with
oversize on bonding

pad and die boundaries

As a result the die is provided with a very
good humidity immunity.

213
-----~-

----------------

Fig. I - Typical Microsection of Device with Nitride
Passivation.

Fig. 3 - Section Along the Pad

Reliability Results
The reliability performance in moist ambient
was evaluated using both 85°C/85% RH/BIAS
and 121°C Pressure Pot test:
Different products in different plastic packages
were tested.
To give an idea of reliability performances
obtained on products with the new passivation
process, we have set out the process
qualification test results in the following table:

Fig. 2 - Section Along the Scribing Line.

CMOS Logics

Memories

"Processors

Hours

Sample

Fail

Sample

Fail

Sample

Fail

Static/Dynamic
Life Test
TA = 125°C
Vee=std.

1000
2000
3000
4000

1355
915
600
600

0
0
0
0

385
385

0
0

270
270

0
0

Temp Humidity
BIAS (85'C/85% RH)
Vee = std.

1000
2000
3000
4000

740
510
260
259

0
0
I func!.
0

240
240

96
144
192
288

965
775
320
320

0
I func!.
0
0

540
540
300
300

Pressure Pot
TA = 121 °C_2 atm

214

-

-

-

-

-

-

-

-

-

0
0
-

0
0
0
I func!.

360
360
-

250
250
120
120

0
0
-

0
0
0
0

PMZ8: Z8S81 in Single Board Computer Application

The PMZ8 Single Board Computer is a
very small system, based on the Z8681 MCU,
which is one of the ROMless version of the
Z8 single chip microcomputer family.
The Z8681 offers all the outstanding
features of the Z8 family architecture except
the on-chip program ROM. It provides up to
16 output address lines, thus permitting an
address space of up to 64K bytes of data on
program memory. Available address space
(up to 128K bytes) can be doubled by
programming bit 4 of Port 3 (P34) to act as a
data memory select output (DM). The two
states of DM, together with the 16 address
outputs, can define separate data and
memory address spaces of up to 64K

bytes each.
The available address space is mapped
into three devices, with up to 2K bytes each:
one EPROM and one RAM/EPROM for the
program space and one data space RAM.
The EPROM contains the monitor program
(the first 2K bytes), which allows the user to
change the content of memory and registers,
load or save the memory from and to a Host
System and to run programs. The second 2K
bytes of address space in the data space are
further decoded to four strobe lines
(WREXO/l and RDEXOIl), which permits the
addition of two 8-bit input and two 8-bit
output ports externally.

Operation
Start Up. After power- on or reset, the ports,
the timer and the stack pOinter are
initialized. No interrupt is enabled. After
that, the memory device in the IC 5 socket is
tested. If this device is an EPROM, the
program therein is started from location
OOCH; otherwise, the monitor software is
entered. This auto start feature permits
starting a user program without any
keyboard entry.
In the user program, the location OOOCH
must not contain OFFH (NOP).
Terminal. The PMZ8 can be operate with
any ASCII terminal, using the following
set-up:
9600 BAUD
8 DATA BITS
I or 2 STOP BITS
NO PARITY
XON-XOFF PROTOCOL
No hardware handshake (CTS/RTS, etc.) is
provided.

Monitor. The monitor software provides the
following commands:

? . . . . . . . . . . . . . ..

Help (display this)

c[*,/]

Change memory content

[addr].....

d[ *,/] [addr].....

Dump memory content

g[addr] . . . . . . . . ..

Go and execute program

I . . . . . . . . . . . . . . ..

Load from host

r[reg] . . . . . . . . . ..

Dump or change register

s<*,/>addr,leng.

Save to host

t. . . . . . . . . . . . . . ..

Test (terminal)

Upper and lower case letters are treaded as
the same. All numbers are in hexadecimal.
H*" and HI" indicate the selected memory
space, where H*" is the program space and
HI" is the data space.
215

Operation (Continued)
c: Change Memory Content. The type of
memory (* or I) is the last one use if not
specified. The address of the location to be
changed must be entered. The type of
memory, the current address and the current
content will be displayed, and the user may
or may not enter a new value for that
location. The input will be accepted after the
following keys:
RETURN The new value (if any) will be
stored, and the next location will
be displayed.
The new value (if any) will be
stored, and the previous location
will be displayed.
The new value (if any) will be
stored, and the current location will
be displayed again.
q

The new value (if any) will be
stored, and the c-Command will be
terminated.

d: Dump Memory Content. The type of
memory (* or /) is the last one used if not
specified. If the address is not specified,
then it is the address of the location which
would be displayed next if the previous
command was also a d-Command. The
memory content is displayed in HEX, and in
ASCII, if possible.
g: Go and Execute. If the address is not
specified, OOCH is used.

216

1: Load from Host. The type of memory, the
address and the length will be sent by the
host.
r: Dump or Change Register Contents. If
no register number is specified, then a
complete dump of all registers takes place.
Otherwise, the register number, the
abbreviation (if any) and the current content
is displayed. The software doesn't take
account of write only or read only registers.
The input of new values is the same as
described above for the c-Command.
s: Save Memory Content to Host. The type
of memory, the address and the length must
be specified. The content of the specified
memory block is sent in pure bynary, and
the software running on the host is
responsible for converting the data to HEX.
No blocks longer than 2048 bytes may be
transferred immediately.
Monitor Entry Points. There is a jump table
at 800H, which allows the use of some of the
monitor routines, as you can see opposite.
The user program may be simply
terminated by return (AFH). In this case, the
monitor software is re-entered.
If the configuration of the microcomputer
is changed by the user's software, it must be
restored before returning to the monitor.
The monitor uses only the registers from 4
to OFH and some locations below 80H for the
stack.

Operation (Continued)

Routine

Address

Description

800

lPMON

803

lP PUTC

Sends character in R7 to the terminal

806

lP GETC

Waits for character from terminal, returns it in R7

809

lP UNGETC

U ngets one character until next getc

80C

lP GETHEX

Reads HEX number from terminal until first non-HEX character is
entered, returns it in RR4

80F

lP TOUP

Converts character in R7 to upper case, and stores it in R6

812

lP PRTHEX

Prints number in R6 in HEX on the terminal

815

lP PRTCRLF

Prints CR and LF on the terminal

818

lP PRTSTR

Prints string on the terminal: start address of string in RR4; bit 7 high

Restart or start monitor

in last character
81B

lP SPCI

Prints one space on the terminal

81E

lP SPC2

Prints two spaces on the terminal

821

lP SPC4

Prints four spaces on ther terminal

FOC

This is reset entry point.
Jump Table

J
2

0

INTERNAL
TELEPHONESET

-"
INTERFACE
(ANALOG OR
DIGITAL)

I
I

5-7943

EPABX: General Structure

227

Operating Modes
At point C (in Figure I) an alternate
conversation (J or t) controlled by "I" is
possible using the command "* 5". Or a call
conference using the command 4 or a
recall using the command * 6.
For flow chart B the call cannot be picked
up if "I" has a person on hold.

Two basic modes of operation are possible:

Day Service (see Figure I and 2). The
incoming calls from either external trunk line
ring all internal extensions. Any extension
can pick up the incoming call by going
off-hook.
Access to outgoing line is gained by dialling O.

*

c

5-7903

Figure 1. Pick Up an Incoming Call

YES

YES

YES

SET GENERAL
BELL
5-790.4

Figure 2. Generation of an External Ring Signal in Day Service

228

Operating Modes (Continued)
Night Service (see figure 3 and 4). The
incoming calls are routed to one extension
(the operator's telephone set). If the operator
does not answer within 30 seconds, all the
telephone are activated and any internal

extension may pick up the call.
If the operator's extension is busy, with
either an external or internal conversation,
the incoming call will cause a busy tone to
be activated into the operator's connection.

Figure 3. Night Service

5-7906

o

Figure 4. Generation of an External Ring Signal in Night Service

229

Network Configuration
The network permits the connection of up
to 8 internal extensions to the 2 trunk lines.
Up to 4 simultaneous conversations can take
place (2 internal and 2 external maximum).
(see Figure 5 and 6).
Power Supplies and Power Failure. The
EPABX is powered from an AC line. A
power failure will automatically route the two
external trunks to two internal extensions
which will operate normally without AC
power.
PhYSical Description. The EP ABX should be
housed in a wall-mounted enclosure. The
internal lines (telephone sets) and the
external trunk lines are connected to a
terminal strip.
Type of Internal Telephone Set and Line
Resistance. The EPABX uses a standard
48V/30mA telephone set with either pulse or
DTMF dialing. The maximum line resistance
for internal extensions is 1000 ohms.

r ----:

;"1

M079

L _____ "
~-----

5-6626

Figure S. Single Cell Matrix Structure by M079 2x2
Cross Point. for Balanced Connection

The M079 is used in severe conditions (low
attenuation, fully separation of channell, due
to double switches).

r----- ~

EXTERNAL 1

:

,.,

I
I
I
I
L _____ '"'

L..; _ _ _ _ _ oJ

r-----'
~

EXTERNAL 2
INTERNAL 1

--- -- '"'

I'" - - - -

:-1

'"' ____ cI

r----- ,
L _____
~

~

-----.,

'"'-----~
DTMF FROM TONE
BUS GENERATOR
TO
(TONE BUS)
(OTMF
RECEIVE)

DEDICATED
INTERNAL
BUSES

DEDICATED
EXTERNAL
BUSES
5-6625

Figure 6. EPABX (Matrix)

230

INTERNAL 8

Network Configuration (Continued)
- Line status supplied to microprocessor
protection

Internal Circuit Blocks. The main EP ABX
system is divided into the following blocks:
The power supply unit providing - 48V
supply for the telephone sets, 70V/20Hz
ringing voltage with I sec/4 sec modulation,
tone generator for
Busy tone,
- Dial tone,
- Ringing tone,
giving a 425Hz sine wave modulated as
shown in flow chart 1, with an output level of
-lOdBm,

"A" Type must provide:
- Dialling actuator (only for pulse dialling)
"B" Type must provide:
- Ring injection (70V, 20 HZ)
- DC feeding (- 48V)
DONE BY

SGS

z a ROM

A central unit containing the microprocessor
and switching matrix circuits (Figure 7), and
line interface circuitry for 8 local extensions
and two trunk lines. (Figure 8 and 9). Both
Must Perform:

EXT.

R1

R2

INT.

- Galvanic insulation
- DC/AC DC coupling
- AC signal bias (to be treated by electronic
matrix)

5-7942

Figure 7. Switching Matrix Circuit

PULSE

DIALLING
(FROM I'P)
RING

FLAG
(TO I'P)

5-6628

Figure 8. "A" Type: External Interface

STATUS

RINGING
SIGNAL

FLAG

(70V.20Hz)

LINE

TO I'P

5-6629

FROM I'P
FROM PABX
RING SOURCE

Figure 9. "B" Type: Internal Interface

231

Network Configuration (Continued)
Allocation of Numbers for Extensions and
Functions.
Internal extensions 2 to 9
Prefix to a call
o for trunk access
1 for trunk call answer
Suffix during a call 4 for conference call
5 alternate conversation
6 recall/hold
Internal Calls. (see Figure 10). When an
extension is taken "off hook" a dial tone is
received. An extension number from 2 to 9
may be dialled. If the called party is idle, a
ringing tone is received, if the called party
is busy, a busy tone is received.
When the conversation has ended, and one
of the extensions is placed "on-hook", the
other will receive a busy tone.

Outgoing Calls. (see Figure 11). An
outgoing call is initiated when an extension
is taken "off-hook" and a "0" is dialled. If
one of the two trunk lines is free, it will
become available and will be received a dial
tone from the public exchange. There is no
limit on, or control over the number
subsequently dialled.

NO

Figure 10. Internal Calls

232

Figure II. Outgoing Calls

Network Configuration (Continued)
Hold/Recall. (see Figure 12). After a call is
placed on hold by following the appropriate
procedure, another internal or external line
may be dialled. The call 'on hold' may be
recalled by dialling 6 and the previous
conversation resumed.

Alternate Conversation. (see Figure 13).
When a call has been placed on hold and
another conversation initiated, a user may
alternate between the two lines by dialling 5.

Transfer. (see Figure 12). After placing a
conversation on hold and establishing a
conversation with another person, a transfer
may be executed by going "on-hook".
However, a transfer to interconnect two
external lines is not allowed.

Figure 13. Alternate Conversation

Notes:
I is an internal extension and is the master of
the call.
J & K are internal or external but if J & K are
external call conference is allowed.
Alternate calls are controlled (* 5) by the
person who called the 3rd party with 6.
If a person on-hold hangs up, he is
automatically disconnected, and consequently
not found with the * 5 command; the generator
receives a busy tone and the original
conversation can, however, be resumered with
the * 6 command. If the generator goes onhook the second person called becomes the
master (only if the 2nd person called is not a
trunk, otherwise the first person called becomes

*

Figure 12. Hold/Recall and Transfer

Notes:
J can be external or internal
K can be external or internal, transfer will not
take place if J and K one both external.
I is the master of the call and J and K are
"slaves". If the generator goes on-hook the
second person called becomes the master (only
if the second person called is not a trunk,
otherwise the first person called becomes the
master or viceversa). If a slave goes on-hook,
the generator remains the master.

the master or viceversa.

If a slave goes on-hook the generator remains
the master.

233

Network Configuration (Continued)
Conferece Call. (see Figure 14). A
conference call is possible up to a maximum
of either one external and 2 internal
conversations, 3 internal conversations, or 2
external and 1 internal (where allowed).

Notes:
- I, J and M may be:
(a) three internal lines
(b) two internal and one external or viceversa.
- Two external lines can be put inconference.
- I is an internal extension and is the master.
- If I leaves, the second person called becomes
the master (only if the 2nd person called is not
a trunk, otherwise the first person called
becomes the master or viceversa.
- If J or M (slaves) leaves the generator (1)
remains the master.

Flow Chart Comments
In these flow charts the following symbols
are used:
1, J, K, M

user identifications
(internal or external)

n,

trunk lines 1 and 2

T2

dial tone
busy tone
ring back tone

Figure 14. Conference Call

234

self explanatory

*

momentary depression of
the rest (or pushing the
momentary connection
button on phones equipt
with this feature)

1-0

dialling 1 to 0

I...J

connection and
conversation of I with J

E.I.C.

external incoming call

Ring Signals Definition Timing

Tone Definition Timing

425Hz
0.8

Figure 15. Busy Tone Over Speech

1.6

0.8

SEC

Figure 19. General Bell Ring Signal

425Hz

0.2

0.2

0.2

SEC

Figure 16. Definition of Tones, Busy Tone.

425Hz

0.8

3.2

0.8

SEC

Figure 20. Internal Incoming Call, Ring Signal

ON
CONTINUOUS

SEC

Figure 17. Dial Tone

0.8

1.6

0.8

SEC

Figure 21. External Incoming Call, Ring Signal

5-7913

425Hz
0.8

3.2

SEC

0.8

Figure 18. Ring. Back Tone
5-7912

235
------------

General Timing Description
Parameter

Characteristic

Dial pulse internal
- Break space
- Mark space

More than 50 ms. Less than 75 ms
More than 30 ms

Dial pulse on trunk

As generated on internal extension

Inter digit

800 ms

Flash

More than 200 ms - Less than 800 ms

Flash on trunk line

80 ms

On-hook

More than 800 ms

Antibounce on DTMF key

37.5 ms

Delay after freeing the trunk line before
engaging the line again

200 ms

Dial tone

Continuous 425 Hz

Busy tone

200 ms ON/200 ms OFF/425Hz

Busy tone over speech

100 ms ON/3.2 sec OFF/425Hz

Ring back tone

800 ms ON/3,2 sec OFF/425Hz

Internal call ring signal

800 ms ON/3.2 sec OFF

External call ring signal

800 ms ON/1.6 sec OFF

Gen bell signal

800 ms ON/1.6 sec OFF

Antibounce on ext-incoming call signal
receiving

37.5 ms'sec

236

Using Z8 MCU in Keyboard Controller

Introduction
The 28 MCU can be used advantageously
in a professional keyboard controller, with
.
serial scanning.
The principal points on which the
application is based are, in essence:
• Use of a new generation highperformance microcomputer (28), which is
well adapted to real time applications;
and

• implementation of a serial scanning
technique for the matrix, facilitated by
28's remarkable execution velocity, with
the possibility of defining a single
dedicated interface circuit which includes
a limited number of pins (28), and is thus
less cost!y .

Description
It should be particularly noted that, if the
architecture and the software available in the
28 MCU are used in a timely way, it is
possible to achieve scanning times at a level
of 2.7 msec for 128 keys with the 8 MHz 28.
Using faster versions (12 MHz), it is possible
to achieve shorter scanning times.
The matrix interface circuit interacts with
Z8 by means of 2 lines:
• CK coming from 28; and
• IN going toward 28.
The CK signal is generated by 28 and
enables the column counter and the line
multiplexer with its rising edge.
The circuit interfaces with the matrix via
the 16 enabling column outputs in opendrain, and the 8 line inputs.
For these inputs, the specific thresholds
(VILmax = 1.5 V) guarantee a correct
interface with the matrix.
During the micro's initialization phase, this
takes place when the interface matrix is
reset, transmitting a timely impulse to the IN
pin, which thus becomes bidirectional.
This arrangement permits leaving out a

less reliable function, power-on reset, which
is built into the device, without adding it to a
later pin, which would result in the package
being carried to a higher pin number (40),
thus at a higher cost.
The complexity of the interface function
has been valued at the equivalent of about
200 gates.
The other functions available in the
keyboard, namely: mouse control; and serial
conversation control synchronized with the
P.C. can be easily worked out using 3 of the
4 external IRQ pins.
These vectorized interrupt requests can be
masked and prioritized through use of
software. An eventual function, namely
controlling asynchronous serial conversation,
can be freely obtained, since it already exists
in the 28. In this case, one of the 2 internal
timers is used as a baud rate generator.
Driving eventual LEDs (caps lock, number
lock) can be achieved directly by
programming the respective pins of port 2 in
open-drain. Using LED limiting resistance in
series, the typical level of current of 10 rnA
can be programmed.

Note Concerning the Block Diagram
It is possible to write a single program
which can automatically recognize if the
device being used is a 28 ROMless or a 28
masked. This permits an immediate
branching from the version with external

EPROM to that using 28 2K/4K ROM. The
test is applied to bits D3 and D4 of register
248 (MODE REGISTER PO and PI)
immediately after reset.

237

Note Concerning the Printout
This type of coding permits:
• Branching from the previous state Sl S2
to the new state S2 IN by retaining a bit
from the previous state (S2) and
introducing the real state of the key (IN).
Status updating is, therefore, easily
achieved through rotation and shift
operations .

Status is coded on 2 bits. The status table
is made up of 32 bytes with 4 states per byte.
The status coding used is the following:

• A simple test for a valid key: the valid
key (on or off) is identified by having the
2 status bits identical (00, 11). This
permits testing key validity and jumping
to the corresponding service routine,
using the single instruction JR NOV,
OUT. The previous instruction on rotation
really sets an overflow bit if the two status
bits are different.

ON
VALID
S -8109
O.KEY OFF
I.KEY ON

Z8
U SING ROM less VERSION
- - - - - --- - -- ---- -

r-

P0 7

- ---------,

I
1

1
1
1

I

As.;.All

I

,

I

EXTERNAL
PROGRAM
MEMORY

~

Y--

e
MATRIX
16d

PORTO
POO ,;,P03

I
1
I
I
I

KEYBOARD
ENCODER

,

LATCH

ADO,..A07

J
----.-- ---

~

-

------------- -

I
I
I
I

PORT 1

I
I

P27

1

I
I

I
I

PORT2

~

P2 1

16

~

----

P2 0

-"..

~

/Z

/'CI

)

vec
PORT 3
P3 0 P3 1

RX
IRa
MOVE

r

P3 2 P34 P3 7

I

a
Ya

S-8108

Figure I. Block Diagram

238

TX

Program Routine

A>TYF'E KEYX.ASII
RBASE: EaU
OEOH
TPTR:
EaU
RBASE+13
NSCAN: EaU
RBASE+14
NBYTE: EaU
RBASE+15
ORG
OCH
lD
P211,tO
lD
P311,tOl
lD
P011I,t45H
;KEY INPUT ON POO
lD
TPTR,t10H
lD
NBYTE,t20H
lD
R7,tOFFH
OPEN:
lD
@TPTR,R7
INC
TPTR
DJNZ
NBYTE,OPEN
lD
R4,teOH
lD
R5,t7FH
OR
R2,R4
lD
NBYTE,t01
lD
NSCAN,tOl
JR
IN
STARTO: lD
TPTR,tOFH
lD
NBYTE,t20H
START1: lD
NSCAN,t04
INC
TPTR
START2: Rl
@TPTR
Rl
@TPTR
RRC
RO
OR
R2,R4
RRC
@TPTR
RRC
@TPTR
JR
NOV,OUT
IN:
AND
R2,R5
RL
@TPTR
Rl
@TF'TR
DJNZ
NSCAN,START2
DJNZ
NBYTE,START1
JR
STARTO
OUT:
JR
IN

iBASE FOR WORKING REGISTERS
;R13=TABlE POINTER (TPTR)
iR14=COUNTER OF N. OF SCANNING INTO THE TABLE (4)
iR15=CQUNTER OF N. OF BYTES INTO THE TABLE (32)
iP20-P27 OUTPUTS,ClK OUTPUTS ON P27
iP2 WITH PUll-UPS ACTIVATED
iP10-P17 OUTPUTS,POO-P07 INPUTS,INTERN.STACK
iPOINTER TO 1ST BYTE TO PRESET
iNUIIBER OF BYTES TO CLEAR
illASK TO PRESET STATUS TABLE
iPRESET All KEY STATUS TO OPEN CONDITION
illASK TO RESET ClK
illASK TO SET ClK
iRESET ClK

iTPTR=STARTING @ OF STATUS TABLE HINUS ONE
iNBYTE=NUIIBER OF BYTES INTO THE TABLE
iNSCAN=N. OF SCANNING TO DO FOR EACH BYTE

iSHIFT INPUT TO CARRY FLAG
iRESET elK
iGENERATE NEW STATUS ON BITS 6 AND 7
;TEST NEW STATUS AND GO OUT IF IT'S 00 OR 11
iSET ClK
iPREPARE THE TABLE FOR THE NEXT KEY VALUE
jCHECK IF All THIS BYTE IS SCANNED
iCHECK IF THE TABLE IS COHPLETED
JAT THE FIRST KEY JP TO STARTO

239

Z8 MCU in Dynamic Keyboard
The Measurements of Pressure Velocity on the Keyboard
of a Musical Instrument

Introduction
Among the characteristics requested from
new generations of musical instruments, in
particular the piano effect, is the control of
amplitude in connection with the velocity of
keyboard pressure, in other words, the socalled dynamic keyboard.
Software using the ZS and supported by
the M112 has been studied by SGS in order
to permit the creation of a dynamic keyboard
with unlimited poliphonicity, up to a
maximum of 104 usable keys on one or two
keyboards.
The ZS/D, which may be considered as a
standard component for this function,

together with the M112, makes it possible for
builders of musical instruments to create a
dynamic keyboard without having to develop
the software or to use complex and costly
circuits.
The number of M112s used together with
the Z8/D depends on the poliphonicity
desired, given the fact that each Ml12
provides a polyphonicity of S notes.
The circuitry necessary for each channel's
configuration is significantly reduced thanks
to the M112's characteristics of being able to
carry out internally the SUSTAIN and
RELEASE phase.

Main Characteristics
• The number of usable keys is
programmable from 40 to 104.
• Contact may be made by a double bar or
by a double rubber contact.
• Total polyphonicity, limited only by the
number of M112s and by the velocity of
the master/micro.
• Asynchronous conversation with master
micro.
• 21 tables which speCify the amplitude of
the sound identified in relation to flight
time (key speed).
• 2 output forms for each key, arranged for
choice among the 21 available.
• Each table consists of 15 words of 6 bits
each.
• Transition time between the two bars:
min. 3 ms and max. 39 ms with CK = 8

MHz (from 0 to 3 ms, equals maximum
amplitude, while, beyond, 39 ms equals
the minimum level).
• Possibility to change the transition time by
varying the CK.
• Exclusion of rebounds on either bar.
• Sending reset tEl master/micro during
initialization and in case of error.
• Percussive and/or sustained effects.
• Each key is defined by 14 bits in the
following way: 7 bits codify the key
number from 0 to 103; 1, the condition of
the key; 6 codify the amplitude.
Note: the M112s should have 3V ± 10% on pin 12
(Vt); HOLD command = 0 and the code for attack
time should never be al = a2 = a3 = O. Thus the
RELEASE phase can be controlled by the M112.

Operation
The keyboard, or keyboards, the extension
of which is programmable, make up a matrix
of 8xN (Nmax = 13, or in other words, 104

keys max.) and every N line is made up of 2
bars, one for release and the other for
pressure (see Figure 8) - the double contact

241

Operation (Continued)
rubber can also be used (see Figure 9).
Keys not being used are in contact with
the release bar and when they are played,
they touch the pressure bar.
Transition time between one bar and the
other, which we will call "flight" time, does
not include rebounds insofar as the count
starts from the last rebound on the release
bar and ends with the first contact with the
pressure bar.
The calculation of flight time takes place
by increasing, every time the keyboard
shifts, a 4-bit counter with which a pair of
tables chosen by the user from among the 21
available can be addressed.
Acquisition of the two tables selected and
of the number of keys is only possible at
mains on.
The time for a shift cycle represents the
basic measuring unit of "flight" time and
thus is fixed at a constant value of 1.5 ms
through use of the ZS/D's internal timer with
CK=S Mhz.
The first 5 steps are increased every 1.5 ms,
while the successive 10 are every 3 ms.
A key is considered pressed at its first
contact with the pressure bar, and released
at its first contact with the release bar;
eventual rebounds, even unlimited ones on
the same bar, are ignored.
The ZS/D microprocessor reads the
keyboard in a sequential· mode and measures
flight time for each key that is pressed; that

of release is not taken into consideration.
This time can thus only assume 15 discrete
values.
Each of these 15 values addresses a pair of
amplitudes or levels which should have the
note which corresponds to that key.
The micro ZS/D will present on 6 pins (3
associated with port PO and 3 associated with
P3) the code for the first amplitude. After 2
p-s, the 3 pins PO (234) which serve, through
the use of 3 input AND to strobe and thus
memorize this first amplitude, are set to l.
The second amplitude is made available on
the same 6 pins, 20 p-s after the first, and is
maintained until the release of the key or
until the successive output (see Figure 3).
The acceptance of keys by the ZS/D is
conditioned by the velocity of the acquisition
of the master/micro with respect to the
quantity of variations of keys in the unit of
time.
In order to not limit polyphonicity because
of excessive slowness of the master/micro, a
FIFO type memory area, has been prepared
inside the ZS/D, capable of holding up to 10
variations ready for the master/micro to use.
The ZS/D micro accepts any key pressed
indistinctly, taking account of the fact that
those coming after filling the FIFO are lost.
The decision of which keys to send to the
M 112 and thus to play, is left to the
master/micro.

Communicating with the Master/Micro
At switch on, the ZS/D puts, on port PI,
the code FF which is received by the
master/micro and interpreted as a reset.
This code is also sent when, for any
reason, the FIFO finds itself in an anomalous
condition - for example when the read
counter is more advanced than the write
pointer. In effect this could leave the "keys
pressed" and never cancell them again.
It is therefore necessary that the master
micro cancels all pressed keys ithas in
memory when it receives FF.
All data supplied by the ZS/D is comprised
of 14 bits which have the follOWing format:
-

7 bits (Plo - PIG) give the key number
with Plo being the LSB.

-

1 bit (PI7) gives the key condition
(l = pressed)

-

6 bits (PO[567] and P3[567] give the two
amplitudes with P05 being the LSB.
Transmission is asynchronous with two
signals from the ZS/D being used: DAV (P34)
which, when a "1", signals to the
master/micro that data is ready to be
transmitted and RDY (P33) which must go to
"1" to alow the ZS/D to make the data
available on its ports.
28/0
AMP

d

P3(S.6.7)

6

P1

PO(S.6.?)

P'4
P33

DAY

MICROI
MANAGEMENT

ROY
S 7863

Figure 1

242

Communicating with the
Master/Micro (Continued)
The timing shown in Figure 2 is relative to
an 8MHz clock.

h = 53 p,s

DAV can go to "1" only if RDY is zero and
vice versa.
a= 972 p,s

When this time has passed, the
data is complete, but the partial
times are:
* 13 p,s OUTPUT PI (TP and
Key No.)
* 33.5 p,s OUTPUT first
amplitude with related strobe
* 55 p,s OUTPUT second
amplitude

b= 16.5 p,s If, however, RDY is not yet at
zero, DAV will wait until it goes
to zero and, then, after 2.5 us,
will go to "1".

i = 4 p,s

c,e,g,m:

n can vary from 7 p,s to 1.5 ms.

d = 7 p,s

These times depend on the
master/micro. However they
should not be less than zero.

Figure 3 shows the detailed timing
beginning from the switching of RDY, in
other words, from the request for new data
and on the supposition that such data is
already available:

In this case, RDY cannot last less
than 7 p,s.

f can vary from 150 p,s to 1.5 ms.

The data on PI and those concerning the
second amplitude remain stable until the
next switching of RDY.
SET-UP

RESET

......

-

OUT

-

FF

g

a

b

I--

I

c d

h

;

T1

r--

r

RDV

m

T2 PRESSED

+

- -l-

DAV

T1 PRESSED

-

-- -

. """"""-

T2

I--I
f

g

I

h

I

mt

-

I---'

5-&277

Figure 2

)!C

Pf
13IJs

OUT VALID

.I

fST
AMPLITUDE

/k
31.5JJs

J_

OUT VALID

""5

2}JS

STROBE

)!C

J

J

PO(234)=1

2ND

OUT VALID

AMPLITUDE

53)Js
5-'1864

Figure 3. RDY Timing

243

Typical Application
Possible applications of ZS/D are many; in
this note, two of these are shown, related to
percussive effects.
The technique used in this application is
bused on the fact that the attack phases are
not contemporary, in other words, it is not
possible to have two or more keys with their
attack time overlapping.
This first application allows the saving of a
latch or sample and hold for each channel,
however the cross-over level between two
note decay levels of will not be defined and
thus this point must be defined by a timer
which, in this case, is made up of rd and
Cd.
The following waveforms demonstrate the
movement in the signals concerning
diagram, in Figure 10.
Ta

(Ro(405l)+Ro(D/A))*C = - I
Kohm*C

Td

RD * C (RD can be controlled with
the assistance of a duty-cycle
variable oscillator)

Ts

3Mohm * (3Mohm is the internal
resistance to M 112 connected to the
mass)

Tr

Rp * C (Rp is the internal resistance
to Ml12 programmable among r I, r2
and r3)

St.D and ta are generated by the
master/micro:
• St.D is the strobe for data transmission for
the M112. The negative transition renders
the Ml12 data operational, and initiates
the attack phase of the external
development circuit.
• ta, which should begin before the defined
St.D, with its negative transition, the
attack phase. This time is quite well
controlled by the master/micro because,
given the characteristics of this
application, the next key can begin the
attack phase only at the end of the
present tAo
• td is the decay phase time, which should
not be confused with the time constant
Td; its value is determined by the
product rd * Cd and by the threshold of
4503.
The second application (see Figure II),
requires a temporary memorization of the
SUSTAIN level for each channel,
however, it permits better envelope
control.
In fact, the DECAY phase now tends
toward a digitally controlled level and
thus the cross-over point between the two
slopes is perfectly calculable even to the
variation of maximum size in relation to
minimum key pressure.

Tp represents the time interval during which
the key is pressed.

St.D

t.

Tp

t.

---1l~--------------~n~------.-J
i

--~I1:~----------~-----

~
~:'1
~3~------------~

MICROI

Z8/D

>--4--+-~---------1

MANAGEMENT

3ST

4069

5-1866

OUT

Figure 5. Circuit to Read Tables Resident in the Master/Micro

Flying
time
(ms)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

3
4,5
6
7,5
9
12
15
18
21
24
27
30
33
36
39

63
63
63
62
60
53
47
44
43
42
40
38
36
35
34

63
63
62
59
54
46
43
39
37
34
32
30
29
28
28

63
62
61
58
50
42
40
38
36
33
30
29
28
28
27

63
62
60
58
56
51
49
47
45
40
35
32
30
27
22

63
61
58
54
47
43
42
41
40
37
34
31
29
27
26

63
61
56
51
47
45
43
42
42
40
37
35
34
34
34

63
59
52
47
41
35
34
33
32
31
29
28
27
25
24

63
56
48
43
39
36
35
34
34
33
31
29
27
26
24

63
52
45
41
39
37
37
35
34

54
51
49
47
44
40
35
32
30
28
27
26
25
24
24

48
44
42
39
37
33
31
29
27
26
26
25
24
24
24

45
42
36
30
27
25
25
24
24
24
24
23
23
23
22

44
40
37
35
33
30
28
27
26
25
25
25
24
24
24

40
37
35
33
32
29
27
26
25
24
24
23
23
23
22

31
33
35
36
34
31
29
29
28
27
27
26
25
24
24

29
31
32
32
30
28
27
26
26
25
25
24
24
24
23

28
30
32
33
34
33
30
28
27
26
25
25
24
24
24

28
29
30
30
29
27
36
25
25
25
24
24
24
23
23

27
28
29
30
31
32
32
32
31
30
28
26
26
25
24

26
27
27
28
28
29
30
30
30
29
28
26
25
24
24

1
2
3
4
5
6
7
8
9
10

34

31
29
27
26
24

11

12
13
14
15

Tab. 1. Table of Amplitude Codes Against Fligth Times

245

VIN (V)
M112

5

4

3.5

2.5
17
18
19

2

1.5 +--r-~~--'----r-~-~-~-~-..,--~--'----r-~_ _+(ms)

o

3

6

9

12

15

18

21

24

27

30

33

FLYING

36

TiME
CK=8MHz

39

5-7867

Figure 6. Layout of Tables Resident in the ZS/O

lOUT
/J A/K
33

/

30

/

27

I

/

24

/

21

/

18

/

15

/

/
/

12

/

/

9
6

I

/

./

./

0 +----r---,---=.=~~--~----~--~--~----~--~--~VIN
(V)
4.5
5
3.5
4
2
2.5
3
1.5
0.5
0
5-7868

Figure 7

246

•
•
•

N0
1

T8

T2

~
T16

2
3

T10

----.r-

~

T26

T32

6
7

~

8
9

T34

~

T50

T64

14
15

~

T72

~

TBO

1B
19

~

T8B

20
21

T82

----.rT96

22
23

----.r-

~

T98

T104

24
25

- 0
1

12

" 2

13

/I

3

2

14
15

"

4

3
4

JNH

A

PO

r--

2<'\7
12K.ll

81<--C

ID

: y 7 Y / ")Ii Y 9~
/' / / / / Y Y 7 7 7
~
~

/

~

Y /

PAIR OF TABLES

KEY N.e.

(Two diodes)

(One diode)

~

~~
~
~

1
I
I
I
I

P2

7

0
1 P1
2

'--5-7869

Figure 8. Diagram of Double Bar Keyboard and Commands

247

o

Figure 9. Diagram of Double Rubber Contact Keyboard

248

~~======:)j P2

lC=z===~

P1

t=~======~

Z8/D

ROY

MICRO I

P331+-----'-~------lMANAGEMENT

PO

ta

HOLD =0
Vr=3V

r-_..L.::.a1:..;=:!a::2 ~~~:p~e~01
St.01

Li'i
0

~-~4-~~~-~~~~CH1

.....

I
I

.,..

I

I

:M112/1

..,..

r

Li'i

0

I

V

.....

..,..

I

!

I

~-~+4-{~-+--4~~~CH8

I

lOon

5-7871

Converter D/A

P37
32

P36
16

P3s
6

PO,
4

pOG
2

POs
1

Figure 10. Diagram for Percussive Effects

249

P2

Z8/D
PO

8
P1
P34
P33

OAV
ROY
MICRO'
MANAGEMENT

4051

~~-.----~~~~~--~-r++--~FH1

I

I Ml12/1

ta

I

51.01

I

I

I
I
I

~~~.-r-~~-C~~~~~~CH8

5-7873

Figure 11. Diagram for Percussive Effects

250

Comparison of Z861 1. 8051 and MC6801 Microcomputers

Introduction
The microcomputer industry has recently
developed single-chip microcomputers that
incorporate on one chip functions previously
performed by peripherals. These
microcomputer units (MCUs) are aimed at
markets requiring a dedicated computer.

This report describes and compares the
most powerful MCUs in today's market: the
Z8611, the 8051, and the MC680 1. Table I
lists facts that should be considered when
comparing these MCUs.

FEATURES

Z8611*

8051

MC6801

On-Chip ROM

4Kx8'

4Kx8

2Kx8

General-Purpose
Registers

124

128

128

Special-Function
Registers
Status/Control
I/O ports

16
4

16
4

17
4

32
Four 8·bit
None

29
Three 8-bit, one 5-bit
Hardware on one port

5
2
5
2 Programmable

7
2
7
Nonprogrammable

1/0
Parallel lines
Ports
Handshake

32
Four 8-bit
Hardware on

three ports

Interrupts
External source
Vector
Priority

8
4
6
48 Programmable

Maskable

6

5

6

External
Memory

120K bytes

124K bytes

64K bytes

Stack
Stack pointer
Internal stack

16·bit
Yes, uses

8·bit
Yes

16-bit
Yes

External stack

8-bits
Yes

No

Yes

Two 16-bit
or two 8-bit
No prescale
with 16-bits;
5·bit prescale
with 8·bits

One 16·bit

Source

orders

orders

Counter lTimers
Counters

Two 8-bit

Prescalers

Two 6-bit

None

, 28601 =2K ROM version

Table I. MCU Comparison

251

Introduction (Continued)

FEATURES
Addressing
Modes
Register
Indirect Register
Indexed
Direct
Relative
Immediate
Implied

Z8611 *

8051

MC6801

Yes

Yes

No

Yes
Yes

Yes

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

124, Any generalpurpose register

I, Uses the
accumulator for
8-bit offset

I, Uses 16-bit index
register

Interface
Full duplex UART
Interrupts for transmit

Yes

Yes

Yes

and receive

One for each

One for both

One for both

Registers Double
buffer

Receiver

Receiver

Transmitter/Receiver

62.5K bls
@8MHz

187.5K bls
@12 MHz

62.5K bls
@4MHz

2.2 !,sec
4.25 !,sec

1.5 !,sec

3.9 !,sec

Longest instruction

4!,sec

10 !,sec

Clock Frequency

8 MHz*

12 MHz

4 MHz

Power Down Mode

Saves first 124

Save first 128
registers

Saves first 64 registers

Saves PC;

Saves PC, PSW,
accumulators, and Index

Index
Registers

Serial
Communication

Serial Data Rate

Speed
Instruction execution
average

registers

. Context Switching

Saves PC and flags

programmer must

save all register

register

Development

40-Pin ROMless
(Z8681182/84)

40-Pin (8751)

40-Pin (68701)

Eprom

4K bytes
8K bytes

4K bytes

2K bytes

• Z8601 =2K ROM version

Table I. MCU Comparison (Continued)

252

Architectural Overview
The three chips have somewhat similar
architectures. There are, however,
fundamental differences in design criteria.
The 8051 and the MC6801 were designed
to maintain compatability with older
. products, whereas the Z8611 design is free
from such restrictions and incorporates many
new ideas. Because of tYtis, the accumulator
architectures of the MC6801 and the 8051
. are not as flexible as that of the Z8611, which
allows any register to be used as an
accumulator.

Memory Spaces. The 28611 CPU
manipulates data in four memory spaces:
• 60K bytes of external data memory
• 60K bytes of external program memory
• 4K bytes of internal program memory
(ROM)
• 144-byte register file
The 8051 CPU manipulates data in four
memory spaces;
• 64K bytes of external data memory
• 60K bytes of external program memory
• 4K bytes of internal program memory
• 148-byte register file
The MC6801 manipulates data in three
memory spaces:
• 62K bytes of external memory
• 2K bytes of internal program memory
• 149-byte register file

On-Chip ROM. All three chips have internal

registers each. In the first group, the lowest
four registers are the I/O ~ort registers. The
other registers are general purpose and can
be accessed with an 8-bit address or a short
4-bit address. Using the 4-bit address saves
bytes and execution time. Four-bit short
addresses are discussed later. All generalpurpose registers can be used as
accumulators, address pOinters, or Index
registers.
The 128 general-purpose registers in the
8051 are grouped into two sets. The lower 32
bytes are allocated as four 8-register banks,
and the upper registers are used for the
stack or for general purpose. The registers
cannot be used for indexing or as address
pointers.
The MC6801 also has a 128-byte, generalpurpose register bank, which can be used as
a stack or as address pointers, but not as
index registers.
The main contrast is that any of the 28611
general-purpose registers can be used for
indexing; the MC6801 and the 8051 cannot
use registers this way. The 28611 can use
any register as an accumulator; the MC6801
and the 8051 have fixed accumulators. The
use of registers as memory pointers is very
valuable, and only the 28611 can use its
registers in this way.
The number of general-purpose registers
on each chip is comparable. However,
because of its flexible design, the 28611
clearly has a more powerful register
architecture.
The Z8611 has 20 special function registers
used for status, control, and I/O. These
registers include:
• Two registers for 16-bit Stack Pointer
(SPH, SPL)
• One register used as Register Pointer for
working registers (RP)

ROM for program memory. The 28611 and
the 8051 have 4K bytes of internal ROM, and
the MC6801 has 2K bytes. In some cases,
external memory may be required with the
MC6801 that is not necessary with the 28611
or the 8051.

• One register for interrupt mask (IMR)

On-Chip RAM. All three chips use internal

• One register for interrupt request (IRQ)

RAM as registers. These registers are
divided into two categories: general-purpose
registers and special function registers
(SFRs).
The 124 general-purpose registers in the
28611 are divided into eight groups of 16

• Three mode registers for the four ports
(PIM, P2M, P3M)

• One register for the status flags (FLAGS)
• One register for interrupt priority (IPR)

• Serial communications port used like a
register (SIO)
• Two counter/timer registers (TO, TI)
253

Architectural Overwiev (Continued)
• One Timer Mode Register (TMR)
• Two prescaler registers (PREO, PREll

• Two registers for 16-bit output compare
used with timer

• Four I/O ports accessed as registers
(PORTO, PORT!, PORT2, PORT3)

• Four data direction registers associated
with the four I/O ports

The 8051 also has 20 special function
registers used for status, control, and I/O.
They include:

• Four I/O ports

• One register for the Stack Pointer (SP)
• Two accumulators (A, B)
• One register for the Program Status Word
(PSW)
• Two registers for pointing to data memory
(DPH, DPL)
• Four registers that serve aS,two l6-bit
counter/timers (THO, THl, TLO, TLl)
• One mode register for the counter/timers
(TMOD)
• One control register for the counter/timers
(TCON)
• One register for interrupt enable (lEC)
• One register for interrupt priority (IPC)
• One register for serial communications
buffer (SBUF)
• One register for serial communications
control (SCON)
• Four registers used as the four I/O ports
(PO, PI, P2, P3)
The MC6801 has 21 special function
registers used for status, control, and I/O.
These include:
• One register for RAMIROM control
• One serial receive register
• One serial transmit register
• One register for serial control and status
• On serial rate and mode register
• One register for status and control of
port 3
• One register for status and control of the
timer
• Two registers for the 16-bit timer
• Two registers for l6-bit input capture
used with timer
254

The special function registers in the three
chips seem comparable in number and
function. However, upon closer examination,
the SFRs of the MC6801 prove less efficient
than those of the Z8611. The MC6801 has
five registers associated with the I/O ports,
whereas the Z8611 uses only three registers
for the same functions. The MC6801 uses
four registers to perform the serial
communication function, whereas the Z8611
uses only one register and part of another.
The 8051 uses two registers for the
accumulators; the Z8611 is not limited by this
restriction. The 8051 also uses two registers
for the serial communication interface,
whereas the Z8611 accomplishes the same
job with one register. Another two registers
in the 8051 are used for data pointers; these
are not necessary in the Z8611 since any
register can be used as an address pointer.
The Z8611 uses registers more efficiently
than either the MC6801 or the 8051. The
registers saved by this optimal design are
used to perform the functions needed for
enhanced interrupt handling and for register
pointing with short addresses. The Z8611 also
supplies the extra register required for the
external stack. These features are not
available on the 8051 or the MC6801.

External Memory. AI! three chips can
access external! memory. The Z8611 and the
8051 can generate signals used for selecting
either program or data memory. The Data
Memory strobe (the signal used for selecting
data or program memory) gives the Z8611
access to 120K bytes of external memory
(60K bytes in each program and data
memory). The 8051 can use 124K bytes of
external memory (64K bytes of external data
memory and 60K bytes of external program
memory). The MC6801 can access only 62K
bytes of external memory and does not
distinguish between program and data
memory. Thus, the Z8611 and the 8051 are
cleary able to access more external memory
than the MC6801.

Architectural Overwiev (Continued)
On-Chip Peripheral Function. In addition
to the CPU and memory spaces, all chips
provide an interrupt system and extensive
I/O facilities including I/O pins, parallel I/O
ports, a bidirectional address/data bus, and
a serial port.
Interrupts. The 28611 acknowledges
interrupts from eight sources, four are
external from pins IRQo-IRQ3, and four are
internal from serial-in, serial-out, and the
two counter/timers. All interrupts are
maskable, and a wide variety of priorities are
realized with the Interrupt Mask Register and
the Interrupt Priority Registers (see Table 1).
All 28611 interrupts are vectored, with six
vectors located in the on-chip ROM. The
vectors are fixed locations, two bytes long,
that contain the memory address of the
service routine.
The 8051 acknowledges interrupts from
five sources: two external sources (from INTO
and INTl) and three internal sources (one
from each of the internal counters and one
from the serial I/O port). All interrupts can
be disabled indiVidually or globally. Each of
the five sources can be assigned one of two
priorities: high or low. All 8051 interrupts
are vectored. There are five fixed locations
in memory, each eight bytes long, allocated
to servicing the interrupt.
The MC6801 has one external interrupt,
one nonmaskable interrupt, an internal
interrupt request, and a software interrupt.
The internal interrupts are caused by the
serial I/O port, timer overflow, timer output
compare, and timer input capture. The
priority of each interrupt is preset and
cannot to be changed. The extenal interrupt
can be masked in the Condition Code
register. The MC6801 vectors the interrupts
to seven fixed addresses in ROM where the
16-bit address of the service routine is
located.
When an interrupt occurs in the 805!, only
the Program Counter is saved; the user must
save the flags, accumulator, and any
registers that the interrupt service routine
might affect. The MC6801 saves the Program
Counter, accumulators, Index register, and
the PSW; the user must save all registers that
the interrupt service routine might affect.
The 28611 saves the Program Counter and
the Flags register. To save the 16 working

registers, only the Registers Pointer register
need be pushed onto the stack and another
set of working registers is used for the
service routine.
With regard to interrupts, the 28611 is
cleary superior. The 28611 requires only one
command to save all the working registers,
which greatly increases the efficiency of
context switching.

I/O Facilities. The 28611 has 32 lines
dedicated to I/O functions. These lines are
grouped into four ports with eight lines per
port. The ports can be configured
individually under software control to
provide input, output, multiplexed
address/data lines, timing, and status. Input
and output can be serial or parallel, with or
without handshake. One port can be
configured for serial transmission and four
ports can be configured for parallel
transmission. With parallel transmission,
ports 0, I, and 2 can transmit data with the
handshake provided by port 3.
The 8051 also has 32 I/O lines grouped
together into four ports of eight lines each.
The ports can be configured under program
control for parallel or serial I/O. The ports
can also be configured for multiplex
address/data lines, timing, and status.
Handshake is provided by user software.
The MC6801 has 29 lines for I/O (three
8-bit ports and one 5-bit port). One port has
two lines for handshake. The ports provide
all the signals needed to control input and
output either serially or in parallel, with or
without multiplexed address/data lines. They
can be used to interface with external
memory.
The main differences in I/O facilities are
the number of 8-bit ports and the hardware
handshake. The 28611 and the 8051 have
four 8-bit ports, whereas the MC6801 has
three 8-bit ports and an additional 5-bit port.
The 28611 has hardware handshake on three
ports, the MC6801 has hardware handshake
on only one port, and the 8051 has no
hardware handshake.
CounterlTimers. The 28611 has two 8-bit
counters and two 6-bit programmable
prescalers. One prescaler can be driven
internally or externally; the other prescaler is
driven internally only. Both timers can
255

Architectural Overwiev (Continued)
interrupt the CPU when counting is
completed. The counters can operate in one
of two modes: they can count down until
interrupted, or they can count down, reload
the initial value, and start counting down
again (continuously). The counters for the
Z8611 can be used for measuring time
intervals and pulse widths, counting events,
or generating periodic interrupts.
The 8051 has two 16-bit counter/timers for
measuring time intervals and pulse widths,
generating pulse widths, counting events,
and generating periodic interrupts. The
counter/timers have several modes of
operation. They can be used as 8-bit
counters or timers with two 5-bit
programmable prescalers. They can also be
used as 16-bit counter/timers. Finally, they
can be set as 8-bit modulo-n counters with
the reload value held in the high byte of the
16-bit register. An interrupt is generated
when the counter/timer has completed
counting.
The MC6801 has one 16-bit counter which
can be used for pulse-width measurement
and generation. The counter/timer actually
consists of three 16-bit registers and an 8-bit
control/status register. The timer has an
input capture register, an output compare
register, and a free-running counter. All
three 16-bit registers can generate interrupts.

Serial Communications Interface. The
Z8611 has a programmable serial
communication interface. The chip contains
a UART for full-duplex, asynchronous, serial
receiver/transmitter operation. The bit rate is
controlled by counter/timer 0 and has a
maximum bit rate of 93.500 b/s. An interrupt
is generated when as assembled character is
transferred to the receive buffer. The
transmitted character generates a separate
interrupt. The receive register is doublebuffered. A hardware parity generator and

detector are integrated.
The 8501 handless serial I/O using one of
its parallel ports. The 8051 bit rate is
controlled by counter/timer 1 and has a
maximum bit rate of 187,500 b/s. The 8051
generates one interrupt for both transmission
and receipt. The receive register is doublebuffered.
The MC6801 contains a full-duplex,
asynchronous, serial communication
interface. The bit rate is controlled by a rate
register and by the MCU's clock or an
external clock. The maximum bit rate is
62,500 b/s. Both the transmit and the receive
registers are double-buffered. The MC6801
generates only one interrupt for both
transmit and receive operations. No
hardware parity generation or detection is
available, although it does have automatic
detection of framming errors and overrun
conditions.
The 8051 and the MC6801 generate only
one interrupt for both transmit and receive,
whereas the Z8611 has a separate interrupt
for each. The ability to generate separate
interrupts greatly enhances the use of serial
communications, since separate service
routines are often required for transmitting
and receiving.
Other differences between the Z8611,
MC6801, and the 8051 occur in the hardware
parity detector, the double-buffering of
registers, framing error detectors and
overrun conditions. The 8051 has a faster
data rate than either the Z8611 or the
MC6801. The MC6801 has the advantage of
a hardware framing error detector and
automatic detection of overrun conditions.
The MC6801 also has both its transmit and
receive registers double-buffered. The Z8611
has hardware parity detector, and for
detection of framing errors and overrun
conditions, a simple, low-overhead software
check is possible using only two instructions.

Instruction Architecture
The architecture of the Z8611 is designed
specifically for microcomputer applications.
This fact is manifest in the instruction
composition. The arduous task of
programming the MC6801 and the 8051
starkly contrasts with programming the
Z8611.
256

Addressing Modes. The Z8611 and the 8051
both have six addressing modes: Register,
Indirect Register, Indexed, Direct, Relative,
and Immediate. The MC6801 has five
addressing modes: Accumulator, Indexed,
Direct, Relative, and Immediate. A quick
comparison of these addressing modes

Instruction Architecture (Continued)
reveals the. versatility of the Z8611 and the
8051. The addressing modes of the MC6801
have several restrictions, as shown in Table
1. While the 8051 has all the addressing
modes of the Z8611, its use of them is
restricted. The Z8611 allows many more
combinations of addressing modes per
instruction, because any of its registers can
be used as an accumulator. For example, the
instructions to clear, complement, rotate,
and swap nibbles are all accumulator
oriented in the 8051 and operate on the
accumulator only. These same commands in
the Z8611 can use any register and access it
either directly, with register addressing, or
with indirect register addressing.

Indexed Addressing. All three chips differ
in their handling of indexing. The Z8611 can
use any register for indexing. The 8051 can
use only the accumulator as an Index
register in conjunction with the data pointer
or the Program Counter. The MC6801 has
one 16-bit Index register. The address
located in the second byte of an instruction
is added to the lower byte of the Index
register. The carry is added to the upper
byte for the complete address. The MC6801
requires the index value to be an immediate
value.
The MC6801 has only one 16-bit Index
register and an immediate 8-bit value from
the second byte of the instruction. Hence,
the Indexed mode of the MC6801 is much
more restrictive than that of the Z8611. The
8051 must use the accumulator as its only
Index register, loading the accumulator with
the register, address each time a reference is
made. Then, using indexing, the data is
moved into the accumulator, eradicating the
previous index. This forces a stream of data
through the accumulator and requires a
reload of the index before access can be
made again., The Z8611 is clearly superior to
both the MC6801 and the 8051 in the
flexibility of its indexed addressing mode.
Short and Long Addressing. Short
addressing helps to optimize memory space
and execution speed. In sample applications
of short register addreSSing, and eight
percent decrease in the number of bytes
used was recorded.

Al three chips have short addressing
modes, but the Z8611 has short addressing
for both external memory and register
memory. The 8051 has short addressing for
the lowest 32 registers only.
The Z8611 has two different modes for
register addressing. The full-byte address
can be used to provide the address, or a
4-bit address can be used with the Register
Pointer. To use the working registers, the
Register Pointer is set for a particular bank
of 16 registers, and then one of the 16
registers is addressed with four bits. Another
feature for addressing external memory is the
use of a 12-bit address in place of a full
16-bit address. To use the 12-bit address,
one port supplies the eight multiplexed
address/data lines and another port supplies
four bits for the address. The remaining four
bits of the second port can be used for 1/0.
This feature allows access to a maximum of
10K bytes of memory.
The 8051 uses short addresses by
organizing its lowest 32 registers into four
banks. The bank select is located in a 2-bit
field in the PSW, with three bits addressing
the register in the bank.
The MC6801 used extended addressing for
addressing external memory. With a special,
nonmultiplexed expansion mode, 256 bytes
of external memory can be accessed without
the need for an external address latch. The
MC6801 consumes one 8-bit port for the
address and another port for the data.

Stacks. The Z8611 and the MC6801 provide
for external stacks, which require a 16-bit
Stack Pointer. Internal stacks use an 8-bit
Stack Pointer. The 8051 uses only a limited
internal stack requiring an 8-bit Stack
Pointer. Using an external stack saves the
internal RAM register for general-purpose
use.
Summary. The stack structure of the Z8611
and the MC6801 is better than that of the
8051. In most applications, the 8051 is more
flexible and easier to program than the
MC6801. The Z8611 is easiers to use than
either the 8051 or the MC6801 because of its
register flexibility and its numerous
combinations of addressing modes. The 8051
features a unique 4/Ls multiply and divide

257

Instruction Architecture (Continued)
command. The MC6801 has a multiply, but it
takes lOlLS to perform it.
In summary, the 28611 has the most
flexible addressing -'modes, the most

advanced indexing capabilities, and superior
space-and time-saving abilities with respect
to short addressing.

Development Support
All vendors provide development support for
their products. This section discusses the
different support features, including
development chips, software, and modules.

Chips. SGS offers an entire family of
microcomputer chips for product
development and final product. The 28611 is
a single-chip microcomputer with 4K bytes of
mask-programmed ROM. For development,
two other chips are offered. The 286E 11 4K
EPROM and the Z86E21 8K EPROM versions.
Intel offers a similar line of development
chips with its 8051 family. The 8031 has no
internal ROM and the 8751 has 4K of
internal EPROM.
Motorola offers the MC6801, MC6803,
MC6803NR, and MC68701. These are all
similar except the MC68701 has 2K bytes of
EPROM and the MC6801 has 2K bytes of
ROM. The MC6803 has no internal ROM and
the MC6803NR has neither ROM nor RAM
on board.

Software. Development software includes
assemblers, and conversion programs. All
manufacturers offer some or all of these
features.
Since the MC6801 is compatible with the
6800, there is no need for a new assembler.
The 28611 and the 8051 both offer
assemblers for their products. The 28611
MAC28 assembler generates relocatable and
absolute object code. MAC28 also supports
high-level control and data statements, such
as IF... THEN... ELSE. Intel offers an
absolute macroassembler, ASM51, with their
product. They also offer a program for
converting 8048 code to 8051 code.
Modules. The 28611 development module has
two 64-pin development versions of the 40-pin,
ROM-masked 28611. Intel offers the EM-51
emulation board, which contains a modified
8051 and PROM or EPROM in place of
memory. Motorola has the MEX680 1EVM
evaluation board for program development.

Additional Features
Additional features include Power Down
mode, selftesting , and family-compatibility.

Power Down Mode. All three
microcomputers offer a Power Down mode.
The 28611 and the 8051 save all of their
registers with an auxiliary power supply. The
MC6801 uses an auxiliary power supply to
save only the first 64 bytes of its register file.
The 28611 uses one of the crystal input
pins for the external power supply to power
the registers in Power Down mode. Since the
XTAL2 input must be used, an external clock
generator is necessary and is input via

258

XTALl. The 8051 and the MC6801 both have
an input reserved for this function. The
MC6801 uses the Vee standby pin, and the
8051 uses the Vpd pin.

Family Compatibility. Another strenght of
the 28611 is its expansion bus, which is
completely with the Z8000 Family 2-BUS.
This means that all 2-BUS peripherals can be
used directly with the 28611.
The MC6801 is fully compatible with all
MC6800 family products. The 8051 is
software compatible with the older 8048
series and all others in that family.

Benchmark

The following benchmark tests were used in
this report to compare the 28611, 8051, and
MC680l:
• Generate CRC check for 16-bit word.
• Search for a character in a block of
memory.
• Execute a computed GOTO - jump to one
of eight locations depending on which of
the eight bits in set.

• Shift a

l6-word five places to the right.

• Move a 64-byte block of data from
external memory to the register file.
• Toggle a single bit on a port.
• Measure the subroutine overhead time.
These programs were selected because of
their importance in microcomputer
applications. Algorithms that reflect a unique
function or feature were excluded for the
sake of comparison. Although programs can
be optimized for a particular chip and for a
particular attribute (code density or speed)
these programs were not.
The figures cited in this text are taken
directly from the vendor's documentation.
Therefore, the cycles given below for the
MC6801 and the 8051 are in machine cycles
and the 28611 figures are given in clock
cycles. The 28611 clock cycles should be
divided by six to give the instruction time in
microseconds. The 8051 and MC6801
machine cycle is I/Ls, and the 28611 clock
cycle is . I 66/Ls at 12MHz.
Because of the lack of availability of the
MC6801 and the 8051, the benchmark
programs listed here have not yet been run.
When these products are readily available,
the programs will be run and later editions
of this document will>reflect any changes in
the findings.

Program Listing
CRC Generation
8051

Machine

Cycles Bytes
MOV INDEX, #8
LOOP: MOV A,DATA
XRL
A,HCHECK
RLC
A
MOV A,LCHECK
XRL
A,LPOLY
RLC
A
MOV LCHECK,A
MOV A,HCHECK
XRL
A,HPOLY
RCL
A
MOV HCHECK,A
CLR
C
MOV A,DATA
RCL
A
MOV DATA,A
DJNZ INDEX, LOOP
RET
N=3+ 17X8= 139 cycles
@12 MHz=1391's
Instructions = 18
Bytes=31

MC6801
LDAA 1'$08
LOOP: STAA COUNT
LDAA HCHECK
EORA DATA
ROLA
LDAD POLY
EORA HCHECK
EORB LCHECK
ROLB
ROLA
STAD LCHECK
DATA
ASL
DEC
COUNT
BNE
LOOP
RTS
N = 45X8 + 7 = 367 cycles
@4 MHz = 3671's
Instructions = 15
Bytes =28

Z86H
LD
INDEX, #8
R6,DATA
LOOP: LD
XOR
R6,HCHECK
RLC
R6
XOR
LCHECK,LPOLY
RLC
LCHECK
XOR
HCHECK,HPOLY
HCHECK
RLC
RCF
RLC
DATA
DJNZ INDEX,LOOP
RET
N = 20 + 66X7 + 64 = 546 cycles
@12 MHz=911's
Instructions = 12
Bytes =22

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2

2
2
2
1
2
2
1
2
2
2
1
2
1
2
1
2
3
1

Machine
Cycles Bytes
2
2
3
2
2
3
3
2
2
1
4
2
3
2
3
2
2
1
2
1
2
4
6
3
6
3
4
2
5
1

Clock
Cycles
6
6
6
6
6
6
6
6
6
6
12orlO
14

Bytes
2
2
2
2
2
2
2
2
1
2
2
1

259

Benchmarks (Continued)
Character Search Through Block 01 40 Bytes
8051
MOV INDEX, #41
MOV DPTR,#TABLE
LOOPI:DINZ INDEX,LOOP2
SIMP OUT
LOOP2:MOV A,INDEX
MOVC A,@A+DPTR
CINE A,CHARAC,LOOPI
OUT:
N = 3 + 39X7 + 4 = 280 cycles
@12 MHz = 2801's
Instructions::: 7
Bytes = 15

MC6801
LDAB #$40
LDAA #CHARAC
LDX
# TABLE
LOOP: CMPA $O,X
BEQ
OUT
INX
DECB
LOOP
BNE
OUT: N = 7 + 40X7 = 687 cycles
@4 MHz = 6871's
Instructions = 8
Bytes = 15

Z8611
LD
LOOP: LD
CP
lR
DINZ
OUT: -

Machine
Cycles Bytes
2
2
2
2
3
3
4
2
4
2
3
I
2
I
4
2

N = 6 + 38X40 = 1524 cycles
@12 MHz = 2541's
Instructions = 5
Bytes = II

8051
MOV INDEX#5
LOOP: CLR
C
MOV A,WORD+ I
RRC
A
MOV WORD+I,A
MOV A,WORK
RRC
A
MOV WORD,A
DJNZ INDEX,LOOP
N = I + 9X5 = 46 Cycles
@12 MHz = 461's
Instructions::: 9
Bytes = 15

MC6801
LDX
#5
LDAD WORK
LOOP: LSRD
DEX
BNE
LOOP
STAD WORD
N= IOX5+ II =61 Cycles
@4 MHz=611's
Instructions::: 6
Bytes = II
Z8611

Clock
Cycles
6

INDEX, #40
DATA, TABLE (INDEX)
!O
DATA, CHARAC
6
Z,OUT
12 or 10
INDEX, LOOP
12 or 10

-

260

Machine
Cycles Bytes
I
2
2
3
2
2
2
2
I
2
2
I
2
3

Shilt 16-Bit Word to Right 5-Bits

Bytes
2
3
2
2
2

INDEX, #5
LD
LOOP: CCF
RRC
WORD+I
RRC
WORD
DJNZ INDEX, LOOP
N = 6 + 4X30 + 28 = 154 Cycles
@12 MHz = 261's
Instructions = 5
Bytes = 9

Machine
Cycles Bytes
I
2
I
I
I
2
I
I
I
2
I
2
I
I
I
2
2
2

Machine
Cycles Bytes
6
3
4
2
3
I
3
I
4
2
4
2

Clock
Cycles
6
6
6
6
12 or !O

Bytes
2
I
2
2
2

Benchmarks (Continued)
Computed GOTO
8051
MOV
LOOP: MOV
RLC
lC
MOV
ADD
MOV
SlMP
OUT: MOV
MOV
lMP
TABLE: LCALL
-

INDEX,@40
A,DATA
A
OUT
A,INDEX
A,#3
INDEX,A
LOOP
DPTR,#TABLE
A, INDEX
@A+DPTR
ADDRI

Move 64·Byte Block
Machine
Cycles Bytes
1
2
1
2
1
1
2
2
1
1
1
2
1
1
2
2
2
3
1
1
2
1
3

8051
MOV INDEX, # COUNT
LOOP: MOV DPTR,#ADDRI
MOVX A,@DPTR
INC
#ADDRI
MOV @ADDR2,A
INC
ADDR2
INDEX, LOOP
D1NZ
N = 1 + 9X64 = 577 Cycles
@12 MHz=577~s
Instructions = 7
Bytes = 10

MC6801

-

LCALL ADDRN
N = 1 + 9X7 + 11 = 75 Cycles
@12 MHz=75~s
Instructions = 12
Bytes = 21

MC6801

2

Machine
Cycles Bytes

LDAB #2
TABLE
LDX
LOOP: RORA
BCS
OUT
ABX
LOOP
lMP
O,X
OUT: LDX
O,X
lMP
N = 8X12 + 14 = 110 Cycles
@4 MHz = 11 O~s
Instructions = 8
Bytes = 17

2
3
2
4
3
3
5
4

Z8611

Clock
Cycles

Z8611
CLR
LOOP: INC
RLC

2
3
1
2
1
2
3
3

LDAB #COUNT
LOOP: LDX
ADDRI
LDAA O,X
INX
STAA ADDRI
LDX
ADDR2
STAA O,X
INX
STX
ADDR2
DECB
BNE
LOOP
N = 64X36 + 2 = 2306 Cycles
@4 MHz = 2306~s
Instructions:::: 11
Bytes = 21

INDEX
INDEX
DATA
NC,LOOP
12
JR
ADDR,TABLE 1,(INDEX)
LD
ADDR+l,TABLE 2,(INDEX)
LD
@ADDR
lP
N = 6 + 24X7 + 54 = 228 Cycles
@12 MHz=38~s
Instructions:::: 7
Bytes = 15

6
6
6
or 10
10
10
12

Bytes
2
1
2
2
3
3
2

Machine
Cycles Bytes
1
2
2
1
1
1
2

2
3
1
1
1
1
1

Machine
Cycles Bytes
2
4
4
3
4
4
4
3
4
2
4

2
3
2
1
2
3
2
1
2
1
2

Clock
Cycles Bytes

LD
INDEX,#COUNT
6
@ADDR2,@ADDRI
LOOP: LDEI
18
DlNZ
INDEX, LOOP
12 or 10
N = 6 + 63X30 + 28 = 1924 Cycles
@12 MHz=321~s
Instructions = 3
Bytes = 6

2
2
2

261

Benchmarks (Continued)

Toggle a Port Bit
8051
XRL
PO,#YY
N =2 Cycles
@12 MHz = 21's

Subroutine Call/Return Overhead
Machine
Cycles Bytes
2
3

8051
LCALL SUBR

Machine
Cycles Bytes
2
3

-

-

Instructions::: 1

-

Bytes=3

SUBR:

-

MC6801
LDAA PORTO
EORA #YY
STAA PORTO
N =8 Cycles
@4 MHz = 81's

Machine
Cycles Bytes
2
3
2
2
3
2

Instructions = 3

RET
N=4 Cycles
@12 MHz = 41's
Instructions::: 2
Bytes =4

MC6801

Bytes = 6
lSR

Z8611
XOR
PORTO#YY
N = 10 Cycles
@12 MHz = 1.7!,s

Clock
Cycles
10

SUBR

2

1

Machine
Cycles Bytes
9
2

-

Bytes
2
SUBR:

-

Instructions::: 1

-

Byte =2

RTS
N = 14 Cycles
@4MHz=14!,s
Instructions::: 2
Bytes=3

Z8611
CALL

@SUBR

5

1

Clock
Cycles
20

Bytes
2

14

1

-

SUBR:

262

RET
N =34 Cycles
@12 MHz=5.7!,s
Instructions::: 2
Bytes=3

Benchmarks (Continued),
Results Table 2 summarizes the results of
this comparison. The relative performance
column lists the speeds of the MC6801 and
8051 divided by the Z8611 speeds (12 MHz).
The overall performance averages the
separate relative performances. The higher
the number, the faster the Z8611 as
compared to the MC6801 and the 805l.
The relative performance figures show that

Benchmark
Test

MC6801
(4 MHz)
cycles time

8051
(12 MHz)
cycles time

the Z8611 runs 50 percent faster than the
8051 and 250 percent faster than the
MC680l. Although speed is not necessarily
the most important criterion for selecting a
particular product, the Z8611 proves to be an
undeniably superior product when speed is
added to the advantages of programming
ease, code density, and flexibility.

Z8
(8 MHz)
cycles time

Z8
(12 MHz)
cycles time

Relative Performance
MC68DI
8051

CRC
Generation

367

367

139

139

546

137

546

91

4.03

1.53

Character
Search

687

687

280

280

1524

382

1524

254

2.70

1.10

Computed
GOTO

110

110

75

75

228

57

228

38

2.89

1.97

Shift Right
5 Bits

61

61

46

46

154

38

154

26

2.35

1.78

2306

2306

577

577

1924

481

1924

321

7.18

1.80

14

14

4

4

34

8

8

2

2

Move 64-Byte
block
Subroutine
Overhead
Toggle a
Port Bit

8.5

34

5.7

2.46

0.70

10
2.5
Overall
Performance

10

1.7

4.71

1.18

3.76

1.44

Note: All times are given in microseconds

Table 2. Benchmark Program Result

Bytes
MC68DI

Time (microseconds)

Instructions

8051

Z8611

MC68DI

8051

Z8611

MC68DI

8051

Z8611

15

18

12

367

139

91

CRC Generation

28

31

22

Character Search

15

15

11

8

7

5

687

280

254

Shift Right 5 Bits

11

15

9

6

9

5

61

46

26

Computed GOTO

17

21

15

8

12

7

110

75

38

Move Block

21

10

6

11

7

3

2306

577

321

Toggle Port Bit

6

3

2

3

1

1

8

2

1.7

Subroutine Call

3

4

3

2

2

2

14

4

5.7

Table 3. Byte/Instruction/Time Comparison

263

Benchmarks (Continued)
Summary The hardware of the three chips
. compared is very similar. The 28611,
however, has several advantages, the most
important of which is its interrupt structure.
It is more advanced than the interrupt
structures of both the 8051 and the MC6801.
Other advantages of the 28611 over either
the MC6801 or the 8051 include va facilities
with parity detection and hardware
handshake and a larger amount of internal
ROM (the MC6801 has only 2K bytes).
Substantial differences are apparent with
regard to software architecture. The
addressing modes of the Z8611 are more

264

flexible than those of either the MC6801 or
the 8051. The 28611 can use byte-saving
addressing with working registers, and it has
short external addresses for saving 1/0 lines.
It can also provide for an external stack. The
register architecture (as opposed to the
accumulator architecture) of the Z861 I saves
execution time and enhances programming
speed by reducing the byte count.
The Z8611 microcomputer stands out as the
most powerful chip of the three, and
concurrently, it is the easiest to program and
configure.

A Programmer's Guide to the Z8 Microcomputer

Introduction
The Z8 is the firts microcomputer to offer
both a highly integrated microcomputer on a
single chip and a fully expandable
microprocessor for I/O-and memory-intensive
applications. The Z8 Z8601, the first one, has
two timer/counters, a UART, 2K bytes
internal ROM, and a 144-byte internal
register file including 124 bytes of RAM, 32
bits of I/O, and 16 control and status
registers. In addition, the Z8 can address up
to 124K bytes of external program and data
memory, which can provide full, memorymapped 1/0 capability.
This application note describes the

important features of the Z8, with software
examples that illustrate its power and ease of
use. It is divided into sections by topic; the
reader need not read each section
sequentially, but may skip around to the
sections of current interest.
It is assumed that the reader is familiar
with the Z8 and its assembly language, as
described in the following documents:

• Z8 Technical/Manual (0. c.: DAZ8TM/2j
• Z8 Programming Manual
(0. C.: DAZ8PM/2j

Accessing Register Memory
The Z8 register space consists of four 1/0
ports, 16 control and status registers, and
124 general-purpose registers. The generalpurpose registers are RAM areas typically
used for accumulators, pointers, and stack
area. This section describes these registers
and how they are used. Bit manipulation and
stack operations affecting the register space
are discussed in Sections 4 and 5,
respectively.
Registers and Register Pairs. The Z8
supports 8-bit registers and 16-bit register
pairs. A register pair consists of an evennumbered register concatenated with the
next higher numbered register (OOH and
01H, 02H and 03H, ... 7EH and 7FH, FOH and
F1H, ... FEH and FFH). A register pair must
be addressed by reference to the evennumbered register. For example,
F1H and F2H is not a valid register pair;
FOH and FIH is a valid register pair,
addressed by reference to FOH.
Register pairs may be incremented (INCW)
and descremented (DECW) and are useful as
pointers for acceSSing program and external
data memory. Section 3 discusses the use of
register pairs for this purpose.

Any instruction which can reference or
modify an 8-bit register can do so to any of
the 144 registers in the Z8, regardless of the
inherent nature of that register. Thus, 1/0
ports, control, status, and general-purpose
registers may all be accessed and
manipulated without the need for specialpurpose instructions. Similarly, instructions
which reference or modify a 16-bit register
pair can do so to any of the valid 72 register
pairs. The only exceptions to this rule are:
• The DINZ (decrement and jump if nonzero) instruction may successfully operate
on the general-purpose RAM registers
(04H-7FH) only.
• Six control registers are write-only
registers and therefore, may be modified
only by such instructions as LOAD, POP,
and CLEAR. Instructions such as OR and
AND require that the current contents of
the operand be readable and therefore
will not function properly on the writeonly registers. These registers are the
follOWing: the timer/counter prescaler
registers PREO and PREl, the port mode
registers POlM, P2M, and P3M, the
interrupt priority register IPR.

265

Accessing Register Memory (Continued)
Register Pointer. Within the register
addressing modes provided by the 28, a
register may be specified by its full 8-bit
address (O-7FH, FOH-FFH) or by a short 4-bit
address. In the latter case, the register is
viewed as one of 16 working registers with-in
a working register group. Such a group must
be aligned on a 16-byte boundary and is
addressed by Register Pointer RP (FDH). As
an example, assume the Register Pointer
contains 70H, thus pointing to the working
register group from 70H to 7FH. The LD
instruction may be used to intialize register
76H to an immediate value in one of two
ways:
LD 76H,#1

or
LD R6,#1

The address calculation for the latter case
is illustrated in Figure 1. Notice that 4-bit
working-register addressing offers code
compactness and fast execution compared to
its 8- bit counterpart.
To modify the contents of the Register
POinter, the 28 provides the instruction
SRP

# value

Execution of this instruction will load the
upper four bits of the Register Pointer; the
lower four bits are always set to zero.
Although a load instruction such as
LD

RP, # value

!8-bit register address is
given by instruction (3 byte
instruction) !

could be used to perform the same function,
SRP provides execution speed (six vs. ten
cycles) and code space (two vs. three bytes)
advantages over the LD instruction. The
instruction

!4-bit working register
address is given by
instruction; 4-bit working
register group address is
given by Register Pointer
(2 byte instruction)!

is used to set the Register Pointer for the
above example.

INSTRUCTION
(LD R6,#1)

SRP

#70H

1000010001'

Figure I. Address Calculation Using the Register Pointer

Context Switching. A typical function
performed during an interrupt service
routine is context switching. Context
switching refers to the saving and subsequent
restoring of the program counter, status, and
registers of the interrupted task. During an
interrupt machine cycle, the 28 automatically
saves the Program Counter and status flags
on the stack. It is the responsibility of the
interrupt service routine to preserve the
register space. The recommended means to
this end is to allocate a speCific portion of
the register file for use by the service
routine. The service routine thus preserves
the register space of the interrupted task by
avoiding modification of registers not
266

allocated as its own. The most efficient
scheme with which to implement this
function in the 28 is to allocate a working
register group (or portion thereof) to the
interrupt service routine. In this way, the
preservation of the interrupted task's
registers is solely a matter of saving the
Register Pointer on entry to the service
routine, setting the Register Pointer to its
own working register group, and restoring
the Register Pointer prior to exiting the
service routine. For example, assume such a
register allocation scheme has been
implemented in which the interrupt service
routine for IRQO may access only working
register Group 4 (registers 40H-4FH). The

Accessing Register Memory (Continued)
service routine for IRQO should be headed
by the code sequence:
PUSH RP
SRP #40H

!preserve Register Pointer of
interrupted task!
!address working register
group 4!

Before exiting, the service routine should
execute the instruction
POP

RP

to restore the Register Pointer to its entry
value.
It should be noted that the technique
described above need not be restricted to
interrupt service routines. Such a technique
might prove efficient for use by a subroutine
requiring intermediate registers to produce
its outputs. In this way, the calling task can
assume that its environment is intact upon
return from the subroutine.

Addressing Mode. The Z8 provides three
addressing modes for accessing the register
space: Direct Register, Indirect Register, and
Indexed.
Direct Register Addressing. This addressing
mode is used when the target register
address is known at assembly time. Both long
(8-bit) register addressing and short (4-bit)
working register addressing are supported in
this mode. Most instructions supporting this
mode provide access to single 8-bit registers.
For example:
LD

FEH, #HI STACK
!load register FEH (SPH)
with the upper 8-bits of the
label STACK!
AND O,MASKJEG
!AND register 0 with register
named MASKJEG!
OR I,R5
lOR register I with working
register 5!
Increment word
word (DECW) are
instructions which
These instructions
the direct register

(INCW) and decrement
the only two Z8
access 16-bit operands.
are illustrated below for
addressing mode.

INCW RRO !increment working register
pair RO, RI:
RI +-RI + I
RO+- RO + carry!

DECW 7EH !decrement working register
pair 7EH, 7FH:
7FH+-7FH-I
7EH +-7EH - carry!
Note that the instruction
!NCW

RR5

will be flagged as an error by the assembler
(RR5 not even-numbered).

Indirect Register Addressing. In this
addressing mode, the operand is pointed to
by the register whose 8-bit register address
or 4-bit working register address is given by
the instruction. This mode is used when the
target register address is not known at
assembly time and must be calculated during
program execution. For example, assume
registers 60H - 7FH contain a buffer for
output to the serial line via repetitive calls to
procedure SERIAL_OUT.
SERIAL_OUT expects working register 0 to
hold the output character. The following
instructions illustrate the use of the indirect
addressing mode to accomplish this task:
LD

RI,#20H
!working register I is the
byte counter: output 20H
bytes!
LD
R2,#60H
!working register 2 is the
buffer pointer register!
ouLagain:
LD
RO,@R2
!load into working register 0
the byte pointed to by
working register 2!
INC
R2
!increment pointer!
CALL SERIAL-OUT
!output the byte!
DJNZ RI, ouLagain
!loop till done!
Indirect addressing may also be used for
accessing a 16-bit register pair via the !NCW
and DECW instructions. For example.
INCW @RO !increment the register pair
whose address is contained
in working register O!
DECW @7FH
!decrement the register pair
whose address is contained
in register 7FH!

267

Accessing Register Memory (Continued)
The contents of registers RO and 7FH
should be even numbers for proper access;
when referencing !il register pair, the least
significant address bit is forced to the
appropriate value by the Z8. However, the
register used to point to the register pair
need not be an even-numbered register.
Since the indirect addressing mode
permits calculation of a target address prior
to the desired register access, this mode may
be used to simulate other, more complex
addressing modes. For example, the
instruction
SUB 4,BASE(R5)
requires the indexed addressing mode which
is not directly supported by the Z8 SUBtract
instruction. This instruction can be simulated
as follows:
LD

R6,#BASE
!working register 6 has the
base address!
ADD R6,R5 !calculate the target address!
SUB 4,@R6 !now use indirect addressing
to perform the actual
subtract!
Any available register or working register
may be used in place of R6 in the above
example.
Indexed Addressing. The indexed
addressing mode is supported by the load
instruction (LD) for the transference of bytes
between a working register and another
register. The effective address of the latter
register is given by the instruction which is
offset by the contents of a designated
working (index) register. This addressing
mode provides efficient memory usage when
addressing consecutive bytes in a block of
register memory, such as a table or a buffer.
The working register used as the index in the
effective address calculation can serve the
additional role of counter for control of a
loop's duration.
For example, assume an ASCII character
buffer exists in register memory starting at
address BUF for LENGTH bytes. In order to
determine the logical length of the character

268

string, the buffer should be scanned
backward until the first nonoccurrence of a
blank character. The follOWing code
sequence may be used to accomplish this
task:
LD

loop:
LD

CP
JR

RO, # LENGTH
!length of buffer!
!starting at buffer end, look
for 1st non-blank!
Rl,BUF-l(RO)
Rl, # ' ,
ne,found
!found non-blank!

DJNZ RO,loop
all~lanks:

!look at next!
!length = O!

found:
5 instructions
12 bytes
1.5 JlS overhead
10.5 JlS (average) per character tested
At labels "all_blanks" and "found," RO
contains the length of the character string.
These labels may refer to the same location,
but they are shown separately for an
application where special processing is
required for a string of zero length. To
perform this task without indexed addressing
would require a code sequence such as:
LD
LD

Rl,#BUF+LENGTH-l
RO,#LENGTH
!starting at buffer end, look
for 1st non-blank!

loopl:

CP
JR

@Rl,#
ne,foundl
!found non-blank!
DEC Rl
!dec pointer!
DJNZ RO,loopl
!are we done?!
all~lanksl:
!length = O!
foundl:
6 instructions
13 bytes
3 JlS overhead
9.5 JlS (average) per character tested

Accessing Register Memory (Continued)
The latter method requires one more byte
of program memory than the former, but is
faster by four execution cycles (1 p,s) per
character tested.
As an alternate example, assume a buffer
exists as described above, but it is desired to
scan this buffer forward for the first
occurrence of an ASCII carriage return. The
following illustrates the code to do this:
LD

RO, # -LENGTH
!starting at buffer start, look
for 1st carriage return
(=ODH)!

next:
LD
CP

rl,BUF + LENGTH(RO)
Rl, #ODH
JR eq,cr !found it!
INC RO
!update counterlindex!
JR nz, next
!tryagain!
cr:
ADD RO, # LENGTH
IRO has length to CR!

7 instructions
16 bytes
1. 5 p,s over head
12 p,s (average) per character tested

Accessing Program and External Data
Memory
In a single instruction, the Z8 can transfer
a byte between register memory and either
program or external data memory. Load
Constant (LDC) and Load Constant and
Increment (LDCI) reference program
memory; Load External (LDE) and Load
External and Increment (LDEI) reference
external data memory. These instructions
require that a working register pair contain
the address of the byte in either program or
external data memory to be accessed by the
instruction (indirect working register pair
addressing mode). The register byte operand
is specified by using the direct working
register addressing mode in LDC and LDE
or the indirect working register addressing
mode in LDCI and LDEI. In addition to
performing the designated byte transfer,
LDCI and LDEI automatically increment both
the indirect registers specified by the
instruction. These instructions are therefore
efficient for performing block moves between
register and either program or external data
memory. Since the indirect addressing mode
is used to specify the operand address within
program or external data memory, more
complex addressing modes may be simulated
as discussed earlier in Section 2.4.2. For
example, the instruction
LDC R3,BASE(R2)
requires the indexed addressing mode,
where BASE is the base address of a table in
program memory and R2 contains the offset
from table start to the desired table entry.

The following code sequence simulates this
instruction with the use of two additional
registers (RO and Rl in this example).
LD
LD

RO,#.H BASE
Rl, #.L BASE
!RRO has table start address!
ADD Rl,R2
ADC RO,#O
!RRO has table entry address!
LDC R3,@RRO
IR3 has the table entry!

Configuring the Z8 for I/O Applications vs.
Memory Intensive Applications. The Z8
offers a high degree of flexibility in memory
and I/O intensive applications. Thirty-two
port bits are prOVided of which 16, 12, eight,
or zero may be configured as address bits to
external memory. This allows for addressing
of 62K, 4K or 256 bytes of external memory,
which can be expanded to 124K, 8K, or 512
bytes if the Data Memory Select output (DM)
is used to distinguish between program and
data memory accesses. The following
instructions illustrate the code sequence
required to configure the Z8 with 12 external
addressing lines and to enable the Data
Memory Select output.
LD
LD

P01M, # (2)000l001OH
!bit 3-4: enable ADo-AD7;
bit 0-1: enable As-All!
P3M, # (2)00001000H
!bit 3 - 4: enable DM!
269

Accessing Program and External Data
Memory (Continued)
The two bytes following the mode selection
of ports 0 and I-should not reference
external memory due to pipe lining of
instructions within the Z8. Note that the load
instruction to P3M satisfies this requirement
(providing that it resides within the internal
2K bytes of memory).

tokenizing an ASCII input buffer. The
program assumes there is a list of delimiters
(space, comma, tab, etc.) in program
memory at address DELIM for COUNT bytes
(accessed via LDC) and that an ASCII input
buffer exists in external data memory
(accessed via LDE). The program scans the
input buffer from the current location and
returns the start address of the next token
(i.e. the address of the first nondelimiter
found) and the length of that token (number
of characters from token start to next
delimiter).

LDC and LDE. To illustrate the use of the
Load Constant (LDC) and Load External
(LDE) instructions, assume there exists a
hardware configuration with external memory
and Data Memory Select enabled. The
following module illustrates a program for
MACZ8
LOC

P 0000
P 0003

2.0
OBl CODE STMT SOURCE STATEMENT

20
2E

3B
OA

2C
aD

P 0006

BO

E2

P
P
P
P
P

82
AO
D6
FD
8D

30
EO
002E'
0015'
0018'

POOlS

8D

0008'

P 0018
paOlA

48
58

EO
EI

P OOIC
P OOID

2E
82

30

270

SCAN
MODULE
CONSTANT
COUNT
6
GLOBAL
$SECTION PROGRAM
DE LIM
ARRAY
[COUNT BYTE]

7
8
9 scan

P 0006

0008
OOOA
OOOC
OOOF
0012

I
2
3
4
5
6

[' , , ';' , ',' , '.' , OAH, ODH]
PROCEDURE

10

! ***********************************************************************

II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

Purpose =

To find the next token within an
ASCII buffer.

Input =

RRO = address of current location
within input buffer in external
memory.

address of start of next token
address of new token's ending
delimiter
R2
length of token
R3
ending delimiter
R6, R7, R8, R9 destroyed

Output=

RR4
RRO

***********************************************************************!

ENTRY
elr
R2
DO
LDE
R3,@RRO
incw
RRO
call
check
IF C THEN

EXIT

!init. length counter!
!get byte from input buffer!
!increment pointer!

!look for non-delimiter!
!found token start!

FI
aD
Id
Id
DO
inc

LDE

R4,RO
R5,RI

!RR4 = token starting addr!

R2
R3,@RRO

!inc. length counter!
!get next input byte!

Accessing Program and External Data Memory (Continued)
P OOIF
P 0022
P 0025

D6
7D
8D

P 0028
P 002A

AO
8D

P 002D
P 002E

AF

002E'
0028'
002D'
EO
OOlC'

P 002E

P 002E
P 0030

6C
7C

00'
00'

P 0032

8C

06

P
P
P
P
P
P

0034
0036
0038
003A
003C
003E

P 003F
P 0040

C2 96
AO E6
A2 93
6B 03
8A F6
DF

AF

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86

call
check
IF NC THEN

EXIT
FI
incw
OD

!look for delimiter!
!found token end!

RRO

!point to next byte!

ret
scan

END
check

PROCEDURE

! ***********************************************************************

Purpose =

compare current charader with
delimiter table until table
end or match found

input=

DELIM = start address of table
COUNT = length of that table
R3 = byte to be scrutinized

output=

Carry flag = I = > input byte
is not a delimiter (no match found)
Carry flag = 0 = > input byte
is a delimiter (match found)
R6, R7, R8, R9 destroyed

**** * * * ** * * * *** * * * * * * *** * * * ** * **** ** * * * * * * ******* * * * * * *** * * ** ** * * * * * * * *

!

ENTRY
Id
Id

R6, #HI DELIM
R7,#LO DELIM

ld

R8,#COUNT

LDC

R9,@RR6
RR6
R9,R3
eq,bye
R8,here

!RR6 points to
delimiter list!
!R8 = length of list!

here:
incw

cp
jr
djnz
scf

!get table entry!
!point to next entry!

!R3 = delimiter?!
!yes, carry = OJ
!next entry!
!table done. R3
not a delimiter!

bye:
END
END

ret
check
SCAN

o ERRORS
ASSEMBLY COMPLETE
27 instructions

58 bytes
Execution time is a function of the number of leading delimiters

before token start (x) and the number of characters in the

token (y): 123 iJ.S overhead + 59x iJ.S 2102y iJ.S
(average) per token

271

Accessing Program and External Data
Memory (Continued)

LOCI. A common function performed in Z8
applications is the initialization of the
register space. The most obvious approach to
this function is the coding of a sequence of
"load register with immediate value"
instructions (each occupying three program
bytes for a register or two program bytes for
a working register). This approach is also the
most efficient technique for initializing less
than eight consecutive registers or 14
consecutive working registers. For a larger
register block, the LDCI instruction provides
an economical means of initializing
consecutive registers from an initialization
table in program memory. The following
code excerpt illustrates this technique of
initializing control registers F2H through
FFH from a 14-byte array (INIT_tab) in
program memory:
SRP
LD
LD
LD
LD

#OOH
!RP not FOH!
R6, #.H INIT_tab
R7, #.L INIT_tab
R8,#F2H
! 1st reg to be initialized!
R9, #14
!length of register block!

loop:
LDCI @R8,@RR6
!load a register from the init
table!
DJNZ R9,loop
!continue till done!

7 instructions
14 bytes
7.5 itS overhead
7.5 itS per register initialized

LDEI. The LDEI instruction is useful for
moving blocks of data between external and
register memory since auto-increment is
performed on both indirect registers
designated by the instruction. The following
code excerpt illustrates a register buffer
being saved at address 40H through 60H into
external memory at address SAVE:
LD
LD
LD
LD

RlO,#.H SAVE
!external memory!
Rll, #.L SAVE
!address!
R8,#40H
!starting register!
R9,#2lH
!number of registers to save
in external data memory!

loop:
LDEI @RRlO,@R8
!init a register!
DJNZ R9,loop
!until done!
6 instructions
12 bytes
6 itS overhead
7.5 itS per register saved

Bit Manipulations
Support of the test and modification of an
individual bit or group of bits is required by
most software applications suited to the Z8
microcomputer. Initializing and modifying
the Z8 control registers, polling interrupt
requests, manipulating port bits for control of
or communication with attached deVices, and
manipulation of software flags for internal
control purposes are all examples of the
heavy use of bit manipulation functions.
These examples illustrate the need for such
functions in all areas of the Z8 register
space. These functions are supported in the
Z8 primarily by six instructions:
• Test under Mask (TM)
• Test Complement under Mask (TCM)

272

• AND
• OR
• XOR
• Complement (COM)
These instructions may access any Z8
register, regardless of its inherent type
(control, I/O, or general purpose), with the
exception of the six write-only control
registers (PREO, PREl, POIM, P2M, P3M,
IPR) mentioned earlier in Section 2.1. Table
1 summarizes the function performed on the
destination byte by each of the above
instructions. All of these instructions, with
the exception of COM, require a mask

Bit Manipulations (Continued)
operand. The "selected" bits referenced in
Table 1 are those bits in the destination
operand fot which the corresponding mask
bit is,? logic 1.
Opcode
TM
TCM

AND
OR
XOR
COM

Use
To
To
To
To
To
To

test selected bits for logic 0
test selected bits for logic 1
rest all but selected bits to logic 0
set selected bits to logic 1
complement selected bits
complement all bits

Table I. Bit Manipulation Instruction Usage

The instructions AND, OR, XOR, and
COM have functions common to today's
micro-processors and therefore are not
described in depth here. However, examples
of the use of these instructions are laced
throughout the remainder of this document,
thus giving an integrated view of their uses
in common functions. Since they are unique
to the Z8, the functions of Test under Mask
and Test Complement under Mask, are
discussed in more detail next.

Test under Mask (TM). The Test under Mask
instruction is used to test selected bits for
logic O. The logical operation performed is
destination AND source
Neither source nor destination operand is
modified; the FLAGS control register is the
only register affected by this instruction. The
zero flag (Z) is set if all selected bits are
logic 0; it is reset otherwise. Thus, if the
selected destination bits are either all logic
or a combination of Is and Os, the zero flag
would be cleared by this instruction. The
sign flag (S) is either set or reset to reflect
the result of the AND operation; the overflow
flag (V) is always reset. All other flags are
unaffected. Table 2 illustrates the flag
settings which result from the TM instruction
on a variety of source and destination

operand combinations. Note that a given TM
instruction will never result in both the Z and
S flags being set.

Test Complement under Mask. The Test
Complement under Mask instruction in used
to test selected bits for logic 1. The logical
operation performed is
(NOT destination) AND source.
As in Test under Mask, the FLAGS control
register is the only register affected by this
operation. The zero flag (Z) is set if all
selected destination bits are I; it is reset
otherwise. The sign flag (S) is set or reset to
reflect the result of the AND operation; the
overflow flag (V) is always reset. Table 3
illustrates the flag settings which result from
the TCM instruction on a variety of source
and destination operand combinations. As
with the TM instruction, a given TCM
instruction will never result in both the Z and
S flags being set.
Destination
(binary)
10001100
01111100
10001100
11111100
00011000
01000000

Source
(binary)
01110000
01110000
11110000
11110000
10100001
10100001

Flags

Z
0
0
0

S
0
0
1
0
0

V
0
0
0
0
0
0

Table 2. Effects of the TM Instruction
Destination
(binary)
10001100
01111100
10001100
11111100
00011000
01000000

Flags

Source
(binary)
01110000
01110000
11110000
11110000
10100001
10100001

Z

0
1
0
1
0
0

S
0
0
0
0

V
0
0
0
0
0
0

Table 3. Effects of the TeM Instruction

273

Stack Operations
The 28 stack resides within an area of data
memory (internal or external). The current
address in the stack is contained in the stack
pointer, which decrements as bytes are
pushed onto the stack, and increments as
bytes are popped from it. The stack pointer
occupies two control register bytes (FEH and
FFH) in the 28 register space and may be
manipulated like any other register. The
stack is useful for subroutine calls, interrupt
service routines, and parameter passing and
saving. Figure 2 illustrates the downward
growth of a stack as bytes are pushed onto it.
x sp_

,-,

CALL instruction. This address may be a
direct address or an indirect register pair
reference.
For example,
LABEL I: CALL 4F98H
!direct addressing: PC is
loaded with the hex value
4F98;
address LABEL I + 3 is
pushed onto the stack!
LABEL 2: CALL @RR4
!indirect addressing: PC is
loaded with the contents of
working register pair R4,
R5; address LABEL 2 + 2 is
pushed onto the stack!

,-2
,-3

,-4
INITIAL

STATE

FOLLOWING
PUSH R1

FOLLOWING
CALL

Figure 2. Growth of a Slack

Internal vs. External Stack. The location of
the stack in data memory may be selected to
be either internal register memory or
external data memory. Bit 2 of control
register POIM (F8H) controls this selection.
Register pair SPH (FEH), SPL (FFH) serves
as the stack pointer for an external stack.
Register SPL is the stack pointer for an
internal stack. In the latter configuration,
SPH is available for use as a data register.
The following illustrates a code sequence
that initializes external stack operations:
LD POIM, # (2)OOOOOOOOH
!bit 2: select external stack!
LD SPH, #.H STACK
LD SPL, #.L STACK
CALL. A subroutine call causes the current
Program Counter (the address of the byte
following the CALL instruction) to be pushed
onto the stack. The Program Counter is
loaded with the address specified by the

274

LABEL 3: CALL @7EH
!indirect addressing: PC is
loaded with the contents of
register pair 7EH, 7FH;
address LABEL 3 + 2 is
pushed onto the stack!

RET. The return (RET) instruction causes the
top two bytes to be popped from the stack
and loaded into the Program Counter.
Typically, this is the last instruction of a
subroutine and thus restores the PC to the
address follOWing the CALL to that
subroutine.

Interrupt Machine Cycle. During an
interrupt machine cycle, the PC followed by
the status flags is pushed onto the stack. (A
more detailed discussion of interrupt
processing is prOVided in Section 6).

IRET. The interrupt return (IRET) instruction
causes the top byte to be popped from the
stack and loaded into the status flag register.
FLAGS (FCH); the next two bytes are then
popped and loaded into the Program
Counter. In this way, status is restored and
program execution continues where it had
left off when the interrupt was recognized.

Stack Operations (Continued)
PUSH and POP. The PUSH and POP
instructions allow the transfer of bytes
between the stack and register memory, thus
providing program access to the stack for
saving and restoring needed values and
passing parameters to subroutines.
Execution of a PUSH instruction causes the
stack pointer to be decremented by 1; the
operand byte is then loaded into the location
pointed to by the decremented stack pointer.
Execution of a POP instruction causes the
byte addressed by the stack pointer to be
loaded into the operand byte; the stack
pointer is then incremented by 1. In both
cases, the operand byte is designated by
either a direct register address or an indirect

register reference. For example:
PUSH Rl

!direct address: push
working register 1 onto the
stack!

POP

!direct address: pop the top
stack byte into register 5!

5

PUSH @R4

!indirect address: pop the
top stack byte into the byte
pointed to by working
register 4!

PUSH @ 17

!indirect address: push onto
the stack the byte pointed to
by register 17!

Interrupts
The Z8 recognizes six different interrupts
from four internal and four external sources,
including internal timer/counters, serial I/O,
and four Port 3 lines. Interrupts may be
individually or globally enabled/disabled via
Interrupt Mask Register IMR (FBH) and may
be prioritized for simultaneous interrupt
resolution via Interrupt Priority Register IPR
(F9H). When enabled, interrupt request
processing automatically vectors to the
designated service routine. When disabled,
and interrupt request may be polled to
determine when processing is needed.

Interrupt Initialization. Before the Z8 can
recognize interrupts following RESET, some
initialization tasks must be performed. The
initialization routine should configure the Z8
interrupt requests to be enabled/disabled, as
required by the target application and
assigned a priority (via IPR) for simultaneous
enabled-interrupt resolution. An interrupt
request is enabled if the corresponding bit in
the IMR is set (= 1) and interrupts are
globally enabled (bit 7 of IMR = 1). An
interrupt request is disabled if the
corresponding bit in the IMR is reset (= 0) or
interrupts are globally disabled (bit 7 of
IMR=O).
A RESET of the Z8 causes the contents of
the Interrupt Request Register IRQ (F AH) to
be held to zero until the execution of an EI

instruction. Interrupts that occur while the Z8
is in this initial state will not be recognized,
since the corresponding IRQ bit cannot be
set. The EI instruction is specially decoded
by the Z8 to enable the IRQ; simply setting
bit 7 of IMR is therefore not sufficient to
enable interrupt processing following RESET.
However, subsequent to this initial EI
instruction, interrupts may be globally
enabled either by the instruction

EI

!enable interrupts!

or by a register manipulation instruction
such as
OR

IMR, #80H

To globally disable interrupts, execute the
instruction

DI

!disable interrupts!

This will cause bit 7 of IMR to be reset.
Interrupts must be globally disabled prior
to any modification of the IMR. IPR or
enabled bits of the IRQ (those corresponding
to enabled interrupt requests), unless it can
be guaranteed that an enabled interrupt will
not occur during the processing of such
instructions. Since interrupts represent the
occurrence of events asynchronous to
program execution, it is highly unlikely that
such a guarantee can be made reliably.

275

Interrupts (Continued)
Vectored Interrupt Processing: Enabled
interrupt requests are processed in an
automatic vectored mode in which the
interrupt service routine address is retrieved
from within the first 12 bytes of program
memory. When an enabled interrupt request
is recognized by the Z8, the Program
Counter is pushed onto the stack (low order
8 bits first, then high-order 8 bits) followed
by the FLAGS register (# FCH). The
corresponding interrupt request bit is reset
in IRQ, interrupts are globally disabled (bit
7 of IMR is reset), and an indirect jump is
taken on the word in location 2 x, 2 x + I
(x = interrupt request number, OsxsS). For
example, if the bytes at addresses 0004H and
OOOSH contain OSH and 78H respectively, the
interrupt machine cycle for IRQ2 will cause
program execution to continue at address
0578H.
When interrupts are sampled, more than
one interrupt may be pending. The Interrupt
Priority Register OPR) controls the selection
of the pending interrupt with highest
priority. While this interrupt is being
serviced, a higher-priority interrupt may

occur. Such interrupts may be allowed
service within the current interrupt service
routine (nested) or may be held until the
current service routine is complete (nonnested).
To allow nested interrupt processing,
interrupts must be selectively enabled upon
entry to an interrupt service routine.
Typically, only higher-priority interrupts
would be allowed to nest within the current
interrupt service. To do this, an interrupt
routine must "know" which interrupts have a
higher priority than the current interrupt
request. Selection of such nesting priorities
is usually a reflection of the priorities
established in the Interrupt Priority Register
OPR). Given this data, the first instructions
executed in the service routine should be to
save the current Interrupt Mask Register,
mask off all interrupts of lower and equal
priority, and globally enable interrupts (EI).
For example, assume that service of interrupt
requests 4 and S are nested within the
service of interrupt request 3. The following
illustrates the code required to enable IRQ4
and IRQ5:

CONSTANT
INT~ASK_3
(2) OOlIOOOOH
GLOBAL
IRQ3----"ervice
PROCEDURE
ENTRY
!service routine for IRQ3!
PUSH IMR
!save Interrupt Mask Register!
!interrupts were globally disabled during the interrupt
machine cycle - no DI is needed prior to modification of IMR!
AND IMR,#INT~ASK_3
!disable all but IRQ4 & 5!
EI
I. .. !
lservice interrupt!
!interrupts are globally enabled now - must disable them prior
to modification of IMR!
DI
POPIMR
!restore entry IMR!
IRET
END IRQ3_service

276

Interrupts (Continued)
Note that IR04 and IR05 are enabled by the
above sequence only if their respective IMR
bits = I on entry to IR03_service.
The service routine for an interrupt whose
processing is to be completed without
interruption should not allow interrupts to be
nested within it. Therefore, it need not
modify the IMR, since interrupts are disabled
automatically during the interrupt machine
cycle.
The service routine for an enabled
interrupt is typically concluded with an IRET
instruction, which restores the FLAGS
register and Program Counter from the top
of the stack and globally enables interrupts.
To return from an interrupt service routine
without re-enabling interrupts, the following
code sequence could be used:
POP FLAGS
RET

IFLAGS<-@SPI
IPC<-@SPI

Polled Interrupt Processing. Disabled
interrupt requests may be processed in a
polled mode, in which the corresponding
bits of the Interrupt Request Register (lRO)
are examined by the software. When an
interrupt request bit is found to be a logic I,
the interrupt should be processed by the
appropriate service routine. During such
processing, the interrupt request bit in the
IRO must be cleared by the software in order
for subsequent interrupts on that line to be
distinguished from the current one. If more
than one interrupt request is to be processed
in a plied mode, polling should occur in the
order of established priorities. For example,
assume that IROO, IROI, and IR04 are to be
polled and that established priorities are,
from high to low, IR04, IROO, IROI. An
instruction sequence like the following
should be used to poll and service the
interrupts:

This accomplishes all the functions of IRET,
except that IMR is not affected.

!. .. !
!poll interrupt inputs here!
TCM
JR
CALL
TESTO:
TCM
JR
CALL
TEST!:
TCM
JR
CALL
DONE:
!... !

IRQ4_service
!... !
AND
!. .. !
RET
END IRQ4_service
IRQO-"ervice
!. .. !
AND
!. .. !
RET
END IRQO_service

IRQI-"ervice
!. .. !
AND
1. .. 1
RET
END IRQ I_service
! ... !

IRQ, # (2)00010000H
NZ, TESTO
IRQ4_service
IRQ, # (2)0000000IH
NZ, TEST!
IRQO_service
IRQ, # (2)00000010H
NZ, DONE
IRQ!_service
PROCEDURE

!IRQ4 need service?!
!no!

!yes!
!RQO need service?!
!no!

!yes!
!IRQI need service?!
lno!
!yes!
ENTRY

IRQ, #(2)11101llIH

PROCEDURE

!clear IRQ4!

ENTRY

IRQ, #(2)11111l10H

PROCEDURE
IRQ, #(2)llllllOlH

!clear IR QO!

ENTRY
!clear IRQI!

277

Timer/Counter Functions
The Z8 provides two 8-bit timer/counters, To
and Tl, which are adaptable to a variety of
application needs aad thus allow the software
(and external hardware) to be relieved fo the
bulk of such tasks. Included in the set of
·such uses are:
• Interval delay timer
• Maintenance of a timer-of-day clock
• Watch-dog timer
• External event counting
• Variable pulse train output
• Duration measurement of external event
• Automatical delay following external event
detection
Each timer/counter is driven by tis own
6-bit prescaler, which is in turn driven by
the internal Z8 clock divided by four. For Tl,
the internal clock may be gated or triggered
by an external event or may be replaced by
an external clock input. Each timer/counter
may operate in either single-pass or
continuous mode where, at end-of-count,
either counting stops of the counter reloads
and continues counting. The counter and
prescaler registers may be altered
individually while the timer/counter is
running; the software controls whether the
new values are loaded immediately or when
end-of-count (EOC) is reached.
Although the timer/counter prescaler
registers (PREO and PREl) are write-only,
there is a technique by which the
timer/counters may simulate a readable
prescaler. This capability is a requirement
for high resolution measurement of an event's
duration. The basic approach requires that
one timer/counter be initialized with the
desired counter and prescaler values. The
second timer/counter is initialized with a
counter equal to the prescaler of the first
timer/counter and a prescaler of I. The
second timer/counter must be programmed
for continuous mode. With both timer/
counters driven by the internal clock and
started and stopped simultaneously, they will
run synchronous to one another; thus, the
value read from the second counter will
always be equivalent to the prescaler of the
first.

218

Time/Count Interval Calculation To
determine the time interval (i) until EOC, the
equation
i=txpxv
characterizes the relation between the
prescaler (p), counter (v), and clock input
period (t); t is given by
l/(XTALl8)
where XTAL is the Z8 input clock frequency;
p is in the range I - 64; v is in the range
I - 256. When programming the prescaler
and counter registers, the maximum load
value is truncated to six and eight bits,
respectively, and is therefore programmed as
zero. For an input dock frequency of 8
MHz, the prescaler and counter register
values may be programmed to time and
interval in the range
1 /-Is xl x I :S i :S l/-lsx64x256
1 /-Is :S i :S 16.384 ms
To determine the count (c) until EOC for
Tl with external clock input, the equation
c=pxv
characterizes the relation between the
T)prescaler (p) and the T) counter (v). The
divide-by-8 on the input frequency is
bypassed in this mode. The count range is
lxl:s c:S 64x256
1 :S c :S 16,384

TOUT Modes. Port 3, bit 6 (P36) may be
configured as an output (Tour) which is
dynamically controlled by one of the
following:
• To
• T)

• Internal clock
When driven by To or T), Tour is reset to a
logic I when the corresponding load bit is
set in timer control register TMR (FIH) and
toggles on EOC from the corresponding
counter. When Tour is driven by the
internal clock, that clock is directly output
on P36.
While programmed as Tour, P36 is
disabled from being modified by a write to
port register 03H; however, its current
output may be examined by the Z8 software
by a read to port register 03H.

Timer/Counter Functions (Continued)
TIN Modes. Port 3, bit I (P31) may be
configured as an input (TIN) which is used in
conjunction with TI in one of four modes:
• External clock input
• Gate input for internal clock
• Nonretriggerable input for internal clock
• Retriggerable input for internal clock
For the latter two modes, it should be noted
that the existence of a synchronizing circuit
within the Z8 causes a delay of two to three
internal clock periods following an external
trigger before clocking of the counter
actually begins.
Each High-to-Low transition on TIN will
generate interrupt request IRQ2, regardless
of the selected TIN mode or the enabled/
disabled state of Tl. IRQ2 must therefore be
masked or enabled according to the needs
of the application.
The "external clock input" TIN mode
supports the counting of external events,
where an event is seen as a High-to-Low
transition on TIN. Interrupt request IRQS is
generated on the nth occurrence (single-pass
mode) or on every nth occurrence
(continuous mode) of that event.
The "gate input for internal clock" TIN
mode provides for duration measurement of
an external event. In this mode, the T)
prescaler is driven by the Z8 internal clock,
gated by a High level on TIN. In other
words, T) will count while TIN is High and
stop counting while TIN is Low. Interrupt
request IRQ2 is generated on the High-toLow transition on TIN. Interrupt request IRQS
is generated on T) EOC. This mode may be
used when the width of a High-going pulse
needs to be measured. In this mode, IRQ2 is
typically the interrupt request of most
importance, since it signals the end of the
pulse being measured. If IRQS is generated
prior to IRQ2 in this mode, the pulse width
on TIN is too large for TI to measure in a
single pass.
The "nonretriggerable input" TIN mode
provides for automatic delay timing following
and external event. In this mode, T) is
loaded and clocked by the Z8 internal clock
following the first High-to-Low transition on
TIN after T) is enabled. TIN transitions that
occur after this point do not affect T). In
single-pass mode, the enable bit is reset on

EOC; further TIN transitions will not cause T)
to load and begin counting until the software
sets the enable bit again. In continuous
mode, EOC does not modify the enable bit,
but the counter is reloaded and counting
continues immediately; IRQS is generated
every EOC until software resets the enable
bit. This TIN mode may be used, for
example, to time the line feed delay
following end of line detection on a printer
or to delay data sampling for some length of
time following a sample strobe.
The "retriggerable input" TIN mode will
load and clock T) with the Z8 internal clock
on every occurrence of a High-to-Low
transition on TIN. T) will time-out and
generate interrupt request IRQS when the
programmed time interval (determined by T)
prescaler and load register values) has
elapsed since the last High-to-Low transition
on TIN. In single-pass mode, the enable bit is
reset on EOC; further TIN transitions will not
cause T) to load and begin counting until
the software sets the enable bit again. In
continuous mode, EOC does not modify the
enable bit, but the counter is reloaded and
counting continues immediately; IRQ5 is
generated at every EOC until the software
resets the enable bit. This TIN mode may
provide such functions as watch-dog timer
(e.g., interrupt if conveyor belt stopped or
clock pulse missed), or keyboard time-out
(e.g., interrupt if no input in x ms).

Examples. Several possible uses of the
timer/counters are given in the following four
examples.
Time of Day Clock. The following module
illustrates the use of T) for maintenance of a
time of day clock, which is kept in binary
format in terms of hours, minutes, seconds,
and hundredths of a second. It is desired
that the clock be updated once every
hundredth of a second; therefore, T) is
programmed in continuous mode to interrupt
100 times a second. Although T) is used for
this example, To is equally suited for the
task.
The procedure for initializing the timer
(TOD_INIT), the interrupt service routine
(TOD) which updates the clock, and the
interrupt vector for T) end-of-count (IRQ_S)
are illustrated below. XTAL = 7.3728 MHz is
assumed.
279

Timer/Counter Functions (Continued)
MACZ8
LOC

P 0000

2.0
OBI CODE STMT SOURCE STATEMENT

OOOF'

P OOOC
P 0000

E6

F3

93

P 0003

E6

F2

00

P
P
P
P
P
P

46
8F
46
9F
AF

FI

DC

FB

20

0006
0009
OOOA
OOOD
OOOE
OOOF

P OOOF
P OOOF

70

FD

P
P
P
P
P
P
P
P
P
P
P
P
P
P

31
FE
A6
EB
BO
EE
A6
EB
BO
DE
A6

10

0011
0013
0014
0017
0019
OOIB
001C
OOIF
0021
0023
0024
0027
0029
002B

P 002C
P 002E
P 002F

EB

BO
CE
50
BF

EF
13
EF

64

EE
OB
EE

3C

ED 3C
03
ED
FD

I
2
3
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II
12
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35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

TIMER I
MODULE
CONSTANT
HOUR
RI2
.MINUTE .RI3
RI4
SECOND .HUND
RI5
.$SECTION PROGRAM
GLOBAL
!!RQ5 interrupt vector!
$ABS
10
IRQ_5
[I WORD]
ARRAY

.-

[TOD]

$REL
TOD.--INIT
ENTRY

END
TOD
ENTRY

PROCEDURE

LD

PREI,#(2)

LD

Tl,#O

OR
TMR,#OCH
DI
OR
IMR,#20H
EI
RET
TOD_INIT

10010011H
!bit 2-7: prescaler = 36,
bit I: internal clock;
bit 0: continuous mode!
!(256) time-out =
11 100 second!
!load, enable Tl!
!enable Tl interrupt!

PROCEDURE

PUSH
RP
!Working register file IOH to IFH contains
the time of day clock!
SRP
#IOH
INC
HUND
! I more .01 sec!
CP
HUND,#lOO
!full second yet?!
NE,TODJXIT !jump if no!
!R
CLR
HUND
INC
SECOND
! I more second!
CP
SECOND,#60 !full minute yet?!
!jump if no!
NE,TODJXIT
JR
CLR
SECOND
INC
MINUTE
! 1 more minute!
MINUTE,#60 !full hour yet?!
CP
NE,TODJXIT !jump if no!
JR
CLR
MINUTE
INC
HOUR
TODJXIT:
!restore entry RP!
POP
RP
!RET
TOD
END
END
TIMER I

o ERRORS
ASSEMBLY COMPLETE
TOD.-lNIT:
7 instructions
15 bytes
16 ~s

280

TOD:
17 instruction
32 bytes
19.5 f.tS (average) including interrupt response time

Timer/Counter (Continued)
Variable Frequency, Variable Pulse Width
Output. The following module illustrates one
possible use of TOUT. Assume it is necessary
to generate a pulse train with a 10% duty
cycle, where the output is repetitively high
for 1.6 ms and then low for 14.4 ms. To do
this, TOUT is controlled by end-of-count from
T I, althrough To could alternately be chosen.
This example makes use fa the Z8 feature
that allows a timer's counter register to be
modified without disturbing the count in
progress. In continuous mode, the new value
is loaded when TI reaches EOC. TI is first
loaded and enabled with values to generate
the short interval. The counter register is
then immediately modified with the value to
generate the long interval; this value is
loaded into the counter automatically on TI
EOC. The prescaler selected value must be
the same for both long and short intervals.
Note that the initial loading of the TI counter

register is followed by setting the TI load bit
of timer control register TMR (FIH); this
action causes TOUT to be reset to a logic 1
output. Each subsequent modification of the
T I counter register does not affect the
current TOUT level, since the TI load bit is
NOT altered by the software. The new value
is loaded on EOC, and TOUT will toggle at
that time. The TI interrupt service routine
should simply modify the TI, counter register
with the new value, alternating between the
long and short interval values.
In the example which follows, bit of
register 04H is used as a software flag to
indicate which value was loaded last. This
module illustrates the procedure for TI/ToUT
initialization (PULSE~NIT), the TI interrupt
service routine (PULSE), and the interrupt
vector for TI EOC (IRQ_5). XTAL = 8 MHz
is assumed.

a

MACZ8
2.0
LOC
OBJ CODE STMT SOURCE STATEMENT
I TIMER2 MODULE
2
$SECTION PROGRAM
3 GLOBAL
4 !IRQ5 interrupt vector!
$ABS
10
5
6 IRQ_5 ARRAY
[I WORD]
P 0000 0017'

[PULSE]

7

P OOOC
P 0000

E6

F3

P 0003
P 0006
P 0009
P OOOA
P OOOD

E6
E6
8F
46
E6

F7
F2

P 0010

00
19

FB 20
FI 8C

E6

F2

P 0013

BO

04

P 0015
P 0016
P 0017

9F
AF

P 0017

03

EI

8
9
10
II
12
13
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15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

$REL
PULSE--.INIT
ENTRY
LD

LD
LD
DI

OR
LD

PROCEDURE
PRE I, # (2)000000 II H

P3M, #00
Tl, #25
IMR, # (2)001 OOOOOH
TMR, #(2)IOOOIIOOH

!bit
bit
bit
!bit

2-7: prescaler=64;
1: internal clock;
0: continuous mode!
5: let P36 be Tout!
!for short interval!
!enable Tl interrupt!

!bit 6-7: Tout controlled
by Tl;
bit 3: enable Tl;
bit 2: load Tl!
!Set long interval counter. to be loaded on Tl EOC!
LD
Tl, #225
!Clear alternating flag for PULSE!
! = 0:25 next;
CLR
04H
= I :225 next!
END
PULSE
ENTRY

PROCEDURE

281

Timer/Counter Functions (Continued)
P
P
P
P

0017
OOIA
OOID
OOIF

E6
B6
6B
E6

P 0022
P 0023

BF

F2
04
03
F2

EI
01
19

36
LD
37
XOR
38
JR
39
LD
40 PULSEJXIT:
41
IRET
42 END
PULSE
43 END
TIMER2

Tl,#225
04H, # I
Z,PULSEJXIT
TI,#25

!new load value!
!which value next?!
!should be 225!
!should be 25!

o ERRORS
ASSEMBLY COMPLETE
PULSE~NIT:

PULSE:
5 instructions
12 bytes

10 instructions
23 bytes
23 ~s

25 p.s (overage) including interrupt response time

Cascaded Timer/Counters. For some
applications it may be necessary to measure
a greater time interval than a single
timer/counter can measure (16.384 ms). In
this case, TIN and TOUT may be used to
XTAL

cascade To and TI to function as a single
unit. TOUT, programmed to toggle on To
end-of-count, should be wired back to TIN,
which is selected as the external clock input
for TI. With To programmed for continuous
mode, TOUT (and therefore TIN) goes
through a High-to-Low transition (causing TI
to count) on every other To EOC. Interrupt
request IRQ5 is generated when the
programmed time interval has elapsed.
Interrupt requests IRQ2 (generated on every
TIN High-to-Low transition) and IRQ4
(generated on To EOC) are of no importance
in this application and are therefore
disabled.
To determine the time interval (i) until
EOC, the equation
i = t X pO X vO X (2 X pI X vl- I)

TO INTERRUPT LOGIC (IRQ4)

characterizes the relation between the To
prescaler (pO) and counter (vO), the TI
prescaler (pI) and counter (vI), and the
clock input period (t); t is defined in Section
7. 1. Assuming XT AL = 8 MHz, the
measurable time interval range is
I
I
I

TO INTERRUPT LOGIC (lRQS)

Figure 3. Cascaded Timer/Col1nters

282

!,-S X I X I X (2 X I - 1) :5 i :5
!,-S X 64 X 256 X (2 X 64 X 256 !,-S :5 i :5 536.854528 s

1)

Figure 3 illustrates the interconnection
between To and TI. The following module
illustrates the procedure required to
initialized the timers for a 1.998 second
delay interval:

Timer/Counter Functions (Continued)
MACZ8
LOC

2.0
OBJ CODE STMT SOURCE STATEMENT

P 0000
E6

F3

28

P 0003.r E6
P 0006 E6
P 0009 E6

F7
F2
F5

00
64
29

P OOOC
P OOOF
P 0010

E6
8F
56

F4

64

FE

2E

P 0013
P 0016
P 0017

46
9F
E6

FE

20

FI

4F

P OOIA
POOlE

AF

P 0000

I
2
3
4
5
6
7

8
9

10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

TIMER3
MODULE
GLOBAL
TIMER_16
PROCEDURE
ENTRY
PREI, #(2)00101000H
LD
!bit 2·7: prescaler = 10;
bit I: external clock;
bit 0: single· pass mode!
P3M, #00
!bit 5: let P36 be Tout!
LD
TI, # 100
!TI counter register!
LD
PREO, # (2)00l0100lH
LD
!bit 2·7: prescaler = 10;
bit 0: continuous mode!
TO,
#
100
1TO counter register!
LD
DI
AND IMR, # (2)001010lIH !disable IRQ2 (Tin);
and IRQ4 (TO) !
IMR, # (2)00l00000H !enable IRQ5 (TI)!
OR
EI
TMR, #(2)01001l1IH
LD
!bit 6-7: Tout controlled
by TO;
bit 4-5: Tin mode is ext.
clock input;
bit 3: enable TI;
bit 2: load TI;
bit I: enable TO;
bit 0: load TO!
RET
TIMER_I 6
END
TIMER3
END

o ERRORS
ASSEMEL Y COMPLETE
11

instructions

27 bytes
26.5 J'S

Clock Monitor. TI and TIN may be used to
monitor a clock line (in a diskette drive, for
example) and generate an interrupt request
when a clock pulse is missed. To accomplish
this, the clock line to be monitored is wired
to P3, (TIN). TIN should be programmed as a
retriggerable input to T I, such that each
falling edge on TIN will cause TI to reload
and continue counting. If TI is programmed
to time-out after an interval of one-and-a-half
times the clock period being monitored, TI
will time-out and generate interrupt request
IRQS only if a clock pulse is missed.

The following module illustrates the
procedure for initializing TI and TIN
(MONITOR_INIT) to monitor a clock with a
period of 2 !,S. XTAL = 8 MHz is assumed.
Note that this example selects single-pass
rather than continuous mode for T I. This is
to prevent a continuous stream of IRQ5
interrupt requests in the event that the
monitored clock fails completely. Rather, the
interrupt service routine (CLKJRR) is left
with the choice of whether or not to reenable the monitoring. Also shown is the TI
interrupt vector (lRQ_5).

283

Timer/Counter Functions (Continued)
2.0
MACza
LOC
OBJCODE STMT SOURCE STATEMENT

P 0000

0015'

P OOOC
P 0000

E6

F3

04

P 0003
P 0006

E6
E6

F7
F2

00
03

P
P
P
P

8F
56
46
9F

FB 3B
FB 20

P DOli

E6

FI

P 0014
POOlS

AF

0009
OOOA
OOOD
0010

38

POOlS

POOlS

46

P 0018
P 0019

BF

FI

08

I
2
3
4
5
6
7
8
9
10
11
12
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23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

TIMER4

MODULE
$SECTION PROGRAM
GLOBAL
!IRQ5 interrupt vector!
$ABS
10
IRQ_5
ARRAY [I WORD]

$REL
MONITOR.-INIT
ENTRY
LD

LD
LD
DI
AND
OR
EI
LD

END

.-

[CLKJRR]

PROCEDURE
PRE I, # (2)000001 OOH
!bit 2-7: prescaler = I;
bit I: external clock;
bit 0: single-pass mode!
P3M,#00
!bit 5: let P36 be Tout!
!Tl load register,
Tl,#3
= 1.5 • 2 usee!
IMR,#(2)00111OIlH !disable !RQ2 (Tin)!
IMR, # (2)00100000H !enable !RQ5 (Tl)!
TMR, # (2)001ll000H
!bit 4-5: Tin mode is
retrig. input;
bit 3: enable Tl!

RET
MONITOR.-INIT

CLK.......ERR PROCEDURE
ENTRY
I. .. !

!handle the missed clock!

Iif clock monitoring should continue ... !
TMR, # (2)00001000H
OR
!bit 3: enable Tl!
IRET
END
CLKJRR
TIMER4
END

o ERRORS
ASSEMBLY COMPLETE
MONITOR-INIT:
9 instructions
21 bytes
21.5 p.s

284

CLK.....ERR:
2 + instructions
4 + bytes
18.5 + p.s including interrupt response time

I/O Functions
The Z8 provides 32 I/O lines mapped into
registers 0-3 of the internal register file.
Each nibble of port 0 is individually
programmable as input, output, or
address/data lines (AI5-AI2, All-As). Port I
is programmable as a single entity to provide
input, output, or address/data lines
(AD7-ADO). The operating modes for the bits
of Ports 0 and I are selected by control
register POIM (F8H). Selection of I/O lines
as address/data lines supports access to
external program and data memory; this is
discussed in Section 3. Each bit of Port 2 is
individually programmable as an input or an
output bit. Port 2 bits programmed as
outputs may also be programmed (via bit 0
of P3M) to all have active pull-ups or all be
open-drain (active pull-ups inhibited). In
Port 3, four bits (P30-P33) are fixed as inputs,
and four bits (P34-P37) are fixed as outputs,
but their functions are programmable.
Special functions provided by Port 3 bits are
listed in Table 4. Use of the Data Memory
select output is discussed in Section 3; uses
of TIN and TOUT are discussed in Section 7.

Asynchronous Receiver/Transmitter
Operation. Full-duplex, serial asynchronous
receiver/transmitter operation is provided by
the Z8 via P37 (output) and P30 (input) in
conjunction with control register S10 (FOH),
which is actually two registers: receiver buffer
and transmitter buffer. Counter/Timer TO
provides the clock for control of the bit rate.
The Z8 always receives and transmits .eight
bits between start and stop bits. However, if
parity is enabled, the eighth bit (D7) is
replaced by the odd-parity bit when
transmitted and a parity-error flag (= I if
error) when received. Table 5 illustrates the
state of the parity bit/parity error flag during
serial I/O with parity enabled.
Although the Z8 directly supports either
odd parity or no parity for serial I/O
operation, even parity may also be provided
with additional software support. To receive

Functions

Bit

Signal

P3j
P32
P33
P34
P35
P36

DAV2/RDY2
DAVO/RDYO

DAVIIRDYI
RDY IIDAV I

P30
P3j
P32
P33

IRQ3
IRQ2
IRQO
IRQI

P3 j
P30

TIN
TOUT

Data Memory
Select
Status Out

P34

DM

Serial 1/0

P30
P3 7

Serial In
Seria Out

Handshake

Interrupt
Request
Counter!
Timer

RDYO/DAVO
RDY2/DAV2

Table 4. Port 3 Special Functions

and transmit with even parity, the Z8 should
be configured for serial I/O with odd parity
disabled. The Z8 software must calculate
parity and modify the eighth bit prior to the
load of a character into SIO and then modify
a parity error flag following the load of a
character form SIO. All other processing
required for serial I/O (e.g. buffer
management, error handling, etc.) is the
same as that for odd parity operations.
To configure the Z8 for Serial I/O, it is
necessary to:
• Enable P30 and P37 for serial I/O and
select parity,
• Set up To for the desired bit rate,
• Configure IRQ3 and IRQ4 for polled or
automatic interrupt mode,
.Load and enable To.

Character Loaded
Into SIO

Transmitted To
Serial Line

Received From
Serial Line

Character
Transferred to SIO

11000011
11000011
01111000
01111000

01000011
01000011
11111000
11111000

01000011
01000111
11111000
01111000

01000011
11000111
01111000
IIl1lOao

Table 5. Serial 1/0 With Odd Pgrily

Note"
no error

error
no error
error
*

Left-most bit is D7

285

I/O Functions (Continued)
To enable P30 and P37 for serial I/O, bit 6 of
P3M (R247) is set. To enable odd parity, bit
7 of P3M is set; to disable it, the bit is reset.
For example, the instruction
LD

P3M,#40H

will enable serial IIO, but disable parity. The
instruction
LD

P3M,#COH

will enable serial IIO, and enable odd
parity.
In the, following discussions, bit rate refers
to all transmitted bits, including start, stop
and parity (if enabled). The serial bit rate is
given by the equation:
input clock frequency
bit rate = -----=----~~---~
(2 x 4 x TO prescaler X TO counter x 16)

The final divide-by-16 is incurred for serial
communications, since in this mode To runs
at 16 times the bit rate in order to
, synchronize the data stream. To configure
the Z8 for a specific bit rate, appropriate
values must first be selected for To prescaler
and To counter by the above equation; these
values are then programmed into registers To
(F4H) and PREO (F5H) respectively. Note
that PREO also controls the continuous vs.
single-pass mode for To; continuous mode
should be selected for serial I/O. For example,
, given an input clock frequency of 7.3728 MHz
and a selected bit rate of 9600 bits per second,
the equation is satisfied by TO counter = 2 and
prescaler = 3. The following code sequence
will configure the To counter and To
prescaler registers:
LD
LD

286

To#2
!To counter=2!
PREO, # (2)000011OIH
!bit 2-7: prescaler=3; bit 0:
continuous mode!

Interrupt request 3 (IRQ3) is generated
whenever a character is transferred into the
receive buffer; interrupt request 4 (IRQ4) is
generated whenever a character is
transferred out of the transmit buffer. Before
accepting such interrupt requests, the
Interrupt Mask, Request, and Priority
Registers (IMR, IRQ, and IPR) must be
programmed to configure the mode of
interrupt response. The section on Interrupt
Processing prOVides a discussion of interrupt
configurations.
To load and enable To, set bits 0 and 1 of
the timer mode register (TMR) via an
instruction such as
OR

TMR,#03H

This will cause the To prescaler and counter
registers (PREO and To) to be transferred to
the To prescaler and counter. In addition, To
is enabled to count, and serial IIO
operations will commence.
Characters to be output to the serial line
should be written to serial IIO register SIO
(FOH). IRQ4 will be generated when all bits
have been transferred out.
Characters input from the serial line may
be read from SIO. IRQ3 will be generated
when a full character has been transferred
into SIO.
The following module illustrates the receipt
of a character and its immediate echo back
to the serial line. It is assumed that the Z8
has been configured for serial IIO as
described above, with IRQ3 (receive)
enabled to interrupt, and IRQ4 (transmit)
configured to be polled. The received
character is stored in a circular buffer in
register memory from address 42H to 5FH.
Register 41H contains the address of the next
available buffer position and should have
been initialized by some earlier routine to
#42H.

I/O Functions (Continued)
MACZ8
LOC

P 0006

2.0
OBI CODE STMT SOURCE STATEMENT

0000'

P 0000

P 0000

E4

FO

FO

P 0003
P 0006
P 0008

F5
20
A6

FO
41
41

41
60

P OOOB
P OOOD

EB
E6

03
41

42

P 0010
P 0013

66
EB

FA
FB

10

P 0015

56
F
BF

FA

E-

P 0018
P 0019

I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

SERIALJO
MODULE
CONSTANT
next_addr
41H
start
42H
.length
lEH
$SECTION PROGRAM
GLOBAL
!lRQ3 vector!
$ABS
6
lRQ_3
ARRAY [I WORD] : = [GET_CHARACTER]
$REL
0
GET_CHARACTER PROCEDURE

ENTRY

!Serial I/O receive interrupt service!
!Echo received character and wait for
echo completion!
ld
SIO,SIO

!echo!

!save it in circular buffer!
ld
@next_addr,SIO

!save in buffer!

inc

next_addr

!point to next position!

next_addr, # start + length
!wrap-around yet?!
ne ,echo_wait
jr
Ina.!
ld
next_addr, # start
!yes. point to start!
!now, wait for echo complete!
echo_wait:
!transmitted yet?!
lRQ,#IOH
tcm
jr
!not yet!

32
33
34 END
35 END

cp

and
lRQ,#EFH
lRET
GET_CHARACTER
SERIALJO

!clear lRQ4!
!return from interrupt!

o ERRORS
ASSEMBLY COMPLETE
10 instructions
25 bytes
35.5 (.AS + 5.5/1-8 for each additional pass through the echo_waif loop,
including interrupt response time

Automatic Bit Rate Detection. In a typical
system, where serial communication is
required (e.g. system with a terminal), the
desired bit rate is either user-selectable via a
switch bank or nonvariable and "hardcoded" in the software. As an alternate
method of bit-rate detection, it is possible to
automatically determine the bit rate of serial
data received by measuring the length of a
start bit. The advantage of this method is that
it places no requirements on the hardware
design for this function and provides a
convenient (automatic) operator interface.

In the technique described here, the serial
channel of the 28 is initialized to expect a bit
rate of 19,200 bits per second. The number
of bits (n) received through Port pin P30 for
each bit transmitted is expressed by
n= 19,200/b

where b = transmission bit rate. For example,
if the transmission bit rate were 1200 bits per
second, each incoming bit would appear to
the receiving serial line as 19,20011200 or 16
bits.

287

1/0 Functions (Continued)
The following example is capable of
distinguishing between the bit rates shown in
Table 6 and assumes an input clock
frequency of 7.3728 MHz, a To prescaler of
3, and serial I/O enabled with parity
disabled. This example requires that a
character with its low order bit = I (such as a
carriage return) be sent to the serial
chann~l. The start bit of this character can
be measured by counting the number of zero
bits collected before the low order I bit. The
number of zero bits actually collected into
data bits by the serial channel is less than n
(as given in the above equation), due to the
detection of start and stop bits.
Figure 4 illustrates the collection (at 19,200
bits per second) of a zero bit transmitted to
the Z8 at 1,200 bits per second. Notice that
only 13 of the 16 zero bits received are
collected as data bits.
Once the number of zero bits in the start
bit has been collected and counted, it
remains to translate this count into the
appropriate To counter value and program
that value into To (F4H). The patterns shown
in the two binary columns of Table 6 are
utilized in the algorithm for this translation.
As a final step, if incoming data is to

Bit Rate

Number of Bits Received
Per Bit Transmitted

19200
9600
4800
2400
1200
600
300
150

commence immediately, it is advisable to
wait until the remainder of the current
"elongated" character has been received,
thus "flushing" the serial line. This can be
accomplished either via a software loop, or
by programming TI to generate an interrupt
request after the appropriate amount of time
has elapsed. Since a character is composed
of eight bits plus a minimum of one stop bit
following the start bit, the length of time to
delay may be expressed as
(9 X n)/b

where nand b are as defined above. The
following module illustrates a sample
program for automatic bit rate detection.

lBTI

I"

DO

I 01 ID'I OSI

04105 I O'

lOTI &PI STlDO I 01,0'

51"" START BIT

SP = ..STOP BIT

Number of 0 Bits Collecled
as Data Bits
dec

binary

0

00000000
00000001
00000011
00000111
00001101
00011001
00110001
01100001

3
7
13
25
49
97

MACZ8
2.0
LOC
OBI CODE STMT SOURCE STATEMENT

288

04\
"'1

On = DATA BIT n

Figure 4. Collection of a Start Bit Transmitted at
1.200 BPS and Receive at 19,200 BPS

Table 6. Inputs to Ihe Automatic Bit Rate Detection Algorithm

P 0000

I

EACH INTERVAL SHOWN"" 1 BIT TIME
AT 19,200 BITS PER SECOND

2
4
8
16
32
64
128

I
2
3
4
5
6

100

1 BIT TIME AT 1,200 BITS PER SECOND

biLrate
EXTERNAL
DELAY PROCEDURE
GLOBAL
main
PROCEDURE
ENTRY

MODULE

TO Counter
dec

binary

2
4
8
16
32
64
128

00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000

I/O Functions (Continued)
P
P
P
P
P
P

0000
0001
0004
0007
OOOA
OOOD

8F
56
56
E6
E6
E6
D

FB
FA
F7
F4
F5

P 0010
P 0012

BO
E6

EO
FI

77
F7
40
01
0

03

P
P
P
P
P
P
P
P

0015 76 FA 08
0018 6B FB
OOIA 18 FO
OOIC 56 FA F7
OOIF IE
0020 IA 05
0022 06 EO 08
0025 8B EE

P
P
P
P

0027 EO EI
0029 7B 03
002B
OE
002C 8B F9

P 002E
P 0030
P 0032

IC
2C
90

07
80
EO

P
P
P
P

90
7B
EO
IA

EO
04
E2
F8

P 003C 29

F4

0034
0036
0038
003A

7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

di
and
and
ld
ld

IMR,#77H
IRQ, #F7H
P3M,#40H
TO,#I

ld

PREO,#(3

clr
ld

RO
TMR,#3

P 003E

D6

0000'

P 0041

56

FA

F7

P 0044

SHL 2)+ I !bit rate = 19,200;
continuous count mode!
!ini\' zero byte counter!
!load and enable TO!

!collect input bytes by counting the number of null
characters received. Stop when non-zero byte received!
collect:
TM
IRQ,#08H !character received?!
jr
Inot yet!
z,collect
ld
RI,SIO
!get the character!
IRQ,#F7
and
!clear interrupt request!
inc
RI
!compare to 0 ... !
djnz
RI,bitloop
!. .. (in 3 bytes of code)!
RO,#8
add
!update count of 0 bits!
jr
collect
bitloop:
!add in zero bits from low!
end of 1st non-zero byte!
RR
RI
jr
c, counLdone
inc
RO
jr
bitloop
IRO has number of zero bits collected!
!translate RO to the appropriate TO counter value!
counLdone:
!RO has count of zero bits!
RI,#7
ld
R2,#80H
!R2 will have TO counter
ld
RL
value!
RO
loop:

RL
jr
RR
djnz

RO
c,done
R2
rl,loop

done:

ld

TO,R2

48

49
50
51
52
53
54
55

!disable interrupts!
!IRQ3 polled mode!
!clear IRQ3!
tenable serial I/O!

!load value for detected
bit rate!

!Delay long enough to clear serial line of bit stream!
call
DELAY
!clear receive interrupt requestl

and
END
END

IRQ,#F7H

main

biLrate

o ERRORS
ASSEMBLY COMPLETE
30 instructions

68 bytes
Execution time is variable based on transmission bit rale.

289

1/0 Functions (Continued)

Port Handshake. Each of Ports 0, I and 2
may be programmed to function under input
or output handshake control. Table 7 defines
the port bits used for the handshaking and
the mode bit settings required to select
handshaking. To input data under handshake
control, the 28 should read the input port
when the DAV input goes Low (signifying
that data is available from the attached
deVice). To output data under handshake
control, the 28 should write the output port
when the RDY input goes Low (signifying
that the previously output data has been
accepted by the attached device).
Interrupt requests !RQO, IRQI, and IRQ2 are
generated by the falling edge of the
handshake signal input to the 28 for Port 0,
Port I, and Port 2 respectively. Port
handshake operations may therefore be
processed under interrupt control.
Consider a system that requires
communication of eight parallel bits of data
under hand-shake control from the 28 to a
peripheral device and that Port 2 is selected
as the output port. The following assembly
code illustrates the proper sequence for
initializing Port 2 for output handshake.

Port 0

CLR P2M

!Port 2 mode register: all
Port 2 bits are outputs!
OR
03H,#40H
!set DA V2: data not available!
LD
P3M,#20H
!Port 3 mode register: enable
Port 2 handshake!
LD 02H,DATA
!output first data byte; DAV2
will be cleared by the 28 to
indicate data available to
the peripheral device!
Note that following the initialization of the
output sequence, the software outputs the
first dat byte without regard to the state of
the RDY2 input; the 28 will automatically
hold DA V2 High until the RDY2 input is
High. The peripheral device should force the
28 RDY2 input line Low after it has latched
the data in response to a Low on DAV2. The
Low on RDY2 will cause the 28 automatically
force DAV2 High until the next byte is
output. Subsequent bytes should be output in
response to interrupt request IRQ2 (caused
by the High-to-Low transition on RDY2) in
either a polled or an enabled interrupt
mode.

Port I

Port 2

Input handshake lines

( P32=DAV
P3s=RDY

P33= DAV
P34= RDY

P31=DAV
P36=RDY

Output handshake lines

( P32=RDY
P3s= DAV

P33=RDY
P34= DAV

P31=RDY
P36=DAV

To select input handshake:

( set bit 6 & reset bit 7 of
POIM (program high
nubble as input)

set bit 3 & reset bit 4 of
POIM (program byte as
input)

set bit 7 of P2M
(program high bit as input)

To select output handshake:

( reset bits 6,7 of POIM
(program high nibble as
output)

reset bits 3, 4 of POIM
(program byte as output)

reset bit 7 of P2M
(program high bit as output)

To enable handshake:

( set bit 5 of Port 3 (P3s );
set bit 2 of P3M

set bit 4 of Port 3 (P34);
set bits 3, 4 of P3M

set bit 6 of Port 3 (P36);
Bet bit 5 of P3M

Table 7. Port Handshake Selection

290

Arithmetic Routines

viewed as a string of four nibbles and is
processed one nibble at a time from left to
right, beginning with the high-order nibble
of the lower memory address. 30H is added
to each nibble if it is the range 0 to 9;
otherwise 37H is added. In this way, OH is
converted to 30H, lH to 3lH, ... AH to 4lH,
... FH to 46H. Figure 5 illustrates the
conversion of RRO (contents = F2BEH) to its
hex ASCII equivalent; the destination buffer
is pointed to by RR4.

This section gives examples of the
arithmetic and rotate instructions for use in
multiplication, division, conversion, and
BCD arithmetic algorithms.

Binary to Hex ASCII. The following module
illustrates the use of the ADD and SWAP
arithmetic instructions in the conversion of a
16-bit binary number to its hexadecimal
ASCII representation. The l6-bit number is

D7

Do

4 S

II,.;~j[1""".q; ik.· •.<.!iI'/Ii~!1

"

Figure 5. Conversion of (RRO) to Hex ASCII

MACZS 2.99 INTERNAL RELEASE
LOC
OBJ CODE STMT SOURCE STATEMENT
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15

P 0000

P 0000

P 0002
P 0004
P 0006

6C 04
FO EO
28 EO
56 E2

OF

ARITH
MODULE
GLOBAL
BINASC
PROCEDURE
! '" '" '" * * '" * '" * "'. '" '" * * * '" * * * * '" '" * *. '" *. *. '" '" '" '" * '" '" '" '" * * '" '" ** '" '" * * '" ** '" * '" ** '" "' .. '" *. '" *** '" * '"
Purpose
To conver! a 16· bit binary
number to Hex ASCII
Input

RRO
16·bit binary number.
RR4 = pointer to destination
buffer in external memory.

Output

Resulting ASCII string (4 bytes)
in destination buffer.
RR4 incremented by 4.
RO, R2, R6 destroyed.

16 '" '" '" '" '" * '" '" '" '" '" '" '" **** '" '" '" '" '" '" * '" * '" '" '" * '" '" '" '" '" '" * ** '" '" '" ** ** '" '" '" '" * '" '* '" '" '" '" '" '" '" '" '" '" '" '" '" -It.,. '" '" '"

r

17 ENTRY
18
19
20 again:
21
22

.
ld
SWAP
Id
and

R6,#04H
RO
R2.RO
R2.#OFH

!nibble count!
!look at next nibble!
!isolate 4 bits!

291

Arithmetic Routines (Continued)

P 0009
P OOOC
P OOOF
paOlI
P 0014
P 0016

06 E2 30
A6 E2 3A
7B 03
06 E2 07
92 24
AO E4

P 0018
P OOIB
P OOlD

A6
EB
08

P OOIF
P 0021
P 0022

6A El
AF

E6
02
El

03

23 !convert to ASCII: R2 + # 30H if RO in range 0 to 9
24
else R2 + # 37H (in range OA to OF)
25!
26
ADD
R2,#30H
cp
27
R2,#3AH
ult,skip
28
ir
R2,#07H
29
ADD
30 skip:
@RR4,R2
Ide
!save ASCII in buffer!
!point to next
31
incw
RR4
buffer position!
32
cp
R6, #03H
!time for second byte?!
33
ne,same~yte
!no.!
34
ir
RO,Rl
!2nd byte!
35
ld
36 same~yte:
37
dinz
R6,again
38
ret
39 END
BINASC
40 END
ARITH

o ERRORS
ASSEMBLY COMPLETE
15 instructions
34 bytes

120.5

~s (average)

BCD Addition. The following module
illustrates the use of the add with carry
(ADC) and decimal adjust (DA) instructions
for the addition of two unsigned BCD strings
of equal length. Within a BCD string, each
nibble represents a decimal digit (0-9). Two
such digits are packed per byte with the

most significant digit in bits 7-4. Bytes within
a BDC string are arranged in memory with
the most significant digits stored in the
lowest memory location. Figure 6 illustrates
the representation of 5970 in a 6-digit BCD
string, starting in register 33H.

BIT

REGISTER

%33

%34

Figure 6. Unsigned BCD Representation

292

%35

Arithmetic Routine (Continued)
MACZ8
LOC

2.0
OBl CODE STMT SOURCE STATEMENT
I
2
3
4
5
6
7

P 0000

8

ARITH
MODULE
CONSTANT
BCD_SRC: = RI
BCD_DST: = RO
BCD_LEN: = R2
GLOBAL
BCD ADD PROCEDURE
! ***********************************************************************
Purpose =
To add two packed BCD strings of
equal length.
dst < -- dst + src

9
10
II
12
13 Input
14
15
16
17
18 Output
19
20
21
22

RO
RI
R2

pointer to dst BCD string.
pointer to src BCD string.
byte count in BCD string
(digit count = (R2)'2).

BCD string pointed to by RO is
the sum.
Carry FLA G = I if overflow.
RO, RI as on entry.
R2 = 0

23 *** *** **** ***** ** **** * * ** ***** * ******************* * ****** **** * * * ***** * * !

P 0000
P 0002
P 0004

02
02
CF

12
02

P 0005

00

El

P 0007

00

EO

P
P
P
P
P

0009
OOOB
OOOD
OOOF
0011

E3
13
40
F3
2A

31
30
E3
03
F2

P 0013

AF

P 0014

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

ENTRY
add
add
ref

BCD_SRC,BCD_LEN

dec

BCD_SRC

BCD~ST,BCD_LEN

!start at leas!...!
!significant digits!
!carry = O!

adLagain:
dec

BCD~ST

ld
ADC
DA
ld
djnz

R3,@BCD_SRC
R3,@BCD_DST
R3
@BCD~ST,R3
BCD~EN ,adLagain

ret
END
END

!point to next two
src digits!
!point to next two
dst digits!
!get src digits!
!add dst digits!
!decimal adjust!
!move to dst!
!loop for next
digits!
!all done!

BCD ADD
ARITH

o ERRORS
ASSEMBLY COMPLETE
11 instructions
20 bytes
Execution time is a function of the number of bytes (n) in input BCD siring;

20 ps + 12.5 (m . 1) ps

293

Arithmetic Routines (Continued)
Multiply. The following module illustates an
efficient algorithm for the multiplication of
two unsigned 8-bit values, resulting in a
16-bit product. The algorithm repetitively
shifts the multiplicand right (using RRC),
with the low-order bit being shifted out (into
the carry flag). If a one is shifted out, the
multiplier is added to the high-order byte of

the partial product. As the high-order bits of
the multiplicand are vacated by the shift, the
resulting partial-product bits are rotated in.
Thus, the multiplicand and the low byte of
the product occupy the same byte, which
saves register space, code, and execution
time.

MACZ8 2.99 INTERNAL RELEASE
LOC
OBJ CODE STMT SOURCE STATEMENT
I
2
3
4
5
6
7
8

ARITH
MODULE
CONSTANT
MULTIPLIER . RI
PRODUCT_LO: =
R3
PRODUCT_HI: =
R2
COUNT
.RO
GLOBAL
MULT
PROCEDURE
9 ! ***********************************************************************
10 Purpose =
To perform an 8-bit by 8-bit unsigned
II
binay multiplication.
12
RI = multiplier
13 Input =
R3 = multiplicand
14
15
16 Output =
RR2 = product
17
RO destroyed

P 000

18

P 0000
P 0002
P 0004
P 0005
P 0007
P 0009
P OOOB
P OOOD
P OOOF
paolO

OC
BO
CF
CO
CO
FB
02
OA
AF

09
E2
E2
E3
02
21
F6

19
20
21
22
23
24
25
26
27
28
29
30

*****************************************************************A*****!

ENTRY

LOOP:

NEXT:
END
END

!8 BITS + I!
Id
COUNT,#9
PRODUCT_HI !INIT HIGH RESULT BYTE!
clr
RCF
!CARRY = O!
RRC PRODUCT_HI
RRC PRODUCT_LO
NC,NEXT
jr
ADD PRODUCT_HI, MULTIPLIER
djnz COUNT,LOOP
ret
MULT
ARITH

o ERRORS
ASSEMBLY COMPLETE
9 instructions
16 bytes
92.5 p.S (average)

Divide. The following module illustrates an
efficient algorithm for the division of a 16-bit
unsigned value by an 8-bit unsigned value,
resulting in an 8-bit unsigned quotient. The
algorithm repetitively shifts the dividend left
(via RLC). If the high-order bit shifted out is
a one or if the resulting high-order dividend
byte is greater than or equal to the divisor,

294

the divisor is subtracted from the high byte
of the dividend. As the low-order bits of the
dividend are vacated by the shift left, the
resulting partial-quotient bits are rotated in.
Thus, the quotient and the low byte of the
dividend occupy the same byte, which saves
register space, code, and execution time.

Arithmetic Routine (Continued)
MACZ8
LOC

2.0
OBl CODE STMT SOURCE STATEMENT

P 0000

P 0000

OC

08

P 0002
P 0004

A2
BB

12
02

P 0006
P 0007

DF
AF

P
P
P
P
P
P
P
P

0008
OOOA
OOOC
OOOE
0010
0012
0014
0015

10
10
7B
A2
BB
22
DF
OA

E3
E2
04
12
03
21

P 0017

10

E3

P 0019
P OOIA

AF

FI

I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

ARITH
MODULE
CONSTANT
COUNT
DIVISOR
DIVIDEND_HI
DIViDEND_LO
.GLOBAL
DIVIDE
PROCEDURE

RO
RI
R2
R3

! ***********************************************************************

Purpose =

To perform an 16-bit by 8-bit unsigned
binary division.

Input =

RI = 8-bit divisor
RR2 = 16-bit dividend

Output

=

R3 = 8-bit quotient
R2 = 8-bit remainder
Carry flag = I if overflow
= 0 no overflow

***********************************************************************

!

ENTRY
ld

COUNT,#8

!LOOP COUNTER!

!CHECK IF RESULT WILL FIT IN 8 BITS!
cp
DIVISOR, DIVIDEND_HI
UGT,LOOP
!CARRY
o (FOR RLC)!
jr
!WON'T FIT. OVERFLOW!
SCF
!CARRY = I!
ret
LOOP:

subt:
next:

!RESULT WILL FIT. GO AHEAD WITH DIVISION
RLC
DIVIDEND_La DIVIDEND • 2!
RLC
DIVIDEND_HI
c,subt
jr
cp
DIVISOR,DIVIDEND_HI
jr
UGT,next
!CARRY = O!
SUB
DIVIDEND_HI, DIVISOR
!TO BE SHIFTED INTO RESULT!
SCF
COUNT,LOOP !no flags affected!
djnz

!ALL

DONE!
RLC
DIVIDEND--.-LO
!CARRY
ret
END DIVIDE
END ARITH

0: no overflow!

o ERRORS
ASSEMBLY COMPLETE
15 instructions

26 bytes
124.5 p.S (average)

295

Conclusion
This Application Note has focused on ways
in which the 28 microcomputer can easily yet
effectively solve various application
problems. In particular, the many sample
routines illustrated in this document should

296

aid the reader in using the 28 to greater
advantage. The major features of the 28 have
been described so that the user can continue
to expand and explore the 28' s repertoire of
uses.

Copyright 1980, 1981, 1983 by Zilog Inc. All rights reserved. No part of this publication may be reproduces, stored in a retrieval system,
or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written permission of Zilog. The information contained herein is published by SGS and subject to change without notice. SGS assumes no responsibility
for the use of circuitry embolied in the product. No other circuit patent licences are implied.

SGS GROUP OF COMPANIES
Italy - Brazil - France - Malta - Malaysia - Singapore - Sweden - Switzerland - United Kingdom - U.S.A. - West Germany
© 1986 SGS, All Rights Reserved - Printed in Italy
*

Z8 is a registered trademark of Zilog Inc.

Garzanti s.p.a. - Cernusco s./N.
Fotocomposizione - Servoffset - Milano

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Telex: 723625

SINGAPORE
SGS Semiconductor (Pte) Ltd.
Singapore 2056
28 Ang Mo Kio
Industrial Park 2
Tel.: 482··1411
Telex: RS 55201 ESGIES

U,S,A,
SGS-Semiconductor Corporation
Phoenix, AZ 85022
1000 East Bell Road
Tel.: (602) 867-6100
Telex: 249976 SGSPH DR

SPAIN
SGS Microelettronica SpA
28036 Madrid
Representative Office
Calle Agustin De FoxB., 25
Tel.: 01 - 7337043
Telex: 41414
SWEDEN
SGS Semiconductor A.B.
19500 Miirsta
Bristagatan, 16
Tel.: 0760 - 40120
Telex: 054 - 10932
SWITZERLAND
SGS Semiconductor S.A.
Sales Offices:
1218 Grand·Saconnex (Geneve)
Chemin Franc;ois-Lehmann, ISlA
Tel.: 022 - 986462/3
Telex: 28895
TAIWAN-REPUBLIC OF CHINA
SGS Semiconductor Asia Ltd
Taipei Sec 4
6th floor, Pacific Commercial Bldg.
285 Chung Hsiao E Road
Tel.: 2-7728203
Telex: 10310 ESGIETWN
UNITED KINGDOM
SGS Semiconductor Limited
Aylesbury, Bucks
Planar House, Walton Street
Tel.: 0296 - 5977
Telex: 051 - 83245
WEST GERMANY
SGS Halbleiter Bauelemente GmbH
8018 Grafing bei Munchen
Haidling, 17
Tel.: 08092-690
Telex: 05 27378
Sales Offices:

3012 Langenhagen
Hans Boeckler Str., 2
Tel.: 0511 - 789881
Telex: 923195
8500 Nurnberg 40
Allersberger Str., 95
eingang Wilhelminenstr.
Tel.: 0911 - 464071
Telex: 626243

Sales Offices:
Bloomington, MN 55420
One Appletree Square

Suite 201-K
Tel.: (612) 854-0525
Ft, Lauderdale FL 33309
100 I NW 62nd Street
Suite 314
Tel.: (305) 4938881
Telex: 291588
Hauppauge, NY 11788
330 Motor Parkway
Suite 100
Tel.: (516) 435-1050
Telex: 221275 SGSHA DR
Indianapolis, IN 46268
8777 Purdue Road
Suite 113
Tel.: (317) 872-4404
Telex: 209144 SGSIN DR
Irvine, CA 92714
18271 W. McDurmott Drive
Suite J.
Tel. (714) 863-1222
Telex: 277793 SGSOR DR
Plano, TX 75074
850 East Central Parkway
Suite 180
Tel.: (214) 881-0848
Telex: 203997 SGSDA DR
Poughkeepsie, NY 12601
201 South Avenue
Suite 206
Tel.: (914) 473-2255
Santa Clara, CA 95051
2700 Augustine Drive
Suite 209
TeL (408) 727-3404
Telex: 278833 SGSSA DR
Schaumburg, IL 60196
600 North Meacham Road
Tel.: (312) 490-1890
Telex: 210159 SGSCH DR
Southfield, MI 48076
21411 Civic Center Dr. 309
Mark Plaza Bldg.
Tel.: (313) 358-4250
Telex: 810-224-4684 "MGA DET SOFD"
Waltham, MA 02154
240 Bear Hill Road
Tel.: (617) 890-6688
Telex: 200297 SGSWH DR
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