ZFx86 Data Book System On A Chip

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ZFx86™
System-on-a-Chip
Data Book
Version 1.0 Rev D
June 5, 2006

ZFx86 Data Book 1.0 Rev D

Page 1

Legal Notice

THIS DOCUMENT AND THE INFORMATION CONTAINED THEREIN IS PROVIDED “AS-IS”
AND WITHOUT A WARRANTY OF ANY KIND. YOU, THE USER, ACCEPT FULL RESPONSIBILITY FOR PROPER USE OF THE MATERIAL. ZF MICRO SOLUTIONS, INC. MAKES NO
REPRESENTATIONS OR WARRANTIES THAT THIS DATA BOOK OR THE INFORMATION
CONTAINED THERE-IN IS ERROR FREE OR THAT THE USE THEREOF WILL NOT
INFRINGE ANY PATENTS, COPYRIGHT OR TRADEMARKS OF THIRD PARTIES. ZF MICRO
SOLUTIONS, INC. EXPLICITLY ASSUMES NO LIABILITY FOR ANY DAMAGES WHATSOEVER RELATING TO ITS USE.
LIFE SUPPORT and HIGH RISK APPLICATION POLICY
Customers of ZF Micro Solutions products will not knowingly integrate, promote, sell, or otherwise transfer any ZF Product to any customer or end user for use in any high risk applications,
LIFE SUPPORT DEVICES or Life support SYSTEMS.
ZF MICRO SOLUTIONS' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN HIGH RISK APPLICATIONS or LIFE SUPPORT DEVICES or LIFE SUPPORT
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZF MICRO SOLUTIONS, INC. and ZF Micro Solutions does not indemnify
for any such uses.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical
implant into the body, or (b) support or sustain life, and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to
affect its safety or effectiveness.
3. A high risk application is any use in any applications where it is reasonably foreseeable that
failure of the product as used in such application(s) would lead to death, bodily injury, or catastrophic property damage. Examples of such applications specifically include, without limitation,
certain uses in nuclear facilities, air traffic control systems, and aeronautical aircraft control applications.

ZFx86 Data Book 1.0 Rev D

Page 2

Legal Notice

© 2001 ZF Micro Devices, Inc. All rights reserved.
© 2006 ZF Micro Solutions, Inc. All rights reserved.
ZFx86, FailSafe FailSafe Boot ROM, Z-tag ZF-Logic, InternetSafe, OEMmodule SCC, ZF
SystemCard, ZF FlashDisk-SC, netDisplay, ZF 104Card, ZF SlotCard, and ZF Micro Solutions
logo are trademarks of ZF Micro Solutions, Inc. Other brands and product names are trademarks
of their respective owners.
All trademarks and copyrights of ZF MicroSystems, ZF Embedded, ZF Linux Devices and ZF
Micro Devices are the property of ZF Micro Solutions.

ZFx86 Data Book 1.0 Rev D

Page 3

ZFx86 Specification Changes

ZFx86 Specification Changes
This application note describes the differences in specifications between the
ZFx86BGA388 devices produced for ZF Micro Solutions by National Semiconductor and
the new devices available as of June 1, 2006 produced for ZF Micro Solutions by IBM
Microelectronics.
DEVICE MARKING
NSC produced devices had the following foundry code: 3100-0200-01 B1 or 3100-020001 A5
IBM produced devices have the following foundry code: 3100-0200-03 C0
CPU PERFORMANCE
Initial units of the IBM produced devices will be available at 100 MHz CPU clock speeds.
(NSC produced versions were: Industrial temp 100MHz; Commercial temp 128MHz)
VOLTAGE
NOTE: IF YOU WILL BE TESTING THE NEW ZFx86 ON AN EXISTING DESIGN THE
CORE VOLTAGE MUST BE CHANGED TO THE SETTING BELOW!
The Vdd-Core voltage specification is expected to be:
Minimum 2.09V
Nominal 2.20V
Maximum 2.31V
(NSC produced versions were also dual voltage devices: 5V tolerant, 3.3V I/O, 2.5V core
voltage at 100MHz and 2.7V core voltage at 128MHz)

MECHANICAL / ENVIRONMENTAL
Commercial Temperature - Up to 100MHz (0C to +70C ambient temperature)
Industrial Temperature - Up to 100MHz (-40C to +85C case temperature)
Package: 388-pin Plastic Ball Grid Array, 35mm x 35mm, fully RoHS compliant
(NSC produced versions were non RoHS compliant)

ZFx86 Data Book 1.0 Rev D

Page 4

ZFx86 Specification Changes

NOTE: After full characterization of the devices from the IBM foundry has been
completed ZF will issue an update regarding final temperature ratings.
SOFTWARE
An updated version of the ZTAG .bin file for loading the Phoenix BIOS is required
however there is no change to the BIOS, just this particular loader module.
Please contact support@zfmicro.com with “NEW Z-TAG” in the subject line and you
will be sent the new file.
Note: When you flash the BIOS using the dongle there are two software components
inside of the dongle; the loader program and the BIOS image. You will now use a new
version of the loader program but the same BIOS image.)

ZFx86 Data Book 1.0 Rev D

Page 5

Revision History

Revision History
This section contains the revision history of this manual, starting with ZFx86 Data Book 1.0
Revision D. The change from revision C to revision D occurred when ZF Micro Solutions
resumed production of the ZFx86 using a new foundry in 2006. Designers who used ZFx86 chips
in pre-2006 products will want to review the specification changes listed herein.

Volume I Revision D June 5th, 2006
Most references to ZF Micro Devices are changed to ZF Micro Systems (except in copyright of
source code listings).
The specification for Vdd-Core has been changed to new voltages in Table 7.2, ‘Recommended
Operating Conditions, ’ on page 482
A note listing important changes between the NSC (previous) and IBM (current) produced chips
appears on "ZFx86 Specification Changes" on page 4

ZFx86 Data Book 1.0 Rev D

Page 6

Table of Contents
Table of Contents
ZFx86 Specification Changes .............................................................................................. 4
Revision History ..................................................................................................................... 6
Volume I Revision D June 5th, 2006 ................................................................................... 6

Table of Contents.......................................................................................................... 7
List of Figures ............................................................................................................. 13
List of Tables............................................................................................................... 17
1. Overview ................................................................................................................... 29
2. 32-bit x86 Processor................................................................................................ 31
2.1. Overview ...................................................................................................................... 31
2.1.1. Internal Clock Logic ............................................................................................ 32
2.1.2. On-Chip Write-Back Cache ................................................................................ 32
2.1.3. System Management Mode................................................................................ 33
2.1.4. Power Management............................................................................................ 33
2.1.5. Signal Summary ................................................................................................. 33
2.2. Programming Interface ................................................................................................ 33
2.2.1. Processor Initialization........................................................................................ 34
2.2.2. Instruction Set Overview..................................................................................... 35
2.2.3. Register Set ........................................................................................................ 36
2.2.4. Address Spaces.................................................................................................. 60
2.2.5. Interrupts and Exceptions ................................................................................... 66
2.2.6. System Management Mode................................................................................ 71
2.2.7. Shutdown and Halt ............................................................................................. 80
2.2.8. Protection............................................................................................................ 80
2.2.9. Virtual 8086 Mode............................................................................................... 82
2.2.10. FPU Operations ................................................................................................ 83
2.3. Instruction Set.............................................................................................................. 86
2.3.1. General Instruction Fields................................................................................... 87
2.3.2. Instruction Set Tables ......................................................................................... 93

3. North Bridge ........................................................................................................... 113
3.1. North Bridge Features ............................................................................................... 113
3.2. Interface Signals ........................................................................................................ 116
3.3. Functional Description ............................................................................................... 118
3.3.1. Processor Interface........................................................................................... 118
3.3.2. DRAM Controller............................................................................................... 122
3.3.3. Configuration and Testability ............................................................................ 126
3.3.4. PCI bus interface and arbiter ............................................................................ 127
3.3.5. PCI Write Buffer and Bursts.............................................................................. 129
3.3.6. Write buffer architecture ................................................................................... 134
3.3.7. System Management Mode.............................................................................. 134
3.3.8. Power Management.......................................................................................... 136
3.4. Register Set ............................................................................................................... 136

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Table of Contents
3.4.1. Register Address Map ...................................................................................... 137
3.4.2. DRAM registers ................................................................................................ 149
3.4.3. Power Management registers........................................................................... 160
3.4.4. Test Signals ...................................................................................................... 162
3.4.5. PCI configuration registers ............................................................................... 162

4. South Bridge .......................................................................................................... 165
4.1. South Bridge Module ................................................................................................. 165
4.1.1. South Bridge Features...................................................................................... 165
4.2. Architecture................................................................................................................ 166
4.2.1. Front-side PCI / Back-Side PCI Bus ................................................................. 167
4.2.2. IDE Controller ................................................................................................... 168
4.2.3. Universal Serial Bus ......................................................................................... 168
4.2.4. Integrated SuperI/O .......................................................................................... 169
4.2.5. ISA Bus Interface.............................................................................................. 169
4.2.6. Power Management.......................................................................................... 170
4.2.7. GPIO Interface.................................................................................................. 171
4.2.8. ZF-Logic............................................................................................................ 171
4.3. Signal Descriptions .................................................................................................... 172
4.3.1. System Interface Signals .................................................................................. 173
4.3.2. Back-Side PCI Interface Signals....................................................................... 175
4.3.3. Integrated SuperI/O Interface Signals .............................................................. 188
4.4. Register Descriptions................................................................................................. 195
4.4.1. PCI Configuration Space and Access Methods................................................ 196
4.4.2. Register Summaries ......................................................................................... 197
4.4.3. Chipset Register Space .................................................................................... 206
4.4.4. USB Controller Registers - PCIUSB ................................................................. 246
4.4.5. ISA Legacy Register Space.............................................................................. 248
4.5. SuperI/O - A PC98 Compliant Cell ............................................................................ 258
4.5.1. Outstanding Features ....................................................................................... 258
4.5.2. Features............................................................................................................ 259
4.5.3. SIGNAL/PIN Descriptions................................................................................. 261
4.5.4. Device Architecture and Configuration ............................................................. 261
4.5.5. Standard Logical Device Configuration Register Definitions ............................ 265
4.5.6. Standard Configuration Registers..................................................................... 267
4.6. SuperI/O Configuration Registers .............................................................................. 269
4.6.1. Register Type Abbreviations ............................................................................ 269
4.7. Floppy Disk Controller (FDC) Configuration .............................................................. 272
4.8. Parallel Port Configuration ......................................................................................... 274
4.8.1. Logical Device 1 (PP) Configuration................................................................. 274
4.9. System Wake-Up Control (SWC) .............................................................................. 276
4.9.1. Overview........................................................................................................... 276
4.9.2. Functional Description ...................................................................................... 276
4.9.3. Event Detection ................................................................................................ 277

ZFx86 Data Book 1.0 Rev D

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Table of Contents
4.9.4. SWC Register Bitmap....................................................................................... 291
4.9.5. Keyboard/Mouse Control .................................................................................. 294
4.9.6. Infrared Communication Port Configuration ..................................................... 297
4.10. ACCESS.Bus Interface (ACB) Configuration........................................................... 298
4.11. Real-time Clock (RTC)............................................................................................. 300
4.11.1. RTC Overview ................................................................................................ 302
4.11.2. Functional Description .................................................................................... 302
4.11.3. RTC Configuration Registers.......................................................................... 307
4.11.4. RTC Registers ................................................................................................ 309
4.11.5. RTC General-purpose RAM Map .................................................................. 321
4.12. ACCESS.bus Interface (ACB) ................................................................................. 322
4.12.1. Functional Description .................................................................................... 322
4.12.2. ACB Registers ................................................................................................ 329
4.13. Legacy Functional Blocks ........................................................................................ 335
4.13.1. Keyboard and Mouse Controller (KBC) .......................................................... 335
4.13.2. Floppy Disk Controller (FDC).......................................................................... 336
4.13.3. Parallel Port .................................................................................................... 337
4.13.4. UART Functionality (SP1/SP2)....................................................................... 340
4.13.5. IR Communication Port (IRCP) Functionality ................................................. 345

5. ZF-Logic and Clocking .......................................................................................... 403
5.1. Features..................................................................................................................... 403
5.2. ZFL Register Space Summary .................................................................................. 404
5.2.1. Pins Associated with ZF-Logic.......................................................................... 408
5.3. ISA Memory Mapper for Flash/SRAM ....................................................................... 410
5.3.1. Window settings registers................................................................................ 415
5.3.2. Control (R/W, 8/16)........................................................................................... 418
5.3.3. Events (SMI, etc.) ............................................................................................. 418
5.3.4. Initialization of mem_cs0 .................................................................................. 418
5.3.5. Sample Code for Memory Window Calculation ................................................ 421
5.4. GPCS I/O mapper...................................................................................................... 422
5.4.1. GPCS control.................................................................................................... 424
5.4.2. GPCS base low byte......................................................................................... 424
5.4.3. GPCS base high byte ....................................................................................... 424
5.4.4. GPCS Events................................................................................................... 424
5.5. Watchdog Timer ........................................................................................................ 424
5.5.1. Watchdog Registers ......................................................................................... 426
5.6. PWM generator.......................................................................................................... 430
5.7. Z-tag Overview .......................................................................................................... 434
5.8. Boot Parameters Register ......................................................................................... 437
5.8.1. Special Notes of Interest................................................................................... 440
5.8.2. Design Example................................................................................................ 441
5.8.3. Clocking and Control Overview ........................................................................ 443
5.9. Data registers (F0H to FEH) ...................................................................................... 444

ZFx86 Data Book 1.0 Rev D

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Table of Contents
5.10. BUR Base Register.................................................................................................. 445
5.11. System Clocking ...................................................................................................... 447
5.11.1. mhz_14c [AF16].............................................................................................. 448
5.11.2. 32KHZC_C [AF01].......................................................................................... 449
5.11.3. SYSCLK_C [A20]............................................................................................ 450
5.11.4. USB_48MHz_C [AE15]................................................................................... 453
5.11.5. PCI Clocking ................................................................................................... 454

6. Z-tag, BUR, and The ZFiX Console....................................................................... 455
6.1. Serial Port Connection ............................................................................................... 455
6.2. Z-Tag Dongles ........................................................................................................... 455
6.2.1. PassThrough Dongle ........................................................................................ 455
6.2.2. Memory Dongle ................................................................................................ 455
6.2.3. Using the Dongle .............................................................................................. 456
6.3. Z-tag Manager Software ............................................................................................ 459
6.3.1. Z-tag Summary ................................................................................................. 459
6.3.2. Z-tag Data Transfer Protocol ............................................................................ 460
6.3.3. Z-tag Port Interface........................................................................................... 461
6.4. Z-tag Register Descriptions ....................................................................................... 461
6.4.1. Z-tag Data (D1h)............................................................................................... 461
6.4.2. Z-tag Control (7Ch).......................................................................................... 461
6.5. BUR (Boot Up ROM) ................................................................................................. 462
6.5.1. ZFiX Console Functions ................................................................................... 463
6.5.2. Z-tag Functionality ............................................................................................ 464
6.5.3. Internal Functionality......................................................................................... 465
6.6. BUR COM1 Download Examples .............................................................................. 466
6.6.1. Procomm: Download a Test Program............................................................... 466
6.6.2. HyperTerminal: Download a Test Program ...................................................... 468
6.6.3. BUR Version Test Program Source Code ........................................................ 469
6.6.4. BUR/BET Memory Map ................................................................................... 470
6.7. Flash Programming Example .................................................................................... 470

7. Electrical Specifications........................................................................................ 481
7.1. General Specifications ............................................................................................... 481
7.1.1. MTTF and FIT Specifications............................................................................ 481
7.1.2. Power/Ground Connections and Decoupling.................................................... 481
7.2. Signal I/O Buffer Type Directory .......................................................................... 483
7.3. Detailed DC Characteristics of Cells.......................................................................... 484
7.4. AC Characteristics ..................................................................................................... 489
7.4.1. System Interface............................................................................................... 489
7.4.2. Memory Interface.............................................................................................. 492
7.4.3. ACCESS.bus Interface ..................................................................................... 494
7.4.4. PCI Bus............................................................................................................. 495
7.4.5. ISA Interface ..................................................................................................... 501
7.4.6. IDE Interface Timing ......................................................................................... 504

ZFx86 Data Book 1.0 Rev D

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Table of Contents
7.4.7. Universal Serial Bus (USB) .............................................................................. 523
7.4.8. Serial Port (UART)............................................................................................ 527
7.4.9. Fast IR Port Timing........................................................................................... 528
7.4.10. JTAG Timing ................................................................................................ 529
7.4.11. GPIO Timing ................................................................................................... 530
7.4.12. Floppy Disk Interface ...................................................................................... 531
7.4.13. Keyboard and Mouse Interface....................................................................... 533
7.4.14. Parallel Port .................................................................................................... 534
7.4.15. ZF-Logic.......................................................................................................... 540

8. Pinout Summary .................................................................................................... 541
8.1. Pad Assignments .......................................................................................................
8.2. Pin Descriptions (Sorted by Pin) ................................................................................
8.3. Pin Descriptions (Sorted by Pin Name) .....................................................................
8.4. Pin Descriptions (Sorted by Pin Description) .............................................................

541
545
558
572

9. BUR API .................................................................................................................. 587
9.1. Using the BUR API .................................................................................................... 587
9.2. Function Call Definitions ............................................................................................ 587

10. Signal Status After POST .................................................................................... 597
10.1. Access Bus .............................................................................................................. 597
10.2. Floppy Disk .............................................................................................................. 597
10.2.1. FDD Active ..................................................................................................... 597
10.2.2. Z-tag Active .................................................................................................... 598
10.3. GPIO ........................................................................................................................ 599
10.4. ISA ........................................................................................................................... 599
10.5. PS/2 ......................................................................................................................... 599
10.6. PCI........................................................................................................................... 600
10.7. LPT .......................................................................................................................... 600
10.8. IR Control (COM2) ................................................................................................... 601
10.9. ZF Logic ................................................................................................................... 601

11. Phoenix BIOS Register Settings......................................................................... 603
11.1. North Bridge............................................................................................................ 603
11.1.1. Reset, Sampling, and Misc North Bridge Registers........................................ 603
11.1.2. DRAM Registers ............................................................................................. 615
11.1.3. Power Management Registers ....................................................................... 623
11.1.4. PCI Configuration Registers ........................................................................... 624
11.2. South Bridge ............................................................................................................ 626
11.2.1. Floppy Disk Controller .................................................................................... 626
11.2.2. Parallel Port .................................................................................................... 629
11.2.3. Serial Port 1 .................................................................................................... 630
11.2.4. Serial Port 2 .................................................................................................... 632
11.2.5. PS/2 Mouse/Keyboard.................................................................................... 633
11.2.6. Infrared Communication Port Configuration ................................................... 635

ZFx86 Data Book 1.0 Rev D

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Table of Contents
11.2.7. Access Bus ..................................................................................................... 636
11.2.8. Pin Multiplexor Registers ................................................................................ 637
11.2.9. GPIO Configuration Pins ................................................................................ 640

Index........................................................................................................................... 653

ZFx86 Data Book 1.0 Rev D

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List of Figures
List of Figures
Table of Contents ......................................................................................................... 7
List of Figures ............................................................................................................ 13
List of Tables .............................................................................................................. 17
1. Overview .................................................................................................................. 29
Figure 1-1

ZFx86 Fail-Safe PC-on-a-Chip Block Diagram ............................................. 30

2. 32-bit x86 Processor ............................................................................................... 31
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 2-17
Figure 2-18
Figure 2-19

Processor Block Diagram ............................................................................. 31
Task Register ............................................................................................... 46
Processor Internal I/O Interface Signals ....................................................... 53
Processor Cache Architecture ...................................................................... 58
Memory and I/O Address Spaces ................................................................ 61
Offset Address Calculation ........................................................................... 61
Real Mode Address Calculation ................................................................... 63
Protected Mode Address Calculation ........................................................... 63
Selector Mechanism ..................................................................................... 64
Paging Mechanism ....................................................................................... 65
Error Code Format ....................................................................................... 70
System Management Memory Address Space ............................................ 72
SMI Execution Flow Diagram ....................................................................... 73
SMM Memory Space Header ....................................................................... 74
SMM and Suspend Mode State Diagram ..................................................... 78
Tag Word Register ....................................................................................... 84
FPU Status Register ..................................................................................... 84
FPU Mode Control Register ......................................................................... 84
Instruction Set Format .................................................................................. 86

3. North Bridge .......................................................................................................... 113
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10

Data Paths .................................................................................................. 114
Block Diagram ............................................................................................ 115
CPU Address Translation and Decode ...................................................... 122
32-Bit Banks Connection ............................................................................ 124
16-Bit Bank Connections ............................................................................ 124
PCI Bus Arbiter Block Diagram .................................................................. 128
PCI Bank Arbiter State Diagram ................................................................. 129
Translation of Type 0 Configuration Cycle ................................................. 132
Translation of Type 1 Configuration Cycle ................................................. 132
SMM RAM Location ................................................................................... 135

4. South Bridge ......................................................................................................... 165
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4

Internal Block Diagram ............................................................................... 167
IDE Channel Connections .......................................................................... 168
South Bridge Block Diagram ...................................................................... 172
Super I/O Block Diagram ............................................................................ 259

ZFx86 Data Book 1.0 Rev D

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List of Figures
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 4-17
Figure 4-18
Figure 4-19

Detailed SuperI/O Block Diagram .............................................................. 262
Structure of the Standard Configuration Register File ................................ 264
Configuration Register Map ........................................................................ 267
Keyboard and Mouse Interfaces ................................................................ 295
Divider Chain Control ................................................................................. 303
Interrupt/Status Timing ............................................................................... 306
Bit Transfer ................................................................................................. 323
Start and Stop Conditions .......................................................................... 323
ACCESS.bus Data Transaction ................................................................. 323
ACCESS.bus Acknowledge Cycle ............................................................. 324
A Complete ACCESS.bus Data Transaction .............................................. 325
UART Mode Register Bank Architecture .................................................... 341
Composite Serial Data ............................................................................... 346
IRCP Register Bank Architecture ............................................................... 355
DMA Control Signals Routing ..................................................................... 377

5. ZF-Logic and Clocking ......................................................................................... 403
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
Figure 5-14

ZF-Logic Features ...................................................................................... 404
Memory Window Mapping .......................................................................... 415
Fields in 32-bit memory settings register .................................................... 416
Watchdog Block Diagram ........................................................................... 425
PWM Control Unit ....................................................................................... 430
PWM Period and Duty Cycle ...................................................................... 431
Dongle (w/o Cover) .................................................................................... 434
Sample DIP Switch Schematic ................................................................... 442
System Clocking and Control ..................................................................... 443
mhz_14c[AF16] Clocking Control Circuitry ................................................. 449
32KHZC_C [AF01] Clocking Control Circuitry ............................................ 450
SYSCLK_C [A20] Clocking Control Circuitry .............................................. 452
USB_48MHz_C [AE15] Clocking Control Circuitry ..................................... 453
PCI Clocking Control Circuitry .................................................................... 454

6. Z-tag, BUR, and The ZFiX Console ...................................................................... 455
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5

Data Transfer Protocol ............................................................................... 460
Data Input ................................................................................................... 460
Dongle Data Record ................................................................................... 465
Using Procomm YMODEM Batch .............................................................. 467
Using HyperTerminal - Send File Ymodem ................................................ 468

7. Electrical Specifications ....................................................................................... 481
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7

Differential Input Sensitivity for Common Mode Range .............................. 486
sysclk_c Timing and Measurement Points ................................................. 490
reset_n timing ............................................................................................. 490
res_out timing ............................................................................................. 491
CPU_trig timing .......................................................................................... 491
Drive Level and Measurement Points for Switching Characters ................ 492
Output Valid Timing .................................................................................... 493

ZFx86 Data Book 1.0 Rev D

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List of Figures
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25
Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30
Figure 7-31
Figure 7-32
Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
Figure 7-39
Figure 7-40
Figure 7-41
Figure 7-42
Figure 7-43
Figure 7-44
Figure 7-45
Figure 7-46
Figure 7-47
Figure 7-48
Figure 7-49
Figure 7-50
Figure 7-51
Figure 7-52
Figure 7-53

Setup and Hold Timing - Read Data In ...................................................... 494
ACB Signals (SDAT AND SCLK) Rising and Falling times ........................ 494
Testing Setup for Slew Rate and Minimum Timing .................................... 496
V/I Curves for PCI Output Signals .............................................................. 496
PCICLK Timing and Measurement Points .................................................. 497
Load Circuits for Maximum Time Measurements ....................................... 498
Output Timing Measurement Conditions .................................................... 499
Input Timing Measurement Conditions ....................................................... 500
Reset Timing .............................................................................................. 500
ISA Read Operation ................................................................................... 503
ISA Write Operation ................................................................................... 503
IDE Reset Timing ....................................................................................... 504
IDE Register Transfer To/From Device ...................................................... 506
IDE PIO Data Transfer To/From Device ..................................................... 508
Multiword Data Transfer ............................................................................. 510
Initiating an Ultra DMA Data in Burst .......................................................... 513
Sustained Ultra DMA Data In Burst ............................................................ 514
Host Pausing an Ultra DMA Data In Burst ................................................. 515
Device Terminating an Ultra DMA Data In Burst ........................................ 516
Host Terminating an Ultra DMA Data In Burst ........................................... 517
Initiating an Ultra DMA Data Out Burst ....................................................... 518
Sustained Ultra DMA Data Out Burst ......................................................... 519
Device Pausing an Ultra DMA Data Out Burst ........................................... 520
Host Terminating an Ultra DMA Data Out Burst ......................................... 521
Device Terminating an Ultra DMA Data Out Burst ..................................... 522
Data Signal Rise and Fall Time .................................................................. 525
Source Differential Data Jitter .................................................................... 525
EOP Width Timing ...................................................................................... 526
Receiver Jitter Tolerance ........................................................................... 526
UART, Sharp-IR, SIR, and Consumer Remote Control Timing .................. 527
Fast IR Timing (MIR and FIR) .................................................................... 528
TCK Timing and Measurement Points ....................................................... 529
GPIO Output Timing Measurement Conditions .......................................... 530
GPIO Input Timing Measurement Conditions ............................................. 530
Floppy Disk Reset Timing .......................................................................... 531
Write Data Timing ....................................................................................... 532
Drive Control Timing ................................................................................... 532
Read Data Timing ...................................................................................... 533
KBC Signals Rising and Falling .................................................................. 533
Parallel Port Interrupt Timing (Compatible Mode) ...................................... 534
Parallel Port Interrupt Timing (Extended Mode) ......................................... 534
Typical Parallel Port Data Exchange .......................................................... 535
Enhanced Parallel Port 1.7 Timing ............................................................. 536
Enhanced Parallel Port 1.9 Timing ............................................................. 537
ECP Parallel Port Forward Timing Diagram ............................................... 538
ECP Parallel Port Backward Timing Diagram ............................................ 539

ZFx86 Data Book 1.0 Rev D

Page 15

List of Figures
Figure 7-54
Figure 7-55

ZF-Logic Output Timing Measurement Conditions ..................................... 540
ZF-Logic Input Timing Measurement Conditions ....................................... 540

8. Pinout Summary ................................................................................................... 541
Figure 8-1
Figure 8-2
Figure 8-1

ZFx86 Package - Solder Balls .................................................................... 542
388 BGA Internal ........................................................................................ 543
ZFx86 Orientation ....................................................................................... 544

9. BUR API ................................................................................................................. 587
10. Signal Status After POST ................................................................................... 597
11. Phoenix BIOS Register Settings ........................................................................ 603
Index .......................................................................................................................... 653

ZFx86 Data Book 1.0 Rev D

Page 16

List of Tables
List of Tables
Table of Contents ......................................................................................................... 7
List of Figures ............................................................................................................ 13
List of Tables .............................................................................................................. 17
1. Overview .................................................................................................................. 29
2. 32-bit x86 Processor ............................................................................................... 31
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Table 2.14
Table 2.15
Table 2.16
Table 2.17
Table 2.18
Table 2.19
Table 2.20
Table 2.21
Table 2.22
Table 2.23
Table 2.24
Table 2.25
Table 2.26
Table 2.27
Table 2.28
Table 2.29
Table 2.30
Table 2.31
Table 2.32
Table 2.33
Table 2.34
Table 2.35
Table 2.36
Table 2.37
Table 2.38
Table 2.39

Initialized Register Controls........................................................................... 34
Application Register Set ................................................................................ 37
Segment Register Selection Rules................................................................ 39
EFLAGS Register .......................................................................................... 40
System Register Set...................................................................................... 41
Control Registers Map................................................................................... 42
CR3, CR2, and CR0 Bit Definitions ............................................................... 42
Effects of Various Combinations of TS, EM and MP Bits .............................. 43
Application and System Segment Descriptors .............................................. 45
Gate Descriptors ........................................................................................... 45
Gate Descriptor Bit Definitions ..................................................................... 46
32-Bit Task State Segment (TSS) Table ....................................................... 46
16-Bit Task State Segment (TSS) Table ....................................................... 47
Configuration Register Map........................................................................... 48
CCR1 Bit Definitions...................................................................................... 49
CCR2 Bit Definitions...................................................................................... 51
CCR3 Bit Definitions...................................................................................... 51
SMAR Size Field ........................................................................................... 52
DIR0 Bit Definitions ....................................................................................... 52
DIR1 Bit Definitions ....................................................................................... 52
Debug Registers............................................................................................ 54
DR6 and DR7 Field Definitions ..................................................................... 55
Test Registers ............................................................................................... 56
TR7 and TR6 Bit Definitions .......................................................................... 56
TR6 Attribute Bit Pairs ................................................................................... 57
TR3-TR5 Bit Definitions................................................................................. 59
Memory Addressing Modes........................................................................... 62
Directory and Page Table Entry (DTE and PTE) Bit Definitions.................... 66
Interrupt Vector Assignments ........................................................................ 68
Interrupt and Exception Priorities .................................................................. 69
Exception Changes in Real Mode ................................................................. 70
Error Code Bit Definitions .............................................................................. 71
Requirement for Recognizing SMI# and SMINT ........................................... 72
SMM Memory Space Header ........................................................................ 75
SMM Instruction Set ...................................................................................... 76
SMM Pin Definitions ...................................................................................... 79
Descriptor Types Used for Control Transfer.................................................. 82
Status Control Register Bit Definitions .......................................................... 84
Mode Control Register Bit Definition ............................................................. 85

ZFx86 Data Book 1.0 Rev D

Page 17

List of Tables
Table 2.40
Table 2.41
Table 2.42
Table 2.43
Table 2.44
Table 2.45
Table 2.46
Table 2.47
Table 2.48
Table 2.49
Table 2.50
Table 2.51
Table 2.52
Table 2.53
Table 2.54
Table 2.55
Table 2.56
Table 2.57
Table 2.58

Instruction Fields ........................................................................................... 87
Instruction Prefix Summary ........................................................................... 87
w Field Encoding ........................................................................................... 88
d Field Encoding............................................................................................ 88
eee Field Encoding........................................................................................ 88
mod r/m Field Encoding ................................................................................ 89
mod r/m Field Encoding Dependent on w Field ............................................ 90
reg Field ........................................................................................................ 90
sreg3 Field Encoding..................................................................................... 90
sreg2 Field Encoding..................................................................................... 91
ss Field Encoding .......................................................................................... 91
index Field Encoding ..................................................................................... 91
mod base Field Encoding .............................................................................. 91
CPU Clock Count Abbreviations ................................................................... 93
Flag Abbreviations......................................................................................... 94
Action of Instruction on Flag .......................................................................... 94
Processor Core Instruction Set Summary ..................................................... 94
FPU Table Abbreviations ............................................................................ 107
MMX Instruction Set Summary.................................................................... 108

3. North Bridge .......................................................................................................... 113
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 3.13
Table 3.14
Table 3.15
Table 3.16
Table 3.17
Table 3.18
Table 3.19
Table 3.20
Table 3.21
Table 3.22
Table 3.23
Table 3.24
Table 3.25
Table 3.26

SDRAM Interface Signals............................................................................ 116
PCI Sideband Signals ................................................................................ 118
Test Signals (JTAG) .................................................................................... 118
Memory Access Map ................................................................................... 119
I/O Address Map ......................................................................................... 119
North Bridge Core Burst Sequence ............................................................. 120
SDRAM Configurations ............................................................................... 123
ROM Shadow Illustration............................................................................. 126
North Bridge Registers ................................................................................ 126
CPU-PCI Cycle Conversion ........................................................................ 133
Configuration Registers ............................................................................. 137
SMM Control Register (SMMC) ................................................................. 140
Processor Control Register (PROC) .......................................................... 142
Write FIFO Control Register (WFIFOC) .................................................... 143
PCI Control Register (PCIC) ...................................................................... 145
Clock Skew Adjust Register (CSA) ............................................................ 146
BUS MASTER And Snooping Control Register (SNOOPCTRL)................. 146
Arbiter Control Register (ARBCTRL)........................................................... 148
PCI Write FIFO Control Register (PCIWFIFOC) ........................................ 148
Shadow RAM Read Enable Control Register (SHADRC) ......................... 149
Shadow RAM Write Enable Control Register ............................................. 150
Bank 0 Control Register (N_B0C) .............................................................. 151
Bank 0 Timing Control Register (N_B0TC) ............................................... 152
Bank 1 Control Register (N_B1C) ............................................................. 152
Bank 1 Timing Control Register (N_B1TC) ............................................... 153
Bank 2 Control Register (N_B2C) .............................................................. 153

ZFx86 Data Book 1.0 Rev D

Page 18

List of Tables
Table 3.27
Table 3.28
Table 3.29
Table 3.30
Table 3.31
Table 3.32
Table 3.33
Table 3.34
Table 3.35
Table 3.36
Table 3.37
Table 3.38
Table 3.39
Table 3.40
Table 3.41
Table 3.42
Table 3.43
Table 3.44

Bank 2 Timing Control Register (N_B2TC) ............................................... 154
Bank 3 Control Register (N_B3C) .............................................................. 155
Bank 3 Timing Control Register (N_B3TC) ............................................... 155
DRAM Configuration Register 1 (DCONF1) .............................................. 156
DRAM Configuration Register 2 (DCONF2) ............................................... 157
DRAM Refresh Control Register (DRFSHC) .............................................. 158
SDRAM Mode Program Register (SDRAMMPR) ....................................... 158
SDRAM Mode Program Register (SDRAMMPREX) .................................. 159
SDRAM Slew Control Register (SDRAMSLEW) ...................................... 159
Clock Control Register (CC) ....................................................................... 160
Clock Control2 Register (CC2) ................................................................... 161
CPU-SYNC Register (CPUSYNC) ............................................................. 162
Vendor ID Register (VID) ........................................................................... 162
Device ID Register (DID) ............................................................................ 162
Command Register (COMMD) ................................................................... 162
Status Register (STAT) .............................................................................. 163
Revision ID Register (RID) ......................................................................... 163
Class Register (CLASS) ............................................................................. 163

4. South Bridge ......................................................................................................... 165
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Table 4.6
Table 4.7
Table 4.8
Table 4.9
Table 4.10
Table 4.11
Table 4.12
Table 4.13
Table 4.14
Table 4.15
Table 4.16
Table 4.17
Table 4.18
Table 4.19
Table 4.20
Table 4.21
Table 4.22
Table 4.23
Table 4.24
Table 4.25
Table 4.26
Table 4.27

Logical Devices ........................................................................................... 169
System Interface Signals............................................................................. 173
Clock and Crystal Interface Signals ............................................................ 173
CPU Interface Signals ............................................................................... 174
Back-Side PCI Bus Interface Signals .......................................................... 175
IDE Interface Signals................................................................................... 180
USB Interface Signals ................................................................................. 182
GPIO Interface Signals................................................................................ 182
Full ISA Interface......................................................................................... 183
Access Bus.................................................................................................. 189
Clock ........................................................................................................... 189
Floppy Disk Controller ................................................................................. 189
Keyboard and Mouse Controller (KBC) ....................................................... 190
Parallel Port ................................................................................................. 192
Power and Ground ...................................................................................... 193
Serial Port 1 and Serial Port 2 (Shared with I/R Port) ................................. 194
Infrared Communication Port (Shared W/COM2)........................................ 195
PCI Configuration Address Register (0CF8h) ............................................ 196
F0: PCI Header/Bridge and GPIO Configuration Register Summary ......... 197
F0BAR0: GPIO Support Registers Summary ............................................. 199
F1: PCI Header Registers for SMI Status Summary .................................. 200
F1BAR0: SMI Status Registers Summary................................................... 200
F2: PCI Header Registers for IDE Controller Support Summary ................ 201
IDE Controller Configuration Summary ....................................................... 202
F3: PCI Header Registers for XBus Expansion Summary ......................... 202
F3BAR0: XBus Expansion Registers Summary ......................................... 203
PCIUSB: USB Controller Register Summary ............................................ 203

ZFx86 Data Book 1.0 Rev D

Page 19

List of Tables
Table 4.28
Table 4.29
Table 4.30
Table 4.31
Table 4.32
Table 4.33
Table 4.34
Table 4.35
Table 4.36
Table 4.37
Table 4.38
Table 4.39
Table 4.40
Table 4.41
Table 4.42
Table 4.43
Table 4.44
Table 4.45
Table 4.46
Table 4.47
Table 4.48
Table 4.49
Table 4.50
Table 4.51
Table 4.52
Table 4.53
Table 4.54
Table 4.55
Table 4.56
Table 4.57
Table 4.58
Table 4.59
Table 4.60
Table 4.61
Table 4.62
Table 4.63
Table 4.64
Table 4.65
Table 4.66
Table 4.67
Table 4.68
Table 4.69
Table 4.70
Table 4.71
Table 4.72
Table 4.73
Table 4.74

ZF-Logic Register Summary ...................................................................... 204
Legacy I/O Register Summary .................................................................. 204
F0 Index xxh: PCI Header and Bridge Configuration Registers ................ 207
F0BAR0+I/O Offset xxh: GPIO Runtime and Configuration Registers ...... 230
F1 Index xxh: PCI Header Registers for SMI Status ................................... 232
F1BAR0+I/O Offset xxh: SMI Status Registers ........................................... 233
F2 Index xxh: PCI Header/Channels 0 & 1 Registers for
IDE Controller Config ................................................................................. 236
F2BAR4+I/O Offset xxh: IDE Controller Configuration Registers................ 239
F3 Index xxh: PCI Header Registers for XBus Expansion .......................... 241
F3BAR0+I/O Offset xxh: XBus Expansion Registers .................................. 244
PCIUSB: USB Controller Registers ............................................................. 246
DMA Channel Control Registers ................................................................. 248
DMA Page Registers .................................................................................. 252
Programmable Interval Timer Registers ..................................................... 253
Programmable Interrupt Controller Registers ............................................. 254
Keyboard Controller Registers .................................................................. 256
Real-Time Clock Registers.......................................................................... 257
Miscellaneous Registers ............................................................................ 257
ACCESS.bus Interface (ACB) ..................................................................... 261
SuperI/O Configuration Options .................................................................. 263
Logical Device Number (LDN) Assignments ............................................... 264
Standard Control Registers ......................................................................... 265
Logical Device Activate Register ................................................................. 265
I/O Space Configuration Registers .............................................................. 265
Interrupt Configuration Registers ................................................................ 266
DMA Configuration Registers ...................................................................... 266
Special Logical Device Configuration Registers.......................................... 266
Register Type Abbreviations ...................................................................... 269
SuperI/O Configuration Registers .............................................................. 269
SuperI/O ID Register (SID) - Index 20H ..................................................... 270
SuperI/O Configuration 1 Register (SIOCF1) - Index 21H ......................... 270
SuperI/O Configuration 2 Register (SIOCF2) - Index 22H ......................... 271
SuperI/O Revision ID Register (SRID) - Index 27H .................................... 271
FDC Registers ............................................................................................. 272
Logical Device 0 (FDC) Configuration ........................................................ 273
FDC Configuration Register - Index F0H ................................................... 273
Drive ID Register - Index F1H .................................................................... 274
Parallel Port Configuration Registers .......................................................... 275
Parallel Port Configuration Register - F0H .................................................. 275
Banks 0 and 1 - The Common Control and Status Register Map .............. 279
Bank 0 - PS/2 KBD/MOUSE Wake-Up Config/Control Register Map ........ 279
Bank 1 - CEIR Wake-Up Config/Control Register Map .............................. 279
Wake-Up Events Status Register (WKSR) - 00H ....................................... 280
Wake-Up Events Control Register (WKCR) - 01H ..................................... 281
Wake-Up Configuration Register (WKCFG) - 02H ..................................... 282
PS/2 Protocol Control Register (PS2CTL) (Bank 0 Offset 03H).................. 283
Keyboard Data Shift Register (KDSR) - Bank 0 Offset 06H ........................ 284

ZFx86 Data Book 1.0 Rev D

Page 20

List of Tables
Table 4.75
Table 4.76
Table 4.77
Table 4.78
Table 4.79
Table 4.80
Table 4.81
Table 4.82
Table 4.83
Table 4.84
Table 4.85
Table 4.86
Table 4.87
Table 4.88
Table 4.89
Table 4.90
Table 4.91
Table 4.92
Table 4.93
Table 4.94
Table 4.95
Table 4.96
Table 4.97
Table 4.98
Table 4.99
Table 4.100
Table 4.101
Table 4.102
Table 4.103
Table 4.104
Table 4.105
Table 4.106
Table 4.107
Table 4.108
Table 4.109
Table 4.110
Table 4.111
Table 4.112
Table 4.113
Table 4.114
Table 4.115
Table 4.116
Table 4.117
Table 4.118
Table 4.119
Table 4.120
Table 4.121

Mouse Data Shift Register (MDSR) 07H ..................................................... 284
PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) ..................... 285
CEIR Wake-Up Control Register (IRWCR) - Bank 1 Offset 3 .................... 285
CEIR Wake-Up Address Register (IRWAD) - Bank 1 Offset 05H .............. 286
CEIR Wake-Up Address Mask Register (IRWAM) - Bank 1 Offset 6 ......... 286
CEIR Address Shift Register (ADSR) - Bank 1 Offset 7 ............................. 286
CEIR Wake-Up Range 0 Registers - IRWTR0L– Bank 1 Offset 8 ............. 287
CEIR Wake-Up Range 0 Registers - IRWTR0H – Bank 1 Offset 9 ............ 287
CEIR Wake-Up Range 1 Registers - IRWTR1L – Bank 1 Offset 0AH ....... 287
CEIR Wake-Up Range 1 Registers - IRWTR1H – Bank 1 Offset 0BH ....... 288
CEIR Wake-Up Range 2 Registers - IRWTR2L – Bank 1 0CH) ................. 289
CEIR Wake-Up Range 2 Registers - IRWTR2H – Bank 1 0DH .................. 289
CEIR Wake-Up Range 3 Registers - IRWTR3L – Bank 1 OEH ................. 289
CEIR Wake-Up Range 3 Registers - IRWTR3H – Bank 1 OFH ................. 290
Time Range Limits for CEIR Protocols ....................................................... 290
Banks 0 and 1 - The Common Three-Register Map .................................. 291
Bank 0 - PS/2 Keyboard/Mouse Wake-Up Config/Ctrl Registers ............... 291
CEIR Wake-Up Configuration and Control Registers ................................. 291
Serial Ports 1 and 2 Configuration Registers .............................................. 292
Serial Ports 1 and 2 Configuration Register - F0H ...................................... 293
System Wake-Up Control (SWC) Configuration.......................................... 294
Mouse Configuration Registers ................................................................... 295
Keyboard Configuration Registers .............................................................. 296
iKBC Configuration Register - F0H ............................................................. 296
Infrared Communication Port Configuration Registers ................................ 297
Infrared Communication Port Configuration Register - F0H........................ 297
ACB Runtime Registers .............................................................................. 298
Access Bus Interface (ACB) Configuration ................................................. 299
ACB Configuration Register – F0H ............................................................. 299
Logical Device A (RTC) Configuration ........................................................ 300
RAM Lock Register (RLR) - F0H ................................................................. 300
Date Of Month Alarm Register Offset (DOMAO) – F1H .............................. 301
Month Alarm Register Offset (MAO) – F2H................................................. 301
Century Register Offset (CENO0) – F3H .................................................... 302
RTC Configuration Register Map ................................................................ 307
RAM Lock Register (RLR) ........................................................................... 307
Date Of Month Alarm Register Offset (DOMAO)......................................... 308
Month Alarm Register Offset (DOMAO) ...................................................... 308
Century Register Offset (CENO) ................................................................. 309
RTC Configuration Register Bitmap ............................................................ 309
RTC Register Map....................................................................................... 310
Seconds Register (SEC)) – Index 00H ....................................................... 310
Seconds Alarm Register (SECA)) – 01H..................................................... 311
Minutes Register (MIN)) – 02H ................................................................... 311
Minutes Alarm Register (MINA) – 03H ....................................................... 311
Hours Register (HOR) – 04H ..................................................................... 312
Hours Alarm Register (HORA) – 05H ......................................................... 312

ZFx86 Data Book 1.0 Rev D

Page 21

List of Tables
Table 4.122
Table 4.123
Table 4.124
Table 4.125
Table 4.126
Table 4.127
Table 4.128
Table 4.129
Table 4.130
Table 4.131
Table 4.132
Table 4.133
Table 4.134
Table 4.135
Table 4.136
Table 4.137
Table 4.138
Table 4.139
Table 4.140
Table 4.141
Table 4.142
Table 4.143
Table 4.144
Table 4.145
Table 4.146
Table 4.147
Table 4.148
Table 4.149
Table 4.150
Table 4.151
Table 4.152
Table 4.153
Table 4.154
Table 4.155
Table 4.156
Table 4.157
Table 4.158
Table 4.159
Table 4.160
Table 4.161
Table 4.162
Table 4.163
Table 4.164
Table 4.165
Table 4.166
Table 4.167
Table 4.168

Day Of Week Register (DOW) – 06H ......................................................... 312
Date Of Month Register (DOM) – 07H ....................................................... 313
Month Register (MON) - 08H ..................................................................... 313
Year Register (YER) - 09H ......................................................................... 313
RTC Control Register A (CRA) – 0AH ........................................................ 314
Divider Chain Control and Test Selection .................................................. 314
Periodic Interrupt Rate Encoding ............................................................... 315
RTC Control Register B (CRB) - 0BH ........................................................ 316
RTC Control Register C (CRC) - 0CH ........................................................ 318
RTC Control Register D (CRD) - 0DH ........................................................ 319
Date of Month Alarm Register (DOMA) ...................................................... 319
Month Alarm Register (MONA) .................................................................. 319
Century Register (CEN) ............................................................................. 320
BCD and Binary Formats ........................................................................... 320
RTC Register Bitmap ................................................................................ 321
Standard RAM Map .................................................................................... 321
Extended RAM Map ................................................................................... 321
ACB Register Map....................................................................................... 329
ACB Serial Data Register (ACBSDA) - 00H ................................................ 329
ACB Status Register (ACBST) - 01H .......................................................... 330
ACB Control Status Register (ACBCST) - 02H ........................................... 331
ACB Control Register 1 (ACBCTL1) - 03H.................................................. 332
ACB Own Address Register (ACBADDR) - 04H ......................................... 333
ACB Control Register 2 (ACBCTL2) - 05H.................................................. 334
ACB Register Bitmap .................................................................................. 334
KBC Register Map....................................................................................... 335
KBC Bitmap Summary ................................................................................ 335
FDC Register Map....................................................................................... 336
FDC Bitmap Summary ................................................................................ 337
Parallel Port Register Map for First Level Offset ......................................... 338
Parallel Port Register Map for Second Level Offset .................................... 338
Parallel Port Bitmap Summary for First Level Offset ................................... 339
Parallel Port Bitmap Summary for Second Level Offset.............................. 340
Bank 0 Register Map ................................................................................... 341
Bank Selection Encoding ............................................................................ 342
Bank 1 Register Map ................................................................................... 342
Bank 2 Register Map ................................................................................... 342
Bank 3 Register Map ................................................................................... 342
Bank 0 Bitmap ............................................................................................. 343
Bank 1 Bitmap ............................................................................................. 344
Bank 2 Bitmap ............................................................................................. 344
Bank 3 Bitmap ............................................................................................. 344
Register Bank Summary ............................................................................ 355
Bank 0 Register Map ................................................................................... 356
Interrupt Enable Register (IER, Non-Extended Mode) ................................ 358
Non-Extended Mode Interrupt Priorities ...................................................... 360
Bit Settings for Parity Control ...................................................................... 364

ZFx86 Data Book 1.0 Rev D

Page 22

List of Tables
Table 4.169
Table 4.170
Table 4.171
Table 4.172
Table 4.173
Table 4.174
Table 4.175
Table 4.176
Table 4.177
Table 4.178
Table 4.179
Table 4.180
Table 4.181
Table 4.182
Table 4.183
Table 4.184
Table 4.185
Table 4.186
Table 4.187
Table 4.188
Table 4.189
Table 4.190
Table 4.191
Table 4.192
Table 4.193
Table 4.194
Table 4.195
Table 4.196

Bank Selection Encoding ............................................................................ 365
Bank 0 Bitmap ............................................................................................. 372
Bank 1 Register Map ................................................................................... 373
Bits Cleared on Fallback ............................................................................. 374
Baud Generator Divisor Settings ................................................................. 374
Bank 1 Bitmap ............................................................................................. 375
Bank 2 Register Map ................................................................................... 375
DMA Threshold Levels ................................................................................ 377
Bank 2 Bitmap ............................................................................................. 380
Bank 3 Register Map ................................................................................... 380
Bank 3 Bitmap ............................................................................................. 381
Bank 4 Register Map ................................................................................... 382
Bank 4 Bitmap ............................................................................................. 384
Bank 5 Register Map ................................................................................... 385
Bank 5 Bitmap ............................................................................................. 388
Bank 6 Register Map ................................................................................... 388
IMIR Pulse Width Settings........................................................................... 390
MIR Beginning Flags ................................................................................... 392
FIR Preamble Length .................................................................................. 392
Bank 6 Bitmap ............................................................................................. 392
Bank 7 Register Map ................................................................................... 393
CEIR, Low Speed Demodulator (RXHSC = 0) ............................................ 394
Consumer IR High Speed Demodulator (RXHSC = 1)................................ 395
Sharp-IR Demodulator ................................................................................ 395
Carrier Clock Pulse Width Options (Frequency Ranges in KHz)................. 396
CEIR Carrier Frequency Encoding (Frequency Ranges in KHz)................. 396
Infrared Receiver Input Selection ................................................................ 400
Bank 7 Bitmap ............................................................................................. 401

5. ZF-Logic and Clocking ......................................................................................... 403
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.9
Table 5.10
Table 5.11
Table 5.12
Table 5.13
Table 5.14
Table 5.15
Table 5.16
Table 5.17
Table 5.18

Access to ZFL ............................................................................................. 404
ZF-Logic Complete Index ............................................................................ 406
ZF-Logic Pin List ......................................................................................... 409
Memory Mapper Pins .................................................................................. 410
Indices For Memory Windows ..................................................................... 411
Memory Window “N” Base Low - Bits 15:12 (nibble 3)................................ 411
Memory Window “N” Base High - Bits 23:16 (nibbles 5-4) .......................... 412
Memory Window “N” Size Low - (nibble 3) .................................................. 412
Memory Window “N” Size High - (nibbles 5-4) ............................................ 412
Memory Window “N' Page Low - (nibble 3) ................................................. 412
Memory Window “N” Page High - (nibbles 5-4)........................................... 412
Memory Control Low -- Index 5AH .............................................................. 413
Memory Control High -- Index 5BH ............................................................. 413
I/O and Memory Window Mapper Events -- Index 66H ............................... 414
GPCS Pins .................................................................................................. 422
ZF-Logic Indices For I/O Windows .............................................................. 423
ZF-Logic Index for I/O Windows .................................................................. 423
I/O Window “N” Base Low Format............................................................... 423

ZFx86 Data Book 1.0 Rev D

Page 23

List of Tables
Table 5.19
Table 5.20
Table 5.21
Table 5.22
Table 5.23
Table 5.24
Table 5.25
Table 5.26
Table 5.27
Table 5.28
Table 5.29
Table 5.30
Table 5.31
Table 5.32
Table 5.33
Table 5.34
Table 5.35
Table 5.36
Table 5.37
Table 5.38
Table 5.39
Table 5.40
Table 5.41
Table 5.42
Table 5.43
Table 5.44
Table 5.45
Table 5.46
Table 5.47
Table 5.48
Table 5.49
Table 5.50
Table 5.51
Table 5.52

I/O Window “N” Base High Format .............................................................. 424
ZF-Logic Index for the Watchdog Timers .................................................... 426
Watchdog 1 Count Low Byte -- Index 0CH ................................................. 426
Watchdog 1 Count High Byte -- Index 0DH................................................. 426
Watchdog Generated Reset Pulse Length -- Index 0FH ............................. 427
Watchdog Control Low -- Index 10H ........................................................... 427
Watchdog Control High -- Index 11H .......................................................... 428
Watchdog Status -- Index 12H .................................................................... 429
ZF-Logic Index for the PWM Generator ...................................................... 430
PWM Prescaler Low Byte - Index 04H ........................................................ 431
PWM Prescaler High Byte - Index 05h ........................................................ 431
PWM duty cycle - Index 06h........................................................................ 431
PWM I/O Control -- Index 08H .................................................................... 432
PWM Read Output -- Index 0AH ................................................................. 432
ZF-Logic Index for the Z-tag ........................................................................ 434
Z-tag Data Write Register -- Index 5EH ...................................................... 435
Z-tag Data Read Register -- Index 60H..................................................... 435
Z-tag Control Register -- Index 7CH............................................................ 436
Z-tag Sequencer Divisor -- Index 7DH ........................................................ 436
Z-tag Sequencer Waveform -- Index 7EH ................................................... 436
Z-tag Sequencer Strobe Points -- Index 7FH .............................................. 437
Z-tag Sequencer Data -- Index 80H ............................................................ 437
ZF-Logic Index for the Boot Parameters Register ....................................... 438
Composite BootStrap Register Map ............................................................ 438
Sample DIP Switch Settings........................................................................ 441
ZF-Logic Index for the Scratch Register...................................................... 444
Indices for Scratch Registers ...................................................................... 444
Scratch Register “N” High or Low................................................................ 445
ZF-Logic Index for BUR Base ..................................................................... 445
BUR Base Bits 15-12 .................................................................................. 445
BUR Base Bits 23-16 .................................................................................. 446
System Clocking.......................................................................................... 447
Formal Clock Names and Clocking Modes ................................................. 448
CORE frequencies (MHz)............................................................................ 451

6. Z-tag, BUR, and The ZFiX Console ...................................................................... 455
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8

Memory Dongle Jumper Settings ................................................................ 458
Z-tag and ZFiX Summary ............................................................................ 459
Pins for the FLOPPY / Z-tag Logic .............................................................. 460
Z-tag Data Lines .......................................................................................... 461
Z-Logic Index for the Z-tag .......................................................................... 461
Z-tag Control Register -- Index 7CH............................................................ 462
ZFix Console Commands ............................................................................ 463
On-Chip RAM Assignment in BUR .............................................................. 470

7. Electrical Specifications ....................................................................................... 481
Table 7.1
Table 7.2

Absolute Maximum Ratings......................................................................... 481
Recommended Operating Conditions ......................................................... 482

ZFx86 Data Book 1.0 Rev D

Page 24

List of Tables
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Table 7.13
Table 7.14
Table 7.15
Table 7.16
Table 7.17
Table 7.18
Table 7.19
Table 7.20
Table 7.21
Table 7.22
Table 7.23
Table 7.24
Table 7.25
Table 7.26
Table 7.27
Table 7.28
Table 7.29
Table 7.30
Table 7.31
Table 7.32
Table 7.33
Table 7.34
Table 7.35
Table 7.36
Table 7.37
Table 7.38
Table 7.39
Table 7.40
Table 7.41
Table 7.42
Table 7.43
Table 7.44
Table 7.45
Table 7.46
Table 7.47
Table 7.48

Current Consumption .................................................................................. 482
Pin Capacitance and Inductance................................................................. 482
I/O Cell Characteristics................................................................................ 483
Input, MPCi.................................................................................................. 484
Input, Generic2............................................................................................ 484
Input, MUSB ................................................................................................ 485
Input, MIDE ................................................................................................. 485
Input, M-FDCP ............................................................................................ 485
Input, MMC-D .............................................................................................. 485
Input, MWUSB............................................................................................. 486
Input, MAC97 .............................................................................................. 486
Output, PCI TRI-STATE Buffer ................................................................... 487
Output, GENERIC 2 .................................................................................... 487
Output, MIDE............................................................................................... 487
Output, MUSB ............................................................................................. 487
Output, M-FDC_PP ..................................................................................... 487
Output, MMC_D .......................................................................................... 488
Output, MWUSB .......................................................................................... 488
Output, MAC97............................................................................................ 488
Default Levels for Measurement of Switching Parameters ......................... 489
sysclk_c Clock Parameters ......................................................................... 489
SDRAM Interface Signals............................................................................ 493
ACCESS.bus Interface ................................................................................ 494
PCI Bus - AC Specifications ........................................................................ 495
PCI Clock Parameters ................................................................................. 497
PCI Bus Timing Parameters ........................................................................ 498
Measurement Condition Parameters........................................................... 499
ISA Output Signals ...................................................................................... 501
General Timing of the IDE Interface ............................................................ 504
IDE Register Transfer To/From Device ....................................................... 505
IDE PIO Data Transfer To/From Device...................................................... 507
IDE Multiword DMA Data Transfer .............................................................. 509
Ultra DMA Data Burst Timing Requirements............................................... 511
Universal Serial Bus (USB) ......................................................................... 523
UART, Sharp-IR, SIR, and Consumer Remote Control Parameters ........... 527
Fast IR Port Timing Parameters .................................................................. 528
JTAG Timing ............................................................................................... 529
GPIO Timing................................................................................................ 530
Floppy Disk Reset Timing ........................................................................... 531
Floppy Disk Write Data Timing .................................................................... 531
Write Data Timing – Minimum tWDW Values.............................................. 531
Drive Control Timing.................................................................................... 532
Read Data Timing ....................................................................................... 533
KBC Signals Rising and Falling................................................................... 533
Standard Parallel Port Timing ..................................................................... 534
Enhanced Parallel Port 1.7 Timing Parameters .......................................... 535

ZFx86 Data Book 1.0 Rev D

Page 25

List of Tables
Table 7.49
Table 7.50
Table 7.51
Table 7.52

Enhanced Parallel Port 1.9 Timing Parameters .......................................... 536
Extended Capabilities Port (ECP) Timing – Forward .................................. 538
Extended Capabilities Port (ECP) Timing – Backward................................ 539
ZF-Logic Signals ......................................................................................... 540

8. Pinout Summary ................................................................................................... 541
Table 8.1
Table 8.2
Table 8.3
Table 8.4

Pin Utilization............................................................................................... 541
Pin Descriptions Sorted by Pin .................................................................... 545
Pin Descriptions Sorted by Pin Name ......................................................... 558
Pin Descriptions Sorted by Pin Description ................................................. 572

9. BUR API ................................................................................................................. 587
10. Signal Status After POST ................................................................................... 597
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10

Access Bus Settings.................................................................................... 597
Floppy Disk (FDD) Settings ......................................................................... 597
Floppy Disk (Z-tag) Settings ........................................................................ 598
GPIO Settings ............................................................................................. 599
ISA Pin Settings .......................................................................................... 599
PS/2 Pin Settings ........................................................................................ 599
PCI Settings ................................................................................................ 600
LPT Settings ................................................................................................ 600
IR Control Settings ...................................................................................... 601
ZF Logic Settings ........................................................................................ 601

11. Phoenix BIOS Register Settings ........................................................................ 603
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.9
Table 12.10
Table 12.11
Table 12.12
Table 12.13
Table 12.14
Table 12.15
Table 12.16
Table 12.17
Table 12.18
Table 12.19
Table 12.20
Table 12.21
Table 12.22

Reset, Sampling, and Misc North Bridge Registers .................................... 603
DRAM Registers.......................................................................................... 615
Power Management Registers .................................................................... 623
PCI Configuration Registers ........................................................................ 624
Floppy Disk Controller Registers ................................................................. 626
Floppy Disk Controller Bitmap Summary .................................................... 627
Parallel Port Registers................................................................................. 629
Serial Port 1 Registers ................................................................................ 630
Serial Port 2 Registers ................................................................................ 632
PS/2 Mouse/Keyboard Registers ............................................................... 633
Infrared Communication Port Configuration Registers ............................... 635
Access Bus Registers ................................................................................. 636
Pin Multiplexor Registers............................................................................. 637
GPIO0 Registers ......................................................................................... 640
GPIO1 Registers ......................................................................................... 641
GPIO2 Registers ......................................................................................... 642
GPIO3 Registers ......................................................................................... 643
GPIO4 Registers ......................................................................................... 644
GPIO5 Registers ......................................................................................... 645
GPIO6 Registers ......................................................................................... 646
GPIO7 Registers ......................................................................................... 647
ZF–Logic Registers ..................................................................................... 648

ZFx86 Data Book 1.0 Rev D

Page 26

List of Tables
Index .......................................................................................................................... 653

ZFx86 Data Book 1.0 Rev D

Page 27

List of Tables

ZFx86 Data Book 1.0 Rev D

Page 28

1
1. Overview
The “ZFx86” System-On-a-Chip (SOC) is a
complete processor and peripheral subsystem
requiring only external clocks, SDRAM, and
BIOS ROM/Flash. It is illustrated in ZFx86
Fail-Safe PC-on-a-Chip Block Diagram and
consists of the following major blocks:
1) Industry standard 32 bit processor core
with integrated floating point co-processor and 8K byte write-back level 1
cache. The clock multiplier design
allows the core to run at a multiple of
the system bus. For example, a 3x
multiplier delivers a system running at
100 MHz with a 33 MHz PCI bus.

4) 12K Bytes of ROM with ZF proprietary
code. This Boot Up ROM (BUR) is
used in a special mode which allows a
flash based BIOS to be updated without removal of any system components or peripherals. See ‘BUR (Boot
Up ROM) ’ on page 462.
5) ZF proprietary digital logic including
specific and general purpose chip
selects, watchdog timer, and flash controller. See ‘ZF-Logic and Clocking ’
on page 403.
The above functions are packaged in a 35
MM. 388 pin Ball Grid Array (BGA). See
‘Pinout Summary ’ on page 541.

2) A North Bridge (system controller) with
“Frontside” PCI Master / Slave Arbitration interface and SDRAM interface.
See ‘North Bridge ’ on page 113.
3) A custom South Bridge with “Frontside” PCI interface to the North Bridge
and “Backside” PCI Master/Slave system interface, enhanced IDE controller
supporting four devices on two channels, USB controller with two hub
ports, real time clock (RTC), floppy
disk controller, serial ports, access
bus, 8042 compatible keyboard and
mouse controller, parallel port, general
purpose programmable I/O’s and
counters, PC/AT system components,
and power management. The PC/AT
system components include 8237
compatible DMA controllers, two 8259
compatible interrupt controllers, 8254
compatible system timer, and ISA bus
interface. See ‘South Bridge ’ on page
165.

ZFx86 Data Book 1.0 Rev D

Page 29

1
Figure 1-1 ZFx86 Fail-Safe PC-on-a-Chip Block Diagram

•
•
•
•

Processor: 486+ CPU at 100 MHz
North Bridge: DRAM Controller and FrontSide 32 MHz PCI Bus
South Bridge: Generates BackSide PCI and ISA Buses.
USB + Extended IDE Device Interface: on the FrontSide PCI Bus

•
•

SuperIO: Industry Standard X86 I/O + I2C
ZF-Logic: ISA Additions for Embedded Systems, Low BOM cost, and FailSafe

ZFx86 Data Book 1.0 Rev D

Page 30

2
2. 32-bit x86 Processor
2.1. Overview
The Processor is an industry standard 32-bit
x86 compatible microprocessor.
Configure the 8 KB cache to run in traditional
write-through mode or in the higher performance write-back mode. Write-back mode
eliminates unnecessary external memory write
cycles offering higher overall performance
than write-through mode.
The processor supports 8-, 16- and 32-bit data
types and operates in real, virtual 8086 and

protected modes. The CPU accesses up to 256
MB of physical memory using a 32-bit burst
mode bus. Floating point instructions are
parallel processed using an on-chip math
coprocessor.
The processor is an ideal design solution for
low-powered applications. Due to its static
design, it features a low current drain while the
input clock is stopped in suspend mode. SMM
(System Management Mode) allows the implementation of transparent system power
management or the software emulation of I/O
peripheral devices.

SUSP#
16-Byte
Instruction
Queue

Instruction
r
Decoder

Control

Core
Clock

Immediate

Prefetch
Data Bus

32

Bus
Clock

SMM,
Suspend
Mode
and
Clock
Control

ROM
Address

SUSPA#
CLK
SMI#
SMADS#

Microcode ROM
Sequencer
Control

Execution Pipeline

Memory
Data
Bus

Execution Unit

Branch Control
Limit
Unit

8
Write

Immediate

Multiplier
Line

3-Input
Adder
Unit

Shift
Unit

Register
File

Buffers

Byte
MUXES
& I/O
Regs

D31-D0
Data
Buffers

32

Linear Address Bus

FPU
Cache and Memory
Management

Memory
Management
Unit

Prefetch
Unit

8 KB
Instr/Data
Cache

Bus
Control

Control

Control

Instruction Address Bus
Data Address Bus

Address
Buffers

AD31-AD2
BE3#-BE0#

32-bit x86-Compatible
Bus Interface

Figure 2-1 Processor Block Diagram

ZFx86 Data Book 1.0 Rev D

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2
2.1.1. Internal Clock Logic
The processor operates in 4 clock rate modes
and 3 clock operation modes. These modes
are controlled by 4 signals, CLKMODE0,
CLKMODE1, PLLMODE and RAWCLK. Additionally 3 signals, CLKDEL[2:0] control the
duty cycle of the internal clock signal.
As you look at the clock modes, please also
reference Table 5.42 "Composite BootStrap
Register Map" on page 438, and Figure 5-9
"System Clocking and Control" on page 443.

2.1.1.1. Clock Rate Modes
The internal clock rate can be 1, 2, 3 or 4
times the input clock rate as controlled by the
CLKMODE[1:0] signals.
RATE
1X
2X
3X
4X

CLKMODE[1:0]
00b
01b
11b
10b

2.1.1.2. Clock Operation Modes
The source of the internal clock is determined
by the PLLMODE and RAWCLK signals.
Three modes of operation are supported, PLL
Mode, Delay Mode and Raw Clock Mode.
Mode
PLLMODE
PLL Mode
1
Delay Mode
0
Rawclock Mode
0
NOT SUPPORTED
1

RAWCLK
1
1
0
0

PLL Mode (DLL Mode)
In PLL Mode the source of the internal clock is
from the Digital Locked Loop. Clock modes 1x,
2x, 3x and 4x are supported. The duty cycle of
the internal clock is determined by the state of
the CLKDEL[2:0] signals.

Delay Mode
In Delay Mode the source of the internal clock
is from the Clock Delay circuitry. Modes 1x,

ZFx86 Data Book 1.0 Rev D

2x, 3x and 4x are supported. The duty cycle
and frequency of the internal clock is determined by the state of the CLKDEL[2:0]
signals. The exact operation of this mode is
beyond the scope of this document.

Raw Clock Mode
Raw Clock Mode is normally used for test
purposes only. In Raw Clock Mode the source
of the internal clock is from the CLK port. Only
clock rate mode 1x is supported in this mode.

Clock Delay Signals
The CLKDEL[2:0] signals effect the duty cycle
of the internal clock. The exact effect is
beyond the scope of this document. The
setting of these signals is determined during
early production testing experimentally. The
setting which results in the best performance
over voltage, temperature and frequency is
normally used as a bond out option in the final
package.

2.1.2. On-Chip Write-Back Cache
The processor on-chip cache can be configured to run in traditional write-through mode or
in a higher performance write-back mode. The
write-back cache mode was specifically
designed to optimize performance of the CPU
core by eliminating bus bottlenecks caused by
unnecessary external write cycles. This writeback architecture is especially effective in
improving performance of the clock-tripled
processor.
Traditional write-through cache architectures
require that all writes to the cache also update
external memory simultaneously. These
unnecessary write cycles create bottlenecks
which result in CPU stalls that adversely
impact performance. In contrast, a write-back
architecture allows data to be written to the
cache without updating external memory. With
a write-back cache, external write cycles are
only required when a cache miss occurs, a
modified line is replaced in the cache, or when
an external bus master requires access to
data.

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2
The processor cache is an 8 KB unified
instruction. Data cache is implemented using
a four-way set associative architecture and an
LRU (Least Recently Used) replacement algorithm. The cache is designed for optimum
performance in write-back mode; however, the
cache can be operated in write-through mode.
The cache line size is 16 bytes and new lines
are only allocated during memory read cycles.
Valid status is maintained on a 16-byte cache
line basis, but modified or “dirty” status for
write-back mode is maintained on a 4-byte
DWORD (Double Word) basis. Therefore, only
the DWORDs that have been modified are
written back to external memory when a line is
replaced in the cache. The CPU core can
access the cache in a single internal clock
cycle for both reads and writes.

2.1.3. System Management Mode
System Management Mode (SMM) provides
an additional interrupt and a separate address
space that can be used for system power
management or software transparent emulation of I/O peripherals. SMM is entered using
the SMI# (System Management Interrupt) or
SMINT instruction. While running in isolated
SMM address space, the SMI interrupt routine
can execute without interfering with the operating system or application programs.
After entering SMM, portions of the CPU state
are automatically saved. Program execution
begins at the base of SMM address space.
The location and size of the SMM memory are
programmable within the processor. Eight
SMM instructions have been added to the
processor instruction set that permit software
entry into SMM, as well as saving and
restoring the total CPU state when in SMM
mode.

consumption is far less than full operation
current.
Suspend mode is entered by either a hardware or a software initiated action. Using the
hardware method to initiate suspend mode
involves a two-signal handshake between the
SUSP# and SUSPA# signals. The software
can initiate suspend mode through the execution of the HALT instruction. Once in suspend
mode, power consumption is further reduced
by stopping the external clock input. Since the
processor is static, no internal data is lost
when the clock is stopped.

2.1.5. Signal Summary
The processor interface signal set includes
five cache interface signals, two coprocessor
interface signals, two power management
signals, and two system management mode
signals.

2.2. Programming Interface
In this chapter the internal operations of the
Processor are described from an application
programmer’s point of view. Included in this
chapter are descriptions of processor initialization, the register set, memory addressing,
various types of interrupts and the shutdown
and halt process. An overview is provided of
real, virtual 8086 and protected operating
modes. FPU operations are described separately at the end of this chapter.

2.1.4. Power Management
The processor power management features
allow for a dramatic improvement in battery life
over systems designed with non-static processors. During suspend mode the typical current

ZFx86 Data Book 1.0 Rev D

Page 33

2
2.2.1. Processor Initialization
The processor is initialized when the RESET#
signal is asserted. The processor is placed in
real mode and the registers listed in Table 2.1
are set to their initialized values. RESET invalidates and disables the processor cache, and
turns off paging. When RESET# is asserted
the processor terminates all local bus activity
and all internal execution. During the entire
time that RESET# is asserted the internal
pipeline is flushed, and no instruction execution or bus activity occurs.

Approximately 150 to 250 external clock
cycles (additional 220 + 60 if self-test is
requested) after RESET is negated, the
processor begins executing instructions at the
top of physical memory (address location FFFF
FFF0h). When the first intersegment JMP or
CALL is executed, address lines AD31-AD20
are driven low for code segment-relative
memory access cycles. While AD31-AD20 are
low, the processor executes instructions only
in the lowest 1 MB of physical address space
until system-specific initialization occurs via
program execution.

Table 2.1 Initialized Register Controls
Register

Register Name

Initialized Contents

EAX

Accumulator

xxxx xxxxh

EBX

Base

xxxx xxxxh

ECX

Count

xxxx xxxxh

EDX

Data

xxxx 0400h + Device ID

EBP

Base Pointer

xxxx xxxxh

ESI

Source Index

xxxx xxxxh

EDI

Destination Index

xxxx xxxxh

ESP

Stack Pointer

xxxx xxxxh

Comments
0000 0000h indicates self-test passed

Device ID = xxh

EFLAGS

Flag Word

0000 0002h

EIP

Instruction Pointer

0000 FFF0h

ES

Extra Segment

0000h

Base address set to 0000 0000h. Limit set to FFFFh

CS

Code Segment

F000h

Base address set to FFFF 0000h. Limit set to FFFFh

SS

Stack Segment

0000h

Base address set to 0000 0000h. Limit set to FFFFh

DS

Data Segment

0000h

Base address set to 0000 0000h. Limit set to FFFFh

FS

Extra Segment

0000h

Base address set to 0000 0000h. Limit set to FFFFh

GS

Extra Segment

0000h

Base address set to 0000 0000h. Limit set to FFFFh

IDTR

Interrupt Descriptor Table Register Base = 0, Limit = 3FFh

CR0

Machine Status Word

6000 0010h

CCR1

Configuration Control 1

00h

CCR2

Configuration Control 2

00h

CCR3

Configuration Control 3

00h

SMAR

SMM Address Region

0000h

DIR0

Device Identification 0

processor = xxh

DIR1

Device Identification 1

Step ID + Revision ID

DR7

Debug Register 7

0000 0400h

Note: x = Undefined value

ZFx86 Data Book 1.0 Rev D

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2
2.2.1.1. Warm Reset
The WM_RESET input signal is used to
support write back caching policy on the
processor. The WM_RESET signal will reset
the entire processor except for the CD and
NW bits in the CR0 register, the CFG0
register, the CFG1 register and the valid and
dirty bits in the cache. The WM_RESET signal
is always enabled and included a pull-down
resistor to keep the pin inactive when not
used.

2.2.2. Instruction Set Overview
The processor instruction set can be divided
into eight types of operations:
• Arithmetic
• Bit Manipulation
• Control Transfer
• Data Transfer
• Floating Point
• High-Level Language Support
• Operating System Support
• Shift/Rotate
• String Manipulation
All processor instructions operate on as few
as 0 operands and as many as 3 operands.
An NOP instruction (no operation) is an
example of a 0 operand instruction. Two
operand instructions allow the specification of
an explicit source and destination pair as part
of the instruction. These two operand instructions can be divided into eight groups
according to operand types:
•
•
•
•
•
•
•
•

Register to Register
Register to Memory
Memory to Register
Memory to Memory
Register to I/O
I/O to Register
Immediate Data to Register
Immediate Data to Memory

ZFx86 Data Book 1.0 Rev D

An operand can be held in the instruction itself
(as in the case of an immediate operand), in a
register, in an I/O port or in memory. An
immediate operand is prefetched as part of the
opcode for the instruction.
• Operand lengths of 8, 16, or 32 bits are
supported as well as 64 or 80 bit associated with floating point instructions.
• Operand lengths of 8 or 32 bits are generally used when executing code written for
x86 32-bit code processors.
• Operand lengths of 8 or 16 bits are generally used when executing existing 8086 or
80286 code (16-bit code).
The default length of an operand can be overridden by placing one or more instruction
prefixes in front of the opcode. For example, by
using prefixes, a 32-bit operand can be used
with 16-bit code or a 16-bit operand can be
used with 32-bit code.
Section 2.3. ‘Instruction Set’ of this manual
lists each instruction in the processor instruction set along with the associated opcodes,
execution clock counts and effects on the
FLAGS register.

2.2.2.1. Lock Prefix
The LOCK prefix may be placed before certain
instructions that read, modify, then write back
to memory. The prefix asserts the LOCK#
signal to indicate to the external hardware that
the CPU is in the process of running multiple
indivisible memory accesses. The LOCK
prefix can be used with the following instructions:
• Bit Test Instructions (BTS, BTR, BTC)
• Exchange Instructions (XADD, XCHG,
CMPXCHG)
• One-operand Arithmetic and Logical
Instructions (DEC, INC, NEG, NOT)

Page 35

2
• Two-operand Arithmetic and Logical
Instructions (ADC, ADD, AND, OR, SBB,
SUB, XOR)
An invalid opcode exception is generated if
the LOCK prefix is used with any other instruction, or with the above instructions when no
write operation to memory occurs (i.e., the
destination is a register). The LOCK prefix
function may be disabled by setting the
NO_LOCK bit in Configuration Control Register
1 (CCR1).
If No_Lock (bit 4 in CCR1) is set, locked
cycles are inhibited for some locked instructions. These instructions include interrupt
acknowledge cycles, descriptor loads, and
updates and accesses to the interrupt
descriptor table. However, locked cycles are
not inhibited by No_Lock bit for TLB table
lookups, XCHG instructions to memory, or any
instruction that includes a lock prefix.
If No_Lock = 0, locked cycles occur for all
locked instructions.

2.2.3. Register Set
There are 40 accessible registers in the
processor, and these registers are grouped
into two sets:

2.2.3.1. Application Register Set
The Application Register Set, shown in Table
2.2, are generally accessible and are not
protected from read or write access.
The contents of the eight General Purpose
Registers are frequently modified by assembly
language instructions and typically contain
arithmetic and logical instruction operands.
In real mode the six Segment Registers
contain the base address for each segment. In
protected mode the Segment Registers
contain segment selectors. The segment
selectors provide indexing for tables (located
in memory) that contain the base address for
each segment, as well as other memory
addressing information.
The Flag Register contains control bits used to
reflect the status of previously executed
instructions. This register also contains control
bits that affect the operation of some instructions.
The Instruction Pointer register points to the
next instruction that the processor will
execute. This register is automatically incremented by the processor as execution
progresses.

• The Application Register Set contains
eight general purpose registers, six
segment registers, a flag register and an
instruction pointer register, and are typically used by application programmers.
• The System Register Set contains the
remaining registers which include three
control registers, four system address
registers, six debug registers, six configuration registers and five test registers, and
are typically used by operating system
programmers.
Each of the registers is discussed in detail in
the following sections.

ZFx86 Data Book 1.0 Rev D

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2
Table 2.2 Application Register Set
31

16

15

8

7

0

Application
Register Set

AX
AH

AL

EAX (Extended A Register)
BX
BH

BL

EBX (Extended B Register)
CX
CH

CL

ECX (Extended C Register)
DX
DH

DL

EDX (Extended D Register)

General
Purpose
Registers

SI (Source Index)
ESI (Extended Source Index)
DI (Destination Index)
EDI (Extended Destination Index)
BP (Base Pointer)
EBP (Extended Base Pointer)
SP (Stack Pointer)
ESP (Extended Stack Pointer)
CS (Code Segment)
SS (Stack Segment)
DS (D Data Segment)
ES (E Data Segment)
FS (F Data Segment)

Segment
(Selector)
Registers

GS (G Data Segment)
EIP (Extended Instruction Pointer Register)
EFLAGS (Extended Flags Register)

General Purpose Registers (eight)
The General Purpose Registers are divided
into four data registers, two pointer registers,
and two index registers.
Data Registers are used by the applications
programmer to manipulate data structures and
to hold the results of logical and arithmetic
operations. Different portions of the general
data registers can be addressed by using
different names. An “E” prefix identifies the
complete 32-bit register. An “X” suffix without
the “E” prefix identifies the lower 16 bits of the

ZFx86 Data Book 1.0 Rev D

Instruction
Pointer and
Flags Register

register. The lower two bytes of the register
can be addressed with an “H” suffix to identify
the upper byte or an “L” suffix to identify the
lower byte. When a destination operand size
specified by an instruction is smaller than the
specified destination register, the other bytes
of the destination register are not affected
when the operand is written to the register.

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2
The Pointer and Index Registers are listed as
follows:

processor to determine the location in memory
of code, data and stack references.
There are six 16-bit segment registers:

• SI or ESI

Source Index

• DI or EDI

Destination Index

• CS – Code Segment

• SP or ESP

Stack Pointer

• DS – Data Segment

• BP or EBP

Base Pointer

• ES – Extra Segment
• SS – Stack Segment

These registers can be addressed as 16- or 32bit registers, with the “E” prefix indicating 32
bits. The pointer and index registers can be
used as general purpose registers, however,
some instructions use a fixed assignment of
these registers. For example, repeated string
operations always use ESI as the source
pointer, EDI as the destination pointer and
ECX as a counter. The instructions using fixed
registers include multiply and divide, I/O
access, string operations, translate, loop, variable shift and rotate and stack operations
instructions.
The processor implements a stack using the
ESP register. This stack is accessed during
the PUSH and POP instructions, procedure
calls, procedure returns, interrupts, exceptions, and interrupt/exception returns. The
microprocessor automatically adjusts the value
of the ESP during operation of these instructions.

• FS – Additional Data Segment
• GS – Additional Data Segment
In real and virtual 8086 operating modes, a
segment register holds a 16-bit segment base.
The 16-bit segment base is multiplied by 16
and a 16-bit or 32-bit offset is then added to it
to create a linear address. The offset size is
dependent on the current address size. In real
mode and in virtual 8086 mode with paging
disabled, the linear address is also the physical address. In virtual 8086 mode with paging
enabled, the linear address is translated to the
physical address using the current page
tables.
In protected mode, a segment register holds a
Segment Selector containing a 13-bit Index, a
Table Indicator (TI) bit, and a two-bit
Requested Privilege Level (RPL) field, as illustrated in Figure 2-1.
15

The EBP register may be used to reference
data passed on the stack during procedure
calls. Local data may also be placed on the
stack and referenced relative to BP. This
register provides a mechanism to access
stack data in high-level languages.

Segment Registers and Selectors (six)
Segmentation provides a means of defining
data structures inside the memory space of
the microprocessor. There are three basic
types of segments: code, data, and stack.
Segments are used automatically by the

ZFx86 Data Book 1.0 Rev D

3
Index

2 1
0
T
RPL
I

TI = Table Indicator
RPL = Request Privilege Level
Figure 2-1 Segment Selector

The Index Register points into a descriptor
table in memory and selects one of 8192 (213)
segment descriptors contained in the
descriptor table. A segment descriptor is an 8byte value used to describe a memory
segment by defining the segment base, the
segment limit, and access control information.

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To address data within a segment, a 16-bit or
32-bit offset is added to the segment’s base
address. Once a segment selector has been
loaded into a segment register, an instruction
needs to specify the offset only. The Table
Indicator (TI) bit of the selector defines which
descriptor table the index points to. If TI = 0,
the index references the Global Descriptor
Table (GDT). If TI = 1, the index references the
Local Descriptor Table (LDT). The GDT and
LDT are described in more detail later in
Section ‘Descriptor Table Registers and
Descriptors’ on page 44.
The Requested Privilege Level (RPL) field contains
a 2-bit segment privilege level (0 = most privileged, 3 = least privileged). The RPL bits are
used when the segment register is loaded to
determine the Effective Privilege Level (EPL). If
the RPL bits indicate less privilege than the
Current Program Level (CPL), the RPL overrides the CPL and the EPL is the less privileged
level. If the RPL bits indicate more privilege than
the program, the CPL overrides the RPL and
again the EPL is the less privileged level.

When a segment register is loaded with a
segment selector, the segment base, segment
limit and access rights are also loaded from
the descriptor table into a user-invisible or
hidden portion of the segment register i.e.,
cached on-chip. The CPU does not access the
descriptor table again until another segment
register load occurs. If the descriptor tables
are modified in memory, the segment registers
must be reloaded with the new selector values
by the software.
The processor automatically selects a default
segment register for memory references. Table
2.3 describes the selection rules. In general, data
references use the selector contained in the
DS register, stack references use the SS
register and instruction fetches use the CS
register. While some of these selections may be
overridden, instruction fetches, stack operations, and the destination write of string operations cannot be overridden. Special segment
override prefixes allow the use of alternate
segment registers including the use of the ES,
FS, and GS segment registers.

Table 2.3 Segment Register Selection Rules
Implied (Default)
Segment

Type of Memory Reference

Segment-Override
Prefix

Code Fetch

CS

None

Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions

SS

None

Source of POP, POPA, POPF, IRET, RET instructions

SS

None

Destination of STOS, MOVS, REP STOS, REP MOVS instructions

ES

None

Other data references with effective address using base registers of:
EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP

DS

CS, ES, FS, GS, SS

SS

CS, DS, ES, FS, GS

Instruction Pointer Register (one)
The Instruction Pointer (EIP) register contains
the offset into the current code segment of the
next instruction to be executed. The register is
normally incremented with each instruction
execution unless implicitly modified through an
interrupt, exception or an instruction that

ZFx86 Data Book 1.0 Rev D

changes the sequential execution flow
(e.g., JMP, CALL).

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Flags Register (one)
The Extended Flags Register, EFLAGS,
contains status information and controls
certain operations on the processor. The lower

16 bits of this register are referred to as the
FLAGS register that is used when executing
8086 or 80286 code. The flag bits are illustrated in Table 2.4

Table 2.4 EFLAGS Register
Bit

Name

Flag Type

31:19

RSVD

--

Description

18

AC

System

Alignment Check Enable — In conjunction with the AM flag in CR0, the AC flag determines
whether or not misaligned accesses to memory cause a fault. If AC is set, alignment faults are
enabled.

17

VM

System

Virtual 8086 Mode — If set while in protected mode, the processor switches to virtual 8086
operation handling segment loads as the 8086 does, but generating exception 13 faults on
privileged opcodes. The VM bit can be set by the IRET instruction (if current privilege level
is 0) or by task switches at any privilege level.

16

RF

Debug

Resume Flag — Used in conjunction with debug register breakpoints. RF is checked at
instruction boundaries before breakpoint exception processing. If set, any debug fault is
ignored on the next instruction.

15

RSVD

--

14

NT

System

Nested Task — While executing in protected mode, NT indicates that the execution of the
current task is nested within another task.

13:12

IOPL

System

I/O Privilege Level — While executing in protected mode, IOPL indicates the maximum current privilege level (CPL) permitted to execute I/O instructions without generating an exception 13 fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL
allowing alteration of the IF bit when new values are popped into the EFLAGS register.

11

OF

Arithmetic

Overflow Flag — Set if the operation resulted in a carry or borrow into the sign bit of the result
but did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted
in a carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign
bit of the result.

10

DF

Control

Direction Flag — When cleared, DF causes string instructions to auto-increment (default) the
appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index
registers to occur.

9

IF

System

Interrupt Enable Flag — When set, maskable interrupts (INTR input signal) are acknowledged and serviced by the CPU.

8

TF

Debug

Trap Enable Flag — Once set, a single-step interrupt occurs after the next instruction completes execution. TF is cleared by the single-step interrupt.

Reserved — Set to 0.

Reserved — Set to 0.

7

SF

Arithmetic

Sign Flag — Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).

6

ZF

Arithmetic

Zero Flag — Set if result is zero; cleared otherwise.

5

RSVD

--

4

AF

Arithmetic

3

RSVD

--

2

PF

Arithmetic

1

RSVD

--

0

CF

Arithmetic

ZFx86 Data Book 1.0 Rev D

Reserved — Set to 0.
Auxiliary Carry Flag — Set when a carry out of (addition) or borrow into (subtraction) bit
position 3 of the result occurs; cleared otherwise.
Reserved — Set to 0.
Parity Flag — Set when the low-order 8 bits of the result contain an even number of ones;
otherwise PF is cleared.
Reserved — Set to 1.
Carry Flag — Set when a carry out of (addition) or borrow into (subtraction) the most significant bit of the result occurs; cleared otherwise.

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2.2.3.2. System Register Set
The System Register Set, shown in Table 2.5,
consists of registers not generally used by
application programmers. These registers are
typically employed by system level programmers who generate operating systems and
memory management programs.
The Control Registers control certain
aspects of the processor such as paging,
coprocessor functions, and segment protection. When a paging exception occurs while
paging is enabled, the control registers retain
the linear address of the access that caused
the exception.
The Descriptor Table Registers and the
Task Register can also be referred to as
system address or memory management
registers. These registers consist of two 48-bit
and two 16-bit registers. These registers
specify the location of the data structures that
control the segmentation used by the
processor. Segmentation is one available
method of memory management.
The Configuration Registers are used to
configure the processor on-chip cache operation, coprocessor interface, power management features and System Management
Mode. The configuration registers also provide
information on the CPU device type and revision.
The Debug Registers provide debugging
facilities for the processor and enable the use
of data access breakpoints and code execution breakpoints.
The Test Registers provide a mechanism to
test the contents of both the on-chip 8 KB
cache and the Translation Lookaside Buffer
(TLB). The TLB is used as a cache for the
tables which are used in translating linear
addresses to physical addresses while paging
is enabled. In the following sections, the
system register set is described in greater
detail.

ZFx86 Data Book 1.0 Rev D

Table 2.5 System Register Set
Group
Control
Registers

Descriptor
Table and
Task
Registers
Configuration
Registers

Debug
Registers

Test
Registers

Name

Width
(Bits)

Function

CR0

System Control Register

32

CR2

Page Fault Linear
Address Register

32

CR3

Page Directory Base Register

32

GDTR

GDT Register

48

IDTR

IDT Register

48

LDTR

LDT Register

16

TR

Task Register Setup

16

CCR1

Configuration Control
Register 1

8

CCR2

Configuration Control
Register 2

8

CCR3

Configuration Control
Register 3

8

SMAR

SMM Address Region
Register

24

DIR0

Device Identification
Register 0

8

DIR1

Device Identification
Register 1

8

DR0

Linear Breakpoint
Address 0

32

DR1

Linear Breakpoint
Address 1

32

DR2

Linear Breakpoint
Address 2

32

DR3

Linear Breakpoint
Address 3

32

DR6

Breakpoint Status

32

DR7

Breakpoint Control

32

TR3

Cache Test

32

TR4

Cache Test

32

TR5

Cache Test

32

TR6

TLB Test Control

32

TR7

TLB Test Status

32

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2.2.3.3. Control Registers (3)
A map of the Control Registers (CR3, CR2
and CR0) is shown in Table 2.6 and the bit
definitions are given in Table 2.7. The CR0
register contains system control flags which
control operating modes and indicate the
general state of the CPU. The lower 16 bits of
CR0 are referred to as the Machine Status
Word (MSW). The reserved bits in CR0 should
not be modified.
When paging is enabled and a page fault is
generated, the CR2 register retains the 32-bit

linear address of the address that caused the
fault. Register CR3 contains the 20 most
significant bits of the physical base address of
the page directory. The page directory must
always be aligned to a 4 KB page boundary;
therefore, the lower 12 bits of CR3 are not
required to specify the base address.
When operating in protected mode, any
program can read the control registers;
however, only privilege level 0 (most privileged) programs can modify the contents of
these registers.

Table 2.6 Control Registers Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

CR3 Register
PDBR (Page Directory Base Register)

RSVD

P P
C W
D T

RSVD

CR2 Register
PFLA (Page Fault Linear Address)
CR0 Register
P
G

C N
D W

RSVD

A
M

R W
S P
V
D

RSVD

N
E

1

T
S

E
M

M
P

P
E

Machine Status Word (MSW)

Table 2.7 CR3, CR2, and CR0 Bit Definitions
Bit

Name

Description

CR3 Register
31:12

PDBR

Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.

11:4

RSVD

Reserved

4

PCD

Page-level Cache Disable: Affects the operation of internal cache.

3

PWT

Page Write Through: Drives output pins for controlling external caches.

2:0

RSVD

Reserved

CR2 Register
31:0

PFLA

Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the
address that caused the page fault.

CR0 Register

ZFx86 Data Book 1.0 Rev D

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Table 2.7 CR3, CR2, and CR0 Bit Definitions (cont.)
Bit

Name

Description

31

PG

Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled.

30

CD

Cache Disable: If CD = 1, no further cache line fills occur; however data already present in the cache continues to be
used if the requested address hits in the cache. The cache must also be invalidated to completely disable any cache
activity.

29

NW

Not Write-Through: If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes are issued
to the external bus only for a cache miss, a line replacement of a modified line, or as the result of a cache inquiry
cycle. If NW = 0, the on-chip cache operates in write-through mode. In write-through mode, all writes (including cache
hits) are issued to the external bus.

28:19

RSVD

18

AM

17

RSVD

16

WP

15:6

RSVD

5

NE

Reserved
Alignment Check Mask: If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable alignment
check faults. Setting AM = 0 prevents AC faults from occurring.
Reserved
Write Protect: Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to be written
from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.
Reserved
Numerics Exception: NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptions are to
be handled by external interrupts.

4

1

3

TS

Task Switched: Set whenever a task switch operation is performed. Execution of a floating point instruction with TS =
1 causes a DNA (Device Not Available) fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.

Reserved: Do not attempt to modify.

2

EM

Emulate Processor Extension: If EM = 1, all floating point instructions cause a DNA fault 7.

1

MP

Monitor Processor Extension: If MP = 1 and TS = 1, a WAIT instruction causes a DNA fault 7. The TS bit is set to 1
on task switches by the CPU. Floating point instructions are not affected by the state of the MP bit. The MP bit should
be set to one during normal operations.

0

PE

Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode is enabled. If
PE = 0, the CPU operates in real mode, with segment based protection disabled, and addresses are formed as in an
8086-style CPU.

Table 2.8 Effects of Various Combinations of TS, EM and MP Bits
CR0[3:1]

Instruction Type

TS

EM

MP

WAIT

ESC

0

0

0

Execute

Execute

0

0

1

Execute

Execute

1

0

0

Execute

Fault 7

1

0

1

Fault 7

Fault 7

0

1

0

Execute

Fault 7

0

1

1

Execute

Fault 7

1

1

0

Execute

Fault 7

1

1

1

Fault 7

Fault 7

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2
Descriptor Table Registers and
Descriptors
The Global, Interrupt and Local Descriptor
Table Registers (GDTR, IDTR and LDTR),
shown in Figure 2-2 "Task Register", are used
to specify the location of the data structures
that control segmented memory management.
The GDTR, IDTR and LDTR are loaded using
the LGDT, LIDT and LLDT instructions,
respectively. The values of these registers are
stored using the corresponding store instructions. The GDTR and IDTR load instructions
are privileged instructions when operating in
protected mode. The LDTR can only be
accessed in protected mode.
The Global Descriptor Table Register (GDTR)
holds a 32-bit linear base address and 16-bit
limit for the Global Descriptor Table (GDT).
The GDT is an array of up to 8192 8-byte
descriptors. When a segment register is
loaded from memory, the TI bit in the segment
selector chooses either the GDT or the Local
Descriptor Table (LDT) to locate a descriptor. If
TI = 0, the index portion of the selector is used
to locate a given descriptor within the GDT.
The contents of the GDTR are completely
visible to the programmer. The first descriptor
in the GDT (location 0) is not used by the CPU
and is referred to as the “null descriptor”. If the
GDTR is loaded while operating in 16-bit
operand mode, the processor accesses a 32bit base value but the upper 8 bits are ignored
resulting in a 24-bit base address.
48

The Interrupt Descriptor Table Register
(IDTR) holds a 32-bit linear base address and
16-bit limit for the Interrupt Descriptor Table
(IDT). The IDT is an array of 256 8-byte interrupt descriptors, each of which is used to point
to an interrupt service routine. Every interrupt
that may occur in the system must have an
associated entry in the IDT. The contents of
the IDTR are completely visible to the
programmer.
The Local Descriptor Table Register (LDTR)
holds a 16-bit selector for the Local Descriptor
Table (LDT). The LDT is an array of up to 8192
8-byte descriptors. When the LDTR is loaded,
the LDTR selector indexes an LDT descriptor
that must reside in the Global Descriptor Table
(GDT). The contents of the selected descriptor
are cached on-chip in the hidden portion of the
LDTR. The CPU does not access the GDT
again until the LDTR is reloaded. If the LDT
descriptor is modified in memory in the GDT,
the LDTR must be reloaded to update the
hidden portion of the LDTR.
When a segment register is loaded from
memory, the TI bit in the segment selector
chooses either the GDT or the LDT to locate a
segment descriptor. If TI = 1, the index portion
of the selector is used to locate a given
descriptor within the LDT. Each task in the
system may be given its own LDT, managed
by the operating system. The LDTs provide a
method of isolating a given task’s segments
from other tasks in the system.
16 15

0

Base Address

Limit

GDTR

Base Address

Limit

IDTR

Selector

LDTR

Figure 2-2 Descriptor Table Registers

ZFx86 Data Book 1.0 Rev D

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2
• Gate Descriptors that define task gates,
interrupt gates, trap gates and call gates.

Descriptors

There are three types of descriptors:
• Application Segment Descriptors that
define code, data and stack segments.
• System Segment Descriptors that define
an LDT segment or a Task State Segment
(TSS) table described later in this text.

Application Segment Descriptors are located in
either the LDT or GDT; System Segment
Descriptors can only be located in the GDT.
Dependent on gate type, gate descriptors are
located in either the GDT, LDT or Interrupt
Descriptor Table (IDT). Table 2.9 illustrates the
descriptor format for both Application Segment
Descriptors and System Segment Descriptors.

Table 2.9 Application and System Segment Descriptors
31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Memory Offset +4
BASE[31:24]

G

D

0

A
V
L

LIMIT[19:16]

P

DPL

D
T

TYPE

BASE[23:16]

Memory Offset +0
BASE[15:0]

LIMIT[15:0]

Gate Descriptors provide protection for
executable segments operating at different
privilege levels. Table 2.10 illustrates the
format for Gate Descriptors and Table 2.11
lists the corresponding bit definitions.
Task Gate Descriptors (TGD) are used to
switch the CPU’s context during a task switch.
The selector portion of the TGD locates a Task
State Segment. TGDs can be located in the
GDT, LDT or IDT tables.

Interrupt Gate Descriptors are used to enter
a hardware interrupt service routine. Trap
Gate Descriptors are used to enter exceptions
or software interrupt service routines. Trap
Gate and Interrupt Gate Descriptors can only
be located in the IDT.
Call Gate Descriptors are used to enter a
procedure (subroutine) that executes at the
same or a more privileged level. A Call Gate
Descriptor primarily defines the procedure
entry point and the procedure’s privilege level.

Table 2.10 Gate Descriptors
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

0

0

0

4

3

2

1

0

Memory Offset +4
OFFSET[31:16]

P

DPL

0

TYPE

PARAMETERS

Memory Offset +0
SELECTOR[15:0]

ZFx86 Data Book 1.0 Rev D

OFFSET[15:0]

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Table 2.11 Gate Descriptor Bit Definitions
Bit

Memory
Offset

31:16
15:0
31:16

+4
+0
+0

SELECTOR

15
14:13
11:8

+4
+4
+4

P
DPL
TYPE

4:0

+4

PARAMETERS

Name

Description

OFFSET

Offset — Used during a call gate to calculate the branch target.
Selector — Segment selector used during a call gate to calculate the
branch target.
Segment present.
Descriptor privilege level.
Segment type:
0100 = 16-bit call gate
0101 = task gate
0110 = 16-bit interrupt gate
0111 = 16-bit trap gate
1100 = 32-bit call gate
1110 = 32-bit interrupt gate
1111 = 32-bit trap gate.
Parameters — Number of 32-bit parameters to copy from the caller’s
stack to the called procedure’s stack.

Task Register

During task switching, the processor saves the
current CPU state in the TSS before starting a
new task. The TR points to the current TSS.
The TSS can be either a 386/486-type 32-bit
TSS as shown in Table 2.12 or a 286-type 16-bit
TSS type as shown on Table 2.13. An I/O
permission bit map is referenced in the 32-bit
TSS by the I/O Map Base Address.

The Task Register (TR) holds a 16-bit selector
for the current Task State Segment (TSS)
table as shown in xxx. The TR is loaded and
stored via the LTR and STR instructions,
respectively. The TR can only be accessed
during protected mode and can only be loaded
when the privilege level is 0 (most privileged).
When the TR is loaded, the TR selector field
indexes a TSS descriptor that must reside in
the Global Descriptor Table (GDT). The
contents of the selected descriptor are cached
on-chip in the hidden portion of the TR

15

0
SELECTOR

Figure 2-2 Task Register

Table 2.12 32-Bit Task State Segment (TSS) Table
31

16 15
I/O Map Base Address

0

0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

T

+64h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Selector for Task’s LDT

+60h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

GS

+5Ch

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FS

+58h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DS

+54h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SS

+50h

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CS

+4Ch

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ES

+48h

ZFx86 Data Book 1.0 Rev D

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2
Table 2.12 32-Bit Task State Segment (TSS) Table (cont.)
31

0

16 15

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EDI

+44h

ESI

+40h

EBP

+3Ch

ESP

+38h

EBX

+34h

EDX

+30h

ECX

+2Ch

EAX

+28h

EFLAGS

+24h

EIP

+20h

CR3

+1Ch

0

SS for CPL = 2

+18h

SS for CPL = 1

+10h

ESP for CPL = 2
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

+14h

ESP for CPL = 1
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

+Ch
SS for CPL = 0

+8h

Back Link (Old TSS Selector)

+0h

ESP for CPL = 0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

+4h

Note: 0 = Reserved

Table 2.13 16-Bit Task State Segment (TSS) Table
15

ZFx86 Data Book 1.0 Rev D

0
Selector for Task’s LDT

+2Ah

DS

+28h

SS

+26h

CS

+24h

ES

+22h

DI

+20h

SI

+1Eh

BP

+1Ch

SP

+1Ah

BX

+18h

DX

+16h

CX

+14h

AX

+12h

FLAGS

+10h

IP

+Eh

SS for Privilege Level 2

+Ch

SP for Privilege Level 2

+Ah

SS for Privilege Level 1

+8h

SP for Privilege Level 1

+6h

SS for Privilege Level 0

+4h

SP for Privilege Level 0

+2h

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2
Table 2.13 16-Bit Task State Segment (TSS) Table (cont.)
15

0
Back Link (Old TSS Selector)

Configuration Registers (six)
The processor provides three 8-bit Configuration Control Registers (CCR1, CCR2 and
CCR3) used to control the on-chip write-back
cache, the coprocessor interface signals and
SMM features. The processor also provides
two 8-bit internal read-only device identification registers (DIR0 and DIR1) and one 24-bit
SMM Address Region Register (SMAR). The
CCR, DIR, and SMAR registers exist in I/O
memory space and are selected by a “register
index” number as listed in ‘Table 2.14 Configuration Register Map’ on page 48.
Access to these registers is achieved by writing
the index of the register to I/O port 22h. I/O
port 23h is then used for data transfer. Each
I/O port 23h data transfer must be preceded
by an I/O port 22h register index selection,
otherwise the second and later I/O port 23h
operations are directed off-chip and produce
external I/O cycles. If the register index
number is outside the C0h-CFh, FEh-FFh
range, external I/O cycles will also occur.
The CCR1 register, Table 2.15 on page 49,
controls SMM features and enables SMM and
cache interface signals.

+0h

The CCR2 register, Table 2.16 on page 51, is
used to setup internal cache operation and
enable suspend control signals.
The CCR3 register, Table 2.17 on page 51,
controls additional SMM features.
The SMAR register, Table 2.18 on page 52, is
used to define the location and size of the
memory region associated with SMM memory
space. The starting address of the SMM
address region must be on a block size
boundary. For example, a 128 KB block is
allowed to have a starting address of 0 KB,
128 KB, 256 KB, etc. The SMM block size
must be defined for SMI# to be recognized.
‘Table 2.19 DIR0 Bit Definitions’ on page 52
contains an 8-bit value that defines the device
type.
‘Table 2.20 DIR1 Bit Definitions’ on page 52
contains additional device type information.
The upper 4 bits of DIR1 represent the stepping number of the device and the lower 4 bits
of DIR1 represent the particular revision
number of the stepping. Actual values for
DIR0 and DIR1 are shown in Table 2.1 "Initialized Register Controls" on page 34.

Table 2.14 Configuration Register Map
Register
Index

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Control Registers

CCR1 (C1h)

RSVD

NO_LOCK

MMAC

SMAC

SMI

RPL

HALT

LOCK_NW

WBAK

RSVD

RSVD

RSVD

RSVD

CCR2 (C2h)

SUSP

BWRT

BARB

WTI

CCR3 (C3h)

RSVD

RSVD

RSVD

RSVD

SMM_MODE

SMM Address Region Registers (24 bits)
CDh

A31

A30

A29

A28

A27

A26

A25

A24

CEh

A23

A22

A21

A20

A19

A18

A17

A16

CFh

A15

A14

A13

A12

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Table 2.14 Configuration Register Map (cont.)
Device ID Registers
DIR0

DEVID
7

DEVID
6

DIR1

DEVID
5

DEVID4

DEVID3

SID[3:0]

DEVID2

DEVID1

DEVID0

RID[3:0]

Note: The following register index numbers are reserved for future use: C0h through CFh and FEh, FFh.

Example

; Enable CPU warm reset (WM_RST). See Table 2.16, ‘CCR2 Bit Definitions,’ on page 51, and see ‘Configuration Registers (six)’ on
page 48. Compare North Bridge Configuration Registers in ‘I/O
Address Map’ on page 119.
mov
out
in
or
mov
mov
out
mov
out

al,
22h,
al,
al,
ah,
al,
22h,
al,
23h,

0C2h
al
23h
2
al
0C2h
al
ah
al

;
;
;
;

select CCR2
set address pointer to CCR2
read data from CCR2
or in WBAK bit Enable WM_RST

;
;
;
;

select CCR2 again (see prev page)
set address pointer to CCR2
or in bit 1 WBAK
write data to CCR2

Table 2.15 CCR1 Bit Definitions
Bit

Name

Description

7:5

RSVD

Reserved.

4

NO_LOCK

Negate LOCK# — If = 1: All bus cycles are issued with LOCK# signal negated except
page table accesses. Interrupt acknowledge cycles are executed as locked cycles
even though LOCK# is negated. With NO_LOCK set, previously noncacheable locked
cycles are executed as unlocked cycles and, therefore, may be cached. This results in
higher CPU performance.

3

MMAC

Main Memory Access — If = 1: All data accesses which occur within an SMI service
routine (or when SMAC = 1) access main memory instead of SMM memory space.
If = 0: No effect on access.

2

SMAC

System Management Memory Access —
If = 1: Any access to addresses within the SMM memory space cause external bus
cycles to be issued with SMADS# output active. SMI# input is ignored.
If = 0: No effect on access.

1

SMI

Enable SMM Signals —
If = 1: SMI# input/output signal and SMADS# output signal are enabled.
If = 0: SMI# input signal ignored and SMADS# output signal floats.

0

RPL

Enable RPL Signals —
If = 1: Enable output signals RPLSET(1-0) and RPLVAL#.
If = 0: Output signals RPLSET(1-0) and RPLVAL# float.

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Table 2.15 CCR1 Bit Definitions (cont.)
Bit

Name

Description

Note: Bits [4:0] are cleared to 0 at reset.

ZFx86 Data Book 1.0 Rev D

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Table 2.16 CCR2 Bit Definitions
Bit

Name

Description

7

SUSP

Enable Suspend Signals —
If = 1: SUSP# input and SUSPA# output are enabled.
If = 0: SUSP# input is ignored and SUSPA# output floats.

6

BWRT

Enable Burst Write Cycles —
If = 1: Enables use of 16-byte burst write-back cycles.

5

BARB

Enable Cache Coherency on Bus Arbitration —
If = 1: Enable write-back of all dirty cache data when HOLD is requested and prior to
asserting HLDA.

4

WT1

Write-Through Region 1 —
If = 1: Forces all writes to the 640 KB to 1 MB address region that hit in the on-chip
cache to be issued on the external bus.

3

HALT

Suspend on HALT —
If = 1: CPU enters suspend mode following execution of a HALT instruction.

2

LOCK_NW

1

WBAK

Enable Write-Back Cache Interface Signals —
If = 1: Enable INVAL and WM_RST input signals, and HITM# output signal.
If = 0: INVAL and WM_RST input signals are ignored, and HITM# output signal floats.

0

RSVD

Reserved.

LOCK NW Bit —
If = 1: Prohibits changing the state of the NW bit in CR0.

Note: All bits are cleared to zero at reset.

Table 2.17 CCR3 Bit Definitions
Bit

Name

Description

7:4

RSVD

Reserved.

3

SMM_MODE

SL-enhanced compatible mode.
If = 1: SL compatible mode enabled.
If = 0: SL compatible mode disabled.
NOTE: Once the SMI_Lock bit is set, the CPU must be reset in order to modify
SMI_Lock and SMM_Mode.

2

RSVD

Reserved

1

NMIEN

NMI Enable —
If = 1: NMI is enabled during SMM.
If = 0: NMI is not recognized during SMM.

0

SMI_LOCK

SMM Register Lock —
If = 1: the following SMM control bits cannot be modified:
CCR1 bits: 1, 2, and 3
CCR3 bit: 1
all SMAR bits
While operating within an SMI handler, these SMM control bits can be modified.
Once set, the SMI_LOCK bit can only be cleared by asserting the RESET signal.

Note: Bits [1:0] are cleared to zero at reset.

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Table 2.18 SMAR Size Field
Bits [3:0]

Block Size

Bits [3:0]

Block Size

0h

Disabled

8h

512 KB

1h

4 KB

9h

1 MB

2h

8 KB

Ah

2 MB

3h

16 KB

Bh

4 MB

4h

32 KB

Ch

8 MB

5h

64 KB

Dh

16 MB

6h

128 KB

Eh

32 MB

7h

256 KB

Fh

4 KB (Same as 1h)

Table 2.19 DIR0 Bit Definitions
Bit

Name

7:0

DEVID[7:0]

Description
Device Identification —
DEVID[7:0] bits define the CPU type. These bits are read only.
processor = xxh

Table 2.20 DIR1 Bit Definitions
Bit

Name

7:4

SID[3:0]

Stepping Identification —
SID[3:0] are read only and indicate device stepping number.

3:0

RID[3:0]

Revision Identification —
RID[3:0] are read only and indicate device revision number.

ZFx86 Data Book 1.0 Rev D

Description

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A31-A2
A20M#

ADS#

AHOLD

BE3#-BE0#

BOFF#

BLAST#

BRDY#

BREQ

BS16#, BS8#

D31-D0

CLK

D/C#

EADS#

1
1

FLUSH#
IGNNE#

2

DP3-DP0

Processor
Input and Output
Signals

2

FERR#

1

HITM#

INTR

HLDA

INVAL

1

LOCK#

HOLD

M/IO#

KEN#

1

1

NMI

PCD
PCHK#

RDY#

PLOCK#

RESET

1

PWT

SMI#

4

1

RPLSET(1-0)

SUSP#

3

1

RPLVAL#

4

SMADS#

3

SUSPA#

UP#
WM_RST

5

W/R#
1=
2=
3=
4=
5=

Cache Interface
Coprocessor Interface
Power Management
System Management Mode
Reset Input

Figure 2-3 Processor Internal I/O Interface Signals

ZFx86 Data Book 1.0 Rev D

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Debug Registers

DR7 that specify the memory access type
associated with the breakpoint.

Six debug registers (DR0-DR3, DR6 and
DR7), shown in Table 2.21, support debugging
on the processor. Memory addresses loaded
in the debug registers, referred to as “breakpoints”, generate a debug exception when a
memory access of the specified type occurs to
the specified address. A breakpoint can be
specified for a particular kind of memory
access such as a read or a write. Code and
data breakpoints can also be set allowing
debug exceptions to occur whenever a given
data access (read or write) or code access
(execute) occurs. The size of the debug target
can be set to 1-, 2-, or 4-bytes. The debug
registers are accessed via MOV instructions
which can be executed only at privilege level
0.

The R/W field can be used to specify instruction execution as well as data access breakpoints. Instruction execution breakpoints are
always taken before execution of the instruction that matches the breakpoint.
The Debug Status Register (DR6) reflects
conditions that were in effect at the time the
debug exception occurred. The contents of the
DR6 register are not automatically cleared by
the processor after a debug exception occurs
and, therefore, should be cleared by software
at the appropriate time. Table 2.22 on page 55
lists the field definitions for the DR6 and DR7
registers.
Code execution breakpoints may also be
generated by placing the breakpoint instruction
(INT 3) at the location where control is to be
regained. The single-step feature may be
enabled by setting the TF flag in the EFLAGS
register. This causes the processor to perform
a debug exception after the execution of every
instruction

Debug Address Registers (DR0-DR3) contain
the linear address for one of four possible
breakpoints. Each breakpoint is specified by
bits in Debug Control Register (DR7). For
each breakpoint address in DR0-DR3, there
are corresponding fields (L, R/W, and LEN) in

Table 2.21 Debug Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

DR7 Register
LEN3

R/W3

LEN2

R/W2

LEN1

R/W1

LEN0

R/W0

0

0

G
D

0

0

1

G
E

L
E

G
3

L
3

G
2

L
2

G
1

L
1

G
0

L
0

0

0

0

0

0

0

B
T

B
S

0

0

1

1

1

1

1

1

1

1

B
3

B
2

B
1

B
0

DR6 Register
0

0

0

0

0

0

0

0

0

0

DR3 Register
Breakpoint 3 Linear Address
DR2 Register
Breakpoint 2 Linear Address
DR1 Register
Breakpoint 1 Linear Address
DR0 Register
Breakpoint 0 Linear Address
Note: All bits marked as 0 or 1 are reserved and should not be modified.

ZFx86 Data Book 1.0 Rev D

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Table 2.22 DR6 and DR7 Field Definitions
Register

Field

Number
Of Bits

DR6

Bi

1

BT

1

BS

1

R/Wi

2

LENi

2

Gi

1

Li

1

GD

1

DR7

Description
Bi is set by the processor if the conditions described by DRi, R/Wi, and LENi
occurred when the debug exception occurred, even if the breakpoint is not
enabled via the Gi or Li bits.
BT is set by the processor before entering the debug handler if a task switch
has occurred to a task with the T bit in the TSS set.
BS is set by the processor if the debug exception was triggered by the singlestep execution mode (TF flag in EFLAGS set).
Applies to the DRi breakpoint address register:
00 - Break on instruction execution only
01 - Break on data writes only
10 - Not used
11 - Break on data reads or writes.
Applies to the DRi breakpoint address register:
00 - One byte length
01 - Two byte length
10 - Not used
11 - Four byte length.
If set to a 1, breakpoint in DRi is globally enabled for all tasks and is not
cleared by the processor as the result of a task switch.
If set to 1, breakpoint in DRi is locally enabled for the current task and is
cleared by the processor as the result of a task switch.
Global disable of debug register access. GD bit is cleared whenever a debug
exception occurs.

Test Registers
The five test registers, shown in Table 2.23,
are used to test the CPU’s Translation Lookaside Buffer (TLB) and on-chip cache. TR6 and
TR7 are used for TLB testing, and TR3-TR5
are used for cache testing. Table 2.24 on page
56 lists the bit definitions for the TR6 and TR7
registers.
The processor TLB is a four-way set associative memory with eight entries per set. Each
TLB entry consists of a 24-bit tag and 20-bit
data. The 24-bit tag represents the high-order
20 bits of the linear address, a valid bit, and
three attribute bits. The 20-bit data portion
represents the upper 20 bits of the physical
address that corresponds to the linear
address.

ZFx86 Data Book 1.0 Rev D

The TLB Test Control Register (TR6) contains
a command bit, the upper 20 bits of a linear
address, a valid bit and the attribute bits used
in the test operation. The contents of TR6 is
used to create the 24-bit TLB tag during both
write and read (TLB lookup) test operations.
The command bit defines whether the test
operation is a read or a write.
The TLB Test Data Register (TR7) contains
the upper 20 bits of the physical address (TLB
data field), three LRU bits and a control bit.
During TLB write operations, the physical
address in TR7 is written into the TLB entry
selected by the contents of TR6. During TLB
lookup operations, the TLB data selected by
the contents of TR6 is loaded into TR7.

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Table 2.23 Test Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

TLB LRU

0

0 PL

3

2

1

0

REP

0

0

0

0

C

TR7 Register
P P
C W
D T

TLB Physical Address

TR6 Register
TLB Linear Address

V

D D# U U# R R# 0

0

TR5 Register
RSVD

Line Selection

Set/
DWORD

CTL

TR4 Register
Cache Tag Address

0

V

Cache
LRU Bits

Dirty Bits

RSVD

0

TR3 Register
Cache Data

Table 2.24 TR7 and TR6 Bit Definitions
Register
Name

Bit

TR7

31:12

11
10
9:7

4

3:2

ZFx86 Data Book 1.0 Rev D

Description
Physical address.
TLB lookup: data field from the TLB.
TLB write: data field written into the TLB.
Page-level cache disable bit (PCD).
Corresponds to the PCD bit of a page table entry.
Page-level cache write-through bit (PWT).
Corresponds to the PWT bit of a page table entry.
LRU bits.
TLB lookup: LRU bits associated with the TLB entry prior to the TLB lookup.
TLB write: ignored.
PL bit.
TLB lookup: If = 1, read hit occurred. If = 0, read miss occurred.
TLB write: If = 1, REP field is used to select the set. If = 0, the pseudo-LRU
replacement algorithm is used to select the set.
Set selection (REP).
TLB lookup: If PL = 1, set in which the tag was found. If PL = 0, undefined data.
TLB write: If PL = 1, selects one of the four sets for replacement. If PL = 0, ignored.

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Table 2.24 TR7 and TR6 Bit Definitions
Register
Name

Bit

TR6

31:12

11

10:9
8:7
6:5
0

Description
Linear address.
TLB lookup: The TLB is interrogated per this address. If one and only one match occurs
in the TLB, the rest of the fields in TR6 and TR7 are updated per the matching
TLB entry.
TLB write: A TLB entry is allocated to this linear address.
Valid bit (V).
TLB write: If set, indicates that the TLB entry contains valid data.
If clear, target entry is invalidated.
Dirty attribute bit and its complement (D, D#). Refer to Table 2-17 on page 30.
User/supervisor attribute bit and its complement (U, U#). Refer to Table 2-17 on page
30.
Read/write attribute bit and its complement (R, R#). Refer to Table 2-17 on page 30.
Command bit (C).
If = 0: TLB write.
If = 1: TLB lookup.

Table 2.25 TR6 Attribute Bit Pairs
Bit
(D, U or R)

Bit Complement (D#,
U#, or R#)

0

0

0

1

1

0

1

1

Effect On TLB Lookup

Undefined.
Match if D, U or R bit = 0.
Clear the bit.
Match if D, U or R bit = 1.
Set the bit.
Match if D, U or R bit = either 1 or 0. Undefined.

Do not match.

Cache Test Registers
The processor 8 KB on-chip cache is a fourway set associative memory that can be
configured as either write-back or writethrough. Each cache set contains 128 entries.
Each entry consists of a 21-bit tag address, a
16-byte data field, a valid bit, and four dirty
bits.
The 21-bit tag represents the high-order 21
bits of the physical address. The 16-byte data
represents the 16 bytes of data currently in
memory at the physical address represented
by the tag. The valid bit indicates whether the
data bytes in the cache actually contain valid
data. The four dirty bits indicate if the data
bytes in the cache have been modified internally without updating external memory (writeback configuration). Each dirty bit indicates

ZFx86 Data Book 1.0 Rev D

Effect On TLB Write

the status for one double-word (4 bytes) within
the 16-byte data field.
For each line in the cache there are three LRU
bits that indicate which of the four sets was
most recently accessed. A line is selected
using bits10-4 of the physical address. Figure
2-4 illustrates the processor cache architecture.
The processor contains three test registers
that allow testing of its internal cache. Bit definitions for the cache test registers are shown
in Table 2.26. Using these registers, cache
writes and reads may be performed.
Cache test writes cause the data in the cache
fill buffer to be written to the selected set and
entry in the cache. Data must be written to
TR3 (32-bit register) four times in order to fill
the cache fill buffer. Once the cache fill buffer

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has been loaded, a cache test write can be
performed. For data to be written to the allocated entry, the valid bit for the entry must be
set prior to the write of the data.

cache flush buffer. Once the buffer has been
loaded, data must be read from TR3 four
times in order to empty the cache flush buffer.
For proper operation, cache tests should be
performed only when the cache is disabled
(CD bit in CR0 = 1).

Cache test reads cause the data in the
selected set and entry to be loaded into the
Line
Address

SET 0

SET 1

SET 2

LRU

SET 3

127
126
A10-A4

D
E
C
O
D
E
0
153

0

153

0

153

0

153

0

2

0

= Cache Entry (154 bits)
Tag Address (21 bits)
Data (128 bits)
Valid Status (1 bit)
Dirty Status (4 bits)

Figure 2-4 Processor Cache Architecture

ZFx86 Data Book 1.0 Rev D

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Table 2.26 TR3-TR5 Bit Definitions
Bit

Name

Description

31:0

TR3

Cache data —
Flush buffer read: data accessed from the cache flush buffer.
Fill buffer write: data to be written into the cache fill buffer.

31:12

TR4

Upper Tag Address —
Cache read: upper 21 bits of tag address of the selected entry.
Cache write: data written into the upper 21 bits of the tag address of
the selected entry.

10

Valid Bit —
Cache read: valid bit for the selected entry.
Cache write: data written into the valid bit for the selected entry.

9:7

LRU Bits —
Cache read: the LRU bits for the selected line.
xx1 = Set 0 or Set 1 most recently accessed.
xx0 = Set 2 or Set 3 most recently accessed.
x1x = Most recent access to Set 0 or Set 1 was to Set 0.
x0x = Most recent access to Set 0 or Set 1 was to Set 1.
1xx = Most recent access to Set 2 or Set 3 was to Set 2.
0xx = Most recent access to Set 2 or Set 3 was to Set 3.
Cache write: ignored.

6:3

Dirty Bits —
Cache read: the dirty bits for the selected entry (one bit per DWORD).
Cache write: data written into the dirty bits for the selected entry.

10:4

TR5

Line Selection —
Physical address bits 10:4 used to select one of 128 lines.

3:2

Set/DWORD Selection —
Cache read: selects which of the four sets is used as the source for data
transferred to the cache flush buffer.
Cache write: selects which of the four sets is used as the destination for data
transferred from the cache fill buffer.
Flush buffer read: selects which of the four Words in the flush buffer is
loaded into TR3.
Fill buffer write: selects which of the four DWORDs in TR3 is written to the fill buffer.

1:0

Control Bits —
If = 00: flush read or fill buffer write. Writing to TR3 fill buffer write. Reading TR3 initiates flush buffer read.
If = 01: cache write.
If = 10: cache read.
If = 11: cache flush.

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2.2.4. Address Spaces

2.2.4.2. Memory Address Space

The CPU can directly address either memory
or I/O space. Figure 2-5 illustrates the range
of addresses available for memory address
space and I/O address space. For the
processor, the addresses for physical memory
range between 0000 0000h and FFFF
FFFFh (4 GB). However, the address bus
capability of the ZFx86 limits external memory
address space to 256 MB.The accessible I/O
addresses space ranges between 0000 0000h
and 0000 FFFFh (64 KB). The processor does
not use coprocessor communication space in
upper I/O space between 8000 00F8h and
8000 00FFh as do the 386-style CPU’s. The
I/O locations 22h and 23h are used for the
processor configuration register access.

The processor directly addresses up to 4 GB
of physical memory. However, the address
bus capability of the ZFx86 limits external
memory address space to 256 MB. Memory
address space is accessed as bytes, WORDS
(16-bits) or DWORDs (32-bits). WORDS and
DWORDs are stored in consecutive memory
bytes with the low-order byte located in the
lowest address. The physical address of a
word or DWORD is the byte address of the
low-order byte.

2.2.4.1. I/O Address Space
The processor I/O address space is accessed
using IN and OUT instructions to addresses
referred to as “ports”. The accessible I/O
address space is 64 KB and can be accessed
as 8-bit, 16-bit or 32-bit ports. The execution
of any IN or OUT instruction causes the M/IO#
signal to be driven low, thereby selecting the
I/O space instead of memory space.
The processor configuration registers reside
within the I/O address space at port addresses
22h and 23h and are accessed using standard
IN and OUT instructions. The configuration
registers are modified by writing the index of
the configuration register to port 22h, then
transferring the data through port 23h.
Accesses to the on-chip configuration registers do not generate external I/O cycles. Each
port 23h operation must be preceded by a port
22h write with a valid index value. Otherwise,
the second and later port 23h operations are
directed off-chip and generate external I/O cycles
without modifying the on-chip configuration
registers. Writes to port 22h outside of the
processor index range (C0h-CFh and FEhFFh) result in external I/O cycles and do not
affect the on-chip configuration registers.
Reads of port 22h are always directed off-chip.

ZFx86 Data Book 1.0 Rev D

Memory can be addressed using nine different
addressing modes. These addressing modes
are used to calculate an offset address often
referred to as an effective address. Depending
on the operating mode of the CPU, the offset
is then combined using memory management
mechanisms to create a physical address that
actually addresses the physical memory
devices.
Memory management mechanisms on the
CPU consist of segmentation and paging.
Segmentation allows each program to use
several independent, protected address
spaces. Paging supports a memory
subsystem that simulates a large address
space using a small amount of RAM and disk
storage for physical memory. Either or both of
these mechanisms can be used for management of the processor memory address space

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Accessible
Programmed
I/O Space

Physical
Memory Space
FFFF FFFFH

FFFF FFFFH

Not
Accessible
Physical Memory
4 GB
Allowed Memory
256 MB

Processor
Configuration
Register I/O
Space

0000 FFFFh
64 KB

0000 0000h

0000 0023h
0000 0022h

0000 0000h

Figure 2-5 Memory and I/O Address Spaces

Offset Mechanism
The offset mechanism computes an offset
(effective) address by adding together up to
three values: a base, an index and a displacement. The base, if present, is the value in one
of eight 32-bit general registers at the time of
the execution of the instruction. The index, like
the base, is a value that is contained in one of
the 32-bit general registers (except the ESP
register) when the instruction is executed. The
index differs from the base in that the index is
first multiplied by a scale factor of 1, 2, 4 or 8
before the summation is made. The third
component added to the memory address
calculation is the displacement which is a
value of up to 32-bits in length supplied as part
of the instruction. See Figure 2-6 "Offset
Address Calculation".
Nine valid combinations of the base, index,
scale factor and displacement can be used
with the processor instruction set. These
combinations are listed in Table 2.27. The

ZFx86 Data Book 1.0 Rev D

base and index both refer to contents of a
register as indicated by [Base] and [Index]
Index

Base

Displacement

Scaling
x1, x2, x4, x8

+
Offset Address
(Effective Address)

Figure 2-6 Offset Address Calculation

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Table 2.27 Memory Addressing Modes
Addressing Mode

Base

Index

Scale
Factor

Direct

Displacement
x

Register Indirect

x

Based

x

Offset Address (OA) Calculation
OA = DP
OA = [BASE]

Index

x

Scaled Index

x

Based Index

x

x

Based Scaled Index

x

x

Based Index with
Displacement

x

x

Based Scaled Index
with Displacement

x

x

x

x

OA = [BASE] + DP

x

OA = [INDEX] + DP

x

OA = ([INDEX] * SF) + DP
OA = [BASE] + [INDEX]
OA = [BASE] + ([INDEX] * SF)

x

x

Real Mode Memory Addressing
In real mode operation, the CPU only
addresses the lowest 1 MB of memory. To
calculate a physical memory address, the 16bit segment base address located in the
selected segment register is multiplied by 16
and then the 16-bit offset address is added.
The resulting 20-bit address is then extended
with twelve zeros in the upper address bits to
create the 32-bit physical address. Figure 2-13
illustrates the real mode address calculation.
The addition of the base address and the
offset address may result in a carry. Therefore,
the resulting address may actually contain up
to 21 significant address bits that can address
memory in the first 64 KB above 1 MB.

x

OA = [BASE] + [INDEX] + DP

x

OA = [BASE] + ([INDEX] * SF) + DP

• Optional Paging Mechanism that translates a linear address to the physical
memory address.
The offset and base address are added
together to produce the linear address. If paging is not used, the linear address is used as
the physical memory address. If paging is
enabled, the paging mechanism is used to
translate the linear address into the physical
address. The offset mechanism is described in
‘Offset Mechanism’ on page 61. and applies to
both real and protected mode. The selector
and paging mechanisms are described in the
following paragraphs.

Protected Mode Memory Addressing
In protected mode three mechanisms calculate
a physical memory address:
• Offset Mechanism that produces the offset
or effective address as in real mode.
• Selector Mechanism that produces the
base address.

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Offset Mechanism

Offset Address
Linear Address = Physical Address

+
Selected Segment
Register

X 16

Figure 2-7 Real Mode Address Calculation

Offset Address
Offset Mechanism

+
Selector
Mechanism

Linear Address

Optional
Paging Mechanism

Physical
Memory
Address

Base Address

Figure 2-8 Protected Mode Address Calculation

Selector Mechanism
Memory is divided into an arbitrary number of
segments, each containing less than the 232
byte (4 GB) maximum.
The six segment registers (CS, DS, SS, ES,
FS and GS) each contain a 16-bit selector that
is used when the register is loaded to locate a
segment descriptor in either the global
descriptor table (GDT) or the local descriptor
table (LDT). The segment descriptor defines
the base address, limit and attributes of the
selected segment and is cached on the
processor as a result of loading the selector.

address in the hidden portion of the segment
register to the offset address. If paging is not
enabled, this linear address is used as the
physical memory address. Figure 2-9
"Selector Mechanism" illustrates the operation
of the selector mechanism.

The cached descriptor contents are not visible
to the programmer. When a memory reference
occurs in protected mode, the linear address
is generated by adding the segment base

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15
Selector
Load

0
Index

Segment
Descriptor

TI

RPL

TI = 0

TI = 1

(Accessed
Segment
Register)

Segment
Descriptor

Local Descriptor Table

Global Descriptor Table
Cache Update
From Memory

Selector

Descriptor
Cache

Base Address

Figure 2-9 Selector Mechanism

Paging Mechanism
The paging mechanism supports a memory
subsystem that simulates a large address
space with a small amount of RAM and disk
storage. The paging mechanism either translates a linear address to its corresponding
physical address or generates an exception if
the required page is not currently present in
RAM. When the operating system services the
exception, the required page is loaded into
memory and the instruction is then restarted.
Pages are either 4 KB or 1 MB in size. The
CPU defaults to 4 KB pages that are aligned to
4 KB boundaries.
A page is addressed by using two levels of
tables as illustrated in Figure 2-10 on page 65.
The upper 10 bits of the 32-bit linear address
are used to locate an entry in the page directory table. The page directory table acts as a
32-bit master index to up to 1 KB individual
second-level page tables. The selected entry
in the page directory table, referred to as the

ZFx86 Data Book 1.0 Rev D

directory table entry, identifies the starting
address of the second-level page table. The
page directory table itself is a page and is,
therefore, aligned to a 4 KB boundary. The
physical address of the current page directory
table is stored in the CR3 control register, also
referred to as the Page Directory Base
Register (PDBR).
Bits 21:12 of the 32-bit linear address, the
Page Table Index, locate a 32-bit entry in the
second-level page table. The Page Table
Entry (PTE) contains the base address of the
page frame. The second-level page table
addresses up to 1 KB individual page frames.
A second-level page table is 4 KB in size and
is itself a page. The lower 12 bits of the 32-bit
linear address, the Page Frame Offset (PFO),
locate the desired physical data within the
page frame.
Since the page directory table can point to 1
KB page tables, and each page table can point
to 1 KB of page frames, a total of 1 MB of page

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frames can be implemented. Since each page
frame contains 4 KB, up to 4 GB of virtual
memory can be addressed by the processor
with a single page directory table.

In addition to the base address of the page
table or the page frame, each directory table
entry or page table entry contains attribute bits
and a Present (P) Flag bit as illustrated in
Figure 2-10 and listed in Table 2.28.

Linear Address
31

22 21

12 11

0

Page Table Index
(PTI)

Directory Table Index
(DTI)

Directory Table

Page Frame Offset
(PFO)

Page Table
4 KB

Page Frame
4 KB

4 KB

Physical Data
PTE
DTE
0

0
CR3

0

Control Register

Figure 2-10 Paging Mechanism

If the P bit is set in the DTE, the page table is
present and the appropriate page table entry
is read. If P = 1 in the corresponding PTE
(indicating that the page is in memory), the
accessed and dirty bits are updated, if necessary, and the operand is fetched. Both
accessed bits are set (DTE and PTE), if
necessary, to indicate that the table and the
page have been used to translate a linear
address. The dirty bit (D) is set before the first
write is made to a page.
The P bits must be set to validate the
remaining bits in the DTE and PTE. If either of
the P bits is not set, a page fault is generated
when the DTE or PTE is accessed. If P = 0,
the remaining DTE/PTE bits are available for
use by the operating system. For example, the

ZFx86 Data Book 1.0 Rev D

operating system can use these bits to record
where on the hard disk the pages are located.
A page fault is also generated if the memory
reference violates the page protection
attributes.

Translation Look-Aside Buffer
The translation look-aside buffer (TLB) is a
cache for the paging mechanism and replaces
the two-level page table lookup procedure for
TLB hits. The TLB is a four-way set associative 32-entry page table cache that automatically keeps the most commonly used page
table entries in the processor. The 32-entry
TLB, coupled with a 4 KB page size, results in
coverage of 128 KB of memory addresses.

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The TLB must be flushed when entries in the
page tables are changed. The TLB is flushed
whenever the CR3 register is loaded. An indi-

vidual entry in the TLB can be flushed using
the INVLPG instruction.

Table 2.28 Directory and Page Table Entry (DTE and PTE) Bit Definitions
Bit

Name

Description

31:12

Base Address

11:9

--

8:7

RSVD

6

D

Dirty Bit — If set, indicates that a write access has occurred to the page (PTE
only; undefined in DTE).

5

A

Accessed Flag — If set, indicates that a read access or write access has
occurred to the page.

4

PCD

Page Caching Disable Flag — If set, indicates that the page is not cacheable
in the on-chip cache.

3

PWT

Page Write-Through Flag — If set, indicates that writes to the page or page
tables that hit in the on-chip cache must update both the cache and external
memory.

2

U/S

User/Supervisor Attribute — If set (user), page is accessible at privilege
level 3. If clear (supervisor), page is accessible only when CPL ≤ 2.

1

W/R

Write/Read Attribute — If set (write), page is writable. If clear (read), page is
read only.

0

P

Present Flag — If set, indicates that the page is present in RAM, and validates the remaining DTE/PTE bits. If clear, indicates that the page is not
present in memory and the remaining DTE/PTE bits can be used by the programmer.

Specifies the base address of the page or page table.
Undefined and available to the programmer.
Reserved and not available to the programmer.

2.2.5. Interrupts and Exceptions

2.2.5.1. Interrupts

The processing of either an interrupt or an
exception changes the normal sequential flow
of a program by transferring program control
to a selected service routine. Except for SMM
interrupts, the location of the selected service
routine is determined by one of the interrupt
vectors stored in the interrupt descriptor table.

External events can interrupt normal program
execution by using one of the three interrupt
signals on the CPU.

True interrupts are hardware interrupts and
are generated by signal sources external to
the CPU. All exceptions (including so-called software interrupts) are produced internally by the
CPU.

ZFx86 Data Book 1.0 Rev D

• Non-maskable Interrupt (NMI signal)
• Maskable Interrupt (INTR signal)
• SMM Interrupt (SMI# signal).
For most interrupts, program transfer to the
interrupt routine occurs after the current
instruction has been completed. When the
execution returns to the original program, it
begins immediately following the interrupted
instruction.

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The NMI interrupt cannot be masked by software and always uses interrupt vector 2 to
locate its service routine. Since the interrupt
vector is fixed and is supplied internally, no
interrupt acknowledge bus cycles are
performed. This interrupt is normally reserved
for unusual situations such as parity errors
and has priority over INTR interrupts.

program execution is passed to an SMI
service routine which runs in SMM address
space reserved for this purpose. The
remainder of this section does not apply to the
SMM interrupts. SMM interrupts are described
in greater detail in Section 2.2.5.4. ‘Interrupt
and Exception Priorities’ on page 69.

Once NMI processing has started no additional NMIs are processed until an IRET
instruction is executed, typically at the end of
the NMI service routine. If NMI is re-asserted
prior to execution of the IRET instruction, one
and only one NMI rising edge is stored and
then processed after execution of the next
IRET.

Exceptions are generated by an interrupt
instruction or a program error. Exceptions are
classified as traps, faults or aborts depending
on the mechanism used to report them and
the ability to restart of the instruction which
first caused the exception.

During the NMI service routine, maskable
interrupts may be enabled. If an unmasked
INTR occurs during the NMI service routine,
the INTR is serviced and execution returns to
the NMI service routine following the next IRET.
If a HALT instruction is executed within the
NMI service routine, the processor restarts
execution only in response to RESET, an
unmasked INTR or an SMM interrupt. NMI
does not restart CPU execution under this
condition.
The INTR interrupt is unmasked when the
Interrupt Enable Flag (IF) in the EFLAGS
register is set to 1. With the exception of string
operations, INTR interrupts are acknowledged
between instructions. Long string operations
have interrupt windows between memory
moves that allow INTR interrupts to be
acknowledged.

2.2.5.2.Exceptions

A Trap Exception is reported immediately
following the instruction that generated the
trap exception. Trap exceptions are generated by execution of a software interrupt
instruction (INTO, INT 3, INT n, BOUND), by a
single- step operation or by a data breakpoint.
Software interrupts can be used to simulate
hardware interrupts. For example, an INT n
instruction causes the processor to execute
the interrupt service routine pointed to by the
nth vector in the interrupt table. Execution of
the interrupt service routine occurs regardless
of the state of the IF flag in the EFLAGS
register.
The one byte INT 3, or breakpoint interrupt
(vector 3), is a particular case of the INT n
instruction. By inserting this one byte instruction in a program, the user can set breakpoints
in the code that can be used during debug.

When an INTR interrupt occurs, the CPU
performs two locked interrupt acknowledge
bus cycles. During the second cycle, the CPU
reads an 8-bit vector which is supplied by an
external interrupt controller. This vector selects
which of the 256 possible interrupt handlers
will be executed in response to the interrupt.

Single-step operation is enabled by setting the
TF bit in the EFLAGS register. When TF is set,
the CPU generates a debug exception (vector
1) after the execution of every instruction.
Data breakpoints also generate a debug
exception and are specified by loading the
debug registers (DR0-DR7) with the appropriate values.

The SMM interrupt has higher priority than
either INTR or NMI. After SMI# is asserted,

A Fault Exception is reported prior to completion of the instruction that generated the

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exception. By reporting the fault prior to
instruction completion, the CPU is left in a
state which allows the instruction to be
restarted and the effects of the faulting instruction to be nullified. Fault exceptions include
divide-by-zero errors, invalid opcodes, page
faults and coprocessor errors. Debug exceptions (vector 1) are also handled as faults
(except for data breakpoints and single-step
operations). After execution of the fault
service routine, the instruction pointer points
to the instruction that caused the fault.
An Abort Exception is a type of fault exception
that is severe enough that the CPU cannot
restart the program at the faulting instruction.
The double fault (vector 8) is the only abort
exception that occurs on the processor.

2.2.5.3.Interrupt Vectors
When the CPU services an interrupt or exception, the current program’s instruction pointer
and flags are pushed onto the stack to allow
resumption of execution of the interrupted
program. In protected mode, the processor
also saves an error code for some exceptions.
Program control is then transferred to the
interrupt handler (also called the interrupt
service routine). Upon execution of an IRET at
the end of the service routine, program execution resumes at the instruction pointer address
saved on the stack when the interrupt was
serviced.

Interrupt Vector Assignments
Each interrupt (except SMI#) and exception is
assigned one of 256 interrupt vector numbers
listed in Table 2.29. The first 32 interrupt
vector assignments are defined or reserved.
INT instructions acting as software interrupts
may use any of interrupt vectors, 0 through
255.
The non-maskable hardware interrupt (NMI) is
assigned vector 2. Illegal opcodes including

ZFx86 Data Book 1.0 Rev D

faulty FPU instructions will cause an invalid
opcode fault, Interrupt Vector 6.
Table 2.29 Interrupt Vector Assignments
Interrupt
Vectors

Function

Exception
Type

0

Divide error

FAULT

1

Debug exception

TRAP/FAULT
(see note)

2

NMI interrupt

3

Breakpoint

TRAP

4

Interrupt on overflow

TRAP

5

BOUND range exceeded

FAULT

6

Invalid opcode

FAULT

7

Device not available

FAULT

8

Double fault

ABORT

9

Reserved

10

Invalid TSS

FAULT

11

Segment not present

FAULT

12

Stack fault

FAULT

13

General protection fault

TRAP/FAULT

14

Page fault

FAULT

15

Reserved

16

FPU error

FAULT

17

Alignment check exception

FAULT

18-31

Reserved

32-255

Maskable hardware interrupts

TRAP

0-255

Programmed interrupt

TRAP

Note: Data breakpoints and single steps are traps. All are debug
exceptions are faults.

In response to a maskable hardware interrupt
(INTR), the processor issues interrupt
acknowledge bus cycles used to read the
vector number from external hardware. These
vectors should be in the range 32-255 as
vectors 0-31 are pre-defined.

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Interrupt Descriptor Table
The interrupt vector number is used by the
CPU to locate an entry in the interrupt
descriptor table (IDT). In real mode, each IDT
entry consists of a 4-byte far pointer to the
beginning of the corresponding interrupt
service routine. In protected mode, each IDT
entry is an 8-byte descriptor. The Interrupt
Descriptor Table Register (IDTR) specifies the
beginning address and limit of the IDT.
Following RESET, the IDTR contains a base
address of 0h with a limit of 3FFh.
The IDT can be located anywhere in physical
memory as determined by the IDTR register.
The IDT may contain different types of
descriptors: interrupt gates, trap gates and
task gates. Interrupt gates are used primarily
to enter a hardware interrupt handler. Trap
gates are generally used to enter an exception
handler or software interrupt handler. If an
interrupt gate is used, the Interrupt Enable
Flag (IF) in the EFLAGS register is cleared
before the interrupt handler is entered. Task
gates are used to make the transition to a new
task.

2.2.5.4. Interrupt and Exception Priorities

exceptions and hardware interrupts. The priorities for competing interrupts and exceptions
are listed in Table 2-31 “Interrupt and Exception Priorities”. SMM interrupts always take
precedence. Debug traps for the previous
instruction and next instructions are handled
as the next priority. When NMI and maskable
INTR interrupts are both detected at the same
instruction boundary, the processor services
the NMI interrupt first.
The processor checks for exceptions in
parallel with instruction decoding and execution. Several exceptions can result from a
single instruction. However, only one exception is generated upon each attempt to
execute the instruction. Each exception
service routine should make the appropriate
corrections to the instruction and then restart
the instruction. In this way, exceptions can be
serviced until the instruction executes properly.
The processor supports instruction restart
after all faults, except when an instruction
causes a task switch to a task whose task
state segment (TSS) is partially not present. A
TSS can be partially not present if the TSS is
not page aligned and one of the pages where
the TSS resides is not currently in memory.

As the processor executes instructions, it
follows a consistent policy for prioritizing
Table 2.30 Interrupt and Exception Priorities
Priority

Description

Notes

0

SMM hardware interrupt.

SMM interrupts are caused by SMI# asserted and
always have highest priority.

1

Debug traps and faults from previous instruction.

Includes single-step trap and data breakpoints
specified in the debug registers.

2

Debug traps for next instruction.

Includes instruction execution breakpoints specified in the debug registers.

3

Non-maskable hardware interrupt.

Caused by NMI asserted.

4

Maskable hardware interrupt.

Caused by INTR asserted and IF = 1.

5

Faults resulting from fetching the next instruction.

Includes segment not present, general protection
fault and page fault.

6

Faults resulting from instruction decoding.

Includes illegal opcode, instruction too long, or
privilege violation.

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Table 2.30 Interrupt and Exception Priorities
Priority

Description

Notes

7

WAIT instruction and TS = 1 and MP = 1.

Device not available. Exception generated.

8

ESC instruction and EM = 1 or TS = 1.

Device not available. Exception generated.

9

Floating point error exception.

Caused by unmasked floating point exception
with NE = 1.

10

Segmentation faults (for each memory reference required by the instruction) that prevent
transferring the entire memory operand.

Includes segment not present, stack fault, and
general protection fault.

11

Page Faults that prevent transferring the entire
memory operand.

12

Alignment check fault.

2.2.5.5. Exceptions in Real Mode

2.2.5.6. Error Codes

Many of the exceptions described in the ‘Interrupt and Exception Priorities’ on page 69 are
not applicable in real mode. Exceptions 10, 11,
and 14 do not occur in real mode. Other
exceptions have slightly different meanings in
real mode as listed in ‘Exception Changes in
Real Mode’ on page 70

When operating in protected mode, the following
exceptions generate a 16-bit error code:
• Double Fault
• Alignment Check
• Invalid TSS
• Segment Not Present

Table 2.31 Exception Changes in Real
Mode
Vector

Protected
Mode Function

• Page Fault

Double fault

Interrupt table limit
overrun.

10

Invalid TSS

--

11

Segment not
present

--

12

Stack fault

SS segment limit overrun

13

General protection fault

CS, DS, ES, FS, GS
segment limit overrun

Page fault

--

Note: -- means “does not occur”.

ZFx86 Data Book 1.0 Rev D

• General Protection Fault

Real Mode Function

8

14

• Stack Fault

The error code format is shown in Figure 2-18
and the error code bit definitions are listed in
Table 2-33. Bits [15:3] (selector index) are not
meaningful if the error code was generated as
the result of a page fault. The error code is
always zero for double faults and alignment
check exceptions.
15

Selector Index

3 2

1

0

S
2

S
1

S
0

Figure 2-11 Error Code Format

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Table 2.32 Error Code Bit Definitions
Fault Type
Page Fault

Selector Index
(Bits [15:3])
Reserved

S2
(Bit 2)

S1
(Bit 1)

S0
(Bit 0)

Fault caused by:

Fault occurred during:

Fault occurred during:

0 = not present page
1 = page-level protection violation

0 = read access
1 = write access

0 = supervisor access
1 = user access

IDT Fault

Index of faulty IDT
selector

Reserved

1

If = 1, exception
occurred while trying
to invoke exception or
hardware interrupt
handler.

Segment
Fault

Index of faulty selector

TI bit of faulty selector

0

If = 1, exception
occurred while trying
to invoke exception or
hardware interrupt
handler.

2.2.6. System Management Mode
System Management Mode (SMM) provides
an additional interrupt which can be used for
system power management or software transparent emulation of I/O peripherals. SMM is
entered using the System Management Interrupt (SMI#) that has a higher priority than any
other interrupt, including NMI. An SMI interrupt
can also be triggered via the software using an
SMINT instruction. After an SMI interrupt,
portions of the CPU state are automatically
saved, SMM is entered, and program execution begins at the base of SMM address space
(Figure 2-12). Running in protected SMM
address space, the interrupt routine does not
interfere with the operating system or any
application program.
Eight SMM instructions are included in the
processor instruction set that permit software
initiated SMM, and saving and restoring of the
total CPU state when in SMM mode. The
signals SMI# and SMADS# support SMM
functions.

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Potential
SMM Address
Space

Physical
Memory Space
FFFF FFFFh

FFFF FFFFh
ADS# Active

4 KB to
32 MB

Physical Memory
4 GB

Defined
SMM
Address
Space

SMADS# Active

Allowed Memory
256 MB

ADS# Active
0000 0000h

0000 0000h
Non-SMM Mode
ADS# Active

SMM Mode

Figure 2-12 System Management Memory Address Space

2.2.6.1. SMM Operation
SMM operation is summarized in Figure 2-20.
Entering SMM requires the assertion of the
SMI# signal for at least two CLK periods or
execution of the SMINT instruction. For the
SMI# or SMINT instruction to be recognized,
the following configuration register bits must be
set as shown in Table 2.33. The configuration
registers are discussed in detail in Section
“Configuration Registers” on page 25.
Table 2.33 Requirement for Recognizing
SMI# and SMINT
SMI#

SMINT

SMI

Register (Bit)
CCR1 [1]

1

1

SMAC

CCR1 [2]

0

1

SMAR

SIZE [3-0]

>0

>0

located at the top of SMM memory space.
After the header is saved, the CPU enters real
mode and begins executing the SMI service
routine starting at the SMM memory base
address.
The SMI service routine is user definable and
may contain system or power management
software. If the power management software
forces the CPU to power down, or the SMI
service routine modifies more than what is
automatically saved, the complete CPU state
information can be saved.

After recognizing SMI# or SMINT and prior to
executing the SMI service routine, some of the
CPU state information is changed. Prior to
modification, this information is automatically
saved in the SMM memory space header

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SMI# Sampled Active or
SMINT Instruction Executed

CPU State Stored in SMM
Address Space Header

Program Flow Transfers
to SMM Address Space

CPU Enters Real Mode

Execution Begins at SMM
Address Space Base Address

RSM Instruction Restores CPU
State Using Header Information

Normal Execution Resumes

Figure 2-13 SMI Execution Flow Diagram

2.2.6.2. SMM Memory Space Header
With every SMI interrupt or SMINT instruction,
certain CPU state information is automatically
saved in the SMM memory space header
located at the top of SMM address space. See
Figure 2-14. The header contains CPU state
information that is modified when servicing an
SMI interrupt. Included in this information are
two pointers. The Current IP points to the
instruction executing when the SMI was
detected.

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31

0

Top of SMM
Address Space

DR7

-4h

EFLAGS

-8h

CR0

-Ch

Current IP

-10h

Next IP
16 15

31

0

-18h

CS Selector

Reserved

-1Ch

CS Descriptor (Bits 63:32)
CS Descriptor (Bits 31:0)

31

Reserved

-14h

3 2 1 0

-20h

I

-24h

I/O Write Address

-28h

S P

16 15
I/O Write Data Size

I/O Write Data

-2Ch

ESI or EDI

-30h

Figure 2-14 SMM Memory Space Header

The Next IP points to the instruction that will
be executed after exiting SMM. Also saved are
the contents of debug register 7 (DR7), the
extended flags register (EFLAGS), and control
register 0 (CR0). If SMM has been entered
due to an I/O trap for a REP INSx or REP
OUTSx instruction, the Current IP and Next IP
fields contain the same addresses and the I and
P field contain valid information.

tion. The I/O write information is not restored
within the CPU when executing an RSM instruction.

If entry into SMM was caused by an I/O trap
(“I/O Trapping” on page 99.), it is useful for the
programmer to know the port address, data
size and data value associated with that I/O
operation. This information is also saved in the
header and is only valid for an I/O write opera-

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Table 2.34 SMM Memory Space Header
Name

Size

Description

DR7

4 Bytes

The contents of Debug Register 7.

EFLAGS

4 Bytes

The contents of Extended Flags Register.

CR0

4 Bytes

The contents of Control Register 0.

Current IP

4 Bytes

The address of the instruction executed prior to servicing SMI interrupt.

Next IP

4 Bytes

The address of the next instruction that will be executed after exiting SMM mode.

CS Selector

2 Bytes

Code segment register selector for the current code segment.

CS Descriptor

8 Bytes

Code segment register descriptor for the current code segment.

S

1 Bit

Software SMM Entry Indicator.
S = 1 if current SMM is the result of an SMINT instruction.
S = 0 if current SMM is not the result of an SMINT instruction.

P

1 Bit

REP INSx/OUTSx Indicator.
P = 1 if current instruction has a REP prefix.
P = 0 if current instruction does not have a REP prefix.

I

1 Bit

IN, INSx, OUT, or OUTSx Indicator.
I = 1 if current instruction performed is an I/O WRITE.
I = 0 if current instruction performed is an I/O READ.

I/O Write Data
Size

2 Bytes

Indicates size of data for the trapped I/O write.
01h = Byte
03h = WORD
0Fh = DWORD

I/O Write
Address

2 Bytes

Address of the trapped I/O write.

I/O Write Data

4 Bytes

Data associated with the trapped I/O write.

ESI or EDI

4 Bytes

Restored ESI or EDI value. Used when it is necessary to repeat a REP OUTSx or
REP INSx instruction when one of the I/O cycles caused an SMI# trap.

Note: INSx = INS, INSB, INSW or INSD instruction.
OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.

2.2.6.3. SMM Instructions
The processor automatically saves the minimal
amount of CPU state information when entering
SMM which allows fast SMI service routine
entry and exit. After entering the SMI service
routine, the MOV, SVDC, SVLDT and SVTS
instructions can be used to save the complete
CPU state information. If the SMI service
routine modifies more than what is automatically
saved or forces the CPU to power down, the
complete CPU state information must be
saved. Since the CPU is a static device, its
internal state is retained when the input clock is

ZFx86 Data Book 1.0 Rev D

stopped. Therefore, an entire CPU state save
is not necessary prior to stopping the input
clock.
The SMM instructions, listed in Table 2-36,
can only be executed if the following conditions are met:

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SMI# is enabled and
SMAR SIZE > 0 and
[the Current Privilege Level (CPL) = 0 and
the SMAC bit (CCR1, bit 2) is set] or
[the Current Privilege Level (CPL) = 0 and
the CPU is in an SMI service routine (SMI# = 0)].
If the above conditions are not met and an
attempt is made to execute an SVDC, RSDC,
SVLDT, RSLDT, SVTS, RSTS, SMINT or RSM
instruction, an invalid opcode exception is
generated. These instructions can be
executed outside of defined SMM space

provided the above conditions are met.
The SMINT instruction can be used by software to enter SMM. The CPU will not drive the
SMI# output low during the software initiated
SMM.

Table 2.35 SMM Instruction Set
Instruction

OPCODE

Format

Description

SVDC

0F 78 [mod sreg3
r/m]

SVDC mem80,
sreg3

Save Segment Register and Descriptor:
Saves reg (DS, ES, FS, GS, or SS) to mem80.

RSDC

0F 79 [mod sreg3
r/m]

RSDC sreg3,
mem80

Restore Segment Register and Descriptor:
Restores reg (DS, ES, FS, GS, or SS) from mem80
Use RSM to restore CS.
Note: Processing “RSDC CS, Mem80” will produce
an exception.

SVLDT

0F 7A [mod 000 r/m]

SVLDT mem80

Save LDTR and Descriptor:
Saves Local Descriptor Table (LDTR) to mem80.

RSLDT

0F 7B [mod 000 r/m]

RSLDT mem80

Restore LDTR and Descriptor:
Restores Local Descriptor Table (LDTR) from
mem80

SVTS

0F 7C [mod 000 r/m]

SVTS mem80

Save TSR and Descriptor:
Saves Task State Register (TSR) to mem80.

RSTS

0F 7D [mod 000 r/m]

RSTS mem80

Restore TSR and Descriptor:
Restores Task State Register (TSR) from mem80.

SMINT

0F 7E

SMINT

Software SMM Entry:
CPU enters SMM mode. CPU state information is
saved in SMM memory space header and execution begins at SMM base address.

RSM

0F AA

RSM

Resume Normal Mode:
Exits SMM mode. The CPU state is restored using
the SMM memory space header and execution
resumes at interrupted point.

Note: mem80 = 80-bit memory location

If the SMI# is asserted to the CPU during a
software SMM, the SMI# handshake occurs
normally. The hardware SMI# is serviced after
the software SMM has been exited by execution of the RSM instruction.

ZFx86 Data Book 1.0 Rev D

All of the SMM instructions (except RSM and
SMINT) save or restore 80 bits of data,
allowing the saved values to include the
hidden portion of the register contents.

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2.2.6.4. SMM Memory Space
SMM memory space is defined by specifying
the base address and size of the SMM
memory space in the SMAR register. The
base address must be a multiple of the SMM
memory space size. For example, a 32 KB
SMM memory space must be located at a
32 KB address boundary. The memory space
size can range from 4 KB to 32 MB.
SMM memory space accesses are always
non-cacheable. SMM accesses ignore the
state of the A20M# input signal and drive the
A20 address bit to the unmasked value.
Access to the SMM memory space can be
made even though not in SMM mode by
setting the SMAC bit in the CCR1 register.
This feature may be used to initialize the SMM
memory space.
While in SMM mode, SMADS# address
strobes are generated instead of ADS# for
SMM memory accesses. Any memory
accesses outside the defined SMM space
result in normal memory accesses and ADS#
strobes. Data (non-code) accesses to main
memory that overlap with defined SMM
memory space are allowed if MMAC in CCR1
is set. In this case, ADS# strobes are generated for data accesses only and SMADS#
strobes continue to be generated for code
accesses.

2.2.6.5. SMI Service Routine Execution
After the SMM header has been saved, upon
entry into SMM the CR0, EFLAGS, and DR7
registers are set to their reset values. The
Code Segment (CS) register is loaded with the
base, as defined by the SMAR register, and a
limit of 4 GB. The SMI service routine then
begins execution at the SMM base address in
real mode.

ately after entering the SMI service routine,
the programmer must use CS as a segment
override. I/O port access is possible during the
routine, but care must be taken to save registers modified by the I/O instructions. Before
using a segment register, the register and the
register’s descriptor cache contents should be
saved using the SVDC instruction. While
executing in the SMM space, execution flow
can transfer to normal memory locations.
Hardware interrupts, (INTRs and NMIs), may
be serviced during a SMI service routine. If
interrupts are to be serviced while executing in
the SMM memory space, the SMM memory
space must be within the 0 to 1 MB address
range to guarantee proper return to the SMI
service routine after handling the interrupt.
INTRs are automatically disabled when
entering SMM since the IF flag is set to its
reset value. Once in SMM, the INTR can be
enabled by setting the IF flag. An NMI event in
SMM mode can be enabled by setting NMIEN
in the CCR3 register. If NMI is not enabled
while in SMM mode, the CPU latches one NMI
event and services the interrupt after NMI has
been enabled or after exiting SMM mode
through the RSM instruction.
Within the SMI service routine, protected
mode may be entered and exited as required,
and real or protected mode device drivers may
be called.
To exit the SMI service routine, a Resume
(RSM) instruction, rather than an IRET, is
executed. The RSM instruction causes the
processor to restore the CPU state using the
SMM header information and resume execution at the interrupted point. If the full CPU
state was saved by the programmer, the
stored values should be reloaded prior to
executing the RSM instruction using the MOV,
RSDC, RSLDT and RSTS instructions.

The programmer must save the value of any
registers that may be changed by the SMI
service routine. For data accesses immedi-

ZFx86 Data Book 1.0 Rev D

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CPU States Related to SMM and Suspend Mode
Figure 2-15 illustrates the various CPU states
associated with SMM and suspend mode.
While in the SMI service routine, the processor
can enter suspend mode either by (1)
executing a halt (HLT) instruction or (2) by
asserting the SUSP# input.
During SMM operations and while in SUSP#
initiated suspend mode, an occurrence of
either NMI or INTR is latched. (In order for
INTR to be latched, the IF flag must be set.)

NMI or INTR
Suspend Mode
(SUSPA# = 0)

The INTR or NMI is serviced after exiting
suspend mode. If suspend mode is entered
via a HLT instruction from the operating
system or application software, the reception
of an SMI# interrupt causes the CPU to exit
suspend mode and enter SMM. If suspend
mode is entered via the hardware (SUSP# =
0) while the operating system or application
software is active, the CPU latches one occurrence of INTR, NMI and SMI#.

Interrupt Service
Routine

IRET*

HLT*

NMI or INTR
SUSP# = 0

OS/Application
Software

RESET
SMI# = 0

SMI# = 0
SMINT*

(INTR, NMI and SMI latched)
RSM*
Non-SMM Operations
SMM Operations

SMI Service
Routine
(SMI# = 0)

INTR or NMI
IRET*
Interrupt Service
Routine

Suspend Mode
(SUSPA# = 0)

SUSP# = 1

HLT*
Suspend Mode
(SUSPA# = 0)
IRET*
INTR and NMI

SUSP# = 0

SUSP# = 1

Interrupt Service
Routine

Suspend Mode
(SUSPA# = 0)

* Instructions

(INTR and NMI latched)

Figure 2-15 SMM and Suspend Mode State Diagram

ZFx86 Data Book 1.0 Rev D

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SL-enhanced Compatibility Mode

SMM Control Bit

Following power-up or RESET, the CPU SMM
interface pins are disabled. Once enabled,
these two pins can either function as defined
previously (SMI and SMADS) or can be
programmed to function with a signalling
protocol compatible with the 32-bit x86enhanced CPUs (SMI, SMIACT). This section
describes the operation of the SMM interface
pins when operating in the SL-compatible
mode.

The SMM_Mode bit in the configuration
register (CCR3 bit 3) controls the SMM interface mode. Once the SMI_Lock bit is set, the
CPU must be reset in order to modify
SMI_Lock and SMM_Mode.

Pin Definitions
The two pins that change function in SLcompatible mode are SMI and SMADS.

Table 2.36 SMM Pin Definitions
Non-SLCompatible Mode

SL-Compatible Mode

SMI: Bidirectional System Management Interrupt pin.

SMI: System Management Interrupt input pin.

Asserted by the system logic to request an SMI interrupt.
Sampled by the CPU on each rising clock edge. Causes I/O
trap to occur if sampled and found asserted at least two clocks
prior to ready sampled asserted for an I/O cycle.

Asserted by the system logic to request an SMI interrupt. Sampled by the CPU on each rising clock edge. SMI is falling edge
sensitive and causes an I/O trap to occur if sampled and found
asserted at least three clocks prior to RDY/BRDY sampled
asserted for any I/O cycle.

Asserted by the CPU during execution of an SMI service routine
or in response to SMINT if SMAC is set.
SMADS: SMI Address Strobe output used to indicate that the
current bus cycle is an SMM memory access.

Nested SMI
In Non-SLCompatible mode, nested SMI’s
cannot occur due to the fact that the SMI pin
becomes an output during SMI servicing. In
SL-Compatible mode, if an SMI occurs during
an SMI service routine, one and only one SMI
is latched. The latched SMI is then serviced
immediately following execution of a RSM
instruction (used to exit the original SMI
service routine).

SMM Features Not Used with SLCompatible Interface.
The SMAC and MMAC functions are disabled
when in SL-Compatible mode. Additionally,
SMIACT remains asserted while executing an
SMI service routine regardless of the address
being accessed. In other words, if the SMI
service routine accesses memory outside the
defined SMM memory space, SMIACT

ZFx86 Data Book 1.0 Rev D

SMIACT: SMI Active output asserted by the CPU during execution of an SMI service routine.

remains asserted. Also, the SMINT instruction
should not be used in SL-Compatible mode.

Write-Back Caching and SMM
The CPU allows caching of SMM memory
accesses. The SMM memory caching may
cause coherency problems in systems where
SMM memory space and normal memory
space overlap. Therefore, one of the following
options is recommended:
1) Flush the cache when entering and exiting
an SMI service routine.
OR
2) Flush the cache when entering an SMI
service routine and then make all SMM
accesses non-cacheable using the KEN pin.
In either case it is recommended to assert the
FLUSH input pin when the SMIACT pin is

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asserted. Asserting FLUSH in this manner is
acceptable for a CPU with write-through cache
as the flush invalidates the cache in a single
clock.

vector and flag information (i.e., stack pointer
is greater than 0005h). Otherwise, shutdown
can only be exited by a processor reset.

However, on CPUs with write-back cache,
asserting FLUSH requires the writing of all
dirty data to external memory prior to invalidating the cache contents. Bus cycles that
address normal memory addresses that
overlap with SMM memory space should not
be issued while SMIACT is asserted.

Segment protection and page protection are
safeguards built into the CPU protected mode
architecture which deny unauthorized or incorrect access to selected memory addresses.
These safeguards allow multitasking
programs to be isolated from each other and
from the operating system. Page protection is
discussed earlier in this chapter in ‘Paging
Mechanism’ on page 64. This section concentrates on segment protection.

Therefore, while in SL-Compatible mode, the
CPU automatically writes all dirty data to
memory and then invalidates the cache prior
to asserting SMIACT. This guarantees that no
dirty data exists in the CPU at the time that
SMIACT is asserted.
SMM accesses are always non-cacheable and
the cache is flushed before entering the SMI
service routine. For these reasons, a bus
snoop that occurs while SMIACT is asserted
can never hit on a dirty line that is in SMM
space or the overlapped normal memory
space.Therefore, bus snoops that occur, while
SMIACT is asserted, never result in memory
incoherences.

2.2.7. Shutdown and Halt
The halt instruction (HLT) stops program
execution and prevents the processor from
using the local bus until restarted. The
processor then enters a low-power suspend
mode if the HLT bit in CCR2 is set. SMI, NMI,
INTR with interrupts enabled (IF bit in
EFLAGS = 1), or RESET forces the CPU out
of the halt state. If interrupted, the saved code
segment and instruction pointer specify the
instruction following the HLT.
Shutdown occurs when a severe error is
detected that prevents further processing. An
NMI input can bring the processor out of shutdown if the IDT limit is large enough to contain
the NMI interrupt vector (at least 000Fh) and
the stack has enough room to contain the

ZFx86 Data Book 1.0 Rev D

2.2.8. Protection

Selectors and descriptors are the key
elements in the segment protection mechanism. The segment base address, size, and
privilege level are established by a segment
descriptor. Privilege levels control the use of
privileged instructions, I/O instructions and
access to segments and segment descriptors.
Selectors are used to locate segment descriptors.
Segment accesses are divided into two basic
types, those involving code segments (e.g.,
control transfers) and those involving data
accesses. The ability of a task to access a
segment depends on:
• the segment type
• the instruction requesting access
• the type of descriptor used to define the
segment
• the associated privilege levels (described
below).
Data stored in a segment can be accessed
only by code executing at the same or a more
privileged level. A code segment or procedure
can only be called by a task executing at the
same or a less privileged level.

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2.2.8.1. Privilege Levels
The values for privilege levels range
between 0 and 3. Level 0 is the highest privilege level (most privileged), and level 3 is the
lowest privilege level (least privileged). The
privilege level in real mode is effectively 0.
The Descriptor Privilege Level (DPL) is the
privilege level defined for a segment in the
segment descriptor. The DPL field specifies
the minimum privilege level needed to access
the memory segment pointed to by the
descriptor.
The Current Privilege Level (CPL) is defined
as the current task’s privilege level. The CPL
of an executing task is stored in the hidden
portion of the code segment register and
essentially is the DPL for the current code
segment.
The Requested Privilege Level (RPL) specifies a selector’s privilege level and is used to
distinguish between the privilege level of a
routine actually accessing memory (the CPL),
and the privilege level of the original requestor
(the RPL) of the memory access. The lesser of
the RPL and CPL is called the effective privilege
level (EPL). Therefore, if RPL = 0 in a segment
selector, the effective privilege level is always
determined by the CPL. If RPL = 3, the effective privilege level is always 3 regardless of
the CPL.
For a memory access to succeed, the effective
privilege level (EPL) must be at least as privileged as the descriptor privilege level (EPL £
DPL). If the EPL is less privileged than the
DPL (EPL > DPL), a general protection fault is
generated. For example, if a segment has a
DPL = 2, an instruction accessing the segment
only succeeds if executed with an EPL £ 2.

2.2.8.2. I/O Privilege Levels
The I/O Privilege Level (IOPL) allows the operating system executing at CPL = 0 to define
the least privileged level at which IOPL-sensitive instructions can unconditionally be used.

ZFx86 Data Book 1.0 Rev D

The IOPL-sensitive instructions include CLI,
IN, OUT, INS, OUTS, REP INS, REP OUTS,
and STI. Modification of the IF bit in the
EFLAGS register is also sensitive to the I/O
privilege level.
The IOPL is stored in the EFLAGS register. An
I/O permission bit map is available as defined
by the 32-bit Task State Segment (TSS). Since
each task can have its own TSS, access to
individual I/O ports can be granted through
separate I/O permission bit maps.
If CPL <= IOPL, IOPL-sensitive operations
can be performed. If CPL > IOPL, a general
protection fault is generated if the current task
is associated with a 16-bit TSS. If the current
task is associated with a 32-bit TSS and CPL
> IOPL, the CPU consults the I/O permission
bitmap in the TSS to determine on a port-by-port
basis whether or not I/O instructions (IN, OUT,
INS, OUTS, REP INS, REP OUTS) are
permitted, and the remaining IOPL-sensitive
operations generate a general protection fault.

2.2.8.3. Privilege Level Transfers
A task’s CPL can be changed only through
intersegment control transfers using gates or
task switches to a code segment with a
different privilege level. Control transfers result
from exception and interrupt servicing and
from execution of the CALL, JMP, INT, IRET
and RET instructions.
There are five types of control transfers that
are summarized in Table 2.37. Control transfers can be made only when the operation
causing the control transfer references the
correct descriptor type. Any violation of these
descriptor usage rules causes a general
protection fault.
Any control transfer that changes the CPL
within a task results in a change of stack. The
initial values for the stack segment (SS) and
stack pointer (ESP) for privilege levels 0, 1,
and 2 are stored in the TSS. During a JMP or
CALL control transfer, the SS and ESP are

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loaded with the new stack pointer and the
previous stack pointer is saved on the new
stack. When returning to the original privilege

level, the RET or IRET instruction restores the
less-privileged stack.

Table 2.37 Descriptor Types Used for Control Transfer
Control Transfer Type

Operation Types

Descriptor

Descriptor Table

Intersegment within the same privilege level.

JMP, CALL, RET,
IRET*

Code Segment

GDT or LDT

Intersegment to the same or a more privileged
level.
Interrupt within task (could change CPL level).

CALL

Gate Call

GDT or LDT

Interrupt Instruction,
Exception
External Interrupt

Trap or Interrupt Gate

LDT

Intersegment to a less privileged level (changes
task CPL).

RET, IRET*

Code Segment

GDT or LDT

Task Switch via TSS.

CALL, JMP

Task State Segment

GDT

Task Switch via Task Gate.

CALL, JMP

Task Gate

GDT or LDT

IRET** Interrupt
Instruction, Exception, External Interrupt

Task Gate

IDT

*
**

NT (Nested Task bit in EFLAGS) = 0
NT (Nested Task bit in EFLAGS) = 1

Gates
Gate descriptors provide protection for privilege transfers among executable segments.
Gates are used to transition to routines of the
same or a more privileged level. Call gates,
interrupt gates and trap gates are used for privilege transfers within a task. Task gates are
used to transfer between tasks.
Gates conform to the standard rules of privilege. In other words, gates can be accessed
by a task if the effective privilege level (EPL) is
the same or more privileged than the gate
descriptor’s privilege level (DPL).

2.2.8.4. Initialization and Transition to
Protected Mode
The processor switches to real mode immediately after RESET. While operating in real
mode, the system tables and registers should
be initialized. The GDTR and IDTR must point to
a valid GDT and IDT, respectively. The size of the

ZFx86 Data Book 1.0 Rev D

IDT should be at least 256 bytes, and the GDT
must contain descriptors which describe the
initial code and data segments.
The processor can be placed in protected
mode by setting the PE bit in the CR0 register.
After enabling protected mode, the CS register
should be loaded and the instruction decode
queue should be flushed by executing an intersegment JMP. Finally, all data segment registers should be initialized with appropriate
selector values.

2.2.9. Virtual 8086 Mode
Both real mode and virtual 8086 (V86) mode
are supported by the CPU, allowing execution of
8086 application programs and 8086 operating
systems. V86 mode allows the execution of
8086-type applications, yet still permits use of
the processor protection mechanism. V86
tasks run at privilege level 3. Upon entry, all

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segment limits are set to FFFFh (64 KB) as in
real mode.

2.2.9.1. Memory Addressing
While in V86 mode, segment registers are
used in an identical fashion to real mode. The
contents of the segment register are multiplied
by 16 and added to the offset to form the
segment base linear address. The CPU
permits the operating system to select which
programs use the V86 address mechanism
and which programs use protected mode
addressing for each task.
The processor also permits the use of paging
when operating in V86 mode. Using paging,
the 1 MB address space of the V86 task can
be mapped to anywhere in the 4 GB linear
address space of the CPU.
The paging hardware allows multiple V86
tasks to run concurrently and provides protection and operating system isolation. The
paging hardware must be enabled to run
multiple V86 tasks or to relocate the address
space of a V86 task to physical address space
greater than 1 MB.

2.2.9.2. Protection
All V86 tasks operate with the least amount of
privilege (level 3) and are subject to all of the
protected mode protection checks. As a result,
any attempt to execute a privileged instruction
within a V86 task results in a general protection fault.
In V86 mode a slightly different set of instructions is sensitive to the I/O privilege level
(IOPL) than in protected mode. The instructions are: CLI, INTn, IRET, POPF, PUSHF, and
STI. The INT3, INTO and BOUND variations
of the INT instruction are not IOPL sensitive.

2.2.9.3. Interrupt Handling
To fully support the emulation of an 8086-type
machine, interrupts in V86 mode are handled
as follows. When an interrupt or exception is
serviced in V86 mode, program execution

ZFx86 Data Book 1.0 Rev D

transfers to the interrupt service routine at
privilege level 0 (i.e., transition from V86 to
protected mode occurs) and the VM bit in the
EFLAGS register is cleared. The protected
mode interrupt service routine then determines if the interrupt came from a protected
mode or V86 application by examining the VM
bit in the EFLAGS image stored on the stack.
The interrupt service routine may then choose
to allow the 8086 operating system to handle
the interrupt or may emulate the function of
the interrupt handler. Following completion of
the interrupt service routine, an IRET instruction restores the EFLAGS register (restores
VM = 1) and segment selectors and control
returns to the interrupted V86 task.

2.2.9.4. Entering and Leaving V86
Mode
V86 mode is entered from protected mode by
either executing an IRET instruction at CPL = 0
or by task switching. If an IRET is used, the
stack must contain an EFLAGS image with
VM = 1. If a task switch is used, the TSS must
contain an EFLAGS image containing a 1 in
the VM bit position. The POPF instruction
cannot be used to enter V86 mode since the
state of the VM bit is not affected. V86 mode
can only be exited as the result of an interrupt
or exception. The transition out must use a 32bit trap or interrupt gate which must point to a
non-conforming privilege level 0 segment
(DPL = 0), or a 32-bit TSS. These restrictions
are required to permit the trap handler to IRET
back to the V86 program.

2.2.10. FPU Operations
2.2.10.1. FPU Register Set
In addition to the registers described to this
point, the FPU circuitry within the CPU
provides the user eight data registers
(accessed in a stack-like manner), a control
register, and a status register. The CPU also
provides a data register tag word which
improves context switching and stack performance by maintaining empty/non-empty

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status for each of the eight data registers. In
addition, registers in the CPU contain pointers
to (a) the memory location containing the
current instruction word and (b) the memory
location containing the operand associated
with the current instruction word (if any).
FPU Tag Word Register. The processor
maintains a tag word register comprised of two
bits for each physical data register. Tag Word
fields assume one of four values depending
on the contents of their associated data registers, Valid (00), Zero (01), Special (10), and
Empty (11). Note: Denormal, Infinity, QNaN,
SNaN and unsupported formats are tagged as
“Special”. Tag values are maintained transparently by the processor and are only available
to the programmer indirectly through the
FSTENV and FSAVE instructions. The tag
word with tag fields for each associated physical register, tag(n), is shown in Figure 2-16.
15

13

11

9

7

5

3

1

Tag 7 Tag 6 Tag 5 Tag 4 Tag 3 Tag 2 Tag 1 Tag 0

Figure 2-16 Tag Word Register

that reflect exception status, operation execution status, register status, operand class, and
comparison results. This register is continuously accessible to the CPU regardless of the
state of the Control or Execution Units. The
Status Register’s bit definitions are given in
Table 2.38.
15

11

7

3

B C3 S S S C2 C1 C0 ES SF P U O Z

D

I

Figure 2-17 FPU Status Register

FPU Mode Control Register. The FPU Mode
Control Register (MCR), Figure 2-18, is used
by the CPU to specify the operating mode of
the FPU. The MCR contains bit fields which
specify the rounding mode to be used, the
precision by which to calculate results, and the
exception conditions which should be reported
to the CPU via traps. The user controls precision, rounding, and exception reporting by
setting or clearing appropriate bits in the MCR.
The Mode Control Register’s bit definitions are
given in Table 2.39.
15

11

7

3

FPU Status Register. The FPU circuitry
- - - - RC RC PC PC - - P U O Z D I
communicates information about its status and
the results of operations to the CPU via the
Figure 2-18 FPU Mode Control Register
status register. The FPU status register, illustrated in Figure 2-17, is comprised of bit fields
Table 2.38 Status Control Register Bit Definitions
Bit

Name

15

B

14, 10:8

C3-C0

13:11

SSS

Top of stack register number which points to the current TOS.

7

ES

Error indicator. Set to 1 if an unmasked exception is detected.

6

SF

Stack Fault or invalid register operation bit.

5

P

Precision error exception bit.

4

U

Underflow error exception bit.

3

O

Overflow error exception bit.

2

Z

Divide by zero exception bit.

1

D

Denormalized operand error exception bit.

ZFx86 Data Book 1.0 Rev D

Description
Copy of the ES bit. (ES is bit 7 in this table.)
Condition code bits.

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Table 2.38 Status Control Register Bit Definitions
Bit

Name

0

I

Description
Invalid operation exception bit.

Table 2.39 Mode Control Register Bit Definition
Bit

Name

Description

15:12

RSVD

Reserved.

11:10

RC

Rounding Control bits:
00
01
10
11

9:8

PC

= Round to nearest or even
= Round towards minus infinity
= Round towards plus infinity
= Truncate

Precision Control bits:
00
01
10
11

= 24-bit mantissa
= Reserved
= 53-bit mantissa
= 64-bit mantissa

5

P

Precision error exception bit mask.

4

U

Underflow error exception bit mask.

3

O

Overflow error exception bit mask.

2

Z

Divide by zero exception bit mask.

1

D

Denormalized operand error exception bit mask.

0

I

Invalid operation exception bit mask.

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2.3. Instruction Set
Depending on the instruction, the CPU instructions follow the general instruction format
shown in Figure 2-19. These instructions vary
in length and can start at any byte address. An
instruction consists of one or more bytes that
can include: prefix byte(s), at least one
opcode byte(s), mod r/m byte, s-i-b byte,
address displacement byte(s) and immediate
data byte(s). An instruction can be as short as
one byte and as long as 15 bytes. If there are
more than 15 bytes in the instruction a general
protection fault (error code 0) is generated.

This section summarizes the Processor
instruction set and provides detailed information on the instruction encodings. All instructions are listed in the CPU Instruction Set
Summary Table Table 2.56 on page 94, and
the FPU Instruction Set Summary Table Table
2.58 on page 108. These tables provide information on the instruction encoding, and the
instruction clock counts for each instruction.
The clock count values for both tables are
based on the assumptions described in the
Section 2.3.2.1. ‘Assumptions Made in Determining Instruction Clock Count’ on page 93.
7

0 7

PPPPPPPP TTTTTTTT

operation prefix
byte(s)

opcode
1 or 2 bytes

0
mod
76

RRR
543

r/m
210

ss
76

index
543

mod r/m
byte

s-i-b
byte

base
210

32

16

8

none

address displacement
4, 2, 1 bytes or none

32

16

8

none

immediate data
(4, 2, 1 bytes or none)

register and address
mode specifier
P = prefix bit
T = opcode bit
R = opcode bit or reg bit
ss = scale
r/m = register/mode

Figure 2-19 Instruction Set Format

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2.3.1. General Instruction Fields
The fields in the general instruction format at
the byte level are listed in Table 2.40.
Table 2.40 Instruction Fields
Field Name

Description

Width

Optional Prefix
Byte(s)

Specifies segment register override, address and operand size,
repeat elements in string instruction, LOCK# assertion.

1 or more bytes

Opcode Byte(s)

Identifies instruction operation.

1 or 2 bytes

mod and r/m Byte

Address mode specifier.

1 byte

s-i-b Byte

Scale factor, Index and Base fields.

1 byte

Address Displacement

Address displacement operand.

1, 2 or 4 bytes

Immediate data

Immediate data operand.

1, 2 or 4 bytes

2.3.1.1. Optional Prefix Byte(s)
Prefix bytes can be placed in front of any
instruction. The prefix modifies the operation
of the next instruction only. When more than
one prefix is used, the order is not important.
There are five types of prefixes as follows:
• Segment Override explicitly specifies
which segment register an instruction will
use for effective address calculation.
• Address Size switches between 16- and
32-bit addressing. Selects the inverse of
the default.

• Repeat is used with a string instruction
which causes the instruction to be
repeated for each element of the string.
• Lock is used to assert the hardware
LOCK# signal during execution of the
instruction.
Table 2.41 lists the encodings for each of the
available prefix bytes. The operand size and
address size prefixes allow the individual overriding of the default value for operand size and
effective address size. The presence of these
prefixes selects the opposite (non-default)
operand size and/or effective address size.

• Operand Size switches between 16- and
32-bit operand size. Selects the inverse of
the default.
Table 2.41 Instruction Prefix Summary
Prefix

Encoding

Description

ES:

26h

Override segment default, use ES for memory operand

CS:

2Eh

Override segment default, use CS for memory operand

SS:

36h

Override segment default, use SS for memory operand

DS:

3Eh

Override segment default, use DS for memory operand

FS:

64h

Override segment default, use FS for memory operand

GS:

65h

Override segment default, use GS for memory operand

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Table 2.41 Instruction Prefix Summary
Prefix

Encoding

Description

Operand Size

66h

Make operand size attribute the inverse of the default

Address Size

67h

Make address size attribute the inverse of the default

LOCK

F0h

Assert LOCK# hardware signal.

REPNE

F2h

Repeat the following string instruction.

REP/REPE

F3h

Repeat the following string instruction.

2.3.1.2. Opcode Byte(s)

2.3.1.4. d Field

The opcode field is either one or two bytes in
length and may be further defined by additional bits in the mod r/m byte. The opcode
field specifies the operation to be performed
by the instruction. Some operations have
more than one opcode, each specifying a
different form of the operation. Some opcodes
name instruction groups. For example, opcode
0x80 names a group of operations that has an
immediate operand, and a register or memory
operand. The opcodes are given in hex
values unless shown within brackets ([ ]).
Values within brackets are given in binary. The
reg field may appear in the second opcode
byte or in the mod r/m byte.

The d field determines which operand is taken
as the source operand and which operand is
taken as the destination.

2.3.1.3. w Field
The 1-bit w field selects the operand size
during 16 and 32 bit data operations.

Table 2.43 d Field Encoding
Direction
of Operation

d Field

Source
Operand

Destination
Operand

0

Register --> Register or
Register --> Memory

reg

mod r/m or
mod s-i-b

1

Register --> Register or
Memory --> Register

mod r/m or
mod s-i-b

reg

2.3.1.5. eee Field
The eee field is used to select the control,
debug and test registers in the MOV instructions. The type of register and base registers
selected by the eee field are listed in Table
2.44. The values shown are the only valid
encodings for the eee bits.

Table 2.42 w Field Encoding
W Field

Operand Size
16-bit Data
Operations

Operand Size
32-bit Data
Operations

0

8 Bits

1

16 Bits

ZFx86 Data Book 1.0 Rev D

Table 2.44 eee Field Encoding
eee Field

Register Type

Base Register

8 Bits

000

Control Register

CR0

32 Bits

010

Control Register

CR2

011

Control Register

CR3

000

Debug Register

DR0

001

Debug Register

DR1

010

Debug Register

DR2

011

Debug Register

DR3

110

Debug Register

DR6

111

Debug Register

DR7

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2
Table 2.44 eee Field Encoding (cont.)
eee Field

Register Type

Base Register

011

Test Register

TR3

100

Test Register

TR4

101

Test Register

TR5

110

Test Register

TR6

111

Test Register

TR7

2.3.1.6. mod and r/m Byte
The mod and r/m fields, within the mod r/m
byte, select the type of memory addressing to
be used. Some instructions use a fixed
addressing mode (e.g., PUSH or POP) and
therefore, these fields are not present. Table
2.45 lists the addressing method when 16-bit
addressing is used and a mod r/m byte is
present. Some mod r/m field encodings are
dependent on the w field and are shown in
Table 2.46.

Table 2.45 mod r/m Field Encoding
mod and r/m
fields

16-bit Address Mode
with mod r/m byte

32-bit Address Mode
with mod r/m byte and
no s-i-b byte present

00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111

DS:[BX+SI]
DS:[BX+DI]
DS:[BP+SI]
DS:[BP+DI]
DS:[SI]
DS:[DI]
DS:[d16]
DS:[BX]

DS:[EAX]
DS:[ECX]
DS:[EDX]
DS:[EBX]
s-i-b is present
DS:[d32]
DS:[ESI]
DS:[EDI]

01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111

DS:[BX+SI+d8]
DS:[BX+DI+d8]
DS:[BP+SI+d8]
DS:[BP+DI+d8]
DS:[SI+d8]
DS:[DI+d8]
SS:[BP+d8]
DS:[BX+d8]

DS:[EAX+d8]
DS:[ECX+d8]
DS:[EDX+d8]
DS:[EBX+d8]
s-i-b is present
SS:[EBP+d8]
DS:[ESI+d8]
DS:[EDI+d8]

10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111

DS:[BX+SI+d16]
DS:[BX+DI+d16]
DS:[BP+SI+d16]
DS:[BP+DI+d16]
DS:[SI+d16]
DS:[DI+d16]
SS:[BP+d16]
DS:[BX+d16]

DS:[EAX+d32]
DS:[ECX+d32]
DS:[EDX+d32]
DS:[EBX+d32]
s-i-b is present
SS:[EBP+d32]
DS:[ESI+d32]
DS:[EDI+d32]

11000-11111

See Table 5-7

See Table 5-7

ZFx86 Data Book 1.0 Rev D

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Table 2.46 mod r/m Field Encoding Dependent on w Field

mod r/m

16-bit
Operation
w=0

16-bit
Operation
w=1

32-bit
Operation
w=0

32-bit
Operation
w=1

11 000

AL

AX

AL

EAX

11 001

CL

CX

CL

ECX

11 010

DL

DX

DL

EDX

11 011

BL

BX

BL

EBX

11 100

AH

SP

AH

ESP

11 101

CH

BP

CH

EBP

11 110

DH

SI

DH

ESI

11 111

BH

DI

BH

EDI

2.3.1.7. reg Field
The reg field determines which general registers are to be used. The selected register is
dependent on whether a 16 or 32 bit operation
is current and the status of the w bit.
Table 2.47 reg Field

reg

16-bit
Operation
w Field Not
Present

32-bit
Operation
w Field Not
Present

16-bit
Operation
w=0

16-bit
Operation
w=1

32-bit
Operation
w=0

32-bit
Operation
w=1

000

AX

EAX

AL

AX

AL

EAX

001

CX

ECX

CL

CX

CL

ECX

010

DX

EDX

DL

DX

DL

EDX

011

BX

EBX

BL

BX

BL

EBX

100

SP

ESP

AH

SP

AH

ESP

101

BP

EBP

CH

BP

CH

EBP

110

SI

ESI

DH

SI

DH

ESI

111

DI

EDI

BH

DI

BH

EDI

2.3.1.8. sreg3 Field
The sreg3 field (Table 2.43) is 3-bit field that is
similar to the sreg2 field, but allows use of the

FS and GS segment registers.
Table 2.48 sreg3 Field Encoding
sreg3 Field

ZFx86 Data Book 1.0 Rev D

Segment Register Selected

000

ES

001

CS

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Table 2.48 sreg3 Field Encoding
sreg3 Field

Table 2.50 ss Field Encoding

Segment Register Selected

ss Field

Scale Factor

010

SS

01

x2

011

DS

01

x4

100

FS

11

x8

101

GS

110

undefined

2.3.1.12. index Field

111

undefined

The sreg2 field (Table 2.42) is a 2-bit field that
allows one of the four 286 type segment registers to be specified.

The index field (Table 2.51) specifies the index
register used by the offset mechanism for
offset address calculation. When no index
register is used (index field = 100), the ss
value must be 00 or the effective address is
undefined.

Table 2.49 sreg2 Field Encoding

Table 2.51 index Field Encoding

2.3.1.9. sreg2 Field

sreg2 FIELD

Segment Register Selected

Index Field

Index Register

00

ES

000

EAX

01

CS

001

ECX

10

SS

010

EDX

11

DS

011

EBX

100

none

101

EBP

2.3.1.10. s-i-b Byte
The s-i-b fields provide scale factor, indexing
and a base field for address selection.

2.3.1.11. ss Field
The ss field (Table 2.50) specifies the scale
factor used in the offset mechanism for
address calculation. The scale factor multiplies the index value to provide one of the
components used to calculate the offset
address.
Table 2.50 ss Field Encoding
ss Field

Scale Factor

00

x1

110

ESI

111

EDI

Base Field

In Table 2.45, the note “s-i-b present” for
certain entries forces the use of the mod and
base field as listed in Table 2.52. The first two
digits in the first column of this table identifies
the mod bits in the mod r/m byte. The last
three digits in the first column identify the base
fields in the s-i-b byte.

Table 2.52 mod base Field Encoding
32-Bit Address Mode
with mod r/m and
s-i-b Bytes Present

mod Field within
mode/rm Byte

base Field
within
s-i-b Byte

00

000

DS:[EAX+(scaled index)]

00

001

DS:[ECX+(scaled index)]

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Table 2.52 mod base Field Encoding (cont.)
32-Bit Address Mode
with mod r/m and
s-i-b Bytes Present

mod Field within
mode/rm Byte

base Field
within
s-i-b Byte

00

010

DS:[EDX+(scaled index)]

00

011

DS:[EBX+(scaled index)]

00

100

SS:[ESP+(scaled index)]

00

101

DS:[d32+(scaled index)]

00

110

DS:[ESI+(scaled index)]

00

111

DS:[EDI+(scaled index)]

01

000

DS:[EAX+(scaled index)+d8]

01

001

DS:[ECX+(scaled index)+d8]

01

010

DS:[EDX+(scaled index)+d8]

01

011

DS:[EBX+(scaled index)+d8]

01

100

SS:[ESP+(scaled index)+d8]

01

101

SS:[EBP+(scaled index)+d8]

01

110

DS:[ESI+(scaled index)+d8]

01

111

DS:[EDI+(scaled index)+d8]

10

000

DS:[EAX+(scaled index)+d32]

10

001

DS:[ECX+(scaled index)+d32]

10

010

DS:[EDX+(scaled index)+d32]

10

011

DS:[EBX+(scaled index)+d32]

10

100

SS:[ESP+(scaled index)+d32]

10

101

SS:[EBP+(scaled index)+d32]

10

110

DS:[ESI+(scaled index)+d32]

10

111

DS:[EDI+(scaled index)+d32]

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2.3.2. Instruction Set Tables
The instruction set is presented in two tables,
the CPU Instruction Set (Table 2.56 on page
94) and the FPU Instruction Set (Table 2.58 on
page 108). Additional information concerning
the FPU Clock Counts is presented on page
107.

2.3.2.1. Assumptions Made in Determining Instruction Clock
Count
The following assumptions have been made in
presenting the clock count values for the individual instructions:
• All clock counts refer to the internal CPU
internal clock frequency. For example, the
clock counts for a clock-doubled processor
refer to 50 MHz clocks while the external
clock is 25 MHz.
• The instruction has been prefetched,
decoded and is ready for execution.
• Bus cycles do not require wait states.
• There are no local bus HOLD requests
delaying processor access to the bus.
• No exceptions are detected during instruction execution.
• If an effective address is calculated, it
does not use two general register components. One register, scaling and displacement can be used within the clock count
shown. However, if the effective address
calculation uses two general register
components, add one clock to the clock
count shown.

• For non-cached memory accesses, add
two clocks (DX) or four clocks (DX2),
assuming zero wait state memory
accesses.
• Locked cycles are not cacheable. Therefore, using the LOCK prefix with an instruction adds additional clocks as specified in
instruction 9 above.

2.3.2.2. CPU Instruction Set Summary
Table Abbreviations
The clock counts listed in the CPU Instruction
Set Summary Table are grouped by operating
mode and whether there is a register/cache hit
or a cache miss. In some cases, more than
one clock count is shown in a column for a
given instruction, or a variable is used in the
clock count. The abbreviations used for these
conditions are listed in Table 2.53.
Table 2.53 CPU Clock Count Abbreviations
Clock
Count
Symbol

Explanation

/

Register operand/memory operand.

n

Number of times operation is repeated.

L

Level of the stack frame.

|

Conditional jump taken | Conditional jump
not taken.
(e.g. “4|1” = 4 clocks if jump taken, 1 clock if
jump not taken)

\

CPL ≤ IOPL \ CPL > IOPL
(where CPL = Current Privilege Level, IOPL =
I/O Privilege Level)

• All clock counts assume aligned 32-bit
memory/ IO operands.
• If instructions access a 32-bit operand on
odd addresses, add one clock for read or
write and add two clocks for read and write.

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2.3.2.3. CPU Instruction Set Summary Table Flags Table
The CPU Instruction Set Summary Table lists
nine flags that are affected by the execution of
instructions. The conventions shown in Table 2.54
are used to identify the different flags. Table
2.55 lists the conventions used to indicate
what action the instruction has on the particular flag.

Table 2.54 Flag Abbreviations (cont.)
Abbreviation
AF

Auxiliary Flag

PF

Parity Flag

CF

Carry Flag

Table 2.55 Action of Instruction on Flag

Table 2.54 Flag Abbreviations
Abbreviation

Name Of Flag

Instruction
Table Symbol

Name Of Flag

Action

x

Flag is modified by the instruction.

OF

Overflow Flag

DF

Direction Flag

-

Flag is not changed by the instruction.

IF

Interrupt Enable Flag

0

Flag is reset to “0”.

1

Flag is set to “1”.

TF

Trap Flag

SF

Sign Flag

ZF

Zero Flag

Table 2.56 Processor Core Instruction Set Summary
Real
Mode

Flags

Instruction

Opcode

O D I T S Z A P C
F F F F F F F F F

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

AAA ASCII Adjust AL after Add

37

-

- -

- -

-

x

-

x

4

AAD ASCII Adjust AX before Divide

D5 0A

-

-

-

-

x

x

-

x

-

4

4

AAM ASCII Adjust AX after Multiply

D4 0A

-

-

-

-

x

x

-

x

-

16

16

AAS ASCII Adjust AL after Subtract

3F

-

-

-

-

-

-

x

-

x

4

4

Register to Register

1 [00dw] [11 reg r/m]

x

-

-

-

x

x

x

x

x

1

1

Register to Memory

1 [000w] [mod reg r/m]

3

3

Prot’d
Mode

Notes

4

ADC Add with Carry

Memory to Register

1 [001w] [mod reg r/m]

Immediate to Register/Memory

8 [00sw] [mod 010 r/m]#

Immediate to Accumulator

1 [010w] #

3

3

1/3

1/3

1

1

1

1

3

3

b

h

b

h

b

h

ADD Integer Add
Register to Register

0 [00dw] [11 reg r/m]

Register to Memory

0 [000w] [mod reg r/m]

Memory to Register

0 [001w] [mod reg r/m]

Immediate to Register/Memory

8 [00sw] [mod 000 r/m]#

Immediate to Accumulator

0 [010w] #

x

-

-

-

x

x

x

x

x

3

3

1/3

1/3

1

1

AND Boolean AND
Register to Register

2 [00dw] [11 reg r/m]

Register to Memory

2 [000w] [mod reg r/m]

Memory to Register

2 [001w] [mod reg r/m]

Immediate to Register/Memory

8 [00sw] [mod 100 r/m]#

Immediate to Accumulator

2 [010w] #

0 -

-

-

x

x

-

x

0

1

1

3

3

3

3

1/3

1/3

1

1

ARPL Adjust Requested Privilege Level

ZFx86 Data Book 1.0 Rev D

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Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction
From Register/Memory

Opcode

O D I T S Z A P C
F F F F F F F F F

63 [mod reg r/m]

-

-

-

-

-

x

-

-

-

62 [mod reg r/m]

-

-

-

-

-

-

-

-

-

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

Prot’d
Mode

Notes

6/10

a

h

11+INT

11+INT

b, e

g,h,j,k,r

11

11

BOUND Check Array Boundaries
If Out of Range (Int 5)
If In Range
BSF Scan Bit Forward
Register, Register/Memory

0F BC [mod reg r/m]

-

-

-

-

-

x

-

-

-

5/7+n

5/7+n

b

h

0F BC [mod reg r/m]

-

-

-

-

-

x

-

-

-

5/7+n

5/7+n

b

h

0F C[1 reg]

-

-

-

-

-

-

-

-

-

4

4

Register/Memory, Immediate

0F BA [mod 100 r/m]#

-

-

-

-

-

-

-

-

x

3/4

3/4

b

h

Register/Memory, Register

0F A3 [mod reg r/m]

3/6

3/6

4/5

4/5

b

h

5/8

5/8

4/5

4/5

b

h

5/8

5/8

3/5

3/5

b

h

4/7

4/7

b

h,j,k,r

BSR Scan Bit Reverse
Register, Register/Memory
BSWAP Byte Swap
BT Test Bit

BTC Test Bit and Complement
Register/Memory, Immediate

0F BA [mod 111 r/m]#

Register/Memory, Register

0F BB [mod reg r/m]

-

-

-

-

-

-

-

-

x

BTR Test Bit and Reset
Register/Memory, Immediate

0F BA [mod 110 r/m]#

Register/Memory, Register

0F B3 [mod reg r/m]

-

-

-

-

-

-

-

-

x

BTS Test Bit and Set
Register/Memory

0F BA [mod 101 r/m

Register (short form)

0F AB [mod reg r/m]

-

-

-

-

-

-

-

-

x

CALL Subroutine Call
Direct Within Segment

E8 +++

7

7

Register/Memory Indirect Within Segment

FF [mod 010 r/m]

-

-

-

-

-

-

-

-

-

8/9

8/9

Direct Intersegment
-Call Gate to Same Privilege
-Call Gate to Different Privilege No Par’s
-Call Gate to Different Privilege m Par’s
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task

9A [unsigned full offset,
selector]

12

30
41
83
81+4x
235
262
179
238
265
182

Indirect Intersegment
-Call Gate to Same Privilege
-Call Gate to Different Privilege No Par’s
-Call Gate to Different Privilege m Par’s
-16-bit Task to 16-bit TSS
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task

FF [mod 011 r/m]

14

14
43
85

86+4x
237
264
181
240
267
184

CBW Convert Byte to Word

98

-

-

-

-

-

-

-

-

-

3

3

CDQ Convert DWORD to Quadword

99

-

-

-

-

-

-

-

-

-

1

1

CLC Clear Carry Flag

F8

-

-

-

-

-

-

-

-

0

1

1

CLD Clear Direction Flag

FC

-

0 -

-

-

-

-

-

-

1

1

CLI Clear Interrupt Flag

FA

-

-

0 -

-

-

-

-

-

7

7

ZFx86 Data Book 1.0 Rev D

m

Page 95

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

O D I T S Z A P C
F F F F F F F F F

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

CLTS Clear Task Switched Flag

0F 06

-

-

-

-

-

-

-

-

-

5

5

CMC Complement the Carry Flag

F5

-

-

-

-

-

-

-

-

x

1

1

x

-

-

-

x

x

x

x

x

Prot’d
Mode

Notes
c

l

b

h

b

h

b

h

b,e

e,h

b

h

CMP Compare Integers
Register to Register

3 [10dw] [11 reg r/m]

Register to Memory

3 [101w] [mod reg r/m]

1

1

Memory to Register

3 [100w] [mod reg r/m]

3

3

Immediate to Register/Memory

8 [00sw] [mod 111 r/m] #

3

3

Immediate to Accumulator

3 [110w] ###

1/3

1/3

CMPS Compare String

A [011w]

x

-

-

-

x

x

x

x

x

7

7

Register1, Register2

0F B [000w] [11 reg2 reg1]

x

-

-

-

x

x

x

x

x

5

5

Memory, Register

0F B [000w] [mod reg r/m]

7

7

CMPXCHG Compare and Exchange

CWD Convert Word to DWORD

99

-

-

-

-

-

-

-

-

-

1

1

CWDE Convert Word to DWORD Extended

98

-

-

-

-

-

-

-

-

-

3

3

DAA Decimal Adjust AL after Add

27

-

-

-

-

x

x

x

x

x

4

4

DAS Decimal Adjust AL after Subtract

2F

-

-

-

-

x

x

x

x

x

4

4

Register/Memory

F [111w] [mod 001 r/m]

x

-

-

-

x

x

x

x

-

1/3

1/3

Register (short form)

4 [1 reg]

1

1

14/15
22/23
38/39

14/15
22/23
38/39

DEC Decrement by 1

DIV Unsigned Divide
Accumulator by Register/Memory
Divisor: Byte
WORD
DWORD

F [011w] [mod 110 r/m]

-

-

-

-

-

-

-

-

-

ENTER Enter New Stack Frame
Level = 0

C8 ++[8-bit Level]

-

-

-

-

-

-

-

-

-

Level = 1
Level (L) > 1
HLT Halt

F4

-

-

-

-

-

-

-

-

-

F [011w] [mod 111 r/m]

-

-

-

-

-

-

-

-

-

7

7

10

10

6+4*L

6+4*L

3

3

19/20
27/28
43/44

19/20
27/28
43/44

l

IDIV Integer (Signed) Divide
Accumulator by Register/Memory
Divisor: Byte
WORD
DWORD

b,e

e,h

IMUL Integer (Signed) Multiply

ZFx86 Data Book 1.0 Rev D

Page 96

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

Accumulator by Register/Memory
Multiplier:
Byte
WORD
DWORD

F [011w] [mod 101 r/m]

Register with Register/Memory
Multiplier:
WORD
Doubleword
Register/Memory with Immediate to
Register2
Multiplier:
Word
DWORD

O D I T S Z A P C
F F F F F F F F F
x

-

-

-

-

-

-

-

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

x

Notes
b

3/5
3/5
7/9

3/5
3/5
7/9

0F AF [mod reg r/m]

3/5
3/5
7/9

3/5
3/5
7/9

6 [10s1] [mod reg r/m] #

3/5
3/5
7/9

3/5
3/5
7/9

Prot’d
Mode

h

IN Input from I/O Port
Fixed Port

E [010w] [port number]

-

-

-

-

-

-

-

-

-

16

6/19

Variable Port

E [110w]

16

6/19

6 [110w]

-

-

-

-

-

-

-

-

-

20

6/19

b

h,m

Register/Memory

F [111w] [mod 000 r/m]

x

-

-

-

x

x

x

x

-

1/3

1/3

b

h

Register (short form)

4 [0 reg]

1

1

INS Input String from I/O Port

m

INC Increment by 1

INT Software Interrupt

ZFx86 Data Book 1.0 Rev D

Page 97

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction
INT i

Opcode
CD [i]

O D I T S Z A P C
F F F F F F F F F
-

x

0

-

-

-

-

Clock Count
(Reg/Cache Hit)

-

Protected Mode:
-Interrupt or Trap to Same Privilege
-Interrupt or Trap to Different Privilege
-16-bit Task to 16-bit TSS by Task Gate
-16-bit Task to 32-bit TSS by Task Gate
-16-bit Task to V86 by Task Gate
-16-bit Task to 16-bit TSS by Task Gate
-32-bit Task to 32-bit TSS by Task Gate
-32-bit Task to V86 by Task Gate
-V86 to 16-bit TSS by Task Gate
-V86 to 32-bit TSS by Task Gate
-V86 to Privilege 0 by Trap Gate/Int Gate

INT 3

Prot’d
Mode

Notes
g,j,k,r

14

49
77
233
260
177
236
263
180
236
263
93
CC

14

49
77
233
260
177
236
263
180
236
263
93
CE
1
15

Protected Mode
Interrupt or Trap to Same Privilege
Interrupt or Trap to Different Priv.
16-bit Tsk - 16-bit TSS by Tsk Gate
16-bit Tsk - 32-bit TSS by Tsk Gate
16-bit Task to V86 by Task Gate
32-bit Tsk - 16-bit TSS by Tsk Gate
32-bit Tsk - 32-bit TSS by Tsk Gate
32-bit Task to V86 by Task Gate
V86 to 16-bit TSS by Task Gate
V86 to 32-bit TSS by Task Gate
V86 to Priv. 0 by Trap Gate/Int Gate

1

49
77
233
260
177
236
263
180
236
263
93

INVD Invalidate Cache

0F 08

-

-

-

-

-

-

-

-

-

4

4

INVLPG Invalidate TLB Entry

0F 01 [mod 111 r/m]

-

-

-

-

-

-

-

-

-

4

4

ZFx86 Data Book 1.0 Rev D

Real
Mode

b,e

Protected Mode
Interrupt or Trap to Same Privilege
Interrupt or Trap to Different Priv.
16-bit Tsk - 16-bit TSS by Tsk Gate
16-bit Tsk - 32-bit TSS by Tsk Gate
16-bit Task to V86 by Task Gate
32-bit Tsk - 16-bit TSS by Tsk Gate
32-bit Tsk - 32-bit TSS by Tsk Gate
32-bit Task to V86 by Task Gate
V86 to 16-bit TSS by Task Gate
V86 to 32-bit TSS by Task Gate
V86 to Priv. 0 by Trap Gate/Int Gate
INTO
If OF==0
If OF==1 (INT 4)

Prot’d
Mode

Page 98

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction
IRET Interrupt Return

Opcode
CF

O D I T S Z A P C
F F F F F F F F F
x

x

x

x

x

x

x

x

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

Prot’d
Mode

Notes

x

g,h,j,k,r
14

Real Mode
Protected Mode:
-Within Task to Same Privilege
-Within Task to Different Privilege
-16-bit Task to 16-bit Task
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task

31
66
229
256
173
232
259
176

JB/JNAE/JC Jump on Below/Not Above or Equal/Carry
8-bit Displacement

72 +

Full Displacement

0F 82 +++

-

-

-

-

-

-

-

-

-

4|1

6|1

4|1

6|1

4|1

6|1

r

JBE/JNA Jump on Below or Equal/Not Above
8-bit Displacement

76 +

Full Displacement

0F 86 +++

r

-

-

-

-

-

-

-

-

4|1

6|1

E3 +

-

-

-

-

-

-

-

-

-

7|3

7|3

r

8-bit Displacement

74 +

-

-

-

-

-

-

-

-

-

4|1

6|1

r

Full Displacement

0F 84 +++

4|1

6|1

JCXZ/JECXZ Jump on CX/ECX Zero
JE/JZ Jump on Equal/Zero

JECXZ Jump on EXC Zero

E3 +

-

-

-

-

-

-

-

-

-

7|3

7|3

r

8-bit Displacement

7C +

-

-

-

-

-

-

-

-

-

4|1

6|1

r

Full Displacement

0F 8C +++

4|1

6|1

4|1

6|1

4|1

6|1

4
4
6/8

6
6
6/8
26
37
238
265
182
241
268
185
30
39
240
267
184
243
270
187

JL/JNGE Jump on Less/Not Greater or Equal

JLE/JNG Jump on Less or Equal/Not Greater
8-bit Displacement

7E +

Full Displacement

0F 8E +++

-

-

-

-

-

-

-

-

-

r

JMP Unconditional Jump
Short
Direct within Segment
Register/Memory Indirect Within Segment
Direct Intersegment
Call Gate Same Privilege Level
16-bit Task to 16-bit TSS
16-bit Task to 32-bit TSS
16-bit Task to V86 Task
32-bit Task to 16-bit TSS
32-bit Task to 32-bit TSS
32-bit Task to V86 Task
Indirect Intersegment
Call Gate Same Privilege Level
16-bit Task to 16-bit TSS
16-bit Task to 32-bit TSS
16-bit Task to V86 Task
32-bit Task to 16-bit TSS
32-bit Task to 32-bit TSS
32-bit Task to V86 Task

EB
E9
FF
EA

+
+++
[mod 100 r/m]
[full offset, selector]

-

-

-

-

-

-

-

-

-

9

FF [mod 101 r/m]

b

h,j,k,r

JNB/JAE/JNC Jump on Not Below/Above or Equal/Not Carry
8-bit Displacement

73 +

Full Displacement

0F 83 +++

-

-

-

-

-

-

-

-

4|1

6|1

4|1

6|1

r

JNBE/JA Jump on Not Below or Equal/Above

ZFx86 Data Book 1.0 Rev D

Page 99

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

8-bit Displacement

77 +

Full Displacement

0F 87 +++

Prot’d
Mode

O D I T S Z A P C
F F F F F F F F F

Clock Count
(Reg/Cache Hit)

-

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

4|1

6|1

2

2

-

-

-

-

-

-

-

Real
Mode

Prot’d
Mode

Notes
r

JNE/JNZ Jump on Not Equal/Not Zero
8-bit Displacement

75 +

Full Displacement

0F 85 +++

-

-

-

-

-

-

-

-

r

JNL/JGE Jump on Not Less/Greater or Equal
8-bit Displacement

7D +

Full Displacement

0F 8D +++

-

-

-

-

-

-

-

-

r

JNLE/JG Jump on Not Less or Equal/Greater
8-bit Displacement

7F +

Full Displacement

0F 8F +++

-

-

-

-

-

-

-

-

r

JNO Jump on Not Overflow
8-bit Displacement

71 +

Full Displacement

0F 81 +++

-

-

-

-

-

-

-

-

r

JNP/JPO Jump on Not Parity/Parity Odd
8-bit Displacement

7B +

Full Displacement

0F 8B +++

-

-

-

-

-

-

-

-

r

JNS Jump on Not Sign
8-bit Displacement

79 +

Full Displacement

0F 89 +++

-

-

-

-

-

-

-

-

r

JO Jump on Overflow
8-bit Displacement

70 +

Full Displacement

0F 80 +++

-

-

-

-

-

-

-

-

r

JP/JPE Jump on Parity/Parity Even
8-bit Displacement

7A +

Full Displacement

0F 8A +++

-

-

-

-

-

-

-

-

r

JS Jump on Sign
8-bit Displacement

78 +

Full Displacement

0F 88 +++

LAHF Load AH with Flags

-

-

-

-

-

-

-

-

r

9F

-

-

-

-

-

-

-

-

-

0F 02 [mod reg r/m]

-

-

-

-

-

x

-

-

-

11/12

a

g,h,j,p

C5 [mod reg r/m]

-

-

-

-

-

-

-

-

-

6

19

b

h,i,j

8D [mod reg r/m]

-

-

-

-

-

-

-

-

-

2

2

LAR Load Access Rights
From Register/Memory
LDS Load Pointer to DS
LEA Load Effective Address
No Index Register
With Index Register

3

3

LEAVE Leave Current Stack Frame

C9

-

-

-

-

-

-

-

-

-

3

3

b

h

LES Load Pointer to ES

C4 [mod reg r/m]

-

-

-

-

-

-

-

-

-

6

19

b

h,i,j

LFS Load Pointer to FS

0F B4 [mod reg r/m]

-

-

-

-

-

-

-

-

-

6

19

b

h,i,j

LGDT Load GDT Register

0F 01 [mod 010 r/m]

-

-

-

-

-

-

-

-

-

9

9

b,c

h,l

LGS Load Pointer to GS

0F B5 [mod reg r/m]

-

-

-

-

-

-

-

-

-

6

19

b

h,i,j

LIDT Load IDT Register

0F 01 [mod 011 r/m]

-

-

-

-

-

-

-

-

-

9

9

b,c

h,l

0F 00 [mod 010 r/m]

-

-

-

-

-

-

-

-

-

16/17

a

g,h,j,l

LLDT Load LDT Register
From Register/Memory
LMSW Load Machine Status Word

ZFx86 Data Book 1.0 Rev D

Page 100

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction
From Register/Memory

Opcode

O D I T S Z A P C
F F F F F F F F F

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

Prot’d
Mode

Notes

0F 01 [mod 110 r/m]

-

-

-

-

-

-

-

-

-

5

5

b,c

h,l

LODS Load String

A [110 w]

-

-

-

-

-

-

-

-

-

4

4

b

h

LOOP — Offset Loop/No Loop

E2 +

-

-

-

-

-

-

-

-

-

7|3

9|3

LOOPNZ/LOOPNE — Offset

E0 +

-

-

-

-

-

-

-

-

-

7|3

9|3

r

LOOPZ/LOOPE — Offset

E1 +

-

-

-

-

-

-

-

-

-

7|3

9|3

r

0F 03 [mod reg r/m]

-

-

-

-

-

x

-

-

-

0F B2 [mod reg r/m]

-

-

-

-

-

-

-

-

-

0F 00 [mod 011 r/m]

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

r

LSL Load Segment Limit
From Register/Memory
LSS Load Pointer to SS

6

14/15

a

g,h,j,p

19

a

h,i,j

16/17

a

g,h,j,l

b

h,i,j

LTR Load Task Register
From Register/Memory
MOV Move Data
Register to Register/Memory

8 [100w] [mod reg r/m]

1/2

1/2

Register/Memory to Register

8 [100w] [mod reg r/m]

1/2

1/2

Immediate to Register/Memory

C [011w] [mod 000 r/m] ###

1/2

1/2

Immediate to Register (short form)

B [w reg] ###

1

1

Memory to Accumulator (short form)

A [000w] +++

2

2

Accumulator to Memory (short form)

A [001w] +++

1/2

1/2

Register/Memory to Segment Register

8E [mod sreg3 r/m]

2/3

15/16

Segment Register to Register/Memory

8C [mod sreg3 r/m]

1/2

1/2

11/3/3

11/3/3

MOV Move to/from Control/Debug/Test Regs

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

l

Register to CR0/CR2/CR3

0F 22 [11 eee reg]

CR0/CR2/CR3 to Register

0F 20 [11 eee reg]

1/3/3

1/3/3

Register to DR0-DR3

0F 23 [11 eee reg]

1

1

DR0-DR3 to Register

0F 21 [11 eee reg]

3

3

Register to DR6-DR7

0F 23 [11 eee reg]

1

1

DR6-DR7 to Register

0F 21 [11 eee reg]

3

3

Register to TR3-5

0F 26 [11 eee reg]

5

5

TR3-5 to Register

0F 24 [11 eee reg]

5

5

Register to TR6-TR7

0F 26 [11 eee reg]

1

1

TR6-TR7 to Register

0F 24 [11 eee reg]

3

3

MOVS Move String

l

A [010w]

-

-

-

-

-

-

-

-

-

5

5

b

h

0F B[111w] [mod reg r/m]

-

-

-

-

-

-

-

-

-

1/3

1/3

b

h

0F B[011w] [mod reg r/m]

-

-

-

-

-

-

-

-

-

2/3

2/3

b

h

F [011w] [mod 100 r/m]

x

-

-

-

b

h

3/5
3/5

3/5
3/5

7/9

7/9
b

h

MOVSX Move with Sign Extension
Register from Register/Memory
MOVZX Move with Zero Extension
Register from Register/Memory
MUL Unsigned Multiply
Accumulator with Register/Memory
Multiplier:
Byte
WORD
DWORD

x

NEG Negate Integer

F [011w] [mod 011 r/m]

x

-

-

-

x

x

x

x

x

1/3

1/3

NOP No Operation

90

-

-

-

-

-

-

-

-

-

1

1

NOT Boolean Complement

F [011w] [mod 010 r/m]

-

-

-

-

-

-

-

-

-

1/3

1/3

b

h

OIO Official Invalid Opcode

0F FF

-

-

0 -

-

-

-

-

-

15

49-300

t

t

ZFx86 Data Book 1.0 Rev D

Page 101

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

O D I T S Z A P C
F F F F F F F F F

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

Prot’d
Mode

Notes

OR Boolean OR
Register to Register

0 [10dw] [11 reg r/m]

Register to Memory

0 [100w] [mod reg r/m]

Memory to Register

0 [101w] [mod reg r/m]

Immediate to Register/Memory

8 [00sw] [mod 001 r/m] ###

Immediate to Accumulator

0 [110w] ###

0 -

-

-

x

x

x

x

0

1

1

3

3

3

3

1/3

1/3

1

1

b

h

OUT Output to Port
Fixed Port

E [011w] #

Variable Port

E [111w]

-

-

-

-

-

-

-

-

OUTS Output String

6 [111w]

-

-

-

-

-

-

-

-

Register/Memory

8F [mod 000 r/m]

-

-

-

-

-

-

-

-

Register (short form)

5 [1 reg]

-

18

4/17

18

4/17

m

-

20

6/19

b

h,m

-

3/5

3/5

b

h,i,j

3

3

POP Pop Value off Stack

Segment Register (ES, CS, SS, DS)

[000 sreg2 111]

4

18

Segment Register (ES, CS, SS, DS, FS,
GS)

0F [10 sreg3 001]

4

18

POPA Pop All General Registers

61

-

-

-

-

-

-

-

-

-

18

18

b

h

POPF Pop Stack into FLAGS

9D

x

x

x

x

x

x

x

x

x

4

4

b

h,n

Assert Hardware LOCK Prefix

F0

-

-

-

-

-

-

-

-

-

Address Size Prefix

67

Operand Size Prefix

66

Segment Override Prefix
-CS
-DS
-ES
-FS
-GS
-SS

2E
3E
26
64
65
36

-

-

-

-

-

-

-

-

-

PREFIX BYTES
m

PUSH Push Value onto Stack
Register/Memory

FF [mod 110 r/m]

2/4

2/4

Register (short form)

5 [0 reg]

2

2

[000 sreg2 110]

2

2

0F [10 sreg3 000]

2

2

Segment Register (ES, CS, SS, DS)
Segment Register (ES. CS. SS, DS, FS,
GS)
Immediate

6 [10s0] ###

b

h

2

2

PUSHA Push All General Registers

60

-

-

-

-

-

-

-

-

-

17

17

b

h

PUSHF Push FLAGS Register

9C

-

-

-

-

-

-

-

-

-

2

2

b

h

D [000w] [mod 010 r/m]

x

-

-

-

-

-

-

-

x

9/9

9/9

b

h

b

h

RCL Rotate Through Carry Left
Register/Memory by 1
Register/Memory by CL

D [001w] [mod 010 r/m]

u -

-

-

-

-

-

-

x

9/9

9/9

Register/Memory by Immediate

C [000w] [mod 010 r/m] #

u -

-

-

-

-

-

-

x

9/9

9/9

RCR Rotate Through Carry Right
Register/Memory by 1

D [000w] [mod 011 r/m]

x

-

-

-

-

-

-

-

x

9/9

9/9

Register/Memory by CL

D [001w] [mod 011 r/m]

u -

-

-

-

-

-

-

x

9/9

9/9

Register/Memory by Immediate

C [000w] [mod 011 r/m] #

u -

-

-

-

-

-

-

x

9/9

9/9

ZFx86 Data Book 1.0 Rev D

Page 102

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

Prot’d
Mode

O D I T S Z A P C
F F F F F F F F F

Clock Count
(Reg/Cache Hit)

Real
Mode

Prot’d
Mode

Notes

REP INS Input String

F2 6[110w]

-

-

-

-

-

-

-

-

-

20+9n

5+9n\
18+9n

b

h,m

REP LODS Load String

F2 A[110w]

-

-

-

-

-

-

-

-

-

4+5n

4+5n

b

h

REP MOVS Move String

F2 A[010w]

-

-

-

-

-

-

-

-

-

5+4n

5+4n

b

h

REP OUTS Output String

F2 6[111w]

-

-

-

-

-

-

-

-

-

20+4n

5+4n\
18+4n

b

h,m

REP STOS Store String

F2 A[101w]

-

-

-

-

-

-

-

-

-

3+4n

3+4n

b

h

F3 A[011w]

x

-

-

-

x

x

x

x

x

5+8n

5+8n

b

h

F3 A[111w]

x

-

-

-

x

x

x

x

x

4+5n

4+5n

b

h

F2 A[011w]

x

-

-

-

x

x

x

x

x

5+8n

5+8n

b

h

F2 A[111w]

x

-

-

-

x

x

x

x

x

4+5n

4+5n

b

h

Within Segment

C3

-

-

-

-

-

-

-

-

-

10

10

b

g,h,j,k,r

Within Segment Adding Immediate to SP

C2 ##

10

10

b

h

b

h

REPE CMPS Compare String
Find non-match
REPE SCAS Scan String
Find non-AL/AX/EAX
REPNE CMPS Compare String
Find match
REPNE SCAS Scan String
Find AL/AX/EAX
RET Return from Subroutine

Intersegment

CB

13

26

Intersegment Adding Immediate to SP

CA ##

13

26

Protected Mode: Different Privilege Level
-Intersegment
-Intersegment Adding Immediate to SP

61
61

ROL Rotate Left
Register/Memory by 1

D[000w] [mod 000 r/m]

x

-

-

-

-

-

-

-

x

2/4

2/4

Register/Memory by CL

D[001w] [mod 000 r/m]

3/5

3/5

Register/Memory by Immediate

C[000w] [mod 000 r/m] #

2/4

2/4

ROR Rotate Right
Register/Memory by 1

D[000w] [mod 001 r/m]

2/4

2/4

Register/Memory by CL

D[001w] [mod 001 r/m]

3/5

3/5

Register/Memory by Immediate

C[000w] [mod 001 r/m] #

2/4

2/4

x

-

-

-

-

-

-

-

x

RSDC Restore Segment Register and
Descriptor

0F 79 [mod sreg3 r/m]

-

-

-

-

-

-

-

-

-

10

10

s

s

RSLDT Restore LDTR and Descriptor

0F 7B [mod 000 r/m]

-

-

-

-

-

-

-

-

-

10

10

s

s

RSM Resume from SMM Mode

0F AA

-x -

-

-

-

-

-

-

-

76

76

s

s

RSTS Restore TSR and Descriptor

0F 7D [mod 000 r/m]

-

-

-

-

-

-

-

-

-

10

10

s

s

SAHF Store AH in FLAGS

9E

x

-

-

-

x

x

-

x

x

2

2
b

h

b

h

SAL Shift Left Arithmetic
Register/Memory by 1

D[000w] [mod 100 r/m]

x

-

-

-

x

x

-

x

x

2/4

2/4

Register/Memory by CL

D[001w] [mod 100 r/m]

u -

-

-

x

x

u x

x

3/5

3/5

Register/Memory by Immediate

C[000w] [mod 100 r/m] #

u -

-

-

x

x

u x

x

2/4

2/4

x

-

-

x

x

x

x

SAR Shift Right Arithmetic
Register/Memory by 1

D[000w] [mod 111 r/m]

2/4

2/4

Register/Memory by CL

D[001w] [mod 111 r/m]

3/5

3/5

Register/Memory by Immediate

C[000w] [mod 111 r/m] #

2/4

2/4

ZFx86 Data Book 1.0 Rev D

-

x

Page 103

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

O D I T S Z A P C
F F F F F F F F F

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

Prot’d
Mode

Notes

SBB Integer Subtract with Borrow
Register to Register

1[10dw] [11 reg r/m]

Register to Memory

1[100w] [mod reg r/m]

Memory to Register

1[101w] [mod reg r/m]

Immediate to Register/Memory

8[00sw] [mod 011 r/m] ###

Immediate to Accumulator (short form)

1[110w] ###

SCAS Scan String

A [111w]

x

x

-

-

-

-

x

x

x

x

x

1

1

3

3

3

3

1/3

1/3

1

1

-

-

x

x

x

x

x

5

5

b

h

b

h

SETB/SETNAE/SETC Set Byte on Below/Not Above or Equal to Register/Memory
0F 92 [mod 000 r/m]

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

SETBE/SETNA Set Byte on Below or Equal/Not Above to Register/Memory
0F 96 [mod 000 r/m]
SETE/SETZ Set Byte on Equal/Zero to Register/Memory
0F 94 [mod 000 r/m]
SETL/SETNGE Set Byte on Less/Not Greater or Equal to Register/Memory
0F 9C [mod 000 r/m]
SETLE/SETNG Set Byte on Less or Equal/Not Greater to Register/Memory
0F 9E [mod 000 r/m]

SETNB/SETAE/SETNC Set Byte on Not Below/Above or Equal/Not Carry to Register/Memory
0F 93 [mod 000 r/m]

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

-

-

-

-

-

-

-

-

-

2/2

2/2

h

0F 98 [mod 000 r/m]

-

-

-

-

-

-

-

-

-

2/2

2/2

h

0F 01 [mod 000 r/m]

-

-

-

-

-

-

-

-

-

6

6

b,c

h

0F 01 [mod 001 r/m]

-

-

-

-

-

-

-

-

-

6

6

b,c

h

0F 01 [mod 000 r/m]

-

-

-

-

-

-

-

-

-

1/2

a

h

SETNBE/SETA Set Byte on Not Below or Equal/Above to Register/Memory
0F 97 [mod 000 r/m]
SETNE/SETNZ Set Byte on Not Equal/Not Zero to Register/Memory
0F 95 [mod 000 r/m]
SETNL/SETGE Set Byte on Not Less/Greater or Equal to Register/Memory
0F 9D [mod 000 r/m]
SETNLE/SETG Set Byte on Not Less or Equal/Greater to Register/Memory
0F 9F [mod 000 r/m]
SETNO Set Byte on Not Overflow to Register/Memory
0F 91 [mod 000 r/m]
SETNP/SETPO Set Byte on Not Parity/Parity Odd to Register/Memory
0F 9B [mod 000 r/m]
SETNS Set Byte on Not Sign to Register/Memory
0F 99 [mod 000 r/m]
SETO Set Byte on Overflow to Register/Memory
0F 90 [mod 000 r/m]
SETP/SETPE Set Byte on Parity/Parity Even to Register/Memory
0F 9A [mod 000 r/m]
SETS Set Byte on Sign to Register/Memory to Register/Memory

SGDT Store GDT Register to Register/Memory

SIDT Store IDT Register to Register/Memory
SLDT Store LDT Register to Register/Memory
STR Store Task Register to Register/Memory

ZFx86 Data Book 1.0 Rev D

Page 104

2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

O D I T S Z A P C
F F F F F F F F F

0F 00 [mod 001 r/m]

-

-

-

-

-

-

-

-

-

SMSW Store Machine Status Word

0F 01 [mod 100 r/m]

-

-

-

-

-

-

-

-

-

STOS Store String

A [101w]

-

-

-

-

-

-

-

-

x

-

-

-

x

x

-

x

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)

Prot’d
Mode

Notes

1/2

a

1/2

1/2

b,c

h
h

-

3

3

b

h

x

b

h

s

s

SHL Shift Left Logical
Register/Memory by 1

D [000w] [mod 100 r/m]

1/3

1/3

Register/Memory by CL

D [001w] [mod 100 r/m]

2/4

2/4

Register/Memory by Immediate

C [000w] [mod 100 r/m] #

1/3

1/3

1/3

1/3

3/5

3/5

SHLD Shift Left Double
Register/Memory by Immediate

0F A4 [mod reg r/m] #

Register/Memory by CL

0F A5 [mod reg r/m]

-

-

-

-

x

x

-

x

x

SHR Shift Right Logical
Register/Memory by 1

D [000w] [mod 101 r/m]

1/3

1/3

Register/Memory by CL

D [001w] [mod 101 r/m]

x

-

-

-

x

x

-

x

x

2/4

2/4

Register/Memory by Immediate

C [000w] [mod 101 r/m] #

1/3

1/3

1/3

1/3

3/5

3/5

-

24

24

SHRD Shift Right Double
Register/Memory by Immediate

0F AC [mod reg r/m] #

Register/Memory by CL

0F AD [mod reg r/m]

-

-

-

SMINT Software SMM Entry

0F 7E

-

-

-

-

-

x

-

x

-

-

-

x

-

x

STC Set Carry Flag

F9

-

-

-

-

-

-

-

-

1

1

1

STD Set Direction Flag

FD

-

1 -

-

-

-

-

-

-

1

1

STI Set Interrupt Flag

FB

-

-

1 -

-

-

-

-

-

7

7

Register to Register

2 [10dw] [11 reg r/m]

x

- -

x

x

x

x

x

1

1

Register to Memory

2 [100w] [mod reg r/m]

3

3

m

SUB Integer Subtract

Memory to Register

2 [101w] [mod reg r/m]

Immediate to Register/Memory

8 [00sw] [mod 101 r/m] ###

Immediate to Accumulator (short form)

2 [110w] ###

-

3

3

1/3

1/3

1

1

b

h

s

SVDC Save Segment Register and Descriptor 0F 78 [mod sreg3 r/m]

-

-

-

-

-

-

-

-

-

18

18

s

SVLDT Save LDTR and Descriptor

0F 7A [mod 000 r/m]

-

-

-

-

-

-

-

-

-

18

18

s

s

SVTS Save TSR and Descriptor

0F 7C [mod 000 r/m]

-

-

-

-

-

-

-

-

-

18

18

s

s

Register/Memory and Register

8 [010w] [mod reg r/m]

0

- -

-

x

x

-

x

0

1/3

1/3

b

h

Immediate Data and Register/Memory

F [011w] [mod 000 r/m] #

1/3

1/3

Immediate Data and Accumulator

A [100w] #

1

1

TEST Test Bits

VERR Verify Read Acces to Register/Memory
0F 00 [mod 100 r/m]

-

-

-

-

-

x

-

-

-

9/10

a

g,h,j,p

0F 00 [mod 101 r/m]

-

-

-

-

-

x

-

-

-

9/10

a

g,h,j,p

WAIT Wait Until FPU Not Busy

9B

-

-

-

-

-

-

-

-

-

5

5

WBINVD Write-Back and Invalidate Cache

0F 09

-

-

-

-

-

-

-

-

-

4

4

VERW Verify Write Access to Register/Memory

XADD Exchange and Add

ZFx86 Data Book 1.0 Rev D

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2
Table 2.56 Processor Core Instruction Set Summary (cont.)
Real
Mode

Flags

Instruction

Opcode

Register1, Register2

0F C[000w] [11 reg2 reg1]

Memory, Register

0F C[000w] [mod reg r/m]

O D I T S Z A P C
F F F F F F F F F
x

-

-

-

x

x

x

x

x

Prot’d
Mode

Real
Mode

Clock Count
(Reg/Cache Hit)
3

3

6

6

3/4

3/4

3

3

3

3

Prot’d
Mode

Notes

XCHG Exchange
Register/Memory with Register

8[011w] [mod reg r/m]

Register with Accumulator

9[0 reg]

XLAT Translate Byte

-

-

-

-

-

-

-

-

-

D7

-

-

-

-

-

-

-

-

-

Register to Register

3 [00dw] [11 reg r/m]

0 -

-

-

x

x

-

x

0

Register to Memory

3 [000w] [mod reg r/m]

b,f

f,h

h

XOR Boolean Exclusive OR

Memory to Register

3 [001w] [mod reg r/m]

Immediate to Register/Memory

8 [00sw] [mod 110 r/m] #

Immediate to Accumulator (short form)

3 [010w] #

Instruction Notes for Instruction Set Summary

Notes a through c apply to Real Address
Mode only:
a. This is a Protected Mode instruction. Attempted execution in Real Mode will result in exception 6 (invalid op-code).
b. Exception 13 fault (general protection)
will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum CS, DS, ES,
FS, or GS segment limit (FFFFH). Exception 12 fault (stack segment limit violation
or not present) will occur in Real Mode if
an operand reference is made that partially or fully extends beyond the maximum
SS limit.
c. This instruction may be executed in Real
Mode. In Real Mode, its purpose is primarily to initialize the CPU for Protected
Mode.
Note: E through g apply to Real Address Mode
and Protected Virtual Address Mode:
d. An exception may occur, depending on
the value of the operand.
e. LOCK# is automatically asserted, regardless of the presence or absence of
the LOCK prefix.

ZFx86 Data Book 1.0 Rev D

1

1

3

3

3

3

1/3

1/3

1

1

b

h

f. LOCK# is asserted during descriptor table accesses.
Note: H through r apply to Protected Virtual
Address Mode only:
g. Exception 13 fault will occur if the memory operand in CS, DS, ES, FS, or GS
cannot be used due to either a segment
limit violation or an access rights violation. If a stack limit is violated, an exception 12 occurs.
h. For segment load operations, the CPL,
RPL, and DPL must agree with the privilege rules to avoid an exception 13 fault.
The segment’s descriptor must indicate
“present” or exception 11 (CS, DS, ES,
FS, GS not present). If the SS register is
loaded and a stack segment not present
is detected, an exception 12 occurs.
i. All segment descriptor accesses in the
GDT or LDT made by this instruction will
automatically assert LOCK# to maintain
descriptor integrity in multiprocessor systems.
j. JMP, CALL, INT, RET, and IRET instructions referring to another code segment
will cause an exception 13, if an applicable privilege rule is violated.

Page 106

2
k. An exception 13 fault occurs if CPL is
greater than 0 (0 is the most privileged
level).

non-cacheable. An invalid opcode exception 6 occurs unless SMI is enabled
and SMAR size > 0, and CPL = 0 and
[SMAC is set or if in an SMI handler].

l. An exception 13 fault occurs if CPL is
greater than IOPL.
m. The IF[9] bit of the EFLAG register is not
updated if CPL is greater than IOPL. The
IOPL and VM fields of the flag register
are updated only if CPL = 0.
n. The PE bit of the MSW (CR0) cannot be
reset by this instruction. Use MOV into
CRO if desiring to reset the PE bit.
o. Any violation of privilege rules as apply to
the selector operand does not cause a
Protection exception, rather, the zero
flag is cleared.
p. If the coprocessor’s memory operand violates a segment limit or segment access rights, an exception 13 fault will
occur before the ESC instruction is executed. An exception 12 fault will occur if
the stack limit is violated by the operand’s starting address.
q. The destination of a JMP, CALL, INT,
RET, or IRET must be in the defined limit
of a code segment or an exception 13
fault will occur.
Note: S applies to processor specific SMM
instructions:
r. All memory accesses to SMM space are

s. As requested by Microsoft® Corporation.

2.3.2.4. FPU Clock Counts
The CPU can be divided into the FPU which
processes floating point instructions and the
remaining circuity collectively called the
integer unit. The FPU can execute instructions
independently of the integer unit. For
example, the integer unit can issue a floating
point instruction without memory operands, in
two clock cycles and then pass the operation
to the FPU to execute. The integer unit will
continue to execute instructions until the next
floating point instruction is encountered. The
FPU loads from memory are similar in that the
integer unit issues the FPU instruction, transfers data to the FPU and then is free to
execute integer instructions. However, when
executing a floating point store, the resources
of both the FPU and integer unit are used.

2.3.2.5. Instruction Set Summary
Table 2.58 summarizes the operation and
allowed forms of the FPU instruction set.

2.3.2.6. Abbreviations
The abbreviations used in Table 2.57 are
listed in the table below:

Table 2.57 FPU Table Abbreviations
Abbreviation
n

Meaning
Stack register number

TOS

Top of stack register pointed to by SSS in the status register.

ST(1)

FPU register next to TOS

ST(n)

A specific FPU register, relative to TOS

M.WI

16-bit integer operand from memory

M.SI

32-bit integer operand from memory

M.LI

64-bit integer operand from memory

M.SR

32-bit real operand from memory

M.DR

64-bit real operand from memory

ZFx86 Data Book 1.0 Rev D

Page 107

2
Table 2.57 FPU Table Abbreviations
M.XR
M.BCD
CC
Env Regs

80-bit real operand from memory
18-digit BCD integer operand from memory
FPU condition code
Status, Mode Control and Tag Registers, Instruction Pointer and Operand Pointer

Table 2.58 MMX Instruction Set Summary
Clock
Count

Notes

TOS <— 2TOS-1

98 - 114

Note 2

E1

TOS <— | TOS |

5

DC

[1100 0 n]

ST(n) <— ST(n) + TOS

80-bit Register

D8

[1100 0 n]

TOS <— TOS + ST(n)

10 - 16

64-bit Real

DC

[mod 000 r/m]

TOS <— TOS + M.DR

13 - 19

MMX Instructions

Opcode

Operation

F2XM1 Function Evaluation 2x-1

D9

F0

FABS Floating Absolute Value

D9

Top of Stack

FADD Floating Point Add
10 - 16

32-bit Real

D8

[mod 000 r/m]

TOS <— TOS + M.SR

11 - 17

FADDP Floating Point Add, Pop

DE

[1100 0 n]

ST(n) <— ST(n) + TOS; then pop TOS

10 - 16

32-bit integer

DA

[mod 000 r/m]

TOS <— TOS + M.SI

18 - 27

16-bit integer

DE

[mod 000 r/m]

TOS <— TOS + M.WI

18 - 26

FCHS Floating Change Sign

D9

E0

TOS <— TOS

FCLEX Clear Exceptions

(9B) DB E2

Wait then Clear Exceptions

8

FNCLEX Clear Exceptions

DB

E2

Clear Exceptions

5

80-bit Register

D8

[1101 0 n

CC set by TOS - ST(n)

8

64-bit Real

DC

[mod 010 r/m]

CC set by TOS - M.DR

12

32-bit Real

D8

[mod 010 r/m]

CC set by TOS - M.SR

10

80-bit Register

D8

[1101 1 n

CC set by TOS - ST(n); then pop TOS

8

64-bit Real

DC

[mod 011 r/m]

CC set by TOS - ST(n); then pop TOS

12

32-bit Real

D8

[mod 011 r/m]

CC set by TOS - ST(n); then pop TOS

10

CC set by TOS-ST(1) then pop TOS and ST(1)

8

FIADD Floating Point Integer Add

5

FCOM Floating Point Compare

FCOMP Floating Point Compare, Pop

FCOMPP Floating Point Compare , Pop Two Stack Elements
DE

D9

FICOM Floating Point Compare
32-bit integer

DA

[mod 011 r/m]

CC set by TOS - M.WI

15 - 17

16-bit integer

DE

[mod 011 r/m]

CC set by TOS - M.SI

15 - 16

FICOMP Floating Point Compare
32-bit integer

DA

[mod 011 r/m]

CC set by TOS - M.WI; then pop TOS

15 - 17

16-bit integer

DE

[mod 011 r/m]

CC set by TOS - M.SI; then pop TOS

15 - 16

FCOS Function Evaluation: Cos(x)

D9

FF

TOS <— COS(TOS)

98 - 143

FDECSTP Decrement Stack Pointer

D9

F6

Decrement top of stack pointer

ZFx86 Data Book 1.0 Rev D

Note 1

5

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2
Table 2.58 MMX Instruction Set Summary (cont.)
MMX Instructions

Clock
Count

Opcode

Operation

Top of Stack

DC

[1111 1 n]

ST(n) <— ST(n) / TOS

28 - 34

80-bit Register

D8

[1111 0 n]

TOS <— TOS / ST(n)

28 - 34

64-bit Real

DC

[mod 110 r/m]

TOS <— TOS / M.DR

35 - 41

32-bit Real

D8

[mod 110 r/m]

TOS <— TOS / M.SR

33 - 39

FDIVP Floating Point Divide, Pop

DE

[1111 1 n]

ST(n) <— ST(n) / TOS; then pop TOS

28 - 34

Top of Stack

DC

[1111 0 n]

TOS <— ST(n) / TOS

28 - 34

80-bit Register

D8

[1111 1 n

ST(n) <— TOS / ST(n)

28 - 34

64-bit Real

DC

[mod 111 r/m]

TOS <— M.DR / TOS

35 - 41

32-bit Real

D8

[mod 111 r/m]

TOS <— M.SR / TOS

33 - 39

Notes

FDIV Floating Point Divide

FDIVR Floating Point Divide Reversed

FIDIVRP Floating Point Integer Divide, Reversed, Pop
DE

[1111 0 n]

ST(n) <— TOS / ST(n); then pop TOS

28 - 34

32-bit Integer

DA

[mod 110 r/m]

TOS <— TOS / M.SI

36 - 44

16-bit Integer

DE

[mod 110 r/m]

OS

<— TOS / M.WI

36 - 43

FIDIV Floating Point Integer Divide

FIDIVR Floating Point Integer Divide Reversed
32-bit Integer

DA

[mod 111 r/m]

TOS <— M.SI / TOS

36 - 43

16-bit Integer

DE

[mod 111 r/m]

TOS <— M.WI / TOS

36 - 43

FFREE Free Floating Point Register

DD

[1100 0 n]

TAG(n) <—Empty

5

F7

Increment top of stack pointer

5

FINCSTP Increment Stack Pointer

D9

FINIT Initialize FPU

(9B)DB E3

Wait then initialize

8

FNINIT Initialize FPU

DB

E3

Initialize

5

D9

[1100 0 n]

Push ST(n) onto stack

4
9

FLD Load Data to FPU Register
Top of Stack
80-bit Register

DB

[mod 101 r/m]

Push M.XR onto stack

64-bit Real

DD

[mod 000 r/m

Push M.DR onto stack

7

32-bit Real

D9

[mod 000 r/m]

Push M.SR onto stack

5

DF

[mod 100 r/m]

Push MBCD onto stack

49 - 53

64-bit Integer

DF

[mod 101 r/m]

Push M.LI onto stack

9 - 13

32-bit Integer

DB

[mod 000 r/m]

Push M.SI onto stack

8 - 10

16-bit Integer

DF

[mod 000 r/m]

Push 1.0 onto stack

8-9

FLD1 Load Floating Const. = 1.0

D9

E8

Push 1.0 onto stack

6

FBLD Load Packed BCD Data to FPU Register
FILD Load Integer Data to FPU Register

FLDCW Load FPU Mode Control Register
D9

[mod 101 r/m]

CTL Word <— Memory

6

FLDENV Load FPU Environment

D9

[mod 100 r/m]

Env Regs <— Memory

28 - 38

FLDL2E Load Floating Const. = Log2(e)

D9

EA

Push Log2(e) onto stack

6

FLDL2T Load Floating Const. = Log2(10) D9

E9

Push Log2(10) onto stack

6

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2
Table 2.58 MMX Instruction Set Summary (cont.)
MMX Instructions

Opcode

Operation

Clock
Count

FLDLG2 Load Floating Const. = Log10(2) D9

EC

Push Log10(2) onto stack

6

FLDLN2 Load Floating Const. = Ln(2)

D9

ED

Push Loge(2) onto stack

6

FLDPI Load Floating Const. = p

D9

EB

Push π onto stack

6

FLDZ Load Floating Const. = 0.0

D9

EE

Push 0.0 onto stack

6

Top of Stack

DC

[1100 1 n]

ST(n) <— ST(n) x TOS

12

80-bit Register

D8

[1100 1 n]

TOS <— TOS x ST(n)

12

64-bit Real

DC

[mod 001 r/m]

TOS <— TOS x M.DR

15

32-bit Real

D8

[mod 001 r/m]

TOS <— TOS x M.SR

13

FMULP Floating Point Multiply & Pop

DE

[1100 1 n

ST(n) <— ST(n) x TOS, then pop TOS

12

Notes

FMUL Floating Point Multiply

FIMUL Floating Point Integer Multiply
32-bit Integer

DA

[mod 001 r/m]

TOS <— TOS x M.SI

21 - 54

16-bit Integer

DE

[mod 001 r/m]

TOS <— TOS x M.WI

21 - 24

FNOP No Operation

D9

D0

No Operation

FPATAN Function Eval: Tan-1(y/x)

D9

F3

ST(1) <— ATAN[ST(1) / TOS]; then pop TOS

97 - 161

FPREM Floating Point Remainder

3

D9

F8

TOS <— Rem[TOS / ST(1)]

82 - 93

FPREM1 Floating Point Remainder IEEE D9

F5

TOS <— Rem[TOS / ST(1)]

82 - 93

FPTAN Function Eval: Tan(x)

D9

F2

TOS <— TAN(TOS); then push 1.0 onto stack 123 - 140

FRNDINT Round to Integer

D9

FC

TOS <— Round(TOS)

[mod 100 r/m]

Restore state

Note 3

Note 1

12 - 21

FRSTOR Load FPU Environment and Register
DD
FSAVE Save FPU Environment and Reg

(9B)DD[mod 110 r/m] Wait then save state

110 - 120
143 -153

FNSAVE Save FPU Environment and Register
DD

[mod 110 r/m]

Save state

FSCALE Floating Multiply by 2n

D9

FD

TOS <— TOS x 2(ST(1))

10 - 15

FSIN Function Evaluation: Sin(x)

D9

FE

TOS <— SIN(TOS)

81 - 159

FSINCOS Function Eval.: Sin(x)& Cos(x) D9

FB

temp <— TOS;
TOS <— SIN(temp); then
push COS (temp) onto stack

150 - 165

FSQRT Floating Point Square Root

FA

TOS <— Square Root of TOS

D9

140 - 150

Note 1

61 - 62

FST Store FPU Register
80-bit Register

DD

[1101 0 n]

ST(n) <— TOS

5

80-bit Real

DB

[mod 111 r/m]

M.XR <— TOS

15

64-bit Real

DD

[mod 010 r/m]

M.DR <— TOS

12

32-bit Real

D9

[mod 010 r/m]

M.SR <— TOS

9

Top of Stack

DB

[1101 1 n]

ST(n) <— TOS; then pop TOS

5

80-bit Real

DB

[mod 111 r/m]

M.XR <— TOS; then pop TOS

15

FSTP —tore FPU Register, Pop

64-bit Real

DD

[mod 011 r/m]

M.DR <— TOS; then pop TOS

12

32-bit Real

D9

[mod 011 r/m]

M.SR <— TOS; then pop TOS

9

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2
Table 2.58 MMX Instruction Set Summary (cont.)
MMX Instructions

Clock
Count

Opcode

Operation

DF

[mod 110 r/m]

M.BCD<—TOS; then pop TOS

32-bit Integer

DB

[mod 010 r/m]

M.SI <— TOS

16 - 22

16-bit Integer

DF

[mod 010 r/m]

M.WI <— TOS

12 - 18

64-bit Integer

DF

[mod 111 r/m]

M.LI <— TOS; then pop TOS

19 - 27

32-bit Integer

DB

[mod 011 r/m]

M.SI <— TOS; then pop TOS

16 - 22

16-bit Integer

DF

[mod 011 r/m]

M.WI <— TOS; then pop TOS

12 - 18

FBSTP Store BCD Data, Pop

Notes

77 - 82

FIST Store Integer FPU Register

FISTP Store Integer FPU Register, Pop

FSTCW Store FPU Mode Control Register
9B)D9[mod 111 r/m]

Wait Memory <—

Control Mode Register

6

FNSTCW Store FPU Mode Control Register
D9
FSTENV Store FPU Environment

[mod 111 r/m]

(9B)D9[mod 110 r/m
[mod 110 r/m]

Memory

<—

Wait Memory <—
<—

3
30 - 40

Env. Registers

27 - 37

FNSTENV Store FPU Environment

D9

FSTSW Store FPU Status Register

(9B)DD[mod 111 r/m]

Wait Memory <—

Status Register

6

FNSTSW Store FPU Status Register

DD

Memory

<—

Status Register

3

FSTSW AX Store FPU Status Reg. to AX (9B)DF E0

Wait AX

<—

Status Register

6

FNSTSW AX Store FPU Status Reg to AX DF

E0

AX

<—

Status Register

3

[mod 111 r/m]

Memory

Control Mode Register
Env. Register

FSUB Floating Point Subtract
Top of Stack

DC

[1110 1 n]

ST(n) <— ST(n) - TOS

10 - 16

80-bit Register

D8

[1110 0 n]

TOS <— TOS - ST(n)

10 - 16

64-bit Real

DC

[mod 100 r/m]

TOS <— TOS - M.DR

13 - 19

2-bit Real

D8

[mod 100 r/m

TOS <— TOS - M.SR

11 - 17

FSUBP Floating Point Subtract, Pop

DE

[1110 1 n]

ST(n) <— ST(n) - TOS; then pop TOS

10 - 16

Top of Stack

DC

[1110 0 n]

TOS <— ST(n) - TOS

10 - 16

80-bit Register

D8

[1110 1 n

ST(n) <— TOS - ST(n)

10 - 16

64-bit Real

DC

[mod 101 r/m]

TOS <— TOS - M.DR - TOS

13 - 19

32-bit Real

D8

[mod 101 r/m]

TOS <— TOS - M.SR - TOS

11 - 17

FSUBRP Floating Point Subtract
Reverse, Pop

DE

[1110 0 n]

TOS <— TOS - ST(n); then pop TOS

10 - 16

32-bit Integer

DA

[mod 100 r/m]

TOS <— TOS - M.SI

18 - 27

16-bit Integer

DE

[mod 100 r/m]

TOS <— TOS - M.WI

18 - 26

FSUBR Floating Point Subtract Reverse

FISUB Floating Point Integer Subtract

FISUBR Floating Point Integer Subtract Reverse
32-bit Integer Reversed

DA

[mod 101 r/m]

TOS <— M.SI - TOS

18 - 27

16-bit Integer Reversed

DE

[mod 101 r/m]

TOS <— M.WI - TOS

18 - 26

FTST Test Top of Stack

D9

E4

CC set by TOS - 0.0

10

FUCOM Unordered Compare

DD

[1110 0 n]

CC set by TOS - ST(n)

8

FUCOMP Unordered Compare, Pop

DD

[1110 1 n]

CC set by TOS - ST(n); then pop TOS

8

CC set by TOS - ST(1); then pop TOS & ST(1)

8

FUCOMPP Unordered Compare, Pop two elements
DA

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Table 2.58 MMX Instruction Set Summary (cont.)
MMX Instructions

Clock
Count

Opcode

Operation

FWAIT Wait

9B

Wait for FPU not busy

3

FXAM Report Class of Operand

D9

E5

CC

4

FXCH Exchange Register with TOS

D9

[1100 1 n]

TOS <—>ST(n) Exchange

FXTRACT Extract Exponent

D9

F4

temp <— TOS
TOS <— exponent (temp); then
push significant (temp) onto stack

FLY2X Function Eval. y × Log2(x)

D9

F1

ST(1) <— ST(1) x Log2(TOS); then pop TOS

FLY2XP1 Function Eval. y × Log2(x+1)

D9

F9

ST(1) <— ST(1) x Log2(1+TOS);then pop TOS 131 - 133

<— Class of TOS

Notes

9

145 - 154
Note 4

FPU Instruction Summary Notes

All references to TOS and ST(n) refer to stack
layout prior to execution.
Notes:
1. Values popped off the stack are discarded.
2. A pop from the stack increments the top of
stack pointer.
3. A push to the stack decrements the top of
stack pointer.
4. For FCOS, FSIN, FSINCOS and FPTAN,
time shown is for absolute value of TOS
< 3p/4.
Add 90 clock counts for argument reduction
if outside this range.
- For FCOS, clock count is 143 if TOS
< p/4 and clock count is 98 if p/4 <
TOS > p/2.
- For FSIN, clock count is 81 to 82 if absolute value of TOS < p/4.
5. For F2XM1, clock count is 98 if absolute value of TOS < 0.5.
6. For FPATAN, clock count is 97 if ST(1)/TOS
< p/32.
7. For FYL2XP1, clock count is 170 if TOS is
out of range and regular FYL2X is called.

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3. North Bridge
The North Bridge (illustrated in Figure 3-1
Data Paths) is a high performance 32 bit controller. Through the use of synchronous
DRAM, high processor to/from system memory bandwidth is supported. This minimizes
the need for second level cache. PCI read and
write buffers allow system memory accesses
to be handled in bursts and hence maximizes
system availability to the processor. Lastly, a
CPU to PCI write buffer allows the processor
to post writes to the PCI and then continue to
other tasks.

• CPU bus to PCI bus bridge with PCI
arbiter. Support for three external masters
and one internal master. Any on chip or off
chip master must connect via this interface.
• External PCI bus mastership. External bus
mastership of System Controller internal
bus. Mastership allows access to system
controller memory devices.
• SDRAM Write Buffer – 32 Bytes
• CPU to PCI Write Buffer – 32 Bytes
• PCI Write Buffer – 16 Bytes

3.1. North Bridge Features

• PCI Read Pre-fetch Buffer – Dual 16 Bytes

The North Bridge controller is based on a
PC87550 PCI System Controller (North
Bridge) designed for a Pentium class processor. Following are the features of the North
Bridge Controller.

• Support for Power Management signals
from the South Bridge

• CPU single cycle and burst bus transactions support
• Cache coherency support

Figure 3-1 "Data Paths" on page 114 & ‘Block
Diagram’ on page 115 provide a detailed look
at the control paths of the North Bridge and
how the data flows through it.

Table 3.0 table base

• CPU level one write back and write
through cache support.
• Support for SMM bus cycles
• Support for Level 1 cache flush via CPU
FLUSH# pin
• Programmable cache, non-cache and
Read-only regions support
• 32 bit data bus structure though out
• Memory Controller to support Synchronous DRAM (SDRAM). Memory can be
configured as 16 or 32 bits wide.
• Support for up to four banks of SDRAM
and 256 Mbytes of memory space

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3
Processor
Internal
Configuration
Registers

Read
DataPath

A
R
B
I
T
E
R

CPU-PCI
Write
Buffer
16 DW

DRAM
Write
Buffer
8 DWORDS

S
D
R
A
M

MemoryPCI
Pre-Fetch
Buffer
Dual
4DW

PCIMemory
Write
Buffer
4 DW

Memory Controller

PCI Controller

PCI BUS
Figure 3-1 Data Paths

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3
C
A

IOCYCLE
Controller

AC
Configuration
Registers

A

A
C

NC_ADDR

L2
Controller
(see Note)

Write Buffer
and Control

ADR

SDRAM
Controller
BRDYPATH
CNTRL
PCI BM
Buffer and
Control

CPU Backoff

A

CKE

Refresh
Control

SNOOPCPU

32 KHz

Int Clocks

PCI
ARBITER

R

HOST2PCI
Control

PCI BM
Control

G

Clock
Control

SUSPA

CLK66

Figure 3-2 Block Diagram

Note: The L2 Controller is not operational in the ZFx86 chip.

ZFx86 Data Book 1.0 Rev D

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3
3.2. Interface Signals
This section provides the description of signals between the North Bridge Core and other
cores or pads. The signal descriptions are
divided into various tables according to the
functionality and interface they relate to for
easy reference.
Table 3.1 SDRAM Interface Signals
Pin No.
(PU/PD)

Signal

Type

Description

O

Chip Select - drives CSn inputs of four pairs of SDRAM banks 7/6,
5/4, 3/2 and 1/0. Disables or enables device operation by masking
or enabling all inputs except CLK, CKE (clock enable) and DQM.

SDRAM_CSn_N[3:0]

0 = B25
1 = A25
2 = A24
3 = B24

SDRAM_DQM[3:0]

0 = C23
1 = B23
2 = D22
3 = A23

O

Data Input/Output Mask - Drives four DQM inputs of SDRAM bank
pair. They correspond to inverse of BEn[3:0] in 32 bits mode, in 16
bits mode DQM[1:0] is used to multiplex the four byte enables.
When DQM is high during a write no data is written and during a
read data pins are tri-stated.

SDRAM_WE_N

C22

O

Data Write Enable - This output drives write enables to all SDRAMs.
Enables write operation and row pre-charge. Latches data in
starting from CAS, WE active. (dram_Wenn)

MA[11:0]

0 = A15
1 = C14
2 = B15
3 = C15
4 = B16
5 = A16
6 = C16
7 = B17
8 = C17
9 = A18
10 = C18
11 = B18

O

Memory Address - Twelve bits of address for SDRAM. Row/column
addresses are multiplexed on the same pin. And it correspond to
Row address : RA11 ~ RA0, Column address : CA9 ~ CA0

MA[13:12]

12 = A19
13 = D18

O

Memory Address - SDRAM chips are organized internally in banks,
and there may be 4 banks{x4, x8 and x16 SDRAMs) or 2 banks
(x32 SDRAM). These banks should not confuse with system level
banks of SDRAMs.

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Table 3.1 SDRAM Interface Signals (cont.)
Pin No.
(PU/PD)

Signal

Type

Description

D[31:0]

0 = C24
1 = A26
2 = B26
3 = C25
4 = D24
5 = C26
6 = E23
7 = D25
8 = E24
9 = D26
10 = E25
11 = E26
12 = F24
13 = F25
14 = G23
15 = F26
16 = G25
17 = G24
18 = G26
19 = H24
20 = H25
21 = H26
22 = J24
23 = J23
24 = J25
25 = J26
26 = K25
27 = K24
28 = K26
29 = L23
30 = L24
31 = L25

I/O

Memory Data Bus -

SDRAM_RAS_N

C20

O

Row Address Strobe - connects RASn input of SDRAM chips.

SDRAM_CAS_N

D20

O

Column Address Strobe - connects to CASn input of all SDRAM
chips.

SDRAMCLK[0:3]

0 = B22
1 = A22
2 = B21
3 = A21

O

SDRAM Clock - The frequency will be x1 of the System Clock
(CLKIN). The SDRAM captures inputs at the positive edge of the
clock.

O

SDRAM Clock Enable - Masks clock to freeze operation from the
next clock cycle. SDRAM_CKE should be enabled at least one
cycle prior to new command.
Disables input buffers for power down mode.

SDRAM_CKE

C21

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Table 3.2 PCI Sideband Signals
Signal

Type

Description

SB_REQnn

I

South Bridge PCI Request - This is a request signal from the South bridge for PCI bus
into the arbiter.

SB_GNTnn

O

South Bridge PCI Grant - This is bus grant signal from the arbiter in response to
SBREQn.

SB_PCICLK

O

South Bridge PCI Clock - This is a clock signal output to the South Bridge.

IRQ13 Internal Only

O

Floating Point Interrupt - Causes SB to send INT to the CPU.

WRM_RESET

I

Warm Reset - This is an input to the core. This pin allows an external source to initiate a
warm reset to the CPU, by setting this pin HIGH. If not used it should be tied LOW.

Table 3.3 Test Signals (JTAG)
Signal

Type

Description

TESTMODE

I

Enable Test Mode.

SCAN_MODE

I

Scan Mode

SCAN_EN

I

Scan Enable

TEST_SI1–TEST_SI4

I

Scan In ports - for four scan chains

TEST_SO1–TEST_SO4

O

Scan Out ports - for four scan chains

CPU_SYNC[3:0]

O

CPU SYNC bus - For syncing Processor test with PCI Masters in simulation and
with PCI Bus Testers in hardware. Only CPU_SYNC[0] actually goes out off chip.

3.3. Functional Description
3.3.1. Processor Interface
Processor Interface will support memory, I/O
and special bus cycles from the processor to
the onboard resource, system memory and
PCI bus. It will also handle snoop cycles to the
processor on behalf of the PCI bus master.

configuration address register is always local,
while access to configuration data register is
special as it could be within the core or external depending on the contents of the configuration address register. This is explained in
more detail in the PCI Configuration section.

3.3.1.1. Address Map
Following Memory and I/O address map specifies how address decoding is done to determine if local (within the core) or external
resource is being accessed. Access to the PCI

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Table 3.4 Memory Access Map
Local/
PCI

Access
Size

Locala

All

0FFF FFFF (256 MB max)

PCI Memory Space

PCI

All

Top-of-Memory => 0FFF FFFF

PCI Memory Space

PCIb

All

1000 0000 FDFF FFFF

SMM Space

Local

All

1DFD 0000 — 1DFE FFFF

PCI

All

FE00 0000 — FFFF FFFF (32 MB)

Memory
Maximum local DRAM

Upper ROM
(Presently this also goes to PCI)

Address Range

a.Some holes may exist in the range of 000A 0000 – 000F FFFF for the Video Memory and ROMs may not be shadowed

b.A hole of 128 KB may be used by SMM, which would be local, if programmed in SMMC

Table 3.5 I/O Address Map
Register

Local/
PCI

Access Size

Address

NB Configuration Index Register

Local

16 bits

24H

NB Configuration Data Register

Local

16 bits

26H

PCI Configuration Cycle Address Register

Local

32 bits

CF8H

All

CFCH

PCI Configuration Cycle Data Register
(If Configuration Enable =1 in PCI Configuration Address
Register)

Local or PCI

3.3.1.2. Special Regions
To allow system flexibility, 4 regions have been
defined that can be individually programmed
to be non-cacheable. The region sizes should
be allowed to be 32KB, 64KB, 128KB, 256KB,
512KB, or 1MB. The starting address and size
are programmed in the registers PR3-PR1,
and the mode is programmed in the register
PRC.

ZFx86 Data Book 1.0 Rev D

Refer to ‘Register Set’ on page 136 for programming information. In a typical system
configuration, these regions are not required
since standard non-cacheable regions — nonshadowed ROM regions between
000C0000H-000FFFFFH — are automatically
marked as non-cacheable.

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3
3.3.1.3. Invalidate ROM Shadowed
Region in L1

.

Table 3.6 North Bridge Core Burst
Sequence

If ROM region is cached in L1, then whenever
write to the ROM region is detected will cause
the NB to run an invalidate cycle back to the
processor.

3.3.1.4. ROM Regions
Since the CPU is not capable of handling
write-back/write-through modes on cache line
basis, all ROM regions shadowed in the memory should be marked as non-cacheable, if the
L1 cache is operating in write-back mode. If L1
is operating in write-through mode then ROM
may be cacheable, if L1WBEN is cleared in
the PROC register and SMM RAM is not overlaid to this ROM region.
The reading from this region of DRAM is controlled by SHADRC and SHADWC register
controls the writing. To load the DRAM with
ROM information, that region should be
marked write-able and disable the reading.
This will cause the reads to happen from the
ROM and write to the DRAM. After loading is
complete the bits may be reversed in
SHADRC and SHADWC for that region. Programming of SHADRC and SHADWC is
explained in more detail in 3.4. "Register Set"
on page 136.

3.3.1.5. Special cycles
The North Bridge will always swallow special
cycles, with the exception of shutdown and
halt cycles, which it will broadcast to the PCI
bus followed by a master-abort cycle.

3.3.1.6. Burst sequence
The North Bridge core will support only linear
burst sequence

Burst Cycle First
Address
A3A2

Linear assumed
burst cycle
address sequence
A3A2

00

00-01-10-11

01

01-10-11-00

10

10-11-00-01

11

11-00-01-10

3.3.1.7. Concurrent CPU and PCI busses
The North Bridge will support an external master and the CPU running concurrently. This
mandates that the PCI bus be (TRDY#) stalled
on external master cycles until we run the
cycle up to the CPU (if snooping is required).
This may result in a write-back cycle, and thus
the DRAM must be updated with the CPU
data. The CPU should only be snooped for
External Master accesses to a new 16 byte
line (A[31:4] change). The initiator of the
snoop request (Memory Controller) will manage this.

3.3.1.8. PCI Master Deadlock Issues
In the event of a PCI deadlock condition, i.e.
where the Target is continually retrying cycles,
we need to take the following steps.
• Condition our response with a large timeout counter.
• CPU interface snoop logic must be able to
generate BOFF# to the CPU to retry the
cycle. Special care must be taken when
there are cycles already been posted to
the write buffer.
• If the deadlock is on a PCI read, the CPU
can be backed off, the external master
granted the bus and the corresponding

ZFx86 Data Book 1.0 Rev D

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3
address snooped to the CPU. In the event
of a write-back cycle, the DRAM is
updated and the external master continues
with the cycle.
• In the event of a deadlock on a PCI write,
with the PCI write buffer full, we must block
the post to the write buffer, assert BOFF#
to the CPU, force the CPU Interface/L2
FASTEN’s to idle and let the CPU retry the
cycle. If the interrupted cycle was to
DRAM, interrupting the cycle in the middle
of a burst and rewriting part or all of the
data is non-destructive (b/c it is linear
memory). This means that in the clock that
BOFF# is asserted to the CPU, all writes to
the Write Buffer are blocked (in the Write
Buffer modules)
• While snooping, AHOLD to the processor
will be used, so that a write-back cycle can
occur, even if BOFF# was generated.

3.3.1.9. Conditions when a memory
address is not cacheable in L1
If any one of the conditions below is true, that
memory address must be made non-cacheable in L1.
• KENEN bit in the PROC register is a ‘0’.
• The address is not within the local DRAM
area.
• The address matches the value
programmed in any of the four programmable regions and the cacheability bit for
the programmable region indicates noncacheable.
• DIS23RMAP bit in SMMC register is a ‘0’
and access is to 20000-3FFFFh region.
• SMM memory is mapped to lower SMM
RAM region.
• When in SMM mode, and SMM memory is
mapped to lower region, D0000-EFFFFh.
Or KDISSMMRAM bit is set to a ’1’ in the

ZFx86 Data Book 1.0 Rev D

SMMC register. "SMM Control Register
(SMMC) - Configuration Index 118H" on
page 140

3.3.1.10. Conditions when a memory
address is marked as WT
Since the Processor does not support WB and
WT regions in the memory, entire cache can
be Write-back (WB) or Write-through (WT).
The corresponding bits in the Programmable
Region Control Register will be treated as
don’t cares.

3.3.1.11. Conditions when there is no
write-posting to PCI buffer
All IO cycles will cause the write buffers to
flush and finish any outstanding cycles. If any
external masters currently occupy the PCI bus
the CPU must be stalled until it regains arbitration priority for the PCI bus.
LOCK and Pseudo-LOCK
CPU drives the LOCK# signal when it is executing read-modify-write type of instruction.
The LOCK# is driven with the ADS# of the first
read bus cycle and stays on till the RDY# for
the last write cycle. During the lock cycle the
access to SDRAM from PCI is blocked till the
LOCK# is de-asserted.
Pseudo Lock indicated by PSLOCK# signal is
asserted by the CPU when doing multi dword
read. NB uses this signal only during 64-bit
write cycle to lock the bus to the SDRAM, just
like LOCK#, till the second write is complete.
The use of PSLOCK# is controlled by a bit,
DIS_PSLOCK, in the PROC register. When
this bit is set, PSLOCK# signal will be ignored.

3.3.1.12. Address Translation
When the processor does a memory access
(MIO# = high) the address goes through a
translation logic before it is fed to the decoders
to determine if the address belongs to local
memory or it is off-chip

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3
CPU

IOC Controller

L2C Controller

NC Addr

A3, A2

Snoop CPU

NC Address
Memory Interface

Cpuaddr[31:2]

DRAM Decode Bank
Useraddr[31:2]
DRAM Decode SMM
usedram

non cache

Write Buffer

firstmeg

DRAM Decode
Single Bank

Shadow Decode

DCONFx
BxC

Regionx Hit

CPU Final Decode

CPU
Local DRAM

Bank Info Decode

CPU Bank Type,
CPU Row Address
CPU Column Address
etc.

Memory
KENnn

Figure 3-3 CPU Address Translation and Decode
.

3.3.2. DRAM Controller
3.3.2.1. DRAM architecture
NB DRAM controller will only support 16 Mb,
64 Mb and 128Mb Synchronous DRAM. It will
have control for up to four banks of 32-bit
memory or 16-bit memory. Each bank can be
made up of a single or multiple SDRAM

ZFx86 Data Book 1.0 Rev D

chip(s). Each 32-bit bank can have capacity
from 8 MB to 64 MB of memory, with four
banks giving a total of 256 MB for the NB. With
16-bit banks lower memory size (2MB) can be
achieved for a low entry cost system design.
DRAM controller will support Single Data
Strobe (SDR) SDRAM of the following configurations:

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3
Table 3.7 SDRAM Configurations
SDRAM
Type

SDRAM
Configuration

SDRAM
Int. Bank
Size

SDRAM
Row
Size

SDRAM
Column
Size

Number of SDRAM
per Memory Bank

Max Memory Bank
Size (Mbytes)

32Bit

16Bit

32Bit

16Bit

2M x 4 x 2

1

11

10

8

4

16

8

1M x 8 x 2

1

11

9

4

2

8

4

512K x 16 x 2

1

11

8

2

1

4

2

4M x 4 x 4

2

12

10

8

4

64

32

2M x 8 x 4

2

12

9

4

2

32

16

1M x 16 x 4

2

12

8

2

1

16

8

512K x 32 x 4

2

11

8

1

1

8

4*

2M x 16 x 4

2

12

9

2

1

32

16

16Mbit

64Mbit

128Mbit

3.3.2.2. DRAM memory map
Address mapping is done to reduce the
encoding logic and cover wide range of memory devices. Row address is presented with a
RAS and column address is presented with a
CAS, bank address need to be stable and
same, during both RAS and CAS times. “P” bit
during CAS indicates to the SDRAM to enable
or disable Auto Pre-Charge. The memory
address MA[11:0] connect to MA[11:0], and
MA[13:12] connect to the internal-bank
address SDRAMs. The exact mapping of
address connection between NB and the
SDRAMs will depend on the technology and
the configuration of the SDRAM.

ZFx86 Data Book 1.0 Rev D

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3

BA<>
MA<>

North
Bridge

D<31:0>
RAS#, CAS#, WE#
CS#

CS#

CS# CS#

Figure 3-4 32-Bit Banks Connection

North
Bridge

BA<>

32 Bit
DIMM

MA<>
D<15:0>
RAS#, CAS#, WE#

CS#
CS#

CS#<1:0>

Figure 3-5 16-Bit Bank Connections

ZFx86 Data Book 1.0 Rev D

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3
3.3.2.3. DRAM Bank location flexibility

3.3.2.8. Pre-charge Time

All DRAMs, regardless of sizes, must be able
to be placed in any Bank and at any starting
address locations (in 2 Meg resolution for 16
bit banks). If there are gaps in the mapping,
the gaps will go to PCI. There is no checking
for the overlapped mapping, and this is done
in the BIOS firmware.

Pre-charge command is used instead of Auto
Pre-charge to pre-charge the rows of the
DRAM. It is initiated at the start of the Mode
Register setting, auto-refresh, self-refresh,
RAS time-out, page-miss and on power-on.

3.3.2.4. Mixing SDRAM banks

Instead of latching the address into the write
FIFO in the NB chip and then decoding the
necessary signals when the actual write cycle
is about to occur, all necessary signals will be
decoded and then written into the FIFO. This
will allow faster DRAM signal generation.

Mixing of SDRAM banks of different size,
speed and/or manufacturers will be allowed
through SDRAM bank control and timing control registers for each bank. The 16-bit banks
only exist on the lower 16 bits of the MD<>
bus. Also a bank can be of 16-bit and another
bank of 32-bit in a system will be supported.

3.3.2.5. DRAM refresh
16 Mb, 64 Mb and 128Mb SDRAM need
refresh every 64 ms/row regardless of the
width. Using Auto Refresh command every
15.625 usec satisfies this requirement.
SDRAM refresh period is generated from
32KHz clock, using both edges of the clock to
generate refresh request pulse. Though 50%
duty cycle clock is not required, the ratio
should be reasonable to allow the system
clock to synchronize this 32KHz clock.

3.3.2.9. Decode all necessary signals
before writing to FIFO

3.3.2.10. ROM shadowing
When ROM is shadowed into DRAM, only
CPU is allowed access to shadowed RAM.
The DRAM controller should treat all non-CPU
access to ROM regions as non-local DRAM
access.
The ROM shadowing is applicable to regions
000C0000H-000FFFFFH. Reg. 200 and 201
specify READ/WRITE ability of the shadowed
ROM. Illustrated below is a table specifying
the 16KB block from D4000H-D7FFFH (1MB160KB).

3.3.2.6. CPU write to 16 bit DRAM bank
If a 16 bit DRAM bank is in the system and the
processor is writing to either the upper word or
lower word only, there should be just one
DRAM write cycle. The DRAM should filter
writes based on the BE[3:0]# and ONLY run 2
cycles if both BE2# AND BE3# are active (i.e.
crossing a WORD boundary).

3.3.2.7. Treat bank miss as page miss
Because bank miss cycles are very infrequent,
bank misses will be treated as page misses.
This will save logic by allowing the use of one
block of logic (i.e. RAS precharge logic) for all
DRAM banks, instead of one for each DRAM
bank.

ZFx86 Data Book 1.0 Rev D

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3
Table 3.8 ROM Shadow Illustration
SHADRC

SHADWC

Description

0

0

Read from 000D4000H:000D7FFH comes from ROM
Write to 000D4000H:000D7FFH is ignored
Read from 4GB→4GB-32MB comes from ROM
Write to 4GB→4GB-32MB is sent to PCI bus

0

1

Read from 000D4000H:000D7FFH comes from ROM
Write to 000D4000H:000D7FFH is to Shadow RAM
Read from 4GB→4GB-32MB comes from ROM
Write to 4GB→4GB-32MB is sent to PCI bus

1

0

Read from 000D4000H:000D7FFH comes from Shadow RAM
Write to 000D4000H:000D7FFH is ignored
Read from 4GB→4GB-32MB comes from ROM
Write to 4GB→4GB-32MB is sent to PCI bus

1

1

Read from 000D4000H:000D7FFH comes from Shadow RAM
Write to 000D4000H:000D7FFH is to Shadow RAM
Read from FFFD4000H:FFFD7FFH comes from ROM
Write to FFFD4000H:FFFD7FFH is sent to PCI bus

3.3.3. Configuration and Testability
3.3.3.1. North Bridge Register Programming
IO address 24H will be used as an index register and IO address 26H will be used as a data

register. All 16 bit register accesses to these
addresses will be absorbed by North Bridge
(NB) and will not appear on the PCI bus. Any
byte accesses to IO 24/26 will be ignored by
NB and passed onto the PCI bus where the
South Bridge will pick up the request.

Table 3.9 North Bridge Registers
Index range

Function

0100H-01FFH

Reset sampling and Miscellaneous Registers

0200H-02FFH

SDRAM Registers

0300H-03FFH

Power Management Registers

0400H-04FFH

L2 Controller Registersa

a.The ZFx86 does not support an L2 Cache.

ZFx86 Data Book 1.0 Rev D

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3
3.3.3.2. PCI Registers
The PCI specification requires that all devices
connected to the PCI bus must implement a
minimum set of 64bytes of PCI configuration
space registers. In order to support this, two
double-word IO addresses, 0CF8H and
0CFCH are used as CONFIG_ADDRESS and
CONFIG_DATA registers, respectively. Only
double-word access to 0CF8H address will be
trapped for local access and it accesses
PCI_CONFIG_ADDRESS register, other size
accesses will go to PCI bus. To access local
PCI configuration registers, address has to be
loaded into PCI_CONFIG_ADDRESS bits 7:0
and with bits 23:11 equal to 0s, and bit31
equal to 1. If bits 23:11 is other than 0s or bit31
is not a 1, or access is not a double-word a
PCI cycle would be run.
See ‘PCI Hardware and Software Architecture
& Design, 4th Edition, Solari & Willse, Annabooks, IBSN 092939259-0.

3.3.4. PCI bus interface and arbiter
3.3.4.1. PCI arbiter
NB will support up to 3 external PCI masters, a
South Bridge request, and the CPU request.
The arbiter will allow a rotating priority scheme
between the PCI-ISA bridge, the CPU, and
one of the PCI REQ/GNT# pairs. It can be
configured to give the PCI REQ#/GNT# pairs
every other arbitration (see GRNT_BANK diagram below). The arbitration is set up on a 4-3
tier formation. The starting arbitration chooses
evenly (round robin), or prioritizes between a
“PCI Winner”, the South Bridge and the CPU.
The beginning arbitration chooses a “PCI Winner” amongst 3 requesters. These 4 requesters can be mapped to any of the REQ#/GNT#
pins.

will give priority access to certain masters (ex.
video or IDE) if they are continually requesting. Although the Requester A can get every
other PCI arbitration, it still needs to arbitrate
with an “ISA winner” and the CPU.
If the PCI Winner is allowed every other arbitration (see GNT_BANK Priority Diagram
below) and the CPU and ISA are all requesting, the Requester A will get 1/2 of all PCI
Arbitration but only get access (to DRAM) 1/4
of the arbitration. If the PCI Winner is programmed for Round Robin (fair arbitration) the
Requester A would have a maximum of 1/6 of
all arbitration to DRAM.
The PCI Arbiter should allow PCI Peer to Peer
access (we decode the address as non-local
DRAM) and allow the CPU to access the
DRAM while the Peer to Peer transaction is
taking place. In the event of a CPU request for
the PCI bus, it must again wait until it is arbitrated the bus, and then the cycle can complete. Note that for PCI peer to peer
transactions we do NOT need to snoop the
CPU because this memory is considered noncacheable.

Figure 3-6 shows the arbitration priority
scheme between requesters on the PCI bank.
in order to determine a “PCI Winner”. Note
Requester A (mapped from any REQ#/GNT#
pair) can win every other PCI arbitration. This

ZFx86 Data Book 1.0 Rev D

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3
ARBITER CONFIGURATION DIAGRAM
From
CFG_REG
CPUREQ#

From
CFG_REG

GNT_a

GNT0#

GNT_b

GNT1#

GNT_c

GNT2#

REQ1#

REQ_b

GNT_d

GNT3#

REQ2#

REQ_c

REQ3#

REQ_d

REQ4#

PCI
BANK

GNT_e

PCI_WINNER

ARBITER
CORE

REQ_e

V3_GNT#

SB_REQ#

ISA
BANK

ARBITER

REQ_a

ARBITER

REQ0#

GNT4#

SB_GNT#

ISA_WINNER
CPUGNT#

SB_REQ#: Can be routed via SB_REQ pin or one of the PCI REQ# pins.
PCI_BANK: Only 5 requests as 6th is routed to V4. Priority scheme as explained.
ISA_BANK: Always ROTATING priority between masters. If SIO_HIPRI bit (Reg111EH[6]) is set, then V4 is
always higher priority.
ARBITER CORE: Priority scheme as explained.

Figure 3-6 PCI Bus Arbiter Block Diagram

ZFx86 Data Book 1.0 Rev D

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3
PCI_BANK PRIORITY SCHEME

Reset

REQ_a

REQ_a
(Slot 0)
Reg11EH(0)

REQ_b

REQ_c

REQ_a
(Slot 1)
Reg11EH(1)
Programmable
Slots

REQ_b
(Slot 2)
Reg11EH(2)

REQ_a
(Slot 3)
Reg11EH(3)

REQ_d

REQ_e
Transition to next state occurs when the master completes one cycle
(locked / unlocked) or PMIT expires

Figure 3-7 PCI Bank Arbiter State Diagram

3.3.5. PCI Write Buffer and Bursts
In order to meet the 100Mb/s PCI transfer rate
requirements, the PCI needs to sustain a continual burst of data to linearly increasing
addresses. Thus the PCI block must look
ahead 3 entries (from the current address and
data) in order to determine if it can sustain the
burst cycle. The 3 entry requirement is based

ZFx86 Data Book 1.0 Rev D

on the need to de-assert FRAME# on the next
to last data transfer. The PCI write buffer will
be 16 DWORD entries long. Read Reordering
is NOT allowed for PCI cycles.

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3
The conditions for preventing or terminating a
burst sequence are:
• The next cycle is to a different (non-contiguous address).
• There are less than 3 entries in the PCI
write buffer.
• The PCI burst enable bit is turned off in the
PCIC register.
• The cycle is to a ROM region.
• The cycle is to I/O space.

3.3.5.1. CPU write/read to PCI
Since the CPU (32-bit X86) and PCI are of
same data widths, CPU memory and I/O
cycles are translated into corresponding PCI
cycles of the same type, except for writes and
reads to configuration address which is
explained in the next section.

3.3.5.2. PCI configuration address and
data registers
The PCI configuration address and data registers have been defined as 0CF8H and 0CFCH
respectively. The North Bridge (NB) is implementing the PCI configuration mechanism #1
with 64 bytes of configuration space (00H3FH). Since some registers within this 64
bytes are reserved, the PCI specification
requires any writes to these areas to be
ignored and any reads from these areas to be
returned as all 0s.

Writes and reads to the Configuration Address
port 0CF8H have to be full double-word and
the composition of the Configuration Address
register is in Figure 3-8 Translation of Type 0
Configuration Cycle, and Figure 3-9 Translation of Type 1 Configuration Cycle. Any
access other than full double-word access will
turn into an I/O cycle on the PCI bus. When
the CPU makes an access to the Configuration Data port 0CFCH, bit 31 of the Configuration Address register decides if its going to be
a configuration cycle or a ordinary I/O cycle.
Configuration cycles to the PCI register space
(Device Address = 0) are trapped to local PCI
registers; other accesses go out to the PCI as
Configuration cycles.
Configuration cycles can be Type 0 or Type 1,
and are differentiated in the way the mapping
of device address is done before it is presented on the PCI bus.
In Type 0 cycles the device address,
CONFIG_ADDR Register[15:11], is decoded
and presented on the AD[31:11] bits, the
CONFIG_ADDR Register[10:2] will go as is on
AD[10:2] and AD[1:0] are forced to ‘00’. In
Type 1 cycles the contents of the CONF Register[31:2] are copied to AD[31:2] and AD[1:0]
are forced to ‘01’. Both Type0 and Type1 configuration cycles are supported, and the type
of cycle run will depend on the value of the
“Bus Number” field in the Configuration
Address register. If it’s zero then Type 0 will be
run otherwise Type 1 would be run.

; Check to see if the NB is in it's default state.
mov
mov
out
add
in
sub
cmp

eax,
dx,
dx,
dl,
al,
dl,
al,

80009048h
0CF8h
eax
4
dx
4
04h

ZFx86 Data Book 1.0 Rev D

;
;
;
;
;
;
;
;
;

(EAX) = Function register
(DX) = PCI register.
Write it on out (full width)
DX = 0CFCH
Get the current value (I/O cycle)
DX = 0CF8H
Check to see if it's the
default value or we have been
programming it.

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3
; Check to see if NB is in it's default state.
mov
mov
out
add
in
sub
shr
cmp

eax,
dx,
dx,
dl,
eax,
dl,
eax,
al,

80009050h
0CF8h
eax
4
dx
4
16
98h

jz

SkipReset

;
;
;
;
;
;
;
;
;
;

(EAX) = Function register
(DX) = PCI register.
Write it on out.
DX - 0CFCH
Get the current value.
DX = 0CF8H
shift reg52 to AL
default value? (ROM read-write gets
changed at table programming (bit1)
Skip reseting PCI if default

; Do reset, if register content was not as
; defaults are supposed to be
;
DoReset:
POSTCODE 02h
mov
out
add
in
or
out
nop
nop
nop
and
out
or
out
sub
jmp

eax, 80009044h
dx, eax
dl, 4
al, dx
al, 0Eh
dx, al

;
;
;
;
;

(EAX) = reset control register, 5540.
Select the reset control register.
Move to PCI index register.
Get the reset status.
Reset PCI, IDE etc.

al, 0F0h
dx, al
al, 1
dx, al
dl, 4
DoReset

;
;
;
;

That reset was edge sensitive.
Clear reset bits
Do X-Bus reset (resets entire system)
do-it

; keep spinning until hardware reset

SkipReset:

ZFx86 Data Book 1.0 Rev D

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3
CONFIG_ADDRESS

31|30

24|23

Reserved

16|15

Bus Number

11|108|7

Device
Number

2|1

Register
Number

0

Type

Function
Number

Only One “1”
31

11|10

2|1

0

PCI_AD BUS
Figure 3-8 Translation of Type 0 Configuration Cycle

CONFIG_ADDRESS

31|30

24|23

Reserved

16|15

Bus Number

11|108|7

Device
Number

2|1

Register
Number

0

Type

Function
Number

01
31

2|1

0

PCI_AD BUS
Figure 3-9 Translation of Type 1 Configuration Cycle

ZFx86 Data Book 1.0 Rev D

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3.3.5.3. CPU to PCI bus cycle conversion
The Following table illustrates the conversion
of CPU cycles to PCI cycles. In most cases it

is one to one except where the configuration
space is involved.

Table 3.10 CPU-PCI Cycle Conversion
M/IO#

D/C#

W/R#

CPU bus definition

C/BE[3:0]#

PCI bus definition

0

0

0

Interrupt Acknowledge

0000

Interrupt Acknowledge

0

0

1

Special Cycle

0001

Special Cycle

0

1

0

I/O Read

0010

I/O Read

0

1

1

I/O Write

0011

I/O Write

0

1

0

I/O Read to CFCH

1010

Configuration Read

0

1

1

I/O Write to CFCH

1011

Configuration Write

1

X

0

Memory Read

0110

Memory Read

1

1

1

Memory Write

0111

Memory Write

3.3.5.4. PCI interrupt acknowledge cycle
The CPU generates 2 INTA cycles, for any
assertion of INTR. However, the PCI bus
specifies that only one INTA cycle is to be run
on the PCI bus. NB will swallow the first INTA
cycle from the CPU, and pass only the second
INTA cycle.

3.3.5.5. AD[31:0] must be actively
driven
If the CPU is the master, the NB must actively
drive out AD[31:0], C/BE[3:0]#, and PAR.

3.3.5.6. Hardware generated PCI special cycle
Hardware generated special cycles on the PCI
bus come from CPU generated special cycles
only. In particular, the CPU ‘SHUTDOWN’ and
‘HALT’ special cycles will be propagated to the
PCI bus and become PCI special cycles. All
other CPU special cycles should not propagate to the PCI bus. For the CPU ‘SHUTDOWN’ cycle, the value 0000H should be
driven out on AD[15:0], until the end of the PCI

ZFx86 Data Book 1.0 Rev D

cycle. For CPU the ‘HALT’ cycle, the value
0001H should be driven out on AD[15:0] until
the end of the PCI cycle. The normal PCI
cycle will have an address phase, followed by
the data phase, while a hardware PCI special
cycle will have an address phase only, and no
data phase.

3.3.5.7. PCI configuration access
For a PCI configuration access, AD[31:0] (in
address phase) needs to be driven out one
PCI clock before FRAME# is asserted. This
will allow enough precharge time for devices
that resistively connect their IDSEL signals to
the AD bus.

3.3.5.8. Master Abort
When the CPU is doing a I/O or memory read
from the PCI bus and a master abort condition
happens, NB must drive out all ‘1’s to the CPU
bus. This is the prescribed behavior for a CPU
bridge according to the PCI Spec. and this
event is recorded in the PCI Configuration Sta-

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tus register.

3.3.6. Write buffer architecture
3.3.6.1. Write FIFO depth
There are two 8 level deep write FIFO’s in NB.
The independent FIFO’s are for buffering
DRAM and PCI writes from the CPU.

3.3.6.2. Read re-ordering support for
DRAM
DRAM read around write should be allowed as
an option for performance purposes.

3.3.6.3. Empty write buffers before
disabling
When the write buffer enable bit has been programmed to disable, the internal logic must
ensure that the write buffer is emptied before
disabling the write buffer. This should be guaranteed by design, since a configuration cycle
(I/O space) will flush the buffers before disabling them.

3.3.6.4. All IO writes should not be
posted
All IO writes should not be posted. This mean
that BRDY# to the processor should not be
returned until the IO cycle is actually finished.

3.3.6.5. PCI Reads should wait for
Empty PCI buffers
All PCI reads should wait for the PCI write
buffer to empty.

3.3.6.6. Concurrent PCI and DRAM
operation
Due to the presence of 2 split write buffer’s,
allowing PCI memory writes and DRAM memory writes/reads to occur in parallel enhances
NB performance. For example, if the CPU
posts 6 PCI memory writes, these should all
be taken from the CPU at 0 or 1 Wait State
(dependent on L2). If the CPU follows with 5
DRAM writes and then a read, the read should
be serviced while the PCI memory writes are

ZFx86 Data Book 1.0 Rev D

in process and while the DRAM writes are
being stored (read-reordering).

3.3.7. System Management Mode
System Management Mode (SMM) provides
system designers with a means of adding new
software controlled features to their computer
products that always operate transparently to
the operating system (OS) and software applications. SMM is intended for use only by system firmware, not by applications software or
general purpose system software.
System Management Mode is entered when
the processor detects an SMI# (generated by
South Bridge). SMM is used for special power
management software or for transparent emulation of I/O devices. Special SMM memory
space is allocated to protect this software from
getting corrupted by the application or OS.
The processor after a RESET needs to be put
in the SL-mode by writing to CCR3 internal
CPU register. In SL-mode the processor generates SMIACT# after it gets an SMI# signal,
and it remains asserted until the RSMI instruction is executed by the SMM software. SMIACT# is generated on the pin marked
SMADS#, as in the default mode of the processor (ST-mode) special System Mode
Address Strobe# (SMADS#) is generated to
access SMM space. When SMIACT# is
asserted NB logic enables the access to the
special SMM memory during this time, which
is usually mapped over some normal memory
addresses explained in the following sections.

3.3.7.1. SMM base address
The SMM base address in the NB system is
defined as either 000D 0000H-000E FFFFH or
1DFD 0000H-1DFE FFFFH region, selected
via SMMC register in NB. The region selected
and its size should be programmed into the
CPU SMAR register. The size of the SMM
memory can be a multiple of 32Kbytes, to
maximum of 128KBytes

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3
All physical memory space used for SMM
memory is at A0000H-BFFFFH in DRAM. The
reason for physically locating SMM memory
here is that normally a Video memory space
exists here, which is never shadowed in the
local DRAM memory.

The address re-mapping logic for DRAM also
re-maps 20000H-3FFFFH to A0000HBFFFFH (physical memory) during the very
first SMM mode access after reset, when
SMMC[2]=0 to allow copying the SMM code.

SMM RAM

Normal Memory

Normal Memory

SMM RAM
Shadowed Region

Normal Memory

Non-overlaid
Region

Overlaid
Region
Figure 3-10 SMM RAM Location

3.3.7.2. L1 Cacheability of SMM RAM
The NB does not allow the SMM RAM to be
cached in the L1 cache if SMM RAM is
mapped to the lower SMM region by keeping
KEN# HIGH during SMM space access. If the
SMM RAM is mapped to the upper region i.e.
1DFD0000-1DFEFFFFh then SMM may be
cached if SMMC[1]=0 and the processor was
operating in the write-through mode. If the L1
was operating in the write-back mode then
BIOS should set SMMC[1] to a ‘1’ to disable
the caching to avoid dirty data remaining in the
L1 cache. "SMM Control Register (SMMC) Configuration Index 118H" on page 140
Reasons why the SMM cannot and should not
be cached in L1:

ZFx86 Data Book 1.0 Rev D

• If the CPU was operating in write-back
mode, the SMM RAM cannot be cached in
L1 as the CPU lacks a WB/WT# pin to put
SMM data in write-through mode. The
SMM data needs to be marked WT, as
after the SMI handler is finished the dirty
data in the L1 cache cannot be written
back to the memory as that SMM space
will not be available to the NB in the
normal mode to write back the data. This is
a CPU limitation.
• If the CPU was operating in the writethrough mode and SMM was mapped in
the lower region which may contain shadowed ROM, the L1 needs to be flushed on
the entry of the SMI handler by asserting
FLUSH# pin of the CPU. Flushing the
SMM code at the end of SMI handler by

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3
asserting the FLUSH# pin again immediately after de-assertion of SMI#. Presently the NB does not have this function to
assert FLUSH# on the start or end of SMI
handler.
The only condition under which SMM memory
can be cached in L1:
• If the CPU was in Write-through mode and
the SMM RAM is mapped to the upper
region, then it is not overlaid on a cacheable memory. Here no cache flushing is
needed at the start or at the end of SMI
handler.

3.3.7.3. SMM code copying to SMM
RAM in non-SMM mode
To copy the SMI handler in the SMM memory
space, LDSMIHLDER bit in the SMMC register should be set to ‘1’ and DIS23RMAP bit
(SMMC[2]) should be set to a ‘0’. See "SMM
Control Register (SMMC) - Configuration
Index 118H" on page 140. Then write to
address 20000H to 3FFFFH with the SMM
code, which actually writes to the physical
A0000H to BFFFFH area in the local DRAM.
Which means that BIOS or the loader software
should not be using the 20000H-3FFFFH
space for code or data storage during this
time. After the loading is complete BIOS
should set bit SMMC[2] to a ‘1’, which disables
the re-mapping of 20000H–3FFFFH to
A0000H-BFFFFH address for normal operation, and clear LDSMHLDER bit. Also the
SMIHLDERLOCK bit should be set in SMMC
after the loading to prevent access to this area
in the normal mode.

3.3.8. Power Management
3.3.8.1. CPU clock management
The South Bridge Core or Chip will do all the
power management. The NB will receive
SUSP# and SUPA# signals from the South
Bridge. On detection of SUSPA# assertion, if
the EN_STOP_CPU_CLK bit is a ‘1’ in the
Clock Control2 (CC2) register, the clock will be
stopped to the CPU within 2-4 clocks. On
detection of SUSP# de-assertion the clock to
the CPU will restart within 2-4 clocks.

3.3.8.2. PCI clock management
PCI clock to the PCI bus is free running.

3.3.8.3. Power Management for
SDRAMs
The CKE (clock enable) pin for SDRAM puts
the device into a low power state. If
EN_SDRAM_CKE_RST bit is a ‘1’ in the Clock
Control2 register, CKE will be driven low on
detection of P_SUSPA# assertion and will be
driven back HIGH on detection of SB_SUSP#
pin de-assertion.
Another bit EN_STOP_SDRAM_CLK in the
CC2 when set to ‘1’ will stop the clocks going
to SDRAM for even lower power consumption
under the conditions described above.

3.4. Register Set
Registers are divided into six groups:
• Reset Sampling
• Memory Configurations Registers
• Power Management Registers

3.3.7.4. Ban non-CPU masters from
accessing SMM RAM
When the PCI master accesses the memory
space reserved for SMM memory, NB will not
re-map the address and it will access the normal memory at that location.

ZFx86 Data Book 1.0 Rev D

• L2 Cache Controller Registers
• PCI Configuration Registers
• Miscellaneous Registers

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3
3.4.1. Register Address Map
The address of these registers will be maintained to be same as in 87550 chip. The register composition may change as certain bits
may be eliminated or meaning changed and
some new ones added.
Note: Some registers discussed here may not
be consecutively numbered; registers
reserved for future expansion are not shown in
this chapter. Ports 24h and 26h are used as
index and data register respectively. Note that

16-bit access to Port 24h and 26h will be
directed to the North Bridge and not passed to
the PCI bus. However, any byte access to
Ports 24h and 26h will be ignored by the North
Bridge and passed to the PCI bus.
This table shows the index numbers and
abbreviations, detailed register descriptions
follows.

Table 3.11 Configuration Registers
Bit

Name

Function

Def.

NB RevisionID Register (RID): Configuration Index 100H
3:0

North Bridge ID

15:4

Reserved

North Bridge version ID.

0H
All 0s

Programmable Region 1 Register (PR1): Configuration Index 110H
2:0

PREG1S<2:0>

Programmable region 1 block size:
000 =
001 =
010 =
011 =
100 =
101 =
11X =

15:3

PREG1S<27:15>

0H

32KB
64KB
128KB
256KB
512KB
1 MB
Reserved

Programmable region 1 starting address: The programmable region starting address must be a multiple of the
block size.

000H

Programmable Region 2 Register (PR2): Configuration Index 111H
2:0

PREG2S<2:0>

Programmable region 2 block size:
000 =
001 =
010 =
011 =
100 =
101 =
11X =

15:3

PREG2S<27:15>

ZFx86 Data Book 1.0 Rev D

0H

32KB
64KB
128KB
256KB
512KB
1 MB
Reserved

Programmable region 2 starting address: The programmable region starting address must be a multiple of the
block size.

000H

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3
Table 3.11 Configuration Registers (cont.)
Bit

Name

Function

Def.

Programmable Region 3 Register (PR3): Configuration Index 112H
2:0

PREG3S<2:0>

Programmable region 3 block size:
000 =
001 =
010 =
011 =
100 =
101 =
11X =

15:3

PREG3S<27:15>

0H

32KB
64KB
128KB
256KB
512KB
1 MB
Reserved

Programmable region 3 starting address: The programmable region starting address must be a multiple of the
block size.

000H

Programmable Region 4 Register (PR4): Configuration Index 113H
2:0

PREG4S<2:0>

Programmable region 4 block size:
000 =
001 =
010 =
011 =
100 =
101 =
11X =

15:3

PREG4S<27:15>

0H

32KB
64KB
128KB
256KB
512KB
1 MB
Reserved

Programmable region 4 starting address: The programmable region starting address must be a multiple of the
block size.

000H

Programmable Region Control Register (PRC): Configuration Index 114H
1:0

PRGREG1_SEL<1:0>

Programmable region 1 select <1:0>:
00 =
01 =
10 =
11 =

3:2

PRGREG2_SEL<1:0>

5:4

PRGREG3_SEL<1:0>

00

Disable
Reserved
non-cacheable
Reserved

Programmable region 3 select <1:0>:
00 =
01 =
10 =
11 =

ZFx86 Data Book 1.0 Rev D

Disable
Reserved
non-cacheable
Reserved

Programmable region 2 select <1:0>:
00 =
01 =
10 =
11 =

00

00

Disable
Reserved
non-cacheable
Reserved

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3
Table 3.11 Configuration Registers (cont.)
Bit

Name

Function

Def.

7:6

PRGREG4_SEL<1:0>

Programmable region 4 select <1:0>:

00

00 =
01 =
10 =
11 =
15:8

Disable
Reserved
non-cacheable
Reserved

Reserved

All 0s

Cacheability Override Register (COR): Configuration Index 115H
0

CACHE_OVR_A24

Cacheability Override A24: When set, all address with
A<24> high is marked non-cacheable. This corresponds to addresses in the range X1000000HX1FFFFFFH.

0

1

CACHE_OVR_A25

Cacheability Override A25: When set, all address with
A<25> high is marked non-cacheable. This corresponds to addresses in the range X2000000HX3FFFFFFH.

0

2

CACHE_OVR_A26

Cacheability Override A26: When set, all address with
A<26> high is marked non-cacheable. This corresponds to addresses in the range X4000000HX7FFFFFFH.

0

3

CACHE_OVR_A27

Cacheability Override A27: When set, all address with
A<27> high is marked non-cacheable. This corresponds to addresses in the range X8000000HXFFFFFFFH.

0

4

CACHE_OVR_A28

Cacheability Override A28: When set, all address with
A<28> high is marked non-cacheable. This corresponds to addresses in the range 10000000H1FFFFFFFH.

0

5

CACHE_OVR_A29

Cacheability Override A29: When set, all address with
A<29> high is marked non-cacheable. This corresponds to addresses in the range 20000000H3FFFFFFFH.

0

6

CACHE_OVR_A30

Cacheability Override A30: When set, all address with
A<30> high is marked non-cacheable. This corresponds to addresses in the range 40000000H7FFFFFFFH.

0

7

CACHE_OVR_A31

Cacheability Override A31: When set, all address with
A<31> high is marked non-cacheable. This corresponds to addresses in the range 80000000HFFFFFFFFH.

0

15:8

Reserved

ZFx86 Data Book 1.0 Rev D

All 0s

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3
Table 3.11 Configuration Registers (cont.)
Bit

Name

Function

Def.

Back-off Control Register (BCR): Configuration Index 117H
1:0

NONPOST_RETRY_CNT<1:0>

Non-posted PCI cycle retry count <1:0>
00 =
01 =
10 =
11 =

2

NONPOST_RETRY_DIS

3

Reserved

5:4

POST_RETRY_CNCT<1:0>

0

3
7
11
15

Disable PCI retry counter for non-posted cycle: 0 =
enable, 1 = disable

Posted PCI cycle retry count<1:0>
00 =
01 =
10 =
11 =

3
7
11
15

6

POST_RETRYCNT_DIS

Disable PCI retry counter for posted cycle: 0 = enable,
1 = disable

7

Reserved

8

RESET_CNT_ON_GNT

RESET retry counter on any bus master grant: 0 = not
reset on gnt, 1 = reset on gnt.

9

HLD_RETRY_ON_REQ

Hold retry on any PCI Bus Master Request: 0 = initiate
retry once before backoff, 1 = initiate retry only after all
pending PCI bus master requests have been serviced

15:10

Reserved

0

0

Table 3.12 SMM Control Register (SMMC)
Bit

Name

Function

Def.

SMM Control Register (SMMC) - Configuration Index 118H
0

Reserved

1

KDISSMMRAM

0
SMM RAM KEN disable: 1= KEN# held inactive (high) during access
to SMM RAM, 0 = KEN# function normally within SMM RAM.

0

Should always be set to ‘1’, to disallow caching.
2

DIS23RMAP

ZFx86 Data Book 1.0 Rev D

Disable 20000H-3FFFFH remap to A0000H-BFFFFH physical
memory in SMM mode: 0 = enabled, 1 = disabled.
Note: This bit can only be used while both L1 and L2 are disabled.

0

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3
Table 3.12 SMM Control Register (SMMC) (cont.)
Bit

Name

Function

Def.

3

FRCREMAP

Enables the SMM remapped address to be used in a non-SMM cycle.
This is used during loading of the SMM code to the memory. It works
in conjunction with bit 14 and 15 of this register, and they need to be
in the correct state to allow the loading.

0

5:4

SMM_DL_SEL[1:0]

SMM D0000H-D7FFFH select<1:0>:

00

00

XXXD0000H-XXXD7FFFH is not used as SMM space.

01

reserved

10

000D0000H-000D7FFFH is used as SMM space. remap to
000A0000H-000A7FFFH in physical DRAM space.)

11

1DFD0000H-1DFD7FFFH is used as SMM space. (remap
to 000A0000H-000A7FFFH in physical DRAM space.)

*Note: When programmed to 10, 000D0000H-000D7FFFH will be
automatically be set to non-cacheable.
7:6

SMM_DH_SEL[1:0]

SMM D8000H-DFFFFH select<1:0>:
00

XXXD8000H-XXXDFFFFH is not used as SMM space.

01

reserved

10

000D8000H-000DFFFFH is used as SMM space. (remap to
000A8000H-000AFFFFH in physical DRAM space.)

11

1DFD8000H-1DFDFFFFH is used as SMM space. (remap
to 000A8000H-000AFFFFH in physical DRAM space.)

00

*Note: When programmed to 10, 000D8000H-000DFFFFH will be
automatically bet set to non-cacheable.
9:8

SMM_EL_SEL[1:0]

SMM E0000H-E7FFFH select<1:0>:

00

00
01
10

XXXE0000H-XXXE7FFFH is not used as SMM space.
reserved
000E0000H-000E7FFFH is used as SMM space. (remap to
000B0000H-000B7FFFH in physical DRAM space.)
11
1DFE0000H-1DFE7FFFH is used as SMM space. (remap to
000B0000H-000B7FFFH in physical DRAM space.)
*Note: When programmed to 10, 000E0000H-000E7FFFH will be
automatically bet set to non-cacheable.
11:10

SMM_EH_SEL[1:0]

SMM E8000H-EFFFFH select<1:0>:

00

00
01
10

XXXE8000H-XXXEFFFFH is not used as SMM space.
reserved
000E8000H-000EFFFFH is used as SMM space. (remap to
000B8000H-000BFFFFH in physical DRAM space.)
11
1DFE8000H-1DFEFFFFH is used as SMM space. (remap
to 000B8000H-000BFFFFH in physical DRAM space.)
*Note: When programmed to 10, 000E8000H-000EFFFFH will be
automatically bet set to non-cacheable.

ZFx86 Data Book 1.0 Rev D

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3
Table 3.12 SMM Control Register (SMMC) (cont.)
Bit
12

Name

Function

SWAP_23_MAP

Swap SMM 2/3 mapping: 0 = 2/3 will be mapped to A/B, 1 = 2/3 will
be mapped to B/A. Here 2/3 and A/B refer to the address bits 19-16,
0=
1=

13

SWAP_DE_MAP

1=

0

2XXXX access will be mapped to AXXXX and 3XXXX to
BXXXX
2XXXX access will be mapped to BXXXX and 3XXXX to
AXXXX

Swap SMM D/E mapping: 0 = D/E will be mapped to A/B, 1 = D/E will
be mapped to B/A. Here again D/E and A/B refer to the address bits
19-16,
0=

Def.

0

DXXXX access will be mapped to AXXXX and EXXXX to
BXXXX
DXXXX access will be mapped to BXXXX and EXXXX to
AXXXX

14

LDSMIHLDER

Load SMI handler into SMM RAM: 1 = enable access to SMM RAM
during normal cycle, 0 = disable access to SMM RAM during normal
cycle.

0

15

SMIHLDERLOCK

SMM RAM access in normal mode lock: This bit provides an option
to lock bit 14 in a disabled state, thereby prohibiting any further
access to SMM RAM from normal mode. This bit can only be written
once. Reading a 0 from this bit indicates that bit 14 above is not
locked. Reading a 1 from this bit indicates that bit 14 above is locked
to disable state.

0

Table 3.13 Processor Control Register (PROC)
Bit

Name

Function

Def.

KEN enable: When low, KEN# will be forced to inactive state for all
cycles. When high, KEN# will be generated for all local memory
cycles.

0

Processor Control Register (PROC) - Configuration Index 119H
0

1

KENEN

L1WBEN

L1 write-back enable: When low, WB_WT# will be in write through
state always. When high, WB_WT# will be in write back state
whenever is possible.

1

NO WB_WT# pin on CPU
2

Reserved

3

Reserved

4

Reserved

ZFx86 Data Book 1.0 Rev D

0
Set to 1 in hardware.

1
0

Page 142

3
Table 3.13 Processor Control Register (PROC)
Bit
5

Name
WRFIFO_EN

Function

Def.

Enable write FIFO: 0 = disable, 1 = enable. This bit controls buffer
depth of CPU-PCI write buffer and CPU-SDRAM write buffer.
When disabled,
CPU-PCI depth = 2
CPU-SDRAM depth = 1

0

When enabled,
CPU-PCI depth is controlled by PCIWFIFOC register
CPU-SDRAM depth is controlled by WFIFOC registers
6

DIS_PSLOCK

Disable PSLOCK – When set to ‘1’, will disable the PSLOCK signal
from being used.

0

7

FLUSH

Setting this bit from 0->1, causes the core to set FLUSHnn pin to the
CPU to go LOW for 1 clock. To do another flush this bit should be
reset to ‘0’ and then set to 1.

0

8

DIS_FPUCLR_BY_F0

Disable clearing of FPU error by writing to IO port F0H: 0 = enable
clearing, 1 = disable clearing.

0

9

DIS_FPUCLR_BY_F1

Disable clearing of FPU error by writing to IO port F1H: 0 = enable
clearing, 1 = disable clearing.

0

10

WRM_RST

Warm Reset – When a ‘1’ is written to this bit, a warm reset
sequence initiates. It works the same as FLUSH bit. For example, to
do another warm reset, clear this bit to ‘0’ and then set it to 1.

0

Address 20 Mask – Used for DOS compatibility.

0

11

A20M

15:12

Reserved

All 0’s

Table 3.14 Write FIFO Control Register (WFIFOC)
Bit

Name

Function

Def.

Write FIFO Control Register (WFIFOC) - Configuration Index 11AH
2:0

FIFOD<2:0>

Write FIFO depth
000
001
010
011
100
101
110
111

3

DRMRDREODEREN

4

Reserved

ZFx86 Data Book 1.0 Rev D

000

8 dwords
7 dwords
6 dwords
5 dwords
4 dwords
3 dwords
2 dwords
1 dword

DRAM read re-ordering enable: 0 = disable, 1 = enable.
When this bit is set and when there’s pending DRAM write
cycle, a DRAM read operation will be performed before a
DRAM write operation.

0

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Table 3.14 Write FIFO Control Register (WFIFOC) (cont.)
Bit
5

Name
CPU&EM_DRAM ARBITRATION

Function
CPU/External Master DRAM Arbitration Priority Scheme: 0
0
CPU has NO Write Buffer access while Ext. Master is accessing DRAM
1

7:6

Reserved

11:8

RD2WR_LAT<3:0>

Def.

CPU has Write Buffer access’ while Ext. Master
is accessing DRAM
00

Read to write pending latency<3:0>: These bits indicate
the number of clocks to delay before switching from a read
cycle back to pending cycles in the write buffer. These
bits have no effect if the read re-ordering is disabled.

2H

Bits<3:0> Number of CPUCLKs
0H
reserved
1H
1
2H
2
3H
3
4H
4
5H
5
6H
6
7H
7
8H
8
9H
9
AH
10
BH
11
CH
12
DH
13
EH
14
FH
15
13:12

Reserved

15:14

WR_LATENCY<1:0>

00
DRAM write latency<1:0>: These bits indicate the number
of processor clocks write are stalled before being issued
to DRAM controller.

00

Bits<1:0> number of clocks
00
01
10
11

ZFx86 Data Book 1.0 Rev D

1
2
3
4

Page 144

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Table 3.15 PCI Control Register (PCIC)
Bit

Name

Function

Def.

PCI Control Register (PCIC) - Configuration Index 11BH
0

CPU2PCI_BURST_EN

CPU to PCI burst enable: When 0, the North Bridge only
does a single PCI transfer when CPU is accessing PCI
bus. When 1, the North Bridge will try to burst to PCI
when CPU is master.

0

1

PCIM2DRM_BRST_EN

PCI master to DRAM burst enable: When 0, the North
Bridge only does a single DRAM transfer when PCI master is accessing DRAM. When 1, the North Bridge tries to
do a burst to DRAM when PCI master is accessing.

0

2

BM_BURSTRD_ALWYS

PCI master read prefetch always: When 0, only PCI read
line or PCI read multiple starts a burst read request. For
PCI single read, a burst read request initiates only after
the first data phase completes and PCI master indicates
that it wants a burst access. When 1, any PCI read cycle
initiates a burst read request.
Note: In order to enable this feature, bit[1] must be
enabled.

0

3

DISC_ON_LN_BOUNDARY

Disconnect from PCI master on CACHE line boundary:
0 = no disconnect, 1 = disconnect.

0

4

EN_PCI_FAST_DECDE

Enable PCI fast decode when accessing DRAM:
0 = disable, 1 = enable.

0

5

EN_ADCBE_FLT_IDLE

Enable AD/CBE/PAR float when PCI is idle and CPU is
the bus master: 0 = disable float, 1 = enable float.

0

6

DIS_RESOURCE_LOCK

Disable Resource Lock: 0 = enable, 1 = disable.

0

Note: when EN_BUS_LOCK(bit 7) is set to 1, this bit
ignored.
7

EN_BUS_LOCK

Enable Bus Lock: 0 = disable, 1 = enable. When
enabled, GNT# to a particular PCI master remains
asserted until LOCK# is deasserted.
Note: When this bit is set to 1,
DIS_RESOURCE_LOCK(BIT 6) ignored.

0

8

LCK_RDBURST_EN

Enable the locking of PCI bus during a 64-bit processor
read access to the PCI bus.
0 = disable, 1 = enable.

0

9

CNFCY_AD_STEP_DIS

PCI configuration cycle address stepping disable:
0 = enable, 1 = disable.

0

10

BM_DONE_DIS

Disable the waiting of PCI master cycle is done before
0
starting processor initated PCI cycle. 0 = enable, 1 = disable. When enabled, the North Bridge’s PCI master controller will not start until, 1)PCI master initiated cycle is
done, 2)PCI master write buffer is empty, and 3) PCI master read prefetch is done.

11

Reserved

0

12

Reserved

0

ZFx86 Data Book 1.0 Rev D

Page 145

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Table 3.15 PCI Control Register (PCIC) (cont.)
Bit
15:12

Name

Function

Reserved

Def.
All 0’s

Table 3.16 Clock Skew Adjust Register (CSA)
Bit

Name

Function

Def.

Clock Skew Adjust Register (CSA) - Configuration Index 11CH
2:0

Reserved

5:3

SDRAMCLK_SKEW

000
There three bits control the skew between the core clock
and the SDRAM clock.
000 –
001 –
010 –
100 –
101 –
Reset –

15:6

000

Nominal
Minus 1 nsec
Minus 2 nsec
Plus 1 nsec
Plus 2 nsec
Default to Nominal

Reserved

All 0’s

Table 3.17 BUS MASTER And Snooping Control Register (SNOOPCTRL)
Bit

Name

Function

Def.

BUS MASTER And Snooping Control Register (SNOOPCTRL) - Configuration Index 11DH
0

DIS_SNOOP

Disable Snooping: 0 = enable snoop, 1 = disable snoop.

0

1

DIS_CHK_HITM

Disable the check of HITM#: 0 = enable the checking of
HITM# during snooping. 1 = disable the checking of
HITM# during snooping. In either case, the L1 cache may
be invalidated with INVAL signal.

0

3:2

CK_HITM_WS<1:0>

Check HITM# wait state:
00
2 clock after EADS# is deasserted.
01
3 clocks after EADS# is deasserted.
10
4 clocks after EADS# is deasserted.
11
5 clocks after EADS# is deasserted.

00

4

ADP_PREF_DIS

Adaptive Prefetch Disable: 0 = enable, 1 = disable. When
enabled, the North Bridge will monitor the average burst
transfer length of a master access and than control the
number of speculative prefetches accordingly.

0

5

Reserved

ZFx86 Data Book 1.0 Rev D

0

Page 146

3
Table 3.17 BUS MASTER And Snooping Control Register (SNOOPCTRL) (cont.)
Bit
6

Name
DIS_WB_MERGE

Function
0=

1=
7

DIS_EM_PREFETCH

0=
1=

Def.

Merge CPU/L2 Write-back data with External
Master writes. The External Master’s valid bytes
overwrite the data cast-out from the CPU/L2 and
subsequently limit the bandwidth requirements to
the s/dram.
Do not merge External Master write data bytes
with CPU/L2 write-back cycle.

0

Prefetch next “cache” line on EM accesses, and
store in prefetch buffer
Disable prefetch logic for External Masters
(CPU clock based)

0

8

DIS_CONCURRENCY

CPU/PCI master concurrency disable:
0 = enable, 1 = disable.

0

9

FAST_TRDY

0=
1=

Normal TRDY# timings
Enable Fast TRDY# timings to EM. Improves
path from prefetch data ready (from CPU writeback, yes we snarf-see bit 10, or from DRAM)

0

10

DIS_BUS_SNARF

0=

Snarf CPU write-back data and return it to the
requesting External Master (read), concurrent
with it’s retirement into DRAM.
Disable bus snarfing and create 2nd cycle to get
data after the write-back has retired it to DRAM.

0

1=
11

FORCE_DRM_PM_PCIM

Force DRAM page miss in bus master cycle:
0=
1=

12

Reserved

13

DISPCIM_ELY_DRM_CY

0

Disable force page miss mode
Enable force page miss mode.
0

Speculatively start DRAM cycle for PCI External Master
Request and restart it in the event of an L1 or L2 writeback: 0 = enable, 1 = disable.

0

Errata: LNB will corrupt system memory with 2 PCI masters. This bug can be eliminated by setting bit 13 -DISPCIM_ELY_DRM_CY, in the SNOOPCTRL register.
14

Reserved

15

DISPCIM_SHADOWRAM

ZFx86 Data Book 1.0 Rev D

0
0=

Claim cycle for PCI Master access to 000C0000- 0
000F0000 region:
1=
Do not Claim cycle for PCI Master access to
ROM space (shadowed RAM)
Note: All DRAM Write/Read protect bits are still applicable

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3
Table 3.18 Arbiter Control Register (ARBCTRL)
Bit

Name

Function

Def.

Arbiter Control Register (ARBCTRL) - Configuration Index 11EH (see also PCI register section REG 41H)
0

REQa_slot0

0=
1=

Disable Slot 0 for REQa
Enable Slot 0 for REQa

0

1

REQa_slot1

0=
1=

Disable Slot 1 for REQa
Enable Slot 1 for REQa

0

2

REQb_slot2

0=
1=

Disable Slot 2 for REQb
Enable Slot 2 for REQb

0

3

REQa_slot3

0=
1=

Disable Slot 3 for REQa
Enable Slot 3 for REQa

0

4

REQpci_slot4

0=
1=

Disable Slot 1 for 2nd Arbitration of PCI (see diagram)
Enable Slot 1 for 2nd Arbitration of PCI (see diagram)

0

5

PC98_support

0=
1=

V4REQ#/V4GNT# pair treated as such.
The V4REQ#/V4GNT# pair is treated as PHOLD#/PHLDA#

0

6

SIO_HIPRI

0=
1=

Fair Arbitration between V3 & V4 REQ# pins
Always give priority to V3 REQ#

0

7

Reserved

[15:8]

CPU_BUSY_TIMER

0
Number of PCI bus clocks that the CPU can “own” of the PCI bus
before it is preempted by any other active requesters
00H =
01H =
02H =
FFH =

00H

Never preempt the CPU
4 clks
8 clks...
1024 clks

Table 3.19 PCI Write FIFO Control Register (PCIWFIFOC)
Bit

Name

Function

Def.

PCI Write FIFO Control Register (PCIWFIFOC) - Configuration Index 120H
2:0

FIFOD[2:0]

PCI Write FIFO depth
Bits
000
001
010
011
100
101
110
111

000

FIFO depth
16 dwords
14 dwords
12 dwords
10 dwords
8 dwords
6 dwords
4 dwords
2 dwords

3

Reserved

0

4

Reserved

0

ZFx86 Data Book 1.0 Rev D

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3
Table 3.19 PCI Write FIFO Control Register (PCIWFIFOC)
Bit

Name

Function

Def.

5

PCI BM_FREERUNMODE

PCI master write buffer PCI entry count free running mode
bit. Transfer loop which copies CPU clocked write buffer
entry count to PCI clocked entry count normally operates
in an on-demand mode. This forces a free running mode
which update the PCI every 6 or 8 CPU clocks (see slow
transfer bit below).

0

6

PCI_BM_SLOWRUNMODE

PCI master write buffer PCI entry count slow transfer
mode. Increases transfer loop period from 6 CPU clocks
to 8 CPU clocks. Transfer loop period is defined as how
often the PCI side entry count is updated from the CPU
entry count.

0

0=
1=

8:7

STALL_PCI_BM_POST

6 CPU clocks
8 CPU clocks

Stall PCI master posting:

00

Bits<1:0> # of clocks
00
no stall
01
1 clock
10
3 clocks
11
7 clocks
11:9

Reserved

All 0’s

15:12

0

3.4.2. DRAM registers
Table 3.20 Shadow RAM Read Enable Control Register (SHADRC)
Bit

Name

Function

Def.

Shadow RAM Read Enable Control Register (SHADRC) - Configuration Index 200H
0

LMEMRDEN0

Local memory C0000H-C3FFFH read enable:
0 = disable, 1 = enable.

0

1

LMEMRDEN1

Local memory C4000H-C7FFFH read enable:
0 = disable, 1 = enable.

0

2

LMEMRDEN2

Local memory C8000H-CBFFFH read enable:
0 = disable, 1 = enable.

0

3

LMEMRDEN3

Local memory CC000H-CFFFFH read enable:
0 = disable, 1 = enable.

0

4

LMEMRDEN4

Local memory D0000H-D3FFFH read enable:
0 = disable, 1 = enable.

0

5

LMEMRDEN5

Local memory D4000H-D7FFFH read enable:
0 = disable, 1 = enable.

0

6

LMEMRDEN6

Local memory D8000H-DBFFFH read enable:
0 = disable, 1 = enable.

0

7

LMEMRDEN7

Local memory DC000H-DFFFFH read enable:
0 = disable, 1 = enable.

0

ZFx86 Data Book 1.0 Rev D

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3
Table 3.20 Shadow RAM Read Enable Control Register (SHADRC) (cont.)
Bit

Name

Function

Def.

8

LMEMRDEN8

Local memory E0000H-E3FFFH read enable:
0 = disable, 1 = enable.

0

9

LMEMRDEN9

Local memory E4000H-E7FFFH read enable:
0 = disable, 1 = enable.

0

10

LMEMRDEN10

Local memory E8000H-EBFFFH read enable:
0 = disable, 1 = enable.

0

11

LMEMRDEN11

Local memory EC000H-EFFFFH read enable:
0 = disable, 1 = enable.

0

12

LMEMRDEN12

Local memory F0000H-F3FFFH read enable:
0 = disable, 1 = enable.

0

13

LMEMRDEN13

Local memory F4000H-F7FFFH read enable:
0 = disable, 1 = enable.

0

14

LMEMRDEN14

Local memory F8000H-FBFFFH read enable:
0 = disable, 1 = enable.

0

15

LMEMRDEN15

Local memory FC000H-FFFFFH read enable:
0 = disable, 1 = enable.

0

Table 3.21 Shadow RAM Write Enable Control Register
Bit

Name

Function

Def.

Shadow RAM Write Enable Control Register (SHADWC) - Configuration Index 201H
0

LMEMWREN0

Local memory C0000H-C3FFFH write enable:
0 = disable, 1 = enable.

0

1

LMEMWREN1

Local memory C4000H-C7FFFH write enable:
0 = disable, 1 = enable.

0

2

LMEMWREN2

Local memory C8000H-CBFFFH write enable:
0 = disable, 1 = enable.

0

3

LMEMWREN3

Local memory CC000H-CFFFFH write enable:
0 = disable, 1 = enable.

0

4

LMEMWREN4

Local memory D0000H-D3FFFH write enable:
0 = disable, 1 = enable.

0

5

LMEMWREN5

Local memory D4000H-D7FFFH write enable:
0 = disable, 1 = enable.

0

6

LMEMWREN6

Local memory D8000H-DBFFFH write enable:
0 = disable, 1 = enable.

0

7

LMEMWREN7

Local memory DC000H-DFFFFH write enable:
0 = disable, 1 = enable.

0

8

LMEMWREN8

Local memory E0000H-E3FFFH write enable:
0 = disable, 1 = enable.

0

9

LMEMWREN9

Local memory E4000H-E7FFFH write enable:
0 = disable, 1 = enable.

0

ZFx86 Data Book 1.0 Rev D

Page 150

3
Table 3.21 Shadow RAM Write Enable Control Register
Bit

Name

Function

Def.

10

LMEMWREN10

Local memory E8000H-EBFFFH write enable:
0 = disable, 1 = enable.

0

11

LMEMWREN11

Local memory EC000H-EFFFFH write enable:
0 = disable, 1 = enable.

0

12

LMEMWREN12

Local memory F0000H-F3FFFH write enable:
0 = disable, 1 = enable.

0

13

LMEMWREN13

Local memory F4000H-F7FFFH write enable:
0 = disable, 1 = enable.

0

14

LMEMWREN14

Local memory F8000H-FBFFFH write enable:
0 = disable, 1 = enable.

0

15

LMEMWREN15

Local memory FC000H-FFFFFH write enable:
0 = disable, 1 = enable.

0

Table 3.22 Bank 0 Control Register (N_B0C)
Bit

Name

Function

Def.

Bank 0 Control Register (N_B0C) - Configuration Index 202H
7:0

B0A<27:20>

8

Reserved

11:9

B0S<2:0>

Bank 0 starting address <27:20>

0
Bank 0 DRAM size
Bits<2:0>
000
001
010
011
100
101
110
111

14:12

COLADR0<2:0>

00H
000

DRAM bank size
2MB
4MB
8MB
16MB
32MB
64MB
Reserved
Reserved

Number of column address bits for Bank 0<2:0>

000

Bits<2:0>Column address
000
8 bits
001
9 bits
010
10 bits
all othersReserved
15

Reserved

ZFx86 Data Book 1.0 Rev D

0

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3
Table 3.23 Bank 0 Timing Control Register (N_B0TC)
Bit

Name

Function

Def.

Bank 0 Timing Control Register (N_B0TC) - Synchronous DRAM - Configuration Index 204H
1:0

B0_TRP

SDRAM Pre-charge cmd to ACT cmd

11

Bits<1:0>
Time
00
Reserved
01
2T
10
3T
11
4T
3:2

B0_TRC

SDRAM ACT cmd to ACT cmd (same bank)

11

Bits<3:2> Addr. hold time
00
6T
01
7T
10
8T
11
9T
6:4

Reserved

111

7

B0_CAS_LATCY

SDRAM CAS Latency: 0 = 2T, 1 = 3T

1

8

B0_TRCD

SDRAM ACT cmd to R/W cmd delay: 0 = 2T,
1 = 3T

1

9

B0_TCCD

SDRAM R/W cmd to R/W cmd: 0 = 1T, 1 = 2T

1

15:10

Reserved

All ‘1’s

Table 3.24 Bank 1 Control Register (N_B1C)
Bit

Name

Function

Def.

Bank 1 Control Register (N_B1C) - Configuration Index 205H
7:0

B1A<27:20>

8

Reserved

11:9

B1S<2:0>

Bank 1 starting address <27:20>

00H
0

Bank 21DRAM size

000

Bits<2:0> DRAM bank size
000
2MB
001
4MB
010
8MB
011
16MB
100
32MB
101
64MB
110
Reserved
111
Reserved

ZFx86 Data Book 1.0 Rev D

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3
Table 3.24 Bank 1 Control Register (N_B1C) (cont.)
Bit
14:12

Name
COLADR1<2:0>

Function
Number of column address bits for Bank 2

Def.
000

Bits<2:0>Column address
000
8 bits
001
9 bits
010
10 bits
all othersReserved
15

Reserved

0

Table 3.25 Bank 1 Timing Control Register (N_B1TC)
Bit

Name

Function

Def.

Bank 1 Timing Control Register (N_B1TC) - Synchronous DRAM - Configuration Index 207H
1:0

B1_TRP

SDRAM Pre-charge cmd to ACT cmd

11

Bits<1:0> Time
00
Reserved
01
2T
10
3T
11
4T
3:2

B1_TRC

SDRAM ACT cmd to ACT cmd (same bank)

11

Bits<3:2>Addr. hold time
00
6T
01
7T
10
8T
11
9T
6:4

Reserved

7

B1_CAS_LATCY

SDRAM CAS Latency: 0 = 2T, 1 = 3T

1

8

B1_TRCD

SDRAM ACT cmd to R/W cmd delay: 0 = 2T, 1 = 3T

1

9

B1_TCCD

SDRAM R/W cmd to R/W cmd: 0 = 1T, 1 = 2T

1

15:10

Reserved

All ‘1’s

Table 3.26 Bank 2 Control Register (N_B2C)
Bit

Name

Function

Def.

Bank 2 Control Register (N_B2C) - Configuration Index 208H
7:0

B2A<27:20>

8

Reserved

ZFx86 Data Book 1.0 Rev D

Bank 2 starting address <27:20>

00H
0

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3
Table 3.26 Bank 2 Control Register (N_B2C)
Bit
11:9

Name
B2S<2:0>

Function
Bank 2 DRAM size

Def.
000

Bits<2:0>DRAM bank size
000
2MB
010
8MB
011
16MB
100
32MB
101
64MB
110
Reserved
111
Reserved
14:12 COLADR2<2:0>

Number of column address bits for Bank 4

000

Bits<2:0>Column address
000
8 bits
001
9 bits
010
10 bits
all others Reserved
15

Reserved

0

Table 3.27 Bank 2 Timing Control Register (N_B2TC)
Bit

Name

Function

Def.

Bank 2 Timing Control Register (N_B2TC) - Synchronous DRAM - Configuration Index 20AH
1:0

B2_TRP

SDRAM Pre-charge cmd to ACT cmd
Bits <1:0> Time
00
Reserved
01
2T
10
3T
11
4T

11

3:2

B2_TRC

SDRAM ACT cmd to ACT cmd (same bank)
Bits <3:2> Addr. hold time
00
6T
01
7T
10
8T
11
9T

11

6:4

Reserved

7

B2_CAS_LATCY

SDRAM CAS Latency: 0 = 2T, 1 = 3T

1

8

B2_TRCD

SDRAM ACT cmd to R/W cmd delay: 0 = 2T, 1 = 3T

1

9

B2_TCCD

SDRAM R/W cmd to R/W cmd: 0 = 1T, 1 = 2T

1

15:10

Reserved

ZFx86 Data Book 1.0 Rev D

All ‘1’s

Page 154

3
Table 3.28 Bank 3 Control Register (N_B3C)
Bit

Name

Function

Def.

Bank 3 Control Register (N_B3C) - Configuration Index 20BH
7:0

B3A<27:20>

8

Reserved

Bank 3 starting address <27:20>

00H

11:9

B3S<2:0>

Bank 3 DRAM size
Bits <2:0> DRAM bank size
000
2MB
001
4MB
010
8MB
011
16MB
100
32MB
101
64MB
110
Reserved
111
Reserved

000

14:12

COLADR3<2:0>

Number of column address bits for Bank 6
Bits<2:0> Column address
000
8 bits
001
9 bits
010
10 bits
011
11 bits
100
12 bits
all others Reserved

000

15

Reserved

0

0

Table 3.29 Bank 3 Timing Control Register (N_B3TC)
Bit

Name

Function

Def.

Bank 3 Timing Control Register (N_B3TC) - Synchronous DRAM - Configuration Index 20DH
1:0

B3_TRP

SDRAM Pre-charge cmd to ACT cmd

11

Bits<1:0> Time
00
Reserved
01
2T
10
3T
11
4T
3:2

B3_TRC

SDRAM ACT cmd to ACT cmd (same bank)

11

Bits<3:2>
Addr. hold time
00
6T
01
7T
10
8T
11
9T
6:4

Reserved

7

B3_CAS_LATCY

ZFx86 Data Book 1.0 Rev D

SDRAM CAS Latency: 0 = 2T, 1 = 3T

1

Page 155

3
Table 3.29 Bank 3 Timing Control Register (N_B3TC) (cont.)
Bit
8

Name
B3_TRCD

Function
SDRAM ACT cmd to R/W cmd delay:

Def.
1

0 = 2T, 1 = 3T
9

B3_TCCD

15:10

Reserved

SDRAM R/W cmd to R/W cmd:

1

0 = 1T, 1 = 2T
All ‘1’s

Table 3.30 DRAM Configuration Register 1 (DCONF1)
Bit

Name

Function

Def.

DRAM Configuration Register 1 (DCONF1) - Configuration Index 20EH
2:0

Reserved

5:3

DRAM_INAT_TO

000
DRAM inactive time-out<2:0>
Bits<2:0> Page size
000
never
001
8T
010
32T
011
128T
100
512T
101
reserved
110
reserved
111
immediate

000

If SDRAM interface is inactive for the set amount of time,
a Pre-charge cycle is generated at the end of timeout.
Pre-charge cycle de-activates the DRAM row which may
be in “ACTIVE” state. Doing a Pre-charge cycle when
SDRAM is in-active for a while saves power. But the next
memory cycle may be to the row which was just closed,
and takes a hit of running a RAS cycle causing lower performance.
7:6

Reserved

8

Reserved

9

Reserved

10

Reserved

11

SDRAM_CMD_PIPELINE

ZFx86 Data Book 1.0 Rev D

00
Fixed to ‘0’ in the hardware

0
0

SDRAM command pipeline enable: 0 = disable the pipelining of SDRAM command cycle. 1 = enable the pipelining of SDRAM command cycle.

0

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3
Table 3.30 DRAM Configuration Register 1 (DCONF1) (cont.)
Bit

Name

Function

Def.

12

EN_RELAX_SDRM_CMD_TMING

Enable relax timing for SDRAM command cycle.
0 = disable,
1 = enable relax timing to the SDRAM command cycle.
=1 MA, RAS, CAS and WE are asserted 1 clk before CS is
asserted.
Note: setting this bit to 1 will not affect performance but at
the same time, allow the potential of not buffering MA,
SDRAM_RAS, SDRAM_CAS, and WE# externally.

0

13

EN_SDRM_PWRDN

Enable SDRAM power-down mode during mix DRAM type
configuration: 0 = disable, 1 = enable SDRAM to get into
power-down mode during mix DRAM type configuration
and when access is to anywhere other than SDRAM.
FW should always set this bit to ‘0’

0

14

FST_SDRM_RD_L2_EN

Enable fast SDRAM read access when L2 is on:
0 = disable, 1 = enable.
FW should always set this bit to ‘0’

0

15:14

Reserved

00

Table 3.31 DRAM Configuration Register 2 (DCONF2)
Bit

Name

Function

Def.

DRAM Configuration Register 2 (DCONF2) - Configuration Index 20FH
0

BANK0_16EN

Bank 0 enable: 0 = disable, 1 = enable.
When enabled, bank 0 operates as a 16bit bank.

1

1

BANK1_16EN

Bank 1 enable: 0 = disable, 1 = enable.
When enabled, bank 1 operates as a 16bit bank.

0

2

BANK2_16EN

Bank 2 enable: 0 = disable, 1 = enable.
When enabled, bank 2 operates as a 16 bit bank.

0

3

BANK3_16EN

Bank 3 enable: 0 = disable, 1 = enable.
When enabled, bank 3 operates as a 32 bit bank.

0

7:4

Reserved

8

BANK0_32EN

0000
=0 Bank 0 disabled (bit0 overides this)

0

=1 Bank 1 enabled as 32 bit bank (this bit overides bit 0)
9

BANK1_32EN

=0 Bank 0 disabled (bit1 overides this)

0

=1 Bank 1 enabled as 32 bit bank (this bit overides bit 1)
10

BANK2_32EN

=0 Bank 0 disabled (bit2 overides this)

0

=1 Bank 1 enabled as 32 bit bank (this bit overides bit 2)
11

BANK3_32EN

=0 Bank 0 disabled (bit3 overides this)

0

=1 Bank 1 enabled as 32 bit bank (this bit overides bit 3)
15:12

Reserved

ZFx86 Data Book 1.0 Rev D

0H

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Table 3.32 DRAM Refresh Control Register (DRFSHC)
Bit

Name

Function

Def.

DRAM Refresh Control Register (DRFSHC) - Configuration Index 211H
4:0

Reserved

00000

7:5

REFRPRD<2:0>

Refresh period: These bits determine the refresh period
for local DRAM.

101

Bits<2:0> Refresh period
000
15us
001
15us
010
15us
011
30us
all others stopped
10:8

Reserved

000

11

MANUAL_REFRESH

13:12

Reserved

11

15:14

Reserved

00

Manual refresh control: A 1-> 0->1 generates a refresh 0
cycle after 128 process clocks. Also, this bit forces normal refresh disabled while left at the 1 setting.

Table 3.33 SDRAM Mode Program Register (SDRAMMPR)
Bit

Name

Function

Def.

SDRAM Mode Program Register (SDRAMMPR) - Configuration Index 213H
0

EN_SDRAM_CONFIG

Enable SDRAM MRS configuration cycle:
0 = disable, 1 = enable.

0

2:1

SDRAM_BANK_CONFIG[1:0]

SDRAM bank configuration select <1:0> programming
options as follows:
Bits<1:0> DRAM bank
00
Bank 0
01
Bank 1
10
Bank 2
11
Bank 3

00

4:3

POWERON_SEQ[1:0]

SDRAM Power-on initialization sequence bits
Bits<1:0>
Function
00
Normal
01
Pre-charge SDRAM bank specified by
BANK_CONFIG[1:0]
10
Trigger Mode Program Register Command
11
Trigger CBR refresh cycle

00

ZFx86 Data Book 1.0 Rev D

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Table 3.33 SDRAM Mode Program Register (SDRAMMPR)
Bit
15:5

Name
WCBR_MA[11:1]=

Function
MA[0]

[2:0]

[3]
[6:4]

[11:7]

comes from the SDRAMMPEX register as it is
needed to handle 16 bit banks to do 8 burst
cycles
set to ‘010’ corresponding to burst length of 4 for
32 bit banks
set to ‘011’ corresponding to burst length of 8 for
16 bit banks
always set to 0 linear burst type (Fixed in
hardware)
010
CAS Latency 2
011
CAS Latency 3
Others Reserved
Always leave at ‘00000’

Def.
019H

Note: MA[13:12] will be forced to 0 always during SDRAM
configuration cycle

Table 3.34 SDRAM Mode Program Register (SDRAMMPREX)
Bit

Name

Function

Def.

SDRAM Mode Program Register (SDRAMMPREX) - Configuration Index 214H
0

WCBR_MA[0]

15:1

Reserved

SDRAM Mode Register bit 0 used together with bits 11:1
defined earlier.

0
0000

Table 3.35 SDRAM Slew Control Register (SDRAMSLEW)
Bit

Name

Function

Def.

SDRAM Slew Control Register (SDRAMSLEW) - Configuration Index 239H
2:0

MD_DQM_SLEW

32 Bit Data and 4 Bit Mask Bus: MD[31:0], DQM[3:0]
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =

111

Force Tri-State
2*N-ch + 4*P-ch
3*N-ch + 6*P-ch
5*N-ch + 10*P-ch
4*N-ch + 8*P-ch
6*N-ch + 12*P-ch
7*N-ch + 14*P-ch
8*N-ch + 16*P-ch

5:3

MA_SLEW

14 Bit Address Bus: BA[1:0], MA[11:0]
Encoding same as for 2:0 bits

111

8:6

RAS_CAS_SLEW

RASnn and CASnn Encoding same as for 2:0 bits

111

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Table 3.35 SDRAM Slew Control Register (SDRAMSLEW) (cont.)
Bit

Name

Function

Def.

11:9

WE_SLEW

Write Enable: Wenn
Encoding same as for 2:0 bits

111

14:12

CS_SLEW

4 Chip Select: CSnn[3:0]
Encoding same as for 2:0 bits

111

15

DATA_BUS_HOLD

Data Bus Holder enabled when LOW

1

3.4.3. Power Management registers
Table 3.36 Clock Control Register (CC)
Bit

Name

Function

Def.

Clock Control Register (CC) - Configuration Index 300H
15:0

Reserved

ZFx86 Data Book 1.0 Rev D

All 0’s

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3
Table 3.37 Clock Control2 Register (CC2)
Bit

Name

Function

Def.

Clock Control 2 Register (CC2) - Configuration Index 3FFH
0

EN_STOP_CPU_CLK

Enables stopping of CPU clock during Suspend mode.
Stopping the clock conserves more power than placing the
CPU in suspend mode. This bit allows the BIOS decide.

0

1

EN_SDRAM_CKE_RST

Enables resetting of SDRAM CKE (clock enable) input
during suspend mode.

0

2

EN_STOP_SDRAM_CLK

Enables stopping of SDRAM CLK during Suspend mode.
Different from SDRAMCLK disable bit in CSA, which
always disables the clock. Only use this bit during suspend mode.

0

3

EN_STOP_CORE_CLK

Enable stopping the core clock during suspend mode.
When set to 1, it stops the clocks to most of the cores
except the clocks needed to detect the end of suspend
mode.

0

15:4

Reserved

All "0"s

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3
3.4.4. Test Signals
Table 3.38 CPU-SYNC Register (CPUSYNC)
Bit

Name

Function

Def.

CPU-SYNC Register (CPUSYNC) - Configuration Index 238H
0

SYNC_OUT

15:1

Reserved

This bit when set to 1, generates a pulse on the
SYNC_OUT port of the NB of 2 processor clock wide.
This bit is not sticky i.e. writing a 1 will be cleared to zero
within two clocks.

0H

00H

3.4.5. PCI configuration registers
Note that any read to PCI registers between
00H-FFH which are not described below must
return all 0s.

Table 3.39 Vendor ID Register (VID)
Bit

Name

Function

Def.

Vendor ID Register (VID) - Configuration Index 00H
15:0

VENDOR_ID

Vendor ID number. These bits are hard-wired.

1066H

Table 3.40 Device ID Register (DID)
Bit

Name

Function

Def.

Device ID Register (DID) - Configuration Index 02H
31:16

DEVICE_ID

Device ID number. These bits are hard-wired.

0005H

Table 3.41 Command Register (COMMD)
Bit

Name

Function

Def.

Command Register (COMMD) - Configuration Index 04H
0

Reserved

1

MEM_RESPOND

5:2

Reserved

6

PARERR_REP

15:7

Reserved

ZFx86 Data Book 1.0 Rev D

0
Memory space enable:
0 = PCI master access to main memory disabled.
1 = PCI master access to main memory is enabled.

1

1H
Parity Error Respond:
0 = the North Bridge does not assert PERR# when a PCI
parity error detected
1 = the North Bridge asserts PERR# when a PCI parity
error detected. .

0

0

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Table 3.42 Status Register (STAT)
Bit

Name

Function

Def.

Status Register (STAT) - Configuration Index 06H
22:16

Reserved

All ‘0’s

23

FAST_B2B_STAT

Fast Back-to-Back status – Use this bit when
EN_PCI_FAST_DCD bit in the PCIC register is set.
This bit indicates that NB as a target can accept fast
back-to-back cycles from another master.

0

24

DATA_PAR_DET

Data Parity Detected: Set this bit when operating as a
bus master and either the PERR# output is driven low
by the North Bridge or the target asserts PERR# and bit
6 of the Device Control Register is set. Reset this bit
writing a 1.

0

26:25

DEVSEL_TIM

DEVSEL Timing: These bits indicate the slowest time
that NB will return DEVSEL#. 00 = fast, 01 = medium,
10 = slow, 11 = reserved.
Note that these bits are hard-wired to 01

01

27

Reserved

28

REC_TAG_ABRT

Receive Target Abort: Reading a 1 indicates receiving
a target abort condition. Reset this bit by writing a 1.

0
0

29

REC_MST_ABRT

Receive Master Abort: Reading a 1 indicates receiving
a master abort condition(not including master abort
generated from a special cycle).
Reset this bit by writing a 1.

0

30

Reserved

31

DET_PAR_ERR

0
Detect parity error: When the North Bridge detects a
PCI parity error, this bit will be set to 1. Reset this bit by
writing a 1.

0

Table 3.43 Revision ID Register (RID)
Bit

Name

Function

Def.

Revision ID Register (RID) - Configuration Index 08H
7:0

REVISION_ID

Revision ID number. These bits are hard wired.

00H

Table 3.44 Class Register (CLASS)
Bit

Name

Function

Def.

Class Register (CLASS) - Configuration Index 09H
31:8

CLASS_CODE

ZFx86 Data Book 1.0 Rev D

Class Code. These bits are hard-wired.

060000H

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ZFx86 Data Book 1.0 Rev D

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4
4. South Bridge
4.1. South Bridge Module
The South Bridge module is an enhanced
PCI-to-ISA bridge module that provides
AT/ISA functionality. The module also contains
a bus mastering IDE controller for support of
up to four ATA-compliant devices. A two-port
Universal Serial Bus (USB) host controller
provides high speed, Plug & Play expansion
for a variety of new consumer peripheral
devices.

4.1.1. South Bridge Features
4.1.1.1. Front-PCI Interface
• PCI protocol for transfers on Front-PCI
• Up to 33 MHz operation
• Point-to-point only connection to North
Bridge enables higher bandwidth
• Uses non-preemptable arbiter connection
to North Bridge
• Subtractive decode handled internally in
conjunction with back-side PCI bus
• Front-PCI signals do not include SERR#
and PERR#

4.1.1.2. PCI Interface
• Off chip “back-side” PCI interface

• Non-supported modes:
- Devices internal to South Bridge (that is,
IDE, USB, ISA, etc.) cannot master to
memory on back-side PCI bus
- Legacy DMA not supported to memory
located on back-side PCI bus
- South Bridge bit-buckets subtractively
decoded I/O cycles originating from backside PCI bus

4.1.1.3. Bus Mastering IDE Controller
• One channel with support for up to two
IDE devices
• Second IDE channel for two more devices
off GPIO
• Independent timing for master and slave
devices
• PCI bus master burst reads and writes
• Ultra DMA (ATA-4) support
• Multiword DMA support
• Programmed I/O (PIO) Modes 0-4 support

4.1.1.4. Universal Serial Bus
• Two independent USB interfaces
• USB 1.1 specification compliant

• PCI 2.1 compliant

• Open Host Controller Interface (OpenHCI)
1.0 specification compliant

• Up to 33 MHz operation

• Second generation proven core design

• Internal PCI master for IDE and USB
controllers

• Overcurrent and power control support

• Subtractive agent for unclaimed transactions
• Supports PCI initiator-to-Front-PCI
• PCI-to-ISA interrupt mapper/translator

• PCI bus master burst reads and writes

4.1.1.5. Integrated SuperI/O
• Floppy disk controller
• Two standard serial ports fully compatible
with 16550A and 16450
• Infrared communication port

ZFx86 Data Book 1.0 Rev D

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4
• Parallel Port: Extended Capabilities Port
(ECP) that is IEEE 1284 compliant,
including level 2
• Real-time clock compatible with DS1287,
MC146818, and CP87911
• 8042 keyboard controller
• ACCESS.bus interface (compatible with
the physical layer of SMBus and I2C)

4.1.1.6. AT Compatibility

4.2. Architecture
The South Bridge architecture provides the
internal functional blocks shown in Figure 4-1
"Internal Block Diagram".
• Front-PCI interface / Back-side PCI bus
• PCI configuration registers
• IDE controller (UDMA-33)
• USB controller

• 8259A-equivalent interrupt controllers

• Integrated SuperI/O

• 8254-equivalent timer

• ISA bus interface

• 8237-equivalent DMA controllers

• AT compatibility logic

• Port A, B, and NMI logic

• Power management

• Positive decode for AT I/O space

• GPIOs

4.1.1.7. ISA Interface

• ZF Logic

• Boot ROM and keyboard chip select
• Extended ROM to 16 MB
• Two general purpose chip selects
• NAND Flash support

4.1.1.8. Power Management
• Automated CPU Suspend modulation
• I/O Traps and Idle Timers for peripheral
power management
• Software SMI and Stop Clock for APM
support
• Keyboard and mouse activity detect for
screen wake-up

4.1.1.9. GPIOs
• Eight GPIOs: All have the capability to
generate Power Management Events
(PMEs)

ZFx86 Data Book 1.0 Rev D

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4
Front-PCI

33-66 MHz
UDMA33

Back-PCI

FXBus
PCI Interface

IDE

GPIOs
GPIOs

33 MHz

Configuration
Registers

USB
XBus
USB
Legacy
(ISA/PIC/PIT/DMA)

PW
PM

Floppy/Parallel/Serial/
IR/RTC/Access Bus/
Fan CTRL/KBD-Mouse/
Wake-Up

ZF
Logic
ISA

SIO

Figure 4-1 Internal Block Diagram

4.2.1. Front-side PCI / Back-Side PCI Bus
The South Bridge provides a PCI bus interface
that is both a slave for PCI cycles initiated by
the North Bridge or other PCI master devices,
and a non-preemptable master for DMA
transfer cycles. The module is also a standard
PCI master for the IDE controller. The South
Bridge supports positive decode for configurable memory and I/O regions, and implements a subtractive decode option for
unclaimed PCI accesses. The South Bridge
also generates address and data parity, and
performs parity checking. The arbiter for the
Front-PCI interface is located in North Bridge.

The main objective of the Front-PCI interface
is two-fold:
• Provide a fast PCI compliant internal bus
between the North and South Bridges.
• Enable a higher bandwidth interface to
system memory for high bandwidth
devices.
To achieve these goals, the following
describes how the Front-PCI interface
manages PCI cycles.

Configuration registers are accessed through
the PCI interface using the PCI Bus Type 1
configuration mechanism as described in the
PCI 2.1 Specification.

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4
4.2.1.1. North Bridge Mastered Cycles
on Front-PCI

this bus. Support for up to three bus masters
is provided. The arbiter is in the South Bridge.

All North Bridge initiated cycles are acted
upon by the South Bridge following the normal
PCI rules for active/subtractive decode using
DEVSEL. Memory writes are automatically
posted. Reads will be retried if they are not
destined for actively decoded devices on the
FXBus or the XBus. This means that a read to
back-side PCI or ISA devices are automatically treated as a delayed transaction through
the PCI retry mechanism. This allows the high
bandwidth devices access to the Front-PCI
interface while the response from a possibly
slow device can be accumulated.

4.2.2. IDE Controller

All types of configuration cycles are supported
and handled appropriately according to the
PCI specification.

The South Bridge integrates a PCI bus
mastering ATA-4 compatible IDE controller.
The IDE controller supports Ultra DMA, Multiword DMA, and Programmed I/O (PIO)
modes. The controller contains two channels
with two devices supported per channel, for a
total of up to four devices. To enable the
second channel, GPIO pins must be reconfigured. Program the data-transfer speed for
each device independently. This allows highspeed IDE peripherals to coexist on the same
channel as lower speed devices. Faster
devices must be ATA-4 compatible.

4.2.1.2. Back-Side PCI Master Cycles to
Front PCI

IDE_DATA[15:0]

Memory cycles mastered by external PCI
devices on the back-side PCI bus are actively
taken if they are within the system memory
address range. Memory cycles to system
memory are forwarded to the Front-PCI interface. Burst transfers are stopped on every
cache line boundary to allow efficient buffering
in the Front-PCI interface block.

CS0#, DREQ0,
DMACK0#, IORDY0,
DIOR0#, DIOW0#

I/O and configuration cycles mastered by
external back-side PCI devices which are
subtractively decoded by the South Bridge will
not be handled. They will be discarded.

4.2.1.3. South Bridge Internal or ISA
Master Cycles to Front PCI
Only memory cycles (not I/O cycles) are
supported by the internal ISA or legacy DMA
masters. These memory cycles are always
forwarded to the Front-PCI interface.

4.2.1.4. Back-Side PCI Bus
The Back-Side PCI bus is a fully-compliant 5V
tolerant PCI bus. PCI slots are connected to

ZFx86 Data Book 1.0 Rev D

IDE_ADDR[2:0]

Primary
Channel

IRQ14

Secondary
Channel

IRQ15

IDE_RST#

CS1#, DREQ1,
DMACK1#, IORDY1,
DIOR1#, DIOW1#

Figure 4-2 IDE Channel Connections

4.2.3. Universal Serial Bus
The South Bridge provides two complete,
independent USB ports. Each port contains a
Data “–” and a Data “+” pin.
The USB ports are Open Host Controller Interface (OpenHCI) version 1.0 compliant. The
OpenHCI specification provides a registerlevel description for a host controller, as well

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4
as common industry hardware/software interface and drivers.
The USB host controller masters Front-PCI to
fetch setup and control information related to
OpenHCI. The USB host controller also
masters the PCI bus performing read and
write bursts to move, transmit, and receive
packet data to system memory.

ISA Specification Version 1.0a. All system
resources assigned to the functional blocks
(I/O address space, DMA channels, and IRQ
lines) are configured in, and managed by the
central configuration register set. In addition,
some function-specific parameters are configurable through this unit and distributed to the
functional blocks through special control
signals

4.2.4. Integrated SuperI/O

4.2.5. ISA Bus Interface

The integrated SuperI/O is based on 11 logical
devices (shown in Table 4.1), the host interface, and a configuration register set, all built
around a central, internal 8-bit bus.

Functional Block

The South Bridge provides an ISA bus interface for subtractive-decoded memory and I/O
cycles on PCI. The South Bridge is the default
subtractive decoding agent and forwards all
unclaimed memory and I/O cycles to the ISA
interface; however, the South Bridge may be
configured to ignore either I/O, memory, or all
unclaimed cycles (subtractive decode
disabled).

00h

Floppy Disk Controller (FDC)

DRAM is not supported on the ISA.

01h

Parallel Port (PP)

02h

Serial Port 2 (SP2)

Table 4.1 Logical Devices
LDN (Logical
Device
Number)

03h

Serial Port 1 (SP1)

04h

System Wake-Up Control (SWC)

05h

Keyboard and Mouse Controller
(KBC) — Mouse interface

06h

Keyboard and Mouse Controller
(KBC) — Keyboard interface

07h

Infrared Communication Port
(IRCP)

08h

ACCESS.Bus (ACB)

09h

Reserved

0Ah

Real Time Clock (RTC)

When you disable the ZF-Logic, the ISA interface of the South Bridge remaps pin functions
to include the followings signals in addition to
the signals used for an ISA interface (chip
pin):
• IOCS0# (mem_cs1), IOCS1# (mem_cs2)
- Asserted on I/O read/write transactions
from/to a programmable address range.

• DOCCS# (mem_cs3)
- Asserted on memory read/write transactions
from/to an 8 KB programmable window.

• ROMCS# (mem_cs0)
The host interface serves as a bridge between
the external ISA interface and the internal bus.
It supports 8-bit I/O read, 8-bit I/O write, and
8-bit DMA transactions as defined in Personal
Computer Bus Standard P996.
The central configuration registers are structured as a subset of the Plug and Play Standard Registers, defined by Intel® and
Microsoft® in Appendix A of the Plug and Play

ZFx86 Data Book 1.0 Rev D

- Asserted on memory read/write to upper 16
MB of address space. Configurable via the
ROM Mask Register (F0 Index 6Eh).

The Boot Flash supported by the South Bridge
can be up to 16 MB using the ROMCS#
signal.

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Forward all unclaimed memory and I/O cycles
to the Boot Flash and I/O Peripheral interface
when subtractive decode is enabled.
Assert the Disk-On-Chip chip-select signal
(DOCCS#) on any memory read or memory
write transaction from/to a predefined 8 KB
window in the address range 0C0000h0EFFFFh. Program the 8 KB window via the
DOCBASE register (F0 Index 78h). The
window’s base address must be on an 8 KB
address boundary.

4.2.5.1. AT Compatibility Logic
The South Bridge integrates:

• ISA bus master device support using
Cascade mode
When there is at least one active DMA request
(DRQ), DACK[7:0] indicates which DRQ is
granted. When there is no active DRQ,
DACK[7:0] are encoded with 00010000b,
which is an unused DACK.

4.2.5.3. Programmable Interval Timer
The South Bridge contains an 8254-equivalent
programmable interval timer. This device has
three timers, each with an input frequency of
1.193 MHz. Each timer can be individually
programmed to different modes.

• Two 8237-equivalent DMA controllers with
full 32-bit addressing

4.2.5.4. Programmable Interrupt
Controller

• Two 8259-equivalent interrupt controllers
providing 13 individually programmable
external interrupts

The South Bridge contains two 8259-equivalent programmable interrupt controllers, with
eight interrupt request lines each, for a total of
16 interrupts. The two controllers cascade
internally, and two of the interrupt request
inputs are connected to the internal circuitry.
This allows a total of 13 externally available
interrupt requests.

• An 8254-equivalent timer for refresh, timer,
and speaker logic
• NMI control and generation for PCI system
errors and all parity errors
• Support for standard AT keyboard controllers
• Positive decode for the AT I/O register
space
• Reset control

4.2.5.2. DMA Controller
The South Bridge supports the industry standard DMA architecture using two 8237compatible DMA controllers in cascaded
configuration. South Bridge supported DMA
functions include:

Individually select any South Bridge IRQ
signal as an edge- or level-sensitive type.
Route the four PCI interrupt signals internally
to any PIC IRQ.

4.2.6. Power Management
The South Bridge integrates advanced power
management features including idle timers for
common system peripherals, address trap
registers for programmable address ranges for
I/O or memory accesses, clock throttling with
automatic speedup for the CPU clock, and
software CPU stop clock.

• Standard seven-channel DMA support
• 32-bit address range support via high page
registers
• IOCHRDY extended cycles for compatible
timing transfers

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4
4.2.7. GPIO Interface
Up to eight GPIOs in the South Bridge provide
for system control. The ZFx86 contains
8 GPIO pins. The features include power
management event (PME) generation. This
means that any of the 8 GPIO pins set in input
mode can be used to wake up the processor.
That is, each GPIO pin can be programmed to
generate an SMI or SCI. The features of the
GPIO pins include the following:
• PME Debounce Enable — Enables or
disables IRQ debounce (debounce
period = 16 ms):
• PME Polarity — Selects the signal polarity
of the signal that issues a PME from the
corresponding GPIO pin (falling/low or
rising/high)
• PME Edge/Level Select — Selects the
signal type (edge or level) that issues a
PME from the corresponding GPIO pin.

• Pull-Up Control — Enables/disables the
internal pull-up capability of the corresponding GPIO pin. It supports open-drain
output signals with internal pull-ups and
TTL input signals.
• Output Type — Controls the output buffer
type (open-drain or push-pull) of the corresponding GPIO pin.
• Output Enable — Indicates the GPIO pin
output state. It has no effect on input.
Note: To clear the GPIO PME source,
complete these two items: (1) write a
“1” to the source bit in the GPIO Status
Register (F0BAR0+0Ch), and (2)
perform a read to that same register.
For more information, see Table 4.31
on page 230.

4.2.8. ZF-Logic
See Chapter 5. "ZF-Logic and Clocking" on
page 403.

• Lock — This bit locks the corresponding
GPIO pin. Once set to 1 by software, it can
only be cleared to 0 by system reset or
power-off.

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4.3. Signal Descriptions

PCI Interface

IDE
Interface

IDE (2x)
Controller

PCI
Bridge

USB
Controller

USB
Interface

Internal X Bus / ISA Bus
Interrupt &
DMA
Interface

Legacy: PIC,
DMA & PIT

GPIO
Interface

Power Man &
GPIO

Parallel
Interface

IEEE 1294
Controller

Key & Mouse
Controller

Keyboard
Mouse
Interface

Floppy Disk
Controller

Floppy
Disk
Interface

I2C Bus
Controller

I2 C
Interface

Access Bus

Serial &
IR
Interface

Two 16550
UARTS & IR

Real-time
Clock

ISA Interface
Figure 4-3 South Bridge Block Diagram

ZFx86 Data Book 1.0 Rev D

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4
4.3.1. System Interface Signals
Table 4.2 System Interface Signals
Signal Name
MEM_CS[0]

POR_N

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

B04

O
(8mA)

---

I
smt

---

C19

Description
ROM Chip Select
ROMCS# is the enable pin for the BIOS ROM and is
asserted for ISA memory accesses that are in the BIOS
address range. ROM size selection is made via F0 Index
52h[2]. This is part of the ZF-Logic described in 5.3. "ISA
Memory Mapper for Flash/SRAM" on page 410.
POR_N
POR# is the system reset signal generated from the
power supply to indicate that the system should be reset.

Table 4.3 Clock and Crystal Interface Signals
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

CLK_14MHZ

AF16

I

---

Description
14MHz Clock
This buffered 14.31818MHz input is used for the ISA bus
OSC. This signal is derived internally if the RTC is
enabled.

CLK_48MHZ

AE15

I

---

48MHz Clock
This input connects to an external 48MHz clock source
and is used by the SIO and USB.

KHZ32_C

AE01

I

---

32KHz Crystal Oscillator Connection
X1C and X2C are used with a capacitor and resistor to
create a 32KHz oscillator connection.

KHZZ32

AF01

I

---

32KHz Clock Connection
If a 32KHz crystal is not used in the system design, this
signal can be directly connected to a 32KHz external
clock.

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4
Table 4.4 CPU Interface Signals
Signal Name
CPU_RST

INTR

IRQ13

FERR#

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

Description

Internal
Pin

O
(8mA)

---

CPU Reset

Internal
Pin

O
(4mA)

---

Internal
Pin

I

Internal
Pin

CPU_RST resets the CPU and is asserted for
approximately 100µs after the negation of POR.
CPU Interrupt Request
INTR is the level output from the integrated 8259 PICs
and is asserted if an unmasked interrupt request (IRQn) is
sampled active.
F0 Index
53h[1] = 1

Interrupt Request 13/Floating Point Error Interrupt

F0 Index
53h[1] = 0

Floating Point Error Interrupt

IRQ13 is the input from floating point unit indicating that
an error was detected and that INTR should be asserted.

FERR# is an input from a processor that supports the
FERR# signal. It indicates that a floating point error was
detected and that IGNNE# should be asserted.
In order for the above event to occur, pin E11 must be
programmed to function as:
IGNNE# (F0 Index 4Ah[3] = 0).
Note that the IGNNE# (pin E11) is only available in the
456 PBGA.

SMI#

Internal
Pin

I/O
(4mA)

---

System Management Interrupt
SMI# is a level-sensitive interrupt to the CPU that can be
configured to assert on a number of different system
events. After an SMI# assertion, System Management
Mode (SMM) is entered, and program execution begins at
the base of SMM address space.
Once asserted, SMI# remains active until the SMI source
is cleared.

NMI

Internal
Pin

SUSPA#

O
(8mA)

---

I

---

Non-Maskable Interrupt Request
Non-maskable Interrupt Request is an output that causes
the processor to suspend execution of the current
instruction stream and begin execution of an NMI interrupt
service routine.
CPU Suspend Acknowledge
SUSPA# is a level input from the processor. When
asserted it indicates the CPU is in Suspend mode as a
result of SUSP# assertion or execution of a HALT
instruction.

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4
Table 4.4 CPU Interface Signals (cont.)
Signal Name

Pin No.
(PU/PD)

SUSP#

Type
(Drive)

Function
Selection

O
(4mA)

---

Description
CPU Suspend
SUSP# asserted requests that the CPU enter Suspend
mode. The CPU then asserts SUSPA# to complete the
handshake, but only after executing a HALT instruction
and turning off the appropriate internal clocks. The
SUSP# pin is then deasserted by the South Bridge upon
detection of a pre-defined Speedup or Wakeup/Resume
event. If the SUSP#/SUSPA# handshake is configured as
a system 3 Volt Suspend, the deassertion of SUSP# will
be delayed to allow the system clock chip and the
processor’s internal clocks to stabilize.
The SUSP#/SUSPA# handshake can occur as a result of
a write to the Suspend Notebook Command Register (F0
Index AFh), or an expiration of the Suspend Modulation
OFF Count Register (F0 Index 94h) when Suspend
Modulation is enabled. Suspend Modulation is enabled
via F0 Index 96[0].

4.3.2. Back-Side PCI Interface Signals
Table 4.5 Back-Side PCI Bus Interface Signals
Signal Name
PCICLK_C

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

U25

I

---

Description
PCI Clock
An input clock signal to the backside PCI interface of the
South Bridge. It runs at the PCI clock frequency and is
used to drive most of the South Bridge circuitry.

PCI_RST_N

CLKRUN#

U26

not
supported

ZFx86 Data Book 1.0 Rev D

O
(14mA)

---

I/O
(PCI)

---

PCI Reset
PCI_RST# is the reset signal for the PCI bus. Asserted for
approximately 100µs after the negation of POR.
Clock Run
CLKRUN# is an I/O that follows the PCI 2.2 defined
protocol.

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Table 4.5 Back-Side PCI Bus Interface Signals (cont.)
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

AD[31:0]

0 = U24

I/O, t/s
(PCI)

---

1 = V26
2 = V24
3 = V25
4 = W26
5 = V23
6 = W25

Description
PCI Address/Data
AD[31:0] is a physical address during the first clock of a
PCI transaction. It is the data during subsequent clocks.
When the South Bridge is a PCI master, AD[31:0] are
outputs during the address and write data phases, and
are inputs during the read data phase of a transaction.
When the South Bridge is a PCI slave, AD[31:0] are
inputs during the address and write data phases, and are
outputs during the read data phase of a transaction.

7 = W24
8 = Y26
9 = Y25
10 = Y23
11 = Y24
12 = AA26
13 = AA25
14 = AA24
15 = AB26
16 = AB25
17 = AB24
18 = AC26
19 = AB23
20 = AC25
21 = AC24
22 = AD25
23 = AD26
24 = AE26
25 = AE25
26 = AD24
27 = AF26
28 = AF25
29 = AE24
30 = AD23
31 = AF24

ZFx86 Data Book 1.0 Rev D

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4
Table 4.5 Back-Side PCI Bus Interface Signals (cont.)
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

C/BE[3:0]_N

0 = T24

I/O, t/s
(PCI)

---

1 = T26

Description
PCI Bus Command and Byte Enables
During the address phase of a PCI transaction,
C/BE[3:0]# define the bus command. During the data
phase of a transaction, C/BE[3:0]# are the data byte
enables.

2 = T25
3 = R24

C/BE[3:0]# are outputs when the South Bridge is a PCI
master and are inputs when it is a PCI slave.
The command encoding and types are:
0000 = Interrupt Acknowledge
0001 = Special Cycle
0010 = I/O Read
0011 = I/O Write
0100 = Reserved
0101 = Reserved
0110 = Memory Read
0111 = Memory Write
1000 = Reserved
1001 = Reserved
1010 = Configuration Read
1011 = Configuration Write
1100 = Memory Read Multiple
1101 = Dual Address Cycle (Rsvd)
1110 = Memory Read Line
1111 = Memory Write and Invalidate
INT9#

D02

I

---

The South Bridge provides inputs for the optional “levelsensitive” PCI interrupts (also known in industry terms as
PIRQx#). These interrupts may be mapped to IRQs of the
internal 8259s using PCI Interrupt Steering Registers 1
and 2 (F0 Index 5Ch and 5Dh).

PCI_INT_A
INT10#

E04

PCI_INT_B
INT11#

D01

Optionally routed internally.

PCI_INT_C
INT12#

PCI Interrupt Pins

For detailed information about routing PCI interrupts using
the ZFx86 BIOS, refer to the “Routing ZFx86 PCI
Interrupts” document (P/N 9150-0015-00) on the ZF Micro
Solutions website: http://www.zfmicro.com

E03

PCI_INT_D
REQ1_N

N23

REQ0_N

M25

GNT1_N

M24

GNT0_N

L26

ZFx86 Data Book 1.0 Rev D

I

---

PCI Bus Requests
The South Bridge asserts REQ# in response to a DMA
request or ISA master request to gain ownership of the
PCI bus. The REQ# and GNT# signals are used to
arbitrate for the PCI bus.

O
(PCI)

---

PCI Bus Grants
GNT# is asserted by an arbiter that indicates to the South
Bridge that access to the PCI bus has been granted.

Page 177

4
Table 4.5 Back-Side PCI Bus Interface Signals (cont.)
Signal Name
FRAME_N

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

P24

I/O, t/s
(PCI)

---

Description
PCI Cycle Frame
FRAME# is asserted to indicate the start and duration of a
transaction. It is deasserted on the final data phase.
FRAME# is an input when the South Bridge is a PCI
slave.

IRDY_N

P25

I/O, t/s
(PCI)

---

PCI Initiator Ready
IRDY# is driven by the master to indicate valid data on a
write transaction, or that it is ready to receive data on a
read transaction.
When the South Bridge is a PCI slave, IRDY# is an input
that can delay the beginning of a write transaction or the
completion of a read transaction.
Wait cycles are inserted until both IRDY# and TRDY# are
asserted together.

TRDY_N

R26

I/O, t/s
(PCI)

---

PCI Target Ready
TRDY# is asserted by a PCI slave to indicate it is ready to
complete the current data transfer.
TRDY# is an input that indicates a PCI slave has driven
valid data on a read or a PCI slave is ready to accept data
from the South Bridge on a write.
TRDY# is an output that indicates the South Bridge has
placed valid data on AD[31:0] during a read or is ready to
accept the data from a PCI master on a write.
Wait cycles are inserted until both IRDY# and TRDY# are
asserted together.

STOP_N

P26

I/O, t/s
(PCI)

---

PCI Stop
As an input, STOP# indicates that a PCI slave wants to
terminate the current transfer. The transfer will either be
aborted or retried.
As an output, STOP# is asserted with TRDY# to indicate
a target disconnect, or without TRDY# to indicate a target
retry. The South Bridge will assert STOP# during any
cache line crossings if in single transfer DMA mode or if
busy.

LOCK_N

N25

I/O, t/s
(PCI)

---

PCI Lock
LOCK# indicates an atomic operation that may require
multiple transactions to complete.
If the South Bridge is currently the target of a LOCKed
transaction, any other PCI master request with the South
Bridge as the target will be forced to retry the transfer.
The South Bridge does not generate LOCKed
transactions.

ZFx86 Data Book 1.0 Rev D

Page 178

4
Table 4.5 Back-Side PCI Bus Interface Signals (cont.)
Signal Name
DEVSEL_N

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

R25

I/O, t/s
(PCI)

---

Description
PCI Device Select
DEVSEL# is asserted by a PCI slave, to indicate to a PCI
master and subtractive decoder that it is the target of the
current transaction.
As an input, DEVSEL# indicates a PCI slave has
responded to the current address.
As an output, DEVSEL# is asserted one cycle after the
assertion of FRAME#, and remains asserted to the end of
a transaction as the result of a positive decode. DEVSEL#
is asserted four cycles after the assertion of FRAME# if
the South Bridge is selected as the result of a subtractive
decode. The subtractive decode sample point can be
configured in F0 Index 41h[2:1]. These cycles are passed
to the ISA bus.

PAR

N26

I/O, t/s
(PCI)

---

PCI Parity
PAR is the parity signal driven to maintain even parity
across AD[31:0] and C/BE[3:0]#.
The South Bridge drives PAR one clock after the address
phase and one clock after each completed data phase of
write transactions as a PCI master. It also drives PAR one
clock after each completed data phase of read
transactions as a PCI slave.

PERR_N

N24

I/O, t/s
(PCI)

---

PCI Parity Error
PERR# is pulsed by a PCI device to indicate that a parity
error was detected. If a parity error was detected, PERR#
is asserted by a PCI slave during a write data phase and
by a PCI master during a read data phase.
When the South Bridge is a PCI master, PERR# is an
output during read transfers and an input during write
transfers. When the South Bridge is a PCI slave, PERR#
is an input during read transfers and an output during
write transfers.
Parity detection is enabled through F0 Index 04h[6]. An
NMI is generated if I/O Port 061h[2] is set. PERR# can
assert SERR# if F0 Index 40h[1] is set.

ZFx86 Data Book 1.0 Rev D

Page 179

4
Table 4.5 Back-Side PCI Bus Interface Signals (cont.)
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

M26

I/O, OD
(PCI)

---

SERR_N

Description
PCI System Error
SERR# is pulsed by a PCI device to indicate an address
parity error, data parity error on a special cycle command,
or other fatal system errors.
SERR# is an open drain output reporting an error
condition, and an input indicating that the South Bridge
should generate an NMI. As an input, SERR# is asserted
for a single clock by the slave reporting the error.
System error detection is enabled with F0 Index 04h[8].
An NMI is generated if I/O Port 061h[2] is set. PERR# can
assert SERR# if F0 Index 40h[1] is set.

Table 4.6 IDE Interface Signals
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

IDE_CS0_N

AE20

---

IDE_CS1_N

AF21

O
(IDE)

IDE_DIOR0_N

AC20

---

IDE_DIOR1_N

AD11

O
(IDE)

O
(IDE)

---

IDE_DIOW1_N

AF11

GPIO[2]

AC22

IDE_DMA_ACK1_N

AE11

---

GPIO[1]

AE23

IDE_DMA_REQ1_N

AE10

I

---

GPIO[5]

AD22

IDE_IORDY1

AD10

GPIO[6]a

ZFx86 Data Book 1.0 Rev D

DMA Request Channels 0 and 1
The DREQ is used to request a DMA transfer from the
South Bridge. The direction of the transfers is
determined by the IDE_IOR/IOW signals.

a

IDE_IORDY0

DMA Acknowledge Channels 0 and 1
The DMACK# acknowledges the DREQ request to
initiate DMA transfers.

a

IDE_DMA_REQ0_N

IDE I/O Write for Channels 0 and 1
IDE_IOW0# is the write signal for Channel 0 and
IDE_IOW1# is the read signal for Channel 1. Each signal
is asserted on write accesses to corresponding the IDE
port addresses.

a

IDE_DMA_ACK0_N

IDE I/O Read for Channels 0 and 1
IDE_IOR0# is the read signal for Channel 0 and
IDE_IOR1# is the read signal for Channel 1. Each signal
is asserted on read accesses to the corresponding IDE
port addresses.

GPIO[3]

AE21

IDE Chip Select for Channels 0 and 1
The chip select signals are used to select the command
block registers in an IDE device.

a

IDE_DIOW0_N

Description

I

---

I/O Ready Channels 0 and 1
When deasserted, these signals extend the transfer
cycle of any host register access when the device is not
ready to respond to the data transfer request.

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4
Table 4.6 IDE Interface Signals (cont.)
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

IDE_ADDR[0]

AD21

---

IDE_ADDR[1]

AF22

O
(IDE)

IDE_ADDR[2]

AE22
I/O
(IDE)

---

O
(IDE)

---

I

---

IDE_DATA[15:0]

0 = AD20
1 = AF20

Description
IDE Address Bits
These address bits are used to access a register or data
port in a device on the IDE bus.
IDE Data Lines
IDE_DATA[15:0] transfers data to/from the IDE devices.

2 = AD19
3 = AE19
4 = AF19
5 = AD18
6 = AC18
7 = AE18
8 = AF18
9 = AE17
10 = AD17
11 = AF17
12 = AC16
13 = AD16
14 = AE16
15 = AD15
IDE_RST_N

AF23

IRQ14

E02

IDE Reset
This signal resets all devices attached to the IDE
interface.
Interrupt Request 14
Normally connected to the primary IDE channel.

IRQ15

E01

I

---

Interrupt Request 15
Normally connected to the secondary IDE channel.

a. See Table 4.8 "GPIO Interface Signals"

ZFx86 Data Book 1.0 Rev D

Page 181

4
Table 4.7 USB Interface Signals
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

Function
Selection

POWER_EN

AE12

O
(4mA)

---

I

---

OVER_CUR1#

AD13

OVER_CUR2#

AF12

PORT1_P

AE13

PORT1_M

PORT2_P

PORT2_M

AF13

AF14

AE14

Description
Power Enable
Enables the power to a bus-powered USB hub.
Over Current
Indicates the USB hub detected an overcurrent on the USB.

I/O
(USB)

---

I/O
(USB)

---

I/O
(USB)

---

I/O
(USB)

---

USB Port 1 Data Positive
The Universal Serial Bus Data Positive for port 1.
USB Port 1 Data Minus
The Universal Serial Bus Data Minus for port 1.
USB Port 2 Data Positive
The Universal Serial Bus Data Positive for port 2.
USB Port 2 Data Minus
The Universal Serial Bus Data Minus for port 2.

Table 4.8 GPIO Interface Signals
Pin No.
(PU/PD)

Type
(Drive)

gpio[0]

AD12

I/O

GPIO/0 (optional 32KHz out). Reference IO_CLK32K_OEca

gpio[1]

AE11

I/O

GPIO/1 (optional 2nd IDE IDE_DMA_ACK1_N)b

gpio[2]

AF11

I/O

GPIO/2 (optional 2nd IDE IDE_DIOW1_N)b

gpio[3]

AD11

I/O

GPIO/3 (optional 2nd IDE IDE_DIOR1_N)b

gpio[4]

AF10

I/O

GPIO/4 (can set GPIO[0] to 32 Khz Out)c

gpio[5]

AE10

I/O

GPIO/5 (optional 2nd IDE IDE_DMA_REQ1_N)b

gpio[6]

AD10

I/O

GPIO/6 (optional 2nd IDE IDE_IORDY1)b

gpio[7]

AF09

I/O

GPIO/7

Signal Name

Description

a. GPIO[0] can also be Chip Select for External BUR. See Table 5.42 "Composite BootStrap Register Map" on page 438.
b. See ‘IO_IDE_ON_GPIO — Drive IDE channel 2 onto gpio. Must also have gpio conditioned to correct direction corresponding to IDE pin functionality.’ on page 245.
c. See Figure 5-9 "System Clocking and Control" on page 443

ZFx86 Data Book 1.0 Rev D

Page 182

4
Example: Setting the ISA Bus Clock
Although the only legal values of the ISA Bus
Clock are 2 and 3, this example steps through
all eight values. It illustrates how to access the
South Bridge configuration registers. The

1
2
3
4
5
6
7
8

“outpd” on line 4 writes a 32-bit value to the
port address specified.
For the pattern output to CF8, see “PCI
Configuration Space and Access Methods” on
page 196, and “PCI Configuration Address
Register (0CF8h)” on page 196

printf ("\r\n\n\n Step Through ISA Bus Clock Divisors\r\n");
for (uii = 0; uii < 8; uii++)
{
outpd (0xCF8, 0x80009050);
outp (0xCFC, ((inp (0xCFC) & 0xF0) | uii));
printf ("Divisor is Now %i - Press Key to Step", uii);
getch();
}

Table 4.9 Full ISA Interface
Signal Name
ISACLK_N

Pin No.
(PU/PD)

Type
(Drive)

ACO2

O
(14mA)

Function
Selection
F0 Index
4Ah[4] = 0

Description
ISA Bus Clock
ISACLK is derived from PCICLK and is typically
programmed for 8.33MHz.
F0 Index 50h[2:0] is used to program the ISA clock
divisor. These bits determine the divisor of the PCI
clock used to make the 8.33MHz ISA bus clock. If F0
Index 50h[2:0] is set to:
010 = Divide by three (PCI clock = 25MHz)
011 = Divide by four (PCI clock = 33MHz)
All other values are invalid and can produce
unexpected results. See Table 4.30 "F0 Index xxh:
PCI Header and Bridge Configuration Registers".

MASTER_N

TC

AEN

BALE

Not Supported

I

A12

C13

AD2

ZFx86 Data Book 1.0 Rev D

F0 Index
4Ah[4] = 0

Master

O
(8mA)

F0 Index
4Ah[4] = 0

Terminal Count

O
(8mA)

F0 Index
4Ah[4] = 0

Address Enable

O
(8mA)

F0 Index
4Ah[4] = 0

Buffered Address Latch Enable

The MASTER# input asserted indicates an ISA bus
master is driving the ISA bus and that it may access
any device on the system board.

TC signals the final data transfer of a DMA transfer.
TC is accepted only when a DACK signal is active.

AEN asserted indicates to ISA memory devices that
a valid address for a DMA transfer is present on
SA[23:0], and for I/O devices to ignore this address
and any data on the ISA bus.

BALE indicates when SA[23:0] and SBHE# are valid
and may be latched. For DMA transfers, BALE
remains asserted until the transfer is complete.

Page 183

4
Table 4.9 Full ISA Interface (cont.)
Pin No.
(PU/PD)

Type
(Drive)

SD[15:0]

0 = AC07
1 = AD07
2 = AF06
3 = AE06
4 = AD06
5 = AF06
6 = AE05
7 = AD05
8 = AF04
9 = AC05
10 = AEO4
11 = AD04
12 = AF03
13 = AE03
14 = AF02
15 = AE02

I/O
(8mA)

F0 Index
4Ah[5] = 0

System Data Bus Bits 15-0

SA[23:0]

0 = AC01
1 = AB02
2 = AB01
3 = AA03
4 = AA02
5 = Y04
6 = AA01
7 = Y02
8 = Y03
9 = Y01
10 = W03
11 = W02
12 = W01
13 = V03
14 = V04
15 = V02
16 = V01
17 = U02
18 = U03
19 = U01
20 = T04
21 = T03
22 = T02
23 = R03

I/O
(8mA)

F0 Index
4Ah[5] = 0

System Address Bus Lines 23-20

Internal

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 1

Signal Name

IRQ1

ZFx86 Data Book 1.0 Rev D

Function
Selection

Description

The SA[23:20] signals provide the address for
memory and I/O accesses on the ISA bus. The
addresses are outputs when the South Bridge owns
the ISA bus and are inputs when an external ISA
master owns the ISA bus.

Keyboard / Mouse

Page 184

4
Table 4.9 Full ISA Interface (cont.)
Pin No.
(PU/PD)

Type
(Drive)

IRQ3

B02

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 3

IRQ4

C01

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 4

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 5

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 6

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 7

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 8

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 9 / PCI Int A

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 10 / PCI Int B

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 11 / PCI Int C

I/O
(4mA)

F0 Index
47h[0] = 0

Interrupt Request 12 / PCI Int D

Signal Name

IRQ5

IRQ6

IRQ7

IRQ8#

IRQ9,

C02

Internal

D03

Internal

D02

PCI_INT_A
IRQ10,

E04

PCI_INT_B

IRQ11,

D01

PCI_INT_C
IRQ12,

E03

PCI_INT_D
IRQ14

E02

I

Function
Selection

---

Description

Refer to IRQ1 signal description.

Refer to IRQ1 signal description.

Refer to IRQ1 signal description.

Refer to IRQ1 signal description.

Refer to IRQ1 signal description.

RTC

Refer to IRQ1 signal description.

Refer to IRQ1 signal description.

Refer to IRQ1 signal description.

PCI Int D
Interrupt Request 14
Normally connected to the primary IDE channel.

IRQ15

E01

I

---

Interrupt Request 15
Normally connected to the secondary IDE channel.

DRQ1

B14

DRQ5

B13

DRQ3

Internal

DRQ6

Internal

ZFx86 Data Book 1.0 Rev D

I

F0 Index
4Ah[4] = 0

DMA Requests
DRQ inputs are asserted by ISA DMA devices to
request a DMA transfer. The request must remain
asserted until the corresponding DACK is asserted.
IDE DMA does not use ISA DMA.

I

F0 Index
47h[0] = 0

DMA Request 3

F0 Index
47h[0] = 0

DMA Request 6

I

The DRQ is used to request DMA service from the
DMA controller.

The DRQ is used to request DMA service from
the DMA controller.

Page 185

4
Table 4.9 Full ISA Interface (cont.)
Signal Name

Pin No.
(PU/PD)

Type
(Drive)

DRQ7

Internal

I

DACK0

Internal

Function
Selection

Description

F0 Index
47h[0] = 0

DMA Request 7

O
(8mA)

F0 Index
47h[0] = 0

DMA Acknowledge 0

The DRQ is used to request DMA service from the
DMA controller.

IDE DMA does not use ISA DMA.

DACK1_N

A14

O
(8mA)

F0 Index
47h[0] = 0

DMA Acknowledge 1

DACK5_N

A13

O
(8mA)

F0 Index
47h[0] = 0

DMA Acknowledge 5

AB04

I

F0 Index
47h[0] = 0

Zero Wait States

F0 Index
47h[0] = 0

System Bus High Enable

ZWS_N

SBHE_N

AC03

I/O
(8mA)

ZWS_N asserted indicates that an ISA 8- or 16-bit
memory slave can shorten the current cycle. The
South Bridge samples this signal in the phase after
BALE is asserted. If asserted, it shortens 8-bit cycles
to three ISACLKs and 16-bit cycles to two ISACLKs.

The South Bridge or ISA master asserts SBHE_N to
indicate that SD[15:8] will be used to transfer a byte
at an odd address.
SBHE_N is an output during non-ISA master DMA
operations. It is driven as the inversion of AD0 during
8-bit DMA cycles. It is forced low for all 16-bit DMA
cycles.
SBHE_N is an input during ISA master operations.

IOCS16_N

MEMCS16_N

SMEMR_N

AF07

AE07

AE08

ZFx86 Data Book 1.0 Rev D

I

F0 Index
47h[0] = 0

I/O Chip Select 16

I/O
(8mA)

F0 Index
47h[0] = 0

Memory Chip Select 16

O
(8mA)

F0 Index
47h[0] = 0

System Memory Read

IOCS16_N is asserted by 16-bit ISA I/O devices
based on an asynchronous decode of SA[15:0] to
indicate that SD[15:0] may be used to transfer data
(8-bit ISA I/O devices use SD[7:0]).

MEMCS_N is asserted by 16-bit ISA memory
devices based on an asynchronous decode of
SA[23:17] to indicate that SD[15:0] may be used to
transfer data (8-bit ISA memory devices use
SD[7:0]).

SMEMR_N is asserted for memory read accesses
below 1MB. It enables 16-bit memory slaves to
decode the memory address on SA[23:0].

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4
Table 4.9 Full ISA Interface (cont.)
Signal Name
SMEMW_N

MR

Pin No.
(PU/PD)

Type
(Drive)

AD08

O
(8mA)

Function
Selection
F0 Index
47h[0] = 0

B20

Description
System Memory Write
SMEMW_N is asserted for all memory write
accesses below 1MB. It enables 16-bit memory
slaves to decode the memory address on
SA[23:0].
Master Reset
An active high MR input signal resets the device with
its default settings.

MEMW_N

MEMR_N

IOR_N

IOW_N

IOCHRDY

AC09

AF08

AD09

AE09

AD01

I/O
(8mA)

---

I/O
(8mA)

---

I/O
(8mA)

---

I/O
(8mA)

---

I/O, OD
(8mA)

---

Memory Write
MEMW_N is asserted for all memory write accesses.
Memory Read
MEMR_N is asserted for all memory read accesses.
I/O Read
IOR_N is asserted to request an ISA I/O slave to
drive data onto the data bus.
I/O Write
IOW_N is asserted to request an ISA I/O slave to
accept data from the data bus.
I/O Channel Ready
IOCHRDY deasserted indicates that an ISA slave
requires additional wait states.
When the South Bridge is an ISA slave, IOCHRDY is
an output indicating additional wait states are
required.

ZFx86 Data Book 1.0 Rev D

Page 187

4
4.3.3. Integrated SuperI/O Interface Signals

IRTX

Infrared
Communication
Port

IRSL3-0
IRRX2,1

Serial
Port 1

Parallel
Port
Configuration
and Control
Registers

RDATA
WDATA

Serial
Port 2

RX1
TX1
RTS1
DTR1
CTS1
DSR1
DCD1
RI1
RX2 [A07]
TX2 [B07]
RTS2
DTR2
CTS2
DSR2
DCD2
RI2

Keyboard
and
Mouse
Controller

KBLOCK
KBCLK
KBDAT
MDAT
MCLK

ACCESS
Bus

SCL

DSKCHG
WP

ZFx86 Data Book 1.0 Rev D

VBAT

VCC_IO

X2C

X1C/X1

ALARM

Real-Time Clock (RTC)

Host
Interface
System
Wake-Up

SDA
TC
DACK0-3
DRQ0-3
IRQ1-12,14-15
IOCHRDY
ZWS
IOWR
IORD
AEN

SIOCFG
CLKIN
MR
D7-0
A15-0

TRK0
INDEX

PWUREQ

FDC

STEP

RING
S_GPWI01
CHASI
S_GPWI02
CHASO

DIR

Internal Bus

HDSEL

Control Signals

WGATE

Page 188

4
Table 4.10 Access Bus
Signal
Name
SCL_C

Pin No.
Type
Power
Buffer Type
(PU/PD) (Drive)
Well
B12

INSM/OD6

I/O

Description

VDD

ACCESS.bus Clock Signal
An internal pull-up is optional, depending upon the
ACCESS.bus configuration register.

SDA

D13

INSM/OD6

I/O

VDD

ACCESS.bus Data Signal
An internal pull-up is optional, depending upon the
ACCESS.bus configuration register.

Table 4.11 Clock
Signal
Name
CLKIN

Pin No. Type
(PU/PD) (Drive)
Internal

Buffer
Type

Power
Well

INT

VDD

I

Description
Clock In
A 48MHz clock input.

Table 4.12 Floppy Disk Controller
Signal
Name
DIR_N

DR0_N

DSKCHG_N

Pin No.
(PU/PD)

Type
(Drive)

Buffer
Type

Power
Well

G03

O

OD14O14/14

VDD

OD14O14/14

VDD

INT

VDD

F01

O

J02

I

Description
Direction
Determines the direction of the Floppy Disk Drive (FDD)
head movement (active = step in, inactive = step out) during
a seek operation. During reads or writes, DIR is inactive.
Drive Select 0
Decoded drive select output signal. DR0 is controlled by
Digital Output Register (DOR) bit 0.
Disk Change
Indicates if the drive door has been opened. The state of this
pin is stored in the Digital Input Register (DIR). This pin can
also be configured as the RGATE data separator diagnostic
input signal via the MODE command.

HDSEL

INDEX_N

H01

O

F03

I

OD14,
O14/14

VDD

INT

VDD

Head Select
Determines which side of the FDD is accessed. Active low
selects side 1, inactive selects side 0.
Index
Indicates the beginning of an FDD track.

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4
Table 4.12 Floppy Disk Controller (cont.)
Signal
Name
MTR0_N

Pin No.
(PU/PD)

Type
(Drive)

Buffer
Type

Power
Well

F02

O

OD14,
O14/14

VDD

Description
Motor Select 0
Active low, motor enable line for drive 0, controlled by bits
D7-4 of the Digital Output Register (DOR).
This signal is not available on the PPM, assuming that the
external FDD is either drive 1 or 3.

RDATA_N

J04

I

INT

VDD

Read Data
Raw serial input data stream read from the FDD.

STEP_N

TRK0_N

G04

O

H03

I

OD14,
O14/14

VDD

INT

VDD

Step
Issues pulses to the disk drive at a software programmable
rate to move the head during a seek operation.
Track 0
Indicates to the controller that the head of the selected floppy
disk drive is at track 0.

WDATA_N

WGATE_N

WRPRT_N

G02

G01

O

O

H02

I

OD14,
O14/14

VDD

OD14,
O14/14

VDD

INT

VDD

Write Data
Carries out the write pre-compensated serial data that is
written to the selected floppy disk drive. Pre-compensation is
software selectable.
Write Gate
Enables the write circuitry of the selected disk drive. WGATE
is designed to prevent glitches during power up and power
down. This prevents writing to the disk when power is cycled.
Write Protected
Indicates that the disk in the selected drive is write protected.
A software programmable configuration bit (FDC
configuration at Index F0h, Logical Device 0) can force an
active write-protect indication to the FDC regardless of the
status of this pin.

Table 4.13 Keyboard and Mouse Controller (KBC)
Signal
Name
KBCLK

Pin No.
(PU/PD)

Type
(Drive)

Buffer
Type

C12

I/O

INTS/OD2

Power
Well

Description

VDD, Keyboard Clock
VCC_IO Transfers the keyboard clock between the SuperI/O chip and
the external keyboard using the PS/2 protocol.
Driven by the internal, inverted KBC P26 signal, and
connected internally to the T0 signal of the KBC. External pullup resistor to 5V required (for PS/2 compliance). The pin is
monitored for wake-up event detection. However, to enable
this activity during power off, it must be pulled up to Keyboard
and Mouse standby voltage.

ZFx86 Data Book 1.0 Rev D

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4
Table 4.13 Keyboard and Mouse Controller (KBC) (cont.)
Signal
Name
KBDAT

Pin No.
(PU/PD)

Type
(Drive)

Buffer
Type

A11

I/O

INTS/OD2

Power
Well

Description

VDD, Keyboard Data
VCC_IO Transfers the keyboard data between the SuperI/O chip and
the external keyboard using the PS/2 protocol.
Driven by the internal, inverted KBC P27 signal, and
connected internally to KBC P10. External pull-up resistor to
5V required (for PS/2 compliance). The pin is monitored for
wake-up event detection. To enable this activity, it must be
pulled up to Keyboard and Mouse standby voltage.

KBLOCK

B11

I

INTS

VDD

Keyboard Lock
P17 input.

MCLK_C

D11

I/O

INTS/OD2

VDD, Mouse Clock
VCC_IO Transfers the mouse clock between the SuperI/O chip and the
external keyboard using the PS/2 protocol.
Driven by the internal, inverted KBC P23 signal, and
connected internally to KBC’s T1. External pull-up resistor to
5V required (for PS/2 compliance). The pin is monitored for
wake-up event detection. To enable the activity, it must be
pulled up to Keyboard and Mouse standby voltage.

MDAT

C11

I/O

INTS/OD2

VDD, Mouse Data
VCC_IO Transfers the mouse data between the SuperI/O chip and the
external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P22 signal, and
is connected internally to KBC’s P11. External pull-up resistor
to 5V is required (for PS/2 compliance). The pin is monitored
for wake-up event detection. To enable the activity, it must be
pulled up to Keyboard and Mouse standby voltage.

ZFx86 Data Book 1.0 Rev D

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4
Table 4.14 Parallel Port
Signal
Name
ACK_N

Pin No.
(PU/PD)

Type
(Drive)

Buffer Type

Power
Well

K02

I

INT

VDD

Description
Acknowledge
Pulsed low by the printer to indicate that it has received data
from the Parallel Port.

AFD_N

L02

O

OD14,
O14/14

VDD

Automatic Feed - AFD
When low, instructs the printer to automatically feed a line
after printing each line. This pin is in TRI-STATE after a 0 is
loaded into the corresponding control register bit. An
external 4.7 KΩ pull-up resistor should be attached to this
pin.
Data Strobe (EPP) - DSTRB
Active low, used in EPP mode to denote a data cycle. When
the cycle is aborted, DSTRB becomes inactive (high).

BUSY

K03

I

INT

VDD

Busy
Set high by the printer when it cannot accept another
character.
Wait
In EPP mode, the Parallel Port device uses this active low
signal to extend its access cycle.

ERR_N

L01

I

INT

VDD

Error
Set active low by the printer when it detects an error.

INIT

PD[7:0]

L03

0 = P03

O

I/O

1 = P01
2 = P02

OD14,
O14/14

VDD

INT/
OD14,
O14/14

VDD

INT

VDD

Initialize
When low, initializes the printer. This signal is in TRI-STATE
after a 1 is loaded into the corresponding control register bit.
Use an external 4.7 KΩ pull-up resistor.
Parallel Port Data
Transfer data to and from the peripheral data bus and the
appropriate Parallel Port data register. These signals have a
high current drive capability.

3 = N01
4 = N02
5 = M01
6 = N03
7 = M02
PE

J01

I

Paper End
Set high by the printer when it is out of paper. This pin has
an internal weak pull-up or pull-down resistor.

SLCT

J03

I

INT

VDD

Select
Set active high by the printer when the printer is selected.

ZFx86 Data Book 1.0 Rev D

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4
Table 4.14 Parallel Port (cont.)
Signal
Name
SLIN_N

Pin No.
(PU/PD)

Type
(Drive)

K01

O

Buffer Type
OD14,
O14/14

Power
Well
VDD

Description
Select Input - SLIN
When low, selects the printer. This signal is in TRI-STATE
after a 0 is loaded into the corresponding control register bit.
Uses an external 4.7 KΩ pull-up resistor.
Address Strobe (EPP) - ASTRB
Active low, used in EPP mode to denote an address or data
cycle. When the cycle is aborted, ASTRB becomes inactive
(high).

STB_N

M03

O

OD14,
O14/14

VDD

Data Strobe - STB
When low, Indicates to the printer that valid data is available
at the printer port. This signal is in TRI-STATE after a 0 is
loaded into the corresponding control register bit. An
external 4.7 KΩ pull-up resistor should be employed.
Write Strobe - WRITE
Active low, used in EPP mode to denote an address or data
cycle. When the cycle is aborted, WRITE becomes inactive
(high).

Table 4.15 Power and Ground
Signal
Name
VBAT

Pin No. Type
(PU/PD) (Drive)
AD3

Buffer
Type

Power
Well

INULR

-

Description
Battery Power Supply
Provides battery back-up to the System Wake-Up Control
registers. The pin is connected to the internal logic through a
series resistor for UL protection.
Note: The ZFx86 contains no reverse polarity protection.

VDD

PWR

-

Main 3.3V Power Supply
See Pin description Table 8.4 on page 572.

GND

GND

-

Ground
See Table 8.4 on page 572

ZFx86 Data Book 1.0 Rev D

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4
Table 4.16 Serial Port 1 and Serial Port 2 (Shared with I/R Port)
Signal
Name

Pin No. Type
(PU/PD) (Drive)

CTS1_N
CTS2_N

1 = D09

DCD1_N
DCD2_N

1 = A10

DSR1_N

1 = C10

DSR2_N

2 = C08

DTR1_N,
BOUT1
DTR2_N,
BOUT2

I

Buffer
Type

Power
Well

INTS

VDD

Clear to Send
When low, indicates that the modem or other data transfer
device is ready to exchange data.

2 = A06
I

INTS

VDD

Data Carrier Detected
When low, indicate that the modem or other data transfer device
has detected the data carrier.

2 = B08

C09

Description

I

INTS

VDD

Data Set Ready
When low, indicate that the data transfer device, e.g., modem, is
ready to establish a communications link.

O

O8/8

VDD

Data Terminal Ready
When low, indicate to the modem or other data transfer device
that the Serial Port is ready to establish a communications link.
After system reset, these pins provides the DTR function, sets
these signals to inactive high, and loopback operation holds
them inactive.

D07

Baud Output
Provides the associated serial channel baud rate generator
output signal if test mode is selected, that is, bit 7 of the EXCR1
Register is set.
RI1_N
RI2_N

A08

RTS1_N
RTS2_N

A09

I

INTS

O

O8/8

B06

VDD,
Ring Indicators (Modem)
VCC_IO When low, indicates that a telephone ring signal has been
received by the modem. These pins may issue a wake-up event.
VDD

When low, indicates to the modem or other data transfer device
that the corresponding Serial Port is ready to exchange data. A
system reset sets these signals to inactive high, and loopback
operation holds them inactive.

C07

RX1
RX2

B10

TX1
TX2

B09

Request to Send

I

INTS

VDD

Serial Input
Receive composite serial data from the communications link
(peripheral device, modem, or other data transfer device).

A07
O

B07

ZFx86 Data Book 1.0 Rev D

O8/8

VDD

Serial Output
Send composite serial data to the communications link
(peripheral device, modem, or other data transfer device). The
SOUT2,1 signals are set active high after system reset.

Page 194

4
Table 4.17 Infrared Communication Port (Shared W/COM2)
Signal
Name
IRRX1

Pin No.
(PU/PD)

Type
(Drive)

Buffer
Type

C06

I

Generic 2

Power
Well

Description

VDD_IO IR Reception 1
Primary input to receive serial data from the IR transceiver
module.

IRSL0

C07

I/O

Generic 2

VDD_IO IR Select 0 - IRSL0
Input/Output to control the IR analog front end.

IRSL1

C08

I/O

Generic 2

VDD_IO IR Select 1 - IRSL1
Input/Output to control the IR analog front end.

IRSL2

B08

I/O

Generic 2

VDD_IO IR Select 2 - IRSL2
Input/Output to control the IR analog front end.

IRSL3

A06

I

Generic 2

VDD_IO IR Select 3 - IRSL3
Input to control the IR analog front end.

IRTX

A05

O

Generic 2

VDD_IO IR Transmit
IR serial output data.

4.4. Register Descriptions
The South Bridge module is a multi-function
device. Its register space can be broadly
divided into three categories in which specific
types of registers are located:
• Chipset Register Space (F0-F3)
• USB Controller Register Space (PCIUSB)
• ISA Legacy Register Space (I/O Port)
The Chipset and USB Controller Register
Spaces are accessed through the PCI interface using the PCI Type One Configuration
Mechanism.
The Chipset Register Space of the South
Bridge module is comprised of four separate
functions; each with its own register space
consisting of PCI header registers and configuration registers.

these registers to configure the PCI for the
device. Use the rest of the 256-byte region to
configure the device or function itself.
The USB Controller Register Space consists
of the standard PCI header registers. The
USB controller supports three ports and is
OpenHCI compliant.
The ISA Legacy I/O Register Space contains
all the legacy compatibility I/O ports that are
internal, trapped, shadowed, or snooped.
The remaining subsections of this chapter
contains the following:
• A brief discussion on how to access the
registers located in PCI Configuration
Space.
• Register summaries
• Bit formats for all registers

The PCI header is a 256-byte region used for
configuring a PCI device or function. The first
64 bytes are the same for all PCI devices and
are predefined by the PCI specification. Use

ZFx86 Data Book 1.0 Rev D

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4
4.4.1. PCI Configuration Space and Access Methods
Configuration cycles are generated from the
North Bridge. All configuration registers in the
South Bridge module are accessed through
the PCI interface using the PCI Configuration
Mechanism 1. This mechanism uses two
DWORD I/O locations at 0CF8h and 0CFCh.

the configuration register offset. On the
following cycle, a read or write to the Configuration Data Register (CDR) causes a PCI
configuration cycle to the South Bridge
module. Byte, word, or double word accesses
are allowed to the CDR at 0CFCh, 0CFDh,
0CFEh, or 0CFFh.

• 0CF8h references the Configuration
Address Register.

The South Bridge module has five PCI configuration register sets, one for each function
(F0-F3) and USB (PCIUSB). Base Address
Registers (BARx) in F0-F3 and PCIUSB set
the base addresses for additional I/O or
memory mapped configuration registers for
each respective function.

• 0CFCh references the Configuration Data
Register.
Note: The write to 0CF8h for configuration
cycles must be a 32 bit IO operation.
To access PCI configuration space, write the
Configuration Address (0CF8h) Register with
data that specifies the South Bridge module as
the device on PCI being accessed, along with

Table 4.18 shows the PCI Configuration
Address Register (0CF8h) and how to access
the PCI header registers.

Table 4.18 PCI Configuration Address Register (0CF8h)
31

30

24

23

16

15

11

10

8

7

2

1

0

Configuration
Space Mapping

RSVD

Bus Number

Device Number

Function

Index

Doubleword
00

1 (Enable)

000 000

0000 0000

xxxx x (Note)

xxx

xxxx xx

00 (Always)

Function 0 (F0): Bridge Configuration and GPIO Configuration Register Space
80h

0000 0000

1001 0

000

Index

Function 1 (F1): SMI Status and Power Management Timer Configuration Register Space
80h

0000 0000

1001 0

001

Index

1001 0

010

Index

1001 0

011

Index

1001 1

000

Index

Function 2 (F2): IDE Controller Configuration Register Space
80h

0000 0000

Function 3 (F3): XBus Expansion Register Space
80h

0000 0000

PCIUSB: USB Controller Register Configuration Space
80h

0000 0000

See “Example: Setting the ISA Bus Clock” on
page 183.

ZFx86 Data Book 1.0 Rev D

Page 196

4
4.4.2. Register Summaries
The tables in this subsection summarize all
the registers of the South Bridge module.

Included in the tables are the register’s reset
values and page references where the bit
formats are found.

Table 4.19 F0: PCI Header/Bridge and GPIO Configuration Register Summary
F0 Index

Width
(Bits)

Type

Name

Reset
Value

Reference
(Table 4.30)

00h-01h

16

RO

Vendor Identification Register

1078h

Page 207

02h-03h

16

RO

Device Identification Register

0400h

Page 207

04h-05h

16

R/W

PCI Command Register

000Fh

Page 207

06h-07h

16

R/W

PCI Status Register

0280h

Page 207

08h

8

RO

Device Revision ID Register

00h

Page 208

09h-0Bh

24

RO

PCI Class Code Register

060100h

Page 208

0Ch

8

R/W

PCI Cache Line Size Register

00h

Page 208

0Dh

8

R/W

PCI Latency Timer Register

00h

Page 208

0Eh

8

RO

PCI Header Type Register

80h

Page 208

0Fh

8

RO

PCI BIST Register

00h

Page 208

10h-13h

32

R/W

Base Address Register 0 (F0BAR0) — Sets the base
address for the I/O mapped GPIO Runtime and Configuration
Registers (summarized in Table 4.20).

00000001h

Page 208

14h-2Bh

--

--

2Ch-2Dh

16

RO

Subsystem Vendor ID

Reserved

1078h

Page 209

2Eh-2Fh

16

RO

Subsystem ID

0400h

Page 209

30h-3Fh

--

--

40h

8

R/W

PCI Function Control Register 1

39h

Page 209

41h

8

R/W

PCI Function Control Register 2

00h

Page 209

42h

--

--

43h

8

R/W

44h

8

R/W

45h

--

--

46h

8

R/W

PCI Functions Enable Register

FEh

Page 210

47h

8

R/W

Miscellaneous Enable Register

00h

Page 210

Reserved

Reserved

--

--

--

PIT Delayed Transactions Register

02h

Page 210

Reset Control Register

01h

Page 210

Reserved

48h-4Bh

--

--

4Ch-4Fh

32

R/W

Top of System Memory

Reserved

50h

8

R/W

51h

8

R/W

--

-FFFFFFFFh

Page 211

PIT Control/ISA CLK Divider

7Bh

Page 211

ISA I/O Recovery Control Register

40h

Page 211

52h

8

R/W

ROM/AT Logic Control Register

98h

Page 211

53h

8

R/W

Alternate CPU Support Register

00h

Page 212

54h-59h

--

--

5Ah

8

R/W

Reserved
Decode Control Register 1

-01h

Page 212

5Bh

8

R/W

Decode Control Register 2

20h

Page 213

5Ch

8

R/W

PCI Interrupt Steering Register 1

00h

Page 213

5Dh

8

R/W

PCI Interrupt Steering Register 2

00h

Page 214

5Eh-6Dh

--

--

Reserved

--

6Eh-6Fh

16

R/W

ROM Mask Register

FFF0h

Page 214

70h-71h

16

R/W

IOCS1# Base Address Register

0000h

Page 214

ZFx86 Data Book 1.0 Rev D

Page 197

4
Table 4.19 F0: PCI Header/Bridge and GPIO Configuration Register Summary (cont.)
Width
(Bits)

Type

72h

8

R/W

73h

--

--

74h-75h

16

R/W

IOCS0# Base Address Register

76h

8

R/W

IOCS0# Control Register

F0 Index

Name
IOCS1# Control Register
Reserved

Reserved

Reset
Value

Reference
(Table 4.30)

00h

Page 214

-0000h

Page 215

00h

Page 215

77h

--

--

78h-7Bh

32

R/W

DOCCS# Base Address Register

00000000h

Page 215

7Ch-7Fh

32

R/W

DOCCS# Control Register

00000000h

Page 215

80h

8

R/W

Power Management Enable Register 1

00h

Page 216

81h

8

R/W

Power Management Enable Register 2

00h

Page 216

82h

8

R/W

Power Management Enable Register 3

00h

Page 217

83h

8

R/W

Power Management Enable Register 4

00h

Page 218

84h

--

--

85h

8

RO

Second Level PME/SMI Status Mirror Register 2

00h

Page 219

86h

8

RO

Second Level PME/SMI Status Mirror Register 3

00h

Page 219

87h

8

RO

Second Level PME/SMI Status Mirror Register 4

00h

Page 220

88h

8

R/W

General Purpose Timer 1 Count Register

00h

Page 220

89h

8

R/W

General Purpose Timer 1 Control Register

00h

Page 220

8Ah

8

R/W

General Purpose Timer 2 Count Register

00h

Page 221

8Bh

8

R/W

General Purpose Timer 2 Control Register

00h

Page 221

8Ch

8

R/W

IRQ Speedup Timer Count Register

00h

Page 222

8Dh-92h

--

--

93h

8

R/W

Miscellaneous Device Control Register

00h

Page 222

94h

8

R/W

Suspend Modulation OFF Count Register

00h

Page 222

95h

8

R/W

Suspend Modulation ON Count Register

00h

Page 222

96h

8

R/W

Suspend Configuration Register

00h

Page 223

97h

--

--

Reserved

Reserved

Reserved

--

--

--

--

98h-99h

16

R/W

Hard Disk Idle Timer Count Register — Primary Channel

0000h

Page 223

9Ah-9Bh

16

R/W

Floppy Disk Idle Timer Count Register

0000h

Page 223

9Ch-9Dh

16

R/W

Parallel / Serial Idle Timer Count Register

0000h

Page 223

9Eh-9Fh

16

R/W

Keyboard / Mouse Idle Timer Count Register

0000h

Page 224

A0h-A1h

16

R/W

User Defined Device 1 Idle Timer Count Register

0000h

Page 224

A2h-A3h

16

R/W

User Defined Device 2 Idle Timer Count Register

0000h

Page 224

A4h-A5h

16

R/W

User Defined Device 3 Idle Timer Count Register

0000h

Page 224

A6h-ABh

--

--

ACh-ADh

16

R/W

AEh

8

WO

AFh

8

WO

B0h-B7h

--

--

B8h

8

RO

DMA Shadow Register

xxh

Page 225

B9h

8

RO

PIC Shadow Register

xxh

Page 225

BAh

8

RO

PIT Shadow Register

xxh

Page 226

BBh

8

RO

RTC Index Shadow Register

xxh

Page 226

BCh

8

R/W

Clock Stop Control Register

00h

Page 226

ZFx86 Data Book 1.0 Rev D

Reserved

-0000h

Page 224

CPU Suspend Command Register

00h

Page 225

Suspend Notebook Command Register

00h

Page 225

Hard Disk Idle Timer Count Register — Secondary
Channel

Reserved

--

Page 198

4
Table 4.19 F0: PCI Header/Bridge and GPIO Configuration Register Summary (cont.)
F0 Index

Width
(Bits)

Type

Name

Reset
Value

Reserved

Reference
(Table 4.30)

BDh-BFh

--

--

C0h-C3h

32

R/W

User Defined Device 1 Base Address Register

00000000h

-Page 226

C4h-C7h

32

R/W

User Defined Device 2 Base Address Register

00000000h

Page 226

C8h-CBh

32

R/W

User Defined Device 3 Base Address Register

00000000h

Page 227

CCh

8

R/W

User Defined Device 1 Control Register

00h

Page 227

CDh

8

R/W

User Defined Device 2 Control Register

00h

Page 227

CEh

8

R/W

User Defined Device 3 Control Register

00h

Page 227

CFh

--

--

D0h

8

WO

D1h-EBh

--

--

ECh

8

R/W

EDh-F4h

--

--

F5h

8

RC

Second Level PME/SMI Status Register 2

00h

Page 228

F6h

8

RC

Second Level PME/SMI Status Register 3

00h

Page 228

F7h

8

RC

Second Level PME/SMI Status Register 4

00h

Page 229

F8h-FFh

--

--

Reserved
Software SMI Register

-00h

Reserved
Timer Test Register

Page 228

-00h

Reserved

Page 228

--

Reserved

--

Table 4.20 F0BAR0: GPIO Support Registers Summary
F0BAR0+
I/O Offset

Width
(Bits)

Type

Name

00h

8

R/W

GPIO Data Out 0 Register

01h-03h

--

--

04h

8

RO

05h-07h

--

--

08h

8

R/W

09h-0Bh

--

--

0Ch

8

R/W1C

0Dh-1Fh

--

--

20h

8

R/W

21h-23h

--

--

24h

8

R/W

25h-27h

--

--

28h

8

R/W

29h-2Bh

--

--

ZFx86 Data Book 1.0 Rev D

Reserved
GPIO Data In 0 Register
Reserved
GPIO Interrupt Enable 0 Register
Reserved
GPIO Status 0 Register
Reserved
GPIO Pin Configuration Select Register
Reserved
GPIO Pin Configuration Access Register
Reserved
GPIO Reset Control Register
Reserved

Reset
Value

Reference
(Table 4.31)

FFh

Page 230

-FFh

Page 230

-00h

Page 230

-00h

Page 230

-00h

Page 230

-44h

Page 231

-00h

Page 231

--

Page 199

4
Table 4.21 F1: PCI Header Registers for SMI Status Summary
Width
(Bits)

Type

Name

Reset
Value

00h-01h

16

02h-03h

16

RO

Vendor Identification Register

1078h

Page 232

RO

Device Identification Register

0401h

Page 232

04h-05h

16

06h-07h

16

R/W

PCI Command Register

0000h

Page 232

RO

PCI Status Register

0280h

08h

Page 232

8

RO

Device Revision ID Register

00h

Page 232

09h-0Bh

24

RO

PCI Class Code Register

000000h

Page 232

0Ch

8

RO

PCI Cache Line Size Register

00h

Page 232

0Dh

8

RO

PCI Latency Timer Register

00h

Page 232

0Eh

8

RO

PCI Header Type Register

00h

Page 232

0Fh

8

RO

PCI BIST Register

00h

Page 232

10h-13h

32

R/W

Base Address Register 0 (F1BAR0) — Sets the base
address for the I/O mapped SMI Status Registers
(summarized in Table 4.22).

00000001h

Page 232

F1 Index

Reserved

Reference
(Table 4.32)

14h-2Bh

--

--

2Ch-2Dh

16

RO

Subsystem Vendor ID

1078h

Page 232

2Eh-2Fh

16

RO

Subsystem ID

0401h

Page 232

30h-FFh

--

--

Reserved

--

--

Table 4.22 F1BAR0: SMI Status Registers Summary
F1BAR0+
I/O Offset

Width
(Bits)

Type

Name

Reset
Value

Reference
(Table 4.33)

00h-01h

16

RO

Top Level PME/SMI Status Mirror Register

0000h

Page 233

02h-03h
04h-05h

16

RC

Top Level PME/SMI Status Register

0000h

Page 233

16

RO

Second Level General Traps & Timers PME/SMI

0000h

Page 234

0000h

Page 235

0000h

Page 235

Status Mirror Register
06h-07h

16

RC

Second Level General Traps & Timers PME/SMI
Status Register

08h-09h

16

Read to
Enable

0Ah-4Fh

--

--

Reserved

50h-FFh

--

--

The I/O mapped registers located here (F1BAR0+Offset 50h-FFh) are also accessible at F0
Index 50h-FFh. The preferred method is to program these registers through the F0 register
space.

ZFx86 Data Book 1.0 Rev D

SMI Speedup Disable Register

--

Page 200

4
Table 4.23 F2: PCI Header Registers for IDE Controller Support Summary
F2 Index
00h-01h

Width
(Bits)

Type

16

RO

Name

Reset
Value

Reference
(Table 4.34)

Vendor Identification Register

1078h

Page 236

02h-03h

16

RO

Device Identification Register

0402h

Page 236

04h-05h

16

R/W

PCI Command Register

0000h

Page 236

06h-07h

16

RO

PCI Status Register

0280h

Page 236

08h

8

RO

Device Revision ID Register

01h

Page 236

09h-0Bh

24

RO

PCI Class Code Register

010180h

Page 236

0Ch

8

RO

PCI Cache Line Size Register

00h

Page 236

0Dh

8

RO

PCI Latency Timer Register

00h

Page 236

0Eh

8

RO

PCI Header Type Register

00h

Page 236

0Fh

8

RO

PCI BIST Register

00h

Page 236

10h-13h

32

RO

Base Address Register 0 (F2BAR0) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 236

14h-17h

32

RO

Base Address Register 1 (F2BAR1) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 236

18h-1Bh

32

RO

Base Address Register 2 (F2BAR2) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 236

1Ch-1Fh

32

RO

Base Address Register 3 (F2BAR3) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 237

20h-23h

32

R/W

Base Address Register 4 (F2BAR4) — Sets the base
address for the I/O mapped Bus Master IDE Registers
(summarized in Table 4.25)

00000001h

Page 237

24h-2Bh

--

--

--

Page 237

2Ch-2Dh

16

RO

Subsystem Vendor ID

1078h

Page 237

2Eh-2Fh

16

RO

Subsystem ID

0402h

Page 237

30h-3Fh

--

--

--

Page 237

40h-43h

32

R/W

Channel 0 Drive 0 PIO Register

00009172h

Page 237

44h-47h

32

R/W

Channel 0 Drive 0 DMA Control Register

00077771h

Page 238

48h-4Bh

32

R/W

Channel 0 Drive 1 PIO Register

00009172h

Page 238

4Ch-4Fh

32

R/W

Channel 0 Drive 1 DMA Control Register

00077771h

Page 238

50h-53h

32

R/W

Channel 1 Drive 0 PIO Register

00009172h

Page 238

54h-57h

32

R/W

Channel 1 Drive 0 DMA Control Register

00077771h

Page 238

58h-5Bh

32

R/W

Channel 1 Drive 1 PIO Register

00009172h

Page 238

5Ch-5Fh

32

R/W

Channel 1 Drive 1 DMA Control Register

00077771h

Page 239

60h-FFh

--

--

ZFx86 Data Book 1.0 Rev D

Reserved

Reserved

Reserved

--

Page 201

4
Table 4.24 IDE Controller Configuration Summary
F2BAR4+
I/O Offset

Width
(Bits)

Type

00h

8

R/W

01h

--

--

02h

8

R/W

Name
IDE Bus Master 0 Command Register — Primary
Not Used
IDE Bus Master 0 Status Register — Primary

03h

--

--

04h-07h

32

R/W

Not Used
IDE Bus Master 0 PRD Table Address — Primary

08h

8

R/W

IDE Bus Master 1 Command Register — Secondary

09h

--

--

0Ah

8

R/W

0Bh

--

--

0Ch-0Fh

32

R/W

Not Used
IDE Bus Master 1 Status Register — Secondary
Not Used
IDE Bus Master 1 PRD Table Address — Secondary

Reset
Value

Reference
(Table 4.35)

00h

Page 239

-00h

Page 239

-00000000h

Page 240

00h

Page 240

-00h

Page 240

-00000000h

Page 240

Table 4.25 F3: PCI Header Registers for XBus Expansion Summary
Width
(Bits)

Type

Name

Reset
Value

00h-01h

16

02h-03h

16

RO

Vendor Identification Register

1078h

Page 241

RO

Device Identification Register

0403h

Page 241

04h-05h

16

06h-07h

16

R/W

PCI Command Register

0000h

Page 241

RO

PCI Status Register

0280h

08h

Page 241

8

RO

Device Revision ID Register

00h

Page 241

09h-0Bh

24

RO

PCI Class Code Register

000000h

Page 241

0Ch

8

RO

PCI Cache Line Size Register

00h

Page 241

0Dh

8

RO

PCI Latency Timer Register

00h

Page 241

0Eh

8

RO

PCI Header Type Register

00h

Page 241

0Fh

8

RO

PCI BIST Register

00h

Page 241

10h-13h

32

R/W

Base Address Register 0 (F3BAR0) — Sets the base
address for the XBus Expansion support registers
(summarized in Table 4.26).

00000000h

Page 241

14h-17h

32

R/W

Base Address Register 1 (F3BAR1) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 242

18h-1Bh

32

R/W

Base Address Register 2 (F3BAR2) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 242

1Ch-1Fh

32

R/W

Base Address Register 3 (F3BAR3) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 242

20h-23h

32

R/W

Base Address Register 4 (F3BAR4) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 242

24h-27h

32

R/W

Base Address Register 5 (F3BAR5) — Reserved for
possible future use by the South Bridge module.

00000000h

Page 242

F3 Index

28h-2Bh

--

--

2Ch-2Dh

16

RO

Subsystem Vendor ID

1078h

Page 242

2Eh-2Fh

16

RO

Subsystem ID

0405h

Page 242

30h-3Fh

--

--

ZFx86 Data Book 1.0 Rev D

Reserved

Reference
(Table 4.36)

Reserved

--

--

Page 202

4
Table 4.25 F3: PCI Header Registers for XBus Expansion Summary (cont.)
Width
(Bits)

Type

Name

Reset
Value

Reference
(Table 4.36)

40h-43h

32

R/W

44h-47h

32

R/W

F3BAR0 Base Address Register Mask

00000000h

Page 242

F3BAR1 Base Address Register Mask

00000000h

48h-4Bh

32

Page 243

R/W

F3BAR2 Base Address Register Mask

00000000h

4Ch-4Fh

Page 243

32

R/W

F3BAR3 Base Address Register Mask

00000000h

Page 243

50h-53h

32

R/W

F3BAR4 Base Address Register Mask

00000000h

Page 243

54h-57h

32

R/W

F3BAR5 Base Address Register Mask

00000000h

Page 243

58h

8

R/W

F3BARx Initialized Register

00h

Page 243

58h-FFh

--

--

F3 Index

Reserved

--

Table 4.26 F3BAR0: XBus Expansion Registers Summary
F3BAR0+
I/O Offset
00h-03h

Width
(Bits)

Type

Name

Reset
Value

Reference
(Table 4.37)

32

R/W

I/O Control Register 1

010C0007h

Page 244

04h-07h

32

R/W

I/O Control Register 2

00000000h

Page 245

08h-0Bh

32

R/W

I/O Control Register 3

00009000h

Page 245

Table 4.27 PCIUSB: USB Controller Register Summary
PCIUSB
Index

Width
(Bits)

Type

Name

Reset Value

Reference
(Table 4.38)

00h-01h

16

RO

Vendor Identification

0E11h

Page 246

02h-03h

16

RO

Device Identification

A0F8h

Page 246

04h-05h

16

R/W

Command Register

00h

Page 246

06h-07h

16

R/W

Status Register

0280h

Page 246

08h

8

RO

Device Revision ID

07h

Page 247

09h-0Bh

24

RO

Class Code

0C0310h

Page 247

0Ch

8

R/W

Cache Line Size

00h

Page 247

0Dh

8

R/W

Latency Timer

00h

Page 247

0Eh

8

RO

Header Type

00h

Page 247

0Fh

8

RO

BIST Register

00h

Page 247

10h-13h

32

R/W

Base Address 0

00000000h

Page 247

14h-2Bh

--

--

2Ch-2Dh

16

R/W

Subsystem Vendor ID

0E11h

Page 247

2Eh-2Fh

16

R/W

Subsystem ID

A0F8h

Page 247

30h-3Bh

--

--

3Ch

8

R/W

Interrupt Line Register

00h

Page 247

3Dh

8

RO

Interrupt Pin Register

01h

Page 248

3Eh

8

RO

Min. Grant Register

00h

Page 248

3Fh

8

RO

Max. Latency Register

50h

Page 248

ZFx86 Data Book 1.0 Rev D

Reserved

Reserved

--

--

Page 203

4
Table 4.27 PCIUSB: USB Controller Register Summary (cont.)
PCIUSB
Index

Width
(Bits)

Type

Name

40h-43h

32

R/W

ASIC Test Mode Enable Register

44h

8

R/W

ASIC Operational Mode Enable

45h-FFh

--

--

Reserved

Reset Value

Reference
(Table 4.38)

000F0000h

Page 248

00h

Page 248

--

Table 4.28 ZF-Logic Register Summary
ISA
Index

Width
(Bits)

Type

218-21Ch

40

--

Name
Reserved for ZF-Logic - See ‘ZF-Logic and Clocking’ on
page 403.

Reset Value

Reference

--

Page 403

Table 4.29 Legacy I/O Register Summary
I/O Port

Type

Name

Reference

DMA Channel Control Registers (Table 4.39)
000h

R/W

DMA Channel 0 Address Register

Page 248

001h

R/W

DMA Channel 0 Transfer Count Register

Page 248

002h

R/W

DMA Channel 1 Address Register

Page 249

003h

R/W

DMA Channel 1 Transfer Count Register

Page 249

004h

R/W

DMA Channel 2 Address Register

Page 249

005h

R/W

DMA Channel 2 Transfer Count Register

Page 249

006h

R/W

DMA Channel 3 Address Register

Page 249

007h

R/W

DMA Channel 3 Transfer Count Register

Page 249

008h

Read

DMA Status Register, Channels 3:0

Page 249

Write

DMA Command Register, Channels 3:0

Page 249

009h

WO

Software DMA Request Register, Channels 3:0

Page 249

00Ah

R/W

DMA Channel Mask Register, Channels 3:0

Page 249

00Bh

WO

DMA Channel Mode Register, Channels 3:0

Page 250

00Ch

WO

DMA Clear Byte Pointer Command, Channels 3:0

Page 250

00Dh

WO

DMA Master Clear Command, Channels 3:0

Page 250

00Eh

WO

DMA Clear Mask Register Command, Channels 3:0

Page 250

00Fh

WO

DMA Write Mask Register Command, Channels 3:0

Page 250

0C0h

R/W

DMA Channel 4 Address Register (Not used)

Page 250

0C2h

R/W

DMA Channel 4 Transfer Count Register (Not Used)

Page 250

0C4h

R/W

DMA Channel 5 Address Register

Page 250

0C6h

R/W

DMA Channel 5 Transfer Count Register

Page 250

0C8h

R/W

DMA Channel 6 Address Register

Page 250

0CAh

R/W

DMA Channel 6 Transfer Count Register

Page 250

0CCh

R/W

DMA Channel 7 Address Register

Page 250

0CEh

R/W

DMA Channel 7 Transfer Count Register

Page 250

ZFx86 Data Book 1.0 Rev D

Page 204

4
Table 4.29 Legacy I/O Register Summary (cont.)
I/O Port

Type

Name

Reference

0D0h

Read

DMA Status Register, Channels 7:4

Page 251

Write

DMA Command Register, Channels 7:4

Page 251

0D2h

WO

Software DMA Request Register, Channels 7:4

Page 251

0D4h

R/W

DMA Channel Mask Register, Channels 7:0

Page 251

0D6h

WO

DMA Channel Mode Register, Channels 7:4

Page 251

0D8h

WO

DMA Clear Byte Pointer Command, Channels 7:4

Page 251

0DAh

WO

DMA Master Clear Command, Channels 7:4

Page 251

0DCh

WO

DMA Clear Mask Register Command, Channels 7:4

Page 251

0DEh

WO

DMA Write Mask Register Command, Channels 7:4

Page 251

DMA Page Registers (Table 4.40)
081h

R/W

DMA Channel 2 Low Page Register

Page 252

082h

R/W

DMA Channel 3 Low Page Register

Page 252

083h

R/W

DMA Channel 1 Low Page Register

Page 252

087h

R/W

DMA Channel 0 Low Page Register

Page 252

089h

R/W

DMA Channel 6 Low Page Register

Page 252

08Ah

R/W

DMA Channel 7 Low Page Register

Page 252

08Bh

R/W

DMA Channel 5 Low Page Register

Page 252

08Fh

R/W

ISA Refresh Low Page Register

Page 252

481h

R/W

DMA Channel 2 High Page Register

Page 252

482h

R/W

DMA Channel 3 High Page Register

Page 252

483h

R/W

DMA Channel 1 High Page Register

Page 252

487h

R/W

DMA Channel 0 High Page Register

Page 252

489h

R/W

DMA Channel 6 High Page Register

Page 252

48Ah

R/W

DMA Channel 7 High Page Register

Page 253

48Bh

R/W

DMA Channel 5 High Page Register

Page 253

Programmable Interval Timer Registers (Table 4.41)
040h
041h
042h
043h

Write

PIT Timer 0 Counter

Page 253

Read

PIT Timer 0 Status

Page 253

Write

PIT Timer 1 Counter (Refresh)

Page 253

Read

PIT Timer 1 Status (Refresh)

Page 253

Write

PIT Timer 2 Counter (Speaker)

Page 253

Read

PIT Timer 2 Status (Speaker)

Page 253

R/W

PIT Mode Control Word Register

Page 254

Programmable Interrupt Controller Registers (Table 4.42)
020h / 0A0h

WO

Master / Slave PCI IWC1

Page 254

021h / 0A1h

WO

Master / Slave PIC ICW2

Page 254

021h / 0A1h

WO

Master / Slave PIC ICW3

Page 254

021h / 0A1h

WO

Master / Slave PIC ICW4

Page 254

021h / 0A1h

R/W

Master / Slave PIC OCW1

Page 255

020h / 0A0h

WO

Master / Slave PIC OCW2

Page 255

020h / 0A0h

WO

Master / Slave PIC OCW3

Page 255

020h / 0A0h

RO

Master / Slave PIC Interrupt Request and Service Registers for OCW3 Commands

Page 255

ZFx86 Data Book 1.0 Rev D

Page 205

4
Table 4.29 Legacy I/O Register Summary (cont.)
I/O Port

Type

Name

Reference

Keyboard Controller Registers (Table 4.43)
060h

R/W

External Keyboard Controller Data Register

Page 256

061h

R/W

Port B Control Register

Page 256

062h

R/W

External Keyboard Controller Mailbox Register

Page 256

064h

R/W

External Keyboard Controller Command Register

Page 256

066h

R/W

External Keyboard Controller Mailbox Register

Page 257

092h

R/W

Port A Control Register

Page 257

Real Time Clock Registers (Table 4.44)
070h

WO

RTC Address Register

Page 257

071h

R/W

RTC Data Register

Page 257

Miscellaneous Registers (Table 4.45)
0F0h, 0F1h

WO

Coprocessor Error Register

Page 257

170h-177h/
376h-377h

R/W

Secondary IDE Registers

Page 257

1F0-1F7h/
3F6h-3F7h

R/W

Primary IDE Registers

Page 257

4D0h

R/W

Interrupt Edge/Level Select Register 1

Page 257

4D1h

R/W

Interrupt Edge/Level Select Register 2

Page 258

4.4.3. Chipset Register Space
The Chipset Register Space of the South
Bridge module is comprised of four separate
functions (F0-F3), each with its own register
space. Base Address Registers (BARs) in
each PCI header register space set the base
address for the configuration registers for
each respective function. The configuration
registers accessed through BARs are I/O or
memory mapped. The PCI header registers in
all functions are very similar.
• Function 0 (F0): PCI Header/Bridge
Configuration Registers and GPIO
Support
• Function 1 (F1): PCI Header Registers for
SMI Status
• Function 2 (F2): PCI Header/Channel 0
and 1 Configuration Registers for IDE
Controller Support

• Function 3 (F3): PCI Header Registers for
XBus Expansion.
F3 contains six BARs in their standard PCI
header locations (that is, Index 10h, 14h,
18h, 1Ch, 20, and 24h). In addition there
are six mask registers that allow the six
BARs to be fully programmed; I/O versus
memory space and size:
--from 4 GB to 16 bytes for memory and
--from 4 GB to 4 bytes for I/O.

4.4.3.1. Bridge, GPIO Registers Function 0
The register space designated as Function 0
(F0) is used to configure Bridge features and
functionality unique to the South Bridge
module. In addition, it configures the PCI
portion of support hardware for the GPIO
support registers. Table 4.30 defines the bit
formats for the PCI Header Registers and
Bridge Configuration.
Note: The registers at F0 Index 50h-FFh can

ZFx86 Data Book 1.0 Rev D

Page 206

4
also be accessed at F1BAR0+I/O
Offset 50h-FFh. However, the preferred
method is to program these registers
through the F0 register space.

Located in the PCI Header Registers of F0 is
Base Address Register (F0BAR0) used for
pointing to the register spaces designated for
GPIO configuration, described in Section
4.4.3.2.

Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers
Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0400h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 000Fh

15:10
9

Reserved — Set to 0.
Fast Back-to-Back Enable (Read Only) — Always reads 0.

8

SERR# — Allow SERR# assertion on detection of special errors: 0 = Disable (Default); 1 = Enable.

7

Wait Cycle Control (Read Only) — Always reads 0.

6

Parity Error — Allow the South Bridge module to check for parity errors on PCI cycles for which it is a target and to
assert PERR# when a parity error is detected: 0 = Disable (Default); 1 = Enable.

5

VGA Palette Snoop Enable (Read Only) — Always disabled. Reads 0.

4

Memory Write and Invalidate — Allow the South Bridge module to do memory write and invalidate cycles, if the PCI
Cache Line Register (F0 Index 0Ch) is set to 32 bytes (08h). 0 = Disable (Default); 1 = Enable.

3

Special Cycles — Allow the South Bridge module to respond to special cycles: 0 = Disable; 1 = Enable (Default).

2

Bus Master — Allow the South Bridge module bus mastering capabilities: 0 = Disable; 1 = Enable (Default).

This bit must be enabled to allow the CPU Warm Reset signal to be triggered from a CPU Shutdown cycle.
This bit must be set to 1.
1

Memory Space — Allow the South Bridge module to respond to memory cycles from the PCI bus:
0 = Disable; 1 = Enable (Default).

0

I/O Space —Allow the South Bridge module to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable (Default).
This bit must be enabled to access I/O offsets through F0BAR0 and F0BAR1 (see F0 Index 10h and 14h).

Index 06h-07h
15

PCI Status Register (R/W)

Reset Value = 0280h

Detected Parity Error — This bit is set whenever a parity error is detected.
Write 1 to clear.

14

Signaled System Error — This bit is set whenever the South Bridge module asserts SERR# active.
Write 1 to clear.

13

Received Master Abort — This bit is set whenever a master abort cycle occurs. A master abort will occur when a PCI
cycle is not claimed, except for special cycles.
Write 1 to clear.

12

Received Target Abort — This bit is set whenever a target abort is received while the South Bridge module is the
master for the PCI cycle.
Write 1 to clear.

11

Signaled Target Abort — This bit is set whenever the South Bridge module signals a target abort. This occurs when an
address parity error occurs for an address that hits in the active address decode space of the South Bridge module.
Write 1 to clear.

10:9

DEVSEL# Timing (Read Only) — These bits are always 01, as the South Bridge module will always respond to cycles
for which it is an active target with medium DEVSEL# timing. 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved.

ZFx86 Data Book 1.0 Rev D

Page 207

4
Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit
8

Description
Data Parity Detected —This bit is set when:
1) The South Bridge module asserted PERR# or observed PERR# asserted.
2) The South Bridge module is the master for the cycle in which the PERR# occurred and the Parity Error bit is set (F0
Index 04h[6] = 1).
Write 1 to clear.

7

Fast Back-to-Back Capable (Read Only) — As a target, the South Bridge module is capable of accepting fast back-toback transactions: 0 = Disable; 1 = Enable.
This bit is always 1.

6:0

Reserved

Index 08h
Index 09h-0Bh
Index 0Ch
7:0

Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (R/W)

Reset Value = 00h
Reset Value = 060100h
Reset Value = 00h

PCI Cache Line Size Register — This register sets the size of the PCI cache line, in increments of four bytes. For
memory write and invalidate cycles, the PCI cache line size must be set to 16 bytes (04h) and the Memory Write and
Invalidate bit must be set (F0 Index 04h[4] = 1).

Index 0Dh

PCI Latency Timer Register (R/W)

Reset Value = 00h

7:4

Reserved

3:0

PCI Latency Timer Value — The PCI Latency Timer Register prevents system lockup when a slave does not respond to
a cycle that the South Bridge module masters. If the value is set to 00h (default), the timer is disabled. If the timer is
written with any other value, bits [3:0] become the four most significant bytes in a timer that counts PCI clocks for slave
response. The timer is reset on each valid data transfer. If the counter expires before the next assertion of TRDY# is
received, the South Bridge module stops the transaction with a master abort and asserts SERR#, if enabled to do so
(F0 Index 04h[8] = 1).

Index 0Eh
7:0

PCI Header Type (RO)

Reset Value = 80h

PCI Header Type Register — This register defines the format of this header. This header is of type format 0.
Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

7

BIST Capable (Read Only) — Is device capable of running a built-in self-test (BIST)? 0 = No; 1 = Yes,

6

Reserved

5:4

Reserved

3:0

BIST Completion Code (Read Only) — Upon completion of the BIST, the completion code will be stored in these bits. A
completion code of zero indicates the BIST has successfully been completed. All other values indicate some type of
BIST failure.

Index 10h-13h

Base Address Register 0 - F0BAR0 (R/W)

Reset Value = 00000001h

This register allows access to I/O mapped GPIO runtime and configuration registers. Bits [5:0] are read only (000001), indicating a
64-byte aligned I/O address space. Table 4.31 gives the bit formats and reset values of the GPIO registers.
31:6

GPIO Base Address

5:0

Address Range (Read Only)

Index 14h-17h

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Reserved

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 18h-2Bh

Reserved

Index 2Ch-2Dh

Subsystem Vendor ID (RO)

Reset Value = 1078h

Index 2Eh-2Fh

Subsystem ID (RO)

Reset Value = 0400h

Index 30h-3Fh

Reserved

Index 40h
7:5
4
3:2

PCI Function Control Register 1 (R/W)

Reset Value = 39h

Reserved
PCI Subtractive Decode — Allow the South Bridge module to act as a subtractive decode agent on the Front-PCI bus:
0 = Disable; 1 = Enable.
Reserved

1

PERR# Signals SERR# — Assert SERR# any time that PERR# is asserted or detected active by the South Bridge
module (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 = Enable.

0

PCI Interrupt Acknowledge Cycle Response — Allow the South Bridge module to respond to PCI interrupt
acknowledge cycles: 0 = Disable; 1 = Enable.

Index 41h
7:4
3

PCI Function Control Register 2 (R/W)

Reset Value = 00h

Reserved
XBus Configuration Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs to one of the configuration registers in PCI Function 3 (F3) register space,
an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

2

IDE Configuration Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs to one of the configuration registers in PCI Function 2 (F2) register space,
an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

1

Power Management Configuration Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs to one of the configuration registers in PCI Function 1 (F1) register space,
an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

0

Legacy Configuration SMI — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs to one of the configuration registers in the ISA Legacy I/O register space,
an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
Note: It is not recommended

Index 42h

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Reserved

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 43h
7:2
1

PIT Delayed Transactions Register (R/W)

Reset Value = 02h

Reserved — Set to 0.
Enable PCI Delayed Transactions for AT legacy PIT I/O Addresses — Some x86 programs (certain
benchmarks/diagnostics) assume a particular latency for PIT accesses; this bit will allow that code to work.
0 = PIT I/O addresses complete as fast as possible on PCI.
1 = Accesses to PIT I/O addresses are delayed transactions on PCI. (Default)
For best performance when running Windows™ this bit should be set to 0.

0

Reserved

Index 44h
7:4
3

Reset Control Register (R/W)

Reset Value = 01h

Reserved
IDE Controller Reset — Reset the IDE controller: 0 = Disable; 1 = Enable.
Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

2

IDE Reset — Reset IDE bus: 0 = Disable; 1 = Enable (will drive outputs to zero).
Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

1

PCI Reset — Reset PCI bus: 0 = Disable; 1 = Enable.
When set, the South Bridge module PCI_RST# output pin is asserted and all devices on the PCI bus including PCIUSB
reset. No other function within the South Bridge module is affected by this bit.
Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

0

XBus Warm Start — Reading/writing this bit has two different meanings/functions:
Read: Has a warm start occurred since power-up? 0 = Yes; 1 = No
Write: 0 = NOP; 1 = Execute system wide reset

Index 45h

Reserved

Index 46h

PCI Functions Enable Register (R/W)

7:4
3

Reset Value = FEh

Reserved
F3 (PCI Function 3) —F3 register space: 0 = Disable; 1 = Enable (Default).
This bit must always be set to 1.

2

F2 (PCI Function 2) — F2 register space: 0 = Disable; 1 = Enable (Default).
This bit must always be set to 1.

1

F1 (PCI Function 1) — F1 register space: 0 = Disable; 1 = Enable (Default).
This bit must always be set to 1.

0

Reserved

Index 47h
7:2

Miscellaneous Enable Register (R/W)

Reset Value = 00h

Reserved

1

F0BAR0 (Function 0, Base Address Register 0) — F0BAR0, pointer to I/O mapped GPIO runtime and configuration
registers: 0 = Disable; 1 = Enable.

0

Reserved

Index 48h-4Bh

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Reserved

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 4Ch-4Fh
31:0

Top of System Memory (R/W)

Reset Value = FFFFFFFFh

Top of System Memory — Highest address in system used to determine active decode for external PCI mastered
memory cycles.
Errata: The last nibble must always remain set else external master bursted writes will be disabled. If an external PCI
master requests a memory address below the value programmed in this register, the cycle is transferred from the
external PCI bus interface to the Front-PCI interface for servicing by the processor module.

Index 50h

PIT Control/ISA CLK Divider (R/W)

Reset Value = 7Bh

7

PIT Software Reset — 0 = Disable; 1 = Enable.

6

PIT Counter 1 — 0 = Forces Counter 1 output (OUT1) to zero;
1 = Allows Counter 1 output (OUT1) to pass to the I/O Port 061h[4].

5

PIT Counter 1 Enable — 0 = Sets GATE1 input low; 1 = Sets GATE1 input high.

4

PIT Counter 0 — 0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0.

3

PIT Counter 0 Enable — 0 = Sets GATE0 input low; 1 = Sets GATE0 input high.

2:0

ISA Clock Divisor — Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed
for approximately 8 MHz:
000 = Divide by 1
001 = Divide by 2

010 = Divide by 3
011 = Divide by 4

100 = Divide by 5
101 = Divide by 6

110 = Divide by 7
111 = Divide by 8

If PCI clock = 25 MHz, use setting of 010 (divide by 3). It PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4).
Index 51h
7:4

0100 = 5 PCI clocks
0101 = 6 PCI clocks
0110 = 7 PCI clocks
0111 = 8 PCI clocks

1000 = 9 PCI clocks
1001 = 10 PCI clocks
1010 = 11 PCI clocks
1011 = 12 PCI clocks

1100 = 13 PCI clocks
1101 = 14 PCI clocks
1110 = 15 PCI clocks
1111 = 16 PCI clocks

16-Bit I/O Recovery — These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This
count is in addition to a preset one-clock delay built into the controller.
0000 = 1 PCI clock
0001 = 2 PCI clocks
0010 = 3 PCI clocks
0011 = 4 PCI clocks

Index 52h
7

Reset Value = 40h

8-Bit I/O Recovery — These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles.
This count is in addition to a preset one-clock delay built into the controller.
0000 = 1 PCI clock
0001 = 2 PCI clocks
0010 = 3 PCI clocks
0011 = 4 PCI clocks

3:0

ISA I/O Recovery Control Register (R/W)

0100 = 5 PCI clocks
0101 = 6 PCI clocks
0110 = 7 PCI clocks
0111 = 8 PCI clocks

1000 = 9 PCI clocks
1001 = 10 PCI clocks
1010 = 11 PCI clocks
1011 = 12 PCI clocks

ROM/AT Logic Control Register (R/W)

1100 = 13 PCI clocks
1101 = 14 PCI clocks
1110 = 15 PCI clocks
1111 = 16 PCI clocks
Reset Value = 98h

Snoop Fast Keyboard Gate A20 and Fast Reset — Enables the snoop logic associated with keyboard commands for
A20 Mask and Reset: 0 = Disable; 1 = Enable (snooping).
If disabled, the keyboard controller handles the commands.

6:5

Reserved

4

Enable A20M# Deassertion on Warm Reset — Force A20M# high during a Warm Reset (guarantees that A20M# is
deasserted regardless of the state of A20): 0 = Disable; 1 = Enable.

3

Enable Port 092h (Port A) — I/O Port 092h decode and the logical functions: 0 = Disable; 1 = Enable.

2

Upper ROM Size — Selects upper ROM addressing size:
0 = 256 KB (FFFC0000h-FFFFFFFFh);
1 = Use ROM Mask Register (F0 Index 6Eh)
ROMCS# goes active for the above ranges. Refer to F0BAR1+I/O Offset 10h[15] for further strapping/programming
details.
Note: The selected range can then be either positively or subtractively decoded through F0 index 5Bh[5].

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit
1

Description
ROM Write Enable — Enable writes to ROM space, allowing Flash programming: 0 = Disable; 1 = Enable.
If strapped for ISA and this bit is set, writes to the configured ROM space will assert ROMCS#, enabling the write cycle to
the Flash device on the ISA bus. Otherwise, ROMCS# is inhibited for writes.
Refer to F0BAR1+I/O Offset 10h[15] for further LPC strapping/programming details.

0

Lower ROM Size — Selects lower ROM addressing size in which ROMCS# goes active:
0 = 000F0000h-000FFFFFh (64 KB) (Default)
1 = 000E0000h-000FFFFFh (128 KB)
ROMCS# goes active for the above ranges. Refer to F0BAR1+I/O Offset 10h[15] for further strapping/programming
details.
Note: The selected range can then be either positively or subtractively decoded through F0 Index 5Bh[5].

Index 53h

Alternate CPU Support Register (R/W)

Reset Value = 00h

7

Enable Keyboard Chip Select — Allow the ROMCS# signal to fire on keyboard controller I/O accesses.
0 = Disable (Default); 1 = Enable.

6

Reserved

5

Bidirectional SMI Enable — 0 = Disable; 1 = Enable.

Note that even if this bit is enabled, F0 Index 81h[3] will prevent the ROMCS# from firing.

This bit must be set to 0.
4:2
1

Reserved
IRQ13 Pin Function Selection — Selects function of IRQ13/FERR# pin: 0 = FERR#; 1 = IRQ13.
This bit must be set to 1.

0

Generate SMI on A20M# toggle — 0 = Disable; 1 = Enable.
SMI status is reported at F1BAR0+I/O Offset 00h/02h[7].

Index 54h-59h
Index 5Ah

Reserved
Decode Control Register 1 (R/W)

Reset Value = 01h

7

Secondary Floppy Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port
372h-375h and 377h: 0 = Subtractive; 1 = Positive.

6

Primary Floppy Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port
3F2h-3F5h and 3F7h: 0 = Subtractive; 1 = Positive.

5

COM4 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 2E8h-2EFh:
0 = Subtractive; 1 = Positive.

4

COM3 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 3E8h-3EFh:
0 = Subtractive; 1 = Positive.

3

COM2 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 2F8h-2FFh:
0 = Subtractive; 1 = Positive.

2

COM1 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 3F8h-3FFh:
0 = Subtractive; 1 = Positive.

1

Keyboard Controller Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 060h
and 064h (and I/O Port 062h/066h if enabled): 0 = Subtractive; 1 = Positive.

0

Real Time Clock Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 070h and
071h: 0 = Subtractive; 1 = Positive.

Note: Positive decoding by the South Bridge module speeds up the I/O cycle time. These I/O Ports do not exist in the South
Bridge module. It is assumed that if positive decode is enabled, the port exists on the ISA bus.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 5Bh

Decode Control Register 2 (R/W)

Reset Value = 20h

7

Keyboard Port 062h/066h Decode — This alternate port to the keyboard controller is provided in support of the 8051SL
notebook keyboard controller mailbox: 0 = Disable; 1 = Enable.

6

Reserved

5

BIOS ROM Positive Decode — Selects positive or subtractive decoding for accesses to the configured ROM space:
0 = Subtractive; 1 = Positive.
ROM configuration is at F0 Index 52h[2:0].

4

Secondary IDE Controller Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port
170h-177h and 376h-377h (excluding writes to 377h): 0 = Subtractive; 1 = Positive.
Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus. Subtractively
decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are then forwarded to ISA.

3

Primary IDE Controller Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port
1F0h-1F7h and 3F6h-3F7h (excluding writes to 3F7h): 0 = Subtractive; 1 = Positive.
Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus. Subtractively
decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are then forwarded to ISA.

2

LPT3 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 3BCh-3BFh:
0 = Subtractive; 1 = Positive.

1

LPT2 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 378h-37Fh:
0 = Subtractive; 1 = Positive.

0

LPT1 Positive Decode — Selects PCI positive or subtractive decoding for accesses to I/O Port 278h-27Fh:
0 = Subtractive; 1 = Positive.

Note: Positive decoding by the South Bridge module speeds up the I/O cycle time. The Keyboard, LPT3, LPT2, and LPT1 I/O
Ports do not exist in the South Bridge module. It is assumed that if positive decode is enabled, the port exists on the ISA
bus.
Index 5Ch
7:4

Reset Value = 00h

INTB# Target Interrupt
0000 = Disable
0001 = IRQ1
0010 = RSVD
0011 = IRQ3

3:0

PCI Interrupt Steering Register 1 (R/W)
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7

1000 = RSVD
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11

1100 = IRQ12
1101 = RSVD
1110 = IRQ14
1111 = IRQ15

0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7

1000 = RSVD
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11

1100 = IRQ12
1101 = RSVD
1110 = IRQ14
1111 = IRQ15

INTA# Target Interrupt
0000 = Disable
0001 = IRQ1
0010 = RSVD
0011 = IRQ3

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt
compatibility

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 5Dh
7:4

0000 = Disable
0001 = IRQ1
0010 = RSVD
0011 = IRQ3
3:0

PCI Interrupt Steering Register 2 (R/W)

Reset Value = 00h

INTD# Target Interrupt
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7

1000 = RSVD
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11

1100 = IRQ12
1101 = RSVD
1110 = IRQ14
1111 = IRQ15

0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7

1000 = RSVD
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11

1100 = IRQ12
1101 = RSVD
1110 = IRQ14
1111 = IRQ15

INTC# Target Interrupt
0000 = Disable
0001 = IRQ1
0010 = RSVD
0011 = IRQ3

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt
compatibility
Index 5Eh-5Fh

Reserved

Index 60h-63h

Reserved

Index 64h-6Dh

Reserved

Index 6Eh-6Fh

ROM Mask Register (R/W)

15:8

Reserved — Read/modify/write.

7:4

ROM Size — If F0 Index 52h[2] = 1, these bits select the upper ROM size:
0000 = 1 MB: FFF00000h-FFFFFFFFh
0001 = 2 MB: FFE00000h-FFFFFFFFh
0010 = RSVD
0011 = 4 MB: FFC00000h-FFFFFFFFh
0100 = RSVD
0101 = RSVD
0110 = RSVD
0111 = 8 MB: FF800000h-FFFFFFFFh

3:0

1000 = RSVD
1001 = RSVD
1010 = RSVD
1011 = RSVD
1100 = RSVD
1101 = RSVD
1110 = RSVD
1111 = 16 MB: FF000000h-FFFFFFFFh

Reserved

Index 70h-71h
15:0

Reset Value = FFF0h

IOCS1# Base Address Register (R/W)

Reset Value = 0000h

I/O Chip Select 1 Base Address — This 16-bit value represents the I/O base address used to enable the assertion of
the IOCS1# signal.
This register, together with F0 Index 72h (control register) is used to configure the operation of the IOCS1# pin.

Index 72h

IOCS1# Control Register (R/W)

Reset Value = 00h

7

I/O Chip Select 1 — IOCS1#: 0 = Disable; 1 = Enable.

6

Writes Result in Chip Select — Writes to configured I/O address (base address configured in F0 Index 70h and range
configured in bits [4:0]) causes IOCS1# signal to be asserted: 0 = Disable; 1 = Enable.

5

Reads Result in Chip Select — Reads from configured I/O address (base address configured in F0 Index 70h and
range configured in bits [4:0]) causes IOCS1# signal to be asserted: 0 = Disable; 1 = Enable.

4:0

IOCS1# I/O Address Range — This 5-bit field is used to select the range of IOCS0# signal:
00000 = 1 byte
01111 = 16 bytes
00001 = 2 bytes
11111 = 32 bytes
00011 = 4 bytes
All other combinations are reserved.
00111 = 8 bytes

Note: This register, together with F0 Index 70h (base address register) is used to configure the operation of the IOCS1# pin.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 74h-75h
15:0

IOCS0# Base Address Register (R/W)

Reset Value = 0000h

I/O Chip Select 0 Base Address — This 16-bit value represents the I/O base address used to enable the assertion of
the IOCS0# signal.
This register, together with F0 Index 76h (control register) is used to configure the operation of the IOCS0# pin.

Index 76h

IOCS0# Control Register (R/W)

Reset Value = 00h

7

I/O Chip Select 0 — IOCS0#: 0 = Disable; 1 = Enable.

6

Writes Result in Chip Select — Writes to configured I/O address (base address configured in F0 Index 74h and range
configured in bits [4:0]) causes IOCS0# signal to be asserted: 0 = Disable; 1 = Enable.

5

Reads Result in Chip Select — Reads from configured I/O address (base address configured in F0 Index 74h and
range configured in bits [4:0]) causes IOCS0# signal to be asserted: 0 = Disable; 1 = Enable.

4:0

IOCS0# I/O Address Range — This 5-bit field is used to select the range of IOCS0# signal:
00000 = 1 byte
01111 = 16 bytes
00001 = 2 bytes
11111 = 32 bytes
00011 = 4 bytes
All other combinations are reserved.
00111 = 8 bytes

Note: This register together with F0 Index 74h (base address register) is used to configure the operation of the IOCS0# pin.
Index 77h
Index 78h-7Bh
31:0

Reserved
DOCCS# Base Address Register (R/W)

Reset Value = 00000000h

Disk-On-Chip Chip Select Base Address — This 32-bit value represents the memory base address used to enable the
assertion of the DOCCS# signal.
This register, together with F0 Index 7Ch (control register) is used to configure the operation of the DOCCS# pin.

Index 7Ch-7Fh
31:27

DOCCS# Control Register (R/W)

Reset Value = 00000000h

Reserved

26

Disk-On-Chip Chip Select — DOCCS#: 0 = Disable; 1 = Enable.

25

Writes Result in Chip Select — Writes to configured memory address (base address configured in F0 Index 78h and
range configured in bits [18:0]) causes DOCCS# signal to be asserted: 0 = Disable; 1 = Enable.

24

Reads Result in Chip Select — Reads from configured memory address (base address configured in F0 Index 78h and
range configured in bits [18:0]) causes DOCCS# signal to be asserted: 0 = Disable; 1 = Enable.

23:19

Reserved

18:0

DOCCS# Memory Address Range — This 19-bit mask is used to further qualify accesses on which the DOCCS# signal
is asserted. It is used to mask the upper 19 bits of the incoming PCI address (AD[31:13]).

Note: This register together with F0 Index 78h (base address register) is used to configure the operation of the DOCCS# pin.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 80h
7:4
3

Power Management Enable Register 1 (R/W)

Reset Value = 00h

Reserved
IRQ Speedup — Any unmasked IRQ (per I/O Ports 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA#
handshake) for a configurable duration when system is power managed using CPU Suspend modulation:
0 = Disable; 1 = Enable.
The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).

2

Traps — Globally enable all power management I/O traps: 0 = Disable; 1 = Enable.

1

Idle Timers — Device idle timers: 0 = Disable; 1 = Enable.
Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.
This bit has no affect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h).
Only applicable when in APM mode.

0

Power Management — Global power management: 0 = Disable; 1 = Enabled.
This bit must be set (1) immediately after POST for power management resources to function.

Index 81h

Power Management Enable Register 2 (R/W)

Reset Value = 00h

7

Reserved

6

User Defined Device 3 (UDEF3) Idle Timer Enable — Turn on UDEF3 Idle Timer Count Register (F0 Index A4h) and
generate an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count.
UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[6].

5

User Defined Device 2 (UDEF2) Idle Timer Enable — Turn on UDEF2 Idle Timer Count Register (F0 Index A2h) and
generate an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count.
UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[5].

4

User Defined Device 1 (UDEF1) Idle Timer Enable — Turn on UDEF1 Idle Timer Count Register (F0 Index A0h) and
generate an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count.
UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[4].

3

Keyboard/Mouse Idle Timer Enable — Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and
generate an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count.
Keyboard Controller: I/O Ports 060h/064h
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[3].

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit
2

Description
Parallel/Serial Idle Timer Enable — Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate
an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count.
LPT1: I/O Port 378h-37Fh, 778h-77Ah
LPT2: I/O Port 278h-27Fh, 678h-67Ah
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded)
COM3: I/O Port 3E8h-3EFh
COM4: I/O Port 2E8h-2EFh
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[2].

1

Floppy Disk Idle Timer Enable — Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI
when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the address ranges (listed below, the timer is reloaded with the programmed count.
Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h,
Secondary floppy disk: I/O Port 372h-375h, 377h
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[1].

0

Primary Hard Disk Idle Timer Enable — Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and
generate an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the address ranges selected in F0 Index 93h[5], the timer reloads with the programmed count.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[0].

Index 82h
7
6

Power Management Enable Register 3 (R/W)

Reset Value = 00h

Reserved
User Defined Device 3 (UDEF3) Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the programmed address range, an SMI generates. UDEF3 address
programming is at F0 Index C8h (base address register) and CEh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[4].

5

User Defined Device 2 (UDEF2) Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the programmed address range, an SMI generates. UDEF2 address
programming is at F0 Index C4h (base address register) and CDh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[3].

4

User Defined Device 1 (UDEF1) Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the programmed address range, an SMI generates. UDEF1 address
programming is at F0 Index C0h (base address register), and CCh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[2].

3

Keyboard/Mouse Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI generates.
Keyboard Controller: I/O Ports 060h/064h
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[3].

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit
2

Description
Parallel/Serial Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
LPT1: I/O Port 378h-37Fh, 778h-77Ah
LPT2: I/O Port 278h-27Fh, 678h-67Ah
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded)
COM3: I/O Port 3E8h-3EFh
COM4: I/O Port 2E8h-2EFh
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[2].

1

Floppy Disk Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI generates.
Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h,
Secondary floppy disk: I/O Port 372h-375h, 377h
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[1].

0

Primary Hard Disk Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI generates.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[0].
Note: Does not work when the internal IDE is used.

Index 83h
7

Power Management Enable Register 4 (R/W)

Reset Value = 00h

Secondary Hard Disk Idle Timer Enable — Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh)
and generate an SMI when the timer expires: 0 = Disable; 1 = Enable.
If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[4].

6

Secondary Hard Disk Trap — 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[5].
Note: Does not work when the internal IDE is used.

5:2
1

Reserved
General Purpose Timer 2 Enable — Turn on GP Timer 2 Count Register (F0 Index 8Ah) and generate an SMI when the
timer expires: 0 = Disable; 1 = Enable.
This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index
8Bh[5,3,2].
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[1].

0

General Purpose Timer 1 Enable — Turn on GP Timer 1 Count Register (F0 Index 88h) and generate an SMI when the
timer expires: 0 = Disable; 1 = Enable.
This idle timer’s load is multi-sourced and gets reloaded any time an enabled event (F0 Index 89h[6:0]) occurs.
GP Timer 1 programming is at F0 Index 8Bh[4].
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[0].

Index 84h

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 85h

Second Level PME/SMI Status Mirror Register 2 (RO, see Note)

Reset Value = 00h

7

Reserved

6

User Defined Device 3 Idle Timer (UDEF3) SMI Status (Read Only) — Was SMI caused by expiration of UDEF3 Idle
Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[6] = 1.

5

User Defined Device 2 Idle Timer (UDEF2) SMI Status (Read Only) — Was SMI caused by expiration of UDEF2 Idle
Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[5] = 1.

4

User Defined Device 1 Idle Timer (UDEF1) SMI Status (Read Only) — Was SMI caused by expiration of UDEF1 Idle
Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[4] = 1.

3

Keyboard/Mouse Idle Timer SMI Status (Read Only) — Was SMI caused by expiration of Keyboard/Mouse Idle Timer
Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[3] = 1.

2

Parallel/Serial Idle Timer SMI Status (Read Only) — Was SMI caused by expiration of Parallel/Serial Port Idle Timer
Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[2] = 1.

1

Floppy Disk Idle Timer SMI Status (Read Only) — Was SMI caused by expiration of Floppy Disk Idle Timer Count
Register (F0 Index 9Ah)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[1] = 1.

0

Primary Hard Disk Idle Timer SMI Status (Read Only) — Was SMI caused by expiration of Primary Hard Disk Idle
Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[0] = 1.

Note: Second level of status reporting. Top level status reported at F1BAR0+I/O Offset 00h/02h[0]. If any SMI source described in
Index 85h occurs, then bit 0 – SMI Source is Power Management Event of F1BAR+I/O Offset 00h/02h sets.
This register is called a “Mirror” register since an identical register exists at F0 Index F5h. Reading this register does not clear the
status, while reading its counterpart at F0 Index F5h clears the status at both the second and top levels.
Index 86h
7:6

Second Level PME/SMI Status Mirror Register 3 (RO, see Note)

Reset Value = 00h

Reserved

5

Secondary Hard Disk Access Trap SMI Status (Read Only) — Was SMI caused by a trapped I/O access to the
secondary hard disk? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[6] = 1.

4

Secondary Hard Disk Idle Timer SMI Status (Read Only) — Was SMI caused by expiration of Hard Disk Idle Timer
Count Register (F0 Index ACh)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[7] = 1.

3

Keyboard/Mouse Access Trap SMI Status (Read Only) — Was SMI caused by a trapped I/O access to the keyboard
or mouse? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[3] = 1.

2

Parallel/Serial Access Trap SMI Status (Read Only) — Was SMI caused by a trapped I/O access to either the serial or
parallel ports? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[2] = 1.

1

Floppy Disk Access Trap SMI Status (Read Only) — Was SMI caused by a trapped I/O access to the floppy disk?
0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[1] = 1.

0

Primary Hard Disk Access Trap SMI Status (Read Only) — Was SMI caused by a trapped I/O access to the primary
hard disk? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[0] = 1.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Note: Second level of status reporting. Top level status reported at F1BAR0+I/O Offset 00h/02h[0]. If any SMI source described in
Index 86h occurs, then bit 0 – SMI Source is Power Management Event of F1BAR+I/O Offset 00h/02h sets.
This register is called a “Mirror” register since an identical register exists at F0 Index F6h. Reading this register does not clear the
status, while reading its counterpart at F0 Index F6h clears the status at both the second and top levels.
Index 87h
7

Second Level PME/SMI Status Mirror Register 4 (RO, see Note)

Reset Value = 00h

GPIO Event SMI Status (Read Only) — Was SMI caused by a transition of any of the GPIOs? 0 = No; 1 = Yes.
Note that F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME. In addition, the selected
GPIO must be enabled as an input (F0BAR0+I/O Offset 20h and 24h).
The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch.

6:4
3

Reserved
SIO PWUREQ SMI Status (Read Only) — Was SMI caused by a power-up event from the SIO? 0 = No; 1 = Yes.
A power-up event is defined as any of the following events/activity: Modem, Telephone, Keyboard, Mouse, CEIR
(Consumer Electronic Infrared).

2

Reserved

1

Reserved

0

Reserved

Note: This is the second level of status reporting. The top level status is reported at F1BAR0+I/O Offset 00h/02h[0]. If any SMI
source described in Index 87h occurs, then bit 0 – SMI Source is Power Management Event of F1BAR+I/O Offset 00h/02h
is set.
This register is called a “Mirror” register since an identical register exists at F0 Index F7h. Reading this register does not clear the
status, while reading its counterpart at F0 Index F7h clears the status at both the second and top levels except for bit 7 which has a
third level of SMI status reporting at F0BAR0+I/O 0Ch/1Ch.
Index 88h
7:0

General Purpose Timer 1 Count Register (R/W)

Reset Value = 00h

General Purpose Timer 1 Count — This field represents the load value for General Purpose Timer 1. This value can
represent either an 8-bit or 16-bit counter (selected in F0 Index 8Bh[4]). It is loaded into the counter when the timer is
enabled (F0 Index 83h[0] = 1). Once enabled, an enabled event (configured in F0 Index 89h[6:0]) reloads the timer.
The counter is decremented with each clock of the configured timebase (1 msec or 1 sec selected at F0 Index 89h[7]).
Upon expiration of the counter, an SMI is generated and the top level SMI status is reported at F1BAR0+I/O Offset
00h/02h[9]. The second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[0]). Once expired, this counter must
be re-initialized by either disabling and enabling it, or writing a new count value here.

Index 89h

General Purpose Timer 1 Control Register (R/W)

Reset Value = 00h

7

General Purpose Timer 1 Timebase — Selects timebase for General Purpose Timer 1 (F0 Index 88h):
0 = 1 sec; 1 = 1 msec.

6

Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity — 0 = Disable; 1 = Enable.
Any access to the configured (memory or I/O) address range for UDEF3 (configured in F0 Index C8h and CEh) reloads
General Purpose Timer 1.

5

Re-trigger General Purpose Timer 1 on User Defined Device 2 (UDEF2) Activity — 0 = Disable; 1 = Enable.
Any access to the configured (memory or I/O) address range for UDEF2 (configured in F0 Index C4h and CDh) reloads
General Purpose Timer 1.

4

Re-trigger General Purpose Timer 1 on User Defined Device 1 (UDEF1) Activity — 0 = Disable; 1 = Enable.
Any access to the configured (memory or I/O) address range for UDEF1 (configured in F0 Index C0h and CCh) reloads
General Purpose Timer 1.

3

Re-trigger General Purpose Timer 1 on Keyboard or Mouse Activity — 0 = Disable; 1 = Enable
Any access to the keyboard or mouse I/O address range listed below reloads General Purpose Timer 1.
Keyboard Controller: I/O Ports 060h/064h
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit
2

Description
Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity — 0 = Disable; 1 = Enable.
Any access to the parallel or serial port I/O address range listed below reloads the General Purpose Timer 1.
LPT1: I/O Port 378h-37Fh, 778h-77Ah
LPT2: I/O Port 278h-27Fh, 678h-67Ah
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded)
COM3: I/O Port 3E8h-3EFh
COM4: I/O Port 2E8h-2EFh

1

Re-trigger General Purpose Timer 1 on Floppy Disk Activity — 0 = Disable; 1 = Enable.
Any access to the floppy disk drive address ranges listed below reloads General Purpose Timer 1.
Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h
Secondary floppy disk: I/O Port 372h-375h, 377h
The active floppy disk drive is configured via F0 Index 93h[7].

0

Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity — 0 = Disable; 1 = Enable.
Any access to the primary hard disk address range selected in F0 Index 93h[5], reloads General Purpose Timer 1.
Note: Does not work when the internal IDE is used.

Index 8Ah
7:0

General Purpose Timer 2 Count Register (R/W)

Reset Value = 00h

General Purpose Timer 2 Count — This field represents the load value for General Purpose Timer 2. This value can
represent either an 8-bit or 16-bit counter (configured in F0 Index 8Bh[5]). It is loaded into the counter when the timer is
enabled (F0 Index 83h[1] = 1). Once the timer is enabled and a transition occurs on GPIO7, the timer is re-loaded.
The counter is decremented with each clock of the configured timebase (1 msec or 1 sec selected at F0 Index 8Bh[3].
Upon expiration of the counter, an SMI is generated and the top level of status is F1BAR0+I/O Offset 00h/02h[9]. The
second level of status is reported at F1BAR0+I/O Offset 04h/06h[1]). Once expired, this counter must be re-initialized by
either disabling and enabling it, or writing a new count value here.
For GPIO7 to act as the reload for this counter, it must be enabled as such (F0 Index 8Bh[2]) and be configured as an
input. (GPIO pin programming is at F0BAR0+I/O Offset 20h and 24h.)

Index 8Bh
7

General Purpose Timer 2 Control Register (R/W)

Reset Value = 00h

Re-trigger General Purpose Timer 1 (GP Timer 1) on Secondary Hard Disk Activity — 0 = Disable; 1 = Enable.
Any access to the secondary hard disk address range selected in F0 Index 93h[4] reloads GP Timer 1.

6

Reserved

5

General Purpose Timer 2 (GP Timer 2) Shift — GP Timer 2 is treated as an 8-bit or 16-bit timer: 0 = 8-bit; 1 = 16-bit.
As an 8-bit timer, the count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah).
As a 16-bit timer, the value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become
zero, and this 16-bit value is used as the count for GP Timer 2.

4

General Purpose Timer 1 (GP Timer 1) Shift — GP Timer 1 is treated as an 8-bit or 16-bit timer: 0 = 8-bit; 1 = 16-bit.
As an 8-bit timer, the count value is loaded into GP Timer 1 Count Register (F0 Index 88h).
As a 16-bit timer, the value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become
zero, and this 16-bit value is used as the count for GP Timer 1.

3

General Purpose Timer 2 (GP Timer 2) Timebase — Selects timebase for GP Timer 2 (F0 Index 8Ah):
0 = 1 sec; 1 = 1 msec.

2

Re-trigger Timer on GPIO7 Pin Transition — A rising-edge transition on the GPIO7 pin reloads GP Timer 2 (F0 Index
8Ah): 0 = Disable; 1 = Enable.
For GPIO7 to work here, it must first be configured as an input. (GPIO pin programming is at F0BAR0+I/O Offset 20h and
24h.)

1:0

Reserved

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 8Ch
7:0

IRQ Speedup Timer Count Register (R/W)

Reset Value = 00h

IRQ Speedup Timer Load Value — This field represents the load value for the IRQ speedup timer. It is loaded into the
counter when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs.
When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU.
Upon expiration, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1
msec.
This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A
typical value here would be 2 to 4 msec.

Index 8Dh-92h
Index 93h

Reserved
Miscellaneous Device Control Register (R/W)

Reset Value = 00h

7

Floppy Disk Port Select — All system resources used to power manage the floppy disk drive use the primary or
secondary FDC addresses for decode: 0 = Secondary; 1 = Primary.

6

Reserved — This bit must always be set to 1 if written.

5

Partial Primary Hard Disk Decode — This bit is used to restrict the addresses which are decoded as primary hard disk
accesses.
0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h-3F7h (excludes writes to 3F7h)
1 = Power management monitors only writes to I/O Port 1F6h and 1F7h

4

Partial Secondary Hard Disk Decode — This bit is used to restrict the addresses which are decoded as secondary
hard disk accesses.
0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h-377h (excludes writes to 377h)
1 = Power management monitors only writes to I/O Port 176h and 177h

3:2

Reserved

1

Mouse on Serial Enable — Mouse is present on a Serial Port: 0 = No; 1 = Yes. (Note)

0

Mouse Port Select — Selects which serial port the mouse is attached to: 0 = COM1; 1 = COM2. (Note)

Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to
monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done
because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the
screen.
These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the
Parallel/Serial Idle Timer Count Register (F0 Index 9Ch).
Index 94h
7:0

Suspend Modulation OFF Count Register (R/W)

Reset Value = 00h

Suspend Signal Deasserted Count — This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin
will be deasserted to the processor. This counter, together with the Suspend Modulation ON Count Register (F0 Index
95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an
effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption.
This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video
speedups.

Index 95h
7:0

Suspend Modulation ON Count Register (R/W)

Reset Value = 00h

Suspend Signal Asserted Count — This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin will
be asserted. This counter, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the
Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective
(emulated) clock frequency, allowing the power manager to reduce CPU power consumption.
This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video
speedups.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 96h
7:2
1

Suspend Configuration Register (R/W)

Reset Value = 00h

Reserved
SMI Speedup Configuration — Selects how Suspend Modulation function reacts when an SMI occurs:
0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI
occurs.
1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register occurs.
(F1BAR0+I/O Offset 08h).
The goal of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA and
Power Management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into
the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI
handler reads the SMI Speedup Disable Register (F1BAR0+I/O Offset 08h). The latter is the preferred method. The IRQ
speedup method is provided for software compatibility with earlier revisions of the South Bridge module. This bit has no
affect if the Suspend Modulation feature is disabled (bit 0 = 0).

0

Suspend Modulation Feature Enable — Suspend Modulation feature: 0 = Disable; 1 = Enable.
When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation
OFF/ON Count Registers (F0 Index 94h/95h).
This bit setting is mirrored in the Top Level PME/SMI Status Register (F1BAR0+I/O Offset 00h/02h[15]. It is used by the
SMI handler to determine if the SMI Speedup Disable Register (F1BAR0+I/O Offset 08h) must be cleared on exit.

Index 97h
Index 98h-99h
15:0

Reserved
Primary Hard Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

Primary Hard Disk Idle Timer Count — This idle timer is used to determine when the hard disk is not in use so that it
can be powered down. The 16-bit value programmed here represents the period of hard disk inactivity after which the
system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the
configured hard disk’s data port (I/O Port 1F0h or 170h). The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[0] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[0].

Index 9Ah-9Bh
15:0

Floppy Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

Floppy Disk Idle Timer Count — This idle timer is used to determine when the floppy disk drive is not in use so that it
can be powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which
the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to
the configured floppy drive’s data port (I/O Port 3F5h or 375h). The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[1] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[1].

Index 9Ch-9Dh
15:0

Parallel / Serial Idle Timer Count Register (R/W)

Reset Value = 0000h

Parallel / Serial Idle Timer Count — This idle timer is used to determine when the parallel and serial ports are not in use
so that the ports can be power managed. The 16-bit value programmed here represents the period of inactivity for these
ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an
access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port
is not considered here. The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[2] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[2].

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index 9Eh-9Fh
15:0

Keyboard / Mouse Idle Timer Count Register (R/W)

Reset Value = 0000h

Keyboard / Mouse Idle Timer Count — This idle timer determines when the keyboard and mouse are not in use so that
the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity for these ports
after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an
access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space when
a mouse is enabled on a serial port. The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[3] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[3].

Index A0h-A1h
15:0

User Defined Device 1 Idle Timer Count Register (R/W)

Reset Value = 0000h

User Defined Device 1 (UDEF1) Idle Timer Count — This idle timer determines when the device configured as UDEF1
is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value
whenever an access occurs to memory or I/O address space configured in F0 Index C0h (base address register) and F0
Index CCh (control register). The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[4] = 1.
Top level SMI status is reported at F1BAR+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[4].

Index A2h-A3h
15:0

User Defined Device 2 Idle Timer Count Register (R/W)

Reset Value = 0000h

User Defined Device 2 (UDEF2) Idle Timer Count — This idle timer determines when the device configured as UDEF2
is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value
whenever an access occurs to memory or I/O address space configured in the F0 Index C4h (base address register) and
F0 Index CDh (control register). The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[5] = 1.
Top level SMI status is reported at F1BAR+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[5].

Index A4h-A5h
15:0

User Defined Device 3 Idle Timer Count Register (R/W)

Reset Value = 0000h

User Defined Device 3 (UDEF3) Idle Timer Count — This idle timer determines when the device configured as UDEF3
is not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value
whenever an access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index
C8h) and UDEF3 Control Register (F0 Index CEh). The counter uses a 1 second timebase.
To enable this timer set F0 Index 81h[6] = 1.
Top level SMI status is reported at F1BAR+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[6].

Index A6h-ABh

Reserved

Index ACh-ADh

Secondary Hard Disk Idle Timer Count Register (R/W)

15:0

Reset Value = 0000h

Secondary Hard Disk Idle Timer Count — This idle timer is used to determine when the hard disk is not in use so that
it can be powered down. The 16-bit value programmed here represents the period of hard disk inactivity after which the
system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the
configured hard disk’s data port (I/O Port 1F0h or 170h). The counter uses a 1 second timebase.
To enable this timer set F0 Index 83h[7] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[4].

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index AEh
7:0

CPU Suspend Command Register (WO)

Reset Value = 00h

Software CPU Suspend Command (Write Only) — If bit 0 in the Clock Stop Control Register is set low (F0 Index
BCh[0] = 0), a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power
state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt condition.
If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend.

Index AFh
7:0

Reset Value = 00h

Software CPU Stop Clock Suspend (Write Only) — A write to this register causes a SUSP#/SUSPA# handshake with
the CPU, placing the CPU in a low-power state.

Index B0h-B7h
Index B8h
7:0

Suspend Notebook Command Register (WO)

Reserved
DMA Shadow Register (RO)

Reset Value = xxh

DMA Shadow (Read Only) — This 8-bit port sequences through the following list of shadowed DMA Controller
registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A
write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last
data written to that location.
The read sequence for this register is:
1. DMA Channel 0 Mode Register
2. DMA Channel 1 Mode Register
3. DMA Channel 2 Mode Register
4. DMA Channel 3 Mode Register
5. DMA Channel 4 Mode Register
6. DMA Channel 5 Mode Register
7. DMA Channel 6 Mode Register
8. DMA Channel 7 Mode Register
9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)
10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 msec, all other bits are 0)

Index B9h
7:0

PIC Shadow Register (RO)

Reset Value = xxh

PIC Shadow (Read Only) — This 8-bit port sequences through the following list of shadowed Interrupt Controller
registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A
write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last
data written to that location.
The read sequence for this register is:
1. PIC1 ICW1
2. PIC1 ICW2
3. PIC1 ICW3
4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0
5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 ( See note below.)
6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1
7. PIC2 ICW1
8. PIC2 ICW2
9. PIC2 ICW3
10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0
11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)
12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1
Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register
value, then with the shadow register value ORed with C0h.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index BAh
7:0

PIT Shadow Register (RO)

Reset Value = xxh

PIT Shadow (Read Only) — This 8-bit port sequences through the following list of shadowed Programmable Interval
Timer registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through
it. A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the
last data written to that location.
The read sequence for this register is:
1. Counter 0 LSB (least significant byte)
2. Counter 0 MSB
3. Counter 1 LSB
4. Counter 1 MSB
5. Counter 2 LSB
6. Counter 2 MSB
7. Counter 0 Command Word
8. Counter 1 Command Word
9. Counter 2 Command Word
Note: The LSB/MSB of the count is the Counter base value, not the current value.
Bits [7:6] of the command words are not used.

Index BBh
7:0

Reset Value = xxh

RTC Index Shadow (Read Only) — The RTC Shadow register contains the last written value of the RTC Index register
(I/O Port 070h).

Index BCh
7:4

RTC Index Shadow Register (RO)

Clock Stop Control Register (R/W)

Reset Value = 00h

PLL Delay — The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the
SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU clock to stabilize before
starting execution. This delay is only invoked if the STP_CLK bit was set.
The four-bit field allows values from 0 to 15 msec.
0000 = 0 msec
0001 = 1 msec
0010 = 2 msec
0011 = 3 msec

3:1
0

0100 = 4 msec
0101 = 5 msec
0110 = 6 msec
0111 = 7 msec

1000 = 8 msec
1001 = 9 msec
1010 = 10 msec
1011 = 11 msec

Reserved
CPU Clock Stop — 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.

Index BDh-BFh

Reserved

Index C0h-C3h

User Defined Device 1 Base Address Register (R/W)

31:0

Reset Value = 00000000h

User Defined Device 1 (UDEF1) Base Address [31:0] — This 32-bit register supports power management (trap and
idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address
comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh). The
South Bridge module can not snoop addresses on the Front-PCI bus unless the South Bridge module actually claims the
cycle. Therefore, traps and idle timers can not support power management of devices on the Front-PCI bus.

Index C4h-C7h
31:0

1100 = 12 msec
1101 = 13 msec
1110 = 14 msec
1111 = 15 msec

User Defined Device 2 Base Address Register (R/W)

Reset Value = 00000000h

User Defined Device 2 (UDEF2) Base Address [31:0] — This 32-bit register supports power management (trap and
idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address
comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh). The
South Bridge module can not snoop addresses on the Front-PCI bus unless the South Bridge module actually claims the
cycle. Therefore, traps and idle timers can not support power management of devices on the Front-PCI bus.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index C8h-CBh
31:0

User Defined Device 3 Base Address Register (R/W)

Index CCh
7
6:0

Reset Value = 00000000h

User Defined Device 3 (UDEF3) Base Address [31:0] — This 32-bit register supports power management (trap and
idle timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address
comparator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh). The
South Bridge module can not snoop addresses on the Front-PCI bus unless the South Bridge module actually claims the
cycle. Therefore, traps and idle timers can not support power management of devices on the Front-PCI bus.
User Defined Device 1 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped — User Defined Device 1 is: 0 = I/O; 1 = Memory.
Mask
If bit 7 = 0 (I/O):
Bit 6

0 = Disable write cycle tracking
1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking
1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (Memory):
Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.

Note: A "1" in a mask bit means that the address bit is ignored for comparison.
Index CDh
7
6:0

User Defined Device 2 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped — User Defined Device 2 is: 0 = I/O; 1 = Memory.
Mask
If bit 7 = 0 (I/O):
Bit 6

0 = Disable write cycle tracking
1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking
1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (Memory):
Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.

Note: A "1" in a mask bit means that the address bit is ignored for comparison.
Index CEh
7
6:0

User Defined Device 3 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped — User Defined Device 3 is: 0 = I/O; 1 = Memory.
Mask
If bit 7 = 0 (I/O):
Bit 6

0 = Disable write cycle tracking
1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking
1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (Memory):
Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.

Note: A "1" in a mask bit means that the address bit is ignored for comparison.
Index CFh

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit

Description

Index D0h
7:0

Index D1h-EBh
Index ECh
7:0

Software SMI Register (WO)

Reset Value = 00h

Software SMI (Write Only) — A write to this location generates an SMI. The data written is irrelevant. This register
allows software entry into SMM via normal bus access instructions.
Reserved
Timer Test Register (R/W)

Reset Value = 00h

Timer Test Value — The Timer Test Register is intended only for test and debug purposes. It is not intended for setting
operational timebases.

Index EDh-F4h
Index F5h

Reserved
Second Level PME/SMI Status Register 2 (RC, see Note)

Reset Value = 00h

7

Reserved

6

User Defined Device3 Idle Timer (UDEF3) SMI Status (Read to Clear) — Was SMI caused by expiration of UDEF3
Idle Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[6] = 1.

5

User Defined Device 2 Idle Timer (UDEF2) SMI Status (Read to Clear) — Was SMI caused by expiration of UDEF2
Idle Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[5] = 1.

4

User Defined Device Idle 1 Timer (UDEF1) SMI Status (Read to Clear) — Was SMI caused by expiration of UDEF1
Idle Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[4] = 1.

3

Keyboard/Mouse SMI Status Idle Timer (Read to Clear) — Was SMI caused by expiration of Keyboard/Mouse Idle
Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[3] = 1.

2

Parallel/Serial SMI Status Idle Timer (Read to Clear) — Was SMI caused by expiration of Parallel/Serial Port Idle
Timer Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[2] = 1.

1

Floppy Disk SMI Status Idle Timer (Read to Clear) — Was SMI caused by expiration of Floppy Disk Idle Timer Count
Register (F0 Index 9Ah)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[1] = 1.

0

Primary Hard Disk SMI Status Idle Timer (Read to Clear) — Was SMI caused by expiration of Primary Hard Disk Idle
Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 81h[0] = 1.

Note: This is the second level of status reporting. The top level status is reported at F1BAR0+I/O Offset 00h/02h[0]. If any SMI
source described in Index F5h occurs, then bit 0 – SMI Source is Power Management Event of F1BAR+I/O Offset 00h/02h
sets. Reading register F5h clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 85h. If the value of the register must be read without clearing
the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead.
Index F6h
7:6
5

Second Level PME/SMI Status Register 3 (RC, see Note)

Reset Value = 00h

Reserved
Secondary Hard Disk Access Trap SMI Status (Read to Clear) — Was SMI caused by a trapped I/O access to the
secondary hard disk? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[6] = 1.

4

Secondary Hard Disk Idle Timer SMI Status (Read to Clear) — Was SMI caused by expiration of Hard Disk Idle Timer
Count Register (F0 Index ACh)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[7] = 1.

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Table 4.30 F0 Index xxh: PCI Header and Bridge Configuration Registers (cont.)
Bit
3

Description
Keyboard/Mouse Access Trap SMI Status (Read to Clear) — Was SMI caused by a trapped I/O access to the
keyboard or mouse? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[3] = 1.

2

Parallel/Serial Access Trap SMI Status (Read to Clear) — Was SMI caused by a trapped I/O access to either the
serial or parallel ports? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[2] = 1.

1

Floppy Disk Access Trap SMI Status (Read to Clear) — Was SMI caused by a trapped I/O access to the floppy disk?
0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[1] = 1.

0

Primary Hard Disk Access Trap SMI Status (Read to Clear) — Was SMI caused by a trapped I/O access to the
primary hard disk? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[0] = 1.

Note: This is the second level of status reporting. The top level status is reported at F1BAR0+I/O Offset 00h/02h[0]. If any SMI
source described in Index F6h occurs, then bit 0 – SMI Source is Power Management Event of F1BAR+I/O Offset 00h/02h
sets. Reading register F6h clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 86h. If the value of the register must be read without clearing
the SMI source (and consequently deasserting SMI), F0 Index 86h may be read instead.
Index F7h
7

Second Level PME/SMI Status Register 4 (RO/RC, see Note)

Reset Value = 00h

GPIO Event SMI Status (Read Only, Read does not Clear) — Was SMI caused by a transition of any of the GPIOs? 0 =
No; 1 = Yes.
Note that F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME. In addition, the selected
GPIO must be enabled as an input (F0BAR0+I/O Offset 20h and 24h).
The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch.

6:4
3

Reserved
SIO PWUREQ SMI Status (Read to Clear) — Was SMI caused by a power-up event from the SIO?
0 = No; 1 = Yes.
A power-up event is defined as any of the following events/activity: Modem, Telephone, Keyboard, Mouse, CEIR
(Consumer Electronic Infrared).

2

Reserved

1

Reserved

0

Reserved

Note: This is the second level of status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[0]. If any SMI source
described in Index F7h occurs, then bit 0 – SMI Source is Power Management Event of F1BAR+I/O Offset 00h/02h sets.
Reading register F7h clears the status at both the second and top levels except for bit 7 which has a third level of status
reporting at F0BAR0+I/O 0Ch/1Ch.
A read-only “Mirror” version of this register exists at F0 Index 87h. If the value of the register must be read without clearing
the SMI source (and consequently deasserting SMI), F0 Index 87h may be read instead.
Index F8h-FFh

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4.4.3.2. GPIO Support Registers
F0 Index 10h, Base Address Register 0
(F0BAR0) points to the base address of where

the GPIO runtime and configuration registers
are located. Table 4.31 gives the bit formats of
the I/O mapped registers accessed through
F0BAR0.

Table 4.31 F0BAR0+I/O Offset xxh: GPIO Runtime and Configuration Registers
Bit
Offset 00h

GPDO0 — GPIO Data Out 0 Register (R/W)

Reset Value = FFFFFFFFh

31:8

Reserved

7:0

GPIO Data Out — Bits [7:0] correspond to GPIO7-GPIO0 pins, respectively. The value of each bit determines the
value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data
unless the bit is locked by the GPIO Configuration Register Lock Bit (F0BAR0+I/O Offset 24h[3]). Reading the bit
returns the value, regardless of the pin value and configuration.
0 = Corresponding GPIO pin driven to low when output enabled.
1 = Corresponding GPIO pin driven or released to high (according to buffer type and static pull-up selection) when
output enabled.

Offset 04h

GPDI0 — GPIO Data In 0 Register (RO)

Reset Value = FFFFFFFFh

31:8

Reserved

7:0

GPIO Data In (Read Only) — Bits [7:0] correspond to GPI07-GPIO0 pins, respectively. Reading each bit returns the
value of the corresponding GPIO pin, regardless of the pin configuration and the GPDO0 Register value. Writes are
ignored.
0 = Corresponding GPIO pin level low; 1 = Corresponding GPIO pin level high.

Offset 08h

GPIEN0 — GPIO Interrupt Enable 0 Register (R/W)

Reset Value = 00000000h

31:8

Reserved

7:0

GPIO Power Management Event (PME) Enable — Bits [7:0] correspond to GPIO7-GPIO0 pins, respectively. Each bit
allows PME generation by the corresponding GPIO pin.
0 = Disable PME generation; 1 = Enable PME generation.
Note: The individually selected GPIO PMEs generate an SMI and the status is reported at F1BAR0+I/O Offset
00h/02h[0].

Offset 0Ch

GPST0 — GPIO Status 0 Register (R/W1C)

Reset Value = 00000000h

31:8

Reserved

7:0

GPIO Status — Bits [7:0] correspond to GPIO7-GPIO0 pins, respectively. Each bit reports a 1 when the hardware
detects the edge (rising/falling on the GPIO pin) programmed in F0BAR0+I/O Offset 24h[5]. If the corresponding bit in
F0BAR0+I/O Offset 08h is set, this edge generates a PME.
0 = No active edge detected since last cleared; 1 = Active edge detected.
Note: Writing a 1 FOLLOWED by reading the Status bit clears it to 0.
This is the third level of SMI status reporting to the second level at F0 Index 87h/F7h[7] and the top level at
F1BAR0+I/O Offset 00h/02h[0]. Clearing the third level also clears the second and top levels.

Offset 10h-1Fh
Offset 20h
31:6
5

Reserved
GPIO Pin Configuration Select Register (R/W)

Reset Value = 00000000h

Reserved
Bank Select — Selects the GPIO bank to be configured: 0 = Bank 0 for GPIO0-GPIO7 pins.

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Table 4.31 F0BAR0+I/O Offset xxh: GPIO Runtime and Configuration Registers (cont.)
Bit
4:0

Pin Select — Selects the GPIO pin to be configured in the Bank selected via bit 5 setting (that is, Bank 0).
If bit 5 = 0; Bank 0
00000 = GPIO0
00001 = GPIO1
00010 = GPIO2
00011 = GPIO3
00100 = GPIO4
00101 = GPIO5
00110 = GPIO6
00111 = GPIO7

Offset 24h
31:7

GPIO Pin Configuration Access Register (R/W)

Reset Value = 00000044h

Reserved

6

PME Debounce Enable — Enables/disables IRQ debounce (debounce period = 16 ms):
0 = Disable; 1 = Enable.

5

PME Polarity — Selects the polarity of the signal that issues a PME from the corresponding GPIO pin (falling/low or
rising/high): 0 = Falling edge or low level input. 1 = Rising edge or high level input.

4

PME Edge/Level Select — Selects the type (edge or level) of the signal that issues a PME from the corresponding
GPIO pin: 0 = Edge input; 1 = Level input.

3

Lock — This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by
system reset or power-off. 0 = No effect (Default); 1 = Direction, output type, pull-up and output value locked.

2

Pull-Up Control — Enables/disables the internal pull-up capability of the corresponding GPIO pin. It supports opendrain output signals with internal pull-ups and TTL input signals. 0 = Disable; 1 = Enable (Default).

For normal operation always set this bit to 0 (edge input). Erratic system behavior will result if this bit is set to 1.

Bits [1:0] must = 01 for this bit to have effect.
1

Output Type — Controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.
0 = Open-drain (Default); 1 = Push-pull
Bit 0 must = 1 for this bit to have effect.

0

Output Enable — Indicates the GPIO pin output state. It has no effect on input.
0 = TRI-STATE (Default); 1 = Output enabled.

Offset 28h
31:1
0

GPIO Reset Control Register (R/W)

Reset Value = 00000000h

Reserved
GPIO Reset — Reset the GPIO logic: 0 = Disable; 1 = Enable.
Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled (normal operation requires this
bit to be 0).

4.4.3.3. SMI Status Registers - Function

pointing to the register spaces designated for
SMI Status, described later in this section.

The register space designated as Function 1
(F1) is used to configure the PCI portion of
support hardware for the SMI Status Registers. The bit formats for the PCI Header Registers are given in Table 4.32.
Located in the PCI Header Registers of F1 is
Base Address Register (F1BAR0) used for

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Table 4.32 F1 Index xxh: PCI Header Registers for SMI Status
Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0401h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:1
0

Reserved
I/O Space — Allow South Bridge module to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable.
This bit must be enabled to access I/O offsets through F1BAR0 (see F1 Index 10h).

Index 06h-07h
Index 08h

PCI Status Register (RO)
Device Revision ID Register (RO)

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 0280h
Reset Value = 00h
Reset Value = 000000h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value = 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value = 00h

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

Index 10h-13h

Base Address Register 0 - F1BAR0 (R/W)

Reset Value = 00000001h

This register allows access to I/O mapped SMI status related registers. Bits [7:0] are read only (0000 0001), indicating a 256-byte
I/O address range. Refer to Table 4.33 for the SMI status registers bit formats and reset values.
31:8

SMI Status Base Address

7:0

Address Range (Read Only)

Index 14h-2Bh

Reserved

Index 2Ch-2Dh

Subsystem Vendor ID (RO)

Reset Value = 1078h

Index 2Eh-2Fh

Subsystem ID (RO)

Reset Value = 0401h

Index 30h-FFh

Reserved

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4.4.3.4. SMI Status Support Registers
F1 Index 10h, Base Address Register 0
(F1BAR0), points to the base address of
where the SMI Status Registers are located.
Table 4.33 gives the bit formats of I/O mapped
SMI Status Registers accessed through
F1BAR0.

Note: The registers at F1BAR0+I/O Offset
50h-can also be accessed F0 Index
50h-FFh. The preferred method is to
program these registers through the F0
register space.

Table 4.33 F1BAR0+I/O Offset xxh: SMI Status Registers
Bit

Description

Offset 00h-01h
15

14

Top Level PME/SMI Status Mirror Register (RO, see Note)

Reset Value = 0000h

Suspend Modulation Enable Mirror (Read Only) — This bit mirrors the Suspend Mode Configuration bit (F0 Index
96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR0+I/O Offset 08h) must
be cleared on exit.
SMI Source is USB (Read Only) — Was SMI caused by USB activity? 0 = No; 1 = Yes.
To enable SMI generation set F5BAR0+I/O Offset 00h[20:19] = 11.

13

SMI Source is Warm Reset Command (Read Only) — Was SMI caused by Warm Reset command? 0 = No; 1 = Yes.

12

Reserved.

11

SMI Source is SIO (Read Only) — Was SMI caused by SIO? 0 = No; 1 = Yes.
The next level (second level) of SMI status is reported in the SIO module.

10

SMI Source is EXT_SMI[7:0] (Read Only) — Was SMI caused by a negative-edge event on EXT_SMI[7:0]?
0 = No; 1 = Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 24h[23:8].

9

SMI Source is GP Timer/UDEF/PCI/ISA Function Trap (Read Only) — Was SMI caused by expiration of GP Timer
1/2, trapped access to UDEF3/2/1, and/or trapped access to F1-F3 or ISA Legacy Register Space? 0 = No; 1 = Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 04h/06h.

8

SMI Source is Software Generated (Read Only) — Was SMI caused by software? 0 = No; 1 = Yes.

7

SMI on an A20M# Toggle (Read Only) — Was SMI caused by an access to either Port 92h or the keyboard command
which initiates an A20M# SMI? 0 = No; 1 = Yes.
This method of controlling the internal A20M# in the processor is used instead of a pin.
To enable SMI generation set F0 Index 53h[0] = 1.

6:1
0

Reserved
SMI Source is Power Management Event (Read Only) — Was SMI caused by one of the power management
resources (except for the GP Timers, UDEF, and PCI/ISA Function traps that are reported in bit 9): 0 = No; 1 = Yes.
The next level (second level) of SMI status is at F0 Index 84h/F4h and 87h/F7h.

Note: Reading this register does not clear the status bits. See F1BAR0+I/O Offset 02h.
Offset 02h-03h

Top Level PME/SMI Status Register (RO/RC, see Note)

Reset Value = 0000h

15

Suspend Modulation Enable Mirror (Read to Clear) — This bit mirrors the Suspend Mode Configuration bit (F0
Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR0+I/O Offset
08h) must be cleared on exit.

14

SMI Source is USB (Read to Clear) — Was SMI caused by USB activity? 0 = No; 1 = Yes.
To enable SMI generation set F5BAR0+I/O Offset 00h[20:19] = 11.

13

SMI Source is Warm Reset Command (Read to Clear) — Was SMI caused by Warm Reset command?
0 = No; 1 = Yes.

12

SMI Source is NMI (Read to Clear) — Was SMI caused by NMI activity? 0 = No; 1 = Yes.

11

SMI Source is SIO (Read to Clear) — Was SMI caused by SIO? 0 = No; 1 = Yes.
The next level (second level) of SMI status is reported in the SIO module.

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Table 4.33 F1BAR0+I/O Offset xxh: SMI Status Registers (cont.)
Bit

Description

10

SMI Source is EXT_SMI[7:0] (Read to Clear in Rev A and Read Only, Read does not Clear in Rev B) — Was SMI
caused by a negative-edge event on EXT_SMI[7:0]? 0 = No; 1 = Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 24h[23:8].

9

SMI Source is General Timers/Traps (Read Only, Read does not Clear) — Was SMI caused by the expiration of
one of the General Purpose Timers or one of the User Defined Traps? 0 = No; 1 = Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 04h/06h.

8

SMI Source is Software Generated (Read to Clear) — Was SMI caused by software? 0 = No; 1 = Yes.

7

SMI on an A20M# Toggle (Read to Clear) — Was SMI caused by an access to either Port 92h or the keyboard
command which initiates an A20M# SMI? 0 = No; 1 = Yes.
This method of controlling the internal A20M# in the processor is used instead of a pin.
To enable SMI generation set F0 Index 53h[0] = 1.

6:1
0

Reserved
SMI Source is Power Management Event (Read Only, Read does not Clear) — Was SMI caused by one of the
power management resources (except for the GP Timers, UDEF, and PCI/ISA Function traps are reported in bit 9):
0 = No; 1 = Yes.
The next level (second level) of SMI status is at F0 Index 84h/F4h-87h/F7h.

Note: Reading this register clears all the SMI status bits except for the "read only" bits because they have a second level of status
reporting. Clearing the second level status bits also clears the top level with the exception of GPIOs. GPIO SMIs have a
third level of SMI status reporting at F0BAR0+I/O Offset 0Ch/1Ch. Clearing the third level GPIO status bits also clears the
second and top levels.
A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 00h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F1BAR0+I/O Offset 00h may be read instead.
Offset 04h-05h
15:6
5

Second Level General Traps & Timers
PME/SMI Status Mirror Register (RO, See Note)

Reset Value = 0000h

Reserved
PCI/ISA Function Trap (Read Only) — Was SMI caused by a trapped PCI/ISA configuration cycle? 0 = No; 1 = Yes.
To enable SMI generation for:
Trapped access to ISA Legacy I/O register space set F0 Index 41h[0] = 1.
Trapped access to F1 register space set F0 Index 41h[1] = 1.
Trapped access to F2 register space set F0 Index 41h[2] = 1.
Trapped access to F3 register space set F0 Index 41h[3] = 1.

4

SMI Source is Trapped Access to User Defined Device 3 (Read Only) — Was SMI caused by a trapped I/O or
memory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[6] = 1.

3

SMI Source is Trapped Access to User Defined Device 2 (Read Only) — Was SMI caused by a trapped I/O or
memory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[5] = 1.

2

SMI Source is Trapped Access to User Defined Device 1 (Read Only) — Was SMI caused by a trapped I/O or
memory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[4] = 1.

1

SMI Source is Expired General Purpose Timer 2 (Read Only) — Was SMI caused by the expiration of General
Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[1] = 1.

0

SMI Source is Expired General Purpose Timer 1 (Read Only) — Was SMI caused by the expiration of General
Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[0] = 1.

Note: This is the second level of status reporting. The top level status is reported at F1BAR0+I/O Offset 00h/02h[9]. Reading this
register does not clear the SMI. See F1BAR0+I/O Offset 06h.

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Table 4.33 F1BAR0+I/O Offset xxh: SMI Status Registers (cont.)
Bit

Description

Offset 06h-07h
15:6

Second Level General Traps & Timers
PME/SMI Status Register (RC, see Note)

Reset Value = 0000h

Reserved

5

PCI/ISA Function Trap (Read to Clear) — Was SMI caused by a trapped PCI/ISA configuration cycle?
0 = No; 1 = Yes.
Trapped Access to ISA Legacy I/O register space; to enable SMI generation set F0 Index 41h[0] = 1.
Trapped Access to F1 register space; to enable SMI generation set F0 Index 41h[1] = 1.
Trapped Access to F2 register space; to enable SMI generation set F0 Index 41h[2] = 1.
Trapped Access to F3 register space; to enable SMI generation set F0 Index 41h[3] = 1.

4

SMI Source is Trapped Access to User Defined Device 3 (Read to Clear) — Was SMI caused by a trapped I/O or
memory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[6] = 1.

3

SMI Source is Trapped Access to User Defined Device 2 (Read to Clear) — Was SMI caused by a trapped I/O or
memory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[5] = 1.

2

SMI Source is Trapped Access to User Defined Device 1 (Read to Clear) — Was SMI caused by a trapped I/O or
memory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 82h[4] = 1.

1

SMI Source is Expired General Purpose Timer 2 (Read to Clear) — Was SMI caused by the expiration of General
Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[1] = 1.

0

SMI Source is Expired General Purpose Timer 1 (Read to Clear) — Was SMI caused by the expiration of General
Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes.
To enable SMI generation set F0 Index 83h[0] = 1.

Note: This is the second level of status reporting. The top level status is reported in F1BAR0+I/O Offset 00h/02h[9]. Reading this
register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 04h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), F1BAR0+I/O Offset 04h may be read instead.
Offset 08h-09h
15:0

SMI Speedup Disable Register (Read to Enable)

Reset Value = 0000h

SMI Speedup Disable — If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this
register invokes the SMI handler to re-enable Suspend Modulation.
The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location
has no effect.

Offset 0Fh-1Bh

Reserved

Offset 1Ch-1Fh

Reserved

Offset 20h-21h

Reserved

Offset 22h-23h

Reserved

Offset 24h-27h

Reserved

Offset 28h-4Fh

Not Used

Offset
50h-FFh

The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) can also be accessed at F0 Index 50h-FFh. The
preferred method is to program these register through the F0 register space.

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4.4.3.5. IDE Controller Registers - Function 2
The register space designated as Function 2
(F2) is used to configure Channels 0 and 1
and the PCI portion of support hardware for
the IDE controllers. The bit formats for the PCI
Header/Channels 0 and 1 Registers are given
in Table 4.34.

Located in the PCI Header Registers of F2 is a
Base Address Register (F2BAR4) used for
pointing to the register space designated for
support of the IDE controllers, described later
in this section.

Table 4.34 F2 Index xxh: PCI Header/Channels 0 & 1 Registers for
IDE Controller Config
Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0402h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:3
2

Reserved
Bus Master — Allow the South Bridge module bus mastering capabilities: 0 = Disable; 1 = Enable (Default).
This bit must be set to 1.

1
0

Reserved
I/O Space — Allow South Bridge module to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable.
This bit must be enabled to access I/O offsets through F2BAR4 (see F2 Index 20h).

Index 06h-07h
Index 08h
Index 09h-0Bh

PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)

Reset Value = 0280h
Reset Value = 01h
Reset Value = 010180h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value = 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value = 00h

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

Index 10h-13h

Base Address Register 0 - F2BAR0 (RO)

Reset Value = 00000000h

Reserved — Reserved for possible future use by the South Bridge module.
Index 14h-17h

Base Address Register 1 - F2BAR1 (RO)

Reset Value = 00000000h

Reserved — Reserved for possible future use by the South Bridge module.
Index 18h-1Bh

Base Address Register 2 - F2BAR2 (RO)

Reset Value = 00000000h

Reserved — Reserved for possible future use by the South Bridge module.

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Table 4.34 F2 Index xxh: PCI Header/Channels 0 & 1 Registers for
IDE Controller Config
Bit

Description

Index 1Ch-1Fh

Base Address Register 3 - F2BAR3 (RO)

Reset Value = 00000000h

Reserved — Reserved for possible future use by the South Bridge module.
Index 20h-23h

Base Address Register 4 - F2BAR4 (R/W)

Reset Value = 00000001h

Base Address 0 Register — This register allows access to I/O mapped Bus Mastering IDE registers. Bits [3:0] are read only
(0001), indicating a 16-byte I/O address range. Refer to Table 4.35 for the IDE controller registers bit formats and reset values.
31:4

Bus Mastering IDE Base Address

3:0

Address Range (Read Only)

Index 24h-2Bh

Reserved

Index 2Ch-2Dh

Subsystem Vendor ID (RO)

Reset Value = 1078h

Index 2Eh-2Fh

Subsystem ID (RO)

Reset Value = 0402h

Index 30h-3Fh

Reserved

Index 40h-43h

Channel 0 Drive 0 PIO Register (R/W)

Reset Value = 00009172h

If Index 44h[31] = 0, Format 0 — Selects slowest PIOMODE per channel for commands.
Format 0 settings for: PIO Mode 0 = 00009172h
PIO Mode 1 = 00012171h
PIO Mode 2 = 00020080h
PIO Mode 3 = 00032010h
PIO Mode 4 = 00040010h
31:20

Reserved

19:16

PIOMODE — PIO mode

15:12

t2I — Recovery time (value + 1 cycle)

11:8

t3 — IDE_IOW# data setup time (value + 1 cycle)

7:4

t2W — IDE_IOW# width minus t3 (value + 1 cycle)

3:0

t1 — Address Setup Time (value + 1 cycle)

If Index 44h[31] = 1, Format 1 — Allows independent control of command and data.
Format 1 settings for: PIO Mode 0 = 9172D132h
PIO Mode 1 = 21717121h
PIO Mode 2 = 00803020h
PIO Mode 3 = 20102010h
PIO Mode 4 = 00100010h
31:28

t2IC — Command cycle recovery time (value + 1 cycle)

27:24

t3C — Command cycle IDE_IOW# data setup (value + 1 cycle)

23:20

t2WC — Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle)

19:16

t1C — Command cycle address setup time (value + 1 cycle)

15:12

t2ID — Data cycle recovery time (value + 1 cycle)

11:8

t3D — Data cycle IDE_IOW# data setup (value + 1 cycle)

7:4

t2WD — Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle)

3:0

t1D — Data cycle address Setup Time (value + 1 cycle)

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Table 4.34 F2 Index xxh: PCI Header/Channels 0 & 1 Registers for
IDE Controller Config
Bit

Description

Index 44h-47h

Channel 0 Drive 0 DMA Control Register (R/W)

Reset Value = 00077771h

If bit 20 = 0, Multiword DMA
Settings for: Multiword DMA Mode 0 = 00077771h
Multiword DMA Mode 1 = 00012121h
Multiword DMA Mode 2 = 00002020h
31
30:21
20

PIO Mode Format — 0 = Format 0; 1 = Format 1
Reserved
DMA Select — DMA operation: 0 = Multiword DMA, 1 = Ultra DMA.

19:16

tKR — IDE_IOR# recovery time (4-bit) (value + 1 cycle)

15:12

tDR — IDE_IOR# pulse width (value + 1 cycle)

11:8

tKW — IDE_IOW# recovery time (4-bit) (value + 1 cycle)

7:4

tDW — IDE_IOW# pulse width (value + 1 cycle)

3:0

tM — IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1#

If bit 20 = 1, Ultra DMA
Settings for: Ultra DMA Mode 0 = 00921250h
Ultra DMA Mode 1 = 00911140h
Ultra DMA Mode 2 = 00911030h
31
30:21
20

PIO Mode Format — 0 = Format 0; 1 = Format 1
Reserved
DMA Select — DMA operation: 0 = Multiword DMA, 1 = Ultra DMA.

19:16

tCRC — CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS)

15:12

tSS — UDMA out (value + 1 cycle)

11:8

tCYC — Data setup and cycle time UDMA out (value + 2 cycles)

7:4

tRP — Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock.

3:0

tACK — IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle)

Index 48h-4Bh

Channel 0 Drive 1 PIO Register (R/W)

Reset Value = 00009172h

Channel 0 Drive 1 Programmed I/O Control Register — Refer to F2 Index 40h for bit descriptions.
Index 4Ch-4Fh

Channel 0 Drive 1 DMA Control Register (R/W)

Reset Value = 00077771h

Channel 0 Drive 1 MDMA/UDMA Control Register — See F2 Index 44h for bit descriptions.
Note: Once the PIO Mode Format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved, read only.
Index 50h-53h

Channel 1 Drive 0 PIO Register (R/W)

Reset Value = 00009172h

Channel 1 Drive 0 Programmed I/O Control Register — Refer to F2 Index 40h for bit descriptions.
Index 54h-57h

Channel 1 Drive 0 DMA Control Register (R/W)

Reset Value = 00077771h

Channel 1 Drive 0 MDMA/UDMA Control Register — See F2 Index 44h for bit descriptions.
Note: Once the PIO Mode Format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved, read only.
Index 58h-5Bh

Channel 1 Drive 1 PIO Register (R/W)

Reset Value = 00009172h

Channel 1 Drive 1 Programmed I/O Control Register — Refer to F2 Index 40h for bit descriptions.

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Table 4.34 F2 Index xxh: PCI Header/Channels 0 & 1 Registers for
IDE Controller Config
Bit

Description

Index 5Ch-5Fh

Channel 1 Drive 1 DMA Control Register (R/W)

Reset Value = 00077771h

Channel 1 Drive 1 MDMA/UDMA Control Register — See F2 Index 44h for bit descriptions.
Note: Once the PIO Mode Format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved, read only.
Index 60h-FFh

Reserved

4.4.3.6. IDE Controller Support Registers
F2 Index 20h, Base Address Register 4
(F2BAR4), points to the base address of
where the registers for IDE controller configuration are located. Table 4.35 gives the bit
formats of the I/O mapped IDE Controller
Configuration Registers accessed through
F2BAR4.

Note: For proper operation the register must
be read before the Bus Master Control
at F2BAR4+0h is cleared, else the
status may be lost.

Table 4.35 F2BAR4+I/O Offset xxh: IDE Controller Configuration Registers
Bit

Description

Offset 00h
7:4
3

IDE Bus Master 0 Command Register — Primary (R/W)

Reset Value = 00h

Reserved — Set to 0. Must return 0 on reads.
Read or Write Control — Sets the direction of bus master transfers: 0 = PCI reads performed;
1 = PCI writes performed.
This bit should not be changed when the bus master is active.

2:1
0

Reserved— Set to 0. Must return 0 on reads.
Bus Master Control — Controls the state of the bus master: 0 = Disable master; 1 = Enable master
Hault bus master operationsn by setting bit 0 to 0. Once an operation halts, it can not be resumed. If bit 0 is set to 0
while a bus master operation is active, the command aborts and the data transferred from the drive is discarded. This
bit should be reset after completion of data transfer.

Offset 01h

Reserved

Offset 02h

IDE Bus Master 0 Status Register — Primary (R/W)

Reset Value = 00h

7

Simplex Mode (Read Only) — Can both the primary and secondary channel operate independently?
0 = Yes; 1 = No (simplex mode)

6

Drive 1 DMA Capable — Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable.

5
4:3
2

Drive 0 DMA Capable — Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable.
Reserved — Set to 0. Must return 0 on reads.
Bus Master Interrupt — Has the bus master detected an interrupt? 0 = No; 1 = Yes.
Write 1 to clear.

1

Bus Master Error — Has the bus master detected an error during data transfer? 0 = No; 1 = Yes.
Write 1 to clear.

0

Bus Master Active — Is the bus master active? 0 = No; 1 = Yes.

Offset 03h

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Reserved

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Table 4.35 F2BAR4+I/O Offset xxh: IDE Controller Configuration Registers
Bit

Description

Offset 04h-07h
31:2

IDE Bus Master 0 PRD Table Address — Primary (R/W)

Reset Value = 00000000h

Pointer to the Physical Region Descriptor Table — This register is a PRD table pointer for IDE Bus Master 0.
When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command
Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.
When read, this register points to the next PRD.
Note: Entries in the PRD must be 32 byte aligned.

1:0

Reserved — Set to 0.

Offset 08h
7:4
3

IDE Bus Master 1 Command Register — Secondary (R/W)

Reset Value = 00h

Reserved — Set to 0. Must return 0 on reads.
Read or Write Control — Sets the direction of bus master transfers: 0 = PCI reads performed;
1 = PCI writes performed.
This bit should not be changed when the bus master is active.

2:1
0

Reserved — Set to 0. Must return 0 on reads.
Bus Master Control — Controls the state of the bus master: 0 = Disable master; 1 = Enable master
Hault bus master operations by setting bit 0 to 0. Once an operation halts, it can not be resumed. If bit 0 is set to 0
while a bus master operation is active, the command aborts and the data transferred from the drive is discarded. This
bit should be reset after completion of data transfer.

Offset 09h

Reserved

Offset 0Ah

IDE Bus Master 1 Status Register — Secondary (R/W)

Reset Value = 00h

7

Simplex Mode — Can both the primary and secondary channel operate independently? 0 = Yes;
1 = No (simplex mode).

6

Drive 1 DMA Capable — Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable.

5
4:3
2

Drive 0 DMA Capable — Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable.
Reserved — Set to 0. Must return 0 on reads.
Bus Master Interrupt — Has the bus master detected an interrupt? 0 = No; 1 = Yes.
Write 1 to clear.

1

Bus Master Error — Has the bus master detected an error during data transfer? 0 = No; 1 = Yes.
Write 1 to clear.

0

Bus Master Active — Is the bus master active? 0 = No; 1 = Yes.

Offset 0Bh

Reserved

Offset 0Ch-0Fh
31:2

IDE Bus Master 1 PRD Table Address — Secondary (R/W)

Reset Value = 00000000h

Pointer to the Physical Region Descriptor Table — This register is a PRD table pointer for IDE Bus Master 1.
When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command
Register bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.
When read, this register points to the next PRD.
Note: Entries in the PRD must be 32 byte aligned.

1:0

Reserved — Set to 0.

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4.4.3.7. XBus Expansion - Function 3
The register space designated as Function 3
(F3) is used to configure the PCI portion of
support hardware for accessing the XBus
Expansion support registers. The bit formats
for the PCI Header Registers are given in
Table 4.36.

Located in the PCI Header Registers of F3 are
five Base Address Registers (F3BARx) used
for pointing to the register spaces designated
for XBus Expansion, described later in this
section.

Table 4.36 F3 Index xxh: PCI Header Registers for XBus Expansion
Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0403h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:2
1

Reserved (Read Only)
Memory Space — Allow South Bridge module to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable.
If any of F3BAR1, F3BAR2, F3BAR3, F3BAR4, or F3BAR5 (see F3 Index 10h, 14h, 18h, 1Ch, 20h, 24h) are defined as
allowing access to memory mapped registers, this bit must be set to 1. BAR configuration is programmed through the
corresponding mask register (see F3 Index 40h, 44h, 48h, 4Ch, 50h, and 54h).

0

I/O Space — Allow South Bridge module to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable.
This bit must be enabled to access I/O offsets through F3BAR0 (see F3 Index 10h).
If any of F3BAR1, F3BAR2, F3BAR3, F3BAR4, or F3BAR5 (see F3 Index 10h, 14h, 18h, 1Ch, 20h, 24h) are defined
as allowing access to I/O mapped registers, this bit must be set to 1. BAR configuration is programmed through the
corresponding mask register (see F3 Index 40h, 44h, 48h, 4Ch, 50h, and 54h).

Index 06h-07h

PCI Status Register (RO)

Index 08h

Device Revision ID Register (RO)

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 0280h
Reset Value = 00h
Reset Value = 000000h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value = 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value = 00h

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

Index 10h-13h

Base Address Register 0 - F3BAR0 (R/W)

Reset Value = 00000000h

XBus Expansion Address Space — This register allows PCI access to I/O mapped XBus Expansion registers. Bits [5:0] must be
set to 000001, indicating a 64-byte aligned I/O address space. Refer to Table 4.36 for the XBus Expansion configuration registers
bit formats and reset values.
Note: The size and type of accessed offsets can be re-programmed through F3BAR0 Mask Register (F3 Index 40h).
31:6

XBus Expansion Base Address

5:0

Address Range — These bits must be set to 000001 for this register operate correctly.

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Table 4.36 F3 Index xxh: PCI Header Registers for XBus Expansion
Bit

Description

Index 14h-17h

Base Address Register 1 - F3BAR1 (R/W)

Reset Value = 00000000h

Reserved— Reserved for possible future use by the South Bridge module.
Configuration of this register is programmed through the F3BAR1 Mask Register (F3 Index 44h).
Index 18h-1Bh

Base Address Register 2 - F3BAR2 (R/W)

Reset Value = 00000000h

Reserved— Reserved for possible future use by the South Bridge module.
Configuration of this register is programmed through the F3BAR2 Mask Register (F3 Index 48h).
Index 1Ch-1Fh

Base Address Register 3 - F3BAR3 (R/W)

Reset Value = 00000000h

Reserved -- Reserved for possible future use by the South Bridge module.
Configuration of this register is programmed through the F3BAR3 Mask Register (F3 Index 4Ch).
Index 20h-23h

Base Address Register 4 - F3BAR4 (R/W)

Reset Value = 00000000h

Reserved — Reserved for possible future use by the South Bridge module.
Configuration of this register is programmed through the F3BAR4 Mask Register (F3 Index 50h).
Index 24h-27h

Base Address Register 5 - F3BAR5 (R/W)

Reset Value = 00000000h

Reserved — Reserved for possible future use by the South Bridge module.
Configuration of this register is programmed through the F3BAR5 Mask Register (F3 Index 54h).
Index 28h-2Bh

Reserved

Index 2Ch-2Dh

Subsystem Vendor ID (RO)

Reset Value = 1078h

Index 2Eh-2Fh

Subsystem ID (RO)

Reset Value = 0405h

Index 30h-3Fh

Reserved

Index 40h-43h

F3BAR0 Mask Address Register (R/W)

Reset Value = 00000000h

To use F3BAR0, the mask register should be programmed first. The mask register defines the size of F3BAR0 and whether the
accessed offset registers are memory or I/O mapped. Note that whenever this mask register is written to, F3BAR0 must also be
rewritten even if the value of F3BAR0 does not change.
Memory Base Address Register (Bit 0 == 0)
31:4

3
2:1

0

Address Mask — Use to determine the size of the BAR. Every bit that is a 1 is programmable in the BAR. Every bit
that is a 0 will be fixed 0 in the BAR. Since the address mask goes down to bit 4, the smallest memory region is 16
bytes, however, the PCI Specification suggests not using less than 4 KB address range.
Prefetchable
Type
00 = Located anywhere in 32-bit address space
01 = Located below 1 MB
10 = Located anywhere in 64-bit address spaced
11 = Reserved
Must = 0 for memory

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Table 4.36 F3 Index xxh: PCI Header Registers for XBus Expansion
Bit

Description

I/O Base Address Register (Bit 0 == 1)
31:2

Address Mask — Use to determine in the size of the BAR. Every bit that is a 1 is programmable in the BAR. Every bit
that is a 0 will be fixed 0 in the BAR. Since the address mask goes down to bit 2, the smallest I/O region is 4 bytes,
however, the PCI Specification suggests not using less than 4 KB address range.

1

Reserved — Must be 0.

0

Must = 1 for I/O

Index 44h-47h

F3BAR1 Mask Address Register (R/W)

Reset Value = 00000000h

To use F3BAR1, the mask register should be programmed first. The mask register defines the size of F3BAR1 and whether the
accessed offset registers are memory or I/O mapped. Note that whenever this mask register is written to, F3BAR1 must also be
rewritten even if the value of F3BAR1 does not change.
See F3 Index 40h (F3BAR0 Mask Address Register) for bit descriptions.
Index 48h-4Bh

F3BAR2 Mask Address Register (R/W)

Reset Value = 00000000h

To use F3BAR2, the mask register should be programmed first. The mask register defines the size of F3BAR2 and whether the
accessed offset registers are memory or I/O mapped. Note that whenever this mask register is written to, F3BAR2 must also be
rewritten even if the value of F3BAR2 does not change.
See F3 Index 40h (F3BAR0 Mask Address Register) for bit descriptions.
Index 4Ch-4Fh

F3BAR3 Mask Address Register (R/W)

Reset Value = 00000000h

To use F3BAR3, the mask register should be programmed first. The mask register defines the size of F3BAR3 and whether the
accessed offset registers are memory or I/O mapped. Note that whenever this mask register is written to, F3BAR3 must also be
rewritten even if the value of F3BAR3 does not change.
See F3 Index 40h (F3BAR0 Mask Address Register) for bit descriptions.
Index 50h-53h

F3BAR4 Mask Address Register (R/W)

Reset Value = 00000000h

To use F3BAR4, the mask register should be programmed first. The mask register defines the size of F3BAR4 and whether the
accessed offset registers are memory or I/O mapped. Note that whenever this mask register is written to, F3BAR4 must also be
rewritten even if the value of F3BAR4 does not change.
See F3 Index 40h (F3BAR0 Mask Address Register) for bit descriptions.
Index 54h-57h

F3BAR5 Mask Address Register (R/W)

Reset Value = 00000000h

To use F3BAR5, the mask register should be programmed first. The mask register defines the size of F3BAR5 and whether the
accessed offset registers are memory or I/O mapped. Note that whenever this mask register is written to, F3BAR5 must also be
rewritten even if the value of F3BAR5 does not change.
See F3 Index 40h (F3BAR0 Mask Address Register) on page 118 for bit descriptions.
Index 58h
7:6

F3BARx Initialized Register (R/W)

Reset Value = 00h

Reserved — Set to 0.

5

F3BAR5 Initialized — This bit reflects if F3BAR5 (F3 Index 24h) has been initialized. At reset this bit is cleared (0).
Writing F3BAR5 sets (1) this bit. If this bit programmed to 0, the decoding of F3BAR5 will be disabled until either this bit
is programmed to 1 or F3BAR5 is written.

4

F3BAR4 Initialized — This bit reflects if F3BAR4 (F3 Index 20h) has been initialized. At reset this bit is cleared (0).
Writing F3BAR4 sets (1) this bit. If this bit programmed to 0, the decoding of F3BAR4 will be disabled until either this bit
is programmed to 1 or F3BAR4 is written.

3

F3BAR3 Initialized — This bit reflects if F3BAR3 (F3 Index 1Ch) has been initialized. At reset this bit is cleared (0).
Writing F3BAR3 sets (1) this bit. If this bit is programmed to 0, the decoding of F3BAR3 will be disabled until either this
bit is programmed to 1 or F3BAR3 is written.

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Table 4.36 F3 Index xxh: PCI Header Registers for XBus Expansion
Bit

Description

2

F3BAR2 Initialized — This bit reflects if F3BAR2 (F3 Index 18h) has been initialized. At reset this bit is cleared (0).
Writing F3BAR2 sets (1) this bit. If this bit is programmed to 0, the decoding of F3BAR2 will be disabled until either this
bit is programmed to 1 or F3BAR2 is written.

1

F3BAR1 Initialized — This bit reflects if F3BAR1 (F3 Index 14h) has been initialized. At reset this bit is cleared (0).
Writing F3BAR1 sets (1) this bit. If this bit is programmed to 0, the decoding of F3BAR1 will be disabled until either this
bit is programmed to 1 or F3BAR1 is written.

0

F3BAR0 Initialized — This bit reflects if F3BAR0 (F3 Index 10h) has been initialized. At reset this bit is cleared (0).
Writing F3BAR0 sets (1) this bit. If this bit is programmed to 0, the decoding of F3BAR0 will be disabled until either this
bit is programmed to 1 or F3BAR0 is written.

Index 59h-FFh

Reserved

4.4.3.8. XBus Expansion Support Registers
F3 Index 10h, Base Address Register 0
(F3BAR0) set the base address that allows
PCI access to additional I/O Control support

registers. Table 4.37 shows the support registers accessed through F3BAR0.

Table 4.37 F3BAR0+I/O Offset xxh: XBus Expansion Registers
Bit

Description

Offset 00h-03h
31:28
27
26:25

I/O Control Register 1 (R/W)

Reset Value = 010C0007h

Reserved
Enable Integrated SIO Infrared (IO_ENABLE_SIO_IR) — 0 = Disable; 1 = Enable.
Integrated SIO Input Configuration (IO_SIOCFG_IN) — These two bits can be used to disable the integrated SIO
totally or limit/control the base address:
00 = Integrated SIO disable
01 = Integrated SIO configuration access disable
10 = Integrated SIO base address 02Eh/02Fh enable
11 = Integrated SIO base address 015Ch/015Dh enable

24

Enable Integrated SIO ISA Bus Control (IO_ENABLE_SIO_DRIVING_ISA_BUS) — Allow the integrated SIO to
drive the internal and external ISA bus: 0 = Disable; 1 = Enable (Default).

23

Reserved

22

IO_CLK32K_OE
This bit is set to drive 32Khz clock out on to GPIO[0]. Reset to 0.

21

IO_RTC_32K
This bit selects which 32K clock source is used. Resets to 0.
0 = use SIO generated 32Khz. Clock is driven by RTC.
1 = use internally generated 32Khz. Clock is derived by dividing the 48Mhz by 1484.
Note: bootstrap[6] = 1 can also be used to select internally generated 32Khz clock.

20

USB Internal SMI (IO_USB_SMI_PWM_EN) — Route USB-generated SMI through the Top Level SMI Status Register
at F1BAR0+I/O Offset 00h[14]: 0 = Disable; 1 = Enable.
Bit 19 must be enabled to allow the USB to generate an SMI for status reporting.

19

USB SMI I/O Configuration (IO_USB_SMI_PIN_EN) — Route USB-generated SMI directly to the SMI# pin:
0 = Disable
1 = Enable, USB-generated SMI pulls SMI# pin active (low)
If bits 19 and 20 are enabled, the SMI generated by the USB is reported through the Top Level SMI Status Register at
F1BAR0+I/O Offset 00h[14]. If only bit 19 is enabled, the USB can generate an SMI but there is no status reporting.

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Table 4.37 F3BAR0+I/O Offset xxh: XBus Expansion Registers
Bit

Description

18

USB (IO_USB_PCI_EN) — USB ports: 0 = Disable; 1 = Enable.

17

External KBC -- Must be left at 0.

16

External RTC -- Must be left at 0.

15:0

Reserved

Offset 04h-07h
31:8

I/O Control Register 2 (R/W)

Reset Value = 00000000h

Reserved

7

IO_CLK_14M_OE — Set to drive the internally generated 12Mhz clock out on GPIO[4]. Resets to 0.

6

Reserved

5

IO_ZT_EN
Set to enable the ZF-Logic ROM interface. Resets to 0.
Note: bootstrap[23] is also used to enable ZF-Logic ROM interface.a

4

IO_ZFL_EN
Set to enable the ZF-Logic. Resets to 0.
Note: bootstrap[22] is also used to enable the ZF-Logic.a

3

IO_FUNC_ON_SIO — Used in design verification only. Resets to 0.

2

IO_BUR_ON_SIO — Used in design verification only. Resets to 0.

1

IO_IDE_ON_GPIO — Drive IDE channel 2 onto gpio. Must also have gpio conditioned to correct direction
corresponding to IDE pin functionality.
See also Table 4.6 "IDE Interface Signals" on page 180.
0 = Do not drive IDE onto gpio. (default)
1 = Drive IDE into gpio.
gpio[1] is dmackx, gpio must be configured as output.
gpio[2] is diowx, gpio must be configured as output.
gpio[3] is diorx, gpio must be configured as output.
gpio[5] is dreq, gpio must be configured as input.
gpio[6] is iordy, gpio must be configured as input.

0

IO_EXT_CLK_14M
Select 14.3Mhz clock source. Select either internally or externally generated 14.3Mhz clock source. If internal source is
selected the actual clock frequency is 12Mhz (48Mhz / 4).
0 = Select external 14.3Mhz input as source. (default)
1 = Select internally generated 14.3Mhz clock source.
Note: bootstrap[5] = 1 can also be used to select internally generated 14.3Mhz clock.a

Offset 08h-0Bh

I/O Control Register 3 (R/W)

Reset Value = 00009000h

31:16

Reserved

15:13

USB Voltage Adjustment Connection (IO_USB_XCVR_VADJ) — These bits connect to the voltage adjustment
interface on the three USB transceivers. Default = 100.

12:8

USB Current Adjustment (IO_USB_XCVT_CADJ) — These bits connect to the current adjustment interface on the
three USB transceivers. Default value = 10000.

7:0

Reserved.

a. See Table 5.42 "Composite BootStrap Register Map" on page 438

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4.4.4. USB Controller Registers - PCIUSB
The registers designated as PCIUSB are 32bit registers decoded from the PCI address
bits 7 through 2 and C/BE[3:0]#, when IDSEL
is high, AD[10:8] select the appropriate function, and AD[1:0] are '00'. Bytes within a 32-bit
address are selected with the valid byte
enables. All registers can be accessed via 8-,
16-, or 32-bit cycles (that is, each byte is individually selected by the byte enables.) Regis-

ters marked as reserved, and reserved bits
within a register are not implemented and
should return 0s when read. Writes have no
effect for reserved registers.
Table 4.38 gives the bit formats for the USB
controller’s PCI header registers. For
complete register/bit formats, refer to Revision
1.0 of the OpenHCI Specification.

Table 4.38 PCIUSB: USB Controller Registers
Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 0E11h

Index 02h-03h

Device Identification Register (RO)

Reset Value = A0F8h

Index 04h-05h

Command Register (R/W)

15:10

Reset Value = 00h

Reserved — Set to 0.

9

Fast Back-to-Back Enable (Read Only) — USB only acts as a master to a single device, so this functionality is not
needed. It is always disabled (must always be set to 0).

8

SERR# — USB asserts SERR# when it detects an address parity error: 0 = Disable; 1 = Enable.

7

Wait Cycle Control — USB does not need to insert a wait state between the address and data on the AD lines. It is
always disabled (bit is set to 0).

6

Parity Error — USB asserts PERR# when it is the agent receiving data, and it detects a data parity error: 0 = Disable;
1 = Enable.

5

VGA Palette Snoop Enable (Read Only) — USB does not support this function. It is always disabled (bit is set to 0).

4

Memory Write and Invalidate — Allow USB to run Memory Write and Invalidate commands: 0 = Disable; 1 = Enable.
The Memory Write and Invalidate Command only occurs if the cacheline size is set to 32 bytes and the memory write is
exactly one cache line.
This bit should be left = 0.

3

Special Cycles — USB does not run special cycles on PCI. It is always disabled (bit is set to 0).

2

PCI Master Enable — Allow USB to run PCI master cycles: 0 = Disable; 1 = Enable.

1

Memory Space — Allow USB to respond as a target to memory cycles: 0 = Disable; 1 = Enable.

0

I/O Space — Allow USB to respond as a target to I/O cycles: 0 = Disable; 1 = Enable.

Index 06h-07h

Status Register (R/W)

Reset Value = 0280h

15

Detected Parity Error — This bit is set whenever the USB detects a parity error, even if the Parity Error (Response)
Detection Enable Bit (Command Register, bit 6) is disabled. Write 1 to clear.

14

SERR# Status — This bit is set whenever the USB detects a PCI address error. Write 1 to clear.

13

Received Master Abort Status — This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory
cycle. Write 1 to clear.

12

Received Target Abort Status — This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted
by a PCI target. Write 1 to clear.

11
10:9

Signaled Target Abort Status — This bit is set whenever the USB signals a target abort. Write 1 to clear.
DEVSEL# Timing (Read Only) — These bits indicate the DEVSEL# timing when performing a positive decode. Since
DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b.

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Table 4.38 PCIUSB: USB Controller Registers
Bit

Description

8

Data Parity Reported — Set to 1 if the Parity Error Response bit (Command Register bit 6) is set, and USB detects
PERR# asserted while acting as PCI master (whether PERR# was driven by USB or not).

7

Fast Back-to-Back Capable — USB does support fast back-to-back transactions when the transactions are not to the
same agent. This bit is always 1.

6:0

Reserved — Set to 0.

Note: The PCI Specification defines this register to record status information for PCI related events. This is a read/write register.
However, writes can only reset bits. A bit is reset whenever the register is written, and the data in the corresponding bit
location is a 1.
Index 08h

Device Revision ID Register (RO)

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 07h
Reset Value = 0C0310h

This register identifies the generic function of USB the specific register level programming interface. The Base Class is 0Ch (Serial
Bus Controller). The Sub Class is 03h (Universal Serial Bus). The Programming Interface is 10h (OpenHCI).
Index 0Ch

Cache Line Size Register (R/W)

Reset Value = 00h

This register identifies the system cacheline size in units of 32-bit words. USB will only store the value of bit 3 in this register since
the cacheline size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register will be read
back as 00h.
Index 0Dh

Latency Timer Register (R/W)

Reset Value = 00h

This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles.
Index 0Eh

Header Type Register (RO)

Reset Value = 00h

This register identifies the type of the predefined header in the configuration space. Since USB is a single function device and not a
PCI-to-PCI bridge, this byte should be read as 00h.
Index 0Fh

BIST Register (RO)

Reset Value = 00h

This register identifies the control and status of Built In Self Test. USB does not implement BIST, so this register is read only.
Index 10h-13h
31:12
11:4
3
2:1
0

Base Address Register (R/W)

Reset Value = 00000000h

Base Address — POST writes the value of the memory base address to this register.
Always 0 — Indicates a 4 KB address range is requested.
Always 0 — Indicates there is no support for prefetchable memory.
Always 0 — Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space.
Always 0 — Indicates that the operational registers are mapped into memory space.

Index 14h-2Bh

Reserved

Index 2Ch-2Dh

Subsystem Vendor ID (R/W)

Reset Value = 0E11h

Index 2Eh-2Fh

Subsystem ID (R/W)

Reset Value = A0F8h

Index 30h-3Bh

Reserved

Index 3Ch

Interrupt Line Register (R/W)

Reset Value = 00h

This register identifies to which of the system interrupt controllers the devices interrupt pin is connected. The value of this register is
used by device drivers and has no direct meaning to USB.

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Table 4.38 PCIUSB: USB Controller Registers
Bit

Description

Index 3Dh

Interrupt Pin Register (RO)

Reset Value = 01h

This register identifies which interrupt pin a device uses. Since USB uses INTA#, this value is set to 01h.
Index 3Eh

Min. Grant Register (RO)

Reset Value = 00h

This register specifies the desired settings for how long of a burst USB needs assuming a clock rate of 33 MHz. The value specifies
a period of time in units of 1/4 microsecond.
Index 3Fh

Max. Latency Register (RO)

Reset Value = 50h

This register specifies the desired settings for how often USB needs access to the PCI bus assuming a clock rate of 33 MHz. The
value specifies a period of time in units of 1/4 microsecond.
Index 40h-43h

ASIC Test Mode Enable Register (R/W)

Reset Value = 000F0000h

Used for internal debug and test purposes only.
Index 44h
7:1
0

ASIC Operational Mode Enable Register (R/W)

Reset Value = 00h

Write Only — Read as 0s.
Data Buffer Region 16 — When set the size of the region for the data buffer is 16 bytes. Otherwise, the size is 32
bytes.

Index 45h-FFh

Reserved

4.4.5. ISA Legacy Register Space
The ISA Legacy registers reside in the ISA I/O
address space in the address range from 000h
to FFFh and are accessed through typical
input/output instructions (that is, CPU direct
R/W) with the designated I/O port address and
8-bit data.
The bit formats for the ISA Legacy I/O Registers plus two chipset-specific configuration
registers used for interrupt mapping in the
South Bridge module core logic are given in

this section. The ISA Legacy registers are
separated into the following categories:
• DMA Channel Control Registers, see Table 4.39
• DMA Page Registers, see Table 4.40
• Programmable Interval Timer Registers, see
Table 4.41
• Programmable Interrupt Controller Registers,
see Table 4.42
• Keyboard Controller Registers, see Table 4.43
• Real Time Clock Registers, see Table 4.44
• Miscellaneous Registers, see Table 4.45
(includes 4D0h and 4D1h Interrupt Edge/Level
Select Registers)

Table 4.39 DMA Channel Control Registers
Bit

Description

I/O Port 000h (R/W)

DMA Channel 0 Address Register

Written as two successive bytes, byte 0, 1.
I/O Port 001h (R/W)

DMA Channel 0 Transfer Count Register

Written as two successive bytes, byte 0, 1.

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Table 4.39 DMA Channel Control Registers (cont.)
Bit

Description

I/O Port 002h (R/W)

DMA Channel 1 Address Register

Written as two successive bytes, byte 0, 1.
I/O Port 003h (R/W)

DMA Channel 1 Transfer Count Register

Written as two successive bytes, byte 0, 1.
I/O Port 004h (R/W)

DMA Channel 2 Address Register

Written as two successive bytes, byte 0, 1.
I/O Port 005h (R/W)

DMA Channel 2 Transfer Count Register

Written as two successive bytes, byte 0, 1.
I/O Port 006h (R/W)

DMA Channel 3 Address Register

Written as two successive bytes, byte 0, 1.
I/O Port 007h (R/W)

DMA Channel 3 Transfer Count Register

Written as two successive bytes, byte 0, 1.
I/O Port 008h (R/W)
Read

DMA Status Register, Channels 3:0

7

Channel 3 Request — Request pending? 0 = No; 1 = Yes.

6

Channel 2 Request — Request pending? 0 = No; 1 = Yes.

5

Channel 1 Request — Request pending? 0 = No; 1 = Yes.

4

Channel 0 Request — Request pending? 0 = No; 1 = Yes.

3

Channel 3 Terminal Count — TC reached? 0 = No; 1 = Yes.

2

Channel 2 Terminal Count — TC reached? 0 = No; 1 = Yes.

1

Channel 1 Terminal Count — TC reached? 0 = No; 1 = Yes.

0

Channel 0 Terminal Count — TC reached? 0 = No; 1 = Yes.

Write

DMA Command Register, Channels 3:0

7

DACK Sense — 0 = Active high; 1 = Active low.

6

DREQ Sense — 0 = Active high; 1 = Active low.

5

Write Selection — 0 = Late write; 1 = Extended write.

4

Priority Mode — 0 = Fixed; 1 = Rotating.

3

Timing Mode — 0 = Normal; 1 = Compressed.

2

Channels 3:0 — 0 = Disable; 1 = Enable.

1:0

Reserved — Set to 0.

I/O Port 009h (W)
7:3
2
1:0

Reserved — Set to 0.
Request Type — 0 = Reset; 1 = Set.
Channel Number Request Select — 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3.

I/O Port 00Ah (R/W)
7:3
2

Software DMA Request Register, Channels 3:0

DMA Channel Mask Register, Channels 3:0

Reserved — Set to 0.
Channel Mask — 0 = Not masked; 1 = Masked

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Table 4.39 DMA Channel Control Registers (cont.)
Bit

Description

1:0

Channel Number Mask Select — 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3

I/O Port 00Bh (W)
7:6

DMA Channel Mode Register, Channels 3:0

Transfer Mode — 00 = Demand; 01 = Single; 10 = Block; 11 = Cascade.

5

Address Direction — 0 = Increment; 1 = Decrement.

4

Auto-initialize — 0 = Disable; 1 = Enable.

3:2

Transfer Type — 00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved.

1:0

Channel Number Mode Select — 00 = Channel 0; 01 = Channel 1; 10 = Channel 2; 11 = Channel 3.

I/O Port 00Ch (W)

DMA Clear Byte Pointer Command, Channels 3:0

I/O Port 00Dh (W)

DMA Master Clear Command, Channels 3:0

I/O Port 00Eh (W)

DMA Clear Mask Register Command, Channels 3:0

I/O Port 00Fh (W)

DMA Write Mask Register Command, Channels 3:0

I/O Port 0C0h (R/W)

DMA Channel 4 Address Register

Not used.
I/O Port 0C2h (R/W)

DMA Channel 4 Transfer Count Register

Not used.
I/O Port 0C4h (R/W)

DMA Channel 5 Address Register

Memory address bytes 1 and 0.
I/O Port 0C6h (R/W)

DMA Channel 5 Transfer Count Register

Transfer count bytes 1 and 0
I/O Port 0C8h (R/W)

DMA Channel 6 Address Register

Memory address bytes 1 and 0.
I/O Port 0CAh (R/W)

DMA Channel 6 Transfer Count Register

Transfer count bytes 1 and 0.
I/O Port 0CCh (R/W)

DMA Channel 7 Address Register

Memory address bytes 1 and 0.
I/O Port 0CEh (R/W)

DMA Channel 7 Transfer Count Register

Transfer count bytes 1 and 0.

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Table 4.39 DMA Channel Control Registers (cont.)
Bit

Description

I/O Port 0D0h (R/W)
Read

DMA Status Register, Channels 7:4

7

Channel 7 Request — Request pending? 0 = No; 1 = Yes.

6

Channel 6 Request — Request pending? 0 = No; 1 = Yes.

5

Channel 5 Request — Request pending? 0 = No; 1 = Yes.

4

Undefined

3

Channel 7 Terminal Count — TC reached? 0 = No; 1 = Yes.

2

Channel 6 Terminal Count — TC reached? 0 = No; 1 = Yes.

1

Channel 5 Terminal Count — TC reached? 0 = No; 1 = Yes.

0

Undefined

Write

DMA Command Register, Channels 7:4

7

DACK Sense — 0 = Active high; 1 = Active low.

6

DREQ Sense — 0 = Active high; 1 = Active low.

5

Write Selection — 0 = Late write; 1 = Extended write.

4

Priority Mode — 0 = Fixed; 1 = Rotating.

3

Timing Mode — 0 = Normal; 1 = Compressed.

2

Channels 7:4 — 0 = Disable; 1 = Enable.

1:0

Reserved — Set to 0.

I/O Port 0D2h (W)
7:3
2
1:0

Reserved — Set to 0.
Request Type — 0 = Reset; 1 = Set.
Channel Number Request Select — 00 = Illegal; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7.

I/O Port 0D4h (R/W)
7:3
2
1:0

5
4

DMA Channel Mask Register, Channels 7:0

Reserved — Set to 0.
Channel Mask — 0 = Not masked; 1 = Masked.
Channel Number Mask Select — 00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7.

I/O Port 0D6h (W)
7:6

Software DMA Request Register, Channels 7:4

DMA Channel Mode Register, Channels 7:4

Transfer Mode — 00 = Demand; 01 = Single; 10 = Block; 11 = Cascade.
Address Direction — 0 = Increment; 1 = Decrement.
Auto-initialize — 0 = Disabled; 1 = Enable.

3:2

Transfer Type — 00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved.

1:0

Channel Number Mode Select — 00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7.
Channel 4 must be programmed in cascade mode. This mode is not the default.

I/O Port 0D8h (W)

DMA Clear Byte Pointer Command, Channels 7:4

I/O Port 0DAh (W)

DMA Master Clear Command, Channels 7:4

I/O Port 0DCh (W)

DMA Clear Mask Register Command, Channels 7:4

I/O Port 0DEh (W)

DMA Write Mask Register Command, Channels 7:4

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Table 4.40 DMA Page Registers
Bit

Description

I/O Port 081h (R/W)

DMA Channel 2 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 082h (R/W)

DMA Channel 3 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 083h (R/W)

DMA Channel 1 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 087h (R/W)

DMA Channel 0 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 089h (R/W)

DMA Channel 6 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 08Ah (R/W)

DMA Channel 7 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 08Bh (R/W)

DMA Channel 5 Low Page Register

Address bits [23:16] (byte 2).
I/O Port 08Fh (R/W)

ISA Refresh Low Page Register

Refresh address.
I/O Port 481h (R/W)

DMA Channel 2 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 081h.
I/O Port 482h (R/W)

DMA Channel 3 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 082h.
I/O Port 483h (R/W)

DMA Channel 1 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 083h.
I/O Port 487h (R/W)

DMA Channel 0 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 087h.
I/O Port 489h (R/W)

DMA Channel 6 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 089h.

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Table 4.40 DMA Page Registers (cont.)
Bit

Description

I/O Port 48Ah (R/W)

DMA Channel 7 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 08Ah.
I/O Port 48Bh (R/W)

DMA Channel 5 High Page Register

Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 08Bh.

Table 4.41 Programmable Interval Timer Registers
Bit

Description

I/O Port 040h
Write
7:0

PIT Timer 0 Counter
Counter Value

Read
7
6

PIT Timer 0 Status
Counter Output — State of counter output signal.
Counter Loaded — Last count written is loaded? 0 = Yes; 1 = No.

5:4

Current Read/Write Mode — 00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB,
followed by MSB.

3:1

Current Counter Mode — 0-5.

0

BCD mode — 0 = Binary; 1 = BCD (binary coded decimal).

I/O Port 041h
Write
7:0

PIT Timer 1 Counter (Refresh)
Counter Value

Read

PIT Timer 1 Status (Refresh)

7

Counter Output — State of counter output signal.

6

Counter Loaded — Last count written is loaded? 0 = Yes; 1 = No.

5:4

Current Read/Write Mode — 00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB,
followed by MSB.

3:1

Current Counter Mode — 0-5.

0

BCD mode — 0 = Binary; 1 = BCD (binary coded decimal).

I/O Port 042h
Write
7:0

PIT Timer 2 Counter (Speaker)
Counter Value

Read
7
6

PIT Timer 2 Status (Speaker)
Counter Output — State of counter output signal.
Counter Loaded — Last count written is loaded? 0 = Yes; 1 = No.

5:4

Current Read/Write Mode — 00 = Counter latch command; 01 = R/W LSB only; 10 = R/W MSB only; 11 = R/W LSB,
followed by MSB.

3:1

Current Counter Mode — 0-5.

ZFx86 Data Book 1.0 Rev D

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Table 4.41 Programmable Interval Timer Registers (cont.)
Bit
0

Description
BCD mode — 0 = Binary; 1 = BCD (binary coded decimal)

I/O Port 043h (R/W)

PIT Mode Control Word Register

7:6

Counter Select — 00 = Counter 0; 01 = Counter 1; 10 = Counter 2; 11 = Read-back command (Note 1).

5:4

Current Read/Write Mode — 00 = Counter latch command (Note 2); 01 = R/W LSB only; 10 = R/W MSB only; 11 =
R/W LSB, followed by MSB.

3:1

Current Counter Mode — 0-5.

0

BCD mode — 0 = Binary; 1 = BCD (binary coded decimal).

Notes: 1. If bits [7:6] = 11: Register functions as Read Status Command and:
Bit 5 = Latch Count
Bit 4 = Latch Status
Bit 3 = Select Counter 2
Bit 2 = Select Counter 1
Bit 1 = Select Counter 0
Bit 0 = Reserved
2. If bits [5:4] = 00: Register functions as Counter Latch Command and:
Bits [7:6] = Selects Counter
Bits [3:0] = Don’t care

Table 4.42 Programmable Interrupt Controller Registers
Bit

Description

I/O Port 020h / 0A0h (WO)

Master / Slave PIC IWC1

7:5

Reserved — Set to 0.

4

Reserved — Set to 1.

3

Trigger Mode — 0 = Edge; 1 = Level.

2

Vector Address Interval — 0 = 8 byte intervals; 1 = 4 byte intervals.

1

Reserved — Set to 0 (cascade mode).

0

Reserved — Set to 1 (ICW4 must be programmed).

I/O Port 021h / 0A1h (WO)

Master / Slave PIC ICW2 (after ICW1 is written)

7:3

A[7:3] — Address lines 7:3 for base vector for interrupt controller.

2:0

Reserved — Set to 0.

I/O Port 021h / 0A1h (WO)

Master / Slave PIC ICW3 (after ICW2 is written)

Master PIC ICW3
7:0

Cascade IRQ — Must be 04h.

Slave PIC ICW3
7:0

Slave ID — Must be 02h.

I/O Port 021h / 0A1h (WO)
7:5
4
3:2
1

Master / Slave PIC ICW4 (after ICW3 is written)

Reserved — Set to 0.
Special Fully Nested Mode — 0 = Disable; 1 = Enable.
Reserved — Set to 0.
Auto EOI — 0 = Normal EOI; 1 = Auto EOI.

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Table 4.42 Programmable Interrupt Controller Registers (cont.)
Bit
0

Description
Reserved — Set to 1 (8086/8088 mode).

I/O Port 021h / 0A1h (R/W)

Master / Slave PIC OCW1
(except immediately after ICW1 is written)

7

IRQ7 / IRQ15 Mask — 0 = Not Masked; 1 = Mask.

6

IRQ6 / IRQ14 Mask — 0 = Not Masked; 1 = Mask.

5

IRQ5 / IRQ13 Mask — 0 = Not Masked; 1 = Mask.

4

IRQ4 / IRQ12 Mask — 0 = Not Masked; 1 = Mask.

3

IRQ3 / IRQ11 Mask — 0 = Not Masked; 1 = Mask.

2

IRQ2 / IRQ10 Mask — 0 = Not Masked; 1 = Mask.

1

IRQ1 / IRQ9 Mask — 0 = Not Masked; 1 = Mask.

0

IRQ0 / IRQ8 Mask — 0 = Not Masked; 1 = Mask.

I/O Port 020h / 0A0h (WO)
7:5

Master / Slave PIC OCW2

Rotate/EOI Codes
000 = Clear rotate in Auto EOI mode
001 = Non-specific EOI
010 = No operation
011 = Specific EOI (bits [2:0] must be valid)

4:3

Reserved — Set to 0.

2:0

IRQ number (000-111)

I/O Port 020h / 0A0h (WO)
7
6:5

Master / Slave PIC OCW3

Reserved — Set to 0.
Special Mask Mode
00 = No operation
01 = No operation

10 = Reset Special Mask Mode
11 = Set Special Mask Mode

4

Reserved — Set to 0.

3

Reserved — Set to 1.

2

Poll Command — 0 = Disable; 1 = Enable.

1:0

100 = Set rotate in Auto EOI mode
101 = Rotate on non-specific EOI command
110 = Set priority command (bits [2:0] must be valid)
111 = Rotate on specific EOI command

Register Read Mode
00 = No operation
01 = No operation

I/O Port 020h / 0A0h (RO)

10 = Read interrupt request register on next read of Port 20h
11 = Read interrupt service register on next read of Port 20h.
Master / Slave PIC Interrupt Request and Service Registers
for OCW3 Commands

Interrupt Request Register
7

IRQ7 / IRQ15 Pending — 0 = Yes; 1 = No.

6

IRQ6 / IRQ14 Pending — 0 = Yes; 1 = No.

5

IRQ5 / IRQ13 Pending — 0 = Yes; 1 = No.

4

IRQ4 / IRQ12 Pending — 0 = Yes; 1 = No.

3

IRQ3 / IRQ11 Pending — 0 = Yes; 1 = No.

2

IRQ2 / IRQ10 Pending — 0 = Yes; 1 = No.

1

IRQ1 / IRQ9 Pending — 0 = Yes; 1 = No.

0

IRQ0 / IRQ8 Pending — 0 = Yes; 1 = No.

ZFx86 Data Book 1.0 Rev D

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Table 4.42 Programmable Interrupt Controller Registers (cont.)
Bit

Description

Interrupt Service Register
7

IRQ7 / IRQ15 In-Service — 0 = No; 1 = Yes.

6

IRQ6 / IRQ14 In-Service — 0 = No; 1 = Yes.

5

IRQ5 / IRQ13 In-Service — 0 = No; 1 = Yes.

4

IRQ4 / IRQ12 In-Service — 0 = No; 1 = Yes.

3

IRQ3 / IRQ11 In-Service — 0 = No; 1 = Yes.

2

IRQ2 / IRQ10 In-Service — 0 = No; 1 = Yes.

1

IRQ1 / IRQ9 In-Service — 0 = No; 1 = Yes.

0

IRQ0 / IRQ8 In-Service — 0 = No; 1 = Yes.

Note: The function of this register is set with bits 1:0 in a write to 020h.

Table 4.43 Keyboard Controller Registers
Bit

Description

I/O Port 060h (R/W)

External Keyboard Controller Data Register

Keyboard Controller Data Register — All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset
features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to
this port assert the A20M# pin or cause a warm CPU reset.
I/O Port 061h (R/W)

Port B Control Register

Reset Value = 00x01100b

7

PERR#/SERR# Status (Read Only) — Was a PCI bus error (PERR#/ SERR#) asserted by PCI device? 0 = No;
1=Yes.

6

IOCHK# Status (Read Only) — Is an I/O device reporting an error? 0 = No; 1 = Yes.

This bit can only be set if ERR_EN is set 0. Set this bit to 0 after a write to ERR_EN with a 1 or after reset.
This bit can only be set if IOCHK_EN is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset.
5

PIT OUT2 State (Read Only) — Reflects the current status of the PIT Timer2-OUT2.

4

Toggle (Read Only) — Toggles on every falling edge of Counter 1 (OUT1).

3

IOCHK Enable
0 = Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control.
1 = Ignores the IOCHK# input signal and does not generate NMI.

2

PERR#/ SERR# Enable — Generate an NMI if PERR#/ SERR# is driven active to report an error:
0 = Enable; 1 = Disable

1

PIT Counter2 (SPKR) — 0 = Forces Counter 2 output (OUT2) to zero. 1 = Allows Counter 2 output (OUT2) to pass to
the speaker

0

PIT Counter2 Enable — 0 = Sets GATE2 input low. 1 = Sets GATE2 input high.

I/O Port 062h (R/W)

External Keyboard Controller Mailbox Register

Keyboard Controller Mailbox Register — Accesses to this port will assert ROMCS# if the Port 062h/066h decode is enabled
through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]).
I/O Port 064h (R/W)

External Keyboard Controller Command Register

Keyboard Controller Command Register — All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20
and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of
writes to this port assert the A20M# pin or cause a warm CPU reset.

ZFx86 Data Book 1.0 Rev D

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Table 4.43 Keyboard Controller Registers (cont.)
Bit

Description

I/O Port 066h (R/W)

External Keyboard Controller Mailbox Register

Keyboard Controller Mailbox Register — Accesses to this port will assert KBROMCS# if the Port 062h/066h decode is enabled
through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]).
I/O Port 092h (R/W)
7:2

Port A Control Register

Reset Value = 02h

Reserved — Set to 0.

1

A20M# SMI Assertion — Assert A20# SMI: 0 = Enable; 1 = Disable.

0

Fast CPU Reset — WM_RST SMI is asserted to the BIOS: 0 = Disable; 1 = Enable.
Clear this bit before the generation of another reset.

Table 4.44 Real-Time Clock Registers
Bit

Description

I/O Port 070h (WO)
7
6:0

RTC Address Register

NMI Mask — 0 = Enable; 1 = Mask.
RTC Register Index — A write of this register sends the data out on the ISA bus.

Note: This register is shadowed within the South Bridge module and is read through the RTC Shadow Register (PCIDV2F1
10h+Memory Offset BBh).
I/O Port 071h (R/W)

RTC Data Register

A read of this register returns the value of the register indexed by the RTC Address Register.
A write of this register sets the value into the register indexed by the RTC Address Register.

Table 4.45 Miscellaneous Registers
Bit

Description

I/O Port 0F0h, 0F1h

Coprocessor Error Register (W)

Reset Value = F0h

A write to either port when the FERR# signal is asserted causes the South Bridge module to assert IGNNE#. IGNNE# remains
asserted until the FERR# deasserts.
I/O Ports 170h-177h/376h-377h

Secondary IDE Registers (R/W)

When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate
according to their configuration rather than generating standard ISA bus cycles.
I/O Ports 1F0h-1F7h/3F6h-3F7h

Primary IDE Registers (R/W)

When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate
according to their configuration rather than generating standard ISA bus cycles.
I/O Port 4D0h
7

Interrupt Edge/Level Select Register 1 (R/W)

Reset Value = 00h

IRQ7 Edge or Level Sensitive Select — Selects PIC IRQ7 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

6

IRQ6 Edge or Level Sensitive Select — Selects PIC IRQ6 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

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Table 4.45 Miscellaneous Registers (cont.)
Bit
5

Description
IRQ5 Edge or Level Sensitive Select — Selects PIC IRQ5 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

4

IRQ4 Edge or Level Sensitive Select — Selects PIC IRQ4 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

3

IRQ3 Edge or Level Sensitive Select — Selects PIC IRQ3 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

2:0

Reserved — Set to 0.

Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. See I/O Port 020h/0A0h.
2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).
I/O Port 4D1h
7

Interrupt Edge/Level Select Register 2 (R/W)

Reset Value = 00h

IRQ15 Edge or Level Sensitive Select — Selects PIC IRQ15 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

6

IRQ14 Edge or Level Sensitive Select — Selects PIC IRQ14 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

5

Reserved — Set to 0.

4

IRQ12 Edge or Level Sensitive Select — Selects PIC IRQ12 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

3

IRQ11 Edge or Level Sensitive Select — Selects PIC IRQ11 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

2

IRQ10 Edge or Level Sensitive Select — Selects PIC IRQ10 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

1

IRQ9 Edge or Level Sensitive Select — Selects PIC IRQ9 sensitivity configuration: 0 = Edge; 1 = Level.
Notes 1 and 2.

0

Reserved — Set to 0.

Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting.
2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).

4.5. SuperI/O - A PC98 Compliant Cell
The SuperI/O is a PC98 compliant component
that offers a complete solution to the most
commonly used ISA peripherals.
The SuperI/O incorporates: a Floppy Disk
Controller (FDC), two enhanced Serial Ports,
an Infrared Communication Port that supports
FIR, MIR, HP-SIR, Sharp-IR, and Consumer
Electronics-IR, a full IEEE 1284 Parallel Port,
an ACCESS.bus Interface (ACB), a Keyboard
and Mouse Controller (KBC), System WakeUp Control (SWC), a Real-Time Clock (RTC)
that provides both RTC timekeeping and
Advanced Power Control (APC) functionality.

ZFx86 Data Book 1.0 Rev D

4.5.1. Outstanding Features
• System Wake-Up Control generates a
power-up request in response to pre
programmed keyboard or mouse
sequence, modem, telephone ring, and
two general-purpose events
• Programmable write protect for Floppy
Disk Controller
• Advanced RTC and APC, Y2K compliant

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Serial
Interface

Serial
Interface

Infrared
Interface

Floppy Drive
Interface

Parallel Port
Interface

ISA
Interface

Serial Port 1

Serial Port 2

IR Comunication
Port

Floppy Disk
Controller

IEEE 1284
Parallel Port

Host Interface

VBAT

System Wake-Up
Control

Real-Time Clock

ACCESS.bus

Wake-Up PWUREQ
Events

SCL

SDA

Keyboard and Mouse
Controller

Keyboard and
Ports
Mouse Interface

Figure 4-4 Super I/O Block Diagram

4.5.2. Features
• PC98 Compliant
— PnP Configuration Register structure
— Flexible resource allocation for all logical
devices
— Relocatable base address
— 9 Parallel IRQ routing options
— 3 optional 8-bit DMA channels (where
applicable)
• Floppy Disk Controller (FDC)
— Programmable write protect
— FM and MFM mode support
— Enhanced mode command for threemode Floppy Disk Drive (FDD) support
— Perpendicular recording drive support for
2.88 MB
— Burst and non-burst modes
— Full support for IBM Tape Drive register
(TDR) implementation of AT and PS/2
drive types
— 16-byte FIFO

ZFx86 Data Book 1.0 Rev D

— Software compatible with the PC8477,
which contains a superset of the FDC
functions in the microDP8473, the NEC
microPD765A and the N82077
— High-performance, digital separator
— Standard 5.25” and 3.5” FDD support
• Parallel Port
— Software or hardware control
— Enhanced Parallel Port (EPP) compatible with new version EPP 1.9 and IEEE
1284 compliant
— EPP support for version EPP 1.7 of the
Xircom specification
— EPP support as mode 4 of the Extended
Capabilities Port (ECP)
— IEEE 1284 compliant ECP, including level 2
— Selection of internal pull-up or pull-down
resistor for Paper End (PE) pin
— PCI bus utilization reduction by supporting a demand DMA mode mechanism
and a DMA fairness mechanism

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4
— Protection circuit that prevents damage
to the parallel port when a printer connected to it powers up or is operated at
high voltages, even if the device is in
power-down
— Output buffers that can sink and source
14 mA
• Serial Ports 1 and 2
— Software compatible with the 16550A
and the 16450
— Shadow register support for write-only bit
monitoring
— UART data rates up to 1.5 Mbps

— Asynchronous access to two data registers and one status register during normal operation
— Support for both interrupt and polling
— 93 instructions
— 8-bit timer/counter
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz
(programmable option)
— Can be customized by using the
PC87323, which includes a RAM-based
KBC as a development platform for KBC
code
• System Wake-Up Control (SWC)

• Infrared Communication Port
—
—
—
—
—
—
—
—
—
—
—
—

Data rate of up to 115.2 Kbps (SIR)
Data rate of 1.152 Mbps (MIR)
Data rate of 4.0 Mbps (FIR)
Selectable internal or external modulation/demodulation (Sharp-IR)
Consumer-IR (TV-Remote) mode
Software compatible with the 16550A
and the 16450
Shadow register support for write-only bit
monitoring
HP-SIR
ASK-IR option of SHARP-IR
DASK-IR option of SHARP-IR
Consumer Remote Control supports
RC-5, RC-6, NEC, RCA and RECS 80
Non-standard DMA support - 1 or 2
channels

• Keyboard and Mouse Controller (KBC)
— 8-bit microcontroller
— Software compatible with the 8042AH
and PC87911 microcontrollers
— 2 KB custom-designed program ROM
— 256 bytes RAM for data
— Four programmable dedicated opendrain I/O lines

ZFx86 Data Book 1.0 Rev D

— Power-up request upon detection of Keyboard, Mouse, RI1, RI2, RING, PME1
and PME2 activity, as follows:
— Preprogrammed Keyboard or Mouse
sequence
— External modem ring on serial ports
— Ring pulse or pulse train on the RING
input
— General-purpose events, PME1 and
PME2
— Battery-backed wake-up setup
— Power-fail recovery support
• Real-Time Clock
— A modifiable address that is referenced
by a 16-bit programmable register
— 13 IRQ options, with programmable polarity
— DS1287, MC146818 and PC87911 compatibility
— 242 bytes of battery backed up CMOS
RAM in two banks
— Selective lock mechanisms for the RTC
RAM
— Battery backed up century calendar in
days, day of the week, date of month,
months, years and century, with automatic leap-year adjustment

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— Battery backed-up time of day in seconds, minutes and hours that allows a 12
or 24 hour format and adjustments for
daylight savings time
— BCD or binary format for time keeping
— Three different maskable interrupt flags:
— Periodic interrupts - At intervals from
122 msec to 500 msec
— Time-of-Month alarm - At intervals
from once per second to once per
Month
— Updated Ended Interrupt - Once per
second upon completion of update
— Separate battery pin, 3.0V operation that
includes an internal UL protection resistor
— 2 mA maximum power consumption during power down

— Double-buffer time registers
• Clock Sources
— 48 MHz clock input
— On-chip low frequency clock generator
for wake-up
— 32.768 KHz crystal with an internal frequency multiplier to generates all required internal frequencies
• Y2K Compliant

4.5.3. SIGNAL/PIN Descriptions

Table 4.46 ACCESS.bus Interface (ACB)
Signal

Pin(s)

I/O Buffer Type Power Well
I/O

SCL_N

AA4

SDA

AB4

INSM/OD6

VDD

Description
ACCESS.bus Clock Signal
An internal pull-up is optional, depending upon the ACCESS.bus
configuration register.

I/O

INSM/OD6

VDD

ACCESS.bus Data Signal
An internal pull-up is optional, depending upon the ACCESS.bus
configuration register.

4.5.4. Device Architecture and Configuration
The SuperI/O device comprises a collection of
4.5.4.1. Overview
generic functional blocks. Each functional
block is described in a separate chapter in this
book. However, some parameters in the
implementation of each functional block may
vary per SuperI/O device. This chapter
describes the SuperI/O structure and provides
all device specific information, including
special implementation of generic blocks,
system interface and device configuration.

ZFx86 Data Book 1.0 Rev D

The SuperI/O is based on 10 logical devices,
the host interface, and a central configuration
register set, all built around a central, internal
8-bit bus.
The host interface serves as a bridge between
the external ISA interface and the internal bus.
It supports 8-bit I/O read, 8-bit I/O write and
8-bit DMA transactions, as defined in Personal
Computer Bus Standard P996.

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IRRX2,1

IRSL3-0

configured in, and managed by, the central
configuration register set. In addition, some
function-specific parameters are configurable
through this unit and distributed to the functional blocks through special control signals.

IRTX

The central configuration registers are structured as a subset of the Plug and Play Standard Registers, defined in Appendix A of the
Plug and Play ISA Specification Version 1.0a
by Intel and Microsoft. All system resources
assigned to the functional blocks (I/O address
space, DMA channels, and IRQ lines) are

Infrared
Communication
Port

Parallel
Port
Configuration
and Control
Registers

Serial
Port 1

Serial
Port 2

Keyboard
and
Mouse
Controller

RDATA
WDATA

SIN1
SOUT1
RTS1
DTR1
CTS1
DSR1
DCD1
RI1
SIN2
SOUT2
RTS2
DTR2
CTS2
DSR2
DCD2
RI2
KBLOCK
KBCLK
KBDAT
MDAT
MCLK

WGATE

WP

VBAT

VCC_IO

X2C

X1C/X1

ALARM

Real-Time Clock (RTC)

Host
Interface
System
Wake-Up

SCL
SDA
TC
DACK0-3
DRQ0-3
IRQ1-12,14-15
IOCHRDY
ZWS
IOWR
IORD
AEN

SIOCFG
CLKIN
MR
D7-0
A15-0

DSKCHG

PWUREQ

TRK0
INDEX

RING
S_GPWI01
CHASI
S_GPWI02
CHASO

FDC

STEP

ACCESS
Bus

Control Signals

DIR

Internal Bus

HDSEL

Figure 4-5 Detailed SuperI/O Block Diagram

ZFx86 Data Book 1.0 Rev D

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4.5.4.2. Coinfiguration Structure And Access
the configuration register that is currently
accessible via the Data Register. Reading the
Index Register returns the last value written to
the Data Register (or the default of 00h after
reset).

This section describes the structure of the
configuration register file, and the method of
accessing the configuration registers.

4.5.4.3. The Index-Data Register Pair
The SuperI/O configuration access is
performed via an Index-Data register pair,
using only two system I/O byte locations. The
base address of this register pair is determined according to the state on the SIOCFG
input pins.

The Data Register is an 8-bit virtual register,
used as a data path to any configuration
register. Accessing the data register results in
a physical access of the configuration register
that is currently being pointed to by the index
register.

The Index Register is an 8-bit R/W register
located at the selected base address
(Base+0). It is used as a pointer to the configuration register file, and holds the contents of

Table 4.47 shows the selected base
addresses as a function of SIOCFG.

Table 4.47 SuperI/O Configuration Options
SIOCFG
F3BAR0
Offset 00h-03h [26:25]
Settings

I/O Address
Description
Index Register

Data Register

00

-

-

SuperI/O disabled

01

-

-

Configuration access disabled

10

002Eh

002Fh

Base address 1 selected

11

015Ch

015Dh

Base address 2 selected

4.5.4.4. Banked Logical Device Registers
Each functional block is associated with a
Logical Device Number (LDN). The configuration registers are grouped into banks, where
each bank holds the standard configuration
registers of the corresponding logical device.
Table 4.47 shows the LDN values of the
device functional blocks.
Figure 4-6 shows the structure of the standard
configuration register file. The SuperI/O
control and configuration registers are not
banked and are accessed by the Index-Data
register pair only, as described above.
However, the device control and device
configuration registers are duplicated over 10
banks for 10 logical devices. Therefore,

ZFx86 Data Book 1.0 Rev D

accessing a specific register in a specific bank
is performed by two dimensional indexing,
where the LDN register selects the bank (or
logical device) and the Index register selects
the register within the bank.
Accessing the Data register while the Index
register holds a value of 30h or higher results
in a physical access to the Logical Device
Configuration registers currently pointed to by
the Index register, within the logical device
bank currently selected by the LDN register.

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07h

Logical Device Number Register

20h
2Fh

SuperI/O Configuration Registers

30h

Logical Device Control Register

60h
63h
70h
71h
74h
75h
F0h
FEh

Standard Logical Device
Standard Registers

Special (Vendor-defined)
Logical Device
Configuration Registers

Bank Select

Banks
(One per Logical Device)

Figure 4-6 Structure of the Standard Configuration Register File

Table 4.48 Logical Device Number (LDN) Assignments
LDN

Functional Block

00h

Floppy Disk Controller (FDC)

01h

Parallel Port (PP)

02h

Serial Port 2 (SP2)

03h

Serial Port 1 (SP1)

04h

System Wake-Up Control (SWC)

05h

Keyboard and Mouse Controller (KBC) - Mouse interface

06h

Keyboard and Mouse Controller (KBC) - Keyboard interface

07h

Infrared Communication Port (IRCP)

08h

ACCESS.Bus (ACB)

09h

Reserved

0Ah

Real-Time Clock (RTC)

Write accesses to unimplemented registers
(that is accessing the Data register while the
Index register points to a non-existing
register), are ignored and read returns 00h on
all addresses except for 74h and 75h (DMA
configuration registers) which returns 04h

ZFx86 Data Book 1.0 Rev D

(indicating no DMA channel is active). The
configuration registers are accessible immediately after reset.

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4.5.5. Standard Logical Device Configuration Register Definitions
Unless otherwise noted in Table 4.49 through
Table 4.54:
• All registers are read/write.
• All reserved bits return 0 on reads, except
where noted otherwise. They must not be
modified as it may cause unpredictable

results. Use read-modify-write to prevent
the values of reserved bits from being
changed during write.
• Write only registers should not use readmodify-write during updates.

Table 4.49 Standard Control Registers
Index

Register Name

Description

07h

Logical Device
Number

This register selects the current logical device. See Table 4.48 for valid numbers. All
other values are reserved.

20h - 2Fh

SuperI/O
Configuration

SuperI/O configuration registers and ID registers

Table 4.50 Logical Device Activate Register
Index
30h

Register Name

Description
Bit 0 - Logical device activation control
0 = Disabled
1 = Enabled
Bits 7-1 - Reserved

Activate

Table 4.51 I/O Space Configuration Registers
Index

Register Name

Description

60h

I/O Port Base
Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0.
Address Bits (15-8)
Descriptor 0

61h

I/O Port Base
Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0.
Address Bits (7-0)
Descriptor 0

62h

I/O Port Base
Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1.
Address Bits (15-8)
Descriptor 1

63h

I/O Port Base
Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1.
Address Bits (7-0)
Descriptor 1

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Table 4.52 Interrupt Configuration Registers
Index

Register Name

Description

70h

Interrupt Number Bits 3-0 select the interrupt number. A value of 1 selects IRQ1, a value of 2
selects IRQ2, etc. (up to IRQ15). IRQ0 is not a valid interrupt selection.

71h

Interrupt Request Indicates the type and level of the interrupt request number selected in the
Type Select
previous register.
Bit 0 - Type of interrupt request selected in previous register
0 = Edge
1 = Level
Bit 1 - Level of interrupt request selected in previous register
0 = Low polarity
1 = High polarity

Table 4.53 DMA Configuration Registers
Index

Register Name

Description

74h

DMA Channel
Select 0

Indicates selected DMA channel for DMA 0 of the logical device (0 - The first DMA
channel in the case of using more than one DMA channel).
Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where a
value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.

75h

DMA Channel
Select 1

Indicates selected DMA channel for DMA 1 of the logical device (1 - The second
DMA channel in the case of using more than one DMA channel).
Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where a
value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.

Table 4.54 Special Logical Device Configuration Registers
Index

Register Name

Description

F0h-FEh

Logical Device
Configuration

Special (vendor-defined) configuration options.

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4.5.6. Standard Configuration Registers

Index

SuperI/O Control and
Configuration Registers

Logical Device Control and
Configuration Registers one per logical device
(some are optional)

Register Name

07h

Logical Device Number

20h

SuperI/O ID

21h

SuperI/O Configuration 1

22h

SuperI/O Configuration 2

27h

SuperI/O Revision ID

2Eh

Reserved

30h

Logical Device Control (Activate)

60h

I/O Port Base Address Descriptor 0 Bits 15-8

61h

I/O Port Base Address Descriptor 0 Bits 7-0

62h

I/O Port Base Address Descriptor 1 Bits 15-8

63h

I/O Port Base Address Descriptor 1 Bits 7-0

70h

Interrupt Number Select

71h

Interrupt Type Select

74h

DMA Channel Select 0

75h

DMA Channel Select 1

F0h

Device Specific Logical Device Configuration 1

F1h

Device Specific Logical Device Configuration 2

F2h

Device Specific Logical Device Configuration 3

F3h

Device Specific Logical Device Configuration 4

Figure 4-7 Configuration Register Map

SuperI/O Control and Configuration
Registers (20h/27h)
The SuperI/O Configuration registers at
indexes 20h to 27h are mainly used for part
identification, global power management and
the selection of pin multiplexing options.
Logical Device Control and Configuration
Registers (30h)
A subset of these registers is implemented for
each logical device.

ZFx86 Data Book 1.0 Rev D

Control
The only implemented logical device control
register is the activate register at index 30h.
Bit 0 of the activate register, together with the
Global Device Enable bit (except for the RTC
and the SWC) control the activation of the
associated function block. Activation of the
block enables access to the block’s registers,
and attaches its system resources, which are
unused as long as the block is not activated.
Other effects may apply, on a function-specific
basis (such as clock enable and active pinout
signaling).

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Standard Configuration
The standard configuration registers are used
to manage the resource allocation to the functional blocks. The I/O port base address
descriptor 0 is a pair of registers at Index 6061, holding the (first or only) 16-bit base
address for the register set of the functional
block. An optional second base-address
(descriptor 1) at index 62-63 is used for
devices with more than one continuous
register set. Interrupt Number Select (index
70h) and Interrupt Type Select (index 71h)
allocate an IRQ line to the block and control its
type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where
applicable. DMA Channel Select 1 (index 75h)
allocates a second DMA channel, where applicable.
Special Configuration
The vendor identification registers, starting at
index F0h are used to control function-specific
parameters such as operation modes, power
saving modes, pin TRI-STATE, clock rate
selection, and non-standard extensions to
generic functions.

4.5.6.1. Default Configuration Setup
The device has three reset types:
• Software Reset
Generated by bit 1 of the SIOCF1 register,
which resets all logical devices. A software
reset also resets most bits in the SuperI/O
Configuration and Control registers (see
Section 4.6.1 for the bits not affected). This
reset does not affect register bits that are
locked for write access.
• Hardware Reset
Activated by the system reset signal. This
resets all logical devices, with the exception
of the RTC and the SWC, and all SuperI/O
Configuration and Control registers, with the
exception of the SIOCF2 register. It also resets all SuperI/O control and configuration
registers, except for those that are batterybacked.

ZFx86 Data Book 1.0 Rev D

• VPP Power-Up Reset
Activated when VBAT is powered on after
both have been off. VPP is an internal voltage which is VBAT. This reset resets all registers whose values are retained by VPP.
The SuperI/O wakes up with the default setup,
as follows:
• In the event of a hardware reset:
— The configuration base address is 2Eh,
15Ch or None, according to the SIOCFG
pin values, as shown in Table 4.47 on
page 263.
— The Keyboard Controller (KBC) may be
activated and all other logical devices
are disabled, with the exception of the
RTC and the SWC, which remains functional but whose registers cannot be accessed.
• In the event of either a hardware or a software reset:
— The legacy devices are assigned with
their legacy system resource allocation.
— Proprietary functions are not assigned
with any default resources and the default values of their base addresses are
all 00h.

4.5.6.2. Address Decoding
A full 16-bit address decoding is applied when
accessing the configuration I/O space, as well
as the registers of the functional blocks.
However, the number of configurable bits in
the base address registers vary for each
device.
The lower 1, 2, 3 or 4 address bits are
decoded within the functional block to determine the offset of the accessed register, within
the device’s I/O range of 2, 4, 8 or 16 bytes,
respectively. The rest of the bits are matched
with the base address register to decode the
entire I/O range allocated to the device.
Therefore the lower bits of the base address
register are forced to 0 (read-only), and the

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base address is forced to be 2, 4, 8 or 16 byte
aligned, according to the size of the IO range.
• The base address of the FDC, RTC, Serial
Port 1, Serial Port 2, Infrared Communication Port and KBC are limited to the I/O
address range of 00h to 7FXh only (bits
11-15 are forced to 0).
• The Parallel Port base address is limited to
the I/O address range of 00h to 3F8h.
• The addresses of the non-legacy devices
are configurable within the full 16-bit
address range (up to FFFXh).

In some special cases, other address bits are
used for internal decoding (such as bit 2 in the
KBC and bit 10 in the Parallel Port). The KBC
has two I/O descriptors with some implied
dependency between them. For more details,
please see the detailed description of the base
address register for each specific logical
device.

4.5.6.3. The Internal Clocks
The source of the device internal clocks is a
48 MHz clock signal, which is routed through
the CLKIN pin. Wake-up on KBD, Mouse and
RING pulse train detection operates on 32
KHz clock.

4.6. SuperI/O Configuration Registers
This section describes the SuperI/O configuration and ID registers (those registers with first
level indexes in the range of 20h - 2Eh). See
Table 4.56 for a summary and directory of
these registers.

4.6.1. Register Type Abbreviations
The register maps in this chapter use the
following abbreviations:

Table 4.55 Register Type Abbreviations
Symbol

Meaning

R/W

Read/Write

R

Read from a specific address returns the value of a specific register.
Write to the same address is to a different register.

W

Write

RO

Read Only

R/W1C

Read/Write 1 to Clear. Writing 1 to a bit clears it to 0.
Writing 0 has no effect.

Table 4.56 SuperI/O Configuration Registers
Index Mnemonic

Register Name

Power Well

Type

Reference

20h

SID

SuperI/O ID

VDD

RO

Table 4.57

21h

SIOCF1

SuperI/O Configuration 1

VDD

R/W

Table 4.58

22h

SIOCF2

SuperI/O Configuration 2

VPP

R/W

Table 4.59

27h

SRID

SuperI/O Revision ID

VDD

RO

Table 4.60

2Eh Reserved

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Table 4.57 SuperI/O ID Register (SID) - Index 20H
Bit

7

6

5

4

Name

3

2

1

0

0

0

1

1

Chip ID

Reset

1

1

1

0

Notes: RO. This register contains the identity number of the chip. The SuperI/O is identified by the value E3H.

Table 4.58 SuperI/O Configuration 1 Register (SIOCF1) - Index 21H
Bit

7

6

General Purpose
Scratch

Name

Reset

0

0

5

4

3

2

1

0

Lock
Scratch

PNF
Status

Reserved

Pin
Function
Lock

SW Reset

Global
Device
Enable

0

X

0

0

0

1

This is a read/write register.

Bit
7-6

Description
General Purpose Scratch
When bit 5 is set to 1, these bits are read only. After reset, these bits can be read or write. Once changed
to read only, the bits can be changed back to read/write only by a hardware reset.

5

Lock Scratch
This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can only be cleared to
0 by a hardware reset.
0 = Bits 7 and 6 of this register are read/write bits (default).
1 = Bits 7 and 6 of this register are read only bits.

4

Reserved.

3

Reserved

2

Pin Function Lock
When bit set to 1, all function selection on the associated pins lock (Bits 0 and 2 of the SIOCF2 register).
When set to 1 by software, it can only be cleared to 0 by Master Reset or power-off.
0 = No effect (default)
1 = Pin function locked

1

SW Reset
Read always returns 0.
0 = Ignored (default)
1 = Resets all the devices that are reset by MR (with the exception of the lock bits) and the registers of the
SWC

0

Global Device Enable
This bit controls the function enable of all the logical devices in the SuperI/O, except the SWC and the RTC. It
allows them to be disabled simultaneously by writing to a single bit.
0=
1=

All logical devices in the SuperI/O disabled, except the SWC and the RTC.
Each logical device enabled according to its Activate register at index 30h (default)

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Table 4.59 SuperI/O Configuration 2 Register (SIOCF2) - Index 22H
Bit

7
Reserved

6

5

4

General Purpose Scratch

Name
Reset

1

0

0

3

2

S_GPWI02
Debounce
Enable

Reserved

1

0

0

1

0

S_GPWI01 S_GPWI01
Debounce
Function
Enable
Select
1

0

This register controls the multiplexing of two pins. Its value is retained by VPP, and is not affected by either hardware
or software reset.

Bit
7
6-4

Description
Reserved
General Purpose Scratch
Battery-backed.

3

S_GPWI02 Debounce Enable
0=
1=

Debounce disabled
16mS debounce enabled (VPP power-up default)

2

Reserved

1

S_GPWI01 Debounce Enable
0=
1=

0

Debounce disabled
16mS debounce enabled (VPP power-up default)

S_GPWI01 Function Select
0=
1=

RING (VPP power-up default)
S_GPWI01

Table 4.60 SuperI/O Revision ID Register (SRID) - Index 27H
Bit

7

Name

Chassis
Intrusion

Reset

1

6

5

4

General Purpose Scratch

0

0

0

3

2

1

0

S_GPWI02 S_GPWI02 S_GPWI01 S_GPWI01
Debounce
Function
Debounce
Function
Enable
Select
Enable
Select
1

0

1

0

This read only register contains the identity number of the chip revision. SRID is incremented on each revision.

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4.7. Floppy Disk Controller (FDC) Configuration
The generic FDC is a standard FDC with a
digital data separator, and is DP8473 and
N82077 software compatible. The FDC
supports 14 of the 17 standard FDC signals
including:
• FM and MFM modes are supported. To
select either mode, set bit 6 of the first
command byte when writing to/reading
from a diskette, where:
0 = FM mode
1 = MFM mode

• A logic 1 is returned for all floating (TRISTATE) FDC register bits upon read
cycles.
• Exceptions to standard FDC support
include:
• DRATE1 is not supported.
Table 4.61 lists the FDC functional block registers.

Table 4.61 FDC Registers
Offset

Mnemonic

00h

SRA

Status A

RO

01h

SRB

Status B

RO

02h

DOR

Digital Output

R/W

03h

TDR

Tape Drive

R/W

04h

MSR

Main Status

R

DSR

Data Rate Select

W

FIFO

Data (FIFO)

05h
06h
07h

Register Name

Type

R/W

N/A

X

DIR

Digital Input

R

CCR

Configuration Control

W

All Registers are described in the Programmers Manual

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Table 4.62 Logical Device 0 (FDC) Configuration
Index

Configuration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

60h

Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

03h

61h

Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read only, 00b.

R/W

F2h

70h

Interrupt Number

R/W

06h

71h

Interrupt Type. Bit 1 is read/write; other bits are read only.

R/W

03h

74h

DMA Channel Select

R/W

02h

75h

Report no second DMA assignment

RO

04h

F0h

FDC Configuration register

R/W

24h

F1h

Drive ID register

R/W

00h

Table 4.63 FDC Configuration Register - Index F0H
Bit

7

6

Name

Four Drive
Control

TDR
Register
Mode

Reset

0

0

5

1

Required

4

3

Reserved

Write
Protect

0

0

2

1
Reserved

1

0
TRI-STATE
Control

0

0

0

RW. This register is reset by hardware to 24h.

Bit
7

Description
Four Drive Control
0=
1=

Two floppy drives directly controlled by DR1-0 and MTR1-0 (default)
Four floppy drives controlled with the aid of external logic

Only one floppy present in ZFx86.
6

TDR Register Mode
0=
1=

PC-AT compatible drive mode; that is, bits 7-2 of the TDR are ignored (default)
Enhanced drive mode

5

Reserved

4

Reserved — Must be set to 0.

3

Write Protect
This bit allows forcing of write protect by software. When set, write to the floppy disk drive is disabled. This
effect is identical to WP when it is active.
0 = Write protected according to WP signal (default)
1 = Write protected regardless of value of WP signal

2-1

Reserved. Reset value of bit 2 is 1.

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Bit
0

Description
TRI-STATE Control
When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0 = Disabled (default)
1 = Enabled

Table 4.64 Drive ID Register - Index F1H
Bit

7

6

5

4

3

2

1

0

Name

Reserved

Drive 1 ID

Drive 0 ID

Reset

0

0

0

RW. This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in the
Enhanced mode. Usage Hints:
Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register in the
Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support
automatic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 respectively (to indicate non-valid
media sense) when the corresponding drive is selected and the Drive ID bit is reflected on bit 5 of the TDR register in
the Enhanced mode.

Bit

Description

7-4

Reserved

3-2

Drive 1 ID. When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.

1-0

Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.

4.8. Parallel Port Configuration
The SuperI/O Parallel Port supports all
IEEE1284 standard communication modes:
• Compatibility (known also as Standard or
SPP)
• Bidirectional (known also as PS/2)

• A group of 21 registers at first level offset,
sharing 14 entries. Three of these registers
(at offsets 403h, 404h, and 405h) use only
the Extended ECP mode.
• A group of four registers, used only in the
Extended ECP mode, are accessed by a
second level offset.

• FIFO, EPP (known also as Mode 4)
• ECP (with an optional Extended ECP
mode).
The Parallel Port includes two groups of
runtime registers:

The desired mode is selected by the ECR
runtime register (offset 402h). The selected
mode determines which runtime registers are
used and which address bits are used for the
base address.

4.8.1. Logical Device 1 (PP) Configuration
Table 4.65 lists the configuration registers,
their offset addresses, and the associated

ZFx86 Data Book 1.0 Rev D

modes which affect the Parallel Port. Only the
last register (F0h) is described here.

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Table 4.65 Parallel Port Configuration Registers
Index

Configuration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

60h Base Address MSB register.
Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for A10) should be set to 0b.

R/W

02h

61h Base Address LSB register.
Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP Mode 4 (EPP) or when using
the Extended registers, bit 2 (A2) should be set to 0b.

R/W

78h

70h Interrupt Number

R/W

07h

71h Interrupt Type
Bits 7-2 are read only.
Bit 1 is a read/write bit.
Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation
mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge
interrupt) in all other modes.

R/W

02h

74h DMA Channel Select

R/W

04h

75h Report no second DMA assignment

RO

04h

F0h Parallel Port Configuration register

R/W

F2h

Table 4.66 Parallel Port Configuration Register - F0H
Bit

7

6

5

Reserved

4

3

Extended
Register
Access

Name
Reset

1

1

1

Required

1

1

1

1

2
Reserved

0

0

1

0

Power
Mode
Control

TRI-STATE
Control

1

0

RW. This read/write register is reset by hardware to F2h.

Bit
7-5
4

Description
Reserved. Must be 111.
Extended Register Access
0=
1=

3-2

Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes
are ignored).
Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports
run-time configuration within the Parallel Port address space.

Reserved

ZFx86 Data Book 1.0 Rev D

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Bit
1

Description
Power Mode Control
When the logical device is active:
0 = Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is
active. Registers are maintained.
1 = Parallel port clock enabled. All operation modes are functional when the logical device is active
(default).

0

TRI-STATE Control
When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0 = Disabled (default)
1 = Enabled

4.9. System Wake-Up Control (SWC)
4.9.1. Overview
The SWC wakes up the system by sending a
power-up request to the controller, in response
to the following maskable system events:
• Modem ring (RI1 and RI2 pins)
• Telephone ring (RING input pin)
• Keyboard activity or specific programmable key sequence
• Mouse activity or specific programmable
sequence of clicks and movements
• Programmable Consumer Electronics IR
(CEIR) address
• General purpose events (S_GPWI01 and
S_GPWI02).

4.9.2. Functional Description
The SWC monitors eight system events or
activities. Each one of them is fed into a dedicated detector that decides when this event is
active, according to predetermined (either
fixed or programmable) criteria. A set of dedicated registers is used to determine the wakeup criteria, including the CEIR address and
the Keyboard sequence.

(WKCR) hold a Status bit and Enable bit,
respectively, for each one of the events.
Upon detection of any active event, the corresponding Status bit is set to 1. If the event is
enabled (the corresponding Enable bit is set
to 1), a power-up request is issued to the
controller. In addition, detection of an active
wake-up event may be also routed to any arbitrary IRQ.
Disabling an event prevents it from issuing
power-up requests, but does not affect the
Status bits. A power-up reset is issued when
both the Status and Enable bits equal 1 for at
least one event.
The SWC logic is powered by VCC_IO. The
SWC control and configuration registers are
battery backed, powered by VPP. The setup of
the wake-up events, including programmable
sequences, is retained throughout power failures (no VCC_IO) as long as the battery is
connected. VPP is taken from VCC_IO if VCC_IO
is greater than the minimum (Min) value;
otherwise, VBAT is used as the VPP source.
Hardware reset does not affect these registers. They are reset only by SuperI/O software
reset or power-up of VPP.

A Wake-Up Events Status Register (WKSR)
and a Wake-Up Events Control Register

ZFx86 Data Book 1.0 Rev D

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4
4.9.3. Event Detection
4.9.3.1. Modem Ring
High to low transitions on RI1 or RI2 indicate
the detection of ring in external modem
connected to Serial Port 1 or Serial Port 2
respectively and can be used as a wake-up
event.

4.9.3.2. Telephone Ring
A telephone ring is detected by the SWC by
processing the raw signal coming directly from
the telephone line into the RING input pin.
Detection of a pulse-train with a frequency
higher than 16 Hz that lasts at least 0.19 sec,
is used as a wake-up event.
The RING pulse-train detection is achieved by
monitoring the falling edges on RING in time
slots of 62.5 msec (a 16 Hz cycle). A positive
detection occurs if falling edges of RING are
detected in three consecutive time slots,
following a time slot in which no RING falling
edge is detected. This detection method guarantees the detection of a RING pulse-train
with frequencies higher than 16 Hz. It filters
out (does not detect) pulses of less than
10 Hz, and may detect pulses between 10 Hz
to 16 Hz.

4.9.3.3. Keyboard and Mouse Activity
The detection of either any activity or a
specific predetermined Keyboard or Mouse
activity can be used as a wake-up event.
The Keyboard wake-up detection can be
programmed to detect:
• Any keystroke
• A specific programmable sequence of up
to eight alphanumeric keystrokes
• Any programmable sequence of up to 8
bytes of data received from the keyboard.
The Mouse wake-up detection can be
programmed to detect either any Mouse click

ZFx86 Data Book 1.0 Rev D

or movement, or a specific programmable
click (left or right) or double-clicks.
The keyboard or mouse event detection operates independently of the KBC (which is
powered down with the rest of the system).

4.9.3.4. CEIR Address
A CEIR transmission received on an IRRX pin
in a pre-selected standard (NEC, RCA or
RC-5) is matched against a programmable
CEIR address. Detection of matching can be
used as a wake-up event.
Whenever an IR signal is detected, the
receiver immediately enters the active state.
When this happens, the receiver keeps
sampling the IR input signal and generates a
bit string where a logic 1 indicates an idle
condition and a logic 0 indicates the presence
of IR energy. The received bit string is de-serialized and assembled into 8-bit characters.
The expected CEIR protocol of the received
signal should be configured through bits 5,4 at
the CEIR Wake-Up Control register (see Table
4.77 on page 285).
The CEIR Wake-Up Address register (IRWAD)
holds the unique address to be compared with
the address contained in the incoming CEIR
message. If CEIR is enabled (bit 0 of the
IRWCR register is 1) and an address match
occurs, then the CEIR Event Status bit of the
WKSR register is set to 1 (see Table 4.70 on
page 280).
The CEIR Address Shift register holds the
received address which is compared with the
address contained in the IRWAD. The
comparison is affected also by the CEIR
Wake-Up Address Mask register (IRWAM) in
which each bit determines whether to ignore
the corresponding bit in the IRWAD.
If CEIR routing to interrupt request is enabled,
the assigned SWC interrupt request may be
used to indicate that a complete address has
been received. To get this interrupt when the

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address is completely received, the IRWAM
should be written with FFh. Once the interrupt
is received, the value of the address can be
read from the ADSR register.
Another parameter that is used to determine
whether a CEIR signal is to be considered
valid is the bit cell time width. There are four
time ranges for the different protocols and
carrier frequencies. Four pairs of registers
define the low and high limits of each time
range. (See ‘CEIR Wake-Up Range 0 Registers’ on page 286 (and following) for more
details regarding the recommended values for
each protocol.)
The CEIR address detection operates independently of the serial port with the IR (which
is powered down with the rest of the system).

4.9.3.5. General-Purpose Events
A general-purpose event is defined as the
detection of falling edge, rising edge, low
level, or high level on a specific signal. Each
signal’s event is configurable via software.
S_GPWI01 and S_GPWI02 may wake up the
system from power-off state, or generate an
interrupt if the system is in power-on state.
A debouncer of 16 mS is enabled (default) on
each event. It may be disabled by software.
The SWC registers are organized in two
banks. The offsets are related to a base
address that is determined by the SWC Base
Address Register in the device configuration.
The lower three registers are common to the
two banks while the upper registers (03-0fh)
are divided as follows:
• Bank 0 holds the Keyboard/Mouse Control
Registers.
• Bank 1 holds the CEIR Control Registers.
The active bank is selected through the
Configuration Bank Select field (bits 1-0) in the
Wake-Up Configuration Register (WKCFG).
See Table 4.72 on page 282.

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4
4.9.3.6. SWC Register Map
Table 4.67 Banks 0 and 1 - The Common Control and Status Register Map
Offset

Mnemonic

Name

Type

Reference

00h

WKSR

Wake-Up Events Status Register

R/W

Page 280

01h

WKCR

Wake-Up Events Control Register

R/W

Page 281

02h

WKCFG

Wake-Up Configuration Register

R/W

Page 282

Table 4.68 Bank 0 - PS/2 KBD/MOUSE Wake-Up Config/Control Register Map
Offset
03h
04h-05h

Mnemonic
PS2CTL

Name

Type

Reference

PS/2 Protocol Control Register

R/W

Page 283

Reserved

06h

KDSR

Keyboard Data Shift Register

RO

Page 284

07h

MDSR

Mouse Data Shift Register

RO

Page 284

R/W

Page 285

08h-0Fh

PS2KEY0–PS2KEY7 PS/2 Keyboard Key Data Registers

Table 4.69 Bank 1 - CEIR Wake-Up Config/Control Register Map
Offset

Mnemonic

Name

Type

Reference

CEIR Wake-Up Control Register

R/W

Page 285

03h

IRWCR

04h

Reserved

05h

IRWAD

CEIR Wake-Up Address Register

R/W

Page 286

06h

IRWAM

CEIR Wake-Up Address Mask Register

R/W

Page 286

07h

ADSR

CEIR Address Shift Register

R/O

Page 286

08h

IRWTR0L

CEIR Wake-Up, Range 0, Low Limit Register

R/W

Page 287

09h

IRWTR0H

CEIR Wake-Up, Range 0, High Limit Register

R/W

Page 287

0Ah

IRWTR1L

CEIR Wake-Up, Range 1, Low Limit Register

R/W

Page 287

0Bh

IRWTR1H

CEIR Wake-Up, Range 1, High Limit Register

R/W

Page 288

0Ch

IRWTR2L

CEIR Wake-Up, Range 2, Low Limit Register

R/W

Page 289

0Dh

IRWTR2H

CEIR Wake-Up, Range 2, High Limit Register

R/W

Page 289

0Eh

IRWTR3L

CEIR Wake-Up, Range 3, Low Limit Register

R/W

Page 289

0Fh

IRWTR3H

CEIR Wake-Up, Range 3, High Limit Register

R/W

Page 290

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4
Table 4.70 Wake-Up Events Status Register (WKSR) - 00H
Bit

Name

Reset

7

6

S_GPWI02 S_GPWI01
Event
Event
Status
Status
0

0

5

4

3

2

1

0

CEIR
Event
Status

Mouse
Event
Status

KBD
Event
Status

RING
Event
Status

RI2
Event
Status

RI1
Event
Status

0

0

0

0

0

0

R/W: This register is set to 00h on power-up of VPP or software reset. It indicates which wake-up events occurred.
Bit
7

Description
S_GPWI02 Event Status
This sticky bit shows the status of the S_GPWI02 event detection.
0 = Event not detected (default)
1 = Event detected

6

S_GPWI01 Event Status
This sticky bit shows the status of the S_GPWI01 event detection.
0 = Event not detected (default)
1 = Event detected

5

CEIR Event Status
This sticky bit shows the status of the CEIR event detection.
0 = Event not detected (default)
1 = Event detected

4

Mouse Event Status
This sticky bit shows the status of the Mouse event detection.
0 = Event not detected (default)
1 = Event detected

3

KBD Event Status
This sticky bit shows the status of the KBD event detection.
0 = Event not detected (default)
1 = Event detected

2

RING Event Status
This sticky bit shows the status of the RING event detection.
0 = Event not detected (default)
1 = Event detected

1

RI2 Event Status
This sticky bit shows the status of RI2 event detection.
0 = Event not detected (default)
1 = Event detected

0

RI1 Event Status
This sticky bit shows the status of RI1 event detection.
0 = Event not detected (default)
1 = Event detected

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4
Table 4.71 Wake-Up Events Control Register (WKCR) - 01H
Bit

7

6

S_GPWI02 S_GPWI01
Event
Event
Enable
Enable

Name

Reset

0

0

5

4

3

2

1

0

CEIR
Event
Enable

Mouse
Event
Enable

KBD
Event
Enable

RING
Event
Enable

RI2
Event
Enable

RI1
Event
Enable

0

0

0

1

1

1

R/W: This register is set to 07h on power-up of VPP or software reset. Detected wake-up events that are enabled activate issue a power-up request signal to the controller.
Bit
7

Description
S_GPWI02 Event Enable
0=
1=

6

S_GPWI01 Event Enable
0=
1=

5

Disabled
Enabled (default)

RI2 Event Enable
0=
1=

0

Disabled (default)
Enabled.

RING Event Enable
0=
1=

1

Disabled (default)
Enabled

KBD Event Enable
0=
1=

2

Disabled (default)
Enabled

Mouse Event Enable
0=
1=

3

Disabled (default)
Enabled

CEIR Event Enable
0=
1=

4

Disabled (default)
Enabled

Disabled
Enabled (default)

RI1 Event Enable
0=
1=

Disabled
Enabled (default)

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Table 4.72 Wake-Up Configuration Register (WKCFG) - 02H
Bit

7

Name

Reserved

Reset

0

6

5

4

3

2

S_GPWI02 S_GPWI02 S_GPWI01 S_GPWI01
Swap KBC
Event
Event
Event
Event
Inputs
Type
Polarity
Type
Polarity
0

0

0

0

0

1

0

Configuration Bank
Select
0

0

R/W: This register is set to 00h on power-up of VPP or software reset. It enables access to CEIR registers or to
Keyboard/Mouse registers.
Bit

Description

7

Reserved

6

S_GPWI02 Event Type
0=
1=

5

S_GPWI02 Event Polarity
0=
1=

4

Falling edge, low level
Rising edge, high level

Swap KBC Inputs
0=
1=

1-0

Edge
Level

S_GPWI01 Event Polarity
0=
1=

2

Falling edge, low level
Rising edge, high level

S_GPWI01 Event Type
0=
1=

3

Edge
Level

No swapping (default)
KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped

Configuration Bank Select
Bits
1 0
0 0
0 1
1 X

Bank Selected
Keyboard/Mouse Registers (Bank 0)
CEIR Registers (Bank 1)
Reserved

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4
4.9.3.7. PS/2 Keyboard and Mouse Wake-Up Events
The SWC can be configured to detect any
predetermined PS/2 keyboard or mouse
activity.

Mouse Wake-Up Events
Program the mouse wake-up detection mechanism to detect either any mouse click or
movement, or a specific programmable click
(left or right) or double-click.

The detection mechanisms for keyboard and
mouse events are independent. Therefore,
they can be operated simultaneously with no
interference. Since both mechanisms are
implemented by hardware which is independent of the device’s keyboard controller, the
keyboard controller itself need not be activated to detect either keyboard or mouse
events. See the ZFx86 User’s Guide for more
information.

To program this mechanism to wake-up on a
specific event, set bits 6-4 of the PS2CTL
register to the required value, according to the
description of these bits in Table 4.73.

Table 4.73 PS/2 Protocol Control Register (PS2CTL) (Bank 0 Offset 03H)
Bit

7

6

Name

Disable
Parity
Check

Reset

0

5

4

3

Mouse Wake-Up Configuration

0

0

0

2

1

0

Keyboard Wake-Up Configuration

0

0

0

0

R/W: This register is set to 00h on power-up of VPP or software reset. It configures the PS/2 Keyboard and Mouse
wake-up features
Bit
7
6-4

Description
Disable Parity Check
Mouse Wake-Up Configuration
6
0
0
0
0
1
1
1
1

Bits
5 4
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1

Configuration
Disable Mouse wake-up detection
Wake-up on any Mouse movement or button click
Wake-up on left button click
Wake-up on left button double-click
Wake-up on right button click
Wake-up on right button double-click
Wake-up on any button single-click (left, right or middle)
Wake-up on any button double-click (left, right or middle)

ZFx86 Data Book 1.0 Rev D

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4
Bit
3-0

Description
Keyboard Wake-Up Configuration
Bits
3 2 1 0
0 0 0 0
0 0 0 1
to
0 1 1 1
1 0 0 0
to
1 1 1 1

Configuration
Disable Keyboard wake-up detection

}
}

Special key seq 2-8 PS/2 scan codes, “Make” and “Break” (incl Shift, Alt keys)

Password enabled with 1-8 keys “Make” code (excluding Shift and Alt keys)

Table 4.74 Keyboard Data Shift Register (KDSR) - Bank 0 Offset 06H
Bit

7

6

5

4

3

Name

Keyboard Data

Reset

0

2

1

0

R/O: This register is set to 00h on power-up of VPP or software reset. It stores the Keyboard data shifted in from the
Keyboard during transmission, only when Keyboard wake-up detection is enabled.

Table 4.75 Mouse Data Shift Register (MDSR) 07H
Bit

7

6

5

4

3

2

1

Name

Reserved

Mouse Data

Reset

0

0

0

R/O: This register is set to 00h on power-up of VCC_IO or software reset. It stores the Mouse data shifted in from the
Mouse during transmission, only when Mouse wake-up detection is enabled.

4.9.3.8. PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7)
Eight registers (PS2KEY0-PS2KEY7) store
the scan codes for the password or key
sequence of the keyboard wake-up feature, as
follows:
• PS2KEY0 register stores the scan code
for the first key in the password/key
sequence.
• PS2KEY1 register stores the scan code
for the second key in the password/key
sequence.

ZFx86 Data Book 1.0 Rev D

• PS2KEY2 - PS2KEY7 registers store the
scan codes for the third to eighth keys in
the password/key sequence.
When one of these registers is set to 00h, it
indicates that the value of the corresponding
scan code byte is ignored (not compared).
These registers are set to 00h on power-up of
VPP or software reset.
Location:

Bank 0, Offset 08h-0Fh

Type:

R/W

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4
Table 4.76 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7)
Bit

7

6

5

Name

4

3

2

1

0

0

0

0

Scan Code of Keys 0-7

Reset

0

0

0

0

0

Table 4.77 CEIR Wake-Up Control Register (IRWCR) - Bank 1 Offset 3
Bit

7

Name

6

Reserved

Reset

0

5

4

CEIR Protocol Select

0

0

3

2

1

0

Select
IRRX2
Input

Invert
IRRXn
Input

Reserved

CEIR
Enable

0

0

0

0

0

R/W: This register is set to 00h on power-up of VPP or software reset.
Bit

Description

7-6

Reserved

5-4

CEIR Protocol Select
Bits
5 4
0 0
0 1
1 X

3

Protocol
RC5
NEC/RCA
Reserved

Select IRRX2 Input.
This selects the IRRX input.
0 = IRRX1 (default)
1 = IRRX2

2

Invert IRRXn Input
0=
1=

Not inverted (default)
Inverted

1

Reserved

0

CEIR Enable
0=
1=

Disabled (default)
Enabled

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4
Table 4.78 CEIR Wake-Up Address Register (IRWAD) - Bank 1 Offset 05H
Bit

7

6

5

4

3

Name

CEIR Wake-Up Address

Reset

0

2

1

0

R/W: This register defines the station address to be compared with the address contained in the incoming CEIR
message. If CEIR is enabled (bit 0 of the IRWCR Register is 1) and an address match occurs, then bit 5 of the WKSR
Register is set to 1 (see Table 4.70, “Wake-Up Events Status Register (WKSR) - 00H,” on page 280).
This register is set to 00h on power-up of VPP or software reset.

Table 4.79 CEIR Wake-Up Address Mask Register (IRWAM) - Bank 1 Offset 6
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

CEIR Wake-Up Address Mask
1

1

1

0

0

R/W: Each bit in this register determines whether the corresponding bit in the IRWAD Register takes part in the
address comparison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected.
This register is set to E0h on power-up of VPP or software reset.
Bit
7-0

Description
CEIR Wake-Up Address Mask
If the corresponding bit is 0, the address bit is not masked (enabled for compare). If the corresponding bit
is 1, the address bit is masked (ignored during compare).

Table 4.80 CEIR Address Shift Register (ADSR) - Bank 1 Offset 7
Bit

7

6

5

4

3

Name

CEIR Address

Reset

0

2

1

0

R/O: This register holds the received address to be compared with the address contained in the IRWAD register.
This register is set to 00h on power-up of VPP or software reset.

CEIR Wake-Up Range 0 Registers
These registers define the low and high limits
of time range 0. The values are represented in
units of 0.1 msec.
For the RC-5 protocol, the bit cell width must
fall within this range for the cell to be consid-

ZFx86 Data Book 1.0 Rev D

ered valid. The nominal cell width is 1.778
msec for a 36 KHz carrier. IRWTR0L and
IRWTR0H should be set to 10h and 14h
respectively (default).
For the NEC protocol, the time distance
between two consecutive CEIR pulses that

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4
encodes a bit value of 0 must fall within this
range. The nominal distance for a 0 is1.125
msec for a 38 KHz carrier. IRWTR0L and

IRWTR0H should be set to 09h and 0Dh
respectively.

Table 4.81 CEIR Wake-Up Range 0 Registers - IRWTR0L– Bank 1 Offset 8
Bit

7

Name
Reset

6

5

4

Reserved
0

0

3

2

1

0

CEIR Pulse Change, Range 0, Low Limit
0

1

0

0

0

0

R/W: This register is set to 10h on power-up of VPP or software reset.

Table 4.82 CEIR Wake-Up Range 0 Registers - IRWTR0H – Bank 1 Offset 9
Bit

7

Name
Reset

6

5

4

Reserved
0

0

3

2

1

0

CEIR Pulse Change, Range 0, High Limit
0

1

0

1

0

0

R/W: This register is set to 14h on power-up of VPP or software reset.

CEIR Wake-Up Range 1 Registers

carrier. IRWTR1L and IRWTR1H should be
set to 07h and 0Bh respectively (default).

These registers define the low and high limits
of time range 1. The values are represented in
units of 0.1 msec.

For the NEC/RCA protocol, the time between
two consecutive CEIR pulses that encodes a
bit value of 1 must fall within this range. The
nominal time for a 1 is 2.25 msec for a 36 KHz
carrier. IRWTR1L and IRWTR1H should be
set to 14h and 19h respectively.

For the RC-5 protocol, the pulse width defining
a half-bit cell must fall within this range in
order for the cell to be considered valid. The
nominal pulse width is 0.889 for a 38 KHz

Table 4.83 CEIR Wake-Up Range 1 Registers - IRWTR1L – Bank 1 Offset 0AH
Bit

7

6

Name

Reserved

Reset

0

5

4

3

2

1

0

CEIR Pulse Change, Range 1, Low Limit
0

0

1

1

1

R/W: This register is set to 07h on power-up of VPP or software reset.

ZFx86 Data Book 1.0 Rev D

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Table 4.84 CEIR Wake-Up Range 1 Registers - IRWTR1H – Bank 1 Offset 0BH
Bit

7

6

Name

Reserved

Reset

0

5

4

3

2

1

0

CEIR Pulse Change, Range 1, High Limit
0

1

0

1

1

R/W: This register is set to 0Bh on power-up of VPP or software reset.

ZFx86 Data Book 1.0 Rev D

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4
For the NEC/RCA protocol, the header pulse
width must fall within this range in order for the
header to be considered valid. The nominal
value is 9 msec for a 38 KHz carrier. IRWTR2L
and IRWTR2H should be set to 50h and 64h
respectively (default).

CEIR Wake-Up Range 2 Registers
These registers define the low and high limits
of time range 2. The values are represented in
units of 0.1 msec. These registers are not
used when the RC-5 protocol is selected.

Table 4.85 CEIR Wake-Up Range 2 Registers - IRWTR2L – Bank 1 0CH)
Bit

7

6

Name
Reset

5

4

3

2

1

0

0

0

CEIR Pulse Change, Range 2, Low Limit
0

1

0

1

0

0

R/W: This register is set to 50h on power-up of Vpp or software reset.

Table 4.86 CEIR Wake-Up Range 2 Registers - IRWTR2H – Bank 1 0DH
Bit

7

6

Name
Reset

5

4

3

2

1

0

0

0

CEIR Pulse Change, Range 2, High Limit
0

1

1

0

0

1

R/W: This register is set to 64h on power-up of Vpp or software reset.

For the NEC protocol, the post header gap
width must fall within this range in order for the
gap to be considered valid. The nominal value
is 4.5 msec for a 36 KHz carrier. IRWTR3L
and IRWTR3H should be set to 28h and 32h
respectively (default).

CEIR Wake-Up Range 3 Registers
These registers define the low and high limits
of time range 3. The values are represented in
units of 0.1 msec. These registers are not
used when the RC-5 protocol is selected.

Table 4.87 CEIR Wake-Up Range 3 Registers - IRWTR3L – Bank 1 OEH
Bit

7

6

Name
Reset

5

4

3

2

1

0

0

0

CEIR Pulse Change, Range 3, Low Limit
0

0

1

0

1

0

R/WS: This register is set to 28h on power-up of Vpp or software reset.

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Table 4.88 CEIR Wake-Up Range 3 Registers - IRWTR3H – Bank 1 OFH
Bit

7

6

5

Name
Reset

4

3

2

1

0

1

0

CEIR Pulse Change, Range 3, High Limit
0

0

1

1

0

0

R/W: This register is set to 32h on power-up of Vpp or software reset.

CEIR Recommended Values
Table 4.89 lists the recommended time ranges
limits for the different protocols and their four

applicable ranges. The values are represented in hexadecimal code where the units
are of 0.1 msec.

Table 4.89 Time Range Limits for CEIR Protocols
RC-5

NEC

RCA

Range
Low Limit

High Limit

Low Limit

0

10h

14h

1

07h

2
3

ZFx86 Data Book 1.0 Rev D

High Limit Low Limit

High Limit

09h

0Dh

0Ch

12h

0Bh

14h

19h

16h

1Ch

-

-

50h

64h

B4h

DCh

-

-

28h

32h

23h

2Dh

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4.9.4. SWC Register Bitmap
Table 4.90 Banks 0 and 1 - The Common Three-Register Map
Register

Bits

Offset Mnemonic

7

6

5

4

3

2

1

0

00h

WKSR

S_GPWI02
Event
Status

S_GPWI01
Event
Status

CEIR
Event
Status

Mouse
Event
Status

KBD
Event
Status

RING
Event
Status

RI2
Event
Status

RI1
Event
Status

01h

WKCR

S_GPWI02
Event
Enable

S_GPWI01
Event
Enable

CEIR
Event
Enable

Mouse
Event
Enable

KBD
Event
Enable

RING
Event
Enable

RI2
Event
Enable

RI1
Event
Enable

02h

WKCFG
Reserved

S_GPWI01
S_GPWI02
Swap KBC
S_GPWI01
S_GPWI02
Event
Event
Inputs
Event Type
Event Type
Polarity
Polarity

Configuration Bank
Select

Table 4.91 Bank 0 - PS/2 Keyboard/Mouse Wake-Up Config/Ctrl Registers
Register

Bits

Offset

Mnemonic

7

03h

PS2CTL

Disable
Parity

6

5

4

3

Mouse Wake-Up Configuration

04-05

2

1

0

Keyboard Wake-Up Configuration

Reserved

06h

KDSR

07h

MDSR

08-0F

PS2KEY0PS2KEY7

Keyboard Data
Reserved

Mouse Data
Scan Code of Keys 0-7

Table 4.92 CEIR Wake-Up Configuration and Control Registers
Register
Offset

Mnemonic

03h

IRWCR

Bits
7

6

Reserved
04h

5

4

CEIR
Protocol Select

3

2

1

0

Select
IRRX2
Input

Invert
IRRXn
Input

Reserved

CEIR
Enable

Reserved

05h

IRWAD

CEIR Wake-Up Address

06h

IRWAM

CEIR Wake-Up Address Mask

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Table 4.92 CEIR Wake-Up Configuration and Control Registers
07h

ADSR

CEIR Address

08h

IRWTR0L

Reserved

CEIR Pulse Change, Range 0, Low Limit

09h

IRWTR0H

Reserved

CEIR Pulse Change, Range 0, High Limit

0Ah

IRWTR1L

Reserved

CEIR Pulse Change, Range 1, Low Limit

0Bh

IRWTR1H

Reserved

CEIR Pulse Change, Range 1, High Limit

0Ch

IRWTR2L

CEIR Pulse Change, Range 2, Low Limit

0Dh

IRWTR2H

CEIR Pulse Change, Range 2, High Limit

0Eh

IRWTR3L

CEIR Pulse Change, Range 3, Low Limit

0Fh

IRWTR3H

CEIR Pulse Change, Range 3, High Limit

4.9.4.1. Serial Port 1 And Serial Port 2 Configuration
Serial Ports 1 and 2 are identical, except for
their reset values as shown in Table 4.93
below.
Logical Devices 2 and 3 (SP2 and SP1)
Configuration

Serial Port 1 is designated as logical device 3,
and Serial Port 2 as logical device 2.
Table 4.93 lists the configuration registers
which affect Serial Ports 1 and 2. Only the last
register (F0h) is described here. See Sections
4.5.5 and 4.5.6 for descriptions of the others.

Table 4.93 Serial Ports 1 and 2 Configuration Registers
Type

Reset
Port 1

Reset
Port 2

30h Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

00h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

03h

02h

61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b.

R/W

F8h

F8h

70h Interrupt Number

R/W

04h

03h

71h Interrupt Type. Bit 1 is R/W; other bits are read only.

R/W

03h

03h

74h Report no DMA Assignment

RO

04h

04h

75h Report no DMA Assignment

RO

04h

04h

F0h Serial Ports 1 and 2 Configuration register

R/W

02h

02h

Index

Configuration Register or Action

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Table 4.94 Serial Ports 1 and 2 Configuration Register - F0H
Bit

7

Name

Bank
Select
Enable

Reset

0

6

5

4

3

Reserved

0

0

0

0

2

1

0

Busy
Indicator

Power
Mode
Control

TRI-STATE
Control

0

1

0

RW. This register is reset by hardware to 02

Bit
7

Description
Bank Select Enable
Enables bank switching for Serial Ports 1 and 2.
0 = Disabled (default).
1 = Enabled

6-3
2

Reserved
Busy Indicator
Read only bit used by power management software to decide when to power-down Serial Ports 1 and 2
logical devices.
0 = No transfer in progress (default).
1 = Transfer in progress.

1

Power Mode Control
When the logical device is active in:
0 = Low power mode
Serial Ports 1 and 2 Clock disabled. The output signals are set to their default states. The RI input
signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in
Index 30 that also prevents access to Serial Ports 1 or 2 registers.)
1 = Normal power mode
Serial Ports 1 and 2 clock enabled. Serial Ports 1 and 2 are functional when the respective logical
devices are active (default).

0

TRI-STATE Control
Controls the TRI-STATE status of the device output pins when it is inactive (disabled).
0 = Disabled (default)
1 = Enabled when device inactive

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4.9.4.2. System Wake-Up Control (SWC) — Logical Device 4
Table 4.95 System Wake-Up Control (SWC) Configuration
Index

Configuration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not accessible.a

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.

R/W

00h

70h

Interrupt Number (For routing the internal PWUREQ signal).

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

RO

04h

75h

Report no DMA assignment

RO

04h

a. The logical device registers are maintained, and all wake-up detection mechanisms are functional.

4.9.5. Keyboard/Mouse Control
The KBC is implemented physically as a
single hardware module and houses two
separate logical devices: a Mouse controller
(logical device 5) and a Keyboard controller
(logical device 6).

P10, P11, P13-P16, P22-P27 of the KBC core
are not available on dedicated pins; neither
are T0 and T1, P10, P11, P22, P23, P26, P27,
T0 and T1 are used to implement the
Keyboard and Mouse interface.

The hardware KBC module is integrated to
provide the following pin functions: KBLOCK
(P17), KBDAT, KBCLK, MDAT, and MCLK.
KBLOCK is implemented as bi-directional,
open-drain pins. The Keyboard and Mouse
interfaces are implemented as bi-directional,
open-drain pins. Their internal connections
are shown in Figure 4-8.

The KBC executes a program fetched from an
on-chip 2Kbyte ROM. The code programmed
in this ROM is user-customizable. The KBC
has two interrupt request signals: one for the
Keyboard and one for the Mouse. The interrupt requests are implemented using ports
P24 and P25 of the KBC core. The interrupt
requests are controlled exclusively by the KBC
firmware, except for the type and number,
which are affected by configuration registers.

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The interrupt requests are implemented as bidirectional signals. When an I/O port is read,
all unused bits return the value latched in the
output registers of the ports.

For KBC firmware that implements interrupton-OBF schemes, it is recommended to implement it as follows:
• Put the data in DBBOUT.
• Set the appropriate port bit to issue an
interrupt request..

KBC
Internal Interface Bus

P17

KBLOCK

P26

KBCLK

STATUS
DBBIN
T0
DBBOUT

P27

KBDAT

P10
P23

MCLK

T1
KBD IRQ
Plug and
Play
Matrix

P24
Mouse IRQ

P22

MDAT

P11
P25

Figure 4-8 Keyboard and Mouse Interfaces

4.9.5.1. Logical Devices 5 and 6 (Mouse and Keyboard) Configuration
Tables 4.96 and 4.97 list the configuration
registers which affect the Mouse and the
Keyboard respectively. Only the last register

(F0h) is described here. See Sections 4.5.5
and 4.5.6 for descriptions of the others.

Table 4.96 Mouse Configuration Registers
Index

Mouse Configuration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1. When the Mouse of the KBC is inactive, the
IRQ selected by the Mouse Interrupt Number register (index 70h) is not asserted.
This register has no effect on host KBC commands handling the PS/2 Mouse.

R/W

00h

70h

Mouse Interrupt Number

R/W

0Ch

71h

Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only.

R/W

02h

74h

Report no DMA assignment

RO

04h

75h

Report no DMA assignment

RO

04h

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Table 4.97 Keyboard Configuration Registers
Index

Keyboard Configuration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1.

R/W

01h

60h

Data Port Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

00h

61h

Data Port Base Address LSB register. Bits 2-0 are read only 000b.

R/W

60h

62h

Command Port Base Address MSB register. Bits 7-3 (for A15-11) are read only,
00000b.

R/W

00h

63h

Command Port Base Address LSB. Bits 2-0 are read only 100b.

R/W

64h

70h

KBC Interrupt Number

R/W

01h

71h

KBC Interrupt Type. Bits 1,0 are read/write; others are read only.

R/W

02h

74h

Report no DMA assignment

RO

04h

75h

Report no DMA assignment

RO

04h

F0h

KBC Configuration register

R/W

40h

Table 4.98 iKBC Configuration Register - F0H
Bit

7

6

5

4

KBC Clock Source

Name
Reset

0

1

3

2

1

Reserved
0

0

0

Required

0
TRI-STATE
Control

0

0

0

0

RW. This register is reset by hardware to 40H. To change the clock frequency of the KBC, perform the following:
1. Disable the KBC logical devices.
2. Change the frequency setting.
3. Enable the KBC logical devices.

Bit
7-6

Description
KBC Clock Source
The clock source can be changed only when the KBC is inactive (disabled).
Bits
7 6
0
0
1
1

5-1

0
1
0
1

Function
8 MHz
12 MHz (default)
16 MHz
Reserved

Reserved. Use read-modify-write to change the value of the register. Do not change the value of these bits.
Bit 2 must be 0.

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Bit

Description

0

TRI-STATE Control
If KBD is inactive (disabled) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRI-STATE.
If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE.
0 = Disabled (default)
1 = Enabled

4.9.6. Infrared Communication Port Configuration
Table 4.99 lists the configuration registers which affect the Infrared Communication Port. Only the
last register (F0h) is described here. See Sections 4.5.5 and 4.5.6 for descriptions of the others.
Table 4.99 Infrared Communication Port Configuration Registers
Index

Configuration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

03h

61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b.

R/W

E8h

70h Interrupt Number

R/W

00h

71h Interrupt Type. Bit 1 is R/W; other bits are read only.

R/W

03h

74h DMA Channel Select 0 (RX_DMA)

R/W

04h

75h DMA Channel Select 1 (TX_DMA)

R/W

04h

F0h Infrared Communication Port Configuration register

R/W

02h

Table 4.100 Infrared Communication Port Configuration Register - F0H
Bit

7

Name

Bank
Select
Enable

Reset

0

6

5

4

3

Reserved

0

0

0

2

1

0

Busy
Indicator

Power
Mode
Control

TRI-STATE
Control

0

1

0

0

RW. This register is reset by hardware to 02H

Bit
7

Description
Bank Select Enable
Enables bank switching.
0 = All attempts to access the extended registers are ignored (default).
1 = Enables bank switching.

6-3

Reserved

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Bit
2

Description
Busy Indicator
This read only bit can be used by power management software to decide when to power-down the device.
0 = No transfer in progress (default).
1 = Transfer in progress.

1

Power Mode Control
When the logical device is active in:
0 = Low power mode
Clock disabled. The output signals are set to their default states. The RI input signal can be
programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also
prevents access to device registers.)
1 = Normal power mode
Clock enabled. The device is functional when the logical device is active (default).

0

TRI-STATE Control
When enabled and the device is inactive, the logical device output pins are in TRI-STATE. One exception
is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit.
0 = Disabled (default)
1 = Enabled

4.10. ACCESS.Bus Interface (ACB) Configuration
The ACB is a two-wire synchronous serial
interface compatible with the ACCESS.bus
physical layer.

The ACB uses a 24 MHz internal clock. The
six runtime registers are shown below.

Table 4.101 ACB Runtime Registers
Offset Mnemonic

ZFx86 Data Book 1.0 Rev D

Register Name

Type

00h

ACBSDA

ACB Serial Data

01h

ACBST

ACB Status

Varies per bit

02h

ACBCST

ACB Control Status

Varies per bit

03h

ACBCTL1

ACB Control 1

04h

ACBADDR ACB Own Address

R/W

05h

ACBCTL2

R/W

ACB Control 2

R/W

R/W

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Table 4.102 Access Bus Interface (ACB) Configuration
Index

Configuration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1 register

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b.

R/W

00h

70h

Interrupt Number

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

RO

04h

75h

Report no DMA assignment

RO

04h

F0h

ACB Configuration register

R/W

00h

Table 4.103 ACB Configuration Register – F0H
Bit

7

6

5

4

3

Reserved

0

0

0

1

Internal
Pull-Up
Enable

Name
Reset

2

0

0

0

0
Reserved

0

0

This register is reset by hardware to 00H.
Bit
7-3
2

Description
Reserved
Internal Pull-Up Enable
0=
1=

1-0

No internal pull-up resistors on SCL and SDA (default)
Internal pull-up resistors on SCL and SDA

Reserved

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4.11. Real-time Clock (RTC)
Table 4.104 shows the logical Device A real
time clock configuration settings.
Table 4.104 Logical Device A (RTC) Configuration
Index

Configuration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not accessible.a

R/W

00h

60h

Standard Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

00h

61h

Standard Base Address LSB register. Bit 0 (for A0) is read only, 0b.

R/W

70h

62h

Extended Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

00h

63h

Extended Base Address LSB register. Bit 0 (for A0) is read only, 0b.

R/W

72h

70h

Interrupt Number

R/W

08h

71h

Interrupt Type. Bit 1 is R/W; other bits are read only.

R/W

00h

74h

Report no DMA Assignment

R/W

04h

75h

Report no DMA Assignment

R/W

04h

F0h

RAM Lock register (RLR)

R/W

00h

F1h

Date of Month Alarm Offset register (DOMAO)

R/W

00h

F2h

Month Alarm Offset register (MONAO)

R/W

00h

F3h

Century Offset register (CENO)

R/W

00h

a. The logical device registers are maintained, and all RTC mechanisms are functional.

Table 4.105 RAM Lock Register (RLR) - F0H
Bit

7

Name

Block
Standard
RAM

Reset

0

6

5

4

3

2

Block
Block
Block
Block
Extended Extended Extended
RAM Write
RAM Write RAM Read
RAM
0

0

0

0

1

0

Reserved

0

0

0

R/W: When a non-reserved bit is set to 1, it can be cleared only by hardware reset.
Bit
7

Description
Block Standard RAM
0=
1=

No effect on Standard RAM access (default)
Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads
return FFh

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Bit
6

Description
Block RAM Write
0=
1=

5

No effect on RAM access (default)
Writes to RAM (Standard and Extended) are ignored

Block Extended RAM Write.
This bit controls writes to bytes 00h-1Fh of the Extended RAM.
0 = No effect on the Extended RAM access (default)
1 = Writes to bytes 00h-1Fh of the Extended RAM are ignored

4

Block Extended RAM Read
This bit controls read from bytes 00h-1Fh of the Extended RAM.
0 = No effect on Extended RAM access (default)
1 = Reads to bytes 00h-1Fh of the Extended RAM are ignored

3

Block Extended RAM
This bit controls access to the Extended RAM 128 bytes.
0 = No effect on Extended RAM access (default)
1 = Read and write to the Extended RAM are blocked: writes are ignored and reads return FFh

2-0

Reserved

Table 4.106 Date Of Month Alarm Register Offset (DOMAO) – F1H
Bit

7

6

Name

Reserved

Reset

0

5

4

3

2

1

0

0

0

1

0

0

0

Date of Month Alarm Register Offset Value
0

0

0

0

0

R/W
Bit
7
6-0

Description
Reserved
Date of Month Alarm Register Offset Value

Table 4.107 Month Alarm Register Offset (MAO) – F2H
Bit

7

Name

Reserved

Reset

0

6

5

4

3

2

Month Alarm Register Offset Value
0

0

0

0

0

R/W
Bit
7
6-0

Description
Reserved
Month Alarm Register Offset Value

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Table 4.108 Century Register Offset (CENO0) – F3H
Bit

7

Name

Reserved

Reset

0

6

5

4

3

2

1

0

0

0

Century Register Offset Value
0

0

0

0

0

R/W
Bit
7
6-0

Description
Reserved
Century Register Offset Value

4.11.1. RTC Overview
The RTC provides timekeeping and calendar
management capabilities. The RTC uses a
32.768 KHz signal as the basic clock for timekeeping. It also includes 242 bytes of batterybacked RAM for general-purpose use.
The RTC provides the following functions:

• Automatic switching from battery to
VCC_IO
• Internal power monitoring on the VRT bit
• Oscillator disabling to save battery during
storage
• Software compatible with the DS1287 and
MC146818

• Accurate timekeeping and calendar
management

4.11.2. Functional Description

• Alarm at a predetermined time and/or date

4.11.2.1. Bus Interface

• Three programmable interrupt sources
• Valid timekeeping during power-down, by
utilizing external battery backup
• 242 bytes of battery-backed RAM

The RTC function is initially mapped to the
default SuperI/O locations at indexes 70h to
73h (two Index/Data pairs). These locations
may be reassigned, in compliance with Plug
and Play requirements.

• Internal oscillator circuit (the crystal itself is
off-chip), or external clock supply for the
32.768KHz clock

To access Bank 1, you most set the RAMSEL
bit to ONE. RAMSEL bit is located at the
general configuration registers, at bit 5 of the
KRR (Keyboard and RTC Control Register), at
index 0516.

• A century counter

4.11.2.2. RTC Clock Generation

• RAM lock schemes to protect its content

• PnP support
• Relocatable index and data registers
• Module access enable/disable option

The RTC uses a 32.768 KHz clock signal as
the basic clock for timekeeping. The
32.768 KHz clock can be supplied by the i48
MHz clock, or by an oscillator (see Section
5.11. ‘System Clocking’ on page 447).

• Host interrupt enable/disable option
• Additional low-power features such as:

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4.11.2.3. Timing Generation
The timing generation function divides the
32.768 KHz clock by 215 to derive a 1 Hz
signal, which serves as the input for the
seconds counter. This is performed by a
divider chain composed of 15 divide-by-two
latches, as shown in Figure 4-9.

becomes active after half of the programmed
period has elapsed, following divider chain
activation.
See Table 4.126 on page 314 for more details.

4.11.2.4. Timekeeping
Data Format

DIVIDER CHAIN
1
2

2
2

3
2

13 14 15
2 2 2

1 Hz

Note: When changing the above formats, reinitialize all the time registers.

Reset
DV2 DV1 DV0
6

5

Daylight Saving

4

Control Register A (CRA)
32.768 KHz
To other
modules

X1C

Osc
Enable

X2C

Figure 4-9 Divider Chain Control

Bits 6-4 (DV2-0) of the CRA Register control
the following functions:
• Normal operation of the divider chain
(counting)
• Divider chain reset to 0
• Oscillator activity when only VBAT power is
present (backup state).
The divider chain can be activated by setting
normal operational mode (bits 6-4 of CRA).
The first update occurs 500 ms after divider
chain activation.
Bits 3-0 of the CRA Register select one the of
fifteen taps from the divider chain to be used
as a periodic interrupt. The periodic flag

ZFx86 Data Book 1.0 Rev D

Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B
(CRB), and in either 12 or 24-hour format, as
determined by bit 1 of this register.

Daylight saving time exceptions are handled
automatically, as described in Table 4.129,
“RTC Control Register B (CRB) - 0BH,” on
page 316.
Leap Years
Leap year exceptions are handled automatically by the internal calendar function. Every
four years, February is extended to 29 days.
Year 2000 is a leap year.

4.11.2.5. Updating
The time and calendar registers are updated
once per second regardless of bit 7 (SET) of
the CRB Register. Since the time and
calendar registers are updated serially, unpredictable results may occur if they are
accessed during the update. Therefore, you
must ensure that reading or writing to the time
storage locations does not coincide with a
system update of these locations. There are
several methods to avoid this contention.
Method 1
1. Set bit 7 of the CRB Register to 1. This
takes a “snapshot” of the internal time registers and loads them into the user copy registers. The user copy registers are seen
when accessing the RTC from outside, and

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are part of the double buffering mechanism.
You may keep this bit set for up to 1 second,
since the time/calendar chain continue to be
updated once per second.
2. Read or write the required registers (since
bit 1 is set, you access the user copy
registers). If you perform a read operation,
the information you read is correct from the
time when bit 1 was set. If you perform a
write operation, you write only to the user
copy registers.
3. Reset bit 1 to 0. During the transition, the
user copy registers update the internal
registers, using the double buffering
mechanism to ensure that the update is
performed between two time updates. This
mechanism enables new time parameters
to be loaded in the RTC.
Method 2
1. Access the RTC registers after detection of
an Update Ended interrupt. This implies that
an update has just been completed and 999
ms remain until the next update.
2. To detect an Update Ended interrupt, you
may either:
a. Poll bit 4 of the CRC Register.
b. Use the following interrupt routine:
— Set bit 4 of the CRB Register.
— Wait for an interrupt from interrupt pin.
— Clear the IRQF flag of the CRC Register before exiting the interrupt routine.

Method 3
Poll bit 7 of the CRA Register. The update
occurs 244 ms after this bit goes high. Therefore, if a 0 is read, the time registers remain
stable for at least 244 ms. See Table 4.126 on
page 314.

2.

Set bit 6 of the CRB Register to enable
the interrupt from periodic interrupt.

3.

Wait for the periodic interrupt appearance. This indicates that the period represented by the following expression
remains until another update occurs:
[(Period of periodic interrupt / 2) +
244 ms]

4.11.2.6. Alarms
The timekeeping function can be set to
generate an alarm when the current time
reaches a stored alarm time. After each RTC
time update (every 1 second), the seconds,
minutes, hours, date of month and month
counters are compared with their corresponding registers in the alarm settings. If
equal, bit 5 of the CRC Register is set. If the
Alarm Interrupt Enable bit was previously set
(bit 5 of the CRB Register), interrupt request
pin will also be active.
Any alarm register may be set to “Unconditional Match” by setting bits 7 and 6 to 11. This
combination, not used by any BCD or binary
time codes, results in a periodic alarm. The
rate of this periodic alarm is determined by the
registers that were set to “Unconditional
Match”.
For example, if all but the seconds and
minutes alarm registers are set to “Unconditional Match”, an interrupt generates every
hour at the specified minute and second. If all
but the seconds, minutes and hours alarm
registers are set to “Unconditional Match”, an
interrupt generates every day at the specified
hour, minute and second.

Method 4
Use a periodic interrupt routine to determine if
an update cycle is in progress, as follows:
1.

Set the periodic interrupt to the desired
period.

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4.11.2.7. Power Supply
The device is supplied from three supply voltages.
• System power supply voltage, VCC.
• System power supply voltage, VCC_IO
• Backup voltage, from low capacity Lithium
battery, VBAT
Note: The ZFx86 contains no reverse polarity
protection.
The RTC is supplied from one of two power
supplies, VCC_IO or VBAT, according to their
levels. An internal voltage comparator delivers
the control signals to a pair of switches.
Battery backup voltage VBAT maintains the
correct time and saves the CMOS memory
when the external voltage is absent, due to
power failure or disconnection of the external
AC/DC input power supply.
To assure that the module uses power from
the external source and not from VBAT, the
voltage should be maintained above its
minimum.
The actual voltage point where the module
switches from VBAT to VCC_IO is lower than the
minimum workable battery voltage, but high
enough to guarantee the correct functionality
of the oscillator and the CMOS RAM.

4.11.2.8. System Bus Lockout
During power on or power off, spurious bus
transactions from the host may occur. To
protect the RTC internal registers from corruption, all inputs are automatically locked out.
The lockout condition is asserted when VCC_IO
is lower than VBAT.

4.11.2.9. Power-Up Detection
When system power is restored after a power
failure or power off state, the lockout condition
continues for a delay of 62 ms (minimum) to
125 ms (maximum) after the RTC switches
from battery to system power.

ZFx86 Data Book 1.0 Rev D

The lockout condition is switched off immediately in the following situations:
• If the Divider Chain Control bits, DV0-2,
(bits 6-4 in the CRA Register) specify a
normal operation mode (01X or 100), all
input signals are enabled immediately
upon detection of system voltage above
that of the battery voltage. See Table
4.126 on page 314
• When battery voltage is below 1 Volt and
HMR is 1, all input signals are enabled
immediately upon detection of system
voltage above that of battery voltage. This
also initializes registers at offsets 00h
through 0Dh in the ZF-Logic See Table 5.2
on page 406.
• If bit 7 (VRT) of the CRD Register is 0, all
input signals are enabled immediately
upon detection of system voltage above
VBAT.

4.11.2.10. Oscillator Activity
The RTC oscillator is active if:
• VCC_IO power supply is higher than its
minimum specified at the DC spec, independent of the battery voltage, VBAT
• VBAT power supply is higher than VBATMIN,
regardless if VCC_IO is present or not.
The RTC oscillator is disabled if:
• During power-down (VBAT only), the
battery voltage drops below VBATMIN.
When this occurs, the oscillator may be
disabled and its functionality cannot be
guaranteed.
• Software wrote 00X to DV2-0 bits of the
CRA Register (see Table 4.126 on page
314) and VCC_IO is removed. This
disables the oscillator and decreases the
power consumption from the battery
connected to the VBAT pin. When disabling

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the oscillator, the CMOS RAM is not
affected as long as the battery is present
at a correct voltage level.
If the RTC oscillator becomes inactive, the
following features will be dysfunctional/disabled:
• Timekeeping

the CRC Register, and then deal with all
pending interrupts by referring to this stored
status.
If an interrupt is not serviced before a second
occurrence of the same interrupt condition, the
second interrupt event is lost. Figure 4-10
illustrates the interrupt timing in the RTC.

• Periodic interrupt
• Alarm

4.11.2.11. Interrupt Handling
The RTC has a single Interrupt Request line
which handles the following three interrupt
conditions:

Bit 7
of CRA
Bit 4
of CRC

P

• Update end interrupt.
The interrupts are generated if the respective
enable bits in the CRB Register are set prior to
an interrupt event occurrence. Reading the
CRC Register clears all interrupt flags. Thus,
when multiple interrupts are enabled, the interrupt service routine should first read and store

P/2

Bit 6
of CRC
B

• Periodic interrupt
• Alarm interrupt

A

244 µs

P/2

30.5 µs

C

Bit 5
of CRC

Flags (and IRQ) are reset at the conclusion of CRC
read or by reset.
A = Update In Progress bit high before
update occurs = 244 µs
B = Periodic interrupt to update
= Period (periodic int) / 2 + 244 µs
C = Update to Alarm Interrupt = 30.5 µs
P = Period is programmed by RS3-0 of CRA
Figure 4-10 Interrupt/Status Timing

4.11.2.12. Battery-Backed RAMs and Registers
The RTC has two battery-backed RAMs and
17 registers, used by the logical units themselves. Battery-backup power enables information retention during system power down.
The RAMs are:
• Standard RAM
• Extended RAM
Note: The ZFx86 contains no reverse polarity
protection.

ZFx86 Data Book 1.0 Rev D

The memory maps and register content of the
RAMs is illustrated in Table 4.136, Table
4.137, and Table 4.138.
The first 14 bytes and 3 programmable bytes
of the Standard RAM are overlaid by time,
alarm data and control registers. The rest 111
bytes are general-purpose memory.
Registers with reserved bits should be written
in “Read-Modify-Write” method.
All register locations within the device are
accessed by the RTC Index and Data registers (at base address and base address+1).

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4.11.3. RTC Configuration Registers

The Index register points to the register location being accessed, and the Data register
contains the data to be transferred to or from
the location. An additional 128 bytes of
battery-backed RAM (also called Extended
RAM) may be accessed via a second pair of
Index and Data registers.

Access the RTC configuration registers at any
time during normal operation mode; for
example, when VDD and VCC_IO are within
the recommended operation range. This
access is disabled during battery-backed
operation.

Access to the two RAMs may be locked. For
details see Table 4.105 on page 300.
Table 4.109 RTC Configuration Register Map
Location

Mnemonic

Device specific

RLR

Device specific

Name

Type

Reset

Reference

RAM Lock Register

R/W

HW

Table 4.110

DOMAO

Date of Month Alarm Register Offset

R/W

HW or SW

Table 4.111

Device specific

MONAO

Month Alarm Register Offset

R/W

HW or SW

Table 4.112

Device specific

CENO

Century Register Offset

R/W

HW or SW

Table 4.113

Table 4.110 RAM Lock Register (RLR)
Bit

7

Name

Block
Standard
RAM

Reset

0

6

5

4

3

Block
Block
Block
Block
Extended Extended Extended
RAM Write
RAM Write RAM Read
RAM
0

0

0

0

2

1

0

Reserved

0

R/W. The location is device specific. When a non-reserved bit is set to 1, it can be cleared only by hardware reset.
Bit
7

Description
Block Standard RAM
0=
1=

6

Block RAM Write
0=
1=

5

No effect on Standard RAM access (default)
Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads
return FHA
No effect on RAM access (default)
Writes to RAM (Standard and Extended) are ignored

Block Extended RAM Write
This bit controls writes to bytes 00h-1Fh of the Extended RAM.
0 = No effect on the Extended RAM access (default)
1 = Writes to bytes 00h-1Fh of the Extended RAM are ignored

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Bit
4

Description
Block Extended RAM Read
This bit controls read from bytes 00h-1Fh of the Extended RAM.
0 = No effect on Extended RAM access (default)
1 = Reads to bytes 00h-1Fh of the Extended RAM are ignored

3

2-0

Block Extended RAM
This bit controls access to the Extended RAM 128 bytes.
0 = No effect on Extended RAM access (default)
1 = Read and write to the Extended RAM are blocked: writes are ignored and reads return FFh
Reserved

Table 4.111 Date Of Month Alarm Register Offset (DOMAO)
Bit

7

Name

Reserved

Reset

0

6

5

4

3

2

1

0

0

0

1

0

Date of Month Alarm Register Offset Value
0

0

0

0

0

R/W. The location is device specific.
Bit
7
6-0

Description
Reserved
Date of Month Alarm Register Offset Value

Table 4.112 Month Alarm Register Offset (DOMAO)
Bit

7

6

5

4

3

2

Name

Reserved

Month Alarm Register Offset Value

Reset

0

0

R/W. The location is device specific.
Bit
7
6-0

Description
Reserved
Month Alarm Register Offset Value

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Table 4.113 Century Register Offset (CENO)
Bit

7

6

5

4

3

2

Name

Reserved

Century Register Offset Value

Reset

0

0

1

0

R/W. The location is device specific.
Bit
7
6-0

Description
Reserved
Century Register Offset Value

Table 4.114 RTC Configuration Register Bitmap
Register

Bits

Location

Mnemonic

7

6

5

4

3

Device
specific

RLR

RAM
Lock

RAM
Mask
Write

RAM
Block
Write

RAM
Block
Read

Upper
RAM
Block

Device
specific

DOMAO

Reserved

Date of Month Alarm Register Offset Value

Device
specific

MONAO

Reserved

Month Alarm Register Offset Value

Device
specific

CENO

Reserved

Century Register Offset Value

2

1

0

Reserved

4.11.4. RTC Registers
The RTC registers can be accessed at any
time during normal operation mode; that is
when VCC_IO is within the recommended
operation range. This access is disabled
during battery-backed operation. The write
operation to these registers is also disabled if
bit 7 of the CRD Register is 0 (see Table 4.131
on page 319).
Note: Before attempting to perform any startup procedures, make sure to read
about bit 7 (VRT) of the CRD Register.
This section describes the RTC Timing and
Control Registers that control basic RTC functionality.

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Table 4.115 RTC Register Map
Index

Mnemonic

00h

SEC

01h

SECA

02h

MIN

03h

Name

Type

Reset

Reference

Seconds Register

R/W

VPP PUR

Table 4.116

Seconds Alarm Register

R/W

VPP PUR

Table 4.117

Minutes Register

R/W

VPP PUR

Table 4.118

MINA

Minutes Alarm Register

R/W

VPP PUR

Table 4.119

04h

HOR

Hours Register

R/W

VPP PUR

Table 4.120

05h

HORA

Hours Alarm Register

R/W

VPP PUR

Table 4.121

06h

DOW

Day Of Week Register

R/W

VPP PUR

Table 4.122

07h

DOM

Date Of Month Register

R/W

VPP PUR

Table 4.123

08h

MON

Month Register

R/W

VPP PUR

Table 4.124

09h

YER

Year Register

R/W

VPP PUR

Table 4.125

0Ah

CRA

RTC Control Register A

R/W

Bit specific

Table 4.126

0Bh

CRB

RTC Control Register B

R/W

Bit specific

Table 4.129

0Ch

CRC

RTC Control Register C

R/O

Bit specific

Table 4.130

0Dh

CRD

RTC Control Register D

R/O

VPP PUR

Table 4.131

Programmablea

DOMA

Date of Month Alarm Register

R/W

VPP PUR

Table 4.132

Programmablea

MONA

Month Alarm Register

R/W

VPP PUR

Table 4.133

Programmablea

CEN

Century Register

R/W

VPP PUR

Table 4.134

a. Overlaid on RAM bytes in range 0Eh-7Fh.

Table 4.116 Seconds Register (SEC)) – Index 00H
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

Seconds Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Seconds Data
Values may be 00 to 59 in BCD format or 00 to 3B in Binary format.

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Table 4.117 Seconds Alarm Register (SECA)) – 01H
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

2

1

0

0

0

0

2

1

0

0

0

0

Seconds Alarm Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Seconds Alarm Data
Values may be 00 to 59 in BCD format or 00 to 3B in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.

Table 4.118 Minutes Register (MIN)) – 02H
Bit

7

6

5

Name
Reset

4

3

Minutes Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Minutes Data
Values may be 00 to 59 in BCD format or 00 to 3B in Binary format.

Table 4.119 Minutes Alarm Register (MINA) – 03H
Bit

7

6

5

Name
Reset

4

3

Minutes Alarm Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Minutes Alarm Data
Values may be 00 to 59 in BCD format or 00 to 3B in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.

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Table 4.120 Hours Register (HOR) – 04H
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

Hours Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Hours Data
For 12-hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and
81 to 8C (PM) in Binary format. For 24-hour mode, values may be 0- to 23 in BCD format or 00 to 17 in
Binary format.

Table 4.121 Hours Alarm Register (HORA) – 05H
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

Hours Alarm Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Hours Alarm Data
For 12-hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and
81 to 8C (PM) in Binary format. For 24-hour mode, values may be 0- to 23 in BCD format or 00 to 17 in
Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.

Table 4.122 Day Of Week Register (DOW) – 06H
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

Day Of Week Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Day Of Week Data. Values may be 01 to 07 in BCD format or 01 to 07 in Binary format.

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Table 4.123 Date Of Month Register (DOM) – 07H
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

2

1

0

0

0

0

2

1

0

Date Of Month Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Date Of Month Data
Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.

Table 4.124 Month Register (MON) - 08H
Bit

7

6

5

Name
Reset

4

3

Month Data
0

0

0

0

0

R/W.
Bit
7-0

Description
Month Data
Values may be 01 to 12 in BCD format or 01 to 0C in Binary format.

Table 4.125 Year Register (YER) - 09H
Bit

7

6

5

4

3

Name

Year Data

Reset

0

R/W.
Bit
7-0

Description
Year Data
Values may be 00 to 99 in BCD format or 00 to 63 in Binary format.

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Table 4.126 RTC Control Register A (CRA) – 0AH
Bit

7

6

Name

Update in
Progress

Reset

0

5

4

3

Divider Chain Control 2-0
0

1

2

1

0

Periodic Interrupt Rate Select 3-0

0

0

0

0

0

R/W. This register controls test selection, among other functions. This register cannot be written before reading bit 7
of the CRD Register.
Bit
7

Description
Update in Progress
This RO bit is not affected by reset. This bit reads 0 when bit 7 of the CRB Register is 1.
0 =: Timing registers not updated within 244 ms
1 = Timing registers updated within 244 ms

6-4

Divider Chain Control
These R/W bits control the configuration of the divider chain for timing generation and register bank
selection. See Table 4.127. They are cleared to 000 as long as bit 7 of the CRD Register is reads 0.

3-0

Periodic Interrupt Rate Select
These R/W bits select one of fifteen output taps from the clock divider chain to control the rate of the
periodic interrupt. See Table 4.128 and Figure 4-9. They are cleared to 000 as long as bit 7 of the CRD
Register is reads 0.

Table 4.127 Divider Chain Control and Test Selection
DV2

DV1

DV0

CRA 6

CRA 5

CRA 4

0

0

X

Oscillator Disabled

0

1

0

Normal Operation

0

1

1

Test

1

0

X

1

1

X

Configuration

ZFx86 Data Book 1.0 Rev D

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Table 4.128 Periodic Interrupt Rate Encoding
Rate Select
3210

Periodic Interrupt Rate (ms)

0000

No interrupts

0001

3.906250

7

0010

7.812500

8

0011

0.122070

2

0100

0.244141

3

0101

0.488281

4

0110

0.976562

5

0111

1.953125

6

1000

3.906250

7

1001

7.812500

8

1010

15.625000

9

1011

31.250000

10

1100

62.500000

11

1101

125.000000

12

1110

250.000000

13

1111

500.000000

14

ZFx86 Data Book 1.0 Rev D

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Table 4.129 RTC Control Register B (CRB) - 0BH
Bit

7

6

5

4

3

Name

Set Mode

Periodic
Interrupt
Enable

Alarm
Interrupt
Enable

Update Ended
Interrupt
Enable

Reserved

Reset

0

0

0

0

0

2
Data
Mode

0

1
Hour
Mode

0

0
Daylight
Saving

0

R/W.
Bit
7

Description
Set Mode.This bit is reset at VPP power-up reset only.
0=
1=

6

Timing updates occur normally
User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update
occurs

Periodic Interrupt Enable
Bits 3-0 of the CRA Register page 314 determine the rate at which this interrupt is generated. It is cleared
to 0 on RTC reset (that is, hardware or software reset) or when RTC is disabled.
0 = Disabled
1 = Enabled

5

Alarm Interrupt Enable
This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and
month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD Register
is reads 0.
0 = Disabled
1 = Enabled

4

Update Ended Interrupt Enable
This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (for example, hardware
or software reset) or when the RTC is disable.
0 = Disabled
1 = Enabled

3

Reserved
Bit always reads 0.

2

Data Mode
This bit is reset at VPP power-up reset only.
0 = BCD format enabled
1 = Binary format enabled

1

Hour Mode
This bit is reset at VPP power-up reset only.
0 = 12-hour format enabled
1 = 24-hour format enabled

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Bit
0

Description
Daylight Saving
This bit is reset at VPP power-up reset only.
0=
1=

Disabled
Enabled
In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.
In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.

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Table 4.130 RTC Control Register C (CRC) - 0CH
Bit

7

6

5

4

Name

IRQ Flag

Periodic
Interrupt
Flag

Alarm
Interrupt
Flag

Update
Ended
Interrupt
Flag

Reset

0

0

0

0

3

2

1

0

0

0

Reserved

0

0

R/O.
Bit
7

Description
IRQ Flag
This RO bit mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear
this bit (and deactivate the interrupt pin), read the CRC Register as the flag bits UF, AF and PF are cleared
after reading this register.
0 = IRQ inactive
1 = Logic equation is true: (UIE and UF) or (AIE and AF) or (PIE and PF).

6

Periodic Interrupt Flag
This RO bit is cleared to 0 on RTC reset (that is, hardware or software reset) or the RTC disabled. In
addition, this bit is cleared to 0 when this register is read.
0 = No transition occurred on the selected tap since the last read
1 = Transition occurred on the selected tap of the divider chain

5

Alarm Interrupt Flag
This RO bit is cleared to 0 as long as bit 7 of the CRD Register is reads 0. In addition, this bit is cleared
to 0 when this register is read.
0 = No alarm detected since the last read
1 = Alarm condition detected

4

Update Ended Interrupt Flag
This RO bit is cleared to 0 on RTC reset (for example, hardware or software reset) or the RTC disabled.
In addition, this bit is cleared to 0 when this register is read.
0 = No update occurred since the last read
1 = Time registers updated

3-0

Reserved

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Table 4.131 RTC Control Register D (CRD) - 0DH
Bit

7

6

5

4

3

Name

Valid RAM
and Time

Reserved

Reset

0

0

2

1

0

R/O.
Bit

Description

7

Valid RAM and Time. This bit senses the voltage that feeds the RTC (VCC_IO or ) and indicates whether
or not it was too low since the last time this bit was read. If it was too low, the RTC contents (time/calendar
registers and CMOS RAM) is not valid.
0 = The voltage that feeds the RTC was too low.
1 = RTC contents (time/calendar registers and CMOS RAM) valid

6-0

Reserved

Table 4.132 Date of Month Alarm Register (DOMA)
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

Date of Month Alarm Data
1

1

0

0

0

R/W.Location is a Programmable Index
Bit
7-0

Description
Date of Month Alarm Data
Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected (default).

Table 4.133 Month Alarm Register (MONA)
Bit

7

6

5

Name
Reset

4

3

2

1

0

0

0

0

Month Alarm Data
1

1

0

0

0

R/W.Location is a Programmable Index
Bit
7-0

Description
Month Alarm Data
Values may be 01 to 12 in BCD format or 01 to 0C in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected (default).

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Table 4.134 Century Register (CEN)
Bit

7

6

5

4

3

Name

Century Data

Reset

0

2

1

0

R/W.Location is a Programmable Index
Bit
7-0

Description
Century Data
Values may be 00 to 99 in BCD format or 00 to 63 in Binary format.

Table 4.135 BCD and Binary Formats
Parameter

BCD Format

Binary Format

Seconds

00 to 59

00 to 3B

Minutes

00 to 59

00 to 3B

12-hour mode: 01 to 12 (AM)
81 to 92 (PM)
24-hour mode: 00 to 23

12-hour mode: 01 to 0C (AM)
81 to 8C (PM)
24-hour mode: 00 to 17

Day

01 to 07 (Sunday = 01)

01 to 07

Date

01 to 31

01 to 1F

01 to 12 (January = 01)

01 to 0C

Year

00 to 99

00 to 63

Century

00 to 99

00 to 63

Hours

Month

4.11.4.1. Usage Hints
1. Read bit 7 of the CRD Register at each system power-up to validate the contents of the
RTC registers and the CMOS RAM. When
this bit is 0, the contents of these registers
and the CMOS RAM are questionable. This
bit is reset when the backup battery voltage
is too low. The voltage level at which this bit
is reset is below the minimum recommended battery voltage, 2.4 V. Although the RTC
oscillator may function properly and the register contents may be correct at lower than
2.4 V, this bit is reset since correct functionality cannot be guaranteed. System BIOS
may use a checksum method to revalidate
the contents of the CMOS-RAM. The checksum byte should be stored in the same
CMOS RAM.

ZFx86 Data Book 1.0 Rev D

2. Change the backup battery while normal
operating power is present, and not in
backup mode, to maintain valid time and
register information. If a low leakage
capacitor is connected to VBAT, the battery
may be changed in backup mode.
3. A rechargeable NiCd battery may be used
instead of a non-rechargeable Lithium
battery. This is a preferred solution for
portable systems, where small size
components is essential.
4. A supercap capacitor may be used instead
of the normal Lithium battery. In a portable
system usually the VCC_IO voltage is
always present since the power
management stops the system before its
voltage falls to low. The supercap capacitor

Page 320

4
in the range of 0.047-0.47 F should supply

the power during the battery replacement.

Table 4.136 RTC Register Bitmap
Register

Bits

Index

Mnemonic

00h

SEC

Seconds Data

01h

SECA

Seconds Alarm Data

02h

MIN

Minutes Data

02h

MINA

Minutes Alarm Data

04h

HOR

Hours Data

05h

HORA

Hours Alarm Data

06h

DOW

Day of Week Data

07h

DOM

Date of Month Data

08h

MON

Month Data

09h

YER

Year Data

0Ah

CRA

Update in
Progress

0Bh

CRB

Set Mode

Periodic
Interrupt

Alarm
Interrupt

Update Ended
Interrupt

0Ch

CRC

IRQ Flag

Periodic
Interrupt
Flag

Alarm
Interrupt
Flag

Update Ended
Interrupt Flag

0Dh

CRD

Valid
RAM and
Time

Prog.

DOMA

Date of Month Alarm Data

Prog.

MONA

Month Alarm Data

Prog.

CEN

Century Data

7

6

5

4

3

Divider Chain Control 2-0

2

1

0

Periodic Interrupt Rate Select 3-0
Reserved

Data
Mode

Hour
Mode

Daylight
Saving

Reserved

Reserved

4.11.5. RTC General-purpose RAM Map
Table 4.137 Standard RAM Map
Index
0Eh - 7Fha

Description
Battery-backed General-purpose 111-byte RAM

a. Battery-backed 111-byte RAM (114 - 3 overlaid registers).

Table 4.138 Extended RAM Map
Index
00h - 7Fh

ZFx86 Data Book 1.0 Rev D

Description
Battery-backed General-purpose 128-byte RAM.

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4
4.12. ACCESS.bus Interface (ACB)
The ACB is a two-wire synchronous serial
interface compatible with the ACCESS.bus
physical layer. The ACB is also compatible
with Intel's SMBus and Philips’ I2C. Configure
the ACB as a bus master or slave, and maintain bi-directional communication with both
multiple master and slave devices. As a slave
device, the ACB may issue a request to
become the bus master.
The ACB allows easy interfacing to a wide
range of low-cost memories and I/O devices,
including: EEPROMs, SRAMs, timers, ADC,
DAC, clock chips and peripheral drivers.
This text describes the general ACB functional
block. A device may include a different implementation. For device specific implementation,
see Section 4.5.4. ‘Device Architecture and
Configuration’ on page 261.

4.12.1. Functional Description
The ACCESS.bus protocol uses a two-wire
interface for bi-directional communication
between the ICs connected to the bus. The
two interface lines are the Serial Data Line
(SDL) and the Serial Clock Line (SCL). These
lines should be connected to a positive supply
via an internal or external pull-up resistor, and
remain high even when the bus is idle.
Each IC has a unique address and can
operate as a transmitter or a receiver (though
some peripherals are only receivers).
During data transactions, the master device
initiates the transaction, generates the clock
signal and terminates the transaction. For
example, when the ACB initiates a data transaction with an attached ACCESS.bus
compliant peripheral, the ACB becomes the
master. When the peripheral responds and
transmits data to the ACB, their master/slave
(data transaction initiator and clock generator)
relationship is unchanged, even though their
transmitter/receiver functions are reversed.

ZFx86 Data Book 1.0 Rev D

4.12.1.1. Data Transactions
One data bit is transferred during each clock
pulse. Data is sampled during the high state of
the serial clock (SCL). Consequently,
throughout the clock’s high period, the data
should remain stable (see Figure 4-11). Any
changes on the SDA line during the high state
of the SCL and in the middle of a transaction
aborts the current transaction. New data
should be sent during the low SCL state. This
protocol permits a single data line to transfer
both command/control information and data,
using the synchronous serial clock.
Each data transaction is composed of a Start
Condition, a number of byte transfers (set by
the software) and a Stop Condition to terminate the transaction. Each byte is transferred
with the most significant bit first, and after
each byte (8 bits), an Acknowledge signal
must follow. The following sections provide
further details of this process.
During each clock cycle, the slave can stall the
master while it handles the previous data or
prepares new data. This can be done for each
bit transferred, or on a byte boundary, by the
slave holding SCL low to extend the clock-low
period. Typically, slaves extend the first clock
cycle of a transfer if a byte read has not yet
been stored, or if the next byte to be transmitted is not yet ready. Some microcontrollers,
with limited hardware support for
ACCESS.bus, extend the access after each
bit, thus allowing the software to handle this
bit.

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4
In addition to the first Start Condition, a
repeated Start Condition can be generated in
the middle of a transaction. This allows
another device to be accessed, or a change in
the direction of data transfer.

.

SDA
SCL
Data Line
Stable:
Data Valid

Change
of Data
Allowed

SDA

Figure 4-11 Bit Transfer
SCL

S

4.12.1.2. Start and Stop Conditions
The ACCESS.bus master generates Start and
Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered
busy and retains this status for a certain time
after a Stop Condition is generated. A high to
low transition of the data line (SDA) while the
clock (SCL) is high indicates a Start Condition.
A low to high transition of the SDA line while
the SCL is high indicates a Stop Condition
(Figure 4-12).

P

Start
Condition

Stop
Condition

Figure 4-12 Start and Stop Conditions

4.12.1.3. Acknowledge (ACK) Cycle
The ACK cycle consists of two signals: the
ACK clock pulse sent by the master with each
byte transferred, and the ACK signal sent by
the receiving device (see Figure 4-13).

Acknowledge
Signal From Receiver
SDA
MSB
SCL

1

S

2 3-6

7

8

9
ACK

1

2

3-8

9
ACK

Start
Condition

P
Stop
Condition

Byte Complete
Interrupt Within
Receiver

Clock Line Held
Low by Receiver
While Interrupt
is Serviced

Figure 4-13 ACCESS.bus Data Transaction

ZFx86 Data Book 1.0 Rev D

Page 323

4
The master generates the ACK clock pulse on
the ninth clock pulse of the byte transfer. The
transmitter releases the SDA line (permits it to
go high) to allow the receiver to send the ACK
signal. The receiver must pull down the SDA

line during the ACK clock pulse, signalling that
it has correctly received the last data byte and
is ready to receive the next byte. Figure 4-14
illustrates the ACK cycle.

Data Output
by Transmitter

Transmitter Stays Off Bus
During Acknowledge Clock

Data Output
by Receiver

Acknowledge
Signal From Receiver

SCL
S

1

2 3-6

7

8

9

Start
Condition

Figure 4-14 ACCESS.bus Acknowledge Cycle

4.12.1.4. Acknowledge after Every Byte
Rule
According to this rule, the master generates
an acknowledge clock pulse after each byte
transfer, and the receiver sends an acknowledge signal after every byte received. There
are two exceptions to this rule:
1. When the master is the receiver, it must indicate to the transmitter the end of data by
not acknowledging (negative acknowledge)
the last byte clocked out of the slave. This
negative acknowledge still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled
down.
2. When the receiver is full, otherwise
occupied, or a problem has occurred, it
sends a negative acknowledge to indicate
that it cannot accept additional data bytes.

4.12.1.5. Addressing Transfer Formats
Each device on the bus has a unique address.
Before any data is transmitted, the master
transmits the address of the slave being
addressed. The slave device should send an
acknowledge signal on the SDA line, once it
recognizes its address.

ZFx86 Data Book 1.0 Rev D

The address consists of the first 7 bits after a
Start Condition. The direction of the data
transfer (R/W) depends on the bit sent after
the address, the eighth bit. A low to high transition during a SCL high period indicates the
Stop Condition, and ends the transaction of
SDA (see Figure 4-15).
When the address is sent, each device in the
system compares this address with its own. If
there is a match, the device considers itself
addressed and sends an acknowledge signal.
Depending on the state of the R/W bit (1=read,
0=write), the device acts either as a transmitter or a receiver.
The I2C bus protocol allows a general call
address to be sent to all slaves connected to
the bus. The first byte sent specifies the
general call address (00h) and the second
byte specifies the meaning of the general call
(for example, write slave address by software
only). Those slaves that require data acknowledge the call, and become slave receivers;
other slaves ignore the call.

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SDA

SCL

S

Start
Condition

1-7

8

9

Address R/W ACK

1-7
Data

8

9

1-7

ACK

Data

8

9
ACK

P
Stop
Condition

Figure 4-15 A Complete ACCESS.bus Data Transaction

4.12.1.6. Arbitration on the Bus
Multiple master devices on the bus require
arbitration between their conflicting bus
access demands. Bus control is initially determined according to address bits and clock
cycle. If the masters are trying to address the
same slave, data comparisons determine the
outcome of this arbitration. In master mode,
the device immediately aborts a transaction if
the value sampled on the SDA line differs from
the value driven by the device. (An exception
to this rule is SDA while receiving data. The
lines may be driven low by the slave without
causing an abort.)
The SCL signal is monitored for clock synchronization and to allow the slave to stall the bus.
The actual clock period is set by the master
with the longest clock period, or by the slave
stall period. The clock high period is determined by the master with the shortest clock
high period.
When an abort occurs during the address
transmission, a master that identifies the
conflict should give up the bus, switch to slave
mode and continue to sample SDA to check if
it is being addressed by the winning master on
the bus.

ZFx86 Data Book 1.0 Rev D

4.12.1.7. Master Mode
Requesting Bus Mastership
An ACCESS.bus transaction starts with a
master device requesting bus mastership. It
asserts a Start Condition, followed by the
address of the device it wants to access. If this
transaction is successfully completed, the software may assume that the device has become
the bus master.
For the device to become the bus master, the
software should perform the following steps:
1. Configure the INTEN bit of the ACBCTL1
Register to the desired operation mode
(Polling or Interrupt) and set the START bit
of this register. This causes the ACB to issue a Start Condition on the ACCESS.bus
when the ACCESS.bus becomes free (BB
bit of the ACBCST Register is cleared, or
other conditions that can delay start). It then
stalls the bus by holding SCL low.
2. If a bus conflict is detected (that is, another
device pulls down the SCL signal), the BER
bit of the ACBST Register set.
3. If there is no bus conflict, the MASTER bit of
the ACBST Register and the SCAST of the
ACBST Register sets.
4. If the INTEN bit of the ACBCTL1 Register is
set and either the BER or SDAST bit of the
ACBST Register sets, then an interrupt is
issued.

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Sending the Address Byte
When the device is the active master of the
ACCESS.bus (the MASTER bit of the ACBST
Register sets), it can send the address on the
bus.
The address sent should not be the device’s
own address, as defined by the ADDR bit of
the ACBADDR Register if the SAEN bit of this
register is set, nor should it be the global call
address if the GCMTCH bit of the ACBCST
Register is set.
To send the address byte, use the following
sequence:
1. For a receive transaction where the software wants only one byte of data, it should
set the ACB bit of the ACBCTL1 Register. If
only an address needs to be sent or if the
device requires stall for some other reason,
set the STASTRE bit of the ACBCTL1 Register.
2. Write the address byte (7-bit target device
address) and the direction bit to the
ACBSDA Register. This causes the ACB to
generate a transaction. At the end of this
transaction, the acknowledge bit received is
copied to the NEGACK bit of the ACBST
Register. During the transaction, the SDA
and SCL lines are continuously checked for
conflict with other devices. If a conflict is
detected, the transaction is aborted, the
BER bit of the ACBST Register is set and
the MASTER bit of this register is cleared.
3. If the STASTRE bit of the ACBCTL1
Register is set and the transaction was
successfully completed (that is, both the
BER and NEGACK bits of the ACBST
Register are cleared), the STASTR bit is set.
In this case, the ACB stalls any further
ACCESS.bus operations (that is, holds SCL
low). If the INTEN bit of the ACBCTL1
Register is set, it also sends an interrupt
request to the host.
4. If the requested direction is transmit and the
start transaction was completed
successfully (that is, neither the NEGACK
nor the BER bit of the ACBST Register is
set, and no other master has accessed the

ZFx86 Data Book 1.0 Rev D

device), the SDAST bit of the ACBST
Register is set to indicate that the ACB
awaits attention.
5. If the requested direction is receive, the
start transaction was completed
successfully and the STASTRE bit of the
ACBCTL1 Register is cleared, the ACB
starts receiving the first byte automatically.
6. Check that both the BER and NEGACK bits
of the ACBST Register are cleared. If the
INTEN bit of the ACBCTL1 Register is set,
an interrupt is generated when either the
BER or NEGACK bit of the ACBST Register
is set.

Master Transmit
After becoming the bus master, the device can
start transmitting data on the ACCESS.bus.
To transmit a byte in an interrupt or polling
controlled operation, the software should do
the following:
1. Check that both the BER and NEGACK bits
of the ACBST Register clears, and that the
SDAST bit of the ACBST Register sets. If
the STASTRE bit of the ACBCTL1 Register
sets, also check that the STASTR bit of the
ACBST Register clears (and clear it if required).
2. Write the data byte to be transmitted to the
ACBSDA Register.
When either the NEGACK or BER bit of the
ACBST Register sets, an interrupt is generated. When the slave responds with a negative acknowledge, the NEGACK bit of the
ACBST Register sets and the SDAST bit of
the ACBST Register remains cleared. In this
case, if the INTEN bit of the ACBCTL1
Register sets, an interrupt issues.
Master Receive
After becoming the bus master, the device
starts receiving data on the ACCESS.bus.
To receive a byte in an interrupt or polling
operation, the software should:
1. Check that the SDAST bit of the ACBST

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Register is set and that the BER bit is
cleared. If the STASTRE bit of the
ACBCTL1 Register is set, also check that
the STASTRE bit of the ACBST Register is
cleared (and clear it if required).
2. Set the ACK bit of the ACBCTL1 Register to
1, if the next byte is the last byte that should
be read. This causes a negative
acknowledge to be sent.
3. Read the data byte from the ACBSDA
Register.
Before receiving the last byte of data, set the
ACK bit of the ACBCTL1 Register.
Master Stop
To end a transaction, set the STOP bit of the
ACBCTL1 Register before clearing the current
stall flag (that is, the SDAST, NEGACK or
STASTR bit of the ACBST Register). This
causes the ACB to send a Stop Condition
immediately, and to clear the STOP bit of the
ACBCTL1 Register. A Stop Condition may be
issued only when the device is the active bus
master (the MASTER bit of the ACBST
Register is set).
Master Bus Stall
The ACB can stall the ACCESS.bus between
transfers while waiting for the host response.
The ACCESS.bus is stalled by holding the
SCL signal low after the acknowledge cycle.
Note that this is interpreted as the beginning of
the following bus operation. The user must
make sure that the next operation is prepared
before the flag that causes the bus stall is
cleared.
The flags that can cause a bus stall in master
mode are:
• Negative acknowledge after sending a
byte
(ACBST.NEGACK=1).
• ACBST.SDAST bit is set.
• ACBCTL1.STASTRE=1, after a successful
start (ACBST.STASTR=1).

ZFx86 Data Book 1.0 Rev D

Repeated Start
A repeated start is performed when the device
is already the bus master (ACBST.MASTER is
set). In this case, the ACCESS.bus is stalled
and the ACB awaits host handling due to:
negative acknowledge (ACBST.NEGACK=1),
empty buffer (ACBST.SDAST=1) and/or a stall
after start (ACBST.STASTR=1).
For a repeated start:
1. Set (1) ACBCTL1.START.
2. In master receive mode, read the last data
item from ACBSDA.
3. Follow the address send sequence, as
described in ‘Sending the Address Byte’ on
326.
4. If the ACB was awaiting handling due to
ACBST.STASTR=1, clear it only after
writing the requested address and direction
to ACBSDA.
Master Error Detection
The ACB detects illegal Start or Stop Conditions (that is, a Start or Stop Condition within
the data transfer, or the acknowledge cycle)
and a conflict on the data lines of the
ACCESS.bus. If an illegal condition is
detected, BER is set, and master mode is
exited (ACBST.MASTER is cleared).
Bus Idle Error Recovery
When a request to become the active bus
master or a restart operation fails, the
ACBST.BER bit is set to indicate the error. In
some cases, both the device and the other
device may identify the failure and leave the
bus idle. In this case, the start sequence may
be incomplete and the ACCESS.bus may
remain deadlocked.
To recover from deadlock, use the following
sequence:
1. Clear ACBST.BER bit and the ACBCST.BB
bit.
2. Wait for a time-out period to check that there

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is no other active master on the bus (that is,
ACBCST.BB remains cleared).
3. Disable, and re-enable the ACB to put it in
the non-addressed slave mode. This
completely resets the functional block.
At this point, some of the slaves may not identify the bus error. To recover, the ACB
becomes the bus master: it asserts a Start
Condition, sends an address byte, then
asserts a Stop Condition which synchronizes
all the slaves.
4.12.1.8. Slave Mode
A slave device waits in idle mode for a master
to initiate a bus transaction. Whenever the
ACB is enabled and it is not acting as a master
(that is, ACBST.MASTER is cleared), it acts as
a slave device.
Once a Start Condition on the bus is detected,
the device checks whether the address sent
by the current master matches either:
• The ACBADDR.ADDR value if
ACBADDR.SAEN=1, or
• The general call address if
ACBCTL1.GCMEN=1.
This match is checked even when
ACBST.MASTER is set. If a bus conflict (on
SDA or SCL) is detected, ACBST.BER is set,
ACBST.MASTER is cleared and the device
continues to search the received message for
a match.

4. The software then reads the ACBST.XMIT
bit to identify the direction requested by the
master device. It clears the
ACBST.NMATCH bit so future byte
transfers are identified as data bytes.
Slave Receive and Transmit
Perform slave receive and transmit after a
match is detected and the data transfer direction is identified. After a byte transfer, the ACB
extends the acknowledge clock until the software reads or writes the ACBSDA Register.
The receive and transmit sequences are identical to those used in the master routine.
Slave Bus Stall
When operating as a slave, the device stalls
the ACCESS.bus by extending the first clock
cycle of a transaction in the following cases:
• ACBST.SDAST is set.
• ACBST.NMATCH and ACBCTL1.NMINTE
are set.
Slave Error Detection
The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (that is, a Start or
Stop Condition within the data transfer or the
acknowledge cycle). When this occurs, the
BER bit is set and MATCH and GMATCH are
cleared, setting the ACB as an unaddressed
slave.

If an address match or a global match is
detected:

4.12.1.9. Configuration

1. The device asserts its SDA pin during the
acknowledge cycle
2. The ACBCST.MATCH and
ACBST.NMATCH bits are set. If
ACBST.XMIT=1 (that is, slave transmit
mode) ACBST.SDAST is set to indicate that
the buffer is empty.
3. If ACBCTL1.INTEN is set, an interrupt is
generated if both the ACBCTL1.INTEN and
ACBCTL1.NMINTE bits are set.

The SDA and SCL are open-drain signals.
The device permits the user to define whether
to enable or disable the internal pull-up of
each of these signals.

ZFx86 Data Book 1.0 Rev D

SDA and SCL Signals

ACB Clock Frequency
The ACB permits the user to set the clock
frequency for the ACCESS.bus clock. The
clock is set by the ACBCTL2.SCLFRQ field,
which determines the SCL clock period used

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by the device. This clock low period may be
extended by stall periods initiated by the ACB
or by another ACCESS.bus device. In case of
a conflict with another bus master, a shorter
clock high period may be forced by the other
bus master until the conflict is resolved.

4.12.2. ACB Registers
The register maps in this chapter use abbreviations for Type. See Table 4.55 "Register Type
Abbreviations" on page 269

Table 4.139 ACB Register Map
Offset Mnemonic

Register Name

Type

Reference

R/W

Table 4.140

00h

ACBSDA

ACB Serial Data

01h

ACBST

ACB Status

Varies per bit

Table 4.141

02h

ACBCST

ACB Control Status

Varies per bit

Table 4.142

03h

ACBCTL1 ACB Control 1

R/W

Table 4.143

04h

ACBADDR ACB Own Address

R/W

Table 4.144

05h

ACBCTL2 ACB Control 2

R/W

Table 4.145

Table 4.140 ACB Serial Data Register (ACBSDA) - 00H
Bit

7

Name

6

5

4

3

2

1

0

ACB Serial Data

Reset
R/W: This shift register is used to transmit and receive data. The most significant bit is transmitted (received) first, and the
least significant bit is transmitted last. Reading or writing to the ACBSDA Register is allowed only when the SDAST bit of
the ACBST Register is set, or for repeated starts after setting the START bit. An attempt to access the register in other
cases may produce unpredictable results.

ZFx86 Data Book 1.0 Rev D

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Table 4.141 ACB Status Register (ACBST) - 01H
Bit

7

6

5

4

3

2

1

0

Name

SLVSTP

SDAST

BER

NEGACK

STASTR

NMATCH

MASTER

XMIT

Reset

0

0

0

0

0

0

0

0

Type (R/W, etc.) varies per bit. This is a read register with a special clear. Some of its bits may be cleared by software, as described in the table below. This register maintains the current ACB status. On reset, and when the ACB is
disabled, ACBST is cleared (00h).
Bit

Type

7

R/W1C

Description
Slave Stop – SLVSTP
Writing 0 to SLVSTP is ignored.
0 = Writing 1 or ACB disabled
1 = Stop Condition detected after a slave transfer in which MATCH or GCMATCH was set

6

RO

SDA Status – SDAST
0=

1=
5

R/W1C

Reading from the ACBSDA Register during a receive, or when writing to it during a
transmit. When ACBCTL1.START is set, reading the ACBSDA Register does not clear
SDAST. This enables ACB to send a repeated start in master receive mode.
SDA Data Register awaiting data (transmit - master or slave) or holds data that should be
read (receive - master or slave).

Bus Error – BER
Writing 0 to BER is ignored.
0 = Writing 1 or ACB disabled
1 = Start or Stop Condition detected during data transfer (that is, Start or Stop Condition during
the transfer of bits 2 through 8 and acknowledge cycle), or when an arbitration problem
detected.

4

R/W1C

Negative Acknowledge – NEGACK
Writing 0 to NEGACK is ignored.
0 = Writing 1 or ACB disabled
1 = Transmission not acknowledged on the ninth clock (In this case, SDAST is not set)

3

R/W1C

Stall After Start – STASTR
Writing 0 to STASTR is ignored.
0 = Writing 1 or ACB disabled
1 = Address sent successfully (that is, a Start Condition sent without a bus error, or Negative
Acknowledge), if ACBCTL1.STASTRE is set. This bit is ignored in slave mode. When
STASTR is set, it stalls the ACCESS.bus by pulling down the SCL line, and suspends any
further action on the bus (e.g., receive of first byte in master receive mode). In addition, if
ACBCTL1.INTEN is set, it also causes the ACB to send an interrupt.

2

R/W1C

New Match – NMATCH
Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent when this bit is
set.
0 = Software writes 1 to this bit
1 = Address byte follows a Start Condition or a repeated start, causing a match or a global-call
match.

ZFx86 Data Book 1.0 Rev D

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4
Bit

Type

1

RO

Description
Master
0=
1=

0

Arbitration loss (BER is set) or recognition of a Stop Condition
Bus master request succeeded and master mode active

Transmit – XMIT

RO

Direction bit.
0 = Master/slave transmit mode not active
1 = Master/slave transmit mode active

Table 4.142 ACB Control Status Register (ACBCST) - 02H
Bit

7

Name

6
Reserved

Reset

0

5

4

3

2

1

0

TGSCL

TSDA

GCMTCH

MATCH

BB

BUSY

0

X

0

0

0

0

0

This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB functions. On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared.
Bit

Type

7-6

Reserved

5

Toggle SCL Line – TGSCL
R/W

4

Enables toggling the SCL line during error recovery.
0 = Clock toggle completed
1 = When the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to
TGSCL while SDA is high is ignored.
Test SDA Line – TSDA

RO

This bit reads the current value of the SDA line. It can be used while recovering from an error
condition in which the SDA line is constantly pulled low by an out-of-sync slave. Data written to this
bit is ignored.
Global Call Match – GCMTCH

3
RO

0=
1=

Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition)
In slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a
Start Condition) is 00h.

Address Match – MATCH

2
RO

1

Description

0=
1=

Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition)
ACBADDR.SAEN is set and the first 7 bits of the address byte (the first byte transferred after a
Start Condition) match the 7-bit address in the ACBADDR Register.

Bus Busy – BB
R/W1C 0 = Writing 1, ACB disabled, or Stop Condition detected
1 = Bus active (a low level on either SDA or SCL), or Start Condition

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Bit

Type

0

Description
Busy

RO

This bit should always be written 0. This bit indicates the period between detecting a Start Condition
and completing receipt of the address byte. After this, the ACB is either free or enters slave mode.
0 = Completion of any state below or ACB disabled
1 = ACB is in one of the following states:
Generating a Start Condition
Master mode (ACBST.MASTER is set)
Slave mode (ACBCST.MATCH or ACBCST.GCMTCH set).

Table 4.143 ACB Control Register 1 (ACBCTL1) - 03H
Bit

7

6

5

4

3

2

1

0

Name

STASTRE

NMINTE

GCMEN

ACK

Reserved

INTEN

STOP

START

Reset

0

0

0

0

0

0

0

0

R/W
Bit
7

Description
Stall After Start Enable – STASTRE
0=
1=

6

New Match Interrupt Enable – NMINTE
0: =
1=

5

No interrupt issued on a new match
Interrupt issued on a new match only if ACBCTL1.INTEN set

Global Call Match Enable – GCMEN
0=
1=

4

When cleared, ACBST.STASTR can not be set. However, if ACBST.STASTR is set, clearing STASTRE
will not clear ACBST.STASTR.
Stall after start mechanism enabled, and ACB stalls the bus after the address byte

ACB not responding to global call
Global call match enabled

Receive Acknowledge
This
stop
0=
1=

bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit holds the
transmitting instruction that is transmitted during the next acknowledge cycle.
Cleared after acknowledge cycle
Negative acknowledge issued on next received byte

3

Reserved

2

Interrupt Enable
0=
1=

ACB interrupt disabled
ACB interrupt enabled. An interrupt is generated in response to one of the following events:
—
—
—
—
—
—

Detection of an address match (ACBST.NMATCH=1) and NMINTE=1
Receipt of Bus Error (ACBST.BER=1)
Receipt of Negative Acknowledge after sending a byte (ACBST.NEGACK=1)
Acknowledge of each transaction (same as the hardware set of the ACBST.SDAST bit)
In master mode if ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1)
Detection of a Stop Condition while in slave mode (ACBST.SLVSTP=1).

ZFx86 Data Book 1.0 Rev D

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4
Bit
1

Description
Stop
0=
1=

0

Automatically cleared after STOP issued
Setting this bit in master mode generates a Stop Condition to complete or abort current message
transfer

Start
Set this bit only when in master mode or when requesting master mode.
0 = Cleared after Start Condition sent or Bus Error (ACBST.BER=1) detected
1 = Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master
of the bus (ACBST.MASTER=0), setting START generates a Start Condition when the ACCESS.bus
becomes free (ACBCST.BB=0). An address transmission sequence should then be performed.
If the device is the active master of the bus (ACBST.MASTER=1), setting START and then writing to the ACBSDA Register generates a Start Condition. If a transmission is already in progress, a repeated Start Condition
is generated. Use this condition to switch the direction of the data flow between the master and the slave, or
to choose another slave device without separating them with a Stop Condition.

Table 4.144 ACB Own Address Register (ACBADDR) - 04H
Bit

7

Name

6

SAEN

5

4

3

2

1

0

ADDR

Reset
R/W: This is a byte-wide register that holds the ACB ACCESS.bus address. The reset value of this register is undefined.
Bit
7

Description
Slave Address Enable – SAEN
0=
1=

6-0

ACB does not check for an address match with ADDR field
ADDR field holds a valid address and enables the match of ADDR to an incoming address byte

Own Address
These bits hold the 7-bit device address. When in slave mode, the first 7 bits received after a Start Condition
are compared with this field (first bit received is compared with bit 6, and the last bit with bit 0). If the address
field matches the received data and ACBADDR.SAEN is 1, a match is declared.

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4
Table 4.145 ACB Control Register 2 (ACBCTL2) - 05H
Bit

7

6

5

4

3

2

1

0

Name

SCLFRQ

ENABLE

Reset

0

0

R/W: This register enables/disables the functional block and determines the ACB clock rate.
Bit

Description

7-1

SCL Frequency – SCLFRQ
This field defines the SCL period (low and high time) when the device serves as a bus master. The clock
low and high times are defined as follows:
tSCLl = tSCLh = 2*SCLFRQ*tCLK where tCLK is the module input clock cycle,.
Program SCLFRQ to values in the range of 00010002 (810) through 11111112 (12710). Using any other value
has unpredictable results.

0

Enable
0=
1=

ACB disabled, ACBCTL1, ACBST and ACBCST cleared, and clocks halted
ACB enabled

Table 4.146 ACB Register Bitmap
Register

Bits

Offset

Mnemonic

7

6

00h

ACBSDA

01h

ACBST

02h

ACBCST

03h

ACBCTL1

STASTRE

04h

ACBADDR

SAEN

05h

ACBCTL2

5

4

3

2

1

0

ACB Serial Data
SLVSTP

SDAST

Reserved

ZFx86 Data Book 1.0 Rev D

NMINTE

BER

NEGACK

STASTR

NMATCH MASTER

XMIT

TGSCL

TSDA

GCMTCH

MATCH

BB

BUSY

GCMEN

ACK

Reserved

INTEN

STOP

START

ADDR
SCLFRQ

ENABLE

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4
4.13. Legacy Functional Blocks
This chapter briefly describes the following
blocks that provide legacy device functions:
• Keyboard and Mouse Controller (KBC)

The register maps in this chapter use abbreviations for Type. See Table 4.55 "Register Type
Abbreviations" on page 269.

• Floppy Disk Controller (FDC)

4.13.1. Keyboard and Mouse Controller
(KBC)

• Parallel Port
• Serial Port 1 and Serial Port 2(SP1 and
SP2), UART Functionality for both Serial
Port 1 and Serial Port 2
• Infrared Communication Port Functionality
The description of each Legacy block includes
the sections listed below.
• General Description

The KBC is implemented physically as a
single hardware module and houses two
separate logical devices: a Mouse controller
and a Keyboard controller.
The KBC is functionally equivalent to the
industry standard 8042A Keyboard controller,
which may serve as a detailed technical reference for the KBC.

• Register Map table(s)
• Bitmap table(s)
Table 4.147 KBC Register Map
Offset
00h

04h

Mnemonic

Register Name

Type

DBBOUT

Read KBC Data

R

DBBIN

Write KBC Data

W

STATUS

Read Status

R

DBBIN

Write KBC Command

W

Table 4.148 KBC Bitmap Summary
Register
Offset Mnemonic

Bits
7

6

5

4

3

2

DBBOUT

KBC Data Bits (For Read cycles)

DBBIN

KBC Data Bits (For Write cycles)

1

0

IBF

OBF

00h

STATUS

General Purpose Flags

F1

F0

04h
DBBIN

ZFx86 Data Book 1.0 Rev D

KBC Command Bits (For Write cycles)

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4.13.2. Floppy Disk Controller (FDC)
The generic FDC is a standard FDC with a
digital data separator, and is DP8473 and
N82077 software compatible.
The FDC is implemented in this device as
follows:
• FM and MFM modes are supported. To
select either mode, set bit 6 of the first
command byte when writing to/reading

from a diskette, where:
0 = FM mode
1 = MFM mode
• Automatic media sense is supported on
the Parallel Port pins.
• A logic 1 is returned for all floating (TRISTATE) FDC register bits upon LPC I/O
read cycles.

Table 4.149 FDC Register Map
Offset

Mnemonic

Register Name

Type

00h

SRA

Status A

RO

01h

SRB

Status B

RO

02h

DOR

Digital Output

R/W

03h

TDR

Tape Drive

R/W

04h

MSR

Main Status

R

DSR

Data Rate Select

W

FIFO

Data (FIFO)

05h
06h
07h

R/W
Reserved

DIR

Digital Input

R

CCR

Configuration Control

W

4.13.2.1. FDC Bitmap Summary
The FDC supports two system operation
modes: PC-AT mode and PS/2 mode (MicroChannel systems). Unless specifically indicated otherwise, all fields in all registers are
valid in both drive modes.

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Table 4.150 FDC Bitmap Summary
Register
Offset Mnemonic
00h

SRAa

01h

SRBa

02h

DOR

Bits
7

6

5

4

3

2

1

0

IRQ
Pending

Reserved

Step

TRK0

Head
Select

INDEX

WP

Head
Direction

Drive
Select 0
Status

WDATA

RDATA

WGATE

Reserved

MTR0

Motor
Enable 0

DMAEN

Reset
Controller

Reserved

Reserved

TDR
03h

TDRb

Reserved
Reserved

05h

Tape Drive Select 1,0
Logical Drive
Exchange

Drive ID Information

MSR

RQM

Data I/O
Direction

Non-DMA
Execution

Command
Drive 3
in
Busy
Progress

DSR

Software
Reset

Low
Power

Reserved

Precompensation Delay Select

04h

FIFO

Drive 2
Busy

Tape Drive Select 1,0
Drive 1
Busy

Drive 0
Busy

Data Transfer Rate
Select

Data Bits

DIRc

DSKCHG

DIRa

DSKCHG

Reserved

07h

07h

Drive Select

CCR

Reserved

High
Density

Reserved

a. Applicable only in PS/2 Mode
b. Applicable only in Enhanced TDR Mode
c. Applicable only in PC-AT Compatible Mode

4.13.3. Parallel Port
The Parallel Port supports all IEEE1284 standard communication modes:
• Compatibility (known also as Standard or
SPP)
• Bidirectional (known also as PS/2)
• FIFO, EPP (known also as Mode 4)
• ECP (with an optional Extended ECP
mode)

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4.13.3.1. Parallel Port Register Map

offset registers are available only when base
address is 8-byte aligned.

The Parallel Port functional block register
maps are grouped according to first and
second level offsets. EPP and second level

Table 4.151 Parallel Port Register Map for First Level Offset
First Level
Offset

Mnemonic

Register Name

Modes (ECR Bits) 7 6 5

Type

000h

DATAR

PP Data

000
001

R/W

000h

AFIFO

ECP Address FIFO

011

W

001h

DSR

Status

All Modes

RO

002h

DCR

Control

All Modes

R/W

003h

ADDR

EPP Address

100

R/W

004h

DATA0

EPP Data Port 0

100

R/W

005h

DATA1

EPP Data Port 1

100

R/W

006h

DATA2

EPP Data Port 2

100

R/W

007h

DATA3

EPP Data Port 3

100

R/W

400h

CFIFO

PP Data FIFO

010

W

400h

DFIFO

ECP Data FIFO

011

R/W

400h

TFIFO

Test FIFO

110

R/W

400h

CNFGA

Configuration A

111

RO

401h

CNFGB

Configuration B

111

RO

402h

ECR

Extended Control

All Modes

R/W

403h

EIR

Extended Index

All Modes

R/W

404h

EDR

Extended Data

All Modes

R/W

405h

EAR

Extended Auxiliary Status

All Modes

R/W

Table 4.152 Parallel Port Register Map for Second Level Offset
Second Level Offset

Register Name

Type

00h

Control0

R/W

02h

Control2

R/W

04h

Control4

R/W

05h

PP Confg0

R/W

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4.13.3.2. Parallel Port Bitmap Summary
The Parallel Port functional block bitmaps are
grouped according to first and second level
offsets.
Table 4.153 Parallel Port Bitmap Summary for First Level Offset
Register
Offset

Mnemonic

Bits
7

6

5

4

3

DATAR

Data Bits

AFIFO

Address Bits

2

1

0

000h

Printer
Status

ACK
Status

PE Status

SLCT
Status

ERR
Status

Reserved

EPP
Time-out
Status

Direction
Control

Interrupt
Enable

PP Input
Control

Printer
Automatic
Initialization Line Feed
Control
Control

Data
Strobe
Control

001h

DSR

002h

DCR

003h

ADDR

EPP Device or Register Selection Address Bits

004h

DATA0

EPP Device or R/W Data

005h

DATA1

EPP Device or R/W Data

006h

DATA2

EPP Device or R/W Data

007h

DATA3

EPP Device or R/W Data

400h

CFIFO

Data Bits

400h

DFIFO

Data Bits

400h

TFIFO

Data Bits

400h

CNFGA

401h

CNFGB

402h

ECR

403h

EIR

404h

EDR

405h

EAR

Reserved

Bit 7 of
PP
Confg0

Reserved

Reserved

Interrupt
Request
Value

Interrupt Select

Reserved

DMA Channel Select

ECP Mode Control

ECP
Interrupt
Mask

ECP
Interrupt
Service

FIFO Full

Reserved

ECP DMA
Enable

Reserved

FIFO
Empty

Second Level Offset
Data Bits

FIFO Tag

ZFx86 Data Book 1.0 Rev D

Reserved

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4
Table 4.154 Parallel Port Bitmap Summary for Second Level Offset
Register
Second
Level
Offset

Mnemonic

Bits
7

6

00h

Control0

02h

Control2

SPP
Compatibility

04h

Control4

Reserved

PP Confg0

Bit 3 of
CNFGA

05h

Reserved

Channel
Address
Enable

5

DCR
Register
Live

Freeze Bit

Reserved

Revision
1.7 or 1.9
Select

PP DMA Request Inactive Time
Demand
DMA
Enable

3

Both Serial Port 1 and 2 provide UART functionality with remote peripheral devices or a
modem using a wired interface. The UART
functions as a standard 16450, 16550, or as
an Extended UART.

2

1

0
EPP
Time-out
Interrupt
Mask

Reserved

Reserved

Reserved

ECP IRQ Channel Number

4.13.4. UART Functionality (SP1/SP2)

ZFx86 Data Book 1.0 Rev D

4

PP DMA Request Active Time
PE
Internal
Pull-up or
Pull-down

ECP DMA Channel
Number

4.13.4.1. UART Mode Register Bank
Overview
Four register banks, each containing eight
registers, control UART operation. All registers
use the same 8-byte address space to indicate
offsets 00h through 07h. The BSR register
selects the active bank and is common to all
banks. See Figure 4-16.

Page 340

4
BANK 3
BANK 2
BANK 1

Common
Register
Throughout
All Banks

BANK 0
Offset 07h
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
Offset 02h
Offset 01h
Offset 00h

16550 Banks
Figure 4-16 UART Mode Register Bank Architecture

4.13.4.2. SP1 and SP2 Register Maps for UART Functionality
Table 4.155 Bank 0 Register Map
Offset

Mnemonic

00h

RXD

Receiver Data Port

RO

00h

TXD

Transmitter Data Port

W

01h

IER

Interrupt Enable

R/W

02h

EIR

Event Identification (Read Cycles)

RO

FCR

FIFO Control (Write Cycles)

W

LCRa

Line Control

BSRa

Bank Select

04h

MCR

Modem/Mode Control

R/W

05h

LSR

Link Status

RO

06h

MSR

Modem Status

RO

03h

07h

Register Name

SPR/ASCR Scratch pad/Auxiliary Status and Control

Type

R/W

R/W

a. When bit 7 of this Register is set to 1, bits 6-0 of BSR select the bank, as shown in
Table 4.156.

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Table 4.156 Bank Selection Encoding
BSR Bits
Bank Selected
7

6

5

4

3

2

1

0

0

x

x

x

x

x

x

x

1

0

x

x

x

x

x

x

1

1

1

x

x

x

x

1

x

1

1

1

x

x

x

x

x

1

1

1

1

1

0

0

0

0

0

2

1

1

1

0

0

1

0

0

3

0

Table 4.157 Bank 1 Register Map
Offset

Mnemonic

Register Name

Type

00h

LBGD(L)

Legacy Baud Generator Divisor Port (Low Byte)

R/W

01h

LBGD(H)

Legacy Baud Generator Divisor Port (High Byte)

R/W

02h

Reserved

03h

LCR/BSR

Line Control/Bank Select

04h - 07h

R/W

Reserved

Table 4.158 Bank 2 Register Map
Offset

Mnemonic

Register Name

00h

BGD(L)

Baud Generator Divisor Port (Low Byte)

R/W

01h

BGD(H)

Baud Generator Divisor Port (High Byte)

R/W

02h

EXCR1

Extended Control1

R/W

03h

LCR/BSR

Line Control/Bank Select

R/W

04h

EXCR2

Extended Control 2

R/W

05h

Type

Reserved

06h

TXFLV

TX_FIFO Level

R/W

07h

RXFLV

RX_FIFO Level

R/W

Table 4.159 Bank 3 Register Map
Offset

Mnemonic

00h

MRID

01h

Register Name

Type

Module Revision ID

RO

SH_LCR

Shadow of LCR (Read Only)

RO

02h

SH_FCR

Shadow of FIFO Control (Read Only)

RO

03h

LCR/BSR

Line Control/Bank Select

R/W

04h-07h

ZFx86 Data Book 1.0 Rev D

Reserved

Page 342

4
4.13.4.3. SP1 and SP2 Bitmap Summary for UART Functionality
Table 4.160 Bank 0 Bitmap
Register
Offset

Mnemonic

Bits
7

6

5

4

3

RXD

Receiver Data Bits

TXD

Transmitter Data Bits

2

1

0

00h

IERa

Reserved

01h
IERb
EIRa
02h

EIRb

Reserved
FEN1

TXEMP_IE

FEN0

Reserved

Reservedc
or DMA_IEd

Reserved

MS_IE

LS_IE

TXLDL_IE RXHDL_IE

MS_IE

LS_IE

TXLDL_IE RXHDL_IE

RXFT

IPR1

TXEMP_EV

Reservedc
or DMA_EVd

MS_EV

IPR0

IPF

LS_EV or
TXLDL_EV RXHDL_EV
TXHLT_EV

FCR

RXFTH1

RXFTH0

TXFTH1

TXFTH0

Reserved

TXSR

RXSR

FIFO_EN

LCRe

BKSE

SBRK

STKP

EPS

PEN

STB

WLS1

WLS0

BSRe

BKSE

ISEN or
DCDLP

RILP

RTS

DTR

TX_DFR

Reserved

RTS

DTR

03h

MCRa

Bank Select
Reserved

LOOP

04h
MCRb

Reserved

05h

LSR

ER_INF

TXEMP

TXRDY

BRK

FE

PE

OE

RXDA

06h

MSR

DCD

RI

DSR

CTS

DDCD

TERI

DDSR

DCTS

SPRa

Scratch Data

07h
ASCRb
a.
b.
c.
d.
e.

Reserved

TXURd

RXACTd

RXWDGd

Reserved

S_OETd

Reserved RXF_TOUT

Non-Extended Mode
Extended Mode
In SP2 only.
In SP1 only
When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 4.156.

ZFx86 Data Book 1.0 Rev D

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Table 4.161 Bank 1 Bitmap
Register

Bits

Offset

Mnemonic

7

6

5

4

3

2

1

00h

LBGD(L)

Legacy Baud Generator Divisor (Least Significant Bits)

01h

LBGD(H)

Legacy Baud Generator Divisor (Most Significant Bits)

0

Reserved

02h
03h

LCR/BSR

Same as Bank 0
Reserved

04h-07h

Table 4.162 Bank 2 Bitmap
Register
Offset Mnemonic

Bits
7

6

5

4

3

2

1

00h

BGD(L)

Baud Generator Divisor Low (Least Significant Bits)

01h

BGD(H)

Baud Generator Divisor High (Most Significant Bits)

02h

EXCR1

03h

LCR/BSR

04h

EXCR2

BTEST

Reserved

ETDLBK

LOOP

0

Reserved

EXT_SL

Same as Bank 0
LOCK

Reserved

PRESL1

PRESL0

Reserved

Reserved

05h
06h

TXFLV

Reserved

TFL4

TFL3

TFL2

TFL1

TFL0

07h

RXFLV

Reserved

RFL4

RFL3

RFL2

RFL1

RFL0

Table 4.163 Bank 3 Bitmap
Register

Bits

Offset

Mnemonic

7

6

5

4

3

00h

MRID

01h

SH_LCR

BKSE

SBRK

STKP

EPS

PEN

STB

WLS1

WLS0

02h

SH_FCR

RXFTH1

RXFTH0

TXFHT1

TXFTH0

Reserved

TXSR

RXSR

FIFO_EN

03h

LCR/BSR

Module ID (MID 7-4)

04h-07h

ZFx86 Data Book 1.0 Rev D

2

1

0

Revision ID(RID 3-0)

Same as Bank 0
Reserved

Page 344

4
4.13.5. IR Communication Port (IRCP) Functionality
This section describes the IR support registers. The IR functional block provides
advanced, versatile serial communications
features with IR capabilities.
The IRCP also supports two DMA channels;
the functional block uses either one or both of

them. One channel required for IR-based
applications, since IR communication works in
half duplex fashion. Two channels would
normally be needed to handle high-speed full
duplex IR based applications.

Section Quick Reference
4.13.5.1. "Functional Overview Of IR Modes" on page 346
"UART Mode" on page 346.
"SHARP-IR Mode" on page 346.
"SIR Mode" on page 347.
"Consumer Electronic IR (CEIR) Mode" on page 347.
"IrDA 1.1 MIR and FIR Modes" on page 349.
"High Speed Infrared Transmit Operation" on page 350.
"High Speed Infrared Receive Operation" on page 351.
4.13.5.2. "Special Features Description" on page 352
"FIFO Timeouts" on page 352.
"Transmit Deferral" on page 352.
"Automatic Fallback to 16550 Compatibility Mode" on page 353.
"Optical Transceiver Interface" on page 354.
4.13.5.3. "IR Mode Register Bank Overview" on page 354
4.13.5.4. "IRCP Register Map" on page 356
"BANK 0" on page 356.
"BANK 1" on page 373.
"BANK 2" on page 375.
"BANK 3" on page 380.
"BANK 4" on page 382.
"BANK 5" on page 385.
"BANK 6" on page 388.
"BANK 7" on page 393.

ZFx86 Data Book 1.0 Rev D

Page 345

4
4.13.5.1. Functional Overview Of IR Modes
This section describes all operation modes.
Although each mode is unique, certain system
resources and features are common.

UART Mode
UART mode supports serial data communication with a remote peripheral device or modem
using a wired interface. The functional block
provides receive and transmit channels that
operate concurrently in full-duplex mode. This
functional block performs all functions required
to conduct parallel data interchange with the
system and composite serial data exchange
with the external data channel.
Use this mode to support serial data communications with a remote peripheral module or
modem using a wired interface. It provides
transmit and receive channels that operate
concurrently to handle full-duplex operation.
They perform parallel-to-serial conversion on
data characters received from the CPU or a
DMA controller, and serial-to-parallel conversion on data characters received from the
serial interface. The format of the serial data
stream is shown in Figure 4-17. A data character contains 5 to 8 data bits, preceded by a
start bit and followed by an optional parity bit
and a stop bit. Data is transferred in Little
Endian order (least significant bit first).

START -LSB- DATA 5-8 -MSB- PARITY

STOP

tional features include: transmitter FIFO
(TX_FIFO) thresholding, DMA capability, and
interrupts on transmitter empty and DMA
event.
The clock for both transmit and receive channels is provided by an internal baud generator
that divides its input clock by any divisor value
from 1 to 216 -1. This output clock frequency
must be programmed to be sixteen times the
baud rate value. The baud generator input
clock is derived from a 24 MHz clock through a
programmable prescaler. The prescaler value
is determined by the PRESL bits in the
EXCR2 register. Its default value is 13. This
allows all the standard baud rates, up to 115.2
Kbaud, to be obtained. Smaller prescaler
values allow baud rates up to 921.6 Kbaud
(standard) and 1.5 Mbaud (non-standard).
Before operation begins, both the communications format and baud rate must be
programmed by the software. Program the
communications format by loading a control
byte into the LCR register, select the baud rate
by loading an appropriate value into the baud
generator divisor register. The software reads
the status of the functional block at any time
during operation. The status information
includes FULL/EMPTY state for both transmit
and receive channels, and any other condition
detected on the received data stream, such as
parity error, framing error, data overrun, or
break event.

Figure 4-17 Composite Serial Data

SHARP-IR Mode
Implement UART mode in standard 16450 and
16550 compatibility (Non-Extended) and
Extended mode. UART 16450 compatibility
mode is the default after power-up or reset.
When you select Extended mode, the functional block architecture changes slightly and
a variety of additional features are available.
The interrupt sources are no longer prioritized,
and an auxiliary status and control register
replaces the scratch pad register. The addi-

ZFx86 Data Book 1.0 Rev D

This mode supports bidirectional data communication with a remote device using IR radiation as the transmission medium. Sharp-IR
uses Digital Amplitude Shift Keying (DASK)
and allows serial communication at baud rates
up to 38.4 Kbaud. The format of the serial data
is similar to the UART data format. Each data
word is sent serially beginning with a 0 value
start bit, followed by up to eight data bits (LSB
first), an optional parity bit, and ending with at

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least one stop bit with a binary value of one. A
logical 0 is signalled by sending a 500 KHz
continuous pulse train of IR radiation. A logical
1 is signalled by the absence of any IR signal.
This functional block performs the modulation
and demodulation operations internally, or
relies on the external optical module to
perform them.
Sharp-IR device operation is similar to operation in UART mode; the main difference being
that data transfer operations normally
performed in half duplex fashion, and the
modem control and status signals are not
used. Selection of the Sharp-IR mode is
controlled by the Mode Select (MDSL) bits in
the MCR register when the functional block is
in Extended mode, or by the IR_SL bits in the
IRCR1 register when the functional block is in
Non-Extended mode. This prevents legacy
software, running in Non-Extended mode,
from spuriously switching the functional block
to UART mode when the software writes to the
MCR register.

SIR Mode
SIR mode supports bidirectional data communication with a remote device using IR radiation as the transmit medium. SIR allows serial
communication at baud rates up to
115.2 Kbaud. The serial data format is similar
to the UART data format. Each data word is
sent serially beginning with a 0 value start bit,
followed by eight data bits (LSB first), an
optional parity bit, and ending with at least one
stop bit with a binary value of 1. A 0 value is
signalled by sending a single IR pulse. A 1
value is signalled by not sending any pulse.
The width of each pulse can be either 1.6
msec or 3/16 of the time required to transmit a
single bit. (1.6 msec equals 3/16 of the time
required to transmit a single bit at 115.2 Kbps.)
This way, each word begins with a pulse for
the start bit.
Operation in SIR is similar to the operation in
UART mode, the main difference being that
data transfer operations are normally

ZFx86 Data Book 1.0 Rev D

performed in half duplex fashion. Selection of
the IrDA 1.0 SIR mode is controlled by the
MDSL bits in the MCR register when the
UART is in Extended mode, or by the IR_SL
bits in the IRCR1 register when the UART is in
Non-Extended mode. This prevents legacy
software, running in Non-Extended mode,
from spuriously switching the functional block
to UART mode when the software writes to the
MCR register.

Consumer Electronic IR (CEIR) Mode
The CEIR circuitry is designed to optimally
support all major protocols presently used in
remote controlled home entertainment equipment: RC-5, RC-6, RECS 80, NEC and RCA.
This module, in conjunction with an external
optical device, provides the physical layer
functions necessary to support these protocols. These functions include: modulation,
demodulation, serialization, deserialization,
data buffering, status reporting, interrupt
generation, and so on. The software is responsible for the generation of the IR code to be
transmitted, and for the interpretation of the
received code.
CEIR Transmit Operation
The code to be transmitted consists of a
sequence of bytes that represent either a bit
string or a set of run-length codes. The
number of bits or run-length codes usually
needed to represent each IR code bit depends
on the IR protocol to be used. The RC-5
protocol, for example, needs two bits or
between one and two run-length codes to
represent each IR code bit.
Transmission is initiated when the CPU or
DMA module writes code bytes into the empty
TX_FIFO. Transmission is normally completed
when the CPU sets the S_EOT bit of the
ASCR register (see ‘ASCR Register, Extended
Mode’ on 371), before writing the last byte, or
when the DMA controller activates the
terminal count (TC). Transmission also terminates if the CPU simply stops transferring data

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and the transmitter becomes empty. However,
in this case, a transmitter-underrun condition
generates, which must be cleared in order to
begin the next transmission.
The transmission bytes are either de-serialized or run-length encoded, and the resulting
bit string modulates a carrier signal and is sent
to the transmitter LED. The transfer rate of this
bit string, like in UART mode, is determined by
the value programmed in the Baud Generator
Divisor registers. Unlike a UART transmission,
start, stop and parity bits are not included in
the transmitted data stream. A logic 1 in the bit
string keeps the LED off, so no IR signal is
transmitted. A logic 0 generates a sequence of
modulating pulses which lights the transmitter
LED. Frequency and pulse width of the modulating pulses are programmed by the MCFR
and MCPW fields in the IRTXMC register, as
well as the TXHSC bit of the RCCFG register.
The RC_MMD field selects the transmitter
modulation mode. If the C_PLS mode is
selected, modulating pulses generate continuously for the entire logic 0 bit time. If 6_PLS or
8_PLS mode is selected, six or eight pulses
generate each time a logic 0 bit is transmitted
following a logic 1 bit.
C_PLS modulation mode is used for RC-5,
RC-6, NEC and RCA protocols. 8_PLS or
6_PLS modulation mode is used for the RECS
80 protocol. The 8_PLS or 6_PLS mode
allows minimization of the number of bits
needed to represent the RECS 80 IR code
sequence. The current transmitter implementation supports only the modulated modes of
the RECS 80 protocol. It does not support the
Flash mode.
Note: The total transmission time for the logic
0 bits must be equal to or greater than 6 or 8
times the period of the modulation subcarrier,
otherwise fewer pulses will be transmitted.

ZFx86 Data Book 1.0 Rev D

CEIR Receive Operation
The CEIR receiver is significantly different
from a UART receiver in two ways. Firstly, the
incoming IR signals are DASK modulated,
therefore, demodulation may be necessary.
Secondly, there are no start bits in the
incoming data stream.
The operations performed by the receiver,
whenever an IR signal is detected, are slightly
different, depending on whether or not
receiver demodulation is enabled. If demodulation is disabled, the receiver immediately
becomes active. If demodulation is enabled,
the receiver checks the carrier frequency of
the incoming signal and becomes active only if
the frequency is within the programmed range.
Otherwise, the signal is ignored and no other
action is taken.
When the receiver enters the active state, the
RXACT bit of the ASCR register is set to 1.
Once in the active state, the receiver keeps
sampling the IR input signal and generates a
bit string, where a logic 1 indicates an idle
condition and a logic 0 indicates the presence
of IR energy. The IR input is sampled regardless of the presence of IR pulses at a rate
determined by the value loaded into the Baud
Generator Divisor registers. The received bit
string is either de-serialized and assembled
into 8 bit characters, or it is converted to runlength encoded values. The resulting data
bytes are then transferred into the receiver
FIFO (RX_FIFO).
The receiver also sets the RXWDG bit of the
ASCR register each time an IR pulse signal is
detected. This bit is automatically cleared
when the ASCR register is read. It is intended
to assist the software in determining when the
IR link has been idle for a certain time. The
software can then stop data from being
received by writing a 1 into the RXACT bit to
clear it and return the receiver to the inactive
state.

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The frequency bandwidth for the incoming
modulated IR signal is selected by the DFR
and DBW fields in the IRRXDC register. There
are two CEIR receive data modes: Oversampled and Programmed T Period. For either
mode, the sampling rate is determined by the
setting of the Baud Generator Divisor registers.
Oversampled mode can be used with the
receiver demodulator either enabled or
disabled. It should be used with the demodulator disabled when a detailed snapshot of the
incoming signal is needed; for example, to
determine the period of the carrier signal. If
the demodulator is enabled, the stream of
samples can be used to reconstruct the
incoming bit string. To obtain good resolution,
a fairly high sampling rate should be selected.
Programmed T Period mode should be used
with the receiver demodulator enabled. The T
Period represents one-half bit time for protocols using biphase encoding, or the basic unit
of pulse distance for protocols using pulse
distance encoding. The baud is usually
programmed to match the T Period. For long
periods of logic low or high, the receiver
samples the demodulated signal at the
programmed sampling rate.

IrDA 1.1 MIR and FIR Modes
The functional block supports both IrDA 1.1
MIR and FIR modes, with data rates of 576
kbps, 1.152 Mbps and 4.0 Mbps. Details on
the frame format, encoding schemes, CRC
sequences, etc. are provided in the appropriate IrDA documents. The MIR transmitter
front end section performs bit stuffing on the
outbound data stream and places the Start
and Stop flags at the beginning and end of
MIR frames. The MIR receiver front end
section removes flags and “de-stuffs” the
inbound bit stream, and checks for abort
conditions.
The FIR transmitter front end section adds the
Preamble as well as Start and Stop flags to
each frame, and encodes the transmit data
into a 4 Pulse Position Modulation (PPM) data
stream. The FIR receiver front end section
strips the Preamble and flags from the
inbound data stream and decodes the 4 PPM
data while also checking for coding violations.
Both MIR and FIR front ends also automatically append CRC sequences to transmitted
frames and check for CRC errors on received
frames.

Whenever a new IR energy pulse is detected,
the receiver synchronizes the sampling
process to the incoming signal timing. This
reduces timing related errors and eliminates
the possibility of missing short IR pulse
sequences, especially with the RECS 80
protocol. In addition, the Programmed T
Period sampling minimizes the amount of data
used to represent the incoming IR signal,
therefore reducing the processing overhead in
the host CPU.

ZFx86 Data Book 1.0 Rev D

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High Speed Infrared Transmit Operation
When the transmitter is empty, if either the
CPU or the DMA controller writes data into the
TX_FIFO, transmission of a frame begins.
Frame transmission can be normally
completed by using one of the following
methods:
• S_EOT bit (Set End of Transmission).
This method is used when data transfers
are performed in Programmed
Input/Output (PIO) mode. When the CPU
sets the S_EOT bit before writing the last
byte into the TX_FIFO, the byte will be
tagged with an EOF indication. When this
byte reaches the TX_FIFO bottom and is
read by the transmitter front end, a CRC is
appended to the transmitted DATA and the
frame is normally terminated.
• DMA TC Signal (DMA Terminal Count).
This method is used when data transfers
are performed in DMA mode. It works similarly to the previous method except that
the tagging of the last byte of a frame
occurs when the DMA controller asserts
the TC signal during the write of the last
byte to the TX_FIFO.
Frame Length Counter. This method can be
used when data transfers are performed in
either PIO or DMA mode. The value of the
FEND_MD bit of the IRCR2 register determines whether the Frame Length Counter is
effective in the PIO or DMA mode. The
counter is loaded from the Frame Length
register (TFRL) at the beginning of each
frame, and it is decremented as each byte is
transmitted. An EOF is generated when the
counter reaches 0. When used in DMA mode
with an 8237 type DMA controller, this method
allows a large data block to be automatically
split into equal-size back-to-back frames, plus
a shorter frame that is terminated by the DMA
TC signal, if the block size is not an exact
multiple of the frame size.

ZFx86 Data Book 1.0 Rev D

An option is also provided to stop transmission
at the end of each frame. This happens when
the transmitter Frame End stop mode is
enabled (TX_MS bit of the IRCR2 register set
to 1). By using this option, the software can
send frames of different sizes without re-initializing the DMA controller for each frame. After
transmission of each frame, the transmitter
stops and generates an interrupt. The software loads the length of the next frame into
the TFRL register and restarts the transmitter
by clearing the TXHFE bit of the ASCR
register.
Note: PIO or DMA mode is only controlled by
setting the DMA_EN bit of the Extended mode
MCR register. The functional block treats CPU
and DMA access cycles the same except that
DMA cycles always access the TX or
RX_FIFO, regardless of the selected bank.
When DMA_EN is set to 1, the CPU can still
access the TX_FIFO and RX_FIFO. The CPU
accesses will, however, be treated as DMA
accesses as far as the function of the
FEND_MD bit is concerned.
While a frame is being transmitted, data must
be written to the TX_FIFO at a rate dictated by
the transmission speed. If the CPU or DMA
controller fails to meet this requirement, a
transmitter underrun occurs, an inverted CRC
is appended to the frame being transmitted,
and the frame is terminated with a Stop flag.
Data transmission then stops. Transmission of
the inverted CRC guarantees that the remote
receiving module receives the frame with a
CRC error and discards it.
Following an underrun condition, data transmission always stops at the next frame
boundary. The frame bytes from the point
where the underrun occurred to the end of the
frame are not sent out to the external infrared
interface. Nonetheless, they are removed from
the TX_FIFO by the transmitter and discarded.
The underrun indication is reported only when
the transmitter detects the end of frame via

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one of the methods described above. The software can do various things to recover from an
underrun condition. For example, it can simply
clear the underrun condition by writing a 1 into
bit 6 of ASCR and retransmit the underrun
frame later, or it can retransmit it immediately,
before transmitting other frames.
If it chooses to retransmit the frame immediately, it needs to perform the following steps:
1. Disable DMA controller, if DMA mode was
selected.
2. Read the TXFLV register to determine the
number of bytes in the TX_FIFO. (This is
needed to determine the exact point where
the underrun occurred, and whether or not
the first byte of a new frame is in the
TX_FIFO.)
3. Reset TX_FIFO.
4. Backup DMA controller registers.
5. Clear Transmitter underrun bit.
6. Re-enable DMA controller.

High Speed Infrared Receive Operation
When the receiver front end detects an
incoming frame, it starts de-serializing the
infrared bit stream and loading the resulting
data bytes into the RX_FIFO. When the EOF
is detected, two or four CRC bytes are
appended to the received data, and an EOF
flag is written into the tag section of the
RX_FIFO, along with the last byte. In the
present implementation, the CRC bytes are
always transferred to the RX_FIFO following
the data. Additional status information, related
to the received frame, is also written into the
RX_FIFO tag section at this time. The status
information is loaded into the LSR register
when the last frame byte reaches the
RX_FIFO bottom.
The receiver keeps track of the number of
received bytes from the beginning of the
current frame. It only transfers to the RX_FIFO
a number of bytes not exceeding the
maximum frame length value which is
programmed via the RFRML register in bank

ZFx86 Data Book 1.0 Rev D

Any additional frame bytes are discarded.
When the maximum frame length value is
exceeded, the MAX_LEN error flag is set.
Although data transfers from the RX_FIFO to
memory can be performed either in PIO or
DMA mode, DMA mode should be used due to
the high data rates.
In order to handle back-to-back incoming
frames, when DMA mode is selected and an
8237 type DMA controller is used, an 8-level
Status FIFO (ST_FIFO) is provided. When an
EOF is detected, in 8237 DMA mode, the
status and byte count information for the frame
is written into the ST_FIFO. An interrupt is
generated when the ST_FIFO level reaches a
programmed threshold or an ST_FIFO timeout
occurs.
The CPU uses this information to locate the
frame boundaries in the memory buffer where
the data, belonging to the received frames,
has been transferred by the 8237 type DMA
controller.
During reception of multiple frames, if the
RX_FIFO and/or the ST_FIFO fills up due to
the DMA controller or CPU not serving them in
time, one or more frames can be crushed and
lost. This means that no bytes belonging to
these frames were written to the RX_FIFO. In
fact, a frame is lost in 8237 mode when the
ST_FIFO is full for the entire time during which
the frame is being received, even though there
were empty locations in the RX_FIFO. This is
because no data bytes can be loaded into the
RX_FIFO and then transferred to memory by
the DMA controller, unless there is at least one
available entry in the ST_FIFO to store the
number of received bytes. This information, as
mentioned before, is needed by the software
to locate the frame boundaries in the DMA
memory buffer.
In the event that a number of frames is lost for
any of the reasons mentioned above, one or
more lost-frame indications including the

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number of lost frames, are loaded into the
ST_FIFO.
Frames can also be lost in PIO mode, but only
when the RX_FIFO is full, since in these
cases, the ST_FIFO is only used to store lostframe indications. It does not store frame
status and byte count.

4.13.5.2. Special Features Description
FIFO Timeouts
Timeout mechanisms are provided to prevent
received data from remaining in the RX_FIFO
indefinitely in case the programmed interrupt
or DMA thresholds are not reached.
An RX_FIFO timeout generates a Receiver
Data Ready interrupt and/or a receiver DMA
request if bit 0 of the IER register and/or bit 2
of the MCR register (in Extended mode) are
set to 1 respectively. An RX_FIFO timeout
also sets bit 0 of the ASCR register to 1 if the
RX_FIFO is below the threshold. When a
Receiver Data Ready interrupt occurs, this bit
is tested by the software to determine whether
a number of bytes indicated by the RX_FIFO
threshold can be read without checking bit 0 of
the LSR register. A Status FIFO (ST_FIFO)
timeout is enabled only in MIR and FIR
modes, and generates an interrupt if bit 6 of
IER is set to 1.
The conditions that must exist for a timeout to
occur in the various modes of operation are
described below. When a timeout has
occurred, it can only be reset when the FIFO
is read by the CPU or DMA controller.
Timeout Conditions for MIR and FIR Modes
RX_FIFO Timeout Conditions:
1. At least one byte is in the RX_FIFO, and
2. More than 64 ms have elapsed since the
last byte was loaded into the RX_FIFO from
the receiver logic, and
3. More than 64 ms have elapsed since the
last byte was read from the RX_FIFO by the

ZFx86 Data Book 1.0 Rev D

CPU or DMA controller.
ST_FIFO Timeout Conditions:
1. At least one entry is in the ST_FIFO, and
2. More than 1 ms has elapsed since the last
byte was loaded into the RX_FIFO by the
receiver logic, and
3. More than 1 ms has elapsed since the last
entry was read from the ST_FIFO by the
CPU.
RX_FIFO Timeout Conditions for UART, SIR
and Sharp-IR Modes
1. At least one byte is in the RX_FIFO, and
2. More than four character times have
elapsed since the last byte was loaded into
the RX_FIFO from the receiver logic, and
3. More than four character times have
elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
Timeout Conditions for CEIR Mode
The RX_FIFO Timeout, in CEIR mode, is disabled while the receiver is active. The conditions for this timeout to occur are as follows:
1. At least one byte has been in the RX_FIFO
for 64 ms or more, and
2. The receiver has been inactive (RXACT=0)
for 64 ms or more, and
3. More than 64 ms have elapsed since the
last byte was read from the RX_FIFO by the
CPU or DMA controller.

Transmit Deferral
This feature allows software to send short
high-speed data frames in PIO mode without
the risk of generating a transmitter underrun.
Even though this feature is available and
works the same way in all modes, it is most
likely to be used in MIR and FIR modes to
support high-speed negotiations. This is
because in other modes, either the transmit
data rate is relatively low and thus the CPU
can keep up with it without letting an underrun
occur, as in the case of CEIR mode, or

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transmit underruns are allowed and are not
considered to be error conditions.
Transmit deferral is available only in Extended
mode and when the TX_FIFO is enabled.
When transmit deferral is enabled (TX_DFR
bit of the MCR register set to 1) and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now
writes data into the TX_FIFO, the transmitter
does not start sending the data until the
TX_FIFO level reaches 14, at which time the
internal flag is cleared. The internal flag is also
cleared and the transmitter starts transmitting
when a timeout condition is reached. This
prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not
reached.
The timeout mechanism is implemented by a
timer that is enabled when the internal flag is
set and there is at least one byte in the
TX_FIFO. Whenever a byte is loaded into the
TX_FIFO, the timer is reloaded with the initial
value. If no byte is loaded for a 64-msec time,
the timer times out and the internal flag is
cleared, thus enabling the transmitter.

Automatic Fallback to 16550
Compatibility Mode
This feature is designed to support existing
legacy software packages using the 16550
Serial Port. For proper operation, many of
these software packages require that the
module look identical to a plain 16550, since
they access the Serial Port registers directly.
Due to the fact that several extended features,
as well as new operational modes are
provided, make sure that the module is in the
proper state before executing a legacy
program.
The fallback mechanism eliminates the need
to change the state when a legacy program is
executed following completion of a program
that used extended features. It automatically
switches the module to 16550 compatibility
mode and turns off any extended features,

ZFx86 Data Book 1.0 Rev D

whenever the Baud Generator Divisor
Register is accessed through the LBGD(L) or
LBGD(H) ports in register bank 1.
In order to avoid spurious fallbacks, baud
generator divisor ports are provided in bank 2.
Baud generator divisor access through these
ports changes the baud rate setting but does
not cause fallback.
New programs designed to take advantage of
the extended features should not use
LBGD(L) and LBGD(H) to change the baud
rate. Instead, they should use BGD(L) and
BGD(H).
A fallback can occur from either Extended or
Non-Extended modes. If Extended mode is
selected, fallback is always enabled. In this
case, when a fallback occurs, the following
happens:
1. TX_FIFO and RX_FIFO switch to 16 levels.
2. A value of 13 is selected for the baud
generator prescaler.
3. ETDLBK and BTEST of the EXCR1 register
are cleared.
4. UART mode is selected.
5. The functional block switches to NonExtended mode.
When fallback occurs from Non-Extended
mode, only the first three of the above actions
occur. No switching to UART mode occurs if
either Sharp_IR or SIR infrared modes were
selected. This prevents spurious switching to
UART mode when a legacy program, running
in Infrared mode, accesses the baud rate
generator divisor register from bank 1.
Fallback from Non-Extended mode can be
disabled by setting LOCK in the EXCR2
register to 1. When LOCK is set and the functional block is in Non-Extended mode, two
scratchpad registers overlaid with LBGD(L)
and LBGD(H) are enabled. Any attempted
CPU access of the baud generator divisor
register through LBGD(L) and LBGD(H)

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accesses the scratchpad registers, without
affecting the baud rate setting. This feature
allows existing legacy programs to run faster
than 115.2 Kbaud, without realizing they are
running at this speed.

Optical Transceiver Interface
This module implements a very flexible interface for the external infrared transceiver.
Several signals are provided for this purpose.
A transceiver module with one or two receive
signals can be directly interfaced without any
additional logic. Since various operational
modes are supported, the transmitter power
as well as the receiver filter in the transceiver
module must be configured according to the
selected mode.

The register bank organization enables
access to the banks as required for activation
of all module modes, while maintaining transparent compatibility with 16450 or 16550 software, which activates only the registers and
specific bits used in those devices. For details,
see “UART Mode” on page 346.
The Bank Selection register (BSR) selects the
active bank and is common to all banks. See
Figure 4-18. Therefore, each bank defines
seven new registers.

Four special interface pins (ID/IRSL2-0 and
ID3) are used to control the operational mode
of the infrared transceiver. The logic levels of
the ID/IRSL2-0 pins are directly controlled by
the software (through the setting of bits 2-0 in
the IRCFG1 register).
The ID/IRSL2-0 pins power up as inputs and
can be driven by an external source. When in
input mode, they can be used to read the identification data of infrared adapters. The ID3 pin
is input only and is also used for this purpose.
The ID0/IRSL0/IRRX2 pin can also function as
an input to support an additional infrared
receive signal. In this case, however, only one
configuration pin will be available. The
IRSL0_DS and IRSL1_DS bits in the IRCFG4
register determine the direction of the
ID/IRSL2-0 pins.

4.13.5.3. IR Mode Register Bank
Overview
Eight register banks, each containing eight
registers, control UART operation. All registers
use the same 8-byte address space to indicate
offsets 00h through 07h. The active bank must
be selected by the software.

ZFx86 Data Book 1.0 Rev D

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BANK 7
BANK 6
Common
Register
Throughout
All Banks

BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
BANK 0
Offset 07h
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
Offset 02h
Offset 01h
Offset 00h

Figure 4-18 IRCP Register Bank Architecture

The default bank selection after system reset
is 0, which places the module in UART 16550
mode. Additionally, setting the baud in bank 1
(as required to initialize the 16550 UART)
switches the module to Non-Extended UART
mode. This ensures that running existing
16550 software switches the system to the

16550 configuration without software modification.
Table 4.164 shows the main functions of the
registers in each bank. Banks 0-3 control both
UART and IR modes of operation; banks 4-7
control and configure the IR modes only.

Table 4.164 Register Bank Summary
Bank

UART

IR Mode

Main Functions

Reference

0

3

3

Global Control and Status

“BANK 0” on page 356

1

3

3

Legacy Bank

“BANK 1” on page 373

2

3

3

Alternative Baud Generator Divisor, Extended
Control and Status

“BANK 2” on page 375

3

3

3

Module Revision ID and Shadow registers

“BANK 3” on page 380

4

3

IR mode setup

“BANK 4” on page 382

5

3

IR Control and Status FIFO

“BANK 5” on page 385

6

3

IR Physical Layer Configuration

“BANK 6” on page 388

7

3

CEIR and Optical Transceiver Configuration

“BANK 7” on page 393

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The register maps in this section use the following abbreviations for Type:
• R/W = Read/Write
• R = Read from a specific address returns
the value of a specific register. Write to the
same address is to a different register.
• W = Write
• RO = Read Only

4.13.5.4. IRCP Register Map
BANK 0
In Non-Extended modes of operation, bank 0
is compatible with both the 16450 and the
16550. Upon reset, this functional block
defaults to the 16450 mode. In Extended
mode, all the registers (except RXD/ TXD)
offer additional features.

• R/W1C = Read/Write 1 to Clear. Writing 1
to a bit clears it to 0. Writing 0 has no
effect.
Table 4.165 Bank 0 Register Map
Offset Mnemonic
00h

Register Name

Type

Section
“Receiver Data Port (RXD) or the Transmitter Data Port
(TXD)” on page 356

RXD

Receiver Data Port

RO

TXD

Transmitter Data Port

W

01h

IER

Interrupt Enable

R/W

“Interrupt Enable Register (IER)” on page 356

02h

EIR

Event Identification

RO

“Event Identification Register (EIR) and FIFO Control
Register (FCR)” on page 359

FCR

FIFO Control

R/W

LCR

Link Control

W

BSR

Bank Select

R/W

04h

MCR

Modem/Mode Control

R/W

“Modem/Mode Control Register (MCR)” on page 366

05h

LSR

Link Status

R/W

“Link Status Register (LSR)” on page 368

06h

MSR

Modem Status

R/W

“Modem Status Register (MSR)” on page 370

07h

SPR

Scratchpad

R/W

“SPR Register, Non-Extended Mode” on page 371

Varies per bit

“ASCR Register, Extended Mode” on page 371

03h

ASCR

Auxiliary Status and
Control

“Link Control Register (LCR) and Bank Select Register
(BSR)” on page 363

Receiver Data Port (RXD) or the Transmitter Data Port (TXD)
These ports share the same address.
RXD is accessed during CPU read cycles. It is
used to read data from the Receiver Holding
register when the FIFOs are disabled, or from
the bottom of the RX_FIFO when the FIFOs
are enabled.
TXD is accessed during CPU write cycles. It is
used to write data to the Transmitter Holding
register when the FIFOs are disabled, or to the
TX_FIFO when the FIFOs are enabled.

ZFx86 Data Book 1.0 Rev D

DMA cycles always access the TXD and RXD
ports, regardless of the selected bank.

Interrupt Enable Register (IER)
This register controls the enabling of various
interrupts. Some interrupts are common to all
operating modes of the functional block, while
others are mode specific. Bits 4 to 7 can be
set in Extended mode only. They are cleared
in Non-Extended mode. When a bit is set to 1,
an interrupt is generated when the corre-

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sponding event occurs. In Non-Extended
mode, most events can be identified by
reading the LSR and MSR registers. The
receiver high-data-level event can only be
identified by reading the EIR register after the
corresponding interrupt has been generated.
In Extended mode, events are identified by
event flags in the EIR register.

performed outside the interrupt service
routine, but with the CPU interrupt disabled.
Note 3: If the LSR, MSR or EIR registers are to
be polled, the interrupt sources which are identified via self-clearing bits should have their
corresponding IER bits set to 0. This prevents
spurious pulses on the interrupt output pin.

The bitmap of this register is defined differently, depending on the operating mode of the
functional block.
The different modes can be divided into the
following groups:
• UART, Sharp-IR and SIR in Non-Extended
mode (EXT_SL of the EXCR1 register is
set to 0)
• UART, Sharp-IR, SIR and CEIR in
Extended mode (EXT_SL of the EXCR1
register is set to 1)
• MIR and FIR modes
The following sections describe the bits in this
register for each of these modes.
Note 1: If the interrupt signal drives an edgesensitive interrupt controller input, it is advisable to disable all interrupts by clearing all the
IER bits upon entering the interrupt routine,
and re-enable them just before exiting it. This
guarantees proper interrupt triggering in the
interrupt controller in case one or more interrupt events occurs during execution of the
interrupt routine.
Note 2: If an interrupt source must be
disabled, the CPU can do so by clearing the
corresponding bit of the IER register.
However, if an interrupt event occurs just
before the corresponding enable bit of the IER
register is cleared, a spurious interrupt may be
generated. To avoid this problem, clearing any
IER bit should be done during execution of the
interrupt service routine. If the interrupt
controller is programmed for level-sensitive
interrupts, clearing IER bits can also be

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IER, Non-Extended Mode (UART, SIR or Sharp-IR in Non-Extended Mode)
Upon reset, the IER supports UART, SIR and
Sharp-IR in Non-Extended modes.
Location:

Offset 01h

Type:

R/W
Table 4.166 Interrupt Enable Register (IER, Non-Extended Mode)

Bit

7

6

Mnemonic

5
Reserved

Reset

0

0

0

Bit
7-4
3

4

3

2

MS_IE

LS_IE

0

0

0

1

0

TXLDL_IE RXHDL_IE
0

0

Description
Reserved
Modem Status Interrupt Enable – MS_IE
Setting this bit to 1 enables the interrupts on Modem Status events. (EIR bits 3-0 are 0000.
See Table 4.167.)

2

Link Status Interrupt Enable – LS_IE
Setting this bit to 1 enables interrupts on Link Status events. (EIR bits 3-0 are 0110.
See Table 4.167.)

1

Transmitter Low Data Level Interrupt Enable – TXLDL_IE
Setting this bit to 1 enables interrupts on Transmitter Low Data Level events (EIR bits 3-0 are 0010.
See Table 4.167.)

0

Receiver High Data Level Interrupt Enable – RXHDL_IE
Setting this bit to 1 enables interrupts on Receiver High Data Level, or RX_FIFO Timeout events (EIR bits
3-0 are 0100 or 1100. See Table 4.167.)

IER, Extended Mode (UART, SIR, Sharp-IR and CEIR in Extended Mode)
Location: Offset 01h
Type:
R/W
Bit
Mnemonic
Reset

7

6

5

4

3

2

TMR_IE

SFIF_IE

TXEMP_IE/
PLD_IE

DMA_IE

MS_IE

LS_IE/
TXHLT_IE

0

0

0

0

0

0

Bit

1

0

TXLDL_IE RXHDL_IE
0

0

Description

7

Timer Interrupt Enable– TMR_IE

6

SFIF_IE (ST_FIFO Interrupt Enable)

5

TXEMP_IE/PLD_IE (Transmitter Empty Interrupt Enable/Pipeline Load Interrupt Enable).
Setting this bit to 1 enables Transmitter Empty interrupts (in all modes) and Pipeline Load Interrupts (in SIR,
MIR and FIR).

4

DMA_IE (DMA Interrupt Enable).
Setting this bit to 1 enables the interrupt on terminal count when the DMA is enabled.

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Bit
3

Description
Modem Status Interrupt Enable – MS_IE
Setting this bit to 1 enables the interrupts on Modem Status events.

2

Link Status Interrupt Enable/Transmitter Halted Interrupt Enable – LS_IE/TXHLT_IE
Setting this bit enables Link Status Interrupts, TX_FIFO underrun interrupts in MIR and FIR and Transmitter
Halted interrupts in CEIR.

1

Transmitter Low-Data-Level Interrupt Enable – TXLDL_IE
Setting this bit to 1 enables interrupts when the TX_FIFO is below the threshold level or the Transmitter
Holding register is empty.

0

Receiver High-Data-Level Interrupt Enable – RXHDL_IE
Setting this bit to 1 enables interrupts when the RX_FIFO is equal to or above the RX_FIFO threshold level,
or an RX_FIFO timeout occurs.

Event Identification Register (EIR) and FIFO Control Register (FCR)
The EIR register, a read only register, shares
the same address as the FCR register, which
is a write only register. The EIR indicates the
interrupt source, and operates in two modes:
Non-Extended Mode (EXT_SL of the EXCR1
register is set to 0), and Extended (EXT_SL of
the EXCR1 register is set to 1).

EIR, Non-Extended Mode
In Non-Extended UART mode, the functional
block prioritizes interrupts into four levels. The
EIR indicates the highest level of interrupt that
is pending. See Table 4.167 for the encoding
of these interrupts

When in Non-Extended mode (default), this
register functions the same as in the 16550
mode.
Location: Offset 02h
Type:
RO
Bit

7

Mnemonic
Reset

6

5

0

0

FEN1, 0
0

4
Reserved

Bit
7-6

3

2

RXFT
0

0

1
IPR1, 0

0

0
IPF

0

1

Description
FEN1, 0 (FIFOs Enabled)
0=
1=

5-4

3

No FIFO enabled (default)
FIFOs enabled (bit 0 of FCR is set to 1)

Reserved – Set to 0.
RX_FIFO Timeout) – RXFT
In the 16450 mode, this bit is always 0. In the 16550 mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read timeout occurred and the associated interrupt is currently the highest priority pending
interrupt.

2-1

Interrupt Priority – IPR1, 0
When bit 0 (IPF) is 0, these bits indicate the pending interrupt with the highest priority. See Table 4.167.
Default value is 0.

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Bit
0

Description
Interrupt Pending Flag – IPF
0=
1=

Interrupt pending
No interrupt pending (default)

Table 4.167 Non-Extended Mode Interrupt Priorities
EIR Bits
3210

Priority
Interrupt Type
Level

0001

N/A

None

0110

Highest

Link Status

0100

Second

1100

Second

RX_FIFO
Timeout

0010

Third

Transmitter
Low Data
Level Event

0000

Fourth

Interrupt Source

Interrupt Reset Control

None

N/A

Parity error, framing error, data overrun
Read Link Status Register (LSR)
or break event

Receiver High Receiver Holding Register (RXD) full, or
Reading the RXD or RX_FIFO level
Data Level RX_FIFO level equal to or above
drops below threshold
Event
threshold
At least one character is in the
RX_FIFO, and no character has been
Reading the RXD port.
input to or read from the RX_FIFO for 4
character times.
Reading the EIR register if this
Transmitter Holding register or TX_FIFO interrupt is currently the highest
empty
priority pending interrupt, or writing
into the TXD port

Modem Status Any transition on CTS, DSR or DCD or Reading the Modem Status register
a low to high transition on RI
(MSR)

register bit setting. When this register is read
the DMA event (bit 4) is cleared if an 8237
type DMA is used. All other bits are cleared
when the corresponding interrupts are
acknowledged by reading the relevant register
(e.g. reading the MSR register clears MS_EV).

EIR, Extended Mode
In Extended mode, each of the previously
prioritized and encoded interrupt sources is
broken down into individual bits. Each bit in
this register acts as an interrupt pending flag,
and is set to 1 when the corresponding event
occurred or is pending, regardless of the IER
Location: Offset 02h
Type:
RO
Bit
Mnemonic
Reset

7

6

5

4

3

TMR_EV

SFIF_EV

TXEMP_EV

DMA_EV

MS_EV

0

0

0

0

0

Bit
7

2

1

0

LS_EV/
TXLDL_EV RXHDL_EV
TXHLT_EV
0

0

1

Description
Timer Event – TMR_EV
Set to 1 when the timer reaches 0. Cleared by writing 1 into bit 7 of the ASCR register.

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Bit
6

Description
ST_FIFO Event – SFIF_EV
Set to 1 when the ST_FIFO level is equal to or above the threshold, or an ST_FIFO timeout occurs. This bit
is cleared when the CPU reads the ST_FIFO and its level drops below the threshold.

5

Transmitter Empty Interrupt Enable – TXEMP_EV
This bit is the same as bit 6 of the LSR register. It is set to 1 when the transmitter is empty.

4

DMA Event – DMA_EV
This bit is set to 1 when a DMA terminal count (TC) is activated. It is cleared upon read.

3

Modem Status Event – MS_EV
UART mode: This bit is set to 1 when any of the 0 to 3 bits in the MSR register is set to 1.
Any IR mode: The function of this bit depends on the setting of IRMSSL of the IRCR2 register (see ‘IR
Control Register 2 (IRCR2)’ on 385). When IRMSSL is 0, the bit functions as Modern Status Interrupt event;
when IRMSSL is set to 1, the bit is forced to 0.

2

Link Status Event – LS_EV (
In UART, Sharp-IR and SIR:
Set to 1 when a receiver error or break condition is reported. When FIFOs are enabled, the Parity Error),
Frame Error and Break conditions are only reported when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error is reported as soon as it occurs.
LS_EV/TXHLT_EV (Link Status Event or Transmitter Halted Event) - In MIR and FIR:
Set to 1 when any of the following conditions occur:
1. Last byte of received frame reaches the bottom of the RX_FIFO
2. Receiver overrun
3. Transmitter underrun
4. Transmitter halted on frame end in CEIR mode
Link Status Event or Transmitter Halted Event – LS_EV/TXHLT_EV
In CEIR:
Set to 1 when the receiver is overrun or the transmitter underrun.
Note: A high speed CPU can service the interrupt generated by the last frame byte reaching the RX_FIFO bottom before that byte is transferred to memory by the DMA controller. This can happen when the CPU interrupt
latency is shorter than the RX_FIFO Timeout (Refer to the “FIFO Timeouts” section). A DMA request is generated only when the RX_FIFO level reaches the DMA threshold or when a FIFO timeout occurs, in order to minimize the performance degradation due to DMA signal handshake sequences. If the DMA controller must be
set up before receiving each frame, the software in the interrupt routine should make sure that the last byte of
the frame just received has been transferred to memory before re-initializing the DMA controller, otherwise that
byte could appear as the first byte of the next received frame.

1

Transmitter Low-Data-Level Event – TXLDL_EV
FIFOs disabled: Set to 1 when the Transmitter Holding register is empty.
FIFOs enabled: Set to 1 when the TX_FIFO level is below the threshold level.

0

Receiver High-Data-Level Event – RXHDL_EV
FIFOs disabled: Set to 1 when a character is in the Receiver Holding register.
FIFOs enabled: Set to 1 when the RX_FIFO is above threshold or an RX_FIFO timeout has occurred.

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FIFO Control Register (FCR)
The FCR register is a write only register which
shares the same address as the EIR (see
"Event Identification Register (EIR) and FIFO
Control Register (FCR)" on page 359) which is
a read only register. FCR is used to enable the

FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the RX_FIFO and
TX_FIFO. FCR may be read through SH_FCR
register in bank 3 (see ‘Shadow of FIFO
Control Register (SH_FCR)’ on 381).

Location: Offset 02h
Type:
W
Bit

7

Mnemonic

6

5

RXFTH1, 0

Reset

0

4
TXFTH1, 0

0

0

Bit
7-6

3

2

1

0

Reserved

TXSR

RXSR

FIFO_EN

0

0

0

0

0
Description

RX_FIFO Interrupt Threshold Level – RXFTH1, 0
These bits select the RX_FIFO interrupt threshold level. An interrupt is generated when the level of the data
in the RX_FIFO is equal to or above the encoded threshold.
Bits

5-4

RX_FIF0 Interrupt Threshold Level

7

6

(16-Level FIFO)

(32-Level FIFO)

0
0
1
1

0
1
0
1

1(Default)
4
8
14

1(Default)
8
16
26

Transmitter Empty – TXFTH1, 0
In Non-Extended modes, these bits have no effect. In Extended modes, these bits select the TX_FIFO
interrupt threshold level. An interrupt is generated when the level of the data in the TX_FIFO drops below
the encoded threshold.
Bits

TX_FIF0 Interrupt Threshold Level

5

4

(16-Level FIFO)

(32-Level FIFO)

0
0
1
1

0
1
0
1

1(Default)
3
9
13

1(Default)
7
17
25

3

Reserved. Write 0.

2

Transmitter Soft Reset – TXSR
Writing a 1 to this bit generates a transmitter soft reset, which clears the TX_FIFO and the transmitter logic.
This bit is automatically cleared by the hardware.

1

Receiver Soft Reset – RXSR
Writing a 1 to this bit generates a receiver soft reset, which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.

0

FIFO Enable – FIFO_EN
When set to 1, enables both the TX_FIFO and RX_FIFOs. Resetting this bit clears both FIFOs. In MIR, FIR
and CEIR modes, the FIFOs are always enabled and the setting of this bit is ignored.

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Link Control Register (LCR) and Bank Select Register (BSR)
These registers share the same address.

Bank Select Enable (BKSE, bit 7) determines
the register to be accessed, as follows:

The Link Control register (LCR) selects the
communications format for data transfers in
UART, SIR and Sharp-IR modes.

• If bit 7 is 0, both LCR and BSR are written
into.

The Bank select register (BSR) is used to
select the register bank to be accessed next.

• If bit 7 is 1, only BSR is written into, and
LCR remains unchanged. This prevents
the communications format from being
spuriously affected when a bank other
than bank 0 or bank 1 is accessed.

Reading the register at this address location
returns the content of the BSR. The content of
LCR may be read from the Shadow of Link
Control register (SH_LCR) in bank 3 (see
‘Shadow of Link Control Register (SH_LCR)’
on 381). During a write operation to this
register at this address location, setting of

LCR Register
Bits 6-0 are only effective in UART, Sharp-IR
and SIR modes. They are ignored in CEIR,
MIR and FIR modes.

Location: Offset 03h
Type:
W
Bit
Mnemonic
Reset

7

6

5

4

3

2

BKSE

SBRK

STKP

EPS

PEN

STB

0

0

0

0

0

0

Bit
7

1

0
WLS1, 0

0

0

Description
Bank Select Enable – BKSE

0: Register functions as the Link Control register (LCR).
1: Register functions as the Bank Select register (BSR).
6

Set Break – SBRK

Enables or disables a break. During the break, the transmitter can be used as a character timer to
accurately establish the break duration. This bit acts only on the transmitter front end and has no
effect on the rest of the transmitter logic.When set to 1 the following occurs:
If a UART mode is selected, the SOUT pin is forced to a logic 0 state.
If SIR mode is selected, pulses are issued continuously on the IRTX pin.
If Sharp-IR mode is selected and internal modulation is enabled, pulses are issued continuously on the IRTX
pin.
If Sharp-IR mode is selected and internal modulation is disabled, the IRTX pin is forced to a logic 1 state.
To avoid transmission of erroneous characters as a result of the break, use the following procedure to set
SBRK:
• Wait for the transmitter to be empty. (TXEMP = 1).
• Set SBRK to 1.
• Wait for the transmitter to be empty, and clear SBRK when normal transmission must be restored.
5

Stick Parity – STKP
When parity is enabled (PEN is 1), this bit and EPS (bit 4) control the parity bit as shown in Table 4.168

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Bit
4

Description
Even Parity Select – EPS
When parity is enabled (PEN is 1), this bit and STKP (bit 5) control the parity bit, as shown in Table 4.168.

0: If parity enabled, an odd number of logic 1’s is transmitted or checked in the data word bits and
parity bit. (default)
1: If parity enabled, an even number of logic 1’s is transmitted or checked
3

Parity Enable – PEN
This bit enables the parity bit. See Table 4.168. The parity enable bit is used to produce an even or odd
number of 1’s when the data bits and parity bit are summed, as an error detection device.

0: No parity bit used (default)
1: A parity bit is generated by the transmitter and checked by the receiver
2

Stop Bits – STB
This bit specifies the number of stop bits transmitted with each serial character.

0: 1 stop bit generated (default)
1: If the data length is set to 5 bits via bits 1,0 (WLS1,0), 1.5 stop bits are generated. For 6, 7 or
8 bit word lengths, 2 stop bits are transmitted. The receiver checks for 1 stop bit only,
regardless of the number of stop bits selected.
1-0 Character Length Select – WLS1, 0
These bits specify the number of data bits in each transmitted or received serial character and are encoded
as follows:

Bits
1 0

Character Length

0
0
1
1

5 (Default)
6
7
8

0
1
0
1

Table 4.168 Bit Settings for Parity Control
PEN

ZFx86 Data Book 1.0 Rev D

EPS

STKP

Selected Parity Bit

0

x

x

None

1

0

0

Odd

1

1

0

Even

1

0

1

Logic 1

1

1

1

Logic 0

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access this register, see the description of
BKSE (bit 7) of the LCR register.

BSR Register, All Banks
The BSR register selects which register bank
is to be accessed next. For details on how to
Location: Offset 03h
Type:
R/W
Bits

7

Mnemonic
Reset

6

5

4

BKSE
0

1

0

0

0

0

0

0

0

0

Description
Bank Select Enable – BKSE
0=
1=

6-0

2

BSR6-0

Bit
7

3

Bank 0 selected
Bits 6-0 specify the selected bank

Bank Select
When BKSE (bit 7) is set to 1, these bits select the bank, as shown in Table 4.169.

Table 4.169 Bank Selection Encoding
BSR Bits
Bank Selected
7

6

5

4

3

2

1

0

0

x

x

x

x

x

x

x

0

1

0

x

x

x

x

x

x

1

1

1

x

x

x

x

1

x

1

1

1

x

x

x

x

x

1

1

1

1

1

0

0

0

0

0

2

1

1

1

0

0

1

0

0

3

1

1

1

0

1

0

0

0

4

1

1

1

0

1

1

0

0

5

1

1

1

1

0

0

0

0

6

1

1

1

1

0

1

0

0

7

1

1

1

1

1

x

0

0

Reserved

1

1

0

x

x

x

0

0

Reserved

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Modem/Mode Control Register (MCR)
This register controls the interface with the modem or data communications set, and the device operational mode when the device is in the
Extended mode. The register function differs
for Extended and Non-Extended modes.
MCR, Non-Extended Mode
Location: Offset 04h
Type:
R/W
Bit

7

6

5

Reserved

Mnemonic
Reset

0

0

0

Required

0

0

0

Bit
7-5
4

4

3

2

1

0

LOOP

ISEN or
DCDLP

RILP

RTS

DTR

0

0

0

0

0

Description
Reserved
Loopback Enable – LOOP
This bit accesses the same internal register as LOOP (bit 4) of the EXCR1 register (See ‘Extended Control
Register 1 (EXCR1)’ on 375 for more information on Loopback mode).
0 = Loopback disabled (default)
1 = Loopback enabled

3

Interrupt Signal Enable or DCD Loopback – ISEN or DCDLP
In normal operation (standard 16450 or 16550) mode, this bit controls the interrupt signal and must be set
to 1 in order to enable the interrupt request signal. When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD. New programs should always keep this bit set to 1 during
normal operation. The interrupt signal should be controlled through the Plug and Play logic.

2

Request Interrupt in Loopback – RILP
When loopback is enabled, this bit internally drives RI. Otherwise, it is unused.

1

Request To Send – RTS
This bit controls the RTS signal output. When set to 1, RTS is driven low. When loopback is enabled, this
bit drives CTS internally.

0

Data Terminal Ready – DTR
Controls the DTR signal output. When set to 1, DTR is driven low. When loopback is enabled, this bit
internally drives DSR.

MCR, Extended Mode
In Extended mode, this register is used to
select the operation mode (IrDA, Sharp, etc.)
of the device and to enable the DMA interface.
In these modes, the interrupt output signal is
always enabled, and loopback can be enabled
by setting bit 4 of the EXCR1 register.

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Location: Offset 04h
Type:
R/W
Bit

7

Mnemonic

6

5

MDSL2-0

Reset

0

0

0

Bit
7-5

4

3

2

1

0

IR_PLS

TX_DFR

DMA_EN

RTS

DTR

0

0

0

0

0

Description
Mode Select – MDSL2-0
These bits select the operation mode of the functional block when in Extended mode. When the mode is
changed, the TX_FIFO and RX_FIFOs are flushed, Link Status and Modem Status Interrupts are cleared,
and all of the bits in the auxiliary status and control register are cleared.

Bits
7 6
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
4

5
0
1
0
1
0
1
0
1

Operation Mode
UART (Default)
Reserved
Sharp-IR
SIR
MIR
FIR
CEIR
Reserved

Infrared Interaction Pulse – IR_PLS
This bit is effective only in MIR and FIR modes. It is set to 1 by writing 1 into it. Writing 0 into it has no effect.
When set to 1, a 2 ms infrared interaction pulse is transmitted at the end of the frame and the bit is
automatically cleared by the hardware.This bit is also cleared when the transmitter is soft reset. The
interaction pulse must be emitted at least once every 500 ms, as long as the high-speed connection lasts,
in order to quiet slower (115.2 kbps or below) systems that might otherwise interfere with the link.

3

Transmit Deferral – TX_DFR
For a detailed description of the transmit deferral see ‘Transmit Deferral’ on 352. This bit is effective only if
the TX_FIFOs is enabled.

0: No transmit deferral enabled (default)
1: Transmit deferral enabled.
2

DMA Enable – DMA_EN
When set to1, DMA mode of operation is enabled. When DMA is selected, transmit and/or receive interrupts
should be disabled to avoid spurious interrupts. DMA cycles always address the Data Holding registers or
FIFOs, regardless of the selected bank.

0: DMA mode disabled (default)
1: DMA mode enabled
1

Request To Send – RTS
This bit controls the RTS signal output. When set to1, RTS is driven low. When loopback is enabled, this bit
internally drives both CTS and DCD

0

Data Terminal Ready – DTR
This bit controls the DTR signal output. When set to 1, DTR is driven low. When loopback is enabled, this
bit internally drives both DSR and RI.

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Link Status Register (LSR)

register was read). They are cleared when
one of the following events occur:

This register provides status information
concerning data transfer.Upon reset, this
register assumes the value of 0x60h. The bit
definitions change depending upon the operation mode of the functional block.

• Hardware reset
• Receiver soft reset
• LSR register read

Bits 1 through 4 of the LSR indicate link status
events. These bits are sticky (accumulate any
conditions occurred since the last time the

The LSR is intended for read operations only.
Writing to the LSR is not permitted.

Location: Offset 05h
Type:
RO
Bit
Mnemonic
Reset

7

6

5

4

ER_INF/
FR_END

TXEMP

TXRDY

BRK/
MAX_LEN

0

1

1

0

Bit
7

3

2

FE/
PE/
PHY_ERR BAD_CRC
0

0

1

0

OE

RXDA

0

0

Description
Error in RX_FIFO – ER_INF/ FR_END
In UART, Sharp-IR and SIR modes, this bit is set to 1 if there is at least one framing error, parity error or
break indication in the RX_FIFO. This bit is always 0 in 16450 mode. It is cleared upon read or upon reset,
if there is no faulted byte in RX_FIFO.
Frame End – FR_END
In MIR and FIR modes, set to 1 when the last byte (Frame End Byte) of a received frame reaches the
bottom of the RX_FIFO. Cleared upon read.

6

Transmitter Empty – TXEMP
This bit is set to 1 when the Transmitter Holding register or the TX_FIFO is empty, and the transmitter front
end is idle.

5

Transmitter Ready – TXRDY
This bit is set to 1 when the Transmitter Holding register or the TX_FIFO is empty. It is cleared when a data
character is written to the TXD register.

4

Break Event Detected – BRK
In UART, Sharp-IR and SIR modes, this bit is set to 1 when a break event is detected (that is, when a
sequence of logic 0 bits, equal or longer than a full character transmission, is received). If the FIFOs are
enabled, the break condition is associated with the particular character in the RX_FIFO to which it applies.
In this case, the BRK bit is set when the character reaches the bottom of the RX_FIFO. When a break event
occurs, only one 0 character is transferred to the Receiver Holding register or to the RX_FIFO. The next
character transfer takes place after at least one logic 1 bit is received followed by a valid start bit. This bit is
cleared upon read.
Maximum Length – MAX_LEN
In MIR and FIR modes, set to 1 when a frame exceeding the maximum length is received, and the last byte
of the frame has reached the bottom of the RX_FIFO. Cleared upon read.

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Bit
3

Description
Framing Error – FE
In UART, Sharp-IR and SIR modes, this bit is set to 1 when the received data character does not have a
valid stop bit (that is, the stop bit following the last data bit or parity bit is a 0). If the FIFOs are enabled, this
Framing Error is associated with the particular character in the FIFO that it applies to. This error is revealed
to the CPU when its associated character is at the bottom of the RX_FIFO. After a framing error is detected,
the receiver will try to resynchronize. If the bit following the erroneous stop bit is 0, the receiver assumes it
to be a valid start bit and shifts in the new character. If that bit is a 1, the receiver enters the idle state and
awaits the next start bit. This bit is cleared upon read.
Physical Layer Error – PHY_ERR
In MIR and FIR modes, set to 1 when an abort condition is detected during the reception of a frame, and
the last byte of the frame has reached the bottom of the RX_FIFO. Cleared upon read.

2

Parity Error – PE
In UART, Sharp-IR and SIR modes, this bit is set to 1 if the received data character does not have the
correct parity, even or odd as selected by the parity control bits of the LCR register. If the FIFOs are
enabled, this error is associated with the particular character in the FIFO that it applies to. This error is
revealed to the CPU when its associated character is at the bottom of the RX_FIFO. This bit is cleared upon
read.
CRC Error – BAD_CRC
In MIR and FIR modes, set to 1 when a mismatch between the received CRC and the receiver-generated
CRC is detected, and the last byte of the received frame has reached the bottom of the RX_FIFO. Cleared
upon read.

1

Overrun Error – OE
In UART, Sharp-IR and SIR modes, set to 1 as soon as an overrun condition is detected by the receiver.
Cleared upon read.
FIFOs Disabled:
An overrun occurs when a new character is completely received into the receiver front end section and the
CPU has not yet read the previous character in the receiver holding register. The new character is
discarded, and the receiver holding register is not affected.
FIFOs Enabled:
An overrun occurs when a new character is completely received into the receiver front end section and the
RX_FIFO is full. The new character is discarded, and the RX_FIFO is not affected.
Overrun Error – OE
In MIR and FIR modes, an overrun occurs when a new character is completely received into the receiver
front end section and the RX_FIFO or the ST_FIFO is full. The new character is discarded, and the
RX_FIFO is not affected. Cleared upon read.

0

Receiver Data Available – RXDA
Set to 1 when the Receiver Holding register is full. If the FIFOs are enabled, this bit is set when at least one
character is in the RX_FIFO. It is cleared when the CPU reads all the data in the Holding register or in the
RX_FIFO.

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Modem Status Register (MSR)

3-0 in MCR (‘Modem/Mode Control Register
(MCR)’ on 366) and to the LOOP & ETDLBK
bits at the EXCR1 (‘Extended Control Register
1 (EXCR1)’ on 375) for more information.
A Modem Status Event (MS_EV) is generated
if the MS_IE bit in IER is enabled and any of
the bits 0, 1, 2 or 3 in this register is set to 1.
Bits 0 to 3 are set to 0 as a result of any of the
following events:
• A hardware reset occurs.
• The operational mode is changed and the
IRMSSL bit is 0.
• The MSR register is read.
In the reset state, bits 4 through 7 are indeterminate as they reflect their corresponding
input signals.
Note: The modem status lines can be used as
general purpose inputs. They have no effect
on the transmitter or receiver operation

The function of this register depends on the
selected operational mode. When a UART
mode is selected, this register provides the
current-state as well as state-change information of the status lines from the modem or data
transmission module.
When any of the IR modes is selected, the
register function is controlled by the setting of
the IRMSSL bit of the IRCR2 (‘IR Control
Register 2 (IRCR2)’ on 385). If IRMSSL is 0,
the MSR register works as in UART mode. If
IRMSSL is 1, the MSR register returns the
value 30 hex, regardless of the state of the
modem input lines.
When loopback is enabled, the MSR register
works similarly except that its status input
signals are internally driven by appropriate bits
in the MCR register since the modem input
lines are internally disconnected. Refer to bits
Location: Offset 06h
Type:
RO
Bit
Mnemonic
Reset

7

6

5

4

3

2

1

0

DCD

RI

DSR

CTS

DDCD

TERI

DDSR

DCTS

X

X

X

X

0

0

0

0

Bit
7

Description
Data Carrier Detect – DCD
This bit returns the inverse of the DCD input signal.

6

Ring Indicate – RI

5

Data Set Ready – DSR

This bit returns the inverse of the RI input signal.
This bit returns the inverse of the DSR input signal.
4

Clear To Send – CTS
This bit returns the inverse of the CTS input signal.

3

Delta Data Carrier Detect – DDCD
Set to 1, when the DCD input signal changes state. 1: DCD signal state changed.

2

Trailing Edge Ring Indicate – TERI
Set to 1, when the RI input signal changes state from low to high. This bit is cleared upon read.

1

Delta Data Set Ready – DDSR
Set to 1, when the DSR input signal changes state. This bit is cleared upon read.

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Bit
0

Description
Delta Clear to Send – DCTS
Set to 1, when the CTS input signal changes state. This bit is cleared upon read.

SPR Register, Non-Extended Mode

This register is accessed when the Extended
mode of operation is selected. The definition
of the bits in this case is dependent upon the
mode selected in the MCR register, bits 7
through 5. This register is cleared upon hardware reset Bit 2 is cleared also when the
transmitter is “soft reset” or after S-EOT byte is
transmitted. Bit 6 is cleared also when the
transmitter is “soft reset” or by writing 1 into it.
Bits 0,1,4 and 5 are cleared also when the
receiver is “soft reset”.

The SPR shares the same address as ASCR
(see ‘ASCR Register, Extended Mode’ on
371).
In Non-Extended mode, this is a Scratchpad
register (as in the 16550) for temporary data
storage.

ASCR Register, Extended Mode
The ASCR shares the same address as SPR
(see ‘SPR Register, Non-Extended Mode’ on
371).
Location: Offset 07h
Type:
Varies per bit
Bit
Mnemonic
Reset

7

6

5

4

3

2

CTE

TXUR

RXACT/
RXBSY

RXWDG/
LOST_FR

TXHFE

S_OET

0

0

0

0

0

0

Bit
7

1

0

FEND_INF RXF_TOUT
0

0

Description
Clear Timer Event – CTE
In SIR, MIR and FIR modes, writing 1 to this bit position clears the TMR_EV bit of the EIR register. Writing
0 has no effect.

6

IR Transmitter Underrun – TXUR
In MIR, FIR and CEIR, this is the Transmitter Underrun flag. This bit is set to 1 when a transmitter underrun
occurs. It is always cleared when a mode other than CEIR is selected. This bit must be cleared, by writing
1 into it, to re-enable transmission.

5

Receiver Active – RXACT
In CEIR, set to 1 when an IR pulse or pulse-train is received. If a 1 is written into this bit position, the bit is
cleared and the receiver is deactivated. When this bit is set, the receiver samples the IR input continuously
at the programmed baud and transfers the data to the RX_FIFO.
Receiver Busy – RXBSY
In MIR and FIR, this bit is read only, and returns a 1 when reception of a frame is in progress.

4

Reception WATCHDOG – RXWDG
In CEIR, set to 1 each time a pulse or pulse-train (modulated pulse) is detected by the receiver. It can be
used by the software to detect a receiver idle condition. Cleared upon read.
Lost Frame Flag – LOST_FR
In MIR and FIR, this bit is read only, and reflects the setting of the lost-frame indicator flag at the bottom of
the ST_FIFO.

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Bit

Description

3

Transmitter Halted on Frame End – TXHFE
In MIR and FIR, this bit is used only when the transmitter frame-end stop mode is selected (TX_MS bit in
IRCR2 set to 1). It is set to 1 by the hardware when transmission of a frame is complete and the end-offrame condition was generated by the TFRCC counter reaching 0. This bit must be cleared, by writing 1 into
it, to re-enable transmission.

2

Set End of Transmission – S_OET
In CEIR, when a 1 is written into this bit position before writing the last character into the TX_FIFO, data
transmission is properly completed. In this mode, if the CPU simply stops writing data into the TX_FIFO at
the end of the data stream, a transmitter underrun is generated and the transmitter stops. In this case this
is not an error, but the software must clear the underrun before the next transmission can occur. This bit is
automatically cleared by hardware when a character is written to the TX_FIFO.
Set End of Frame – S_OET
In MIR and FIR, when a 1 is written into this bit position before writing the last character into the TX_FIFO,
frame transmission is completed and a CRC + EOF is sent. This bit can be used as an alternative to the
Transmitter Frame Length register. If this method is to be used, the FEND_MD bit of the IRCR2 register
should be set to 1, or the Transmitter Frame Length register should be set to maximum count.

1

Transmitter Halted on Frame End – FEND_INF
In MIR and FIR, this bit is read only, and is set to 1 when one or more Frame End bytes are in the
RX_FIFO. Cleared when no Frame End byte is in the RX_FIFO.

0

RX_FIFO Timeout – RXF_TOUT
This bit is read only and set to 1 when an RX_FIFO timeout occurs. It is cleared when a character is read
from the RX_FIFO.

Table 4.170 Bank 0 Bitmap
Register

Bits

Offset

Mnemonic

7

6

5

4

3

2

1

0

00h

RXD

RXD7

RXD6

RXD5

RXD4

RXD3

RXD2

RXD1

RXD0

00h

TXD

TXD7

TXD6

TXD5

TXD4

TXD3

TXD2

TXD1

TXD0

01h

a

MS_IE

LS_IE

TXLDL_IE

RXHDL_IE

MS_IE

LS_IE

TXLDL_IE

RXHDL_IE

IER

IERb
02h

Reserved
TMR_IE

FEN1, 0

EIRa
EIRb

TMR_EV

FCR
03h
04h

SFIF_IE

BKSE

BSR

BKSE

DMA_IE

Reserved

SFIF_EV

RXFTH1, 0

LCR

TXEMP_IE/
PLD_IE

SBRK

TXEMP_EV/
PLD_EV

DMA_EV

TXFTH1, 0
STKP

EPS

RXFT

IPR1, 0

IPF

MS_EV

LS_EV/
TXLDL_EV
TXHLT_EV

RXHDL_IE

Reserved

TXSR

RXSR

FIFO_EN

PEN

STB

WLS1

WLS0

BSR6-0

MCRa

Reserved

LOOP

ISEN or
DCDLP

RILP

RTS

DTR

MCRb

MDSL2-0

IR_PLS

TX_DFR

DMA_EN

RTS

DTR

05h

LSR

ER_INF/
FR_END

TXEMP

TXRDY

BRK/
MAX_LEN

FE/
PHY_ERR

PE/
BAD_CRC

OE

RXDA

06h

MSR

DCD

RI

DSR

CTS

DDCD

TERI

DDSR

DCTS

07h

a

S_OET

FEND_INF

RXF_TOU
T

Scratch Data

SPR

ASCRb

CTE/PLD

TXUR

RXACT/
RXBSY

RXWDG/
LOST_FR

TXHFE

a. Non-Extended mode
b. Extended mode

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BANK 1
Table 4.171 Bank 1 Register Map
Offset

Mnemonic

Register Name

Type

Reference
page 373

00h

LBGD(L) Legacy Baud Generator Divisor Port (Low Byte)

R/W

01h

LBGD(H) Legacy Baud Generator Divisor Port (High Byte)

R/W

02h
03h

Reserved
LCR/BSR

Link Control/Bank Select

04h - 07h

Legacy Baud Generator Divisor Ports
LSB (LBGD(L)) and MSB (LBGD(H))
The Legacy Baud Generator Divisor (LBGD)
port provides an alternate data path to the
Baud Divisor Generator register. This port is
implemented to maintain compatibility with
16550 standard and to support existing legacy
software packages. In case of using legacy
software, the addresses 0 and 1 are shared
with the data ports RXD/TXD (see ‘Receiver
Data Port (RXD) or the Transmitter Data Port
(TXD)’ on 356). The selection between them is
controlled by the value of the BKSE bit (see
‘Link Control Register (LCR) and Bank Select
Register (BSR)’ on 363, LCR bit 7). See ‘Automatic Fallback to 16550 Compatibility Mode’
on 353 for more information regarding the fallback mechanism.
The programmable baud rates in the NonExtended mode are achieved by dividing a 24
MHz clock by a prescale value of 13, 1.625 or
1. This prescale value is selected by the
PRESL field of EXCR2 (‘Extended Control and
Status Register 2 (EXCR2)’ on 378). This
clock is subdivided by the two Baud Generator
Divisor buffers, which output a clock at 16
times the desired baud (this clock is the BOUT
clock). This clock is used by I/O circuitry, and
after a last division by 16 produces the output
baud.

R/W

Reserved

Generator counter is immediately loaded.
Table 4.173 shows typical baud divisors. After
reset the divisor register contents are indeterminate.
Any access to the LBGD(L) or LBGD(H) ports
causes a reset to the default Non-Extended
mode, that is, 16550 mode (‘Automatic Fallback to 16550 Compatibility Mode’ on 353). To
access a Baud Generator Divisor when in
Extended mode, use the port pair in bank 2
(see ‘Baud Generator Divisor Ports, LSB
(BGD(L)) and MSB (BGD(H))’ on 375).
Table 4.172 shows the bits which are cleared
when fallback occurs during Extended or NonExtended modes. If the UART is in NonExtended mode and the LOCK bit is 1, the
content of the divisor (BGD) ports will not be
affected and no other action is taken. When
programming the baud, the new divisor is
loaded upon writing into LBGD(L) and
LBGD(H). After reset, the contents of these
registers are indeterminate. Divisor values
between 1 and 216-1 can be used (zero is
forbidden). Table 4.173 shows typical baud
divisors.

Divisor values between 1 and 216-1 can be
used (zero is forbidden). The Baud Generator
Divisor must be loaded during initialization to
ensure proper operation of the Baud Generator. Upon loading either part of it, the Baud

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Table 4.172 Bits Cleared on Fallback
Register
Mnemonic

UART Mode and LOCK Bit before Fallback
Extended Mode LOCK = x Non-Extended Mode LOCK = 0 Non-Extended Mode LOCK = 1

MCR

2 to 7

None

None

EXCR1

0, 5 and 7

5 and 7

None

EXCR2

0 to 5

0 to 5

None

Table 4.173 Baud Generator Divisor Settings
Prescaler Value

13

1.625

1

Baud

Divisor

% Error

Divisor

% Error

Divisor

% Error

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
14400
19200
28800
38400
57600
115200
230400
460800
750000
921600
1500000

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
8
6
4
3
2
1
-----------

0.16%
0.16%
0.19%
0.10%
0.16%
0.16%
0.16%
0.16%
0.16%
0.53%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
-----------

18461
12307
8391
6863
6153
3076
1538
769
512
461
384
256
192
128
96
64
48
32
24
16
8
4
2
--1
---

0.00%
0.01%
0.01%
0.00%
0.01%
0.03%
0.03%
0.03%
0.16%
0.12%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
--0.16%
---

30000
20000
13636
11150
10000
5000
2500
1250
833
750
625
416
312
208
156
104
78
52
39
26
13
----2
--1

0.00%
0.00%
0.00%
0.02%
0.00%
0.00%
0.00%
0.00%
0.04%
0.00%
0.00%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
----0.00%
--0.00%

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Link Control Register (LCR) and Bank Select Register (BSR)
These registers are the same as the registers
at offset 03h in bank 0.
Table 4.174 Bank 1 Bitmap
Register

Bits

Offset

Mnemonic

00h

LBGD(L)

LBGD7-0

01h

LBGD(H)

LBGD15-8

7

6

5

4

3

2

1

0

PEN

STB

WLS1

WLS0

Register Name

Type

Section

02h
03h

Reserved
LCR

BKSE

BSR

BKSE

SBRK

STKP

EPS

BSR6-0

04-07h

Reserved

BANK 2
Table 4.175 Bank 2 Register Map
Offset

Mnemonic

00h

BGD(L)

Baud Generator Divisor Port (Low Byte)

R/W

01h

BGD(H)

Baud Generator Divisor Port (High Byte)

R/W

02h

EXCR1

Extended Control1

R/W

03h

BSR

Bank Select

R/W

04h

EXCR2

Extended Control 2

R/W

06h

TXFLV

TX_FIFO Level

RO

07h

RXFLV

RX_FIFO Level

RO

05h

Reserved

Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H))
These ports perform the same function as the
Legacy Baud Divisor Ports in Bank 1 and are
accessed identically, but do not change the
operation mode of the functional block when
accessed. See ‘Legacy Baud Generator
Divisor Ports LSB (LBGD(L)) and MSB
(LBGD(H))’ on 373 for more details.

writing to BGDH causes the baud to change
immediately.

Extended Control Register 1 (EXCR1)
Use this register to control operation in the
Extended mode. Upon reset all bits are set
to 0

Use these ports to set the baud when operating in Extended mode to avoid fallback to a
Non-Extended operation mode, that is, 16550
compatible. When programming the baud,

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Location: Offset 02h
Type:
R/W
Bits
Mnemonic
Reset

7

6

5

4

3

2

1

0

BTEST

Reserved

EDTLBK

LOOP

DMASWP

DMATH

DMANF

EXT_SL

0

1

0

0

0

0

0

0

0

0

0

Required

1

Bit
7

Description
Baud Generator Test – BTEST
When set, this bit routes the Baud Generator output to the DTR pin for testing purposes.

6

Reserved. Write 1.

5

Enable Transmitter During Loopback – EDTLBK
When this bit is set to 1, the transmitter serial output is enabled and functions normally when loopback is
enabled

4

Loopback Enable – LOOP
During loopback, the transmitter output is connected internally to the receiver input, to enable system selftest of serial communications. In addition to the data signal, all additional signals within the UART are
interconnected to enable real transmission and reception using the UART mechanisms. When this bit is set
to 1, loopback is selected. This bit accesses the same internal register as bit 4 in the MCR register, when
the UART is in a Non-Extended mode. Loopback behaves similarly in both Non-Extended and Extended
modes. When Extended mode is selected, the DTR bit of the MCR register internally drives both DSR and
RI, and the RTS bit drives CTS and DCD.
During loopback, the following actions occur:
— The transmitter and receiver interrupts are fully operational. The Modem Status Interrupts are also fully
operational, but the interrupt sources are now the lower bits of the MCR register. Modem interrupts in IR
modes are disabled unless the IRMSSL bit of the IRCR2 register is 0. Individual interrupts are still controlled by the IER register bits.
— The DMA control signals are fully operational.
— UART and IR receiver serial input signals are disconnected. The internal receiver input signals are connected to the corresponding internal transmitter output signals.
— The UART transmitter serial output is forced high and the IR transmitter serial output is forced low, unless
the ETDLBK bit is set to 1 in which case they function normally.
— The modem status input pins (DSR, CTS, RI and DCD) are disconnected. The internal modem status
signals are driven by the lower bits of the MCR register.

3

DMA Swap – DMASWP
This bit selects the routing of the DMA control signals between the internal DMA logic and the configuration
module of the chip. When this bit is 0, the transmitter and receiver DMA control signals are not swapped.
When it is 1, they are swapped. A block diagram illustrating the control signals routing is given in Figure 419. The swap feature is particularly useful when only one 8237 DMA channel is used to serve both
transmitter and receiver. In this case only one external DMA Request/DMA Acknowledge pair will be
interconnected to the swap logic by the configuration module. Routing the external DMA channel to either the
transmitter or the receiver DMA logic is then simply controlled by the DMASWP bit. This way, the IR device
drivers do not need to know the details of the configuration module.

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Bit
2

Description
DMA FIFO Threshold – DMATH
This bit selects the TX_FIFO and RX_FIFO threshold levels used by the DMA request logic to support
demand transfer mode. A transmission DMA request is generated when the TX_FIFO level is below the
threshold. A reception DMA request is generated when the RX_FIFO level reaches the threshold or when a
DMA timeout occurs. Table 4.176 lists the threshold levels for each FIFO.

1

DMA Fairness Control – DMANF
This bit controls the maximum duration of DMA burst transfers.
0 = DMA requests forced inactive after approximately 10.5 msec of continuous transmitter and/or receiver
DMA operation (default)
1 = TX-DMA request deactivated when the TX_FIFO is full. An RX DMA request is deactivated when the
RX_FIFO is empty.

0

Extended Mode Select – EXT_SL
When set to 1, Extended mode is selected.

Table 4.176 DMA Threshold Levels
DMA Threshold for FIFO Type
Bit
Value

TX_FIFO
RX_FIFO
16 Levels

32 Levels

0

4

13

29

1

10

7

23

.
DMA Swap Logic
RX-Channel
DMA Logic

Configuration Module

RX_DMA
Routing
Logic
Routing
Logic

TX-Channel
DMA Logic

DMA Handshake
Signals

TX_DMA

DMASWP

Figure 4-19 DMA Control Signals Routing

Bank Select Register (BSR)
These register is the same as the BSR register
at offset 03h in bank 0.

ZFx86 Data Book 1.0 Rev D

Page 377

4
Extended Control and Status Register 2 (EXCR2)
This register configures the RX_FIFO and
TX_FIFO sizes and the value of the Prescaler

and controls the Baud Divisor register Lock.
Upon reset all bits are set to 0.

Location: Offset 04h
Type:
R/W
Bit
Mnemonic

7

6

LOCK

Reserved

0

0

Reset

5

3

0

0

PRESL1, 0
0

Bit
7

4

2

1

0

0

RF_SIZ1, 0

0
TF_SIZ1, 0
0

Description
Baud Divisor Register Lock – LOCK
When set to 1, accesses to the Baud Generator Divisor register through LBGD(L) and LBGD(H) as well as
fallback are disabled from non-extended mode. In this case two scratchpad registers overlaid with LBGD(L)
and LBGD(H) are enabled, and any attempted CPU access of the Baud Generator Divisor register through
LBGD(L) and LBGD(H) will access the ScratchPad registers instead. This bit must be set to 0 when
extended mode is selected.

6
5-4

Reserved
Prescaler Select – PRESL1, 0
The prescaler divides the 24 MHz input clock frequency to provide the clock for the Baud Generator.

3-2

Bits
5 4

Prescaler Value

0
0
1
1

13 (Default)
1.625
Reserved
1.0

0
1
0
1

RX_FIFO Levels Select – RF_SIZ 1, 0
These bits select the number of levels for the RX_FIFO. They are effective only when the FIFOs are
enabled.

1-0

Bits
3 2

RX_FIFO Levels

0 0
0 1
1 X

16 (Default)
32
Reserved

TX_FIFO Levels Select – TF_SIZ1, 0
These bits select the number of levels for the TX_FIFO. They are effective only when the FIFOs are
enabled.

Bits
3 2

TX_FIFO Levels

0 0
0 1
1 X

16 (Default)
32
Reserved

Reserved Register
Upon reset, all bits in bank 2 register with
offset 05h are set to 0.

ZFx86 Data Book 1.0 Rev D

Page 378

4
TX_FIFO Current Level Register (TXFLV)
This register returns the number of bytes in
the TX_FIFO. It can be used to facilitate
programmed I/O modes during recovery from

transmitter underrun in one of the fast IR
modes.

Location: Offset 06h
Type:
RO
Bit

7

Mnemonic
Reset

6

5

4

3

Reserved
0

2

1

0

0

0

0

TFL5-0
0

0

Bit

0

0

Description

7-6

Reserved

5-0

Number of Bytes in TX_FIFO – TFL5-0
These bits specify the number of bytes in the TX_FIFO.
Note: The contents of TXFLV and RXFLV are not frozen during CPU reads. Therefore, invalid data could be
returned if the CPU reads these registers during normal transmitter and receiver operation. To obtain correct
data, the software should perform three consecutive reads and then take the data from the second read, if
first and second read yield the same result, or from the third read, if first and second read yield different
results.

RX_FIFO Current Level Register (RXFLV)
This register returns the number of bytes in
the RX_FIFO. It can be used for software
debugging.
Location: Offset 07
Type:
RO
Bit

7

Mnemonic
Reset

6

5

4

3

0

0

0

0

Reserved
0

2

1

0

0

0

0

RFL5-0

Bit

Description

7-6

Reserved

5-0

Number of Bytes in RX_FIFO – RFL5-0
These bits specify the number of bytes in the RX_FIFO.
Note: The contents of TXFLV and RXFLV are not frozen during CPU reads. Therefore, invalid data could be
returned if the CPU reads these registers during normal transmitter and receiver operation. To obtain correct
data, the software should perform three consecutive reads and then take the data from the second read, if
first and second read yield the same result, or from the third read, if first and second read yield different
results.

ZFx86 Data Book 1.0 Rev D

Page 379

4
Table 4.177 Bank 2 Bitmap
Register

Bits

Offset

Mnemonic

00h

BGD(L)

BGD7-0

01h

BGD(H)

BGD15-8

02h

EXCR1

BTEST

03h

BSR

BKSE

04h

EXCR2

LOCK

7

6

5

Reserved

4

EDTLBK

LOOP

3

2

1

0

DMASWP

DMATH

DMANF

EXT_SL

BSR6-0
Reserved

PRESL1, 0

05h

RF_SIZ1, 0

TF_SIZ1, 0

Reserved

06h

TXFLV

Reserved

TFL5-0

07h

RXFLV

Reserved

RFL5-0

BANK 3
Table 4.178 Bank 3 Register Map
Offset

Mnemonic

Register Name

Type

00h

MRID

Module Identification and Revision ID

RO

01h

SH_LCR

Shadow of LCR

RO

02h

SH_FCR

Shadow of FIFO Control

RO

03h

BSR

Bank Select

R/W

04h-07h

Section

Reserved

Module Identification and Revision ID Register (MRID)
This register identifies the revision of the
module. When read, it returns the module ID

and revision level in the format 2xh, where x
indicates the revision number.

Location: Offset 00h
Type:
RO
Bit

7

6

Mnemonic
Reset

4

3

2

MID3-0
0

Bit
7-4

5

0

1

0

X

X

RID3-0
1

0

X

X

Description
Module ID – MID3-0
The value in these bits identifies the module type.

3-0

Revision ID – RID3-0
The value in these bits identifies the revision level.

ZFx86 Data Book 1.0 Rev D

Page 380

4
Shadow of Link Control Register (SH_LCR)
This register returns the value of the LCR
register. The LCR register is written into when
a byte value, according to bits 1,0 of the LCR
register in ‘Link Control Register (LCR) and

Bank Select Register (BSR)’ on 363, is written
to the LCR/BSR registers location (at offset
03h) from any bank.

Location: Offset 01h
Type:
RO
Bit
Mnemonic

7

6

5

4

3

2

1

0

Reserved

SBRK

STKP

EPS

PEN

STB

WLS1

WLS0

0

0

0

0

0

0

0

0

3

2

1

0

Reserved

TXSR

RXSR

FIFO_EN

0

0

0

0

Reset

See ‘Link Control Register (LCR) and Bank Select Register (BSR)’ on 363 for bit descriptions.

Shadow of FIFO Control Register (SH_FCR)
This register returns the contents of the FCR
register in bank 0
Location: Offset 02h
Type:
RO
Bit

7

Mnemonic

6

5

RXFTH1, 0

Reset

0

4
TXFTH1, 0

0

0

0

Bank Select Register (BSR)
This register is the same as the BSR register at
offset 03h in bank 0.

Reserved Registers
Bank 3 registers with offsets 04h to 07h are reserved.

Table 4.179 Bank 3 Bitmap
Register
Offset

Mnemonic

00h

MRID

01h

SH_LCR

02h

SH_FCR

03h

BSR

Bits
7

6

5

4

3

2

MID3-0
Reserved

SBRK

RXFTH1, 0

ZFx86 Data Book 1.0 Rev D

0

RID3-0

STKP

EPS

TXFTH1, 0

BKSE

04h-07h

1

PEN

STB

WLS1

WLS0

Reserved

TXSR

RXSR

FIFO_EN

BSR6-0
Reserved

Page 381

4
BANK 4
Table 4.180 Bank 4 Register Map
Offset

Mnemonic

Register Name

Type

Page
page 382

00h

TMR(L)

Timer (Low Byte)

RO

01h

TMR(H)

Timer (High Byte)

RO

02h

IRCR1

IR Control 1

page 383

03h

BSR

Bank Select

04h

TFRL(L)/
TFRCC(L)

Transmitter Frame Length (Low Byte)/
Transmitter Frame Current Count (Low Byte)

R/W

05h

TFRL(H)/
TFRCC(H)

Transmitter Frame Length (High Byte)/
Transmitter Frame Current Count (High Byte)

R/W

06h

RFRML(L)/
RFRCC(L)

Receiver Frame Maximum Length (Low Byte)/
Receiver Frame Current Count (Low Byte)

R/W

07h

RFRML(H)/
RFRCC(H)

Receiver Frame Maximum Length (High Byte)/
Receiver Frame Current Count (High Byte)

R/W

Timer Registers (TMR)
The Timer registers at offsets 00h, 01h are
used to program the reload value for the
internal down-counter as well as to read the
current counter value. TMR is 12 bits wide and
is split into two independently accessible parts
occupying consecutive address locations.
TMR(L) is located at the lower address and
accesses the least significant 8 bits, whereas
TMR(H) is located at the higher address and
accesses the most significant 4 bits. Values
from 1 to 212 –1 can be used. The 0value is
reserved and must not be used. The upper 4
bits of TMR(H) are reserved and must be
written with 0's.

ZFx86 Data Book 1.0 Rev D

page 383
page 383

page 384

The timer resolution is 125 ms, providing a
maximum timeout interval of approximately
0.5 seconds. To properly program the timer,
the CPU must always write the lower value
into TMR(L) first, and then the upper value into
TMR(H). Writing into TMR(H) causes the
counter to be loaded. A read of TMR returns
the current counter value if the CTEST bit is 0,
or the programmed reload value if CTEST is 1.
In order for a read access to return an accurate value, the CPU should always read
TMR(L) first, and then TMR(H). This is
because a read of TMR(H) returns the content
of an internal latch that is loaded with the 4
most significant bits of the current counter
value when TMR(L) is read. After reset, the
content of this register is indeterminate.

Page 382

4
IR Control Register 1 (IRCR1)
Enables the Sharp-IR or SIR IR mode in NonExtended mode of operation.
Upon reset, all bits are set to 0.
Location: Offset 02h
Type:
R/W
Bit

7

6

0

0

Mnemonic

5

4

3

0

0

0

Reserved

Reset

2
IR_SL1, 0

Bit

0

1

0

CTEST

TMR_EN

0

0

Description

7-4

Reserved

3-2

Sharp-IR or SIR Mode Select – IR_SL1, 0
Non-Extended mode only. These bits enable Sharp-IR and SIR modes in Non-Extended mode. They allow
selection of the appropriate IR interface when Extended mode is not selected. These bits are ignored when
Extended mode is selected.

Bits

1

1 0

Selected Mode

0
0
1
1

UART (Default)
Reserved
Sharp-IR
SIR

0
1
0
1

Counters Test – CTEST
When this bit is set to 1, the TMR register reload value, as well as the TFRL and RFRML register contents,
are returned during CPU reads.

0

Timer Enable – TMR_EN
Extended mode only. When this bit is 1, the timer is enabled. When it is 0, the timer is frozen.

Bank Select Register (BSR)
These register is the same as the BSR
register at offset 03h in bank 0.

Transmitter Frame Length/Current
Count (TFRL/TFRCC)
These registers share the same addresses.
TFRL is always accessed during write cycles
and is used to program the frame length, in
bytes, for the frames to be transmitted. The
frame length value does not include any
appended CRC bytes. TFRL is accessed
during read cycles if the CTEST bit is set to 1,
and returns the previously programmed value.
Values from 1 to 213 –1 can be used. The
0value is reserved and must not be used.

ZFx86 Data Book 1.0 Rev D

TFRCC is loaded with the content of TFRL
when transmission of a frame begins, and
decrements after each byte is transmitted. It is
read only and is accessed during CPU read
cycles when the CTEST bit is 0. It returns the
number of currently remaining bytes of the
frame being transmitted. These registers are
13 bits wide and are split into two independently accessible parts occupying consecutive
address locations. TFRL(L) and TFRCC(L) are
located at the lower address and access the
least significant 8 bits, whereas TFRL(H) and
TFRCC(H) are located at the higher address
and access the most significant 5 bits. To
properly program TFRL, the CPU must always
write the lower value into TFRL(L) first, and

Page 383

4
then the upper value into TFRL (H). The upper
3 bits of TFRL(H) are reserved and must be
written with 0's. In order for a read access of
TFRCC to return an accurate value, the CPU
should always read TFRCC(L) first, and then
TFRCC(H). After reset, the content of the
TFRL register is 800h.

Receiver Frame Maximum Length/Current Count (RFRML/RFRCC)
These registers share the same addresses.
RFRML is always accessed during write
cycles and is used to program the maximum
frame length, in bytes, for the frames to be
received. The maximum frame length value
includes the CRC bytes. RFRML is accessed
during read cycles if the CTEST bit is set to 1,
and returns the previously programmed value.
Values from 4 to 213 –1 can be used. The
values from 0 to 3 are reserved and must not
be used. RFRCC holds the current byte count
of the incoming frame, and increments after

each byte is received. It is read only and is
accessed during CPU read cycles when the
CTEST bit is 0. These registers are 13 bits
wide and are split into two independently
accessible parts occupying consecutive
address locations. RFRML(L) and RFRCC(L)
are located at the lower address and access
the least significant 8 bits, whereas RFRML(H)
and RFRCC(H) are located at the higher
address and access the most significant 5 bits.
To properly program RFRML, the CPU must
always write the lower value into RFRML(L)
first, and then the upper value into RFRML(H).
The upper 3 bits of RFRML(H) are reserved
and must be written with 0's. In order for a
read access of RFRCC to return an accurate
value, the CPU should always read RFRCC(L)
first, and then RFRCC(H). After reset, the
content of the RFRML register is 800h.
Note: TFRCC and RFRCC are intended for
testing purposes only. Use of these registers
for any other purpose is not recommended.

Table 4.181 Bank 4 Bitmap
Register

Bits

Offset

Mnemonic

00h

TMR(L)

01h

TMR(H)

Reserved

02h

IRCR1

Reserved

03h

BSR

04h

TFRL(L)/
TFRCC(L)

05h

TFRL(H)/
TFRCC(H)

06h

RFRML(L)/
RFRCC(L)

07h

RFRML(H)/
RFRCC(H)

7

6

5

4

3

2

1

0

CTEST

TMR_EN

TMR7-0

BKSE

ZFx86 Data Book 1.0 Rev D

TMR11-8
IR_SL1,0
BSR6-0
TFRL7-0/TFRCC7-0

Reserved

TFRL12-8/TFRCC12-8
RFRML7-0/RFRCC7-0

Reserved

RFRML12-8/RFRCC12-8

Page 384

4
BANK 5
Table 4.182 Bank 5 Register Map
Offset

Mnemonic

Register Name

Type

Reference

00h

SPR2

Scratchpad 2

R/W

Page 385

01h

SPR3

Scratchpad 3

R/W

02h

Reserved

03h

BSR

Bank Select

R/W

Page 385

04h

IRCR2

IR Control 2

R/W

Page 385

05h

FRM_ST

Frame Status

RO

06h

RFRL(L)/LSTFRC

Received Frame Length (Low Byte) / Lost Frame Count

RO

07h

RFRL(H)

Received Frame Length (High Byte)

RO

Scratchpad Registers
Reserved Register

These registers are to be used by the
programmer to contain data temporarily. They
have no control over the device operation. The
reset value of SPR2 is 01h; the reset value of
SPR3 is 00h.

Bank 5 register with offset 02h is reserved.

Bank Select Register (BSR)
This register is the same as the BSR register
at offset 03h in bank 0.

IR Control Register 2 (IRCR2)
This register controls the basic settings of the
IR modes. Upon reset, the content of this
register is 02h
Location: Offset 04h
Type:
R/W
Bit
Mnemonic

7

6

Reserved

SFTSL

0

0

Reset

5

4

FEND_MD AUX_IRRX
0

Bit

3

2

1

0

TX_MS

MDRS

IRMSSL

IR_FDPLX

0

0

1

0

0
Description

7

Reserved

6

ST_FIFO Threshold Select – SFTSL
An interrupt request is generated when the ST_FIFO level reaches the threshold or when an ST_FIFO
timeout occurs.

0: Threshold level 2 (default)
1: Threshold level 4
5

Frame End Control – FEND_MD
This bit selects whether a terminal-count condition from the TFRCC register generates an EOF in PIO mode
or DMA mode.

0: TFRCC terminal count effective in PIO mode (default)
1: TFRCC terminal count effective in DMA mode

ZFx86 Data Book 1.0 Rev D

Page 385

4
Bit
4

Description
Auxiliary IR Input Select – AUX_IRRX
When set to 1, the IR signal is received from the auxiliary input. (Separate input signals may be desired for
different front end circuits). See Table 4.195.

3

Transmitter Mode Select – TX_MS
This bit is used in MIR and FIR modes only. When it is set to 1, transmitter frame-end stop mode is selected.
In this case the transmitter stops after transmission of a frame is complete, if the end-of-frame condition was
generated by the TFRCC counter reaching 0. The transmitter can be restarted by clearing the TXHFE bit of
the ASCR register.

2

MIR Data Rate Select – MDRS
This bit determines the data rate in MIR mode.
0 = 1.152 Mbps
1 = 0.576 Mbps

1

MSR Register Function Select in IR Mode – IRMSSL
This bit selects the behavior of the Modem Status register (MSR) and the Modem Status Interrupt (MS_EV)
when any IR mode is selected. When a UART mode is selected, the Modem Status register and the Modem
Status Interrupt function normally, and this bit is ignored.
0 = MSR register and modem status interrupt work in the IR modes as in the UART mode (Enables external
circuitry to perform carrier detection and provide wake-up events).
1 = MSR register returns 30h, and Modem Status Interrupt disabled (default)

0

Enable IR Full Duplex Mode – IR_FDPLX
When set to 1, the IR receiver is not masked during transmission.

The Status FIFO
The ST_FIFO is used in MIR and FIR Modes.
It is an 8-level FIFO and is intended to support
back-to-back incoming frames in DMA mode,
when an 8237-type DMA controller is used.
Each ST_FIFO entry contains either status
information and frame length for a single
frame, or the number of lost frames.
The bottom entry spans three address locations, and is accessed via the FRMST,
RFRL(L)/LSTFRC and RFRL(H) registers.
The ST_FIFO is flushed when a hardware
reset occurs or when the receiver is soft reset.

ZFx86 Data Book 1.0 Rev D

Note: The status and length information of
received frames is loaded into the ST_FIFO
whenever the DMA_EN bit of the extendedmode MCR register is set to 1 and an 8237
type DMA controller is used, regardless of
whether the CPU or the DMA controller is
transferring the data from the RX_FIFO to
memory. This implies that, during testing, if full
duplex is enabled and a DMA channel is
servicing the transmitter while the CPU is
servicing the receiver, the CPU must still read
the ST_FIFO. Otherwise, it fills up and
incoming frames will be rejected.

Page 386

4
Frame Status (FRM_ST)
This register returns the status byte at the
bottom of the ST_FIFO. If the LOSTFR bit is 0,
bits 0 to 4 indicate if any error condition

occurred during reception of the corresponding frame. Error conditions also affect
the error flags in the LSR register.

Location: Offset 05h
Type:
RO
Bit
Mnemonic

7

6

5

4

3

2

1

0

VLD

LOST_FR

Reserved

MAX_LEN

PHY_ERR

BAD_CRC

OVR1

OVR2

0

0

0

0

0

0

1

0

Reset
Bit
7

Description
ST_FIFO Entry Valid – VLD
When set to 1, the bottom ST_FIFO entry contains valid data.

6

Lost Frame Flag – LOST_FR
Indicates the type of information provided by this ST_FIFO entry.
0 = Entry provides status information and length for a received frame
1 = Entry provides overrun indications and number of lost frames

5

Reserved

4

Maximum Frame Length Exceeded – MAX_LEN
Set to 1 when a frame exceeding the maximum length has been received.

3

Physical Layer Error – PHY_ERR
Set to 1 when an encoding error or the sequence BOF-data-BOF is detected in FIR mode, or an abort
condition is detected in MIR mode.

2

CRC Error – BAD_CRC
Set to 1 when a mismatch between the received CRC and the receiver-generated CRC is detected.

1

Overrun Error 1 – OVR1
This bit is set to 1 when incoming characters or entire frames have been discarded due to the RX_FIFO
being full.

0

Overrun Error 2 – OVR2
This bit is set to 1 when incoming characters or entire frames have been discarded due to the ST_FIFO
being full.

Received Frame Length Low Byte (RFRL(L)) / Lost Frame Count (LSTFRC)
This read only register should be read only
when the VLD bit in FRM_ST is 1. The information returned depends on the setting of the
LOST_FR bit. Upon reset, all bits are set to 0.

LOST_FR = 0: Least significant 8 bits of the
received frame length.
LOST_FR = 1: Number of lost frames

Received Frame Length High Byte (RFRL(H))
This read only register should be read only
when the VLD bit in FRM_ST is 1. The information returned depends on the setting of the
LOST_FR bit. Upon reset, all bits are set to 0.

ZFx86 Data Book 1.0 Rev D

LOST_FR = 0: Most significant 5 bits of the
received frame length.
LOST_FR = 1: Reading this register removes
the bottom ST_FIFO entry.

Page 387

4
Table 4.183 Bank 5 Bitmap
Register

Bits

Offset

Mnemonic

00h

SPR2

Scratchpad 2

01h

SPR3

Scratchpad 3

7

6

5

02h

4

3

2

1

0

MDRS

IRMSSL

IR_FDPLX

OVR1

OVR2

Reserved

03h

BSR

BKSE

BSR6-0

04h

IRCR2

Reserved

05h

FRM_ST

VLD

06h

RFRL(L)/
LSTFRC

RFRL7-0/LSTFRC7-0

07h

RFRL(H)

RFRL15-8

SFTSL

FEND_MD AUX_IRRX

TX_MS

LOST_FR Reserved MAX_LEN PHY_ERR BAD_CRC

BANK 6
Table 4.184 Bank 6 Register Map
Offset

Mnemonic

Register Name

Type

Page

00h

IRCR3

IR Control 3

R/W

Page 389

01h

MIR_PW

MIR Pulse Width Control

R/W

Page 391

02h

SIR_PW

SIR Pulse Width Control

R/W

Page 391

03h

BSR

Bank Select

R/W

Page 391

04h

BFPL

Beginning Flags/ Preamble Length

R/W

Page 391

05h-07h

ZFx86 Data Book 1.0 Rev D

Reserved

Page 388

4
IR Control Register 3 (IRCR3)
This register is used to select the operating
mode of the infrared interface.
Location: Offset 00h
Type:
R/W.
Bit

7

Mnemonic
Reset

6

SHDM_DS SHMD_DS
0

5

4

3

FIR_CRC

MIR_CRC

Reserved

1

0

0

0

Bit
7

0

TXCRC_INV TXCRC_DS Reserved
0

0

0

Sharp-IR Demodulation Disable – SHDM_DS
Internal 500 KHz receiver demodulation enabled (default)
Internal demodulation disabledþ

Sharp-IR Modulation Disable – SHMD_DS
0=
1=

5

1

Description

0=
1=
6

2

Internal 500 KHz transmitter modulation enabled (default)
Internal modulation disabled

FIR Mode CRC Select – FIR_CRC
Determines the length of the CRC in FIR mode.
0 = 16-bit CRC
1 = 32-bit CRC

4

MIR Mode CRC Select – MIR_CRC
Determines the length of the CRC in MIR mode.
0 = 16-bit CRC
1 = 32-bit CRC

3

Reserved

2

Invert Transmitter CRC – TXCRC_INV
When set to 1, an inverted CRC is transmitted.This bit can be used to force a bad CRC for testing purposes.

1

Disable Transmitter CRC – TXCRC_DS
When set to 1, a CRC is not transmitted.

0

Reserved

ZFx86 Data Book 1.0 Rev D

Page 389

4
MIR Pulse Width Register (MIR_PW)
This register is used to program the width of
the transmitted MIR infrared pulses in increments of either 20.833 ns or 41.666 ns
depending on the setting of the MDSR bit of

the IRCR2 register. The programmed value
has no effect on the MIR receiver. After reset,
the content of this register is 0Ah.

Location: Offset 01h
Type:
R/W
Bit

7

6

Mnemonic
Reset

5

4

3

2

Reserved
0

0

1

0

1

0

MPW3-0
0

Bit

0

1

0

Description

7-4

Reserved

3-0

MIR Pulse Width – MPW 3-0
The settings of the pulse width are given in Table 4.185.

Table 4.185 IMIR Pulse Width Settings
Encoding

Pulse Width
MDRS = 0

Pulse Width
MDRS = 1

00XX
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Reserved
83.33 ns
104.16 ns
125 ns
145.83 ns
166.66 ns
187.50 ns
208.33 ns
229.16 ns
250 ns
270.83 ns
291.66 ns
312.5 ns

Reserved
166.66 ns
208.33 ns
250 ns
291.66 ns
333.33 ns
374.99 ns
416.66 ns
458.33
500 ns
541.66 ns
583.32 ns
625 ns

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4
SIR Pulse Width Register (SIR_PW)
This register sets the pulse width for transmitted pulses in SIR operation mode. These settings do not affect the receiver. Upon reset, the
content of this register is 00h, which defaults to
a pulse width of 3/16 of the baud
Location: Offset 02h
Type:
R/W.
Bit

7

6

Mnemonic
Reset

5

4

3

2

Reserved
0

0

1

0

0

0

SPW3-0
0

Bit

0

0

0

Description

7-4

Reserved

3-0

SIR Pulse Width – SPW 3-0
Two codes for setting the pulse width are available. All other values for this field are reserved.
0000: Pulse width = 3/16 of bit period (default)
1101: Pulse width = 1.6 msec

Bank Select Register (BSR)
These register is the same as the BSR register
at offset 03h in bank 0.

Beginning Flags/Preamble Length Register (BFPL)
Used to program the number of beginning flags
and preamble symbols for MIR and FIR modes
respectively.
After reset, the content of this register is 2Ah,
selecting 2 beginning flags and 16 preamble
symbols.
Location: Offset 04h
Type:
R/W
Bit

7

6

0

0

Mnemonic
Reset

4

3

2

1

0

1

0

MBF7-4

Bit
7-4

5

1

0

1

0

FPL3-0

Description
MIR Beginning Flags– MBF7-4
Selects the number of beginning flags for MIR frames.The settings of the are given in Table 4.186.

3-0

FIR Preamble Length – FPL3-0
Selects the number of preamble symbols for FIR frames.The settings of the are given in Table 4.187.

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Table 4.187 FIR Preamble Length

Table 4.186 MIR Beginning Flags
Encoding

Beginning Flags

Encoding

Preamble Length

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Reserved
1
2 (Default)
3
4
5
6
8
10
12
16
20
24
28
32
Reserved

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Reserved
1
2
3
4
5
6
8
10
12
16 (Default)
20
24
28
32
Reserved

Reserved Registers
Bank 6 registers with offsets 05h-07h are reserved.
Table 4.188 Bank 6 Bitmap
Register

Bits

Offset

Mnemonic

00h

IRCR3

01h

MIR_PW

Reserved

02h

SIR_PW

Reserved

03h

BSR

04h

BFPL

7

6

5

4

3

2

1

0

TXCRC_
INV

TXCRC_
DS

Reserved

MPW3

MPW2

MPW1

MPW0

SPW3

SPW2

SPW1

SPW0

SHDM_DS SHDM_DS FIR_CRC MIR_CRC Reserved

BKSE

05h-07h

ZFx86 Data Book 1.0 Rev D

BSR6-0
MBF7-4

FPL3-0
Reserved

Page 392

4
BANK 7
Table 4.189 Bank 7 Register Map
Offset

Mnemonic

Register Name

Type

00h

IRRXDC

IR Receiver Demodulator Control

R/W

01h

IRTXMC

IR Transmitter Modulator Control

R/W

02h

RCCFG

CEIR Configuration

R/W

03h

BSR

Bank Select

R/W

04h

IRCFG1

IR Interface Configuration 1

Varies per bit

05h

Reserved

06h

Reserved

07h

IRCFG4

IR Interface Configuration 4

Section

R/W

The CEIR utilizes two carrier frequency
ranges (see also Table 4.194):
• Low range which spans from 30 KHz to
56 KHz, in 1 KHz increments, and
• High range which includes three frequencies: 400 KHz, 450 KHz or 480 KHz.
High and low frequencies are specified independently to allow separate transmission and
reception modulation settings. The transmitter
uses the carrier frequency settings in Table
4.194.
The four registers at offsets 04h through 07h
(the IR transceiver configuration registers) are
provided to configure the IR Interface (the
transceiver). The transceiver mode is selected
by up to three special output signals (IRSL20). When programmed as outputs these
signals are forced to low when a UART mode
is selected.

ZFx86 Data Book 1.0 Rev D

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4
IR Receiver Demodulator Control Register (IRRXDC)

mode. The value of this register is ignored in
both modes if the receiver demodulator is
disabled (see bit 4 at ‘CEIR Configuration
Register (RCCFG)’ on 397). The available
frequency ranges for CEIR and Sharp-IR
modes are given in Tables 4.190 through
4.192.

This register controls settings for Sharp-IR
and CEIR reception. After reset, the content of
this register is 29h. This setting selects a
subcarrier frequency in a range between
34.61 KHz and 38.26 KHz for the CEIR mode,
and from 480.0 to 533.3 KHz for the Sharp-IR
Location: Offset 00h
Type:
R/W
Bit

7

6

Mnemonic

5

4

2

DBW2-0

Reset

0

1

0

0

1

DFR4-0

0

1

0

Bit
7-5

3

1

0

Description
Demodulator Bandwidth – DBW2-0
These bits set the demodulator bandwidth for the selected frequency range. The subcarrier signal frequency
must fall within the specified frequency range in order to be accepted. Used for both Sharp-IR and CEIR
modes.

4-0

Demodulator Frequency – DFR4-0
These bits select the subcarrier’s center frequency for the CEIR mode.

Table 4.190 CEIR, Low Speed Demodulator (RXHSC = 0)
DFR
Bits
43210

DBW2-0 Bits (Bits 7-5 of IRRXDC)
001

010

011

100

101

110
Freq.

min

max

min

max

min

max

min

max

min

max

min

max

00011

28.6

31.6

27.3

33.3

26.1

35.3

25.0

37.5

24.0

40.0

23.1

42.9

KHz

00100

29.3

32.4

28.0

34.2

26.7

36.2

25.6

38.4

24.6

41.0

23.7

43.9

KHz

00101

30.1

33.2

28.7

35.1

27.4

37.1

26.3

39.4

25.2

42.1

24.3

45.1

KHz

00110

31.7

35.1

30.3

37.0

29.0

39.2

27.8

41.7

26.7

44.4

25.6

47.6

KHz

00111

32.6

36.0

31.1

38.1

29.8

40.3

28.5

42.8

27.4

45.7

26.3

48.9

KHz

01000

33.6

37.1

32.0

39.2

30.7

41.5

29.4

44.1

28.2

47.0

27.1

50.4

KHz

01001

34.6

38.3

33.0

40.4

31.6

42.8

30.3

45.4

29.1

48.5

28.0

51.9

KHz

01011

35.7

39.5

34.1

41.7

32.6

44.1

31.3

46.9

30.0

50.0

28.8

53.6

KHz

01100

36.9

40.7

35.2

43.0

33.7

45.5

32.3

48.4

31.0

51.6

29.8

55.3

KHz

01101

38.1

42.1

36.4

44.4

34.8

47.1

33.3

50.0

32.0

53.3

30.8

57.1

KHz

01111

39.4

43.6

37.6

45.9

36.0

48.6

34.5

51.7

33.1

55.1

31.8

59.1

KHz

10000

40.8

45.1

39.0

47.6

37.3

50.4

35.7

53.6

34.3

57.1

33.0

61.2

KHz

10010

42.3

46.8

40.4

49.4

38.6

52.3

37.0

55.6

35.6

59.3

34.2

63.5

KHz

10011

44.0

48.6

42.0

51.3

40.1

54.3

38.5

57.7

36.9

61.5

35.5

65.9

KHz

ZFx86 Data Book 1.0 Rev D

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4
Table 4.190 CEIR, Low Speed Demodulator (RXHSC = 0)
DFR
Bits
43210

DBW2-0 Bits (Bits 7-5 of IRRXDC)
001

010

011

100

101

110
Freq.

min

max

min

max

min

max

min

max

min

max

min

max

10101

45.7

50.5

43.6

53.3

41.7

56.5

40.0

60.0

38.4

64.0

36.9

68.6

KHz

10111

47.6

52.6

45.5

55.6

43.5

58.8

41.7

62.5

40.0

66.7

38.5

71.4

KHz

11010

49.7

54.9

47.4

57.9

45.3

61.4

43.5

65.2

41.7

69.5

40.1

74.5

KHz

11011

51.9

57.4

49.5

60.6

47.4

64.1

45.4

68.1

43.6

72.7

41.9

77.9

KHz

11101

54.4

60.1

51.9

63.4

49.7

67.2

47.6

71.4

45.7

76.1

43.9

81.6

KHz

Table 4.191 Consumer IR High Speed Demodulator (RXHSC = 1)
DFR
Bits
43210

DBW2-0 Bits (Bits 7-5 of IRRXDC)
001

010

011

100

101

110
Freq.

min

max

min

max

min

max

min

max

min

max

min

max

00011

381.0

421.1

363.6

444.4

347.8

470.6

333.3

500.0

320.0

533.3

307.7

571.4

KHz

01000

436.4

480.0

417.4

505.3

400.0

533.3

384.0

564.7

369.2

600.0

355.6

640.0

KHz

01011

457.7

505.3

436.4

533.3

417.4

564.7

400.0

600.0

384.0

640.0

369.9

685.6

KHz

Table 4.192 Sharp-IR Demodulator
DFR
Bits
4321
0
xxxxx

DBW2-0 Bits (Bits 7-5 of IRRXDC)
001

010

011

100

101

110
Freq.

min

max

min

max

min

max

min

max

min

max

min

max

480.0

533.3

457.1

564.7

436.4

600.0

417.4

640.0

400.0

685.6

384.0

738.5

ZFx86 Data Book 1.0 Rev D

KHz

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4
IR Transmitter Modulator Control Register (IRTXMC)
This register selects the modulation subcarrier
parameters for CEIR and Sharp-IR mode
transmission. For Sharp-IR, only the subcarrier
pulse width is controlled by this register - the
subcarrier frequency is fixed at 500 KHz.
Type:
R/W
Location: Offset 01
Bit

7

Mnemonic
Reset

6

5

4

3

MCPW2-0
0

1

2

1

0

0

1

MCFR4-0
1

Bit
7-5

After reset, the value of this register is 69h, selecting a carrier frequency of 36 KHz and an IR
pulse width of 7 msec for CEIR, or a pulse
width of 0.8 msec for Sharp-IR.

0

1

0

Description
Modulation Subcarrier Pulse Width – MCPW2-0
Specify the pulse width of the subcarrier clock as shown in Table 4.193.

4-0

Modulation Subcarrier Frequency – MCFR4-0
These bits set the frequency for the CEIR modulation subcarrier. The encoding is defined in Table 4.194.

Table 4.193 Carrier Clock Pulse Width Options (Frequency Ranges in KHz)
Encoding
MCPW Bits
765

Low Frequency
(TXHSC = 0)

High Frequency
(TXHSC = 1)

Encoding
MCPW Bits
765

Low Frequency
(TXHSC = 0)

High Frequency
(TXHSC = 1)

000

Reserved

Reserved

100

9 msec

0.9 msec

001

Reserved

Reserved

101

10.6 msec

Reserved

010

6 msec

0.7 msec

110

Reserved

Reserved

011

7 msec

0.8 msec

111

Reserved

Reserved

)

Table 4.194 CEIR Carrier Frequency Encoding (Frequency Ranges in KHz)
Encoding
MCFR Bits
43210

Low Frequency
(TXHSC = 0)

High Frequency
(TXHSC = 1)

Encoding
MCFR Bits
43210

Low Frequency
(TXHSC = 0)

High Frequency
(TXHSC = 1)

00000

Reserved

Reserved

01011

38 KHz

480 KHz

00001

Reserved

Reserved

01100

39 KHz

Reserved

00010

Reserved

Reserved

01101

40 KHz

Reserved

00011

30 KHz

400 KHz

01110

41 KHz

Reserved

00100

31 KHz

Reserved

---

---

---

00101

32 KHz

Reserved

11010

53 KHz

Reserved

00110

33 KHz

Reserved

11011

54 KHz

Reserved

00111

34 KHz

Reserved

11100

55 KHz

Reserved

ZFx86 Data Book 1.0 Rev D

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4
Table 4.194 CEIR Carrier Frequency Encoding (Frequency Ranges in KHz) (cont.)
Encoding
MCFR Bits
43210

Low Frequency
(TXHSC = 0)

01000
01001
01010

High Frequency
(TXHSC = 1)

Encoding
MCFR Bits
43210

35 KHz

450 KHz

11101

56 KHz

Reserved

36 KHz

Reserved

11110

56.9 KHz

Reserved

37 KHz

Reserved

11111

Reserved

Reserved

Low Frequency
(TXHSC = 0)

High Frequency
(TXHSC = 1)

CEIR Configuration Register (RCCFG)
This register control the basic operation of the
CEIR mode.
Location: Offset 02h
Type:
R/W
Bit
Mnemonic

7

6

5

4

3

2

R_LEN

T_OV

RXHSC

RCDM_DS

Reserved

TXHSC

0

0

0

0

0

0

Reset
Bit
7

1

0

RC_MMD1, 0
0

0

Description
Run Length Control – R_LEN
When set to 1 enables or disables run length encoding/decoding. The format of a run length code is:
YXXXXXXX where Y is the bit value and XXXXXXX is the number of bits minus 1 (Selects from 1 to 128 bits).

6

Receiver Sampling Mode – T_OV
0=
1=

5

Receiver Carrier Frequency Select – RXHSC This bit selects the receiver demodulator frequency range.
0=
1=

4

Programmed T period sampling
Oversampling mode
Low frequency: 30-56.9 KHz
High frequency: 400-480 KHz

Receiver Demodulation Disable – RCDM_DS
When this bit is 1, the internal demodulator is disabled. The internal demodulator, when enabled, performs
carrier frequency checking and envelope detection. This bit must be set to 1 (disabled), when the
demodulation is performed externally, or when oversampling mode is selected to determine the carrier
frequency.

3

Reserved

2

Transmitter Subcarrier Frequency Select – TXHSC
This bit selects the modulation carrier frequency range.
0 = Low frequency: 30-56.9 KHz
1 = High frequency: 400-480 KHz

ZFx86 Data Book 1.0 Rev D

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4
Bit

Description

1-0 Transmitter Modulator Mode – RC_MMD1,0
Determine how IR pulses are generated from the transmitted bit string.
Bits Mode Description
00
C_PLS Modulation Mode. Pulses are generated continuously for the entire logic 0 bit time.
01
8_PLS Modulation Mode. 8 pulses are generated each time one or more logic 0 bits are transmitted
following a logic 1 bit.
10
6_PLS Modulation Mode. 6 pulses are generated each time one or more logic 0 bits are transmitted
following a logic 1 bit.
11
Reserved. Result is indeterminate.

Bank Select Register (BSR)
This register is the same as the BSR register at
offset 03h in bank 0.

IR Interface Configuration Register 1 (IRCFG1)
This register holds the transceiver configuration data for Sharp-IR and SIR modes. It is also
used to directly control the transceiver operation mode when automatic configuration is not
Location: Offset 04h
Type:
Varies per bit
Bit
Mnemonic

enabled. The four least significant bits are also
used to read the identification data of a Plug
and Play IR interface adapter.

7

6

5

4

3

STRV_MS

Reserved

Set IRTXa

IRRX1
Levela

IRID3

0

0

0

0

0

Reset

2

1

0

IRIC2-0
0

0

X

a. The values shown for bits 5-4 are valid when the value of the MRID register, bank 3, is 24h or higher. If the MRID
register value is lower than 24h, bits 5-4 are reserved.

Bit
7

Description
Special Transceiver Mode Selection – STRV_MS
When this R/W bit is set to 1, the IRTX output signal is forced to active high and a timer is started. The timer
times out after 64 msec, at which time the bit is reset and the IRTX output signal becomes low again. The
timer is restarted every time a 1 is written to this bit. Although it is possible to extend the period during
which IRTX remains high beyond 64 msec, this should be avoided to prevent damage to the transmitter
LED. Writing a 0 to this bit has no effect.

6

Reserved

5

Set IRTX
When this R/W bit is set to 1, it forces the IRTX signal high.

4

IRRX1 Level
This RO bit reflects the value of the IRRX1 input signal, either 0 or 1.

3

Transceiver Identification – IRID3 (
Upon read, this RO bit returns the logic level of the IRSL3 pin. Data written to this bit is ignored.

ZFx86 Data Book 1.0 Rev D

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4
Bit
2-1

Description
Transceiver Identification/Control – IRIC2-1
The function of these R/W bits depends on whether IRSL2-1 pins are programmed as inputs or outputs.
If IRSL(2-1) are programmed as input (IRSL21_DS = 0) then:
• Upon read, these bits return the logic level of the pins (allowing external devices to identify themselves).
• Data written to these bit positions is ignored.
If IRSL(2-1) are programmed as output (IRSL21_DS = 1) then:
• If AMCFG (bit 7 of IRCFG4) is set to 1, these bits drive the IRSL(2-1) pins when Sharp-IR mode is selected.

• If AMCFG is 0, these bits drive the IRSL(2-1) pins, regardless of the selected mode.
Upon read, these bits return the values previously written.
0

IRIC0 (Transceiver Identification/Control). The function of this R/W bit depends on whether IRSL0/IRRX2
pin is programmed as an input or an output.
If IRSL0/IRRX2 is programmed as an input (IRSL0_DS = 0) then:
• Upon read, this bit returns the logic level of the pin (allowing external devices to identify themselves).
• Data written to this bit position is ignored.
If IRSL0/IRRX2 is programmed as an output (IRSL0_DS = 1), then:
• If AMCFG (bit 7 of IRCFG4) is set to 1, this bit drives the IRSL0/IRRX2 pin when Sharp-IR mode is selected.
• If AMCFG is 0, this bit drive the IRSL0/IRRX2 pin, regardless of the selected mode. Upon read, this bit
returns the value previously written.

Reserved Registers
Bank 7 registers with offset 05h and 06h are reserved.

ZFx86 Data Book 1.0 Rev D

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4
IR Interface Configuration Register 4 (IRCFG4)
This register configures the receiver data path
and enables the automatic selection of the configuration pins.
Location: Offset 07h
Type:
R/W
Bit
Mnemonic

After reset, this register contains 00h.

7

6

5

4

3

Reserved

IRRX_MD

IRSL0_DS

RXINV

IRSL21_DS

0

0

0

0

0

Reset
Bit

2

1

0

Reserved
0

0

0

Description

7

Reserved. This bit must be written with 0.

6

IRRX Mode Select – IRRX_MD
Determines whether a single input or two separate inputs are used for Low-Speed and High-Speed IrDA
modes. Table 4.195 shows the IRRXn pins used for the low-speed and high-speed infrared modes, and for
the various combinations of IRSL0_DS, IRRX_MD and AUX_IRRX.
0 = One input is used for both SIR and MIR/FIR.
1 = Separate inputs are used for SIR and MIR/FIR.

5

IRSL0/IRRX2 Pin Direction Select – IRSL0_DS
This bit determines the direction of the IRSL0/IRRX2 pin. See Table 4.195.
0 = Pin direction input
1 = Pin direction output

4

IRRX Signal Invert – RXINV
This bit supports optical transceivers with receive signals of opposite polarity (active high instead of active
low). When set to 1, an inverter is placed on the receiver input signal path.

3

IRSL2-1 Pin Direction Select – IRSL21_DS
This bit determines the direction of the IRSL2 and IRSL1 pins.
0 = Pin direction input
1 = Pin direction output

2-0

Reserved

Table 4.195 Infrared Receiver Input Selection
IRSL0_DSa

IRRX_MDb

AUX_IRRXc

HIS_IRd

IRRXn

0

0

0

x

IRRX1

0

0

1

x

IRRX2

0

1

x

0

IRRX1

0

1

x

1

IRRX2

1

0

0

x

IRRX1

1

0

1

x

Reserved

1

1

x

0

IRRX1

1

1

x

1

Reserved

a.
b.
c.
d.

IRSL0_DS (bit 5 of IRCF4) in ‘IR Interface Configuration Register 4 (IRCFG4)’ on 400.
IRRX_MD (bit 6 of IRCF4) in ‘IR Interface Configuration Register 4 (IRCFG4)’ on 400.
AUX_IRRX (bit 4 of IRCR2) in ‘IR Control Register 2 (IRCR2)’ on 385.
HIS_IR = 1 When the selected mode is MIR or FIR.

ZFx86 Data Book 1.0 Rev D

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4
Table 4.196 Bank 7 Bitmap
Register

Bits

Offset

Mnemonic

00h

IRRXDC

DBW2-0

DFR4-0

01h

IRTXMC

MCPW2-0

MCFR4-0

02h

RCCFG

R_LEN

03h

BSR

BKSE

04h

IRCFG1

STRV_MS

7

6

T_OV

5

4

RXHSC

RCDM_DS

SIRC2-0
Reserved

06h

Reserved
IRCFG4

Reserved

ZFx86 Data Book 1.0 Rev D

2

Reserved

TXHSC

1

0

RC_MMD1, 0

BSR6-0

05h

07h

3

IRRX_MD

IRSL0_DS

RXINV

IRID3

IRIC2-0

IRSL12_DS

Reserved

Page 401

4

ZFx86 Data Book 1.0 Rev D

Page 402

5
5. ZF-Logic and Clocking
The ZF-Logic module (ZFL) is a collection of
additional functions for the ZFx86. ZFL is connected internally to ISA bus. ZFL uses dedicated IO pads on ZFx86 to control external
devices. There is interconnect between the
bootstrap register bits and the system clocking
setup.
Chapter Quick Reference
5.2. "ZFL Register Space Summary" on page 404
5.3. "ISA Memory Mapper for Flash/SRAM" on page 410

5.1. Features
The features of the ZFL is shown in Figure 5-1
ZF-Logic Features. These features include:
• ZFL Register Set in ISA I/O Space
• Programmable PWM generator
• Programmable Watchdog timer
• ISA Memory Mapper for Flash/SRAM
• ISA I/O Mapper General Purpose Chip
Select (GPCS)
• Programmable Z-tag Interface

5.4. "GPCS I/O mapper" on page 422
5.5. "Watchdog Timer" on page 424
5.6. "PWM generator" on page 430
5.7. "Z-tag Overview" on page 434

• Bootstrap Register (DIP switches/PullUps) External Control of Boot Process
• User and BIOS Scratch Registers

5.8. "Boot Parameters Register" on page 437
5.9. "Data registers (F0H to FEH)" on page 444
5.10. "BUR Base Register" on page 445
5.11. "System Clocking" on page 447

ZFx86 Data Book 1.0 Rev D

Page 403

5
System FDD Lines

Internal ISA Bus

FDD MUX

ZFx86 Internal
Boot Up ROM
(BUR)

FDD Lines

Z-tag

CS

io_cs*

IO/Mapper

PWM

ISA Interface
to the ZFL
Register Set
Ports 218-21A

wdi, wdo
Watchdog
NMI, SCI, SMI,
or reset

ISA Memory Mapper

Scratch
Registers
Bootstrap
Registers

mem_cs*

Read 24-Bits on Reset

Clocking
Control

Address
MUX

ISA Address

Figure 5-1 ZF-Logic Features

5.2. ZFL Register Space Summary
The ZFL register space is accessed from a 8bit index register and 8, 16, or 32-bit data
pathway located in ISA IO space. The
addresses are:

ZFL data registers are accessed in one of the
the following ways:
A. 8-bit data transfer: Works with all indexes.
Indexes single 8-bit register at index.
1.

Write register number to port 218H.

2.

Write the register value using data register 219H.

Table 5.1 Access to ZFL
Item

I/O Address

8-bit Index

218h

8-bit Data at index

219h

16-bit Data at index

21Ah

32-bit Data at index

21Ah

ZFx86 Data Book 1.0 Rev D

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5
B. 16 and 32 bit access. Works only with
even indexes. Indexes two or four consecutive data registers with single IO instruction.
1.

Write register number to port 218H.

2.

Read or write the register value using
data register 21AH.

Example: Read the 16-Bit Data at Index 02 to
pick up the ZF-Logic Revision:
The current revision, and thus the revision of
this specification, is 1234H.

mov
mov
out
mov
in

al,02h
dx,218h
dx,al
dx,21Ah
ax,dx

;
;
;
;
;

even (word aligned) address to do a 16-bit
transfer (into AX), and we used index port
21A. This is the correct way to do it

Accessing the ZF-Logic Registers
A complete index of the ZF-Logic registers is
shown in the tables below. While all registers
can be accessed as single bytes, sometimes it
is convenient to access them as 16-bit words
(see the example on the previous page).
You may also access them as 32-bit words
when appropriate. See the example in ‘Fields
in 32-bit memory settings register’ on page
416.

Index
Index Address
Set Index
read value:
AX=1234H

Programming Caution: 16 bit access has
two opportunities for the programmer to get
wrong results: make attempt to use 16 bit
access for odd addresses and use wrong data
IO address. In the example above, we used an

ZFx86 Data Book 1.0 Rev D

Page 405

5
Table 5.2 ZF-Logic Complete Index
8-Bit Data at Index

8-Bit Data at Index + 1

02

ZF-Logic Revision (LSB) -- (02H)

ZF- Logic Revision (MSB) -- (03H)

04

PWM Prescaler Low Byte -- (04H)

PWM Prescaler High Byte - (05H)

06

PWM duty cycle -- (06H)

08

PWM I/O Control -- (08H)

0A

PWM Read Output -- (0AH)

0C

Watchdog 1 Count Low Byte -- (0CH)

Watchdog 1 Count High Byte -- (0DH)

0E

Watchdog 2 Count Value -- (0EH)

Watchdog Reset Pulse Length -- (0FH)

10

Watchdog Control Low -- (10H)

Watchdog Control High -- (11H)

12

Watchdog Status -- (12H)

Index

8-Bit Data at Index

8-Bit Data at Index + 1

14

I/O Window 0 Base Low (14H)

I/O Window 0 Base High (15H)

16

I/O Window 0 Control (16H)

18

I/O Window 1 Base Low (18H)

1A

I/O Window 1 Control (1AH)

1C

I/O Window 2 Base Low (1CH)

1E

I/O Window 2 Control (1EH)

20

I/O Window 3 Base Low (20H)

22

I/O Window 3 Control (22EH)

I/O Window 2 Base High (1DH)

I/O Window

I/O Window 1 Base High (19H)

W/D

PWM

Index

I/O Window 3 Base High (21H)

24

ZFx86 Data Book 1.0 Rev D

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5
Table 5.2 ZF-Logic Complete Index (cont.)
Index

8-Bit Data at Index

8-Bit Data at Index + 1

26

Memory Window 0 Base Bits 7-0

MW0 Base 15-12

28

Memory Window 0 Base Bits 23-16

Memory Window 0 Base Bits 31-24

2A

Memory Window 0 Size Bits 7-0

MW0 Size 15-12

2C

Memory Window 0 Size Bits 23-16

Memory Window 0 Size Bits 31-24

2E

Memory Window 0 Page Bits 7-0

MW0 Page 15-12

30

Memory WIndow 0 Page Bits 23-16

Memory Window 0 Page Bits 31-24

32

Memory Window 1 Base Bits 7-0

MW1 Base 15-12

34

Memory Window 1 Base Bits 23-16

Memory Window 1 Base Bits 31-24

36

Memory Window 1 Size Bits 7-0

MW1 Size 15-12

38

Memory Window 1 Size Bits 23-16

Memory Window 1 Size Bits 31-24

3A

Memory Window 1 Page Bits 7-0

MW1 Page 15-12

3C

Memory Window 1 Page Bits 23-16

Memory Window 1 Page Bits 31-24

3E

Memory Window 2 Base Bits 7-0

MW2 Base 15-12

40

Memory Window 2 Base Bits 23-16

Memory Window 2 Base Bits 31-24

42

Memory Window 2 Size Bits 7-0

MW2 Size 15-12

44

Memory Window 2 Size Bits 23-16

Memory Window 2 Size Bits 31-24

46

Memory Window 2 Page Bits 7-0

MW2 Page 15-12

48

Memory Window 2 Page Bits 23-16

Memory Window 2 Page Bits 31-24

4A

Memory Window 3 Base Bits 7-0

MW3 Base 15-12

4C

Memory Window 3 Base Bits 23-16

Memory Window 3 Base Bits 31-24

4E

Memory Window 3 Size Bits 7-0

MW3 Size 15-12

50

Memory Window 3 Size Bits 23-16

Memory Window 3 Size Bits 31-24

52

Memory Window 3 Page Bits 7-0

MW3 Page 15-12

54

Memory Window 3 Page Bits 23-16

Memory Window 3 Page Bits 31-24

ZFx86 Data Book 1.0 Rev D

MW0 Base 11-8

MW0 Size 11-8

MW0 Page 11-8

MW1 Size 11-8

MW1 Page 11-8

Memory Window

MW1 Base 11-8

MW2 Base 11-8

MW2 Size 11-8

MW2 Page 11-8

MW3 Base 11-8

MW3 Size 11-8

MW3 Page 11-8

Page 407

5
Table 5.2 ZF-Logic Complete Index (cont.)
Index

8-Bit Data at Index

56

8-Bit Data at Index + 1
BUR Base Low (57H)

58

BUR Base High (58H)

5A

Memory Control Low (5AH)

Memory Control High (5BH)

5C
5E

Z-tag Data Write Register (5EH)

60

Z-tag Data Read Register (60H)

62

Bootstrap Bits 7-0 (62H)

64

Bootstrap Bits 23-16 (64H)

66

I/O+Memory Window Map Events 66H

68

Scratch Register 0 Low (68H)

Scratch Register 0 High (69H)

6A

Scratch Register 1 Low (6AH)

Scratch Register 1 High (6BH)

6C

Scratch Register 2 Low (6CH)

Scratch Register 2 High (6CH)

6E

Scratch Register 3 Low (6EH)

Scratch Register 3 High (6FH)

70

Scratch Register 4 Low (70H)

Scratch Register 4 High (70H)

72

Scratch Register 5 Low (72H)

Scratch Register 5 High (73H)

74

Scratch Register 6 Low (74H)

Scratch Register 6 High (75H)

76

Scratch Register 7 Low (76H)

Scratch Register 7 High (77H)

78

Scratch Register 8 Low (78H)

Scratch Register 8 High (79H)

7A

Scratch Register 9 Low (7AH)

Scratch Register 9 High (7BH)

7C

Z-tag control register (7CH)

Z-tag Sequencer Divisor Register (7DH)

7E

Z-tag Sequencer Waveform (7EH)

Z-tag Sequencer Strobe Points (7FH)

80

Z-tag Sequencer Data (80H)

Z-tag Sequencer Status (81H)

5.2.1. Pins Associated with ZF-Logic
Listed below (for a complete reference) are all
of the electrical pins associated with the ZFLogic.

ZFx86 Data Book 1.0 Rev D

Scratch Registers

Bootstrap Bits 15-8 (63H)

You may cross refererence to ‘Pin Descriptions Sorted by Pin’ on page 545.

Page 408

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Table 5.3 ZF-Logic Pin List
B03

io_cs0

ZF-Logic I/O Mapper GPCS 0

A02

io_cs1

ZF-Logic I/O Mapper GPCS 1

A01

io_cs2

ZF-Logic I/O Mapper GPCS 2

C03

io_cs3

ZF-Logic I/O Mapper GPCS 3

B04

Mem_cs0

ZF-Logic Memory Mapper CS 0a

D05

Mem_cs1

ZF-Logic Memory Mapper CS 1a.

A03

Mem_cs2

ZF-Logic Memory Mapper CS 2a.

C04

Mem_cs3

ZF-Logic Memory Mapper CS 3a.

B05

Pwm

ZF-Logic PWM Output

AC01

sa[00]

ISA Address/Bootstrap Register In

AB02

sa[01]

ISA Address/Bootstrap Register In

AB01

sa[02]

ISA Address/Bootstrap Register In

AA03

sa[03]

ISA Address/Bootstrap Register In

AA02

sa[04]

ISA Address/Bootstrap Register In

Y04

sa[05]

ISA Address/Bootstrap Register In

AA01

sa[06]

ISA Address/Bootstrap Register In

Y02

sa[07]

ISA Address/Bootstrap Register In

Y03

sa[08]

ISA Address/Bootstrap Register In

Y01

sa[09]

ISA Address/Bootstrap Register In

W03

sa[10]

ISA Address/Bootstrap Register In

W02

sa[11]

ISA Address/Bootstrap Register In

W01

sa[12]

ISA Address/Bootstrap Register In

V03

sa[13]

ISA Address/Bootstrap Register In

V04

sa[14]

ISA Address/Bootstrap Register In

V02

sa[15]

ISA Address/Bootstrap Register In

V01

sa[16]

ISA Address/Bootstrap Register In

U02

sa[17]

ISA Address/Bootstrap Register In

U03

sa[18]

ISA Address/Bootstrap Register In

U01

sa[19]

ISA Address/Bootstrap Register In

ZFx86 Data Book 1.0 Rev D

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Table 5.3 ZF-Logic Pin List
T04

sa[20]

ISA Address/Bootstrap Register In

T03

sa[21]

ISA Address/Bootstrap Register In

T02

sa[22]

ISA Address/Bootstrap Register In

R03

sa[23]

ISA Address/Bootstrap Register In

A04

Wdi

ZF Logic - Watch Dog Timer

C05

Wdo

ZF Logic - Watch Dog Timer

a. When the ZF-Logic is disabled, the MEM_CS* pins remain active. However, their functions changes. Generally
there is never a reason to disable the ZF-Lgoic. See ‘Composite BootStrap Register Map’ on page 438.

5.3. ISA Memory Mapper for Flash/SRAM
The ZFL allows the ZFx86 to control up to four
external memory devices on the ISA bus.
These devices can be mapped into the system
memory address space. Typically, this feature
is used to map external Flash memory into the
ISA address space without external address
decoding logic.
ISA Memory Mapper

Mem_cs*

Translated ISA
Address
ISA Address

Address
MUX

ISA Address

Table 5.4 Memory Mapper Pins

These devices are connected externally to ISA
BUS address, data and memr/memw signals.
Each device has a dedicated chip select signal generated by ZFL. Each device can
occupy up to 16 Megabytes (occupying all 24
ISA address lines). The minimum window size
is 8Kbyte.
These devices are mapped into the system
memory space and accessed through windows (memory view ports) in the memory
space. In DOS mode these windows can be
up to 256K bytes and reside only in upper 1
Mbyte DOS ROM area (C0000-FFFFF). In
protected mode the windows can occupy all
24 ISA address lines (000000 - FFFFFF). This
area is accessed in protected mode through
memory space above system SDRAM. If the
address is not in the system memory and no
PCI device claims it then it is forwarded to the
ISA bus. This makes the ISA bus appear multiple times in the upper memory area.

PKG Name

Description

B04

Mem_cs0

ZF-Logic Memory Mapper CS 0

D05

Mem_cs1

ZF-Logic Memory Mapper CS 1

A03

Mem_cs2

ZF-Logic Memory Mapper CS 2

• Window Size

C04

Mem_cs3

ZF-Logic Memory Mapper CS 3

• Base address

A separate window (memory viewport) can be
defined for each device with the following
parameters:

• Page

ZFx86 Data Book 1.0 Rev D

Page 410

5
All parameters are aligned with 4 KB increments in system memory.Access mode
(rd_only / wr) can be changed from the window control register (see Table 5.12, ‘Memory
Control Low -- Index 5AH,’ on page 413). The
Memory Chip Select lines (Mem_cs*) are
always active low.

lines. The ISA address lines in ZFx86 are stable during entire memory cycle and thus
FLASH can be directly connected to ISA bus
signals.
A memory windows overlap event is generated if two or more mem_cs* signals are
active at the same time, i.e. when memory
windows do overlap in memory space. This
event can be routed to NMI, SCI or SMI.
Access to overlapping area will not cause any
of the mem_cs* to became active.

The BASE and SIZE are the window in the
ZFx86 ISA address space, and the PAGE is a
relative value (+ or - from BASE) used to calculate the target address in the flash.
Memory page registers are translated on-thefly using ISA bus address lines. If an active
mapping window is accessed then the FLASH
page register is added to ISA upper address

Window 0 has special power up initialization.

Table 5.5 Indices For Memory Windows
Function

0

1

2

3

Base Low

27H

33H

3FH

4BH

Table 5.6 on p. 411

base bits 15:12 (nibble 3)

Base High

28H

34H

40H

4CH

Table 5.7 on p. 412

base bits 23:16 (nibbles 5-4)

Size Low

2BH

37H

43H

4FH

Table 5.8 on p. 412

page size nibble 3

Size High

2CH

38H

44H

50H

Table 5.9 on p. 412

page size nibbles 5 - 4

Page Low

2FH

3BH

47H

53H

Table 5.10 on p. 412

page nibble 3

Page High

30H

3CH

48H

54H

Table 5.11 on p. 412

page nibbles 5 - 4

Reference

Description

Control Low

5AH

Table 5.12 on p. 413

read/write control

Control High

5BH

Table 5.13 on p. 413

address decoding for boot

Status

66H

Table 5.14 on p. 414

Memory (and I/O) Status

Table 5.6 Memory Window “N” Base Low - Bits 15:12 (nibble 3)
Bit
Function
Default
R/W

7

6

5

4

d15

d14

d13

d12

reserved

0

0

0

0

0

R/W

R/W

R/W

R/W

R/O

ZFx86 Data Book 1.0 Rev D

3

2

1

0

Page 411

5
Table 5.7 Memory Window “N” Base High - Bits 23:16 (nibbles 5-4)
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

d23

d22

d21

d20

d19

d18

d17

d16

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Table 5.8 Memory Window “N” Size Low - (nibble 3)
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

d15

d14

d13

d12

reserved

reserved

reserved

reserved

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/O

R/O

R/O

R/O

Programming Notes for Memory Window Size: Setting the memory window size to zero disables the memory window.

Table 5.9 Memory Window “N” Size High - (nibbles 5-4)
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

d23

d22

d21

d20

d19

d18

d17

d16

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Table 5.10 Memory Window “N' Page Low - (nibble 3)
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

d15

d14

d13

d12

reserved

reserved

reserved

reserved

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/O

R/O

R/O

R/O

Table 5.11 Memory Window “N” Page High - (nibbles 5-4)
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

d23

d22

d21

d20

d19

d18

d17

d16

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

ZFx86 Data Book 1.0 Rev D

Page 412

5
Table 5.12 Memory Control Low -- Index 5AH
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

w3_ro

w2_ro

w1_ro

w0_ro

w3_8

w2_8

w1_8

w0_8

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Note: The default value for this register bit 0 is dependent on bootstrap jumper setting, connected to the ZFx86 SA12
line. This can be overridden writing new value to the memory window control register.
Setting the memory window to read-only mode disables both, the MEMW_N and SMEMW_N signals on ISA bus for
the according memory window region.
Bit

Name

7:4

Function
wn_ro

Window n Read-write Control
0: Window N Is Read-write
1: Window N Is Read-only

3:0

wn_8

Window n Data Bus Width
0=

Window N Uses 16-bit Data Access

1=

Window N Uses 8-bit Data Access

Table 5.13 Memory Control High -- Index 5BH
Bit

7

6

Function
Default
R/W

Bit

Name

7:1

Reserved

0

full ISA

ZFx86 Data Book 1.0 Rev D

5

4

3

2

1

0

reserved

full ISA

0

0

R/O

R/W

Function
Masks address bits 23:20 out of comparison. This is used for boot to fetch data from
ROM
0=

Enable only bits 19:0 in address calculations

1=

Enable full ISA 23:0 in address calculations

Page 413

5
Table 5.14 I/O and Memory Window Mapper Events -- Index 66H
Bit

7

6
Reserved

5

4
Event Type

Function

3

2

1

0

Memory

I/O

memory

I/O

Overlap

Overlap

window

window
change

change
Default
R/W

Bit

0

0

0

0

0

0

R/O

R/W

R/W

R/W

R/W

R/W

Name

7:6

Reserved

5:4

Event Type

Function

Generated event type
00 =
01 =
10 =
11 =

3

Memory Overlap

Enable resolve event on memory overlap
0=
1=

2

I/O Overlap

Memory Access

I/O Access

Disable event on I/O window overlap
Enable event on I/O window overlap

Enable event on memory window change
0=
1=

0

Disable event on memory overlap
Enable event on memory overlap

Enable event on I/O window overlap
0=
1=

1

No event
SCI
NMI
SMI

Disable event
Enable event

Enable event on I/O window change
0=
1=

Disable event
Enable event

It is only possible to boot from these sources:
• External 8 bit ROM/FLASH , mem_cs0
• External 16-bit ROM/FLASH, mem_cs0,
bootstrap 12 = 0
• External BUR, always 8-bit, gpio0, bootstrap 11 = 0. See BS11 in Table 5.42.
• Internal BUR, always 8-bit
The selection between BUR and ROM/FLASH
is done according to bootstrap bit 23:

1 = boot from BUR
The boot starts from the first code fetch at
address FFFFFFF0 which is translated to ISA
space FFFFF0 (upper 8 bits truncated).
The internal decoder sees only the first megabyte of it (the FULL_ISA bit in ZF reg space )
-FFFF0. The chip select is programmed to
respond to the addesses in the range F0000 –
FFFFF or the last 64 Kbytes.

0 = boot from ROM/FLASH

ZFx86 Data Book 1.0 Rev D

Page 414

5
16 MB

Window

Size

Window
Page + Base

Base
Address

0

External Address
Space (Flash, etc.)

0 MB

ISA Address Space
Figure 5-2 Memory Window Mapping

5.3.1. Window settings registers
The starting address, window size and page
define the mapping for each of the four external memory devices. The mapping is disabled
when window size is zero.
The register map of Memory decode area is
shown in Table 5.5, ‘Indices For Memory Windows,’ on page 411 Window 0 has special
power up initialization. See "Initialization of
mem_cs0" on page 418.,
The starting address, window size and page
registers are each 32-bit registers. Each of
these consumes four 8-bit registers in ZFL
register space. Window size, location and
FLASH page can be set in 4KB increments (as
the last 12 bits are implicitly 0). ISA BUS limits

ZFx86 Data Book 1.0 Rev D

the address space to 24 bits, so the top 8 bits
are implicitly 0. The layout of the memory settings register is shown below. The lower 12
bits must be zero to comply with 4KB increments and the upper 8 bits are 0 because the
ISA bus has only 24 address lines.
When determining whether or not an
addresses emitted by the processor should
generate a mem_cs*, the upper 8-bits of the
32-bit memory address are ignored. Thus a
memory page can appear (alias) many places
in the (CPU’s) 4 GB address space.

5.3.1.1. Page Register Calculations
Note, that page addresses are always ADDED

Page 415

5
to the actual address, so in order to access
flash chip at address smaller than memory
window location, the page register value must
cause roll-over at 16Mbyte boundary. The simple rule of the thumb for calculating desired
page register value is:
Page_register = (16M-memory_window_base)
+ desired_flash_offset
Therefore, in order to map flash offset 0000h
for memory window, located at E0000h, the
correct formula is:
Page_register = (1000000h-E0000h)+0 =
F20000h
For another example, see 5.3.5. "Sample
Code for Memory Window Calculation" on
page 421.

5.3.1.2. Size Register
The right-most 12 bits of the Size Register are
implicitly 1’s. So F000H is really FFFFH. The
size actually represents the maximum address
from memory window base that will be
decoded as window, so the window size
0FFFFH (actually 0FxxxH) will result 64 Kbyte
window, and 10000H (actually 10xxxH) will

result in a 68 Kbyte window.

5.3.1.3. Base Register
The memory window content is visible using
two different access methods:
a) Memory window can be located in upper
portion of the first 1MB of the address space at
addresses (C0000-FFFFF). This window is
directly visible as far as shadow memory is not
mapped to that area. (See Memory Holes following).
b) Because of the ISA-PCI address mapping,
the same memory window will roll over at
every 16Mbyte on entire 4 Gbyte PCI memory
space as far as there is no SDRAM at this
area and no PCI device claims it. For example, if 5 Mbyte memory window is created in
memory area 100000h-600000h, the same
memory window content can be seen and
accessed at regions 1100000h-1600000h,
2100000h-2600000h etc. This allows the
access of the memory window content despite
of the SDRAM presence, since memory window accesses can always happen above first
256 Mbyte.

There are two 8-bit registers each for Window Size, Base and Page. In each
case, the two 8-bit registers supply bits 15-12 and bits 23-16 respectively. You
may access these registers as a 32-bit operand. That is, you do a 32-bit in or out
to the lowest of the 4 addresses. See the programming example following.
Bits 15-12

Bits 23-16

12 bits

8 bits

12 bits

24|23

31
00H

12|11

0
00H

User Defined

32 bits
Figure 5-3 Fields in 32-bit memory settings register

5.3.1.4. Viewing Memory Holes

ZFx86 Data Book 1.0 Rev D

The DRAM address space is potentially the
first 265 MB of the address space (depending

Page 416

5
upon the size of the DRAM). Table 3.20,
‘Shadow RAM Read Enable Control Register
(SHADRC),’ on page 149, and Table 3.21,
‘Shadow RAM Write Enable Control Register,’
on page 150, describe the allocation of DRAM
memory between C0000 and F0000. DRAM
which not enabled for write and not enabled
for read represent a memory hole. DRAM
addresses in that range propagate to the ISA
address bus and can be “intercepted” by
#define NBIndex
#define NBData
#define RID
#define SHADRC
#define SHADWC

0x24
0x26
0x100
0x200
0X201

memory windows.The printout below is from a
DOS application program run on ZFx86 Integrated Development System after boot using
the Phoenix BIOS. This tells you which
addresses in the range C0000 to FFFFF are
available for windows. In this case addresses
from C0000 to C7FFF (32K) are taken up by
the video BIOS on the Video Card.

// North Bridge Configuration Index Register
// North Bridge Configuration Data Register
// North Bridge RevisionID Register
// Shadow RAM Read Enable Control Register
// Shadow RAM Write Enable Control Register

void displayNBConfiguration (void)
{
unsigned long uii;
printf ("North Bridge RevisionID Register = %04XH\r\n", uiGetNB (RID));
printf ("North Bridge Shadow RAM Read Enable Control Register = %04XH\r\n", uiGetNB (SHADRC));
printf ("North Bridge Shadow RAM Write Enable Control Register = %04XH\r\n", uiGetNB (SHADWC));
// figure out which pages are available for memory mapping we need 0 in both -uii = uiGetNB (SHADRC) | uiGetNB (SHADWC);
uii = uii ^ 0xFFFF; // toggle all the bits - 1 means that both RD and WR disabled
if ( (uii & BIT0 ) == BIT0 ) printf ("Window OK at C0000-C3FFFH \r\n");
if ( (uii & BIT1 ) == BIT1 ) printf ("Window OK at C4000-C7FFFH \r\n");
if ( (uii & BIT2 ) == BIT2 ) printf ("Window OK at C8000-CBFFFH \r\n");
if ( (uii & BIT3 ) == BIT3 ) printf ("Window OK at CC000-CFFFFH \r\n");
if ( (uii & BIT4 ) == BIT4 ) printf ("Window OK at D0000-D3FFFH \r\n");
if ( (uii & BIT5 ) == BIT5 ) printf ("Window OK at D4000-D7FFFH \r\n");
if ( (uii & BIT6 ) == BIT6 ) printf ("Window OK at D8000-DBFFFH \r\n");
if ( (uii & BIT7 ) == BIT7 ) printf ("Window OK at DC000-DFFFFH \r\n");
if ( (uii & BIT8 ) == BIT8 ) printf ("Window OK at E0000-E3FFFH \r\n");
if ( (uii & BIT9 ) == BIT9 ) printf ("Window OK at E4000-E7FFFH \r\n");
if ( (uii & BIT10 ) == BIT10 ) printf ("Window OK at E8000-EBFFFHWindow
\r\n");
if ( (uii & BIT11 ) == BIT11 ) printf ("Window OK at EC000-EFFFFH \r\n");
if ( (uii & BIT12 ) == BIT12 ) printf ("Window OK at F0000-F3FFFHWindow
\r\n");
if ( (uii & BIT13 ) == BIT13 ) printf ("Window OK at F4000-F7FFFH \r\n");
if ( (uii & BIT14 ) == BIT14 ) printf ("Window OK at F8000-FBFFFHWindow
\r\n");
if ( (uii & BIT15 ) == BIT15 ) printf ("Window OK at FC000-FFFFFH \r\n");
Window
}
unsigned int uiGetNB (unsigned int uiNBItem) {
Window
outpw (NBIndex, uiNBItem);
return inpw (NBData); }
Window

ZFx86 Data Book 1.0 Rev D

OK at C8000-CBFFFH
OK at CC000-CFFFFH
OK at D0000-D3FFFH
OK at D4000-D7FFFH
OK at D8000-DBFFFH
OK at DC000-DFFFFH

Page 417

5
5.3.2. Control (R/W, 8/16)
The control register is common for all four
memory devices. The first four bits control the
data width of external memory device. The
lower four bits set the write enable mask to
write protect memory. See Table 5.13, ‘Memory Control High -- Index 5BH,’ on page 413.

The default initialization provides a 64K window starting at F000H in the ZFx86.
Default Power-Up Initialization of mem_cs0
(window 0) is done by the ZFx86 hardware to
boot from flash using window 0:
• Base address = F0000H

5.3.3. Events (SMI, etc.)

• Window size = 64K-1 (F000H)

The mem_cs* is asserted when it does not
overlap with others in system RAM. This runtime test is executed every time the memory
mapping registers are accessed. The events
register (Table 5.14, ‘I/O and Memory Window
Mapper Events -- Index 66H,’ on page 414)
allows control of the generated event (SCI,
NMI, etc.) based on Window Change or Window Overlap.

• Width = dependent on bootstrap at SA12

5.3.4. Initialization of mem_cs0
The ZFx86 is designed to boot from an external ROM/FLASH chip using mem_cs0. In
order to do this, the ZFx86 pre-loads the Base,
Size and Page registers for mem_cs0 on
power up. It also sets the width bit based on
your setting of SA12 (see ‘Boot Parameters
Register’ on page 437). The mem_cs0 registers are set up such that the top 64K of the
external Flash Chip will be accessed.

• Page = 00000h
It's essential to set the mem_cs0 page to
00F00000h before the first FAR jump in BIOS.
Otherwise the boot fails with flash chips bigger
than 1MB, since upper addresses are cleared
from the ISA bus after a far jump and the next
memory reads (instruction fetches) go to the
last 64K of the first 1M of the flash chip.

Mem_cs0 Programming Example
NOTE: It’s essential to set the mem_cs0 page
address to 00F00000h before the first FAR
jump in BIOS for flash chips larger than 1
Mbyte. Otherwise the POST fails, since upper
addresses are cleared from the ISA bus after
the first far jump and subsequent memory
reads appear at the first megabyte of the chip,
instead of the last megabyte.

The exact boot up sequence of an X86 processor is well known -- but the addition of the
ZFx86 ISA Memory Mapper makes the process a bit tricky.

ZFx86 Data Book 1.0 Rev D

Page 418

5
; set page address to access last MB inside flash
mov
mov
out
add
mov
out

al, 2Eh ; Memwindow 0 page register 32-bit access
dx, 218h ; ZFL IDX register
dx, al ; Select memwin 0 base
dx, 2 ; seek to 32-bit data register
eax, 00F00000h ; set page to be 16Mbyte-1Mbyte
dx, eax ; set page (not needed see below)

; Following near jump is mandatory
jmp $+2 ; refill CPU pipeline
comment * Thanks to code already fetched into CPU pipeline we do not crash after next OUT instruction. However, after that we can not make another code fetch from ISA device until we make the
first FAR jump that clears upper address bits bus. *
out dx,eax
; Nothing must come between OUT and FAR JMP or we don’t fit
; inside pipeline (16 bytes) any more.
db 0EAh ; JMP FAR absolute
dw offset FirstFarJmp
dw 0F000h
FirstFarJmp:
comment * We are all right now for whatever chip size, because we always see the last megabyte of
the chip from now on. If we need a bigger window to flash (because of the 256K BIOS image perhaps), we can enable it here and now, before proceeding with actual POST *
IF (WINDOW_256K) ; set window size to 256K now
mov
dec
dec
out
inc
inc
mov
out

al, 2Ah
dx
dx
dx, al
dx
dx
eax, 40000h-1 ; window size to 256K
dx, eax

; drop window base address to C0000h
mov
dec
dec
out
inc
inc
mov
out

al, 26h
dx
dx
dx, al
dx
dx
eax, 0C0000h
dx, eax

ENDIF ;(WINDOW_256K)
; Jump now whenever it was necessary in a first place
db 0EAh
; JMP FAR absolute
FJum_Offset dw 0h ; offset into BIOS

ZFx86 Data Book 1.0 Rev D

Page 419

5
FJump_Segment dw 0h ; segment into BIOS

ZFx86 Data Book 1.0 Rev D

Page 420

5
5.3.5. Sample Code for Memory Window Calculation
Here we will create a 32K window starting at
D0000 in the ZFx86 address space. The
window initially point to offset 2000H within
the flash chip.

Example: You would have to set the Page
register to 00F32000H (or F32 in the ZFx86
Phoenix BIOS Memory Window Setup
Screen).

Phoenix ZFx86 BIOS Memory Window Setup Calculator

Helper: Enter Window Size between 8 and 16384K: 32
Recommended Value for Size = 007000H

Enter Desired Window Base in Hex (example DC000) D0000
Enter Desired Window Size in Hex (example 1000 = 8K, FFF000 = 16 MB 7000
unsigned long ulBase, ulSize, ulTarget, ulPage, ulDesiredK;
printf ("\r\n\n\nPhoenix ZFx86 BIOS Memory Window Setup Calculator \r\n", uiWorkingCS);
printf ("\r\nHelper: Enter Window Size between 8 and 16384K: ");
ulDesiredK = uiScanInDecimal(0);
if ((ulDesiredK >= 8) && (ulDesiredK <= 16384))
printf ("\r\n Recommended Value for ""Size"" = %06lXH\r\n", (ulDesiredK-4) * 1024 );
printf ("\r\nEnter Desired Window Base in Hex (example DC000) ");
ulBase = ulScanInHex ();
printf ("\r\nEnter Desired Window Size in Hex (example 1000 = 8K, FFF000 = 16 MB ");
ulSize = ulScanInHex ();
printf ("\r\nEnter Flash Target Address in Hex (example 2000 = 8K) ");
ulTarget = ulScanInHex ();
ulBase = ulBase & 0xFFF000;
ulSize = ulSize & 0xFFF000 ;
ulTarget = ulTarget & 0xFFF000;
printf ("\r\nBase = %08lXH or %03lXH or %04ld decimal", ulBase, ulBase >> 12, ulBase
>>12);
if (ulSize == 0) printf ("\r\nWindow Disabled Size == 0");
else
printf ("\r\nSize = %08lXH or %03lXH or %04ld decimal for Size = %dK", ulSize, ulSize
>> 12, ulSize >>12, ((ulSize >> 12) + 1) * 4);
ulPage = (0x1000000 - ulBase + ulTarget) & 0xFFF000;
printf ("\r\nPage = %08lXH or %03lXH or %04ld decimal for Flash Off set =
%08lXH\r\n\n",
ulPage, ulPage >> 12, ulPage >>12, ulTarget);

ZFx86 Data Book 1.0 Rev D

Page 421

5
5.4. GPCS I/O mapper
ZFx86 has four GPCS (General Purpose Chip
Select) signals mapped to io_cs* pins. GPCS
signals can be used to connect external
devices to ISA I/O space without external
address decode logic. Each io_cs* signal is
assigned an address (or a set of consecutive
addresses) in the ISA I/O space. This address,
or set of consecutive addresses, is called the
“window”. The window can cover 16 byte ports
or 8 word ports.

I/O ranges of different GPCS signals can not
overlap. An internal check is done to assure
that this condition is satisfied before enabling
the io_cs* lines.

For example, if the chip you wish to connect to
the ZFx86 using one of the io_cs pins has four
ports (such as the old 8255 chip), you would
want the chip select to be asserted for four
consecutive addresses. The chip itself would
differentiate between the addresses by looking
at the low two bits of the ISA address bus.

The base address register is 16-bits wide. This
allows the window to be defined anywhere in
the 16-bit IO space.

.

The io_cs* signal can be programmed for
either 8-bit or 16-bit wide bus access: on an
aligned 16 bit I/O transfer, a 16-bit wide bus
would generate one I/O cycle, and an 8-bit
wide bus would generate two I/O cycles.

The GPCS register set is shown below, and
also in Table 5.16.
1. GPCS 0 settings
• 15H-14H:io_cs0 base address

I/O Mapper

io_cs*

Table 5.15 GPCS Pins

• 16H: io_cs0 control
2. GPCS 1 settings
• 19H-18H:io_cs0 base address
• 1AH: io_cs0 control

PKG

Name

Description

B03

io_cs0

ZF-Logic I/O Mapper GPCS 0

A02

io_cs1

ZF-Logic I/O Mapper GPCS 1

• 1DH-1CH:io_cs0 base address

A01

io_cs2

ZF-Logic I/O Mapper GPCS 2

• 1EH: io_cs0 control

C03

io_cs3

ZF-Logic I/O Mapper GPCS 3

3. GPCS 2 settings

4. GPCS 3 settings
• 21H-20H:io_cs0 base address
• 22H: io_cs0 control
5. Events Register (66H) (NMI, etc.)

ZFx86 Data Book 1.0 Rev D

Page 422

5
Table 5.16 ZF-Logic Indices For I/O Windows
Function

0

1

2

3

Reference

Description

Base Low

14H

18H

1CH

20H

Table 5.18 on page 423

base bits 7-0

Base High

15H

19H

1DH

21H

Table 5.19 on page 424

base bits 15-8

Control

16H

1AH

1EH

22H

Table 5.20 on page 426

Table 5.17 ZF-Logic Index for I/O Windows
I/O Window 0 Base Low (14H)

16

I/O Window 0 Control (16H)

18

I/O Window 1 Base Low (18H)

1A

I/O Window 1 Control (1AH)

1C

I/O Window 2 Base Low (1CH)

1E

I/O Window 2 Control (1EH)

20

I/O Window 3 Base Low (20H)

22

I/O Window 3 Control (22H)

I/O Window 0 Base High (15H)

I/O Window

14

I/O Window 1 Base High (19H)

I/O Window 2 Base High (1DH)

I/O Window 3 Base High (21H)

...
Note: see Table 5.14, ‘I/O and Memory Window Mapper Events -- Index 66H,’ on page 414
66

I/O+Memory Window Map Events (66H)
Events Register

Table 5.18 I/O Window “N” Base Low Format
Bit

7

Function
Default
R/W

ZFx86 Data Book 1.0 Rev D

6

5

4

3

2

1

0

I/O Window 0 Base Low
0
R/W

Page 423

5
Table 5.19 I/O Window “N” Base High Format
Bit

7

6

5

Function

4

2

1

0

I/O Window 0 Base High

Default

0

R/W

R/W

Bit
7

3

Name
win_ro

Function
I/O window read/write control
0: = Access is read-write
1: = Access is read-only
Setting window to read-only mode disables IOW_N signal on ISA bus for IO
window address range.

6

16_bit

I/O window datapath width
0=
1=

5

act_lvl

io_cs active level
0=
1=

4

win_en

win_siz

io_cs is active low
io_cs is active high

I/O window enable in I/O space
0=
1=

3:0

8-bit wide access
16-bit wide access

I/O window is disabled
I/O window is enabled

Number of consecutive 8-bit I/O addresses to decode starting from I/O window base.
The number of consecutive addresses decoded is win_siz + 1. For example,
setting the window size to 0 enables one I/O address at I/O window base.
Setting size to 0Fh will enable I/O window of 16 addresses starting from I/O
window base. You can access a maximum of 16 byte ports or 8 word ports.

5.4.1. GPCS control

5.4.3. GPCS base high byte

The Active Level (act_lvl) selects the active
level of io_cs* line. The Window Enable
(win_en) enables the decoder. The Write
Enable (win_ro) masks the ISA I/O write signal
making the window read-only. The Window
Size (win_siz) determines the window size in
the ISA IO space.

This byte is located at GPCS base + 1 in ZFL
register map. It determines the high byte of
window start address in ISA IO space.

5.4.2. GPCS base low byte

5.5. Watchdog Timer

This byte is located at GPCS base in ZFL register map. It determines the low byte of the
window start address in the ISA IO space.

The watchdog timer is used to stabilize and
recover the system in case possible failures
and bugs in a program make the ZFx86
uncontrollable. Whenever the watchdog timer

ZFx86 Data Book 1.0 Rev D

5.4.4. GPCS Events
See Table 5.14, ‘I/O and Memory Window
Mapper Events -- Index 66H,’ on page 414.

Page 424

5
is not reloaded during a pre programmed
interval it generates an event to notify the system of an error condition.
It works like this: The first watchdog timer is
initialized to a 16-bit time-out value through
registers 0Ch and 0Dh. After enabling through
control register (10h) it starts the countdown to
zero. The first watchdog timer can be reloaded
to an initial value by writing into control register (10h) or asserting the watchdog external
control pin on ZFx86 (WDI).
Whenever the first watchdog is not reloaded
during the time-out value it generates an event
to notify the system of an error condition and
outputs the logical “1” to a watchdog output

pin on ZFx86 (WDO). The notification event
can be routed to NMI, SMI, SCI or it can reset
the system immediately. The watchdog in ZFL
consists of two timers - WD#1 and WD#2.
Both timers are driven by 32 KHz clock. The
maximum period for WD#1 is 2 seconds and
for WD#2 7.2 ms. After WD#1 has expired it
can generate NMI, SMI, SCI or RESET and
start timer WD#2.
The second watchdog timer 8-bit time-out
value is initialized through register 0Eh and
starts counting down after WD#1 time-out.
When the WD#2 counter reaches zero, it will
unconditionally cause system reset.

DMX

NMI
SCI
SMI
RESET
WD0

WDI

WD#1
16-bit counter
2 sec. max

WD#2
8-bit counter
7.2 ms max

RESET

32 KHz
Figure 5-4 Watchdog Block Diagram

There is a WDO and WDI pin -- the WDI can
be programmed to reload WD#1. If you toggle
WDI (falling or rising) you can prevent the WD
from ever expiring. The benefit of this is that
so long as an external square wave is coming
in, the WD never expires. You are thus using
an EXTERNAL way of keeping the ZFx86
from resetting -- you are watching for an external “dead man” switch.

nect WDO to WDI with an OR gate or AND
gate to that external signal.
If you set it up this way, then you set wdo-1 to
generate event 1 pulse before expiring. If you
did not do this, it would expire. See wdo-1 in
Table 5.6 "Memory Window “N” Base Low Bits 15:12 (nibble 3)" on page 411

To do this, you need to have an outside event
generator. Let’s assume that all you have is a
logic signal which shows you if the external
system is working or not. You can then con-

ZFx86 Data Book 1.0 Rev D

Page 425

5
5.5.1. Watchdog Registers

0C

Watchdog 1 Count Low Byte -- (0CH)

Watchdog 1 Count High Byte -- (0DH)

0E

Watchdog 2 Count Value -- (0EH)

Watchdog Reset Pulse Length -- (0FH)

10

Watchdog Control Low -- (10H)

Watchdog Control High -- (11H)

12

Watchdog Status -- (12H)

W/D

Table 5.20 ZF-Logic Index for the Watchdog Timers

Table 5.21 Watchdog 1 Count Low Byte -- Index 0CH
Bit

7

6

5

4

Function

3

2

1

0

1

0

Watchdog 1 count low byte

Default

0

R/W

R/W

Table 5.22 Watchdog 1 Count High Byte -- Index 0DH
Bit

7

Function

6

5

4

3

2

Watchdog 1 Count High Byte

Default

0

R/W

R/W

Example: This example illustrates reading the
counter as a single 16-bit register, and writing
back an incremented value:
MOV AL, 0CH
MOV DX, 218H
OUT DX, AL
MOV
IN
INC
OUT

DX, 21AH
AX, DX
; Get Counter Value
DX
; Increment Data
DX, AX
; Write Back

ZFx86 Data Book 1.0 Rev D

Page 426

5
Table 5.23 Watchdog Generated Reset Pulse Length -- Index 0FH
Bit

7

6

5

Function

4

3

2

1

0

Reset Pulse Length

Default

0

R/W

R/W

Programming Notes: When WD#1 is programmed to cause system reset or when WD#2 resets the system, this register is used to determine the number of 32kHz ticks to hold the system reset signal low.

Table 5.24 Watchdog Control Low -- Index 10H
Bit

7

Function
Default
R/W

Bit

6

5

4

3

reserved

wd2 load

wd1 load

reserved

0

0

0

0

0

0

R/O

R/W

R/W

R/O

R/W

R/W

Name

7:6

Reserved

5

wd2 load

2

1

0

wd2 enable wd1 enable

Function
Reload WD#2 counter.
Active event for this bit is transition from 0 to 1

4

wd1 load

3:2

Reserved

Reload WD#1 counter.
Active event for this bit is transition from 0 to 1

1

wd2 enable

Enable WD#2
0=
1=

0

wd1 enable

Enable WD#1
0=
1=

ZFx86 Data Book 1.0 Rev D

WD#2 is disabled
WD#2 is enabled
WD#1 is disabled
WD#1 is enabled

Page 427

5
Table 5.25 Watchdog Control High -- Index 11H
Bit
Function
Default
R/W

Bit

7

6

5

4

3

2

1

0

reserved

wdi_en

wdo_-1

wdi edge

wd1 reset

wd1

wd1 NMI

wd1 SCI

SMI
0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Name

7

Reserved

6

wdi_en

Function
Enable the assertion of WDI input pin on ZFx86 to reload the watchdog 1 counter
0=
1=

5

wdo_-1

Create output on WDO output pin on ZFx86 at WD#1 time-out or one 32kHz clock
tick before
0=
1=

4

wdi edge

wd1 reset

wd1 SMI

wd1 NMI

wd1 SCI

WD#1 will not generate NMI on time-out
WD#1 generates NMI on time-out

WD#1 generates SCI on time-out
0=
1=

ZFx86 Data Book 1.0 Rev D

WD#1 will not generate SMI
WD#1 generates SMI on time-out

WD#1 generates NMI on time-out
0=
1=

0

WD#1 will not generate system reset
WD#1 will generate system reset on time-out

WD#1 generates SMI on time-out
0=
1=

1

WDI is asserted on 0->1 transition
WDI is asserted on 1->0 transition

WD#1 generates System Reset on time-out
0=
1=

2

WDO signal will be set high on WD#1 expiration
WDO signal is set high one clock tick before WD#1 expires. WD#1 events
will always occur at WD#1 time-out and are not affected of wdo_-1 bit setting. This feature allows automatic reload of WD#1 when WDO is wired to
WDI.

Active front of WDI input
0=
1=

3

WDI input ignored
WDI assertion reloads watchdog 1 counter

WD#1 will not generate SCI on time-out
WD#1 generates SCI on time-out

Page 428

5
Table 5.26 Watchdog Status -- Index 12H
Bit
Function
Default
R/W

7

6

5

4

3

2

1

0

wd1_gn

wd1_gc

wd1_gs

wd1 reset

wd2 reset

wd1_ev

reserved

reserved

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/O

R/O

Bit

Name

7

wd1_gn

Function
WD#1 generated NMI
0: WD#1 did not generate NMI
1: WD#1 did generate NMI

6

wd1_gc

WD#1 generated SCI
0: WD#1 did not generate SCI
1: WD#1 did generate SCI

5

wd1_gs

WD#1 generated SMI
0: WD#1 did not generate SMI
1: WD#1 did generate SMI

4

wd1 reset

WD#1 caused system reset
0: WD#1 did not reset the system
1: WD#1 did reset the system

3

wd2 reset

WD#2 caused system reset
0: WD#2 did not reset the system
1: WD#2 did reset the system

2

wd1_ev

WDI input pin asserted
0: WDI input has not been asserted
1: WDI input has been asserted

1:0

Reserved

Programming Notes: This register is set each time any of the watchdog events occurs. The register is NOT reset by
POR (Power On Reset) signal of ZFx86. The register can be cleared by writing anything into it. Any write to watchdog
status register (12h) will reset all the register bits to default values (00h).

ZFx86 Data Book 1.0 Rev D

Page 429

5
5.6. PWM generator
The PWM (Pulse Width Modulation) output
may be used to create DC control voltage for
an LCD backlight or any other device that
requires this feature. The conversion is done
by integrating variable duty cycle signal externally. At higher frequencies it may be used to
control external transformer for DC/DC conversion.
The clock signal derives the first timer. This
16-bit timer (prescaler) sets PWM period. The
input clock can be set to the (generally) 8MHz
ISA bus clock (see "ISACLK_N" on page 183)
or 32kHz clock. The prescaler resets the PWM
output to low and clocks second 8-bit timer

32kHz/8MHz

16-bit Prescaler

what starts counting from zero. When it
reaches the reference count given in 8-bit
PWM duty cycle register (06h), the comparator sets PWM output value to high. This process repeats forever. By changing the
comparator reference value it is possible to
generate different duty cycles. From the control register it is also possible to control the
signal value on PWM output pin directly.
The precision is 1/(2^8)=1/256 or approximately 0.5%
The pulse width generator (PWM) generator is
controlled using four 8-bit registers in ZFL.

PWM Out

8-bit counter
Comparator

16-PWM duty cycle value

Figure 5-5 PWM Control Unit

Table 5.27 ZF-Logic Index for the PWM Generator
PWM Prescaler Low Byte -- (04H)

06

PWM duty cycle -- (06H)

08

PWM I/O Control -- (08H)

0A

PWM Read Output -- (0AH)

ZFx86 Data Book 1.0 Rev D

PWM Prescaler High Byte - (05H)

PWM

04

Page 430

5
Table 5.28 PWM Prescaler Low Byte - Index 04H
Bit

7

6

5

4

Function

3

2

1

0

PWM Master Prescaler Low Byte

Default

0

R/W

R/W

16-bit PWM prescaler divisor word low byte. Divides ISACLK_N or 32kHz input clock selected at PWM control register. Actual divisor is 16-bit PWM divisor word (combined of registers 04h and 05h) + 1

Table 5.29 PWM Prescaler High Byte - Index 05h
Bit

7

6

5

Function

4

3

2

1

0

PWM Master Prescaler High Byte

Default

0

R/W

R/W

16-bit PWM prescaler divisor word high byte. Divides ISACLK_N or 32kHz input clock selected at PWM control register. Actual divisor is 16-bit PWM divisor word (combined of registers 04h and 05h) + 1

Table 5.30 PWM duty cycle - Index 06h
Bit

7

6

5

Function
Default
R/W

4

3

2

1

0

This is the duty cycle of the PWM
0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Programming Notes: This sets the% of the cycle to be low.
0 = 100%
255 = 0%

PWM period defined by
registers 04h, 05h and 08h

% from cycle to be LOW
defined by register 06h

Figure 5-6 PWM Period and Duty Cycle

ZFx86 Data Book 1.0 Rev D

Page 431

5
Table 5.31 PWM I/O Control -- Index 08H
Bit

7

6

5

4

enable
direct

direct output

reserved

0

0

0

0

0

0

R/O

R/W

R/W

R/O

R/W

R/W

reserved

Function
Default
R/W

Bit

3

2

1

0

slow-fast

Enable
PWM

clksrc

Name

Function

7:6

Reserved

5

enable direct

Enables direct control of PWM output by bit 4
0: PWM drives the output
1: Bit 4 of register 08H drives the PWM output pin

4

direct output

The value of PWM output when bit of register 08h is set to 1

3:2

Reserved

1

slow-fast (clksrc)

Selects the PWM prescaler input clock
1: PWM is clocked by 32kHz clock
0: PWM is clocked by 8 MHz ISA clock (ISACLK_N)

0

Enable/Disable PWM

Enable/Disable PWM output
0: PWM is disabled
1: PWM is enabled

Table 5.32 PWM Read Output -- Index 0AH
Bit

7

6

Function
Default
R/W

Bit

5

4

Reserved

0

pwmval

ZFx86 Data Book 1.0 Rev D

2

1

0

reserved

pwmval

0

0

R/O

R/O

Name

7:1

3

Function

Value at PWM output pin

Page 432

5
Example:
; initialize PWM as:
; prescaler = 0
; duty cycle = 50%
; ISA clocked, enabled
;
; This setup will cause PWM generator to produce output frequency
; 4.078kHz
;

0124
0126
0129
012A
012D
0130

B0
BA
EE
BA
B8
EF

04
0218

0131
0133
0136
0137
013A
013C

B0
BA
EE
BA
B0
EE

06
0218

013D
013F
0142
0143
0146
0148

B0
BA
EE
BA
B0
EE

08
0218

021A
0000

0219
80

0219
03

ZFLWritew
mov
mov
out
mov
mov
out

04h,0
al,04h
dx,ZFLINDEX
dx,al
dx,ZFLDATA16
ax,0
dx,ax

ZFLWriteb
mov
mov
out
mov
mov
out

06h,80h
al,06h
dx,ZFLINDEX
dx,al
dx,ZFLDATA8
al,80h
dx,al

ZFLWriteb
mov
mov
out
mov
mov
out

08h,03
al,08h
dx,ZFLINDEX
dx,al
dx,ZFLDATA8
al,03
dx,al

; Now change duty cycle to 90%. As result of this PWM output
; waveform will be "mostly" HIGH

0149
014B
014E
014F
0152
0154

B0
BA
EE
BA
B0
EE

06
0218
0219
E8

ZFx86 Data Book 1.0 Rev D

ZFLWriteb
mov
mov
out
mov
mov
out

06h,0E8h
al,06h
dx,ZFLINDEX
dx,al
dx,ZFLDATA8
al,0E8h
dx,al

Page 433

5
5.7. Z-tag Overview
The Z-tag interface is used to read data for
programming FLASH devices in system maintenance mode. Maintenance mode is entered
from the internal boot ROM.
• Improves speed over using serial interface
• Frees legacy ports from system FLASH
update function
• Creates a dedicated and simple interface
for system upgrading

The Z-tag interface shares pins with FDD bus.
The Floppy device will ignore Z-tag data when
MTR0 and SEL0 signals are inactive. These
lines are probed by the Z-tag dongle to enable
the output buffers. Shared floppy lines in Z-tag
mode are multiplexed to ZFL block. Four
inputs and four outputs are used to connect
external flash updating device (Z-tag dongle or
other source) to the ZFx86. These lines can
be accessed through dedicated register in
ZFL.

System FDD Lines

FDD Lines

FDD MUX

Z-tag

Figure 5-7 Dongle (w/o Cover)

.
Table 5.33 ZF-Logic Index for the Z-tag
5E

Z-tag Data Write Register (5EH)

60

Z-tag Data Read Register (60H)

Z-tag

...
7C

Z-tag control register (7CH)

Z-tag Sequencer Divisor Register (7DH)

7E

Z-tag Sequencer Waveform (7EH)

Z-tag Sequencer Strobe Points (7FH)

80

Z-tag Sequencer Data (80H)

Z-tag Sequencer Status (81H)

ZFx86 Data Book 1.0 Rev D

Z-tag

Page 434

5
Table 5.34 Z-tag Data Write Register -- Index 5EH
Bit

7

6

Function
Default
R/W

Bit

5

4

3

2

1

0

reserved

write hdsel

write data

write step

write dir

0

0

0

0

0

R/O

R/W

R/W

R/W

R/W

Name

Function

7:4

Reserved

3

write hdsel

controls the HDSEL line on FDD interface

2

write data

controls the DATA line on FDD interface

1

write step

controls the STEP line on FDD interface

0

write dir

controls the DIR line on FDD interface

Programming Notes: These bits control FDD lines if ZT_CTRL (7CH) reg bit 4 is 1

Table 5.35 Z-tag Data Read Register -- Index 60H
Bit

7

Function

6
reserved

Default

5

4

3

2

1

0

read drv0

read mtr0

read disc

read rdata

read wrprt

read trk0

R/O

R/O

R/O

R/O

R/O

R/O

0

R/W

R/O

Bit

Name

Function

7:6

Reserved

5

read drv0

Monitors DRV0 line on FDD interface

4

read mtr0

Monitors MTR0 line on FDD interface

3

read dskch

Monitors DSKCH line on FDD interface

2

read rdata

Monitors RDATA line on FDD interface

1

read wrprt

Monitors WRPRT line on FDD interface

0

read trk0

Monitors TRK0 line on FDD interface

ZFx86 Data Book 1.0 Rev D

Page 435

5
Table 5.36 Z-tag Control Register -- Index 7CH
Bit

7

6

Function
Default
R/W

Bit

5

4

3

2

1

0

reserved

Z-tag
enable

accel
enable

snoop
ahead

reg select

0

0

0

0

0

R/O

R/W

R/W

R/W

R/W

1

0

1

0

Name

Function

7:4

Reserved

3

Z-tag enable

Muxes the FDD lines
0: normal operation
1: Z-tag signals on FDD lines

2

Accel enable

0: Z-tag normal operation
1: Z-tag accelerator active

1

Snoop ahead

0: Clear ready flag on accel reg read
1: Do not change the ready flag on accel read

0

Reg select

0: Select the output buffer for read
1: Select the accumulator register for read

Table 5.37 Z-tag Sequencer Divisor -- Index 7DH
Bit

7

6

5

4

Function

3

2

ISA Divider

Default

0

R/W

R/W

Programming Notes: ISA Divider Divides the ISA clock for sequencer input

Table 5.38 Z-tag Sequencer Waveform -- Index 7EH
Bit

7

Function
Default
R/W

6

5

4

3

2

Waveform programming register
0
R/W

Programming Notes: This register is clocked with ISA clock divided by DIVIDER register. The cyclic sequencer outputs the bits as the clock signal to Z-tag interface starting from lower bit.

ZFx86 Data Book 1.0 Rev D

Page 436

5
Table 5.39 Z-tag Sequencer Strobe Points -- Index 7FH
Bit

7

6

5

Function

4

3

2

1

0

1

0

Z-tag strobe

Default

0

R/W

R/W

Programming Notes: 0->1 transition marks the data strobe point in Z-tag accelerator

Table 5.40 Z-tag Sequencer Data -- Index 80H
Bit

7

6

5

Function

2

0

R/W

R/O

data is the data byte from Z-tag sequencer.

The Z-tag interface has two operating modes
selected from control register:
1. Direct software control of IO pins.
The CPU is responsible for checking the status and data bits and controlling the clock.
Slow because single bit input demands at
least 4 ISA IO instructions.
2. Internal FSM
Serial input device with bit-level handshaking
and waveform control. This device collects the
serial data from the Dongle and stores it into
read buffer. It waits for acknowledge from
Dongle and when the read buffer is full. With
standard 8 MHz input clock it can read as
much as 4 Mbit/sec.
For additional information on Z-tag, see Chapter 6. Z-tag, BUR, and The ZFiX Console.

ZFx86 Data Book 1.0 Rev D

3

sequencer data

Default

Programming Notes: The sequencer

4

5.8. Boot Parameters Register
When power-on reset is asserted 24 signals
are read into the Boot Parameters Register
(configuration register) from the ISA Address
Bus. External hardware is responsible to place
data on the external ISA Address bus during
the time that the power on reset line is
asserted. Typically the user will provide this
data via DIP switches or pull-up/pull-downs.
These 24 inputs are stored into the internal
power-up Boot Parameters Register (configuration register).
This 24 bit register is loaded off the ISA
address pins when the ZFx86 is reset. During
normal operation, these pins are output only
but during reset, they are tri-state and allow an
external device to drive them. During reset,
these pins are also driven by weak internal
pull-ups or pull-downs. If a pin is not driven
externally during reset, then these pull the pin
to the indicated default. In a typical design,
the DIP switches will be connected such that
an ON is a pull-up if the default is low, and that
an OFF is a pull-down if the default is high.

Page 437

5
When the ZFx86 receives the reset pulse, it
samples the ISA address bus. The 24 bits
read in are stored in the boot parameters register.
The ISA address bus (pins SA0-SA23) is tristated during the reset pulse. It contains onchip weak (about 20K) pull-ups and pulldowns to set the default state of the bootstrap
register. To override this, we use a 2.2K pullup or pull down and a DIP switch or jumper.
Once the reset pulse is done, the ISA bus has
sufficient drive to overcome the effect of these
2.2K resistors.

the data in the bootstrap registers.
In a typical design, DIP switches or jumpers
are used (with appropriate resistors) set to the
bits in the BootStrap Register.

DIP SWS

DIP SWS

These bits are latched on reset and are read
only.
Example:

Thus, conceptually the ISA address bus has
three “modes”: (1) the weak on-chip pullups/pull-downs which are operative during the
tri-state; (2) the 2.2K pull-ups/pull-downs
which may be activated via DIP switches; and
(3) the normal execution time mode where the
drive of the ISA address bus will override
these resistors.

; read bootstrap registers as 32-bit value into
EAX

Since the Boot Parameters Register is read
only, the values sampled on the ISA bus on
the trailing edge of reset are “permanent” until
the next hardware reset. Software can read
the data which is latched, but cannot change

0102

B0 62 mov

0104

BA 0218mov dx,

ZFLINDEX

0107

EE

dx,

al

0108

BA 021Ain

eax,

dx

010D

66| 25 00FFFFFFandeax,0FFFFFFh

out

al,

62h

Table 5.41 ZF-Logic Index for the Boot Parameters Register
62

Bootstrap Bits 7-0 (62H)

64

Bootstrap Bits 23-16 (64H)

Bootstrap Bits 15-8 (63H)

Table 5.42 Composite BootStrap Register Map
ISA
BIT

ZFL
Index

BS
Bit

0-3

62H

0-3

4

62H

4

Name

Default

Function

User Defined

0

User Defined

Reserved

0

South Bridge scan enableda.

BIOS / BUR Mapping to
ZFx86 I/O Control
Register (or notes)

1 = enable scan in operational mode.

ZFx86 Data Book 1.0 Rev D

Page 438

5
Table 5.42 Composite BootStrap Register Map (cont.)
ISA
BIT

ZFL
Index

BS
Bit

5

62H

5

6

62H

6

Name

Default

14 Mhz clock
source

0

32 KHz

0

Function
14MHz Clock Source
If 1, derive from 48Mhz. If 0, use
mhz14_c pin. [AF16]
32KHz Clock Source
If 1, derive from 48MHz. If 0, use
32KHZC [AF01]

7

62H

7

Reserved

1

BIOS / BUR Mapping to
ZFx86 I/O Control
Register (or notes)
See "IO_EXT_CLK_14M"
on page 245

See "IO_RTC_32K" on
page 244

486 DLL modea
1 = DLL mode enabled

8

63H

0

Reserved

1

486 raw clock modea.
1 = raw clock disable.

9

63H

1

3rd PCI
Request

0

Third PCI Request/Grant
1 = drq1 = req2_n and
dack1_n = gnt2_n

10

63H

2

Reserved

0

SIO Test Mode a.

11

63H

3

Reserved

1

Internal / External BUR Sourcea.
0 = External BUR
1 = Internal BUR

12

13

63H

63H

4

5

ISA Boot ROM
Width

1

Reserved

0

0 = 16 bit
1 = 8 bit

14

6

1

15

7

0

16

64H

17

18

0

2

11

00 - Sys Clk * 1
01 - Sys Clk * 2
11 - Sys Clk * 3 (default)
10 - Sys Clk * 4

FPCI divide

0

Frontside PCI Clock Divide.
0- SysClk
1 - SysClk / 2.
Note: SYSCLK_C is pin A20

ZFx86 Data Book 1.0 Rev D

External BUR uses GPIO0
as chip select.b

This is ignored for External
BUR (Bit 11).

CPU Delaya.

CLK MODE

1

64H

ISA Boot ROM Width

Shared I/O Pins switched
to DMA or PCI. See
5.8.1.1. "Multiplexing of
Pins A14 - B14" on page
440.

Note: Frontside is the on
chip PCI devices such as
the IDE controller and the
USB controller. See ZFx86
Fail-Safe PC-on-a-Chip
Block Diagram.

Page 439

5
Table 5.42 Composite BootStrap Register Map (cont.)
ISA
BIT

ZFL
Index

BS
Bit

19

64H

3

Name
BPCI divide

Default
0

Function
Backside PCI Clock Divide.
0- SysClk
1 - SysClk / 2.
Note: No effect if bit 20 is 0

20

64H

4

BPCI Select

1

BIOS / BUR Mapping to
ZFx86 I/O Control
Register (or notes)
Note: Backside PCI is the
slots or off-chip PCI
devices. See ZFx86 FailSafe PC-on-a-Chip Block
Diagram.

Backside PCI Clock Select.
0 - External clock.
1- Internal clock.

21

64H

5

Reserved

0

0 = USB normal operationa.
1 = USB test mode

22

64H

6

Reserved

1

ZF-Logic Enable. a.
Disables

23

64H

7

Z-tag enable

0

allc

ZF-Logic if low.

See "IO_ZT_EN" on page
245

Causes BUR Boot. Enables the
See "IO_ZFL_EN" on
Z-tag Interface and BUR if high. See page 245
5.10. "BUR Base Register" on page
445

a. This is a reserved bit used in testing. It should be left in its default state in user-designed systems.
b. If you select BUR boot (BS23) and external BUR (BS11) - in that case GPIO0 becomes the chip select for the external
BUR. BS12 is ignored in this case, and the width of the external ROM/FLASH is forced to 8-bits. External BUR allows ZF
to produce custom BUR chips for special applications.
c. When the ZF Logic is disabled, the MEM_CS* pins remain active.

5.8.1. Special Notes of Interest
The bootstrap registers or boot parameters
register, as it is sometimes called, highlights a
number of options and points of interest.

decision was made to share one set of I/O
pins (A14 and B14 - see 8.2. "Pin Descriptions
(Sorted by Pin)" on page 545) between the following functions:
1) DMA Request/Acknowledge #1

5.8.1.1. Multiplexing of Pins A14 - B14
While designing the ZFx86 “System on a
Chip”, every attempt was made to include all
of the standard features and services used by
current PCs, plus as many extras as we could
squeeze in. In order to accomplish this, a few
trade-offs had to be made. The number of
available I/O pins on the ZFx86 do not allow
all functions to operate simultaneously. We
assumed that designers would tend to user
either PCI or ISA devices, but not a large number of both types on the same board. The

ZFx86 Data Book 1.0 Rev D

These signals are used (primarily) by ISA
cards. Specifically, ISA Sound Boards tend to
use these as one of the default DMA channels. It is often possible to select a different
DMA channel, and avoid using these signals.
2) PCI Request/Grant on Slot #3
These signals are needed for any card
installed into the third PCI slot. The ZFx86
Integrated Development System, and any
other design built around the ZFx86 Chip, can
use either of these sets of signals, but only

Page 440

5
ONE of the two functions can be used on a
given board.
A more detailed disussion of this occurs in the
Quick Start Guide for the Integrated Development System, where BS9 is changed in conjunciton with another jumper to route pins
A14-B14 to their appropriate ISA or PCI destination.

5.8.2. Design Example
Table 5.43 Sample DIP Switch Settings
SW

Function

1

ON - USER DEFINED

2

ON - USER DEFINED

3

ON - USER DEFINED

4

ON - USER DEFINED

5

ON - EXT ROM when Z-tag enableda

6

System Clock Speed

7

System Clock Speed

8

ON - BUR Boot (and thus Z-tag enabled)
a. This bit should NOT be used in real designs. It is for
testing only.

A sample hardware design is shown below.
Note that DIP Switch 8 controls SA23 (Boot
Parameters Register Bit 23). When the dongle
is plugged in to the board, the dongle connects CLK to ACK and also pulls up SA23.
See 6.3.2. "Z-tag Data Transfer Protocol" on
page 460.
Compare this table (and the drawing below)
with the Boot Parameters Register. For example, note that SW 6-7 go to SA16-17.

ZFx86 Data Book 1.0 Rev D

Page 441

5

Note: This schematic is a sample. Refer to ZF’s reference designs for
a "real world" DIP switch application.

Figure 5-8 Sample DIP Switch Schematic

ISA BIT

ZFL
Index

BS
Bit

23

64H

7

Name
Boot from BUR
(sometimes called
Z-tag_EN)

Default
0

Function
Boot from BUR
1 = Boot from BUR
0 = Boot from Flash

ZFx86 Data Book 1.0 Rev D

Page 442

5
NB IDX 11Ch
bits 5:3
SDRAMCLK_SKEW

SDRAM clock output pins
NB IDX 3FFHh bit 2
EN_STOP_SDRAM_CLK

NB IDX 3FFh
bit 3
EN_STOP_CORE_CLK

NB IDX 3FFh
bit 0
EN_STOP_CPU_CLK

BS@SA7
DLL/OLD

CPU

SUSP

SUSP
SUSP

DELAY

BS@SA17-16 (from register)
SysClk Multiplier

CPU
INTERFACE

CORE

BS@ SA8
RAWCLK

DLL

SUSP
MX

NB IDX 239H bits 14..0
NB IDX 239H bit 15
DATA_BUS_HOLD

SLEW
OLD

PCI INTERFACE

MX

HOLD
SDRAM
INTERFACE

φ1

North Bridge

∆

CORE
φ2

/2

BS@ SA18 (from register)
Frontside PCI Clock Divide.
0- SYSCLK, 1 - SYSCLK / 2

BS@ SA15…13
DLY= ∆(φ1 − φ2 )

SYSCLK [A20]
48 MHz

/2

CLK_48MHZ [AE15]

BS@ SA19 (from register)
Backside PCI Clock Divide.
0- SYSCLK , 1 - SYSCLK / 2.

/4

/1484
12 MHz

32.345 kHz

MUX

14.318 MHz
mhz14_c [AF16]

Mux2
ISA clock
ISACLK_C [AC02]
SB F0 offset 50h
bits 2:0
ISA clock divisor

8.33 MHz

/n

MUX
IDE
PCI
CORE

Mux1
USB
SIO

8254
TIMER

REFRESH
APM

32.768 kHz
32KHz [AF01]

MUX

GPIO4/14 MHz OUT

Omux2

MUX

RTC

PCI clock
CLK pin
U25

BS@SA20 (from Register)
Backside PCI Clock Select.
0 - External clock. 1- Internal clock.

+

MUX

South Bridge
Super I/O

RTC and CMOS backup battery
[AD03] VBAT

GPIO0/32kHz OUT

Omux1

(a)

(b)

(c)

(d)

(e)

(f)

(a)

GPIO4 pin [AF10]

(b)

Ioc2[7] IO_CLK_14M_OE

(c)

BS@SA5 / Ioc2[0] IO_EXT_CLK_14M

(d)

GPIO0 pin [AD12]

(e)

Ioc1[22] IO_CLK32K_OE

(f)

BS@SA6 32KHz Clock Source IO_RTC_32K

Figure 5-9 System Clocking and Control

5.8.3. Clocking and Control Overview
ZF Micro Solutions Inc. has not attempted to
hide some of the complexity of the chip; this
manual instead illustrates internal functionality
which is controlled by the bootstrap bits (even
though many of these bits are reserved for
testing).These bits rely on jumpers and/or DIP
switches which appear on the demonstration
and evaluation boards available from ZF. See
Chapter 9. Design Example - Evaluation 1
Board and the "Evaluation 1 Board Quick Start
Guide".

other control bits related to the SDRAM and
CPU core options.
The four clocks which may all be present are:
• CLK_48MHZ - USB Clock
• 32KHz - Refresh Generator / APM / RTC
• SYSCLK (typically 66 MHz)
• mhz14_c - Used for the 8254 PIT

In general, the chart above illustrates clocking
control bits, APM/suspend control bits, and

ZFx86 Data Book 1.0 Rev D

Page 443

5
5.8.3.1. Clocking Options

5.9. Data registers (F0H to FEH)

The ZFx86 has various clocking options.
These options represent different trade-offs
that the designer must investigate to come to
the best solution for the application being
considered. Essentially, the chip can be
clocked using as many as four clocks or as
few as one.

These 20 bytes of register space are used to
store the ZFx86 BIOS specific data.
• The first 5 registers are reset during cold
boot ( registers 68H to 71H).
• The second 5 keep their values
(registers 72H to 7BH).

Various combinations of bootstrap registers
allow the ZFx86 to be used with fewer clocks
in the system. Examples are shown in
"System Clocking" on page 447.

These registers do not interfere with other
device functions and are used by BIOS as a
scratch area.

68

Scratch Register 0 Low (68H)

Scratch Register 0 High (69H)

6A

Scratch Register 1 Low (6AH)

Scratch Register 1 High (6BH)

6C

Scratch Register 2 Low (6CH)

Scratch Register 2 High (6DH)

6E

Scratch Register 3 Low (6EH)

Scratch Register 3 High (6FH)

70

Scratch Register 4 Low (70H)

Scratch Register 4 High (71H)

72

Scratch Register 5 Low (72H)

Scratch Register 5 High (73H)

74

Scratch Register 6 Low (74H)

Scratch Register 6 High (75H)

76

Scratch Register 7 Low (76H)

Scratch Register 7 High (77H)

78

Scratch Register 8 Low (78H)

Scratch Register 8 High (79H)

7A

Scratch Register 9 Low (7AH)

Scratch Register 9 High (7BH)

Scratch Registers

Table 5.44 ZF-Logic Index for the Scratch Register

Table 5.45 Indices for Scratch Registers
Function

0

1

2

3

4

5

6

7

8

9

Description

Low

68H

6AH

6CH

6EH

70H

72H

74H

76H

78H

7AH Scratch Register “N” Low

High

69H

6BH

6DH

6FH

71H

73H

75H

77H

79H

7BH Scratch Register “N” High

Temporary Scratch Registers

ZFx86 Data Book 1.0 Rev D

Persistent Scratch Registers

Page 444

5
Table 5.46 Scratch Register “N” High or Low
Bit

7

6

5

4

Function

3

2

1

0

Temporary Data Register

Default

0

R/W

R/W

5.10. BUR Base Register
Table 5.47 ZF-Logic Index for BUR Base
Index

8-Bit Data at Index

8-Bit Data at Index + 1

56
58

BUR Base Low (57H)
BUR Base High (58H)

Table 5.48 BUR Base Bits 15-12
Bit
Function

7

6

5

4

3

2

1

0

d15

d14

d13

d12

fixed

fixed

fixed

fixed

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

N/A

N/A

N/A

N/A

Default
R/W

Bit

Name

Function

7:4

d15..d12

BUR base address bits 15..12

3-0

fixed

Fixed in Hardware

Programming Notes: The BUR base register defines the beginning address of the on-chip BUR software in system
memory space. Normally this register is initialized to zero and BUR does not appear anywhere in memory. However,
if BUR is requested by bootstrap at SA23 on system reset, the BUR base register is initialized to 000FC000H and
BUR becomes visible at BIOS ROM area.
Writing zero to that register instantly disables the BUR window.
The BUR is actually 12Kbyte software inside the chip, however the base register enables a 16K byte window for it.
Therefore, the actual data begins at BASE+4Kbyte.
The BUR base register is 32-bit register, accessible through 218h/21Ah. The middle two bytes can be accessed
through 8-bit accesses at 218h/219h

ZFx86 Data Book 1.0 Rev D

Page 445

5
Table 5.49 BUR Base Bits 23-16
Bit
Function

7

6

5

4

3

2

1

0

d23

d22

d21

d20

d19

d18

d17

d16

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default
R/W

Bit
7:0

Name

Function

d23-16

BUR base address bits 23..16

Programming Notes: .BUR base register are internally 32-bit register, that can be accessed through 218h/21Ah. The
bits 32..24 and 7..0 of the BUR base address register are fixed and can not be modified. The register is also accessible as 8-bit registers through 218h/219h.
Using the 32-bit access at 218h/21Ah allows to write the direct 32-bit value to a register BUR base address.

32-bit access through 218h/21Ah
8-bit access through 218h/219h 8-bit access through 218h/219h
+3
Fixed to 0

+2
BUR base bits 23..16

ZFx86 Data Book 1.0 Rev D

+1
BUR base bits 15..12

+0
Fixed to 0

IDX
56h

Page 446

5
5.11. System Clocking
Table 5.50 System Clocking
Functional block
System clock

Type

Pin

Name

Frequencies allowed

SYSCLK_C

1 to 66MHz a

Input

A20

Real-time clock

Crystal

AE01

32KHZ_C

32768Hz

Real-time clock

Crystal

AF01

32KHZC_C

32768Hz

8254 timer

Input

AC14

14MHz_C

14.318MHz b

Super-IO

Input

AE15

USB_48MHz_C

48MHz c

ISA bus

Output

AC02

ISACLK_C

Derived from the Backside PCI Clock

Backside PCI

Output

U25

PCICLK_C

SYSCLK or SYSCLK/2

SDRAM

Output

B22

SDRAM_CLK[0]

SYSCLK

SDRAM

Output

A22

SDRAM_CLK[1]

SYSCLK

SDRAM

Output

B21

SDRAM_CLK[2]

SYSCLK

SDRAM

Output

A21

SDRAM_CLK[3]

SYSCLK

Optional 32 KHz

Output

AD12

GPIO[0]d

Program GPIO[0] pin to output this frequency.

Optional 14 MHz

Output

AF10

GPIO[4]

d.

Program GPIO[4] pin to output this frequency.

a. The System clock drives the North bridge (including the SDRAM interface), the CPU and the South bridge PCI interface. It is possible to use any frequency up to 66 MHz. The CPU also has a multiplier that allows it to be clocked at 1, 2,
3 or 4 times the system clock.
b. 8254 timer (PIT, Programmable Interval Timer) clock drives the 8254 timer circuit. It provides the timer interrupt and
Legacy system time-base. If this clock is any other value than 14.318 MHz (ISA bus OSC signal) it is necessary to
reprogram PIT to create the correct time-base.
c. Super-IO clock synchronizes all Super-IO devices. It must be EXACTLY 48 MHz to create the correct USB and RS232
timings. It is possible to run ZFx86 from only this source.
d. See Table 4.8 "GPIO Interface Signals" on page 182, and see Figure 5-9 "System Clocking and Control" on page 443
(and the figures following in this section).

Various combinations of bootstrap registers
allow the ZFx86 to be used with fewer clocks
in the system.

Mode 1:

Mode 2:
Two clock sources: USB and Real Time
clocks.

• Compatible with legacy PC systems

• 14 MHz ISA clock derived from the USB
clock, this will generate a clocking error. It
also requires the Programmable Interval
Timer (PIT divider) to be changed.

• Most flexible in both speed, features, and
software

• PCI clocks need to be either 24MHz
(SYSCLK divided by two) or 48MHz.

• Most expensive HW cost

• Less expensive HW.

All clock sources present. System, Real Time,
USB and 8254 Timer clocks.

• No change to SW/HW

ZFx86 Data Book 1.0 Rev D

Page 447

5
Mode 3:

• Will lose the clock (Date and Time) if the
power is removed from the system.

One clock source: USB clock only with
GPIO[0] pin fed back to RTC. Connect the
USB clock input to the SYSCLK input.,

• Legacy SW/HW may need to be changed
if dependent on legacy timers.

• Incompatible with legacy PC systems.

• Least expensive HW solution.

Table 5.51 Formal Clock Names and Clocking Modes
Name

Reference

Nominal

Mode
1a

Mode 2

Mode 3

System Clock (generates PCI and
CPU Clock)

"SYSCLK_C [A20]" on page 450

33-66 MHz

yes

b

b.

Real Time Clock

‘32KHZC_C [AF01]’ on page 449

32KHz

yes

yes

c

USB Clock

‘USB_48MHz_C [AE15]’ on page 453

48 MHz

yes

yes

yes

8254 Timer

‘mhz_14c [AF16]’ on page 448

14 MHz

yes

d

d.

a. In mode 1 all clocks are present.
b. Drive both the USB Clock and the SYSCLK with a 48 MHz signal.,
c. Drive the 32KHz Real Time Clock with GPIO[0] output which is USB_48MHz/1484. See Figure 5-11 "32KHZC_C [AF01]
Clocking Control Circuitry" on page 450.
d. Get the 8254 Timer the USB Clock/4 or 12 MHz. See Figure 5-13 "USB_48MHz_C [AE15] Clocking Control Circuitry" on
page 453.

5.11.1. mhz_14c [AF16]
This clock generates the timer interrupt from
the 8254 PIT. The sources for this signal are
from mux2. The default is to use the 14.318
MHz input pin, but you can use an internally
generated 12 MHz clock by asserting either
IO_EXT_CLK_14M or SA5.The 12 MHz clock
comes from CLK_48MHz. Z which is a
reguired clock. See IO_EXT_CLK_14M on
page 245).
The output of Mux2 (14.318 or 12 MHz) may
be driven out on GPIO[4] . See
IO_CLK_14M_OE on page 245. 1
If you use the 12 MHz source, the input frequency to the 8254 PIT is lower, but it is possi1.

ble to compensate for it by using different
divisors in the PIT.
The clock input to the 8254 PIT drives all 3 PIT
channels. The clock input is divided by 12 (not
shown in the schematic).
The legacy PIT Channel 0 is used to create
refresh DMA cycles. As the memory controller
has moved to North Bridge this is obsolete.
The legacy PIT Channel 1 creates PC speaker
tones. The higher tones (10 KHz) differ by
(12/14 ) / 1000 = 0.8 mHz. The lower tones differ in µHz areas. This change is not noticeable
in a PC-Speaker.

In order to GPIO[4] to work as a clock output, you must program a "0" (or at least not program a "1" to the
GPIO[4] output pin. See Table 4.33 on page 233.

ZFx86 Data Book 1.0 Rev D

Page 448

5
The legacy PIT Channel 3 creates a timer
interrupt. by dividing the input signal by
0xFFFF. The legacy result is 18.206268 Hz or
54.926138 ms. In our case the timer runs at
1 µs therefore, the divisor must be 54926
(decimal) resulting in a frequency of

18.206313 Hz (54.926002 ms). This creates
an error of 2.47x10-4 % or one timer tick less
in 398014 ticks. If not corrected this produces
one second delay every four days.

48 MHz
CLK_48MHZ [AE15]

register)
k Divide.
SCLK / 2.

/4

/1484
12 MHz

32.345 kHz

MUX

14.318 MHz
mhz14_c [AF16] ?

Mux2

MUX
Mux1
8254
TIMER

REFRESH
APM

32.768 kHz
32KHz [AF01]

MUX

GPIO4/14 MHz OUT

Omux2

RTC

MUX

South Bridge
Super I/O

GPIO0/32kHz OUT

Omux1

(a)

(b)

(c)

(d)

(e)

(f)

(a)

GPIO4

(b)

Ioc2[7] IO_CLK_14M_OE

(c)

BS@SA5 / Ioc2[0] IO_EXT_CLK_14M

(d)

GPIO0

(e)

Ioc1[22] IO_CLK32K_OE

(f)

BS@SA6 32KHz Clock Source IO_RTC_32K

Figure 5-10 mhz_14c[AF16] Clocking Control Circuitry

5.11.2. 32KHZC_C [AF01]
This signal generates the refresh for SDRAM
and drives power management logic. It also
synchronizes the Watchdog timers and PWM
in ZF-logic. The two sources are from MUX1.
MUX1 selects between the 32.768 kHz input
in pin AF01, or the 48 MHz clock divided by
1484.
If you do not have a 32.768 kHz input, you
may use the 48 MHz clock. To use the 48MHz
clock to emulate the 32 KHz clock, assert SA6
using a DIP switch or resistor pack (see Table
5.42) or use software to assert IO_RTC_32K
(see page 244).

ZFx86 Data Book 1.0 Rev D

The real time clock 32 Khz crystal is required
to keep the clock running from battery. If time
loss is not important, then the RTC can be
driven from the internal 32 KHz by first outputting it to GPIO0 and then connecting it externally to crystal input pin.
If you do not have a 32.768 kHz clock, and
use the 48 MHz SIO clock divided by 1484,
you will get an RTC error of approximately
1.29% (32345 vs. 32768).
This 32 kHz (actual or derived) clock may be
driven out on GPIO[0] by setting
IO_CLK32K_OE (see page 244).

Page 449

5
If you are using the derived clock (the 48 MHz
clock /1484 option), please note that the 32
kHZ clock does not go to the RTC as there is
no interconnect along that pathway. In that
case, you can use GPIO0 in its 32kHz output
mode and run that output back around into the

32KHz input. That is somewhat roundabout,
but it works.
Compare 9.2.5. "Schematic Page 2 JP9 - Real
Time Clock (32KHz)" on page 595.

48 MHz
CLK_48MHZ [AE15]

BS@ SA19 (from register)
Backside PCI Clock Divide.
0- SYSCLK , 1 - SYSCLK / 2.

/4

/1484
12 MHz

32.345 kHz

MUX

14.318 MHz
mhz14_c [AF16]

Mux2

MUX
Mux1
USB
SIO

8254
TIMER

REFRESH
APM

32.768 kHz
32KHz [AF01]

MUX

GPIO4/14 MHz OUT

Omux2

RTC

GPIO0/32kHz OUT

Omux1

(a)

RTC and CMOS backup battery
[AD03] VBAT

+

MUX

South Bridge
Super I/O

(b)

(c)

(d)

(e)

(f)

(a)

GPIO4 pin [AF10]

(b)

Ioc2[7] IO_CLK_14M_OE

(c)

BS@SA5 / Ioc2[0] IO_EXT_CLK_14M

(d)

GPIO0 pin [AD12]

(e)

Ioc1[22] IO_CLK32K_OE

(f)

BS@SA6 32KHz Clock Source IO_RTC_32K

Figure 5-11 32KHZC_C [AF01] Clocking Control Circuitry

5.11.3. SYSCLK_C [A20]
This clock drives the Processor, the North
Bridge and both South Bridge PCI interfaces.
The signal has a single source - the SYSCLK
input pin. This clock is limited by following
considerations:
1.

The backside PCI bus implies a limit of
33 MHz for external devices. Although
internally it can be higher each external
device has to be checked separately. It
is possible to divide the SB PCI frequency separately by two and run the
SDRAM and CPU interfaces at a higher
frequency. A very key component of the
performance of the system is the clock

ZFx86 Data Book 1.0 Rev D

speed at which the SDRAM gets
accessed. Therefore, pushing the system clock up significantly enhances the
system performance.
2.

Front side PCI core frequency must
always be greater than or equal to the
backside PCI bus. It's recommended
not to exceed 33 MHz. This clock can
also be divided by two.

3.

The memory controller can run at a
maximum speed of 66 MHz.

These conditions are summarized in Table
5.52.

Page 450

5
Table 5.52 CORE frequencies (MHz).
Functional Block

Min. Freq.

Typical Freq.

1

33

33 (dependent on device)

1

33

33 (greater than or equal to the
backside PCI)

1

33

66

4 (4x)

99 (3x)

Backside PCI
Frontside PCI
SDRAM controller and CPU interface
CPU clock (multiplier)

Max. Freq.

132 (2x)

CPU clock

Suspend logic

The CPU clock can be programmed to be 1, 2,
3 or 4 times the SYSCLK. As the CPU core
will work only up to 100 MHz it is necessary to
select the proper multiplier based on the
selected SYSCLK frequency. Suspend logic is
present in the device to allow for stopping the
clock to the CPU if the North bridge receives a
suspend request from the South bridge.

The suspend logic allows the clocks to be
turned off when a suspend request is active.
The system suspend has the following hierarchy:
1.

South bridge suspend request -> North
bridge

2.

North bridge suspend request -> CPU

3.

CPU suspended

4.

CPU suspend acknowledge -> North
bridge

5.

North bridge suspended

6.

North bridge suspend acknowledge ->
South bridge

7.

South bridge suspended

SDRAM clock
SDRAM clock is exactly the same as SYSCLK
input. It has a skew control register, however,
all measurements taken during the development cycle indicate that the skew register
should be left at zero.

Front and Back side PCI clock
These clocks can be selected to run at the
system clock frequency or half the system
clock frequency.

ISA Clock
See ISACLK in Table 4.9 "Full ISA Interface"
on page 183. ISACLK is derived from PCICLK
and is typically programmed for 8.33MHz.
F0 Index 50h[2:0] is used to program the ISA
clock divisor. These bits determine the divisor
of the PCI clock used to make the 8.33MHz
ISA bus clock. See "F0 Index xxh: PCI Header
and Bridge Configuration Registers" on page
207.

ZFx86 Data Book 1.0 Rev D

Page 451

5
The wakeup follows the opposite scheme:
SB -> NB -> CPU. It is possible to switch off
the SDRAM, CPU and NB core clocks when
the system is suspended. The PCI and ISA
clocks will always run and the system will keep
the last value on the output pins when
suspended. The South bridge is responsible
for generating suspend and wakeup events.
NB IDX 11Ch
bits 5:3
SDRAMCLK_SKEW

SDRAM clock output pins
NB IDX 3FFHh bit 2
EN_STOP_SDRAM_CLK

NB IDX 3FFh
bit 3
EN_STOP_CORE_CLK

NB IDX 3FFh
bit 0
EN_STOP_CPU_CLK

BS@SA17-16 (from register)
SysClk Multiplier

BS@SA7
DLL/OLD

CPU

SUSP

SUSP
SUSP

DELAY

Refer to the South Bridge spec for a detailed
description of all possible wakeup events. The
CPU can suspend itself until the next interrupt
following HLT command. This must be
enabled in the CPU control register.

CPU
INTERFACE

CORE

BS@ SA8
RAWCLK

DLL

SUSP
MX

NB IDX 239H bits 14..0
NB IDX 239H bit 15
DATA_BUS_HOLD

SLEW
OLD

PCI INTERFACE

MX

HOLD
SDRAM
INTERFACE

φ1

North Bridge

∆

CORE
φ2

/2

BS@ SA18 (from register)
Frontside PCI Clock Divide.
0- SYSCLK, 1 - SYSCLK / 2

BS@ SA15…13
DLY= ∆(φ1 − φ2 )

SYSCLK [A20]
48 MHz

/2

CLK_48MHZ [AE15]

BS@ SA19 (from register)
Backside PCI Clock Divide.
0- SYSCLK , 1 - SYSCLK / 2.

/4

/1484
12 MHz

32.345 kHz

MUX

14.318 MHz
mhz14_c [AF16]

Mux2
ISA clock
ISACLK_C [AC02]
SB F0 offset 50h
bits 2:0
ISA clock divisor

8.33 MHz

/n

MUX
IDE

Mux1
USB
SIO

PCI
CORE

8254
TIMER

REFRESH
APM

32.768 kHz
32KHz [AF01]

MUX

GPIO4/14 MHz OUT

Omux2

MUX

RTC

PCI clock
CLK pin
U25

BS@SA20 (from Register)
Backside PCI Clock Select.
0 - External clock. 1- Internal clock.

+

MUX

South Bridge
Super I/O

RTC and CMOS backup battery
[AD03] VBAT

GPIO0/32kHz OUT

Omux1

(a)

(b)

(c)

(d)

(e)

(f)

(a)

GPIO4 pin [AF10]

(b)

Ioc2[7] IO_CLK_14M_OE

(c)

BS@SA5 / Ioc2[0] IO_EXT_CLK_14M

(d)

GPIO0 pin [AD12]

(e)

Ioc1[22] IO_CLK32K_OE

(f)

BS@SA6 32KHz Clock Source IO_RTC_32K

Figure 5-12 SYSCLK_C [A20] Clocking Control Circuitry

ZFx86 Data Book 1.0 Rev D

Page 452

5
5.11.4. USB_48MHz_C [AE15]

is therefore not reasonable to set the system
clock below 33 MHz when using it.

Note that the USB and SIO (Super I/O) get
their timing from a fixed 48 MHz clock and do
not depend from other clocks. However the
USB is a BUS master device and requires
certain bandwith to operate at high speeds. It

Note that when using only one clock for the
entire system, you need to provide this clock.
See ‘Mode 3:’ on page 448.

SYSCLK [A20]
48 MHz
CLK_48MHZ [AE15]

BS@ SA19 (from register)
Backside PCI Clock Divide.
0- SYSCLK , 1 - SYSCLK / 2.

/4

/1484
12 MHz

32.345 kHz

MUX

14.318 MHz
mhz14_c [AF16]

Mux2

MUX
Mux1
USB
SIO

8254
TIMER

REFRESH
APM

32.768 kHz
32KHz [AF01]

MUX

GPIO4/14 MHz OUT

Omux2

RTC

+

MUX

South Bridge
Super I/O

RTC and CMOS backup battery
[AD03] VBAT

GPIO0/32kHz OUT

Omux1

(a)

(b)

(c)

(d)

(e)

(f)

(a)

GPIO4 pin [AF10]

(b)

Ioc2[7] IO_CLK_14M_OE

(c)

BS@SA5 / Ioc2[0] IO_EXT_CLK_14M

(d)

GPIO0 pin [AD12]

(e)

Ioc1[22] IO_CLK32K_OE

(f)

BS@SA6 32KHz Clock Source IO_RTC_32K

Figure 5-13 USB_48MHz_C [AE15] Clocking Control Circuitry

ZFx86 Data Book 1.0 Rev D

Page 453

5
5.11.5. PCI Clocking
As an example, you could set SYSCLK to 66
MHz. Then use a clock multiplier of 2 to run
the CPU at 132 MHz. You can use SA18 to
control the frequency of the Frontside PCI
Bus. The frontside bus should be running at a
clock greater than or equal to the backside
PCI Bus. The frontside PCI clock controls the
internal IDE devices.

NB IDX 11Ch
bits 5:3
SDRAMCLK_SKEW

NB IDX 3FFh
bit 3
EN_STOP_CORE_CLK

NB IDX 3FFh
bit 0
EN_STOP_CPU_CLK

CPU
INTERFACE

CORE

NB IDX 3FFHh bit 2
EN_STOP_SDRAM_CLK

TO CPU

SUSP

SUSP
SUSP

DELAY

SDRAM clock output pins

If you use the internal IDE controllers, they are
validated at 33 MHz and thus the FrontSide
PCI bus should not be set to a speed higher
than that. In that case, you would enable both
/2 divisors and use 33 MHz for the FrontSide
and BackSide PCI Clocks. The PCI Core
circuitry inside of the South Bridge drives the
external PCI buses.

SUSP

NB IDX 239H bits 14..0

SLEW

NB IDX 239H bit 15
DATA_BUS_HOLD

HOLD

SYSCLK
PCI INTERFACE

SDRAM
INTERFACE

North Bridge
/2

BS@ SA18 (from register)
Frontside PCI Clock Divide.
0- SYSCLK, 1 - SYSCLK / 2

SYSCLK

frontside
PCI Clock

/2

BS@ SA19 (from register)
Backside PCI Clock Divide.
0- SYSCLK , 1 - SYSCLK / 2.

backside
PCI Clock
ISA clock
ISACLK_C [AC02]
SB F0 offset 50h
bits 2:0
ISA clock divisor

8.33 MHz

/n

IDE
PCI
CORE

USB
SIO

8254
TIMER

REFRESH
APM

MUX

RTC

PCI clock
CLK pin
U25

BS@SA20 (from Register)
Backside PCI Clock Select.
0 - External clock. 1- Internal clock.

+

South Bridge
Super I/O

RTC and CMOS backup battery
[AD03] VBAT

Figure 5-14 PCI Clocking Control Circuitry

ZFx86 Data Book 1.0 Rev D

Page 454

6
6. Z-tag, BUR, and The ZFiX Console
The ZFx86 introduces a solution to resolve the
situation created by having a high integration
CPU connected to flash device that has not
been initialized. During the manufacturing process the on board flash device must be initialized with the system startup code (BIOS)
and/or application software. This implies that
the ZFx86 chip is in a situation where there is
no boot code that can be read from the flash
device to allow the update. For that purpose,
the ZFx86 contains a special Boot Up ROM
(BUR), that when executed updates the flash
memory. The BUR contains the minimal code
necessary to read data into the ZFx86 chip. In
order to update the flash, flash component
specific software must also be downloaded
and executed. The connection between the
ZFx86 chip and the flash data source can be
made in two ways: by a ZF proprietary Z-tag
Dongle interface or by using a serial port.

6.1. Serial Port Connection
The serial connection utilizes the ZFx86
embedded standard COM1 (base address
0x3f8), allowing a remote PC with special host
software or a terminal to access the ZFx86
flash device and use the update process. This
solution can be used in ZFx86 applications
where the serial port is not hardwired to an
external device and access to the serial port is
physically possible.

6.2. Z-Tag Dongles
ZF provides two dongles types: PassThrough
and Memory

6.2.1. PassThrough Dongle
Use the ZFx86 PassThrough Dongle, supplied
with the ZFx86 IDS system, to make a physical connection from the PC running Z-tag
Manager to the target system.

ZFx86 Data Book 1.0 Rev D

The PassThrough Dongle contains three
LEDs (two green and one yellow) that indicate
power, busy, and status.

6.2.2. Memory Dongle
An optional ZFx86 “Memory" Dongle contains
256Kbytes of memory, two LEDs (green and
red) that indicate status, and two configuration
jumpers.
• Jumper JP1 sets write protection for the
Dongle’s onboard SEEPROM(s), when set
in position 2-3.
• Jumper JP2 enables PassThrough or
Normal operation mode. Jumpering
2-and-3 enables the Z-tag software
PassThrough mode, while jumpering
1-and-2 selects Normal Mode.
On hardware reset the ZFx86 samples the ISA
address bit 32 (bootstrap bit 32). If it is pulled
high, the BUR is executed. If it is pulled low,
the boot is attempted from the external Flash
memory.

Page 455

6
Note that the PassThrough dongle requires
a Printer cable connected from the Host
system to the Z-tag dongle for proper
operation.

6.2.3. Using the Dongle
Primarilary, you use the dongle and the Z-tag
Manager interface to download programs (like
BIOS) into your designs external Flash
memory. You need not power down the
design system to do this. You simply plug in
the Dongle, press the system’s reset button,
and wait for the BIOS to download. When it
completes, the Status LED appears solid
yellow.
Since you can replace the entire Flash
memory "almost instantly", you can also put
manufacturing test programs into the dongle,
load them, run them, and when finished simply
replace the memory. How is this done? The
on-chip BUR code has the capability to read
commands and data buckets from the
dongle – thus the intelligence to do the
transfer (similar to the ZFx86 FailSafe Mechanism) is already on chip.
Create the command set in a host PC running
32-bit Windows using a ZF Windows application called the Z-tag Manager. This application
allows you to drag and drop commands into a
command list. One of the commands contains
an embedded (attached) ROM image. The
ROM image is contained within a “basket” or
as an attachment.

ZFx86 Data Book 1.0 Rev D

6.2.3.1. Using the PassThrough Dongle
The PassThrough Dongle serves as an
adapter that connects the Host PC to your
target board. The Z-tag Manager software
manages the transfer of data directly to the
target system, emulating the behavior of the
SEEPROM(s) on the “Memory” Dongle but
from within the software. An advantage of
PassThrough dongle is that it handles largersized transfer images. Because the data is not
written into the Dongle’s SEEPROM(s), it
instead transfers directly to the target system’s
memory chip(s). See the Z-tag Manager
User’s Manual for more information.

6.2.3.2. Using the Memory Dongle
In the figure following, the Memory dongle is
being programmed while attached to the
Printer port of the host system. Then the
dongle is plugged into the target system, and
the program download into the ZFx86. See

Page 456

6
6.2.3.3. "Carrying the Command Set in The
Memory Dongle".

create a command set which includes carrying
a ROM image in a “basket”. This command
sequence, which includes a file image as part
of a transfer command, is stored in the
SEEPROM in the dongle. There are two
SEEPROMs on the Memory dongle, so you
can load a program with a total size of 256K
Bytes.
Note: If your program exceeds 256KBytes,
use the ZF designed PassThrough
dongle.

It is also possible to bypass the SEEPROMS
on the Memory dongle, and use it in
"PassThrough" mode where a cable from the
host system is connected to the dongle, and
the dongle is left plugged into the target board
Enable the PassThrough mode in software
using the Z-tag Manager.
• In “normal mode” you load the software
and command set directly into the dongle’s
SEEPROM memory chips.
• In “passthrough mode” you directly
connect the ZFx86 board (through the
dongle) to the host PC.
In both cases, you use the Z-tag manager to
transfer the information into the dongle or
throught the dongle directly to the target
board. The Z-tag manager is available at no
cost on the ZF web site and on the ZF CD
ROM.
Note: Additional Flash chip-specific software
is required to program a specific flash
device. See 6.7. "Flash Programming
Example" on page 470.

6.2.3.3. Carrying the Command Set in
The Memory Dongle
Connect the Memory dongle directly to the
printer port of a personal computer running
Windows. Then, using the Z-tag manager,

ZFx86 Data Book 1.0 Rev D

After using the Z-tag manager to load the
Memory dongle, unplug the dongle from your
PC printer port, and plug it into the ZFx86
board using the Z-tag header. Use a a
2514-6002UB 3M DIP-14 Header, or equivalent, to create the Z-tag header on your board.
If you have the dongle connected, the dongle
jumpers CLK to ACK and pulls up SA23.
When there is a reset-pulse with the Memory
dongle plugged in, the BUR starts [SA23] and
reads from the dongle. If the BUR finds no
Z-tag commands, it switchs to COM1 and
looks for Z-tag commands. If none are found
there, then the BUR starts the ZFix Console
on COM1.
Note: To use the BUR with no dongle
connected, use the DIP switch to pull up
SA23.
The speed of the transfer from the dongle into
the ZFx86 is limited by the software (that is,
the clock frequency) of the BUR. Typically we
would expect about 1.5 Mbps. The Z-tag interface is designed (from electrical waveform
point of view) to match the signals set of an
SEEPROM. That is, the BUR puts out a CLK
signal and reads in data. The basic protocol is
that when CLK goes high the SEEPROM (or
data source) puts new data on the data pin.
The data is read when CLK goes low. When
CLK goes high again the data source puts
fresh data on the data pin.

Page 457

6
This transfer method works just fine if the
Z-tag interface is directly connected to the
dongle or to an SEEPROM. However, if the
data source is a host computer and the dongle
is being used in PassThrough mode, then the
host computer (which is generating waveforms
on its printer port) may not be able to send the
data out quick enough. Therefore, another
signal was added called acknowledge (ACK).
When the dongle is plugged into the ZFx86 (in
the dongle “normal” mode of operation), the
dongle connects ACK to CLK.

6.2.3.4. Memory Dongle Jumper
Settings
The Memory dongle contains two jumpers
(see Table 6.1). The Mode jumper sets the
dongle to “PassThrough” mode or “normal”
mode.
• In “PassThrough” mode, the Z-tag interface simply passes through the dongle to
the printer connection; and you must run a
cable from the printer port on your
personal computer to the dongle (which

then passes through to the Z-tag interface). In this case, CLK is not hardwired to
ACK, allowing the host informationprovider to provide the ACK signal after it
places the data bit on the data pin. Thus,
in “PassThrough” mode, the host
computer watchs the CLK signal. When
CLK goes high, the host computer places
data on the data pin and raises the ACK
signal. When the BUR sees the ACK
signal go high, it drops CLK low and reads
the data. See 6.3.2. "Z-tag Data Transfer
Protocol" on page 460.
• In “normal” mode, the dongle directly
connects the CLK output to the ACK
output, allowing a maximum speed
transfer. Note that this is totally transparent
to the BUR, as BUR simply watches for
ACK and then drops CLK.
The second jumper on the Memory dongle
simply write protects the SEEPROMs on the
dongle.

Table 6.1 Memory Dongle Jumper Settings
Name

Location

Function

Comments

JP2

Dongle

PassThrough or Normal

Normal Connects CLK to ACK when Dongle Plugged In

JP1

Dongle

Protect SEEPROM’s memory

Bootstrap
SA23

Host Board Cause BUR Boot

Automatically set by Dongle — add DIP switch to provide
BUR boot w/o Dongle

CLK to ACK Host Board Reads Host Board SEEPROM Not Needed if SEEPROM in the Dongle is providing Data

6.2.3.5. Using the Memory Dongle in
“PassThrough” Mode
If you connect the host computer printer port
through a cable to the dongle which in turn is
plugged into the ZFx86 board, the operation is
similar in that you use the software Z-tag
manager to create your command set. When
you have created the command set, you can

ZFx86 Data Book 1.0 Rev D

then push the reset button on the ZFx86 board
and the BUR will read from the Z-tag interface
and get the same command set that you
would have loaded into the dongle. The
benefit of this mode is that you do not have to
program the SEEPROM(s) in the dongle, but
you can go directly to the desired operation.
See Table 6.2.

Page 458

6
Table 6.2 Z-tag and ZFiX Summary
Hardware

Software

Function

Dongle + Host

Mode

Z-tag Manager Windows Application

Programs the Dongle

Dongle + Board Normal

BUR

Read/execute commands from the dongle.

Host + Dongle + PassThrough Z-tag Manager Windows Application
Board
and BUR

Read/execute commands from the host.

Host + COM1

Z-tag Manager Windows Application
and BUR ZFix

Read and Execute Commands from the
Host.

Host + COM1

Windows Terminal Emulator and BUR
ZFix

Console Commands

6.3. Z-tag Manager Software
The Z-tag Manager program is a Windows
Application provided by ZF Linux Devices. The
program is used to create Z-tag command
sequences and transfer them to the dongle or
directly to the ZFx86 PC board. See the Z-tag
Manager Manual and also see Chapter 4 in
the ZFx86 Integrated Development System
Quick Start Guide.

6.3.1. Z-tag Summary
Z-tag is ZF proprietary connection interface
that does not interfere with any PC legacy
devices and can be accessed even if all of the
ZFx86 external peripheral interfaces are allocated. Physically, the Z-tag signals share the
pins with the FDD interface and appear when
the FDD MTR0 and DRV0 signals are not
active. The communication protocol is compatible with standard serial EEPROM devices,
thus allowing a direct connection of the serial
EEPROM to the Z-tag interface as a source
media. A second possibility for a data source
is a remote PC emulating the Z-tag protocol
with the parallel port. An adapter, called “the
dongle”, converts the FDD pins (generally a
header on the ZFx86 circuit board) to a Parallel Printer port interface. Z-tag Hardware Interface.

ZFx86 Data Book 1.0 Rev D

The Z-tag manufacturing connector layout has
the following pinout.
• CLK, RST and DATA are asynchronous
serial interface signals used on serial
EEPROM’s. The use of these signals can
be determined from the timing diagram of
the Z-tag communication protocol.
• ACK input to ZFx86 is a loopback from
CLK signal and is useful in situations
where the source media response speed
is unknown (i.e. emulation through PC
parallel interface). The ACK signal can be
either the CLK if the source media speed
is considered to be faster than the ZFx86
clocking (i.e. the data bit will be set fast
enough after the CLK rising edge appears)
or specially created after the data bit is set
by the source media.
• LED1 and LED2 are general purpose
output bits, that are used to provide
progress or status information when Boot
Up ROM is updating the flash.

Page 459

6
Table 6.3 Pins for the FLOPPY / Z-tag Logic
Pin

Pin Name

Pin Description

Cell Type

ORCAD Name

G03

DIR _N, Z-tagOut3

FLOPPY, Z-tag

m_fdc_p

DIR

F01

DR0_N

FLOPPY

m_fdc_p

DR0

J02

DSKCHG_N, Z-tagIn0

FLOPPY, Z-tag

m_fdc_p

DSKCHG

H01

HDSEL_N, Z-tagOut0

FLOPPY, Z-tag

m_fdc_p

HDSEL

F03

INDEX_N

FLOPPY

m_fdc_p

INDEX

F02

MTR0_N

FLOPPY

m_fdc_p

MTR0

J04

RDATA_N, Z-tagIn1

FLOPPY, Z-tag

m_fdc_p

RDATA

G04

STEP_N, Z-tagOut2

FLOPPY, Z-tag

m_fdc_p

STEP

H03

TRK0_N, Z-tagin3

FLOPPY, Z-tag

m_fdc_p

TRK0

G02

WDATA_N, Z-tagOut1

FLOPPY, Z-tag

m_fdc_p

WDATA

G01

WGATE_N

FLOPPY

m_fdc_p

WGATE

H02

WRPRT_N, Z-tagin2

FLOPPY, Z-tag

m_fdc_p

WRPRT

6.3.2. Z-tag Data Transfer Protocol
The hardware component of the data transfer
is illustrated by following the timing diagram
shown in Figure 6-1 "Data Transfer Protocol".
The data bit latching (see blue arrows) must
happen at a rising edge of the CLK signal. In
those cases when the source device speed is
unknown, the ACK signal is used to determine
when the bit is ready for reading at DATA input
(ACK=High) and when source device is ready
to accept the new rising edge of CLK signal
(ACK=Low).
RST

In this case, the source (host) device sets the
ACK signal when it has received the CLK
edge and latched the data to the DATA input.
The target (ZFx86) then reads a bit and resets
the CLK signal. After that, the target/ZFx86
starts reading the ACK signal again, waiting
for it to become low. When ACK goes low, the
cycle will be repeated for next data bit. The bit
stream following the reset deactivation is a
continuous 8-bit character bit stream with no
control bits, byte separators or addressing
information. The software must implement a
special packet header for determining the
addressing and other control information.

CLK

RST

DATA

CLK

ACK

DATA
BITS

1

0

0

1

0

1

ACK

Figure 6-1 Data Transfer Protocol
BITS

DATA input shown in figure Figure 6-2 "Data
Input".

ZFx86 Data Book 1.0 Rev D

1

0

0

1

0

1

Figure 6-2 Data Input

Page 460

6
6.3.3. Z-tag Port Interface
The Z-tag interface access is done via 8-bit ZF
registers Z-tag Data Write Register (5EH), and
Z-tag Data Read Register (60H). See ‘Z-Logic
Index for the Z-tag”

BIT

Name

Description

6.4. Z-tag Register Descriptions

7

Z-tagIn3

Z-tag in 3, (TRK0)

6.4.1. Z-tag Data (D1h)

6

Z-tagIn2

Z-tag in 2, (WRPRT)

Z-tag interface is used to update ROM devices
in BIOS upgrade mode. FDD interface signals
are connected to the Z-tag data register when
MTR0 and DRV0 are not asserted. FDD MUX
is controlled using a bit in Z-tag control register. This process is transparent to the user.

5

Z-tagIn1

Z-tag in 1, (RDATA)

4

Z-tagIn0

Z-tag in 0, (DSKCHG)

3

Z-tagOut3

Z-tag out 3, (DIR)

2

Z-tagOut2

Z-tag out 2, (STEP)

1

Z-tagOut1

Z-tag out 1, (WDATA)

0

Z-tagOut0

Z-tag out 0, (HDSEL)

The Z-tag has four inputs and four outputs.
Each Z-tag line is connected to FDD line. In
Table 6.4 "Z-tag Data Lines" the FDD lines are
shown in parenthesis.

Table 6.4 Z-tag Data Lines

Table 6.5 Z-Logic Index for the Z-tag
5E

Z-tag Data Write Register (5EH)

Z-tag

60

Z-tag Data Read Register (60H)

7C

Z-tag control register (7CH)

Z-tag Sequencer Divisor Register (7DH)

7E

Z-tag Sequencer Waveform (7EH)

Z-tag Sequencer Strobe Points (7FH)

80

Z-tag Sequencer Data (80H)

Z-tag Sequencer Status (81H)

Z-tag

6.4.2. Z-tag Control (7Ch)
The Z-tag enable bit of the Z-tag Control Register switches the FDD pins between FDD and
Z-tag. These pins are listed in Table 6.4 "Z-tag
Data Lines" on page 461. The four FDD output
signals are taken from Z-tag data write register. The FDD WGATE, MTR0 and DRV0 signal
are put to logical '1'. This ensures that the
FDD is not interfering with the Z-tag data.

System FDD Lines

FDD MUX

FDD Lines

Z-tag

ZFx86 Data Book 1.0 Rev D

Page 461

6
Table 6.6 Z-tag Control Register -- Index 7CH
Bit

7

6

5

4

3

2

1

0

Function

Reserved

Z-tag
enable

accel
enable

snoop
ahead

reg select

Default

0

0

0

0

0

R/W

R/O

R/W

R/W

R/W

R/W

Bit

Name

Function

7:4

Reserved

3

Z-tag enable

Muxes the FDD lines
0: normal operation
1: Z-tag signals on FDD lines

2

Accel enable

0: Z-tag normal operation
1: Z-tag accelerator active

1

Snoop ahead

0: Clear ready flag on accel reg read
1: Do not change the ready flag on accel read

0

Reg select

0: Select the output buffer for read
1: Select the accumulator register for read

6.5. BUR (Boot Up ROM)
BUR is a ZFx86 built-in software that serves
as a prototype debug tool and Flash update
utility. BUR is a 12K binary image residing
inside ZFx86 as ROM memory. On startup, the
BUR performs basic component initialization
functions and tests the ZF internal Static RAM.
The Static RAM is used as an 8K scratch pad
Area for performing BUR tasks. See ‘On-Chip
RAM Assignment in BUR” on page 470.
After initialization, following system components are active:
•
•
•
•
•
•
•
•

North Bridge
South Bridge
ISA Bus
Internal Static RAM
IRQ controller
Timer (8259)
COM1
Z-tag interface

ZFx86 Data Book 1.0 Rev D

The 32-entry interrupt table is built and vectors
are assigned for IRQ0-15. And INT0-8. (Additional 8 remaining interrupt table entries are
used for internal service vectors by BUR
code).
No DRAM is initialized or used by BUR code.
The functionality of BUR code can be divided
into four categories:
• Basic component initialization
• Elementary debugger console functionality
through COM1
• Data fetch and execution through Z-tag
interface
• Basic OS functionality for user code
When BUR is executed after system reset, the
component initialization occurs first. After
component initialization, BUR will probe the Ztag interface for dongle present (see

Page 462

6
Figure 5-7 "Dongle (w/o Cover)" on page 434).
If the dongle is found, the BUR will start
fetching command records from the dongle
and perform accordingly. When the dongle
cannot be found using the Z-tag interface,
BUR will initialize COM1 and start ZFiX
debugger console on COM1. An example of
downloading a small test program via the
COM1 port into the scratch pad RAM is shown

in ‘BUR COM1 Download Examples” on page
466.

6.5.1. ZFiX Console Functions
The ZFiX console is an ordinary TTY
command-line interpreter that can receive
typed commands and performs tasks
requested by the operator. See Table 6.7 for
the supported commands.

Table 6.7 ZFix Console Commands
Command

Action

i[n[b]]/inw/ind 

read 8/16/32-bit value from port

o[ut[b]]/outw/outd  

write 8/16/32-bit value to port

zfr 

read 8-bit value from ZFLogic register

zfw  

write 8-bit value to ZFLogic register

db/dw/dd 


display memory in byte/word/dword mode

d

display next memory page in previous mode
poke[b]/pokew/poked 
  -

linear

use linear mode addressing

real

use real mode addressing

h[elp]/?

show help

ver

display verson information

speed <96/19/38/56/115> 

serial speed. Set hs to 1 for RTS/CTSa

ztreset

reset Z-tag device

ztdir 

show Z-tag device content within given size

ztload 
 

load bytes to location from Z-tag

ztexec  [range]

fetch and exec command from Z-tag if in range

ztseek  [range]

seek Z-tag device to record number if in range

ztseekl 

seek Z-tag device to byte offset

ztremote [record]

start automatic fetch-exec procedure

yload 


load data through YModem to address

ysend 
  [filename]

send data through YModem from address

g[o] 


start executing from address

dls

Display available download segment address
a. The default speed on power up is 9600. The  handshake bit is currently not working. You may try higher speeds,
but you may lose data.

ZFx86 Data Book 1.0 Rev D

Page 463

6
The information in the table above is from the
actual ZFiX console help screen (displayed in
response to the “help” command).
Most of help line descriptions are self-explanatory, however, some of these do need a
second look:
“real/linear” - allows to use 16-bit or 32-bit
memory addressing for db, dw, dd and poke*
commands. If “linear” is selected, the whole
4Gb memory range can be examined and
addressed. “real” command will drop back into
real mode, when SEG:OFFSET notation
should be used and only first megabyte of
memory is accessible.
“zt*” - These commands are used for operating the Z-tag dongle as a block device. They
give you access like to normal data storage
device and allow executing and loading data
from dongle manually or request automatic
fetch and execution procedure from dongle.
The optional range parameter on some
commands is used to prevent infinite seek
when requested command record is not found,
since there is no way for determining serial
data stream length and without specified
range BUR tries to load more and more bytes
from the dongle until the specified record
number is found.
“ysend/yload” - these are YModem data
transfer functions. Data transfers are
protected by 16-bit CRC and are compatible
with popular terminals like Term95, Hyperterm,
Telix etc.

ZFx86 Data Book 1.0 Rev D

The console command line parser handles all
entered numeric values as hexadecimal and
uses extensive data type checking to catch
user errors like entering a double word in
place of a word. The command line is also
cleared up before parsing, i.e. all lowercase is
converted to uppercase and extra spaces
removed between tokens.

6.5.2. Z-tag Functionality
If Z-tag dongle is detected at BUR startup, the
command records will be fetched from the
dongle and executed. The Z-tag dongle is
serial stream device, so the execution will be
done on record-by-record basis starting from
offset0 and new records are fetched and
executed until STOP record (type 05) is
reached.
The Z-tag dongle data is divided into records.
Each record has its own header and CRC.
The header structure for Z-tag dongle data
record is seen in Figure 6-3.
There are 6 different type of commands which
the BUR understands and executes:
00 - Start/Resume BUR console. After this
command BUR will drop into console mode
and no more data from Z-tag dongle is fetched
nor processed. Note, that by default there is
no Serial output defined for BUR, so
command 02 (Serial Console Mode) must be
executed before or after command 00.

Page 464

6
;db
;db
;db
;db
;db
;db
;db
;dd
;db
;dw

07Fh,0F0h,055h
001h
019h,099h,010h,021h
023h,059h
006h
'Sample'
001h,030h
00000100
body_length dup (?)
E2FC

; command start ID
; command code
; BCD date = 1999.10.21
; BCD time = 23:59
; description string length
; description string (23 bytes max!)
; BCD version = 1.30
; body length
; body
; 16-bit CRC of body

Figure 6-3 Dongle Data Record

01 - Upload and execute code. This function
finds “best fit” available memory location and
uploads code specified in command body from
Z-tag dongle there. It executes the data after
loading and when the executable returns with
RETF (x86 RETurn Far from a procedure)
instruction, resumes data fetch from Z-tag.
02 - Serial console mode. When fetching data
from Z-tag, there can or can not be data
display to serial port. By default, the output is
disabled. This command allows to enable the
data outputting. The console setting remains
selected until next execution of this command,
so this command should be executed only for
changing/disabling the output device.
Note, that there is a special serial console
mode, what enables data redirection to Z-tag
LED pins. This way the terminal console can
be used without COM1 port usage.
03 - Execute console command line. This may
be useful, if some kind of command scripting
is used at board debugging. You can specify
the command line and BUR goes and
executes it on ZFiX console. If command
results should be displayed through serial
port, the command 02 must be executed first.
04 - Add command to a console. This function
creates the internal command for BUR
console, so users can specify new commands
they need at the debugging process and
upload them using Z-tag dongle. If you type

ZFx86 Data Book 1.0 Rev D

“help”, the new command definition can be
seen as well (the help line is defined at
command definition data).
05 - Stop. This will just light up the GREEN
LED on Z-tag dongle and freeze BUR. May be
useful to place after everything else to notify
operator, that everything is done and prevent
infinite execution of data fetch/exec procedure.
FF - Basket. The command code 0FFh is
reserved by developers and dedicated for
generic payload data, if needed (like BIOS
images etc.).
Any other command code is ignored and BUR
execution continues without interruption.

6.5.3. Internal Functionality
There is some support for programmers, who
implement the BUR Extensions (for example
the flash programming routines. At the end of
BUR, there is 80-byte area with the pointers to
useful functions and tables inside BUR what
can be re-used by BUR Extension code to
perform checksum calculations, serial I/O,
timer and various other tasks. Between all
BUR versions, this table location and structure
remains same to maintain future compatibility.
The detailed descriptions about this functionality can be found in ‘BUR API’ on page 587

Page 465

6
6.6. BUR COM1 Download Examples
The two examples following show how to
download a test program using Procomm or
HyperTerminal via COM1. These little test

programs which run entirely on the ZFx86
space are called the BUR Extensions.

6.6.1. Procomm: Download a Test Program
1.

Connect Null Modem Cable

2.

Set Procomm 2.4.2 to the following:

3.
4.

• 9600 baud
• 8 bits
• no parity
• 1 stop bit
Press the reset push button on the
board.

5.

Use the yload command to download.
In order to do the file transfer, see Figure
6-4 "Using Procomm YMODEM Batch"

6.

Run the program using the “g”
command.

Use DLS to find available memory.
Reference Table 6.7 "ZFix Console
Commands". See also Table 6.8 "OnChip RAM Assignment in BUR"

ZFx86 Data Book 1.0 Rev D

Page 466

6
ZFiX - ZFx86 PCe Internal Console
(c)2002 ZF Micro Devices, Inc.
: DLS

// Display available segment for
downloads

0070
: yload 70:0

Please start YModem transmission now or press 
... Figure 6-4 "Using Procomm
// see
CCCCCCCCCCCC ← waiting for xfr

YMODEM Batch" on page 467

YModem data transfer succeeded.
: g 70:0

Press PgUp in Procomm to
bring up the "UPLOAD" dialog.
Select YMODEM Batch.

Then enter the name of the
.com file to download:

Figure 6-4 Using Procomm YMODEM Batch

ZFx86 Data Book 1.0 Rev D

Page 467

6
6.6.2. HyperTerminal: Download a Test Program
1.

Connect Null Modem Cable

2.

Set HyperTerminal to the following:

3.

• 9600 baud
• 8 bits
• no parity
• 1 stop bit
Press the reset push button on the
board

4.

Use DLS to find available memory.
Reference Table 6.7 "ZFix Console
Commands".

5.

Use the yload command to download.
In order to do the file transfer, see Figure
6-5 "Using HyperTerminal - Send File
Ymodem"

6.

Run the program using the “g”
command.

Figure 6-5 Using HyperTerminal - Send File Ymodem

ZFx86 Data Book 1.0 Rev D

Page 468

6
6.6.3. BUR Version Test Program Source Code
;; Copyright 2002 ZF Micro Devices, Inc. All rights reserved.
title ZFx86 Bur Extension Code sample Obtains BUR Version Number
.486
burrom
segment
; Services table. These
; uploaded code use.
org
Bur_Version
db

CRLF
SerOut16
SerSend
burrom
CODE

org
label
org
label
org
label
ends

USE16 at 0f000h
are the function pointers for
0ff00h
?
0ff0ah
far
0ff22h
far
0ff3ah
far

; f000:ff00 in BUR ROM

; call ff00:ff0a --> CR/LF to COM1
; call ff00:ff22 --> AX to COM1 as decimal
; call ff00:ff3a --> Charout to COM1

segment USE16 ’CODE’
assume cs:code

START:
push
pop
mov
xor
call

cs
es
di,offset VerText
cx,cx
SerSend

les
mov

bx,psBur_Version
ax,es:[bx]

; es:bx --> Bur_Version String

call

SerOut16

; display AX to COM1 as

call

CRLF

; CR/LF to COM1

; ES:DI - text to show
; display until 0 reached

decimal

retf

; resume with BUR

psBur_Version
VerText

dd
db

Bur_Version
’BUR Version: ’,0

CODE

ends
end

START

ZFx86 Data Book 1.0 Rev D

; define string pointer

Page 469

6
6.6.4. BUR/BET Memory Map
Table 6.8 On-Chip RAM Assignment in BUR
Address Range

Assignment

00000h-0007Fh (000h:0000h-0000h:007Fh)

IRQ vector space (128 bytes)

00080h-002FFh (000h:0080h-0000h:02FFh)

System variables (640 bytes) -- Reserved for BUR

00300h-006FFh (030h:0000h-0030h:03FFh)

stack (1024 bytes)

00700h-01FFFh (070h:0000h-0070h:18FFh)

generic code/data space (6400 bytes)

6.7. Flash Programming Example
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

On-board flash programmer on ZFx86 BUR environment for AT49F516 chip
(c)2002 ZF Micro Devices, Inc.
Target Chip:Atmel AT49F516
Size:
64K
Chipselect:ms_cs0
Mode:
16-bit
Chip page:00000000h
Window base:E0000h
Window size:10000h (64K)
This code executes as BUR "Load and execute" function. It will fetch
payload code following to the executable code in dongle.

.MODEL TINY
.CODE
.486p
org

0

push
pop

cs
es

mov
xor
call
call
call

di, offset HelloText; ES:DI - text to show
cx, cx ; display until 0 reached
SerSend
CRLF
ZTPrepareRead

START:

ZFx86 Data Book 1.0 Rev D

Page 470

6
; Fetch header now
mov

cx, 4

shl
call
loop

eax, 8
ZTRead
GetSig

cmp
jz
mov
xor
call
call
jmp

eax, 7FF055FFh; is that a basket?
@f
di, offset NoPayloadText
cx, cx
SerSend
CRLF
ExitPgmrFail

GetSig:

@@:
; Loose date and time
mov

cx, 6

call
loop

ZTRead
DiscardTime

DiscardTime:

; Output basket name
mov
xor
call

di, offset WritingText
cx, cx
SerSend

call
xor
mov

ZTRead
cx, cx
cl, al

call
call
loop

ZTRead
SerSend2
ShowDesc

; string length

ShowDesc:

; Show version
mov
call
mov
call
call
call
mov
call
call
call

al, ' '
SerSend2
al, 'V'
SerSend2
ZTRead
SerOut8
al, '.'
SerSend2
ZTRead
SerOut8

ZFx86 Data Book 1.0 Rev D

Page 471

6
; Show size
mov
xor
call

di, offset SizeText
cx, cx
SerSend

mov

cx, 4

shl
call
loop

eax, 8
ZTRead
ReadSize

ReadSize:

bswap eax
push eax

; convert bytes to double
; save basket byte count

call

SerOut32

mov
xor
call
call

di, offset BytesText
cx, cx
SerSend
CRLF

; OK, bells and whistles are there. Do programming now.
; Create Memory window 0 from E0000 to FFFFF
mov
mov
out
mov
mov
out

dx, 218h
al, 26h
dx, al
dx, 21Ah
eax, 0E0000h; set window base to E0000h
dx, eax

; Set memwin0 size to 64K
mov
mov
out
mov
mov
out

dx, 218h
al, 2Ah
dx, al
dx, 21Ah
eax, 10000h-1; create 64K window
dx, eax

; Set chip page to 0
mov
mov
out
mov
mov
out

dx, 218h
al, 2Eh
dx, al
dx, 21Ah
eax, 0h; set page to the beginning of
dx, eax; the chip

ZFx86 Data Book 1.0 Rev D

Page 472

6
; Set chip width to 16-bit and read-write mode
mov
mov
out
mov
in
and
out

dx,
al,
dx,
dx,
al,
al,
dx,

218h
5Ah
al
219h
dx
11101110b
al

; Turn ISA bus speed as slow as possible, since we do not know what the
; SYSCLK is and we can not program device well if we do it too fast
pushf
cli
mov
mov
out
mov
in
or
out
popf

eax, 80009050h; PIT Control/ISA Clock divider
dx, 0CF8h
dx, eax
dx, 0CFCh
al, dx
al, 00000111b; divide by 8
dx, al

; Now we have chip layed out from E000:0 to E000:FFFF
; Time to program some flash.
; Check, whenever or not we have AT49F516 part on-board
mov
call

al, 90h
FlashCMD16

push
pop
xor
mov

0E000h
ds
si, si
eax, ds:[si]; get chip ID to EAX

mov

ebx, eax

mov
xor
call
call
mov
xor
call
shr
call
call

di, offset MfgText
cx, cx
SerSend
SerOut8
di, offset DevIDText
cx, cx
SerSend
eax, 16
SerOut8
CRLF

mov

al, 0F0h

ZFx86 Data Book 1.0 Rev D

; get ID

; save ID

Page 473

6
call

FlashCMD16; end identification mode

pop

ecx

and
the minor version
cmp
jz
mov
xor
call
call
jmp

; restore bytes count (was EAX originally)

ebx, 0FFFCFFFFh ; strip ID two low bits, since this may be
code
ebx, 00084001Fh ; check, if it's AT49F516
@f
di, offset WrongDevText
cx, cx
SerSend
CRLF
ExitPgmrFail

@@:
; We have right chip. Erase device now
push

ecx

mov
xor
call

di, offset ErasingText
cx, cx
SerSend

mov
call
mov
call

al, 80h ; chip erase command part 1
FlashCmd16
al, 10h; chip erase command part 2
FlashCmd16

; Erase is now in progress. Check, when we are ready.
push
pop
xor
call
mov
mov

0E000h
fs
si, si
DSBX2Var
ax, 182
ds:[bx.CountDown], ax; gives 10sec. timeout

mov
mov
out
inc
in
and
out
call

dx, 218h
al, 05Eh ;ZT_SIG_OUT
dx, al
dx
al, dx
al, 11110101b ; disable LED's
dx, al
ZTPrepareRead ; ZFLogic back to track

cmp
jz
cmp
jnz

word ptr ds:[bx.CountDown], 0
@f
dword ptr fs:[si], 0FFFFFFFFh
@b ; loop until erase completes

@@:

@@:

ZFx86 Data Book 1.0 Rev D

Page 474

6
; reset timer, so we will not loose our blinking LED's
mov
cmp
jz

word ptr ds:[bx.CountDown], 0
dword ptr fs:[si], 0FFFFFFFFh
@f

mov
xor
call
jmp

di, offset FailedText
cx, cx
SerSend
ExitPgmrFail

mov
xor
call

di, offset OkText
cx, cx
SerSend

@@:

; All set. Programming ...
call

ResetCRC

mov
xor
call

di, offset PgmText
cx, cx
SerSend

pop
cmp
jz

ecx
; restore byte count in basket
ecx, 0; don’t do anything
PgmDone; if basket size is 0

shr

ecx, 1; divide by two to get word count

push
pop
xor

0E000h
ds
si, si

mov
call
call
shl
call
xchg
mov
mov

al, 0A0h; "program word" command
FlashCmd16
ZTRead
ax, 8
ZTRead
al, ah; byte order for 16-bit writing to memory
ds:[si], ax
bx, ax

ProgramLoop:

; in the extreme case we can have PCI backside clock 80Mhz. ISA
; divider is 8, so we have 10M ISA bus clock. Programming cycle can be max.
; 50us, so we need to wait here about 500 ISA cycles to kill that time.
push
mov

cx
cx, 500

in

al, 80h; create one ISA cycle

WaitWriting:

ZFx86 Data Book 1.0 Rev D

Page 475

6
cmp
ds:[si], bx; see, if we have byte ready
loopnzWaitWriting
pop
cx
mov
int

ax, ds:[si]; read back the word we
17h
; programmed
; update CRC
shr
ax, 8
int
17h
add
si, 2
cmp
ds:[si-2], bx
loopz ProgramLoop
PgmDone:
cmp
jz

ds:[si-2], bx; see, why we exited
@f
; Last byte is OK, so it's because all is

mov
xor
call
jmp

di, offset FailedText
cx, cx
SerSend
ExitPgmrFail

mov
xor
call

di, offset OkText
cx, cx
SerSend

done

@@:

; Get original checksum
call
shl
call
xchg

ZTRead
ax, 8
ZTRead
al, ah

call
cmp
jz

DSBX2Var; get variables block to DS:BX
word ptr ds:[bx.YModemCRChi_C], ax
CRCOK

mov
xor
call

di, offset CRCFailedText
cx, cx
SerSend

call
mov
call
mov
call
call
jmp

SerOut16
al, ' '
SerSend2
ax, word ptr ds:[bx.YModemCRChi_C]
SerOut16
CRLF
ExitPgmrFail

mov
xor

di, offset CRCOkText
cx, cx

CRCOK:

ZFx86 Data Book 1.0 Rev D

Page 476

6
call
call

SerSend
CRLF

jmp
ExitPgmrOk
ExitPgmrFail:
; Lit up RED LED and do not do anything else!
mov
mov
out
inc
in
and
or
out

dx,
al,
dx,
dx
al,
al,
al,
dx,

218h
05Eh ;ZT_SIG_OUT
al

jmp

$

; Lit
mov
mov
out
inc
in
and
or
out

up GREEN LED and continue with BUR
dx, 218h
al, 05Eh ;ZT_SIG_OUT
dx, al
dx
al, dx
al, 11110101b
al, ZT_LED_GREEN;00000010b
dx, al

call

CRLF

dx
11110101b
ZT_LED_RED;00001000b
al

ExitPgmrOk:

ExitPgmr:

; Set timer to maximum value. This is useful to prevent
; BUR from blinking with LED's when loading next commands.
; This way we maintain our RED or GREEN LED setting
call
mov

DSBX2Var
word ptr ds:[bx.CountDown], 0FFFFh

; Always exit with ZFL registers prepared for accelerated read!
call

ZTPrepareRead

retf

; resume with BUR

include ..\BURAPI.ASM
HelloTextdb 0Dh, 0Ah
db
'PGM - ZFx86 AT49F516 Flash Programmer V0.80', 0Dh, 0Ah
db
'---------------------------------------------', 0
NoPayloadTextdb'No Payload. Exiting.', 0
WritingTextdb'Source: ', 0
SizeTextdb ' (0x', 0

ZFx86 Data Book 1.0 Rev D

Page 477

6
BytesTextdb ' bytes)', 0
MfgText
db
'Device: Mfg=',0
DevIDTextdb ' DevID=',0
WrongDevTextdb'This is not Atmel AT49F516', 0
OkText
db
'OK!', 0Dh, 0Ah, 0
FailedTextdb'FAILED!', 0Dh, 0Ah, 0
ErasingTextdb'Erasing .. ', 0
PgmText
db
'Programming .. ', 0
CRCFailedTextdb'Data CRC failure: ', 0
CRCOkTextdb 'Data CRC was OK!', 0

;
;
;
;
;
;
;
;
;

Execute flash device command
Entry: AL - command code
Exit: none
Uses: none

FlashCMD16proc
push
push

ds
si

push

ax

push
pop

0e000h
ds

; we have address bits shifted by one in 16-bit socket. It means,
; that control bytes should actually go one bit shifted to left, in
; order to get A0 right
mov
mov
shl
mov

al, 0AAh; CMD sequence part 1
si, 05555h
si, 1
ds:[si], al

mov
mov
shl
mov

al, 055h; CMD sequence part 2
si, 0AAAAh
si, 1
ds:[si], al

pop

ax

mov
shl
mov

si, 05555h
si, 1
ds:[si], al

ZFx86 Data Book 1.0 Rev D

; restore command code

Page 478

6
pop
pop
ret
FlashCMD16endp

si
di

END START
ENDS

ZFx86 Data Book 1.0 Rev D

Page 479

6

ZFx86 Data Book 1.0 Rev D

Page 480

7
7. Electrical Specifications
This chapter provides information about:
• General electrical specifications

7.1.2. Power/Ground Connections and
Decoupling
When testing and operating the ZFx86 device,
use standard high frequency techniques to
reduce parasitic effects. For example:

• DC characteristics
• AC characteristics
All voltage values in this chapter are with
respect to VSS unless otherwise noted.

• Filter the DC power leads with low-inductance decoupling capacitors.

7.1. General Specifications

• Use low-impedance wiring.

7.1.1. MTTF and FIT Specifications
The ZFx86’s Mean Time To Failure (MTTF)
and Failures In Time (FIT – Failures per billion
operating device-hours) specifications are as
follows.
Parameter

ZFx86

Technology

CMOS 8

°

Dynamic Op Life Temperature

125 C

Dynamic Op Life Voltage

3.2V

Typical Use Temperature and Voltage

60 C; 2.5V

Mean Time To Failure

21,129,173.19
hours

°

• Utilize the POWER and GND pins.

Absolute Maximum Ratings
Stresses beyond those indicated in the
following table may cause permanent damage
to the ZFx86 device, reduce device reliability
and result in premature failure, even when
there is no immediately apparent sign of
failure. Prolonged exposure to conditions at or
near the absolute maximum ratings may also
result in reduced device life span and reduced
reliability.
Note: The values in the following table are
stress ratings only. They do not imply that
operation under other conditions is impossible.

Table 7.1 Absolute Maximum Ratings
Parameter

Min

Max

Operating case temperature1, 2

-40

85oC

Storage temperature3

-45

125oC

Supply voltage

Maximum supply voltage is as indicated. See Table 7.2.

Voltage on:
-5V tolerance pins
-others

-0.5

6.0V

-0.5

4.2V

Input clamp current, IIK1

10mA

Output clamp current, IOK1

25mA

1. Power applied
2. Temperature range industrial
3. No bias

ZFx86 Data Book 1.0 Rev D

Page 481

7
Table 7.2 Recommended Operating Conditions
Symbol
TC

Parameter

Conditions

Min

Typ

Max

Extended Temperature Range ZFx86

33/66/100 MHz1

–40oC

—

85oC

Standard ZFx86

100 MHz2

–0oC

—

70oC

Operating Case Temperature

VBAT

Battery Supply Voltage. Powers RTC

—

2.85V

3.0V

3.15V

Vdd–Core

Core Processor (CPU) Power Supply

—

2.09V

2.20V

2.31V

I/O Buffer Power Supply

—

3.14V

3.30V

3.46V

Vdd–I/O

1. Temperature range industrial
2. Temperature range commercial

Table 7.3 Current Consumption
Symbol

Parameter

Conditions

Max

Idd–Core

Core Supply Current

33 MHz sysclk with 3X CPU

380mA

Idd–Core

Core Supply Current

Suspend mode with external clocks running

120mA

Idd–Core

Core Supply Current

Suspend mode with external clocks off

45mA

VBAT Battery Supply Current

VBAT = 3V other supplies at 0V

2.0µA

Idd–I/O

Vdd–I/O Power Supply Current

Suspend mode

51TBDmA

Idd–I/O

Vdd–I/O Power Supply Current

Generic OS

18TBDmA

IBAT

Table 7.4 Pin Capacitance and Inductance
Symbol

Parameter

Min

Typ

Max

CIN1

Input Pin Capacitance

TBD pF

TBD pF

TBD pF

CIN1

Clock Input Capacitance

TBD pF

TBD pF

TBD pF

CI/O1

I/O Pin Capacitance

TBD pF

TBD pF

TBD pF

CO1

Output Pin Capacitance

TBD pF

TBD pF

TBD pF

LPIN2

Pin Inductance

TBD nH

TBD nH

TBD nH

1. TA = 25°C, f = 1 MHz. All capacitances not 100% tested.
2. Not 100% tested.

ZFx86 Data Book 1.0 Rev D

Page 482

7
7.2. Signal I/O Buffer Type Directory
The table shown below describes the various
buffer types which are used for signals of the
ZFx86 device. Immediately following this table

is another table which lists all the signals
according to logical group, and the buffer
types which are relevant for each signal.

Table 7.5 I/O Cell Characteristics
TYPE

Generic2
I/O, OE, IE

MIDE
I/O, OE, IE

MAC97
I/O, OE, IE

MPCI
I/O, OE, IE

IOH

-8ma

-3ma

-2ma

-1ma

MPCI_CLK
I/O, OE, IE

—

AC
L=>H

AC
H=>L

10ma

10ns
buf delay
.4/2.4 V
50pf

10ns
buf delay
2.4/.4 V
50pf

RENU (160mic amps)
REND (036mic amps)
input hysteresis 250mv.
For ISA Bus.

5ma

15/28ns
buf delay
.4/2.4 V
75pf /
150pf

15/28ns
buf delay
2./.4 V
75pf /
150pf

No RENU or REND
Input hysteresis 200mv
For IDE interface

8ma

10ns
buf delay
.4/2.4 V
50pf

10ns
buf delay
2.4/.4 V
50pf

RENU only
input hysteresis
For AC97 and Open Drain

1.5ma

5ns
buf delay
50pf
32ma
peak

5ns
buf delay
50pf
38ma
peak

RENU only
Designed to meet PCI specification

5ns

5ns

RENU only
For PCI CLK

10ns
buf delay
2.4/.4 V
50pf

RENU & REND.
input hysteresis.
floppy, parallel, and open drain

IOL

—

-14ma

14ma

10ns
buf delay
.4/2.4 V
50pf

MVBAT
~ a wire

—

—

—

—

MUSB
I/O, OE, IE

—

—

—

—

MWUSB
just a wire

—

—

—

—

2ma

5ma

2v/ns
60pf load

2v/ns
60pf load

M_FDC_PP
I/O, OE, IE

MMC_D
I/O, OE, IE
Slew cntrl
JTAG Bound support

ZFx86 Data Book 1.0 Rev D

COMMENT

For vbat. Wire with poly resis
No RENU or REND
USB power enable and over current
Connects pad to USB hard Macro
No RENU or REND
No hysteresis
For SDRAM data and address

Page 483

7
Table 7.5 I/O Cell Characteristics (cont.)
TYPE

IOH

MMC_SDCLK
Out & OE
No slew.
JTAG Bound support

IOL

2ma

5ma

—

—

MMC_SDCLKIN
Input only.
No IE.
JTAG Bound support

AC
L=>H

AC
H=>L

1.7v/ns
60pf load

1.7v/ns
60pf load

—

—

COMMENT

No RENU or REND
For SDRAM output clocks

No RENU or REND
No hysteresis
SDRAM or other high speed clock input

Note: See further information in the Cell Types in 7.3. "Detailed DC Characteristics of Cells" on
page 484.

7.3. Detailed DC Characteristics of Cells
Table 7.6 Input, MPCi
Symbol

Parameter

Conditions

Min

Max

VIH

Input High Voltage

—

0.5VIO

VIO+0.5V1

VIL

Input Low Voltage

—

-0.5V1

0.3VIO

—

0.7VIO

—

0 < VIN < VIO

—

+/-10µA

VIPU
lIL

Input Pull-up Voltage2
Input Leakage Current

2, 3

1. Not 100% tested.
2. Not 100% tested. This parameter indicates the minimum voltage to which we calculate the pull-up
resistors in order to pull a floated network.
3. Input leakage currents include hi-Z output leakage for all bidirectional buffers with TRI-STATE
outputs.

Table 7.7 Input, Generic2
Symbol

Parameter

Conditions

Min

Max

VIH

Input High Voltage

—

2.0V

VIO+0.5V

VIL

Input Low Voltage

—

−0.5V

0.8V

IIL

Input Leakage Current

VIN = VIO

—

10µA

VIN = VSS

—

−10µA

—

250mV

—

VH

Input Hysteresis

ZFx86 Data Book 1.0 Rev D

Page 484

7
Table 7.8 Input, MUSB
Symbol

Parameter

Conditions

Min

Max

VIH

Input High Voltage

—

0.5VIO

VIO+0.5V

VIL

Input Low Voltage

—

−0.5V

0.3VIO

IIL

Input Leakage Current

VIN = VI/O

—

10µA

VIN = VSS

—

−10µA

VHIS

Input Hysteresis

200mV

Table 7.9 Input, MIDE
Symbol

Parameter

Conditions

Min

Max

VIH

Input High Voltage

—

0.5VI/O

VIO+0.5V

VIL

Input Low Voltage

—

−0.5V

0.3VI/O

IIL

Input Leakage Current

VIN = VI/O

—

10µA

VIN = VSS

—

−10µA

—

200mV

—

Conditions

Min

Max

VHIS

Input Hysteresis

Table 7.10 Input, M-FDCP
Symbol

Parameter

VIH

Input High Voltage

—

0.5VI/O

VI/O+0.5V

VIL

Input Low Voltage

—

−0.5V

0.3VI/O

IIL

Input Leakage Current

VIN = VI/O

—

10µA

VIN = VSS

—

−10µA

—

200mV

—

Conditions

Min

Max

VHIS

Input Hysteresis

Table 7.11 Input, MMC-D
Symbol

Parameter

VIH

Input High Voltage

—

0.5VI/O

VI/O+0.5V

VIL

Input Low Voltage

—

−0.5V

0.3VI/O

IIL

Input Leakage Current

VIN = VI/O

—

10µA

VIN = VSS

—

−10µA

—

200mV

—

VHIS

Input Hysteresis

ZFx86 Data Book 1.0 Rev D

Page 485

7
Table 7.12 Input, MWUSB
Symbol

Parameter

Conditions

Min

Max

VIH

Input High Voltage

—

0.5VI/O

VI/O+0.5V1

VIL

Input Low Voltage

—

−0.5V1

0.3VI/O

IIL

Input Leakage Current

VIN = VI/O

—

10µA

VIN = VSS

—

−10µA

—

200mV

—

|(D+)−(D−)| and Figure 7-1

0.2V

—

VHIS

Input Hysteresis1

VDI

Differential Input Sensitivity

VCM

Differential Common Mode Range

Includes VDI Range

0.8V

2.5V

VSE

Single Ended Receiver Threshold

—

0.8V

2.0V

1. Not 100% tested.

Minimum Differential Sensitivity (volts)

1.0

0.8

0.6

0.4

0.2

0.0
0.0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
Common Mode Input Voltage (volts)

Figure 7-1 Differential Input Sensitivity for Common Mode Range

Table 7.13 Input, MAC971
Symbol
VIH

Parameter
Input High Voltage

VIL

Input Low Voltage

IIL

Input Leakage Current

VHIS

Input hysteresis

Conditions

Min

Max

—

1.4V

—

—

-0.5V2

0.8V

VIN=VI/O

—

10µA

VIN=VSS

—

−10µA

—

200mV

—

1. Buffer Type: INAB
2. Not 100% tested.

ZFx86 Data Book 1.0 Rev D

Page 486

7
Table 7.14 Output, PCI TRI-STATE Buffer
Symbol

Parameter

Conditions

Min

Max

VOH

Output High Voltage

lOH = -500 µA

0.9VI/O

—

VOL

Output Low Voltage

lOL =1500 µA

—

0.1VIO

I PU

Pull-up current

Output short to ground

mA

mA

Table 7.15 Output, GENERIC 21
Symbol

Parameter

Conditions

Min

Max

VOH

Output High Voltage

lOH = -8 mA

2.4V

—

VOL

Output Low Voltage

lOL = 10 mA

—

0.4V

I PU

Pull-up current

Output short to ground

mA

mA

I PD

Pull-down current

Output short to VI/O

mA

mA

1. Output, TRI-STATE buffer capable of sourcing I/OH mA and sinking I/OL mA

Table 7.16 Output, MIDE
Symbol

Parameter

Conditions

Min

Max

VOH

Output High Voltage

lOH = -3 mA

2.4V

—

VOL

Output Low Voltage

lOL = 5 mA

—

0.4V

Conditions

Min

Max

Table 7.17 Output, MUSB
Symbol

Parameter

VOH

Output High Voltage

lOH = -? mA

2.4V

—

VOL

Output Low Voltage

lOL = ? mA

—

0.4V

Table 7.18 Output, M-FDC_PP
Symbol

Parameter

Conditions

Min

Max

VOH

Output High Voltage

IOH = -14 mA

2.4V

—

VOL

Output Low Voltage

IOL = 14 mA

—

0.4V

I PU

Pull-up current

Output short to ground

mA

mA

I PD

Pull-down current

Output short to V I/O

mA

mA

ZFx86 Data Book 1.0 Rev D

Page 487

7
Table 7.19 Output, MMC_D
Symbol

Parameter

Conditions

Min

Max

VOH

Output High Voltage

lOH = -2 mA

2.4V

—

VOL

Output Low Voltage

lOL = 5 mA

—

0.4V

.
Table 7.20 Output, MWUSB1
Symbol

Parameter

Conditions

Min

Max

VUSB_OH

High-level output voltage

IOH = -0.25 mA
RL = 15 KΩ to GND

2.8V

3.6V2

VUSB_OL

Low-level output voltage

IOL = 2.5 mA
RL = 1.5 KΩ to 3.6V

—

0.3V

tUSB_CRS

Output signal crossover voltage

—

1.3V

2.0V

1. Buffer Type: OUSB
2. Tested by characterization.

Table 7.21 Output, MAC971
Symbol

Parameter

Conditions

Min

Max

VOH

Output High Voltage

lOH = - 2 mA

0.9VI/O

—

VOL

Output Low Voltage

lOL = 8 mA

—

0.1VI/O

I PU

Pull-up current

Output short to ground

mA

mA

1. Buffer Type: OMAC97I

ZFx86 Data Book 1.0 Rev D

Page 488

7
7.4. AC Characteristics
The tables in this section list the following AC
characteristics:
• Output delays
• Input setup requirements
• Input hold requirements
• Output float delays
The default levels for measurement of the
rising clock edge reference voltage (VREF),
and other voltages are shown in the Table

below. Input or output signals must cross
these levels during testing. Unless otherwise
specified, all measurement points in this
section conform to these default levels.
Note: The following naming conventions are
used in this section:
name1,2 = name1 or name2
name1/name2 = name1 or name2
namex1,2/namey1,2 = namex1,
namex2, namey1, or namey2

Table 7.22 Default Levels for Measurement of Switching Parameters
Symbol

Parameter

Value

Reference

VREF

Reference voltage

1.5V

VIHD

Input High Drive voltage

2.4V

Figure 7-2

VILD

Input Low Drive voltage

0.4V

Figure 7-2

VOHD

Output High Drive voltage

2.4V

VOLD

Output Low Drive voltage

0.4V

7.4.1. System Interface
Table 7.23 sysclk_c Clock Parameters
Symbol

t CYC
t HIGH
t LOW

ZFx86 Data Book 1.0 Rev D

Parameter

Min

Max

Clock Cycle Time

500nS

15nS

Clock High Time

14nS

7nS

Clock Low Time

14nS

7nS

Clock Slew Rate

1V/nS

4V/ns

Page 489

7
V IHD
sysclk_c
V ILD

t HIGH

t LOW

t CYC
Figure 7-2 sysclk_c Timing and Measurement Points

reset_n

V ILD

T LOW
reset_n may be asserted and de-asserted asynchronous to clock. T LOW must be at least
15 nano seconds.

Figure 7-3 reset_n timing

ZFx86 Data Book 1.0 Rev D

Page 490

7
sysclk_c

reset_n

res_out

pcirtst_n has the same timing as res_out but opposite in sign. Both res_out and pcirst_n are
asserted when reset_n is asserted without regards to clock.Both de-assert on the high to low
edge of clock.
Figure 7-4 res_out timing

sysclk_c

cpu_trig

Figure 7-5 CPU_trig timing

ZFx86 Data Book 1.0 Rev D

Page 491

7
7.4.2. Memory Interface

All AC tests are as follows unless otherwise
specified:

The Minimum Input setup and hold times
described in Figure 7-6 (legend C and D)
define the smallest acceptable sampling
window during which a synchronous input
signal must be stable to ensure correct operation.

VOH

• VI/O = 3.0V to 3.6V (3.3V nominal)
• TC = 0 oC to 70 oC
• CL = 50 pF

VOHD

dr_clk[3:0]_c

VREF

VOLD

VOL

A
B

Max
Min

VOH
Valid Output n

OUTPUTS

Valid Output n+1

VREF

VOL
tx
tx

VIH

VIHD

VREF

dr_clk[3:0]_c
VILD

VIL

C

D

VIH
VREF

INPUTS
VIL
Legend: A = Maximum Output Delay
B = Minimum Output Delay
C = Minimum Input Setup
D = Minimum Input Hold

Figure 7-6 Drive Level and Measurement Points for Switching Characters

ZFx86 Data Book 1.0 Rev D

Page 492

7
Table 7.24 SDRAM Interface Signals
Symbol

t1
t2
t3
t4
t5
t6
t7

Parameter

Min

Max

Control Output 1 Valid from dr_clk

2.3nS

5.5nS

ma[3:0], Output Valid from dr_clk

2.0nS

4.4nS

d[31:0] Output Valid from dr_clk

2.4nS

5.9nS

d[31:0] Read Data in Setup to dr_clk

3.1nS

6.6nS

d[31:0] Read Data Hold to dr_clk

2.0nS

3.0nS

dr_clk cycle time

Same as sysclk_c

dr_clk fall/rise time between (VOLD-VOHD)

2.5nS

2.5nS

1. Control output includes all the following signals: dr_cs[3:0]_n, dr_msk[3:0]_n, dr_we0_n,
dr_ras0_n,dr_cas0_n Load = 50pF, VCORE = 2.5, VI/O = 3.3V, @25oC.
t6
t1, t2, t3
VOHD

VREF

VOLD

dr_clk[3:0]_c
t7
t7
Control Output, ma[13:0]
d[31:0]

VREF

Figure 7-7 Output Valid Timing

VIHD
VREF
VILD

dr_clk[3:0]_c
t4

d[31:0]
Data Valid

t5

t5

t4

Data Valid

Read Data In

ZFx86 Data Book 1.0 Rev D

Page 493

7
Figure 7-8 Setup and Hold Timing - Read Data In

7.4.3. ACCESS.bus Interface
1. All ACCESS.bus timing is not 100% tested. Timing is guaranteed by design.
Table 7.25 ACCESS.bus Interface
Symbol

tSCLfi
tSCLri
tSDAfi
tSDAri

SDAT

Parameter

Min

Max

Reference

SCLK signal fall time

300nS

Figure 7-9

SCLK signal rise time

1µs

Figure 7-9

SDAT signal fall time

300nS

Figure 7-9

SDAT signal rise time

1µs

Figure 7-9

0.7VIO

0.7VIO

0.3VIO

0.3VIO

tSDAr

SCLK

tSDAf

0.7VIO

0.7VIO

0.3VIO

0.3VIO

tSCLr

tSCLf

Figure 7-9 ACB Signals (SDAT AND SCLK) Rising and Falling times

ZFx86 Data Book 1.0 Rev D

Page 494

7
7.4.4. PCI Bus
The SC1400B device is compliant with PCI
Bus Rev. 2.1 specifications. Relevant information from the PCI Bus specifications is
provided below.

The PME signal is compliant with PCI Bus
Revision 2.2.
All parameters in the following table are not
100% tested.

Table 7.26 PCI Bus - AC Specifications
Symbol

Min

Max

Unit

-12VI/O

—

mA

-17.1(VI/O-VOUT)

—

mA

0.7VI/OVOUT>01, 2

—

Equation B

Test Point

VOUT-=0.18VI/O

—

38VI/O

mA

ICL

Low Clamp Current

-3VIN>VI/O+1

25+(VIN-VI/O-1)/0.015

—

mA

SLEWR3

Output Rise Slew Rate

0.2VI/O - 0.6 VI/O Load

1V/nS

4V/nS

V/nS

SLEWF3

Output Fall Slew Rate

0.6VI/O - 0.2 VI/O Load

1V/nS

4V/nS

V/nS

IOH(AC)1, 2

Parameter
Switching
Current High

Test
IOL(AC)1

Point2

Switching
Current Low

2

Condition
0VOUTŠ≥0.6VI/O
0.6VI/O>VOUT>0.1VI/O1

1. Refer to the V/I curves in Figure 7-11 This specification does not apply to PCICLK0, PCICLK1, and PCIRST
which are system outputs.
2. Maximum current requirements are met when drivers pull beyond the first step voltage. Equations which define
these maximum values (A and B) are provided with relevant diagrams in Figure 7-11. These maximum values
are guaranteed by design.
3. Rise slew rate does not apply to open-drain outputs. This parameter is interpreted as the cumulative edge rate
across the specified range. According to the test circuit Figure 7-10.

ZFx86 Data Book 1.0 Rev D

Page 495

7
Pin
0.5" max.

Output
Buffer
1KΩ

10pF

VCC

1KΩ

Figure 7-10 Testing Setup for Slew Rate and Minimum Timing

Output Voltage
Volts

Output Voltage
Volts

Pull-Up

VIO

Test Point

0.9
VIO

AC
Drive Point

0.6
VIO
DC
Drive Point

DC
Drive Point
0.3
VIO

Pull-Down

AC
Drive Point
-0.5

0.5VI

0.1
VIO
-12VIO

-48VIO

Equation A

IOH mA

Test Point

1.5

16VIO

64VIO

IOL mA

Equation B

Ioh=(98.0/VIO)*(VOUT-VIO)*(VOUT+0.4VIO)
for VIO>VOUT>0.7VIO

IOL=(256/VIO)*VOUT*(VIO-VOUT)
for 0V on the selected terminal
output. This function will output bytes 0Dh 0Ah
to the currently selected serial device.
Entry:

none

Exit:

none

Uses:

flags

Page 587

9
Delay
Do uncalibrated but sufficiently long delay. The
delay is blocking (no execution will return to
caller before delay is expired) but does not
switch off interrupts.
The actual delay is performed by following
code:
mov

cx, 20

in
loop

al, 80h
DlyLoop

Depending on value in AL the type checking is
done for parameter as well. This means that if
the byte value is desired (AL = 0) and parser
finds larger numeric value than 0FFh at
specific parameter position, it will automatically return with the carry flag cleared (NC).
The parser will ignore extra spaces and extra
zeros (CHR(0x30)) at the beginning of the
numbers.

DlyLoop:
Entry:

The I/O port 80h read is done for wasting
reasonably longer amount of time than “NOP”
would have been.
Entry:

none

Exit:

none

Uses:

flags

Parm2EDX

AL – parse type code:
0h – byte (range 0-FFh)
1h – word (range 0-FFFFh)
2h – dword (range 0-FFFFFFFFh)
3h – address (depending on flag “Addressing”
at Variables area (see below)):
If Addressing = 0 (real mode), then checks for
type WORD:WORD (0-FFFFh:0-FFFFh)
If Addressing = 1 (linear mode), then checks
for doubleword (0-FFFFFFFFh))
CL – parameter number to parse (1 = first
parameter etc.)

Exit:

EDX – Parsed value if CF is set to CY
CF – CY = value parsed successfully
– NC = failed parsing the value

Uses:

EDX, flags

This function will parse the data placed at
BUR variables area “CmdLine” position (see
below) according to the parse type notification
supplied as a parameter in AL. This function is
used internally by BUR as ZfiX console
command line parameters parser and made
available for the user application when interaction through the console is performed. This
function is also useful when user is implementing the new command for the console,
since it helps to gather all necessary parameters without implementing the parser.

ResetCRC

The data at CmdLine area must be zero-terminated and parameter parsing starts after first
space (CHR(0x20)) encountered in command
line string.

This Interrupt will automatically update the
CRC value at BUR internal variables area,
named “YModemCRChi_C” and
“YModemCRClo_C”, for upper and lower byte
of 16-bit CRC respectively.

The parser is parsing only hexadecimal
numeric values, so running the parser for the
first parameter in string “command 1234”
returns 1234h as a return.

ZFx86 Data Book 1.0 Rev D

BUR has internal 16-bit CRC calculation
routines. This routine is mapped as interrupt
service, so the CRC calculation will be
performed by setting the byte value to AL and
then calling INT 17h.

ResetCRC function is used for helping to reset
that data area to zeros. This function is equivalent of manually resetting
“YModemCRChi_C” and “YModemCRClo_C”
to 00h.

Page 588

9
Entry:

none

Exit:

none

Uses:

flags

to the first non-space character of the parameter.
The returned value in SI is pointer inside
“CmdLine” field at BUR variables area, so the
actual string location in memory is:

INT 17h (Interrupt Vector)
Although being an interrupt vector, it is a place
to describe it’s behavior, since this is the only
interrupt vector provided by BUR as functional
service to user application.
This interrupt is used for CRC updating at
BUR variables data area, located at
“YModemCRChi_C” and “YModemCRClo_C”.
For more information see description of BUR
API function “ResetCRC”.
The reason why CRC calculation algorithm is
interrupt vector rather than callable service
was the fact that all BUR functions are
residing inside ROM area. Code fetch from
ROM area is very slow and since the CRC
calculation is done for each byte received, it
will slow down the entire data processing
significally. To avoid that, BUR is caching CRC
calculation (and some aggressively used
internal functions) from ROM to RAM and
mapping them as interrupts.
Entry:

AL – byte to include for CRC calculation

Exit:

none

Uses:

none

SeekParm
It is desired sometimes to use non-numeric
parameters for command line parsing. To
process those, it is necessary to determine the
start offset of string tokens inside the
command line.
SeekParm provides that functionality, allowing
search within the command line string located
at “CmdLine” at BUR internal variables area
by parameter number. This function will skip
all trailing spaces from command line string
tokens, so pointer returned is actually pointing

ZFx86 Data Book 1.0 Rev D

0000:[Variables.CmdLine + SI]
Entry:

CL – parameter number (1 = first parameter
etc.)

Exit:

SI – offset to parameter within CmdLine when
CF is CY
CF – CY = parameter seeked successfully
– NC = parse error

Uses:

SI, flags

SerOut8
Displays 8-bit hexadecimal numeric value on
active serial console.
The active serial console is selected at BUR
variables area at position “SerMode” where
0 = no serial output
1 = COM1
2 = Z-tag LED pins.
The number is displayed in hexadecimal
format “as is”, so no leading zeros or type
identifiers are added. Value 1Ah therefore
appears “1A” on serial console.
Entry:

AL

Exit:

none

Uses:

flags

– value to display

SerOut16
Displays 16-bit hexadecimal numeric value on
active serial console. See comments for the
function “SerOut8”.
Value 12ABh appears as “12AB” on console.
Entry:

AX

Exit:

none

Uses:

flags

– value to display

Page 589

9
SerOut32
Displays 32-bit hexadecimal numeric value on
active serial console. See comments for the
function “SerOut8”.
Value 1234ABCDh appears as “1234ABCD”
on console.
Entry:

EAX

Exit:

none

Uses:

flags

– value to display

SerOutBits
Displays 8-bit numeric value on active serial
console as bit pattern, starting from MSB. See
comments for the function “SerOut8”.
Value 5Ah appears as “01011010” on console.
Entry:

AL

Exit:

none

Uses:

flags

– value to display

SerSend
Transmits string to the active serial console.
See comments for the function “SerOut8”.

Entry:

AL

Exit:

none

Uses:

flags

SerRec
Receive character from active serial console
input with no character waiting.
The active serial console is selected at BUR
variables area at position “SerMode” where:
0 = no serial output
1 = COM1
2 = Z-tag interface.
The serial communication on BUR is interruptdriven, so the SerRec function returns byte
from the receive buffer located at BUR variables area position “CircBuf”. When buffer is
empty, this function will return with ZF set to Z.
Otherwise ZF is set to NZ and character is
moved from receive buffer to AL.
Receive buffer is 128 bytes long, so host can
send 128 symbols without loss before BUR
application starts receiving.
Entry:

none

Exit:

AL – symbol received if ZF is NZ

The string can be either zero-terminated or
with the specified length.
Entry:

ES:DI – string to display
CX
– string length (CX = 0 if string is 0terminated)

Exit:

none

Uses:

flags

– character to display

ZF – NZ = character received
– Z = no character received
Uses:

AX, flags

SerSend2
Transmit character to active serial console.
See comments for the function “SerOut8”.
The symbol can be any ASCII character
between 0 and 255. No character translation
is performed, all data will be transmitted to
serial port “as is”.

ZFx86 Data Book 1.0 Rev D

Page 590

9
SerRecWait

YModemGetHeader

SerRecWait is functionally identical to the
SerRec but waits for character to appear into
receive buffer for 220ms if receive buffer is
empty.

BUR has built-in Ymodem transmission
protocol for transferring files over serial link.
This functionality is also made available as
public function for using at BUR applications.

Entry:

none

Exit:

AL – symbol received if ZF is NZ
ZF – NZ = character received
– Z = no character received

Uses:

AX, flags

Addr2Linear
Helper function for converting real-mode
address to linear address.
The function behaves differently depending on
flag “Addressing” at BUR variables area.
When flag indicates 1h (linear addressing), the
function will simply pass EDX to EDI. When
flag indicates 0h (real mode translation), the
address translation is performed.
The actual translation is performed by
following routine:
mov

edi, edx
cmp
byte ptr ds:[bx.Addressing], 1
; EDX
was linear?
jz
Converted
xor
di, di
shr
edi, 12
shl
edx, 16
shr
edx, 16
;
clear high 16 bits in EDX
add
edi, edx
;
edi is now 20-bit address Converted:
Entry:

EDX – value to convert. Bits 31..16 = realmode segment address
Bits 15..0 = real-mode offset address

Exit:

EDI – linear memory location (20-bit if
converted from real mode)

Uses:

EDI, flags

ZFx86 Data Book 1.0 Rev D

Ymodem support functions are made of two
parts: YmodemGetHeader and YmodemGetData.
YmodemGetHeader initiates the receive
procedure by sending poll characters (‘C’) to
the serial line. After each character it will
check for response symbol for about 1.5
seconds and re-send the poll character if no
response from host is received.
If host sends escape character (0x1B), the
YmodemGetHeader function will cancel and
exit with error (CF is set to NC).
When host responds to poll character with
either STX (0x2) or SOH (0x1), the transmission procedure continues with receiving the
packet header information from host.
During the header receive YmodemGetHeader will automatically, according to transmitted header, fill in the values at BUR
variables area for fields YmodemHdrByte,
YmodemFileSize, YModemCRChi, and
YModemCRClo.
Entry:

none

Exit:

CF – CY = header information received OK
– NC = error receiving header (error or
cancelled by user)

Uses:

flags

Page 591

9
YModemGetData
This function is second of Ymodem data
receiveing functions. It pairs with
YmodemGetHeader and can be called only
after YmodemGetHeader has been executed
successfully.
This function will receive all the actual data
records of the file transferred by Ymodem.
Data is received as “bit-bucket”, so all the
fetched data is simply stored in memory
starting from specified start address. No filenames are processed and can not be
retrieved by BUR application.
After receiving is complete, YmodemGetHeader must be executed again to check for
batch transfers. If YmodemGetHeader returns
with no-error condition, YModemGetData
must be re-executed to receive next transmission in batch.

Note also that YModemGetData takes linear
address as pointer to a receive buffer. This is
originated from the fact that YModemGetData
is able to store data anywhere within 4 Gb
memory range because data storing to
memory is always performed in linear mode.
For using this function with real-mode
addressing, addresses can be converted
using the function “Addr2Linear” (see definition above).
Entry:

EDI – linear (32-bit) memory address for
destination buffer

Exit:

EDI – points to the next byte after received
data end
CF – CY = data received OK
– NC = error during transmission

Uses:

EDI, flags

The example skeleton of the receiving
program utilizing the YModemGetXXXX functions is:

.
.
Determine address for store buffer into EDX (See
definition of “Addr2Linear” function for EDX layout)
.
.
ymodem_tryagain:
call YmodemGetHeader
jnc
yload_err

; initiate transmission
; header error, so quit

cmp
jz

byte ptr ds:[bx.YModemHdrByte], 0
ymodem_tryagain
; if empty header, try again

call

Addr2Linear

; convert EDX to linear EDI

xor

cx, cx

; reset batch transmissions counter

yload_nextfile:
call
jc

YModemGetData
NextHeader

; Header was OK, get data
; data was ok, go check if
; it is a batch transfer and there
; is more to come..

; if we are here, there was error on receiving

ZFx86 Data Book 1.0 Rev D

Page 592

9
cmp
jz
jmp
NextHeader:
inc
call
jnc

cx, 0
yload_err
yload_suspicious

; anything successfully received?
; nothing was received
; broken batch transmission

cx

; indicate that we had successful
; transmission already
YmodemGetHeader
; request for next header
yload_ok
; no header found, so we quit
; if we are here, then we have batch transmission. However,
; some Ymodem terminals like to send empty batch packet
; as terminator, so exit batch if received header was empty.

cmp
jz

byte ptr ds:[bx.YModemHdrByte], 0
yload_ok

cmp
jz

dword ptr ds:[bx.YModemFileSize], 0
yload_ok

; it IS a valid batch transmission. Go get next part.
jmp
yload_nextfile
yload_err:
.
.
Do something for error condition
.
.
jmp
yload_quit
yload_ok:
.
.
Do something for OK condition
.
.
jmp
yload_quit
yload_suspicious:
.
.
Do something for incorrect batch transmission (may be
protocol incompatibility or something else, the fact is
that some files (count is in CX) did come through OK).
.
.
jmp
yload_quit
yload_quit:

ZFx86 Data Book 1.0 Rev D

Page 593

9
YmodemSendHeader
YmodemSendHeader and YmodemSendData
are complements to the YModemGetXXXX
functions but are used for transmitting data
from ZFx86 side to the host.
The usage and operation logic is close to
receiving functions but transmitting functionality does not support batch transmissions.
The YmodemSendHeader function can take
optional destination filename as parameter.
This parameter is fetched from the BUR variables area “CmdLine” entry as third parameter
on command line. The first parameters are not
important for YmodemSendHeader functionality, so in order to specify filename, CmdLine
buffer may look as follows:
db

tion for console command “ysend 

 [filename]” , in which case we have
optional destination filename at command line
buffer third position.
This function will wait for ‘C’ characters appear
from host side and if received, send header
packet. After header it will wait for ACK and
receive additional 'C' between packet 0 and 1.
Entry:

EDI – linear address for data source (see
notes on YModemGetData). Used for
automatic destination filename creation only.
EAX
– length of the data to transmit

Exit:

CF – CY = header transmitted OK
– NC = error transmitting header

Uses:

flags

YmodemSendData

‘x x x FILENAME.DAT’, 0

If the command line buffer does not contain
third parameter (terminating zero is reached
before third parameter parse), an automatic
filename will be created based on the linear
address of data source address in form of
XXXXXXXX.DAT where XXXXXXXX represents the hexadecimal source address in
linear mode, padded with leading zeros (i.e.
‘0001FAE8.DAT’).
A kind of awkward processing of user-defined
filename is originated from the fact that
YmodemSendHeader function is used internally by BUR as immediate processing func-

Actual data transmission function for
executing after YmodemSendHeader. This
function transmits all the data packets to the
host.
Entry:

EDI – linear address for data source (see
notes on YModemGetData)
EAX – length of the data to transmit

Exit:

CF – CY = data transmitted successfully
– NC = transmission failed

Uses:

flags

The example skeleton for transmitting data
from ZFx86 side to host is very simple:

.
.
Determine address of source buffer into EDX (Seedefinition of
“Addr2Linear” function for EDX layout)
and set filename to BUR internal variables CmdLine area
if specific filename is desired.
.
.
call

Addr2Linear

; EDX -> linear EDI

call
jnc

YModemSendHeader
ysend_failed

; header transmission error, so quit

ZFx86 Data Book 1.0 Rev D

Page 594

9
call
jnc

YModemSendData
ysend_failed

; data tranismission error, so quit

.
.
OK condition handling here
.
.
jmp
ysend_quit
ysend_failed:
.
.
Failure condition handling here
.
.
ysend_quit:

ZTCMDExec
Z-tag Command processor. This routine
fetches and executes single record from Z-Tag
dongle. The executable code is always placed
starting from DownloadSegment (defined in
BUR Variables area) offset 0.
The routine fetches command data out from
dongle but assumes that Z-tag dongle is
seeked past proper record signature, i.e. next
byte fetched will be the command code
(means that 7F F0 55 must be read before this
function is called).
NOTE: This is a function used internally by
BUR and is useful ONLY when there is a need
for application program to take over the Z-tag
records executing from dongle for some
reason. Normally this is done by BUR itself
and user programs do not have a need to
modify this behavior.
Entry:

none

Exit:

none

Uses:

flags

ZFx86 Data Book 1.0 Rev D

ZT_Init
Initialize Z-tag interface. This function will
perform Z-tag interface init together with
checking the CLK to ACK loop and performs
reset on Z-tag device. The function will exit
with Z-tag device released from Reset condition (i.e. in a condition when reset is not
active).
Note that after executing this function the
connected Z-tag device will start delivering the
data from offset 0, so this function must be
used only when it is desired to fetch data from
the beginning of the device.
Use ZTPrepareRead when Z-tag interface
initialization is needed without resetting the
device and loosing the track of the data.
Entry:

none

Exit:

none

Uses:

flags

Page 595

9
ZTPrepareRead

ZTRead

Prepare Z-tag read accelerator for data
reading.

Unlike other commands defined in BURAPI,
ZTRead is a function implemented inside BUR
API itself, not as a pointer into BUR binary
code. The ZTRead function allows data
fetching from Z-tag interface utilizing ZFx86
internal Z-tag read accelerator. This simple
accelerator fetches data bits automatically
from Z-tag interface, speeding significally up
the data transfer speed between Z-tag device
and BUR application.

After Z-tag interface initialization with ZT_Init
the Z-tag interface is ready to fetch data. The
data reading procedure is performed by
accessing the register 80h in ZF-logic address
space through index and data I/O-ports
218h/21Ah.
The data read from Z-tag by accelerator is
always appearing at the byte read form
register 21Ah/80h. It is, however, unnecessary
to update the index register each time, so the
read can be done in the following way
(pseudo-code):
out
in
in

218h, 80h; select register 80h
21Ah ; get first byte
21Ah ; get second byte

etc…

The read process can therefore be possibly
speeded up by writing index only once and
then performing the multiple reads.
ZTPrepareRead is a function which selects
the register 80h from ZF-logic space. The
code that does the work for this function is:
mov
mov

dx, 218h
al, 80h
out
dx, al

It is necessary to call this function before
starting to use ZTRead function (see below)
and each time after the ZF-logic registers are
accessed between ZTRead calls. This function does not affect the behavior of the Z-tag
device nor does it reset the data pointers at
Z-Tag device.
Entry:

none

Exit:

none

Uses:

none

ZFx86 Data Book 1.0 Rev D

The read accelerator is essentially a two stage
serial to parallel converter with read ahead.
For more information about accelerated Z-tag
interface usage refer ZFx86 datasheet(s).
The ZTRead function will blink both LED
signals on Z-tag interface (LED1 and LED2)
with 1 sec period if continuous receive is
performed.
Note that this function waits until the character
is received, so it will block the operation of the
BUR application when there is no data to
receive.
The actual transfer rate is depending on the
device connected to a Z-tag interface but up to
1.2 Mbit transfer rates are possible to achieve.
For more information about the behavior of
ZTRead function please refer the
BURAPI.ASM where the actual function code
resides.
Entry:

none

Exit:

AL

Uses:

flags

– character received

Page 596

10
10. Signal Status After POST
Default control signal setting of various I/O
devices are found in the following tables.

10.1. Access Bus
Table 10.1 Access Busa Settings
Signal Name

Pin No.

Status After POST

Comment

scl_c

B12

Input with internal pull-up enabled

ACCESS BUS

sda

D13

Input with internal pull-up enabled*

ACCESS BUS

a. Not all pull ups are implemented.

10.2. Floppy Disk
Tables 10.2 and 10.3 contain Floppy Disk
signal settings for the Floppy Disk in FFD
active or Z-tag active operation mode.

10.2.1. FDD Active
Table 10.2 Floppy Disk (FDD) Settings
Signal Name

Pin No.

Status After POST

Comment

DSKCHG_N

J02

Input

Floppy Disk change. Door open.

INDEX_N

F03

Input

Floppy disk index pulse

DIR_N

G03

Output high

Floppy Head Direction. Low - in, High - out.

HDSEL_N

H01

Output high

Floppy Head select. Low indicates side zero.

RDATA_N

J04

Input

Floppy Read data.

DRV_N

F01

Output high

Floppy Selects floppy disk 0

MTR_N

F02

Output high

Floppy Selects motor driver 0

STEP_N

G04

Output high

Floppy Step head

TRK0_N

H03

Input

Floppy Track 0 indicator

WDATA_N

G02

Output high

Floppy Write Data (gated internally with wgate_n)

WGATE_N

G01

Output high

Floppy Write Enable Gate

WRPRT_N

H02

Input

Floppy Write protect

ZFx86 Data Book 1.0 Rev D

Page 597

10
10.2.2. Z-tag Active
Table 10.3 Floppy Disk (Z-tag) Settings
Signal Name

Pin No.

Status After POST

Comment

J02

Input

Z-tag general-purpose input. This can also be
used as secondary chip enable for daisychained on-board FailSafe PROM programming.

F03

Input

NOT USED for the Z-tag interface. (Floppy
disk index pulse)

G03

Output high

Must connect to Z-tag dongle through 1K ohm
resistor. This pin serves as RESET output for
external device connected to a Z-tag.

H01

Output high

The Z-tag interface has two LED outputs capable of driving the status LED’s of the device
connected.

J04

Input

Z-tag data input (referred in a document
mostly as DATA)

F01

Output high

NOT USED for the Z-tag interface. (Floppy
Selects floppy disk 0)

F02

Output high

NOT USED for the Z-tag interface. (Floppy
Selects motor driver 0)

G04

Output high

The Z-tag interface has two LED outputs capable of driving the status LED’s of the device
connected.

H03

Input

Z-tag general-purpose input

G02

Output high

Must connect to Z-tag dongle through
470 ohn resistor. This pin serves as CLK output when BUR fetches a code through Z-tag
interface.

G01

Output high

NOT USED for the Z-tag interface. (Floppy
Write Enable Gate)

Input

Acknowledge input

ZPGPI1/CEN2_N

INDEX_N

ZRST

ZLED1

ZDIN
DRV_N
MTR_N

ZLED2
ZGPI0

ZCLK

WGATE_N
ZACK

H2

ZFx86 Data Book 1.0 Rev D

Page 598

10
10.3. GPIO
Use the GPIO1, 2, 3, 5, and 6 as the
secondary IDE control signals when enabled
in BIOS.
Table 10.4 GPIOa Settings
Signal Name

Pin No.

Status After POST

Comment

GPIO[0]

AD12

Input with internal pull-up enabled

GPIO (32KHz out)

GPIO[1]

AE11

Input with internal pull-up enabled or 2nd IDE DACK

GPIO / IDE_DACK1_N

GPIO[2]

AF11

Input with internal pull-up enabled or 2nd IDE IOW

GPIO / IDE_DIOW1_N

GPIO[3]

AD11

Input with internal pull-up enabled or 2nd IDE IOR

GPIO / IDE_DIOR1_N

GPIO[4]

AF10

Input with internal pull-up enabled

GPIO

GPIO[5]

AE10

Input with internal pull-up enabled or 2nd IDE DREQ

GPIO / IDE_DREG1

GPIO[6]

AD10

Input with internal pull-up enabled or 2nd IDE IORDY

GPIO / IDE_IORDY1

GPIO[7]

AF09

Input with internal pull-up enabled

GPIO

a. Not all pull-ups are implemented.

10.4. ISA
Table 10.5 ISA Pin Settings
Signal Name

Pin No.

Status After POST

Comment

DACK1_N

A14

output/bi-dir

ISA DACK1_N/ PCI GRNT2_N (BS9)

DRQ1

B14

Input/bi-dir

ISA DRQ1/ PCI REQ2_N (BS9)

ISA_ERR_N

AB3

input

ISA Fatal bus error

10.5. PS/2
Table 10.6 PS/2 Pin Settings
Signal Name

Pin No.

Status After POST

Comment

KCLOCK_C

C12

bi-dir with internal pull-up

Keyboard Clock

KDATA

A11

bi-dir with internal pull-up

Keyboard Data

KBLOCK_N

B11

bi-dir with internal pull-up

Keyboard Lock. Blocks keyboard input.

MCLK_C

D11

bi-dir with internal pull-up

Mouse Clock

MDAT

C11

bi-dir with internal pull-up

Mouse Data

ZFx86 Data Book 1.0 Rev D

Page 599

10
10.6. PCI
Table 10.7 PCI Settings
Signal Name

Pin No.

Status After POST

Comment

PCICLK_C

U25

Input/output

PCI CLOCK (BS20)

IRQ9

D02

Input with internal pull-up

PCI_INT_ A

IRQ10

E04

Input with internal pull-up

PCI_INT_ B

IRQ11

D01

Input with internal pull-up

PCI_INT_ C

IRQ12

E03

Input with internal pull-up

PCI_INT_ D

10.7. LPT
Refer to BIOS settings.
Table 10.8 LPT Settings
Signal Name

Pin No.

Status After POST

Comment

ACK_N

K02

bi-dir-u

Printer acknowledge.

AUTOFD_N

L02

bi-dir-u

Printer auto-linefeed.

BUSY

K03

bi-dir-d

Printer busy.

STRB_N

M03

bi-dir-u

Printer Data valid strobe.

PD[0]

P03

bi-dir

Printer Data.

PD[1]

P01

bi-dir

Printer Data.

PD[2]

P02

bi-dir

Printer Data.

PD[3]

N01

bi-dir

Printer Data.

PD[4]

N02

bi-dir

Printer Data.

PD[5]

M01

bi-dir

Printer Data.

PD[6]

N03

bi-dir

Printer Data.

PD[7]

M02

bi-dir

Printer Data.

ERR_N

L01

bi-dir-u

Printer error.

INIT_N

L03

bi-dir-u

Printer Initialize printer.

SLCK

J03

bi-dir-d

Printer is selected.

PE_N

J01

bi-dir-ud

Printer Port paper end.

SLCTIN_N

K01

bi-dir-u

Printer Port select printer.

ZFx86 Data Book 1.0 Rev D

Page 600

10
10.8. IR Control (COM2)
Table 10.9 IR Control Settings
Signal Name

Pin No.

Status After POST

Comment

CTS2_N

A06

Input

CTS2_N / IR control 3 – input

DCD2_N

B08

Input

DCD2_N / IR control 2 –output

DSR2_N

C08

Input

DSR2_N / IR control 1 – output

RTS2_N

C07

Output high

RTS2_N / IR control 0 – output

10.9. ZF Logic
Table 10.10 ZF Logic Settings
Signal Name

Pin No.

Status After POST

Comment

IO_CS0

B03

Output high

ZFLogic IO chip select.

IO_CS1

A02

Output high

ZFLogic IO chip select.

IO_CS2

A01

Output high

ZFLogic IO chip select.

IO_CS3

C03

Output high

ZFLogic IO chip select.

MEM_CS1

D05

Output high

ZFLogic Memory chip select *

MEM_CS2

A03

Output high

ZFLogic Memory chip select *

MEM_CS3

C04

Output high

ZFLogic Memory chip select *

MEM_CS0

B04

Output

ZFLogic Memory chip select * #

PWM

B05

Output low

ZFLogic Pulse width modulation

WDI

A04

Input with internal pull-up

ZFLogic Watchdog timer input. Re-start timer.

WDO

C05

Output low

ZFLogic Watchdog timer output. Time-out.

ZFx86 Data Book 1.0 Rev D

Page 601

10

ZFx86 Data Book 1.0 Rev D

Page 602

11
11. Phoenix BIOS Register Settings
This chapter contains Phoenix BIOS register
settings, brief comments that may apply, and
all bits extracted from the registers. It contains
an overview of the North Bridge, and South
Bridge registers discussed in detail in
Chapters 3 and 4 of this manual.

The Phoenix BIOS version 1.03 was booted
with default settings (CMOS cleared), except
both IDE channels were enabled.
For booting MS Windows 98, default
installation was used with BootGUI=0
modification in MSDOS.SYS.

11.1. North Bridge
11.1.1. Reset, Sampling, and Misc North Bridge Registers
Table 12.1 Reset, Sampling, and Misc North Bridge Registers
Register/ Bit
100H
3:0
15:4
110H
2:0

15:3

111H
2:0

15:3

112H
2:0

15:3

Name
RID
Lambda ID
Reserved
PR1
PREG1S<2:0>

PREG1A<27:15>

PR2
PREG2S<2:0>

PREG2A<27:15>

PR3
PREG3S<2:0>

PREG3A<27:15>

ZFx86 Data Book 1.0 Rev D

Function
NB Revision ID Register
Lambda version ID.
Programmable Region 1 Register
Programmable region 1 block size:
Bit <2:0> Block size
Bit<2:0> Block size
000
32KB
100
512KB
001
64KB
1011
MB
010
128KB
11X
Reserved
011
256KB
Programmable region 1 starting address: The
programmable region starting address must be a
multiple of the block size.
Programmable Region 2 Register
Programmable region 2 block size:
Bit <2:0> Block size
Bit<2:0> Block size
000
32KB
100
512KB
001
64KB
101
1MB
010
128KB
11X
Reserved
0112
56KB
Programmable region 2 starting address: The
programmable region starting address must be a
multiple of the block size.
Programmable Region 3 Register
Programmable region 3 block size:
Bit <2:0> Block size
Bit<2:0> Block size
000
32KB
100
512KB
001
64KB
101
1MB
010
128KB
11X
Reserved
011
256KB
Programmable region 3 starting address: The
programmable region starting address must be a
multiple of the block size.

Value
0002h
2H
All 0s
0000h
0h

000h

0000h
0h

000h

0000h
0h

000h

Page 603

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
113H
2:0

15:3

114H
1:0

3:2

5:4

7:6

Name

Function

PR4
PREG4S<2:0>

Programmable Region 4 Register
Programmable region 4 block size:

PREG4A<27:15>

PRC
PRGREG1_SEL<1:0>

Bit <2:0> Block size
Bit<2:0> Block size
000
32KB
100
512KB
001
64KB
1011
MB
010
128KB
11X
Reserved
011
256KB
Programmable region 4 starting address: The
programmable region starting address must be a
multiple of the block size
Programmable Region Control Register
Programmable region 1 select<1:0>:

PRGREG2_SEL<1:0>

Bits<1:0> Function
Bits<1:0> Function
00
Disable
10
non-cacheable
01
Reserved
11
Reserved
Programmable region 2 select<1:0>:

00b

PRGREG3_SEL<1:0>

Bits<1:0> Function
Bits<1:0> Function
00
Disable
10
non-cacheable
01
Reserved
11
Reserved
Programmable region 3 select<1:0>:

00b

PRGREG4_SEL<1:0>

Bits<1:0> Function
Bits<1:0> Function
00
Disable
10
non-cacheable
01
Reserved
11
Reserved
Programmable region 4 select<1:0>:

00b

Bits<1:0> Function
00
Disable
01
Reserved
15:8
115H
0

Value

Reserved
COR
CACHE_OVR_A24

1

CACHE_OVR_A25

2

CACHE_OVR_A26

3

CACHE_OVR_A27

ZFx86 Data Book 1.0 Rev D

0000
0h

000h

0000h
0h

Bits<1:0> Function
10
non-cacheable
11
Reserved

Cacheability Override Register
Cacheability Override A24: When set, all address with
A<24> high is marked non-cacheable.This corresponds
to addresses in the range X1000000h–X1FFFFFFh.
Cacheability Override A25: When set, all address with
A<25> high is marked non-cacheable.
This corresponds to addresses in the range
X2000000h–X3FFFFFFh.
Cacheability Override A26: When set, all address with
A<26> high is marked non-cacheable.
This corresponds to addresses in the range
X4000000h–X7FFFFFFh.
Cacheability Override A27: When set, all address with
A<27> high is marked non-cacheable.
This corresponds to addresses in the range
X8000000h–XFFFFFFFh.

All “0”s
0000h
0b

0b

0b

0b

Page 604

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit

Name

4

CACHE_OVR_A28

5

CACHE_OVR_A29

6

CACHE_OVR_A30

7

CACHE_OVR_A31

15:8
117H
1:0

2

3
5:4

Reserved
BCR
NONPOST_RETRY_CNT<1:0>

NONPOST_RETRY_DIS

Reserved
POST_RETRY_CNCT<1:0>

6

POST_RETRYCNT_DIS

7
8

Reserved
RESET_CNT_ON_GNT RESET

9

HLD_RETRY_ON_REQ

15:10

Reserved

ZFx86 Data Book 1.0 Rev D

Function
Cacheability Override A28: When set, all address with
A<28> high is marked non-cacheable.
This corresponds to addresses in the range
10000000h–1FFFFFFFh.
Cacheability Override A29: When set, all address with
A<29> high is marked non-cacheable.
This corresponds to addresses in the range
20000000h–3FFFFFFFh.
Cacheability Override A30: When set, all address with
A<30> high is marked non-cacheable.
This corresponds to addresses in the range
40000000h–7FFFFFFFh.
Cacheability Override A31: When set, all address with
A<31> high is marked non-cacheable.
This corresponds to addresses in the range
80000000h–FFFFFFFFh.
Back-off Control Register
Non-posted PCI cycle retry count<1:0>
Bits<1:0> count
Bits<1:0> count
00
3
10
11
01
7
11
15
These count are effective only when another PCI
master is requestor is requesting the bus.Otherwise the
cycles will continue to be retried forever
Disable PCI retry counter for non-posted cycle:
0=
Enable
1=
Disable
Posted PCI cycle retry count<1:0>
Bits<1:0> count
Bits<1:0> count
00
3
10
11
01
7
11
15
Just like Bit[1:0], these bits are effective only when a
PCI request is active.
Disable PCI retry counter for posted cycle:
0=
Enable
1=
Disable.
retry counter on any bus master grant:
0=
not reset on grant
1=
reset on grant.
Hold retry on any PCI Bus Master Request:
0=
initiate retry once been backoff
1=
initiate retry only after all pending PCI Bus
Master requests have been serviced

Value
0b

0b

0b

0b

All “0”s
0000h
00b

0b

0b
00b

0b

0b
0b

0b

All ‘0’s

Page 605

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
118H

Name

0
1

SMMC
Reserved
KDISSMMRAM

2

DIS23RMAP

3

5:4

FRCREMAP

SMM_DL_SEL[1:0]

Function
SMM Control Register
SMM RAM KEN disable:
1=
KEN# will be inactive(high) during access to
SMM RAM
0=
KEN# will function normally within SMM
RAM.
Should always be set a ‘1’, to disallow caching.
Disable 20000h-3FFFFh remap to A0000h–BFFFFh
physical memory in SMM mode:
0=
Enabled
1=
Disabled.
Note: This bit can only be used while both L1 and L2
are disabled.
Enables the SMM remapped address to be used in a
non-SMM cycle. This is used during loading of the SMM
code to the memory. It works in conjunction with bit 14
and 15 of this register, and they need to be in the
correct state to allow the loading.
SMM D0000h–D7FFFh select<1:0>:

Value
00A6h
0b
1b

1b

0b

10b

Bits<1:0> Function
00
01
10

11

7:6

SMM_DH_SEL[1:0]

XXXD0000h–XXXD7FFFh is not used as SMM
space.
reserved
000D0000h–000D7FFFh is used as SMM space.
(Remap to 000A000h–-000A7FFFh in physical
DRAM space.)
1DFD0000h–-1DFD7FFFh is used as SMM
space. (Remap to 000A0000h–-000A7FFFh in
physical DRAM space.)

Note: When programmed to 10, 000D0000h–000D7FFFh will be automatically be set to noncacheable.
SMM D8000h-DFFFFh select<1:0>:

10b

Bits<1:0> Function
00
01
10

11

XXXD8000h–-XXXDFFFFh is not used as SMM
space.
reserved
000D8000h–-000DFFFFh is used as SMM space.
(remap to 000A8000h-000AFFFFh in physical
DRAM space.)
1DFD8000h–-1DFDFFFFh is used as SMM
space. (remap to 000A8000h–-000AFFFFh in
physical DRAM space.)

Note: When programmed to 10, 000D8000h–000DFFFFh will be automatically bet set to noncacheable.

ZFx86 Data Book 1.0 Rev D

Page 606

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
9:8

Name
SMM_EL_SEL[1:0]

Function
SMM E0000h–-E7FFFh select<1:0>:

Value
00b

Bits<1:0> Function
00
01
10

11

11:10

SMM_EH_SEL[1:0]

XXXE000h–--XXXE7FFFh is not used as SMM
space.
reserved
000E0000h–-000E7FFFh is used as SMM space.
(remap to 000B0000h-000B7FFFh in physical
DRAM space.)
1DFE0000h–-1DFE7FFFh is used as SMM
space. (remap to 000B0000h–-000B7FFFh in
physical DRAM space.)

Note: When programmed to 10, 000E0000h–000E7FFFh will be automatically bet set to noncacheable
SMM E8000h–-EFFFFh select<1:0>:

00b

Bits<1:0> Function
00
01
10

11

12

13

14

SWAP_23_MAP

SWAP_DE_MAP

LDSMIHLDER

Note: When programmed to 10, 000E8000h–000EFFFFh will be automatically bet set to noncacheable.
Swap SMM 2/3 mapping:
0=
2/3 will be mapped to A/B
1=
2/3 will be mapped to B/A.
Here 2/3 and A/B refer to the address bits 19-16.
When 0 = 2XXXX access will be mapped to AXXXX
and 3XXXX to BXXXX.
When 1 = 2XXXX access will be mapped to BXXXX
and 3XXXX to AXXXX
Swap SMM D/E mapping:
0=
D/E will be mapped to A/B
1=
D/E will be mapped to B/A.
Here again D/E and A/B refer to the address bits 19-16.
When 0 = DXXXX access will be mapped to AXXXX
and EXXXX to BXXXX.
When 1 = DXXXX access will be mapped to BXXXX
and EXXXX to AXXXX
Load SMI handler into SMM RAM:
1=
0=

ZFx86 Data Book 1.0 Rev D

XXXE8000h–-XXXEFFFFh is not used as SMM
space.
reserved
000E8000h–-000EFFFFh is used as SMM space.
(remap to 000B8000h-000BFFFFh in physical
DRAM space.)
1DFE8000h–-1DFEFFFFh is used as SMM
space. (remap to 000B8000h–-000BFFFFh in
physical DRAM space.)

0b

0b

0b

Enable access to SMM RAM during normal
cycle
Disable access to SMM RAM during normal
cycle.

Page 607

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit

Name

15

SMIHLDERLOCK

0

PROC
KENEN

1

L1WBEN

2
3

Reserved
LINEARBURST

119H

Function
SMM RAM access in normal mode lock: This bit
provides an option to lock bit 14 in a disabled state,
thereby prohibiting any further access to SMM RAM
from normal mode. This bit can only be written once.
Reading a 0 from this bit indicates that bit 14 above is
not locked. Reading a 1 from this bit indicates that bit
14 above is locked to disable state.
Processor Control Register
KEN enable: When low, KEN# will be de-asserted for all
cycles. When high, KEN# will be asserted for all local
memory cycles, except for cycles to local space which
has been explicitly marked as non-cacheable via PRC
and COR registers, or implied non-cacheable via
SMMC register or SHADRC/SHADWC registers
L1 write-back enable: This bit should normally reflect
the state of the L1 cache inside the processor. This bit
to determine how an access to shadow ROM is
handled. If it is a ‘0’, i.e. write-through state, a read to
shadow ROM is allowed to be cached (KENEN =1) and
a write to shadow ROM causes an invalidation cycle
back to the 486. If it is a ‘1’, i.e. write-back state, during
a read KENnn is returned HIGH, non-cacheable, and
on a write no Invalidation takes place, as data cannot
be in the L1 cache.
Enable linear burst: 0 = Toggle burst, 1 = Linear burst.
This bit should be set to the correct value before the L1
and L2 cache is turn on. This bit determines L2 as well
as S/DRAM burst sequencing.

Value

006Bh
1b

1b

0b
1b

Only Linear will be supported (Fixed to a ‘1’ in
hardware)
4
5

Reserved
WRFIFO_EN

6

DIS_PSLOCK

7

FLUSH

8

DIS_FPUCLR_BY_F0

ZFx86 Data Book 1.0 Rev D

Enable write FIFO: 0 = Disable, 1 = Enable. This bit
controls buffer depth of CPU-PCI write buffer and CPUSDRAM write buffer.When disabled, CPU-PCI depth =
2 CPU-SDRAM depth = 1 When enabled, CPU-PCI
depth is controlled by PCIWFIFOC register CPUSDRAM depth is controlled by WFIFOC registers Note
this bit affects the depth of the write buffer only, other
characteristics of the write buffers are still controlled by
the respective bits in the WFIFOC and PCIWFIFOC.
Disable PSLOCK – When set to ‘1’, will disable the
PSLOCK signal from being used.
Setting this bit from 0->1, will cause the core to set
FLUSHnn pin to the 486 to go LOW for 1 clock. To do
another flush this bit should be reset to ‘0’ and then set
to a ‘1’.
Disable clearing of FPU error by writing to IO port F0h:
0=
Enable clearing
1=
Disable clearing.

0b
1b

1b
0b

0b

Page 608

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit

Name

9

DIS_FPUCLR_BY_F1

10

WRM_RST

11
15:12
11AH
2:0

3

A20M
Reserved
WFIFOC
FIFOD<2:0>

DRMRDREODEREN

Function

Value

Disable clearing of FPU error by writing to IO port F1H:
0=
Enable clearing
1=
Disable clearing.
Warm Reset – When a ‘1’ is written to this bit, a warm
reset sequence will be initiated. It works same as
FLUSH bit i.e. to do another warm reset, this bit should
be cleared to ‘0’ and then set to a ‘1’
Address 20 Mask – Used for DOS compatibility.

0b

Write FIFO Control Register
Write FIFO depth
Bits<2:0> FIFO depth
Bits<2:0>
000
8 dwords
100
001
7 dwords
101
010
6 dwords
110
011
5 dwords
111
DRAM read re-ordering enable:

0b

0b
All 0’s
0220h
000b

FIFO depth
4 dwords
3 dwords
2 dwords
1 dword
0b

0=
Disable
1=
Enable.
When this bit is set and when there’s pending DRAM
write cycle, a DRAM read operation will be performed
before a DRAM write operation.
4
5

7:6
11:8

Reserved
CPU&EM_DRAM_ARBITRATION

Reserved
RD2WR_LAT<3:0>

CPU/External Master DRAM Arbitration Priority
Scheme: Bits5 Function 0 = CPU has NO Write Buffer
access while Ext. Master is accessing DRAM 1 = CPU
has Write Buffer access while Ext. Master is writing to
DRAM
Read to write pending latency<3:0>: These bits indicate
the number of clocks to delay before switching from a
read cycle back to pending cycles in the write buffer..
Bits<3:0>
0H
1H
2H
3H
4H
5H
6H
7H

13:12
15:14

Reserved
WR_LATENCY<1:0>

ZFx86 Data Book 1.0 Rev D

# of CPUCLKs
reserved
1
2
3
4
5
6
7

Bits<3:0>
8H
9H
AH
BH
CH
DH
EH
FH

1b

00b
2h

# of CPUCLKs
8
9
10
11
12
13
14
15

DRAM write latency<1:0>: These bits indicate the
number of processor clocks write are stalled before
being issued to DRAM controller.
Bits<1:0>

number of clocks

Bits<1:0>

number of clocks

00
01

1
2

10
11

3
4

00b
00b

Page 609

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
11BH

Name

0

PCIC
CPU2PCI_BURST_EN

1

PCIM2DRM_BRST_EN

2

BM_BURSTRD_ALWYS

Function

Value

PCI Control Register
CPU to PCI burst enable: When 0, Lambda will only do
single PCI transfer when CPU is accessing PCI bus.
When 1, Lambda will try to burst to PCI when CPU is
master.
PCI master to DRAM burst enable: When 0, Lambda
will only do single DRAM transfer when PCI master is
accessing DRAM. When 1, Lambda will try to do a burst
to DRAM when PCI master is accessing.
PCI master read prefetch always: When 0, only PCI
read line or PCI read multiple will start a burst read
request. For PCI single read, a burst read request will
be initiated only after the first data phase is completed
and PCI master indicated that it wants a burst access.

0217h
1b

1b

1b

When 1, any PCI read cycle will initiate a burst read
request.

3

DISC_ON_LN_BOUNDARY

4

EN_PCI_FAST_DECDE

5

EN_ADCBE_FLT_IDLE

6

DIS_RESOURCE_LOCK

Note: In order to enable this feature, bit[1] must be
enabled.
Disconnect from PCI master on CACHE line boundary:
0=
No disconnect
1=
Disconnect.
Enable PCI fast decode when accessing DRAM:
0=
Disable
1=
Enable.
Enable AD/CBE/PAR float when PCI is idle and CPU is
the bus master:
0=
Disable float
1=
Enable float.
Disable Resource Lock:

0b

1b

0b

0b

0=
Enable
1=
Disable.
If set, a LOCK cycle on the PCI bus will not cause LNB
to lock itself.

7

EN_BUS_LOCK

Note: When EN_BUS_LOCK(bit 7) is set to 1, this bit is
ignored.
Enable Bus Lock:

0b

0=
Disable
1=
Enable.
When enabled, GNT# to a particular PCI master
remains asserted until LOCK# is deasserted.
Note: When this bit is set to 1,
DIS_RESOURCE_LOCK(BIT 6) is ignored.

ZFx86 Data Book 1.0 Rev D

Page 610

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
8

Name
LCK_RDBURST_EN

Function

Value

Enable the locking of PCI bus during a 64-bit processor
read access to the PCI bus.

0b

0=
1=

9

10

CNFCY_AD_STEP_DIS

BM_DONE_DIS

Disable
Enable.

Note: Bit not used as CPU cannot do a burst read on
PCI. Refer to issue 14 in the Issues section.
PCI configuration cycle address stepping disable:
0=
Enable,
1=
Disable.
Disable the waiting of PCI master cycle is done before
starting processor initiated PCI cycle.

1b

0b

0=
Enable
1=
Disable.
When enabled, Lambda’s PCI master controller will not
start until, 1) PCI master initiated cycle is done, 2) PCI
master write buffer is empty, and 3) PCI master read
prefetch is done.
11
12
15:12
11CH
2:0
5:3

Reserved
Reserved
Reserved
CSA
Reserved
SDRAMCLK_SKEW

Clock Skew Adjust Register
There three bits control the skew between the core
clock and the SDRAM clock.
000 =
001 =
010 =
100 =
101 =
Rest =

15:6
11DH
0

1

0b
0b
All 0’s
0000h
000b
000b

Nominal
Minus 1 nS
Minus 2 nS
Plus 1 nS
Plus 2 nS
Default to Nominal

Reserved
SNOOPCTRL
DIS_SNOOP

BUS MASTER And Snooping Control Register
Disable Snooping:

DIS_CHK_HITM

0=
Enable snoop
1=
Disable snoop.
Disable the check of HITM#:

0b

0=

3:2

CK_HITM_WS<1:0>

Enable the checking of HITM# during
snooping.
1=
Disable the checking of HITM# during
snooping.
In either case, the L1 cache may be invalidated with
INVAL signal
Check HITM# wait state:

All 0’s
23D0h
0b

00b

Bits<1:0> Check HITM# wait state
00
2 clock after EADS# is deasserted.
Others – Reserved

ZFx86 Data Book 1.0 Rev D

Page 611

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
4

Name
ADP_PREF_DIS

Function
Adaptive Prefetch Disable:

Value
1b

0=
Enable
1=
Disable
When enabled, Lambda monitors the average burst
transfer length of a master access and then controls the
number of speculative prefetches accordingly.
5
6

Reserved
DIS_WB_MERGE

7

DIS_EM_PREFETCH

8

DIS_CONCURRENCY

9

FAST_TRDY

10

DIS_BUS_SNARF

11

FORCE_DRM_PM_PCIM

0=

Merge CPU/L2 Write-back data with
External Master writes. The External
Master’s valid bytes overwrite the data castout from the CPU/L2 and subsequently limit
the bandwidth requirements to the s/dram.
1=
Do not merge External Master write data
bytes with CPU/L2 write-back cycle.
0=
Prefetch next “cache” line on EM accesses,
and store in prefetch buffer
1=
Disable prefetch logic for External Masters
(CPU clock based)
CPU/PCI master concurrency disable:
0=
1=
0=
1=

Enable
Disable
Normal TRDY# timings
Enable Fast TRDY# timings to EM.
Improves path from prefetch data ready
(from CPU write-back, yes we snarf-see bit
10, or from DRAM)
0=
Snarf CPU write-back data and return it to
the requesting External Master (read),
concurrent with it’s retirement into DRAM.
1=
Disable bus snarfing and create 2nd cycle to
get data after the write-back has retired it to
DRAM.
Force DRAM page miss in bus master cycle:
0=
1=

12
13

Reserved
DISPCIM_ELY_DRM_CY

14
15

Reserved
ENPCIM_SHADOWRAM

1=
0=

1b

1b

1b

0b

0b

Disable force page miss mode
Enable force page miss mode.

Speculatively start DRAM cycle for PCI External Master
Request and restart it in the event of an L1 or L2 writeback:
0=
1=

0b
1b

0b
1b

Enable
Disable.
Claim cycle for PCI Master access to
000C0000-000F0000 region.
Do not Claim cycle for PCI Master access to
ROM space (shadowed RAM).

0b
0b

Note: All DRAM Write/Read protect bits are still
applicable

ZFx86 Data Book 1.0 Rev D

Page 612

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
11EH

Name
ARBCTRL

0

REQa_slot0

1

REQa_slot1

2

REQb_slot2

3

REQa_slot3

4

REQpci_slot4

5

PC98_support

6

SIO_HIPRI

7
15:8

11FH
0

Reserved
CPU_BUSY_TIMER

DOCKC
TS_DOCK_SIGS

Function

Value

Arbiter Control Register
See also PCI register section REG 41H
0=
Disable Slot 0 for REQa
1=
Enable Slot 0 for REQa
0=
Disable Slot 1 for REQa
1=
Enable Slot 1 for REQa
0=
Disable Slot 2 for REQb
1=
Enable Slot 2 for REQb
0=
Disable Slot 3 for REQa
1=
Enable Slot 3 for REQa
0=
Disable Slot 1 for 2nd Arbitration of PCI
1=
Enable Slot 1 for 2nd Arbitration of PCI
0=
V4REQ#/V4GNT# pair treated as such.
1=
The V4REQ#/V4GNT# pair is treated as
PHOLD#/PHLDA#
0=
Fair Arbitration between V3 & V4 REQ# pins
1=
Always give priority to V3 REQ#

0000h

Number of PCI clocks that the CPU can own the PCI
bus before it is preempted by any other active
requesters.
00h =
Never preempt the CPU
01h =
4 clks
02h =
8 clks
...FFh = 1024 clks
Docking Control Register
Tri-state DOCK_PCIRST# and DOCK_PCICLK in
normal operating mode.
0=
1=

1
2

Reserved
DOCK_RST_DASSERT

0b
0b
0b
0b
0b
0b

0b
0b
00h

0000h
0b

drive out DOCK_PCIRST# and
DOCK_PCICLK.
tri-state DOCK_PCIRST# and
DOCK_PCICLK.

Deassert DOCK_PCIRST#:
0=
1=

3

DOCK_CLK_EN

assert DOCK_PCIRST# in a low state.
DOCK_PCIRST# will follow the state of
PCIRST#.
Enable DOCK_PCICLK to toggle:

0b
0b

0=
1=

4

force DOCK_PCICLK low.
Enable DOCK_PCICLK to follow the state of
PCICLK.
DISBSERCK_DOCK_HOLD_ACK Disable the checking of the bser bit
‘DOCK_HOLD_ACK’

0b

0=
1=
14:5

Reserved

ZFx86 Data Book 1.0 Rev D

0b

Enable checking
Disable.
All 0’s

Page 613

11
Table 12.1 Reset, Sampling, and Misc North Bridge Registers (cont.)
Register/ Bit
15

120H
2:0

Name
DOCKED

PCIWFIFOC
FIFOD[2:0]

Function

Value

System DOCKed indication: This bit is used when the
PCI floating method is used. This bit is set to 1 by SMI
handler when the system is docked. This bit will be
reset to 0 when it’s previously set to 1 and
DOCK_REQ# is deasserted to indicate the completion
of the un-dock procedure.
PCI Write FIFO Control Register
PCI Write FIFO depth. This FIFO is for CPU-PCI write
transfers.

0b

Bits<2:0>
000
001
010
011
3
4
5

Reserved
Reserved
PCI_BM_FREERUNMODE

6

PCI_BM_SLOWRUNMODE

Reserved
Reserved
Reserved

ZFx86 Data Book 1.0 Rev D

Bits<2:0>
100
101
110
111

FIFO depth
8 dwords
6 dwords
4 dwords
2 dword

PCI master write buffer PCI entry count free running
mode bit. Transfer loop which copies CPU clocked write
buffer entry count to PCI clocked entry count normally
operates in an on-demand mode. This forces a free
running mode which update the PCI every 6 or 8 CPU
clocks (see slow transfer bit below).
PCI master write buffer PCI entry count slow transfer
mode. Increases transfer loop period from 6 CPU
clocks to 8 CPU clocks. Transfer loop period is how
often the PCI side entry count is updated from the CPU
entry count.
0=
1=

8:7
11:9
15:12

FIFO depth
16 dwords
14 dwords
12 dwords
10 dwords

0000h
000b

0b
0b
0b

0b

6 CPU clocks.
8 CPU clocks.
00b
All 0’s
0000b

Page 614

11
11.1.2. DRAM Registers
Table 12.2 DRAM Registers
Register/ Bit
200H

Name

0

SHADRC
LMEMRDEN0

1

LMEMRDEN1

2

LMEMRDEN2

3

LMEMRDEN3

4

LMEMRDEN4

5

MEMRDEN5

6

LMEMRDEN6

7

LMEMRDEN7

8

LMEMRDEN8

9

LMEMRDEN9

10

LMEMRDEN10

11

LMEMRDEN11

12

LMEMRDEN12

13

LMEMRDEN13

14

LMEMRDEN14

15

LMEMRDEN15

0

SHADWC
LMEMWREN0

1

LMEMWREN1

2

LMEMWREN2

3

LMEMWREN3

4

LMEMWREN4

201H

ZFx86 Data Book 1.0 Rev D

Function
Shadow RAM Read Enable Control Register
Local memory C0000h-C3FFFh read enable:
0 = Disable, 1 = Enable.
Local memory C4000h-C7FFFh read enable:
0 = Disable, 1 = Enable.
Local memory C8000h-CBFFFh read enable:
0 = Disable, 1 = Enable.
Local memory CC000h-CFFFFh read enable:
0 = Disable, 1 = Enable.
Local memory D0000h-D3FFFh read enable:
0 = Disable, 1 = Enable.
Local memory D4000h-D7FFFh read enable:
0 = Disable, 1 = Enable.
Local memory D8000h-DBFFFh read enable:
0 = Disable, 1 = Enable
Local memory DC000h-DFFFFh read enable:
0 = Disable, 1 = Enable.
Local memory E0000h-E3FFFh read enable:
0 = Disable, 1 = Enable.
Local memory E4000h-E7FFFh read enable:
0 = Disable, 1 = Enable.
Local memory E8000h-EBFFFh read enable:
0 = Disable, 1 = Enable.
Local memory EC000h-EFFFFh read enable:
0 = Disable, 1 = Enable
Local memory F0000h-F3FFFh read enable:
0 = Disable, 1 = Enable.
Local memory F4000h-F7FFFh read enable:
0 = Disable, 1 = Enable.
Local memory F8000h-FBFFFh read enable:
0 = Disable, 1 = Enable.
Local memory FC000h-FFFFFh read enable:
0 = Disable, 1 = Enable.
Shadow RAM Write Enable Control Register
Local memory C0000h-C3FFFh write enable:
0 = Disable, 1 = Enable.
Local memory C4000h-C7FFFh write enable:
0 = Disable, 1 = Enable.
Local memory C8000h-CBFFFh write enable:
0 = Disable, 1 = Enable.
Local memory CC000h-CFFFFh write enable:
0 = Disable, 1 = Enable.
Local memory D0000h-D3FFFh write enable:
0 = Disable, 1 = Enable.

Value
0FF03h
1b
1b
0b
0b
0b
0b
0b
0b
1b
1b
1b
1b
1b
1b
1b
1b
0000h
0b
0b
0b
0b
0b

Page 615

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit

Name

5

LMEMWREN5

6

LMEMWREN6

7

LMEMWREN7

8

LMEMWREN8

9

LMEMWREN9

10

LMEMWREN10

11

LMEMWREN11

12

LMEMWREN12

13

LMEMWREN13

14

LMEMWREN14

15

LMEMWREN15

202H
7:0
8
11:9

N_B0C
B0A<27:20>
Reserved
B0S<2:0>

Function
Local memory D4000h-D7FFFh write enable:
0 = Disable, 1 = Enable.
Local memory D8000h-DBFFFh write enable:
0 = Disable, 1 = Enable.
Local memory DC000h-DFFFFh write enable:
0 = Disable, 1 = Enable.
Local memory E0000h-E3FFFh write enable:
0 = Disable, 1 = Enable.
Local memory E4000h-E7FFFh write enable:
0 = Disable, 1 = Enable.
Local memory E8000h-EBFFFh write enable:
0 = Disable, 1 = Enable.
Local memory EC000h-EFFFFh write enable:
0 = Disable, 1 = Enable.
Local memory F0000h-F3FFFh write enable:
0 = Disable, 1 = Enable.
Local memory F4000h-F7FFFh write enable:
0 = Disable, 1 = Enable.
Local memory F8000h-FBFFFh write enable:
0 = Disable, 1 = Enable.
Local memory FC000h-FFFFFh write enable:
0 = Disable, 1 = Enable.
Bank 0 Control Register
Bank 0 starting address <27:20>
Bank 0 DRAM size
Bits<2:0>

14:12

15
204H
1:0

3:2

COLADR0<2:0>

Value

DRAM bank size

Bits<2:0>

0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0000h
00h
0b
000b

DRAM bank size

000
2MB
100
32MB
001
4MB
101
64MB
010
8MB
110
Reserved
011
16MB
111
Reserved
Number of column address bits for Bank 0<2:0>
Bits<2:0>

Column address

Bits<2:0>

000
0101

8 bits
0 bits

001
9 bits
all others Reserved

000b

Column address

Reserved
N_B0TC
B0_TRP

Bank 0Timing Control Register
SDRAM Pre-charge cmd to ACT cmd

B0_TRC

Bits<1:0> Time
Bits<1:0> Time
00
Reserved
10
3T
01
2T
11
4T
SDRAM ACT cmd to ACT cmd (same bank)

0b
0FC71h
01b

00b

Bits<3:2> Addr. hold time Bits<3:2> Addr. hold time
00
6T
10
8T
01
7T
11
9T
This field is actually not used by the hardware. TRC is
fixed to 9T.

ZFx86 Data Book 1.0 Rev D

Page 616

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit
6:4
7
8
9
15:10
205H
7:0
8
11:9

Name
Reserved
B0_CAS_LATCY
B0_TRCD
B0_TCCD
Reserved
N_B1C
B1A<27:20>
Reserved
B1S<2:0>

Function
SDRAM CAS Latency: 0 = 2T, 1 = 3T Should be same as
what is programmed in SDRAM via SDRAMMPR.
SDRAM ACT cmd to R/W cmd delay: 0 = 2T, 1 = 3T
SDRAM R/W cmd to R/W cmd: 0 = 1T, 1 = 2T
Bank 1 Control Register
Bank 1 starting address <27:20>
Bank 21DRAM size
Bits<2:0>

14:12

15
207H
1:0

3:2

COLADR1<2:0>

Value

DRAM bank size

Bits<2:0>

111b
0b
0b
0b
All ‘1’s
0000h
00h
0b
000b

DRAM bank size

000
2MB
100
32MB
001
4MB
101
64MB
010
8MB
110
Reserved
011
16MB
111
Reserved
Number of column address bits for Bank 2<2:0>
Bits<2:0>

Column address

Bits<2:0>

000
010

8 bits
10 bits

001
9 bits
all others Reserved

000b

Column address

Reserved
N_B1TC
B1_TRP

Bank 1 Timing Control Register
SDRAM Pre-charge cmd to ACT cmd

B1_TRC

Bits<1:0> Time
Bits<1:0> Time
00
Reserved
10
3T
01
2T
11
4T
SDRAM ACT cmd to ACT cmd (same bank)

0b
0FC71h
01b

00b

Bits<3:2> Addr. hold time Bits<3:2> Addr. hold time
00
6T
10
8T
01
7T
11
9T
This field is actually not used by the hardware. TRC is
fixed to 9T.
6:4
7

Reserved
B1_CAS_LATCY

8

B1_TRCD

9

B1_TCCD

15:10
208H
7:0
8

Reserved
N_B2C
B2A<27:20>
Reserved

ZFx86 Data Book 1.0 Rev D

SDRAM CAS Latency: 0 = 2T, 1 = 3T Should be same as
what is programmed in SDRAM via SDRAMMPR.
SDRAM ACT cmd to R/W cmd delay:
0 = 2T
1 = 3T
SDRAM R/W cmd to R/W cmd:
0 = 1T
1 = 2T
Bank 2 Control Register
Bank 2 starting address <27:20>

111b
0b
0b

0b

All ‘1’s
1800h
00h
0b

Page 617

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit
11:9

Name
B2S<2:0>

Function
Bank 2 DRAM size
Bits<2:0>

14:12

15
20AH
1:0

3:2

COLADR2<2:0>

Value

DRAM bank size

100b
Bits<2:0>

DRAM bank size

000
2MB
100
32MB
001
4MB
101
64MB
010
8MB
110
Reserved
011
16MB
111
Reserved
Number of column address bits for Bank 4<2:0>
Bits<2:0>

Column address

Bits<2:0>

000
010

8 bits
10 bits

001
9 bits
all others Reserved

001b

Column address

Reserved
N_B2TC
B2_TRP

0
0FC71h
01b

Bank 2 Timing Control Register
SDRAM Pre-charge cmd to ACT cmd

B2_TRC

Bits<1:0> Time
Bits<1:0> Time
00
Reserved
10
3T
01
2T
11
4T
SDRAM ACT cmd to ACT cmd (same bank)

00b

Bits<3:2> Addr. hold time Bits<3:2> Addr. hold time
00
6T
10
8T
01
7T
11
9T
This field is actually not used by the hardware. TRC is
fixed to 9T.
6:4
7
8

9

Reserved
B2_CAS_LATCY
B2_TRCD

SDRAM CAS Latency: 0 = 2T, 1 = 3T Should be same as
what is programmed in SDRAM via SDRAMMPR.
SDRAM ACT cmd to R/W cmd delay:

B2_TCCD

0 = 2T
1 = 3T
SDRAM R/W cmd to R/W cmd:

111b
0b
0b

0b

0 = 1T
1 = 2T
15:10
20BH
7:0
8
11:9

Reserved
N_B3C
B3A<27:20>
Reserved
B3S<2:0>

Bank 3 DRAM size
Bits<2:0>

14:12

15

COLADR3<2:0>

Reserved

ZFx86 Data Book 1.0 Rev D

All ‘1’s
1820h
20h
0b
100b

Bank 3 Control Register
Bank 3 starting address <27:20>

DRAM bank size

Bits<2:0>

DRAM bank size

000
2MB
100
32MB
00
14MB
101
64MB
010
8MB
110
Reserved
01
116MB
111
Reserved
Number of column address bits for Bank 6<2:0>
Bits<2:0>

Column address

Bits<2:0>

000
010

8 bits
10 bits

001
9 bits
all others Reserved

001b

Column address

0b

Page 618

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit
20DH
1:0

3:2

Name

Function

B_B3TC
B3_TRP

Bank 3 Timing Control Register
SDRAM Pre-charge cmd to ACT cmd

B3_TRC

Bits<1:0> Time
Bits<1:0> Time
00
Reserved
10
3T
01
2T
11
4T
SDRAM ACT cmd to ACT cmd (same bank)

Value
0FC71h
01b

00b

Bits<3:2> Addr. hold time Bits<3:2> Addr. hold time
00
6T
10
8T
01
7T
11
9T
This field is actually not used by the hardware. TRC is
fixed to 9T.
6:4
7

8

9
15:10
20EH
2:0
5:3

Reserved
B3_CAS_LATCY

SDRAM CAS Latency:

B3_TRCD

0=
2T
1=
3T
Should be same as what is programmed in SDRAM via
SDRAMMPR.
SDRAM ACT cmd to R/W cmd delay:

B3_TCCD
Reserved
DCONF1
Reserved
DRAM_INAT_TO

0=
2T
1=
3T
SDRAM R/W cmd to R/W cmd: 0 = 1T, 1 = 2T
DRAM Configuration Register 1
DRAM inactive time-out<2:0>

111b
0b

0b

0b
All ‘1’s
0000h
000b
000b

Bits<2:0> Page size
Bits<2:0> Page size
000
never
100
512T
00
18T
101
reserved
010
32T
110
reserved
011
128T
111
immediate
If SDRAM interface is inactive for the set amount of time,
a Pre-charge cycle is generated at the end of timeout.
Pre-charge cycle would de-activate the DRAM row which
may be in “ACTIVE” state. Doing a Pre-charge cycle
when SDRAM is in-active for a while will save power. But
next memory cycle may be to the row which was just
closed, will take a hit of running a RAS cycle causing
lower performance.
7:6
8
9
10

Reserved
Reserved
Reserved.
Reserved.

ZFx86 Data Book 1.0 Rev D

Fixed to ‘0’ in hardware.

00b
0b
0b
0b

Page 619

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit
11

Name
SDRAM_CMD_PIPELINE

Function
SDRAM command pipeline enable:

0b

0=

12

13

EN_RELAX_SDRM_CMD_T
MING

EN_SDRM_PWRDN

Disable the pipelining of SDRAM command
cycle.
1=
Enable the pipelining of SDRAM command
cycle.
If enabled this bit would allow a new command to be
sampled from the Writebuffer as son as the present cycle
has been started. Since 486 does not pipeline cycles,
there may not be much difference in cycle times whether
this bit is a 1 or 0.
Enable relax timing for SDRAM command cycle.

Value

0b

0=
1=

Ddisable
Enable relax timing to the SDRAM command
cycle.
=1 MA, RAS, CAS and WE are asserted 1 clk before CS
is asserted.
Note: setting this bit to 1 will not affect performance but
at the same time, allow the potential of not buffering MA,
SDRAM_RAS, SDRAM_CAS, and WE# externally.
Enable SDRAM power-down mode during mix DRAM
type configuration:
0=
1=

14

FST_SDRM_RD_L2_EN

15
0

Reserved
DCONF2
BANK0_16EN

1

BANK1_16EN

2

BANK2_16EN

3

BANK3_16EN

4
5
6
7
8

Reserved
Reserved
Reserved
Reserved
BANK0_32EN

20FH

ZFx86 Data Book 1.0 Rev D

Disable
Enable SDRAM to get into power-down mode
during mix DRAM type configuration and
when access is to anywhere other than
SDRAM.
FW should always set this bit to ‘0’
Enable fast SDRAM read access when L2 is on:
0=
Disable
1=
Enable.
FW should always set this bit to ‘0’

0b

DRAM Configuration Register 2
Bank 0 enable: 0 = Disable, 1 = Enable.
When enabled, bank 0 will operate as a 16bit bank.
Bank 1 enable: 0 = Disable, 1 = Enable.
When enabled, bank 1 will operate as a 16bit bank.
Bank 2 enable: 0 = Disable, 1 = Enable.
When enabled, bank 2 will operate as a 16 bit bank.
Bank 3 enable: 0 = Disable, 1 = Enable.
When enabled, bank 3 will operate as a 32 bit bank.

0 = Bank 0 disabled (bit0 overides this)
1 = Bank 1 enabled as 32 bit bank (this bit overides bit 0)

0b

0b
0C00h
0b
0b
0b
0b
0b
0b
0b
0b
0b

Page 620

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit

Name

9

BANK1_32EN

10

BANK2_32EN

11

BANK3_32EN

15:12
211H
0
2:1
4:3
7:5

Reserved
DRFSHC
Reserved
Reserved
Reserved
REFRPRD<2:0>

Function

Value

0 = Bank 0 disabled (bit1 overides this)
1 = Bank 1 enabled as 32 bit bank (this bit overides bit 1)
0 = Bank 0 disabled (bit2 overides this)
1 = Bank 1 enabled as 32 bit bank (this bit overides bit 2)
0 = Bank 0 disabled (bit3 overides this)
1 = Bank 1 enabled as 32 bit bank (this bit overides bit 3)

0b

DRAM Refresh Control Register

Refresh period: These bits determine the refresh period
for local DRAM.
Bits<2:0>
000
010
011

9:8
10
11

13:12
15:14
213H
0

2:1

4:3

Reserved
Reserved
MANUAL_REFRESH

Refresh period
15us
15us
30us

1b
0h
0000h
0b
00b
00b
000b

Bits<2:0> Refresh period
001
15us
all others stopped

Manual refresh control: A 1-> 0->1 will generate a refresh
cycle after 128 process clocks. Also, this bit will force
normal refresh disabled while left at the 1 setting.

Reserved
Reserved
SDRAMMPR
EN_SDRAM_CONFIG

SDRAM Mode Program Register
Enable SDRAM MRS configuration cycle:
0 = Disable,
1 = Enable.
SDRAM_BANK_CONFIG[1:0 SDRAM bank configuration select<1:0>:
]
SDRAM bank configuration select <1:0> programming
options as follows:

POWERON_SEQ[1:0]

1b

Bits<1:0> DRAM bank
00
Bank 0
01
Bank 1
10
Bank 2
11
Bank 3
SDRAM Power-on initialization sequence bits<1:0>

00b
0b
0b

00b
00b
0226h
0b

11b

00b

Bits<1:0> Function
00
Normal
01
Pre-charge SDRAM bank specified by
BANK_CONFIG[1:0]
10
Trigger Mode Program Register Command
11
Trigger CBR refresh cycle

ZFx86 Data Book 1.0 Rev D

Page 621

11
Table 12.2 DRAM Registers (cont.)
Register/ Bit
15:5

Name
WCBR_MA[11:1]

Function
MA[0] comes from the SDRAMMPEX register as it is
needed to handle 16 bit banks to do 8 burst cycles
[2:0]

[3]
[6:4]

214H
0
15:1
218H
239H
2:0

SDRAMMPREX
WCBR_MA[0]
Reserved
Reserved
SDRAMSLEW
MD_DQM_SLEW

5:3

MA_SLEW

8:6

RAS_CAS_SLEW

11:9
14:12
15

WE_SLEW
CS_SLEW
DATA_BUS_HOLD

ZFx86 Data Book 1.0 Rev D

Value
11h

set to ‘010’ corresponding to burst length of 4
for 32 bit banks
set to ‘011’ corresponding to burst length of 8
for 16 bit banks
always set to 0 = linear burst type (Fixed in
hardware)
010=CAS Latency=2, 011=CAS Latency=3,
Others Reserved [11:7]Always leave at
‘00000’

Note: MA[13:12] will be forced to 0 always during
SDRAM configuration cycle
SDRAM Mode Program Register
SDRAM Mode Register bit 0 used together with bits 11:1
defined earlier.

0000h
0b
0h

SDRAM Slew Control Register
32 Bit Data and 4 Bit Mask Bus: MD[31:0], DQM[3:0]
000 =
Force Tri-State
001 =
2*N-ch + 4*P-ch
010 =
3*N-ch + 6*P-ch
011 =
5*N-ch + 10*P-ch
100 =
4*N-ch + 8*P-ch
101 =
6*N-ch + 12*P-ch
110 =
7*N-ch + 14*P-ch
111 =
8*N-ch + 16*P-ch
14 Bit Address Bus: BA[1:0], MA[11:0] Encoding same as
for 2:0 bits
RAS and CAS Controls: RASnn and CASnn Encoding
same as for 2:0 bits
Write Enable: Wenn Encoding same as for 2:0 bits
4 Chip Select: Csnn[3:0] Encoding same as for 2:0 bits
Data Bus Holder enabled when LOW

1249h
001b

001b
001b
001b
001b
0b

Page 622

11
11.1.3. Power Management Registers
Table 12.3 Power Management Registers
Register/ Bit
300H
15:0
3FFH
0

Name
CC
Reserved
CC2
EN_STOP_CPU_CLK

1

EN_SDRAM_CKE_RST

2

EN_STOP_SDRAM_CLK

3

EN_STOP_CORE_CLK

15:4

Reserved

ZFx86 Data Book 1.0 Rev D

Function

Value

Clock Control Register

0000h

Clock Control2 Register
Enables stopping of CPU clock during Suspend
mode. Stopping the clock conserve much more
power than mere putting CPU in Suspend mode.
This bit is provided to let the BIOS decide to do
that or not. For this bit to function bit1 should also
be set.
Enables resetting of SDRAM CKE input during
Suspend mode.
Enables stopping of SDRAM CLK during Suspend
mode. This different from SDRAMCLK disable bit
in CSA, which disables the clock always. Whereas
this bit is used only during Suspend mode. For this
bit to function bit1 should also be set.
Enable stopping of core clock during Suspend
mode. When set to ‘1’, it will stop clocks to most of
the cores except clocks needed to detect end of
suspend mode. For this bit to function bit1 should
also be set.

0000h
0b

0b
0b

0b

All "0"s

Page 623

11
11.1.4. PCI Configuration Registers
Table 12.4 PCI Configuration Registers
Register/ Bit
00H
15:0
02h
31:16
04H
0
1

Name
VID
VENDOR_ID
DID
DEVICE_ID
COMMD
Reserved
MEM_RESPOND

Function
Vendor ID Register
Vendor ID number. These bits are hard-wired.
Device ID Register
Device ID number. These bits are hard-wired.
Command Register
Memory space enable:

Value
100Bh
100BH
0023h
0023H
0006h
0
1b

When 0, PCI master access to main memory is disabled.
When 1, PCI master access to main memory is enabled.
5:2
6

Reserved
PARERR_REP

Parity Error Respond:

0001b
0b

When 1, Lambda will assert PERR# when a PCI parity error is
detected.
When 0, Lambda will not assert PERR# when a PCI parity
error is detected.
8:7
15:9
22:16
23

Reserved
Reserved
STAT
Reserved
FAST_B2B_STAT

24

DATA_PAR_DET

06H

26:25

DEVSEL_TIM

Status Register
Fast Back-to-Back status – This bit is when
EN_PCI_FAST_DCD bit in the PCIC register is set. This bit
indicates that LNB as a target can accept fast back-to-back
cycles from another master.
Data Parity Detected: This bit will be set when operating as a
bus master and either the PERR# output is driven low by
Lambda or the target asserts PERR# and bit 6 of the Device
Control Register is set. This bit can be reset by writing a 1.
DEVSEL Timing: These bits indicate the slowest time that
LNB will return DEVSEL#.

00b
0h
2280h
All ‘0’s
1b

0b

01b

00 =
fast,
01 =
medium
10 =
slow
11 =
reserved.
These bits are hard-wired to 01
27
28

Reserved
REC_TAG_ABRT

29

REC_MST_ABRT

30
31

Reserved
DET_PAR_ERR

ZFx86 Data Book 1.0 Rev D

Receive Target Abort: Reading a 1 indicates receiving a target
abort condition. This bit can be reset by writing a 1.
Receive Master Abort: Reading a 1 indicates receiving a
master abort condition(not including master abort generated
from a special cycle). This bit can be reset by writing a 1.
Detect parity error: When Lambda detect a PCI parity error,
this bit will be set to 1. This bit can be reset by writing a 1.

0b
0b
1b

0b
0b

Page 624

11
Table 12.4 PCI Configuration Registers (cont.)
Register/ Bit
08H

Name

15:8

RID
REVISION_ID
CLASS
CLASS_CODE
LTMR
LAT_TIM

2:0

ARB_ROUTE
REQa_MAP

7:0
09h
31:8
0DH

40H

3
6:4

7
10:8

11
14:12

15

REQa_PREEMPT
REQb_MAP

REQb_PREEMPT
REQc_MAP

REQc_PREEMPT
REQd_MAP

REQd_PREEMPT

18:16
19
22:20

Reserved
Reserved
V3_REQ_MAP

23

V3_PREEMPT

26:24
27
28

Reserved
Reserved
MASKALLREQ

31:29

Reserved

ZFx86 Data Book 1.0 Rev D

Function
Revision ID Register
Revision ID number. These bits are hard wired.
Class Register
Class Code. These bits are hard-wired.
Latency Timer Register
Latency Timer: Maximum Number of PCI clocks for Lambda
initiated Burst cycles.
PCI Arbiter Routing Register
000 =
REQ0#/GNT0#
001 =
REQ1#/GNT1#
010 =
REQ2#/GNT2#
011 =
REQ3#/GNT3#
0=
REQa is non-preemtable
1=
REQa is pre-emptable
000 =
REQ1#/GNT1#
001 =
REQ2#/GNT2#
010 =
REQ3#/GNT3#
101 =
REQ0#/GNT0#
0=
REQc is non-preemtable
1=
REQb is preemptable
000 =
REQ2#/GNT2#
001 =
REQ3#/GNT3#
100 =
REQ0#/GNT0#
101 =
REQ1#/GNT1#
0=
REQc is non-preemtable
1=
REQc is preemptable
000 =
REQ3#/GNT3#
011 =
REQ0#/GNT0#
100 =
REQ1#/GNT1#
101 =
REQ2#/GNT2#
0=
REQd is non-preemtable
1=
REQd is preemptable

000 =
001 =
010 =
011 =
100 =
0=
1=

1=
0=

SB_REQ#/SB_GNT#
REQ0#/GNT0#
REQ1#/GNT1#
REQ2#/GNT2#
REQ3#/GNT3#
V3 REQ# is non-preemptable
V3 REQ is preemptable

mask all REQ’s (for dram initialization)
unmask all REQ’s

Value
00h
00h
060000h
060000h
0000h
00h
0000h
000b

0b
000b

0b
000b

0b
000b

0b
000b
0b
000b

0b
000b
0b
0b
000b

Page 625

11
11.2. South Bridge
11.2.1. Floppy Disk Controller
(SIO LDN 00h)
Table 12.5 Floppy Disk Controller Registers
Register/ Bit
30H

60H
61H
7Hh
71H

Name

Function

Value

LDN activate

Bit 0:

01h

LDN Base addr MSB
LDN Base addr LSB
LDN IRQ
LDN IRQ type select

1=
device enabled
0=
device disabled
Bits 7-3 (for A15-11) are read only, 00000b.
Bits 2 and 0 (for A2 and A0) are read only, 00b.
Interrupt Number R/W
Bit 1 is read/write; other bits are read only. Indicates
the type and level of the interrupt request number
selected in the previous register.

03h
F0h
06h
03h

Bit 0 –

74H

LDN DMA Select 0

Type of interrupt request selected in
previous register
0 = Edge
1 = Level
Bit 1 –
Level of interrupt request selected in
previous register
0 = Low polarity
1 = High polarity
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

02h

Bits 2-0 select the DMA channel for DMA 0. The
valid choices are 0-3, where a value of 0 selects
DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The
valid choices are 0-3, where a value of 0 selects
DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
F0H
0

2:1

LDN Config
TRI-STATE Control

Reserved

ZFx86 Data Book 1.0 Rev D

The values 5-7 are reserved.
FDC Configuration register R/W
When enabled and the device is inactive, the logical
device output pins are in TRI-STATE.
0 = Disabled (Default)
1 = Enabled
Reset value of bit 2 is 1.

24h
0b

10b

Page 626

11
Table 12.5 Floppy Disk Controller Registers (cont.)
Register/ Bit
3

Name
Write Protect

4
5

Reserved
DENSEL Polarity Control

6

TDR Register Mode

7

Four Drive Control

F1H
1:0

LDN Drive ID
Drive 0 ID

3:2

Drive 1 ID

7:4

Reserved

Function
This bit allows forcing of write protect by software.
When set, write to the floppy disk drive is disabled.
This effect is identical to WP when it is active.
0 = Write protected according to WP signal (Default)
1 = Write protected regardless of value of WP signal
Must be 0
0 = Active low for 500 Kbps or 1 Mbps data rates
1 = Active high for 500 Kbps or 1 Mbps data rates
(Default)
0 = PC-AT compatible drive mode; i.e., bits 7-2 of the
TDR are ignored (Default)
1 = Enhanced drive mode
0 = Two floppy drives directly controlled by DR1-0
and MTR1-0 (Default)
1 = Four floppy drives controlled with the aid of
external logic
(One floppy only present in ZFx86)
Drive ID register
When drive 0 is accessed, these bits are reflected on
bits 5-4 of the TDR register, respectively.
When drive 1 is accessed, these bits are reflected on
bits 5-4 of the TDR register, respectively.

Value
0b

0b
1b

0b

0b

00h
00b
00b
0000b

12.2.1.1. Floppy Disk Controller Bitmap

Summary

Table 12.6 Floppy Disk Controller Bitmap Summary
Register/ Bit
00H1

Name
SRA

0
1
2
3
4
5
6
7
01H1

SRB
0
1
2
3
4
5
7:6

ZFx86 Data Book 1.0 Rev D

Function
Status A
Head Direction
WP#
INDEX#
Head Select
TRK0#
Step
Reserved
IRQ pending
Status B
MTR0#
Reserved
WGATE#
RDATA#
WDATA#
Drive Select 0 status
Reserved

Value
0FFh
1b
1b
1b
1b
1b
1b
1b
1b
0FFh
1b
1b
1b
1b
1b
1b
10b

Page 627

11
Table 12.6 Floppy Disk Controller Bitmap Summary (cont.)
Register/ Bit
02H

Name
DOR

1:0
2
3
4
7:5
03H

TDR
1:0
3:22
5:42
7:6

04H

MSR
0
1
2
3
4
5
6
7

05H

FIFO
7:0

06H

DIR
6:0
7

07H

DIR
6:0
7

Function
Digital Output
Drive select
Reset controller
DMAEN
Motor Enable 0
Reserved
Tape Drive
Tape Drive select 1,0
Logical Drive exchange
Drive ID information
Reserved
Main Status
Drive 0 busy
Drive 1 busy
Drive 2 busy
Drive 3 busy
Command in progress
Non-DMA execution
Data I/O direction
RQM
Data (FIFO)
Data bits
Digital Input
Reserved
DSKCHG#
Digital Input
Reserved
DSKCHG#

Value
0Ch
00b
1b
1b
0b
000b
0FCh
00b
11b
11b
11b
80h
0b
0b
0b
0b
0b
0b
0b
1b
02h
2h
7Fh
1111111b
0b
7Fh
1111111b
0b

1. Applicable only in PS/2 Mode
2. Applicable only in Enhanced TDR Mode

ZFx86 Data Book 1.0 Rev D

Page 628

11
11.2.2. Parallel Port
SIO LDN 01
Table 12.7 Parallel Port Registers
Register/ Bit
30H

Name
LDN Activate

60H

LDN Base addr MSB

61H

LDN Base addr LSB

70H
71H

LDN IRQ
LDN IRQ Type Select

Function
Bit 0:
1=
device enabled
0=
device disabled
Bits 7-3 (for A15-11) are read only, 00000b.
Bit 2 (for A10) should be 0b.
Bits 1 and 0 (A1 and A0) are read only, 00b.
For ECP Mode 4 (EPP) or when using the Extended
registers, bit 2 (A2) should also be 0b.
Interrupt number
Indicates the type and level of the interrupt request
number selected in the previous register.

00h

03h
78h

00h
02h

Bit 0 =

74H

LDN DMA Select 0

Type of interrupt request selected in
previous register
0 = Edge
1 = Level
Bit 1 =
Level of interrupt request selected in
previous register
0 = Low polarity
1 = High polarity
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

Value

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA
channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA
channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
The values 5–7 are reserved.

ZFx86 Data Book 1.0 Rev D

Page 629

11
Table 12.7 Parallel Port Registers (cont.)
Register/ Bit
0F0H
0

1

Name

Function

LDN Config
TRI-STATE Control

Parallel port configuration register
When enabled and the device is inactive, the logical
device output pins are in TRI-STATE.

Power Mode Control

0=
Disabled (Default)
1=
Enabled
When the logical device is active:
0=

1=

3:2
4

Reserved
Extended Register Access

7:5.

Reserved

Value
0E2h
0b

1b

Parallel port clock disabled. ECP modes
and EPP time-out are not functional when
the logical device is active. Registers are
maintained.
Parallel port clock enabled. All operation
modes are functional when the logical
device is active (Default).

0=

Registers at base (address) + 403h, base +
404h and base + 405h are not accessible
(reads and writes are ignored).
1=
Registers at base (address) + 403h, base +
404h and base + 405h are accessible. This
option supports run-time configuration
within the Parallel Port address space.
Must be 111

00b
0b

111b

11.2.3. Serial Port 1
SIO LDN 02
Table 12.8 Serial Port 1 Registers
Register/ Bit
30H

60H
61H
70H
71H

Name
LDN Activate

LDN Base addr MSB
LDN Base addr LSB
LDN IRQ
LDN IRQ Type Select

Function
Bit 0:

Bit 1 =

ZFx86 Data Book 1.0 Rev D

01h

1=
device enabled
0=
device disabled
Bits 7-3 (for A15-11) are read only, 00000b.
Bits 2:0 (for A2:0) are read only, 000b.
Interrupt number
Indicates the type and level of the interrupt request
number selected in the previous register.
Bit 0 =

Value

02h
0F8h
03h
03h

Type of interrupt request selected in
previous register
0 = Edge
1 = Level
Level of interrupt request selected in
previous register
0 = Low polarity
1 = High polarity

Page 630

11
Table 12.8 Serial Port 1 Registers (cont.)
Register/ Bit
74H

Name
LDN DMA Select 0

Function
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

Value
04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA
channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA
channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
0F0H
0

1

LDN Config
TRI-STATE Control

Power Mode Control

The values 5-7 are reserved.
Serial port configuration register
This bit controls the TRI-STATE status of the device
output pins when it is inactive (disabled).
0=
Disabled (Default)
1=
Enabled when device inactive
When the logical device is active in:
0=

82h
0b

1b

Low power mode. Serial Ports 1 and 2
clock disabled. The output signals are set
to their default states. The RI input signal
can be programmed to generate an
interrupt. Registers are maintained.
(Unlike Active bit in Index 30 that also
prevents access to Serial Ports 1 or 2
registers.)

1=

2

BUSY

Normal power mode. Serial Ports 1 and 2
clock enabled. Serial Ports 1 and 2 are
functional when the respective logical
devices are active (Default).
This read only bit can be used by power
management software to decide when to powerdown

0b

Serial Ports 1 and 2 logical devices.
0 = No transfer in progress (Default).
1 = Transfer in progress.
6:3
7

Reserved
Bank select

Enables bank switching for Serial Ports 1 and 2.

0000b
1b

0 = Disabled (Default).
1 = Enabled

ZFx86 Data Book 1.0 Rev D

Page 631

11
11.2.4. Serial Port 2
SIO LDN 03
Table 12.9 Serial Port 2 Registers
Register/ Bit
30H

Name
LDN Activate

60H
61H
70H
71H

LDN Base addr MSB
LDN Base addr LSB
LDN IRQ
LDN IRQ Type Select

Function
Bit 0:

Value
00h

1=
Device enabled
0=
Device disabled
Bits 7-3 (for A15-11) are read only, 00000b.
Bits 2:0 (for A2:0) are read only, 000b.
Interrupt number
Indicates the type and level of the interrupt request
number selected in the previous register.
Bit 0 =

74H

LDN DMA Select 0

Type of interrupt request selected in previous
register
0 = Edge
1 = Level
Bit 1 =
Level of interrupt request selected in previous
register
0 = Low polarity
1 = High polarity
Indicates selected DMA channel for DMA 0 of the logical
device (0 – The first DMA channel when using more than
one DMA channel).

03h
0F8h
04h
03h

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA channel
0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the logical
device (0 – The first DMA channel when using more than
one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA channel
0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
0F0H
0

LDN Config
TRI-STATE Control

The values 5-7 are reserved.
Serial port configuration register
This bit controls the TRI-STATE status of the device
output pins when it is inactive (disabled).
0=
1=

ZFx86 Data Book 1.0 Rev D

02h
0b

Disabled (Default)
Enabled when device inactive

Page 632

11
Table 12.9 Serial Port 2 Registers (cont.)
Register/ Bit
1

Name
Power Mode Control

Function

Value

When the logical device is active in:
0=

1b

Low power mode. Serial Ports 1 and 2 clock
disabled. The output signals are set to their
default states. The RI input signal can be
programmed to generate an interrupt.
Registers are maintained. (Unlike Active bit in
Index 30 that also prevents access to Serial
Ports 1 or 2 registers.)

1=

2

Normal power mode. Serial Ports 1 and 2
clock enabled. Serial Ports 1 and 2 are
functional when the respective logical devices
are active (Default).
This read only bit can be used by power management
software to decide when to power-down

BUSY

0b

Serial Ports 1 and 2 logical devices.
0=
No transfer in progress (Default).
1=
Transfer in progress.
6:3
7

Reserved
Bank select

Enables bank switching for Serial Ports 1 and 2.
0=
1=

0000b
0b

Disabled (Default).
Enabled

11.2.5. PS/2 Mouse/Keyboard
SIO LDN 05 and 06
Note: The following table contains only
LDN 06 register information.
Table 12.10 PS/2 Mouse/Keyboard Registers
Register/ Bit
30H

60H
61H
62H
63H
70H

Name

Function

Value

LDN Activate

Bit 0:

01h

LDN Base addr MSB
LDN Base addr LSB
LNB Port base MSB
LNB Port base LSB
LDN IRQ

1=
Device enabled
0=
Device disabled
Activate. See also bit 0 of the SIOCF1. When the
Mouse of the KBC is inactive, the IRQ selected by the
Mouse Interrupt Number register (index 70h) is not
asserted.
This register has no effect on host KBC commands
handling the PS/2 Mouse.
Bits 7-3 (for A15-11) are read only, 00000b.
Bits 2:0 (for A2:0) are read only, 000b.
Bits 7:3 (for A15:11) are read only, 00000b
Bits 2:0 rea read only 100b
KBC Interrupt number

00h
60h
00h
64h
01h

ZFx86 Data Book 1.0 Rev D

Page 633

11
Table 12.10 PS/2 Mouse/Keyboard Registers (cont.)
Register/ Bit
71H

Name
LDN IRQ Type Select

Function
KBC interrupt type. Indicates the type and level of the
interrupt request number selected in the previous
register.

02h

Bit 0 =

74H

LDN DMA Select 0

Type of interrupt request selected in
previous register
0 = Edge
1 = Level
Bit 1 =
Level of interrupt request selected in
previous register
0 = Low polarity
1 = High polarity
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

Value

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA
channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the
logical device (0 = The first DMA channel when using
more than one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA
channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
0F0H
0

LDN Config
TRI-STATE Control

5:1

Reserved

7:6

Clock Source

The values 5-7 are reserved.
KBC configuration register
If KBD is inactive (disabled) when this bit is set, the
KBD pins (KBCLK and KBDAT) are in TRI-STATE. If
Mouse is inactive (disabled) when this bit is set, the
Mouse pins (MCLK and MDAT) are in TRI-STATE.
0=
Disabled (Default)
1=
Enabled
Use read-modify-write to change the value of the
register. Do not change the value of these bits.
Bit 2 must be 0.
The clock source can be changed only when the KBC
is inactive (disabled).
Bits7 6
00
01
10
11

ZFx86 Data Book 1.0 Rev D

40h
0b

00000b

01b

Function
8 MHz
12 MHz (Default)
16 MHz
Reserved

Page 634

11
11.2.6. Infrared Communication Port Configuration
(SIO LDN 07)
Table 12.11 Infrared Communication Port Configuration Registers
Register/ Bit

Name

30H

LDN Activate

60H
61H
70H
71H

LDN Base addr MSB
LDN Base addr LSB
LDN IRQ
LDN IRQ Type Select

Function
Bit 0:
1=
device enabled
0=
device disabled
Bits 7-3 (for A15-11) are read only, 00000b.
Bits 2:0 (for A2:0) are read only, 000b.
Interrupt number
Indicates the type and level of the interrupt request
number selected in the previous register.

00h

03h
0E8h
00h
03h

Bit 0 =

74H

LDN DMA Select 0

Type of interrupt request selected in previous
register
0 = Edge
1 = Level
Bit 1 =
Level of interrupt request selected in previous
register
0 = Low polarity
1 = High polarity
Indicates selected DMA channel for DMA 0 of the logical
device (0 = The first DMA channel when using more than
one DMA channel).

Value

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA channel
0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the logical
device (0 = The first DMA channel when using more than
one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA channel
0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
0F0H
0

LDN Config
TRI-STATE Control

The values 5-7 are reserved.
Infrared configuration register
When enabled and the device is inactive, the logical
device output pins are in TRI-STATE.

02h
0b

One exception is the IRTX pin, which is driven to 0 when
Serial Port 2 is inactive and is not affected by this bit.
0=
1=

ZFx86 Data Book 1.0 Rev D

Disabled (Default)
Enabled

Page 635

11
Table 12.11 Infrared Communication Port Configuration Registers (cont.)
Register/ Bit
1

Name

Function

Power Mode Control

When the logical device is active in:

1b

0=

2

Low power mode
Clock disabled. The output signals are set to
their default states. The RI input signal can be
programmed to generate an interrupt.
Registers are maintained. (Unlike Active bit in
Index 30 that also prevents access to device
registers.)
1=
Normal power mode
Clock enabled. The device is functional when
the logical device is active (Default).
This read only bit can be used by power management
software to decide when to power-down the device.

Value

BUSY

0=
1=
6:3
7

Reserved
Bank select

No transfer in progress (Default).
Transfer in progress.
0000b
0b

Enables bank switching.
0=
1=

0b

All attempts to access the extended registers
are ignored (Default).
Enables bank switching.

11.2.7. Access Bus
(SIO LDN 08)
Table 12.12 Access Bus Registers
Register/ Bit
30H

Name
LDN Activate

60H
61H

LDN Base addr_ MSB
LDN Base addr LSB

70H
71H

LDN IRQ
LDN IRQ Type Select

Function
Bit 0:

Bit 1 =

ZFx86 Data Book 1.0 Rev D

00h

1=
device enabled
0=
device disabled
Base address MSB
Base address LSB. Bits 2-0 (for A2-0) are read only,
000b.
Interrupt number
Indicates the type and level of the interrupt request
number selected in the previous register.
Bit 0 =

Value

00h
00h
00h
03h

Type of interrupt request selected in previous
register
0 = Edge
1 = Level
Level of interrupt request selected in previous
register
0 = Low polarity
1 = High polarity

Page 636

11
Table 12.12 Access Bus Registers (cont.)
Register/ Bit
74H

Name

Function

LDN DMA Select 0

Value

Indicates selected DMA channel for DMA 0 of the logical
device (0 = The first DMA channel when using more than
one DMA channel).

04h

Bits 2–0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA channel
0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
75H

LDN DMA Select 1

The values 5-7 are reserved.
Indicates selected DMA channel for DMA 0 of the logical
device (0 = The first DMA channel when using more than
one DMA channel).

04h

Bits 2-0 select the DMA channel for DMA 0. The valid
choices are 0-3, where a value of 0 selects DMA channel
0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
0F0H
1:0
2

LDN ACBCNF
Reserved
Internal Pullup Enable

The values 5-7 are reserved.
ACB configuration register
0=
1=

7:3

No internal pull-up resistors on SCL and SDA
(Default)
Internal pull-up resistors on SCL and SDA

Reserved

04h
00b
1b

00000b

11.2.8. Pin Multiplexor Registers
Table 12.13 Pin Multiplexor Registers
Register/ Bit
F3BAR0+00H
15:0

Name

Function

I/O Control register 1

Value
05040000h

Reserved

0000h

16

External RTC

Must be left at 0

0b

17

External KBC

Must be left at 0

0b

18

IO_USB_PCI_EN

USB ports

1b

0=
1=
19

IO_USB_SMI_PIN_EN

Disable
Enable

USB SMI I/O Configuration — Route USB-generated
SMI directly to the SMI# pin:

0b

0=
1=

Disable
Enable, USB-generated SMI pulls SMI# pin
active (low)
If bits 19 and 20 are enabled, the SMI generated by
the USB is reported through the Top Level SMI Status
Register at F1BAR0+I/O Offset 00h[14]. If only bit 19 is
enabled, the USB can generate an SMI but there is no
status reporting.

ZFx86 Data Book 1.0 Rev D

Page 637

11
Table 12.13 Pin Multiplexor Registers (cont.)
Register/ Bit
20

Name
IO_USB_SMI_PWM_EN

Function
USB Internal SMI — Route USB-generated SMI
through the Top Level SMI Status Register at
F1BAR0+I/O Offset 00h[14]:

Value
0b

0=
Disable
1=
Enable
Bit 19 must be enabled to allow the USB to generate
an SMI for status reporting.
21

IO_RTC_32K

This bit selects which 32K clock source is used.
Resets to 0.
0=
1=

0b

Use SIO generated 32Khz. Clock is driven
by RTC.
Use internally generated 32Khz. Clock is
derived by dividing the 48Mhz by 1484.

Note: Bootstrap[6] = 1 can also be used to select
internally generated 32Khz clock.
22

IO_CLK32K_OE

This bit is set to drive 32Khz clock out on to GPIO[0].
Reset to 0.

23

Reserved

0b

24

IO_ENABLE_SIO_DRIVING_ Enable Integrated SIO ISA Bus Control — Allow the
ISA_BUS
integrated SIO to drive the internal and external ISA
bus:

1b

0=
1=
26:25

IO_SIOCFG_IN

11 =
27

IO_ENABLE_SIO_IR

31:28

Reserved
I/O Control register 2

ZFx86 Data Book 1.0 Rev D

10b

Integrated SIO disable
Integrated SIO configuration access disable
Integrated SIO base address 02Eh/02Fh
enable
Integrated SIO base address 015Ch/015Dh
enable

Enable integrated SIO infrared
0=
1=

F3BAR0+04H

Disable
Enable (Default).

Integrated SIO Input Configuration. These two bits can
be used to disable the integrated SIO totally or
limit/control the base address:
00 =
01 =
10 =

0b

0b

Disable
Enable
0h
00000032

Page 638

11
Table 12.13 Pin Multiplexor Registers (cont.)
Register/ Bit
0

Name
IO_EXT_CLK_14M

Function
Select 14.3Mhz clock source. Select either internally
or externally generated 14.3Mhz clock source. If
internal source is selected the actual clock frequency
is 12Mhz (48Mhz / 4).
0=
1=

Value
0b

Select external 14.3Mhz input as source.
(Default)
Select internally generated 14.3Mhz clock
source.

Note: Bootstrap[5] = 1 can also be used to select
internally generated 14.3Mhz clock
1

IO_IDE_ON_GPIO

Drive IDE channel 2 onto gpio. Must also have gpio
conditioned to correct direction corresponding to IDE
pin functionality.

1b

0=
do not drive IDE onto gpio. (Default)
1=
drive IDE into gpio.
gpio[1] is dmackx, gpio must be configured as output.
gpio[2] is diowx, gpio must be configured as output.
gpio[3] is diorx, gpio must be configured as output.
gpio[5] is dreq, gpio must be configured as input.
gpio[6] is iordy, gpio must be configured as input.
2

IO_BUR_ON_SIO

This bit is used in design verification only. Resets to 0.

0b

3

IO_FUNC_ON_SIO

This bit is used in design verification only. Resets to 0.

0b

4

IO_ZFL_EN

This bit is set to enable the ZF-Logic. Resets to 0.

1b

Note: Bootstrap[22] also used to enable the ZF-Logic.
5

IO_ZT_EN

This bit is set to enable the ZF-Logic ROM interface.
Resets to 0.

1b

Note: Bootstrap[23] also used to enable ZF–Logic
ROM interface.
6

Reserved

7

IO_CLK_14M_OE

31:8

Reserved

ZFx86 Data Book 1.0 Rev D

0b
This bit is set to drive the internally generated 12Mhz
clock out on GPIO[4]. Resets to 0.

0b
0000000h

Page 639

11
11.2.9. GPIO Configuration Pins
12.2.9.1. GPIO 0
Table 12.14 GPIO0 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

Lock

0b

Open-drain (Default
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

3

Value

GPIO Pin Configuration Access Register
44H
Indicates
the
GPIO
pin
output
state.
It
has
no
effect
on
input.
Output Enable
0b

1b

Disable
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

5

PME Edge/Level Select

PME Polarity

No effect (Default)
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
Edge input
1=
Level input.
For normal operation always set this bit to 0 (edge input).
Erratic system behavior results if this bit is set to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
1=

6

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

0b

Falling edge or low level input.
Rising edge or high level input.

Enables/disables IRQ debounce (debounce period = 16 ms)

0=
1=

0b

1b

Disable
Enable.
0h

Page 640

11
12.2.9.2. GPIO 1
Table 12.15 GPIO1 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

03H
1b

1b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

0b

Disable;
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default);
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

PME Polarity

6

PME Debounce Enable

Reserved

ZFx86 Data Book 1.0 Rev D

0b

Falling edge or low level input.
Rising edge or high level input.

Enables/disables IRQ debounce (debounce period = 16 ms):

0=
1=
31:7

Edge input;
Level input.

Note: For normal operation always set this bit to 0 (edge
input). Erratic system behavior will result if this bit is set
to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high).
0=
1=

0b

0b

Disable;
Enable.
0h

Page 641

11
12.2.9.3. GPIO 2
Table 12.16 GPIO2 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

03H
1b

1b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

0b

Disable;
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default);
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

6

PME Polarity

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

Edge input;
Level input.

Note: For normal operation always set this bit to 0 (edge
input). Erratic system behavior results if this bit is set
to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
Falling edge or low level input.
1=
Rising edge or high level input.
Enables/disables IRQ debounce (debounce period =
16 ms):
0=
1=

0b

0b

0b

Disable
Enable.
0h

Page 642

11
12.2.9.4. GPIO 3
Table 12.17 GPIO3 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

03H
1b

1b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

0b

Disable
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default);
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

6

PME Polarity

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

Edge input;
Level input.

Note: For normal operation always set this bit to 0 (edge
input). Erratic system behavior results if this bit is set
to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
Falling edge or low level input.
1=
Rising edge or high level input.
Enables/disables IRQ debounce (debounce period =
16 ms):
0=
1=

0b

0b

0b

Disable
Enable.
0h

Page 643

11
12.2.9.5. GPIO 4
Table 12.18 GPIO4 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

44H
0b

0b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have an effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

1b

Disable
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have an effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default)
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

6

PME Polarity

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

Edge input;
Level input.

Note: For normal operation always set this bit to 0 (edge
input). Erratic system behavior results if this bit is set
to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
Falling edge or low level input.
1=
Rising edge or high level input.
Enables/disables IRQ debounce (debounce period =
16 ms):
0=
1=

0b

0b

1b

Disable
Enable.
0h

Page 644

11
12.2.9.6. GPIO 5
Table 12.19 GPIO5 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

00H
0b

0b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

0b

Disable
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default);
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

6

PME Polarity

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

Edge input;
Level input.

Note: For normal operation, always set this bit to 0 (edge
input).
Erratic system behavior results if this bit is set to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
Falling edge or low level input.
1=
Rising edge or high level input.
Enables/disables IRQ debounce (debounce period =
16 ms):
0=
1=

0b

0b

0b

Disable
Enable.
0h

Page 645

11
12.2.9.7. GPIO 6
Table 12.20 GPIO6 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

00h
0b

0b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

0b

Disable
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default)
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

6

PME Polarity

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

Edge input;
Level input.

Note: For normal operation always set this bit to 0 (edge
input).
Erratic system behavior results if this bit is set to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
Falling edge or low level input.
1=
Rising edge or high level input.
Enables/disables IRQ debounce (debounce period = 16
ms):
0=
1=

0b

0b

0b

Disable
Enable.
0h

Page 646

11
12.2.9.8. GPIO 7
Table 12.21 GPIO7 Registers
Register/ Bit
F0BAR0+24H
0

1

Name

Function

GPIO Pin Configuration Access Register
Output Enable
Indicates the GPIO pin output state. It has no effect on
input.

Output Type

0=
TRI-STATE (Default)
1=
Output enabled.
Controls the output buffer type (open-drain or push-pull)
of the corresponding GPIO pin.
0=
1=

2

Pull-Up Control

3

Lock

44H
0b

0b

Open-drain (Default)
Push-pull

Note: Bit 0 must = 1 for this bit to have effect.
Enables/disables the internal pull-up capability of the
corresponding GPIO pin. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0=
1=

Value

1b

Disable
Enable (Default).

Note: Bits [1:0] must = 01 for this bit to have effect.
This bit locks the corresponding GPIO pin. Once this bit
is set to 1 by software, it can only be cleared to 0 by
system reset or power-off.
0=
1=

4

PME Edge/Level Select

No effect (Default);
Direction, output type, pull-up and output
value locked.
Selects the type (edge or level) of the signal that issues a
PME from the corresponding GPIO pin:

0b

0=
1=

5

6

PME Polarity

PME Debounce Enable

31:7

Reserved

ZFx86 Data Book 1.0 Rev D

Edge input;
Level input.

Note: For normal operation always set this bit to 0 (edge
input). Erratic system behavior will result if this bit is set
to 1.
Selects the polarity of the signal that issues a PME from
the corresponding GPIO pin (falling/low or rising/high):
0=
Falling edge or low level input.
1=
Rising edge or high level input.
Enables/disables IRQ debounce (debounce period = 16
ms):
0=
1=

0b

0b

1b

Disable
Enable.
0h

Page 647

11
12.2.9.9. ZF–LOGIC Registers
Table 12.22 ZF–Logic Registers
Register/ Bit
06H
7:0
08H
0

1

Name
PWM Duty Cycle
Duty

Function
00h =
0FFh =

5

00h
Enable/Disable PWM output

0b

Clksrc

0=
PWM is disabled
1=
PWM is enabled
Selects the PWM prescaler input clock

0b

Reserved
Dlevel
Direct

7:6
0

1

5

00b
0b
0b

PWM drives the PWM output pin
bit4 of register 08h drives the PWM output pin

Reserved
Watchdog control 1
wd1_en

00b
Enable watchdog 1

0b

wd2_en

0=
WD1 is disabled
1=
WD1 is enabled
Enable watchdog 2

0b

00h

0=
1=
3:2
4

PWM is clocked from 32kHz clock
PWM is clocked from 8MHz ISA clock

Value to be set at PWM output pin when bit5 of register
08h is set to 1
Enables direct control of PWM output by bit 4
0=
1=

10H

00h
00h

PWM Control
PWMEN

0=
1=
3:2
4

100% low
0% low

Value

WD2 is disabled
WD2 is enabled

Reserved
wd1_ld

Reload WD1 counter

00b
0b

wd2_ld

Active event for this bit is transition from 0 to 1
Reload WD2 counter.

0b

Active event for this bit is transition from 0 to 1
7:6
11H
0

1

2

Reserved
Watchdog control 2
wd1_c

00b
Enable SCI on WD1 expiry

0b

wd1_n

0=
WD1 will not generate SCI
1=
WD1 will generate SCI event on expiry
Enable NMI on WD1 expiry

0b

wd1_s

0=
WD1 will not generate NMI
1=
WD1 will generate NMI on expiry
Enable SMI event on WD1 expiry

0b

00h

0=
1=

ZFx86 Data Book 1.0 Rev D

WD1 will not generate SMI
WD1 will generate SMI event on expiry

Page 648

11
Table 12.22 ZF–Logic Registers (cont.)
Register/ Bit
3

4

5

Name

Function

wd1_rs

Enable RESET on WD1 expiry

0b

wdi_ed

0=
WD1 will not generate system reset
1=
WD1 will generate system reset on expiry
Active front of WDI input

0b

Wdo_-1

0=
WDI is asserted on 0->1 transition
1WDI is asserted on 1->0 transition
Create output on WDO output pin on ZFx86 at WD1
expiry or one 32kHz clock tick before
0=
1=

6

Value

wdi_en

0b

WDO signal will be set high on WD1 expiery
WDO signal is set high one clock tick before
WD1 expires. WD1 events will always occur
at WD1 expiry and are not affected of wdo_-1
bit setting.

Note: This feature gives possibility to cause automatic
reload of WD1 when WDO is wired to WDI.
Enable the assertion of WDI input pin on ZFx86 to to

0b

reload the watchdog 1 counter
0=
1=
7
16H
3:0

4

5

6

7

Reserved
IO Window 0 control
Win_siz

WDI input ignored
WDI assertion reloads watchdog 1 counter

Number of consecutive 8-bit I/O addresses to decode
starting from I/O window base.

0b
00h
0000b

win_en

The number of addresses decoded is win_siz + 1. For
example, setting the window size to 0 enables one I/O
address at I/O window base. Setting size to 0Fh will
enable I/O window of 16 addresses starting from I/O
window base.
I/O window enable in I/O space

0b

act_lvl

0=
I/O window is disabled
1=
I/O window is enabled
io_cs active level

0b

16_bit

0=
io_cs is active low
1=
io_cs is active high
I/O window datapath width

0b

win_ro

0=
8-bit wide access
1=
16-bit wide access
I/O window wead/write control

0b

0=
1=

Access is read-write
Access is read-only

Note: Setting window to read-only mode disables
IOW_N signal on ISA bus for IO window address range.

ZFx86 Data Book 1.0 Rev D

Page 649

11
Table 12.22 ZF–Logic Registers (cont.)
Register/ Bit
1AH
3:0

4

5

6

7

Name
IO Window 1 control
Win_siz

Function
Number of consecutive 8-bit I/O addresses to decode
starting from I/O window base.

Value
00h
0000b

win_en

The number of addresses decoded is win_siz + 1. For
example, setting the window size to 0 enables one I/O
address at I/O window base. Setting size to 0Fh will
enable I/O window of 16 addresses starting from I/O
window base.
I/O window enable in I/O space

0b

act_lvl

0=
I/O window is disabled
1=
I/O window is enabled
io_cs active level

0b

16_bit

0=
io_cs is active low
1=
io_cs is active high
I/O window datapath width

0b

win_ro

0=
8-bit wide access
1=
16-bit wide access
I/O window wead/write control

0b

0=
1=

Access is read-write
Access is read-only

Note: Setting window to read-only mode disables
IOW_N signal on ISA bus for IO window address range.
1EH
3:0

IO Window 2 control
Win_siz

Number of consecutive 8-bit I/O addresses to decode

00h
0000b

starting from I/O window base.

4

5

6

7

win_en

The number of addresses decoded is win_siz + 1. For
example, setting the window size to 0 enables one I/O
address at I/O window base. Setting size to 0Fh will
enable I/O window of 16 addresses starting from I/O
window base.
I/O window enable in I/O space

0b

act_lvl

0=
I/O window is disabled
1=
I/O window is enabled
io_cs active level

0b

16_bit

0=
io_cs is active low
1=
io_cs is active high
I/O window datapath width

0b

win_ro

0=
8-bit wide access
1=
16-bit wide access
I/O window wead/write control

0b

0=
1=

Access is read-write
Access is read-only

Note: Setting window to read-only mode disables
IOW_N signal on ISA bus for IO window address range.

ZFx86 Data Book 1.0 Rev D

Page 650

11
Table 12.22 ZF–Logic Registers (cont.)
Register/ Bit
22H
3:0

4

5

6

7

Name
IO Window 3 control
Win_siz

Function
Number of consecutive 8-bit I/O addresses to decode
starting from I/O window base.

00h
0000b

win_en

The number of addresses decoded is win_siz + 1. For
example, setting the window size to 0 enables one I/O
address at I/O window base. Setting size to 0Fh will
enable I/O window of 16 addresses starting from I/O
window base.
I/O window enable in I/O space

0b

act_lvl

0=
I/O window is disabled
1=
I/O window is enabled
io_cs active level

0b

16_bit

0=
io_cs is active low
1=
io_cs is active high
I/O window datapath width

0b

win_ro

0=
8-bit wide access
1=
16-bit wide access
I/O window wead/write control

0b

0=
1=

27H
28H
2BH
2CH
2FH
30H
33H
34H
37H
38H
3BH
3CH
3FH
40H
43H
44H
47H
48H
4BH
4CH
4FH
50H
53H
54H

Value

Memory window 0 base 1
Memory window 0 base 2
Memory window0 size 1
Memory window 0 size 2
Memory window 0 page 1
Memory window 0 page 2
Memory window 1 base 1
Memory window 1 base 2
Memory window 1 size 1
Memory window 1 size 2
Memory window 1 page 1
Memory window 1 page 2
Memory window 2 base 1
Memory window 2 base 2
Memory window 2 size 1
Memory window 2 size 2
Memory window 2 page 1
Memory window 2 page 2
Memory window 3 base 1
Memory window 3 base 2
Memory window 3 size 1
Memory window 3 size 2
Memory window 3 page 1
Memory window 3 page 2

ZFx86 Data Book 1.0 Rev D

Access is read-write
Access is read-only

Note: Setting window to read-only mode disables
IOW_N signal on ISA bus for IO window address range.
Memory window base address bits 15..12
Memory window base address bits 23..16
Memory window size bits 15..12
Memory window size bits 23..16
Memory window page bits 15..12
Memory window page bits 23..16
Memory window base address bits 15..12
Memory window base address bits 23..16
Memory window size bits 15..12
Memory window size bits 23..16
Memory window page bits 15..12
Memory window page bits 23..16
Memory window base address bits 15..12
Memory window base address bits 23..16
Memory window size bits 15..12
Memory window size bits 23..16
Memory window page bits 15..12
Memory window page bits 23..16
Memory window base address bits 15..12
Memory window base address bits 23..16
Memory window size bits 15..12
Memory window size bits 23..16
Memory window page bits 15..12
Memory window page bits 23..16

00h
0F0h
0F0h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h

Page 651

11

ZFx86 Data Book 1.0 Rev D

Page 652

Index
Index

Numerics
0 Wait States 186
00H
PCI Vendor ID Register 624
Seconds Register (RTC) 310
Serial Data Register (ACB) 329
Vendor ID Register 162
Wake-Up Events Status Register 280
01H
Seconds Alarm Register (RTC) 311
Status Register (ACB) 330
Wake-Up Events Control Register 281
02H
Control Status Register (ACB) 331
Minutes Register (RTC) 311
Wake-Up Config Register 282
03H
Control Register 1 (ACB) 332
Minutes Alarm Register (RTC) 311
04H
Command Register 162
Hours Register (RTC) 312
Own Addresss Register (ACB) 333
PCI Command Register 624
05H
Control Register 2 (ACB) 334
Hours Alarm Register (RTC) 312
06H
Day of Week Register (RTC) 312
PCI Status Register 624
PWM Duty Cycle Register 648
Status Register 163
07H, Mouse Data Shift Register 284
08H
Month Register (RTC) 313
PCI Revision ID Register 625
PWM Control Register 648
Revision ID Register 163
09H
Class Register 163
Year Register (RTC) 313
0BH, Control Register B (RTC) 316
0DH, Control Register D (RTC) 319
0DH, PCI Latency Timer Register 625
100H, NB Revision ID Register 137, 603
10H
Watchdog Control 1 Register 648
Watchdog Control Low 427
110H, Programmable Region 1 Register 137, 603
111H, Programmable Region 2 Register 137, 603

ZFx86 Data Book 1.0 Rev D

I

112H, Programmable Region 3 Register 138, 603
113H, Programmable Region 4 Register 138, 604
114H, Programmable Region Control Register 138,
604
115H, Cacheability Override Register 139, 604
117H, Back-off Control Register 140, 605
118H, SMM Control Register 140, 606
119H, Processor Control Register 142, 608
11AH, Write FIFO Control Register 143, 609
11BH, PCI Control Register 145, 610
11CH, Clock Skew Adjust Register 146, 611
11DH
Bus Master 146
Bus Master Register 611
Snoop Control Register 146, 611
11EH, Arbiter Control Register 148, 613
11FH, Docking Control Register 613
11H
Watchdog Control 2 Register 648
Watchdog Control High 428
120H, PCI Write FIFO Control Register 148, 614
12H, Watchdog Status 429
14H, ZF-Logic Index for I/O Windows 423
14MHz Clock 173
16H, I/O Window 0 Control Register 649
1AH, I/O Window 1 Control Register 650
1EH, I/O Window 2 Control Register 650
200H, Shadow RAM Read Enable Control Register
149, 615
201H, Shadow RAM Write Enable 150, 615
202H
Bank 0 Control Register 151
Bank 0 Starting Address 616
204H, Bank 0 Timing Register 152, 616
205H, Bank 1 Control Register 152, 617
207H, Bank 1 Timing Register 617
207H, Bank 1Timing Register 153
208H, Bank 2 Control Register 153, 617
20AH, Bank 2 Timing Register 154, 618
20BH, Bank 3 Control Register 155, 618
20DH, Bank 3 Timing Register 155, 619
20EH, DRAM Configuration Register 1 156, 619
20FH, DRAM Configuration Register 2 157, 620
20H, SuperI/O ID Register 270
211H, DRAM Refresh Control Register 158, 621
213H, SDRAM Mode Program Register 158, 621
214H, SDRAM Mode Program Register 159, 622
21H, SuperI/O Config 1Register 270
22H
I/O Window 3 Control Register 651
SuperI/O Config 2 Register 271

Page 653

Index
238H, CPU-SYNC Register 162
239H, SDRAM Slew Control Register 159, 622
24H, NB Config Index Register 119
26H, NB Configuration Data Registers 119
27H 651
27H, SuperI/O Revision ID Register 271
27H, ZF-Logic 411
28H 651
2BH 651
2CH 651
2FH 651
3.3V Power Supply 193
300H, Clock Control Register 160, 623
30H 651
32KHz
Clock Connection 173
Crystal Oscillator Connection 173
32KHZ_C , AF01 449
33H 651
34H 651
37H 651
38H 651
3BH 651
3CH 651
3FFH, Clock Control 2 Register 161, 623
3FH 651
40H 651
PCI Arbiter Routing Register 625
43H 651
44H 651
47H 651
48 MHz Clock pin 173
48H 651
4BH 651
4CH 651
4FH 651
50H 651
53H 651
54H 651
7CH, Z-tag Control Register 462

A
A20, SYSCLCK, ZF-Logic 450
A20M 143
AC Characteristics 489–540
ACB
Configuration Register, F0H 299
Control Register 1, 03H 332
Control Register 2, 05H 334
Control Status Register, 02H 331

ZFx86 Data Book 1.0 Rev D

I

Own Address Register, 04H 333
Register Bitmap Table 334
Register Map Table 329
Runtime Registers 298
Serial Data Register, 00H 329
Status Register, 01H 330
ACBADDR 334
ACBCST 334
ACBCTL1 334
ACBCTL2 334
ACBSDA 334
ACBST 334
ACCESS.bus 322–334
Clock Signal 189, 261
Data Signa 189
Data Signal 261
Electrical Specifications 494
Register Table 636
Runtime Register Table 298
VDD 261
Accessing the ZF-Logic Registers 405
ACK_N 192, 600
Acknowledge, SB 192
Addr2Linear 591
Address
Enable 183
Map, NB 118
Strobe, SB 193
Translation 121
ADF 192
ADP_PREF_DIS 146
ADRAM_CAS 117
ADSR 292
AE01, 32 KHz Crystal Oscillator Connect pin 173
AEN 183
AF01
32KHz clock
Connection pin 173
32kHz clock 449
AF16, 14MHz clock pin 173
Alternate CPU Support Register 212
ARB_ROUTE 625
Arbiter Control Register, 11EH 148, 613
Architecture
North Bridge 113
South Bridge 166
AT compatibility Logic, SB 170
AUTOFD_N 600
Automatic Feed, SB 192

Page 654

Index

B
B04, Memory Chip Select pin 173
B0A 151
B0S 151
B1A 152
B1S 152
B2A 153
B2S 154
B3A 155
B3S 155
Back-off Control Register, 117H 140, 605
BALE 183
BANK 157
Bank 0
Control Register 202H 151
Offset 03H, PS/2 Protocol Control Register 283
Offset 06H, Keyboard Data Shift Register 284
Starting Address, 202H 616
Timing Control, 204H 616
Timing Register 204H 152
Bank 1
Control Register 205H 152
Control Register, 205H 617
Timing Control Register, 207H 617
Timing Register 207H 153
Bank 2
Control Register 208H 153
Control Register, 208H 617
Timing Control Register, 20AH 618
Timing Register 20AH 154
Bank 3
Control Register 20BH 155
Control Register, 20BH 618
Timing Control Register, 20DH 619
Timing Register 20DH 155
Base Address
Register 0 208
SMM 134
Battery Power Supply, SB 193
Battery Supply Current 482
Baud Output, SB 194
BCD and Binary Formats Table 320
BCR 605
BIST Register, USB 247
BM_BURSTRD_ALWYS 145
BM_DONE_DIS 145
boot from these sources 414
BootStrap Register, ZF-Logic 438
Buffered Address Latch Enable 183
BUR 462–470

ZFx86 Data Book 1.0 Rev D

I

Base Register, ZF-Logic 445
On-Chip RAM Assignments 470
Z-tag 455
Burst sequence, NB 120
Bus Master, 11DH 146, 611
Bus Timing Parameters, PIC 498
BUSY 600
Busy, SB 192

C
C/BE, PCI Bus Command and Byte Enables 177
C19, POR# system reset pin 173
CACHE_OVR 139
Cacheability Override Register, 115H 139, 604
CAS_LATCY 152, 153, 154, 155
CEIR
Address Shift Register, Bank 1 Offset 7 286
Carrier Frequency EncodingTable 396
Mode, SB 347
Receive Operation, SB 348
Transmit Operation, SB 347
CEIR Wake-Up
Address Mask Register, Bank 1 Offset 6 286
Config/Control Register Map 279
Control Register, Bank 1 Offset 3 285
CEIR Wake-Up Range
0 Registers Bank 1 Offset 9 287
1 Registers
Bank 1 Offset 0AH 287
Bank 1 Offset 0BH 288
3 Registers
Bank 1 OEH 289
Bank 1 OFH 290
Century Register 320
Offset (RTC) 309
Offset, F3H 302
CF8H, NB PCI Config Cycle Address Register 119
CFCH, NB PCI Config Cycle Data Register 119
CK_HITM_WS 146
Class Register 09H 163
Clear to Send, SB 194
CLK_14MHZ 173
CLK_48MHZ 173
CLKIN 189
CLKRUN 175
Clock Control Register
300H 160, 623
3FFH 161, 623
Clock In, SB 189
Clock Parameters, PCI 497

Page 655

Index
Clock Skew Adjust, 11CH 146, 611
Clock Stop Control Register 226
Clocking Options, ZF-Logic 444
CNFCY_AD_STEP_DIS 145
COLADR 151, 153, 154, 155
Command Register
04H 162
USB 246
COMMD 624
Common
Control and Status Register Map 279
Three-Register Map, Banks 0 and 1 291
Composite BootStrap Register Table 438
Configuration
Access disabled 263
Register table, NB 137
Control Register, Z-tag 462
Coprocessor Error Register 257
COR 604
Core Supply Current 482
CPU
bus cycle conversion, NB 133
busses, NB 120
Clock management, NB 136
Interrupt Request internal pin 174
reset internal pin 174
Suspend Acknowledge, SUSPA 174
Suspend Command Register 225
Suspend, SUSP 175
CPU&EM_DRAM 144
CPU_BUSY_TIMER 148, 613
CPU_RST 174
CPU_SYNC 118
CPU_trig timing 491
CPU2PCI_BURST_EN 145
CPU-SYNC Register 238H 162
CRLF 587
CS_SLEW 160
CTS1 194
CTS2_N 601

D
DACK 186
DACK1_N 599
Data Carrier Detected, SB 194
Data Set Ready, SB 194
Data Strobe, SB 192, 193
Data Terminal Ready, SB 194
DATA_BUS_HOLD 160
DATA_PAR_DET 163

ZFx86 Data Book 1.0 Rev D

I

Date Of Month Alarm Register 319
Offset (RTC) 308
Offset, F1H 301
Day Of Week Register, 06H 312
DBBIN 335
DBBOUT 335
DCD 194
DCD2_N 601
DCONF1 619
DCONF2 620
Decode Control Register 212
Delay 588
DET_PAR_ERR 163
Device ID Register 162, 207
Device Revision ID Register 208
DEVSEL_N 179
DEVSEL_TIM 163
DIR 189
DIR _N 460
DIR_N 597
Direction 189
DIS_BUS_SNARF 147
DIS_CHK_HITM 146
DIS_CONCURRENCY 147
DIS_EM_PREFETCH 147
DIS_FPUCLR_BY 143
DIS_PSLOCK 143
DIS_RESOURCE_LOCK 145
DIS_SNOOP 146
DIS_WB_MERGE 147
DIS23RMAP 140
DISC_ON_LN_BOUNDARY 145
Disk Change, SB 189
DISPCIM_ELY_DRM_CY 147
DISPCIM_SHADOWRAM 147
DMA
Acknowledge 186
Acknowledge Channels, SB 180
Channel Address Register 248
Channel Mask Register, 249
Channel Mode Register 250
Channel Transfer Count Register 248
Control, Channel 0 Drive 0 238
Control, Channel 0 Drive 1 238
Control, Channel 1 Drive 0 238
Control, Channel 1 Drive 1 239
Controller, SB 170
Request 185
Request Channels, SB 180
Shadow Register 225
Software Request Register 249

Page 656

Index
TC Signal 350
Ultra DMA Data Burst Timing Req 511
DOCCS#
Base Address Register 215
Control Register 215
DOCKC 613
Docking Control Register, 11FH 613
Dongle
Jumpers 458
Pass-through Mode 458
Z-tag 456
DR0 189
DRAM
architecture 122
Configuration Register 1, 20EH 156, 619
Configuration Register 2, 20FH 157, 620
maximum local 119
memory map 123
Refresh Control Register, 211H 158, 621
DRAM_INAT_TO 156
DRFSHC 621
Drive Select 0, SB 189
DRMRDREODEREN 143
DRQ 185
DRQ1 599
DRV_N 597, 598
DSBX2Var 587
DSKCHG 189, 460
DSKCHG_N 597
DSR 194
DSR2_N 601
DSTRB 192
DTR1_N 194

E
Edge/Level Select, Interrupt
Register 1 257
Register 2 258
Electrical Specifications 481–540
EN_ADCBE_FLT_IDLE 145
EN_BUS_LOCK 145
EN_PCI_FAST_DECDE 145
EN_RELAX_SDRM_CMD_TMING 157
EN_SDRAM_CKE_RST 161
EN_SDRAM_CONFIG 158
EN_SDRM_PWRDN 157
EN_STOP_CORE_CLK 161
EN_STOP_CPU_CLK 161
EN_STOP_SDRAM_CLK 161
ERR_N 192, 600

ZFx86 Data Book 1.0 Rev D

I

Errata 147, 211
Error, SB 192
Extended RAM Map 321
External Keyboard Controller
Command Register 256
Mailbox Register 256, 257
External Memory Devices 410

F
F0 Index 47h 184
F0 Index 4Ah 183, 184
F0 Index 53H 174
F0BAR0 197
F0BAR0+24H
GPIO Pin Config Access Registers 640–647
F0H
ABC Config Register 299
Data Registers, ZF-Logic 444
Floppy Disk Control Config Register 273
IKBC Config Register 296
Infrared Comm Port Config Register 297
Parallel Port Config Register 275
RAM Lock Register 300
Serial Ports 1/2 Config Registers 293
F1BAR0 SMI Status Register Table 200
F1H
Date of Month Alarm Register 301
Floppy Drive ID Register 274
F2H, Month Alarm Register Offset 301
F3BAR0+00H I/O Control Register 1 637
F3BAR0+04H, I/O Control Register 2 638
F3BARx Initialized Register 243
F3H, Century Register Offset 302
Fast IR Port Timing, Electrical Specifications 528
FAST_B2B_STAT 163
FAST_TRDY 147
FDC
Bitmap Summary Table 337
Configuration Register, F0H 273
FEH, Data Registers, ZF-Logic 444
FERR, FO Index 53H 174
FIFO
Control Register 362
PCI Write Control Register, 120H 614
Timeouts, SB 352
Write Control Register, 11AH 609
FIFOD 143, 148
Floating Point Error Interrupt 174
IRQ13 174
Floating Point Interrupt 118

Page 657

I

Index
Floppy Disk
Controller 272–274
Controller Bitmap Summary Table 627
Controller Register Table 626
Controller, SB 336
Drive Control Timing 532
Electrical Specifications 531
ID Register, F1H 274
Idle Timer Count Register 223
Idle Timer Enable 217
Port Select 222
Reset Timing 531
Trap 218
Write Data Timing 531
Z-tag Pins 460
FLUSH 143
FORCE_DRM_PM_PCIM 147
FRAME_N 178
FRCREMAP 141
FST_SDRM_RD_L2_EN 157
Function Name 587

Support Registers Summary Table 199
Timing, Electrical Specifications 530
Ground 193

H
HDSEL 189
HDSEL_N 460, 597
Head Select, SB 189
High Speed Infrared
Receive Operation 351
Transmit Operation 350
HLD_RETRY_ON_REQ 140
Hours
Alarm Register, 05H 312
Register, 04H 312

I
I/O
Channel Ready, SB 187
Chip Select 16, SB 186
Control Register 244, 245
Control Register 1, F3BAR0+00H 637
Control Register 2, F3BAR0+04H 638
Port 0D0h 251
Read, SB 187
Ready Channel, SB 180
Window 0 Control Register, 16H 649
Window 1 Control Register, 1AH 650
Window 2 Control Register, 1EH 650
Window 3 Control Register, 22H 651
Write, SB 187

G
General Purpose Timer 1
Control Register 220
Count Register 220
Generic 2
Input Table 484
Output Table 487
Generic2 483
GND 193
GNT1 177
GPCS I/O mapper 422
GPIO 599
Config Register Summary Table 197
Data In 230
Data Out 230
Event SMI Status 220
Interface 171
Signal Table 182
Signals 182
Interface, SB 171
Pin Config Access Registers, F0BAR0+24H
640–647
Pin Configuration
Access Register 231
Select Register 230
Power Management Event 230
Reset Control Register 231
Status 230

ZFx86 Data Book 1.0 Rev D

IDE
Address Bits, SB 181
Bus Master 0
Command Register 239
PRD Table Address 240
Status Register 239
Bus Master 1
Command Register 240
PRD Table Address 240
Status Register 240
Chip Select, SB 180
Controller Support Summary Table 201
DACK 599
Data Lines, SB 181
DREQ 599
I/O Read, SB 180
I/O Write, SB 180
Interface Timing Table 504

Page 658

Index
IOR 599
IORDY 599
IOW 599
Multiword DMA Data Transfer 509
PIO Data Transfer To/From Device 507
Register Transfer To/From Device Table 505
Reset Timing Figure 504
Reset, SB 181
IDE_ADDR 181
IDE_CS 180
IDE_D 180
IDE_DATA 181
IDE_DIOR1_N 182
IDE_DIOW0 180
IDE_DIOW1_N 182
IDE_DMA_ACK 180
IDE_DMA_ACK1 182
IDE_DMA_REQ 180
IDE_DMA_REQ1_N 182
IDE_IORDY 180
IDE_IORDY1 182
IDE_RST 181
Idle Timers 216
IER, Extended Mode 358
iKBC Configuration Register, F0H 296
Index, SB 189
INDEX_N 189, 460, 597, 598
Infrared
Comm Port Configuration
Register, F0H 297
Table 297
Receive, High Speed 351
Transmit, High Speed 350
Infrared Comm Port Config Table 635
INIT 192
INIT_N 600
Initialize, SB 192
Input
Generic 2 484
MAC97 486
M-FDC_PP 485
MIDE 485
MMC-D 485
MPCi 484
MUSB 485
MWUSB 486
Pin Capacitance 482
Timing Measurement Figure 500
INT 17h 589
INT9 177
Integrated Super I/O, SB 169

ZFx86 Data Book 1.0 Rev D

I

Interrupt Edge/Level Select Register 257
Interrupt Request
IRQ1 184
IRQ10 600
IRQ11 600
IRQ12 600
IRQ13 118, 174
IRQ14 181
IRQ15 181
IRQ3 185
IRQ9 600
INTR 174
IO_CS0 422, 601
IO_RTC_32K 244, 449
IOCHRDY 187
IOCS0#
Base Address Register 215
Control Register 215
IOCS1#
Base Address Registe 214
Control Register 214
IOCS16 186
IOR 187
IOW 187
IR
Communication Port, SB 345
Mode Register Bank Overview 354
Port Timing Parameters Table 528
Reception, SB 195
Select, SB 195
Transmit, SB 195
Transmitter Modulator Control Register 396
IrDA 1.1 MIR and FIR Modes 349
IRDY_N 178
IRQ Speedup 216
Timer Count Register 222
IRQ1 184
IRQ10 600
IRQ11 600
IRQ12 118, 600
IRQ13 174
IRQ14 181
IRQ15 181
IRQ3 185
IRQ9 600
IRR 195
IRSL 195
IRTX 195
IRWAD 291
IRWCR 291
IRWTR0L 292

Page 659

Index
ISA
Bus Clock, SB 183
Bus interface, SB 169
Electrical Specifications 501
I/O Recovery Control Registe 211
Legacy Register 248
Master Cycles, SB 168
Memory Mapper, ZF-Logic 410
Output Signals Table 501
Read Operation Figure 503
Write Operation Figure 503
ISA_ERR_N 599
ISACLK_N 183

J
JTAG Timing, Electrical Specifications 529
Jumpers on the Z-tag 458

K
KBC
Bitmap Summary Table 335
Register Map Table 335
KBCLK 190
KBDAT 191
KBLOCK 191
KBLOCK_N 599
KCLOCK_C 599
KDATA 599
KDISSMMRAM 140
KDSR 291
KENEN 142
Keyboard
Clock, SB 190
Data Shift Register, Bank 0 Offset 06H 284
Data, SB 191
Lock, SB 191
Keyboard/Mouse
Controller 335
Idle Timer
Count Register 224
Enable 216
Interface Electrical Specifications 533
Trap 217
KHZ32_C 173
KHZZ32 173

L
L1 ROM regions 120
L1WBEN 142

ZFx86 Data Book 1.0 Rev D

I

LBN Revision ID Register, 100H 603
LCK_RDBURST_EN 145
LDSMIHLDER 142
Legacy I/O Register Summary Table 204
Llockout Condition 305
LMEMRDEN 149
LMEMWREN 150
LOCK_N 178
LTMR 625

M
M_FDC_PP 483
MA, Memory Address 116
MA_SLEW 159
MAC97 483
Input Table 486
Output Table 488
Main 3.3V Power Supply 193
Manager Software, Z-tag 459
MANUAL_REFRESH 158
Mask Address Register
F3BAR0 242
F3BAR1 243
F3BAR2 243
F3BAR3 243
F3BAR4 243
F3BAR5 243
Master input assert 183
Master Reset, SB 187
MASTER_N 183
MCLK 191
MCLK_C 599
MCPI
MPCI_CLK 483
MD_DQM_SLEW 159
MDAT 191, 599
MDSR 291
Measurement
Condition Parameters 499
IDE Reset Timing Figure 504
Input Timing Figure 500
ISA Read Operation Figure 503
ISA Write Operation Figure 503
Output Timing Figure 499
ResetTiming Figure 500
MEM_CS 173, 410, 601
MEM_RESPOND 162
MEMCS16 186
Memory address is not cacheable 121
Memory Chip Select 173

Page 660

I

Index
Select 16 186
Memory Data Bus 117
Memory Interface 492
Memory Read, SB 187
Memory Write, SB 187
MEMR 187
MEMW 187
M-FDC_PP
Input Table 485
Output Table 487
MIDE 483
Input 485
Output Table 487
Minutes
Alarm Register, 03H 311
Register, 02H 311
Miscellaneous
Device Control Register 222
Enable Register 210
MMC_D 483
MMC_SDCLK 484
MMC_SDCLKIN 484
MMC-D, Input Table 485
Modem Status Register, SB 370
Month Alarm Register 319
Offset (RTC) 308
Offset, F2H 301
Month Register, 08H 313
Motor Select, SB 190
Mouse
Clock, SB 191
Configuration Register Table 295
Data Shift Register, 07H 284
Data, SB 191
On Serial Enable 222
Port Select 222
MPCI 483
Input 484
MR 187
MTR_N 597, 598
MTR0 190
Multiword DMA Data Transfer, IDE 509
MUSB 483
Input 485
Output Table 487
MVBAT 483
MWUSB 483
Input Table 486
Output Table 488

ZFx86 Data Book 1.0 Rev D

N
N_B0C 616
N_B0TC 616
N_B1C 617
N_B1TC 617
N_B2TC 618
N_B3C 618
NMI, Non-Maskable Interrupt 174
No Write-Posting to PCI Buffer 121
Non-Maskable Interrupt 174
NONPOST_RETRY_CNT 140
NONPOST_RETRY_DIS 140
North Bridge
Address Map 118
Address Translation 121
Burst sequence 120
clock management, NB 136
Concurrent CPU and PCI busses 120
Configuration register table 137
CPU to PCI bus cycle conversion 133
CPU_SYNC 118
D signal 117
Deadlock 120
DRAM architecture 122
DRAM memory map 123
features 113
interface signals 116
IRQ13 118
MA 116
maximum local DRAM 119
PCI arbiter 127
PCI Config Address/Data Registers 130
PCI Memory Space 119
PCI Reads 134
PCI Registers 127
PCI Write Buffer and Bursts 129
Power Management 136
Processor Interface 118
Register programming 126
Register Set 136
Revision ID Register 100H 137
ROM Regions 120
SB_GNT 118
SB_PCICLK 118
SB_REQ 118
SCAN_EN 118
SCAN_MODE 118
SDRAM_CAS 117
SDRAM_CKE 117
SDRAM_CS 116
SDRAM_DQM 116

Page 661

Index
SDRAM_RA 117
SDRAM_WE 116
SDRAMCLK 117
SMM Space 119
Special cycles 120
System Management Mode 134
Test Signals 162
TEST_SI1 118
TEST_SO1 118
TESTMODE 118
Upper ROM 119
Write buffer architecture 134
WRM_RESET 118

O
OAH, Control Register A (RTC) 314
OCH, Control Register C (RTC) 318
On-Chip RAM Assignments 470
Operating case temperature 481
Optical Transceiver Interface 354
Output
Generic 2 487
ISA Signals Table 501
MAC97 488
M-FDC_PP 487
MIDE 487
MMC_D 488
MUSB 487
MWUSB 488
PCI TRI-STATE Buffer 487
Timing Measurement Figure 499
Valid Timing Figure 493
Over Current, SB 182
OVER_CUR 182

P
Pad Assignments 541
Paper End, SB 192
PAR 179
Parallel / Serial Idle Timer Count Register 223
Parallel Port 274–276
Configuration Register F0H 275
Data, SB 192
Electrical Specifications 534
Register Map Table 338
Register Table 629
Timing 534
Parallel/Serial Idle Timer Enable 217
PARERR_REP 162

ZFx86 Data Book 1.0 Rev D

I

Parm2EDX 588
PC98 148, 613
PCI
Address/Data signals, SB 176
Arbiter Routing Register, 40H 625
arbiter, NB 127
Back-side, SB 168
BIST Register 208
BM_FREERUNMODE 149
Bus Command and Byte Enables, SB 177
bus cycle conversion, NB 133
Bus Grants, SB 177
Bus Requests, SB 177
Bus Timing Parameters 498
Bus, Electrical Specifications 495
busses, NB 120
Cache Line Size Register 208
Class Code Register 208
Class Code Register, USB 247
Clock management, NB 136
clock management, NB 136
Clock Parameters Table 497
Clock Run, SB 175
Clock SB 175
Clock, U25 pin 175
Command Register 207
Index 04h-05h 236
XBus Expansion 241
Command Register, 04H 624
Config Address/Data Registers, NB 130
Config Cycle Address Register 119
Configuration Address Register table 196
Control Register 11BH 145
Control Register, 11BH 610
Cycle Frame, SB 178
Deadlock 120
Device Select, SB 179
Function Control Registe 209
Functions Enable Register 210
Header Type 208
Header/Bridge Summary Table 197
Initiator Ready, SB 178
Interrupt Pins, SB 177
Interrupt Steering Register 213
Latency Timer Register 208
Latency Timer Register, 0DH 625
Lock, SB 178
Master Cycles, SB 168
Memory Space 119
NB Config Cycle Data Register 119
Parity Error, SB 179

Page 662

Index
Parity, SB 179
reads, NB 134
registers, NB 127
Reset SB pin, U26 175
Revision Register, 08H 625
SMI Status Register Summary Table 200
Status Register 207
Status Register, 06H 624
Stop, SB 178
System Error, SB 180
Target Ready, SB 178
Tri-State Output 487
Vendor ID Register, 00H 624
Write buffer and bursts 129
Write FIFO Control Register 120H 148
Write FIFO Control Register, 120H 614
PCI_BM_SLOWRUNMODE 149
PCI_INT 177
PCI_RST_N 175
PCIC 610
PCICLK Figure 497
PCICLK_C 175, 600
PCIM2DRM_BRST_EN 145
PD 192, 600
PE 192
PE_N 600
PERR_N 179
PIC
Master / Slave 254
Shadow Register 225
Pin Capacitance 482
Pin Descriptions
Sorted by Pin Description 572
Sorted by Pin Name 558
Sorted by Pin Number 545
Pin List, ZF-Logic 409
Pin Multiplexor Register Table 637
Pinout Summary 541
PIO Data Transfer To/From Device, IDE 507
PIO Register
Channel 0 Drive 0 237
Channel 0 Drive 1 238
Channel 1 Drive 0 238
Channel 1 Drive 1 238
PIT
Control/ISA CLK Divider 211
Delayed Transactions Register 210
Shadow Registe 226
Timer Counter 253
POR_N 173
Port 22h 48
Port 23h 48

ZFx86 Data Book 1.0 Rev D

I

Port A Control Register 257
PORT1_M 182
PORT1_P 182
PORT2_M 182
PORT2_P 182
POST_RETRY_CNCT 140
POST_RETRYCNT_DIS 140
Power Enable, SB 182
Power Management
Enable Register 216
NB 136
SB 170
POWER_EN 182
POWERON_SEQ 158
PR1 603
PR2 603
PR3 603
PR4 604
PRC 604
PREG1S 137
PRGREG1_SEL 138
Primary Hard Disk
Idle Timer
Count Register 223
Enable 217
Trap 218
Primary IDE Registers 257
PROC 608
Processor Control Register, 119H 142, 608
Processor interface 118
Programmable Interrupt Controller, SB 170
Programmable Interval Timer, SB 170
Programmable Region
1 Register, 110H 137, 603
2 Register 111H 137, 603
3 Register 112H 138, 603
4 Register 113H 138
Control Register 114H 138
Control Register, 114H 604
Programmable Region 4 Register, 113H 604
PS/2
KBD/MOUSE Wake-Up Config/Control Register Map 279, 291
Mouse/Keyboard Register Table 633
Protocol Ctrl Reg Bank 0 Offset 03h 283
PS2CTL 291
PS2KEY 291
PWM 601
Control Register, 08H 648
Duty Cycle Register, 06H 648
Generator, ZF-Logic 430

Page 663

Index

R
RAM Lock Register
F0H 300
Table 307
RAM, On-Chip Assignments 470
RAS_CAS_SLEW 159
RD2WR_LAT 144
RDATA 190
RDATA_N 597
Read Data, SB 190
Real Time Clock 300–322
Config Register Table 300
REC_MST_ABRT 163
REC_TAG_ABRT 163
REFRPRD 158
Register
Bitmap (RTC) 321
Programming, NB 126
Transfer To/From Device Table, IDE 505
Register Descriptions 195–257
REND 483
RENU 483
REQ1 177
REQa 148, 613
REQb 148
REQpci 148, 613
Request to Send, SB 194
res_out timing 491
Reset
Control Register 210
CRC 588
RESET_CNT_ON_GNT 140
reset_n timing 490
Timing Measurement Figure 500
Revision ID Register 08H 163
RI 194
RID 603, 625
Ring Indicators (Modem), SB 194
ROM
location of upper 119
Mask Register 214
ROM/AT Logic Control Register 211
RTC
Address Register 257
Configuration 300
Configuration Register Bitmap Table 309
Configuration Register Map Table 307
Control
Register A, 0AH 314
Register B, 0BH 316
Register C, 0CH 318

ZFx86 Data Book 1.0 Rev D

I

Register D, 0DH 319
Data Register 257
Index Shadow Register 226
Register Bitmap 321
Register Map Table 310
ZF-Logic, System Clock 447
RTS 194
RTS2_N 601
RX 194
RX_FIFO 352

S
S_EOT 350
SA, System Address Bus Lines 184
SB_GNT 118
SB_PCICLK 118
SB_REQ 118
SBHE_N 186
SCAN_EN 118
SCAN_MODE 118
SCL Frequency 334
SCL_C 189
SCL_N 261
Scratch Register Index 444
SD, System Data Bus 184
SDA 189, 261
SDRAM
Interface Signals Table 493
Mode Program Register 213H 158
Mode Program Register 214H 159
Mode Program Register, 213H 621
Mode Program Register, 214H 622
Power management, NB 136
Slew Control Register 239H 159
Slew Control Register, 239H 622
SDRAM_BANK_CONFIG 158
SDRAM_CKE 117
SDRAM_CMD_PIPELINE 156
SDRAM_CS 116
SDRAM_DQM 116
SDRAM_RA 117
SDRAM_WE 116
SDRAMCLK 117
SDRAMCLK_SKEW 146
SDRAMMPR 621
SDRAMSLEW 622
Second Level
General Traps & Timers 234
PME/SMI Status Mirror Register 219
PME/SMI Status Registe 228
Secondary IDE Registers 257

Page 664

I

Index
Seconds
Alarm Register, 01H 311
Register, Index 00H 310
SeekParm 589
Select Input, SB 193
Select, SB 192
Serial Input, SB 194
Serial Output, SB 194
Serial Port 1 Register Table 630
Serial Port 1/2 Configuration Register, F0H 293
Serial Port 2, Register Table 632
Serial Port Electrical Specifications 527
SerOut16 589
SerOut32 590
SerOut8 589
SerOutBits 590
SERR_N 180
SerRec 590
SerRecWait 591
SerSend 590
SerSend2 590
Shadow RAM
Read Enable Control Register, 200H 149
Read Enable Register, 200H 615
Write Enable Control Register, 201H 150
Write Enable Register, 201H 615
SHADRC 615
SHADWC 615
SHARP-IR Mode, SB 346
Signal Descriptions 172–194
Clock Interface Signals 173
CPU Interface Signals 174
IDE Interface Signals 180
Reset Interface Signals 173
USB Interface Signals 182
SIO PWUREQ SMI Status 220
SIO_HIPRI 148, 613
SIOCFG 263
SIR Mode, SB 347
Slave Address Enable 333
SLCK 600
SLCT 192
SLCTIN_N 600
SLIN_N 193
SMEMR 186
SMEMW 187
SMI
Speedup Disable Register 235
Status Register Summary Table 200
System Management Interrupt 174

ZFx86 Data Book 1.0 Rev D

SMIHLDERLOCK 142
SMM
base address 134
Control Register, 118H 606
memory space 119
North Bridge 134
SMM_DH_SEL 141
SMM_DL_SEL 141
SMM_EH_SEL 141
SMM_EL_SEL 141
SMMC 606
Snoop Control Register, 11DH 146, 611
SNOOPCTRL 611
Software SMI Register 228
South Bridge
ACCESS.Bus Interface 298, 322
Architecture 166
AT Compatibility Logic 170
Back-Side PCI Bus 168
Banked Logical Device Registers 263
Battery-Backed RAMs and Registers 306
Bus Arbitration 325
CEIR
Mode 347
Receive Operation 348
Transmit Operation 347
Chipset Register Space 206
DMA Controller 170
FDC Bitmap Summary 336
Features 165
FIFO
Control Register 362
Timeouts 352
Floppy Disk Controller 272, 336
GPIO
Interface 171
Support Registers 230
High Speed Infrared
Receive 351
Transmit 350
IDE Controller 168
Registers 236
Support Registers 239
IER, Extended Mode 358
Infrared Comm Port Config 297
Integrated SuperI/O 169
IR
Communication Port 345
Mode Register Bank 354
IrDA Mode 349

Page 665

I

Index
ISA
Bus Interface 169
Legacy Register Space 248
Keyboard/Mouse Control 294, 335
Master Mode 325
Modem Status Register 370
Mouse Wake-Up Events 283
Mouse/Keyboard Config 295
Optical Transceiver I/F 354
Parallel Port
Bitmap Summary Table 339
Register Map 338
Parallel Port Config 274–276
PCI Address/Data 176
Power Management 170
Power Supply 305
Programmable Interrupt Controller 170
Programmable Interval Timer 170
PS/2
Keyboard Registers 284
Keyboard/Mouse Wake-Up Events 283
RTC
Configuration Registers 307
Overview 302
Registers 309
Serial Port 1 and 2 Config 292
SHARP-IR Mode 346
SIR Mode 347
SMI Status Support Registers 233
SuperI/O 258–271
Configuration Registers 269
System Wake-Up Control 276, 294
Timekeeping 303
Timer Registers 382
Timing Generation 303
UART Functionality 340
USB 168
Controller Registers 246
Special cycles, NB 120
ST_FIFO 352
STALL_PCI_BM_POST 149
Standard RAM Map 321
STAT 624
Status FIFO, SB 386
Status Register
06H 163
USB 246
STB_N 193
Step, SB 190
STEP_N 597
STOP_N 178

ZFx86 Data Book 1.0 Rev D

STRB_N 600
Subsystem
ID 209
Vendor ID 209
SuperI/O 258–271
Configuration 1 Register, 21H 270
Configuration 2 Register 22H 271
Configuration Options Table 263
disabled 263
General Purpose Scratch 270
Global Device Enable 270
ID Register, 20H 270
Lock Scratch 270
Pin Function Lock 270
Revision ID Register 27H 271
SW Reset 270
SUSP, CPU Suspend 175
SUSPA, CPU Suspend Acknowledge 174
Suspend Configuration Register 223
Suspend Logic 451
Suspend Modulation
OFF Count Register 222
ON Count Registe 222
Suspend Notebook Command Register 225
SWAP_23_MAP 142
SWAP_DE_MAP 142
SYNC_OUT 162
SYSCLK, A20 450
sysclk_c 490
System
Address Bus Lines 184
Bus High Enable, SB 186
Clocking, ZF-Logic 447
Data Bus, SB 184
System Management
Interrupt 174
Mode 134
System Memory
Read 186
Write 187
System Wake-Up Control 276–298

T
TC 183
TCCD 152, 153, 154, 156
Temperature
Absolute Maximum Ratings 481
Recommended Operating Conditions 482
Terminal Count 183
Test signals, NB 162

Page 666

Index
TEST_SI1 118
TEST_SO1 118
TESTMODE 118
Timer Registers 382
Timer Test Register 228
Timing
Fast IR Port 528
Floppy Disk
Drive Control Timing 532
Reset 531
Write Data 531
GPIO 530
JTAG 529
Parallel Port 534
ZF-Logic 540
Top Level PME/SMI Status
Mirror Register 233
Register 233
Top of System Memory 211
Track 0, SB 190
Traps 216
TRC 152, 153, 154, 155
TRCD 152, 153, 154, 156
TRDY_N 178
TRK0 190
TRK0_N 597
TRP 152, 153, 154, 155
TX 194

U
UART
Functionality 340
SP1/SP2 Bitmap 343
Mode, SB 346
Serial Port Electrical Specifications 527
Ultra DMA Data Burst Timing Requirements 511
USB
ASIC
Operational Mode Enable Register 248
Test Mode Enable Register 248
BIST Register 247
Cache Line Size Register 247
Command Register 246
Controller Register Summary Table 203
Electrical Specifications Table 523
Header Type Register ( 247
Interrupt Line Register 247
Interrupt Pin Register 248
Latency Timer Register 247
Max. Latency Register 248
Min. Grant Register 248

ZFx86 Data Book 1.0 Rev D

I

Port Data Minus, SB 182
Port Data Positive, SB 182
South Bridge 168
Status Register 246
Subsystem ID 247
Subsystem Vendor ID 247
User Defined Device 216
Base Address Register 226
Control Register 227
Idle Timer Count Register 224
Using the Dongle 456

V
VBAT 193, 482
VDD 193
Vdd
Core 482
I/O 482
Vendor ID Register 207
00H 162
VENDOR_ID 162
VID 624
VIH 484

W
Wait, SB 192
Wake-Up 452
Configuration Register, 02H 282
Events
Control Register, 01H 281
Status Register 00H 280
Warm reset 118
Watchdog
Control 1 Register, 10H 648
Control 2 Register, 11H 648
Control High, 11H 428
Control Low, 10H 427
Generated Reset Pulse Length 427
Registers 426
Status, 12H 429
Timer 424
WCBR_MA 159
WDATA 190
WDATA_N 597
WDI 601
WDO 601
WE_SLEW 160
WFIFOC 609
WGATE 190
WGATE_N 597, 598

Page 667

Index
WKCFG 291
WKCR 291
WKSR 291
WR_LATENCY 144
WRFIFO_EN 143
Write buffer architecture, NB 134
Write data, SB 190
Write FIFO Control Register, 11AH 143, 609
Write Gate, SB 190
Write Protected, SB 190
Write Strobe, SB 193
WRM_RESET 118
WRM_RST 143
WRPRT 190
WRPRT_N 597

X
XBus Expansion Summary Table 202

Y
Year Register, 09H 313
YModemGetData 592
YModemGetHeader 591
YModemSendData 594
YModemSendHeader 594

Z
ZACK 598
ZCLK 598
ZDIN 598
Zero Wait States, SB 186
ZFiX 459
ZF-Logic
BUR Base Register 445
Clocking 403
Options 444
Composit BootStrap Register 438
Data Registers, F0H to FEH 444
GPCS I/O mapper 422
Indices For Memory Windows 411
io_cs 422
ISA Memory Mapper for Flash/SRAM 410
Mem_cs 410
Pin List Table 409
Pins Associated 408
PWM
Duty Cycle Index 406
Generator 430
I/O Control index 406

ZFx86 Data Book 1.0 Rev D

I

Prescaler Low Byte Index 406
Read Output Index 406
Register Space Summary 404
Register Summary Table 204
Revision Index 406
Scratch Register Index 444
System Clocking 447
Timing 540
Watchdog
Control High 428
Generated Reset Pulse 427
Registers 426
Status, 12H 429
Timer 424
ZGPI0 598
ZLED1 598
ZLED2 598
ZPGPI1/CEN2_N 598
ZRST 598
ZT_Init 595
Z-tag
Control Register 462
Dongle Jumpers 458
Floppy Disk Pins 460
Jumpers 458
Manager Software 459
Pass-through Mode 458
Using the dongle 456
ZFiX 459
ZTCMDExec 595
ZTPrepareRead 596
ZTRead 596
ZWS_N 186

Page 668

ZF Micro Solutions, Inc.
1000 Elwell Court - Suite 134
Palo Alto, California 94303
(650) 965-3800 · Fax 965-4050

www.zfmicro.com

ZFx86 Data Book 1.0 Rev D

Page 670



---

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Description                     : 9100-0044-01 Rev C
Title                           : ZFx86 Data Book
Creator                         : ZF Micro Devices, Inc.
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Author                          : ZF Micro Devices, Inc.
Subject                         : 9100-0044-01 Rev C

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