ARMv7 M Architecture Reference Manual Application Level
User Manual:
Open the PDF directly: View PDF
Page Count: 916 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- ARMv7-M Architecture Reference Manual
- Contents
- Preface
- Part A: Application Level Architecture
- A1: Introduction
- A2: Application Level Programmers’ Model
- A3: ARM Architecture Memory Model
- A3.1 Address space
- A3.2 Alignment support
- A3.3 Endian support
- A3.4 Synchronization and semaphores
- A3.4.1 Exclusive access instructions and Non-shareable memory regions
- A3.4.2 Exclusive access instructions and Shareable memory regions
- A3.4.3 Tagging and the size of the tagged memory block
- A3.4.4 Context switch support
- A3.4.5 Load-Exclusive and Store-Exclusive usage restrictions
- A3.4.6 Synchronization primitives and the memory order model
- A3.5 Memory types and attributes and the memory order model
- A3.6 Access rights
- A3.7 Memory access order
- A3.8 Caches and memory hierarchy
- A4: The ARMv7-M Instruction Set
- A4.1 About the instruction set
- A4.2 Unified Assembler Language
- A4.3 Branch instructions
- A4.4 Data-processing instructions
- A4.4.1 Standard data-processing instructions
- A4.4.2 Shift instructions
- A4.4.3 Multiply instructions
- A4.4.4 Saturating instructions
- A4.4.5 Packing and unpacking instructions
- A4.4.6 Divide instructions
- A4.4.7 Parallel addition and subtraction instructions, DSP extension
- A4.4.8 Miscellaneous data-processing instructions
- A4.5 Status register access instructions
- A4.6 Load and store instructions
- A4.7 Load Multiple and Store Multiple instructions
- A4.8 Miscellaneous instructions
- A4.9 Exception-generating instructions
- A4.10 Coprocessor instructions
- A4.11 Floating-point load and store instructions
- A4.12 Floating-point register transfer instructions
- A4.13 Floating-point data-processing instructions
- A5: The Thumb Instruction Set Encoding
- A5.1 Thumb instruction set encoding
- A5.2 16-bit Thumb instruction encoding
- A5.3 32-bit Thumb instruction encoding
- A5.3.1 Data processing (modified immediate)
- A5.3.2 Modified immediate constants in Thumb instructions
- A5.3.3 Data processing (plain binary immediate)
- A5.3.4 Branches and miscellaneous control
- A5.3.5 Load Multiple and Store Multiple
- A5.3.6 Load/store dual or exclusive, table branch
- A5.3.7 Load word
- A5.3.8 Load halfword, memory hints
- A5.3.9 Load byte, memory hints
- A5.3.10 Store single data item
- A5.3.11 Data processing (shifted register)
- A5.3.12 Data processing (register)
- A5.3.13 Parallel addition and subtraction, signed
- A5.3.14 Parallel addition and subtraction, unsigned
- A5.3.15 Miscellaneous operations
- A5.3.16 Multiply, multiply accumulate, and absolute difference
- A5.3.17 Long multiply, long multiply accumulate, and divide
- A5.3.18 Coprocessor instructions
- A6: The Floating-Point Instruction Set Encoding
- A7: Instruction Details
- A7.1 Format of instruction descriptions
- A7.2 Standard assembler syntax fields
- A7.3 Conditional execution
- A7.4 Shifts applied to a register
- A7.5 Memory accesses
- A7.6 Hint Instructions
- A7.7 Alphabetical list of ARMv7-M Thumb instructions
- A7.7.1 ADC (immediate)
- A7.7.2 ADC (register)
- A7.7.3 ADD (immediate)
- A7.7.4 ADD (register)
- A7.7.5 ADD (SP plus immediate)
- A7.7.6 ADD (SP plus register)
- A7.7.7 ADR
- A7.7.8 AND (immediate)
- A7.7.9 AND (register)
- A7.7.10 ASR (immediate)
- A7.7.11 ASR (register)
- A7.7.12 B
- A7.7.13 BFC
- A7.7.14 BFI
- A7.7.15 BIC (immediate)
- A7.7.16 BIC (register)
- A7.7.17 BKPT
- A7.7.18 BL
- A7.7.19 BLX (register)
- A7.7.20 BX
- A7.7.21 CBNZ, CBZ
- A7.7.22 CDP, CDP2
- A7.7.23 CLREX
- A7.7.24 CLZ
- A7.7.25 CMN (immediate)
- A7.7.26 CMN (register)
- A7.7.27 CMP (immediate)
- A7.7.28 CMP (register)
- A7.7.29 CPS
- A7.7.30 CPY
- A7.7.31 DBG
- A7.7.32 DMB
- A7.7.33 DSB
- A7.7.34 EOR (immediate)
- A7.7.35 EOR (register)
- A7.7.36 ISB
- A7.7.37 IT
- A7.7.38 LDC, LDC2 (immediate)
- A7.7.39 LDC, LDC2 (literal)
- A7.7.40 LDM, LDMIA, LDMFD
- A7.7.41 LDMDB, LDMEA
- A7.7.42 LDR (immediate)
- A7.7.43 LDR (literal)
- A7.7.44 LDR (register)
- A7.7.45 LDRB (immediate)
- A7.7.46 LDRB (literal)
- A7.7.47 LDRB (register)
- A7.7.48 LDRBT
- A7.7.49 LDRD (immediate)
- A7.7.50 LDRD (literal)
- A7.7.51 LDREX
- A7.7.52 LDREXB
- A7.7.53 LDREXH
- A7.7.54 LDRH (immediate)
- A7.7.55 LDRH (literal)
- A7.7.56 LDRH (register)
- A7.7.57 LDRHT
- A7.7.58 LDRSB (immediate)
- A7.7.59 LDRSB (literal)
- A7.7.60 LDRSB (register)
- A7.7.61 LDRSBT
- A7.7.62 LDRSH (immediate)
- A7.7.63 LDRSH (literal)
- A7.7.64 LDRSH (register)
- A7.7.65 LDRSHT
- A7.7.66 LDRT
- A7.7.67 LSL (immediate)
- A7.7.68 LSL (register)
- A7.7.69 LSR (immediate)
- A7.7.70 LSR (register)
- A7.7.71 MCR, MCR2
- A7.7.72 MCRR, MCRR2
- A7.7.73 MLA
- A7.7.74 MLS
- A7.7.75 MOV (immediate)
- A7.7.76 MOV (register)
- A7.7.77 MOV (shifted register)
- A7.7.78 MOVT
- A7.7.79 MRC, MRC2
- A7.7.80 MRRC, MRRC2
- A7.7.81 MRS
- A7.7.82 MSR
- A7.7.83 MUL
- A7.7.84 MVN (immediate)
- A7.7.85 MVN (register)
- A7.7.86 NEG
- A7.7.87 NOP
- A7.7.88 ORN (immediate)
- A7.7.89 ORN (register)
- A7.7.90 ORR (immediate)
- A7.7.91 ORR (register)
- A7.7.92 PKHBT, PKHTB
- A7.7.93 PLD (immediate)
- A7.7.94 PLD (literal)
- A7.7.95 PLD (register)
- A7.7.96 PLI (immediate, literal)
- A7.7.97 PLI (register)
- A7.7.98 POP
- A7.7.99 PUSH
- A7.7.100 QADD
- A7.7.101 QADD16
- A7.7.102 QADD8
- A7.7.103 QASX
- A7.7.104 QDADD
- A7.7.105 QDSUB
- A7.7.106 QSAX
- A7.7.107 QSUB
- A7.7.108 QSUB16
- A7.7.109 QSUB8
- A7.7.110 RBIT
- A7.7.111 REV
- A7.7.112 REV16
- A7.7.113 REVSH
- A7.7.114 ROR (immediate)
- A7.7.115 ROR (register)
- A7.7.116 RRX
- A7.7.117 RSB (immediate)
- A7.7.118 RSB (register)
- A7.7.119 SADD16
- A7.7.120 SADD8
- A7.7.121 SASX
- A7.7.122 SBC (immediate)
- A7.7.123 SBC (register)
- A7.7.124 SBFX
- A7.7.125 SDIV
- A7.7.126 SEL
- A7.7.127 SEV
- A7.7.128 SHADD16
- A7.7.129 SHADD8
- A7.7.130 SHASX
- A7.7.131 SHSAX
- A7.7.132 SHSUB16
- A7.7.133 SHSUB8
- A7.7.134 SMLABB, SMLABT, SMLATB, SMLATT
- A7.7.135 SMLAD, SMLADX
- A7.7.136 SMLAL
- A7.7.137 SMLALBB, SMLALBT, SMLALTB, SMLALTT
- A7.7.138 SMLALD, SMLALDX
- A7.7.139 SMLAWB, SMLAWT
- A7.7.140 SMLSD, SMLSDX
- A7.7.141 SMLSLD, SMLSLDX
- A7.7.142 SMMLA, SMMLAR
- A7.7.143 SMMLS, SMMLSR
- A7.7.144 SMMUL, SMMULR
- A7.7.145 SMUAD, SMUADX
- A7.7.146 SMULBB, SMULBT, SMULTB, SMULTT
- A7.7.147 SMULL
- A7.7.148 SMULWB, SMULWT
- A7.7.149 SMUSD, SMUSDX
- A7.7.150 SSAT
- A7.7.151 SSAT16
- A7.7.152 SSAX
- A7.7.153 SSUB16
- A7.7.154 SSUB8
- A7.7.155 STC, STC2
- A7.7.156 STM, STMIA, STMEA
- A7.7.157 STMDB, STMFD
- A7.7.158 STR (immediate)
- A7.7.159 STR (register)
- A7.7.160 STRB (immediate)
- A7.7.161 STRB (register)
- A7.7.162 STRBT
- A7.7.163 STRD (immediate)
- A7.7.164 STREX
- A7.7.165 STREXB
- A7.7.166 STREXH
- A7.7.167 STRH (immediate)
- A7.7.168 STRH (register)
- A7.7.169 STRHT
- A7.7.170 STRT
- A7.7.171 SUB (immediate)
- A7.7.172 SUB (register)
- A7.7.173 SUB (SP minus immediate)
- A7.7.174 SUB (SP minus register)
- A7.7.175 SVC
- A7.7.176 SXTAB
- A7.7.177 SXTAB16
- A7.7.178 SXTAH
- A7.7.179 SXTB
- A7.7.180 SXTB16
- A7.7.181 SXTH
- A7.7.182 TBB, TBH
- A7.7.183 TEQ (immediate)
- A7.7.184 TEQ (register)
- A7.7.185 TST (immediate)
- A7.7.186 TST (register)
- A7.7.187 UADD16
- A7.7.188 UADD8
- A7.7.189 UASX
- A7.7.190 UBFX
- A7.7.191 UDF
- A7.7.192 UDIV
- A7.7.193 UHADD16
- A7.7.194 UHADD8
- A7.7.195 UHASX
- A7.7.196 UHSAX
- A7.7.197 UHSUB16
- A7.7.198 UHSUB8
- A7.7.199 UMAAL
- A7.7.200 UMLAL
- A7.7.201 UMULL
- A7.7.202 UQADD16
- A7.7.203 UQADD8
- A7.7.204 UQASX
- A7.7.205 UQSAX
- A7.7.206 UQSUB16
- A7.7.207 UQSUB8
- A7.7.208 USAD8
- A7.7.209 USADA8
- A7.7.210 USAT
- A7.7.211 USAT16
- A7.7.212 USAX
- A7.7.213 USUB16
- A7.7.214 USUB8
- A7.7.215 UXTAB
- A7.7.216 UXTAB16
- A7.7.217 UXTAH
- A7.7.218 UXTB
- A7.7.219 UXTB16
- A7.7.220 UXTH
- A7.7.221 VABS
- A7.7.222 VADD
- A7.7.223 VCMP, VCMPE
- A7.7.224 VCVTA, VCVTN, VCVTP, and VCVTM
- A7.7.225 VCVT, VCVTR (between floating-point and integer)
- A7.7.226 VCVT (between floating-point and fixed-point)
- A7.7.227 VCVT (between double-precision and single-precision)
- A7.7.228 VCVTB, VCVTT
- A7.7.229 VDIV
- A7.7.230 VFMA, VFMS
- A7.7.231 VFNMA, VFNMS
- A7.7.232 VLDM
- A7.7.233 VLDR
- A7.7.234 VMAXNM, VMINNM
- A7.7.235 VMLA, VMLS
- A7.7.236 VMOV (immediate)
- A7.7.237 VMOV (register)
- A7.7.238 VMOV (ARM core register to scalar)
- A7.7.239 VMOV (scalar to ARM core register)
- A7.7.240 VMOV (between ARM core register and single-precision register)
- A7.7.241 VMOV (between two ARM core registers and two single-precision registers)
- A7.7.242 VMOV (between two ARM core registers and a doubleword register)
- A7.7.243 VMRS
- A7.7.244 VMSR
- A7.7.245 VMUL
- A7.7.246 VNEG
- A7.7.247 VNMLA, VNMLS, VNMUL
- A7.7.248 VPOP
- A7.7.249 VPUSH
- A7.7.250 VRINTA, VRINTN, VRINTP, and VRINTM
- A7.7.251 VRINTX
- A7.7.252 VRINTZ, VRINTR
- A7.7.253 VSEL
- A7.7.254 VSQRT
- A7.7.255 VSTM
- A7.7.256 VSTR
- A7.7.257 VSUB
- A7.7.258 WFE
- A7.7.259 WFI
- A7.7.260 YIELD
- Part B: System Level Architecture
- B1: System Level Programmers’ Model
- B1.1 Introduction to the system level
- B1.2 About the ARMv7-M memory mapped architecture
- B1.3 Overview of system level terminology and operation
- B1.4 Registers
- B1.4.1 The ARM core registers
- B1.4.2 The special-purpose program status registers, xPSR
- B1.4.3 The special-purpose mask registers
- B1.4.4 The special-purpose CONTROL register
- B1.4.5 Reserved special-purpose register bits
- B1.4.6 Special-purpose register updates and the memory order model
- B1.4.7 Register-related definitions for pseudocode
- B1.5 ARMv7-M exception model
- B1.5.1 Overview of the exceptions supported
- B1.5.2 Exception number definition
- B1.5.3 The vector table
- B1.5.4 Exception priorities and preemption
- B1.5.5 Reset behavior
- B1.5.6 Exception entry behavior
- B1.5.7 Stack alignment on exception entry
- B1.5.8 Exception return behavior
- B1.5.9 Exceptions in single-word load operations
- B1.5.10 Exceptions in Load Multiple and Store Multiple operations
- B1.5.11 Exceptions on exception entry
- B1.5.12 Exceptions on exception return, and tail-chaining exceptions
- B1.5.13 Exception status and control
- B1.5.14 Fault behavior
- B1.5.15 Unrecoverable exception cases
- B1.5.16 Reset management
- B1.5.17 Power management
- B1.5.18 Wait For Event and Send Event
- B1.5.19 Wait For Interrupt
- B1.6 Floating-point support
- B2: System Memory Model
- B2.1 About the system memory model
- B2.2 Caches and branch predictors
- B2.2.1 Cache identification
- B2.2.2 Cache enabling and disabling
- B2.2.3 Cache behavior
- B2.2.4 Branch predictors
- B2.2.5 Terms used in describing cache maintenance operations
- B2.2.6 The ARMv7-M abstraction of the cache hierarchy
- B2.2.7 Cache and branch predictor maintenance operations
- B2.2.8 System level caches
- B2.2.9 Performing cache maintenance operations
- B2.3 Pseudocode details of general memory system operations
- B2.3.1 Memory data type definitions
- B2.3.2 Basic memory accesses
- B2.3.3 Interfaces to memory system specific pseudocode
- B2.3.4 Aligned memory accesses
- B2.3.5 Unaligned memory accesses
- B2.3.6 Reverse endianness
- B2.3.7 Pseudocode details of operations on exclusive monitors
- B2.3.8 Access permission checking
- B2.3.9 MPU access control decode
- B2.3.10 Default memory access decode
- B2.3.11 MemManage fault handling
- B3: System Address Map
- B3.1 The system address map
- B3.2 System Control Space (SCS)
- B3.2.1 About the System Control Block
- B3.2.2 System control and ID registers
- B3.2.3 CPUID Base Register
- B3.2.4 Interrupt Control and State Register, ICSR
- B3.2.5 Vector Table Offset Register, VTOR
- B3.2.6 Application Interrupt and Reset Control Register, AIRCR
- B3.2.7 System Control Register, SCR
- B3.2.8 Configuration and Control Register, CCR
- B3.2.9 About the System Handler Priority Registers
- B3.2.10 System Handler Priority Register 1, SHPR1
- B3.2.11 System Handler Priority Register 2, SHPR2
- B3.2.12 System Handler Priority Register 3, SHPR3
- B3.2.13 System Handler Control and State Register, SHCSR
- B3.2.14 Status registers for configurable-priority faults
- B3.2.15 Configurable Fault Status Register, CFSR
- B3.2.16 HardFault Status Register, HFSR
- B3.2.17 MemManage Fault Address Register, MMFAR
- B3.2.18 BusFault Address Register, BFAR
- B3.2.19 Auxiliary Fault Status Register, AFSR
- B3.2.20 Coprocessor Access Control Register, CPACR
- B3.2.21 Floating Point Context Control Register, FPCCR
- B3.2.22 Floating Point Context Address Register, FPCAR
- B3.2.23 Floating Point Default Status Control Register, FPDSCR
- B3.2.24 Interrupt Controller Type Register, ICTR
- B3.2.25 Auxiliary Control Register, ACTLR
- B3.2.26 Software Triggered Interrupt Register, STIR
- B3.3 The system timer, SysTick
- B3.4 Nested Vectored Interrupt Controller, NVIC
- B3.4.1 NVIC operation
- B3.4.2 Implemented interrupts
- B3.4.3 NVIC register support in the SCS
- B3.4.4 Interrupt Set-Enable Registers, NVIC_ISER0-NVIC_ISER15
- B3.4.5 Interrupt Clear-Enable Registers, NVIC_ICER0-NVIC_ICER15
- B3.4.6 Interrupt Set-Pending Registers, NVIC_ISPR0-NVIC_ISPR15
- B3.4.7 Interrupt Clear-Pending Registers, NVIC_ICPR0-NVIC_ICPR15
- B3.4.8 Interrupt Active Bit Registers, NVIC_IABR0-NVIC_IABR15
- B3.4.9 Interrupt Priority Registers, NVIC_IPR0-NVIC_IPR123
- B3.5 Protected Memory System Architecture, PMSAv7
- B3.5.1 Relation of the MPU to the system memory map
- B3.5.2 Behavior when the MPU is disabled
- B3.5.3 PMSAv7-compliant MPU operation
- B3.5.4 Register support for PMSAv7 in the SCS
- B3.5.5 MPU Type Register, MPU_TYPE
- B3.5.6 MPU Control Register, MPU_CTRL
- B3.5.7 MPU Region Number Register, MPU_RNR
- B3.5.8 MPU Region Base Address Register, MPU_RBAR
- B3.5.9 MPU Region Attribute and Size Register, MPU_RASR
- B3.5.10 MPU alias register support
- B4: The CPUID Scheme
- B4.1 About the CPUID scheme
- B4.2 Processor Feature ID Registers
- B4.3 Debug Feature ID register
- B4.4 Auxiliary Feature ID register
- B4.5 Memory Model Feature Registers
- B4.6 Instruction Set Attribute Registers
- B4.6.1 About the Instruction Set Attribute Register descriptions
- B4.6.2 Instruction Set Attribute Register 0, ID_ISAR0
- B4.6.3 Instruction Set Attribute Register 1, ID_ISAR1
- B4.6.4 Instruction Set Attribute Register 2, ID_ISAR2
- B4.6.5 Instruction Set Attribute Register 3, ID_ISAR3
- B4.6.6 Instruction Set Attribute Register 4, ID_ISAR4
- B4.7 Floating-point feature identification registers
- B4.8 Cache Control Identification Registers
- B5: System Instruction Details
- Part C: Debug Architecture
- C1: ARMv7-M Debug
- C1.1 Introduction to ARMv7-M debug
- C1.2 The Debug Access Port
- C1.3 ARMv7-M debug features
- C1.4 Debug and reset
- C1.5 Debug event behavior
- C1.6 Debug system registers
- C1.7 The Instrumentation Trace Macrocell
- C1.8 The Data Watchpoint and Trace unit
- C1.8.1 The DWT comparators
- C1.8.2 Exception trace support
- C1.8.3 CYCCNT cycle counter and related timers
- C1.8.4 Profiling counter support
- C1.8.5 Program counter sampling support
- C1.8.6 DWT register summary
- C1.8.7 Control register, DWT_CTRL
- C1.8.8 Cycle Count register, DWT_CYCCNT
- C1.8.9 CPI Count register, DWT_CPICNT
- C1.8.10 Exception Overhead Count register, DWT_EXCCNT
- C1.8.11 Sleep Count register, DWT_SLEEPCNT
- C1.8.12 LSU Count register, DWT_LSUCNT
- C1.8.13 Folded-instruction Count register, DWT_FOLDCNT
- C1.8.14 Program Counter Sample Register, DWT_PCSR
- C1.8.15 Comparator registers, DWT_COMPn
- C1.8.16 Comparator Mask registers, DWT_MASKn
- C1.8.17 Comparator Function registers, DWT_FUNCTIONn
- C1.9 Embedded Trace Macrocell support
- C1.10 Trace Port Interface Unit
- C1.11 Flash Patch and Breakpoint unit
- Part D: Appendixes
- D1: ARMv7-M CoreSight Infrastructure IDs
- D2: Legacy Instruction Mnemonics
- D3: Deprecated Features in ARMv7-M
- D4: Debug ITM and DWT Packet Protocol
- D5: ARMv7-R Differences
- D6: Pseudocode Definition
- D6.1 Instruction encoding diagrams and pseudocode
- D6.2 Limitations of pseudocode
- D6.3 Data types
- D6.4 Expressions
- D6.5 Operators and built-in functions
- D6.6 Statements and program structure
- D6.7 Miscellaneous helper procedures and functions
- D6.7.1 ArchVersion()
- D6.7.2 BKPTInstrDebugEvent()
- D6.7.3 BreakPoint()
- D6.7.4 CallSupervisor()
- D6.7.5 ConditionPassed()
- D6.7.6 Coproc_Accepted()
- D6.7.7 Coproc_DoneLoading()
- D6.7.8 Coproc_DoneStoring()
- D6.7.9 Coproc_GetOneWord()
- D6.7.10 Coproc_GetTwoWords()
- D6.7.11 Coproc_GetWordToStore()
- D6.7.12 Coproc_InternalOperation()
- D6.7.13 Coproc_SendLoadedWord()
- D6.7.14 Coproc_SendOneWord()
- D6.7.15 Coproc_SendTwoWords()
- D6.7.16 DataMemoryBarrier()
- D6.7.17 DataSynchronizationBarrier()
- D6.7.18 EncodingSpecificOperations()
- D6.7.19 GenerateCoprocessorException()
- D6.7.20 GenerateIntegerZeroDivide()
- D6.7.21 HaveDSPExt()
- D6.7.22 HaveFPExt()
- D6.7.23 Hint_Debug()
- D6.7.24 Hint_PreloadData()
- D6.7.25 Hint_PreloadInstr()
- D6.7.26 Hint_SendEvent()
- D6.7.27 Hint_Yield()
- D6.7.28 InstructionSynchronizationBarrier()
- D6.7.29 IntegerZeroDivideTrappingEnabled()
- D6.7.30 ProcessorID()
- D6.7.31 ResetSCSRegs()
- D6.7.32 SetPending()
- D6.7.33 SerializeVFP()
- D6.7.34 ThisInstr()
- D6.7.35 VFPExcBarrier()
- D7: Pseudocode Index
- D8: Register Index
- Glossary