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W170HN

Preface

Notebook Computer
W170HN
Service Manual
Preface

I

Preface

Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes.

Preface

Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Version 1.0
April 2011

Trademarks
Intel, and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.

II

Preface

About this Manual
This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the W170HN
series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.

Preface

Appendix A, Part Lists
Appendix B, Schematic Diagrams
Appendix C, Updating the FLASH ROM BIOS

III

Preface

IMPORTANT SAFETY INSTRUCTIONS
Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment:

Preface

1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 4.74A (90W) minimum AC/DC Adapter.

CAUTION

This Computer’s Optical Device is a Laser Class 1 Product

FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.

IV

Preface

Instructions for Care and Operation
The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1.

Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer
to any shock or vibration.

2.

Do not place anything heavy
on the computer.

Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not leave it in a place
where foreign matter or moisture may affect the system.

Don’t use or store the computer in a humid environment.

Do not place the computer on
any surface which will block
the vents.

Preface

Do not expose it to excessive
heat or direct sunlight.

3.

Do not place it on an unstable
surface.

Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power
until you properly shut down
all programs.

Do not turn off any peripheral
devices when the computer is
on.

Do not disassemble the computer by yourself.

Perform routine maintenance
on your computer.

V

Preface
4.
5.

Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data.
Take care when using peripheral devices.
Use only approved brands of
peripherals.

Unplug the power cord before
attaching peripheral devices.

Preface

Power Safety
The computer has specific power requirements:



VI

•
•

Power Safety
Warning

•

Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.

•
•
•

Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
Before cleaning the computer, make sure it is disconnected from any external power supplies.
Do not plug in the power
cord if you are wet.

Do not use the power cord if
it is broken.

Do not place heavy objects
on the power cord.

Preface

Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.

Battery Guidelines

Preface

The following can also apply to any backup batteries you may have.
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.


Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.

Battery Level
Click the battery icon
in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.

VII

Preface

Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD/DVD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.

System Startup
Remove all packing materials.
Place the computer on a stable surface.
Insert the battery and make sure it is locked in position.
Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
5. Attach the AC/DC adapter to the DC-In jack at the rear of the
computer, then plug the AC power cord into an outlet, and connect
the AC power cord to the AC/DC adapter.
6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 130 degrees); use the other hand (as illustrated in
Figure 1) to support the base of the computer (Note: Never lift the
computer by the lid/LCD).
7. Press the power button to turn the computer “on”.

Preface

1.
2.
3.
4.


Shut Down
Note that you should always shut your computer down by choosing Shut Down from
the Start Menu.
This will help prevent hard disk or system
problems.

VIII

Figure 1
Opening the Lid/LCD/
Computer with AC/DC
Adapter Plugged-In

130

Preface

Contents
Introduction ..............................................1-1
Overview .........................................................................................1-1
Specifications ..................................................................................1-2
External Locator - Top View with LCD Panel Open ......................1-4
External Locator - Front & Right Side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) .........................................1-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9
Mainboard Overview - Top (Connectors) .....................................1-10
Mainboard Overview - Bottom (Connectors) ...............................1-11
Overview .........................................................................................2-1
Maintenance Tools ..........................................................................2-2
Connections .....................................................................................2-2
Maintenance Precautions .................................................................2-3
Disassembly Steps ...........................................................................2-4
Removing the Battery ......................................................................2-5
Removing the Hard Disk Drive .......................................................2-6
Removing the Optical (CD/DVD) Device ......................................2-8
Removing the System Memory (RAM) ..........................................2-9
Removing and Installing a Processor ............................................2-11
Removing the Wireless LAN Module ...........................................2-14
Removing the Keyboard ................................................................2-15

Part Lists ..................................................A-1
Part List Illustration Location ........................................................ A-2
Top ................................................................................................. A-3
Bottom ............................................................................................ A-4
LCD ............................................................................................... A-5

Schematic Diagrams................................. B-1
System Block Diagram ...................................................................B-2
CPU 1/7 (DMI, PEG, FDI) .............................................................B-3
CPU 2/7 (CLK, MISC, JTAG) .......................................................B-4
CPU 3/7 (DDR3) ............................................................................B-5
CPU 4/7 (Power) .............................................................................B-6
CPU 5/7 (Graphics Power) .............................................................B-7
CPU 6/7 (GND) ..............................................................................B-8
CPU 7/7 (RESERVED) ..................................................................B-9
DDR3 SO-DIMM_0 .....................................................................B-10
DDR3 SO-DIMM_1 .....................................................................B-11
Panel, Inverter, CRT .....................................................................B-12
VGA PCI-E Interface ....................................................................B-13
VGA Frame Buffer Interface ........................................................B-14
VGA Frame Buffer A ...................................................................B-15
VGA Frame Buffer C ...................................................................B-16
VGA I/O .......................................................................................B-17
VGA NVVDD Cecoupling ...........................................................B-18
CougarPoint - M 1/9 .....................................................................B-19
CougarPoint - M 2/9 .....................................................................B-20
CougarPoint - M 3/9 .....................................................................B-21
CougarPoint - M 4/9 .....................................................................B-22
CougarPoint - M 5/9 .....................................................................B-23
CougarPoint - M 6/9 .....................................................................B-24
CougarPoint - M 7/9 .....................................................................B-25
CougarPoint - M 8/9 .....................................................................B-26
CougarPoint - M 9/9 .....................................................................B-27
IX

Preface

Disassembly ...............................................2-1

SATA BLU-RAY Combo ............................................................. A-6
SATA DVD ................................................................................... A-7
HDD ............................................................................................... A-8

Preface

Preface
WLAN, 3G, Mini PCIE ................................................................ B-28
USB, Fan, TP, FP, Multi-Conn .................................................... B-29
USB 3.0 ........................................................................................ B-30
Card Reader (JMC251C) .............................................................. B-31
SATA ODD, LED, Hotkey, LID SW ........................................... B-32
HDMI, RJ45 ................................................................................. B-33
Audio Codec ALC269 .................................................................. B-34
KBC-ITE IT8518E ....................................................................... B-35
5VS, 3VS, 3.3VM, 1.5VS_CPU .................................................. B-36
VDD3, VDD5 ............................................................................... B-37
Power 0.85VS, 1.8VS, PEX_VDD .............................................. B-38
Power 1.5V/1.05VS/0.75V ........................................................... B-39
Power V-Core1 ............................................................................. B-40
Power V-Core2 ............................................................................. B-41
Power VGA NVVDD ................................................................... B-42
AC_IN, Charger ........................................................................... B-43
W150HNM Audio Board ............................................................. B-44
W150HNM Second HDD Board .................................................. B-45
B5100 Click Board ....................................................................... B-46
B5100 Fingerprint Board ............................................................. B-47
B5100 LED & VGA SW Board ................................................... B-48
B5100 Power Switch Board ......................................................... B-49
Sequence ....................................................................................... B-50

Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ....................................................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive ................................................................................................ C-1
Set the computer to boot from the external drive ........................... C-1
Use the flash tools to update the BIOS .......................................... C-2
Restart the computer (booting from the HDD) .............................. C-2
X

Introduction

Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the W170HN series notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s
Manual. The manual is shipped with the computer.
Operating systems (e.g. Window 7, etc.) have their own manuals as do application softwares (e.g. word processing and database programs). If you
have questions about those programs, you should consult those manuals.

The balance of this chapter reviews the computer’s technical specifications and features.

Overview 1 - 1

1.Introduction

The W170HN series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description of the upgrade procedures
for each specific component. Please take note of the warning and safety information indicated by the “” symbol.

Introduction

Specifications

Latest Specification Information

1.Introduction

The specifications listed here are correct at the
time of sending them to the press. Certain items
(particularly processor types/speeds) may be
changed, delayed or updated due to the manufacturer's release schedule. Check with your
service center for more details.


CPU
The CPU is not a user serviceable part. Accessing the CPU in any way may violate your
warranty.

Processor Options

Video Adapter

Intel® Core™ i7 Processor
i7-2820QM (2.30GHz)
8MB L3 Cache, 32nm, DDR3-1600MHz, TDP 45W
i7-2720QM (2.20GHz)
6MB L3 Cache, 32nm, DDR3-1600MHz, TDP 45W
i7-2630QM (2.00GHz)
6MB L3 Cache, 32nm, DDR3-1333MHz, TDP 45W
i7-2620M (2.70GHz)
4MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W
Intel® Core™ i5 Processor
i5-2540M (2.60GHz), i5-2520M (2.50GHz), 
i5-2410M (2.30GHz)
3MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W
Intel® Core™ i3 Processor
i3-2310M (2.10GHz)
3MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W

Intel® GMA HD and NVIDIA® GeForce N12P-GS
Supports NVIDIA® Optimus Technology

Core Logic
Intel® HM65 Chipset

BIOS
One 32Mb SPI Flash ROM
Phoenix™ BIOS

LCD
17.3" (43.94cm) HD+/ FHD LCD

Memory
Two 204 Pin SO-DIMM Sockets Supporting DDR3 1333/
1600MHz Memory
Memory Expandable up to 8GB

1 - 2 Specifications

Intel Integrated GPU (Intel® GMA HD):
Microsoft DirectX®10.1 Compatible
NVIDIA Discrete GPU (NVIDIA® GeForce N12P-GS):
1GB GDDR3 Video RAM
Microsoft DirectX®11 Compatible

Security
BIOS Password
Security (Kensington® Type) Lock Slot

Audio
High Definition Audio Compliant Interface
THX TruStudio Pro
2 * Built-In Speakers
Built-In Microphone

Storage
(Factory Option) One Changeable 12.7mm(h) Optical Device
Type Drive (Super Multi Drive Module or Blu-Ray Combo Drive
Module)
One Changeable 2.5" 9.5 mm (h) SATA (Serial) HDD

Interface
Two USB 2.0 Ports
Two USB 3.0 Ports
One eSATA Port
One HDMI-Out Port
One Headphone-Out Jack
One Microphone-In Jack
One S/PDIF Out Jack
One RJ-45 LAN Jack
One External Monitor Port
One DC-in Jack

Introduction
Keyboard

Power

Full-size “WinKey” keyboard (with numeric keypad)

Full Range AC/DC Adapter
AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 4.74A (90W)

Pointing Device
Built-in Touchpad (scrolling key functionality integrated)

Communication

Dimensions & Weight
413mm (w) * 277.5mm (d) * 25.1 - 38.9mm (h)
3.1kg with ODD & 48.84WH Battery

1.Introduction

Built-In Gigabit Ethernet LAN
(Factory Option) 1.3M/2.0M Pixel USB PC Camera Module
(Factory Option) Intel® WiFi Link 6230 (802.11a/g/n) Wireless LAN + Bluetooth 3.0 Half Mini-Card Combo Module
(Factory Option) Intel® WiFi Link 1030 (802.11b/g/n) Wireless LAN + Bluetooth 3.0 Half Mini-Card Combo Module
(Factory Option) Intel® WiFi Link 6300 (802.11a/g/n) Wireless LAN Half Mini-Card Module
(Factory Option) Third-Party Wireless LAN (802.11b/g/n) +
Bluetooth 3.0 Half Mini-Card Combo Module

6 Cell Smart Lithium-Ion Battery Pack, 48.84WH
(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH

(Factory Option) Third-Party 802.11b/g/n Wireless LAN Half
Mini-Card Module

Card Reader
Embedded Multi-in-1 Card Reader
MMC (MultiMedia Card) / RS MMC

SD (Secure Digital) / Mini SD / SDHC/ SDXC
MS (Memory Stick) / MS Pro / MS Duo

Mini Card Slots
Slot 1 for WLAN Module or WLAN and Bluetooth Combo
Module

Environmental Spec
Temperature
Operating: 5°C - 35°C
Non-Operating: -20°C - 60°C
Relative Humidity
Operating: 20% - 80%
Non-Operating: 10% - 90%

Specifications 1 - 3

Introduction

External Locator - Top View with LCD Panel Open
Figure 1
Top View

1.Introduction

1
1. PC Camera
(Optional)
2. LCD
3. Power Button
4. GPU Button
5. LED Indicators
6. Hot Key Buttons
7. Keyboard
8. Built-In
Microphone
9. Touchpad &
Buttons

2

3
4

5

6
7

8
9

1 - 4 External Locator - Top View with LCD Panel Open

3

Introduction

External Locator - Front & Right Side Views

Figure 2
Front View
1. LED Indicators

1

1

2

3

4

5

6

1. Headphone-Out
Jack
2. Microphone-In
Jack
3. S/PDIF-Out Jack
4. USB 2.0 Port
5. Optical Device
Drive Bay
6. Emergency Eject
Hole

External Locator - Front & Right Side Views 1 - 5

1.Introduction

Figure 3
Right Side View

Introduction

External Locator - Left Side & Rear View
/

Figure 4

1.Introduction

Left Side View
1. External Monitor
Port
2. RJ-45 LAN Jack
3. HDMI-Out Port
4. USB 2.0 Port
5. 2 * USB 3.0 Ports
6. Vent
7. eSATA Port
8. Multi-in-1 Card
Reader

1

2

3

4

5
6

7

5

8

Figure 5
Rear View
1. Security Lock Slot
2. Battery
3. DC-In Jack

1

1 - 6 External Locator - Left Side & Rear View

2

3

Introduction

External Locator - Bottom View

Figure 5
Bottom View

1
3

1. Battery
2. Component Bay
Cover
3. Vent
4. Hard Disk Bay
Cover
5. Speakers

1.Introduction

3

3
2


4

5

Overheating

3

5

To prevent your computer from overheating, make sure nothing blocks any vent
while the computer is
in use.

External Locator - Bottom View 1 - 7

Introduction
Figure 6

Mainboard Overview - Top (Key Parts)

Mainboard Top
Key Parts

1.Introduction

1. JMC251C
2. KBC-ITE IT8502E
3. Audio Codec

1

2

3

1 - 8 Mainboard Overview - Top (Key Parts)

Introduction

Mainboard Overview - Bottom (Key Parts)

Figure 7
Mainboard Bottom
Key Parts

1

2

3

4

5

Mainboard Overview - Bottom (Key Parts) 1 - 9

1.Introduction

1. CPU Socket (no
CPU installed)
2. Memory Slots
DDR3 SO-DIMM
3. Mini-Card
Connector (WLAN
Module)
4. Platform Controller
Hub
5. Multi-in-1 Card
Reader

Introduction
Figure 8

Mainboard Overview - Top (Connectors)

Mainboard Top
Connectors

1.Introduction

1.
2.
3.
4.
5.

HDMI-Out Port
USB 2.0 Port
USB 3.0 Ports
eSATA Port
LED Cable
Connector
6. Microphone
Cable Connector
7. Audio Cable
Connector
8. TouchPad Cable
Connector
9. Keyboard Cable
Connector
10. Switch Board
Cable Connector

10
1

2
5
3
8

9

6
4

3
7

1 - 10 Mainboard Overview - Top (Connectors)

Introduction

Mainboard Overview - Bottom (Connectors)

Figure 9
Mainboard Bottom
Connectors

7

6
9
8

1

5

3

4

Mainboard Overview - Bottom (Connectors) 1 - 11

1.Introduction

2

1. Battery
Connector
2. CMOS Battery
Connector
3. Speaker Cable
Connector
4. CPU Fan Cable
Connector
5. RJ-45 LAN Jack
6. External Monitor
Port
7. DC-In Jack
8. LCD Cable
Connector
9. CCD Cable
Connector

Disassembly

Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the W170HN series notebook’s parts and subsystems.
When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.

To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a 
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also.


Information

A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar.


Warning

Overview 2 - 1

2.Disassembly

Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.

Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).

Maintenance Tools
The following tools are recommended when working on the notebook PC:

2.Disassembly

•
•
•
•
•
•

M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap

Connections
Connections within the computer are one of four types:

2 - 2 Overview

Locking collar sockets for ribbon connectors

To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.

Pressure sockets for multi-wire connectors

To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.

Pressure sockets for ribbon connectors

To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When replacing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.

Board-to-board or multi-pin sockets

To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.

Disassembly

Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions:

•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies.
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire.

6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.

Power Safety
Warning
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.

Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.

Overview 2 - 3

2.Disassembly

1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
components could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight.
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor
the position of magnetized tools (i.e. screwdrivers).
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly
damaged.
5. Be careful with power. Avoid accidental shocks, discharges or explosions.



Disassembly

Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.

To remove the Battery:
1. Remove the battery

page 2 - 5

To remove the HDD:

2.Disassembly

1. Remove the battery
2. Remove the HDD

page 2 - 5
page 2 - 6

To remove the Optical Device:
1. Remove the battery
2. Remove the Optical device

page 2 - 5
page 2 - 8

To remove the System Memory:
1. Remove the battery
2. Remove the system memory

page 2 - 5
page 2 - 9

To remove and install a Processor:
1. Remove the battery
2. Remove the processor
3. Install the processor

page 2 - 5
page 2 - 11
page 2 - 13

To remove the Wireless LAN Module:
1. Remove the battery
2. Remove the WLAN module

page 2 - 5
page 2 - 14

To remove the Keyboard:
1. Remove the battery
2. Remove the keyboard

2 - 4 Disassembly Steps

page 2 - 5
page 2 - 15

Disassembly

Removing the Battery
1.
2.
3.
4.

Figure 1
Battery Removal

Turn the computer off, and turn it over.
Slide the latch 1 in the direction of the arrow (Figure 1a).
Slide the latch 2 in the direction of the arrow, and hold it in place (Figure 1a).
Slide the battery 63 in the direction of the arrow 4 (Figure 1b).

a.

a. Slide the latch and hold it
in place.
b. Slide the battery in the direction of the arrow.

b.
2

1

3

2.Disassembly

4


3. Battery

Removing the Battery 2 - 5

Disassembly

Removing the Hard Disk Drive
Figure 2
HDD Assembly
Removal

2.Disassembly

a. Locate the HDD bay cover
and remove the screws.

The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
(h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Chapter 4 of the User’s Manual) when setting up a new hard disk.

Hard Disk Upgrade Process
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 (Figure 2a).



a.

HDD System Warning
New HDD’s are blank. Before you
begin make sure:
You have backed up any data
you want to keep from your old
HDD.

1


• 2 Screws

2 - 6 Removing the Hard Disk Drive

2

You have all the CD-ROMs and
FDDs required to install your operating system and programs.
If you have access to the internet,
download the latest application
and hardware driver updates for
the operating system you plan to
install. Copy these to a removable medium.

Disassembly
3.
4.
5.
6.
7.

Remove the hard disk bay cover 63 (Figure 3b).
Grip the tab and slide the hard disk in the direction of arrow 4 (Figure 3c).
Lift the hard disk assembly 65 out of the bay 6 (Figure 3d).
Remove the screw 7 - 10 and the mylar cover 11 from the hard disk 12 (Figure 3e).
Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b.

d.

6

Figure 3
HDD Assembly
Removal (cont’d.)
b. Remove the HDD bay
cover.
c. Grip the tab and slide the
HDD assembly in the direction of the arrow.
d. Lift the HDD assembly
out of the bay.
e. Remove the screws and
mylar cover.

2.Disassembly

3
5

e.

c.

7


10

8
4

11
12

9

3. HDD Bay Cover
5. HDD Assembly
11. Mylar Cover
12. HDD

• 4 Screws

Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4
Optical Device
Removal

1.
2.
3.
4.

Turn off the computer, remove the battery (page 2 - 5) and hard disk (page 2 - 6).
Remove the screw at point 1 (Figure 4a).
Use a screwdriver to carefully push out the optical device 3 at point 2 (Figure 4b).
Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
screw holes should line up).
5. Restart the computer to allow it to automatically detect the new device.
a.

b.

2.Disassembly

a. Remove the screw at
point 1 .
b. Use a screwdriver to
carefully push out the
optical device at point
2 .

Removing the Optical (CD/DVD) Device

3

1

2

2


3. Optical Device

• 1 Screw

2 - 8 Removing the Optical (CD/DVD) Device

Disassembly

Removing the System Memory (RAM)

Figure 5

The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
DDRIII (DDR3) Up to 1333/1600MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1024MB and 2048MB DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your computer.

Memory Upgrade Process
1. Turn off the computer, turn it over and remove the battery (page 2 - 5).
2. Remove screws 1 - 4 from the component bay cover (Figure 5a).
3. The RAM modules will be visible at point 5 on the mainboard (Figure 5b).

a. Remove the screws
from the component
bay cover.
b. The RAM modules will
be visible at point 5
on the mainboard.
c. Pull the release latches.
d. Remove the module.

b.
1



2

Contact Warning

3

5
4

Be careful not to touch
the metal pins on the
module’s
connecting
edge. Even the cleanest
hands have oils which
can attract particles, and
degrade the module’s
performance.


• 4 Screw

Removing the System Memory (RAM) 2 - 9

2.Disassembly

a.

RAM Module
Removal

Disassembly
Figure 6
RAM Module
Removal (cont’d)
c. Pull the release latches.
d. Remove the module.

4. Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the
arrows (Figure 5c). The RAM module 8 will pop-up (Figure 6d), and you can then remove it.
5. Pull the latches to release the second module if necessary.
c.

d.

6

7

2.Disassembly

8


Contact Warning
Be careful not to touch
the metal pins on the
module’s
connecting
edge. Even the cleanest hands have oils
which can attract particles, and degrade the
module’s performance.

6. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
7. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot
as it will go. DO NOT FORCE IT; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
9. Replace the component bay cover and the screws (see page 2 - 9).
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.


8. RAM Module

2 - 10 Removing the System Memory (RAM)

Disassembly

Removing and Installing a Processor

Figure 7
Processor Removal

Processor Removal Procedure
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
2. The CPU heat sink will be visible at point A (Figure 7a) on the mainboard.
3. Remove screws 3 , 2 , 1 , the reverse order indicated on the label (Figure 7b).

a. Remove the cover and
Iocate the heat sink.
b. Remove the screws in
the order indicated.

b.

a.

1

2.Disassembly

A
3

2


•

3 Screws

Removing and Installing a Processor 2 - 11

Disassembly

Figure 8
Processor Removal
(cont’d)

2.Disassembly

c. Remove the heat sink.
d. Turn the release latch to
unlock the CPU.
e. Lift the CPU out of the
socket.

4.
5.
6.
7.
8.

Carefully lift up the heat sink B (Figure 8c) off the computer.
Turn the release latch C towards the unlock symbol
, to release the CPU (Figure 8d).
Carefully (it may be hot) lift the CPU D up out of the socket (Figure 8e).
See page 2 - 13 for information on inserting a new CPU.
When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).

c.

e.

D

B


Caution
The heat sink, and CPU
area in general, contains
parts which are subject to
high temperatures. Allow
the area time to cool before removing these parts.

d.

C


B. Heat Sink
D. CPU

Unlock

2 - 12 Removing and Installing a Processor

Disassembly

Processor Installation Procedure

Figure 9

1. Insert the CPU A (Figure 9a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE
IT!), and turn the release latch B towards the lock symbol
(Figure 9b).
2. Remove the sticker C (Figure 9c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 9d.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 9d).
5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws (page 2 - 9).
a.

c.

Processor
Installation
a. Insert the CPU.
b. Turn the release latch towards the lock symbol.
c. Remove the sticker from
the heat sink and insert
the heat sink.
d. Tighten the screws.

C

A

2.Disassembly

d.

b.

1

D

B
3

lock

2

Note:
Tighten the screws
in the order as indicated on the label.


A. CPU
D. Heat Sink

• 3 Screws

Removing and Installing a Processor 2 - 13

Disassembly
Figure 10
Wireless LAN
Module Removal

2.Disassembly

a. Locate the WLAN.
b. Disconnect the cables
and remove the screw.
c. The WLAN module will
pop up.
d. Remove the Wireless
LAN module.

Removing the Wireless LAN Module
1.
2.
3.
4.

Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a).
Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b).
The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer (Figure 10d).
c.

a.

Note: Make sure you
reconnect the antenna
cable to the “1 + 2”
socket (Figure 10b).

d.

5

1

b.
2


5.Wireless LAN Module

• 1 Screw

2 - 14 Removing the Wireless LAN Module

3

5
4

Disassembly

Removing the Keyboard

Figure 11

1. Turn off the computer and remove the battery (page 2 - 5).
2. Remove the screws 1 - 2 and use a screwdriver to carefully push out the top cover module at point 3 (Figure
11a).
3. Remove the top cover module 4 (Figure 11b) and the screws 5 - 9 (Figure 11c).
4. Carefully lift the keyboard 10 up, being careful not to bend the keyboard ribbon cable (Figure 11d).
5. Disconnect the keyboard ribbon cable 11 from the locking collar socket 12 (Figure 11d).
6. Carefully lift up the keyboard 10 (Figure 11e) off the computer.
a.

d.
1

3

11

2

Keyboard Removal
a. Remove the screws and
use a screwdriver to carefully push out the top cover
module at point 3 .
b. Remove the top cover
module.
c. Remove the screws.
d. Lift the keyboard up and
disconnect the cable from
the locking collar.
e. Remove the keyboard.

2.Disassembly

10
12

b.

44

e.


4. Top cover module
10. Keyboard

c.

5

6

7

8

9
• 7 Screws

10

Removing the Keyboard 2 - 15

2.Disassembly

Disassembly

2 - 16

Appendix A:Part Lists
This appendix breaks down the W170HN series notebook’s construction into a series of illustrations. The component
part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.

A.Part Lists

Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.

A - 1

Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1

A.Part Lists

Part List Illustration
Location

A - 2

Part

W170HN

Top

page A - 3

Bottom

page A - 4

LCD

page A - 5

Combo

page A - 6

DVD

page A - 7

HDD

page A - 8

Top

Top

非耐落

黑色

灰色

Top A - 3

A.Part Lists

Figure A - 1

A.Part Lists

Bottom

Figure 2
Bottom

A - 4 Bottom

LCD

Figure A - 3

LCD A - 5

A.Part Lists

LCD

SATA BLU-RAY Combo

A.Part Lists

Figure A - 4
SATA BLU-RAY
Combo

(非耐落)

A - 6 SATA BLU-RAY Combo

SATA DVD

Figure A - 5

(非耐落)

SATA DVD A - 7

A.Part Lists

SATA DVD

HDD

A.Part Lists

Figure A - 6
HDD

A - 8 HDD

Schematic Diagrams

Appendix B: Schematic Diagrams
This appendix has circuit diagrams of the W170HN notebook’s PCB’s. The following table indicates where to find the
appropriate schematic diagram.
Diagram - Page

Diagram - Page

Diagram - Page

CougarPoint - M 1/9 - Page B - 19

5VS, 3VS, 3.3VM, 1.5VS_CPU - Page B - 36

CPU 1/7 (DMI, PEG, FDI) - Page B - 3

CougarPoint - M 2/9 - Page B - 20

VDD3, VDD5 - Page B - 37

CPU 2/7 (CLK, MISC, JTAG) - Page B - 4

CougarPoint - M 3/9 - Page B - 21

Power 0.85VS, 1.8VS, PEX_VDD - Page B 38

CPU 3/7 (DDR3) - Page B - 5

CougarPoint - M 4/9 - Page B - 22

Power 1.5V/1.05VS/0.75V - Page B - 39

CPU 4/7 (Power) - Page B - 6

CougarPoint - M 5/9 - Page B - 23

Power V-Core1 - Page B - 40

CPU 5/7 (Graphics Power) - Page B - 7

CougarPoint - M 6/9 - Page B - 24

Power V-Core2 - Page B - 41

CPU 6/7 (GND) - Page B - 8

CougarPoint - M 7/9 - Page B - 25

Power VGA NVVDD - Page B - 42

CPU 7/7 (RESERVED) - Page B - 9

CougarPoint - M 8/9 - Page B - 26

AC_IN, Charger - Page B - 43

DDR3 SO-DIMM_0 - Page B - 10

CougarPoint - M 9/9 - Page B - 27

W150HNM Audio Board - Page B - 44

DDR3 SO-DIMM_1 - Page B - 11

WLAN, 3G, Mini PCIE - Page B - 28

W150HNM Second HDD Board - Page B - 45

Panel, Inverter, CRT - Page B - 12

USB, Fan, TP, FP, Multi-Conn - Page B - 29

B5100 Click Board - Page B - 46

VGA PCI-E Interface - Page B - 13

USB 3.0 - Page B - 30

B5100 Fingerprint Board - Page B - 47

VGA Frame Buffer Interface - Page B - 14

Card Reader (JMC251C) - Page B - 31

B5100 LED & VGA SW Board - Page B - 48

VGA Frame Buffer A - Page B - 15

SATA ODD, LED, Hotkey, LID SW - Page B - 32

B5100 Power Switch Board - Page B - 49

VGA Frame Buffer C - Page B - 16

HDMI, RJ45 - Page B - 33

Sequence - Page B - 50

VGA I/O - Page B - 17

Audio Codec ALC269 - Page B - 34

VGA NVVDD Cecoupling - Page B - 18

KBC-ITE IT8518E - Page B - 35

Table B - 1
SCHEMATIC
DIAGRAMS


Version Note
The schematic diagrams in this chapter
are based upon version 6-7P-W1507-002.
If your mainboard (or
other boards) are a later version, please
check with the Service
Center for updated diagrams (if required).

B - 1

B.Schematic Diagrams

System Block Diagram - Page B - 2

Schematic Diagrams

System Block Diagram
VDD3,VDD5

W150HNM/W170HN Huron River System Block Diagram

6-71-W1500-D02

GPU NVDIDA N12x NVVDD
PCIE*8

AUDIO BOARD

5V,3V,5VS,3VS,1.5VS,
1.8VS,+1.5S_CPU
1.8V, PEX_VDD,0.85VS

B.Schematic Diagrams

1.5V,0.75VS(VTT_MEM)
FBVDDQ

Nvidia
Fermi N12P
RAM SIZE:1~2GB
(64MX16)
969 Balls

0.1"~13

DMI*4
<=8"

CougarPoint
Controller
Hub (PCH)

MIC
IN

HP
OUT

USB PORT (USB8)

33 MHz

W170HN 8IN1 6-7P-W1708-001
W150HN MAIN BOARD

BIOS
SPI

24 MHz

THERMAL
SENSOR
W83L771AWG

SMART
FAN

SMART
BATTERY
AC-IN

PCIE

6-71-W170N-D01

USB2.0

<12"

1"~16"

6-71-B7117-D01

AZALIA LINK
100 MHz

W150HNM
SECOND HDD BOARD

USB PORT1
(USB0)

25
MHz

<12"

6-71-B7112-D02

POWER SWITCH BOARD

USB3.0
NEC uPD720200
VLI8012

Mini PCIE
Mini PCIE
SOCKET
SOCKET
WLAN
3G MSATA CARD
(USB2/SATA3)
(USB2)

B5100

eSATA

K/B TRANSFER BOARD

6-71-B711S-D02
32.768KHz

480 Mbps

(B4100M)

PHONE JACK x3, USB x1
RJ-11 6-71-W170A-D01

CLICK BOARD

SATA I/II 3.0Gb/s

SATA ODD

AUDIO BOARD

SECOND HDD/ODD BOARD

EC SMBUS

INT. K/B

B - 2 System Block Diagram

W150HNM
INT SPKER-L

Azalia Codec
REALTAK
ALC269

INT MIC

14 *1 4*1 .6m m

6-71-B510S-D03

LED & VGA S/W BOARD

6-71-W1500-D01

27x27mm
989 Ball FCBGA

LPC

6-71-B5102-D04

6-71-B5134-D01

W150HNM (INT SPK R)

32.768 KHz

SATA HDD

CLICK BOARD
POWER SWITCH BOARD

TPM 1.2
Optional

0.5"~11"

DDRIII
SO-DIMM1

W150HNM
INT SPKER-R

SPI

128pins LQFP

FINGER PRINTER BOARD

AUDIO BOARD
SPDIF
OUT

HDMI Connector

EC
ITE 8518E

6-71-W150N-D02

DDRIII
SO-DIMM2

6-71-B510F-D02

SYSTEM SMBUS

<8"
<15"

LCD CONNECTOR
CRT CONNECTOR

SECOND HDD/ODD BOARD

rPGA988B

0.5"~5.5"

SENTELIC
6-49-C4
102-010
TOUCH
PAD
CLICK BOARD

800/1067/1333 MHz
DDR3 / 1.5V

PROCESSOR

FDI

Sheet 1 of 49
System Block
Diagram

PHONE JACK x3, USB x1
RJ-11 6-71-W150A-D02

Sandy Bridge

1.05VS_VTT
VGFX_CORE

W150HNM 7IN1 6-7P-W1507-001
W150HNM MAIN BOARD

CCD
(USB5)

JMC251_C
CARD
LAN READER

RJ-45

FINGER PRINTER BOARD

(USB4)
FingerPrint
(Optional)

JMICRO

USB PORT2

USB PORT3

12 MHz

USB3.0

7IN1
SOCKET

LED & VGA S/W BOARD
6-71-B7134-D01

DEBUG BOARD
6-71-W840TD-D03

Schematic Diagrams

CPU 1/7 (DMI, PEG, FDI)
Sandy Bridge Processor 1/7 ( DMI,PEG,FDI )
1 . 0 5V S _ V T T

CPU

U 49A

I _T X N
I _T X N
I _T X N
I _T X N

20
20
20
20

D
D
D
D

M
M
M
M

I _T X P 0
I _T X P 1
I _T X P 2
I _T X P 3

20
20
20
20

D MI _ R X N 0
D MI _ R X N 1
D MI _ R X N 2
D MI _ R X N 3

20
20
20
20

D
D
D
D

MI _ R
MI _ R
MI _ R
MI _ R

B2 7
B2 5
A2 5
B2 4

0
1
2
3

B2 8
B2 6
A2 4
B2 3
G2 1
E2 2
F21
D2 1
G2 2
D2 2
F20
C2 1

XP0
XP1
XP2
XP3

20
20
20
20
20
20
20
20

FD
FD
FD
FD
FD
FD
FD
FD

I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN

0
1
2
3
4
5
6
7

20
20
20
20
20
20
20
20

FD
FD
FD
FD
FD
FD
FD
FD

I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP

0
1
2
3
4
5
6
7

A2 1
H1 9
E1 9
F18
B2 1
C2 0
D1 8
E1 7
A2 2
G1 9
E2 0
G1 8
B2 0
C1 9
D1 9
F17
J18
J17

1. 05 V S _V TT
20
20

F DI_ F S Y N C0
F DI_ F S Y N C1

20

F DI_ IN T

20
20

F DI_ L S Y NC 0
F DI_ L S Y NC 1

D
D
D
D

MI _ R
MI _ R
MI _ R
MI _ R

X #[
X #[
X #[
X #[

D
D
D
D

MI _ R
MI _ R
MI _ R
MI _ R

X [0 ]
X [1 ]
X [2 ]
X [3 ]

D
D
D
D

MI _ T X # [ 0 ]
MI _ T X # [ 1 ]
MI _ T X # [ 2 ]
MI _ T X # [ 3 ]

P E G_ I C OM P I
P E G _ I C O MP O
P E G_ R C O MP O

0]
1]
2]
3]

DMI

M
M
M
M

D MI _ T X [ 0 ]
D MI _ T X [ 1 ]
D MI _ T X [ 2 ]
D MI _ T X [ 3 ]

FD
FD
FD
FD
FD
FD
FD
FD

I 0 _ T X# [ 0 ]
I 0 _ T X# [ 1 ]
I 0 _ T X# [ 2 ]
I 0 _ T X# [ 3 ]
I 1 _ T X# [ 0 ]
I 1 _ T X# [ 1 ]
I 1 _ T X# [ 2 ]
I 1 _ T X# [ 3 ]

FD
FD
FD
FD
FD
FD
FD
FD

I 0 _ T X[ 0 ]
I 0 _ T X[ 1 ]
I 0 _ T X[ 2 ]
I 0 _ T X[ 3 ]
I 1 _ T X[ 0 ]
I 1 _ T X[ 1 ]
I 1 _ T X[ 2 ]
I 1 _ T X[ 3 ]

F D I0 _ F S Y NC
F D I1 _ F S Y NC

H2 0

R 5 21
1 K _ 1 % _ 04

R5 1 9
24 . 9 _ 1 % _0 4

F D I_ IN T
J19
H1 7

F D I0 _ L SYN C
F D I1 _ L SYN C

ED P F unc ti on Di sa ble
ED P_ HP D: Pu ll -u p1 0K - DIS AB LE D

Q 44
*M T N 7 0 0 2 Z H S 3

G
S

1 1 EM B_ HP D

A1 8
A1 7
B1 6

D

11/1

E D P _ HP D

11
11

D P _ A UX P
D P _ A UX N

C 1 97
C 2 14

* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4

D P _ A UX _ P
D P _ A UX _ N

C1 5
D1 5

C 1 78
C 1 96
C 1 82

* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4

D P _ TX P _ 0
D P _ TX P _ 1
D P _ TX P _ 2

C1 7
F16
C1 6
G1 5

C 1 67
C 1 86
C 1 79

* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4

D P _ TX N _ 0
D P _ TX N _ 1
D P _ TX N _ 2

C1 8
E1 6
D1 6
F15

e D P _ C O MP I O
e D P _ I C O MP O
e D P _ HP D

e D P _ AUX
e D P _ AUX#

R5 2 0
*1 0 0 K _ 04

11
11
11

D P _ T XP 0
D P _ T XP 1
D P _ T XP 2

11
11
11

D P _ T XN 0
D P _ T XN 1
D P _ T XN 2

11/1

eD
eD
eD
eD

P _ TX [ 0 ]
P _ TX [ 1 ]
P _ TX [ 2 ]
P _ TX [ 3 ]

eD
eD
eD
eD

P _ TX # [ 0 ]
P _ TX # [ 1 ]
P _ TX # [ 2 ]
P _ TX # [ 3 ]

P Z 9 88 2 7 -3 6 4B -0 1F

eDP

E D P _ C O MP I O

DP Compensation Signal

PCI EXPRESS* - GRAPHICS

1 .0 5 VS _ V T T

D
D
D
D

P E G_ R X # [ 0 ]
P E G_ R X # [ 1 ]
P E G_ R X # [ 2 ]
P E G_ R X # [ 3 ]
P E G_ R X # [ 4 ]
P E G_ R X # [ 5 ]
P E G_ R X # [ 6 ]
P E G_ R X # [ 7 ]
P E G_ R X # [ 8 ]
P E G_ R X # [ 9 ]
P E G_ R X# [ 1 0 ]
P E G_ R X# [ 1 1 ]
P E G_ R X# [ 1 2 ]
P E G_ R X# [ 1 3 ]
P E G_ R X# [ 1 4 ]
P E G_ R X# [ 1 5 ]
P E G _ RX [0 ]
P E G _ RX [1 ]
P E G _ RX [2 ]
P E G _ RX [3 ]
P E G _ RX [4 ]
P E G _ RX [5 ]
P E G _ RX [6 ]
P E G _ RX [7 ]
P E G _ RX [8 ]
P E G _ RX [9 ]
P E G_ R X [ 1 0 ]
P E G_ R X [ 1 1 ]
P E G_ R X [ 1 2 ]
P E G_ R X [ 1 3 ]
P E G_ R X [ 1 4 ]
P E G_ R X [ 1 5 ]
P E G _ TX # [ 0 ]
P E G _ TX # [ 1 ]
P E G _ TX # [ 2 ]
P E G _ TX # [ 3 ]
P E G _ TX # [ 4 ]
P E G _ TX # [ 5 ]
P E G _ TX # [ 6 ]
P E G _ TX # [ 7 ]
P E G _ TX # [ 8 ]
P E G _ TX # [ 9 ]
P E G _ T X# [ 1 0 ]
P E G _ T X# [ 1 1 ]
P E G _ T X# [ 1 2 ]
P E G _ T X# [ 1 3 ]
P E G _ T X# [ 1 4 ]
P E G _ T X# [ 1 5 ]
P E G _T X [ 0 ]
P E G _T X [ 1 ]
P E G _T X [ 2 ]
P E G _T X [ 3 ]
P E G _T X [ 4 ]
P E G _T X [ 5 ]
P E G _T X [ 6 ]
P E G _T X [ 7 ]
P E G _T X [ 8 ]
P E G _T X [ 9 ]
P E G _ TX [ 1 0 ]
P E G _ TX [ 1 1 ]
P E G _ TX [ 1 2 ]
P E G _ TX [ 1 3 ]
P E G _ TX [ 1 4 ]
P E G _ TX [ 1 5 ]

K 33
M 35
L34
J35
J32
H 34
H 31
G 33
G 30
F 35
E 34
E 32
D 33
D 31
B 33
C 32

P E G _ I R C OM P _ R

P
P
P
P
P
P
P
P

E G_ R
E G_ R
E G_ R
E G_ R
E G_ R
E G_ R
E G_ R
E G_ R

X #0
X #1
X #2
X #3
X #4
X #5
X #6
X #7

R1 3 3

2 4 . 9 _ 1 %_ 0 4

12
12
12
12
12
12
12
12

PEG Compensation Signal

J33
L35
K 34
H 35
H 32
G 34
G 31
F 33
F 30
E 35
E 33
F 32
D 34
E 31
C 33
B 32

P
P
P
P
P
P
P
P

E G_ R
E G_ R
E G_ R
E G_ R
E G_ R
E G_ R
E G_ R
E G_ R

X0
X1
X2
X3
X4
X5
X6
X7

CAD NOTE: PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
- typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with
- max length = 500 mils
- typical impedance = 14.5 mohms

12
12
12
12
12
12
12
12

M 29
M 32
M 31
L32
L29
K 31
K 28
J30
J28
H 29
G 27
E 29
F 27
D 28
F 26
E 25

PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG

_T X # _ 0
_T X # _ 1
_T X # _ 2
_T X # _ 3
_T X # _ 4
_T X # _ 5
_T X # _ 6
_T X # _ 7

C5 9 1
C5 8 9
C5 9 4
C5 9 6
C5 9 8
C6 0 1
C6 0 6
C6 0 8

0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R

_04
_04
_04
_04
_04
_04
_04
_04

M 28
M 33
M 30
L31
L28
K 30
K 27
J29
J27
H 28
G 28
E 28
F 28
D 27
E 26
D 25

PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG

_T X _ 0
_T X _ 1
_T X _ 2
_T X _ 3
_T X _ 4
_T X _ 5
_T X _ 6
_T X _ 7

C5 8 7
C5 8 8
C5 9 3
C5 9 5
C5 9 7
C6 0 2
C6 0 4
C6 0 7

0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R
0 . 2 2u _ 1 0 V _ X 5R

_04
_04
_04
_04
_04
_04
_04
_04

P
P
P
P
P
P
P
P

E G_ T X # 0
E G_ T X # 1
E G_ T X # 2
E G_ T X # 3
E G_ T X # 4
E G_ T X # 5
E G_ T X # 6
E G_ T X # 7

P
P
P
P
P
P
P
P

E G_ T X 0
E G_ T X 1
E G_ T X 2
E G_ T X 3
E G_ T X 4
E G_ T X 5
E G_ T X 6
E G_ T X 7

12
12
12
12
12
12
12
12

12
12
12
12
12
12
12
12

Q 26
5
G ND

N C
GN D

VC C

VO

4
3 .3 V

Sheet 2 of 49
CPU 1/7
(DMI, PEG, FDI)

SC70-5 & SC70-3
Co-lay

1
2
3

* T MP 2 0
Q 27
2

1
VC C

OU T

1:2 (4mils:8mils)

C 67 3
C6 7 2

3

T H E R M _V OL T 3 4

8/30

G ND
0 . 1 u _1 0 V _ X 7 R _ 0 4

G 7 11 S T 9 U

0 . 1 u_ 1 0 V _ X 7 R _ 0 4

1
3

PLACE NEAR U3

2

3, 5 , 2 3 , 2 4 , 2 5, 35 , 3 9 1 . 0 5 V S _ V T T
3 , 8 , 1 1 , 12 , 1 6 , 1 8 , 1 9 , 20 , 2 2 , 2 3 , 2 4, 25 , 2 7 , 2 8 , 2 9, 30 , 3 3 , 3 5 , 3 7, 38 , 3 9 3 . 3 V

CPU 1/7 (DMI, PEG, FDI) B - 3

B.Schematic Diagrams

CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with
- typical impedance < 25 mohms

20
20
20
20

Int el(R) FDI

H1 6
H1 5
H 8
H 8 _ 0 D 4 _ 4 H 8 _ 0 D 4_ 4 H 8 _0 D 4 _4

20 mil

J22
J21
H 22

Schematic Diagrams

CPU 2/7 (CLK, MISC, JTAG)
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )

Processor Pullups/Pull downs

PU/PD for JTAG signals

1 .0 5 VS _ VT T

1 . 05 V S _ V T T
H _ P R O C H OT #
X D P _ T MS
X DP _ T DI_ R
X D P _ P RE Q #
X D P _ TD O_ R
X D P _T C LK
X D P _ TR S T #

U 4 9B

AN3 4

XD P _ D B R _R
A L3 3

H_ P E C I

R 10 9

39 H _ P R O C H OT #

*1 0 m il _ s ho rt

5 6_ 1 % _0 4

H_ P E C I_ R A N3 3

H _ P R O C H OT # _ D

PEC I

A L3 2

P R OC H O T#

If PROCHOT# is not used, then it must be terminated
with a 56-O +-5% pull-up resistor to 1.05VS_VTT A .
N3 2

Sheet 3 of 49
CPU 2/7
(CLK, MISC, JTAG)

T H E R MT R I P #
R4 9 6

2 3 H _ T H R MT R I P #

A2 8
A2 7

S M _ R C OM P [ 0 ]
S M _ R C OM P [ 1 ]
S M _ R C OM P [ 2 ]

CL K _ DP _ P 1 9
CL K _ DP _ N 1 9

R8

C P UD RA M RS T #

AK1
A5
A4

S M _ R C OMP _0
S M _ R C OMP _1
S M _ R C OMP _2

AP2 9
AP2 7

X D P _P R D Y #
X D P _P R E Q #

A R2 6
A R2 7
AP3 0

X D P _T C LK
X D P _T M S
X D P _T R S T#

A R2 8
AP2 6

X D P _T D I _R
X D P _T D O_ R

AL 3 5

X D P _D B R _ R

H _ T H R MT R I P #_ R

*1 0 m li _ sh o rt

DDR3 Compensation Signals

3 .3 V

R1 7 4

V8

U N C OR E P W R G OO D

S M _D R A MP W R OK

AR3 3
R ESET #

7 5_ 0 4
R 6 58

3

# [0 ]
# [1 ]
# [2 ]
# [3 ]
# [4 ]
# [5 ]
# [6 ]
# [7 ]

AT2 8
A R2 9
A R3 0
AT3 0
AP3 2
A R3 1
AT3 1
A R3 2

X DP
X DP
X DP
X DP
X DP
X DP
X DP
X DP

_B P
_B P
_B P
_B P
_B P
_B P
_B P
_B P

M0 _ R
M1 _ R
M2 _ R
M3 _ R
M4 _ R
M5 _ R
M6 _ R
M7 _ R

4
2

3 8 1. 5S _ C P U _ P W R GD
U1 4

* 39 _ 0 4

G
3 5 , 3 7, 38 S U S B

* MT N 7 0 0 2Z H S 3

D

MT N 70 0 2 Z H S 3
S

1

3 4 H _ P R OC H O T# _ E C

R 5 18

Q1 6

C6 2 2
47 p _ 5 0V _ N P O_ 0 4

* 1 . 5K _1 % _ 04

C 6 21
6 8 p _5 0 V _ N P O _ 04

S3 circuit:- DRAM_RST# to memory
should be high during S3
1 . 5V

1 0 0K _0 4

R 5 17

R 23 1
R 2 00

*0 _ 0 4

R2 3 0
1 K _0 4

3 . 3V
3 .3 V

1 .5 VS_ CPU

*0 _ 0 4

CAD Note: Capacitor need to be placed
close to buffer output pin

C P U D R A MR S T #

Q1 7
MT N 7 0 0 2 Z H S 3
S
D

1 K _ 04
R2 3 5

3 .3 V

D D R 3_ D R A M R S T # 9 , 10

R2 2 5
* 0. 1u _ 1 6V _ Y 5V _0 4
R 15 7

* 1 0K _0 4
1 . 5S _C P U _ P W R GD
D

* 10 K _ 0 4

Q 12

38

5

R 16 6

U 11
* MC 74 V H C 1 G0 8 D F T1 G

*1 . 1 K _ 1 % _0 4

1
37 1 . 0 5 V S _ V TT _ P W R GD

3 . 3V _E N _ D G

4

DR A M P W RG D_ CP U

R1 5 2

* 1 . 5K _ 1 % _ 04

V D D P W R G OO D _ R

2

Q 11

3

S

C

* MT N 70 0 2 Z H S 3
R 15 8
*3 K _ 1 % _0 4
* 2N 3 90 4

B - 4 CPU 2/7 (CLK, MISC, JTAG)

6 , 8, 9 , 1 0 , 2 5, 2 9 , 3 3 , 35 , 3 7 , 3 8 1 . 5 V
6 ,3 5 1 .5 V S _ C P U
2 , 5 , 2 3 , 24 , 2 5 , 3 5, 3 9 1 . 0 5 V S _ V TT
2 , 8 , 1 1 , 12 , 1 6 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 4, 2 5 , 2 7 , 28 , 2 9 , 3 0, 3 3 , 3 5 , 37 , 3 8 , 3 9 3 . 3 V
6 , 9 , 1 0, 1 1 , 1 2 , 18 , 1 9 , 2 0, 2 1 , 2 2 , 23 , 2 4 , 2 5, 2 7 , 2 8, 29 , 3 0 , 31 , 3 2 , 3 3, 3 4 , 3 5 , 39 3 . 3 V S

D RA M RS T _ CN T RL 8 ,1 9

G

C 26 8

4 . 99 K _ 1 % _0 4

R 1 65

E

Q 13

H _ P R O C H OT #

* 75 0 _ 1 %_ 0 4

B

R 16 8

*M C 7 4 V H C 1G 0 8D F T 1 G
R1 8 6
0_04

G
R 20 3

1 .5 V S _ CP U

P MS Y S _ P W R G D _ B U F

4

6

BPM
BPM
BPM
BPM
BPM
BPM
BPM
BPM

R 17 5
2 0 0 _1 % _ 04

1

2 0 P M_ D R A M _P W R G D

Q 3 7B
D MN 60 1 D W K -7

Q3 7 A
D M N 6 0 1D W K -7

R5 2 4
1 0 0K _0 4

DB R #

1 .5 V S _ CP U

P Z 98 8 2 7-3 6 4 B -0 1F

S

S

R 18 8

S

D

5G
D

2G

TD I
T DO

C 2 78
R 18 7

B U F _C P U _ R S T#
43 . 2 _ 1% _ 0 4

R5 1 5

1 2 , 2 2, 2 8 P L T _ R S T #

T CK
T MS
TR S T #

*1 0 0K _0 4

V D D P W R G OO D _ R

R5 1 2

1 0K _0 4

20 0 _ 1 %_ 0 4

5

H _ C P U P W R GD _R

1 30 _ 1 %_ 0 4

B U F _ C P U _R S T #
3 .3 V S

25 . 5 _ 1 %_ 0 4

S M _R C O MP _ 2 R 5 2 9

3 .3 V

*2 0 0 _ 04

*1 0 m li _ sh o rt

AP3 3

P M _S Y N C

1 . 0 5V S _V T T

Buffered reset to CPU

14 0 _ 1 %_ 0 4

S M _R C O MP _ 1 R 5 2 8

D

P M S Y S _P W R G D _ B U F

A M3 4

JTAG & BPM

R4 9 8

2 3 H _ C P U P W R GD

H _ P M_ S Y N C _ R

*1 0 m li _ sh o rt

PWR MANAGEMENT

R4 9 5

S M _R C O MP _ 0 R 5 3 1

S3 circuit:- DRAM PWR GOOD logic
P R DY #
P RE Q #

2 0 H _ P M _S Y N C

R4 9 9

CL K _ E X P _ P 1 9
CL K _ E X P _ N 1 9

A1 6
A1 5

S M_ D R A MR S T #

1 0 K_ 0 4

*0 . 1 u_ 1 6 V _ Y 5V _0 4

2 3 ,3 4

R4 9 7

C A TE R R #

D P L L _ R E F _ S S C LK
DP L L _ RE F _ S S C L K #

R1 1 0

TRACE WIDTH 10MIL, LENGTH <500MILS

3

H_ CA T E R R#

B.Schematic Diagrams

SKT O CC #

DDR3
MISC

1 K _ 04

CLOCKS

P R OC _S E LE C T #

3 .3 VS

R4 9 4

B C LK
BC L K#

C2 6

H _ S N B _I V B #

2 3 H _ S N B _I V B #

H _ CP U P W RG D_ R

MISC

R5 1 0
R5 0 6
R5 0 8
R5 1 1
R5 1 3
R5 0 5

THERMAL

5 1_ 0 4
5 1_ 0 4
* 5 1_ 0 4
5 1_ 0 4
5 1_ 0 4
5 1_ 0 4

6 2_ 0 4

C3 1 5
0 . 04 7 u _ 10 V _ X 7R _ 04

Schematic Diagrams

CPU 3/7 (DDR3)
Sandy Bridge Processor 3/7 ( DDR3 )
U49C

9
9
9

M_A_BS0
M_A_BS1
M_A_BS2

9
9
9

M_A_CAS#
M_A_RAS#
M_A_WE#

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M
8
N10
N8
N7
M10
M
9
N9
M
7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10
V6

AE8
AD9
AF9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

PZ98827-364B-01F

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]

SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_M
A[0]
SA_M
A[1]
SA_M
A[2]
SA_M
A[3]
SA_M
A[4]
SA_M
A[5]
SA_M
A[6]
SA_M
A[7]
SA_M
A[8]
SA_M
A[9]
SA_M
A[10]
SA_M
A[11]
SA_M
A[12]
SA_M
A[13]
SA_M
A[14]
SA_M
A[15]

AB6
AA6
V9

M
_A_CLK_DDR0 9
M
_A_CLK_DDR#0 9
M
_A_CKE0 9

AA5
AB5
V10

10 M_B_DQ[ 63: 0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M
_A_CLK_DDR1 9
M
_A_CLK_DDR#1 9
M
_A_CKE1 9

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

M
_A_CS#0 9
M
_A_CS#1 9

AH3
AG3
AG2
AH2

M
_A_ODT0 9
M
_A_ODT1 9

C4
G6
J3
M6
AL6
AM
8
AR12
AM
15

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

D4
F6
K3
N6
AL5
AM
9
AR11
AM
14

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQS#[7:0] 9

M_A_DQS[7:0] 9

M_A_A[15:0] 9

10
10
10

M_B_BS0
M_B_BS1
M_B_BS2

10
10
10

M_B_CAS#
M_B_RAS#
M_B_WE#

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7
R6

AA10
AB8
AB9

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_CLK[ 0]
SB_CLK#[ 0]
SB_CKE[ 0]

SB_CLK[ 1]
SB_CLK#[ 1]
SB_CKE[ 1]

SB_CLK[ 2]
SB_CLK#[ 2]
SB_CKE[ 2]

SB_CLK[ 3]
SB_CLK#[ 3]
SB_CKE[ 3]

SB_CS#[ 0]
SB_CS#[ 1]
SB_CS#[ 2]
SB_CS#[ 3]

SB_ODT[ 0]
SB_ODT[ 1]
SB_ODT[ 2]
SB_ODT[ 3]

SB_DQS#[ 0]
SB_DQS#[ 1]
SB_DQS#[ 2]
SB_DQS#[ 3]
SB_DQS#[ 4]
SB_DQS#[ 5]
SB_DQS#[ 6]
SB_DQS#[ 7]

SB_DQS[ 0]
SB_DQS[ 1]
SB_DQS[ 2]
SB_DQS[ 3]
SB_DQS[ 4]
SB_DQS[ 5]
SB_DQS[ 6]
SB_DQS[ 7]

SB_MA[ 0]
SB_MA[ 1]
SB_MA[ 2]
SB_MA[ 3]
SB_MA[ 4]
SB_MA[ 5]
SB_MA[ 6]
SB_MA[ 7]
SB_MA[ 8]
SB_MA[ 9]
SB_MA[ 10]
SB_MA[ 11]
SB_MA[ 12]
SB_MA[ 13]
SB_MA[ 14]
SB_MA[ 15]

AE2
AD2
R9

M_B_CLK_DDR2 10
M_B_CLK_DDR#2 10
M_B_CKE2 10

AE1
AD1
R10

M_B_CLK_DDR3 10
M_B_CLK_DDR#3 10
M_B_CKE3 10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

M_B_CS#2 10
M_B_CS#3 10

AE4
AD4
AD5
AE5

Sheet 4 of 49
CPU 3/7
(DDR3)

M_B_ODT2 10
M_B_ODT3 10

D7
F3
K6
N3
AN5
AP9
AK12
AP15

M
_B_DQS#0
M
_B_DQS#1
M
_B_DQS#2
M
_B_DQS#3
M
_B_DQS#4
M
_B_DQS#5
M
_B_DQS#6
M
_B_DQS#7

C7
G3
J6
M3
AN6
AP8
AK11
AP14

M
_B_DQS0
M
_B_DQS1
M
_B_DQS2
M
_B_DQS3
M
_B_DQS4
M
_B_DQS5
M
_B_DQS6
M
_B_DQS7

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M
_B_A0
M
_B_A1
M
_B_A2
M
_B_A3
M
_B_A4
M
_B_A5
M
_B_A6
M
_B_A7
M
_B_A8
M
_B_A9
M
_B_A10
M
_B_A11
M
_B_A12
M
_B_A13
M
_B_A14
M
_B_A15

M
_B_DQS#[7:0] 10

M
_B_DQS[7: 0] 10

M_B_A[15:0] 10

PZ98827-364B-01F

CPU 3/7 (DDR3) B - 5

B.Schematic Diagrams

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DDR SYSTEM MEMORY B

M_A_DQ[63:0]

DDR SYSTEM MEMORY A

9

U49D

Schematic Diagrams

CPU 4/7 (Power)
Sa ndy Br idg e Pro ces sor 4/ 7 ( P OWE R )
U4
9F

POWER

PRO CESSO R CORE POWE R

*22u_6.3V_X5R_
08

22u
_6.3V_
X5R
_08

22u_6
.3
V_X5R
_08

C620

C627

C169

C162

C6
28

*22u_6.3V_X5R_08

22u_6
.3
V_X5R
_08

C6
13

*22u_6.3V_X5R_
08

C161

22u_6.3V_X5R_08

C125

22u_6.3V_X5R_08

C619

*22
u_6.3V_X5R
_08

C166

VCORE

1
0u_6.3V_X5
R_06

10u
_6.3V_
X5R
_06

10u_6
.3
V_X5R
_06

C174

C192

C193

C171

C1
75

10u
_6.3V_
X5R
_06

10u_6
.3
V_X5R
_06

C1
73

*10u_6.3V_X5R_
06

C172

*10u_
6.3V_X5R
_06

C170

*10u_
6.3V_X5R
_06

C191

*10
u_6.3V_X5R
_06

C190

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

PZ98827-364B-01F

B - 6 CPU 4/7 (Power)

8.5A

1.05VS_VTT
AG
35
AG
34
AG
33
AG
32
AG
31
AG
30
AG
29
AG
28
AG
27
AG
26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

PEG AND DDR

C6
18
22u_6
.3
V_X5R
_08

22u_6.3V_X5R_08

C617
22u
_6.3V_
X5R
_08

22u_6.3V_X5R_0
8

C165
*22u_6.3V_X5R_
08

C616

22u_6.3V_X5R_0
8

Sheet 5 of 49
CPU 4/7
(Power)

C615

10u_6.3V_X5R_0
6

B.Schematic Diagrams

VCORE

4 8A

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

VCCIO40

1.05VS_VT
T

C668
+

C223

C222

C236

C230

C237

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_0
8

2
2u_6.3V_X5R_0
8

C231

C654

C650

C247

C652

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_0
8

2
2u_6.3V_X5R_0
8

C659

C647

C646

C645

C644

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_08

2
2u_6.3V_X5R_0
8

2
2u_6.3V_X5R_0
8

C643

C642

C641

C640

C629

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

C216

C194

C195

C226

C225

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

C224

C227

C228

C229

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

*22u_6.3V_X5R_08

220u_6.3V_6.3*6.3*4.2

C639
+
220u_6.3V_6.3*6.3*4.2

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23

1
. 05
VS_VCCP_F R129

*15mli_short_06 1.05VS_VTT

CAD Note: H_CPU_SVIDALRT #_R,H_CPU_SVIDDAT_R
Place the PU resistors c lose to CPU

SVID Signals
1.05VS_VTT

SVID

SV 48

VIDALERT#
VIDSCLK
VIDSOUT

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#_R
H_CPU_SVIDCLK_R
H_CPU_SVIDDAT_R

R116
R114
R120

43.2_1%_04
0_04
0_04

H_CPU_
SVIDALRT
# 39
H_CPU_
SVIDCLK 39
H_CPU_
SVIDDAT 39

CAD Note: H_CPU_SVIDCLK_R
Plac e the PU
resi stors close to VR

VCORE

R8
7
100_
04

VCO
RE_VCC_SENSE 39
VCO
RE_VSS_SENSE 39
R9
4
100_
04
1.05VS_VTT

SENSE LINES

ICCMAX Maximum Processor

PR OCESSO R UNCO RE PO WER

CORE SUPPLY

VCORE

VCC_SENSE
VSS_SENSE

VCCIO_SENSE
VSSIO_SENSE

AJ35
AJ34

B10
A10

R523
10
_04

VCCIO_SENSE
VSSIO
_SENSE

VCCP_SENSE 38
VSSP_SENSE 38

R526
10_04

39,40
VCORE
2,3,23,24
, 25
,3
5,39 1
.0
5VS_VTT

H_CPU_SVIDALRT#
75_04
H_CPU_SVIDCLK
*54.9_1%_0
4
H_CPU_SVIDDAT_R 130_1%_04

R1
18
R1
17
R1
22

Schematic Diagrams

CPU 5/7 (Graphics Power)
Sandy Bridge Processor 5/7 ( GRAPHICS POWER )
1 .5 V

10/22

POWER

2 2u _ 6 . 3V _X 5 R _ 0 8

C 2 11

C6 5 5

C 18 5

C1 8 4

2 2 u _6 . 3 V _ X 5R _ 08

22 u _ 6. 3 V _ X 5 R _ 0 8

2 2u _ 6 . 3V _X 5 R _ 0 8

2 2 u_ 6 . 3 V _ X5 R _0 8

2 2u _ 6 . 3V _X 5 R _ 0 8

C 2 20

C2 1 2

C 63 2

C6 2 4

22 u _ 6. 3 V _ X 5 R _ 0 8

2 2u _ 6 . 3V _X 5 R _ 0 8

2 2 u_ 6 . 3 V _ X5 R _0 8

2 2u _ 6 . 3V _X 5 R _ 0 8

10/26

C1 8 9
+
2 2 0u _ 6 . 3 V _6 . 3 *6 . 3 *4 . 2

1.2A

1 . 8V S

B 6
A 6
A 2

C6 6 9
+

C2 5 1

C 67 0

1 0u _ 6 . 3 V _X 5 R _ 0 6

56 0 u _2 . 5 V _ 6 . 6* 6 . 6* 5 . 9

C6 6 3

1u _ 6 . 3 V _Y 5 V _ 04

V C C P LL 1
V C C P LL 2
V C C P LL 3

1 u _6 . 3 V _ X 5R _ 04

10/22
S USB #

A L1

V_SM_VR EF

S M _V R E F

1 .5 V S _ CP U

V D D Q1
V D D Q2
V D D Q3
V D D Q4
V D D Q5
V D D Q6
V D D Q7
V D D Q8
V D D Q9
V D D Q 10
V D D Q 11
V D D Q 12
V D D Q 13
V D D Q 14
V D D Q 15

VC
VC
VC
VC
VC
VC
VC
VC

CSA 1
CSA 2
CSA 3
CSA 4
CSA 5
CSA 6
CSA 7
CSA 8

A
A
A
A
A
A
Y
Y
Y
U
U
U
P
P
P

12A

F7
F4
F1
C7
C4
C1
7
4
1
7
4
1
7
4
1

C 6 83
+

C6 7 8

C 6 79

C 67 7

10 u _ 6. 3 V _ X 5 R _ 0 6

1 0 u _6 . 3 V _ X 5R _ 06

1 0 u_ 6 . 3 V _ X5 R _0 6

C6 8 0

C 6 81

C 68 2

10 u _ 6. 3 V _ X 5 R _ 0 6

1 0 u _6 . 3 V _ X 5R _ 06 10 u _ 6. 3 V _ X 5 R _ 0 6

0 .8 5 VS

C1 6 3

C1 6 4

C 1 51

1 0u _ 6 . 3 V _X 5 R _ 0 8

10 u _ 6 . 3V _ X 5 R _ 0 8

1 0 u _ 6. 3 V _ X 5 R _ 0 6

C1 2 6
+
*3 3 0U _ 2. 5V _ D 2_ D

10/28
1 . 05 V S

H 23

VCC SA _ S EN SE

V CC S A _ S E NS E

V C C S A _S E N S E

37

1 .5 V

10 K _ 0 4
R 5 09
F C _ C 22
V CC S A _ V ID1

C 2 2 R6 4 8
C 24

*0 _ 04

10 K _ 0 4

R1 2 6
VCC S A_ VID 0 3 7
V C C S A _V I D 1 3 7

*1 0 K _ 04
R1 2 3

*0 _0 4

6
V CC

RH

G ND

RW

2
3

4
S CL

9 , 1 0 , 19 S M B _ C L K
9 , 1 0 , 19 S M B _ D A T A

*1 2 . 1K _ 1 % _ 04

*A D 52 4 7

SDA

1

R 2 50
3

5
R 25 5
* 12 . 1 K _ 1 %_ 0 4

+
2

U 25
1

C 3 08

C3 1 0

3 .3 VS

5

1 . 5V S

Sheet 6 of 49
CPU 5/7
(Graphics Power)

5 6 0 u_ 2 . 5 V _ 6. 6 * 6. 6 * 5. 9

6A

M 27
M 26
L26
J26
J25
J24
H 26
H 25

V _S M _ V R E F
3 . 3V S

C3 5 5

1K _1 % _ 04

CAD Note: +V_SM_VREF should
have 10 mil trace width

1 . 5V S _C P U

R2 6 7

R2 6 5

20 , 2 9 , 34 , 3 5

R 53 0 V _ S M _ V R E F _ C N T

0 _0 4

P Z 9 8 82 7 -3 64 B -0 1 F

VREF circuitry for +V_SM_VREF(SNB)

10/21

U2 7 A
4

R 26 8

*2 . 2 _0 4

*L M 32 1

For DIGITAL POT: AD5247BKSZ10-1RL7
SMBus Address is WRITE- 2EH
READ-2FH

1 8 , 19 , 2 0 , 2 4, 2 5 , 2 9 , 35 , 3 7 , 3 8, 3 9 1 . 0 5V S
9, 1 0 , 2 4, 35 1 . 5 V S
37
0 . 85 V S
4 0 V GF X _ C O R E
3 , 3 5 1 . 5V S _C P U
23 , 2 4 , 3 7 1. 8 V S
3 , 8 , 9, 10 , 2 5 , 29 , 3 3 , 3 5, 3 7 , 3 8 1. 5V
3 , 9, 1 0 , 1 1 , 12 , 1 8 , 1 9, 2 0 , 2 1, 22 , 2 3 , 24 , 2 5 , 2 7, 2 8 , 2 9 , 30 , 3 1 , 3 2, 3 3 , 3 4 , 35 , 3 9 3 . 3V S

CPU 5/7 (Graphics Power) B - 7

B.Schematic Diagrams

C 65 6

R2 6 6
*1 0 0 K _ 1% _ 0 4

1K _1 % _ 04
V _ S M _V R E F _ C N T

0 . 1 u_ 1 0 V _X 5R _ 04

2 2 u_ 6 . 3 V _ X5 R _0 8

Q 18
* A O3 4 02 L
S
D

V _S M_ V R E F

0 . 1 u_ 1 0 V _X 5R _ 04

2 2u _ 6 . 3V _X 5 R _ 0 8

V C C _ GT _ S E N S E 39
V S S _ GT _ S E N S E 3 9

0 . 1 u _1 0 V _ X 5 R _ 0 4

22 u _ 6. 3 V _ X 5 R _ 0 8

A K 35
A K 34

G

2 2 u _6 . 3 V _ X 5R _ 08

VREF

C1 6 8

DDR3 -1.5V RAILS

C 18 3

R2 6 3

V A X G _S E N S E
V S S A X G _S E N S E

SA RAIL

C2 2 1

MISC

C 1 99

V A X G1
V A X G2
V A X G3
V A X G4
V A X G5
V A X G6
V A X G7
V A X G8
V A X G9
V A X G1 0
V A X G1 1
V A X G1 2
V A X G1 3
V A X G1 4
V A X G1 5
V A X G1 6
V A X G1 7
V A X G1 8
V A X G1 9
V A X G2 0
V A X G2 1
V A X G2 2
V A X G2 3
V A X G2 4
V A X G2 5
V A X G2 6
V A X G2 7
V A X G2 8
V A X G2 9
V A X G3 0
V A X G3 1
V A X G3 2
V A X G3 3
V A X G3 4
V A X G3 5
V A X G3 6
V A X G3 7
V A X G3 8
V A X G3 9
V A X G4 0
V A X G4 1
V A X G4 2
V A X G4 3
V A X G4 4
V A X G4 5
V A X G4 6
V A X G4 7
V A X G4 8
V A X G4 9
V A X G5 0
V A X G5 1
V A X G5 2
V A X G5 3
V A X G5 4

GRAPHICS

C 19 8

AT2 4
AT2 3
AT2 1
AT2 0
AT1 8
AT1 7
AR 2 4
AR 2 3
AR 2 1
AR 2 0
AR 1 8
AR 1 7
AP2 4
AP2 3
AP2 1
AP2 0
AP1 8
AP1 7
AN 2 4
AN 2 3
AN 2 1
AN 2 0
AN 1 8
AN 1 7
AM 2 4
AM 2 3
AM 2 1
AM 2 0
AM 1 8
AM 1 7
AL 2 4
AL 2 3
AL 2 1
AL 2 0
AL 1 8
AL 1 7
AK2 4
AK2 3
AK2 1
AK2 0
AK1 8
AK1 7
AJ 2 4
AJ 2 3
AJ 2 1
AJ 2 0
AJ 1 8
AJ 1 7
AH 2 4
AH 2 3
AH 2 1
AH 2 0
AH 1 8
AH 1 7

1.8V RAIL

33A

SENSE
LINES

U4 9 G
V G F X _ C OR E

Schematic Diagrams

CPU 6/7 (GND)
Sandy Bridge Processor 6/7 ( GND )

B.Schematic Diagrams

U49H

CAD Note: 0 ohm resistor
should be placed close
to CPU

Sheet 7 of 49
CPU 6/7 (GND)

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

PZ98827 -364 B-0 1F

B - 8 CPU 6/7 (GND)

U49I

VSS

VSS8 1
VSS8 2
VSS8 3
VSS8 4
VSS8 5
VSS8 6
VSS8 7
VSS8 8
VSS8 9
VSS9 0
VSS9 1
VSS9 2
VSS9 3
VSS9 4
VSS9 5
VSS9 6
VSS9 7
VSS9 8
VSS9 9
VSS10 0
VSS10 1
VSS10 2
VSS10 3
VSS10 4
VSS10 5
VSS10 6
VSS10 7
VSS10 8
VSS10 9
VSS11 0
VSS11 1
VSS11 2
VSS11 3
VSS11 4
VSS11 5
VSS11 6
VSS11 7
VSS11 8
VSS11 9
VSS12 0
VSS12 1
VSS12 2
VSS12 3
VSS12 4
VSS12 5
VSS12 6
VSS12 7
VSS12 8
VSS12 9
VSS13 0
VSS13 1
VSS13 2
VSS13 3
VSS13 4
VSS13 5
VSS13 6
VSS13 7
VSS13 8
VSS13 9
VSS14 0
VSS14 1
VSS14 2
VSS14 3
VSS14 4
VSS14 5
VSS14 6
VSS14 7
VSS14 8
VSS14 9
VSS15 0
VSS15 1
VSS15 2
VSS15 3
VSS15 4
VSS15 5
VSS15 6
VSS15 7
VSS15 8
VSS15 9
VSS16 0

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N 35
N 34
N 33
N 32
N 31
N 30
N 29
N 28
N 27
N 26
M34
L 33
L 30
L 27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J 34
J 31
H 33
H 30
H 27
H 24
H 21
H 18
H 15
H 13
H 10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G 35
G 32
G 29
G 26
G 23
G 20
G 17
G 11
F34
F31
F29

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

PZ98 827-3 64B-01F

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D 35
D 32
D 29
D 26
D 20
D 17
C 34
C 31
C 28
C 27
C 25
C 23
C 10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

Schematic Diagrams

CPU 7/7 (RESERVED)
Sandy Bridge Processor 7/7 ( RESERVED )
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
1 . 5V

C F G2
C
C
C
C

F G4
F G5
F G6
F G7

Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
CFG4 attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port

C F G4

R4 9 3

CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G

RS
RS
RS
RS
RS

[0 ]
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
[ 1 0]
[ 1 1]
[ 1 2]
[ 1 3]
[ 1 4]
[ 1 5]
[ 1 6]
[ 1 7]

VD2 8
VD2 9
VD3 0
VD3 1
VD3 2

V R E F _ C H _A _D I MM

R 14 9
* 1K _0 4

VD1
VD2
VD3
VD4

AJ 3 1
AH 3 1
AJ 3 3
AH 3 3

D R A MR S T _C N T R L 3, 1 9

VD3 7
VD3 8
VD3 9
VD4 0

R6 4 3

V A X G_ V A L _ S E N S E
V S S A X G_ V A L_ S E N S E
V C C _ V A L _S E N S E
V S S _ V A L _ S E NS E

RS
RS
RS
RS
RS

VD4 1
VD4 2
VD4 3
VD4 4
VD4 5

RS
RS
RS
RS
RS

VD4 6
VD4 7
VD4 8
VD4 9
VD5 0

*0 _ 0 4

R1 5 9

A R 35
AT3 4
AT3 3
AP3 5
A R 34

Q1 0
*A O 3 40 2 L
S
D MV R E F _ D Q _ D I M 1

R 15 3
* 1K _0 4

10/21

1 K _ 1% _ 0 4
R2 7 7

R1 6 0

C 3 67

1 K _ 1% _ 0 4

PCIE Port Bifurcation Straps

CFG[6:5]
CF G 5

CF G 6

R 49 2
R 50 0

11:
10:
01:
00:

(Default) x16 - Device 1 functions 1 and 2 disabled
x8, x8 - Device 1 function 1 enabled ; function 2 disabled
Reserved - (Device 1 function 1 disabled ; function 2 enabled)
x8,x4,x4 - Device 1 functions 1 and 2 enabled

*1 K _ 0 4
*1 K _ 0 4

3 .3 V

R 5 14

1 0K _ 1 % _ 04

H _ S N B _I V B #_ P W R C TR L

R5 1 6

*1 0 m li _ s ho rt

H_ S N B _ IV B # _ P W RC T RL _ R

F2 5
F2 4
F2 3
D 24
G 25
G 24
E2 3
D 23
C 30
A3 1
B3 0
B2 9
D 30
B3 1
A3 0
C 29

J20
B1 8
A1 9

RS V D 6
RS V D 7

RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

RS V D 2 4
RS V D 2 5
V C C I O_ S E L

RESERVED

RS V D 5

B4
D 1

MV R E F _ D Q _D I MM A 9

1 .5 V
RS
RS
RS
RS

T8
J16
H 16
G 16

AJ 2 6

V R E F _C H _ A _ D I MM
V R E F _C H _ B _ D I MM

0 _ 04

C3 5 7

AT2 6
A M 33
AJ 2 7

V R E F _ C H _B _D I MM
P U_ RS
P U_ RS
P U_ RS
P U_ RS

R2 5 4
R1 5 0
1K _ 1 % _ 04

RS V D3 3
RS V D3 4
RS V D3 5

* 1 K _0 4
H_ C
H_ C
H_ C
H_ C

10/21

1K _ 1 % _ 04
MV R E F _ D Q _D I M 0

RS V D5 1
RS V D5 2

B3 4
A3 3
A3 4
B3 5
C 35

D RA M RS T _ CN T RL 3 ,1 9

0 _ 04

MV R E F _ D Q_ D I M MB

10

Sheet 8 of 49
CPU 7/7
(RESERVED)

AJ 3 2
AK3 2

A H 27
V C C _D I E _ S E N S E

RS V D5 4
RS V D5 5

RS V D5 6
RS V D5 7
RS V D5 8

A N 35
A M 35

AT2
AT1
AR 1

J15

On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V

PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7 0: PEG Wait for BIOS for training

C F G7

R4 9 1

RS V D 2 7
B1
KEY

P Z 9 8 8 27 -3 6 4B -01 F

* 1K _0 4

3 , 6 , 9, 10 , 2 5 , 2 9, 3 3 , 3 5 , 37 , 3 8 1 . 5V
2 , 3 , 1 1 , 1 2, 1 6 , 1 8 , 19 , 2 0 , 2 2, 2 3 , 2 4 , 25 , 2 7 , 2 8, 29 , 3 0 , 3 3, 3 5 , 3 7 , 38 , 3 9 3 . 3V

CPU 7/7 (RESERVED) B - 9

B.Schematic Diagrams

AK2 8
AK2 9
AL 2 6
AL 2 7
AK2 6
AL 2 9
AL 3 0
AM 3 1
AM 3 2
AM 3 0
AM 2 8
AM 2 6
AN 2 8
AN 3 1
AN 2 6
AM 2 7
AK3 1
AN 2 9

C F G0

0 . 1u _ 1 0 V _X 5R _ 04

* 1 K _0 4

Q9
*A O 3 40 2 L
S
D

G

R5 0 3

*0 _ 0 4
R1 5 5

L7
AG 7
AE7
AK2
W8

G

C F G2

R6 4 2
U4 9 E

0 . 1 u _1 0 V _ X 5 R _ 0 4

1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed

CFG2

Schematic Diagrams

DDR3 SO-DIMM_0
SO-DIMM A
CHANGE TO STANDARD
C 3 5 4 * 10 p _ 50 V _ N P O _ 04
M _ A _C L K _D D R 0
M_ A _ C L K _ D D R # 0
J D I M M1 A

M_ A _ A [ 1 5: 0 ]

M_ A _ A 0
M_ A _ A 1
M_ A _ A 2
M_ A _ A 3
M_ A _ A 4
M_ A _ A 5
M_ A _ A 6
M_ A _ A 7
M_ A _ A 8
M_ A _ A 9
M_ A _ A 1 0
M_ A _ A 1 1
M_ A _ A 1 2
M_ A _ A 1 3
M_ A _ A 1 4
M_ A _ A 1 5

Sheet 9 of 49
DDR3 SO-DIMM_0

4
4
4
4

4
M_ A _ B S 0
4
M_ A _ B S 1
4
M_ A _ B S 2
4
M_ A _ C S #0
4
M_ A _ C S #1
M_ A _ C L K _ D D R 0
M_ A _ C L K _ D D R # 0
M_ A _ C L K _ D D R 1
M_ A _ C L K _ D D R # 1
4
M_ A _ C K E 0
4
M_ A _ C K E 1
4
M _A _C A S #
4
M _A _R A S #
4
M _A _W E #

10 9
10 8
79
11 4
12 1
10 1
10 3
10 2
10 4
73
74
11 5
11 0
11 3
19 7
20 1
20 2
20 0

S A 0 _ DIM 0
S A 1 _ DIM 0

6, 1 0 , 1 9 S MB _ C L K
6, 1 0 , 1 9 S MB _ D A TA
4
4

11 6
12 0

M_ A _ OD T 0
M_ A _ OD T 1

11
28
46
63
13 6
15 3
17 0
18 7
4

M_ A _ D Q S [ 7 : 0]

3. 3 V S
4 M_ A _ D QS # [ 7 : 0]
R N3
1 0 K _ 8P 4 R _0 4
1
8 S A 1_ D I M1
2
7 S A 0_ D I M1
3
6 S A 1_ D I M0
4
5 S A 0_ D I M0

S A 1_ D I M1 1 0
S A 0_ D I M1 1 0

M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q

S0
S1
S2
S3
S4
S5
S6
S7

12
29
47
64
13 7
15 4
17 1
18 8

M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q

S# 0
S# 1
S# 2
S# 3
S# 4
S# 5
S# 6
S# 7

10
27
45
62
13 5
15 2
16 9
18 6

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1 0 /A P
A1 1
A1 2 /B C#
A1 3
A1 4
A1 5

D Q0
D Q1
D Q2
D Q3
D Q4
D Q5
D Q6
D Q7
D Q8
D Q9
D Q1 0
D Q1 1
D Q1 2
D Q1 3
D Q1 4
D Q1 5
D Q1 6
D Q1 7
D Q1 8
D Q1 9
D Q2 0
D Q2 1
D Q2 2
D Q2 3
D Q2 4
D Q2 5
D Q2 6
D Q2 7
D Q2 8
D Q2 9
D Q3 0
D Q3 1
D Q3 2
D Q3 3
D Q3 4
D Q3 5
D Q3 6
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
D Q4 2
D Q4 3
D Q4 4
D Q4 5
D Q4 6
D Q4 7
D Q4 8
D Q4 9
D Q5 0
D Q5 1
D Q5 2
D Q5 3
D Q5 4
D Q5 5
D Q5 6
D Q5 7
D Q5 8
D Q5 9
D Q6 0
D Q6 1
D Q6 2
D Q6 3

BA0
BA1
BA2
S0 #
S1 #
CK 0
C K 0#
CK 1
C K 1#
CK E 0
CK E 1
CA S #
RA S #
W E#
SA0
SA1
SC L
SD A
OD T 0
OD T 1
DM
DM
DM
DM
DM
DM
DM
DM

0
1
2
3
4
5
6
7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0
S1
S2
S3
S4
S5
S6
S7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0 #
S1 #
S2 #
S3 #
S4 #
S5 #
S6 #
S7 #

M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M _ A _ D Q[ 6 3 : 0 ] 4

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

J D I MM 1B
1 .5 V

3 .3 VS

2 0 mi ls
C 3 59

C 3 60

1 u _ 6. 3 V _ X 5R _ 04

0 . 1 u _1 6 V _ Y 5 V _ 0 4

77
12 2
12 5

1 0 K _ 04

19 8
30

1 0 T S # _D I MM 0 _1
3, 1 0 D D R 3 _ D R A MR S T #
C 3 75
C 3 74
R2 5 7

8 MV R E F _ D Q _ D I M MA

1 u_ 6 . 3 V _X 5 R _ 0 4
0 . 1u _ 1 6V _ Y 5V _0 4
0_04
R 2 62

V R E F _ D Q_ C A _0

C 3 28
C 3 25

1 u_ 6 . 3 V _X 5 R _ 0 4
0 . 1u _ 1 6V _ Y 5V _0 4

CLOSE TO SO -D IMM _0
R2 2 9

1. 5 V

1 K _ 1 %_ 0 4

1
12 6

M V R E F _D I M0

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

V R E F _ DQ
V R E F _ CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5

S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
S 28
S 29
S 30
S 31
S 32
S 33
S 34
S 35
S 36
S 37
S 38
S 39
S 40
S 41
S 42
S 43
S 44
S 45
S 46
S 47
S 48
S 49
S 50
S 51
S 52

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

V T T_ M E M
V T T1
V T T2
G1
G2

203
204
G ND 1
G ND 2

C 3 16

1 K _ 1 %_ 0 4

0 . 1 u _1 0 V _ X5 R _0 4

R 2 5 2 * 0 _0 4
MV R E F _ D Q_ D I MM A
3 .3 VS

1 .5 VS

C 33 4

C3 7 6

C 36 6

C3 4 1

C 34 0

1

1 0 u_ 1 0 V _ Y 5 V _ 08

1u _ 6 . 3V _X 5 R _ 0 4

1 u _6 . 3 V _ X 5R _ 04

1u _ 6 . 3 V _X 5 R _ 0 4

1 u _6 . 3 V _ X 5R _ 04

2

U 21
VC C

6
R H
5

G ND

R W

SC L

S DA

3
6 , 1 0, 19 S M B _ C L K

EVEN T#
R ESET#

VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS

7 8 1 21 -0 0 11

R 2 39

For DIGITAL POT: ISL90727
SMBus Address is
Write: 5CH
Read: 5DH

1 .5 V

N C1
N C2
N CT E ST

*0 _ 04

MV R E F _ D I M 0

3. 3 V S

4
* I S L 90 7 2 7

* 12 . 1 K _ 1 %_ 0 4
R2 3 4

1
3

R 2 43

+
-

U2 2
R 2 4 9 * 2 . 2_ 0 4
4

*L M3 2 1

* 12 . 1 K _ 1 %_ 0 4

6 , 1 0, 19 S M B _ D A T A

C 36 4

C3 7 0

C 33 3

C3 3 7

C 33 8

C3 3 0

C 37 1

C3 3 6

C 33 2

C3 3 9

0 . 1 u_ 1 6 V _ Y 5 V _ 04

0. 1 u _ 16 V _ Y 5V _ 0 4

0 . 1 u_ 1 6 V _ Y 5 V _ 04

0. 1u _ 1 6V _ Y 5V _ 0 4

0 . 1 u _1 6 V _ Y 5 V _ 04

0. 1u _ 1 6V _ Y 5V _ 0 4

0 . 1 u _1 6 V _ Y 5 V _ 04

0 . 1u _ 1 6V _ Y 5V _ 0 4

0 . 1 u _1 6 V _ Y 5 V _ 04

0 . 1u _ 1 6V _ Y 5V _ 0 4
6, 1 0 , 2 4, 3 5
1 0, 3 8
3 , 6, 8 , 1 0 , 25 , 2 9 , 3 3, 3 5 , 3 7, 3 8
3 , 6, 1 0 , 1 1, 12 , 1 8 , 19 , 2 0 , 21 , 2 2 , 2 3, 2 4 , 2 5, 27 , 2 8 , 29 , 3 0 , 31 , 3 2 , 3 3, 3 4 , 3 5, 3 9

1 .5 V

11/5
C 39 4

B - 10 DDR3 SO-DIMM_0

D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8

V D DS PD

R2 5 1

V TT _ ME M

C 38 2
+

5 6 0u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9

VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD

19 9
3 .3 VS

7 8 12 1 -0 0 11

+

75
76
81
82
87
88
93
94
99
10 0
10 5
10 6
11 1
11 2
11 7
11 8
12 3
12 4

5

B.Schematic Diagrams

La y out Note :
signa l/spa c e/ signa l:
8 /4 / 8

98
97
96
95
92
91
90
86
89
85
10 7
84
83
11 9
80
78

2

4

C 3 4 8 * 10 p _ 50 V _ N P O _ 04
M _ A _C L K _D D R 1
M_ A _ C L K _ D D R # 1

* 22 0 u _6 . 3 V _ 6. 3* 6. 3 * 4. 2

C 33 5

C3 6 1

C 32 4

C3 6 8

C 36 9

C3 3 1

C 36 5

C3 6 3

1 0 u_ 1 0 V _ Y 5 V _ 08

10 u _ 10 V _ Y 5V _ 0 8

1 0 u_ 6 . 3 V _ X5 R _0 6

1u _ 6 . 3 V _X 5 R _ 0 4

1 u _ 6. 3 V _ X 5R _ 04

1 u_ 6 . 3 V _X 5 R _ 0 4

1 u _ 6. 3 V _ X 5R _ 04

1 u_ 6 . 3 V _X 5 R _ 0 4

1 .5 V S
V T T _M E M
1 .5 V
3 .3 V S

Schematic Diagrams

DDR3 SO-DIMM_1
CHANGE TO STANDARD
SO-DIMM B
J D I M M2 B
C 40 5
M _ B _ CL K _ DD R2

*1 0 p _5 0 V _ N P O _ 04
M _B _C L K _ D D R # 2

C 40 1
M _ B _ CL K _ DD R3

*1 0 p _5 0 V _ N P O _ 04
M _B _C L K _ D D R # 3

4

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

Lay out N ote :
signa l/ spa ce /si gnal :
8 /4 / 8

_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B

_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

116
120

M _ B _ OD T2
M _ B _ OD T3

11
28
46
63
136
153
170
187
4

M _B _D QS [ 7: 0 ]

4 M _ B _ D Q S # [ 7: 0 ]

M
M
M
M
M
M
M
M

_B
_B
_B
_B
_B
_B
_B
_B

_D
_D
_D
_D
_D
_D
_D
_D

QS
QS
QS
QS
QS
QS
QS
QS

0
1
2
3
4
5
6
7

12
29
47
64
137
154
171
188

M
M
M
M
M
M
M
M

_B
_B
_B
_B
_B
_B
_B
_B

_D
_D
_D
_D
_D
_D
_D
_D

QS
QS
QS
QS
QS
QS
QS
QS

#0
#1
#2
#3
#4
#5
#6
#7

10
27
45
62
135
152
169
186

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 1 0 /A P
A1 1
A 1 2 /B C#
A1 3
A1 4
A1 5

DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 1 0
DQ 1 1
DQ 1 2
DQ 1 3
DQ 1 4
DQ 1 5
DQ 1 6
DQ 1 7
DQ 1 8
DQ 1 9
DQ 2 0
DQ 2 1
DQ 2 2
DQ 2 3
DQ 2 4
DQ 2 5
DQ 2 6
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
DQ 3 1
DQ 3 2
DQ 3 3
DQ 3 4
DQ 3 5
DQ 3 6
DQ 3 7
DQ 3 8
DQ 3 9
DQ 4 0
DQ 4 1
DQ 4 2
DQ 4 3
DQ 4 4
DQ 4 5
DQ 4 6
DQ 4 7
DQ 4 8
DQ 4 9
DQ 5 0
DQ 5 1
DQ 5 2
DQ 5 3
DQ 5 4
DQ 5 5
DQ 5 6
DQ 5 7
DQ 5 8
DQ 5 9
DQ 6 0
DQ 6 1
DQ 6 2
DQ 6 3

BA0
BA1
BA2
S0 #
S1 #
CK 0
C K 0#
CK 1
C K 1#
CK E0
CK E1
CA S#
RA S#
W E#
SA0
SA1
SC L
SD A
OD T 0
OD T 1
DM
DM
DM
DM
DM
DM
DM
DM

0
1
2
3
4
5
6
7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0
S1
S2
S3
S4
S5
S6
S7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

S0 #
S1 #
S2 #
S3 #
S4 #
S5 #
S6 #
S7 #

M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
1 29
1 31
1 41
1 43
1 30
1 32
1 40
1 42
1 47
1 49
1 57
1 59
1 46
1 48
1 58
1 60
1 63
1 65
1 75
1 77
1 64
1 66
1 74
1 76
1 81
1 83
1 91
1 93
1 80
1 82
1 92
1 94

M_ B _ D Q[ 6 3 : 0 ] 4

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

3. 3 V S

20 m ils
C4 1 8

C4 1 0

199

1 u_ 6 . 3 V _ X5 R _0 4

0 . 1u _ 1 6 V _Y 5 V _ 04

77
122
125

C4 1 6
C4 1 5
0 _ 04

R 28 2

8 M V R E F _ D Q _D I MM B

1 u _ 6. 3V _ X 5 R _ 0 4
0 . 1 u _ 16 V _ Y 5V _ 0 4
R2 7 9

V R E F _D Q_ C A _ 1

R2 7 0

1 K _ 1% _ 0 4

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

1 u _ 6. 3V _ X 5 R _ 0 4
0 . 1 u _ 16 V _ Y 5V _ 0 4

MV R E F _ D I M 1

R 2 74

Note:- For DIGITAL POT: ISL90728
SMBus Address is WRITE:7CH
READ: 7DH

1 u_ 6 . 3 V _ X5 R _0 4

1 u_ 6 . 3 V _ X5 R _ 04

1 u _ 6 . 3V _X 5 R _ 0 4

U 28

6

VC C

R H

G ND

RW

GN D 1
GN D 2

M V R E F _ D Q_ D I MM B

SC L

S DA

* 12 . 1 K _ 1 % _0 4

1

R 2 72
3

5

3
6 , 9 , 1 9 S MB _ C LK

1 . 5V

G1
G2

2 03
2 04

R 2 7 8 * 0_ 0 4

5
1u _ 6 . 3 V _ X5 R _0 4

V T T_ M E M
VTT1
VTT2

3. 3V S

4
* I S L 90 7 2 8

R 2 75

+
2

C3 8 1
2

10 u _ 1 0V _ Y 5 V _0 8

Sheet 10 of 49
DDR3 SO-DIMM_1

1. 5V S

1
C3 8 5

44
48
49
54
55
60
61
65
66
71
72
1 27
1 28
1 33
1 34
1 38
1 39
1 44
1 45
1 50
1 51
1 55
1 56
1 61
1 62
1 67
1 68
1 72
1 73
1 78
1 79
1 84
1 85
1 89
1 90
1 95
1 96

0 . 1u _ 1 0 V _X 5 R _0 4

3 .3 VS

C3 8 0

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5

VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2

7 8 19 2 -0 0 11

C 3 84

1 K _ 1 % _0 4

V R E F _ DQ
V R E F _ CA

*0 _ 04

CLO SE TO SO -DI MM 1

1 .5 V

EVEN T #
RE SE T #

1
126

MV R E F _ D I M1
C3 9 7
C4 0 2

NC 1
NC 2
NC T E S T

198
30

9 TS # _ D I MM 0_ 1
3 , 9 D D R 3 _ D R A MR S T #

V T T _M E M

C4 1 7

D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8

V D DS P D

7 8 19 2 -0 0 11

C3 9 8

VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD

U 29
R2 8 0

*2 . 2 _0 4

4

* L M3 2 1

* 12 . 1 K _ 1 % _0 4

6 , 9 , 1 9 S MB _ D A TA
C3 7 2

C4 0 3

C4 0 6

C3 9 0

C3 9 1

C4 0 8

C3 8 6

C 38 8

10 u _ 1 0V _ Y 5 V _0 8

10 u _ 1 0V _Y 5 V _0 8

1 0u _ 1 0V _Y 5 V _ 08

1 u_ 6 . 3 V _ X5 R _ 04

1 u_ 6 . 3 V _ X 5R _ 04

1 u_ 6 . 3 V _ X 5R _ 04

1 u _6 . 3 V _ X 5R _ 04

1 u _6 . 3 V _ X 5R _ 0 4

La yout Note :
SO -D IMM _1 i s pl ac e d fa rt he r f rom t he GM CH tha n S O- DIM M_ 0

1. 5 V

C 40 7
0. 1u _ 1 6V _Y 5 V _ 04

C3 8 7

C4 0 9

C4 0 0

C3 8 9

C4 0 4

C4 1 4

C 41 3

C 41 2

C 41 1

0. 1u _ 1 6V _Y 5 V _ 04

0 . 1u _ 1 6 V _Y 5 V _ 04

0 . 1u _ 1 6 V _Y 5 V _ 04

0 . 1u _ 1 6 V _ Y 5 V _ 0 4

0 . 1 u_ 1 6 V _ Y 5 V _ 0 4

0 . 1 u_ 1 6 V _ Y 5 V _ 0 4

0 . 1 u_ 1 6 V _ Y 5 V _ 0 4

0 . 1 u_ 1 6 V _ Y 5 V _ 0 4

0 . 1 u _1 6 V _ Y 5 V _ 0 4

9, 3 8
3, 6, 8 , 9 , 2 5 , 2 9, 3 3 , 3 5 , 37 , 3 8
3 , 6, 9 , 1 1 , 1 2, 18 , 1 9 , 2 0, 2 1 , 2 2 , 23 , 2 4 , 2 5 , 27 , 2 8 , 2 9, 3 0 , 3 1 , 3 2, 3 3 , 3 4 , 35 , 3 9
6 , 9 , 24 , 3 5

V T T _M E M
1 .5 V
3 .3 VS
1 .5 VS

DDR3 SO-DIMM_1 B - 11

B.Schematic Diagrams

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200

4
M _ B_ BS0
4
M _ B_ BS1
4
M _ B_ BS2
4
M _ B_ CS# 2
4
M _ B_ CS# 3
4 M_ B _ C L K _ D D R 2
4 M_ B _ C L K _ D D R #2
4 M_ B _ C L K _ D D R 3
4 M_ B _ C L K _ D D R #3
4 M_ B _ C K E 2
4 M_ B _ C K E 3
4
M_ B _ C A S #
4
M_ B _ R A S #
4
M_ B _ W E #
9
S A 0_ D I M1
9
S A 1_ D I M1
6, 9 , 1 9 S M B _C L K
6, 9 , 1 9 S M B _D A T A
4
4

1 . 5V

J D I M M2 A

M_ B _ A [ 1 5 : 0]

Schematic Diagrams

Panel, Inverter, CRT
3 .3 V S

R 30

V IN

*C D B U 00 3 40
A

P 2 0 03 E V G

C4 8 8

0 . 1 u_ 1 6V _Y 5 V _ 0 4

0 . 1u _ 1 6V _ Y 5 V _ 04

10 u _ 10 V _ Y 5 V _ 08

G

C2 4 8

1 0 K _ 04
R 86

10 0 K _ 04

2A

L E D P L_ V I N

R6 5 4

S
Q 22 A
D MN 60 1 D W K -7

C 16

2 00 _ 1 %_ 0 4

10/29
Q2 2 B 5 G
D MN 60 1 D W K -7

10 0 K _ 04
C1 9

R2 2 6

*1 00 K _ 0 4

2G

N B _E N A V D D

21 , 3 4 N B _ E N A V D D

D

R 1 97

3

I N V _ B L ON
E MB _H P D _ C O MB O

3. 3 V

0. 1 u _ 16 V _ Y 5 V _ 0 4

D

S

P _ GN D

L2

*0 . 1 u _1 6 V _ Y 5 V _0 4

0 . 1 u_ 1 6 V _Y 5 V _0 4
R 4 89

.
34

H C B 16 0 8 K F -1 21 T 25

* 10 0 K _ 04

BKL _ EN

21

R 2 28

BKL _ EN

1

B L ON

2

U4 5 A
7 4L V C 08 P W
3

BL O N

B LO N 1

U4 5 B
7 4L V C 08 P W

4

3 .3 V
6 B L ON 2

5
R 4 90

3A

C1 2 8

OP E N _ 2A

3 .3 VS
P LV D D

1 0 0K _0 4

2 1 0 _1 % _ 06

7

3
2
1

Q4 6
R5 7 8

8
7
6
5

* 1u _ 6 . 3V _ X 5 R _ 04

3. 3 V

C 21

3.3V

.

C 1 44
2

3 .3 V

LE D P L _V I N
L1
*H C B 1 6 08 K F -1 2 1 T2 5

P J 33

R 22 3

L V D S -L 2 N 2 1
L V D S -L 2 P 2 1

8 7 21 6 -4 00 6

A

D6
C

C

*B A V 99 R E C T I F I E R

3 4 BRIG HT NE S S
V IN

0 _ 04

>100 mil1

>100mil

4

D2 4

L VDS & ED P C o- lay

Sheet 11 of 49
Panel, Inverter,
CRT

*1 0 K _0 4 B R I GH TN E S S _ R

OP E N _ 2A
3 .3 VS

L V D S -U 0 N 2 1
L V D S -U 0 P 21

PL VD D

Q3 0
A O 3 41 5
S
D

>100 mil
10/29

2

C1 7

U 4 5C
7 4 L V C0 8 P W

14

R 4 60

PL VD D

L V D S -L 0N
L V D S -L 0 P

P J 20

14

21
21

>100 mil1

6

L V D S -L 1 N _ C OMB O
L V D S -L 1 P _ C O MB O

5V S

L V D S -U 2 N 2 1
L V D S -U 2 P 21

1

G1
G 2

L V D S -L C LK N _ C OM B O
L V D S -L C LK P _C OMB O

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

14

8 * 0_ 8 P 4 R _ 04 L V D S -U C L K N _C OM B O
7
L V D S -U C L K P _ C O MB O
6
L V D S -U 1 N _ C O MB O
5
L V D S -U 1 P _ C OM B O
8 * 0_ 8 P 4 R _ 04 L V D S -LC LK N _ C O MB O
7
L V D S -LC LK P _C OM B O
6
L V D S -L1 N _ C OMB O
5
L V D S -L1 P _ C O MB O
*0 _ 04
E MB _ H P D _ C O MB O

L V D S -U 1 N _ C O MB O
L V D S -U 1 P _C OM B O

PL VD D
LV DS :3 .3 V 2A
eD P 3D :5 V 3A

7

RN1 1 1
2
3
4
RN2 1 1
2
3
4
R 6 64

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

L V D S -U C L K N _C OM B O
L V D S -U C L K P _ C O MB O

P _ DD C_ DA T A 2 1
P _ DD C_ CL K 2 1

G nd1
Gn d 2

-U C L K N _C OM B O
-U C L K P _ C O MB O
-U 1 N _ C O MB O
-U 1 P _ C OM B O
-LC LK N _ C O MB O
-LC LK P _C OM B O
-L1 N _ C OMB O
-L1 P _ C O MB O

AC

1 0 _ 8P 4 R _0 4 L V D S
2
L V DS
3
L V DS
4
L V DS
1 0 _ 8P 4 R _0 4 L V D S
2
L V DS
3
L V DS
4
L V DS

S B _ B LO N
28 , 3 4

LI D _ S W #

13

R4 3 3

R 4 32

1 50 _ 1 %_ 0 4

15 0 _ 1% _ 0 4

1 5 0 _1 % _ 04

H5
MT H 7 _ 0 D 2 _8 _ O

M1 1
M1 6
M1 2
M 13
M-M A R K M-M A R K M-MA R K M -MA R K

C 5 60

F C M 10 0 5M F -6 00 T 0 1

F G RN

2

F C M 10 0 5M F -6 00 T 0 1

F B L UE

3

9
10

C 5 62

C5 6 1

C5 5 9

4
5

2
3
4
5

M T H 7 _0 D 2_ 8

H1 8

9
1

7
6

MT H 7 _ 0D 2 _8

2
3
4
5

H2 6

9
1

7
6

MT H 7 _ 0 D 2 _8

H 17
2
3
4
5

1

GN D H 6
9
2
8
3
7
4
6
5

1

GN D
9
2
8
3
7
4
6
5

H2 8

1

GN D
H1 4
9
2
3
7
4
1
6
5

G ND
9
8
7
6

13
15

2 1 DA C_ V S Y N C
5V S

R 4

1

1_ 0 4

1

GN D H 2 4
9
2
8
3
1
7
4
6
5

M TH 7 _0 D 2_ 8
GN D

B - 12 Panel, Inverter, CRT

GN D
9
2
3
7
4
6
5

M T H 7 _0 D 2_ 8
GN D

H7
1

GN D
9
8
7
6

MT H 7 _ 0D 2 _8
GN D

C 2

MT H 7 _ 0 D 2 _8

GN D

G ND

C 6

7

0 . 2 2 u_ 1 0 V _Y 5V _ 0 4

H 3
2
3
4
5

MT H 7 _ 0D 2 _8

8

BY P

C 3
D D C D A TA

9
D D C _I N 1

D D C _ OU T 1

D D C _I N 2

D D C _ OU T 2

S Y N C _I N 1

S Y N C _ OU T 1

S Y N C _I N 2

S Y N C _ OU T 2

VC C_ SY NC

V I D E O_ 1

2

0 . 2 2u _ 1 0V _ Y 5 V _ 04

GN D

M T H 7 _0 D 2_ 8

D D C LK

U4 0
11

21 D A C _ D D C A C LK

3. 3V S
M TH 7 _0 D 2_ 8

VSYN C

15

5 VS

10

21 D A C _ D D C A D A TA

2 1 DA C_ HS Y NC

GN D

HSY NC

14
8

1
2
3
4
M TH 7 _0 D 2_ 8

9
8
7
6

D DC DA T A

13
7

RN 1
2 . 2K _8 P 4 R _ 0 4

1

12
6

8
7
6
5

3 .3 VS

24 mil

11

C5 5 8

C 1

R 4 34

6p _ 5 0V _ N P O _ 04

H1 9
H6 _ 0 D3 _ 7

H 12

0. 1 u _1 0 V _ X5 R _0 4

1 0 00 p _ 50 V _ X 7 R _ 04

L 41

C 4

D A C_ B L UE

L 42

DA C_ B L UE

2 2 0p _ 5 0V _ N P O_ 0 4

21

DAC_ G RE EN

1

C5

2 1 D A C _ GR E E N

FR ED

2 2 0 p_ 5 0 V _N P O_ 0 4

H2 2
C 1 5 8D 1 58

F C M 10 0 5M F -6 00 T 0 1

10 0 0 p_ 5 0V _X 7 R _ 0 4

H1
C 1 58 D 15 8

L 43

GN D 1
G ND 2

H2 3
C 1 5 8D 1 58

DAC_ R E D

6 p_ 5 0 V _N P O _ 0 4

H2
C1 5 8 D1 5 8

M2
M9
M4
M5
M-M A R K M-M A R K M-MA R K M -MA R K

2
3
4
5

* 1M _0 4

J_ C R T 1
1 0 8A H 15 F S T 0 4 N 1 C 3

11/5 EMI

D AC_ R E D

C 56 3

9
8
7
6

10/22
C 5 84

1 1 LI D _S W #1

6p _ 5 0V _ N P O _ 0 4

M1 0
M1 5
M7
M 14
M-M A R K M-M A R K M-MA R K M -MA R K

1

I N V _ B L ON

R 48 6

7

CRT

H2 5
C 1 4 6D 1 10

6 p _ 50 V _ N P O _0 4

H2 0
C 1 58 D 15 8

6 p_ 5 0V _N P O _ 0 4

H2 1
C 1 4 6D 1 10

6 p _ 50 V _ N P O _ 04

H4
C1 4 6 D1 1 0

21

H 27

U4 5 D
7 4L V C 08 P W

12

20 , 3 4 , 39 A L L _S Y S _ P W R G D

N B _ E NAV D D

M1
M6
M3
M8
M-M A R K M-M A R K M-MA R K M -MA R K

2
3
4
5

8
10

11/5
G2

Q4 5A S
D M N 6 01 D W K -7

3. 3 V

*1 00 K _ 0 4
S B _ B L ON 1

23

S

4
6

D

R4 8 8

Q4 5 B
D M N 6 0 1D W K -7

5G
C 15
* 0. 1 u _ 50 V _ Y 5 V _ 0 6

4 . 7 u_ 6 . 3 V _X 5 R _ 0 6

7

4

D

14

3

9
1 M_ 04

1

B.Schematic Diagrams

D P _T X N 0
D P _ TX P 0
D P _T X N 1
D P _ TX P 1
D P _A U X N
D P_ AUX P
D P _T X N 2
D P _ TX P 2
E MB _ H P D

8
7
6
5
RN1 0 8
7
6
5

PANEL POWER

.
.
.

2
2
2
2
2
2
2
2
2

RN8

LV D S -U C L K N
L V D S -U C L K P
L V D S -U 1 N
L V D S -U 1 P
L V D S -LC L K N
LV D S -L C L K P
L V D S -L 1 N
L V D S -L 1 P

R2 7
2 . 2 K _0 4

J_ L C D 1
21
21
21
21
21
21
21
21

R 28
2 . 2 K _ 04

PANEL CONNECTOR (LED+EDP)

VC C_ VID E O

V I D E O_ 2

V C C_ DD C

V I D E O_ 3

12

D D C LK

14

H S YN C_ C R1 3

16

V S Y N C _C R 1

H SYN C

3 3 _0 4

VSYN C

FR ED

4

F G RN

5

FBL U E

6
BY P

3 3 _0 4

3

GN D

I P 47 7 2 C Z 1 6
C 55 7
0 . 2 2 u_ 1 0V _Y 5V _0 4

CM2009-02QR PN:6-02-20090-B60
IP4772CZ16 PN:6-02-47721-B60

35 , 3 6 , 37 , 3 8 , 39 , 4 0 , 41 , 4 2 V I N
1 8, 2 4 , 2 5, 2 7 , 2 8, 3 1 , 3 2, 3 3 , 3 5, 3 9 , 4 0 5 V S
2 , 3 , 8 , 12 , 1 6 , 18 , 1 9 , 20 , 2 2 , 23 , 2 4 , 25 , 2 7 , 28 , 2 9 , 30 , 3 3 , 35 , 3 7 , 38 , 3 9 3. 3 V
3 , 6 , 9 , 10 , 1 2 , 18 , 1 9 , 20 , 2 1 , 22 , 2 3 , 24 , 2 5 , 27 , 2 8 , 29 , 3 0 , 31 , 3 2 , 33 , 3 4 , 35 , 3 9 3. 3 V S

Schematic Diagrams

VGA PCI-E Interface
G PU
H9
H1 1
H 13
H 8_0D 4_4 H8 _0D 4_4 H 8_0D 4_4

U46A
1/16 PCI _EXPR ESS

PEX _VD D
PEX_IO VDD
PEX_IO VDD
PEX_IO VDD
PEX_IO VDD
PEX_IO VDD

3V3 _RU N

AK1
AK1
AK2
AK2
AK2

6
7
1
4
7

3V3_ RU N
C1 17

C 106

C 94

C 123

C3 6

C40

0. 1u_10V _X7R _04

0. 1u_10 V_X7R _04

1u_ 6.3 V_X5R _04

1u_6 .3V _X5R _04

10u_6 .3V _X5R _06

4.7 u_6. 3V_ X5R_ 06 2 2u_6. 3V _X5R _08

BIOS ROM

C 33

3V3_ RU N
R45 1

PLA CE N EA R BA LLS

R 45
100 K_04

5

2
A R1 3
PE X_C LKR EQ

D

S

19 VGA_P EXC LK
19 VGA_P EXC LK #
2
2

PE G_ RX0
PE G_ RX# 0

2
2

P EG _TX0
P EG _TX# 0

2
2

PE G_ RX1
PE G_ RX# 1

2
2

P EG _TX1
P EG _TX# 1

2
2

PE G_ RX2
PE G_ RX# 2

2
2

P EG _TX2
P EG _TX# 2

2
2

PE G_ RX3
PE G_ RX# 3

2
2

P EG _TX3
P EG _TX# 3

2
2

PE G_ RX4
PE G_ RX# 4

2
2

P EG _TX4
P EG _TX# 4

2
2

PE G_ RX5
PE G_ RX# 5

2
2

P EG _TX5
P EG _TX# 5

2
2

PE G_ RX6
PE G_ RX# 6

2
2

P EG _TX6
P EG _TX# 6

2
2

PE G_ RX7
PE G_ RX# 7

2
2

P EG _TX7
P EG _TX# 7

3

PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ

PE G_ CLK RE Q# _R

R5 2

*10mil _shor t

PE X_TS TC LK_O UT
*220_1%_0 4 PE X_TS TC LK_O UT #

R6 8
V GA _PE XCL K
V GA _PE XCL K#
P EG_R X0
P EG_R X#0

A R1 6
A R1 7
C 71
C 75

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X0
PE X_R X0#

P EG_TX0
P EG_TX#0
P EG_R X1
P EG_R X#1

C 74
C 82

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X1
PE X_R X1#

C 87
C 83

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X2
PE X_R X2#

C 86
C 95

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X3
PE X_R X3#

C 97
C 103

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X4
PE X_R X4#

C 108
C 109

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X5
PE X_R X5#

C 121
C 122

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X6
PE X_R X6#

P EG_TX6
P EG_TX#6
P EG_R X7
P EG_R X#7
P EG_TX7
P EG_TX#7

AL2 0
A M2 0
AP2 0
A N2 0

P EG_TX5
P EG_TX#5
P EG_R X6
P EG_R X#6

AL1 9
AK1 9
A R1 9
A R2 0

P EG_TX4
P EG_TX#4
P EG_R X5
P EG_R X#5

PEX_TS TCLK_O UT
PEX_TS TCLK_O UT

PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ

PEX_R EFCLK
PEX_R EFCLK

MX 25L512 1EMC-20G
PE X_V DD

AG 25
AG 26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK1 8
AK2 0
AK2 3
AK2 6
AL16

C8 5

C 78

C 98

C65

0. 1u_10V _X7R _04

0. 1u_10 V_X7R _04

1u_ 6.3 V_X5R _04

1u_6. 3V_ X5R _04 10u _6. 3V_X 5R_0 6

C 124
C 139

0. 22u_10V _X5R _04
0. 22u_10V _X5R _04

PE X_R X7
PE X_R X7#

P LAC E N EAR BG A

I2C H_SD A
AB5

SPDI F_NC

M_S TRA P_R EF 0 N9
40. 2K _1%_04
40. 2K _1%_04 M_S TRA P_R EF 1 M9

R 64
R 66

16 mi l
GF 108
GT 21X

P EX_SVDD _3V3
PEX_SVD D_3V3_NC
PEX_S VDD_3V 3

AG 19
F7

W5
W7
V7

VG A_S TRA P0
VG A_S TRA P1
VG A_S TRA P2

BU FRS T
PGOOD _OU T
MULT _
I STR AP_REF _
0G ND
MULT _
I STR AP_REF _
1G ND
GND
GND

L5

PEX _VD D_ SVD D

F6

I2C _S CL

R47 4

2. 2K_0 4

G6

I2C _S DA

R47 5

2. 2K_0 4

6-04-25512-B71
6-04-25512-B70
6-04-25512-B72
6-04-25010-490

C EC

3 V3_R UN

A5
A4
C5

AK 14
K9

Sheet 12 of 49
VGA PCI-E
Interface

N 12P -G S Q S

.
C 104

C 55

4. 7u_6. 3V _X5R _06

0. 1u_1 0V_X 7R_0 4

H CB 1005K F-121T2 0

PE X_VD D

PEX_TX 2
PEX_TX 2

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

PEX_R X2
PEX_R X2
PEX_TX 3
PEX_TX 3
PEX_R X3
PEX_R X3

A N2 2
AP2 2

PEX_R X4
PEX_R X4

AL2 2
AK2 2

PEX_TX 5
PEX_TX 5

A R2 2
A R2 3

PEX_R X5
PEX_R X5

NC
NC
NC
NC
NC
NC

PEX_TX 6
PEX_TX 6
PEX_R X6
PEX_R X6

A M2 4
A M2 5

PEX_TX 7
PEX_TX 7

A N2 5
AP2 5

PEX_R X7
PEX_R X7

AL2 5
AK2 5

22u_6 .3 V_X5R _08

PEX_R X1

PEX_TX 4
PEX_TX 4

AP2 3
A N2 3

C5 8

4. 7u_6. 3V _X5R _06

I 2CH_SC L
PL AC E NE AR B ALL S

PEX_R X0
PEX_R X0
PEX_TX 1
PEX_TX 1

STRA P0
STRA P1
STRA P2

C 138

PEX_TX 0
PEX_TX 0

A M2 1
A M2 2

AL2 3
A M2 3

C 32

3V3 _RU N

PEX_R X1

P EG_TX3
P EG_TX#3
P EG_R X4
P EG_R X#4

A M1 8
A M1 9
A N1 9
AP1 9

P EG_TX2
P EG_TX#2
P EG_R X3
P EG_R X#3

AL1 7
A M1 7
AP1 7
A N1 7

P EG_TX1
P EG_TX#1
P EG_R X2
P EG_R X#2

AJ1 7
AJ1 8

0.1 u_16V _Y5 V_04
4

G ND

VD D33
VD D33
VD D33
VD D33
VD D33

A2
A7
AA4
AB4
AB7
AC 5
AD 6
AF6
AG 6
AJ5
AK1 5
AL7
B7
C7
D5
D6
D7
E5
E7
F4
G5
H32
P6
U7
V6
Y4

L3
PLA CE N EA R BA LLS

H C B100 5KF-12 1T20

C 49
4. 7u_6. 3V_ X5R _06

16 mi l

V ID _P LLVD D

C37

C42

0. 1u_10V _X7R _04

4.7 u_6. 3V_X 5R_ 06 0 .1u _10V_ X7R _04

C 47

C 38
0. 1u_ 10V_X 7R_ 04
U46D
14/ 16XTA L
_P L

L4

12 mi l
C 41

HC B1 005K F-121T20

SP _PLLV DD

AE9
A D9
AF9

C 45

PLLVD D
VI D_PLLVD D
SP _
P LLVDD

4 .7u _6. 3V_X5 R_0 6 0. 1u_ 10V_X 7R_ 04

P LAC E N EAR BA LLS
X _SSI N

D2

R47 7

XT AL_SSN
I

B1

XT AL_OUT BUFF

XT AL_IN

XT AL_OUT

D1

X_O U TBU FF

B2
R 476

10K_0 4

N 12P- G S QS
1 0K_04

J10
J11
J12
J13
J9

X1 1
XTAL_ N
I
19

3V 3_R UN

C4 8

C35

C 31

0. 1u_10 V_X7R _04

0. 1u_10V _X7R _04

0.1 u_10V _X7R _04

4 .7u _6. 3V_X5 R_0 6 1u _6. 3V_X5 R_0 4

H SX84 0GA _27MH Z
2

XTA L_O UT

XTAL _IN
C 566

N1 2P -G S

3V 3_R UN
C6 4

1

C 567

11/9
2 0p_50V _N PO _04

20p_ 50V_N PO _04

C 59

PEX_TX 8
PEX_TX 8

R 35

*20K_1 %_ 04

VG A_R OM_S I

R 472

20K_1 %_ 04

R 450

*4.9 9K_1%_0 4

VG A_R OM_S O

R 449

10 K_04

34. 8K_1 %_ 04

VG A_R OM_S CLK

R 473

*34. 8K _1%_04

VG A_S TRA P0

R 42

*4. 99K _1%_04

P LAC E N EAR BA LLS
A R2 5
A R2 6
AL2 6
A M2 6
AP2 6
A N2 6
A M2 7
A M2 8
A N2 8
AP2 8
AL2 8
AK2 8
A R2 8
A R2 9

A M2 9
A M3 0
A N3 1
AP3 1
A M3 1
A M3 2
A R3 1
A R3 2

R 36

PEX_TX 9
PEX_TX 9

VDD _SENS E
VDD _SENS E
VDD _SENS E
GND _SENS E
GND _SENS E
GND _SENS E

PEX_R X9
PEX_R X9

D35
P7
AD 20
AD 19
R7
E35

R 41
PS 1_VD D _SE NS E
PS 1_G ND _SE NS E

PS1 _VD D_ SEN SE 41
PS1 _GN D _SE NS E 41

45 .3K _1%_04

3. 3V

PEX_TX 10
PEX_TX 10

R 56

*34. 8K_1%_0 4

VG A_S TRA P1

R 55

34 .8K _1%_04

R 54

*10K_0 4

VG A_S TRA P2

R 53

24 .9K _1%_04

3V3 _RU N
Q4
A O34 09
S
D

C 46

PEX_R X10
PEX_R X10

C 39
dGP U_ PWR _EN _#2

10 u_10V _Y5 V_08

PEX _VD D

P EX_PLLVDD

AG 14

L7

P EX_P LLV DD

PEX_R X11
PEX_R X11

C3 4
0 .02 2u_16V _X7R _04

1 6m il

PEX_TX 11
PEX_TX 11

C 72

C 96

H C B100 5KF- 121 T20
C 70

1u _6. 3V_X5 R_0 4

4. 7u_6 .3V _X5R _06

10/26
R 48

0. 1u_1 6V_Y 5V_ 04

PEX_TX 12
PEX_TX 12

PLA CE NE AR B ALLS

PEX_R X12
PEX_R X12

100 K_04

3. 3VS

P LAC E N EAR BG A

1u->0.1u C990525

PEX_TX 13
PEX_TX 13

10/28

4. 7u_6. 3V_ X5R _06

R 37

.

1K_ 04
dG PU _PW R_E N_ #1
#

AK2 9
AL2 9
AP2 9
A N2 9

PEX_R X8
PEX_R X8

R49

PR 279
200_1 %_ 04

PEX_R X13
PEX_R X13
PEX_TX 14
PEX_TX 14
PEX_R X14
PEX_R X14

Q5B
dGPU _PWR _E N_# 0

RFU

G F108
P EX_PLL_HVD D_NC
PEX_TE RMP

A N3 2
AP3 2

PEX_TX 15

A R3 4
AP3 4

PEX_R X15
PEX_R X15

D

10K_0 4

G T21X

D

5G

AG 20
AG 21

PE X_TE RMP

R 82

2. 49K _1%_04

GPU _TES TMOD E

R 507

10 K_04

22, 34, 37 d GP U_P WR_ EN #

S
D MN 601D WK- 7

dGPU _PWR _EN #

PQ 73
MT N70 02ZH S3

G

R 58
1M_04

2G
S

Q 5A

DMN6 01D WK-7

PEX_TX 15
AP3 5
TESTMOD E

N12 P-GS Q S

16, 41 3V3 _RU N
13, 37 PE X_VD D
2, 3,8 ,11 ,16 ,18 ,19 ,20 ,22 ,23 ,24 ,2 5,2 7,2 8,2 9,3 0,3 3,3 5,3 7,3 8,3 9 3. 3V
3, 6, 9, 10, 11, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 39 3. 3VS

VGA PCI-E Interface B - 13

B.Schematic Diagrams

Q 39
MTN 7002Z HS 3

PEX_C LKREQ

1 00K_0 4
0
* _04

C56 9

SI
SO
SCK

3

G

R 63

5
2
6

8

VC C

D

R67
3 V3_R UN

PEX_R ST

V GA _R OM_SI
V GA _R OM_SO
V GA _R OM_SC LK

4

3 ,22 ,28 PLT _RS T#

19 P EG _CL KR EQ #

A M1 6

D3
C4
D4

U4 2
HO D
L
WP
CS

S

P ER STB #

V GA _R OM_C S#

RO M_C S
RO M_SI
RO M_SO
RO M_SC LK

2 2 00 m A

3
1

G

4

C3

6

dGP U_ RS T#

10K_ 04

.

34

U 46
K
3/ 16MISC 2
1
J26
B BA
I S N_NC
J25
B BA
I S P_NC

1

1 u_6. 3V_X 5R_ 04

1

P LAC E N EAR BG A

.

C 69
U5
MC 74VH C 1G08 DF T2G

PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ
PE X_IOV DDQ

AG 11
AG 12
AG 13
AG 15
AG 16
AG 17
AG 18
AG 22
AG 23
AG 24

7

3V 3_R UN

Schematic Diagrams

VGA Frame Buffer Interface
Frame Buf fer Interface
U 46B

U 46C
3/16 FBB

F BA_ D0
F BA_ D1
F BA_ D2
F BA_ D3
F BA_ D4
F BA_ D5
F BA_ D6
F BA_ D7
F BA_ D8
F BA_ D9
F BA_ D10
F BA_ D11
F BA_ D12
F BA_ D13
F BA_ D14
F BA_ D15
F BA_ D16
F BA_ D17

F BA_ D21
F BA_ D22
F BA_ D23
F BA_ D24
F BA_ D25
F BA_ D26
F BA_ D27
F BA_ D28
F BA_ D29
F BA_ D30
F BA_ D31
F BA_ D32
F BA_ D33

Sheet 13 of 49
VGA Frame Buffer
Interface

F BA_ D34
F BA_ D35
F BA_
F BA_
F BA_
F BA_
F BA_
F BA_

D36
D37
D38
D39
D40
D41

F BA_ D42
F BA_ D43
F BA_ D44
F BA_ D45
F BA_ D46
F BA_ D47
F BA_ D48
F BA_ D49
F BA_ D50
F BA_ D51
F BA_ D52
F BA_ D53
F BA_ D54
F BA_ D55
F BA_ D56
F BA_ D57
F BA_ D58
F BA_ D59
F BA_ D60
F BA_ D61
F BA_ D62
F BA_ D63
1 4 F BAD QM[ 7: 0]

F BVDD Q
F BVDD Q

N 34
N 35
P35
P33
P34

FBA_D2
FBA_D3
FBA_D4

F BVDD Q
F BVDD Q
F BVDD Q

FBA_D5
FBA_D6

F BVDD Q
F BVDD Q

K35
K33
K34
H 33
G 34
G 33
E34
E33
G 31
F30
G 30

F BAD QM2
F BAD QM3
F BAD QM4
F BAD QM5
F BAD QM6
F BAD QM7

FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12

F BVDD Q
F BVDD Q
F BVDD Q
F BVDD Q
F BVDD Q
F BVDD Q

FBA_D13
FBA_D14

F BVDD Q
F BVDD Q

FBA_D15
FBA_D16
FBA_D17

F BVDD Q
F BVDD Q
F BVDD Q

C 131

C 130

C1 32

0. 1u_10 V_X7 R_0 4

0. 1u_ 10V_ X7R _04

0 .1u _10V _X7R _04

0. 1u_10 V_X7 R_0 4

F BC _D 3
F BC _D 4
F BC _D 5
F BC _D 6
F BC _D 7
F BC _D 8
F BC _D 9
F BC _D 10

PLA CE U N DE R B GA

F BC _D 11
F BC _D 12
F BC _D 13

G 17
G 18
G 22
G8
G9
H 29
J 14
J 15

F BVDD Q
F BVDD Q
F BVDD Q

J 16
J 17

K32
H 30
K31

FBA_D21
FBA_D22

F BVDD Q
F BVDD Q

J 20
J 21
J 22

L31
L30

FBA_D23
FBA_D24
FBA_D25

F BVDD Q
F BVDD Q
F BVDD Q

J 23
J 24

M32
N 30
M30

FBA_D26
FBA_D27
FBA_D28

F BVDD Q

J 29

F BC _D 14
F BC _D 15

C5 3

C 79

1u_6 .3V _X5R _06

4 .7 u_6. 3V_ X5R _06

F BC _D 16
F BC _D 17
F BC _D 18
F BC _D 19
F BC _D 20
F BC _D 21
F BC _D 22
F BC _D 23

PLA CE N E AR B GA

F BC _D 24
F BC _D 25
F BC _D 26

FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45

D 30
E29
B29

FBB_D46
FBB_D47

C 31
C 29

FBB_D48
FBB_D49
FBB_D50

B31
C 32
B32

FBB_D51
FBB_D52
FBB_D53

B35
B34
A29

FBB_D54
FBB_D55

B28
A28

FBB_D56
FBB_D57
FBB_D58

FBA_D42
FBA_D43
FBA_D44

A K32
A J30
AH 30

FBA_D45
FBA_D46

AH 33
AH 35

FBA_D47
FBA_D48
FBA_D49

AH 34
AH 32
A J33

FBA_D50
FBA_D51
FBA_D52

A L35
AM34
AM35

FBA_D53
FBA_D54

A F33
A E32

FBA_D55
FBA_D56
FBA_D57

A F34
A E35
A E34
A E33
A B32
AC 35

FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

P32
H 34
J30
P30
A F32
A L32
A L34
A F35

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FB AD QS _WP 6 A J34
FB AD QS _WP 7 AC 33
FB AD QS_R N[ 7: 0]

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

F BC _D 43
F BC _D 44

FBA _CMD2
FBA _CMD0
FBA _CMD10
FBA _CMD26
FBA _CMD14
FBA _CMD7
FBA _CMD1
FBA _CMD22
FBA _CMD20
FBA _CMD24
FBA _CMD18
FBA _CMD9
FBA _CMD29
FBA _CMD8
FBA _CMD27
FBA _CMD15
FBA _CMD11
FBA _CMD16
FBA _CMD28
FBA _CMD3
FBA _CMD17
FBA _CMD5
FBA _CMD4
FBA _CMD21
FBA _CMD6
FBA _CMD13
FBA _CMD19
FBA _CMD12
FBA _CMD30
NA
/

FB A_CMD3
FB A_CMD4
FB A_CMD5

T 35
U 33
W 32
W 33
W 31

FB A_CMD6
FB A_CMD7
FB A_CMD8
FB A_CMD9
FB A_CMD10

W 34
U 34
U 35

FB A_CMD11
FB A_CMD12
FB A_CMD13

U 32
T 34

FB A_CMD14
FB A_CMD15

T 33
W 30
A B30

FB A_CMD16
FB A_CMD17
FB A_CMD18

A A30
A B31
A A32

FB A_CMD19
FB A_CMD20
FB A_CMD21

A B33
Y 32

FB A_CMD22
FB A_CMD23

Y 33
A B34
A B35

FB A_CMD24
FB A_CMD25
FB A_CMD26

Y 35
W 35
Y 34

H 31
N 32

FBA_DQS_RN 1
FBA_DQS_RN 2
FBA_DQS_RN 3
FBA_DQS_RN 4
FBA_DQS_RN 5

FB AD QS _R N7 AC 34

F BC _D 53
F BC _D 54
F BC _D 55

FB A_C MD 3
FB A_C MD 4
FB A_C MD 5

F BC _D 56
F BC _D 57
F BC _D 58

FB A_C MD 6
FB A_C MD 7

F BC _D 59
F BC _D 60

FB A_C MD 8
FB A_C MD 9
FB A_C MD 10

F BC _D 61
F BC _D 62
F BC _D 63
15
FB A_O DT _L
FB A_O DT _H
FB A_C KE _L

FB A_C MD 14
FB A_C MD 15
FB A_C MD 16
FB A_C MD 17
FB A_C MD 18

FB A_C KE _H
FB A_R ST#

FB A_C MD0

R93
FB A_C MD19 R98
FB A_C MD3 R11 2

10K _04
10K _04
10K _04

FB A_C MD16 R99
FB A_C MD20 R52 7

10K _04
10K _04

FB CD QM0
FB CD QM1
FB CD QM2
FB CD QM3
FB CD QM4
FB CD QM5
FB CD QM6
FB CD QM7

FB A_C MD 30
FB A_C MD 31

A16
D 10
F11
D 15
D 27
D 34
A34
D 28

FB CD QS_W P[ 7: 0]
FB CD QS_WP 0 C 14
A10
FB CD QS_WP 1
FB CD QS_WP 2 E10
FB CD QS_WP 3 D 14
E26
FB CD QS_WP 4
FB CD QS_WP 5 D 32
FB CD QS_WP 6 A32

FB A_C MD 24
FB A_C MD 25
FB A_C MD 26

W 29
Y 29

FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

15 FB CD QS_WP [ 7:0 ]

FB A_C MD 22
FB A_C MD 23

FB A_CMD30
FB A_CMD31

B25
A25

FBB_D59
FBB_D60
FBB_D61

FBC D QM[ 7: 0]

FB A_C MD 19
FB A_C MD 20
FB A_C MD 21

Y 31
Y 30

C 28
C 26
D 25

FB CD QM[ 7: 0]

FB A_C MD 11
FB A_C MD 12
FB A_C MD 13

FB A_C MD 27
FB A_C MD 28
FB A_C MD 29

C 99

C1 33

0. 1u_10 V_X7 R_0 4

0. 1u_ 10V_ X7R _04

0 .1 u_10V _X7R _04

0. 1u_10 V_X7 R_0 4

W 27
Y 27

C1 05

C 11 0

1u_6 .3V _X5R _06

4 .7 u_6. 3V_ X5R _06

P LAC E N EA R B GA

FBC _C MD[ 31: 0]

FB C_C MD1
FB C_C MD1 7
FB C_C MD3 1
GT21X
FB B_CMD25
FB B_CMD23
FB B_CMD2
FB B_CMD0
FB B_CMD10
FB B_CMD26
FB B_CMD14
FB B_CMD7
FB B_CMD1
FB B_CMD22
FB B_CMD20
FB B_CMD24
FB B_CMD18
FB B_CMD9
FB B_CMD29
FB B_CMD8
FB B_CMD27
FB B_CMD15
FB B_CMD11
FB B_CMD16
FB B_CMD28
FB B_CMD3
FB B_CMD17
FB B_CMD5

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6

FB B_CMD4
FB B_CMD21
FB B_CMD6
FB B_CMD13
FB B_CMD19
FB B_CMD12
FB B_CMD30
N /A

UNUSED NTES

GF 108
FB B_CMD0
FB B_CMD1

F 18
E 19

FB B_CMD2
FB B_CMD3

D 18
C 17
F 19

FB B_CMD4
FB B_CMD5
FB B_CMD6

C 19
B 17
E 20
B 19
D 20

FB B_CMD7
FB B_CMD8
FB B_CMD9
F BB_CMD10
F BB_CMD11

A 19
D 19
C 20

F BB_CMD12
F BB_CMD13
F BB_CMD14

F 20
B 20

F BB_CMD15
F BB_CMD16

G 21
F 22
F 24

F BB_CMD17
F BB_CMD18
F BB_CMD19

F 23
C 25
C 23

FB C_C MD0
FB C_C MD1
FB C_C MD2
FB C_C MD3
FB C_C MD4
FB C_C MD5
FB C_C MD6
FB C_C MD7
FB C_C MD8
FB C_C MD9
FB C_C MD1 0
FB C_C MD1 1

F BA_ OD T_L
F BA_ OD T_H
F BA_ CK E_L

FB C_C MD1 2
FB C_C MD1 3
FB C_C MD1 4

F BA_ CK E_H
F BA_ RS T#

FB C_C MD1 5
FB C_C MD1 6

F BC _C MD 0 R 75
F BC _C MD 19 R 83
F BC _C MD 3 R 73
F BC _C MD 16
R 88
F BC _C MD 20 R 84

FB C_C MD1 7
FB C_C MD1 8
FB C_C MD1 9
FB C_C MD2 0
FB C_C MD2 1
FB C_C MD2 2

F BB_CMD20
F BB_CMD21
F BB_CMD22

F 21
E 22

F BB_CMD23
F BB_CMD24

D 21
A 23
D 22

F BB_CMD25
F BB_CMD26
F BB_CMD27

B 23
C 22
B 22

F BB_CMD28
F BB_CMD29
F BB_CMD30

A 22
A 20

FB C_C MD2 8
FB C_C MD2 9
FB C_C MD3 0

F BB_CMD31

G 20

FB C_C MD3 1

FB C_C MD2 3
FB C_C MD2 4
FB C_C MD2 5
FB C_C MD2 6
FB C_C MD2 7

FB CD QS_WP 7

B26

FBB_DQS_WP7

FB CD QS_R N 0
FB CD QS_R N 1

B14
B10
D9

FBB_DQS_RN 0
FBB_DQS_RN 1

E14
F26

FBB_DQS_RN 2
FBB_DQS_RN 3
FBB_DQS_RN 4

FB B_CLK0
FB B_CLK0
FB B_CLK1

D 17
D 23

FB C_C LK 0
FB C_C LK 0#
FB C_C LK 1

FB C_ CLK 0 1 5
FB C_ CLK 0# 15

FB CD QS_R N 5 D 31
FB CD QS_R N 6 A31
FB CD QS_R N 7 A26

FBB_DQS_RN 5
FBB_DQS_RN 6

FB B_CLK1

E 23

FB C_C LK 1#

FB C_ CLK 1 1 5
FB C_ CLK 1# 15

F BB_DE BUG0_
C AS2
FB B_DEBU G1

G 19
G 16

FB CD QS_R N [7 0
: ]

F BC _C MD [ 31: 0] 15

15 FB CD Q S_R N [7: 0]
T 32
T 31
A C3 1

FB A_CLK0
FB A_CLK0

FBA_DQS_RN 0

FB AD QS _R N4 AD 32
FB AD QS _R N5 A J31
FB AD QS _R N6 A J35

F BC _D 48
F BC _D 49
F BC _D 50

FB A_C MD 0
FB A_C MD 1
FB A_C MD 2

FB A_CMD27
FB A_CMD28
FB A_CMD29

14 FB AD QS _R N[ 7: 0]
L35
G 35

F BC _D 45
F BC _D 46
F BC _D 47

F BC _D 51
F BC _D 52
V 30
U 31
V 32

FBB_D22
FBB_D23

E31
C 33
F29

AM33
A L33
A K30

FB A_CMD1
FB A_CMD2

D 11
E11
D 12

F32
D 33

AN 33
A L31

FBA_D39
FBA_D40
FBA_D41

FB A_CMD0

FBB_D19
FBB_D20
FBB_D21

FBB_D35
FBB_D36
FBB_D37

FBA_D37
FBA_D38

FBA _CMD25
FBA _CMD23

F12
D8

D 24
E25
E32

A E30
AC 32
AD 30

F BVDD Q
F BVDD Q
F BVDD Q

C 141

P LAC E U N DE R BGA

FBB_D14
FBB_D15

FBB_D32
FBB_D33
FBB_D34

F BC _D 37
F BC _D 38
F BC _D 39
F BC _D 40
F BC _D 41
F BC _D 42

FBV D DQ

C1 36

FBB_D16
FBB_D17
FBB_D18

FBB_D30
FBB_D31

F BC _D 35
F BC _D 36

UNUSED NTES

FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13

E28
D 26
F25

FBA_D34
FBA_D35
FBA_D36

FB A_C MD 17
FB A_C MD 31

F BVDD Q
F BVDD Q

FBB_D27
FBB_D28
FBB_D29

AH 31
A F31
A F30

FB A_C MD 1

B8
A8
E8
F8
F10
F9

FBB_D6
FBB_D7

F27
F28

F BC _D 32
F BC _D 33
F BC _D 34

U 30

C 10
C8

F BVDD Q
F BVDD Q
F BVDD Q

F16
F17
D 29

F BC _D 30
F BC _D 31

GF 10
8

B11
C 11
A11

F BVDD Q
F BVDD Q
F BVDD Q

FBB_D3
FBB_D4
FBB_D5

FBB_D24
FBB_D25
FBB_D26

FBA_D31
FBA_D32
FBA_D33

GT21X

C 16
B16
A17
D 16
C 13

FBB_D0
FBB_D1
FBB_D2

F14
F15
E16

FBA_D29
FBA_D30

F BA _C MD [ 31: 0] 14

D 13
A13
A14

E13
F13

P31
R 32
R 30

FBA _C MD [ 31: 0]

B13

F BC _D 27
F BC _D 28
F BC _D 29

AG 30
AG 32

L34
FB AD QS _WP 0
FB AD QS _WP 1 H 35
FB AD QS _WP 2 J32
N 31
FB AD QS _WP 3
FB AD QS _WP 4 A E31
FB AD QS _WP 5 A J32

FB AD QS _R N0

C1 34

A J28
B 18
E 21

FBA_D18
FBA_D19
FBA_D20

FB AD QS_WP [7 0
:]

FB AD QS _R N1
FB AD QS _R N2
FB AD QS _R N3

FB C_ D[ 63: 0]
F BC _D 0
F BC _D 1
F BC _D 2

G 32
K30

FB AD QM[ 7: 0]
F BAD QM0
F BAD QM1

14 FB AD QS _WP [7: 0]

FBA_D0
FBA_D1

FB C_ D[ 63: 0]

FB A_CLK1
FB A_CLK1

A C3 0

FB A_C LK0
FB A_C LK0 #

F BA _CL K0 14

FB A_C LK1
FB A_C LK1 #

F BA _CL K0# 14
F BA _CL K1 14
F BA _CL K1# 14

FB CD QS_R N 2
FB CD QS_R N 3
FB CD QS_R N 4

FBA_DQS_RN 6
FBA_DQS_RN 7

E 17

FBB_DQS_RN 7

P29
FBA_WCK0
FBA_WCK0
FBA_WCK1
FBA_WCK1
FBA_WCK2

AD 29
A E29

FBA_WCK2
FBA_WCK3
FBA_WCK3

F BA_DE BUG 0_
C AS2

T 30

FB A_ DE BU G0

FBA _DEBU G1

T 29

FB A_ DE BU G1

R 97
R 92

*6 0.4 _04
*1 0K_0 4

F B V DD Q

G 14
G 15

FBB_WCK0
FBB_WCK0

G 11
G 12
G 27

FBB_WCK1
FBB_WCK1

G 28
G 24

FBB_WCK2
FBB_WCK2
FBB_WCK3

G 25
PLA CE N EA R B GA C LO SE TO C AP S

P LAC E N EA R BA LLS

GT 21X
R FU
R FU
G F108
F B_V RE F_TP

J27

FB_VRE F_NC

G T21X

GF108
F B_DLLAVD D
FB_PLLAVD D

L8

*6 0. 4_04

R 76

*1 0K_0 4

FB _CA L_P D_V D DQ

R 90

4 0. 2_1%_04

FB _CA L_P U_GN D

R 96

4 0. 2_1%_04

FB _CA L_TE RM_GN D R 91

6 0. 4_1%_04

C1 37

C 143

0 .1 u_10V _X7R _04

4. 7u_6. 3V _X5R _06

FBB_WCK3

4. 7u_ 6.3 V_X5 R_0 6
F B_CAL_PD _VDD Q
FB_CA _
LP U_GN D

FB_V REF

FB_CA L_TERM_GN D
L6

*HC B1 005K F-121T2 0

.

C90

C84

0.1 u_10V _X7R _04

4. 7u_6. 3V _X5R _06

PE X_VD D
N 12P - GS QS

12, 37 PEX _VD D
14, 15, 37 FBV DD Q

B - 14 VGA Frame Buffer Interface

F B V D DQ

HC B10 05KF - 121T20

C 135

F B_D P LLAV DD
N 12P - GS QS

R 81

.

FB A_P LLA VD D_G P U

FB_PLLAVD D

F BC _DE BU G 0
F BC _DE BU G 1

P EX_V DD

1 6m i l

A G2 7
A F27

F B_DLLAVD D

M 27 L27 K2 7

R 29
L29
M29
AG 29
AH 29

J18
J19

B.Schematic Diagrams

F BA_ D18
F BA_ D19
F BA_ D20

L32
N 33
L33

15

FBV D DQ

AE 27
ADAC
2727
ABAB
29
AA
27AA
31AA
2927

FB A_D [ 63: 0]

V3 4
V2V2
9 7
U 29
U 27
T2 7
R 27
P2N727

2/16 FBA
FB A_D [ 63: 0]
14

F BV D D Q

1 0K_0 4
1 0K_0 4
1 0K_0 4
1 0K_0 4
1 0K_0 4

Schematic Diagrams

VGA Frame Buffer A
Frame Buffer Partition A

F B A_ CMD [ 31 :0 ]

1 3 FB A_ C MD [ 31 : 0]

F BA _D [ 63: 0]
13

F BA _D [ 63: 0 ]

F BV D D Q
F BA D QM[ 7: 0 ]

F BV D D Q

13 F BA D Q M[ 7 :0 ]
F BA D QS _W P[ 7: 0 ]
1 3 FB AD Q S _WP [ 7: 0]

C 210

C6 31

C 6 66

C 24 1

C 234

C 244

C 2 15

C 65 1

0. 1u _10 V_X 7R _0 4

0. 1u_ 10V _X 7R _04

0 .1 u_1 0V _X7 R_ 04

0. 1 u_1 0V_ X7R _ 04

0. 1u _10 V_ X7R _0 4

1u_ 6. 3V _X5 R_ 04

1 u_6 .3 V_ X5R _ 04

1u _6. 3 V_X 5R _0 4

C 243

C2 40

C 64 9

C 66 5

C 187

C1 81

C 18 0

C 63 0

0. 1u _10V _X 7R _04

0. 1u_ 10V _X7 R _04

0 .1 u_1 0V _X7 R_ 04

0. 1u _10 V_ X7R _0 4

0. 1u _10V _X 7R _0 4

1u_ 6. 3V _X5R _ 04

1 u_6 .3 V_ X5R _0 4

1u _6. 3V _X 5R _04

C 664

C6 53

C 66 2

C 21 3

C 218

C2 00

C 18 8

C 63 7

0. 1u _10V _X 7R _04

0. 1u_ 10V _X7 R _04

0 .1 u_1 0V _X7 R_ 04

0. 1u _10 V_ X7R _0 4

0. 1u _10V _X 7R _0 4

1u_ 6. 3V _X5R _ 04

1 u_6 .3 V_ X5R _0 4

1u _6. 3V _X 5R _04

F BA D QS _R N [ 7: 0]
1 3 FB AD Q S _R N [7 : 0]
F B VD D Q

C6 48

C 23 8

C 23 2

C 217

1u_6 . 3V_ X5R _ 04

1 u_6 .3 V_ X5R _0 4

1u _6. 3V _X 5R _04

1u_ 6. 3V _X5 R _04

F BV D D Q

F BV D D Q

C 625

C2 45

C 2 46

C 63 4

C 658

C 638

C 6 67

C 20 9

0. 1u _10 V_X 7R _0 4

0. 1u_ 10V _X 7R _04

0 .1 u_1 0V _X7 R_ 04

0. 1 u_1 0V_ X7R _ 04

0. 1u _10 V_ X7R _0 4

1u_ 6. 3V _X5 R_ 04

1 u_6 .3 V_ X5R _ 04

1u _6. 3 V_X 5R _0 4

U9

MIR R OR MO DE C OMMAN D MAP PIN G

U 51
F BV D D Q

J 3
K3

F BA _C MD 28

L3
L2

F BA _C MD 2

F BA _C MD 7
F BA _C MD 10
F BA _C MD 24
F BA _C MD 6
F BA _C MD 22
F BA _C MD 26
F BA _C MD 5
F BA _C MD 21

P3
N2
P8
P2
R8
R2

F BA _C MD 8
F BA _C MD 4

T8
R3

F BA _C MD 25

L7
R7
N7

F BA _C MD 23
F BA _C MD 9

10/29

N3
P7

F BA _C MD 12

T3
T7
M7

RAS
CAS

V DD
V DD

WE

V DD

CS

V DD
V DD

A0
A1
A2
A3

V DD
V DD
V DD

FB VD D Q

B2
D9

F BA _C M D 11
F BA _C MD 15

J3
K3

G7
K2

F BA _C MD 28

L3
L2

F BA _C MD 2

K8
N1
N9
R1

F BA _C MD 7
F BA _C MD 10

R9

F BA _C MD 24

V DD

F BA _C MD 6
F BA _C MD 22

A1

A4

V DDQ

A5
A6

V DDQ
V DDQ

A7

V DDQ

A8
A9

V DDQ
V DDQ

A 10
A 11
A 12

V DDQ
V DDQ
V DDQ

A8
C1

F BA _C MD 26

N3
P7
P3
N2
P8
P2
R8

C9

F BA _C MD 5
F BA _C MD 21

D2
E9

F BA _C MD 8
F BA _C MD 4

T8
R3

F1
H2
H9

F BA _C MD 25

L7
R7
N7

F BA _C MD 23
F BA _C MD 9

10 /29

A 13

F BA _C MD 12

R2

T3
T7
M7

A 14
A 15

RAS
CAS

V DD
V DD

WE

V DD

CS

V DD
V DD

A0
A1
A2
A3

V DD
V DD
V DD

M2

F BA _C MD 13

N8
M3

F BA _C MD 27

13
13

FB A_ CL K0
FB A_ CL K0 #

F BA _C MD 3

K9

F BA _C LK 0

J 7

F BA _C LK 0#

K7

VS S
B A0

VS S

B A1
B A2

VS S
VS S

CKE

VS S
VS S
VS S

CK

VS S

CK

VS S
VS S

J 1
J 9
L1
L9

F BA _C MD 20
F BA _C MD 0
F BA _Z Q0

VS S
NC1
NC2

VS S

NC3
NC4

VS S Q
VS S Q
VS S Q
VS S Q
VS S Q

T2
R E SE T

VS S Q

ODT

VS S Q
VS S Q

K1

F BA _C MD 29

M2

E1
G8

F BA _C MD 13

N8
M3

F BA _C MD 27

J2
J8
M1
M9

FB A_ CL K0

P1
P9
T1
T9

A4

VD D Q
VD D Q
VD D Q

A7

VD D Q

A8
A9

VD D Q
VD D Q

A 10
A 11
A 12

VD D Q
VD D Q
VD D Q

2 43_ 1%_0 4

F BA _C MD 3

K9

F BA _C L K0

J7

F BA _C L K0#

K7

1 60_ 1%_ 04
B1
B9

J9
L1
L9

FB A_ CL K0 #

D1
D8
E2
E8

FB VD D Q

F9
G1

F BA _C MD 20
F BA _C MD 0

V SS
BA0

V SS

BA1
BA2

V SS
V SS

CKE

V SS
V SS
V SS

CK

V SS

CK

V SS
V SS

R1 41

FB A_ ZQ 1

V SS
NC1
NC2

V SS

NC3
NC4

V SS Q
V SS Q
V SS Q
V SS Q
V SS Q

T2
R E S ET

V SS Q

ODT

V SS Q
V SS Q

K1

G9

H1
M8

A8
C1
C9
D2
E9

B3

A2 A1
A11 A9

CMD26

A5

CMD7
CMD8

CMD7
CMD15

A0 A12
CAS* CAS*

CMD13

BA1

R 14 0

L3
L2

F BA _C MD 18

A3

CMD4 A9 A1
CMD18
CS0*
CMD29 BA0 BA0
CMD27 BA2 A15
CMD6 A3 BA1

F BA _C MD 10

CMD15

CMD17

CS1*

F BA _C MD 13
F BA _C MD 26

CMD16
CMD17

CMD19
ODT
CMD22 A4 A5

F BA _C MD 22

CMD18
CMD19

CMD12 A13 A14
CMD28 WE* A0
1
CMD10 A1

F BA _C MD 21
F BA _C MD 5

A2

CMD21
CMD22
CMD23

CMD25 A10 WE*
CMD9 A12 A0
CMD1 CS1*
CMD11 RAS* RAS*
CMD0 ODT

CMD26

CMD5

CMD27
CMD28

CMD16
CKE
CMD20 RST RST

CMD29

CMD14 A14 A13

A6

F BA _C MD 9
F BA _C MD 24

P3
N2
P8
P2
R8
R2

F BA _C MD 8
F BA _C MD 23

T8
R3

F BA _C MD 28

L7
R7
N7

F BA _C MD 4
F BA _C MD 7

10/29

N3
P7

F BA _C MD 14

A7

T3
T7
M7

M2

F BA _C MD 6

N8
M3

F BA _C MD 30

F BA _C MD 16

K9

M9

F BA _C LK 1

J7

F BA _C LK 1#

K7

13
13

P1
P9

FB A_ C LK1
FB A_ C LK1 #

T1
T9

V DD
V DD

WE

V DD

CS

V DD
V DD

A0
A1
A2
A3

B1
B9

L1
L9

D1
D8
E2
E8

F BA _C MD 20

F9
G1

V DD
V DD
V DD

F BA _C MD 19

F B A_C MD 11
F B A_C MD 15

J3
K3

G7
K2

F B A_C MD 25

L3
L2

F B A_C MD 18

K8
N1
N9
R1

F B A_C MD 9
F B A_C MD 24

R9

F B A_C MD 10
F B A_C MD 13
F B A_C MD 26

A1

A4

V DDQ
V DDQ
V DDQ

A7

V DDQ

A8
A9

V DDQ
V DDQ

A 10
A 11
A 12

V DDQ
V DDQ
V DDQ

A8
C1

F B A_C MD 22

F BA _Z Q 2

FB A_ D 10
FB A_ D 15
FB A_ D 11

E3
F7
F2
F8
H3
H8
G2
H7

E7
F3
FB AD Q S _WP 1
FB AD Q S _R N 1 G 3

D7
D Q L0

DQ U 0

D Q L1

DQ U 1

D Q L2
D Q L3

DQ U 2
DQ U 3

D Q L4

DQ U 4

F B A_C MD 8
F B A_C MD 23

T8
R3

F B A_C MD 28

L7
R7
N7

F B A_C MD 4
F B A_C MD 7

D Q L5
D Q L6

DQ U 5
DQ U 6

D Q L7

DQ U 7

D ML
D Q SL

D MU
DQS U

D Q SL

DQS U

FB AD Q M1

K4 W1G 1 646 E-H C 11

F BA _D 29
F BA _D 28
F BA _D 30
F BA _D 25
F BA _D 26

B8

F BA _D 27
F BA _D 31

A3

FB A _D 16

F BA _D 24

B7

F BA D Q M2
F BA D Q S_W P2
F BA D Q S_R N 2

T3
T7
M7

VD D
VD D

WE

VD D

CS

VD D
VD D

A0
A1
A2
A3

VD D
VD D
VD D

VS S
B A0

VS S

B A1
B A2

VS S
VS S

CK E

VS S
VS S
VS S

CK

VS S

CK

VS S
VS S
VS S

NC1
NC2

VS S

NC3
NC4

VS S Q
VS S Q
VS S Q
VS S Q
VS S Q

R E SE T

VS S Q

OD T

VS S Q
VS S Q

K1

R1 39

F B A_C MD 29

M2

E1
G8

F B A_C MD 6

N8
M3

F B A_C MD 30

J2
J8
M1
M9

FB A_ C LK1

P1
P9
T1
T9

F B A_C MD 16

K9

F B A_C L K1

J7

F B A_C L K1 #

K7

243_ 1%_ 04

N1
N9
R1
R9
A1

A4

VD D Q
VD D Q
VD D Q

A7

VD D Q

A8
A9

VD D Q
VD D Q

A10
A11
A12

VD D Q
VD D Q
VD D Q

A8
C1

Sheet 14 of 49
VGA Frame Buffer
A

C9
D2
E9
F1
H2
H9

A13
A14
A15
V SS
BA 0

V SS

BA 1
BA 2

V SS
V SS

CK E

V SS
V SS
V SS

CK

V SS

CK

V SS
V SS

J1
160 _1%_ 04

B1
B9

J9
L1
L9

FB A_ C LK1 #

D1
D8
E2
E8

FB VD D Q

F9
G1

F B A_C MD 20
F B A_C MD 19
FB A_ ZQ 3

V SS
NC 1
NC 2

V SS

NC 3
NC 4

V SS Q
V SS Q
V SS Q
V SS Q
V SS Q

T2
RE S ET

V SS Q

OD T

V SS Q
V SS Q

K1

G9

H1
M8

K8

VD D

A5
A6

R1 35

B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

V SS Q

L8
ZQ

R 144

16mli
<500mil
V R EF D Q
V R EF C A

10 /28

G7
K2

A9

B3

VS S Q

L8

B2
D9

16mil
<500mil

1. 1K _1%_ 04

FB A _VR E F1

R 52 2

VR E FD Q
VR E FC A

24 3_1 %_04

C 24 2

H1
M8

F BA _V R EF 1

1 0/28
C 26 9

0 .0 1u_ 16V _X 7R _04

0 .0 1u_ 16V _X 7R _04
1. 1K _1%_ 04

FB A _D 18
FB A _D 23

D3
C7

R2

RA S
CA S

R 143

FB A _D 20
FB A _D 17
FB A _D 21

C8
C2
A7
A2

F B A_C MD 14

10/29

A 14
A 15

0. 0 1u_ 16V _X7 R _04

FB A _D 22
FB A _D 19

C3

P2
R8

F1
H2
H9

1. 1K _1%_ 04

FB A_ D 14
FB A_ D 8
FB A_ D 13

P8

D2
E9

R1 38
0. 0 1u_ 16V _X7 R _04

FB A_ D 12
FB A_ D 9

P3
N2

F B A_C MD 21
F B A_C MD 5

ZQ

C 23 5

N3
P7

C9

A 13

T2

G9

F BA _V RE F 0

FB VD D Q

B2
D9

V DD

A5
A6

J1
J9

H1
M8

RA S
CA S

A9
F BA _C MD 29

16mil
<500m
il
V R EF D Q
VR E FC A

24 3_1 %_04

J3
K3

F BA _C MD 25

CMD13
CMD14

CMD24
CMD25

U 50
F B VD D Q

F BA _C MD 11
F BA _C MD 15

CMD10
CMD11
CMD12

V SS Q

L8

U 10

A4

J2
J8
M1

1. 1K _1%_ 04

C 23 3

CS0*
A7 A6

CMD24
CMD23

CMD6

CMD30 CMD30 A15 BA2
N/ A CMD31

E1
G8

ZQ

FB A_ VR E F0

CMD2
CMD21

CMD4
CMD5

CMD20

F1
H2
H9

A 14
A 15

J1

16m
il
<500mil
V R EF D Q
V R EF C A

R9

A 13

R 1 36

ZQ

R 1 37

N1
N9
R1

A1

A5
A6

CMD2
CMD3

CMD9

K8

A9

B3

VS S Q

L8

G7
K2

V DD

A9
F BA _C MD 29

B2
D9

0-31 32-63
CKE
A8 A8

E3
F7
F2
F8
H3
H8
G2
H7

E7
F3
F BA D QS _W P3
F BA D QS _R N 3 G 3

D7
D QL 0

D Q U0

D QL 1

D Q U1

D QL 2
D QL 3

D Q U2
D Q U3

D QL 4

D Q U4

D QL 5
D QL 6

D Q U5
D Q U6

D QL 7

D Q U7

D ML
D QS L

D MU
DQ S U

D QS L

DQ S U

F BA D QM3

K 4W1 G 164 6E-H C 11

FB A _D 3
FB A _D 6

FB A_ D 37
FB A_ D 33

FB A _D 1
FB A _D 7
FB A _D 2

FB A_ D 39
FB A_ D 32
FB A_ D 36

B8

FB A _D 5
FB A _D 0

FB A_ D 34
FB A_ D 38

A3

FB A _D 4

FB A_ D 35

C3
C8
C2
A7
A2

D3
C7
B7

FB A DQ M0
FB A DQ S _WP 0
FB A DQ S _R N 0

E3
F7
F2
F8
H3
H8
G2
H7

E7
F3
FB AD Q S _WP 4
FB AD Q S _R N 4 G 3

D7
D Q L0

DQ U 0

D Q L1

DQ U 1

D Q L2
D Q L3

DQ U 2
DQ U 3

D Q L4

DQ U 4

D Q L5
D Q L6

DQ U 5
DQ U 6

D Q L7

DQ U 7

D ML
D QS L

D MU
D QS U

D QS L

D QS U

FB AD Q M4

FB A _D 56
FB A _D 59

F BA _D 45
F BA _D 47

FB A _D 58
FB A _D 62
FB A _D 61

F BA _D 42
F BA _D 46
F BA _D 43

B8

FB A _D 57
FB A _D 60

F BA _D 44
F BA _D 40

A3

FB A _D 63

F BA _D 41

C3
C8
C2
A7
A2

D3
C7
B7

E3
F7
F2
F8
H3
H8
G2
H7

E7
F3
F BA D QS _W P5
F BA D QS _R N 5 G 3

F BA D Q M7

D7
DQ L 0

D Q U0

DQ L 1

D Q U1

DQ L 2
DQ L 3

D Q U2
D Q U3

DQ L 4

D Q U4

DQ L 5
DQ L 6

D Q U5
D Q U6

DQ L 7

D Q U7

DML
DQ S L

D MU
D QS U

DQ S L

D QS U

F BA D QM5

F BA D Q S_ WP 7
F BA D Q S_ RN 7

K4 W1 G1 646 E- H C 11

C3
C8
C2
A7
A2

F BA _D 51
F BA _D 52
F BA _D 48
F BA _D 54
F BA _D 49

B8

F BA _D 55
F BA _D 50

A3

F BA _D 53

D3
C7

F BA D Q M6

B7

F BA D Q S_ WP 6
F BA D Q S_ RN 6

K 4W 1G 164 6E -H C 11

1 3, 15, 37 F BV D D Q

VGA Frame Buffer A B - 15

B.Schematic Diagrams

F BA _C M D 11
F BA _C MD 15

GT21x GF108
CMD0 CMD3
CMD1 CMD8

Schematic Diagrams

VGA Frame Buffer C
F B C _C MD[ 3 1: 0]
1 3 FB C _C MD 3
[ 1: 0]

Frame Buffer Partition C

F BC _D [ 63 :0 ]
13

F BC _D [ 63 :0 ]
F BC D Q M[7 : 0]

13 F BC D QM[7 : 0]

F BV D D Q
F BC D Q S_ WP [7 : 0]

F BV D D Q

1 3 F B CD QS _WP [ 7: 0]
1 3 F B C DQS _R N [ 7: 0]

C 5 70

C 30

C 57 8

C 576

C 574

C 54

C 56 8

0 .1 u_1 0V _X7 R _04

0 .1 u_1 0V _X7 R_ 04

0. 1u _10 V_ X7R _ 04

0. 1u _10 V_ X7R _0 4

0. 1u_ 10V _X 7R _0 4

1 u_6 .3 V_ X5R _0 4

1u _6. 3V _X 5R _0 4

F BC D Q S_ R N[ 7 :0 ]
C 155

C 1 52

C 14 7

C 57 2

C 62

C 120

C1 57

0. 1u _10 V_ X7R _0 4

0 . 1u_1 0V _X7 R _04

0 .1 u_1 0V _X7 R_ 04

0. 1 u_10 V_ X7R _ 04

0. 1u _10 V_ X7R _0 4

1u_ 6. 3V _X5 R _04

1u_ 6. 3V _X5 R_ 04

F BV D D Q

F BV D D Q

C 6 05

C 58 6

C 61 0

C 600

C 146

C 59 2

C 15 6

C 68

C 1 60

C 11 6

C 58 5

C 599

C 590

C6 03

0 .1 u_1 0V _X7 R _04

0 .1 u_1 0V _X7 R_ 04

0. 1u _10 V_ X7R _ 04

0. 1u _10 V_ X7R _0 4

0. 1u_ 10V _X 7R _0 4

1 u_6 .3 V_ X5R _0 4

1u _6. 3V _X 5R _0 4

0. 1u _10 V_ X7R _0 4

0 . 1u_1 0V _X7 R _04

0 .1 u_1 0V _X7 R_ 04

0. 1 u_10 V_ X7R _ 04

0. 1u _10 V_ X7R _0 4

1u_ 6. 3V _X5 R _04

1u_ 6. 3V _X5 R_ 04

B.Schematic Diagrams

U4

U 44

U7

FB VD D Q
F BC _C MD 11
F BC _C MD 15

J3
K3

F BC _C MD 28
F BC _C MD 2

L3
L2

F BC _C MD 7
F BC _C MD 10

N3
P7

V DD

CAS
W E
CS

V DD
V DD
V DD
V DD

F BC _C MD 24

Sheet 15 of 49
VGA Frame Buffer
C

F BC _C MD 6
F BC _C MD 22
F BC _C MD 26
F BC _C MD 5

10/29

P3
N2
P8
P2
R8

F BC _C MD 21

R2

F BC _C MD 8
F BC _C MD 4

T8
R3

F BC _C MD 25

L7

F BC _C MD 23
F BC _C MD 9
F BC _C MD 12

R7
N7
T3
T7
M7

F BC _C MD 29

M2

F BC _C MD 13

N8
M3

F BC _C MD 27

F BC _C MD 3
F BC _C L K0
13
13

FB C _C LK 0
FB C _C LK 0#

F BC _C L K0 #

J7
K7

L9

F BC _C MD 0

V DD

A4
A5
A6

VD D Q
VD D Q
VD D Q

A7
A8
A9

VD D Q
VD D Q
VD D Q

A 10

VD D Q

A 11
A 12
A 13

VD D Q
VD D Q

FB C _C M D 11
FB C _C MD 15

D9

L3
L2

N1
N9
R1

FB C _C MD 7
FB C _C MD 10

N3
P7

R9

FB C _C MD 24

A1
A8
C1

FB C _C MD 6
FB C _C MD 22
FB C _C MD 26
FB C _C MD 5

C9

FB C _C MD 21

R2

D2
E9

FB C _C MD 8
FB C _C MD 4

T8
R3

F1

FB C _C MD 25

L7

H2
H9

FB C _C MD 23
FB C _C MD 9
FB C _C MD 12

R7
N7
T3
T7

K8

10/29

V SS
V SS

BA1

V SS

BA2

V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS

NC1
NC2

V SS

NC3

V SS Q

NC4

V SS Q
V SS Q
V SS Q

T2
R E SE T
K1
L8

A9
B3
E1
G8

FB C _C MD 29

M2

FB C _C MD 13

N8
M3

FB C _C MD 27

J2
J8
M1

FB C _C MD 3
FB C _C LK 0

F BC _C L K0

M9

FB C _C LK 0#

P1
P9
T1

16 0_1 %_04
B1

V SS Q
V SS Q
V SS Q
V SS Q
V SS Q

F BC _C L K0#

B9
D1
D8
E2
E8

V R EF D Q
VR E FC A

J7
K7

F BV D D Q

J1
J9
L1
L9

FB C _C MD 20
FB C _C MD 0

V DD
V DD
V DD

A0
A1

F BC _ ZQ1

V DD
V DD
V DD

A2
A3

V DD

A4
A5
A6

V DDQ
V DDQ
V DDQ

A7
A8
A9

V DDQ
V DDQ
V DDQ

A 10

V DDQ

A 11
A 12
A 13

V DDQ
V DDQ

F BC _ CMD 11
F BC _ CMD 15

D9

L3
L2

N1
N9
R1

F BC _ CMD 9
F BC _ CMD 24

N3
P7

R9

F BC _ CMD 10

A1
A8
C1

F BC _ CMD 13
F BC _ CMD 26
F BC _ CMD 22
F BC _ CMD 21

C9

F BC _ CMD 5

R2

D2
E9

F BC _ CMD 8
F BC _ CMD 23

T8
R3

F1

F BC _ CMD 28

L7

H2
H9

F BC _ CMD 4
F BC _ CMD 7
F BC _ CMD 14

R7
N7
T3
T7

K8

10/29

VS S
VS S

B A1

VS S

B A2

VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S

NC1
NC2

VS S

NC3

V SS Q

NC4

V SS Q
V SS Q
V SS Q

T2
R E SE T
K1
L8

A9
B3
E1
G8

N8
M3

13
13

P1
P9

FB C _C LK 1
FB C _C LK 1#

F BC _ CL K1 #

V SS Q
V SS Q
V SS Q
V SS Q
V SS Q

CA S
WE
CS

VD D
VD D
VD D

A0
A1

J7
K7

T9

J1
J9
L1

B9
D1

L9

D8
E2
E8

F BC _ CMD 20

VD D

A4
A5
A6

VD D Q
VD D Q
VD D Q

A7
A8
A9

VD D Q
VD D Q
VD D Q

A 10

VD D Q

A 11
A 12
A 13

VD D Q
VD D Q

F BC _ CMD 19

V SS
V SS

BA1

V SS

BA2

V SS
V SS
V SS

CK E
CK
CK

H1
M8

FB C _V R EF 0
C 277

V SS
V SS
V SS
V SS
V SS

NC1
NC2

V SS

NC3

V SS Q

NC4

V SS Q
V SS Q
V SS Q

R E S ET
K1
L8

F BC _C MD 25
F BC _C MD 18

L3
L2

N1
N9
R1

F BC _C MD 9
F BC _C MD 24

N3
P7

R9

F BC _C MD 10

A1
A8
C1

F BC _C MD 13
F BC _C MD 26
F BC _C MD 22
F BC _C MD 21

C9

F BC _C MD 5

R2

D2
E9

F BC _C MD 8
F BC _C MD 23

T8
R3

F1

F BC _C MD 28

L7

H2
H9

F BC _C MD 4
F BC _C MD 7
F BC _C MD 14

R7
N7
T3
T7

G7
K2
K8

V SS Q
V SS Q
V SS Q
V SS Q
V SS Q

10/29

A9
B3
E1
G8

243 _1%_ 04

FB C _D 14
FB C _D 8
FB C _D 13
FB C _D 11

E3
F7

D QL0

D Q U0

F2
F8
H3

D QL1
D QL2

D Q U1
D Q U2

D QL3

D Q U3

T1

H8

D QL4
D QL5
D QL6
D QL7

D Q U4
D Q U5
D Q U6
D Q U7

D ML
D QS L

D MU
DQS U

D QS L

DQS U

G2
H7

E7
FB C D QM1
FB C D QS _W P1 F 3
FB C D QS _R N 1 G 3

K 4W1 G1646 E- H C 11

F BC _ CL K1 #

B9
D1
D8
E2
E8

J7
K7

F BV D D Q

J1
J9
L1
L9

F BC _C MD 20
F BC _C MD 19

V DD

A4
A5
A6

VD D Q
VD D Q
VD D Q

A7
A8
A9

VD D Q
VD D Q
VD D Q

A 10

VD D Q

A 11
A 12
A 13

VD D Q
VD D Q

R 50 1

F BC _ ZQ 3

G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9

A 14
A 15

B A0

V SS
V SS

B A1

V SS

B A2

V SS
V SS
V SS

CKE
CK
CK

V SS
V SS
V SS
V SS
V SS

NC1
NC2

V SS

NC3

V SS Q

NC4

V SS Q
V SS Q
V SS Q

T2
R E SE T
K1
ODT

16mil
<500mil

V DD
V DD
V DD

A2
A3

K9

F9
G1
G9

L8

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1

V SS Q
V SS Q
V SS Q
V SS Q
V SS Q

B9
D1
D8
E2
E8
F9
G1
G9

16m
il
<500mil

ZQ
1 .1 K_ 1%_0 4

F BC _ VR E F1

R 504
V R EF D Q
VR E FC A

243 _1% _04

C 142

H1
M8

F BC _V R EF 1
C 29 8

0. 01 u_16 V_ X7R _ 04

10/28

0 .0 1u_ 16V _X 7R _04

FB C _D 28
FB C _D 26
FB C _D 29
FB C _D 27
FB C _D 30
FB C _D 24

B8
A3

F BC _ D2 2
F BC _ D1 6

FB C _D 31
FB C _D 25

D3
C7

FB C DQ M2
FB C DQ S _W P2

E7
FB C DQM3
FB C DQS _W P3 F 3

B7

FB C DQ S _R N 2

FB C DQS _R N 3 G3

E3
F7

D Q L0

D QU 0

F2
F8
H3

D Q L1
D Q L2

D QU 1
D QU 2

D Q L3

D QU 3

H8

D Q L4
D Q L5
D Q L6
D Q L7

D QU 4
D QU 5
D QU 6
D QU 7

D ML
D Q SL

D MU
D QS U

D Q SL

D QS U

G2
H7

K4 W1G 1 646 E-H C 11

FB C _D 3

FB C _D 37

FB C _D 7
FB C _D 0
FB C _D 6

FB C _D 35
FB C _D 36
FB C _D 34

FB C _D 1
FB C _D 4

FB C _D 39
FB C _D 33

B8
A3

FB C _D 2
FB C _D 5

FB C _D 38
FB C _D 32

D3
C7

FB C D QM0
FB C D QS _W P0

E7
FB C D QM4
FB C D QS_ WP4 F 3

B7

FB C D QS _R N 0

FB C D QS_ RN 4 G 3

D7
C3
C8
C2
A7
A2

E3
F7

D QL 0

D QU 0

F2
F8
H3

D QL 1
D QL 2

D QU 1
D QU 2

D QL 3

D QU 3

H8

D QL 4
D QL 5
D QL 6
D QL 7

D QU 4
D QU 5
D QU 6
D QU 7

D ML
D QS L

D MU
D QS U

D QS L

D QS U

G2
H7

F B C_ D 59

FB C _D 44

F B C_ D 62
F B C_ D 57
F B C_ D 61

FB C _D 46
FB C _D 40
FB C _D 45

F B C_ D 58
F B C_ D 63

FB C _D 42
FB C _D 47

B8
A3

F B C_ D 56
F B C_ D 60

FB C _D 41
FB C _D 43

D3
C7

FB C D QM7
FB C D QS _W P7

E7
FB C D QM5
FB C D QS _W P5 F 3

B7

FB C D QS _R N 7

FB C D QS _R N 5 G3

D7
C3
C8
C2
A7
A2

K 4W1 G164 6E -H C 11

E3
F7

D QL0

D QU0

F2
F8
H3

D QL1
D QL2

D QU1
D QU2

D QL3

D QU3

H8

D QL4
D QL5
D QL6
D QL7

D QU4
D QU5
D QU6
D QU7

D ML
D QS L

D MU
DQ S U

D QS L

DQ S U

G2
H7

K 4W1 G1 646 E- H C 11

13 , 14, 37 F BV D D Q

B - 16 VGA Frame Buffer C

A0
A1

D9

1 .1 K_ 1%_0 4

F BC _ D1 8
F BC _ D1 7

A2

V DD
V DD
V DD

R 10 8
1 60_1 %_0 4

H1
M8

V DD

CAS
WE
CS

R 50 2

F BC _ D2 1
F BC _ D2 3
F BC _ D1 9

C8
C2
A7

N8
M3

T9

0. 01 u_16 V_ X7R _ 04

F BC _ D2 0

D7
C3

M2

F BC _C L K1#

P1
P9

1. 1 K_1 %_0 4

FB C _D 9
FB C _D 12
FB C _D 10

P8
P2
R8

F BC _C MD 6

F BC _C MD 16
F BC _C L K1

F BC _ CL K1

M9

R 48 5
0. 01u _16 V_ X7R _0 4

FB C _D 15

P3
N2

F BC _C MD 29
F BC _C MD 30

J2
J8
M1

ZQ

VR E FD Q
VR E FC A

B2
RAS

V DD

B1

R 95

10/28

J3
K3

M7

BA0

OD T
F BC _ ZQ 2

F BC _C MD 11
F BC _C MD 15

D9

A 14
A 15

T2

F9
G1
G9

VD D
VD D
VD D

A2
A3

K9

16mil
<500mil
V R EF D Q
V R E FC A

VD D

T1

B1

R 484
243 _1%_ 04

M2

F BC _ CMD 6

F BC _ CMD 16
F BC _ CL K1

M9

ZQ

C4 3

F BC _ CMD 29
F BC _ CMD 30

J2
J8
M1

1. 1 K_1 %_0 4

F BC _ VR E F0

P8
P2
R8

FB VD D Q

B2
RA S

VD D

P3
N2

M7

B A0

CK E
CK
CK

J3
K3

F BC _ CMD 25
F BC _ CMD 18

G7
K2

A 14
A 15

OD T
R 60

H1
M8

CA S
WE
CS

K9

F9
G1
G9

16mil
<500mil

R6 9

V DD

R 43

T9

ZQ

243 _1%_ 04

P8
P2
R8

FB V DD Q

B2
RA S

V DD

P3
N2

M7

BA0

CKE
CK
CK

J3
K3

FB C _C MD 28
FB C _C MD 2

G7
K2

A 14
A 15

ODT
F BC _Z Q0

V DD
V DD
V DD

A2
A3

K9

J1
J9
L1

F BC _C MD 20

A0
A1

U 47

F B VD D Q

B2
RAS

D7
C3
C8
C2
A7
A2

F BC _ D4 9
F BC _ D5 3
F BC _ D4 8
F BC _ D5 4
F BC _ D5 1
F BC _ D5 5

B8
A3

F BC _ D5 0
F BC _ D5 2

D3
C7

F BC D Q M6
F BC D Q S_ WP 6

B7

F BC D Q S_ R N 6

Schematic Diagrams

VGA I/O

AJ 8

I F PC _A U X
I F PC _A U X

TXC
TXC

I FP C _L3
I FP C _L3

TXD0
TXD0

I FP C _L2
I FP C _L2

TXD1
TXD1

I FP C _L1
I FP C _L1

TXD2
TXD2

I FP C _L0
I FP C _L0

I FP C _I OV D D

HPDC

IF PC

GP O
I 1

A N3
AP2

9/ 1

A R2
AP1
A M4
A M3
A M5
AL 5

MIOAD0_NC
MIOAD1_NC
MIOAD2_NC
MIOAD3_NC
MIOAD4_NC
MIOAD5_NC
MIOAD6_NC
MIOAD7_NC
MIOAD8_NC
MIOAD9_NC
MIOAD10_NC
MIOAD11_NC
MIOAD12_NC
MIOAD13_NC
MIOAD14_NC

R 1 98

0. 1 u_ 1 6V _ Y 5V _ 04

SDA
SCL

C5 0
1 0K _ 04
U 5
T5

A M6
A M7

N 5

MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC

AA9
AB9
W9
Y 9
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

C5 1

U 46 P
11/16 MIOB
MIOB_ VDDQ_NC
MIOB_ VDDQ_NC
MIOB_ VDDQ_NC
MIOB_ VDDQ_NC

MIOBD0_NC
MIOBD1_NC
MIOBD2_NC
MIOBD3_NC
MIOBD4_NC
MIOBD5_NC
MIOBD6_NC
MIOBD7_NC
MIOBD8_NC
MIOBD9_NC
MIOBD10_NC
MIOBD11_NC
MIOBD12_NC
MIOBD13_NC
MIOBD14_NC

R 1 11
10 K _ 04
AA7

MIOBCAL_PD_VDDQ_NC

AA6

MIOBCAL_PU_GND_NC

AF 1

MIOA_ VREF_NC

A B 3Y 3Y 2Y 1

DP

DVI/HDMI

I FP C _R SE T

U 46 O
10/16 MIOA
MIOA_ VDDQ_NC
MIOA_ VDDQ_NC
MIOA_ VDDQ_NC
MIOA_ VDDQ_NC

0. 1 u_ 16 V _ Y5 V _0 4

I FP C _PL LV DD

AK7

I FP C _I OV D D

U 46 I
9/16 IFPEF
P9
R 9
T9
U 9

P2 P1 P4 N 1

U 46 H
8/1 6 IF PC
I FP C _P L LV D D A J 9

AB2
AB1
AC 4
AC 1
AC 2
AC 3
AE3
AE2
U 6
W6
Y 6

I F P E F _ PL L V D D

AL 1

N 12 P -GS QS

P5
N3
L3
N2

MIOB_CTL3_NC
MIOB_ HSYNC_NC
M IOB_VSYNC_NC
M IOB_DE_NC

W3
W1
W2
Y 5

IF PD _ O
I V DD

I FP E_ AU X
I FP E_ AU X

TXC
TXC

TXC
TXC

FI PE _L3
IF PE _L3

TXD0
TXD0

TXD0
TXD0

IF PE _L2
IF PE _L2

TXD1
TXD1

TXD1
TXD1

FI PE _L1
IF PE _L1

TXD2
TXD2

TXD2
TXD2

FI PE _L0
IF PE _L0

HPDE

HPDE

GP IO 15

DP

AE7

MIOA_CLKOUT_NC
MIOA_CLKOUT_NC
MIOA_CLKIN_NC

MIOB_CLKOUT_NC
MIOB_CLKOUT_NC
MIOB_CLKIN_NC

AD7

I FP E _I OV D D

DVI/HDMI

R4 4

N 12 P -GS QS

DP

IF PD _ L3
IF PD _ L3

TXD0
TXD0

IF PD _ L2
IF PD _ L2

TXD1
TXD1

FI PD _ L1
IF PD _ L1

TXD2
TXD2

FI PD _ L0
IF PD _ L0

10 K _ 04

1 0K _ 04

A R4
A R5

I FP F_ AU X
I FP F_ AU X

TXC
TXC

FI PF _L3
IF PF _L3

TXD3
TXD3

TXD0
TXD0

FI PF _L2
IF PF _L2

TXD4
TXD4

TXD1
TXD1

FI PF _L1
IF PF _L1

TXD5
TXD5

TXD2
TXD2

FI PF _L0
IF PF _L0

HPDF

GP IO 21

10 /2 6
3V 3 _R U N

IFPEF

AP5
A N5

Sheet 16 of 49
VGA I/O

N 12 P -GS QS

A N7
AP7

5

TXC
TXC

A N4
AP4

A R7
A R8

4

3 Q2 4B
*M TD N 70 02 Z H S 6R

S MC _ VG A _T H E R M
S MD _ VG A _T H E R M

D

I FP D _A U X
I FP D _A U X

S

SDA
SCL

R3 8

N 12 P -GS QS

SDA
SCL

I FP F _I OV D D

V4
W4
A E 1M I OB _C LK I N _ N C

G

AK 8

R4
T4
N 4 MI O A _C L K I N _ N C

IF PD _ PLL VD D
IF PD _ RS E T

SDA
SCL

S MC _ V GA _ TH E R M 34
S MD _ V GA _ TH E R M 34

RN1 6
GPI O19

HPDD

L7

2

I F P C _ P LL V D D
I F P A B _P L LV D D
I F P D _ I OV D D
I F P C _ I OV D D

IF PD

R3 2

*1 0 mi l_ sh o rt

R2 6

*0 _0 4

3 V 3_ R U N
3 . 3V
RN1 3
2 . 2K _ 8P 4 R _0 4
4
3
2
1

3 V 3_ R U N

AJ 1 2

U 46 F
4/1 6 DACA
D AC A _V D D

AK1 2
R 65

S N N _ A _S D A
S N N _ A _S C L
I 2C B _S D A
I 2C B _S C L

2I C A _S C L
I 2C A _SD A

G1
G4

C2 2

D AC A _R S ET

C 60
*0 . 1u _1 6V _ Y 5V _ 04

10 K _0 4

D AC A _H S YN C
D A C A_V S YN C
D A C A_ RE D
D AC A _GR EE N
D A C A_ BLU E

0 .1 u _1 6V _ Y 5 V _0 4

AK6
A H7

U 46 E
6/16 DACB
D A CB _V D D

A M13
A L1 3

S NN_ HS Y NC
S NN_ V S Y NC

A M15

S NN_ RE D

A M14

S N N _ GR E E N

A L1 4

S N N _ B LU E

I2 CB _S C L
I 2C B _S DA

G3
G2

D AC B _H S YN C
D A C B_ VS YN C
D A C B_ R ED
D AC B _GR E EN
DA C B_ BL UE

AK9
A J1 1

LVDS
DVI-SL

I PAB_TXD0*
F
IF PAB_TXD0

IF PA_TXD0
IF PA_TXD0

I PAB_TXD1*
F
IF PAB_TXD1
IFPAB_PLLVDD

I PA_TXD1
F
IF PA_TXD1

I PAB_TXD2*
F
IF PAB_TXD2

I PA_TXD2
F
IF PA_TXD2

IFPAB_RSET
I PA_TXD3
F
IF PA_TXD3

RN1 5
4
3
2
1

R N 14
2 . 2K _ 8P 4 R _ 04

V GA _ TH E R MD C

U 4 6J
12/16 MISC1
T H ER MD N

C 23
10 00 p _5 0V _ X7 R _ 04
V GA _ TH E R MD A

B5

I 2 C B _S C L
I 2 C B _S D A

AP1 4
A R1 4
A N1 4
A N1 6
V _J TA G _T R S TA P 1 6

I 2C S_ SC L
I2C S _S D A

A M1
A M2
AK4

R 48 7

A L4

1K _ 04

E2
E1
E3
E4

S MC _ V GA _T H E R M 1
S MD _ V GA _T H E R M 1
I 2C C _S C L
I 2C C _S D A

11 /5

T H ER MD P

J TA G_TC K
J TA G_TM S
J TA G_TD I
J TA G_TD O
J TA G_TR S T

R 46
R 57
R 70
R 11 3
GPI O2
GPI O3
GPI O4
GPI O5
GPI O6
GPI O7
GPI O8
GPI O9
GPI O10
GPI O11
GPI O12
GPI O13
GPI O14
GPI O16
GPI O17
GPI O18

A J4

GPI O20
GPI O22
GPI O23
GPI O24

N 12 P -GS QS

5I F P E F _P L LV D D
6I F P A B _I OV D D
7I F P E F _I OV D D
8I F P D _ P LL V D D

I PAB_TXC*
F
IF PAB_TXC

IFPA_TXC
IFPA_TXC

1 0K _ 8P 4 R _ 04

I2C C _ SC L
I 2C C _S D A

R4 0
1 0K _ 04

I FP A B _ P LL V D D

3 V 3_ R U N

S N N _ A_ S C L
S N N _ A _S D A

D A CB _V R EF
D A CB _R S ET

3. 3 V
*1 0m i l_ sh ort

N 12 P -GS QS

D A C B _ V D D A G7

R2 9

V GA _ T H E R M_ SH D W N # 1

D AC A _V R EF

AK1 3

6 Q2 4A
*M TD N 70 02 Z H S 6R

DVI-DL

6 -0 2- 00 78 1- LD 0

B4

D A C A _V D D

1

V GA _T H E R M D C
V GA _T H E R M D A
V GA _V D D

8
7
6
5

R 61

4
3
2
1

GN D T H E R M#
A LE R T#
DS DA T A
D+
S CL K
VD D
G 78 1-1 P 8U F

9 /2 4
R N 27
1 0K _ 8 P4 R _ 04
8
1
7
2
6
3
5
4

5
6
7
8

11 /4

5
6
7
8

U 46 L
7/16 IFPAB

D

V GA _T H E R M_ S H D W N #
S MD _ VG A _T H E R M
S MC _ VG A _T H E R M

S

Test Point

*0_ 0 4

V GA _T H E R M_ S H D W N _ #
U 3

N 1 2P -GS Q S
1 0K _ 8P 4 R _0 4

1
2
3
4

5
6
7
8

G

4
3
2
1

K3
H3
H2
H1
H4
H5
H 6 V _GP I O8
J 7 V _GP I O9
K4
K5
H7
A C_ DE T R5 1
J4
J6

*10 K _0 4
*10 K _0 4
10 K _0 4
10 K _0 4

I F P A B _ I OV D D

A G9

IFPA_IOVDD

A G1 0

IFPB_IOVDD

3 V 3_ R U N

IF PAB_TXD3*
I PAB_TXD3
F

I PB_TXD4
F
IF PB_TXD4

I PAB_TXD4*
F
IF PAB_TXD4

I PB_TXD5
F
IF PB_TXD5

I PAB_TXD5*
F
IF PAB_TXD5

I PB_TXD6
F
IF PB_TXD6
I PB_TXD7
F
IF PB_TXD7

NV V DD_ V ID0
NV V DD_ V ID1
R 47
R 59

NV V DD_ V ID0 4 1
NV V DD_ V ID1 4 1
* 0_ 04 V GA _ T H E R M_ S H D W N #
* 0_ 04 E C _ V GA _ A LE R T #

IFPB_TXC
IFPB_TXC

3 V 3_ R U N
*1 0K _ 04
HPDAB

L2
L4
M4

GPIO0

IFPAB
N 12 P -GS QS

L5
L6
M6
M7

N 1 2P -GS QS

1 2, 4 1 3V 3 _R U N
2, 3 , 8, 1 1, 1 2, 1 8, 1 9 ,2 0 , 22 , 23 , 24 , 25 , 2 7, 2 8, 2 9, 3 0, 3 3 ,3 5 , 37 , 38 , 39 3. 3 V

VGA I/O B - 17

B.Schematic Diagrams

U 4 6G
5/16 IFPD

I F P D _ I OV D D

I FP E F_R S E T

MIOB_ VREF_NC

I F P E F _ I OV D D

AB 6

I FP E F_P LL VD D

DVI-SL
HDMI

SDA
SCL

K2
MIOA_CTL3_NC
MIOA_ HSYNC_NC
M IOA_VSYNC_NC
MIOA_DE_NC

I F P D _ P LL V D D A C 6

AJ 6

DVI-DL

Schematic Diagrams

VGA NVVDD Cecoupling
U46M

Sheet 17 of 49
VGA NVVDD
Cecoupling

B - 18 VGA NVVDD Cecoupling

16/16 NVVD D

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

N12P-GS QS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

NVVDD

11/ 8
C100

C76

C93

C56

0.22u_10V_X5R_04

0.22u_10V_X5R_04

10u_6.3V_X5R_06

10u_6.3V_X5R_06

C107

C129

C118

C67

0.022u_16V_X7R_04

0.022u_16V_X7R_04

0.022u_16V_X7R_04

0.022u_16V_X7R_04

C88

C66

C73

C52

C91

C111

10u_6.3V_X5R_06

0.01u_16V_X7R_04

0.01u_16V_X7R_04

0.01u_16V_X7R_04

10u_6.3V_X5R_06

0.01u_16V_X7R_04

C89

C102

C101

C57

C92

0.047u_10V_X7R_04

0.047u_10V_X7R_04

0.047u_10V_X7R_04

1u_6.3V_X5R_04

4.7u_6.3V_X5R_06

11/8

11/ 8

PLACE IN THE BACKPLATEAREA

11/8
NVVDD

C550
+

C426
+

C119
+

C424

C430

C706
10u_6.3V_X5R_08

N12P-GSQS

NVVDD
U46N

22u_6.3V_X5R_08

G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND

NVVDD

22u_6.3V_X5R_08

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

E15
E18
E24
E27
E30
E6
E9
F2
F31
F34
F5
J2
J31
J34
J5
L9
M11
M13
M15
M17
M19
M2
M21
M23
M25
M31
M34
M5
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R31
R34
R5
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V12
V14
V16
V18
V2
V20
V22
V24
V31
V5
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25

560u_2.5V_6.6*6.6*5.9

G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND

560u_2.5V_6.6*6.6*5.9

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

330u_2.5V_V_A

B.Schematic Diagrams

15/16 GND

AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AA5
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD11
AD13
AD15
AD17
AD2
AD21
AD23
AD25
AD31
AD34
AD5
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG31
AG34
AG5
AK2
AK31
AK34
AK5
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AL6
AL9
AN2
AN34
AP12
AP15
AP18
AP21
AP24
AP27
AP3
AP30
AP33
AP6
AP9
B12
B15
B21
B24
B27
B3
B30
B33
B6
B9
C2
C34
E12

41

NVVDD

Schematic Diagrams

CougarPoint - M 1/9
R TC V C C
D2 8
B A T 54 C W GH
1 A
C 3
R T C _ V B A T 2_ 1 A

20mils
V D D3

CougarPoint - M (HDA,JTAG,SATA)

20mils
C 46 3

C 70 3
1 8p _ 5 0V _ N P O_ 0 4

1 u _ 6. 3 V _ X 5 R _ 04

2
1

3
4

J OP E N 1
* OP E N _1 0 m li -1 MM

3
4

1

RT C C LE AR
C7 0 2
1 8p _ 5 0V _ N P O_ 0 4

RT C_ X 1

R3 5 5
20 K _ 1 %_ 0 4

IN T RUD E R#

1 u_ 6 . 3 V _X 5 R _ 0 4
P C H _ I N T V R ME N

3 30 K _ 0 4

C 17
I N T V R ME N

33

R 6 11

3 . 3A _ 1 . 5 A _ H D A _ I O

C 42 8
S H OR T * 0. 1 u _ 16 V _ Y 5 V _ 0 4

32 Mb it
S P I _S I

S P I _C S 0 #

SP KR
H D A _ R S T#

3 17 S P I _S I _R
2 94 S P I _ S O _R
3 25 S P I _S C L K _ R
2 93 S P I _ C S _ 0 #
3 06 S P I _ C S _ 1 #

33
33
33
33

H DA _ S Y N C
H DA _ S P K R
H DA _ RS T #
H DA _ S D IN0

H DA _ S D IN0
H DA _ S D IN1

33

H D A _ S D OU T

A 34

S CK

H DA _ S D IN3
4

H OL D #

VSS
34

*M X 25 L 3 20 5 D M 2I -1 2 G
S A T A _R X P 1_ C
S A TA _ R XN 1_ C
S A T A _ TX N 1_ C
S A TA _ T X P 1_ C
J_ H D D 1
S1
S2
S3
S4
S5
S6
S7

S A T A _ RX P 1
S A T A _ RX N1
S A T A _ TX N 1
S A T A _ TX P 1

ME _ W E

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

3. 3 V S

R B 7 51 S -4 0 C 2
A

R 60 3

0_04

R 60 2

* 9 10 _ 0 4

D 29
C

A 36

H DA _ S D O

C 36
31
1K _ 0 4 1
J OP E N 2

R 60 6

3. 3 A _ 1 . 5A _H D A _ I O
J _S A T A 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

2

S A T A _R X N 2
S A T A _R X P 2

LE D _ I GP U #

H D A _ D O C K _ E N # / GP I O 33
N 32

29 U S B 3. 0_ S M I #

* OP E N _ 10 m i -l 1 MM

3 .3 V

Flash Descriptor
Security Overide
Low = Disabled-(Default)
High = Enabled

S A T A _T X P 2
S A T A _T X N 2

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

S A T A 3 RX N
S A T A 3 RX P
S A T A 3T X N
S A T A 3 TX P
S A T A 4 RX N
S A T A 4 RX P
S A T A 4T X N
S A T A 4 TX P

H D A _ D O C K _ R S T# / G P I O1 3

R 5 66

J T A G_ T C K

S A T A 5 RX N
S A T A 5 RX P
S A T A 5T X N
S A T A 5 TX P

J T A G_ T MS

S A TA I C OM P O

1 0K _ 0 4
P C H _J T A G_ T C K _ B U F J3

10/28

P C H _J T A G_ T MS

H7

P C H _J T A G_ T D I

K5

P C H _J T A G_ T D O

H1

R3 0 1

*1 K _ 04

R3 1 3

J T A G_ T D O

5 VS

*2 . 2 u _6 . 3 V _ Y 5 V _ 0 6 * 2 20 u _6 . 3 V _ 6 . 3* 6. 3* 4. 2
S A T A _ TX P 1 _ C
S A T A _ TX N 1 _ C
S A T A _ RX N1 _ C
S A T A _ R X P 1 _C

GN D1
GN D 2

*A C E S -91 9 0 7-0 2 2 0A -H 0 1

V 5

S E RIR Q

A
A
A
A

M3
M1
P7
P5

S A T A RX N0
S A T A RX P 0
S A T A TX N 0
S A T A TX P 0

A
A
A
A

M1 0
M8
P 11
P 10

S A T A _R X N 1
S A T A _R X P 1
S A T A _T X N 1
S A T A _T X P 1

SATA HDD

A
A
A
A

D7
D5
H5
H4

S A T A _R X N 2
S A T A _R X P 2
S A T A _T X N 2
S A T A _T X P 2

SATA ODD

A
A
A
A

B8
B 10
F3
F1

*1 0 K _0 4
R3 8 6

S E RIR Q 2 8 ,3 4

*1 0 K _0 4

E-SATA HDD
W15XX/W17XX

Sheet 18 of 49
CougarPoint - M 1/9

S A T A _ RX N 3 2 7
S A T A _ RX P 3 2 7
S A T A _ T XN 3 27
S A T A _ T XP 3 2 7

Y 7
Y 5
A D3
A D1
Y
Y
A
A

3 . 3V S

B o a rd I D

S A T A _ R X N 4_ 1 4
S A T A _ R X P 4 _ 14
S A T A _ T XN 4 _1 4
S A T A _ T XP 4_ 1 4

31
31
31
31

W14XX

SATA ODD

3
1
B3
B1
1. 05 V S
S A T A I C OMP

R3 0 8

3 7 . 4_ 1 % _0 4

S A T A 3 C O MP

R3 0 9

4 9 . 9_ 1 % _0 4

S A T A I C O MP I
1. 05 V S
A B 12
A B 13

S P I_ S CL K
R 5 62
S P I_ CS 0 #
R 3 15

S P I _S C L K _ R T3
*0 _ 04
S P I _C S _ 0# Y 14
*0 _ 04
T1
S P I _C S _ 1#

SPI_ SI
R 3 03
SPI_ SO
R 3 07

S P I _S I _R
*0 _ 04
S P I _S O_ R
*3 3 _0 4

Gen3

* 0. 1u _ 16 V _ Y 5 V _ 0 4

E 36
K 36

W14XX R391
W15XX/W17XX
R386
R3 9 1

S A T A 3 C O MP I

+C 6 86

C 68 7

LP C _ F R A M E # 28 , 3 4

S A T A 3 R C OM P O

5V S _O D D

C 6 89

LP C _ A D 0 2 8, 34
LP C _ A D 1 2 8, 34
LP C _ A D 2 2 8, 34
LP C _ A D 3 2 8, 34

Y 10

S A T A _ OD D _ D A # 2 2, 31

H D D _N C 0

38
38
37
37

Y 11
J T A G_ T D I

S A T A _ OD D _ P R S N T# 2 3 , 3 1

8 80 1 4 -30 0 0 1

H D D _N C 1
H D D _N C 2
H D D _N C 3

IHDA

H DA _ S D IN2
S P I _S C L K

S A T A 1 RX N
S A T A 1 RX P
S A T A 1T X N
S A T A 1 TX P
S A T A 2 RX N
S A T A 2 RX P
S A T A 2T X N
S A T A 2 TX P

C 34

CE #
6

S A T A 0 RX N
S A T A 0 RX P
S A T A 0T X N
S A T A 0 TX P

E 34
G 34

SATA

S P I _S O

1

SO
W P#

R
R
R
R
R

K 34

JT AG

R3 2 8
*3 . 3 K _1 % _ 04
S P I _W P # 3

2

0_04
0_04
0_04
0_04
* 0_ 0 4

H S P I _M S I
H S P I _ MS O
H S P I_ S CL K
H S P I_ CE #

H DA _ S Y NC
T 10

R5 7 9
R5 8 1
R5 8 8
R5 9 0

*0 _ 04
*0 _ 04
*0 _ 04
*0 _ 04

S A T A _ TX P 1
S A T A _ TX N 1
S A T A _ RX N1
SA T A_ RXP1

S P I _C LK

S A T A 3 RB IA S

A H1

R B I A S _ S A T A 3 R 57 0

R 56 3

S P I _C S 1 #

V4
S P I _M OS I

P 3

*1 0K _0 4

S A T A _L E D #

SAT AL ED #

S A TA _ L E D # 3 1
V 14

O D D _ D E TE C T #

S A TA 0 G P / GP I O 2 1

U3

75 0 _ 1% _ 0 4
3 .3 VS

S P I _C S 0 #

S PI

5

34
34
34
34

H D A _ B C LK
L 34

1 K _0 4

C
A
B
C

S E RIR Q

N 34

PLL ODVR VOLTAGE: HDA_SYNC
LOW-1.8 V (DEFAULT) HIGH-15V

Share ROM
SI

*1 K _ 04

S P I_ S I

OD D _ D E T E C T # 2 3
P 1

S P I _M I S O

S A TA 1 G P / GP I O 1 9

H M6 5 _ B D 8 2 C P M S _E S 2

B B S _ B IT 0

R5 6 4

*1 K _ 0 4

BBS_BIT0 - BIOS BOOT STRAP BIT 0

P IN G ND 1 ~ 2 = G ND
3 .3 V

L ay ou t No te :

HOST

RN 2
3 .3 V S
3 .3 V S

5
6
7
8

4
3
2
1

*4 . 7 K _ 8P 4 R _0 4

D1

D0

R X _1 N
RX _ 1 P
T -P A D

T X _ 1N
T X _ 1P

1 2 S A T A _ RX N0 _ R
1 1 S A T A _ R X P 0 _R

GND
GN D
GND
GN D
G ND

*0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 S A T A _ R X N 0 4
*0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 S A T A _ R X P 0 5

DEVICE

L ay ou t no te :

NEAR TO J_ESATA1
SN75LVCP412RTJ

6 -0 2- 754 12 -K Q0

S A TA _T X P 0 _R
R5 4 9

R2 8 5

R2 8 4

2 10 _ 1 %_ 0 6

2 10 _ 1 %_ 0 6

21 0 _ 1% _ 0 6

C 31 4

S A TA _T X N 0 _ R C 31 2

3. 3V S
*4 . 7 K _ 0 4

C5 0 0

C3 1 7

P C H _ JT A G _T MS
P C H _ JT A G _T D I
P C H _ JT A G _T D O

C3 1 8
1u _ 6 . 3V _Y 5 V _ 0 4

R X _0 P
R X _0 N

3
13
17
18
19

*0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 S A T A _ TX P 0 1
*0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 S A T A _ TX N 0 2

U 19
* S N7 5 L V CP 4 1 2
E S A TA _E N 1
7
EN
1 5 S A T A _ TX P 0 _ R
TX _ 0 P 1 4 S A T A _ TX N 0_ R
T X _0 N

Closed to U4

0 . 1u _ 1 6V _ Y 5 V _ 04

VD D
VDD
VD D
VDD

6
10
16
20

R2 1 1

0 . 01 u _ 16 V _ X 7 R _ 0 4

S A T A _ TX P 0 _ R
S A T A _ TX N 0_ R
S A T A _ RX N0 _ R
S A T A _ R X P 0 _R

D1
D 0

S A TA R X N 0 C 30 9
S A TA R X P 0 C 30 5

0 _0 4
0 _0 4
0 _0 4
0 _0 4

21

S A TA T X P 0 C 31 3
S A TA T X N 0 C 31 1

R 2 24
R 2 20
R 2 17
R 2 14

8
9

S A T A T XP 0
S A T A T XN 0
S A T A RX N0
S A T A RX P 0

ESATA POART

3 . 3V S

ESATA REDRIVER

J _ ESATA1
1
GN D 1

2
S A TA _T X P 0 _C 1
L21
S A T A _T X P _ 0_ C
0. 0 1 u _1 6 V _ X7 R _ 0 4
3
S A TA _T X N 0 _ C 4
S A T A _T X N _ 0 _ C
0. 0 1 u _1 6 V _ X7 R _ 0 4
* W C M 20 1 2 F 2S -16 1 T 03 -s h ort

2

2
S A TA _R XN 0 _C 1
L20
S A T A _R X N _ 0_ C
0. 0 1 u _1 6 V _ X7 R _ 0 4
3
S A TA _R XP 0_ C 4
S A T A _R X P _0 _ C
* W C M 20 1 2 F 2S -16 1 T 03 -s h ort
0. 0 1 u _1 6 V _ X7 R _ 0 4

5

T XP
3
T XN
4
GN D 2

S A TA _R XN 0 _R C 30 7
S A TA _R XP 0_ R C 30 4

RXN
6
RXP
7

R5 6 8

R2 9 8

R2 9 7

Gen3

GN D 3
A T 0 7J 3 6 B A A 0 90

10 0 _ 1% _ 0 4

R 5 67

1 00 _ 1% _ 0 4

5 1_ 0 4

10 0 _ 1% _ 0 4

2 5 3 . 3A _ 1 . 5 A _H D A _ I O
20 , 2 5 R TC V C C
6 , 1 9, 2 0 , 2 4, 2 5 , 2 9, 35 , 3 7 , 38 , 3 9 1. 0 5 V S
2 7, 2 8 , 3 0, 34 , 3 5 , 36 , 4 1 , 42 V D D 3
1 1, 2 4 , 2 5, 2 7 , 2 8, 3 1 , 3 2, 33 , 3 5 , 39 , 4 0 5V S
2 , 3, 8 , 1 1 , 1 2, 1 6 , 1 9, 2 0 , 2 2, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 0 , 3 3, 35 , 3 7 , 38 , 3 9 3. 3 V
3 , 6, 9 , 1 0 , 11 , 1 2 , 1 9, 2 0 , 2 1, 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 3 1 , 3 2, 33 , 3 4 , 35 , 3 9 3. 3 V S
P C H _J T A G_ T C K _ B U F

CougarPoint - M 1/9 B - 19

B.Schematic Diagrams

SPI_* = 1.5"~6.5"

H DA _ B IT CL K

L DRQ 0 #
L D R Q1 # / GP I O 2 3

SATA 6G

R 5 95

N C3

P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15

K 22

INTVRMEN- Integrated SUS 1.05V VRM Enable
High - Enable Internal VRs /Low - Enable External VRs

VD D

H D A _S P K R

D 36

S R T C R S T#

R TC V C C

R 32 7
* 3. 3 K _ 1 %_ 0 4
S P I _ H O LD # 7

G 22

S M_ I N T R U D E R #

F W H0 / L A D 0
F W H1 / L A D 1
F W H2 / L A D 2
F W H3 / L A D 3

F W H 4 / LF R A ME #

RTC

1M _ 04

U 32

S RT C_ RT C #
C4 6 8

BIOS ROM

S P I _V D D 8

D 20

RT C_ RS T #

R T CRS T #

R3 5 0

3 .3 V S

C 20
R T CX 2

Zo= 50O? 5%

*8 5 20 5 -0 27 0 1

Co-lay

A 20

2

2

R2 8 9

6-03-00651-0S0

R T CX 1
R T C _X 2

1

A A A -B A T-0 2 2 -K 01

U5 4 A

1 0M _0 4

R TC _V B A T
2

1 0 K _ 04

R5 9 8

L PC

2
1

X1 3
M C -3 0 6 _3 2 . 7 68 K H z

C4 5 9
1 u_ 6 . 3 V _X 5 R _ 0 4

J _ CB A T 1

1

S E R IRQ

X 14

6-22-32R76-0B2
6-22-32R76-0BG

*3 2 . 7 68 K H z

R 34 4
2 0 K _1 % _ 04

10/15

J _ CB A T 2

3 . 3V S

i TP M ENA BL E/ DI SA BL E
TP M F UN CT ION :S PI _SI H ig h Ena bl e

R 5 92
1 K_ 0 4

NO R EBO OT S TR AP
NO RE BO OT S TRA P: H DA_ SP KR Hi gh E nab le

Schematic Diagrams

CougarPoint - M 2/9
CougarPoint - M (PCI-E,SMBUS,CLK)
U 5 4B

P C I E _R X N 3 _ W L A N
P C I E _R X P 3 _W L A N
P C IE _ T X N3 _ W L A N
P C I E _ T X P 3 _W L A N

P C I E _T X N 2_ C
P C I E _T X P 2 _ C

C5 3 3
C5 2 6

0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u_ 1 0 V _ X 7R _ 04

P C I E _T X N 3_ C
P C I E _T X P 3 _ C

B G 36
B J 36
A V 34
A U 34

P C I E _T X N 4_ C
P C I E _T X P 4 _ C

BF
BE
AY
BB

36
36
34
34

BG
BH
AY
BB

37
37
36
36

0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u_ 1 0 V _ X 7R _ 04

Usage

1
2
3
4
5
6
7
8

34
34
32
32

B J 38
B G 38
A U 36
A V 36

USB3.0 FOR VIA
USB3.0
WLAN
GLAN / CARD READER
X
X
X
X

B G 40
B J 40
A Y 40
B B 40
BE
BC
AW
AY

38
38
38
38

Y 40
Y 39
P C I E C L K R Q0 #

10 0MH z R 3 4 6
R4 5 2

*1 0 m li _ s ho rt
*1 0 m li _ s ho rt

C L K _ P C I E _ U S B _ 3 0 _# _ V L I A B 49
A B 47
C L K _ P C I E _ U S B _ 3 0 _V LI
U S B 3 0_ C LK R E Q # _V LI

10 0MH z R 3 4 0

*1 0 m li _ s ho rt
*1 0 m li _ s ho rt

R2 9 2

*1 0 m li _ s ho rt

10 0MH z

R 36 1
R 36 2

*1 0 m li _ s h or t
*1 0 m li _ s h or t

C L K _ P CIE _ M INI N
C L K _ P CIE _ M INI P

S M L 0_ C L K

G 12

S M L 0_ D A T A

C 13

L P D _S P I _ I N T R #

E 14

S M C_ C P U_ T H E RM

S M L 0D A T A

6 , 9, 10

S MB _ D A T A 6 , 9 , 10
LP D _ S P I _ I N T R #
P C H _ B T _E N #
P E G_ B _ C L K R Q #
P E G_ P C I E C L K R Q 7 #

D R A MR S T _C N TR L 3 , 8

S M L 1C L K / G P I O 58
M 16

S M D_ C P U_ T H E RM

P E RN 8
P E RP 8
P E T N8
PETP8

M7

C L_ C L K 1

T11

C L_ D A T A 1

P 10

C L_ R S T # 1

CL _ CL K 1

CL _ DA T A 1

C L _ R S T 1#

10 K _ 0 4
10 K _ 0 4

C L _ CL K 1 2 7

C L _ DA T A 1 2 7

C L _ RS T # 1 2 7

M 10

P E G _ CL K R E Q #

A B3 7
A B3 8

V G A _ P E X CL K #
V G A _ P E X CL K

P E G _ A _ C L K R Q# / G P I O 47

CL K O UT _ P E G _ A _ N
C LK OU T _P E G_ A _ P

C L K O UT _ DM I_ N
C L K O U T _ D MI _ P

CL KO UT _ D P_ N
C L K OU T _D P _ P
C L K O U T _ P C I E 2N
C L K O U T _ P C I E 2P
CL K IN _ DM I_ N
C LK I N _ D MI _ P

V 10

C L K O U T _ P C I E 3N
C L K O U T _ P C I E 3P

C L K I N _G N D 1 _ N
C L K I N _ GN D 1 _ P

P E G_ C LK R E Q # 1 2

10 0M Hz
10 0M Hz

A V2 2
A U2 2

A M1 2
A M1 3

_N
_P
CL K _ N
CL K _ P

R N 19
1 0 K _ 8 P 4 R_ 0 4
8
1
7
2
6
3
5
4

C L K _ B U F _ D O T9 6 _ P
C L K _ B U F _ D O T9 6 _ N
C L K _ B U F _ C K S S C D _P
C L K _ B U F _ C K S S C D _N

RN 9
1 0 K _ 8 P 4 R_ 0 4
8
1
7
2
6
3
5
4

CL K _ P C
CL K _ P C
CL K _ B U
CL K _ B U

V GA _ P E XC L K # 1 2
V GA _ P E XC L K 1 2

IE _ ICH
IE _ ICH
F _ CP Y
F _ CP Y

CL K _ E X P _ N 3
CL K _ E X P _ P 3
P C H _ C L K _D P _ N _R
P C H _ C L K _D P _ P _ R

R 30 4
R 30 5

*1 0 m i _l s h or t
*1 0 m i _l s h or t

12 0M Hz

C L K _ D P _N
C L K _ D P _P

B F 1 8 CL K _ P C IE _ ICH _ N
B E 1 8 CL K _ P C IE _ ICH _ P

3
3

11/1

CL K _ B U F _ RE F 1 4
P E G_ C L K R E Q #
LA N _ C L K R E Q #

R3 3 5
R4 1 0
R3 7 1

1 0 K_ 0 4
1 0 K_ 0 4
* 1 0K _0 4

B J3 0 C L K _ B U F _ C P Y C L K _ N
B G3 0 C L K _ B U F _ C P Y C L K _ P

A8

C L K _ P CIE _ G L A NN
C L K _ P CIE _ G L A NP
L A N _C L K R E Q#

Y 43
Y 45
L 12

C L K I N _S A T A _ N
CL K I N_ S A T A _ P

P C I E C L K R Q 4 # / GP I O2 6
V 45
V 46

P C I E C LK R Q 5#

C L K I N _D OT _ 9 6 N
C L K I N _ D O T _9 6 P
C L K O U T _ P C I E 4N
C L K O U T _ P C I E 4P

C L K O U T _ P C I E 5N
C L K O U T _ P C I E 5P

G 24
E 24

C L K _ B U F _ D O T9 6 _ N
C L K _ B U F _ D O T9 6 _ P

A K7
A K5

C L K _ B U F _ C K S S C D _N
C L K _ B U F _ C K S S C D _P

K 45

CL K _ B U F _ RE F 1 4

RE F C L K 1 4 IN

L 14

Crystal 8045 & 3225 Co-lay
C7 3 5

3 3MHz

H 45
C L K I N _ P C I L OO P B A C K

R 6 20
C L K _ P C I _F B 2 2

X1 5

1 M _0 4
2

P C I E C L K R Q 5 # / GP I O4 4
A B 42
A B 40
P E G _ B _ C L K R Q#

C L K O U T _ P E G _B _N
C L K O U T _ P E G _B _P

XT A L 2 5 _ I N
X T A L 2 5_ O U T

V 47
V 49

X T A L 2 5_ I N
X T A L 2 5_ O U T

Y 47

X C L K _ R C O MP

E6
P E G_ B _ C LK R Q # / GP I O5 6
V 40
V 42

P C I E C LK R Q 6#

P C I E C L K R Q 6 # / GP I O4 5

P E G _ P C I E C L K R Q7 # K 12
A K 14
A K 13

C L K O U T _ P C I E 7N
C L K O U T _ P C I E 7P
P C I E C L K R Q 7 # / GP I O4 6
CL K O UT _ IT P X DP _ N
CL K O UT _ IT P X DP _ P

9 0 . 9 _ 1 %_ 0 4

1 .0 5 VS

90.9-O ? % pullup to +VccIO
(1.05V, S0 rail)close to
PCH

T 13
V 38
V 37

C LK _X D P _ N
C LK _X D P _ P

X C L K _ R C OM P
C L K O U T _ P C I E 6N
C L K O U T _ P C I E 6P

R 62 1

K 43

R 53 6

*0 _ 0 4

F 47

R 54 5
R 55 2

C L K O U T F L E X 1 / G P I O 65
H 47
C L K O U T F L E X 2 / G P I O 66
K 49
C L K O U T F L E X 3 / G P I O 67

10/22

X T A L _ IN

12

*0 _ 0 4

L AN XIN

30

*0 _ 0 4

U S B 3 0 _ XT 1 2 9

C L K O U T F L E X 0 / G P I O 64

D GP U _ P R S N T #

H M 6 5_ B D 8 2C P M S _ E S 2
6 , 1 8 , 2 0, 24 , 2 5 , 2 9 , 35 , 3 7 , 3 8 , 3 9 1 . 0 5 V S
2 , 3 , 8 , 1 1, 12 , 1 6 , 1 8 , 20 , 2 2 , 2 3 , 2 4, 2 5 , 2 7 , 2 8, 2 9 , 3 0 , 3 3, 35 , 3 7 , 3 8 , 39 3 . 3 V
3, 6 , 9 , 1 0 , 1 1 , 12 , 1 8 , 2 0 , 2 1, 2 2 , 2 3 , 2 4, 25 , 2 7 , 2 8 , 29 , 3 0 , 3 1 , 3 2, 3 3 , 3 4 , 3 5, 39 3 . 3 V S

1 8p _ 5 0 V _ N P O _ 04

1

*1 0 m li _ s h or t
*1 0 m li _ s h or t

4

R 36 3
R 37 3

*H S X 32 1 S _ 2 5 MH Z
2

P C I E C L K R Q 3 # / GP I O2 5

10 0MH z

2 2 LA N _ C LK R E Q #

B - 20 CougarPoint - M 2/9

3 .3 VS

10K pull-down to
GND

C L K O U T _ P C I E 0N
C L K O U T _ P C I E 0P

C L K O U T _ P C I E 1N
C L K O U T _ P C I E 1P

S M D _ C P U _ T H E R M 34

2. 2K _0 4
2. 2K _0 4
1K _0 4

N5
_8 P 4 R _0 4
8
1
7
2
6
3
5
4

D GP U _ P R S N T #
R 41 8
U S B 3 0 _ C L K R E Q# _ N E C _ 2 R 29 1

P E RN 7
P E RP 7
P E T N7
PETP7

P C I E C L K R Q 0 # / GP I O7 3

R 33 2
R 33 0
R 58 3

R
1 0K
U S B 3 0 _ C L K R E Q# _ V L I
P C I E C L K R Q6 #
P C I E C L K R Q5 #
P C IE C L K RQ 0 #

S M C _ C P U _ T H E R M 34

S M L1 D A T A / G P I O 75

R N4
1 0K _8 P 4 R _0 4
8
1
7
2
6
3
5
4

S MD _ C P U _ TH E R M
S MC _ C P U _ TH E R M
D R A MR S T _ C N T R L

S M L 1A LE R T # / P C H H OT # / G P I O 74

P C I E C L K R Q 1 # / GP I O1 8

Y 37
Y 36

D R A MR S T _ C N TR L

C 8
SM L 0 CL K

P C I E C L K R Q 2 # / GP I O2 0

2 7 W L A N _ C L K R E Q#

3 0 C L K _ P CIE _ G L A N#
3 0 C LK _P C I E _ G LA N

P E RN 4
P E RP 4
P E T N4
PETP4

M1

C L K _ P C I E _ U S B _ 3 0 _# _ N E C A A 48
C L K _ P C I E _ U S B _ 3 0 _N E C A A 47
U S B 3 0 _ C L K R E Q# _ N E C _ 2

2 9 U S B 3 0_ C LK R E Q # _N E C

2 7 C LK _P C I E _ M I N I #
2 7 C L K _ P C I E _ MI N I

R3 5 1

A 12
S ML 0 A L E R T # / G P I O 60

S MB _ C LK

3

2 9 C LK _P C I E _ U S B 3 0 #_ N E C
2 9 C L K _ P C I E _ U S B 3 0_ N E C

S M B _ D A TA

3 .3 V

RN 6
2 . 2 K _ 8P 4R _ 0 4
8
1
7
2
6
3
5
4

S MB _ C L K
S MB _ D A T A
S ML 0 _ C L K
S ML 0 _ D A T A

P C H _B T_ E N # 2 7

X 8A 02 5 0 0 0F G 1 H _ 2 5 M H z

2 9 C L K _ P C I E _ U S B 30 # _ V L I
2 9 CL K _ P C IE _ US B 3 0 _ V L I

J2

S M B _ CL K

S MB D A T A

P E RN 3
P E RP 3
P E T N3
PETP3

P E RN 6
P E RP 6
P E T N6
PETP6

H 14
C 9

S MB C L K

P E RN 2
P E RP 2
P E T N2
PETP2

P E RN 5
P E RP 5
P E T N5
PETP5

P C H_ B T _ E N #

1

Sheet 19 of 49
CougarPoint - M 2/9

0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u_ 1 0 V _ X 7R _ 04

C5 3 4
C5 2 9

PCI-E x1
Lane
Lane
Lane
Lane
Lane
Lane
Lane
Lane

C5 1 5
C5 2 1

BE
BF
BB
AY

FLEX CLOCKS

B.Schematic Diagrams

3 0 P C I E _ R X N 4_ G L A N
3 0 P C I E _ R X P 4 _ GL A N
3 0 P C I E _ TX N 4_ G L A N
3 0 P C I E _ TX P 4 _ GL A N

P C I E _T X N 1_ C
P C I E _T X P 1 _ C

E 12
S M B A L E R T # / G P I O 11

SMBUS

27
27
27
27

0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u_ 1 0 V _ X 7R _ 04

P E RN 1
P E RP 1
P E T N1
PETP1

Link

C5 6 4
C5 6 5

P C I E _R X N 2 _ U S B 3 0_ N E C
P C I E _R X P 2 _U S B 3 0 _ N E C
P C I E _ T X N 2 _ U S B 3 0_ N E C
P C I E _ T X P 2 _U S B 3 0 _ N E C

B G 34
B J 34
A V 32
A U 32

Controller

SB3 0 _ VL I
S B 3 0 _V LI
SB3 0 _ VL I
S B 3 0 _V LI

CLOCKS

29
29
29
29

P C I E _ R X N 1 _U
P C IE _ RX P 1 _ U
P C I E _ TX N 1 _U
P C I E _ TX P 1 _ U

PCI-E*

9/3
29
29
29
29

C7 3 6

X 16

1 8p _ 5 0 V _ N P O _ 04

Schematic Diagrams

CougarPoint - M 3/9
CougarPoint -M (DMI,FDI,GPIO)
U 54C

I_ RX N
I_ RX N
I_ RX N
I_ RX N

2
2
2
2

DM I_ RX P 0
DM I_ RX P 1
DM I_ RX P 2
DM I_ RX P 3

2
2
2
2

D
D
D
D

2
2
2
2

D MI _T X P 0
D MI _T X P 1
D MI _T X P 2
D MI _T X P 3

MI
MI
MI
MI

_T X N
_T X N
_T X N
_T X N

B C2 4
BE2 0
B G1 8
B G2 0

0
1
2
3

BE2 4
B C2 0
B J1 8
B J2 0
AW 2 4
AW 2 0
BB1 8
AV1 8

0
1
2
3

AY2 4
AY2 0
AY1 8
A U1 8

DM
DM
DM
DM

I0 RX N
I1 RX N
I2 RX N
I3 RX N

F
F
F
F
F
F
F
F

DM I0 RX P
DM I1 RX P
DM I2 RX P
DM I3 RX P
DM
DM
DM
DM

I 0 T XN
I 1 T XN
I 2 T XN
I 3 T XN

D M I 0 T XP
D M I 1 T XP
D M I 2 T XP
D M I 3 T XP

DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R

FD
FD
FD
FD
FD
FD
FD
FD

FDI

DM
DM
DM
DM

DMI

2
2
2
2

I _R
I _R
I _R
I _R
I _R
I _R
I _R
I _R

X N0
X N1
X N2
X N3
X N4
X N5
X N6
X N7
XP0
XP1
XP2
XP3
XP4
XP5
XP6
XP7

B
A
B
B
B
B
B
B

J 14
Y1 4
E1 4
H1 3
C1 2
J 12
G1 0
G9

B
B
B
B
B
B
B
B

G1 4
B1 4
F14
G1 3
E1 2
G1 2
J 10
H9

A W16

B J2 4

DM I_ CO M P _ R

A V1 2
D M I _ Z C OM P

R5 9 4

75 0 _ 1 % _ 0 4

B C1 0
D M I _ I R C O MP

F D I_ F S Y N C1

DM I2 RB IAS

F DI_ L S Y N C0

B H2 1

D M I _2 R B I A S

DI_ T X P 0
DI_ T X P 1
DI_ T X P 2
DI_ T X P 3
DI_ T X P 4
DI_ T X P 5
DI_ T X P 6
DI_ T X P 7

3 .3 V
P M _ SL P _ L A N#
SW I #
SU S_ PW R _ AC K

R3 2 3
R5 7 6
R5 8 2

P C IE _ W A K E #
PW R _ BTN #
P M _ B A T L OW #

2
2
2
2
2
2
2
2

* 10 K _0 4
1 0 K_ 0 4
1 0 K_ 0 4

R3 2 2
R3 3 6
R5 7 5

1 K_ 0 4
*1 0 K _ 0 4
8 .2 K _ 0 4

R5 5 3

8 .2 K _ 0 4

R5 9 6

3 3 0K _0 4

R5 9 3

*3 3 0 K _ 0 4

R3 5 8

1 0 K _ 04

3 .3 V S
P M _ CL K RU N#

F DI_ F S Y N C0 2

F D I_ F S Y N C0

B G2 5

F
F
F
F
F
F
F
F

2
2
2
2
2
2
2
2

RT C V C C

F DI_ F S Y N C1 2

A V1 4

DS W O DV R E N

F DI_ L S Y NC 0 2
B B1 0

F DI_ L S Y NC 1 2

F DI_ L S Y N C1

AL L _ SY S_ PW R G D
A 18

D S W O D V RE N

E 22

R S M RS T #

B 9

PC IE _ W A K E #

N 3

P M _ C LK R U N #

G 8

S4 _ ST AT E #

Sheet 20 of 49
CougarPoint - M 3/9

System Power Management

D S W V R ME N
C1 2

SU S_ PW R _ AC K

S US A CK #
R 55 6

3 .3 V S

10/22

C 698

1 0 K_ 0 4

*0 . 1 u _ 1 0 V _ X 5 R _ 0 4

S Y S _ RE S E T #

K3

SY S_ PW R O K

P1 2

S Y S _R E S E T #

S Y S _P W R OK

R3 5 4

0 _ 04

P M _ P CH _ P W R O K _ R

L2 2

R3 5 2

*1 0 m i _l s h o rt

P M _ MP W R O K

L1 0

3 4 P M _P C H _ P W R O K

P W R OK

APW R O K
B1 3
3

P M_ D R A M_ P W R G D

D R A M P W R OK
C2 1

R S MR S T #
34

RS M R S T #

R3 5 3

34

RS M R S T #

1 0K _0 4

3 4 S U S _ P W R_ A C K

P W R_ B T N #

S US _ PW R _ A CK

K1 6

P W R _ B T N#

E2 0

A C_ P RE S E NT

H2 0

W A KE#

C L K R U N # / GP I O3 2

D 10

SL P_ S5 #

Disabled

S 4_ S TA TE # 2 8

H 4
SL P_ S4 #

SU SC # 3 4 ,3 8
F 4

SL P_ S3 #

SU SB#
G 10

S L P _A #

G 16

S L P _S U S #

SL P_ A#

A C P R E S E N T / GP I O3 1

SL P_ SU S#

B A T L OW # / GP I O7 2

P MS Y N C H

A P1 4

A1 0

S W I#

S U S C LK

Enabled (DEFAULT)

R681

P M_ C LK R U N # 28

S LP _S 5 # / GP I O6 3

E1 0

SW I#

N 14

R680

S U S C L K / GP I O6 2

P W R B T N#

P M _B A T L OW #

DSWODVREN - On Die DSW VR Enable
P C I E _W A K E # 2 7 , 2 9 , 3 0

S U S _S TA T # / GP I O6 1

S U S W A R N # / S U S P W R D N A C K / G P I O 30

2 2 ,3 4 AC _ PR ESEN T

34

D P W RO K

H _ P M _S Y N C

K 14
RI#

6 ,2 9 ,3 4 ,3 5

3

PM _ SL P_ L AN #

S L P _ L A N # / GP I O2 9

H M 6 5 _B D 8 2 C P MS _ E S 2
3 .3 V

14

U 31D
7 4 L V C 0 8P W
12
3 9 D E L A Y _ P W R GD

3 .3 V
U3 1 C
7 4L V C 0 8 P W

S Y S _ P W RO K

A LL _ S Y S _ P W R G D

7

1 1, 34 , 3 9

C 699
* 0 . 1 u_ 1 0 V _ X 5 R _ 0 4

4
37 1. 8V S _ P W R GD
3 DD R_ 1 .0 5 V S _ P W RG D

1

* 10 m i l _ sh o rt

8
10

14

14
3 8 D D R 1 . 5 V _ P W R GD

R5 7 1

R 572
1 0 K_ 0 4

9

3 7 0 . 8 5V S _ P W R GD
U 31B
7 4 L VC 0 8 PW

U3 1 A
7 4L V C 0 8 P W

1 1 S Y S _ P W R _ OK
13
7

14
3 .3 V
3 .3 V

3 4 P M _P C H _ P W R OK

10/27

6

1 . 0 5 V S _V TT _ E N

5

2

7

7

3 8 1 .0 5 V S _ P W R G D
R 64 9

10 K _0 4
D

3 .3 V
R 584

* 1 0K _ 04

P M _ MP W R O K

1 .0 5 V S _ V T T _ E N # 3 5
Q 32
M T N 70 0 2 Z H S 3

ON

S

G
1 8 , 2 5 RT C V C C
6 , 1 8 , 1 9 , 2 4 , 2 5 , 2 9 , 35 , 3 7 , 3 8 , 3 9 1 . 0 5 V S
2 , 3 , 8 , 1 1 , 1 2 , 1 6, 18 , 1 9 , 2 2 , 2 3 , 2 4 , 2 5, 27 , 2 8 , 2 9 , 3 0 , 3 3 , 3 5, 37 , 3 8 , 3 9 3 . 3 V
3 , 6 , 9 , 1 0 , 1 1 , 1 2 , 1 8, 19 , 2 1 , 2 2 , 2 3 , 2 4 , 2 5, 2 7 , 2 8 , 2 9 , 3 0 , 3 1 , 3 2, 3 3 , 3 4 , 3 5 , 3 9 3 . 3 V S

CougarPoint - M 3/9 B - 21

B.Schematic Diagrams

49 . 9 _ 1 % _ 0 4

DI_ T X N0
DI_ T X N1
DI_ T X N2
DI_ T X N3
DI_ T X N4
DI_ T X N5
DI_ T X N6
DI_ T X N7

F DI_ IN T 2

F D I _I N T
R5 9 9

1 .0 5 V S

F
F
F
F
F
F
F
F

Schematic Diagrams

CougarPoint - M 4/9
CougarPoint -M (LVDS,DDI)

U5 4 D
L _B K LT E N
L _V D D _E N

S D V O_ T V C L K I N N
S D V O _T V C L K I N P

P4 5
L _B K LT C T L

L VD S_ IBG

T45
P3 9
A F37
A F36
A E4 8
A E4 7

A K3 9
A K4 0

11 L V D S -L C L K N
11 L V D S -L C L K P

Sheet 21 of 49
CougarPoint - M 4/9

11 L V D S -L 0 N
11 L V D S -L 1 N
11 L V D S -L 2 N

AN 4 8
AM 4 7
A K4 7
AJ 4 8

11 L V D S -L 0 P
11 L V D S -L 1 P
11 L V D S -L 2 P

AN 4 7
AM 4 9
A K4 9
AJ 4 7
A F40
A F39

11 L V D S -U C L K N
11 L V D S -U C L K P

11

D A C_ B L U E

11

D A C_ G RE E N

11

D A C_ R E D

11 L V D S -U 0N
11 L V D S -U 1N
11 L V D S -U 2N

AH 4 5
AH 4 7
A F49
A F45

11 L V D S -U 0P
11 L V D S -U 1P
11 L V D S -U 2P

AH 4 3
AH 4 9
A F47
A F43

L _C T R L _ C L K
L _C T R L _ D A T A
L V D_ IB G
L V D_ V B G

S D V O _C T R L C LK
S D V O_ C T R L D A TA

L V D S A _C L K #
L V D S A _C L K
L V D S A _D A T A # 0
L V D S A _D A T A # 1
L V D S A _D A T A # 2
L V D S A _D A T A # 3
L V DS A
L V DS A
L V DS A
L V DS A

_D
_D
_D
_D

D DP B _ A UX N
D D P B _ A U XP
D D P B _H P D

ATA0
ATA1
ATA2
ATA3

L V D S B _C L K #
L V D S B _C L K
L V D S B _D A T A # 0
L V D S B _D A T A # 1
L V D S B _D A T A # 2
L V D S B _D A T A # 3
L V DS B
L V DS B
L V DS B
L V DS B

_D
_D
_D
_D

ATA0
ATA1
ATA2
ATA3

* 15 m i _l s h o rt D A C _ B L U E _ R
C7 2 9
C7 3 4
C7 3 8

EMI

R6 1 9
* 33 p _ 5 0V _N P O _0 4
R6 2 4
* 33 p _ 5 0V _N P O _0 4
R6 2 6
* 33 p _ 5 0V _N P O _0 4

R6 1 8
R6 2 3
R6 2 5

* 15 m i _l s h o rt D A C _ GR E E N _ R

N 48
1 5 0_ 1 % _ 04 D A C _ B L U E _ R
1 5 0_ 1 % _ 04 D A C _ GR E E N _R P 4 9
T49
1 5 0_ 1 % _ 04 D A C _ R E D _ R

D AC_ R ED_ R

C R T _B LU E
C R T _G R E E N
C R T _R E D

* 15 m i _l s h o rt

NEAR PCH

11
11
R3 8 8

T39
M 40

1 1 DA C_ DD CA CL K
1 1 DA C_ DD CA DA T A

M 47
M 49

D AC_ H SY N C
D A C_ V S Y NC

1 K _ 1 % _0 4

D A C _I R E F _ R

Connect to GND

T43
T42

P3 8
M3 9
3 .3 VS

L V D_ V R E F H
L V D_ V R E F L

C R T _D D C _ C L K
C R T _D D C _ D A T A

D
D
D
D
D
D
D
D

DPB _ 0 N
D P B _ 0P
DPB _ 1 N
D P B _ 1P
DPB _ 2 N
D P B _ 2P
DPB _ 3 N
D P B _ 3P

D D P C _C T R L C LK
D D P C _ C T R L D A TA

D DP C _ A UX N
D D P C _ A U XP
D D P C _H P D
DD PC_ 0 N
D D P C _ 0P
DD PC_ 1 N
D D P C _ 1P
DD PC_ 2 N
D D P C _ 2P
DD PC_ 3 N
D D P C _ 3P

D D P D _C T R L C LK
D D P D _ C T R L D A TA

C R T _H S Y N C
C R T _V S Y N C
DA C _ IRE F
C R T _I R T N

D DP D _ A UX N
D D P D _ A U XP
D D P D _H P D
DD PD_ 0 N
D D P D _ 0P
DD PD_ 1 N
D D P D _ 1P
DD PD_ 2 N
D D P D _ 2P
DD PD_ 3 N
D D P D _ 3P

AT4 9
AT4 7
AT4 0
AV4 2
AV4 0
AV4 5
AV4 6
A U 48
A U 47
AV4 7
AV4 9

R 42 0

R4 1 9

2 .2 K_ 0 4

2. 2K _0 4

P4 6
P4 2

H D MI _ C TR L C L K 3 2
H D MI _ C TR L D A T A 32

AP4 7
AP4 9
AT3 8

P C H _ C D P C _ H P C R 39 4

A Y 47
A Y 49
A Y 43
A Y 45
BA4 7
BA4 8
BB4 7
BB4 9

H
H
H
H
H
H
H
H

DM
DM
DM
DM
DM
DM
DM
DM

IC_ C
IC_ C
IC_ C
IC_ C
IC_ C
IC_ C
IC_ C
IC_ C

0_04

0C N
0C P
1C N
1C P
2C N
2C P
LK C N
LK C P

DM
DM
DM
DM
DM
DM
DM
DM

IC_ C
IC_ C
IC_ C
IC_ C
IC_ C
IC_ C
IC_ C
IC_ C

0C
0C
1C
1C
2C
2C
LK
LK

32

N 32
P 32
N 32
P 32
N 32
P 32
CN 3 2
CP 3 2

M4 3
M3 6

AT4 5
AT4 3
B H 41
BB4 3
BB4 5
BF4 4
BE4 4
BF4 2
BE4 2
BJ 4 2
B G 42

H M 6 5 _B D 8 2 C P M S _ E S 2

External Graphics (PCH Integrated Graphics Disable)

3 , 6 , 9 , 10 , 1 1 , 1 2 , 18 , 1 9 , 2 0 , 2 2, 2 3 , 2 4 , 2 5, 2 7 , 2 8 , 2 9, 3 0 , 3 1 , 3 2, 33 , 3 4 , 3 5, 39 3 . 3 V S
1 1 , 1 8, 2 4 , 2 5 , 2 7, 2 8 , 3 1 , 3 2, 33 , 3 5 , 3 9, 40 5 V S

B - 22 CougarPoint - M 4/9

P O R T C _H P C
H
H
H
H
H
H
H
H

SDVO

L _ C TR L _C L K
L _ C TR L _D A T A

2. 3 7 K _ 1 % _0 4

A M 42
A M 40
AP3 9
AP4 0

Display Port B

10 K _ 0 4
10 K _ 0 4

R 3 87

S DV O _ INT N
S D V O_ I N TP

AP4 3
AP4 5

Display Port C

R 3 97
R 3 79

L _D D C _ C L K
L _D D C _ D A T A

Digital Display Interface

T40
K4 7

11 P _D D C _ C L K
11 P _D D C _ D A T A

LVDS

Ver:1.0
pull up 2.2K

CRT

B.Schematic Diagrams

3 . 3V S

S D V O_ S T A L L N
S D V O _ S T A L LP

Display Port D

J47
M 45

11
BL O N
1 1 ,3 4 NB _ E N A V D D

Schematic Diagrams

CougarPoint - M 5/9
C ouga rPo int -M (PC I,U SB, NVRA M)
U54
E

0
1
0
1
R415

LPC
Reserved
PCI
SPI
*1K_04

(NAND)

BBS_BIT1

B21
M
20
AY16
BG
46

Flash Descriptor security override strap
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG
32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

LOW = PCI_GNT#3 swap override
PCI_GNT#3
HIGH = Default

Un derstand the RED FONT defi ne
R409

*1K_0
4

R406

*1K_0
4

PCI_GNT#3

TP21
TP22
TP23
TP24

RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24

12,34,37 DGPU_PWR_EN#

R40
7

*0
_04

INT
_PIRQ
A#
INT
_PIRQ
B#
INT
_PIRQ
C#
INT
_PIRQ
D#

K40
K38
H38
G
38

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

DGPU_HO
LD_RST#
DGPU_SELECT
#
D_GPU_PWR_EN#

C46
C44
E40

BBS_BIT1
DG
PU_PWM_SELECT#
PCI_G
NT#3

18,31 SATA_ODD_DA#

INT
_PIRQ
E#
SATA_
ODD_
DA#
INT
_PIRQ
G#
INT
_PIRQ
H#

D47
E42
F46

G
42
G
40
C42
D44

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AC_PRESENT
USB_OC#2
3
USB_OC#8
9
USB_OC#1
213

RN7
10K_8P4R_04
5
4
6
3
7
2
8
1

USB_OC#1
4
USB_OC#6
7
USB_OC#1
011
USB_OC#4
5

RN18
10K_8P4R_04
5
4
6
3
7
2
8
1

INT_PIRQE#
SATA_ODD_DA#
INT_PIRQD#
INT_PIRQA#

3.3V

3.3VS

RN12
10K_8P4R_04
4
5
3
6
2
7
1
8

RN20
10K_8P4R_04
DGPU_HOLD_
RST# 4
5
3
6
DGPU_SELECT#
7
D_GPU_
PWR_EN# 2
INT
_PIRQ
G#
1
8

AV5
AV10

Sheet 22 of 49
CougarPoint - M 5/9

AT8

RSVD26
RSVD27
RSVD28
RSVD29

AY5
BA2

INT_PIRQB#
INT
_PIRQ
C#
INT
_PIRQ
H#
LAN_CLKREQ#

AT12
BF3

RN23
10K_8P4R_04
4
5
3
6
2
7
1
8

19 LAN_CLKREQ
#
DGPU_PWM_SELECT
#

*10K_
04

R400

1 0/ 1 5

INT_PIRQ
E#

MPC Switch Control
MPC OFF -- 0 DEFAULT
MPC ON -- 1

AY7
AV7
AU3
BG4

RSVD25

REQ1
# / GPIO50
REQ2
# / GPIO52
REQ3
# / GPIO54
GNT1# / GPI O
51
GNT2# / GPI O
53
GNT3# / GPI O
55

PIRQE# / GPI O
2
PIRQF# / GPI O
3
PIRQG
#/ G
PIO4
PIRQH# / G
PIO5

USB

0
0
1
1

Boot BIOS Location

PCI

BBS_BIT0

RSVD1
RSVD2
RSVD3
RSVD4

RSVD

B o o t BI O S S t ra p
BBS_BIT1

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

C2
4
A24
C2
5
B25
C2
6
A26
K28
H2
8
E28
D2
8
C2
8
A28
C2
9
B29
N2
8
M2
8
L30
K30
G3
0
E30
C3
0
A30
L32
K32
G3
2
E32
C3
2
A32

C3
3
USBRBIAS#

USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5

28
28
27
27
27
27
27
27
28
28
28
28

U SB PORT0
U SB PORT1
3G
10/22
WLAN
FING ER
CCD
11/10

USB_PN8_FP14 27
USB_PP8_
FP14 27

USB_BIAS

R604

W14X X FINGER

22.6_1%_06

B33
30,34

PME#

R425
PLT_RST#

*0_04

K10
PME#
C6

3,12,28 PLT_RST#

28 PCLK_TPM
19 CLK_PCI_FB
34 PCLK_KBC

R416
R616

*22
_04
22_04

R392

22_04

USBRBI AS

PLTRST#
H49
H43
PCL
K_TPM_PCH
J48
CLK_PCI _
FB_R
K42
CLK_PCI_KBC_R H40

CL
KO
UT_PCI0
CL
KO
UT_PCI1
CL
KO
UT_PCI2
CL
KO
UT_PCI3
CL
KO
UT_PCI4

OC0# / G
PIO
59
OC1# / G
PIO
40
OC2# / G
PIO
41
OC3# / G
PIO
42
OC4# / G
PIO
43
O
C5# / GPI O
9
OC6# / G
PIO
10
OC7# / G
PIO
14

A14
K20
B17
C1
6
L16
A16
D1
4
C1
4

USB_OC#01
USB_OC#23
USB_OC#45
USB_OC#67
USB_OC#89
USB_OC#101
1
USB_OC#121
3
USB_OC#14 R591

USB_OC#01 28

*0_04

AC_PRESENT 20
, 34

HM
65_BD82CPMS_ES2
3.3VS

P IN PL T_ RS T# t o B uf fe r

*0.1u_16V_Y5V_04
5

C69
0

1
4

BUF_PLT_RST# 27,29,30,34

2
3

PLT_
RST#

U53
MC74VHC1G08DFT2
G

R574
100K_
04

2, 3
, 8,11,12,16,18,19,20,23,24,25,27,28,29,30,33,35,37,38,39 3.3V
3, 6
, 9,10,11,12,18,19,20,21,23,24,25,27,28,29,30,31,32,33,34,35,39 3.3VS

CougarPoint - M 5/9 B - 23

B.Schematic Diagrams

BG
26
BJ26
BH25
BJ16
BG
16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM
4
AM
5
Y13
K24
L24
AB46
AB45

Schematic Diagrams

CougarPoint - M 6/9
3. 3V
R569
R295

1K_04
1K_04

CougarPoint - M (GPIO,VSS_NCTF,RSVD)

HOST_ALERT#1
HOST_ALERT#2

3.3VS

10/21

U54F

*10K_04 DGPU_PWROK
1K_04 SATA_ODD_PWRGT
10K_04
MFG_MODE
10K_04
SATA_DET#4

29,34

SMI#

34

R573

3.3V
29

SCI#

R465

OCPPE#

SMI#
DGPU_HPD_INTR#

H36

SCI#

E38

ICC_EN#

C10

10K_04 EDID_SELECT#
*0_04

HOST_ALERT#1

ODD_DETECT# 18

SATA_DET#4

*1K_04
100K_04

PCH_TS_VSS1
PCH_TS_VSS2
PCH_TS_VSS3
PCH_TS_VSS4
11

PLL_ODVR_EN
FDI_OVRVLTG

P L L _O D VR _ E N: H IG H - E N AB L E D[ D E FA U LT ]
L OW - D I SA B L ED

R466

ICPPE#

*0_04

I NT E R NA L G F X : L OW ( DE F A UL T )
E XT E R NA L G F X :H I GH

100K_04

U2

R290

34 CRI T_TEMP_REP#
R296

D40

HOST_ALERT#2

E8

10/2 1

GFX_CRB_DET
R565

TACH2 / GPIO6

TACH6 / GPIO70

TACH3 / GPIO7

TACH7 / GPIO71

31 LED_DGPU#
PCH_MUTE#
SATA_ODD_PRSNT#

E16
P8

B41 PCH_GPIO57

10K_04

BIOS_REC
R287
*0_04

B I OS RE C O VE R Y
D I SA B LE - - -- H IG H (D E FA U L T)
E N AB L E- - - -- L OW

GPIO15

A20GATE
PECI

SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24 / MEM_LED
GPIO27
GPIO28

K4
V8
M5

MFG_MODE

N2

GFX_CRB_DET

M3

TEST_SET_UP

V13

*0_04 CRIT_TEMP_REP#_R

V3
D6

PROCPWRGD
THRMTRI P#
INIT3_3V#
DF_TVS
TS_VSS1

STP_PCI # / GPIO34

R612

1.5K_1%_04

3.3VS

R610

1.5K_1%_04

3.3VS

TS_VSS2

GPIO35
TS_VSS3
SATA2GP / GPIO36
TS_VSS4

R300

P4
AU16HPECI_R
P5

NC_1

KBC_RST#

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17

A4
A44
A45

A5
3. 3V
A6
B3
10K_04

ICC_EN#
B47
R577
*1K_04

I N TE G RA T E D C lo c k C h ip E na b le
I C C_ E N# : HI G H - DI S AB L E D [ DE F A UL T ]
LO W - E NA B LE D

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BD1
BD49
BE1
BE49
BF1
BF49

INIT3_3V#

AY1

NV_CLE

AH8

PCH_TS_VSS1

AK11

PCH_TS_VSS2

390_1%_06
R560

R559

AH10 PCH_TS_VSS3
PCH_TS_VSS4

P37

BG2
BG48
BH3

BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

HM65_BD82CPMS_ES2

6, 24, 37 1.8VS
2, 3,5,24,25,35,39 1.05VS_VTT
2, 3,8,11,12,16,18,19,20,22,24,25,27,28,29,30,33, 35, 37, 38, 39 3.3V
3, 6,9,10,11,12,18,19,20,21,22,24,25,27,28,29,30,31,32, 33, 34, 35, 39 3.3VS

B - 24 CougarPoint - M 6/9

34

H_PECI 3,34

H_CPUPWRGD 3

T14

AK10

GA20

KBC_RST# 34

AY10HTHRMTRIP#_R R318

SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48

3. 3VS
*10K_04 1. 05VS_VTT
*0_04

AY11

SATA3GP / GPIO37
SLOAD / GPI O38

10K_04

R320
R316

VSS_NCTF_18

A46

R414

R609

A40 GPIO71

BH47
R288

SATA_ODD_PWRGT 31
1.5K_1%_04

C41 GPIO70

GPIO8

K1

FDI_OVRVLTG

100K_04 TEST_DET

C40 SATA_ODD_PWRGT

LAN_PHY_PWR_CTRL / GPIO12
G2

T5

SB_BLON

SB_BLON

18,31 SATA_ODD_PRSNT#
*10K_04

TACH5 / GPIO69

C4

BIOS_REC

PLL_ODVR_EN
29,34

3. 3VS
R555

TACH4 / GPIO68

TACH1 / GPIO1

NCTF

B.Schematic Diagrams

R299
R314

Sheet 23 of 49
CougarPoint - M 6/9

*10mil_short
*10mil_short
*10mil_short
*10mil_short

BMBUSY# / GPI O0

RCIN#
DGPU_PWROK

R326
R310
R319
R311

T7
A42

CPU/MISC

RN22
10K_8P4R_04
1
8
KBC_RST#
2
7
DGPU_HPD_INTR#
3
6
SCI #
4
5
SMI #
R302
200K_04 SATA_ODD_PRSNT#
RN17
10K_8P4R_04
1
8
S_GPIO
2
7
ODD_DETECT#
3
6
TEST_SET_UP
4
5
CRIT_TEMP_REP#_R

S_GPIO

GPIO

R401
R402
R554
R551

1K_04

H_THRMTRIP# 3
2.2K_04 1.8VS
H_SNB_IVB# 3

DMI & FDI Termination Voltage
NV_CLE

Set to Vss when LOW
Set to Vcc when HIGH

P L A CE R4 6 4 C L OS E TO TH E BR A NC H I NG PO I N T
( T O C PT a nd NV R A M C ON N E CT O R

Schematic Diagrams

CougarPoint - M 7/9
CougarPoint -M (POWER)

3 . 3V S
L5 2
H C B 16 0 8 K F -1 2 1T 2 5

.

POWER

C4 9 4

1u _ 6 . 3 V _ X5 R _0 4

C 4 67

1 u _ 6. 3 V _ X 5 R _ 0 4

1. 0 5 V S

1u _ 6 . 3 V _ X5 R _0 4

1 . 0 5 V S _ V C C A P L L _E XP

CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC

OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR

E[1 ]
E[2 ]
E[3 ]
E[4 ]
E[5 ]
E[6 ]
E[7 ]
E[8 ]
E[9 ]
E [ 1 0]
E [ 1 1]
E [ 1 2]
E [ 1 3]
E [ 1 4]
E [ 1 5]
E [ 1 6]
E [ 1 7]

VC CA_ D AC_ 3 .3 VS
V CC A DA C

U4 8

1mA
C7 3 1

C7 3 7

C 7 42

C7 4 0

0 . 0 1 u _1 6 V _ X 7R _ 04

0 . 1 u_ 1 0 V _ X5 R _0 4

1 0u _ 6 . 3 V _X 5 R _0 6

0 . 1 u _ 10 V _ X 5 R _ 0 4

2 2u _ 6 . 3 V _X 5 R _ 0 8

3 .3 V S
R 36 5

AK3 7

.

HVCMOS

V C C I O [ 1 6]
A N2 1

1 . 8V S _ V C C TX _ L V D

V C C I O [ 1 7]

.

AP3 6

C5 3 0

C5 3 6

C 5 43

AP3 7

0. 0 1 u _1 6 V _ X 7R _ 0 4

0. 01 u _ 16 V _ X 7 R _ 0 4

2 2 u _6 . 3 V _ X 5R _ 08

C5 2 8
V C C 3_ 3 [ 7 ]

V3 4

V C C I O [ 1 9]
C 5 03

C 5 05

C 48 5

AP2 1

1 u _ 6. 3 V _ X 5 R _ 0 4

1 u _ 6. 3 V _ X 5 R _ 0 4

1 u _6 . 3 V _ X 5 R _ 0 4

AP2 3

G ND

APL5603-33B 6-02-56033-4C0
G9091-330T11UF 6-02-90913-4C0

0. 1 u _ 10 V _ X 5 R _ 0 4

AT 1 6

160mA

AT 2 0

42mA

V CC V RM [3 ]

V C C I O [ 2 0]

AP2 6
V C C I O [ 2 3]
V C C I O [ 2 4]

1 .0 5 VS _ V T T

V CC DM I[1 ]

VCCIO

V C C I O [ 2 2]

DMI

V C C I O [ 2 1]
AP2 4

A T2 4

SET

* A P L 56 0 3 -3 3B

1 . 5 V S _ 1 . 8V S
V C C I O [ 1 8]

1 u _ 6. 3 V _ X 5 R _ 0 4

2

Sheet 24 of 49
CougarPoint - M 7/9

266mA

V C C 3_ 3 [ 6 ]

A N2 7
C 4 95

L3 9
1 .8 V S
H C B 1 60 8 K F -1 2 1T 2 5

60mA

A M 38
V C C T X _L V D S [ 2 ]

A N2 6

1 0 u _6 . 3 V _ X 5 R _ 0 6

C 74 1
SH DN #

*1 u _ 6. 3V _ X 5 R _ 0 4
A M 37

3 . 3V S

V C C I O [ 1 5]

C 4 77

R 6 27

* 1 5m i l _s h o rt _ 06

C5 2 3

VSSAL VD S

V C C T X _L V D S [ 1 ]

V C C T X _L V D S [ 4 ]

A N1 7

2.92A

* 2 3. 7 K _ 1 % _0 4
4
SET

* 1 0K _ 1 % _ 04

V3 3

2.93A

1

R6 3 0

3 . 3V S _V C C A _L V D

1mA

AK3 6

V C CA P L L E X P

*1 0 u _ 6. 3 V _ X 5 R _ 0 6

IN

V C C I O [ 2 8]

A N1 6

1. 0 5 V S

OU T

3

B J2 2

C 70 1

5

C4 5 8

2mA
AB3 6
V C CC L K DM I

V C C C LK D MI

R 37 5
*1 5 m il _ s ho rt _ 0 6

C4 5 4

1 u _6 . 3 V _ X 5R _ 04

1 . 05 V S

1 0 u_ 6 . 3 V _ X5 R _0 6

A N3 3
V C C I O [ 2 5]
A N3 4
3 .3 V S

266mA

V C CD F T E RM [1 ]

V C C 3 _ 3 [ 3]

V C CD F T E RM [2 ]

1 . 5 V S _ 1 . 8V S

0 . 1 u _ 10 V _ X 5 R _ 0 4
AP1 6
1 . 0 5V S _V C C A P LL _ F D I
R3 2 4

1. 0 5 V S

V C C V R M[ 2 ]
B G6

* 0 _0 6

V _ N V R A M _V C C Q
A G 17

DFT / SPI

160mA

C 6 93

A G 16
V C C I O [ 2 6]

B H2 9

V c c A F D IP L L

190mA

R 5 58
C4 5 6

V C CD F T E RM [3 ]

R5 6 1

V C CD F T E RM [4 ]
V C CM E 3 .3 V

3 .3 V S

1. 05 V S

1 .5 VS

VC CS PI

V1

20mA

R 55 7

3 .3 V

* 0 _0 4
* 1 5m i l _s h o rt _ 06

C 694
1 u _ 6 . 3V _X 5 R _ 0 4

R 34 8

1 .0 5 VS _ VT T

V C C D MI [ 2 ]

FDI

V C C I O [ 2 7]
A U2 0

*0 _ 04

0. 1 u _ 1 0V _ X 5 R _ 0 4
AJ 1 7

R5 5 0

1 .0 5 S _ V CC _ DM I

3. 3 V S

AJ 1 6

AP1 7

42mA

1 .8 V S
*1 5 m il _ sh o rt _ 0 6

* 1 5m i l _s h o rt _ 06

1 .8 VS

H M6 5 _ B D 8 2 C P M S _ E S 2

1 . 5 V S _ 1 . 8V S

R 42 2
R 33 1
R 62 2

*0 _ 0 4
* 1 0m i l _s h o rt
*0 _ 0 4

6 , 9, 10 , 3 5 1 . 5V S
2 5 1 . 5 V S _ 1 . 8V S
6, 2 3 , 3 7 1 . 8V S
6 , 18 , 1 9 , 2 0, 25 , 2 9 , 3 5, 3 7 , 3 8 , 39 1 . 0 5 V S
11 , 1 8 , 2 5, 2 7 , 2 8 , 31 , 3 2 , 3 3, 3 5 , 3 9 , 40 5 V S
2 , 3 , 5 , 23 , 2 5 , 3 5, 3 9 1 . 0 5 V S _ V TT
2 , 3 , 8 , 11 , 1 2 , 1 6, 18 , 1 9 , 2 0, 2 2 , 2 3 , 25 , 2 7 , 2 8, 2 9 , 3 0 , 33 , 3 5 , 3 7, 38 , 3 9 3 . 3V
3 , 6 , 9, 1 0 , 1 1 , 12 , 1 8 , 1 9, 20 , 2 1 , 2 2, 2 3 , 2 5 , 27 , 2 8 , 2 9, 3 0 , 3 1 , 32 , 3 3 , 3 4, 35 , 3 9 3 . 3V S

CougarPoint - M 7/9 B - 25

B.Schematic Diagrams

A N1 9
1 . 0 5 V S _ V C C A P L L _E XP 1

V C CA _ DA C3 .3 V S

C 7 30

V C CA L V D S

*1 0 m il _ s ho rt

L47
* B K P 1 0 0 5H S 1 2 1_ 0 4

U 55

.

U4 7
V S S A DA C

V C C T X _L V D S [ 3 ]
R 5 97

5 VS

L5 1
H C B 16 0 8 K F -1 2 1T 2 5

* 1u _ 6 . 3 V _X 5R _ 04

C 5 14

1 0u _ 6 . 3 V _ X5 R _0 6

VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC

CRT

C4 7 8

AA2 3
A C2 3
A D2 1
A D2 3
AF2 1
AF2 3
A G2 1
A G2 3
A G2 4
A G2 6
A G2 7
A G2 9
A J2 3
A J2 6
A J2 7
A J2 9
A J3 1

LVDS

1.3A

VCC CORE

U 5 4G

1 . 0 5V S

Schematic Diagrams

CougarPoint - M 8/9
CougarPoint - M (POWER)

CougarPoint power supply range

1 . 05 V S _ V C C A _ C L K
L50
*H C B 1 0 0 5K F -12 1 T 20
1 . 0 5V S

Note: C417 - STUFFED ONLY FOR CPT INTERPOSER;
UNSTUFF FOR CPT

3mA

V C C I O [ 29 ]

V CC DS W 3 _ 3

1u _ 6 . 3 V _X 5 R _ 0 4
P 28

C4 4 9

.

*0 . 1u _ 1 0 V _X 5 R _ 0 4 P C H _ V C C D S W

2 66 mA

V C C3 _ 3

C 7 32

C 5 32

1 0 u _6 . 3 V _ X 5R _ 06

1u _ 6 . 3V _ X 5 R _ 0 4

.

L48

V1 2

97 mA

V C C I O [ 32 ]

V C C 3_ 3 [ 5 ]
T23
V C C S U S 3 _ 3[ 7 ]
V C C A P LL D MI 2

C4 6 1

C 5 02

0. 1u _ 1 0V _ X 5 R _ 0 4

0 . 1 u _1 0 V _ X 5R _ 04

T24
V C C S U S 3 _ 3[ 8 ]

AL 2 9
V C C I O[ 1 4 ]

V 23

USB

D CPS U S

*0 . 1u _ 1 6 V _Y 5 V _0 4

AL 2 4
D CP S US [3 ]

V C C S U S 3 _ 3[ 9 ]
V 24

D1 5
C

1mA

V C C S U S 3 _ 3 [ 10 ]

R 3 70

AA1 9

1 0_ 1 % _0 4

V CC A S W [1 ]

1.0 1A

V C C I O [ 34 ]

AA2 1

1. 0 5 V S

T26

0 . 1u _ 1 0V _ X 5 R _ 0 4

AA2 6
V CC A S W [4 ]
AA2 7
V CC A S W [5 ]
AA2 9
V CC A S W [6 ]
AA3 1

C 4 80

C4 8 4

2 2 u _6 . 3 V _ X 5R _ 08

1u _ 6 . 3V _ X 5 R _ 0 4

V CC A S W [7 ]
AC 2 6
V CC A S W [8 ]
AC 2 7
V CC A S W [9 ]
AC 2 9
V C C A S W [ 1 0]
AC 3 1

C 4 86
AD 2 9
1 u _ 6. 3V _ X 5 R_ 0 4
AD 3 1
W21

V C C A S W [ 1 1]
V C C A S W [ 1 2]
V C C A S W [ 1 3]
V C C A S W [ 1 4]

W23

V 5 R E F _ S US

V C C A S W [ 1 5]

Note: C1289- STUFFED ONLY FOR CPT INTERPOSER;
UNSTUFF FOR CPT

M 2 6 5 V A _ PC H_ V CC 5 RE F S U S
A N2 3

V C CA _ U S B S US

C4 6 5

* 1u _ 6 . 3V _X 5 R_ 0 4

DC P S US [4 ]
A N2 4

3 . 3V

V C C S U S 3 _ 3[ 1 ]

5V S _P C H _ V C C 5 R E F S U S
P 34

1mA

N 20

97mA

D 17
C

R B 7 51 S -4 0 C 2
A

V 5 RE F

PCI/GPIO/LPC

1u _ 6 . 3V _ X 5 R _ 0 4

Clock and Miscellaneous

V CC A S W [3 ]

C5 1 7

2 2 u _6 . 3 V _ X 5R _ 08

5V

C5 0 7

1 . 0 5V S

V CC A S W [2 ]
AA2 4
C 4 81

R B 7 5 1 S -4 0C 2
A
3 .3 V

P 24
V C C S U S 3 _ 3[ 6 ]

Sheet 25 of 49
CougarPoint - M 8/9

Max
1.10V
1.58V
1.89V
3.47V
5.25V

T29
V C C I O [ 33 ]

T38
BH 2 3

V C C A P L L _C P Y _ P C H
*H C B 1 6 0 8K F -12 1 T 25

C4 7 6

3. 3 V
T27

D CP S US B Y P

1. 0 5 V S

V C C A S W [ 1 6]

3 .3 VS
R3 6 7

V C C S U S 3 _ 3[ 2 ]

1 0 _ 1% _ 0 4

5 VS

C 51 8
N 22

V C C S U S 3 _ 3[ 3 ]

1 u _ 6. 3 V _ X 5R _ 04
P 20

V C C S U S 3 _ 3[ 4 ]
P 22

3. 3V

V C C S U S 3 _ 3[ 5 ]
V C C 3 _ 3[ 1 ]

C 48 7

266mA

A A 16

3 .3 VS

W 16

C 52 2

C7 1 1

C 4 66

T34

0 . 1 u _1 0 V _ X5 R _0 4

0 . 1u _ 1 0V _X 5 R _ 0 4

0 . 1 u _ 10 V _ X 5R _ 04

1 u _6 . 3 V _ X 5R _ 04

V C C 3 _ 3[ 8 ]

W24
V C C 3 _ 3[ 4 ]

W26
V C C A S W [ 1 7]

C4 6 0

W29

0. 1 u _ 10 V _ X 5R _ 04

V C C A S W [ 1 8]
W31

1 . 5 V S _ 1. 8 V S

1 .0 5 V S

V C C A S W [ 2 0]

1. 0 5 S _ S A T A 3
A F 13

2.92A

C 73 3

C 5 47

2 2 u_ 6 . 3 V _ X5 R _0 8

1 u _ 6. 3 V _ X 5 R _ 04

1 . 05 V S

N 16

C 44 7

D CP RT C

A H1 3
V C C I O [ 12 ]

1 6mA

C 73 9

Y 49

R4 0 3

1 u _ 6. 3 V _ X 5R _ 04
A H1 4

V C C V R M [ 4]

V C C I O [ 13 ]

*0 _ 0 4 1. 05 V S _ V C C A _ B _ D P L

80mA
80mA

10/18

V C C I O[ 6 ]

BD 4 7
V CC A DP L L A

SATA

*2 2 0 u_ 6 . 3 V _ 6. 3 * 4. 2

BF4 7
V CC A DP L L B

H C B 1 0 0 5 K F -1 21 T 2 0
C 72 4

C7 2 7

C 71 9

C5 4 0

* 22 u _ 6 . 3V _ X 5 R _0 8

*2 2 u _6 . 3 V _ X 5 R _ 0 8

2 2 u _6 . 3 V _ X 5 R _ 0 8

1 u_ 6 . 3 V _X 5 R _ 0 4

1. 0 5 V S

AF1 7
AF3 3
AF3 4
AG 3 4

150mA

C 4 79

C 45 5

1 u _ 6. 3V _ X 5 R _ 0 4

1 u _6 . 3 V _ X 5R _0 4

V
V
V
V

CC
CC
CC
CC

I O[ 7 ]
D I F F C LK N [ 1 ]
D I F F C LK N [ 2 ]
D I F F C LK N [ 3 ]

V C C A P LL S A T A

1. 0 5 V S

V1 6

C 4 69

1 . 0 5 M_ V C C S U S
*1 u_ 6 . 3 V _ X5 R _0 4

T17
V1 9

0 . 1 u _ 10 V _ X 5R _ 04

0. 1 u _ 10 V _ X 5 R _ 04

2mA

A D1 7

C7 0 8

C 7 10

C7 1 5

1 u_ 6 . 3 V _ X5 R _ 0 4

0 . 1 u _ 10 V _ X 5R _ 04

0. 1 u _ 10 V _ X 5 R _ 04

C 45 3

V C C I O[ 4 ]

*0 _ 06
0_ 0 6

1 u _ 6. 3 V _ X 5R _ 04

D CP S US [1 ]
D CP S US [2 ]

V _P R OC _ I O

A2 2

1.01A
1. 05 V S

V C C A S W [ 22 ]

H M 65 _ B D 8 2 C P MS _ E S 2

MISC

BJ 8

T21

V CC RT C
RT CV C C

3. 3 A _ 1 . 5 A _H D A _I O

R 60 7
R 60 8

D CP S S T

CPU

4 . 7u _ 6 . 3V _X 5 R _ 0 6

1 .5 V

A C1 7

RTC

<1mA
1. 0 5 V S _ V T T
C4 5 1

3 .3 V

A C1 6
V C C I O[ 2 ]

V CC S S C
0 . 1 u_ 1 0 V _X 5 R _ 0 4 V C C S S T

C 4 46

1 . 05 V S

1 . 5V S _1 . 8 V S

A F 11
V C C V R M[ 1 ]

AG 3 3

C 4 48

C4 5 0

L4 6
*H C B 1 0 05 K F -1 2 1 T2 0
1 . 05 V S _ V C C A P L L _ S A T A 3

V C C I O[ 3 ]

1 . 0 5V S
C 4 96

A F 14
A K1

1 u _ 6. 3 V _ X 5 R _ 0 4

V C C A S W [ 23 ]

V 21
T19

V C C A S W [ 21 ]

3 . 3A _1 . 5 A _ V C C P A Z S U S
3 . 3 A _ 1. 5 A _ H D A _ I O
P 32

16mA

R 61 3

V CC S US H DA
C5 0 6

0. 1 u _ 10 V _ X 7 R _ 0 4

B - 26 CougarPoint - M 8/9

L 32
H C B 1 00 5 K F -1 2 1T 2 0

V C C I O[ 5 ]
V C C R T C E XT

L36

V C C 3 _ 3[ 2 ]

W33

L38
H CB 10 0 5 K F -1 21 T 2 0

+

A J2
V C C A S W [ 1 9]

1 . 0 5 V S _ V C C A _ A _D P L

HDA

B.Schematic Diagrams

C5 1 6
P 26

V C C I O [ 30 ]

T16

V C C I O [ 31 ]

L49
H C B 1 6 0 8K F -12 1 T 25

1. 0 5 V S

N 26
V CC A CL K

0. 1 u _ 10 V _ X 5R _ 04

Voltage
1.05V
1.5V
1.8V
3.3V
5V

Min
1.00V
1.43V
1.71V
3.14V
4.75V

2 .92 A

AD 4 9

C 4 82

3. 3 V S

POWER

U5 4 J

3 .3 V

1 . 0 5V S

*1 5 mi l _ sh o rt _ 0 6

1 8 3. 3A _ 1 . 5 A _ H D A _I O
1 8 ,2 0
RT C V CC
2 4 1 . 5 V S _ 1 . 8V S
6 , 1 8 , 19 , 2 0 , 2 4, 2 9 , 3 5, 37 , 3 8 , 39 1 . 0 5 V S
3 , 6 , 8, 9, 1 0 , 2 9, 3 3 , 3 5 , 37 , 3 8 1 . 5V
2 , 3 , 5 , 2 3, 2 4 , 3 5 , 39 1 . 0 5 V S _ V TT
1 1 , 1 8 , 24 , 2 7 , 2 8, 3 1 , 3 2, 3 3 , 3 5 , 39 , 4 0 5 V S
2 , 3 , 8, 11 , 1 2 , 16 , 1 8 , 1 9, 2 0 , 2 2, 2 3 , 2 4 , 27 , 2 8 , 2 9, 3 0 , 3 3, 3 5 , 3 7 , 38 , 3 9 3 . 3V
3 , 6 , 9, 1 0 , 1 1, 12 , 1 8 , 19 , 2 0 , 2 1, 2 2 , 2 3, 2 4 , 2 7 , 28 , 2 9 , 3 0, 3 1 , 3 2, 3 3 , 3 4 , 35 , 3 9 3 . 3V S
2 7, 2 8 , 2 9, 3 5 , 3 7 , 38 , 4 1 5 V

Schematic Diagrams

CougarPoint - M 9/9
CougarPoint -M (GND)
U54I
U54H
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG2
9
N24
AJ3
AD4
7
B43
BE10
BG4
1
G14
H16
T36
BG2
2
BG2
4
C22
AP13
M14
AP3
AP1
BE16
BC1
6
BG2
8
BJ28

H5
VSS[ 0]
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

VSS[ 1]
VSS[ 2]
VSS[ 3]
VSS[ 4]
VSS[ 5]
VSS[ 6]
VSS[ 7]
VSS[ 8]
VSS[ 9]
VSS[ 10
]
VSS[ 11
]
VSS[ 12
]
VSS[ 13
]
VSS[ 14
]
VSS[ 15
]
VSS[ 16
]
VSS[ 17
]
VSS[ 18
]
VSS[ 19
]
VSS[ 20
]
VSS[ 21
]
VSS[ 22
]
VSS[ 23
]
VSS[ 24
]
VSS[ 25
]
VSS[ 26
]
VSS[ 27
]
VSS[ 28
]
VSS[ 29
]
VSS[ 30
]
VSS[ 31
]
VSS[ 32
]
VSS[ 33
]
VSS[ 34
]
VSS[ 35
]
VSS[ 36
]
VSS[ 37
]
VSS[ 38
]
VSS[ 39
]
VSS[ 40
]
VSS[ 41
]
VSS[ 42
]
VSS[ 43
]
VSS[ 44
]
VSS[ 45
]
VSS[ 46
]
VSS[ 47
]
VSS[ 48
]
VSS[ 49
]
VSS[ 50
]
VSS[ 51
]
VSS[ 52
]
VSS[ 53
]
VSS[ 54
]
VSS[ 55
]
VSS[ 56
]
VSS[ 57
]
VSS[ 58
]
VSS[ 59
]
VSS[ 60
]
VSS[ 61
]
VSS[ 62
]
VSS[ 63
]
VSS[ 64
]
VSS[ 65
]
VSS[ 66
]
VSS[ 67
]
VSS[ 68
]
VSS[ 69
]
VSS[ 70
]
VSS[ 71
]
VSS[ 72
]
VSS[ 73
]
VSS[ 74
]
VSS[ 75
]
VSS[ 76
]
VSS[ 77
]
VSS[ 78
]
VSS[ 79
]

VSS[ 80]
VSS[ 81]
VSS[ 82]
VSS[ 83]
VSS[ 84]
VSS[ 85]
VSS[ 86]
VSS[ 87]
VSS[ 88]
VSS[ 89]
VSS[ 90]
VSS[ 91]
VSS[ 92]
VSS[ 93]
VSS[ 94]
VSS[ 95]
VSS[ 96]
VSS[ 97]
VSS[ 98]
VSS[ 99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM
11
AM
14
AM
36
AM
39
AM
43
AM
45
AM
46
AM
7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

S0 Iccmax Current (A)
1 (mA)
1 (mA)
1 (mA)
0.266
1 (mA)
0.08
0.08
1.3
0.042
2.925
1.01
0.020
2 (mA)
0.19
0.097
1 (mA)
0.16
0.02
0.095
0.055
1 (mA)
0.06

Sheet 26 of 49
CougarPoint - M 9/9

HM65_BD82CPM
S_ES2

HM65_BD82CPMS_ES2

CougarPoint - M 9/9 B - 27

B.Schematic Diagrams

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

Voltage Rail Voltage
V_CPU_IO
1.05
V5REF
5
V5REF_Sus
5
Vcc3_3
3.3
VccADAC3
1.05
VccADPLLA
1.05
VccADPLLB
1.05
VccCore
1.05
VccDMI
1.1
VccIO
1.05
VccASW
1.05
VccSPI
3.3
VccDSW3_3
3.3
VccDFTERM
1.8
VccSus3_3
3.3
VccSusHDA
3.3
VccVRM
1.5
VccClKDMI
1.05
VccSSC
1.05
VccDIFFCLKN
1.05
VccALVDS
3.3
VccTX_LVDS
1.8

Schematic Diagrams

C 5 75

2 2 0u _ 6 . 3V _ 6 . 3 *6 . 3 *4 . 2

C 5 82
J _ 3 G1
1
3
5

W AKE#
C OE X 1
C OE X 2

7
11
13
9
15

3G _3 . 3 V

C
R
R
G
G

3 . 3V A U X _0
1 . 5 V _0
U I M _P W R
U I M_ D A T A
U I M_ C L K
U I M_ R E S E T
U I M_ V P P

LK R E Q#
E F CL KE F CL K+
ND0
ND1

3G _ 3. 3 V
UIM
UIM
UIM
UIM
UIM

_P W R
_D A T A
_C LK
_R S T
_V P P

3 .3 V S_ F P
1
2
3
4

C4 4
0 . 1 u_ 1 6V _Y 5V _ 0 4

4

1

U S B _ P N 8_ F P 1 4 2 2
US B _ P P 8 _ F P 1 4 2 2

>48 mil

1 0 /2 2
3 G_ 3 . 3V

>48 mil

C 29 2
C7 4 4
C7 4 3

0 . 1 u_ 1 6V _Y 5V _ 0 4

Port 4

* 85 2 0 1-0 4 0 51
GN D

2

OP E N _ 2A
Q4 8
A O 3 41 5
S
D

3 .3 V

L18
3 .3 VS
H C B 1 60 8 K F -1 2 1T 2 5

J _ F P1

GN D 5

P J 43

W140HN ONLY

60 mil s

2
6
8
10
12
14
16

3G POWER

FP CONN

GN D

0. 1 u _ 16 V _ Y 5 V _ 0 4

1 u _6 . 3 V _ X5 R _0 4

C7 4 5

G

MINI CARD

.

3G/MSATA

+

WLAN, 3G, Mini PCIE

1 0u _ 1 0V _ Y 5V _ 0 8

0 . 1 u_ 1 6V _Y 5V _ 0 4

C2 9 5

R 63 8

R6 4 0

1 u_ 1 0 V _Y 5V _0 6

1 0 K _ 04

C 14 0

KEY

*0 _ 04

3 . 3V A U X _1
1 . 5 V _1
1 . 5 V _2
3 . 3V A U X _2
LE D _ W W A N #
L E D_ W L A N#
LE D _ W P A N #

3 G_ E N

D

34

From H8 default HI
U S B _P N 2 22
U S B _P P 2 22

6 0mi ls

24
28
48
52
42
44
46

CPU FAN CONTROL

3G _ 3. 3 V

C6 1 4

2 2 0u _ 6 . 3V _ 6 . 3 *6 . 3* 4 . 2

5V S
5V S _F A N

C 39 6

S P T4
S MD 7 9 X 13 8

S P T3
S MD 7 9 X 13 8

SPT 1
S M D 7 9 X1 3 8

G ND

F ON 1
2
3
4

FO N
VIN
V O UT
VSE T

G
G
G
G

5 VS_ F AN

33
33

34

1
1

1
1

1

1

1

1
2
3

1 0u _ 1 0V _ Y 5V _ 0 8

33

SP DIF O

L26

8 52 0 5 -03 7 0 1

R 5 42

3 .3 V S

WLAN MINI CARD
20 mil

3 . 3V
19 W L A N _ C LK R E Q#
19 C L K _ P C I E _M I N I #
19 C LK _ P C I E _M I N I

R 6 29

1 0 K _0 4
7
11
13
9
15

C
R
R
G
G

3 .3 V AUX _ 0
1 .5 V _ 0
U I M_ P W R
U I M_ D A T A
U I M_ C L K
U I M_ R E S E T
U I M_ V P P

L K R E Q#
E F CL KE F CL K+
ND 0
ND 1

G ND 5

2
6
8
10
12
14
16

19
19
19
19
31 , 3 4

35
23
25
31
33

34
W LA N _ D E T #
P C I E _ R XN 3_ W L A N
P C I E _ R X P 3 _ W LA N
P C I E _ T XN 3_ W L A N
P C I E _ TX P 3 _ W LA N
* 0_ 0 4 B T _ E N _ R

R6 3 1

BT_ EN

3 .3 V

19
19
19

R6 3 2
R6 3 3
R6 3 4
R6 3 6

C L _C L K 1
C L _D A T A 1
C L _R S T #1
3 . 3V

*
*
*
*

0_ 0 4
0_ 0 4
0_ 0 4
10 K _ 0 4

CL _ CL K _ 1
CL _ DA T A_ 1
C L _ R S T # _1
P C H _B T_ E N _ #

17
19
37
39
41
43
45
47
49
51

G ND 2
G ND 3
G ND 4
G N D 11
P E Tn 0
P E Tp 0
P E Rn 0
P E Rp 0
R e se rv e d 0
R e se rv e d 1
G N D 12
3 .3 VA UX_ 3
3 .3 VA UX_ 4
G N D 13
R e se rv e d 2
R e se rv e d 3
R e se rv e d 4
R e se rv e d 5

G ND 6
G ND 7
G ND 8
G ND 9
GN D 1 0
W _ D I S A B LE #
PER SET #
S MB _ C L K
S MB _ D A T A
USB _ DUS B _ D +
3 .3 V AUX _ 1
1 .5 V _ 1
1 .5 V _ 2
3 .3 V AUX _ 2
L E D_ W W A N #
L E D_ W L A N #
L E D_ W P A N #

R6 2 8

*0 _ 0 4

R6 5 5

1 0K _0 4

1 9 P C H _ B T _E N #

B - 28 WLAN, 3G, Mini PCIE

R 6 35

0 _ 04

R 6 37

* 0_ 0 4

U SB_ PP1

R 53 7
R 54 1
R 54 6
R 54 8

24
28
48
52
42
44
46

0 _0 4
*0 _ 04
0 _0 4
*0 _ 04

U I M_ P W R

A U DG
U S B _ P N1 _ CN1
U S B _ P N1 _ CN2
U S B _ P P 1_ C N 1
U S B _ P P 1_ C N 2

3 IN1

U I M _C
R7 4

*1 0 mi l _ sh o rt

B T_ D E T# 3 4
U S B _ P N3 2 2
U SB_ PP3 2 2

20 mil
R4 1 2

40 mil

0 _0 4

U I M_ D A T A

(T OP VI EW)
D E TE C T _S W
U I M_ D A T A
U I M_ C L K
U I M_ R S T
U I M_ P W R

U I M _M C M D
U I M _I / O
U I M_ V P P
U I M_ GN D

8
6
4
2

*2 2 p_ 5 0 V _N P O_ 0 4

G ND
GN D
3 . 3V

Port 3
3 . 3V

9
7
5
3
1

9 17 1 2 -00 9 0P
C7 7

0 . 1u _ 1 6V _ Y 5 V _ 0 4

3 . 3V S
W L A N _E N 2 8, 3 4
B U F _ P LT _ R S T # 2 2, 2 9 , 3 0, 3 4

20 mil

* 4 . 7K _ 0 4

J _ S I M1

34

C1 1 3
R4 1 3
*1 0 K _ 04

3 . 3V A U X _1

R8 5

P C H _ B T_ E N # 1 9
8 0C LK
34

GN D

R8 9
*1 0 m li _ sh o rt
U I M_ D

U I M _D A T A
U I M _V P P

C1 1 5

C1 1 4

C 1 27

G ND
R3 8 2
4 7K _ 0 4

3 .3 V
B T _D E T #
W L A N _ LE D # 3 1
C5 3 7
* 18 0 p _5 0 V _ N P O_ 0 4

B T_ E N

U S B _ P N1

22

V DD 3

88 9 1 0-5 2 04 M -01
3 1, 34

22

U I M_ C LK
U I M_ R S T
U I M_ P W R

20
22
30
32
36
38

*8 71 5 1 -20 0 7 G
1 00 0 p _5 0 V _ X7 R _ 0 4

4

18
26
34
40
50

1
NC1
NC2

10/15

SIM CONN

20 mil

KE Y
21
27
29

JSW1
20

3 . 3V

J_ M I N I 1
W A KE#
C OE X 1
C OE X 2

C4 1 9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

3
4 . 7K _ 0 4
1

1
3
5

U S B _ P N 1_ C N 1
US B_ P P 1 _ CN1
S P D I F O _R
F C M1 00 5 K F -1 2 1T 0 3

J_FAN1

34 C P U _ F A N S E N

P CIE_ W A KE #

S P K _H P #

CO-lay

GN D

1 0 /2 2

M I C 1 -R
M I C 1 -L
A U DG
H E A D P H ON E -R
H E A D P H ON E -L
J D_ S E N SE
SPK_ H P#
J D_ S E N SE _ B
S P K O U T R -_ R
S P K O UT R+ _ R
G ND
U S B _ P N 1 _C N 2
U S B _ P P 1_ C N 2
87 2 13 -1 6 00 G S P D I F O_ R

33 JD _ S E N S E _ B
33 S P K O U T R -_ R
33 S P K O U T R + _ R

C PU _F AN

C3 9 9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

MI C 1 -R
MI C 1 -L

33 H E A D P H ON E -R
33 H E A D P H ON E -L
33 JD _ S E N S E

P 27 9 3 A

0 . 1 u_ 1 6 V _Y 5 V _0 4

H1 0
H6 D2 _ 8

ND
ND
ND
ND

8
7
6
5

J _ F A N1

20 , 2 9 , 30 P C I E _W A K E #

J_ C N 2

U3 0

+

G ND

5V

5V

J _C N 1

C P U _F A N

SPT 2
S MD 79 X 1 38

FOR AUDIO BOARD

3G _ 3. 3 V

8 8 9 08 -5 2 04 M-0 1
GN D

Q 47
M TN 7 00 2 Z H S 3

G

3 G_ P OW E R

S

34

20
22
30
32
36
38

10 0 K _ 04

*2 2p _ 5 0V _ N P O _ 0 4

R 6 44

R es e rv e d0
R es e rv e d1
G ND1 2
3 .3 VA UX_ 3
3 .3 VA UX_ 4
G ND1 3
R es e rv e d2
R es e rv e d3
R es e rv e d4
R es e rv e d5

R 6 39

Port 2

*2 2 p_ 5 0 V _N P O _ 0 4

GN D

3 G _E N

1 0u _ 1 0V _ Y 5 V _ 08

0. 1u _ 16 V _ Y 5 V _ 04

G ND

C6 1 2

W _ D I S A B LE #
P E R S E T#
S MB _ C L K
S MB _ D A T A
U SB _ DUS B _ D+

18
26
34
40
50

*2 2 p _5 0 V _ N P O _ 0 4

60 mil s
C6 1 1

G ND1 1
PET n 0
PET p 0
P E R n0
P E R p0

17
19
37
39
41
43
45
47
49
51

3G _ 3. 3 V

Sheet 27 of 49
WLAN, 3G, Mini
PCIE

GN D 6
GN D 7
GN D 8
GN D 9
G N D 10

GN G
G ND
GN D
GN D

1 8 S A T A _ RX P 3
1 8 S A T A _R XN 3
1 8 S A T A _T X N 3
1 8 S A T A _ T XP 3

1

B.Schematic Diagrams

34
3 G_ D E T #
0 . 0 1u _ 1 6V _ X 7 R _ 04
0 . 0 1u _ 1 6V _ X 7 R _ 04
0 . 0 1u _ 1 6V _ X 7 R _ 04
0 . 0 1u _ 1 6V _ X 7 R _ 04

C7 7 8
C7 7 9
C7 8 0
C7 8 1

G ND2
G ND3
G ND4

35
23
25
31
33

GN D 1
G ND 2
GN D 3
G ND 4

21
27
29

10 / 2 9
GN D

1 00 K _ 0 4

J_FP1
4
1

.

G ND
0 . 1 u_ 1 6 V _Y 5 V _0 4

1 1 , 18 , 2 4 , 25 , 2 8 , 31 , 3 2 , 33 , 3 5 , 39 , 4 0 5V S
2 5 , 2 8, 2 9 , 3 5, 3 7 , 3 8, 4 1 5 V
1 8, 2 8 , 3 0, 3 4 , 3 5, 3 6 , 4 1, 4 2 V D D 3
2 , 3, 8 , 1 1 , 12 , 1 6 , 18 , 1 9 , 20 , 2 2 , 23 , 2 4 , 25 , 2 8, 29 , 3 0, 3 3 , 3 5, 3 7 , 3 8, 3 9 3 . 3V
3 , 6, 9 , 1 0 , 11 , 1 2 , 18 , 1 9 , 20 , 2 1 , 22 , 2 3, 24 , 2 5, 2 8 , 2 9, 3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 3 9 3 . 3V S

Schematic Diagrams

USB, Fan, TP, FP, Multi-Conn
USB Charge PORT

10/28

CCD

V DD 5
U SBV C C0 1

5V
U S B _P N 0
U S B _P P 0

17

U1 5

V DD 3

U S B _P N 0

22

U S B _P P 0

2
D M_ O
D P_ O

R7 4 3

3 4 , 3 5, 3 6 D D _ ON
VDD 5
U S B _ A C _ I N R 7 40

U S B _ A C_ IN
D

34

R7 4 1

* 10 K _ 0 4 7

*0 . 1 u_ 1 6V _Y 5V _0 4

I L I M1

C T L2

N C

C 14

V DD 3

16

R 7 36

* 15 K _ 1 %_ 0 4

15

R 7 38

* 10 K _ 0 4

3 . 3V

9/21
R 7 39
*1 0K _ 0 4

R7 4 2
1 0K _ 0 4

34

9
G _ OC # 0 1

13

R4 3 7

F A U L T#

* 0 _0 4

3

VIN
VIN

V OU T

EN

G ND

1

1A

48 mil
C1 0
R 22

C1 2

C1 1

1 0 0K _0 4

0. 1 u _ 16 V _ Y 5 V _ 0 4

1 u_ 6 . 3 V _Y 5 V _0 4

2

J _ CCD 1

Port 5

CC D_ EN

U S B _O C # 0 1 22

1u _ 6 . 3V _Y 5V _0 4

G 5 24 3 A

22
22
34

From KBC default HI

1
2
3
4
5

U S B _P N 5
U SB_ PP5
C C D _ D E T#

8 5 20 5 -0 50 0 1

M_PQFP16
3 .3 V

CT L2
CT L2
CT L2

CTL3: 0
CTL3: 1
CTL3: X

X
1
1

1--- -- > De dicat ed Ch argin g Pot, Auto- de te ct
1- -- --> Charg ing Do wn stre am Port , BC Sp ecif icatio n 1.1
0--- -- > St and ard Do wn stre am Port , USB2.0 M od e

TPM 1.2

R 3 96
*1 0 K _0 4
U SB VC C0 1

8/31

5V

FUNCTION

G_ OC #0 1

5

50 mil

2

6

H

Charge

Battery

L

Discharge

U2 4

F L G# V O U T 1
V IN1

C 1 12

AC/DC

V IN2

1 0 u _1 0 V _ Y 5 V _ 08

7

C5 0 8

C 7 54

8

0 . 1u _ 1 6V _ Y 5V _ 0 4

22 u _ 6. 3 V _ X 5R _ 08

V O UT 2

3
V O UT 3

4

3 5 ,3 8

18 , 3 4
18 , 3 4
18 , 3 4
18 , 3 4
22

60 mil

D D _ ON #

U S B _ V C C 0 1 _0

C1 7 7

22 u _ 6. 3 V _ X 5R _ 08 2 2 u _6 . 3 V _ X5 R _0 8

0. 1u _ 16 V _ Y 5 V _ 0 4

100 MIL
11/2

C 3 53

C3 4 2

0 . 1 u _1 6 V _ Y 5 V _ 04

*2 2 u_ 1 0 V _Y 5 V _0 8

28

3 .3 VS

C 3 52

C 35 1

*0 . 1u _ 1 6V _ Y 5V _ 0 4

* 0. 1 u _ 16 V _ Y 5 V _ 0 4

1

L 14

Port 0

TP M _ B A D D

R 26 1

J_ U S B 1

*1 0K _ 0 4

11/9

V+

U SB_ PN0 _ R

1

2

U S B _ P N_ 0

2

U S B _ P P 0 _R

4

3

U SB_ PP_ 0

3

D A T A _L

0
1
2
3

G ND
C 1 0 77 0 -1 04 A 3
P I N GN D 3 ~ 4 = GN D

GN D 3
GN D 4

G ND 3
G ND 4

C 3 79

C 3 78

C 32 0

*0 . 1 u_ 1 6 V _Y 5 V _0 4

*0 . 1u _ 1 6V _Y 5V _0 4

* 0. 1u _ 16 V _ Y 5 V _ 0 4

* 1u _ 16 V _ X 5 R _ 06

3 .3 VS
5
V SB

*0 . 1 u _1 6 V _ Y 5 V _ 04
6
2

GP I O
GP I O2

T E S T B I/B A D D

7

T P M3 0 0 4
T P M3 0 0 5

13

XTALI

14

XTALO

XTAL I
P P

TP M 3 00 1 1
TP M 3 00 2 3
TP M 3 00 3 1 2

X TA LO
N C_ 1
N C_ 2
N C_ 3

4
11
18
25

GN D _ 1
GN D _ 2
GN D _ 3
GN D _ 4

*S L B 9 63 5 T T

Ass ert ed before ent er ing S3
LPC reset t iming:
LPCPD # inac tive to LRS T# inact ive 32~96us
HI: ACCESS
LOW: NORM AL ( Inte rnal PD)
HI: 4 E/ 4F H
TPM _BADD LOW: 2E/ 2F H

5V S
5V S

Sheet 28 of 49
USB, Fan, TP, FP,
Multi-Conn

C3 2 3

L P C P D#

TPM _PP

CLICK CONN

C3 2 2

TPM

L F R A ME #
L R ESET#
S E RIR Q
C L K RU N#

T ESTI

4

*W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt

TP M _ P P

9

10
19
24

V D D1
V D D2
V D D3

8

D A T A _H
GN D 1
GN D 2

*1 0 0u _ 6 . 3V _ B _ A

C 6 91

G ND 1
GN D 2

C6 8 8

L AD
L AD
L AD
L AD

L C LK
22
16
27
15

20 S 4 _ S T A TE #

H C B 1 60 8 K F -1 2 1T 2 5 + C 2 3 9
5V

P C LK _ T P M

1 8, 34 L P C _ F R A ME #
3 , 1 2, 22 P L T _R S T #
1 8, 34 S E R I R Q
20 P M _C L K R U N #

.

100 MIL

26
23
20
17

0
1
2
3

21

G ND

L 13

U SBVCC 0 1

L P C_ A D
L P C_ A D
L P C_ A D
L P C_ A D

1
E N#

R T9 7 15 B G S

U S B V C C0 1

3 .3 VS

U 6

X6
4
3

*3 2 . 7 68 K H z
1
2

X5
4
3

*3 2 . 7 68 K H z
1
2

C 3 93

C 39 2

* 1 8p _ 5 0V _ N P O_ 0 4

* 18 p _ 50 V _ N P O _ 04

3. 3 V S
TP M_ P P

R2 5 8

* 10 K _ 0 4

TP M_ B A D D

R2 5 9

* 10 K _ 0 4

R2 6 4

* 10 K _ 0 4

R2 3 2

C 32 1
P C L K _ TP M 1

P CL K _ T P M
*3 3 _0 4

* 10 p _ 50 V _ N P O _ 04

5V S
0. 1 u _ 16 V _ Y 5 V _ 0 4
C2 8 9
J _ TP2
10
9
8
7
6
5
4
3
2
1

T P _ CL K
T P _ DA T A

J _ TP 1

R 19 1

R1 9 0

C 2 86

1 0 K _ 04

10 K _ 0 4

*1 0u _ 1 0V _ Y 5V _ 0 8

1
2
3
4
5
6

U S B _ P N 4_ T P 2
US B _ P P 4 _ T P 2

T P _C L K
T P _D A T A
T P B U T T ON _L
T P B U T T ON _R

T P _ CL K
T P _ DA T A
C 29 0

C2 8 8

4 7 p _5 0 V _ N P O _0 4
47 p _ 50 V _ N P O _ 04

*8 5 20 1 -0 60 5 1

8 5 2 01 -1 0 05 1

K20100125

For W150HNM

K20100125

For W140HN
CSW1~2

U S B _ P N4 2 2
U SB_ PP4 2 2

1
3

SW 2
* TJ G -53 3 -S -T / R

5
6

0_ 0 4
0_ 0 4

LIFT
KEY
2
4

TP B U T T ON _ L

2
1

4
3
1
3

SW 3
*T J G-5 3 3-S -T / R

5
6

?? ?? ?? ?? ?
U S B _ P N 4 _ TP 2 R 6 6 0
U S B _ P P 4_ T P 2 R 6 6 1

FOR POWER SWITCH BOARD

3 . 3V S

RIGHT
KEY
2
4

T P B U TT ON _ R

34
34

J _S W 1
1
2
3
4
5
6
7
8
9
10
11
12

S MC _ B A T 3 4 , 42
S MD _ B A T 3 4 , 42

R3 9 9

3 . 3V S

*1 K _ 04
M _B TN # 35

W L A N _S W # 3 4

W LA N _ E N _ R

MU TE _S W # 3 4
L I D _ S W # 1 1, 3 4

*0 _ 04

R7 8

0 _ 04

R7 9

W L A N _E N 2 7 , 34

V D D3
C C D _S W # 3 4

W140HN R78
W150HNM R79

8 7 1 51 -1 2 07 G

35 , 3 6
V D D5
1 1, 1 8 , 2 4, 2 5 , 2 7, 3 1 , 3 2, 3 3 , 3 5, 39 , 4 0 5V S
25 , 2 7 , 29 , 3 5 , 3 7, 3 8 , 4 1 5 V
1 8 , 2 7, 3 0 , 3 4, 3 5 , 3 6, 4 1 , 4 2 V D D 3
2 , 3, 8 , 1 1 , 12 , 1 6 , 18 , 1 9 , 2 0, 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 9, 3 0 , 3 3, 3 5 , 3 7, 38 , 3 9 3. 3 V
3 , 6, 9 , 1 0 , 11 , 1 2 , 18 , 1 9 , 20 , 2 1 , 2 2, 2 3 , 2 4, 2 5 , 2 7, 2 9 , 3 0, 3 1 , 3 2, 3 3 , 3 4, 35 , 3 9 3. 3 V S

USB, Fan, TP, FP, Multi-Conn B - 29

B.Schematic Diagrams

CT L1
CT L1
CT L1

USB_AC_IN

MODEL

5 V _ CC D

U 2
4
5

C1 3

To So uth Bridg e OC Pin.

*T P S 2 54 0

G

A C _ IN#

C T L1

C T L3

Q2 5
*MT N 70 0 2 Z H S 3

U S B _P P 0_ R

I L I M0

8

S

3 4, 42

R7 3 7

*1 0 K _ 04

10
14
E N /DS C

* 10 K _ 0 4 6

C3 4 9

GN D

5

*1 0 K _0 4

U S B _P N 0 _R

D P_ IN

I L I M _S E L
VDD 5

11
D M_ I N

3
4

R 41 7
* 10 K _ 0 4

1A

OU T

1 u _6 . 3 V _ Y 5V _0 4

IN
22

U S B _ P N0 _ R
US B _ P P 0 _ R

0_ 0 4
0_ 0 4

12
PPAD

1

R 43 5
R 43 6

1 u _6 . 3 V _ Y 5 V _0 4

C 4 89
*1 0u _ 1 0V _ Y 5V _ 0 8

Schematic Diagrams

USB 3.0
VL I VL 8012 USB3 .0

3.3VA

USB_SPI _SCLKM2
USB_SPI _CE# N2 SPISCK
USB_SPI _SI N1 SPICSB
USB_SPI _SO M1 SPISI
SPISO

uPD 72020 0

*0_04
K13
K14 GND
J13 GND
GND
P4
GND

PPON
10K_04

D
S

PPON G

50 MIL
6
7
8
1

10/27
C356

C377

C358

2 2 0 u _ 6. 3 V_ 6 3. * 6. 3 4* . 2

USB_O N1#

U26
5 FLG# VOUT1
R374
2
VIN 1 VOUT2
C373
3
VIN 2 VOUT3
*10K_04 10u_10V_Y5V_08
4
EN# GND
RT9715BGS
Q38
R347
*2N7002W
0_04

3A

750_1%_04

C548

1.05VS_VE801
C765

C766

+

0.1u_16V_Y5V_04
*0. 1u_16V_Y5V_04

R 540
100K_04

PR122

C767

C768

3.3VS_VL801

C769

R405

C 70

C771

C772

C773

3.3VS_VL801 3.3VS_VL801

U SBVCC3.0

SSTX1_NEC
TXP0_VIA
SSTX1#_NEC
TXN0_VIA
SSTX2_NEC
TXP1_VIA
SSTX2#_NEC
TXN1_VIA

*15mi_l short

L24

HCB1608KF-121T25

CLO SE TO CONN ECTOR

R651
R453
R652
R455
R653
R457
R662
R458
R668
R459
R669
R462
R670
R463
R671
R464

0_04
*0_04
0_04
*0_04
0_04
*0_04
0_04
*0_04
0_04
*0_04
0_04
*0_04
0_04
*0_04
0_04
*0_04

22u_6.3V_X5R_08

C752
C498
C525

22u_6.3V_X5R_08 GND
0.1u_16V_Y5V_04 GND
*220u_6.3V_6.3*6.3*4.2
GND

R443
*10K_04

G_DM0
G_DP0
G_DM1
G_DP1

TXP0

TXP1
C524 0.1u_10V_X7R_04 TXP _1R
TXN1
C520 0.1u_10V_X7R_04 TXN 1_R
G_DM1
1
2
*WCM2012F2S-161T03-short
L63
G_DP1
4
3
RXP1
1
2
*WCM2012
F2S-161T03-short 4
RXN1
3 L64
D if f. tr ace 90ohm

9
1
8
24
3
6
57

9X
*X8A025000FG1H_25MHz

*10K_04

3.3V_VI A

GND1

SSTX+ SHIELD
VBUS
SSTXDGND
D+
SSRX+
GND2
GND_D
SSRX- SHIELD

SPISI

3

SPISO
SPISCS#
SPISCLK

5
SI
2
SO
1
CE#
6
S CK
7
4
HOLD# VSS
*M2X5L512M C-12G SO8
6-04-25512-B72
WP#

USB_ON1#
SPISO
SPISI
SPISC KL
SPISC S#
GPC IE_RXN1_USB3_R
C759
GPC IE_RXP1_USB3_RC635

TXN0
TXP1
TXN1

R440

22, 27,30,34 BUF_PLT_R ST#

CLK_PCI
CLK_PCIEE_USB30#_VLI
_USB30_VLI 1919
PEXREXT R438

*3.01K_1%_04

3. 3VS V_L801
1. 05VS_VL801

6* .04K_1%_04
TXP1_VIA
TXN1_VI A
RXP1_VI A
RXN 1_VI A
G_D P1_VI A
G_D M1_VIA

R456

1* 0K_04

CPPE#

Q34
*AO3415
G

R665

RXP0

USBVCC3.0

RXN0
RXP1

L25

HCB1608KF-121T25

USB3.0POWERSETTING

CLO SE TO CONN ECTOR

3.3V

C746
C395
C538

3. V3_NEC 3.3VS
1

PJ34
2

G

1.05VS_VI A

CPPE#
C577 *1u_10V_Y5V_06
R454
1* 00K_04 3.3V _VI A

Q35
*AO3415
G

3.3VS_VI A
1

TXP0
C420 0.1u_10V_X7R_04 TXP _0R
TXN0
C421 0.1u_10V_X7R_04 TXN 0_R
G_DM0
4
3
*WCM2012F2S-161T03-short
L65
G_DP0
1
2
RXP0
4
3
*WCM2012
F2S-161T03-short 1
RXN0
2 L66
GN D

9
1
8
24
3
6
7
5

GND1
SSTX+ SHIELD
VBUS
SSTXDGND
D+
SSRX+
GND2
GND_D
SSRX- SHIELD
C19007-90905-L

PJ39

R666
*0_04

OPEN_2A
3. V3_VIA

1.05VS

ICPP E# 23, 34

1.05VS_VE

1.05VS_VIA

1 PJ352

PJ36
1

OPEN_2A
1.05V

*20mli _P_04

2
OPEN_2A

1. 05V_NEC
1 PJ372

1.05VS

3.3VS

3.3V

OFF

ON

OPEN_2A
GND

S3

OFF

25,27,28,35, 73,38,41 5V
6,18,19,20,24,25,35, 73,38,39 1.05VS
2,3,81, 1,12,16,18,19,20, 2, 23,24,25,27, 28,30,33,35, 73,38,39 3.3V
3,6,9,10,11,12,18,19,20,21,22, 23, 24,25,27,28, 30,31,32,33, 43,35,39 3.3VS
3,6,8,9,10,25,33, 53,37,38 1.5V

Q40
*AO3415
G

L54
*HCB1608KF-121T25

2
CPPE# R444

OPEN_2A
RXN1

Q33
*AO3415
G

*0_04

AL801_RS #T

Q41
*AO3415

22u_6.3V_X5R_08 GND
0.1u_16V_Y5V_04 GND
*220u_6.3V_6.3*6.3*4.2
GND
8/19
J_USB2

C692

PCIE_RXN1_USB30_VLI 19
PCIE_RXP1_USB30_VLI 19
PCIE_TXN1_USB30_VLI 19
PCIE_TXP1_USB30_VLI 19

3. 3VS_VL801

UB111RC-C1B1F-8H GND
22u_6.3V_X5R_08 GND

GN D

*0.1u_10V_X7R_04
*0.1u_10V_X7R_04

3.3VS_VIA

*20p_50V N_ PO_04

10/18

8 U48
VDD

44
VSUS33 43
USBHPE2#
42
USBHPE3# 41
USBHPE4# 40
SPISO
39
SPI SI 38
SPISC KL 37
SPIC S# 36
VDD 35
VCCA33PEXTX 34
PEXTX0PEXTX0+ 33
32
VCC A33PEXM 31
PEXRX0- 30
PEXRX0+
VCCA33PE XR X 29
28
PEXCLK- 27
PEXC LK+ 26
VCCA33RE G12
25
PEXR EXT 24
VCCA33REVDD
G25 23

C327

GND

J_USB3

D if f. tr ace 90ohm
UGND

C747

X17
2 1
3 4
GND
*X8A025000FG1H _25MHz
2
1

*20p_50V_NP O_04

U3 8
*V L 80 1_ QNF 88 _A1
VL8004PORT
VL8012PORT

6-03-00801-031

GND

*0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y 5V_04

USB3.0 Port

0_04
*0_04
0_04
*0_04
0_04
*0_04
0_04
*0_04

RXP0_VIA
RXN0_V AI

VDD
SSTX1+
SSTX1VCCA10SSRX1
SSRX1+
SSRX1VCCA33SS1
USBHP1+
USBHP1VCCA33SS1
SSTX
SSTX22+VCCA10SSRX2
SSRX2+
SSRX2VCCA33SS2
USBHP2+
USBHP2VCCA33SS2
VCCA10SSM
SSXI
SSXO

R411
*1M_04

C297

R543
R271
R544
R273
R646
R276
R647
R281

XTP0_VIA
TXN0_VIA

SSXI
SSXO

USB3.0 VLI ROM

U2DM1_N EC
G_DM0_VIA
U2DP _1NEC
G_DP _0VIA
U2DM2_
N EC
G_DM1_VIA
U2DP _2NEC
G_DP _1VIA

1. 05VS_VE801

C707
0. 1u_16V_Y5V_04

*10U_10V_0810u_10V_Y V5_08

0.022u_16V_X7R_04

R441

D

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M12
13
M
M11
M10
M9
M8
M
M76
M5
M4
M
3
L12
L11
L7
L6

67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

C763

*0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y 5V_04 *0.1u_16V_Y5V_04

C 704

G_OC_14#

.

USBVCC3.0

10/22
5V

C762

.
*H CB1608KF-121T25 C 764

10u_10V_Y5V_08

SSRX1_NEC
RXP0_VI A
SSRX1#_NEC
RXN0_VI A
SSRX2_NEC
RXP1_VI A
SSRX2#_NEC
RXN1_VI A

R283
10K_04
USB30_OC
3.3V

C761

1.6K_1%_04

UGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C 21
C1 3
D3
D 4
D1 1
D1 2
D1 43
D1
E1
E1E23
E1 4
FF 46
F7
F8
F F1 19
F12
G1
G 2
G6
GG7 8
G9
G1 1
G1
G1 23
H6
HH7 8
H9
H1J 23
J4
J6
JJ7 8
J9
JJ1 11 2
K3
LK41
L2
L3
L4

3. 3V

C721

C760

1.05VS_VE
L55

(15nF~48nF)

C427

C 657

G_DP0_VIA
G_DM0_VIA

R390

*20mi _l P_04 USB30_OC

C531

*0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y 5V_04 *0.1u_16V_Y5V_04

1.05V

1u_10V_Y5V_06

C718

A X6615

C535

S

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1u_6.3V_Y5V_04

P10 U2DP1_NEC
B12 SSRX1_NEC
A12 SSRX1#_NEC

C519

D

A1
A2
A3
11/2
A4
A5
X8 24.000MHz/ 16pF / +30ppm A7
A9
2 1
A11
A13
C423
C422
A14
B3
B4
20p_50V_NPO_04
20p_50V_NPO_04 B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11

A10 SSTX1#_N EC
N10 U2DM1_NE C

C623

0.1u_16V _Y V5_04 2.4K_1%_04

N14
M14 XT1
XT2
P6
CSEL

X7 *24MHZ
2 1

C725

P12
RREF N12 R424
U2AVSS
N11
U2PVSS
D6
U3AVSS

GND
G ND
GN D
GND
GND
GN D
GND
GND
G ND
GND
GND
G ND
GN D
GND
GND
GN D
GND
GGNDND
GND
GGNDND
GND
GND
GND D
GN
GND
GND D
GN
GND
GND
G ND
GND
GGNDND
GN D
GND
GND
GN D
GND
GGNDND
GND
GND
G ND
GN D
GND

R471
100_04

C636

C471
U 36
5
6
VIN VCNTL
9 VIN
7
4
POK VOUT
3
VOUT
8 EN
1 GND VFB 2

R445

*0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y 5V_04 *0.1u_16V_Y5V_04

5V

2A

R345

C 626

1.05VS_VL801

+

C14
19 USB30_XT1

C758

S t an d ar d -A

AUXDET_R R398

B - 30 USB 3.0

1.5V

USB30_OC

G_OC_23#

3.3V V_I A

+

1u_25V_08

3.3V_VIA

?? ? ? PIN6? <2mm

B10 SSTX1_NEC
U3TXDP1
U3TXDN1
U2DM1
U2DP1
U3RXDP1
U3RXDN1

3.3V_VIA

S

P5 PONRSTB
C429

1* 0K_04
1* 0K_04
1* 0K_04
1* 0K_04

CPPE#
R442
*4.7K_04
AL801_RS #T

USB3.0NECcore power 1.05V
5V

G14
OCI2B H13
OCI1B
PPON2 H14
J14
PPON1

*20mli _P_04

20, 27,30 PCIE_WAKE#

6-04-25010-490

B6 SS XT2_NEC
U3TXDP2
A6 SS XT2#_NEC
U3TXDN2 N8 U2DM2_NEC
U2DM2
B8 U2DP2_N EC
U2DP2 P8
SS RX2_NEC
U3RXDP2
A8 SS RX2#_NEC
U3RXDN2

PERSTB
PEWAKEB
PECREQB
AUXDET
PSEL
SMIB

R446

23, 34 SMI#

R333
47K_04

KB C_S PI_ *_ R = 0. 1"~ 0. 5"

S t an d ar d -A

H2
0_04 PEWAKE K1
R 343 0_04 K2
0_04 AUXDET_RJ2
10K_04
J1
H1

C542

D

VDD3
VD D33 3
VDD 3
VDD3
VDD 33
VDD3 3
VD D3 3
VDD3 3
VD D3 3
VDD 3
VDD3
VDD 33
VDD3 3
VDD3 3
VDD1 0
VDD1D10 0
VD
VDD 01
VDD1 0
VDD 01
VDD1 0
VDD1
VD D10 0
VDD1
VD D10 0
VVDD1
DD10 0
VDD1 0
VDD1
VDD 01 0
VDD1D10 0
VD
VDD1 0
VDD1 0
U3 AVDD3 3
U2 AVDD3 3

C

3. V3_NEC22, 27,30,34 BUF_PLT_R ST#
R468
20,27,30 PCI E_WAKE#
19 USB30_CLKREQ#_NEC
10/22
AUXD ETR426
D18
R349
3.3V R408
0_SMI#
RB751S-40C2 680K_1%_04 181USB3.
0/21

R469

A

B.Schematic Diagrams

19 PCIE_RXP2_USB30_NEC
19 PCIE_RXN2_USB30_NEC
19 PCIE_TXP2_USB30_NEC
19 PCIE_TXN2_USB30_NEC

Sheet 29 of 49
USB 3.0

D 10
F13
F14
F3
G3
G4
L9
L 10
L13
L 14
N4
N5
N6
P3
C4
C 5
C6
C7
D 5
C8
C9
D8
D9
E3
E4
E1 1
E1 2
H3
H4
L5
H 1
K1 1
LK18 2

S

B2
B1 PECLKP
PECLKN
C326 0. 1u_10V_X5R_04 D2
C705 0. 1u_10V_X5R_04 D1 PETXP
PETXN
F2 PERXP
F1
PERXN

19 CLK_PCIE_USB30_NEC
91 CLK_PCI E_USB30#_N EC

512Kbit
8

U37
VDD

5 USB_SPI_SI_R R389
47_04 US B_SPI_SI
SI
2
USB_SPI_SO_RR421
15_1%_04 USB_SPI_S O
SO
1 USB_SPI_CE#_RR359
1K_04USB_FLASH 3
15_1%_04USB_SPI _CE#
WP# CE#
6 USB_SPI_SCLK_R
USB_SPI _SCLK
R360
47_04
SCK
6-04-25512-B71
4
4.7K_04USB_HOLD#7
HOLD# VSS
6-04-25512-B70
MX25L5121EMC-20G
6-04-25512-B72

R423

0 . u1 _ 1 0 V_ X5 R_ 04
0 0. 1 u _ 1 6 V_X 7 R_ 0 4

U39

C755

*0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y 5V_04 *0.1u_16V_Y5V_04

C709
C549
0.01u_16V_X7R_04
0.01u_16V_X7R_04
C554
C 539
C527
C551 0.01u_16V _X7R_04
0.01u_16V_X7R_04
0. 01u_16V_X7R _04 0.01u_16V_X7R_04
C472
C720
C552 C499
0.01u_16V_X7R_04
0.01u_16V_X7R_04
C553 5p_50V_NPO_04
C609
C674
C425
C541
0.01u_16V_X7R_04
0.01u_16V_X7R_04 0.01u_16V_X7R_04
0.01u_16V_X7R_04
D7
P13

G

6,20,34,35 SUSB#

C490

D

D
C 546
0. 1u_16V_Y5V_04
*MTN7002ZHS3

C757

NC4
*NC_04
C462 0.1u_16V_Y V5_04
USB_SPI_VDD_1

3.3VA

Q42

R404
R337
R447
R439

ForUSB3.0 Legacy
To PCHGPIO13
C 756

S

AUXDET

C633

S

C723
C4
70_10V_X5R_04
0.1u
0. 1u_10V_X5R_04
C717
0.1u_10V_X5R_04
0.1u_10V_X5R_04

3. 3V_N EC

C716

D

3.3V_NEC

C509
HCB1608KF-121T25
0.1u_10V_X5R_04

10K_04

3.3V_VI A

USB3.0NECROM

S

.

66 56
64
66 23
61
60
559 8
57
565 5
54
55 32
51
50
449 8
47
464 5

R467

VDD
VSUVDDS3 3
T EST EN
SMDAT
SMCL K #
PEXRST
PEXWA KE#
J T AGTSMI
M# S
J T AGT DO
J VSU
T AGT S3
DI3
VDD
J T AGCK
C OREPW
RDN#
USBH OC1 #
USBHOC 2 #
USBHOC3
USB HOC4# #
USBHPE1 #
VSUS3 3

1.05V_NEC

VSUSUSB
SSREXT
VC
CA3 3 SSM
SST X3 +
SST X3 VCCA1 +0 SSRX3
SSRX3
SSRX3 VCCA3
3 SS3
US
BHP3
+
USBHP3 VCCA3
G ND 3 SS3
SST X4 +
X4 - 0 SSRX4
VSSTCCA1
SSRX4 +
SSRX4 VCCA3
3 SS4
USB HP4
+
USBHP4 VCCA3 3 SS4
G1

3.3VA

L40

21
3
54
6
7
89
10
11 2
13
11 54
16
17
118 9
20
221 2
G1

3.3V_NEC

SSREXT

3.3V_NEC

1.05VS_VL801

OCPPE# 23

Schematic Diagrams

Card Reader (JMC251C)
S D_ CL K

JMC251 C

*1 0p _ 5 0V _N P O_ 0 6

3 .3 V S

S D _ C LK

R1 6 2

0_04

S D_ CD #
MS _ I N S #

S D XC _ P OW E R

3 . 3 V _ LA N

C2 6 1
2. 2u _ 6 . 3V _ X 5 R _ 0 6

*0 . 1u _ 1 6V _Y 5 V _0 4

11/1
M S _I N S #
U 12

R 1 47

D V DD

R 1 46

D V DD

* 1 5m i l _s h o rt _0 6

* 1 5m i l _s h o rt _0 6

* 1 5m i l _s h o rt _0 6

32
32

LA N _ MD I P 0
LA N _ MD I N 0

32
32

LA N _ MD I P 1
LA N _ MD I N 1

32
32

3. 3V _ L A N
LA N _ MD I P 2
LA N _ MD I N 2

32
32

LA N _ MD I P 3
LA N _ MD I N 3

A V D D 1 2_ 5 5

L A N _ MD I P 2
L A N _ MD I N 2
A V D D 1 2_ 6 2
L A N _ MD I P 3
L A N _ MD I N 3

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

MD I O1 0
MD I O9
MD I O8
VDD
VIP_ 1
V I N _1
AV D D1 2
VIP_ 2
V I N _2
GN D
AV D D3 3
VIP_ 3
V I N _3
AV D D1 2
VIP_ 4
V I N _4

10/26

C2 9 9

C2 9 6

10 u _ 6. 3V _ X 5 R_ 0 6
Pin#32

0 . 1 u _1 6 V _ Y 5 V _ 0 4
Pin#32

JM C 2 5 1 -LG B Z 0 C

C 2 87

C2 85

1 0 u _6 . 3 V _ X 5R _ 06
Pin#31

0. 1 u _ 16 V _ Y 5 V _ 0 4
Pin#31

JMC251 C
(LQFP 64)

RE X T _ C

R 15 4

0 . 1u _ 1 6V _Y 5V _0 4
Pin#33

4

0 . 1u _ 1 6V _Y 5V _0 4
Pin#13

V D DR E G
V C C3 V
P W RC R
TEST
M PD
W AK EN
L A N_ L E D2
C R_ L E D
R STN
CP P E N
GN D
VDD IO
MD I O6
M D I O 12
M D I O 14
C R_ CD 0 N

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

R 18 2

R1 8 3

* 15 m i _l s h ort _ 0 6

*0 _ 06

WP
A0
A1
A2

1
2
3

( >20 mi l)

V D DR E G

( >20 mi l)

3. 3 V S
V C C _C A RD
MP D
P ME #
LA N _ S C L
LA N _ S D A

3. 3V S V D D 3

SD_ W P
MD I O1 2
MD I O1 4
SD_ CD #

10/26

B U F _ P L T_ R S T# 2 2 , 2 7, 2 9 , 3 4

CP P E N

MP D

3. 3 V _ L A N

R1 9 5

1 0 K _ 04

R1 9 6
C 28 3

* 4. 7 K _ 0 4

Core power 1.2V

0. 1u _ 1 6V _ Y 5V _ 0 4

V DD 3

3. 3V

V DD3
R 4 78
* 0_ 0 6

C7 1 4
*1 u _ 6. 3 V _ X 5 R _ 0 4

V D D3

R2 0 9
*0 _ 0 6

U 33

P CI e Di ffe re nt ia l
P ai rs = 10 0 Oh m

I S ON _ 2 5 1C

R1 5 1

0 _0 4

R1 5 6

* 10 0 K _ 0 4

6
D VDD

1A

VCN T L

4

V IN
V IN
P OK

V OU T

5
9
7

IN_ C

Sheet 30 of 49
Card Reader
(JMC251C)

3
R 4 80

R1 7 0
D V DD

R1 6 9
D V DD

3 . 3 V _L A N

C2 7 5

G ND

V OU T

*1 . 2 7 K _ 1% _ 0 4

8
EN

2

A V D D 12 _ 1 3

0. 1u _ 1 6V _ Y 5V _ 0 4
Pin#7

S CL
S DA

3. 3 V

3. 3 V _ L A N

C2 6 6

7
V CC

6
5

1 2 K _ 1% _ 0 4
A V DD1 2 _ 7

U 17
8

*A T 2 4C 0 2B N
V D D3

6-03-02510-0P0

1
2
3
4
5
6
7
A V D D 12 _ 7
* 15 m i l_ s h or t _0 6 8
9
10
11
12
A V D D 12 _ 1 3 1 3
* 15 m i l_ s h or t _0 6 14
M D IO7
15
C R _ C D 1N
16

3 .3 VS

(> 20 mi l)

10 u _ 6. 3V _ X 5 R _ 0 6
Pin#33

L A N X IN
L ANXO UT

V DD 3

( >2 0m il)

* 4. 7 K _ 0 4

R1 7 6

* 0 _0 4

R1 7 7

0_04

P C I E _ RX P _ 4_ G LA N C 2 7 2
P C I E _ RX N _ 4 _G L A N C 2 7 0

3 .3 V

R 14 8

*0 _ 06

R 16 4

*0 _ 06

1
VF B

V DD 3

G ND

C7 2 2
* 8 2p _ 5 0V _ N P O_ 0 4
R 47 9
*2 . 4 9 K _1 % _ 04

C 7 26
* 1 u_ 6 . 3 V _X 5 R _ 0 4

*AX6615

MS _ I N S #
3 . 3 V _L A N

0 . 1 u _ 10 V _ X 7R _ 04
0 . 1 u _ 10 V _ X 7R _ 04

P C I E _ R X P 4 _ GL A N 1 9
P C I E _ R XN 4 _G L A N 1 9

R 18 0
1 0 K _ 04
D9

A V D D 1 2 _ 52

A V D D 12 _ 5 5

C2 5 6

A V DD 12 _ 6 2

C2 5 5

A V D D 1 2 _7

C2 5 3

P C I E _ TX N 4_ G LA N
P C I E _ T X P 4 _G L A N
C LK _ P C I E _ GL A N
C L K _ P CI E _G L A N #

C2 71

19
19
19
19

A

2 0, 2 7 , 2 9 P C I E _ W A K E #

C

P ME #

2 2 ,3 4

R B 75 1 S -4 0 C 2

L A NX O UT
0. 1u _ 1 6V _ Y 5V _ 0 4
Pin#52

0 . 1u _ 1 6V _Y 5V _0 4
Pin#55

0 . 1u _ 1 6 V _Y 5 V _0 4
Pin#62

*1 0u _ 6 . 3 V _X 5 R_ 0 6
Pin#7
Reserved

4 IN 1 SOCKET SD/MMC/MS/MS Pro
R 16 1

*1 M_ 0 4
X1

1
3. 3 V _ L A N

L A NX IN

LA N X I N 1 9

F S X -8 L _ 25 MH z
2

V C C_ C A RD

Card Reader
Power

Fo r JM C2 51 C

FSX8L_25MHz? ? ? ? ?
X2
C2 8 2

C 2 52

C2 8 4

C2 9 3

0. 1u _ 1 6V _ Y 5V _ 0 4
Pin#43

* 0. 1u _ 1 0V _ Y 5V _ 0 4
Pin#43

0 . 1u _ 1 6 V _Y 5 V _0 4

0 . 1 u_ 1 6 V _Y 5 V _ 04

4

3

1

2

J _ C A R D -R E V 1
S D_ C D#
S D_ D 2
S D_ D 3
S D_ BS

10/22

V C C_ CA R D
3. 3 V _ L A N

V CC _ CA R D

S D _ C LK
C7 1 2

C 2 81

* H S X 3 21 S _ 2 5 MH Z

C2 5 7
0 . 1 u_ 1 6 V _Y 5 V _0 4

C2 6 4
2 2p _ 5 0V _N P O_ 0 4

3. 3 V _ L A N

C 26 0
2 2 p _5 0 V _ N P O _0 4

* 0 . 1u _ 1 6V _Y 5V _0 4
Pin#2

*1 0u _ 6 . 3 V _X 5 R _ 0 6
Pin#2

R6 0 0
7 5_ 0 4

C2 6 2
1 0u _ 6 . 3V _X 5 R _ 0 6
V CC _ CA R D
C5 4 4
0 . 1 u_ 1 6 V _Y 5 V _0 4

C2 4 9

C2 5 4

C2 5 9

C2 58

10 u _ 6. 3V _ X 5 R_ 0 6
Pin#59
Reserved

0 . 1u _ 1 6V _Y 5V _0 4
Pin#59

0 . 1u _ 1 6 V _Y 5 V _0 4
Pin#2

0. 1 u _ 16 V _ Y 5 V _ 0 4
Pin#21

Place all capacitors clo sed to c hip.
The su bscript in ea ch CAP inc icates the pin
number of JM C2 51/JMC261 t hat should be
close d to .

6-22- 25 R00-1B4
6-22- 25 R00-1B5

Crystal 8045 & 3225 Co-lay

V CC _ CA R D

S D_ D 0
S D_ D 1
S D_ W P
S D _ C LK
S D_ D 3
MS _ I N S #
S D_ D 2
S D_ D 0
S D_ D 1
S D_ BS

P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
P1 6
P1 7
P1 8
P1 9
P2 0
P2 1

CD _ S D
DA T 2 _ S D
C D / DA T 3 _ S D
CM D_ S D
VSS_ SD
V DD _ S D
CL K _ S D
VSS_ SD
DA T 0 _ S D
DA T 1 _ S D
W P_ SD
V S S _ MS
V C C _ MS
S CL K_ M S
D A T 3 _ MS
I N S _M S
D A T 2 _ MS
S D I O/ D A T0 _ MS
D A T 1 _ MS
B S _ MS
V S S _ MS

GN D
GN D

P2 2
P2 3

M D R 01 9 -C 0 -1 0 42
C 7 13

C5 4 5

0 . 1 u _ 16 V _ Y 5 V _ 0 4

*4 . 7 u_ 6 . 3 V _X 5 R _ 0 6

Near Cardreader CONN

2 5, 2 7 , 2 8, 2 9 , 3 5 , 37 , 3 8 , 4 1 5 V
32
DV D D
1 8, 2 7 , 2 8 , 34 , 3 5 , 36 , 4 1 , 4 2 V D D 3
2, 3, 8 , 1 1 , 12 , 1 6 , 1 8, 1 9 , 2 0, 22 , 2 3 , 24 , 2 5 , 2 7, 2 8 , 2 9, 3 3 , 3 5 , 37 , 3 8 , 3 9 3 . 3 V
3, 6 , 9 , 1 0 , 11 , 1 2 , 18 , 1 9 , 2 0, 2 1 , 2 2, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 3 9 3 . 3 V S

Card Reader (JMC251C) B - 31

B.Schematic Diagrams

R 1 45

D V DD

MD I O1 0
MD I O9
MD I O8
A V D D 1 2_ 5 2

REXT
A V DD3 3
X IN
XO UT
CL KN
C L KP
A VD D1 2
R XP
RXN
G ND
T XN
T XP
A VD D1 2
M D IO1 3
M DIO 7
C R_ C D1 N

Card Reader Pull High/Low
Resistors

L A N _S C L R 1 9 4
C2 7 3

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1 K_ 0 4

C2 7 4

For J MC 25 1C /26 1 on ly

M D IO1 1
L A N_ L E D0
L A N _L E D 1
IS ON
G ND
V DD IO
VD DO
M DIO 5
M D IO4
M DIO 3
M D IO2
M DIO 1
M D IO0
FB1 2
G ND
LX

R1 7 8

* 4. 7 K _ 0 4

L A N _S D A

R E G LX

S D_ W P

1 K_ 0 4

3 .3 V _ L A N
S D X C _ P OW E R
S D_ CL K _ C
SD_ BS
S D_ D3
S D _D 2
S D_ D1
S D _D 0
D VD D

C 2 63

R1 8 1

R1 9 3

( >2 0m il )

S W F 2 5 2 0C F -4 R 7 M -M
M D I O 11
L A N _L E D 0
L AN_ L ED1
I S O N _ 2 5 1C

V C C_ C A R D

DV D D

.

*4 . 7 K _ 04
*4 . 7 K _ 04

DV D D

10/26

L16

(>2 0m il )
RE G L X

R 18 5
R 18 4

3 . 3V _L A N

S wit ch in g Re gul at or
c los e to P IN 33

near Pin#41

C 2 65

Schematic Diagrams

SATA ODD, LED, Hotkey, LID SW
Zero Power ODD

W140XX ONLY

5 VS

J _ OD D 1

Z e ro_ V I N

C 2 80

S A T A _T X P 4 _1 4 1 8
S A T A _T X N 4 _ 14 1 8

C2 7 9

V O UT

2

3
G ND

EN

G5 2 4 3A

S A T A _ OD D _ D A # 1 8, 22

V GA _ S W #

V GA _ S W # 3 4

D 2
* R Y -S P 1 95 U H Y U Y G 4

S A T A _O DD _P W R GT 2 3
R1 6 7

C 67 5

C6 7 6

C 67 1

C 27 6

C 2 67

1 0 0K _ 0 4

+

27 , 3 4

add WLAN_LED#
C990713

B

BT_ EN

0 . 1u _ 1 6V _ Y 5V _ 0 4
1 u _1 0 V _ Y 5 V _ 06
* 22 0 u _6 . 3 V _ 6. 3 *4 . 2
0 . 1 u_ 1 6 V _Y 5V _0 4
1 0 u _1 0 V _ Y 5 V _ 08

* C 1 85 5 3 -11 3 0 5-L

3

4
5

2
4

W LA N _ LE D #

Q2
* D T C 1 1 4E U A
E

G N GDN1G DN 2D 3

GN D 4

VIN
VIN

5V S _ O D D

S A T A _ OD D _ P R S N T# 1 8 , 23

R1 6

*2 2 0 _0 4 *2 2 0_ 0 4

SW 1
*T J G-5 33 -S -T / R
1
3

4

U1 3

1

P1
P2
P3
P4
P5
P6

R1 2

*0 . 0 1 u_ 5 0 V _X 7 R _ 0 4

S A T A _R X N 4 _1 4 1 8
S A T A _R X P 4_ 1 4 18

1

*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

3 .3 VS

W140XX ONLY

* 15 m li _ s ho rt _ 0 6

G
R

C7 7 6
C7 7 7

R 1 79

2

*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

C

C7 7 4
C7 7 5

5
6

S1
S2
S3
S4
S5
S6
S7

0 . 1u _ 1 6V _ Y 5 V _ 04

SATA ODD

P I N G N D 1 ~ 4 = GN D

W140XX/W150XX/W170XX
3 . 3V S

3 . 3V S

R4 3 0

R4 3 1

2 20 _ 0 4

2 20 _ 0 4

2 20 _ 0 4

R1 1

R 9

R 3

*2 20 _ 0 4

* 2 20 _ 04

* 2 20 _ 04

D3

SCROLL
LOCK LED

D 22

CAPS LOCK
LED

R Y -S P 1 7 0 Y G3 4 -5 M

G re en

D1

IGPU LED

*R Y -S P 1 7 2 Y G3 4

DGPU LED

*R Y -S P 1 7 2U H R 24 -5 M

Green

White

M 100 12 6

Red

M1 00 126

G re en

C

C

G re en

D5

HDD/CD-ROM
LED

*H T- 17 0 B P Z
C

R Y -S P 1 7 0 Y G 34 -5 M

C

D 21

NUM LOCK
LED

R Y -S P 17 0 Y G 34 -5 M

A

A

A

R4 2 9

D 20

3 . 3V S

3 .3 VS

A

3 .3 VS

A

3 .3 V S

C

LED

A

Sheet 31 of 49
SATA ODD, LED,
Hotkey, LID SW

C

L E D _ DG P U #
LE D _ N U M#

L E D _ CA P #

LE D _N U M # 34

LE D _C A P # 3 4

L E D _ S C R OL L #

S A T A_ L E D#

L E D _ S C R OL L # 3 4

L E D_ IG P U#

S A T A _ LE D # 18

W140XX/W150XX/W170XX

34 O P TI MU S _ M OD E
3 .3 V S
E

8/17
K P B -3 02 5 Y S G C

B

R6
34

LE D _ A C I N

R 44 8

2 2 0 _0 4

1

2

LE D _ P W R

R 46 1

2 2 0 _0 4

3

SG

C
4

R 5
* 22 0 _ 04

3

1

D3 0

3 4 LE D _ B A T _F U L L

R 42 8

R 42 7

2 2 0 _0 4

1

2 2 0 _0 4

3

2

Y
SG

B
Q1
* DT C1 1 4 E UA

4

3 .3 VS
J _ LE D 1

D2 3

BAT CHARGE/FULL LED
27

W L A N _L E D #

L E D _I G P U #
L E D _D GP U #
VG A_ SW #
BT_ EN
S A TA _ L E D #
O P T I MU S _M OD E
W LA N _L E D #

1
2
3
4
5
6
7
8
9
10
8 8 48 6 -1 00 1

8 pin ->10 pin add WLAN_LED#
C990713

B - 32 SATA ODD, LED, Hotkey, LID SW

* RY _S P 1 9 5

4

Y

D 4 Green

C 2

K P B -3 02 5 Y S G C

W150XX/W170XX LED CON

SG

RED

AC IN/POWER ON LED

3 4 LE D _ B A T _C H G

Q3
* D T A 1 14 E U A

*2 2 0 _0 4

Y
34

L E D_ DG P U# 2 3

L E D _ I GP U # 18

E

B.Schematic Diagrams

For V41XX

1 8 , 2 7, 2 8 , 3 0, 3 4 , 3 5, 3 6 , 4 1, 4 2 V D D 3
1 1 , 18 , 2 4 , 25 , 2 7 , 28 , 3 2 , 33 , 3 5 , 39 , 4 0 5V S
3, 6 , 9 , 1 0, 1 1 , 1 2, 1 8 , 1 9, 2 0 , 2 1, 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 3 2 , 3 3, 3 4 , 3 5, 3 9 3 . 3V S

Schematic Diagrams

HDMI, RJ45
11/5 EMI

LAN POART

GIGA LAN (JMC251C)

*W C M2 0 12 F 2 S -1 6 1T 0 3 -sh o rt
1
2
4

L44

3

L15
J _ RJ _ 1

D V DD

30
30
30
30

L A N _ MD I P 0
L A N _ MD I N 0
L A N _ MD I P 1
L A N _ MD I N 1

30
30
30
30

L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD

LA N
LA N
LA N
LA N

_ MD I
_ MD I
_ MD I
_ MD I

P0
N0
P1
N1

12
11
9
8

LA N _ MD I P 2
LA N _ MD I N 2
LA N _ MD I P 3
LA N _ MD I N 3

6
5
3
2

T D4 T D4 +
T D3 T D3 +

MX 4 MX 4 +
MX 3 MX 3 +

T D2 T D2 +
T D1 T D1 +

MX 2 MX 2 +
MX 1 MX 1 +

13
14
16
17

LM
LM
LM
LM

19
20
22
23

L M X3 +
L M X3 L M X4 +
L M X4 -

*W C M2 0 12 F 2 S -1 6 1T 0 3 -sh o rt
1
2

X1 +
X1 X2 +
X2 -

4

3

D L MX 1 +
D L MX 1 D L MX 2 +
D L MX 2 -

1
2
3
6

D L MX 3 +
D L MX 3 D L MX 4 +
D L MX 4 -

4
5
7
8

DA+
DADB+
DB-

s h i el d
s h i el d

GN D 1
GN D 2

L17
R6 2
*0 _ 04

IP2
IN2
IP3
IN3

T C T4
T C T3
T C T2
T C T1

10
7
4
1

T CT 4
T CT 3
T CT 2
T CT 1

M
M
M
M

*W C M2 0 12 F 2 S -1 6 1T 0 3 -sh o rt
1
2
4

15
18
21
24

CT 4
CT 3
CT 2
CT 1

N
N
N
N

MC
MC
MC
MC

T_ 4
T_ 3
T_ 2
T_ 1

3

L23

DC +
DC DD +
DD 1 3 04 5 1 -02

Main 6-21-84020-008
Sec 6-21-84030-008

*W C M2 0 12 F 2 S -1 6 1T 0 3 -sh o rt
1
2

G S T5 0 0 9 L F
4
C5 7 9

C 57 3

C 57 1

0. 01 u _1 6 V _ X7 R _0 4

*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

*0 . 0 1 u_ 1 6 V _ X7 R _ 0 4

* 0. 0 1 u _1 6 V _ X7 R _0 4

3

L33

D03 LP16 CHANGE
TO RN22
R5 0
R3 9
R3 4
R3 3

7 5 _ 04
7 5 _ 04
7 5 _ 04
7 5 _ 04

NM CT _ R

Sheet 32 of 49
HDMI, RJ45

C 63
1 0 00 p _ 2K V _ X 7 R _ 1 2_ H 1 2 5

5V S _ H D MI

R7 1

C 20 6
C 20 5

0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C 2 C N _ C4 5
0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C 2 C P _C 4 4

C 20 8
C 20 7

0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C L K C N _4C8
0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C L K C P _C4 7
HDM I_ CT RL CL K
HDM I_ CT RL DA T A

2 1 H D MI _ C T R LC LK
2 1 HDM I_ CT RL DA T A
21

P OR TC _ H P C
3. 3 V S

R1 2 5

0_ 0 4

R1 2 1
R1 1 9

*4 . 7K _ 0 4
*0 _0 4

P OR T C _H P _ C

R1 2 8
3 . 3V S

3. 3 V S

R 13 2
R 13 4

49 9 _1 % _ 04
*4 . 7 K _ 04
*4 . 7 K _ 04

IN_ D3 +
IN_ D3 -

O UT _ D3 +
OU T_ D 3-

IN_ D4 +
IN_ D4 -

O UT _ D4 +
OU T_ D 4-

SCL
SDA

S CL _ S INK
S DA _ S INK

7
OE #

PC0
PC1
RE X T

3
4
6

OE _ 1
OE _ 2

34
35

R 12 7

4 . 7K _0 4

DCC _ E N#

R 13 1

4 . 7K _0 4

PC0

R 13 0

*4 . 7 K _ 04

PC1

T MD S _ D A T A 1 # -R
T MD S _ D A T A 1 -R

16
17

T MD S _ D A T A 0 # -R
T MD S _ D A T A 0 -R
T MD S _ C L OC K # -R
T MD S _ C L OC K -R

28
29

H D M I _S C L -C
H D M I _S D A -C

V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC

DC C_ E N#
RT _ E N#
PC0
PC1
RE X T
OE _ 1
QE _ 2

P a ra de P S 8 1 0 1
P I N 4 9 = G ND

[ 1]
[ 2]
[ 3]
[ 4]
[ 5]
[ 6]
[ 7]
[ 8]

G N D [ 1]
G N D [ 2]
G N D [ 3]
G N D [ 4]
G N D [ 5]
G N D [ 6]
G N D [ 7]
G N D [ 8]
G N D [ 9]
GN D [ 1 0]

J _ HDM I1
C8 1

C8 0

10 u _1 0 V _ Y 5 V _ 08

22 u _ 6. 3 V _ X 5R _ 08

R 1 24

10 0 K _ 04
T MD S _ C L OC K -R

1
5
12
18
24
27
31
36
37
43

A

C

C

AC

AC

H D M I _H P D -C

H D MI _ S D A -C

11/2
T MD S _ C L OC K #-R

2
11
15
21
26
33
40
46

D 27

H D MI _ S D A -C

19

16
14

H D M I _H P D -C

D 26

H D MI _ S C L-C

18
13
14

H P D_ S INK

25
32
10

19
20

30
HP D

OE #
DC C_ E N #

SN75DP139 Change 3.9K

9
8

O UT _ D2 +
OU T_ D 2-

G ND

2 1 H D MI C _ C LK C N
2 1 H D MI C _ C LK C P

O UT _ D1 +
OU T_ D 1-

IN_ D2 +
IN_ D2 -

D 25

*B A V 99 R E C T I F I E R
*B A V 9 9 R E C TI F I E R
*B A V 9 9 R E C T I F I E R

1_ 0 4

3. 3 V S
C1 7 6

C 15 9

T MD S _ D A T A 1 #-R

0 . 1u _ 1 6V _ Y 5V _ 0 4

0 . 1 u_ 1 6 V _Y 5 V _0 4

T MD S _ D A T A 1 -R

L1 2
4

R1 0 7
3

1

2

R1 0 6
* W C M 20 1 2F 2S -1 6 1 T0 3 -s ho rt
L1 0
R1 0 3
4
3
1

2
R1 0 2

* W C M 20 1 2F 2S -1 6 1 T0 3 -s ho rt
C1 5 3

C 15 8

5 VS
Q6
*M T N 7 00 2 Z H S 3

0 . 1u _ 1 6V _ Y 5V _ 0 4

* 49 9 _1 % _ 04
T MD S _ C L OC K # 1 2
T MD S _ C L OC K
*4 99 _ 1 %_ 0 4
* 49 9 _1 % _ 04
TM D S _ D A TA 1 #
T M DS _ DA T A 1
* 49 9 _1 % _ 04

H O T P LU G D E TE C T
+5 V

17
D DC/C E C G ND

S DA

15

C 1 54

H D MI _ S C L-C

11/2

S CL
RES ER V ED

13

H DM I_ CE C

CE C
TM D S C LO C K -

11

10

C L K S H I E LD
TM D S C LO C K +

8

9

R1 0 5

*4 9 9_ 1 %_ 0 4

T MD S _D A T A 0#

L11
1

2

T MD S _D A TA 0# -R

4

3

T MD S _D A TA 0-R

T MD S D A T A 0 S HIE L D0

7

6

T MD S D A T A 0 +
TM D S D A T A 1-

5

4

SH IE L D1
TM D S D A T A 1+

2

3

T MD S _D A T A 0
R1 0 4
*4 9 9_ 1 %_ 0 4
R1 0 1
*4 9 9_ 1 %_ 0 4
T MD S _D A T A 2#

*W C M2 0 12 F 2 S -1 6 1T 0 3 -sh o rt
L9
1
2 TM D S _ D A T A 2 # -R

T MD S D A T A 2 S HIE L D2

1
T MD S D A T A 2 +

T MD S _D A T A 2
R1 0 0
*4 9 9_ 1 %_ 0 4

4

3

T MD S _D A TA 2-R

*W C M2 0 12 F 2 S -1 6 1T 0 3 -sh o rt

0 . 1 u_ 1 6 V _Y 5 V _0 4
G

H D MI _ H P D -C

H D MI G N D

C 1 2 81 7 -1 19 A 5 -L
P I N GN D 1 ~ 4 = GN D

0 . 1 u _1 6 V _ Y 5 V _ 04
49

21 H D MI C _ C 2 C N
21 H D MI C _ C 2 C P

IN_ D1 +
IN_ D1 -

5 V S _H D M I _I N R 7 2

G ND
GN D
G ND
GN D

0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C 1 C N _ C4 2
0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C 1 C P _C 4 1

1_ 0 4

G ND 1
GN D2
G ND 3
GN D4

C 20 4
C 20 3

T MD S _ D A T A 2 # -R
T MD S _ D A T A 2 -R

DH D M I G N D

21 H D MI C _ C 1 C N
21 H D MI C _ C 1 C P

22
23

S

21 H D MI C _ C 0 C N
21 H D MI C _ C 0 C P

0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C 0 C N _ C3 9
0 . 1 u_ 1 0V _X 7 R _ 0 4 H D M I C _ C 0 C P _C 3 8

AC

U 8
C 20 2
C 20 1

R8 0
2 . 2K _ 0 4

A

R7 7
2 . 2K _0 4
5 V S _ HDM I

5 VS

Fo r ES D
A

HDMI CONNECTOR

C

FOR INTEL GRAPHIC

SN75DP139 6-03-75139-030
6-03-03360-030
PS8101 (6-03-08101-030) PIN TO PIN
30
DV D D
1 1, 1 8 , 2 4, 2 5 , 2 7, 2 8 , 3 1, 3 3 , 3 5, 39 , 4 0 5V S
3 , 6 , 9, 10 , 1 1, 12 , 1 8 , 19 , 2 0 , 21 , 2 2 , 23 , 2 4 , 25 , 2 7 , 28 , 2 9 , 30 , 3 1 , 33 , 3 4 , 35 , 3 9 3 . 3V S

HDMI, RJ45 B - 33

B.Schematic Diagrams

C5 8 3

Schematic Diagrams

Audio Codec ALC269
CODEC (ALC269 & VT1802P)

P V D D1 _ 2

0_04

For 3 .3 V HD A Link .

C4 7 3

C 4 74

1 0u _ 6 . 3V _X 5 R _ 0 6

0 . 1 u _ 16 V _ Y 5 V _ 0 4

C 43 9

C6 9 6

0 . 1 u_ 1 6 V _ Y 5 V _ 04

10 u _ 6 . 3V _ X 5 R _ 0 6

PD# Control
AZ_R ST# For 3 .3V
HD A Link De -pop
H D A _R S T #

C 4 42

C4 4 4

0 . 1 u _1 6 V _ Y 5 V _ 04

1 0 u _6 . 3 V _ X 5R _0 6

0 . 1u _ 1 6 V _Y 5 V _0 4

10 K _ 0 4

3 .3 V

Layout Note:

27
Layout Note:

C lo se t o P CH
R3 3 8

R 3 57

3 3_ 0 4

3 .3 VS

PC BEEP
18

K B C_ B E E P
H D A _S P K R

D1 6
B A T 5 4C W G H
1 A
C 3
2 A

25
38
AVD D1
AVDD 2

9

1
D VDD 1

DIGITAL
A Z _ S DO UT _ R

ANALOG

5

L I N E 1 -L
L I N E 1 -R

S D A T A -OU T
A Z _ B IT CL K _ R

6

6-03-02695-030

B I T -C LK
D

S Q 23
M TN 7 00 2 Z H S 3

A Z _ S D I N 0_ R

8

A Z _ S Y N C_ R

10

S D A T A -I N

H D A _R S T #

11
R ESET#

R 37 2

4 7 K _ 04

BEEP_ R

R 36 4

4 . 7 K _ 04

C 4 92

PC BEEP 1 2

C4 9 1

1 0 0p _ 5 0 V _N P O_ 0 4

3. 3VS_ AUD
5 VS
2 0ms

PC BEEP

1 u_ 6 . 3 V _ X5 R _0 4

BEE P

Ple a se Le t LC Fil te r
toge the r a nd close to
Codec .I F Spe ak e r
w ire le ngth i s l e ss
tha n 80 00 mil s I t don't
nee d t he LC Fil te r.

13

SEN SE_ A

R3 6 8

2 0 K _1 % _ 04

14
15

L I N E 2 -L
L I N E 2 -R

R3 6 9

3 9 . 2K _ 1 % _ 04

MI C 2_ L C 5 1 0
MI C 2_ R C 5 1 1

16
17

4 . 7 u _ 6. 3 V _ X 5R _ 06
4 . 7 u _ 6. 3 V _ X 5R _ 06

C4 9 7
1 u_ 6 . 3 V _ Y 5 V _ 04

DIG ITAL

S E N S E -B

19
20

J DR E F
MO N O -OU T

21
22

MI C 1 -L _R C 5 1 2
MI C 1 -R _ R C 5 1 3

23
24

L I N E 1 -L
L I N E 1 -R

27

V R E F -A L C 2 6 9

H P - OU T -L
H P -OU T -R

32
33

R3 6 6
C5 0 4

A U DG

20 K _ 1 %_ 0 4
*1 0 0 p_ 5 0 V _ N P O _0 4

4 . 7 u _ 6. 3 V _ X 5R _ 06 M I C 1 _ L
4 . 7 u _ 6. 3 V _ X 5R _ 06 M I C 1 _ R
C 4 75

A UD G

*1 0m i l _s h o rt

C5 5 5

0. 1 u _ 16 V _ Y 5 V _ 0 4

C5 5 6

0. 1 u _ 16 V _ Y 5 V _ 0 4

A U DG

L D O _C A P
M I C 1 -V R E F O-R
M I C 2 -V R E F O

35

C B N -A L 2 69

C B P -A L C 2 6 9
OP V E E -A L C 2 6 9

C 4 64

1 0 u _6 . 3 V _ X5 R _0 6

J_INTMIC1

M I C 2 -V R E F O

VT1802P NC PIN

H E A D P H ON E -L
H E A D P H ON E -R

36
34

10u

H E A D P H ON E -L 2 7
H E A D P H ON E -R 27

C 4 43

2 1

A U DG

4 . 7 K _0 4

J _ I N T MI C 1

2 . 2 u_ 6 . 3 V _X 5 R _ 0 6
I N T _ MI C R 2 1 3

1 K_ 0 4

2
1

VT1802P
C 3 06
330P 6 80 p _ 50 V _ X 7 R _ 04

C 4 45

A L C 2 6 9Q -V B 5 -GR
MI C 1 -V R E F O -L

R2 1 6

VT1802P
2.2K_04

2 . 2 u _ 6. 3 V _ X 5R _ 06

8 8 26 6 -0 20 0 1
P C B F o ot p ri n t = 88 2 6 6-2 R

VT1802P 75_1%_05
M IC1 _ R

R3 7 7

1 K_ 0 4

M I C 1 -L

27

M IC1 _ L

R3 8 3

1 K_ 0 4

M I C 1 -R

27

M I C 1 -V R E F O- L

R3 8 4

2 .2 K _ 0 4

M I C 1 -V R E F O- R

R3 7 8

2 .2 K _ 0 4

A U DG
A U DG

The rma l Pa d pla ce 9
Via hole .

S P K OU TL +

VT1802P 4.7K_1%_05
S P K O U T L +_ L

8/27
Headphone Anti-Pop Circuit

C4 3 2

C 43 5

*1 u_ 1 6 V _ X5 R _0 6

* 18 0 p _5 0 V _ N P O _ 04

3. 3 V S

H E A D P H ON E -L
HE A D P HO NE - R

J _S P K L1

8 52 0 5 -02 7 0 1

* F C M 1 60 8 K -1 2 1T 0 6 _s h o rt
L30
C4 3 4
*1 8 0 p_ 5 0 V _ N P O _0 4

EMI Require

R3 9 5
*2 2 0K _0 4
E A P D _M OD E

G

R 3 80

9/21

Q 29
*2 N 7 0 02 W

G

* 4. 7 K _ 0 4
C4 3 1

C 43 6

*1 u_ 1 6 V _ X5 R _0 6

* 18 0 p _5 0 V _ N P O _ 04

1 0K _0 4
C 7 53
* 1 0u _ 6 . 3V _ X 5 R _ 0 6

A U DG
J_SPK1
2
1

S P K O U T R -_ R
* F C M 1 60 8 K -1 2 1T 0 6 _s h o rt
L29
C4 3 3
*1 8 0 p_ 5 0 V _ N P O _0 4

La y out note :
C lose t o code c

A U DG
R3 8 5

D

S P K O UT R+ _ R

S P K O UT R-

Q 31
* 2 N 7 0 02 W

G
* 1 0K _ 0 4
Q3 6
*A O 3 41 5 R 39 3

S P K OU T R + _ R 2 7
S P K OU T R -_ R 2 7

L28
* F C M 1 60 8 K -1 2 1T 0 6 _s h o rt
S P K O UT R+

D

2
1

S P K O U T L -_L

S

S P K OU T L-

Spe a ke r 4 ohm-- -- --> 40 mil s
Spe a ke r 8 ohm-- -- --> 20 mil s

B - 34 Audio Codec ALC269

*1 0m i l _s h o rt

J P1

2 . 2 u _6 . 3 V _ X 5R _0 6

VT1802P

L31
* F C M 1 60 8 K -1 2 1T 0 6 _s h o rt

Spe a ke r w i re le ngt h le ss tha n 8 000 mi ls , I t don't nee d LC Filt e r.
SP KOUTR+, R-, L+ , L- Tra ce w i dt h

J P2

0 . 1 u_ 1 6 V _Y 5 V _ 04

CB N
C BP
O PVEE

H C B 10 0 5 K F -1 21 T 2 0

I N T _ MI C

AZ_R ST#
PD #

L35

J D _S E N S E _ B 2 7

VT1802P 5.1K_1%_04

C 4 83
28
30
29

EMI Require
J D _S E N S E 2 7

NEAR CODEC

18

VR EF

L D O _C A P
M I C 1 -V R E F O -R
MI C 2 -V R E F O

S Y NC

FOR VOLUMN
ADJUST

M I C 1 -V R E F O-L

H D A _S Y N C

3 3_ 0 4

M I C 1 -L
MI C 1 -R

AVSS1
AVS S2

18

3 3_ 0 4

J DR EF
M ON O-O U T

G P I O0 -D MI C -D A T
G P I O1 -D MI C -C L K

31

R 3 39

R 34 2

*1 0 u _ 6. 3 V _ X 5R _ 06

S e ns e A

S P D I F C 2/ E A P D
S P D IF O

GN D

H D A _B I T C LK

H DA _ S D IN0

C 69 5

1 0 u _ 6. 3 V _ X 5R _ 06

M I C 2 -L
MI C 2 -R

26
37

H D A _S D OU T

18

*1 0 K _ 0 418

C 5 01

0 . 1u _ 1 6V _Y 5 V _0 4

L I N E 2 -L
L I N E 2 -R

49

18

3 3_ 0 4

C4 9 3

0 . 1 u _1 6 V _ Y 5 V _ 0 4

S e ns e -B

PVSS 1
PVSS2

2 2p _ 5 0V _N P O_ 0 4
R 3 34

2
3

C 44 0

ANALOG

S P K -R S P K -R +

A udi o Co de c

G

C 4 52

47
48

D MI C - D A T
D MI C - C L K

5 VS

L3 4
H C B 1 0 05 K F -1 2 1 T2 0

A UD G

S P K -L+
S P K -L-

44
45

E A P D _ M OD E
S P DIF O

V ery c lo se t o

D V D D -I O

S

S P K O UT R S P K O UT R +

40
41

D VSS2

AZ_RS T# For 1 .5V
HD A Link De -pop

34

PD #
S P K O UT L +
S P K O UT L -

Q2 1
*B S S 13 8 _ N L

H D A _R S T # G

Sheet 33 of 49
Audio Codec
ALC269

4

Q 20
*2 N 7 0 02 W

G

7

*1 0 0 K _0 4
D

R 32 9

S

B.Schematic Diagrams

D

U 34

39
46

P D#

PVD D1
PVDD 2

D 1 3 R B 7 51 S -4 0 C 2
A

C

3 4 K B C _ MU TE #

? ? ?

5V S _A U D

C 43 8
R 3 21

D 1 2 * C D B U 0 0 3 40
A

E A P D _ MOD E C

5V S _A U D

* 10 u _ 6. 3V _ X 5 R _ 0 6

3 .3 VS
L2 7
3 . 3V S _A U D
H C B 1 0 05 K F - 12 1 T 20

42
43

18

C 43 7

* 0. 1 u _ 16 V _ Y 5 V _ 0 4
5 VS_ AU D

D 1 4 R B 7 51 S -4 0 C 2
A

C

VT1802P

C 44 1

D

R3 4 1

La yout not e:
GND a nd AUDG spa ce i s
60m il s ~ 1 00 mil s

5 VS
DV D D_ IO

For 1 .5 V HD A Link .
3 .3 V S _ A UD

R 3 12
* 1 5m i _l s h o rt _0 6

* 0_ 0 4

S

R3 5 6

S

1 . 5V

2 , 3 , 8, 11 , 1 2 , 16 , 1 8 , 1 9, 2 0 , 2 2, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0, 3 5 , 3 7 , 38 , 3 9 3 . 3V
3 , 6 , 8, 9, 1 0 , 2 5, 2 9 , 3 5 , 37 , 3 8 1 . 5V
1 1 , 1 8, 2 4 , 2 5, 2 7 , 2 8 , 31 , 3 2 , 35 , 3 9 , 4 0 5 V S
3 , 6, 9 , 1 0 , 1 1, 1 2 , 1 8 , 19 , 2 0 , 21 , 2 2 , 2 3, 2 4 , 2 5, 27 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 4, 3 5 , 3 9 3. 3 V S

A UD G

Schematic Diagrams

KBC-ITE IT8518E
K B C_ A V DD

L19
H C B 1 0 05 K F -1 2 1T 2 0

V D D3
C 34 6

0. 1 u _ 16 V _ Y 5 V _ 0 4

1 0u _ 1 0V _ Y 5V _ 0 8

0 . 1 u_ 1 6 V _Y 5 V _0 4

0 . 1 u _1 6 V _ Y 5 V _ 04

C 34 3
0 . 1 u_ 1 6 V _Y 5 V _0 4

18 , 2 8 L P C _ A D 0
18 , 2 8 L P C _ A D 1
18 , 2 8 L P C _ A D 2
18 , 2 8 L P C _ A D 3
22
P C LK _K B C
18 , 2 8 LP C _ F R A M E #
18 , 2 8
S E RIR Q
2 2 , 27 , 2 9 , 30 B U F _ P LT _ R S T #

PCL K_ KBC

23
28 , 4 2

L E D_ A CI N
2 0, 2 2 A C _P R E S E N T
23 , 2 9
23

* 0 _0 4

S M I#
S C I#

10/22

42
B A T _ DE T
42 B A T _V OL T
28
CC D_ S W #
2 TH E R M _ V OL T
42
TO TA L_ C U R
28

C C D _D E T #

28 , 4 2
28 , 4 2
1 6 S MC _ V G
1 6 S MD _ V G

S MC _B A T
S MD _B A T
A _ TH E R M
A _ TH E R M

33
K B C_ B E E P
31 L E D _ S C R O LL #
31
L E D _N U M #
31
L E D _C A P #

C C D _ D E T#
MO D E L _ I D
S MC _ B A T
S MD _ B A T
S MC _ V GA _ T H E R M
S MD _ V GA _ T H E R M
S MC _ C P U _ T H E R M_ R
S MD _ C P U _ T H E R M_ R

1 10
1 11
1 15
1 16
1 17
1 18

L C D _B R I GH TN E S S
K B C_ B E E P

24
25
28
29
30
31
32
34

3 1 LE D _ B A T_ C H G
3 1 L E D _ B A T _F U L L
31
L E D_ P W R
27
8 0 CL K
27
BT _ DET #
27
3 IN1
1 2, 2 2 , 3 7 dG P U _ P W R _E N #
28
T P _C L K
28
TP _D A T A

E C S CI# /G P D3 ( P U )
E C S MI # / G P D 4 ( P U )

DAC
G
G
D
D
D
D

AD
AD
AD
AD
AD
AD
AD
AD
SM
SM
SM
SM
SM
SM

C 0 / GP I
C 1 / GP I
C 2 / GP I
C 3 / GP I
C 4 / GP I
C 5 / GP I
C 6 / GP I
C 7 / GP I

0
1
2
3
4
5
6
7

GPIO
( P D )K S O1 6 / GP C 3
( P D )K S O1 7 / GP C 5
(
(
(
(
(
(
(
(

PWM
0 / GP A 0 (
1 / GP A 1 (
2 / GP A 2 (
3 / GP A 3 (
4 / GP A 4 (
5 / GP A 5 (
6 / GP A 6 (
7 / GP A 7 (

PU
PU
PU
PU
PU
PU
PU
PU

)
)
)
)
)
)
)
)

LK 0 / G
A T0 / G
LK 1 / G
A T1 / G
LK 2 / G
A T2 / G

PF0 (
PF1 (
PF2 (
PF3 (
PF4 (
PF5 (

18
21

20

W150HNM

K B C _ W R E S E T#

( P D )T A C H 0 / GP D 6
( P D )T A C H 1 / GP D 7
( P D )T MR I 0/ W U I 2 / GP C 4
( P D )T MR I 1/ W U I 3 / GP C 6

CIR
( P D )C R X / GP C 0
( P D )C TX / G P B 2

LPC/WAKE UP

G I N T / GP D 5 ( P U )

58
59
60
61
62
63
64
65

K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55

K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O

1 00
1 01
1 02
1 03
1 04
1 05
1 06

KBC
KBC
KBC
VSH
KBC

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

J_ K B 2
8 5 20 1 -2 40 5 1

4
5
6
8
11
12
14
15

K
K
K
K
K
K
K
K

B -S I 0
B -S I 1
B -S I 2
B -S I 3
B -S I 4
B -S I 5
B -S I 6
B -S I 7

4
5
6
8
11
12
14
15

1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24

K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

B -S O0
B -S O1
B -S O2
B -S O3
B -S O4
B -S O5
B -S O6
B -S O7
B -S O8
B -S O9
B -S O1 0
B -S O1 1
B -S O1 2
B -S O1 3
B -S O1 4
B -S O1 5

1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24

1 u_ 6 . 3 V _Y 5 V _0 4

EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)
V ER .

RX

V OL TA GE

V 1. 0

R2 02 10 K/ R 204 X

3. 3V

R2 02 X /R 20 4 1 0K

MO D E L _ I D

3 G_ P OW E R

_S P I _C E #
_S P I _S I
_S P I _S O
G_ S E L
_S P I _S C L K

56
57

SU SB#
S U S C#

93
94
95
96
97
98
99
1 07

CCD _ S W #
MU T E _ S W #
3G _D E T #
CCD _ DE T #

27

S MC _ C
S MC _ C
S MD _ C
S MD _ C

28

V GA _ S W # 3 1
dG P U _ R S T# 1 2
H _ P R O C H O T #_ E C

35
17

P CL K _ K B C

R 24 6
C 34 4

0 _04 F OR I T85 12 CX /EX
0 .1U _0 4 FO R I TE 85 12- J( IT E85 02 -J

*0 _0 4

AVSS

CLOCK

75

I T8 5 18 E V E R : C

1 19
1 23

W/0 C IR )

S H OR T
0 . 1u _ 1 6V _ Y 5V _ 0 4

S H OR T

1 1 B R I GH T N E S S

C K 3 2K E
CK 3 2 K

C 3 45

*1 0 mi l _ sh o rt

L CD _ B RIG HT NE S S

* 0. 1 u _ 16 V _ Y 5 V _ 0 4

K B C _A G N D

H_ P E CI 3 ,2 3
S MC _C P U _ T H E R M 1 9
S MD _C P U _ T H E R M 1 9
U S B _ A C _ I N 28

R2 4 2

P C LK _ K B C _ R
*1 0_ 0 4

C3 5 0

*1 0 p_ 5 0 V _N P O_ 0 4

C3 0 1

1 u _1 0 V _ Y 5 V _ 06

U1 6
S P I_ V DD _ 1
S W I#

20

C H G_ E N

42

8
V DD

R1 8 9
2
1 28

CK 3 2 K E
CK 3 2 K
R2 3 7

*1 0M _ 04

*0 _0 4

R2 4 0

0_ 0 4

R2 4 1

N B _ E NA V D D 1 1 ,2 1

K B C_ S P I_ S I_ R R2 0 8

4 7_ 0 4

K B C_ S P I_ S I

2

K B C _ S P I _ S O_ R R 1 7 1

1 5_ 1 % _0 4

K B C_ S P I_ S O

1

K B C_ S P I_ CE # _ R
R1 7 2

1 5_ 1 % _0 4

K B C_ S P I_ C E #

6

K B C _ S P I _ S C L K _R 2R 1 0

4 7_ 0 4

K B C _ S P I _ S C LK

S I

K B C _F L A S H
1 K_ 0 4

3
W P#

C E#
S CK

I CP P E #

2 3 , 29

R1 9 2

X 4 * 32 . 7 68 K H z
1
4
2
3

R2 5 6
0 _0 4

5
SO

K B C _H OL D #
4 . 7 K _ 04

7

4
H O LD #

VSS

P C T 2 5 V F 0 32 B

*3 2. 7 6 8 K H z
4
3

6-04-25032-491

J _ 80 D E B U G 1
C3 2 9
*1 2 p _5 0 V _ N P O _0 4

R2 4 4

4 3 _ 1% _ 0 4
* 0 _0 4
* 0 _0 4
* 0 _0 4

KBC_SPI_*_R = 0.1"~0.5"

32 Mb it

C 2 91

19

V DD3

NC 2

21 9
22 7
24 8
25 3

N C1

C E LL _ C O N T R O L 42
PM E#
22 , 3 0

X3
1
2

E C C os t Do wn

R
R
R
R

V DD 3

P M _P C H _ P W R OK 2 0
A L L _S Y S _ P W R G D 1 1 , 2 0, 3 9

E C_ V S S

0 . 1 u_ 1 6 V _Y 5 V _0 4

M_ R
M_ R
M_ R
M_ R

1 0K _ 0 4
1 0K _ 0 4
1 0K _ 0 4
1 0K _ 0 4

3

C P U_ F A NS E N 2 7
W L A N _S W # 2 8

1 20
1 24

( P D )L 80 H LA T / G P E 0

VSS
VS S
VSS
VSS
VSS
VSS
VSS

R XD / GP B 0 ( P U )
T X D/G P B 1 ( P U )

V DD 3
R 53 2
R 47 0
R 20 6
R 20 5

R S MR S T# 2 0
K B C _ R S T # 23

47
48

( P D )R I N G # / P W R F A I L # / L P C R S T# / G P B 7

1
12
27
49
91
113
1 22

1 08
1 09

31 O P T I MU S _M OD E
27
W LA N _ D E T #

P U_ T HE R
P U_ T HE R
P U_ T HE R
P U_ T HE R

Sheet 34 of 49
KBC-ITE IT8518E

6 , 20 , 2 9 , 35
2 0, 3 8

S U S _ P W R _A C K 2 0
BT_ EN
2 7, 3 1
B K L _E N 1 1
H S P I _ C E # 18
H S P I_ S CL K 1 8
H S P I _ MS O 18
H S P I _ MS I 1 8
D D _ ON
2 8, 3 5 , 3 6

82
83
84

V DD 3

*1 0 K _0 4

RX

1 12

UART

1 0K _ 0 4

R2 0 4

V S H G_ S E L 4 2
C CD_ E N

MO DEL _I D

0V

R2 0 2

B A T _V O L T

PWM/COUNTER

GP INTERRUPT

P W R _ B TN #

0
1
2
3
4
5
6
7

( P D )W U I 5 / G P E 5
( P D )L P C P D # / W U I 6 / G P E 6

)
)
)
)
)
)

R I 1# / W U I 0 / GP D 0( P U )
R I 2# / W U I 1 / GP D 1( P U )

33

0/ I D
1/ I D
2/ I D
3/ I D
4/ I D
5/ I D
6/ I D
1/ I D

WAKE UP

PU
PU
PU
PU
PU
PU

P W R S W / G P E 4( P U )

35
PW R _ SW #
11 , 2 8
L ID_ S W #

)GP H
)GP H
)GP H
)GP H
)GP H
)GP H
)GP H
)GP G

( P D )E G A D / G P E 1
( P D )E GC S # / G P E 2
( P D )E GC L K / G P E 3

WAKE UP

3 G _E N

PD
PD
PD
PD
PD
PD
PD
PD

EXT GPIO

PS/2
PS2 C
PS2 D
PS2 C
PS2 D
PS2 C
PS2 D

R2 4 7

10/13

F L F R A ME # / GP G 2
F L A D0 /S C E #
F L A D 1/ S I
F L A D2 /S O
F L A D 3 / GP G 6
F L CL K /S C K
( P D )F LR S T #/ W U I 7 / GP G 0/ T M

C L K 0 / GP B 3
D A T 0 / GP B 4
C L K 1 / GP C 1
D A T 1 / GP C 2
C L K 2 / GP F 6 ( P U )
D A T 2 / GP F 7 ( P U )

PW M
PW M
PW M
PW M
PW M
PW M
PW M
PW M

1 25
27

IT8518
6-03-085
18-0P1
FLASH

SMBUS

85
86
87
88
89
90

8 0C L K

P J0
P J1
A C 2 / GP J 2
A C 3 / GP J 3
A C 4 / GP J 4
A C 5 / GP J 5

ADC

66
67
68
69
70
71
72
73

B A T _ DE T
B A T _ V OL T
CC D_ S W #

K S I0 /S T B #
KSI1 /AF D #
K S I2 /INIT #
K S I 3 / S LI N #
KSI4
KSI5
KSI6
KSI7

K S O 0/ P D 0
K S O 1/ P D 1
K S O 2/ P D 2
K S O 3/ P D 3
K S O 4/ P D 4
K S O 5/ P D 5
K S O 6/ P D 6
K S O 7/ P D 7
K S O8 / A C K #
K S O 9 /B US Y
K S O 1 0/ P E
K S O1 1 / E R R #
K S O1 2 / S LC T
K S O1 3
K S O1 4
K S O1 5

G A 20 / G P B 5
K B R S T #/ G P B 6 ( P U )
P W U R E Q # / GP C 7( P U )
L 8 0L L A T / GP E 7 ( P U )

76
77
78
79
80
81

MU T E _S W #
*0 _ 04
R5 3 8
0 _0 4
R5 3 9

W140XX

LPC K/B MATRIX

23
15

2 7, 2 8 W L A N _ E N
33
KBC_ M UT E#
18
M E _W E
27
C P U_ F A N
28
M UT E_ SW #
23 C R I T _T E M P _ R E P #
27
3G _ D E T #

10/22

R 6 73

24

J_KB1

J _K B 1
* 8 52 0 1 -24 0 5 1

W R ST#

1 26
4
16
20

GA 2 0
A C_ IN#

1

1
2
3
4
5
8 8 26 6 -0 50 0 1

3 IN1
8 0 CL K
8 0 DE T #

R2 4 5
1 0K _ 0 4

1 8 , 2 7, 2 8 , 3 0, 3 5 , 3 6, 41 , 4 2 V D D 3
3 , 6, 9 , 1 0 , 11 , 1 2 , 18 , 1 9 , 20 , 2 1 , 2 2, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 2 , 3 3, 35 , 3 9 3. 3 V S

KBC-ITE IT8518E B - 35

B.Schematic Diagrams

31

L A D0
L A D1
L A D2
L A D3
L P CC L K
L F R A ME #
S E R IRQ
L P C R S T #/ W U I 4 / GP D 2 ( P U )

14

K B C _W R E S E T #

3

U 18
10
9
8
7
13
6
5
22

*0 . 1 u _1 6 V _ Y 5 V _ 04

C3 4 7

VST BY
VS TBY
VST BY
VST BY
VST BY
VST B Y

M 74 0T/ TU

V CC

0 _0 4 f or M 760 T/ TU
B KP 100 5H S1 21_ 04 f or
E MI So lu ti on

C3 0 0

* 0. 1 u _ 16 V _ Y 5 V _ 0 4

1 00 K _ 0 4

26
50
92
11 4
1 21
127

E C_ V C C

.

3 . 3V S

V DD 3

C 30 3

0 . 1u _ 1 6V _ Y 5V _ 0 4

K B C _ A GN D

VBAT

H C B 1 0 0 5K F -12 1 T 20

11

L 22

VDD 3

C3 0 2

74

C 3 19

AV CC

C 68 4

.

C2 9 4

0 . 1u _ 1 6V _ Y 5 V _ 0 4

C 6 85

Schematic Diagrams

5VS, 3VS, 3.3VM, 1.5VS_CPU
V DD 3
V IN
V DD 3

10/28
10/22

R2 6 0
*1 2 . 1 K _1 % _ 06
28

10/13

U2 0
1

VA

VA

M_ B T N #

VIN

1 K_ 0 6

3

10/22

4

10/13

V IN1

VIN 1

2

V IN
R 22 2

R2 2 1

8
7

R 2 18

6

P W R _ S W #R

10 K _ 0 4

1 K _0 4 D D _O N

M _B TN #

P W R _S W #

I N S T A N T -ON

P R2 1 7
1 0K _0 4

10/13

D D _O N _ L A T C H

R 5 34

1K _0 4

P W R_ S W # 3 4

5

G ND

1 . 0 5V S _V T T _ P W R G D # 3 7

P 28 0 8 B 0

1.05VS_VTT

2 , 3 , 5 , 23 , 2 4 , 25 , 3 9 1. 0 5 V S _ V T T

E

10/28

1. 0 5 V S _ V T T

3

22 0 0 p_ 5 0V _X 7 R _ 0 4

1 0 K _ 04
S US B

D D _ ON #

DD_ O N#

2 8 , 38

S

5G

6 , 2 0 , 29 , 3 4 S U S B #

P Q 1 8A

* 0 . 1u _ 16 V _ Y 5 V _ 0 4
S
D M N 6 01 D W K -7

10 0 K _ 04

8
7

P R 23 0

P Q5 8 A
MT N N 20 N 0 3 Q8
2
1

5 VS

SYS1 5 V

1 . 5V

P R 2 43

P R 2 41

PQ 1 5
P 2 7 0 3B A G
6
5
2
4
1

1 .5 V

20 0m A

1 .5 V S

1 .5 V S _ CP U

6

D

22 0 0p _ 5 0V _ X 7 R _ 0 4

P J 18

P Q6 8 A
R T 3K 44 M
G 2

4 0 m il

D
P Q 6 8B
R T 3K 4 4 M
S

* 22 0 _ 04

P C 54

P C5 5

*0 . 1 u _1 6 V _ Y 5 V _ 04

*1 0u _ 6 . 3V _X 5 R _ 0 6

P C5 6

P Q 11 B
*M T N N 2 0 N 0 3 Q8
5

SU SB

G

P Q 10
* MT N 7 0 02 Z H S 3

*2 2 00 p _ 50 V _ X7 R _0 4
6

1

P Q 1 1A
* MT N N 2 0N 03 Q 8
2
1

1 .5 V S _ CP U E N1

5 G

S US B

S

4 0 mi l
2

2

P C 2 05

8
7

4

3 , 3 7, 3 8

1

6

1

S US B

PJ 9

6

5

4 7 0 p_ 5 0V _X 7 R _ 0 4

1 . 5 V S _L O

3

P Q 58 B
M TN N 2 0 N 0 3 Q8

D D _ ON #

P R8 0
*1 M_ 0 4

3

P C 2 03
5

2 20 0 p _5 0 V _ X7 R _0 4

P R 2 44
1 0 0_ 0 4

10 u _1 0 V _ Y 5 V _0 8

P C1 9 5

1. 5 V S _ E N 1

P C 20 9

4

4

4

0. 1 u _ 16 V _ Y 5 V _ 0 4

5V S _ E N 1

P Q 5 7B
M TN N 2 0 N 0 3 Q8

P R 79

NM OS

P C2 0 6
0 . 1 u _1 6 V _ Y 5V _ 0 4

Power Plane

5V _ E N 1

PC2 0 4

3

3

1 M _0 4

2
*5 m m

1M _0 4
1 M_ 0 4

PJ 7 MU ST S HOR T

PJ 5
1
S Y S 15 V

D 1 . 5V S _C P U _ L O

S Y S 1 5 V V D D5
5V

3A

20 A

10/13

NM OS

ON

S

P Q5 7 A
MT N N 20 N 03 Q8
2
1

1.5VS_CPU

1.5VS
NMOS

ON

3

5VS
NMOS

ON

ON

6

1 . 05 V S _ V T T _E N # 20

6

5V

ON

ON

3.3VS

3.3V

V DD 3

3

10/27

P R2 3 9
1 M_ 04

P C 20 1

3 .3 V S _ E N1
4

3 . 3 V _E N 1

P C 19 6

P Q 5 9B
M TN N 2 0 N 0 3 Q8
5

D D _ ON #

P C2 0 0
2 20 0 p_ 5 0 V _X 7 R _ 0 4

6

4

2 20 0 p _5 0 V _ X7 R _0 4

P C 2 02
P R2 4 0
75 _ 0 4

P Q6 0 B
MT N N 20 N 03 Q8
5

G
S

S US B

6

ON

B - 36 5VS, 3VS, 3.3VM, 1.5VS_CPU

ON

3. 3 V S

3 . 3 V S _ LO

S Y S 15 V

D

Power Plane

P R 23 1
1 M_ 0 4

3. 3 V

3A

P Q 60 A
MT N N 2 0 N 0 3Q 8
8
2
7
1

0. 1 u _ 16 V _ Y 5 V _0 4

8
7

ON

NMO S

3

V DD 3

P Q5 9 A
MT N N 20 N 03 Q8
2
1

1 0u _ 10 V _ Y 5 V _ 08

NMO S
S Y S 1 5V

3, 3 7 , 3 8

D MN 60 1 D W K -7

P R1 1 8

ON

8
7

S US B
P C 1 84

P Q 18 B

5

EMI

V DD 5

D

P C 80
*0 . 1 u _1 6 V _ Y 5 V _ 04

1
4

P Q6 9 B
M TN N 2 0 N 0 3Q 8

D

2G

2 8 , 34 , 3 6 D D _ ON
P Q4 5B
M T N N 2 0 N 0 3 Q8

P R 22 5

1 0 K _ 04

5

S Y S 1 5V

P R 1 14

6

C 6 60

P R 2 69
1 0 0 _0 4

10 u _ 10 V _ Y 5 V _0 8

1. 05 V S _ V T T_ E N 1

4

0 . 1u _ 5 0V _ Y 5 V _ 06

Sheet 35 of 49
5VS, 3VS, 3.3VM,
1.5VS_CPU

3

1M _0 4

SY S5 V

P C 22 8

3

P C2 2 7
0 . 1 u _1 6 V _ Y 5V _ 0 4

VIN

C2 5

10/28
S Y S 5V

P R2 4 5

0 . 1 u_ 5 0 V _Y 5V _ 0 6

B.Schematic Diagrams

VIN

2 N 3 9 04

ON

1 0A

MT N N 2 0N 03 Q 8
8
2
7
1

C 24

P Q4 6

1 00 K _ 0 4

P Q6 9 A
MT N N 20 N 03 Q8
8
2
7
1

P Q4 5 A

S Y S 15 V

B

4

1. 0 5 V S

NM OS

P R2 4 2

C

11/2

ON

P Q6 7
MT N 7 0 02 Z H S 3

42
VA
36
VIN 1
2 8, 3 6
V DD 5
6 , 9 , 1 0, 2 4 1 . 5V S
3 ,6
1 .5 V S _ CP U
36
S Y S 5V
3 6, 3 7 S Y S 1 5V
2 5 , 27 , 2 8 , 29 , 3 7 , 38 , 4 1 5V
6 , 1 8 , 19 , 2 0 , 24 , 2 5 , 29 , 3 7 , 38 , 3 9 1. 05 V S
1 1 , 3 6, 3 7 , 3 8, 3 9 , 4 0, 4 1 , 4 2 V I N
3 , 6, 8 , 9 , 1 0, 2 5 , 2 9, 3 3 , 3 7, 3 8 1 . 5V
1 8, 2 7 , 2 8, 3 0 , 3 4, 3 6 , 4 1, 4 2 V D D 3
1 1 , 18 , 2 4 , 25 , 2 7 , 28 , 3 1 , 32 , 3 3 , 39 , 4 0 5V S
2 , 3 , 5 , 2 3, 2 4 , 2 5, 3 9 1 . 05 V S _ V T T
2, 3 , 8 , 1 1, 1 2 , 1 6, 1 8 , 1 9, 2 0 , 2 2, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 0 , 3 3, 3 7 , 3 8, 3 9 3 . 3V
3 , 6 , 9 , 1 0, 1 1 , 1 2, 1 8 , 1 9, 2 0 , 2 1, 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 3 1 , 3 2, 3 3 , 3 4, 3 9 3 . 3V S

Schematic Diagrams

VDD3, VDD5
V R E F _ VDD

P R 87

* 0 _ 04

P R 88

0_04
P C5 8

1 u_ 1 0 V _ Y 5 V _ 0 6
VFB 1

TO NSEL

VFB2
PR 9 1
EN _ 3 V

PR9 0
E N _5 V

PC 6 3
1 0 0 K _0 4

P C 61
1 00 0 p _ 50 V _ X 7 R _ 0 4

10 0 K _ 0 4
2

1
EN1

VFB1

21

1u _ 2 5 V _0 8
UG A T E1

20

PH ASE1

19

L GA T E 1

4

C

V R EF _ V DD
V R E G5

P R 1 02

0_04

P R 1 00

* 0_ 0 4

P R9 7
*0 _ 0 4

PD 9
C

P R 98

0_04

R B 0 54 0 S 2

*0 _ 0 4

P R1 0 1
2. 2_ 0 6

P C7 1

V DD 5
P J1 7
1

2
*5 m m

P R8 9
P C6 0

P 12 0 3 B V

VR EG 5

M990125

1 0 00 p _ 5 0V _ X 7 R _ 0 4

PD 1 0
B A T 54 S W GH
A 1
3 C
A 2

V R E G5

Rb
P R8 4
1 9 .1 K _ 1 % _0 6

SY S5 V
S Y S 1 0V

0 . 0 1 u_ 5 0 V _ X 7R _ 04

1026

V IN 1

Sheet 36 of 49
VDD3, VDD5

P C8 2
+

P C 1 85
0 . 1 u _1 6 V _ Y 5 V _ 0 4

P C7 0

P C 73
A

P C 69

4 . 7 u _2 5 V _ X 5 R _ 0 8

V IN

V IN _ 6 1 8 2

*6 8 0K _1 % _ 0 4

P R9 9

SY S5 V

Ra

PD1 1

C

5
6
7
8
A

VDD5
5A

3 0 K _ 1 % _0 6
1
2
3

VCL K

L DO 5

18

17

16

25
15

14

E N_ A L L

PL 1 0
T M P C 0 6 0 3 H -4 R 7 M -Z 0 1
2

P Q5 0

P R9 4
R B 0 5 40 S 2

9/6 EMC DVT request

1

P D6
C

4 .7 u _2 5 V _ X 5R _ 0 8

4

P D7
A

V R E G5

13

PD 1 4

LG A T E 1
V IN

EN 0

4

3
2
1

PD 1 3

PH ASE1

P C 1 80

4 .7u _ 2 5 V _ X5 R _0 8

P Q4 9
P 1 2 03 B V

P D1 2
L GA T E 2

P C 2 0 7 P C2 0 8
+
+

P C7 5

1 5 u _2 5 V _ 6 . 3 *4 . 4

P C 17 9
0 .1 u _ 50 V _ Y 5 V _0 6

1
2
3
P HA S E 2

SKI PSEL

20 K _ 1 % _ 04

S Y S 5V

UG A T E 1

GN D P A D
G ND

8
7
6
5
P R8 6

12

C

C
1 3 K _ 1 % _0 6

L G AT E2

P Q5 1
P 1 20 3 B V

A
* S K 3 4S A

0 .1 u _ 16 V _ Y 5V _0 4

P C 59

CSO D1 4 0 SH
A

P R8 5

1 0 0p _ 5 0 V _N P O _0 4

+
2 2 0 u_ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2

P C1 8 6

11

S K IP S E L

*5 m m
PC 8 1

10

P HA S E 2

P C6 5
B O OT 1

B O OT 1

uP6182

UG A T E 2

PL 1 1
T MP C 0 6 0 3H -4 R 7 M -Z 0 1
2
1

1

B OO T 2

0 .1u _ 5 0 V _ Y 5 V _ 0 6
U G A TE 2

22

5
6
7
8

8
7
6
5

4

S Y S 3V
PJ 1 9

9

B OO T2

P R 92
* 1 0K _ 0 4
P O K _ 61 8 2

3
2
1

R B 0 5 4 0S 2

1 u _1 0 V _ Y 5 V _ 0 6

P C6 8

PD 8
B A T 54 S W GH
A 1
3 C
A 2

2 2 0 0 p_ 5 0 V _ X 7R _ 04

S YS1 5 V

0.0 1 u _ 50 V _ X 7 R _ 0 4
P C6 7

2 2 0 0 p_ 5 0 V _ X 7R _ 04

V RE G 5
E N _3 V 5 V P R 8 1

* 0 _0 6

E N_ 3 V

PR 8 3
P R 1 53

3

1 0 K _ 04
D

4

V DD 3

P C6 4

23
PO K

S
D M N6 0 1 D W K -7

10/22

P Q 12 B
5G

D
1

6

D D _O N _E N _ V D D

2G
1

S

6

D M N 6 0 1 D W K -7

A C _ IN

PC 5 7

0 .1 u _1 0 V _ X 5R _ 0 4

1 0 0K _0 4

D

2G
S
1

42

P R8 2
PJ 6
* 40 m i l

P Q 63 A
2

28 , 3 4 , 3 5 D D _O N

E N_ 5 V
* 1 0m i l _s h o rt

P Q1 2 A

D MN 6 01 D W K -7
Support Intel V-Pro Function

35
VIN 1
2 8 ,3 5
V DD 5
35
S Y S 5V
3 5 ,3 7 S Y S 1 5V
1 1 , 3 5 ,37 , 3 8 , 3 9 ,40 , 4 1 , 4 2 V I N
1 8 , 2 7,2 8 ,3 0 , 3 4,3 5 ,4 1 ,4 2 V D D 3

VDD3, VDD5 B - 37

B.Schematic Diagrams

5A
2

L DO 3

* 1 5u _ 2 5 V _ 6. 3 * 4. 4

8
1u _ 1 0 V _ Y 5 V _ 0 6
P Q5 2
P 1 20 3 B V

C

4 . 7u _ 2 5 V _ X5 R _0 8

P C6 2

VDD3

A
C S O D 1 40 S H

P C1 7 6

4 . 7 u _ 25 V _ X 5 R _ 0 8

V IN
24
VO 1

A
* SK3 4 SA

P C1 7 5

P U5

2 2 0 u _6 . 3 V _ 6 . 3 *6 . 3 *4 . 2

V O2

3

4

7

VR EF

5
VFB2

EN 2

V RE G 3
V IN

T ON S E L

6

1 0 00 p _ 5 0V _X 7 R _0 4

Schematic Diagrams

Power 0.85VS, 1.8VS, PEX_VDD
PEX_VDD
1.05V@4A
250 MIL

M TN N 2 0 N 0 3 Q8
2
1

P E X_ V D D

1

5V

*1 0 m li _ s ho rt

PJ 1
2

3 .3 V

1 M_ 0 4
P C2 3 1

0 . 1 u_ 1 6 V _Y 5 V _ 04

10 u _ 10 V _ Y 5 V _ 0 8

D

P R2 2 9

5V

2

3 , 35 , 3 8

d GP U _ P W R _ E N #

1. 8 V S

2A

V C NT L

PJ 2 1

4

1

P R2 2 4

SU SB

E N 1. 8 V S

1 M_ 0 4

3

2
G ND

*1 u _ 6. 3V _ Y 5V _0 4
P Q6 3 B
D MN 6 01 D W K -7

5G

d GP U _P W R _ E N # 1 2 , 2 2 , 34

O P E N_ 3 A

V OU T
EN

D

VF B

P C 1 90
1 . 2 7 K _1 % _ 04
P C 18 9

82 p _ 50 V _ N P O_ 0 4

P C1 8 7

P C 1 83

11/5

0 . 1 u_ 1 6 V _ Y 5 V _ 04

2 2 00 p _ 50 V _ X 7R _ 04

2 2 0 0p _ 5 0V _ X 7 R _ 0 4

P C 19 1

P C 19 3

V F B _ 6 61 0 P R 2 2 7

AX6615
M 99 01 25

S

2

V OU T

1

P C 19 4
P C 21 0

V 1 .8

6
VIN
VIN
PO K

8

E N 1. 8V S 1
P C 18 8

10/22

S

1

1 0 K_ 0 4

PJ 2
4 0m i l

P O K _ 6 61 0

3

P Q7 0
MT N 7 0 0 2Z H S 3

G

6

R 5 47

4

4

5

5
9
7

1 0K _ 0 4

1 . 8V S _P W R G D

2 0 1. 8 V S _ P W R GD

PQ 5 B
M TN N 2 0 N 0 3 Q8

6 8 00 p _ 50 V _ X 7 R _ 0 4

P R2 2 8

1 0u _ 1 0V _ Y 5V _ 0 8

1K _ 1 % _ 04

ON

NM OS

V IN

FBVDDQ

S S _0 . 8 5 V S 3 . 3 V
9 . 3 1 K _ 1% _ 0 4

P R 1 93

1 0 K _ 1 %_ 0 4

12 K _ 1 % _0 4

2

1 M_ 0 4
10 u _ 10 V _ Y 5V _ 0 8

*O P E N _ 1 1 A
1 0 . 7 K _ 1% _ 0 4

P R 19 4
P C5 2

E A P _0 . 8 5 V S

P R1 9 5

SE
SE
SE
SE
FB

T3
T2
T1
T0

GN D
PH ASE
LG
VC C
RT
C SP

P C 14 7
2 2 _0 4

C S N _ 0. 85 V S

4 7 p _5 0 V _ N P O _ 04

P R2 0 6
*1 0 m li _ sh o rt

P R2 7 6

1 0 0 K _ 1% _ 0 4

1. 0 5 V S _ V T T _P W R G D 3

D

6 V C C S A _V I D 0
6 V C C S A _V I D 1

G

7

P R7

2

B - 38 Power 0.85VS, 1.8VS, PEX_VDD

P C1 4 5

1 00 K _ 0 4

2

1
* 6m i l
PJ 2 8

0 . 1 u _5 0 V _ Y 5 V _ 0 6
C S P _ 0. 85 V S
C S N _ 0. 8 5 V S

1

1 0_ 0 4

PC 1 6

PJ 2 6
2

P R 20 8

*6 m i l

P R 2 00

1 . 3 K _ 1% _ 0 4

P R 24

0 _ 04
V C CS A _ S E N S E 6

0 .9 V

PJ 2 9
4 0 m li

P J 30
12 K _ 1 % _0 4

P R2 3 7

* 1u _ 6 . 3V _X 5 R _ 0 4

1

M T N 7 0 02 Z H S 3

P Q3 1 B
P D 1 5 03 Y V S

P C1 5 1

+
PR 1 2
0_04

3
P R 19 6

* 6m i l
S

3 5 1 . 05 V S _ V T T _ P W R G D #

P C 14 4

0_ 0 4

3 3 K _1 % _ 04

0 . 8 5V _ O N

PQ 3 9

P C 14 1

3 .3 V
0 . 85 V _ O N

P R2 0 5
1 0 0 K _ 04

0 . 0 1u _ 5 0V _X 7 R _0 4

P R2 0 2
* 0_ 0 4

V 0. 85 P J 1 4
0 .8 5 VS
OP E N -6 mm
1
2

6A

P R1 1

P C 14 8
P C1 5 0

PL 5
T MP C 0 6 03 H - 1R 0 M-Z 0 1
1
2

P H A S E _0 . 8 5 V S
L G_ 0 . 8 5V S

R T_ 0 . 8 5 V S

C OMP _0 . 8 5 V S

0. 01 u _ 50 V _ X 7R _ 04

P D 1 50 3 Y V S

8
0 . 1 u_ 5 0 V _Y 5 V _ 06

5 6 0 u_ 2 . 5 V _6 . 6 *6 . 6 *5 . 9

P R2 0 4
5V

P C 14 0

4

1 K _ 1 %_ 0 4

EAP
SS
P OK
U G
B OO T

S E T 3 _ 0. 8 5 V S 6
S E T 2 _ 0. 8 5 V S 7
S E T 1 _ 0. 8 5 V S 8
S E T 0 _ 0. 8 5 V S 9
10
F B _ 0 . 8 5V S

21
20
19
18
17
16

P Q 3 1A

5
6

5
4
3
2
1
P R2 0 1

ON

1 0 K _ 1 %_ 0 4

1 5 K _ 1% _ 0 4
P R 1 99

11
12
13
14
15

P S _ N V V D D _P G OO D #

P R 19 8

P C1 9 8

C S P _ 0 . 8 5V S

4 1 P S _N V V D D_ P GO OD #

6

5

6

5

PU 9
u P 6 1 22

C O MP
V ID 0
V ID 1
E N /P S M
CSN

P Q 7 2B
MT N N 2 0N 0 3Q 8

6 8 00 p _ 50 V _ X 7 R _ 0 4

+

* 3 30 u _ 2. 5 V _ V _ A

P Q7 1 B
MT N N 20 N 03 Q 8

4

4

P C 23 2

0.85VS

B O OT _0 . 8 5 V S
1
2

9. 1 K _ 1 % _0 4

1 0 0 _0 4

0. 1 u _ 16 V _ Y 5 V _ 0 4

P C2 3 4

0 . 1 u_ 1 6 V _Y 5 V _ 04

P D2 1
R B 05 4 0 S 2

1 0 _0 4

1

P C 23 3

P R 2 75

3

F B V D D Q _P W R _ E N

P R1 8 7
1 0K _ 0 4
P R 18 8

2

PJ 3

0 _ 04

* 0 . 1u _ 1 6V _ X 7 R _0 6

1

F B _ V DD Q

P R 19 2

10/14

240MIL

3

P R 27 4

P R 18 9

0 . 1 u _5 0 V _ Y 5 V _ 06

P C1 3 7

4 . 7u _ 2 5V _ X 5 R _0 8

F B V D DQ

0. 0 2 2 u_ 1 6 V _ X 7R _ 04

P Q7 1 A
MT N N 2 0N 0 3Q 8
8
2
7
1

P C 1 23

5V

11A

SY S1 5 V

4 . 7 u _2 5 V _ X 5 R _ 0 8

0 . 85 V S _ P W R GD 2 0

PC1 2 2

9. 3 1 K _ 1 %_ 0 4
P R 1 91

0. 1 u _ 50 V _ Y 5 V _ 0 6

P R 19 0

P C 1 21

P Q7 2 A
MT N N 2 0N 0 3Q 8
8
2
7
1

PC1 3 1

1. 5V

A

10/13

C

Sheet 37 of 49
Power 0.85VS,
1.8VS, PEX_VDD

GS7113 6-02-07113-320
AX6610 6-02-06610-320
APL5930KC 6-02-05930-420

1 u _1 0 V _ Y 5 V _ 06

B.Schematic Diagrams

PU 1 1
2. 2 u _ 6. 3V _ Y 5V _0 6

P R2 2 6

3 .3 V

1 00 _ 0 4
P C 22 9

P C1 9 2

2A

* OP E N _ 5A
P R2 2 3

3

1 . 05 V _ P W R _ E N

P C 23 0

1 0u _ 1 0 V _Y 5 V _ 0 8

PQ 5 A
8
7

P R 22 2

1.8VS

0 . 1 u_ 1 6 V _ Y 5V _ 0 4

NM OS

1. 0 5 V S

* 1 0u _ 1 0V _ Y 5 V _ 0 8

SY S1 5 V

VCC SA _V ID 0
VCC SA _V ID 1

0
0
SET0

6
0 .8 5 VS
6 ,2 3 ,2 4 1 .8 V S
3 5, 3 6 S Y S 1 5 V
3, 6, 8 , 9 , 1 0, 25 , 2 9 , 33 , 3 5 , 3 8 1 . 5 V
1 2, 1 3 P E X _ V D D
13 , 1 4 , 1 5 F B V D D Q
3 5, 3 6 S Y S 5 V
2 5 , 2 7, 28 , 2 9 , 35 , 3 8 , 4 1 5 V
1 1, 3 5 , 3 6, 38 , 3 9 , 40 , 4 1 , 4 2 V I N
6, 1 8 , 1 9, 20 , 2 4 , 25 , 2 9 , 3 5, 3 8 , 3 9 1. 0 5 V S
2, 3 , 8 , 1 1 , 12 , 1 6 , 1 8, 1 9 , 2 0, 22 , 2 3 , 24 , 2 5 , 2 7, 2 8 , 2 9, 30 , 3 3 , 35 , 3 8 , 3 9 3 . 3 V

0. 8V

0 .7 25 V 0 .67 5V

0
1
SET2

1
1
0
1
SET1 SET3

Schematic Diagrams

Power 1.5V/1.05VS/0.75V
4
2
3
1
23

P C 85

22
V L DO IN

1 0 u_ 1 0 V _ Y 5 V _ 08
1

VB ST

VBST

24

VTT

VTT

21

D RV H

P C1 8 1

0 . 1u _ 1 0V _ X 7 R _ 0 4

20

LL

D RV H

V T T GN D

PJ 1 6
1

2
1 .5 V

P C8 4
P R1 1 9

D RV L

S 5 _6 1 6 3

C

5
6
7
8

11

2 . 2 _ 06

A

2
3
1

A
P C7 7

10

S 3 _6 1 6 3

+

P R1 1 6

PC 7 9
3 .3 V

8/18

DEL PR223,PR222,PC177
P R 2 20

P R1 0 6
1 0 0 K _ 04

GN D

S3
N C

D
S

P GO OD _6 1 6 3

1 u _ 1 0V _ Y 5 V _ 0 6

P R1 0 8

P R 1 10

13

S5

9
V D DQ S E T
V D D QS E T
* 1 00 0 p _X 7 R _0 4

PC7 2

*M TN 7 00 2 Z H S 3

*1 0 _ 04

*1 0 00 p _ X 7 R _ 0 4

P Q1 3
G

4

P V C C 5 _ 6 16 3

P GO OD

V D DQ S NS

4

6 . 2 K _ 1% _ 0 6

1 u_ 1 0 V _ Y 5V _0 6

P C7 6

C O MP

V D D QS N S 8

PR1 0 7

*2 2 _0 4

P R1 1 2

15
14

P V C C5
V C C5

V T T RE F

0_ 0 6
5V

CS

P C1 7 1

0 _ 06

Sheet 38 of 49
Power 1.5V/1.05VS/
0.75V

DD R1 .5 V _ P W RG D
DD R1 .5 V _ P W RG D 2 0

5V
* 1 0K _ 1 % _ 04
P R 22 1

D

PJ 7

2 8 , 35

P Q1 6

D M N 6 0 1D W K -7

2 0 , 34

5G

*M TN 7 00 2 Z H S 3

4 0 mi l
4

S US C #

0 . 1 u _ 16 V _ Y 5 V _ 0 4

G

S

P Q1 7 B
S

9 . 7 6K _1 % _ 06

P C7 4

2G

1 00 K _ 0 4
3

P Q 17 A
D
D M N 6 0 1D W K -7

S

P R 1 05

0. 1 u _ 16 V _ Y 5 V _ 0 4

2G

1

P C6 6
D
P Q1 4 A

5V

S

D D _ ON #

D M N 6 0 1D W K -7

A

V IN
5V

P D2

1u _ 1 0V _Y 5 V _0 6

P R 16
4 . 0 2K _ 1 % _ 04

1

PR 1 8

P J3 1
*6 m li

10 _ 0 4
2

5
6
7
8

5
6
7
8

C
S K 3 4S A

0 . 1 u _ 50 V _ Y 5 V _ 06
P C 16 0

*6 m li P J 4 2
2
1

*9 0 . 9 K _ 04

F B _ 1 . 0 5V S _6 1 2 7

PC 1 9

PC 2 1

P R 15

0 . 0 1 u_ 1 6 V _X 7 R _ 0 4

* 2 0p _ 5 0V _ N P O_ 0 4

1 0 K _1 % _ 0 4

V C CP _ S E N S E 5

PC 2 2
2

1

* 15 p _ 50 V _ NP O_ 0 4
*6 m li

P R1 3

2

*O P E N -1 2 m m
P C 1 58
+

0 . 1 u_ 1 6 V _Y 5V _ 0 4

P C2 0

+
P D3

4

R TN

5V

1 . 0 5V S

P J 15

V C C P _ S E N S E _ 61 2 7

0 _ 04

20A

V1 .0 5
1

* 5 60 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9

17

R TN

PR 1 4

1.05VS

P C 1 59

* ME 4 6 2 6- G

A

G ND

P Q 37
PQ 3 4
ME 4 6 2 6-G
4

D L

5

N .C
7

N. C
8

PAD

4

2
3
1

D L
R TN

FB

BS T

3

2
3
1

VC C

56 0 u _2 . 5 V _ 6 . 6* 6. 6* 5. 9

9

P C1 2 5

1
BS T

V OU T

+

LX
2

P GD
10

P C1 3 5

4 . 7 u _2 5 V _ X 5 R _ 0 8

5
6
7
8
2
3
1

DH

LX

11
P K 39 0 6

P C 1 34

PL 6
TM P C 1 0 0 4H -1 R 0 M- Z 01
1
2

0 . 1u _ 5 0V _ Y 5V _0 6

16

15

P C1 7

D H

EN

N .C

12

1 . 0 5 V S _ P W R GD

20 1 . 0 5 V S _ P W R G D

N .C

IL IM

1 0 K _ 04

14

13

I LI M

* 0. 1 u _ 16 V _ Y 5V _ 0 4

P R1 0

0 . 1 u _5 0 V _ Y 5 V _0 6

C

4

6

3
3. 3 V

PQ 3 5
ME 4 8 9 4-G

P C 15

D MN 6 01 D W K -7

P C 1 30

5 . 1 K _ 1% _ 0 4

PU 1
U P 61 2 7

S
P Q1 4 B

P C 1 32

R B 0 5 4 0S 2
P R9

D

5G

*1 5u _ 2 5V _6 . 3 *4 . 4 _ C

1 . 0 5 V _ ON

SU SB

4 . 7 u _2 5 V _ X 5 R _ 0 8

PR 8
10 0 K _ 04

4

SU SB

4 7 K _ 04

D

P R 1 04

5V

9. 5 3 K _ 1 %_ 0 6

6

P R1 0 9
VTTEN

1

* 10 0 K _ 0 4

2

P R9 3

6

3 1 . 5 S _ C P U _P W R G D

1 0 0K _0 4

1

5V

P R9 5

VSSP_ SEN SE 5

PJ 3 2

9 , 1 0 V TT _ ME M
35 , 3 6 , 37 S Y S 1 5 V
1 3 , 1 4 , 15 , 3 7 F B V D D Q
2 5 , 2 7, 2 8 , 2 9, 35 , 3 7 , 41 5 V
1 1 , 35 , 3 6 , 37 , 3 9 , 4 0, 4 1 , 4 2 V I N
6 , 18 , 1 9 , 20 , 2 4 , 2 5, 2 9 , 3 5 , 37 , 3 9 1 . 05 V S
3 , 6, 8, 9 , 1 0 , 25 , 2 9 , 3 3, 3 5 , 3 7 1. 5 V
2 , 3 , 8 , 1 1, 1 2 , 1 6 , 18 , 1 9 , 2 0, 2 2 , 2 3, 24 , 2 5 , 27 , 2 8 , 2 9, 3 0 , 3 3, 35 , 3 7 , 39 3 . 3 V

Power 1.5V/1.05VS/0.75V B - 39

B.Schematic Diagrams

C OM P _ V D D 6

0 _ 06

P R1 1 5

16
C S

CSO D1 4 0 SH

V T T RE F 5
0 . 1 u_ 1 0 V _ X7 R _0 4

P C 78

P R 10 3

5V

P G ND
C S _G N D

MO D E

N C

*0 _ 0 6

GN D

4

7

P R1 1 1

M OD E

+

P C 1 72

25

*0 _ 0 6

12

0 _0 6

P R1 1 3

P D1 6

*5 . 1 _0 6

P R1 1 7

PD 1 5

P C 1 73

0. 1u _ 1 6V _ Y 5 V _ 0 4

V DD Q
5V

P Q 54
ME 46 2 6 -G

OP E N _ 8 A
P C 1 74

0. 1 u _ 16 V _ Y 5 V _ 0 4

0_ 0 6
18
17

C

P Q1 9
*ME 46 2 6 -G

DR V L

* S K 3 4S A

19
V T T S NS

3

5
6
7
8

2

1 0 u _1 0 V _ Y 5 V _ 0 8 * 1 0u _ 1 0V _Y 5 V _0 8

2
3
1

P R 12 1
0 _ 06 V T TS N S

LL

5 60 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9

PC 8 6

*1 0 00 p _ X 7R _ 06

P C 87

1 0 u_ 1 0 V _ Y 5 V _ 08

S US B

30A

5 60 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9

1
P C 88

3 , 35 , 3 7 S U S B

1.5V

V D DQ
PL 9
T MP C 1 00 4 H -R 5 6M -Z 0 1
1
2

P R 1 20
3 . 3 _ 06

O P E N_ 2 A

P R 96

P C8 3
0 . 1u _ 5 0 V _Y 5 V _ 0 6

R B 05 4 0 S 2

P J8

V T T _ ME M

P C8 9

V D DQ

VTT_MEM
2

P C9 0

5
6
7
8

u P 6 1 63

V T T _M E M

P C1 8 2

0 . 1u _ 5 0V _Y 5 V _ 0 6

P Q 55
ME 48 9 4 -G

4 . 7u _ 2 5V _ X 5 R _0 8

V IN
C

5V

4. 7u _ 2 5V _ X 5 R _0 8

P D 17
A

PU 6

Schematic Diagrams

Power V-Core1
1.05VS_VTT
P C 1 64 6 80 p _ 50 V _ X 7R _0 4

P R2 8

P R3 3

P R4 7

13 0 _ 1% _ 0 4

*7 5 _ 04

5 4. 9 _ 1 %_ 0 4

2 4 . 9 K _ 1% _ 0 4

H_ C P U_ S V ID DA T
H _ C P U _ S V I D A LR T#
H _ C P U _S V I D C L K

B~43 50

P C 16 3

PUT COLSE
TO VCORE
Phase 1
Inductor

R T2

33 0 0 p_ 5 0 V _X 7 R _ 0 4

A_GN D

1

2

1 00 K _ N T C _0 6 _ B
DI FFOU T

5 H_ CP U_ S V IDD A T
5 H _ C P U _ S V I D A L R T#
5 H_ CP U_ S V IDC L K

P R2 1 1

TSE NSE

P C 29
P R3 9

10 0 _ 04

P R4 0

1K _0 4

1 0 0p _ 5 0V _ N P O_ 04

PC 3 4

2 2 p_ 5 0 V _N P O_ 0 4
P R5 0

FB

T RB ST

P R 2 0 9 1 . 2 k_ 1 % _0 4

10/13

P R3 6
PC 3 0
4 . 0 2 K _1 % _ 04

3 3 00 p _ 50 V _ X 7R _ 04

P R 32

P R4 8
10 K _ 0 4

P R7 7

3 H _ P R OC H OT #

P R 49

P R4 4

1 0 K _0 4

2 0 D E L A Y _P W R GD
V R _O N
P R5 3

5VS

P R5 2

0 _ 04

2 . 2_ 0 6
A_G ND

TSE NSEA

P R5 7

VIN

1 K _ 1% _ 0 4

VSP
T S E NS E
V R H OT #
S DIO
S CL K
A L E RT #
V R_ R DY
V R_ R DY A
E N A B LE
V CC
RO S C
V RM P
T S E NS E A

P R6 1

PC 4 0

*1 4K _ 1 % _0 4

0 . 0 1 u_ 5 0 V _X 7 R _ 0 4

A_G ND

1 0 0K _N T C _ 0 6_ B

A_GND

IMO NA

I MO N

N C P 6 13 1 S

V S N A _ 61 3 1
V S P A _ 6 13 1

1 u _6 . 3 V _ X 5 R _ 0 4

R T4
1

P R 2 16

B~ 3 964
2

8 . 2 5 K _1 % _ 04

CSCO M P

TR BST
A_G ND

1
TSENSE 2
3
4
H_CPU _S VIDD AT
5
H_CPU _S VIDC LK
H_CPU _S VIDALRT# 6
7
VR_RD Y
8
VR_RD YA
V R _ ON _E N A B L E _ 61 3 19
6131_VC C 1 0
1
1
PR 5 4
1 0K _ 0 4
V R MP _V I N 1 2
TSEN SEA 1 3

P C3 9
P C4 1

40

1014

P R2 1 4

1 0_ 0 4

P R2 1 3

1 0_ 0 4

CS N 1

40

CS N 3

40

CSN 3
P C3 7

10 0 0 p_ 5 0 V _X 7 R _ 0 4

PU 3

0 . 0 4 7u _ 1 0V _ X 7 R _ 0 4

P R 45

5 . 49 K _ 1 %_ 0 4
C SP3
C SN1

A_G ND

5VS
P R4 2

C S N2
CS P 2
C S N3
CS P 3
C S N1
CS P 1
D R ON
P W M 1/ A D D R
P W M3 / V B O OT
P W M2 / I S H E D
I MA X
P W MA / I MA X A
V B O OT A

39
38
37
36
35
34
33
32
31
30
29
28
27

CSN 1
P C3 8

CS N 3
CS P P 3
CSN 1
CS P P 1
D R ON

5 . 49 K _ 1 %_ 0 4
C SP1
D R ON

P R5 5

5VS

0 _0 4

P R2 1 8

V R 1 _P W MA 4 0

P R5 9

10 K _ 0 4

5VS

* 10 K _ 0 4

1 1 3K _ 1 % _0 4
2

1

1 0K _ 0 4

P J2 4

* 6 mi l

P R5 6
P R2 1 9
1 8. 7 K _ 1 %_ 0 4

1 0 K _ 04

76 . 8 K _ 1% _ 0 4

OPTION:
1014
DISALBE
ICC_ MAX_2 1h A_GN D
V_GT
=R *1 0uA*25 6A/ 2V

1 02 5A_GN D
2 2 00 p _ 50 V _ X 7R _0 4

P R2 1 5

A_GN D

A_G ND

P R2 3 2
PJ 2 3
*6 m i l

1 02 1

1 13 K _ 1 %_ 0 4

A_G ND
A_GN D

CSN A
CSPPA

P C 48
C SPA

P R 2 10

P C 1 65

C SCO MPA

P C4 9

47 0 p _5 0 V _ X7 R _0 4

C OMPA

P C4 5

27 0 p _5 0 V _ X7 R _0 4

1 1 0K _ 1 % _0 6

40
P R6 4
4 . 87 K _ 1 % _0 6

PUT COLSE
TO V_GT
HOT SPOT

22 K _ 1 %_ 0 4

PR 6 2

0 . 1u _ 1 0V _ X 5 R _ 0 4

1014

10 21
A_GN D

A_GND

1014

1 3 . 7 K _1 % _ 04 0 2

0. 1u _ 10 V _ X 5 R _ 04

1014

A_G ND

D IFFO UTA
A_GND

P R7 0

P R 2 3 1 0 0_ 0 4

P C4 4

P R6 5
6 8p _ 5 0V _ N P O_ 0 4

FBA
P R 6 7 0 _0 4

40

V _ GT

2

1 0 0 K _N T C _ 06 _ B

PC 4 3

P C 47
1 0 00 p _ 50 V _ X 7R _ 04

B~435 0

1 0 0p _ 5 0V _ N P O_ 0 4

P R6 8
P R 2 5 1 0 0_ 0 4

16 5 K _ 1% _ 0 6

R T3
1

1K _0 4

P R 6 6 0 _0 4
6 V S S _ G T_ S E N S E

6 V C C _ GT _ S E N S E

P R 73
7 5K _ 1 % _0 4

1 0 _1 % _ 04

PR 7 1

PC 5 0
3 . 01 K _ 1 %_ 0 4

3 3 00 p _ 50 V _ X 7R _ 04

PUT COLSE
TO V_GT
Inductor

3 .3 V S

1

1 0 K _0 4
P R 23 8

2

PJ 4
*6 m i l
P R6 3
1 1 , 20 , 3 4 A L L_ S Y S _P W R G D

*1 5 m li _ sh o rt
V R _ ON
2 , 3, 8 , 1 1 , 12 , 1 6 , 18 , 1 9 , 20 , 2 2 , 23 , 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 3 3 , 3 5, 3 7 , 3 8 3. 3 V
2, 3 , 5 , 2 3, 2 4 , 2 5, 3 5 1 . 0 5V S _ V T T
6 , 1 8, 1 9 , 2 0, 2 4 , 2 5, 2 9 , 3 5, 3 7 , 3 8 1. 0 5 V S
1 1 , 3 5, 3 6 , 3 7, 3 8 , 4 0, 4 1 , 4 2 V I N
11 , 1 8 , 2 4, 2 5 , 2 7, 2 8 , 3 1, 3 2 , 3 3, 3 5 , 4 0 5V S
3, 6, 9 , 1 0 , 11 , 1 2 , 18 , 1 9 , 20 , 2 1 , 22 , 2 3 , 24 , 2 5 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5 3. 3 V S

B - 40 Power V-Core1

CSN A

0 . 0 4 7u _ 1 0V _X 7 R _ 0 4

P R 72

2 4. 9 K _ 1 % _0 4
A_GN D

V R 1_ P W M 1 40

V R 1 _P W M3 4 0

P W M2 _ 6 13 1
I MA X _ 6 13 1
VR1_PWMA

P R 23 3

40

40

C SSUMA
P C4 6

40

0 . 0 4 7u _ 1 0V _ X 7 R _ 0 4

P R5 1

PR 5 8

P C4 2

40

0_04

C S N 2_ 5 V S

I MO N

P R6 9

40

P C3 5
A_GND

* 7 5_ 0 4

0_04

C SP3

13 7 K _ 1% _ 0 4

1

6-13-93121-28B

1.05VS

I MO NA

* 0_ 0 4

*1 5 mi l _s h o rt

53
52
51
50
49
48
47
46
45
44
43
42
41
40

0 _ 04

PR 7 4

3 3 0 p_ 5 0V _X 7 R _ 0 4
CSSU M

EPAD
D IF F O U T
VSN
T RBS T
FB
C OM P
IL IM
D R O OP
C S C OM P
C SSUM
IOU T
C SRE F
NC 2
N C1

PR 7 5

1 0 0 0p _ 50 V _ X 7 R _ 04

P C3 2

V R1_C SREF

VSNA
VSPA
FBA
D IF F OU T A
T RB ST A
CO M PA
I LI M A
D R OO P A
C SCO M PA
IOU T A
C SSUM A
CSP A
C SNA

V CO RE

3.3V

P R6 0

P C3 1

14
15
16
17
18
19
20
21
22
23
24
25
26

5 , 40

3.3VS

1 0 0_ 0 4
V C C _ S E N S E _ 61 3 1

1 0 0K _N T C _ 0 6_ B

2

0 _0 4

5 V C O R E _ V C C _S E N S E
P R 19

20 K _ 1 % _0 4

10 21

C OM P_ CPU

R T1

P R 2 07
1

P R3 8

B~ 3 964
9 3 . 1 K _1 % _ 06

0 . 1u _ 1 0V _X 7 R _0 4

10 0 0 p_ 5 0 V _X 7 R _ 0 4

PUT COLSE
TO VCORE
HOT SPOT

Sheet 39 of 49
Power V-Core1

PR 4 1
V S S _S E N S E _ 6 13 1

0 _0 4

P C3 3

A_GN D

0 . 1u _ 1 0V _X 7 R _0 4

B.Schematic Diagrams

P C3 6

40

1 6 5K _ 1 % _0 6

1 0 0_ 0 4
P R3 4

C SP1
P R 35
P R4 6

P R 22
5 V C OR E _V S S _S E N S E

Qua d 45 W CPU
VID1 =0.9 V
Ic cMa x= 9 4A
R_LL= 1. 9m ohm
OCP ~1 20 A

13 7 K _ 1% _ 0 4

7 5K _ 1 % _0 4

2

P R 21 2 10 _ 04

VCORE_1

Q ua d V CCAXG
VI D1=1 .15 V
I ccMa x = 26 A
R_ LL= 3 .9m ohm
O CP~31 A

C SPA

40

40

Schematic Diagrams

Power V-Core2

G ND 6
LG 5

V CC

S

1

G

G

G
S K 3 4S A

A

S

S

S

PAD
P C 28

SW

5VS

7

V R E G_ S W 3 _O U T
PQ 3 6
M D U 26 5 4

G ND 6
LG

5

G
S

V R E G_ S W 3 _H G

PQ 3
M DU2 6 5 4

P Q3 3
M D U 2 65 4

* 33 0 u _C A R 3 1 5L

P C2 5

V R E G_ S W 3 _L G

1
G

G

A

SK3 4 SA

S

S

S

1u _ 6 . 3V _X 5 R _ 0 4

C S N3

39

PR 2 0

*1 5 mi l _ sh o rt

C SP3

39

0 . 1u _ 5 0V _ Y 5 V _ 0 6

PR 2 9

*1 5 mi l _ sh o rt

PQ 4 7
M D U 26 5 4

GN D 6

V GFX_COR E

VRE G_SWA_LG
G

P C 1 62
P R 37

CS N A

39
+

P R 43

10 26

* 1 5m i l_ s h ort

CS P A

39

P C1 6 6
+

10 26

V C OR E
P C1 3 9
+

P C 1 55
+

P C 1 57
+

P C 1 36
+

P C 14 3 P C 2 6
+

*5 6 0u _ 2 . 5V _ 6 . 6 *6 . 6 *5 . 9

+

5 6 0u _ 2 . 5V _ 6 . 6 *6 . 6 *5 . 9

P C1 4 9
5 6 0u _ 2 . 5V _ 6 . 6 *6 . 6 *5 . 9

A
5 , 39

* 1 5m i l_ s h ort

5 60 u _2 . 5 V _ 6 . 6* 6. 6* 5. 9

G

9

5 60 u _ 2. 5 V _ 6 . 6* 6 . 6* 5. 9

5

39

P D5

5 60 u _ 2. 5 V _ 6 . 6 *6 . 6* 5 . 9

LG

P Q7
*M D U 2 6 5 4

V _G T

VGFX_CORE

PL 8
T MP C 1 00 4 H -R 3 6M -Z 0 1
1
2

VRE G_SWA

PA D
PC 5 3

VGFX_CORE

P C1 6 7

S
VRE G_SWA_HG

C

3
4 9. 9 _ 1 %_ 0 4 E N
4
V CC

7

SK3 4 SA

5VS

SW

D

P R7 8

HG 8

PW M

S

DRO N

BST

S

39

2

1 u_ 6 . 3 V _X 5 R _0 4

V R 1 _ P W MA

D

1
39

N C P 59 1 1

P C 1 68
4 . 7u _ 2 5V _ X 5 R _ 0 8

PQ 8
M D U 26 5 7
G

P U4

V C OR E 5 , 3 9

*1 5 mi l _ sh o rt

4 . 7 u_ 2 5V _X 5 R _0 8

1014

Sheet 40 of 49
Power V-Core2

2

D

0 .2 2 u_ 1 0 V _X 7 R _ 0 6

39

PL 1 3
PR 2 1
* TM P C 1 0 04 H -R 3 6 M-Z 0 1

P C1 6 9

P C5 1

CS P 1

G

9

2. 2 _ 0 6

39

V COR E

VIN

PR 7 6

CS N1

PD 2 2

PAD
P C1 4 2

P C2 3

P L4
TM P B 1 23 5 MP -R 3 6M -Z 0 1
1
2
C

P WM

3
49 .9 _ 1% _ 0 4 E N
4
V CC

8

S

G
HG

D

2
P R1 9 7

BST

P C2 4

1 5 u_ 2 5 V _6 . 3 *4 . 4

D
D RO N

*1 5 mi l _ sh o rt

P Q4
M D U 2 65 7

D

1
V R 1 _ P W M3

PR 2 6

D

PQ 3 8
M D U 26 5 7

P U1 0 NCP 5 9 1 1

39

*1 5 mi l _ sh o rt

VIN

0 . 22 u _ 10 V _ X 7R _ 06

D

P C 1 46

1014

39

PL 1 4
* TM P C 1 0 04 H -R 3 6 M-Z 0 1 P R 2 7

P C1 3 8
+

2. 2 _ 0 6

V C OR E 5,3 9

2

+

P C1 8
+

6 V GF X _ C O R E
5 ,3 9 V C O R E
1 1 ,35 , 3 6 ,37 ,3 8 , 39 , 4 1 , 42 V I N
11 ,1 8 , 24 , 2 5 ,27 ,2 8 ,31 ,3 2 , 33 , 3 5 ,39 5 V S
3,6 , 9 , 1 0, 1 1 ,1 2,1 8 , 1 9, 2 0 , 2 1, 22 ,2 3 , 24 , 2 5 , 27 , 2 8 ,29 ,3 0 , 31 ,3 2 , 33 , 3 4 ,35 ,3 9 3 .3V S

Power V-Core2 B - 41

B.Schematic Diagrams

1 u _6 . 3 V _ X 5 R _ 04

9

P R 20 3

V COR E

P D4

V R E G_ S W 1 _ L G

* 33 0 u _2 . 5 V _ V _ A

5VS

EN

5 60 u _ 2. 5 V _ 6 . 6* 6 . 6* 5 . 9

4

P Q6
M D U 2 65 4

*3 3 0 u_ 2 . 5 V _V _A

3
4 9 . 9 _1 % _ 04

P Q 42
M DU2 6 5 4

+P C 17 7

* 33 0 u_ 2 . 5 V _ V _A

PR 3 0

PQ 4 3
M D U 26 5 4

0 . 1 u _5 0 V _ Y 5V _ 0 6

D RO N

SW

P L7
TM P B 1 23 5 MP -R 3 6M -Z 0 1
1
2

V R E G_ S W 1 _ OU T

7

P WM

4 . 7 u _2 5 V _ X 5R _ 08

39

2

4 . 7 u _2 5 V _ X 5 R _ 08

V R 1 _ P W M1

G

V R E G_ S W 1 _ H G

HG 8

C

39

NCP 5 9 1 1

BST

S

1

D

P U2

P Q4 0
M D U 2 65 7

G

P C1 5 2
0 . 1 u _5 0 V _ Y 5V _ 0 6

PQ 4 1
M D U 26 5 7

1014

D

0 . 22 u _ 10 V _ X 7R _ 06

D

P C2 7

D

2. 2 _ 0 6

D

P R 31

P C1 5 3

*4 . 7 u _2 5 V _ X 5R _ 08

P C 1 54

* 4. 7u _ 25 V _ X 5 R _ 0 8

VIN

VCORE_2

Schematic Diagrams

Power VGA NVVDD
1 029
0.975V 1V

0.825V 0.8V

NVVDD_VID0

0

0

1

NVVDD_VID1

0

1

0

1
1

S ET0

S ET2

S ET1

S ET3

VDD3

1108
3V3_RUN
PC101

PR138
10K_04

0.047u_10V_X7R_04

PS_NVVDD_PGOOD# 37
D

PR123
10K_04

1 111

S

5V

11. 8K_1%_04
A

PC99
*100p_50V_NPO_04

PD18
PR133
13. 7K_1%_04

RB0540S2
PR131

PC3

PC4

PC2

PC5

PC98

4.7u_25V_X5R_08

4.7u_25V_X5R_08

4.7u_25V_X5R_08

4. 7u_25V_X5R_08

4. 7u_25V_X5R_08

0.01u_50V_X7R_04

S

S

PR236

C

10 29

PD23
PR2
5.1_06

G
PR128
0_04
220p_50V_NPO_04
PR124
12K_1%_04

100K_04
2

2

PJ25
*6mil
PJ27

PR127
0_04

PC1

PC95

1
CSP_NVVDD
0.1u_25V_X7R_06
6-07-10422-7G0

1

+

+

PC94
*0.1u_16V_X7R_06

*6mil

16 NVVDD_VID0

1112
PR234

EN_VGA_CORE

16 NVVDD_VID1

VDD3

3V3_RUN
PR129

2
PR235

PJ10

PR145

10_04

PR146

0_04

PR147

0_04

PR148

10_04

PJ41
1

2
*6mil

PR126

1.2K_1%_04

*6mil

11/10
PR251
100K_04
PC100
*2200p_50V_X7R_06

3,6, 9,10,11,12,18, 19,20,21,22,23, 24,25,27,28, 29,30,31,32,33, 34,35,39 3. 3VS
17
NVVDD
12,16 3V3_RUN
25, 27,28,29,35,37, 38 5V
18,27,28,30,34, 35,36,42 VDD3
11,35, 36,37,38,39,40, 42 VI N
2,3, 8,11,12,16,18, 19,20,22,23,2 4,25,27,28,29, 30,33,35,37,38, 39 3.3V

B - 42 Power VGA NVVDD

1

100K_04

10K_04

PR152

10K_04

CSN_NVVDD

100K_04

PS1_VDD_SENSE 12
PS1_GND_SENSE 12

*560u_2.5V_6. 6*6.6*5.9

100K_1%_04

G
C990317

PD1

PJ11
1

0.1u_10V_X7R_04

PR137

VDD3

PQ30
MDU2654

31A

560u_2.5V_6.6*6.6*5. 9

47p_50V_NPO_04

G

PQ22
MDU2654

C

33K_1%_04

CSN_NVVDD
PC105
PC102
PR140
*0_04

PQ1
MDU2654

D

11
12
13
14
15

PR125

N12P_VGA
VGA_VCORE

PC97

22_04

PL2
BCI H1367HC-R82M
1
2

PC106

PR139

PL12
*TMPC1004H-R36M- Z01
1
2

111 1

PC103

PC104 0. 01u_50V_X7R_04

G

S

21
20
19
18
17
16
CSP_NVVDD

1K_1%_04

GND
PHASE
LG
VCC
RT
CSP

0.1u_50V_Y5V_06

A
SK34SA
A
*CSOD140SH

PR136

SET3
SET2
SET1
SET0
FB

PC96

D

6
7
8
9
10

G

PC199

S

PU7
uP6122

EAP
SS
POK
UG
BOOT

15. 8K_1%_04

COMP
VI D0
VI D1
EN/PSM
CSN

PR135
11. 8K_1%_04

PR144

PQ29
MDU2657

D

PQ21
MDU2657

S

10. 7K_1%_04

12.7 K_1%_04

D

PR134
PR143

D

0_04

5
4
3
2
1

Sheet 41 of 49
Power VGA NVVDD

15. 8K_1%_04
C

PR142

1u_10V_Y5V_06

B.Schematic Diagrams

PR132
11K_1%_04

VIN

G

PR130
0_04

PR141

PQ20
MTN7002ZHS3

NVVDD
2

*12mm

Schematic Diagrams

AC_IN, Charger
0_04

P R1 7 8
0 _0 4

P R 1 83
0_04

A
R B 0 5 4 0S 2
C B _3 9 A 1 32

P C 1 33

PIN25 th
FOR 2SCONNECT TO GND
FOR 3SCONNECT N.C.
FOR 4SCONNECT TO VREF PI N

1 u_ 2 5 V _0 8

*0 _ 04

P R1 8 1

*0 _ 04

P C 1 27

0 . 1u _ 5 0V _ Y 5V _0 6

MB 3 9 A 1 32

1 5 . 4 K _1 % _ 0 4
P C 11 9
0 . 01 u _ 50 V _ X 7R _ 04

C
AC

B A T_ D E T

A

D7
B A V 99 R E C T I F I E R

S GN D 5
34

C

P R 2 48

* 10 m i l_ s h ort

T OT A L _ C U R

AC

B A T_ V O L T
B A T _ V OL T

S G ND 5

CUR _ S E NS E
A

D8
B A V 99 R E C T I F I E R

0 . 1 u _5 0 V _ Y 5 V _ 0 6

P C1 2 0

V R E F _ 3 9 A 13 2
R T _3 9 A 1 3 2
P R 1 73
C S _ 3 9A 1 3 3
P C 1 17
V OL T -S E L
B A TT _ 3 9A 13 2

0 . 1 u _5 0 V _ Y 5 V _ 0 6

FOR EMI
SG ND 5

S GN D 5

P R 1 55

P R1 5 4

1 K _ 1 %_ 0 4

4 9. 9 K _ 1 % _0 4

VH =4 .2 V ( 22 00 mA H c el l)
VL =4 .3 V ( 28 00 mA ce ll )
V S H G_ S E L 34
P C 1 13

P R1 6 5

P R1 5 8

P R1 5 9
1 0 0 p_ 5 0 V _N P O_ 0 4

P R 1 56

1 0K _ 1 % _0 4
P R 2 49

36

P C1 1 6

1 K _1 % _ 04

1 0 2 K _1 % _ 04

*1 0 m li _ sh o rt

2 M _1 % _ 04

4 7 p _5 0 V _ N P O _0 4

P R 1 67

Sheet 42 of 49
AC_IN, Charger

3 9 . 2 K _1 % _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4

A D J 2 _3 9 A 1 32
-I N C 2_ 3 9 A 13 2
+I N C 2 _ 39 A 1 3 2

PR32 = 10K for W760C

P C 1 15
A C_ IN

C T L1 _ 3 9A 13 2

F OR B 410 0

V OL T -S E L

2 2 K _ 1% _ 0 4

D

A

D1 1
B A V 99 R E C T I F I E R

34

VIN
CT L 1
G ND
TRERMAL PAD V R E F
R T
CS
A DJ 3
BATT
S G ND

P R2 4 6

Support Intel V-Pro Function

*O P E N _ 1 0 mi l -1 MM
1 00 0 p _5 0 V _ X7 R _0 4

PQ 2 5

P R1 6 6

P J 40

0_04

M T N 7 00 2 Z H S 3

2

P C1 1 1
2 20 0 p _5 0 V _ X7 R _0 4

P R 2 47

G

2 2K _ 1 % _0 4

V D D3

S

P R 1 76
C

AC

S MD _B A T

0 . 1u _ 5 0V _ Y 5 V _ 0 6

32
31
30
29
28
27
26
25

1 0K _ 1 % _0 4

P C1 2 4

C TL2
CB
O U T -1
LX
V B
OU T -2
P GND
CEL L S

V CC
-I N C 1
+I N C 1
A CIN
A CO K
-I N E 3
A DJ 1
C OM P 1

24
23
22
21
20
19
18
17
33

P R1 5 7
*0 _ 04

7 6. 8 K _ 1 % _0 4
P R 1 50

J BATTA1

1

P R1 7 5
2 0 K _ 1% _ 0 4

A

D1 0
B A V 99 R E C T I F I E R

VA

-I N E 1
OU T C 1
O UT C 2
+ IN C 2
-I N C 2
ADJ 2
C OM P 2
CO M P 3

C
AC

S MC _B A T

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

1 0 K _ 04
4 . 7 K _ 04
4 . 7 K _ 04

P U8

- I N E 1 _ 39 A 1 3 2
O U T C 2 _ 3 9A 13 2

R2 0 7
R2 1 5
R2 1 2

0 . 1 u _5 0 V _ Y 5 V _0 6

0 . 1u _ 5 0V _ Y 5 V _ 0 6

V D D3

P C8

P C1 2 9

V C C _ 3 9A 1 3 2
-I N C 1 _ 39 A 1 3 2
+ I N C 1_ 3 9 A 1 32
A C I N _ 3 9A 1 3 2
A C OK _ 3 9A 1 3 2
-I N E 3_ 3 9 A 1 32
A D J1 _ 3 9A 1 3 2
P R1 7 2

C 27

P C1 2

VA
P C 12 6

P C6

1
2
3
4
5

S GN D 5

* B T D -0 5 TI 1 G
C E LL S _ 3 9A 13 2

1 0 K _ 04

C

E

P D1 9 U DZ 1 6 B
A C_ IN#

A

2 8 ,3 4

P Q 2 3B
5G

D
P Q 6 2B

D MN 60 1 D W K -7

P R1 8 5
1 00 K _ 0 4

5G

P R 1 6 0 * 1M _ 04

P R1 8 2

P R1 6 9

1 8K _ 1 % _0 6

1 00 K _ 0 4

4

D M N 6 0 1D W K -7
G

3

C E CL M

P Q 6 2A

S

6

D MN 60 1 D W K -7

D

SY S3 V

P C1 9 7

5G

1 00 K _ 0 4

B T D -05 T I 1 G

FO R B51 00

S
6

P J 22

D

34

2G

P R1 8 4

C H G_ E N

S P Q2 8 A

D MN 60 1 D W K -7

P R 1 86
1 0 0 K _0 4

* OP E N _ 10 m i -l 1 M M

1 . 5M _ 04

P R6

2

S GN D 5

G

P R 1 62
2 0 0 K _1 % _ 04

* 15 m i _l s h ort _0 6

P J 13
*O P E N _ 1 0 mi l -1 MM

D M N 6 0 1D W K -7

2

B A T _ V OL T

P R 1 64

Battery Voltage:
9V~12.6V

0 . 01 u _ 50 V _ X 7R _ 04
1

S

S
1

P Q2 4
P R1 6 1
A O3 4 0 9 3 0K _ 1 % _0 4
D

P Q2 8 B

2G
1

34 C E L L_ C O N T R OL

D

MT N 7 0 0 2Z H S 3

VL =4 S1 P/1 .5 A

1
2
3
4
5

C T L 1 _3 9 A 1 3 2
P Q3 2

V H= 3S 2P/ 3A

4

2 0 0 K _1 % _ 04

BAT

B A T_ D E T
S MD _B A T
S MC _B A T

34
B A T_ D E T
2 8 , 3 4 S MD _ B A T
2 8 , 3 4 S MC _ B A T

S

P R 1 49

1

S

J BATTA2
S G ND 5

D

4

VA

S Y S 3V

P Q6 1
D T A 11 4 E U A

D

3 B

3

C

P R1 5 1

P C1 1 0

6 . 04 K _ 1 % _0 4

0 . 1u _ 1 6V _ Y 5V _0 4

S GN D 5

6

P Q2 3 A
D

VIN

D M N 6 0 1D W K -7
S
1

SY S3 V

2G
P C 1 78

P C1 5 6

PC 1 4

P C1 3

0 . 1 u_ 5 0 V _Y 5 V _0 6

0 . 1u _ 5 0V _ Y 5V _0 6

0 . 1 u _5 0 V _ Y 5 V _ 0 6

0 . 1u _ 5 0V _ Y 5V _0 6

3 5, 3 6 , 3 7 S Y S 1 5 V
35
VA
3 5 ,3 6
SYS5 V
1 8, 2 7 , 2 8 , 30 , 3 4 , 35 , 3 6 , 4 1 V D D 3
1 1 , 35 , 3 6 , 37 , 3 8 , 3 9, 4 0 , 4 1 V I N

AC_IN, Charger B - 43

B.Schematic Diagrams

C E LL S _ 3 9A 13 2 S G N D 5 P R 1 8 0

C 28

0 . 1u _ 5 0V _ Y 5 V _ 0 6

4 . 7u _ 2 5V _ X 5 R _0 8

PC 7
4 . 7u _ 2 5V _ X 5 R _ 0 8

0 . 1u _ 5 0V _ Y 5 V _ 0 6
P C 1 07

4 . 7u _ 2 5V _ X 5 R _0 8

P Q 2 6B
P D 1 50 3 Y V S

P C1 0 8

* 10 m i l_ s h ort

0 . 1u _ 5 0V _ Y 5V _0 6

C
PD 2 0

4 . 7 u _2 5 V _ X 5 R _ 0 8

PR 3
P R1 6 8
*1 0 m li _ sh o rt

BAT

0 . 1u _ 5 0V _ Y 5 V _ 0 6

PC1 2 8
P R1 7 0
1 00 K _ 0 4

3

PR 4
0 . 02 _ 1 %_ 3 2
4 . 7u _ 2 5V _ X 5 R _0 8

4
1 0K _ 1 % _0 4

BAT

3A

P C 1 09

P R1 7 7

5
6

P R 1 71

4

P C 1 18

0 . 1 u _5 0 V _ Y 5 V _ 0 6

Total Power : 80W

PL 3
0 6 0 3H -6 R 8 M-Z 0 1

1 0 0 0p _ 5 0V _ X 7 R _ 0 4

0 . 1 u _5 0 V _ Y 5 V _ 0 6
1 0 K _ 08
0 . 1u _ 5 0V _ Y 5V _0 6

0 . 33 u _ 16 V _ Y 5 V _ 06

P C9 3

0 . 02 _ 1 %_ 3 2

C ha rg e V ol ta ge 12 .6 V

0 . 1 u _5 0 V _ Y 5 V _0 6

P R 2 50

4

1 30 K _ 1 %_ 0 4
P C9 2

P R1 6 3

8
X L_ 3 9 A 13 2

P R1 7 4
PC 9 1

3
2
1

P C 9 4 . 7 u _2 5 V _ X 5 R _ 0 8

8
7
6
5

P Q 2 6A
P D 1 5 0 3Y V S
2
1
7
P C 1 0 4 . 7u _ 2 5V _ X 5 R _0 8

1
2
GN D 1
GN D 2

PQ 2 7
M E P 4 43 5 Q8

P C 1 1 *4 . 7 u _2 5 V _ X 5R _ 08

VA

PL 1
H C B 4 53 2 K -8 00 _ 1 8

2 0 0 K _1 % _ 04

11/5 EMI

J _ D C -J A C K 1
5 0 9 32 -0 0 30 1 -0 01

Charge Current : 3.0A

PQ 2
M E P 4 43 5 Q8
5
6
7
8

1
2
3

PC1 1 4

P R5

PC1 1 2

VA
V IN

Schematic Diagrams

W150HNM Audio Board
USB PORT(PORT3)
A _ U S B V CC
AL 6
H CB 1 6 08 K F -1 2 1 T2 5

A_ USB V C C2

60 mil
A C1 9
+
*1 00 u _ 6. 3 V _ B _ A

A _ US BV C C

AC3
0. 1u _ 10 V _ X 7 R _ 04
A J_ U S B 1

V IN 1

V OU T2

V IN 2

V OU T3

EN #

GN D

AC 1 5

8

4

1 0 u _1 0 V _ Y 5 V _ 08

1
V+
A G ND

7

3

AC 1 3

6

AC1 6

0 . 1 u _1 0 V _ X5 R _0 4

0. 1 u _ 10 V _ X 5R _ 04

2

A US B _P P 8_ R

3

D A T A _L

A C 17
A L7

1

A US B _P N 8 _R

11/2

D A T A _H
4

1 0u _ 1 0V _Y 5V _0 8

R T 97 1 5 B GS

A US B _P N 8

4

3

A US B _P P 8

1

2

G ND
C 1 07 7 0 -10 4 A 3

*W C M2 01 2 F 2 S -1 61 T 0 3-s h o rt
A G ND

A GN D

AG ND

GN D 2

F L G # V OU T1

2

GN D 1

5

60 mil

60 mil

G ND2

A U1

G ND 1

A _ 5V

B.Schematic Diagrams

A C1 1
+
2 20 u _ 6. 3 V _ 6 . 3 *6 . 3* 4 . 2

10/22

A GN D
A GND

Sheet 43 of 49
W150HNM Audio
Board

AUDIO BOARD

A C8
0. 01 u _5 0 V _ X 7R _0 4
AS P D IF O
A S P DI F O -R A L5
A USB _ PN 8

CO-Ray

A
A
A
A

A USB _ PP 8

A _ 5V

10/22

A M I C 1 -R
A M I C 1 -L
A _ AU DG
A H E A D P H ON E -R
A H E A D P H ON E -L
A M IC_ SE N S E
A S P K _H P #
A H P _ S E NS E
A S P K OU T R -_R
A S P K OU T R +_ R
A G ND
A U S B _ P N8 _ A U D 2
A U S B _ P P 8 _A U D2
ASPD IF O

0 _0 4
*0 _ 04
0 _0 4
*0 _ 04

A US
A US
A US
A US

B _P N
B _P N
B _P P
B _P P

8 _A U D1
8 _A U D2
8_ A U D1
8_ A U D2

F C M1 0 0 5K F -10 2 T 02

AR 3
2 2 0 _0 4

AC9

10 0 0 p_ 5 0 V _X 7 R _ 0 4

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

A GN D

A J_ S P K L 1
A MI C 1- R
A MI C 1 -L

A S P K O U T R -_ R
AS P KO UT R+ _ R

A HE A D P H ONE - R
A H E A D P H O N E -L
A MI C _ S E N S E
A SP K _ HP #
A HP_ SE N S E
A S P K OU TR -_ R
A S P K OU T R+ _ R

SPDIF OUT

A GN D
A MI C _ S E NS E

1
2

A MI C 1 -R

AL 3

F C M1 00 5 K F -1 2 1T 0 3

A MI C1 -R _R

A MI C 1 -L

AL 4

F C M1 00 5 K F -1 2 1T 0 3

A MI C1 -L _ R

5
4
3

A J_ M I C 1
R

8 5 2 04 -0 2 00 1
A C 18

A C 14

1 8 0p _ 5 0V _ N P O_ 0 4

MI C _ P I N 6
AC 2

1 80 p _ 50 V _ N P O_ 04

AC7

6 80 p _5 0 V _ X 7R _0 4
6 8 0 p_ 5 0 V _X 7 R _ 0 4

A U S B _P N 8 _A UD 1
A U S B _P P 8_ A U D 1
ASPD IF O

11/2

8 7 2 13 -1 6 00 G

* 87 1 5 1-2 0 0 7G

AG ND

R

BLACK

AJ _ AUD 1

N C2
N C1

A J_ S P D I F 1

A S P D I F O_ R 2
S P D I F _P I N 6 6
L
1
2 S J -T3 5 1 -S 23

11/3

A _ 5V

A J _ A UD 2
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

R5 52
R6 45
R6 56
R6 57

S P D I F _P I N 5 5
S P D I F _P I N 4 4
3

Re sist or 32 or 33 _0 4
me e t W LK Te st
VT1802P
33_1%_04

2
6
L
1
2 S J -T3 5 1 -S 23

MIC IN

BLACK
A GN D

A HP _S E N S E

A _ A U DG

A SP K _ HP #

A H E A D P HON E -R A R4

2 4 0 _1 % _ 06 A H E A D P HO N E -R -R

A L1

F CM1 0 0 5K F -12 1 T 03

A H E A D P HO N E -R _R

A H E A D P HON E -L A R5

2 4 0 _1 % _ 06 A H E A D P HO N E -L -R

A L2

F CM1 0 0 5K F -12 1 T 03

A H E A D P HO N E -L _ R

5
4
3

R

2
6
L
1
2 S J -T3 5 1 -S 23

A _ A UD G

A H3
AH2
C 5 6 D 5 6 C5 6 D5 6

A J_ H P 1

AR 1

A R2

AC 6

* 1K _ 0 4

*1 K _0 4

6 80 p _5 0 V _ X 7R _0 4
6 8 0 p_ 5 0 V _X 7 R _ 0 4

AC5

HEAD PHONE

BLACK
A _ A U DG

2
3
4
5

AH5

9
8
7
6

1

2
3
4
5

MT H 6_ 0 D2 _ 2
AG ND

B - 44 W150HNM Audio Board

AG ND

A H1
1

9
8
7
6

2
3
4
5

MT H7 _ 0D 2 _8
A GN D

AH 4
1

AC1 0

9
8
7
6

A GN D

A GN D

0. 1 u _ 10 V _ X 5R _ 04

AC1 2

0. 1 u _ 10 V _ X 5R _ 04

H P- L

AC4

0. 1 u _ 10 V _ X 5R _ 04

H P- R

G ND

M T H 7 _0 D 2_ 8
AG ND

0. 1 u _ 10 V _ X 5R _ 04

AC1

A GN D

A _ AUD G

G ND

Schematic Diagrams

W150HNM Second HDD Board
OJ _O D D 1
S1
S2
S3
S4
S5
S6
S7

OJ _SA TA 1
OC 15
OC 16

0. 01u_16V _X7R _04
0. 01u_16V _X7R _04

O _D S AT A_TXP 2
O _D S AT A_TXN 2

O_ H S ATA _TXP 1
O_ H S ATA _TXN 1

OC 17
OC 18

0. 01u_16V _X7R _04
0. 01u_16V _X7R _04

O _D S AT A_R XN 2
O _D S AT A_R XP2

O_ H S ATA _R X N 1
O_ H S ATA _R X P1

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

O _3. 3V S
P1
P2
P3
P4
P5
P6

O GN D
O_S ATA _O D D _P R S N T#

O_H D D _5V S
O_Z ero_OD D _5V S

O_S A TA_ OD D _ D A #

+

OC 10
220u_6. 3V _6. 3*6. 3* 4. 2

F P-> AT1 3035 BAA 089
C 990 326

A T1303 5BA A 089

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

O_D SA TA _TXP 2
O_D SA TA _TXN 2
O_D SA TA _R XN 2
O_D SA TA _R XP 2
O_S A TA _OD D _PR SN T#
O_S ATA _OD D _D A #
O_Z ero_OD D _5V S

88028-3010
OG N D

O GN D

6-2 1-C1D6 0-215

OG N D

W150HNM Zero Power
OJ _H D D 1
S1
S2
S3
S4
S5
S6
S7

Sheet 44 of 49
W150HNM Second
HDD Board

Gen3
O C 11
O C 12

0. 01u_16V _X7R _04
0. 01u_16V _X7R _04

O_H S A TA _TXP1
O_H S A TA _TXN 1

O C 13
O C 14

0. 01u_16V _X7R _04
0. 01u_16V _X7R _04

O_H S A TA _R XN 1
O_H S A TA _R XP 1
O_3. 3V S

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

O C3

OC 5

* 0. 01u_50V _X7R _0 4

* 10u_10V _Y 5V _08
O _H D D _5VS

OGN D

O GN D
OC 1

O C6

OC 8

OC 7

OC 9

OC 4

0. 1u_1 0V_X5 R _04

0. 1u_10V _X5R _04

0. 1u_10V _X5R _04

1u_6. 3V _X5R _04

* 10u_10V _Y 5V _08

+

220u_6. 3V _6. 3*6. 3* 4. 2

C 16664-1220 4-L
P I N G N D 1 ~ 2= G N D
O GN D
O GN D

6-2 1-C270 0-122

2
3
4
5

OH 6
1

9
8
7
6

2
3
4
5

H 6_ 5D 2_3
OG N D

OH 4
1

OH 1
H 6_5 D 3_7

9
8
7
6

OH 2
H 6_5D 3_7

OH 5
C 67D 67

OH 3
C 67D 6 7

H 6_ 5D 2_3
OGN D

OG N D

OGN D

OGN D

OGN D

W150HNM Second HDD Board B - 45

B.Schematic Diagrams

O GN D

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Schematic Diagrams

B5100 Click Board
CSW1~2
2
1

T+ 5 VS
C C1
0 . 1 u_ 1 0V _X 7 R _ 0 4

T + 5V S
F CR 7
*3 2 mi l _ sh o rt

T J _ TP B 1

T GN D

TJ _ T P 1
TG T P _C L K
T GT P _ D A TA

1
2
3
4
5
6

T _3 . 3 V
T C 16
T U S B _P N 1 0
TU S B _ P P 1 0

0 . 1 u _1 6 V _ Y 5 V _ 0 4

1
3

LIFT
KEY

C SW 2
T J G-5 3 3-S -T / R

T GT P _ C L K
T GT P _ D A TA
C TP B U T T ON _ L
C TP B U T T ON _ R

2
4

1
3

C T P B U T T ON _ R

CS W 1
TJ G -53 3 -S -T / R

5
6

1
2
3
4
5
6
7
8
9
10

4
3

RIGHT
KEY

1
3

8 5 20 1 -0 60 5 1

2
4

C TP B U T TO N _ L

5
6

V15XX CLICK BOARD

T 3 . 3V

C SW 4
* TJ G-5 3 3 -S -T / R

2
4

1
3

CS W 3
*T J G-5 33 -S -T / R

2
4

* 32 m i _l s ho rt
T R 1 0 T E S D _G N D

T GN D

T G ND

5
6

T GN D

8 5 2 01 -1 0 05 1

5
6

TG N D

6-20-94A20-110
T GN D

B.Schematic Diagrams

It is st rongly rec ommended that the TESD_ GND h as
a d edica ted conn ec tion to th e s yste m ch as sis or
ca ble shield .

T GN D

Sheet 45 of 49
B5100 Click Board

T 3 .3 V
TU 1
TM OS I
TM I S O
TM C S
TM C L K
T R1 2

*4 . 7 K _ 04

T MI S O

T R1 1

*4 . 7 K _ 04

T MOS I

T R2

4 . 7K _ 0 4

5
2
1
6

1
3
5
7
9
11
13
15
17
19
21
23

T X IN
T X OU T
T M OS I
T M CL K
T M CS
T N RE S E T
T 3 .3 V

T 3. 3 V

2
4
6
8
10
12
14
16
18
20
22
24

8

V DD

3

T 3. 3 V

T C2

W P#

0 . 1u _ 1 6V _ Y 5V _ 0 4

TJ _ F P B 1
T R E G_ OU T
T B D RIV E 1
T B D RIV E 2

S
Q
C S#
SC K

4

7
VS S

TR E F _ OS C

HO L D#

M9 5 12 8 W MN 6 TP
TB E Z E L1
TB E Z E L2

T GN D

TAVD D

T GN D

TG N D

951206
T NRE S E T

TM I S O
TU S B _ C O N N
TP D _ R E G
TU S B _ P N _ R
TU S B _ P P _ R

T R E F _ OS C

TR 4

4 7 K _ 04

TC 4

1 u _ 6. 3 V _ Y 5 V _ 0 4

T C 11

2 7 p _5 0 V _ N P O _0 4

T 3. 3 V

TB E Z E L 1
TU 2
TB D R I V E 1

T R1 3

10 0 _ 1% _ 0 4

1

TB D R I V E 2

T R1 4

10 0 _ 1% _ 0 4

2

3

TB E Z E L 2

R C L A M P 05 0 2 B

T GN D

*C O N 2 4 A
T GN D

T G ND

T C1 3
T E S D_ G ND
T P D_ RE G

Place Botton

T 3 . 3V

TR 9

3 3 0 K _0 4

T C 12

1 u _ 6. 3 V _ Y 5 V _ 0 4

1 8p _ 5 0V _ N P O_ 0 4

T 3. 3 V
T G ND

J_FP1
1

23

TC 5

T C1 4

T C 15
TAVD D

1u _ 6 . 3V _X 5 R _ 0 4
24

2
TOP VIEW

1 u _6 . 3 V _ X5 R _0 4

0 . 1 u _1 6 V _ Y 5 V _ 04
T R E G _O U T

2
24
BOTTON VIEW

T R6

2 . 2_ 1 % _0 6
T U S B _ P N _R

TC 8

TC 7

T R8

2 7 . 4_ 1 % _0 4

T U S B _P N 1 0

T C6

T GN D
1u _ 1 6V _X 5 R _ 0 6

B5100M ONLY

1
6
TJ_FP1

1 u _ 16 V _ X 5R _ 06
0 . 1 u _1 6 V _ Y 5 V _ 04

TC 10
47 p _ 50 V _ N P O _ 04

T GN D

T GN D
T GN D

T XI N

TR 3

4 7 0 _0 4

T U S B _ C ON N

T R5

1 . 5 K _ 1% _ 0 4

T US B _ P P _ R

T R7

2 7 . 4_ 1 % _0 4

TU S B _ P P 1 0

T XI N _ R
TC 9

T R1
1 M_ 0 4

T GN D

2

3
4
TX1
H S X 53 1 S _ 1 2M H Z
TH 1
2
3
4
5

T H3

1

9
8
7
6

2
3
4
5

T H4

1

9
8
7
6

2
3
4
5

TH 2

1

9
8
7
6

2
3
4
5

1

9
8
7
6

T H5
H 3 _ 0D 2 _3

47 p _ 50 V _ N P O _ 04

1

T X OU T

T GN D

MT H 6 _ 0 D 2 _ 3_ S

M TH 6_ 0 D 2 _ 3 _S

TC 1

T C3

T GN D
TG N D

B - 46 B5100 Click Board

T GN D

T GN D

TG N D

1 8 p_ 5 0 V _ N P O_ 0 4

M T H 6 _ 0D 2_ 3 _ S

T GN D
T GN D

T GN D

TH 6
H 3 _ 0D 2_ 3

18 p _5 0 V _ N P O _ 04
M T H 6 _ 0D 2_ 3 _ S

HSX531S+-20pp m

TG N D

T GN D

Schematic Diagrams

B5100 Fingerprint Board

V51XX FINGERPRINT BOARD

FPJ T1

FP U 1
B5

FU S B_C ON N

B11

FB D RI V E1

B10

FB D RI V E2

A5

FB EZE L1

U SB_C ON N EC T
BD R I VE1
BD R I VE2
B7

BEZ EL1A
NC1
NC2
BEZ EL2A

B9

FMOS I
FMC LK
FMC S
FN R E SE T
F3. 3V

FB EZE L2

The path be marked in RED

F 3. 3V

A10
R E G_OU T
A VD D
ES D _GN D 1

A3

F GN D

F3. 3V

FGN D

A4

FP D _R E G

B2

FMC S

C6

FMI SO

B4

FMOSI

B3

FMC LK

B1

FU S B_PN

C1

FU S B_PP

A2

FN R ES ET

PD _R EG

MOSI
MC LK

U S B_D P
N R E SET

C 11

B6
ES D _G N D 4

FJ1
23

23

1

FGN D
FR E F_OSC

2
24
BOTTON VIEW

24
2
TOP VIEW

FGN D

AGN D
XTA LI N

FXI N

C8
F GN D
A6

XTA LOU T

A9

B5100M ONLY
1

C4

A8

DGN D 2

Sheet 46 of 49
B5100 Fingerprint
Board

A11
C9

R E F_OSC

FGN D

FGN D

ES D _GN D 3

DGN D 1

FU SB _PN
FU SB _PP

FGN D

A1

U SB_D N

FMI SO
FU SB _CON N
FPD _R EG

FA VD D

D VD D 1

MI SO

FAV D D

6-21-41710-212

C 10

C3

MC S

FBE ZE L1
FBE ZE L2

FR E G_OU T

ES D _GN D 2

D VD D 2

FR EF _OS C

S PN Z-24S2-VB-017-1-R

needs to be design t o be short and at low im pedance.

C7
BEZ EL2B

NC4

2
4
6
8
10
12
14
16
18
20
22
24

FXOU T

TCS5BF

FGN D

B5100 Fingerprint Board B - 47

B.Schematic Diagrams

NC3
C2

C5

FXI N
FXOU T

The TESD_GND trace has to be w ide ( > 20mil)

A7
BEZ EL1B

B8

1
3
5
7
9
11
13
15
17
19
21
23

FR E G_OUT
FB D R IV E1
FB D R IV E2

Schematic Diagrams

B5100 LED & VGA SW Board

HDD LED

BT LED

BL_3. 3VS

BL_3. 3VS
BLJ_LED 1

BL_3.3VS
BLR1

BL_LED _I GP U#
BL_LED _D GPU#
BL_VGA_SW #
BL_BT_EN
BL_SATA_LE D#
BL_OPTIMU S_MOD E
BL_WLAN_LED#

BLR7

BLR 2
220_04 220_04

Green
C990713

3

B

BL_BT_EN

BLGN D

BL_SATA_LE D#

BL_3. 3VS

S

BLGN D

BL_3.3VS

88486-1001

8 pin ->10 pin add WLAN_LED#
C990713

BL_W LA N_LED #

BLQ1
DTC 114EU A

Sheet 47 of 49
B5100 LED & VGA
SW Board

add WLAN_LED#
C990713

C

2

RY -SP195UH YU Y G4

E

C

HDD/CD-ROM
LED

G

BL_3.3VS

BLR 4

220_04

220_04

BLQ2
AO3409

D

BLR5
BLR 3

220_04
BLR6

C

C

BL_LED _D GPU #

BL_OPTI MU S_MODE

B
BLQ3
DTC114EUA

B5130M ONLY

E

BL_LED _I GPU #

R Y-SP195U HY UY G4

1
3
2
3
4
5

BLH 1
1

9
8
7
6

2
3
4
5

BLH2
1

9
8
7
6

2
3
4
5

BLH3
1

9
8
7
6

BLGN D
BLH 4
H4_4D2_2

BLH 5
H4_4D2_2

BL_SW1
TJ G-533-S-T/ R

5
6

Red

BLD5 Green

4

RY -SP170UH Y24-5M

Green

3

RED

DGPU LED

G
R

BLD 4

RY -SP170UY G24-5M

2

BLD 3

1

A

A

470_04

IGPU LED

C

B.Schematic Diagrams

RY -SP170Y G34-5M

G
R

BLD1
BLD 2

4

A

1

220_04

10
9
8
7
6
5
4
3
2
1

BLGN D
H6_0D2_3
BLGND

H 6_0D2_3
BLGN D

B - 48 B5100 LED & VGA SW Board

BLGN D

H 6_0D 2_3
BLGND

BLGND

BLGN D

DUMMY NET
C990713

2
4

BL_VGA_SW #

Schematic Diagrams

B5100 Power Switch Board

V51XX POWER SWITCH BOARD
BH_3. 3V S

BVD D 3 BH _3.3VS

*BAV99
AC

BPW RBTN #

*BAV99
AC

BWE B#0

AC

P OWER
B UTTON
L ED

BD 3

*BAV99

*BAV99

BW EB#1

BJ_SW1

BR 1
680_06

BVDD 3
BD2

C

BD 1
C

C

BD 4

BVD D 3

AC

BW EB#0

BW EB#2

BW EB#1
BLID _SW#
BW EB#2

A

M100126
BD GN D

C

A

A

A

BD 5
H T-150BP

BD GN D

BD GN D

BDGND

Sheet 48 of 49
B5100 Power
Switch Board

BD GN D
BDGND

Mute

BSW 2
4
3

1
2

4
3

BWEB#1

TJ G-533-S-T/ R
BD GN D

Wl an

BSW 3
1
2

4
3

BW EB#0

TJG-533-S -T/R

PIN5, 6=BDGND

B DGND

CCD

BS W1
1
2

BR2

BDGN D

B5100M ONLY

10K _04

VC C

OUT

0. 1u_16V_Y 5V_04
BD GN D

2

BLID _S W#

MH-248

3

B C7

B VDD 3

BDGN D

9
8
7
6

2
3
4
5

H 6_0D 2_3

BH2
1

9
8
7
6

2
3
4
5

H6_0D 2_3
BDGND

BD GN D

BH3
1

9
8
7
6

BH 4
H 4_4D 2_2

BVDD 3

BVDD 3

BVD D3

BC 6

BC 3

B C5

BC4

*0. 1u_16V_Y 5V_04

*0. 1u_16V_Y 5V_04

*0.01u_50V _X7R _04

*0.01u_50V_X7R _04

BD GN D

B DGND

PIN5,6=BDGND

BDGN D

G ND

1

1

BPW RBTN#

TJG-533-S-T/R

PIN5,6=BDGND

BU1

BH 1

1
2

LID SWITCH IC

BVD D3

2
3
4
5

4
3

BW EB#2

TJ G-533-S-T/ R

PIN5,6=BDG ND

POWER
BOTTOM

BSW 4

BD GN D

BD GN D

BD GND

BH 5
H 4_4D 2_2

H8_0D3_0
B DGND

BD GN D

BD GN D

BD GN D

BD GN D

B5100 Power Switch Board B - 49

B.Schematic Diagrams

1
2
3
4
5
6
7
8
9
10
11
12
87151-1207G

BPW R BTN #

A BH _PI NA

BVDD 3

C

BVD D3

Schematic Diagrams

Sequence
P B 5 0 / P B 7 0

H u r o n

R i v e r

P O W E R

S E Q U E N C E

VCCRTC
36mS
SPEC

MIN

9mS

RTCRST #

DD_ON#
1. 675mS
5V
1. 276mS

3V
RSMRST #

S PEC

MIN

10m S

SUS_PW R_DN_ACK

B.Schematic Diagrams

5mS
SPEC

MAX

MAX

9 0mS
SPEC Minimum
PWR BTN# can

PWRBTN#

SLP_A#

Sheet 49 of 49
Sequence

734mS
200mS

240mS
SPEC

ACPRESE NT

SPEC

SLP_S5 #

S PEC

MIN

MIN

SPEC

SLP_S3 #

neve r

go

high

l ater

than

S LP_S3#

30us

MIN

30uS

2.17mS
SPEC M IN

APWROK

Will

16m S.

5mS

98. 5mS
SPE C MIN

SLP_S4 #

5ms

du ration of P WRBTN# asse rtion =
as sert before or after R SMRST#

1ms

5VS
3.3VS
SPEC
1.8V S(VccPLL)

SPEC

MIN
MIN

0 ms
0ms

1 .85mS
1.5V S
1. 73mS

1.05 VS

1.73m S

1.05 VS_VTT

1.73mS

0.85 VS

1.73m S

H_VT TPWRGD(ALL_ SYS_PWRGD)
IMVP _VR_EN

1.73mS
SPEC

PWRO K

MIN

99mS

UNCO REPWRGOOD

SPEC

MIN

5m S~MAX650ms

DRAM PWROK

SPEC

MIN

2m S~MAX650ms

SPEC
SPEC

MIN

M IN

2mS

0mS

SYS_ PWROK

SPEC

SUS_ STATE#

MIN

1mS

SPEC

PLT_ RST#

SPEC

MIN

MIN

60 uS

1mS~MA X100ms

IMVP _VR_EN
CPU

SVID

BUS

SPEC

MIN

se tVID
SL OW
pa cket

MAX5ms
SPEC

MAX500us

A
C
K
SPEC

MIN50 us~MAX2000u s

SPEC

MAX50 us

VCORE

MVP_ PWRGD

B - 50 Sequence

(VR_R eady)

SPE C

MAX5ms

BIOS Update

Appendix C:Updating the FLASH ROM BIOS
To update the FLASH ROM BIOS you must:
•
•
•
•
•
•
•

Download the BIOS
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel.
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model
(see sidebar for important information on BIOS versions).

Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the
downloaded files.
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software).

BIOS Version
Make sure you download the latest correct
version of the BIOS appropriate for the computer model you are
working on.
You
should
only
download BIOS versions
that
are
V1.01.XX or higher as
appropriate for your
computer model.
Note that BIOS versions
are not backward compatible and therefore
you may not downgrade your BIOS to an
older version after upgrading to a later version (e.g if you upgrade
a BIOS to ver 1.01.05,
you MAY NOT then go
back and flash the BIOS
to ver 1.01.04).

Set the computer to boot from the external drive
1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the “+” and “-” keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
C - 1

C:BIOS Update

Download the BIOS update from the web site.
Unzip the files onto a bootable CD/DVD/USB Flash Drive.
Reboot your computer from an external CD/DVD/USB Flash Drive.
Use the flash tools to update the flash BIOS using the commands indicated below.
Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer.
After rebooting the computer you may restart the computer again and make any required changes to the default BIOS
settings.



BIOS Update

Use the flash tools to update the BIOS
1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:

C:BIOS Update

C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
restarts.

Restart the computer (booting from the HDD)
1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults (or press F9) and select “Yes” to confirm the selection.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.

Your computer is now running normally with the updated BIOS
You may now enter the BIOS and make any changes you require to the default settings.

C-2

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