Compal LA 2411 Schematic. Www.s Manuals.com. R0.3 Schematics
User Manual: Compal LA-2411 - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 66
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
Cover Sheet
165, 07, 2004
星期三 七月
Compal Electronics, Inc.
Schematics Document
Compal confidential
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2004-06-28
DT TRANSPORT or Prescott uFCPGA
with ATI-RC300M+SB200 core logic
LA-2411
REV:0.3
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
Block Diagram
265, 07, 2004
星期三 七月
Compal Electronics, Inc.
page 7
MDC & BT Conn
EC I/O Buffer
page 25
VGA DDR x2 CHB
page 38
page 41
HDD
Connector
page 31
Thermal Sensor
ADM1032AR
page 42
AC-LINK
page 43
LCD Conn
ATI-RC300M
SUPER I/O SMC 207
DC/DC Interface CKT.
page 25
page 45
CABLE CONN.
page 14,15,16
page 47
page 4,5,6
Audio Codec
ATI-M9+X/M10C
page 40
page 26,27,28,29
CDROM
Connector
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)
page 36
BGA 457 pin
page 44
CardBus Controller
868 pin u-BGA
Secondary IDE
ENE910
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
page 41page 34
VGA DDR x2 CHA
IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)
ALC 250
Primary IDE
Touch Pad
Mini PCI
socket
IEEE 1394
TI-TSB43AB22
Compal confidential
AGP BUS
page 30
USB2.0
page 33
page 50,51,52,53,54,55,56,57
page 33
page 43
ATI-SB200
H_A#(3..31)
PCI BUS
RTC CKT.
page 23
RJ45 CONN
LAN
Int.KBD
Power Circuit DC/DC
uFCBGA-479/uFCPGA-478 CPU
H_D#(0..63)
page 22
page 26
ATA-100
page 45
RJ11 CONN
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)
2.5V DDR- 200/266
BIOS
USB conn x4
A-Link
page 37
Power OK CKT.
ATA-100
page 7
PSB
Intel Northwood/Prescott Processor
page 41
page 46
Fan Control
page 42
Mini-PCI solt
LPC BUS
AMP & Audio Jack
RTL 81000CL
page 32
File Name :LA2411
W/EXT VGA CHIP
page 46
800MHz
DDR-SO-DIMM X2
Slot 0
page 17,18,19,20,21
3.3V 33 MHz
page 35
W/EXT VGA CHIP
Power On/Off CKT.
BANK 0, 1, 2, 3
Memory BUS(DDR)
FIR
W/O EXT VGA CHIP
page 8,9,10,11,12,13
CRT & TV-OUT Conn.
ENE 714/1410
VGA M9 Embeded
W/O EXT VGA CHIP
*RJ45 CONN
*LINE IN JACK
*DC JACK
*COM PORT
*USB CONN x1
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT KEY
+TV-OUT PORT
page 30
Card slot
BT
USB1.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
CLOCK GENERATOR
ICS951402AGT
page 24
page 32
page 42
A
A
1 1
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
Notes List
365, 07, 2004
星期三 七月
Compal Electronics, Inc.
External PCI Devices
Voltage Rails
IDSEL # PIRQ
DDR SO-DIMM 0
REQ/GNT #DEVICE
NB Internal VGA
1 0 1 0 0 0 0 XA0
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18 2
N/A
3
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A
A
D
B
C
A
A
A.B
C
D
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.) A2
D2 1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
Power Plane
B+
+1.25VS
Description
VIN
+VCC_CORE Core voltage for CPU
AC or battery power rail for power circuit.
1.25V switched power rail for DDR Vtt
The voltage for Processor VID select
Adapter power supply (19V)
+VCCVID
ON
N/A
N/A
S3
OFF
ON
S5
OFF
N/A
OFF
N/A
N/A
ON
N/A
OFF
OFF OFF
S0-S1
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
OFF
OFF
ON
2.5V switched power rail
+3VS OFF
ON*
+2.5VS
3.3V switched power rail
ONON
2.5V system power rail for DDR
ON*
ON
OFF
+2.5VALW
+2.5V
ON
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
OFF
2.5V always on power rail
+3VALW
ON
ON
OFF
ON
OFF
+1.5VS
3.3V always on power rail
+1.8VS
ON
1.8V switched power rail for ATI-RS300M/RC300M NB.
OFF
OFF
OFF
ON
ON
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
12V always on power rail
+5VS
ON
ON
ON
OFF
ON
ON
ON
+12VALW
5V switched power rail OFF
RTC power
ON*
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
RTCVCC ON
ON*+5VALW 5V always on power rail
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
ON
ON
OFF
+5V 5V system power rail .
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ON ON OFF
M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means build ATI SB USB2.0 related to turn on the function .
NEC@ : means build NEC USB2.0 related to turn on the function .
7
PCB Revision
0.1
Board ID Table for AD channel
Vcc 3.3V +/- 5%
100K +/- 5%Ra
Board ID
Rb V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
Vtyp
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CK_BCLK#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#31
H_A#29
H_A#30
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_IERR#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
CK_BCLK
H_D#[0..63] <8>H_A#[3..31]<8>
H_REQ#[0..4]<8>
H_ADS#<8>
H_BR0#<8>
H_LOCK#<8>
CK_BCLK<24>CK_BCLK#<24>
H_HIT#<8>
H_HITM#<8>
H_DEFER#<8>
H_BOOTSELECT <54>
H_BNR#<8> H_BPRI#<8>
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5VS+5VS
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
Prescott Processor in uFCPGA478
465, 07
星期三 七月
, 2004
Compal Electronics, Inc.
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
Prescott
B6 FERR# FERR#/PBE# Pull-up 62ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name Prescott
Pin name
Commend Commend
AA20 ITPCLKOUT0 Pull-up56ohm
to +VCC_CORE TESTHI6 Pull-up 62ohm
to +VCC_CORE
Pop
Pop
Pop
Pop
Pop
PopDepop
Pop
Pop
Depop
DepopPop
Pop
Northwood
Pop
Depop
Depop
AB22 ITPCLKOUT1 Pull-up 56ohm
to +VCC_CORE TESTHI7 Pull-up 62ohm
to +VCC_CORE
AD2 NC VIDPWRGD Pull-up 2.43K ohm
to +VCCVID
float
AD3 NC float VID5 Pull-up1Kohm to
+3VRUN & connect
to PWRIC
AF3 NC float VCCVIDLB Connect to +VCCVID
Northwood
MT
Northwood MT
Pin name
AD20
VCCA VCCIOPLLConnect to CPU
Filter
FERR#
ITPCLKOUT0
ITPCLKOUT1
Connect to CPU
Filter
AE23
Connect to CPU
Filter Connect to CPU
Filter
NC
NC
NC
VCCA
VSS
VCCIOPLL VCCA
AD1 VSS BOOTSELECT
VCCIOPLL
VSS
Connect to GND CPU determine
AE26 VSS Connect to GND OPTIMIZED/
COMPAT#
Commend
float
Pop
Pop
Pop
TESTHI12 TESTHI12AD25 DPSLP
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to GND
Pop
Pop
float
float
float
Depop
Depop
Depop
Pull-up 62ohm
to +VCC_CORE Pop
Pull-up 200ohm
to +VCC_CORE Connect to PLD
through 0ohm Pop Pop
A6 TESTHI11 GHIPull-up 200ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE Connect to PLD
CPUPREF through
0ohm PopPop Pop
TESTHI11
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R230
51_0402_5%
1 2
R900
100K_0402_5%
12
R1099
47K_0402_5%
12
R1100
47K_0402_5%
12
R899 22K_0402_5%
1 2
Prescott
JP8A
AMP_3-1565030-1_Prescott
A#3
K2
A#4
K4
A#5
L6
A#6
K1
A#7
L3
A#8
M6
A#9
L2
A#10
M3
A#11
M4
A#12
N1
A#13
M1
A#14
N2
A#15
N4
A#16
N5
A#17
T1
A#18
R2
A#19
P3
A#20
P4
A#21
R3
A#22
T2
A#23
U1
A#24
P6
A#25
U3
A#26
T4
A#27
V2
A#28
R6
A#29
W1
A#30
T5
A#31
U4
A#32
V3
A#33
W2
A#34
Y1
A#35
AB1
REQ#0
J1
REQ#1
K5
REQ#2
J4
REQ#3
J3
REQ#4
H3
ADS#
G1
AP#0
AC1
AP#1
V5
BINIT#
AA3
IERR#
AC3
BNR#
G2 BPRI#
D2 BR0#
H6
LOCK#
G4
DEFER#
E2 HITM#
E3 HIT#
F3
D#0 B21
D#1 B22
D#2 A23
D#3 A25
D#4 C21
D#5 D22
D#6 B24
D#7 C23
D#8 C24
D#9 B25
D#10 G22
D#11 H21
D#12 C26
D#13 D23
D#14 J21
D#15 D25
D#16 H22
D#17 E24
D#18 G23
D#19 F23
D#20 F24
D#21 E25
D#22 F26
D#23 D26
D#24 L21
D#25 G26
D#26 H24
D#27 M21
D#28 L22
D#29 J24
D#30 K23
D#31 H25
D#32 M23
D#33 N22
D#34 P21
D#35 M24
D#36 N23
D#37 M26
D#38 N26
D#39 N25
D#40 R21
D#41 P24
D#42 R25
D#43 R24
D#44 T26
D#45 T25
D#46 T22
D#47 T23
D#48 U26
D#49 U24
D#50 U23
D#51 V25
D#52 U21
D#53 V22
D#54 V24
D#55 W26
D#56 Y26
D#57 W25
D#58 Y23
D#59 Y24
D#60 Y21
D#61 AA25
D#62 AA22
D#63 AA24
VCC_0 A10
VCC_1 A12
VCC_2 A14
VCC_3 A16
VCC_4 A18
VCC_5 A20
VCC_6 A8
VCC_7 AA10
VCC_8 AA12
VCC_9 AA14
VCC_10 AA16
VCC_11 AA18
VCC_12 AA8
VCC_13 AB11
VCC_14 AB13
VCC_15 AB15
VCC_16 AB17
VCC_17 AB19
VCC_18 AB7
VCC_19 AB9
VCC_20 AC10
VCC_21 AC12
VCC_22 AC14
VCC_23 AC16
VCC_24 AC18
VCC_25 AC8
VCC_26 AD11
VCC_27 AD13
VCC_28 AD15
VCC_29 AD17
VCC_30 AD19
VCC_31 AD7
VCC_32 AD9
VCC_33 AE10
VCC_34 AE12
VCC_35 AE14
VCC_36 AE16
VCC_37 AE18
VCC_38 AE20
VCC_39 AE6
VCC_40 AE8
VCC_41 AF11
VCC_42 AF13
VCC_43 AF15
VCC_44 AF17
VCC_45 AF19
VCC_46 AF2
VCC_47 AF21
VCC_48 AF5
VCC_49 AF7
VCC_50 AF9
VCC_51 B11
VCC_52 B13
VCC_53 B15
VCC_54 B17
VCC_55 B19
VCC_56 B7
VCC_57 B9
VCC_58 C10
VCC_59 C12
VCC_61 C14
VCC_62 C16
VCC_63 C18
VCC_64 C20
VCC_65 C8
VCC_66 D11
VCC_67 D13
VCC_68 D15
VCC_69 D17
VCC_70 D19
VCC_71 D7
VCC_72 D9
VCC_74
E12 VCC_75
E14 VCC_76
E16 VCC_77
E18 VCC_78
E20 VCC_79
E8 VCC_80
F11
VSS_0
H1
VSS_1
H4
VSS_2
H23
VSS_3
H26
VSS_4
A11
VSS_5
A13
VSS_6
A15
VSS_7
A17
VSS_8
A19
VSS_9
A21
VSS_10
A24
VSS_11
A26
VSS_12
A3
VSS_13
A9
VSS_14
AA1
VSS_15
AA11
VSS_16
AA13
VSS_17
AA15
VSS_18
AA17
VSS_19
AA19
VSS_20
AA23
VSS_21
AA26
VSS_22
AA4
VSS_23
AA7
VSS_24
AA9
VSS_25
AB10
VSS_26
AB12
VSS_27
AB14
VSS_28
AB16
VSS_29
AB18
VSS_30
AB20
VSS_31
AB21
VSS_32
AB24
VSS_33
AB3
VSS_34
AB6
VSS_35
AB8
VSS_36
AC11
VSS_37
AC13
VSS_38
AC15
VSS_39
AC17
VSS_40
AC19
VSS_41
AC2
VSS_42
AC22
VSS_43
AC25
VSS_44
AC5
VSS_45
AC7
VSS_46
AC9
BOOTSELECT
AD1
VSS_47
AD10
VSS_48
AD12
VSS_49
AD14
VSS_50
AD16
VSS_51
AD18
VSS_52
AD21
VSS_53
AD23
VSS_54
AD4
VSS_55
AD8
BCLK0
AF22
BCLK1
AF23
VCC_81
F13
VCC_82
F15
VCC_83
F17
VCC_84
F19
VCC_85
F9
VCC_73 E10
R231 51_0402_5%
1 2
Q106
2SC2411K_SC59
C1
E
3
B
2
Q107
MMBT3904_SOT23
2
3 1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ITP_TMS
ITP_TDI
ITP_TCK
ITP_TDO
H_TESTHI2_7
H_FERR#
H_THERMTRIP#
H_RESET#
H_PROCHOT#
H_PWRGOOD
CK_ITP
CK_ITP#
VID3
VID4
VID5
ITP_TRST#
H_TESTHI9
H_PWRGOOD
H_RS#0
ITP_BPM#3
ITP_TDI
ITP_TCK
H_RS#2
H_RESET#
ITP_BPM#0
H_RS#1
H_PROCHOT#
ITP_BPM#2
VID0
H_THERMTRIP#
ITP_DBRESET#
H_TESTHI0_1
COMP0
ITP_TDO
H_VCCA
ITP_BPM#1
COMP1
H_FERR#
H_TESTHI11
ITP_TRST#
ITP_BPM#5
ITP_BPM#4
H_TESTHI10
H_THERMDC
H_TESTHI8
ITP_TMS
H_THERMDA
H_DPSLP#
VID1
VID2
VID4
VID1
VID2
VID5
VID3
VID0
H_VID_PWRGD
ITP_DBRESET#
H_VSSA
CPU_STP#
CPU_STP#
H_VID_PWRGD
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26> H_FERR#<26> H_IGNNE#<26> H_SMI#<26>
H_PWRGOOD<26> H_STPCLK#<26>
H_INTR<26> H_NMI<26>H_INIT#<26>
H_RESET#<8,26>
H_DBSY#<8> H_DRDY#<8>
H_THERMDA<7> H_THERMDC<7>
H_THERMTRIP#<7>
VCCSENSE<54> VSSSENSE<54>
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_ADSTB#0 <8>
H_ADSTB#1 <8>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_PROCHOT# <49>
H_DINV#3 <8>
H_CPUSLP# <26>
VID4<54>
VID2<54> VID1<54>
VID5<54>
VID0<54>
VID3<54>
VID_PWRGD<53,54>
CK_ITP<24> CK_ITP#<24>
CPU_GHI# <27>
CPUCLK_STP#<11,26,54>
BSEL0<13,24> BSEL1<13,24>
+CPU_GTLREF
+CPU_GTLREF
+VCCVID
+VCC_CORE
+3VS
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+3VS
+3VALW
+VCCVID
+VCCVID
+3VS
+VCC_CORE
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
Prescott Processor in uFCPGA478
565, 07
星期三 七月
, 2004
Compal Electronics, Inc.
Place near SB200 (U6)
Place near CPU
Close to the CPU
3. Place decoupling cap 220PF near CPU.
GTL Reference Voltage
2. Place R_A and R_B near CPU.
Layout note :
R_A
R_B
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
1.Place cap within 600 mils of
the VCCA and VSSA pins.
Note: Please change to 10uH, DC current
of 100mA parts and close to cap
PLL Layout note :
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
Close to the ITP
Between the CPU and ITP
H_TESTHI12
If CPU is P4 , Change the resistor
R546 value to 75_0603_1%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Pop: Northwood
Depop: Prescott
R_E
RE
Pop: Prescott
Depop: Northwood
51.1 Ohm for Northwood,
61.9 Ohm for Prescott
width= 10mil
W/O ITP
R1017->
Pop: Prescott
Depop: Northwood
for mobile CPU
R522 56_0402_5%
1 2
R545
4.7K_0402_5%
R521 56_0402_5%
1 2
R1125
12K_0402_5%
1 2
R559
1K_0402_5%
1 2
R550
1K_0402_5%
12
+
C854
33U_D2_8M_R35
1
2
G
D
S
Q45
2N7002 1N_SOT23
2
13
C546
1U_0603_10V4Z
1
2
RP137 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
L37 LQG21F4R7N00_0805
1 2
Prescott
JP8B
AMP_3-1565030-1_Prescott
RS#0
F1
RS#1
G5
RS#2
F4
RSP#
AB2
TRDY#
J6
A20M#
C6
FERR#
B6
IGNNE#
B2
SMI#
B5
PWRGOOD
AB23
STPCLK#
Y4
TESTHI12 AD25
LINT0
D1
LINT1
E5
INIT#
W5
RESET#
AB25
DRDY#
H2 DBSY#
H5
THERMDC
C4 THERMDA
B3
TDI
C1 TCK
D4
TDO
D5
TMS
F7
TRST#
E6
COMP1
P1 COMP0
L24
DP#0 J26
DP#1 K25
DP#2 K26
DP#3 L25
VSS_57 AE11
VSS_58 AE13
VSS_59 AE15
VSS_60 AE17
VSS_61 AE19
VSS_62 AE22
VSS_63 AE24
OPTIMIZED/COMPAT# AE26
VSS_65 AE7
VSS_66 AE9
VSS_67 AF1
VSS_68 AF10
VSS_69 AF12
VSS_70 AF14
VSS_71 AF16
VSS_72 AF18
VSS_73 AF20
SKTOCC# AF26
VSS_75 AF6
VSS_76 AF8
VSS_77 B10
VSS_78 B12
VSS_79 B14
VSS_80 B16
VSS_81 B18
VSS_82 B20
VSS_83 B23
VSS_84 B26
VSS_85 B4
VSS_86 B8
VSS_87 C11
VSS_88 C13
VSS_89 C15
VSS_90 C17
VSS_91 C19
VSS_92 C2
VSS_93 C22
VSS_94 C25
VSS_95 C5
VSS_96 C7
VSS_97 C9
VSS_98 D10
VSS_99 D12
VSS_100 D14
VSS_101 D16
VSS_102 D18
VSS_103 D20
VSS_104 D21
VSS_105 D24
VSS_106 D3
VSS_107 D6
VSS_108 D8
VSS_109 E1
VSS_110 E11
VSS_111 E13
VSS_112 E15
VSS_113 E17
VSS_114 E19
VSS_115 E23
VSS_116 E26
VSS_117 E4
VSS_118 E7
VSS_119 E9
VSS_120 F10
VSS_121 F12
VSS_122 F14
VSS_123 F16
VSS_124 F18
VSS_125 F2
VSS_126 F22
VSS_127 F25
VSS_128 F5
VID0
AE5
VID1
AE4
VID2
AE3
VID3
AE2
VID4
AE1
GTLREF0 AA21
GTLREF1 AA6
GTLREF2 F20
GTLREF3 F6
NC1 A22
NC2 A7
TESTHI0 AD24
TESTHI1 AA2
TESTHI2 AC21
TESTHI3 AC20
TESTHI4 AC24
TESTHI5 AC23
TESTHI6 AA20
TESTHI7 AB22
TESTHI8 U6
TESTHI9 W4
TESTHI10 Y3
TESTHI11 A6
VSS_129
F8
VSS_130
G21
VSS_131
G24
VSS_132
G3
VSS_133
G6
VSS_134
J2
VSS_135
J22
VSS_136
J25
VSS_137
J5
VSS_138
K21
VSS_139
K24
VSS_140
K3
VSS_141
K6
VSS_142
L1
VSS_143
L23
VSS_144
L26
VSS_145
L4
VSS_146
M2
VSS_147
M22
VSS_148
M25
VSS_149
M5
VSS_150
N21
VSS_151
N24
VSS_152
N3
VSS_153
N6
VSS_154
P2
VSS_155
P22
VSS_156
P25
VSS_157
P5
VSS_158
R1
VSS_159
R23
VSS_160
R26
VSS_161
R4
VSS_162
T21
VSS_163
T24
VSS_164
T3
VSS_165
T6
VSS_166
U2
VSS_167
U22
VSS_168
U25
VSS_169
U5
VSS_170
V1
VSS_171
V23
VSS_172
V26
VSS_173
V4
VSS_174
W21
VSS_175
W24
VSS_176
W3
VSS_177
W6
VSS_178
Y2
VSS_179
Y22
VSS_180
Y25
VSS_181
Y5
BSEL0
AD6
BSEL1
AD5
BPM#0
AC6
BPM#1
AB5
BPM#2
AC4
BPM#3
Y6
BPM#4
AA5
BPM#5
AB4
DSTBN#0 E22
DSTBN#1 K22
DSTBN#2 R22
DSTBN#3 W22
DSTBP#0 F21
DSTBP#1 J23
DSTBP#2 P23
DSTBP#3 W23
ITP_CLK0
AC26
ITP_CLK1
AD26
ADSTB#0 L5
ADSTB#1 R5
DBI#0 E21
DBI#1 G25
DBI#2 P26
DBI#3 V21
DBR# AE25
VCCIOPLL
AD20
VCCSENSE
A5
VCCA
AE23
VCCVID
AF4
THERMTRIP#
A2
PROCHOT# C3
MCERR# V6
SLP# AB26
VSSA
AD22
VSSSENSE
A4
VIDPWRGD
AD2
VID5
AD3
NC5 AE21
NC4 AF24
NC3 AF25
VCCVIDLB
AF3
R547
@54.9_0603_1%
1 2
R530 56_0402_5%
1 2
L36 LQG21F4R7N00_0805
1 2
R529 56_0402_5%
1 2
R542 1K_0402_5%
1 2
R514
@0_0402_5%
1 2
C547
220P_0402_25V8K
1
2
RP136 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
R520 @0_0402_5%
1 2
R527 56_0402_5%
1 2
R518 300_0402_5%
1 2
R552 1K_0402_5%
1 2
RP94 1K_1206_8P4R_5%
18 27 36 45
R519 56_0402_5%
1 2
R543 1K_0402_5%
1 2
+
C544
33U_D2_8M_R35
1
2
R539
61.9_0603_1%
12
R558
169_0402_1%
12
R1017 0_0402_5%
1 2
R546
@54.9_0603_1%
1 2
R556 1K_0402_5%
12
R515 56_0402_5%
1 2
R517 130_0402_5%
1 2
C932
0.1U_0402_10V6K
1
2
R541
680_0603_5%
1 2
Q95
MMBT3904_SOT23
2
3 1
R553
100_0402_1%
12
R513 56_0402_5%
1 2
R993
4.7K_0402_5%
12
R990 300_0402_5%
1 2
Q96
MMBT3904_SOT23
2
3 1
R540
61.9_0603_1%
12
U32A
SN74LVC14APWLE_TSSOP14
O2
I
1
P14
G
7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
CPU Decoupling
665, 07
星期三 七月
, 2004
Compal Electronics, Inc.
Place 11 North of Socket(Stuff 6)
Place 12 Inside Socket(Stuff all)
Place 9 South of Socket(Unstuff all)
Place Inside Socket around the edge
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SANYO OS-CON 820uF H:13*3 (C163,C164,C165)
SANYO OS-CON 820uF H:9*2 (C166,C167)
+
C178
@470U_D2_2.5VM
1
2
C159
22U_1206_16V4Z
1
2
C143
22U_1206_16V4Z
1
2
+
C180
470U_D2_2.5VM
1
2
C162
22U_1206_16V4Z
1
2
C172
0.22U_0603_10V7K
1
2
C132
22U_1206_16V4Z
1
2
C170
0.22U_0603_10V7K
1
2
C139
22U_1206_16V4Z
1
2
C168
0.22U_0603_10V7K
1
2
+
C163
820U_E9_2_5V_M_R7
1
2
+
C183
@470U_D2_2.5VM
1
2
C134
22U_1206_16V4Z
1
2
C154
22U_1206_16V4Z
1
2
C153
22U_1206_16V4Z
1
2
C151
22U_1206_16V4Z
1
2
C145
22U_1206_16V4Z
1
2
C135
22U_1206_16V4Z
1
2
C146
22U_1206_16V4Z
1
2
C173
0.22U_0603_10V7K
1
2
C156
22U_1206_16V4Z
1
2
+
C179
470U_D2_2.5VM
1
2
C141
22U_1206_16V4Z
1
2
C147
22U_1206_16V4Z
1
2
+
C166
820U_E9_2_5V_M_R7
1
2
C152
22U_1206_16V4Z
1
2
C155
22U_1206_16V4Z
1
2
C158
22U_1206_16V4Z
1
2
C138
22U_1206_16V4Z
1
2
C131
22U_1206_16V4Z
1
2
C171
0.22U_0603_10V7K
1
2
+
C176
@470U_D2_2.5VM
1
2
C142
22U_1206_16V4Z
1
2
C136
22U_1206_16V4Z
1
2
+
C164
820U_E9_2_5V_M_R7
1
2
C161
22U_1206_16V4Z
1
2
+
C182
470U_D2_2.5VM
1
2
C157
22U_1206_16V4Z
1
2
C150
22U_1206_16V4Z
1
2
C140
22U_1206_16V4Z
1
2
C149
22U_1206_16V4Z
1
2
C160
22U_1206_16V4Z
1
2
C133
22U_1206_16V4Z
1
2
C148
22U_1206_16V4Z
1
2
+
C174
470U_D2_2.5VM
1
2
+
C177
@470U_D2_2.5VM
1
2
C144
22U_1206_16V4Z
1
2
C137
22U_1206_16V4Z
1
2
+
C175
470U_D2_2.5VM
1
2
+
C165
820U_E9_2_5V_M_R7
1
2
+
C181
470U_D2_2.5VM
1
2
C169
0.22U_0603_10V7K
1
2
+
C167
820U_E9_2_5V_M_R7
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EN_FAN1 EN_FAN2
FAN1 FAN2
H_THERMTRIP#
H_THERMDA
H_THERMDC
H_THERMDA
H_THERMDC
EC_SMC_2 <44>
EC_SMD_2 <44>
H_THERMDA <5>
H_THERMDC <5>
EN_FAN1<44> EN_FAN2<44>
FANSPEED2<44>FANSPEED1<44>
H_THERMTRIP#<5>
MAINPWON <48,49,51>
+3VALW
+VCC_CORE
+5VS
+3VS
+5VS
+3VS
+12VALW
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
CPU Thermal Sensor&FAN CTRL
765, 07
星期三 七月
, 2004
Compal Electronics, Inc.
Thermal Sensor ADM1032AR
Address:1001_100X
W=15mil
FAN CONN.1 FAN CONN. 2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C265
10U_0805_10V4Z
1
2
R916
10K_0402_5%
12
R917 8.2K_0402_5%
1 2
C840
0.1U_0402_10V6K
1
2
R920 10K_0402_5%
1 2
R918 8.2K_0402_5%
1 2
JP11
ACES_85205-0300
1
2
3
C253
2200P_0402_25V7K
1
2
C
B
E
Q90
FMMT619_SOT23
1
2
3
JP10
ACES_85205-0300
1
2
3
U10A
LM358A_SO8
+IN
3
-IN
2OUT 1
P8
G
4
R283
@10K_0402_5%
12
C856
1000P_0402_16V7K
1
2
C855
1000P_0402_16V7K
1
2
C
B
E
Q91
FMMT619_SOT23
1
2
3
D25
1N4148_SOD80
12
C251
0.1U_0402_10V6K
1
2
C907
1000P_0402_16V7K
1
2
Q17
2SC2411K_SC59
C1
E
3
B
2
D68
1SS355_SOD323
12
R913 100_0402_5%
1 2
D67
1SS355_SOD323
12
C838
10U_0805_16V4Z
12
C266
10U_0805_10V4Z
1
2
R286 300_0402_5%
12
C256 @1U_0603_10V6K
12
R919 10K_0402_5%
1 2
C839
10U_0805_16V4Z
1
2
R915
10K_0402_5%
12
D26
1N4148_SOD80
12
U8
ADM1032AR_SOP8
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
R914 100_0402_5%
1 2
C841
0.1U_0402_10V6K
1
2
C908
1000P_0402_16V7K
1
2
U10B
LM358A_SO8
+IN
5
-IN
6OUT 7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#[0..63]
H_REQ#[0..4]
H_A#[3..31]
H_D#62
H_DSTBP#3
H_D#37
H_D#59
H_DINV#2
H_D#39
H_D#54
H_D#11
H_DSTBN#2
H_D#12
H_D#46
H_D#63
H_D#8
H_DSTBP#2
H_D#48
H_D#50
H_DSTBN#0
H_D#19
H_D#47
H_D#0
H_D#6
H_D#13
H_D#5
H_D#9
H_D#18
H_D#4
H_D#28
H_D#57
H_D#40
H_D#36
H_DSTBP#1
H_D#43
H_D#33
H_D#24
H_D#25
H_D#34
H_D#29
H_D#55
H_DSTBN#3
H_DINV#0
H_D#16
H_D#51
H_D#2
H_D#45
H_D#31
H_D#23
H_D#52
H_D#3
H_D#20
H_D#17
H_D#7
H_DINV#3
H_D#22
H_D#15
H_D#30
H_DSTBP#0
H_D#32
H_D#58
H_D#10
H_D#1
H_D#35
H_D#21
H_D#41
H_D#44
H_D#42
H_D#53
H_D#60
H_D#27
H_D#38
H_DSTBN#1
H_D#56
H_D#49
H_D#26
H_D#61
H_DINV#1
H_D#14
H_A#28
H_ADSTB#1
H_A#7
H_A#30
H_A#3
H_A#20
H_A#29
H_A#6
H_A#22
H_A#18
H_A#24
H_REQ#3
H_A#23
H_BNR#
H_A#9
H_A#8
H_A#25
H_A#11
H_DEFER#
H_A#10
H_ADSTB#0
H_A#4
H_DRDY#
H_LOCK#
H_A#17
H_TRDY#
H_A#27
H_A#16
H_A#13
H_HIT#
H_ADS#
H_RS#1
H_RESET#
H_DBSY#
H_A#5
COMP_P
H_A#15
H_A#14
H_A#26
H_A#31
H_HITM#
H_RS#2
H_BPRI#
H_REQ#1
H_A#19
H_REQ#2
NB_GTLREF
H_A#21
H_REQ#4
H_REQ#0
H_RS#0
H_A#12
H_BR0#
COMP_N
CPVSS
CPVDD
H_D#[0..63] <4>
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_DSTBP#0 <5>
H_DSTBN#3 <5>
H_DSTBN#0 <5>
H_DSTBP#3 <5>
H_DSTBP#2 <5>
H_DSTBN#2 <5>
H_DSTBP#1 <5>
H_DSTBN#1 <5>
H_TRDY#<5>
H_RS#1<5>
H_DEFER#<4>
H_HITM#<4> H_HIT#<4>
NB_PWRGD<10,46>
H_ADSTB#1<5>
H_DRDY#<5>
H_ADSTB#0<5>
H_RS#2<5>
H_LOCK#<4>
H_DBSY#<5>
H_BPRI#<4> H_BNR#<4>
H_RS#0<5>
H_RESET#<5,26>
NB_RST#<17,26>
H_ADS#<4>
H_BR0#<4>
H_DINV#3 <5>
H_DINV#0 <5>
H_DINV#2 <5>
H_DINV#1 <5>
NB_SUS_STAT#<27>
+VCC_CORE
+VCC_CORE +1.8VS
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI RC300M-AGTL+
865, 07, 2004
星期三 七月
Compal Electronics, Inc.
C363 CLOSE
TO Ball W28
PLACE CLOSE TO U27 Ball
W28, USE 20/20
WIDTH/SPACE
Note: PLACE CLOSE TO RC300M,
USE 10/10 WIDTH/SPACE
L
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
--> 412_0402_1%
R383
100_0402_1%
1 2
C372
0.1U_0402_10V6K
1
2
R381 24.9_0402_1%
1 2
C366
0.1U_0402_10V6K
1
2
R384
169_0402_1%
12
C368
0.1U_0402_10V6K
1
2
C369
0.1U_0402_10V6K
1
2
C362
1U_0603_10V6K
1
2
L34
HB-1M2012-121JT03_0805
1 2
R382 49.9_0402_1%
1 2
C364
22U_1206_16V4Z_V1
1
2
C371
0.1U_0402_10V6K
1
2
C99610U_0805_10V4Z
1 2
C365
0.1U_0402_10V6K
1
2
R385
4.7K_0402_5%
12
C363
220P_0402_25V8K
1
2
C361
@1U_0603_10V6K
1 2
R380 330_0402_5%
1 2
C370
0.1U_0402_10V6K
1
2
C974
0.1U_0402_10V6K
12
C367
0.1U_0402_10V6K
1
2
PART 1 OF 6
PENTIUM
IV
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
MISC.
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
AGTL+ I/F
U27A
216RC300M_BGA_718
CPU_ADS#
L27
CPU_BNR#
K25
CPU_BPRI#
H26
CPU_D0# L30
CPU_D1# K29
CPU_D2# J29
CPU_D3# H28
CPU_D4# K28
CPU_D5# K30
CPU_D6# H29
CPU_D7# J28
CPU_D8# F28
CPU_D9# H30
CPU_D10# E30
CPU_D11# D29
CPU_D12# G28
CPU_D13# E29
CPU_D14# D30
CPU_D15# F29
CPU_D16# B26
CPU_D17# C30
CPU_D18# A27
CPU_D19# B29
CPU_D20# C28
CPU_D21# C29
CPU_D22# B28
CPU_D23# D28
CPU_D24# D26
CPU_D25# B27
CPU_D26# C26
CPU_D27# E25
CPU_D28# E26
CPU_D29# A26
CPU_D30# B25
CPU_D31# C25
CPU_D32# F24
CPU_D33# D24
CPU_D34# E23
CPU_D35# E24
CPU_D36# F23
CPU_D37# C24
CPU_D38# B24
CPU_D39# A24
CPU_D40# F21
CPU_D41# A23
CPU_D42# B23
CPU_D43# C22
CPU_D44# B22
CPU_D45# C21
CPU_D46# E21
CPU_D47# D22
CPU_D48# B21
CPU_D49# F20
CPU_D50# A21
CPU_D51# C20
CPU_D52# E20
CPU_D53# D20
CPU_A3#
M28
CPU_A4#
P25
CPU_D54# A20
CPU_D55# D19
CPU_D56# C18
CPU_D57# B20
CPU_D58# E18
CPU_D59# B19
CPU_D60# D18
CPU_D61# B18
CPU_D62# C17
CPU_D63# A18
CPU_ADSTB0#
R27
CPU_ADSTB1#
T29
CPU_BR0#
F25 CPU_DBSY#
G27
CPU_DEFER#
J27
CPU_DRDY#
L26
CPU_LOCK#
K26
CPU_TRDY#
F26
CPU_REQ0#
M29
CPU_REQ1#
N25
CPU_REQ2#
R26
CPU_REQ3#
L28
CPU_REQ4#
L29
CPU_HIT#
J26
CPU_HITM#
H25
CPU_RS0#
J25 CPU_RS1#
G26 CPU_RS2#
G25
CPU_DSTBN3# E19
CPU_DSTBN2# E22
CPU_DSTBN1# D27
CPU_DSTBN0# G30
CPU_DSTBP3# F18
CPU_DSTBP2# F22
CPU_DSTBP1# E27
CPU_DSTBP0# G29
CPU_DBI3# F19
CPU_DBI2# D23
CPU_DBI1# A28
CPU_DBI0# E28
CPU_CPURSET#
A17
CPU_COMP_P
W29
CPU_COMP_N
V28
CPVSS
J23
CPU_VREF
W28
THERMALDIODE_N
Y29
THERMALDIODE_P
Y28
TESTMODE
B17
CPVDD
H23
SYSRESET#
AG5
POWERGOOD
C7
CPU_A5#
M25
CPU_A6#
N29
CPU_A7#
N30
CPU_A8#
M26
CPU_A9#
N28
CPU_A10#
P29
CPU_A11#
P26
CPU_A12#
R29
CPU_A13#
P30
CPU_A14#
P28
CPU_A15#
N26
CPU_A16#
N27
CPU_A17#
U30
CPU_A18#
T30
CPU_A19#
R28
CPU_A20#
R25
CPU_A21#
U25
CPU_A22#
T28
CPU_A23#
V29
CPU_A24#
T26
CPU_A25#
U29
CPU_A26#
U26
CPU_A27#
V26
CPU_A28#
T25
CPU_A29#
V25
CPU_A30#
U27
CPU_A31#
U28
SUS_STAT#
AH5 CPU_RSET#
A9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MPVSS
DDRA_DQ44
DDRA_DQ48
DDRA_DQ49
DDRA_DQ54
DDRA_DQ59
DDRA_DM0
DDRA_DM3
DDRA_ADD15
DDRA_CLK3
MEN_COMP
DDRA_DQ3
DDRA_DQ33
DDRA_DQ52
DDRA_ADD4
DDRA_ADD8
DDRA_DM5
DDRA_CLK1
DDRA_DQ18
DDRA_DQ21
DDRA_DQ23
DDRA_ADD10
DDRA_DM6
DDRA_CLK4
DDRA_DQ6
DDRA_DQ13
DDRA_DQ38
DDRA_DQ42
DDRA_DQ43
DDRA_DQ47
DDRA_DQS1
DDRA_DQ57
DDRA_ADD12
DDRA_CLK0
DDRA_CLK1#
DDRA_DQ7
DDRA_DQ15
DDRA_DQ17
DDRA_DQ24
DDRA_DQ25
DDRA_DQ35
DDRA_DQ40
DDRA_DQ41
DDRA_DQ60
DDRA_DQ63
DDRA_ADD6
DDRA_ADD9
DDRA_RAS#
DDRA_CAS#
DDRA_DQS4
MPVDD
DDRA_CLK3#
DDRA_CLK4#
DDRA_DQ9
DDRA_DQ62
DDRA_ADD5
DDRA_DM4
DDRA_DQ4
DDRA_DQ32
DDRA_DQ34
DDRA_DQ53
DDRA_DQ56
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_DQ11
DDRA_DQ14
DDRA_DQ16
DDRA_DQ37
DDRA_DQ55
DDRA_DQS5
DDRA_CLK0#
DDRA_DQ20
DDRA_DQ26
DDRA_DQ27
DDRA_DQ45
DDRA_ADD2
DDRA_ADD7
DDRA_DQ2
DDRA_DQ5
DDRA_DQ51
DDRA_DQ61
DDRA_ADD3
DDRA_ADD13
DDRA_DQS0
DDRA_DQ0
DDRA_DQ1
DDRA_DQ8
DDRA_DQ19
DDRA_DQ12
DDRA_DQ28
DDRA_DQ39
DDRA_DQ46
DDRA_ADD14
DDRA_DM2
DDRA_WE#
DDRA_DQS2
DDRA_DQ30
DDRA_DQ50
DDRA_DQ58
DDRA_ADD1
DDRA_ADD11
DDRA_DM7
DDRA_DQS6
DDRA_DQ10
DDRA_DQ22
DDRA_DQ29
DDRA_DQ36
DDRA_DM1
DDRA_DQS3
DDRA_DQ31
DDRA_ADD0
DDRA_DQS7
DDRA_CKE_R2
DDRA_CKE_R3
DDRA_CS#0
DDRA_CS#1
DDRA_CS#3
DDRA_CS#2
DDR_VREF
DDRA_DQ23
DDRA_SDQ22
DDRA_SDQ23
DDRA_DQ19
DDRA_DQ22 DDRA_SDQ18
DDRA_SDQ19
DDRA_DQ18
DDRA_ADD[0..15]
DDRA_SDQS[0..7]
DDRA_SDQ[0..63]
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ4
DDRA_SDQ5DDRA_DQ5
DDRA_DQ1
DDRA_DQ4
DDRA_DQ0
DDRA_DQ30
DDRA_DQ29
DDRA_DQ25
DDRA_DQS3 DDRA_SDQS3
DDRA_DQ28
DDRA_DQ31
DDRA_SDQ30
DDRA_DQ27
DDRA_SDQ28
DDRA_SDQ31
DDRA_DQ24
DDRA_SDQ29
DDRA_DQ26
DDRA_SDQ24
DDRA_SDQ27
DDRA_SDQ26
DDRA_DM3 DDRA_SDM3
DDRA_SDQ25
DDRA_DM0
DDRA_DQS0 DDRA_SDQS0
DDRA_SDM0
DDRA_DQ9
DDRA_DQ10
DDRA_DQ15
DDRA_DQ11
DDRA_DQ8
DDRA_DQ12
DDRA_DQ14
DDRA_DQ13
DDRA_DM1
DDRA_DQS1
DDRA_SDM1
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ8
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ15
DDRA_SDQ14
DDRA_SDM[0..7]
DDRA_SDM5
DDRA_SDQS6DDRA_DQS6
DDRA_DM7
DDRA_DQ51
DDRA_DQ54
DDRA_SDQS7
DDRA_DQ50
DDRA_SDM7
DDRA_DQS5
DDRA_SDM4
DDRA_DQS7
DDRA_SDQS4
DDRA_SDQ50
DDRA_SDQS5
DDRA_SDQ54
DDRA_DM4
DDRA_SDQ51
DDRA_DQ55
DDRA_DM5
DDRA_SDQ55
DDRA_DQS4
DDRA_SDM6DDRA_DM6
DDRA_DQ49 DDRA_SDQ49
DDRA_SDQ53DDRA_DQ53
DDRA_SDQ48DDRA_DQ48
DDRA_DQ52 DDRA_SDQ52
DDRA_SDQ63DDRA_DQ63
DDRA_DQ59 DDRA_SDQ59
DDRA_SDQ62DDRA_DQ62
DDRA_DQ58 DDRA_SDQ58
DDRA_SDQ61DDRA_DQ61
DDRA_DQ57 DDRA_SDQ57
DDRA_SDQ56DDRA_DQ56
DDRA_DQ60 DDRA_SDQ60
DDRA_SDQ43
DDRA_SDQ47DDRA_DQ47
DDRA_DQ43
DDRA_SDQ46
DDRA_SDQ42
DDRA_DQ46
DDRA_DQ42
DDRA_DQ45
DDRA_DQ41 DDRA_SDQ45
DDRA_SDQ41
DDRA_SDQ40
DDRA_SDQ44DDRA_DQ44
DDRA_DQ40
DDRA_DQ39
DDRA_DQ35 DDRA_SDQ35
DDRA_SDQ39
DDRA_SDQ38
DDRA_SDQ34
DDRA_DQ38
DDRA_DQ34
DDRA_DQ33
DDRA_DQ37 DDRA_SDQ33
DDRA_SDQ37
DDRA_SDQ32
DDRA_SDQ36
DDRA_DQ32
DDRA_DQ36
DDRA_SDQ21
DDRA_SDQ17
DDRA_DQ21
DDRA_DQ17
DDRA_SDQ16
DDRA_SDQ20
DDRA_DQ16
DDRA_DQ20
DDRA_DM2 DDRA_SDM2
DDRA_SDQS2
DDRA_DQ2
DDRA_DQ3
DDRA_DQ6
DDRA_DQ7 DDRA_SDQ3
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ6
DDRA_DQS2
DDRA_CLK0<14>
DDRA_CLK3<15>
DDRA_CLK1#<14>
DDRA_CLK4<15>
DDRA_CLK3#<15>
DDRA_CLK1<14>
DDRA_CLK4#<15>
DDRA_CLK0#<14>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_SDM[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
DDRA_CKE_R0<14,16> DDRA_CKE_R1<14,16> DDRA_CKE_R2<15,16> DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16> DDRA_CS#1<14,16> DDRA_CS#2<15,16> DDRA_CS#3<15,16>
DDRA_RAS#<14,15,16> DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
+2.5V
+1.8VS
+2.5V+2.5V
DDR_VREF
+2.5V
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI RC300M-DDR I/F
965, 07, 2004
星期三 七月
Compal Electronics, Inc.
DDR_VREF trace width of
20mils and space
20mils(min)
L
Group 6 sweep Group 7
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
Layout note
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RP64
0_0404_4P2R_5%
1 4
2 3
C381
0.1U_0402_10V6K
1
2
RP46
0_0404_4P2R_5%
1 4
2 3
R405 49.9_0402_1%
1 2
RP31
0_0404_4P2R_5%
1 4
2 3
RP52
0_0404_4P2R_5%
1 4
2 3
RP61
0_0404_4P2R_5%
1 4
2 3
C376
0.1U_0402_10V6K 1
2
C384
0.1U_0402_10V6K
1
2
C385
0.1U_0402_10V6K
1
2
C374 0.47U_0603_16V7K
1 2
RP63
0_0404_4P2R_5%
1 4
2 3
C860
@0.1U_0402_10V6K
1
2
RP30
0_0404_4P2R_5%
1 4
2 3
RP47
0_0404_4P2R_5%
1 4
2 3
RP36
0_0404_4P2R_5%
1 4
2 3
RP33
0_0404_4P2R_5%
1 4
2 3
C380
0.1U_0402_10V6K
1
2
RP55
0_0404_4P2R_5%
1 4
2 3
C388
0.1U_0402_10V6K
1
2
R412 0_0402_5%
12
RP34
0_0404_4P2R_5%
1 4
2 3
R403 0_0402_5%
12
C386
0.1U_0402_10V6K
1
2
RP48
0_0404_4P2R_5%
1 4
2 3
RP51
0_0404_4P2R_5%
1 4
2 3
C382
0.1U_0402_10V6K
1
2
C859
@0.1U_0402_10V6K
1
2
R413 0_0402_5%
12
RP45
0_0404_4P2R_5%
1 4
2 3
R415 0_0402_5%
12
R395 0_0402_5%
12
RP37
0_0404_4P2R_5%
1 4
2 3
R387 0_0402_5%
12
+
C378
150U_D2_6.3VM
1
2
R404 0_0402_5%
12
R406 0_0402_5%
12
R409
1K_0603_1%
12
R408
1K_0603_1%
12
RP44
0_0404_4P2R_5%
1 4
2 3
R416 0_0402_5%
12
R394 0_0402_5%
12
R398 0_0402_5%
12
C858
@0.1U_0402_10V6K
1
2
C383
0.1U_0402_10V6K
1
2
RP62
0_0404_4P2R_5%
1 4
2 3
RP58
0_0404_4P2R_5%
1 4
2 3
RP54
0_0404_4P2R_5%
1 4
2 3
RP59
0_0404_4P2R_5%
1 4
2 3
RP40
0_0404_4P2R_5%
1 4
2 3
R389 0_0402_5%
12
RP43
0_0404_4P2R_5%
1 4
2 3
R386 0_0402_5%
12
MEM I/F
PART 2 OF 6
U27B
216RC300M_BGA_718
MEM_DQ0 AG6
MEM_DQ1 AJ7
MEM_DQ2 AJ9
MEM_DQ3 AJ10
MEM_DQ4 AJ6
MEM_DQ5 AH6
MEM_DQ6 AH8
MEM_DQ7 AH9
MEM_DQ8 AE7
MEM_DQ9 AE8
MEM_DQ10 AE12
MEM_DQ11 AF12
MEM_DQ12 AF7
MEM_DQ13 AF8
MEM_DQ14 AE11
MEM_DQ15 AF11
MEM_DQ16 AJ12
MEM_DQ17 AH12
MEM_DQ18 AH14
MEM_DQ19 AH15
MEM_DQ20 AH11
MEM_DQ21 AJ13
MEM_DQ22 AJ15
MEM_DQ23 AJ16
MEM_DQ24 AF18
MEM_DQ25 AG20
MEM_DQ26 AG21
MEM_DQ27 AF22
MEM_DQ28 AF19
MEM_DQ29 AF20
MEM_DQ30 AE22
MEM_DQ31 AF23
MEM_DQ32 AJ21
MEM_DQ33 AJ22
MEM_DQ34 AJ24
MEM_DQ35 AK25
MEM_DQ36 AH21
MEM_DQ37 AH22
MEM_DQ38 AH24
MEM_DQ39 AJ25
MEM_DQ40 AK26
MEM_DQ41 AK27
MEM_DQ42 AJ28
MEM_DQ43 AH29
MEM_DQ44 AH25
MEM_DQ45 AJ26
MEM_DQ46 AJ29
MEM_DQ47 AH30
MEM_DQ48 AF29
MEM_DQ49 AE29
MEM_DQ50 AB28
MEM_DQ51 AA28
MEM_DQ52 AE28
MEM_DQ53 AD28
MEM_DQ54 AC29
MEM_DQ55 AB29
MEM_DQ56 AC26
MEM_DQ57 AB25
MEM_DQ58 Y26
MEM_DQ59 W26
MEM_DQ60 AE26
MEM_DQ61 AD26
MEM_DQ62 AA26
MEM_DQ63 Y27
MEM_DDRVREF AK20
MEM_A0
AH19
MEM_A1
AJ17
MEM_A2
AK17
MEM_A3
AH16
MEM_A4
AK16
MEM_A5
AF17
MEM_A6
AE18
MEM_A7
AF16
MEM_A8
AE17
MEM_A9
AE16
MEM_A10
AJ20
MEM_A11
AG15
MEM_A12
AF15
MEM_A13
AE23
MEM_A14
AH20
MEM_DM0
AH7
MEM_DM1
AF10
MEM_DM2
AJ14
MEM_DM3
AF21
MEM_DM4
AH23
MEM_DM5
AK28
MEM_DM6
AD29
MEM_DM7
AB26
MEM_RAS#
AF24
MEM_CAS#
AF25
MEM_WE#
AE24
MEM_CKE0
AF13
MEM_DQS0
AJ8
MEM_DQS1
AF9
MEM_DQS2
AH13
MEM_DQS3
AE21
MEM_DQS4
AJ23
MEM_DQS5
AJ27
MEM_DQS6
AC28
MEM_DQS7
AA25
MEM_CK0#
AH10 MEM_CK0
AK10
MEM_CS#0
AH26
MEM_CS#1
AH27
MEM_CS#2
AF26
MEM_CS#3
AG27
MPVDD
AC18
MPVSS
AD18
MEM_A15
AE25
MEM_CKE1
AE13
MEM_CK1
AH18
MEM_CK1#
AJ19
MEM_CK2
AG30
MEM_CK2#
AG29
MEM_CK3
AK11
MEM_CK3#
AJ11
MEM_CK4
AH17
MEM_CK4#
AJ18
MEM_CK5
AF28
MEM_CK5#
AG28
MEM_CKE2
AG14
MEM_CKE3
AF14
MEM_CAP1 AF6
MEM_CAP2 AA29
MEM_COMP AK19
RP41
0_0404_4P2R_5%
1 4
2 3
RP49
0_0404_4P2R_5%
1 4
2 3
RP57
0_0404_4P2R_5%
1 4
2 3
L35
HB-1M2012-121JT03_0805
1 2
C391
0.1U_0402_10V6K
1
2
RP28
0_0404_4P2R_5%
1 4
2 3
RP50
0_0404_4P2R_5%
1 4
2 3
R388 0_0402_5%
12
C387
0.1U_0402_10V6K
1
2
RP56
0_0404_4P2R_5%
1 4
2 3
C375
2.2U_0805_10V4Z
1 2
C379
0.1U_0402_10V6K
1
2
C857
0.1U_0402_10V6K
1
2
C373 0.47U_0603_16V7K
1 2
R407 0_0402_5%
12
RP27
0_0404_4P2R_5%
1 4
2 3
R397 0_0402_5%
12
RP60
0_0404_4P2R_5%
1 4
2 3
C390
0.1U_0402_10V6K
1
2
C389
0.1U_0402_10V6K
1
2
C861
@0.1U_0402_10V6K
1
2
RP53
0_0404_4P2R_5%
1 4
2 3
C377
0.1U_0402_10V6K 1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
AGP_AD2
AGP_SBA2
AGP_WBF#
AGP_AD27
AGP_AD18
AGP_AD4
AGP_SBSTB#
AGP_AD13
AGP_PAR
AGP_SBA6
AGP_SBA1
AGP_AD25
AGP_AD20
AGP_AD7
AGP_AD6
AGP_ST2
AGP_AD28
AGP_CBE#3
AGP_AD31
AGP_AD14
AGP_AD3
AGP_DBI_LO
AGP_RBF#
AGP_SBA4
AGP_AD12
AGP_AD1
AGP_DEVSEL#
AGP_ADSTB1
AGP_SBSTB
AGP_AD26
AGP_AD10
AGP_ST0
AGP_ADSTB1#
AGP_AD29
AGP_AD22
AGP_DBI_HI/PIPE#
AGP_STOP#
AGP_ADSTB0
AGP_AD19
AGP_AD9
AGP_ST1
AGP_SBA7
AGP_CBE#0
AGP_AD23
AGP_AD8
AGP_AD16
AGP_AD11
AGP_SBA5
AGP_SBA3
AGP_FRAME#
AGP_CBE#2
AGP_ADSTB0#
AGP_AD5
AGP_AD0
AGP_IRDY#
AGP_CBE#1
AGP_AD21
AGP_AD17
AGP_SBA0
AGP_TRDY#
AGP_AD30
AGP_AD24
AGP_AD15
A_AD11
A_AD17
A_AD20
A_END#
A_AD27
A_AD6
A_DEVSEL#
A_AD26
A_AD24
A_AD25
A_AD18
A_AD9
A_AD0
A_AD3
A_AD7
A_AD5
A_ACAT#
A_AD12
A_AD15
A_SBGNT#
A_AD1
A_AD13
A_AD16
A_AD30
A_AD22
A_AD29
AGP_GNT#
A_CBE#3
A_OFF#
A_AD31
A_AD8
A_SBREQ#
A_CBE#0
A_CBE#1
A_CBE#2
A_AD23
A_AD14
A_PAR
A_AD19
A_AD4
A_AD28
A_AD2
A_STROBE#
A_AD10
AGP_REQ#
A_AD21
AGP_SBA2
AGP_SBA3
ENBKL#
AGP_SBA4
AGP_SBA5
AGPREF_8X
AGP_COMP
AGP8X_DET#
DDC_DAT
DDC_CLK
AGP8X_DET#
AGPREF_8X
AGP_ST[0..2]
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_SBA1
AGP_SBA0
ENBKL#
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
AGP_RBF# <17>
AGP_WBF# <17>
AGP_TRDY# <17>
AGP_IRDY# <17>
AGP_FRAME# <17>
AGP_ADSTB1# <17>
AGP_ADSTB0# <17>
AGP_STOP# <17>
AGP_SBSTB# <17>
AGP_SBSTB <17>
AGP_PAR <17>
AGP_ADSTB1 <17>
AGP_ADSTB0 <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_DEVSEL# <17>
AGP_GNT#<17> AGP_REQ#<17>
VREF_8X_IN<17>
A_DEVSEL#<26>
A_SBGNT#<26>
A_OFF#<26>
A_END#<26>
A_SBREQ#<26>
A_ACAT#<26>
A_PAR<13,26>
A_STROBE#<26>
ENAVDD <17,25>
AGP_BUSY# <17,27>
AGP_STP# <17,27>
DDC_DAT <17,25>
DDC_CLK <17,25>
PCI_PIRQA#<17,26,31,34>
AGP8X_DET#<17>
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_ST[0..2] <17>
AGP_CBE#[0..3] <17>
ENBKL <17,44>
NB_PWRGD<8,46>
+1.5VS +3VS
+3VS
+3VS
+1.5VS
+1.5VS
+1.5VS+1.5VS
+1.5VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI RC300M-AGP, ALINK BUS
10 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
AGPAND LVDS MUXED SIGNALS
?
PLACE CLOSE TO
CONNECTOR
8X(M9+M10@)
Ra
169_0402_1%
324_0402_1%
100_0402_1%
4X(NAGP@)
Rb
Rc
Ra
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ATI request
1K_0402_1%
1K_0402_1%
Rb
Rc
Note: PLACE CLOSE TO U27 (NB RC300M)
L
Pop for internal AGP
Depop for M11P
Pop for internal AGP
Depop for M11P
Depop
C553
0.1U_0402_10V6K
1
2
C550
0.1U_0402_10V6K
1 2
R945
NAGP@47K_0402
1 2
G
D
S
Q1
NAGP@2N7002_SOT23
2
13
C557
0.1U_0402_10V6K
1
2
C573
0.1U_0402_10V6K
1
2
C943
0.1U_0402_10V6K
1
2
R560 NAPG@0_0402_5%
1 2
C556
0.1U_0402_10V6K
1
2
C935
0.01U_0402_16V7Z
1
2
C570
0.1U_0402_10V6K
1
2
C567
0.1U_0402_10V6K
1
2
C864
0.01U_0402_16V7Z
1
2
C572
0.1U_0402_10V6K
1
2
C560
0.1U_0402_10V6K
1
2
C951
0.01U_0402_16V7Z
1
2
R568
NAPG@10K_0402_5%
1 2
C938
0.1U_0402_10V6K
1
2
C950
0.01U_0402_16V7Z
1
2
C942
0.1U_0402_10V6K
1
2
C948
0.01U_0402_16V7Z
1
2
C574
0.1U_0402_10V6K
1
2
R576
324_0402_1%
1 2
C554
0.1U_0402_10V6K
1
2
R563 NAPG@0_0402_5%
1 2
C934
0.01U_0402_16V7Z
1
2
C578
0.1U_0402_10V6K
1
2
C947
0.01U_0402_16V7Z
1
2
C555
0.1U_0402_10V6K
1
2
R577
100_0402_1%
1 2
C939
0.1U_0402_10V6K
1
2
C945
0.1U_0402_10V6K
1
2
C568
0.1U_0402_10V6K
1
2
+
C551
47U_B_6.3VM
1
2
G
D
S
Q2
NAGP@2N7002_SOT23
2
13
C936
0.01U_0402_16V7Z
1
2
C562
0.1U_0402_10V6K
1
2
C940
0.1U_0402_10V6K
1
2
C946
0.1U_0402_10V6K
1
2
C577
0.1U_0402_10V6K
1
2
C569
0.1U_0402_10V6K
1
2
R570
8.2K_0402_5%
1 2
R569
NAGP@0_0402_5%
1 2
C563
0.1U_0402_10V6K
1
2
C561
0.1U_0402_10V6K
1
2
C564
0.1U_0402_10V6K
1
2
C566
0.1U_0402_10V6K
1
2
C576
0.1U_0402_10V6K
1
2
C571
0.1U_0402_10V6K
1
2
C559
0.1U_0402_10V6K
1
2
C632
10U_0805_10V4Z
1
2
C941
0.1U_0402_10V6K
1
2
C575
0.1U_0402_10V6K
1
2
R561 NAPG@0_0402_5%
1 2
R562 NAPG@0_0402_5%
1 2
R567
NAGP@10K_0402_5%
1 2
C933
0.01U_0402_16V7Z
1
2
C949
0.01U_0402_16V7Z
1
2
R994 NAPG@0_0402_5%
1 2
C558
0.1U_0402_10V6K
1
2
+
C552
47U_B_6.3VM
1
2
C944
0.1U_0402_10V6K
1
2
R575
169_0402_1%
1 2
R1005 0_0402_5%
1 2
C565
0.1U_0402_10V6K
1
2
C937
0.1U_0402_10V6K
1
2
PART 3 OF 6
PCI Bus 0 / A-Link I/F
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
U27C
216RC300M_BGA_718
ALINK_AD0
AK5
ALINK_AD1
AJ5
ALINK_AD2
AJ4
ALINK_AD3
AH4
ALINK_AD4
AJ3
ALINK_AD5
AJ2
ALINK_AD6
AH2
ALINK_AD7
AH1
ALINK_AD8
AG2
ALINK_AD9
AG1
ALINK_AD10
AG3
ALINK_AD11
AF3
ALINK_AD12
AF1
ALINK_AD13
AF2
ALINK_AD14
AF4
ALINK_AD15
AE3
ALINK_AD16
AE4
ALINK_AD17
AE5
ALINK_AD18
AE6
ALINK_AD19
AC2
ALINK_AD20
AC4
ALINK_AD21
AB3
ALINK_AD22
AB2
ALINK_AD23
AB5
ALINK_AD24
AB6
ALINK_AD25
AA2
ALINK_AD26
AA4
ALINK_AD27
AA5
ALINK_AD28
AA6
ALINK_AD29
Y3
ALINK_AD30
Y5
ALINK_AD31
Y6
ALINK_CBE#0
AG4
ALINK_CBE#1
AE2
ALINK_CBE#2
AC3
ALINK_CBE#3
AA3
PCI_PAR/ALINK_NC
AD5
PCI_FRAME#/ALINK_STROBE#
AC6
PCI_IRDY#/ALINK_ACAT#
AC5
PCI_TRDY#/ALINK_END#
AD2
INTA#
W4
ALINK_DEVSEL#
AD3
PCI_STOP#/ALINK_OFF#
AD6
ALINK_SBREQ#
W5
ALINK_SBGNT#
W6
PCI_REQ#0/ALINK_NC
V5
PCI_GNT#0/ALINK_NC
V6
AGP_AD0/TMD2_HSYNC Y2
AGP_AD1/TMD2_VSYNC W3
AGP_AD2/TMD2_D1 W2
AGP_AD3/TMD2_D0 V3
AGP_AD4/TMD2_D3 V2
AGP_AD5/TMD2_D2 V1
AGP_AD6/TMD2_D5 U1
AGP_AD7/TMD2_D4 U3
AGP_AD8/TMD2_D6 T2
AGP_AD9/TMD2_D9 R2
AGP_AD10/TMD2_D8 P3
AGP_AD11/TMD2_D11 P2
AGP_AD12/TMD2_D10 N3
AGP_AD13 N2
AGP_AD14 M3
AGP_AD15 M2
AGP_AD16/TMD1_VSYNC L1
AGP_AD17/TMD1_HSYNC L2
AGP_AD18/TMD1_DE K3
AGP_AD19/TMD1_D0 K2
AGP_AD20/TMD1_D1 J3
AGP_AD21/TMD1_D2 J2
AGP_AD22/TMD1_D3 J1
AGP_AD23/TMD1_D4 H3
AGP_AD24/TMD1_D7 F3
AGP_AD25/TMD1_D6 G2
AGP_AD26/TMD1_D9 F2
AGP_AD27/TMD1_D8 F1
AGP_AD28/TMD1_D11 E2
AGP_AD29/TMD1_D10 E1
AGP_AD30/TMDS_HPD D2
AGP_AD31 D1
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON E5
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL E6
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK# T3
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK U2
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK# G3
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK H2
AGP2_CBE#0/AGP3_CBE0/TMD2_D7 R3
AGP2_CBE#1/AGP3_CBE1/TMD2_DE M1
AGP2_CBE#2/AGP3_CBE2 L3
AGP2_CBE#3/AGP3_CBE3/TMD1_D5 H1
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA R5
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA P6
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK P5
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK R6
AGP2_WBF#/AGP3_WBF N5
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0 C3
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1 C2
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON E4
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY# F5
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT G6
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN G5
AGP_ST0 L6
AGP_ST1 M6
AGP_ST2 L5
AGP8X_DET#
M5
AGP_VREF/TMDS_VREF
J6
AGP2_REQ#/AGP3_REQ
K6 AGP2_GNT#/AGP3_GNT
K5
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON# D4
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP# F6
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA T6
AGP_PAR T5
AGP2_RBF#/AGP3_RBF N6
AGP2_PIPE#/AGP3_DBI_HI C1
AGP2_NC/AGP3_DBI_LO D3
AGP_COMP
J5
R995 NAPG@0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RC300M_X2
RC300M_X1
CLK_AGP_66M
CLK_MEM_66M
CLK_AGP_66M
+1.8VS_LPVDD
+1.8VS_LVDDR
CRMA_R
COMPS_R
LUMA_R
HSYNC_R
GREEN_R
RED_R
BLUE_R
VSYNC_R
NB_RSET
CLK_NB_BCLK#
CLK_NB_BCLK
RC300M_X2
3VDDCCL
DDCDATA_R
DDCCLK_R
CRMA_R
3VDDCDA
DDCDATA_R
DDCCLK_R
CLK_MEM_66M
GREEN_RCRT_G
VSYNC_R
CRT_B BLUE_R
CRT_HSYNC
CRT_R
HSYNC_R
RED_R
CRT_VSYNC
RC300M_X1
TV_CRMA
LUMA_R TV_LUMA
TV_COMPSCOMPS_R
PLLVDD_18
+1.8VS_AVDDQ
+1.8VS_AVDDDI
CPUCLK_STP#
CLK_AGP_66M<24>
TXACLK-_NB <25>
TXA0+_NB <25>
TXB0+_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXB2-_NB <25>
TXA1-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXB1+_NB <25>
TXB1-_NB <25>
TXA2-_NB <25>
TXACLK+_NB <25>
TXA2+_NB <25>
CLK_NB_BCLK#<24> CLK_NB_BCLK<24>
3VDDCCL <17,25>
TV_LUMA <17,46>
TV_COMPS <17,46>
TV_CRMA <17,46>
3VDDCDA <17,25>
CLK_MEM_66M<24>
CRT_HSYNC<17,25> CRT_VSYNC<17,25>
CRT_B<17,25>
CRT_R<17,25> CRT_G<17,25>
REFCLK1_NB<24>
TXB0-_NB <25>
TXA1+_NB <25>
PCI_RST# <26,30,31,33,34,38,41,44>
CPUCLK_STP# <5,26,54>
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI RC300M-VIDEO I/F
11 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Note: PLACE CLOSE TO U27 (NB CHIP)
L
Note: PLACE CLOSE TO U6 (VGA CHIP)
L
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
L
Note: PLACE CLOSE TO U27 (NB CHIP)
R595 NAPG@0_0402_5%
1 2
C600
10U_0805_16V4Z
1
2
R590 1K_0402_5%
R599 NAPG@0_0402_5%
1 2
C601
@15P_0402_50V8J
L58
FBM-11-160808-121-T_0603
1 2
C594
0.1U_0402_10V6K
1
2
L63
KC FBM-L11-201209-221LMAT_0805
1 2
R587
56_0402_5%
12
R596 NAPG@0_0402_5%
1 2
RP104
NAGP@0_4P2R_0402_5%
14 23
L59
KC FBM-L11-201209-221LMAT_0805
12
L61
KC FBM-L11-201209-221LMAT_0805
1 2
C587
0.1U_0402_10V6K
1
2
L62
KC FBM-L11-201209-221LMAT_0805
1 2
R592 10K_0402_5%
R597 NAPG@0_0402_5%
1 2
C605
@18P_0402_50V8K
C588
0.1U_0402_10V6K
1
2
Y4
@14.31818MHZ_20P_6X1430004201
12
R593
@1M_0402_1%
12
L60
KC FBM-L11-201209-221LMAT_0805
1 2
R589 @0_0402_5%
C598
0.1U_0402_10V6K
1
2
R591
@10_0402_5%
12
C592
0.1U_0402_10V6K
1
2
G
D
S
Q97
@2N7002 1N_SOT23
2
1 3
L64
KC FBM-L11-201209-221LMAT_0805
1 2
PART 4 OF 6
CRT
CLK. GEN.
SVID LVDS
U27D
216RC300M_BGA_718
TXOUT_U0N D12
TXOUT_U0P E12
TXOUT_U1N F11
TXOUT_U1P F12
TXOUT_U2N D13
TXOUT_U2P D14
TXCLK_UN E13
TXCLK_UP F13
TXOUT_L0N E10
TXOUT_L0P D10
TXOUT_L1N B9
TXOUT_L1P C9
TXOUT_L2N D11
TXOUT_L2P E11
TXCLK_LN B10
TXCLK_LP C10
LVDDR_18 B12
LPVSS A11
LVDDR_18 C12
LPVDD_18 A12
LVSSR B11
LVSSR C11
C_R E15
Y_G C15
COMP_B D15
DACSCL D6
DACSDA C6
CPUSTOP# D5
RED
F14
GREEN
F15
BLUE
E14
DACHSYNC
C8
DACVSYNC
D9
RSET
C14
VDDR3
H9
AVDDQ
A15
AVSSN
B13
AVDD_25
A14
AVDDDI_18
B14
AVSSDI
C13
AVSSQ
B15
PLLVDD_18
H11
PLLVSS
G11
VDDR3
G9
XTALIN
A4
XTALOUT
B4
EXT_MEM_CLK
A3
SYSCLK A8
SYSCLK# B8
AGPCLKIN
B3
HCLKIN#
B5
ALINK_CLK
D8
AGPCLKOUT
B2
USBCLK
D7
REF27
B7
SYS_FBCLKOUT
B6
OSC
C5
SYS_FBCLKOUT#
A6
HCLKIN
A5
C596
10U_0805_16V4Z
1
2
R594 NAPG@0_0402_5%
1 2
R584 715 _0402_1%
1 2
R598 NAPG@0_0402_5%
1 2
C590
0.1U_0402_10V6K
1
2
C591
10U_0805_16V4Z
1
2
C589
0.1U_0402_10V6K
1
2
C603
@15P_0402_50V8J
C586
0.1U_0402_10V6K
1
2
R588
@10_0402_5%
12
RP103
NAGP@0_4P2R_0402_5%
1 4
2 3
C599
0.1U_0402_10V6K
1
2
C593
0.1U_0402_10V6K
1
2
C604
@18P_0402_50V8K
R585 0_0402_5%
1 2
C595
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5VS +2.5V
+VCC_CORE
+3VS
+3VS
+1.5VS
+1.8VS
+1.5VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI RC300M-POWER
12 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Pop for M11P
Depop for internal AGP
Pop for internal AGP
Depop for M11P
C583
0.1U_0402_10V6K
1
2
C582
0.1U_0402_10V6K
1
2
C579
10U_0805_10V4Z
1
2
C580
0.1U_0402_10V6K
1
2
R418 M9-M10@0_0603_5%
1 2
C581
0.1U_0402_10V6K
1
2
PART 6 OF 6
GND
U27F
216RC300M_BGA_718
VSS
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7 VSS J8
VSS K27
VSS K4
VSS L23
VSS L24
VSS L25
VSS L7
VSS L8
VSS M15
VSS M16
VSS M27
VSS M4
VSS N15
VSS N16
VSS N23
VSS N24
VSS N8
VSS P15
VSS P16
VSS P27
VSS P4
VSS R1
VSS R12
VSS R13
VSS R14
VSS R15
VSS R16
VSS R17
VSS R18
VSS R19
VSS R23
VSS R7
VSS R8
VSS T12
VSS T13
VSS T14
VSS T15
VSS T16
VSS T17
VSS T18
VSS T19
VSS T27
VSS T4
VSS U15
VSS U16
VSS U7
VSS U8
VSS V15
VSS V16
VSS V27
VSS V4
VSS V7
VSS V8
VSS W15
VSS W16
VSS W27
VSS Y1
VSS Y23
VSS Y24
VSS Y30
VSS Y4
VSS Y7
VSS Y8
R419 NAGP@0_0603_5%
1 2
PART 5 OF 6
POWER
CORE PWR
AGP PWR
MEM I/F PWR
CPU I/F PWRALINK PWR
U27E
216RC300M_BGA_718
VDD_CORE
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_18 H22
VDD_18 H10
VDD_18 AC9
VDD_18 AC22
VDDP_AGP/VDDP33 G8
VDDP_AGP/VDDP33 F7
VDDP_AGP/VDDP33 E7
VDDP_AGP T8
VDDP_AGP R4
VDDP_AGP P8
VDDP_AGP P7
VDDP_AGP P1
VDDP_AGP N4
VDDP_AGP M8
VDDP_AGP M7
VDDP_AGP L4
VDDP_AGP K8
VDDP_AGP J4
VDDP_AGP H7
VDDP_AGP H6
VDDP_AGP H5
VDDP_AGP G4
VDDP_AGP A2
VDDR_MEM AA23
VDDR_MEM AA27
VDDR_MEM AB30
VDDR_MEM AC10
VDDR_MEM AC12
VDDR_MEM AC13
VDDR_MEM AC15
VDDR_MEM AC17
VDDR_MEM AC19
VDDR_MEM AC21
VDDR_MEM AC23
VDDR_MEM AC24
VDDR_MEM AC25
VDDR_MEM AC27
VDDR_MEM AD10
VDDR_MEM AD12
VDDR_MEM AD13
VDDR_MEM AD15
VDDR_MEM AD17
VDDR_MEM AD19
VDDR_MEM AD21
VDDR_MEM AD23
VDDR_MEM AD24
VDDR_MEM AD25
VDDR_MEM AD27
VDDR_MEM AE10
VDDR_MEM AE14
VDDR_MEM AE15
VDDR_MEM AE19
VDDR_MEM AE20
VDDR_MEM AE30
VDDR_MEM AE9
VDDR_MEM AF27
VDDR_MEM AG11
VDDR_MEM AG12
VDDL_ALINK
W8 VDDL_ALINK
AK3 VDDL_ALINK
AD8 VDDL_ALINK
AD7 VDDL_ALINK
AD1 VDDL_ALINK
AC8 VDDL_ALINK
AC7 VDDL_ALINK
AA8 VDDL_ALINK
AA7 VDDL_ALINK
AA1
VDDR2_CPU
W30 VDDR2_CPU
U24 VDDR2_CPU
U23 VDDR2_CPU
T24 VDDR2_CPU
T23 VDDR2_CPU
P24 VDDR2_CPU
P23 VDDR2_CPU
M23 VDDR2_CPU
K24 VDDR2_CPU
K23 VDDR2_CPU
H24 VDDR2_CPU
H21 VDDR2_CPU
H19 VDDR2_CPU
H17 VDDR2_CPU
H16 VDDR2_CPU
G24 VDDR2_CPU
G23 VDDR2_CPU
G21 VDDR2_CPU
G17 VDDR2_CPU
F17 VDDR2_CPU
F16 VDDR2_CPU
E17 VDDR2_CPU
E16 VDDR2_CPU
D17 VDDR2_CPU
D16 VDDR2_CPU
C16
VDDR_MEM AG17
VDDR_MEM AG18
VDDR_MEM AG23
VDDR_MEM AG24
VDDR_MEM AG26
VDDR_MEM AG8
VDDR_MEM AG9
VDDR_MEM AJ30
VDDR_MEM AK14
VDDR_MEM AK23
VDDR_MEM AK8
VDDR_MEM V23
VDDR_MEM W23
VDDR_MEM W24
VDDR_MEM W25
VDDR_MEM Y25
VDDP_AGP U4
VDDP_AGP U5
VDDP_AGP U6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
A_AD24
A_AD30
A_AD17
A_AD18
A_PAR
A_AD31
A_CBE#0
A_CBE#3
A_AD26
A_AD28
A_AD21
A_AD29
A_AD20
A_AD27
A_AD25
A_AD23
A_AD22
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
A_PAR<10,26>
BSEL1 <5,24>
BSEL0 <5,24>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI RC300M-SYSTEM STRAP
13 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
0: IOQ=1
1: IOQ=12
DEFAULT:1
A_AD23 : CLOCK BYPASS DISABLE
A_AD24 : MOBILE CPU SELECT
A_CBE#3: NOT USED
0: DISABLE
1: ENABLE
0: TEST MODE
1: NORMAL MODE
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
A_AD28: SPREAD SPECTRUM ENABLE
0: DISABLE
1: ENABLE
0: REDUCEDE SET
DEFAULT : 0
DEFAULT: 01
1: FULL SET
A_AD26 : ENABLE IOQ
DEFAULT: 1
A_AD29: STRAP CONFIGURATION
A_AD27: FrcShortReset#
A_AD[31..30] : FSB CLK SPEED
DEFAULT:0
DEFAULT: 1
0: TEST MODE
1: NORMAL
DEFAULT: 10
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT: 1
A_CBE#0 :NO USED
DEFAULT: 1
DEFAULT : 1
A_AD20 : INTERNAL CLK GEN ENABLE
0: DEBUG MODE
1: NORMAL
0: BANIAS CPU
1: OTHER CPU
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
PAR: EXTENDED DEBUG MODE
0:PCICLK OUT
1: OSC CLK OUT
DEFAULT : 1
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD18 : ENABLE PHASE CALIBRATION
0: DISABLE
1:ENABLE
DEFAULT: 0
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R431 4.7K_0402_5%
R428 4.7K_0402_5%
R422 4.7K_0402_5%
R429 @4.7K_0402_5%
R469 @4.7K_0402_5%
R438 10K_0402_5%
1 2
R430 @10K_0402_5%
1 2
R461 10K_0402_5%
1 2
R425 4.7K_0402_5%
R443 10K_0402_5%
1 2
R434 10K_0402_5%
1 2
R427 10K_0402_5%
1 2
R463 @4.7K_0402_5%
R435 @4.7K_0402_5%
R452 10K_0402_5%
1 2
R448 10K_0402_5%
1 2
D86
RB751V_SOD323
2 1
R468 @4.7K_0402_5%
R1309 10K_0402_5%
1 2
R423 4.7K_0402_5%
R454 @4.7K_0402_5%
D85
RB751V_SOD323
2 1
R460 4.7K_0402_5%
R465 4.7K_0402_5%
R464 @4.7K_0402_5%
R466 @4.7K_0402_5%
R420 10K_0402_5%
1 2
R444 @4.7K_0402_5%
R467 @4.7K_0402_5%
R421 @4.7K_0402_5%
R424 10K_0402_5%
1 2
R440 @4.7K_0402_5%
R457 @4.7K_0402_5%
R462 @4.7K_0402_5%
R426 @4.7K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQS[0..7]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_ADD[0..15]
DDRA_SDQ32
DDRA_SDQS3
DDRA_SDQ42
DDRA_SDQS4
DDRA_SDQS2
DDRA_SDQ19
DDRA_SDQ34
DDRA_SDQS5
DDRA_SDQ43
DDRA_WE#
DDRA_SDQ26
DDRA_SDQ16
DDRA_SDQ35
DDRA_SDQ41
DDRA_SDQ27
DDRA_SDQ18
DDRA_SDQ40
DDRA_SDQ25
DDRA_SDQ33
DDRA_SDQ24
DDRA_SDQ17
DDRA_SDQ44
DDRA_RAS#
DDRA_SDQ38
DDRA_CAS#
DDRA_SDQ39
DDRA_SDQ46
DDRA_SDM4
DDRA_SDQ36
DDRA_SDQ23
DDRA_SDM5
DDRA_SDQ37
DDRA_SDQ45
DDRA_SDQ47
DDRA_SDQ31
DDRA_SDM3
DDRA_SDQ20
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ28
DDRA_VREF
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ4
DDRA_SDM1
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDM0
DDRA_SDQ5
DDRA_SDQ12
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ1
DDRA_SDQ8
DDRA_SDQ3
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQS1
DDRA_CKE_R1 DDRA_CKE_R0
DDRA_CS#0 DDRA_CS#1
DDRA_ADD5
DDRA_ADD12
DDRA_ADD9
DDRA_ADD7
DDRA_ADD3
DDRA_ADD1
DDRA_ADD10
DDRA_ADD13
DDRA_ADD6
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_ADD14
DDRA_ADD11
DDRA_ADD8
DDRA_ADD15
SMB_CK_DAT2<15,24,27> SMB_CK_CLK2<15,24,27>
DDRA_SDQ[0..63]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
DDRA_CKE_R1<9,16>
DDRA_CLK0<9> DDRA_CLK0#<9>
DDRA_WE#<9,15,16>
DDRA_CLK1# <9>
DDRA_CLK1 <9>
DDRA_CAS# <9,15,16>
DDRA_RAS# <9,15,16>
DDRA_CKE_R0 <9,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
+2.5V
+2.5V
+3VS
+2.5V
+2.5V
+2.5V+2.5V
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
DDR-SODIMM SLOT1
14 65, 07
星期三 七月
, 2004
Compal Electronics, Inc.
System Memory Decoupling caps
DDRA_VREF trace width of
20mils and space 20mils(min)
DIMM0
Group 6 sweep Group 7
Group 6 sweep Group 7
Group 0 sweep Group 1
Group 0 sweep Group 1
L
REVERSE
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C419
0.1U_0402_10V6K
1
2
C431
0.1U_0402_10V6K
1
2
C414
0.1U_0402_10V6K
1
2
C435
0.1U_0402_10V6K
1
2
C428
0.1U_0402_10V6K
1
2
C425
10U_0805_6.3V6M
1
2
C424
0.1U_0402_10V6K
1
2
C430
0.1U_0402_10V6K
1
2
C432
0.1U_0402_10V6K
1
2
C411
0.1U_0402_10V6K
1
2
R472
1K_0603_1%
12
C412
0.1U_0402_10V6K
1
2
C416
0.1U_0402_10V6K
1
2
C433
0.1U_0402_10V6K
1
2
C436
0.1U_0402_10V6K
1
2
C422
0.1U_0402_10V6K
1
2
C426
0.1U_0402_10V6K
1
2
C434
0.1U_0402_10V6K
1
2
C438
10U_0805_6.3V6M
1
2
C417
0.1U_0402_10V6K
1
2
C437
0.1U_0402_10V6K
1
2
C429
0.1U_0402_10V6K
1
2
C415
0.1U_0402_10V6K
1
2
R473
1K_0603_1%
12
C418
0.1U_0402_10V6K
1
2
C427
0.1U_0402_10V6K
1
2
C413
0.1U_0402_10V6K
1
2
JP24
AMP_1565918-1
VREF
1
VSS
3
DQ0
5
DQ1
7
VDD
9
DQS0
11
DQ2
13
VSS
15
DQ3
17
DQ8
19
VDD
21
DQ9
23
DQS1
25
VSS
27
DQ10
29
DQ11
31
VDD
33
CK0
35
CK0#
37
VSS
39
DQ16
41
DQ17
43
VDD
45
DQS2
47
DQ18
49
VSS
51
DQ19
53
DQ24
55
VDD
57
DQ25
59
DQS3
61
VSS
63
DQ26
65
DQ27
67
VDD
69
CB0
71
CB1
73
VSS
75
DQS8
77
CB2
79
VDD
81
CB3
83
DU
85
VSS
87
CK2
89
CK2#
91
VDD
93
CKE1
95
DU/A13
97
A12
99
A9
101
VSS
103
A7
105
A5
107
A3
109
A1
111
VDD
113
A10/AP
115
BA0
117
WE#
119
S0#
121
DU
123
VSS
125
DQ32
127
DQ33
129
VDD
131
DQS4
133
DQ34
135
VSS
137
DQ35
139
DQ40
141
VDD
143
VREF 2
VSS 4
DQ4 6
DQ5 8
VDD 10
DM0 12
DQ6 14
VSS 16
DQ7 18
DQ12 20
VDD 22
DQ13 24
DM1 26
VSS 28
DQ14 30
DQ15 32
VDD 34
VDD 36
VSS 38
VSS 40
DQ20 42
DQ21 44
VDD 46
DM2 48
DQ22 50
VSS 52
DQ23 54
DQ28 56
VDD 58
DQ29 60
DM3 62
VSS 64
DQ30 66
DQ31 68
VDD 70
CB4 72
CB5 74
VSS 76
DM8 78
CB6 80
VDD 82
CB7 84
DU/RESET# 86
VSS 88
VSS 90
VDD 92
VDD 94
CKE0 96
DU/BA2 98
A11 100
A8 102
VSS 104
A6 106
A4 108
A2 110
A0 112
VDD 114
BA1 116
RAS# 118
CAS# 120
S1# 122
DU 124
VSS 126
DQ36 128
DQ37 130
VDD 132
DM4 134
DQ38 136
VSS 138
DQ39 140
DQ44 142
VDD 144
DQ41
145
DQS5
147
VSS
149
DQ42
151
DQ43
153
VDD
155
VDD
157
VSS
159
VSS
161
DQ48
163
DQ49
165
VDD
167
DQS6
169
DQ50
171
VSS
173
DQ51
175
DQ56
177
VDD
179
DQ57
181
DQS7
183
VSS
185
DQ58
187
DQ59
189
VDD
191
SDA
193
SCL
195
VDD_SPD
197
VDD_ID
199
DQ45 146
DM5 148
VSS 150
DQ46 152
DQ47 154
VDD 156
CK1# 158
CK1 160
VSS 162
DQ52 164
DQ53 166
VDD 168
DM6 170
DQ54 172
VSS 174
DQ55 176
DQ60 178
VDD 180
DQ61 182
DM7 184
VSS 186
DQ62 188
DQ63 190
VDD 192
SA0 194
SA1 196
SA2 198
DU 200
C421
0.1U_0402_10V6K
1
2
C420
0.1U_0402_10V6K
1
2
C423
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQS[0..7]
DDRA_SDM[0..7]
DDRA_ADD[0..15]
DDRA_SDQ[0..63]
DDRB_VREF
DDRA_SDQ30
DDRA_SDQ23
DDRA_SDQ32
DDRA_SDQ24
DDRA_SDQ43
DDRA_SDQ31
DDRA_SDQ29
DDRA_SDQ35
DDRA_SDQ42
DDRA_SDQ39
DDRA_SDQ28
DDRA_SDM2
DDRA_SDQS4
DDRA_SDQ47
DDRA_SDM5
DDRA_SDQS2
DDRA_SDM4
DDRA_SDQ21
DDRA_SDQ26
DDRA_SDQ19
DDRA_SDQ36
DDRA_SDQ20
DDRA_SDQ46
DDRA_SDQ33
DDRA_SDQ27
DDRA_SDQ44
DDRA_SDM3
DDRA_SDQ17
DDRA_SDQS5
DDRA_SDQ37
DDRA_SDQ41
DDRA_SDQ34
DDRA_SDQ16
DDRA_SDQ45
DDRA_SDQ38
DDRA_SDQ22
DDRA_SDQ40
DDRA_SDQS3
DDRA_SDQ25
DDRA_SDQ18
DDRA_SDQS7
DDRA_SDQ50
DDRA_SDQ59
DDRA_SDQ51
DDRA_SDQS6
DDRA_SDQ48
DDRA_SDQ58
DDRA_SDQ57
DDRA_SDQ49
DDRA_SDQ56 DDRA_SDQ61
DDRA_SDM6
DDRA_SDM7
DDRA_SDQ52
DDRA_SDQ62
DDRA_SDQ60
DDRA_SDQ63
DDRA_SDQ54
DDRA_SDQ53
DDRA_SDQ55
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SWE#
DDRA_SCS#2
DDRA_CKE2
DDRA_SCS#3
DDRA_SRAS#
DDRA_SCAS#
DDRA_CKE3
DDRA_SMA13
DDRA_SMA10
DDRA_SMA12
DDRA_SMA3
DDRA_SMA7
DDRA_SMA1
DDRA_SMA9
DDRA_SMA5
DDRA_SMA15
DDRA_SMA6
DDRA_SMA8
DDRA_SMA2
DDRA_SMA0
DDRA_SMA11
DDRA_SMA4
DDRA_SMA14
DDRA_CKE3DDRA_CKE_R3
DDRA_WE# DDRA_SWE#
DDRA_CS#2 DDRA_SCS#2
DDRA_CKE2DDRA_CKE_R2
DDRA_RAS# DDRA_SRAS#
DDRA_CAS# DDRA_SCAS#
DDRA_CS#3 DDRA_SCS#3
DDRA_SMA9
DDRA_SMA12 DDRA_ADD9
DDRA_ADD12
DDRA_SMA7
DDRA_SMA5 DDRA_ADD7
DDRA_ADD5
DDRA_SMA3
DDRA_SMA1 DDRA_ADD3
DDRA_ADD1
DDRA_SMA10
DDRA_SMA13 DDRA_ADD10
DDRA_ADD13 DDRA_SMA14DDRA_ADD14
DDRA_ADD15DDRA_SMA15
DDRA_SMA11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_ADD11
DDRA_ADD8
DDRA_ADD6
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
DDRA_SDM[0..7]<9,14,16>
SMB_CK_CLK2<14,24,27> SMB_CK_DAT2<14,24,27>
DDRA_CLK3<9> DDRA_CLK3#<9>
DDRA_CLK4# <9>
DDRA_CLK4 <9>
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
DDRA_CKE_R2<9,16>
DDRA_RAS#<9,14,16>
DDRA_CAS#<9,14,16>
DDRA_CS#3<9,16>
DDRA_CKE_R3<9,16>
+2.5V
+3VS
+2.5V
+2.5V
+2.5V
+2.5V+2.5V
+3VS
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
DDR-SODIMM SLOT2
15 65, 07
星期三 七月
, 2004
Compal Electronics, Inc.
System Memory Decoupling caps
DIMM1
Group 6 sweep Group 7
Group 0 sweep Group 1
Group 0 sweep Group 1
DDRB_VREF trace width of
20mils and space
20mils(min)
L
STANDARD
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R401 10_0402_5%
12
R1122 10_0402_5%
12
R471
1K_0603_1%
12
C406
0.1U_0402_10V6K
1
2
R390 10_0402_5%
12
C408
0.1U_0402_10V6K
1
2
RP39
10_0404_4P2R_5%
1 4
2 3
JP23
AMP_1565917-1
VREF
1
VSS
3
DQ0
5
DQ1
7
VDD
9
DQS0
11
DQ2
13
VSS
15
DQ3
17
DQ8
19
VDD
21
DQ9
23
DQS1
25
VSS
27
DQ10
29
DQ11
31
VDD
33
CK0
35
CK0#
37
VSS
39
DQ16
41
DQ17
43
VDD
45
DQS2
47
DQ18
49
VSS
51
DQ19
53
DQ24
55
VDD
57
DQ25
59
DQS3
61
VSS
63
DQ26
65
DQ27
67
VDD
69
CB0
71
CB1
73
VSS
75
DQS8
77
CB2
79
VDD
81
CB3
83
DU
85
VSS
87
CK2
89
CK2#
91
VDD
93
CKE1
95
DU/A13
97
A12
99
A9
101
VSS
103
A7
105
A5
107
A3
109
A1
111
VDD
113
A10/AP
115
BA0
117
WE#
119
S0#
121
DU
123
VSS
125
DQ32
127
DQ33
129
VDD
131
DQS4
133
DQ34
135
VSS
137
DQ35
139
DQ40
141
VDD
143
VREF 2
VSS 4
DQ4 6
DQ5 8
VDD 10
DM0 12
DQ6 14
VSS 16
DQ7 18
DQ12 20
VDD 22
DQ13 24
DM1 26
VSS 28
DQ14 30
DQ15 32
VDD 34
VDD 36
VSS 38
VSS 40
DQ20 42
DQ21 44
VDD 46
DM2 48
DQ22 50
VSS 52
DQ23 54
DQ28 56
VDD 58
DQ29 60
DM3 62
VSS 64
DQ30 66
DQ31 68
VDD 70
CB4 72
CB5 74
VSS 76
DM8 78
CB6 80
VDD 82
CB7 84
DU/RESET# 86
VSS 88
VSS 90
VDD 92
VDD 94
CKE0 96
DU/BA2 98
A11 100
A8 102
VSS 104
A6 106
A4 108
A2 110
A0 112
VDD 114
BA1 116
RAS# 118
CAS# 120
S1# 122
DU 124
VSS 126
DQ36 128
DQ37 130
VDD 132
DM4 134
DQ38 136
VSS 138
DQ39 140
DQ44 142
VDD 144
DQ41
145
DQS5
147
VSS
149
DQ42
151
DQ43
153
VDD
155
VDD
157
VSS
159
VSS
161
DQ48
163
DQ49
165
VDD
167
DQS6
169
DQ50
171
VSS
173
DQ51
175
DQ56
177
VDD
179
DQ57
181
DQS7
183
VSS
185
DQ58
187
DQ59
189
VDD
191
SDA
193
SCL
195
VDD_SPD
197
VDD_ID
199
DQ45 146
DM5 148
VSS 150
DQ46 152
DQ47 154
VDD 156
CK1# 158
CK1 160
VSS 162
DQ52 164
DQ53 166
VDD 168
DM6 170
DQ54 172
VSS 174
DQ55 176
DQ60 178
VDD 180
DQ61 182
DM7 184
VSS 186
DQ62 188
DQ63 190
VDD 192
SA0 194
SA1 196
SA2 198
DU 200
R393 10_0402_5%
12
C410
0.1U_0402_10V6K
1
2
+
C1120
150U_D2_6.3VM
1
2
C399
0.1U_0402_10V6K
1
2
C392
0.1U_0402_10V6K
1
2
RP26
10_0404_4P2R_5%
1 4
2 3
C404
0.1U_0402_10V6K
1
2
C396
0.1U_0402_10V6K
1
2
C393
0.1U_0402_10V6K
1
2
R392 10_0402_5%
12
C401
10U_0805_6.3V6M
1
2
RP32
10_0404_4P2R_5%
1 4
2 3
C402
10U_0805_6.3V6M
1
2
R1121 10_0402_5%
12
+
C1121 150U_D2_6.3VM
1
2
C403
0.1U_0402_10V6K
1
2
C407
0.1U_0402_10V6K
1
2
R396 10_0402_5%
12
RP38
10_0404_4P2R_5%
1 4
2 3
C394
22U_1206_10V4Z
1
2
R470
1K_0603_1%
12
+
C1119 150U_D2_6.3VM
1
2
C409
0.1U_0402_10V6K
1
2
+
C1118
150U_D2_6.3VM
1
2
RP29
10_0404_4P2R_5%
1 4
2 3
R402 10_0402_5%
12
C398
0.1U_0402_10V6K
1
2
RP42
10_0404_4P2R_5%
1 4
2 3
C405
0.1U_0402_10V6K
1
2
C397
0.1U_0402_10V6K
1
2
C400
0.1U_0402_10V6K
1
2
RP35
10_0404_4P2R_5%
1 4
2 3
R391 10_0402_5%
12
C395
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_ADD[0..15]
DDRA_SDQS[0..7]
DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQ21
DDRA_SDQ16
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQ14
DDRA_SDQS1
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ22
DDRA_SDQS2
DDRA_SDQ50
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ51
DDRA_SDQ49
DDRA_SDQ53
DDRA_SDQS6
DDRA_SDM6
DDRA_SDQ59
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ48
DDRA_SDQ62
DDRA_SDQ58
DDRA_SDQS7
DDRA_SDM7
DDRA_SDQ56
DDRA_SDQ60
DDRA_SDQ57
DDRA_SDQ61
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQ41
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ42
DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ35
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ44
DDRA_SDQ38
DDRA_SDQ34
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ37
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDQS3
DDRA_SDM3
DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ20
DDRA_SDQ17
DDRA_SDQ6
DDRA_SDQ2
DDRA_SDQ7
DDRA_SDQ3
DDRA_SDQ5
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDM0
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ12
DDRA_SDQ9
DDRA_CS#0
DDRA_SDQ30
DDRA_SDQ26
DDRA_SDQ31
DDRA_SDQ27
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CS#3
DDRA_ADD9
DDRA_ADD8
DDRA_ADD2
DDRA_ADD10
DDRA_ADD13
DDRA_ADD15
DDRA_ADD1
DDRA_ADD0
DDRA_ADD14
DDRA_RAS#
DDRA_ADD12
DDRA_CS#1
DDRA_CS#2
DDRA_WE#
DDRA_ADD11
DDRA_ADD3
DDRA_ADD5
DDRA_CKE_R3
DDRA_CKE_R2
DDRA_ADD4
DDRA_ADD6
DDRA_CAS#
DDRA_ADD7
DDRA_SDQ[0..63]<9,14,15>
DDRA_SDQS[0..7]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
DDRA_CS#0 <9,14>
DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>
DDRA_CS#3 <9,15>
DDRA_RAS# <9,14,15>
DDRA_CS#1 <9,14>
DDRA_CS#2 <9,15>
DDRA_WE# <9,14,15>
DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>
DDRA_CAS# <9,14,15>
+2.5V
+2.5V
+1.25VS +1.25VS
+2.5V
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
Title
Size Document Number Re v
Date: Sheet of
LA-2411
0.1
DDR Termination Resistors
16 65, 07
星期三 七月
, 2004
Compal Electronics, Inc.
DDR Termination resistors & Decoupling caps
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM & Layout 93.1.9
C466
0.1U_0402_10V6K
1
2
C486
0.1U_0402_10V6K
1
2
C470
0.1U_0402_10V6K
1
2
C469
0.1U_0402_10V6K
1
2
RP73
56 _0804_8P4R_5%
18 27 36 45
R474
33_0402_5%
12
C472
0.1U_0402_10V6K
1
2
C495
0.1U_0402_10V6K
1
2
C458
0.1U_0402_10V6K
1
2
RP91
56 _0804_8P4R_5%
18 27 36 45
RP89
33_0404_4P2R_5%
14 23
RP70
56 _0804_8P4R_5%
18 27 36 45
C494
0.1U_0402_10V6K
1
2
RP82
56 _0804_8P4R_5%
18 27 36 45
RP68
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
RP65
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
C460
0.1U_0402_10V6K
1
2
C476
0.1U_0402_10V6K
1
2
C484
0.1U_0402_10V6K
1
2
C463
0.1U_0402_10V6K
1
2
RP78
33_0804_8P4R_5%
18 27 36 45
C490
4.7U_0805_16V6K
1
2
RP85
56 _0804_8P4R_5%
18 27 36 45
C473
0.1U_0402_10V6K
1
2
C474
0.1U_0402_10V6K
1
2
C496
0.1U_0402_10V6K
1
2
C471
0.1U_0402_10V6K
1
2
C465
0.1U_0402_10V6K
1
2
RP84
33_0804_8P4R_5%
18 27 36 45
C467
0.1U_0402_10V6K
1
2
C464
0.1U_0402_10V6K
1
2
RP88
56 _0804_8P4R_5%
18 27 36 45
RP79
56 _0804_8P4R_5%
18 27 36 45
RP92
33_0404_4P2R_5%
14 23
C455
0.1U_0402_10V6K
1
2
C493
0.1U_0402_10V6K
1
2
C461
0.1U_0402_10V6K
1
2
C483
0.1U_0402_10V6K
1
2
RP81
33_0804_8P4R_5%
18 27 36 45
C452
0.1U_0402_10V6K
1
2
C462
0.1U_0402_10V6K
1
2
RP67
56 _0804_8P4R_5%
18 27 36 45
RP75
33_0804_8P4R_5%
18 27 36 45
+
C491
@100U_D2_10M_R45
1
2
C468
0.1U_0402_10V6K
1
2
C489
4.7U_0805_16V6K
1
2
RP72
33_0404_4P2R_5%
14 23
+
C492
100U_D2_10M_R45
1
2
C457
0.1U_0402_10V6K
1
2
RP90
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
RP80
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
RP86
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
C478
0.1U_0402_10V6K
1
2
C459
0.1U_0402_10V6K
1
2
C497
4.7U_0805_16V6K
1
2
C479
0.1U_0402_10V6K
1
2
C475
0.1U_0402_10V6K
1
2
RP71
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
C482
0.1U_0402_10V6K
1
2
RP83
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
RP87
33_0404_4P2R_5%
14 23
C481
0.1U_0402_10V6K
1
2
C456
0.1U_0402_10V6K
1
2
C451
0.1U_0402_10V6K
1
2
RP76
56 _0804_8P4R_5%
18 27 36 45
C480
0.1U_0402_10V6K
1
2
R1180
@100_0402_5%
1 2
C453
0.1U_0402_10V6K
1
2
RP74
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
C488
0.1U_0402_10V6K
1
2
C485
0.1U_0402_10V6K
1
2
C454
0.1U_0402_10V6K
1
2
C487
0.1U_0402_10V6K
1
2
RP69
33_0404_4P2R_5%
14 23
C477
0.1U_0402_10V6K
1
2
RP93
56 _0804_8P4R_5%
18 27 36 45
RP77
56 _0804_8P4R_5%
1 8
2 7
3 6
4 5
RP66
56 _0804_8P4R_5%
18 27 36 45
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
STRAP_A
STRAP_L
STRAP_F
FREQOUT
STRAP_E
AGP_AD[0..31]
STRAP_M
STRAP_O
STRAP_N
STRAP_D
STRAP_B
AGP_ST[0..2]
AGP_SBA[0..7]
AGP_CBE#[0..3]
STRAP_J
XTALIN_SSFREQOUT
STRAP_G
XTALIN
XTALIN_SS
CRT_R
TV_LUMA
AGP_REQ#
AGP_AD12
AGP_RSET
TXA0-
STRAP_E
AGP_SBA7
AGP_SBA2
AGP_AD22
AGP_AD2
CRT_HSYNC
TXBCLK+
VREFG
STRAP_J
TV_CRMA
AGP_ADSTB0
AGP_AD27
AGP_AD16
DVOMODE
STRAP_M
AGP_SBSTB#
AGP_ST0
AGP_RBF#
AGP_DEVSEL#
AGP_AD23
AGP_AD17
AGP_AD8
TXB0+
AGP_AD5
TXA2+
TXA1+
STRAP_B
TV_COMPS
AGP_SBA4
AGP_BUSY#
AGP_AD10
TXBCLK-
AGP_SBA1
AGP_PAR
AGP_CBE#3
AGP_AD15
AGP_AD1
STRAP_K
CRT_G
STRAP_A
STRAP_K
AGP_ADSTB0#
AGP_IRDY#
AGP_AD20
AGP_AD11
STRAP_O
XTALIN
AGP_DBI_HI/PIPE#
AGP_ST2
AGP_SBA3
AGP_STP#
AGP_AD29
AGP_AD19
AGP_AD4
CRT_B
AGP_DBI_LO
AGP_ST1
AGP_AD14
3VDDCCL
TXB1-
MCLK_SPREAD
STRAP_F
AGP_CBE#1
AGP_CBE#0
AGP_AD18
AGP_AD9
TXB2+
TXB2-
TXA1-
STRAP_D
SUSSTAT#
AGP_AD26
AGP_AD25
TXACLK-
STRAP_G
SSIN
AGP_SBA0
AGP_ADSTB1
CLK_AGP_EXT_66M
AGP_CBE#2
AGP_AD31
AGP_AD0
TXA0+
STRAP_T
STRAP_N
AGP_SBA5
AGP_FRAME#
AGP_AD24
AGP_AD3
STRAP_H
3VDDCDA
TXB1+
TXACLK+
STRAP_L
AGP_ADSTB1#
AGP_GNT#
AGP_AD30
AGP_AD28
AGP_AD21
AGP_AD7
CRT_VSYNC
ENAVDD
TXB0-
STRAP_H
AGP_STOP#
TXA2-
AGP_SBSTB
AGP_SBA6
AGP_TRDY#
AGP_AD13
AGP_AD6
DRAM128M
STRAP_S
STRAP_R
SSOUT
ENBKL
STRAP_T
STRAP_R
STRAP_S
ENBKL
DRAM128M
XTALIN_SS
NB_RST_R#NB_RST#
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
CLK_AGP_EXT_66M<24>
AGP_BUSY#<10,27> AGP_STP#<10,27>
VREF_8X_IN<10>
AGP8X_DET#<10>
TV_LUMA<11,46>
AGP_RBF#<10>
PCI_PIRQA#<10,26,31,34>
AGP_WBF#<10>
CRT_B <11,25>
CRT_HSYNC <11,25>
AGP_ADSTB0<10>
AGP_REQ#<10>
3VDDCCL <11,25>
AGP_TRDY#<10>
AGP_STOP#<10>
AGP_IRDY#<10>
AGP_ADSTB1<10>
3VDDCDA <11,25>
AGP_SBSTB#<10>
TV_COMPS<11,46>
AGP_ADSTB1#<10> AGP_ADSTB0#<10>
CRT_R <11,25>
CRT_VSYNC <11,25>
AGP_DBI_HI/PIPE#<10>
AGP_PAR<10>
AGP_SBSTB<10>
AGP_DBI_LO<10>
AGP_GNT#<10>
NB_RST#<8,26>
CRT_G <11,25>
TV_CRMA<11,46>
AGP_DEVSEL#<10>
AGP_FRAME#<10>
TXACLK- <25>
TXB0+ <25>
TXBCLK- <25>
TXA0- <25>
TXA0+ <25>
TXB1- <25>
TXA2- <25>
TXB1+ <25>
TXA1- <25>
TXA2+ <25>
TXB2+ <25>
TXB2- <25>
TXBCLK+ <25>
TXB0- <25>
TXA1+ <25>
TXACLK+ <25>
ENAVDD <10,25>
DDC_DAT <10,25>
DDC_CLK <10,25>
AGP_SUS_STAT#<27>
ENBKL <10,44>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+1.5VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI M10-P & M9+X (AGP BUS)
17 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
GPIO0
GPIO6
GPIO5
GPIO4
VGA_Disable
3.3V OSC out for W180
GPIO7
1.5V OSC out for M9+X
1.2V OSC out for
M10-P
ID_Disable
Rb
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
GPIO8
Ra
GPIO3
GPIO13
GPIO2
GPIO12
GPIO11
GPIO9
GPIO1
AGP, DAC & LVDS INTERFACE
AGP8X_DET#
Low:
AGP3.0
(15mil)
(25mil)
(15mil)
(15mil)
(25 mil)
SS%
(Closed to M26)
If M10+P POP 47_0603_1%
If M9+P POP 137_0603_1%
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)
L
Ra 261_0603_1%
150_0402_5%
150_0402_5%
180_0603_5%
M10-PM9+X
Rb
Fin>Fout>Fin-3.75%
Spread % Setting for
Freq. Range
Fin>Fout>Fin-1.25%
0
1
Selection Table For W180
SS%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
For VGA DDR spread sprum
Vedio Memory Config.
*R S
0 0
0 1
1 0
1 1
4Mx32 Samsung
4Mx32 Hynix
8Mx32 Samsung
8Mx32 Hynix
Size Vendor
For 8Mx32 VGA DRAM only
R235 @1K_0402_5%
1 2
R1 @0_0402_5%
1 2
R267 100K_0402_5%
R247 @10K_0402_5%
12
R270 10K_0402_5%
12
C184 @10P_0402_50V8K
1 2
R268 22_0402_5%
1 2
R234
M10@1K_0603_1%
12
R238 @10K_0402_5%
12
U7
W180-01GT_SO8
X1/CLK
1
X2 2
FS1
7
FS2
8
VDD 6
CLKOUT 5
SS% 4
GND
3
R1255 10K_0402_5%
12
C189
0.1U_0402_10V6K
1
2
R257 @10K_0402_5%
12
R258 0_0402_5%
1 2
R250 @10K_0402_5%
12
R272 499_0402_1%
1 2
R236 @10K_0402_5%
12
R233 @10K_0402_5%
12
R244 @10K_0402_5%
12
R242 @10K_0402_5%
12
R232 @10K_0402_5%
12
R239
M10@1K_0603_1%
12
R16 0_0402_5%
12
R1256 10K_0402_5%
12
R243 M10@10K_0402_5%
12
R1316 @47_0603_1%
1 2
R271 @10K_0402_5%
12
R274 10K_0402_5%
1 2
R264 47_0603_1%
1 2
L13
FCM2012C-800_0805
1 2
R246 @10K_0402_5%
12
R936 10K_0402_5%
C191
2.2U_0603_6.3V4Z
1
2
R266 715_0603_1%
R1297
M9@10K_0402_5%
1 2
C186
0.1U_0402_10V6K
1
2
R248 @10K_0402_5%
12
R276 1K_0603_5%
1 2
C188
0.1U_0402_10V6K
1
2
R265
M9+M10@0_0402_5%
1 2
R269 10K_0402_5%
12
C185
0.1U_0402_10V6K
1
2
R249 @10_0402_5%
1 2
D69
@RB751V_SOD323 2 1
R259 @10K_0402_5%
12
G
D
S
Q30
M9@2N7002_SOT23
2
13
R1149
@10K_0402_5%
12
R245 @10K_0402_5%
12
R254 @10K_0402_5%
12
R241 M10@10K_0402_5%
12
R6
0_0603_5%
1 2
R252 @10K_0402_5%
12
R261
10K_0402_5%
12
R830 M10@0_0402_5%
1 2
R260 @10K_0402_5%
12
C187
@15P_0402_50V8J
X1
27MHZ_15P
OUT 3
GND 2
VDD
4
OE
1
R275 1K_0603_5%
1 2
R2 @22_0402_5%
1 2
R262 261_0603_1%
1 2
PCI/AGPAGP8XCLK
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1
SSC DAC2
M10-P/(M9+X)
(1/6)
THRM
U6A
SA002160E00(0301021300)
AD0
H29
AD1
H28
AD2
J29
AD3
J28
AD4
K29
AD5
K28
AD6
L29
AD7
L28
AD8
N28
AD9
P29
AD10
P28
AD11
R29
AD12
R28
AD13
T29
AD14
T28
AD15
U29
AD16
N25
AD17
R26
AD18
P25
AD19
R27
AD20
R25
AD21
T25
AD22
T26
AD23
U25
AD24
V27
AD25
W26
AD26
W25
AD27
Y26
AD28
Y25
AD29
AA26
AD30
AA25
AD31
AA27
C/BE#0
N29
C/BE#1
U28
C/BE#2
P26
C/BE#3
U26
PCICLK
AG30
RST#
AG28
REQ#
AF28
GNT#
AD26
PAR
M25
STOP#
N26
DEVSEL#
V29
TRDY#
V28
IRDY#
W29
FRAME#
W28
INTA#
AE26
WBF#
AC26
STP_AGP#
AH30
AGP_BUSY#
AH29
RBF#
AE29
AD_STBF_0
M28
AD_STBF_1
V25
AD_STBS_0
M29
AD_STBS_1
V26
SBA0
AD28
SBA1
AD29
SBA2
AC28
SBA3
AC29
SBA4
AA28
SBA5
AA29
SBA6
Y28
SBA7
Y29
ST0
AF29
ST1
AD27
ST2
AE28
SB_STBF
AB29
SB_STBS
AB28
AGPREF
M26
AGPTEST
M27
DBI_HI
AB25
DBI_LO
AB26
AGP8X_DET#
AC25
DMINUS
AE11
DPLUS
AF11
R2SET
AK21
C_R
AJ23
Y_G
AJ22
COMP_B
AK22
H2SYNC
AJ24
V2SYNC
AK24
DDC3CLK
AG23
DDC3DATA
AG24
SSIN
AK25
SSOUT
AJ25
XTALIN
AH28
XTALOUT
AJ29
TESTEN
AH27
SUS_STAT#
AG26
GPIO0 AJ5
GPIO1 AH5
GPIO2 AJ4
GPIO3 AK4
GPIO4 AH4
GPIO5 AF4
GPIO6 AJ3
GPIO7 AK3
GPIO8 AH3
GPIO9 AJ2
GPIO10 AH2
GPIO11 AH1
GPIO12 AG3
GPIO13 AG1
GPIO14 AG2
GPIO15 AF3
GPIO16 AF2
VREFG/(NC) AG4
ROMCS# AF5
ZV_LCDDATA0 AH6
ZV_LCDDATA1 AJ6
ZV_LCDDATA2 AK6
ZV_LCDDATA3 AH7
ZV_LCDDATA4 AK7
ZV_LCDDATA5 AJ7
ZV_LCDDATA6 AH8
ZV_LCDDATA7 AJ8
ZV_LCDDATA8 AH9
ZV_LCDDATA9 AJ9
ZV_LCDDATA10 AK9
ZV_LCDDATA11 AH10
ZV_LCDDATA12 AE6
ZV_LCDDATA13 AG6
ZV_LCDDATA14 AF6
ZV_LCDDATA15 AE7
ZV_LCDDATA16 AF7
ZV_LCDDATA17 AE8
ZV_LCDDATA18 AG8
ZV_LCDDATA19 AF8
ZV_LCDDATA20 AE9
ZV_LCDDATA21 AF9
ZV_LCDDATA22 AG10
ZV_LCDDATA23 AF10
ZV_LCDCNTL0 AJ10
ZV_LCDCNTL1 AK10
ZV_LCDCNTL2 AJ11
ZV_LCDCNTL3 AH11
DVOMODE AE10
TXOUT_L0N AK16
TXOUT_L0P AH16
TXOUT_L1N AH17
TXOUT_L1P AJ16
TXOUT_L2N AH18
TXOUT_L2P AJ17
TXOUT_L3N AK19
TXOUT_L3P AH19
TXCLK_LN AK18
TXCLK_LP AJ18
TXOUT_U0N AG16
TXOUT_U0P AF16
TXOUT_U1N AG17
TXOUT_U1P AF17
TXOUT_U2N AF18
TXOUT_U2P AE18
TXOUT_U3N AH20
TXOUT_U3P AG20
TXCLK_UN AF19
TXCLK_UP AG19
DIGON AE12
BLON/(BLON#) AG12
TX0M AJ13
TX0P AH14
TX1M AJ14
TX1P AH15
TX2M AJ15
TX2P AK15
TXCM AH13
TXCP AK13
DDC2CLK AE13
DDC2DATA AE14
HPD1 AF12
RAK27
GAJ27
BAJ26
HSYNC AG25
VSYNC AH25
RSET AH26
DDC1DATA AF25
DDC1CLK AF24
AUXWIN AF26
TEST_MCLK/(NC) B6
TEST_YCLK/(NC) E8
PLLTEST/(NC) AE25
RSTB_MSK/(NC) AG29
R263
150_0402_5%
12
R237 0_0402_5%
1 2
R955
@10K_0402_5%
12
R574 10K_0402_5%
R240 @10K_0402_5%
12
R829 M9@0_0402_5%
1 2
R253 0_0402_5%
1 2
R256 @10K_0402_5%
12
C190
0.1U_0402_10V6K
1
2
R273
10K_0402_5%
1 2
R255 @10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NDQSA3
NMDA13
NMDA26
NMDA32
NMDA7
NDQSA0
NMAA6
NMDA12
NDQMA1
NMDA59
NMDA16
NMDA43
MVREFS
NMDA30
NMDA27
NDQMA4
NMDA3
NMDA1
NMAA11
NMDA25
NMAA12
NDQSA7
NMDA11
NMDA46
NMDA50
NMDA2
NDQMA0
NMAA4
NMDA52
NMDA55
NDQSA5
NDQMA3
NMDA24
NMAA0
NMDA45
NMDA48
NDQSA2
NMDA49
NDQMA7
NMDA33
NMDA19
NMCASA#
NMDA18
NMDA28
NMDA38
NMAA2
NMDA41
NMDA47
NMDA35
NMAA10
NMCLKA0#
NMDA14
NMDA31
NMDA15
NMDA20
NMDA56
NDQSA4
NMAA[0..13]
NMDA54
MVREFD
NMDA58
NMDA51
NMDA37
NMDA42
NMDA6
NMDA34
NMAA9
NMDA10
NMDA60
NMDA62
NDQMA6
NMCKEA
NMDA4
NMWEA#
NMDA36
NMDA61
NDQMA[0..7]
NMDA44 NMCSA0#
NDQMA5
NMDA39
NMDA63
NMDA0
NMDA17
NDQSA6
MVREFD
NMAA8
NMDA29
NDQMA2
NMAA7
NMDA[0..63]
NMAA3
NDQSA1
NMCLKA1
NMAA1
NMAA13
NMDA57
NMDA21
NMDA5
NMDA9
MVREFS
NMAA5
NMDA23
NMDA22
NMDA53
NMDA40
NMDA8
NDQSA[0..7]
NMCLKA1#
NMRASA#
NMCLKA0
NMCSA1#
NMCLKA0# <22>
NMCASA# <22>
NMDA[0..63]<22>
NMCSA0# <22>
NDQMA[0..7]<22>
NMCLKA1 <22>
NMAA[0..13]<22>
NMWEA# <22>
NDQSA[0..7]<22>
NMCLKA1# <22>
NMCKEA <22>
NMRASA# <22>
NMCLKA0 <22>
NMCSA1# <22>
+2.5VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI M10-P/M9+X DDR-A
18 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Poped for M10-P
Depoped for
M9+X
MEMORY
INTERFACE A
(25 mil)
(25 mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R475
1K_0402_1%
12
R486
M10@1K_0402_1%
12
R478
1K_0402_1%
12
R487
M10@1K_0402_1%
12
C498
0.1U_0402_10V6K
1
2
MEMORY INTERFACE
A
M10-P/(M9+X)
(2/6)
U6B
SA002160E00(0301021300)
DQA0
L25
DQA1
L26
DQA2
K25
DQA3
K26
DQA4
J26
DQA5
H25
DQA6
H26
DQA7
G26
DQA8
G30
DQA9
D29
DQA10
D28
DQA11
E28
DQA12
E29
DQA13
G29
DQA14
G28
DQA15
F28
DQA16
G25
DQA17
F26
DQA18
E26
DQA19
F25
DQA20
E24
DQA21
F23
DQA22
E23
DQA23
D22
DQA24
B29
DQA25
C29
DQA26
C25
DQA27
C27
DQA28
B28
DQA29
B25
DQA30
C26
DQA31
B26
DQA32
F17
DQA33
E17
DQA34
D16
DQA35
F16
DQA36
E15
DQA37
F14
DQA38
E14
DQA39
F13
DQA40
C17
DQA41
B18
DQA42
B17
DQA43
B15
DQA44
C13
DQA45
B14
DQA46
C14
DQA47
C16
DQA48
A13
DQA49
A12
DQA50
C12
DQA51
B12
DQA52
C10
DQA53
C9
DQA54
B9
DQA55
B10
DQA56
E13
DQA57
E12
DQA58
E10
DQA59
F12
DQA60
F11
DQA61
E9
DQA62
F9
DQA63
F8
AA0 E22
AA1 B22
AA2 B23
AA3 B24
AA4 C23
AA5 C22
AA6 F22
AA7 F21
AA8 C21
AA9 A24
AA10 C24
AA11 A25
AA12/(AA13) E21
AA13/(AA12) B20
AA14/(NC) C19
DQMA#0 J25
DQMA#1 F29
DQMA#2 E25
DQMA#3 A27
DQMA#4 F15
DQMA#5 C15
DQMA#6 C11
DQMA#7 E11
QSA0 J27
QSA1 F30
QSA2 F24
QSA3 B27
QSA4 E16
QSA5 B16
QSA6 B11
QSA7 F10
RASA# A19
CASA# E18
WEA# E19
CSA0# E20
CSA1# F20
CKEA B19
CLKA0 B21
CLKA0# C20
CLKA1 C18
CLKA1# A18
DIMA0 D30
DIMA1 B13
MVREFD B7
MVREFS/(NC) B8
C503
M10@0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDB26
NMDB40
NMAB5
NMDB62
NMDB[0..63]
NMDB44
NMDB48
NMDB18
NMDB54
NDQSB3
NMDB49
NMDB63
NMAB0
NMAB11
NDQSB4
NDQSB7
NMDB39
NMDB22
NMDB36
NMAB7
NMDB12
NMDB21
NMDB31
NMCLKB0#
NMDB42
NMAB2
NMAB4
NMDB34
NMDB43
NMCLKB0
NMDB19
NDQMB6
NMDB20
NMDB11
NMDB29
NDQMB1
NMCASB#
NDQMB4
NMDB53
NMDB52
NMDB14
NMAB12
NDQMB0
NMAB[0..13]
NMDB10
NMDB38
NMDB46
NMDB35
NMDB45
NMDB51 NMCLKB1#
NMDB61
NMDB13
NMAB1
NMDB50
NDQMB[0..7]
NMDB60
NMDB25
NMDB2
NMDB4
NMWEB#
NMDB16
NMDB23
NMDB7
NMAB3
NMAB10
NMDB59
NMDB41
NMDB24
NMDB3
NMDB58
NDQMB7
NMDB30
NMDB57
NMAB6
NMDB8
NDQSB1
NDQSB6
NDQMB5
NMAB13
NMDB28
NMDB27
NMAB9
NDQSB[0..7]
NMAB8
NMCSB0#
NMDB47
NDQMB2
NMDB6
NMDB55
NMDB9
NMDB33
NMDB56
NMDB15
NDQSB0
NMDB5
NMDB17
NMDB32
NMDB37
NMRASB#
NDQMB3
NMDB1
NMDB0
NDQSB5
NDQSB2
NMCKEB
NMCLKB1
NMCSB1#
NMCASB# <23>
NMWEB# <23>
NMCLKB0 <23>
NMDB[0..63]<23>
NMCKEB <23>
NDQMB[0..7]<23>
NMCSB0# <23>
NMAB[0..13]<23>
NMCLKB0# <23>
NDQSB[0..7]<23>
NMRASB# <23>
NMCLKB1# <23>
NMCLKB1 <23>
NMCSB1# <23>
+1.8VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI M10-P/M9+X DDR-B
19 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
(15mil)
MEMORY
INTERFACE B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MEMORY INTERFACE B
M10-P/(M9+X)
(3/6)
U6C
SA002160E00(0301021300)
DQB0
D7
DQB1
F7
DQB2
E7
DQB3
G6
DQB4
G5
DQB5
F5
DQB6
E5
DQB7
C4
DQB8
B5
DQB9
C5
DQB10
A4
DQB11
B4
DQB12
C2
DQB13
D3
DQB14
D1
DQB15
D2
DQB16
G4
DQB17
H6
DQB18
H5
DQB19
J6
DQB20
K5
DQB21
K4
DQB22
L6
DQB23
L5
DQB24
G2
DQB25
F3
DQB26
H2
DQB27
E2
DQB28
F2
DQB29
J3
DQB30
F1
DQB31
H3
DQB32
U6
DQB33
U5
DQB34
U3
DQB35
V6
DQB36
W5
DQB37
W4
DQB38
Y6
DQB39
Y5
DQB40
U2
DQB41
V2
DQB42
V1
DQB43
V3
DQB44
W3
DQB45
Y2
DQB46
Y3
DQB47
AA2
DQB48
AA6
DQB49
AA5
DQB50
AB6
DQB51
AB5
DQB52
AD6
DQB53
AD5
DQB54
AE5
DQB55
AE4
DQB56
AB2
DQB57
AB3
DQB58
AC2
DQB59
AC3
DQB60
AD3
DQB61
AE1
DQB62
AE2
DQB63
AE3
AB0 N5
AB1 M1
AB2 M3
AB3 L3
AB4 L2
AB5 M2
AB6 M5
AB7 P6
AB8 N3
AB9 K2
AB10 K3
AB11 J2
AB12/(AB13) P5
AB13/(AB12) P3
AB14/(NC) P2
DQMB#0 E6
DQMB#1 B2
DQMB#2 J5
DQMB#3 G3
DQMB#4 W6
DQMB#5 W2
DQMB#6 AC6
DQMB#7 AD2
QSB0 F6
QSB1 B3
QSB2 K6
QSB3 G1
QSB4 V5
QSB5 W1
QSB6 AC5
QSB7 AD1
RASB# R2
CASB# T5
WEB# T6
CSB0# R5
CSB1# R6
CKEB R3
CLKB0 N1
CLKB0# N2
CLKB1 T2
CLKB1# T3
MEMVMODE0 C6
MEMVMODE1 C7
DIMB0 E3
DIMB1 AA3
MEMTEST C8
R509 4.7K_0402_5%
1 2
R510 4.7K_0402_5%
1 2
R511 47_0603_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+LVDDR+VDDC1.5
+1.8VS
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_PNLIO1.8
+VDD_PNLIO2.5
+3VS
+2.5VDDRH
+VDD_PLL1.8
+VDD_PNLPLL1.8
+VDD_DAC1.8
+3VS
+2.5VS
+VDD_MEMPLL1.8
+1.8VS
+VDD_PNLIO1.8
+2.5VS
+1.8VS
+2.5VS
+2.5VS
+VDD_MEMPLL1.8
+VDD_DAC1.8
+VDD_PNLPLL1.8
+VDD_PNLPLL1.8
+2.5VDDRH
+VDD_PNLIO1.8
+1.8VS
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_PLL1.8
+1.8VS
+1.5VS
+1.5VS
+VDDC1.5 +LVDDR
+3VS
+1.5VS
+2.5VS
+1.8VS
+VDD_PNLIO1.8
+VDD_PNLIO2.5
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI M10-P/M9+X POWER-A
20 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
(20 mil)
As close as possible to related pin
(20 mil)
(20 mil)
POWER
INTERFACE
(20 mil)
(20 mil)
(20 mil)
(20 mil)
(20 mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)
L
SA052050010(MIC5205-2.8BM5), max:150mA
Poped for M10-P
Poped for M9+X
Poped for
M10-P
Poped for M9+X
Poped for M10-P
C215
0.1U_0402_10V6K
1
2
C869
0.1U_0402_10V6K
1
2
C194
0.1U_0402_10V6K
1
2
C199
0.1U_0402_10V6K
1
2
C203
0.1U_0402_10V6K
1
2
R279
M10@0_0805_5%
1 2
C209
10U_0805_6.3V6M
1
2
C220
0.1U_0402_10V6K
1
2
R281 M9@0_0603_5%
1 2
C202
2.2U_0603_6.3V4Z
1
2
C863
0.1U_0402_10V6K
1
2
C868
0.1U_0402_10V6K
1
2
C192
22U_1206_10V4Z
1
2
C208
0.1U_0402_10V6K
1
2
C201
0.01U_0402_16V7K
1
2
L17
CHB1608U301_0603
1 2
R277 M10@0_0402_5%
1 2
C213
0.1U_0402_10V6K
1
2
C217
0.1U_0402_10V6K
1
2
L20
CHB1608U301
1 2
R280 M10@0_0603_5%
1 2
C862
0.1U_0402_10V6K
1
2
C870
0.1U_0402_10V6K
1
2
C216
0.1U_0402_10V6K
1
2
C200
0.01U_0402_16V7K
1
2
R278 M10@0_0402_5%
1 2
L21
@CHB1608U301
1 2
C193
0.1U_0402_10V6K
1
2
C865
0.1U_0402_10V6K
1
2
C212
0.1U_0402_10V6K
1
2
C205
0.1U_0402_10V6K
1
2
C207
0.1U_0402_10V6K
1
2
C968
0.1U_0402_10V6K
1
2
C871
0.1U_0402_10V6K
1
2
C196
0.01U_0402_16V7K
1
2
C214
10U_0805_6.3V6M
1
2
C866
0.1U_0402_10V6K
1
2
C195
0.01U_0402_16V7K
1
2
L15
CHB1608U301_0603
1 2
C967
0.1U_0402_10V6K
1
2
L14
CHB1608U301_0603
1 2
C210
0.1U_0402_10V6K
1
2
C197
22U_1206_10V4Z
1
2
C92
0.1U_0402_10V6K
1
2
I/O POWER
M10-P/(M9+X)
(4/6)
U6D
SA002160E00(0301021300)
VDDR1
B1
VDDR1
B30
VDDR1
A15
VDDR1
A21
VDDR1
A28
VDDR1
A3
VDDR1
A9
VDDR1
AA1
VDDR1
AA4
VDDR1
AA7
VDDR1
AA8
VDDR1
AD4
VDDR1
D5
VDDR1
D8
VDDR1
D11
VDDR1
D13
VDDR1
D14
VDDR1
D17
VDDR1
D20
VDDR1
D23
VDDR1
D26
VDDR1
E27
VDDR1
F4
VDDR1
G7
VDDR1
G10
VDDR1
G13
VDDR1
G15
VDDR1
G19
VDDR1
G22
VDDR1
G27
VDDR1
H10
VDDR1
H13
VDDR1
H15
VDDR1
H17
VDDR1
H19
VDDR1
H22
VDDR1
J1
VDDR1
J23
VDDR1
J24
VDDR1
J4
VDDR1
J7
VDDR1
J8
VDDR1
L27
VDDR1
L8
VDDR1
M4
VDDR1
N4
VDDR1
N7
VDDR1
N8
VDDR1
R1
VDDR1
T4
VDDR1
T7
VDDR1
T8
VDDR1
V4
VDDR1
V7
VDDR1
V8
VDDR1/(CLKAFB)
D19
VDDR1/(CLKBFB)
R4
VDDC15/(VDDC18)
AC11
VDDC15/(VDDC18)
AC20
VDDC15/(VDDC18)
H11
VDDC15/(VDDC18)
H20
VDDC15/(VDDC18)
L23
VDDC15/(VDDC18)
P8
VDDC15/(VDDC18)
Y23
VDDC15/(VDDC18)
Y8
TPVDD
AK12
TPVSS
AJ12
AVSSN
AH23
AVSSQ
AD24
VDDRH0 F18
VDDRH1 N6
VSSRH0 F19
VSSRH1 M6
VDDR4 AC10
VDDR4 AC9
VDDR4 AD10
VDDR4 AD9
VDDR4 AG7
VDDP AA23
VDDP AA24
VDDP AB30
VDDP AC23
VDDP AC27
VDDP AE30
VDDP AF27
VDDP J30
VDDP M23
VDDP M24
VDDP N30
VDDP P23
VDDP P27
VDDP T23
VDDP T24
VDDP T30
VDDP U27
VDDP V23
VDDP V24
VDDP W30
VDDP Y27
LVSSR AF20
LVSSR AF15
LVSSR AE19
LVSSR AE16
LPVSS AJ19
VSS1DI AE23
VSS2DI AE21
VDD1DI AE24
VDD2DI AE22
TXVDDR AF13
TXVDDR AF14
TXVSSR AG13
TXVSSR AG14
TXVSSR AH12
AVDD
AH24
A2VDD
AG21
A2VDD
AH21
A2VDDQ
AF22
A2VSSN
AH22
A2VSSN
AJ21
A2VSSQ
AF23
MPVDD A7
MPVSS A6
PVSS AJ28
PVDD AK28
VDDR3 AC19
VDDR3 AC21
VDDR3 AC22
VDDR3 AC8
VDDR3 AD19
VDDR3 AD21
VDDR3 AD22
VDDR3 AD7
LVDDR_25/(LVDDR_18_25) AE20
LVDDR_25/(LVDDR_18_25) AE17
LVDDR_18 AF21
LVDDR_18 AE15
LPVDD AJ20
C931
2.2U_0603_6.3V4Z
1
2
C219
0.1U_0402_10V6K
1
2
C204
1U_0603_10V6K
1
2
C549
@470P_0402_50V7K
1
2
C970
0.1U_0402_10V6K
1
2
L16
CHB1608U301_0603
1 2
C211
10U_0805_6.3V6M
1
2
C198
0.1U_0402_10V6K
1
2
L19
CHB1608U301_0603
1 2
C969
0.1U_0402_10V6K
1
2
C867
0.01U_0402_16V7K
1
2
C218
10U_0805_6.3V6M
1
2
U59
MIC5205-2.8BM5_SOT23-5~D
PG 4
VOUT
5
EN 3
VIN 1
GND
2
R282
M9@0_0805_5%
1 2
C206
10U_0805_6.3V6M
1
2
L18
CHB1608U301_0603
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+2.5VS
+VGA_CORE
+VGA_CORE
+VGA_CORE
+VGA_CORE_CI
+VGA_CORE_CI
+2.5VS
+VGA_CORE
+1.2VS_VGA
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
ATI M10-P/M9+X POWER-B
21 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
As close as ppossible to related pin
(20 mil)
POWER
INTERFACE
As close as ppossible to related pin
480MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(12A,480mils ,Via NO.=24)
+
C221
47U_D2_6.3VM
1
2
C239
0.01U_0402_16V7K
1
2
C230
0.01U_0402_16V7K
1
2
C238
0.01U_0402_16V7K
1
2
C236
0.1U_0402_10V6K
1
2
CORE POWER
M10-P/(M9+X)
(5/6)
U6E
SA002160E00(0301021300)
VSS
A10
VSS
A16
VSS
A2
VSS
A22
VSS
A29
VSS
AA30
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC4
VSS
AD12
VSS
AD16
VSS
AD18
VSS
AD25
VSS
AD30
VSS
AE27
VSS
AG11
VSS
AG15
VSS
AG18
VSS
AG22
VSS
AG27
VSS
AG5
VSS
AG9
VSS
AJ1
VSS
AJ30
VSS
AK2
VSS
AK29
VSS
C1
VSS
C28
VSS
C3
VSS
C30
VSS
D10
VSS
D12
VSS
D15
VSS
D18
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D4
VSS
D6
VSS
D9
VSS
E4
VSS
F27
VSS G12
VSS G16
VSS H4
VSS H8
VSS H9
VSS H12
VSS H14
VSS H18
VSS H21
VSS H23
VSS H27
VSS K1
VSS K23
VSS K24
VSS K27
VSS K30
VSS K7
VSS K8
VSS L4
VSS M30
VSS M7
VSS M8
VSS N23
VSS N24
VSS N27
VSS P4
VSS R23
VSS R24
VSS R30
VSS R7
VSS R8
VSS T1
VSS T27
VSS U23
VSS U4
VSS U8
VSS V30
VSS W23
VSS W24
VSS W27
VSS W7
VSS W8
VSS Y4
VSS G9
VSS G24
VSS G21
VSS G18
C248
0.1U_0402_10V6K
1
2
C245
0.1U_0402_10V6K
1
2
C227
0.1U_0402_10V6K
1
2
L22
CHB1608U301
1 2
JOPEN5
PAD-OPEN 4x4m
1 2
C237
0.1U_0402_10V6K
1
2
C229
0.01U_0402_16V7K
1
2
C250
0.01U_0402_16V7K
1
2
CORE POWER
M10-P/(M9+X)
(6/6)
M10-P&M9+X
COMMON
M10-P
ONLY
M9+X
ONLY
U6F
SA002160E00(0301021300)
VDDC AD15
VDDC AD13
VDDC AC17
VDDC AC15
VDDC AC13
VDDC
M12
VDDC
M13
VDDC
M14
VDDC
M17
VDDC
M18
VDDC
M19
VDDC
N12
VDDC
N13
VDDC
N14
VDDC
N17
VDDC
N18
VDDC
N19
VDDC
P12
VDDC
P13
VDDC
P14
VDDC
P17
VDDC
P18
VDDC
P19
VDDC
U12
VDDC
U13
VDDC
U14
VDDC
U17
VDDC
U18
VDDC
U19
VDDC
V12
VDDC
V13
VDDC
V14
VDDC
V17
VDDC
V18
VDDC
V19
VDDC
W12
VDDC
W13
VDDC
W14
VDDC
W17
VDDC
W18
VDDC
W19
VDDCI T12
VDDCI M15
VDDCI W16
VDDCI R19
VSS R12
VSS R13
VSS T13
VSS R14
VSS T14
VSS N15
VSS P15
VSS R15
VSS T15
VSS U15
VSS V15
VSS W15
VSS H16
VSS M16
VSS N16
VSS P16
VSS R16
VSS T16
VSS U16
VSS V16
VSS R17
VSS T17
VSS R18
VSS T18
VSS T19
VDDC
AB22
VDDC
AB9
VDDC
J10
VDDC
J12
VDDC
J14
VDDC
J15
VDDC
J16
VDDC
J17
VDDC
J19
VDDC
J21
VDDC
K22
VDDC
K9
VDDC
M22
VDDC
M9
VDDC
P22
VDDC
P9
VDDC
R22
VDDC
R9
VDDC
T22
VDDC
T9
VDDC
U22
VDDC
U9
VDDC
V22
VDDC
V9
VDDC
Y22
VDDC
Y9
VSS AA22
VSS AA9
VSS J11
VSS J13
VSS J18
VSS J20
VSS J22
VSS J9
VSS L22
VSS L9
VSS N22
VSS N9
VSS W22
VSS W9
C244
0.1U_0402_10V6K
1
2
C235
0.1U_0402_10V6K
1
2
C234
0.1U_0402_10V6K
1
2
C228
0.1U_0402_10V6K
1
2
C246
0.1U_0402_10V6K
1
2
C247
0.1U_0402_10V6K
1
2
C242
0.1U_0402_10V6K
1
2
C231
0.01U_0402_16V7K
1
2
C223
22U_1206_10V4Z
1
2
C232
22U_1206_10V4Z
1
2
C243
22U_1206_10V4Z
1
2
C224
22U_1206_10V4Z
1
2
C225
0.1U_0402_10V6K
1
2
C240
10U_0805_6.3V6M
1
2
+
C222
150U_D2_6.3VM
1
2
C241
0.1U_0402_10V6K
1
2
C233
0.1U_0402_10V6K
1
2
C249
0.01U_0402_16V7K
1
2
C226
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDA30
NMDA7
NDQSA3
NDQMA3
NMAA2 NMDA52
NMDA17
NMCLKA1#
NDQMA7
NMRASA#
NMDA43
NMAA5 NMDA49
NDQSA4
NMDA56
VREF_2
NDQMA5
NMDA21
NMDA61
NMDA41
NMDA10
NMAA5
NMDA34
NMAA12
NMAA10
NMWEA#
NMDA[0..63]
NMDA38
NMCSA0#
NMAA8
NMAA6
NMAA1
NMDA19
NMDA22
NMAA9
NMAA7
NMDA1
NMDA44
NMCLKA1
NMDA57
NMDA4
NMDA50
NDQMA1
NMAA13
NMDA13
NMAA13
NMAA7
NMDA42
NMDA2
NMAA4
NMDA29
NDQSA1
NMDA14
NMAA12
NMDA53
NMAA3
NMDA62
NMDA28
NMAA1
NMAA2
NMDA35
NMCKEA
NMDA3
NDQMA2
NMDA54
NMRASA#
NMDA51
NDQSA[0..7]
NMAA8
NMDA45
NMDA47
NMDA39
NMAA4
NMDA24
NMDA15
NMCSA0#
NMDA25
NMAA11
NMDA36
NMDA6
NMDA9
NDQSA5
NDQSA7
NMDA31
NMDA27
NMDA16
NMCASA#
NMAA0
NMDA26
NDQSA0
NMCKEA
NMCASA#
NMAA0
NMDA18
NMDA55
NMDA37
NMDA46
NMDA32
NDQMA0
NMCLKA0
NMDA11
NMDA59
NMDA23
NMDA0
VREF_1
NMAA[0..13]
NMAA11
NDQSA6
NMAA9
NMDA40
NMDA20 NMAA3
NMDA8 NMWEA#
NMAA6
NMDA33
NDQMA[0..7]
NDQSA2
NMDA58
NMDA5
NMDA48
NMDA63
NDQMA4
NMDA12
NMAA10
NDQMA6
NMDA60
NMCLKA0#
NMCSA1#
NMCSA1#
NMCLKA1#<18>
NMCLKA1<18>
NDQSA[0..7]<18>
NMCSA0#<18> NMWEA#<18>
NMCLKA0<18>
NDQMA[0..7]<18>
NMAA[0..13]<18>
NMCKEA<18>
NMDA[0..63]<18>
NMRASA#<18>
NMCLKA0#<18>
NMCASA#<18>
NMCSA1#<18>
+2.5VS+2.5VS
+2.5VS+2.5VS
+2.5VS +2.5VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
VGA DDR FOR CHANNEL A
22 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
(25mil)
VGA DDR FOR CHANNEL A
As close as ppossible to related pin
(25mil)
As close as ppossible to related pin
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C506
0.1U_0402_10V6K
1
2
C504
10U_0805_10V3M
1
2
C512
0.1U_0402_10V6K
1
2
C1126
0.1U_0402_10V6K
1
2
U28
K4D263238A-GC
DQ0 B7
DQ1 C6
DQ2 B6
DQ3 B5
DQ4 C2
DQ5 D3
DQ6 D2
DQ7 E2
DQ8 K13
DQ9 K12
DQ10 J13
DQ11 J12
DQ12 G13
DQ13 G12
DQ14 F13
DQ15 F12
DQ16 F3
DQ17 F2
DQ18 G3
DQ19 G2
DQ20 J3
DQ21 J2
DQ22 K2
DQ23 K3
DQ24 E13
DQ25 D13
DQ26 D12
DQ27 C13
DQ28 B10
DQ29 B9
DQ30 C9
DQ31 B8
A0
N5
A1
N6
A2
M6
A3
N7
A4
N8
A5
M9
A6
N9
A7
N10
A8/AP
N11
A9
M8
A10
L6
A11
M7
BA0
N4
BA1
M5
DM0
B3
DM1
H12
DM2
H3
DM3
B12
DQS0
B2
DQS1
H13
DQS2
H2
DQS3
B13
VREF
N13
MCL
M13
RFU1
L9
RFU2
M10
RAS#
M2
CAS#
L2
WE#
L3
CS#
N2
CKE
N12
CK
M11
CK#
M12
VDD D7
VDD D8
VDD E4
VDD E11
VDD L4
VDD L7
VDD L8
VDD L11
VDDQ C3
VDDQ C5
VDDQ C7
VDDQ C8
VDDQ C10
VDDQ C12
VDDQ E3
VDDQ E12
VDDQ F4
VDDQ F11
VDDQ G4
VDDQ G11
VDDQ J4
VDDQ J11
VDDQ K4
VDDQ K11
VSSQ B4
VSSQ B11
VSSQ D4
VSSQ D5
VSSQ D6
VSSQ D9
VSSQ D10
VSSQ D11
VSSQ E6
VSSQ E9
VSSQ F5
VSSQ F10
VSSQ G5
VSSQ G10
VSSQ H5
VSSQ H10
VSSQ J5
VSSQ J10
VSSQ K5
VSSQ K10
VSS TH
F6
VSS TH
F7
VSS TH
F8
VSS TH
F9
VSS TH
G6
VSS TH
G7
VSS TH
G8
VSS TH
G9
VSS TH
H6
VSS TH
H7
VSS TH
H8
VSS TH
H9
VSS TH
J6
VSS TH
J7
VSS TH
J8
VSS TH
J9
VSS
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
NC
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
C507
10U_0805_10V3M
1
2
R626
56.2_0402_1%
C515
0.1U_0402_10V6K
1
2
R489
1K_0402_1%
12
R488
1K_0402_1%
12
C516
0.1U_0402_10V6K
1
2
R627
56.2_0402_1%
R491
1K_0402_1%
12
U29
K4D263238A-GC
DQ0 B7
DQ1 C6
DQ2 B6
DQ3 B5
DQ4 C2
DQ5 D3
DQ6 D2
DQ7 E2
DQ8 K13
DQ9 K12
DQ10 J13
DQ11 J12
DQ12 G13
DQ13 G12
DQ14 F13
DQ15 F12
DQ16 F3
DQ17 F2
DQ18 G3
DQ19 G2
DQ20 J3
DQ21 J2
DQ22 K2
DQ23 K3
DQ24 E13
DQ25 D13
DQ26 D12
DQ27 C13
DQ28 B10
DQ29 B9
DQ30 C9
DQ31 B8
A0
N5
A1
N6
A2
M6
A3
N7
A4
N8
A5
M9
A6
N9
A7
N10
A8/AP
N11
A9
M8
A10
L6
A11
M7
BA0
N4
BA1
M5
DM0
B3
DM1
H12
DM2
H3
DM3
B12
DQS0
B2
DQS1
H13
DQS2
H2
DQS3
B13
VREF
N13
MCL
M13
RFU1
L9
RFU2
M10
RAS#
M2
CAS#
L2
WE#
L3
CS#
N2
CKE
N12
CK
M11
CK#
M12
VDD D7
VDD D8
VDD E4
VDD E11
VDD L4
VDD L7
VDD L8
VDD L11
VDDQ C3
VDDQ C5
VDDQ C7
VDDQ C8
VDDQ C10
VDDQ C12
VDDQ E3
VDDQ E12
VDDQ F4
VDDQ F11
VDDQ G4
VDDQ G11
VDDQ J4
VDDQ J11
VDDQ K4
VDDQ K11
VSSQ B4
VSSQ B11
VSSQ D4
VSSQ D5
VSSQ D6
VSSQ D9
VSSQ D10
VSSQ D11
VSSQ E6
VSSQ E9
VSSQ F5
VSSQ F10
VSSQ G5
VSSQ G10
VSSQ H5
VSSQ H10
VSSQ J5
VSSQ J10
VSSQ K5
VSSQ K10
VSS TH
F6
VSS TH
F7
VSS TH
F8
VSS TH
F9
VSS TH
G6
VSS TH
G7
VSS TH
G8
VSS TH
G9
VSS TH
H6
VSS TH
H7
VSS TH
H8
VSS TH
H9
VSS TH
J6
VSS TH
J7
VSS TH
J8
VSS TH
J9
VSS
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
NC
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
C629
10P_0402_50V8K
1
2
R490
1K_0402_1%
12
C1125
0.1U_0402_10V6K
1
2
C510
10U_0805_10V3M
1
2
C628
10P_0402_50V8K
1
2
C508
0.1U_0402_10V6K
1
2
C509
0.1U_0402_10V6K
1
2
C505
0.1U_0402_10V6K
1
2
C513
10U_0805_10V3M
1
2
C511
0.1U_0402_10V6K
1
2
C517
0.1U_0402_10V6K
1
2
R625
56.2_0402_1%
C1122
22U_1206_10V4Z
1
2
C1123
22U_1206_10V4Z
1
2
C514
0.1U_0402_10V6K
1
2
C1124
0.1U_0402_10V6K
1
2
R628
56.2_0402_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDB5
NMDB49
NDQSB3
NMAB4
NMDB8 NMDB33
VREF_4 NMDB53
NMAB8
NMAB6
NMDB25
NMAB10
NMAB11
NMDB12
NDQMB4
NMDB57
NMDB43NMAB4
NMDB40
NDQMB7
NMAB2
NMDB28
NMDB1
NMAB10
NMDB6
NMDB22NMAB9
NMDB9
NMAB6
NMAB13
NMDB34
NDQMB2
NMDB54
NMDB41
NMDB50NMDB26
NMDB13
NMDB44
NMAB12
NMDB56
NDQMB1
NDQMB5
NMDB32
NDQMB[0..7]
NMAB0
NMDB29
VREF_3
NMDB2
NDQSB1
NMDB37
NMDB7
NMCKEB
NMAB5
NMDB62
NMDB23
NMDB10
NDQSB0
NMDB55
NMAB3
NDQSB2 NMDB35
NMDB19
NMDB45
NMDB63
NMAB7
NDQMB3
NMDB30
NMAB1
NMCLKB1NMCLKB0
NMAB11
NMDB16
NMAB5
NMDB3
NMDB51
NMAB1
NMAB[0..13]
NMCASB#
NMDB59
NDQMB0
NMAB9
NMDB38
NMDB36
NMDB14
NDQSB[0..7]
NMDB31
NDQSB4
NMDB20
NMAB0 NMDB46
NMDB17
NMRASB#
NMDB39
NMAB12
NMCASB#
NMWEB#
NMDB42
NDQSB6
NMDB60
NDQSB7
NMAB2
NMDB4
NMDB48
NMRASB#
NMAB8
NMCKEB
NMDB15
NMDB21
NMDB52
NMAB7
NMDB58
NMDB24
NMAB13
NMDB61
NMDB11
NMAB3
NMDB47
NDQMB6
NMDB18
NMDB27
NMCSB0#
NMDB0
NDQSB5
NMDB[0..63]
NMCLKB0# NMCLKB1#
NMCSB1# NMCSB1#
NMWEB#
NMCSB0#
NMRASB#<19>
NMCLKB1#<19>
NMCKEB<19>
NMCSB0#<19>
NMCASB#<19>
NDQMB[0..7]<19>
NMCLKB0<19> NMCLKB1<19>
NDQSB[0..7]<19>
NMCLKB0#<19>
NMAB[0..13]<19>
NMWEB#<19>
NMDB[0..63]<19>
NMCSB1#<19>
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
VGA DDR FOR CHANNEL B
23 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
(25mil)
As close as ppossible to related pin As close as ppossible to related pin
VGA DDR FOR CHANNEL
B
(25mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C539
0.1U_0402_10V6K
1
2
C631
10P_0402_50V8K
1
2
C537
0.01U_0402_16V7K
1
2
U30
K4D263238A-GC
DQ0 B7
DQ1 C6
DQ2 B6
DQ3 B5
DQ4 C2
DQ5 D3
DQ6 D2
DQ7 E2
DQ8 K13
DQ9 K12
DQ10 J13
DQ11 J12
DQ12 G13
DQ13 G12
DQ14 F13
DQ15 F12
DQ16 F3
DQ17 F2
DQ18 G3
DQ19 G2
DQ20 J3
DQ21 J2
DQ22 K2
DQ23 K3
DQ24 E13
DQ25 D13
DQ26 D12
DQ27 C13
DQ28 B10
DQ29 B9
DQ30 C9
DQ31 B8
A0
N5
A1
N6
A2
M6
A3
N7
A4
N8
A5
M9
A6
N9
A7
N10
A8/AP
N11
A9
M8
A10
L6
A11
M7
BA0
N4
BA1
M5
DM0
B3
DM1
H12
DM2
H3
DM3
B12
DQS0
B2
DQS1
H13
DQS2
H2
DQS3
B13
VREF
N13
MCL
M13
RFU1
L9
RFU2
M10
RAS#
M2
CAS#
L2
WE#
L3
CS#
N2
CKE
N12
CK
M11
CK#
M12
VDD D7
VDD D8
VDD E4
VDD E11
VDD L4
VDD L7
VDD L8
VDD L11
VDDQ C3
VDDQ C5
VDDQ C7
VDDQ C8
VDDQ C10
VDDQ C12
VDDQ E3
VDDQ E12
VDDQ F4
VDDQ F11
VDDQ G4
VDDQ G11
VDDQ J4
VDDQ J11
VDDQ K4
VDDQ K11
VSSQ B4
VSSQ B11
VSSQ D4
VSSQ D5
VSSQ D6
VSSQ D9
VSSQ D10
VSSQ D11
VSSQ E6
VSSQ E9
VSSQ F5
VSSQ F10
VSSQ G5
VSSQ G10
VSSQ H5
VSSQ H10
VSSQ J5
VSSQ J10
VSSQ K5
VSSQ K10
VSS TH
F6
VSS TH
F7
VSS TH
F8
VSS TH
F9
VSS TH
G6
VSS TH
G7
VSS TH
G8
VSS TH
G9
VSS TH
H6
VSS TH
H7
VSS TH
H8
VSS TH
H9
VSS TH
J6
VSS TH
J7
VSS TH
J8
VSS TH
J9
VSS
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
NC
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
C529
0.1U_0402_10V6K
1
2
C535
0.1U_0402_10V6K
1
2
R632
56.2_0402_1%
C533
22U_1206_10V4Z
1
2
R494
1K_0603_1%
1 2
C532
0.01U_0402_16V7K
1
2
C538
0.1U_0402_10V6K
1
2
R629 56.2_0402_1%
C630
10P_0402_50V8K
1
2
U31
K4D263238A-GC
DQ0 B7
DQ1 C6
DQ2 B6
DQ3 B5
DQ4 C2
DQ5 D3
DQ6 D2
DQ7 E2
DQ8 K13
DQ9 K12
DQ10 J13
DQ11 J12
DQ12 G13
DQ13 G12
DQ14 F13
DQ15 F12
DQ16 F3
DQ17 F2
DQ18 G3
DQ19 G2
DQ20 J3
DQ21 J2
DQ22 K2
DQ23 K3
DQ24 E13
DQ25 D13
DQ26 D12
DQ27 C13
DQ28 B10
DQ29 B9
DQ30 C9
DQ31 B8
A0
N5
A1
N6
A2
M6
A3
N7
A4
N8
A5
M9
A6
N9
A7
N10
A8/AP
N11
A9
M8
A10
L6
A11
M7
BA0
N4
BA1
M5
DM0
B3
DM1
H12
DM2
H3
DM3
B12
DQS0
B2
DQS1
H13
DQS2
H2
DQS3
B13
VREF
N13
MCL
M13
RFU1
L9
RFU2
M10
RAS#
M2
CAS#
L2
WE#
L3
CS#
N2
CKE
N12
CK
M11
CK#
M12
VDD D7
VDD D8
VDD E4
VDD E11
VDD L4
VDD L7
VDD L8
VDD L11
VDDQ C3
VDDQ C5
VDDQ C7
VDDQ C8
VDDQ C10
VDDQ C12
VDDQ E3
VDDQ E12
VDDQ F4
VDDQ F11
VDDQ G4
VDDQ G11
VDDQ J4
VDDQ J11
VDDQ K4
VDDQ K11
VSSQ B4
VSSQ B11
VSSQ D4
VSSQ D5
VSSQ D6
VSSQ D9
VSSQ D10
VSSQ D11
VSSQ E6
VSSQ E9
VSSQ F5
VSSQ F10
VSSQ G5
VSSQ G10
VSSQ H5
VSSQ H10
VSSQ J5
VSSQ J10
VSSQ K5
VSSQ K10
VSS TH
F6
VSS TH
F7
VSS TH
F8
VSS TH
F9
VSS TH
G6
VSS TH
G7
VSS TH
G8
VSS TH
G9
VSS TH
H6
VSS TH
H7
VSS TH
H8
VSS TH
H9
VSS TH
J6
VSS TH
J7
VSS TH
J8
VSS TH
J9
VSS
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
NC
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
C519
0.1U_0402_10V6K
1
2
C520
0.1U_0402_10V6K
1
2
C528
22U_1206_10V4Z
1
2
C525
0.1U_0402_10V6K
1
2
R630 56.2_0402_1%
C534
0.1U_0402_10V6K
1
2
C524
0.1U_0402_10V6K
1
2
C522
0.01U_0402_16V7K
1
2
R497
1K_0603_1%
1 2
C527
0.01U_0402_16V7K
1
2
R495
1K_0603_1%
1 2
C530
0.1U_0402_10V6K
1
2
R631
56.2_0402_1%
R496
1K_0603_1%
1 2
C531
0.01U_0402_16V7K
1
2
C523
22U_1206_10V4Z
1
2
C521
0.01U_0402_16V7K
1
2
C526
0.01U_0402_16V7K
1
2
C536
0.01U_0402_16V7K
1
2
C518
22U_1206_10V4Z
1
2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CLK_BCLK#
MEM_66M
CLK_48M AGP_66M
FS3
+3V_VDD
CLK_BCLK
CLK_NB#
CLK_NB
SMB_CK_DAT2
SMB_CK_CLK2
CLK_IREF
PCI33/66#
FS1
FS2
FS3
PCI33/66#
CLK_BCLK
CLK_BCLK#
AGP_EXT_66M
FS4
FS0
FS4
XTALIN_CLK
XTALOUT_CLK
24/48#
CLK_SD
FS2
CK_BCLK
CK_BCLK#
FS1
FS0
VSSA
CLK_NB_BCLK <11>
CLK_NB_BCLK# <11>
CK_BCLK <4>
CK_BCLK# <4>
CLK_MEM_66M <11>
CLK_ALINK_SB <26>
CK_ITP <5>
CK_ITP# <5>
CLK_SD_48M<31>
SMB_CK_DAT2<14,15,27> SMB_CK_CLK2<14,15,27>
CLK_AGP_66M <11>
CLK_AGP_EXT_66M <17>
VTT_PWRGD<27,46>
CLK_14M_SIO<38> CLK_SB_14M<27>
REFCLK1_NB<11>
BSEL0<5,13>
BSEL1<5,13>
CLK_14M_CODEC<36>
CLK_SB_48M<27>
+3VS
+3VS
+3V_CLK
+3V_CLK
+3VS
+3V_CLK
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
Clock Generator
24 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Width=40 mils
133
0 0 0 1 0
PCI33/66# = HIGH
FS2 MEMFS1
200
FS3
200
A-LINK FREQ
Note: 0 = PULL LOW
1 = PULL HIGH
66MHZ
PCI33/66# = LOW 33MHZ
CLOCK FREQUENCY SELECT TABLE
FS0
133
CPUFS4 With Spread Enabled…
0 0 0 0 1
*
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0 0 0 0 0
100 100
Spreaf OFF OR
Center spread +/-0.3%
L12
CHB2012U121_0805
1 2
R224
4.7K_0402_5%
12
R196 49.9_0402_1%
1 2
R228
@10K_0402_5%
12
R202 49.9_0402_1%
1 2
R201 33_0402_1%
1 2
C127 2.2P_0402_50V8C
1 2
R213 33_0402_1%
1 2
R219
10K_0402_5%
12
C120
0.1U_0402_10V6K
1
2
R1068 33_0402_1%
1 2
C124
0.1U_0402_10V6K
1
2
R996 68_0402_5%
1 2
R215 33_0402_1%
1 2
R210 M9_M10@33_0402_1%
1 2
R1056 10K_0402_5%
1 2
R197 49.9_0402_1%
1 2
C130 2.2P_0402_50V8C
1 2
C125
0.1U_0402_10V6K
1
2
R221
@10K_0402_5%
12
R998
10K_0402_5%
12
C123
0.1U_0402_10V6K
1
2
R962 10K_0402_5%
1 2
C122
0.1U_0402_10V6K
1
2
U5
ICS951402AGT_TSSOP48
XIN
6
XOUT
7
VDDREF 1
FS0/REF0
2FS1/REF1
3FS2/REF2
4
GNDREF
5GNDXTAL
8
VDDXTAL 9
PCI33/66#SEL
11
PCI_STOP#
12
VDDPCI 13
FS3/PCICLK_F0 14
FS4/PCICLK_F1 15
GNDPCI
18
VDDPCI 19
GNDPCI
24
VDDSD 48
SDRAMOUT 47
GNDSD
46
CPU_STP#
45
CPUT1 44
CPUC1 43
VDDCPU 42
GNDCPU
41
CPUC0 39
CPUT0 40
IREF
38
VSSA 37
VDDA 36
SCLK
35
SDATA
34
VTTPWRGD/PD#
10
AGPCLK0 32
VDDAGP 30
AGPCLK1 31
VDD48M 29
48MHz_0
28
24/48#SEL
26
GND48M
25
48MHz_1
27
GNDAGP
33
PCICLK0 16
PCICLK1 17
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
R226
10K_0402_5%
12
R963
@1M_0402_5%
12
R997 33_0402_1%
1 2
R193 @0_0402_5%
R204 33_0402_1%
1 2
R227
10K_0402_5%
12
C118
10U_0805_6.3V6M
1
2
R223
10K_0402_5%
12
R195 33_0402_1%
1 2
R203 49.9_0402_1%
1 2
D83 RB751V_SOD323
21
C126
0.1U_0402_10V6K
1
2
R999
4.7K_0402_5%
12
Y2
14.318MHZ
12
C119
0.1U_0402_10V6K
1
2
R225
10K_0402_5%
12
R194 @0_0402_5%
R206 @33_0402_1%
1 2
D84 RB751V_SOD323
21
R1111 10K_0402_5%
1 2
R220
@10K_0402_5%
12
R200 33_0402_1%
1 2
R218
475_0402_1%
1 2
L11
HB-1M2012-121JT03_0805
1 2
R205 33_0402_1%
1 2
C128
0.1U_0402_10V6K
1
2
R208 33_0402_1%
1 2
C121
0.1U_0402_10V6K
1
2
R222
@10K_0402_5%
12
C129
10U_0805_6.3V6M
1
2
R207 33_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_G
CRT_R
CRT_B
DISPOFF#
CRTL_G
CRTL_B
CRTL_R
CRT_VCC
TXB1-
TXA1- TXB0+
TXACLK+
TXB2-
TXACLK-
TXB0-
LCDVDD_A
TXA2-
TXBCLK+
TXB1+
TXA0+
TXB2+ TXBCLK-
TXA1+
TXA2+
TXA0-
TXB2+_NB
TXB0+_NB
TXBCLK+_NB
TXBCLK-_NB
TXB1-_NB
TXB0-_NB
TXA2+_NB
TXB2-_NB
TXA0-_NB
TXB1+_NB
TXACLK-_NB
TXA2-_NB
TXA1+_NB
TXA1-_NB
TXA0+_NB
TXACLK+_NB
DISPOFF#
DAC_BRIG
INVT_PWM
DISPOFF#
DDC_CLK
DDC_DAT
DDC_CLK
DDC_DAT
ENAVDD
LCDVDD_A
CRT_HSYNCRFL
CRT_VSYNCRFL
CRT_HSYNC
CRT_VSYNC
3VDDCDA
3VDDCCL
3VDDCCL
3VDDCDA
CRT_R<11,17>
CRT_G<11,17>
CRT_B<11,17>
3VDDCDA<11,17>
3VDDCCL<11,17>
BKOFF#<44>
ENAVDD<10,17>
TXA1-<17> TXA1+<17>
TXA0-<17>
TXB0+ <17>
TXBCLK- <17>
TXA2+<17>
TXB1+<17> TXB1-<17>
TXBCLK+ <17>
TXA2-<17>
TXB2+<17> TXB2-<17>
TXA0+<17>
TXB0- <17>
TXACLK-<17> TXACLK+<17>
TXA0+_NB<11>
TXA2-_NB<11>
TXB1-_NB<11>
TXA1-_NB<11>
TXB1+_NB<11>
TXACLK-_NB<11>
TXB0-_NB <11>
TXBCLK-_NB <11>
TXA2+_NB<11>
TXB2-_NB<11> TXBCLK+_NB <11>
TXB0+_NB <11>
TXB2+_NB<11>
TXACLK+_NB<11>
TXA0-_NB<11>
TXA1+_NB<11>
INVT_PWM <44>
DAC_BRIG <44>
DDC_DAT <10,17>
DDC_CLK <10,17>
CRT_HSYNC<11,17>
CRT_VSYNC<11,17>
+3VS
+3VS
R_CRT_VCC
+5VS CRT_VCC
INVPWR_B+
+12VALW+5VS
+3VS
LCDVDD
+12VALW
LCDVDD
+3VS
+12VALW
B+
+5VS
LCDVDD
INVPWR_B+
INVPWR_B+
+3VS
+3VS
+3VS
CRT_VCC
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
LCD,CRT,TV-OUT & Inverter BD CONN.
Custom 25 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
LCD CONN
CRT CONNECTOR
SI2302DS: N CHANNEL
VGS: 4.5V, RDS: 85 mOHM
VGS: 2.5V, RDS: 115mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V
SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V
AT LEAST 60 MIL
AT LEAST 60 MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
For M9/M110P/M11P
For internal AGP
D43
DAN217_SOT23
2
3
1
C117
220P_0402_25V8K
1
2
C108
10P_0402_50V8K
1
2
C89
0.047U_0402_16V4Z
1
2
D21
DAN217_SOT23
2
31
R185
75_0402_5%
1 2
G
D
S
Q13
2N7002 1N_SOT23
2
1 3
C101
10P_0402_50V8K
1
2
R191
4.7K_0402_5%
C87
0.1U_0402_10V6K
1
2C90
0.1U_0402_10V6K
1
2
D23
DAN217_SOT23
2
31
L38
KC FBM-L11-201209-221LMAT_0805
1 2
C618
10U_0805_10V3M
1
2
G
D
S
Q14
2N7002 1N_SOT23
2
1 3
F1
FUSE_1A
21
R187
75_0402_5%
1 2
R1153 20_0402_5%
1 2
L5 FCM2012C-800_0805
1 2
C620
0.01U_0402_50V7K
1
2
R175
100K_0402_5%
R1007
2.2K_0402_5%
1 2
D16 RB751V_SOD323
21
C116
220P_0402_25V8K
1
2
D17
RB411D_SOT23
2 1
R182
100K_0402_5%
L9
FBM-L10-160808-300LM-T
1 2
C91
4.7U_0805_10V4Z
1
2
R1118
4.7K_0402_5%
JP6
SUYIN_7849S-15G2T-HC
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
D
S
Q10
2N7002_SOT23
2
13
R180
1K_0402_1%
12
C100
10P_0402_50V8K
1
2
L6 FCM2012C-800_0805
1 2
C102
10P_0402_50V8K
1
2
C993
27P_0402_50V8J
1
2
G
D
S
Q11
2N7002_SOT23
2
13
C104
22P_0402_25V8K
1
2
C619
1000P_0402_50V8J
1
2
R1154 20_0402_5%
1 2
R192
4.7K_0402_5%
U58
74AHCT1G125GW
2 4
1
35
C86
4.7U_0805_10V4Z
1
2
C97
0.1U_0402_10V6K
1
2
R1008
2.2K_0402_5%
1 2
C109
10P_0402_50V8K
1
2
R1117
4.7K_0402_5%
R174
4.7K_0402_5%
12
R181
150K_0402_5%
D22
DAN217_SOT23
2
31
L2
KC FBM-L11-201209-221LMAT_0805
1 2
L41
KC FBM-L11-201209-221LMAT_0805
1 2
R186
75_0402_5%
1 2
C103
22P_0402_25V8K
1
2
C994
27P_0402_50V8J
1
2
L10
FBM-L10-160808-300LM-T
1 2
D42
DAN217_SOT23
2
3
1
L3 FCM2012C-800_0805
1 2
G
D
S
Q9
SI2302DS 1N_SOT23
2
13
C105
22P_0402_25V8K
1
2
U57 74AHCT1G125GW
2 4
1
35
22K
22K
Q12
DTC124EK_SOT23
2
13
JP27
M9-M10@JST BM40B-SRDS
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
C88
0.1U_0402_10V6K
1
2
R1115
1.2K_0402_5%
12
JP28
NAGP@JST BM40B-SRDS
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
C997
220P_0402_50V7K
1
2
R1150
1K_0402
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
PCI_FRAME#
PCI_PAR
PCI_SERR#
PCI_TRDY#
PCI_STOP#
PCI_IRDY#
PCI_PERR#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_REQ#3
PCI_GNT#2
PCI_REQ#1
PCI_GNT#4
PCI_GNT#0
PCI_REQ#4
PCI_GNT#1
PCI_REQ#0
PCI_REQ#2
PCI_GNT#3
LPC_AD3
LPC_AD2
LPC_AD1
LPC_DRQ#0
LPC_AD0
CLK_ALINK_SB
H_CPUSLP#
H_SMI#
H_A20M#
H_INTR
H_IGNNE#
H_NMI
H_STPCLK#
H_NMI
H_INTR
LPC_FRAME#
LPC_DRQ#1
SIRQ
PCI_CLKRUN#
H_INIT#
H_INIT#
PCI_RST#
NBRST# NB_RST#
CPURSTIN#
OVCUR#5
H_A20M#
A_SERR#
PCI_CLK_R
PCI_AD4
PCI_CBE#3
A_SBREQ#
A_CBE#0
A_AD19
LPC_DRQ#1
PCI_AD25
PCI_AD21
PCI_AD16
PCI_AD12
PCI_AD0
LPC_FRAME#
PCI_CBE#2
PCI_MINI
PCI_PIRQC#
A_OFF#
A_AD29
A_AD21
A_AD5
H_CPUFERR#
PCI_AD26
H_A20M#
RTCX2
A_CBE#2
A_AD30
A_AD8
A_AD0
GPIO0
PCI_REQ#4
PCI_AD31
PCI_AD20
PCI_AD13
PCI_AD10
PCI_AD5
LPC_AD1
PCI_IRDY#
H_CPUFERR#
A_ACAT#
A_AD26
PCI_AD17
PCI_LAN
SBCLK_STP#
A_AD16
PCI_AD18
PCI_AD8
PCI_AD7
PCI_AD2
PCI_SIO
A_PAR
A_AD22
A_AD14
PCI_GNT#4
PCI_AD24
PCI_GNT#2
PCI_REQ#2
SB_APIC_D0 OVCUR#5
A_STROBE#
A_AD28
NBRST#
CLK_ALINK_SB
PCI_AD28
PCI_AD15
PCI_AD9
SIRQ
LPC_AD3
LPC_AD2
PCI_PERR#
PCI_CBE#1
PCI_PIRQA#
A_AD25
PCI_AD3
LPC_AD0
PCI_PCM
A_AD18
PCI_AD22
LPC_DRQ#0
PCI_STOP#
PCI_CBE#0
PCI_1394
PCICLK_STP#
A_DEVSEL#
A_AD20
A_AD13
A_AD12
PCI_AD19
PCI_GNT#1
PCI_AD11
PCI_GNT#3
A_AD15
PCI_AD27
PCI_FRAME#
RTCX1
A_SERR#
A_AD27
A_AD17
PCI_AD[0..31]
PCIRST#
PCI_AD1
PCI_DEVSEL#
A_END#
A_AD23
A_AD9
A_AD7
A_AD1
PCI_CBE#[0..3]
PCI_AD30
PCI_AD6
PCI_EC
PCI_GNT#0
PCI_REQ#3
PCI_TRDY#
OVCUR#4
A_CBE#1
A_AD31
A_AD10
A_AD2
PCI_AD23
PCI_REQ#1
SB_APIC_D1
CPURSTIN#
A_SBGNT#
A_CBE#3
A_AD11
PCI_AD29
PCI_AD14
PCI_CLKRUN#
PCI_SERR#
PCI_REQ#0
PCI_PAR
PCI_PIRQD#
A_AD24
A_AD6
A_AD3
OVCUR#3
A_AD4 PCI_CLK_FB
PCIRST#
PCI_PIRQB#
GPIO1
OVCUR#4
GPIO0
PCI_DEVSEL#
SBCLK_STP#
H_PWRGOOD
H_CPUSLP#
H_SMI#
H_STPCLK#
H_IGNNE#
RTCX1RTCX2
+RTCBATT
OVCUR#3
A_SBREQ#<10>
A_AD[0..31]<10,13>
A_CBE#[0..3]<10,13>
A_STROBE#<10>
A_SBGNT#<10>
A_DEVSEL#<10> A_ACAT#<10> A_END#<10> A_PAR<10,13>
PCI_PIRQA#<10,17,31,34>
H_STPCLK#<5>
H_PWRGOOD<5>
H_A20M#<5>H_IGNNE#<5>
H_INIT#<5>
PCI_CBE#[0..3] <31,33,34,41>
PCI_AD[0..31] <29,31,33,34,41>
H_INTR<5>
H_FERR#<5>
PCI_RST# <11,30,31,33,34,38,41,44>
NB_RST# <8,17>
DPRSLPVR<54>
H_RESET#<5,8>
PCI_PIRQC#<41> PCI_PIRQD#<33,41>
CLK_PCI_1394 <34>
CLK_PCI_SIO <38>
CLK_PCI_EC <44>
CLK_PCI_MINI <41>
CLK_PCI_PCM <31>
CLK_PCI_LAN <33>
CPUCLK_STP#<5,11,54>
PCI_GNT#2 <31>
PCI_GNT#1 <33>
PCI_PERR# <31,33,34,41>
LPC_AD0 <38,44>
PCI_GNT#4 <41>
PCI_REQ#0 <34>
LPC_DRQ#1 <38>
LPC_AD2 <38,44>
PCI_PIRQB#<31>
CLK_ALINK_SB<24>
PCI_REQ#2 <31>
H_NMI<5>
PCI_SERR# <31,33,41>
PCI_STOP# <31,33,34,41>
LPC_FRAME# <38,44>
PCI_REQ#4 <41>
H_SMI#<5>
LPC_AD1 <38,44>
PCI_GNT#0 <34>
PCI_FRAME# <31,33,34,41>
PCI_CLKRUN# <33,38,41,44>
PCI_DEVSEL# <31,33,34,41>
H_CPUSLP#<5>
PCI_GNT#3 <41>
SIRQ <31,38,44>
PCI_IRDY# <31,33,34,41>
PCI_REQ#1 <33>
A_OFF#<10>
PCI_PAR <31,33,34,41>
PCI_TRDY# <31,33,34,41>
LPC_AD3 <38,44>
PCI_REQ#3 <41>
OVCUR#3 <35>
+VCC_CORE
+3VS
+3VS
+3V
+3VALW +3VALW
+3VALW
+VCC_CORE
+VCC_CORE
+3VS
+3VS
+3VS
+3VS
+RTCVCC
CHGRTC
+RTCBATT
+SB_VBAT
+SB_VBAT
+3V
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
SB200M(1/4)- PCI/CPU/LPC
26 65, 15, 2004
星期四 七月
Compal Electronics, Inc.
Layout note:
Trace length of PCI_CLK_R + PCI_CLK_FB should
be less than 200 mils.
PULL DOWN FOR S3
PLACE CLOSE TO CPU SOCKET
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
**
-+
RTC Battery
W=20mils
Place J1 close
to DDR-SODIMM
No short
RP17
8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
C1066 220P_0402_50V7K
12
R152 200_0402_5%
1 2
R124 39_0402_5%
1 2
R1155 10K_0402_5%
12
R154 200_0402_5%
1 2
BATT1
RTCBATT
12
C872
0.1U_0402_10V6K
1
2
U45F
SN74LVC14APWLE_TSSOP14
O12
I
13
P14
G
7
R126 39_0402_5%
1 2
RP138
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R150 200_0402_5%
1 2
R1067 1K_0402_1%
1 2
Y1
32.768KHZ_12.5P_1TJS125DJ2A073
OUT 4
IN 1
NC
3
NC
2
R1151
10K_0402_5% 12
R1000
@470_0402_5%
12
R125 8.2K_0402_5%
C76 @22P_0402_50V8J
1 2
R138
8.2K_0402_5%
JOPEN1
1 2
D93
BAS40-04_SOT23
1
2
3
R1059 10K_0402_5%
1 2
R149 200_0402_5%
1 2
R40
1K_0402_5%
12
Q5 MMBT3904_SOT23
2
3 1
C78 220P_0402_50V7K
12
R132
470_0402_5%
12
RP14
8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
C1068 220P_0402_50V7K
12
R131
330_0402_5%
RP15
8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
R127 39_0402_5%
1 2
U45E
SN74LVC14APWLE_TSSOP14
O10
I
11
P14
G
7
R134
10_0402_5%
12
R1157 10K_0402_5%
12
R172
@20M_0603_5%
12
Q98 @MMBT3904_SOT23
2
3 1
R128 39_0402_5%
1 2
RP18
8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
R130 39_0402_5%
1 2
RP21
100K_1206_8P4R_5%
1 8
2 7
3 6
4 5
U45D
SN74LVC14APWLE_TSSOP14
O8
I
9
P14
G
7
C79 220P_0402_50V7K
12
R146
4.7K_0402_5% 12
C82
12P_0402_50V8J
1
2
C1065 220P_0402_50V7K
12
C617 220P_0402_50V7K
12
R122 39_0402_5%
1 2
R921
4.7K_0402_5%
12
R169
330_0402_5%
R137
8.2K_0402_5%
C77
15P_0402_50V8J
R1064 10K_0402_5%
1 2
R1002 47K_0402_5%
1 2
R1298
220_0805_5%
1 2
R168 220_0805_5%
1 2
R171 20M_0603_5%
1 2
R158 200_0402_5%
1 2
C1064 220P_0402_50V7K
12
C956 220P_0402_50V7K
12
R946 8.2K_0402_5%
R153 200_0402_5%
1 2
RP16
8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
R156 200_0402_5%
1 2
C81
12P_0402_50V8J
1
2
C1067 220P_0402_50V7K
12
C1128
0.1U_0402_16V4Z
1
2
R123 39_0402_5%
1 2
R151 200_0402_5%
1 2
R1300 10K_0402_5%
12
C80
1U_0603_10V4Z
1
2
A-LINK INTERFACE
Part 1 of 3
SB200 SB
PCI INTERFACE
LPC
RTC
CPU XTAL
PCI CLKS
U3A
South bridge SB200
PCICLKF
B22
A_RST#
R22
A_AD0
H22
A_AD1
P23
A_AD2
L23
A_AD3
N23
A_AD4
N22
A_AD5
M23
A_AD6
M22
A_AD7
K22
A_AD8
M21
A_AD9
M20
A_AD10
L21
A_AD11
K21
A_AD12
L20
A_AD13
N21
A_AD14
K23
A_AD15
K20
A_AD16
F23
A_AD17
G21
A_AD18
F20
A_AD19
H21
A_AD20
F22
A_AD21
F21
A_AD22
G20
A_AD23
E21
A_AD24
E20
A_AD25
D23
A_AD26
D22
A_AD27
E22
A_AD28
D20
A_AD29
C23
A_AD30
D21
A_AD31
C22
A_CBE#0
L22
A_CBE#1
J23
A_CBE#2
G22
A_CBE#3
E23
A_STROBE#
H20
A_DEVSEL#
J21
A_ACAT#
G23
A_END#
H23
A_PAR
J20
A_OFF#
J22
A_SERR#
P22
PCI_STP#
R23
A_SBREQ#
B21
A_SBGNT#
B20
CPU_STP#/DPSLP#
N20
A_INTA#
C20
INTB#
P20
INTC#
B23
INTD#
P21
RTC_CS#/USBOC3#/GPIO2 AC8
RTC_ALE/USBOC4#/GPIO3 AB7
RTC_WR#/RTC_CLKOUT AB8
USBOC5#/GPM1 AA2
X1
AC12
X2
AC11
VBAT AC10
INTR/LINT0
B17
SMI#
C16
STPCLK#
E16
NMI/LINT1
B16
FERR#
E19
IGNNE#
D17
A20M#
D18
SLP#
F19
INIT
C17
CPURSTIN#
B18
APIC_D0
C19
APIC_D1
C18
APIC_CLK
B19
GPIO1/ROMCS# AB5
PCICLK0 B15
PCICLK1 D16
PCICLK2 A14
PCICLK3 A15
PCIRST# C15
CBE#0/ROMA10 B3
CBE#1/ROMA1 C5
CBE#2/ROMWE# A7
CBE#3/RTC_RD# D10
FRAME# B7
DEVSEL#/ROMA0 A6
IRDY# C7
TRDY#/ROMOE# D7
PAR A5
STOP# B6
PERR# C6
REQ#0 B12
REQ#1 C12
REQ#2 D13
REQ#3/PDMAREQ0# A12
GNT#0 A13
GNT#1 B13
GNT#2 C14
GNT#3/PDMAGNT0# D14
SERR# D6
CLKRUN# A20
LAD0 Y14
LAD1 AA14
LAD2 AB14
LAD3 AA13
LFRAME# AB13
LDRQ#0 AC14
SERIRQ AC13
RTC_GND AB11
PCICLK4 A16
PCICLK5 A17
PCICLK6 D15
AD0/ROMA18 B1
AD1/ROMA17 C1
AD2/ROMA16 A1
AD3/ROMA15 D2
AD4/ROMA14 B2
AD5/ROMA13 C2
AD6/ROMA12 A2
AD7/ROMA11 D3
AD8/ROMA9 C3
AD9/ROMA8 A3
AD10/ROMA7 D4
AD12/ROMA5 C4
AD13/ROMA4 A4
AD14/ROMA3 D5
AD15/ROMA2 B5
AD16/ROMD0 C8
AD17/ROMD1 D8
AD18/ROMD2 B8
AD19/ROMD3 A8
AD20/ROMD4 C9
AD21/ROMD5 D9
AD22/ROMD6 B9
AD23/ROMD7 A9
AD24/RTC_AD7 C10
AD25/RTC_AD6 B10
AD26/RTC_AD5 D11
AD27/RTC_AD4 A10
AD28/RTC_AD3 C11
AD29/RTC_AD2 B11
AD30/RTC_AD1 D12
AD31/RTC_AD0 A11
AD11/ROMA6 B4
REQ#4/PLLBP33/PDMAREQ1# C13
GNT#4/PLLBP50/PDMAGNT1# B14
LDRQ#1 Y13
SSMUXSEL/GPIO0
E17
DPRSLPVR
E18
PCICLK7 A18
PCICLK_FB A19
CPU_PWRGD
E4
R966
10K_0402_5%
12
R1001
47K_0402_5%
1 2
U45B
SN74LVC14APWLE_TSSOP14
O4
I
3
P14
G
7
R1065 10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_SMI#
AC97_SDOUT_R
AC97_RST#
AC97_SDIN0
OSCLIN
AC97_BITCLK
AC97_SYNC_R
SB_EC_SWI#
SB_AC_IN
SB_SCI#
USB_RCOMP
SUS_STAT#
SB_EC_SMI#
OVCUR#0
SB_TEST1
SB_PM_BATLOW#
SB_PWRGD
SLP_S5#
SLP_S3#
PWRBTN_OUT#
SB_TEST0
SB_LID_OUT#
OVCUR#1
USB20P5-
PWR_STRP
AC97_SDIN1
AC97_SDIN0
AC97_RST#
PCI_ACT_REQ#
LPC_PME#
SB_GA20
SB_KBRST#
LPC_SMI#
SB_EC_SWI#
IDESAA0
IDESAA1
IDESAA2
IDEIORDYA
IDEIRQA
IDEDA7
IDEDA13
IDEDA9
IDEDA0
IDEDA1
IDEDA15
IDEDA14
IDEDA8
IDEDA4
IDEDA5
IDEDA6
IDEDA12
IDEDA10
IDEDA11
IDEDA2
IDEDA3
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3
IDEREQB
IDEDACK#B
IDESAB1
IDEIRQB
IDEIORDYB
IDESAB0
IDEIOR#B
IDECS#B3
IDEIOW#B
IDECS#B1
IDESAB2
IDEDB0
IDEDB1
IDEDB2
IDEDB3
IDEDB7
IDEDB4
IDEDB5
IDEDB6
IDEDB11
IDEDB8
IDEDB9
IDEDB10
IDEDB15
IDEDB12
IDEDB13
IDEDB14
AC97_SDOUT
AC97_SDIN1
SB_SPKR
AC97_SDIN2
AC97_SYNC
AC97_SDIN2
USB20P3-
USB20P0-
IDERSTHD#
CLK_SB_14M
EC_RSMRST#
32KHZ_S5_OUT
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
SB_EEDO
SB_EECLK
SPDIF_OUT
SMB_CK_CLK2_SB
SMB_CK_DAT2
SMB_CK_CLK2
SMB_CK_DAT2_SB
AC97_BITCLK
IDERSTCD#
SB_SCI#
SB_LID_OUT#
SB_EC_THERM#
SB_PM_BATLOW#
AGP_BUSY#_R
AGP_STP#_R
USB20P5+
SB_AC_IN
SB_EC_SMI#
LPC_PME#
SB_EC_THERM#
SB_KBRST#
SB_GA20
PCI_ACT_REQ#
SLP_S3#
PWRBTN_OUT#
SLP_S5#
AGP_STP#_R
VGATE
CLK_SB_14M
GHI
AGP_BUSY#AGP_BUSY#_R
AGP_BUSY#_R
USB20P1-
USB20P0+
SB_PM_BATLOW#
SB_EC_THERM#
SB_EC_SWI#
PM_BATLOW#
EC_THERM#
EC_SWI#
ACINSB_AC_IN
SB_KBRST#
SB_GA20 GA20
KBRST#
EC_SMI#
LID_OUT#SB_LID_OUT#
SB_EC_SMI#
SB_SCI# SCI#
IDERSTHD#
IDERSTCD#
AGP_STP#
SB_TEST0
SB_TEST1
AGP_BUSY#
AGP_STP#
USB20P4-
USB20P2+
USB20P2-
USB20P1+
USB20P3+
USB20P4+
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
SMB_CK_CLK2
EC_FLASH#
IDERST_HD#
IDERST_CD#
GHI
AC97_BITCLK
OVCUR#2
USB20P3+
USB20P4+
USB20P0-
USB20P2-
USB20P3-
USB20P4-
USB20P0+
USB20P5+
USB20P5-
USB20P1+
USB20P2+
USB20P1-
OSCLIN
SUS_STAT#
SUS_STAT#
OVCUR#2
OVCUR#0
OVCUR#1
SLP_S5# <44>
SLP_S3# <44>
PWRBTN_OUT# <44>
SB_PWRGD <46>
AC97_SYNC <29,36,42>
AC97_RST# <36,42>
AC97_BITCLK <36,42>
AC97_SDIN1 <42>
AC97_SDOUT <29,36,42>
AC97_SDIN0 <36>
SB_SPKR<37>
USB20P5-<42>
USB20P5+<42>
CLK_SB_14M<24>
EC_RSMRST#<44>
OVCUR#0<35>
32KHZ_S5_OUT<29>
SB_EEDO<29>
SPDIF_OUT <29>
MII_TXD1<29>
SB_EECLK<29>
MII_TXEN<29>
MII_TXD2<29>
MII_TXD0<29>
MII_TXD3<29>
EC_FLASH#<45>
IDEIOR#A <30>
IDESAA0 <30>
IDEIRQA <30>
IDECS#A1 <30>
IDEDACK#A <30>
IDEIORDYA <30>
IDESAA1 <30>
IDESAA2 <30>
IDECS#A3 <30>
IDEREQA <30>
IDEIOW#A <30>
IDESAB2 <30>
IDEREQB <30>
IDECS#B3 <30>
IDECS#B1 <30>
IDEIOR#B <30>
IDEIOW#B <30>
IDESAB1 <30>
IDEIORDYB <30>
IDEIRQB <30>
IDESAB0 <30>
IDEDACK#B <30>
IDEDB[0..15] <30>
IDEDA[0..15] <30>
OVCUR#1<35>
AGP_BUSY# <10,17>
IDERST_CD#<30>
IDERST_HD#<30>
AGP_STP#<10,17>
VTT_PWRGD <24,46>
EC_THERM# <44>
PM_BATLOW# <44>
EC_SWI# <44>
GA20 <44>
KBRST# <44>
ACIN <44,48,51>
EC_SMI# <44>
SCI# <44>
LID_OUT# <44>
USB20P0+<35>
USB20P0-<35>
USB20P2-<35>
USB20P2+<35>
USB20P3-<35>
USB20P3+<35>
USB20P1-<35>
USB20P1+<35> PWR_STRP <29>
CPU_GHI#<5>
SMB_CK_CLK2 <14,15,24>
SMB_CK_DAT2 <14,15,24>
OVCUR#2<35>
AGP_SUS_STAT# <17>
NB_SUS_STAT# <8>
CLK_SB_48M<24>
+3VS
+3V
+3V
+3VALW
+3VS
+3VS
+3VS
+3VS
+3V
+3VS
+2.5V
+2.5V
+2.5V
+2.5V
+3V
+3V +3V
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
SB200M(2/4) - IDE/USB/MII
27 65, 07, 20
星期三 七月
04
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R952
@10K_0402_5%
12
R1184
0_0402_5%
1 2
R120 10K_0402_5%
1 2
RP107
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP12 2.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP108
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R951 10K_0402_5%
12
R71
@10_0402_5%
12
RP13 8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
X2 48MHZ_4P_FN4800002
OUT 3
GND 2
VDD
4
OE
1
D7 RB751V_SOD323
2 1
R1293 @0_0402_5%
D77
RB751V_SOD323
2 1
D4 RB751V_SOD323
2 1
D6 RB751V_SOD323
2 1
R1188
4.7K_0402_5%
1 2
R63
12.4K_0603_1%
D11 RB751V_SOD323
2 1
R950 10K_0402_5%
12
RP11 10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R1303 10K_0402_5%
1 2
R948 10K_0402_5%
12
R1187
M10@10K_0402_5%
12
G
D
S
Q89 2N7002 1N_SOT23
2
1 3
D9 RB751V_SOD323
2 1
Q4 MMBT3904_SOT23
2
3 1
RP112
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
RP109
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
SECONDARY ATA 66/100
PRIMARY ATA 66/100
ACPI / WAKE UP EVENTS
Part 2 of 3
SB200 SB
AC97
USB INTERFACE
ETHERNET MIIEEPROMCLK / RST
GPIOGPIO_XTRA
U3B
South bridge SB200
TALERT#/ETH_TALERT# AB4
PME#/EXT_EVNT0# AC9
RI#/EXT_EVNT1# AC7
SLP_S3# AA11
SLP_S5# AB10
PWR_BTN# AA10
PCI_REQACT# C21
SUS_STAT# Y10
TEST1 AA5
32KHZ_IN/GPM3
W11
USBOC1#/GPM4
AB1
SPEAKER/GPM5
Y4
FANOUT0/GPM6
AA1
RSMRST#
AB9
GEVENT5#/ETH_VALERT# Y8
GPOC0#/SCL0 AA12
GPOC1#/SDA0 W12
GPOC2#/SCL1 Y12
GPOC3#/SDA1 AB12
PWR_GOOD Y11
PIDE_IORDY AB17
PIDE_IRQ AC16
PIDE_A0 AB15
PIDE_A1 AB16
PIDE_A2 AC15
PIDE_DACK# Y16
PIDE_DRQ AA17
PIDE_IOR# AA16
PIDE_IOW# AC17
PIDE_CS1# Y15
PIDE_CS3# AA15
PIDE_D0 AC18
PIDE_D1 AA18
PIDE_D2 AC19
PIDE_D3 AA19
PIDE_D4 AC20
PIDE_D5 AA20
PIDE_D6 AC21
PIDE_D7 AB21
PIDE_D8 AA21
PIDE_D9 Y20
PIDE_D10 AB20
PIDE_D11 Y19
PIDE_D12 AB19
PIDE_D13 Y18
PIDE_D14 AB18
PIDE_D15 Y17
SIDE_IORDY AA23
SIDE_IRQ AA22
SIDE_A0 AC23
SIDE_A1 Y21
SIDE_A2 AB23
SIDE_DACK# Y22
SIDE_DRQ W21
SIDE_IOR# Y23
SIDE_IOW# W20
SIDE_CS1# AC22
SIDE_CS3# AB22
SIDE_D0 W23
SIDE_D1 V21
SIDE_D2 V23
SIDE_D3 U21
SIDE_D4 U23
SIDE_D5 T21
SIDE_D6 T23
SIDE_D7 R21
SIDE_D8 R20
SIDE_D9 T22
SIDE_D10 T20
SIDE_D11 U22
SIDE_D12 U20
SIDE_D13 V22
SIDE_D14 V20
SIDE_D15 W22
AC_BITCLK E1
AC_SDOUT E2
AC_SDIN0 Y1
AC_SDIN1 Y2
AC_SDIN2 Y3
AC_SYNC E3
AC_RST# V5
SPDIF_OUT E5
USBCLK/CLK48
P3
USB_HSDP0+
F1
TEST0 AA6
GEVENT6#/ETH_FALERT# AA7
GEVENT7#/ETH_CALERT# AB6
LPC_SMI#/GEVNT4# W5
LPC_PME#/GEVNT3# Y6
KB_RST#/GEVNT1# AA4
GA20_IN/GEVNT0# Y5
SMB_ALERT#/GEVNT2# AB3
USB_RCOMP
R1
USB_ATEST1
N4
USB_ATEST0
N3
USBOC0#/GPM7
P4
USB_FLDP0+
F2
USB_HSDM0-
G1
USB_FLDM0-
G2
USB_HSDP5+
M2
USB_FLDP5+
M1
USB_HSDM5-
N2
USB_FLDM5-
N1
USB_HSDP4+
L4
USB_FLDP4+
L3
USB_HSDM4-
M4
USB_FLDM4-
M3
USB_HSDP3+
K2
USB_FLDP3+
K1
USB_HSDM3-
L2
USB_FLDM3-
L1
USB_HSDP2+
H2
USB_FLDP2+
H1
USB_HSDM2-
J2
USB_FLDM2-
J1
USB_HSDP1+
G3
USB_FLDP1+
J3
USB_HSDM1-
H3
USB_FLDM1-
K3
MCOL
R5
MCRS
W1
MDCK
V4
MDIO
V2
RX_CLK
T1
RXD3
T3
RXD2
U2
RXD1
T5
RXD0
W4
RX_DV
T2
RX_ERR
U1
TX_CLK
T4
TXD3
U4
TXD2
V1
TXD1
U3
TXD0
V3
TX_EN
W2
PHY_RST#
U5 PHY_PD
W3
EE_CS
P2
EE_DI
R3
EE_DO
R2
EE_CK
R4
OSC_IN
A23
SIO_CLK
W6
FANOUT1/USBOC2#/GPM2
AA3 BLINK/GPM0
AB2
USB_VREFOUT
P1
CLK_25M
Y7
GPIO_X0/AGP_STP#
AC1
GPIO_X1/AGP_BUSY#
AC6
GPIO_X2/GHI#
AC2
GPIO_X3/VGATE
AC3
GPIO_X4
AC4
GPIO_X5
AC5
RTC_IRQ#/PWR_STRP AA8
R1176 8.2K_0402_5%
D3 RB751V_SOD323
2 1
D8 RB751V_SOD323
2 1
D10 RB751V_SOD323
2 1
RP110
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R92
@10_0402_5%
12
R117 33_0402_5%
R1301 10K_0402_5%
12
R1185
4.7K_0402_5%
1 2
R68
10K_0402_5%
1 2
R1003
33_0402_5%
1 2
D13 RB751V_SOD323
2 1
C1010
0.1U_0402_10V6K
1
2
R119 33_0402_5%
D14 RB751V_SOD323
2 1
R112 100K_0402_5%
R934 1K_0603_5%
1 2
R947 10K_0402_5%
12
R1186
M10@4.7K_0402_5%
1 2
R69
4.7K_0402_5%
1 2
C74
@15P_0402_50V8J
RP111
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R1302 10K_0402_5%
12
R111 8.2K_0402_5%
D2 RB751V_SOD323
2 1
RP113
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
Q3 M10@MMBT3904_SOT23
2
3 1
R121 10K_0402_5%
1 2
D5 RB751V_SOD323
2 1
R1183
10K_0402_5%
12
RP140 8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
C75
@15P_0402_50V8J
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3VS +3VS
+2.5VS
+2.5V
+3V
+2.5VS
+2.5VALW
+3VALW
+2.5VS
+3V_AVDDUSB
+3V_AVDDUSB
+3V_AVDDC
+3V_AVDDC
+2.5V_AVDDCK
+2.5VS
+2.5V_AVDDCK
+3V
+3V
+3V
+2.5V
+3VS
+2.5VS
+3V
+2.5V
+5VS
+3VS
+3V_AVDDUSB
+3V_AVDDC
+2.5V_AVDDCK
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
SB200M(3/4) - PWR
28 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ATI request
ATI request
ATI request
ATI request
CLOSE TO
L6,H6,J6
ATI request
ATI request
ATI request
C35
0.1U_0402_10V6K
1
2
C887
10U_0805_10V6K
C34
0.1U_0402_10V6K
1
2
C46
0.1U_0402_10V6K
1
2
+
C888
47U_B_6.3VM
1
2
C24
22U_1206_16V4Z_V1
1
2
R1114
1K_0402_5%
12
C27
0.1U_0402_10V6K
1
2
C66
0.1U_0402_10V6K
1
2
C63
0.1U_0402_10V6K
1
2
C64
0.1U_0402_10V6K
1
2
C51
0.1U_0402_10V6K
1
2
C982
0.01U_0402_16V7Z
1
2
C49
22U_1206_16V4Z_V1
1
2
C96
470P_0402_50V7K
1
2
C53
0.1U_0402_10V6K
1
2
C877
0.1U_0402_16V7Z
1
2
Part 3 of 3
SB200 SB
POWER
U3C
South bridge SB200
VSS N10
VSS M9
VSS M6
VSS M15
VSS M14
VSS M13
VSS M12
VSS M11
VSS M10
VSS L19
VSS L18
VSS L14
VSS L13
VSS L12
VSS L11
VSS L10
VSS K19
VSS K18
VSS K14
VSS K13
VSS K12
VSS K11
VSS K10
VSS J9
VSS J19
VSS J18
VSS J15
VSS J12
VSS G6
VSS F9
VSS F6
VSS F18
VSS F14
VSS F13
VSS F10
VSS E9
VDDQ
E11
VDDQ
E12
VDDQ
E15
VDDQ
E7
VDDQ
E8
VDDQ
F11
VDDQ
F12
VDDQ
F15
VDDQ
F16
VDDQ
F17
VDDQ
F7
VDDQ
F8
VDDQ
G18
VDDQ
G19
VDDQ
H18
VDDQ
H19
VDDQ
M18
VDDQ
M19
VDDQ
N18
VDDQ
N19
VDDQ
T18
VDDQ
T19
VDDQ
U18
VDDQ
U19
VDDQ
V17
VDDQ
V18
VREF_CPU
D19
5V_VREF
D1
STB_3.3V
W9
STB_3.3V
W10
VDD_CORE
K15
VDD_CORE
J11
VDD_CORE
J14
VDD_CORE
L15
VDD_CORE
N15
VDD_CORE
K9
VDD_CORE
J10
VDD_CORE
J13
VDD_CORE
L9
VSS E6
VSS E14
VSS E13
VSS E10
STB_3.3V
V11 STB_3.3V
V10 STB_3.3V
V9 STB_3.3V
U6 STB_3.3V
T6
AVDD_CK
A21
AVSSCK A22
AVDDTX0
F4
AVDDTX1
J4
AVDDTX2
K5
AVDDRX0
F3
AVDDRX1
K4
AVDDRX2
L5
AVSSTX0 F5
AVSSTX1 H4
AVSSTX2 K6
AVSSRX1 J5
AVSSRX0 G4
AVSSRX2 M5
VSS N11
VSS N12
VSS N13
VSS N14
VSS N6
VSS P10
VSS P11
VSS P12
VSS P13
STB_2.5V
W13 STB_2.5V
V13 STB_2.5V
R6 STB_2.5V
P6
VDD_CORE
N9
VDD_CORE
P15
VDD_CORE
P9
AVDDC
P5
VDD_USB
J6 VDD_USB
H6 VDD_USB
L6
VSS_USB H5
VSS_USB G5
AVSSC N5
VDDQ
W17
VDDQ
W18
VSS P14
VSS P18
VSS P19
VSS R12
VSS R15
VSS R18
VSS R19
VDD_CORE
R10
VDD_CORE
R11
VDD_CORE
R13
VDD_CORE
R14
VSS R9
VSS V14
VSS V15
VSS V16
VSS V19
VSS V6
VSS V7
VSS V8
VSS W14
VSS W15
VSS W16
VSS W19
S5_2.5V
Y9
S5_3.3V
AA9
STB_2.5V
V12
VSS W7
VSS W8
C40
22U_1206_16V4Z_V1
1
2
C69
0.1U_0402_10V6K
1
2
C47
0.1U_0402_10V6K
1
2
C983
1000P_0402_16V7K
1
2
C67
0.1U_0402_10V6K
1
2
C59
1U_0603_10V6K
1
2
C30
0.1U_0402_10V6K
1
2
C882
0.1U_0402_16V7K
C55
0.1U_0402_10V6K
1
2
C98
680P_0402_50V7K
1
2
C32
0.1U_0402_10V6K
1
2
C980
0.01U_0402_16V7Z
1
2
C878
0.1U_0402_16V7Z
1
2
C62
22U_1206_16V4Z_V1
1
2
C28
0.1U_0402_10V6K
1
2
C72
0.1U_0402_10V6K
1
2
C880
0.1U_0402_16V7Z
1
2
C874
0.1U_0402_16V7Z
1
2
C65
0.1U_0402_10V6K
1
2
C39
0.1U_0402_10V6K
1
2
C70
0.1U_0402_10V6K
1
2
C981
1000P_0402_16V7K
1
2
C29
0.1U_0402_10V6K
1
2
R62
FBM-10-201209-260-T_0805
1 2
C883
0.1U_0402_16V7K
C42
0.1U_0402_10V6K
1
2
C99
680P_0402_50V7K
1
2
C58
0.1U_0402_10V6K
1
2
C48
0.1U_0402_10V6K
1
2
C57
0.1U_0402_10V6K
1
2
C44
0.1U_0402_10V6K
1
2
C843
1U_0603_10V6K
1
2
C886
0.1U_0402_16V7K
C876
0.1U_0402_16V7Z
1
2
C881
0.1U_0402_16V7Z
1
2
C36
0.1U_0402_10V6K
1
2
C885
0.1U_0402_16V7K
C25
0.1U_0402_10V6K
1
2
C93
680P_0402_50V7K
1
2
C95
470P_0402_50V7K
1
2
C873
0.1U_0402_16V7Z
1
2
R60
FBM-10-201209-260-T_0805
1 2
C60
0.1U_0402_10V6K
1
2
C43
0.1U_0402_10V6K
1
2
C68
0.1U_0402_10V6K
1
2
C37
0.1U_0402_10V6K
1
2
C966
0.1U_0402_16V7K
D90
RB751V_SOD323
2 1
C56
0.1U_0402_10V6K
1
2
C879
0.1U_0402_16V7Z
1
2
C94
1000P_0402_50V7K
1
2
C26
0.1U_0402_10V6K
1
2
R61
FBM-10-201209-260-T_0805
1 2
C71
1U_0603_10V6K
1
2
C50
0.1U_0402_10V6K
1
2
C875
0.1U_0402_16V7Z
1
2
C45
0.1U_0402_10V6K
1
2
C41
0.1U_0402_10V6K
1
2
C23
22U_1206_16V4Z_V1
1
2
C889
22U_1206_16V4Z_V1
1
2
C31
0.1U_0402_10V6K
1
2
C54
22U_1206_16V4Z_V1
1
2
C52
0.1U_0402_10V6K
1
2
C33
0.1U_0402_10V6K
1
2
C38
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_STRP<27> SB_EEDO<27> SB_EECLK<27>AC97_SYNC<27,36,42>AC97_SDOUT<27,36,42> SPDIF_OUT<27>
MII_TXEN<27> MII_TXD3<27> MII_TXD2<27> MII_TXD1<27> MII_TXD0<27>
32KHZ_S5_OUT<27>
PCI_AD26<26,31,33,34,41>
+3VS
+3VALW +3V +3V +3VS +3VS +3V +3V +3V +3V +3V +3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
SB200M(4/4) - STRAPS
29 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
SIO 24MHzUSE
DEBUG
STRAPS
CPU_STP#
STRAP
HIGH
ROM ON
LPC
BUS
ROM ON
PCI BUS
DEFAULT
INIT ACTIVE
HIGH
DEFAULT
PROCESSOR FREQ MULTIPLIER
SIO 48MHzAUTO
PWR
ON
ETHERNET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP
ENABLE
SPEED
STEP
DISABLE
SPEED
STEP
DEFAULT
REQUIRED SYSTEM STRAPS
AC_SYNC
INIT ACTIVE
LOW (PIII)
33MHz NB
BUS
EEDO
DEFAULT
DEFAULT DEFAULT
EECK
HI SPEED
A-LINK
STRAP
LOW
IGNORE
DEBUG
STRAPS
DEFAULT
DISABLE
CPU FREQ
SETTING
ENABLE CPU
FREQSETTING
TX_EN
IGN DEBUG SPEEDSTEP FREQLTCH
MANUAL
PWR ON
DEFAULT
32KHZ_S5
32KHZ
OUTPUT
FROM SB200
(INT RTC)
32KHZ INPUT
TO SB200
(EXT RTC)
DEFAULT
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
High : ENE910
Low : NS591L
R967
@10K_0402_5%
12
R42
10K_0402_5%
R48
10K_0402_5%
12
R37
@10K_0402_5%
R44
10K_0402_5%
R35
@10K_0402_5%
R39
@10K_0402_5%
R59
@10K_0402_5%
R45
10K_0402_5%
R57
@10K_0402_5%
R41
10K_0402_5%
12
R54
@10K_0402_5%
R50
10K_0402_5%
1 2
R51
10K_0402_5%
12
R58
@10K_0402_5%
R46
10K_0402_5%
12
R953
10K_0402_5%
12
R43
10K_0402_5%
R52
10K_0402_5%
12
R55
@10K_0402_5%
R34
10K_0402_5%
12
R36
@10K_0402_5%
R38
@10K_0402_5%
R56
@10K_0402_5%
R47
@10K_0402_5%
R49
10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IDEDA[0..15]
SD_SBA2
SD_SIOW#
PD_IRQA
PD_IOW#
SD_DACK#
SD_SBA1
SD_SIOR#
SD_SBA0
PD_DACK#
SD_SCS3#
IDESAB1
IDESAB0
SD_IDERST#
HD_IDERST#
IDESAA0
HDD_LED#
CDLED#
PD_D4
PD_D5
PD_A2
PD_D12
PD_A0
PD_A1
PD_D14
HDD_LED#
PD_D11
PCSEL
HD_IDERST#
PD_IOR#
PD_DACK#
PD_D3
PD_IOW#
PD_D9
PD_D1
PD_D6
PD_D2
PD_CS#3
PD_D15
PD_D13
PD_CS#1
PD_D10
PD_D8
PD_IRQA
PD_IORDY
PD_D7
PD_D0
SD_DREQ
CDROM_L
SD_D9
SD_SIOW#
SD_D4
SD_IDERST#
SD_DACK#
SD_SBA2
SD_D11
SD_D3
SD_CSEL
SD_D8
SD_D2
SD_D6
SD_SIORDY
SD_D0
SD_IRQ15
SD_D12
SD_SCS3#SD_SCS1#
SD_D1 SD_D14
SD_D15
SD_D7
SD_SBA1
CD_AGND
SD_D13
SD_D10
SD_SIOR#
CDROM_R
SD_DREQ
SD_SBA0
SD_D5
IDEDB0
IDEDB10
IDEDB7
IDEDB2
IDEDB3
IDEDB5
IDEDB1
IDEDB14
IDEDB11
IDEDB13
IDEDB15
IDEDB6
IDEDB9
IDEDB8
IDEDB12
IDEDB4
PD_D14
PD_D0
PD_D1
PD_D15
PD_D8
PD_D6
PD_D7
SD_SIORDY
SD_SCS1#
PD_IOR#
SD_DREQ
SD_IRQ15
IDEDA14
IDEDA0
IDEDA15
IDEDA1
IDEDA7
IDEDA6
IDEDA9
IDEDA8
IDEDA3
IDEDA12
IDEDA2
IDEDA13 PD_D2
PD_D12
PD_D3
PD_D9
IDEDA11
IDEDA4
PD_D11
PD_D5
PD_D10
IDEDA5
IDEDA10
PD_D4
PD_IORDY
PD_D13
IDEDB[0..15]
CDLED#
SD_D6
SD_D3
SD_D12
SD_D2
SD_D13
SD_D10
SD_D8
SD_D7
SD_D0
SD_D15
SD_D1
SD_D14
SD_D5
SD_D9
SD_D4
SD_D11
PD_A0
PD_A2
PD_CS#3
PD_A1
PD_CS#1
PD_DREQ#
PD_DREQ#
IDECS#A3
IDESAA2
IDESAA1
IDECS#A3<27>
IDEIOW#A<27>
IDEIRQA<27>
IDEREQA<27>
IDEDA[0..15]<27>
IDEDACK#A<27>
PCI_RST#<11,26,31,33,34,38,41,44>
IDERST_CD#<27>
IDERST_HD#<27>
IDEIOR#A<27>
IDESAA0<27>
IDESAA1<27>
IDESAA2<27>
ACT_LED# <44>
CD_AGND <36>
CDROM_R <36>CDROM_L<36>
IDECS#B3<27>
IDESAB0<27>
IDESAB2<27>
IDEIRQB<27>
IDEIOW#B<27> IDEIOR#B<27>
IDESAB1<27>
IDEREQB<27>
IDEDACK#B<27>
IDEDB[0..15]<27>
IDEIORDYA<27>
IDEIORDYB<27>
IDECS#B1<27>
IDECS#A1<27>
+5VS
+5VS
+5VS
+5VS +5VS
+5VS
+5VS
+5VS
+5VS +5VS
+5VS
+5VS
+5VS
+5VS+5VS
+3VS
+3VS
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
HDD & CDROM Connector
30 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
+5VCD trace to CONN W=100mils
W=100mils
HDD/CD-ROM Module
Placea caps. near CDROM CONN.
W=100mils
+5VCD trace to CONN W=100mils
Placea caps. near CDROM CONN.
Placea caps. near HDD CONN.
W=80mils
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R970 33_0402_5%
1 2
C5
0.1U_0402_10V6K
1
2
C12
@47P_0402_25V8K
1 2
C2
10U_0805_16V4Z
1
2
R26 33_0603_1%
C17
1000P_0402_50V7K
1
2
U1C
74HCT08PW_TSSOP14
I0
9
I1
10 O8
RP3 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
R613 @100K_0402_5%
1 2
C8
4.7U_0805_10V4Z
1
2
U1B
74HCT08PW_TSSOP14
I0
4
I1
5O6
R9 470_0402_5%
1 2
R31 33_0603_1%
RP9 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
U1A
74HCT08PW_TSSOP14
I0
1
I1
2O3
P14
G
7
R3 10K_0402_5%
12
RP4 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
C19
1U_0603_10V6K
1
2
RP7 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
R33
8.2K_0402_5%
1 2
R15
10K_0402_5%
1 2
RP124
33_0804_8P4R_5%
1 8
2 7
3 6
4 5
R32 5.6K_0402_5%
1 2
C3
10U_0805_16V4Z
1
2
R614
470_0402_5%
1 2
C18
10U_0805_16V4Z
1
2
RP1 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
R1110 @10K_0402_5%
1 2
C20
0.1U_0402_10V6K
1
2
JP2
CD-ROM CONN.
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
C21
1000P_0402_50V7K
1
2
RP8 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
C14
10U_0805_16V4Z
1
2
R24
10K_0402_5%
1 2
C11 @10U_0805_6.3V6M
12
RP10 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
R25
4.7K_0402_5%
12
R18 33_0603_1%
U1D
74HCT08PW_TSSOP14
I0
12
I1
13 O11
R969 33_0402_5%
1 2
R11 33_0603_1%
C1
1000P_0402_50V7K
1
2
C22 33P_0402_25V8K
1 2
C15
1U_0603_10V6K
1
2
RP5 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
R8
4.7K_0402_5%
1 2
C6
4.7U_0805_10V4Z
1
2
R968
8.2K_0402_5%
1 2
RP125 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
C9
1U_0603_25V4Z
1
2
R19
5.6K_0402_5%
12
RP2 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
C4
1U_0603_10V6K
1
2
R4 33_0402_5%
1 2
RP6 33_8P4R_0804_5%
1 8
2 7
3 6
4 5
C16
0.1U_0402_10V6K
1
2
R611
10K_0402_5%
12
JP1
OCTEK_HDD-22HG2_REVERSE
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
C610 0.1U_0402_10V6K
12
C7
1U_0603_25V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S1_CD1# S1_CD2#
XD_MS_PWREN#
SDCD#
SDWP
SDCD#
SDWP
SDPWREN#
S1_D0
S1_D9
S1_D10
S1_D1
S1_D8
S1_A3
PCI_AD1
S1_A6
S1_A4
S1_A5
S1_A1
S1_A0
S1_A2
PCI_AD4
PCI_AD2
PCI_AD6
PCI_AD7
PCI_AD0
PCI_AD3
PCI_AD5
PCI_AD9
PCI_AD12
PCI_AD10
PCI_AD11
PCI_AD8
PCI_AD13
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD14
PCI_AD18
PCI_AD20
PCI_AD19
PCI_AD22
PCI_AD21
PCI_AD26
PCI_AD31
PCI_AD24
PCI_AD23
PCI_AD25
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
S1_A7
S1_A17
S1_A24
S1_A25
S1_D3
S1_D13
S1_D5
S1_D12
S1_D4
S1_D11
S1_IORD#
S1_CE2#
S1_A11
S1_D6
S1_A10
S1_D15
S1_D7
S1_IOWR#
S1_A9
S1_OE#
PCI_RST#
S1_A8
S1_CE1#
S1_REG#
S1_A12
CLK_PCI_PCM A16_CLK
S1_A22
S1_WAIT#
S1_RST
S1_A21
S1_A23
S1_A14
S1_INPACK#
S1_A20
S1_A15
S1_A13
S1_A16
S1_WE#
S1_WP
S1_BVD1
S1_A19
PCM_SPK#
S1_CD2#
S1_RDY#
S1_BVD2
S1_VS2
3V_PCM_SUSP
S1_VS1
S1_CD1#
S1_D[0..15]
S1_A[0..25]
PCI_AD[0..31]
PCM_IDPCI_AD20
SDCM_XDALE
S1_D2
S1_A18
S1_D14
PCI_PIRQB#
CLK_PCI_PCM
PCI_PIRQA#
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
PCI_RST#
MSBS_XDD1
MSD0_XDD2
MSD1_XDD6
SDDA0_XDD7
SDDA2_XDCL
SDDA1_XDD0
SDDA3_XDD4
MSD2_XDD5SDCM_XDALE MSD3_XDD3
MSD2_XDD5
MSD3_XDD3
MSBS_XDD1
MSD1_XDD6
MSD0_XDD2
SD_PULLHIGH
SD_PULLHIGH
MSINS#
SDOC#
SDCD#<32> XD_MS_PWREN# <32>
VCCD1#<32> VCCD0#<32>
SDWP<32>
SDPWREN#<32>
VPPD0<32> VPPD1<32>
SDOC#<32>
XDBSY# <32>
PCI_CBE#3<26,33,34,41>
PCI_CBE#1<26,33,34,41> PCI_CBE#0<26,33,34,41>
PCI_CBE#2<26,33,34,41>
S1_IORD# <32>
S1_IOWR# <32>
S1_CE2# <32>
S1_OE# <32>
XDCE# <32>
PCI_PERR#<26,33,34,41>
SDDA2_XDCL<32> SDDA3_XDD4<32>
SDDA0_XDD7<32> SDDA1_XDD0<32>
PCI_RST#<11,26,30,33,34,38,41,44>
PCI_STOP#<26,33,34,41>
PCI_IRDY#<26,33,34,41>
PCI_DEVSEL#<26,33,34,41>
PCI_FRAME#<26,33,34,41>
PCI_TRDY#<26,33,34,41>
PCI_PAR<26,33,34,41>
PCI_GNT#2<26>
PCI_SERR#<26,33,41>
PCI_REQ#2<26>
CLK_PCI_PCM<26>
MSCLK_XDRE# <32>
S1_CE1# <32>
S1_REG# <32>
S1_A[0..25] <32>
S1_D[0..15] <32>
PCI_AD[0..31]<26,29,33,34,41>
S1_WAIT# <32>
S1_INPACK# <32>
S1_WE# <32>
S1_RST <32>
S1_WP <32>
S1_BVD2 <32>
S1_RDY# <32>
S1_BVD1 <32>
S1_CD1# <32>
PCM_SPK# <37>
S1_VS2 <32>
S1_CD2# <32>
S1_VS1 <32>
CLK_SD_48M<24>
CARD_LED#<44>
SDCM_XDALE<32>
SDCK_XDWE#<32>
MSD0_XDD2 <32>
PCI_PIRQB#<26>
MSD1_XDD6 <32>
MSD2_XDD5 <32>
MSD3_XDD3 <32>
MSBS_XDD1 <32>
PCI_PIRQA#<10,17,26,34>
SIRQ<26,38,44>
XDWP# <32>
XDCD# <32>
MSINS# <32>
SM_CD#<32>
+3VS
+S1_VCC
+3VS
+S1_VCC
+3VS
+3VS
+3VS
+VCC_5IN1
+VCC_5IN1
+3VS +3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
PCMCIA Controller ENE CB714
Custom
31 65
星期
, 07, 2004
三七月
IDSEL:
PCI_AD20
Close chip termenal
Closed to Pin A4Closed to Pin L12
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
Close chip termenal
R1209 10K_0402_5%
1 2
C1037
0.1U_0402_16V4Z
1
2
C1038
0.1U_0402_16V4Z
1
2
R1216 @43K_0402_5%
1 2
C1040
10P_0402_50V8J
1
2
R1306 0_0805_5%
1 2
R1220 @43K_0402_5%
1 2
C1029
0.1U_0402_16V4Z
1
2
R1211 100_0402_5%
1 2
R20
10K_0402_5%
1 2
R1212 43K_0402_5%
1 2
R1215 @43K_0402_5%
1 2
R1221 @43K_0402_5%
1 2
R1218 @43K_0402_5%
1 2
C1031
0.1U_0402_16V4Z
1
2
R1217 33_0402_5%
1 2
C1027
0.1U_0402_16V4Z
1
2
R1210 43K_0402_5%
1 2
R1219 33_0402_5%
1 2
R1207 33_0402_5%
1 2
C1030
0.1U_0402_16V4Z
1
2
C1039
@18P_0402_50V8K
1
2
CARDBUS
SD/MMC/MS/SM
PCI Interface
U37
CB714_LFBGA169
PCIREQ#
A1
PCIGNT#
B1
AD31
C2
AD30
C1
AD29
D4
AD28
D2
AD27
D1
AD26
E4
AD25
E3
AD24
E2
CBE3#
E1
IDSEL
F4
VCC2 G1
AD23
F2
AD22
F1
AD21
G2
VCCA1 G13
AD20
G3
PCIRST#
G4
PCICLK
H1
AD19
H3
AD18
H4
AD17
J1
AD16
J2
CBE2#
J3
FRAME#
J4
IRDY#
K1
VCC3 K2
TRDY#
K3
DEVSEL#
L1
STOP#
L2
PERR#
L3
SERR#
M1
PAR
M2
CBE1#
N1
AD15
N2
AD14
M3
AD13
N3
AD12
K4
AD11
M4
VCCA2 A7
AD10
K5
AD9
L5
AD8
M5
CBE0#
N5
AD7
K6
VCC4 N4
AD6
M6
AD5
N6
AD4
M7
AD3
N7
AD2
L7
AD1
K7
AD0
N8
RIOUT#_PME#
L8
MFUNC0
K8
MFUNC1
N9
SPKROUT M9
VCC1 F3
MFUNC2
K9
MFUNC3
N10
GRST#
M10
MFUNC4
L10
MFUNC5
N11
MFUNC6
M11
SUSPEND#
L11
VPPD0 N12
VPPD1 M12
VCCD0# N13
VCCD1# M13
CCD1#/CD1# L12
CAD0/D3 L13
CAD2/D11 K10
CAD1/D4 K12
CAD4/D12 K13
CAD3/D5 J10
CAD6/D13 J11
CAD5/D6 J12
CAD7/D7 H10
VCC5 L6
CAD8/D15 H12
CCBE0#/CE1# H13
CAD9/A10 G12
VCC9 C8
CAD10/CE2# G11
CAD11/OE# G10
CAD13/IORD# F13
CAD12/A11 F11
CAD15/IOWR# F10
CAD14/A9 E13
CAD16/A17 E12
CCBE1#/A8 E11
CPAR/A13 D13
VCC6 L9
CBLOCK#/A19 D11
CPERR#/A14 C13
CSTOP#/A20 C12
CGNT#/WE# C11
CDEVSEL#/A21 B13
CCLK/A16 B12
CTRDY#/A22 A13
CIRDY#/A15 A12
CFRAME#/A23 B11
CCBE2#/A12 A11
CAD17/A24 D10
CAD18/A7 B10
CAD19/A25 A10
CVS2/VS2# D9
CAD20/A6 C9
CRST#/RESET B9
CAD21/A5 A9
CAD22/A4 D8
VCC7 H11
CREQ#/INPACK# B8
CAD23/A3 A8
CCBE3#/REG# B7
VCC10 B4
CAD24/A2 C7
CAD25/A1 D7
CAD26/A0 A6
CVS1/VS1 C6
CINT#/READY_IREQ# D6
CSERR#/WAIT# A5
CAUDIO/BVD2_SPKR# B5
CSTSCHG/BVD1_STSCHG# C5
CCLKRUN#/WP_IOIS16# D5
CCD2#/CD2# A4
VCC8 D12
CAD27/D0 C4
CAD28/D8 A3
CAD29/D1 B3
CAD30/D9 C3
CAD31/D10 B2
CRSV1/D14 J13
CRSV2/A18 E10
CRSV3/D2 A2
MFUNC7
J9
MSINS# H7
MSPWREN#/SMPWREN# J8
VCC_SD
E7
GND_SD
G5
SDCLKI
H5
MSCLK/SMRE# E9
MSBS/SMDATA1 H8
MSDATA0/SMDATA2 G9
MSDATA1/SMDATA6 H9
MSDATA2/SMDATA5 G8
MSDATA3/SMDATA3 F9
SMBSY# H6
SMCD# J7
SMWP# J6
SMCE# J5
SDCD#
E8
SDWP/SMWPD#
F8
SDPWREN33#
G7
GND1
D3
GND2
H2
GND3
L4
GND4
M8
GND5
K11
GND6
F12
GND7
C10
GND8
B6
SDCLK/SMWE#
F6
SDCMD/SMALE
E5
SDDAT0/SMDATA7
E6
SDDAT1/SMDATA0
F7
SDDAT2/SMCLE
F5
SDDAT3/SMDATA4
G6
R1307 @43K_0402_5%
1 2
R1206
@10_0402_5%
12
R1222 @43K_0402_5%
1 2
C1034
0.1U_0402_16V4Z
1
2
R1308
2.2K_0402_5%
1 2
C1035
0.1U_0402_16V4Z
1
2
R1304
@0_0805_5%
1 2
C1032
0.1U_0402_16V4Z
1
2
R1223 @43K_0402_5%
1 2
C1036
0.1U_0402_16V4Z
1
2
R1214 43K_0402_5%
1 2
C1028
0.1U_0402_16V4Z
1
2
C1033
0.1U_0402_16V4Z
1
2
R1213 43K_0402_5%
1 2
R1208 43K_0402_5%
1 2
C1041
10P_0402_50V8J
1
2
R1305
43K_0402_5%
1 2
XDBSY#
SDCK_XDWE#
MSCLK_XDRE#
MSCLK_XDRE#
SDCK_XDWE#
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP
S1_RST
S1_A[0..25]
S1_D[0..15]
S1_CE2#
S1_CE1#
S1_WP
S1_OE#
S1_CD2#
S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
XDCD#
SDDA1_XDD0
MSBS_XDD1
SDDA3_XDD4
MSD3_XDD3
MSD0_XDD2
SDDA0_XDD7
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
SDDA1_XDD0
MSD1_XDD6
SDDA0_XDD7
SDDA1_XDD0
SDDA3_XDD4
MSBS_XDD1
MSD1_XDD6
SDDA2_XDCL
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
SDCM_XDALE
SDCK_XDWE#
MSD2_XDD5
XDCD#
SDCD#
MSCLK_XDRE#
MSBS_XDD1
MSD0_XDD2
SDWP
SDCK_XDWE#
XDWP#
SDDA2_XDCL
SDCM_XDALE
XDBSY#
MSCLK_XDRE#
XDCE#
XDCE#
XDCD#
XDBSY#
XDWP#
MSCLK_XDRE#
SDDA2_XDCL
SDCK_XDWE#
SDCM_XDALE
MSD2_XDD5
MSD3_XDD3
SDWP
SDOC# <31>
XDBSY# <31>
SDPWREN#<31>
XD_MS_PWREN#<31>
XDCE# <31>
MSCLK_XDRE#<31>
S1_A[0..25]<31>
S1_D[0..15]<31>
VCCD0# <31>
VCCD1# <31>
VPPD0 <31>
VPPD1 <31>
SDCK_XDWE#<31>
S1_CE1#<31>
S1_OE#<31>
S1_WE#<31>
S1_RDY#<31>
S1_WP<31>
S1_CD1# <31>
S1_CE2# <31>
S1_VS1 <31>
S1_IORD# <31>
S1_IOWR# <31>
S1_VS2 <31>
S1_RST <31>
S1_WAIT# <31>
S1_INPACK# <31>
S1_REG# <31>
S1_BVD2 <31>
S1_BVD1 <31>
S1_CD2# <31>
XDCD# <31>
MSD3_XDD3<31>
MSD1_XDD6<31> MSD2_XDD5<31> SDDA3_XDD4<31>
SDDA1_XDD0<31>
SDDA0_XDD7<31>
MSBS_XDD1<31> MSD0_XDD2<31>
SDCD# <31>
MSINS#<31>
XDWP#<31>
SDDA2_XDCL <31>
SDCM_XDALE <31>
XDCE# <31>
MSCLK_XDRE# <31>
SDCK_XDWE# <31>
XDCD# <31>
XDBSY# <31>
SDWP <31>
SM_CD# <31>
+3VS
+VCC_5IN1
+VCC_5IN1
+5VS
+S1_VCC
+S1_VCC
+S1_VPP
+5VS
+3VS
+S1_VCC
+S1_VPP
+S1_VCC
+S1_VPP
+3VS +3VS
+S1_VPP
+S1_VCC
+VCC_5IN1
+3VS
+VCC_5IN1
+VCC_5IN1
+VCC_5IN1
+VCC_5IN1
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
PCMCIA Socket
Custom
32 65
星期
, 07, 2004
三七月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
xD PU and PD. Close to Socket
SD CLK
40mil
20mil
MS CLK
SD PWR Control
Close to
CardBus Conn.
Reserve for Debug.
PCMCIA Power Controller CardBus Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Compal Electronics, Inc.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C10480.1U_0402_16V4Z
C1042 0.1U_0402_16V4Z
1 2
R122847K_0402_5% 12
C1050
10U_0805_10V4Z
1
2
MS INTERFACE XD INTERFACE
SM INTERFACESD INTERFACE
JP31
PRO_FIT068-20-3100
SDIO_MS(P4)
34
SCLK_MS(P8)
38
INS_MS(P6)
36
BS_MS(P2)
32
D0_XD(P10)
10
D1_XD(P11)
11
D2_XD(P12)
12
D3_XD(P13)
13
D4_XD(P14)
14
D5_XD(P15)
15
D6_XD(P16)
16
D7_XD(P17)
17
R/B#_XD(P2)
2
RE#_XD(P3)
3
CE#_XD(P4)
4
WE#_XD(P7)
7
WP#_XD(P8)
8
CLE_XD(P5)
5
ALE_XD(P6)
6
VCC_XD(P18)
18
VSS_XD(P9)
9
DAT0_SD(P7) 23
DAT1_SD(P8) 22
DAT2_SD(P9) 30
CD/DAT3_SD(P1) 29
CLK_SD(P5) 25
CMD_SD(P2) 28
VDD_SD(P4) 26
VSS1_SD(P6) 27
VSS2_SD(P3) 24
IO 1_SM(P6) 60
IO 2_SM(P7) 64
IO 3_SM(P8) 54
IO 4_SM(P9) 49
IO 5_SM(P13) 45
IO 6_SM(P14) 50
IO 7_SM(P15) 52
IO 8_SM(P16) 56
CLE_SM(P2) 53
ALE_SM(P3) 59
CE_SM(P21) 51
RE_SM(P20) 61
WE_SM(P4) 63
WP_SD 19
GND_SD 20
CD_SD 21
LVD_SM(P17) 62
VCC_SM(P12) 46
VCC_SM(P22) 55
VSS_SM(P1) 57
VSS_SM(P10) 48
GND_SM(P18) 58
WP1_SM 41
WP2_SM 42
CD1_SM 43
CD2_SM 44
GND0
67
GND1
68
VSS_MS(P1)
31
VSS_MS (P10)
40
VCC_MS(P3)
33
VCC_MS(P9)
39
RSVD_MS(P5)
35
RSVD_MS(P7)
37
CD/GND_XD(P1)
1
R/B_SM(P19) 65
WP_SM(P5) 66
CD/VSS_SM(P11) 47
VCC_XD
70
GND_XD
69
R122947K_0402_5% 12
R123047K_0402_5% 12
R1224
10K_0402_5%
1 2
C1045 10U_0805_10V4Z
1 2
C1153
0.1U_0402_16V4Z
C10534.7U_0805_10V4Z
R1232 43K_0402_5%
1 2
C1057
@10P_0402_50V8K
1
2
R1235 2.2K_0402_5%
1 2
R122743K_0402_5% 12
C10440.1U_0402_16V4Z
C1055
0.01U_0402_25V4Z
1
2
C1152
0.1U_0402_16V4Z
R1233
10K_0402_5%
1 2
R1237 @43K_0402_5%
1 2
R1238 43K_0402_5%
1 2
R123147K_0402_5% 12
C1047 1U_0603_10V4Z
1 2
U38
CP-2211_SSOP16
VCCD0 1
VCCD1 2
3.3V
3
3.3V
4
5V
5
5V
6
GND
7
OC 8
12V
9
VPP 10
VCC 11
VCC 12
VCC 13
VPPD1 14
VPPD0 15
SHDN
16
C10494.7U_0805_10V4Z
C1054
4.7U_0805_10V4Z
1
2
R1234
10K_0402_5%
1 2
R1236 43K_0402_5%
1 2
C1056
@10P_0402_50V8K
1
2
JP29
FOX_WZ21131-G2-P4
GND
69
GND
71
GND
73
GND
75
GND
77
GND
79
GND
81
GND
83
GND 70
GND 72
GND 74
GND 76
GND 78
GND 80
GND 82
GND 84
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35 35
36 36
37 37
38 38
39 39
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
61 61
62 62
63 63
64 64
65 65
66 66
67 67
68 68
C10520.1U_0402_16V4Z
C1156
0.1U_0402_16V4Z
R1226
@0_0402_5%
12
U60
TPS2041ADR_SO8
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
C1151
10U_0805_10V4Z
1
2
C1046 0.01U_0402_25V4Z
1 2
C1155
0.1U_0402_16V4Z
C1051
0.1U_0402_16V4Z
1
2
R1225
@0_0402_5%
12
C1043 0.1U_0402_16V4Z
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
PCI_AD19
PCI_AD[0..31]
PCI_AD24
PCI_AD4
PCI_AD8
PCI_AD21
PCI_AD25
PCI_AD15
PCI_AD23
PCI_AD9
PCI_AD20
PCI_AD3
PCI_AD29
PCI_AD13
PCI_AD16
PCI_AD7
PCI_AD26
PCI_AD10
PCI_AD22
PCI_AD17
PCI_AD2
PCI_AD12
PCI_AD28
PCI_AD11
PCI_AD6
PCI_AD27
PCI_AD1
PCI_AD18
PCI_AD30
PCI_AD14
PCI_AD31
PCI_AD0
PCI_AD5
PCI_CBE#[0..3]
PCI_CBE#2
PCI_CBE#1
PCI_CBE#3
PCI_CBE#0
LINK_10_100_1000#
TXD+/MDI0+
ACTIVITY#
TXD-/MDI0-
RXIN+/MDI1+
PCI_AD19
RXIN-/MDI1-
CTRL25
EEDI
CTRL18
CTRL18
EESK
EEDO
EECS
CTRL25
X1
X2
X2X1
RJ45_RX-
RXIN+/MDI1+
RJ45_TX-
RJ45_TX+
RJ45_RX+
RJ45_GND
TXD-/MDI0-
TXD+/MDI0+
RXIN-/MDI1-
RJ45_GND
RJ45_RX-
ACTIVITY#
RJ45_TX+
LANGND
LINK_10_100_1000#
RJ45_RX+
RJ45_TX-
PCI_AD[0..31]<26,29,31,34,41>
PCI_CBE#[0..3]<26,31,34,41>
PCI_IRDY#<26,31,34,41>
PCI_PAR<26,31,34,41>
PCI_SERR#<26,31,41>
PCI_FRAME#<26,31,34,41>
PCI_DEVSEL#<26,31,34,41> PCI_TRDY#<26,31,34,41>
PCI_STOP#<26,31,34,41>
PCI_PIRQD#<26,41>
CLK_PCI_LAN<26>
PCI_GNT#1<26>
PCI_RST#<11,26,30,31,34,38,41,44>
PCI_PERR#<26,31,34,41>
PCI_REQ#1<26>
ONBD_LAN_PME#<34,41,44,45>
PCI_CLKRUN#<26,38,41,44>
EN_WOL#<44>
+V2.5_LAN
+LANVDD
+LANVDD
+LANVDD
+V2.5_LAN
+LANVDD
+LANVDD
+V2.5_LAN
+LANVDD
+V1.8_LAN +LANVDD
+LANVDD
+LANVDD
+V1.8_LAN
+V2.5_LAN
+V1.8_LAN
+5VS
+LANVDD
+V1.8_LAN
+LANVDD
+3VALW
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
Gigabit Ethernet RTL8110S
33 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
R64 5.6K for 8100C
2.49K for 8110S
Place as close to
LAN Chip
Place as close to
Magnetic
R1260 3.6K_0402_5%
12
R1277
49.9_0402_1%
12
R1279
75_0402_1%
12
C1082
4.7U_0805_10V4Z
1
2
C1091
0.1U_0402_16V4Z
1
2
C1113
8110S@0.1U_0402_16V4Z
1
2
U62
AT93C46-10SI-2.7_SO8
CS
1SK
2DI
3DO
4
VCC 8
NC 7
NC 6
GND 5
JP54
FOX_JM36113-L1H7
PR1-
2
PR1+
1
PR2+
3
PR3+
4
PR3-
5
PR2-
6
PR4+
7
PR4-
8
SHLD1
13
SHLD2
14 LED_GREEN 10
LED_ORANGE 9
LDE_YELLOW+ 12
LDE_YELLOW- 11
C1095
0.1U_0402_16V4Z
1
2
C1106
0.1U_0402_16V4Z
1
2
Q125
2SB1188_SOT89
3
1
2
C1097
0.1U_0402_16V4Z
1
2
R1285 8110S@0_0805_5%
1 2
R1259 300_0402_5%
12
R1284
75_0402_1%
1 2
R1283 8100C@0_0805_5%
1 2
C1088
0.1U_0402_16V4Z
1
2
R1270 5.6K_0603_1%
12
C1114
8110S@0.1U_0402_16V4Z
1
2
C1116
8100C@0.1U_0402_16V4Z
1
2
R1282
@10_0402_5%
1 2
R1258
@0_1206_5%
1 2
C1117
8100C@0.1U_0402_16V4Z
1
2
R1272 @0_0402_5%
12
R1281
75_0402_1%
1 2
C1103
0.1U_0402_16V4Z
1
2
R1268 15K_0402_5%
12
C1107
0.1U_0402_16V4Z
1
2
C1111
8110S@0.1U_0402_16V4Z
1
2
C1073
22U_1206_10V4Z
1
2
C1094
0.1U_0402_16V4Z
1
2
G
D
S
Q124
SI2301DS_SOT23
2
1 3
U63
Pulse H0013
RD+
1
RD-
2
CT
3
NC
4
NC
5
CT
6
RX+ 16
RX- 15
CT 14
NC 13
NC 12
CT 11
TD+
7TX+ 10
TX- 9
TD-
8
C1099
0.1U_0402_16V4Z
1
2
C1109
0.1U_0402_16V4Z
1
2
C1104
0.1U_0402_16V4Z
1
2
R1257 300_0402_5%
12
R1274 100_0402_5%
1 2 R1273
8110S@0_0805_5%
1 2
C1090
27P_0402_50V8J
1
2
R1280
75_0402_1%
12
C1080
0.1U_0402_16V4Z
1
2
R1271 8110S@0_0805_5%
1 2
C1078
0.1U_0402_16V4Z
1
2
PCI I/F
Power LAN I/F
U39
RTL8100C_QFP128
AD0
104
AD1
103
AD2
102
AD3
98
AD4
97
AD5
96
AD6
95
AD7
93
AD8
90
AD9
89
AD10
87
AD11
86
AD12
85
AD13
83
AD14
82
AD15
79
AD16
59
AD17
58
AD18
57
AD19
55
AD20
53
AD21
50
AD22
49
AD23
47
AD24
43
AD25
42
AD26
40
AD27
39
AD28
37
AD29
36
AD30
34
AD31
33
C/BE#3
44
IDSEL
46
C/BE#2
60
FRAME#
61
IRDY#
63
TRDY#
67
DEVSEL#
68
STOP#
69
PERR#
70
SERR#
75
PAR
76
C/BE#1
77 C/BE#0
92
ISOLATE# 23
EECS 106
RTSET 127
RTT3/CRTL18 125
PME#
31
LED0 117
LED1 115
LED2 114
X2 122
INTA#
25
RST#
27
CLK
28
GNT#
29 REQ#
30
TXD+/MDI0+ 1
TXD-/MDI0- 2
RXIN+/MDI1+ 5
RXIN-/MDI1- 6
AUX/EEDI 109
EESK 111
NC/VSS 9
NC/AVDDH 10
NC/HSDAC+ 11
NC/VSS 13
NC/MDI2+ 14
NC/MDI2- 15
NC/M66EN 88
NC/MDI3+ 18
NC/MDI3- 19
NC/GND 22
NC/VDD18 24
NC/GND 48
NC/GND 62
CLKRUN#
65
NC/SMBCLK 72
NC/GND 73
NC/SMBDATA 74
NC/VDD18 110
NC/GND 112
NC/GND 118
NC/HV 120
NC/HG 123
NC/LG2 124
NC/LV2 126
NC/VDD18 45
NC/VDD18 64
VDD33 41
VDD33 56
VDD33 71
VDD33 84
VDD33 94
VDD33 107
AVDD33/AVDDL 3
AVDD33/AVDDL 20
AVDD33/AVDDL 7
VDD25/VDD18 54
VDD25/VDD18 78
VDD25/VDD18 99
AVDD25/HSDAC- 12
CTRL25 8
GND/VSS
4
GND/VSS
17
GND/VSSPST
21
GND
35
GND/VSSPST
38
GND/VSSPST
51
GND
52
GND/VSSPST
66
GND
80
GND/VSSPST
81
GND/VSSPST
91
GND
100
GND/VSSPST
101
GND/VSSPST
119
GND/VSS
128
VDD33 26
X1 121
NC/VDD18 116
VDD25/VDD18 32
LWAKE 105
EEDO 108
NC/LED3 113
NC/AVDDL 16
C1077
1U_0603_10V4Z
1
2
C1086
8110S@0.1U_0402_16V4Z
1
2
Y5
25MHZ_20P
12
R1290 8100C@0_0805_5%
1 2
R1275
49.9_0402_1%
12
C1079
0.1U_0402_16V4Z
1
2
C1112
8110S@0.1U_0402_16V4Z
1
2
C1101
0.1U_0402_16V4Z
1
2
C1096
0.1U_0402_16V4Z
1
2
Q123
8110S@2SB1188_SOT89
3
1
2
C1075
8110S@4.7U_0805_10V4Z
1
2
C1098
0.1U_0402_16V4Z
1
2
R1278
49.9_0402_1%
12
C1087
8110S@0.1U_0402_16V4Z
1
2
C1093
10U_0805_10V4Z
1
2
C1102
0.1U_0402_16V4Z
1
2
C1108
0.1U_0402_16V4Z
1
2
C1085
8110S@0.1U_0402_16V4Z
1
2
C1074
0.1U_0402_16V4Z
1
2
R1276
49.9_0402_1%
12
C1076
8110S@0.1U_0402_16V4Z
1
2
C1115
8110S@0.1U_0402_16V4Z
1
2
C1100
1000P_1206_2KV7K
1 2
R1266
1K_0402_5%
12
R1286 8110S@0_0805_5%
1 2
C1092
0.1U_0402_16V4Z
1
2
R1287 8100C@0_0805_5%
1 2
C1105
@15P_0402_50V8D
1
2
C1089
27P_0402_50V8J
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XTPBIAS0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD30
PCI_AD29
PCI_AD31
XTPA0-
XTPA0+
XTPB0-
XTPB0+
XO
XI
EEDI_LAN
XI
XTPBIAS0
EECK_LAN
PCI_AD0
XO
XTPA0+PCI_AD16 XTPA0-
XTPB0+
PCI_AD[0..31]
XTPB0-
EEDI_LAN
EECK_LAN
CLK_PCI_1394
PCI_REQ#0<26>
CLK_PCI_1394<26>
PCI_PIRQA#<10,17,26,31>
PCI_PERR#<26,31,33,41> PCI_STOP#<26,31,33,41>
PCI_DEVSEL#<26,31,33,41>
PCI_PAR<26,31,33,41>
PCI_AD[0..31]<26,29,31,33,41>
PCI_RST#<11,26,30,31,33,38,41,44>
PCI_FRAME#<26,31,33,41> PCI_IRDY#<26,31,33,41>
PCI_CBE#0<26,31,33,41>
PCI_TRDY#<26,31,33,41>
PCI_CBE#1<26,31,33,41> PCI_CBE#2<26,31,33,41> PCI_CBE#3<26,31,33,41>
PCI_GNT#0<26>
1394_PME# <33,41,44,45>
+3VS
+3V_1394
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
IEEE 1394 CONTROLLER
34 65,
星期三
07, 2004
七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Note:These components need to close to chip pins.
C683
0.1U_0402_16V4Z
1
2
JP33
FOX_UV31413-4R1-TR
1
1
3
3
55
66
4
4
2
2
R727
4.99K_0603_1%
12
R715
560_0402_5%
1 2
R721
54.9_0402_1%
12
C694
0.1U_0402_16V4Z
1
2
C687
0.1U_0402_16V4Z
1
2
R1312
1K_0402_5%
R1310
0_0402_5%
1 2
C700
0.1U_0402_16V4Z
1
2
C695
0.1U_0402_16V4Z
1
2
C690
0.1U_0402_16V4Z
1
2
C686
0.1U_0402_16V4Z
1
2
IEEE 1394
VT6301S
PCI Bus
NC
OSC
1394 Differential Pairs
EEPROM
I/F
Power
PM & Test
U42
VT6301S-CD_LQFP128
AD27
98
AD28
97
AD29
96
AD30
95
AD31
94
AD15
2AD14
3AD13
4AD12
7AD11
8AD10
9AD9
10 AD8
11 AD7
14 AD6
15 AD5
16 AD4
18 AD3
19 AD2
20 AD1
24 AD0
25
AD26
101 AD25
102 AD24
103 AD23
106 AD22
107 AD21
109 AD20
113 AD19
114 AD18
115 AD17
116 AD16
117
CBE1#
1CBE0#
12
CBE3#
104 CBE2#
119
VCC 99
VCC 110
VCC 122
VCC 5
VCC 17
VCC 32
VCC 111
VCC 21
IDSEL
105
FRAME#
120
IRDY#
121
TRDY#
123
DEVSEL#
124
STOP#
125
PERR#
127
PAR
128
REQ#
93
GNT#
92
INTA#
88
PCIRST#
89
PCICLK
90
GND 56
PVA 59
TPBIAS0 71
TPA0P 70
TPA0M 69
TPB0P 68
TPB0M 67
XREXT 63
XCPS 60
XO
58
XI
57
PME# 34
PVA 62
GND 61
EECS 26
EEDO 27
EEDI/SDA 28
EECK/SCL 29
PVD 36
PVD 46
VCC 30
PHYRESET# 55
PVA 72
PVA 73
PVA 86
PVA 87
GND 65
GND 66
GND 79
GND 80
GND 91
GND 100
GND 108
GND 118
GND 126
GND 6
GND 13
GND 23
GND 33
GND 112
GND 22
GND 38
GND 47
GND 31
NC
45
NC
48
NC
49
NC
50
NC
37
NC
51
NC
52
NC
53
NC
54
NC
40
NC
39
NC
35
NC
74
NC
75
NC
76
NC
77
NC
78
NC
64
NC
81
NC
82
NC
83
NC
84
NC
85
I2CEN
43
CARDEN
44
NC
41
NC
42
C685
0.1U_0402_16V4Z
1
2
C699
10P_0402_50V8K
1
2
R1315
1M_0402_5%
C693
0.1U_0402_16V4Z
1
2
R5 @4.7K_0402_5%
R726
@10_0402_5%
12
C703
@18P_0402_50V8K
1
2
C698
10P_0402_50V8K
1
2
C702
270P_0402_25V8K
1
2
C688
0.1U_0402_16V4Z
1
2
U33
AT24C02N-10SC-2.7_SO8
A0
1
A1
2
SDA 5
SCL 6
VCC 8
A2
3
GND
4
WC 7
R723
54.9_0402_1%
12
L44
FCM2012C-800_0805
1 2
R1311
1K_0402_5%
C701
0.33U_0603_16V4Z
1
2
R717
100_0402_1%
1 2
R711 4.7K_0402_5%
X3
24.576MHz_16P_3XG-24576-43E1
1 2
C691
0.1U_0402_16V4Z
1
2
R720
54.9_0402_1%
12
C705
47P_0402_50V8J
1
2
C684
0.1U_0402_16V4Z
1
2
R722
54.9_0402_1%
12
R716
6.34K_0402_1%
C689
0.1U_0402_16V4Z
1
2
C692
0.1U_0402_16V4Z
1
2
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
SYSON#
SYSON#
USB20P1-
USB20P1+
USB20P2-
USB20P2+
USB20P0-
USB20P0+
USB20P3-
USB20P3+
USB20P2+<27> USB20P2-<27>
USB20P3+<27> USB20P3-<27>
USB20P1-<27> USB20P1+<27>
OVCUR#2 <27>
OVCUR#3 <26>
OVCUR#1 <27>
OVCUR#0 <27>
USB20P0+<27> USB20P0-<27>
SYSON#<47>
+USB_AS
+USB_AS
+USB_CS
+USB_CS
+USB_AS
+5VALW
+5VALW +USB_CS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
USB2.0 Connector
35 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
W=40mils
W=40mils
W=40mils
W=40mils
C1138@2.2P_0402_50V8C 1
2
JP18
suyin_020167mr004s511zu_4p
1
2
3
4
R896 0_0402_5%
1 2
+
C312
150U_D2_6.3VM
1
2
C308
0.1U_0402_10V6K
1
2
C1008
4.7U_0805_10V4Z
1
2
+
C315
150U_D2_6.3VM
1
2
C1000
0.1U_0402_10V6K
1
2
R894 0_0402_5%
1 2
+
C307
150U_D2_6.3VM
1
2
C314
1000P_0402_50V7K
1
2
C1002
4.7U_0805_10V4Z
1
2
C1134@2.2P_0402_50V8C 1
2
C1139
@2.2P_0402_50V8C
1
2
+
C1001
150U_D2_6.3VM
1
2
JP19
suyin_020167mr004s511zu_4p
1
2
3
4
U13
G528_SO8
GND
1
IN
2
FLG 5
OUT 6
OUT 8
IN
3
EN#
4
OUT 7
C1140@2.2P_0402_50V8C 1
2
C1135
@2.2P_0402_50V8C
1
2
C316
0.1U_0402_10V6K
1
2
C999
1000P_0402_50V7K
1
2
C1136@2.2P_0402_50V8C 1
2
U14
G528_SO8
GND
1
IN
2
FLG 5
OUT 6
OUT 8
IN
3
EN#
4
OUT 7
C309
1000P_0402_50V7K
1
2
JP20
suyin_020167mr004s511zu_4p
1
2
3
4
C313
0.1U_0402_10V6K
1
2
C317
1000P_0402_50V7K
1
2
C1137
@2.2P_0402_50V8C
1
2
JP48
suyin_020167mr004s511zu_4p
1
2
3
4
C1133
@2.2P_0402_50V8C
1
2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
+VDDA
MICIN
CD_GNA
MDC_RC_SPKMDC_R_SPK
CDROM_RC_L
CDROM_RC_R
AFILT1
AFILT2
CDGNDA
CDROM_R_R
NBA_PLUG
AUD_REF
CDROM_R_L
HP_SENSE
CLK_14M_CODEC
CDROM_R<30>
MIC_IN<37>
LINE_OUTL <37>
AC97_RST#<27,42>
AC97_SDOUT<27,29,42>
LINE_OUTR <37>
CD_AGND<30>
AC97_SDIN0 <27>
AC97_BITCLK <27,42>CDROM_L<30>
AC97_SYNC<27,29,42>
MD_SPK<42>
LINE_IN_L<37>
LINE_IN_R<37>
NBA_PLUG<37>
EAPD<37>
MONO_IN<37>
CLK_14M_CODEC <24>
+VDDA
+5VAMP
+5VS
+AVDD_AC97
+3VS +AUD_VREF
+3VS
+AUD_VREF
+AUD_VREF
+VDDA
+AVDD_AC97
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
AC97 CODEC
Custom 36 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R771
24.576MHz Crystal
or External Colck
MODE
14.318MHz External
Stuff
No-Stuff
40mil
10mil
GND GNDA
40mil
R736
150K_0603_1%
12
C735 1U_0603_10V4Z
1 2
R771 0_0402_5%
1 2 C751
@1U_0603_10V4Z
1 2
C750
1U_0603_10V4Z
1 2
R1143
@10_0402_5%
12
C737 1U_0603_10V4Z
1 2
R1199 0_0402_5%
1 2
C730
10U_0805_10V4Z
1
2
C985 4.7U_0805_10V4Z
1 2
Y6 @24.576MHz_16P_3XG-24576-43E1
1 2
R1200 @47K_0402_5%
1 2
C720
0.1U_0402_16V4Z
1
2
C1018
0.1U_0402_16V4Z
1
2
C991 1U_0603_10V4Z
1 2
R757 2.7K_0402_5%
1 2
C10 27P_0402_50V8J
1 2
C747
0.01U_0402_16V7K
1
2
C992 1U_0603_10V4Z
1 2
C1025
@22P_0402_50V8J
1
2
R749 4.7K_0402_5%
1 2
C715
22U_1206_10V4Z
1
2
R762
2.4K_0402_5%
12
C986 4.7U_0805_10V4Z
1 2
C1024
10U_0805_10V4Z
1
2
C1023
0.1U_0402_16V4Z
1
2
C904 1U_0603_10V4Z
1 2
C1026
@22P_0402_50V8J
1
2
C716
10U_0805_10V4Z
1
2
C746
0.1U_0402_16V4Z
1
2
R1201
22_0402_5%
12
C1021 1000P_0402_50V7K
1 2
R1202 22_0402_5%
12
C736 1U_0603_10V4Z
1 2
C752
1000P_0402_50V7K
1
2
R1205
@1M_0402_5%
1 2
C745
1U_0603_10V4Z
1
2
R1196 0_0805_5%
1 2
C749 1U_0603_10V4Z
1 2
R755 2.7K_0402_5%
12
C1022
1U_0603_10V4Z
1 2
C1020 1000P_0402_50V7K
1 2
U46
SI9182DH-AD_MSOP8
VIN
4
SD
8
VOUT 5
GND 3
SENSE or ADJ 6
ERROR
7CNOISE 1
DELAY
2
R1197 0_0805_5%
1 2
C984
1000P_0402_50V7K
1
2
R1198 0_0805_5%
1 2
R7
1M_0402_5%
1 2
C729
0.1U_0402_16V4Z
1
2
R1295 0_0402_5%
12
C990
0.1U_0402_16V4Z
1
2
L30
KC FBM-L11-201209-221LMAT_0805
1 2
C717
10U_0805_10V4Z
1
2
R761
10K_0402_5%
12
L31
CHB2012U170_0805
1 2
C734 1U_0603_10V4Z
1 2
C989
0.1U_0402_16V4Z
1
2
R752 4.7K_0402_5%
12
L29
KC FBM-L11-201209-221LMAT_0805
1 2
R737
51K_0603_1%
12
C1019 @0.1U_0402_16V4Z
12
R751 4.7K_0402_5%
1 2
R748 4.7K_0402_5%
12
C973
@15P_0402_50V8J
C905
0.1U_0402_16V4Z
1
2
U47
ALC250_LQFP48
AUX_L
14
AUX_R
15
JD1
17
JD2
16
LINE_IN_L
23
LINE_IN_R
24
CD_L
18
CD_R
20
CD_GND
19
MIC1
21
MIC2
22
PHONE
13
PC_BEEP
12
LINE_OUT_L 35
LINE_OUT_R 36
MONO_OUT/VREFOUT3 37
RESET#
11
SYNC
10
BIT_CLK 6
SDATA_OUT
5
SDATA_IN 8
XTL_IN 2
XTL_OUT 3
AFILT1 29
AFILT2 30
VREFOUT 28
VREF 27
DVDD1 1
DVDD2 9
AVDD1 25
AVDD2 38
DCVOL 32
XTLSEL
46
SPDIFI/EAPD
47
SPDIFO
48
DVSS1
4
DVSS2
7
NC 31
VREFOUT2 33
VAUX 34
SCK 43
SDA 44
NC
45
NC 40
AVSS1 26
AVSS2 42
HP_OUT_L 39
HP_OUT_R 41
C1017
1U_0603_10V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MONO_IN1
EAPD
SHUTDOWN#
NBA_PLUG
VOL_AMP
NBA_PLUG
LEFT_2
HP_L
LINE_OUTL
HP_R
RIGHT_2
LINE_OUTR
SPKL+
SPKR+
BYPASS
SPKR-
SPKL-
VOL_AMP
NBA_PLUG
INTSPK_R1-2
INTSPK_L1-2
INTSPK_R1-3
INTSPK_L1-3
INTSPK_R1-4
INTSPK_L1-4
SPKL+
SPKR+
LINE_IN_L-1
LINE_IN_R-1
INT_MIC
LINE_IN_L-1
LINE_IN_R-1
SPKL+
SPKL-
SPKR+
SPKR-
PCM_SPK#<31>
SB_SPKR<27>
BEEP#<44>
NBA_PLUG<36>
LINE_OUTR<36>
LINE_OUTL<36>
EAPD <36>
MONO_IN <36>
MIC_IN<36>
LINE_IN_L<36>
LINE_IN_R<36>
+3VALW
+3VALW
+3VALW
+VDDA
+3VALW
+3VALW
+5VAMP
+5VAMP
+5VAMP
+5VAMP
+AUD_VREF
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
AMP & Audio Jack
37 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
W=40Mil
(0.65V -> 10dB )
LOW
HIGH
PIN 5,23 ACTIVE
PIN 6,20 ACTIVE
Pin 2
Internal MIC
EXT.
MICPHONE
JACK
R739
560_0402_5%
1 2
R733
10K_0402_1%
12
C712
1U_0603_10V6K
12
C1012
0.47U_0603_16V4Z
1
2
C8950.47U_0603_16V4Z
1 2
L28
FBM-11-160808-700T_0603
1 2
C1063
220P_0402_50V7K
1
2
R973
100K_0402_5%
12
L68 FBM-11-160808-700T_0603
1 2
R741
560_0402_5%
1 2
U45C
SN74LVC14APWLE_TSSOP14
O6
I
5
P14
G
7
C714 1U_0603_10V6K
12
C891
0.1U_0402_16V4Z
1
2
JP51
AMP_1-1470184-2
1
2
3
4
5
6
C1132
@220P_0402_50V7K
1
2
+
C1058
150U_D2_6.3VM
1 2
R974 100K_0402_5%
1 2
L65 FBM-11-160808-700T_0603
1 2
R1241
47_0402_5%
1 2
C
B
E
Q56
2SC2411K_SOT23
1
2
3
C722
1U_0603_10V6K
12
JP50
AMP_1-1470184-2
1
2
3
4
5
6
R742
10K_0402
12
C774
4.7U_0805_10V4Z
1
2
R1240
47_0402_5%
1 2
C1011
1U_0603_10V4Z
1
2
R732
560_0402_5%
1 2
C1131
@220P_0402_50V7K
1
2
D46
RB751V_SOD323
2 1
C257
220P_0402_50V7K
1
2
R1063
39K_0603_1%
1 2
U18B
SN74LVC32APWLE_TSSOP14
A
4
B
5O6
P14
G
7
L27
FBM-11-160808-700T_0603
1 2
C1014 0.1U_0402_16V4Z
1 2
R729
@100K_0402_1%
12
C713
0.22U_0603_10V7K
1
2
R1245
2.2K_0402_5%
12
L24
FBM-11-160808-700T_0603
1 2
C979
0.1U_0402_10V6K
1
2
C773
0.1U_0402_16V4Z
1
2
C719
1U_0603_25V4Z
1 2
C894
0.47U_0603_16V4Z
1 2
+
C1059
150U_D2_6.3VM
1 2
R738
10K_0402_5%
1 2
U52
TPA0232PWP_TSSOP24
HP/LINE#
2
VOLUME
3
LOUT+
4
ROUT+
21
LLINEIN
5
LHPIN
6
RHPIN
20
PVDD
7
PVDD
18
VDD
19
RLINEIN
23
GND 24
GND 13
GND 12
GND 1
RIN 8
LIN 10
ROUT- 16
LOUT- 9
BYPASS 11
PC-BEEP 14
SE/BTL# 15
CLK
17
SHUTDOWN# 22
MIC1
@WM-64PCY_2P
1
2
L25
FBM-11-160808-700T_0603
1 2
L66 FBM-11-160808-700T_0603
1 2
C896 0.47U_0603_16V4Z
1 2
C890
0.47U_0603_16V4Z
1 2
C1130
@220P_0402_50V7K
1
2
C721
1U_0603_10V6K
12
C1060
330P_0402_50V7K
1
2
JP34
ACES_85205-0400
1
1
2
2
3
3
4
4
U45A
SN74LVC14APWLE_TSSOP14
O2
I
1
P14
G
7
L23
FBM-11-160808-700T_0603
1 2
R972
1.5K_0402_1%
12
C1013
0.47U_0603_16V4Z
1
2
C1061
330P_0402_50V7K
1
2
C892
0.047U_0603_16V7K
1
2
U32F
SN74LVC14APWLE_TSSOP14
O12
I
13
P14
G
7
L67 FBM-11-160808-700T_0603
1 2
R731
10K_0402_1%
1 2
C1129
@220P_0402_50V7K
1
2
R1246
@2.2K_0402_5%
12
R735
10K_0402_1%
12
R971
10K_0402_5%
12
G
D
S
Q119
2N7002_SOT23
2
13
C1062
220P_0402_50V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M11_UMA_DET#
IRRX
DCD#1
RI#1
CTS#1
DSR#1
LPCPD# IRTXOUT
IRRX
CTS#1
RTS#1
RI#1
TXD1
DCD#1
DTR#1
DSR#1
PCI_CLKRUN#
RXD1
LPC_DRQ#1
LPC_AD3
LPC_AD0
LPC_AD1
LPC_AD2
LPC_FRAME#
CLK_PCI_SIO IRMODE
PCI_RST#
CLK_14M_SIO
IO_PME#
CLK_14M_SIOCLK_PCI_SIO
DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
MDC_DET#
CTS#1
RTS#1
RI#1
TXD1
DCD#1
DTR#1
DSR#1
RXD1
IRTXOUT
IRRX
IRMODE
LPC_AD3
LPC_AD0
LPC_AD1
LPC_AD2
CLK_PCI_SIO
LPC_FRAME#
LPC_DRQ#1
PCI_RST#
SIRQ
SIRQ
PCI_CLKRUN#
CLK_14M_SIO
LPCPD#
IO_PME#
MDC_DET#
M11P_M11C_DET#
M11_UMA_DET#
M11P_M11C_DET#
MDC_DET#<42>
IRRX <43>
IRTXOUT <43>
CLK_PCI_SIO<26>
PCI_CLKRUN#<26,33,41,44>
LPC_DRQ#1<26>
LPC_AD3<26,44>
LPC_AD1<26,44> LPC_AD2<26,44>
LPC_AD0<26,44>
IRMODE <43>
PCI_RST#<11,26,30,31,33,34,41,44>
LPC_FRAME#<26,44>
CLK_14M_SIO<24>
SIRQ<26,31,44>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+5V
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
LPC SUPER I/O VIA VT1211
38 65,
星期三 七
07, 2004
月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SUPER I/O SMsC FDC47N217
Base I/O Address
0 = 02Eh
1 = 04Eh
*
0 = UMA
1 = M11
0 = M11C
1 = M11P
none = UMA
R798 10K_0402_5%
1 2
RP151
4.7K_8P4R_1206_5%
1 8
2 7
3 6
4 5
R797
@1K_0402_5%
1 2
R1292 @10K_0402
12
R790
10_0402_5%
12
R1291 10K_0402
12
C788
18P_0402_50V8K
1
2
LPC I/F
SERIAL I/F
DLPC I/F
IR GPIO
U50
@LPC47N207-JN_STQFP64
LAD0
64
LAD1
2
LAD2
4
LAD3
7
LDRQ1#
12
LDRQ0#
24
LFRAME#
14
CLKRUN#
16
SERIRQ
19
PCI_CLK
21
PCIRST#
22
SIO_14M
23
DLAD0
63
DLAD1
1
DLAD2
3
DLAD3
6
DLPC_CLK_33
9
DLDRQ1#
11
DLFRAME#
13
DCLKRUN#
15
DSER_IRQ
18
DSIO_14M
26
LPCPD#
25
LPC_CLK_33
10
IO_PME#
47
3.3V 5
3.3V 17
3.3V 31
3.3V 42
3.3V 60
VTR 48
IRRX2 50
IRTX2 49
IRMODE/IRRX3 51
RXD1 52
TXD1 53
DRSR1# 54
RTS1#/SYSOPT0 55
CTS1# 56
DTR1#/SYSOPT1 57
RI1# 58
DCD1# 59
GPIO10 27
GPIO11 28
GPIO12/IO_SMI# 30
GPIO13/IRQIN1 32
GPIO14/IRQIN2 33
GPIO15 34
GPIO16 35
GPIO17 36
GPIO30 38
GPIO31 39
GPIO32 40
GPIO33 41
GPIO34 43
GPIO35 44
GPIO36 46
GPIO37 61
GND0
8
GND1
20
GND2
29
GND3
37
GND4
45
GND5
62
R792 10K_0402_5%
1 2
C785
0.1U_0402_16V4Z
1
2
R791
@10_0402_5%
12
POWER
CLOCK
GPIO
LPC I/F
SERIAL I/F
FIR
PARALLEL I/F
U51
LPC47N217_STQFP64
LAD0
10
LAD1
12
LAD2
13
LAD3
14
LFRAME#
15
LDRQ#
16
PCI_RESET#
17
LPCPD#
18
CLKRUN#
19
PCI_CLK
20
SER_IRQ
21
IO_PME#
6
RXD1 62
TXD1 63
DSR1# 64
RTS1# 1
CTS1# 2
DTR1# 3
RI1# 4
DCD1# 5
IRRX2 37
IRTX2 38
IRMODE/IRRX3 39
INIT# 41
SLCTIN# 42
PD0 44
PD1 46
PD2 47
PD3 48
PD4 49
PD5 50
PD6 51
PD7 53
SLCT 55
PE 56
BUSY 57
ACK# 58
ERROR# 59
ALF# 60
STROBE# 61
GPIO40
23
GPIO41
24
GPIO42
25
GPIO43
27
GPIO44
28
GPIO45
29
GPIO46
30
GPIO47
31
GPIO10
32
GPIO11/SYSOPT
33
GPIO12/IO_SMI#
34
GPIO13/IRQIN1
35
GPIO14/IRQIN2
36
GPIO23
40
CLK14
9
VTR 7
VCC 26
VCC 54
VSS
8
VSS
22
VSS
43
VSS
52 VCC 45
VCC 11
R1174 @10K_0402
12
C780
0.1U_0402_16V4Z
1
2
C789
@10P_0402_25V8K
1
2
R991 @10K_0402_5%
1 2
R795 10K_0402_5%
1 2
R787 10K_0402_5%
1 2
R1173 10K_0402
12
C787
0.1U_0402_16V4Z
1
2
R992 @10K_0402_5%
1 2
R796 1K_0402_5%
1 2
R793 10K_0402_5%
1 2
JP49
@96212-1011S
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
R794
1K_0402_5%
1 2
C784
4.7U_0805_10V4Z
1
2
R80 @10K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
SPR Connector
39 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
EMI Clip PAD
CF5
1
H1
HOLEA
1
H28
HOLEA
1
CF16
1
H20
HOLEA
1
CF4
1
H22
HOLEA
1
H8
HOLEA
1
FM5
1
CF2
1
CF15
1
H30
HOLEA
1
CF20
1
H17
HOLEA
1
FM3
1
H31
HOLEA
1
H19
HOLEA
1
H6
HOLEA
1
CF6
1
CF18
1
CF7
1
H23
HOLEA
1
CF13
1
H10
HOLEA
1
H16
HOLEA
1
H7
HOLEA
1
CF11
1
CF17
1
H24
HOLEA
1
CF9
1
FM2
1
H18
HOLEA
1
CF21
1
EP1
EMI-126X142
1
FM1
1
H13
HOLEA
1
FM6
1
H27
HOLEA
1
CF24
1
CF3
1
CF8
1
H3
HOLEA
1
CF1
1
CF22
1
H14
HOLEA
1
CF19
1
H4
HOLEA
1
H12
HOLEA
1
H26
HOLEA
1
H9
HOLEA
1
FM4
1
H21
HOLEA
1
H2
HOLEA
1
CF14
1
CF12
1
CF23
1
H5
HOLEA
1
CF10
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TP_DATA
TP_CLK
EN_WL#
EN_BT#
WL_ON_LED#
BT_ON_LED#
EN_WL#EN_BT#
CAPSLED#<44> NUMLED#<44> MEDIA_LED#<44>
PWR_SUSP_LED#<44> PWR_LED#<44> BATT_FULL_LED#<44> BATT_CHGI_LED#<44>
EN_WL#<44> EN_BT#<44>
WL_ON_LED#<44> BT_ON_LED#<44>
TP_DATA<44> TP_CLK<44>
E_MAIL_LED#<44>
+5VALW +5VALW +5VALW
+5VALW
+5VS
+3VALW+3VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
LED INDICATOR
B
40 65
星期
, 07, 2004
三七月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
(GRN) (GRN) (GRN) (GRN)
D62
HT-170UYG-DT GRN_0805
21
D60
HT-170UYG-DT GRN_0805
21
D65
HT-170UYG-DT GRN_0805
21
R889
360_0603_5%
1 2
R885
360_0603_5%
1 2
R925
360_0603_5%
1 2
R890
360_0603_5%
1 2
D63
HT-170UYG-DT GRN_0805
21
R923
360_0603_5%
1 2
JP53
ACES_85201-2005
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
16
16
17
17
18
18
15
15
20
20 19
19
R882
360_0603_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
WLAN_PME#
PCI_AD18
PCI_PIRQD#
PCI_AD18
CLK_PCI_MINI PCI_AD22
CLK_PCI_MINI
PCI_PIRQC#
WL_ON
PCI_AD14<26,31,33,34>
PCI_GNT#3 <26>
PCI_CLKRUN#<26,33,38,44>
PCI_AD18 <26,31,33,34>
PCI_PERR#<26,31,33,34>
PCI_AD16 <26,31,33,34>
PCI_AD3<26,31,33,34>
PCI_AD29<26,31,33,34>
PCI_AD21<26,31,33,34>
PCI_PAR <26,31,33,34>
PCI_AD20 <26,31,33,34>
PCI_PIRQD#<26,33>
PCI_AD15 <26,31,33,34>
PCI_AD17<26,31,33,34>
PCI_AD5<26,31,33,34>
PCI_CBE#2<26,31,33,34>
PCI_SERR#<26,31,33>
PCI_AD11 <26,31,33,34>
PCI_AD23<26,31,33,34>
PCI_AD8<26,31,33,34>
WLAN_PME# <33,34,44,45>
PCI_AD28 <26,31,33,34>
PCI_STOP# <26,31,33,34>
PCI_AD2 <26,31,33,34>
PCI_AD12<26,31,33,34>
PCI_AD26 <26,29,31,33,34>
PCI_AD9 <26,31,33,34>
PCI_AD31<26,31,33,34>
PCI_RST# <11,26,30,31,33,34,38,44>
PCI_AD30 <26,31,33,34>
PCI_AD7<26,31,33,34>
PCI_AD25<26,31,33,34>
PCI_AD10<26,31,33,34>
PCI_REQ#3<26>
PCI_IRDY#<26,31,33,34>
PCI_AD6 <26,31,33,34>
PCI_AD24 <26,31,33,34>
PCI_CBE#0 <26,31,33,34>
PCI_AD0 <26,31,33,34>
PCI_DEVSEL# <26,31,33,34>
PCI_FRAME# <26,31,33,34>
PCI_CBE#3<26,31,33,34>
PCI_GNT#4 <26>PCI_REQ#4<26>
PCI_TRDY# <26,31,33,34>
PCI_AD27<26,31,33,34>
PCI_AD13 <26,31,33,34>
PCI_AD22 <26,31,33,34>
PCI_AD19<26,31,33,34>
PCI_AD4 <26,31,33,34>
PCI_AD1<26,31,33,34>
CLK_PCI_MINI<26>
PCI_CBE#1<26,31,33,34>
WL_ON<44>
WLAN_BT_CLK <42>
WLAN_BT_DATA<42>
PCI_PIRQC# <26>
+5VS
+3VS
+3V
+5VS
+5VS
+3V
+3V
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
Mini PCI Slot
41 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
W=40mils
W=40mils
LAN RESERVED LAN RESERVED
TIP
W=40mils
W=40mils
IDSEL : AD18
RING
W=30mils
W=30mils
W=30mils
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R302
@10_0402_5%
12
C275
@15P_0402_50V8J
1
2
C286
1000P_0402_50V7K
1
2
KEY KEY
JP12
AMP_1318644-1
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
51
51 52 52
53
53 54 54
55
55 56 56
57
57 58 58
59
59 60 60
61
61 62 62
63
63 64 64
65
65 66 66
67
67 68 68
69
69 70 70
71
71 72 72
73
73 74 74
75
75 76 76
77
77 78 78
79
79 80 80
81
81 82 82
83
83 84 84
85
85 86 86
87
87 88 88
89
89 90 90
91
91 92 92
93
93 94 94
95
95 96 96
97
97 98 98
99
99 100 100
101
101 102 102
103
103 104 104
105
105 106 106
107
107 108 108
109
109 110 110
111
111 112 112
113
113 114 114
115
115 116 116
117
117 118 118
119
119 120 120
121
121 122 122
123
123 124 124
127
127
128
128
C284
4.7U_0805_10V4Z
1
2
C272
0.1U_0402_10V6K
1
2
C285
0.1U_0402_10V6K
1
2
D89 RB751V_SOD323
21
C278
1000P_0402_50V7K
1
2
C281
4.7U_0805_10V4Z
1
2
C269
0.1U_0402_10V6K
1
2
C277
0.1U_0402_10V6K
1
2
C274
0.1U_0402_10V6K
1
2
C276
4.7U_0805_10V4Z
1
2
C280
4.7U_0805_10V4Z
1
2
C270
1000P_0402_50V7K
1
2
C271
0.1U_0402_10V6K
1
2C273
1000P_0402_50V7K
1
2
R301 100_0402_5%
1 2
+5VMDC
MRING
BT_VCC
TIP
BT_VCC
USB5-
USB5+
MDC_DET# <38>
AC97_SYNC <27,29,36>
AC97_SDIN1 <27>
AC97_RST#<27,36>
MD_SPK <36>
AC97_BITCLK <27,36>
AC97_SDOUT<27,29,36>
USB20P5-<27> USB20P5+<27>
WLAN_BT_DATA<41> WLAN_BT_CLK<41>
BT_ON#<44>
+3VS +5VS
+3V
+3VS
+3V
+3VS
+3V
+3VALW
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
MDC , Bluetooth & USB CONN.
42 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MDC Conn.
RJ11 CONN.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BT CONNECTOR
R22 0_0402_5%
1 2
C299
@0.1U_0402_10V6K
1
2
R323 10K_0402_5%
1 2
JP16
FOXCONN_JM34613-L002-TR
3
3
4
466
55
1
1
2
2
JP43
ACES_87213-0800
1
1
3
3
5
5
6
6
4
4
2
2
7
7
8
8
R320
100K_0402_5%
1 2
R319 0_0805_5%
1 2
G
D
S
Q99
SI2301DS_SOT23
2
1 3
C977
@220PF_3KV_1808
12
C958
0.1U_0402_10V6K
1
2
L46
0_0603_5%
12
R325 22_0402_5%
12
JP47
MOLEX_53398_0290
1
1
2
2
C978
@220PF_3KV_1808
12
C304
0.1U_0402_10V6K
1
2
R981 0_0402_5%
1 2
C955
0.1U_0402_10V6K
1
2
R326 22_0402_5%
12
C298
@1000P_0402_50V7K
1
2
C954
1000P_0402_50V7K
1
2C302 @1000P_0402_50V7K
12
C305
@22P_0402_25V8K
1
2
C301
0.1U_0402_10V6K
1
2
R980 0_0402_5%
1 2
L45
0_0603_5%
12
R21 0_0402_5%
1 2
C300
1000P_0402_50V7K
1
2
C303
4.7U_0805_10V4Z
1
2
C957
10U_0805_10V3M
1
2
R327
@10_0402_5%
1 2
JP17
ACES_88021-3000
MONO_OUT/PC_BEEP
1
GND
3
AUXA_RIGHT
5
AUXA_LEFT
7
CD_GND
9
CD_RIGHT
11
CD_LEFT
13
GND
15
AC97_SDATA_OUT
23 3.3Vmain
21
3.3Vaux
17
GND
19
AC97_RESET#
25
GND
27
AC97_MSTRCLK
29
AUDIO_PWDN 2
MONO_PHONE 4
Bluetooth Enable 6
GND 8
+5V 10
USB Data+ 12
USB Data- 14
PRIMARY DN 16
5Vd 18
GND 20
AC97_SYNC 22
AC97_SDATA_IN1 24
AC97_SDATA_IN0 26
GND 28
AC97_BITCLK 30
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ON/OFFBTN#
EC_ON
ON/OFF#
KSI[0..7]
KSO[0..15]
ON/OFFBTN#
KSI3
KSO15
KSO5
KSO1
KSI4
KSO7
KSI6
KSO4
KSI1
KSO14
KSO10
KSO2
KSI7
KSO8
KSO6
KSO13
KSO9
KSI5
KSO12
KSI2
KSO0
KSO3
KSO11
KSI0
KSO10
KSI1
KSO11
KSI0
KSO15
KSO14
KSO13
KSO12
KSO5
KSO7
KSO4
KSO6
KSI3
KSO8
KSI2
KSO9
KSO3
KSO2
KSO1
KSI4
KSI5
KSO0
KSI6
KSI7
KSO16 KSO16 KSO16 KSO16
+IR_3VS IRMODEIRRX IRTXOUT
EC_PWR_ON# <48>
ON/OFF# <44>
LID_SW# <44>
EC_ON<44>
KSO[0..15] <44>
KSI[0..7] <44>
KSI0 <44> KSI1 <44> KSI2 <44> KSI3 <44>KSO16<44>
IRMODE <38>IRRX<38> IRTXOUT <38>
+3VALW
+3VALW
+3VS
+3VS
+IR_ANODE
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
KBD,ON/OFF,T/P,LED & FIR
43 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
FIR Module
Power BTN
WHEN R=33K,Vbe=0.8V
WHEN R=0,Vbe=1.35V
INT_KBD CONN.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Internet ButtonConsole/E-MAIL Button USER Button1 USER Button 2
(60mil)
Vishay populate two 4.7 Ohm resistor
Agilent populate one 4.7 Ohm resistor
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT
(30mil)
(60mil)
Vishay = 47 Ohm
Agilent = 0 Ohm
(Left)
(Right)
22K
22K
Q21
DTC124EK_SOT23
2
13
R309 4.7_1206_5%
1 2
D29
RLZ20A_LL34
12
R306
470_0402_5%
12
SW8
PTC010-PS11CET_5P
2
3
1
4
5
R1204
0_1206_5%
1 2
R307 0_0402_5%
1 2
D27 @PSOT03C
3
2
CP4
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
SW9
ESE11MV9_4P
2
4
1
3
JP13
ACES_85202-2405
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
C294
0.1U_0402_16V4Z
1
2
D28
DAN202U_SC70
2
3
1
R305 100K_0402_5%
1 2
D30 @PSOT03C
3
2
+
C292
@150U_D2_6.3VM
1 2
SW1
TC010-PS11CET_5P
2
3
1
4
5
SW10
PTC010-PS11CET_5P
2
3
1
4
5
CP1
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
R308 @4.7_1206_5%
1 2
CP2
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
C291
10U_0805_10V4Z
1
2
CP5
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
SW2
PTC010-PS11CET_5P
2
3
1
4
5
C289
1000P_0402_50V7K
1
2
G
D
S
Q112
@2N7002_SOT23 2
13
U12
HSDL-3603-007_9P
IRED_C
2
GND
8MODE 7
SD/MODE 5
IRED_A 1
RXD
4
VCC
6
TXD 3
GND 9
CP3
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
CP6
100P_1206_8P4C_50V8
2
3
4 5
6
7
81
SW11
PTC010-PS11CET_5P
2
3
1
4
5
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
ADB[0..7]
LID_SW#
SELIO#
FRD#
KBA3
KBA[0..19]
FSEL#
KBA5
EC_SMI#
KBA1
ECAGND
KBA2
SCI#
KBD_DATA
KBD_CLK
TP_DATA
TP_CLK
VR_ON
KBA19
KBA17
KBA9
CRY2
KSI0
ECAGND
KBA15
KBA5
ADP_IR
TP_CLK
KBD_DATA
KBD_CLK
KSO9
ECAGND
KSO14
KSO8
GA20
KBA18
KBA13
KBA7
KSO[0..15]
FSEL#
KBA11
EC_SMC_1
KSI5
SCI#
EC_SMD_1
KSO13
KSO12
KSO2
EC_SMI#
KSO15
KSO6
KSO5
KSI1
KBA10
KBA8
ADB1
EC_SMD_2
EC_USCLK
ADB6
KBA3
KBA1
KSO4
CLK_PCI_EC
EC_RST#
ADB3
KSO0
KSI3
KSI[0..7]
KBA16
KSO7
SELIO#
PS2_CLK
AC_IN
ADB5
ADB0
KBA6
KBA4
EC_SMC_2
PS2_DATA
KBA14
ADB7
ADB2
FANSPEED1
KSO3
SYSON
KBA12
FWR#
ADB4
TP_DATA
KSO1
KSI6
FRD#
KBA2
KBA0
LID_SW#
CRY1
KSI4
KBRST#
KSO11
KSI7
SUSP#
KSI2
KSO10
CLK_PCI_EC
VR_ON
SUSP#
BID
EC_UTXD
AC_IN
EC_TDI
EC_TCK
EC_TMS
EC_TDO
EC_TINIT#
KSO16
EC_UTXD
EC_USCLK
EC_TDI
EC_TDO
EC_TMS
EC_TCK
EC_TINIT# PCI_RST#
KBA0
KBA4
CRY2CRY1
EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1
PS2_DATA
PS2_CLK
KSO16
BID
SYSON
LPC_FRAME#<26,38>
ADB[0..7] <45>
LPC_AD1<26,38> LPC_AD2<26,38>
LPC_AD0<26,38>
KBA[0..19] <45>
SIRQ<26,31,38>
LPC_AD3<26,38>
ADP_I <49,50>
CLK_PCI_EC<26>
KSO[0..15]<43> KSI[0..7]<43>
TP_DATA<40>
FSEL#<45>
SUSP#<45,47>
EC_SWI#<27>
ENBKL<10,17>
EC_SMI#<27>
VR_ON<53>
BKOFF#<25>
SYSON<47>
ACIN <27,48,51>
GA20<27>
EC_RSMRST#<27>
SCI#<27>
PCI_RST# <11,26,30,31,33,34,38,41>
PME_EC# <33,34,41,45>
EN_BT#<40>
ON/OFF# <43>
CAPSLED# <40>
EC_THERM# <27>
EC_ON <43>
DAC_BRIG <25>
INVT_PWM <25>
EN_FAN2 <7>
FRD# <45>
SLP_S5# <27>
FWR# <45>
BEEP# <37>
FSTCHG <50>
PWRBTN_OUT# <27>
LID_SW#<43>
EN_FAN1 <7>
BATT_OVP <50>
FANSPEED2 <7>
FANSPEED1 <7>
NUMLED# <40>
EC_SMD_2 <7>
LID_OUT# <27>
EC_SMC_1 <45,49>
KBRST#<27>
SLP_S3# <27>
WL_ON <41>
SELIO# <45>
PM_BATLOW# <27>
EC_SMD_1 <45,49>
EC_SMC_2 <7>
ACOFF <50>
TP_CLK<40>
BATT_TEMPA <49>
IREF <50>
PCI_CLKRUN# <26,33,38,41>
EN_WOL#<33>
ACT_LED#<30> EN_WL#<40>
KSO16 <43>
BT_ON#<42>
CARD_LED#<31>
PWR_LED# <40>
BATT_FULL_LED# <40>
BATT_CHGI_LED# <40>
PWR_SUSP_LED# <40>
BT_ON_LED# <40>
WL_ON_LED# <40>
MEDIA_LED# <40>
E_MAIL_LED# <40>
+3VALW
+EC_AVCC
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
+3VALW
+5VS
+5VS
+5VS
+EC_AVCC
+3VALW
+5VALW
+3VALW
+3VALW
+3VALW +3VALW
+RTCVCC
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
KBD EC CTRL-ENE910
44 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
(BADDR1)
(BADDR0)
(ENV1)
(SHBM)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
For EC Tools
I/O Address
SHBM(KBA5)=1: Enable shared memory with host BIOS
0
1
0
4E
Reserved
ENV1 (KBA1)
0
ENV0 (KBA0) TRIS (KBA4)
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
11
PROG 0
2E 2F
4F
DEV 0
0
Data
OBD 0
1
Index
IRE
TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use
0
0
1
BADDR1(KBA3) BADDR0(KBA2)
0
0
01
11
*
*
KB910 87591
R341
R340 no stuff
0
20M
120K
*
R337
@10_0402_5%
12
C318
1000P_0402_50V7K
1
2
R1250
100K_0402_5%
1 2
C330
10P_0402_25V8K
1
2
R345 0_0402_5%
R929
100K_0402_5%
12
R333 1K_0402_5%
1 2
R1252 @1K_0402_5%
1 2
Host interface
Key matrix scan
JTAG debug port
PS2 interface
AD Input
DA output
PWM
or PORTA
PORTB
PORTC
PORTE
PORTH
PORTI
PORTJ-1
PORTD-1
PORTD-2
PORTJ-2
PORTK
PORTL
PORTM
U15
PC87591L-VPCN01 A2_LQFP176
GA20/IOPB5
5
KBRST/IOPB6
6
LAD0
15
LAD1
14
LAD2
13
LAD3
10
RESET1#
19
LFRAME#
9
SERIRQ
7
LCLK
18
IOPD3/ECSCI#
31
SMI#
22
PWUREQ#
23
LDRQ#
8
VDD 16
VCC1 34
VCC2 45
VCC3 123
VCC4 136
AVCC 95
VBAT 161
KBSIN0
71
KBSIN1
72
KBSIN2
73
KBSIN3
74
KBSIN4
77
KBSIN5
78
KBSIN6
79
KBSIN7
80
KBSOUT0
49
KBSOUT1
50
KBSOUT2
51
KBSOUT3
52
KBSOUT4
53
KBSOUT5
56
KBSOUT6
57
KBSOUT7
58
KBSOUT8
59
KBSOUT9
60
KBSOUT10
61
KBSOUT11
64
KBSOUT12
65
KBSOUT13
66
KBSOUT14
67
KBSOUT15
68
TCK
106
TDI
108 TDO
107
TINT#
105
TMS
109
PSCLK1/IOPF0
110
PSDAT1/IOPF1
111
PSCLK2/IOPF2
114
PSDAT2/IOPF3
115
PSCLK3/IOPF4
116
PSDAT3/IOPF5
117
PSCLK4/IOPF6
118
PSDAT4/IOPF7
119
32KX1/32KCLKIN
158
32KX2
160
AD0 81
AD1 82
AD2 83
AD3 84
IOPE0AD4 87
IOPE1/AD5 88
IOPE2/AD6 89
IOPE3/AD7 90
DP/AD8 93
DN/AD9 94
DA0 99
DA1 100
DA2 101
DA3 102
IOPA0/PWM0 32
IOPA1/PWM1 33
IOPA2/PWM2 36
IOPA3/PWM3 37
IOPA4/PWM4 38
IOPA5/PWM5 39
IOPA6/PWM6 40
IOPA7/PWM7 43
IOPB0/URXD 153
IOPB1/UTXD 154
IOPB2/USCLK 162
IOPB3/SCL1 163
IOPB4/SDA1 164
IOPB7/RING/PFAIL/RESET2 165
IOPC0 168
IOPC1/SCL2 169
IOPC2/SDA2 170
IOPC3/TA1 171
IOPC4/TB1/EXWINT22 172
IOPC5/TA2 175
IOPC6/TB2/EXWINT23 176
IOPC7/CLKOUT 1
IOPE4/SWIN 2
IOPE5/EXWINT40 44
IOPE6/LPCPD/EXWIN45 24
IOPE7/CLKRUN/EXWINT46 25
IOPH0/A0/ENV0 124
IOPH1/A1/ENV1 125
IOPH2/A2/BADDR0 126
IOPH3/A3/BADDR1 127
IOPH4/A4/TRIS 128
IOPH5/A5/SHBM 131
IOPH6/A6 132
IOPH7/A7 133
IOPI0/D0 138
IOPI1/D1 139
IOPI2/D2 140
IOPI3/D3 141
IOPI4/D4 144
IOPI5/D5 145
IOPI6/D6 146
IOPI7/D7 147
IOPJ0/RD 150
IOPJ1/WR0 151
SELIO# 152
AGND
96
GND1
17
GND2
35
GND3
46
GND4
122
GND5
159
IOPD0/RI1/EXWINT20 26
IOPD1/RI2/EXWINT21 29
IOPD2/EXWINT24/RESET2 30
VCC5 157
VCC6 166
GND6
167
GND7
137
IOPD4 41
IOPD5 42
IOPD6 54
IOPD7 55
IOPJ2/BST0
62
IOPJ3/BST1
63
IOPJ4/BST2
69
IOPJ5/PFS
70
IOPJ6/PLI
75
IOPJ7/BRKL_RSTO
76 IOPK0/A8 143
IOPK1/A9 142
IOPK2/A10 135
IOPK3/A11 134
IOPK4/A12 130
IOPK5/A13_BE0 129
IOPK6/A14_BE1 121
IOPK7/A15_CBRD 120
IOPL0/A16 113
IOPL1/A17 112
IOPL2/A18 104
IOPL3/A19 103
IOPM0/D8
148
IOPM1/D9
149
IOPM2/D10
155
IOPM3/D11
156
IOPM4/D12
3
IOPM5/D13
4
IOPM6/D14
27
IOPM7/D15
28
IOPL4/WR1# 48
SEL0#
173
SEL1#
174
CLK
47
NC2
12
NC3
20
NC4
21
NC5
85
NC6
86
NC7
91
NC8
92
NC9
97
NC10
98
NC1
11
C326
0.1U_0402_10V6K 1
2
R331
10K_0402_5%
1 2
RP24
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C1072
1000P_0402_50V7K
1
2
R340
@20M_0603_5%
1 2
R1175 @0_0402_5%
C911
0.1U_0402_10V6K
1
2
R986 0_0402_5%
12
L33 FBM-L11-160808-800LMT_0603
12
R1251
@100K_0402_5%
1 2
R926 0_0603_5%
1 2
C320
0.1U_0402_10V6K
1
2
R341
0_0402_5%
1 2
R332
47K_0402_5%
1 2
R1299 @10K_0402_5%
1 2
R335 1K_0402_5%
1 2
R336 1K_0402_5%
1 2
R1169 10K_0402_5%
1 2
R342 20K_0402_5%
1 2
C1071
4.7U_0805_6.3V6K
1
2
C327
1000P_0402_50V7K
1
2
C321
0.01U_0402_16V7K
1
2
R1170 10K_0402_5%
1 2
D36 RB751V_SOD323
2 1
C319
0.1U_0402_10V6K
1
2
C325 0.01U_0402_16V7K
1 2
L32
FBM-L11-160808-800LMT_0603
12
C322
0.1U_0402_10V6K
1
2
R1171 10K_0402_5%
1 2
R1162 10K_0402_5%
1 2
R931
0_0402_5%
12
R1253 @1K_0402_5%
1 2
R959 10K_0402_5%
1 2
R984 @0_0402_5%
1 2
RP23
10K_0804_8P4R_5%
SD309100200
1 8
2 7
3 6
4 5
R1172 10K_0402_5%
1 2
C329
@15P_0402_50V8J
1
2
C328
0.22U_0603_10V7K
1
2
C1070 0.1U_0402_10V6K
1 2
C323
4.7U_0805_6.3V6K
1
2
JP52
@96212-1011S
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
Y3
32.768KHZ_12.5P_1TJS125DJ2A073
OUT 4
IN 1
NC
3
NC
2
R338 10K_0402_5%
1 2
R344 47K_0402_5%
1 2
R960 10K_0402_5%
1 2
R927 @0_0603_5%
1 2
R334 @1K_0402_5%
1 2
R1163 10K_0402_5%
1 2
C331
12P_0402_50V8J
1
2
R1123 @10K_0402_5%
1 2
C324
0.1U_0402_10V6K
1
2
KBA5
FWE#
KBA12
KBA[0..19]
ADB2
FWE#
KBA3
KBA8
KBA0
KBA17
ADB5
KBA1
ADB0
KBA11
KBA6 KBA13
ADB1
KBA15
ADB6
KBA10
ADB7
KBA4
FSEL#
KBA7
ADB[0..7]
ADB3
KBA16
KBA2
KBA9
KBA14
KBA18
ADB4
FRD#
ADB5
AA
ADB1
ADB4
ADB2
ADB3
KBA2
ADB0
ADB7
SELIO#
ADB6
LARST#
KBA17
ADB7
KBA2
KBA18
ADB4
ADB0
KBA12
KBA10
RESET#
KBA7
ADB6
KBA16
FSEL#
ADB3
KBA15
FWE#
KBA14
ADB1
KBA19
KBA3
KBA4
KBA9
KBA6
ADB5
KBA5
KBA0
KBA13
KBA8
ADB2
KBA1
KBA11
FRD#
AA
EC_SMC_1<44,49>
ADB[0..7]<44>
EC_FLASH# <27>
FWR# <44>
EC_SMD_1<44,49>
KBA[0..19]<44>
MDM_PME#<33,34,41,44>
ONBD_LAN_PME#<33,34,41,44> PME_EC# <33,34,41,44>
WLAN_PME#<33,34,41,44>
FSEL#<44> FRD#<44>
SELIO#<44>
SUSP# <44,47>
1394_PME#<33,34,41,44>
+3VALW
+3VALW +3VALW +3VALW
+5VALW
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
+5VALW +5VALW
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
BIOS & EC I/O Port
45 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
OUTPUT
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
U18ASN74LVC32APWLE_TSSOP14
A
1
B
2O3
P14
G
7
R360
@100K_0402_5%
1 2
C333
@0.1U_0402_16V7K
1 2
R12
@100K_0402_5%
12
R356
4.7K_0402_5%
12
R354
10K_0402_5%
12
U20
@SST39VF080-70_TSOP40
A0
21
A1
20
A2
19
A3
18
A4
17
A5
16
A6
15
A7
14
A8
8
A9
7
A10
36
A11
6
A12
5
A13
4
A14
3
A15
2
A16
1
A18
13
CE#
22
OE#
24
D0 25
D1 26
D2 27
D3 28
D4 32
D5 33
D6 34
D7 35
GND1 39
A17
40
WE#
9
VCC1 30
VCC0 31
GND0 23
A19
37
NC0 29
NC1 38
NC 11
RP# 10
READY/BUSY# 12
U19
512K8-90_PLCC32
A18
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
13
DQ1
14
DQ2
15
DQ3 17
DQ4 18
DQ5 19
DQ6 20
DQ7 21
CE# 22
A10 23
OE# 24
A11 25
A9 26
A8 27
A13 28
A14 29
WE# 31
VDD 32
VSS
16
A17 30
U18C
SN74LVC32APWLE_TSSOP14
A9
B10
O
8
P14
G
7
G
D
S
Q29 2N7002 1N_SOT23
2
1 3
R359
100K_0402_5%
12
C338
0.1U_0402_10V6K
1
2
R357
100K_0402_5%
12
R358
100K_0402_5%
12
C334
@1U_0603_10V6K
1 2
U21
AT24C164-10SC_SO8
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WC
7
R352
@20K_0402_5%
1 2
U17
@SN74HCT273PW_TSSOP20
Q0 2
D1
4Q1 5
D2
7Q2 6
D3
8Q3 9
D4
13 Q4 12
D5
14 Q5 15
D6
17 Q6 16
D7
18 Q7 19
D0
3
CP
11
VCC 20
MR
1
GND
10
C336
0.1U_0402_10V6K
1
2
C337
0.1U_0402_10V6K
1
2
TV_COMPS
TV_LUMAL
TV_CRMA TV_COMPSL
TV_CRMAL
TV_LUMA
SUSP
NB_PWRGD <8,10>
SB_PWRGD <27>
TV_COMPS<11,17> TV_CRMA<11,17>
TV_LUMA<11,17>
VCORE_PWRGD<54>
SUSP<47,53>
VTT_PWRGD <24,27>
+3VALW
+2.5VS
+3VALW +3VALW
+3VALW
+3VS
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
POWER GOOD & P/S2 CKT
46 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
TV_OUT CONNECTOR
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R188
75_0402_5%
12
D20
@DAN217_SOT23
2
31
U32E
SN74LVC14APWLE_TSSOP14
O10
I
11
P14
G
7
R603
330K_0603_5%
1 2
C111
@68P_0402_50V8K
1
2
L7 CHB1608B121_0603
1 2
R1106
330K_0402_5%
1 2
R610
47K_0402_5%
12
R1107
1K_0402_5%
12
R608
1K_0402_5%
12
U18D
SN74LVC32APWLE_TSSOP14
A
12
B
13 O11
P14
G
7
L8 CHB1608B121_0603
1 2
R190
75_0402_5%
12
U32D
SN74LVC14APWLE_TSSOP14
O8
I
9
P14
G
7
G
D
S
Q110
@2N7002_SOT23
2
13
R189
75_0402_5%
12
C110
@68P_0402_50V8K
1
2
G
D
S
Q52
2N7002_SOT23
2
13
R605
1M_0402_5%
12
U32B
SN74LVC14APWLE_TSSOP14
O4
I
3
P14
G
7
U32C
SN74LVC14APWLE_TSSOP14
O6
I
5
P14
G
7
C115
@68P_0402_50V8K
1
2
C606
0.1U_0402_16V7K
1
2
R601
10K_0402_5%
12
R606
10K_0402_5%
12
D19
@DAN217_SOT23
2
31
R604 47_0603_5%
1 2
L4 CHB1608B121_0603
1 2
C607
0.47U_0603_10V7K
1
2
G
D
S
Q111
@2N7002_SOT23
2
13
C114
@68P_0402_50V8K
1
2
C112
@68P_0402_50V8K
1
2
C113
@68P_0402_50V8K 1
2
JP7
SUYIN_35138S-07T1-DF
1
2
3
4
5
6
7
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SYSON
SUSP SUSP
SUSP
SUSP
SYSON#
SUSPSUSP
SUSP
SYSON#
SYSON# SUSP
SUSP SUSP
SUSP
SYSON#
SUSP SYSON# SYSON#SYSON#
SUSP#<44,45>
SUSP<46,53>
SYSON<44>
SYSON#<35>
+2.5VALW
+3VALW
+1.8VS
+2.5V
+5VALW
+2.5VS
+5VS
+12VALW
+5VALW
+3VS
+2.5VS
+5VALW
+3VS +5VS+1.25VS
+12VALW
+2.5VALW
+3V+3VALW
+5V+5VALW
+12VALW
+12VALW +12VALW
+12VALW
+1.5VSP +1.5VS+12VALW
+1.2VS_VGA +2.5V
+5V+1.5VS +3V
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
DC/DC Circuits
47 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
+3VALW to +3VS Transfer
+2.5VALW to +2.5V Transfer
Discharge circuit
+5VALW to +5VS Transfer
+2.5V to +2.5VS Transfer
+3VALW to +3V Transfer
+5VALW to +5V Transfer
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(6A,240mils ,Via NO.= 12)
+1.5VSP to +1.5VS Transfer
Place close to PJP4
L
(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)
G
D
S
Q39
2N7002 1N_SOT23
2
13
C350
10U_0805_6.3V6M
1
2
U23
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C959
10U_0805_6.3V6M
1
2
R362
100K_0402_5%
12
R1101
68K_0402_5%
12
C346
10U_0805_6.3V6M
1
2
G
D
S
Q43
2N7002 1N_SOT23
2
13
R1102
470_0402_5%
12
R1094
470_0402_5%
12
G
D
S
Q41
2N7002 1N_SOT23
2
13
G
D
S
Q38
2N7002 1N_SOT23
2
13
G
D
S
Q40
2N7002 1N_SOT23
2
13
R369
10K_0402_5%
12
R376
470_0402_5%
12
C347
0.1U_0402_10V6K
1
2
C355
10U_0805_6.3V6M
1
2
G
D
S
Q32
2N7002 1N_SOT23
2
13
U56
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C627
0.1U_0402_10V6K
1
2
G
D
S
Q102
2N7002 1N_SOT23
2
13
U24
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C357
10U_0805_6.3V6M
1
2
G
D
S
Q109
2N7002 1N_SOT23
2
13
C342
10U_0805_6.3V6M
1
2
R373
10K_0402_5%
12
R363
95.3K_0603_1%
12
C344
10U_0805_6.3V6M
1
2
G
D
S
Q42
2N7002 1N_SOT23
2
13
G
D
S
Q73
2N7002 1N_SOT23
2
13
R902
95.3K_0603_1%
12
G
D
S
Q74
2N7002 1N_SOT23
2
13
C844
0.1U_0402_10V6K
1
2
C358
0.1U_0402_10V6K
1
2
U25
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
U22
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C352
0.1U_0402_10V6K
1
2
R372
470_0402_5%
12
R1095
470_0402_5%
12
C625
0.1U_0402_10V6K
1
2
C359
10U_0805_6.3V6M
1
2
C356
0.1U_0402_10V6K
1
2
R904
47K_0402_5%
12
C354
0.1U_0402_10V6K
1
2
C360
0.1U_0402_10V6K
1
2
R375
470_0402_5%
12
C341
10U_0805_6.3V6M
1
2
U26
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C353
10U_0805_6.3V6M
1
2
C960
0.1U_0402_10V6K
1
2
C343
0.1U_0402_10V6K
1
2
G
D
S
Q115
2N7002 1N_SOT23
2
13
G
D
S
Q36
2N7002 1N_SOT23
2
13
G
D
S
Q103
2N7002 1N_SOT23
2
13
R374
470_0402_5%
12
C351
10U_0805_6.3V6M
1
2
G
D
S
Q76
2N7002 1N_SOT23
2
13
R901
6.8K_0402_5%
12
C626
10U_0805_6.3V6M
1
2
C961
10U_0805_6.3V6M
1
2
U36
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C962
0.1U_0402_10V6K
1
2
R378
470_0402_5%
12
C348
0.1U_0402_10V6K
1
2
G
D
S
Q75
2N7002 1N_SOT23
2
13
R377
470_0402_5%
12
R1116
470_0402_5%
12
G
D
S
Q31
2N7002 1N_SOT23
2
13
C345
0.1U_0402_10V6K
1
2
R903
100K_0402_5%
12
G
D
S
Q108
2N7002 1N_SOT23
2
13
C624
10U_0805_6.3V6M
1
2
G
D
S
Q34
2N7002 1N_SOT23
2
13
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
ADPIN
PACIN
PACIN
N2
CHGRTCP
N3
ACIN <27,46,53>
PACIN <52>
MAINPWON<7,51,53>
DCSRD<52>
EC_PWR_ON#<45>
DC_IN
VL B+
DC_IN DC_IN
VS
VL
VS
ADPIN
+5VALW
RTCVREF
RTCVREF
DC_IN
BATT+
CHGRTC
B+
VS
Title
Size Document Number Rev
Date: Sheet of
0.1
Detector
48 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Detector
Vin Detector
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ACIN
Precharge detector
15.8 16.339 15.274
13.692 14.145 13.166
BATT
detector
11.489 11.852 11.133
9.380 9.658 9.025
18.234 17.841 17.449
17.597 17.210 16.813
3.3V
3.3V
PR6
82.5K_0603_0.1%
12
PC1
100P_0603_50V8J
12
PD8
RB751V_SOD323
12
100K
100K
PQ47
DTC115EKA_SOT23
2
13
PR8
1K_0603_5%
1 2
PC6
1000P_0402_50V7K
12
PQ2
TP0610T_SOT23
13
2
PR12
10K_0603_5%
12
PL1
FBM-L18-453215-900LMA90T_1812
1 2
PC4
1000P_0402_50V7K
12
PD10
@RLZ16B_LL34
2 1
PC23
10U_0805_10V4Z
12
PR41
200_0603_5%
12
PD7
1N4148_SOD80
1 2
PU1B
LM393M_SO8
+
5
-
6O7
P8
G
4
PR38
100K_0603_1%
12
PC2
1000P_0402_50V7K
12
PR9
22K_0603_1%
1 2
PR192
47K_0603_5%
1 2
PR11
19.6K_0603_0.1%
12
PC7
0.1U_0603_16V7K
12
1
2
G
G
PCN1
SINGA_2DC-G213-B04
1
2
4
3
PR1
10K_0603_5%
1 2
PR43
200_0603_5%
1 2
PU3 G920AT24U_SOT89
IN 2
GND
1
OUT
3
PC9
0.047U_0603_16V7K
12
PC10
1000P_0603_16V7K
12
PR14
10K_0603_5%
12
PR28
1.5K_1206_5%
1 2
PD6
1N4148_SOD80
12
PR2
1M_0402_1%
12
PC17
0.22U_1206_25V7K
12
PC8
1000P_0603_16V7K
12
PC5
0.01U_0603_50V7K
12
PR5
499K_0603_1%
12
PR39
22K_0603_5%
1 2
PU1A
LM393M_SO8
+3
-2
O
1
P8
G
4
PR191
499K_0603_1%
12
PR4
1M_0603_0.5%
1 2
PR230
200_0603_5%
1 2
PD1
RB751V_SOD323
12
PR27
1.5K_1206_5%
1 2
PD22
RB751V_SOD323
12
PZD1
RLZ4.3B_LL34
12
PR29
1.5K_1206_5%
1 2
G
D
S
PQ46
2N7002_SOT23
2
13
PC3
100P_0603_50V8J
12
PR31
47_1206_5%
12
PC18
0.1U_0805_25V7K
12
PR3
432K_0603_1%
12
PR10
10K_0603_5%
12
PC22
1U_0805_50V4Z
12
PR7
10K_0805_5%
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
EC_SMCA
TS_A
EC_SMDA
EC_SMC_1 <46,47>
BATT_TEMPA <46>
EC_SMD_1 <46,47>
MAINPWON <7,50,53>
H_PROCHOT# <5,26>
ADP_I<46,52>
BATT+
VMB
+3VALWP
+5VALWP
VS
VL
VL
VREF
VREF
VS
Title
Size Document Number Rev
Date: Sheet of
0.1
BATTERY CONN / OTP
49 65,
星期三
07, 2004
七月
Compal Electronics, Inc.
PH1 near main Battery CONN :
Recovery at 45 degree C
BAT. thermal protection at 80 degree C
PR25
@100K_0603_1%
12
PR32
47K_0402_1%
1 2
PR40
150K_0402_1%
12
PD4
@BAS40-04_SOT23
1
3
2
PC97
@0.01U_0603_50V4Z
12
PH1
10K_TH11-3H103FT_0603_1%
12
G
D
S
PQ1
@2N7002_SOT23
2
13
PR23
@200K_0603_1%
1 2
PR193
@75K_0603_1%
1 2
PR24
6.49K_0603_1%
1 2
PC14
@1000P_0603_50V7K
12
PC20
1U_0805_16V7K
12
PR22
@11.5K_0603_1%
1 2
PC21
1000P_0402_50V7K
12
PR36
16.9K_0603_1%
1 2
PR26
1K_0603_5%
12
PR30
2.15K_0603_1%
12
PD3
@BAS40-04_SOT23
1
3
2
PR42
150K_0402_1%
12
PR19
100_0603_5%
12
PR17
@1M_0603_1%
1 2
PC15
@1000P_0603_50V7K
12
PU2A
LM393M_SO8
+
3
-
2O1
P8
G
4
PD5
@BAS40-04_SOT23
1
3
2
PR21
@47K_0603_5%
12
PR18
100_0603_5%
12
PC11
1000P_0402_50V7K
12
PL2
C8B BPH 853025_2P
1 2
PC12
0.01U_0603_50V7K
12
PCN2
SUYIN_200275MR009G130ZL
BATT+ 1
TS 3
SMD 4
GND 7
BATT+ 2
SMC 5
GND 6
PC13
0.1U_0603_50V4Z
12
PU2B
LM393M_SO8
+
5
-
6O7
P8
G
4
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
CHGSS
N18
LXCHRG
DCSRD
ACOFF#
PACIN
ACOFF#
CHGSS
ACOFF <46>
IREF<46>
BATT_OVP<46>
FSTCHG<46>
ADP_I<46,51>
PACIN<50>
DCSRD
<50>
DC_IN
BATT+
P3 B+ B++
VMB
+3VALWP
VL
VREF
DC_IN
P2
Title
Size Document Number Rev
Date: Sheet of
0.1
CHARGER
50 65,
星期三
07, 2004
七月
Compal Electronics, Inc.
Iadp=0~6.5A
CC=0.4~3A
CV=16.8V(8 CELLS LI-ION)
IREF=0.44~3.3V
IREF=1.096*Icharge
4.2V
OVP voltage : LI
(BAT_OVP=0.1111 *VMB)
4S2P : 17.4V--> BATT_OVP= 1.94V
Throttling -1 level: ADP_I=1.4V
Throttling +1 level: ADP_I=1.14V
PC36
1500P_0603_50V7K
1 2
PC29
0.1U_0603_25V7K
12
PC45
0.01U_0603_50V7K
12
PR56
10K_0603_1%
12
PC38
1500P_0603_50V7K
1 2
PR50
0_0603_5%
12
100K
100K
PQ11
DTC115EKA_SOT23
2
13
PD13
1SS355_SOD323
1 2
PR48
47K_0603_5%
1 2
PQ61 AO4407_SO8
3 6
5
7
8
2
4
1
PC37
0.1U_0805_25V7K
1 2
PR44
0.01_2512_1%(1W)
12
10K
47K
PQ48
DTA144YKA_SC70
2
1 3
PC98
0.1U_0603_25V7K
12
PC42
0.1U_0603_16V7K
12
PD30
1SS355_SOD323
1 2
PR52
47K_0603_1%
12
PC24
4.7U_1206_25V6K
12
100K
100K
PQ8
DTC115EKA_SOT23
2
13
PC25
4.7U_1206_25V6K
12
PC28
2200P_0402_50V7K
12
PR54
28.7K_0603_1%
12
G
D
S
PQ50
2N7002_SOT23
2
13
PC35
0.1U_0603_16V7K
12
PD14
SKS30-04AT_TSMA
2 1
PR69
340K_0603_1%
12
PQ5
AO4407_SO8
3 6
5
7
8
2
4
1
PR61
0.02_2512_1%
1 2
G
D
S
PQ9
2N7002_SOT23
2
13
PR58
3K_0603_5%
1 2
PU5A
LM358A_SO8
+3
-2
0
1
P8
G
4
PR70
499K_0603_1%
12
PR53
150K_0603_1%
12
PR195
47K_0402_5%
12
PC31
0.1U_0805_25V7K
1 2
PC33
4700P_0603_50V7K
1 2
PQ6
AO4407_SO8
36
5
7
82
4
1
PR250
95.3K_0603_0.1%
12
PQ3
AO4407_SO8
36
5
7
82
4
1
PU4
MB3887_SSOP24
-INC2
1
OUTC2
2
+INE2
3
-INE2
4
+INC2 24
GND 23
CS 22
VCC(o) 21
FB2
5
VREF
6
FB1
7
-INE1
8
+INE1
9
OUTC1
10
OUTD
11
-INC1
12
OUT 20
VH 19
VCC 18
RT 17
-INE3 16
FB3 15
CTL 14
+INC1 13
PR47
200K_0603_5%
12
PL3
FBM-L18-453215-900LMA90T_1812
1 2
PR67
143K_0603_0.1%
12
PR63
47K_0603_1%
1 2
PC41
4.7U_1206_25V6K
12
PR64
174K_0603_1%
1 2
PR72
105K_0603_0.5%
12
PC39
4.7U_1206_25V6K
12
PL4
15U_SPC-1204P-150_4A_20%
1 2
PR66
95.3K_0603_0.1%
12
PC34
0.1U_0603_50V4Z
1 2
PR57
1K_0603_1%
1 2
PR51
10K_0603_5%
12
PR60
68K_0603_5%
1 2
100K
100K
PQ49
DTC115EKA_SOT23
2
13
PR62
10K_0603_1%
12
G
D
S
PQ10
2N7002_SOT23
2
13
PR68
47K_0603_5%
12
PC43
0.1U_0603_50V4Z
12
PR59
1K_0603_1%
1 2
PC32
0.1U_0603_16V7K
12
PC40
4.7U_1206_25V6K
12
PQ4
AO4407_SO8
3 6
5
7
8
2
4
1
PC30 2200P_0402_50V7K
1 2
PR247
15K_0603_5%
12
PR240
1K_0603_5%
12
PC26
0.1U_0805_25V7K
12
PR65
100K_0603_1%
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DH3
BST51
DL5
LX3
FLYBACKSNB
DH51DH5
DL3
BST31
LX5
ACIN
DH31
ACIN<27,46,50>
MAINPWON <7,50,51>
VS
VL
B++++
B++++
VL
+12VALWP
+3VALWP
VS
2.5VREF
VL
+5VALWP
B+
Title
Size Document Number Rev
Date: Sheet of
0.1
5V/3.3V/12V
Compal Electronics, Inc.
51 65,
星期三
07, 2004
七月
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
INC.
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
PC71
100P_0402_50V8J
12
PC80
0.47U_0603_16V7K
12
PU6
MAX1902EAI_SSOP28
LX3
26
DL3
24
BST3
25
DH3
27
CSH3
1
CSL3
2
FB3
3
SKIP#
10
GND
8
12OUT 4
VDD 5
BST5 18
DH5 16
LX5 17
DL5 19
PGND 20
CSH5 14
CSL5 13
FB5 12
SEQ 15
REF 9
SYNC 6
RST# 11
SHDN#
23
TIME/ON5
7
RUN/ON3
28
VL 21
V+ 22
PQ14
SI4810DY_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PD19
1SS355_SOD323
1 2
PR89
10K_0402_5%
1 2
PQ13
SI4800DY-T1_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PD15
EC11FS2_SOD106
12
PR75
0_0402_5%
12
PC75
100P_0402_50V8J
12
PR91
3.32K_0603_1%
1 2
PR85
0_0402_5%
1 2
+
PC76
150U_D2_6.3VM
1
2
PR242
620_0402_5%
1 2
PR78
1.54K_0603_1%
12
PR80
0_0402_5%
1 2
PC53
0.1U_0805_25V7K
1 2
PD18
SKS10-04AT_TSMA
2 1
PC47
470P_0805_100V7K
1 2
PC58
4.7U_1206_25V6K
12
PR100
10K_0402_1%
12
PC61
4.7U_1206_25V6K
12
PR95
0_0402_5%
1 2
PC56
2200P_0402_50V7K
12
PR99
47K_0402_5%
12
PC73
680P_0402_50V7K
12
PR239
2.7K_1206_5%
12
PC68
0.47U_0603_16V7K
12
PC52
4.7U_1206_25V6K
12
PR79
0_0402_5%
12
PR73
22_1206_5%
12
PC60
0.1U_0805_25V7K
12
PR97
10K_0402_1%
1 2
+
PC69
150U_D2_6.3VM
1
2
+
PC70
@150U_D2_6.3VM
1
2
PR77
0_0402_5%
1 2
PR101
806K_0603_1%
12
PD16
DAP202U_SOT323
1
2
3
PR94
@0_0402_5%
1 2
PR243
698_0402_1%
1 2
PR81
1.27K_0603_1%
1 2
PC54
4.7U_1206_10V7K
12
PC46
4.7U_1206_25V6K
12
PC65
47P_0402_50V8J
12
PT1
9U_SDT-1204P-9R0-120_4.5A_20%
1 4
3 2
PR241
1.27K_0603_1%
1 2
PR92
@300K_0402_5%
12
PR74
0_0402_5%
1 2
PD17
SKUL30-02AT_SMA
2 1
PR82
2M_0402_1%
12
PC67
0.47U_0603_16V7K
12
PC50
2200P_0402_50V7K
12
PJP23
JUMP_43X118
11
2
2
PQ15
SI4810DY_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PQ12
SI4800DY-T1_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PC57
4.7U_1206_25V6K
12
PC51
4.7U_1206_25V6K
12
PC79
@0.047U_0603_16V7K
12
PL6
10U_SPC-1204P-100_4.5A_20%
12
PR96
10.2K_0603_1%
12
G
D
S
PQ51
2N7002_SOT23
2
13
PC48
0.1U_0805_25V7K
1 2
PC63
47P_0402_50V8J
12
PR83
1M_0402_1%
1 2
PC72
4.7U_1206_10V7K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_MAX1845
VCC_MAX1845
B+
+5VALWP
+1.5VSP +2.5VALWP
+3VALW
+2.5VALW
+VCCVID
+2.5VALWP
+12VALW
+5VALW
+1.25VS
+5VALWP
+VCCVIDP
+12VALWP
+1.25VSP
+3VALWP
+1.8VS
+1.8VSP
+5VALWP
+5VALWP
+VGA_CORE
+1.2VS_VGA
Title
Size Document Number Rev
Date: Sheet of
0.1
DDR POWER 2.5V & 1.5V
Compal Electronics, Inc.
52 65, 07, 2004
星期三 七月
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC81
2200P_0402_50V7K
12
PR114
16.9K_0603_1%
12
PR105
0_0603_5%
1 2
PD21
SKS10-04AT_TSMA
2 1
PR102
0_0603_5%
1 2
PR236
0_0603_5%
12
PR248
@0_0402_5%
1 2
PC99
0.22U_0603_16V7K
12
PJP24
JUMP_43X118
1
122
+
PC93
220U_D2_4VM
1
2
PJP22
JUMP_43X118
1
122
PR115
15.4K_0603_1%
12
PL9
4.7U_SPC-1204P4R7_5.7A_20%
1 2
PR117
100K_0603_1%
12
PU7
MAX1845EEI_QSOP28
OUT2 15
BST2 19
FB2 14
CS2 16
VDD 21
UVP 9
SKIP
6
V+ 4
GND
23
ON1
11
DH1
26
LX1
27
ILIM2 13
DL1
24
VCC 22
PGOOD 7
FB1
2ON2 12
ILIM1 3
OVP
8
REF
10
LX2 17
DL2 20
TON 5
CS1
28
BST1
25
DH2 18
OUT1
1
PC211
@100P_0402_50V8K
12
PC85
2200P_0402_50V7K
12
PC87
4.7U_1206_25V6K
12
PJP4
JUMP_43X118
1
122
PC84
4.7U_1206_25V6K
12
PR249
0_0402_5%
12
PR116
100K_0603_1%
12
PJP6
JUMP_43X39
1
122
PQ17
SI4800DY_SO8
3 6
5
7
8
2
4
1
PC183
4.7U_1206_25V6K
12
PQ18
SI4810DY_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PC89
0.1U_0805_25V7K
12
PD23
SKS10-04AT_TSMA
2 1
PJP10
JUMP_43X118
1
122
PC184
4.7U_1206_25V6K
12
PC94
4.7U_0805_6.3V6K
12
PD20
DAP202U_SOT323
1
2
3
PC83
4.7U_1206_25V6K
12
PR108
0_0603_5%
1 2
PQ19
SI4810DY_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PJP2
JUMP_43X118
1
122
PR103
0_0603_5%
1 2
+
PC95
220U_D2_4VM
1
2
PR268
0_0603_5%
12
PJP21
JUMP_43X118
1
122
PR107
0_0603_5%
1 2
PJP8
JUMP_43X39
1
122
PR267
@0_0603_5%
12
PL8
4.7U_SPC-1204P4R7_5.7A_20%
12
PJP5
JUMP_43X118
1
122
PC96
4.7U_0805_6.3V6K
12
PC92
0.1U_0805_25V7K
12
PC88
4.7U_0805_10V4Z
12
PR106
0_0603_5%
1 2
PC91
1U_0805_16V7K
12
PC90
0.1U_0805_25V7K
12
PJP1
JUMP_43X118
1
122
PJP3
JUMP_43X118
1
122
PR104
20_0603_1%
12
PQ16
SI4800DY_SO8
3 6
5
7
8
2
4
1
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VR_ON<46>
VID_PWRGD<5,56>
SUSP37,42
SUSP
+VCCVIDP
+3VALWP
+3VS +1.8VSP
+3VALW
+1.25VSP
+2.5V
+1.2VS_VGA
+5VALW
Title
Size Document Number Rev
Date: Sheet of
0.1
VGA/1.8V/VCCVID/1.25V
Compal Electronics, Inc.
53 65, 07, 2004
星期三 七月
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M11P: 1.2V--> PR265=1.74K ohm
M9-X: 1.5V-->PR265=3K ohm
PC209
@0.1U_0402_16V7K
1 2
PC203
1U_0603_6.3V6M
12
PD43
1N4148_SOD80
1 2
PU30
APL1085UC-TR_TO252
VOUT 2
ADJUST
1
VIN
3
PC196
4.7U_0805_6.3V6K
1 2
PC172
4.7U_0805_10V4Z
12
PQ58
SI4800DY-T1_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
+
PC188
220U_D2_4VM_R25
1
2
PC200
@0.1U_0402_16V7K
12
PJP20
JUMP_43X118
11
2
2
PC210
0.1U_0402_16V7K
1 2
PU27
MIC5258_SOT23-5
PG
4
OUT 5
EN
3
IN
1
GND 2
PR265
1.74K_0603_1%
1 2
PC201
10U_1206_6.3V7K
12
PC194
1U_0603_6.3V6M
12
PC204
22U_1206_6.3V
12
PR258
100_0402_1%
12
PR260
1K_0402_1%
12
PL16
2.2UH_SPC-1205P-2R2B_13A_30%
1 2
PU31
APW7057KC-TR_SOP8
BOOT 1
LGATE 4
UGATE 2
FB
6
PHASE 8
GND
3
OCSET
7
VCC 5
PJP19
JUMP_43X118
1
122
PR264
0_0402_5%
1 2
G
D
S
PQ57
2N7002_SOT23
2
13
PC205
22U_1206_6.3V
12
PC208
0.1U_0402_16V7K
12
PR266
3.4K_0603_1%
1 2
PR123
0_0603_5%
12
PC197
0.1U_0402_16V7K
12
PC193
10U_1206_6.3V7K
12
PC189
10U_1206_25VAK
12
PU29
APL5331KAC-TR_SO8
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
PQ60
SI4810DY_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PC195
10U_1206_6.3V7K
12
G
D
S
PQ59
2N7002_SOT23
2
13
PR259
0_0402_5%
1 2
PR257
1K_0402_1%
12
PR217
0_0603_5%
12
PC206
22U_1206_6.3V
12
+
PC199
@150U_D2_6.3VM
1
2
PC171
4.7U_0805_10V4Z
12
+
PC187
@220U_D2_4VM
1
2
PR261
44.2_0402_1%
12
PR263
8.45K_0603_1%
1 2
PR218
100K_0402_1%
1 2
PR262
10_0603_1%
1 2
PJP18
JUMP_43X118
1
122
PC198
100P_0402_50V8J
1 2
PC207
470P_0402_50V7K
12
CM-
CM+
BSTM
CORE_REF
BSTM
OAIN-
OAIN+
OAIN+
FB
OAIN-
FB
OAIN+
OAIN+
OAIN+
OAIN-
FB
SKIP#
CORE_REF
VID5
<5>
VID4
<5>
VID3
<5>
VID1
<5>
VID2
<5>
VCCSENSE<5>
CORE_REF<57>
VID_PWRGD<5,55>
DLM<57>
CM+
<57> CM-
<57>
DLS<57>
VSSSENSE<5>
VCORE_PWRGD<48>
CPUCLK_STP# <5,11,26>
CORE_REF <57>
H_BOOTSELECT<4>
CS- <4,5,6,7,8,26,57>
CS+ <57>
DPRSLPVR
<26>
SKIP#
VCCSENSE <5>
VID0
<5>
+CPU_B+
B+
+CPU_B+
+VCC_CORE
+5VS_CORE
+VCCVID +5VS_CORE
+5VS +5VS_CORE
+5VS_CORE
+VCC_CORE
+5VS_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
0.1
CPU_CORE(1)
A3
54 65,
星期三
07, 2004
七月
H_BOOTSELECT=1
H_BOOTSELECT=0
PRESCOTT
NORTHWOOD
1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line.
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.
For Prescott: Pop PR167
For Northwood: Pop PR269
PQ29
SI7886DP_SO8
3
2
4
1
5
PR170
0_0402_5%
12
PR152
@1.74K_0402_1%
1 2
G
D
S
PQ33
2N7002_SOT23
2
13
PR154
100K_0402_1%
1 2
PQ27
SI7392DP_SO8
3 5
2
4
1
PR2220_0402_5%
1 2
PC120
0.1U_0805_25V7K
12
PR109
@100K_0402_1%
1 2
PC116
10U_1206_25VAK
12
PR246
@0_0402_5%
1 2
PR135
100K_0402_1%
12
PC114
0.22U_0603_16V7K
12
PR144
61.9K_0402_1%
12
PR2250_0402_5%
1 2
PC129
@4700P_0402_25V7K
12
PC118
10U_1206_25VAK
12
PR165
100K_0402_1%
1 2
PR173
1K_0603_1%
1 2
PR245
@0_0402_5%
1 2
PQ31
SI7886DP_SO8
3
2
4
1
5
PC136
470P_0402_50V7K
12
PR111
150_0402_1%
1 2
+
PC212
100U_25V_M
1
2
PC115 0.22U_0603_16V7K
1 2
PR168
9.31K_0603_1%
1 2
PR161
150K_0402_1%
1 2
PC133
10U_1206_25VAK
12
G
D
S
PQ45
2N7002_SOT23
2
13
PC131
10U_1206_25VAK
12
PD27
SKS30-04AT_TSMA
2 1
PC126
1000P_0402_50V7K
12
PC117
10U_1206_25VAK
12
PD29
SKS30-04AT_TSMA
2 1
PL12
0.5U_CXZM1350-R50_35A_20%
12
PQ28
SI7886DP_SO8
3
2
4
1
5
PU9
MAX1546
TIME
1
FB
15
VCC
10
ILIM
9
REF
8
SHDN#
6
TON
2
CCV
12
SKIP 18
DHS 33
BSTM 26
DLM 29
SUS 3
LXS 34
LXM 27
BSTS 35
D4
20
CMP 37
D3
21
PGND 31
OAIN+
17
CSP 40
OAIN-
16
CMN 38
OFS
7VROK
25
GND
11
S1 5
CSN 39
D5
19
V+ 36
DLS 32
DHM 28
VDD 30
CCI
14
D2
22
D0
24
D1
23
S0 4
GNDS
13
PC138
100P_0603_50V8J
12
PC139
2200P_0402_50V7K
12
PR2240_0402_5%
1 2
PR156
0_0402_5%
1 2
PR2210_0402_5%
1 2
PR143
0_0603_5%
1 2
PR167
100K_0402_1%
12
PQ30
SI7392DP_SO8
3 5
2
4
1
PR155
0_0603_5%
1 2
PD28
DAP202U_SOT323
1
2
3
PC125
2.2U_0805_16V4Z
12
PR180
2.87K_0603_1%
12
PC181
470P_0402_50V7K
12
PR153
499_0402_1%
12
PR110
22.6_0402_1%
12
PR132
0_0402_5%
1 2
PC141
0.47U_0603_16V7K
1 2
PC135
0.1U_0805_25V7K
12
PC123
1U_0603_16V6K
12
PR159
100K_0402_1%
1 2
PC180
100P_0402_50V8J
12
PR133
10K_0402_5%
1 2
PC182
1000P_0402_50V7K
12
PR136
100K_0402_1%
12
G
D
S
PQ44
2N7002_SOT23
2
13
+
PC202
100U_25V_M
1
2
PR157
0_0402_5%
1 2
PQ26
MMBT3904_SOT23
C1
E
3
B
2
PC140
100P_0603_50V8J
12
G
D
S
PQ43
2N7002_SOT23
2
1 3
PR162
1K_0603_1%
12
PC132
10U_1206_25VAK
12
PR139
0_0402_5%
1 2
PC119
2200P_0402_50V7K
12
PR163
0_0402_5%
1 2
G
D
S
PQ20
2N7002_SOT23
2
13
PD26
SKS30-04AT_TSMA
2 1
PR160
20K_0402_1%
1 2
PR158
2.87K_0603_1%
12
PC122
270P_0402_50V7K
12
PR140
100K_0402_1%
12
PC124
0.47U_0603_16V7K
1 2
+
PC130
100U_25V_M
1
2
PC128
0.22U_0603_16V7K
12
PR148
0_0402_5%
1 2
PR2230_0402_5%
1 2
PR138
@0_0402_5%
1 2
PR244
0_0402_5%
1 2
G
D
S
PQ40
2N7002_SOT23
2
13
PR145
0.001_2512_5%
1 2
PR137
30.1K_0603_1%
1 2
PR15
0_0402_5%
1 2
PR141
0_0402_5%
1 2
PL11
FBM-L18-453215-900LMA90T_1812
12
PL13
0.5U_CXZM1350-R50_35A_20%
1 2
PR2200_0402_5%
1 2
PJP14
JUMP_43X79
1
122
PR227
0_0402_5%
1 2
PC142
@100P_0603_50V8G
12
PR149
0_0402_5%
12
PR147
10_0603_1%
1 2
PQ32
SI7886DP_SO8
3
2
4
1
5
PR171
1K_0603_1%
1 2
PR269
@100K_0402_1%
12
PR146
1K_0603_1%
12
PC134
2200P_0402_50V7K
12
PR164
499_0402_1%
12
PR166
0_0402_5%
1 2
SKIP#
CS- <4,5,6,7,8,26,56>
CS+ <56>
CORE_REF
6
>
CM- <56>
CM+ <56>
DLM<56>
SKIP# <56>
DLS<56>
+VCC_CORE
+CPU_B+
+CPU_B+
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5VS_CORE
+5VS_CORE
Title
Size Document Number Rev
Date: Sheet of
0.1
+CPU_CORE(2)
Compal Electronics, Inc.
55 65,
星期三
07, 2004
七月
PQ38
SI7886DP_SO8
3
2
4
1
5
PR178
0_0603_5%
1 2
PC155
1000P_0603_16V7K
12
PC167
2200P_0402_50V7K
1 2
PQ37
SI7392DP_SO8
3 5
2
4
1
PL14
0.5U_CXZM1350-R50_35A_20%
1 2
PC160
10U_1206_25VAK
12
PD35
@1SS355_SOD323
1 2
PD41
@1SS355_SOD323
1 2
PC166
0.47U_0603_16V7K
1 2
PC147
10U_1206_25VAK
12
PD42
SKS30-04AT_TSMA
2 1
PL15
0.5U_CXZM1350-R50_35A_20%
12
PQ39
SI7886DP_SO8
3
2
4
1
5
PC159
10U_1206_25VAK
12
PR176
10_0603_1%
12
PR204
1K_0603_1%
12
PR188
0_0603_5%
1 2
PC170
100P_0603_50V8J
12
PR174
0_0603_5%
1 2
PQ36
SI7886DP_SO8
3
2
4
1
5
PC169
1000P_0603_16V7K
12
PC168
1000P_0603_16V7K
12
PU10
MAX1980
VDD
11
LIMIT
18
VCC
12
POL
7
TON
3
COMP
6
DD/
13
ILIM
19
GND
8
V+ 17
BST 16
DH 14
LX 15
DL 10
PGND 9
CS+ 5
CS- 4
CM+ 1
CM- 2
TRIG 20
PC149
2.2U_0805_16V4Z
12
PC150
0.22U_0603_16V7K
12
PR184
200K_0603_1%
12
PC165
0.22U_0603_16V7K
12
PC161
10U_1206_25VAK
12
PR196
0_0603_5%
1 2
PR199
0_0603_5%
1 2
PR201
0_0603_5%
1 2
PR207
200K_0603_1%
12
PC146
10U_1206_25VAK
12
PC151
0.22U_0603_16V7K
12
PR181
1K_0603_1%
12
PR200
0_0603_5%
1 2
PR198
10_0603_1%
12
PU11
MAX1980
VDD
11
LIMIT
18
VCC
12
POL
7
TON
3
COMP
6
DD/
13
ILIM
19
GND
8
V+ 17
BST 16
DH 14
LX 15
DL 10
PGND 9
CS+ 5
CS- 4
CM+ 1
CM- 2
TRIG 20
PC164
0.22U_0603_16V7K
12
PC158
2.2U_0805_16V4Z
12
PC154
1000P_0603_16V7K
12
PD33
1SS355_SOD323
12
PC144
0.1U_0805_25V7K
12
PD39
1SS355_SOD323
12
PQ34
SI7392DP_SO8
3 5
2
4
1
PC156
100P_0603_50V8J
12
PD36
SKS30-04AT_TSMA
2 1
PC145
10U_1206_25VAK
12
PC153
2200P_0402_50V7K
1 2
PR177
0_0603_5%
1 2
PC163
0.1U_0805_25V7K
12
PC148
2200P_0402_50V7K
12
PC162
2200P_0402_50V7K
12
PR183
20K_0402_1%
1 2
PR206
20K_0402_1%
1 2
PQ35
SI7886DP_SO8
3
2
4
1
5
PR189
49.9K_0402_1%
12
PC152
0.47U_0603_16V7K
1 2
PR187
0_0603_5%
1 2
PR172
0_0603_5%
1 2
PR210
49.9K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
56 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDate Request
Owner Solution Description Rev.Page#
10.2
0.2
Title
2
3
change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24
54,55,
56,57 03/25/2003 Compal
DPRSLPVR56 03/25/2003
Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
4
Add PJP14
57 Compal Change Netname of +5VS_CORE
5 51 RTC charger Add PR230
wrong layout
pad wrong layout pad
Compal
Compal
CPU VR-Cont. 03/25/2003 Change the netname +5VS_CORE for power
consumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
0.2
0.2
0.2
6re-located both PL10 and PQ21, PQ23
as well as 1.2VS_VGA related power circitry
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
0.2
0.2
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP
to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
0.2
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,
and add PR236 for SUSP# signal
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V
and add a PR236 for SUSP# signal 0.2
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(1)
57 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
----PLEASE SEE NEXT PAGE
BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >
-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)
1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.
-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,
U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)
3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request .
<Page 26,27,36,44> 92.03.18.
-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)
4.Modify the Audio related schematic for Customer request . <Page 37,38> 92.03.20.
-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)
-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
-Add R1048,R1050,R1052 . (Modify CKT&Layout)
2.Modify the Audio related schematic for Customer request . <Page 37> 92.03.17.
-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)
-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)
15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.
-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)
-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)
9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.
-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.
5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.
-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)
-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)
-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net .
(Modify CKT,BOM&Layout)
-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)
-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
12. Del Via Hole on schematic for ME modify . <Page 41> 92.03.24.
-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)
7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request .
<Page 10> 92.03.21.
10. Modify the ON1 related to speed up the power sequence for ATI request . <Page 48,54> 92.03.23.
8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.
-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)
-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) .
(Modify CKT,BOM&Layout)
-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348
from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)
14.Swap the USB20*P3* and USB20*P5* for Customer request . <Page 44> 92.03.24.
-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)
13.Modify the MiniPCI and BlueTooth conn related for Customer request . <Page 43,44> 92.03.24.
-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)
A-TEST SMT BUILT
-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;
Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;
R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;
R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)
-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);
Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)
11. Modify power source CAP.'s value by Brian . <Page 26,49> 92.03.24.
-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)
16.Modify the schematic H_BOOTSELECT related by Power Team . <Page 04> 92.03.25.
-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) .
(Modify CKT,BOM&Layout)
-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% .
(Modify CKT&BOM)
17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.
-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),
C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)
-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K
to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)
18. Modify power source Resistor and CAP.'s value for power sequence . <Page 49> 92.03.26.
-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)
-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)
19. Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.
-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)
20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.
-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)
21. Change the Resistor's value for ATI recommend . <Page 17 > 92.03.26.
-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)
23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.
-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.
-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)
24. Change the power sequence related part's power source by Brian . <Page 5,37,48> 92.03.27.
-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)
25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.
-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K .
(Modify CKT&BOM)
-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)
26. Modify the SPDIF related schematic for Customer request . <Page 37,41> 92.03.28.
-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)
27. Modify the NEC USB2.0 Controller Chip related schematic for Customer request . <Page 36> 92.03.28.
-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) .
(Modify CKT,BOM&Layout)
-Add R1104(@0_0402_5%) . (Modify CKT&Layout)
-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)
28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.
-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)
29. Modify the related schematic after Brian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.
-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)
30. Modify the related schematic after Layout check <Page 44> 92.03.31.
-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)
31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.
-Update JP40 . (Modify CKT&Layout)
32. Modify the schematic for cost down . <Page 10,12,26,37,> 92.04.04.
-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(2)
58 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
----PLEASE SEE NEXT PAGE
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >
-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EE
Circuit)
1.1394 Connector JP33 Pin define sequence error. <Page 35> 92.04.08. 1.FDD Connector JP38 PCB Footprint error. <Page 40> 92.04.09.
-Check JP38 ACES_85201-2605_26P. (Modify Layout)
2.Power Switch U53 PCB Footprint error. <Page 12> 92.04.09.
-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)
3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.
-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)
4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.
-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES
85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)
2.LED Circuit to Power Button(PRES)modify . <Page 42, Page 46> 92.04.09.
-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)
-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)
3.Add +1.2VS_VGA Discharge Circuit. <Page 49> 92.04.09.
-Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.
-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)
5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep. <Page 31> 92.04.09.
6. MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.
-Update BOM add R326. (Modify EE Circuit)
7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.
-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)
-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)
8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.
9. Add SUSP# pull Down. <Page 46> 92.04.14.
-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)
10. Add CPUCLK_STP# pull High Circuit. <Page 26, 5> 92.04.14.
-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)
-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)
12. SIO Circuit All Power Plan +3V -> +3VS. <Page 39> 92.04.15.
-Add CPUCLK_STP# serial resistor R1125 to Q96.2. (Modify EE Circuit)
11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.
5. Change BOM & Layout LED D57 Footprint . <Page 42> 92.04.15.
-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)
13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.
-Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)
-Update BOM R1046 -> @. (Modify EE Circuit)
6. Change Layout Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.
-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)
7. Change Layout FrontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.
-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)
16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.
15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.
18. Change BOM C191 4.7U -> 2.2U. <Page 17> 92.04.17.
19. Change BOM C202,C931 10U -> 2.2U. <Page 20> 92.04.17.
20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.
21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.
14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.
17. Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.
24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.
23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.
22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.
25. Change BOM C966 22U -> 0.1U. <Page 18> 92.04.18.
26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.
27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.
28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(3)
59 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
----PLEASE SEE NEXT PAGE
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. > BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.
32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.
36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull
High +3V. <Page 41> 92.04.21.
33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.
29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.
30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->
AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.
31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.
34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.
37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.
38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.
39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.
40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.
41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.
42. Change BOM R40 @ -> Del @, R53 -> @. <Page 29> 92.04.23.
43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.
44. Change BOM R230 -> @. <Page 4> 92.04.23.
45. EMI add R1144 for SSOUT. <Page 10> 92.04.24.
46. EMI change D73, D74, D75, D76 part. <Page 38> 92.04.24.
47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.
48. Change BOM R623 10K -> 0. <Page 25> 92.04.28.
49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.
BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >
1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.
2. Change C963 -> @. <Page 41> 92.04.28.
3. Change C974 -> @. <Page 17> 92.04.28.
4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.
5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.
6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.
7. DEL R761,R762 <Page 37> 92.04.28.
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(4)
60 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR
<92.05.07.~92.05.30. >
0.5Add Nets: NMCSA1# and NMCSB1#
18, 19,
22, 23
6Add CS1# for Hynix 8Mx32 VGA DRAM
1Prevent CPUCLK_STP# abnormal state happened 5 Change R1125 from 4.7K to 12K
26 Delete R1126
29 Change R40 from 10K to 1K
7 Change the power of U8 from +3VS to +3VALW
M.B. Ver.
0.5
0.5
Prevent power leakage
Power saving 7 Change the power of Fans from +5VALW to +5VS 0.5
2
3
Reason for change PAGE Modify ListFixed IssueItem
ATI recommendation 8 Add C974 0.54
Add VGA DRAM size detect function517 Add R1149 for 128MB VGA DRAM (un-populate for 64MB) 0.5
7Change M9+X VGA_CORE from +1.5VS to individual power source 21 Delete JOPEN3 0.5
8Delete useless components
25 Delete C96
0.5
25 Change R619.1 and R622.1 net from +5VS to CRT_VCC 0.5Solve power leakage from CRT9
26
10 Prevent DPRSLPVR abnormal state happened Change R1001 from 100K to 47K, R1002 from 0 to 47K 0.5
11 Using rechargeable RTC battery for HP's request Delete D66, D71 and D72; Add D91 (BAS40-04, the same as LA-1761 D30); Change
BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1) 0.526
12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798
from 22u to @10u; Change C801 from 1000p to @1000p 0.5
5 Delete R538
13 Enhance brightness of blue LEDs 0.5Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,
R885, R888, R889, R890, R925 and R1136 to 220
42, 45
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;
Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 to
PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to
PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS
44
14 Solve PWR_ACTIVE LED function fail issue 42 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 0.5
46 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; Change
U15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to
PWR_ACTIVE_PAV#
15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0.5
16 Add discharge components 49 Add R372, R1095, R1102, Q36, Q103 and Q109 0.5
17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0.5
18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0.5
27 Delete Q114, Add R1145
19 Increase MONO_IN voltage level 37 Change R738 from 2.4K to 10K 0.5
20 Decrease Audio AMP Gain 38 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0.5
Update with Item23
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(5)
61 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5
HW PIR <92.05.07.~92.05.30. >
21 RTL8101L no need transistor for 3.3V to 2.5V anymore 34 Delete Q55, R944 and C668
44 Change PCB Footprint from SUYIN_020167MR004SX01ZR_4P to
suyin_020167mr004s511zu_4p for JP18, JP19 and JP20
M.B. Ver.
0.5
0.5Connector Spec. change for ME's request
Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0.5
22
23
Reason for change PAGE Modify ListFixed IssueItem
Change R704 from 5.6K_0402_5% to 5.6K_0402_1%REALTEK recommendation
Delete useless components with BOM 10 Delete R574, R1086 and C952 0.524
24 Delete R210 for UMA only
Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1151 0.525
Add components for EMI 37 Add R1152 0.526
40 Add L65 ~ L78
Solve DOS cold-boot shunt down issue 7 Delete C256 0.527
40 Add L79 ~ L97
Decrease overshoot & undershoot 25 Add R1153 and R1154 0.628
Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0.629
Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0.630
40The pin-definition of FDD conn. was error on rev0.5 M/B31 0.6Correct the pin-definition for JP38
40
32 0.6Change RP119 from 1K to 330; Delete RP121; Add R? and R?VIA recommendation
41
33 0.6Change R880 from 10K to 470Enhance brightness of Docking LEDs
0.634 44To support wake-up function with TP Change TP power from +5VS to +5V
0.635 5Delete useless components Delete R535, R536, R991 and R992
12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17 Delete Q15 and R251
20 Delete R1022
24 Delete R211 and R216
25 Delete C93~C95 and C930
26 Delete Q113, R1124 and D91; Add D93
0.6
27 Delete RP149, RP150, R1145 and Q114
29 Delete R53
37 Delete L45, R1019, Y6, R756, C740 and C741
Add components for EMI38 37 Add L98 and L99 0.6
38 Delete R1142
40 Add C975, C976, CP15~CP17
0.6
36 To improve RTC accuracy 26 Change Y1 from +/-20ppm to +/-10ppm
37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37.C11 to G_RST#
39 Improve Audio quality 38 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3 0.6
39 Delete RP153 and R1132
41 Add R1161
40 42 Add D92
Add components for ID & ME
41 Change R904 from 91K to 47K49Modify +5V power-up timing to lead +3V
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6
HW PIR <92.06.20.~92.07.03. >
Delete C753~C756; Add R1165~R1168 and C97937
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(6)
62 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7
HW PIR <92.07.03.~92.08.08. >
42 Correct Y1 and Y3 pin-out 26 Using pin-1 and pin-2 of these crystals
44 Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95
M.B. Ver.
0.7
0.7
ATI Product Advisory, refer to PA_218IXP0T1
Solve CD-ROM audio noise issue 30 Delete C11 0.7
43
44
Reason for change PAGE Modify ListFixed IssueItem
Solve audio noise issue 37 Change R733.1 from +5VS to +5VAMP_CODEC 0.745
For EMI 38 Add L100, L101, L102 and L103 0.746
For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 0.747
ATI recommendation 27 Change RP12 from 10K to 2.2K 0.748
Delete useless components 46 Delete D69 and D70 0.749
To support wake-up function with TP 46 Delete RP154; Add R1169, R1170, R1171 and R1172 0.750
Solve M10 can't power up issue 49 Delete C844 0.751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
46
46 Add R1175
Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 0.752
Modify brightness of LEDs 42 Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre. 0.753
45
Fast power on for battery only 45 Change R306 from 100K to 470; Delete Q112 0.754
Change R901 from 27K to 6.8K
Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0.755
Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0.756
Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0.757
Reserve for EMI Add JOPEN6, JOPEN7 and JOPEN8 0.758 37
Improve USB2.0 signal quality Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2 0.759 36
Reserve VRAM detect function for ATI recommendation Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS 1.060 17
For EMI Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A)1.061 38
Reduce GHI# "LOW" voltage level Change R527 to 300 ohm 1.062 5
Delete C110~C11548
36 Change L89, R1079 & R1080 to CHB1608U301
7 Add C855, C856, C907 and C908
24 Change L11 & L12 to MBV2012301YZT
26 Change PCI clock damping resisters to 39 ohm
28 Add C873~C881, C980~C983; Change R60~R62 to MBV2012301YZT
37 Delete R769 & R770; Add C984~C992 & L104
Fix "Pop" sound during boot up 1.0Add C97963 37
41 Add L105
For PCBA skew reducing 1.064 42 Change R885, R888, R890, R1136 and R925 to 130
45
25 Add C993 & C994
TI recommendation 1.065 32 Add R1177
Solve audio L/R swap issue 1.066 37 Change R750 & R753 to 27 ohm
44 Delete R327 & C305
67 Improve NIC transmit return loss 34 Change U41 to NS0019 1.0
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
H/W2 EE Dept. PIR SHEET(2)
63 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 LA-1811 REV:1.0 ->1A
HW PIR
67 16 Add R1180
43 Connect MiniPCI clamp (pin127 and pin128) to GND
M.B. Ver.
1A
68
69
Reason for change PAGE Modify ListFixed IssueItem
70
71
72
73
74
75
76
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
77
78
79
80
81
83
84
85
86
87
88
89
90
91
82
1A
reserve Hynix DDR blue screen issue when boot to Win XP
For EMI
Add D94 and R117846For EC NS97551 +3VALW undershoot issue 1A
Delete unnecessary component 46 Delete JP21
47 Delete JP22
1A
46 Add R1179 and C995 1A
54 Delete PJP10 than short it directly
Reserve for when you connect the dock station cable in unit playing an audio
occur a speaker switch
The region is ME height limited zero 1A
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
64 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDate Request
Owner Solution Description Rev.Page#
10.2
0.3
Title
2
3
change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24
54,55,
56,57 03/25/2003 Compal
DPRSLPVR56 03/25/2003
Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
4
Add PJP14
57 Compal Change Netname of +5VS_CORE
5 51 RTC charger Add PR230
wrong layout
pad wrong layout pad
Compal
Compal
CPU VR-Cont. 03/25/2003 Change the netname +5VS_CORE for power
consumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
6re-located both PL10 and PQ21, PQ23
as well as 1.2VS_VGA related power circitry
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP
to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,
and add PR236 for SUSP# signal
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V
and add a PR236 for SUSP# signal
10 54 +1.5VALWP 04/16/2003 Compal
11 04/16/2003 Compal
Compal
Change power time-sequence of 1.5VSP input power
Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode
12 Change power JUMP SIZE to follow new jump role
56 CPU DPRSLPVR
56
5554 PWR JUMP
13 CPU DPRSLPVR56
04/16/2003
04/18/2003 Compal Reserve DPRSLPVR function
and add a PR136 for +5VS_CORE signal
14
15
50 Vin DETECTOR 04/30/2003 Compal Change PR8 form 10k_0603 to 0K_0603
50 Precharge 04/30/2003 Compal Change PR1 from 10k_0603 to 100k_0603
16 04/30/2003 Compal Change PC20 from .22u to 1u ;PR40&PR42 from 100k to
150k; PC80 from 1u to .47u
Battery OTP
to make ACIN to enable to pull low
BOM error
To change feekbeck time
17
51
51 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 to S-812C33AUA-C2N
18 52 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71
19 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 to EC11FS2
04/30/2003 Compal To improve the 3V output ripple Voltage Delet PC7720 53 5V/3.3V/12V
change 1.5V time sequence
Change DPRSLPVR design
For DFX issuse
Change DPRSLPVR design
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.3
0.3
0.3
0.3
0.3
0.3
0.3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
LA-2411
0.1
65 65, 07, 2004
星期三 七月
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDate Request
Owner Solution Description Rev.Page#
21
0.4
Title
Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k55 04/30/2003 Compal1.2VS_VGA BOM errors
22 50
Precharge
detector 05/16/2003 Compal System can't power on by battery
Add
PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)
Change PR5 from 150k to 180k
0.5
23 51 Colok THROTTLING 05/16/2003 Compal To modify the circuit Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form
84.5K to 11.5K
24 56,57 CPU_CORE(1&2) 05/16/2003 Compal Change the freqeuce 300k to 200k delet PR138 ; add PR187(0_0603)&PR188(0_0603)
0.5
0.5
25 52 Charger 05/16/2003 Compal To modify the charger circuit 0.5
Add PR194(1K)
,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)
26 55 1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA add PR124(11.5k_0603) 0.5
27
56 CPU_CORE
07/4/2003 Compal To modify the DCR sense Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)
,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet
PR86,PR88,PR90,PR93 0.6
28
53 3V/5V/12V
07/4/2003 Compal To modify THE CPU Load line form -1.5mV/A to -2.2mV/A Change PR158,PR180 from 2k to 3.4k 0.6
29 56,57 CPU_CORE(1&2) 07/4/2003 Compal To improve the CPU_CORE effecient Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6
30
31
32
0.7
0.7
50 DC_in 08/4/2003 Compal For Gibson issue ,add two schottky diodes add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)
Charger 08/4/2003 Compal
53 3V/5V/12V 08/4/2003 Compal To solve the DCR sense for 5V OCP issue change PR81(1.27k) ,PR78(1.54K),PR79(0_0402)
,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add
PR241(1.24k),PR242(620 ohm),PR243(698 ohm)
33 56 CPU_CORE 08/4/2003 Compal To modify THE CPU Load line form -2.2mV/A to
-1.5mV/A, and senes CPU VCC and VSS Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)
and PR245(0 ohm)
0.7
0.7
52 Add PD30(1SS355_SOD323) ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA
_S
34 52 Charger 08/4/2003 Compal
To modify the Precharge circuit
To improve the charger feedback loop for charger noise issueChange PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7
change 2.5V from fix to adjust Add pr267, PR268 and PC2112004.05.31
35
52
