Compal LA 3061 Schematics. Www.s Manuals.com. R0.3 Schematics

User Manual: Compal LA-3061 - Schematics. Free.

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Compal confidential

2

2

HGT30/31 Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_GM/PM+ICH7-M core logic

3

3

2006-02-15
REV:0.3

4

4

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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PDF created with pdfFactory Pro trial version www.pdffactory.com

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Title

Compal Electronics, Inc.
Cover Sheet

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
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of

47

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ZZZ1

Compal confidential
File Name : LA-3061

PCB

PCI-E x 16 VGA Sub BD
V RAM
128/ 256MB

LVDS Panel
Interface

Mobile Yonah
uFCBGA-479/uFCPGA-478 CPU

Thermal Sensor
AD M1032

1

1

page 4
page 4, 5, 6

Fan Control

H_A#(3..31)

page 4

Clock Generator
I CS 954306

FSB

H_D#(0..63)

533/667MHz

page 15

Nvidia
G7 2/G73M

PCI-E x 16

Intel Calistoga GMCH

page 18

DDR2 -400/533/667

PCBGA 1466
LVDS Panel
Interface
page

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3

page 13,14

Dual Channel

page 7, 8, 9, 10,11,12

16

Mini-PCIE Card

2

CRT & TV OUT
page 17, 36

New Card
Connector
x2
page 37

PCIE x3
USB2.0

Intel ICH7-M

LAN I/F

2

page 28

DMI

AC-LINK

mBGA-652

PCI BUS

3.3V 33 MHz

page 19, 20, 21, 22

USB conn X3
page 31, 37

10/100/1G LAN

CardBus Controller 1394+CARD

RTL8110CL/SBL

E NE CB1410

page 27

READER R5C832
page 24

LPC BUS

page 26

MO DEM
A MOM page

B T Conn

29

page 28

3

3

SubWoofer
page 31

RJ45 CONN
page 28

Slot 0

1394

page 25

page 26

3IN1 READER
page 38

ENE KB910/L

Audio AD1986A
A MOM page 29

page 33

RTC CKT.
page 20

page 32

BIOS

page 32

SPR CONN.
*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1

page 23

PATA CDROM
Connector

page 34

page 23

T ouch Pad
4

page 30

SATA HDD
Connector x2

Int.KBD

Power On/Off CKT.

AMP & Audio Jack

page 37

DC/DC Interface CKT.
page 35

4

page 34

Power Circuit DC/DC

Compal Secret Data

Security Classification
2005/03/10

Issued Date

page 39~45

2006/03/10

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Title

Compal Electronics, Inc.
Block Diagram

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
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of

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A

B+

Power Block Diagram Of The IMVP6

+3VALW

+5VALW

RTCVREF
Regulator
G920AT24

DC IN

MOS
AO4916

B+
BATT+

MOS
TP0610K

SPOK#

(3.3V)

VIN
VIN
Detector

+VSB

+5VS
MOS
SI4800

SUSP

PWM CONT.
MAX8734AEE

Switch

BATT

SI9182DH

OUT2
ON2

PWM
OZ813

ON1

OUT1

U:SI7840 X1
L:AO4410X2

SUSP

+2.5VS

MOS
AO4916

PWM CONT.
MAX8770GTL+

PCI DEVICES

+1.8VS

Regulator
APL5331KAC
SYSON

SUSP

MOS
SI4800

+1.5VS

SUSP#

CARD BUS

R E Q/GNT#

AD20

CB1410
CARD READER & 1394
R5C832
L A N CONTROLLER
RTL8110SBL/CL

2

PWM
ISL6269CRZ

PCI_PIRQG#

AD17

3

PCI_PIRQF#

USB

DEVICE
Express Card

2

Mini Card

I2C / SMB Address
KB910/L (SM1-Pulled-Up 5V)
ADDRESS R/W
A3/A2 H
17/16 H

KB910/L (SM2-Pulled-Up 3.3V)
ADM1032AR

99/98 H

G7xM (I2CC-Pulled-Up 3.3V)
G781-1 (RESERVED)

9B/9A

ICH7M SM Bus
ICS9LPR325AKLFT
DDR II DIMM0
DDR II DIMM1
Express Card
Mini-Express

LDO5

S5 S4/ Battery only

O
O
O
O
O

S5 S4/AC & Battery
don't exist

X

S1

DEVICE

PORT

1

DEVICE
AT24C16AN
SMART BATTERY

LDO3

S0

PCIE LANE
LANE

PCI_PIRQH#

+B

State
S4 : STD
S5 : SOFT OFF

D3/D2 H
A1/A0 H
A3/A2 H
NC
NC

(3.3V)
(3.3V)
(3.3V)
(2.5V)
(2.5V)

0
1
2
3
4
5
6

LEFT SIDE
BLUE TOOTH
RIGHT SIDE
NC
RIGHT SIDE
NC
NC

BOM Structure
MARK
@

FUNCTION
NC FOR ALL

EXP@

PCIE-NEW CARD

BT@

BLUE TOOTH

UMA@

Internal 945GM

VGA@

External G7xM

SUBWOOFER@
HGT30@
CB@

S3 : STR
S5 S4/AC

+5VALW

+1.8V

+3VALW

+5V

O
O
O
O

X
X

O
O
O

ID

MB ID
0
1

0
1
2
3
4
5

P NAME
HGT-30
HGT-31

MB REV#
R01 (EVT)
R02 (DVT)
R03
R04

6
7

O
O

X
X
X
X

X
X
X

BRD_ID
MB_ID

+5VS
+3VS
+2.5VS
+1.8VS
+1.5VS
+VGA_CORE
+1.2VS
+0.9VS
+CPU_CORE
+VCCP

R119(Ra)=100K Ohm

1A
1.5A
1.8A
300mA
1A
mA
70mA
3A

EXPRESS CARD
HDD
ODD
MDC
APA2066
TPA0211
AD1986
USB PORT * 6

480mA
1A
200mA
1A
655mA
680mA
mA
15mA
200mA
mA

+2.5VS

VGA CARD (G7XM)
NB

130mA
(143mA)

SUSP#

O MEANS ON
X MEANS OFF

power
plane

PCI_PIRQA#

0

2.5A
9.8A
(14.7A)

NB
EXPRESS CARD
CLK_GEN
LCDVCC
VGA CARD (G7XM)
SB
R5C832
BIOS ROM
KB910L
CB1410

OUT2

VCCP

PIRQ

AD22

36A

+3VS

MOS
U:SI4810B
L:SI4810B

+1.05VS

Voltage Rails
IDSEL#

CPU
NB

+0.9VS

1

EXTERNAL

+VCCP

MOS
SI4800

SUSP#

MOS
U:SI4810B
L:SI4810B

P.40

CPU

+5VS

+1.8V

Charger
MB39A126

+CPU_CORE

mA
160mA

+3.3VS
Regulator
APL5912-KAC

MOS
AO4407

VID[0..6]

+VDDA

+3VALW
MOS
AO4916

+CPU_CORE

+5VALW

KB910L
SB
RTL8110SBL/CL

+1.8V
+1.8VS

+0.9VREF
+0.9VS

DDR2_DIMM
NB (667Mhz)

1

8A
3.1A

GDDR2
VGA CARD (G7XM)

6A
4.06A

DDR2_DIMM

10mA

GDDR2

1A

DDR2_DIMM

2A

+1.5V

SB

40mA

+1.5VS

NB
SB
MiniCard
EXPRESS CARD
VGA CARD (G7XM)

R115(Rb) Vab

0
8.2K
18K
33K
56K
100K
200K
NC

0V
0.25V
0.50V
0.82V
1.19V
1.65V
2.20V
3.30V

8.9A(13.8A)
3.8A
1A
0.65A
2A

SUBWOOFER

HGT30
PCMCIA/CARD BUS

GIGA@

8110SBL(SCL)Giga LAN

10/100@

8110CL 10/100Mb LAN

Compal Secret Data

Security Classification
2005/03/10

Issued Date

Deciphered Date

2006/03/10

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Notes List
Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

A

PDF created with pdfFactory Pro trial version www.pdffactory.com

Compal Electronics, Inc.

星 期 四 , 二 月 23, 2006

R ev
0 .1
Sheet

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5

4

3

2

1

+ VCCP
H_ D #[0..63] <7>
I TP_TDI

C

2

<7>
<7>
<7>

H_LOCK#
H_RESET#

H_ R S#[0..2]

<7>

H_ RS#0
H_ RS#1
H_ RS#2
H_ T R DY#

H_ T R DY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

B

<45> H_ PROCHOT#

1 R 83

F3
F4
G3
G2

AD4
AD3
AD1
AC4

ITP_DBRESET# C20
H_ D B SY#
E1
H _DPSLP#
B5
H _DPRSTP#
E5
H_ DPW R#
D24
ITP_BPM#4
AC2
ITP_BPM#5
AC1
H_ PROCHOT#D21

<21> ITP_DBRESET#
<7>
H_ D B S Y#
<20>
H_DPSLP#
<20,45> H_DPRSTP#
<7>
H_ D PW R#

+ VCCP

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1

2

68_0402_5%
<20> H_ PW RGOOD
<7,20> H_ C PUSLP#

R 71
R 74

2 @ 1K_0402_5%
2 51_0402_5%

1
1

H_ PW RGOOD D6
H_ C PUSLP#
D7
ITP_TCK
AC5
I TP_TDI
AA6
ITP_TDO
AB3
TEST1
C26
TEST2
D25
ITP_TMS
AB5
ITP_TRST#
AB6
H_ T H ERMDA
A24
H_ T H ERMDC
A25
H_ T HERMTRIP# C7

<7,20> H_ T HERMTRIP#

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

CONTROL

RS0#
RS1#
RS2#
TRDY#

56_0402_5%

2

56_0402_5%

ITP_BPM#5

R 103 1

2

56_0402_5%

ITP_TRST#

R 95

1

2

56_0402_5%

ITP_TCK

R 96

1

2

56_0402_5%

ITP_DBRESET#

DINV0#
DINV1#
DINV2#
DINV3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

MISC

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24

H_ D INV #0
H_ D INV #1
H_ D INV #2
H_ D INV #3

H_ DSTBN#0
H_ DSTBN#1
H_ DSTBN#2
H_ DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

H_ A 20M#
H_ F ERR#
H_ IGNN E#
H_ INI T#
H_ IN TR
H _ NMI

D5
A3

H_STPCLK#
H_ S MI#

LEGACY CPU

THERMAL
THERMDA DIODE
THERMDC
THERMTRIP#

STPCLK#
SMI#

P AD T13
P AD
P AD
P AD
P AD
P AD

T17
T18
T20
T16
T19

D

Thermal Sensor G781F
+3VS
U1 6
H_ T H ERMDA

2

C 311

1

H_ T H ERMDC
2200P_0402_50V7K
EC_SMB_CK2

2

<33> EC_SMB_CK2

E C_SMB_DA2

<33> E C_SMB_DA2

3
8
7

D+

VDD1

D-

ALERT#

SCLK

THERM#

SDATA

1

2
C 310

1
0 . 1 U_0402_16V4Z

6
T HERM#
2
10K_0402_5%

4

1
R 226

+3VS

5

GND

C

G781F_SOP8

Address:100_1100

+5VS

H_ D INV#0
H_ D INV#1
H_ D INV#2
H_ D INV#3

<7>
<7>
<7>
<7>

1

2

C 303
1 0 U_1206_10V4Z

2

H_ D STBN#[0..3] <7>

+3VS

1 C 309

0 . 0 1U_0402_25V4Z

<33>

3

E N_ F AN1

1

OUT
-IN

H_DSTBP#[0..3] <7>

F AN1 _ON

B

D Q19
SI3456BDV-T1-E3_TSOP6

G

+IN

2

R 222
10K_0402_5%

3
S

U1 5 A
LM358A_SO8

J P2

1

A6
A5
C4
B3
C6
B4

2 @ 200_0402_1%

1

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

+VSB

BPM0#
BPM1#
BPM2#
BPM3#

R 85

1

1

+ VCCP

H_ A DS#
H_ B NR#
H_ B PRI#
H_ BR0#
H_ D EFER#
H_ D R D Y#
H_ HI T#
H_ HI TM#
H_ IE RR#
H _LOCK#
H_RESET#

H_ ADS#
H_ B NR#
H_ B PRI#
H_ BR0#
H_ D EFER#
H_ D R D Y#
H_ HIT#
H_ HITM#

HOST CLK

2

1
2
5
6

<7>
<7>
<7>
<7>
<7>
<7>
R 84
<7>
56_0402_5%
<7>

BCLK0
BCLK1

1

R 101 1

R 219
150K_0402_5%

H_ A20M# <20>
H_ F ERR# <20>
H_ IGNNE# <20>
H_ INIT#
<20>
H_ INTR
<20>
H _ NMI
<20>

F AN1

2

R 218
100K_0402_5%

1

C LK_CPU_BCLK A22
C LK_CPU_BCLK# A21

<15> C LK_CPU_BCLK
<15> C LK_CPU_BCLK#

R 97

ITP_TDO

2

ADSTB0#
ADSTB1#

ITP_TMS

D 11
1 N4148_SOD80

H_STPCLK# <20>
H_ S MI#
<20>

1

2

1

2

1
2
3

C305 10U_0805_10V4Z

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_ D#10
H_ D#11
H_ D#12
H_ D#13
H_ D#14
H_ D#15
H_ D#16
H_ D#17
H_ D#18
H_ D#19
H_ D#20
H_ D#21
H_ D#22
H_ D#23
H_ D#24
H_ D#25
H_ D#26
H_ D#27
H_ D#28
H_ D#29
H_ D#30
H_ D#31
H_ D#32
H_ D#33
H_ D#34
H_ D#35
H_ D#36
H_ D#37
H_ D#38
H_ D#39
H_ D#40
H_ D#41
H_ D#42
H_ D#43
H_ D#44
H_ D#45
H_ D#46
H_ D#47
H_ D#48
H_ D#49
H_ D#50
H_ D#51
H_ D#52
H_ D#53
H_ D#54
H_ D#55
H_ D#56
H_ D#57
H_ D#58
H_ D#59
H_ D#60
H_ D#61
H_ D#62
H_ D#63

4

L2
V4

DATA GROUP

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

2

H _ADSTB#0
H _ADSTB#1

ADDR GROUP

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

P

K3
H2
K2
J3
L5

YONAH

G

<7> H_ADSTB#0
<7> H_ADSTB#1

H _REQ#0
H _REQ#1
H _REQ#2
H _REQ#3
H _REQ#4

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

4

<7> H_ REQ#[0..4]

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

2

D

H_ A #3
H_ A #4
H_ A #5
H_ A #6
H_ A #7
H_ A #8
H_ A #9
H_ A#10
H_ A#11
H_ A#12
H_ A#13
H_ A#14
H_ A#15
H_ A#16
H_ A#17
H_ A#18
H_ A#19
H_ A#20
H_ A#21
H_ A#22
H_ A#23
H_ A#24
H_ A#25
H_ A#26
H_ A#27
H_ A#28
H_ A#29
H_ A#30
H_ A#31

This shall place near CPU
R 98 1
56_0402_5%
2

C307
1000P_0402_50V7K

JP 1A

1

H_ A# [3..31]

8

<7>

ACES_85205-0300

<33> F AN_SPEED1

5

+IN
OUT

6

-IN

TYCO_1-1674770-2_Yonah~D
ME@

1

7
C 308
1000P_0402_50V7K

U1 5B
LM358A_SO8

2

+ VCCP

A

1

+ VCCP
R 100
H _DPSLP# 1

@ 56_0402_5%

@ 56_0402_5%
R 99
H _DPRSTP# 1
2

B

2 2

R 73

2

5

OCP#

2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

E

H_ PROCHOT# 3
1 OCP#
Q4
@ PMBT3904_SOT23

Compal Secret Data

Security Classification

@ 56_0402_5%
<21>

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Yonah CPU in mFCPGA479

Size
D oc um ent Num ber
C us tom HGT 3 0 /31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

4

of

47

4

3

+ VCCP

Length match within 25 mils
The trace width 18 mils space
<45> VC CSENSE
7 mils
<45> VSSENSE

1

D

+ CPU_CORE
R 69
1K_0402_1%

1

2

+ CPU_GTLREF

R 93
100_0402_1%
VC CSENSE

2

1

2

2

R 62
2K_0402_1%

C

1

1

2

2

1 0 U_0805_10V4Z

Close to CPU pin
within 500mils.

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

0

0

1

C 132

0 . 0 1U_0402_25V4Z

<45>

H_ PSI#

<45>
<45>
<45>
<45>
<45>
<45>
<45>

C P U_ VID0
C P U_ VID1
C P U_ VID2
C P U_ VID3
C P U_ VID4
C P U_ VID5
C P U_ VID6

H_ P SI#

AE6

C P U_ VID0
C P U_ VID1
C P U_ VID2
C P U_ VID3
C P U_ VID4
C P U_ VID5
C P U_ VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2
AD26

+ CPU_GTLREF

166

0

1

1

<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2

1
2

1

R104
54.9_0402_1%

2

1

R102
27.4_0402_1%

2

1

R72
54.9_0402_1%

2

R70
27.4_0402_1%

+ CPU_CORE

Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

J P1C
D

AF7
AE7
B26

C 122

Close to CPU pin AD26
within 500mils.

+CPU_CORE

+ VCCP
V SSENSE

1

J P1B
VC CSENSE
V SSENSE

+1.5VS

R 94
100_0402_1%

1

2

C PU_BSEL0
C PU_BSEL1
C PU_BSEL2

B22
B23
C21

C OMP0
C OMP1
C OMP2
C OMP3

R26
U26
U1
V1
E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

VCCSENSE
VSSSENSE
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

5

B

D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C

B

TYCO_1-1674770-2_Yonah~D
ME@

TYCO_1-1674770-2_Yonah~D
ME@

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Yonah CPU in mFCPGA479

Size
D oc um ent Num ber
C us tom HGT 3 0 /31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

5

of

47

5

4

3

2

1

+ CPU_CORE

D

D

1
Place these capacitors on L8
(North side,Secondary Layer)

2

1
C 318
1 0 U_0805_6.3V6M

1
C 326
1 0 U_0805_6.3V6M

2

2

1
C 151
1 0 U_0805_6.3V6M

2

1
C171
2 2 U_0805_6.3V6M

1
C 346
1 0 U_0805_6.3V6M

2

2

C184
1 0 U_0805_6.3V6M

+ CPU_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

1

1

C 325
1 0 U_0805_6.3V6M

2

C 186
1 0 U_0805_6.3V6M

2

1

1

C 341
1 0 U_0805_6.3V6M

2

1

C 178
1 0 U_0805_6.3V6M

2

C 316
1 0 U_0805_6.3V6M

1
C 185
1 0 U_0805_6.3V6M

2

2

1
C 166
1 0 U_0805_6.3V6M

2

C342
1 0 U_0805_6.3V6M

2

+ CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

1

1

C 183
1 0 U_0805_6.3V6M

2

C 170
1 0 U_0805_6.3V6M

2

1

1

C 334
1 0 U_0805_6.3V6M

2

C 319
1 0 U_0805_6.3V6M

2

2

1
C172
2 2 U_0805_6.3V6M

1
C 333
1 0 U_0805_6.3V6M

2

2

1
C 181
2 2 U_0805_6.3V6M

C176
1 0 U_0805_6.3V6M

2

C

C

+ CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

1

1

C 150
1 0 U_0805_6.3V6M

2

C 165
1 0 U_0805_6.3V6M

2

1

1

C 345
1 0 U_0805_6.3V6M

2

1

C 173
1 0 U_0805_6.3V6M

2

C 179
1 0 U_0805_6.3V6M

2

1
C 177
1 0 U_0805_6.3V6M

2

1
C 317
1 0 U_0805_6.3V6M

2

2

C 182
2 2 U_0805_6.3V6M

Mid Frequence Decoupling

2

1
+

2

1
+

2

1
+

2

C343
330U_V_2.5VK_R9

+

C320
330U_V_2.5VK_R9

2

1

C339
330U_V_2.5VK_R9

+

C175
330U_V_2.5VK_R9

B

1

C180
330U_V_2.5VK_R9

South Side Secondary

C324
330U_V_2.5VK_R9

+ CPU_CORE

1
+

North Side Secondary

ESR <= 1.5m ohm
Capacitor > 1980uF

2
B

+ VCCP

1
C 109
2 2 0U_D2_4VM

+

1

1
C 190
0 . 1 U_0402_16V4Z

2

2

1
C 136
0 . 1 U_0402_16V4Z

2

1
C 138
0 . 1 U_0402_16V4Z

2

1
C 137
0 . 1 U_0402_16V4Z

2

1
C 189
0 . 1 U_0402_16V4Z

C188
0 . 1 U_0402_16V4Z

2

2

Place these inside
socket cavity on L8
(North side
Secondary)

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
CPU Bypass capacitors

Size
D oc um ent Num ber
C us tom HGT 3 0 /31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

6

of

47

5

4

3

2

1

U1 4

1
2

1

R27
54.9_0402_1%

R26
54.9_0402_1%

HCLKN
HCLKP
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#

VGA@

UMA_ GML@

B9
C13

H _ADSTB#0
H _ADSTB#1

AG1
AG2

C L K_MCH_BCLK#
C L K_MCH_BCLK

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_ DSTBN#0
H_ DSTBN#1
H_ DSTBN#2
H_ DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_ D INV #0
H_ D INV #1
H_ D INV #2
H_ D INV #3

<13>
<13>
<14>
<14>
H_ADSTB#0 <4>
H_ADSTB#1 <4>

<13>
<13>
<14>
<14>

C L K_MCH_BCLK# <15>
C L K_MCH_BCLK <15>
H_ D STBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_ RS#0
H_ RS#1
H_ RS#2

HRS0#
HRS1#
HRS2#

<21>
<21>
<21>
<21>

D MI_RXN0
D MI_RXN1
D MI_RXN2
D MI_RXN3

<21>
<21>
<21>
<21>

D MI_RXP0
D MI_RXP1
D MI_RXP2
D MI_RXP3

H_ D INV#0
H_ D INV#1
H_ D INV#2
H_ D INV#3

D D R _ C S0_DIMMA#
D D R _ C S1_DIMMA#
D D R _ CS2_DIMMB#
D D R _ CS3_DIMMB#

<13>
<13>
<14>
<14>

1
1

AE35
AF39
AG35
AH39

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

D MI _RXN0
D MI _RXN1
D MI _RXN2
D MI _RXN3

AE37
AF41
AG37
AH41

D M I_RXP0
D M I_RXP1
D M I_RXP2
D M I_RXP3

AC37
AE41
AF37
AG41

M_ CLK_DDR0
M_ CLK_DDR1
M_ CLK_DDR2
M_ CLK_DDR3

AY35
AR1
AW7
AW40

M_ CLK_DDR#0
M_ CLK_DDR#1
M_ CLK_DDR#2
M_ CLK_DDR#3

AW35
AT1
AY7
AY40

D D R _ CKE0_DIMMA
D D R _ CKE1_DIMMA
D D R _CKE2_DIMMB
D D R _CKE3_DIMMB

AU20
AT20
BA29
AY29

M_ CLK_DDR#0
M_ CLK_DDR#1
M_ CLK_DDR#2
M_ CLK_DDR#3

D D R _ C S0_DIMMA# AW13
D D R _ C S1_DIMMA# AW12
D D R _ CS2_DIMMB# AY21
D D R _ CS3_DIMMB# AW21

M_ODT0
M_ODT1
M_ODT2
M_ODT3

2 80.6_0402_1%
2

R 28

<4>
<4>
<4>
<4>

D M I_TXN0
D M I_TXN1
D M I_TXN2
D M I_TXN3

M_ CLK_DDR0
M_ CLK_DDR1
M_ CLK_DDR2
M_ CLK_DDR3

D D R _ CKE0_DIMMA
D D R _ CKE1_DIMMA
D D R _CKE2_DIMMB
D D R _CKE3_DIMMB

+1.8V

R 29

B4
E6
D6

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

<13>
<13>
<14>
<14>

H_ REQ#[0..4] <4>

H _REQ#0
H _REQ#1
H _REQ#2
H _REQ#3
H _REQ#4

H_RESET#
H_ A DS#
H_ T R DY#
H_ DPW R#
H_ D R D Y#
H_ D EFER#
H_ HI TM#
H_ HI T#
H _LOCK#
H_ BR0#
H_ B NR#
H_ B PRI#
H_ D B SY#
H_ C PUSLP#

<21>
<21>
<21>
<21>

<13>
<13>
<14>
<14>

D8
G8
B8
F8
A8

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

D MI_TXN0
D MI_TXN1
D MI_TXN2
D MI_TXN3

M _OCDOCMP0
M _OCDOCMP1

AL20
AF10

M_ODT0
M_ODT1
M_ODT2
M_ODT3

BA13
BA12
AY20
AU21

S MR COMPN
S MRCOMPP

AV9
AT9

80.6_0402_1%

AK1
AK41

+ D D R _MCH_REF

R 88
<21> P M_ B MBUSY#
0_0402_5% <13,14> PM_EXTTS#0

H_RESET# <4>
2
H_ ADS# <4> <21,45> D P RSLPVR
H_ T R DY# <4>
H_ DPW R# <4>
H_ D R D Y# <4>
<19,23,28,37> PLT_RST#
H_ DEFER# <4>
H_ HITM# <4>
H_ HIT#
<4>
H_LOCK# <4>
H_ BR0#
<4>
H_ B NR# <4>
H_ B PRI# <4>
H_ D B SY# <4>
H_ CPUSLP# <4,20>

P M_ B MBUSY#
G28
PM_EXTTS#0
F25
PM_EXTTS#1
1
H26
H_
T
HERMTRIP#
G6
<4,20> H_ T HERMTRIP#
IC H _POK
AH33
<21,33> IC H_POK
PLTRST_R#
2
1
AH34
R 55
100_0402_1%

K28

<19> MC H_ IC H_ S YNC#

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3

C FG

U1 4

GML

Description at page15.

U1 4B
<21>
<21>
<21>
<21>

DMITXP0
DMITXP1
DMITXP2
DMITXP3

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

SM_CK0
SM_CK1
SM_CK2
SM_CK3

C LK

PM

1

R20
24.9_0402_1%

HADSTB#0
HADSTB#1

H_ A #3
H_ A #4
H_ A #5
H_ A #6
H_ A #7
H_ A #8
H_ A #9
H_ A#10
H_ A#11
H_ A#12
H_ A#13
H_ A#14
H_ A#15
H_ A#16
H_ A#17
H_ A#18
H_ A#19
H_ A#20
H_ A#21
H_ A#22
H_ A#23
H_ A#24
H_ A#25
H_ A#26
H_ A#27
H_ A#28
H_ A#29
H_ A#30
H_ A#31

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

D_REF_CLKN
D_REF_CLKP
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SM_RCOMPN
SM_RCOMPP

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

SM_VREF0
SM_VREF1
PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#

C ALISTOGA_FCBGA1466~D
UMA_ GM@

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

MC H_CLKSEL0
MC H_CLKSEL1
MC H_CLKSEL2
C F G3
P AD
C F G4
P AD
C F G5
C F G6
P AD
C F G7
C F G8
P AD
C F G9
C F G10
P AD
C F G11
C F G12
C F G13
C F G14
C F G15
C F G16
C F G17
C F G18
C F G19
C F G20

P AD
P AD
P AD

AG33 C L K_MCH_3GPLL
AF33 C L K_MCH_3GPLL#
A27
A26

MC H_CLKREQ# <15>

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

C

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

B

1

R 46
10K_0402_5%

2
1
R18

221_0603_1%

2

1
R22

2

1

R 49
10K_0402_5%

1

1

2

R 21

1

R 45
@ 40.2_0402_1%

100_0402_1%

2

M _OCDOCMP0

2

C16
0.1U_0402_16V4Z

+VCCP

221_0603_1%

2

@
PM_EXTTS#1

+ D D R _MCH_REF

+ VCCP

100_0402_1%

PM_EXTTS#0

100_0402_1%

+ VCCP

1

C L K _MCH_SSCDREFCLK# <15>
C L K _MCH_SSCDREFCLK <15>

MC H_CLKREQ#

+1.8V

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

2

C L K _MCH_DREFCLK# <15>
C L K _MCH_DREFCLK <15>

H_ R S#[0..2] <4>

R 25

R30

C L K_MCH_3GPLL <15>
C L K_MCH_3GPLL# <15>

C L K _MCH_DREFCLK#
C L K _ MCH_DREFCLK

C40 MC H _SSCDREFCLK#
D41 MC H_ SSCDREFCLK
H32

D

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

C ALISTOGA_FCBGA1466~D
UMA_ GM@

A

MC H_CLKSEL0 <15>
MC H_CLKSEL1 <15>
MC H_CLKSEL2 <15>
T9
T3
C F G5
<11>
T10
C F G7
<11>
T7
C F G9
<11>
T5
C F G11
<11>
C F G12
<11>
C F G13
<11>
T2
T8
C F G16
<11>
T1
C F G18
<11>
C F G19
<11>
C F G20
<11>

+3VS

2

1
2

R23
24.9_0402_1%

B

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

PM

J13
+ H _VREF K13
H _XRCOMP E1
H _XSCOMP E2
H_ YR C OMP Y1
H_ YS COMP U1
+ H _SW NG0 E4
+ H _SW NG1 W1

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

+ VCCP

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DMI

C

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

NC

D

2

H_ A#[3..31] <4>

U1 4 A
H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_ D#10
H_ D#11
H_ D#12
H_ D#13
H_ D#14
H_ D#15
H_ D#16
H_ D#17
H_ D#18
H_ D#19
H_ D#20
H_ D#21
H_ D#22
H_ D#23
H_ D#24
H_ D#25
H_ D#26
H_ D#27
H_ D#28
H_ D#29
H_ D#30
H_ D#31
H_ D#32
H_ D#33
H_ D#34
H_ D#35
H_ D#36
H_ D#37
H_ D#38
H_ D#39
H_ D#40
H_ D#41
H_ D#42
H_ D#43
H_ D#44
H_ D#45
H_ D#46
H_ D#47
H_ D#48
H_ D#49
H_ D#50
H_ D#51
H_ D#52
H_ D#53
H_ D#54
H_ D#55
H_ D#56
H_ D#57
H_ D#58
H_ D#59
H_ D#60
H_ D#61
H_ D#62
H_ D#63

RESERVED

H_ D # [0..63]

HOST

<4>

2

1

R 31
@ 40.2_0402_1%
M _OCDOCMP1

2

1
A

+ H _SW NG0

+ H _SW NG1

1

2

0.1U_0402_16V4Z
C11

1
R19

2

2

100_0402_1%

1

0.1U_0402_16V4Z
C19

1
R24

2

2

100_0402_1%

C26

1

0.1U_0402_16V4Z

1
2

R36

200_0402_1%

+ H _VREF

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Calistoga (1/6)

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

7

of

47

5

4

3

2

1

D

D

<13> D D R _A_DQS[0..7]

C

<13> D D R _A_DQS#[0..7]

<13> D D R _ A_MA[0..13]

AU12
AV14
BA20

D D R _A_DM0
D D R _A_DM1
D D R _A_DM2
D D R _A_DM3
D D R _A_DM4
D D R _A_DM5
D D R _A_DM6
D D R _A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

D D R_A_DQS0
D D R_A_DQS1
D D R_A_DQS2
D D R_A_DQS3
D D R_A_DQS4
D D R_A_DQS5
D D R_A_DQS6
D D R_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

D D R_A_DQS#0
D D R_A_DQS#1
D D R_A_DQS#2
D D R_A_DQS#3
D D R_A_DQS#4
D D R_A_DQS#5
D D R_A_DQS#6
D D R_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

D D R _A_MA0
D D R _A_MA1
D D R _A_MA2
D D R _A_MA3
D D R _A_MA4
D D R _A_MA5
D D R _A_MA6
D D R _A_MA7
D D R _A_MA8
D D R _A_MA9
D D R _A_MA10
D D R _A_MA11
D D R _A_MA12
D D R _A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

D D R _A_CAS#
D D R _A_RAS#
D D R_A_W E#
S A_ R C V ENIN#
S A_ RCVENOUT#

AY13
AW14
AY14
AK23
AK24

U14E

SA_BS0
SA_BS1
SA_BS2

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR SYS MEMORY A

<13> D D R _ A_DM[0..7]

D DR_A_BS#0
D DR_A_BS#1
D DR_A_BS#2

B

<13> D D R _A_CAS#
<13> D D R _A_RAS#
<13> D D R_A_W E#
T6 P AD
T12 P AD

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

check layout

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

D D R _A_D0
D D R _A_D1
D D R _A_D2
D D R _A_D3
D D R _A_D4
D D R _A_D5
D D R _A_D6
D D R _A_D7
D D R _A_D8
D D R _A_D9
D D R _A_D10
D D R _A_D11
D D R _A_D12
D D R _A_D13
D D R _A_D14
D D R _A_D15
D D R _A_D16
D D R _A_D17
D D R _A_D18
D D R _A_D19
D D R _A_D20
D D R _A_D21
D D R _A_D22
D D R _A_D23
D D R _A_D24
D D R _A_D25
D D R _A_D26
D D R _A_D27
D D R _A_D28
D D R _A_D29
D D R _A_D30
D D R _A_D31
D D R _A_D32
D D R _A_D33
D D R _A_D34
D D R _A_D35
D D R _A_D36
D D R _A_D37
D D R _A_D38
D D R _A_D39
D D R _A_D40
D D R _A_D41
D D R _A_D42
D D R _A_D43
D D R _A_D44
D D R _A_D45
D D R _A_D46
D D R _A_D47
D D R _A_D48
D D R _A_D49
D D R _A_D50
D D R _A_D51
D D R _A_D52
D D R _A_D53
D D R _A_D54
D D R _A_D55
D D R _A_D56
D D R _A_D57
D D R _A_D58
D D R _A_D59
D D R _A_D60
D D R _A_D61
D D R _A_D62
D D R _A_D63

D D R _ A_D[0..63] <13>
<14> DDR_B_BS#0
<14> DDR_B_BS#1
<14> DDR_B_BS#2

<14> D D R _B_DM[0..7]

<14> D D R_B_DQS[0..7]

<14> D D R_B_DQS#[0..7]

<14> D D R _ B_MA[0..13]

<14> D D R_B_CAS#
<14> D D R_B_RAS#
<14> D DR_B_W E#
T4 P AD
T11 P AD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

D D R_B_DM0
D D R_B_DM1
D D R_B_DM2
D D R_B_DM3
D D R_B_DM4
D D R_B_DM5
D D R_B_DM6
D D R_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

D DR_B_DQS0
D DR_B_DQS1
D DR_B_DQS2
D DR_B_DQS3
D DR_B_DQS4
D DR_B_DQS5
D DR_B_DQS6
D DR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

D DR_B_DQS#0
D DR_B_DQS#1
D DR_B_DQS#2
D DR_B_DQS#3
D DR_B_DQS#4
D DR_B_DQS#5
D DR_B_DQS#6
D DR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

D D R_B_MA0
D D R_B_MA1
D D R_B_MA2
D D R_B_MA3
D D R_B_MA4
D D R_B_MA5
D D R_B_MA6
D D R_B_MA7
D D R_B_MA8
D D R_B_MA9
D D R_B_MA10
D D R_B_MA11
D D R_B_MA12
D D R_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

D D R_B_CAS#
D D R_B_RAS#
D DR_B_W E#
S B _ R C VENIN#
S B _RCVENOUT#

AR24
AU23
AR27
AK16
AK18

SB_BS0
SB_BS1
SB_BS2

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR SYS MEMORY B

U1 4D
<13> D DR_A_BS#0
<13> D DR_A_BS#1
<13> D DR_A_BS#2

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

check layout

C ALISTOGA_FCBGA1466~D
UMA_ GM@

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

D D R _B_D[0..63] <14>

D D R_B_D0
D D R_B_D1
D D R_B_D2
D D R_B_D3
D D R_B_D4
D D R_B_D5
D D R_B_D6
D D R_B_D7
D D R_B_D8
D D R_B_D9
D D R_B_D10
D D R_B_D11
D D R_B_D12
D D R_B_D13
D D R_B_D14
D D R_B_D15
D D R_B_D16
D D R_B_D17
D D R_B_D18
D D R_B_D19
D D R_B_D20
D D R_B_D21
D D R_B_D22
D D R_B_D23
D D R_B_D24
D D R_B_D25
D D R_B_D26
D D R_B_D27
D D R_B_D28
D D R_B_D29
D D R_B_D30
D D R_B_D31
D D R_B_D32
D D R_B_D33
D D R_B_D34
D D R_B_D35
D D R_B_D36
D D R_B_D37
D D R_B_D38
D D R_B_D39
D D R_B_D40
D D R_B_D41
D D R_B_D42
D D R_B_D43
D D R_B_D44
D D R_B_D45
D D R_B_D46
D D R_B_D47
D D R_B_D48
D D R_B_D49
D D R_B_D50
D D R_B_D51
D D R_B_D52
D D R_B_D53
D D R_B_D54
D D R_B_D55
D D R_B_D56
D D R_B_D57
D D R_B_D58
D D R_B_D59
D D R_B_D60
D D R_B_D61
D D R_B_D62
D D R_B_D63

C

B

C ALISTOGA_FCBGA1466~D
UMA_ GM@

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Calistoga (2/6)

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

8

of

47

5

4

3

2

1

D

D

+ 1.5VS_PCIE
R 54
24.9_0402_1%

U1 4C

L VDSA0+
L VDSA1+
LVDSA2+

<38>
<38>
<38>

L VDSA0L VDSA1L VDSA2-

<38>
<38>
<38>

LVDSB0+
LVDSB1+
LVDSB2+

<38>
<38>
<38>
<38>
<38>
<38>
<38>
C

L VDSAC+
L VDSACLVDSBC+
L VDSBC-

<16> GMC H_ L VDDEN

2
R 208

2
R 209

<17>
<17>
<17>

L VDSA0L VDSA1L VDSA2-

C37
B35
A37

LVDSB0+
LVDSB1+
LVDSB2+

F30
D29
F28

LVDSB0LVDSB1LVDSB2-

G30
D30
F29

L VDSAC+
L V DSACLVDSBC+
L VDSBC-

A32
A33
E26
E27

GMC H _ENBKL

TV_COMPS
T V_LUMA
T V_CRMA

L D DC_CLK
L D DC_DATA
GMC H_ L VDDEN

2

1

R 53

1.5K_0402_1%

TV_COMPS
T V_ LUMA
T V _CRMA

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32
A16
C18
A19

2 R 42

1

J20

4.99K_0402_1%

B16
B18
B19
J29
K30

<17> C R T _ VSYNC
<17> C R T _ HS YNC
<17>
CRT_B

B

2
R 210

2
R 211

2
R 212

3 VD DCCL
3 VD D CDA

C RT_R
UMA@ 150_0603_1%
C RT_G
1
UMA@ 150_0603_1%
CRT_B
1
UMA@ 150_0603_1%

1

<17>

C RT_G

<17>

C RT_R

3 VD DCCL
3 VD D CDA

C26
C25

C R T _ V SYNC
C R T _ HS YNC
CRT_B

H23
G23
E23
D23
C22
B22
A21
B21

C RT_G
C RT_R

2 R 47

1

J22

255_0402_1%

LA_DATA#0
LA_DATA#1
LA_DATA#2
LB_DATA0
LB_DATA1
LB_DATA2
LB_DATA#0
LB_DATA#1
LB_DATA#2
LA_CLK
LA_CLK#
LB_CLK
LB_CLK#
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
TVDAC_A
TVDAC_B
TVDAC_C
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

C RT

<17>
<17>

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

LA_DATA0
LA_DATA1
LA_DATA2

TV

TV_COMPS
1
UMA@ 150_0603_1%
T V_ LUMA
1
UMA@ 150_0603_1%
T V _CRMA
1
UMA@ 150_0603_1%

2

B37
B34
A36

LVDSB0LVDSB1LVDSB2-

<16> GMC H_ENBKL

R 207

L VDSA0+
L VDSA1+
L VDSA2+

EXP_COMPI
EXP_COMPO

LV DS

<38>
<38>
<38>

SDVOCTRL_DATA
SDVOCTRL_CLK

CRT_IREF

PCI-EXPRESS GRAPHICS

H27
H28

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

PEGCOMP

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

P EG_RXN0
P EG_RXN1
P EG_RXN2
P EG_RXN3
P EG_RXN4
P EG_RXN5
P EG_RXN6
P EG_RXN7
P EG_RXN8
P EG_RXN9
P EG_RXN10
P EG_RXN11
P EG_RXN12
P EG_RXN13
P EG_RXN14
P EG_RXN15

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

1

2
P EG_RXN[0..15] <18>

PEG_RXP[0..15] <18>

C

P EG_M_TXN[0..15] <18>

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

C 153
C 124
C 142
C 115
C 155
C 126
C 148
C 117
C 157
C 128
C 140
C 119
C 159
C 130
C 144
C 121

0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C 152
C 123
C 141
C 114
C 154
C 125
C 147
C 116
C 156
C 127
C 139
C 118
C 158
C 129
C 143
C 120

0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z
0 . 1 U_0402_16V4Z

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

PEG_M_TXP[0..15] <18>

B

C ALISTOGA_FCBGA1466~D
UMA_ GM@

1

1
D

S

L D DC_CLK

3

E D I D_CLK_LCD

1

E D ID_CLK_LCD <38>

2

G

Q18
BSS138_SOT23
UMA@
A

R 217
2.2K_0402_5%
UMA@

2

R 214
1
2.2K_0402_5%
@ 0_0402_5%
UMA@

2
R 709

2

1

R216
2.2K_0402_5%

UMA@

1

+3VS

2

2

UMA@

R215
2.2K_0402_5%

+2.5VS

A

G

2

+2.5VS

L D DC_DATA

3

1

E D I D_DAT_LCD

D

S
Q17
BSS138_SOT23
UMA@

2
R 710

E D ID_DAT_LCD <38>

Compal Secret Data

Security Classification
1

2005/10/06

Issued Date

@ 0_0402_5%

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Calistoga (3/6)

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

9

of

47

5

4

3

2

1

2

+ VCCP

D13

+2.5VS

@

D

D

U1 4 H

1
B26
C39
AF1

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

A38
B39

+2.5VS

AF2

+1.5VS_MPLL

2

2

C99
0.1U_0402_16V4Z

10U_1206_6.3V6M

10U_1206_6.3V6M
C105

1

2

+1.5VS_DPLLA

2

close pin G41
CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

1

2

1
+

1

+1.5VS

2

UMA@

1

2

L5
CHB1608U301_0603

2

1
+

2

1

+1.5VS

UMA@

C

+2.5VS

+3VS_TVBG

1

2

+1.5VS_T VDAC

+3VS

1

2

1

1

2

2

1

1

2

1

0_0805_5%

2
B

PCI-E/MEM/PSB PLL decoupling

+1.5VS

2

1

1

2

1

2

@

+1.5VS_MPLL

2

C13

2

1

2

A

2005/10/06

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A ND TRA DE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DE P A RTME NT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

PDF created with pdfFactory Pro trial version www.pdffactory.com

+1.5VS

2

2

1

1

2

2

R17
0_0603_5%

45mA Max.

2

2

T itle

1

@

1

Compal Secret Data

Security Classification
Issued Date

1

1

+1.5VS

R213
0_0603_5%

2

+1.5VS_HPLL

R16
0_0603_5%

45mA Max.

+1.5VS_TVDAC

C301
0.1U_0402_16V4Z

1

+1.5VS

R56
0_0603_5%

2

1

+1.5VS

10U_1206_6.3V6M

2

+1.5VS_3GPLL

1
C9

1

1

4

1

0_0603_5%

+3VS

2

C14

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

2

0.1U_0402_16V4Z

2

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

2

1

C37
2200P_0402_50V7K

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

A23
B23
B25

1

C67
0.1U_0402_16V4Z

VCCHV0
VCCHV1
VCCHV2

D21
H19

2

C104
0.1U_0402_16V4Z

VCCD_TVDAC
VCCDQ_TVDAC

2

1

2

R205

A28
B28
C28

C98
10U_1206_6.3V6M

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

C8

VCCD_HMPLL0
VCCD_HMPLL1

+3VS

C46
0.1U_0402_16V4Z

2

close pin A38

1

C45
2200P_0402_50V7K

2

1

C58
0.1U_0402_16V4Z

+1.5VS

2

+3VS_T VDACA

+3VS_T VDACA
R206

C297
2200P_0402_50V7K

AH1
AH2

+3VS_T VDACA

1

C54
0.1U_0402_16V4Z

+3VS_T VDACA

1

C55
2200P_0402_50V7K

+3VS_TVBG

E19
F19
C20
D20
E20
F20

+3VS_T VDACA

10U_1206_6.3V6M

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

+3VS_T VDACA
C304

VCCA_TVBG
VSSA_TVBG

H20
G20

0.01U_0402_25V4Z

VCCA_MPLL

C102

P O W E R

CALIST OGA_F CBGA1466~D
UMA_GM@

5

+1.5VS_DPLLB

L16
CHB1608U301_0603

+2.5VS

C97
0.1U_0402_16V4Z

C296
0.47U_0603_16V4Z

+1.5VS

VCCA_LVDS
VSSA_LVDS

1

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

2
F BM-11-160808-601-T_0603

1

0.1U_0402_16V4Z

2

C10
0.47U_0603_16V4Z
MCH_AB1

1

C12
0.22U_0603_10V7K

2

MC H_D2

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

1

0.1U_0402_16V4Z

C50
2.2U_0805_16V4Z

C24
4.7U_0805_10V4Z
C94
0.22U_0603_10V7K

1

+2.5VS_CRT DAC

+2.5VS

C49
0.1U_0402_16V4Z

2

2
B

E21
F21
G21

L4

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

+1.5VS

C100

1

+1.5VS_3GPLL
+2.5VS

2

1

330U_V_2.5VK_R9
C101

M CH_A6

AC33
G41
H41

2

1

0.1U_0402_16V4Z

2

2

1

C300

2

1

+

330U_V_2.5VK_R9
C82

1

1

R57
0_0805_5%

2

0.1U_0402_16V4Z

C

+1.5VS_PCIE

C63
2200P_0402_50V7K

2

10_0402_5%

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

AB41
AJ41
L41
N41
R41
V41
Y41

+2.5VS

W=40 mils

C71
0.1U_0402_16V4Z

+

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

B30
C30
A30

C711
4.7U_0805_10V4Z

1 1

+3VS

R220
@

1

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

C72
2200P_0402_50V7K

C91
220U_D2_4VM

D12
@
CH751H-40_SC76

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

2

C298
10U_1206_6.3V6M

2
2

+1.5VS

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

1

C306
0.1U_0402_16V4Z

C302
0.1U_0402_16V4Z

R221
@ 10_0402_5%

H22

220U_D2_4VM
C107

VCC_SYNC
+2.5VS

C108

+ VCCP

C299
0.1U_0402_16V4Z

1 1

CH751H-40_SC76

2

A

Compal Electronics, Inc.
Calistoga (4/6)

Size
Document Number
C ustom H G T 3 0 /31 LA-3061
Date:

Rev
0.1

星期四 , 二月 23, 2006

Sheet
1

10

of

47

5

4

3

2

1

Strap Pin Table
CFG[3:17] have internal pull up

C18
220U_D2_4VM

1
+

C79
@ 220U_D2_4VM

2

1
+

2

B

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

+ VCCP
+ 1.8V

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

C ALISTOGA_FCBGA1466~D
UMA_ GM@

1

2

C17
0.47U_0603_16V4Z

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C15
0.47U_0603_16V4Z

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

1

2

Place near pin AV1 & AJ1

MC H_AT41
MC H_ AM41

011
001

1

2

C103
0.47U_0603_16V4Z

CFG[2:0]

1

2

CFG5
CFG7

0 = Reserved
1 = Mobile Yonah CPU*(Default)

CFG9

0 = Lane Reversal Enable
1 = Normal Operation (Default)*

CFG6

0 = Reserved

Place near pin AT41 & AM41

C47

1

2

0.1U_0402_16V4Z

C86

2

0.1U_0402_16V4Z

C20

2

0.1U_0402_16V4Z

2

1

=
=
=
=

D

*

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation * (Default)

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled * (Default)

CFG16
1

1 = Calistoga
00
01
10
11

CFG[13:12]

1

= 667MT/s FSB
= 533MT/s FSB

0 = DMI x 2
1 = DMI x 4 * (Default)

PSB 4X CLK Enable

0.1U_0402_16V4Z

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

C106
0.47U_0603_16V4Z

C25
0.22U_0603_10V7K

C

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

10 = 1.05V* (Default)
01 = 1.5V

CFG10 CFG18

0 = Normal Operation * (Default)
1 = DMI Lane Reversal Enable

CFG19

0 = No SDVO Device Present *
(Default)

SDVO_CTRLDATA

1 = SDVO Device Present

CFG20
(PCIE/SDVO select)

0 = Only PCIE or SDVO is
operational. * (Default)
1 = PCIE/SDVO are operating
simu.

C

1

2

Place near pin BA23

1

2

1

2

C59
@ 220U_D2_4M_R45

2

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C78
10U_1206_6.3V6M

2

1

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

C21

1

2

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C27
0.47U_0603_16V4Z

2

2

1

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

CFG[19:18] have internal pull down

+ 1.8V

U1 4G

C44
10U_1206_6.3V6M

1

1

C31
1U_0603_10V4Z

2

C61
0.22U_0603_10V7K

1

C95
10U_1206_6.3V6M

C48
10U_1206_6.3V6M

C69
0.22U_0603_10V7K

D

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+ VCCP

+1.5VS

<7>

C F G5

<7>

C F G7

<7>

C F G9

<7>

C F G11

<7>

C F G12

<7>

C F G13

<7>

C F G16

1
+

R 32

1

2

R 40

1

2 @

@ 2.2K_0402_5%
2.2K_0402_5%

R 37

1

2 @

2.2K_0402_5%

R 35

1

2 @

2.2K_0402_5%

R 34

1

2 @

2.2K_0402_5%

R 38

1

2 @

2.2K_0402_5%

R 33

1

2

R 48
R 50
R 51

1
1
1

2 @ 1K_0402_5%
2 @ 1K_0402_5%
2 @ 1K_0402_5%

@ 2.2K_0402_5%

2

+3VS

C93
0.47U_0603_16V4Z

U1 4 F

+VCCP

<7>
<7>
<7>

1

C F G18
C F G19
C F G20

B

2

Place near pin BA15

C ALISTOGA_FCBGA1466~D
UMA_ GM@

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Calistoga (5/6)

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

11

of

47

5

4

3

2

U 14I

AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

D

C

B

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

1

U1 4 J

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

D

C

B

C AL ISTOGA_FCBGA1466~D
UMA_ GM@

C ALISTOGA_FCBGA1466~D
UMA_ GM@

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Calistoga (6/6)

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

12

of

47

5

4

3

2

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

<8> D D R_A_DQS#[0..7]

+ D D R_MCH_REF1

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

D D R _A_D16
D D R _A_D17

2

1

C83

C43

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C57

2

0.1U_0402_16V4Z

2

1

C85

C30

2

1

0.1U_0402_16V4Z

C92

2

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C28

2.2U_0805_16V4Z

C87

2.2U_0805_16V4Z

C89

2.2U_0805_16V4Z

2

1

D D R_A_DQS#2
D D R_A_DQS2
D D R _A_D18
D D R _A_D19

2

D D R _A_D29
D D R _A_D24
D D R _A_DM3
<14,33> EC_P80_DATA
D D R _A_D26
D D R _A_D27

C

<7> D D R _ CKE0_DIMMA
<14,33> EC_P80_CLK
<8> D DR_A_BS#2

Layout Note:
Pla c e one cap close to every 2 pullup
resistors terminated to +0.9VS

D D R _ CKE0_DIMMA

D DR_A_BS#2
D D R _A_MA12
D D R _A_MA9
D D R _A_MA8
D D R _A_MA5
D D R _A_MA3
D D R _A_MA1

<8> D DR_A_BS#0
<8> D D R_A_W E#

+0.9VS

<8> D D R _A_CAS#
<7> D D R _ C S1_DIMMA#

2

1

2

1

2

<7>

M_ODT1

D D R _A_CAS#
D D R _ C S1_DIMMA#
M_ODT1

1

D D R _A_D37
D D R _A_D36

2

D D R_A_DQS#4
D D R_A_DQS4

C33

C70

C39

C77

C64

C53

C40

C34

C42

C51

C60

C66

C74

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

D D R _A_MA10
D DR_A_BS#0
D D R_A_W E#

D D R _A_D35
D D R _A_D32
D D R _A_D40
D D R _A_D44

B

D D R _A_DM5
D D R _A_D41
D D R _A_D46
+0.9VS
RP1
D D R_A_W E#
D D R _A_CAS#
D D R _ C S1_DIMMA#
M_ODT1

1
2
3
4

R P2

8
7
6
5

56_0804_8P4R_5%

8
7
6
5

1
2
3
4

D D R _A_RAS#
D D R _ C S0_DIMMA#
M_ODT0
D D R _A_MA13

D D R _A_D49
D D R _A_D48

Layout Note:
P l ace t hese r esi st or
cl osel y JP41,all
t r ace l engt h M ax=1.5"

D D R_A_DQS#6
D D R_A_DQS6
D D R _A_D54
D D R _A_D50

56_0804_8P4R_5%

D D R _A_D61
D D R _A_D60

R P6
56_0402_5%
D DR_A_BS#0 R 39
D D R _A_MA10 R 43

1

2

1

2

5
6
7
8

4
3
2
1

D DR_A_BS#1
D D R _A_MA0
D D R _A_MA2
D D R _A_MA4

D D R _A_DM7

56_0402_5%

D D R _A_D59
D D R _A_D58

56_0804_8P4R_5%
R P7
D D R _A_MA1
D D R _A_MA3
D D R _A_MA5
D D R _A_MA8

4
3
2
1

RP9

5
6
7
8

5
6
7
8

4
3
2
1

<14,15> C LK_SMBDATA
<14,15> CLK_SMBCLK

D D R _A_MA6
D D R _A_MA7
D D R _A_MA11
D D R _ CKE1_DIMMA

C LK_SMBDATA
CLK_SMBCLK
+3VS
C7

A

56_0804_8P4R_5%

0 . 1 U_0402_16V4Z
R P10
D D R _A_MA9
D D R _A_MA12
D DR_A_BS#2
D D R _ CKE0_DIMMA

4
3
2
1

1

56_0804_8P4R_5%

5
6
7
8

2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

SO-DIMM A

2

D

M_ CLK_DDR0
M_ CLK_DDR#0

M_ CLK_DDR0 <7>
M_ CLK_DDR#0 <7>

D D R _A_D11
D D R _A_D10

D D R _A_D20
D D R _A_D21
PM_EXTTS#0 <7,14>

D D R _A_DM2
D D R _A_D23
D D R _A_D22
D D R _A_D28
D D R _A_D25
D D R_A_DQS#3
D D R_A_DQS3
D D R _A_D31
D D R _A_D30
D D R _ CKE1_DIMMA

C

D D R _ C KE1_DIMMA <7>

D D R _A_MA11
D D R _A_MA7
D D R _A_MA6
D D R _A_MA4
D D R _A_MA2
D D R _A_MA0
D DR_A_BS#1
D D R _A_RAS#
D D R _ C S0_DIMMA#
M_ODT0
D D R _A_MA13

D DR_A_BS#1 <8>
D D R _A_RAS# <8>
D D R _ C S0_DIMMA# <7>
M_ODT0

<7>

D D R _A_D39
D D R _A_D38
D D R _A_DM4
D D R _A_D34
D D R _A_D33
D D R _A_D45
D D R _A_D43
B

D D R_A_DQS#5
D D R_A_DQS5
D D R _A_D47
D D R _A_D42
D D R _A_D52
D D R _A_D53
M_ CLK_DDR1
M_ CLK_DDR#1

M_ CLK_DDR1 <7>
M_ CLK_DDR#1 <7>

D D R _A_DM6
D D R _A_D51
D D R _A_D55
D D R _A_D57
D D R _A_D56
D D R_A_DQS#7
D D R_A_DQS7
D D R _A_D62
D D R _A_D63

A

Top side
Compal Secret Data

Security Classification

56_0804_8P4R_5%

2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1

D D R _A_DM1

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

F OX_ASOA426-M2RN-7F
ME@

2

1

D D R _A_D9
D D R _A_D15

1

2

D D R_A_DQS#1
D D R_A_DQS1

100_0402_1%

2

+1.8V

2

+ D D R _MCH_REF1 <14>

D D R _A_D13
D D R _A_D12

1

1
R 87

1

2

C149
0.1U_0402_16V4Z

Layout Note:
Pla c e near JP41

D D R _A_D8
D D R _A_D14

2

2
+ D D R_MCH_REF1

<14> + D D R_MCH_REF1

D D R _A_D5
D D R _A_D7

R15
10K_0402_5%

D D R _A_D2
D D R _A_D3

100_0402_1%
D

D D R _A_DM0

R13
10K_0402_5%

1

D D R_A_DQS#0
D D R_A_DQS0

R 86

D D R _A_D6
D D R _A_D0

C134

<8> D D R _ A_MA[0..13]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C145

D D R _A_D4
D D R _A_D1

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

0.1U_0402_16V4Z

+ 1.8V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

<8> D D R _ A_DM[0..7]
<8> D D R _A_DQS[0..7]

1

+ 1.8V

JP 3

<8> D D R _A_D[0..63]

1

1

+1.8V

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
DDRII-SODIMM SLOT1

Size
D oc um ent Num ber
C u s tom HGT 3 0/31 LA-3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

13

of

47

5

4

3

2

1

+ 1.8V

<8> D D R_B_DQS#[0..7]

+1.8V

<8> D D R _B_D[0..63]

+ D D R_MCH_REF1

<8> D D R _B_DM[0..7]

D DR_B_DQS#1
D DR_B_DQS1
D D R_B_D10
D D R_B_D11
+ 1.8V

2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

D D R_B_D17
D D R_B_D20

1

C32

C88

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C75

2

0.1U_0402_16V4Z

2

1

C68

0.1U_0402_16V4Z

2

1

C22

C96

2

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C90

2

2.2U_0805_16V4Z

C23

2.2U_0805_16V4Z

C29

2.2U_0805_16V4Z

2

1

D DR_B_DQS#2
D DR_B_DQS2

2

D D R_B_D18
D D R_B_D19
D D R_B_D28
D D R_B_D25
D D R_B_DM3
<13,33> EC_P80_DATA
D D R_B_D30
D D R_B_D31

C

<7> D D R _CKE2_DIMMB

Layout Note:
Pla c e one cap close to every 2 pullup
resistors terminated to +0.9VS

<13,33> EC_P80_CLK
<8> DDR_B_BS#2

D D R _CKE2_DIMMB

DDR_B_BS#2
D D R_B_MA12
D D R_B_MA9
D D R_B_MA8
D D R_B_MA5
D D R_B_MA3
D D R_B_MA1

+ 0.9VS

1

2

1

2

1

2

1

2

1

2

1

2

<8> D D R_B_CAS#
<7> D D R _CS3_DIMMB#

1

<7>

M_ODT3

D D R_B_MA10
DDR_B_BS#0
D DR_B_W E#
D D R_B_CAS#
D D R _ CS3_DIMMB#
M_ODT3
D D R_B_D32
D D R_B_D33

2
C36

C38

C65

C84

C52

C62

C81

C56

C41

C35

C76

C80

C73

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

<8> DDR_B_BS#0
<8> D DR_B_W E#

D DR_B_DQS#4
D DR_B_DQS4
D D R_B_D34
D D R_B_D35

B

D D R_B_D40
D D R_B_D41
D D R_B_DM5
D D R_B_D42
D D R_B_D43

Layout Note:
P l ace t hese r esi st or
cl osel y JP42,all
t r ace l engt h M ax=1.5"

+0.9VS
R P3
D D R_B_CAS#
D DR_B_W E#
D D R _ CS3_DIMMB#
M_ODT3

8
7
6
5

RP4

1
2
3
4

56_0804_8P4R_5%

4
3
2
1

D D R_B_D48
D D R_B_D49

5
6
7
8

D DR_B_DQS#6
D DR_B_DQS6

D D R_B_MA13
M_ODT2
D D R _ CS2_DIMMB#
D D R_B_RAS#

D D R_B_D51
D D R_B_D50

56_0804_8P4R_5%

D D R_B_D56
D D R_B_D61

RP5
DDR_B_BS#0
D D R_B_MA10

R 44 1
2
56_0402_5%
R 41 1
2

4
3
2
1

5
6
7
8

DDR_B_BS#1
D D R_B_MA0
D D R_B_MA2
D D R_B_MA4

D D R_B_DM7
D D R_B_D59
D D R_B_D58

56_0804_8P4R_5%
R P8

RP11

4
3
2
1

4
3
2
1

5
6
7
8

+3VS

D D R_B_MA7
D D R_B_MA11
D D R_B_MA6
D D R _CKE3_DIMMB

C6
0 . 1 U_0402_16V4Z

56_0804_8P4R_5%

56_0804_8P4R_5%

1

2

2

D D R_B_DM1
M_ CLK_DDR3
M_ CLK_DDR#3

M_ CLK_DDR3 <7>
M_ CLK_DDR#3 <7>

D D R_B_D14
D D R_B_D15

D D R_B_D21
D D R_B_D16
PM_EXTTS#0 <7,13>

D D R_B_DM2
D D R_B_D22
D D R_B_D23
D D R_B_D26
D D R_B_D24
D DR_B_DQS#3
D DR_B_DQS3
D D R_B_D29
D D R_B_D27

C

D D R _CKE3_DIMMB

D D R _ CKE3_DIMMB <7>

D D R_B_MA11
D D R_B_MA7
D D R_B_MA6
D D R_B_MA4
D D R_B_MA2
D D R_B_MA0
DDR_B_BS#1
D D R_B_RAS#
D D R _ CS2_DIMMB#

D DR_B_BS#1 <8>
D D R_B_RAS# <8>
D D R _ CS2_DIMMB# <7>

M_ODT2
D D R_B_MA13

M_ODT2

<7>

D D R_B_D36
D D R_B_D37
D D R_B_DM4
D D R_B_D39
D D R_B_D38
D D R_B_D44
D D R_B_D45

B

D DR_B_DQS#5
D DR_B_DQS5
D D R_B_D46
D D R_B_D47
D D R_B_D52
D D R_B_D53
M_ CLK_DDR2
M_ CLK_DDR#2

M_ CLK_DDR2 <7>
M_ CLK_DDR#2 <7>

D D R_B_DM6
D D R_B_D54
D D R_B_D55
D D R_B_D60
D D R_B_D57
D DR_B_DQS#7
D DR_B_DQS7
D D R_B_D62
D D R_B_D63

P-TW O_A5692B-A0G16-P
ME@

SO-DIMM B

R 12

1
R14

5
6
7
8

C LK_SMBDATA
CLK_SMBCLK

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

1

D

10K_0402_5%

A

D D R_B_MA1
D D R_B_MA3
D D R_B_MA5
D D R_B_MA9

<13,15> C LK_SMBDATA
<13,15> CLK_SMBCLK

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

2

D D R_B_D12
D D R_B_D13

1

D D R_B_D8
D D R_B_D9

D D R_B_D6
D D R_B_D7

1

2

+3VS

10K_0402_5%
A

2

D D R_B_D2
D D R_B_D3

Layout Note:
Pla c e near JP42

D D R_B_DM0

C135

D

D D R_B_D5
D D R_B_D4

C146

D DR_B_DQS#0
D DR_B_DQS0

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

D D R_B_D0
D D R_B_D1

<8> D D R _ B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2.2U_0805_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<8> D D R_B_DQS[0..7]

1

+ D D R_MCH_REF1 <13>

J P4

R P12
D D R _CKE2_DIMMB 8
DDR_B_BS#2
7
D D R_B_MA12
6
D D R_B_MA8
5

1
2
3
4

5

Compal Secret Data

Security Classification
2005/10/06

Issued Date

56_0804_8P4R_5%

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
DDRII-SODIMM SLOT2

Size

D oc um ent Num ber

R ev
0 .1

HGT 3 0/31 LA-3061
D ate:

星 期 四 , 二 月 23, 2006

Sheet
1

14

of

47

5

4

FSLC

FSLB

FSLA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

3

PCI
MHz

SRC
MHz

+3VS

1

166

33.3

100

2.2K_0402_5%
Q29
2N7002_SOT23

33.3

533MHz

2

0 . 1 U_0402_16V4Z

CLK_Rd CLK_Re CLK_Rf
<21,28,37>

Stuff

CLK_Rd CLK_Re CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

1

3

D

S

IC H_SMBCLK

Stuff

CLK_Rd CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

1

1

C 413

1

C 458

1 0 U_0805_10V4Z

2

0 . 1 U_0402_16V4Z

HGT30 @ 10/11

12

2 + C K_VDD_REF
0 . 1 U_0402_16V4Z
2 + CK_VDD_48
0 . 1 U_0402_16V4Z

C 422

C LK_XTAL_IN

18
40
20

VDDA
GNDA
PCI_SRC_STOP#

VDDPCI
VDDPCI

CPU_STOP#

VDDCPU
CPUCLKT1LP
VDDREF

CLK_XTAL_OUT

R 326
1K_0402_5%

CPUCLKC1LP
CPUCLKT0LP
X1

1

C L K _ 48M_ICH

2

1

2
R 123

33_0402_5% 2

<33> C LK_PCI_LPC

33_0402_5% 2

<24> C L K_PCI_PCM

33_0402_5% 2

<27> C L K _ PCI_LAN
<32> C L K_PCI_DB

@ 1K_0402_5%

1

1

1

2

R 122
1K_0402_5%

2

<7> C L K _MCH_DREFCLK#

CLK_Rb

@

45

1 R 381
1 R 387
1 R 388

P C I_ MINI
P C I_EC
P C I _PCM

23

FSLB/TEST_MODE/24Mhz
SRCCLKT9LP
REF0/FSLC/TEST_SEL
SRCCLKC9LP

34
33
32

1 R 404 P C I_ LAN
1 R 395

27

15_0402_5% 2
15_0402_5% 2

1 R 415C LK_CODEC
1 R 145

22

MC H_ DREFCLK
2
UMA@ 33_0402_5%
MC H_ DREFCLK#
2
UMA@ 33_0402_5%

USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP

PCICLK4/FCTSEL1

CLKREQ9#

SEL_48M/PCICLK3

SRCCLKT8LP

SEL_24M/PCICLK2

SRCCLKC8LP

SEL_PCI6/PCICLK1

CLKREQ8#
SRCCLKT7LP

SEL_PCI5/REF1
SRCCLKC7LP

43
44

DOTT_96MHz/27MHz_NonspreadCLKREQ7#/48Mhz_1
DOTC_96MHz/27MHz_spread

R 120
<19> C L K _ P CI_ICH

0_0402_5%

CLK_Re

2

F SB

1

15_0402_5% 2
15_0402_5% 2

C L K _ MCH_DREFCLK 1
R 362
C L K _MCH_DREFCLK#1
R 361

<7> C L K _ MCH_DREFCLK

1

R 121
0_0402_5%

<29> C LK_14M_CODEC
<32> C LK_14M_SIO

MC H_CLKSEL1 <7>

41

C LKREF1
33_0402_5%

2
R 412

<26> C LK_PCI_1394

HGT30 @ 10/7

FSA

33_0402_5%

C L K _ 14M_ICH

2

<21> C L K _ 14M_ICH

+ VCCP

R 701
8.2K_0402_5%

X2
CPUCLKT2_ITP/SRCCLKT10LP

R 323

HGT30 @ 10/7

19

R 364
<21> C L K _ 48M_ICH

<45> C LK_ENABLE#

C L K _ P CI_ICH

2 R 372

1

P C I_ I CH

37

33_0402_5%

SRCCLKT6LP
SRCCLKC6LP

ITP_EN/PCICLK_F0
CLKREQ6#

C LK_ENABLE#

39

VTT_PWRGD#/PD

SRCCLKT5LP

B

SRCCLKC5LP

+ VCCP
CLK_SMBCLK

16

SMBCLK

CLKREQ5#/PCICLK6

SMBDAT

SRCCLKC4LP

GND

SRCCLKT3LP

GNDSRC

SRCCLKC3LP

GNDCPU

CLKREQ3#/PCICLK5

GNDREF

SRCCLKT2LP

GNDPCI

SRCCLKC2LP

2

<13,14> CLK_SMBCLK

SRCCLKT4LP

R 383

1

MCH_CLKSEL2 <7>

1

R 407
1K_0402_5%

2

17

R 430

2

C L K IREF

4

2

+3VS

+3VS

ITP

CLK_Rf

R 363

15

+3VS

PCI6

R 368

PCI5

21

1

0_0402_5%

+3VS

1

@ R 390

1

CLK_Rc

9

0_0402_5%

1

R 397
0_0402_5%

C LK_SMBDATA

CLKREQ4#

2

1

1

<13,14> C LK_SMBDATA

@ 1K_0402_5%

1

R 396
8.2K_0402_5%
C LKREF1 2
1

R 382

31
R 406

35
2

42
68

1

1

0 . 1 U_0402_16V4Z

2
2

2

1

C 233
0 . 1 U_0402_16V4Z

2

C 449
0 . 1 U_0402_16V4Z

+ C K_VDD_REF

C446

+ CK_VDD_48

R 427
2.2_0805_1%

D

27P_0402_50V8J

Y2
1 4 .31818MHZ_16PF_DSX840GA

C LK_XTAL_IN

R 405

10K_0402_5%

10K_0402_5%

GNDPCI

CLKREQ2#

GND48

SRCCLKT1LP

GNDSRC

SRCCLKC1LP
CLKREQ1#
LCD100/96/SRC0_TLP
LCD100/96/SRC0_CLP

1

C 450

2

C448

27P_0402_50V8J

+3VS

C 451

7
0 . 1 U_0402_16V4Z

8
25
24
11

2

10

H _STP_CPU#

MC H _BCLK
MC H_BCLK#

C P U_BCLK
C P U_BCLK#

Pl ace cr yst al within
500 m i l s of CK410

Place near U4
Place these components
near each pin within 40
mils.

H_STP_CPU# <21>

1

C L K_MCH_BCLK

2
0_0402_5%

1

C L K_MCH_BCLK#

2
0_0402_5%

1

C LK_CPU_BCLK

2

R 426

13

1 0 U_0805_10V4Z

H_STP_PCI# <21>

R 423

14

2

H _STP_PCI#

R 424

0_0402_5%

1

C LK_CPU_BCLK#

2

R 425

0_0402_5%

C L K_MCH_BCLK <7>
C L K_MCH_BCLK# <7>

C LK_CPU_BCLK
2
R 434
C LK_CPU_BCLK# 2
R 433

C LK_CPU_BCLK <4>
C LK_CPU_BCLK# <4>

C L K_MCH_BCLK 2
R 432
C L K_MCH_BCLK# 2
R 431

6

1
@ 49.9_0402_1%

1
@ 49.9_0402_1%

1

C

@ 49.9_0402_1%

1
@ 49.9_0402_1%

5
C L K _MCH_SSCDREFCLK
1
R 345
C L K _MCH_SSCDREFCLK#
1
R 344
C L K _ PCIE_MCARD 1
R 341
C L K _ PCIE_MCARD# 1
R 340
C L K_MCH_3GPLL
1
R 398
C L K_MCH_3GPLL#
1
R 409
C L K _PCIE_VGA
1
R 343
C L K _PCIE_VGA#
1
R 342
C L K _ P CIE_ICH
1
R 385
C L K _ PCIE_ICH#
1
R 392
C L K _ MCH_DREFCLK 1
R 347
C L K _MCH_DREFCLK#1
R 346
C LK_PCIE_SATA 1
R 413
C LK_PCIE_SATA# 1
R 416
C L K _PCIE_NC1
2
R 370
C L K _PCIE_NC1# 2
R 377

3
2
72
70
69
71
66

P C IE_SATA

1

67

P CIE_SATA#

C LK_PCIE_SATA

2

R 414

0_0402_5%

1

C LK_PCIE_SATA#

2

R 417

0_0402_5%
SATAREQ#

38

C LK_PCIE_SATA <20>
C LK_PCIE_SATA# <20>
SATAREQ# <21>

63
64
62
60
61
29
58
59

MC H _3GPLL

1

C L K_MCH_3GPLL

2

R 399
MC H_3GPLL# 1
R 410
CLKREQ5#
2
R 394
P C IE _ ICH
1
R 386
P C IE _ ICH#
1
R 393

0_0402_5%
C L K_MCH_3GPLL#

2
0_0402_5%

MC H_CLKREQ#
0_0402_5%
C L K _ P CIE_ICH
2
0_0402_5%
C L K _ PCIE_ICH#
2
0_0402_5%

1

C L K_MCH_3GPLL <7>
C L K_MCH_3GPLL# <7>
MC H_CLKREQ# <7>
C L K _ PCIE_ICH <21>

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%

2
@49.9_0402_1%

2
@ 49.9_0402_1%

2
@49.9_0402_1%

2
@ 49.9_0402_1%

2
@ 49.9_0402_1%
B

2
@ 49.9_0402_1%

1
@ 49.9_0402_1%

1
@49.9_0402_1%

C L K _ PCIE_ICH# <21>

57
55

P C I E_NC1

56

P C I E_NC1#

1

2

R 371

EXP@

1

2

R 378

EXP@

28
52
53

P C IE _MCARD 1
R 356
P C IE _MCARD#1
R 355

50

C L K _ PCIE_MCARD

2

C L K _ PCIE_MCARD#

2
0_0402_5%

C L KREQ_MCARD#
P C I E_VGA

1
R 358

51

C L K _PCIE_NC1
0_0402_5%
C L K _PCIE_NC1#
0_0402_5%
C L KREQ_NC#

0_0402_5%

26

P C I E_VGA#

2
VGA@

1

2

R 357

VGA@

C L K _PCIE_VGA
0_0402_5%
C L K _PCIE_VGA#
0_0402_5%

C L K _PCIE_NC1 <37>
C L K _PCIE_NC1# <37>
C LKREQ_NC# <37>
SATAREQ#

C L K _PCIE_MCARD <28>

2
R366

C L K _PCIE_MCARD# <28>

C L KREQ_NC#

2
R137

C L KREQ_MCARD# <28>

C L KREQ_MCARD# 2
R140

C L K _PCIE_VGA <18>

1
10K_0402_5%

+3VS

1
10K_0402_5%

1
10K_0402_5%

C L K _PCIE_VGA# <18>

46
47

2

10K_0402_5%
@

10K_0402_5%
C LK_CODEC

R 389

2

+3VS

@

P C I_ LAN

R 367

2

2

R 352
10K_0402_5%
@

@ 10K_0402_5%

P C I_ I CH

1

1

C LK_ENABLE#

2

10K_0402_5%

2

2

10K_0402_5%

0 . 1 U_0402_16V4Z

VDD48

1

MC H_CLKSEL0 <7>

@ 1K_0402_5%

C PU_BSEL2

1

C 222

R 330
1_0805_1%

C 457

1

VDDSRC
VDDSRC
VDDSRC
VDDSRC

CPUCLKC0LP

2

2

1

30
36

1

2

1

2

CLK_XTAL_OUT

1
49
54
65

C 452

1

CLK_Ra

C PU_BSEL1

0 . 1 U_0402_16V4Z

1

0_0805_5%

U2 9

CLK_Rd

R 332
0_0402_5%

2

1

C 432

L 17
C HB1608U301_0603

2
R 353
8.2K_0402_5%
FSA 2
1

F SB

2

1

R 331

2N7002_SOT23
Q28

@ R 349
56_0402_5%

1

0 . 1 U_0402_16V4Z

CLK_SMBCLK

1

C PU_BSEL0

1

C 219

1

CLK_Re

C

2

2

No Stuff

2

CLK_Ra CLK_Rb CLK_Rc

+ VCCP

<5>

1

C 218

+ C K _ VDD_MAIN1

667MHz

<5>

1 0 U_0805_10V4Z

2

G

Stuff

1

2

* (Default)

1

C 227

+ C K _ VDD_MAIN2
+3VS
+3VS

<5>

1

C LK_SMBDATA

FSB Frequency Selet:
CPU Driven

2
0_0805_5%

2

3

2

D

1

<21,28,37> IC H_ SMBDATA

Table : ICS954306

1
R 429

2.2K_0402_5%

S

1

0

100

133

D

1

+3VS

R 419

G

0

1

+ C K _ VDD_MAIN1

R 428

0

2

48

S S CDREFCLK 1
R 360
S SCDREFCLK#1
R 359

C L K _MCH_SSCDREFCLK
2
0_0402_5%
C L K _MCH_SSCDREFCLK#
2
UMA@ 0_0402_5%

UMA@

C L K _MCH_SSCDREFCLK <7>
C L K _MCH_SSCDREFCLK# <7>
A

1

A

R 374

FCTSEL1
(PIN34)

PIN43

PCI_PME=SEL_PCI6
PIN44

PIN47

PIN48

PCI_LAN

P C I_ MINI

1

2

@ 10K_0402_5%

PCI_MINI = FCTSEL1

R373

0

DOT96T

DOT96C

96/100M_T 96/100M_C

2

10K_0402_5%

1

27Mout
5

27MSSout

SRCT0

0

PIN27
CLKREQ5

1

PCICLK6

S LG8LP465VTR_QFN72

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SRCC0
4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
Clock generator

Size

D oc um ent Num ber

R ev
0 .1

HGT 3 0 /31 LA3061
D ate:

星 期 四 , 二 月 23, 2006

Sheet
1

15

of

47

A

B

C

D

E

F

G

H

1

1

+ 5VALW

1

1 2

100K_0402_5%
UMA@

2N7002_SOT23
Q15
U MA@ S

D

3

AO3413_SOT23

2

1

2

G

0 . 047U_0402_16V4Z

G

3

1

10K_0402_5%
UMA@

1
2 R 203
1
U MA@ 0_0402_5%

<9> GMC H_ L VDDEN

1

R 711

D

2

100_0402_1%
UMA@

UMA@
Q14

R 201

S

R 196

+3VS

+ LCDVDD

2

1

+ L CDVDD

Q16
DTC124EK_SC59
UMA@

2

1

C 288

2

1

1

C 289
4 . 7 U_0805_10V4Z

2 UMA@

2

C 290
4 . 7 U_0805_10V4Z
UMA@

0 . 1 U_0402_16V4Z
UMA@
2

3

2

C 291
UMA@

2

INVPW R_B+
L14

1

2 0_0805_5%

@L15

1

2 0_0805_5%

+3VS
0 . 1 U_0603_50V4Z
2
1 C 294

2

B+

R 202

1
4.7K_0402_5%
D9
C H751H-40_SC76
J P40
<33>

INVT_PW M

<33>

D AC _ BRIG
INVPW R_B+

D I SPOFF#

<33>

1

B KOFF#

E NBKL

<9> GMC H_ENBKL

2 R 52
UMA@

2

D I SPOFF#

D ISPOFF#

D 10

C H751H-40_SC76
1@
2

1

0_0402_5%

3

2

3

<33>

1
2
3
4
5
6
7

1

2

C 295
68P_0402_50V8K

R 204

MOLEX_53780-0790

2 R 89
VGA@

100K_0402_5%

1

0_0402_5%

1

<18> G7X_ENBKL

4

4

Issued Date

2005/10/06

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

PDF created with pdfFactory Pro trial version www.pdffactory.com

Compal Electronics, Inc.

Compal Secret Data

Security Classification

E

F

Title

LVDS Connector
Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
星 期 四 , 二 月 23, 2006

D ate:
G

R ev
0 .1
Sheet

16
H

of

47

A

B

C

D

E

TV-OUT Conn.
2

VGA@0_0402_5%

2

1

R 59

VGA@ 0_0402_5%

T V_ LUMA

<9>

T V_CRMA

<9>

TV_COMPS

R 224 UMA@ 0_0402_5%

2

1

R 225 UMA@ 0_0402_5%

2

1

1

R5
150_0603_1%

<9>

1

2

2

R3
150_0603_1%

VGA@ 0_0402_5%
R4
150_0603_1%

R 61

<36>

C R MA

<36>

C OMP

<36>

1

1

1

L UMA

2

2

<18> C ARD_COMP

1

1

R 60

2

<18> C AR D _ LUMA

<18> C AR D _ CRMA

1

R 223 UMA@ 0_0402_5%

Pop when with internal graphics

CRT Conn.
VGA@
<18> C AR D _ VGA_R

2

1

R 64

1

0_0402_5%

2

L1

0_0603_5%

R ED

<36>

GR EEN

<36>

B LUE

<36>

VGA@
<18> C AR D _ VGA_G

2

1

R 66

1

0_0402_5%

2

L2

0_0603_5%

1
0_0402_5%

1

1

1

0_0603_5%

@

UMA@
<9>

C RT_G

<9>

CRT_B

2

1

2

@

1

2

C2
82P_0402_50V8J

2
R 63

L3

C3
82P_0402_50V8J

C RT_R

2

2

<9>

R8
150_0603_1%

UMA@
2

2

0_0402_5%

R6
150_0603_1%

R 68

1
R7
150_0603_1%

1

2

2

C1
82P_0402_50V8J

VGA@
<18> C AR D _VGA_B

1

2

2

@

1

R 65

0_0402_5%
UMA@

2

1

R 67

0_0402_5%

Pop when with internal graphics

1
2

R 199
R 200
0_0402_5%0_0402_5%
UMA@
VGA@

2

2

R 197
R 198
0_0402_5% 0_0402_5%
VGA@
UMA@

2

+3VS

1

1

+2.5VS

1

+3VS

+3VS

1

1

+3VS
R 10
2.2K_0402_5%

G

2

R9
2.2K_0402_5%

1 2N7002_SOT23

1

R2

@ 0_0402_5%

1

+ CRT_VCC

2

R 75

2

1

R 11

@ 0_0402_5%

0_0402_5%

1

3 VD DCCL

3

VGA_DDC_CLK <36>

0_0402_5%
UMA@

<9>

3

1

2

R 76

D

3 VD DCDA

Q2
1 2N7002_SOT23

S

UMA@
<9>

VGA_DDC_DAT <36>

2

3
2

3

2

Q1

2

VGA@1
10_0402_5%
VGA@ 0_0402_5%

G

2
2

D

R 80
R 79

S

<18> C AR D _DDCDATA
<18> C AR D _DDCCLK

0 . 1 U_0402_16V4Z

R1
1K_0402_5%

2
4

G

J VGA_HS <36>

2

C4

2

A

U2

Y

4

J VGA_VS <36>

3

G

Pop when with internal graphics

1

1

39_0402_5%

1 U MA@ 2
R 77
39_0402_5%

U1

Y

74AHCT1G125GW _SOT353-5

3

0_0402_5%

5

R 78

+ CRT_VCC

1

1 UMA@ 2

A

OE#

<9> C R T _ VSYNC

R 81

2

0_0402_5%
VGA@

P

<9> C R T _ HS YNC

2

1

0.1U_0402_16V4Z

<18> C AR D _ VS YNC

2
R 82

P

VGA@
<18> C AR D _ HS YNC

1

C5

5

2

OE#

1

74AHCT1G125GW _SOT353-5

4

4

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D

Title

Compal Electronics, Inc.
CRT & TVout

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
E

17

of

47

5

4

3

2

1

D

D

MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V

PEG_M_TXP[0..15]

PEG_M_TXP[0..15] <9>

P EG_M_TXN[0..15]

P EG_M_TXN[0..15] <9>

PEG_RXP[0..15]

PEG_M_TXP13
PEG_M_TXN13
PEG_M_TXP15
PEG_M_TXN15
+1.5VS

+3VS

<@R03>
+ 2.5VS

PEG_M_TXP0
PEG_M_TXN0

PEG_RXP3
P EG_RXN3

PEG_M_TXP2
PEG_M_TXN2

PEG_RXP5
P EG_RXN5

PEG_M_TXP4
PEG_M_TXN4

PEG_RXP7
P EG_RXN7

PEG_M_TXP6
PEG_M_TXN6

PEG_RXP9
P EG_RXN9

PEG_M_TXP8
PEG_M_TXN8

PEG_RXP11
P EG_RXN11

PEG_M_TXP10
PEG_M_TXN10

PEG_RXP13
P EG_RXN13

PEG_M_TXP12
PEG_M_TXN12

PEG_RXP15
P EG_RXN15

PEG_M_TXP14
PEG_M_TXN14

+5VS

+1.8VS

<@R03>

<15> C L K _PCIE_VGA
<15> C L K _PCIE_VGA#
<17> C AR D _DDCCLK
<17> C AR D _ DDCDATA

B+

<17> C AR D _ VS YNC
<17> C AR D _ HS YNC
<17> C AR D _VGA_R
<17> C AR D _VGA_G
<17> C AR D_VGA_B

ACES_88363-08001
ME@

B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

P E G_RXN[0..15]

P E G_RXN[0:15] <9>

PEG_RXP0
P EG_RXN0
PEG_RXP2
P EG_RXN2
PEG_RXP4
P EG_RXN4
PEG_RXP6
P EG_RXN6

C

PEG_RXP8
P EG_RXN8
+5VS

PEG_RXP10
P EG_RXN10
PEG_RXP12
P EG_RXN12

2

PEG_RXP14
P EG_RXN14
S USP#
G7X_THER_ALERT#

S USP#
<24,26,33,34,35,37,43,44>
G7X_THER_ALERT# <21>

1

+ 2.5VS

VGA@

2

1

VGA@

2

1

VGA@

2

1

0.1U_0402_16V4Z
C113

PEG_M_TXP11
PEG_M_TXN11

PEG_RXP1
P EG_RXN1

0.1U_0402_16V4Z
C112

PEG_M_TXP9
PEG_M_TXN9

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

0.1U_0402_16V4Z
C240

PEG_M_TXP7
PEG_M_TXN7
C

PEG_RXP[0:15] <9>

JP 8

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

VGA@

G7X_ENBKL <16>
PLTRST_VGA# <19>

+3VS

C ARD_COMP <17>
C AR D _ LUMA <17>
C AR D _CRMA <17>

ACES_88363-08001
ME@

< New Add Pin.28 for +3VS, Pin.68 for +1.8VS @R03 >

1

2

VGA@

C111
0.047U_0402_16V4Z

PEG_M_TXP5
PEG_M_TXN5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

0.1U_0402_16V4Z
C244

PEG_M_TXP3
PEG_M_TXN3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

C110
0.047U_0402_16V4Z

JP7
PEG_M_TXP1
PEG_M_TXN1

1

2

B

VGA@

A

A

Title
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Compal Electronics, Inc.
VGA/B connector

Size
D oc um ent Num ber
C u s tom HGT 3 0 / 31 LA3061
D ate:

星 期 四 , 二 月 23, 2006

Sheet
1

18

R ev
0 .1
of

47

5

4

3

2

1

D

D

+3VS

P C I_DEVSEL#

P C I_ FRAME#

2 8.2K_0402_5%

P CI_PLOCK#

R 287 1

2 8.2K_0402_5%

P C I_ IR D Y#

R 274 1

2 8.2K_0402_5%

P C I_SERR#

R 276 1

2 8.2K_0402_5%

P C I_PERR#

R 272 1

2 8.2K_0402_5%

P CI_REQ4#

R 270 1

2 8.2K_0402_5%

P CI_REQ3#

U3 B

<24,26,27,32> P C I_ AD[0..31]

P C I _AD0
P C I _AD1
P C I _AD2
P C I _AD3
P C I _AD4
P C I _AD5
P C I _AD6
P C I _AD7
P C I _AD8
P C I _AD9
P C I _AD10
P C I _AD11
P C I _AD12
P C I _AD13
P C I _AD14
P C I _AD15
P C I _AD16
P C I _AD17
P C I _AD18
P C I _AD19
P C I _AD20
P C I _AD21
P C I _AD22
P C I _AD23
P C I _AD24
P C I _AD25
P C I _AD26
P C I _AD27
P C I _AD28
P C I _AD29
P C I _AD30
P C I _AD31

C

+3VS

R 298 1

2 8.2K_0402_5%

P C I _PIRQA#

R 300 1

2 8.2K_0402_5%

P C I_PIRQB#

R 294 1

2 8.2K_0402_5%

P C I _PIRQC#

R 291 1

2 8.2K_0402_5%

P C I _PIRQD#

R 283 1

2 8.2K_0402_5%

P C I_PIRQE#

R 290 1

2 8.2K_0402_5%

P C I _PIRQF#

R 279 1

2 8.2K_0402_5%

P C I _PIRQG#

R 284 1

2 8.2K_0402_5%

P C I_ PIRQH#

R 286 1

2 8.2K_0402_5%

P CI_REQ0#

R 264 1

2 8.2K_0402_5%

P CI_REQ1#

R 261 1

2 8.2K_0402_5%

P CI_REQ2#

R 282 1

2 8.2K_0402_5%

P CI_REQ5#

<24> P C I_PIRQA#
P C I_PIRQB#

P C I _PIRQA#
P C I_PIRQB#
P C I _PIRQC#
P C I _PIRQD#

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

PCI

C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#

Interrupt
PIRQA#
PIRQB#
PIRQC#
PIRQD#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

P CI_REQ0#
P C I _GNT0#
P CI_REQ1#

P CI_REQ0# <26>
P C I_GNT0# <26>

P CI_REQ2#
P C I _GNT2#
P CI_REQ3#
P C I _GNT3#
P CI_REQ4#

P CI_REQ2#
P C I_GNT2#
P CI_REQ3#
P C I_GNT3#

B15
C12
D12
C15

P C I_CBE#0
P C I_CBE#1
P C I_CBE#2
P C I_CBE#3

<24>
<24>
<27>
<27>
+3VS

P CI_REQ5#

5

2 8.2K_0402_5%

R 273 1

P CI_CBE#0
P CI_CBE#1
P CI_CBE#2
P CI_CBE#3

P C I_PCIRST#

<24,26,27,32>
<24,26,27,32>
<24,26,27,32>
<24,26,27,32>

1

U2 1

B

P

R 263 1

A

G

P C I_ TRDY#

Y

2

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

P C I_ IR D Y#
P C I _PAR
P C I_PCIRST#
P C I_DEVSEL#
P C I_PERR#
P CI_PLOCK#
P C I_SERR#
PCI_STOP#
P C I_ TRDY#
P C I_ FRAME#

C26
A9
B19

PCI_PLTRST#
C L K _ P CI_ICH
P C I_PME#

G8
F7
F8
G7

P C I_PIRQE#
P C I _PIRQF#
P C I _PIRQG#
P C I_ PIRQH#

AE9
AG8
AH8
F21
AH20

P C I_ IR DY# <24,26,27>
P C I_PAR <24,26,27>

4

P CI_RST#

P CI_RST# <21,24,25,26,27,32,33>

T C7SH08FUF_SSOP5

3

2 8.2K_0402_5%

C

2

1

R 257

P CI_DEVSEL# <24,26,27>
P C I_PERR# <24,26,27>

@ 0_0402_5%
+3VS
R 236

P C I_SERR# <24,26,27>
PCI_STOP# <24,26,27>
P C I_ TRDY# <24,26,27,32>
P C I_FRAME# <24,26,27,32>

2

5

PCI_STOP#

R 269 1

PCI_PLTRST#

1

U1 8

B

Y

2

A

C L K _ P CI_ICH <15>
P CI_PME# <33>

2

P C I_PIRQE#
P C I_PIRQF# <27>
P C I_PIRQG# <26>
P C I_ PIRQH# <26>

R 235

1

PLTRST_VGA# <18>

0_0402_5%

P

2 8.2K_0402_5%

4

PLT_RST#

PLT_RST# <7,23,28,37>

G

2 8.2K_0402_5%

R 268 1

T C7SH08FUF_SSOP5

3

R 271 1

1
@ 0_0402_5%

MC H_ IC H_ S YNC# <7>

Place closely pin A9

IC H7 _BGA652~D

C L K _ P CI_ICH
B

2

B

R 277

1

@ 10_0402_5%

C 364
@ 8.2P_0402_50V

1

2

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
ICH7-M(1/4)

Size

D oc um ent Num ber

R ev
0 .1

HGT 3 0 /31 LA3061
D ate:

星 期 四 , 二 月 23, 2006

Sheet
1

19

of

47

4

OUT

1
4

U3 A

AB1
AB2

IC H_RTCX2

15P_0402_50V8J

D

R293 1
20K_0402_5%

+ RTCVCC

IC H_RTCRST#

2

IC H_ INT V RMEN
S M_ I NTRUDER#

J1

1

RTXC1
RTCX2

AA3

L P C _AD[0..3] <32,33>

RTCRST#

W4
Y5

INTVRMEN
INTRUDER#

2

LDRQ0#
LDRQ1# / GPIO23

3 MM

1

2

R 288

V3

1 M_0402_5%

U3

2

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

S M_ I NTRUDER#

LAN_CLK
LAN_RSTSYNC

U5
V4
T5

+ RTCVCC

1

2

1

1 R 310

2

1
R 314

<29> IC H_ AC _ S DIN0
<28> IC H_ AC _ S DIN1

1

<28> IC H_ S DOUT_MDC

IC H_ A C_BITCLK_R
IC H_ AC _ S Y NC_R
33_0402_5%
IC H_ AC_RST_R#
2
33_0402_5%
IC H_ AC _ SDIN0
IC H_ AC _ SDIN1

U1
R6

IC H_ A C_SDOUT_R
33_0402_5%

T4

2
2

R 281

<28> IC H_RST_MDC#

IC H_ INT V RMEN
C

2

R 315

SATA_LED#

<38> SATA_LED#

R 702
R 703

1
1

<15> C LK_PCIE_SATA#
<15> C L K_PCIE_SATA

1K_0402_5%
1K_0402_5%

2
2

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT

AF3
AE3
AG2
AH2

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA_CLKN
SATA_CLKP

AH10
AG10

2

SATARBIASN
SATARBIASP

24.9_0402_1%

4.7K_0402_5% 2
8.2K_0402_5% 2
10K_0402_5% 2

1 R 266
1 R 265
1 R 259

P D _ IO RDY
P D _IRQ
SATA_LED#

<23>
<23>
<23>
<23>
<23>

B

P D _ IORDY
P D _IRQ
P D_DACK#
P D _IOW #
P D _IOR#

P D _ IO RDY
P D _IRQ
P D _DACK#
P D_IOW #
P D _IOR#

IDE

AG16
AH16
AF16
AH15
AF15

RCIN#
SMI#
NMI
STPCLK#
THERMTRIP#

DCS1#
DCS3#

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

AA6
AB5
AC4
Y6

L P C_AD0
L P C_AD1
L P C_AD2
L P C_AD3

AC3
AA5

L PC_DRQ0#

AB3

L P C_FRAME#

D

L PC_DRQ#0 <32>

L P C _FRAME# <32,33>

1 R 250 10K_0402_5%

2

AE22
AH28

G ATEA20
H_ A 20M#

AG27

H_ C PUSLP_R#

2

AF24
AH25

DPRSLP#
H _DPSLP#

2

AG26

H_ F ERR#

AG24

H_ PW RGOOD

AG22
AG21
AF22
AF25

H_ IGNN E#

@

2

KB_RST#

AF23
AH24

H_ S MI#
H _ NMI

AH22

H_STPCLK#

AF26

T HR MT RIP_ICH#

1 R 233 0_0402_5%

H_ C PUSLP# <4,7>

1 R 243 0_0402_5%

H_DPRSTP# <4,45>

H_ DPSLP# <4>

1

H_ F E RR# <4>

56_0402_5% + VCCP
R 234

H_ PW RGOOD <4>
H_ IGNNE # <4>

H_ INI T#
H_ IN TR

AG23

+3VS

GATEA20 <33>
H_ A20M# <4>

H_ INIT#
H_ INT R

2

DA0
DA1
DA2

SATALED#

AF1
AE1

R 275
+3VS

ACZ_RST#

T2
T3
T1

AF7
AE7
AG6
AH6

C LK_PCIE_SATA#
C LK_PCIE_SATA

1

R5

SATA

HGT30 @ 10/11

ACZ_BCLK
ACZ_SYNC

AF18

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

<23> PSATA_IRX_DTX_N0_C
<23> PSATA_IRX_DTX_P0_C

SATA RX n/p need tie to GND when no used

IGNNE#
INIT3_3V#
INIT#
INTR

AC-97/AZALIA

332K_0402_1%

FERR#

R 311
33_0402_5%

1
1

<28> IC H_ B ITCLK_MDC
<28> IC H_ S YNC _ MDC

CPUSLP#

GPIO49 / CPUPWRGD
LAN_TXD0
LAN_TXD1
LAN_TXD2

2

@ 10_0402_5%
10P_0402_25V8K

R 296

A20GATE
A20M#

TP1 / DPRSTP#
TP2 / DPSLP#

LAN_RXD0
LAN_RXD1
LAN_RXD2

U7
V6
V7

C 389@

LAN

C 392
1 U_ 0603_10V4Z

1

LFRAME#

W1
Y1
Y2
W3

CPU

+ RTCVCC

LAD0
LAD1
LAD2
LAD3

<4>
<4>

1 R 251 10K_0402_5%

+ VCCP

+3VS

KB_RST# <33>

1

IN

NC

RTC

C 196

NC

H_ S MI#
H _ NMI

<4>
<4>

R 245
C

56_0402_5%

H_STPCLK# <4>

2

3

LPC

2

1

1

Y1
3 2 .768KHZ_12.5P_1TJS125BJ2A251

2

IC H_RTCX1

15P_0402_50V8J

R109
10M_0402_5%

C 195

3

2

5

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DDREQ

1 R 237

2

H_ T HERMTRIP# <4,7>

24.9_0402_1%

AH17
AE17
AF17

P D_A0
P D_A1
P D_A2

AE16
AD16

P D_CS#1
P D_CS#3

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

P D_D0
P D_D1
P D_D2
P D_D3
P D_D4
P D_D5
P D_D6
P D_D7
P D_D8
P D_D9
P D_D10
P D_D11
P D_D12
P D_D13
P D_D14
P D_D15

AE15

P D_DREQ

P D _A0
P D _A1
P D _A2

<23>
<23>
<23>

PD_CS#1 <23>
PD_CS#3 <23>

PD_DREQ <23>

B

IC H7_BGA652~D

P D _D[0..15]
<23> PSATA_ITX_DRX_N0

<23> PSATA_ITX_DRX_P0

PSATA_ITX_DRX_N0
1
C 387

2

PSATA_ITX_DRX_P0

2

1
C 388

P D _D[0..15] <23>

PSATA_ITX_DRX_N0_C
3900P_0402_50V7K
PSATA_ITX_DRX_P0_C
3900P_0402_50V7K
BATT1.1

+ RTCVCC

Close to U7

+

R 114

1
1

<29> IC H_ S D O UT_AUDIO

R 299

IC H_ A C_SDOUT_R
33_0402_5%

2

IC H_ AC _ S Y NC_R
33_0402_5%

1

2

100_0603_1%
C 203

A

R 280

1

<29> IC H_ R S T_AUDIO#

<29> IC H_ B IT CLK_AUDIO

R 313

1
1 R 312

2

2

2

0 . 1 U_0402_16V4Z

+ C HGRTC ML1220T13RE
45@

RB751V_SOD323

2 IC H_ AC_RST_R#
33_0402_5%

A

IC H_ A C_BITCLK_R
33_0402_5%

2

@ C 390
2 2P_0402_50V8J

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2

D3

1
1

<29> IC H_ S YNC _ AUDIO

BATT1

1
W=20mils

2

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
ICH7-M(2/4)

Size
D oc um ent Num ber
C us tom HGT 3 0 /31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

20

of

47

5

4

3

2

1

Place closely pin B2

+3VS

Place closely pin AC1

C L K _ 48M_ICH

2

2.2K_0402_5%

+ 3VALW

IC H _SMBCLK
IC H_ SMBDATA
L I NKALERT#
IC H_ S M LINK0
IC H_ S M LINK1

C22
B22
A26
B25
A25

IC H_ R I#

A28

SB_SPKR
SUS_STAT#
ITP_DBRESET#

A19
A27
A22

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

+ 3VALW
R 232
10K_0402_5%
R 242 1
2 L I NKALERT#

1
<29>

10K_0402_5%
R 246 1
2 OCP#

<7> P M_ BMBUSY#
<4>

10K_0402_5%
S P I_MISO

2

O CP#

<15> H_STP_PCI#
<15> H_STP_CPU#

10K_0402_5%
R 285 1
2 S PI_CS#

P M_ B MBUSY#
OCP#

AB18

GPIO0 / BM_BUSY#

B23

H _STP_PCI#
H _STP_CPU#

ID ERST_CD#

<23> IDERST_CD#

SPKR
SUS_STAT#
SYS_RST#

GPIO18 / STPPCI#
GPIO20 / STPCPU#

A21

GPIO26

B21
E23
R 255 1

C

1K_0402_5%
2 IC H_ PCIE_W AKE#

<24,26,27,33> P C I_ C LKRUN#

<28,37> IC H_ P CIE_W AKE#
<24,26,32,33> S IRQ
<33> E C_THERM#

10K_0402_5%
S P I_MOSI

2

GPIO27
GPIO28

AG18

GPIO32 / CLKRUN#

<45>

VGATE

PWROK
GPIO16 / DPRSLPVR
TP0 / BATLOW#
PWRBTN#
LAN_RST#

VRMPWRGD

AC21
AC18
E21

GPIO

GPIO6
GPIO7
GPIO8
IC H7_BGA652~D

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

2

1

2

2

1

C 384

C 391
D

S B _INT_FLASH_SEL <34>

1 R260

@ 4.7P_0402_50V8C

2

@ 4.7P_0402_50V8C

100_0402_5%

AC1
B2

C L K _ 14M_ICH
C L K _ 48M_ICH

C L K _ 14M_ICH <15>
C L K _ 48M_ICH <15>

C20

IC H_ SUSCLK

B24
D23
F22

SLP_S3#
SLP_S4#
SLP_S5#

AA4

IC H _POK

SLP_S4# <33>
T44

P AD

SLP_S3#

SLP_S4#

@ 0_0402_5%

SLP_S5#

C21

D P RSLPVR
1
2
R 90
100_0402_5%
IC H_LOW _BAT#

C23

PBTN_OUT#

C19

P CI_RST#

Y4

EC_RSMRST#
R 297 10K_0402_5%

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

2

SLP_S5# <33>

R 295

2 10K_0402_5%

1

AC22

1
R482

<33>

IC H_POK <7,33>

D PRSLPVR <7,45>

PBTN_OUT# <33>
PCI_RST# <19,24,25,26,27,32,33>

1

WAKE#
SERIRQ
THRM#

AD22

G7X_THER_ALERT#
E C _SMI#

<18> G7X_THER_ALERT#
<33>
E C _SMI#

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

<>

AF19
AH18
AH19
AE19

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

IC H_ PCIE_W AKE# F20
S I RQ
AH21
E C_THERM#
AF20
V GATE

CLK14
CLK48

RSMRST#

AC19
U2

8.2K_0402_5%
R 252 2
1 IC H_LOW _BAT#
10K_0402_5%
R 240 1
W L_ON
2
R 292 1

P C I_ C LKRUN#

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO11 / SMBALERT#

AC20
AF21

GPIO

R 304 1

RI#

SYS

SB_SPKR
P AD T41
<4> ITP_DBRESET#

ITP_DBRESET#

2

2

8.2K_0402_5%

150_0402_5%
R 248 1

@ 10_0402_5%

U 3C

SMB

<15,28,37> IC H_ SMBCLK
<15,28,37> IC H_ S MBDATA

1

1

10K_0402_5%

2

2.2K_0402_5%

D

1

1

R 241

2

R 239
10K_0402_5%

R 308

@ 10_0402_5%

SATA
GPIO

P C I_ C LKRUN#

2

10K_0402_5%
R 254 1
2 G7X_THER_ALERT#

R 305
R 247

Clocks

R 258 1

R 256

POWER MGT

8.2K_0402_5%

2

1

S I RQ

2

2

R 253 1

C L K _ 14M_ICH

+ 3VALW

1

+ 3VALW
10K_0402_5%

EC_RSMRST# <33>

2

E C _SCI#

E C _SCI#
A C IN

E C _LID_OUT#

<33>
<33,39>

D P RSLPVR

C PUSB#
W L_ON
E C _ FLASH#
SATAREQ#

C PUSB#

2

C

1

R 91
@ 100K_0402_5%

E C_LID_OUT# <33>
<37>

E C _FLASH# <34>
SATAREQ# <15>
K ILL_MDC# <28>

Need update symbol

0 . 1U_0402_16V7K
0 . 1U_0402_16V7K

C 323
C 331

P C IE_RXN1
P CIE_RXP1
P CIE_C_TXN1
PCIE_C_TXP1

F26
F25
E28
E27

<28> P C IE_RXN2
<28> PCIE_RXP2
<28> PCIE_TXN2
<28> PCIE_TXP2

0 . 1U_0402_16V7K
0 . 1U_0402_16V7K

C 328
C 329

P C IE_RXN2
P CIE_RXP2
P CIE_C_TXN2
PCIE_C_TXP2

H26
H25
G28
G27

PERn1
PERp1
PETn1
PETp1
PERn2
PERp2
PETn2
PETp2
PERn3
PERp3
PETn3
PETp3

M26
M25
L28
L27

B

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

USB_OC#0

<37>

USB_OC#2

<37>

USB_OC#4

R2
P6
P1

S P I_MOSI
S P I_MISO

P5
P2

U SB_OC#0
U SB_OC#1
U SB_OC#2
U SB_OC#3
U SB_OC#4
U SB_OC#5
U SB_OC#6
U SB_OC#7

PERn6
PERp6
PETn6
PETp6
SPI_CLK
SPI_CS#
SPI_ARB

SPI

<31>

S PI_CS#

PCI-EXPRESS

K26
K25
J28
J27

DIRECT MEDIA INTERFACE

U 3D
<37> P C IE_RXN1
<37> PCIE_RXP1
<37> PCIE_TXN1
<37> PCIE_TXP1

SPI_MOSI
SPI_MISO

D3
C4
D5
D4
E5
C3
A2
B3

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

A

USB

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

V26
V25
U28
U27

D MI _RXN0
D M I_RXP0
D M I_TXN0
DMI_TXP0

Y26
Y25
W28
W27

D MI _RXN1
D M I_RXP1
D M I_TXN1
DMI_TXP1

AB26
AB25
AA28
AA27

D MI _RXN2
D M I_RXP2
D M I_TXN2
DMI_TXP2

AD25
AD24
AC28
AC27

D MI _RXN3
D M I_RXP3
D M I_TXN3
DMI_TXP3

AE28
AE27

C L K _ PCIE_ICH#
C L K _ P CIE_ICH

C25
D25

D MI_ IRCOMP

D MI_RXN0
D MI_RXP0
D MI_TXN0
DMI_TXP0

<7>
<7>
<7>
<7>

D MI_RXN1
D MI_RXP1
D MI_TXN1
DMI_TXP1

<7>
<7>
<7>
<7>

D MI_RXN2
D MI_RXP2
D MI_TXN2
DMI_TXP2

<7>
<7>
<7>
<7>

D MI_RXN3
D MI_RXP3
D MI_TXN3
DMI_TXP3

<7>
<7>
<7>
<7>

C L K _ PCIE_ICH# <15>
C L K _ P CIE_ICH <15>
R 238 24.9_0402_1%

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

US B20_N0
U SB20_P0
US B20_N1
U SB20_P1
US B20_N2
U SB20_P2

D2
D1

US B RBIAS

B

1

2

US B20_N4
U SB20_P4

Within 500 mils
+ 1.5VS

US B20_N0
USB20_P0
US B20_N1
USB20_P1
US B20_N2
USB20_P2

RP15
U SB_OC#4
U SB_OC#2
U SB_OC#3
U SB_OC#1

<31>
<31>
<28>
<28>
<37>
<37>

5
6
7
8

+ 3VALW

10K_1206_8P4R_5%

RP16

US B20_N4 <37>
USB20_P4 <37>
T701 P AD
T702 P AD

US B20_N7
U SB20_P7

4
3
2
1

U SB_OC#0
U SB_OC#5
U SB_OC#6
U SB_OC#7

4
3
2
1

5
6
7
8

+ 3VALW

10K_1206_8P4R_5%

US B20_N7 <37>
USB20_P7 <37>
R 307 22.6_0402_1%

USBRBIAS#
USBRBIAS

1

2

Within 500 mils
A

IC H7_BGA652~D

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
ICH7-M(3/4)

Size
D oc um ent Num ber
C u s tom HGT 3 0 /31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

21

of

47

5

4

3

2

1

+ VCCP
U 3F

F6

+3VS
C327

2

1

+

R 278

D 15
C H751H-40_SC76

C335

1

C 340

2

1

C332

2

0 . 1 U_0402_16V4Z

1

2
0 . 1 U_0402_16V4Z

1

2

100_0402_5%

2

220U_D2_4VM

+5VS

1

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

IC H_ V5 R E F_RUN

1

2

1

C 362
0 . 1 U_0402_16V4Z

2

Place closely pin
D28,T28,AD28.

C 361
0 . 1 U_0402_16V4Z

2

1

+ 5VALW + 3VALW

R 289

D 16

C

C H751H-40_SC76

1

2

10_0402_5%

1

2

IC H_ V5 REF_SUS

C 371
0 . 1 U_0402_16V4Z

+3VS

C352
0 . 1 U_0402_16V4Z

1

2

Place closely pin AG28 within 100mlis.
+ 1 .5VS_DMIPLLR

+ 1.5VS_DMIPLL

B27

R 230

2

1

0.5_0805_1%

2
0_0805_5%

C375

+1.5VS

1

2

0.1U_0402_16V4Z

B

+ 1.5VS_DMIPLL

1

1

+1.5VS

2

2

C 338
0 . 0 1U_0402_25V4Z
C 373
0 . 1 U_0402_16V4Z

1

2

C 372

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

1

2

AD2
AH11
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

+ 1.5VS
C 365
1 U_ 0603_10V4Z

1

2

E3

Place closely pin AG9.

+ 3VALW

0 . 1 U_0402_16V4Z

AG28

Place closely pin AG5.
+3VS

C355
0.1U_0402_16V4Z

R 229

1

C330
10U_0805_10V4Z

+1.5VS

1

C1

+1.5VS

2

1

C 366
0 . 1 U_0402_16V4Z

T47
T45

P AD
P AD

IC H_ A A2
I C H_ Y7

AA2
Y7

2

+ 3VALW
+3VS

1

V5
V1
W2
W7

2

R 712

@ 0_0402_5%

1

2

R 497

0_0402_5%

1

V5REF_Sus
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

Vcc3_3[1]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

VccDMIPLL
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

Vcc1_5_A[19]
Vcc1_5_A[20]

VccSATAPLL
Vcc3_3[2]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

1
C 363

1

C 357

2

1

+ C 351

2

2

2 2 0U_D2_4VM

1 U_ 0603_10V4Z

U6

+3VS

R7

+3VALW

1

+ VCCP
C 354

AE23
AE26
AH26

1

2

2

C 356
0 . 1 U_0402_16V4Z

0 . 1 U_0402_16V4Z

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

1

+3VS

1

2

C 353
0 . 1 U_0402_16V4Z

C 359

1
2

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

1

2

1

2

2

0 . 1 U_0402_16V4Z
C 358
4 . 7 U_0805_10V4Z

1

2

+3VS

W5

+ RTCVCC

P7
1

A24
C24
D19
D22
G19

2

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

1

2

1

C 386
0 . 1 U_0402_16V4Z

1

C 367
0 . 1 U_0402_16V4Z

AB17
AC17

2

2

+ 3VALW
C 376
0 . 1 U_0402_16V4Z

1

1

2

2

C370
0.1U_0402_16V4Z

IC H_ V5 REF_SUS
0 . 1 U_0402_16V4Z

V5REF[2]

0 . 1 U_0402_16V4Z

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C369
0.1U_0402_16V4Z

+1.5VS
D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C337
0.1U_0402_16V4Z

AD17

U3E

V5REF[1]

C350
0.1U_0402_16V4Z

G10

C368
0.1U_0402_16V4Z

IC H_ V5 R E F_RUN

+ 3VALW
C 377
0 . 1 U_0402_16V4Z

+1.5VS

T7
F17
G17
AB8
AC8

1

2

K7

C 348 0 . 1 U_0402_16V4Z
IC H _K7
P AD

T46

C28
G20

IC H_ C28
IC H_ G20

T15
T43

A1
H6
H7
J6
J7

P AD
P AD
+1.5VS

1

2

C 360
0 . 1 U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

D

C

B

IC H7_BGA652~D

IC H7 _BGA652~D
C349

A

A

2

0 . 1 U_0402_16V4Z

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
ICH7-M(4/4)

Size
D oc um ent Num ber
C u s tom HGT 3 0 /31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

22

of

47

5

4

3

2

1

JP 9

D

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

<20> PSATA_ITX_DRX_P0
<20> PSATA_ITX_DRX_N0

2
2

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

2
@ 0_0805_5%

1

2

R 170

0_0805_5%

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

+5VS

+3VS
0 . 1 U_0402_16V4Z

1

2

1

1

1
C256

2

2

1
C 271

2

2

1 U_ 0603_10V4Z

1

2

@

@ 0 . 1 U_0402_16V4Z

1

1

1
C 247

2

2

1
C 251

2

2

@ 1 U_ 0603_10V4Z

@

Pleace near HD CONN

Pleace near HD CONN

C245
0.1U_0402_16V4Z

+5VS

1
R 151

C246
1000P_0402_50V7K

+3VS

1
3900P_0402_50V7K

C252
22U_1206_6.3V6M

C 234

PSATA_IRX_DTX_P0

C258
0.1U_0402_16V4Z

<20> PSATA_IRX_DTX_P0_C

PSATA_IRX_DTX_N0

1
3900P_0402_50V7K

C257
1000P_0402_50V7K

C 230

D

GND
A+
AGND
BB+
GND

C266
22U_1206_6.3V6M

<20> PSATA_IRX_DTX_N0_C

1
2
3
4
5
6
7

@

ALLTO_C16630-122A4-L_RV

Main SATA +5V Default

C

P D _D[0..15]

C

P D _D[0..15] <20>

P D _A[0..2]

P D _A[0..2] <20>

J P10

<21> IDERST_CD#
<7,19,28,37> PLT_RST#

R 262
R 267

1
1

2@
2

<29>
INT _CD_L
<29> C D _ AGND
0_0402_5%
33_0402_5%

P D_D7
P D_D6
P D_D5
P D_D4
P D_D3
P D_D2
P D_D1
P D_D0

B

1

+3VS

P D_IOW #
P D _ IO RDY
P D _IRQ
P D_A1
P D_A0
P D_CS#1

<20> P D_IOW #
<20> P D _ IO RDY
<20>
P D_IRQ

2

R 249
10K_0402_5%

<38> O DD_LED#

O DD_LED#

<20>

PD_CS#1

+5VS

2

P R I_CSEL

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

INT _ CD_R <29>
P D_D8
P D_D9
P D_D10
P D_D11
P D_D12
P D_D13
P D_D14
P D_D15
P D_DREQ
P D _IOR#

B

P D_DREQ <20>
P D _IOR# <20>

P D _DACK#

P D _DACK# <20>

P D I AG#
P D_A2
P D_CS#3

2

1
R 244

2

100K_0402_5% +5VS
+5VS

PD_CS#3 <20>

+5VS

1

1

C 347 0 . 1 U_0402_16V4Z

2

1
C 344
1 U_ 0603_10V4Z

2

C 336
1 0 U_0805_10V4Z

O C TEK_CDR-50DY1G
ME@

1

R 231
470_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
HDD & CDROM

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

23

of

47

A

B

C A R D _ S 1 _ A [0 ..2 5 ]

C

+ S 1 _ V CC

+ 3VS

C431
0 .1 U _0402_16V4Z

C A R D _ S 1 _ D [ 0 ..1 5 ] < 2 5 >

P C I _ A D [ 0 . .3 1 ]

P C I _ A D [ 0 . .3 1 ] < 1 9 ,2 6 ,2 7 ,3 2 >

C400
4 . 7 U_ 0 8 0 5 _ 1 0 V 4 Z
CB@

Power on RESET#
Reset# Here

1

1

1

1

1

C456
CB@
C 4 02
C 4 36
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z 0 . 1 U _ 0 4 0 2 _ 1 6 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
2 C B@
2 CB @
2
+ 3VS

2

1

2

>1ms

P C I _ A D3 1
P C I _ A D3 0
P C I _ A D2 9
P C I _ A D2 8
P C I _ A D2 7
P C I _ A D2 6
P C I _ A D2 5
P C I _ A D2 4
P C I _ A D2 3
P C I _ A D2 2
P C I _ A D2 1
P C I _ A D2 0
P C I _ A D1 9
P C I _ A D1 8
P C I _ A D1 7
P C I _ A D1 6
P C I _ A D1 5
P C I _ A D1 4
P C I _ A D1 3
P C I _ A D1 2
P C I _ A D1 1
P C I _ A D1 0
P C I _ A D9
P C I _ A D8
P C I _ A D7
P C I _ A D6
P C I _ A D5
P C I _ A D4
P C I _ A D3
P C I _ A D2
P C I _ A D1
P C I _ A D0

PCIRST#

3

Entry S3
>1ms

SUSPEND#

PCIRST#
< 1 9 ,2 6 ,2 7 ,3 2 >
< 1 9 ,2 6 ,2 7 ,3 2 >
< 1 9 ,2 6 ,2 7 ,3 2 >
< 1 9 ,2 6 ,2 7 ,3 2 >

P C I_ C BE#3
P C I_ C BE#2
P C I_ C BE#1
P C I_ C BE#0

P C I_ C BE#3
P C I_ C BE#2
P C I_ C BE#1
P C I_ C BE#0

SUSPEND# will gate the PCIRST# or
GRST#, so need S3 wake up function,
SUSPEND# must be LOW ahead the PCIRST# < 1 9 , 2 1 ,2 5 ,2 6 ,2 7 ,3 2 ,3 3 > P C I _ RS T #
< 1 9 ,2 6 ,2 7 ,3 2 > P C I _ F R A ME #
about 1ms.
< 1 9 ,2 6 ,2 7 > P C I _ I R D Y #
2

+3 V S

C L K _ P C I _ P CM

20
28
29
31
32
33
34
35
36
1
2
21

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

63
VCCI

138
122
102
86
50
30
14
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

126
90
VCCSK0
VCCSK1

44
18
VCCP0
VCCP1

72
71

PQFP 144
22.2 X 22.2 X 1.60

C/BE3#
C/BE2#
C/BE1#
C/BE0#

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

RST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
REQ#
GNT#
PCLK

CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCLK/A16

CB@
P C I _ A D2 0

1

2

R408

1
C429
10P_0402_25V8K @

59
70

<3 3 > C B _ P ME #

2
D 17
@ R B 7 5 1 V _ S OD3 2 3

<1 9 > P C I _ P I R QA #

Note: MF0 -- MF6 must
refer the data sheet for
< 2 1 ,2 6 ,3 2 ,3 3 >
design.

2

P C I _ P C M _ ID 13
2
100_0402_5%
P C I _ P I R QA #
60

RI_OUT#/PME#
SUSPEND#

CSTSCHG/BVD1
CCLKRUN#/WP

61
64
65
67
68
69

S IRQ

< 2 1 ,2 6 ,2 7 ,3 3 > P C I _ C L K R U N #

66

CBLOCK#/A19

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

CINT#/READY

VCC/GRST#

SPKOUT
CAUDIO/BVD2

6
22
42
58
78
94
114
130

< 1 9 , 2 1 ,2 5 ,2 6 ,2 7 ,3 2 ,3 3 > P C I _ RS T #

IDSEL

RSVD/D14
RSVD/A18
RSVD/D2

1

84
100
143

< 1 8 , 2 6 ,3 3 ,3 4 ,3 5 ,3 7 ,4 3 ,4 4 > S U S P #

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

R379
3 3_0402_5% @

CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1#

C B@

2

1
C B@

2

C B@

2

C 4 45
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z

C454
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z

1

2

C 4 04
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z

1
CB@

CB@

2

2

C421
0 .1 U _0402_16V4Z

4

ENE CB1410 just have one vcc plane internal,
if want S3 wake-up function(PME#),then at S3
status must keep all Vcc +3V. That is different
with TI 1410 and O2-Micro 6912, just keep the
VCCI pin +3V, the other vcc can use +3VS.

CB@

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

C A R D _ S 1 _ D1 0
C A R D _ S 1 _ D9
C A R D _ S 1 _ D1
C A R D _ S 1 _ D8
C A R D _ S 1 _ D0
C A R D _ S 1_A0
C A R D _ S 1_A1
C A R D _ S 1_A2
C A R D _ S 1_A3
C A R D _ S 1_A4
C A R D _ S 1_A5
C A R D _ S 1_A6
C A R D _ S 1_A25
C A R D _ S 1_A7
C A R D _ S 1_A24
C A R D _ S 1_A17
C A R D _ S 1 _ I O W R#
C A R D _ S 1_A9
C A R D _ S 1 _ I O R D#
C A R D _ S 1_A11
C A R D _ S 1 _ OE #
C A R D _ S 1 _ CE 2 #
C A R D _ S 1_A10
C A R D _ S 1 _ D1 5
C A R D _ S 1 _ D7
C A R D _ S 1 _ D1 3
C A R D _ S 1 _ D6
C A R D _ S 1 _ D1 2
C A R D _ S 1 _ D5
C A R D _ S 1 _ D1 1
C A R D _ S 1 _ D4
C A R D _ S 1 _ D3

125
112
99
88

C A R D _ S 1 _ R E G#
C A R D _ S 1_A12
C A R D _ S 1_A8
C A R D _ S 1 _ CE 1 #

119
111
110
109
107
105
104
133
101
123
106
108

C A R D _ S 1 _ RS T
C A R D _ S 1_A23
C A R D _ S 1_A15
C A R D _ S 1_A22
C A R D _ S 1_A21
C A R D _ S 1_A20
C A R D _ S 1_A14
C A R D _ S 1 _ W A IT #
C A R D _ S 1_A13
C A R D _ S 1 _ I N P A CK #
CA RD_ S 1 _ WE#
C A R D _ A 1 6 _ CL K

3

C A R D _ S 1 _ I O W R# < 2 5 >
C A R D _ S 1 _ I O R D# < 2 5 >
C A R D _ S 1 _ OE # <2 5 >
C A R D _ S 1 _ CE 2 # < 2 5 >

C A R D _ S 1 _ R E G# < 2 5 >

C A R D _ S 1 _ CE 1 # < 2 5 >
C A R D _ S 1 _ RS T <2 5 >

2

C A R D _ S 1 _ W A IT # < 2 5 >

1

C A R D _ S 1 _ I N P A CK # < 2 5 >
C A R D _ S 1 _ WE# < 25>
C A R D _ S 1_A16
2
3 3_0402_5%
CB@

R420

1

C L K _ P C I _ P CM

12
27
37
48

P C I _ RS T #

< 1 9 ,2 6 ,2 7 ,3 2 > P C I _ T R D Y #
< 1 9 ,2 6 ,2 7 > P C I _ D E V S E L #
< 1 9 ,2 6 ,2 7 > P C I _ S T OP #
< 1 9 ,2 6 ,2 7 > P C I _ P E R R#
< 1 9 ,2 6 ,2 7 > P C I _ S E R R#
< 1 9 ,2 6 ,2 7 > P C I _ P A R
1
2
<1 9 > P C I _ R E Q2 #
R 3 1 8 10K_0402_5%
<1 9 > P C I _ G NT 2 #
C B@
<1 5 > C L K _ P C I _ P CM

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

VPPD1
VPPD0

74
73
VCCD1#
VCCD0#

U 28

C438
0 .1 U _0402_16V4Z

1

2

C403
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z

CLK

1
CB@

C455
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z

< 2 5 > V P P D0
< 2 5 > V P P D1
< 25> V C C D 0 #
< 25> V C C D 1 #

VCC

1
C B@

+3 V S

4

SUSPEND#

E

+3 V S

C A R D _ S 1 _ A [0 ..2 5 ] < 2 5 >

C A R D _ S 1 _ D [ 0 ..1 5 ]

D

135
136

C A R D _ S 1 _ B V D1
CA RD_ S 1 _ WP

103

C A R D _ S 1_A19

132

C A RD_S 1_RDY #

62
134

P C M_ S P K #
C A R D _ S 1 _ B V D2

137
75
117
131

C A R D _ S 1 _ C D 2#
C A R D _ S 1 _ C D 1#
C A R D _ S 1_VS2
C A R D _ S 1_VS1

C A R D _ S 1 _ B V D1 < 2 5 >
C A R D _ S 1 _ W P <2 5 >

C A R D _ S 1 _ R D Y # < 25>
P C M_ S P K # <2 9 >
C A R D _ S 1 _ B V D2 < 2 5 >
C A R D _ S 1 _ C D 2# < 25>
C A R D _ S 1 _ C D 1# < 25>
C A R D _ S 1 _ V S 2 <2 5 >
C A R D _ S 1 _ V S 1 <2 5 >

C B 1 4 1 0 _ L QF P 1 4 4
C B@
C A R D _ S 1 _ D2
C A R D _ S 1_A18
C A R D _ S 1 _ D1 4

1

Compal Secret Data

Security Classification
2005/10/06

Issued Date
PROPRIETARY NOTE

1

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T itle

A

B

C

D

CB ENE1410(One Solt)

S ize
D o c u m e n t N u mb e r
C u s to m

R ev
0 .1

HGT30/31 LA3061

Da te :

PDF created with pdfFactory Pro trial version www.pdffactory.com

Compal Electronics, Inc.

星期四,

G月 23, 2006

S heet
E

24

of

47

A

B

C

D

E

PC MC I A Power Controller
C A R D _ S 1 _ A [0 ..2 5 ]
C A R D _ S 1 _ D [ 0 ..1 5 ]

< 2 4 > C A R D _ S 1 _ A [0 ..2 5 ]
< 2 4 > C A R D _ S 1 _ D [ 0 ..1 5 ]

J P 11

+ S 1 _ V CC

1

U5

VCC
VCC
VCC

1

9

12V

13
12
11

2

C210
0 .1 U _0402_16V4Z
CB @
+S 1 _ V P P

< 2 4 > C A R D _ S 1 _ CE 1 #
< 2 4 > C A R D _ S 1 _ OE #

+5 V S
+ 5VS

1

2

1
VPP

1

C 1 97
C193
1 0 U _ 1 2 0 6 _ 1 0 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
C B@
2
C B@

5
6

VCCD0
VCCD1
VPPD0
VPPD1

C B@

SHDN

GND
7

3.3V
3.3V

CB @

16

2

3
4

1

C209
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z

2

+ 3VS

C198
C194
1 0 U _ 1 2 0 6 _ 1 0 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
2
C B@

CB @

5V
5V

+3 V S

1

10

OC

1
2
15
14

V CCD0#
V CCD1#
V P P D0
V P P D1

< 24> C A R D _ S 1 _WE#
< 24> C A R D _ S 1 _ R D Y #
+ S 1 _ V CC
+S 1 _ V P P

<2 4 >
<2 4 >
<2 4 >
<2 4 >

8

C P -2 2 1 1 _ S S OP 1 6

P C I _ RS T #

P C I _ RS T # < 1 9 , 2 1 ,2 4 ,2 6 ,2 7 ,3 2 ,3 3 >
<2 4 > C A R D _ S 1 _ W P

C A R D _ S 1 _ D3
C A R D _ S 1 _ D4
C A R D _ S 1 _ D5
C A R D _ S 1 _ D6
C A R D _ S 1 _ D7
C A R D _ S 1 _ CE 1 #
C A R D _ S 1_A10
C A R D _ S 1 _ OE #
C A R D _ S 1_A11
C A R D _ S 1_A9
C A R D _ S 1_A8
C A R D _ S 1_A13
C A R D _ S 1_A14
CA RD_ S 1 _ WE#
C A RD_S 1_RDY #

C A R D _ S 1_A16
C A R D _ S 1_A15
C A R D _ S 1_A12
C A R D _ S 1_A7
C A R D _ S 1_A6
C A R D _ S 1_A5
C A R D _ S 1_A4
C A R D _ S 1_A3
C A R D _ S 1_A2
C A R D _ S 1_A1
C A R D _ S 1_A0
C A R D _ S 1 _ D0
C A R D _ S 1 _ D1
C A R D _ S 1 _ D2
CA RD_ S 1 _ WP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

+S 1 _ V P P

2

1

2

C241
CB@

1

2

C 2 15
C B@

1

2

C 2 43
1 U _0805_25V4Z
C B@

69
70
71
72
73
74
75
76

0 . 0 1 U_ 0 4 0 2 _ 2 5 V 4 Z 4 . 7 U_ 0 8 0 5 _ 1 0 V 4 Z

GND
GND
D3
CD1#
D4
D11
D5
D12
D6
D13
D7
D14
CE1#
D15
A10
CE2#
OE#
VS1#
A11
IORD#
A9
IOWR#
A8
A17
A13
A18
A14
A19
WE#
A20
IREQ#
A21
VCC
VCC
VPP1
VPP2
A16
A22
A15
A23
A12
A24
A7
A25
A6
VS2#
A5
RESET
A4
WAIT#
A3
INPACK#
A2
REG#
A1
SPKR#
A0
STSCHG#
D0
D8
D1
D9
D2
D10
IOIS16#
CD2#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
HOLE1
HOLE2
HOLE3
HOLE4

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

C A R D _ S 1 _ C D 1#
C A R D _ S 1 _ D1 1
C A R D _ S 1 _ D1 2
C A R D _ S 1 _ D1 3
C A R D _ S 1 _ D1 4
C A R D _ S 1 _ D1 5
C A R D _ S 1 _ CE 2 #
C A R D _ S 1_VS1
C A R D _ S 1 _ I O R D#
C A R D _ S 1 _ I O W R#
C A R D _ S 1_A17
C A R D _ S 1_A18
C A R D _ S 1_A19
C A R D _ S 1_A20
C A R D _ S 1_A21

C A R D _ S 1 _ C D 1 # <2 4 >

1

C A R D _ S 1 _ CE 2 # <2 4 >
C A R D _ S 1_VS1 < 24>
C A R D _ S 1 _ I O R D # <2 4 >
C A R D _ S 1 _ I O W R # <2 4 >

+ S 1 _ V CC
+S 1 _ V P P

C A R D _ S 1_A22
C A R D _ S 1_A23
C A R D _ S 1_A24
C A R D _ S 1_A25
C A R D _ S 1_VS2
C A R D _ S 1 _ RS T
C A R D _ S 1 _ W A IT #
C A R D _ S 1 _ I N P A CK #
C A R D _ S 1 _ R E G#
C A R D _ S 1 _ B V D2
C A R D _ S 1 _ B V D1
C A R D _ S 1 _ D8
C A R D _ S 1 _ D9
C A R D _ S 1 _ D1 0
C A R D _ S 1 _ C D 2#

C A R D _ S 1_VS2 < 24>
C A R D _ S 1 _ RS T < 2 4 >
C A R D _ S 1 _ W A IT # <2 4 >
C A R D _ S 1 _ I N P A CK # < 2 4 >
C A R D _ S 1 _ R E G# <2 4 >
C A R D _ S 1 _ B V D2 <2 4 >
C A R D _ S 1 _ B V D1 <2 4 >

C A R D _ S 1 _ C D 2 # <2 4 >
2

77
78
79
80
81
82
83
84

+ S 1 _ V CC

1

1

C239
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
CB@ 2

2

87
88
89
90

1
C216

2

C238
0 . 0 1 U_ 0 4 0 2 _ 2 5 V 4 Z
C B@

1 0 U_ 1 2 0 6 _ 1 0 V 4 Z
CB @

F O X _ W Z 2 1 1 3 1 -G2 -P 4 _ L T
ME@

3

3

4

4

Compal Secret Data

Security Classification
2005/10/06

Issued Date

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T itle

A

B

C

D

CardBus Socket

S ize
D o c u m e n t N u mb e r
C u s to m

R ev
0 .1

HGT30/31 LA3061

Da te :

PDF created with pdfFactory Pro trial version www.pdffactory.com

Compal Electronics, Inc.

星期四,

G月 23, 2006

S heet
E

25

of

47

4

3

2

1

+3VS

10K_0402_5%

UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

HWSPND#
TEST

2

R463

0_0402_5%

111
107
103
102
99

@

B

97

AGND
AGND
AGND
AGND
AGND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC

SDWP#_XDRB#
S D PWR0_MSPWR_XDPWR

T P_MSEXTCK
S DCMD_MSBS
SDCLK_MSCLK
SDDAT A0_MSDATA0
SDDAT A1_MSDATA1
SDDAT A2_MSDATA2
SDDAT A3_MSDATA3

MS EN
XD EN

94
95

R5C832XI
R5C832XO

1

C522

10U_0805_6.3V6M

C489

0.01U_0402_25V4Z

C507

0.1U_0402_16V4Z

C515

0.01U_0402_25V4Z

C516

0.47U_0603_16V4Z

C491

Layout Note: Place close to R5C832
and Shield GND for SDCLK_MSCLK

0.01U_0402_25V4Z

S IRQ
<21,24,32,33>
P AD
T49
P AD
T48

2
C461

MDIO06

SDLED#

MMCLED#

MSLED#

MDIO08

SDCCMD

MMCCMD

MSBS

XDWE#

MDIO09

SDCCLK

MMCCLK

MSCCLK

XDRE#

MDIO10

SDCDAT0

MMCDAT

MSCDAT0

XDCDAT0

MDIO11

SDCDAT1

MSCDAT1

XDCDAT1

MDIO12

SDCDAT2

MSCDAT2

XDCDAT2

MDIO13

SDCDAT3

MSCDAT3

XDCDAT3

0.01U_0402_25V4Z 1

+ V CC_4IN1

XDCDAT4

MDIO15

XDCDAT5

MDIO16

XDCDAT6

MDIO17

XDCDAT7

MDIO18

XDCLE

MDIO19

XDALE
C

UDIO3

UDIO4

MSEN

XDEN

Pull-up

Pull-up

Pull-up

Pull-up

Function
Enable
SD,XD,MS,MMC Card

Layout Note: Place close to R5C832
and Shield GND for SD_CLK

MS EN
UD I O3
UD I O4
UD I O5

R474
R468
R475
R473

XD EN

R471 1

1
1
1
1

2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%

2 10K_0402_5%

X2
24.576MHz_16P_1BG24576CKIA

2

R5C832XO

1

1

2

2

Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK

B

Solve MS Duo Adaptor short problem

R705 1

2 0_0402_5%

TPBTPB+
TPATPA+

GND
GND
GND
GND

2

VIN
VOUT
VIN/CE VOUT

1
5

GND

1

R706 1

RT 9701CB_SOT25

SDDAT A2_MSDATA2

1

2

SDDAT A1

SDDAT A1 <38>

2 0_0402_5% @
Q35
2N7002_SOT23
SDDAT A2

1

3

+5VS

1

@

Q33
3 2N7002_SOT23

+ V CC_4IN1

U35

3
4

2

SDDAT A2 <38>

2

R456

10K_0402_5%

SDCD#_XDCD0#

D

S

2
G

@ Q34
2N7002_SOT23

5
6
7
8

A

C462
0.33U_0603_16V4Z

SUYIN_020115F B004S512ZL
ME@

C459
0.01U_0402_25V4Z

1

MSEXTCK

16P_0603_50V8J

1

1

XDLED#

R5C832XI

2

1

+3VS

2

D

XDWP#

MDIO14

SDDAT A1_MSDATA1

2

XDPWR

C481

1

16P_0603_50V8J

C473

4
13
22
28
54
62
63
68
118
122

C494
0.1U_0402_16V4Z

2
1
2
1

R438
56.2_0603_1%

2
1

R437
56.2_0603_1%

2

SDPWR1

Function set pin define

2 C471

JP13

Compal Electronics, Inc.

Layout Note: Shield GND for
IEEE1394_TPA and TPB

T itle
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A ND TRA DE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DE P A RTME NT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IEEE1394_T PBIAS0

5

2

1

SDDAT A3_MSDATA3 <38>

S I RQ
T P_UDIO1
T P_UDIO2
UD I O3
UD I O4
UD I O5

1
2
3
4

C493
1U_0603_10V4Z

2

1

S DCMD_MSBS <38>
SDCLK_MSCLK <38>
SDDAT A0_MSDATA0 <38>

96
101
100

CBS_GRST#

2

2

1

MDIO05

XDR/B#
MSWR

+3VS

58
55

72
60
56
65
59
57

XDCD1#

MMCPWR

40mil

IEEE1394_T PBN0
IEEE1394_TPBP0
IEEE1394_T PAN0
IEEE1394_TPAP0

1

C460

S DWP#_XDRB# <38>

1

SDPWR0

2

1
2

2

R421
5.1K_0603_1%

C453
270P_0402_50V7K

1
S DCD#_XDCD0# <38>
MSCD#_XDCD1 <38>

C467
1000P_0402_50V7K

SDCD#_XDCD0#
MSCD#_XDCD1

MDIO04

MDIO07

2

BLM21A601SPT_0805

R440
56.2_0603_1%

2
1

R439
56.2_0603_1%

1
2

2

1 @

R462
100K_0402_5%

1

C463
R444
4.7P_0402_50V8C10_0402_5%

2

2

C466
1000P_0402_50V7K

80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83

1

+3VS

C469
0.1U_0402_16V4Z

105
104

IEEE1394_TPBP0
IEEE1394_T PBN0

Z3008
A

2

L18
C470
0.1U_0402_16V4Z

IEEE1394_TPAP0
IEEE1394_T PAN0

S D PWR0_MSPWR_XDPWR

+3VS

2

0.01U_0402_25V4Z 10U_0805_6.3V6M

CLK_PCI_1394

@

2

C465
22U_0805_6.3V6M

109
108

Layout Note: Place close to R5C832

2

2

2

+ 3V_PHY

R5C832_T QFP128~D

1

0.47U_0603_16V4Z

IEEE1394_T PBIAS0

C505

2

0.01U_0402_25V4Z

C464

113

2

0.01U_0402_25V4Z

+ 3 V_PHY

2

1

1

D

69
66

INTA#
INTB#

MSCD#

S

FIL0
REXT
VREF

XD Card
PIN Name
XDCD0#

G

XI
XO

C486

98
106
110
112

2

1

1

1

2

R464

2

1

MSEN
XDEN
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#

+3VS

1

1

1

S

+3VS

<18,24,33,34,35,37,43,44> S USP#

REQ#
GNT#

R5_PME#

115
116

1

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#

67
86

1

1

D

<33>
R5_PME#
<19> P C I_PIRQG#
<19> P C I_ PIRQH#

C/BE3#
C/BE2#
C/BE1#
C/BE0#

16
34
64
114
120

SDWP#

1

@

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

MS Card
PIN Name

XDCE#

MDIO03

3

2 0_0402_5%

TPBP0
TPBN0

0.01U_0402_25V4Z 10U_0805_6.3V6M

61

2

R435 1

TPAP0
TPAN0

MMC Card
PIN Name
MMCCD#

MDIO02

1

R436 1
<21,24,27,33> P C I_ CLKRUN#

121
119
71
117
70

CBS_GRST#
2 10K_0402_5%

TPBIAS0

SD Card
PIN Name
SDCD#

MDIO01

+3VS

1

<15> CLK_PCI_1394
<19,21,24,25,27,32,33> PCI_RST #

124
123

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

C506

2

2

PCI_REQ0#
PCI_GNT 0#

<19> PCI_REQ0#
<19> PCI_GNT 0#

VCC_3V
VCC_MD3V

C468

2

R483
150K_0402_5%

100_0402_5%
<19,24,27> P C I_PERR#
<19,24,27> P C I_SERR#

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

1

C517
1U_0603_10V4Z

2

33
23
25
24
29
26
8
30
31

VCC_RIN

1

2

R455

P C I_PAR
P CI_F RAME#
P C I_T RDY#
P C I_ I RDY#
PCI_ST OP#
PCI_DEVSEL#
C BS_IDSEL
P C I_PERR#
P C I_SERR#

P C I_PAR
PCI_F RAME#
P CI_T RDY#
P C I_ IRDY#
PCI_ST OP#
PCI_DEVSEL#

R5C832

10
20
27
32
41
128

R441
10K_0402_5%

1

7
21
35
45

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

1

P CI_AD22

P CI_CBE#3
P CI_CBE#2
P CI_CBE#1
P CI_CBE#0

P CI_CBE#3
P CI_CBE#2
P CI_CBE#1
P CI_CBE#0

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C437
0.1U_0402_16V4Z

C

125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53

C521
10U_1206_6.3V6M

P CI_AD31
P CI_AD30
P CI_AD29
P CI_AD28
P CI_AD27
P CI_AD26
P CI_AD25
P CI_AD24
P CI_AD23
P CI_AD22
P CI_AD21
P CI_AD20
P CI_AD19
P CI_AD18
P CI_AD17
P CI_AD16
P CI_AD15
P CI_AD14
P CI_AD13
P CI_AD12
P CI_AD11
P CI_AD10
P CI_AD9
P CI_AD8
P CI_AD7
P CI_AD6
P CI_AD5
P CI_AD4
P CI_AD3
P CI_AD2
P CI_AD1
P CI_AD0

D

<19,24,27>
<19,24,27,32>
<19,24,27,32>
<19,24,27>
<19,24,27>
<19,24,27>

MDIO
PIN Name
MDIO00

U34

<19,24,27,32> PCI_AD[0..31]

<19,24,27,32>
<19,24,27,32>
<19,24,27,32>
<19,24,27,32>

SD,MMC,MS,XD muti-function pin define

G

5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

1394+3 in 1 Card
Size

Document Number

Date:

星期四 , 二月 23, 2006

Rev
0.1

HGT30/31 LA3061
Sheet
1

26

of

47

5

4

3

2

1

+ 3VALW
+ 3 V_LAN
+ 3 V_LAN
C 385
1 U_ 0603_10V4Z

1

2

+3VS
GIGA@ 2SB1188_SC62

1

R 403

3
CTRL25

2
CTRL12

R 499 0_0402_5%

+ 1 .2V_LAN

1

@

1

Q21

2

+ 2 .5V_LAN
Q27
2SB1188_SC62

5.6K_0603_1%
100@

1

+
C433
2 2 U_A_4VM

1

2

C 393

2

2

R 400 1

2 3.6K_0402_5%

U2 4

P C I_CBE#0
P C I_CBE#1
P C I_CBE#2
P C I_CBE#3

L AN_ IDSEL46
100_0402_5%

1

2

R 302
<19,24,26> P C I_PAR
<19,24,26,32> P C I_FRAME#
<19,24,26> P C I_ IR DY#
<19,24,26,32> P C I_ TRDY#
<19,24,26> P CI_DEVSEL#
<19,24,26> PCI_STOP#

76
61
63
67
68
69

<19,24,26> P C I_PERR#
<19,24,26> P C I_SERR#

70
75
30
29

<19> P CI_REQ3#
<19> P C I_GNT3#
B

25

<19> P C I_PIRQF#
<33> L AN_PME#

31

<19,21,24,25,26,32,33> P CI_RST#

27
C L K _ PCI_LAN 28

<15> C L K _PCI_LAN
<21,24,26,33> P C I_ C LKRUN#

65

4
17
128
21
38
51
66
81
91
101
119

1

C L K _ PCI_LAN

R 316
@ 10_0402_5%

LED0
LED1
LED2
NC/LED3
TXD+/MDI0+
TXD-/MDI0RXIN+/MDI1+
RXIN-/MDI1NC/MDI2+
NC/MDI2NC/MDI3+
NC/MDI3X1
X2
LWAKE
ISOLATE#
RTSET
NC/SMBCLK
NC/SMBDATA
NC/M66EN
NC/AVDDH
AVDDH

C/BE#0
C/BE#1
C/BE#2
C/BE#3

NC/HSDAC+
NC/HG
NC/LG2
VDD12A

108
109
111
106

L A N_EEDO
L AN_ EEDI
L A N_EECLK
L A N_EECS

4
3
2
1

1
2
5
6

TXD+/MDI0+
TXD-/MDI0R XI N+/MDI1+
R XIN -/MDI1-

14
15
18
19

NC / M DI2+
NC / M DI2NC / M DI3+
NC / M DI3-

121
122
105
23
127
72
74

PERR#
SERR#
REQ#
GNT#

NC/VSS
NC/VSS
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

2

35
52
80
100

C 397
@ 10P_0402_25V8K

A

1
C 410

0 . 1 U_0402_16V4Z
+ 3VALW

2

Y3
L AN_X1

1

2

1

L AN_X2

2

2 5 MHZ_20P_1BG25000CK1A 1
C 442
2 2P_0402_50V8J

+ 2 . 5V_LAN
C 443
22P_0402_50V8J

2

L AN_X1
L AN_X2

@
R319
R317
R403

ISOLATE#
RTSET

2 1K_0402_5%
2 15K_0402_5%
2 2.49K_0603_1%

1
1
1

+3VS

0 . 0 1U_0402_25V4Z
GIGA@

GIGA@

5.6K for 8100CL
2.49K for 8110S(B)

10
120
11
123
124
126

2
R 354

0 . 0 1U_0402_25V4Z
GIGA@

1
1

9
13

2

CTRL25
PME#
CTRL12
RST#
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

CLK
CLKRUN#

GND/VSS
GND/VSS
GND/VSS

R XI N+/MDI1+
R XIN -/MDI1-

9
8
7

NC / M DI2+
NC / M DI2-

6
5
4

NC / M DI3+
NC / M DI3-

3
2
1

1 C 418

2

0 . 0 1U_0402_25V4Z
GIGA@

1 C 408

2
D VD D_A

12
11
10

1 C 396

2
88
GIGA@ 0 . 1 U_0402_16V4Z
+ AV DDH
1 R 418
2 GIGA@ 0_0805_5% + 3 V_LAN
1
1
C 441
C 420
GIGA@ 0 . 1 U_0402_16V4Z
1 0_0402_5%
2
2
GIGA@

U2 3
R 734
0_0402_5%
TXD+/MDI0+
TXD-/MDI0-

1 C 398

2

0 . 0 1U_0402_25V4Z
GIGA@

+ 1 .2V_LAN

R 301
GIGA@ 0_0402_5%

TD4TD4+
TCT4

MX4MX4+
MCT4

TD3TD3+
TCT3

MX3MX3+
MCT3

TD2TD2+
TCT2

MX2MX2+
MCT2

TD1TD1+
TCT1

MX1MX1+
MCT1

MDO0+
MDO0MCT0

13
14
15

MDO0+
MDO0-

AVDDL
AVDDL
AVDDL
AVDDL

RTL8110SCL_LQFP128
GIGA@

NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12
NC

R J 45_PR <38>

16
17
18

MDO1+
MDO1MCT1

19
20
21

MDO2+
MDO2-

22
23
24

MDO3+
MDO3-

MDO1+
MDO1-

<38>
<38>

1 R 325

2

75_0402_5%
MDO2+
MDO2-

<38>
<38>

1 R 320

2

GIGA@ 75_0402_5%
MDO3+
MDO3-

<38>
<38>

1 R 322

2

GIGA@ 75_0402_5%

use 24ST1041A-4

C 378
GIGA@ 0 . 1 U_0402_16V4Z

use 24ST1041A-4
U2 2

22
48
62
73
112
118

TXD+/MDI0+
TXD-/MDI0-

1
8

CTRL25

125

CTRL12

26
41
56
71
84
94
107

0 . 1 U_0402_16V4Z
R XI N+/MDI1+
C 401
R XIN -/MDI1-

2

8
7
6
3
2
1

TDTD+
CT

TXTX+
CT

CT
RDRD+

CT
RXRX+

9
10
11

MDO0+
MDO0MCT0

14
15
16

MCT1
MDO1+
MDO1-

NS0013_16P
100@

1

1

C 394
0 . 1 U_0402_16V4Z

2

C 381
0 . 1 U_0402_16V4Z

2

1
C 406
0 . 1 U_0402_16V4Z

2

2

1

NC / M DI3-

1

@

1
C 440
0 . 1 U_0402_16V4Z

R 324
@ 49.9_0402_1%
NC / M DI3+ 2

C 423
0 . 1 U_0402_16V4Z

2

AVD DL

1

1

R 422 1
1 00@

1

C 409
0 . 1 U_0402_16V4Z

C 425
0 . 1 U_0402_16V4Z

2

C 428
0 . 1 U_0402_16V4Z

1

+ DVDD

2

1

1

C 405
0 . 1 U_0402_16V4Z

24
45
64
110
116

C 427
0 . 1 U_0402_16V4Z

2

+ 3 V_LAN

C 382
0 . 1 U_0402_16V4Z

1

NC / M DI2-

1

2

2

C 380

C 383

2

2

GIGA@ C 439

2

C 444

GIGA@ 0 . 1 U_0402_16V4Z

0 . 1 U_0402_16V4Z
V _12P
R 350 1
100@
1
C 414
R 351 1
GIGA@
0 . 1 U_0402_16V4Z

1

1

1

R 329
49.9_0402_1%

R 380
1 00@ 49.9_0402_1%
TXD+/MDI0+ 2

R 303 1

2

+ 1 . 2V_LAN

R 375
100@ 49.9_0402_1%

+ 2 . 5V_LAN

R 369
100@ 49.9_0402_1%
R XI N+/MDI1+ 2

2

1

0 . 0 1U_0402_25V4Z
@

C 430

1

2
TXD-/MDI0-

1

1
0 . 0 1U_0402_25V4Z
100@

0_0805_5%
R 306
1 00@

1

2

R XIN -/MDI1-

C 407

GIGA@

1

C 415

2
2

1

0 . 0 1U_0402_25V4Z
@

R 333
@ 49.9_0402_1%
NC / M DI2+ 2

+ 2 . 5V_LAN

+ 1 .2V_LAN
GIGA@

R 321
49.9_0402_1%

2
GIGA@ 0_0805_5%

2

2

R 376 1

1
C 395
0 . 1 U_0402_16V4Z

2

0_0805_5%
GIGA@ 0_0805_5%

+ D VDD

32
54
78
99

2

B

C 412

2

+ 3 V_LAN

1

3
7
20
16

12

R J 45_PR

2

2
VDD12
VDD12
VDD12
VDD12

1 R 348

75_0402_5%

@

GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST

C

<38>
<38>

2

GIGA@ 0.5u_24HST1041A-2

1 00@

INTA#

GND
GND
GND
GND

5
6
7
8

GND
NC
NC
VCC

AT93C46-10SU-2.7_SO8

IDSEL
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

DO
DI
SK
CS

117
115
114
113

2

1

2

D

C379
GIGA@ 0 . 1 U_0402_16V4Z

+ 3 V_LAN

U3 1

EEDO
AUX/EEDI
EESK
EECS

Power

P C I _AD17

92
77
60
44

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

LAN I/F

C

104
103
102
98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33

PCI I/F

P C I _AD0
P C I _AD1
P C I _AD2
P C I _AD3
P C I _AD4
P C I _AD5
P C I _AD6
P C I _AD7
P C I _AD8
P C I _AD9
P C I _AD10
P C I _AD11
P C I _AD12
P C I _AD13
P C I _AD14
P C I _AD15
P C I _AD16
P C I _AD17
P C I _AD18
P C I _AD19
P C I _AD20
P C I _AD21
P C I _AD22
P C I _AD23
P C I _AD24
P C I _AD25
P C I _AD26
P C I _AD27
P C I _AD28
P C I _AD29
P C I _AD30
P C I _AD31
P CI_CBE#0
P CI_CBE#1
P CI_CBE#2
P CI_CBE#3

2

0 . 1 U_0402_16V4Z

P C I_ AD[0..31]

<19,24,26,32> P C I_ AD[0..31]

<19,24,26,32>
<19,24,26,32>
<19,24,26,32>
<19,24,26,32>

1

GIGA@ +
C 374
2 2 U_A_4VM

1

D

2

1 00@

2

8100CL

1

U2 4

1

3

R 498 0_0402_5%

2

R 365
1 00@ 49.9_0402_1%

GIGA@ 0 . 1 U_0402_16V4Z

1

C 424

1

2
2

1

1
0 . 0 1U_0402_25V4Z
100@
A

0 . 1 U_0402_16V4Z

2
0_0402_5%

2

+ 2 .5V_LAN

0 . 1 U_0402_16V4Z

near LAN controller

+ AV DDH

0_0402_5%

2

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
LAN CONTROLLER

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

27

of

47

A

B

C

D

E

Mini-Express Card(Slot 1-WLAN)
<21,37> IC H_ PCIE_W AKE#

J P16

1 0_0402_5%
1 0_0402_5%

@

<15> C L KREQ_MCARD#

C L K _ PCIE_MCARD#
C L K _ PCIE_MCARD

<15> C L K _PCIE_MCARD#
<15> C L K _PCIE_MCARD

<21> P C IE_RXN2
<21> PCIE_RXP2

<21> P CIE_TXN2
<21> PCIE_TXP2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1

GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS

1

2
PLT_RST#

2

1

R 729 2
1
R 730
@
IC H _SMBCLK
IC H_ SMBDATA

W L_OFF# <33>
PLT_RST# <7,19,23,37>
+3VALW
0_0402_5% +3VS
0_0402_5%

+1.5VS

1

2

1

0.1U_0402_16V4Z

@

C498

1

R 480 2
R 479 2

0.1U_0402_16V4Z
C499

B T_AVTIVE
W L AN _AVTIVE

IC H_SMBCLK <15,21,37>
IC H_ SMBDATA <15,21,37>

W IRELESS_LED#

W IRELESS_LED# <37>

54

FOX_AS0B226-S56N-7F

+ 3VALW

2

MDC CONN.
C 495

1

2

2

1
R 495
J P17
10K_0402_1%
@
1

3
5
7
9
11

<20> IC H_ S DOUT_MDC
<20> IC H_ S YNC _ MDC
<20> IC H_ AC _ S DIN1
<20> IC H_RST_MDC#

A Z_ S YNC
AZ_ S D I N3

33_0402_5%

1

2
2

R 107

1

R 496
D 23

0_0402_5%

1
3
5
7
9
11

2
4
6
8
10
12

2
1 U_ 0 805_25V4Z

2
4
6
8
10
12

11/20

+3VALW

IC H_ BITCLK_MDC <20>

2
13
14
15
16
17
18
19
20

1
3

K ILL_MDC#

13
14
15
16
17
18
19
20

<21>

@ DAP202U_SOT323

ACES_88012-1207
ME@

1

+5VS

3

3

1 2

R 108
10K_0402_1%

0.1U_0402_16V4Z

2
Q23
DTC124EK_SC59

1

2

J P 38

<21>
<21>

US B20_N1
USB20_P1

1
2

2

US B20_N1
U SB20_P1
BTON_LED
B T_AVTIVE
W L AN _AVTIVE

2

3
4

1

0 . 1 U_0402_16V4Z

C701

1

1

+3VS_BT
C 164

3

AO3413_SOT23
G

BTONLED

Q22
D

BTONLED

+3VS

S

<37>

BT MODULE CONN

Q9
DTC124EK_SC59

2

BT_OFF#

3

<33>

BT_OFF

R 309
10K_0402_5%
@

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND1
GND2

MOLEX_53780-0870
ME@

Compal Secret Data

Security Classification
2005/10/06

Issued Date

4

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D

Title

Compal Electronics, Inc.
Mini Card / MDC CONN

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
E

28

of

47

A

B

C

D

E

1

+ VDDA

AC97 Codec

R 153
10K_0402_1%

2

28.7K for Module Design (VDDA = 4.702)

C477
@ 0 . 1 U_0402_16V4Z

R 159
10K_0402_1%

560_0402_5%
1 U_ 0 603_10V4Z

1

2MO NO _IN1
R 158 20K_0402_5%

C 487 1 U_ 0603_10V4Z
2
1 MO NO _IN

C 490

R167

2

C 482

1

B

R 449
150K_0603_1%

1

CNOISE

SD

3

GND

4.85V

1

1

2

C 478
1 0 U_0805_10V4Z

C 476

S I9182DH-AD_MSOP8

2
R 450
51K_0603_1%

E

3

560_0402_5%
1 U_ 0 603_10V4Z

ERROR

8

1

+ VDDA

6

DELAY SENSE or ADJ

7

2

(output = 250 mA)

40mil

5

VOUT

10K_0402_5%

Q12
2SC2411K_SC59

2

VIN

2

1 0 U_1206_10V4Z

2

4

0 . 1 U_0402_16V4Z

2

@ 0 . 1 U_0402_16V4Z

1 1

1 0 U_0805_10V4Z

2

1

U3 3

60mil

C

R 160
C472

1

1

C 253

2
1

L 22
1
2
KC FBM-L11-201209-221LMAT_0805
L 21
1
2
KC FBM-L11-201209-221LMAT_0805

2

2

<24> PCM_SPK#

+ 5VAMP

1 U_ 0603_10V4Z

R 168

1 1

2

1

1

2

BEEP#

2

<33>

+5VS

1

C 263
1

1

1C 255

2

2

C 254
R 161

1 1

2
560_0402_5%

1 U_ 0603_10V4Z

1

2

SB_SPKR

1

<21>

D4

R 171
RB751V_SOD323

2

2

@ 10K_0402_5%

+ VDDC
R176
C HB1608U301_0603

+ AVDD_AC97

1

2

1

L 11
C HB1608U301_0603
0 . 1 U_0402_16V4Z

AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
1

14
C 702
1 U_ 0603_10V4Z 15

R 166 1

2 40.2K_0402_1%

16

R 717 2

1 20K_0402_5%

17

2

23

1

+ AVDD_AC97

R 484

2.49K_0402_1%

24
<23> INT _CD_L

<23> INT _ CD_R
3

C D _ A GND

C D _ AGND

R 447 2
1
10K_0402_5%

2
2
2
2

1
1
1
1

20K_0402_5% C D _R_L
20K_0402_5%
20K_0402_5%
20K_0402_5% C D _R_R

C 261 1

2

1 U_ 0402_6.3V4Z

C D _RC_L

C 260 1

2

1 U_ 0402_6.3V4Z

C D _ RC_R

20

C D _ G NA C 479 1

2

1 U_ 0603_10V4Z

C D _ G NDA

19

M IC
1
C 480

2

C _ M IC

21

1

2

1

2

18

C D _ G NA
<30>

M IC

1

<23>

R 157
R 156
R 155
R 154

C 703

10K_0402_5%

@ C 262

1 U_ 0603_10V4Z

22
1 U_ 0603_10V4Z
MD C_RC_SPK

13

MO NO _IN

12

0 . 1 U_0402_16V4Z

2

R 448

@
+3VS
<20> IC H_ R S T_AUDIO#

R 458 1
R 459 1

2 5 0_LINE_OUTL
1
C 280
2 5 0_LINE_OUTR
1
C 281

2 47K_0402_5%
2 0_0402_5%

11
10

<20> IC H_ S YNC _ AUDIO

5

<20> IC H_ S D OUT_AUDIO

AUX_L

SURR_L

AUX_R

SURR_R

SENSE_A

MONO_OUT

SENSE_B

HP_OUT_L

LINE_IN_L

HP_OUT_R
BIT_CLK

CD_L
SDATA_IN
CD_R
XTL_IN

@

35

R 715 1

2 0_0402_5%

2 5 0_LINE_OUTL

36

R 716 1

2 0_0402_5%

2 5 0_LINE_OUTR

@

37
39
41

1

33_0402_5%

6
8

2 5 0 _SDIN

R 173 1

2 33_0402_5%

2 50_XTL_IN

2

2

48
+ AUD_VREF

1
1
R 152

2
0_0603_5%

C 275
1 U_ 0 603_10V4Z

2

10mil

4
7

<30>

HP _R

<30>

IC H_ B ITCLK_AUDIO <20>
IC H_ AC _ SDIN0 <20>

2 C LK_14M_CODEC
@ 0_0402_5%

C LK_14M_CODEC <15>

1

@ R 177 0_0402_5%

MIC2

GPIO

PHONE

VREFOUT_LI
VREFOUT_CL

3

2

R 169

1

10K_0402_5%

29
33

+ AVDD_AC97
C 274
2 2P_0402_50V8J
@

2

R 457
1 M_0402_5%
@

PC_BEEP
VREFOUT_MIC

28

+ AUD _VREF

RESET#
VREF
SYNC
SDATA_OUT

LFE_OUT
CENTER_OUT

27
0 . 1 U_0402_16V4Z

32
31

1

1

C 268

EAPD

LINE_OUT_L
LINE_OUT_R

SPDIF_OUT
AVSS1
AVSS2
AVSS3
AVSS4

DVSS1
DVSS2

43
45

C 492

1 U_ 0603_10V4Z

1

2

R 718 1
R 719 1

2 0_0402_5%
2 0_0402_5%

1

2

1 U_ 0603_10V4Z

C705

2 5 0_LINE_OUTL

1
C 508

2 5 0_LINE_OUTR

INT _ MIC

<30,37,38>

1 U_ 0603_10V4Z

C 509

26
40
44
30

2

1

1 U_ 0603_10V4Z
L IN E_OUTL
1 U_ 0603_10V4Z
L IN E_OUTR
2

2

L INE_OUTL <30>
L INE_OUTR <30>

AD1986A_CSP48

1

2

HP _L

3

MIC1

C704

47

IC H_ AC _ SDIN0

1
R 175

CD_GND_REF

L 701
C HB1608U301_0603

1

C 267 1
2 22P_0402_50V8J
@
IC H_ B IT CLK_AUDIO

2

R 174

2

<30,31,33> E APD

2
@ 1000P_0402_50V7K

0 . 1 U_0402_16V4Z

@

LINE_IN_R

2
@ 1000P_0402_50V7K

1

2

2

R 494
2.49K_0402_1%

1
<37> J AC K _ P LUG_MIC

1 0 U_0805_10V4Z

2

U1 1

0 . 1 U_0402_16V4Z + AVDD_AC97

<37> J AC K_PLUG

2

2

C 497

0 . 1 U_0402_16V4Z

2

@12/20

2

+3VS

1

2

2
C 282

C 503

2

2

1

9

2

1

1

C 264

1

DVDD2

1
C277
1 0 U_0805_10V4Z

DVDD1

2

25
38
42
46
34

1

+ VDDA

C 496

1

C 272
0 . 1 U_0402_16V4Z

C706 1

2

1 U_ 0603_10V4Z

C707 1

2

1 U_ 0603_10V4Z

L FE_OUT <31>

4

4

1
R 451

1
R 187

2
0_0603_5%

2
0_0603_5%

Compal Secret Data

Security Classification
2005/10/06

Issued Date

GND

GNDA

A

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D

Title

Compal Electronics, Inc.
AD1986 Codec

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
E

29

of

47

A

B

C

D

E

1

1

+ 5VAMP
+ 5VAMP

2

W=40mil
R 704
10K_0402_5%
C 504
0 . 1 U_0402_16V4Z

1 1

1

2

2

C 502
4 . 7 U_0805_10V4Z

1

R 708
1.5K_0402_1%

C 511

2

V OL_AMP

<29>

L INE_OUTL

<29> L INE_OUTR

7

V OLMAX
0_0402_5%

2

1

R 454

2

2
0 . 1 U_0402_16V4Z

U3 6

10
15

8
13

1

L IN E_OUTL

R 467
R 165 1

100K_0402_5%
2 10K_0402_5%

L IN

L IN E_OUTR

R 162 1

2 10K_0402_5%

R IN

6
3
4

1

2

MUTE
SHUTDOWN#
LOUT-

VOLUME
ROUTVOLMAX
LOUT+
SE/BTL#
ROUT+
LINRINBYPASS

M UTE

J P20
SPKL+O
SPKL-O
SPKR+O
SPKR-O

AMP_OFF# <31>

1
2
3
4

9

SPKL-

L 23

1

2 0_0603_5%

SPKL-O

16

SPKR-

L 24

1

2 0_0603_5%

SPKR-O

11

SPKL+

L 20

1

2 0_0603_5%

SPKL+O

C 163

14

SPKR+

L8

1

0_0603_5%

SPKR+O

@ 47P_0402_50V8J

2

1

1

1

C 162

@47P_0402_50V8J

2

2

C 168

1

ACES_85204-0400
ME@

C 167

@ 4 7P_0402_50V8J

2

2

@ 47P_0402_50V8J

GND
GND

5
12
+ AUD _VREF

APA2068KAI-TRL_SOP16
C 488
4 . 7 U_0805_10V4Z

2

1

2

VDD
VDD

1
2

1

(0.65V -> 10dB)

1

MIC IN
2

<33> E C_MUTE

3

R 445
2.2K_0402_5%

R 720
M UTE

<29>

1

M IC

2

1

2

FBM-11-160808-601-T_0603

EXT_MIC

EXT_MIC <37>

1

1

R 446
2.2K_0402_5%
L19

2

<29,31,33> E APD

@

2

D 20

D AN2 02U_SC70

2

1

INT _ MIC

INT _ MIC

<29,37,38>

0_0402_5%

1

2

R 485

1K_0402_5%

R 721
100K_0402_5%

C474
47P_0402_50V8J

1
C475
47P_0402_50V8J

2

2

2

+3VS

1

R 183
10K_0402_5%
3

3

AMP_OFF# <31>

1

AM P_OFF#

Q13

2

HEADPHONE

DTC124EK_SC59

<29>

HP _L

C 270
1 0 0 U_D2_6.3VM
R 181
SPKL+_C 1
1
2

<29>

HP _ R

1

+

2 0_0402_5% INTSPK_CL+
L10

PL

2

PL

<37>

PR

<37>

R 179

2

SPKR+_C 1

1 0 0 U_D2_6.3VM

2 0_0402_5%
R 180

1

+

C 269

1

FBM-11-160808-601-T_0603

I NTSPK_CR+ 1
2
L9 FBM-11-160808-601-T_0603
R178
C 279
47P_0402_50V8J
1K_0402_5%

1

2

2

C 278
47P_0402_50V8J

C

Q701
2SC2411K_SC59

2

2

B
E

1

3

2

1K_0402_5%

PR

1

1

3

@

1

M UTE

C
M UTE

1
R 727

2

Q702
2SC2411K_SC59

2

1K_0402_5%

B

3

E
4

1
R 728

2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

1K_0402_5%

Compal Secret Data

Security Classification

D

4

2

Title

Compal Electronics, Inc.
AMP & Audio Jack

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
E

30

of

47

SUBWOOFER (Reserved for C38)
WOOFER@
+ AVDD_AC97
C 285

1 U_ 0603_10V4Z

2
C 518 1

L FE_OUT R 478 1

L FE_OUT

2

1

100K_0402_5%

2 C 519

P

+

O

2

-

1 U_ 0603_10V4Z

8
R 184

1

+ AVDD_AC97

R 182

2

1

5

560_0402_5%

6

1

2

560_0402_5%

+

R 477

2

C 513

C 523

O
-

4

<29>

3

2 0 . 1 U_0603_50V4Z

U3 7 A
TLV2462CDR_SO8

8

2
0 . 1 U_0402_16V4Z

G

1
C 512

P

1

4

1

1 U_ 0603_10V4Z
+ AUD _VREF_LF
2

G

+ AUD _VREF_LF
C 514

7

2

M IX_OUT

1

U3 7B
TLV2462CDR_SO8

0 .22U_0603_10V7K

10mil

1 43K_0402_5%

2

0 . 1 U_0603_50V4Z
C 708 1

1 00P_0402_50V8J

2

1

@

Gain = 3.1dB

Fc(LPF)= 1.5KHz

20mil

1

+ AVDD_AC97

R 722
100K_0402_5%

2

SubWoofer Conn.
30mil

2

U1 2
W O O FER_IN

1

1

<30> AMP_OFF#

2
R 732 @

2

1
0_0402_5%

3
<29,30,33> E APD

2
R 733

1
0_0402_5% 2

C 710

2

4

1

VO-

SD#

GND

VDD

SE/BTL#

BYPASS

C 284

2
1

J P44

IN

20K_0402_5%

VO+

W OOFER-

8

2 FBMA-L11-160808-700LMT_0603
2 FBMA-L11-160808-700LMT_0603

1
1

1
2

7
3
4

6
W OOFER+

5

TPA0211DGN_MSOP8

1
2
GND
GND

MOLEX_53780-0270
ME@

1U_0603_10V4Z

0.1U_0402_16V4Z

R 724
100K_0402_5%

C 283

1 0 . 4 7U_0603_16V4Z

L13
L12

1

R 185
M IX_OUT

2

R 723
100K_0402_5%

1
2

1 U_ 0603_10V4Z

2

1

C 709

+ 5VAMP

Fc(HPF)= 36.2Hz
Gain = 15.9dB

+ AUD_VREF_LF

USB Port
+ US B_VCCA
+5VS

1
+

C 174
1 5 0 U_D_6.3VM

+ USB_VCCA
U2 5
C 411 0 . 1 U_0402_16V4Z

2

1

<35,37> S YS O N#

1
2
3
S YS ON# 4

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

C 161

2

8
7
6
5

1

1

2

2

C 160
1000P_0402_50V7K

0 . 1 U_0402_16V4Z
USB_OC#0 <21>

J P21

G528_SO8

D 14
@ PSOT24C_SOT23

C 321
@10P_0402_25V8K

2

1

2

C 322
@ 10P_0402_25V8K

5
6
7
8

VCC
DD+
GND
GND1
GND2
GND3
GND4

1

2

1

2

C 417
@ 1000P_0402_50V7K

3

1

1
2
3
4

<21> US B 20_N0
<21> USB20_P0

S UYIN_ 0 2 0173MR004G565ZR
ME@

For EMI

Compal Secret Data

Security Classification
Issued Date

2005/10/06

Deciphered Date

2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

Title

Compal Electronics, Inc.
Bluetooth & USB CONN.

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

星 期 四 , 二 月 23, 2006

R ev
0 .1
Sheet

31

of

47

5

4

3

2

1

D

D

INT_KBD CONN.( TYPE "D" KB)
C P1
K S I[0..7]

K S I[0..7]

KSO[0..16]

K SI1
K SI7
K SI6
KSO9

<33,38>

K SO[0..16] <33,38>

1
2
3
4

8
7
6
5

100P_1206_8P4C_50V8
C P2

1
2
3
4

+3VALW

Power BTN

8
7
6
5

1

K SI4
K SI5
KSO0
K SI2

R 118
100K_0402_5%

JP26

2
D2
O N /OFFBTN#

<38> O N/ OFFBTN#

100P_1206_8P4C_50V8
C P4
KSO2 1
8
KSO4 2
7
KSO7 3
6
KSO8 4
5

2

O N/ OFF

3

5 1ON#

1

O N/OFF# <33>
5 1ON#

SW1

1

+3VALW

3

C

<38,39>

D AN202U_SC70

100P_1206_8P4C_50V8
C P6
KSO6 1
8
KSO3 2
7
KSO123
6
KSO134
5

R 113
4.7K _0402_5%
@

SMT1-05_4P
E C _ON

E C _ON

D1
R L Z20A_LL34

2 C 205
1000P_0402_50V7K

2

3

<33>

DTC124EK_SC59
1

2

4

1

2

1

Q10

1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

C

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

100P_1206_8P4C_50V8
C P3
K SI3 1
8
KSO5 2
7
KSO1 3
6
K SI0 4
5

6
5

K SI1
K SI7
K SI6
KSO9
K SI4
K SI5
KSO0
K SI2
K SI3
KSO5
KSO1
K SI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

100P_1206_8P4C_50V8
C P5
KSO141
KSO112
KSO103
KSO154

ACES_85202-2405

8
7
6
5

100P_1206_8P4C_50V8

B

B

JP33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

J P43

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

FOR LPC SIO DEBUG PORT

+5VS

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS

L P C_AD0
L P C_AD1
L P C_AD2
L P C_AD3
L P C_FRAME#
L PC_DRQ#0
P CI_RST#

S I RQ

C LK_14M_SIO <15>

L P C _AD[0..3]

L P C_FRAME# <20,33>
L PC_DRQ#0 <20>
P CI_RST# <19,21,24,25,26,27,33>
C L K_PCI_DB <15>
S IRQ
<21,24,26,33>

L P C_AD[0..3] <20,33>

R 391
10K_0402_5%

2

1
@

ACES_85201-2005
ME@

P C I_CBE#0
P C I _AD6
P C I _AD4
P C I _AD2
P C I _AD0
P C I _AD1
P C I _AD3
P C I _AD5
P C I _AD7
P C I _AD8
P C I_CBE#1
P C I_CBE#2
P C I_CBE#3

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

P C I _AD9

P C I_CBE#0 <19,24,26,27>
P C I_AD6 <19,24,26,27>
P C I_AD4 <19,24,26,27>
P C I_AD2 <19,24,26,27>
P C I_AD0 <19,24,26,27>
P C I_AD1 <19,24,26,27>
P C I_AD3 <19,24,26,27>
P C I_AD5 <19,24,26,27>
P C I_AD7 <19,24,26,27>
P C I_AD8 <19,24,26,27>
P C I_CBE#1 <19,24,26,27>
P C I_CBE#2 <19,24,26,27>
P C I_CBE#3 <19,24,26,27>

DEBUG PORT
2

+ 5VALW

R 725

2

+3VS

R 726

1
@ 0_0402_5%

1

+5VALW : FOR EC
+3VS : FOR P-80

@ 0_0402_5%
J P 22

<33>
<33>

EC_TX
EC_RX

1
2
3
4

EC_TX

1
2
3
4

P80_DATA
P80_CLK

ACES_85205-0400
ME@

C L K_PCI_DB <15>
+5VS
P CI_RST# <19,21,24,25,26,27,33>
P C I_ FRAME# <19,24,26,27>
P C I_ TRDY# <19,24,26,27>
P C I_AD9 <19,24,26,27>

ACES_85201-2005
ME@

A

A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
KBD,ON/OFF,T/P,LED/B,DEBUG

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

32

of

47

5

4

3

2

1

+3VALW

+EC_AVCC

2
+3VALW

2

D

<27> LAN_PME#
<19> PCI_PME#

KSO[0..15]
<32>

+5VS
1
2
3
4

<32,38> KSI[0..7]

8
7
6 EC_GPIO4C
5 EC_GPIO4D
10K_1206_8P4R_5%
@

+3VALW

KSO[0..15]
K SI[0..7]

RP13

<38>
<38>

RP14
1
2
3
4

8
F RD#
7
6
FSEL#
5
100K_1206_8P4R_5%
<13,14> EC_P80_CLK
<13,14> EC_P80_DATA

+5VALW

+3VS
B

EC_SMB_CK2
2
4.7K_0402_5%
EC_SMB_DA2
2
4.7K_0402_5%
C226

1
R135
1
R139

@ 100P_0402_50V8J

<4> EC_SMB_DA2
<4> EC_SMB_CK2
<34,40> EC_SMB_DA1
<34,40> EC_SMB_CK1
0_0402_5%
2
0_0402_5%
2

R7131
R7141

<32>
EC_TX
<32>
EC_RX
<37> PWR_LED#
<38> NUM_LED#
<37> CHARGE_LED0#
<37> CHARGE_LED1#
<38> CAPS_LED#
<38> EC_GPIO55
<35,37,43> S YS ON

EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%

1
R130
1
R133

KSO16
KSO17

1

2

<21> EC_RSMRST#
1
<16> BKOFF#
C223
<21> SLP_S3#
<21> EC_LID_OUT#
@100P_0402_50V8J
<21> SLP_S5#
2
<21>
EC_SMI#
R4011
<38> EC_GPIO09
<37> L ID_SWITCH#
<18,24,26,34,35,37,43,44> SUSP#
<21> PBTN_OUT#

COMM EC_GPIO Configuration

A

HDL00/HDL10
NC
EASY_KEY1#
SUSP_LED#
NC
NC
NC
NC
NC
NC
MEDIA#
VOL_UP#
VOL_DOWN#
KILL_SW#
AMP_MUTE

HGT30/HGT31
TP_ACT_LED#
LED6#
EC_P80_DATA
LED3#
LED4#
NC
LED1#
LED2#
LED5#
BT_OFF#
NOVO_BTN#
SLP_S4#
WIRE_LAN_BTN#
TP_LOCK_LED#

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

88
87
86
85

EC_TX
EC_RX

34
35
38
40
CHARGE_LED0# 99
CHARGE_LED1# 101
CAPS_LED#
100
102
S YSON
104
4
BKOFF#
7
8
EC_LID_OUT#
16
17
EC_SMI#
18
0_0402_5% 19
2
LID_SWITCH#
20
SUSP#
21
PBTN_OUT#
22
EC_PME#
23

C RY1
C RY2

140
138

key Matrix
scan

KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
EC URXD/KSO16/GPIO48
EC UTXD/KSO17/GPIO49

EC SMD2/ GPIO47/SDA2
EC SMC2/GPIO46/SCL2
EC SMD1/GPIO44/SDA1
EC SMC1/GPIO44/SCL1

PS2 interface

Data
BUS

Address
BUS
SM BUS

PCM_SPK#/EMAIL_LED#/ GPIO16
SB_SPKR/PWR_SUSP_LED#/ GPIO17
PWRLED#/ GPIO19
NUMLED#/ GPIO1A
BATT CHGI LED#/ E51CS#
BATT LOW LED#/ E51MR0
CAPS LED#/ E51TMR1
ARROW LED#/ E51 INT0
SYSON/GPIO56/ E51 INT1

ADB0/D0
ADB1/D1
ADB2/D2
ADB3/ D3
ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19
SELIO2#/ GPIO43
SELIO#/ GPIO50
FRD#/RD#
FWR#/WR#
FSEL#/SELMEM#

EC_RSMRST#/ GPIO02
BKOFF#/GPIO03
PM SLP S3#/GPIO04
EC LID OUT#/GPIO06
PM SLP S05#/ GPIO07
EC SMI#/GPIO08
EC SWI#/GPIO09
LID SW#/ GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC PME#/GPIO0D

XCLKO
XCLKI

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

EC ON/ GPIO1B
AC IN/ GPIO1C
ECTHERM#/GPIO11
ONOFF/GPIO18
PCMRST#/GPIO1E
WL OFF#/GPIO1F
ALI/MH#/GPIO40
FSTCHG/GPIO41
VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

91
92
93
94
95
96

EC_GPIO4C
EC_GPIO4D
TP_CLK
TP_DATA

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

84
97
135
136
144

BT_OFF#
F RD#
F WR#
FSEL#

EC_GPIO4A <38>
EAPD
<29,30,31>
EC_GPIO4C <38>
EC_GPIO4D <38>
TP_CLK <37>
TP_DATA <37>

ID
0
1

<34>

KBA[0..19]

<34>

ADB[0..7]

R125(Ra)

MB

81
82
83
137
142
143

EC_ON
EC_THERM#
ICH_POK

FSTCHG
V R_ON
EC_GPIO57
EC_GPIO58
1
EC_GPIO59 R486

0.1U_0402_16V4Z

1
2

+3VALW

HGT31

R125
100K_0402_1%
UMA@
1

Ra

MB_ID

R126
0_0402_5%
VGA@

Rb

HGT30

C

R126(Rb)

KBA[0..19]
ADB[0..7]

+5VS
TP_CLK

1
R142
TP_DATA 1
R146

2
4.7K_0402_5%
2
4.7K_0402_5%
+3VALW

KBA1
KBA4

41
43
29
36
45
46

18K_0402_5%

HGT30(VGA)
NC
0 Ohm
HGT31(UMA)100K Ohm
NC

ENBKL
BT_OFF#
FRD#
F WR#
FSEL#

<16>
<28>
<34>
<34>
<34>

KBA5

EC_ON
<32>
A C IN
<21,39>
EC_THERM# <21>
ON/OFF# <32>
ICH_POK <7,21>
WL_OFF# <28>
EC_MUTE <30>
FSTCHG <41>
VR_ON
<45>
EC_GPIO57 <38>
2
0_0402_5%
EC_GPIO59 <38>

C RY1

SLP_S4#

@
1
2
R147
1K_0402_5%
1
2
R148 @ 1K_0402_5%
1
2
R149 @ 1K_0402_5%

KB910L_LQFP144

B

1 R150
2 C RY2
@ 20M_0603_5%

C250

<21>

C249
X1

32.768KHZ_12.5P_1TJS125BJ2A251
A

Compal Secret Data

Security Classification
2005/10/06

Issued Date

2006/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Compal Electronics, Inc.
ENE-KB910L

Size Document Number
C ustom

R ev
0.1

HGT30/31 LA3061

Date:
5

0V
0.25V
0.50V
0.82V
1.19V
1.65V
2.20V
3.30V

2

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
89
90

ACOFF
FAN_SPEED1
MB_ID

INVT_PWM <16>
BEEP#
<29>
TP_LOCK_LED# <37>
ACOFF
<39,41>
FAN_SPEED1 <4>

0
8.2K
18K
33K
56K
100K
200K
NC
R119(Ra)=100K Ohm
MB_ID

E CAGND

GPIO
EC_GPIO3F
EC_GPIO09
EC_GPIO17
EC_GPIO1D
EC_GPIO4A
EC_GPIO4B
EC_GPIO4C
EC_GPIO4D
EC_GPIO55
EC_GPIO50
EC_GPIO57
EC_GPIO58
EC_GPIO59
EC_GPIO12

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPI032
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPI035
KSI6/GPIO36
KSI7/GPIO37

139
129
103
13
28
39

PIN
80
19
35
44
91
92
93
94
102
97
137
142
143
30

INVT_PWM
BEEP#

R115(Rb) Vab

R01 (EVT)
R02 (DVT)
R03 (PVT)
R04

1

EC_PME#

63
64
65
66
67
68
69
70

INVT_PWM/GPIO0F/PWM1
BEEP#/GPIO10/PWM2
OUT BEEP/GPIO12/PWM3
ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

0
1
2
3
4
5
6
7

15P_0402_50V8J

<26> R5_PME#

2
@ 0_0402_5%
2
@ 0_0402_5%
2
0_0402_5%
2
0_0402_5%

25
27
30
31
32
33

DAC_BRIG <16>
EN_FAN1 <4>
IRE F
<41>
TP_ACT_LED# <37>

Rb

R115
2

4

1
R131
1
R141
1
R138
1
R127

<24> CB_PME#

DAC_BRIG
EN_FAN1
IR EF

1

C

76
78
79
80

FAN/PWM
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

BRD ID

BRD ID

IN

1

R134
10K_0402_5%

DAC_BRIG/DA0/GPIO3D
EN DFAN1/DA1/GPIO3D
IREF2/DA2
EN DFAN2/DA3/ GPIO3F
DA output or GPO

PWR

1

C208

OUT

2

+3VALW

EC_RST#
EC_SCI#
R3361
2
@ 0_0402_5%

ID

B RD_ID



2
0.1U_0402_16V4Z

NC

C232
@ 22P_0402_50V8J

<19,21,24,25,26,27,32> PCI_RST#
2
47K_0402_5%
<21>
EC_SCI#
<21,24,26,27> PCI_CLKRUN#
2
C200
<38> EC_GPIO1D
0.1U_0402_16V4Z
1
1
R112

1
C206

Ra

BATT_TEMP <40>
ADP_ID

B RD_ID

NC

+3VALW

1 C202 ECAGND
0.01U_0402_25V4Z

BATT_OVP <41>

15P_0402_50V8J

1
10_0402_5%

BATT_TEMP
BATT_OVP

@

AGND

2
R143@

71
72
73
74

AD INtput or GPI

77

1

GND
GND
GND
GND
GND
GND

2

BATTEMP/AD0/GPIO38
BATT OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD BID0/AD3/GPIO3B

3

<15> CLK_PCI_LPC

2

GA20/ GPIO00/GA20
KBRST#/GPIO01/KBRST#
SERIRQ
LPC_FRAME# / LFRAME#
LPC AD3/LAD3
LPC AD2/LAD2
Host
LPC AD1/LAD1 INTERFACE
LPC AD0/LAD0
CLK_PCI_EC/PCICLK
PCIRST#
EC RST#/ ECRST#
EC SCI#/SCI#/GPIO0E
PM_CLKRUN#/ CLKRUN#

R119
100K_0402_1%

2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
5
6
9
10
12
14
15
42
24
44

75

U6
<20>
GATEA20
<20>
KB_RST#
<21,24,26,32> S IRQ
<20,32> LPC_FRAME#
<20,32> LPC_AD3
<20,32> LPC_AD2
<20,32> LPC_AD1
<20,32> LPC_AD0

EC_AVCC / AVCC

2

Analog Board ID definition,
Please see page 3.

1

11
26
37
105
127
141

2

1

C201
1000P_0402_50V7K

2

1

C237
1000P_0402_50V7K

2

1

C220
0.1U_0402_16V4Z

D

2

1

C248
0.1U_0402_16V4Z

FBM-11-160808-601-T_0603

1

C447
0.1U_0402_16V4Z

C231
0.1U_0402_16V4Z

L6
1
2
+EC_AVCC
FBM-11-160808-601-T_0603 2
1
C212
C211
0.1U_0402_16V4Z
1000P_0402_50V7K
L7
1 ECAGND 2
1
2

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

+3VALW

星期四, 二月 23, 2006

Sheet
1

33

of

47

+ 5VALW

1

+5VALW
C 199
2 0 . 1 U_0402_16V4Z

1

R 116
100K_0402_1%

8
7
6
5

<33,40> EC_SMB_CK1
<33,40> E C_SMB_DA1

2

U4

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

AT24C16AN-10SU-2.7_SO8
+ 3VALW

1

+3VALW

R 117
100K_0402_1%

R 442
100K_0402_1%

S USP#

2

2

1

3

E C _ FLASH# <21>

S

I1

O

D

I0

1
Q30
2N7002_SOT23

3

F W R#

+3VALW

<33>

@

R 339
IN T_FSEL# 1

5

2 0_0402_5%
@
@

2

4

P

R707 1

I0

G

4

P
F W E#

G

2

5

U3 2
T C7SH32FU_SSOP5

<18,24,26,33,35,37,43,44>

2

2

0 . 1 U_0402_16V4Z

G

1

1

C 501

I1

O

1

F SEL#

F SEL#

<33>

3

22_0402_5%

U2 6
R 337
TC7SH32FU_SSOP5
@ 100K_0402_5%
INT _ F LASH_EN# 1
2
2

1

2

R338

0_0402_5%

Reserve R339, if U26 is single gate.
<33>

K BA[0..19]

<33>

AD B[0..7]

K B A[0..19]

1MB Flash ROM

AD B [0..7]

+ 3VALW
U3 0

<33>

FRD#

K BA0
K BA1
K BA2
K BA3
K BA4
K BA5
K BA6
K BA7
K BA8
K BA9
K BA10
K BA11
K BA12
K BA13
K BA14
K BA15
K BA16
K BA17
K BA18
K BA19

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

IN T_FSEL#
F R D#
F W E#

22
24
9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE#
OE#
WE#

VCC0
VCC1
D0
D1
D2
D3
D4
D5
D6
D7
RP#
NC
READY/BUSY#
NC0
NC1

GND0
GND1

31
30
25
26
27
28
32
33
34
35
10
11
12
29
38

1
A DB0
A DB1
A DB2
A DB3
A DB4
A DB5
A DB6
A DB7

RESET#

2

1MB ROM Socket

C416
0 . 1 U_0402_16V4Z

J P34

SB_INT_FLASH_SEL tie to ATI SB
GPIO1 and pull down
1
R443
100K_0402_1%

2

+ 3VALW

<21> S B _ INT_FLASH_SEL

23
39

K BA16
K BA15
K BA14
K BA13
K BA12
K BA11
K BA9
K BA8
F W E#
RESET#
INT _ F LASH_EN#
S B _ INT_FLASH_SEL
K BA18
K BA7
K BA6
K BA5
K BA4
K BA3
K BA2
K BA1

SST39VF080-70-4C-EIE_TSOP40

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

K BA17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

K BA19
K BA10
A DB7
A DB6
A DB5
A DB4
+ 3VALW
A DB3
A DB2
A DB1
A DB0
F R D#
F SEL#
K BA0

ME@ S UYIN_80065AR-040G2T

Compal Secret Data

Security Classification
Issued Date

2005/10/06

Deciphered Date

2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

Title

Compal Electronics, Inc.
BIOS & EC I/O Port

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

星 期 四 , 二 月 23, 2006

R ev
0 .1
Sheet

34

of

47

A

B

C

D

E

F

G

H

I

J

1

+5VALW

R 92

+5VALW to +5VS Transfer
1

1

2

47K_0402_5%

U2 7
C 435
1 0 U_0805_10V4Z

8
7
6
5

1

1

+VSB

2

D
D
D
D

S YS ON#

<31,37> S YS ON#
0 . 1 U_0402_16V4Z

S
S
S
G

1
2
3
4

S I4 800DY_SO8

2

Q6
2N7002_SOT23

C 419

2

+5VALW

2

1

R 384
10K _0402_5%

S

G

1
C 426
1 0 U_0805_10V4Z

D

2

<33,37,43> S YS ON

1

1

+5VS

3

+ 5VALW

R UNO N

R 334

2
10K _0402_5%

1

D

2

1

2

2

S

<44>

S USP

1

G
Q26
2N7002_SOT23

S USP
D

3

C 434
0 . 1 U_0603_50V4Z

2
3

S USP

S

2

<18,24,26,33,34,37,43,44> S USP#

G

Q24
2N7002_SOT23

3

3

+3VALW to +3VS Transfer
+ 3VALW
+3VS

+5VS

+ 1.8VS

C 224
0 . 1 U_0603_50V4Z

R 58

470_0402_5%

470_0402_5%

1 2

R 335

D

2 S USP
G
Q25
2N7002_SOT23

3

S

1

C 313
VGA@
1 0 U_0805_10V4Z

2

D
D
D
D

S
S
S
G

1
2
3
4

1

S I4 800DY_SO8
VGA@

R 227
33K _0402_5%
VGA@

2

C 131
VGA@
1 0 U_0805_10V4Z

1

1

S

2

2

2

C

D

470_0402_5%
D

2 S YS ON#
G
Q5
2N7002_SOT23

S

R 105
470_0402_5%

6

D

2 S USP
G
Q704
2N7002_SOT23

S

2 S USP
G
Q7
2N7002_SOT23

R UNO N
0_0402_5%

Compal Secret Data
2005/10/06

Deciphered Date

2006/10/06

Title

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

R 731

470_0402_5%

7

Issued Date

A

R 228

D

5

S USP
2
G
Q8
2N7002_SOT23

C 312
0 . 1 U_0603_50V4Z
VGA@

Security Classification

8

C 133

3

2

R 129 1
D

3

S USP 2
G
Q20
2N7002_SOT23
VGA@

1

S

@

7

1

VGA@
0 . 1 U_0402_16V4Z

S

+2.5VS

1 2

+VSB

8
7
6
5

1

2 S USP
G
Q3
2N7002_SOT23

S

+3VS

1 2

+1.8VS
U1 7

6

470_0402_5%
D

1

+ 1.8V

+1.8V

R 106

D

5

+1.8V to +1.8VS Transfer

+0.9VS

1

2

R UNO N
2
@0_0402_5%

1 2

S

2

G
Q11
2N7002_SOT23

4

1

1

C 225

2

3

2
1

R 132 1
D

3

S USP

1 0 U_0805_10V4Z

1

2

R 136
22K _0402_5%

1

C 229

1 2

S I4 800DY_SO8

3

1

1

2

0 . 1 U_0402_16V4Z

1
2
3
4

1 2

1

4

C 236
1 0 U_0805_10V4Z

S
S
S
G

3

+VSB

D
D
D
D

3

U7

8
7
6
5

1

E

PDF created with pdfFactory Pro trial version www.pdffactory.com

F

G

H

Compal Electronics, Inc.

8

DC/DC Circuit
Size
D oc um ent Num ber
C u s tom HGT 3 0 /31 LA3061
D ate:

星 期 四 , 二 月 23, 2006

I

R ev
0 .1
Sheet

35

of

J

47

A

B

C

D

E

CLOSE TO JTVOUT1

VGA I/O PORT Connector

L 802

1

1

1

D 803

D 804

D A204U_SC70
@

D A2 04U_SC70
@

D A204U_SC70
@

S-VIDEO
J P802

L UM A_OUT

C R MA_OUT

C R MA_OUT
COMP_OUT

L UM A_OUT

1
2
3
4
5
6

L 803

1

2

C804
82P_0402_50V8J

C R MA

C803
82P_0402_50V8J

<17>

FLM1608081R8K_0603

1

2

1

3

2

3

2

D 802

2
2

1

+3VS

1

2

1

2

FLM1608081R8K_0603

3

1

C801
82P_0402_50V8J

L UMA

C802
82P_0402_50V8J

<17>

COMP_OUT

1

1
2
3
4
5
6

G1

G2

7

8

MOLEX_53780-0670
ME @

2

L 801

1

2

C806
82P_0402_50V8J

FLM1608081R8K_0603

1

1

D805

D 801

D 806

+CRT_VCC

D A204U_SC70
@

D A2 04U_SC70
@

D A204U_SC70
@

DSUB

2

R ED_OUT
+5VS + CRT_VCC

L804
CHB1608B121_0603

GR E EN

1

B L UE

1

J VG A_VS_OUT

2

2

1
C809

1

2

MSEMS#

VGA _DDC_DAT_OUT
VGA _DDC_CLK_OUT

2

22P_0402_50V8J

2

22P_0402_50V8J

C807

1

J VGA _HS_OUT

RB751V_SOD323

L806
CHB1608B121_0603

C808

<17>

B LUE_OUT

D 807

2

L805
CHB1608B121_0603

22P_0402_50V8J

<17>

1

RED

1

<17>

GR EEN_OUT

2

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

3

2

3

2

J P801

2

2

+3VS

1

1

1

3

C OMP

C805
82P_0402_50V8J

<17>

1

1

P IN4

1
1

C 810
C 811
C 812
10P_0402_25V8K10P_0402_25V8K 10P_0402_25V8K
2
2
@
@
@

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1

C814

2

ACES_87213-1400
ME@

C 813
0 . 0 1U_0402_25V4Z

2

2 0 . 1 U_0402_16V4Z

+ CRT_VCC

2
1

R804
2.2K_0402_5%

2
1

2

R803
2.2K_0402_5%

1

CF8

1

@

2

C F9

1

C F 10

1

C F11

1

C F 12

1

C F13

1

C F 14

1

F M6

1

H9
HO LEA

H1 0
HO LEA

H1 1
HO LEA

H1 2
HO LEA

H1 3
HO LEA

H1 4
HO LEA

H1 5
HO LEA

1

H8
HO LEA

1

H7
HO LEA

1

H6
HO LEA

1

H5
HO LEA

1

H4
HO LEA

2

1

H3
HO LEA

F M5

1

C F7

1

@

1

1

F M4

1

CF6

1

1

1

H2
HO LEA

1

1

H1
HO LEA

F M3

1

C F5

1

CHB1608B121_0603

1

F M2

1

CF4

1

1

F M1

1

C F3

1

1

CF2

1

1

C F1

1

2
2
C815
33P_0402_50V8J

L808

R ED_OUT
GR EEN_OUT
B LUE_OUT
VGA _DDC_DAT_OUT
VGA _DDC_CLK_OUT
J VGA _HS_OUT
J VG A_VS_OUT

CHB1608B121_0603

1
1

C816
33P_0402_50V8J

L807

<17> VGA_DDC_CLK
<17> JVGA_ HS
<17> JVGA_VS

1

3

R802
1K_0402_5%

<17> VGA_DDC_DAT

2

R801
1K_0402_5%

1

PIN ASSIGMENT

4

FUNCTION
+CRT_VCC
RED
GND
GREEN
GND
BLUE
GND
VSYNC
GND
HSYNC
SENSE
SM_DAT
SM_CLK
PIN4

3

4

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

PIN SVIDEO FUNCTION
1
1
NC
2
4
CRMA
3
2
GND
4
3
LUMA
5
5
GND
6
6
CVBS

1

1

1

1

H2 7
H2 8
H2 9
H3 0
C L1
HO LEA HO LEA HO LEA HO LEA C L IP

1

H2 6
HO LEA

1

H2 5
HO LEA

1

H2 3
HO LEA

1

H2 2
HO LEA

1

H2 1
HO LEA

1

H2 0
HO LEA

1

H1 9
HO LEA

1

H1 8
HO LEA

1

1

H1 7
HO LEA

PIN D-SUB
1
9
2
1
3
6
4
2
5
7
6
3
7
8
8
14
9
10
10
13
11
11
12
12
13
15
14
4

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D

Title

Compal Electronics, Inc.
CRT & TVout Connector

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
E

36

of

47

5

4

3

2

NEW CARD FOR C38

1

LED Indicator ON M/B
+1.5VS_PEC

3

2

1

B

B A

B A

4 . 7 U_0805_10V4Z

Express Card Power Switch
EXP@
C 819
+1.5VS
0 . 1 U_0402_16V4Z
D

2

1

12
14

EXP@
C 820
0 . 1 U_0402_16V4Z

2

+3VS

C 821

2

1

2
4
+3VALW

20

S USP#

2 R 807

+ 3VALW

6

S YS ON

<33,35,43> S YS O N
<18,24,26,33,34,35,43,44> S USP#

<21>

17

PLT_RST#

0 . 1 U_0402_16V4Z
<7,19,23,28> PLT_RST#

+1.5VS_PEC

1.5Vin
1.5Vin

1
C 818

2

+5VS
EXP@

2

1

1EXP@ 100K_0402_5%

10
9

C P USB#

18

3.3Vin
3.3Vin

3
5

3.3Vout
3.3Vout

AUX_IN

SHDN#

PERST#

EXP@
C 822
0 . 1 U_0402_16V4Z

16

NC

CPPE#

( 1 )

8

PERST#

STBY#

1

1

2

2

<28> BTONLED

1
C 825

EXP@

( 2 )

2

close to JP14

EXP@

0_0402_5%

<21,28> IC H_ PCIE_W AKE#

2

IC H _SMBCLK
IC H_ SMBDATA
+1.5VS_PEC
+1.5VS_PEC

P C IE_PME#_R

+3V_PEC

EXP@
0_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

U SB7USB7+
C PUSB#

2
2

R 811 1

+ 5VALW

Blue
LED802

2 150_0402_5%

J P803

0_0402_5%

<15,21,28> IC H_SMBCLK
<15,21,28> IC H_ SMBDATA

R 810 1

PERST#

+3VS_PEC
C L K RENC#
C PUSB#
C L K _PCIE_NC1#
C L K _PCIE_NC1

<15> C L KREQ_NC#
<15> C L K _PCIE_NC1#
<15> C L K _PCIE_NC1

P C IE_RXN1
P CIE_RXP1

<21> P C IE_RXN1
<21> PCIE_RXP1

P CIE_TXN1
PCIE_TXP1

<21> P CIE_TXN1
<21> PCIE_TXP1

27
28

close to JP14

C HA RGE_LED1#

<33> C HARGE_LED1#

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

( 3 )

1

2

4

3

2 220_0402_5%

1

C

HT - 2 97UD/NB_BLUE/AMB_0603

Amber

LED803
P W R_LED#

<33> P W R_LED#

R 813 1

2 150_0402_5%

1

2

Blue : Power On, HT-191NB5-DT_BLUE_0603~D
Blinking Blue : Suspend
47K
<33> TP_ACT_LED#

2

TP_ACT

10K

150_0402_5%
R844 1
2

D T A114YKA_SC59
Q802

2

<33> TP_LOCK_LED#

GND
GND

+5VS

LED804

1

2

HT-191NB5-DT_BLUE_0603~D
LED805

47K

R845 1

2

470_0402_5%

10K

1

2

HT-191NB5-DT_BLUE_0603~D
D T A114YKA_SC59
Q803

F OX_1CH4110C
ME@

TP_LOCK
B

1

B

R 812

BATT_LOW_LED#

3

1
1

3

3

EXP@
R 808
R 809

2

4

1

US B20_N7
U SB20_P7

1

2 220_0402_5%

BLUE
Blinking Blue
Amber

BATT_CHG_LED#
C HA RGE_LED0#

<33> C HARGE_LED0#

US B20_N7
USB20_P7

2 150_0402_5%

Amber
STATUS
AC
Chargin
Low BATT

RCLKEN

2

1

C 823 EXP@
4 . 7 U_0805_10V4Z

4 . 7 U_0805_10V4Z

1

R 806

HT - 297UD/NB_BLUE/AMB_0603

+3VS_PEC

EXP@
C 824
0 . 1 U_0402_16V4Z

<21>
<21>

BTONLED

7

GND

CPUSB#

R 5538_QFN20
EXP@

C

R 805 1

<28> W IRELESS_LED#

+3V_PEC
+3V_PEC

19

OC#

L ED801

Blue

15

AUX_OUT

SYSRST#

D

Wireless / Bluetooth LED

11
13

1.5Vout
1.5Vout

+3VS_PEC

1

EXP@

1
EXP@
C 817
0 . 1 U_0402_16V4Z

U8 01

+ USB_VCCB

USB board

T/P Board

1
+

C 826
1 5 0 U_D_6.3VM

LID Switch
+5VS

+3VALW
C 483 0 . 1 U_0402_16V4Z

2
R 193
47K_0402_5%

ACES_87151-0807G
ME@

1

1
2
3

S YS ON# 4

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

8
7
6
5

3

D 19

1

2
RB751V_SOD323

G528_SO8

C 287
U1 3

A3212EEHLT-T_SOT23W-3
A

2

R 816 0_0402_5%

Pulled up on ICH7M side

L ID _ SW ITCH# <33>

2

C 828
1000P_0402_50V7K

<21> US B20_N2
<21> USB20_P2

1
2
1R 814 0_0402_5%
2

<21> US B20_N4
<21> USB20_P4

1
2
1R 817 0_0402_5%
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

R 815 0_0402_5%

USB_OC#2 <21>

1

OUTPUT

1

2

R 481
100K_0402_5%

1

USB_OC#4 <21>

R 818 0_0402_5%

1

2

R 846 0_0402_5%
@

<30>
PL
<29> J AC K _PLUG
<30>
PR

EXT_MIC
C 835

C835 ~ C838 For EMI Solution

EXT_MIC

<30> EXT_MIC
<29,30,38> INT _ MIC
<29> J AC K _ PLUG_MIC

C500
@ 1000P_0402_50V7K

2

15P_0402_50V8J

C 286
0 . 1 U_0402_16V4Z

1

<31,35> S YS O N#

1

2

0 . 1 U_0402_16V4Z

2

<33>
<33>

1

TP_DATA
TP_CLK

2

1

0_0402_5%

2

TP_DATA
TP_CLK

1
R 195

2

+ 3VALW
+5VS

VDD

1
2
3
4
5
6
7
8

GND

1
2
3
4
5
6
7
8

1

J P27

U9
JP804

C 827

2

+ USB_VCCB

C 169
C836

C 837

680P_0402_50V7K

680P_0402_50V7K

C838
680P_0402_50V7K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_87213-2000
ME@

680P_0402_50V7K

680P_0402_50V7K

Normally Short For JACK_PLUG
Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
INDICATE LED

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

37

of

47

A

5

4

3

2

1

UMA LCD/PANEL Conn.

3 IN 1 Card Reader

J P805

31

GND

JP806

3 IN 1 MS/SD/MMC

+ VC C_4IN1
<26> S DCLK_MSCLK

2
4
6
8
10
12
14
16
18
20
21
22
23
24
25

S DCLK_MSCLK
S D DATA0_MSDATA0
S DDATA1

<26> S DDATA0_MSDATA0
<26> S DDATA1

S DCD#_XDCD0#
SDW P#_XDRB#

<26> S D CD#_XDCD0#
<26> SDW P#_XDRB#

Connector
DAT2_SD
DAT3_SD
CMD_SD
VSS_SD
VCC_SD
CLK_SD
VSS_SD
DAT0_SD
DAT1_SD
GND_SD
CD_SD
WP_SD
GND_SD
GND
GND

MS INTERFACE

S DDATA2
S D DATA3_MSDATA3
S DCMD_MSBS

<26> S DDATA2
<26> S DDATA3_MSDATA3
<26> S DCMD_MSBS

SD INTERFACE

D

VSS_MS
VCC_MS
SCLK_MS
DAT3_MS
INS_MS
DAT2_MS
SDIO/DAT0_MS
DAT1_MS
BS_MS
VSS_MS

1
3
5
7
9
11
13
15
17
19

S DCLK_MSCLK
S D DATA3_MSDATA3
M SCD#_XDCD1
S DDATA2
S D DATA0_MSDATA0
S DDATA1
S DCMD_MSBS

+ VC C_4IN1
SDCLK_MSCLK <26>
S D DATA3_MSDATA3 <26>
MSCD#_XDCD1 <26>
S DDATA2 <26>
S D DATA0_MSDATA0 <26>
S DDATA1 <26>
S DCMD_MSBS <26>

TAISO_143-2300302900_23P_LB
ME@

32

GND

(60 MIL)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

+ L CDVDD

+3VS

E D I D_CLK_LCD
E D I D_DAT_LCD
LVDSBC+
L VDSBC-

E D ID_CLK_LCD <9>
E D ID_DAT_LCD <9>
L VDSBC+ <9>
L VDSBC- <9>
D

LVDSB2+
LVDSB2-

LVDSB2+ <9>
LVDSB2- <9>

LVDSB1+
LVDSB1-

LVDSB1+ <9>
LVDSB1- <9>

LVDSB0+
LVDSB0-

LVDSB0+ <9>
LVDSB0- <9>

L VDSAC+
L V DSAC-

L VDSAC+ <9>
L VDSAC- <9>

L VDSA1+
L VDSA1-

LVDSA1+

<9>

L VDSA1- <9>

L VDSA0+
L VDSA0-

LVDSA0+ <9>
L VDSA0- <9>

L VDSA2+
L VDSA2-

L VDSA2+
L VDSA2-

<9>
<9>

FOX_GS23302-1010S-7F
ME@

SWITCH BD

RJ11+RJ45 CONN
C

C

Dial Wheel
LED Indicator BD

1
L

JP807
<27>

MDO0+

<27>

MDO0-

<27>

MDO1+

<27>

MDO2+

<27>

MDO2-

<27>

MDO1-

<27>

MDO3+

<27>

MDO3-

MDO0+

1

MDO0-

2

MDO1+

3

MDO2+

4

MDO2-

5

MDO1-

6

MDO3+

7

MDO3-

8

TX1+

2

3

4

5

M

TX1-

+5VALW

6
H

+5VS

+ VCC5_LED

NOVA_BTN#

1

2

C 829

1

2

R 819 0_0402_5%

1

2

R 820 0_0402_5%
@

1000P_0402_50V7K

Function

RX1+
KEY Matrix

TX2+
TX2-

KO16

KO17

KSI0

DW-UP

DW-DOWN

KSI1

DW-ENTER

LED6#
LED5#
LED4#
LED3#
LED2#
LED1#

RX1RX2+
SGND1
RX2SGND2

MUTE

11
12

<33>
<33>
<32,33>
<32,33>

KSO16
KSO17
K SI0
K SI1

KSO16
KSO17
K SI0
K SI1

L ED6#

<33> E C_GPIO55

L ED4#

<33> E C _GPIO1D
<33> E C _GPIO4D
<33> E C _GPIO4C

R 821
R 822
R 823
R 824
R 825
R 826

1
1
1
1
1
1

2
2
2
2
2
2

220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%

L ED6#

RJ45
3

<29,30,37> INT _ MIC

47K

D T A114YKA_SC59
Q801

2

RJ11
ALLTO_C100B6-110A4-L
0 . 1 U_0402_16V4Z
R J 45_PR ME@ 1
2
C 840
1
1000P_1206_2KV7K
C 834

R J45_PR

0 . 1 U_0402_16V4Z

0 . 1 U_0402_16V4Z

0 . 1 U_0402_16V4Z

C 830

2
L ED4#

1

C 831

2

1

C 832

100K_0402_5%
100K_0402_5%
100K_0402_5%

<33> E C_GPIO59

10K

R 830

J P808

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

R 831

@

WIRE_LAN_BTN#
2

2

<33> E C _GPIO4A

R 829

@

N OVO_BTN#

4 . 7 U_0805_10V4Z
D T A114YKA_SC59
Q804

HDD

1

D 808

<20> SATA_LED#

1

+ 3VALW

D 809

1

2
C H751H-40_SC76

1

<23> O DD_LED#

2
C H751H-40_SC76

CD-ROM
R 835
100K_0402_5%

NOVO BTN

MDC CONN

N OVO_BTN#

<33> C APS_LED#

E C_GPIO57

E C_GPIO57 <33>

3

5 1ON#

5 1 ON#

1

1

2

2

1

ME@
ACES_87151-2007L~N
C 842
1000P_0402_50V7K
A

<32,39>

C839, C841, C842 For EMI Solution

D AN2 02U_SC70

1
2

C 841
470P_0402_50V8J

2
2

JP809
R J _TIP
R J_ R ING

2 220_0402_5%
2 220_0402_5%
2 220_0402_5%

1
1
1

<33> NUM_LED#

D 810

A

R 832
R 833
R 834

B

C 839
1000P_0402_50V7K
@

2

<32> O N/OFFBTN#

47K

2

1

+3VS

1

1

<27>

2
10K

2

R 828

RJ11_1
RJ11_2

2

<33> E C_GPIO09

1

0_0603_5%

1

1

C 833

1
9
10_0603_5% 10

1

2
2

2

R 827
R J _TIP
R J_ R ING

3

B

E DL71_MDC

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

Compal Electronics, Inc.
INDICATE LED

Size
D oc um ent Num ber
C us tom HGT 3 0 / 31 LA3061
D ate:

R ev
0 .1

星 期 四 , 二 月 23, 2006

Sheet
1

38

of

47

A

B

C

D

ACIN

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.169V 6.231V 6.361V
L-->H 7.168V 7.349V 7.537V

Precharge detector
Min.
typ.
Max.
H-->L 14.620V 14.853V 15.245V
L-->H 15.534V 15.970V 16.421V
V IN
A D P IN

1

2

VS

2

P R8
1 K_1206_5%

1

2
1

1

1
< 2 1 ,3 3 >

P A CIN

< 41>

1 2

A CIN

2

1

2

P R16
1 0K_0402_1%
RTCV RE F

1

P R15
10K_0402_1%

P U1A
L M 3 9 3 DG_ S O8

1

-

P A CIN

1

2

O

2

A COFF

2

PQ2
D T C 1 1 5 E UA _ S C7 0

Vin Detector

P Q3
D T C 1 1 5 E UA _ S C7 0

High 18.384 17.901 17.430
Low 17.370 16.907 16.630

3.3V

B+

2

3

< 3 3 ,4 1 >

P

+

3

2

P R13
1 00K_0402_5%

1

1
2

P R11
1 0K_0402_5%

1

P D3
R L Z 4 .3 B _ L L 3 4

2

4

1

3

G

2

2

P R9
1 0K_0402_1%

2

8

P R12
2 2K_0402_1%

P C6
0 . 1 U_ 0 4 0 2 _ 1 6 V 7 K

1

P R10
8 4 .5 K _ 0 4 0 2 _ 1 %

2

3

1

2

VS

P R14
2 0K_0402_1%

1

2

P R4
1 K_1206_5%

P R5
1 M_ 0 4 0 2 _ 1 %

1

2

1

1

2

1

1

1

2

P Q1
T P 0 6 1 0 K -T 1 -E 3 _ S OT23

P R7
1 00K_0402_5%

2

V IN

P C5
1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7K

P R3
1 K_1206_5%

2

1

2

VIN

1

2

P D2
R L S 4 1 4 8 _ L L DS 2

P R 175
P C 131
1 0 K _ 0 4 0 2 _ 1 % @ 0 . 0 1 U_ 0 4 0 2 _ 2 5 V 7 K

@

2

1

P R6
1 00K_0402_5%

1
1
2

1
2

1
2

1

2

@ J S T _ B 4 B -E H-A (L F )(S N)

P C3
100P_0402_50V8J

4

2

3

2

4

P R2
1 K_1206_5%

2

P R1
P D1
1 0_1206_5%
R L Z24B_LL34

1

1

3

2

P C2
1 00P_0402_50V8J

2

P L2
F B MA -L 1 8 -4 5 3 2 1 5 -9 0 0 L MA 9 0 T _ 1 812

P C1
5 6 0 P _ 0 4 0 2 _ 5 0 V 7K

1

1

1

P C4
560P_0402_50V7K

P JP1

P R17
2 . 2 M_ 0 4 0 2 _ 5 %

VL

2

1

2

1

RTCVREF

2
2

1

(6A,240mils ,Via NO.=12)

P J4
P A D - O P E N 3 x3 m

2

+ 5 VALW

1

+ 0 .9 V S P

2

(5A,200mils ,Via NO.= 10)

+ 3 VALWP

1

1
2

1

P C7
0 . 0 1 U_ 0 4 0 2 _ 2 5 V 7 K

PACIN <41>

+5VALWP

2

@
+ 0 .9 V S

P Q6
D T C 1 1 5 E UA _ S C7 0

(0.3A,40mils ,Via NO.= 2)

P J6
P A D - O P E N 3 x3 m

4

1

S

3

1

P R29
4 7K_0402_5%

2

G

2

+ 5 VALWP

2
2

(6A,240mils ,Via NO.= 12)

P J3
P A D - O P E N 3 x3 m

P Q5
R H U 0 0 2 N 0 6 _ S OT 3 2 3

P R 25
4 99K_0402_1%

1

1
1

D

P R 24
1 91K_0402_1%

3

6

P R G ++ 2

P U1B
L M 3 9 3 DG_ S O8

5

P C9
1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7K

-

P R28
3 4K_0402_1%

+ 1 .8 V

P R18
499K_0402_1%

8
+

O

2

1
2

1

P
7

G

1
2

P R 19
1 00K_0402_1%

1

4

2

3

ACON

1

1

+ 1 .8 V P

<41>

3

+ 1 .5 V S

2

1

2

<40,42> MAINPWON

P R 30
6 6 .5 K _ 0 4 0 2 _ 1 %

1

P D6
R B 7 1 5 F _ S OT 3 2 3
VS

1

2

P R 27
2 2K_0402_1%
1
2
< 3 2 ,3 8 >
51ON#
P J2 P A D - O P E N 3 x3 m

P J1
P A D - O P E N 3 x3 m
+ 1 .5 V S P

3

P C12
0 . 2 2 U_ 1 2 0 6 _ 2 5 V 7 K

1

C H GRTCP

1

GND

1

2

2

1

2

2

IN

1

OUT

P R26
1 00K_0402_5%

2

1

3
P C11
4 . 7 U _ 0 8 0 5 _ 6 .3 V 6 K

2

2

P R 21
5 610 _ 0 6 0 3 _ 5 %2 1
+ C HGRTC

P R23
2 00_0805_5%
P C10
1 U _ 0805_25V4Z

P R22
5 60_0603_5%

PQ4
T P 0 6 1 0 K -T 1 -E 3 _ S OT23

2

P U2
G 9 2 0 A T 2 4 U_ S OT 8 9

P C8
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

2
1

R TCV RE F

3

VS

P C13
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

3.3V

2

1 1

P D5
R B 7 5 1 V -4 0 T E 1 7 _ S OD3 2 3 -2
BATT+

P R 20
3 3_1206_5%
P D4
R L S 4 1 4 8 _ L L DS 2

V IN

P J1 1
P A D - O P E N 3 x3 m

2

+ 3 VALW

+ 2 .5 V S P

1

2

4

+ 2 .5 V S

(4.5A,180mils ,Via NO.= 9)
P J7
P A D - O P E N 3 x3 m
+ 1 .0 5 V S P

1

+V CCP

(5A,200mils ,Via NO.= 10)
A

+VSBP

1

2

Issued Date
+VSB

Compal Electronics, Inc.

Compal Secret Data

Security Classification

P J8
P A D - O P E N 3 x3 m

2

2005/08/01

Deciphered Date

2006/08/01

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(0.3A,40mils ,Via NO.= 2)

T itle

DCIN/DECTOR
S ize
B
Da te :

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D o c u m e n t N u mb e r

R ev
0 .1

星 期 一, 二月 20, 2006

S heet
D

39

of

48

B

C

VS

P R38
1 K_0402_1%

4

1

M A I N P W O N < 3 9 ,4 2 >

2

1

VS
+V S B P

+

P

8
6

O
-

7

G

5

4

1
2

P C21
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

1

2

1
2

P C20
0 . 2 2 U_ 1 2 0 6 _ 2 5 V 7 K

1

P R41
100K_0402_5%

1

2

D

3

P R44
0 _0402_5%

1

P U3B
L M 3 9 3 DG_ S O8

S P Q8
R H U 0 0 2 N 0 6 _ S OT 3 2 3

2
G

2

1

S P OK

O

P U3A
L M 3 9 3 DG_ S O8

3

P C22
0 . 1 U_ 0 4 0 2 _ 1 6 V 7 K

2
1
< 42>

P R 43
1 00K_0402_5%

3

2

2

P R42
2 2K_0402_1%

-

P R39

2
PQ7
T P 0 6 1 0 K -T 1 -E 3 _ S OT23

3

+

2 1 5 0 K _ 0 4 012 _ 1 %VL

2

B+

2

P R40
1 50K_0402_1%

1
2

P C 19
1 U _ 0 6 0 3 _ 6 .3 V 6 M

1
2

1
2

E C _ S MB _ CK 1 < 3 3 ,3 4 >

1

2
3

T M _ RE F 1

B A T T _ TEMP <3 3 >

P R32
150K_0402_1%

1

16 1 .9 K _ 0 6 0 32_ 1 %

P

P R37

+ 3 VALWP

E C _ S MB _ DA 1 < 3 3 ,3 4 >

VL

P R34

1 4 4 2 K _ 0 6 023 _ 1 %

G

2

2

1

2

P R36
6 .49K_0402_1%

1

1

VL

8

A L I / M H#

2

1

1

VL

P C 17
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

1
2

1
2

1

+ 3 VALWP

P C 15
1000P_0603_50V7K

2

2

1

PH1 under CPU botten side :
CPU thermal protection at 85 degree C
Recovery at 70 degree C

B A T T+

2

P H1
1 0 0 K _ 0 6 0 3 _ 1 % _ T H1 1 -4 H1 0 4 F T

2

P R 178
4 7K_0402_5%
P A D - O P E N 3 x3 m

P C18
1000P_0402_50V7K

2

1

@ S U Y I N _ 2 5 0 0 0 5 MR0 0 7 G1 6 1 Z L _ 7 P _ RV

1

1

2

1

P R 176
1 K_0402_1%

1

P L3
F B MA -L 1 8 -4 5 3 2 1 5 -9 0 0 L MA 9 0 T _ 1 812

1
P C 14
1000P_0603_50V7K

A L I / N I M H#
A B /I
TS_A
E C _ S MDA
E C _ S MCA

2
3
4
5
6
7

P R35
1 00_0402_1%

1

P R 177
1 K_0402_1%

2

ID
B/I
TS
SMD
SMC
GND

2

P R31
1 00_0402_1%

BATT+

B A T T _S1

1

P R33
1 0 .7 K _ 0 4 0 2 _ 1 %

B A T T++

P J2 2

P JP 2

D

P C 16
0 . 0 1 U_ 0 6 0 3 _ 5 0 V 7 K

A

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/08/01

Deciphered Date

2006/08/01

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T itle

BATTERY CONN. / OTP
S ize
B
Da te :

A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

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R ev
0 .1

星 期 一, 二月 20, 2006

S heet
D

40

of

48

B

4
2

2

1

PC26
2200P_0402_50V7K

1
2

1

PC25
0.1U_0603_25V7K

2

19

1

3

2

18

VIN

P R58
47K_0402_1%

17

1

+INE1

-INE3

OUTC1 FB123

15

PR62
33K_0402_1%
M B39A126 1

P C35
1500P_0603_50V7K

21

2

2

P R56
0.02_2512_1%

1

4

2

3

12

-INC1

CTL
+INC1

14
PC40
10P_0402_50V8J

13

1

1

SEL

2

BATT+

BATT+

2

2

10

16

2

1

PL5
10U_LF919AS-100M-P3_4.5A_20%

1

2

1

RT

AC O FF <33,39>

PQ14
D T C115EUA_SC70

2

-INE1

AC O FF

PC38
4.7U_1206_25V6K

VH

ACIN XACOK

P C32
0 .1U_0603_25V7K

1

VREF

OUT

1

ACOK

2

1
2

PR65
0_0402_5%

1

2

PD11
EC31QS04

8

11

2

+3VALWP

IREF=0.932*Icharge
IREF=0.466~2.61V
I fast charge=2.8A

AC O N

P C41
47P_0402_50V8J

CS

1

2

1

1

2

PR67
47K_0402_5%

CC=2.8A

3

(100K/(100K+133K))*2.61V=1.12V

2

3

1

LI-3S :13.05V----BATT-OVP=1.45V
BATT-OVP=0.111*BATT+

PQ18
D TC115EUA_SC70

2

1
2
2

1

1
2
-

6

G

-

3
2

P

+

0

5V*(10K/(30K+10K))=1.25V
1.25V/(20*0.02)=3.125A

5

P U12B
LM358A_SO8

8
1

65W HGT31 CP Point=3.125A

2

1

+
0

1.666V/(20*0.02)=4.166A

2

7

5V*(10K/(30k+10k))=1.666V

4

P U12A
LM358A_SO8

2005/08/01

A

B

C

4

Compal Electronics, Inc.
2006/08/01

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

Charge voltage
3S CC-CV MODE : 12.6V
SEL is L

Compal Secret Data

Security Classification
Issued Date

PC43
0.01U_0402_25V7K

<33> BATT_OVP

1

VS

4

90W HGT30 CP Point=4.166A

PR69
PR68
499K_0402_1% 340K_0402_1%

VS

3

1.12/(20*0.02)=2.8A

BATT+
PQ19
D T C115EUA_SC70

PR72
105K_0402_1%

F S T CHG

3

<33>

PC42
0.01U_0402_25V7K

1

2

<39>

P AC IN

1

20

PD10
EC31QS04

2

P R61
10K_0402_1%

PR66
22K_0402_1%
<39>

PC30
0 .1U_0603_25V7K

21

2

1

PD12
RLS4148_LLDS2

1

VCC

PQ13
AO4407_SO8

4

2

1

2

PC39
0.01U_0402_25V7K

1
2

G

CS

-INE2

1

5
6
7
8
P R57
P C34
1K_0402_1% 2200P_0402_50V7K
M B39A1261

2

2

S PQ17
R HU002N06_SOT323

2

+INE2

AC OFF#
P C29
0 .22U_0603_16V7K
CS

22

LXCHRG

7

2

PR63
100K_0402_1%

1

1

24
23

1

6

PR60
133K_0402_1%
<33>

3

IR E F

GND

2

5

9

D

+INC2

1

NA

PR54
20K_0402_1%

1

1

PR53
10K_0402_1%

2
1
2

PC33
0.22U_0603_16V7K

PQ16
R HU002N06_SOT323

2

1
2

S

PC31
0.01U_0402_25V7K

1
2

G

PR55
150K_0402_1%

PQ15
D T C115EUA_SC70

4

OUTC2

VIN

2

2
3

D

-INC2

1

1

2

PC37
4.7U_1206_25V6K

2

PR48
47K_0402_1%

1

PC36
4.7U_1206_25V6K

PR52
100K_0402_1%

2

1

1

1

8
7
6
5

3
2
1

PC28
4700P_0402_25V7K

2

1

1
3

1

2

1
2
1
1
P R51
10K_0402_1%

47K

2

AC OFF#

2

P U4
MB39A126PFV-ER_SSOP24

2

CHG_B+
PC24
4.7U_1206_25V6K

1

1
2
3

PR50
10K_0402_1%

PL4
FBMA-L11-322513-201LMA40T_1210

P2

M B39A126

1

3

PR49
0_0603_5%

2

3

4

2

2

PQ12
D T A144EUA_SC70
47K

2

1

PQ11
AO4407_SO8

4

1
2

2

8
7
6
5

Charger

B+

3

1
2

PR47
47K_0402_5%

1

4

1

1
2
3
PR46
200K_0402_1%

1
2
3
PC27
0.1U_0603_25V7K

8
7
6
5

VIN

E

Fosc=14100/Rt=14100/47=300KHz

P R45
0.02_2512_1%

PQ10
AO4407_SO8

PQ9
AO4407_SO8

D

Iadp=0~3.125A
Iadp=0~4.166A

PR59
47K_0402_5%

P2

C

PR54=30K_0402_1%
PR54=20K_0402_1%

PR64
47K_0402_5%

PR45=0.02_2512_1%
PR45=0.02_2512_1%

PC23
4.7U_1206_25V6K

A

65W
90W

D

Title

PWR-Charger
Size
B
D ate:

D oc um ent Num ber

R ev
0 .1

星 期 一 , 二 月 20, 2006

Sheet
E

41

of

48

A

B

C

D

2

B+

P L6
F B MA -L 1 1 -3 2 2 5 1 3 -2 0 1 L MA 4 0 T _ 1 210

1
P J 23

2

P C 46
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K
B S T 3B

1

2

MA X 8 7 4 3 _B+

1
2

P Q 20
S I 4 8 0 0 B DY -T 1 -E 3 _ S O8

5
6
7
8
D
D
D
D
4
3
2
1

G
S
S
S

1
2

P Q3 0
S I 4 8 1 0 B DY -T 1 -E 3 _ S O8

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

P R82
0 _0603_5%

2
2
1
2

S P OK

P R93
P R90
0 _0402_5% @ 3 .57K_0402_1%

7
2

1
+

2

+3VALWP

P C58
1 5 0 U _ V _ 6 .3 V M_ R1 8

1

D H3

P L8
4 . 7 U H _ P C M C 0 6 3 T -4 R7 MN_ 5 .5 A _ 2 0 %

2

D L3

PRO#
< 40>

P C51
1 0 U_ 1 2 0 6 _ 2 5 V A K

1
2

1

P C50
2 2 0 0 P _ 0 4 0 2 _ 5 0 V 7K

2
1

2
2
1
2
1

28
26
24
27
22

B S T 3A

1

2

P R84
P R81
3 74K_0402_1% 2 00K_0402_1%

2
2 1
1

1
3

P C 60
14 . 7 U _ 0 8 0 5 _26 .3 V 6 K 10
P R 92
0 _0402_5%

1
2
P R94
4 7K_0402_5%

REF

11

3HG
LX3

P C61
0 . 0 4 7 U_ 0 6 0 3 _ 1 6 V 7 K

1
2

P C57
0 . 0 4 7 U_ 0 6 0 3 _ 1 6 V 7 K

+5V Ipeak = 6.5A ~ 10.4A

P R89

10 _ 0 4 0 2 _ 5 %2

2

2

2 1

1

1

12

2VREF_19998

P R88
4 7K_0402_5%

P R91
1 00K_0402_5%

P ZD1
R L Z 5 .1 B _ L L 3 4

LDO3

2
P R86
0 _0402_5%

25

1

@

1

VS

2

6
4
3

LX5
DL5
ILIM5
OUT5
P U6
FB5
BST3
N.C.MA X 8 7 3 4 A E E I+_ QS OP 2 8 DH3
DL3
SHDN#
LX3
ON5
OUT3
ON3
FB3
SKIP#
PGOOD

P R 83
P R80
3 74K_0402_1% 2 00K_0402_1%

5

DH5

GND

15
19
21
9
1

P R79
0 _0603_5%

1
2
1
2

ILIM3

P C53
1 U _0805_16V7K

17

2
13

V+

BST5

VCC

16

1
P A D - O P E N 3 x3 m

2VREF_1999

TON

18
14

2

P C49
0 . 1 U_ 0 4 0 2 _ 1 6 V 7 K

2

P R 75
4 7_0402_5%

1

1
2

P R77
4 .7 _ 1 2 0 6 _ 5 %

1
2
2
1
2

P C 54
4 . 7 U _ 0 8 0 5 _ 6 .3 V 6 K

1 P C55
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

P C52
1 U _ 0805_25V4Z

1

P Q2 9
S I 4 8 1 0 B DY -T 1 -E 3 _ S O8

S
S
S
G
1
2
3
4

B S T 5A

23

P R 85
1 0 .2 K _ 0 4 0 2 _ 1 %

D L5

P R87
0 _0402_5%

1

2

1

+

2

1

P C56
1 5 0 U _ V _ 6 .3 V M_ R1 8

2

1

+5VALWP

@

VL

P C59
0 . 2 2 U_ 0 6 0 3 _ 1 6 V 7 K

2
PL7

2

4 . 7 U H _ P C M C 0 6 3 T -4 R7 MN_ 5 .5 A _ 2 0 %

D
D
D
D

8
7
6
5

LX5

P R76
4 .7 _ 1 2 0 6 _ 5 %

D H5

2

20

2

P J 24

P R74
0 _0603_5%

1

P R78
0 _0603_5%

1

VL

MA X 8 7 4 3_B+

LD05

5HG

P D13
C H P 2 0 2 U _ S C7 0

1

P Q 21
S I 4 8 0 0 B DY -T 1 -E 3 _ S O8

D
D
D
D
S
S
S
G
1
2
3
4

1
2

P C48

1
2

8
7
6
5

1

1 0 U_ 1 2 0 6 _ 2 5 V A K

P C47
2 2 0 0 P _ 0 4 0 2 _ 5 0 V 7K

1

P A D - O P E N 3 x3 m
MA X 8 7 4 3_B+

B S T 5B

2

B +++

1

2

3

1

P C45
0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

3

+3.3V Ipeak = 6.5A ~ 8.26A

1
2

P C62
1 U _ 0 6 0 3 _ 6 .3 V 6 M

M A I N P W O N < 3 9 ,4 0 >

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/08/01

Deciphered Date

2006/08/01

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T itle

+5VALWP/+3VALWP
S ize
D o c u m e n t N u mb e r
C u s to m
Da te :

A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

R ev
0 .1

星 期 一, 二月 20, 2006

S heet
D

42

of

48

5

4

3

2

1

+1.8VP Ilimit = 7.87A~12.5A
+1.05VSP Ilimit=6.33A~10.03A

D

D

OZ813_B+
PL9
FBMA-L11-322513-201LMA40T_1210

P J25

1

1
2
1
2

1

OZ813_B+

P AD-OPEN 3x3m
PL11
3 . 3 UH_PCMC063T-3R3MN_6A_20%

2

P C80
5600P_0402_50V7K

1.05VS1P

2

1
2

1

+

2

1

1.05VS1N

2

1

PC78
220U_D2_4VM_R15

1
2

2 1

PR107
51_0402_1%

+1.05VSP

P R108
PR109
100K_0402_1% 29.4K_0402_1%

1

28mohm

2

B

PC82
4700P_0402_25V7K

1

PC79
10U_1206_25VAK

2

C

PC70
4700P_0402_25V7K

1

PC69
22P_0402_50V8J

2
2

PC81
22P_0402_50V8J

PQ31
SI4810BDY-T1-E3_SO8

+

2

P J26

PC156
2.2U_0603_6.3V6K

1
2
PQ24
SI4800BDY-T1-E3_SO8

D
D
D
D
G
S
S
S
4
3
2
1
5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

PR95
51_0402_1%

8
7
6
5
D
D
D
D
S
S
S
G

1
2
3
4
1
2

1
2

PR264
1K_0402_1%

1
2

5
6
7
8

2
2

+3VALW P
P C132
0 . 1U_0402_16V7K

1

2

1.8VS2N

1

DL_1.05V

PR263
0_0402_5%

2
1

LX1.05V

2
1

1

1

+5VALW P

2

2

PC68
6800P_0402_25V7K

PC71
1 U_0805_16V7K

DH_1.05V

1

PR179
100K_0402_1%

1

1.8VS2P

2

RB751V-40TE17_SOD323-2
P C76
0 .1U_0603_25V7K

B+

+1.8VP

P R98
22K_0402_1%

2

P D17

1.05VS1N

B

1

BST_1.05V1

1.05VS1P

P C77
1000P_0402_50V7K

1

+5VALW P

VSET1
CS1N
CS1P
PGD1
LX1
HDR1

1

2

2
PR106

1

150K_0402_1%

PR172
61.9K_0402_1%

2

P R97
100K_0402_1%

RB751V-40TE17_SOD323-2
P D16

BST_1.8V

18
17
16
15
14
13

OZ813LN_QFN24

1.05SET

2

PC66
220U_D2_4VM_R15

1

PQ23
SI4810BDY-T1-E3_SO8

DL_1.8V

1
BST2
LDR2
VDDP
GDNP
LDR1
BST1

1.8VSET

<18,24,26,33,34,35,37,44> S USP#

2

24
23
22
21
20
19

25
GNDA

ON/SKIP2
VIN
VREF
TSET
VDDA
ON/SKIP1

7
8
9
10
11
12

1
2

PC75
0.01U_0402_25V7K

1

VSET2
CS2N
CS2P
PGD2
LX2
HDR2

2

2
1
2

2

2

1
2

1

1

PC73

0.1U_0603_25V7K

P R105
75K_0402_1%

PC74
1U_0603_6.3V6M

DREF

1

2

2

PC72
0.022U_0402_16V7K

1

PR103
24K_0402_1%
@

1
2
3
4
5
6

1

P R101
0_0402_5%

2

PR100
1K_0402_1%

@

1

PR99
22_0402_1%

P U7

PC67
0.1U_0603_25V7K

2

P C65
1000P_0402_50V7K

PR104
100K_0402_1%

2
C

1

P AD-OPEN 3x3m

LX_1.8V

1

1
1

2

1

PL10
3 . 3 UH_PCMC063T-3R3MN_6A_20%28mohm

1.8VSET
PC184
0.01U_0402_25V7K

<33,35,37> S YS O N

1
2
3
4

DH_1.8V

2

8
7
6
5
S
S
S
G

2

2

+5VALW P
PR266
0_0402_5%

PQ22
SI4800BDY-T1-E3_SO8

P R262
0_0402_5%

1

D
D
D
D

1

1.8VS2N
1.8VS2P

PR261
1K_0402_1%

+ 3VALW P

PC63
10U_1206_25VAK

2

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/08/01

2006/08/01

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

1.05VP/1.8VP
Size
D oc um ent Num ber
C u s tom
D ate:

R ev
0 .1

星期一, 二月 20, 2006

Sheet
1

43

of

48

5

4

3

2

1

+1.5VSP Ilimit = 9.38A~12.5A

B+

P J27

1

2

D

2

FBMA-L11-322513-201LMA40T_1210

1

2

1

P AD-OPEN 3x3m

PC83
10U_1206_25VAK

PL12

D

P H ASE_VCCPP
PR265
10K_0402_1%

1

UG_ VCCPP
PR110

2
1

2

1

0_0603_5%

2

P C85 0 . 1U_0402_16V7K

BOOT_VCCPP

1

+5VS

5
6
7
8

13

VIN

PVCC

D
D
D
D
1

G
S
S
S

12

2 PC86

2 .2U_0603_6.3V6K
6 2 69_VCC

2

VCC

LG

PQ26

P R1122 6 2 69_VCC
4.7_0603_5%

SI4800BDY-T1-E3_SO8

4
3
2
1

1

BOOT

UG

2

14

15
PHASE

GND

PGOOD

1

16

17

P R111
@ 4.7_0603_5%
P U8

L G _VCCPP

11

P L13

1

2

+1.5VSP

1

5
6
7
8

10

D
D
D
D
IS E 1N_VCCPP 2
PR115
8.66K_0402_1%

+

PQ27
SI4810BDY-T1-E3_SO8

P C88
2 2 0 U_D2_4VM_R15

C

G
S
S
S

2
4
3
2
1

VO

9

8

1

PC89
0 .01U_0402_25V7K

FSET

ISEN
COMP

EN

7

4

2

PGND

0_0402_5%

2
47K_0402_5%

FCCM

5

1

<18,24,26,33,34,35,37,43> S USP#

3

2

FB

P R114

C

1
P C87
2 . 2U_0603_6.3V6K

3 . 3 UH_PCMC063T-3R3MN_6A_20%

6

2

1

P R113

1

2

PC90
0 .01U_0402_25V7K

2

PR117

1
1

2

P R116
49.9K_0402_1%

2

2

22P_0402_50V8J

PC91

1

1

IS L6269CRZ-T_QFN16

57.6K_0402_1%
P C92
6800P_0402_25V7K
PR118

1

2

1

4.53K_0402_1%
P R119
3K_0402_1%

+1.8VP
B

1

1

2

+3VS

B

2
2

P J10
JUMP_43X79

2

P U9

1
2
1

3

P R120
1K_0402_1%

4

VCNTL

GND

NC

VREF

NC

VOUT

NC

4

1

7

PC95
1 U_0603_6.3V6M

8
9

+0.9VSP

1

R HU002N06_SOT323
PQ28 D

1

2
G

2

S

P R124
P C101
1K_0402_1% 0 . 1U_0402_16V7K

2

2

2

1

1

PR123
100K_0402_1%
S USP

3

<35>

1

P C98
@ 1 5 0 U_D_6.3VM

1

+

2

+3VALW P

APL5331KAC-TRL_SO8

2

22U_1206_6.3V6M

1

2
1

0 .01U_0402_25V7K

2

P C99
2.15K_0402_1%

PC97

1

1
P R122

9

APL5912-KAC-TRL_SO8

TP

+2.5VSP

2

FB
VIN

1

EN

2

2

PC100
0 .01U_0402_25V7K

3

6
5

2

PC94
2 2 U_1206_6.3V6M

P C96
2 2 U_1206_6.3V6M

2

1
VOUT
VOUT

8

GND

2
1

<18,24,26,33,34,35,37,43> S USP#

5

VIN

2

PR121
33K_0402_1%

1

VIN

2

POK

VCNTL

P U10

7

6

1

2

1 U_0603_6.3V6M

1

P C93

2

1

1

1

+5VS

P J9
J UMP_43X118

PC102
2 2 U_1206_6.3V6M

P C103
0 .1U_0402_16V7K

PR125
1K_0402_1%
A

2

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/08/01

2006/08/01

Deciphered Date

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

Title

+VCCPP/+2.5VSP/0.9VSP
Size
D oc um ent Num ber
C u s tom
D ate:

R ev
0 .1

星期一, 二月 20, 2006

Sheet
1

44

of

48

5

4

3

2

1

+5VS

B+
PL14
FBM-L11-322513-201LMAT_1210
2
1

1

34

<5>

CPU_VID4

2

1

35

<5>

CPU_VID5

2

1

36

<5>

CPU_VID6

1

2

37
71.5K_0402_1%
1
7
2
470P_0402_50V8J
1

<4,20> H_DPRSTP#

1

2

40

1

2

3

+3VS

CSN1

CCV

FB

REF

CCI

DPRSLPVR

DH2

DPRSTP

BST2

PSI

LX2

PWRGD

DL2

16

CSN1_CPU

12

FB_CPU

10

C CI_CPU

21

DH2_CPU

20

BST2_CPU

22

LX2_CPU

24

DL2__CPU

CSP2

VRHOT

CSN2

CSP2_CPU

15

CSN2__CPU

PR238

@ 3K_0603_1%
1
2

PR242
1

PC171 @
1

3.65K_0402_1%
2

1

2

1

1

NTC PR245
@ 3K_0603_1%
1

@

PC163
2200P_0402_50V7K
2
1

PC162
0.1U_0603_25V7K
2
1

0.022U_0402_16V7K
CPU_VCC_SENSE
2

2

PR243

100_0402_5%

PC172
4700P_0402_25V7K

2
PR246
3K_0603_1%

2

1

2

4

3
2
1

PC181
0.1U_0402_16V7K

5
6
7
8

2

1

2

PQ36
FDS6676AS_SO8
4
G
D
3
S
D
2
S
D
1
S
D

DL2__CPU

5
6
7
8
PQ37
FDS6676AS_SO8
4
G
D
3
S
D
2
S
D
1
S
D

2

1

PL16
P_0.36H_ETQP4LR36WFC_24A_20%

NTC
PR259
10K_0603_5%
1
2

PR258
3.48K_0402_1%
1
2

1
PR260 0_0402_5%
1
2

A

2005/06/20

Issued Date

PC183

Deciphered Date

2006/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

A

Title

+CPU_CORE
Size Document Number
C ustom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

2

0.22U_0603_16V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification

5

PC180
2200P_0402_50V7K
2
1

D HS

2

PR255
@10_0402_5%

2

B

PR254 10K_0402_5%
2

2
1

29.6

PR267
1

1

POUT

PQ35
SI7840DP_SO8

2.2_0603_5%

VSSENSE

PC179
0.1U_0603_25V7K
2
1

VSSENSE
<5>

CPU_B+

PC178
10U_1206_25VAK
2
1

PR253 @ 0_0402_5%
1
2

PC173
470P_0402_50V8J

PR248
20K_0402_1%

1

<4> H_PROCHOT#

C

PC176
10U_1206_25VAK
2
1

B

1

PR252
56_0402_5%

1

3

S

1000P_0402_50V7K
PR251
100_0402_5%

2

+3VS
PR250
10K_0402_5%
@

PC175
2
1

1

PR249
0_0402_5%

PQ38
2
G

VCCSENSE

2

1

1

PC174

2

V R_ON

2

0.22U_0603_16V7K

13
BSTM2_CPU

GNDS
TP

POUT

2

D

14

2

1

4

<5>
1
PC169

PR235
0_0402_5%

2

SHDN

MAX8770GTL+_TQFN40

1

RHU002N06_SOT323

5

2
0_0402_5%
@ PR247
1
2
<33>

23

41

<15> CLK_ENABLE#

PGND2

PR239

PR240
PR241
2.1K_0402_1% @ 2K_0402_1%
1

1

CLKEN

NTC
3.48K_0402_1% 10K_0603_5%
PR230
PR231
2
1
2

1

PR237 0_0402_5%
1
2

1

38

<21> VGATE

PC161
10U_1206_25VAK
2
1

5

CSP1__CPU

17

2

2

1

PR244
0_0402_5%

PC160
10U_1206_25VAK
2
1

1

TIME

18

2

2

CSP1

PC177
10U_1206_25VAK
2
1

H_PSI#

GND

D6

DL1__CPU

27

+CPU_CORE

PR257
2.1K_0402_1%

<5>

D5

26

1

0_0402_5%

2

PGND1

2

0_0402_5%

PR236

11

0.22U_0603_16V7K 39

1

D4

PC182
680P_0603_50V7K

PR234

PC170

<7,21> DPRSLPVR

DL1

+CPU_CORE
PL15
P_0.36H_ETQP4LR36WFC_24A_20%
2
1

2

1

499_0402_1%

9

LX1

D3

PR268

PR256
4.7_1206_5%
1

PR233

1
PC168
2

D2

LX1__CPU

2

2

28

1

1

CPU_VID3

DH1

2.2_0603_5%

PC166
BSTM1_CPU 1
2

10_0402_5%
1

<5>

D1

2

PR229
2

33

DH1__CPU

2.1K_0402_1%
PR226
1
2

CPU_VID2

1

BST1_CPU 1

29

PC167
680P_0603_50V7K

<5>

2

PR220
30

PR224
4.7_1206_5%
1

32

8

2

1

BST1

1

2

TON

D0

2

CPU_VID1

THRM

3
2
1

<5>

C

D

4

5
6
7
8

31

PR232 2

2

200K_0402_5%
2 PR216 1

1

1

0.22U_0603_16V7K

5

PR228 0_0402_5%

2

0_0402_5%

PQ34
FDS6676AS_SO8
4
G
D
3
S
D
2
S
D
1
S
D

PR227 0_0402_5%

+
2

PQ32
SI7840DP_SO8

25

DL1__CPU

PR225 0_0402_5%

6

CPU_VID0

VDD

5
6
7
8

PR223 0_0402_5%

2

<5>

Vcc

PQ33
FDS6676AS_SO8
4
G
D
3
S
D
2
S
D
1
S
D

PR222 0_0402_5%

19

0_0402_5%

PR221 0_0402_5%

VCC

0.22U_0603_16V7K

PR219 0_0402_5%

1

PU11

1

NTC
0_0402_5%
PR218
1

1

2

PC164
2.2U_0603_6.3V6K
PC165
1U_0603_6.3V6M

2

PR217
@ 13K_0402_1%

2

2
D

PC159
10U_1206_25VAK
2
1

0_1206_5%
PR215
10_0402_5%

PC157
0.01U_0402_25V7K

1

1

PC158
100U_25V_M

CPU_B+
PR214
5VS12

2

R ev
0.1

星期一 , 二 ?20, 2006

Sheet
1

45

of

48

5

4

3

2

Version change list (P.I.R. List)
Item
D

C

Fixed Issue

1

Reason for change

Rev.

P G#

Modify List

1

Page 1 of 1
for PWR

VER

Phase

MODIFY 3V/5V current limit to 6.5A~8.1A/6.5A to 10.2A

42

MODIFY PR83/PR84 FROM 499K TO 374K

DVT

2

ADD or decrease CPU CORE ring with EMI solution :
snubber

45

Reserve PR224//PR256: 4.7 1206 ,add
PC167/PC182:680P

DVT

3

Reserve PR267,PR268 seperate in CPU CORE high
side gate for EMI require

45

4

change PJP1 from 5 pin to 4 pin

39

5

modify sequecce

43

6

modify Vgate

45

Reserve PR267,PR268:0 0603

D

DVT

change PJP1 from 5 pin to 4 pin

DVT

change PR179 to 100k, PC132 =0.1U

DVT

add PQ38:RHU002N06,PR240:2K,delete PR247

7

C

8
9
10

11

B

B

8
9

A

A

Compal Electronics, Inc.
T itle

PIR (PWR)

5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

3

2

S ize

D o c u m e n t Nu mb e r

D a te:

星 期一, 二月 20, 2006

R ev
0 .2
Sheet
1

46

of

48

A

B

C

D

Version change list (P.I.R. List)
I tem

E

Page 1 of 1

Fixed Issue

Rev.

Add EC_Port80 Signals to DDR2 DIMM1 & DIMM2

0.2

PG#

Modify List

B.Ver#

P hase

1

1

P.13
1

1.Connect U6.91 (EC_P80_CLK) through a 0 Ohm R to JP3.83 & JP4.83

P.14

2.Connect U6.92 (EC_P80_DATA) through a 0 Ohm R to JP3.69 & JP4.69

0.2

DVT

2

Impedance not match for both CRT & TV Out

0.2

P.17

R3, R4, R5, R6, R7, R8 Change from NC to 150 Ohm

0.2

DVT

3

LCD Panel will flash white frame when power on

0.2

P.16

no stuff D10 (CH751H), stuff R204 (100K)

0.2

DVT

0.2

P.21

GPIO10 connect to ACIN

4

ICH7's GPIO configuration modification
0.2

DVT

0.2

DVT

GPIO7 connect to G7X_THER_ALERT#
GPIO39 connect to KILL_MDC#

5

 MDC supports S4/S5 resuming

0.2

P.28

MDC power connection change to +3VALW from +3VS
Line-Out connection change from Pin.35/Pin.36 to Pin.43/Pin.45

Audio Circuit modification for :
Connect Pin.32 (LFE_OUT) through 2 1uF Cap to Pin.43/Pin.45

2

1. Line-Out connection change from Pin.35/Pin.36 to Pin.43/Pin.45

2

+Audio_VREF_LF connection change to 1/2 +AVDD_AC97

6
2. Audio-OUT Auto-Switch by HP Pluging In

0.2

0.2

DVT

0.2

DVT

P.29-31 Int.MIC connection changes to Pin31/Pin32 through 1uF for each

3. MicPhone Noise Reduction

New Add a JACK_PLUG_MIC signal from MIC JACK

4. Cleared off BO Sound from both entry of Windows XP & Power Off

EAPD signal connect to EC'sGPIO4B
APA2068's 13PIN(SE/BTL#) connect to GND

New add Port80 information OUT from Pin34(CLK), pin35(DATA)
EC GPIO configuration modification
LED4 connection changes from GPIO17(35 PIN) to GPIO4A(91 PIN)
New Add DAC’s EAPD connect to EC’s GPIO4B (92PIN).
SKU_ID (GPIO3B) Changes to BRD_ID
0.2

7

P.33

New Add WL_OFF# (GPIO1F, 46PIN)
New Add BT_OFF# (GPIO50, 84PIN)
New Add TP_ACT_LED# (GPIO3F, 80PIN)
New Add TP_LOCK_LED# (GPIO12, 30PN)

3

3

8

Lid Switch changes from USB BD to M/B

0.2

P.37

Circuit of Lid SW changes from USB BD to M/B (DEL Lid SW on USB BD)

9

Blue LED too dark when active due to VF too High on blue LED

0.2

P.37-38 Changes LED power from +3VS(+3VALW) to +5VS(+5VALWS)

New Add LED Buffer for LED4, TP_LOCK_LED#, TP_ACT_LED#

0.2

P.37

0.2

DVT

0.2

DVT

0.2

DVT

0.2

DVT

TP_ACT_LED# connect to Q802.2, and Q802.1 to GND,
then connect to LED804 through a 220 Ohm R

10
TP_LOCK_LED# connect to Q803.2, and Q802.1 to GND,
then connect to LED805 through a 220 Ohm R
P.38
EC_GPIO4A connect to Q804.2, and Q804.1 to GND,
then connect to R283 (220 Ohm)
NC For R458, R402, R411, R128, R831, R829
11

leakage of electricit when System is running S3 mode

0.2

4

4

Compal Electronics, Inc.
T itle

PIR
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D

S ize

D o c u m e n t N u mb e r

R ev
0 .0

HGT30/31 LA-3061
Da te :

星 期 @, 二月 20, 2006

S heet
E

47

of

48

A

B

C

D

Version change list (P.I.R. List)
I tem

E

Page 1 of 1

Fixed Issue

Rev.

PG#

Modify List

B.Ver#

P hase

1

1

1. Add a R734 (0 Ohm) resistor between +2.5V_LAN & VTCT for MAC
GIGA LAN function failed for both Loopback or PXE on RTL8110SCL solution
2. Removed all of the bypass Cap.(C398, C396, C418, C408)
0.3

12

P.27

0.3

PVT

0.3

PVT

0.3

PVT

for MAC's TCT pins
3. Removed all of pulled down resistors (49.9 Ohm) & Cap.(0.01u)

13

Subwoofer still make POP Sound

14

Mic Switch between Int. & Ext. be Failed

15

Wrong parts

0.3

P.31

1. Add 0 Ohm resistors, R732 (0 Ohm) connection between AMP_OFF# &
U12.2 (SD#) for reserved
2. a 0 Ohm connection between EAPD & U12.2(SD#)

0.3

P.29

1. R717.1 Disconnect from U11.17
2. R717.1 connect to U11.16

0.3

P.35

Change package of C434, C224 & C312 from 0402 to 0603

0.3
PVT

1. Connect +3.3VS to R731.1
2. Connect R731.2 to Q704.1

2

16

Add a discharging path of +3.3VS

0.3

2

P.35

0.3

PVT

3. Connect Q704.2 to NET : SUSP signal
4. Connect Q704.3 to GND

3

3

4

4

Compal Electronics, Inc.
T itle

PIR
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

PDF created with pdfFactory Pro trial version www.pdffactory.com

C

D

S ize

D o c u m e n t N u mb e r

R ev
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HGT30/31 LA-3061
Da te :

星 期 @, 二月 20, 2006

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