Compal LA 4117P Schematics. Www.s Manuals.com. R0.3 Schematics

User Manual: Compal LA-4117P - Schematics. Free.

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Page Count: 57

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

Cover Sheet

Custom

1 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Schematics Document

REV:0.3

2009-03-15

Mobile AMD S1G3 CPU with ATI

RS880M(NB) & SB710(SB) core logic

Compal confidential

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

Block Diagram

Custom

2 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Compal Confidential

Thermal Sensor

ADM1032ARMZ

Fan conn

AMD S1G3 CPU

638-PIN uFCPGA 638

Mini-Card*2

16X16

ATI RS880M

Power On/Off CKT.

LPC BUS

DC/DC Interface CKT.

Page 4, 5, 6, 7

Page 10, 11, 12, 13, 14

Page 8, 9

Page 19, 20, 21, 22, 23

Page 24

Page 24

SATA ODD Connector

Page 25

Page 19

RTC CKT.

ATI SB710

Power OK CKT.

Touch Pad CONN. Int.KBD

KBC

Realtek

8102E(10/100M)

RJ45/11 CONN

PCI-E BUS*5

BANK 0, 1, 2, 3

LED

DDR2-SO-DIMM X2

SATA HDD Connector

SATA Master-1

SATA Slave

A-Link Express II

4X PCI-E

Page 26

Page 26

Page 24

Multi-Bay HDD/ODD Option Connector

SATA Slave

SATA Master-2

Page 31

e-SATA Connector

Consumer AMD 14" UMA - Ripley 2.0 (NBW20)

Page 17

Express Card

Page 26

WLAN & WWAN

Page 28 Page 29

Page 31

Page 31

P41

Page 33

Page 33

Page 36

CRT

LVDS Panel

Interface

Page 16

Codec_IDT9271B7

Audio CKT AMP & Audio Jack

TPA6017A2

USB conn x2

USB2.0 X12

Azalia (HDA I/F)

BT Conn

Mini-Card WWAN

Page 6

Page 4

HDMI

Page 18

Clock Generator

SLG8SP626VTR

Page 15

72QFN

ENE KB926-C0

Page 34

P35

P35

Page 12

Side-Port DDR2 SDRAM

1024Mbits(64Mbx16)

DDR2 400MHz

Hyper Transport Link

Page 25

SPI ROM

MX25L1605

AM2C-12G

Page 32

Page 17

USB WebCam

Page 34

Consumer IR SPI

Docking CONN.

*RJ-45(LED*2)

*RJ-11(Pass Through)

*CRT

*COMPOSITE Video Out

*S-VIDEO OUT

*SPDIF

*Headphone/Line Out L/R

*Stereo Mic L/R

*Volume Control

*Consumer IR

*USB x1

*DC JACK

page 35

Module

FingerPrinter AES1610

USBx1

Module

New Module

Page 35

DDR2 800MHz 1.8V

Dual Channel

Page 34

MDC V1.5 daughter board

Accelerometer

ST LIS302DLTR

Page 30

Page 27

CardReader

JMicron

JMB385-LGEZ0A

daughter board

Page 31

USB conn x1

Page 27

CardReader Socket

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B

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C

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D

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

Notes List

Custom

3 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Voltage Rails

O MEANS ON X MEANS OFF

O

O

X

+0.9V

S3

+3VS

X

X

+3VALW

+5VS

S1

O

+2.5VS

+CPU_CORE

OO

OO

X

X X

+VCCP

power

plane

O

O

O

O

O

X

S5 S4/ Battery only

X X X

+B

State

+1.5VS

+1.8V

S5 S4/AC & Battery

don't exist

S5 S4/AC

+5VALW

S0

O

O

Symbol Note :

: means Digital Ground

: means Analog Ground

SERIAL SENSOR

SMB_EC_CK2

SOURCE

KB926

INVERTER BATT EEPROM

THERMAL

SODIMM CLK CHIP

SMBUS Control Table

MINI CARD

SMB_EC_DA2

SMB_EC_CK1

SMB_EC_DA1

KB926

LCD

ADM1032

X

X X X

X

X X

X

X

X X

X

V V

V

1 0 1 0 0 1 0 0A 4

I2C / SMBUS ADDRESSING

1 0 1 0 0 0 0 0

D2

A 0

CL OCK GENERATOR (EXT.)

HEX

DDR SO-D IMM 1

ADDRESS

DDR SO-D IMM 0

1 1 0 1 0 0 1 0

DEVICE

+VGA_CORE

+1.8VS

+0.9VGA

+1.2VS

HEX

98H

HEX

16H

EC SM Bus1 address

Device

A0H

1010 000X b

Address Address

EC SM Bus2 address

Device

1001 100X b0001 011X b

Smart Battery

24C16

CPU

9AH

1001 101X b

ADI1032-2 CPU

L

Layout Notes

Slot 2I / II

CPU &

V

I2C_CLK

I2C_DATA

RS780M

X X X X X X X

V V

SCL0

SDA0 SB700

X X X X X

HDMI

X

X

X

DDC_CLK0

DDC_DATA0 RS780M

X X X X X

DDC_CLK1

DDC_DATA1 RS780M

X X X X X

X X X V

X X X X

XX

XX XX

SDA3

X

SB700

SCL3

XX

XX XX

SDA1 SB700

SCL1

XXX X V

X X

XX XX

SDA2

X

SB700

SCL2

XXX X

Please see VGA@ as no install. No support RX780M.

G-Sensor

X

X

X

X

X

X

V

X

X

: Question Area Mark.(Wait check)

"*" as default BOM setting

*PA@ : means install when Ripley PA.

PR@ : means install when Ripley PR.

RM@ : means install when Rachman.

*RP@ : means install when Ripley.

SIDE@ : means install when SidePort support.

@ : means just reserve , no build

45@ : Install when 45 level Assy

VCPU

ADM1032

DAZ=DAZ03Y00201 DAZ=DAZ03Y00101

SB700

RS780

PCB for 1.0/1.0a

R3 NB and SB: RS780R3@,SBR3@

R1 NB and SB: RS780R1@,SBR1@

DAZ=DAZ03Y00203 DAZ=DAZ03Y00102

PCB for 1.1

For Riply PA-> PA@/RP@/RPZ@

For Rachman UMA-> RM@/PRM@/RMZ@

For Riply PA-> PA@, RP@

For Riply PR-> PR@, RP@, PRM@

For Rachman UMA-> RM@, PRM@

1.0/1.0a

2.0

RP11@,RM11@:For 1.A PCB

RP10@,RM10@:For 1.0 PCB.

For Riply PA-> PA@, RP@,RPZ@

For Riply PR-> PR@, RP@, PRM@,RPZ@

For Rachman UMA-> RM@, PRM@,RMZ@

1.1

DAZ=DAZ09100102DAZ=DAZ09000102

PCB for 2.0

Z Z Z

PCB-Ripley MB

RP10@

Z Z Z

PCB-Rachman UMA MB

RM11@

Z Z Z

PCB-Rachman UMA MB

RM@

Z Z Z

PCB-Ripley MB

RP@

Z Z Z

PCB-Ripley MB

RP11@

U15

SB700 R1

SBR1@

U3

RS780 R1

RS780R1@

X76

X76

Z Z Z

PCB-Rachman UMA MB

RM10@

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

H_CADIN1

H_CADIN0

H_CADIP3

H_CADIN2

H_CADIP2

H_CADIP1

H_CADIN3

H_CADIP4

H_CADIN5

H_CADIN4

H_CADIP5

H_CADIN6

H_CADIN8

H_CADIN7

H_CADIN9

H_CADIP8

H_CADIP6

H_CADIP7

H_CADIN10

H_CADIP10

H_CADIN11

H_CADIP11

H_CADIP9

H_CADIN13

H_CADIN12

H_CADIP14

H_CADIP12

H_CADIN14

H_CADIP0

H_CADIN15

H_CADIP15

H_CADIP13

H_CADON15

H_CADOP13

H_CADON2

H_CADON3

H_CADON9

H_CADON6

H_CADON0

H_CADOP11

H_CADOP8

H_CADOP6

H_CADON13

H_CADOP1

H_CADOP2

H_CADOP4

H_CADOP5

H_CADON12

H_CADON7

H_CADON5

H_CADON10

H_CADON8

H_CADON4

H_CADON1

H_CADOP12

H_CADOP15

H_CADOP9

H_CADOP10

H_CADOP14

H_CADOP7

H_CADOP3

H_CADOP0

H_CADON14

H_CADON11

+VCC_FAN

H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

H_CADIP[0..15]

+VLDT_B

H_CADON[0..15] <10>H_CADIN[0..15]<10>

H_CADOP[0..15] <10>

H_CLKIN0<10>

H_CLKIN1<10>

H_CLKIP1<10>

H_CTLIN1<10>

H_CLKIP0<10>

H_CTLIP1<10> H_CTLOP1 <10>

H_CLKOP1 <10>

H_CADIP[0..15]<10>

H_CLKOP0 <10>

H_CLKON0 <10>

H_CLKON1 <10>

H_CTLON1 <10>

H_CTLOP0 <10>

H_CTLON0 <10>H_CTLIN0<10>

H_CTLIP0<10>

FAN_PWM<33>

+1.2V_HT

+1.2V_HT

+5VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

AMD CPU S1G2 HT I/F

Custom

4 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

250 mil

VLDT=500mA

PWM Fan Control circuit

Athlon 64 S1

Processor Socket

Near CPU Socket

VLDT CAP.

If VLDT is connected only on one side, one

4.7uF cap should be added to the island

side.

9/20 S P07000DM00/SP07000EQ00

C1

4.7U_0805_10V4Z

1

2

HT LINK

JCPUA

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

VLDT_A3

D4 VLDT_A2

D3 VLDT_A1

D2 VLDT_A0

D1

VLDT_B3 AE5

VLDT_B2 AE4

VLDT_B1 AE3

VLDT_B0 AE2

L0_CADIN_H15

N5

L0_CADIN_L15

P5

L0_CADIN_H14

M3

L0_CADIN_L14

M4

L0_CADIN_H13

L5

L0_CADIN_L13

M5

L0_CADIN_H12

K3

L0_CADIN_L12

K4

L0_CADIN_H11

H3

L0_CADIN_L11

H4

L0_CADIN_H10

G5

L0_CADIN_L10

H5

L0_CADIN_H9

F3

L0_CADIN_L9

F4

L0_CADIN_H8

E5

L0_CADIN_L8

F5

L0_CADIN_H7

N3

L0_CADIN_L7

N2

L0_CADIN_H6

L1

L0_CADIN_L6

M1

L0_CADIN_H5

L3

L0_CADIN_L5

L2

L0_CADIN_H4

J1

L0_CADIN_L4

K1

L0_CADIN_H3

G1

L0_CADIN_L3

H1

L0_CADIN_H2

G3

L0_CADIN_L2

G2

L0_CADIN_H1

E1

L0_CADIN_L1

F1

L0_CADIN_H0

E3

L0_CADIN_L0

E2

L0_CADOUT_H15 T4

L0_CADOUT_L15 T3

L0_CADOUT_H14 V5

L0_CADOUT_L14 U5

L0_CADOUT_H13 V4

L0_CADOUT_L13 V3

L0_CADOUT_H12 Y5

L0_CADOUT_L12 W5

L0_CADOUT_H11 AB5

L0_CADOUT_L11 AA5

L0_CADOUT_H10 AB4

L0_CADOUT_L10 AB3

L0_CADOUT_H9 AD5

L0_CADOUT_L9 AC5

L0_CADOUT_H8 AD4

L0_CADOUT_L8 AD3

L0_CADOUT_H7 T1

L0_CADOUT_L7 R1

L0_CADOUT_H6 U2

L0_CADOUT_L6 U3

L0_CADOUT_H5 V1

L0_CADOUT_L5 U1

L0_CADOUT_H4 W2

L0_CADOUT_L4 W3

L0_CADOUT_H3 AA2

L0_CADOUT_L3 AA3

L0_CADOUT_H2 AB1

L0_CADOUT_L2 AA1

L0_CADOUT_H1 AC2

L0_CADOUT_L1 AC3

L0_CADOUT_H0 AD1

L0_CADOUT_L0 AC1

L0_CLKIN_H1

J5

L0_CLKIN_L1

K5

L0_CLKIN_H0

J3

L0_CLKIN_L0

J2

L0_CTLIN_H1

P3

L0_CTLIN_L1

P4

L0_CTLIN_H0

N1

L0_CTLIN_L0

P1

L0_CLKOUT_H1 Y4

L0_CLKOUT_L1 Y3

L0_CLKOUT_H0 Y1

L0_CLKOUT_L0 W1

L0_CTLOUT_H1 T5

L0_CTLOUT_L1 R5

L0_CTLOUT_H0 R2

L0_CTLOUT_L0 R3

JP2

ACES_88231-02001

CONN@

1

1

2

2

GND

3

GND

4

D1

CH751H-40PT_SOD323-2

2 1

C7 4.7U_0805_10V4Z

1 2

S

G

D

Q1

SI3456BDV-T1-E3_TSOP6

3

6

2

4 5

1

C9

0.1U_0402_16V4Z

1

2

C8

4.7U_0805_10V4Z

1

2

C3

0.22U_0603_16V4Z

1

2

C2

4.7U_0805_10V4Z

1

2

C5

180P_0402_50V8J

1

2

D2

RLZ5.1B_LL34

@

12

C6

180P_0402_50V8J

1

2

C4

0.22U_0603_16V4Z

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+MCH_REF

DDR_B_MA10

DDR_B_MA7

DDR_B_MA1

DDR_B_MA12

DDR_B_MA6

DDR_B_MA11

DDR_B_MA0

DDR_B_MA9

DDR_B_MA15

DDR_B_MA3

DDR_B_MA5

DDR_B_MA8

DDR_B_MA13

DDR_B_MA2

DDR_B_MA4

DDR_CKE1_DIMMB

DDR_B_D0

DDR_CKE0_DIMMB

DDR_B_DQS6

DDR_B_DQS#6

DDR_B_DQS2

DDR_B_DQS#2

DDR_B_DQS5

DDR_B_DQS#5

DDR_B_DQS1

DDR_B_DQS#1

DDR_B_DQS4

DDR_B_DQS#4

DDR_B_DQS0

DDR_B_DQS#0

DDR_B_DQS7

DDR_B_DQS#7

DDR_B_DQS3

DDR_B_DQS#3

DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK0

DDR_B_CLK#0

DDR_B_CLK1

DDR_B_CLK#1

DDR_A_DQS0

DDR_A_DQS#0

DDR_A_DQS3

DDR_A_DQS#3

DDR_A_DQS2

DDR_A_DQS#2

DDR_A_DQS1

DDR_A_DQS#1

DDR_A_DQS4

DDR_A_DQS#4

DDR_A_DQS5

DDR_A_DQS#5

DDR_A_DQS6

DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_DQS7

VTT_SENSE

DDR_A_CLK0

DDR_A_CLK#0

+MCH_REF

DDR_B_ODT0

DDR_B_ODT1

DDR_A_ODT1

DDR_A_ODT0

DDR_B_CLK#0

DDR_B_CLK0

DDR_B_CLK1

DDR_B_CLK#1DDR_A_CLK#1

DDR_A_CLK#0

DDR_A_CLK0

DDR_A_CLK1

DDR_CKE0_DIMMA

DDR_CKE1_DIMMA

DDR_B_D28

DDR_B_D16

DDR_B_D22

DDR_B_D19

DDR_B_D9

DDR_B_D50

DDR_B_D35

DDR_B_D46

DDR_B_D5

DDR_B_D37

DDR_B_D26

DDR_B_D3

DDR_B_D8

DDR_B_D29

DDR_B_D14

DDR_B_D7

DDR_B_D59

DDR_B_D51

DDR_B_D10

DDR_B_D17

DDR_B_D44

DDR_B_D41

DDR_B_D38

DDR_B_D47

DDR_B_D63

DDR_B_D32

DDR_B_D20

DDR_B_D52

DDR_B_D30

DDR_B_D53

DDR_B_D40

DDR_B_D27

DDR_B_D45

DDR_B_D55

DDR_B_D56

DDR_B_D11

DDR_B_D48

DDR_B_D39

DDR_B_D1

DDR_B_D42

DDR_B_D36

DDR_B_D2

DDR_B_D58

DDR_B_D33

DDR_B_D62

DDR_B_D31

DDR_B_D21

DDR_B_D54

DDR_B_D24

DDR_B_D15

DDR_B_D60

DDR_B_D12

DDR_B_D49

DDR_B_D43

DDR_B_D18

DDR_B_D61

DDR_B_D34

DDR_B_D4

DDR_B_DM6

DDR_B_DM4

DDR_B_DM2

DDR_B_DM0

DDR_B_DM5

DDR_B_DM3

DDR_B_DM1

DDR_B_DM7

DDR_A_DM6

DDR_A_DM5

DDR_A_DM4

DDR_A_DM3

DDR_A_DM2

DDR_A_DM1

DDR_A_DM0

DDR_A_DM7

DDR_A_D59

DDR_A_D3

DDR_A_D13

DDR_A_D60

DDR_A_D40

DDR_A_D29

DDR_A_D56

DDR_A_D20

DDR_A_D28

DDR_A_D36

DDR_A_D19

DDR_A_D23

DDR_A_D34

DDR_A_D61

DDR_A_D15

DDR_A_D4

DDR_A_D0

DDR_A_D53

DDR_A_D47

DDR_A_D43

DDR_A_D33

DDR_A_D24

DDR_A_D39

DDR_A_D46

DDR_A_D22

DDR_A_D51

DDR_A_D9

DDR_A_D5

DDR_A_D6

DDR_A_D54

DDR_A_D8

DDR_A_D31

DDR_A_D7

DDR_A_D50

DDR_A_D57

DDR_A_D12

DDR_A_D21

DDR_A_D26

DDR_A_D63

DDR_A_D62

DDR_A_D42

DDR_A_D48

DDR_A_D44

DDR_A_D25

DDR_A_D58

DDR_A_D32

DDR_A_D1

DDR_A_D17

DDR_A_D2

DDR_A_D55

DDR_A_D38

DDR_A_D11

DDR_A_D10

DDR_A_D27

DDR_A_D18

DDR_A_D14

DDR_A_D41

DDR_A_D49

DDR_A_D16

DDR_A_D52

DDR_A_D37

DDR_A_D35

DDR_A_D30

DDR_B_D6

DDR_A_D45

DDR_B_RAS#

DDR_B_CAS#

DDR_B_WE#

DDR_B_BS#0

DDR_B_BS#1

DDR_B_BS#2

DDR_A_WE#

DDR_B_D25

DDR_A_CAS#

DDR_A_RAS#

DDR_B_D23

DDR_B_D57

DDR_B_D13

DDR_A_BS#2

DDR_A_BS#1

DDR_A_BS#0

DDR_A_MA15

DDR_A_MA12

DDR_A_MA14

DDR_A_MA13

DDR_A_MA11

DDR_A_MA10

DDR_A_MA6

DDR_A_MA1

DDR_A_MA7

DDR_A_MA2

DDR_A_MA3

DDR_A_MA8

DDR_A_MA5

DDR_A_MA4

DDR_A_MA9

DDR_A_MA0

DDR_B_MA14

DDR_CS1_DIMMA# DDR_CS0_DIMMB#

DDR_CS1_DIMMB#

DDR_CS0_DIMMA#

DDR_CKE1_DIMMB <9>

DDR_CKE0_DIMMB <9>

DDR_CS0_DIMMA#<8>

DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>

DDR_CS1_DIMMB# <9>

DDR_B_D[63..0]<9>

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>

DDR_A_D[63..0] <8>

DDR_B_DQS7<9>

DDR_B_DQS#7<9>

DDR_B_DQS6<9>

DDR_B_DQS5<9>

DDR_B_DQS4<9>

DDR_B_DQS3<9>

DDR_B_DQS2<9>

DDR_B_DQS1<9>

DDR_B_DQS0<9>

DDR_B_DQS#6<9>

DDR_B_DQS#5<9>

DDR_B_DQS#4<9>

DDR_B_DQS#3<9>

DDR_B_DQS#2<9>

DDR_B_DQS#1<9>

DDR_B_DQS#0<9>

DDR_A_DQS3 <8>

DDR_A_DQS2 <8>

DDR_A_DQS1 <8>

DDR_A_DQS0 <8>

DDR_A_DQS#3 <8>

DDR_A_DQS#2 <8>

DDR_A_DQS#1 <8>

DDR_A_DQS#0 <8>

DDR_A_DQS4 <8>

DDR_A_DQS#4 <8>

DDR_A_DQS5 <8>

DDR_A_DQS#5 <8>

DDR_A_DQS6 <8>

DDR_A_DQS#6 <8>

DDR_A_DQS7 <8>

DDR_A_DQS#7 <8>

DDR_B_RAS# <9>

DDR_B_CAS# <9>

DDR_B_WE# <9>

DDR_B_BS#0 <9>

DDR_B_BS#1 <9>

DDR_B_BS#2 <9>

DDR_A_RAS#<8>

DDR_A_CAS#<8>

DDR_A_WE#<8>

DDR_A_BS#0<8>

DDR_A_BS#1<8>

DDR_A_BS#2<8>

DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>

DDR_B_ODT0 <9>

DDR_B_ODT1 <9>

DDR_A_ODT0<8>

DDR_A_ODT1<8>

DDR_B_CLK0 <9>

DDR_B_CLK#0 <9>

DDR_B_CLK1 <9>

DDR_B_CLK#1 <9>

DDR_A_CLK0<8>

DDR_A_CLK#0<8>

DDR_A_CLK1<8>

DDR_A_CLK#1<8>

DDR_CKE0_DIMMA<8>

DDR_CKE1_DIMMA<8>

+1.8V

+0.9V+0.9V

+1.8V

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

AMD CPU S1G2 DDRII I/F

Custom

5 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH

Athlon 64 S1

Processor

Socket

Athlon 64 S1

Processor Socket

Place them close to CPU within 1"

Processor DDR2 Memory Interface

T1PAD

C11

1.5P_0402_50V9C

1

2

R2

1K_0402_1%

1 2

C12

0.1U_0402_16V4Z

1

2

T3PAD

R1

1K_0402_1%

1 2

T2 PAD

R4 39.2_0402_1%

1 2

MEM:DATA

JC PUC

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

MB_DATA63

AD11 MB_DATA62

AF11 MB_DATA61

AF14 MB_DATA60

AE14 MB_DATA59

Y11 MB_DATA58

AB11 MB_DATA57

AC12 MB_DATA56

AF13 MB_DATA55

AF15 MB_DATA54

AF16 MB_DATA53

AC18 MB_DATA52

AF19 MB_DATA51

AD14 MB_DATA50

AC14 MB_DATA49

AE18 MB_DATA48

AD18 MB_DATA47

AD20 MB_DATA46

AC20 MB_DATA45

AF23 MB_DATA44

AF24 MB_DATA43

AF20 MB_DATA42

AE20 MB_DATA41

AD22 MB_DATA40

AC22 MB_DATA39

AE25 MB_DATA38

AD26 MB_DATA37

AA25 MB_DATA36

AA26 MB_DATA35

AE24 MB_DATA34

AD24 MB_DATA33

AA23 MB_DATA32

AA24 MB_DATA31

G24 MB_DATA30

G23 MB_DATA29

D26 MB_DATA28

C26 MB_DATA27

G26 MB_DATA26

G25 MB_DATA25

E24 MB_DATA24

E23 MB_DATA23

C24 MB_DATA22

B24 MB_DATA21

C20 MB_DATA20

B20 MB_DATA19

C25 MB_DATA18

D24 MB_DATA17

A21 MB_DATA16

D20 MB_DATA15

D18 MB_DATA14

C18 MB_DATA13

D14 MB_DATA12

C14 MB_DATA11

A20 MB_DATA10

A19 MB_DATA9

A16 MB_DATA8

A15 MB_DATA7

A13 MB_DATA6

D12 MB_DATA5

E11 MB_DATA4

G11 MB_DATA3

B14 MB_DATA2

A14 MB_DATA1

A11 MB_DATA0

C11

MA_DATA63 AA12

MA_DATA62 AB12

MA_DATA61 AA14

MA_DATA60 AB14

MA_DATA59 W11

MA_DATA58 Y12

MA_DATA57 AD13

MA_DATA56 AB13

MA_DATA55 AD15

MA_DATA54 AB15

MA_DATA53 AB17

MA_DATA52 Y17

MA_DATA51 Y14

MA_DATA50 W14

MA_DATA49 W16

MA_DATA48 AD17

MA_DATA47 Y18

MA_DATA46 AD19

MA_DATA45 AD21

MA_DATA44 AB21

MA_DATA43 AB18

MA_DATA42 AA18

MA_DATA41 AA20

MA_DATA40 Y20

MA_DATA39 AA22

MA_DATA38 Y22

MA_DATA37 W21

MA_DATA36 W22

MA_DATA35 AA21

MA_DATA34 AB22

MA_DATA33 AB24

MA_DATA32 Y24

MA_DATA31 H22

MA_DATA30 H20

MA_DATA29 E22

MA_DATA28 E21

MA_DATA27 J19

MA_DATA26 H24

MA_DATA25 F22

MA_DATA24 F20

MA_DATA23 C23

MA_DATA22 B22

MA_DATA21 F18

MA_DATA20 E18

MA_DATA19 E20

MA_DATA18 D22

MA_DATA17 C19

MA_DATA16 G18

MA_DATA15 G17

MA_DATA14 C17

MA_DATA13 F14

MA_DATA12 E14

MA_DATA11 H17

MA_DATA10 E17

MA_DATA9 E15

MA_DATA8 H15

MA_DATA7 E13

MA_DATA6 C13

MA_DATA5 H12

MA_DATA4 H11

MA_DATA3 G14

MA_DATA2 H14

MA_DATA1 F12

MA_DATA0 G12

MB_DM7

AD12 MB_DM6

AC16 MB_DM5

AE22 MB_DM4

AB26 MB_DM3

E25 MB_DM2

A22 MB_DM1

B16 MB_DM0

A12

MB_DQS_H7

AF12

MB_DQS_L7

AE12

MB_DQS_H6

AE16

MB_DQS_L6

AD16

MB_DQS_H5

AF21

MB_DQS_L5

AF22

MB_DQS_H4

AC25

MB_DQS_L4

AC26

MB_DQS_H3

F26

MB_DQS_L3

E26

MB_DQS_H2

A24

MB_DQS_L2

A23

MB_DQS_H1

D16

MB_DQS_L1

C16

MB_DQS_H0

C12

MB_DQS_L0

B12

MA_DM7 Y13

MA_DM6 AB16

MA_DM5 Y19

MA_DM4 AC24

MA_DM3 F24

MA_DM2 E19

MA_DM1 C15

MA_DM0 E12

MA_DQS_H7 W12

MA_DQS_L7 W13

MA_DQS_H6 Y15

MA_DQS_L6 W15

MA_DQS_H5 AB19

MA_DQS_L5 AB20

MA_DQS_H4 AD23

MA_DQS_L4 AC23

MA_DQS_H3 G22

MA_DQS_L3 G21

MA_DQS_H2 C22

MA_DQS_L2 C21

MA_DQS_H1 G16

MA_DQS_L1 G15

MA_DQS_H0 G13

MA_DQS_L0 H13

R3 39.2_0402_1%

1 2

MEM:CMD/CTRL/CLK

JCPUB

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

VTT1

D10

VTT2

C10

VTT3

B10

VTT4

AD10

VTT5 W10

VTT6 AC10

VTT7 AB10

VTT8 AA10

VTT9 A10

MA1_ODT1

V19 MA1_ODT0

U21 MA0_ODT1

V22 MA0_ODT0

T19

MB1_ODT0 Y26

MB0_ODT1 W23

MB0_ODT0 W26

RSVD_M2 B18

MB1_CS_L0 U22

MB0_CS_L1 W25

MB0_CS_L0 V26

MA0_CS_L1

U19

MA1_CS_L1

V20 MA1_CS_L0

U20

MA0_CS_L0

T20

MA_ADD15

K19 MA_ADD14

K24 MA_ADD13

V24 MA_ADD12

K20 MA_ADD11

L22 MA_ADD10

R21 MA_ADD9

K22 MA_ADD8

L19 MA_ADD7

L21 MA_ADD6

M24 MA_ADD5

L20 MA_ADD4

M22 MA_ADD3

M19 MA_ADD2

N22 MA_ADD1

M20 MA_ADD0

N21

MA_BANK2

J21 MA_BANK1

R23 MA_BANK0

R20

MA_RAS_L

R19

MA_CAS_L

T22

MA_WE_L

T24

MEMZP

AF10

MEMZN

AE10 VTT_SENSE Y10

MEMVREF W17

MA_CLK_H4

P19

MA_CLK_L4

P20

MA_CLK_H7

Y16

MA_CLK_L7

AA16

MA_CLK_H1

E16

MA_CLK_L1

F16

MA_CLK_H5

N19

MA_CLK_L5

N20

MB_CLK_H4 R26

MB_CLK_L4 R25

MB_CLK_H7 AF18

MB_CLK_L7 AF17

MB_CLK_H1 A17

MB_CLK_L1 A18

MB_CLK_H5 P22

MB_CLK_L5 R22

MA_CKE0

J22

MA_CKE1

J20 MB_CKE0 J25

MB_CKE1 H26

MB_ADD15 J24

MB_ADD14 J23

MB_ADD13 W24

MB_ADD12 L25

MB_ADD11 L26

MB_ADD10 T26

MB_ADD9 K26

MB_ADD8 M26

MB_ADD7 L24

MB_ADD6 N25

MB_ADD5 L23

MB_ADD4 N26

MB_ADD3 N23

MB_ADD2 P26

MB_ADD1 N24

MB_ADD0 P24

MB_BANK2 J26

MB_BANK1 U26

MB_BANK0 R24

MB_RAS_L U25

MB_CAS_L U24

MB_WE_L U23

RSVD_M1

H16

C13

1000P_0402_25V8J

1

2

C15

1.5P_0402_50V9C

1

2

C10

1.5P_0402_50V9C

1

2

C14

1.5P_0402_50V9C

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

THERMDA_CPU

THERMDC_CPU

CPU_DBRDY

CPU_TDO

CPU_TMS

CPU_TCK

CPU_TDI

CPU_TRST#

CPU_DBREQ#

HDT_RST#

LDT_RST#

CPU_VDD1_FB_H

CPU_THERMTRIP#_R

VDD_NB_FB_H

CPU_VDD0_FB_L

VDD_NB_FB_LCPU_VDD1_FB_L

VDD_NB_FB_H

VDD_NB_FB_L

CPU_HTREF0

CPU_HTREF1

CPU_TEST25_L_BYPASSCLK_L

CPU_DBRDY

CPU_TMS

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST19_PLLTEST0

CPU_CLKIN_SC_P

CPU_THERMTRIP#_R

LDT_RST#

H_PW RGD_CPU

LDT_STOP#

THERMDA_CPU

LDT_STOP#

THERMDC_CPU

CPU_SID

CPU_SIC

CPU_LDT_REQ#

CPU_CLKIN_SC_N

CPU_VDD0_FB_H

CPU_TDI

CPU_TRST#

CPU_TCK

CPU_DBREQ#

CPU_TDO

CPU_SVC

CPU_SVD

CPU_TEST12_SCANSHIFTENB

CPU_TEST20_SCANCLK2

CPU_TEST21_SCANEN

CPU_TEST24_SCANCLK1

CPU_TEST22_SCANSHIFTEN

CPU_TEST29_L_FBCLKOUT_N

CPU_TEST29_H_FBCLKOUT_P

CPU_TEST17_BP3

CPU_TEST16_BP2

CPU_TEST14_BP0

CPU_TEST15_BP1

CPU_TEST28_L_PLLCHRZ_N

CPU_TEST28_H_PLLCHRZ_P

H_PW RGD_CPU

LDT_RST#

CPU_TEST23_TSTUPD

CPU_MEMHOT#_1.8V

CPU_LDT_REQ#

CPU_TEST27_SINGLECHAIN

CPU_PROCHOT#_1.8

CPU_TEST18_PLLTEST1

C PU _ PR O C HOT# _1. 8

CPU_VDD0_FB_H

CPU_VDD0_FB_L

CPU_VDD1_FB_H

CPU_VDD1_FB_L

CPU_TEST21_SCANEN

CPU_TEST27_SINGLECHAIN

CPU_TEST18_PLLTEST1

CPU_TEST19_PLLTEST0

CPU_TEST15_BP1

CPU_TEST20_SCANCLK2

CPU_TEST22_SCANSHIFTEN

CPU_TEST12_SCANSHIFTENB

CPU_TEST24_SCANCLK1

CPU_TEST14_BP0

CPU_SVD

CPU_SVC

SMB_EC_CK1

SMB_EC_DA1CPU_SID

CPU_SIC

SB_PWRGD <20,33,43>

CPU_SVD <43>

CPU_SVC <43>

H_PW RGD_CPU<19>

LDT_RST#<19>

LDT_STOP#<11,19>

VDD_NB_FB_H <43>

VDD_NB_FB_L <43>

CPU_VDD0_FB_H<43>

CPU_VDD0_FB_L<43>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

CPU_LDT_REQ# <11,19>

H_THERMTRIP# <20>

EN0 <37,39>

H_PROCHOT# <19>

H_THERMTRIP#_EC <33>

SMB_EC_CK2 <33>

SMB_EC_DA2 <33>

SMB_EC_CK1 <32,33,34,37>

SMB_EC_DA1 <32,33,34,37>

+3VS

+1.8V

+3VS

+1.8V

+1.2V_HT

+2.5VDDA

+2.5VS

+1.8VS

+1.8VS

+1.8VS

+1.8VS

+CPU_CORE_NB

+1.8V

+1.8V

+CPU_CORE_0

+CPU_CORE_0

+1.8V

+1.8V

+3VS

+1.8V

+1.8V

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

AMD CPU S1G2 CTRL

Custom

6 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

2200p change to

100p

Address:100_1101

HDT Connector

NOTE: HDT TERMINATION IS REQUIRED

FOR REV. Ax SILICON ONLY.

Address:100_1100

+1.8V sense no support

0718 AMD , need check with AMD

0718 Silego -- 216 ohm

Place close to CPU wihtin 1.5"

VDDA=300mA

as short as possible

route as differential

testpoint under package

Close to CPU

Close to CPU

9/20 S P020016900

0718 AMD --> 1K ohm

FDV301N, the Vgs is:

min = 0.65V

Typ = 0.85V

Max = 1.5V

EC is PU to 5VALW

2.09V for Gate

02/12 Remove R59.

02/15 Follow Trinity design.

02/15 Change R18 and R19

from 390 to 2.2K ohm.

02/27 Change net name to EN0.

03/04 Reserve R175, R814, C939, Q127 and Q129.

Reserve the R488 and R489 for S1G3 CPU

R484 10_0402_5%

1 2

R175

20K_0402_5%

@

12

T11 PAD

R38220_0402_5%@

12

R5 300_0402_5%

1 2

+

C16

100U_D2_10VM

@

1

2

T10PAD

C174.7U_0805_10V4Z

1

2

R13 44.2_0402_1%

1 2

R22 1K_0402_5%

1 2

G

D

S

Q129

FDV301N_NL_SOT23-3

@

2

13

C20

3900P_0402_50V7K

1 2

C19

0.22U_0603_16V4Z

1

2

R33 300_0402_5%@

12

C

B

E

Q3

PMBT3904_SOT23

1

2

3

R40220_0402_5%@

12

R11 10K_0402_5%@

12

C23

0.1U_0402_16V7K

1

2

R8

169_0402_1%

12

L1

FBM_L11_201209_300L_0805

1 2

SAMTEC_ASP-68200-07

JP3

CONN@

2

4

6

8

10

12

14

16

18

20

22

2423

21

19

17

15

13

11

9

7

5

3

1

26

R14 44.2_0402_1%

1 2

R23 1K_0402_5%

1 2

R6 0_0402_5%@

1 2

R486 10_0402_5%

1 2

R16 0_0402_5%

1 2

T5PAD

E

B

C

Q2

MMBT3904_NL_SOT23-3@

2

3 1

R7 0_0402_5%

1 2

C18

3300P_0402_50V7K

1

2

U2

ADM1032ARMZ-2REEL_MSOP8

VDD

1

ALERT# 6

THERM#

4GND 5

D+

2

D-

3

SCLK 8

SDATA 7

R814

34.8K_0402_1%~N

@

12

R29 300_0402_5%@

12

R36

300_0402_5%

1 2

T12PAD

C27

100P_0402_25V8K

C22

0.01U_0402_25V4Z

@

1

2

U1

NC7SZ08P5X_NL_SC70-5@

B2

A1

Y

4

P5

G

3

R9 300_0402_5%

1 2

C24

0.01U_0402_25V4Z

@

1

2

C939 0.1U_0402_16V4Z

@

1 2

R25 0_0402_5%

1 2

R28 300_0402_5%

12

R489 10_0402_5%@

1 2

R488 10_0402_5% @

1 2

R27 300_0402_5%@

12

C21 3900P_0402_50V7K

1 2

T6PAD

T42PAD

G

D

S

Q127

FDV301N_NL_SOT23-3

@

2

13

R59 0_0402_5%@

1 2

R19

2.2K_0402_5%

12

T7PAD

R31 300_0402_5%@

12

JC PUD

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

VDDA1

F8

VDDA2

F9

RESET_L

B7

PWROK

A7

LDTSTOP_L

F10

SIC

AF4

SID

AF5

HT_REF1

P6 HT_REF0

R6

VDD0_FB_H

F6

VDD0_FB_L

E6 VDDIO_FB_H W9

VDDIO_FB_L Y9

THERMTRIP_L AF6

PROCHOT_L AC7

RSVD2

A5

LDTREQ_L

C6

SVC A6

SVD A4

RSVD6 C5

RSVD4

B5

RSVD1

A3

CLKIN_H

A9

CLKIN_L

A8

DBRDY

G10

TMS

AA9

TCK

AC9

TRST_L

AD9

TDI

AF9

DBREQ_L E10

TDO AE9

TEST25_H

E9

TEST25_L

E8

TEST19

G9 TEST18

H10

RSVD8 AA7

TEST9

C2

TEST17 D7

TEST16 E7

TEST15 F7

TEST14 C7

TEST12

AC8

TEST7 C3

TEST6

AA6

THERMDC W7

THERMDA W8

VDD1_FB_H

Y6

VDD1_FB_L

AB6

TEST29_H C9

TEST29_L C8

TEST24

AE7

TEST23

AD7

TEST22

AE8

TEST21

AB8

TEST20

AF7

TEST28_H J7

TEST28_L H8

TEST27

AF8

ALERT_L

AE6

TEST10 K8

TEST8 C4

RSVD3

B3

RSVD5

C1

VDDNB_FB_H H6

VDDNB_FB_L G6

RSVD7 D5

KEY2 W18

MEMHOT_L AA8

RSVD10 H18

RSVD9 H19

KEY1 M11

R24 300_0402_5%@

1 2

R30

300_0402_5%

1 2

T13PAD

T4 PAD

R39220_0402_5%@

12

R37220_0402_5%@

12

R15

300_0402_5%

1 2

T9 PAD

C25

0.01U_0402_25V4Z

@

1

2

R10 10K_0402_5%

1 2

R485 10_0402_5%

1 2

R17

300_0402_5%@

12

T14PAD

R32 300_0402_5%@

12

R487 10_0402_5%

1 2

R35 300_0402_5%@

12

R18

2.2K_0402_5%

12

T43PAD

R26 300_0402_5%

1 2

T8PAD

R34 300_0402_5%@

12

R21

300_0402_5%

1 2

R41300_0402_5%

12

C26

0.1U_0402_16V4Z

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+0.9V

+CPU_CORE_0

+CPU_CORE_0

+CPU_CORE_0

+1.8V

+1.8V

+1.8V

+1.8V +1.8V

+0.9V

+0.9V

+CPU_CORE_NB

+1.8V

+1.8V

+CPU_CORE_0

+CPU_CORE_0

+CPU_CORE_0

+CPU_CORE_NB

+CPU_CORE_0+CPU_CORE_0

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

AMD CPU S1G2 PWR & GND

Custom

7 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

A: Add C165 and C176

to follow AMD Layout

review recommand for

EMI

Between CPU Socket and DIMM

180PF Qt'y follow the distance between

CPU socket and DIMM0. <2.5inch>

Under CPU Socket

Athlon 64 S1

Processor Socket

Near CPU Socket

VTT decoupling.

VDD(+CPU_CORE) decoupling.

VDDIO decoupling.

+CPU_CORE_NB decoupling.

C: Change to NBO CAP

C: Change to NBO CAP

Under CPU Socket

Near CPU Socket Right side.

Near CPU Socket Left side.

Near Power Supply

Athlon 64 S1

Processor Socket

L

18A/720mil/36vias

L

4A/160mil/8vias

L

3A/120mil/6vias

Tigris platform will be 4A

01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0

01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0

C40

0.22U_0603_16V4Z

1

2

+

C29

330U_X_2VM_R6M

1

2

C33

22U_0805_6.3V6M

1

2

C65

180P_0402_50V8J

1

2

C73

180P_0402_50V8J

1

2

C75

4.7U_0805_10V4Z

1

2

C85

180P_0402_50V8J

1

2

C32

22U_0805_6.3V6M

1

2

C43

0.22U_0603_16V4Z

1

2

C45

180P_0402_50V8J

1

2

C54

22U_0805_6.3V6M

@

1

2

C71

1000P_0402_25V8J

1

2

C46

22U_0805_6.3V6M

1

2

C44

0.01U_0402_25V4Z

1

2

+

C28

330U_X_2VM_R6M

1

2

C47

22U_0805_6.3V6M

1

2

C69

0.22U_0603_16V4Z

1

2

C56

0.22U_0603_16V4Z

1

2

C55

0.22U_0603_16V4Z

1

2

C48

0.22U_0603_16V4Z

1

2

C36

22U_0805_6.3V6M

1

2

C79

4.7U_0805_10V4Z

1

2

C52

22U_0805_6.3V6M

1

2

C41

0.01U_0402_25V4Z

1

2

C61

0.01U_0402_25V4Z

1

2

C86

180P_0402_50V8J

1

2

C58

0.22U_0603_16V4Z

1

2

C63

180P_0402_50V8J

1

2

JCPUE

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

VDD1_25 AC4

VDD1_26 AD2

VDD0_1

G4

VDD0_2

H2

VDD0_3

J9

VDD0_4

J11

VDD0_5

J13

VDD0_7

K6

VDD0_8

K10

VDD0_9

K12

VDD0_10

K14

VDD0_11

L4

VDD0_12

L7

VDD0_13

L9

VDD0_14

L11

VDD0_15

L13

VDD0_17

M2

VDD0_18

M6

VDD0_19

M8

VDD0_20

M10

VDD0_21

N7

VDD0_22

N9

VDD0_23

N11

VDD1_1 P8

VDD1_2 P10

VDD1_3 R4

VDD1_4 R7

VDD1_5 R9

VDD1_6 R11

VDD1_7 T2

VDD1_8 T6

VDD1_9 T8

VDD1_10 T10

VDD1_11 T12

VDD1_12 T14

VDD1_13 U7

VDD1_14 U9

VDD1_15 U11

VDD1_16 U13

VDD1_18 V6

VDD1_19 V8

VDD1_20 V10

VDD1_21 V12

VDD1_22 V14

VDD1_23 W4

VDD1_24 Y2

VDD0_6

J15

VDDNB_1

K16

VDD0_16

L15

VDDNB_2

M16

VDDNB_3

P16

VDDNB_4

T16

VDD1_17 U15

VDDNB_5

V16

VDDIO1

H25

VDDIO2

J17

VDDIO3

K18

VDDIO4

K21

VDDIO5

K23

VDDIO6

K25

VDDIO7

L17

VDDIO8

M18

VDDIO9

M21

VDDIO10

M23

VDDIO11

M25

VDDIO12

N17 VDDIO13 P18

VDDIO14 P21

VDDIO15 P23

VDDIO16 P25

VDDIO17 R17

VDDIO18 T18

VDDIO19 T21

VDDIO20 T23

VDDIO21 T25

VDDIO22 U17

VDDIO23 V18

VDDIO24 V21

VDDIO25 V23

VDDIO26 V25

VDDIO27 Y25

C38

22U_0805_6.3V6M

1

2

C68

0.22U_0603_16V4Z

1

2

C37

22U_0805_6.3V6M

1

2

C81

0.22U_0603_16V4Z

1

2

C64

180P_0402_50V8J

1

2

+

C59

220U_Y_4VM

1

2

C80

4.7U_0805_10V4Z

1

2

C84

1000P_0402_25V8J

1

2

C53

22U_0805_6.3V6M

1

2

C62

180P_0402_50V8J

1

2

C67

4.7U_0805_10V4Z

1

2

C82

0.22U_0603_16V4Z

1

2

C42

180P_0402_50V8J

1

2

C76

4.7U_0805_10V4Z

1

2

C74

4.7U_0805_10V4Z

1

2

C70

1000P_0402_25V8J

1

2

C39

22U_0805_6.3V6M

1

2

C51

180P_0402_50V8J

1

2

C34

22U_0805_6.3V6M

1

2

C66

4.7U_0805_10V4Z

1

2

C77

4.7U_0805_10V4Z

1

2

C57

0.22U_0603_16V4Z

1

2

C49

0.22U_0603_16V4Z

1

2

+

C78

220U_Y_4VM

@

1

2

+

C31

330U_X_2VM_R6M

1

2

JC P UF

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

VSS1

AA4

VSS2

AA11

VSS3

AA13

VSS4

AA15

VSS5

AA17

VSS6

AA19

VSS7

AB2

VSS8

AB7

VSS9

AB9

VSS10

AB23

VSS11

AB25

VSS12

AC11

VSS13

AC13

VSS14

AC15

VSS15

AC17

VSS16

AC19

VSS17

AC21

VSS18

AD6

VSS19

AD8

VSS20

AD25

VSS21

AE11

VSS22

AE13

VSS23

AE15

VSS24

AE17

VSS25

AE19

VSS26

AE21

VSS27

AE23

VSS28

B4

VSS29

B6

VSS30

B8

VSS31

B9

VSS32

B11

VSS33

B13

VSS34

B15

VSS35

B17

VSS36

B19

VSS37

B21

VSS38

B23

VSS39

B25

VSS40

D6

VSS41

D8

VSS42

D9

VSS43

D11

VSS44

D13

VSS45

D15

VSS46

D17

VSS47

D19

VSS48

D21

VSS49

D23

VSS50

D25

VSS51

E4

VSS52

F2

VSS53

F11

VSS54

F13

VSS55

F15

VSS56

F17

VSS57

F19

VSS58

F21

VSS59

F23

VSS60

F25

VSS61

H7

VSS62

H9

VSS63

H21

VSS64

H23

VSS65

J4

VSS66 J6

VSS67 J8

VSS68 J10

VSS69 J12

VSS70 J14

VSS71 J16

VSS72 J18

VSS73 K2

VSS74 K7

VSS75 K9

VSS76 K11

VSS77 K13

VSS78 K15

VSS79 K17

VSS80 L6

VSS81 L8

VSS82 L10

VSS83 L12

VSS84 L14

VSS85 L16

VSS86 L18

VSS87 M7

VSS88 M9

VSS89 AC6

VSS90 M17

VSS91 N4

VSS92 N8

VSS93 N10

VSS94 N16

VSS95 N18

VSS96 P2

VSS97 P7

VSS98 P9

VSS99 P11

VSS100 P17

VSS101 R8

VSS102 R10

VSS103 R16

VSS104 R18

VSS105 T7

VSS106 T9

VSS107 T11

VSS108 T13

VSS109 T15

VSS110 T17

VSS111 U4

VSS112 U6

VSS113 U8

VSS114 U10

VSS115 U12

VSS116 U14

VSS117 U16

VSS118 U18

VSS119 V2

VSS120 V7

VSS121 V9

VSS122 V11

VSS123 V13

VSS124 V15

VSS125 V17

VSS126 W6

VSS127 Y21

VSS128 Y23

VSS129 N6

C83

1000P_0402_25V8J

1

2

+

C30

330U_X_2VM_R6M

1

2

C60

0.01U_0402_25V4Z

1

2

C35

22U_0805_6.3V6M

1

2

C72

180P_0402_50V8J

1

2

C50

180P_0402_50V8J

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

DDR_CKE1_DIMMA

+V_DDR_MCH_REF

DDR_A_MA3

DDR_A_BS#0

DDR_A_RAS#

DDR_CS1_DIMMA#

DDR_CKE0_DIMMA

DDR_A_ODT1

DDR_A_WE#

DDR_A_D4

DDR_A_CAS# DDR_A_ODT0

DDR_CS0_DIMMA#

DDR_CKE1_DIMMA

DDR_A_D29

DDR_A_D30

DDR_A_D35

DDR_A_D26

DDR_A_D38

DDR_A_BS#0

DDR_A_D28

DDR_A_D34

DDR_A_D36

DDR_A_D33

DDR_A_D31

DDR_A_D32

DDR_A_D27

DDR_A_D53

DDR_A_D46

DDR_A_D43

DDR_A_D48

DDR_A_D41

DDR_A_D44

DDR_A_D50

DDR_A_D45

DDR_A_D49

DDR_A_D37

DDR_A_D55

DDR_A_D39

DDR_A_D51

DDR_A_D40

DDR_A_D47

DDR_A_D42

DDR_A_D63

DDR_A_D54

DDR_A_D6

DDR_A_D14

DDR_A_D52

DDR_A_D3

DDR_A_D59

DDR_A_D58

DDR_A_D9

DDR_A_D61

DDR_A_D60

DDR_A_D57

DDR_A_D7

DDR_A_D8

DDR_A_D56

DDR_A_D5

DDR_A_D24

DDR_A_D23

DDR_A_D12

DDR_A_D15

DDR_A_D21

DDR_A_BS#1

DDR_A_D22

DDR_A_D16 DDR_A_D20

DDR_A_BS#2

DDR_A_D10

DDR_A_D13

DDR_A_D19

DDR_A_D18

DDR_A_D17

DDR_A_D11

DDR_A_DM5

DDR_A_MA11

DDR_A_DM6

DDR_A_DM4

DDR_A_D0

DDR_A_DM7

DDR_A_D62

DDR_A_DM1

DDR_A_DM0

DDR_A_MA4

DDR_A_DM2

DDR_A_D25

DDR_A_D1

DDR_A_DM3

DDR_A_D2

DDR_A_MA8

DDR_A_MA12

DDR_A_MA14

DDR_A_MA9

DDR_A_MA10

DDR_A_DQS#0

DDR_A_MA13

DDR_A_MA1 DDR_A_MA0

DDR_A_MA2

DDR_A_MA7

DDR_A_MA15

DDR_A_MA3

DDR_A_MA5

DDR_A_MA6

DDR_A_DQS2

DDR_A_DQS6

DDR_A_DQS1

DDR_A_DQS0

DDR_A_DQS#6

DDR_A_DQS3

DDR_A_DQS#3

DDR_A_DQS4

DDR_A_DQS5

DDR_A_DQS#2

DDR_A_DQS7

DDR_A_DQS#4

DDR_A_DQS#7

DDR_A_DQS#5

DDR_A_DQS#1

DDR_A_MA4

DDR_A_MA11

DDR_A_MA12

DDR_A_MA5

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

+V_DDR_MCH_REF

DDR_A_MA15

DDR_A_BS#2

DDR_CKE0_DIMMA

DDR_A_MA7

DDR_A_MA6

DDR_A_MA14

DDR_A_MA0

DDR_A_BS#1

DDR_A_MA2

DDR_A_ODT0

DDR_A_MA13

DDR_A_RAS#

DDR_CS0_DIMMA#

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA1

DDR_A_CAS#

DDR_A_WE#

DDR_CS1_DIMMA#

DDR_A_ODT1

DDR_A_CLK0 <5>

DDR_A_CLK#0 <5>

DDR_CKE0_DIMMA<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5>

DDR_A_WE#<5>

DDR_A_CAS#<5>

DDR_CS1_DIMMA#<5>

DDR_A_ODT1<5>

DDR_A_CLK1 <5>

DDR_A_CLK#1 <5>

DDR_CS0_DIMMA# <5>

DDR_A_ODT0 <5>

DDR_A_RAS# <5>

DDR_A_BS#1 <5>

DDR_CKE1_DIMMA <5>

DDR_A_MA[0..15] <5>

DDR_A_D[0..63] <5>

DDR_A_DQS[0..7] <5>

DDR_A_DM[0..7] <5>

DDR_A_DQS#[0..7] <5>

SMB_CK_DAT0<9,15,20,30>

SMB_CK_CLK0<9,15,20,30>

+V_DDR_MCH_REF <9>

+1.8V+1.8V

+3VS

+1.8V

+1.8V

+0.9V

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

DDRII SO-DIMM 0

Custom

8 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

9/20 S P07000BZ00/SP07000EU00

DDR2 S OCKET H9.2 (REV)

Cross between +1.8V and +0.9V power plan

C101 0.1U_0402_16V4Z

1 2

C91 0.1U_0402_16V4Z

1 2

C97 0.1U_0402_16V4Z

1 2

C96

0.1U_0402_16V4Z

1

2

RP4

47_0804_8P4R_5%

18

27

36

45

C95

1000P_0402_25V8J

1

2

C102 0.1U_0402_16V4Z

1 2

C103

0.1U_0402_16V4Z

1

2

C87 0.1U_0402_16V4Z

1 2

C93 0.1U_0402_16V4Z

1 2

C100 0.1U_0402_16V4Z

1 2

RP3

47_0804_8P4R_5%

18

27

36

45

C90 0.1U_0402_16V4Z

1 2

C98 0.1U_0402_16V4Z

1 2

R43

1K_0402_1%

1 2

RP1

47_0804_8P4R_5%

18

27

36

45

RP2

47_0804_8P4R_5%

18

27

36

45

RP7

47_0804_8P4R_5%

18

27

36

45

C94 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

1 2

RP6

47_0804_8P4R_5%

18

27

36

45

C92 0.1U_0402_16V4Z

1 2

C89 0.1U_0402_16V4Z

1 2

RP5

47_0804_8P4R_5%

18

27

36

45

JP4

FOX_AS0A426-N8RN-7F

CONN@

VREF

1

VSS

3

DQ0

5

DQ1

7

VSS

9

DQS0#

11

DQS0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

VSS

41

DQ16

43

DQ17

45

VSS

47

DQS2#

49

DQS2

51

VSS

53

DQ18

55

DQ19

57

VSS

59

DQ24

61

DQ25

63

VSS

65

DM3

67

NC

69

VSS

71

DQ26

73

DQ27

75

VSS

77

CKE0

79

VDD

81

NC

83

BA2

85

VDD

87

A12

89

A9

91

A8

93

VDD

95

A5

97

A3

99

A1

101

VDD

103

A10/AP

105

BA0

107

WE#

109

VDD

111

CAS#

113

NC/S1#

115

VDD

117

NC/ODT1

119

VSS

121

DQ32

123

DQ33

125

VSS

127

DQS4#

129

DQS4

131

VSS

133

DQ34

135

DQ35

137

VSS

139

DQ40

141

DQ41

143

VSS

145

DM5

147

VSS

149

DQ42

151

DQ43

153

VSS

155

DQ48

157

DQ49

159

VSS

161

NC,TEST

163

VSS

165

DQS6#

167

DQS6

169

VSS

171

DQ50

173

DQ51

175

VSS

177

DQ56

179

DQ57

181

VSS

183

DM7

185

VSS

187

DQ58

189

DQ59

191

VSS

193

SDA

195

SCL

197

VDDSPD

199

VSS 2

DQ4 4

DQ5 6

VSS 8

DM0 10

VSS 12

DQ6 14

DQ7 16

VSS 18

DQ12 20

DQ13 22

VSS 24

DM1 26

VSS 28

CK0 30

CK0# 32

VSS 34

DQ14 36

DQ15 38

VSS 40

VSS 42

DQ20 44

DQ21 46

VSS 48

NC 50

DM2 52

VSS 54

DQ22 56

DQ23 58

VSS 60

DQ28 62

DQ29 64

VSS 66

DQS3# 68

DQS3 70

VSS 72

DQ30 74

DQ31 76

VSS 78

NC/CKE1 80

VDD 82

NC/A15 84

NC/A14 86

VDD 88

A11 90

A7 92

A6 94

VDD 96

A4 98

A2 100

A0 102

VDD 104

BA1 106

RAS# 108

S0# 110

VDD 112

ODT0 114

NC/A13 116

VDD 118

NC 120

VSS 122

DQ36 124

DQ37 126

VSS 128

DM4 130

VSS 132

DQ38 134

DQ39 136

VSS 138

DQ44 140

DQ45 142

VSS 144

DQS5# 146

DQS5 148

VSS 150

DQ46 152

DQ47 154

VSS 156

DQ52 158

DQ53 160

VSS 162

CK1 164

CK1# 166

VSS 168

DM6 170

VSS 172

DQ54 174

DQ55 176

VSS 178

DQ60 180

DQ61 182

VSS 184

DQS7# 186

DQS7 188

VSS 190

DQ62 192

DQ63 194

VSS 196

SA0 198

SA1 200

R44

1K_0402_1%

1 2

C88 0.1U_0402_16V4Z

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

DDR_B_BS#0

DDR_B_D26

DDR_B_D29

DDR_B_D27

DDR_B_D30

DDR_B_D33

DDR_B_D31

DDR_B_D32

DDR_B_D28

DDR_B_D34

DDR_B_D35

DDR_B_D38

DDR_B_D36

DDR_B_D39

DDR_B_D37

DDR_B_D41

DDR_B_D42

DDR_B_D44

DDR_B_D40

DDR_B_D43 DDR_B_D47

DDR_B_D48

DDR_B_D45

DDR_B_D46

DDR_B_D49 DDR_B_D53

DDR_B_D51 DDR_B_D55

DDR_B_D50

DDR_B_D52

DDR_B_D56

DDR_B_D54

DDR_B_D59

DDR_B_D57

DDR_B_D58

DDR_B_D61

DDR_B_D63

DDR_B_D60

DDR_B_D3

DDR_B_D8

DDR_B_D6

DDR_B_D7

DDR_B_D5

DDR_B_D14

DDR_B_D13

DDR_B_D11

DDR_B_D10

DDR_B_D9

DDR_B_D15

DDR_B_D12

DDR_B_D17

DDR_B_D20

DDR_B_D18 DDR_B_D22

DDR_B_D19

DDR_B_D24

DDR_B_D16

DDR_B_D23

DDR_B_BS#2

DDR_B_BS#1

DDR_B_D25

DDR_B_D62

DDR_B_DM7

DDR_B_DM2

DDR_B_DM4

DDR_B_DM3

DDR_B_DM1

DDR_B_DM0

DDR_B_DM6

DDR_B_DM5

DDR_B_MA4

DDR_B_D0

DDR_B_D2

DDR_B_D1

DDR_B_D4

DDR_B_MA11

DDR_B_MA10

DDR_B_MA12

DDR_B_MA9

DDR_B_MA6DDR_B_MA8

DDR_B_MA5

DDR_B_MA7

DDR_B_MA3

DDR_B_MA0

DDR_B_MA8

DDR_B_MA9

DDR_B_MA13

DDR_B_MA15

DDR_B_MA2

DDR_B_MA1

DDR_B_MA14

DDR_B_DQS2

DDR_B_DQS#0

DDR_B_DQS4

DDR_B_DQS0

DDR_B_DQS#1

DDR_B_DQS5

DDR_B_DQS7

DDR_B_DQS3

DDR_B_DQS6

DDR_B_DQS#7

DDR_B_DQS#4

DDR_B_DQS#2

DDR_B_DQS#6

DDR_B_DQS#3

DDR_B_DQS1

DDR_B_DQS#5

DDR_B_ODT1

DDR_CKE0_DIMMB

DDR_CS1_DIMMB#

DDR_B_RAS#

DDR_B_WE#

DDR_CKE1_DIMMB

DDR_B_CAS# DDR_B_ODT0

DDR_CS0_DIMMB#

DDR_B_MA12

DDR_B_MA5

DDR_B_MA4

DDR_B_D[0..63]

DDR_B_MA[0..15]

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_WE#

DDR_B_CAS#

DDR_CS1_DIMMB#

DDR_B_ODT1

DDR_B_MA3

DDR_B_MA1

DDR_B_BS#0

DDR_B_MA10

DDR_B_MA13

DDR_B_ODT0

DDR_B_BS#1

DDR_B_RAS#

DDR_CS0_DIMMB#

DDR_B_MA0

DDR_B_MA2

DDR_B_MA6

DDR_B_MA7

DDR_B_MA11

DDR_B_MA14

DDR_B_D21

DDR_B_MA15

DDR_CKE1_DIMMB

DDR_CKE0_DIMMB

DDR_B_BS#2

+V_DDR_MCH_REF<8>

DDR_B_CLK0 <5>

DDR_B_CLK#0 <5>

DDR_CKE0_DIMMB<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5>

DDR_B_WE#<5>

DDR_B_CAS#<5>

DDR_CS1_DIMMB#<5>

DDR_B_ODT1<5>

DDR_B_CLK1 <5>

DDR_B_CLK#1 <5>

DDR_B_ODT0 <5>

DDR_B_RAS# <5>

DDR_B_BS#1 <5>

DDR_CKE1_DIMMB <5>

DDR_CS0_DIMMB# <5>

DDR_B_MA[0..15] <5>

DDR_B_D[0..63] <5>

DDR_B_DQS[0..7] <5>

DDR_B_DM[0..7] <5>

DDR_B_DQS#[0..7] <5>

SMB_CK_DAT0<8,15,20,30>

SMB_CK_CLK0<8,15,20,30>

+1.8V+1.8V

+3VS

+0.9V

+3VS

+1.8V

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

DDRII SO-DIMM 1

Custom

9 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

9/20 S P07000ET00/SP07000GN00

Cross between +1.8V and +0.9V power plan

RP8

47_0804_8P4R_5%

18

27

36

45

RP14

47_0804_8P4R_5%

18

27

36

45

C108 0.1U_0402_16V4Z

12

RP10

47_0804_8P4R_5%

18

27

36

45

C105 0.1U_0402_16V4Z

12

C113 0.1U_0402_16V4Z

1 2

C114 0.1U_0402_16V4Z

12

RP11

47_0804_8P4R_5%

18

27

36

45

C119

0.1U_0402_16V4Z

1

2

C107 0.1U_0402_16V4Z

1 2

C106 0.1U_0402_16V4Z

1 2

C104

1000P_0402_25V8J

1

2

C117 0.1U_0402_16V4Z

1 2

RP12

47_0804_8P4R_5%

18

27

36

45

C110 0.1U_0402_16V4Z

1 2

C111 0.1U_0402_16V4Z

12

JP5

TYCO_292527-4

CONN@

VREF

1

VSS

3

DQ0

5

DQ1

7

VSS

9

DQS0#

11

DQS0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

VSS

41

DQ16

43

DQ17

45

VSS

47

DQS2#

49

DQS2

51

VSS

53

DQ18

55

DQ19

57

VSS

59

DQ24

61

DQ25

63

VSS

65

DM3

67

NC

69

VSS

71

DQ26

73

DQ27

75

VSS

77

CKE0

79

VDD

81

NC

83

BA2

85

VDD

87

A12

89

A9

91

A8

93

VDD

95

A5

97

A3

99

A1

101

VDD

103

A10/AP

105

BA0

107

WE#

109

VDD

111

CAS#

113

NC/S1#

115

VDD

117

NC/ODT1

119

VSS

121

DQ32

123

DQ33

125

VSS

127

DQS4#

129

DQS4

131

VSS

133

DQ34

135

DQ35

137

VSS

139

DQ40

141

DQ41

143

VSS 2

DQ4 4

DQ5 6

VSS 8

DM0 10

VSS 12

DQ6 14

DQ7 16

VSS 18

DQ12 20

DQ13 22

VSS 24

DM1 26

VSS 28

CK0 30

CK0# 32

VSS 34

DQ14 36

DQ15 38

VSS 40

VSS 42

DQ20 44

DQ21 46

VSS 48

NC 50

DM2 52

VSS 54

DQ22 56

DQ23 58

VSS 60

DQ28 62

DQ29 64

VSS 66

DQS3# 68

DQS3 70

VSS 72

DQ30 74

DQ31 76

VSS 78

NC/CKE1 80

VDD 82

NC/A15 84

NC/A14 86

VDD 88

A11 90

A7 92

A6 94

VDD 96

A4 98

A2 100

A0 102

VDD 104

BA1 106

RAS# 108

S0# 110

VDD 112

ODT0 114

NC/A13 116

VDD 118

NC 120

VSS 122

DQ36 124

DQ37 126

VSS 128

DM4 130

VSS 132

DQ38 134

DQ39 136

VSS 138

DQ44 140

DQ45 142

VSS 144

VSS

145

DM5

147

VSS

149

DQ42

151

DQ43

153

VSS

155

DQ48

157

DQ49

159

VSS

161

NC,TEST

163

VSS

165

DQS6#

167

DQS6

169

VSS

171

DQ50

173

DQ51

175

VSS

177

DQ56

179

DQ57

181

VSS

183

DM7

185

VSS

187

DQ58

189

DQ59

191

VSS

193

SDA

195

SCL

197

VDDSPD

199

DQS5# 146

DQS5 148

VSS 150

DQ46 152

DQ47 154

VSS 156

DQ52 158

DQ53 160

VSS 162

CK1 164

CK1# 166

VSS 168

DM6 170

VSS 172

DQ54 174

DQ55 176

VSS 178

DQ60 180

DQ61 182

VSS 184

DQS7# 186

DQS7 188

VSS 190

DQ62 192

DQ63 194

VSS 196

SAO 198

SA1 200

GND 202

GND

201

C115 0.1U_0402_16V4Z

1 2

RP13

47_0804_8P4R_5%

18

27

36

45

C109 0.1U_0402_16V4Z

12

RP9

47_0804_8P4R_5%

18

27

36

45

C118 0.1U_0402_16V4Z

12

C112 0.1U_0402_16V4Z

1 2

C116 0.1U_0402_16V4Z

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

H_CADIN7

H_CADIN15

H_CTLIN1H_CTLON1

H_CADON7

H_CADON15

PCIE_ITX_PRX_P5

PCIE_ITX_PRX_N5

PCIE_ITX_PRX_P1

PCIE_ITX_PRX_N1

PCIE_ITX_PRX_P2

PCIE_ITX_PRX_N2

PCIE_ITX_PRX_P3

PCIE_ITX_PRX_N3

PCIE_ITX_PRX_P0

PCIE_ITX_PRX_N0

SB_TX2P_C

SB_TX2N_C

SB_TX3P_C

SB_TX3N_C

SB_TX0P_C

SB_TX0N_C

SB_TX1P_C

H_CADIN[0..15]

H_CADIP[0..15]H_CADOP[0..15]

H_CADON[0..15]

SB_TX1N_C

H_CADIP5

H_CADIN9

H_CADIN11

H_CTLIP1

H_CTLIP0

H_CADIN2

H_CADIP3

H_CADIN12

H_CADOP2

H_CADOP6

H_CADOP9

H_CADOP12

H_CADIN8

H_CADON4

H_CADIN5

H_CADIP8

H_CADIP11

H_CADIP14

H_CADOP0

H_CTLIN0

H_CADIN10

H_CADON1

H_CADOP13

H_CADIN1

H_CADIN3

H_CADIN4

H_CADIP10

H_CADIP13

H_CTLOP1

H_CADON5

H_CADON9

H_CADON13

H_CADIP0

H_CADIP7

H_CADON3

H_CADIP4

H_CADIP15

H_CADIN14

H_CTLOP0

H_CADIP2

H_CADOP1

H_CADON0

H_CADON10

H_CADON14

H_CADIP1

H_CADIP6

H_CTLON0

H_CADON2

H_CADOP5

H_CADOP10

H_CADOP3

H_CADOP7

H_CADON8

H_CADOP11

H_CADIP9

H_CADIP12

H_CADON11

H_CADOP14

H_CADIN6

H_CADOP4

H_CADIN0

H_CADIN13

H_CADON6

H_CADOP8

H_CADON12

H_CADOP15

PCIE_PTX_C_IRX_P5<26>

PCIE_PTX_C_IRX_N5<26>

H_CLKIN0 <4>

H_CLKIP0 <4>

H_CTLIN0 <4>

H_CTLIP0 <4>

H_CLKON0<4>

H_CLKOP0<4>

H_CLKOP1<4>

H_CLKON1<4>

H_CTLOP0<4>

H_CTLON0<4>

H_CLKIN1 <4>

H_CLKIP1 <4>

H_CTLIN1 <4>

H_CTLIP1 <4>H_CTLOP1<4>

H_CTLON1<4>

PCIE_ITX_C_PRX_P5 <26>

PCIE_ITX_C_PRX_N5 <26>

PCIE_ITX_C_PRX_N1 <27>

PCIE_ITX_C_PRX_P1 <27>

PCIE_ITX_C_PRX_P2 <26>

PCIE_ITX_C_PRX_N2 <26>

PCIE_ITX_C_PRX_P3 <25>

PCIE_ITX_C_PRX_N3 <25>

PCIE_ITX_C_PRX_P0 <26>

PCIE_ITX_C_PRX_N0 <26>

PCIE_PTX_C_IRX_P0<26>

PCIE_PTX_C_IRX_N0<26>

PCIE_PTX_C_IRX_P1<27>

PCIE_PTX_C_IRX_N1<27>

PCIE_PTX_C_IRX_P3<25>

PCIE_PTX_C_IRX_N3<25>

PCIE_PTX_C_IRX_P2<26>

PCIE_PTX_C_IRX_N2<26>

H_CADIP[0..15] <4>

H_CADON[0..15]<4> H_CADIN[0..15] <4>

H_CADOP[0..15]<4>

SB_RX1P<19>

SB_RX1N<19>

SB_RX0P<19>

SB_RX0N<19> SB_TX0P <19>

SB_TX1N <19>

SB_TX0N <19>

SB_TX1P <19>

SB_RX3P<19>

SB_RX3N<19>

SB_RX2P<19>

SB_RX2N<19> SB_TX2P <19>

SB_TX2N <19>

SB_TX3N <19>

SB_TX3P <19>

TMDS_B_CLK <18>

TMDS_B_CLK# <18>

TMDS_B_DATA0 <18>

TMDS_B_DATA0# <18>

TMDS_B_DATA1 <18>

TMDS_B_DATA1# <18>

TMDS_B_DATA2 <18>

TMDS_B_DATA2# <18>

+1.1VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

RS880-HT/PCIE

Custom

10 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

NEED CHECK R68 & R69 WITH AMD

0718 Place within 1"

layout 1:2

0718 Place within 1"

layout 1:2

LAN10/100

WLAN

New Card

CardReader

DP0

GFX_TX0,TX1,TX2 and TX3

RS780M Display Port Support (muxed on GFX)

DP1

GFX_TX4,TX5,TX6 and TX7

AUX0 and HPD0

AUX1 and HPD1

TV Tuner

9/20 S A00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH

C164 0.1U_0402_16V7K

1 2

C162 0.1U_0402_16V7K

1 2

C167 0.1U_0402_16V7K

1 2

PART 1 OF 6

HYPER TRANSPORT CPU I/F

U3A

RS880M_FCBGA528

HT_RXCAD15P

U19

HT_RXCAD15N

U18

HT_RXCAD14P

U20

HT_RXCAD14N

U21

HT_RXCAD13P

V21

HT_RXCAD13N

V20

HT_RXCAD12P

W21

HT_RXCAD12N

W20

HT_RXCAD11P

Y22

HT_RXCAD11N

Y23

HT_RXCAD10P

AA24

HT_RXCAD10N

AA25

HT_RXCAD9P

AB25

HT_RXCAD9N

AB24

HT_RXCAD8P

AC24

HT_RXCAD8N

AC25

HT_RXCAD7P

N24

HT_RXCAD7N

N25

HT_RXCAD6P

P25

HT_RXCAD6N

P24

HT_RXCAD5P

P22

HT_RXCAD5N

P23

HT_RXCAD4P

T25

HT_RXCAD4N

T24

HT_RXCAD3P

U24

HT_RXCAD3N

U25

HT_RXCAD2P

V25

HT_RXCAD2N

V24

HT_RXCAD1P

V22

HT_RXCAD1N

V23

HT_RXCAD0P

Y25

HT_RXCAD0N

Y24

HT_RXCLK1P

AB23

HT_RXCLK1N

AA22

HT_RXCLK0P

T22

HT_RXCLK0N

T23

HT_RXCTL0P

M22

HT_RXCTL0N

M23

HT_RXCTL1P

R21

HT_RXCTL1N

R20

HT_RXCALP

C23

HT_RXCALN

A24

HT_TXCAD15P P18

HT_TXCAD15N M18

HT_TXCAD14P M21

HT_TXCAD14N P21

HT_TXCAD13P M19

HT_TXCAD13N L18

HT_TXCAD12P L19

HT_TXCAD12N J19

HT_TXCAD11P J18

HT_TXCAD11N K17

HT_TXCAD10P J20

HT_TXCAD10N J21

HT_TXCAD9P G20

HT_TXCAD9N H21

HT_TXCAD8P F21

HT_TXCAD8N G21

HT_TXCAD7P K23

HT_TXCAD7N K22

HT_TXCAD6P K24

HT_TXCAD6N K25

HT_TXCAD5P J25

HT_TXCAD5N J24

HT_TXCAD4P H23

HT_TXCAD4N H22

HT_TXCAD3P F23

HT_TXCAD3N F22

HT_TXCAD2P F24

HT_TXCAD2N F25

HT_TXCAD1P E24

HT_TXCAD1N E25

HT_TXCAD0P D24

HT_TXCAD0N D25

HT_TXCLK1P L21

HT_TXCLK1N L20

HT_TXCLK0P H24

HT_TXCLK0N H25

HT_TXCTL0P M24

HT_TXCTL0N M25

HT_TXCTL1P P19

HT_TXCTL1N R18

HT_TXCALP B24

HT_TXCALN B25

C165 0.1U_0402_16V7K

1 2

C160 0.1U_0402_16V7K

1 2

C168 0.1U_0402_16V7K

1 2

C154 0.1U_0402_16V7K

1 2

C159 0.1U_0402_16V7K

1 2

R57 301_0402_1%

1 2

C169 0.1U_0402_16V7K

1 2

C152 0.1U_0402_16V7K

1 2

R58 301_0402_1%

1 2

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

U3B

RS880M_FCBGA528

SB_TX3P AD5

SB_TX3N AE5

GPP_TX2P AA2

GPP_TX2N AA1

GPP_TX3P Y1

GPP_TX3N Y2

SB_RX3P

W5

SB_RX3N

Y5

GPP_RX2P

AD1

GPP_RX2N

AD2

GPP_RX3P

V5

GPP_RX3N

W6

SB_TX0P AD7

SB_TX0N AE7

SB_TX1P AE6

SB_TX1N AD6

SB_RX0P

AA8

SB_RX0N

Y8

SB_RX1P

AA7

SB_RX1N

Y7

PCE_CALRP(PCE_BCALRP) AC8

PCE_CALRN(PCE_BCALRN) AB8

SB_TX2N AC6

SB_RX2P

AA5

SB_RX2N

AA6 SB_TX2P AB6

GPP_RX0P

AE3

GPP_RX0N

AD4

GPP_RX1P

AE2

GPP_RX1N

AD3

GPP_TX0P AC1

GPP_TX0N AC2

GPP_TX1P AB4

GPP_TX1N AB3

GFX_RX0P

D4

GFX_RX0N

C4

GFX_RX1P

A3

GFX_RX1N

B3

GFX_RX2P

C2

GFX_RX2N

C1

GFX_RX3P

E5

GFX_RX3N

F5

GFX_RX4P

G5

GFX_RX4N

G6

GFX_RX5P

H5

GFX_RX5N

H6

GFX_RX6P

J6

GFX_RX6N

J5

GFX_RX7P

J7

GFX_RX7N

J8

GFX_RX8P

L5

GFX_RX8N

L6

GFX_RX9P

M8

GFX_RX9N

L8

GFX_RX10P

P7

GFX_RX10N

M7

GFX_RX11P

P5

GFX_RX11N

M5

GFX_RX12P

R8

GFX_RX12N

P8

GFX_RX13P

R6

GFX_RX13N

R5

GFX_RX14P

P4

GFX_RX14N

P3

GFX_RX15P

T4

GFX_RX15N

T3

GFX_TX0P A5

GFX_TX0N B5

GFX_TX1P A4

GFX_TX1N B4

GFX_TX2P C3

GFX_TX2N B2

GFX_TX3P D1

GFX_TX3N D2

GFX_TX4P E2

GFX_TX4N E1

GFX_TX5P F4

GFX_TX5N F3

GFX_TX6P F1

GFX_TX6N F2

GFX_TX7P H4

GFX_TX7N H3

GFX_TX8P H1

GFX_TX8N H2

GFX_TX9P J2

GFX_TX9N J1

GFX_TX10P K4

GFX_TX10N K3

GFX_TX11P K1

GFX_TX11N K2

GFX_TX12P M4

GFX_TX12N M3

GFX_TX13P M1

GFX_TX13N M2

GFX_TX14P N2

GFX_TX14N N1

GFX_TX15P P1

GFX_TX15N P2

GPP_TX4P Y4

GPP_TX4N Y3

GPP_TX5P V1

GPP_TX5N V2

GPP_RX4P

U5

GPP_RX4N

U6

GPP_RX5P

U8

GPP_RX5N

U7

C155 0.1U_0402_16V7K

1 2

C161 0.1U_0402_16V7K

1 2

C163 0.1U_0402_16V7K

1 2

C156 0.1U_0402_16V7K

1 2

C157 0.1U_0402_16V7K

1 2

C166 0.1U_0402_16V7K

1 2

R55 1.27K_0402_1%

1 2

C158 0.1U_0402_16V7K

1 2

C153 0.1U_0402_16V7K

1 2

R56 2K_0402_1%

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+VDDA18HTPLL

+NB_HTPVDD

+AVDD2

NB_THERMAL_DC

NB_THERMAL_DA

TV_LUMA

NB_RESET#

+AVDD1

RED

BLUE

CRT_VSYNC

GREEN

CRT_HSYNC

NB_PWRGD

NB_ALLOW_LDTSTOP

NB_LDTSTOP#

+VDDLT18

TV_COMPS

TV_CRMA

+AVDDQ

+VDDLTP18

RED

GREEN

BLUE

+NB_PLLVDD

+VDDA18PCIEPLL

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

NB_PWM

ENBKL

UMA_CRT_CLK<16>

UMA_CRT_DAT<16>

HDMIDAT_UMA<18>

NB_PWRGD<20>

CRT_HSYNC<14,16>

CRT_VSYNC<14,16>

UMA_ENVDD <17>

NBGFX_CLK<15>

NBGFX_CLK#<15>

CLK_SBLINK_BCLK<15>

CLK_SBLINK_BCLK#<15>

HPD <18>

CLK_NBHT<15>

CLK_NBHT#<15>

PLT_RST#<14,19,25,26,27,32,33>

RED<16>

GREEN<16>

BLUE<16>

AUX_CAL<14>

RS780_DFT_GPIO_0<14> SUS_STAT# <20>

LVDS_A2+ <17>

LVDS_A0+ <17>

LVDS_A1+ <17>

LVDS_ACLK- <17>

HDMICLK_UMA<18>

LVDS_ACLK+ <17>

LVDS_A2- <17>

LVDS_A0- <17>

LVDS_A1- <17>

LCD_DDC_DAT<17>

LCD_DDC_CLK<17>

NB_OSC_14.318M<15>

LDT_STOP#<6,19>

CPU_LDT_REQ#<6,19>

SUS_STAT_R# <14>

ENBKL <33>

NB_PWM <17>

+3VS

+3VS

+1.8VS

+1.8VS

+1.8VS

+1.8VS

+1.8VS

+1.8VS

+1.1VS

+1.1VS

+1.8VS

+1.8VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

RS880 VEDIO/CLK GEN

Custom

11 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Strap pin

AVDD=100mA

Strap pin

PA_RS780A4

placement close to NB ball

NB temp to SB

Strap pin

L

0.08A/10mil/1vias

R

R73

R1072

R1085

R1086

Veri-Bright Non Veri-Bright

@

@

@

@

Ripely 2.0 support Veri-Bright function

R71

4.7K_0402_5%

1 2

T48 PAD

R64 150_0402_1%@

1 2

L10

BLM18PG121SN1D_0603

1 2

C179

2.2U_0603_6.3V4Z

1

2

R371 300_0402_5%

1 2

T46 PAD

T49PAD

L4

0_0603_5%

R65 715_0402_1%

1 2

L6

BLM18PG121SN1D_0603

1 2

R73

0_0402_5%

1 2

C180

2.2U_0603_6.3V4Z

1

2

R1072 100K_0402_5%

1 2

L11

BLM18PG121SN1D_0603

1 2

C175

2.2U_0603_6.3V4Z

1

2

L5

BLM18PG121SN1D_0603

1 2

R66 0_0402_5%

1 2

R72

4.7K_0402_5%

1 2

T50PAD

C1120

0.1U_0402_16V4Z

1

2

R77 0_0402_5%

1 2

C172

2.2U_0603_6.3V4Z

1

2

C171

2.2U_0603_6.3V4Z

1

2

L2

BLM18PG121SN1D_0603

1 2

T47 PAD

C178

2.2U_0603_6.3V4Z

1

2L3

BLM18PG121SN1D_0603

1 2

R67

0_0402_5%

1 2

R63 150_0402_1%@

1 2

PART 3 OF 6

PM

CLOCKs PLL PWR

MIS.

CRT/TVOUT

LVTM

U3C

RS880M_FCBGA528

VDDA18HTPLL

H17

SYSRESETb

D8

POWERGOOD

A10

LDTSTOPb

C10

ALLOW_LDTSTOP

C12

REFCLK_P/OSCIN(OSCIN)

E11

PLLVDD(NC)

A12

HPD(NC) D10

DDC_CLK0/AUX0P(NC)

A8 DDC_DATA0/AUX0N(NC)

B8

THERMALDIODE_P AE8

THERMALDIODE_N AD8

I2C_CLK

B9

STRP_DATA

B10

GFX_REFCLKP

T2

GFX_REFCLKN

T1

GPP_REFCLKP

U1

GPP_REFCLKN

U2

PLLVDD18(NC)

D14

PLLVSS(NC)

B12

TXOUT_L0P(NC) A22

TXOUT_L0N(NC) B22

TXOUT_L1P(NC) A21

TXOUT_L1N(NC) B21

TXOUT_L2P(NC) B20

TXOUT_L2N(DBG_GPIO0) A20

TXOUT_L3P(NC) A19

TXOUT_U0P(NC) B18

TXOUT_L3N(DBG_GPIO2) B19

TXOUT_U0N(NC) A18

TXOUT_U1P(PCIE_RESET_GPIO3) A17

TXOUT_U1N(PCIE_RESET_GPIO2) B17

TXOUT_U2P(NC) D20

TXOUT_U2N(NC) D21

TXOUT_U3P(PCIE_RESET_GPIO5) D18

TXOUT_U3N(NC) D19

TXCLK_LP(DBG_GPIO1) B16

TXCLK_LN(DBG_GPIO3) A16

TXCLK_UP(PCIE_RESET_GPIO4) D16

TXCLK_UN(PCIE_RESET_GPIO1) D17

VDDLTP18(NC) A13

VSSLTP18(NC) B13

C_Pr(DFT_GPIO5)

E17

Y(DFT_GPIO2)

F17

COMP_Pb(DFT_GPIO4)

F15

RED(DFT_GPIO0)

G18

TMDS_HPD(NC) D9

I2C_DATA

A9

TESTMODE D13

HT_REFCLKN

C24 HT_REFCLKP

C25

SUS_STAT#(PWM_GPIO5) D12

GREEN(DFT_GPIO1)

E18

BLUE(DFT_GPIO3)

E19

DAC_VSYNC(PWM_GPIO6)

B11 DAC_HSYNC(PWM_GPIO4)

A11

DAC_RSET(PWM_GPIO1)

G14

AVDD1(NC)

F12

AVDD2(NC)

E12

REDb(NC)

G17

GREENb(NC)

F18

AVDDDI(NC)

F14

AVSSDI(NC)

G15

AVDDQ(NC)

H15

AVSSQ(NC)

H14

VDDLT18_2(NC) B15

VDDLT33_1(NC) A14

VDDLT33_2(NC) B14

VSSLT1(VSS) C14

VSSLT2(VSS) D15

VDDLT18_1(NC) A15

VSSLT3(VSS) C16

VSSLT4(VSS) C18

VSSLT5(VSS) C20

LVDS_DIGON(PCE_TCALRP) E9

LVDS_BLON(PCE_RCALRP) F7

LVDS_ENA_BL(PWM_GPIO2) G12

VSSLT6(VSS) E20

VDDA18PCIEPLL1

D7

VDDA18PCIEPLL2

E7

BLUEb(NC)

F19

AUX_CAL(NC)

C8

GPPSB_REFCLKP(SB_REFCLKP)

V4

GPPSB_REFCLKN(SB_REFCLKN)

V3

DDC_DATA1/AUX1N(NC)

A7 DDC_CLK1/AUX1P(NC)

B7

DAC_SCL(PCE_RCALRN)

F8

DAC_SDA(PCE_TCALRN)

E8

REFCLK_N(PWM_GPIO3)

F11

VSSLT7(VSS) C22

RSVD

G11

R1086 100K_0402_5%@

1 2

L7

BLM18PG121SN1D_0603

1 2

C176

2.2U_0603_6.3V4Z

1

2

R80

1.8K_0402_5%

1 2

R1085 0_0402_5%@1 2

C173

0.1U_0402_16V4Z

1

2

C174

4.7U_0805_10V4Z

1

2

R88 10K_0402_5%

12

R62 150_0402_1%@

1 2

L9

BLM18PG121SN1D_0603

1 2

C170

2.2U_0603_6.3V4Z

1

2

R68

0_0402_5%

1 2

R69 0_0402_5%

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

MEM_DQS_P0

MEM_DQS_P1

MEM_DQS_N0

MEM_A9

MEM_A2

MEM_A12

MEM_DQ10

MEM_DQS_P0

+MEM_VREF

MEM_DQS_N0

MEM_ODT

MEM_DQS_P1

MEM_DM1

MEM_DQS_N1

MEM_DQ14

MEM_A2

MEM_DQ7

MEM_A8

MEM_DQ12

MEM_A1

+NB_IOPLLVDD

+1.8V_IOPLLVDD

MEM_A3

+MEM_VREF

MEM_A0

MEM_DQ4

MEM_DQ2

MEM_DQ5

MEM_DQ0

MEM_DQ6

MEM_DQ11

MEM_DQ1

MEM_A11

MEM_BA0

MEM_BA1

MEM_CKE

MEM_WE#

MEM_CS#

MEM_A4

MEM_DQS_N1

MEM_RAS#

MEM_CAS#

MEM_BA2

MEM_DM1

MEM_CLKP

MEM_CLKN

MEM_ODT

MEM_DM0

MEM_A10

MEM_DQ15

+MEM_VREF1

MEM_A11

MEM_A8

MEM_A9

MEM_CAS#

MEM_CS#

MEM_CLKN

MEM_CKE

MEM_RAS#

MEM_CLKP

MEM_WE#

MEM_DM0

MEM_BA0

MEM_A7

MEM_DQ13

+MEM_VREF1

MEM_A0

MEM_A10

MEM_BA2

MEM_A3

MEM_DQ8

MEM_BA1

MEM_A6

+VDDL

MEM_DQ9

MEM_A1

MEM_A6

MEM_A7

MEM_A4

MEM_A5

MEM_DQ3

MEM_DQ2

MEM_DQ0

MEM_DQ1

MEM_DQ3

MEM_DQ10

MEM_DQ7

MEM_DQ11

MEM_DQ8

MEM_DQ5

MEM_DQ6

MEM_DQ9

MEM_DQ15

MEM_DQ13

MEM_DQ14

MEM_DQ4

MEM_DQ12

MEM_A12

MEM_A5

MEM_COMP_P

MEM_COMP_N

+1.8VS

+1.8VS

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

+1.1VS

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

RS880 Side-Port DDR2 SDRAM

Custom

12 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Side Port disable,VREF need

connect to +1.8VS for DDR2

Layout Note: 50 mil for VSSDL

MEM_COMP_P and MEM_COMP_N trace

width >=10mils and 10mils spacing from

other Signals in X,Y,Z directions

220 ohm @ 100MHz,2A

9/20 S A000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P

02/15 Remove L96. 02/15 Change L12 and L13 from bead to 0 ohm resistor.

Support 8M x 16bit x 8 bank side port

SBD_MEM/DVO_I/F

PAR 4 OF 6

U3D

RS880M_FCBGA528

MEM_A0(NC)

AB12

MEM_A1(NC)

AE16

MEM_A2(NC)

V11

MEM_A3(NC)

AE15

MEM_A4(NC)

AA12

MEM_A5(NC)

AB16

MEM_A6(NC)

AB14

MEM_A7(NC)

AD14

MEM_A8(NC)

AD13

MEM_A9(NC)

AD15

MEM_A10(NC)

AC16

MEM_A11(NC)

AE13

MEM_A12(NC)

AC14

MEM_A13(NC)

Y14

MEM_BA0(NC)

AD16

MEM_BA1(NC)

AE17

MEM_BA2(NC)

AD17

MEM_RASb(NC)

W12

MEM_CASb(NC)

Y12

MEM_WEb(NC)

AD18

MEM_CSb(NC)

AB13

MEM_CKE(NC)

AB18

MEM_ODT(NC)

V14

MEM_CKP(NC)

V15

MEM_CKN(NC)

W14

MEM_DM0(NC) W17

MEM_DM1/DVO_D8(NC) AE19

MEM_DQS0P/DVO_IDCKP(NC) Y17

MEM_DQS0N/DVO_IDCKN(NC) W18

MEM_DQS1P(NC) AD20

MEM_DQS1N(NC) AE21

MEM_DQ0/DVO_VSYNC(NC) AA18

MEM_DQ1/DVO_HSYNC(NC) AA20

MEM_DQ2/DVO_DE(NC) AA19

MEM_DQ3/DVO_D0(NC) Y19

MEM_DQ4(NC) V17

MEM_DQ5/DVO_D1(NC) AA17

MEM_DQ6/DVO_D2(NC) AA15

MEM_DQ7/DVO_D4(NC) Y15

MEM_DQ8/DVO_D3(NC) AC20

MEM_DQ9/DVO_D5(NC) AD19

MEM_DQ10/DVO_D6(NC) AE22

MEM_DQ11/DVO_D7(NC) AC18

MEM_DQ12(NC) AB20

MEM_DQ13/DVO_D9(NC) AD22

MEM_DQ14/DVO_D10(NC) AC22

MEM_DQ15/DVO_D11(NC) AD21

MEM_COMPP(NC)

AE12

MEM_COMPN(NC)

AD12 MEM_VREF(NC) AE18

IOPLLVDD18(NC) AE23

IOPLLVSS(NC) AD23

IOPLLVDD(NC) AE24

C202

0.1U_0402_16V4Z

1

2

R97

1K_0402_1%

1 2

C184

1U_0603_10V6K

1

2

C607

1U_0402_6.3V4Z

1

2

C182

0.1U_0402_16V4Z

1

2

C195

0.1U_0402_16V4Z

1

2

R99

1K_0402_1%

1 2

L15

0_0805_5%

1 2

R92 40.2_0402_1%

12

R96

1K_0402_1%

1 2

C196

0.1U_0402_16V4Z

1

2

C181

2.2U_0603_6.3V4Z

1

2

C203

22U_0805_6.3V6M

1

2

C201

0.1U_0402_16V4Z

1

2

C608

1U_0402_6.3V4Z

1

2

R93 40.2_0402_1%

12

L12

0_0603_5%

1 2

R98

1K_0402_1%

1 2

U61

HY5PS561621AFP-25_FBGA84

VREF

J2

LDM

F3

UDM

B3

DQ14 B1

DQ13 D9

DQ12 D1

DQ11 D3

DQ10 D7

DQ9 C2

DQ8 C8

DQ7 F9

DQ6 F1

DQ5 H9

DQ4 H1

DQ3 H3

DQ2 H7

DQ1 G2

DQ0 G8

BA1

L3 BA0

L2

A11

P7

A10/AP

M2

A9

P3

A8

P8

A7

P2

A6

N7

A5

N3

A4

N8

A3

N2

A0

M8 A1

M3 A2

M7

RAS

K7

CKE

K2

ODT

K9

CS

L8

CAS

L7

CK

J8 CK

K8

WE

K3 VDDQ G9

VDDQ A9

VDDQ C1

VDDQ C3

VDDQ C7

VDDQ C9

VDDQ E9

VDDQ G1

VSSQ A7

VSSQ B2

VSSQ B8

VSSQ D2

VSSQ D8

VSSQ E7

VSSQ F2

VSSQ F8

VSSQ H2

VSSQ H8

VSS A3

VSS E3

VSS J3

VSS N1

VSS P9

UDQS

A8 UDQS

B7

LDQS

E8 LDQS

F7

VDDQ G3

VDDQ G7

VDD A1

VDD E1

VDD J9

VDD M9

VDD R1

A12

R2

DQ15 B9

VDDL J1

VSSDL J7

NC

R8

NC

A2

NC

L1

NC

R3

NC

R7

NC

E2

C200

0.1U_0402_16V4Z

1

2

C199

0.1U_0402_16V4Z

1

2

C183

2.2U_0603_6.3V4Z

1

2

L13

0_0603_5%

1 2

R91

100_0402_1%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+VDDA11PCIE

+VDDHTRX

+VDDHT

+VDDA18PCIE

+VREF1.35V

+1.8V_VDD_SP

+VDDHTTX

VLDT_EN#<36>

+1.1VS

+1.8VS

+1.1VS +NB_VDDC

+1.8VS

+3VS

+1.8VS

+1.2V_HT

+1.1VS

+3VS

+1.8VS

+1.35VS

+1.8VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

RS880 PWR/GND

Custom

13 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

2A

2A

2A

2A

VDDA_12=2.5A

VDD_CORE=5A

L

Just for RS780M A11 version boot issue

L

0.6A/50mil/4vias

L

0.45A/40mil/3vias

L

0.5A/50mil/4vias

L

0.25A/30mil/2vias

L

0.7A/60mil/4vias

L

7A/280mil/16vias

L

0.15A/30mil/2vias

C2470.1U_0402_16V4Z

1

2

C239

0.1U_0402_16V4Z

1

2

C238

0.1U_0402_16V4Z

1

2

C1067

10U_0805_10V4Z@

1

2

C216

0.1U_0402_16V4Z

1

2

G

D

S

Q163

2N7002_SOT23-3@

2

13

C215

4.7U_0805_10V4Z

1

2

C2420.1U_0402_16V4Z

1

2

L22

0_0805_5%

12

C2440.1U_0402_16V4Z

1

2

L16

0_0805_5%

12

C248 0.1U_0402_16V4Z

12

C217

0.1U_0402_16V4Z

1

2

PART 5/6

POWER

U3E

RS880M_FCBGA528

VDDHT_1

J17

VDDHT_2

K16

VDDHT_3

L16

VDDHT_4

M16

VDDHT_5

P16

VDDHT_6

R16

VDDHT_7

T16

VDDHTTX_1

AE25

VDDHTTX_2

AD24

VDDHTTX_3

AC23

VDDHTTX_4

AB22

VDDHTTX_5

AA21

VDDHTTX_6

Y20

VDDHTTX_7

W19

VDDHTTX_8

V18

VDDHTRX_1

H18

VDDHTRX_2

G19

VDDHTRX_3

F20

VDDHTRX_4

E21

VDDHTRX_5

D22

VDD18_1

F9

VDD18_2

G9

VDD18_MEM1(NC)

AE11

VDD18_MEM2(NC)

AD11

VDDA18PCIE_1

J10

VDDA18PCIE_2

P10

VDDA18PCIE_3

K10

VDDA18PCIE_10

Y9

VDDA18PCIE_11

AA9

VDDA18PCIE_12

AB9

VDDA18PCIE_13

AD9

VDDA18PCIE_14

AE9

VDDA18PCIE_6

W9

VDDA18PCIE_7

H9

VDDPCIE_1 A6

VDDPCIE_2 B6

VDDPCIE_3 C6

VDDPCIE_4 D6

VDDPCIE_5 E6

VDDPCIE_6 F6

VDDPCIE_7 G7

VDDPCIE_8 H8

VDDPCIE_9 J9

VDDA18PCIE_4

M10

VDDA18PCIE_5

L10

VDDC_1 K12

VDDC_2 J14

VDDC_3 U16

VDDPCIE_11 M9

VDDC_4 J11

VDDC_5 K15

VDDPCIE_10 K9

VDDC_6 M12

VDDC_7 L14

VDDC_8 L11

VDDC_9 M13

VDDC_10 M15

VDDC_11 N12

VDDC_12 N14

VDDC_13 P11

VDDC_14 P13

VDDC_15 P14

VDDC_16 R12

VDDC_17 R15

VDDC_18 T11

VDDC_19 T15

VDDC_20 U12

VDDC_21 T14

VDD33_1(NC) H11

VDD33_2(NC) H12

VDD_MEM1(NC) AE10

VDD_MEM2(NC) AA11

VDD_MEM3(NC) Y11

VDD_MEM4(NC) AD10

VDD_MEM6(NC) AC10

VDD_MEM5(NC) AB10

VDDA18PCIE_8

T10

VDDC_22 J16

VDDPCIE_12 L9

VDDA18PCIE_9

R10

VDDPCIE_13 P9

VDDPCIE_14 R9

VDDPCIE_15 T9

VDDPCIE_16 V9

VDDPCIE_17 U9

VDDA18PCIE_15

U10

VDDHTRX_6

B23

VDDHTRX_7

A23

VDDHTTX_9

U17

VDDHTTX_10

T17

VDDHTTX_11

R17

VDDHTTX_12

P17

VDDHTTX_13

M17

C598 0.1U_0402_16V4Z

12

+

C234

330U_D2E_2.5VM_R15

1

2

C228

0.1U_0402_16V4Z

1

2

C218

0.1U_0402_16V4Z

1

2

C597 0.1U_0402_16V4Z

12

C1064

10U_0805_10V4Z@

1

2

C2310.1U_0402_16V4Z

1

2

C2500.1U_0402_16V4Z

1 2

C209

4.7U_0805_10V4Z

1

2

C223 0.1U_0402_16V4Z

12

C237

0.1U_0402_16V4Z

1

2

C23310U_0805_10V4Z

1

2

C222 1U_0402_6.3V4Z

1 2

C236

0.1U_0402_16V4Z

1

2

R1051 0_0603_5%

1 2

R1017 0_0402_5%@

1 2

C2300.1U_0402_16V4Z

1

2

R1016

3K_0402_5%@

12

L18

0_0805_5%

12

L17

FBMA-L11-201209-221LMA30T_0805

1 2

C251

1U_0402_6.3V4Z

1

2

U64

G2992F1U_SO8@

VOUT

4

NC 5

GND

2

VREF

3

VIN

1VCNTL 6

NC 7

NC 8

TP 9

C246

4.7U_0805_10V4Z

1

2

C599 0.1U_0402_16V4Z

12

C2410.1U_0402_16V4Z

1

2

C229

0.1U_0402_16V4Z

1

2

C214

0.1U_0402_16V4Z

1

2

C208

0.1U_0402_16V4Z

1

2

C224 0.1U_0402_16V4Z

12

PJP604

PAD-OPEN 4x4m

1 2

C225

4.7U_0805_10V4Z

1

2

PART 6/6

GROUND

U3F

RS880M_FCBGA528

VSSAHT1

A25

VSSAHT2

D23

VSSAHT3

E22

VSSAHT4

G22

VSSAHT5

G24

VSSAHT6

G25

VSSAHT7

H19

VSSAHT8

J22

VSSAHT9

L17

VSSAHT10

L22

VSSAHT11

L24

VSSAHT12

L25

VSSAHT13

M20

VSSAHT14

N22

VSSAHT15

P20

VSSAHT16

R19

VSSAHT17

R22

VSSAHT18

R24

VSSAHT19

R25

VSSAHT21

U22

VSSAHT22

V19

VSSAHT23

W22

VSSAHT24

W24

VSSAHT25

W25

VSSAHT26

Y21

VSSAHT27

AD25

VSS2 D11

VSS3 G8

VSS4 E14

VSS5 E15

VSS7 J12

VSS8 K14

VSS9 M11

VSS10 L15

VSS11

L12

VSS12

M14

VSS13

N13

VSS14

P12

VSS15

P15

VSS16

R11

VSS17

R14

VSS18

T12

VSS19

U14

VSS20

U11

VSS21

U15

VSS22

V12

VSS23

W11

VSS24

W15

VSS25

AC12

VSS26

AA14

VSS27

Y18

VSS28

AB11

VSS29

AB15

VSS30

AB17

VSS31

AB19

VSS32

AE20

VSSAPCIE1 A2

VSSAPCIE2 B1

VSSAPCIE3 D3

VSSAPCIE4 D5

VSSAPCIE5 E4

VSSAPCIE6 G1

VSSAPCIE7 G2

VSSAPCIE8 G4

VSSAPCIE9 H7

VSSAPCIE10 J4

VSSAPCIE11 R7

VSSAPCIE12 L1

VSSAPCIE13 L2

VSSAPCIE14 L4

VSSAPCIE15 L7

VSS34

K11

VSSAPCIE16 M6

VSSAPCIE17 N4

VSSAPCIE18 P6

VSSAPCIE19 R1

VSSAPCIE20 R2

VSSAPCIE21 R4

VSSAPCIE22 V7

VSSAPCIE23 U4

VSSAPCIE24 V8

VSSAPCIE25 V6

VSSAPCIE26 W1

VSSAPCIE27 W2

VSSAPCIE28 W4

VSSAPCIE29 W7

VSSAPCIE30 W8

VSSAPCIE31 Y6

VSSAPCIE32 AA4

VSSAPCIE33 AB5

VSSAPCIE34 AB1

VSSAPCIE35 AB7

VSSAPCIE36 AC3

VSSAPCIE37 AC4

VSSAPCIE38 AE1

VSSAPCIE39 AE4

VSSAPCIE40 AB2

VSS1 AE14

VSSAHT20

H20

VSS33

AB21

VSS6 J15

C252

1U_0402_6.3V4Z

1

2

C249 4.7U_0805_10V4Z

12

R1015

1K_0402_1%

@

12

C206

0.1U_0402_16V4Z

1

2

L19

0_0805_5%

12

C235

4.7U_0805_10V4Z

1

2

C212 10U_0805_10V4Z

C2320.1U_0402_16V4Z

1

2

C2400.1U_0402_16V4Z

1

2

C227

0.1U_0402_16V4Z

1

2

C2530.1U_0402_16V4Z

1 2

C219 1U_0402_6.3V4Z

1 2

C1068

0.1U_0402_16V7K@

1

2

C220 1U_0402_6.3V4Z

1 2

C1066

0.1U_0402_16V7K@

1

2

C221 1U_0402_6.3V4Z

1 2

C211 10U_0805_10V4Z

C226

0.1U_0402_16V4Z

1

2

C210

0.1U_0402_16V4Z

1

2

C2430.1U_0402_16V4Z

1

2

C1065

1U_0603_10V6K@

1

2

C207

0.1U_0402_16V4Z

1

2

C24510U_0805_10V4Z

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SUS_STAT_R#<11> PLT_RST# <11,19,25,26,27,32,33>

RS780_DFT_GPIO_0<11>

CRT_HSYNC<11,16>

CRT_VSYNC<11,16>

AUX_CAL<11>

+3VS

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

RS880 STRAPS

Custom

14 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS740/RS780)

0 : Enable (RS740/RS780)

RX780: Enables the Test Debug Bus using PCIE bus

1 : Disable ( Can still be enabled using nbcfg register access )

0 : Enable

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

Enables the Test Debug Bus using GPIO.

1 : Disable (RS780) Enable (RX780)

0 : Enable (RS780) Disable (RX780)

PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Selects Loading of STRAPS from EPROM

1 : Bypass the loading of EEPROM straps and use Hardware Default Values

0 : I2C Master can load strap values from EEPROM if connected, or use

default values if not connected

RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

DFT_GPIO1: LOAD_EEPROM_STRAPS

RS780 use HSYNC to enable SIDE PORT (internal pull high)

RS780 DFT_GPIO1

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K

R102 1K_0402_5%@

12

R107 3K_0402_5%

12

R101 1K_0402_5%

12

D4 CH751H-40PT_SOD323-2@

2 1

R105 1K_0402_5%@

12

R104 150_0402_1%@

1 2

R1064 3K_0402_5%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

CLKREQ_MCARD2#

CLK_XTAL_OUT

CLK_XTAL_IN

CLKREQ_NCARD#

CLKREQ_MCARD2#

CLK_48M_USB_R

CLK_XTAL_IN

CLK_XTAL_OUT

NB_OSC_14.318M_R

SEL_SATA

27M_SEL

SEL_SATA

27M_SEL

CLK_CPU_BCLK_R

CLK_CPU_BCLK#_R

CLKREQ_NCARD#

CLKREQ_MCARD1#

CLKREQ_MCARD1#

CLKREQ_LAN#

CLKREQ_LAN#

CLKREQ4

CLKREQ4

CLK_48M_USB

NB_OSC_14.318M

CLK_14M_SIO

CLK_PCIE_MCARD0# <27>

CLK_PCIE_MCARD0 <27>

NB_OSC_14.318M <11>

CLK_PCIE_MCARD2<26>

CLK_PCIE_MCARD2#<26>

CLK_PCIE_MCARD1#<26>

CLK_PCIE_MCARD1<26>

CLK_CPU_BCLK# <6>

CLK_CPU_BCLK <6>

NBGFX_CLK <11>

NBGFX_CLK# <11>

CLK_PCIE_NCARD <26>

CLK_PCIE_NCARD# <26>

CLKREQ_NCARD# <26>

CLKREQ_MCARD2# <26>

SMB_CK_CLK0<8,9,20,30>

SMB_CK_DAT0<8,9,20,30>

CLK_NBHT# <11>

CLK_NBHT <11>

CLK_48M_USB <20>

CLK_PCIE_LAN <25>

CLK_PCIE_LAN# <25>

CLK_SBLINK_BCLK#<11>

CLK_SBLINK_BCLK<11> CLK_SBSRC_BCLK# <19>

CLK_SBSRC_BCLK <19>

CLKREQ_MCARD1# <26>

CLKREQ_LAN# <25>

CLK_14M_SB <19>

+3VS_CLK

+VDDCLK_IO

+3VS_CLK

+3VS_CLK

+VDDCLK_IO

+3VS_CLK

+3VS_CLK

+3VS_CLK

+3VS_CLK

+VDDCLK_IO

+1.2V_HT

+3VS_CLK

+3VS_CLK

+3VS_CLK

+3VS_CLK

+3VS_CLK

+3VS_CLK

+3VS_CLK

+VDDCLK_IO

+VDDCLK_IO

+VDDCLK_IO

+3VS_CLK

+3VS_CLK

+3VS

+3VS_CLK

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

Clock generator

Custom

15 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

100M DIFF(IN/OUT)*

HT_REFCLKP

RX780 RS780

NB CLOCK INPUT TABLE

100M DIFF

100M DIFF

100M DIFF

100M DIFF

14M SE (1.8V) 14M SE (1.1V)

NB CLOCKS

NC vr ef

HT_REFCLKN

REFCLK_P

REFCLK_N

GFX_REFCLK 100M DIFF

Card Reader

SEL_SATA

* default

configure as normal SRC(SRC_6) output

1

*

0

configure as SATA output

MiniCard_2

CPU

MiniCard_1

GLAN

New Card

configure as single-ended 66MHz output1

*0 configure as differential 100MHz output

NB

NB GFX

configure as 27M and 27M_SS output

NB_OSC_14.318M

1 *

0 con f igure as SRC_7 output

* default

RS780

1.8V 75R/100RRX780

1.1V 200R/100R

OSC_14M_NB

27M_SEL

PA_RS7X0A1

* default

Routing the trace at least 10mil

SB LINK SB SRC

Use voltage divider resistor R379 & R380 to pull low

PA_RS7X0A1

For IC S need to pull high.

For SL G is NC

EMI Caps for single end clock.

01/23 14.318MHz For SB710 reference

C446

0.1U_0402_16V4Z

1

2

C451

1U_0402_6.3V4Z

@

1

2

C461

0.1U_0402_16V4Z

1

2

C447

0.1U_0402_16V4Z

1

2

Y2

14.31818MHZ_20P_6X1430004201

12

C453

0.1U_0402_16V4Z

1

2

R324 8.2K_0402_5%

1 2

R325 8.2K_0402_5%

1 2

R326 8.2K_0402_5%

1 2

C450

0.1U_0402_16V4Z

1

2

SLG8SP626VTR_QFN72_10x10

U10

VDD_CPU 54

VDD_CPU_I/O 53

VSS_CPU 52

CLKREQ_1# 51

CLKREQ_2# 50

VDD_A 49

VSS_SRC

19

SRC_1#

20

SRC_1

21

SRC_0#

22

SRC_0

23

CLKREQ_0#

24

ATIGCLK_2#

25

ATIGCLK_2

26

VSS_ATIG

27

VDD_ATIG_IO

28

VDD_ATIG

29

ATIGCLK_1#

30

ATIGCLK_1

31

ATIGCLK_0#

32

VSS_SB_SRC

36 SB_SRC_1

35 SB_SRC_1#

34 ATIGCLK_0

33

VSS_A 48

VSS_SATA 47

SRC_6/SATA 46

SRC_6#/SATA# 45

VDD_SATA 44

CLKREQ_3# 43

CLKREQ_4# 42

SB_SRC_SLOW# 41

SB_SRC_0 40

SB_SRC_0# 39

VDD_SB_SRC 38

VDD_SB_SRC_IO 37

REF_1/SEL_SATA 64

REF_2/SEL_27 63

VDD_REF 62

VDD_HTT 61

HTT_0/66M_0 60

HTT_0#/66M_1 59

VSS_HTT 58

PD# 57

CPU_K8_0 56

CPU_K8_0# 55

SCL

1

SDA

2

VDD_DOT

3

SRC_7#/27M

4

SRC_7/27M_SS

5

VSS_DOT

6

SRC_5#

7

SRC_5

8

SRC_4#

9

SRC_4

10

VSS_SRC

11

VDD_SRC_IO

12

SRC_3#

13

SRC_3

14

SRC_2#

15

SRC_2

16

VDD_SRC

17

VDD_SRC_IO

18

REF_0/SEL_HTT66 65

VSS_REF 66

XTAL_IN 67

XTAL_OUT 68

VDD_48 69

48MHz_1 70

48MHz_0 71

VSS_48 72

GND 73

C465

22P_0402_50V8J

1

2

R379 158_0402_1%

1 2

C460

0.1U_0402_16V4Z

1

2

R372 10K_0402_5%

1 2

R186

261_0402_1%@

1 2

R1106

110_0402_5%

C464

22P_0402_50V8J

1

2

C455

0.1U_0402_16V4Z

1

2

R946 0_0402_1%

1 2

R179

8.2K_0402_5%

@

1 2

R1045 8.2K_0402_5%@

1 2

C1075

12P_0402_50V8J

1

2

R168

0_0805_5%

1 2 C448

0.1U_0402_16V4Z

1

2

R1105 75_0402_1%

@

1 2

R174 8.2K_0402_5%

1 2

C452

10U_0805_10V4Z

1

2

C458

0.1U_0402_16V4Z

1

2

R945 0_0402_1%

1 2

C449

0.1U_0402_16V4Z

1

2

R380

90.9_0402_1%

1 2

R180

8.2K_0402_5%

1 2

C457

0.1U_0402_16V4Z

1

2

C459

0.1U_0402_16V4Z

1

2

C445

0.1U_0402_16V4Z

1

2

R170 33_0402_5% 1 2

C1076

12P_0402_50V8J

1

2

R181

8.2K_0402_5%

1 2

C1123

1U_0402_6.3V4Z

1 2

R167

0_0805_5%

1 2

C1106

0.1U_0603_25V7K

1

2

C1074

12P_0402_50V8J

1

2

R1039 8.2K_0402_5%

1 2

C444

10U_0805_10V4Z

1

2

C454

0.1U_0402_16V4Z

1

2

C456

0.1U_0402_16V4Z

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

GREEN_L

D_DDCCLK

D_DDCDATA

H S YNC

VSYNC

BLUE_L

GREEN

RED

BLUE

RED_L

D_HSYNC

D_DDCCLK

VSYNC

H S YNC

D_VSYNC

D_DDCDATA

D_HSYNC <35>

D_VS YNC <35>

RED_L <35>

GREEN_L <35>

BLUE_L <35>

RED<11>

GREEN<11>

BLUE<11>

UMA_CRT_CLK<11>

UMA_CRT_DAT<11> D_DDCDATA <35>

D_DDCCLK <35>

CRT_HSYNC<11,14>

CRT_VSYNC<11,14>

+3VS

+CRT_VCC

+CRT_VCC

+CRT_VCC+5VS

+CRT_VCC

+R_CRT_VCC

+3VS

+CRT_VCC

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

CRT Connector

Custom

16 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

CRT CONNECTOR

v0.2 ADD

v0.2 ADD

F2

1A_6VDC_MINISMDC110

21

C475

0.1U_0402_16V4Z

1

2

U13

SN74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

JCRT

SUYIN_070546FR015S263ZRCONN@

RGND

6

ID0

11

Red

1

GGND

7

SDA

12

Green

2

BGND

8

Hsync

13

Blue

3

+5V

9

Vsync

14

res

4

SGND

10

SCL

15

GND

5

GND

16

GND

17

Q10A

2N7002DW-7-F_SOT363-6

61

2

C477

0.1U_0402_16V4Z

@

1 2

R211

75_0402_1%

12

L49

BLM15AG121SN1D_0402

1 2

L48

BLM15AG121SN1D_0402

1 2

C858

6P_0402_50V8K

1

2

R214

75_0402_1%

12

D35

DAN217_SC59

@

2

3

1

C469

6P_0402_50V8K

1

2

D37

DAN217_SC59

@

2

3

1

L47

BLM15AG121SN1D_0402

1 2

R100

6.8K_0402_5%

C857

470P_0402_50V8J

@

1

2

D36

RB491D_SOT23

2 1

U14

SN74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

R237

4.7K_0402_5%

12

C470

10P_0402_50V8J

@

1

2

C1107

0.1U_0603_25V7K

1

2

C856

470P_0402_50V8J

@

1

2

C859

6P_0402_50V8K

1

2

R1022 0_0402_5%@

1 2

R240 0_0603_5%

1 2

C476

6P_0402_50V8K

1

2

Q10B

2N7002DW-7-F_SOT363-6

3

5

4

R241 0_0603_5%

1 2

C474

10P_0402_50V8J

@

1

2

D34

DAN217_SC59

@

2

3

1

R217

75_0402_1%

12

R238

4.7K_0402_5%

1 2

R218

6.8K_0402_5%

C471

6P_0402_50V8K

1

2

C472

6P_0402_50V8K

1

2

C473

0.1U_0402_16V4Z

1 2

R1023 0_0402_5%@

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

LVDS_A1+

LVDS_A1-

BKOFF#

LVDS_A2+

LCD_DDC_DAT

DAC_BRIG

LVDS_A0+

LVDS_A0-

DMIC_CLK

DMIC_DAT

LVDS_A2-

LCD_DDC_DAT

LCD_DDC_CLK

LCD_DDC_CLK

BKOFF#

LVDS_ACLK-

LVDS_ACLK+

USB20_P5

USB20_N5

LVDS_A1+LVDS_A1-

LVDS_A2+

LVDS_A0+LVDS_A0-

LVDS_A2-

LVDS_ACLK- LVDS_ACLK+

USB20_P5

USB20_N5

INV_PWM

INV_PWM

DAC_BRIG <33>

BKOFF# <33>

DMIC_DAT <28>

DMIC_CLK <28>

LCD_DDC_DAT <11>

LCD_DDC_CLK <11>

LVDS_A2+ <11>

LVDS_A2- <11>

LVDS_A1+ <11>

LVDS_A1- <11>

LVDS_ACLK+ <11>

LVDS_ACLK- <11>

LVDS_A0+ <11>

LVDS_A0- <11>

UMA_ENVDD<11>

CAM_SHDN# <21>

USB20_P5<20>

USB20_N5<20>

NB_PWM<11>

EC_PWM<33>

+3VS

+3VS

INVPWR_B++LCDVDD

+USB_CAM

+LCDVDD

+LCDVDD

+5VALW

+5VS

B+

+USB_CAM

+5VALW

+USB_CAM

+3VS

+5VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

LCD CONN. / WebCam

Custom

17 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

LVDS CONN

80mil

USB_VCCA is +3.9V, R892:100K;

R891:215KKohm

G916 Vref=1.25V when U54 install

G916-390T1UF

9/20 S P02000EA00/SP02000BW00

L

Close to JLVDS

80mil

L

C718 install when U54 is

RT9193-39GB

Ripely 2.0 Support Veri-Bright function

PJP4

PAD-OPEN 2x2m

2 1

R1084 0_0402_5%

1 2

C867

680P_0402_50V7K

@

12

C483

680P_0402_50V7K

@

1

2

L44

FBMA-L11-201209-221LMA30T_0805

1 2

R2754.7K_0402_5%

1 2

C1108

680P_0402_50V7K

1

2

R491

100_0805_5%

1 2

R892

100K_0402_1%@

12

R224

1M_0402_5%

1 2

R1078 0_0402_5%@1 2

D22

PRTR5V0U2X_SOT143-4@

GND 1

IO1 2

IO2

3

VIN

4

C1056 10P_0402_50V8J@

1 2

C719

10U_0805_10V4Z

1

2

U54

RT9193-39GB_SOT23-5

VIN

1

GND

2

EN

3

VOUT 5

BP 4

C720

10U_0805_10V4Z 1

2

C1058 10P_0402_50V8J@

1 2

C1057 10P_0402_50V8J@

1 2

R276

2.2K_0402_5%

1 2

G

D

S

Q43

SI2301BDS-T1-E3_SOT23-3

2

1 3

C480

680P_0402_50V7K

12

JLVDS

ACES_88242-4001

CONN@

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

22

44

66

88

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

GND

41 GND 42

Q45B

2N7002DW-7-F_SOT363-6

3

5

4

R891

215K_0402_1%@

12

C1059 10P_0402_50V8J@

1 2

R222

100K_0402_5%

1 2

C718

0.1U_0402_16V4Z

1

2

C866

680P_0402_50V7K

@

12

C487

4.7U_0805_10V4Z

R1014

0_0402_5%

@

1 2

C863

1000P_0402_50V7K

1

2

R225

220_0402_5%

12

R2744.7K_0402_5%

1 2

C491

0.1U_0402_16V4Z

1

2

Q45A

2N7002DW-7-F_SOT363-6

61

2

C479

680P_0402_50V7K

1

2

C481

680P_0402_50V7K

12

C482

680P_0402_50V7K

@

1

2

PJP6

PAD-OPEN 2x2m

2 1

R4834.7K_0402_5%@

1 2

R1013

0_0402_5%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

HDMI_R_D0-

HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_R_D0+

HDMI_TX1-

HDMI_R_D2-

HDMI_R_D2+HDMI_TX2+

HDMI_TX2-

HDMI_R_D1+

HDMI_R_D1-

HDMI_TX1+

HDMI_SDATA

HDMI_SCLK

HDMI_TX0-

HDMI_TX0+

HDMI_TX1-

HDMI_TX1+

HDMI_TX2-

HDMI_TX2+

HDMI_HPD

HDMI_CLK+

HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2+

HDMI_TX2-

HDMI_CLK-

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D2-

HDMI_R_D2+

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_D0+

HDMI_R_D0-

HDMI_R_CK+

HDMI_R_CK-

HDMI_SCLK

HDMI_SDATA

HDMI_HPDHDMI_CLK+

HDMI_CLK+

HDMICLK_UMA<11>

HDMIDAT_UMA<11>

HPD <11>

TMDS_B_CLK<10>

TMDS_B_CLK#<10>

TMDS_B_DATA0<10>

TMDS_B_DATA0#<10>

TMDS_B_DATA1<10>

TMDS_B_DATA1#<10>

TMDS_B_DATA2<10>

TMDS_B_DATA2#<10>

+HDMI_5V_OUT+3VS

+5VS +HDMI_5V_OUT

+HDMI_5V_OUT

+3VS

+HDMI_5V_OUT

+5VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

HDMI

Custom

18 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

MP:Update D10 to meet HDMI.

L

Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P

HDMI Connector

03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

1/19 Use one mos to instead of two dule MOS design

v0.2 ADD

v0.2 ADD

C804 0.1U_0402_16V7K

1 2

R1018

0_0402_5%

@

1 2

R210

6.8K_0402_5%

Q134B

2N7002DW-7-F_SOT363-6

3

5

4

G

D

S

Q173

2N7002_SOT23-3

2

13

R307

715_0402_1%

12

R209

4.7K_0402_5%

1 2

R115 0_0402_5%@

1 2

L88

WCM-2012-900T_4P

1

1

4

433

22

R120 0_0402_5%@

1 2

L86

WCM-2012-900T_4P

1

1

4

433

22

R118 0_0402_5%@

1 2

R173

715_0402_1%

1 2

C468

0.1U_0402_16V4Z

1

2

R113 0_0402_5%@

1 2

U39

SN74AHCT1G125GW_SOT353-5

A

2Y4

OE# 1

G

3P5

R615

2.2K_0402_5%

12

R236

6.8K_0402_5%

R119 0_0402_5%@

1 2

R139

715_0402_1%

1 2

C852 0.1U_0402_16V7K

1 2

R117 0_0402_5%@

1 2

D10

RB491D_SOT23

2 1

R112 0_0402_5%@

1 2

C655 0.1U_0402_16V7K

1 2

L87

WCM-2012-900T_4P

1

1

4

433

22

R315

715_0402_1%

1 2

R1104

100K_0402_5%

1 2

Q134A

2N7002DW-7-F_SOT363-6

61

2

R141

715_0402_1%

1 2

C507 0.1U_0402_16V7K

1 2

C827 0.1U_0402_16V7K

1 2

C850

0.1U_0402_16V4Z

1

2R1019

0_0402_5%

@

1 2

JHDMI

SUYIN_100042MR019S153ZLCONN@

D2+

1

GND 2

D2-

3D1+

4

GND 5

D1-

6D0+

7

GND 8

D0-

9CK+

10

GND 11

CK-

12

CEC 13

Reserved 14

SCL

15 SDA

16

DDC/CEC_GND 17

+5V

18

HP_DET

19

GND 20

GND 21

GND 22

GND 23

R628

100K_0402_5%

1 2

C508 0.1U_0402_16V7K

1 2

C853 0.1U_0402_16V7K

1 2

C675 0.1U_0402_16V7K

1 2

R176

4.7K_0402_5%

12

R297

715_0402_1%

1 2

R304

715_0402_1%

1 2

C851

0.1U_0402_16V4Z

1

2

R172

715_0402_1%

1 2

L85

WCM-2012-900T_4P

1

1

4

433

22

R116 0_0402_5%@

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

CLK_PCI_SIO_R PCI_CLK3

CPU_LDT_REQ#

PLT_RST#

NB_RST#_R

SB_RX0P_C

SB_RX0N_C

SB_RX1P_C

SB_RX1N_C

CPU_LDT_REQ#

H_PROCHOT#

NB_RST#_R

SB_32KHI

SB_32KHO

NB_RST#_R

+SB_PCIEVDD

PCI_PIRQH#

SB_RX2P_C

SB_RX2N_C

SB_RX3P_C

SB_RX3N_C

CLK_PCI_EC_R

LPCCLK1

H_PROCHOT#

SB_32KHI

SB_32KHO

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD26

PCI_AD27

PCI_AD28

H_PW RGD

CLK_PCI_EC

LPCCLK1 CLK_PCI_SIO

CLK_PCI_SIO2

CLK_PCI_SIO

CLK_PCI_EC

H_PW RGD_SB

PCI_CLK3 <23>

PCI_CLK5 <23>

PLT_RST# <11,14,25,26,27,32,33>

PCI_CLK4 <23>

PCICLK2 <23>SB_RX0P<10>

SB_RX0N<10>

SB_RX1P<10>

SB_RX1N<10>

SB_TX1P<10>

SB_TX1N<10>

SB_TX0P<10>

SB_TX0N<10>

SB_TX2P<10>

SB_TX2N<10>

SB_TX3P<10>

SB_TX3N<10>

SB_RX2P<10>

SB_RX2N<10>

SB_RX3P<10>

SB_RX3N<10>

RTC_CLK <23>

LPC_FRAME# <32,33>

LPC_AD1 <32,33>

LPC_AD2 <32,33>

LPC_AD0 <32,33>

LPC_AD3 <32,33>

LDT_STOP#<6,11>

CPU_LDT_REQ#<6,11>

H_PROCHOT#<6>

SIRQ <32,33>

CLK_SBSRC_BCLK<15>

CLK_SBSRC_BCLK#<15>

LDT_RST#<6>

ACCEL_INT <30>

PCI_AD23 <23>

PCI_SERR# <33>

PCI_AD24 <23>

PCI_AD25 <23>

PCI_AD26 <23>

PCI_AD27 <23>

PCI_AD28 <23>

H_PW RGD_CPU<6>

H_PW RGD<43>

LPC_DRQ# <32>

CLK_PCI_EC <23,33>

LPCCLK1 <23>

CLK_PCI_SIO <32>

H_PW RGD<43>

CLK_14M_SB<15>

+RTCVCC

+SB_VBAT

+1.8VS

+3VALW

+RTCBATT

+3VL

+3VS

+PCIE_VDDR

+1.2V_HT

+SB_VBAT +RTCVCC_R

+RTCBATT_R

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

SB710-PCIE/PCI/ACPI/LPC/RTC

Custom

19 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

W=20mils

EC & Debug

STRAP PIN

STRAP PIN

Check AMD need pull low or not

W=20mils

W=20mils

Close to SB

Close to SB

9/20 S A00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH

9/20 S P020008T00

01/23 14.318MHz for SB710 reference

R1107 0_0402_5%

1 2

R305 562_0402_1%

12

R311

0_0402_5%

1 2

C497 0.1U_0402_16V7K

1 2

T15PAD

U16

NC7SZ08P5X_NL_SC70-5@

B

2

A

1Y4

P5

G

3

C643

18P_0402_50V8J

1 2

C496 0.1U_0402_16V7K

1 2

L53

BLM18PG121SN1D_0603

1 2

C506

0.1U_0402_16V4Z@

12

C510

1U_0402_6.3V4Z

1

2

C504

10U_0805_10V4Z

1

2

R308 33_0402_5%

1 2

C1086 12P_0402_50V8J

1 2

R301 0_0402_5%

1 2

C492 0.1U_0402_16V7K

1 2

R1079

0_0402_5%

1 2

C494 0.1U_0402_16V7K

1 2

R876

1K_0402_5%

1 2

C495 0.1U_0402_16V7K

1 2

C498 0.1U_0402_16V7K

1 2

Y3

32.768KHZ_12.5PF_Q13MC14610050_10PPM

OSC

4

OSC

1

NC 3

NC 2

PCI EXPRESS IN TERFACE

Part 1 of 5

SB700

PCI INTER FACE

L PC

RTC

C P U

RTC XTAL

PC I CLKS

CL O CK GENERATOR

U15A

218-0660011 A14 SB7_FCBGA528

A_RST#

N2

PCIE_RX2P

R20

PCIE_RX2N

R21

PCIE_RX3P

R18

PCIE_TX3N

T22 PCIE_TX3P

T23 PCIE_TX2N

U24 PCIE_TX2P

U25

PCIE_RX1P

U19

PCIE_RX1N

V19

PCIE_RX0P

U22

PCIE_RX0N

U21

PCIE_TX1N

V25 PCIE_TX1P

V24 PCIE_TX0N

V22 PCIE_TX0P

V23

PCIE_RCLKP/NB_LNK_CLKP

N25

PCIE_RCLKN/NB_LNK_CLKN

N24

PCIE_CALRP

T25

PCIE_CALRN

T24

PCIE_PVDD

P24

GPP_CLK1N

L19

X1

A3

X2

B3

VBAT B2

GPP_CLK0N

J18

GPP_CLK2P

M19

ALLOW_LDTSTP

F23

CPU_HT_CLKN

M18

GPP_CLK2N

M20

SLT_GFX_CLKP

M23

CPU_HT_CLKP

P17

LDT_RST#

G24

PCICLK0 P4

PCICLK1 P3

PCICLK2 P1

PCICLK3 P2

PCIRST# N1

CBE0# W2

CBE1# U7

CBE2# AA7

CBE3# Y1

FRAME# AA6

DEVSEL# W5

IRDY# AA5

TRDY# Y5

PAR U6

STOP# W6

PERR# W4

REQ0# AC3

REQ1# AD4

REQ2# AB7

REQ3#/GPIO70 AE6

GNT0# AD2

GNT1# AE4

GNT2# AD5

GNT3#/GPIO72 AC6

SERR# V7

CLKRUN# AD6

LAD0 H24

LAD1 H23

LAD2 J25

LAD3 J24

LFRAME# H25

LDRQ0# H22

SERIRQ V15

PCICLK4 T4

LPCCLK0 G22

LPCCLK1 E22

AD0 U2

AD1 P7

AD2 V4

AD3 T1

AD4 V3

AD5 U1

AD6 V1

AD7 V2

AD8 T2

AD9 W1

AD10 T9

AD12 R7

AD13 R5

AD14 U8

AD15 U5

AD16 Y7

AD17 W8

AD18 V9

AD19 Y8

AD20 AA8

AD21 Y4

AD22 Y3

AD23 Y2

AD24 AA2

AD25 AB4

AD26 AA1

AD27 AB3

AD28 AB2

AD29 AC1

AD30 AC2

AD31 AD1

AD11 R6

REQ4#/GPIO71 AB6

GNT4#/GPIO73 AE5

LDRQ1#/GNT5#/GPIO68 AB8

GPP_CLK1P

L20

RTCCLK C3

PCIE_RX3N

R17

INTE#/GPIO33 AD3

INTF#/GPIO34 AC4

INTG#/GPIO35 AE2

INTH#/GPIO36 AE3

LOCK# V5

PCIE_PVSS

P25

PCICLK5/GPIO41 T3

BMREQ#/REQ5#/GPIO65 AD7

NB_HT_CLKP

M24

LDT_PG

F22

LDT_STP#

G25

GPP_CLK3N

P22

INTRUDER_ALERT# C2

NB_DISP_CLKP

K23

25M_48M_66M_OSC

L18

GPP_CLK0P

J19

NB_HT_CLKN

M25

SLT_GFX_CLKN

M22

GPP_CLK3P

N22

14M_X1

J21

14M_X2

J20

NB_DISP_CLKN

K22

PROCHOT#

F24

R316

120_0402_5%

1 2

C652

18P_0402_50V8J

1 2

C505

1U_0402_6.3V4Z

1

2

J1

JUMP_43X39@

1

122

R389

20M_0402_5%

12

R317

120_0402_5%

1 2

R312 33_0402_5%

12

R1109 1K_0402_5%@

12

C1087 12P_0402_50V8J

1 2

R302 33_0402_5%

1 2

R306 2.05K_0402_1%

12

R314 20M_0402_5%@

1 2

R967 0_0402_5%

12

T16PAD

R1108 0_0402_5%@

12

R319 10K_0402_5%

12

T18PAD

C509

0.1U_0402_16V4Z

1

2

C499 0.1U_0402_16V7K

1 2

C493 0.1U_0402_16V7K

1 2

T17PAD

R300 8.2K_0402_5%@

1 2

R318 10K_0402_5%@

12

D42

DAN202U_SC70

2

3

1JBATT1

ACES_85205-02001CONN@

1

1

2

2

GND

3

GND

4

C1085 12P_0402_50V8J@

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

NBPW RGD

USB20_N0

USB20_P0

USB20_N1

USB20_P1

USB20_P2

USB20_N2

USB20_P3

USB20_N3

USB20_N5

USB20_P5

USB20_N6

USB20_P6

USB20_P7

USB20_N7

USB20_N11

USB20_P11

USB20_P10

USB20_N10

USB20_N8

USB20_P8

SMB_CK_DAT1

SMB_CK_CLK1

SUS_STAT#

H_THERMTRIP#

USB_RCOMP

SMB_CK_CLK0

SMB_CK_DAT0

SUS_STAT#

HDA_SDIN1

HDA_SDIN0

HDA_SDOUT

HDABITCLK

HDA_SYNC

HDARST#

SB_TEST2

SB_TEST1

SB_TEST0

SB_TEST2

SB_TEST1

SB_TEST0

SMB_CK_DAT0

SMB_CK_CLK0

SMB_CK_CLK1

SMB_CK_DAT1

EC_RSMRST#

EXP_CPPE#

NBPW RGD

PCIE_WAKE#

PCIE_WAKE#

CR_CPPE#

SB_GPIO5

HDA_BITCLK_CODEC

HDA_BITCLK_MDC

HDA_SDOUT_MDC

HDA_SDOUT_CODEC

HDABITCLK

HDA_BITCLK

HDA_BITCLK

EC_RSMRST#

EC_LID_OUT#<33>

EC_SCI#<33>

USB20_N0 <31>

USB20_P0 <31>

USB20_N1 <31>

USB20_P1 <31>

USB20_P2 <31>

USB20_N2 <31>

USB20_P3 <35>

USB20_N3 <35>

USB20_N5 <17>

USB20_P5 <17>

USB20_N6 <31>

USB20_P6 <31>

USB20_P7 <31>

USB20_N7 <31>

USB20_N11 <26>

USB20_P11 <26>

USB20_P10 <26>

USB20_N10 <26>

USB20_N8 <26>

USB20_P8 <26>

HDARST#<23,33>

SMB_CK_DAT1<26>

SMB_CK_CLK1<26>

EC_RSMRST#<33>

SMB_CK_DAT0<8,9,15,30>

SMB_CK_CLK0<8,9,15,30>

H_THERMTRIP#<6>

SB_SPKR<28>

CLK_48M_USB <15>

SUS_STAT#<11>

HDA_SDIN0<28>

HDA_SDIN1<34>

HDA_SDOUT_MDC<34>

HDA_SDOUT_CODEC<28>

HDA_BITCLK_CODEC<28>

HDA_BITCLK_MDC<34>

HDA_SYNC_MDC<34>

HDA_SYNC_CODEC<28>

HDA_RST#_CODEC<28>

HDA_RST#_MDC<34>

SLP_S3#<33>

SLP_S5#<33>

PWRBTN_OUT#<33>

SB_PWRGD<6,33,43>

KB_RST#<33>

GATEA20<33>

EC_SMI#<33>

GPIO16 <23>

GPIO17 <23>

EXP_CPPE#<26>

NB_PWRGD<11>

LAN_PCIE_WAKE#<25>

MINI_PCIE_WAKE#<26>

CR_CPPE#<27>

3/5V_OK<39,41>

+3VS

+3VALW

+3VALW

+3VS

+3VALW

+3VS

+3VS

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

SB710 USB/AC97

Custom

20 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Touch Screen (delete)

STRAP PIN

USB-0 Right side (S/W Debug Port)

USB-7 Fingerprint

USB-5 USB Camera

USB-10 MiniCard(TV or WWAN)

USB-4 Left side

STRAP PIN

USB-2 Left Side

USB-6 Bluetooth

SB700 has internal PD

USB-3 Dock

USB-1 Right side

USB-11 New Card

USB-8 MiniCard(WLAN)

USB-9 Card Reader (delete)

STRAP PIN

demo circuit LID use RI#

For SB700 A11 divider to

1.8V for RS & RX780

03/05 Add SSC circuit for HDA_BITCLK.

R81 0_0402_5%

1 2

C1122

0.1U_0402_16V4Z

@1

2

R321 2.2K_0402_5%@

1 2

R1081

10K_0402_5%

@

12

R1082

10K_0402_5%

@

12

R32311.8K_0402_1%

1 2

U66

ASM3P623S00BF-08TR_TSSOP8

@

CLKOUT

6

VDD

7

NC 2

CLKIN 1

NC 8

SS 3

SSON

5

GND

4

C1089 82P_0402_50V8J

1 2

C1091 82P_0402_50V8J

1 2

R339 33_0402_5%

1 2

R337 33_0402_5%

1 2

R322 2.2K_0402_5%@

1 2

R82 0_0402_5%

1 2

R540

10K_0402_5%

1 2

R320 2.2K_0402_5%@

1 2

R83

10K_0402_5%

1 2

R331 2.2K_0402_5%

1 2

R340 33_0402_5%

1 2

USB 2.0

Part 4 of 5

SB700

ACPI / WAKE UP EVENTS

GPIO

HD AUDIO

US B OC

USB 1.1

USB M ISC

INTEGRATED uC

INTEGRATED uC

U15D

218-0660011 A14 SB7_FCBGA528

USBCLK/14M_25M_48M_OSC C8

USB_RCOMP G8

USB_OC6#/IR_TX1/GEVENT6#

B9

USB_HSD5P C12

USB_HSD5N D12

USB_HSD4P B12

USB_HSD4N A12

USB_HSD3P G12

USB_HSD3N G14

USB_HSD2P H14

USB_HSD2N H15

USB_HSD1P A13

USB_HSD1N B13

USB_HSD0P B14

USB_HSD0N A14

USB_OC4#/IR_RX0/GPM4#

A8

USB_OC3#/IR_RX1/GPM3#

A9

USB_OC1#/GPM1#

F8 USB_OC2#/GPM2#

E5

USB_HSD7P G11

USB_HSD7N H12

USB_HSD6P E12

USB_HSD6N E14

USB_OC0#/GPM0#

E4

DDR3_RST#/GEVENT7#

G5

SATA_IS0#/GPIO10

AE18

AZ_SDIN3/GPIO46

M3

PCI_PME#/GEVENT4#

E1

RI#/EXTEVNT0#

E2

SLP_S3#

F5

SLP_S5#

G1

PWR_BTN#

H2

PWR_GOOD

H1

SUS_STAT#

K3

TEST1

H4

TEST0

H3

GA20IN/GEVENT0#

Y15

KBRST#/GEVENT1#

W15

SMBALERT#/THRMTRIP#/GEVENT2#

J6

LPC_PME#/GEVENT3#

K4

LPC_SMI#/EXTEVNT1#

K24

S3_STATE/GEVENT5#

F1

SYS_RESET#/GPM7#

J2

WAKE#/GEVENT8#

H6

RSMRST#

D3

CLK_REQ3#/SATA_IS1#/GPIO6

AD18

NB_PWRGD

W14

SMARTVOLT1/SATA_IS2#/GPIO4

AA19

SMARTVOLT2/SHUTDOWN#/GPIO5

Y19

SPKR/GPIO2

W21

SCL0/GPOC0#

AA18

SDA0/GPOC1#

W18

DDC1_SCL/GPIO9

AA20

DDC1_SDA/GPIO8

Y18

AZ_BITCLK

M1

AZ_SDOUT

M2

AZ_SYNC

L6

AZ_RST#

M4

USB_HSD9P A11

USB_HSD9N B11

USB_HSD8P C10

USB_HSD8N D10

LLB#/GPIO66

C1

AZ_DOCK_RST#/GPM8#

L5

SLP_S2/GPM9#

H7

USB_OC5#/IR_TX0/GPM5#

B8

BLINK/GPM6#

F2

SCL1/GPOC2#

K1

SDA1/GPOC3#

K2

TEST2

H5

CLK_REQ0#/SATA_IS3#/GPIO0

W17

AZ_SDIN2/GPIO44

L8 AZ_SDIN1/GPIO43

J8 AZ_SDIN0/GPIO42

J7

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

V17

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W20

USB_FSD13P E6

USB_FSD13N E7

USB_FSD12P F7

USB_FSD12N E8

USB_HSD11P H11

USB_HSD11N J10

USB_HSD10P E11

USB_HSD10N F11

KSO_17 B18

IMC_PWM0/IMC_GPIO10 F21

SCL2/IMC_GPIO11 D21

SDA2/IMC_GPIO12 F19

SCL3_LV/IMC_GPIO13 E20

SDA3_LV/IMC_GPIO14 E21

IMC_PWM1/IMC_GPIO15 E19

IMC_PWM2/IMC_GPO16 D19

IMC_PWM3/IMC_GPO17 E18

KSI_0 G20

KSI_1 G21

KSI_2 D25

KSI_3 D24

KSI_4 C25

KSI_5 C24

KSI_6 B25

KSI_7 C23

PS2_DAT

H19

PS2_CLK

H20

SPI_CS2#/IMC_GPIO2

H21

IDE_RST#/F_RST#/IMC_GPO3

F25

PS2KB_DAT

D22

PS2KB_CLK

E24

PS2M_DAT

E25

PS2M_CLK

D23

KSO_16 A18

KSO_0 B24

KSO_1 B23

KSO_2 A23

KSO_3 C22

KSO_4 A22

KSO_5 B22

KSO_6 B21

KSO_7 A21

KSO_8 D20

KSO_9 C20

KSO_10 A20

KSO_11 B20

KSO_12 B19

KSO_13 A19

KSO_14 D18

KSO_15 C18

R1080 0_0402_5%

1 2

R336 33_0402_5%

1 2

R329 1.2K_0402_5%

1 2

R1083

10K_0402_5%

@

1 2

R333 33_0402_5%

1 2

R1052

0_0402_5%

12

C1088 82P_0402_50V8J

1 2

R327

2.2K_0402_5%

1 2

R335 33_0402_5%

1 2

R338 33_0402_5%

1 2

R332 2.2K_0402_5%

1 2

T19PAD

R328 1.2K_0402_5%

1 2

C1090 82P_0402_50V8J

1 2

R994 0_0402_5%@

12

R1053

100_0402_5%@

12

R334 33_0402_5%

1 2

D58

CH751H-40PT_SOD323-2

21

R993 47_0402_5%

12

R388 4.7K_0402_5%

1 2

T41PAD

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+PLLVDD_SATA

+XTLVDD_SATA

LFB_ID1

LFB_ID2

LFB_ID0

+SB_AVDD

LFB_ID2

THERMAL_DC

SATA_STX_DRX_P1

SATA_STX_DRX_N1

SATA_STX_DRX_P0

SATA_STX_DRX_N0

SATA_X2

SATA_X1

SATA_CAL

LFB_ID1

LFB_ID0

SATA_X2

SATA_X1

SATA_STX_DRX_P2

SATA_STX_DRX_N2

SATA_STX_DRX_P3

SATA_STX_DRX_N3

AC_IN_SB

SATA_TXP0<24>

SATA_TXN0<24>

SATA_RXP0_C<24>

SATA_RXN0_C<24>

SATA_LED#<34>

SATA_TXP1<24>

SATA_TXN1<24>

SATA_RXP1_C<24>

SATA_RXN1_C<24>

EC_THERM# <33>

CAM_SHDN# <17>

BT_OFF <31>

SATA_TXP2<31>

SATA_TXN2<31>

SATA_RXP2_C<31>

SATA_RXN2_C<31>

WLOFF# <26>

BT_COMBO_EN# <26>

WWOFF# <26>

SATA_TXP3<24>

SATA_TXN3<24>

SATA_RXP3_C<24>

SATA_RXN3_C<24>

HDD_HALTLED# <34>

SB_INT_FLASH_SEL

CR_WAKE# <27>

AC_IN <33,38>

+3VALW

+3VS

+1.2V_HT

+3VS

+3VALW

+3VALW

+3VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

SB710 SATA/IDE/SPI

Custom

21 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

LFB_ID0 to LFB_ID2 got internal PU 10K to S5.

Hynix

Qimonda

Samsung

LFB_ID0LFB_ID1LFB_ID2

0 0 0

0 0 1

0 01

Local Frame Buffer Strapping List

Copy from Becks.

02/18 Add R1071 and D56 to connect to AC_IN.

R1071

150K_0402_5%

12

C51710P_0402_50V8J

12

C523

1U_0402_6.3V4Z

1

2

D56

CH751H-40PT_SOD323-2

2 1

R1062 0_0402_5%

1 2

R342 1K_0402_1%

12

R344 1K_0402_5%

1 2

C526

2.2U_0603_6.3V4Z

1

2

L56

BLM18PG121SN1D_0603

12

ATA 66/100/133

Part 2 of 5

SB700

SATA PWR SERIAL ATA

SPI ROM

HW MONITOR

U15B

218-0660011 A14 SB7_FCBGA528

IDE_IORDY AA24

IDE_IRQ AA25

IDE_A0 Y22

IDE_A1 AB23

IDE_A2 Y23

IDE_DACK# AB24

IDE_DRQ AD25

IDE_IOR# AC25

IDE_IOW# AC24

IDE_CS1# Y25

IDE_CS3# Y24

IDE_D0/GPIO15 AD24

IDE_D1/GPIO16 AD23

IDE_D2/GPIO17 AE22

IDE_D3/GPIO18 AC22

IDE_D4/GPIO19 AD21

IDE_D5/GPIO20 AE20

IDE_D6/GPIO21 AB20

IDE_D7/GPIO22 AD19

IDE_D8/GPIO23 AE19

IDE_D9/GPIO24 AC20

IDE_D10/GPIO25 AD20

IDE_D11/GPIO26 AE21

IDE_D12/GPIO27 AB22

IDE_D13/GPIO28 AD22

IDE_D14/GPIO29 AE23

IDE_D15/GPIO30 AC23

XTLVDD_SATA

W12

PLLVDD_SATA

AA11

SATA_TX2P

AB12

SATA_TX2N

AC12

SATA_RX2P

AD12 SATA_RX2N

AE12

SATA_TX3P

AD13

SATA_TX3N

AE13

SATA_RX3P

AC14 SATA_RX3N

AB14

SATA_TX0P

AD9

SATA_TX0N

AE9

SATA_RX0N

AB10

SATA_RX0P

AC10

SATA_TX1P

AE10

SATA_TX1N

AD10

SATA_RX1N

AD11

SATA_RX1P

AE11

SATA_CAL

V12

SATA_X1

Y12

SATA_X2

AA12

SATA_ACT#/GPIO67

W11

SPI_DI/GPIO12 G6

SPI_DO/GPIO11 D2

SPI_CLK/GPIO47 D1

SPI_HOLD#/GPIO31 F4

SPI_CS1#/GPIO32 F3

FANOUT1/GPIO48 M5

FANOUT2/GPIO49 M7

FANIN0/GPIO50 P5

FANIN1/GPIO51 P8

FANIN2/GPIO52 R8

LAN_RST#/GPIO13 U15

ROM_RST#/GPIO14 J1

VIN0/GPIO53 A4

VIN1/GPIO54 B4

VIN2/GPIO55 C4

VIN3/GPIO56 D4

VIN4/GPIO57 D5

VIN5/GPIO58 D6

VIN6/GPIO59 A7

VIN7/GPIO60 B7

TEMPIN0/GPIO61 B6

TEMPIN1/GPIO62 A6

TEMPIN2/GPIO63 A5

TEMPIN3/TALERT#/GPIO64 B5

FANOUT0/GPIO3 M8

AVDD F6

AVSS G7

TEMP_COMM C6

SATA_TX4P

AE14

SATA_TX4N

AD14

SATA_RX4N

AD15

SATA_RX4P

AE15

SATA_TX5P

AB16

SATA_TX5N

AC16

SATA_RX5N

AE16

SATA_RX5P

AD16

C525

0.1U_0402_16V4Z

1

2

R367 10K_0402_5%

1 2

L54

BLM18PG121SN1D_0603

12

C512 0.01U_0402_25V7K

1 2

R341

10M_0402_5%

12

C522

1U_0402_6.3V4Z

1

2

C520 1000P_0402_50V7K

1 2

R1032

1K_0402_5%@

1 2

C513 0.01U_0402_25V7K

1 2

C519 0.01U_0402_25V7K

1 2

L55

BLM18PG121SN1D_0603

12

Y4

25MHz_20pF_6X25000017

12

C515 0.01U_0402_25V7K

1 2

R343 10K_0402_5%

1 2

R345 10K_0402_5%

1 2

C521 1000P_0402_50V7K

1 2

R1033

1K_0402_5%@

1 2

C524

1U_0402_6.3V4Z

1

2

C518 0.01U_0402_25V7K

1 2

C514 0.01U_0402_25V7K

1 2

C51610P_0402_50V8J

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+AVDDCK_1.2V

+1.2V_CKVDD

+AVDDCK_3.3V

+V5_VREF

+S5_3V

+AVDDCK_3.3V

+AVDDCK_1.2V

+AVDDC

+S5_1.2V

+1.2V_SB_CORE

+1.2_USB

+3.3V_SB_IDE

+3VS

+1.2V_HT

+1.2V_HT

+3VALW

+3VS

+3VS

+5VS

+1.2V_HT

+1.2V_HT

+PCIE_VDDR

+1.2V_SATA

+3VALW

+AVDD_USB

+1.2VALW

+1.2VALW

+1.2V_HT

+1.2VALW

+3VALW

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

SB710 PWR/GND

Custom

22 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

L

0.45A/40mil/3vias ?

L

0.45A/30mil/3vias

L

0.8A/50mil/4vias

L

<1.25A/50mil/4vias

L

<1.25A/50mil/4vias?

L

0.6A/50mil/4vias

L

0.3A/30mil/2vias

L

0.1A/30mil/2vias ?

L

C567,C568 change to 1U_0402 when SI-2

L69

0_0805_5%

12

C544 1U_0402_6.3V4Z@

1 2

C5621U_0402_6.3V4Z

12

C579

1U_0603_10V4Z

1

2

C560 0.1U_0402_16V4Z

1 2

C580 1U_0402_6.3V4Z

1 2

C547 1U_0402_6.3V4Z@

1 2

L63

0_0805_5%

12

C539 1U_0402_6.3V4Z

1 2

C582 0.1U_0402_16V4Z

1 2

R592 0_0805_5%@

1 2

C581 1U_0402_6.3V4Z

1 2

C535 1U_0402_6.3V4Z

1 2

C55622U_0805_6.3V6M

1 2

SB700

GROUND

Part 5 of 5

U15E

218-0660011 A14 SB7_FCBGA528

VSS_4 D7

VSS_2 A25

VSS_21 M13

VSS_10 K16

VSS_11 L4

VSS_1 A2

VSS_17 L16

VSS_8 K9

VSS_9 K11

VSS_46 AB1

VSS_13 L10

VSS_14 L11

VSS_15 L12

VSS_16 L14

VSS_18 M6

VSS_19 M10

VSS_20 M11

VSS_22 M15

VSS_23 N4

VSS_26 P6

VSS_27 P9

VSS_28 P10

VSS_29 P11

VSS_32 R1

VSS_33 R2

VSS_34 R4

VSS_36 R10

VSS_37 R12

VSS_3 B1

VSS_35 R9

VSS_30 P13

AVSS_SATA_15

AB13

AVSS_SATA_18

AC8

AVSS_SATA_5

V11

AVSS_SATA_11

Y17

AVSS_SATA_19

AD8

VSS_31 P15

VSS_24 N12

AVSS_SATA_14

AB11

AVSS_SATA_2

U10

AVSS_SATA_3

U11

AVSS_SATA_1

T10

AVSS_SATA_17

AB17

AVSS_SATA_4

U12

AVSS_SATA_12

AA9

AVSS_SATA_6

V14

AVSS_SATA_10

Y14

AVSS_SATA_7

W9

AVSS_SATA_8

Y9

AVSS_SATA_16

AB15

AVSS_SATA_20

AE8

AVSS_SATA_13

AB9

AVSS_USB_5

D9

AVSS_USB_8

D14

AVSS_USB_4

D8 AVSS_USB_3

C14

AVSS_USB_6

D11

AVSS_USB_7

D13

AVSS_USB_2

B15

AVSS_USB_21

K10

AVSS_USB_10

E15

AVSS_USB_20

J15

AVSS_USB_22

K12

AVSS_USB_11

F12

AVSS_USB_12

F14

AVSS_USB_23

K14

AVSS_USB_16

J9 AVSS_USB_15

H17

AVSS_USB_19

J14

AVSS_USB_14

H9

AVSS_USB_1

A15

AVSS_USB_24

K15

VSS_12 L7

AVSS_USB_17

J11

AVSS_USB_18

J12

VSS_7 H8

VSS_25 N14

VSS_6 G19

AVSS_USB_13

G9

AVSS_USB_9

D15

AVSSCK L17

PCIE_CK_VSS_3

J22

PCIE_CK_VSS_14 U20

PCIE_CK_VSS_13 U18

PCIE_CK_VSS_12 T17

PCIE_CK_VSS_18 W19

PCIE_CK_VSS_6

M17

PCIE_CK_VSS_11 R19

PCIE_CK_VSS_8

P16 PCIE_CK_VSS_7

M21

PCIE_CK_VSS_17 V21

PCIE_CK_VSS_16 V20

PCIE_CK_VSS_15 V18

VSS_50 AE24

PCIE_CK_VSS_21 W25

PCIE_CK_VSS_19 W22

PCIE_CK_VSS_20 W24

AVSSC

F9

PCIE_CK_VSS_2

J17 PCIE_CK_VSS_1

H18

PCIE_CK_VSS_4

K25

VSS_5 F20

PCIE_CK_VSS_5

M16

PCIE_CK_VSS_9 P23

PCIE_CK_VSS_10 R16

VSS_49 AE1

VSS_44 V6

VSS_45 Y21

VSS_42 U4

VSS_48 AB25

VSS_47 AB19

VSS_41 T14

VSS_43 U14

VSS_38 R14

VSS_39 T11

VSS_40 T12

AVSS_SATA_9

Y11

C5630.1U_0402_16V4Z

12

C576 10U_0805_10V4Z

1 2

C5381U_0402_6.3V4Z

12

C5270.1U_0402_16V4Z

12

L64 0_0603_5%

R12

0_0603_5%@

1 2

Part 3 of 5

SB700

POWER

PCI/GPIO I/O

CO RE S0

3.3V_S5 I/OCO RE S5

A-LINK I/O

SATA I/O

USB I/O

PL L CLKGEN I/O

IDE/FLSH I/O

U15C

218-0660011 A14 SB7_FCBGA528

VDDQ_2

M9

VDDQ_6

U17

VDDQ_3

T15

VDDQ_11

AB5

VDDQ_1

L9

VDDQ_4

U9

VDDQ_5

U16

VDDQ_12

AB21

VDDQ_10

AA4

VDDQ_7

V8

VDDQ_8

W7

VDDQ_9

Y6

S5_3.3V_1 A17

S5_3.3V_2 A24

S5_3.3V_3 B17

S5_3.3V_4 J4

S5_3.3V_5 J5

S5_1.2V_2 G4

S5_1.2V_1 G2

USB_PHY_1.2V_1 A10

USB_PHY_1.2V_2 B10

V5_VREF AE7

AVDDCK_3.3V J16

AVDDCK_1.2V K17

AVDDC E9

AVDDTX_0

A16

AVDDTX_1

B16

AVDDTX_2

C16

AVDDTX_3

D16

AVDDTX_5

E17 AVDDTX_4

D17

AVDDRX_2

F18

AVDDRX_0

F15

AVDDRX_5

G18 AVDDRX_4

G17

PCIE_VDDR_4

P21 PCIE_VDDR_3

P20

PCIE_VDDR_7

R25

PCIE_VDDR_2

P19

PCIE_VDDR_5

R22

PCIE_VDDR_1

P18

PCIE_VDDR_6

R24

AVDD_SATA_1

AA14

AVDD_SATA_4

AB18

AVDD_SATA_2

AA15

AVDD_SATA_3

AA17

AVDD_SATA_5

AC18

AVDD_SATA_6

AD17

AVDD_SATA_7

AE17

VDD_1 L15

VDD_2 M12

VDD_3 M14

VDD_4 N13

VDD_5 P12

VDD_6 P14

VDD_7 R11

VDD_9 T16

VDD_8 R15

AVDDRX_1

F17

AVDDRX_3

G15

VDD33_18_2

AA21

VDD33_18_4

AE25 VDD33_18_3

AA22

VDD33_18_1

Y20

CKVDD_1.2V_2 L22

CKVDD_1.2V_1 L21

CKVDD_1.2V_4 L25

CKVDD_1.2V_3 L24

S5_3.3V_7 L2

S5_3.3V_6 L1

C550 10U_0805_10V4Z

1 2

L61

0_0805_5%

12

C57310U_0805_10V4Z

1 2

C5741U_0402_6.3V4Z

12

C5650.1U_0402_16V4Z

12

C5880.1U_0402_16V4Z 12

C552 4.7U_0805_10V4Z

12

C52910U_0805_6.3V6M

1 2

L66

0_0805_5%

12

L67

0_0805_5%

12

C5900.1U_0402_16V4Z 12

C5860.1U_0402_16V4Z 12

C5341U_0402_6.3V4Z

12

L60

0_0805_5%

12

C548 0.1U_0402_16V4Z 12

C533 1U_0402_6.3V4Z

1 2

C568 1U_0805_16V7K

1 2

C558 1U_0402_6.3V4Z

1 2

C542 0.1U_0402_16V4Z

1 2

R3461K_0402_5%

12

D14

CH751H-40PT_SOD323-2

21

C5611U_0402_6.3V4Z

12

C549 1U_0402_6.3V4Z

1 2

C5852.2U_0603_6.3V4Z

12

C5691U_0402_6.3V4Z

12

C571 0.1U_0402_16V4Z

1 2

C528 22U_0805_6.3V6M

12

C5591U_0402_6.3V4Z

12

R564 0_0805_5%

1 2

C5751U_0402_6.3V4Z

12

C578

0.1U_0402_16V4Z

1

2

C584 0.1U_0402_16V4Z

1 2

C5700.1U_0402_16V4Z

12

C566 22U_0805_6.3V6M

12

L65 0_0603_5%

C555 1U_0402_6.3V4Z

1 2

C583 0.1U_0402_16V4Z

1 2

C546 1U_0402_6.3V4Z

1 2

C5371U_0402_6.3V4Z

12

C543 22U_0805_6.3V6M@

12

C567 1U_0805_16V7K

1 2

C557 0.1U_0402_16V4Z

1 2

C545 1U_0402_6.3V4Z

1 2

C554 1U_0402_6.3V4Z

1 2

C531 1U_0402_6.3V4Z

1 2

C536 1U_0402_6.3V4Z@

1 2

C530 1U_0402_6.3V4Z

1 2

C551 0.1U_0402_16V4Z 12

L68

0_0805_5%

12

C572 0.1U_0402_16V4Z

1 2

C5640.1U_0402_16V4Z

12

C5892.2U_0603_6.3V4Z

12

C5872.2U_0603_6.3V4Z

12

C553 1U_0402_6.3V4Z

1 2

C5321U_0402_6.3V4Z

12

C541 0.1U_0402_16V4Z

1 2

R593 0_0805_5%

1 2

C577 10U_0805_10V4Z

1 2

C5400.1U_0402_16V4Z

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

PCI_AD28<19>

PCI_AD27<19>

PCI_AD26<19>

PCI_AD25<19>

PCI_AD24<19>

PCI_AD23<19>

PCICLK2<19>

PCI_CLK3<19>

PCI_CLK4<19>

PCI_CLK5<19>

CLK_PCI_EC<19,33>

LPCCLK1<19>

RTC_CLK<19>

HDARST#<20,33>

GPIO17<20>

GPIO16<20>

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

SB700 STRAPS

Custom

23 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Intern al pull up

RESERVED

DEBUG STRAPS

PCI_AD25 PCI_AD24

USE EEPROM

PCIE STRAPS

USE DEFAULT

PCIE STRAPS

DEFA U LT

BYPASS

ACPI

BCLK

USE ACPI

BCLK

DEFA U LT

USE IDE

PL L

USE

LONG

RESET

USE

SHORT

RESET

USE PCI

PL L

DEFA U LT

BYPASS IDE

PL L

PULL

HIGH

DEFA U LT

BYPASS

PCI PLL

PCI_AD27 PCI_AD26

PULL

LOW

DEFA U LT

PCI_AD28

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD23

LPC_CLK0

ENABLE PCI

MEM BOOT

EXT. RTC

(PD on X1,

apply

32KHz to

RTC_CLK)

DEFA U LT

GP17

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

DISABLE PCI

MEM BOOT

PULL

LOW

PULL

HIGH

REQUIRED STRAPS

INTERNAL

RTC

DEFA U LT

RTC_CLKLPC_CLK1

CLKGEN

ENABLED

DEFA U LT

CLKGEN

DISABLED

AZ_RST_CD#

EC

ENABLED

EC

DISABLED

DEFA U LT

GP16PCI_CLK2

BOOTFAIL

TIMER

ENABLED

DEFA U LT

BOOTFAIL

TIMER

DISABLED

PCI_CLK3

RESERVED

DEFA U LT

IGNORE

DEBUG

STRAPS

USE

DEBUG

STRAPS

PCI_CLK4 PCI_CLK5

RESERVED

L,H = LPC ROM (Default)

H,H = Reserved

H,L = SPI ROM

L,L = FWH ROM

R349

10K_0402_5%

@

12

R358

10K_0402_5%

12

R347

10K_0402_5%

@

12

R374

2.2K_0402_5%

@

12

R348

10K_0402_5%

@

12

R364

10K_0402_5%

12

R376

2.2K_0402_5%

@

12

R353

10K_0402_5%

@

12

R365

2.2K_0402_5%

12

R378

2.2K_0402_5%

@

12

R351

10K_0402_5%

@

12

R361

10K_0402_5%

12

R356

2.2K_0402_5%

12

R357

10K_0402_5%

12

R362

10K_0402_5%

12

R373

2.2K_0402_5%

@

12

R360

10K_0402_5%

@

12

R377

2.2K_0402_5%

@

12

R359

10K_0402_5%

@

12

R363

2.2K_0402_5%

@

12

R375

2.2K_0402_5%

@

12

R355

10K_0402_5%

@

12

R354

10K_0402_5%

@

12

R366

2.2K_0402_5%

@

12

R352

10K_0402_5%

@

12

R350

10K_0402_5%

@

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SATA_RXP1 SATA_RXP1_C

SATA_TXP1

SATA_TXN1

SATA_RXN1 SATA_RXN1_C

SATA_RXP0_CSATA_RXP0

SATA_RXN0 SATA_RXN0_C

SATA_TXP0

SATA_TXN0

SATA_TXP3

SATA_TXN3

SATA_RXP3_C

SATA_RXN3 SATA_RXN3_C

SATA_RXP3

SATA_RXP1_C <21>

SATA_TXP1 <21>

SATA_TXN1 <21>

SATA_RXN1_C <21>

SATA_RXN0_C <21>

SATA_RXP0_C <21>

SATA_TXN0 <21>

SATA_TXP0 <21>

SATA_TXP3 <21>

SATA_TXN3 <21>

SATA_RXN3_C <21>

SATA_RXP3_C <21>

+5VS

+5VS

+5VS

+3VS +3VS_HDD1

+5VS

+5VS

+3VS_HDD1

+5VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

HDD/CDROM

Custom

24 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

CD-ROM Connector

Placea caps. ne ar ODD CONN.

Multi-Bay Connector-option

Place close to Multi-Bay

Connector-option JP10

HDD Connector

Pleace near HD CONN (JP23)

Pleace near HD CONN (JP23)

Max 3A

Near CONN side.

Near CONN side.

Near CONN side.

C591

0.1U_0402_16V4Z

1

2

C595

0.1U_0402_16V4Z

1

2

R1009

0_0805_5%

@

1 2

R970 0_0402_5%

1 2

JP10

TYCO_2023087-3

CONN@

GND 1

VCC5

4VCC5

2

TX- 5

TX+ 3

VCC5

6

GND 7

VCC3

8

RX- 9

VCC3

10

RX+ 11

VCC3

12

GND 13

GND

14

GND 15

GND

16

GND 17

GND

18

C603

0.1U_0402_16V4Z

PA@

1

2

C1032

10U_0805_10V4Z

@

1

2

C594

0.1U_0402_16V4Z

1

2

C611

0.01U_0402_16V7K

12

C614

1U_0603_10V4Z

1

2

C605

0.01U_0402_16V7K

12

+

C600

150U_Y_6.3VM@

1

2

C606

0.01U_0402_16V7K

12

C601

10U_0805_10V4Z

PA@

1

2

C613

0.1U_0402_16V4Z

1

2

C1035

0.1U_0402_16V4Z

@

1

2

C1033

0.1U_0402_16V4Z

@

1

2

C602

0.1U_0402_16V4Z

PA@

1

2

C615

10U_0805_10V4Z

1

2

C616

10U_0805_10V4Z

1

2

JP9

SUYIN_127072FR022G523_RV

CONN@

GND 1

A+ 2

A- 3

GND 4

B- 5

B+ 6

GND 7

V33 8

V33 9

V33 10

GND 11

GND 12

GND 13

V5 14

V5 15

V5 16

GND 17

Reserved 18

GND 19

V12 20

V12 21

V12 22

C612

0.01U_0402_16V7K

12

C1034

0.1U_0402_16V4Z

@

1

2

JP11

SUYIN_127382FR013G509ZRCONN@

GND 1

A+ 2

A- 3

GND 4

B- 5

B+ 6

GND 7

DP 8

V5 9

V5 10

MD 11

GND 12

GND 13

C596

0.01U_0402_16V7K

12

C604

0.1U_0402_16V4Z

PA@ 1

2

C593

10U_0805_10V4Z

1

2

C592

0.01U_0402_16V7K

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

LAN_SK_LAN_LINK#

LAN_MDI0+

LAN_MDI0-

LANGND

RJ45_MIDI1-

RJ45_MIDI0+

LAN_ACTIVITY#

RJ45_MIDI1+

RJ45_MIDI0-

LAN_CT0

RJ45_MIDI0+

RJ45_MIDI0-

LAN_MDI1+

LAN_X1 LAN_X2

RJ45_CT0

LAN_MDI1-

RJ45_CT1

RJ45_MIDI1-

RJ45_MIDI1+

LAN_CT1

VCTRL12

LAN_CS

LAN_SK_LAN_LINK#

LAN_DI

LAN_ACTIVITY#

VCTRL12

LAN_MDI1+

LAN_MDI1-

LAN_MDI0-

LAN_MDI0+

ISOLATEB

LAN_X2

LAN_X1

ISOLATEB

PCIE_PTX_IRX_P3

PCIE_PTX_IRX_N3

LAN_DI

LAN_CS

RJ45_GND

RJ45_CT0_C

RJ45_CT1_C

LAN_ACTIVITY#

LAN_SK_LAN_LINK#

RJ45_MIDI0+ <35>

RJ45_MIDI0- <35>

RJ45_MIDI1- <35>

RJ45_MIDI1+ <35>

PCIE_ITX_C_PRX_P3<10>

PCIE_ITX_C_PRX_N3<10>

CLK_PCIE_LAN#<15>

CLK_PCIE_LAN<15>

CLKREQ_LAN#<15>

PLT_RST#<11,14,19,26,27,32,33>

LAN_PCIE_WAKE#<20>

PCIE_PTX_C_IRX_P3<10>

PCIE_PTX_C_IRX_N3<10>

LAN_POWER_OFF<33>

+3V_LAN

+3V_LAN

+3V_LAN

+LAN_VDD12

+LAN_VDD12

+EVDD12

+EVDD12

+LAN_VDD12

+3VS

+LAN_VDD12

+3V_LAN

+3V_LAN

+3VALW

+3V_LAN

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

RTL8111C/8102E 10/100/1000 LAN

Custom

25 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

LAN Conn.

9/20 D C234001G00

Close to Pin48

Close to Pin1,37,29

Close to Pin45

Close to Pin10,13,30,36

Close to Pin19

Place Close to Chip

40 mils

C1084 0.01U_0603_100V7-M

1 2

R395 300_0402_5%

12

R1057 0_0402_5%

1 2

C621

0.1U_0402_16V4Z

1

2

JRJ45

FOX_JM36113-P1122-7F

CONN@

PR1-

2

PR1+

1

PR2+

3

PR3+

4

PR3-

5

PR2-

6

PR4+

7

PR4-

8

Green LED-

12

Green LED+

11

Yellow LED-

14

Yellow LED+

13

SHLD1 15

SHLD1 16

DETECT PIN1 9

DETCET PIN2 10

G

D

S

Q144

SI2301BDS-T1-E3_SOT23-3

2

13

C631

0.1U_0402_16V4Z

1

2

C628

0.1U_0402_16V4Z

1

2

C1081

1U_0402_6.3V4Z

1

2

C632

0.1U_0402_16V4Z

1

2

R1059 2.49K_0402_1%

1 2

C620

0.1U_0402_16V4Z

1

2

R1067 0_0805_5%@

1 2

C647 0.01U_0402_16V7K

1 2

R1056

100K_0402_5%

@

1 2

R394

75_0402_1%

1 2

C658

1000P_1206_2KV7K

1

2

C1083 0.01U_0603_100V7-M

1 2

C633

10U_0805_10V4Z@

1

2

R391 300_0402_5%

12

C657

68P_0402_50V8K

@

1

2

C662

4.7U_0805_10V4Z

1

2

R1055 3.6K_0402_5%

1 2

Y5

25MHz_20pF_6X25000017

12

C1082

0.1U_0402_16V4Z

1

2

R1061

15K_0402_5%

C488 0.1U_0402_16V7K

12

R1060

1K_0402_1%

12

C1080

0.1U_0402_16V4Z

1

2

C656

68P_0402_50V8K

@

1

2

C485 0.1U_0402_16V7K

12

C648 0.01U_0402_16V7K

1 2

C622

0.1U_0402_16V4Z

1

2

R396

75_0402_1%

1 2

C654

27P_0402_50V8J

1

2

C1077

0.1U_0402_16V4Z

@

1

2

C630

0.1U_0402_16V4Z

1

2

C661

0.1U_0402_16V4Z

1

2

C653

27P_0402_50V8J

1

2

R1058 10K_0402_5%

12

C629

0.1U_0402_16V4Z

1

2

D55

PACDN042Y3R_SOT23-3

@

2

3

1

U19

NS681680

RD+

1

RD-

2

CT

3

CT

6

TD+

7

TD-

8TX- 9

TX+ 10

CT 11

CT 14

RX- 15

RX+ 16

NC

4

NC

5NC 13

NC 12

RTL8102EL

U44

RTL8103EL-GR_LQFP48_7X7

AVDD33 1

MDIP0 2

MDIN0 3

NC 4

MDIP1 5

MDIN1 6

GND

7

NC 8

NC 9

DVDD12 10

NC 11

NC 12

RSET

46

VCTRL12A 48

GND

47

CKXTAL2

42 CKXTAL1

41

NC 40

NC 44

LED0 38

VDD33 37

NC 43

DVDD12 13

GND

14

HSIP

15

HSIN

16

REFCLK_P

17

REFCLK_M

18

VDDTX 19

HSOP

20

HSON

21

GNDTX

22

NC

23

NC

24

LED1/EESK 35

LED2/EEDI/AUX 34

LED3/EEDO 33

EECS 32

DVDD12 36

GND

31

DVDD12 30

VDD33 29

ISOLATEB

28

PERSTB

27

LANWAKEB

26

CLKREQB

25

NC 39

VCTRL12D 45

C1079

10U_0805_10V4Z@

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SMB_CK_DAT1

SMB_CK_CLK1

MINI_PCIE_WAKE#

CLKREQ_NCARD#

PERST#

EXP_CPPE#

EXP_CPPE#

PERST#

PLT_RST#

PLT_RST#

SMB_CK_CLK1

SMB_CK_DAT1

WW_LED#

UIM_RST

UIM_PWR

UIM_CLK

UIM_DATA

UIM_VPP

WW_OFF#

WL_LED#

PLT_RST#

SMB_CK_DAT1

SMB_CK_CLK1

CH_DATA

CH_CLK

MINI_PCIE_WAKE#

WL_OFF#

EXP_CPPE#

CH_CLK

UIM_PWRUIM_DATA

UIM_RST

UIM_PWR

UIM_DATA

UIM_VPP

WW_OFF#

WL_OFF#

UIM_CLK UIMCLK

SMB_CK_CLK1<20>

SMB_CK_DAT1<20>

CLK_PCIE_NCARD<15>

USB20_P11<20>

USB20_N11<20>

PCIE_ITX_C_PRX_N0<10>

PCIE_ITX_C_PRX_P0<10>

PCIE_PTX_C_IRX_P0<10>

PCIE_PTX_C_IRX_N0<10>

CLK_PCIE_NCARD#<15>

CLKREQ_NCARD#<15>

PLT_RST#<11,14,19,25,27,32,33>

SUSP#<28,33,36,38,41>

SYSON<33,36,40>

USB20_N10 <20>

USB20_P10 <20>

CLKREQ_MCARD1#<15>

CLK_PCIE_MCARD1<15>

CLK_PCIE_MCARD1#<15>

PCIE_PTX_C_IRX_P5<10>

PCIE_PTX_C_IRX_N5<10>

PCIE_ITX_C_PRX_P5<10>

PCIE_ITX_C_PRX_N5<10>

MINI_PCIE_WAKE#<20>

WW_LED# <34>

WL_LED# <34>

USB20_P8 <20>

USB20_N8 <20>

CLKREQ_MCARD2#<15>

CH_DATA<31>

CH_CLK<31>

CLK_PCIE_MCARD2<15>

CLK_PCIE_MCARD2#<15>

PCIE_PTX_C_IRX_P2<10>

PCIE_PTX_C_IRX_N2<10>

PCIE_ITX_C_PRX_N2<10>

PCIE_ITX_C_PRX_P2<10>

EXP_CPPE#<20>

BT_COMBO_EN#<21>

WWAN_POWER_OFF<33>

WWOFF# <21>

WLOFF# <21>

+3VS_PEC

+1.5VS_PEC

+3V_PEC

+3VS_PEC

+3V_PEC

+1.5VS_PEC

+3VS_MINI +1.5VS_MINI+3VALW_WWAN+3VS_MINI

+3VALW +3VS +1.5VS

+1.5VS_PEC

+3V_PEC

+3VS_PEC

+3VALW

+1.5VS

+3VS

+3VALW_WWAN

+3VS_MINI

+1.5VS_MINI

+3VS_MINI

+3VALW_WLAN

+3VS_WLAN

+1.5VS_WLAN

+3VS_WLAN

+3VALW

+3VS +1.5VS+3VS_WLAN +1.5VS_WLAN +3VALW_WLAN

+3VS_WLAN

+3VS_MINI

+3VS_MINI+3VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

WLAN/TV tuner/Express Card

Custom

26 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Express Card Power Switch

Mini Card Slot 1---TV tuner / WWAN / Robson

New Card

Near to Express Card slot.

USE TI TPS2231MRGPR

9/20 S P02000B000

9/20 S P01000HS00/SP01000LX00

9/20 S TANDOFF (H=7.5 mm) ES000000D00

9/20 S P02000IQ00

Mini Card Slot 2---WLAN

9/20 S TANDOFF (H=7.5 mm) ES000000D00

9/20 S P01000HS00/SP01000LX00

Max 2.7A

Max 1.3A

Max 0.65A

Max 0.3A Max 0.3A

Max 0.5A

Max 1A Max 0.5A

Max 0.275A

R406

0_0805_5%

1 2

L78

0_1206_5%

PA@

1 2

C665

0.1U_0402_16V4Z

1

2

R47 0_0603_5%

1 2

C784

0.1U_0402_16V7K

@

1

2

JP6

ACES_88266-07001

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7G1 8

G2 9

C782

0.1U_0402_16V4Z

PA@ 1

2

C677

0.1U_0402_16V4Z

RP@ 1

2

C787

4.7U_0805_10V4Z

PA@ 1

2

R421

33_0402_5%

1 2

C1071

4.7U_0805_10V4Z

PA@

1

2

C669

0.1U_0402_16V4Z

1

2

R54

0_0402_5%

RP@

1 2

C670

4.7U_0805_10V4Z

1

2C781

0.01U_0402_16V7K

PA@ 1

2

R1043 0_0603_5%@

1 2

C1094

39P_0402_50V8J

PA@ 1

2

R48

4.7K_0402_5%

12

R1042 0_0603_5%

1 2

C683

0.1U_0402_16V4Z

RP@ 1

2

JEXP

SANTA_130801-5_LTCONN@

GND

1

USB_D-

2

USB_D+

3

CPUSB#

4

RSV

5

RSV

6

SMB_CLK

7

SMB_DATA

8

+1.5V

9

+1.5V

10

WAKE#

11

+3.3VAUX

12

PERST#

13

+3.3V

14

+3.3V

15

CLKREQ#

16

CPPE#

17

REFCLK-

18

REFCLK+

19

GND

20

PERn0

21

PERp0

22

GND

23

PETn0

24

PETp0

25

GND

26

GND

27

GND

28

C671

0.1U_0402_16V4Z

PA@ 1

2

C1070

0.1U_0402_16V4Z

PA@

1

2

R972 0_0603_5%@

12

U21

R5538D001-TR-F_QFN20_4X4~D

RP@

3.3Vin

2

3.3Vin

43.3Vout 3

3.3Vout 5

SYSRST#

6

SHDN#

20

STBY#

1

PERST# 8

OC# 19

RCLKEN

18

AUX_IN

17 AUX_OUT 15

CPPE#

10

CPUSB#

9

NC 16

GND 7

1.5Vin

12

1.5Vin

14 1.5Vout 11

1.5Vout 13

THERMAL_PAD 21

C783

4.7U_0805_10V4Z

PA@ 1

2

C786

0.1U_0402_16V4Z

PA@ 1

2

C1093

39P_0402_50V8J

PA@

1

2

L79

0_0805_5%

PA@

12

C684

0.1U_0402_16V4Z

RP@ 1

2

JP14

FOX_AS0B226-S99N-7F

CONN@

3

344

5

566

7

788

9

910 10

11

11 12 12

13

13 14 14

15

15 16 16

17

17 18 18

19

19 20 20

21

21 22 22

23

23 24 24

25

25 26 26

27

27 28 28

29

29 30 30

31

31 32 32

33

33 34 34

35

35 36 36

37

37 38 38

39

39 40 40

41

41 42 42

43

43 44 44

45

45 46 46

47

47 48 48

49

49 50 50

51

51 52 52

1

122

G1

53

G2

54

G3

55

G3

56

R971 0_0603_5%

PA@

12

C666

4.7U_0805_10V4Z

1

2

C667

0.1U_0402_16V4Z

1

2

C679

0.1U_0402_16V4Z

RP@

12

C685

4.7U_0805_10V4Z

RP@ 1

2

C680

0.1U_0402_16V4Z

RP@

12

C785

0.01U_0402_16V7K

PA@ 1

2

D59

CH751H-40PT_SOD323-2

2 1

C1092

39P_0402_50V8J

PA@

1

2

R1087 0_0603_5%@

1 2

C1095

39P_0402_50V8J

PA@

1

2

R49

0_0402_5%

1 2

G

D

S

Q167

SI2301BDS-T1-E3_SOT23-3

@

2

1 3

C738

39P_0402_50V8J

PA@

1

2

D60

CH751H-40PT_SOD323-2

2 1

R401 0_0603_5%

PA@

1 2

C682

4.7U_0805_10V4Z

RP@ 1

2

C1096

39P_0402_50V8J

PA@

1

2

C681

0.1U_0402_16V4Z

RP@

12

JP13

FOX_AS0B226-S99N-7F

CONN@

3

344

5

566

7

788

9

910 10

11

11 12 12

13

13 14 14

15

15 16 16

17

17 18 18

19

19 20 20

21

21 22 22

23

23 24 24

25

25 26 26

27

27 28 28

29

29 30 30

31

31 32 32

33

33 34 34

35

35 36 36

37

37 38 38

39

39 40 40

41

41 42 42

43

43 44 44

45

45 46 46

47

47 48 48

49

49 50 50

51

51 52 52

1

122

G1

53

G2

54

G3

55

G3

56

R1037

10K_0402_5%@

1 2

C678

4.7U_0805_10V4Z

RP@ 1

2

R407

0_0805_5%

12

C668

0.01U_0402_16V7K

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

XD_CD#

APREXT

PCIE_PTX_IRX_P1

PCIE_PTX_IRX_N1

XDCD0#_SDCD#

XDCD1#_MSCD#

XD_RB#

XD_ALE

XD_SD_D6

XD_SD_D7

XD_RE#

XD_SD_D4

XD_SD_D5

XD_CLE

XDWP#_SDWP#

SDCMD_MSBS_XDWE#

XD_SD_MS_D3

XD_SD_MS_D0

XD_SD_MS_D1

XD_SD_MS_D2

XDCD0#_SDCD#

XDCD1#_MSCD#

XD_RB#

XDWP#_SDWP#

XD_RE#

XD_CLE

CPPE#

SDCMD_MSBS_XDWE#

SDCMD_MSBS_XDWE#

MSCLK

XDCD1#_MSCD#

XD_SD_MS_D0

SDCLK

XD_SD_MS_D3

XD_SD_MS_D2

XD_SD_MS_D1

XD_SD_MS_D0

XD_SD_MS_D3

XD_SD_MS_D2

XD_SD_MS_D1

XD_ALE

XD_CLE

XDWP#_SDWP#

XDCE#

XD_RB#

SDCMD_MSBS_XDWE#

XD_CD#

XD_RE#

XDWP#_SDWP#

XD_SD_D6

XD_SD_D7

XD_SD_D4

XD_SD_D5

XD_SD_MS_D2

XD_SD_MS_D1

XD_SD_MS_D0

XD_SD_MS_D3

XDCD0#_SDCD#

XD_SD_D6

XD_SD_D4

XD_SD_D5

XD_SD_D7

SDCLK

XDCE#

SDCLK

MSCLK

SDCLK_MSCLK_XDCE#

MSCLK XDCE#

CPPE#

XDCD0#_SDCD#

XD_ALE

CR_LED#

PCIE_ITX_C_PRX_P1<10>

PCIE_ITX_C_PRX_N1<10>

PCIE_PTX_C_IRX_P1<10>

PCIE_PTX_C_IRX_N1<10>

PLT_RST#<11,14,19,25,26,32,33>

CLK_PCIE_MCARD0#<15>

CLK_PCIE_MCARD0<15>

CR_CPPE#<20>

CR_WAKE#<21>

+VCC_4IN1+VCC_OUT

+1.8VS_OUT

+3VS_CR

+1.8VS_OUT

+VCC_OUT

+3VS_CR

+VCC_4IN1

+3VS_CR

+1.8VS

+3VS+3VS_CR

+5VS_LED

+3VS

+VCC_OUT +VCC_4IN1

+VCC_4IN1 +VCC_4IN1

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

PCI-E I/F Card Reader-JM385

Custom

27 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Card Reader Connector

Use 0805 type and over 20 mils

trace width on both side

8mA sink current

White LED: VF=3V, IF = 10mA, Res = 200 ohm

use for PWR_EN#

Power Circuit

Strap pin for JMicro

25mA

45mA

58mA

1mA

D3 Normal 30mA Deepest 3mA

Ripple 100mV

Ripple 100mV

Ripple 250mV

Ripple 250mV

place near pin 5 and

pin 10.

20mil

12mil

40mil

L

Place R413,C902 close to JREAD.20; R412,C901

close to JREAD.26; R411,C900 close to JREAD.37

L

At least 20mils

L

Place R455~R457 close to U23.42

R411

100_0402_5%

@

1 2

R369

0_0402_5%

1 2

U22

G5250C2T1U_SOT23-5@

IN

3

EN

4OUT 1

OUT 5

GND

2

R413

100_0402_5%

@

1 2

C6950.1U_0402_16V4Z

12

JMB385

U23

JMB385-LGEZ0A_LQFP48_7X7

XRSTN

1

XTEST

2

APCLKN

3

APCLKP

4APVDD 5

APGND 6

APREXT

7

APRXP

8APRXN

9

APV18 10

APTXN

11

APTXP

12

SEEDAT

13

SEECLK

14

CR1_CD1N

15

CR1_CD0N

16

CR1_PCTLN

17

DV18 18

DV33 19

DV33 20

CR1_LEDN

21

MDIO14 22

MDIO13 23

GND 24

MDIO12 25

MDIO11 26

MDIO10 27

MDIO9 28

MDIO8 29

TAV33 30

GND 31

GND 32

GND 33

NC 34

NC 35

NC 36

DV18 37

PCIES_EN

38

PCIES

39

MDIO7 40

MDIO6 41

MDIO5 42

MDIO4 43

DV33 44

MDIO3 45

MDIO2 46

MDIO1 47

MDIO0 48

R45 10K_0402_5%

12

R106910K_0402_5%

12

R123

150K_0402_5%

@

12

R455 22_0402_5%

12

R124

10K_0402_5%

12

C690

0.1U_0402_16V4Z

1

2

C896

1U_0603_10V4Z

@

1

2

T45PAD

D40

DAN202U_SC70

2

3

1

7 IN 1 CONN

JREAD

TAITW_R015-B10-LM

CONN@

XD-WP

33

XD-D4

7

MS-DATA3 24

MS-DATA0 17

SD-DAT2 30

SD-DAT0 14

SD-CMD 25

MS-DATA1 15

XD-D6

5SD-DAT3 29

SD-DAT1 12

XD-ALE

35

XD-D0

32

SD_CLK 20

XD-D2

9

MS-INS 22

MS-DATA2 19

MS-SCLK 26

XD-RE

38

MS-BS 13

XD-D5

6

XD-D7

4

XD-D1

10

XD-CE

37

XD-R/B

39

XD-D3

8

XD-WE

34

MS-VCC 28

7IN1 GND

11

XD-CLE

36

7IN1 GND

31

SD-VCC 21

XD-VCC

3

XD-CD

40 SD-CD-SW 1

SD-WP-SW 2

7IN1 GND

41

7IN1 GND

42

SD-DAT4 27

SD-DAT5 23

SD-DAT6 18

SD-DAT7 16

R1070

0_0402_5%

1 2

R412

100_0402_5%

@

1 2

R1021

0_0603_5%

12

R121 4.7K_0402_5%

12

R370

470_0402_5%

12

C696

270P_0402_50V7K

1

2

R86200K_0402_5%

12

C694

0.1U_0402_16V4Z

1

2

C892

10U_0805_10V4Z

@1

2

C692

0.1U_0402_16V4Z

1

2

G

D

S

Q53

2N7002_SOT23-3

@

2

13

R106 10K_0402_5%

12

D5

HT-F196BP5_WHITE

21

C686

0.1U_0402_16V4Z

1

2

R454

4.7K_0402_5%

@

12

C693 0.1U_0402_16V7K

1 2

R457 22_0402_5%

12

C895

0.1U_0402_16V4Z@

1

2

R40510K_0402_5%

12

R12210K_0402_5% @

12

C893

0.1U_0402_16V4Z

1

2

R383

0_0805_5%

1 2

C688

0.1U_0402_16V4Z

1

2

R111 4.7K_0402_5%

12

C689

10U_0805_10V4Z

1

2

C687

1U_0402_6.3V4Z

1

2

C900

100P_0402_25V8K

@

1

2

R1020

0_0603_5%

@

12

C902

100P_0402_25V8K

@

1

2

C691

0.1U_0402_16V4Z

1

2

C697 0.1U_0402_16V7K

1 2

R456 22_0402_5%

12

R114

8.2K_0402_5%

12

C901

100P_0402_25V8K

@

1

2

G

D

S

Q54

2N7002_SOT23-3

2

1 3

R409

10K_0402_5%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

HDA_BITCLK_CODEC

EAPD_CODEC

MIC_EXTR

MIC_EXTL

MIC_INR

MIC_INL

LINE_OUT_L

LINE_OUT_R

VREFOUT_B

SENSE

HP_OUTL

HP_OUTR

DOCK_MICR

DOCK_MICL

HDA_SYNC_CODEC

HDA_RST#_CODEC

MONO_INR

SENSEB#

VC_REFA

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

SPDIF_OUT

SUSP#<26,33,36,38,41>

GNDA <29>

EAPD_CODEC <33>

DMIC_DAT <17>

HP_OUTR <29>

INTMIC_DET# <29>

LINE_OUT_L <29>

LINE_OUT_R <29>

VREFOUT_B <29>

EXTMIC_DET# <29>

HP_OUTL <29>

MIC_EXT_L <29>

MIC_EXT_R <29>

MIC_IN_L <29>

MIC_IN_R <29>

DOCK_MIC_L <35>

DOCK_MIC_R <35>

HDA_BITCLK_CODEC<20>

HDA_SDOUT_CODEC<20>

HDA_SDIN0<20>

HDA_SYNC_CODEC<20>

HDA_RST#_CODEC<20>

SB_SPKR<20>

SENSE_B#<35>

DMIC_CLK<17>

JACK_DET# <29,35>

EC_BEEP<33>

SPDIF_OUT <35>

+5VALW +VDDA_CODEC

+3VS_HDA

+3VS

+3VDD_CODEC +VDDA_CODEC

+3VDD_CODEC

+VDDA_CODEC_R

+3VS_HDA

+VDDA_CODEC_R

+VDDA_CODEC_R

+VDDA_CODEC_R+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

Audio Codec-IDT9271B7

Custom

28 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

CODEC POWER

W=40Mil

300mA

(4.75V(4.56~4.94V))

Use an 80mil to

connection or place

a 1206 resistor under

CODEC with double

vias.

GNDAGND

DOCK MIC

HP Jack & Dock

Internal SPKR.

Internal MIC

Jack MIC

F

H

39.2K

5.11K

SENSE A

10K

Port

D

G

A

20K

C

Resistor

B

10K

5.11K

39.2K E

PortResistor

20K

SENSE B

T21PAD

C745

33P_0402_50V8K@

1

2

C749

0.1U_0402_16V4Z

@

1 2

R198

0_1206_5%

1 2

U32

G9191-475T1U_SOT23-5

IN

1

GND

2

SHDN

3

OUT 5

BYP 4

R523 10K_0402_5%

1 2

C984 0.022U_0603_25V7KPRM@

1 2

C986 1U_0603_10V6KRP@

1 2

R230

22_0402_5%RP@

1 2

C913 1U_0603_10V4Z

12

C985 1U_0603_10V6KRP@

1 2

R1006

0_0402_5%

@

1 2

C982 1U_0603_10V6K

1 2

R195

0_0805_5%

@

1 2

C979

0.1U_0402_16V4Z

RP@ 1

2

R422 0_0603_5%PR@

1 2

C983 0.022U_0603_25V7KPRM@

1 2

R522 33_0402_5%

1 2

R978

BLM18BD601SN1D_0603

1 2

C956 0.1U_0402_16V4Z

1 2

C733

0.1U_0402_16V4Z

1

2

R563 47K_0402_5%@

1 2

C1046

0.1U_0402_16V4Z

1

2

R570 10K_0402_1%

1 2

C728 0.1U_0402_16V4Z

1 2

R910 39.2K_0402_1%RP@ 1 2

R525

47_0402_5%@

12

C744

10U_0805_10V4Z

1 2

C955

0.1U_0402_16V4Z

1 2

R524 47K_0402_5%

1 2

C729

2.2U_0805_16V4Z

1

2

C981 1U_0603_10V6K

1 2

C730

0.1U_0402_16V4Z

1

2

R885

BLM18BD601SN1D_0603

1 2

C734

1U_0603_10V4Z

1

2

C746

0.1U_0402_16V4Z

@

1 2

C731

1U_0603_10V4Z

1

2

R569 20K_0402_1%

1 2

U27

92HD71B7X5NLGXA1X8_QFN48_7X7

DVDD_CORE

1

BITCLK

6

VOL_DN/DMIC_1/GPIO 2 4

SDO

5

VOL_UP/DMIC_0/GPIO 1 2

DVDD_IO

3

SDI_CODEC

8

DVSS**

7

PCBEEP

12

RESET#

11

SYNC

10

DVDD_CORE*

9

SENSE_A 13

PORTE_L 14

PORTE_R 15

PORTF_L 16

PORTF_R 17

NC

18

NC

19

NC

20

PORTB_L 21

PORTB_R 22

PORTC_L 23

PORTC_R 24

PORTD_R 36

PORTD_L 35

SENSE_B / NC

34

CAP2

33

MONO_OUT

32

VREFOUT-E / GPIO 4 31

GPIO 3 30

VREFOUT-C 29

VREFOUT-B 28

VREFFILT

27

AVSS1*

26

AVDD1*

25

SPDIF OUT0 48

EAPD/ SPDIF OUT 0 or 1 / GPIO 0 47

DMIC_CLK

46

SPDIF OUT1 / GPIO 7 45

GPIO 6 44

GPIO 5 43

AVSS2**

42

PORTA_R 41

NC / OTP

40

PORTA_L 39

AVDD2**

38

NC

37

R979

0_0603_5%

1 2

R548 5.1K_0402_1%

1 2

R911

0_0603_5%

RM@

12

C748

0.1U_0402_16V4Z

@

1 2

C732

0.1U_0402_16V4Z

1

2

R571 39.2K_0402_1%

1 2

R982 5.1K_0402_1%

1 2

C747

0.1U_0402_16V4Z

@

1 2

C951 0.1U_0402_16V4Z

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

HP_OUT_R

HP_OUT_L

EXTMIC_DET#

HP_DET#

CIR_ IN

MIC_EXT_R

MIC_EXT_L

MIC_EXT_L

MIC_EXT_R

HP_OUT_L

HP_OUT_R

SPKL-

SPKL+

SPKR-

EC_MUTE#

SPKR+

SPKL+

SPKL-

SPKR+

SPKR-

MIC_IN_R

MIC_IN_R

MIC_IN_L

MIC_IN_L

HP_DET#

DOCK_LOUT_C_R

DOCK_LOUT_C_L

DOCK_LOUT_CR_R

DOCK_LOUT_CR_LDOCK_LOUT_L

DOCK_LOUT_R

GNDA_DOCK_1GNDA_DOCK

GNDA_DOCK_2

MIC_IN_R<28>

MIC_IN_L<28>

INTMIC_DET#<28>

ANA_MIC_DET<33>

EXTMIC_DET#<28>

CIR_IN<33,35>

MIC_EXT_L<28>

MIC_EXT_R<28>

VREFOUT_B<28>

JACK_DET#<28,35>

HP_OUTR<28>

HP_OUTL<28>

LINE_OUT_L<28>

LINE_OUT_R<28>

EC_MUTE#<33>

DOCK_LOUT_C_L <35>

DOCK_LOUT_C_R <35>

GNDA_DOCK_1 <35>

GNDA_DOCK_2 <35>

+3VS

+VDDA_CODEC

+5VL

+VDDA_CODEC

B+

+3VALW

+5VS+5VAMP

+5VS

+3VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

AMP & Audio Jack

Custom

29 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

SPEAKER

INTMIC IN

Audio/B & CIR

EXTMIC IN

HP OUT For M/B

Keep 10 mil width

15.6dB

GAIN0 GAIN1 Av(inv)

0 6dB

15.6dB

21.6dB

0

1

0

1

1

9/20 S P02000H700/SP02000H900

Close to CODEC U27

Close to CODEC U27

0 1 10dB

9/20 S P02000H800

HP OUT For Docking

R909

0_0402_5%

12

JP20

E&T_3806-F04N-02RCONN@

1

1

2

2

3

3

4

4

GND1

5

GND2

6

C760

100P_0402_50V8J

1

2

R973

10K_0402_5%

RP@

1 2

R908

4.7K_0402_5%

12

R969

60.4_0603_1%

RP@

1 2

C1041 0.022U_0603_25V7K

1 2 C743

1U_0603_10V4Z

PRM@

1 2

C1054 47P_0402_50V8J

1 2

D61

PSOT24C_SOT23-3

PRM@

2

3

1

R968

60.4_0603_1%

RP@

1 2

R1003

100K_0402_5%

12

+

C776 150U_Y_6.3VM

RP@

1 2

C1051

0.1U_0402_16V4Z

1

2

+

C773 150U_Y_6.3VM

1 2

R974

10K_0402_5%

RP@

1 2

Q145A

2N7002DW-7-F_SOT363-6

RP@

61

2

C742

1U_0603_10V4Z

1 2

R1001

100K_0402_5%

12

C766

10U_0805_10V4Z

1

2

C761

100P_0402_50V8J

1

2

R125

0_0402_5%

@

12

G

D

S

Q151

2N7002_SOT23-3

PR@ 2

13

Q148A

2N7002DW-7-F_SOT363-6RP@

61

2

R906

1K_0402_5% PRM@

12

R975

330K_0402_5%

RP@

12

R1005

0_0402_5%

12

+

C774 150U_Y_6.3VM

1 2

R977 0_0603_5%RP@

1 2

G

D

S

Q161

2N7002_SOT23-3

RP@

2

13

R414

0_0402_5%

RM@

1 2

C1040 0.022U_0603_25V7K

1 2

R1002

0_0402_5%

12

R955 10K_0402_5%PRM@

12

JP43

ACES_87213-1400GCONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

C1052 47P_0402_50V8J

1 2

R1004

100K_0402_5%@

12

C762

100P_0402_50V8J

1

2

R907

4.7K_0402_5%

12

C1049 0.022U_0603_25V7K

1 2

C1050 0.022U_0603_25V7K

1 2

JP42

ACES_88231-04001

CONN@

1

1

2

2

3

3

4

4

GND1

5

GND2

6

Q145B

2N7002DW-7-F_SOT363-6

RP@

3

5

4

C763

100P_0402_50V8J

1

2

Q147A

2N7002DW-7-F_SOT363-6RP@

6 1

2

R905

4.7K_0402_5%

PR@

12

+

C775 150U_Y_6.3VM

RP@

1 2

G

D

S

Q160

2N7002_SOT23-3

PR@ 2

13

C767

0.1U_0402_16V4Z

1

2

C1055 47P_0402_50V8J

1 2

R103

10K_0402_5%

PA@

12

U28

TPA6017A2_TSSOP20

GND4

1GND3

11 GND2

13 GND1

20

VDD 16

PVDD1 15

RIN-

17

BYPASS 10

NC 12

LOUT- 8

LOUT+ 4

ROUT- 14

ROUT+ 18

RIN+

7

LIN-

5

LIN+

9

GAIN0 2

GAIN1 3

PVDD2 6

SHUTDOWN

19

THERMAL PAD

21

Q148B

2N7002DW-7-F_SOT363-6RP@

3

5

4

R1000

100K_0402_5%

@

12

R951

100K_0402_5%

PR@

12

R904

4.7K_0402_5%

PRM@

12

R126

0_0402_5%

12

Q147B

2N7002DW-7-F_SOT363-6RP@

3

5

4

C1053 47P_0402_50V8J

1 2

R594

0_1206_5%

1 2

C1044

1U_0805_50V4Z

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SMB_CK_CLK0

SMB_CK_DAT0

ACCEL_INT <19>

HDD_HALTLED <34>

SMB_CK_DAT0 <8,9,15,20>

SMB_CK_CLK0 <8,9,15,20>

+3VS_ACL_IO

+3VS_ACL

+3VS_ACL+3VS +3VS_ACL_IO

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

Accelerometer

Custom

30 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

ACCELEROMETER

0011101b

L

Must be placed in the center of the system.

VDDIO absolute man

rating is VDD+0.1

D44

CH751H-40PT_SOD323-2

RP@

2 1

R999 10K_0402_5%

RP@

12

C1030

0.1U_0402_16V4Z

RP@ 1

2

C1031

10U_0805_6.3V6M

RP@

1

2

U63

LIS302DLTR_LGA14_3x5

RP@

SCL / SPC 14

GND

2

Reserved

3

GND

4

GND

5

CS

7

Vdd_IO

1

Vdd

6

SDA / SDI / SDO 13

SDO 12

Reserved 11

GND 10

INT 2 9

INT 1 8

R998

0_0402_5%

RP@

1 2

R997

0_0402_5%

RP@

1 2

R959 0_0603_5%

RP@

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

USB20_P6

USB20_N6

USB_EN#

SATA_RXP2

SATA_RXN2

SATA_TXP2

SATA_TXN2

USB_EN#

USB_EN#

USB20_N7

USB20_P7

USB20_N2_R

USB20_P2_R

SATA_TXP2

SATA_TXN2

USB20_N2_R

USB20_P2_R

BT_LED

USB20_P6

USB20_N6

USB20_N7

+3VS_FB

+3VS_FB

USB20_P7

BT_LED

USB20_P6

USB20_N6

SATA_TXP2<21>

SATA_TXN2<21>

SATA_RXN2_C<21>

SATA_RXP2_C<21>

USB_EN#<33>

USB20_N0<20>

USB20_P0<20>

USB20_N1<20>

USB20_P1<20>

USB20_P7<20>

USB20_N7<20>

BT_OFF<21>

USB20_P2<20>

USB20_N2<20>

BT_LED <34>

CH_DATA <26>

CH_CLK <26>

USB20_N6 <20>

USB20_P6 <20>

+3VAUX_BT+3VS

+3VAUX_BT

+USB_VCCA+5VALW

+USB_VCCA +5VALW

+3VS+3VALW

+USB_VCCA

+USB_VCCA

+3VAUX_BT

+5VALW

+3VAUX_BT

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

USB, BT, eSATA,FPR

Custom

31 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

BT Connector

Check BT power consumption < 1A

W=100mils

Left side USB CONNECTOR Right side USB 0&1 Board Conn

9/20 S P02000DX00

9/20 S P02000HC00/SP02000HB00

9/20 S P01000B000

Finger printer

Max 0.5A

Max 2.5A

USB

ESATA

JESAT

TYCO_1759576-1

CONN@

VBUS

1

D-

2

D+

3

GND

4

GND

5

A+

6

A-

7

GND

8

B-

9

B+

10

GND

11

GND

12

GND

13

GND

14

GND

15

L51

WCM-2012-900T_4P

1

1

4

433

22

JP47

ACES_87213-1000G

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

GND1

11

GND2

12

U40

TPS2061IDGN_MSOP8~N

GND

1

IN

2

OC# 5

OUT 6

OUT 8

IN

3

EN#

4

OUT 7

+

C789

150U_D_6.3VM

1

2

C791

1000P_0402_50V7K

1

2

C790

0.1U_0402_16V4Z

1

2

C801

4.7U_0805_10V4Z

1

2

C832

0.1U_0402_16V4Z

1

2

C792 1000P_0402_50V7K

1 2

C1121

0.1U_0402_16V4Z

1

2

C788

4.7U_0805_10V4Z

1

2

C799

0.01U_0402_16V7K

1

2

C800

0.1U_0402_16V4Z

1

2

R520

10K_0402_5%

1 2

D12

PRTR5V0U2X_SOT143-4

@

GND 1

IO1 2

IO2

3

VIN

4

R519

100K_0402_5%

12

C1109

820P_0402_25V7K

1

2

C802 0.1U_0402_16V4Z

1 2

R517 1K_0402_5%@1 2

D11

PRTR5V0U2X_SOT143-4@

GND 1

IO1 2

IO2

3

VIN

4

G

D

S

Q24 SI2301BDS-T1-E3_SOT23-3

2

13

JP55

JST_SM06B-XSRK-ETB(HF)

CONN@

11

22

33

44

55

66

GND 7

GND 8

C798

1U_0603_10V4Z

1

2

JP39

ACES_85201-06051

CONN@

GND

7

GND

8

1

1

2

2

3

3

4

4

5

5

6

6

R581

0_0603_5%

1 2

JP32

ACES 87213-0800G

CONN@

11

22

33

44

55

66

77

88

GND1 9

GND2 10

C793 1000P_0402_50V7K

1 2

D16

PRTR5V0U2X_SOT143-4@

GND 1

IO1 2

IO2

3

VIN

4

D21

PRTR5V0U2X_SOT143-4

@

GND 1

IO1 2

IO2

3

VIN

4

G

D

S

Q31 SI2301BDS-T1-E3_SOT23-3@

2

13

R518 1K_0402_5%@1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SPI_CS# INT_SPI_CS#

SPI_CLK_R

EC_SO_SPI_SI_R EC_SI_SPI_SO_R

LPC_AD2

CLK_PCI_SIO

PLT_RST#

LPC_DRQ#

LPC_AD1

LPC_FRAME#

SIRQ

LPC_AD0

LPC_AD3

EC_SI_SPI_SO <33>

SMB_EC_CK1<6,33,34,37>

SMB_EC_DA1<6,33,34,37>

SPI_CLK<33>

EC_SO_SPI_SI<33>

SPI_CS#<33>

LPC_FRAME#<19,33>

LPC_AD0 <19,33>

PLT_RST# <11,14,19,25,26,27,33>

LPC_AD2 <19,33>

SIRQ<19,33>

LPC_AD3<19,33>

LPC_AD1<19,33>

CLK_PCI_SIO <19>

LPC_DRQ# <19>

+3VL

+3VALW

+3VAL

+3VALW

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

BIOS ROM/Debug Tool

Custom

32 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

SPI Flash (16Mb*1)

20mils

LPC Debug Port

9/20 ??????

L

Need add back R221 if no ext BIOS design U30 install.

Ripely 2.0 will support 16Mb SPI ROM

SA00001IT00

H31

DEBUG_PAD@

1

2

3

4

56

7

8

9

10

R232

22_0402_5%

@

1 2

U29

WIESON G6179 8P SPI

CONN@

S

1

VCC

8

Q2

HOLD

7

VSS 4

D

5

C

6

W

3

C486

22P_0402_50V8J

@

1

2

R996 0_0402_5%

1 2

R227 0_0402_5%

1 2

R221 0_0402_5%

1 2

U31

AT24C16AN-10SI-2.7_SO8

@

A0 1

A1 2

SDA

5SCL

6

VCC

8

A2 3

GND 4

WP

7

R995 0_0402_5%@

1 2

C803

0.1U_0402_16V4Z

1

2

R521

100K_0402_5%

12

C484

0.1U_0402_16V4Z

1

2

R223 0_0402_5%

12

R526

100K_0402_5%

12

&U29

SA00001IT00

45@

R229 0_0402_5%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

LID_SW#

ON /OFF#

KSO8

KSO12

KSI7

KSO13

KSO4

KSO14

FSTCHG

KSO5

KSO0

KSO1

KSO6

KSO9

KSO7

KSO2

KSO3

BATT_OVP

KSO11

KSO10

SYSONSMB_EC_CK2

SMB_EC_DA2

SB_PWRGD

ECRST#

ACOFF

SLP_S3#

TP_CLK

TP_DATA

ON/OFFBTN_LED#

SLP_S5#

E51_RXD

PWRBTN_OUT#

TP_BTN#

E51_TXD

KSI6

KSI1

KSI5

KSI2

KSO15

KSI4

BKOFF#

EC_RSMRST#

SMB_EC_CK1

SMB_EC_DA1

SUSP#

TP_LED#

NMI_DBG#

BAT_LED#

EC_SMI#

LPC_LFRAME#

LID_SW#

IR EF

KSO17

SIRQ

GATEA20

LPC_AD2

KSO16

LPC_AD1

LPC_AD3

KB_RST#

LPC_AD0

ECAGND

ECAGND

EC_PWM

TP_CLK

PLT_RST#

TP_DATA

CLK_PCI_EC

FAN_PWM

EC_SCI#

BATT_TEMP

C R Y2

KSI3

KSI0

C R Y1

EC_BEEP

KSI5

KSO11

KSO0

KSO1

KSI0

KSI7

KSO13

KSO2

KSI2

KSO4

KSO8

KSO15

KSO10

KSO3

KSO5

KSI4

KSO7

KSO14

KSI3

KSO6

KSO12

KSI6

KSI1

KSO9

KSI5

KSO11

KSO0

KSO1

KSI0

KSI7

KSO13

KSO2

KSI2

KSO4

KSO8

KSO15

KSO10

KSO3

KSO5

KSI4

KSO7

KSO14

KSI3

KSO6

KSO12

KSI6

KSI1

KSO9

VR_ON

AC_IN_EC

SUSP# SYS ON

SMB_EC_CK2

SMB_EC_DA2

SMB_EC_DA1

SMB_EC_CK1

DOCK_VOL_UP#

DOCK_VOL_DWN#

TP_BTN#

H_THERMTRIP#_EC

CIR_ IN

LAN_POWER_OFF E51_RXD

WL_BLUE_BTN

WL_BLUE_BTN

E51_TXD

ESB_DAT

EC_CLK

EC_DAT

EC_CLK

EC_DAT

EC_CLK

EC_DAT

ESB_CLK

NB_OTP

PLT_RST#<11,14,19,25,26,27,32>

ANA_MIC_DET <29>

CONA#<35>

LPC_AD1<19,32>

CIR_IN <29,35>

LPC_FRAME#<19,32>

SIRQ<19,32>

LPC_AD2<19,32>

LPC_AD0<19,32>

LPC_AD3<19,32>

CLK_PCI_EC<19,23>

SMB_EC_CK1<6,32,34,37>

EC_SCI#<20>

SMB_EC_DA1<6,32,34,37>

EC_SO_SPI_SI <32>

SMB_EC_CK2<6>

SMB_EC_DA2<6>

EC_SI_SPI_SO <32>

SPI_CS# <32>

SPI_CLK <32>

BATT_OVP <37>

BATT_TEMP <37>

DAC_BRIG <17>

SYSON <26,36,40>

FAN_PWM <4>

EC_RSMRST# <20>

EC_ON <36,39>

BAT_LED# <34>

LID_SW#<34>

ADP_I <38>

VR_ON <43>

GATEA20<20>

KB_RST#<20>

EC_THERM# <21>

ON/OFFBTN_LED# <34>

EC_LID_OUT# <20>

SLP_S3#<20>

SLP_S5#<20>

EC_SMI#<20>

TP_CLK <34>

TP_DATA <34>

ON/OFF#<34>

SB_PWRGD <6,20,43>

BKOFF# <17>

EAPD_CODEC <28>DIM_LED<36>

TP_BTN# <34>

MUTE_LED <35>

ACOFF <38>

I2C_INT <34>

DOCK_VOL_DWN# <35>

DOCK_VOL_UP# <35>

USB_EN# <31>

EC_MUTE# <29>

STD_ADP <38>

ENBKL <11>

AC_SET <38>

VLDT_EN<36>

TP_LED# <34>

FSTCHG <38>

ADP_ID <37>

PCI_SERR# <19>

HDARST#<20,23>

IREF <38>

CAPS_LED# <34>

EC_BEEP <28>

WL_BLUE_LED# <34>

AC_IN <21,38>

NUM_LED#<34>

DOCK_SLP_BTN#<35>

PWRBTN_OUT# <20>

VCTRL <38>

VGATE <43>

SUSP# <26,28,36,38,41>

H_THERMTRIP#_EC<6>

LAN_POWER_OFF<25>

WL_BLUE_BTN<34>

VFIX_EN <43>

AC_LED# <37>

ESB_DAT<34>

ESB_CLK<34>

EC_PWM <17>

WWAN_POWER_OFF <26>

NB_OTP <37>

+EC_AVCC

+3VL_EC

+3VL_EC

+EC_AVCC

+3VL_EC

+5V_TP

+3VL_EC+3VL

+3VL_EC

+3VL_EC

+3VS

+3VL

+3VS

+3VS

+5VS_LED

+5VL

+3VL +3VL_EC

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

EC KB926/KB conn

Custom

33 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

KB Back Light Conn

For EMI

EC DEBUG port

Need 4.7uf for 926 C version

9/20 S P01000KC00/SP010009O10

9/20 S P01000FF00/SP01000G300

Keyboard Connector

L

TP_LED#=L, T/P disable

TP_LED#=float (GPO), T/P enable

02/15 Remove JP34 and

reserve R1068 for EC debug.

02/22 Add R1076, C1104 and R1077 for EMI request.

L

Please close to EC.

1/19 Change EC P/N to D3 version

R531

4.7K_0402_5%

12

C807

1000P_0402_50V7K

1

2

R547

0_0402_5%

1 2

C822 100P_0402_25V8K@1 2

C758 100P_0402_25V8K@1 2

C884 100P_0402_25V8K@1 2

C609 100P_0402_25V8K@1 2

C756 100P_0402_25V8K@1 2

C876 100P_0402_25V8K@1 2

C875 100P_0402_25V8K@1 2

C885 100P_0402_25V8K@1 2

C826 100P_0402_25V8K@1 2

JP48

ACES_85201-04051

CONN@

11

22

33

44

G1

5

G2

6

R527

0_0805_5%

1 2

C887 100P_0402_25V8K@1 2

C886 100P_0402_25V8K@1 2

R513

10K_0402_5%

1 2

C878 100P_0402_25V8K@1 2

C888 100P_0402_25V8K@1 2

C811

0.1U_0402_16V4Z

12

C809

1000P_0402_50V7K

1

2

LPC & MISC

Int. K/B

Matrix

SM Bus

GPIO

GPIO

AD Input

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Fla sh ROM

G PO

GPI

U33

KB926QFC0_LQFP128_14X14

GA20/GPIO00

1

KBRST#/GPIO01

2

SERIRQ#

3

LFRAME#

4

LAD3

5

PM_SLP_S3#/GPIO04

6

LAD2

7

LAD1

8

VCC 9

LAD0

10

GND

11

PCICLK

12

PCIRST#/GPIO05

13

PM_SLP_S5#/GPIO07

14

EC_SMI#/GPIO08

15

LID_SW#/GPIO0A

16

SUSP#/GPIO0B

17

PBTN_OUT#/GPIO0C

18

EC_PME#/GPIO0D

19

SCI#/GPIO0E

20

INVT_PWM/PWM1/GPIO0F 21

VCC 22

BEEP#/PWM2/GPIO10 23

GND

24

EC_THERM#/GPIO11

25

FANPWM1/GPIO12 26

ACOFF/FANPWM2/GPIO13 27

FAN_SPEED1/FANFB1/GPIO14

28

FANFB2/GPIO15

29

EC_TX/GPIO16

30

EC_RX/GPIO17

31

ON_OFF/GPIO18

32

VCC 33

PWR_LED#/GPIO19

34

GND

35

NUMLED#/GPIO1A

36

ECRST#

37

CLKRUN#/GPIO1D

38

KSO0/GPIO20

39

KSO1/GPIO21

40

KSO2/GPIO22

41

KSO3/GPIO23

42

KSO4/GPIO24

43

KSO5/GPIO25

44

KSO6/GPIO26

45

KSO7/GPIO27

46

KSO8/GPIO28

47

KSO9/GPIO29

48

KSO10/GPIO2A

49

KSO11/GPIO2B

50

KSO12/GPIO2C

51

KSO13/GPIO2D

52

KSO14/GPIO2E

53

KSO15/GPIO2F

54

KSI0/GPIO30

55

KSI1/GPIO31

56

KSI2/GPIO32

57

KSI3/GPIO33

58

KSI4/GPIO34

59

KSI5/GPIO35

60

KSI6/GPIO36

61

KSI7/GPIO37

62

BATT_TEMP/AD0/GPIO38 63

BATT_OVP/AD1/GPIO39 64

ADP_I/AD2/GPIO3A 65

AD3/GPIO3B 66

AVCC 67

DAC_BRIG/DA0/GPIO3C 68

AGND

69

EN_DFAN1/DA1/GPIO3D 70

IREF/DA2/GPIO3E 71

DA3/GPIO3F 72

CIR_RX/GPIO40 73

CIR_RLC_TX/GPIO41 74

AD4/GPIO42 75

SELIO2#/AD5/GPIO43 76

SCL1/GPIO44

77

SDA1/GPIO45

78

SCL2/GPIO46

79

SDA2/GPIO47

80

KSO16/GPIO48

81

KSO17/GPIO49

82

PSCLK1/GPIO4A 83

PSDAT1/GPIO4B 84

PSCLK2/GPIO4C 85

PSDAT2/GPIO4D 86

TP_CLK/PSCLK3/GPIO4E 87

TP_DATA/PSDAT3/GPIO4F 88

FSTCHG/SELIO#/GPIO50 89

BATT_CHGI_LED#/GPIO52 90

CAPS_LED#/GPIO53 91

BATT_LOW_LED#/GPIO54 92

SUSP_LED#/GPIO55 93

GND

94

SYSON/GPIO56 95

VCC 96

SDICS#/GPXOA00 97

SDICLK/GPXOA01 98

SDIDO/GPXOA02 99

EC_RSMRST#/GPXO03 100

EC_LID_OUT#/GPXO04 101

EC_ON/GPXO05 102

EC_SWI#/GPXO06 103

ICH_PWROK/GPXO06 104

BKOFF#/GPXO08 105

WL_OFF#/GPXO09 106

GPXO10 107

GPXO11 108

SDIDI/GPXID0 109

PM_SLP_S4#/GPXID1 110

VCC 111

ENBKL/GPXID2 112

GND

113

GPXID3 114

GPXID4 115

GPXID5 116

GPXID6 117

GPXID7 118

SPIDI/RD# 119

SPIDO/WR# 120

VR_ON/XCLK32K/GPIO57 121

XCLK1

122

XCLK0

123 V18R 124

VCC 125

SPICLK/GPIO58 126

AC_IN/GPIO59 127

SPICS# 128

R46 10K_0402_5%

1 2

C823 100P_0402_25V8K@1 2

C757 100P_0402_25V8K@1 2

D54

CH751H-40PT_SOD323-2

2 1

R536

100K_0402_5%

12

R528

4.7K_0402_5%

12

C824 100P_0402_25V8K@1 2

L80

0_0603_5%

12

R1077 0_0402_5%

1 2

R1050

10K_0402_5%

1 2

R589

10K_0402_5%

12

R542 0_0402_5%

RP@

1 2

C814 4.7U_0805_10V4Z

12

R539

100K_0402_5%

12

C769 100P_0402_25V8K@1 2

C816 0.1U_0402_16V4Z

1 2

R533

47K_0402_5%

1 2

C759 100P_0402_25V8K@1 2

C768 100P_0402_25V8K@1 2

C808

0.1U_0402_16V4Z

1

2

C806

0.1U_0402_16V4Z

1

2

C1073

100P_0402_50V8J

1 2

+

C1105

22U_A_4VM

@

1

2

R541 10K_0402_5%

12

C213 100P_0402_25V8K@1 2

R1076 0_0402_5%

1 2

C813

15P_0402_50V8J

1 2

R535

10K_0402_5%

1 2

R530

33_0402_5%@

1 2

C764 100P_0402_25V8K@1 2

R532

4.7K_0402_5%

12

R1068

0_0603_5%

@

1 2

C805

0.1U_0402_16V4Z

1

2

R1044 100K_0402_5%

1 2

Y7

32.768KHZ_12.5PF_Q13MC30610003

OUT 4

IN 1

NC

3

NC

2

C815

15P_0402_50V8J

1 2

R544

0_0402_5%

1 2

R538

10K_0402_5%

12

L81

0_0603_5%

1 2

R529

4.7K_0402_5%

12

C754 100P_0402_25V8K@1 2

C812

0.01U_0402_16V7K

1 2

C1104

33P_0402_50V8K

@

1

2

R516

150_0603_1%

12

R1040

150K_0402_5%

12

R545

20M_0402_5%

@

12

R514 4.7K_0402_5%

1 2

JP33

ACES_85201-24051

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

GND1

25

GND2

26

R1063 10K_0402_5%

12

R543

4.7K_0402_5%

1 2

C877 100P_0402_25V8K@1 2

C810

15P_0402_50V8J@

1 2

C825 100P_0402_25V8K@1 2

R534

10K_0402_5%

1 2

R590

10K_0402_5%

12

R515 4.7K_0402_5%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

TP_DATA

TP_CLK

TP_DATA

TP_CLK

ON/OFFBTN_LED#

HDA_SDIN1_MDC

ON/OFFBTN_LED#

ON /OFF#

TP_BTN#

TP_LED#

WL/WW_LED#

WL_BLUE_LED#

WL_BLUE_LED#

ESB_CLK1

EC_CK1

ESB_DAT1

+3VL_R

EC_DA1

ON/OFFBTN_LED#

ON /OFF#

EC_CK1

EC_DA1

I2C_INT

ESB_CLK1

ESB_DAT1

I2C_INT

TP_CLK <33>

TP_DATA <33>

LID_SW#<33>

ON/OFF#<33>

ON/OFFBTN_LED#<33>

HDD_HALTLED <30>

CAPS_LED#<33>

HDA_BITCLK_MDC <20>

HDA_SYNC_MDC<20>

HDA_SDIN1<20>

HDA_SDOUT_MDC<20>

HDA_RST#_MDC<20>

SYSON#<35,36,42>

TP_BTN# <33>

TP_LED# <33>

BAT_LED#<33>

WL_LED# <26>

WW_LED# <26>

BT_LED <31>

WL_BLUE_LED#<33>

SATA_LED#<21>

HDD_HALTLED# <21>

SMB_EC_CK1<6,32,33,37>

NUM_LED#<33>

ESB_CLK<33>

I2C_INT<33>

ESB_DAT<33>

WL_BLUE_BTN<33>

SMB_EC_DA1<6,32,33,37>

+5V_TP

+3VL

+5VS_LED

+5VALW_LED

+5VS_LED

+3VS

+3VS

+3VS

+5VALW_LED

+5VALW +5V_TP

+3VALW

+5VS_LED

+5VS

+5VALW_LED

+3VS

+3VS

+5VS

+3VS

+3VL_CAP

+5VS_LED

+5VALW_LED

+3VL

+3VL_CAP+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

TP,MDC,ON/OFF,S/W,LED,Reed

Custom

34 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

9/20

SP0100 0KC00/SP01E000900

M/B TO TP/B

Reed switch BOARD.

9/20 S P01000J100

HDD/G-Sensor LED

CAPS LOCK LED

WHITE

POWER LED

WHITE

MDC 1.5 Conn.

ON/OFF Button Connector

9/20 S TANDOFF (H= 5.0 mm) ES000000800

Battery Charge LED

White LED: VF=3V, IF = 10mA, Res = 200 ohm

Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

TP ON/OFF

TouchPAD ON/OFF LED

T/P Enable (TP_LED#=L)-> White

T/P Disable (TP_LED#=X)-> Amber

WLAN and BT LED inform pin to KBC

WHITE

Max 0.5A

Max 0.5A

9/20 S P01000H400

SWITCH BOARD.

ENE ESB

CY SMB_EC

02/22 Reserve for EMI request.

L

Please close to JP36

11/11 Del reserved LDO for ENE cap board

C777

10P_0402_50V8J@

1

2

Q7A

2N7002DW-7-F_SOT363-6

61

2

R20

10K_0402_5%

12

C1103

33P_0402_50V8K

@

12

R554

0_0603_5%RP@

12

C1100

0.1U_0402_16V4Z

1

2

R989

47K_0402_5%

1 2

R1025

100K_0402_5%

12

G

D

S

Q55

2N7002_SOT23-3 2

13

R555

0_0603_5%RM@

12

G

D

S

Q85

SI2301BDS-T1-E3_SOT23-3

@

2

13

R1041

10K_0402_5%@

12

SW1

SMT1-05-A_4P

3

2

1

4

5

6

R985

10K_0402_5%

@

12

R984

200_0402_5%

12

JP36

ACES_85201-1005N

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

GND

11

GND

12

JP1

ACES_85201-04051

CONN@

1

1

2

2

3

3

4

4G1 5

G2 6

R496

10_0402_5%@

1 2

R1048 47_0402_5%RP@

1 2

D31

PSOT24C_SOT23-3

2

3

1

JP40

ACES_85201-04051

CONN@

1

1

2

2

3

3

4

4G1 5

G2 6

R1046 0_0402_5%RP@

1 2

WHITE

YELLOW

D19

HT-297UY5/BP5_YELLOW-WHITE

PRM@

21

43

D57

CH751H-40PT_SOD323-2

2 1

C821

100P_0402_50V8J

@

1

2

R1065 0_0402_5%RM@

1 2

R988

200_0402_5%

RP@

12

D6

HT-F196BP5_WHITE

21

D8

HT-F196BP5_WHITE

21

R552

470_0402_5%

1 2

WHITE

YELLOW

D18

HT-297UY5/BP5_YELLOW-WHITE

21

43

G

D

S

Q156

2N7002_SOT23-3@

2

13

C820

100P_0402_50V8J

@

1

2

R558 10K_0402_5%RM@

12

PJP605

PAD-OPEN 2x2m

@

21

R1008 0_0402_5%PA@

1 2

R550

200_0402_5%

1 2

R1074

0_0402_5%

RP@

12

R987

200_0402_5%

12

R1047 0_0402_5%

RP@

1 2

JP37

ACES_85201-04051

CONN@

11

22

33

44

G1

5

G2

6

R1038

10K_0402_5%@

12

C819

0.1U_0402_16V4Z

1

2

C1098

4.7U_0603_6.3V6K

1

2

WHITE

YELLOW

D17

HT-297UY5/BP5_YELLOW-WHITE

PA@

21

43

C1119

0.1U_0402_16V4Z

RP@

1

2

R549

200_0402_5%

1 2

C1101

10P_0402_50V8J

1

2

R983

200_0402_5%

12

C254

0.047U_0402_16V7K

RP@

R1049 47_0402_5%RP@

1 2

C780

4.7U_0805_10V4Z

@

1

2

JP25

ACES_88020-12101

CONN@

1

1

3

3

5

5

7

7

9

9

11

11

22

44

66

88

10 10

12 12

GND

13

GND

14

GND

15

GND

16

GND

17

GND

18

C255

0.047U_0402_16V7K

RP@

Q7B

2N7002DW-7-F_SOT363-6

3

5

4

R1007 0_0402_5%

1 2

C1102

33P_0402_50V8J

RP@

12

C257

0.1U_0402_16V4Z

1

2

R495

33_0402_5%

1 2

R1066 0_0402_5%RM@

1 2

D7

HT-F196BP5_WHITE

21

R235 0_0603_5%

1 2

R1035 0_0402_5%RM@

1 2

R42

0_0402_5%

RP@

1 2

C779

0.1U_0402_16V4Z

1

2

G

D

S

Q153

2N7002_SOT23-3

2

13

R1034 0_0402_5%RM@

1 2

R1075

47_0402_5%

@

12

C778

1000P_0402_50V7K

1

2C256

0.1U_0402_16V4Z

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

JACK_DET#

DOCK_SLP_BTN#

MUTELED

DOCK_PWR_ON

CIR_ IN

TV_LUMA_L

TV_CRMA_L

TV_COMPS_L

AUDIO_IGND

DOCK_PRESENT

DOCK_MIC_L_C

DOCK_MIC_R_C

DOCK_LOUT_C_L

DOCK_LOUT_C_R

AUDIO_OGND

R_VOL_DWN# DOCK_VOL_DWN#

R_VOL_UP# DOCK_VOL_UP#

+V_BATTERY

DOCK_PWR_ON

DOCK_PRESENT

SPDIFO_L

DOCK_MIC_L_C

DOCK_MIC_R_CDOCK_MIC_R_R

DOCK_MIC_L_C

DOCK_MIC_L_R

R_VOL_UP# R_VOL_DWN#

DOCK_LOUT_C_LDOCK_LOUT_C_R

SPDIFO_L

RJ45_MIDI1-

RJ45_MIDI0-

D_DDCDATA

D_HSYNC

USB20_N3

RJ45_MIDI1+

RJ45_MIDI0+

D_DDCCLK

D_VSYNC

USB20_P3

AUDIO_IGND

AUDIO_IGND

AUDIO_OGND

AUDIO_IGND

GNDA_DOCKA

GNDA_DOCK_1

GNDA_DOCKA

GNDA_DOCK_2

CONA# <33>

DOCK_VOL_DWN# <33>

JACK_DET# <28,29>

DOCK_SLP_BTN# <33>

DOCK_LOUT_C_R <29>

DOCK_LOUT_C_L <29>

DOCK_VOL_UP# <33>

CIR_IN <29,33>

MUTE_LED <33>

SYSON#<34,36,42>

DOCK_MIC_R<28>

DOCK_MIC_L<28>

SENSE_B# <28>

SPDIF_OUT <28>

USB20_P3<20>

RJ45_MIDI1-<25>

RJ45_MIDI0-<25>

GREEN_L<16>

D_DDCDATA<16>

D_HSYNC<16>

USB20_N3<20>

RJ45_MIDI1+<25>

RJ45_MIDI0+<25>

BLUE_L<16>

RED_L<16>

D_DDCCLK<16>

D_VSYNC<16>

GNDA_DOCK_1<29>

GNDA_DOCK_2<29>

+3VL_EC

B+

+3VALW

+5VS

+3VS

+DOCKVIN

+1.5VS

+DOCKVIN

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

DOCK CONN

Custom

35 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

DOCK_PWR_ON Spec

0V = Notebook S4/S5, Dock off

2.5V = Notebook S3, Dock on

4V = Notebook S0, Dock on

Atlas/ Saturn Dock

Need 600 Ohm 500 mA

MIC_Dock

SPDIF

Close to CODEC U27

L

R976/Q149/R646 be option with R992/C945

03/03 Change JDOCK Footprint

01/23 Change NMOS type to solve Saturn docking issue

H43

H_4P2@

1

R591 1K_0402_5%RP@

1 2

H51

H_6P0X5P0N@

1

H32

H_2P8@

1

R586 1K_0402_5%

RP@

1 2

D43

DAN202U_SC70

RP@

2

3

1

H42

H_2P8@

1

R647

220_0402_5%

RP@

1 2

H54

H_3P3X0P6N@

1

C943

220P_0402_50V7K

RP@ 1

2

G

D

S

Q18

2N7002_SOT23-3

RP@

2

13

R568 200_0402_5%RP@ 1 2

R914

10K_0402_5%

RP@

1 2

R912

10K_0402_5%

RP@

1 2

R943 10K_0402_5%RP@

12

C843

1000P_0402_50V7K

RP@

1

2

R915

10K_0402_5%

RP@

1 2

L93

FCM1608KF-601T02_2P

RP@

1 2

C942

220P_0402_50V7K

RP@ 1

2

C

B

E

Q16

PMBT3904_SOT23

RP@

1

2

3

JDOCK

FOX_QL1122L-H212AR-9F

CONN@

CRT_Green

40

TV composite 33

CRT_Blue

34

TV ground 31

Vsync

26 CIR input 29

USB-

28

USB+

22

PWR_ON 27

Digital gnd

24

MDI0-

6

MDI3-

18

Mute_LED 25

DDC_Clock

30 DDC_DATA

36

Digital gnd 39

TV chroma 35

TV Luma 37

CRT_Red

38

Hsync

32

MDI3+

20

MD2I-

14

MDI2+

16

MDI1-

10

MDI1+

12

Sleep Botton 23

Jack Detect 21

VOL_up 19

VOL_down 17

MDI0+

8

Battery out

2

Battery out

4

SPDIF 15

Audio Output gnd 13

Left headphone 9

Right headphone 11

Mic_Right 7

Dock_present 1

Mic gnd 3

Mic_Left 5

GND 41

GND 42

GND 43

GND 44

GND

45

GND

46

H36

H_2P8@

1

G

D

S

Q33

2N7002_SOT23-3

RP@

2

13

C844

1000P_0402_50V7K

RP@

1

2

H35

H_2P8@

1

H57

H_2P8@

1

C921

220P_0402_50V7K

RP@

1

2

R415

0_0402_5%

RP@

1 2

R588

10K_0402_5%

RP@

1 2

R573

110_0402_5%RP@

12

H41

H_2P8@

1

H48

H_3P3@

1

R127

0_0402_5%

12

H33

H_2P8@

1

R942 10K_0402_5%RP@

12

H53

H_3P3X0P6N@

1

R976

33_0402_5%@

1 2

H55

H_5P6N@

1

R585 1K_0402_5%

RP@

1 2

C831

1000P_0402_50V7K

RP@

1

2

L94

FCM1608KF-601T02_2P

RP@

1 2

R980

1.21K_0402_1%

RP@

12

E

B

C

Q149

MMBT3904_NL_SOT23-3

@

2

3 1

H46

H_4P2@

1

R646

0_0402_5%@

1 2

C922

220P_0402_50V7K

RP@

1

2

R944

1.21K_0402_1%

RP@

12

T51PAD

H56

H_2P5N@

1

R913

47K_0402_5%

RP@

1 2

T53PAD

PJP5

PAD-OPEN 2x2m

21

H39

H_2P8@

1

T52PAD

H34

H_2P8@

1

H37

H_2P8@

1

C978

1U_0603_10V6K

RP@

1

2

R572 22_0402_5%

RP@

1 2

C944

220P_0402_50V7K

RP@ 1

2

H40

H_2P8@

1

G

D

S

Q100

2N7002_SOT23-3

RP@

2

13

C945

0.1U_0402_16V7K

RP@

1 2

R565

10K_0402_5%

RP@

1 2

R566

2K_0402_5%

RP@

12

R417 0_0603_5%RP@

1 2

R128

0_0402_5%

@

12

R418 0_0603_5%RP@

1 2

R992

0_0603_5%RP@

1 2

H52

H_1P5N@

1

H47

H_3P3@

1

H44

H_4P2@

1

G

D

S

Q36

2N7002_SOT23-3

RP@

2

13

R567 200_0402_5%RP@ 1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

RUNON

VLDT_EN#

EC_ON#

SUSPSYSON#

VLDT_EN# S YSON#

VLDT_EN

VLDT_EN#

SUSP SUSP

SYSON

SYSON#

SUSP

SUSP

RUNON

SUSP

SUSP

EC_ON#

DIM_LED#

DIM_LED

DIM_LED#

SUSP

1.8VS_ENABLE

SYSON#<34,35,42> SUSP <42>

EC_ON<33,39>

SUSP# <26,28,33,38,41>SYSON<26,33,40> VLDT_EN<33>

DIM_LED<33>

VLDT_EN#<13>

+5VL

B+

+1.2VALW +1.2V_HT

+5VALW +5VS

+5VL+5VL

+5VS

+3VS

+1.8VS

+0.9V

+5VL

+1.8VS

+1.8V

+1.2V_HT +1.8V +1.2VALW

B+

+3VALW +3VS

+1.5VS +1.1VS

+5VALW

+5VALW_LED

+5VS

+5VS_LED

B+

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

0.3

DC/DC Circuits

Custom

36 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

+1.2VALW TO +1.2V_HT

+5VALW TO +5VS

+1.8V TO +1.8VS

Discharge circuit

Change to +3VL(same as EC)

to avoid leakage

+3VALW TO +3VS

DIM LED

G

D

S

Q40

2N7002_SOT23-3

2

13

CF1

1

C846

1U_0402_6.3V4Z

1

2

G

D

S

Q52

2N7002_SOT23-3

2

13

C1112

0.1U_0603_25V7K

1

2

FM1

1

R596

100K_0402_5%

12

C848

1U_0402_6.3V4Z

1

2

G

D

S

Q37

2N7002_SOT23-3

2

13

C839

1U_0402_6.3V4Z

1

2

R292

470_0805_5%

1 2

R420 0_0603_5%

1 2

Q4

IRF8113PBF_SO8

36

5

7

8

2

4

1

G

D

S

Q48

2N7002_SOT23-3

2

13

C840

4.7U_0805_10V4Z

1

2

R280

470_0805_5%

1 2

C1111

0.1U_0603_25V7K

1

2

R597

100K_0402_5%

12

G

D

S

Q46

2N7002_SOT23-3

2

13

FM3

1

C835

4.7U_0805_10V4Z

1

2

C1116

0.1U_0603_25V7K

1

2

G

D

S

Q41

2N7002_SOT23-3

2

13

C833

1U_0402_6.3V4Z

1

2

C837

0.01U_0402_25V7K

1

2

PJP8

PAD-OPEN 2x2m

21

G

D

S

Q12

2N7002_SOT23-3

2

13

R294

470_0805_5%

1 2

R137

750K_0402_5%

12

G

D

S

Q13

2N7002_SOT23-3

2

13

C1114

0.1U_0603_25V7K

1

2

R368

470_0805_5%@

1 2

G

D

S

Q166 SI2301BDS-T1-E3_SOT23-3@

2

13

C849

0.01U_0402_25V7K

1

2

R587

10K_0402_5%

@

12

C862

4.7U_0805_10V4Z

1

2

C836

0.1U_0402_16V4Z

@

1

2

C1113

0.1U_0603_25V7K

1

2

C1115

0.1U_0603_25V7K

1

2

Q14

SI4800BDY_SO8

S1

S2

S3

G4

D

8

D

7

D

6

D

5

C838

4.7U_0805_10V4Z

1

2

R284

470_0805_5%

1 2

Q11

IRF8113PBF_SO8

36

5

7

8

2

4

1

C847

4.7U_0805_10V4Z

1

2

R288

470_0805_5%

1 2

R293

470_0805_5%

1 2

G

D

S

Q44

2N7002_SOT23-3

2

13

G

D

S

Q17

2N7002_SOT23-3

2

13

G

D

S

Q42

2N7002_SOT23-3@

2

13

C1110

0.1U_0603_25V7K

1

2

G

D

S

Q32 SI2301BDS-T1-E3_SOT23-3@

2

13

Q35

SI4800BDY_SO8

S1

S2

S3

G4

D

8

D

7

D

6

D

5

G

D

S

Q39

2N7002_SOT23-3

2

13

C841

10U_0805_10V4Z

1

2

R138

330K_0402_5%

1 2

CF3

1

FM2

1

R598

100K_0402_5%

12

R233

330K_0402_5%

12

C834

0.01U_0402_25V7K

1

2

G

D

S

Q49

2N7002_SOT23-3

2

13

R152

330K_0402_5%

12

C864

4.7U_0805_10V4Z

1

2

G

D

S

Q38

2N7002_SOT23-3

2

13

R419 0_0603_5%

1 2

R234

750K_0402_5%

12

C1117

0.1U_0603_25V7K

1

2

CF2

1

R595

100K_0402_5%

12

C842

4.7U_0805_10V4Z

1

2

G

D

S

Q47

2N7002_SOT23-3

2

13

PJP7

PAD-OPEN 2x2m

21

R239

470_0805_5%

1 2

R279

470_0805_5%

1 2

G

D

S

Q51

2N7002_SOT23-3

@

2

13

G

D

S

Q50

2N7002_SOT23-3

2

13

C1069

0.1U_0402_16V4Z

@

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

EC_SMD

EC_SMC

SMB_EC_DA1

SMB_EC_CK1

ADP_SIGNAL

ADPINA DPIN

ENTRIP1 <39>

BATT_OVP <33>

EN0 <6,39>

SMB_EC_CK1 <6,32,33,34>

SMB_EC_DA1 <6,32,33,34>

BAT_ID <38>

BATT_TEMP <33>

ADP_ID <33>

AC_LED# <33>

NB_OTP <33>

+5VS

+5VALW

BATT

+5VALW

VMB

+3VL

BATT

VIN +DOCKVIN

+3VALW

+3VL

+5VALW

+5VS

+5VALW

+5VS

+3VL

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4111P

0.1

DC Connector/CPU_OTP

Custom

37 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

CPU

PH1 under CPU botten side :

CPU thermal protection at 95 +-3 degree C

PR14

100_0402_5%

12

PR24

@100K_0402_5%

1 2

PR9

100K_0402_5%

1 2

PU2

@LMV331IDCKRG4_SC70-5

P5

IN+

1

IN-

3

G

2

O4

PR23

@10K_0402_5%

12

PR7

604K_0402_1%

1 2

PC3

1000P_0402_50V7K

12

PC10

0.22U_0603_10V7K

12

PL1

SMB3025500YA_2P

1 2

PC4

100P_0402_50V8J

12

G

D

S

PQ2

SSM3K7002FU_SC70-3

2

13

PC9

0.01U_0402_50V4Z

12

PJP2

SUYIN_200275MR008GXOLZR

11

33

44

55

66

GND 9

GND 10

22

77

88

PR1

340K_0402_1%

12

PD3

@SM24.TC_SOT23-3

2

3

1

PR21

@2.21K_0402_1%

12

PD1

@PJSOT24C_SOT23-3

2

3

1

PR6

105K_0402_1%

12

PH1

10KB_0603_1%_TH11-3H103FT

12

PC15 0.1U_0402_16V7K

1 2

PC6

0.01U_0402_25V7K

12

PC14

820P_0402_50V7K

12

PL2

SMB3025500YA_2P

12

PR3

10K_0402_5%

1 2

PC5

1000P_0402_50V7K

12

PR5

10K_0402_5%

12

G

D

S

PQ1

@SSM3K7002FU_SC70-3

2

13

PR11

150K_0402_1%

1 2

PU1A

LM358ADT_SO8

+

3

-

201

P8

G

4

PR13

100_0402_5%

12

PR16

6.49K_0402_1%

1 2

PR2

10K_0402_5%

12

PC2

100P_0402_50V8J

12

PR22

@150K_0402_1%

12

PC8

1000P_0402_50V7K

12

PR10

200K_0402_1%

1 2

PR17

1K_0402_5%

12

PR15

150K_0402_1%

12

PD4

RLZ3.6B_LL34

12

PR4

499K_0402_1%

12

PD2

@SM05_SOT23

2

3

1

PC17

@1000P_0402_50V7K

12

PL3

HCB2012KF-121T50_0805

1 2

PR12

2.21K_0402_1%

12

PC7

2200P_0402_50V7K

12

PR20

@150K_0402_1%

1 2

PC12

@1000P_0402_50V7K

12

PL4

HCB2012KF-121T50_0805

1 2

PC18

@0.01U_0402_25V7K

12

G

D

S

PQ4

@SSM3K7002FU_SC70-3

2

13

PC13

390P_0402_50V7K

12

PR8

2K_0402_5%

1 2

PC16

@0.22U_0603_10V7K

12

PR19

@15K_0402_1%

1 2

PU1B

LM358ADT_SO8

+

5

-

607

P8

G

4

PJP1

ACES_88334-057N

11

33

44

55

22

BATT1

CR2032 RTC BATTERY

45@

PC1

0.01U_0402_25V7K

12

PH2

@10KB_0603_1%_TH11-3H103FT

12

PC11

1000P_0402_50V7K

12

PQ3

TP0610K-T1-E3_SOT23-3

2

1 3

PR18

@47K_0402_1%

1 2

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

D L _ C HG

D H _ C H G

LX _ CHG

C H G EN #

BS T _ CHG

R E GNVA D J

BATT

AC D ET

AC S ET

I AD AP T

C H G EN #

F ST C H G#

AC D ET

VI N_ 1

PA C IN

AC OFF#

AC OFF#

AC S ET

VI N_ 1

PACIN

I R E F < 33>

VC T RL<33>

ADP_I<33>

BA T_ID <37>

AC _SET<33>

SU S P #< 2 6,28,33,36,41>

AC_IN <21,33>

STD_ADP <33>

FST CH G<33>

A C OF F <33>

PACIN_1 <39>

V I N

P4

BATT

V I N

V I N

BATT

B+

V I N

CHG_B +

CHG_B +

P2

V I N

+3VL

BQ 2 4740VREF

1. 24 VREF

BQ 2 4740VREF

+3VL

+3VL

+3VL

1. 24 VREF

V I N

Title

Size Documen t N u mber R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA- 3941P

0. 1

Charger

38 56Mon d ay, M arch 16, 2009

2007/05/29 2008/05/29

Compal Electronics, Inc.

Charge Detector

PC 1 24

0. 1U _ 0603_25V7K

12

PD 1 0 4

1S S 355_SOD323-2

1 2

PR 1 1 1

3K _ 0402_1%

1 2

PR 1 4 0

10 0 K_0402_5%

12

PR 1 1 3

143K_0402_1%

12

PC 1 1 7

1U _ 0 603_10V6K

12

PC 1 2 1

100P_0402_50V8J

12

PR 1 3 9

4.7_1206_5%

1 2

PR 1 1 9

47K_0402_5%

12

PC 1 0 7

@0.01 U _0402_16V7K

12

PR 1 0 5

10 K _0402_5%

12

PR 1 3 4

10 K _0402_5%

12

PR 1 0 3

47K_0402_5%

1 2

PC 1 0 6

0. 47 U _0603_16V7K

12

PC 1 02

1U _ 0 603_6.3V6M

1 2

PC 1 1 9

1U _ 0 603_10V6K

12

PR 1 2 6

100K_0402_1%

12

PC 1 1 1

0. 1U _ 0402_10V7K

1 2

PR 1 17

10 0 K_0402_5%

1 2

PC 1 1 2

1U _ 0 603_6.3V6M

1 2

PR 1 04

0_0402_5%

1 2

PR 1 0 1

47K_0402_5%

1 2

PQ 1 08

AO 4 466_SO8

3 6

5

7

8

2

4

1

PR 1 3 2

100K_0402_5%

12

PC 1 16

4. 7U _ 0805_25V6-K

12

PR 1 2 8

10K_0402_5%

12

PC 1 2 7

22 P _0402_50V8J

12

PC 1 0 8

0. 1U _ 0603_25V7K

12

PR 1 12

0.015_1206_1%

1 2

G

D

S

PQ 1 09

SS M 3 K7002FU_SC70-3

2

13

PD 1 0 3

RLZ 4. 3 B_LL34

12

PC 1 0 9

@0.1U _ 0603_25V7K

12

PQ 1 10

FDS66 90AS_SO8

3 6

5

7

8

2

4

1

PR 1 2 7

10K_0402_1%

12

PQ 1 06

DTC115 EUA_SC70-3

2

13

PC 1 18

0. 1U _ 0402_10V7K

1 2

PQ 1 05

DTC115 EUA_SC70-3

2

13

PC 1 2 9

1200P_0402_50V7K

12

G

D

S

PQ 1 11

SS M 3 K7002FU_SC70-3

2

13

PC 1 0 1

47 P _0402_50V8J

12

PC 1 0 5

4. 7U _ 0805_25V6-K

12

PC 1 2 2

@0.1U _ 0603_25V7K

12

PR 1 2 2

681K_0402_1%

1 2

PC 1 13

4. 7U _ 0805_25V6-K

12

PR 1 08

10_1206_5%

1 2

PD 1 0 2

1S S 355_SOD323-2

12

PR 1 18

10K_0402_5%

1 2

PR 1 3 7

20K_0402_1%

1 2

PR 1 0 7

47K_0402_1%

1 2

PU 1 0 2B

LM 3 9 3DG_SO8

+

5

-

6O7

P8

G

4

PR 1 2 0

133K_0402_1%

12

PQ 1 03

SI 48 35BDY-T1-E3_SO8

3 6

5

7

8

2

4

1

PR 1 25

47 _ 1206_5%

12

PL 1 02

10 U _ LF919AS-100M-P3_4.5A_20%

1 2

BQ 2 4740R H D R _ QFN28_5X5

PU 1 0 1

ACP 3

LPMD 4

CHGEN 1

ACN 2

ACDET 5

ACSET 6

IADSLP

8

SRP

19

BAT

17

IADAPT

15

PGND 22

SRSET

16

ISYNSET

14

VADJ

12

VDAC

11

LPREF 7

VREF

10

DPMDET

21

LODRV 23

CELLS

20

SRN

18

AGND

9

REGN 24

EXTPWR

13

PH 25

HIDRV 26

BTST 27

PVCC 28

TP 29

PR 1 3 1

13 3 K_0402_1%

12

PC 1 3 1

680P_0603_50V7K

12

PR 1 2 9

10 K _0402_1%

12

PC 1 2 3

0. 1U _ 0402_10V7K

12

PR 1 2 3

1M_0402_5%

1 2

PC 1 2 0

0. 22 U _0603_10V7K

12

PC 1 0 4

4. 7U _ 0805_25V6-K

12

PR 1 3 6

60.4K_0402_1%

1 2

G

D

S

PQ 1 12

SS M 3 K7002FU_SC70-3

2

13

PQ 101

SI 48 35BDY-T1-E3_SO8

36

5

7

8

2

4

1

PQ 1 02

FDS66 75BZ_SO8

3 6

5

7

8

2

4

1

PC 1 2 8

220P_0402_50V7K

12

PR 1 10

0_0402_5%

1 2

PR 1 1 5

10 0 K_0402_1%

12

G

D

S

PQ 1 13

SS M 3 K7002FU_SC70-3

2

13

PL 101

HCB20 12KF-121T50_0805

1 2

PR 1 09

150K_0402_5%

12

PQ 1 04

DTA14 4EUA_SC70-3

2

1 3

PC 1 1 0

1U _ 0 805_25V6K

1 2

PD 1 0 1

1S S 355_SOD323-2

1 2

PR 1 2 1

20 0 K_0402_1%

12

PC 1 0 3

4. 7U _ 0805_25V6-K

12

PU 1 0 3

AP L 1431LBBC-TR_SOT23-5

NC 2

REF

4

NC 1

CATHODE 3

ANODE

5

PC 1 2 5

0. 1U _ 0603_25V7K

12

PR 1 1 4

@0_0 402_5%

1 2

PR 1 0 2

0.012_2512_1%

1 2

PC 1 15

4. 7U _ 0805_25V6-K

12

PR 1 38

100K_0402_1%

12

PU 1 0 2A

LM 3 9 3DG_SO8

+

3

-

2O1

P8

G

4

PR 1 0 6

20 0 K_0402_5%

12

PR 1 2 4

1K _ 0402_5%

1 2

PC 1 14

4. 7U _ 0805_25V6-K

12

G

D

S

PQ 1 07

SS M 3 K7002FU_SC70-3

2

13

PC 1 2 6

0. 04 7U_0402_16V7K

12

PC 1 32

4. 7U _ 0805_25V6-K

12

PR 1 3 0

2.15K_0402_1%

1 2

PR 1 3 3

10 K _0603_0.1%

12

PC 1 3 0

680P_0402_50V7K

12

PR 1 3 5

10 K _0603_0.1%

12

PR 1 1 6

15K_0402_1%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

BST_5V

LX_5V

LG_3V

LX_3V

UG_3V

ENTRIP2

UG1_3V

UG_5V

BST_3V

ENTRIP2

ENTRIP1

LG_5V

EC_ON <33,36>

ENTRIP1<37>

3/5V_OK <20,41>

PACIN_1<38>

EN0<6,37>

B++

+5VALWP

VL

+3VALWP

B++

B++

2VREF_51125

B+

+3VL

+3VLP

+3VLP

2VREF_51125

VL

+5VALWP

+3VALW

+5VALW

+3VALWP

+5VL

VL

+3VL

B++

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4111P

0.1

3.3VALWP/5VALWP

Custom

39 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

(4.5A,180mils ,Via NO.= 9)

(3A,120mils ,Via NO.= 6)

G

D

S

PQ307

SSM3K7002FU_SC70-3

2

13

PR315

@4.7_1206_5%

12

PR317

100K_0402_5%

12

PC303

4.7U_0805_25V6-K

12

PR308

2.2_0402_5%

1 2

PR304

20K_0402_1%

1 2

PC313

4.7U_0805_25V6-K

12

PR314

100K_0402_5%

12

G

D

S

PQ306

SSM3K7002FU_SC70-3

2

13

PR318

@604K_0402_1%

1 2

PC316

@0.1U_0402_25V4K

12

PJP303

PAD-OPEN 4x4m

1 2

PR305

140K_0402_1%

1 2

PJP304

PAD-OPEN 2x2m

2 1

+

PC309

150U_D_6.3VM

1

2

PL301

HCB2012KF-121T50_0805

<BOM Structure>

1 2

PR307

0_0402_5%

1 2

PC315

680P_0603_50V8J

12

PC319

@22U_0805_6.3V6M

12

PC317

@0.1U_0402_25V4K

12

PR303

20K_0402_1%

1 2

PC322

390P_0402_50V7K

12

PC305

4.7U_0805_25V6-K

12

PQ302

AO4466_SO8

3 6

5

7

8

2

4

1

PR306

113K_0402_1%

1 2

PL303

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

PC311

10U_0805_10V6K

12

+

PC310

150U_D_6.3VM

1

2

PC302

0.22U_0603_10V7K

12

PJP302

PAD-OPEN 4x4m

1 2

PR312

1M_0402_1%

1 2

PC306

10U_0805_6.3V6M

12

PC304

2200P_0402_50V7K

12

PR309

0_0402_5%

1 2

PR313

100K_0402_5%

1 2

PC320

@22U_0805_6.3V6M

12

PR301

13.7K_0402_1%

1 2

PC314

@680P_0603_50V8J

12

PR311

191K_0402_1%

12

PQ304

SI4894BDY-T1-E3_SO8

3 6

5

7

8

2

4

1

PJP301

PAD-OPEN 2x2m

2 1

PC307

0.1U_0402_10V7K

1 2

G

D

S

PQ305

SSM3K7002FU_SC70-3

2

13

PC321

2200P_0402_50V7K

12

PC301

2200P_0402_50V7K

12

PC318

@0.047U_0603_16V7K

12

PR316

4.7_1206_5%

12

PL302

4.7UH_SIQB74B-4R7PF_4A_20%

12

PC308

0.1U_0402_10V7K

1 2

PU301

TPS51125RGER_QFN24_4X4

VREF 3

TONSEL 4

ENTRIP1 1

VFB1 2

VFB2 5

ENTRIP2 6

VREG3

8

DRVL1 19

VREG5

17

GND

15

VBST1 22

VIN

16

SKIPSEL

14

DRVL2

12

LL2

11

VO2

7

DRVH2

10 DRVH1 21

PGOOD 23

LL1 20

VCLK

18

VBST2

9

VO1 24

EN0

13

P PAD

25

G

D

S

PQ308

@SSM3K7002FU_SC70-3

2

13

AO4932_SO8

PQ301

D1

21G 8

G2

3

1S/2D 5

D1

1

1S/2D 7

S2

41S/2D 6

PR302

30.9K_0402_1%

1 2

PC312

0.1U_0603_25V7K

12

PR310

0_0402_5%

1 2

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

+5VALW

DH_1.8V

1.8V_B+

DL_1.8V

LX_1.8V

BST1_1.8VBST_1.8V

DH_1.8V_1

+5VALW+5VALW

SYSON<26,33,36>

+1.8VP

+1.8VP

+5VALW

+1.8VP

B+

+1.8V

+1.8VP

Title

Size Docum ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-3941P

0.1

1.8VP

40 56Monday, March 16, 2009

2007/05/29 2008/05/29

Compal Electronics, Inc.

(7A,280mils ,Via NO.= 14)

PQ402

SI4894BDY-T1-E3_SO8

3 6

5

7

8

2

4

1

PR406

10.7K_0402_1%

1 2

PR405

0_0402_5%

12

PR402

0_0402_5%

1 2

PC406

470P_0402_50V7K

12

PC409

1U_0603_10V6K

12

PL401

HCB1608KF-121T30_0603

1 2

PC413

@10P_0402_50V8J

1 2

+

PC408

220U_D2_4VY_R25M

1

2

PL402

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

PR401

0_0402_5%

1 2

PU401

TPS51117RGYR_QFN14_3.5x3.5

VOUT

3

V5FILT

4

EN_PSV 1

TON

2

VFB

5

PGOOD

6DRVL 9

DRVH 13

LL 12

GND

7

PGND

8

TRIP 11

V5DRV 10

VBST 14

TP 15

PC414

@0.1U_0402_25V4K

12

PR407

@4.7_1206_5%

12

PR404

255K_0402_1%

1 2

PQ401

AO4466_SO8

3 6

5

7

8

2

4

1

PC402

0.1U_0402_10V7K

1 2

PC412

@680P_0603_50V7K

1 2

PJP401

PAD-OPEN 4x4m

1 2

PC405

2200P_0402_50V7K

12

PC401

@1000P_0402_50V7K

12

PR403

316_0402_1%

12

PC404

4.7U_0805_25V6-K

12

PR409

10K_0603_0.1%

12

PC415

4.7U_0805_10V6K

12

PC403

4.7U_0805_25V6-K

12

PR410

0_0402_5%

1 2

PR408

14.3K_0603_0.1%

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

LX_1.2V

UG1_1.1V

BST_1.2V

+1.2VALWP

LG_1.2V

UG1_1.2V

LG_1.1V

+1.1VSP

UG_1.2V

+1.1VSP

BST_1.1V

LX_1.1V

UG_1.1V

+1.2VALWP

+1.1VS

+1.1VSP

B+++

VCCP_POK

SUSP#<26,28,33,36,38>

3/5V_OK <20,39>

B+++

+1.2VALWP

B+

+1.1VSP

+5VALW

B+++

+1.1VS

+1.1VSP +1.2VALW

+1.2VALWP

+1.1VSP +1.1VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4111P

0.1

1.1VSP/1.2VALWP

Custom

41 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

(4A,160mils ,Via NO.=8)

(6A,240mils ,Via NO.=12)

PQ503

FDS6690AS_NL_SO8

3 6

5

7

8

2

4

1

PC520

470P_0603_50V8J

12

PL501

2.2UH_PCMC063T-2R2MN_8A_20%

12

PJP501

PAD-OPEN 4x4m

1 2

PR515

4.7_1206_5%

12

PJP503

PAD-OPEN 4x4m

1 2

PC516

470P_0402_50V7K

12

PC518

@0.1U_0402_25V4K

12

PC504

4.7U_0805_25V6-K

12

PC506

0.1U_0402_10V7K

12

PC501

4.7U_0805_25V6-K

12

PR502

24.9K_0402_1%

1 2

PC507

0.1U_0402_10V7K

1 2

PC509

4.7U_0805_6.3V6K

12

+

PC511

220U_B2_2.5VM

1

2

PC512

0.1U_0402_16V7K

12

PJP502

PAD-OPEN 4x4m

1 2

PC502

2200P_0402_50V7K

12

PC505

2200P_0402_50V7K

12

PR518

0_0402_5%

1 2

PC517

4.7U_0805_25V6-K

12

PR511

15.4K_0402_1%

1 2

PC503

@0.022U_0603_25V7K

12

PR5080_0402_5%

12

+

PC508

220U_D2_4VY_R25M

1

2

PR517

10_0402_5%

1 2

PR514

3.3_0402_5%

1 2

PC513

0.1U_0402_10V7K

12

PR504

11.5K_0402_1%

12

PC521

@0.1U_0402_25V4K

12

PC510

4.7U_0805_6.3V6K

1 2

PR503

18.7K_0402_1%

12

PR513

0_0402_5%

12

PR516

4.7_1206_5%

12

PR509

0_0402_5%

12

PC515

4.7U_0805_10V6K

12

PR510

10.5K_0402_1%

12

PQ504

AO4468_SO8

3 6

5

7

8

2

4

1

PC514

1U_0603_10V6K

12

PU501

TPS51124RGER_QFN24_4x4

GND 3

TONSEL 4

VO1 1

VFB1 2

VFB2 5

VO2 6

EN2

8

DR VL1 19

TRIP1

17

V5FILT

15

VBST1 22

V5IN

16

TRIP2

14

DR VL2

12

LL2

11

PGOOD2

7

DR VH2

10 DR VH1 21

EN1 23

LL1 20

PGND1

18

VBST2

9

PGOOD1 24

PGND2

13

P PAD

25

PQ501

AO4466_SO8

3 6

5

7

8

2

4

1

PC519

470P_0603_50V8J

12

PR505

0_0402_5%

1 2

PR519

1K_0402_5%

12

PR506

2.2_0402_5%

12

PR512

33K_0402_5%

1 2

PL502

HCB2012KF-121T50_0805

12

PL503

3.3UH 30% MSCDRI-7030AB-3R3N 4.1A

1 2

PR501

11.5K_0402_1%

1 2

PR507

2.2_0402_5%

12

PQ502

AO4466_SO8

3 6

5

7

8

2

4

1

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

VREF1.5V

SUSP<36>

SYSON#<34,35,36>

SUSP<36>

+5VALW

+0.9VP

+1.8V

+5VALW

+1.5VSP

+1.8V

+0.9VP +0.9V

+1.5VSP +1.5VS

+2.5VSP

+3VS

+2.5VSP +2.5VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4111P

0.1

0.9VSP/2.5VSP/1.5VSP

Custom

42 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

(2A,80mils ,Via NO.= 4)

(1A,40mils ,Via NO.= 2)

(500mA,40mils ,Via NO.= 1)

(500mA,40mils ,Via NO.= 1)

G

D

S

PQ601

SSM3K7002FU_SC70-3

2

13

PC613

10U_0805_10V4Z

12

PJP602

PAD-OPEN 3x3m

1 2

PJP603

PAD-OPEN 3x3m

1 2

PC601

10U_0805_10V4Z

12

PU602

APL5508-25DC-TRL_SOT89-3

IN

2

GND

1

OUT 3

PJP601

PAD-OPEN 3x3m

1 2

PC607

1U_0603_6.3V6M

12

PC614

10U_0805_6.3V6M

12

PR602

0_0402_5%

1 2

PC605

10U_0805_6.3V6M

12

PU603

G2992F1U_SO8

VOUT

4

NC 5

GND

2

VREF

3

VIN

1VCNTL 6

NC 7

NC 8

TP 9

PR608

0_0402_5%

1 2

PU601

G2992F1U_SO8

VOUT

4

NC 5

GND

2

VREF

3

VIN

1VCNTL 6

NC 7

NC 8

TP 9

PC608

4.7U_0805_6.3V6K

12

PC604

0.1U_0402_16V7K

12

PC602

@10U_0805_10V4Z

12

PC606

@0.1U_0402_16V7K

12

PC603

1U_0603_16V6K

12

PR601

1K_0402_1%

12

PR605

@150_1206_5%

12

PC611

0.1U_0402_16V7K

12

PC612

1U_0603_16V6K

12

PR604

@0_0402_5%

1 2

PC610

@0.1U_0402_16V7K

12

G

D

S

PQ602

SSM3K7002FU_SC70-3

2

13

PR607

5.1K_0402_1%

12

PC609

@10U_0805_10V4Z

12

PR603

1K_0402_1%

12

PR606

1K_0402_1%

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

BOOT_NB1

ISP 0

+CPU_CORE_0

BOOT0

UGATE0

LGATE0

BOOT1

LGATE1

UGATE1

PHASE1

ISP 0

PHASE0

ISP 1

+CPU_CORE_0

ISP 1

BOOT_NB

RTN_NB

SVD

SVC

UGATE NB

PHASE NB

PHASE NB

UGATE NB

LGATE NB

LGATE NB

VSEN_NB

RTN1

RTN0

ISL6265_PWROK

ISL6265_PWROK

UGATE0_1

UGATE1_1

ISL6265_PWROK

VSEN0

VSEN1

VDD_NB_FB_H<6>

VGATE<33>

SB_PWRGD<6,20,33>

CPU_SVD<6>

CPU_SVC<6>

VR_ON<33>

CPU_VDD0_FB_H<6>

CPU_VDD0_FB_L<6>

VDD_NB_FB_L<6>

VFIX_EN<33>

H_PW RGD<19>

+CPU_CORE_0

+5VS

B+

CPU_B+

CPU_B+

+CPU_CORE_NB

CPU_B+

+5VS

CPU_B+

+3VS

+5VS

+CPU_CORE_0

+1.8V

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4111P

0.1

CPU_CORE

Custom

43 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

Connect to EC pin 110.

PC214

2200P_0402_50V7K

12

PR219

0_0603_5%

1 2

PR212

0_0402_5%

1 2

PR211

1_0603_5%

12

PC257

390P_0402_50V7K

12

PC254

1800P_0402_50V7K

12

PC256

1800P_0402_50V7K

12

PR225

255_0402_1%

1 2

PC241

1000P_0402_50V7K

12

PR222

0_0402_5%

1 2

PC239

330P_0402_50V7K

12

PQ208

IRFH7932TRPBF_PQFN

3 5

2

4

1

PR206

0_0402_5%

12

PC209

33P_0402_50V8K

12

PR246 100K_0402_5%

1 2

PR232

6.81K_0402_1%

1 2

PC222

2200P_0402_50V7K

12

PC227

180P_0402_50V8J

1 2

PC251

680P_0603_50V7K

12

PR226

0_0603_5%

1 2

PC237

4.7U_0805_25V6-K

12

PR217

@4.02k_0603_1%

1 2

PC213

4.7U_0805_25V6-K

12

PC236

4.7U_0805_25V6-K

12

PR210

44.2K_0402_1%

12

PL202

SMB3025500YA_2P

12

G

D

S

PQ209

@SSM3K7002FU_SC70-3

2

13

PC253

47P_0402_50V8J

12

PC220

4.7U_0805_25V6-K

12

PR209

0_0402_5%

12

PC243

1000P_0402_50V7K

1 2

PR236

@6.81K_0402_1%

12

PR221

3.65K_0402_1%

12

PC249

3300P_0402_50V7K

12

PR244

4.7_1206_5%

12

PQ206

IRF8714TRPBF_SO8

4

7

8

6

5

1

2

3

PC250

1800P_0402_50V7K

12

PL203

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

PR230

54.9K_0402_1%

1 2

PR218

0_0402_5%

1 2

PC218

2200P_0603_50V7K

12

PC226

2200P_0603_50V7K

12

PR241

@0_0402_5%

1 2

PC246

@1000P_0402_50V7K

12

PC203

2200P_0402_50V7K

12

PR220

4.7_1206_5%

12

PC215

1000P_0402_50V7K

12

PC219

0.1U_0603_25V7K

1 2

PR245

4.7_1206_5%

12

PR237

0_0402_5%

1 2

PU201

ISL6265IRZ-T_QFN48_6X6

PWROK

3

SVD

4

OFS/VFIXEN

1

PGOOD

2

SVC

5

ENABLE

6

OCSET

8

VDIFF1

19

RTN1

17

VSEN0

15

VW1

22

RTN0

16

ISN0

14

VW0

12

COMP0

11

RBIAS

7

FB0

10

COMP1

21

ISP1

23

FB1

20

VSEN1

18

VDIFF0

9

ISN1

24

ISP0

13

BOOT1 25

UGATE1 26

PHASE1 27

PGND1 28

LGATE1 29

PVCC 30

LGATE0 31

PGND0 32

PHASE0 33

UGATE0 34

BOOT0 35

BOOT_NB 36

UGATE_NB 37

PHASE_NB 38

LGATE_NB 39

PGND_NB 40

OCSET_NB 41

RTN_NB 42

VSEN_NB 43

FSET_NB 44

COMP_NB 45

FB_NB 46

VCC 47

VIN 48

TP

49

PC247

@1000P_0402_50V7K

12

PL201

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PR227

1K_0402_1%

1 2

PR208

2_0402_5%

1 2

PR224

10K_0402_1%

1 2

PR205

2_0402_5%

1 2

PC224

0.22U_0603_10V7K

1 2

PR234 @100K_0402_5%

1 2

PC221

4.7U_0805_25V6-K

12

PC261

47P_0402_50V8J

12

PR242

4.7_1206_5%

12

PR235

0_0402_5%

1 2

PC232

@1200P_0402_50V7K

12

PC248

3300P_0402_50V7K

12

PC244

@1000P_0402_50V7K

12

PC208

1200P_0402_50V7K

12

PC223

4700P_0402_25V7K

1 2

PR233

@4.02k_0603_1%

1 2

PC242

@1000P_0402_50V7K

12

PQ203

IRF8714TRPBF_SO8

<BOM Structure>

4

7

8

6

5

1

2

3

PC229

0.1U_0603_25V7K 1 2

PC235

4.7U_0805_25V6-K

12

PC230

@1000P_0402_50V7K

12

PC231

@180P_0402_50V8J

12

PR239

0_0402_5%

1 2

PC238

470P_0402_50V7K

12

PC252

47P_0402_50V8J

12

PR240

@1K_0402_1%

12

PC216

0.1U_0603_25V7K

12

PC201

10U_0805_6.3V6M

12

PC206

0.1U_0402_16V7K

12

PR215

@10K_0402_5%

1 2

PC260

47P_0402_50V8J

12

PR203

0_0402_5%

1 2

PR238

@54.9K_0402_1%

12

PC207

0.1U_0402_16V7K

12

PR229

4.7_1206_5%

12

PR228

2.2_0603_5%

1 2

PL204

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

PC217

0.22U_0603_10V7K

1 2

PR223

107K_0402_1%

1 2

PQ205

IRFH7932TRPBF_PQFN

3 5

2

4

1

PC240

2200P_0402_50V7K

12

PR204

22K_0402_1%

1 2

+

PC202

220U_B2_2.5VM

1

2

PC233

@4700P_0402_25V7K

12

PC258

2200P_0402_50V7K

12

PC234

4.7U_0805_25V6-K

12

PC205

1000P_0402_50V7K

1 2

PC259

47P_0402_50V8J

12

PR214

2.2_0603_5%

1 2

PR243

@255_0402_1%

12

PC245

@1000P_0402_50V7K

12

PQ202

AO4466_SO8

3 6

5

7

8

2

4

1

PR216

10K_0402_1%

12

PQ201

AO4468_SO8

3 6

5

7

8

2

4

1

PR213

@0_0402_5%

1 2

PC225

1200P_0402_50V7K

1 2

PC255

390P_0402_50V7K

12

PR231

3.65K_0402_1%

12

PC204

4.7U_0805_25V6-K

12

PC228

1000P_0402_50V7K

1 2

PR207

17.4K_0402_1%

12

+

PC262 68U_25V_M

1

2

PC210

2.2U_0603_6.3V6K

12

+

PC211

68U_25V_M

1

2

PC212

4.7U_0805_25V6-K

12

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

Power Changed-List History-1

Custom

44 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C ha n ge L ist (

V ersion C h ange L ist ( V ersion C h ange L ist (

V ersion C h ange L ist ( P . I. R . L ist ) for P ow er C ircu it

P . I. R . L ist ) for P ow er C ircu itP . I. R . L ist ) for P ow er C ircu it

P . I. R . L ist ) for P ow er C ircu it

P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

R e v .

R e v .R e v .

R e v .I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nI t e m

I t e mI t e m

I t e m R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

D a t e

D a t eD a t e

D a t e

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

1

37 PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805

and add PL4 the same of the value.

2

41 PC508 and PC511 change the value from 220U_6.3VM_R15 to

220U_D24VY_R25M

3

4

43

Add PJP503

5

41

PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M

7

43

Add PC241 PC242 PC243, and the value are 1000P_0402_50V7K.

Reserve PC244 PC245 PC246 PC247, and the value are

1000P_0402_50V7K.

43 Add PJP201 PJP202

9/29

9/29

9/29

9/29

9/29

9/29

DC Connector

/CPU_OTP for Layout

HW request

Compal

Compal1.1VSP/1.2VALWP

1.1VSP/1.2VALWP Compal HW request

CPU_CORE Compal HW request

CPU_CORE Compal TI FAE suggested that after he review

the layout.

CPU_CORE TI FAE suggested that after he review

the layout.

Compal

6

38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102

8

37 DC Connector

/CPU_OTP 10/08 Compal for Layout These two choke are parallel ,it's not series.

9

38 Charger 10/08 Compal the footprint is wrong Change the footprint of PR102

10

40 1.8VP 10/08 Compal Delete PC410 and PC411

11

41 1.1VSP/1.2VALWP 10/08 Compal Add PR517 PR518PWR request

PWR request

12

37

3.3VALWP/5VALWP

11/01 Compal PWR request Add PD4 PC12

13

37 11/01 Compal for Layout change PQ301, Cencel PQ303

DC Connector

/CPU_OTP

14

43 CPU_CORE EMI requestCompal11/02 Add PC248, PC249, PC250

15

37 3.3VALWP/5VALWP 11/12 Compal for Layout Change PC310, add PC319

16

17

Add PU302, control signal changed to ACOFF

12/31 PWR requestCompal3.3VALWP/5VALWP37

Change PR221 and PR231 to 16.6K_ohm

Change PR217 and PR233 to 4.02K_ohm

Change PR223 to 17.8K_ohm

Change PR224 to 100K_ohm

12/31CPU_CORE Compal Vendor request43

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

Power Changed-List History-1

Custom

45 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist (

V ersion C h ange L ist ( V ersion C h ange L ist (

V ersion C h ange L ist ( P . I. R . L ist ) for P ow er C ircu it

P . I. R . L ist ) for P ow er C ircu itP . I. R . L ist ) for P ow er C ircu it

P . I. R . L ist ) for P ow er C ircu it

P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

R e v .

R e v .R e v .

R e v .I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nI t e m

I t e mI t e m

I t e m R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

D a t e

D a t eD a t e

D a t e

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

18

19

20

21

22

24

23

25

26

38 Charger 01/08 Compal EMI request Add PC128 220pF

DC Connector

/CPU_OTP

37 01/09 Compal AC LED change to KBC control AC_LED# connect to KBC pin 97

Change PC309 to D size and add PC32001/14 Compal for layout3.3VALWP/5VALWP37

Charger 02/2738 Compal EMI request CHG_B+ Add 1200pF and 330pF

02/27 Compal EMI request CPU_B+ Add 1800pF*2 2200pF*1 and 390pF*243 CPU_CORE

02/27 Compal3.3VALWP/5VALWP37 EMI request B+ Add 2200pF and 390pF

DC Connector

/CPU_OTP

02/2737 Compal EMI request VIN Add 2200pF and 390pF, ADPIN add 820pF

37 3.3VALWP/5VALWP 02/27 Change OTC shun down pin.Compal Change OTC shun down pin to PU301 pin13.

CPU_CORE Compal03/04 Change high-side MOS for WWAN issue Change PQ203 and PQ206 to powerpak43

27

CPU_CORE Compal03/04 HW request add H_PWRGD control net43

28

Compal04/02 AC LED issue37 Chaange AC_LED# pull high to +3VLDC Connector

/CPU_OTP

29

04/24 Compal acoustic noise43 Add PC262CPU_CORE

04/24 Compal HW CPU thermal protection

change to 95 +-3 degree C

Chaange PR12 to 2.21K_ohm

30

37

37

31

1.1VSP/1.2VALWP

DC Connector

/CPU_OTP

05/23 Compal +1.2VALW leakage Add PR519

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-1

Custom

46 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

1

11

1 2 5

2 52 5

2 5

L

LL

L A N

A NA N

A N 1 0

1 01 0

1 0 / 2 9

/ 2 9/ 2 9

/ 2 9

H W

H WH W

H W C h a n g e L A N C h

C h a n g e L A N C hC h a n g e L A N C h

C h a n g e L A N C h ip U 2 0 f ro m M a r v e ll 8 8 E 8 0 4 2 t o

ip U 2 0 fr o m M a r v e l l 8 8 E 8 0 4 2 toip U 2 0 fr o m M a r v e l l 8 8 E 8 0 4 2 to

ip U 2 0 fr o m M a r v e l l 8 8 E 8 0 4 2 to

R e a l t e k

R e a l t e kR e a l t e k

R e a l t e k R T L 8 1 0 2 E L

R T L 8 1 0 2 E L R T L 8 1 0 2 E L

R T L 8 1 0 2 E L

U p

U pU p

U p d a t e t h e L A N D es ig n p a g e a n d s u p p o r t c ir c u it

d a t e th e L A N D es ig n p a g e a n d s u p p o r t c ir cu itd a t e th e L A N D es ig n p a g e a n d s u p p o r t c ir cu it

d a t e th e L A N D es ig n p a g e a n d s u p p o r t c ir cu it

0 . 2

0 . 20 . 2

0 . 2

2

22

2 2 5

2 52 5

2 5

L

LL

L A N

A NA N

A N 1 0

1 01 0

1 0 / 2 9

/ 2 9/ 2 9

/ 2 9

H P Q

H P QH P Q

H P Q A d d

A d d A d d

A d d P O E (P o w e r O v e r E t h e r n e t ) d e sig n

P O E ( P o w e r O v e r E t h e r n e t ) d e sig nP O E ( P o w e r O v e r E t h e r n e t ) d e sig n

P O E ( P o w e r O v e r E t h e r n e t ) d e sig n

U p

U pU p

U p d a t e t h e L A N D es ig n p a g e a n d s u p p o r t c ir c u it

d a t e th e L A N D es ig n p a g e a n d s u p p o r t c ir cu itd a t e th e L A N D es ig n p a g e a n d s u p p o r t c ir cu it

d a t e th e L A N D es ig n p a g e a n d s u p p o r t c ir cu it

0 . 2

0 . 20 . 2

0 . 2

0 . 2

0 . 20 . 2

0 . 23

33

3 1 6

1 61 6

1 6

C

CC

C R T

R TR T

R T 1 0

1 01 0

1 0 / 2 9

/ 2 9/ 2 9

/ 2 9

H W

H WH W

H W C R T

C R TC R T

C R T c a n n o t d i s p la y

c a n n o t d i s p la y c a n n o t d i s p la y

c a n n o t d i s p la y

C h a n g e t h e C R T C o n n .

C h a n g e t h e C R T C o n n .C h a n ge t h e C R T C o n n .

C h a n g e t h e C R T C o n n . s ig n a ls co n n e c ti o n f irs t .

si g n a ls co n n e ct io n f irs t . si g n a ls co n n e ct io n f irs t .

si g n a ls co n n e ct io n f irs t .

W a i t c o r r e c t s y m b o l f

W a i t c o r r e c t s y m b o l fW a i t c o r r e c t s y m b o l f

W a i t c o r r e c t s y m b o l f or fi x

o r f ixo r f ix

o r f ix

4

44

4 2 9

2 92 9

2 9

A u d io

A u d ioA u d io

A u d io

0 . 2

0 . 20 . 2

0 . 2

1 0

1 01 0

1 0 / 3 0

/ 3 0/ 3 0

/ 3 0

H W

H WH W

H W S p e a k e

S p e a k eS p e a k e

S p e a k e r n o so u n d

r n o s o u n dr n o s o u n d

r n o s o u n d

A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #

A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #

A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #

F

FF

F A N

A NA N

A N

4

44

45

55

5 0 . 2

0 . 20 . 2

0 . 2

C h a n g e J P 2 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 2

C h a n g e J P 2 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 2C h a n g e J P 2 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 2

C h a n g e J P 2 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 2 00 1 _ 2 P to

0 0 1 _ 2 P t o0 0 1 _ 2 P to

0 0 1 _ 2 P t o

A C E S _ 8

A C E S _ 8A C E S _ 8

ACES_88231-02001_2P

8231-02001_2P8231-02001_2P

8231-02001_2P

F

FF

F A N C o n n . n o t c o rre c t p a rt

A N C o n n . n o t c o rre c t p a rtA N C o n n . n o t c o rre c t p a rt

A N C o n n . n o t c o rre c t p a rtH W

H WH W

H W

1 1

1 11 1

1 1 / 0 1

/ 0 1/ 0 1

/ 0 1

6

66

6 2 9

2 92 9

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S pS p

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e a k ere a k er

e a k er

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H WH W

H W S p e a k e r C o n n . n o t c o rr e c t p a

S p e a k e r C o n n . n o t c o r r e c t p aS p e a k e r C o n n . n o t c o r r e c t p a

S p e a k e r C o n n . n o t c o r r e c t p a rt

rtrt

rt

C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 4 0

C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 4 0C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 4 0

C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 5 2 0 4 - 0 4 0 0 1 _ 4 P t o

0 1 _ 4 P t o0 1 _ 4 P to

0 1 _ 4 P t o

A C E S _ 8

A C E S _ 8A C E S _ 8

ACES_88231-04001_4P

8231-04001_4P8231-04001_4P

8231-04001_4P

7

77

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3 43 4

3 4

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M D CM D C

M D C 1 1

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H WH W

H W M D C C o n n . n o t c o r r e c t

M D C C o n n . n o t c o r r e c t M D C C o n n . n o t c o r r e c t

M D C C o n n . n o t c o r r e c t p a r t

p a r tp a r t

p a r t 0 . 2

0 . 20 . 2

0 . 2

C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 8 0 1 8 - 1

C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 8 0 1 8 - 1C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 8 0 1 8 - 1

C h a n g e J P 2 0 P C B F o o t p r in t f ro m A C E S _ 8 8 0 1 8 - 1 2 4 G _ 1 2 P t o

2 4 G _ 1 2 P t o2 4 G _ 1 2 P t o

2 4 G _ 1 2 P t o

A C E S _ 8 8

A C E S _ 8 8A C E S _ 8 8

A C E S _ 8 8 0 2 0 - 1 2 1 0 1 _ 1 2 P

020-12101_12P020-12101_12P

020-12101_12P

8

88

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11,11,

1 1 , 3 5

3 53 5

3 5

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TT

T V _ O U T

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V _ O U T 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

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H W

H WH W

H W T V - O U T F u n

T V - O U T F u nT V - O U T F u n

T V - O U T F u n c t io n n o s u p p o r t

c t io n n o s u p p o r tc t i o n n o s u p p o r t

c t io n n o s u p p o r t

D

DD

D e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V -O U T r e l a t e d d e s i g n .

e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V -O U T r e l a t e d d e s i g n .e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V -O U T r e l a t e d d e s i g n .

e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V -O U T r e l a t e d d e s i g n .

0 . 2

0 . 20 . 2

0 . 2

9

99

9 1 1 ,

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2 12 1

2 1

N B / S B T h e

N B / S B T h eN B / S B T h e

N B / S B T h e rm al

r m a lr m a l

r m a l 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

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H W

H WH W

H W N B T h e r m

N B T h e r mN B T h e r m

N B T h e r m a l F u n c tio n n o s u p p o rt (lo c a t e t o o f a r )

a l F u n c t i o n n o s u p p o r t ( l o c a t e to o f a r)a l F u n c t i o n n o s u p p o r t ( l o c a t e to o f a r)

a l F u n c t i o n n o s u p p o r t ( l o c a t e to o f a r)

C a n ce l N B _ T H E R M A L _ D A / D C c o n n e c t io n b e

C a n ce l N B _ T H E R M A L _ D A / D C c o n n e c t io n b eC a n ce l N B _ T H E R M A L _ D A / D C c o n n e c t io n b e

C a n ce l N B _ T H E R M A L _ D A / D C c o n n e c t io n b e t w e en N B a n d

tw ee n N B a n dtw ee n N B a n d

tw ee n N B a n d

S B

S BS B

S B ,d e l C 5 0 0

,d e l C 5 0 0, d e l C 5 0 0

,d e l C 5 0 0

0 . 2

0 . 20 . 2

0 . 2

0 . 2

0 . 20 . 2

0 . 21 0

1 01 0

1 0 2 1 ,

21,21,

2 1 , 3 1

3 13 1

3 1

S B

S BS B

S B S A T A

S A T A S A T A

S A T A 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

/ 0 5

H W

H WH W

H W S B S

S B SS B S

S B S A T A P o rt 5 c h a n g e t o P o rt 2 f o r A T I C o m m o n

A T A P o rt 5 c h a n g e t o P o rt 2 f o r A T I C o m m o nA T A P o rt 5 c h a n g e t o P o rt 2 f o r A T I C o m m o n

A T A P o rt 5 c h a n g e t o P o rt 2 f o r A T I C o m m o n

D

DD

D e s i g n

e s i g ne s i g n

e s i g n

C h a n g e S B S A T A

C h a n g e S B S A T A C h a n ge S B S A T A

C h a n g e S B S A T A p o r t 5 to p o rt 2

p o rt 5 t o p o r t 2p o r t 5 to p o r t 2

p o rt 5 t o p o r t 2

1 1

1 11 1

1 1 0 . 2

0 . 20 . 2

0 . 22 1

2 12 1

2 1

S B

S BS B

S B S A T A

S A T A S A T A

S A T A 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

/ 0 5

H W

H WH W

H W S B S A T A _ A C T # P u l l H ig h b e c o m

S B S A T A _ A C T # P u l l H ig h b e c o mS B S A T A _ A C T # P u l l H ig h b e c o m

S B S A T A _ A C T # P u l l H ig h b e c o m e + 3 V S

e + 3 V Se + 3 V S

e + 3 V S

C h a n g e R 3 4 3 .1 p o w e r r a il f r o m + 5 V S t o + 3 V

C h a n g e R 3 4 3 .1 p o w e r r a il f r o m + 5 V S t o + 3 VC h a n g e R 3 4 3 .1 p o w e r r a i l f r o m + 5 V S t o + 3 V

C h a n g e R 3 4 3 .1 p o w e r r a il f r o m + 5 V S t o + 3 V S . I n s ta ll R 3 4 3 .

S . In s ta ll R 34 3 .S . I n s t a ll R 3 4 3 .

S . In s ta ll R 34 3 .

1 2

1 21 2

1 2 2 1

2 12 1

2 1 0 . 2

0 . 20 . 2

0 . 2

S

SS

S B G P I O

B G P IOB G P I O

B G P IO 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

/ 0 5

H W

H WH W

H W C

CC

C h a n g e S B G P I O r e f e r t o J B K 0 0 f o r c o m m o n

h a n g e S B G P I O r e f e r t o J B K 0 0 fo r c o m m o nh a n g e S B G P I O r e f e r t o J B K 0 0 fo r c o m m o n

h a n g e S B G P I O r e f e r t o J B K 0 0 fo r c o m m o n

1 . C o n n e c t U 1 5 . C 6 t o G

1 . C o n n e c t U 1 5 . C 6 t o G1 . C on n e c t U 1 5 . C 6 t o G

1 . C o n n e c t U 1 5 . C 6 t o G N D b y 0 _ 0 4 0 2 .

N D b y 0 _ 0 4 0 2 .N D b y 0 _ 0 4 0 2 .

N D b y 0 _ 0 4 0 2 .

2 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P IO 6

2 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P IO 62 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P IO 6

2 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P IO 6 1 .

1 .1 .

1 .

3 . C h a n g e B T _ C O M B O _ E N # f ro m G P I O 5

3 . C h a n g e B T _ C O M B O _ E N # f ro m G P I O 53 . C h a n g e B T _ C O M B O _ E N # f ro m G P I O 5

3 . C h a n g e B T _ C O M B O _ E N # f ro m G P I O 5 1 t o G P I O 6 2 .

1 t o G P I O 6 2 .1 t o G P I O 6 2 .

1 t o G P I O 6 2 .

4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P IO 6 3 .

4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P IO 6 3 .4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P IO 6 3 .

4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P IO 6 3 .

1 3

1 31 3

1 3 3 1

3 13 1

3 1 0 . 2

0 . 20 . 2

0 . 2

S B

S BS B

S B S A T A

S A T A S A T A

S A T A 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

/ 0 5

H W

H WH W

H W V e r t ic a

V e rt ic aV e r t ic a

V e r t i c a l L 5 1 1 < --> 4 , 2 < - - > 3 f o r l a y o u t r o u t i n g

l L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u t r o u t i n gl L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u t r o u t i n g

l L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u t r o u t i n g

V er t ica l L 5 1 1 < -- > 4 , 2 < -- > 3 f o r la y o u t

V er t ica l L 5 1 1 < -- > 4 , 2 < -- > 3 f o r la y o u tV er t ica l L 5 1 1 < -- > 4 , 2 < -- > 3 f o r la y o u t

V er t ica l L 5 1 1 < -- > 4 , 2 < -- > 3 f o r la y o u t ro u t in g

ro u ti n g rou t in g

ro u ti n g

1 4

1 41 4

1 4 2 9

2 92 9

2 9

A u d io H

A u d io HA u d io H

A u d io H P O U T

P O U TP O U T

P O U T 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

/ 0 5

H W

H WH W

H W 0 . 2

0 . 20 . 2

0 . 2A d d

A d d A d d

A d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L

1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L

1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L

A d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R /L

A d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R /LA d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R /L

A d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R /L

1 5

1 51 5

1 5 2 5

2 52 5

2 5

L A N

L A NL A N

L A N T r a n s f e rm o r

T r a n sf e r m o r T r a n s f e rm o r

T r a n sf e r m o r 1 1

1 11 1

1 1 / 0 5

/ 0 5/ 0 5

/ 0 5

H W

H WH W

H W C o r r e c t

C o r r e c t C o r r e c t

C o r r e c t U 1 9 L A N T ra n s f e r m o r p i n d e f i n i t io n

U 1 9 L A N T r a n s fe rm o r p in d e fin it i o nU 1 9 L A N T r a n s f e r m o r p in d e f in it i o n

U 1 9 L A N T r a n s fe rm o r p in d e fin it i o n

C o r r e ct U 1 9 L A N T ra n s f e r m o r p in d e

C o r r e ct U 1 9 L A N T ra n s f e r m o r p in d eC o r r e ct U 1 9 L A N T ra n s f e r m o r p in d e

C o r r e ct U 1 9 L A N T ra n s f e r m o r p in d e fin it io n

f in i t io nfi n it io n

f in i t io n

0 . 2

0 . 20 . 2

0 . 2

1 6

1 61 6

1 6 0 . 2

0 . 20 . 2

0 . 22 1 ,

21,21,

2 1 , 2 4

2 42 4

2 4

S B

S BS B

S B S A T A

S A T A S A T A

S A T A 1 1

1 11 1

1 1 / 0 6

/ 0 6/ 0 6

/ 0 6

H W

H WH W

H W S

SS

S B S A T A P o rt 4 c h a n g e t o P o rt 3 f o r A T I O p e n I s su e

B S A T A P o rt 4 c h a n g e t o P o rt 3 f o r A T I O p e n I s s u eB S A T A P o rt 4 c h a n g e t o P o rt 3 f o r A T I O p e n I s s u e

B S A T A P o rt 4 c h a n g e t o P o rt 3 f o r A T I O p e n I s s u e

C h a n g e S B S A T A

C h a n g e S B S A T A C h a n ge S B S A T A

C h a n g e S B S A T A p o r t 4 to p o rt 3

p o rt 4 t o p o r t 3p o r t 4 to p o r t 3

p o rt 4 t o p o r t 3

1 7

1 71 7

1 7 3 6

3 63 6

3 6

D I M L E D

D I M L E DD I M L E D

D I M L E D 1 1

1 11 1

1 1 / 0 6

/ 0 6/ 0 6

/ 0 6

H W

H WH W

H W 0 . 2

0 . 20 . 2

0 . 2R e

R eR e

R e d u c e D IM L E D u n n e c e s s a ry d e s ig n

d u c e D IM L E D u n n e c e s s a r y d e s i g nd u c e D IM L E D u n n e c e s s a r y d e s i g n

d u c e D IM L E D u n n e c e s s a r y d e s i g n

D el R 1 0 2 6 a n d Q 1 6 7 , a d d N e t "D I M _ L E D # " f o

D el R 1 0 2 6 a n d Q 1 6 7 , a d d N e t "D I M _ L E D # " f oD el R 1 0 2 6 a n d Q 1 6 7 , a d d N e t "D I M _ L E D # " f o

D el R 1 0 2 6 a n d Q 1 6 7 , a d d N e t "D I M _ L E D # " f o r co n n e ct.

r c o n n ec t .r c o n n ec t .

r c o n n ec t .

C h a n g e lo c a t i o n f r o m P J P 6 0

C h a n g e lo c a t i o n f r o m P J P 6 0C h a n g e l o c a t io n f r o m P J P 6 0

C h a n g e lo c a t i o n f r o m P J P 6 0 4 t o P J P 8 .

4 t o P J P 8 .4 t o P J P 8 .

4 t o P J P 8 .

1 8

1 81 8

1 8 2 7

2 72 7

2 7

C a r

C a rC a r

C a r d R e a d er

d R e a d erd R e a d er

d R e a d er 1 1

1 11 1

1 1 / 0 6

/ 0 6/ 0 6

/ 0 6

H W

H WH W

H W 0 . 2

0 . 20 . 2

0 . 2C h a n g e C a r d R ea d e r S o c k e t f o r M / E n e w p a rt

C h a n g e C a r d R ea d e r S o c k e t f o r M / E n e w p a rtC h a n g e C a r d R ea d e r S o c k e t f o r M / E n e w p a rt

C h a n g e C a r d R ea d e r S o c k e t f o r M / E n e w p a rt a n d

a n d a n d

a n d

C h i p f o

C h i p f oC h i p f o

C h i p f o r J M i c r o n n e w v e r s io n

r J M ic r o n n e w v e rs i o nr J M ic r o n n e w v e rs i o n

r J M ic r o n n e w v e rs i o n

C h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 -L

C h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 -LC h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 - L

C h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 -L M .

M .M .

M .

R e s e r v e R 4 1 3 ,C 9 0 2 c l o s e t o J R E A D .2

R e s e r v e R 4 1 3 ,C 9 0 2 c l o s e t o J R E A D .2R e s e r v e R 4 1 3 ,C 9 0 2 c l o s e t o J R E A D .2

R e s e r v e R 4 1 3 ,C 9 0 2 c l o s e t o J R E A D .2 0;

0 ; 0 ;

0 ;

R 4 1 2 , C 9 0 1 c lo s e t o J R E A D .2 6 ; R 4 1 1 , C 9 0 0 c l o s e

R 4 1 2 , C 9 0 1 c lo s e t o J R E A D .2 6 ; R 4 1 1 , C 9 0 0 c l o s eR 4 1 2 ,C 9 0 1 clo s e t o J R E A D .2 6 ; R 4 1 1 , C 9 0 0 c l o s e

R 4 1 2 , C 9 0 1 c lo s e t o J R E A D .2 6 ; R 4 1 1 , C 9 0 0 c l o s e t o J R E A D .3 7 .

to J R E A D .3 7 . t o J R E A D .3 7 .

to J R E A D .3 7 .

C

CC

C h a n ge R 4 5 7 c l o s e t o U 2 3 . 4 2

h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2

h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2

A d d

A d d A d d

A d d R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2

R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2

R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2

D e l Q

D e l QD e l Q

D e l Q 1 6 9 , R 1 0 5 1 .

169,R1051.169,R1051.

169,R1051.

C h a n g e n e t C R _ L E D # b eco m e C R _ L E D c o n n e c t U

C h a n g e n e t C R _ L E D # b eco m e C R _ L E D c o n n e c t UC h a n g e n e t C R _ L E D # b eco m e C R _ L E D c o n n e c t U

C h a n g e n e t C R _ L E D # b eco m e C R _ L E D c o n n e c t U 2 3 . 2 1 a n d Q 53 .2

2 3 . 2 1 a n d Q 5 3 . 22 3 . 2 1 a n d Q 53 . 2

2 3 . 2 1 a n d Q 5 3 . 2

A d d R 4 5 4 p u ll d o w n t o

A d d R 4 5 4 p u ll d o w n t o A d d R 4 5 4 p u ll d o w n t o

A d d R 4 5 4 p u ll d o w n t o G N D

G N DG N D

G N D

C h a n g e R 4 0 5 ,R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u ll- h

C h a n g e R 4 0 5 ,R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u ll- hC h a n g e R 4 0 5 ,R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u ll- h

C h a n g e R 4 0 5 ,R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u ll- h ig h

i g hi g h

i g h

R e m o v

R e m o vR e m o v

R e m o v e C 8 9 5 , U 2 2

e C 8 9 5 , U 2 2e C 8 9 5 , U 2 2

e C 8 9 5 , U 2 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

47 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

1 9

1 91 9

1 9 1 6

1 61 6

1 6

C

CC

C R T

R TR T

R T 1 1

1 11 1

1 1 / 0 7

/ 0 7/ 0 7

/ 0 7

H W

H WH W

H W N o r m a l i

N o r m a l iN o r m a l i

N o r m a l i z e C R T d e s i g n f o r c o m m o n

z e C R T d e s i g n f o r c o m m o nz e C R T d e s i g n f o r c o m m o n

z e C R T d e s i g n f o r c o m m o n

C h a n

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491 from 200_0402 to 200_0805491 from 200_0402 to 200_0805

491 from 200_0402 to 200_0805

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U p d a t e th e W e b C a m + D ig it a l M i c r e s e rv e r co n n .

c o n n .c o n n .

c o n n .

C h a n g e

C h a n g e C h a n g e

C h a n g e J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p i n ) -- > S P 0 2 0 0 0 I L 0 0 ( 6 p i n )

J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p in )- -> S P 0 2 0 0 0 I L 0 0 (6 p i n )J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p in )- -> S P 0 2 0 0 0 I L 0 0 (6 p i n )

J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p in )- -> S P 0 2 0 0 0 I L 0 0 (6 p i n )

0 . 2

0 . 20 . 2

0 . 2

3 7

3 73 7

3 7 6 ,

6 ,6 ,

6 , 3 1

3 13 1

3 1

1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e d u c e S 3

R e d u c e S 3 R e d u c e S 3

R e d u c e S 3 p o w e r c o n s u m p t i o n

p o w e r c o n s u m p t io np o w e r c o n s u m p t io n

p o w e r c o n s u m p t io n

C h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o n

C h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o nC h a n ge R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o n

C h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o n n ec t io n fr o m

n e ct io n f ro mn ec t io n f ro m

n e ct io n f ro m

+ 1 . 8 V t o + 1 .8 V S ; R em o v e R 6 2 2 , i n s

+ 1 . 8 V t o + 1 .8 V S ; R em o v e R 6 2 2 , i n s+ 1 .8 V t o + 1 . 8 V S ; R e m o v e R 6 2 2 , i n s

+ 1 . 8 V t o + 1 .8 V S ; R em o v e R 6 2 2 , i n s t a ll R 5 8 1

ta ll R 58 1ta ll R 58 1

ta ll R 58 1

0 . 2

0 . 20 . 2

0 . 2

N B

N BN B

N B

3 8

3 83 8

3 8 1 1

1 11 1

1 1

1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e d u c e

R e d u c eR e d u c e

R e d u c e t h e le v e l s h if t d e s ig n f o r C h i p A 1 2 .

th e le v e l s h i f t d e s i g n f o r C h ip A 1 2 . th e le v e l s h i f t d e s i g n f o r C h ip A 1 2 .

th e le v e l s h i f t d e s i g n f o r C h ip A 1 2 .

D e l Q 6 , R 8 7 ; Q

D e l Q 6 , R 8 7 ; QD e l Q 6 , R 8 7 ; Q

D e l Q 6 , R 8 7 ; Q 5 ,R 8 4 a n d r e p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 )

5 ,R 8 4 a n d r e p l a c e b y 0 o h m (a d d R 6 7 , R 6 8 )5 , R 8 4 a n d r e p l a c e b y 0 o h m (a d d R 6 7 ,R 6 8 )

5 ,R 8 4 a n d r e p l a c e b y 0 o h m (a d d R 6 7 , R 6 8 )

c o n n e c t

c o n n e c t c o n n ec t

c o n n e c t d i r e c t l y . I n s t a ll R 3 7 1 (1 0 K o h m )

d ire c t ly . I n s t a l l R 3 7 1 (1 0 K o h m )d i r ec t l y . I n s t a ll R 3 7 1 (1 0 K o h m )

d ire c t ly . I n s t a l l R 3 7 1 (1 0 K o h m )

0 . 2

0 . 20 . 2

0 . 2

4 0

4 04 0

4 0 6 ,

6 ,6 ,

6 , 3 3

3 33 3

3 3

C P U ,

C P U ,C P U ,

C P U , K B C

K B CK B C

K B C 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W U

UU

U p d a t e T H E R M T R IP # d e s ig n to E C

p d a t e T H E R M T R I P # d e s ig n t o E Cp d a t e T H E R M T R I P # d e s ig n t o E C

p d a t e T H E R M T R I P # d e s ig n t o E C

C h a n g e R 1 6 . 2 c o n n e c

C h a n g e R 1 6 . 2 c o n n e cC h a n g e R 1 6 . 2 c o n n e c

C h a n g e R 1 6 . 2 c o n n e c tio n f ro m T H E R M T R IP # t o

t i o n f r o m T H E R M T R I P # t otio n f r o m T H E R M T R IP # t o

t i o n f r o m T H E R M T R I P # t o

T H E R M T R I P # _ E C f o r

T H E R M T R I P # _ E C f o rT H E R M T R I P # _ E C f o r

T H E R M T R I P # _ E C f o r s e p a r a t e

se p a r a t e s e p a r a t e

se p a r a t e

0 . 2

0 . 20 . 2

0 . 2

4 1

4 14 1

4 1 1 8

1 81 8

1 8

H

HH

H D M I

D M ID M I

D M I 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e

R eR e

R e m o v e E M I s o lu tio n b e c o m e re se rv e f o r v e r ify

m o v e E M I s o lu t i o n b e c o m e re s e r v e f o r v e r ifym o v e E M I so lu t i o n b e c o m e r e s e r v e f o r v e r i f y

m o v e E M I s o lu t i o n b e c o m e re s e r v e f o r v e r ify

A d d R

A d d RA d d R

A d d R 1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - la y

1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y

1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y

0 . 2

0 . 20 . 2

0 . 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

48 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

4 2

4 24 2

4 2 1 9 .

19.19.

1 9 . 3 2

3 23 2

3 2

S B

S BS B

S B ,B I O S

,B I O S,B I O S

,B I O S 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e d

R e dR e d

R e d u c e S B r e la t e d d e si g n fo r C h ip A 1 2 a n d o t h e r s

u c e S B re l a t e d d e s i g n f o r C h i p A 1 2 a n d o t h e r su c e S B re l a t e d d e s i g n f o r C h i p A 1 2 a n d o t h e r s

u c e S B re l a t e d d e s i g n f o r C h i p A 1 2 a n d o t h e r s

D e

D eD e

D e l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 clo s e t o U 1 5 .

l Q 1 5 5 , R 9 8 6 , a n d a d d R 3 1 1 c l o s e t o U 1 5 .l Q 15 5 ,R 9 8 6 , a n d a d d R 3 1 1 clo s e t o U 1 5 .

l Q 1 5 5 , R 9 8 6 , a n d a d d R 3 1 1 c l o s e t o U 1 5 .

D e l R 1 0 1 1 b e c o m e T

D e l R 1 0 1 1 b e c o m e TD e l R 1 0 1 1 b e c o m e T

D e l R 1 0 1 1 b e c o m e T 1 8 , C a n c e l R 1 0 1 2 a n d co n n e c t t o H 3 1

1 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 11 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 1

1 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 1

a n d J P 4 1

a n d J P 4 1 a n d J P 4 1

a n d J P 4 1 d ire c t ly

d i r e c t l yd i r e c t l y

d i r e c t l y

0 . 2

0 . 20 . 2

0 . 2

4 3

4 34 3

4 3 2 1 ,

21,21,

2 1 , 3 2

3 23 2

3 2

S B

S BS B

S B ,B I O S

,B I O S,B I O S

,B I O S 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W B I O S D eb u g T o o l r e s e r

B I O S D eb u g T o o l r e s e rB I O S D eb u g T o o l r e s e r

B I O S D eb u g T o o l r e s e r v e

v ev e

v e 0 . 2

0 . 20 . 2

0 . 2

A d d S B _ I N T _ F L A S H _ S E

A d d S B _ I N T _ F L A S H _ S EA d d S B _ I N T _ F L A S H _ S E

A d d S B _ I N T _ F L A S H _ S E L a n d re l a t e d

L a n d r e l a t e dL a n d re l a t e d

L a n d r e l a t e d

(J P 1 2 , U 3 0 ,R 2 2 8 , R 2 2 6 ,C 4 8 9 c lo s e t o U

(J P 1 2 , U 3 0 ,R 2 2 8 , R 2 2 6 ,C 4 8 9 c lo s e t o U( J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 , C 4 8 9 c l o s e t o U

(J P 1 2 , U 3 0 ,R 2 2 8 , R 2 2 6 ,C 4 8 9 c lo s e t o U 2 9 )

29)29)

29)

4 4

4 44 4

4 4 2 5

2 52 5

2 5

L

LL

L A N

A NA N

A N 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W U p d a t e

U p d a t eU p d a t e

U p d a t e L A N C h ip S y m b o l lin k to C I S se r v e r

L A N C h i p S y m b o l lin k t o C I S s e r v e r L A N C h i p S y m b o l lin k t o C I S s e r v e r

L A N C h i p S y m b o l lin k t o C I S s e r v e r

U p d a t e L A N

U p d a t e L A N U p d a t e L A N

U p d a t e L A N C h i p U 2 0 S y m b o l l i n k t o C I S s e rv e r

C h i p U 2 0 S y m b o l lin k t o C I S se r v e rC h i p U 2 0 S y m b o l lin k t o C I S se r v e r

C h i p U 2 0 S y m b o l lin k t o C I S se r v e r

0 . 2

0 . 20 . 2

0 . 2

4 5

4 54 5

4 5 1 3

1 31 3

1 3

N B

N BN B

N B 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W A d d 0 o h m _ 0 6 0 3 t o

A d d 0 o h m _ 0 6 0 3 t oA d d 0 o h m _ 0 6 0 3 t o

A d d 0 o h m _ 0 6 0 3 t o s e p a r a te V D D 1 8 _ M E M

se p a ra t e V D D 1 8 _ M E M se p a ra t e V D D 1 8 _ M E M

se p a ra t e V D D 1 8 _ M E M

Add R1051(0_0603) b

Add R1051(0_0603) bAdd R1051(0_0603) b

A d d R 1 0 5 1 ( 0 _ 0 6 0 3 ) b et w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S P

e t w ee n + 1 . 8 V S & + 1 .8 V _ V D D _ S Pe t w ee n + 1 . 8 V S & + 1 .8 V _ V D D _ S P

e t w ee n + 1 . 8 V S & + 1 .8 V _ V D D _ S P

0 . 2

0 . 20 . 2

0 . 2

4 6

4 64 6

4 6 1 8

1 81 8

1 8

H

HH

H D M I

D M ID M I

D M I 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e

R eR e

R e d u c e H D M I r e l a t e d d e s i g n f o r c o m m o n

d u c e H D M I r e la t e d d e s i g n f o r c o m m o nd u c e H D M I re la te d d e s ig n f o r c o m m on

d u c e H D M I r e la t e d d e s i g n f o r c o m m o n

D e l

D e lD e l

D e l R 4 9 0 (1 0 0 K _ 0 4 0 2 )

R490 (100K_0402) R490 (100K_0402)

R490 (100K_0402)

0 . 2

0 . 20 . 2

0 . 2

4 7

4 74 7

4 7 2 0

2 02 0

2 0

S B

S BS B

S B 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e d u

R e d uR e d u

R e d u ce S B r e la t e d d e s ig n fo r c o m m on a n d A 1 2 c h ip

c e S B re l a t e d d e s ig n f o r c o m m on a n d A 1 2 c h ipc e S B re l a t e d d e s ig n f o r c o m m on a n d A 1 2 c h ip

c e S B re l a t e d d e s ig n f o r c o m m on a n d A 1 2 c h ip

R em o v e

R em o v e R e m o v e

R em o v e R 9 9 4 (0 _ 0 4 0 2 )

R994 (0_0402)R994 (0_0402)

R994 (0_0402)

C h a n g e U 1

C h a n g e U 1C h a n g e U 1

C h a n g e U 1 5 .F 1 c o n n e c t i o n b e c o m e t es t p o i n t

5 .F 1 c o n n e c t i o n b e c o m e t es t p o i n t5 .F 1 c o n n e c t i o n b e c o m e t es t p o i n t

5 .F 1 c o n n e c t i o n b e c o m e t es t p o i n t

R em o v e R 1 0 5 3 ,

R em o v e R 1 0 5 3 ,R em o v e R 1 0 5 3 ,

R em o v e R 1 0 5 3 , c h a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2

ch a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2 c h a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2

ch a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2

0 . 2

0 . 20 . 2

0 . 2

4 8

4 84 8

4 8 2 0 , 2 1 ,

20,21,20,21,

20,21,

2 7

2 72 7

2 7

S B ,C

S B ,CS B ,C

S B ,C a r d re a d er

a r d re a d e ra r d r ea d e r

a r d re a d e r 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e s e r v e C a r d re a d e r D 3 E f u n c t i o n (C R _ W A

R e s e r v e C a rd r e a d e r D 3 E f u n c t i o n (C R _ W AR e s e r v e C a rd r e a d e r D 3 E f u n c t i o n (C R _ W A

R e s e r v e C a rd r e a d e r D 3 E f u n c t i o n (C R _ W A K E # &

K E # &K E # &

K E # &

C R _ C

C R _ CC R _ C

C R _ C P P E # )

P P E # )P P E # )

P P E # )

A d d R

A d d RA d d R

A d d R 8 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 8

8 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 88 1 cl o s e t o U 1 5 ; Q 5 4 , R 1 2 4 cl o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 8

8 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 8

t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n ec t U 1 5 . M 5 t o U 2 3 .

t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n ec t U 1 5 . M 5 t o U 2 3 . to U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n ec t U 1 5 . M 5 t o U 2 3 .

t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n ec t U 1 5 . M 5 t o U 2 3 . 1 6

1 61 6

1 6

0 . 2

0 . 20 . 2

0 . 2

4 9

4 94 9

4 9 2 1 ,

21,21,

2 1 , 3 3

3 33 3

3 3

S B ,K B C

S B ,K B CS B ,K B C

S B ,K B C 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R

RR

R e d u c e S B re l a t e d d e s ig n f o r c o m m on

e d u c e S B r e la t e d d e sig n fo r c o m m o ne d u c e S B r e la t e d d e sig n fo r c o m m o n

e d u c e S B r e la t e d d e sig n fo r c o m m o n

D el D 5 1 a n d R 1 0 3 4 , C h a n ge t h e n e t A C _ IN

D el D 5 1 a n d R 1 0 3 4 , C h a n ge t h e n e t A C _ IND el D 5 1 a n d R 1 0 3 4 , C h a n ge t h e n e t A C _ IN

D el D 5 1 a n d R 1 0 3 4 , C h a n ge t h e n e t A C _ IN b ec o m e A C _ IN _ D

b e co m e A C _ I N _ D b e co m e A C _ I N _ D

b e co m e A C _ I N _ D

0 . 2

0 . 20 . 2

0 . 2

5 0

5 05 0

5 0 2 8 ,

28,28,

2 8 , 3 3

3 33 3

3 3

C

CC

C o d e c , K B C

o d e c , K B Co d e c ,K B C

o d e c , K B C 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H P Q

H P QH P Q

H P Q E C

E CE C

E C _ B E E P f u n c t i o n f o r K B C a d d

_ B E E P f u n c t i o n f o r K B C a d d_ B E E P f u n c t i o n f o r K B C a d d

_ B E E P f u n c t i o n f o r K B C a d d

A d

A dA d

A d d R 5 6 3 c lo s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1

d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1

d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1

0 . 2

0 . 20 . 2

0 . 2

5 1

5 15 1

5 1 3 3

3 33 3

3 3

K B C

K B CK B C

K B C 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e d u c e

R e d u c e R e d u c e

R e d u c e S 5 P o w er C o n s u m p t io n

S 5 P o w er C o n s u m p t i o nS 5 P o w er C o n s u m p t io n

S 5 P o w er C o n s u m p t i o n

C h a n g e R 1 0 4 0 . 1 c o n n e c t io n f r o m + 3 V L _

C h a n g e R 1 0 4 0 . 1 c o n n e c t io n f r o m + 3 V L _C h a n g e R 1 0 4 0 . 1 c o n n e c t i o n f r o m + 3 V L _

C h a n g e R 1 0 4 0 . 1 c o n n e c t io n f r o m + 3 V L _ E C t o + 3 V A L W

E C to + 3 V A L WE C to + 3 V A L W

E C to + 3 V A L W

D el R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p la c e b y a d d R 5 4 7 c l o s

D el R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p la c e b y a d d R 5 4 7 c l o sD el R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p la c e b y a d d R 5 4 7 c l o s

D el R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p la c e b y a d d R 5 4 7 c l o s e t o

e t oe to

e t o

U

UU

U 3 3 f o r s h o r t

3 3 f o r s h o r t3 3 f o r s h o rt

3 3 f o r s h o r t

0 . 2

0 . 20 . 2

0 . 2

5 2

5 25 2

5 2 3 3

3 33 3

3 3

K B C

K B CK B C

K B C 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W R e d u c e K B C D e s ig n f o r c o m m on a n d V e r:C 0

R e d u c e K B C D e s ig n f o r c o m m o n a n d V e r :C 0R e d u c e K B C D e s ig n f o r c o m m o n a n d V e r :C 0

R e d u c e K B C D e s ig n f o r c o m m o n a n d V e r :C 0 C h ip

C h ip C h i p

C h ip

C h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S A

C h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S AC h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S A

C h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S A 0 0 0 0 1 J 5 4 0

00001J54000001J540

00001J540

D el R 5 3 7 b e c o m e T e s t P o in t, c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6

D el R 5 3 7 b e c o m e T e s t P o in t, c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6D e l R 5 3 7 b e c o m e T es t P o i n t , ch a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6

D el R 5 3 7 b e c o m e T e s t P o in t, c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6 03

0 30 3

0 3

R e m o v e R 1 0 4 4 , ch a n g e R 1 0 4 0 f r o m 1 0 K t o 1

R e m o v e R 1 0 4 4 , ch a n g e R 1 0 4 0 f r o m 1 0 K t o 1R em o v e R 1 0 4 4 , c h a n ge R 1 0 4 0 f r o m 1 0 K t o 1

R e m o v e R 1 0 4 4 , ch a n g e R 1 0 4 0 f r o m 1 0 K t o 1 0 0 K

00K00K

00K

C h a n g e R 5 2 8 .2 , R 5 2 9 .2 c o n n e ct i o n f r o m + 5

C h a n g e R 5 2 8 .2 , R 5 2 9 .2 c o n n e ct i o n f r o m + 5C h a n g e R 5 2 8 .2 , R 5 2 9 .2 co n n e ctio n f r o m + 5

C h a n g e R 5 2 8 .2 , R 5 2 9 .2 c o n n e ct i o n f r o m + 5 V A L W to + 5 V L

V A L W t o + 5 V LV A L W t o + 5 V L

V A L W t o + 5 V L

I n s t a l l C 8 1 4 ( 4 . 7 U _ 0 8 0 5 )

I n s t a l l C 8 1 4 ( 4 . 7 U _ 0 8 0 5 )I n s t a l l C 8 1 4 ( 4 . 7 U _ 0 8 0 5 )

I n s t a l l C 8 1 4 ( 4 . 7 U _ 0 8 0 5 )

0 . 2

0 . 20 . 2

0 . 2

5 3

5 35 3

5 3 3 4

3 43 4

3 4

S w i

S w iS w i

S w i t ch D es ig n

tc h D es ig ntc h D es ig n

tc h D es ig n 1 1

1 11 1

1 1 / 1 3

/ 1 3/ 1 3

/ 1 3

H W

H WH W

H W U p d a t e C S D f

U p d a t e C S D fU p d a t e C S D f

U p d a t e C S D f u n c t io n b o a r d d e s i g n f o r c o m m o n

u n c t io n b o a r d d e s i g n f o r c o m m o nu n c t i o n b o a r d d e s ig n f o r c o m m o n

u n c t io n b o a r d d e s i g n f o r c o m m o n

C h a n g e J P 3 6 . 1 c o n n e c t io n b e c o m e + 3 V L ;C h a n g e R 1

C h a n g e J P 3 6 . 1 c o n n e c t io n b e c o m e + 3 V L ;C h a n g e R 1C h a n g e J P 3 6 . 1 c o n n e c t io n b e c o m e + 3 V L ;C h a n g e R 1

C h a n g e J P 3 6 . 1 c o n n e c t io n b e c o m e + 3 V L ;C h a n g e R 1 0 4 6 .1

046.1 046.1

046.1

a n d R 1 0 4 7 .1 c o n n ect i o n b e c o m e S M B _

a n d R 1 0 4 7 .1 c o n n ect i o n b e c o m e S M B _a n d R 1 0 4 7 .1 c o n n ect i o n b e c o m e S M B _

a n d R 1 0 4 7 .1 c o n n ect i o n b e c o m e S M B _ E C _ C K 1/D A 1

E C _ C K 1 /D A 1E C _ C K 1 /D A 1

E C _ C K 1 /D A 1

C h a n g e J P 3 6 . 7 c o n n e c t io n f r o m G N

C h a n g e J P 3 6 . 7 c o n n e c t io n f r o m G NC h a n g e J P 3 6 . 7 c o n n e c t i o n f r o m G N

C h a n g e J P 3 6 . 7 c o n n e c t io n f r o m G N D t o + 5 V A L W _ L E D b y

D t o + 5 V A L W _ L E D b y D t o + 5 V A L W _ L E D b y

D t o + 5 V A L W _ L E D b y

0 . 2

0 . 20 . 2

0 . 2

5 4

5 45 4

5 4 3 4

3 43 4

3 4

L

LL

L E D

E DE D

E D 1 1

1 11 1

1 1 / 1 4

/ 1 4/ 1 4

/ 1 4

H W

H WH W

H W C o r r e c t T / P O n / O f f L E D d e s ig n d e f

C o r r e c t T / P O n / O f f L E D d e s ig n d e fC o rr e c t T / P O n / O f f L E D d e s i g n d e f

C o r r e c t T / P O n / O f f L E D d e s ig n d e f in e

in ein e

in e

C o r r e

C o r r eC o r r e

C o r r e ct G - S e n so r L E D d e s i g n d e fin e

c t G -S e n s o r L E D d e s ig n d e f in ect G - S e n s o r L E D d e s i g n d e f i n e

c t G -S e n s o r L E D d e s ig n d e f in e

C

CC

C h a n ge Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2

h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2

h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2

C h a n g e R 9 8 8 .1 c o n n e ct io n f r o m +

C h a n g e R 9 8 8 .1 c o n n e ct io n f r o m +C h a n g e R 9 8 8 . 1 c o n n e c t io n f r o m +

C h a n g e R 9 8 8 .1 c o n n e ct io n f r o m + 5 V S _ L E D to + 3 V S

5 V S _ L E D t o + 3 V S5 V S _ L E D to + 3 V S

5 V S _ L E D t o + 3 V S

0 . 2

0 . 20 . 2

0 . 2

2 9

2 92 9

2 9

A u d io

A u d ioA u d io

A u d i o - D o c k

- D o c k- D o c k

- D o c k 1 1

1 11 1

1 1 / 1 4

/ 1 4/ 1 4

/ 1 4

H P Q

H P QH P Q

H P Q F

FF

F o r G S m a rk r e q u ire m en t

o r G S m a rk r e q u ire m en to r G S m a r k r e q u ir e m e n t

o r G S m a rk r e q u ire m en t

A d

A dA d

A d d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .

d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .

d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .

0 . 2

0 . 20 . 2

0 . 25 5

5 55 5

5 5

H o le s

H o le sH o l e s

H o le s 1 1

1 11 1

1 1 / 1 4

/ 1 4/ 1 4

/ 1 4

M E

M EM E

M E U p d a t e

U p d a t e U p d a t e

U p d a t e H o l e s t o m ee t M / E D ra w in g

H o le s t o m e e t M / E D ra w in gH o l e s t o m e e t M / E D ra w i n g

H o le s t o m e e t M / E D ra w in g

A d d

A d d A d d

A d d b a ck H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4

b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D el C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4

b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D el C F 4

0 . 2

0 . 20 . 2

0 . 25 6

5 65 6

5 6 2 9

2 92 9

2 9

M u

M uM u

M u lt i- B a y

lt i- B a ylti- B a y

lt i- B a y 1 1

1 11 1

1 1 / 1 4

/ 1 4/ 1 4

/ 1 4

5 7

5 75 7

5 7 M E

M EM E

M E U p d a t e S y

U p d a t e S yU p d a t e S y

U p d a t e S y m bo l to m e e t M / E D ra w in g

m b o l to m e e t M / E D ra w in gm b o l to m e e t M / E D ra w in g

m b o l to m e e t M / E D ra w in g

U p d a t e J P 2 ,J P 9 ,J P 1 0 , J P 1 1 ,J P 2 0 , J P 4 0 ,J H D M I ,J

U p d a t e J P 2 ,J P 9 ,J P 1 0 , J P 1 1 ,J P 2 0 , J P 4 0 ,J H D M I ,JU p d a t e J P 2 ,J P 9 ,J P 1 0 , J P 1 1 ,J P 2 0 , J P 4 0 ,J H D M I ,J

U p d a t e J P 2 ,J P 9 ,J P 1 0 , J P 1 1 ,J P 2 0 , J P 4 0 ,J H D M I ,J E S A T , J C R T ,

E S A T , JC R T ,E S A T , JC R T ,

E S A T , JC R T ,

J D O C K

J D O C KJ D O C K

J D O C K S y m b o l

S y m b o l S y m bo l

S y m b o l

0 . 2

0 . 20 . 2

0 . 24 ,

4 ,4 ,

4 , 2 4

2 42 4

2 4

H o le s

H o le sH o l e s

H o le s 1 1

1 11 1

1 1 / 1 4

/ 1 4/ 1 4

/ 1 4

5 8

5 85 8

5 8 M E

M EM E

M E U p d a t e

U p d a t e U p d a t e

U p d a t e H o l e s t o m ee t M / E D ra w in g

H o le s t o m e e t M / E D ra w in gH o l e s t o m e e t M / E D ra w i n g

H o le s t o m e e t M / E D ra w in g

A d d

A d d A d d

A d d b a ck H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4

b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D el C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4

b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D el C F 4

0 . 2

0 . 20 . 2

0 . 23 3

3 33 3

3 3

S B

S BS B

S B 1 1

1 11 1

1 1 / 1 6

/ 1 6/ 1 6

/ 1 6

5 9

5 95 9

5 9 A

AA

A T I

T IT I

T I R e

R eR e

R e se r v e t o f i x t h e O T S 3 2 5 0 5 5 I s su e

s e rv e to fix t h e O T S 3 2 5 0 5 5 I s s u e se rv e t o fix t h e O T S 3 2 5 0 5 5 I ss u e

s e rv e to fix t h e O T S 3 2 5 0 5 5 I s s u e

R e s

R e sR e s

R e s e r v e R 8 3 P H t o + 3 V S

e rv e R 8 3 P H t o + 3 V Se rv e R 8 3 P H t o + 3 V S

e rv e R 8 3 P H t o + 3 V S

0 . 2

0 . 20 . 2

0 . 22 0

2 02 0

2 0

6 0

6 06 0

6 0

K B C

K B CK B C

K B C 1 1

1 11 1

1 1 / 1 6

/ 1 6/ 1 6

/ 1 6

E C

E CE C

E C3 3

3 33 3

3 3 C h

C hC h

C h a n g e d e s ig n f o r E C t e a m d e b u g

a n g e d e si g n fo r E C te a m d e b u ga n g e d e si g n fo r E C te a m d e b u g

a n g e d e si g n fo r E C te a m d e b u g

C h a n g e J P 3 4 . 1 f r o m + 5 V A L W

C h a n g e J P 3 4 . 1 f r o m + 5 V A L W C h a n g e J P 3 4 . 1 f r o m + 5 V A L W

C h a n g e J P 3 4 . 1 f r o m + 5 V A L W to + 5 V L

to + 5 V Lto + 5 V L

to + 5 V L

0 . 2

0 . 20 . 2

0 . 2

6 1

6 16 1

6 1 3 5

3 53 5

3 5

D O C K

D O C KD O C K

D O C K 1 1

1 11 1

1 1 / 1 6

/ 1 6/ 1 6

/ 1 6

E

EE

E M C

M CM C

M C C o n n e

C o n n eC o n n e

C o n n e c t D O C K g u i d e p i n t o G N D

c t D O C K g u id e p i n t o G N Dc t D O C K g u id e p i n t o G N D

c t D O C K g u id e p i n t o G N D

A d d J D O C K .4 5 / 4 6

A d d J D O C K .4 5 / 4 6 A d d J D O C K . 4 5 / 4 6

A d d J D O C K .4 5 / 4 6 t o G N D

to G N Dt o G N D

to G N D

0 . 2

0 . 20 . 2

0 . 2

6 2

6 26 2

6 2 3 3

3 33 3

3 3

K

KK

K / B

/ B/ B

/ B 1 1

1 11 1

1 1 / 1 6

/ 1 6/ 1 6

/ 1 6

H W

H WH W

H W F i x K B m a t r i

F i x K B m a t r iF ix K B m a t ri

F i x K B m a t r i x issu e

x is s u ex issu e

x is s u e

D el K S I 6 a n d K S O 9 o u t o f p

D el K S I 6 a n d K S O 9 o u t o f pD e l K S I 6 a n d K S O 9 o u t o f p

D el K S I 6 a n d K S O 9 o u t o f p a g e n et c o n n ec t

a g e n e t c o n n e cta g e n et c o n n ec t

a g e n e t c o n n e ct

0 . 2

0 . 20 . 2

0 . 2

6 3

6 36 3

6 3 2 8 ,

28,28,

2 8 , 2 9

2 92 9

2 9

A U

A UA U

A U D I O

D I OD I O

D I O 1 1

1 11 1

1 1 / 1 8

/ 1 8/ 1 8

/ 1 8

H P Q

H P QH P Q

H P Q M a k e s

M a k e sM a k e s

M a k e s om e A u d io re l a t e d d e s ig n c h a n g e

o m e A u d i o re la te d d e s ig n c h a n g eo m e A u d i o re la te d d e s ig n c h a n g e

o m e A u d i o re la te d d e s ig n c h a n g e

C h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , C

C h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , CC h a n g e C 9 8 3 ,C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , C

C h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , C 1 0 5 0 , C 10 4 0 ,C 1 0 4 1

1050,C1040,C1041 1050,C1040,C1041

1050,C1040,C1041

f r o m 0 .4 7 U F t o 0 .0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n g

f r o m 0 .4 7 U F t o 0 .0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n gf r o m 0 .4 7 U F t o 0 .0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n g

f r o m 0 .4 7 U F t o 0 .0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n g e

e e

e

C 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , R

C 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , RC 1 0 4 4 f r o m 1 0 U F t o 4 .7 U F . R e m o v e R 1 0 0 0 , R

C 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , R 1 0 0 4 ; I n s t a l l R 1 0 0 1 , R 1 0 0 3 .

1 0 0 4 ; I n st a ll R 10 0 1 ,R 1 0 0 3 .1 0 0 4 ; I n st a ll R 10 0 1 ,R 1 0 0 3 .

1 0 0 4 ; I n st a ll R 10 0 1 ,R 1 0 0 3 .

0 . 2

0 . 20 . 2

0 . 2

6 4

6 46 4

6 4 2 9

2 92 9

2 9

A U

A UA U

A U D I O

D I OD I O

D I O 1 1

1 11 1

1 1 / 1 9

/ 1 9/ 1 9

/ 1 9

H P Q

H P QH P Q

H P Q M a k e s

M a k e sM a k e s

M a k e s om e A u d io re l a t e d d e s ig n c h a n g e

o m e A u d i o re la te d d e s ig n c h a n g eo m e A u d i o re la te d d e s ig n c h a n g e

o m e A u d i o re la te d d e s ig n c h a n g e

C h a n g e R 9 6 8 ,R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3

C h a n g e R 9 6 8 ,R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3C h a n g e R 9 6 8 , R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3

C h a n g e R 9 6 8 ,R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3

0 . 2

0 . 20 . 2

0 . 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

49 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

6 5

6 56 5

6 5 1 3

1 31 3

1 3

N B

N BN B

N B 1 1

1 11 1

1 1 / 2 0

/ 2 0/ 2 0

/ 2 0

A

AA

A T I

T IT I

T I D e s i g

D e s i gD e s i g

D e s i g n C h a n g e f o r N B A 1 2 V e rs i o n c h ip

n C h a n g e f o r N B A 1 2 V er s io n c h ipn C h a n g e f o r N B A 1 2 V er s io n c h ip

n C h a n g e f o r N B A 1 2 V er s io n c h ip

R e m

R e mR e m

Remove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017.

ove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017.ove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017.

ove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017.

I n

I nI n

I n s t a ll L 1 9 , r e m o v e L 9 5

s t a l l L 1 9 , re m o v e L 9 5s t a l l L 1 9 , re m o v e L 9 5

s t a l l L 1 9 , re m o v e L 9 5

0 . 2

0 . 20 . 2

0 . 2

6 6

6 66 6

6 6 2 2

2 22 2

2 2

S B

S BS B

S B 1 1

1 11 1

1 1 / 2 0

/ 2 0/ 2 0

/ 2 0

A

AA

A T I

T IT I

T I D e s i g

D e s i gD e s i g

D e s i g n C h a n g e f o r S B A 1 2 V er s io n c h ip

n C h a n g e f o r S B A 1 2 V ers i o n c h ipn C h a n g e f o r S B A 1 2 V er s io n c h ip

n C h a n g e f o r S B A 1 2 V ers i o n c h ip

I n s t a l l

I n s t a l l I n s t a l l

I n s t a l l R 5 9 3 , r em o v e R 5 9 2

R 5 9 3 , r e m o v e R 5 9 2R 5 9 3 , re m o v e R 5 9 2

R 5 9 3 , r e m o v e R 5 9 2

0 . 2

0 . 20 . 2

0 . 2

6 7

6 76 7

6 7 2 2

2 22 2

2 2

S B

S BS B

S B 1 1

1 11 1

1 1 / 2 0

/ 2 0/ 2 0

/ 2 0

H W

H WH W

H W R e d u c e S B

R e d u c e S B R e d u c e S B

R e d u c e S B P o w er D es i g n -N o I D E s u p p o r t

P o w er D es i g n -N o I D E s u p p o r tP o w er D es i g n -N o I D E s u p p o r t

P o w er D es i g n -N o I D E s u p p o r t

R e

R eR e

R e m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 , C 5 4 7 , C 5 3 6

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R e s e r v e R 1 0 3 4 c l o s e t o J P 3 6 . 4 , R 1 0 3 5 c l o s e J P 3 6 .5 ,R e m o v e R 1 0 3 6

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C h a n g e R 5 2 0 f ro m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0

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g e d e s i g n f o r n e w v e r sio n C L K G e n .

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re c o m m en d fo r u p d a t e

C h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a n

C h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a nC h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a n

C h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a n g e R 3 5 6 fr o m 1 0 K _ 0 4 0 2

g e R 3 5 6 f r o m 1 0 K _ 04 0 2g e R 3 5 6 f r o m 1 0 K _ 04 0 2

g e R 3 5 6 f r o m 1 0 K _ 04 0 2

t o 2 .2 K _ 0 4 0 2 ; I n s t a ll

t o 2 .2 K _ 0 4 0 2 ; I n s t a ll t o 2 .2 K _ 0 4 0 2 ; I n s t a ll

t o 2 .2 K _ 0 4 0 2 ; I n s t a ll C 2 3 a s 0 . 1 U F _ 0 4 0 2

C 2 3 a s 0 .1 U F _ 0 4 0 2C 2 3 a s 0 .1 U F _ 0 4 0 2

C 2 3 a s 0 .1 U F _ 0 4 0 2

0 . 2

0 . 20 . 2

0 . 2

9 0

9 09 0

9 0 3 3

3 33 3

3 3

K B C

K B CK B C

K B C 1 1

1 11 1

1 1 / 3 0

/ 3 0/ 3 0

/ 3 0

H W

H WH W

H W C

CC

C h a n g e 3 2 .7 6 8 K H z M a in S o u r c e V e n d o r b e c o m e E P S O N

h a n g e 3 2 . 7 6 8 K H z M a i n S o u rc e V en d o r b e c o m e E P S O Nh a n g e 3 2 . 7 6 8 K H z M a i n S o u rc e V en d o r b e c o m e E P S O N

h a n g e 3 2 . 7 6 8 K H z M a i n S o u rc e V en d o r b e c o m e E P S O N

C

CC

C h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0

h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0

h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0

0 . 2

0 . 20 . 2

0 . 2

3 2

3 23 2

3 2

B

BB

B I O S

IO SI O S

IO S

9 1

9 19 1

9 1

1 2

1 21 2

1 2 / 0 3

/ 0 3/ 0 3

/ 0 3

H W

H WH W

H W C a n c e l E x t . B IO S re f la s h d e s i g n b e c a u

C a n c e l E x t . B I O S re f la s h d e s i g n b e c a uC a n c e l E x t . B I O S re f la s h d e s i g n b e c a u

C a n c e l E x t . B I O S re f la s h d e s i g n b e c a u se o f + 3 V L e rroe

se o f + 3 V L e rro ese o f + 3 V L e rro e

se o f + 3 V L e rro e

A d d

A d dA d d

A d d R 2 2 1 ; R em ov e U 3 0 , R 2 2 6 ,R 2 2 8 , C 4 8 9

R 2 2 1 ; R e m ov e U 3 0 ,R 2 2 6 ,R 2 2 8 , C 4 8 9 R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 , R 2 2 8 ,C 4 8 9

R 2 2 1 ; R e m ov e U 3 0 ,R 2 2 6 ,R 2 2 8 , C 4 8 9

0 . 2

0 . 20 . 2

0 . 2

3 4

3 43 4

3 4

L

LL

L E D

E DE D

E D

9 2

9 29 2

9 2

1 2

1 21 2

1 2 / 0 3

/ 0 3/ 0 3

/ 0 3

H W

H WH W

H W C a n c e l

C a n c e lC a n c e l

C a n c e l G - S e n s o r I N T 2 L E D f u n c ti o n

G -S e n s o r I N T 2 L E D f u n c t i o n G - S e n s o r I N T 2 L E D f u n c t i o n

G -S e n s o r I N T 2 L E D f u n c t i o n

R em o v e

R em o v e R e m o v e

R em o v e Q 1 5 6

Q 1 5 6Q 1 5 6

Q 1 5 6

0 . 2

0 . 20 . 2

0 . 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

50 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

01 19 SB HW

Remove R303 from PCICLK3 and add R301 as 0 ohm.

0.3

Add R303 and connect to CLK_PCI_ISO2.

23

Chage net name to PCI_CLK3.

29 Amplifier

Change value from 4.7uF to 1uF.

Speaker

Speaker right and left channel reverse. Reverse JP20 pin define.

31 Finger Printer

Delete R622

32 BIOS ROM

Reserve R221

Stuff U30, R228, R226, C489. Change power from +3VALW to +3VL

33

Add pull down resistor R1063.

T/P ON/OFF LED

Reverse TP on/off LED

35 Docking

Change R572 to 22 ohm and R566 to 2K ohm

35 MDC

Change PCB Footprint from 3P3 to 4P0

12/26

12/26

12/26

12/26

12/26

12/26

EC

12/26

12/26

12/26

12/26

12/26

12/26

SB

SB

BIOS ROM

HW

HW

HW

HW

HW

HW

HW

HW

EC

HW

ME

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

02

03

04

05

06

07

08

09

11

12

13

01/03

HW

HW

HW

0.3

0.3

0.3

Delete R556, R557.

34

R1036

Connect R1046 to JP36.3 and connect R1047 to JP36.9

Switch board

Switch board

Switch board

01/03

01/03 Option Cypress and ENE Cap. board.

Useless

Useless

ME change stand off.

Common design.

19

15

16

17

34

34

34

23

32

Power 0.333

Connect VFIX_EN to EC pin 110.

EC

01/07

18

14 HW 0.319 SB

01/08 Add pull high resistor R1064.

HW17 0.3

Remove reserve circuit for Webcam and Digital MIC.01/08

Webcam and Digital MIC

20

19 EMI

0.3

24 SB

01/09 Add reserve cap. C1085~C1087.

25 19 EMI

0.3

SB

Fine-tune R302, R303, R308 from 22 ohm to 33 ohm.

26 20 SB EMI

0.3

Add reserve cap. C1088~C1091

27 21 SB DFB

Y4 Change Footprint to the same as Y2.

0.3

28 25 LAN DFB

Change Y5 Footprint to the same as Y2.

0.3

25 Realtek22 LAN

01/08 Chage part number from SA000026Q00 to SA000026Q10

31 Layout23 USB port

01/08 Swap D11, D12, L51 pin define per layout request.

22 HW21 SB

01/08 Change L61, L63, L66, L60, L67, L68, L69 to 0 ohm resistor.

Change C528, C543, C566, C504 to MLCC tpye.

Change C552 from 22uF to 4.7uF.

0.3

29 26 WWAN EMI

Add C738, C739, C740, C750, C751 as 39pF

30 33 EC HW

Connect AC_LED# to PQ3

31 35 M/B ME

Add screw hole.

32 36 DC-DC HW

Remove +1.2V and +3V circuit.

01/09

01/09

01/09

01/09

01/09

01/09

01/09

01/09

0.3

0.3

0.3

0.3

0.3

0.3

33 34 Switch board HW

Add R1065 and R1066 for OPP power button board01/10

0.3

34 33 Keyboard connector

01/10

DFB

Change Keyboard connector same as JBK00.

0.3

35 34 Lid switch connector

01/10

DFB

Change Lid switch connector type.

0.3

36 34 Switch board

01/10

EMI

Change R1048 and R1049 from 0 ohm to bead.

0.3

36 06 HDT debug port

01/14

AMD

Stuff R26, R28 and R41.

0.3

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

51 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

37 25 LAN

01/14

HW

Reserve Q1056, Q1057, C1077 and Q144. Change PJP605 to R1067.

0.3

8102E (10/100M 48 pin) can not support DSM function.

38 33 EC

01/14

HW

Reserve R544

0.3

8102E (10/100M 48 pin) can not support DSM function.

39 11 NB

01/15

HW

No support daul channel panel. Remove LVDS signal of Channel B.

0.3

40 17 LVDS

01/15

HW

Remove LVDS signal of Channel B (remove C1061~C1063)

0.3

No support daul channel panel.

41 15 Clock GEN.

01/15

HW

Chagne C1074~C1076 to 12pF

0.3

To slove noise issue.

42 15 Clock GEN.

01/15

Vendor

Clock Gen. spec. update Change R379 to 158 ohm and R380 to 90.9 ohm.

0.3

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

52 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

01 25 LAN

02/12

HW

Reserve D55.

0.4

For ESD protect.

HW

HW

HW

HW

3402

S/W board connector

02/12 Reserve R558.

0.4

To avoid cap. sensor board abnormal.

03 06 CPU

Reserve R59.

0.4

02/12

06 CPU

Change CPU SM BUS from EC2 to EC1.

0.4

02/15

04

Follow Trinity design.

Reserve C16.

06 CPU

02/15

06 CPU

02/15

05

06

Change R18 and R19 from 330 to 2.2K ohm.Follow Trinity design.

HW

0.4

0.4

07 CPU

02/15

07

Reserve C54.

HW 0.4

12 NB

02/15

08

Remove L96.

HW 0.4

12 NB

02/15

09

Change L12, L13 from bead to 0 ohm.

HW 0.4

13 NB

02/15

10

Change L16, L18, L19, L22 from bead to 0 ohm.

HW 0.4

13 NB

02/15

11

Remove L95.

HW 0.4

24 Multibay connector

02/15

12

Change JP10 Footprint.

ME 0.4

27 Card Reader

02/15

13

Change Card Reader LED active status. Reserve Q53 and R454, add R1070.

HW 0.4

27

02/15

14

Reserve R112 and add pull low resistor R1069.

HW 0.4

31 BT

02/15

15

Change JP32 Footprint and reverse pin define.

ME 0.4

31 BT

02/15

16

Saving Power consumption. Change BT power source from +3VALW to +3VS.

HW 0.4

33 EC

02/15

17

Remove JP34 and reserve R1068 for EC debug.

HW 0.4

33 EC

02/15

18

To solve can't power on when first plug in AC adapter. Change R1040 from 100K to 10K ohm and connect to +3VL_EC.

HW 0.4

Change Card Reader LED active status.

Card Reader

19 34 Debug SW

02/15 Remove SW2.

HW 0.4

20 34 TP LED

02/15 Add D19 for PR sku.

ME 0.4

21 11 NB

02/18 Change R371 from 10K to 300 ohm.

HW 0.4

22 11 NB

02/18 Add pull low resistor R1072.

HW 0.4

23 19 SB

02/18 Reserve C1085 and R303.

HW 0.4

24 21 SB

02/18 To solve can't power on when first plug in AC adapter. Add R1071 and D56 to connect to AC_IN.

HW 0.4

25 32 SPI BIOS

02/18 Remove U30, C489, R226, and R228. Stuff R221.

HW 0.4

26 34 WL/BT LED control

02/18 Modify circuit WLAN/WWAN/BT LED control.

HW 0.4

27 33 EC

02/18 Change R514 and R515 from 10K to 4.7K ohm.

HW 0.4

Follow Trinity design.

28 35 Screw hole

02/19

ME

Add H57.To slove TP on/off button feeling no good when press.

0.4

29 34

02/19

ENE

For ENE cap. board. Add LDO circuit (U65, R1073, C1097,C1099, J2).

0.4

S/W board connector

For ENE cap. board.

30 34

02/19

ENE

S/W board connector

Change R554 pin 1 power plan from +3VL to +3VL_CAP.

0.4

31

For cap. board.

34

S/W board connector

02/22

HW

Add C1098.

0.4

32 11

To splve CRT rising/falling fail issue.

NB

02/22

HW

Reserve R62, R63, R64.

0.4

33 16

CRT connector

02/22

HW

Change R211, R214 and R217 from 150 ohm to 75 ohm

0.4

To splve CRT rising/falling fail issue.

1634

Change C472, C476, C858 from 22pF to 6pF.

HW

02/22

CRT connector

0.4

To splve CRT rising/falling fail issue.

35 34

Lid switch connector

02/22

HW

To solve short issue for lid switch board. Move C1100 and C1101 from lid swtich board to M/B

0.4

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

53 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

0.4

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

R e v .

R e v .R e v .

R e v .P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

36 25

LAN

02/22

DFB

To solve kink pin to interfere with PCB. Update JRJ45 PCB Footprint.

37 35

Screw hole

02/22

DFB

Change H53 and H54 from non PTH to PTH hole.

38 34

02/22

EMI

Change R1048 and R1049 from bead to 0 ohm.

39 34

02/22

EMI

Reserve R1074/C1102 for ESB_CLK1 and R1075/C1103 for ESB_DAT1.

S/W board connector

S/W board connector

To solve EMI issue for ENE cap. board.

To solve EMI issue for ENE cap. board.

40 33

02/22

EMI

Add R1076, C1104 and R1077.

EC

To solve EMI issue for ENE cap. board.

41 33

EC

02/22

EMI

Add C1105.

42 36

DC/DC

02/25

EMI

Add C1110~C1117.

43 31

USB connector

EMI

Add C1109.

44 15

Clock GEN.

EMI

Add C1106.

For EMI request.

For EMI request.

For EMI request.

02/25

02/25

45 16

CRT Connector

EMI

Add C1107.02/25 For EMI request.

46 17

LCD Connector

02/25

EMI

For EMI request. Add C1108.

47 32

Debug connector

02/26

EMI

For EMI request. Add C1118.

48 17

WEBcam LDO

02/26

HW

To reduce power consumption in S3 mode. Add PJP6 to connect to +5VS. Stuff R1013 and reserve R1014.

49 34

Lid switch connector

02/26

HW

Connect JP40 pin 4 to +3VALW.

50 06

CPU

02/27

POWER

Change net name ENTRIP2 to EN0.

51 34

03/03

EMI

Change R558 to C1119 (0.1uF)

S/W board connector

For EMI request.

52 11

NB

03/03

EMI

Change C1120 (0.1uF)For EMI request.

53 31

USB connector

03/03

EMI

For EMI request. Change C1121 (0.1uF)

54 22

SB

03/03

HW

Change L60, L61, L63, L66, L67, L68, L69 from 0 ohm to bead.

55 13

NB

03/03

HW

Remove L20, L21 and use PJP604 to replace.

56 35

Docking connector

03/03

DFB

Change JDOCK connector Footprint.

57 11

NB

03/03

AMD

Add D58 and connect to INV_PWM.

59 33

EC

03/03

AMD

Change JDOCK connector Footprint.

To support VariBright feature.

58 11

NB

03/03

AMD

Change backlight inform signal (R70, R1072) from LVDS_BLON to LVDS_ENA_BL.To support VariBright feature.

To support VariBright feature.

60 06

CPU

03/04

AMD

Reserve R175, R814, C939, Q127 and Q129.

61 19

SB

03/04

AMD

Change net name from H_PWRGD to H_PWRGD_SB.

62 20

SB

03/05

EMI

Add SSC circuit (U66, R1080, R1081, R1082, R1083, C1122) for HDA_BITCLK.

To solve can not power on when use single core CPU.

For EMI request

64 21

SB

03/06

AMD

Change C520 and C521 from 0.01uF to 1000pF.For eSATA GEN1 fail issue.

65 31

eSATA connector

03/06

AMD

For eSATA GEN1 fail issue. Change C792 and C793 from 0.01uF to 1000pF.

63 21

SB

03/06

AMD

For eSATA GEN1 fail issue. Change C520 and C521 from 0.01uF to 1000pF.

66 17

LCDVCC circuit

03/06

HW

To solve LCD power up sequence fail. Change R225 from 470 ohm to 220 ohm.

67 15

Clock GEN.

03/06

HW

Add C1123.

68 20

SB

03/06

HW

Add D58 and connect to 3/5V_OK.

67 15

WWAN connector

03/06

HW

Add power on/off control circuit (Q167, R1087).

67 15

WWAN/WLAN

03/06

HW

Add D59 and D60.

To avoid CMOS data lose when shutdown suddenly.

To support wake on WWAN feature.

To avoid leakage power from SB.

For IDT CLOCK GEN.

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

54 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

0.4

0.4

0.4

0.4

0.4

0.4

R e v .

R e v .R e v .

R e v .

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

68 20

SB

03/06

HW

To solve can not power on if use CPU with single core Stuff R83.

69 11

NB

03/06

HW

Add R1085 and R1086.To support VariBright feature.

70 25

LAN

03/06

HW

Stuff Q144, R1056, R1057, C1077 and reserve R1067.To reduce power consumption in S3 mode.

71 33

LAN

03/06

HW

Stuff R544.To reduce power consumption in S3 mode.

72 18

HDMI

03/07

HW

To pass HDMI test.

Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

73 18

HDMI

03/07

HW

For EMI request.

Reserve 0 ohm and stuff common choke.

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

55 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

0.4

0.4

0.4

0.4

0.4

0.4

R e v .

R e v .R e v .

R e v .

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

68 20

SB

03/06

HW

To solve can not power on if use CPU with single core Stuff R83.

69 11

NB

03/06

HW

Add R1085 and R1086.To support VariBright feature.

70 25

LAN

03/06

HW

Stuff Q144, R1056, R1057, C1077 and reserve R1067.To reduce power consumption in S3 mode.

71 33

LAN

03/06

HW

Stuff R544.To reduce power consumption in S3 mode.

72 18

HDMI

03/07

HW

To pass HDMI test.

Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-4117P

1.C

HW Changed-List History-2

Custom

56 56Monday, March 16, 2009

2007/08/02 2008/08/02

Compal Electronics, Inc.

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

1.0

0.4

0.4

0.4

0.4

0.4

0.4

0.4

V ersion C h ange L ist

V ersion C h ange L istV ersion C h ange L ist

V ersion C h ange L ist ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it

0.4

0.4

0.4

0.4

0.4

R e v .

R e v .R e v .

R e v .

R e q

R e qR e q

R e q u e s t

u e s tu e s t

u e s t

O w n

O w nO w n

O w n e r

e re r

e r

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

I t e m

I t e mI t e m

I t e m I s s u e D

I s s u e DI s s u e D

I s s u e D e s c r ip t i o n

e s c r i p t i o ne s c r i p t i o n

e s c r i p t i o nD a t e

D a t eD a t e

D a t e

S o

S oS o

S o lu tio n D es c rip tio n

lu t io n D es c r ip t io nlu t io n D es cr ip t io n

lu t io n D es c r ip t io n

P a

P aP a

P a g e #

g e #g e #

g e #

T

TT

T i t le

it l eit l e

it l e

68 20

SB

03/06

HW

To solve can not power on if use CPU with single core Stuff R83.

69 11

NB

03/06

HW

Add R1085 and R1086.To support VariBright feature.

70 25

LAN

03/06

HW

Stuff Q144, R1056, R1057, C1077 and reserve R1067.To reduce power consumption in S3 mode.

71 33

LAN

03/06

HW

Stuff R544.To reduce power consumption in S3 mode.

72 18

HDMI

03/07

HW

To pass HDMI test.

Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

33

EC

73 HW

09/10

R589 R590 use 10k ohm pull high

Avoid DOCK_VOL_UP# and DOCK_VOL_down# folating

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