Compal LA 4117P Schematics. Www.s Manuals.com. R0.3 Schematics
User Manual: Compal LA-4117P - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 57
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
Cover Sheet
Custom
1 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
Schematics Document
REV:0.3
2009-03-15
Mobile AMD S1G3 CPU with ATI
RS880M(NB) & SB710(SB) core logic
Compal confidential
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
Block Diagram
Custom
2 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
Compal Confidential
Thermal Sensor
ADM1032ARMZ
Fan conn
AMD S1G3 CPU
638-PIN uFCPGA 638
Mini-Card*2
16X16
ATI RS880M
Power On/Off CKT.
LPC BUS
DC/DC Interface CKT.
Page 4, 5, 6, 7
Page 10, 11, 12, 13, 14
Page 8, 9
Page 19, 20, 21, 22, 23
Page 24
Page 24
SATA ODD Connector
Page 25
Page 19
RTC CKT.
ATI SB710
Power OK CKT.
Touch Pad CONN. Int.KBD
KBC
Realtek
8102E(10/100M)
RJ45/11 CONN
PCI-E BUS*5
BANK 0, 1, 2, 3
LED
DDR2-SO-DIMM X2
SATA HDD Connector
SATA Master-1
SATA Slave
A-Link Express II
4X PCI-E
Page 26
Page 26
Page 24
Multi-Bay HDD/ODD Option Connector
SATA Slave
SATA Master-2
Page 31
e-SATA Connector
Consumer AMD 14" UMA - Ripley 2.0 (NBW20)
Page 17
Express Card
Page 26
WLAN & WWAN
Page 28 Page 29
Page 31
Page 31
P41
Page 33
Page 33
Page 36
CRT
LVDS Panel
Interface
Page 16
Codec_IDT9271B7
Audio CKT AMP & Audio Jack
TPA6017A2
USB conn x2
USB2.0 X12
Azalia (HDA I/F)
BT Conn
Mini-Card WWAN
Page 6
Page 4
HDMI
Page 18
Clock Generator
SLG8SP626VTR
Page 15
72QFN
ENE KB926-C0
Page 34
P35
P35
Page 12
Side-Port DDR2 SDRAM
1024Mbits(64Mbx16)
DDR2 400MHz
Hyper Transport Link
Page 25
SPI ROM
MX25L1605
AM2C-12G
Page 32
Page 17
USB WebCam
Page 34
Consumer IR SPI
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*SPDIF
*Headphone/Line Out L/R
*Stereo Mic L/R
*Volume Control
*Consumer IR
*USB x1
*DC JACK
page 35
Module
FingerPrinter AES1610
USBx1
Module
New Module
Page 35
DDR2 800MHz 1.8V
Dual Channel
Page 34
MDC V1.5 daughter board
Accelerometer
ST LIS302DLTR
Page 30
Page 27
CardReader
JMicron
JMB385-LGEZ0A
daughter board
Page 31
USB conn x1
Page 27
CardReader Socket
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
Notes List
Custom
3 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
Voltage Rails
O MEANS ON X MEANS OFF
O
O
X
+0.9V
S3
+3VS
X
X
+3VALW
+5VS
S1
O
+2.5VS
+CPU_CORE
OO
OO
X
X X
+VCCP
power
plane
O
O
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.8V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
O
O
Symbol Note :
: means Digital Ground
: means Analog Ground
SERIAL SENSOR
SMB_EC_CK2
SOURCE
KB926
INVERTER BATT EEPROM
THERMAL
SODIMM CLK CHIP
SMBUS Control Table
MINI CARD
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
KB926
LCD
ADM1032
X
X X X
X
X X
X
X
X X
X
V V
V
1 0 1 0 0 1 0 0A 4
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2
A 0
CL OCK GENERATOR (EXT.)
HEX
DDR SO-D IMM 1
ADDRESS
DDR SO-D IMM 0
1 1 0 1 0 0 1 0
DEVICE
+VGA_CORE
+1.8VS
+0.9VGA
+1.2VS
HEX
98H
HEX
16H
EC SM Bus1 address
Device
A0H
1010 000X b
Address Address
EC SM Bus2 address
Device
1001 100X b0001 011X b
Smart Battery
24C16
CPU
9AH
1001 101X b
ADI1032-2 CPU
L
Layout Notes
Slot 2I / II
CPU &
V
I2C_CLK
I2C_DATA
RS780M
X X X X X X X
V V
SCL0
SDA0 SB700
X X X X X
HDMI
X
X
X
DDC_CLK0
DDC_DATA0 RS780M
X X X X X
DDC_CLK1
DDC_DATA1 RS780M
X X X X X
X X X V
X X X X
XX
XX XX
SDA3
X
SB700
SCL3
XX
XX XX
SDA1 SB700
SCL1
XXX X V
X X
XX XX
SDA2
X
SB700
SCL2
XXX X
Please see VGA@ as no install. No support RX780M.
G-Sensor
X
X
X
X
X
X
V
X
X
: Question Area Mark.(Wait check)
"*" as default BOM setting
*PA@ : means install when Ripley PA.
PR@ : means install when Ripley PR.
RM@ : means install when Rachman.
*RP@ : means install when Ripley.
SIDE@ : means install when SidePort support.
@ : means just reserve , no build
45@ : Install when 45 level Assy
VCPU
ADM1032
DAZ=DAZ03Y00201 DAZ=DAZ03Y00101
SB700
RS780
PCB for 1.0/1.0a
R3 NB and SB: RS780R3@,SBR3@
R1 NB and SB: RS780R1@,SBR1@
DAZ=DAZ03Y00203 DAZ=DAZ03Y00102
PCB for 1.1
For Riply PA-> PA@/RP@/RPZ@
For Rachman UMA-> RM@/PRM@/RMZ@
For Riply PA-> PA@, RP@
For Riply PR-> PR@, RP@, PRM@
For Rachman UMA-> RM@, PRM@
1.0/1.0a
2.0
RP11@,RM11@:For 1.A PCB
RP10@,RM10@:For 1.0 PCB.
For Riply PA-> PA@, RP@,RPZ@
For Riply PR-> PR@, RP@, PRM@,RPZ@
For Rachman UMA-> RM@, PRM@,RMZ@
1.1
DAZ=DAZ09100102DAZ=DAZ09000102
PCB for 2.0
Z Z Z
PCB-Ripley MB
RP10@
Z Z Z
PCB-Rachman UMA MB
RM11@
Z Z Z
PCB-Rachman UMA MB
RM@
Z Z Z
PCB-Ripley MB
RP@
Z Z Z
PCB-Ripley MB
RP11@
U15
SB700 R1
SBR1@
U3
RS780 R1
RS780R1@
X76
X76
Z Z Z
PCB-Rachman UMA MB
RM10@
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN1
H_CADIN0
H_CADIP3
H_CADIN2
H_CADIP2
H_CADIP1
H_CADIN3
H_CADIP4
H_CADIN5
H_CADIN4
H_CADIP5
H_CADIN6
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP6
H_CADIP7
H_CADIN10
H_CADIP10
H_CADIN11
H_CADIP11
H_CADIP9
H_CADIN13
H_CADIN12
H_CADIP14
H_CADIP12
H_CADIN14
H_CADIP0
H_CADIN15
H_CADIP15
H_CADIP13
H_CADON15
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
+VCC_FAN
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
+VLDT_B
H_CADON[0..15] <10>H_CADIN[0..15]<10>
H_CADOP[0..15] <10>
H_CLKIN0<10>
H_CLKIN1<10>
H_CLKIP1<10>
H_CTLIN1<10>
H_CLKIP0<10>
H_CTLIP1<10> H_CTLOP1 <10>
H_CLKOP1 <10>
H_CADIP[0..15]<10>
H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKON1 <10>
H_CTLON1 <10>
H_CTLOP0 <10>
H_CTLON0 <10>H_CTLIN0<10>
H_CTLIP0<10>
FAN_PWM<33>
+1.2V_HT
+1.2V_HT
+5VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
AMD CPU S1G2 HT I/F
Custom
4 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
250 mil
VLDT=500mA
PWM Fan Control circuit
Athlon 64 S1
Processor Socket
Near CPU Socket
VLDT CAP.
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
side.
9/20 S P07000DM00/SP07000EQ00
C1
4.7U_0805_10V4Z
1
2
HT LINK
JCPUA
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VLDT_A3
D4 VLDT_A2
D3 VLDT_A1
D2 VLDT_A0
D1
VLDT_B3 AE5
VLDT_B2 AE4
VLDT_B1 AE3
VLDT_B0 AE2
L0_CADIN_H15
N5
L0_CADIN_L15
P5
L0_CADIN_H14
M3
L0_CADIN_L14
M4
L0_CADIN_H13
L5
L0_CADIN_L13
M5
L0_CADIN_H12
K3
L0_CADIN_L12
K4
L0_CADIN_H11
H3
L0_CADIN_L11
H4
L0_CADIN_H10
G5
L0_CADIN_L10
H5
L0_CADIN_H9
F3
L0_CADIN_L9
F4
L0_CADIN_H8
E5
L0_CADIN_L8
F5
L0_CADIN_H7
N3
L0_CADIN_L7
N2
L0_CADIN_H6
L1
L0_CADIN_L6
M1
L0_CADIN_H5
L3
L0_CADIN_L5
L2
L0_CADIN_H4
J1
L0_CADIN_L4
K1
L0_CADIN_H3
G1
L0_CADIN_L3
H1
L0_CADIN_H2
G3
L0_CADIN_L2
G2
L0_CADIN_H1
E1
L0_CADIN_L1
F1
L0_CADIN_H0
E3
L0_CADIN_L0
E2
L0_CADOUT_H15 T4
L0_CADOUT_L15 T3
L0_CADOUT_H14 V5
L0_CADOUT_L14 U5
L0_CADOUT_H13 V4
L0_CADOUT_L13 V3
L0_CADOUT_H12 Y5
L0_CADOUT_L12 W5
L0_CADOUT_H11 AB5
L0_CADOUT_L11 AA5
L0_CADOUT_H10 AB4
L0_CADOUT_L10 AB3
L0_CADOUT_H9 AD5
L0_CADOUT_L9 AC5
L0_CADOUT_H8 AD4
L0_CADOUT_L8 AD3
L0_CADOUT_H7 T1
L0_CADOUT_L7 R1
L0_CADOUT_H6 U2
L0_CADOUT_L6 U3
L0_CADOUT_H5 V1
L0_CADOUT_L5 U1
L0_CADOUT_H4 W2
L0_CADOUT_L4 W3
L0_CADOUT_H3 AA2
L0_CADOUT_L3 AA3
L0_CADOUT_H2 AB1
L0_CADOUT_L2 AA1
L0_CADOUT_H1 AC2
L0_CADOUT_L1 AC3
L0_CADOUT_H0 AD1
L0_CADOUT_L0 AC1
L0_CLKIN_H1
J5
L0_CLKIN_L1
K5
L0_CLKIN_H0
J3
L0_CLKIN_L0
J2
L0_CTLIN_H1
P3
L0_CTLIN_L1
P4
L0_CTLIN_H0
N1
L0_CTLIN_L0
P1
L0_CLKOUT_H1 Y4
L0_CLKOUT_L1 Y3
L0_CLKOUT_H0 Y1
L0_CLKOUT_L0 W1
L0_CTLOUT_H1 T5
L0_CTLOUT_L1 R5
L0_CTLOUT_H0 R2
L0_CTLOUT_L0 R3
JP2
ACES_88231-02001
CONN@
1
1
2
2
GND
3
GND
4
D1
CH751H-40PT_SOD323-2
2 1
C7 4.7U_0805_10V4Z
1 2
S
G
D
Q1
SI3456BDV-T1-E3_TSOP6
3
6
2
4 5
1
C9
0.1U_0402_16V4Z
1
2
C8
4.7U_0805_10V4Z
1
2
C3
0.22U_0603_16V4Z
1
2
C2
4.7U_0805_10V4Z
1
2
C5
180P_0402_50V8J
1
2
D2
RLZ5.1B_LL34
@
12
C6
180P_0402_50V8J
1
2
C4
0.22U_0603_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+MCH_REF
DDR_B_MA10
DDR_B_MA7
DDR_B_MA1
DDR_B_MA12
DDR_B_MA6
DDR_B_MA11
DDR_B_MA0
DDR_B_MA9
DDR_B_MA15
DDR_B_MA3
DDR_B_MA5
DDR_B_MA8
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_CKE1_DIMMB
DDR_B_D0
DDR_CKE0_DIMMB
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS3
DDR_B_DQS#3
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS7
VTT_SENSE
DDR_A_CLK0
DDR_A_CLK#0
+MCH_REF
DDR_B_ODT0
DDR_B_ODT1
DDR_A_ODT1
DDR_A_ODT0
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CLK#1DDR_A_CLK#1
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_B_D28
DDR_B_D16
DDR_B_D22
DDR_B_D19
DDR_B_D9
DDR_B_D50
DDR_B_D35
DDR_B_D46
DDR_B_D5
DDR_B_D37
DDR_B_D26
DDR_B_D3
DDR_B_D8
DDR_B_D29
DDR_B_D14
DDR_B_D7
DDR_B_D59
DDR_B_D51
DDR_B_D10
DDR_B_D17
DDR_B_D44
DDR_B_D41
DDR_B_D38
DDR_B_D47
DDR_B_D63
DDR_B_D32
DDR_B_D20
DDR_B_D52
DDR_B_D30
DDR_B_D53
DDR_B_D40
DDR_B_D27
DDR_B_D45
DDR_B_D55
DDR_B_D56
DDR_B_D11
DDR_B_D48
DDR_B_D39
DDR_B_D1
DDR_B_D42
DDR_B_D36
DDR_B_D2
DDR_B_D58
DDR_B_D33
DDR_B_D62
DDR_B_D31
DDR_B_D21
DDR_B_D54
DDR_B_D24
DDR_B_D15
DDR_B_D60
DDR_B_D12
DDR_B_D49
DDR_B_D43
DDR_B_D18
DDR_B_D61
DDR_B_D34
DDR_B_D4
DDR_B_DM6
DDR_B_DM4
DDR_B_DM2
DDR_B_DM0
DDR_B_DM5
DDR_B_DM3
DDR_B_DM1
DDR_B_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
DDR_A_DM7
DDR_A_D59
DDR_A_D3
DDR_A_D13
DDR_A_D60
DDR_A_D40
DDR_A_D29
DDR_A_D56
DDR_A_D20
DDR_A_D28
DDR_A_D36
DDR_A_D19
DDR_A_D23
DDR_A_D34
DDR_A_D61
DDR_A_D15
DDR_A_D4
DDR_A_D0
DDR_A_D53
DDR_A_D47
DDR_A_D43
DDR_A_D33
DDR_A_D24
DDR_A_D39
DDR_A_D46
DDR_A_D22
DDR_A_D51
DDR_A_D9
DDR_A_D5
DDR_A_D6
DDR_A_D54
DDR_A_D8
DDR_A_D31
DDR_A_D7
DDR_A_D50
DDR_A_D57
DDR_A_D12
DDR_A_D21
DDR_A_D26
DDR_A_D63
DDR_A_D62
DDR_A_D42
DDR_A_D48
DDR_A_D44
DDR_A_D25
DDR_A_D58
DDR_A_D32
DDR_A_D1
DDR_A_D17
DDR_A_D2
DDR_A_D55
DDR_A_D38
DDR_A_D11
DDR_A_D10
DDR_A_D27
DDR_A_D18
DDR_A_D14
DDR_A_D41
DDR_A_D49
DDR_A_D16
DDR_A_D52
DDR_A_D37
DDR_A_D35
DDR_A_D30
DDR_B_D6
DDR_A_D45
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_A_WE#
DDR_B_D25
DDR_A_CAS#
DDR_A_RAS#
DDR_B_D23
DDR_B_D57
DDR_B_D13
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_MA15
DDR_A_MA12
DDR_A_MA14
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_MA6
DDR_A_MA1
DDR_A_MA7
DDR_A_MA2
DDR_A_MA3
DDR_A_MA8
DDR_A_MA5
DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_B_MA14
DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMA#
DDR_CKE1_DIMMB <9>
DDR_CKE0_DIMMB <9>
DDR_CS0_DIMMA#<8>
DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>
DDR_CS1_DIMMB# <9>
DDR_B_D[63..0]<9>
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_A_D[63..0] <8>
DDR_B_DQS7<9>
DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS5<9>
DDR_B_DQS4<9>
DDR_B_DQS3<9>
DDR_B_DQS2<9>
DDR_B_DQS1<9>
DDR_B_DQS0<9>
DDR_B_DQS#6<9>
DDR_B_DQS#5<9>
DDR_B_DQS#4<9>
DDR_B_DQS#3<9>
DDR_B_DQS#2<9>
DDR_B_DQS#1<9>
DDR_B_DQS#0<9>
DDR_A_DQS3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>
DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>
DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>
DDR_A_BS#0<8>
DDR_A_BS#1<8>
DDR_A_BS#2<8>
DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>
DDR_B_ODT0 <9>
DDR_B_ODT1 <9>
DDR_A_ODT0<8>
DDR_A_ODT1<8>
DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
DDR_A_CLK0<8>
DDR_A_CLK#0<8>
DDR_A_CLK1<8>
DDR_A_CLK#1<8>
DDR_CKE0_DIMMA<8>
DDR_CKE1_DIMMA<8>
+1.8V
+0.9V+0.9V
+1.8V
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
AMD CPU S1G2 DDRII I/F
Custom
5 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
Athlon 64 S1
Processor
Socket
Athlon 64 S1
Processor Socket
Place them close to CPU within 1"
Processor DDR2 Memory Interface
T1PAD
C11
1.5P_0402_50V9C
1
2
R2
1K_0402_1%
1 2
C12
0.1U_0402_16V4Z
1
2
T3PAD
R1
1K_0402_1%
1 2
T2 PAD
R4 39.2_0402_1%
1 2
MEM:DATA
JC PUC
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
MB_DATA63
AD11 MB_DATA62
AF11 MB_DATA61
AF14 MB_DATA60
AE14 MB_DATA59
Y11 MB_DATA58
AB11 MB_DATA57
AC12 MB_DATA56
AF13 MB_DATA55
AF15 MB_DATA54
AF16 MB_DATA53
AC18 MB_DATA52
AF19 MB_DATA51
AD14 MB_DATA50
AC14 MB_DATA49
AE18 MB_DATA48
AD18 MB_DATA47
AD20 MB_DATA46
AC20 MB_DATA45
AF23 MB_DATA44
AF24 MB_DATA43
AF20 MB_DATA42
AE20 MB_DATA41
AD22 MB_DATA40
AC22 MB_DATA39
AE25 MB_DATA38
AD26 MB_DATA37
AA25 MB_DATA36
AA26 MB_DATA35
AE24 MB_DATA34
AD24 MB_DATA33
AA23 MB_DATA32
AA24 MB_DATA31
G24 MB_DATA30
G23 MB_DATA29
D26 MB_DATA28
C26 MB_DATA27
G26 MB_DATA26
G25 MB_DATA25
E24 MB_DATA24
E23 MB_DATA23
C24 MB_DATA22
B24 MB_DATA21
C20 MB_DATA20
B20 MB_DATA19
C25 MB_DATA18
D24 MB_DATA17
A21 MB_DATA16
D20 MB_DATA15
D18 MB_DATA14
C18 MB_DATA13
D14 MB_DATA12
C14 MB_DATA11
A20 MB_DATA10
A19 MB_DATA9
A16 MB_DATA8
A15 MB_DATA7
A13 MB_DATA6
D12 MB_DATA5
E11 MB_DATA4
G11 MB_DATA3
B14 MB_DATA2
A14 MB_DATA1
A11 MB_DATA0
C11
MA_DATA63 AA12
MA_DATA62 AB12
MA_DATA61 AA14
MA_DATA60 AB14
MA_DATA59 W11
MA_DATA58 Y12
MA_DATA57 AD13
MA_DATA56 AB13
MA_DATA55 AD15
MA_DATA54 AB15
MA_DATA53 AB17
MA_DATA52 Y17
MA_DATA51 Y14
MA_DATA50 W14
MA_DATA49 W16
MA_DATA48 AD17
MA_DATA47 Y18
MA_DATA46 AD19
MA_DATA45 AD21
MA_DATA44 AB21
MA_DATA43 AB18
MA_DATA42 AA18
MA_DATA41 AA20
MA_DATA40 Y20
MA_DATA39 AA22
MA_DATA38 Y22
MA_DATA37 W21
MA_DATA36 W22
MA_DATA35 AA21
MA_DATA34 AB22
MA_DATA33 AB24
MA_DATA32 Y24
MA_DATA31 H22
MA_DATA30 H20
MA_DATA29 E22
MA_DATA28 E21
MA_DATA27 J19
MA_DATA26 H24
MA_DATA25 F22
MA_DATA24 F20
MA_DATA23 C23
MA_DATA22 B22
MA_DATA21 F18
MA_DATA20 E18
MA_DATA19 E20
MA_DATA18 D22
MA_DATA17 C19
MA_DATA16 G18
MA_DATA15 G17
MA_DATA14 C17
MA_DATA13 F14
MA_DATA12 E14
MA_DATA11 H17
MA_DATA10 E17
MA_DATA9 E15
MA_DATA8 H15
MA_DATA7 E13
MA_DATA6 C13
MA_DATA5 H12
MA_DATA4 H11
MA_DATA3 G14
MA_DATA2 H14
MA_DATA1 F12
MA_DATA0 G12
MB_DM7
AD12 MB_DM6
AC16 MB_DM5
AE22 MB_DM4
AB26 MB_DM3
E25 MB_DM2
A22 MB_DM1
B16 MB_DM0
A12
MB_DQS_H7
AF12
MB_DQS_L7
AE12
MB_DQS_H6
AE16
MB_DQS_L6
AD16
MB_DQS_H5
AF21
MB_DQS_L5
AF22
MB_DQS_H4
AC25
MB_DQS_L4
AC26
MB_DQS_H3
F26
MB_DQS_L3
E26
MB_DQS_H2
A24
MB_DQS_L2
A23
MB_DQS_H1
D16
MB_DQS_L1
C16
MB_DQS_H0
C12
MB_DQS_L0
B12
MA_DM7 Y13
MA_DM6 AB16
MA_DM5 Y19
MA_DM4 AC24
MA_DM3 F24
MA_DM2 E19
MA_DM1 C15
MA_DM0 E12
MA_DQS_H7 W12
MA_DQS_L7 W13
MA_DQS_H6 Y15
MA_DQS_L6 W15
MA_DQS_H5 AB19
MA_DQS_L5 AB20
MA_DQS_H4 AD23
MA_DQS_L4 AC23
MA_DQS_H3 G22
MA_DQS_L3 G21
MA_DQS_H2 C22
MA_DQS_L2 C21
MA_DQS_H1 G16
MA_DQS_L1 G15
MA_DQS_H0 G13
MA_DQS_L0 H13
R3 39.2_0402_1%
1 2
MEM:CMD/CTRL/CLK
JCPUB
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VTT1
D10
VTT2
C10
VTT3
B10
VTT4
AD10
VTT5 W10
VTT6 AC10
VTT7 AB10
VTT8 AA10
VTT9 A10
MA1_ODT1
V19 MA1_ODT0
U21 MA0_ODT1
V22 MA0_ODT0
T19
MB1_ODT0 Y26
MB0_ODT1 W23
MB0_ODT0 W26
RSVD_M2 B18
MB1_CS_L0 U22
MB0_CS_L1 W25
MB0_CS_L0 V26
MA0_CS_L1
U19
MA1_CS_L1
V20 MA1_CS_L0
U20
MA0_CS_L0
T20
MA_ADD15
K19 MA_ADD14
K24 MA_ADD13
V24 MA_ADD12
K20 MA_ADD11
L22 MA_ADD10
R21 MA_ADD9
K22 MA_ADD8
L19 MA_ADD7
L21 MA_ADD6
M24 MA_ADD5
L20 MA_ADD4
M22 MA_ADD3
M19 MA_ADD2
N22 MA_ADD1
M20 MA_ADD0
N21
MA_BANK2
J21 MA_BANK1
R23 MA_BANK0
R20
MA_RAS_L
R19
MA_CAS_L
T22
MA_WE_L
T24
MEMZP
AF10
MEMZN
AE10 VTT_SENSE Y10
MEMVREF W17
MA_CLK_H4
P19
MA_CLK_L4
P20
MA_CLK_H7
Y16
MA_CLK_L7
AA16
MA_CLK_H1
E16
MA_CLK_L1
F16
MA_CLK_H5
N19
MA_CLK_L5
N20
MB_CLK_H4 R26
MB_CLK_L4 R25
MB_CLK_H7 AF18
MB_CLK_L7 AF17
MB_CLK_H1 A17
MB_CLK_L1 A18
MB_CLK_H5 P22
MB_CLK_L5 R22
MA_CKE0
J22
MA_CKE1
J20 MB_CKE0 J25
MB_CKE1 H26
MB_ADD15 J24
MB_ADD14 J23
MB_ADD13 W24
MB_ADD12 L25
MB_ADD11 L26
MB_ADD10 T26
MB_ADD9 K26
MB_ADD8 M26
MB_ADD7 L24
MB_ADD6 N25
MB_ADD5 L23
MB_ADD4 N26
MB_ADD3 N23
MB_ADD2 P26
MB_ADD1 N24
MB_ADD0 P24
MB_BANK2 J26
MB_BANK1 U26
MB_BANK0 R24
MB_RAS_L U25
MB_CAS_L U24
MB_WE_L U23
RSVD_M1
H16
C13
1000P_0402_25V8J
1
2
C15
1.5P_0402_50V9C
1
2
C10
1.5P_0402_50V9C
1
2
C14
1.5P_0402_50V9C
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
THERMDA_CPU
THERMDC_CPU
CPU_DBRDY
CPU_TDO
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TRST#
CPU_DBREQ#
HDT_RST#
LDT_RST#
CPU_VDD1_FB_H
CPU_THERMTRIP#_R
VDD_NB_FB_H
CPU_VDD0_FB_L
VDD_NB_FB_LCPU_VDD1_FB_L
VDD_NB_FB_H
VDD_NB_FB_L
CPU_HTREF0
CPU_HTREF1
CPU_TEST25_L_BYPASSCLK_L
CPU_DBRDY
CPU_TMS
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST19_PLLTEST0
CPU_CLKIN_SC_P
CPU_THERMTRIP#_R
LDT_RST#
H_PW RGD_CPU
LDT_STOP#
THERMDA_CPU
LDT_STOP#
THERMDC_CPU
CPU_SID
CPU_SIC
CPU_LDT_REQ#
CPU_CLKIN_SC_N
CPU_VDD0_FB_H
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_DBREQ#
CPU_TDO
CPU_SVC
CPU_SVD
CPU_TEST12_SCANSHIFTENB
CPU_TEST20_SCANCLK2
CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST14_BP0
CPU_TEST15_BP1
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST28_H_PLLCHRZ_P
H_PW RGD_CPU
LDT_RST#
CPU_TEST23_TSTUPD
CPU_MEMHOT#_1.8V
CPU_LDT_REQ#
CPU_TEST27_SINGLECHAIN
CPU_PROCHOT#_1.8
CPU_TEST18_PLLTEST1
C PU _ PR O C HOT# _1. 8
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CPU_VDD1_FB_H
CPU_VDD1_FB_L
CPU_TEST21_SCANEN
CPU_TEST27_SINGLECHAIN
CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST15_BP1
CPU_TEST20_SCANCLK2
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST24_SCANCLK1
CPU_TEST14_BP0
CPU_SVD
CPU_SVC
SMB_EC_CK1
SMB_EC_DA1CPU_SID
CPU_SIC
SB_PWRGD <20,33,43>
CPU_SVD <43>
CPU_SVC <43>
H_PW RGD_CPU<19>
LDT_RST#<19>
LDT_STOP#<11,19>
VDD_NB_FB_H <43>
VDD_NB_FB_L <43>
CPU_VDD0_FB_H<43>
CPU_VDD0_FB_L<43>
CLK_CPU_BCLK<15>
CLK_CPU_BCLK#<15>
CPU_LDT_REQ# <11,19>
H_THERMTRIP# <20>
EN0 <37,39>
H_PROCHOT# <19>
H_THERMTRIP#_EC <33>
SMB_EC_CK2 <33>
SMB_EC_DA2 <33>
SMB_EC_CK1 <32,33,34,37>
SMB_EC_DA1 <32,33,34,37>
+3VS
+1.8V
+3VS
+1.8V
+1.2V_HT
+2.5VDDA
+2.5VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+CPU_CORE_NB
+1.8V
+1.8V
+CPU_CORE_0
+CPU_CORE_0
+1.8V
+1.8V
+3VS
+1.8V
+1.8V
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
AMD CPU S1G2 CTRL
Custom
6 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
2200p change to
100p
Address:100_1101
HDT Connector
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
Address:100_1100
+1.8V sense no support
0718 AMD , need check with AMD
0718 Silego -- 216 ohm
Place close to CPU wihtin 1.5"
VDDA=300mA
as short as possible
route as differential
testpoint under package
Close to CPU
Close to CPU
9/20 S P020016900
0718 AMD --> 1K ohm
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
EC is PU to 5VALW
2.09V for Gate
02/12 Remove R59.
02/15 Follow Trinity design.
02/15 Change R18 and R19
from 390 to 2.2K ohm.
02/27 Change net name to EN0.
03/04 Reserve R175, R814, C939, Q127 and Q129.
Reserve the R488 and R489 for S1G3 CPU
R484 10_0402_5%
1 2
R175
20K_0402_5%
@
12
T11 PAD
R38220_0402_5%@
12
R5 300_0402_5%
1 2
+
C16
100U_D2_10VM
@
1
2
T10PAD
C174.7U_0805_10V4Z
1
2
R13 44.2_0402_1%
1 2
R22 1K_0402_5%
1 2
G
D
S
Q129
FDV301N_NL_SOT23-3
@
2
13
C20
3900P_0402_50V7K
1 2
C19
0.22U_0603_16V4Z
1
2
R33 300_0402_5%@
12
C
B
E
Q3
PMBT3904_SOT23
1
2
3
R40220_0402_5%@
12
R11 10K_0402_5%@
12
C23
0.1U_0402_16V7K
1
2
R8
169_0402_1%
12
L1
FBM_L11_201209_300L_0805
1 2
SAMTEC_ASP-68200-07
JP3
CONN@
2
4
6
8
10
12
14
16
18
20
22
2423
21
19
17
15
13
11
9
7
5
3
1
26
R14 44.2_0402_1%
1 2
R23 1K_0402_5%
1 2
R6 0_0402_5%@
1 2
R486 10_0402_5%
1 2
R16 0_0402_5%
1 2
T5PAD
E
B
C
Q2
MMBT3904_NL_SOT23-3@
2
3 1
R7 0_0402_5%
1 2
C18
3300P_0402_50V7K
1
2
U2
ADM1032ARMZ-2REEL_MSOP8
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
R814
34.8K_0402_1%~N
@
12
R29 300_0402_5%@
12
R36
300_0402_5%
1 2
T12PAD
C27
100P_0402_25V8K
C22
0.01U_0402_25V4Z
@
1
2
U1
NC7SZ08P5X_NL_SC70-5@
B2
A1
Y
4
P5
G
3
R9 300_0402_5%
1 2
C24
0.01U_0402_25V4Z
@
1
2
C939 0.1U_0402_16V4Z
@
1 2
R25 0_0402_5%
1 2
R28 300_0402_5%
12
R489 10_0402_5%@
1 2
R488 10_0402_5% @
1 2
R27 300_0402_5%@
12
C21 3900P_0402_50V7K
1 2
T6PAD
T42PAD
G
D
S
Q127
FDV301N_NL_SOT23-3
@
2
13
R59 0_0402_5%@
1 2
R19
2.2K_0402_5%
12
T7PAD
R31 300_0402_5%@
12
JC PUD
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VDDA1
F8
VDDA2
F9
RESET_L
B7
PWROK
A7
LDTSTOP_L
F10
SIC
AF4
SID
AF5
HT_REF1
P6 HT_REF0
R6
VDD0_FB_H
F6
VDD0_FB_L
E6 VDDIO_FB_H W9
VDDIO_FB_L Y9
THERMTRIP_L AF6
PROCHOT_L AC7
RSVD2
A5
LDTREQ_L
C6
SVC A6
SVD A4
RSVD6 C5
RSVD4
B5
RSVD1
A3
CLKIN_H
A9
CLKIN_L
A8
DBRDY
G10
TMS
AA9
TCK
AC9
TRST_L
AD9
TDI
AF9
DBREQ_L E10
TDO AE9
TEST25_H
E9
TEST25_L
E8
TEST19
G9 TEST18
H10
RSVD8 AA7
TEST9
C2
TEST17 D7
TEST16 E7
TEST15 F7
TEST14 C7
TEST12
AC8
TEST7 C3
TEST6
AA6
THERMDC W7
THERMDA W8
VDD1_FB_H
Y6
VDD1_FB_L
AB6
TEST29_H C9
TEST29_L C8
TEST24
AE7
TEST23
AD7
TEST22
AE8
TEST21
AB8
TEST20
AF7
TEST28_H J7
TEST28_L H8
TEST27
AF8
ALERT_L
AE6
TEST10 K8
TEST8 C4
RSVD3
B3
RSVD5
C1
VDDNB_FB_H H6
VDDNB_FB_L G6
RSVD7 D5
KEY2 W18
MEMHOT_L AA8
RSVD10 H18
RSVD9 H19
KEY1 M11
R24 300_0402_5%@
1 2
R30
300_0402_5%
1 2
T13PAD
T4 PAD
R39220_0402_5%@
12
R37220_0402_5%@
12
R15
300_0402_5%
1 2
T9 PAD
C25
0.01U_0402_25V4Z
@
1
2
R10 10K_0402_5%
1 2
R485 10_0402_5%
1 2
R17
300_0402_5%@
12
T14PAD
R32 300_0402_5%@
12
R487 10_0402_5%
1 2
R35 300_0402_5%@
12
R18
2.2K_0402_5%
12
T43PAD
R26 300_0402_5%
1 2
T8PAD
R34 300_0402_5%@
12
R21
300_0402_5%
1 2
R41300_0402_5%
12
C26
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+0.9V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+1.8V
+1.8V
+1.8V
+1.8V +1.8V
+0.9V
+0.9V
+CPU_CORE_NB
+1.8V
+1.8V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_NB
+CPU_CORE_0+CPU_CORE_0
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
AMD CPU S1G2 PWR & GND
Custom
7 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI
Between CPU Socket and DIMM
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
Under CPU Socket
Athlon 64 S1
Processor Socket
Near CPU Socket
VTT decoupling.
VDD(+CPU_CORE) decoupling.
VDDIO decoupling.
+CPU_CORE_NB decoupling.
C: Change to NBO CAP
C: Change to NBO CAP
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
Athlon 64 S1
Processor Socket
L
18A/720mil/36vias
L
4A/160mil/8vias
L
3A/120mil/6vias
Tigris platform will be 4A
01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0
01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0
C40
0.22U_0603_16V4Z
1
2
+
C29
330U_X_2VM_R6M
1
2
C33
22U_0805_6.3V6M
1
2
C65
180P_0402_50V8J
1
2
C73
180P_0402_50V8J
1
2
C75
4.7U_0805_10V4Z
1
2
C85
180P_0402_50V8J
1
2
C32
22U_0805_6.3V6M
1
2
C43
0.22U_0603_16V4Z
1
2
C45
180P_0402_50V8J
1
2
C54
22U_0805_6.3V6M
@
1
2
C71
1000P_0402_25V8J
1
2
C46
22U_0805_6.3V6M
1
2
C44
0.01U_0402_25V4Z
1
2
+
C28
330U_X_2VM_R6M
1
2
C47
22U_0805_6.3V6M
1
2
C69
0.22U_0603_16V4Z
1
2
C56
0.22U_0603_16V4Z
1
2
C55
0.22U_0603_16V4Z
1
2
C48
0.22U_0603_16V4Z
1
2
C36
22U_0805_6.3V6M
1
2
C79
4.7U_0805_10V4Z
1
2
C52
22U_0805_6.3V6M
1
2
C41
0.01U_0402_25V4Z
1
2
C61
0.01U_0402_25V4Z
1
2
C86
180P_0402_50V8J
1
2
C58
0.22U_0603_16V4Z
1
2
C63
180P_0402_50V8J
1
2
JCPUE
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VDD1_25 AC4
VDD1_26 AD2
VDD0_1
G4
VDD0_2
H2
VDD0_3
J9
VDD0_4
J11
VDD0_5
J13
VDD0_7
K6
VDD0_8
K10
VDD0_9
K12
VDD0_10
K14
VDD0_11
L4
VDD0_12
L7
VDD0_13
L9
VDD0_14
L11
VDD0_15
L13
VDD0_17
M2
VDD0_18
M6
VDD0_19
M8
VDD0_20
M10
VDD0_21
N7
VDD0_22
N9
VDD0_23
N11
VDD1_1 P8
VDD1_2 P10
VDD1_3 R4
VDD1_4 R7
VDD1_5 R9
VDD1_6 R11
VDD1_7 T2
VDD1_8 T6
VDD1_9 T8
VDD1_10 T10
VDD1_11 T12
VDD1_12 T14
VDD1_13 U7
VDD1_14 U9
VDD1_15 U11
VDD1_16 U13
VDD1_18 V6
VDD1_19 V8
VDD1_20 V10
VDD1_21 V12
VDD1_22 V14
VDD1_23 W4
VDD1_24 Y2
VDD0_6
J15
VDDNB_1
K16
VDD0_16
L15
VDDNB_2
M16
VDDNB_3
P16
VDDNB_4
T16
VDD1_17 U15
VDDNB_5
V16
VDDIO1
H25
VDDIO2
J17
VDDIO3
K18
VDDIO4
K21
VDDIO5
K23
VDDIO6
K25
VDDIO7
L17
VDDIO8
M18
VDDIO9
M21
VDDIO10
M23
VDDIO11
M25
VDDIO12
N17 VDDIO13 P18
VDDIO14 P21
VDDIO15 P23
VDDIO16 P25
VDDIO17 R17
VDDIO18 T18
VDDIO19 T21
VDDIO20 T23
VDDIO21 T25
VDDIO22 U17
VDDIO23 V18
VDDIO24 V21
VDDIO25 V23
VDDIO26 V25
VDDIO27 Y25
C38
22U_0805_6.3V6M
1
2
C68
0.22U_0603_16V4Z
1
2
C37
22U_0805_6.3V6M
1
2
C81
0.22U_0603_16V4Z
1
2
C64
180P_0402_50V8J
1
2
+
C59
220U_Y_4VM
1
2
C80
4.7U_0805_10V4Z
1
2
C84
1000P_0402_25V8J
1
2
C53
22U_0805_6.3V6M
1
2
C62
180P_0402_50V8J
1
2
C67
4.7U_0805_10V4Z
1
2
C82
0.22U_0603_16V4Z
1
2
C42
180P_0402_50V8J
1
2
C76
4.7U_0805_10V4Z
1
2
C74
4.7U_0805_10V4Z
1
2
C70
1000P_0402_25V8J
1
2
C39
22U_0805_6.3V6M
1
2
C51
180P_0402_50V8J
1
2
C34
22U_0805_6.3V6M
1
2
C66
4.7U_0805_10V4Z
1
2
C77
4.7U_0805_10V4Z
1
2
C57
0.22U_0603_16V4Z
1
2
C49
0.22U_0603_16V4Z
1
2
+
C78
220U_Y_4VM
@
1
2
+
C31
330U_X_2VM_R6M
1
2
JC P UF
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VSS1
AA4
VSS2
AA11
VSS3
AA13
VSS4
AA15
VSS5
AA17
VSS6
AA19
VSS7
AB2
VSS8
AB7
VSS9
AB9
VSS10
AB23
VSS11
AB25
VSS12
AC11
VSS13
AC13
VSS14
AC15
VSS15
AC17
VSS16
AC19
VSS17
AC21
VSS18
AD6
VSS19
AD8
VSS20
AD25
VSS21
AE11
VSS22
AE13
VSS23
AE15
VSS24
AE17
VSS25
AE19
VSS26
AE21
VSS27
AE23
VSS28
B4
VSS29
B6
VSS30
B8
VSS31
B9
VSS32
B11
VSS33
B13
VSS34
B15
VSS35
B17
VSS36
B19
VSS37
B21
VSS38
B23
VSS39
B25
VSS40
D6
VSS41
D8
VSS42
D9
VSS43
D11
VSS44
D13
VSS45
D15
VSS46
D17
VSS47
D19
VSS48
D21
VSS49
D23
VSS50
D25
VSS51
E4
VSS52
F2
VSS53
F11
VSS54
F13
VSS55
F15
VSS56
F17
VSS57
F19
VSS58
F21
VSS59
F23
VSS60
F25
VSS61
H7
VSS62
H9
VSS63
H21
VSS64
H23
VSS65
J4
VSS66 J6
VSS67 J8
VSS68 J10
VSS69 J12
VSS70 J14
VSS71 J16
VSS72 J18
VSS73 K2
VSS74 K7
VSS75 K9
VSS76 K11
VSS77 K13
VSS78 K15
VSS79 K17
VSS80 L6
VSS81 L8
VSS82 L10
VSS83 L12
VSS84 L14
VSS85 L16
VSS86 L18
VSS87 M7
VSS88 M9
VSS89 AC6
VSS90 M17
VSS91 N4
VSS92 N8
VSS93 N10
VSS94 N16
VSS95 N18
VSS96 P2
VSS97 P7
VSS98 P9
VSS99 P11
VSS100 P17
VSS101 R8
VSS102 R10
VSS103 R16
VSS104 R18
VSS105 T7
VSS106 T9
VSS107 T11
VSS108 T13
VSS109 T15
VSS110 T17
VSS111 U4
VSS112 U6
VSS113 U8
VSS114 U10
VSS115 U12
VSS116 U14
VSS117 U16
VSS118 U18
VSS119 V2
VSS120 V7
VSS121 V9
VSS122 V11
VSS123 V13
VSS124 V15
VSS125 V17
VSS126 W6
VSS127 Y21
VSS128 Y23
VSS129 N6
C83
1000P_0402_25V8J
1
2
+
C30
330U_X_2VM_R6M
1
2
C60
0.01U_0402_25V4Z
1
2
C35
22U_0805_6.3V6M
1
2
C72
180P_0402_50V8J
1
2
C50
180P_0402_50V8J
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_CKE1_DIMMA
+V_DDR_MCH_REF
DDR_A_MA3
DDR_A_BS#0
DDR_A_RAS#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_A_ODT1
DDR_A_WE#
DDR_A_D4
DDR_A_CAS# DDR_A_ODT0
DDR_CS0_DIMMA#
DDR_CKE1_DIMMA
DDR_A_D29
DDR_A_D30
DDR_A_D35
DDR_A_D26
DDR_A_D38
DDR_A_BS#0
DDR_A_D28
DDR_A_D34
DDR_A_D36
DDR_A_D33
DDR_A_D31
DDR_A_D32
DDR_A_D27
DDR_A_D53
DDR_A_D46
DDR_A_D43
DDR_A_D48
DDR_A_D41
DDR_A_D44
DDR_A_D50
DDR_A_D45
DDR_A_D49
DDR_A_D37
DDR_A_D55
DDR_A_D39
DDR_A_D51
DDR_A_D40
DDR_A_D47
DDR_A_D42
DDR_A_D63
DDR_A_D54
DDR_A_D6
DDR_A_D14
DDR_A_D52
DDR_A_D3
DDR_A_D59
DDR_A_D58
DDR_A_D9
DDR_A_D61
DDR_A_D60
DDR_A_D57
DDR_A_D7
DDR_A_D8
DDR_A_D56
DDR_A_D5
DDR_A_D24
DDR_A_D23
DDR_A_D12
DDR_A_D15
DDR_A_D21
DDR_A_BS#1
DDR_A_D22
DDR_A_D16 DDR_A_D20
DDR_A_BS#2
DDR_A_D10
DDR_A_D13
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D11
DDR_A_DM5
DDR_A_MA11
DDR_A_DM6
DDR_A_DM4
DDR_A_D0
DDR_A_DM7
DDR_A_D62
DDR_A_DM1
DDR_A_DM0
DDR_A_MA4
DDR_A_DM2
DDR_A_D25
DDR_A_D1
DDR_A_DM3
DDR_A_D2
DDR_A_MA8
DDR_A_MA12
DDR_A_MA14
DDR_A_MA9
DDR_A_MA10
DDR_A_DQS#0
DDR_A_MA13
DDR_A_MA1 DDR_A_MA0
DDR_A_MA2
DDR_A_MA7
DDR_A_MA15
DDR_A_MA3
DDR_A_MA5
DDR_A_MA6
DDR_A_DQS2
DDR_A_DQS6
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS#6
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS#2
DDR_A_DQS7
DDR_A_DQS#4
DDR_A_DQS#7
DDR_A_DQS#5
DDR_A_DQS#1
DDR_A_MA4
DDR_A_MA11
DDR_A_MA12
DDR_A_MA5
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
+V_DDR_MCH_REF
DDR_A_MA15
DDR_A_BS#2
DDR_CKE0_DIMMA
DDR_A_MA7
DDR_A_MA6
DDR_A_MA14
DDR_A_MA0
DDR_A_BS#1
DDR_A_MA2
DDR_A_ODT0
DDR_A_MA13
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA1
DDR_A_CAS#
DDR_A_WE#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_CLK0 <5>
DDR_A_CLK#0 <5>
DDR_CKE0_DIMMA<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5>
DDR_A_WE#<5>
DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_RAS# <5>
DDR_A_BS#1 <5>
DDR_CKE1_DIMMA <5>
DDR_A_MA[0..15] <5>
DDR_A_D[0..63] <5>
DDR_A_DQS[0..7] <5>
DDR_A_DM[0..7] <5>
DDR_A_DQS#[0..7] <5>
SMB_CK_DAT0<9,15,20,30>
SMB_CK_CLK0<9,15,20,30>
+V_DDR_MCH_REF <9>
+1.8V+1.8V
+3VS
+1.8V
+1.8V
+0.9V
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
DDRII SO-DIMM 0
Custom
8 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
9/20 S P07000BZ00/SP07000EU00
DDR2 S OCKET H9.2 (REV)
Cross between +1.8V and +0.9V power plan
C101 0.1U_0402_16V4Z
1 2
C91 0.1U_0402_16V4Z
1 2
C97 0.1U_0402_16V4Z
1 2
C96
0.1U_0402_16V4Z
1
2
RP4
47_0804_8P4R_5%
18
27
36
45
C95
1000P_0402_25V8J
1
2
C102 0.1U_0402_16V4Z
1 2
C103
0.1U_0402_16V4Z
1
2
C87 0.1U_0402_16V4Z
1 2
C93 0.1U_0402_16V4Z
1 2
C100 0.1U_0402_16V4Z
1 2
RP3
47_0804_8P4R_5%
18
27
36
45
C90 0.1U_0402_16V4Z
1 2
C98 0.1U_0402_16V4Z
1 2
R43
1K_0402_1%
1 2
RP1
47_0804_8P4R_5%
18
27
36
45
RP2
47_0804_8P4R_5%
18
27
36
45
RP7
47_0804_8P4R_5%
18
27
36
45
C94 0.1U_0402_16V4Z
1 2
C99 0.1U_0402_16V4Z
1 2
RP6
47_0804_8P4R_5%
18
27
36
45
C92 0.1U_0402_16V4Z
1 2
C89 0.1U_0402_16V4Z
1 2
RP5
47_0804_8P4R_5%
18
27
36
45
JP4
FOX_AS0A426-N8RN-7F
CONN@
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SA0 198
SA1 200
R44
1K_0402_1%
1 2
C88 0.1U_0402_16V4Z
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_BS#0
DDR_B_D26
DDR_B_D29
DDR_B_D27
DDR_B_D30
DDR_B_D33
DDR_B_D31
DDR_B_D32
DDR_B_D28
DDR_B_D34
DDR_B_D35
DDR_B_D38
DDR_B_D36
DDR_B_D39
DDR_B_D37
DDR_B_D41
DDR_B_D42
DDR_B_D44
DDR_B_D40
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D45
DDR_B_D46
DDR_B_D49 DDR_B_D53
DDR_B_D51 DDR_B_D55
DDR_B_D50
DDR_B_D52
DDR_B_D56
DDR_B_D54
DDR_B_D59
DDR_B_D57
DDR_B_D58
DDR_B_D61
DDR_B_D63
DDR_B_D60
DDR_B_D3
DDR_B_D8
DDR_B_D6
DDR_B_D7
DDR_B_D5
DDR_B_D14
DDR_B_D13
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D15
DDR_B_D12
DDR_B_D17
DDR_B_D20
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_D24
DDR_B_D16
DDR_B_D23
DDR_B_BS#2
DDR_B_BS#1
DDR_B_D25
DDR_B_D62
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM3
DDR_B_DM1
DDR_B_DM0
DDR_B_DM6
DDR_B_DM5
DDR_B_MA4
DDR_B_D0
DDR_B_D2
DDR_B_D1
DDR_B_D4
DDR_B_MA11
DDR_B_MA10
DDR_B_MA12
DDR_B_MA9
DDR_B_MA6DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA3
DDR_B_MA0
DDR_B_MA8
DDR_B_MA9
DDR_B_MA13
DDR_B_MA15
DDR_B_MA2
DDR_B_MA1
DDR_B_MA14
DDR_B_DQS2
DDR_B_DQS#0
DDR_B_DQS4
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS5
DDR_B_DQS7
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS#4
DDR_B_DQS#2
DDR_B_DQS#6
DDR_B_DQS#3
DDR_B_DQS1
DDR_B_DQS#5
DDR_B_ODT1
DDR_CKE0_DIMMB
DDR_CS1_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_CKE1_DIMMB
DDR_B_CAS# DDR_B_ODT0
DDR_CS0_DIMMB#
DDR_B_MA12
DDR_B_MA5
DDR_B_MA4
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_MA3
DDR_B_MA1
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA13
DDR_B_ODT0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_MA0
DDR_B_MA2
DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_B_MA14
DDR_B_D21
DDR_B_MA15
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_B_BS#2
+V_DDR_MCH_REF<8>
DDR_B_CLK0 <5>
DDR_B_CLK#0 <5>
DDR_CKE0_DIMMB<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5>
DDR_B_WE#<5>
DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>
DDR_B_ODT0 <5>
DDR_B_RAS# <5>
DDR_B_BS#1 <5>
DDR_CKE1_DIMMB <5>
DDR_CS0_DIMMB# <5>
DDR_B_MA[0..15] <5>
DDR_B_D[0..63] <5>
DDR_B_DQS[0..7] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS#[0..7] <5>
SMB_CK_DAT0<8,15,20,30>
SMB_CK_CLK0<8,15,20,30>
+1.8V+1.8V
+3VS
+0.9V
+3VS
+1.8V
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
DDRII SO-DIMM 1
Custom
9 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
9/20 S P07000ET00/SP07000GN00
Cross between +1.8V and +0.9V power plan
RP8
47_0804_8P4R_5%
18
27
36
45
RP14
47_0804_8P4R_5%
18
27
36
45
C108 0.1U_0402_16V4Z
12
RP10
47_0804_8P4R_5%
18
27
36
45
C105 0.1U_0402_16V4Z
12
C113 0.1U_0402_16V4Z
1 2
C114 0.1U_0402_16V4Z
12
RP11
47_0804_8P4R_5%
18
27
36
45
C119
0.1U_0402_16V4Z
1
2
C107 0.1U_0402_16V4Z
1 2
C106 0.1U_0402_16V4Z
1 2
C104
1000P_0402_25V8J
1
2
C117 0.1U_0402_16V4Z
1 2
RP12
47_0804_8P4R_5%
18
27
36
45
C110 0.1U_0402_16V4Z
1 2
C111 0.1U_0402_16V4Z
12
JP5
TYCO_292527-4
CONN@
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
GND 202
GND
201
C115 0.1U_0402_16V4Z
1 2
RP13
47_0804_8P4R_5%
18
27
36
45
C109 0.1U_0402_16V4Z
12
RP9
47_0804_8P4R_5%
18
27
36
45
C118 0.1U_0402_16V4Z
12
C112 0.1U_0402_16V4Z
1 2
C116 0.1U_0402_16V4Z
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN7
H_CADIN15
H_CTLIN1H_CTLON1
H_CADON7
H_CADON15
PCIE_ITX_PRX_P5
PCIE_ITX_PRX_N5
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
SB_TX1N_C
H_CADIP5
H_CADIN9
H_CADIN11
H_CTLIP1
H_CTLIP0
H_CADIN2
H_CADIP3
H_CADIN12
H_CADOP2
H_CADOP6
H_CADOP9
H_CADOP12
H_CADIN8
H_CADON4
H_CADIN5
H_CADIP8
H_CADIP11
H_CADIP14
H_CADOP0
H_CTLIN0
H_CADIN10
H_CADON1
H_CADOP13
H_CADIN1
H_CADIN3
H_CADIN4
H_CADIP10
H_CADIP13
H_CTLOP1
H_CADON5
H_CADON9
H_CADON13
H_CADIP0
H_CADIP7
H_CADON3
H_CADIP4
H_CADIP15
H_CADIN14
H_CTLOP0
H_CADIP2
H_CADOP1
H_CADON0
H_CADON10
H_CADON14
H_CADIP1
H_CADIP6
H_CTLON0
H_CADON2
H_CADOP5
H_CADOP10
H_CADOP3
H_CADOP7
H_CADON8
H_CADOP11
H_CADIP9
H_CADIP12
H_CADON11
H_CADOP14
H_CADIN6
H_CADOP4
H_CADIN0
H_CADIN13
H_CADON6
H_CADOP8
H_CADON12
H_CADOP15
PCIE_PTX_C_IRX_P5<26>
PCIE_PTX_C_IRX_N5<26>
H_CLKIN0 <4>
H_CLKIP0 <4>
H_CTLIN0 <4>
H_CTLIP0 <4>
H_CLKON0<4>
H_CLKOP0<4>
H_CLKOP1<4>
H_CLKON1<4>
H_CTLOP0<4>
H_CTLON0<4>
H_CLKIN1 <4>
H_CLKIP1 <4>
H_CTLIN1 <4>
H_CTLIP1 <4>H_CTLOP1<4>
H_CTLON1<4>
PCIE_ITX_C_PRX_P5 <26>
PCIE_ITX_C_PRX_N5 <26>
PCIE_ITX_C_PRX_N1 <27>
PCIE_ITX_C_PRX_P1 <27>
PCIE_ITX_C_PRX_P2 <26>
PCIE_ITX_C_PRX_N2 <26>
PCIE_ITX_C_PRX_P3 <25>
PCIE_ITX_C_PRX_N3 <25>
PCIE_ITX_C_PRX_P0 <26>
PCIE_ITX_C_PRX_N0 <26>
PCIE_PTX_C_IRX_P0<26>
PCIE_PTX_C_IRX_N0<26>
PCIE_PTX_C_IRX_P1<27>
PCIE_PTX_C_IRX_N1<27>
PCIE_PTX_C_IRX_P3<25>
PCIE_PTX_C_IRX_N3<25>
PCIE_PTX_C_IRX_P2<26>
PCIE_PTX_C_IRX_N2<26>
H_CADIP[0..15] <4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP[0..15]<4>
SB_RX1P<19>
SB_RX1N<19>
SB_RX0P<19>
SB_RX0N<19> SB_TX0P <19>
SB_TX1N <19>
SB_TX0N <19>
SB_TX1P <19>
SB_RX3P<19>
SB_RX3N<19>
SB_RX2P<19>
SB_RX2N<19> SB_TX2P <19>
SB_TX2N <19>
SB_TX3N <19>
SB_TX3P <19>
TMDS_B_CLK <18>
TMDS_B_CLK# <18>
TMDS_B_DATA0 <18>
TMDS_B_DATA0# <18>
TMDS_B_DATA1 <18>
TMDS_B_DATA1# <18>
TMDS_B_DATA2 <18>
TMDS_B_DATA2# <18>
+1.1VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
RS880-HT/PCIE
Custom
10 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
NEED CHECK R68 & R69 WITH AMD
0718 Place within 1"
layout 1:2
0718 Place within 1"
layout 1:2
LAN10/100
WLAN
New Card
CardReader
DP0
GFX_TX0,TX1,TX2 and TX3
RS780M Display Port Support (muxed on GFX)
DP1
GFX_TX4,TX5,TX6 and TX7
AUX0 and HPD0
AUX1 and HPD1
TV Tuner
9/20 S A00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH
C164 0.1U_0402_16V7K
1 2
C162 0.1U_0402_16V7K
1 2
C167 0.1U_0402_16V7K
1 2
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U3A
RS880M_FCBGA528
HT_RXCAD15P
U19
HT_RXCAD15N
U18
HT_RXCAD14P
U20
HT_RXCAD14N
U21
HT_RXCAD13P
V21
HT_RXCAD13N
V20
HT_RXCAD12P
W21
HT_RXCAD12N
W20
HT_RXCAD11P
Y22
HT_RXCAD11N
Y23
HT_RXCAD10P
AA24
HT_RXCAD10N
AA25
HT_RXCAD9P
AB25
HT_RXCAD9N
AB24
HT_RXCAD8P
AC24
HT_RXCAD8N
AC25
HT_RXCAD7P
N24
HT_RXCAD7N
N25
HT_RXCAD6P
P25
HT_RXCAD6N
P24
HT_RXCAD5P
P22
HT_RXCAD5N
P23
HT_RXCAD4P
T25
HT_RXCAD4N
T24
HT_RXCAD3P
U24
HT_RXCAD3N
U25
HT_RXCAD2P
V25
HT_RXCAD2N
V24
HT_RXCAD1P
V22
HT_RXCAD1N
V23
HT_RXCAD0P
Y25
HT_RXCAD0N
Y24
HT_RXCLK1P
AB23
HT_RXCLK1N
AA22
HT_RXCLK0P
T22
HT_RXCLK0N
T23
HT_RXCTL0P
M22
HT_RXCTL0N
M23
HT_RXCTL1P
R21
HT_RXCTL1N
R20
HT_RXCALP
C23
HT_RXCALN
A24
HT_TXCAD15P P18
HT_TXCAD15N M18
HT_TXCAD14P M21
HT_TXCAD14N P21
HT_TXCAD13P M19
HT_TXCAD13N L18
HT_TXCAD12P L19
HT_TXCAD12N J19
HT_TXCAD11P J18
HT_TXCAD11N K17
HT_TXCAD10P J20
HT_TXCAD10N J21
HT_TXCAD9P G20
HT_TXCAD9N H21
HT_TXCAD8P F21
HT_TXCAD8N G21
HT_TXCAD7P K23
HT_TXCAD7N K22
HT_TXCAD6P K24
HT_TXCAD6N K25
HT_TXCAD5P J25
HT_TXCAD5N J24
HT_TXCAD4P H23
HT_TXCAD4N H22
HT_TXCAD3P F23
HT_TXCAD3N F22
HT_TXCAD2P F24
HT_TXCAD2N F25
HT_TXCAD1P E24
HT_TXCAD1N E25
HT_TXCAD0P D24
HT_TXCAD0N D25
HT_TXCLK1P L21
HT_TXCLK1N L20
HT_TXCLK0P H24
HT_TXCLK0N H25
HT_TXCTL0P M24
HT_TXCTL0N M25
HT_TXCTL1P P19
HT_TXCTL1N R18
HT_TXCALP B24
HT_TXCALN B25
C165 0.1U_0402_16V7K
1 2
C160 0.1U_0402_16V7K
1 2
C168 0.1U_0402_16V7K
1 2
C154 0.1U_0402_16V7K
1 2
C159 0.1U_0402_16V7K
1 2
R57 301_0402_1%
1 2
C169 0.1U_0402_16V7K
1 2
C152 0.1U_0402_16V7K
1 2
R58 301_0402_1%
1 2
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS880M_FCBGA528
SB_TX3P AD5
SB_TX3N AE5
GPP_TX2P AA2
GPP_TX2N AA1
GPP_TX3P Y1
GPP_TX3N Y2
SB_RX3P
W5
SB_RX3N
Y5
GPP_RX2P
AD1
GPP_RX2N
AD2
GPP_RX3P
V5
GPP_RX3N
W6
SB_TX0P AD7
SB_TX0N AE7
SB_TX1P AE6
SB_TX1N AD6
SB_RX0P
AA8
SB_RX0N
Y8
SB_RX1P
AA7
SB_RX1N
Y7
PCE_CALRP(PCE_BCALRP) AC8
PCE_CALRN(PCE_BCALRN) AB8
SB_TX2N AC6
SB_RX2P
AA5
SB_RX2N
AA6 SB_TX2P AB6
GPP_RX0P
AE3
GPP_RX0N
AD4
GPP_RX1P
AE2
GPP_RX1N
AD3
GPP_TX0P AC1
GPP_TX0N AC2
GPP_TX1P AB4
GPP_TX1N AB3
GFX_RX0P
D4
GFX_RX0N
C4
GFX_RX1P
A3
GFX_RX1N
B3
GFX_RX2P
C2
GFX_RX2N
C1
GFX_RX3P
E5
GFX_RX3N
F5
GFX_RX4P
G5
GFX_RX4N
G6
GFX_RX5P
H5
GFX_RX5N
H6
GFX_RX6P
J6
GFX_RX6N
J5
GFX_RX7P
J7
GFX_RX7N
J8
GFX_RX8P
L5
GFX_RX8N
L6
GFX_RX9P
M8
GFX_RX9N
L8
GFX_RX10P
P7
GFX_RX10N
M7
GFX_RX11P
P5
GFX_RX11N
M5
GFX_RX12P
R8
GFX_RX12N
P8
GFX_RX13P
R6
GFX_RX13N
R5
GFX_RX14P
P4
GFX_RX14N
P3
GFX_RX15P
T4
GFX_RX15N
T3
GFX_TX0P A5
GFX_TX0N B5
GFX_TX1P A4
GFX_TX1N B4
GFX_TX2P C3
GFX_TX2N B2
GFX_TX3P D1
GFX_TX3N D2
GFX_TX4P E2
GFX_TX4N E1
GFX_TX5P F4
GFX_TX5N F3
GFX_TX6P F1
GFX_TX6N F2
GFX_TX7P H4
GFX_TX7N H3
GFX_TX8P H1
GFX_TX8N H2
GFX_TX9P J2
GFX_TX9N J1
GFX_TX10P K4
GFX_TX10N K3
GFX_TX11P K1
GFX_TX11N K2
GFX_TX12P M4
GFX_TX12N M3
GFX_TX13P M1
GFX_TX13N M2
GFX_TX14P N2
GFX_TX14N N1
GFX_TX15P P1
GFX_TX15N P2
GPP_TX4P Y4
GPP_TX4N Y3
GPP_TX5P V1
GPP_TX5N V2
GPP_RX4P
U5
GPP_RX4N
U6
GPP_RX5P
U8
GPP_RX5N
U7
C155 0.1U_0402_16V7K
1 2
C161 0.1U_0402_16V7K
1 2
C163 0.1U_0402_16V7K
1 2
C156 0.1U_0402_16V7K
1 2
C157 0.1U_0402_16V7K
1 2
C166 0.1U_0402_16V7K
1 2
R55 1.27K_0402_1%
1 2
C158 0.1U_0402_16V7K
1 2
C153 0.1U_0402_16V7K
1 2
R56 2K_0402_1%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA18HTPLL
+NB_HTPVDD
+AVDD2
NB_THERMAL_DC
NB_THERMAL_DA
TV_LUMA
NB_RESET#
+AVDD1
RED
BLUE
CRT_VSYNC
GREEN
CRT_HSYNC
NB_PWRGD
NB_ALLOW_LDTSTOP
NB_LDTSTOP#
+VDDLT18
TV_COMPS
TV_CRMA
+AVDDQ
+VDDLTP18
RED
GREEN
BLUE
+NB_PLLVDD
+VDDA18PCIEPLL
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
NB_PWM
ENBKL
UMA_CRT_CLK<16>
UMA_CRT_DAT<16>
HDMIDAT_UMA<18>
NB_PWRGD<20>
CRT_HSYNC<14,16>
CRT_VSYNC<14,16>
UMA_ENVDD <17>
NBGFX_CLK<15>
NBGFX_CLK#<15>
CLK_SBLINK_BCLK<15>
CLK_SBLINK_BCLK#<15>
HPD <18>
CLK_NBHT<15>
CLK_NBHT#<15>
PLT_RST#<14,19,25,26,27,32,33>
RED<16>
GREEN<16>
BLUE<16>
AUX_CAL<14>
RS780_DFT_GPIO_0<14> SUS_STAT# <20>
LVDS_A2+ <17>
LVDS_A0+ <17>
LVDS_A1+ <17>
LVDS_ACLK- <17>
HDMICLK_UMA<18>
LVDS_ACLK+ <17>
LVDS_A2- <17>
LVDS_A0- <17>
LVDS_A1- <17>
LCD_DDC_DAT<17>
LCD_DDC_CLK<17>
NB_OSC_14.318M<15>
LDT_STOP#<6,19>
CPU_LDT_REQ#<6,19>
SUS_STAT_R# <14>
ENBKL <33>
NB_PWM <17>
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.1VS
+1.1VS
+1.8VS
+1.8VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
RS880 VEDIO/CLK GEN
Custom
11 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
Strap pin
AVDD=100mA
Strap pin
PA_RS780A4
placement close to NB ball
NB temp to SB
Strap pin
L
0.08A/10mil/1vias
R
R73
R1072
R1085
R1086
Veri-Bright Non Veri-Bright
@
@
@
@
Ripely 2.0 support Veri-Bright function
R71
4.7K_0402_5%
1 2
T48 PAD
R64 150_0402_1%@
1 2
L10
BLM18PG121SN1D_0603
1 2
C179
2.2U_0603_6.3V4Z
1
2
R371 300_0402_5%
1 2
T46 PAD
T49PAD
L4
0_0603_5%
R65 715_0402_1%
1 2
L6
BLM18PG121SN1D_0603
1 2
R73
0_0402_5%
1 2
C180
2.2U_0603_6.3V4Z
1
2
R1072 100K_0402_5%
1 2
L11
BLM18PG121SN1D_0603
1 2
C175
2.2U_0603_6.3V4Z
1
2
L5
BLM18PG121SN1D_0603
1 2
R66 0_0402_5%
1 2
R72
4.7K_0402_5%
1 2
T50PAD
C1120
0.1U_0402_16V4Z
1
2
R77 0_0402_5%
1 2
C172
2.2U_0603_6.3V4Z
1
2
C171
2.2U_0603_6.3V4Z
1
2
L2
BLM18PG121SN1D_0603
1 2
T47 PAD
C178
2.2U_0603_6.3V4Z
1
2L3
BLM18PG121SN1D_0603
1 2
R67
0_0402_5%
1 2
R63 150_0402_1%@
1 2
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS880M_FCBGA528
VDDA18HTPLL
H17
SYSRESETb
D8
POWERGOOD
A10
LDTSTOPb
C10
ALLOW_LDTSTOP
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC) D10
DDC_CLK0/AUX0P(NC)
A8 DDC_DATA0/AUX0N(NC)
B8
THERMALDIODE_P AE8
THERMALDIODE_N AD8
I2C_CLK
B9
STRP_DATA
B10
GFX_REFCLKP
T2
GFX_REFCLKN
T1
GPP_REFCLKP
U1
GPP_REFCLKN
U2
PLLVDD18(NC)
D14
PLLVSS(NC)
B12
TXOUT_L0P(NC) A22
TXOUT_L0N(NC) B22
TXOUT_L1P(NC) A21
TXOUT_L1N(NC) B21
TXOUT_L2P(NC) B20
TXOUT_L2N(DBG_GPIO0) A20
TXOUT_L3P(NC) A19
TXOUT_U0P(NC) B18
TXOUT_L3N(DBG_GPIO2) B19
TXOUT_U0N(NC) A18
TXOUT_U1P(PCIE_RESET_GPIO3) A17
TXOUT_U1N(PCIE_RESET_GPIO2) B17
TXOUT_U2P(NC) D20
TXOUT_U2N(NC) D21
TXOUT_U3P(PCIE_RESET_GPIO5) D18
TXOUT_U3N(NC) D19
TXCLK_LP(DBG_GPIO1) B16
TXCLK_LN(DBG_GPIO3) A16
TXCLK_UP(PCIE_RESET_GPIO4) D16
TXCLK_UN(PCIE_RESET_GPIO1) D17
VDDLTP18(NC) A13
VSSLTP18(NC) B13
C_Pr(DFT_GPIO5)
E17
Y(DFT_GPIO2)
F17
COMP_Pb(DFT_GPIO4)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC) D9
I2C_DATA
A9
TESTMODE D13
HT_REFCLKN
C24 HT_REFCLKP
C25
SUS_STAT#(PWM_GPIO5) D12
GREEN(DFT_GPIO1)
E18
BLUE(DFT_GPIO3)
E19
DAC_VSYNC(PWM_GPIO6)
B11 DAC_HSYNC(PWM_GPIO4)
A11
DAC_RSET(PWM_GPIO1)
G14
AVDD1(NC)
F12
AVDD2(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
AVDDDI(NC)
F14
AVSSDI(NC)
G15
AVDDQ(NC)
H15
AVSSQ(NC)
H14
VDDLT18_2(NC) B15
VDDLT33_1(NC) A14
VDDLT33_2(NC) B14
VSSLT1(VSS) C14
VSSLT2(VSS) D15
VDDLT18_1(NC) A15
VSSLT3(VSS) C16
VSSLT4(VSS) C18
VSSLT5(VSS) C20
LVDS_DIGON(PCE_TCALRP) E9
LVDS_BLON(PCE_RCALRP) F7
LVDS_ENA_BL(PWM_GPIO2) G12
VSSLT6(VSS) E20
VDDA18PCIEPLL1
D7
VDDA18PCIEPLL2
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
GPPSB_REFCLKP(SB_REFCLKP)
V4
GPPSB_REFCLKN(SB_REFCLKN)
V3
DDC_DATA1/AUX1N(NC)
A7 DDC_CLK1/AUX1P(NC)
B7
DAC_SCL(PCE_RCALRN)
F8
DAC_SDA(PCE_TCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS) C22
RSVD
G11
R1086 100K_0402_5%@
1 2
L7
BLM18PG121SN1D_0603
1 2
C176
2.2U_0603_6.3V4Z
1
2
R80
1.8K_0402_5%
1 2
R1085 0_0402_5%@1 2
C173
0.1U_0402_16V4Z
1
2
C174
4.7U_0805_10V4Z
1
2
R88 10K_0402_5%
12
R62 150_0402_1%@
1 2
L9
BLM18PG121SN1D_0603
1 2
C170
2.2U_0603_6.3V4Z
1
2
R68
0_0402_5%
1 2
R69 0_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MEM_DQS_P0
MEM_DQS_P1
MEM_DQS_N0
MEM_A9
MEM_A2
MEM_A12
MEM_DQ10
MEM_DQS_P0
+MEM_VREF
MEM_DQS_N0
MEM_ODT
MEM_DQS_P1
MEM_DM1
MEM_DQS_N1
MEM_DQ14
MEM_A2
MEM_DQ7
MEM_A8
MEM_DQ12
MEM_A1
+NB_IOPLLVDD
+1.8V_IOPLLVDD
MEM_A3
+MEM_VREF
MEM_A0
MEM_DQ4
MEM_DQ2
MEM_DQ5
MEM_DQ0
MEM_DQ6
MEM_DQ11
MEM_DQ1
MEM_A11
MEM_BA0
MEM_BA1
MEM_CKE
MEM_WE#
MEM_CS#
MEM_A4
MEM_DQS_N1
MEM_RAS#
MEM_CAS#
MEM_BA2
MEM_DM1
MEM_CLKP
MEM_CLKN
MEM_ODT
MEM_DM0
MEM_A10
MEM_DQ15
+MEM_VREF1
MEM_A11
MEM_A8
MEM_A9
MEM_CAS#
MEM_CS#
MEM_CLKN
MEM_CKE
MEM_RAS#
MEM_CLKP
MEM_WE#
MEM_DM0
MEM_BA0
MEM_A7
MEM_DQ13
+MEM_VREF1
MEM_A0
MEM_A10
MEM_BA2
MEM_A3
MEM_DQ8
MEM_BA1
MEM_A6
+VDDL
MEM_DQ9
MEM_A1
MEM_A6
MEM_A7
MEM_A4
MEM_A5
MEM_DQ3
MEM_DQ2
MEM_DQ0
MEM_DQ1
MEM_DQ3
MEM_DQ10
MEM_DQ7
MEM_DQ11
MEM_DQ8
MEM_DQ5
MEM_DQ6
MEM_DQ9
MEM_DQ15
MEM_DQ13
MEM_DQ14
MEM_DQ4
MEM_DQ12
MEM_A12
MEM_A5
MEM_COMP_P
MEM_COMP_N
+1.8VS
+1.8VS
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ
+1.1VS
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
RS880 Side-Port DDR2 SDRAM
Custom
12 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
Side Port disable,VREF need
connect to +1.8VS for DDR2
Layout Note: 50 mil for VSSDL
MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions
220 ohm @ 100MHz,2A
9/20 S A000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P
02/15 Remove L96. 02/15 Change L12 and L13 from bead to 0 ohm resistor.
Support 8M x 16bit x 8 bank side port
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS880M_FCBGA528
MEM_A0(NC)
AB12
MEM_A1(NC)
AE16
MEM_A2(NC)
V11
MEM_A3(NC)
AE15
MEM_A4(NC)
AA12
MEM_A5(NC)
AB16
MEM_A6(NC)
AB14
MEM_A7(NC)
AD14
MEM_A8(NC)
AD13
MEM_A9(NC)
AD15
MEM_A10(NC)
AC16
MEM_A11(NC)
AE13
MEM_A12(NC)
AC14
MEM_A13(NC)
Y14
MEM_BA0(NC)
AD16
MEM_BA1(NC)
AE17
MEM_BA2(NC)
AD17
MEM_RASb(NC)
W12
MEM_CASb(NC)
Y12
MEM_WEb(NC)
AD18
MEM_CSb(NC)
AB13
MEM_CKE(NC)
AB18
MEM_ODT(NC)
V14
MEM_CKP(NC)
V15
MEM_CKN(NC)
W14
MEM_DM0(NC) W17
MEM_DM1/DVO_D8(NC) AE19
MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
MEM_DQS1P(NC) AD20
MEM_DQS1N(NC) AE21
MEM_DQ0/DVO_VSYNC(NC) AA18
MEM_DQ1/DVO_HSYNC(NC) AA20
MEM_DQ2/DVO_DE(NC) AA19
MEM_DQ3/DVO_D0(NC) Y19
MEM_DQ4(NC) V17
MEM_DQ5/DVO_D1(NC) AA17
MEM_DQ6/DVO_D2(NC) AA15
MEM_DQ7/DVO_D4(NC) Y15
MEM_DQ8/DVO_D3(NC) AC20
MEM_DQ9/DVO_D5(NC) AD19
MEM_DQ10/DVO_D6(NC) AE22
MEM_DQ11/DVO_D7(NC) AC18
MEM_DQ12(NC) AB20
MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
MEM_DQ15/DVO_D11(NC) AD21
MEM_COMPP(NC)
AE12
MEM_COMPN(NC)
AD12 MEM_VREF(NC) AE18
IOPLLVDD18(NC) AE23
IOPLLVSS(NC) AD23
IOPLLVDD(NC) AE24
C202
0.1U_0402_16V4Z
1
2
R97
1K_0402_1%
1 2
C184
1U_0603_10V6K
1
2
C607
1U_0402_6.3V4Z
1
2
C182
0.1U_0402_16V4Z
1
2
C195
0.1U_0402_16V4Z
1
2
R99
1K_0402_1%
1 2
L15
0_0805_5%
1 2
R92 40.2_0402_1%
12
R96
1K_0402_1%
1 2
C196
0.1U_0402_16V4Z
1
2
C181
2.2U_0603_6.3V4Z
1
2
C203
22U_0805_6.3V6M
1
2
C201
0.1U_0402_16V4Z
1
2
C608
1U_0402_6.3V4Z
1
2
R93 40.2_0402_1%
12
L12
0_0603_5%
1 2
R98
1K_0402_1%
1 2
U61
HY5PS561621AFP-25_FBGA84
VREF
J2
LDM
F3
UDM
B3
DQ14 B1
DQ13 D9
DQ12 D1
DQ11 D3
DQ10 D7
DQ9 C2
DQ8 C8
DQ7 F9
DQ6 F1
DQ5 H9
DQ4 H1
DQ3 H3
DQ2 H7
DQ1 G2
DQ0 G8
BA1
L3 BA0
L2
A11
P7
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A0
M8 A1
M3 A2
M7
RAS
K7
CKE
K2
ODT
K9
CS
L8
CAS
L7
CK
J8 CK
K8
WE
K3 VDDQ G9
VDDQ A9
VDDQ C1
VDDQ C3
VDDQ C7
VDDQ C9
VDDQ E9
VDDQ G1
VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
VSSQ D8
VSSQ E7
VSSQ F2
VSSQ F8
VSSQ H2
VSSQ H8
VSS A3
VSS E3
VSS J3
VSS N1
VSS P9
UDQS
A8 UDQS
B7
LDQS
E8 LDQS
F7
VDDQ G3
VDDQ G7
VDD A1
VDD E1
VDD J9
VDD M9
VDD R1
A12
R2
DQ15 B9
VDDL J1
VSSDL J7
NC
R8
NC
A2
NC
L1
NC
R3
NC
R7
NC
E2
C200
0.1U_0402_16V4Z
1
2
C199
0.1U_0402_16V4Z
1
2
C183
2.2U_0603_6.3V4Z
1
2
L13
0_0603_5%
1 2
R91
100_0402_1%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+VDDHTRX
+VDDHT
+VDDA18PCIE
+VREF1.35V
+1.8V_VDD_SP
+VDDHTTX
VLDT_EN#<36>
+1.1VS
+1.8VS
+1.1VS +NB_VDDC
+1.8VS
+3VS
+1.8VS
+1.2V_HT
+1.1VS
+3VS
+1.8VS
+1.35VS
+1.8VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
RS880 PWR/GND
Custom
13 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
2A
2A
2A
2A
VDDA_12=2.5A
VDD_CORE=5A
L
Just for RS780M A11 version boot issue
L
0.6A/50mil/4vias
L
0.45A/40mil/3vias
L
0.5A/50mil/4vias
L
0.25A/30mil/2vias
L
0.7A/60mil/4vias
L
7A/280mil/16vias
L
0.15A/30mil/2vias
C2470.1U_0402_16V4Z
1
2
C239
0.1U_0402_16V4Z
1
2
C238
0.1U_0402_16V4Z
1
2
C1067
10U_0805_10V4Z@
1
2
C216
0.1U_0402_16V4Z
1
2
G
D
S
Q163
2N7002_SOT23-3@
2
13
C215
4.7U_0805_10V4Z
1
2
C2420.1U_0402_16V4Z
1
2
L22
0_0805_5%
12
C2440.1U_0402_16V4Z
1
2
L16
0_0805_5%
12
C248 0.1U_0402_16V4Z
12
C217
0.1U_0402_16V4Z
1
2
PART 5/6
POWER
U3E
RS880M_FCBGA528
VDDHT_1
J17
VDDHT_2
K16
VDDHT_3
L16
VDDHT_4
M16
VDDHT_5
P16
VDDHT_6
R16
VDDHT_7
T16
VDDHTTX_1
AE25
VDDHTTX_2
AD24
VDDHTTX_3
AC23
VDDHTTX_4
AB22
VDDHTTX_5
AA21
VDDHTTX_6
Y20
VDDHTTX_7
W19
VDDHTTX_8
V18
VDDHTRX_1
H18
VDDHTRX_2
G19
VDDHTRX_3
F20
VDDHTRX_4
E21
VDDHTRX_5
D22
VDD18_1
F9
VDD18_2
G9
VDD18_MEM1(NC)
AE11
VDD18_MEM2(NC)
AD11
VDDA18PCIE_1
J10
VDDA18PCIE_2
P10
VDDA18PCIE_3
K10
VDDA18PCIE_10
Y9
VDDA18PCIE_11
AA9
VDDA18PCIE_12
AB9
VDDA18PCIE_13
AD9
VDDA18PCIE_14
AE9
VDDA18PCIE_6
W9
VDDA18PCIE_7
H9
VDDPCIE_1 A6
VDDPCIE_2 B6
VDDPCIE_3 C6
VDDPCIE_4 D6
VDDPCIE_5 E6
VDDPCIE_6 F6
VDDPCIE_7 G7
VDDPCIE_8 H8
VDDPCIE_9 J9
VDDA18PCIE_4
M10
VDDA18PCIE_5
L10
VDDC_1 K12
VDDC_2 J14
VDDC_3 U16
VDDPCIE_11 M9
VDDC_4 J11
VDDC_5 K15
VDDPCIE_10 K9
VDDC_6 M12
VDDC_7 L14
VDDC_8 L11
VDDC_9 M13
VDDC_10 M15
VDDC_11 N12
VDDC_12 N14
VDDC_13 P11
VDDC_14 P13
VDDC_15 P14
VDDC_16 R12
VDDC_17 R15
VDDC_18 T11
VDDC_19 T15
VDDC_20 U12
VDDC_21 T14
VDD33_1(NC) H11
VDD33_2(NC) H12
VDD_MEM1(NC) AE10
VDD_MEM2(NC) AA11
VDD_MEM3(NC) Y11
VDD_MEM4(NC) AD10
VDD_MEM6(NC) AC10
VDD_MEM5(NC) AB10
VDDA18PCIE_8
T10
VDDC_22 J16
VDDPCIE_12 L9
VDDA18PCIE_9
R10
VDDPCIE_13 P9
VDDPCIE_14 R9
VDDPCIE_15 T9
VDDPCIE_16 V9
VDDPCIE_17 U9
VDDA18PCIE_15
U10
VDDHTRX_6
B23
VDDHTRX_7
A23
VDDHTTX_9
U17
VDDHTTX_10
T17
VDDHTTX_11
R17
VDDHTTX_12
P17
VDDHTTX_13
M17
C598 0.1U_0402_16V4Z
12
+
C234
330U_D2E_2.5VM_R15
1
2
C228
0.1U_0402_16V4Z
1
2
C218
0.1U_0402_16V4Z
1
2
C597 0.1U_0402_16V4Z
12
C1064
10U_0805_10V4Z@
1
2
C2310.1U_0402_16V4Z
1
2
C2500.1U_0402_16V4Z
1 2
C209
4.7U_0805_10V4Z
1
2
C223 0.1U_0402_16V4Z
12
C237
0.1U_0402_16V4Z
1
2
C23310U_0805_10V4Z
1
2
C222 1U_0402_6.3V4Z
1 2
C236
0.1U_0402_16V4Z
1
2
R1051 0_0603_5%
1 2
R1017 0_0402_5%@
1 2
C2300.1U_0402_16V4Z
1
2
R1016
3K_0402_5%@
12
L18
0_0805_5%
12
L17
FBMA-L11-201209-221LMA30T_0805
1 2
C251
1U_0402_6.3V4Z
1
2
U64
G2992F1U_SO8@
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
C246
4.7U_0805_10V4Z
1
2
C599 0.1U_0402_16V4Z
12
C2410.1U_0402_16V4Z
1
2
C229
0.1U_0402_16V4Z
1
2
C214
0.1U_0402_16V4Z
1
2
C208
0.1U_0402_16V4Z
1
2
C224 0.1U_0402_16V4Z
12
PJP604
PAD-OPEN 4x4m
1 2
C225
4.7U_0805_10V4Z
1
2
PART 6/6
GROUND
U3F
RS880M_FCBGA528
VSSAHT1
A25
VSSAHT2
D23
VSSAHT3
E22
VSSAHT4
G22
VSSAHT5
G24
VSSAHT6
G25
VSSAHT7
H19
VSSAHT8
J22
VSSAHT9
L17
VSSAHT10
L22
VSSAHT11
L24
VSSAHT12
L25
VSSAHT13
M20
VSSAHT14
N22
VSSAHT15
P20
VSSAHT16
R19
VSSAHT17
R22
VSSAHT18
R24
VSSAHT19
R25
VSSAHT21
U22
VSSAHT22
V19
VSSAHT23
W22
VSSAHT24
W24
VSSAHT25
W25
VSSAHT26
Y21
VSSAHT27
AD25
VSS2 D11
VSS3 G8
VSS4 E14
VSS5 E15
VSS7 J12
VSS8 K14
VSS9 M11
VSS10 L15
VSS11
L12
VSS12
M14
VSS13
N13
VSS14
P12
VSS15
P15
VSS16
R11
VSS17
R14
VSS18
T12
VSS19
U14
VSS20
U11
VSS21
U15
VSS22
V12
VSS23
W11
VSS24
W15
VSS25
AC12
VSS26
AA14
VSS27
Y18
VSS28
AB11
VSS29
AB15
VSS30
AB17
VSS31
AB19
VSS32
AE20
VSSAPCIE1 A2
VSSAPCIE2 B1
VSSAPCIE3 D3
VSSAPCIE4 D5
VSSAPCIE5 E4
VSSAPCIE6 G1
VSSAPCIE7 G2
VSSAPCIE8 G4
VSSAPCIE9 H7
VSSAPCIE10 J4
VSSAPCIE11 R7
VSSAPCIE12 L1
VSSAPCIE13 L2
VSSAPCIE14 L4
VSSAPCIE15 L7
VSS34
K11
VSSAPCIE16 M6
VSSAPCIE17 N4
VSSAPCIE18 P6
VSSAPCIE19 R1
VSSAPCIE20 R2
VSSAPCIE21 R4
VSSAPCIE22 V7
VSSAPCIE23 U4
VSSAPCIE24 V8
VSSAPCIE25 V6
VSSAPCIE26 W1
VSSAPCIE27 W2
VSSAPCIE28 W4
VSSAPCIE29 W7
VSSAPCIE30 W8
VSSAPCIE31 Y6
VSSAPCIE32 AA4
VSSAPCIE33 AB5
VSSAPCIE34 AB1
VSSAPCIE35 AB7
VSSAPCIE36 AC3
VSSAPCIE37 AC4
VSSAPCIE38 AE1
VSSAPCIE39 AE4
VSSAPCIE40 AB2
VSS1 AE14
VSSAHT20
H20
VSS33
AB21
VSS6 J15
C252
1U_0402_6.3V4Z
1
2
C249 4.7U_0805_10V4Z
12
R1015
1K_0402_1%
@
12
C206
0.1U_0402_16V4Z
1
2
L19
0_0805_5%
12
C235
4.7U_0805_10V4Z
1
2
C212 10U_0805_10V4Z
C2320.1U_0402_16V4Z
1
2
C2400.1U_0402_16V4Z
1
2
C227
0.1U_0402_16V4Z
1
2
C2530.1U_0402_16V4Z
1 2
C219 1U_0402_6.3V4Z
1 2
C1068
0.1U_0402_16V7K@
1
2
C220 1U_0402_6.3V4Z
1 2
C1066
0.1U_0402_16V7K@
1
2
C221 1U_0402_6.3V4Z
1 2
C211 10U_0805_10V4Z
C226
0.1U_0402_16V4Z
1
2
C210
0.1U_0402_16V4Z
1
2
C2430.1U_0402_16V4Z
1
2
C1065
1U_0603_10V6K@
1
2
C207
0.1U_0402_16V4Z
1
2
C24510U_0805_10V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUS_STAT_R#<11> PLT_RST# <11,19,25,26,27,32,33>
RS780_DFT_GPIO_0<11>
CRT_HSYNC<11,16>
CRT_VSYNC<11,16>
AUX_CAL<11>
+3VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
RS880 STRAPS
Custom
14 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)
RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
Enables the Test Debug Bus using GPIO.
1 : Disable (RS780) Enable (RX780)
0 : Enable (RS780) Disable (RX780)
PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
DFT_GPIO1: LOAD_EEPROM_STRAPS
RS780 use HSYNC to enable SIDE PORT (internal pull high)
RS780 DFT_GPIO1
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
R102 1K_0402_5%@
12
R107 3K_0402_5%
12
R101 1K_0402_5%
12
D4 CH751H-40PT_SOD323-2@
2 1
R105 1K_0402_5%@
12
R104 150_0402_1%@
1 2
R1064 3K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLKREQ_MCARD2#
CLK_XTAL_OUT
CLK_XTAL_IN
CLKREQ_NCARD#
CLKREQ_MCARD2#
CLK_48M_USB_R
CLK_XTAL_IN
CLK_XTAL_OUT
NB_OSC_14.318M_R
SEL_SATA
27M_SEL
SEL_SATA
27M_SEL
CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLKREQ_NCARD#
CLKREQ_MCARD1#
CLKREQ_MCARD1#
CLKREQ_LAN#
CLKREQ_LAN#
CLKREQ4
CLKREQ4
CLK_48M_USB
NB_OSC_14.318M
CLK_14M_SIO
CLK_PCIE_MCARD0# <27>
CLK_PCIE_MCARD0 <27>
NB_OSC_14.318M <11>
CLK_PCIE_MCARD2<26>
CLK_PCIE_MCARD2#<26>
CLK_PCIE_MCARD1#<26>
CLK_PCIE_MCARD1<26>
CLK_CPU_BCLK# <6>
CLK_CPU_BCLK <6>
NBGFX_CLK <11>
NBGFX_CLK# <11>
CLK_PCIE_NCARD <26>
CLK_PCIE_NCARD# <26>
CLKREQ_NCARD# <26>
CLKREQ_MCARD2# <26>
SMB_CK_CLK0<8,9,20,30>
SMB_CK_DAT0<8,9,20,30>
CLK_NBHT# <11>
CLK_NBHT <11>
CLK_48M_USB <20>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
CLK_SBLINK_BCLK#<11>
CLK_SBLINK_BCLK<11> CLK_SBSRC_BCLK# <19>
CLK_SBSRC_BCLK <19>
CLKREQ_MCARD1# <26>
CLKREQ_LAN# <25>
CLK_14M_SB <19>
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+VDDCLK_IO
+1.2V_HT
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+VDDCLK_IO
+VDDCLK_IO
+VDDCLK_IO
+3VS_CLK
+3VS_CLK
+3VS
+3VS_CLK
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
Clock generator
Custom
15 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
100M DIFF(IN/OUT)*
HT_REFCLKP
RX780 RS780
NB CLOCK INPUT TABLE
100M DIFF
100M DIFF
100M DIFF
100M DIFF
14M SE (1.8V) 14M SE (1.1V)
NB CLOCKS
NC vr ef
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK 100M DIFF
Card Reader
SEL_SATA
* default
configure as normal SRC(SRC_6) output
1
*
0
configure as SATA output
MiniCard_2
CPU
MiniCard_1
GLAN
New Card
configure as single-ended 66MHz output1
*0 configure as differential 100MHz output
NB
NB GFX
configure as 27M and 27M_SS output
NB_OSC_14.318M
1 *
0 con f igure as SRC_7 output
* default
RS780
1.8V 75R/100RRX780
1.1V 200R/100R
OSC_14M_NB
27M_SEL
PA_RS7X0A1
* default
Routing the trace at least 10mil
SB LINK SB SRC
Use voltage divider resistor R379 & R380 to pull low
PA_RS7X0A1
For IC S need to pull high.
For SL G is NC
EMI Caps for single end clock.
01/23 14.318MHz For SB710 reference
C446
0.1U_0402_16V4Z
1
2
C451
1U_0402_6.3V4Z
@
1
2
C461
0.1U_0402_16V4Z
1
2
C447
0.1U_0402_16V4Z
1
2
Y2
14.31818MHZ_20P_6X1430004201
12
C453
0.1U_0402_16V4Z
1
2
R324 8.2K_0402_5%
1 2
R325 8.2K_0402_5%
1 2
R326 8.2K_0402_5%
1 2
C450
0.1U_0402_16V4Z
1
2
SLG8SP626VTR_QFN72_10x10
U10
VDD_CPU 54
VDD_CPU_I/O 53
VSS_CPU 52
CLKREQ_1# 51
CLKREQ_2# 50
VDD_A 49
VSS_SRC
19
SRC_1#
20
SRC_1
21
SRC_0#
22
SRC_0
23
CLKREQ_0#
24
ATIGCLK_2#
25
ATIGCLK_2
26
VSS_ATIG
27
VDD_ATIG_IO
28
VDD_ATIG
29
ATIGCLK_1#
30
ATIGCLK_1
31
ATIGCLK_0#
32
VSS_SB_SRC
36 SB_SRC_1
35 SB_SRC_1#
34 ATIGCLK_0
33
VSS_A 48
VSS_SATA 47
SRC_6/SATA 46
SRC_6#/SATA# 45
VDD_SATA 44
CLKREQ_3# 43
CLKREQ_4# 42
SB_SRC_SLOW# 41
SB_SRC_0 40
SB_SRC_0# 39
VDD_SB_SRC 38
VDD_SB_SRC_IO 37
REF_1/SEL_SATA 64
REF_2/SEL_27 63
VDD_REF 62
VDD_HTT 61
HTT_0/66M_0 60
HTT_0#/66M_1 59
VSS_HTT 58
PD# 57
CPU_K8_0 56
CPU_K8_0# 55
SCL
1
SDA
2
VDD_DOT
3
SRC_7#/27M
4
SRC_7/27M_SS
5
VSS_DOT
6
SRC_5#
7
SRC_5
8
SRC_4#
9
SRC_4
10
VSS_SRC
11
VDD_SRC_IO
12
SRC_3#
13
SRC_3
14
SRC_2#
15
SRC_2
16
VDD_SRC
17
VDD_SRC_IO
18
REF_0/SEL_HTT66 65
VSS_REF 66
XTAL_IN 67
XTAL_OUT 68
VDD_48 69
48MHz_1 70
48MHz_0 71
VSS_48 72
GND 73
C465
22P_0402_50V8J
1
2
R379 158_0402_1%
1 2
C460
0.1U_0402_16V4Z
1
2
R372 10K_0402_5%
1 2
R186
261_0402_1%@
1 2
R1106
110_0402_5%
C464
22P_0402_50V8J
1
2
C455
0.1U_0402_16V4Z
1
2
R946 0_0402_1%
1 2
R179
8.2K_0402_5%
@
1 2
R1045 8.2K_0402_5%@
1 2
C1075
12P_0402_50V8J
1
2
R168
0_0805_5%
1 2 C448
0.1U_0402_16V4Z
1
2
R1105 75_0402_1%
@
1 2
R174 8.2K_0402_5%
1 2
C452
10U_0805_10V4Z
1
2
C458
0.1U_0402_16V4Z
1
2
R945 0_0402_1%
1 2
C449
0.1U_0402_16V4Z
1
2
R380
90.9_0402_1%
1 2
R180
8.2K_0402_5%
1 2
C457
0.1U_0402_16V4Z
1
2
C459
0.1U_0402_16V4Z
1
2
C445
0.1U_0402_16V4Z
1
2
R170 33_0402_5% 1 2
C1076
12P_0402_50V8J
1
2
R181
8.2K_0402_5%
1 2
C1123
1U_0402_6.3V4Z
1 2
R167
0_0805_5%
1 2
C1106
0.1U_0603_25V7K
1
2
C1074
12P_0402_50V8J
1
2
R1039 8.2K_0402_5%
1 2
C444
10U_0805_10V4Z
1
2
C454
0.1U_0402_16V4Z
1
2
C456
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GREEN_L
D_DDCCLK
D_DDCDATA
H S YNC
VSYNC
BLUE_L
GREEN
RED
BLUE
RED_L
D_HSYNC
D_DDCCLK
VSYNC
H S YNC
D_VSYNC
D_DDCDATA
D_HSYNC <35>
D_VS YNC <35>
RED_L <35>
GREEN_L <35>
BLUE_L <35>
RED<11>
GREEN<11>
BLUE<11>
UMA_CRT_CLK<11>
UMA_CRT_DAT<11> D_DDCDATA <35>
D_DDCCLK <35>
CRT_HSYNC<11,14>
CRT_VSYNC<11,14>
+3VS
+CRT_VCC
+CRT_VCC
+CRT_VCC+5VS
+CRT_VCC
+R_CRT_VCC
+3VS
+CRT_VCC
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
CRT Connector
Custom
16 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
CRT CONNECTOR
v0.2 ADD
v0.2 ADD
F2
1A_6VDC_MINISMDC110
21
C475
0.1U_0402_16V4Z
1
2
U13
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
JCRT
SUYIN_070546FR015S263ZRCONN@
RGND
6
ID0
11
Red
1
GGND
7
SDA
12
Green
2
BGND
8
Hsync
13
Blue
3
+5V
9
Vsync
14
res
4
SGND
10
SCL
15
GND
5
GND
16
GND
17
Q10A
2N7002DW-7-F_SOT363-6
61
2
C477
0.1U_0402_16V4Z
@
1 2
R211
75_0402_1%
12
L49
BLM15AG121SN1D_0402
1 2
L48
BLM15AG121SN1D_0402
1 2
C858
6P_0402_50V8K
1
2
R214
75_0402_1%
12
D35
DAN217_SC59
@
2
3
1
C469
6P_0402_50V8K
1
2
D37
DAN217_SC59
@
2
3
1
L47
BLM15AG121SN1D_0402
1 2
R100
6.8K_0402_5%
C857
470P_0402_50V8J
@
1
2
D36
RB491D_SOT23
2 1
U14
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R237
4.7K_0402_5%
12
C470
10P_0402_50V8J
@
1
2
C1107
0.1U_0603_25V7K
1
2
C856
470P_0402_50V8J
@
1
2
C859
6P_0402_50V8K
1
2
R1022 0_0402_5%@
1 2
R240 0_0603_5%
1 2
C476
6P_0402_50V8K
1
2
Q10B
2N7002DW-7-F_SOT363-6
3
5
4
R241 0_0603_5%
1 2
C474
10P_0402_50V8J
@
1
2
D34
DAN217_SC59
@
2
3
1
R217
75_0402_1%
12
R238
4.7K_0402_5%
1 2
R218
6.8K_0402_5%
C471
6P_0402_50V8K
1
2
C472
6P_0402_50V8K
1
2
C473
0.1U_0402_16V4Z
1 2
R1023 0_0402_5%@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LVDS_A1+
LVDS_A1-
BKOFF#
LVDS_A2+
LCD_DDC_DAT
DAC_BRIG
LVDS_A0+
LVDS_A0-
DMIC_CLK
DMIC_DAT
LVDS_A2-
LCD_DDC_DAT
LCD_DDC_CLK
LCD_DDC_CLK
BKOFF#
LVDS_ACLK-
LVDS_ACLK+
USB20_P5
USB20_N5
LVDS_A1+LVDS_A1-
LVDS_A2+
LVDS_A0+LVDS_A0-
LVDS_A2-
LVDS_ACLK- LVDS_ACLK+
USB20_P5
USB20_N5
INV_PWM
INV_PWM
DAC_BRIG <33>
BKOFF# <33>
DMIC_DAT <28>
DMIC_CLK <28>
LCD_DDC_DAT <11>
LCD_DDC_CLK <11>
LVDS_A2+ <11>
LVDS_A2- <11>
LVDS_A1+ <11>
LVDS_A1- <11>
LVDS_ACLK+ <11>
LVDS_ACLK- <11>
LVDS_A0+ <11>
LVDS_A0- <11>
UMA_ENVDD<11>
CAM_SHDN# <21>
USB20_P5<20>
USB20_N5<20>
NB_PWM<11>
EC_PWM<33>
+3VS
+3VS
INVPWR_B++LCDVDD
+USB_CAM
+LCDVDD
+LCDVDD
+5VALW
+5VS
B+
+USB_CAM
+5VALW
+USB_CAM
+3VS
+5VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
LCD CONN. / WebCam
Custom
17 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
LVDS CONN
80mil
USB_VCCA is +3.9V, R892:100K;
R891:215KKohm
G916 Vref=1.25V when U54 install
G916-390T1UF
9/20 S P02000EA00/SP02000BW00
L
Close to JLVDS
80mil
L
C718 install when U54 is
RT9193-39GB
Ripely 2.0 Support Veri-Bright function
PJP4
PAD-OPEN 2x2m
2 1
R1084 0_0402_5%
1 2
C867
680P_0402_50V7K
@
12
C483
680P_0402_50V7K
@
1
2
L44
FBMA-L11-201209-221LMA30T_0805
1 2
R2754.7K_0402_5%
1 2
C1108
680P_0402_50V7K
1
2
R491
100_0805_5%
1 2
R892
100K_0402_1%@
12
R224
1M_0402_5%
1 2
R1078 0_0402_5%@1 2
D22
PRTR5V0U2X_SOT143-4@
GND 1
IO1 2
IO2
3
VIN
4
C1056 10P_0402_50V8J@
1 2
C719
10U_0805_10V4Z
1
2
U54
RT9193-39GB_SOT23-5
VIN
1
GND
2
EN
3
VOUT 5
BP 4
C720
10U_0805_10V4Z 1
2
C1058 10P_0402_50V8J@
1 2
C1057 10P_0402_50V8J@
1 2
R276
2.2K_0402_5%
1 2
G
D
S
Q43
SI2301BDS-T1-E3_SOT23-3
2
1 3
C480
680P_0402_50V7K
12
JLVDS
ACES_88242-4001
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
GND
41 GND 42
Q45B
2N7002DW-7-F_SOT363-6
3
5
4
R891
215K_0402_1%@
12
C1059 10P_0402_50V8J@
1 2
R222
100K_0402_5%
1 2
C718
0.1U_0402_16V4Z
1
2
C866
680P_0402_50V7K
@
12
C487
4.7U_0805_10V4Z
R1014
0_0402_5%
@
1 2
C863
1000P_0402_50V7K
1
2
R225
220_0402_5%
12
R2744.7K_0402_5%
1 2
C491
0.1U_0402_16V4Z
1
2
Q45A
2N7002DW-7-F_SOT363-6
61
2
C479
680P_0402_50V7K
1
2
C481
680P_0402_50V7K
12
C482
680P_0402_50V7K
@
1
2
PJP6
PAD-OPEN 2x2m
2 1
R4834.7K_0402_5%@
1 2
R1013
0_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDMI_R_D0-
HDMI_CLK-
HDMI_TX0+
HDMI_TX0-
HDMI_R_D0+
HDMI_TX1-
HDMI_R_D2-
HDMI_R_D2+HDMI_TX2+
HDMI_TX2-
HDMI_R_D1+
HDMI_R_D1-
HDMI_TX1+
HDMI_SDATA
HDMI_SCLK
HDMI_TX0-
HDMI_TX0+
HDMI_TX1-
HDMI_TX1+
HDMI_TX2-
HDMI_TX2+
HDMI_HPD
HDMI_CLK+
HDMI_CLK-
HDMI_TX0+
HDMI_TX0-
HDMI_TX1+
HDMI_TX1-
HDMI_TX2+
HDMI_TX2-
HDMI_CLK-
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D2-
HDMI_R_D2+
HDMI_R_D1+
HDMI_R_D1-
HDMI_R_D0+
HDMI_R_D0-
HDMI_R_CK+
HDMI_R_CK-
HDMI_SCLK
HDMI_SDATA
HDMI_HPDHDMI_CLK+
HDMI_CLK+
HDMICLK_UMA<11>
HDMIDAT_UMA<11>
HPD <11>
TMDS_B_CLK<10>
TMDS_B_CLK#<10>
TMDS_B_DATA0<10>
TMDS_B_DATA0#<10>
TMDS_B_DATA1<10>
TMDS_B_DATA1#<10>
TMDS_B_DATA2<10>
TMDS_B_DATA2#<10>
+HDMI_5V_OUT+3VS
+5VS +HDMI_5V_OUT
+HDMI_5V_OUT
+3VS
+HDMI_5V_OUT
+5VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
HDMI
Custom
18 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
MP:Update D10 to meet HDMI.
L
Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P
HDMI Connector
03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
1/19 Use one mos to instead of two dule MOS design
v0.2 ADD
v0.2 ADD
C804 0.1U_0402_16V7K
1 2
R1018
0_0402_5%
@
1 2
R210
6.8K_0402_5%
Q134B
2N7002DW-7-F_SOT363-6
3
5
4
G
D
S
Q173
2N7002_SOT23-3
2
13
R307
715_0402_1%
12
R209
4.7K_0402_5%
1 2
R115 0_0402_5%@
1 2
L88
WCM-2012-900T_4P
1
1
4
433
22
R120 0_0402_5%@
1 2
L86
WCM-2012-900T_4P
1
1
4
433
22
R118 0_0402_5%@
1 2
R173
715_0402_1%
1 2
C468
0.1U_0402_16V4Z
1
2
R113 0_0402_5%@
1 2
U39
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R615
2.2K_0402_5%
12
R236
6.8K_0402_5%
R119 0_0402_5%@
1 2
R139
715_0402_1%
1 2
C852 0.1U_0402_16V7K
1 2
R117 0_0402_5%@
1 2
D10
RB491D_SOT23
2 1
R112 0_0402_5%@
1 2
C655 0.1U_0402_16V7K
1 2
L87
WCM-2012-900T_4P
1
1
4
433
22
R315
715_0402_1%
1 2
R1104
100K_0402_5%
1 2
Q134A
2N7002DW-7-F_SOT363-6
61
2
R141
715_0402_1%
1 2
C507 0.1U_0402_16V7K
1 2
C827 0.1U_0402_16V7K
1 2
C850
0.1U_0402_16V4Z
1
2R1019
0_0402_5%
@
1 2
JHDMI
SUYIN_100042MR019S153ZLCONN@
D2+
1
GND 2
D2-
3D1+
4
GND 5
D1-
6D0+
7
GND 8
D0-
9CK+
10
GND 11
CK-
12
CEC 13
Reserved 14
SCL
15 SDA
16
DDC/CEC_GND 17
+5V
18
HP_DET
19
GND 20
GND 21
GND 22
GND 23
R628
100K_0402_5%
1 2
C508 0.1U_0402_16V7K
1 2
C853 0.1U_0402_16V7K
1 2
C675 0.1U_0402_16V7K
1 2
R176
4.7K_0402_5%
12
R297
715_0402_1%
1 2
R304
715_0402_1%
1 2
C851
0.1U_0402_16V4Z
1
2
R172
715_0402_1%
1 2
L85
WCM-2012-900T_4P
1
1
4
433
22
R116 0_0402_5%@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLK_PCI_SIO_R PCI_CLK3
CPU_LDT_REQ#
PLT_RST#
NB_RST#_R
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
CPU_LDT_REQ#
H_PROCHOT#
NB_RST#_R
SB_32KHI
SB_32KHO
NB_RST#_R
+SB_PCIEVDD
PCI_PIRQH#
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
CLK_PCI_EC_R
LPCCLK1
H_PROCHOT#
SB_32KHI
SB_32KHO
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
H_PW RGD
CLK_PCI_EC
LPCCLK1 CLK_PCI_SIO
CLK_PCI_SIO2
CLK_PCI_SIO
CLK_PCI_EC
H_PW RGD_SB
PCI_CLK3 <23>
PCI_CLK5 <23>
PLT_RST# <11,14,25,26,27,32,33>
PCI_CLK4 <23>
PCICLK2 <23>SB_RX0P<10>
SB_RX0N<10>
SB_RX1P<10>
SB_RX1N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX0P<10>
SB_TX0N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>
SB_RX2P<10>
SB_RX2N<10>
SB_RX3P<10>
SB_RX3N<10>
RTC_CLK <23>
LPC_FRAME# <32,33>
LPC_AD1 <32,33>
LPC_AD2 <32,33>
LPC_AD0 <32,33>
LPC_AD3 <32,33>
LDT_STOP#<6,11>
CPU_LDT_REQ#<6,11>
H_PROCHOT#<6>
SIRQ <32,33>
CLK_SBSRC_BCLK<15>
CLK_SBSRC_BCLK#<15>
LDT_RST#<6>
ACCEL_INT <30>
PCI_AD23 <23>
PCI_SERR# <33>
PCI_AD24 <23>
PCI_AD25 <23>
PCI_AD26 <23>
PCI_AD27 <23>
PCI_AD28 <23>
H_PW RGD_CPU<6>
H_PW RGD<43>
LPC_DRQ# <32>
CLK_PCI_EC <23,33>
LPCCLK1 <23>
CLK_PCI_SIO <32>
H_PW RGD<43>
CLK_14M_SB<15>
+RTCVCC
+SB_VBAT
+1.8VS
+3VALW
+RTCBATT
+3VL
+3VS
+PCIE_VDDR
+1.2V_HT
+SB_VBAT +RTCVCC_R
+RTCBATT_R
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
SB710-PCIE/PCI/ACPI/LPC/RTC
Custom
19 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
W=20mils
EC & Debug
STRAP PIN
STRAP PIN
Check AMD need pull low or not
W=20mils
W=20mils
Close to SB
Close to SB
9/20 S A00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH
9/20 S P020008T00
01/23 14.318MHz for SB710 reference
R1107 0_0402_5%
1 2
R305 562_0402_1%
12
R311
0_0402_5%
1 2
C497 0.1U_0402_16V7K
1 2
T15PAD
U16
NC7SZ08P5X_NL_SC70-5@
B
2
A
1Y4
P5
G
3
C643
18P_0402_50V8J
1 2
C496 0.1U_0402_16V7K
1 2
L53
BLM18PG121SN1D_0603
1 2
C506
0.1U_0402_16V4Z@
12
C510
1U_0402_6.3V4Z
1
2
C504
10U_0805_10V4Z
1
2
R308 33_0402_5%
1 2
C1086 12P_0402_50V8J
1 2
R301 0_0402_5%
1 2
C492 0.1U_0402_16V7K
1 2
R1079
0_0402_5%
1 2
C494 0.1U_0402_16V7K
1 2
R876
1K_0402_5%
1 2
C495 0.1U_0402_16V7K
1 2
C498 0.1U_0402_16V7K
1 2
Y3
32.768KHZ_12.5PF_Q13MC14610050_10PPM
OSC
4
OSC
1
NC 3
NC 2
PCI EXPRESS IN TERFACE
Part 1 of 5
SB700
PCI INTER FACE
L PC
RTC
C P U
RTC XTAL
PC I CLKS
CL O CK GENERATOR
U15A
218-0660011 A14 SB7_FCBGA528
A_RST#
N2
PCIE_RX2P
R20
PCIE_RX2N
R21
PCIE_RX3P
R18
PCIE_TX3N
T22 PCIE_TX3P
T23 PCIE_TX2N
U24 PCIE_TX2P
U25
PCIE_RX1P
U19
PCIE_RX1N
V19
PCIE_RX0P
U22
PCIE_RX0N
U21
PCIE_TX1N
V25 PCIE_TX1P
V24 PCIE_TX0N
V22 PCIE_TX0P
V23
PCIE_RCLKP/NB_LNK_CLKP
N25
PCIE_RCLKN/NB_LNK_CLKN
N24
PCIE_CALRP
T25
PCIE_CALRN
T24
PCIE_PVDD
P24
GPP_CLK1N
L19
X1
A3
X2
B3
VBAT B2
GPP_CLK0N
J18
GPP_CLK2P
M19
ALLOW_LDTSTP
F23
CPU_HT_CLKN
M18
GPP_CLK2N
M20
SLT_GFX_CLKP
M23
CPU_HT_CLKP
P17
LDT_RST#
G24
PCICLK0 P4
PCICLK1 P3
PCICLK2 P1
PCICLK3 P2
PCIRST# N1
CBE0# W2
CBE1# U7
CBE2# AA7
CBE3# Y1
FRAME# AA6
DEVSEL# W5
IRDY# AA5
TRDY# Y5
PAR U6
STOP# W6
PERR# W4
REQ0# AC3
REQ1# AD4
REQ2# AB7
REQ3#/GPIO70 AE6
GNT0# AD2
GNT1# AE4
GNT2# AD5
GNT3#/GPIO72 AC6
SERR# V7
CLKRUN# AD6
LAD0 H24
LAD1 H23
LAD2 J25
LAD3 J24
LFRAME# H25
LDRQ0# H22
SERIRQ V15
PCICLK4 T4
LPCCLK0 G22
LPCCLK1 E22
AD0 U2
AD1 P7
AD2 V4
AD3 T1
AD4 V3
AD5 U1
AD6 V1
AD7 V2
AD8 T2
AD9 W1
AD10 T9
AD12 R7
AD13 R5
AD14 U8
AD15 U5
AD16 Y7
AD17 W8
AD18 V9
AD19 Y8
AD20 AA8
AD21 Y4
AD22 Y3
AD23 Y2
AD24 AA2
AD25 AB4
AD26 AA1
AD27 AB3
AD28 AB2
AD29 AC1
AD30 AC2
AD31 AD1
AD11 R6
REQ4#/GPIO71 AB6
GNT4#/GPIO73 AE5
LDRQ1#/GNT5#/GPIO68 AB8
GPP_CLK1P
L20
RTCCLK C3
PCIE_RX3N
R17
INTE#/GPIO33 AD3
INTF#/GPIO34 AC4
INTG#/GPIO35 AE2
INTH#/GPIO36 AE3
LOCK# V5
PCIE_PVSS
P25
PCICLK5/GPIO41 T3
BMREQ#/REQ5#/GPIO65 AD7
NB_HT_CLKP
M24
LDT_PG
F22
LDT_STP#
G25
GPP_CLK3N
P22
INTRUDER_ALERT# C2
NB_DISP_CLKP
K23
25M_48M_66M_OSC
L18
GPP_CLK0P
J19
NB_HT_CLKN
M25
SLT_GFX_CLKN
M22
GPP_CLK3P
N22
14M_X1
J21
14M_X2
J20
NB_DISP_CLKN
K22
PROCHOT#
F24
R316
120_0402_5%
1 2
C652
18P_0402_50V8J
1 2
C505
1U_0402_6.3V4Z
1
2
J1
JUMP_43X39@
1
122
R389
20M_0402_5%
12
R317
120_0402_5%
1 2
R312 33_0402_5%
12
R1109 1K_0402_5%@
12
C1087 12P_0402_50V8J
1 2
R302 33_0402_5%
1 2
R306 2.05K_0402_1%
12
R314 20M_0402_5%@
1 2
R967 0_0402_5%
12
T16PAD
R1108 0_0402_5%@
12
R319 10K_0402_5%
12
T18PAD
C509
0.1U_0402_16V4Z
1
2
C499 0.1U_0402_16V7K
1 2
C493 0.1U_0402_16V7K
1 2
T17PAD
R300 8.2K_0402_5%@
1 2
R318 10K_0402_5%@
12
D42
DAN202U_SC70
2
3
1JBATT1
ACES_85205-02001CONN@
1
1
2
2
GND
3
GND
4
C1085 12P_0402_50V8J@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NBPW RGD
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_P7
USB20_N7
USB20_N11
USB20_P11
USB20_P10
USB20_N10
USB20_N8
USB20_P8
SMB_CK_DAT1
SMB_CK_CLK1
SUS_STAT#
H_THERMTRIP#
USB_RCOMP
SMB_CK_CLK0
SMB_CK_DAT0
SUS_STAT#
HDA_SDIN1
HDA_SDIN0
HDA_SDOUT
HDABITCLK
HDA_SYNC
HDARST#
SB_TEST2
SB_TEST1
SB_TEST0
SB_TEST2
SB_TEST1
SB_TEST0
SMB_CK_DAT0
SMB_CK_CLK0
SMB_CK_CLK1
SMB_CK_DAT1
EC_RSMRST#
EXP_CPPE#
NBPW RGD
PCIE_WAKE#
PCIE_WAKE#
CR_CPPE#
SB_GPIO5
HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDABITCLK
HDA_BITCLK
HDA_BITCLK
EC_RSMRST#
EC_LID_OUT#<33>
EC_SCI#<33>
USB20_N0 <31>
USB20_P0 <31>
USB20_N1 <31>
USB20_P1 <31>
USB20_P2 <31>
USB20_N2 <31>
USB20_P3 <35>
USB20_N3 <35>
USB20_N5 <17>
USB20_P5 <17>
USB20_N6 <31>
USB20_P6 <31>
USB20_P7 <31>
USB20_N7 <31>
USB20_N11 <26>
USB20_P11 <26>
USB20_P10 <26>
USB20_N10 <26>
USB20_N8 <26>
USB20_P8 <26>
HDARST#<23,33>
SMB_CK_DAT1<26>
SMB_CK_CLK1<26>
EC_RSMRST#<33>
SMB_CK_DAT0<8,9,15,30>
SMB_CK_CLK0<8,9,15,30>
H_THERMTRIP#<6>
SB_SPKR<28>
CLK_48M_USB <15>
SUS_STAT#<11>
HDA_SDIN0<28>
HDA_SDIN1<34>
HDA_SDOUT_MDC<34>
HDA_SDOUT_CODEC<28>
HDA_BITCLK_CODEC<28>
HDA_BITCLK_MDC<34>
HDA_SYNC_MDC<34>
HDA_SYNC_CODEC<28>
HDA_RST#_CODEC<28>
HDA_RST#_MDC<34>
SLP_S3#<33>
SLP_S5#<33>
PWRBTN_OUT#<33>
SB_PWRGD<6,33,43>
KB_RST#<33>
GATEA20<33>
EC_SMI#<33>
GPIO16 <23>
GPIO17 <23>
EXP_CPPE#<26>
NB_PWRGD<11>
LAN_PCIE_WAKE#<25>
MINI_PCIE_WAKE#<26>
CR_CPPE#<27>
3/5V_OK<39,41>
+3VS
+3VALW
+3VALW
+3VS
+3VALW
+3VS
+3VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4117P
0.3
SB710 USB/AC97
Custom
20 56Monday, March 16, 2009
2007/08/02 2008/08/02
Compal Electronics, Inc.
Touch Screen (delete)
STRAP PIN
USB-0 Right side (S/W Debug Port)
USB-7 Fingerprint
USB-5 USB Camera
USB-10 MiniCard(TV or WWAN)
USB-4 Left side
STRAP PIN
USB-2 Left Side
USB-6 Bluetooth
SB700 has internal PD
USB-3 Dock
USB-1 Right side
USB-11 New Card
USB-8 MiniCard(WLAN)
USB-9 Card Reader (delete)
STRAP PIN
demo circuit LID use RI#
For SB700 A11 divider to
1.8V for RS & RX780
03/05 Add SSC circuit for HDA_BITCLK.
R81 0_0402_5%
1 2
C1122
0.1U_0402_16V4Z
@1
2
R321 2.2K_0402_5%@
1 2
R1081
10K_0402_5%
@
12
R1082
10K_0402_5%
@
12
R32311.8K_0402_1%
1 2
U66
ASM3P623S00BF-08TR_TSSOP8
@
CLKOUT
6
VDD
7
NC 2
CLKIN 1
NC 8
SS 3
SSON
5
GND
4
C1089 82P_0402_50V8J
1 2
C1091 82P_0402_50V8J
1 2
R339 33_0402_5%
1 2
R337 33_0402_5%
1 2
R322 2.2K_0402_5%@
1 2
R82 0_0402_5%
1 2
R540
10K_0402_5%
1 2
R320 2.2K_0402_5%@
1 2
R83
10K_0402_5%
1 2
R331 2.2K_0402_5%
1 2
R340 33_0402_5%
1 2
USB 2.0
Part 4 of 5
SB700
ACPI / WAKE UP EVENTS
GPIO
HD AUDIO
US B OC
USB 1.1
USB M ISC
INTEGRATED uC
INTEGRATED uC
U15D
218-0660011 A14 SB7_FCBGA528
USBCLK/14M_25M_48M_OSC C8
USB_RCOMP G8
USB_OC6#/IR_TX1/GEVENT6#
B9
USB_HSD5P C12
USB_HSD5N D12
USB_HSD4P B12
USB_HSD4N A12
USB_HSD3P G12
USB_HSD3N G14
USB_HSD2P H14
USB_HSD2N H15
USB_HSD1P A13
USB_HSD1N B13
USB_HSD0P B14
USB_HSD0N A14
USB_OC4#/IR_RX0/GPM4#
A8
USB_OC3#/IR_RX1/GPM3#
A9
USB_OC1#/GPM1#
F8 USB_OC2#/GPM2#
E5
USB_HSD7P G11
USB_HSD7N H12
USB_HSD6P E12
USB_HSD6N E14
USB_OC0#/GPM0#
E4
DDR3_RST#/GEVENT7#
G5
SATA_IS0#/GPIO10
AE18
AZ_SDIN3/GPIO46
M3
PCI_PME#/GEVENT4#
E1
RI#/EXTEVNT0#
E2
SLP_S3#
F5
SLP_S5#
G1
PWR_BTN#
H2
PWR_GOOD
H1
SUS_STAT#
K3
TEST1
H4
TEST0
H3
GA20IN/GEVENT0#
Y15
KBRST#/GEVENT1#
W15
SMBALERT#/THRMTRIP#/GEVENT2#
J6
LPC_PME#/GEVENT3#
K4
LPC_SMI#/EXTEVNT1#
K24
S3_STATE/GEVENT5#
F1
SYS_RESET#/GPM7#
J2
WAKE#/GEVENT8#
H6
RSMRST#
D3
CLK_REQ3#/SATA_IS1#/GPIO6
AD18
NB_PWRGD
W14
SMARTVOLT1/SATA_IS2#/GPIO4
AA19
SMARTVOLT2/SHUTDOWN#/GPIO5
Y19
SPKR/GPIO2
W21
SCL0/GPOC0#
AA18
SDA0/GPOC1#
W18
DDC1_SCL/GPIO9
AA20
DDC1_SDA/GPIO8
Y18
AZ_BITCLK
M1
AZ_SDOUT
M2
AZ_SYNC
L6
AZ_RST#
M4
USB_HSD9P A11
USB_HSD9N B11
USB_HSD8P C10
USB_HSD8N D10
LLB#/GPIO66
C1
AZ_DOCK_RST#/GPM8#
L5
SLP_S2/GPM9#
H7
USB_OC5#/IR_TX0/GPM5#
B8
BLINK/GPM6#
F2
SCL1/GPOC2#
K1
SDA1/GPOC3#
K2
TEST2
H5
CLK_REQ0#/SATA_IS3#/GPIO0
W17
AZ_SDIN2/GPIO44
L8 AZ_SDIN1/GPIO43
J8 AZ_SDIN0/GPIO42
J7
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
V17
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
W20
USB_FSD13P E6
USB_FSD13N E7
USB_FSD12P F7
USB_FSD12N E8
USB_HSD11P H11
USB_HSD11N J10
USB_HSD10P E11
USB_HSD10N F11
KSO_17 B18
IMC_PWM0/IMC_GPIO10 F21
SCL2/IMC_GPIO11 D21
SDA2/IMC_GPIO12 F19
SCL3_LV/IMC_GPIO13 E20
SDA3_LV/IMC_GPIO14 E21
IMC_PWM1/IMC_GPIO15 E19
IMC_PWM2/IMC_GPO16 D19
IMC_PWM3/IMC_GPO17 E18
KSI_0 G20
KSI_1 G21
KSI_2 D25
KSI_3 D24
KSI_4 C25
KSI_5 C24
KSI_6 B25
KSI_7 C23
PS2_DAT
H19
PS2_CLK
H20
SPI_CS2#/IMC_GPIO2
H21
IDE_RST#/F_RST#/IMC_GPO3
F25
PS2KB_DAT
D22
PS2KB_CLK
E24
PS2M_DAT
E25
PS2M_CLK
D23
KSO_16 A18
KSO_0 B24
KSO_1 B23
KSO_2 A23