Compal LA 5752P Schematics. Www.s Manuals.com. R0.3 Schematics

User Manual: Motherboard Compal LA-5752P NIWE2 Arrandale - Schematics. Free.

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

LA-5752P

0.3

Cover Sheet

Custom

1 51Thursday, October 29, 2009

2008/03/25 2008/04/

Compal Electronics,Ltd.

REV:0.3

Compal Confidential

Arrandale

with Intel IBEX PEAK-M core logic

NIWE2

Schematics Document

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Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

MB Block Diagram

Custom

2 51Thursday, October 29, 2009

2008/03/24 2008/04/

Compal Electronics, Inc.

LA-5752P

File Name :

Compal confidential

SPI ROM

SPI ROM

BIOS

page13

CAP SENSOR BD:LS-5752P

VOLUME UP

VOLUME DOWN

MUTE

AUDIO ENHANCE

BUTTON & LED

ESATA HDD AND USB CONN

page38

HDMI

USB PORT X1(Left)

page37

page32

37.5mm*37.5mm

25mm*25mm

USB(WWAN)

SATA HDD CONN

SATA ODD CONN

DDR3-1067(1.5V)

Card Reader/Audio Jack SB

CONN

RTL8111DL-VB-GR

ICS9LRS3199AKLFT

6*PCI-E BUS

page28

PCI Express

Mini card Slot 1

CARD READER BD:

LS-5753P

RTS5138

HP JACK

MIC JACK

10/100/1G LAN

USB CONN X1(Right)

page37

level shift IC

page25

ASM1442

FDI *8

100MHz

2.7GT/s

intel

DDR3*4

6*SATA serial

UP TO 8G

NVidia N11M-GE1

Realtek 5138

MS/MS

pro/SD/SD

pro/mmc/XD

Analog MIC_Int

page33

HP X 1+

MIC_Ext X1

New Card X1

page28

WWAN

page28

SIM Card

PCI-E X16

page28

page28

page32

page37

POWER BD: LS-5754P

POWER BT

NOVO BT

POWER MANAGE BT

(UMA/DIS)

BlueTooth CONN

CMOS Camera

Conexant

CX20671

Audio Codec

2Channel Speaker

LPC BUS

CRT Connector

AZALIA

RJ45 CONN Int.KBD

ENE KB926D

Touch Pad

BANK 0, 1, 2, 3

DDR3-SO-DIMM X2

DDR3-800(1.5V)

Dual Channel

14*USB2.0

LVDS

Connector

EC

page26

page27

page29

page30

page34

page35 page36

page35

page37

page27

page33

page33

page 10,11

Clock Generator

page12

page5~9

page 13~18

Arrandale

Socket-rPGA989

DMI *4

FCBGA 951

Intel Ibex Peak M

VRAM 64*16

page20

page19~23

CONN

page24

PCI Express

Mini card Slot 2

Z Z Z

15.6W_PCB_LA5752P

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

MB Notes List

B

3 51Thursday, October 29, 2009

2008/03/24 2008/04/

Compal Electronics, Inc.

LA-5752P

O

X

S3

+3VS

X

X

+3VALW

+5VS

O

+CPU_CORE

OO

X

X X

+VCCP

power

plane

O

O

O

O

X

S5 S4/ Battery only

X X X

+B

State

+1.5VS

+1.5V

S5 S4/AC & Battery

don't exist

S5 S4/AC

+5VALW

S0

O

O

+VGA_CORE

+1.8VS

DDR3 Voltage Rails

+0.75VS

Cap sensor

board

X

X

XX

NEW

CARD PCH

X X

X

X

N10x

Thermal

Sensor

X

X

X

SML0CLK

SML0DATA PCH

X

+3VS

X X

SMB_EC_CK2

SOURCE

KB926

RAM

M2

BATT KE926 SODIMM CLK CHIP

SMBUS Control Table

SMBCLK

SMBDATA PCH

WLAN

WWAN

SMB_EC_DA2

SMB_EC_CK1

SMB_EC_DA1

N10x

XV

V V

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

KB926

SML1CLK

SML1DATA PCH

XXX X X X X X

1 0 1 0 0 1 0 0A4

I2C / SMBUS ADDRESSING

1 0 1 0 0 0 0 0

D2

A0

CLOCK GENERATOR (EXT.)

HEX

DDR SO-DIMM 1

ADDRESS

DDR SO-DIMM 0

1 1 0 1 0 0 1 0

DEVICE

5

BT

3G

6

4

CMOS

RIGHT SIDE

RIGHT SIDE0

DEVICEPORT

3

2

11

NEW CARD

USB PORT LIST

WIRELESS8

10

1WLAN

NEW CARD

CARD READER

3G

9

7

LAN

LEFT SIDE

6

4

DEVICEPORT

5

3

2

PCIE PORT LIST

1

12

13

7

8

+1.05VS

X

V

X

+3VALW

+3VALW

+3VALW

+3VALW

+3VALW

+3VALW

+3VALW

V

+3VALW

X X

+3VALW

V

+3VS

+3VS

V

+3VS

V

V

+3VS

LEFT SIDE

10M@

11M@

FOR 10M CHIP

FOR 11M CHIP

100@ 10/100 LAN

BT@ Blue Tooth

ESATA@

UMA@

DIS@

UMA only (Arranddale)

HU@

HD@

SWITCHABLE or UMA only

SWITCHABLE or DIS only

SKU

Arrandale(dGPU)

Arrandale(iGPU)

Arrandale(iGPU+dGPU)

DIS@ / 100@ for EVT

UMA@ / 100@ for EVT

VGA@+HD@+HU@+HYBRID@

DIS only

UMA only

SWITCHABLE

DIS only (Arranddale)

HYBRID@ FOR SWITCHABLE

@ FUNCTION

45@

X76@

GIGA@

UMA_HDMI@

HDMI@

3G@

GIGA LAN

FOR UMA HDMI components

FOR HDMI components

3G(WWAN) function

(X76 BOM)

(45 BOM)

EVT NON-USE

VGA@ FOR NVIDIA PART

CMOS@

ESATA function

Camera function

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

VGA Notes List

B

4 51Thursday, October 29, 2009

2009/03/16 2010/03/15

Compal Electronics, Inc.

LA-5752P

(+3VS)

FBVDDQ

(+VGA_CORE)

(1.05VS)

tNVVDD

PEX_VDD can ramp up any time

VDD33

NVVDD

The ramp time for any rail must be more than 40us

(1.5VS)

Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

IN

OUT

OUT

OUT

OUT

OUT

OUT

I/O

OUT

OUT

I/O

IN

OUT

OUT

Panel Back-Light brightness(PWM capable)

Panel Power Enable

Panel Back-Light On/Off (PWM)

GPU VID0

GPU VID1

GPU VID2

Thermal Catastrophic Overtemp

Thermal Alert

Memory VREF switch

SLI raster sync

AC power detect pin

MEM_VID orPower supply control

N/A

-

H

H

H

L

L

Hot plug detect for IFP link C

GPIO I/O ACTIVE Function Description

N/A

-

-

-

L

-

-

- Power supply control

IN

OUT

IN

IN

IN

IN

IN

IN

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

-

-

-

-

-

-

-

-

Hot plug detect for IFP Link E

Programmable Fan Control

Hot plug detect for IFP link F

SLI swap ready signal

I/O

Products

GPU Mem NVCLK

/MCLK NVVDD FBVDD FBVDDQ PCI Express I/O and

PLLVDD I/O and

PLLVDD Other

(3.3V)(1.05V)(1.8V)

(1.05V)

(1.5V)(1.5V) (GPU+Mem)

(4) (1,5) (6)

(V) (A) (W) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

N10P-GS

N10P-GE

128bit

1024MB

DDR3

128bit

1024MB

DDR3

21.07

(W) (W)

20.97

128bit

N10P-LP

1024MB

DDR3

15.48

6.67

6.73

6.44

(MHz)

TBD

TBD

TBD

TBD

TBD

TBD

18.25

19.17

13.95

17.34

17.25

11.86

2.06

2.03

1.90

3.09

3.05

2.85

4.09

3.99

6.14

5.99

850 75 0.14

63 0.07

55 0.18

4.09 6.14

0.89

0.85

0.88840

810

75 0.14

75 0.14

63 0.07

63 0.07

55 0.18

55 0.18

Products

GPU Mem NVCLK

/MCLK NVVDD FBVDD FBVDDQ PCI Express I/O and

PLLVDD I/O and

PLLVDD Other

(3.3V)(1.05V)(1.8V)

(1.05V)

(1.5V)(1.5V) (GPU+Mem)

(4) (1,5) (6)

(V) (A) (W) (A) (W)

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

N10M-GE

64bit

512MB

DDR3

13.36

(W) (W)

14.29

8.28

2.93

3.10

2.91

(MHz)

TBD

TBD

TBD

TBD

TBD

TBD

11.89

11.53

6.60

10.70

11.53

5.61

0.66

0.70

0.62

0.99

1.05

0.93

2.16

2.20

3.24

3.3

792 75 0.14

63 0.07

100 0.33

2.28 3.42

0.83

0.82

0.86817

782

75 0.14

75 0.14

63 0.07

63 0.07

64bit

N10M-GS

512MB

DDR3

64bit

N10M-LP

512MB

DDR3

100 0.33

100 0.33

Hot plug detect for IFP Link D

PEX_VDD

(1.8VS)IFPAB_IOVDD

tNV-IFPAB_IOVDD

tNV-FBVDDQ

Power Sequence

0 1

12

0.85V 12

GPIO6

P-State

0,10

GPU_VID1 GPU_VID0 VGA_CORE

0.8V

1 0

00

0.9V

GPIO5 N10M-GS N10P-GS

1 1 1.0V (N10M-GS)

0.925V (N10P-GS)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDP_TRST#

XDP_TDO

CO MP3

CO MP2

CO MP1

CO MP0

TP_ SKTOCC#

H_PECI_IS O

H_THE RMTRIP#

H_P M_S YNC_R

V CC P WR GOOD _0

V DD PW R GOOD _R

PLT_RST#_R

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

PM_EXTTS#0

PM_EXTTS#1

PM_EXTTS#0

SM_RCOMP0

SM_RCOMP1

H _ CPUR ST #_R

SM_RCOMP2

PM_EXTTS#1

CLK_C PU_BCLK #

CLK_EXP#

CLK_EXP

C LK _CPU_ BCLK

XDP _PREQ#

XDP_TDI

XDP_TMS

XDP_TCK

H _C AT ERR#

V CC P WR GOOD _1

XDP_BPM#3

XDP_BPM#4

XDP_BPM#0

XDP_BPM#2

XDP_BPM#5

XDP_BPM#1

XDP_BPM#6

XDP_BPM#7

H _P RO CHO T#

XDP _DBRESET#

XDP _PREQ#

XDP_TMS

XDP_TDO

XDP_TDI

XDP _DBRESET#

XDP_TCK

XDP_TRST#

DRA M_P WRGD

DRAMRS T_CNTRL_R

DRAMRST# SM _DRAMRST#

SM_D RAMRST#

VTT_POK

CLK_C PU_I TP#

CLK_C PU_I TP

XDP _PRDY#

VCCP_P OK

S3_0. 75V_EN

V DD PW R GOOD _R

CLK_C PU_BCLK # <16>

C LK _C P U_B C LK <16 >

CLK_EXP# <14>

CLK_EXP <14>

H _ PE CI<16 >

H _P R OC HO T#<3 4, 48>

H _ PM _S Y NC<1 5>

H_THE RMTRIP#<16>

PM_DRA M _PWRGD<15>

BUF_PLT_RST#<16,19, 28,29>

H _C P UP W R GD<1 6>

PM_EXTTS#1_R <10,11>

VCCP_P OK<46>

DRAMRS T_CNTRL_EC<34>

DRAMRST#<10,11>

DRAMRS T_CNTRL_P CH<16>

VCCP_P OK<46>

S3_0. 75V_EN <44>

+ V CC P

+ V CC P

+ V CC P

+ V CC P

+3VS

+3VALW

+1.5V

+5VALW

+1.5V

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.3

Arrandale(1/5)-Thermal/XDP

C us t om

5 51Thurs day , Oc tober 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

Layout Note:Please these

resistors near Processor

DDR3 Compensation Signals

Layout rule 10mil width trace

length < 0.5", spacing 20mil

pins unused by

Clarksfield on the

rPGA989 Package

CHECK INTEL DOCUMENT #385422

Debug Port Design Guide Rev1.3

5

EC GPIO CONTROL

6

PCH GPIO CONTROL

DDR3 CONNECTER

3

3

For Intel S3 Power Reduction.

For Intel S3 Power Reduction.

FROM POWER VTT

POWER GOOD SIGNAL

R 1 87

0_0402_5%

1 2

R 1 37

1K _0402_5%@

1 2

R 5 69 68 _0 40 2_5%

12

R 13 8 51 _0 402_ 1%@

1 2

R 5 66 24 .9 _0 402_ 1%

1 2

R 3 01

1K _0402_1%

1 2

R 2 81 0_ 04 02_ 5%

1 2

R 6 10

10K_0402_5%

12

R 5 5749 .9 _0 402 _1%

1 2

R 1 90

0_0402_5%

1 2

C 33 8

0.01U_0402_16V7K

1

2

G

D

S

Q27

2N7002_SOT23

2

1 3

R 5 4849 .9 _0 402 _1%

1 2

R 1 95

1.5K_ 0402_1%

1 2

R 1 91

0_0402_5%

1 2

G

D

S

Q42

2N7002_SOT23

2

13

R 18 6

750_0402_1%

12

R 5 67 10 0_ 04 02_1%

1 2

R 2 82 0_ 04 02_ 5%@

1 2

R 5 65 13 0_ 04 02_1%

1 2

T18 P AD

R 56 4 0_ 04 02_5 %

1 2

R 18 4

1K _0402_1%

12

R 5 6020 _0 402 _1%

1 2

R57 51_0 402_1%@

1 2

R 19 2

3K _0402_1%

@

12

R 55 6 51 _0 402_ 1%@

1 2

R 19 3

1.1K_ 0402_1%

@

12

R 2 83 1 00 K_ 040 2_5%

12

R 1 3568 _0 40 2_5%

12

U8

MC74V HC1G08DFT 2G S C70 5P

B

2

A

1Y4

P5

G

3

R 1 85

1.5K_ 0402_5%

1 2

R555 0_0402_5%

12

R 5 61 10 K _04 02_5%

1 2

R 16 349 .9 _0 402_ 1%

12

R3000_0402_5%

@

1 2

T17 P AD

R 5 5820 _0 402 _1%

1 2

R 13 4 51 _0 402_ 5%

1 2

R 13 6 51 _0 402_ 1%@

1 2

R 5 62 10 K _04 02_5%

1 2

T19 P A D

CLOCKS

MISC THERMAL PWR MANAGEMENT

DDR3

MISC

JTAG & BPM

J C PU 1B

I C, A UB _CF D_ rP G A, R1 P0

ME@

SM_RCOMP[1] AM1

SM_RCOMP[2] AN1

SM_DRAMRST# F6

SM_RCOMP[0] AL1

BCLK# B16

BCLK A16

BCLK_ITP# AT30

BCLK_ITP AR30

PEG_CLK# D16

PEG_CLK E16

DPLL_REF_SSCLK# A17

DPLL_REF_SSCLK A18

CATERR#

AK14

COMP3

AT23

PECI

AT15

PROCHOT#

AN26

THERMTRIP#

AK15

RESET_OBS#

AP26

VCCPWRGOOD_1

AN14

VCCPWRGOOD_0

AN27

SM_DRAMPWROK

AK13

VTTPWRGOOD

AM15

RSTIN#

AL14

PM_EXT_TS#[0] AN15

PM_EXT_TS#[1] AP15

PRDY# AT28

PREQ# AP27

TCK AN28

TMS AP28

TRST# AT27

TDI AT29

TDO AR27

TDI_M AR29

TDO_M AP29

DBR# AN25

BPM#[0] AJ22

BPM#[1] AK22

BPM#[2] AK24

BPM#[3] AJ24

BPM#[4] AJ25

BPM#[5] AH22

BPM#[6] AK23

BPM#[7] AH23

COMP2

AT24

PM_SYNC

AL15

TAPPWRGOOD

AM26

COMP1

G16

COMP0

AT26

SKTOCC#

AH24

R 18 3

560_0402_5%

1 2

R 19 4

750_0402_1%

12

R 5 63 0_ 04 02_ 5%

1 2

R 13 3 51 _0 402_ 5%

1 2

R 1 39

0_0402_5%

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG0

CFG7

CFG4

CFG3

CFG0

CFG3

EXP_ICOMPI

EXP_RBIAS

CFG4

H_R SVD 17_R

H_R SVD 18_R

RS VD64_ R

RS VD65_ R

FDI_CT X_PRX_N0

FDI_CT X_PRX_N1

FDI_CT X_PRX_N2

FDI_CT X_PRX_N3

FDI_CT X_PRX_N4

FDI_CT X_PRX_N5

FDI_CT X_PRX_N6

FDI_CT X_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P1

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

FDI_CTX_PRX_P4

FDI_CTX_PRX_P5

FDI_CTX_PRX_P6

FDI_CTX_PRX_P7

FDI_LS Y NC0

F DI _F S YN C 0

FDI_LS Y NC1

F DI _F S YN C 1

F DI _IN T

F DI _F S YN C 0

FDI_LS Y NC1

F DI _F S YN C 1

F DI _IN T

FDI_LS Y NC0

PCIE_CRX_GTX_N15

PCIE_CRX_GTX_N10

PCIE_CRX_GTX_N14

PCIE_CRX_GTX_N0

PCIE_CRX_GTX_N8

PCIE_CRX_GTX_N6

PCIE_CRX_GTX_N7

PCIE_CRX_GTX_N4

PCIE_CRX_GTX_N3

PCIE_CRX_GTX_N9

PCIE_CRX_GTX_N12

PCIE_CRX_GTX_N13

PCIE_CRX_GTX_N5

PCIE_CRX_GTX_N2

PCIE_CRX_GTX_N1

PCIE_CRX_GTX_N11

PCI E_CRX_GTX_P15

PCI E_CRX_GTX_P14

PCIE_CRX_GTX_P8

PCIE_CRX_GTX_P4

PCIE_CRX_GTX_P0

PCI E_CRX_GTX_P10

PCIE_CRX_GTX_P7

PCIE_CRX_GTX_P9

PCI E_CRX_GTX_P13

PCIE_CRX_GTX_P6

PCIE_CRX_GTX_P3

PCI E_CRX_GTX_P12

PCIE_CRX_GTX_P5

PCI E_CRX_GTX_P11

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2

PCIE_CTX_GRX_C_P0

PCIE_CTX_GRX_C_P10

PCIE_CTX_GRX_C_P15

PCIE_CTX_GRX_C_P14

PCIE_CTX_GRX_C_P8

PCIE_CTX_GRX_C_P6

PCIE_CTX_GRX_C_P4

PCIE_CTX_GRX_C_P13

PCIE_CTX_GRX_C_P7

PCIE_CTX_GRX_C_P1

PCIE_CTX_GRX_C_P9

PCIE_CTX_GRX_C_P12

PCIE_CTX_GRX_C_P3

PCIE_CTX_GRX_C_P5

PCIE_CTX_GRX_C_P2

PCIE_CTX_GRX_C_P11

PCIE_CTX_GRX_C_N14

PCIE_CTX_GRX_C_N15

PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_N10

PCIE_CTX_GRX_C_N6

PCIE_CTX_GRX_C_N8

PCIE_CTX_GRX_C_N13

PCIE_CTX_GRX_C_N4

PCIE_CTX_GRX_C_N9

PCIE_CTX_GRX_C_N5

PCIE_CTX_GRX_C_N2

PCIE_CTX_GRX_C_N12

PCIE_CTX_GRX_C_N7

PCIE_CTX_GRX_C_N1

PCIE_CTX_GRX_C_N11

PCIE_CTX_GRX_C_N3

PCIE_CTX_GRX_N15

PCIE_CTX_GRX_N0

PCIE_CTX_GRX_N14

PCIE_CTX_GRX_N10

PCIE_CTX_GRX_N6

PCIE_CTX_GRX_N8

PCIE_CTX_GRX_N13

PCIE_CTX_GRX_N4

PCIE_CTX_GRX_N9

PCIE_CTX_GRX_N5

PCIE_CTX_GRX_N2

PCIE_CTX_GRX_N12

PCIE_CTX_GRX_N7

PCIE_CTX_GRX_N1

PCIE_CTX_GRX_N11

PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_P0

PCI E_CTX_GRX_P10

PCI E_CTX_GRX_P15

PCI E_CTX_GRX_P14

PCIE_CTX_GRX_P3

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P4

PCI E_CTX_GRX_P13

PCIE_CTX_GRX_P2

PCI E_CTX_GRX_P11

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P9

PCI E_CTX_GRX_P12

DMI_CTX_PRX_P0<15>

DMI_CRX_PTX_P0<15>

DM I_CTX_PRX_N1<15>

DM I_CRX_PTX_N1<15>

DMI_CTX_PRX_P3<15>

DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_P2<15>

DM I_CTX_PRX_N0<15>

DM I_CRX_PTX_N3<15>

DMI_CRX_PTX_P2<15>

DM I_CTX_PRX_N3<15>

DMI_CTX_PRX_P1<15>

DM I_CRX_PTX_N0<15>

DM I_CRX_PTX_N2<15>

DMI_CRX_PTX_P1<15>

DM I_CTX_PRX_N2<15>

PCIE_CTX_GRX_P[0..15] <19>

PCIE_CTX_GRX_N[0..15] <19>

PCIE_CRX_ GTX_N[0..15] < 19>

PCIE_CRX_ GTX_P[0..15] <19>

FDI_CTX_PRX_N0<15>

FDI_CTX_PRX_N1<15>

FDI_CTX_PRX_N2<15>

FDI_CTX_PRX_N3<15>

FDI_CTX_PRX_N4<15>

FDI_CTX_PRX_N5<15>

FDI_CTX_PRX_N6<15>

FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>

FDI_CTX_PRX_P1<15>

FDI_CTX_PRX_P2<15>

FDI_CTX_PRX_P3<15>

FDI_CTX_PRX_P4<15>

FDI_CTX_PRX_P5<15>

FDI_CTX_PRX_P6<15>

FDI_CTX_PRX_P7<15>

FDI_FS Y N C 0<15>

FDI_FS Y N C 1<15>

F D I_ I NT<15 >

F DI _ LS Y NC 0<15>

F DI _ LS Y NC 1<15>

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.3

Arrandale(2/5)-DMI/PEG/FDI

C us t om

6 51Thurs day , Oc tober 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

CFG Straps for PROCESSOR

0: Bifurcation enabled

Not applicable for Clarksfield Processor

1: Single PEG

CFG0

PCI-Express Configuration Select

0: Lane Numbers Reversed

1: Normal Operation

CFG3

CFG3-PCI Express Static Lane Reversal

15 -> 0, 14 ->1, .....

Layout rule trace

length < 0.5"

CFG[1:0] 11=1*16 PEG

10=2*8 PEG

FOR ES1 SAMPLE ONLY

0: Enabled; An external Display Port

1: Disabled; No Physical Display Port

CFG4

CFG4-Display Port Presence

attached to Embedded Display Port

device is connected to the Embedded

Display Port

VGA@

PCIE Lane Numbers Reversed

CFG3-PCI Express Static Lane Reversal

C 5 61 0. 1U _0 40 2_10 V6K

1 2

C 5 65 0. 1U _0 40 2_10 V6K

1 2

RESERVED

J C PU 1E

I C, A UB _CF D_ rP G A, R1 P0

ME@

CFG[0]

AM30

CFG[1]

AM28

CFG[2]

AP31

CFG[3]

AL32

CFG[4]

AL30

CFG[5]

AM31

CFG[6]

AN29

CFG[7]

AM32

CFG[8]

AK32

CFG[9]

AK31

CFG[10]

AK28

CFG[11]

AJ28

CFG[12]

AN30

CFG[13]

AN32

CFG[14]

AJ32

CFG[15]

AJ29

CFG[16]

AJ30

CFG[17]

AK30

RSVD34 AH25

RSVD35 AK26

RSVD38 AJ26

RSVD_NCTF_42 AT3

RSVD39 AJ27

RSVD_NCTF_40 AP1

RSVD_NCTF_41 AT2

RSVD_NCTF_43 AR1

RSVD_TP_86

H16

RSVD45 AL28

RSVD46 AL29

RSVD47 AP30

RSVD48 AP32

RSVD49 AL27

RSVD50 AT31

RSVD51 AT32

RSVD52 AP33

RSVD53 AR33

RSVD_NCTF_54 AT33

RSVD_NCTF_55 AT34

RSVD_NCTF_56 AP35

RSVD_NCTF_57 AR35

RSVD58 AR32

RSVD_NCTF_30

C35

RSVD_NCTF_31

B35

RSVD_NCTF_28

A34

RSVD_NCTF_29

A33

RSVD27

J28 RSVD26

J29

RSVD16

A19 RSVD15

B19

RSVD17

A20

RSVD18

B20

RSVD20

T9 RSVD19

U9

RSVD22

AB9 RSVD21

AC9

RSVD_NCTF_23

C1

RSVD_NCTF_24

A3

RSVD_TP_66 AA5

RSVD_TP_67 AA4

RSVD_TP_68 R8

RSVD_TP_71 AA2

RSVD_TP_72 AA1

RSVD_TP_73 R9

RSVD_TP_69 AD3

RSVD_TP_74 AG7

RSVD_TP_70 AD2

RSVD_TP_75 AE3

RSVD_TP_76 V4

RSVD_TP_77 V5

RSVD_TP_78 N2

RSVD_TP_81 W3

RSVD_TP_82 W2

RSVD_TP_83 N3

RSVD_TP_79 AD5

RSVD_TP_84 AE5

RSVD_TP_80 AD7

RSVD_TP_85 AD9

RSVD36 AL26

RSVD_NCTF_37 AR2

RSVD1

AP25

RSVD2

AL25

RSVD3

AL24

RSVD4

AL22

RSVD5

AJ33

RSVD6

AG9

RSVD7

M27

RSVD8

L28

SA_DIMM_VREF

J17

SB_DIMM_VREF

H17

RSVD11

G25

RSVD12

G17

RSVD13

E31

RSVD14

E30

RSVD32 AJ13

RSVD33 AJ12

RSVD_TP_59 E15

RSVD_TP_60 F15

KEY A2

RSVD62 D15

RSVD63 C15

RSVD64 AJ15

RSVD65 AH15

VSS AP34

R61 3.01K_0402_1%

1 2

C 5 57 0. 1U _0 40 2_10 V6K

1 2

R 54 5 75 0_ 0402 _1%

1 2

R 5 32 1K _ 040 2_5%D I S@

1 2

C 5 27 0. 1U _0 40 2_10 V6K

1 2

C 5 47 0. 1U _0 40 2_10 V6K

1 2

R 5 47

0_0402_5%

@

1 2

C 5 62 0. 1U _0 40 2_10 V6K

1 2

R 5 36 1K _ 040 2_5%D I S@

1 2

R58 3.01K_0402_1%

@

1 2

R 5 33 1K _ 040 2_5%D I S@

1 2

C 5 41 0. 1U _0 40 2_10 V6K

1 2

C 5 36 0. 1U _0 40 2_10 V6K

1 2

C 5 35 0. 1U _0 40 2_10 V6K

1 2

C 5 60 0. 1U _0 40 2_10 V6K

1 2

C 5 59 0. 1U _0 40 2_10 V6K

1 2

C 5 33 0. 1U _0 40 2_10 V6K

1 2

R 5 35 1K _ 040 2_5%D I S@

1 2

R 18 8

0_0402_5%

@

12

R 5 46

0_0402_5%

@

1 2

C 5 43 0. 1U _0 40 2_10 V6K

1 2

R 54 4 49 .9 _0 402_ 1%

1 2

C 5 32 0. 1U _0 40 2_10 V6K

1 2

C 5 42 0. 1U _0 40 2_10 V6K

1 2

R 18 9

0_0402_5%

@

12

C 5 34 0. 1U _0 40 2_10 V6K

1 2

C 5 40 0. 1U _0 40 2_10 V6K

1 2

C 5 58 0. 1U _0 40 2_10 V6K

1 2

C 5 46 0. 1U _0 40 2_10 V6K

1 2

C 5 56 0. 1U _0 40 2_10 V6K

1 2

C 5 30 0. 1U _0 40 2_10 V6K

1 2

C 5 48 0. 1U _0 40 2_10 V6K

1 2

C 5 55 0. 1U _0 40 2_10 V6K

1 2

R 5 34 1K _ 040 2_5%D I S@

1 2

C 5 44 0. 1U _0 40 2_10 V6K

1 2

C 5 49 0. 1U _0 40 2_10 V6K

1 2

PCI EXPRESS -- GRAPHICS

DMI Intel(R) FDI

J C PU 1A

I C, A UB _CF D_ rP G A, R1 P0

ME@

DMI_RX#[0]

A24

DMI_RX#[1]

C23

DMI_RX#[2]

B22

DMI_RX#[3]

A21

DMI_RX[0]

B24

DMI_RX[1]

D23

DMI_RX[2]

B23

DMI_RX[3]

A22

DMI_TX#[0]

D24

DMI_TX#[1]

G24

DMI_TX#[2]

F23

DMI_TX#[3]

H23

DMI_TX[0]

D25

DMI_TX[1]

F24

DMI_TX[3]

G23 DMI_TX[2]

E23

FDI_TX#[0]

E22

FDI_TX#[1]

D21

FDI_TX#[2]

D19

FDI_TX#[3]

D18

FDI_TX#[4]

G21

FDI_TX#[5]

E19

FDI_TX#[6]

F21

FDI_TX#[7]

G18

FDI_TX[0]

D22

FDI_TX[1]

C21

FDI_TX[2]

D20

FDI_TX[3]

C18

FDI_TX[4]

G22

FDI_TX[5]

E20

FDI_TX[6]

F20

FDI_TX[7]

G19

FDI_FSYNC[0]

F17

FDI_FSYNC[1]

E17

FDI_INT

C17

FDI_LSYNC[0]

F18

FDI_LSYNC[1]

D17

PEG_ICOMPI B26

PEG_ICOMPO A26

PEG_RBIAS A25

PEG_RCOMPO B27

PEG_RX#[0] K35

PEG_RX#[1] J34

PEG_RX#[2] J33

PEG_RX#[3] G35

PEG_RX#[4] G32

PEG_RX#[5] F34

PEG_RX#[6] F31

PEG_RX#[7] D35

PEG_RX#[8] E33

PEG_RX#[9] C33

PEG_RX#[10] D32

PEG_RX#[11] B32

PEG_RX#[12] C31

PEG_RX#[13] B28

PEG_RX#[14] B30

PEG_RX#[15] A31

PEG_RX[0] J35

PEG_RX[1] H34

PEG_RX[2] H33

PEG_RX[3] F35

PEG_RX[4] G33

PEG_RX[5] E34

PEG_RX[6] F32

PEG_RX[7] D34

PEG_RX[8] F33

PEG_RX[9] B33

PEG_RX[10] D31

PEG_RX[11] A32

PEG_RX[12] C30

PEG_RX[13] A28

PEG_RX[14] B29

PEG_RX[15] A30

PEG_TX#[0] L33

PEG_TX#[1] M35

PEG_TX#[2] M33

PEG_TX#[3] M30

PEG_TX#[4] L31

PEG_TX#[5] K32

PEG_TX#[6] M29

PEG_TX#[7] J31

PEG_TX#[8] K29

PEG_TX#[9] H30

PEG_TX#[10] H29

PEG_TX#[11] F29

PEG_TX#[12] E28

PEG_TX#[13] D29

PEG_TX#[14] D27

PEG_TX#[15] C26

PEG_TX[0] L34

PEG_TX[1] M34

PEG_TX[2] M32

PEG_TX[3] L30

PEG_TX[4] M31

PEG_TX[5] K31

PEG_TX[6] M28

PEG_TX[7] H31

PEG_TX[8] K28

PEG_TX[9] G30

PEG_TX[10] G29

PEG_TX[11] F28

PEG_TX[12] E27

PEG_TX[13] D28

PEG_TX[14] C27

PEG_TX[15] C25

C 5 50 0. 1U _0 40 2_10 V6K

1 2

C 5 63 0. 1U _0 40 2_10 V6K

1 2

C 5 45 0. 1U _0 40 2_10 V6K

1 2

C 5 64 0. 1U _0 40 2_10 V6K

1 2

R 59

3.01K _0402_1%

@

1 2

R60 3.01K_0402_1%

@

1 2

C 5 28 0. 1U _0 40 2_10 V6K

1 2

C 5 29 0. 1U _0 40 2_10 V6K

1 2

C 5 31 0. 1U _0 40 2_10 V6K

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

D DR _ A_ D63

D DR _ A_ D62

DDR_A _D8

DDR_A _D3

DDR_A _D4

DDR_A _D7

DDR_A _D5

DDR_A _D6

D DR _ A_ D59

D DR _ A_ D58

D DR _ A_ D57

D DR _ A_ D56

D DR _ A_ D47

D DR _ A_ D46

D DR _ A_ D42

D DR _ A_ D43

D DR _ A_ D34

D DR _ A_ D39

D DR _ A_ D44

D DR _ A_ D45

D DR _ A_ D35

D DR _ A_ D41

D DR _ A_ D40

D DR _ A_ D38

D DR _ A_ D36

D DR _ A_ D37

D DR _ A_ D32

D DR _ A_ D33

D DR _ A_ D61

D DR _ A_ D60

DDR_A _D2

DDR_A _D1

DDR_A _D0

D DR _ A_ D55

D DR _ A_ D54

D DR _ A_ D51

D DR _ A_ D48

D DR _ A_ D50

D DR _ A_ D49

D DR _ A_ D52

D DR _ A_ D53

D DR _ A_ D31

D DR _ A_ D14

D DR _ A_ D15

D DR _ A_ D25

D DR _ A_ D24

D DR _ A_ D26

D DR _ A_ D27

D DR _ A_ D30

DDR_A _D9

D DR _ A_ D13

D DR _ A_ D12

D DR _ A_ D10

D DR _ A_ D11

D DR _ A_ D29

D DR _ A_ D28

D DR _ A_ D19

D DR _ A_ D20

D DR _ A_ D16

D DR _ A_ D21

D DR _ A_ D17

D DR _ A_ D22

D DR _ A_ D18

D DR _ A_ D23

DD R_ A_DQ S# 7

DD R_ A_DQ S# 0

DD R_ A_DQ S# 2

DD R_ A_DQ S# 5

DD R_ A_DQ S# 3

DD R_ A_DQ S# 1

DD R_ A_DQ S# 4

DD R_ A_DQ S# 6

DD R_ A_DM 7

DD R_ A_DM 2

DD R_ A_DM 5

DD R_ A_DM 4

DD R_ A_DM 1

DD R_ A_DM 6

DD R_ A_DM 3

DD R_ A_DM 0

DDR_A _MA5

DDR_A _MA0

DDR_A _MA9

DDR_A _MA14

DDR_A _MA11

DDR_A _MA4

DDR_A _MA7

DDR_A _MA6

DDR_A _MA10

DDR_A _MA1

DDR_A _MA12

DDR_A _MA2

DDR_A _MA13

DDR_A _MA3

DDR_A _MA8

DDR_B _D3

D DR _ B_ D51

D DR _ B_ D56

DDR_B _D9

D DR _ B_ D31

D DR _ B_ D39

D DR _ B_ D49

D DR _ B_ D54

D DR _ B_ D57

D DR _ B_ D24

D DR _ B_ D10

DDR_B _D1

DDR_B _D6

D DR _ B_ D44

D DR _ B_ D43

D DR _ B_ D20

D DR _ B_ D42

D DR _ B_ D55

D DR _ B_ D15

D DR _ B_ D34

D DR _ B_ D23

D DR _ B_ D60

D DR _ B_ D33

D DR _ B_ D11

D DR _ B_ D41

D DR _ B_ D45

DDR_B _D0

D DR _ B_ D48

D DR _ B_ D50

D DR _ B_ D38

D DR _ B_ D21

D DR _ B_ D32

D DR _ B_ D22

DDR_B _D4

D DR _ B_ D14

D DR _ B_ D27

D DR _ B_ D25

D DR _ B_ D62

D DR _ B_ D59

D DR _ B_ D19

D DR _ B_ D52

DDR_B _D7

DDR_B _D5

D DR _ B_ D17

D DR _ B_ D58

D DR _ B_ D30

D DR _ B_ D26

D DR _ B_ D36

D DR _ B_ D13

D DR _ B_ D53

D DR _ B_ D18

DDR_B _D8

D DR _ B_ D35

D DR _ B_ D46

D DR _ B_ D12

D DR _ B_ D47

D DR _ B_ D28

DDR_B _D2

D DR _ B_ D37

D DR _ B_ D63

D DR _ B_ D40

D DR _ B_ D29

D DR _ B_ D61

D DR _ B_ D16

DDR_A _MA15

DDR _A _DQS 0

DDR _A _DQS 2

DDR _A _DQS 1

DDR _A _DQS 6

DDR _A _DQS 5

DDR _A _DQS 4

DDR _A _DQS 3

DDR _A _DQS 7

DDR_B _MA0

DDR_B _MA9

DDR_B _MA7

DDR_B _MA13

DDR_B _MA2

DDR_B _MA4

DDR_B _MA11

DDR_B _MA3

DDR_B _MA5

DDR_B _MA6

DDR_B _MA10

DDR_B _MA8

DDR_B _MA1

DDR_B _MA12

DDR_B _MA14

DDR_B _MA15

DD R_ B_DQ S# 1

DD R_ B_DQ S# 7

DD R_ B_DQ S# 5

DD R_ B_DQ S# 4

DD R_ B_DQ S# 0

DD R_ B_DQ S# 3

DD R_ B_DQ S# 6

DD R_ B_DQ S# 2

DDR _B _DQS 7

DDR _B _DQS 0

DDR _B _DQS 1

DDR _B _DQS 5

DDR _B _DQS 4

DDR _B _DQS 3

DDR _B _DQS 2

DDR _B _DQS 6

DD R_ B_DM 3

DD R_ B_DM 1

DD R_ B_DM 5

DD R_ B_DM 0

DD R_ B_DM 6

DD R_ B_DM 7

DD R_ B_DM 4

DD R_ B_DM 2

DDR_A _MA[ 0..15] <10>

D DR _ A _DM [ 0.. 7] <1 0>

D DR _A _D [0. .6 3]<1 0>

D DR _A _B S 0<10 >

D DR _A _B S 1<10 >

D DR _A _B S 2<10 >

D DR _ A _W E #<10 >

D D R_ A_ RA S#<10 >

D D R_ A_ CA S#<10 >

DDR_B _MA[ 0..15] <11>

D DR _ B _DM [ 0.. 7] < 11>

D DR _B _B S 0<11 >

D DR _B _B S 1<11 >

D DR _B _B S 2<11 >

D DR _ B _W E#<11 >

D D R_ B_ RA S#<11 >

D D R_ B_ CA S#<11 >

D DR _B _D [0. .6 3]<1 1>

M _C LK _DD R0 <10>

M_CLK _DDR#0 < 10>

DDR_CKE0_DI MMA <10>

M _C LK _DD R1 <10>

M_CLK _DDR#1 < 10>

DDR_CKE1_DI MMA <10>

DDR_CS0_DIM MA# <10>

DDR_CS1_DIM MA# <10>

M_ODT0 <10>

M_ODT1 <10>

M_ODT2 <11>

M_ODT3 <11>

DDR_CS2_DIM MB# < 11>

DDR_CS3_DIM MB# < 11>

D DR _ B _D QS [ 0.. 7] < 11>

D DR _ A _DQ S #[ 0.. 7] <1 0>

D DR _ A _DQ S [0 ..7 ] <10 >

D DR _ B _DQ S #[ 0.. 7] < 11>

M _C LK _DD R2 <11>

M _C LK _DD R#2 <11>

DDR_CKE2_DI MMB <11>

M _C LK _DD R3 <11>

M _C LK _DD R#3 <11>

DDR_CKE3_DI MMB <11>

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

Arrandale(3/5)-DDR III

C us t o m

7 5 1Thurs day , Oc tober 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

DDR SYSTEM MEMORY A

JCP U 1 C

I C, A UB _CF D_ rP G A, R1 P0

ME@

SA_BS[0]

AC3

SA_BS[1]

AB2

SA_BS[2]

U7

SA_CAS#

AE1

SA_RAS#

AB3

SA_WE#

AE9

SA_CK[0] AA6

SA_CK[1] Y6

SA_CK#[0] AA7

SA_CK#[1] Y5

SA_CKE[0] P7

SA_CKE[1] P6

SA_CS#[0] AE2

SA_CS#[1] AE8

SA_ODT[0] AD8

SA_ODT[1] AF9

SA_DM[0] B9

SA_DM[1] D7

SA_DM[2] H7

SA_DM[3] M7

SA_DM[4] AG6

SA_DM[5] AM7

SA_DM[6] AN10

SA_DM[7] AN13

SA_DQS[0] C8

SA_DQS#[0] C9

SA_DQS[1] F9

SA_DQS#[1] F8

SA_DQS[2] H9

SA_DQS#[2] J9

SA_DQS[3] M9

SA_DQS#[3] N9

SA_DQS[4] AH8

SA_DQS#[4] AH7

SA_DQS[5] AK10

SA_DQS#[5] AK9

SA_DQS[6] AN11

SA_DQS#[6] AP11

SA_DQS[7] AR13

SA_DQS#[7] AT13

SA_MA[0] Y3

SA_MA[1] W1

SA_MA[2] AA8

SA_MA[3] AA3

SA_MA[4] V1

SA_MA[5] AA9

SA_MA[6] V8

SA_MA[7] T1

SA_MA[8] Y9

SA_MA[9] U6

SA_MA[10] AD4

SA_MA[11] T2

SA_MA[12] U3

SA_MA[13] AG8

SA_MA[14] T3

SA_MA[15] V9

SA_DQ[0]

A10

SA_DQ[1]

C10

SA_DQ[2]

C7

SA_DQ[3]

A7

SA_DQ[4]

B10

SA_DQ[5]

D10

SA_DQ[6]

E10

SA_DQ[7]

A8

SA_DQ[8]

D8

SA_DQ[9]

F10

SA_DQ[10]

E6

SA_DQ[11]

F7

SA_DQ[12]

E9

SA_DQ[13]

B7

SA_DQ[14]

E7

SA_DQ[15]

C6

SA_DQ[16]

H10

SA_DQ[17]

G8

SA_DQ[18]

K7

SA_DQ[19]

J8

SA_DQ[20]

G7

SA_DQ[21]

G10

SA_DQ[22]

J7

SA_DQ[23]

J10

SA_DQ[24]

L7

SA_DQ[25]

M6

SA_DQ[26]

M8

SA_DQ[27]

L9

SA_DQ[28]

L6

SA_DQ[29]

K8

SA_DQ[30]

N8

SA_DQ[31]

P9

SA_DQ[32]

AH5

SA_DQ[33]

AF5

SA_DQ[34]

AK6

SA_DQ[35]

AK7

SA_DQ[36]

AF6

SA_DQ[37]

AG5

SA_DQ[38]

AJ7

SA_DQ[39]

AJ6

SA_DQ[40]

AJ10

SA_DQ[41]

AJ9

SA_DQ[42]

AL10

SA_DQ[43]

AK12

SA_DQ[44]

AK8

SA_DQ[45]

AL7

SA_DQ[46]

AK11

SA_DQ[47]

AL8

SA_DQ[48]

AN8

SA_DQ[49]

AM10

SA_DQ[50]

AR11

SA_DQ[51]

AL11

SA_DQ[52]

AM9

SA_DQ[53]

AN9

SA_DQ[54]

AT11

SA_DQ[55]

AP12

SA_DQ[56]

AM12

SA_DQ[57]

AN12

SA_DQ[58]

AM13

SA_DQ[59]

AT14

SA_DQ[60]

AT12

SA_DQ[61]

AL13

SA_DQ[62]

AR14

SA_DQ[63]

AP14

DDR SYSTEM MEMORY - B

JCP U 1 D

I C, A UB _CF D_ rP G A, R1 P0

ME@

SB_BS[0]

AB1

SB_BS[1]

W5

SB_BS[2]

R7

SB_CAS#

AC5

SB_RAS#

Y7

SB_WE#

AC6

SB_CK[0] W8

SB_CK[1] V7

SB_CK#[0] W9

SB_CK#[1] V6

SB_CKE[0] M3

SB_CKE[1] M2

SB_CS#[0] AB8

SB_CS#[1] AD6

SB_ODT[0] AC7

SB_ODT[1] AD1

SB_DM[0] D4

SB_DM[1] E1

SB_DM[2] H3

SB_DM[3] K1

SB_DM[4] AH1

SB_DM[5] AL2

SB_DM[6] AR4

SB_DM[7] AT8

SB_DQS[4] AG2

SB_DQS#[4] AH2

SB_DQS[5] AL5

SB_DQS#[5] AL4

SB_DQS[6] AP5

SB_DQS#[6] AR5

SB_DQS[7] AR7

SB_DQS#[7] AR8

SB_DQS[0] C5

SB_DQS#[0] D5

SB_DQS[1] E3

SB_DQS#[1] F4

SB_DQS[2] H4

SB_DQS#[2] J4

SB_DQS[3] M5

SB_DQS#[3] L4

SB_MA[0] U5

SB_MA[1] V2

SB_MA[2] T5

SB_MA[3] V3

SB_MA[4] R1

SB_MA[5] T8

SB_MA[6] R2

SB_MA[7] R6

SB_MA[8] R4

SB_MA[9] R5

SB_MA[10] AB5

SB_MA[11] P3

SB_MA[12] R3

SB_MA[13] AF7

SB_MA[14] P5

SB_MA[15] N1

SB_DQ[0]

B5

SB_DQ[1]

A5

SB_DQ[2]

C3

SB_DQ[3]

B3

SB_DQ[4]

E4

SB_DQ[5]

A6

SB_DQ[6]

A4

SB_DQ[7]

C4

SB_DQ[8]

D1

SB_DQ[9]

D2

SB_DQ[10]

F2

SB_DQ[11]

F1

SB_DQ[12]

C2

SB_DQ[13]

F5

SB_DQ[14]

F3

SB_DQ[15]

G4

SB_DQ[16]

H6

SB_DQ[17]

G2

SB_DQ[18]

J6

SB_DQ[19]

J3

SB_DQ[20]

G1

SB_DQ[21]

G5

SB_DQ[22]

J2

SB_DQ[23]

J1

SB_DQ[24]

J5

SB_DQ[25]

K2

SB_DQ[26]

L3

SB_DQ[27]

M1

SB_DQ[28]

K5

SB_DQ[29]

K4

SB_DQ[30]

M4

SB_DQ[31]

N5

SB_DQ[32]

AF3

SB_DQ[33]

AG1

SB_DQ[34]

AJ3

SB_DQ[35]

AK1

SB_DQ[36]

AG4

SB_DQ[37]

AG3

SB_DQ[38]

AJ4

SB_DQ[39]

AH4

SB_DQ[40]

AK3

SB_DQ[41]

AK4

SB_DQ[42]

AM6

SB_DQ[43]

AN2

SB_DQ[44]

AK5

SB_DQ[45]

AK2

SB_DQ[46]

AM4

SB_DQ[47]

AM3

SB_DQ[48]

AP3

SB_DQ[49]

AN5

SB_DQ[50]

AT4

SB_DQ[51]

AN6

SB_DQ[52]

AN4

SB_DQ[53]

AN3

SB_DQ[54]

AT5

SB_DQ[55]

AT6

SB_DQ[56]

AN7

SB_DQ[57]

AP6

SB_DQ[58]

AP8

SB_DQ[59]

AT9

SB_DQ[60]

AT7

SB_DQ[61]

AP9

SB_DQ[62]

AR10

SB_DQ[63]

AT10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCSENS E

VSS SENSE

VCCSENS E

VSS SENSE

H_V ID 1

H_V ID 4

H_V ID 3

H_V ID 5

VCC_S E NSE

H_V ID 2

PM_DPRS LPVR_R

H_V ID 0

VSS _SENSE

H_V ID 6

VTT_SELECT

GFX _IMON

GFX _IMON

GFX _VR_EN

GFX _VR_EN

SUS P

1.5V_ DDR3_GATE

PSI# <48>

H _V I D [0 .. 6] <48>

P RO C_ DP RSLP VR <48>

IM V P_IMON <48>

VTT_SENSE <46>

V CC SE NS E <48>

VSS SENSE <48>

VTT_SELECT <46>

GFX VR_IMON <47>

GFX VR_DPRSLPVR <47>

GFX VR_EN <47>

GFX VR_VID_0 < 47>

GFX VR_VID_1 < 47>

GFX VR_VID_3 < 47>

GFX VR_VID_2 < 47>

GFX VR_VID_4 < 47>

GFX VR_VID_5 < 47>

GFX VR_VID_6 < 47>

VSS_AXG_SENSE <47>

VCC_A XG_SENSE <47>

SUS P<39,44,45>

+ CP U _CO RE

+ C PU _C OR E

+ V CC P

+ V CC P

+ V CC P

+ 1. 5V _D DR 3

+ V CC P

+1.8VS

+ V CC P

+ V CC P

+V CCP

+G FX_CORE

+1.5V

+ 1. 5V _D DR 3

+1 .5 V + 1. 5V _D DR 3

+5VALW

+ 1 .5 V_ DD R3

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.3

Arrandale(4/5)-PWR

C us t om

8 51Thurs day , Oc tober 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

CPU

H_VTTVID1 = Low, 1.1V FOR Clarksfiel

H_VTTVID1 = High, 1.05V FOR Auburndale

48A 15A18A

3A

0.6A

Close to CPU

BUT A SMALL AMOUNT OF POWER

(~15MW) MAYBE WASTED

DESIGN GUIDE REV1.1

AS NO CONNECT

2

1

1

For Intel S3 Power Reduction.

For Intel S3 Power Reduction.

Modify for cost revew.

09/16/2009

POWER

GRAPHICS VIDs

GRAPHICS

DDR3 - 1.5V RAILS

FDI PEG & DMI

SENSE

LINES

1.1V1.8V

J C PU 1G

IC ,AUB _CFD_rPGA, R1P 0

ME@

GFX_VID[0] AM22

GFX_VID[1] AP22

GFX_VID[2] AN22

GFX_VID[3] AP23

GFX_VID[4] AM23

GFX_VID[5] AP24

GFX_VID[6] AN24

GFX_VR_EN AR25

GFX_DPRSLPVR AT25

GFX_IMON AM24

VAXG_SENSE AR22

VSSAXG_SENSE AT22

VAXG1

AT21

VAXG2

AT19

VAXG3

AT18

VAXG4

AT16

VAXG5

AR21

VAXG6

AR19

VAXG7

AR18

VAXG8

AR16

VAXG9

AP21

VAXG10

AP19

VAXG11

AP18

VAXG12

AP16

VAXG13

AN21

VAXG14

AN19

VAXG15

AN18

VAXG16

AN16

VAXG17

AM21

VAXG18

AM19

VAXG19

AM18

VAXG20

AM16

VAXG21

AL21

VAXG22

AL19

VAXG23

AL18

VAXG24

AL16

VAXG25

AK21

VAXG26

AK19

VAXG27

AK18

VAXG28

AK16

VAXG29

AJ21

VAXG30

AJ19

VAXG31

AJ18

VAXG32

AJ16

VAXG33

AH21

VAXG34

AH19

VAXG35

AH18

VAXG36

AH16

VTT1_45

J24

VTT1_46

J23

VTT1_47

H25

VTT1_48

K26

VTT1_49

J27

VTT1_50

J26

VTT1_51

J25

VTT1_52

H27

VTT1_53

G28

VTT1_54

G27

VTT1_55

G26

VTT1_56

F26

VTT1_57

E26

VTT1_58

E25

VDDQ1 AJ1

VDDQ2 AF1

VDDQ3 AE7

VDDQ4 AE4

VDDQ5 AC1

VDDQ6 AB7

VDDQ7 AB4

VDDQ8 Y1

VDDQ9 W7

VDDQ10 W4

VDDQ11 U1

VDDQ12 T7

VDDQ13 T4

VDDQ14 P1

VDDQ15 N7

VDDQ16 N4

VDDQ17 L1

VDDQ18 H1

VTT0_59 P10

VTT0_60 N10

VTT0_61 L10

VTT0_62 K10

VCCPLL1 L26

VCCPLL2 L27

VCCPLL3 M26

VTT1_63 J22

VTT1_64 J20

VTT1_65 J18

VTT1_66 H21

VTT1_67 H20

VTT1_68 H19

R56 0_04 02_5%

1 2

C 1 60

22U_0805_6.3V6M

@

1

2

C 2 73

10U_0805_10V4K

1

2

G

D

S

Q23

2N7002_SOT23

2

13

C 2 58

22U_0805_6.3V6M

1

2

G

D

S

Q19

BSS 138_NL_SOT23-3

2

13

C 2 15

10U_0805_10V4K

1

2

C 2 16

10U_0805_10V4K

@

1

2

C 21 8

10U_0805_10V4K

1

2

+

C 5 54

330U_D2_2.5VY_R9M

1

2

C 2 07

10U_0805_10V4K

1

2

C 2 89

0.1U_0402_10V6K

1

2

C 2 52

22U_0805_6.3V6M

1

2

C 1 82

10U_0805_10V4K

1

2

C 25 7

1U_0603_10V4Z

1

2

T15P AD

@

C 2 72

10U_0805_10V4K

1

2

C 2 08

10U_0805_10V4K

1

2

+

C 2 68

220U_B2_2.5VM_R35

@

1

2

C 2 40

10U_0805_10V4K

1

2

R 2 67

0_0402_5%

@

1 2

R 2 68

20K_0402_5%

C 21 3

10U_0805_10V4K

1

2

C 16 7

1U_0603_10V4Z

1

2

C 18 9

22U_0805_6.3V6M

UM A@

1

2

C 1 91

22U_0805_6.3V6M

@

1

2

C 2 70

10U_0805_10V4K

@

1

2

C 16 8

2.2U_0603_6.3V4Z

1

2

R 55 9

0_0402_5%

D I S@

12

R 1 41 0_ 04 02_ 5%

UM A@

1 2

C 2 10

10U_0805_10V4K

1

2

R 55 1 1 00_ 040 2_1%

1 2

R 60 8 1K _0 40 2_5%

1 2

C 2 09

10U_0805_10V4K

1

2

U11

SI480 0BDY-T1-E3_SO8

S1

S2

S3

G4

D

8

D

7

D

6

D

5

R 14 0

4.7K_ 0402_5%

UM A@

1 2

C 2 19

10U_0805_10V4K

1

2

C 2 74

10U_0805_10V4K

1

2

C 25 3

1U_0603_10V4Z

1

2

C 14 9

1U_0603_10V4Z

1

2

C 25 6

1U_0603_10V4Z

1

2

C 1 98

10U_0805_10V4K

1

2

C 25 5

1U_0603_10V4Z

1

2

C 2 11

10U_0805_10V4K

1

2

C 16 9

10U_0805_10V4K

1

2

C 2 69

0.1U_0402_10V6K

@

1

2

C 5 91

10U_0805_6.3V6M

UM A@

1

2

C 2 01

10U_0805_10V4K

1

2

C 2 17

10U_0805_10V4K

1

2

C 2 88

0.1U_0402_10V6K

1

2

C 2 12

10U_0805_10V4K

1

2

C 2 71

10U_0805_10V4K

1

2

R 55 2 1 00_ 040 2_1%

1 2

C 17 0

4.7U_0603_6.3V6K

1

2

C 1 81

10U_0805_10V4K

1

2

R 55 3 0_ 04 02_5 %

1 2

R 55 4

0_0402_5%

1 2

J2

JUMP_43X118

@

11

2

2

R 1 32

1K _0402_5%

D I S@

12

C 25 4

1U_0603_10V4Z

1

2

C 2 86

0.1U_0402_10V6K

1

2

C 1 61

22U_0805_6.3V6M

@

1

2

C 1 59

22U_0805_6.3V6M

UM A@

1

2

C 19 0

22U_0805_6.3V6M

@

1

2

C 2 14

10U_0805_10V4K

1

2

C 1 99

10U_0805_10V4K

1

2

C 2 00

10U_0805_10V4K

1

2

J3

JUMP_43X118

@

11

2

2

C 2 87

0.1U_0402_10V6K

1

2

POWER

CPU CORE SUPPLY

1.1V RAIL POWER

SENSE LINES

CPU VIDS

JCP U 1 F

I C, A UB _CF D_ rP G A, R1 P0

ME@

ISENSE AN35

VTT_SENSE B15

PSI# AN33

VID[0] AK35

VID[1] AK33

VID[2] AK34

VID[3] AL35

VID[4] AL33

VID[5] AM33

VID[6] AM35

PROC_DPRSLPVR AM34

VTT_SELECT G15

VCC_SENSE AJ34

VSS_SENSE_VTT A15

VCC1

AG35

VCC2

AG34

VCC3

AG33

VCC4

AG32

VCC5

AG31

VCC6

AG30

VCC7

AG29

VCC8

AG28

VCC9

AG27

VCC10

AG26

VCC11

AF35

VCC12

AF34

VCC13

AF33

VCC14

AF32

VCC15

AF31

VCC16

AF30

VCC17

AF29

VCC18

AF28

VCC19

AF27

VCC20

AF26

VCC21

AD35

VCC22

AD34

VCC23

AD33

VCC24

AD32

VCC25

AD31

VCC26

AD30

VCC27

AD29

VCC28

AD28

VCC29

AD27

VCC30

AD26

VCC31

AC35

VCC32

AC34

VCC33

AC33

VCC34

AC32

VCC35

AC31

VCC36

AC30

VCC37

AC29

VCC38

AC28

VCC39

AC27

VCC40

AC26

VCC41

AA35

VCC42

AA34

VCC43

AA33

VCC44

AA32

VCC45

AA31

VCC46

AA30

VCC47

AA29

VCC48

AA28

VCC49

AA27

VCC50

AA26

VCC51

Y35

VCC52

Y34

VCC53

Y33

VCC54

Y32

VCC55

Y31

VCC56

Y30

VCC57

Y29

VCC58

Y28

VCC59

Y27

VCC60

Y26

VCC61

V35

VCC62

V34

VCC63

V33

VCC64

V32

VCC65

V31

VCC66

V30

VCC67

V29

VCC68

V28

VCC69

V27

VCC70

V26

VCC71

U35

VCC72

U34

VCC73

U33

VCC74

U32

VCC75

U31

VCC76

U30

VCC77

U29

VCC78

U28

VCC79

U27

VCC80

U26

VCC81

R35

VCC82

R34

VCC83

R33

VCC84

R32

VCC85

R31

VCC86

R30

VCC87

R29

VCC88

R28

VCC89

R27

VCC90

R26

VCC91

P35

VCC92

P34

VCC93

P33

VCC94

P32

VCC95

P31

VCC96

P30

VCC97

P29

VCC98

P28

VCC99

P27

VCC100

P26

VTT0_33 AF10

VTT0_34 AE10

VTT0_35 AC10

VTT0_36 AB10

VTT0_37 Y10

VTT0_38 W10

VTT0_39 U10

VTT0_40 T10

VTT0_41 J12

VTT0_42 J11

VTT0_1 AH14

VTT0_2 AH12

VTT0_3 AH11

VTT0_4 AH10

VTT0_5 J14

VTT0_6 J13

VTT0_7 H14

VTT0_8 H12

VTT0_9 G14

VTT0_10 G13

VTT0_11 G12

VTT0_12 G11

VTT0_13 F14

VTT0_14 F13

VTT0_15 F12

VTT0_16 F11

VTT0_17 E14

VTT0_18 E12

VTT0_19 D14

VTT0_20 D13

VTT0_21 D12

VTT0_22 D11

VTT0_23 C14

VTT0_24 C13

VTT0_25 C12

VTT0_26 C11

VTT0_27 B14

VTT0_28 B12

VTT0_29 A14

VTT0_30 A13

VTT0_31 A12

VTT0_32 A11

VSS_SENSE AJ35

VTT0_43 J16

VTT0_44 J15

C 32 5

0.1U_0603_25V7K

1

2

C 5 92

10U_0805_6.3V6M

UM A@

1

2

R 2 33

220_0402_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSS _NCTF7_R

VSS _NCTF5_R

VSS _NCTF3_R

VSS _NCTF2_R

VSS _NCTF1_R

VSS _NCTF6_R

VSS _NCTF4_R

+ C PU _C OR E

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.3

Arrandale(5/5)-GND/Bypass

C us t om

9 51Thurs day , Oc tober 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

470uF 4.5mohm

Under cavity

between Inductor and socket

CPU CORE

Inside cavity

C 16 2

10U_0805_6.3V6M

1

2

C 14 8

10U_0805_6.3V6M

1

2

C 5 84

22U_0805_6.3V6M

1

2

C 1 29

22U_0805_6.3V6M

1

2

C 16 3

10U_0805_6.3V6M

1

2

C 88

10U_0805_6.3V6M

1

2

C 90

22U_0805_6.3V6M

1

2

C 1 92

10U_0805_6.3V6M

1

2

C 5 79

22U_0805_6.3V6M

1

2

C 5 78

22U_0805_6.3V6M

1

2

C 91

22U_0805_6.3V6M

1

2

+

C 92

470U_D2T_2VM

1

2 3

C 19 4

10U_0805_6.3V6M

1

2

C 19 3

10U_0805_6.3V6M

1

2

+

C 76

470U_D2T_2VM

1

2 3

C 16 5

10U_0805_6.3V6M

1

2

C 5 83

22U_0805_6.3V6M

1

2

C 5 85

22U_0805_6.3V6M

1

2

VSS

NCTF

J C PU 1 I

I C, A UB _CF D_ rP G A, R1 P0

ME@

VSS161

K27

VSS162

K9

VSS163

K6

VSS164

K3

VSS165

J32

VSS166

J30

VSS167

J21

VSS168

J19

VSS169

H35

VSS170

H32

VSS171

H28

VSS172

H26

VSS173

H24

VSS174

H22

VSS175

H18

VSS176

H15

VSS177

H13

VSS178

H11

VSS179

H8

VSS180

H5

VSS181

H2

VSS182

G34

VSS183

G31

VSS184

G20

VSS185

G9

VSS186

G6

VSS187

G3

VSS188

F30

VSS189

F27

VSS190

F25

VSS191

F22

VSS192

F19

VSS193

F16

VSS194

E35

VSS195

E32

VSS196

E29

VSS197

E24

VSS198

E21

VSS199

E18

VSS200

E13

VSS201

E11

VSS202

E8

VSS203

E5

VSS204

E2

VSS205

D33

VSS206

D30

VSS207

D26

VSS208

D9

VSS209

D6

VSS210

D3

VSS211

C34

VSS212

C32

VSS213

C29

VSS214

C28

VSS215

C24

VSS216

C22

VSS217

C20

VSS218

C19

VSS219

C16

VSS220

B31

VSS221

B25

VSS222

B21

VSS223

B18

VSS224

B17

VSS225

B13

VSS226

B11

VSS227

B8

VSS228

B6

VSS229

B4

VSS230

A29

VSS_NCTF1 AT35

VSS_NCTF2 AT1

VSS_NCTF3 AR34

VSS_NCTF4 B34

VSS_NCTF5 B2

VSS_NCTF6 B1

VSS_NCTF7 A35

VSS231

A27

VSS232

A23

VSS233

A9

VSS

J C PU 1 H

IC ,AUB _CFD_rPGA, R1P 0

ME@

VSS1

AT20

VSS2

AT17

VSS3

AR31

VSS4

AR28

VSS5

AR26

VSS6

AR24

VSS7

AR23

VSS8

AR20

VSS9

AR17

VSS10

AR15

VSS11

AR12

VSS12

AR9

VSS13

AR6

VSS14

AR3

VSS15

AP20

VSS16

AP17

VSS17

AP13

VSS18

AP10

VSS19

AP7

VSS20

AP4

VSS21

AP2

VSS22

AN34

VSS23

AN31

VSS24

AN23

VSS25

AN20

VSS26

AN17

VSS27

AM29

VSS28

AM27

VSS29

AM25

VSS30

AM20

VSS31

AM17

VSS32

AM14

VSS33

AM11

VSS34

AM8

VSS35

AM5

VSS36

AM2

VSS37

AL34

VSS38

AL31

VSS39

AL23

VSS40

AL20

VSS41

AL17

VSS42

AL12

VSS43

AL9

VSS44

AL6

VSS45

AL3

VSS46

AK29

VSS47

AK27

VSS48

AK25

VSS49

AK20

VSS50

AK17

VSS51

AJ31

VSS52

AJ23

VSS53

AJ20

VSS54

AJ17

VSS55

AJ14

VSS56

AJ11

VSS57

AJ8

VSS58

AJ5

VSS59

AJ2

VSS60

AH35

VSS61

AH34

VSS62

AH33

VSS63

AH32

VSS64

AH31

VSS65

AH30

VSS66

AH29

VSS67

AH28

VSS68

AH27

VSS69

AH26

VSS70

AH20

VSS71

AH17

VSS72

AH13

VSS73

AH9

VSS74

AH6

VSS75

AH3

VSS76

AG10

VSS77

AF8

VSS78

AF4

VSS79

AF2

VSS80

AE35

VSS81 AE34

VSS82 AE33

VSS83 AE32

VSS84 AE31

VSS85 AE30

VSS86 AE29

VSS87 AE28

VSS88 AE27

VSS89 AE26

VSS90 AE6

VSS91 AD10

VSS92 AC8

VSS93 AC4

VSS94 AC2

VSS95 AB35

VSS96 AB34

VSS97 AB33

VSS98 AB32

VSS99 AB31

VSS100 AB30

VSS101 AB29

VSS102 AB28

VSS103 AB27

VSS104 AB26

VSS105 AB6

VSS106 AA10

VSS107 Y8

VSS108 Y4

VSS109 Y2

VSS110 W35

VSS111 W34

VSS112 W33

VSS113 W32

VSS114 W31

VSS115 W30

VSS116 W29

VSS117 W28

VSS118 W27

VSS119 W26

VSS120 W6

VSS121 V10

VSS122 U8

VSS123 U4

VSS124 U2

VSS125 T35

VSS126 T34

VSS127 T33

VSS128 T32

VSS129 T31

VSS130 T30

VSS131 T29

VSS132 T28

VSS133 T27

VSS134 T26

VSS135 T6

VSS136 R10

VSS137 P8

VSS138 P4

VSS139 P2

VSS140 N35

VSS141 N34

VSS142 N33

VSS143 N32

VSS144 N31

VSS145 N30

VSS146 N29

VSS147 N28

VSS148 N27

VSS149 N26

VSS150 N6

VSS151 M10

VSS152 L35

VSS153 L32

VSS154 L29

VSS155 L8

VSS156 L5

VSS157 L2

VSS158 K34

VSS159 K33

VSS160 K30

C 5 80

22U_0805_6.3V6M

1

2

C 89

10U_0805_6.3V6M

1

2

C 16 6

10U_0805_6.3V6M

1

2

C 1 96

10U_0805_6.3V6M

1

2

C 5 77

22U_0805_6.3V6M

1

2

C 5 74

22U_0805_6.3V6M

1

2

C 1 97

10U_0805_6.3V6M

1

2

C 5 71

22U_0805_6.3V6M

1

2

C 5 68

22U_0805_6.3V6M

1

2

C 14 7

10U_0805_6.3V6M

1

2

C 5 73

22U_0805_6.3V6M

1

2

+

C 75

470U_D2T_2VM

1

2 3

+

C 1 64

470U_D2T_2VM

1

2 3

C 1 95

10U_0805_6.3V6M

1

2

C 87

22U_0805_6.3V6M

1

2

C 1 80

10U_0805_6.3V6M

1

2

C 17 9

10U_0805_6.3V6M

1

2

C 5 72

22U_0805_6.3V6M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

D DR _ A_ D31

D DR _ A_ D12

DDR_CKE0_DI M MA

D DR _ A_ D59

DDR_A _D6

DDR_A _MA3

SMB_CLK_S3

DDR_CS1_DIM M A#

D DR _ A_ D39

D DR _A_B S1

DDR _A _DQS 0

DDR _A _W E#

DDR_A _MA7

DDR_A _MA0

DD R_ A_DM 2

DD R_ A_DM 1

DDR _A _DQS 7

DDR_A _D0

D DR _ A_ D57

D DR _ A_ D46

D DR _ A_ D28

DD R_ A_DM 0

D DR _ A_ D19

DD R_ A_DQ S# 5

D DR _ A_ D51

DDR_A _D4

DD R_ A_DM 4

D DR _ A_ D30

DDR _A _DQS 2

D DR _ A_ D44

DD R_ A_RA S#

D DR _ A_ D33

D DR _ A_ D58

DD R_ A_DM 5

DDR _A _DQS 3

DDR_A_MA8

DDR_CS0_DIM M A#

D DR _ A_ D10

DDR_A_MA6

D DR _ A_ D27

DDR_A _D3

DRAMRST#

DDR_A _MA10

DD R_ A_DQ S# 7

DDR_A _D1

DD R_ A_DQ S# 6

D DR _ A_ D40

DDR_A _MA9

D DR _ A_ D16

D DR _ A_ D29

DD R_ A_DQ S# 4

D DR _ A_ D52

DD R_ A_DM 3

DDR _A _DQS 5

D DR _ A_ D54

D DR _ A_ D49

D DR _A_B S2

D DR _ A_ D45

DDR_A _D9

DD R_ A_DM 7

DDR_A _D7

DDR_A _MA1

D DR _ A_ D13

D DR _ A_ D20

D DR _ A_ D60

D DR _A_B S0

DD R_ A_CA S# M _ODT0

D DR _ A_ D37

DDR_A _MA5

DD R_ A_DQ S# 1

DDR_A _MA14

D DR _ A_ D55

DDR_A _MA4

D DR _ A_ D21

D DR _ A_ D62

D DR _ A_ D24

D DR _ A_ D15

D DR _ A_ D23

D DR _ A_ D56

D DR _ A_ D53

D DR _ A_ D47

D DR _ A_ D18

M_ODT1

D DR _ A_ D43

D DR _ A_ D34

M _CLK_DDR1

M _CLK_DDR#1

D DR _ A_ D48

SMB_DATA_S3

DD R_ A_DQ S# 2

D DR _ A_ D11

D DR _ A_ D38

M _CLK_DDR0

M _CLK_DDR#0

DD R_ A_DQ S# 3

D DR _ A_ D32

DDR_A _D8

DDR _A _DQS 1

DDR_A _MA13

DDR_A_MA11

D DR _ A_ D50

D DR _ A_ D61

DDR_A _MA2

D DR _ A_ D41

D DR _ A_ D17

D DR _ A_ D36

D DR _ A_ D26

D DR _ A_ D63

DDR_A _D2

DDR_A _D5

D DR _ A_ D22

D DR _ A_ D25

DDR _A _DQS 6

D DR _ A_ D35

D DR _ A_ D14

DDR_A _MA12

DD R_ A_DQ S# 0

DDR _A _DQS 4

DD R_ A_DM 6

D DR _ A_ D42

DDR_CKE1_DI M MA

PM_EXTTS#1_R

+V REF_DQ_DIMMA

DDR_A _MA15

D DR _ A _DQ S #[ 0.. 7]<7>

D DR _A _D [0. .6 3]<7>

D DR _ A _DM [ 0.. 7]<7>

D DR _ A _D QS [ 0.. 7]<7>

DDR_A _MA[ 0..15]<7>

DDR_CKE0_DI MMA<7>

DDR_A _BS2<7>

M _C LK _DD R0<7>

M_CLK _DDR#0<7>

DDR_A _BS0<7>

D DR _ A _W E#<7 >

D D R_ A_ CA S#< 7>

DDR_CS1_DIM MA#<7>

DDR_CKE1_DI MMA <7>

DDR_A _BS1 < 7>

D D R_ A_ RA S# <7>

DDR_CS0_DIM MA# <7>

M_ODT0 <7>

M _C LK _DD R1 <7>

M_CLK _DDR#1 <7>

M_ODT1 <7>

DRAMRST# <5,11>

PM_EXTTS#1_R <5,11>

SMB_DATA_S3 <11,12,14,28>

SMB_CLK_S3 <11,12,14,28>

+0.75VS

+3VS

+1.5V +1.5V

+V REF_DQ_ DIMMA

+1.5V

+V REF_DQ_ DIMMA

+1.5V

+0.75VS

+V REF_DQ_ DIMMA

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

DDRIII-SODIMM SLOT1

C us t o m

10 51Thur sday, October 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

DDR3 SO-DIMM A

Layout Note:

Place near DIMM

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VDDQ(1.5V) =

3*0805 10uf

VTT(0.75V) =

4*0402 1uf

1*0402 0.1uf

VREF =

1*0402 2.2uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

For Arranale only +VREF_DQ_DIMMA

supply from a external 1.5V voltage divide

circuit.

07/17/2009

C 60 8

2.2U_0603_6.3V4Z

1

2

C 31 0

10U_0603_6.3V6M

1

2

+

C 5 69

220U_B2_2.5VM_R35

1

2

C 31 7

0.1U_0402_10V6K

1

2

C 58 1

10U_0603_6.3V6M

1

2

C 31 6

0.1U_0402_10V6K

1

2

C 31 4

0.1U_0402_10V6K

1

2

C 61 7

0.1U_0402_10V6K

1

2

C 57 0

10U_0603_6.3V6M

1

2

C 34 7

2.2U_0603_6.3V4Z

1

2

C 30 9

10U_0603_6.3V6M

1

2

R 29 7

1K _0402_1%

12

C 58 6

10U_0603_6.3V6M

1

2

C 31 5

0.1U_0402_10V6K

1

2

C 6 06

1U_0603_10V4Z

1

2

C 58 8

10U_0603_6.3V6M

@

1

2

R 3 05

1K _0402_1%

12

C 35 5

2.2U_0603_6.3V4Z

1

2

R 5 71

10K_0402_5%

12

C 6 07

1U_0603_10V4Z

1

2

C 3 01

1U_0603_10V4Z

1

2

C 30 3

0.1U_0402_10V6K

1

2

C 3 00

1U_0603_10V4Z

1

2

R 5 70

10K_0402_5%

1 2

C 6 05

1U_0603_10V4Z

1

2

C 30 8

10U_0603_6.3V6M

1

2

JDIMM1

FOX _AS0A626-U4SN-7F

ME@

VREF_DQ

1VSS1 2

VSS2

3DQ4 4

DQ0

5DQ5 6

DQ1

7VSS3 8

VSS4

9DQS#0 10

DM0

11 DQS0 12

VSS5

13 VSS6 14

DQ2

15 DQ6 16

DQ3

17 DQ7 18

VSS7

19 VSS8 20

DQ8

21 DQ12 22

DQ9

23 DQ13 24

VSS9

25 VSS10 26

DQS#1

27 DM1 28

DQS1

29 RESET# 30

VSS11

31 VSS12 32

DQ10

33 DQ14 34

DQ11

35 DQ15 36

VSS13

37 VSS14 38

DQ16

39 DQ20 40

DQ17

41 DQ21 42

VSS15

43 VSS16 44

DQS#2

45 DM2 46

DQS2

47 VSS17 48

VSS18

49 DQ22 50

DQ18

51 DQ23 52

DQ19

53 VSS19 54

VSS20

55 DQ28 56

DQ24

57 DQ29 58

DQ25

59 VSS21 60

VSS22

61 DQS#3 62

DM3

63 DQS3 64

VSS23

65 VSS24 66

DQ26

67 DQ30 68

DQ27

69 DQ31 70

VSS25

71 VSS26 72

A12/BC#

83 A11 84

A9

85 A7 86

VDD5

87 VDD6 88

A8

89 A6 90

CKE0

73 CKE1 74

VDD1

75 VDD2 76

NC1

77 A15 78

BA2

79 A14 80

VDD3

81 VDD4 82

A5

91 A4 92

VDD7

93 VDD8 94

A3

95 A2 96

A1

97 A0 98

VDD9

99 VDD10 100

CK0

101 CK1 102

CK0#

103 CK1# 104

VDD11

105 VDD12 106

A10/AP

107 BA1 108

BA0

109 RAS# 110

VDD13

111 VDD14 112

WE#

113 S0# 114

CAS#

115 ODT0 116

VDD15

117 VDD16 118

A13

119 ODT1 120

S1#

121 NC2 122

VDD17

123 VDD18 124

NCTEST

125 VREF_CA 126

VSS27

127 VSS28 128

DQ32

129 DQ36 130

DQ33

131 DQ37 132

VSS29

133 VSS30 134

DQS#4

135 DM4 136

DQS4

137 VSS31 138

VSS32

139 DQ38 140

DQ34

141 DQ39 142

DQ35

143 VSS33 144

VSS34

145 DQ44 146

DQ40

147 DQ45 148

DQ41

149 VSS35 150

VSS36

151 DQS#5 152

DM5

153 DQS5 154

VSS37

155 VSS38 156

DQ42

157 DQ46 158

DQ43

159 DQ47 160

VSS39

161 VSS40 162

DQ48

163 DQ52 164

DQ49

165 DQ53 166

VSS41

167 VSS42 168

DQS#6

169 DM6 170

DQS6

171 VSS43 172

VSS44

173 DQ54 174

DQ50

175 DQ55 176

DQ51

177 VSS45 178

VSS46

179 DQ60 180

DQ56

181 DQ61 182

DQ57

183 VSS47 184

VSS48

185 DQS#7 186

DM7

187 DQS7 188

VSS49

189 VSS50 190

DQ58

191 DQ62 192

DQ59

193 DQ63 194

VSS51

195 VSS52 196

SA0

197 EVENT# 198

VDDSPD

199 SDA 200

SA1

201 SCL 202

VTT1

203 VTT2 204

G1

205 G2 206

C 34 6

0.1U_0402_10V6K

1

2

C 58 9

10U_0603_6.3V6M

@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

D DR _ B_ D26

DDR_B _D2

DDR_B _D5

D DR _ B_ D22

D DR _ B_ D25

D DR _ B_ D14

DD R_ B_DQ S# 0

D DR _ B_ D31

D DR _ B_ D12

DDR_B _D6

DDR _B _DQS 0

DD R_ B_DM 2

DD R_ B_DM 1

+V REF_DQ_DIMMB

DDR_B _D0

D DR _ B_ D28

DD R_ B_DM 0

D DR _ B_ D19

DDR_B _D4

D DR _ B_ D30

DDR _B _DQS 2

DDR _B _DQS 3

D DR _ B_ D10

D DR _ B_ D27

DDR_B _D3

DRAMRST#

DDR_B _D1

D DR _ B_ D16

D DR _ B_ D29

DD R_ B_DM 3

DDR_B _D9

DDR_B _D7

D DR _ B_ D13

D DR _ B_ D20

DD R_ B_DQ S# 1

D DR _ B_ D21

D DR _ B_ D24

D DR _ B_ D15

D DR _ B_ D23D DR _ B_ D18

DD R_ B_DQ S# 2

D DR _ B_ D11

DD R_ B_DQ S# 3

DDR_B _D8

DDR _B _DQS 1

D DR _ B_ D17

D DR _ B_ D36

D DR _ B_ D63

DDR_B _MA15

DD R_ B_DM 6

DDR_CKE3_DI M MB

D DR _ B_ D39

D DR _B_B S1

DDR_B _MA7

DDR_B _MA0

DDR _B _DQS 7

D DR _ B_ D46

DD R_ B_DQ S# 5

DD R_ B_DM 4

D DR _ B_ D44

DD R_ B_RA S#

DDR_CS2_DIM M B#

DDR_B_MA6

DD R_ B_DQ S# 7

D DR _ B_ D52

DDR _B _DQS 5

D DR _ B_ D54

D DR _ B_ D45

D DR _ B_ D60

M_ODT2

D DR _ B_ D37

DDR_B _MA14

D DR _ B_ D55

DDR_B _MA4

D DR _ B_ D62

D DR _ B_ D53

D DR _ B_ D47

M_ODT3

M _CLK_DDR3

M _CLK_DDR#3

D DR _ B_ D38

DDR_B_MA11

D DR _ B_ D61

DDR_B _MA2

SMB_CLK_S3

SMB_DATA_S3

PM_EXTTS#1_R

DDR _B _DQS 6

D DR _ B_ D35

DDR_B _MA12

DDR _B _DQS 4

D DR _ B_ D42

DDR_CKE2_DI M MB

D DR _ B_ D59

DDR_B _MA3

DDR_CS3_DIM M B#

DDR _B _W E#

D DR _ B_ D57

D DR _ B_ D51

D DR _ B_ D33

D DR _ B_ D58

DD R_ B_DM 5

DDR_B_MA8

DDR_B _MA10

DD R_ B_DQ S# 6

D DR _ B_ D40

DDR_B _MA9

DD R_ B_DQ S# 4

D DR _ B_ D49

D DR _B_B S2

DD R_ B_DM 7

DDR_B _MA1

D DR _B_B S0

DD R_ B_CA S#

DDR_B _MA5

D DR _ B_ D56

D DR _ B_ D43

D DR _ B_ D34

D DR _ B_ D48

M _CLK_DDR2

M _CLK_DDR#2

D DR _ B_ D32

DDR_B _MA13

D DR _ B_ D50

D DR _ B_ D41

DRAMRST# <5,10>

D DR _ B _DQ S #[ 0.. 7]< 7>

D DR _B _D [0. .6 3]< 7>

D DR _ B _DM [ 0.. 7]< 7>

D DR _ B _DQ S [0 ..7 ]<7>

DDR_B _MA[ 0..15]<7>

DDR_CKE3_DI MMB <7>

M _ CL K_ DD R3 <7>

M _C LK _DD R#3 <7>

D DR _B _B S 1 <7>

D DR _ B _RA S # <7>

DDR_CS2_DIM MB# <7>

M_ODT2 <7>

M_ODT3 <7>

SMB_DATA_S3 <10,12,14,28>

SMB_CLK_S3 <10,12,14,28>

PM_EXTTS#1_R <5,10>

D DR _B _B S 2<7>

DDR_CKE2_DI MMB<7>

M _C LK _DD R2<7>

M _C LK _DD R#2<7>

D DR _B _B S 0<7>

D DR _ B _W E #<7>

D D R_ B_ CA S#<7>

DDR_CS3_DIM MB#<7>

+0.75VS

+3VS

+1.5V +1.5V

+V REF_DQ_ DIMMB

+1.5V

+0.75VS

+V REF_DQ_DIMMB

+1.5V

+V REF_DQ_ DIMMB

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.3

DDRIII-SODIMM SLOT2

11 51Thurs day , Oc tober 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

Layout Note:

Place near DIMM

Layout Note:

Place near DIMM

1*0402 0.1uf 1*0402 2.2uf

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

3*0805 10uf

VTT(0.75V) =

4*0402 1uf

1*0402 0.1uf

VDDQ(1.5V) =

1*0402 2.2uf

VDDSPD (3.3V)=

For Arranale only +VREF_DQ_DIMMB

supply from a external 1.5V voltage divide

circuit.

07/17/2009

C 5 87

10U_0603_6.3V6M

@

1

2

C 3 83

2.2U_0603_6.3V4Z

1

2

R 34 1

1K _0402_1%

12

R 5 72

10K_0402_5%

1 2

C 3 82

2.2U_0603_6.3V4Z

1

2

C 5 95

1U_0603_10V4Z

1

2

C 5 96

10U_0603_6.3V6M

1

2

C 2 99

1U_0603_10V4Z

1

2

C 3 04

0.1U_0402_10V6K

1

2

C 3 84

0.1U_0402_10V6K

1

2

R 3 40

1K _0402_1%

12

C 3 13

10U_0603_6.3V6M

1

2

C 3 05

0.1U_0402_10V6K

1

2

R 5 73 1 0K _0 402_5 %

1 2

JDIMM2

TYCO_2-2013297-2~D

ME@

VREF_DQ

1

VSS

3

DQ0

5

DQ1

7

VSS

9

DM0

11

VSS

13

DQ2

15

DQ3

17

VSS

19

DQ8

21

DQ9

23

VSS

25

DQS1#

27

DQS1

29

VSS

31

DQ10

33

DQ11

35

VSS

37

DQ16

39

VSS 2

DQ4 4

DQ5 6

VSS 8

DQS0# 10

DQS0 12

VSS 14

DQ6 16

DQ7 18

VSS 20

DQ12 22

DQ13 24

VSS 26

DM1 28

RESET# 30

VSS 32

DQ14 34

DQ15 36

VSS 38

DQ20 40

DQ17

41

VSS

43

DQS2#

45

DQS2

47

VSS

49

DQ18

51

DQ19

53

VSS

55

DQ24

57

DQ25

59

VSS

61

DM3

63

VSS

65

DQ26

67

DQ27

69

VSS

71

CKE0

73

VDD

75

NC

77

BA2

79

VDD

81

A12/BC#

83

A9

85

VDD

87

A8

89

A5

91

VDD

93

A3

95

A1

97

VDD

99

CK0

101

CK0#

103

VDD

105

A10/AP

107

BA0

109

VDD

111

WE#

113

CAS#

115

VDD

117

A13

119

S1#

121

VDD

123

TEST

125

VSS

127

DQ32

129

DQ33

131

VSS

133

DQS4#

135

DQS4

137

VSS

139

DQ34

141

DQ35

143

VSS

145

DQ40

147

DQ41

149

VSS

151

DM5

153

VSS

155

DQ42

157

DQ43

159

VSS

161

DQ48

163

DQ49

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SA0

197

VDDSPD

199

DQ21 42

VSS 44

DM2 46

VSS 48

DQ22 50

DQ23 52

VSS 54

DQ28 56

DQ29 58

VSS 60

DQS3# 62

DQS3 64

VSS 66

DQ30 68

DQ31 70

VSS 72

CKE1 74

VDD 76

A15 78

A14 80

VDD 82

A11 84

A7 86

VDD 88

A6 90

A4 92

VDD 94

A2 96

A0 98

VDD 100

CK1 102

CK1# 104

VDD 106

BA1 108

RAS# 110

VDD 112

S0# 114

ODT0 116

VDD 118

ODT1 120

NC 122

VDD 124

VREF_CA 126

VSS 128

DQ36 130

DQ37 132

VSS 134

DM4 136

VSS 138

DQ38 140

DQ39 142

VSS 144

DQ44 146

DQ45 148

VSS 150

DQS5# 152

DQS5 154

VSS 156

DQ46 158

DQ47 160

VSS 162

DQ52 164

DQ53 166

VSS 168

DM6 170

VSS 172

DQ54 174

DQ55 176

VSS 178

DQ60 180

DQ61 182

VSS 184

DQS7# 186

DQS7 188

VSS 190

DQ62 192

DQ63 194

VSS 196

EVENT# 198

SDA 200

SA1

201

VTT

203

GND1

205

SCL 202

VTT 204

GND1 206

C 3 06

0.1U_0402_10V6K

1

2

C 5 75

10U_0603_6.3V6M

1

2

C 61 8

2.2U_0603_6.3V4Z

1

2

C 61 6

0.1U_0402_10V6K

1

2

C 3 07

0.1U_0402_10V6K

1

2

C 3 85

0.1U_0402_10V6K

1

2

C 5 98

1U_0603_10V4Z

1

2

C 5 82

10U_0603_6.3V6M

@

1

2

C 5 90

10U_0603_6.3V6M

1

2

C 5 76

10U_0603_6.3V6M

1

2

C 3 11

10U_0603_6.3V6M

1

2

C 3 12

10U_0603_6.3V6M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK _XTAL_IN

CLK_XTAL_OUT

CLK_XTAL_OUT

SMB_CLK_S3

SMB_DATA_S3

CLK _XTAL_IN

CK_P WRG D

CP U_S TOP#

CLK_14M_PCH

R_CLK _BUF_B CLK# CLK_ BUF_BCL K#

CLK_48M_CR_R

R EF_ 0/C PU _SEL

CLK_14M_PCH

CLK_B UF_DOT96#

CLK_B UF_DOT96

L_CLK_BU F_DO T96#

L_CLK_BU F_D OT96

CLK_D MI#

CLK_D MI

L_CLK_DMI#

L_CLK_DMI

CLK_48M_CR_R

CK_P WRG D

R EF_ 0/C PU _SEL

R EF_ 0/C PU _SEL

R _C LK_B UF _BCLK CL K_BUF _BCL K

VDD_3 V3_1V5

VDD_3 V3_1V5

VDD_3 V3_1V5

VDD_3 V3_1V5

C L K_BU F_CK SS CD

C L K_BU F_CK SS CD #

CLK _B UF_CKSSCD_R

C L K_BU F_CK SS CD #_R CLK_B UF_B CLK # <14>

CLK_B UF_B CLK <14>

CLK_14M_PCH <14>

CLK_E N# <48>

CLK_D MI<14>

CLK_D MI#<14>

CLK_B UF_DOT96<14>

CLK_B UF_DOT96#<14>

SMB_DATA_S3 <10,11,14,28>

SMB_CLK_S3 <10,11,14,28>

CLK_48M_CR

C LK _ BUF_ CK SS CD<14>

C L K_ BU F_ CK S SC D#<1 4>

+3VS +3VS_CK505

+1.05VS_CK505+1.05VS

+3VS_CK505 +1. 05V S_CK505+3VS_CK505 +1. 05V S_CK505

+1.05VS

+3VS_CK505

+3VS_CK505

VDD_3 V3_1V5+3VS_CK505

+1.5VS

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

CLOCK GENERATOR

12 51Thur sday, October 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

1 PCS CAP(0.1u) BY 1 INPUT PIN

ICS9LVS3199AKLFT MLF 32P CLK GEN (SA00003HR00)

1 PCS CAP(0.1u) BY 1 INPUT PIN

1

CPU_1PIN 30 CPU_0

0 133MHz

(Default)

133MHz

100MHz 100MHz

CLOSE U27

CLK GEN TO PCH

1. CLK_DMI

EMI Capacitor

2. CLK_BUF_BCLK

3. CLK_BUF_CKSSCD

4. CLK_BUF_DOT96

5. CLK_14M_PCH

PIN8 IS GND FOR ICS3197

PIN8 IS 48MHz FOR ICS3199

CLK GEN TO VGA

1. 27M_CLK

1. 27M_CLK_SS

RTM890N-631-GRT QFN 32P CLK GEN (SA00003HQ00)

Reserve for Low Power CLK GEN.

RTM890N-632

SLG8LV597VTR

1 PCS CAP(0.1u) BY 1 INPUT PIN

unstuff 09.09.08

R 2 780 _0 603 _5%

@

1 2

C 3 66

0.1U_0402_10V6K

1

2

C 3 48

22P_0402_50V8J

1

2

C 3 64

22P_0402_50V8J

12

C 34 9

22P_0402_50V8J

1

2

C 33 1

10U_0805_10V4K

1

2

R 30 8

0_0402_5%

1 2

Y1

14.31818MH Z_16PF_DSX840GA

12

C 36 7

0.1U_0402_10V6K

1

2

U14

SLG8SP 587VTR_QFN32_5X5

CPU_1# 19

SATA

10

CKPWRGD/PD# 25

DOT_96#

4

CPU_0# 22

XTAL_OUT 27

VSS_REF 26

VDD_CPU 24

CPU_0 23

27MHZ_SS

7

XTAL_IN 28

27MHZ

6

USB_48

8

CPU_1 20

VSS_CPU 21

VDD_CPU_IO 18

VDD_USB_48

1

VSS_48M

2

REF_0/CPU_SEL 30

SDA 31

SCL 32

VDD_27

5

VSS_27M

9

SATA#

11

VSS_SRC

12

SRC_1

13

SRC_1#

14

VDD_SRC_IO

15

VDD_SRC 17

VDD_REF 29

DOT_96

3

CPU_STOP#

16

TGND

33

R 27 90_ 06 03_5 %

1 2

R 27 70_ 06 03_5 %

1 2

R 2 76 0_ 04 02_ 5%

1 2

R 2 98

10K_0402_5%

1 2

C 33 3

10U_0805_10V4K

1

2

C 34 3

0.1U_0402_10V6K

1

2

G

D

S

Q25

2N7002_SOT23-3

2

13

R 2 690 _0 603 _5%

1 2

C 34 2

0.1U_0402_10V6K

1

2

C 3 30

0.1U_0402_10V6K

1

2

C 33 2

0.1U_0402_10V6K

1

2

C 3 34

0.1U_0402_10V6K

1

2

R 30 6

0_0402_5%

1 2

C 35 0

0.1U_0402_10V6K

1

2

R 31 5

33_0402_1%

12

R 3 19 0 _0 40 2_5%

1 2

R 3 230 _0 40 2_5%

@

12

C 36 5

10P_0402_50V8J@

12

R307 0_0402_5%

1 2

R324 0_0402_5%

1 2

C 34 4

10U_0805_10V4K

1

2

R 32 233_ 04 02_1%

@

1 2

R 2 75 0_ 04 02_ 5%

1 2

R 29 9

10K_0402_5%

1 2

R 31 6 10 K_ 04 02_5%

1 2

R 31 7 10 K_ 04 02_5%@

1 2

R 3 18 0 _0 40 2_5%

1 2

C 3 36

10U_0805_10V4K

1

2

C 33 5

0.1U_0402_10V6K

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCH_R T CX1

PCH_R T CX2

PCH_R T CX1

PCH_R T CX2

PCH_R TCR ST#

PCH_S RTCRS T#

S M_INTRUDE R#

PCH_I NTVRMEN

S M_INTRUDE R#

HDA_R ST#

P CH _SPK R

H DA _ SD IN1

SE RIRQ

GPIO 23

SATAICOMPPCH_J TA G_RST#

PCH _JTAG_TMS

PCH_J TAG_TDI

PCH_J TAG_TDO

BIT CLK

HDA_S Y N C

H DA _ SD IN0

H DA _S DOUT

PCH_I NTVRMEN

SATA_ITX_DRX_P0

SATA_ITX_DRX_N0

SAT A_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

SAT A_ITX_C_DRX_N0

SATA_ITX_C_DRX_P0

SAT A_ITX_C_DRX_N4

SATA_ITX_C_DRX_P4

SATA_ITX_DRX_P1

SATA_ITX_DRX_N1

SAT A_DTX_C_IRX_N1

SATA_DTX_C_IRX_P1

SAT A_ITX_C_DRX_N1

SATA_ITX_C_DRX_P1

PCH_J TA G_TCK

SPI _WP#

SPI _HO LD#

S PI_CLK_PC H_R

SPI _SB_CS0#

SPI _ SI

SPI _SO_R

PCH _JTAG_TMS P CH_JTAG_RST#PCH_J TAG_TDO PCH_J TAG_TDI

GPIO 19

GPIO 21

GPIO 19

GPIO 21

P CH _SPK R

GPIO 13

SPI _WP#

SPI _HO LD#

SPI _SB_CS0#

SPI _SO_R SPI_ SO_L

SPI _ SI

SPI _CLK_P CH

SPI _CLK_P CH

SPI _CLK_P CH

SAT A _ITX _DRX_N4_CONN

SAT A_DTX_C_IRX_N4

SAT A _ITX_DRX_P4_CONN

SATA_DTX_C_IRX_P4

PCH_J TA G_TCK

H DA _ S D IN1< 33>

LP C_A D0 <28,34>

LP C_A D1 <28,34>

LP C_A D2 <28,34>

LP C_A D3 <28,34>

LP C_F RAME# <28,34>

S E RI RQ <34>

H DD _ L ED # < 36>

H DA _ BI TC LK _C OD EC<33 >

H DA _ S Y N C_ C O DE C<3 3>

H D A_ RS T_ CO DE C#<33 >

H DA _ SD OUT _C OD EC<33>

SAT A_DTX_C_IRX_N0 <32>

SATA_DTX_C_IRX_P0 <32>

SATA_ITX_DRX_N0 <32>

SATA_ITX_DRX_P0 <32>

SATA_ITX_DRX_N1 <32>

SATA_ITX_DRX_P1 <32>

SAT A_DTX_C_IRX_N1 <32>

SATA_DTX_C_IRX_P1 <32>

P CH _S PK R<33>

ME_FLASH<34>

SATA_DTX_C_IRX_P4 <37>

SAT A _ITX_DRX_N4_CONN <37>

SAT A_DTX_C_IRX_N4 <37>

SAT A _ITX_DRX_P4_CONN <37>

+ R TC VC C

+ R TC VC C

+1.05VS

+3VS

+3VS

+3VS

+3VALW+3VALW +3VALW +3VALW +3VS

+ R TC VC C

+RTCBATT

+3VS

+3VALW

+3VS

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

IBEX-M(1/6)-HDA/JTAG/SATA

C us t o m

13 51Thur sday, October 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

H Integrated VRM enable

L Integrated VRM disable

*

GPIO33 = GPO , internal pull-up,should not be pulled low

GPIO19 = GPI,3.3V,CORE

GPIO21 = GPI,3.3V,CORE

GPIO23 = NATIVE,3.3V,CORE

GPIO13 = GPI,3.3V,SUS

flash ME core of strap pin pull down

*

No Install

No Install

No Install

100ohm 100ohm

100ohm 100ohm

10Kohm 10Kohm

20Kohm 20Kohm

100ohm

200ohm

200ohm

200ohm

200ohm

200ohm

51ohm

No Install

R580

No Install

No InstallPCH_JTAG_TMS

PCH JTAG

Pre-Production

PCH JTAG

Production

RefDesPCH Pin

No InstallPCH_JTAG_TDO

ES1 MPES2

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

R584

R583

R591

R590

No InstallR587

R586

R595

R594

No Install

No Install

51ohm 51ohm

(2009,07,07)

4M SPI ROM FOR HM55

(ME code & BIOS code)

SA00003K800

HDD

ODD

E-SATA

(2009,05,04)

FOR INTEL DPDG REV1.6 (MAY 2009)

R 1 18

10K_0402_5%

@

12

R 45 3 1 0K _0 402_5 %

1 2

R 1 44

100_0603_1%

1 2

T7 P AD

R 62

3.3K_ 0402_5%

1 2

RTCIHDA

SATA LPC

SPI JTAG

U 7A

IB EXPEAK-M_FCBGA1071

RTCX1

B13

RTCX2

D13

INTVRMEN

A14

INTRUDER#

A16

HDA_BCLK

A30

HDA_SYNC

D29

HDA_RST#

C30

HDA_SDIN0

G30

HDA_SDIN1

F30

HDA_SDIN2

E32

HDA_SDO

B29

SATALED# T3

FWH0 / LAD0 D33

FWH1 / LAD1 B33

FWH2 / LAD2 C32

FWH3 / LAD3 A32

LDRQ1# / GPIO23 F34

FWH4 / LFRAME# C34

LDRQ0# A34

RTCRST#

C14

HDA_SDIN3

F32

HDA_DOCK_EN# / GPIO33

H32

HDA_DOCK_RST# / GPIO13

J30

SRTCRST#

D17

SATA0RXN AK7

SATA0RXP AK6

SATA0TXN AK11

SATA0TXP AK9

SATA1RXN AH6

SATA1RXP AH5

SATA1TXN AH9

SATA1TXP AH8

SATA2RXN AF11

SATA2RXP AF9

SATA2TXN AF7

SATA2TXP AF6

SATA3RXN AH3

SATA3RXP AH1

SATA3TXN AF3

SATA3TXP AF1

SATA4RXN AD9

SATA4RXP AD8

SATA4TXN AD6

SATA4TXP AD5

SATA5RXN AD3

SATA5RXP AD1

SATA5TXN AB3

SATA5TXP AB1

SATAICOMPI AF15

SPI_CLK

BA2

SPI_CS0#

AV3

SPI_CS1#

AY3

SPI_MOSI

AY1

SPI_MISO

AV1

SATA0GP / GPIO21 Y9

SATA1GP / GPIO19 V1

JTAG_TCK

M3

JTAG_TMS

K3

JTAG_TDI

K1

JTAG_TDO

J2

TRST#

J4

SERIRQ AB9

SPKR

P1

SATAICOMPO AF16

R 1 15

100_0402_1%

@

12

U3

S IC FL 16M EN25F16-100 HIP SOP 8P

CS#

1

SO

2

WP#

3

GND

4

VCC 8

HOLD# 7

SCLK 6

SI 5

R74

200_0402_5%

@

12

C 1 71

15P_0402_50V8J

1

2

C 46 0

0.1U_0402_16V4Z

1 2

R 4 82

10K_0402_5%

1 2

R 1 00

33_0402_5%

@

12

R 16 7 33 _0 402_ 5%

1 2

R 1 14 51 _0 40 2_5%

1 2

R 4 20

330K_0402_5%

1 2

C L RP 3

SHORT PADS

12

R 44 7

10K_0402_5%

1 2

C L RP 2

SHORT PADS

12

R 50 0

37.4_0402_1%

1 2

C 14 00. 01 U_ 04 02_ 16V7K

12

C 64 81 2P _0 40 2_50V 8J

@

1 2

C 64 71 2P _0 40 2_50V 8J

@

1 2

C 1 83

15P_0402_50V8J

1

2

R 47 910 K_ 040 2_5%

12

X1

32.768K HZ_12.5PF _9H03200413

OSC 4

OSC 1

NC

3

NC

2

R 16 9 33 _0 402_ 5%

1 2

C 42 80. 01 U_ 04 02_ 16V7K

12

R 1 02

3.3K_ 0402_5%

1 2

R99

0_0402_5%

1 2

C 2 02

1U_0603_10V4Z

1

2

R 42 2 20 K_ 04 02_1%

1 2

C 42 70. 01 U_ 04 02_ 16V7K

12

R75

20K_0402_5%

@

1 2

R 1 16

100_0402_1%

@

12

R 1 17

100_0402_1%

@

12

R 4 52 1 K_ 04 02_5%@

1 2

C LR P 1

SHORT PADS

12

C 1 420. 01 U_ 04 02 _16V7 K ESATA@

12

R 16 8 33 _0 402_ 5%

1 2

R 1 54 10 M _0402_ 5%

1 2

R73

200_0402_5%

@

12

R 16 6 33 _0 402_ 5%

1 2

R 4 25 0_ 04 02_ 5%

1 2

C 1 430. 01 U_ 04 02 _16V7 K ESATA@

12

C 14 10. 01 U_ 04 02_ 16V7K

12

R 42 4 10 K_ 04 02_5%

@

1 2

R 10 3

15_0402_5%

1 2

R 4 09 1K _ 040 2_5%@

1 2

C 4 41

0.1U_0402_16V4Z

1

2

R72

200_0402_5%

@

12

R 1 01

15_0402_5%

12

C 1 38

22P_0402_50V8J

@

R 4 21

1M_0402_5%

1 2

R 41 9 20 K_ 04 02_1%

1 2

C 1 84

1U_0603_10V4Z

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

C LK _P CIE_ WLAN 1_R

C LK _P CIE_ WLAN 1#_R

PCIE_PTX_DRX_P3

PCIE _PTX_DRX_N3

PCIE_PRX_DTX_P3

PCIE _PRX_DTX_N3

PCIE_PTX_DRX_P2

PCIE _PTX_DRX_N2

PCIE_PRX_DTX_P2

PCIE _PRX_DTX_N2

LID_OUT#

SMBCLK

SMBDATA

GPIO 60

SML0CLK

SML0DATA

GPIO 74

SMB_EC_CK2_REC_SMB_CK2

SMB_EC_DA2_REC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA2

SML1CLK

SML1DATA

LID_OUT#

PEG _CLK REQ#

SMBCLK

SMBDATA

SML1CLK

SML1DATA

SML0CLK

SML0DATA

GPIO 74

SMB_CLK_S3

SMB_DATA_S3

SMB_CLK_S3

SMB_DATA_S3

XTAL25_IN

CLK_14M_PCH

GPIO 60

SMBCLK

SMBDATA S MB_DATA_S3

SMB_CLK_S3

SMB_EC_CK2_R

SMB_EC_DA2_R

EC_SMB_CK2

EC_SMB_DA2

PEG _CLK REQ#

C LK _P CI_F B

CLK_P CIE_LAN _R

CLK_P CIE_LAN #_R

CLKOUT_DP_N

CLKOUT_DP_P

CL K_14 M_ PCHC LK _P CI_F B

CLK_P CIE_ VGA#

CLK_P CIE_VGA

CLK_P CIE_VGA#_R

CLK_P CIE_VGA_R

CLK _EXP#_R

CLK _EXP_R

PCIE_PTX_DRX_P4

PCIE _PRX_DTX_N4

PCIE_PRX_DTX_P4

PCIE _PTX_DRX_N4

C LK _ PC IE _CA RD _PCH #_R

CLK_P CIE _CA RD_ PCH_R

C L K_PC I_DB _R

XTAL25_IN

XTAL25_OUT

XTAL25_OUTCLK_P CIE_EXP_PCH_R

CLK_P CIE_EXP_PCH#_R

CLK REQ_EXP#

PCIE_PTX_DRX_P5

PCIE _PTX_DRX_N5

PCIE_PRX_DTX_P5

PCIE _PRX_DTX_N5

WLAN_CLK REQ1#<28>

C LK _P C IE _W LA N1<28 >

CLK_P CIE_WLA N1#<28>

PCIE_PTX_C_DRX_P2<28>

PCIE_PRX_DTX_N2<28>

PCIE_P TX_C_DRX_N2<28>

PCIE_PRX_DTX_P2<28>

PCIE_PTX_C_DRX_P3<29>

PCIE_PRX_DTX_N3<29>

PCIE_P TX_C_DRX_N3<29>

PCIE_PRX_DTX_P3<29>

SMB_EC_DA2_R <19,31>

SMB_EC_CK2_R <19,31>

EC_SMB_CK2 <34>

EC_SMB_DA2 <34>

CLK_14M_PCH <12>

SMB_CLK_S3 <10,11,12,28>

SMB_DATA_S3 <10,11,12,28>

CLK_D MI# <12>

C LK _D M I <12 >

CLK_B UF_B CLK <12>

CLK_B UF_B CLK # <12>

CLK_B UF_DOT96 <12>

CLK_B UF_DOT96# <12>

C LK _ BUF_ CK SS CD <12>

C L K_ BU F_ CK S SC D# < 12>

SMBCLK

SMBDATA

C LK _P C I_F B <1 6>

EC_LI D_O UT# < 34>

CLKRE Q _LA N#<29>

CLK_P CIE_LAN<29>

CLK_P CIE_LAN#<29>

PEG _CLKREQ# <19>

CLK_P CIE_VGA# <19>

CLK_P CIE_VGA <19>

CLK_EXP <5>

CLK_EXP# <5>

PCIE_PTX_C_DRX_P4<28>

PCIE_P TX_C_DRX_N4<28>

PCIE_PRX_DTX_N4<28>

PCIE_PRX_DTX_P4<28>

C LK _ PCIE _C AR D_P CH #<2 8>

C LK _ P CI E _C AR D_ PC H<28>

PCIECLKRE Q 3#<28>

C LK _P C I_D B <2 8>

CLK_P CIE_EXP_PCH<28>

CLK_P CIE_EXP_PCH#<28>

CLKREQ_EXP#<28>

PCIE_PTX_C_DRX_P5<28>

PCIE_PRX_DTX_N5<28>

PCIE_P TX_C_DRX_N5<28>

PCIE_PRX_DTX_P5<28>

+3VALW

+3VALW

+3VALW

+3VALW

+3VS

+3VALW

+3VS

+3VS

+3VS

+1.05VS

+3VS +3V A LW

+3VS

+3VS

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

IBEX-M(2/6)-PCI-E/SMBUS/CLK

C us t o m

14 51Thur sday, October 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

WLAN

WLAN

LAN

LAN

Nvidia

thermal

sensor

DTS , read from EC

DDR3*2 AND CLK GEN

EC_THERMAL

NEW CARD

WLAN

MINI1

LAN

WLAN

NEW CARD

LAN

6

4

DEVICEPORT

5

3

2

PCIE PORT LIST

1

7

8

X

X

X

GPIO11 = NATIVE,3.3V,SUS

GPIO60 = NATIVE,3.3V,SUS

GPIO74 = NATIVE,3.3V,SUS

GPIO47 = 10Kohm PULL DOWN

GPIO56 = NATIVE,3.3V,SUS

GPIO44 = NATIVE,3.3V,SUS

GPIO26 = NATIVE,3.3V,SUS

GPIO25 = NATIVE,3.3V,SUS

GPIO20 = NATIVE,3.3V,CORE

GPIO18 = NATIVE,3.3V,CORE

GPIO73 = NATIVE,3.3V,SUS

EMI REQUEST 0303

25MHz crystal not used, XTAL25_IN

need to GND.

(checklist Rev1.6)

3G

3G

3G

X

C631 Resistor Pull down

EXP

EXP

R 22 0 0_ 04 02_5 %

1 2

R 81 0_ 040 2_5%

@

1 2

R 22 3 0_ 04 02_5 %3G@

1 2

C 2 22 0. 1U _0 40 2_10 V6K

1 2

R 41 3

33_0402_5%

@

1 2

R 12 2

0_0402_5%

@

1 2

R 1 48 2. 2K _0 40 2_5%

1 2

R 4 04 2. 2K _0 40 2_5%

1 2

R 22 2 0_ 04 02_5 %3G@

1 2

R 5 98 1M _ 0402_ 5%@

1 2

C 2 31 0. 1U _0 40 2_10 V6K3G @

1 2

R 49 1 9 0. 9_ 04 02_1%

1 2

R106 0_0402_5%

1 2

R105 0_0402_5%

1 2

C 63 1

0_0402_5%

1

2

C 2 63

22P_0402_50V8J

@

R 43 4 10 K_ 04 02_5%

1 2

R79

0_0402_5%

R 22 4 0_ 04 02_5 %

1 2

C 2 21 0. 1U _0 40 2_10 V6K

1 2

C 2 32 0. 1U _0 40 2_10 V6K3G @

1 2

C 63 0

18P_0402_50V8J

@

1

2

R525 0_0402_5%

1 2

C 2 23 0. 1U _0 40 2_10 V6K

1 2

R 22 5 0_ 04 02_5 %

1 2

C 2 29 0. 1U _0 40 2_10 V6K

1 2

C 2 20 0. 1U _0 40 2_10 V6K

1 2

R 40 7

0_0402_5%

R 43 1 10 K_ 04 02_5%

1 2

R 45 7 10 K_ 04 02_5%

1 2

R 19 7 0_ 04 02_5 %

1 2

R 78 2. 2K_0 402_5%

1 2

Y4

25MHZ _20P_1BG25000CK1A

@

1 2

R 19 6 0_ 04 02_5 %

1 2

R524 0_0402_5%

1 2

R 4 121 0K _0 402_5%

1 2

R 1 47 2. 2K _0 40 2_5%

1 2

R 1 98

22_0402_5%

@

1 2

R 4 06 10 K _04 02_5%

1 2

R80

0_0402_5%

R 2 09

33_0402_5%

@

1 2

R 4 00 10 K _04 02_5 %

1 2

Q8B

2N7002DW-T/R7_SOT363-6

3

5

4

R 83 0_ 040 2_5%

@

1 2

R 43 5 10 K_ 04 02_5%

1 2

C 43 9

22P_0402_50V8J

@

R 4 03 2. 2K _0 40 2_5%

1 2

C 2 30 0. 1U _0 40 2_10 V6K

1 2

R 22 1 0_ 04 02_5 %

1 2

R 1 24

2.2K_ 0402_5%

R 1 45 10 K _04 02_5 %

1 2

R 11 9

0_0402_5%

@

1 2

R 1 23 2. 2K _0 40 2_5%

1 2

R 3 99 10 K _04 02_5 %

1 2

R 1 21 10 K _04 02_5%

1 2

PCI-E*

SMBus

Controller

From CLK BUFFER PEG

Clock Flex

Link

U7B

IB EXPEAK-M_FCBGA1071

PERN1

BG30

PERP1

BJ30

PERN2

AW30

PERP2

BA30

PERN3

AU30

PERP3

AT30

PERN4

BA32

PERP4

BB32

PERN5

BF33

PERP5

BH33

PERN6

BA34

PERP6

AW34

PERN7

AT34

PERP7

AU34

PERN8

BG34

PERP8

BJ34

PETN1

BF29

PETP1

BH29

PETN2

BC30

PETP2

BD30

PETN3

AU32

PETP3

AV32

PETN4

BD32

PETP4

BE32

PETN5

BG32

PETP5

BJ32

PETN6

BC34

PETP6

BD34

PETN7

AU36

PETP7

AV36

PETN8

BG36

PETP8

BJ36

SMBALERT# / GPIO11 B9

SMBCLK H14

SMBDATA C8

SML0CLK C6

SML0DATA G8

CLKOUT_PCIE0N

AK48

CLKOUT_PCIE0P

AK47

CLKOUT_PCIE1N

AM43

CLKOUT_PCIE1P

AM45

CLKOUT_PCIE2N

AM47

CLKOUT_PCIE2P

AM48

CLKOUT_PCIE3N

AH42

CLKOUT_PCIE3P

AH41

CLKOUT_PCIE4N

AM51

CLKOUT_PCIE4P

AM53

CLKOUT_PCIE5N

AJ50

CLKOUT_PCIE5P

AJ52

SML0ALERT# / GPIO60 J14

CL_CLK1 T13

CL_DATA1 T11

CL_RST1# T9

CLKIN_BCLK_N AP3

CLKIN_BCLK_P AP1

CLKIN_DMI_N AW24

CLKIN_DMI_P BA24

CLKIN_DOT_96N F18

CLKIN_DOT_96P E18

CLKIN_SATA_N / CKSSCD_N AH13

CLKIN_SATA_P / CKSSCD_P AH12

XTAL25_IN AH51

XTAL25_OUT AH53

REFCLK14IN P41

CLKIN_PCILOOPBACK J42

CLKOUT_PEG_A_N AD43

CLKOUT_PEG_A_P AD45

PEG_A_CLKRQ# / GPIO47 H1

PCIECLKRQ0# / GPIO73

P9

PCIECLKRQ1# / GPIO18

U4

PCIECLKRQ2# / GPIO20

N4

PCIECLKRQ3# / GPIO25

A8

PCIECLKRQ4# / GPIO26

M9

PCIECLKRQ5# / GPIO44

H6

CLKOUTFLEX0 / GPIO64 T45

CLKOUTFLEX1 / GPIO65 P43

CLKOUTFLEX2 / GPIO66 T42

CLKOUTFLEX3 / GPIO67 N50

CLKOUT_DMI_N AN4

CLKOUT_DMI_P AN2

PEG_B_CLKRQ# / GPIO56

P13

CLKOUT_PEG_B_P

AK51 CLKOUT_PEG_B_N

AK53

SML1ALERT# / GPIO74 M14

SML1CLK / GPIO58 E10

SML1DATA / GPIO75 G12

XCLK_RCOMP AF38

CLKOUT_DP_P / CLKOUT_BCLK1_P AT3

CLKOUT_DP_N / CLKOUT_BCLK1_N AT1

R 11 3 10 K_ 04 02_5%

1 2

R82

2.2K_ 0402_5%

R 12 0 10 K_ 04 02_5%

1 2

Q7B

2N7002DW-T/R7_SOT363-6

3

5

4

Q8A

2N7002DW-T/R7_SOT363-6

6 1

2

R 45 4 10 K_ 04 02_5%

1 2

Q7A

2N7002DW-T/R7_SOT363-6

6 1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PM_RSMRST#

SLP_S4#

SLP_S5#

SYS _RST#

PM_DRA M _PWRGD

GPIO 61

GPIO 62

S YS_ PWRO K

SLP_S3#

GPIO 72

PBT N_OUT#

DM I _CTX_PRX_N2

DM I _CRX_PTX_N0

DM I _CRX_PTX_N1

DM I _CRX_PTX_N2

DM I _CRX_PTX_N3

DMI_CRX_PTX_P0

DMI_CRX_PTX_P1

DMI_CRX_PTX_P2

DMI_CRX_PTX_P3

DM I _CTX_PRX_N1

DM I _CTX_PRX_N0

PM_RSMRST#

DM I _CTX_PRX_N3

DMI_CTX_PRX_P1

DMI_CTX_PRX_P2

DMI_CTX_PRX_P0

DMI_CTX_PRX_P3

DM I_IRCO MP

AC_PRE SENT_R

PCIE_W A KE#

CRT _I REF

FDI_CT X_PRX_N0

FDI_CT X_PRX_N1

FDI_CT X_PRX_N2

FDI_CT X_PRX_N3

FDI_CT X_PRX_N4

FDI_CT X_PRX_N6

FDI_CT X_PRX_N5

FDI_CTX_PRX_P1

FDI_CT X_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P3

FDI_CTX_PRX_P2

FDI_CTX_PRX_P6

FDI_CTX_PRX_P5

FDI_CTX_PRX_P4

FDI_CTX_PRX_P7

F DI _IN T

F DI _F S YN C 1

F DI _F S YN C 0

FDI_LS Y NC1

FDI_LS Y NC0

PCH_E NVD D

EDID_DATA

E DI D _CL K

DA C _BLU

DA C_ R ED

DA C_ G RN

HD MIC LK_N B

HDMIDA T_NB

TMDS_B _ DATA2#_PCH

TMDS_B _ DATA2_PCH

TMDS_B _ DATA1#_PCH

TMDS_B _ DATA0#_PCH

TMDS_B _CLK#_PCH

TMDS_B _ DATA1_PCH

TMDS_B _ DATA0_PCH

TMDS_B _CLK_PCH

DA C _BLU

DA C_ R ED

DA C_ G RN

PCH_E NBKL

E DI D _CL K

EDID_DATA

SUS _PW R_DN_A CK_R

S YS_ PWRO K

VGATE

I C H_P OK

VGATE<48>

I C H_ PO K<3 4>

PBT N_OUT#<34>

PM_DRA M _PWRGD<5>

PCIE_W AKE# <28>

SLP_S5# <34>

H _P M _S YN C <5>

SLP_S4# <34>

SLP_S3# <34>

EC_RS M RST#<34>

DM I_CRX_PTX_N0<6>

DM I_CTX_PRX_N0<6>

DM I_CTX_PRX_N1<6>

DM I_CTX_PRX_N2<6>

DM I_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6>

DMI_CTX_PRX_P1<6>

DMI_CTX_PRX_P2<6>

DMI_CTX_PRX_P3<6>

DM I_CRX_PTX_N1<6>

DM I_CRX_PTX_N2<6>

DM I_CRX_PTX_N3<6>

DMI_CRX_PTX_P0<6>

DMI_CRX_PTX_P1<6>

DMI_CRX_PTX_P2<6>

DMI_CRX_PTX_P3<6>

AC_PRE SENT<34>

FDI_CTX_PRX_N0 <6>

FDI_CTX_PRX_N1 <6>

FDI_CTX_PRX_N3 <6>

FDI_CTX_PRX_N2 <6>

FDI_CTX_PRX_N5 <6>

FDI_CTX_PRX_N4 <6>

FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_N6 <6>

FDI_CTX_PRX_P1 <6>

FDI_CTX_PRX_P0 <6>

FDI_CTX_PRX_P3 <6>

FDI_CTX_PRX_P2 <6>

FDI_CTX_PRX_P4 <6>

FDI_CTX_PRX_P5 <6>

FDI_CTX_PRX_P7 <6>

FDI_CTX_PRX_P6 <6>

F D I_ I NT <6 >

FDI_FS Y N C 0 <6>

F DI _ LS Y NC 0 <6>

FDI_FS Y N C 1 <6>

F DI _ LS Y NC 1 <6>

LV DS_A CLK#<27>

LV DS_A CLK<27>

LV DS_A0#<27>

LV DS_A1#<27>

LV DS_A2#<27>

LV DS_A0<27>

LV DS_A1<27>

LV DS_A2<27>

EDID_DATA<27>

P CH _ E NV DD<27>

PCH_P W M<27>

E D I D_C LK<27>

C RT _ HS Y NC<2 6>

C RT _ V SY NC< 26>

C RT _ D DC _C LK< 26>

C RT _D DC _D AT A<26>

D A C _B LU<26 >

D AC_G R N<26>

D A C_ R E D< 26>

TMDS_B_HPD# <25>

HDMIDA T_NB <25>

H D MI CL K_ NB <2 5>

P CH _E NB KL<27>

S U S_ P WR _D N_A C K<34>

TMDS_B_DATA2# <25>

TMDS_B_DATA2 <25>

TMDS_B_DATA1# <25>

TMDS_B_DATA1 <25>

TMDS_B_DATA0# <25>

TMDS_B_DATA0 <25>

TMDS_B_CLK# <25>

TMDS_B_CLK <25>

+3VALW

+3VS

+3VALW

+3VALW

+3VALW

+1.05VS

+3VS

+3VALW

+3VS

+3VS

+3VS

+3VS

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

IBEX-M(3/6)-DMI/GPIO/LVDS

C us t o m

15 51Thur sday, October 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

GPIO61 = NATIVE,3.3V,SUS

GPIO62 = NATIVE,3.3V,SUS

Checklist0.8 MEPWROK

can be connect to

PWROK if iAMT disable

If not using integrated

LAN,signal may be left as NC.

Can be left NC when IAMT is

not support on the platfrom

GPIO29 = GPO,3.3V,SUS

GPIO31 = GPI,3.3V,SUS

GPIO30 = GPI,3.3V,SUS

RSMRST circuit

4mil width and place

within 500mil of the PCH

GPIO32 = GPO,3.3V,CORE

CRT OUT

(2009,05,04)

update R492 tolerance for

DAC_CRT from 0.5% to 5%

(checklist 2.0)

HDMI

Reserved

(2009,09,08)

R 4 18 1 0K _0 402 _5%@

1 2

R 4 96 10 K _04 02_5 %

1 2

R 14 6 1 0K _0 402_ 5%

1 2

R 4 17 1 0K _0 402 _5%@

1 2

C 64 0 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

R77 8.2K_0402_1%

1 2

T10 P AD

LVDS

Digital Display Interface

CRT

U7D

IB E XPEAK-M_FCBGA1071

L_BKLTCTL

Y48

L_BKLTEN

T48

L_CTRL_CLK

AB46

L_CTRL_DATA

V48

L_DDC_CLK

AB48

L_DDC_DATA

Y45

L_VDD_EN

T47

LVDSA_CLK#

AV53

LVDSA_CLK

AV51

LVDSA_DATA#0

BB47

LVDSA_DATA#1

BA52

LVDSA_DATA#2

AY48

LVDSA_DATA#3

AV47

LVDSA_DATA0

BB48

LVDSA_DATA1

BA50

LVDSA_DATA2

AY49

LVDSA_DATA3

AV48

LVDSB_CLK#

AP48

LVDSB_CLK

AP47

LVDSB_DATA#0

AY53

LVDSB_DATA#1

AT49

LVDSB_DATA#2

AU52

LVDSB_DATA#3

AT53

LVDSB_DATA0

AY51

DDPB_0N BD42

DDPB_1N BJ42

LVD_VREFH

AT43

LVD_VREFL

AT42

DDPD_2N BF37

DDPD_3N BE36

DDPB_2N BB40

DDPB_3N AW38

DDPC_0N BE40

DDPC_1N BF41

DDPC_2N BD38

DDPC_3N BB36

DDPD_0N BJ40

DDPD_1N BJ38

DDPB_0P BC42

DDPB_1P BG42

DDPD_2P BH37

DDPD_3P BD36

DDPB_2P BA40

DDPB_3P BA38

LVDSB_DATA1

AT48

LVDSB_DATA2

AU50

LVDSB_DATA3

AT51

LVD_IBG

AP39

LVD_VBG

AP41

DDPC_1P BH41

DDPC_0P BD40

DDPC_2P BC38

DDPC_3P BA36

DDPD_0P BG40

DDPD_1P BG38

CRT_BLUE

AA52

CRT_DDC_CLK

V51

CRT_DDC_DATA

V53

CRT_GREEN

AB53

CRT_HSYNC

Y53

CRT_IRTN

AB51

CRT_RED

AD53

CRT_VSYNC

Y51

DAC_IREF

AD48

SDVO_CTRLCLK T51

SDVO_CTRLDATA T53

DDPC_CTRLCLK Y49

DDPC_CTRLDATA AB49

DDPD_CTRLCLK U50

DDPD_CTRLDATA U52

DDPB_AUXN BG44

DDPC_AUXN BE44

DDPD_AUXN BC46

DDPB_AUXP BJ44

DDPC_AUXP BD44

DDPD_AUXP BD46

DDPB_HPD AU38

DDPC_HPD AV40

DDPD_HPD AT38

SDVO_TVCLKINP BG46

SDVO_TVCLKINN BJ46

SDVO_STALLP BG48

SDVO_STALLN BJ48

SDVO_INTP BH45

SDVO_INTN BF45

R 4 16 1 0K _0 402 _5%@

1 2

C 64 2 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

C 64 4 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

C 64 1 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

R 39 8 0_ 04 02_5 %@

1 2

R 4 50 10 K _04 02_5 %

1 2

R 1 08 10 K _04 02_5%

1 2

DMI

FDI

System Power Management

U7C

IB EXPEAK-M_FCBGA1071

DMI0RXN

BC24

DMI1RXN

BJ22

DMI2RXN

AW20

DMI3RXN

BJ20

DMI0RXP

BD24

DMI1RXP

BG22

DMI2RXP

BA20

DMI3RXP

BG20

DMI0TXN

BE22

DMI1TXN

BF21

DMI2TXN

BD20

DMI3TXN

BE18

DMI0TXP

BD22

DMI1TXP

BH21

DMI2TXP

BC20

DMI3TXP

BD18

DMI_ZCOMP

BH25

DMI_IRCOMP

BF25

FDI_RXN0 BA18

FDI_RXN1 BH17

FDI_RXN2 BD16

FDI_RXN3 BJ16

FDI_RXN4 BA16

FDI_RXN5 BE14

FDI_RXN6 BA14

FDI_RXN7 BC12

FDI_RXP0 BB18

FDI_RXP1 BF17

FDI_RXP2 BC16

FDI_RXP3 BG16

FDI_RXP4 AW16

FDI_RXP5 BD14

FDI_RXP6 BB14

FDI_RXP7 BD12

FDI_FSYNC0 BF13

FDI_FSYNC1 BH13

FDI_LSYNC0 BJ12

FDI_LSYNC1 BG14

FDI_INT BJ14

PMSYNCH BJ10

TP23 N2

SLP_M# K8

SLP_S3# P12

SLP_S4# H7

SLP_S5# / GPIO63 E4

SYS_RESET#

T6

SYS_PW ROK

M6

PWRBTN#

P5

RI#

F14

WAKE# J12

SUS_STAT# / GPIO61 P8

SUSCLK / GPIO62 F3

ACPRESENT / GPIO31

P7

LAN_RST#

A10

MEPWROK

K5

BATLOW# / GPIO72

A6

PWROK

B17

CLKRUN# / GPIO32 Y1

SUS_PWR_DN_ACK / GPIO30

M1

RSMRST#

C16

DRAMPWROK

D9

SLP_LAN# / GPIO29 F6

R 5 20 4 9. 9_ 04 02_1 %

1 2

C 64 3 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

C 64 5 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

R 16 5 10 K_ 040 2_5%

1 2

D 8B

BAV 99DW-7_SOT363

4

5

3

R 4 58 2. 2K _ 040 2_5%UMA@

C

B

E

Q14

MMBT3906_SOT23-3

1

2

3

R 4 01

10K_0402_5%

12

R 50 4

2.2K_ 0402_5%

UM A@

12

R 4 37 1 0K _0 402_5 %

1 2

C 63 8 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

R 4 95 15 0_ 04 02_1%UMA@

1 2

R 50 3

2.2K_ 0402_5%

UM A@

12

R 1 76 4 .7 K_ 04 02_5%

1 2

R 4 48

10K_0402_5%

1 2

C 63 9 0. 1U _0 40 2_10V 6KUM A _HDMI@

1 2

R 17 5

2.2K_ 0402_5%

1 2

U28

MC74V HC1G08DFT 2G S C70 5P

@

B

2

A

1

Y4

P

5G3

R 5 10 1 0K _0 402 _5%

12

R 45 1 0 _04 02_ 5%

1 2

R 5 02

2.37K _0402_1%

12

R 5 99 0 _0 402 _5%@

1 2

R 4 97

10K_0402_5%

1 2

R 4 94 15 0_ 04 02_1%UMA@

1 2

R 39 7 0_ 04 02_5 %

1 2

R 4 93 15 0_ 04 02_1%UMA@

1 2

R 40 2

0_0402_5%

@

1 2

R 43 6

10K_0402_5%

1 2

R 4 55

0_0402_5%

1 2

R 4 98 2. 2K _ 040 2_5%UMA@

R 49 2

1K _0402_5%

12

R 3 96 10 0K _0 402_ 1%

12

D8A

BAV 99DW-7_SOT363

1

2

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

US B RBIA S

US B 20_N0

US B 20_P0

US B 20_N5

US B 20_P5

US B 20_P10

US B 20_N10

US B 20_N8

US B 20_P8

US B 20_P2

US B 20_N2

US B _OC #4

NV _RC OMP

EC_S MI#

H _ PE CI

KB_RST#

US B 20_N1

US B 20_P1

PLT_RST#

US B _OC #0

GPI O0

PCI_FRAME#

PCI_DEVS EL#

PCI_STOP#

PCI_LOCK #

P CI _ TR DY #

P CI _IRD Y#

P C I_PE RR#

P C I_SE RR#

PCI_PIRQA #

P CI _ PIRQ D#

PCI_PIRQE #

P CI _ PIRQ H#

PCI_PIRQB #

P C I_PI RQF#

P CI _ PIRQ C#

P CI _PIRQG#

PCI_REQ2#

PCI_REQ1#

PCI_REQ3#

PCI_REQ0#

PLT_RST#

PCI_GNT0#

PCI_GNT1#

PCI_GNT3#

N V_C LE

NV _A LE

PCI_GNT1#

PCI_GNT0#

US B 20_N11

US B 20_P11

US B 20_N13

US B 20_P13

US B _OC #1

US B _OC #2

US B _OC #3

US B _OC #5

US B _OC #6

US B _OC #7

US B _OC #2

US B _OC #7

US B _OC #4

US B _OC #0

US B _OC #3

US B _OC #5

US B _OC #1

US B _OC #6

GPI O1

GPI O6

GPIO 15

GPIO 22

GPIO 28

GPIO 35

GPIO 37

GPIO 38

GPIO 39

GPIO 45

GPIO 48

C L K_PC I_LP C_R

C L K_PC I_FB _R

C PUS B#

GPIO 34

KB_RST#

IN T3_ 3V#

TP24

PCH_TEMP_ALERT#

EC_S MI#

E C _SCI #

PCH_TEMP_ALERT#

PCI_DEVS EL#

P CI _ TR DY #

PCI_FRAME#

PCI_STOP#

PCI_LOCK #

P CI _IRD Y#

P C I_PE RR#

P C I_SE RR#

PCI_REQ3#

PCI_REQ0#

PCI_REQ1#

PCI_REQ2#

P CI _ PIRQ H#

PCI_PIRQE #

P CI _ PIRQ D#

PCI_PIRQA #

P CI _ PIRQ C#PCI _PIR QB#

P C I_PI RQF#

P CI _PIRQG#

E C _SCI #

US B 20_P3

US B 20_N3

PCI_GNT3#

GPIO 16

GPIO 17

GPIO 36

GPIO 36

GPIO 17

GPIO 16

H_THE RMTRIP#_L

PCI_GNT2#

NV _A LE

N V_C LE

DRAMRS T_CNTRL_P CH GPI O 46

DRAMRS T_CNTRL_P CH

GPIO 57

US B 20_N0 <37>

US B 20_P0 <37>

US B 20_N2 <27>

US B 20_P2 <27>

US B 20_N5 <38>

US B 20_P5 <38>

US B 20_N8 <28>

US B 20_P8 <28>

US B 20_N10 <28>

US B 20_P10 <28>

BUF_PLT_RST#<5,19,28,29>

GATEA20 <34>

H _C P UP W R GD <5>

H _P E CI <5 >

H_THE RMTRIP# <5>

KB_ RST# <34>

US B _OC #0 <37>

C LK _C P U_B C LK <5>

CLK_C PU_BCLK # <5>

PCI_PME#<34>

PCI_RST#<28,34>

US B 20_N11 <37>

US B 20_P11 <37>

C LK _P C I_L P C<34 >

C LK _P C I_F B<1 4>

C P US B#<2 8>

EC_SMI#<34>

E C _S CI #<3 4>

US B 20_N1 <37>

US B 20_P1 <37>

US B 20_N13 <28>

US B 20_P13 <28>

US B 20_N3 <37>

US B 20_P3 <37>

US B _OC #1 <37>

SUS P#<28,34,39,42,44,46> VGA _EN <45>

DRAMRS T_CNTRL_P CH<5>

PCH_TEMP_ALERT#<34>

+3VS +3VS

+ V CC P

+3VS

+3VALW

+3VS

+3VS

+1.8VS

+3VALW

+3VALW

+3VALW

+3VALW

+3VS

+3VALW

+3VS

+3VS

+3VALW

+3VS

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

IBEX-M(4/6)-PCI/USB/RSVD

C us t o m

16 51Thur sday, October 29, 2009

2008/08/12 2009/08/12

Compal Electronics, Inc.

LA-5752P

Within 500 mils minimum spacing to other

signal is 15mil

LEFT USB (COMBO)

Bluetooth

3G CARD

CARD READER

EXPRESS

WLAN

USB Camera

GPIO27 if pull down to turn off 1.8V VR

GPIO8

Weak internal PU, don't PD

*

GNT2

Default-Internal pull up

Low=Configures DMI for ESI

compatible operation(for

servers only.Not for

mobile/desktops)

*

override/Top-Block

Low=A16 swap

PCI_GNT3#

A16 swap overide Strap/Top-Block

Swap Override jumper

Swap Override enabled

High=Default

Intel Anti-Theft Techonlogy

*

Weak internal

PU,Do not pull low

Set to Vcc when HIGH

DMI Termination Voltage

NV_ALE

High=Enabled

Low=Disable(floating)

NV_CLE

Set to Vss when LOW

NV_ALE

NV_CLE

Enable Intel Anti-Theft

Technology 8.2K PU to +3VS

Disable Intel Anti-Theft

Technology floating(internal PD)

DMI termination voltage.

weak internal PU, don't PD

11

PCI_GNT1#PCI_GNT0#

0

Boot BIOS

Location

1

LPC

Boot BIOS Strap

PCI

0

Reserved(NAND)

SPI

1

0

0

*

GPIO27

GPIO15

*

5

BT

3G

6

4

CMOS

RIGHT SIDE0

DEVICEPORT

3

2

11

NEW CARD

USB PORT LIST

WIRELESS8

10

1

CARD READER

9

7

12

13

GPIO18 = NATIVE,5V,CORE

GPIO52 = NATIVE,5V,CORE

GPIO54 = NATIVE,5V,CORE

GPIO2 = GPI,5V,CORE

GPIO3 = GPI,5V,CORE

GPIO4 = GPI,5V,CORE

GPIO5 = GPI,5V,CORE

GPIO0 = GPI,3.3V,CORE

RIGHT USB

LEFT USB

LEFT SIDE

LEFT SIDE

56 5%-->checklist 1.6

54.9 1%-->CRB 1.0

H Intel ME Crypto Transport

Layer Security(TLS) chiper suite

with confidentiality

L Intel ME Crypto Transport

Layer Security(TLS) chiper suite

with no confidentiality

High Enables the internal VccVRM

to have a clean supply for analog

rails. no need to use on board

filter circuit.

Default Do not connect(floating)

it have weak internal PU 20K

GPIO12 = GPI,3.3V,SUS

GPIO8 = GPO,3.3V,SUS

GPIO7 = GPI,3.3V,CORE

GPIO6 = GPI,3.3V,CORE

GPIO1 = GPI,3.3V,CORE

Check list Rev0.8 section1.23.2

If not implemented, the

Braidwood

interface signals can be

left as No Connect (NC).

within 500mil

6

checklist 2.0 update 2009.0916

R 4 29 1 0K _0 402 _5%

1 2

R 42 71 0K _0 402 _5%

1 2

R 21 2 1K _0 40 2_5%@

1 2

R 1 99 22 _0 402 _5%

1 2

R506 0_0402_5%

D I S@

1 2

R 60 9 1 0K _0 402_5 %

@

1 2

R 44 91 0K _0 402 _5%

1 2

R 4 26 1 0K _0 402 _5%

@

1 2

RP5

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

R98 1K _0402_5%@

1 2

R 45 61 0K _0 402 _5%

12

R 1 64 2 2. 6_ 04 02_1 %

1 2

R 2 00 1 K_ 04 02_5%@

1 2

GPIO

MISC

NCTF

RSVD

CPU

U 7F

IB EXPEAK-M_FCBGA1071

GPIO27

AB12

GPIO28

V13

GPIO24

H10

GPIO57

F8

LAN_PHY_PWR_CTRL / GPIO12

K9

VSS_NCTF_1

A4

VSS_NCTF_2

A49

VSS_NCTF_3

A5

VSS_NCTF_4

A50

VSS_NCTF_5

A52

VSS_NCTF_6

A53

VSS_NCTF_7

B2

VSS_NCTF_8

B4

VSS_NCTF_9

B52

VSS_NCTF_10

B53

VSS_NCTF_11

BE1

VSS_NCTF_12

BE53

VSS_NCTF_13

BF1

VSS_NCTF_14

BF53

VSS_NCTF_15

BH1

VSS_NCTF_16

BH2

VSS_NCTF_17

BH52

VSS_NCTF_18

BH53

VSS_NCTF_19

BJ1

VSS_NCTF_20

BJ2

VSS_NCTF_21

BJ4

VSS_NCTF_22

BJ49

VSS_NCTF_23

BJ5

VSS_NCTF_24

BJ50

VSS_NCTF_25

BJ52

VSS_NCTF_26

BJ53

VSS_NCTF_27

D1

VSS_NCTF_28

D2

VSS_NCTF_29

D53

VSS_NCTF_30

E1

VSS_NCTF_31

E53

TACH2 / GPIO6

D37

TACH0 / GPIO17

F38

TACH3 / GPIO7

J32

TP9 M18

TP10 N18

TP11 AJ24

TP12 AK41

SATA3GP / GPIO37

AB13

SATA5GP / GPIO49

AA4

SCLOCK / GPIO22

Y7

SLOAD / GPIO38

V3

SDATAOUT0 / GPIO39

P3

SDATAOUT1 / GPIO48

AB6

A20GATE U2

PROCPWRGD BE10

RCIN# T1

PECI BG10

THRMTRIP# BD10

GPIO8

F10

CLKOUT_PCIE6N AH45

CLKOUT_PCIE6P AH46

PCIECLKRQ6# / GPIO45

H3

CLKOUT_PCIE7N AF48

CLKOUT_PCIE7P AF47

PCIECLKRQ7# / GPIO46

F1

TP5 AY46

TP4 AY45

TP6 AV43

TP7 AV45

BMBUSY# / GPIO0

Y3

TP16 M30

TP17 N30

NC_1 AB45

NC_2 AB38

NC_3 AB42

NC_4 AB41

GPIO15

T7

TACH1 / GPIO1

C38

TP13 AK42

TP3 BB22

TP1 BA22

TP2 AW22

TP14 M32

TP15 N32

SATA2GP / GPIO36

AB7

NC_5 T39

INIT3_3V# P6

STP_PCI# / GPIO34

M11

SATACLKREQ# / GPIO35

V6

SATA4GP / GPIO16

AA2

TP24 C10

TP8 AF13

CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3

CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1

TP19 AA23

TP18 H12

R 1 10

10K_0402_5%

1 2

R 11 1

10K_0402_5%

12

PCI

NVRAM

USB

U 7E

IB EXPEAK-M_FCBGA1071

AD0

H40

AD1

N34

AD2

C44

AD20

C42

AD21

K46

AD22

M51

AD23

J52

AD24

K51

AD25

L34

AD26

F42

AD27

J40

AD28

G46

AD29

F44

AD3

A38

AD30

M47

AD31

H36

AD4

C36

AD5

J34

AD6

A40

AD7

D45

AD8

E36

AD9

H48

C/BE0#

J50

C/BE1#

G42

C/BE2#

H47

C/BE3#

G34

PCIRST#

K6

PERR#

E50

PIRQA#

G38

PIRQB#

H51

PIRQC#

B37

PIRQD#

A44

PLOCK#

D49

PLTRST#

D5

PME#

M7

REQ0#

F51

REQ1# / GPIO50

A46

REQ2# / GPIO52

B45

REQ3# / GPIO54

M53

SERR#

E44

STOP#

D41

TRDY#

C48

NV_ALE BD3

NV_CE#0 AY9

NV_CE#1 BD1

NV_CE#2 AP15

NV_CE#3 BD8

NV_CLE AY6

NV_DQS0 AV9

NV_DQS1 BG8

NV_DQ0 / NV_IO0 AP7

NV_DQ1 / NV_IO1 AP6

NV_DQ10 / NV_IO10 BD6

NV_DQ11 / NV_IO11 BB7

NV_DQ12 / NV_IO12 BC8

NV_DQ13 / NV_IO13 BJ8

NV_DQ14 / NV_IO14 BJ6

NV_DQ15 / NV_IO15 BG6

NV_DQ2 / NV_IO2 AT6

NV_DQ3 / NV_IO3 AT9

NV_DQ4 / NV_IO4 BB1

NV_DQ5 / NV_IO5 AV6

NV_DQ6 / NV_IO6 BB3

NV_DQ7 / NV_IO7 BA4

NV_DQ8 / NV_IO8 BE4

NV_DQ9 / NV_IO9 BB6

NV_RB# AV7

NV_RCOMP AU2

NV_WR#0_RE# AY8

NV_WR#1_RE# AY5

NV_WE#_CK0 AV11

NV_WE#_CK1 BF5

USBP0N H18

USBP0P J18

USBP10N A22

USBP10P C22

USBP11N G24

USBP11P H24

USBP12N L24

USBP12P M24

USBP13N A24

USBP13P C24

USBP1N A18

USBP1P C18

USBP2N N20

USBP2P P20

USBP3N J20

USBP3P L20

USBP4N F20

USBP4P G20

USBP5N A20

USBP5P C20

USBP6N M22

USBP7N B21

USBP7P D21

USBP8N H22

USBP8P J22

USBP9N E22

USBP9P F22

USBRBIAS# B25

USBRBIAS D25

USBP6P N22

AD10

E40

AD11

C40

AD12

M48

AD13

M45

AD14

F53

AD15

M40

AD16

M43

AD17

J36

AD18

K48

AD19

F40

DEVSEL#

F46

FRAME#

C46

GNT0#

F48

GNT1# / GPIO51

K45

GNT2# / GPIO53

F36

GNT3# / GPIO55

H53

PIRQE# / GPIO2

B41

PIRQF# / GPIO3

K53

PIRQG# / GPIO4

A36

PIRQH# / GPIO5

A48

IRDY#

A42

PAR

H44

OC0# / GPIO59 N16

OC1# / GPIO40 J16

OC2# / GPIO41 F16

OC3# / GPIO42 L16

OC4# / GPIO43 E14

OC5# / GPIO9 G16

OC6# / GPIO10 F12

OC7# / GPIO14 T15

CLKOUT_PCI0

N52

CLKOUT_PCI1

P53

CLKOUT_PCI2

P46

CLKOUT_PCI3

P51

CLKOUT_PCI4

P48

R 4 85 1 0K _0 402 _5%

1 2

R P 6

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

R 4 14 1 0K _0 402 _5%

@

1 2

R 48 31 0K _0 402 _5%

1 2

R P 2

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

R 10 91 0K _0 402 _5%

1 2

R 1 07 1 0K _0 402 _5%

12

R7610K_0 402_5%

1 2

R 48 01 0K _0 402 _5%

1 2

R149 0_0402_5%

1 2

R 4 84 1 0K _0 402 _5%

1 2

RP4

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

R P 1

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

R 50 71 0K _0 402 _5%

@

12

R 1 04

32.4_0402_1%

@

1 2

R 4 05 10 K_ 04 02_5%

12

R 42 81 0K _0 402 _5%

1 2

R 15 5

100K_0402_5%

12

R P 3

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

RP7

8.2K_ 0804_8P4R_5%

1 8

2 7

3 6

4 5

R 11 21 0K _0 402 _5%

1 2

R 41 5 1 0K _0 402_5 %

1 2

R 5 18

56_0402_5%

1 2

R 48 11 0K _0 402 _5%

1 2

R 44 61 0K _0 402 _5%

1 2

R 4 08 1 00 K_ 0402_ 1%

12

R 2 11 22 _0 402 _5%

1 2

R 43 31 K _04 02_5 %

1 2

R 51 5 1K _0 40 2_5%@

1 2

U5

MC74V HC1G08DFT 2G S C70 5P

@

B2

A1

Y

4

P

5G3

R 21 0 1K _0 40 2_5%@

1 2

R 43 21 0K _0 402 _5%

12

R 51 9

56_0402_5%

12

C 6 46

0.1U_0402_16V4Z

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

P CH _V5REF_SUS

+P CH_VCC1_1_23

P CH _V5REF_SUS

+P CH_VCC1_1_22

+P CH_VCC1_1_20

+V 1.1A_INT_V CCSUS

+V C CSST

+P CH_VCC1_1_21

+V C CRTCEXT

P CH _V 5 REF_ RUN

P CH _V 5 REF_ RUN

+V C CTX_LVDS

+V CCA_LVDS

+1.05VS

+1.05VS

+1.05VS

+3VS

+3VS

+ V CC P

+3VS

+P CH_VRM

+1.05VS

+3VALW

+3VS

+ V CC P

+ R TC VC C

+1.05VS

+3VS

+1.05VS

+1.05VS

+3VALW

+1.05VS

+5VS +3VS+3VALW+5VALW

+3VS

+3VS

+P CH_VRM

+1.05VS

+P CH_VRM

+3VALW

+1.05VS

+3VS_DAC

+3VS

+1.8VS

+3VALW

+1.05VS

+3VS

+1.8VS

+V CCADPLLB

+V CCADPLLA+1.05VS

+V CCADPLLA

+V CCADPLLB

+P CH_VRM +1.8VS

+1.5V

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

IBEX-M(5/6)-PWR

C us t o m

17 51Thur sday, October 29, 2009

2008/08/12 2009/08/12

Compal Electronics, Inc.

LA-5752P

20 mils20 mils

3.208A

0.163A

1.998A

0.344A

0.052A

0.035A

0.072A

0.073A 0.357A

2mA

>1mA

>1mA

6mA

0.032A

0.069A

0.030A

0.156A

6mA

0.035A

0.061A

0.059A

0.085A

0.042A

1.524A

>1mA

UPDATE 0210

DG1.1 no M3

support and not

Intel LAN, VCCLAN

Source=>GND

0.1uH inductor, 200mA

10uH inductor, 120mA

10uH inductor, 120mA

lsolate AF32,AF34,AH34

from AH35,AJ35

for Intel request 09.09.08

C 4 55

0.1U_0402_16V4Z

1

2

C 45 3

0.1U_0402_16V4Z

1 2

C 4 71

1U_0402_6.3V6K

1

2

C 4 75

1U_0402_6.3V6K

1

2

C 45 4

0.1U_0402_16V4Z

1 2

C 13 9

0.1U_0402_16V4Z

1 2

C 5 00

4.7U_0603_6.3V6K

1

2

C 4 89

0.1U_0402_16V4Z

1

2

L26

10UH_LB 2012T100MR_20%

1 2

D6

CH751H- 40P T_SOD323-2

21

C 4 92

10U_0805_6.3V6M

UM A@

1

2

R 50 9

0_0402_5%

1 2

R 4 89 0_ 04 02_ 5%

1 2

C 22 4

0.1U_0402_16V4Z

1

2

R410 0_0402_5%

1 2

C 47 4

1U_0402_6.3V6K

1

2

D9

CH751H- 40P T_SOD323-2

21

R411 0_0402_5%

@

1 2

C 48 3

1U_0402_6.3V6K

1

2

C 4 68

0.1U_0402_16V4Z

1

2

C 4 93

1U_0402_6.3V4Z

@

1

2

R 42 3

10_0402_1%

1 2

R 2 08

0_0603_5%

1 2

R 4 88 0_ 04 02_ 5%

1 2

R 21 3 0 .0 22 _0 805_1%UMA@

1 2

C 2 62

10U_0805_6.3V6M

1

2

R 4 90 0_ 04 02_ 5%

1 2

C 46 3

0.1U_0402_16V4Z

1 2

C 48 6

0.01U_0402_16V7K

UM A@

1

2

R 5 21

0_0402_5%

@

12

R 4 87 0_ 04 02_ 5%

1 2

L 28

0.1UH_M LF1608DR10K T_10%_1608

UM A@

12

C 4 77

0.01U_0402_16V7K

@

1

2

C491 1U_0402_6.3V6K

1 2

C 4 84

1U_0402_6.3V6K

1

2

C 4 72

1U_0402_6.3V6K

1

2

C 4 65

1U_0402_6.3V6K

1

2

C 47 3

1U_0402_6.3V6K

1

2

C 4 64

1U_0402_6.3V6K

1

2

R501 0_0402_5%

@

1 2

C 48 5

0.01U_0402_16V7K

UM A@

1

2

C 4 94

1U_0402_6.3V4Z

@

1

2

+

C 5 07

220U_B2_2.5VM_R35

UM A@

1

2

C 45 2

0.1U_0402_16V4Z

1 2

C 4 76

0.1U_0402_16V4Z

1

2

C 4 78

0.1U_0402_16V4Z

1

2

POWER

VCC CORE

DMI

PCI E*

CRTLVDS

FDI

NAND / SPI HVCMOS

U7G

IB EXPEAK-M_FCBGA1071

VCCCORE[1]

AB24

VCCCORE[2]

AB26

VCCCORE[3]

AB28

VCCCORE[4]

AD26

VCCCORE[5]

AD28

VCCCORE[6]

AF26

VCCCORE[7]

AF28

VCCCORE[8]

AF30

VCCCORE[9]

AF31

VCCCORE[10]

AH26

VCCCORE[11]

AH28

VCCCORE[12]

AH30

VCCCORE[13]

AH31

VCCCORE[14]

AJ30

VCCCORE[15]

AJ31

VCCPNAND[4] AK19

VCCPNAND[3] AK20

VCCIO[27]

AN23

VCCIO[28]

AN24

VCCIO[29]

AN26

VCCIO[30]

AN28

VCCIO[54]

AN30

VCCIO[55]

AN31

VCCIO[33]

AT26

VCCIO[34]

AT28

VCCIO[35]

AU26

VCCIO[36]

AU28

VCCIO[37]

AV26

VCCIO[38]

AV28

VCCIO[39]

AW26

VCCIO[40]

AW28

VCCIO[41]

BA26

VCCIO[42]

BA28

VCCIO[43]

BB26

VCCIO[44]

BB28

VCCIO[45]

BC26

VCCIO[46]

BC28

VCCIO[47]

BD26

VCCIO[48]

BD28

VCCIO[49]

BE26

VCCIO[50]

BE28

VCCIO[51]

BG26

VCCIO[52]

BG28

VCCIO[53]

BH27

VCCIO[31]

BJ26

VCCIO[32]

BJ28

VCCADAC[1] AE50

VCCADAC[2] AE52

VCCTX_LVDS[1] AP43

VCCTX_LVDS[2] AP45

VCCALVDS AH38

VCCVRM[2] AT24

VCCVRM[1]

AT22

VCCAPLLEXP

BJ24

VCCFDIPLL

BJ18

VCCPNAND[6] AK13

VCCPNAND[5] AK15

VCCPNAND[7] AM12

VCCPNAND[8] AM13

VCCIO[24]

AK24 VCCTX_LVDS[4] AT45

VCCTX_LVDS[3] AT46

VSSA_DAC[1] AF53

VSSA_LVDS AH39

VSSA_DAC[2] AF51

VCCIO[1]

AM23

VCC3_3[2] AB34

VCC3_3[3] AB35

VCC3_3[4] AD35

VCC3_3[1]

AN35

VCCME3_3[1] AM8

VCCME3_3[2] AM9

VCCME3_3[3] AP11

VCCME3_3[4] AP9

VCCPNAND[2] AK16

VCCPNAND[9] AM15

VCCPNAND[1] AM16

VCCDMI[1] AT16

VCCDMI[2] AU16

VCCIO[25]

AN20

VCCIO[26]

AN22

C 5 15

10U_0603_6.3V6M

1

2

C 4 62

1U_0402_6.3V6K

1

2

R 43 8

10_0402_1%

1 2

+

C 5 06

220U_B2_2.5VM_R35

UM A@

1

2

C 43 5

1U_0402_6.3V6K

1

2

C 4 67

0.1U_0402_16V4Z

1

2

C 5 02

10U_0603_6.3V6M

1

2

POWER

SATA

USB

Clock and Miscellaneous

HDA

CPU

PCI/GPIO/LPC

RTC PCI/GPIO/LPC

U 7J

IB EXPEAK-M_FCBGA1071

DCPSUSBYP

Y20

VCCME[1]

AD38

VCCME[2]

AD39

VCCME[3]

AD41

VCCME[5]

AF41

VCCME[6]

AF42

VCCSUSHDA L30

VCCSUS3_3[28] U23

VCCIO[56] V23

VCCIO[13] AD19

VCCIO[14] AF20

VCCIO[15] AF19

VCCME[7]

V39

VCCME[8]

V41

VCCME[9]

V42

VCCME[10]

Y39

VCCME[11]

Y41

VCCME[12]

Y42

V5REF K49

VCC3_3[8] J38

VCC3_3[9] L38

VCC3_3[10] M36

VCC3_3[11] N36

VCC3_3[12] P36

VCC3_3[13] U35

VCCRTC

A12

VCCSUS3_3[27] A26

VCCSUS3_3[26] A28

VCCSUS3_3[25] B27

VCCSUS3_3[24] C26

VCCSUS3_3[23] C28

VCCSUS3_3[22] E26

VCCSUS3_3[21] E28

VCCSUS3_3[20] F26

VCCSUS3_3[19] F28

VCCSUS3_3[18] G26

VCCSUS3_3[17] G28

VCCSUS3_3[16] H26

VCCSUS3_3[15] H28

VCCSUS3_3[14] J26

VCCSUS3_3[13] J28

VCCSUS3_3[12] L26

VCCSUS3_3[11] L28

VCCSUS3_3[10] M26

VCCSUS3_3[9] M28

VCCSUS3_3[8] N26

VCCSUS3_3[7] N28

VCCSUS3_3[6] P26

VCCSUS3_3[5] P28

VCCSUS3_3[4] U24

VCCSUS3_3[3] U26

VCCSUS3_3[2] U28

VCCSUS3_3[1] V28

VCCIO[11] AD20

VCCIO[20] AD22

VCCIO[10] AH19

VCCADPLLA[2]

BB53

VCCADPLLB[1]

BD51

VCCIO[22]

AJ35

V5REF_SUS F24

VCCIO[16] AH20

VCCIO[17] AB19

VCCIO[18] AB20

VCCIO[19] AB22

VCCIO[12] AF22

VCC3_3[14] AD13

VCCIO[9] AH22

VCCVRM[4] AT20

DCPSUS

Y22

VCCIO[2]

AF34

VCCIO[3]

AH34

VCCLAN[1]

AF23

VCCLAN[2]

AF24

VCCADPLLA[1]

BB51

VCCADPLLB[2]

BD53

VCCVRM[3]

AU24

VCCACLK[1]

AP51

VCCACLK[2]

AP53

DCPRTC

V9

VCCIO[4]

AF32

VCCME[4]

AF43

VCCIO[23]

AH35

VCCIO[21]

AH23

DCPSST

V12 VCCSATAPLL[2] AK1

VCCSATAPLL[1] AK3

VCCME[13] AA34

VCCME[14] Y34

VCCME[15] Y35

VCCME[16] AA35

VCC3_3[5]

V15

VCC3_3[6]

V16

VCC3_3[7]

Y16

VCCSUS3_3[29]

P18

VCCSUS3_3[30]

U19

VCCSUS3_3[31]

U20

VCCSUS3_3[32]

U22

VCCIO[5] V24

VCCIO[6] V26

VCCIO[7] Y24

VCCIO[8] Y26

V_CPU_IO[1]

AT18

V_CPU_IO[2]

AU18

C 44 7

1U_0402_6.3V6K

1

2

C 5 16

10U_0603_6.3V6M

1

2

R 5 27

0_0603_5%

@

1 2

R 2 14

0_0402_5%

D I S@

12

C 4 42

0.1U_0402_16V4Z

1

2

C456 0.1U_0402_16V4Z

1 2

C 51 4

10U_0603_6.3V6M

1

2

C 4 70

1U_0402_6.3V6K

1

2

C 4 40

0.1U_0402_16V4Z

1

2

T8P AD

R508 0_0402_5%

1 2

R 48 6

0_0402_5%

12

C461 0.1U_0402_16V4Z

1 2

R 5 28

0_0402_5%

D I S@

12

C 4 69

1U_0402_6.3V4Z

@

1

2

C 4 48

1U_0402_6.3V6K

1

2

C 46 6

1U_0402_6.3V6K

1

2

C 5 03

10U_0603_6.3V6M

1

2

C 5 01

0.1U_0402_16V4Z

1

2

L25

10UH_LB 2012T100MR_20%

1 2

C 5 04

10U_0603_6.3V6M

1

2

C457 0.1U_0402_16V4Z

1 2

C 50 5

10U_0805_6.3V6M

UM A@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number R e v

D at e : S hee t o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0 .3

IBEX-M(6/6)-GND

C us t o m

18 51Thur sday, October 29, 2009

2008/10/31 2009/10/31

Compal Electronics, Inc.

LA-5752P

U7H

IB EXPEAK-M_FCBGA1071

VSS[1]

AA19

VSS[2]

AA20

VSS[3]

AA22

VSS[5]

AA24

VSS[6]

AA26

VSS[7]

AA28

VSS[8]

AA30

VSS[9]

AA31

VSS[10]

AA32

VSS[11]

AB11

VSS[12]

AB15

VSS[13]

AB23

VSS[14]

AB30

VSS[15]

AB31

VSS[16]

AB32

VSS[17]

AB39

VSS[18]

AB43

VSS[19]

AB47

VSS[20]

AB5

VSS[21]

AB8

VSS[22]

AC2

VSS[23]

AC52

VSS[24]

AD11

VSS[25]

AD12

VSS[26]

AD16

VSS[27]

AD23

VSS[28]

AD30

VSS[29]

AD31

VSS[30]

AD32

VSS[31]

AD34

VSS[33]

AD42

VSS[34]

AD46

VSS[35]

AD49

VSS[36]

AD7

VSS[37]

AE2

VSS[38]

AE4

VSS[39]

AF12

VSS[43]

AF35

VSS[44]

AP13

VSS[46]

AF45

VSS[47]

AF46

VSS[48]

AF49

VSS[49]

AF5

VSS[50]

AF8

VSS[51]

AG2

VSS[52]

AG52

VSS[53]

AH11

VSS[54]

AH15

VSS[55]

AH16

VSS[56]

AH24

VSS[57]

AH32

VSS[59]

AH43

VSS[60]

AH47

VSS[61]

AH7

VSS[62]

AJ19

VSS[63]

AJ2

VSS[64]

AJ20

VSS[65]

AJ22

VSS[66]

AJ23

VSS[67]

AJ26

VSS[68]

AJ28

VSS[69]

AJ32

VSS[70]

AJ34

VSS[71]

AT5

VSS[72]

AJ4

VSS[73]

AK12

VSS[76]

AK26

VSS[77]

AK22

VSS[78]

AK23

VSS[79]

AK28

VSS[80] AK30

VSS[81] AK31

VSS[82] AK32

VSS[83] AK34

VSS[84] AK35

VSS[85] AK38

VSS[86] AK43

VSS[87] AK46

VSS[88] AK49

VSS[89] AK5

VSS[90] AK8

VSS[91] AL2

VSS[92] AL52

VSS[93] AM11

VSS[96] AM20

VSS[97] AM22

VSS[98] AM24

VSS[99] AM26

VSS[100] AM28

VSS[102] AM30

VSS[103] AM31

VSS[104] AM32

VSS[105] AM34

VSS[106] AM35

VSS[107] AM38

VSS[108] AM39

VSS[109] AM42

VSS[110] AU20

VSS[111] AM46

VSS[112] AV22

VSS[113] AM49

VSS[114] AM7

VSS[116] BB10

VSS[117] AN32

VSS[118] AN50

VSS[119] AN52

VSS[120] AP12

VSS[121] AP42

VSS[122] AP46

VSS[123] AP49

VSS[124] AP5

VSS[125] AP8

VSS[126] AR2

VSS[127] AR52

VSS[128] AT11

VSS[131] AT32

VSS[132] AT36

VSS[133] AT41

VSS[134] AT47

VSS[135] AT7

VSS[136] AV12

VSS[137] AV16

VSS[138] AV20

VSS[139] AV24

VSS[140] AV30

VSS[141] AV34

VSS[142] AV38

VSS[143] AV42

VSS[144] AV46

VSS[145] AV49

VSS[146] AV5

VSS[147] AV8

VSS[148] AW14

VSS[149] AW18

VSS[150] AW2

VSS[151] BF9

VSS[152] AW32

VSS[153] AW36

VSS[154] AW40

VSS[155] AW52

VSS[156] AY11

VSS[157] AY43

VSS[158] AY47

VSS[40]

Y13

VSS[42]

AU4

VSS[45]

AN34

VSS[115] AA50

VSS[0]

AB16

VSS[58]

AV18

VSS[32]

AU22

VSS[4]

AM19

VSS[74]

AM41

VSS[75]

AN19

VSS[41]

AH49

VSS[129] BA12

VSS[130] AH48

VSS[101] BA42

VSS[95] AD24

VSS[94] BB44

U7I

IB EXPEAK-M_FCBGA1071

VSS[159]

AY7

VSS[160]

B11

VSS[161]

B15

VSS[162]

B19

VSS[163]

B23

VSS[164]

B31

VSS[165]

B35

VSS[166]

B39

VSS[167]

B43

VSS[168]

B47

VSS[169]

B7

VSS[170]

BG12

VSS[171]

BB12

VSS[172]

BB16

VSS[173]

BB20

VSS[174]

BB24

VSS[175]

BB30

VSS[176]

BB34

VSS[177]

BB38

VSS[178]

BB42

VSS[179]

BB49

VSS[180]

BB5

VSS[181]

BC10

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC32

VSS[187]

BC36

VSS[188]

BC40

VSS[189]

BC44

VSS[190]

BC52

VSS[191]

BH9

VSS[192]

BD48

VSS[193]

BD49

VSS[194]

BD5

VSS[195]

BE12

VSS[196]

BE16

VSS[197]

BE20

VSS[198]

BE24

VSS[199]

BE30

VSS[200]

BE34

VSS[201]

BE38

VSS[202]

BE42

VSS[203]

BE46

VSS[204]

BE48

VSS[205]

BE50

VSS[206]

BE6

VSS[207]

BE8

VSS[208]

BF3

VSS[209]

BF49

VSS[210]

BF51

VSS[211]

BG18

VSS[212]

BG24

VSS[213]

BG4

VSS[214]

BG50

VSS[215]

BH11

VSS[216]

BH15

VSS[217]

BH19

VSS[218]

BH23

VSS[219]

BH31

VSS[220]

BH35

VSS[221]

BH39

VSS[222]

BH43

VSS[223]

BH47

VSS[224]

BH7

VSS[225]

C12

VSS[226]

C50

VSS[227]

D51

VSS[228]

E12

VSS[229]

E16

VSS[230]

E20

VSS[231]

E24

VSS[232]

E30

VSS[233]

E34

VSS[234]

E38

VSS[235]

E42

VSS[236]

E46

VSS[237]

E48

VSS[264] K47

VSS[265] K7

VSS[266] L14

VSS[267] L18

VSS[268] L2

VSS[269] L22

VSS[270] L32

VSS[271] L36

VSS[272] L40

VSS[273] L52

VSS[274] M12

VSS[275] M16

VSS[276] M20

VSS[277] N38

VSS[278] M34

VSS[279] M38

VSS[280] M42

VSS[281] M46

VSS[282] M49

VSS[283] M5

VSS[284] M8

VSS[285] N24

VSS[286] P11

VSS[288] P22

VSS[289] P30

VSS[290] P32

VSS[291] P34

VSS[292] P42

VSS[293] P45

VSS[294] P47

VSS[295] R2

VSS[296] R52

VSS[297] T12

VSS[298] T41

VSS[299] T46

VSS[300] T49

VSS[301] T5

VSS[302] T8

VSS[303] U30

VSS[304] U31

VSS[305] U32

VSS[306] U34

VSS[307] P38

VSS[308] V11

VSS[309] P16

VSS[310] V19

VSS[311] V20

VSS[312] V22

VSS[313] V30

VSS[314] V31

VSS[315] V32

VSS[316] V34

VSS[238]

E6

VSS[239]

E8

VSS[240]

F49

VSS[241]

F5

VSS[242]

G10

VSS[243]

G14

VSS[244]

G18

VSS[245]

G2

VSS[246]

G22

VSS[247]

G32

VSS[248]

G36

VSS[249]

G40

VSS[250]

G44

VSS[251]

G52

VSS[317] V35

VSS[318] V38

VSS[319] V43

VSS[320] V45

VSS[321] V46

VSS[322] V47

VSS[323] V49

VSS[324] V5

VSS[325] V7

VSS[326] V8

VSS[327] W2

VSS[328] W52

VSS[329] Y11

VSS[330] Y12

VSS[331] Y15

VSS[332] Y19

VSS[333] Y23

VSS[334] Y28

VSS[335] Y30

VSS[336] Y31

VSS[337] Y32

VSS[338] Y38

VSS[339] Y43

VSS[340] Y46

VSS[342] Y5

VSS[343] Y6

VSS[344] Y8

VSS[341] P49

VSS[345] P24

VSS[287] AD15

VSS[252]

AF39

VSS[253]

H16

VSS[254]

H20

VSS[255]

H30

VSS[256]

H34

VSS[257]

H38

VSS[258]

H42

VSS[346] T43

VSS[347] AD51

VSS[348] AT8

VSS[349] AD47

VSS[350] Y47

VSS[351] AT12

VSS[352] AM6

VSS[353] AT13

VSS[354] AM5

VSS[355] AK45

VSS[356] AK39

VSS[366] AV14

VSS[262] K11

VSS[263] K43

VSS[259] H49

VSS[260] H5

VSS[261] J24

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

VGA_DDCDATA_C

VGA_DDCCLK_C

VGA_LVDS_SCL_C

VGA_LVDS_SDA_C

XTALIN

PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N0

PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P4

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_N5

PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_N7

PCIE_CTX_GRX_N8

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P9

PCIE_CTX_GRX_N9

PCIE_CTX_GRX_N10

PCIE_CTX_GRX_P10

PCIE_CTX_GRX_N11

PCIE_CTX_GRX_P11

PCIE_CTX_GRX_N12

PCIE_CTX_GRX_P13

PCIE_CTX_GRX_N13

PCIE_CTX_GRX_P12

PCIE_CTX_GRX_P14

PCIE_CTX_GRX_N14

PCIE_CTX_GRX_P15

PCIE_CTX_GRX_N15

PCIE_CRX_GTX_N12

PCIE_CRX_GTX_P12

PCIE_CRX_C_GTX_N12

PCIE_CRX_GTX_P13

PCIE_CRX_GTX_N13

PCIE_CRX_GTX_P9

PCIE_CRX_GTX_N9

PCIE_CRX_GTX_N15

PCIE_CRX_GTX_P15

PCIE_CRX_GTX_N14

PCIE_CRX_GTX_P14

PCIE_CRX_GTX_P0

PCIE_CRX_GTX_N0

PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P6

PCIE_CRX_GTX_N2

PCIE_CRX_C_GTX_P14

PCIE_CRX_C_GTX_P15

PCIE_CRX_C_GTX_N14

PCIE_CRX_C_GTX_N15

PCIE_CRX_C_GTX_P0

PCIE_CRX_C_GTX_N0

PCIE_CRX_C_GTX_N1

PCIE_CRX_C_GTX_P1

PCIE_CRX_C_GTX_P2

PCIE_CRX_C_GTX_P3

PCIE_CRX_C_GTX_N3

PCIE_CRX_GTX_P4

PCIE_CRX_C_GTX_N2

PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4

PCIE_CRX_C_GTX_P5

PCIE_CRX_C_GTX_P4

PCIE_CRX_C_GTX_N5

PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P11

PCIE_CRX_GTX_N11

PCIE_CRX_GTX_P8

PCIE_CRX_GTX_N8

PCIE_CRX_GTX_P5

PCIE_CRX_GTX_N5

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

CLK_PCIE_VGA#

CLK_PCIE_VGA

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_N2

PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P3

PCIE_CRX_GTX_P2

PCIE_CRX_C_GTX_N6

PCIE_CRX_GTX_P3

PCIE_CRX_C_GTX_P6

PCIE_CRX_GTX_N3

PCIE_CRX_C_GTX_N7

PCIE_CRX_C_GTX_P7

PCIE_CRX_C_GTX_P8

PCIE_CRX_C_GTX_N8

PCIE_CRX_GTX_N10

PCIE_CRX_GTX_P10

PCIE_CRX_C_GTX_P9

PCIE_CRX_C_GTX_N9

PCIE_CRX_C_GTX_N10

PCIE_CRX_C_GTX_P10

PCIE_CRX_C_GTX_P11

PCIE_CRX_C_GTX_N11

PCIE_CRX_C_GTX_P12

PCIE_CRX_GTX_P7

PCIE_CRX_GTX_N7

PCIE_CRX_C_GTX_P13

PCIE_CRX_C_GTX_N13

XTALOUT

VGA_GPIO14

VGA_CRT_B

VGA_GPIO14

VGA_GPIO11

JTAG_TMS

VGA_CRT_R

DACA_VREF

VGA_CRT_G

VGA_LVDS_SCL_C

VGA_LVDS_SDA_C

DACA_RSET

JTAG_TCK

VGA_ENBKL_R

VGA_ENVDD_R

VGA_GPIO11

JTAG_TRST_N

JTAG_TDO

JTAG_TDI

GPU_VID0

GPU_VID1

SMB_EC_DA2_R

VGA_DDCDATA_C

VGA_LVDS_SCL_C

SMB_EC_CK2_R

VGA_DDCCLK_C

VGA_LVDS_SDA_C

HDCP_SMB_CK1

HDCP_SMB_DAI

I2CB_SDA

I2CB_SCL

VGA_DDCDATA_C

VGA_DDCCLK_C

NV_INVTPWM

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PEG_CLKREQ#

TESTMODE

VGA_LVDS_SCL <27>

VGA_LVDS_SDA <27>

VGA_DDCDATA <26>

VGA_DDCCLK <26>

PCIE_CTX_GRX_P[0..15]<6>

PCIE_CRX_GTX_N[0..15]<6>

PCIE_CRX_GTX_P[0..15]<6>

CLK_PCIE_VGA<14>

CLK_PCIE_VGA#<14>

GPU_VID1 <45>

HDMI_DETECT_VGA <24>

GPU_VID0 <45>

VGA_ENBKL_R <27>

VGA_ENVDD_R <27>

VGA_CRT_G <26>

VGA_CRT_B <26>

VGA_VSYNC <26>

VGA_CRT_R <26>

VGA_HSYNC <26>

SMB_EC_CK2_R <14,31>

SMB_EC_DA2_R <14,31>

PCIE_CTX_GRX_N[0..15]<6>

PEG_CLKREQ#<14>

BUF_PLT_RST#<5,16,28,29>

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

N10M-GE1 PCIE,GPIO,CLK

B

19 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

N10M-GS

(40nm)

Device ID

0x0A74

CRT OUT

I2CS is VDD33 power plane

same as EC +3.3VS.

DIS@

I2CS is internal thermal sensor.

1

Deep P12

1

0.85V

P-State

1.0V

VGA_COREGPU_VID0

0

GPU_VID1

0.8V

P0

1

P8

00

GPIO6GPIO5

1

Deep P12

1

0.85V

P-State

0.9V

VGA_COREGPU_VID0

0

GPU_VID1

0.8V

P0

1

P8

00

0x0A7D

N11M-GE1/LP1

(40nm)

Device ID

Removed external HDCP.

07/17/2009

Pull Hi at CRT CONN side.

C96 0.1U_0402_16V7KDIS@ 1 2

C104 0.1U_0402_16V7KDIS@ 1 2

R505

10K_0402_5%

@

12

R538 150_0402_1%DIS@

1 2

C77 0.1U_0402_16V7KDIS@ 1 2

T13

PAD

R537 150_0402_1%DIS@

1 2

L8

MBK1608121YZF_0603DIS@

1 2

C93 0.1U_0402_16V7KDIS@ 1 2

T4

PAD

R517 2.2K_0402_5%DIS@

1 2

C101 0.1U_0402_16V7KDIS@ 1 2

C100 0.1U_0402_16V7KDIS@ 1 2

R512 0_0402_5%DIS@

1 2

C450

12P_0402_50V8J

DIS@

1

2

C94 0.1U_0402_16V7KDIS@ 1 2

R444 4.7K_0402_5%@12

R511 0_0402_5%DIS@

1 2

R516 2.2K_0402_5%

DIS@

1 2

C112 0.1U_0402_16V7KDIS@ 1 2

R24 10K_0402_5%DIS@

1 2

C114 0.1U_0402_16V7KDIS@ 1 2

R540 200_0402_5% @

1 2

R513

10K_0402_5%

@

12

C120 0.1U_0402_16V7KDIS@ 1 2

C107 0.1U_0402_16V7KDIS@ 1 2

C79 0.1U_0402_16V7KDIS@ 1 2

T12

PAD

C106 0.1U_0402_16V7KDIS@ 1 2

C97 0.1U_0402_16V7KDIS@ 1 2

T11

PAD

R530 150_0402_1%DIS@

1 2

R499

2.2K_0402_5%

DIS@

R542

10K_0402_5%

DIS@

1 2

C98 0.1U_0402_16V7KDIS@ 1 2

T9

PAD

R478

2.2K_0402_5%

DIS@

R2510K_0402_5% @

1 2

C451

12P_0402_50V8J

DIS@

1

2

C81 0.1U_0402_16V4Z

DIS@ 12

R543 0_0402_5%@

1 2

R539 10K_0402_5%DIS@

1 2

C113 0.1U_0402_16V7KDIS@ 1 2 T14

PAD

C115 0.1U_0402_16V7KDIS@ 1 2

R34

10K_0402_5%

DIS@

12

C119 0.1U_0402_16V7KDIS@ 1 2

C102 0.1U_0402_16V7KDIS@ 1 2

C109 0.1U_0402_16V7KDIS@ 1 2

R64 2.2K_0402_5%DIS@ 12

C99 0.1U_0402_16V7KDIS@ 1 2

C110 0.1U_0402_16V7KDIS@ 1 2

C118 0.1U_0402_16V7KDIS@ 1 2

R42

10K_0402_5%

DIS@

12

C108 0.1U_0402_16V7KDIS@ 1 2

R48 124_0402_1%DIS@

C116 0.1U_0402_16V7KDIS@ 1 2

R443 4.7K_0402_5%@12

L7 MBK1608121YZF_0603DIS@

1 2

R63 2.2K_0402_5%DIS@ 12

R46

10K_0402_5%

@

12

C103 0.1U_0402_16V7KDIS@ 1 2

C69

20P_0402_50V8

DIS@

1

2

C105 0.1U_0402_16V7KDIS@ 1 2

GPIO

PCI EXPRESS

TEST

CLK

Part 1 of 5

I2C DACADACB

U22A

N11M-GE1-S-A2 _BGA533

DIS@

PEX_RX0

AE12

PEX_RX0_N

AF12

PEX_RX1

AG12

PEX_RX1_N

AG13

PEX_RX2

AF13

PEX_RX2_N

AE13

PEX_RX3

AE15

PEX_RX3_N

AF15

PEX_RX4

AG15

PEX_RX4_N

AG16

PEX_RX5

AF16

PEX_RX5_N

AE16

PEX_RX6

AE18

PEX_RX6_N

AF18

GPIO0 N1

GPIO1 G1

GPIO2 C1

GPIO3 M2

GPIO4 M3

GPIO5 K3

GPIO6 K2

GPIO7 J2

GPIO8 C2

GPIO9 M1

GPIO10 D2

GPIO11 D1

GPIO13 J1

DACA_HSYNC AD2

DACA_VSYNC AD1

DACA_RED AE2

DACA_BLUE AD3

DACA_GREEN AE3

DACA_RSET AE1

DACA_VREF AF1

PEX_TSTCLK_OUT

AF10

PEX_TSTCLK_OUT_N

AE10

GPIO14 K1

GPIO15 F3

GPIO16 G3

GPIO17 G2

GPIO18 F1

GPIO19 F2

GPIO12 J3

PEX_REFCLK

AB10

PEX_REFCLK_N

AC10

PEX_RST_N

AD9

PEX_RX7

AG18

PEX_RX7_N

AG19

PEX_RX8

AF19

PEX_RX8_N

AE19

PEX_RX9

AE21

PEX_RX9_N

AF21

PEX_RX10

AG21

PEX_RX10_N

AG22

PEX_RX11

AF22

PEX_RX11_N

AE22

PEX_RX12

AE24

PEX_RX12_N

AF24

PEX_RX13

AG24

PEX_RX13_N

AF25

PEX_RX14

AG25

PEX_RX14_N

AG26

PEX_RX15

AF27

PEX_RX15_N

AE27

PEX_TERMP

AG10

PEX_TX0

AD10

PEX_TX0_N

AD11

PEX_TX1

AD12

PEX_TX1_N

AC12

PEX_TX2

AB11

PEX_TX2_N

AB12

PEX_TX3

AD13

PEX_TX3_N

AD14

PEX_TX4

AD15

PEX_TX4_N

AC15

PEX_TX5

AB14

PEX_TX5_N

AB15

PEX_TX6

AC16

PEX_TX6_N

AD16

PEX_TX7

AD17

PEX_TX7_N

AD18

PEX_TX8

AC18

PEX_TX8_N

AB18

PEX_TX9

AB19

PEX_TX9_N

AB20

PEX_TX10

AD19

PEX_TX10_N

AD20

PEX_TX11

AD21

PEX_TX11_N

AC21

PEX_TX12

AB21

PEX_TX12_N

AB22

PEX_TX13

AC22

PEX_TX13_N

AD22

PEX_TX14

AD23

PEX_TX14_N

AD24

PEX_TX15

AE25

PEX_TX15_N

AE26

PEX_CLKREQ_N

AE9

DACB_HSYNC U6

DACB_VSYNC U4

DACB_RED T5

DACB_BLUE R4

DACB_GREEN T4

DACB_VREF R6

DACB_RSET V6

JTAG_TCK AF3

JTAG_TDI AG4

JTAG_TDO AE4

JTAG_TMS AF4

JTAG_TRST_N AG3

TESTMODE AD25

XTAL_SSIN D11

XTAL_OUTBUFF E9

XTAL_OUT E10

XTAL_IN D10

I2CS_SCL T1

I2CS_SDA T2

I2CH_SCL A3

I2CH_SDA A4

I2CC_SCL A2

I2CC_SDA B1

I2CB_SCL R2

I2CB_SDA R3

I2CA_SCL R1

I2CA_SDA T3

C85

12P_0402_50V8J

DIS@

1

2

C80 0.1U_0402_16V7KDIS@ 1 2

Y2

27MHZ_16PF_X7S027000BG1H-U

DIS@

OUT 3

GND 2

GND

4

IN

1

R541 2.49K_0402_1% DIS@

1 2

C56

20P_0402_50V8

DIS@

1

2

C95 0.1U_0402_16V7KDIS@ 1 2

C117 0.1U_0402_16V7KDIS@ 1 2

C86

12P_0402_50V8J

DIS@

1

2

L17 MBK1608121YZF_0603DIS@

1 2

L18 MBK1608121YZF_0603DIS@

1 2

C78 0.1U_0402_16V7KDIS@ 1 2

C111 0.1U_0402_16V7KDIS@ 1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FB_VREF1

IFPC_AUX

FBA_D[0..63]

VGA_LVDS_A1

VGA_LVDS_A1#

VGA_LVDS_A0

VGA_LVDS_A2#

VGA_LVDS_A2

VGA_LVDS_A0#

VGA_LVDS_ACLK#

VGA_LVDS_ACLK

ROM_SI

ROM_SO

ROM_SCLK

STRAP2

STRAP1

STRAP0

IFPC_AUX

IFPC_AUX_N

SPDIF_IN

FBA_D62

FBA_D63

FBA_D0

FBA_D1

FBA_D2

FBA_D3

FBA_D4

FBA_D5

FBA_D6

FBA_D7

FBA_D8

FBA_D9

FBA_D10

FBA_D11

FBA_D12

FBA_D13

FBA_D14

FBA_D15

FBA_D16

FBA_D17

FBA_D18

FBA_D19

FBA_D20

FBA_D21

FBA_D22

FBA_D23

FBA_D24

FBA_D25

FBA_D26

FBA_D27

FBA_D28

FBA_D29

FBA_D30

FBA_D31

FBA_D32

FBA_D33

FBA_D34

FBA_D35

FBA_D36

FBA_D37

FBA_D38

FBA_D39

FBA_D40

FBA_D41

FBA_D42

FBA_D43

FBA_D44

FBA_D45

FBA_D46

FBA_D47

FBA_D48

FBA_D49

FBA_D50

FBA_D51

FBA_D52

FBA_D53

FBA_D54

FBA_D55

FBA_D56

FBA_D57

FBA_D58

FBA_D59

FBA_D60

FBA_D61

FBA_BA2

FBBA3

FBBA5

FBAA2

FBAA3

FBAA0

FBAWE#

FBBA2

FBAA1

FBAA11

FBAA10

FBAA8

FBAA9

FBAA6

FBAA5

FBBACS0#

FBAA7

FBAA_CKE

FBACAS#

FBA_BA1

FBA_BA0

FBA_RST

FBAA12

FBBA4

FBARAS#

FBBA_CKE

FBAA[0..13]

FBBA[2..5]

FBADQS#2

FBADQS#1

FBADQS#3

FBADQS#4

FBADQS#6

FBADQS#5

FBADQS#7

FBADQS#0

FBADQS2

FBADQS1

FBADQS3

FBADQS4

FBADQS6

FBADQS5

FBADQS7

FBADQS0

FBADQM5

FBADQM4

FBADQM0

FBADQM2

FBADQM1

FBADQM3

FBADQM7

FBADQM6

FBADQM[0..7]

FBADQS#[0..7]

FBADQS[0..7]

FBAA4

FBAACS0#

IFPC_AUX_N

FBAA13

FBBAODT0

FBAAODT0

VGA_LVDS_ACLK#

VGA_LVDS_ACLK

FBACLK0 <23>

FBACLK0# <23>

FBACLK1 <23>

FBACLK1# <23>

VGA_HDMI_SCL <24>

VGA_HDMI_SDA <24>

FBAD[0..63]<23>

VGA_LVDS_ACLK#<27>

VGA_LVDS_ACLK<27>

VGA_LVDS_A0<27>

VGA_LVDS_A1<27>

VGA_LVDS_A2<27>

VGA_LVDS_A0#<27>

VGA_LVDS_A1#<27>

VGA_LVDS_A2#<27>

ROM_SO <22>

ROM_SCLK <22>

ROM_SI <22>

STRAP1 <22>

STRAP2 <22>

STRAP0 <22>

FBBA_CKE <23>

FBAWE# <23>

FBA_BA2 <23>

FBA_BA0 <23>

FBACAS# <23>

FBBACS0# <23>

FBAA_CKE <23>

FBA_RST <23>

FBAA12 <23>

FBA_BA1 <23>

FBARAS# <23>

FBADQS#[0..7]<23>

FBADQS[0..7]<23>

FBADQM[0..7]<23>

FBAACS0# <23>

FBAAODT0 <23>

FBBAODT0 <23>

VGA_HDMI_TX2+<24>

VGA_HDMI_TX0+<24>

VGA_HDMI_TX2-<24>

VGA_HDMI_TX1-<24>

VGA_HDMI_TX1+<24>

VGA_HDMI_CLK-<24>

VGA_HDMI_CLK+<24>

VGA_HDMI_TX0-<24>

+1.5VS

+3VS

+3VS

+3VS

+3VS

+1.5VS

FBAA[0..13]<23>

FBBA[2..5]<23>

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

N10M-GE1 LVDS,Memory Bus

B

20 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

10mil

1.27V~0.9V

5V PULL UP IN CONNECTER SIDE

HDMI

LVDS

C43

0.01U_0402_16V7K

@

1

2

R39 1K_0402_1%DIS@

1 2

Q38A

2N7002DW-T/R7_SOT363-6

DIS@

61

2

R445

10K_0402_5%

DIS@

12

R23

10K_0402_5%

DIS@

12

Q38B

2N7002DW-T/R7_SOT363-6

DIS@

3

5

4

R22

10K_0402_5%

DIS@

12

T2

PAD

T3

PAD

R531

4.7K_0402_5%

DIS@

1 2

R40 1K_0402_1%@

1 2

R30

1.3K_0402_1%

@

12

R32 36K_0402_5%

DIS@

1 2

R18

10K_0402_5%

DIS@

12

R15

10K_0402_5%

DIS@

12

R29

1.3K_0402_1%

@

12

T1

PAD

R477 1K_0402_1%@

1 2

R44 1K_0402_1%@

1 2

C649

12P_0402_50V8J

@1

2

R468

10K_0402_5%

DIS@

12

C650

12P_0402_50V8J

@

1

2

MEMORY INTERFACE

Part 2 of 5

U22B

N11M-GE1-S-A2 _BGA533

DIS@

FBA_D36

T23

FBA_CMD0 F26

FBA_CMD1 J24

FBA_CMD2 F25

FBA_CMD3 M23

FBA_CMD4 N27

FBA_CMD5 M27

FBA_CMD6 K26

FBA_CMD7 J25

FBA_CMD8 J27

FBA_CMD9 G23

FBA_CMD10 G26

FBA_CMD11 J23

FBA_CMD12 M25

FBA_CMD13 K27

FBA_CMD14 G25

FBA_CMD15 L24

FBA_CMD16 K23

FBA_CMD17 K24

FBA_CMD18 G22

FBA_CMD19 K25

FBA_CMD20 H22

FBA_CMD21 M26

FBA_CMD22 H24

FBA_CMD23 F27

FBA_CMD24 J26

FBA_CMD25 G24

FBA_CMD26 G27

FBA_CMD27 M24

FBA_CMD28 K22

FBA_DEBUG M22

FBA_CLK1 N24

FBA_CLK1_N N23

FBA_CLK0 F24

FBA_CLK0_N F23

FB_VREF A16

FBA_DQS_WP2 E19

FBA_DQS_WP4 T22

FBA_DQS_RN2 E18

FBA_DQS_RN4 R22

FBA_DQM2 D19

FBA_DQM4 T24

FBA_CMD29 J22

FBA_CMD30 L22

FBA_DQM1 B19

FBA_DQM3 D23

FBA_DQM0 C26

FBA_DQM5 AA23

FBA_DQM6 AB27

FBA_DQM7 T26

FBA_DQS_RN1 A18

FBA_DQS_RN3 B24

FBA_DQS_RN0 D25

FBA_DQS_RN5 Y24

FBA_DQS_RN6 AA27

FBA_DQS_RN7 R27

FBA_DQS_WP1 A19

FBA_DQS_WP3 A24

FBA_DQS_WP0 C25

FBA_DQS_WP5 AA24

FBA_DQS_WP6 AA26

FBA_DQS_WP7 T27

FBA_D63

N26 FBA_D62

N25

FBA_D60

R26

FBA_D61

T25

FBA_D59

V27

FBA_D56

V25

FBA_D57

R25

FBA_D58

V26

FBA_D55

AD27

FBA_D44

AA22

FBA_D51

W25

FBA_D52

AB25

FBA_D53

AB26

FBA_D54

AD26

FBA_D49

W27

FBA_D50

W26

FBA_D48

AA25 FBA_D47

V22 FBA_D46

W22 FBA_D45

W23

FBA_D40

AC24

FBA_D41

AB23

FBA_D42

AB24

FBA_D43

W24

FBA_D39

P22 FBA_D38

P24 FBA_D37

R23

FBA_D32

U24

FBA_D33

V24

FBA_D34

V23

FBA_D35

R24

FBA_D31

A26 FBA_D30

B25 FBA_D29

A25 FBA_D28

C22

FBA_D0

D22

FBA_D1

E24

FBA_D2

E22

FBA_D3

D24

FBA_D4

D26

FBA_D5

D27

FBA_D6

C27

FBA_D7

B27

FBA_D8

A21

FBA_D9

B21

FBA_D10

C21

FBA_D11

C19

FBA_D12

C18

FBA_D13

D18

FBA_D14

B18

FBA_D15

C16

FBA_D16

E21

FBA_D17

F21

FBA_D18

D20

FBA_D19

F20

FBA_D20

D17

FBA_D21

F18

FBA_D22

D16

FBA_D23

E16

FBA_D24

A22

FBA_D25

C24

FBA_D26

D21

FBA_D27

B22

R16

10K_0402_5%

DIS@

12

R26

10K_0402_5%DIS@

1 2

Part 3 of 5

NCRFU

LVDS / TMDS

GENERAL STRAPSERIAL

U22C

N11M-GE1-S-A2 _BGA533

DIS@

IFPA_TXC

AC4

IFPA_TXC_N

AD4

IFPA_TXD0

V5

IFPA_TXD0_N

V4

IFPA_TXD1

AA5

IFPA_TXD1_N

AA4

IFPA_TXD2

W4

IFPA_TXD2_N

Y4

IFPA_TXD3

AB4

IFPA_TXD3_N

AB5

BUFRST_N N5

THERMDN D8

ROM_SCLK C9

ROM_SI A10

ROM_SO C10

ROM_CS_N B10

STRAP0 C7

IFPB_TXC

AB3

IFPB_TXC_N

AB2

IFPB_TXD4

W1

IFPB_TXD4_N

V1

IFPB_TXD5

W3

IFPB_TXD5_N

W2

IFPB_TXD6

AA2

IFPB_TXD6_N

AA3

IFPB_TXD7

AB1

IFPB_TXD7_N

AA1

IFPD_AUX_I2CX_SCL

D3

IFPD_AUX_I2CX_SDA_N

D4

IFPD_L0

F5

IFPD_L0_N

F4

IFPD_L1

E4

IFPD_L1_N

D5

IFPD_L2

C3

IFPD_L2_N

C4

IFPD_L3

B3

IFPD_L3_N

B4

IFPC_AUX_I2CW_SCL

G4

IFPC_AUX_I2CW_SDA_N

G5

IFPC_L0

P4

IFPC_L0_N

N4

IFPC_L1

M5

IFPC_L1_N

M4

IFPC_L2

L4

IFPC_L2_N

K4

IFPC_L3

H4

IFPC_L3_N

J4

IFPE_AUX_I2CY_SCL

F7

IFPE_AUX_I2CY_SDA_N

G6

IFPE_L0

D6

IFPE_L0_N

C6

IFPE_L1

A6

IFPE_L1_N

A7

IFPE_L2

B6

IFPE_L2_N

B7

IFPE_L3

E6

IFPE_L3_N

E7 IFPE_RSET F8

IFPD_RSET M6

IFPC_RSET R5

IFPAB_RSET AB6

STRAP2 A9

STRAP1 B9

SPDIF F9

CEC N2

NC C15

NC D15

NC J5

RFU_1 T6

RFU_2 W6

RFU_3 Y6

RFU_4 AA6

RFU_5 N3

THERMDP D9

R526

4.7K_0402_5%

DIS@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+PEX_PLLVDD

+DACA_VDD

+PEX_SVDD_3V3

+1.05VS_PLL

+FB_PLLAVDD

+DACB_VDD

+FB_PLLAVDD

+IFPC_PLLVDD

+IFPAB_PLLVDD

+SP_PLLVDD

+SP_PLLVDD

+IFPAB_PLLVDD

+DACA_VDD

+PEX_SVDD_3V3

+IFPB_IOVDD

+IFPC_IOVDD

+IFPC_PLLVDD

+IFPA_IOVDD

+VGASENSE +VGASENSE <45>

+VGA_CORE

+3VS

+3VS

+1.5VS

+3VS

+1.8VS

+3VS

+1.05VS

+1.05VS

+1.05VS

+1.05VS

+1.05VS

+1.5VS

+1.05VS

+1.05VS

+1.05VS

Title

Size D ocument Number R ev

D at e: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

N10M-GE1 PWR

C u st om

21 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA -5 752P

N10M-GS: 15.8A

N11M-GE1:16.7A

NEAR BALL

120mA

NEAR BALL

PLACE UNDER GPU

12~16mil

120mA

NEAR BGA

NEAR BGA

300mA

NEAR BGA NEAR BALL

NEAR BGA

NEAR BALL

285mA

220mA

NEAR BGA

NEAR BALL

120mA

CLOSE TO GPU

NEAR BALL

NEAR BALL NEAR BGA

NEAR BGA 2A

VID_PLLVDD=45mA

SP_PLLVDD=45mA

PLLVDD=60mA

FB_PLLVDD=100mA

FB_DLLVDD=100mA

220mA

NEAR BGA

NEAR BALL

NEAR BGA

120mA

NEAR BALL

NEAR BGA

NEAR BGA

NEAR BALL NEAR BGA

The power is base on VRAM type.

N10M-GS: 2.63A

N11M-GE1:2.55A

C496

0.1U_0402_10V7K

DIS@

1

2

R465 40.2_0402_1%D IS@

C459

1U_0402_6.3V6K

DIS@

1

2

C499

1U_0402_6.3V6K

DIS@

1

2

R4710K_0402_5%

@

12

C24

4.7U 6.3V K X5R 0603

DIS@

1

2

C458

0.1U_0402_10V7K

DIS@

1

2

L4

MBK1608121YZF_0603

DIS@

1 2

C537

4.7U 6.3V K X5R 0603

DIS@

1

2

C32

0.047U_0402_25V7K

DIS@

1

2

C47

0.1U_0402_10V7K

DIS@

1

2

C512

4.7U 6.3V K X5R 0603

DIS@

1

2

C511

0.1U_0402_10V7K

DIS@

1

2

C49

1U_0402_6.3V6K

DIS@

1

2

C61

0.1U_0402_10V7K

DIS@

1

2

L6

MBK1608121YZF_0603

DIS@

1 2

R4110K_0402_5%

DIS@

12

R4310K_0402_5%

DIS@

12

C26

4.7U 6.3V K X5R 0603

DIS@

1

2

C46

0.1U_0402_10V7K

DIS@

1

2

C65

1U_0402_6.3V6K

DIS@

1

2

C63

0.1U_0402_10V7K

DIS@

1

2

R49 0_0402_5%

DIS@

1 2

C84

4.7U 6.3V K X5R 0603

DIS@

1

2

C523

470P_0402_50V7K

DIS@

1

2

C538

10U_0805_6.3V6M

DIS@

1

2

C60

0.1U_0402_10V7K

DIS@

1

2

C482

4.7U 6.3V K X5R 0603

DIS@

1

2

C481

0.1U_0402_10V7K

DIS@

1

2

C519

1U_0402_6.3V6K

DIS@

1

2

C42

0.047U_0402_25V7K

DIS@

1

2

C36

0.047U_0402_25V7K

DIS@

1

2

R45 10K_0402_5%DIS@

1 2

C40

0.01U_0402_16V7K

DIS@

1

2

C488

4.7U 6.3V K X5R 0603

DIS@

1

2

C71

1U_0402_6.3V6K

DIS@

1

2

C54

0.1U_0402_10V7K

DIS@

1

2

C520

0.1U_0402_10V7K

DIS@

1

2

C62

0.1U_0402_10V7K

DIS@

1

2

C58

0.1U_0402_10V7K

DIS@

1

2

C524

4.7U 6.3V K X5R 0603

DIS@

1

2

C28

0.01U_0402_16V7K

DIS@

1

2

C41

0.047U_0402_25V7K

DIS@

1

2

C37

0.01U_0402_16V7K

DIS@

1

2

C82

4.7U 6.3V K X5R 0603

DIS@

1

2

C513

0.1U_0402_10V7K

DIS@

1

2

C31

0.047U_0402_25V7K

DIS@

1

2

C35

1U_0402_6.3V6K

DIS@

1

2

C30

1U_0402_6.3V6K

DIS@

1

2

C521

0.1U_0402_10V7K

DIS@

1

2

L24

MBK1608121YZF_0603

DIS@

1 2

C50

0.1U_0402_10V7K

DIS@

1

2

Part 4 of 5

POWER

U22D

N11M-GE1-S-A2 _BGA533

DIS@

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

T9

VDD

T11

VDD

T17

VDD

U9

VDD

P11 VDD

N19 VDD

N17 VDD

N16 VDD

N15 VDD

N14

VDD

R12

VDD

M11

VDD

N12

VDD

M9 VDD

L9 VDD

J13 VDD

J12 VDD

J10 VDD

J9

VDD

N13

VDD

P12

VDD

P13

VDD

P14

VDD

P15

VDD

P16

VDD

P17

VDD

R9

VDD

R11

VDD

N11

VDD

M17

VDD

N9

VDD

U19

VDD

W9

VDD

W13

VDD

W18

VDD

W19

FBVDDQ A13

FBVDDQ B13

FBVDDQ C13

FBVDDQ D13

FBVDDQ D14

FBVDDQ E13

FBVDDQ F13

FBVDDQ F14

FBVDDQ F15

FBVDDQ F16

VDD

W12 VDD

W10

FBVDDQ F17

FBVDDQ F19

FBVDDQ F22

FBVDDQ H23

FBVDDQ H26

FBVDDQ J15

FBVDDQ J16

FBVDDQ J18

FBVDDQ J19

FBVDDQ L19

FBVDDQ L23

FBVDDQ L26

FBVDDQ M19

FBVDDQ N22

FBVDDQ U22

FBVDDQ Y22

PEX_IOVDDQ AB7

PEX_IOVDDQ AB8

PEX_IOVDDQ AB9

PEX_IOVDDQ AB13

PEX_IOVDDQ AB16

PEX_IOVDDQ AB17

PEX_IOVDDQ AC7

PEX_IOVDDQ AC13

PEX_IOVDDQ AD6

PEX_IOVDDQ AE6

PEX_IOVDDQ AF6

PEX_IOVDDQ AG6

PEX_IOVDD AG7

PEX_IOVDD AF7

PEX_IOVDD AE7

PEX_IOVDD AD8

PEX_IOVDD AD7

PEX_IOVDD AC9

PEX_PLLVDD AF9

VID_PLLVDD K6

SP_PLLVDD L6

PLLVDD K5

FB_PLLAVDD R19

VDD_SENSE W15

FB_CAL_PD_VDDQ B15

DACB_VDD W5

DACA_VDD AG2

FB_PLLAVDD AC19

FB_DLLAVDD T19

VDD_SENSE E15

VDD33

A12

VDD33

B12

VDD33

C12

VDD33

D12

VDD33

E12

VDD33

F12

IFPE_PLLVDD

D7

IFPD_PLLVDD

N6

IFPC_PLLVDD

P6

IFPAB_PLLVDD

AD5

IFPDE_IOVDD

H6

IFPC_IOVDD

J6

IFPB_IOVDD

V2

IFPA_IOVDD

V3

PEX_SVDD_3V3

AG9

C23

4.7U 6.3V K X5R 0603

DIS@

1

2

C29

0.01U_0402_16V7K

DIS@

1

2

L1

MBK1608121YZF_0603

DIS@

1 2

C44

0.1U_0402_10V7K

DIS@

1

2

C497

0.1U_0402_10V7K

DIS@

1

2

C64

1U_0402_6.3V6K

DIS@

1

2

L21

MBK1608121YZF_0603

DIS@

12

C57

4.7U 6.3V K X5R 0603

DIS@

1

2

C48

1U_0402_6.3V6K

DIS@

1

2

C38

0.047U_0402_25V7K

DIS@

1

2

C74

0.1U_0402_10V7K

DIS@

1

2

C39

0.01U_0402_16V7K

DIS@

1

2

C552

22U_0805_6.3V6M

DIS@

1

2

C480

0.1U_0402_10V7K

DIS@

1

2

L27

MBK1608121YZF_0603

DIS@

1 2

C27

0.01U_0402_16V7K

DIS@

1

2

C52

0.01U_0402_16V7K

DIS@

1

2

C53

0.01U_0402_16V7K

DIS@

1

2

C73

4.7U 6.3V K X5R 0603

DIS@

1

2

C83

1U_0402_6.3V6K

DIS@

1

2

L5

MBK1608121YZF_0603

DIS@

1 2

C51

0.01U_0402_16V7K

DIS@

1

2

L29

MBK1608121YZF_0603

DIS@

12

C55

0.1U_0402_10V7K

DIS@

1

2

C66

0.1U_0402_10V7K

DIS@

1

2

C522

4700P_0402_25V7K

DIS@

1

2

C510

0.1U_0402_10V7K

DIS@

1

2

L3

MBK1608121YZF_0603

DIS@

1 2

C553

10U_0805_6.3V6M

DIS@

1

2

C59

0.1U_0402_10V7K

DIS@

1

2

C551

4.7U 6.3V K X5R 0603

DIS@

1

2

C45

1U_0402_6.3V6K

DIS@

1

2

C67

1U_0402_6.3V6K

DIS@

1

2

C68

4.7U 6.3V K X5R 0603

DIS@

1

2

C498

1U_0402_6.3V6K

DIS@

1

2

C72

1U_0402_6.3V6K

DIS@

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STRAP1

STRAP2

ROM_SO

ROM_SI

ROM_SCLK

STRAP0

STRAP2<20>

STRAP1<20>

STRAP0<20>

ROM_SO<20>

ROM_SI<20>

ROM_SCLK<20>

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

N10M-GE1 GND & STRAP

B

22 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

A total of 8 signals are required for GB1 strapping this includes

2 reference signals

A total of 24 logical strapping bits are available

6 physical strapping pins

4 logical strapping bits

Place Components Close to BGA

DG-04642-001-V01(May 22, 2009)

Memory/PKG

40.2 ohm

FB_CAL_PU_GND FBCAL_PD_VDDQ

DDR3

FBCAL_TERM_GNDFBVDDQ

+1.5VS

Must be used 1% resister for driver calibration

40.2/60.4 ohm40.2 ohm

N11M-GE1

LP1

X76

STRAP1 use for 3GIO_PADCFG to set 35K pull up.

(PUN-04335-001_V10 HW9 update)

K4W1G1646E-HC12

H5TQ1G63BFR-12C

PU 30KPD 10K

PU 35KN11M-GE1

LP1

(0x0A7D)

40nm

PD 15K

PD 15K

ROM_SO

PU 35K

ROM_SIROM_SCLK STRAP0STRAP1STRAP2GPU

Samsung

800MHz

(defaul)

PU 45K

FB Memory (DDR3)

PU 45KPD 10K PD 20K64Mx16

Hynix

800MHz

PU 30K

PD 15K64Mx16

R466

10K_0402_5%

DIS@

12

R464

40.2K_0402_1%

DIS@

12

R470

20K_0402_1%

X76@

12

R472

34.8K_0402_1%

DIS@

12

R467

2K_0402_5%

@

12

R476

10K_0402_5%

@

12

GND

Part 5 of 5

U22E

N11M-GE1-S-A2 _BGA533

DIS@

GND

B2

GND

B5

GND

B8

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND T14

GND T15

GND T16

GND U2

GND U5

GND U11

GND U12

GND U13

GND U14

GND U15

GND U16

GND U17

GND AF14

GND AF17

GND AF20

GND AF23

GND AF26

GND U23

GND U26

GND V9

GND V19

GND W11

GND W14

GND W17

GND Y2

GND Y5

GND Y23

GND Y26

GND AC2

GND AC5

GND AC6

GND AC8

GND AC11

GND AC14

GND AC17

GND AC20

GND AC23

GND AC26

GND AF2

GND AF5

GND AF8

GND AF11

GND

E17

GND

E20

GND

E23

GND

E26

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K9

GND

K19

GND

L2

GND

L5

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND_SENSE

E14

GND_SENSE

W16

FB_CAL_PU_GND A15

FB_CAL_TERM_GND B16

MULTI_STRAP_REF0_GND F10

MULTI_STRAP_REF1_GND F11

GND F6

R475

30K_0402_1%

DIS@

12

R471

34.8K_0402_1%

@

12

R473

45.3K_0402_1%

DIS@

12

R27 60.4_0402_1%

DIS@

1 2

R463

40.2K_0402_1%

DIS@

12

R469

2K_0402_5%

@

12

R28 40.2_0402_1%DIS@

1 2

R474

30K_0402_1%

@

12

R50

15K_0402_1%

@

12

R51

15K_0402_1%

DIS@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FBA CLK1#

FBA CLK1

FBA DQS#1

FBA DQM1

FBA DQS1

FBA CLK1

FBA CLK1#FBA CLK0#

FBA CLK0

FBA DQS#2

FBA DQM2

FBA DQS2

FBA _BA1

FBA A 11

FBAA5

FBAA4

FBACAS#

F BA WE#

FBA _BA0

FBA A 12

FBAA7

FBA A 10

FBA A_C KE

FBAA0

FBAA9

FBAA6

FBAA2

FBAA8

FBAA3

FBAA1

FBA A 13

FBA _BA2

FBA ACS0#

FBARAS#

FBA _ RST

FBA AODT0

FBA _ RST

FBAA0

FBA A 12

FBA A 13

FBA ACS0#

FBAA2

FBAA5

F BA WE#

FBAA3

FBA AODT0

FBAA9

FBAA7

FBACAS#

FBARAS#

FBAA4

FBA A_C KE

FBA _BA0

FBAA1

FBA _BA2

FBAA6

FBA _BA1

FBA A 11

FBA A 10

FBAA8

FBARAS#

FBA _BA1

FBBA2

FBBA4

FBBA3

FBB ACS0#

FBA A 11

FBACAS#

F BA WE#

FBA _BA0

FBBA5

FBA A 12

FBA _ RST

FBAA7

FBA A 10

FBAA0

FBAA9

FBAA6

FBAA8

FBAA1

FBA A 13

FBA _BA2

FBB AODT0

FBA _BA0

FBB AODT0

FBAA9

FBB ACS0#

FBAA8

FBBA2

FBA A 13

FBA A 10

FBARAS#

FBBA5

FBAA6

FBA _ RST

FBA A 11

FBBA4

F BA WE#

FBA _BA2

FBAA0

FBA _BA1

FBA A 12

FBAA1

FBAA7

FBACAS#

FBBA3

FBB A_C KE

FBB A_C KE

FBA CLK1#

FBA CLK1

FBA CLK0#

FBA CLK0

FBA DQS6

FBA DQM6

FBA DQS#6

FBA DQM[ 0 ..7]

F BA DQ S# [ 0. . 7]

F BA DQ S[ 0 . .7]

F BA _D [ 0. . 63]

F BA A[ 0 . .13]

F BB A[ 2 . .5]

FBA _D23

FBA _D21

FBA _D20

FBA _D18

FBA _D19

FBA _D17

FBA _D22

FBA _D16

FBA DQS5

FBA DQM5

FBA DQS#5

FBA _D24

FBA _D29

FBA _D27

FBA _D28

FBA _D26

FBA _D25

FBA _D31

FBA _D30

FBA DQS3

FBA DQM3

FBA DQS#3

FBA DQS0

FBA DQS#0

FBA DQM0

FBA _D0

FBA _D7

FBA _D5

FBA _D6

FBA _D1

FBA _D4

FBA _D3

FBA _D2

FBA _D58

FBA _D60

FBA _D56

FBA _D59

FBA _D62

FBA _D63

FBA _D57

FBA _D61

FBA _D39

FBA _D35

FBA _D38

FBA _D37

FBA DQM7

FBA DQS#7

FBA DQS7

FBA DQS4

FBA DQM4

FBA DQS#4

FBA _D48

FBA _D50

FBA _D55

FBA _D54

FBA _D52

FBA _D53

FBA _D51

FBA _D49

FBA _D8

FBA _D9

FBA _D13

FBA _D11

FBA _D10

FBA _D15

FBA _D12

FBA _D14

FBA _D41

FBA _D40

FBA _D42

FBA _D44

FBA _D43

FBA _D45

FBA _D46

FBA _D47FBA _D34

FBA _D33

FBA _D36

FBA _D32

FBA CLK0#<20> FBAC LK1#<20>

FBA CLK1<20>FBA CLK0<20>

FBA D[0. . 6 3]<20>

FBA DQS#[0.. 7]<20>

FBA DQS[ 0..7]<20>

FBA DQM[ 0 ..7]<20>

F BA RA S#<2 0>

FBA _BA0<20>

FBA _BA1<20>

FBA _BA2<20>

FBA A_C KE<20>

FBB A_C KE<20>

FBA _RST<20>

FBA AODT0<20> FB BAO DT0<20>

FBA ACS0#<20> F BBA C S0#<20>

F BA CA S#<2 0>

F B A WE #<20 >

+1. 5VS

+1. 5VS

+1. 5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS + 1.5VS

+VR AM_VREFA +VR A M_VREFB

+VR AM_V REFC + VRAM _VREF D

+VR AM_V REFA

+VR AM_VREFB

+VR AM_VREFA

+VR AM_VREFB

+VR AM_V REFC

+VR AM_V REFD

+VR AM_V REFC

+VR AM_V REFD

FBA A[0. .13]<20>

FBB A[2. .5]<20>

Title

Size Doc umen t Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0. 3

VRAM DDR3

C

23 51Thu rsda y, Oc t ober 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

N10x 40nm DDR3 MAPPING

NVIDIA COCUMENT FOR DA-3978-001

12MIL 12MIL

12MIL 12MIL

3

2

7 6

4 5

0

1

C51 8

10 U _0603_6.3V6M

D I S@

1

2

R52 3

240_0402_1%

D I S@

12

C 10

1U _ 040 2_6. 3V4Z

D I S@

1

2

10 0-BALL

SD R AM DDR 3

U1

K4 B1G1646 D-HC F 8_FBGA100

X76@

WE

L4

RAS

J4

CAS

K4

CS

L3

CKE/CKE0

K10

CK

J8

CK

K8

DQSU

B8

BA0

M3

BA1

N9

A2

P4

A3

N3

A4

P9

A5

P3

A6

R9

A7

R3

A8

T9

A9

R4

A10/AP

L8

A11

R8

DQL0 E4

DQL1 F8

DQL2 F3

DQL3 F9

DQL4 H4

DQL5 H9

DQL6 G3

DQL7 H8

VSSQ D2

VSS A10

VSS E2

VSS B4

NC/ODT1

J2

VDD B3

VDD D10

VDDQ A2

VDDQ A9

VDDQ C2

VDDQ C10

NC/CS1

L2

NC/CE1

J10

VDDQ E10

ZQ/ZQ0

L9

RESET

T3

DQSL

F4

DMU

D4 DML

E8

VSSQ B2

VSSQ B10

VSSQ D9

VSSQ E3

DQSU

C8

VSSQ E9

DQSL

G4

VDDQ F2

VSSQ F10

VSSQ G2

VDDQ H3

VDDQ H10

VSSQ G10

VREFCA

M9

VSS G9

VDD G8

ODT/ODT0

K2

A0

N4

A1

P8

VDD K3

A12

N8

VSS J3

VDD K9

DQU1 C4

DQU2 C9

DQU3 C3

DQU4 A8

DQU5 A3

DQU6 B9

DQU7 A4

DQU0 D8

A13

T4

A14

T8

A15/BA3

M8

BA2

M4

VREFDQ

H2

NCZQ1

L10

VDD N2

VDD N10

VDD R2

VDD R10

VSS J9

VSS M2

VSS M10

VSS P2

VSS P10

VSS T2

VSS T10

VDDQ D3

NC

A1

NC

A11

NC

T1

NC

T11

C44 6

1U _ 040 2_6.3V4Z

D I S@

1

2

C49 5

0. 1 U_04 02_10V6K

D I S@

1

2

+

C43 6

22 0U_B 2_2. 5VM_R35

1

2

R 21

240_0402_1%

D I S@

12

C 16

1U _ 040 2_6.3V4Z

D I S@

1

2

C 52 6

1U _ 040 2_6. 3V4Z

D I S@

1

2

10 0-BALL

SD R AM DDR 3

U 23

K4 B1G1646 D-HC F 8_FBGA100

X76@

WE

L4

RAS

J4

CAS

K4

CS

L3

CKE/CKE0

K10

CK

J8

CK

K8

DQSU

B8

BA0

M3

BA1

N9

A2

P4

A3

N3

A4

P9

A5

P3

A6

R9

A7

R3

A8

T9

A9

R4

A10/AP

L8

A11

R8

DQL0 E4

DQL1 F8

DQL2 F3

DQL3 F9

DQL4 H4

DQL5 H9

DQL6 G3

DQL7 H8

VSSQ D2

VSS A10

VSS E2

VSS B4

NC/ODT1

J2

VDD B3

VDD D10

VDDQ A2

VDDQ A9

VDDQ C2

VDDQ C10

NC/CS1

L2

NC/CE1

J10

VDDQ E10

ZQ/ZQ0

L9

RESET

T3

DQSL

F4

DMU

D4 DML

E8

VSSQ B2

VSSQ B10

VSSQ D9

VSSQ E3

DQSU

C8

VSSQ E9

DQSL

G4

VDDQ F2

VSSQ F10

VSSQ G2

VDDQ H3

VDDQ H10

VSSQ G10

VREFCA

M9

VSS G9

VDD G8

ODT/ODT0

K2

A0

N4

A1

P8

VDD K3

A12

N8

VSS J3

VDD K9

DQU1 C4

DQU2 C9

DQU3 C3

DQU4 A8

DQU5 A3

DQU6 B9

DQU7 A4

DQU0 D8

A13

T4

A14

T8

A15/BA3

M8

BA2

M4

VREFDQ

H2

NCZQ1

L10

VDD N2

VDD N10

VDD R2

VDD R10

VSS J9

VSS M2

VSS M10

VSS P2

VSS P10

VSS T2

VSS T10

VDDQ D3

NC

A1

NC

A11

NC

T1

NC

T11

C43 7

1U _ 040 2_6. 3V4Z

D I S@

1

2

C 19

1U _ 040 2_6. 3V4Z

D I S@

1

2

C47 9

1U _ 040 2_6. 3V4Z

D I S@

1

2

10 0-BALL

SD R AM DDR 3

U 21

K4 B1G1646 D-HC F 8_FBGA100

X76@

WE

L4

RAS

J4

CAS

K4

CS

L3

CKE/CKE0

K10

CK

J8

CK

K8

DQSU

B8

BA0

M3

BA1

N9

A2

P4

A3

N3

A4

P9

A5

P3

A6

R9

A7

R3

A8

T9

A9

R4

A10/AP

L8

A11

R8

DQL0 E4

DQL1 F8

DQL2 F3

DQL3 F9

DQL4 H4

DQL5 H9

DQL6 G3

DQL7 H8

VSSQ D2

VSS A10

VSS E2

VSS B4

NC/ODT1

J2

VDD B3

VDD D10

VDDQ A2

VDDQ A9

VDDQ C2

VDDQ C10

NC/CS1

L2

NC/CE1

J10

VDDQ E10

ZQ/ZQ0

L9

RESET

T3

DQSL

F4

DMU

D4 DML

E8

VSSQ B2

VSSQ B10

VSSQ D9

VSSQ E3

DQSU

C8

VSSQ E9

DQSL

G4

VDDQ F2

VSSQ F10

VSSQ G2

VDDQ H3

VDDQ H10

VSSQ G10

VREFCA

M9

VSS G9

VDD G8

ODT/ODT0

K2

A0

N4

A1

P8

VDD K3

A12

N8

VSS J3

VDD K9

DQU1 C4

DQU2 C9

DQU3 C3

DQU4 A8

DQU5 A3

DQU6 B9

DQU7 A4

DQU0 D8

A13

T4

A14

T8

A15/BA3

M8

BA2

M4

VREFDQ

H2

NCZQ1

L10

VDD N2

VDD N10

VDD R2

VDD R10

VSS J9

VSS M2

VSS M10

VSS P2

VSS P10

VSS T2

VSS T10

VDDQ D3

NC

A1

NC

A11

NC

T1

NC

T11

R9

1.33K_0402_1%

D I S@

12

C50 9

1U _ 040 2_6.3V4Z

D I S@

1

2

R52 9

1.33K_0402_1%

D I S@

12

C 43 8

1U _ 040 2_6.3V4Z

D I S@

1

2

C7

10 U _0603_6.3V6M

D I S@

1

2

C9

1U _ 040 2_6. 3V4Z

D I S@

1

2

C48 7

1U _ 040 2_6.3V4Z

D I S@

1

2

C 17

1U _ 040 2_6. 3V4Z

D I S@

1

2

10 0-BALL

SD R AM DDR 3

U 2

K4 B1G1646 D-HC F 8_FBGA100

X76@

WE

L4

RAS

J4

CAS

K4

CS

L3

CKE/CKE0

K10

CK

J8

CK

K8

DQSU

B8

BA0

M3

BA1

N9

A2

P4

A3

N3

A4

P9

A5

P3

A6

R9

A7

R3

A8

T9

A9

R4

A10/AP

L8

A11

R8

DQL0 E4

DQL1 F8

DQL2 F3

DQL3 F9

DQL4 H4

DQL5 H9

DQL6 G3

DQL7 H8

VSSQ D2

VSS A10

VSS E2

VSS B4

NC/ODT1

J2

VDD B3

VDD D10

VDDQ A2

VDDQ A9

VDDQ C2

VDDQ C10

NC/CS1

L2

NC/CE1

J10

VDDQ E10

ZQ/ZQ0

L9

RESET

T3

DQSL

F4

DMU

D4 DML

E8

VSSQ B2

VSSQ B10

VSSQ D9

VSSQ E3

DQSU

C8

VSSQ E9

DQSL

G4

VDDQ F2

VSSQ F10

VSSQ G2

VDDQ H3

VDDQ H10

VSSQ G10

VREFCA

M9

VSS G9

VDD G8

ODT/ODT0

K2

A0

N4

A1

P8

VDD K3

A12

N8

VSS J3

VDD K9

DQU1 C4

DQU2 C9

DQU3 C3

DQU4 A8

DQU5 A3

DQU6 B9

DQU7 A4

DQU0 D8

A13

T4

A14

T8

A15/BA3

M8

BA2

M4

VREFDQ

H2

NCZQ1

L10

VDD N2

VDD N10

VDD R2

VDD R10

VSS J9

VSS M2

VSS M10

VSS P2

VSS P10

VSS T2

VSS T10

VDDQ D3

NC

A1

NC

A11

NC

T1

NC

T11

R52 2

1.33K_0402_1%

D I S@

12

C 22

0. 1 U_04 02_10V6K

D I S@

1

2

C 18

1U _ 040 2_6.3V4Z

D I S@

1

2

R 11

1.33K_0402_1%

D I S@

12

R 19

1.33K_0402_1%

D I S@

12

C 11

1U _ 040 2_6. 3V4Z

D I S@

1

2

C8

0. 1 U_04 02_10V6K

D I S@

1

2

R 12

240_0402_1%

D I S@

12

R8

1.33K_0402_1%

D I S@

12

C44 4

10 U _0603_6.3V6M

D I S@

1

2

R 10

1.33K_0402_1%

D I S@

12

C5

1U _ 040 2_6. 3V4Z

D I S@

1

2

R7

240_0402_1%

D I S@

12

C 12

1U _ 040 2_6. 3V4Z

D I S@

1

2

C6

10 U _0603_6.3V6M

D I S@

1

2

C4

0. 1 U_04 02_10V6K

D I S@

1

2

C44 5

1U _ 040 2_6. 3V4Z

D I S@

1

2

C 21

10 U _0603_6.3V6M

D I S@

1

2

C3

10 U _0603_6.3V6M

D I S@

1

2

C51 7

1U _ 040 2_6. 3V4Z

D I S@

1

2

C 20

1U _ 040 2_6. 3V4Z

D I S@

1

2

R 14

243_0402_1%

D I S@

12

R 44 2

243_0402_1%

D I S@

1 2

C52 5

1U _ 040 2_6. 3V4Z

D I S@

1

2

R 20

1.33K_0402_1%

D I S@

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDMI_TX1+_CK

HDMI_TX2-_CK

HDMI_TX1-_CK

HDMI_CLK-_CK

HDMI_TX2+_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_CLK+_CK

HDMI_DETECT_VGA

HDMI_TX1+_CK

HDMI_TX2-_CK

HDMI_TX1-_CK

HDMI_CLK-_CK

HDMI_TX2+_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_CLK+_CK

HDMIDAT_R

HDMICLK_R

+5VS_HDMI

HDMI_TX0+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX1+_CONN

HDMI_ CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX2-_CONN

HDMI_TX0-_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_CLK+_CONN

HDMI_TX2-_CONN

HDMI_ CLK-_CONN

HDMI_TX2+_CONN

HDMI_TX1+_CK

HDMI_TX2-_CK

HDMI_TX1-_CK

HDMI_CLK-_CK

HDMI_TX2+_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_CLK+_CK

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_CLK+_CONN

HDMI_TX1+_CONN

HDMI_TX2-_CONN

HDMI_ CLK-_CONN

HDMI_TX1+_CK

HDMI_TX2-_CK

HDMI_TX1-_CK

HDMI_CLK-_CK

HDMI_TX2+_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_CLK+_CK

HDMICLK_R

HDMIDAT_R

HDMIDAT_R

HDMICLK_R

HDMI_ CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI_DET_UMA

HDMI_DETECT_VGA<19>

VGA_HDMI_SCL<20>

VGA_HDMI_SDA<20>

HDMICLK_R<25>

HDMIDAT_R<25>

VGA_HDMI_TX0-<20>

VGA_HDMI_TX0+<20>

VGA_HDMI_TX1-<20>

VGA_HDMI_CLK-<20>

VGA_HDMI_TX1+<20>

VGA_HDMI_TX2-<20>

VGA_HDMI_TX2+<20>

VGA_HDMI_CLK+<20>

HDMI_TX1+_CK<25>

HDMI_TX1-_CK<25>

HDMI_TX2+_CK<25>

HDMI_TX2-_CK<25>

HDMI_CLK+_CK<25>

HDMI_CLK-_CK<25>

HDMI_TX0+_CK<25>

HDMI_TX0-_CK<25>

HDMI_DET_UMA<25>

+3VS

+5VS

+5VS

+5VS +5VS

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

HDMI CONN

C u sto m

24 51Thursday, October 29, 2009

2008/03/25 2008/04/

Compal Electronics,Ltd.

LA-5752P

NEAR CONNECT

C599 0.1U_0402_16V7KD IS@

1 2

R595 499_0402_1%D IS@

1 2

C281 0.1U_0402_16V7KD IS@

1 2

D28

RB491D_SC59-3

HDMI@

21

R257

2.2K_0402_5%

HDMI@

1 2

R581

0_0805_5%

@R591 499_0402_1%D IS@

1 2

C284 0.1U_0402_16V7KD IS@

1 2

R587 499_0402_1%D IS@

1 2

C627

0.1U_0402_16V4Z

HDMI@

1

2

R584 0_0402_5%HDMI@

1 2

C302

12P_0402_50V8J

DIS@

1

2

L16 MBK1608121YZF_0603DIS @

1 2

L35

WCM-2012-900T_4P

@

1

1

4

433

22

L36

WCM-2012-900T_4P

@

1

1

4

433

22

R590 0_0402_5%HDMI@

1 2

R588 0_0402_5%HDMI@

1 2

R579

10K_0402_1%

DIS@

1 2

D23

BAT54S-7-F_SOT23-3

@

2

3

1

C282 0.1U_0402_16V7KD IS@

1 2

D25

BAT54S-7-F_SOT23-3

@

2

3

1

R582 0_0402_5%HDMI@

1 2

C601 0.1U_0402_16V7KD IS@

1 2

R594 0_0402_5%HDMI@

1 2

R249

2.2K_0402_5%

HDMI@

1 2

R589 499_0402_1%D IS@

1 2

R597 499_0402_1%D IS@

1 2

C600 0.1U_0402_16V7KD IS@

1 2

D24

BAT54S-7-F_SOT23-3

@

2

3

1

L15 MBK1608121YZF_0603DIS @

1 2

R592 0_0402_5%HDMI@

1 2

D22

RB751V_SOD323

@

2 1

JHDMI1

TA ITW _PD VBR9 -19 FLBS4NN4N 1

ME@

D2+

1D2_shield

2D2-

3D1+

4D1_shield

5D1-

6D0+

7D0_shield

8D0-

9CK+

10 CK_shield

11 CK-

12 CEC

13 Reserved

14 SCL

15 SDA

16 DDC/CEC_GND

17 +5V

18 HP_DET

19

GND 20

GND 21

GND 22

GND 23

C295

12P_0402_50V8J

DIS@

1

2

R585 499_0402_1%D IS@

1 2

R583 499_0402_1%D IS@

1 2

G

D

S

Q41

2N7002W -T/R7_SOT323-3

DIS@

2

13

L33

WCM-2012-900T_4P

@

1

1

4

433

22

R593 499_0402_1%D IS@

1 2

R578

100K_0402_5%

DIS@

1 2

L34

WCM-2012-900T_4P

@

1

1

4

433

22

C283 0.1U_0402_16V7KD IS@

1 2

R596 0_0402_5%HDMI@

1 2

C614 0.1U_0402_16V7KD IS@

1 2

R586 0_0402_5%HDMI@

1 2

C603

330P_0402_50V7K

DIS@

L30MBK1608121YZF_0603

DIS@

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDMI_CLK+_CK

HDMI_TX2-_CK

TMDS_B_HPD#

HDMI_TX2+_CK

HDMI_DET_UMA

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMIDAT_R

HDMICLK_R

HDMI_TX1+_CK

HDMI_TX0-_CK

HDMI_TX1-_CK

TMDS_B_HPD#

TMDS_B_DATA2<15>

TMDS_B_DATA2#<15>

TMDS_B_CLK<15>

TMDS_B_CLK#<15>

TMDS_B_HPD# <15>

TMDS_B_DATA1<15>

TMDS_B_DATA1#<15>

TMDS_B_DATA0<15>

TMDS_B_DATA0#<15>

HDMICLK_R<24>

HDMIDAT_R<24>

HDMI_DET_UMA<24>

HDMICLK_NB <15>

HDMIDAT_NB <15>

HDMI_CLK+_CK <24>

HDMI_CLK-_CK <24>

HDMI_TX0+_CK <24>

HDMI_TX0-_CK <24>

HDMI_TX1+_CK <24>

HDMI_TX1-_CK <24>

HDMI_TX2+_CK <24>

HDMI_TX2-_CK <24>

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

Level Shiftter_ASM1442

C u sto m

25 51Thursday, October 29, 2009

2008/03/25 2008/04/

Compal Electronics,Ltd.

LA-5752P

P/N:SA00001U900 (CH7318A)

P/N:SA00002D700 (8101T)

internal pull down

internal pull down

FOR 7318C PIN6 PULL DOWN 1.2Kohm

PIN7 PULL DOWN 7.5Kohm

PIN7 PULL UP 20Kohm

input

output

R428 STUFF

RESERVE THE R668 PULL UP TO 3VS

FOR asmedia

RESERVE THE R670 PULL DOWN TO GND

CHANGE R483 FROM 499 TO 3.4K OHM

P/N:SA00003GT00 (ASM1442)

R253

20K_0402_1%

@

12

R232 4.7K_0402_5%@

1 2

U12

ASM1442_QFN48_7X7

UMA_HDMI@

VCC 2

REXT 6

HPD# 7

SDA 8

SCL 9

RT_EN# 10

GND 12

GND 5

GND 1

GND 18

GND 24

GND 27

GND 31

GND 36

GND 37

GND 43

VCC 11

VCC 15

VCC 21

VCC 26

VCC 33

VCC 40

VCC 46

PC1 4

PC0 3

OUT_D4+ 13

OUT_D4- 14

OUT_D3+ 16

OUT_D3- 17

OUT_D2+ 19

IN_D4+

48

IN_D4-

47

IN_D3+

45

IN_D3-

44

IN_D2+

42

IN_D2-

41

IN_D1-

38

OE#

25

SCL_SINK

28

SDA_SINK

29

HPD_SINK

30

DDC_EN

32

OUT_D2- 20

OUT_D1+ 22

OUT_D1- 23

IN_D1+

39

CFG0

34

CFG1

35

PAD 49

R255

4.7K_0402_5%

@

1 2

R245 3.4K_0402_1%UMA_HDMI@

1 2

R254

4.7K_0402_5%

@

1 2

R243

0_0402_5%

@

12

R230

0_0402_5%

UMA_HDMI@

12

C602

0.1U_0402_16V4Z

UMA_HDMI@

1

2

R248 4.7K_0402_5%@

1 2

R247

4.7K_0402_5%

@

1 2

C285

10U_0805_10V4Z

UMA_HDMI@

1

2

R252

7.5K_0402_1%

@

12

R244

4.7K_0402_5%

@

1 2

R246 4.7K_0402_5%@

1 2

C604

0.1U_0402_16V4Z

UMA_HDMI@

1

2

C280

0.1U_0402_16V4Z

UMA_HDMI@

1

2

R242

4.7K_0402_5%

UMA_HDMI@

12

R231

0_0402_5%

@

12

R256

4.7K_0402_5%

@

1 2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

CRT_R

CRT_G

CRT_BDAC_BLU

DAC_RED

DAC_GRN

CRT_R

CRT_R

CRT_G

CRT_BVGA_CRT_B

VGA_CRT_R

VGA_CRT_G

CRT_G

CRT_B

R EDGR EENBLUE

CRT_DDC_DAT_CONN

CRT_DDC_DAT_CONN

CRT_DDC_CLK_CONN

R ED

CRT_DDC_DATA

CRT_DDC_CLK

CRT_HSYNC_1

GREEN

JVGA_HS

BLUE

VSYNC_G

JVGA_VSJVGA_HS

CRT_DDC_CLK_CONN

H S YNC _G

CRT_VSYNC_1 JVGA_VS

R ED

GREEN

JVGA_HS

JVGA_VS

BLUE

VGA_DDCDATA

VGA_DDCCLK

CRT_DDC_DATA_R

CRT_DDC_CLK_R

VGA_HSYNC<19>

CRT_HSYNC<15>

CRT_DDC_DATA<15>

CRT_DDC_CLK<15>

VGA_VSYNC<19>

CRT_VSYNC<15>

VGA_DDCDATA<19>

VGA_DDCCLK<19>

DAC_RED<15>

DAC_GRN<15>

DAC_BLU<15>

VGA_CRT_R<19>

VGA_CRT_G<19>

VGA_CRT_B<19>

+3VS

+5VS +5VS +5VS +5VS +5VS

+5VS

+CRT_VCC

+CRT_VCC

+CRT_VCC

+CRT_VCC

+3VS

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

CRT Connector

C u sto m

26 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

UMA only

DIS only

CLOSE TO CONN

CRT Connector

W=40mils

C619

0.1U_0402_16V4Z

1

2

C145

10P_0402_50V8J

1

2

R93 0_0402_5%UMA@

1 2

R153

150_0402_1%

12

R91 0_0402_5%UMA@

1 2

L10

FCM1608CF-121T03 0603

1 2

R71 0_0402_5%

DIS@

12

L9

FCM1608CF-121T03 0603

1 2

R575

1K_0402_5%

1 2

D21

RB491D_SC59-3

2 1

C146

10P_0402_50V8J

1

2

C620

0.1U_0402_16V4Z

1

2

L31 FCM1608CF-121T03 0603

1 2

U25

SN74AHCT1G125DCKR_SC70-5

A

2Y4

OE# 1

G

3P5

C157

10P_0402_50V8J

1

2

R66 0_0402_5%DIS@

1 2

R67 0_0402_5%DIS@

1 2

R94 0_0402_5%UMA@

1 2

R70 0_0402_5%

DIS@

12

C625

10P_0402_50V8J

@

1

2

U26

SN74AHCT1G125DCKR_SC70-5

A

2Y4

OE# 1

G

3P5

Q13B

2N7002DW -T/R7_SOT363-6

3

5

4

R65 0_0402_5%DIS@

1 2

G

G

JCRT1

TYCO_1775763-1

ME@

6

11

1

7

12

2

8

13

3

9

14

4

10

15

5

16

17

C178

100P_0402_50V8J

@

1

2

R580

1K_0402_5%

1 2

D3

BAT54S-7-F_SOT23-3

@

2

3

1

R97 0_0402_5%

UMA@

12

Q13A

2N7002DW -T/R7_SOT363-6

61

2

C137

10P_0402_50V8J

1

2

R68 0_0402_5%DIS @

1 2

L11

FCM1608CF-121T03 0603

1 2

R158

2.2K_0402_5%

12

R157

2.2K_0402_5%

12

C177

68P_0402_50V8K

@

1

2

R159

2.2K_0402_5%

12

C629

0.1U_0402_16V4Z

1

2

R92 0_0402_5%UMA@

1 2

D27

BAT54S-7-F_SOT23-3

@

2

3

1

L32 FCM1608CF-121T03 0603

1 2

D1

BAT54S-7-F_SOT23-3

@

2

3

1

R131

150_0402_1%

12

R69 0_0402_5%DIS @

1 2

D2

BAT54S-7-F_SOT23-3

@

2

3

1

R90

150_0402_1%

12

C628

100P_0402_50V8J

<BOM Structure>

1

2

D26

BAT54S-7-F_SOT23-3

@

2

3

1

R95 0_0402_5%UMA@

1 2

F1

1.1A_6V_SMD1812P110TF

21

R96 0_0402_5%

UMA@

12

R162

2.2K_0402_5%

12

C626

10P_0402_50V8J

@

1

2

C136

10P_0402_50V8J

1

2

C158

10P_0402_50V8J

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BKOFF#

DAC_BRIG

LCD_ENVDD

DISPOFF#

EDID_CLK

EDID_DATA CONN_LVDS_SDA

CONN_LVDS_SCL

CONN_LVDS_A1

CONN_LVDS_A1#

CONN_LVDS_ACLK#

CONN_LVDS_ACLK

CONN_LVDS_A0

CONN_LVDS_A0#

CONN_LVDS_A2#

CONN_LVDS_A2

LVDS_A2#

LVDS_A2

LVDS_A1#

LVDS_A1

LVDS_A0

LVDS_A0#

INVPWM

INVPWM

CMOS1

CONN_LVDS_SDA

CONN_LVDS_SCL

VGA_LVDS_SDA

VGA_LVDS_SCL

VGA_LVDS_A1

VGA_LVDS_A1#

VGA_LVDS_ACLK#

VGA_LVDS_ACLK

VGA_LVDS_A0

VGA_LVDS_A0#

VGA_LVDS_A2#

VGA_LVDS_A2

CONN_LVDS_A1

CONN_LVDS_A1#

CONN_LVDS_ACLK#

CONN_LVDS_ACLK

CONN_LVDS_A0

CONN_LVDS_A0#

CONN_LVDS_A2#

CONN_LVDS_A2

INVPWM

DISPOFF#

CONN_LVDS_A1

CONN_LVDS_A2#

CONN_LVDS_A1#

CONN_LVDS_A2

CONN_LVDS_ACLK#

CONN_LVDS_ACLK

CONN_LVDS_A0

CONN_LVDS_A0#

CONN_LVDS_SCL

USB20_N2

USB20_P2

DISPOFF#

INVPWM

CONN_LVDS_SDA

LVDS_ACLK

LVDS_ACLK#

PCH_PWM_R

BKOFF#<34>

PCH_PWM<15>

CMOS_OFF#<34>

USB20_N2 <16>

USB20_P2 <16>

INVT_PWM<34>

DAC_BRIG<34>

LCD_COLOR_1

VGA_LVDS_SCL<19>

VGA_LVDS_SDA<19>

EDID_CLK<15>

EDID_DATA<15>

VGA_LVDS_A0<20>

VGA_LVDS_A0#<20>

VGA_LVDS_A1<20>

VGA_LVDS_A1#<20>

VGA_LVDS_A2<20>

VGA_LVDS_A2#<20>

VGA_LVDS_ACLK<20>

VGA_LVDS_ACLK#<20>

LVDS_A2<15>

LVDS_A2#<15>

LVDS_A1<15>

LVDS_A1#<15>

LVDS_A0<15>

LVDS_A0#<15>

LVDS_ACLK#<15>

LVDS_ACLK<15>

PCH_ENBKL<15>

VGA_ENBKL_R<19> ENBKL <34>

VGA_ENVDD_R<19>

PCH_ENVDD<15>

+3VS

+3VS

+LCDVDD +5VALW

+LCDVDD_CONN

+LCDVDD

+3VS

+3VS

+5VS

+LEDVDD B+

+LCDVDD_CONN

+3VS

+CMOS_PW

+3VS

+CMOS_PW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

LVDS/CAMERA

B

27 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

LCD POWER CIRCUIT

DTC124EK

W=60mils

W=60mils

For EMI

For GMCH DPST

CMOS

CMOS Camera

(60 MIL)

R3830_0402_5% UMA@ 12

R850_0402_5% DIS@ 12

C13

470P_0402_50V7K

@

1

2

R3840_0402_5% UMA@ 12

R1500_0402_5% DIS@ 12

R549 0_0805_5%

1 2

R3850_0402_5% UMA@ 12

R3870_0402_5% UMA@ 12

R259

100K_0402_1%

1 2

C34

0.1U_0402_16V4Z

1

2

C337

10U_0805_10V4Z

CMOS@

1

2

C25

0.1U_0402_16V4Z

1

2

R261 0_0402_5%DIS@

1 2

C14

680P_0402_50V7K

@1

2

R31

100K_0402_5%

12

R3820_0402_5% UMA@ 12

R161

0_0402_5%

UMA@

1 2

U6

NC7SZ14P5X_NL_SC70-5

UMA@

A

2Y4

P5

NC 1

G

3

R36 0_0402_5%

DIS@

12

R160

0_0402_5%

@

1 2

C296

470P_0402_50V7K

@

1

2

C33

4.7U_0805_10V4Z

1

2

R3890_0402_5% UMA@ 12

C326 0.01U_0402_16V7K

CMOS@

1 2

C539

4.7U_0805_10V4Z

1

2

R550 0_0805_5%

1 2

Q21

DTC124EKAT146_SC59-3

CMOS@

IN

2

OUT 1

GND

3

C566

4.7U_0805_25V6-K

1

2

R270

10K_0402_5%

CMOS@

12

C567

680P_0402_50V7K

@

1

2

R1260_0402_5% DIS@ 12

R3930_0402_5% UMA@ 12

G

D

S

Q12

2N7002_SOT23

@

2

13

C275

0.1U_0402_16V4Z

CMOS@

1

2

D12

CH751H-40PT_SOD323-2

21

R1270_0402_5% DIS@ 12

R37

100K_0402_5%

@

12

R840_0402_5% DIS@ 12

R17

0_0402_5% DIS@

1 2

R3860_0402_5% UMA@ 12

R3880_0402_5% UMA@ 12

C15

470P_0402_50V7K

@

1

2

R260 0_0402_5%

UMA@

1 2

R860_0402_5% DIS@ 12

R1280_0402_5% DIS@ 12

R280

0_0603_5%

CMOS@

12

JLVDS1

ACES_87142-3041

ME@

GND 31

GND

32

11

2

2

33

4

4

55

6

6

77

8

8

99

10

10

11 11

12

12

13 13

14

14

15 15

16

16

17 17

18

18

19 19

20

20

21 21

22

22

23 23

24

24

25 25

26

26

27 27

28

28

29 29

30

30

G

D

S

Q3

2N7002_SOT23

2

13

R392

2.2K_0402_5%

@

R35 0_0402_5%

UMA@

12

R1250_0402_5% DIS@ 12

G

D

S

Q24 AO3413_SOT23-3

CMOS@

2

13

R13

150_0603_1%

R3910_0402_5% DIS@ 12

R38 220K_0402_5%

1 2

R250

4.7K_0402_5%

12

G

D

S

Q4

AO3413_SOT23-3

2

1 3

R395

2.2K_0402_5%

@

R156

10K_0402_5% @

12

R3900_0402_5% DIS@ 12

R3940_0402_5% UMA@ 12

L2

FBMA-L11-201209-221LMA30T_0805

1 2

Q5

DTC124EKAT146_SC59-3

IN

2

OUT 1

GND

3

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

WLA N_CL KREQ 1#

BT _ ACT IVE

PC I E_WA K E#

C PU SB#

PE RST#

EC_TX_P80_DATA

EC _ RX_P80_CLK

WLA N_LED#

SYSON

SUSP#

U IM _ DAT A

UIM_ VPP

U IM _ C LK

U IM _ RST

+UI M _PWR

+UI M _PWR

+ UI M _P W RU IM _ DAT A

PE RST#

C PU SB#

USB 20_P10

USB 20_ N10

C PU SB#

+UI M _PWR

U IM _ DAT A

U IM _ C LK

U IM _ RST

PC I ECLK R EQ3#

USB 20_ N13

USB 20_P13

BT _ ACT IVE

PC I E_WA K E#

UIM_ VPP

EC_TX_P80_DATA

EC _ RX_P80_CLK

LP C _F R AM E#

LP C _AD 3

LP C _AD 2

LP C _AD 1

LP C _AD 0

LP C _F R AM E #_R

LP C _AD 3_R

LP C _AD 2_R

LP C _AD 1_R

LP C _AD 0_R

LP C _F R AM E #_R

LP C _AD 3_R

LP C _AD 2_R

LP C _AD 1_R

LP C _AD 0_R

PC I _RST#_R

CLK _PC I _DB

PC I _R S T#

CLK _PC I _DB

PC I _RST#_R

CLK _PC I E_WL AN1<14>

PC I E_WA KE#<15>

WLA N_CL KREQ 1#<14>

CLK _PC I E_WL AN1#<14>

BU F _PLT_RST#< 5,16,19,29>

CPU SB#<16>

USB 20_ N8 <16>

USB 20_P8 <16>

BU F _PLT_RST# <5, 16,19,29>

W L_ OF F# < 34>

EC_TX_P80_DATA<34,35>

EC _ RX_P80_CLK<34,35>

WLA N_LED# <36>

BT _ACT IVE<37>

SYSO N<34,39,44>

SU S P#<16,34,39,42,44,46>

SM B _CLK_S3 <1 0,11,12,14>

SM B_DATA_S3 < 10, 11,12,14>

PC I E_PTX_C_DRX_N2<14>

PC I E_PTX_C_DRX_P2<14>

PC I E_PRX_DTX_N2<14>

PC IE_PRX_DT X_P2<14>

PC IE_PRX_DT X_P5<14>

C PU SB #<16>

USB 20_ N10<16>

CLK _PC I E_EXP_PCH<14>

PC I E_PRX_DTX_N5<14>

CLK _PC I E_EXP_PCH#<14>

SM B _DATA_S3<10 ,11,12,14>

SM B _CLK_S3< 10,11,12,14>

CLK REQ_EXP#<14>

PC I E_PTX_C_DRX_P5<14>

USB 20_P10<16>

PC I E_WA KE#<15>

PC I E_PTX_C_DRX_N5<14>

C LK _P CI E_ CA RD _P CH<14>

PC I E_WA KE#<15>

PC I ECLK R EQ3#<14>

BU F _PLT_RST# <5, 16,19,29>

CLK _PC I E_CA R D_PC H #<14>

SM B _CLK_S3 <1 0,11,12,14>

SM B _DATA_S3 <1 0,11,12,14>

3G _OFF# <34>

EC_TX_P80_DATA<34,35>

EC _ RX_P80_CLK<34,35>

BT _ACT IVE<37>

PC I E_PRX_DTX_N4<14>

USB 20_P13 <16>

USB 20_ N13 <16>

PC I E_PTX_C_DRX_N4<14>

PC I E_PTX_C_DRX_P4<14>

PC IE_PRX_DT X_P4<14>

LP C _AD 2 < 13,34>

LP C _AD 1 < 13,34>

LP C _AD 3 < 13,34>

LP C _AD 0 < 13,34>

LP C _FRAME# <13,34>

PC I _RST# <16,34>

CLK _PC I _DB <14>

+3VS

+1.5VS

+3VALW

+3VS

+3VALW

+1. 5VS_CARD1

+3VALW _CARD1

+3VS_C ARD1

+1.5VS

+3VS

+3VALW

+3VS

+3VS

+3VALW

+3VALW

+3VS

+3VS

+3VS_C ARD1

+1. 5VS_CARD1

+3VALW _CARD1

+3VS_C ARD1

+1. 5VS_CARD1

+3VALW _CARD1

+1. 5VS

+1.5VS

+3VS

+3VS

+3VS

+3VS

+3VALW

+1.5VS

Title

Size Doc umen t Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0 . 3

Mini-Card/Nwe Card/SIM

28 51Thu rsda y, Oc t ober 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

Mini-Express Card for WLAN/WiMAX(Half)

60mil

40mil

40mil

Express Card Power Switch

2Watt

40mil

Mini-Express Card for WWAN(Full)

New Card 34mm Socket (Left/TOP)

Imax = 0.275A

Imax = 0.75A

Imax = 1.35A

Mini-Express Card(WWAN 3G)

Vcc 3.3V +/- 8%

Peak Icc 2750mA

with max supply droop 50mA

Average Icc 1000mA

2Watt

Mini-Express Card(WLAN/WiMAX)

Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.

C18 8

4. 7 U_08 05_10V4Z

1

2

R 36 6 0_ 04 02_5%@

1 2

C36 0

10 U _08 05_10V4Z

1

2

C 42 2

0. 1 U_04 02_16V4Z

1

2

R 36 8 0_ 04 02_5%3 G@

1 2

R37 1300_0402_5%

12

C35 7

0. 1 U_04 02_16V4Z

1

2

R 36 9 0_ 04 02_5%@

1 2

D5

DAN 217T 146_SC59-3

@

2

3

1

R27 4

100_0402_1%

1 2

R 33 4 10 0K _04 02_5%@

1 2

R28 4 0_0 402_5%@

1 2

J P2

TAI T W _PMPAT6-06GLBS7N14N0

ME@

VCC 1

RST 2

CLK 3

GND

4

VPP

5

I/O

6

GND 8

GND 9

DET

7

C41 8

10 U _08 05_10V4Z

1

2

R 37 6 0_ 04 02_5%@

1 2

D 4

CM1293-04SO_SOT23-6

@

CH3 6

Vp 5

CH4 4

CH2

3

Vn

2

CH1

1

C35 8

0. 1 U_04 02_16V4Z

1

2

R27 3

100_0402_1%

1 2

R 37 3 0_ 04 02_5%@

1 2

R28 7 0_0 402_5%@

1 2

R28 6 0_0 402_5%@

1 2

C38 6

0. 1 U_04 02_16V4Z

1

2

J 4

JUMP_43X79

@

11

2

2

R28 5 0_0 402_5%@

1 2

R 37 7 0_ 04 02_5%

1 2

R 37 4 0_ 04 02_5%@

1 2

C38 8

10 U _08 05_10V4Z

1

2

R28 8 0_0 402_5%@

1 2

U 15

G5 77BSR91 U _QFN20

3.3Vin

2

3.3Vin

43.3Vout 3

3.3Vout 5

SYSRST#

6

SHDN#

20

STBY#

1

PERST# 8

OC# 19

RCLKEN

18

AUX_IN

17 AUX_OUT 15

CPPE#

10

CPUSB#

9

NC 16

GND 7

1.5Vin

12

1.5Vin

14 1.5Vout 11

1.5Vout 13

C35 6

10 U _08 05_10V4Z

@

1

2

R37 0 0_0 402_5%@

1 2

R15 2

10 K_0402_5%

@

12

R 36 5 0_ 04 02_5%@

1 2

JP1 0

TAI T W _PF PET0-AF GLBG1ZZ4N0

ME@

WAKE#

1

NC

3

NC

5

CLKREQ#

7

GND

9

REFCLK-

11

REFCLK+

13

GND

15

NC

17

NC

19

GND

21

PERn0

23

PERp0

25

GND

27

GND

29

PETn0

31

PETp0

33

GND

35

NC

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

GND

53

3.3V 2

GND 4

1.5V 6

NC 8

NC 10

NC 12

NC 14

NC 16

GND 18

NC 20

PERST# 22

+3.3Vaux 24

GND 26

+1.5V 28

SMB_CLK 30

SMB_DATA 32

GND 34

USB_D- 36

USB_D+ 38

GND 40

LED_WWAN# 42

LED_WLAN# 44

LED_WPAN# 46

+1.5V 48

GND 50

+3.3V 52

GND 54

C35 9

0. 1 U_04 02_16V4Z

1

2

C42 0

10 U _08 05_10V4Z

@

1

2

C 41 7

0. 1 U_04 02_16V4Z

1

2

R29 0 0_0 402_5%@

1 2

R33 3 0_0 402_5%@

1 2

C41 9

0. 1 U_04 02_16V4Z

1

2

R 37 5 0_ 04 02_5%

1 2

R15 1

10K_0402_5%

12

R36 4

100_0402_1%

3G @

1 2

R 36 7 0 _0 402_5%@

1 2

C37 2

0. 1 U_04 02_16V4Z

1

2

C38 7

0. 1 U_04 02_16V4Z

1

2

J P9

TAI T W _PF PET0-AF GLBG1ZZ4N0

ME@

WAKE#

1

NC

3

NC

5

CLKREQ#

7

GND

9

REFCLK-

11

REFCLK+

13

GND

15

NC

17

NC

19

GND

21

PERn0

23

PERp0

25

GND

27

GND

29

PETn0

31

PETp0

33

GND

35

NC

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

GND

53

3.3V 2

GND 4

1.5V 6

NC 8

NC 10

NC 12

NC 14

NC 16

GND 18

NC 20

PERST# 22

+3.3Vaux 24

GND 26

+1.5V 28

SMB_CLK 30

SMB_DATA 32

GND 34

USB_D- 36

USB_D+ 38

GND 40

LED_WWAN# 42

LED_WLAN# 44

LED_WPAN# 46

+1.5V 48

GND 50

+3.3V 52

GND 54

C17 6

0. 1 U_04 02_16V4Z

1

2

R37 2300_0402_5% @

12

R36 3 100_0402_1%

3G @

1 2

JEXP1

SANTA_130801-5_LT

ME@

GND

1

USB_D-

2

USB_D+

3

CPUSB#

4

RSV

5

RSV

6

SMB_CLK

7

SMB_DATA

8

+1.5V

9

+1.5V

10

WAKE#

11

+3.3VAUX

12

PERST#

13

+3.3V

14

+3.3V

15

CLKREQ#

16

CPPE#

17

REFCLK-

18

REFCLK+

19

GND

20

PERn0

21

PERp0

22

GND

23

PETn0

24

PETp0

25

GND

26

GND

27

GND

28

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

LAN_CS

LAN_SK#

LAN_DI

ACTIVITY#

VCTRL12

ISOLATEB

LAN_XTALO

LAN_XTALI

ISOLATEB

LAN_DI

LAN_CS

EN_WOL#

PCIE_IRX_C_PTX_N3

PCIE_IRX_C_PTX_P3

LAN_XTALOLAN_XTALI

VCTRL12

MDI1+

MDI0-

MDI0+

MDI2+

MDI1-

MDI2-

MDI3+

MDI3-

CLK_PCIE_LAN#<14>

CLK_PCIE_LAN<14>

CLKREQ_LAN#<14>

LAN_WAKE#<34>

BUF_PLT_RST#<5,16,19,28>

EN_WOL#<34>

PCIE_PRX_DTX_N3<14>

PCIE_PRX_DTX_P3<14>

PCIE_PTX_C_DRX_N3<14>

PCIE_PTX_C_DRX_P3<14>

MDI1+ <30>

MDI2- <30>

MDI2+ <30>

MDI0- <30>

MDI0+ <30>

MDI1- <30>

MDI3+ <30>

MDI3- <30>

ACTIVITY# <30>

LAN_SK# <30>

+EVDD12

+LAN_VDD12

+3VS

+3V_LAN

+3V_LAN

+3V_LAN

+3V_LAN

+3VALW

+5VALW

+3V_LAN

+EVDD12

+LAN_VDD12

+LAN_VDD12

+3V_LAN

+3V_LAN

+LAN_VDD12

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

RTL8103EL

Custom

29 51

Thursday, October 29, 2009

2006/08/04 2006/10/06

Compal Electronics, Inc.

LA-5752P

Place Close to Chip

Layou t Notic e : Place as close

ch ip a s possible.

Close to 8111DL pins--1,29,37

The trace length L69 to 8111DL's pin<200mils.

L69 to C934/C941<200mils. Close to U44 pin19

Close to U44 pin10,13,30,36

For RTL8111DL pin43:

pull hi if switching regulator is enable.

pull low if external power 1.2Vis used.

For RTL8103EL is NC.

40 mil width

60 mil width

60 mil width

Close to pin.

C246

0.1U_0402_16V4Z

1

2

R172

0_0603_5%GIGA@

1 2

C238

22U_0805_6.3V6M

1

2

R205

15K_0402_5%

R170

0_0603_5%100@

1 2

R219

33K_0402_5%

12

C261

4.7U_0805_10V4Z

C251

1U_0603_10V4Z

1

2

L12

S INDUC_ 4.7UH +-20% SIA4012-4R7M

GIGA@

1 2

G

D

S

Q17

AO3414_SOT23-3

2

1 3

R177

0_0402_5%GIGA@

12

C597

0.1U_0402_16V4Z

1

2

C239

0.1U_0402_16V4Z

1

2

C244

22U_0805_6.3V6M

GIGA@

1

2

C611

30P_0402_50V8J

1

2

R180

0_0402_5%

GIGA@

1 2

RTL8111DL

U24

RTL8111DL-VB-GR_LQFP48_7X7

GIGA@

AVDD33 1

MDIP0 2

MDIN0 3

FB12 4

MDIP1 5

MDIN1 6

GND

7

MDIP2 8

MDIN2 9

AVDD12 10

MDIP3 11

MDIN3 12

RSET

46

SROUT12 48

GND

47

CKTAL2

42 CKTAL1

41

AVDD33 40

VDDSR 44

LED0 38

VDD33 37

ENSR 43

DVDD12 13

GND

14

HSIP

15

HSIN

16

REFCLK_P

17

REFCLK_N

18

EVDD12 19

HSOP

20

HSON

21

EGND

22

GPO

23

NC

24

LED1/EESK 35

LED2/EEDI/AUX 34

LED3/EEDO 33

EECS 32

DVDD12 36

GND

31

DVDD12 30

VDD33 29

ISOLATEB

28

PERSTB

27

LANWAKEB

26

CLKREQB

25

AVDD12 39

VDDSR 45

C593 0.1U_0402_16V7K

C612

30P_0402_50V8J

1

2

R182 3.6K_0402_5%

100@

1 2

C245

0.1U_0402_16V4Z

1

2

J1

JOPEN

@

12

R179

0_0402_5%

@

1 2

R173

0_0603_5%GIGA@

1 2

C613

0.1U_0402_16V4Z

1

2

C243

0.1U_0402_16V4Z

GIGA@

12

U24

RTL8103EL-VB-GR

100@

R171 2.49K_0402_1%

1 2

R203 1K_0402_5%

1 2

C267

0.1U_0402_16V4Z

1

2

C242

0.1U_0402_16V4Z

GIGA@

1

2

R206 10K_0402_5%

@

12

R576

0_0603_5%GIGA@

1 2

R577

0_0603_5%100@

1 2

C594 0.1U_0402_16V7K

C247

0.1U_0402_16V4Z

1

2C248

0.1U_0402_16V4Z

1

2

Y3

25MHZ_20P

1 2

C260

0.1U_0402_16V4Z

1

2

R204

1K_0402_5%

12

C250

1U_0603_10V4Z

1

2

G

D

S

Q18

2N7002_SOT23-3

2

13

R181

0_0402_5%GIGA@

12

C259

0.1U_0402_16V4Z

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MDI1-

MDI1+

MDI0+

MDI0- MDO0-

MDO0+

MCT0

MCT1

MDO1-

MDO1+

MDO2+

MDO2-

MCT2

MCT3

MDO3+

MDO3-

MDI2+

MDI2-

MDI3-

MDI3+

ACTIVITY#

LAN_SK#

MDO2+

MDO0-

MDO1+

MDO1-

MDO2-

MDO3+

MDO3-

MDO0+

MDI0+<29>

MDI0-<29>

MDI1+<29>

MDI1-<29>

MDI2-<29>

MDI2+<29>

MDI3-<29>

MDI3+<29>

LAN_SK#<29>

ACTIVITY#<29>

+3V_LAN

+3V_LAN

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

LAN_Transformer

C u sto m

30 51Thursday, October 29, 2009

2009/03/20 2010/03/20

Compal Electronics, Inc.

LA-5752P

RJ45 Conn.

Place close to TCT pin

Close to T14

For EMI.

R52 75_0402_5%

12

T16

HH-065

100@

R574 300_0402_5%

12

R178 300_0402_5%

12

C132 0.01U_0402_16V7K

GIGA@

12

C130 0.01U_0402_16V7K

12

R53 75_0402_5%

12

1:1

1:1

1:1

1:1

T16

LG-2446S

GIGA@

TCT1

1

TD1+

2

TD1-

3

TCT2

4

TD2+

5

TD2-

6

TCT3

7

TD3+

8

TD3-

9

TCT4

10

TD4+

11

TD4-

12 MX4- 13

MX3- 16

MCT3 18

MX2- 19

MX2+ 20

MCT2 21

MX1- 22

MX1+ 23

MCT1 24

MX4+ 14

MCT4 15

MX3+ 17

JRJ45

FOX_JM36113-P2221-7F

ME@

PR1-

2

PR1+

1

PR2+

3

PR3+

4

PR3-

5

PR2-

6

PR4+

7

PR4-

8

Green LED+

9

Green LED-

10

Amber LED+

11

Amber LED-

12

SHLD4 16

SHLD3 15

SHLD2 14

SHLD1 13

C131 0.01U_0402_16V7K

12

C70

470P_0402_50V7K

@

12

R55 75_0402_5%GIGA@

12

C249

68P_0402_50V8K

@

1

2

R54 75_0402_5%GIGA@

12

C133 0.01U_0402_16V7K

GIGA@

12

C609

68P_0402_50V8K

@

1

2

C128

1000P_1206_2KV7K

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FAN_PW M

SMB_EC_DA2_R

V DD

REMOTE2+

REMOTE2-

REMOTE1-

REMOTE1+

TACH

TRIP_SET

REMOTE2+

REMOTE2-

ALERT#

SMB_EC_CK2_R

SHDN_SEL

TACH_R

FA N_PW M_R

FA N_PW M_R

TACH

FAN_PW M

TACH_R

REMOTE1-

REMOTE1+

REMOTE2-

REMOTE2+

SMB_EC_DA2_R

SMB_EC_CK2_R

ALERT#

V DD

REMOTE2-

REMOTE2+

REMOTE1-

REMOTE1+

REMOTE1+

REMOTE1-REMOTE2+

REMOTE2-

SMB_EC_DA2_R <14,19>

SMB_EC_CK2_R<14,19>

EC_FAN_PW M<34>

EC_TACH<34>

+3VS+3VS +3VS+3VS

+5VS

+3VS+3VS +3VS

+3VS

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

EMC2103/1403_Thermal sensor/FAN

C u sto m

31 51Thursday, October 29, 2009

2008/03/25 2008/04/

Compal Electronics,Ltd.

LA-5752P

TRIP_SET

R439 (1%)

Shutdown

Temp

93

94

95

96

97

98

99

100

101

102

103

104

105

953ohm

1020ohm

1100ohm

1150ohm

1240ohm

1330ohm

1400ohm

1500ohm

1580ohm

1690ohm

1820ohm

1960ohm

2050ohm

SMSC thermal sensor

placed near by VRAM

internal pull up 1.2K to 1.5V

R for initial thermal

shutdown temp

Close to DDR

Under WWAN

FAN_PWM & TACH

for PWM FAN

FAN1 Conn

Address 0101_110xb

REMOTE1,2+/-:

Trace width/space:10/10 mil

Trace length:<8"

Address 1001_101xb

Close U20

1403:

@C508/@C324=100p

E

B

C

Q39

MMST3904-7-F_SOT323-3

2

3 1

C443

0.1U_0402_16V4Z

1

2

C324

1000P_0402_50V7K

@

1

2

R620 0_0402_5%

1 2

R462

10K_0402_5%

2103@

12

U29

EMC1403-2-AIZL-TR_MSOP10

1403@

DN1

3

DP1

2

VDD

1

GND 6

ALERT# 8

DP2

4

DN2

5

THERM# 7

SMDATA 9

SMCLK 10

C651

2200P_0402_50V7K

1

2

R441

10K_0402_5%

2103@

12

U20

EMC2103-2-AP-TR_QFN16_4X4

2103@

DN1

1

VDD

3

GPIO2

5

SYS_SHDN#

7

GPIO1 4

DP1 2

ALERT# 6

SMDATA 8

SMCLK

9

PWM

11

SHDN_SEL

13

TACH 10

GND 12

TRIP_SET 14

DN2 / DP3

15 DP2 / DN3 16

GPAD 17

R622 0_0402_5%

2103@

1 2

C490

10U_0805_10V4Z

1

2

R624

10K_0402_5%

@

12

C449

2200P_0402_50V7K

1403@

1

2

JP12

ACES_85205-04001

ME@

1

1

2

2

3

3

G5

5

G6

6

4

4

R617 0_0402_5%

@

1 2

R460

10K_0402_5%

2103@

12

R430

0_0402_5%

1403@

R461

10K_0402_5%

2103@

12

C508

1000P_0402_50V7K

@

1

2

R623 0_0402_5%

2103@

1 2

R430

68_0402_5%

2103@

12

R618 0_0402_5%

@

1 2

R440

10K_0402_5%

@

12

R439

1.5K_0402_1%

@

1 2

R459

6.8K_0402_5%

2103@

12

R619 0_0402_5%

1 2

E

B

C

Q22

MMST3904-7-F_SOT323-3

2

3 1

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

1 1

2 2

3 3

4 4

SATA_DTX_IRX_P1

SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_DTX_IRX_N0SATA_DTX_C_IRX_N0

SATA_ITX_DRX_N1

SATA_DTX_C_IRX_N1

SATA_DTX_IRX_P0

SATA_ITX_DRX_P1

SATA_DTX_IRX_N1

SATA_ITX_DRX_P0

SATA_DTX_C_IRX_P1

ODD_Power_ON#

SATA_DTX_C_IRX_N1<13>

SATA_ITX_DRX_P1<13>

SATA_ITX_DRX_P0<13>

SATA_DTX_C_IRX_N0<13>

SATA_DTX_C_IRX_P1<13>

SATA_DTX_C_IRX_P0<13>

SATA_ITX_DRX_N1<13>

SATA_ITX_DRX_N0<13>

ODD_Power_ON#<34>

ODD_OFF#<34>

+5VS

+5V_ODD

+3VS

+3VS

+5VS +3VS

+5VS +5V_ODD

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

HDD/ODD Connector

B

32 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

SATA HDD Conn.

SATA ODD Conn.

ODD Power Control

R378

10K_0402_5%

@

12

Q36

DTC124EKAT146_SC59-3

@

IN

2

OUT 1

GND

3

G

D

S

Q37 AO3413_SOT23-3

@

2

13

C122

10U_0805_10V4Z

1

2

C426 0.01U_0402_16V7K

1 2

C423 0.01U_0402_16V7K

@

1 2

C425 0.01U_0402_16V7K

1 2

C125

1000P_0402_50V7K

1

2

R379 0_0402_5%@

1 2

JODD1

OCTEK_SLS-13SB1G_RV

ME@

GND

1

A+

2

A-

3

GND

4

B-

5

B+

6

GND

7

DP

8

+5V

9

+5V

10

MD

11

GND

12

GND

13

GND 17

GND 16

C431

10U_0805_10V4Z

@

1

2

C123

10U_0805_10V4Z

1

2

J6

JUMP_43X79

@

11

2

2

R380

10K_0402_5%@

1 2

C424

0.1U_0402_16V4Z

1

2

C433 0.01U_0402_16V7K

1 2

JH DD1

SUYIN_127043FB022G208ZR_RV

ME@

GND

1

A+

2

A-

3

GND

4

B-

5

B+

6

GND

7

VCC3.3

8

VCC3.3

9

VCC3.3

10

GND

11

GND

12

GND

13

VCC5

14

VCC5

15

VCC5

16

GND

17

RESERVED

18

GND

19

VCC12

20

VCC12

21

VCC12

22

C434 0.01U_0402_16V7K

1 2

C124

1U_0603_10V4Z

1

2

C121

0.1U_0402_16V4Z

@

1

2

C126

0.1U_0402_16V4Z

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PC _ BEEP

HDA_SDO U T_CO D EC

HDA_BIT C LK_C O DEC

HDA_RST _ CODE C#

H D A _ SY N C _C O DE C

PC _ BEEPPC _ BEEP1

SP K_L2+

SP K_R1-

SP K _L1-

SP K_R2+

SP K_R2+

SP K _L1-

SP K_L2+

SP K_R1-

EC _ MUTE#

+VAUX_3.3

GN DA

M IC _ I NL

MIC_ I NR

M IC _ I NL

MIC_ I NR

HDA_BIT C LK_C O DEC

H D A _ SY N C _C O DE C

HDA_RST _ CODE C#

HDA_SDO U T_CO D EC

SP K_L2+_CONN

SP K _L 1- _C O NN

SP K_R2 +_CO N N

SP K_R1 -_CO NN

M IC _ IN R M IC _ I NL

H P_ OU T R _R

H P_ OU T L_R

HDA_RST _ CODE C#<13>

HDA_BIT C LK_C ODEC<13>

H D A _S D IN 1<1 3>

H D A _ SY N C_ C OD E C<1 3>

P C H_ SP KR< 13>

BE EP#<34>

E AP D<34>

HDA_SDO U T_CO D EC<13>

M I C_JD <38 >

PL U G_I N <38>

EC _ MUTE#<34>

HP_ OUTL <38>

HP_ OUTR <38>

EXT_MIC_R <38>

EXT_MIC_L <38>

+3VS

+1.5V

+LD O_OUT_3. 3V

+3VS

+5VS

+5VS

+VAUX_3.3

+MI C BIASC

+MI C BIASC

+3VALW

+3VALW

+3VS

+3VS

+MI C BIASB

+MI C BIASB

Title

Size Doc umen t Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0 . 3

CX20671 Codec

C

33 51Thu rsda y, Oc t ober 29, 2009

2008/03/25 2008/04/

Compal Electronics,Ltd.

LA-5752P

AVDD_3.3 pinis output of

internal LDO. NOT connect

to external supply.

To suuport W ake-on-Jack or W ake-on-Ring, the CODEC

VAUX_3.3 & VDD_IO pins must be powerd by a rail that

is not removed unless AC power is removed.

*DSH page42 has more detail.

Please bypass caps very close to device.

PC Beep

ICH Beep

EC Beep

Internal SPEAKER

Port C

Port A

wide 20MIL

External MIC

Sense resistors must be

connected same power

that is used for VAUX_3.3

CX20671

High Definition Audio Codec SoC

With Integrated Class-D Stereo

Amplifier.

An integrated 5 V to 3.3 V Low-dropout

voltage regulator (LDO).

GND GNDA

EAPD active low

0=power down ex AMP

1=power up ex AMP

10K only needed if s upply to VAUX_3.3

is removed during system re-start.

Headphone

Internal MIC

EMI

An integrated 3.3 V to 1.8V Low-dropout

voltage regulator (LDO).

Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low

resistance (<0.01 ohms)

R30 9

10 K_0402_5%

12

C 37 4 1U _060 3_10V4Z

12

C39 3

0. 1 U_04 02_16V4Z

1

2

R35 5

0_ 0402_5%

1 2

C37 1

10 U _08 05_10V4Z

1

2

C39 4 2.2U _0603_10V7K

1 2

C 37 0

22 P_0402_50V8J

1

2

D 15

RB7 51V _SOD323

@

2 1

R 32 80_ 0402_5%

12

MIC1

WM-64PC Y_2P

45@

1

2

L2 3 0_0603_5%

1 2

C41 1

0. 1 U_04 02_16V4Z

1

2

C40 5

0. 1 U_04 02_16V4Z

1 2

L1 9 0_0603_5%

1 2

L2 0 0_0603_5%

1 2

R34 30_0402_5%

12

R36 2

0_ 0402_5%

1 2

C63 2

1000P_0402_50V7K

1

2

R 33 2

10K_0402_5%

12

C38 1

10 U _08 05_10V4Z

1

2

C 39 2

0. 1 U_04 02_16V4Z

1

2

C35 2

1U _ 060 3_10V4Z

12

C63 4

1000P_0402_50V7K

1

2

R35 0 100 _0402_1%

C41 6

0. 1 U_04 02_16V4Z

1 2

R 33 70_ 0402_5%

@

12

R 33 6 33 _0 402_5%

1 2

R35 4

0_ 0402_5%

1 2

R35 1 2.2K _0402_5%

C 40 4

10 U _08 05_10V4Z

1

2

C 34 5

0. 1 U_04 02_16V4Z@

1

2

C40 8

0. 1 U_04 02_16V4Z

1

2

C35 1

1U _ 060 3_10V4Z

12

C 36 8

1U _ 060 3_10V4Z

12

C 37 6

22 P_0402_50V8J

@

1

2

C 40 6

0. 1 U_04 02_16V4Z

1

2

C40 1 1U_0 603 _10V4Z

1 2

R34 4 5.11 K_0402_1%

1 2

C 37 5

22 P_0402_50V8J

@

1

2

C40 9

0. 1 U_04 02_16V4Z

1

2

C39 5

0. 1 U_04 02_16V4Z

1 2

R32 5

10K_0402_1%

12

R60 15. 1_0 402_5%

1 2

C40 2 2.2U _0603_10V7K

@

1 2

C36 9

1U _ 060 3_10V4Z

1

2

C37 9

0. 1 U_04 02_16V4Z

1

2

C 39 1

0. 1 U_04 02_16V4Z

1

2

J7

SH O RT PADS

1 2

R 60 00 _0402_ 5%

1 2

C41 3

10 U _08 05_10V4Z

1

2

C40 0

0. 1 U_04 02_16V4Z

1

2

R60 25. 1_0 402_5%

1 2

R 33 90_ 0402_5%

12

R34 6 39. 2 K_0402_1%

1 2

C41 0

10 U _08 05_10V4Z

1

2

C41 5 2.2U _0603_10V7K

1 2

R 32 7 20K_ 0402 _5%

1 2

R34 9

4. 7 K_0402_5%

12

R 32 90_ 0402_5%

@

12

C41 2

0. 1 U_04 02_16V4Z

1

2

C41 4

1U _ 060 3_10V4Z

1

2

U 17

CX2 0671-11Z_QFN40_6X6

VDD_IO 7

VAUX_3.3 2

SDATA_OUT

4

BIT_CLK

5

SDATA_IN

6

DVDD_3.3 18

SYNC

8

RESET#

9

PORTA_L 22

PORTA_R 23

AVDD_3.3 27

PORTC_L 30

RPWR_5.0 15

LPWR_5.0 12

FLY_P 19

FLY_N 20

RIGHT-

14 RIGHT+

16

PORTB_L 34

B_BIAS 33

PORTB_R 35

DMIC_CLK

40

AVEE 21

C_BIAS 32

PORTC_R 31

FILT_1.65 29

LEFT-

13

GPIO1/SPK_MUTE#

37

DMIC_1/2

1

AVDD_5V 28

GPIO0/EAPD#

38

LEFT+

11

SENSE_A 36

CLASS-D_REF 17

AVDD_HP 26

FILT_1.8 3

PC_BEEP

10

GND

41

NC 24

NC 25

NC 39

C63 3

1000P_0402_50V7K

1

2

JSPK1

AC E S_8 8231-04001

ME@

1

1

2

2

3

3

4

4

GND1

5

GND2

6

R34 8

0.1_1206_1%

1 2

R31 1

560_0402_5%

1 2

C40 3 2.2U _0603_10V7K

1 2

C63 5

1000P_0402_50V7K

1

2

R 31 0

560_0402_5%

1 2

C 37 8

22 P_0402_50V8J

@

1

2

C 39 0

10 U _08 05_10V4Z

1

2

R 33 5

20K_0402_5%

@

1 2

C 39 9

10 U _08 05_10V4Z

1

2

C38 0

0. 1 U_04 02_16V4Z

1

2

R34 5 10K _0402_1%

1 2

L2 2 0_0603_5%

1 2

R33 80_0402_5%

1 2

R33 13 3_0402_5%

1 2

C40 7

10 U _08 05_10V4Z

1

2

R35 2 2.2K _0402_5%

C37 7

0. 1 U_04 02_16V4Z

1

2

C39 6

0. 1 U_04 02_16V4Z

1 2

R32 6

10K_0402_1%

12

R 33 00_ 0402_5% @

12

R35 6 100 _0402_1%

C

B

E

Q3 0

2S C 2411KT146_SOT23-3

1

2

3

KSO[0..17]

KSI [0..7]

KSO9

SPI_CLK

KSI0

KSO10

KSO2

EC_RST#

CAPS_LED#

KSI2

KSO14

KSO4

KSO3

KSI6

ECAGND

EC_SMB_CK1

KSO8

ACOFF

EC_SCI#

ACIN

BKOFF#

CHARGE_LED0#

KSO1

EC_SMI#

LPC_AD0

CHARGE_LED1#

KSO13

LPC_AD3

BATT_OVP

KSI5

EC_SMB_DA2

KSO7

FW R#SPI_SI

EC_ON

EC_LID_OUT#

TP_CLK

KSO0

LPC_AD1 BATT_TEMP

KSO12

EC_SMB_CK2

IR EF

ECAGND

KSI4

KSI1

KSO6

FRD#SPI_SO

EC_PME#

LID_SW#

LPC_AD2

DAC_BRIG

KSO11

INVT_PWM

SYSON

TP_DATA

KSI3

EC_SMB_DA1

KSI7

KSO15

KSO5

EC_MUTE#

ICH_POK_EC ICH_POK

BEEP#

USB_ON

KB_RST#

SUSP#

PBTN_OUT#

I2C_INT

SUSP#

XCLKO

FSEL#SPICS#

KSO1

KSO2

USB_ON#

TP_DATA

TP_CLK

BATT_OVP

ACIN

BATT_TEMP

EC_SMB_CK2

EC_SMB_DA2

FRD#SPI_SO

FSEL#SPICS#

EC_SMB_DA1

EC_SMB_CK1

ESB_CLK

ESB_DAT

ESB_CLK

ESB_DAT

I2C_INT

ODD_OFF#

RST#

PM_BTN#

KSO16

KSO17

EC_FAN_PWM

PCH_TEMP_ALERT#

ODD_Power_ON#

EC_FAN_PWM

EC_ID

EC_ID

EC_TACH

H_PROCHOT#

XCLKI

EC_TX_P80_DATA

XCLKO

EC_RX_P80_CLK

EC_TACH

XCLKI

CLK_PCI_LPC<16>

KSO[0..17]<35>

KSI[0..7]<35>

EC_SMB_CK1<41>

EC_SMB_DA2<14>

EC_SMB_DA1<41>

EC_SMB_CK2<14>

NUM_LED#<38>

SLP_S3#<15>

SLP_S5#<15>

EC_SMI#<16>

GATEA20<16>

LPC_FRAME#<13,28>

LPC_AD2<13,28>

LPC_AD1<13,28>

LPC_AD3<13,28>

LPC_AD0<13,28>

PCI_RST#<16,28>

EC_SCI#<16>

EC_RX_P80_CLK<28,35>

EC_TX_P80_DATA<28,35>

BATT_OVP <42>

BATT_TEMP <41>

DAC_BRIG <27>

IREF <42>

TP_DATA <35>

TP_CLK <35>

CHARGE_LED1# <36>

CAPS_LED# <38>

CHARGE_LED0# <36>

SYSON <28,39,44>

EC_RSMRST# <15>

EC_ON <38>

ACIN <40>

VR_ON <48>

FSTCHG <42>

ON/OFF#<38>

BKOFF# <27>

INVT_PWM <27>

ACOFF <40,42>

LID_SW#<35>

EC_LID_OUT# <14>

USB_ON# <37>

ENBKL <27>

EC_MUTE# <33>

ADP_I <42>

LAN_WAKE#<29>

PCI_PME#<16>

SERIRQ<13>

WL_OFF# <28>

ICH_POK <15>

SLP_S4# <15>

BEEP# <33>

FRD#SPI_SO <36>

SPI_CLK <36>

FW R#SPI_SI <36>

SUSP# <16,28,39,42,44,46>

PBTN_OUT# <15>

KILL_SW#<35>

EN_WOL# <29>

PWR_LED# <36>

KB_RST#<16>

CHGVADJ <42>

CMOS_OFF# <27>

3G_OFF#<28>

EAPD <33>

FSEL#SPICS# <36>

KSI3<35>

KSI4<35>

BT_OFF# <37>

BATT_SEL_EC <42>

AC_PRESENT <15>

ME_FLASH <13>

I2C_INT <38>

ESB_DAT<38>

ESB_CLK<38>

ODD_OFF# <32>

EC_TACH<31>

DRAMRST_CNTRL_EC <5>

PM_BTN# <38>

RST# <38>

SUS_PWR_DN_ACK <15>

EC_FAN_PWM <31>

PCH_TEMP_ALERT# <16>

H_PROCHOT#<5,48>

NOVO# <38>

ODD_Power_ON# <32>

+3VALW

+EC_AVCC

+3VALW

+3VALW +EC_AVCC

+3VALW

+3VALW

+3VS

+3VALW

+3VS

+3VALW

+5VS

+3VALW

+3VS

+3VALW

+3VS

+3VALW

+3VALW

+3VS

+3VS

+3VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

BIOS & EC I/O Port

Custom

34 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

KB926 SPI STRAP PIN

needed to update to D3 version

SA00001J580

ENE UPDATE 08/10/21

6

FAN control by EC 09.09.08

changed 09.09.08

changed 09.09.08

changed 09.09.08

EC_ID to identify KB926 D or E

C298 100P_0402_50V8J

1 2

C339

0.1U_0402_16V4Z

1

2

R262 100K_0402_1%@

1 2

C341

1000P_0402_50V7K

1

2

R303 0_0402_5%@

1 2

R613

10K_0402_5%

@

12

R614

4.7K_0402_5%

@

1 2

C291

100P_0402_50V8J

@

1

2

C293

0.1U_0402_16V4Z

1

2

C318

1000P_0402_50V7K

@

1

2

R258 0_0402_5%

1 2

L13 FBM-11-160808-601-T_0603

1 2

R265 47K_0402_5%

1 2

C327

1000P_0402_50V7K

1

2

R615

4.7K_0402_5%

@

1 2

R289 10_0402_5%@

12

R271 100K_0402_1%@

1 2

R263 47K_0402_5%

1 2

C340 22P_0402_50V8J@

12

R235 4.7K_0402_5%

1 2

R238 10K_0402_5%

1 2

R227

2.2K_0402_5%

@

C329

0.1U_0402_16V4Z

1

2

R226

2.2K_0402_5%

@

R292

10K_0402_5%

1 2

C319

0.1U_0402_16V4Z

1

2

R251 10K_0402_5%

@

1 2

C321 15P_0402_50V8J

1 2

C292

100P_0402_50V8J

@

1

2

D11 RB751V_SOD323

@

21

C290

0.1U_0402_16V4Z

1

2

R234 4.7K_0402_5%@

1 2

R266 47K_0402_5%

1 2

R607

4.7K_0402_5%

1 2

R236 4.7K_0402_5%

1 2

R294

4.7K_0402_5%

1 2

G

D

S

Q26

2N7002_SOT23

@

2

13

C328 100P_0402_50V8J

1 2

C322 15P_0402_50V8J

1 2

L14

FBM-11-160808-601-T_0603

1 2

C297 100P_0402_50V8J

1 2

C294

1000P_0402_50V7K

1

2

R291

4.7K_0402_5%

1 2

R293 0_0402_5%

1 2

R237 10K_0402_5%

1 2

R611

10K_0402_5%

12

C323

0.1U_0402_16V4Z 1

2

C320

4.7U_0805_10V4Z

1

2

R239

4.7K_0402_5%

1 2

X2

32.768KHZ_12.5PF_1TJS125DJ4A420P

OUT 4

IN 1

NC

3

NC

2

R264

20M_0603_5%

@

12

R240

4.7K_0402_5%

1 2

LPC & MISC

Int. K/B

Matrix

SM Bus

GPIO

GPIO

AD Input

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Fla sh ROM

G PO

GPI

U13

KB926QFA1_LQFP128

GA20/GPIO00

1

KBRST#/GPIO01

2

SERIRQ#

3

LFRAME#

4

LAD3

5

PM_SLP_S3#/GPIO04

6

LAD2

7

LAD1

8

VCC 9

LAD0

10

GND

11

PCICLK

12

PCIRST#/GPIO05

13

PM_SLP_S5#/GPIO07

14

EC_SMI#/GPIO08

15

LID_SW#/GPIO0A

16

SUSP#/GPIO0B

17

PBTN_OUT#/GPIO0C

18

EC_PME#/GPIO0D

19

SCI#/GPIO0E

20

INVT_PWM/PWM1/GPIO0F 21

VCC 22

BEEP#/PWM2/GPIO10 23

GND

24

EC_THERM#/GPIO11

25

FANPWM1/GPIO12 26

ACOFF/FANPWM2/GPIO13 27

FAN_SPEED1/FANFB1/GPIO14

28

FANFB2/GPIO15

29

EC_TX/GPIO16

30

EC_RX/GPIO17

31

ON_OFF/GPIO18

32

VCC 33

PWR_LED#/GPIO19

34

GND

35

NUMLED#/GPIO1A

36

ECRST#

37

CLKRUN#/GPIO1D

38

KSO0/GPIO20

39

KSO1/GPIO21

40

KSO2/GPIO22

41

KSO3/GPIO23

42

KSO4/GPIO24

43

KSO5/GPIO25

44

KSO6/GPIO26

45

KSO7/GPIO27

46

KSO8/GPIO28

47

KSO9/GPIO29

48

KSO10/GPIO2A

49

KSO11/GPIO2B

50

KSO12/GPIO2C

51

KSO13/GPIO2D

52

KSO14/GPIO2E

53

KSO15/GPIO2F

54

KSI0/GPIO30

55

KSI1/GPIO31

56

KSI2/GPIO32

57

KSI3/GPIO33

58

KSI4/GPIO34

59

KSI5/GPIO35

60

KSI6/GPIO36

61

KSI7/GPIO37

62

BATT_TEMP/AD0/GPIO38 63

BATT_OVP/AD1/GPIO39 64

ADP_I/AD2/GPIO3A 65

AD3/GPIO3B 66

AVCC 67

DAC_BRIG/DA0/GPIO3C 68

AGND

69

EN_DFAN1/DA1/GPIO3D 70

IREF/DA2/GPIO3E 71

DA3/GPIO3F 72

CIR_RX/GPIO40 73

CIR_RLC_TX/GPIO41 74

AD4/GPIO42 75

SELIO2#/AD5/GPIO43 76

SCL1/GPIO44

77

SDA1/GPIO45

78

SCL2/GPIO46

79

SDA2/GPIO47

80

KSO16/GPIO48

81

KSO17/GPIO49

82

PSCLK1/GPIO4A 83

PSDAT1/GPIO4B 84

PSCLK2/GPIO4C 85

PSDAT2/GPIO4D 86

TP_CLK/PSCLK3/GPIO4E 87

TP_DATA/PSDAT3/GPIO4F 88

FSTCHG/SELIO#/GPIO50 89

BATT_CHGI_LED#/GPIO52 90

CAPS_LED#/GPIO53 91

BATT_LOW_LED#/GPIO54 92

SUSP_LED#/GPIO55 93

GND

94

SYSON/GPIO56 95

VCC 96

SDICS#/GPXOA00 97

SDICLK/GPXOA01 98

SDIDO/GPXOA02 99

EC_RSMRST#/GPXO03 100

EC_LID_OUT#/GPXO04 101

EC_ON/GPXO05 102

EC_SWI#/GPXO06 103

ICH_PWROK/GPXO06 104

BKOFF#/GPXO08 105

WL_OFF#/GPXO09 106

GPXO10 107

GPXO11 108

SDIDI/GPXID0 109

PM_SLP_S4#/GPXID1 110

VCC 111

ENBKL/GPXID2 112

GND

113

GPXID3 114

GPXID4 115

GPXID5 116

GPXID6 117

GPXID7 118

SPIDI/RD# 119

SPIDO/WR# 120

VR_ON/XCLK32K/GPIO57 121

XCLK1

122

XCLK0

123 V18R 124

VCC 125

SPICLK/GPIO58 126

AC_IN/GPIO59 127

SPICS# 128

R241

10K_0402_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

KSO[0..17]

KSI[0..7]

KSO2

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

TP_CLK

TP_DATA

EC_TX_P80_DATA

EC_RX_P80_CLK

+VCC_LID

KSO12

KSO0

KSI0

KSO1

KSO11

KSO5

KSO7

KSI6

KSO17

KSO16

KSO3

KSI5

KSO14

KSI3

KSO4

KSO15

KSO6

KSI4

KSO13

KSI2

KSO2

KSI7

KSI1

KSO10

KSO8

KSO9

KSO16

KSO17

KSO[0..17] <34>

KSI[0..7] <34>

TP_CLK<34>

TP_DATA<34>

EC_RX_P80_CLK<28,34>

EC_TX_P80_DATA<28,34>

LID _SW # <34>

KILL_SW #<34>

+5VS

+3VALW

+3VALW

+3VALW

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

KB /SW /LPC Debug Conn.

B

35 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

INT_KBD Conn.

To TP/B Conn.

EC DEBUG PORT

CONN PIN define need double check

CONN PIN define need double check

Lid Switch

KILL_SW#

Kill Switch

1,2(LOW)

STATUS

OFF

2,3(HI) ON

Kill

reversal of NIWE1

U18

A3212ELHLT-T_SOT23W-3

GND

1

OUTPUT 3

VDD 2

C151

100P_0402_50V8J

@

1

2

C154 100P_0402_50V8J@

1 2

C185 100P_0402_50V8J@

1 2

C174 100P_0402_50V8J@

1 2

C150

0.1U_0402_16V4Z

JP5

ACES_85201-3005N

ME@

G1 31

G2 32

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

C236 100P_0402_50V8J@

1 2

C175 100P_0402_50V8J@

1 2

R353 100K_0402_5%

1 2

C156 100P_0402_50V8J@

1 2

C204 100P_0402_50V8J@

1 2

C173 100P_0402_50V8J@

1 2

C226 100P_0402_50V8J@

1 2

C398

0.1U_0402_16V4Z

1

2

JP4

E&T_6905-E04N-00R

ME@

1

12

23

34

4

R347 0_0402_5%

1 2

C225 100P_0402_50V8J@

1 2

C227 100P_0402_50V8J@

1 2

JP11

ACES_85205-0400

ME@

1

1

2

2

3

3

4

4

C203 100P_0402_50V8J@

1 2

C228 100P_0402_50V8J@

1 2

C235 100P_0402_50V8J@

1 2

C172 100P_0402_50V8J@

1 2

C636 100P_0402_50V8J@

1 2

C234 100P_0402_50V8J@

1 2

C233 100P_0402_50V8J@

1 2

C155 100P_0402_50V8J@

1 2

R295

100K_0402_5%

12

C637 100P_0402_50V8J@

1 2

C241 100P_0402_50V8J@

1 2

C205 100P_0402_50V8J@

1 2

C187 100P_0402_50V8J@

1 2

SW 2

LSSM12-P-V-T-R_3P

1

1

2

2

3

3

C397

10P_0402_50V8J

1

2

C152

100P_0402_50V8J

@

1

2

C186 100P_0402_50V8J@

1 2

C206 100P_0402_50V8J@

1 2

C153 100P_0402_50V8J@

1 2

FW R#SPI_SI

SPI_CLKSPI_CLK_R

HOLD#FRD#SPI_SO SPI_SO

SPI_CLK_R

FSEL#SPICS#

SPI_SI_EC FWR#SPI_SI <34>

SPI_CLK <34>

FRD#SPI_SO<34>

FSEL#SPICS#<34>

HDD_LED#<13>

BT_LED#<37>

WLAN_LED#<28>

PWR_LED#<34>

CHARGE_LED1#<34>

CHARGE_LED0#<34>

+3VALW

+5VS

+5VS

+5VALW

+3VALW

+5VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

LED/EC SPI ROM

B

36 51Thursday, October 29, 2009

2007/10/15 2008/10/15

Compal Electronics, Inc.

LA-5752P

LED

20mils

EMI 3G

A:H_2P8

C:H_3P8

D:H_3P8 X2

G:H_3P2 X2

I:H_3P0 X1

J:H_2P8 X1

H_4P5X3P0N H_6P0N

White

White

Amber

BATT_LOW_LED#

BATT_CHG_LED#

White

White

H_3P0X4P0N

Colse to EC

Changed to BEAD for EMI.

Close to EC after C1059.

G:H_3P2 X2

FOR EC 256KB SPI ROM

(150mil PACKAGE)

P/N : SA00003GK00

SC500006M00

SC500005B00

SC500005B00

SC500005B00

R361300_0402_5%

12

H2

HOLEA

1

LED3

19-213A-T1D-CP2Q2HY-3T_WHITE

21

R216

0_0402_5%

@

12

H14

HOLEA

1

H7

HOLEA

1

C265

0.1U_0402_16V4Z

1

2

LED4

19-213A-T1D-CP2Q2HY-3T_WHITE

21

H16

HOLEA

1

D16

RB751V_SOD323

21

H18

HOLEA

1

C266

10P_0402_50V8J

1

2

H27

HOLEA

1

H6

HOLEA

1

H11

HOLEA

1

O

W

LED2

18-225A-S2T3D-C01-3T_ORG-WHITE

21

43

R360300_0402_5%

12

H17

HOLEA

1

H10

HOLEA

1

H19

HOLEA

1

H3

HOLEA

1

C264

12P_0402_50V8J

@

1

2

H12

HOLEA

1

R359300_0402_5%

12

FD4

1

H15

HOLEA

1

FD1

1

R201

15_0402_5%

1 2

FD2

1

H5

HOLEA

1

R218 15_0402_5%

1 2

H20

HOLEA

1

D17

RB751V_SOD323

21

H23

HOLEA

1

H13

HOLEA

1

FD3

1

H22

HOLEA

1

R217

10K_0402_5%

12

H9

HOLEA

1

R358300_0402_5%

12

H21

HOLEA

1

R357300_0402_5%

12

H1

HOLEA

1

R215 FBMA-10-100505-101T 0402

1 2

H4

HOLEA

1

U9

MX25L2005CMI-12G SOP

VCC 8

HOLD# 7

CLK 6

DIO 5

GND

4WP#

3DO

2CS#

1

H8

HOLEA

1

H24

HOLEA

1

LED1

19-213A-T1D-CP2Q2HY-3T_WHITE

21

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

BTON_LED

+USB_VCCA

SATA_DTX_IRX_P4

SATA_DTX_IRX_N4SATA_DTX_C_IRX_N4

SATA_DTX_C_IRX_P4

USB20_N1

USB20_P1

+USB_VCCB

SATA_ITX_DRX_N4_CONN

SATA_ITX_DRX_P4_CONN

USB_ON#

USB_ON#

USB20_N3

USB20_P3

USB20_P0

USB20_N0

USB20_N1

USB20_P1

USB20_P11

USB20_N11

BT_ACTIVE

BT_LED#<36>

BT_OFF#<34>

USB20_N1<16>

USB20_P1<16>

SATA_DTX_C_IRX_P4<13>

SATA_DTX_C_IRX_N4<13>

SATA_ITX_DRX_P4_CONN<13>

SATA_ITX_DRX_N4_CONN<13>

USB_ON#<34>

USB_ON#<34> USB_OC#0 <16>

USB_OC#1 <16>

USB20_P0<16>

USB20_N0<16>

USB20_N3<16>

USB20_P3<16>

USB20_P11<16>

USB20_N11<16>

BT_ACTIVE<28>

+3VS

+5VALW

+3VS_BT

+USB_VCCA

+USB_VCCB

+USB_VCCB

+5VALW

+USB_VCCA

+USB_VCCB

+5VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.3

USB ports/BT/E-SATA

Custom

37 51Thursday, October 29, 2009

2006/08/18 2007/8/18

Compal Electronics, Inc.

LA-5752P

BT MODULE CONN

30mils

W=80mils

W=80mils

Left USB Conn.

Right USB Conn.

ESATA and USB Conn.

W=80mils

A+ = RXP

A- = RXN

B+ = TXP

B- = TXN

RIGHT USB PORT X1

E-SATA COMBO

LEFT USB PORT

USB

Low Active

Low Active

Q31

DTC124EKAT146_SC59-3

BT@

IN

2

OUT 1

GND

3

C421 0.1U_0402_16V4Z

12

U27

APL3510BKI_SO8

GND

1

IN

2

OC# 5

OUT 6

OUT 8

IN

3

EN

4

OUT 7

R304

100K_0402_5%

BT@

12

+

C430

150U_B2_6.3VM_R35M

1

2

D10

PJDLC05_SOT23-3

@

2

3

1

R616

100K_0402_5%

BT@

1 2

USB

ESATA

JESAT1

TYCO_1759576-1

ME@

VBUS

1

D-

2

D+

3

GND

4

GND

5

A+

6

A-

7

GND

8

B-

9

B+

10

GND

11

GND

12

GND

13

GND

14

GND

15

C622

470P_0402_50V7K

1

2

G

D

S

Q32 AO3413_SOT23-3

BT@

2

13

C432

470P_0402_50V7K

1

2

JUSB2

SUYIN_020173MR004S558ZL

ME@

1

1

2

2

3

3

4

4

GND

5

GND

6

GND

7

GND

8

C610

1000P_0402_50V7K@

1

2

JUSB1

ACES_85205-04001

ME@

1

1

2

2

3

3

G5

5

G6

6

4

4

C353 0.1U_0402_16V4Z

BT@

1 2

+

C615

150U_B2_6.3VM_R35M

1

2

U19

APL3510BKI_SO8

GND

1

IN

2

OC# 5

OUT 6

OUT 8

IN

3

EN

4

OUT 7

C621 0.1U_0402_16V4Z

12

C237

470P_0402_50V7K

1

2

C354

0.1U_0402_16V4Z

BT@

1

2

JP7

ACES_87213-0600G

ME@

1

1

2

2

3

3

4

4

5

5

6

6G1 7

G2 8

D7

PJDLC05_SOT23-3

@

2

3

1

Q29

DTC124EKAT146_SC59-3

BT@

IN 2

OUT 1

GND

3

C623

0.01U_0402_16V7K ESATA@

12

C6240.01U_0402_16V7K

ESATA@

12

C429

1000P_0402_50V7K

@

1

2

ON/O FF#

51_ON#

EC_ON

NOVO_BTN# ON /OFFBTN#

51_ON#

NOVO_BTN#

NOVO#

ON/OFFBTN#

PM_BTN#

I2C_ INT_R

NOVO_BTN#

ON/OFFBTN#

PM_BTN#

PM_BTN#

MIC_ JD

PLUG_IN

USB20_P5

EXT_MIC_L

HP_OUTR

USB20_N5

EXT_MIC_R

HP_OUTL

EC_ON<34>

ON/O FF# <34>

51_ON# <40>

51_ON#<40>

NOVO#<34>

I2C_INT<34>

ESB_DAT<34>

ESB_CLK<34>

CAPS_LED#<34>

PM_BTN#<34>

NUM_LED#<34>

RST#<34>

MIC_JD<33>

PLUG_IN<33>

USB20_P5<16>

EXT_MIC_L<33>

HP_OUTR<33>

USB20_N5<16>

EXT_MIC_R<33>

HP_OUTL<33>

+3VALW

+3VALW

+5VS

+3VS

+5VS

+3VS

+3VALW

Title

Size D o c u m ent Number R ev

D at e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

Audio Jack & SW connector

C u sto m

38 51Thursday, October 29, 2009

2008/03/25 2008/04/

Compal Electronics,Ltd.

LA-5752P

TOP Side

Bottom Side

ON/OFF switch

Power Button

Cap Sensor Board Conn. 6pin

EMI REQUEST 1ST = SCA00000E00

2ST = SCA00000R00

Card Reader/Audio Jack SB CONN

ENE SB3534

Power Bottom Board Conn. 8pin

R1 0_0402_5%

1 2

D20

PJSOT24C 3P C/A SOT-23

@

2

3

1

D19

PJSOT24C 3P C/A SOT-23

@

2

3

1

R272

100K_0402_5%

1 2

C1

33P_0402_50V8J

@

1

2

R296

100K_0402_5%

1 2

R603

100K_0402_1%

12

R2 0_0402_5%

1 2

JP3

ACES_85201-08051

ME@

GND

9

GND

10

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D13

DAN202UT106_SC70-3

2

3

1

R3 0_0402_5%

1 2

JP8

ACES_85201-1205N

ME@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12 GND 13

GND 14

SW 1

SMT1-05_4P

@

3

2

1

4

5

6

G

D

S

Q28

2N7002_SOT23-3

2

13

J5

SHORT PADS

1 2

D14

DAN202UT106_SC70-3

2

3

1

JP1

ACES_85201-08051

ME@

GND

9GND

10

1

12

23

34

45

56

67

78

8

R302

10K_0402_5%

1 2

C2

33P_0402_50V8J

@

1

2

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SUSP

SUSP

SUSP

SUSPSUSP

SYSON# SUSP SUSPSUSP

SUSP

1.5VS_GATE5VS_GATE

SUSP

SUSP

SYSON#

SYSON

5VS_GATE_R

SUSP<8,44,45>

SUSP#<16,28,34,42,44,46> SYSON<28,34,44>

+5VALW +3VALW

+1.5V

+3VS

+1.5VS

B+

+5VS

+1.5V +VCCP+1.8VS +0.75VS

B+

+1.05VS

+5VALWRTCVREF

+5VALW

B+

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.3

DC Interface

Custom

39 51Thursday, October 29, 2009

2006/08/18 2007/8/18

Compal Electronics, Inc.

LA-5752P

+3VALW TO +3VS+5VALW TO +5VS +1.5V to +1.5VS

For Intel S3 Power Reduction.

C278

0.1U_0603_25V7K

1

2

C363

1U_0603_10V4Z

1

2

U10

SI4800BDY-T1-E3_SO8

S1

S2

S3

G4

D

8

D

7

D

6

D

5

R143

470_0603_5%

@

12

U4

SI4800BDY-T1-E3_SO8

S1

S2

S3

G4

D

8

D

7

D

6

D

5

G

D

S

Q20

2N7002_SOT23

2

13

G

D

S

Q40

2N7002_SOT23

2

13

C389

10U_0805_10V4Z

1

2

R5

100K_0402_5%

@

12

R142

470_0603_5%

@

12

R6

100K_0402_5%

@

12

R89

47K_0402_5%

12

R229

20K_0402_5%

R202

470_0603_5%

@

12

Q1

DTC124EKAT146_SC59-3

IN

2

OUT 1

GND

3

C127

10U_0805_10V4Z

1

2

G

D

S

Q9

2N7002_SOT23

2

13

C144

0.1U_0603_25V7K

1

2

R174

470_0603_5%

@

12

R314

470_0603_5%

@

12

R4

100K_0402_5%

12

G

D

S

Q35

2N7002_SOT23

@

2

13

R312

100K_0402_5%

12

R313

0_0402_5%

@

1 2

G

D

S

Q34

2N7002_SOT23

@

2

13

R87

470_0603_5%

@

12

G

D

S

Q33

2N7002_SOT23

2

13

U16

SI4800BDY-T1-E3_SO8

S1

S2

S3

G4

D

8

D

7

D

6

D

5

G

D

S

Q6

2N7002_SOT23

@

2

13

G

D

S

Q16

2N7002_SOT23

@

2

13

R568

22_0603_5%

12

C362

10U_0805_10V4Z

1

2

C373

0.1U_0603_25V7K

DIS@

1

2

C135

1U_0603_10V4Z

1

2

R342

470_0603_5%

@

12

C279

10U_0805_10V4Z

1

2

Q2

DTC124EKAT146_SC59-3

@

IN

2

OUT 1

GND

3

C134

10U_0805_10V4Z

1

2

C276

1U_0603_10V4Z

1

2

G

D

S

Q11

2N7002_SOT23

@

2

13

C277

10U_0805_10V4Z

1

2

C361

0.1U_0603_25V7K

1

2

G

D

S

Q15

2N7002_SOT23

@

2

13

R228

10K_0402_5%

12

R88

0_0402_5%

@

1 2

G

D

S

Q10

2N7002_SOT23

@

2

13

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

51ON-3

51ON-1

51ON-2

CHGR TC INRTCVREF-1

CHGRTCP

VINDE-1

VINDE-2

PAC IN

VINDE-3

APD IN APDI N1

PRG++

51_ON#<38>

A C IN <34>

PAC IN <42>

ACO FF<34,42>

ACON<42>

MAINPWON<41,43>

PACIN <42>

VIN

VS

BATT+

RTCVREF

+CHGRTC

VIN

V IN

RTCVREF

V IN

VS

+RTCBATT

+CHGRTC

B+

RTCVREF

VL

VS

+5VALW

VIN

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1

DCIN & DETECTOR

Cus t om

40 51Thursday, October 29, 2009

2009/01/06 2010/01/06

Compal Electronics, Inc.

3.3V

3.3V

- +

RTC Battery

DC030006J00

BATT ONLY

L-->H 7.196V 7.349V 7.505V

Precharge detector

Min. typ. Max.

H-->L 6.138V 6.214V 6.056V

Precharge detector

Min. typ. Max.

H-->L 13.860V 14.247V 14.621V

L-->H 14.991V 15.381V 15.782V

ACIN

L-->H 17.430V 17.901V 18.384V

Vin Detector

Min. typ. Max.

H-->L 16.976V 17.262V 17.728V

PC13

0.1U_0402_16V7K

12

PC98

0.1U_0603_25V7K

12

PR39

100K_0402_1%

12

PR141

68_1206_5%

12

PD13

RLS4148_LL34-2

12

PC8

0.1U_0603_25V7K

12

PC97

0.01U_0402_25V7K

12

PU8

G920AT24U_SOT89-3

IN 2

GND

1

OUT

3

PR136

47K_0402_5%

12

PC6

100P_0402_50V8J

12

PR18

10K_0402_1%

1 2

PQ12

DTC115EUA_SC70-3

2

13

PR123

200_0603_5%

12

PR17

10K_0402_5%

12

PQ11

DTC115EUA_SC70-3

2

13

PQ4

TP0610K-T1-E3_SOT23-3

2

13

PC12

0.01U_0402_25V7K

12

PD10

RB715F_SOT323-3

2

3

1

PR19

10K_0402_5%

12

LLZ4V3B_LL34-2

PD9

2 1

PQ26

TP0610K-T1-E3_SOT23-3

2

13

PC5

1000P_0402_50V7K

12

J D C IN

4602-Q04C-09R 4P P2.5

@

11

33

44

22

PQ25

DTC115EUA_SC70-3

2

13

PR22

499K_0402_1%

12

PR26

1M_0402_1%

1 2

PD12

LL4148_LL34-2

12

PD2

LL4148_LL34-2

1 2

PR27

22K_0402_1%

1 2

PC11

1000P_0402_50V7K

12

PR142

1K_1206_5%

1 2

PC14

1000P_0603_50V7K

12

G

D

S

PQ3

SSM3K7002F_SC59-3

2

13

PF1

7A_24VDC_429007.WRML

21

PC91

10U_0603_6.3V6M

12

PR25

2.2M_0402_5%

12

PR122

200_0603_5%

1 2

PC7

0.1U_0603_25V7K

12

PU10B

LM393DG_SO8

+5

-6

O

7

P8

G

4

PR21

10K_0805_5%

12

PR20

10K_0402_5%

12

PR134

84.5K_0402_1%

12

PR124

560_0603_5%

1 2

PC16

0.1U_0603_25V7K

12

JRTC

MAXEL_ML1220T10@

12

PD8

RB751V-40_SOD323-2

1 2

PR31

1K_1206_5%

1 2

PR23

205K_0402_1%

12

PC90

1U_0805_25V6K

12

PR140

68_1206_5%

12

PR125

560_0603_5%

1 2

PC9

1000P_0402_50V7K

12

PR16

22K_0402_1%

1 2

PR38

1K_1206_5%

1 2

PR138

100K_0402_1%

12

PR15

100K_0402_1%

12

PL2

SMB3025500YA_2P

1 2

PC4

0.22U_0603_25V7K

1 2

PR143

100K_0402_1%

12

PR24

499K_0402_1%

12

PC99

0.01U_0402_25V7K

12

PR135

20K_0402_1%

12

PC10

100P_0402_50V8J

12

PR137

100K_0402_1%

12

PU10A

LM393DG_SO8

+

3

-

2O1

P8

G

4

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

TM-3

TM-1

TM_REF1

TM-2

EC_SMDA

EC_SMCA

MA INPW ON < 40,43>

BATT_TEMP <34>

EC_SMB_DA1 <34>

EC_SMB_CK1 <34>

BATT+

VMB

VL

VL

VL

+3VALW

VMB2

VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1

BATTERY CONN / OTP

41 51Thursday, October 29, 2009

Compal Electronics, Inc.

2010/01/062009/01/06

Recovery at 56 degree C

CPU thermal protection at 92 degree C

PH1 under CPU botten side :

A/D

PR87

13.7K_0402_1%

1 2

PR83

47K_0402_1%

1 2

PU4A

LM393DG_SO8

+

3

-

2O1

P8

G

4

G

D

S

PQ20

SSM3K7002FU_SC70-3

2

13

PR86

100K_0402_1%

12

PL3

SMB3025500YA_2P

1 2

PC62

0.01U_0402_25V7K

12

PR3

100_0402_1%

12

PC63

0.22U_0603_25V7K

12

PH1

100K_0402_1%_TSM0B104F4251RZ

12

PC110

1000P_0402_50V7K

12

JBATT

TYCO_1775789-1

@

11

33

44

55

66

GND 8

GND 9

22

77

PR88

15.4K_0402_1%

12

PR85

100K_0402_1%

12

PC109

0.01U_0402_25V7K

12

PR5

10K_0402_5%

1 2

PU4B

LM393DG_SO8

+

5

-

6O7

P8

G

4

PR4

100_0402_1%

12

PF2

12A_65V_451012MRL

21

PR6

6.49K_0402_1%

1 2

PR84

47K_0402_1%

1 2

PC64

1000P_0402_50V7K

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

C HGC HG

ACO FF

6251_EN CSON

ACO FF

6251_VDD

6251_VDD

6251_VREF

CSOP

6251_VREF

6251_DCIN

PAC IN

BST_CHG

PAC IN

CSIP

DL_ CHG

C S IN

LX_CHG

6251_VDDP

BST_CHGA

CELLS

SUSP#

FSTCHG

DH_CHG

6251_DCIN

CELLS

IREF<34>

FSTCHG<34>

ADP _I<34>

PAC IN<40>

ACO FF<34,40>

BATT_OVP<34>

SUSP# <16,28,34,39,44,46>

FSTCHG <34>

ACON<40>

CHGVADJ<34>

BATT_SEL_EC<34>

VIN

P2

P3

VS

VIN

BATT+

B+

CHG_B+

V IN

VMB2

VS

P3

6251_VDD 6251_VDD

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1

42 51Thursday, October 29, 2009

Compal Electronics, Inc.

2008/6/222007/6/22

CHARGER

LI-3S :13.5V----BATT-OVP=1.5012V

BATT-OVP=0.1112*VMB

Per cell=3.5V

Connect to EC A/D Pin.

Vcell

CHGVADJ=(Vcell-4)/0.10627

4V

4.2V

CHGVADJ

4.35V

0V

1.882V

3.2935V

CC=0.25A~3A

IREF=0.254V~3.048V

IREF=1.016*Icharge

VCHLIM need over 95mV

DIS CP mode

Vaclim=2.39*{(31.6K//514K)/((31.6K//514K)+(21K//514K))}=1.425V

Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)

where Vaclim=1.425V, Iinput=4A

UMA CP mode

Vaclim=2.39*{(2.26K//514K)/((2.26K//514K)+(21K//514K))}=0.239V

Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)

where Vaclim=0.239V, Iinput=2.75A

PC122

4.7U_0805_6.3V6K

12

PC114

4.7U_1206_25V6K

1 2

PQ29

SIS412DN-T1-GE3 _PAK1212-8

3 5

2

4

1

PR168

100K_0402_1%@

1 2

PR29

150K_0402_1%

12

PR173

154K_0402_1%

12

PR13

100K_0402_1%

12

PC106

10U_1206_25V6M

12

PD14

RB751V-40TE17_SOD323-2

12

PR172

21K_0402_1%

1 2

PC1

0.1U_0402_16V7K

1 2

PC123

0.1U_0402_16V7K

1 2

PC2

0.01U_0402_25V7K

12

PC131 6800P_0402_25V7K

1 2

PR161

20_0402_5%

1 2

PR178

100K_0402_1%@

1 2

PC15

470P_0603_50V8J

12

PR7

10K_0402_1%

12

PR176

0_0402_5%

12

PC130

100P_0402_50V8J@

1 2

PQ38

DTC115EUA_SC70-3

2

13

PR30

200K_0402_1%

12

PR158

2.2_0402_5%

1 2

PD15

RB751V-40TE17_SOD323-2

1 2

PC101

0.01U_0402_25V7K@

12

PD1

RB715F_SOT323-3

2

3

1

G

D

S

PQ8

2N7002KW _SOT323-3

2

13

PR163

4.7_0402_5%

1 2

PR139

10K_0402_1%@

1 2

PQ1A

2N700 2KDW -2N_SOT363-6@

61

2

PQ28

DTC115EUA_SC70-3

2

13

PC111

2200P_0402_50V7K

1 2

PC125

0.1U_0603_25V7K

12

PR171

15.4K_0402_1%

1 2

PQ32

DTC115EUA_SC70-3

2

13

PJ11

JUMP_43X118@

11

2

2

PL5

10U_LF919AS-100M-P3_4.5A_20%

1 2

PR9

340K_0402_1%@

12

PR37

3K_0402_1%

1 2

PQ1B

2N700 2KDW -2N_SOT363-6@

34

5

PR174

100_0402_1%

1 2

PC132

0.1U_0402_16V7K

1 2

PR157

2.2_0402_5%

1 2

PR175 6.81K_0402_1%

1 2

PR155

10K_0402_1%

1 2

PR145

47K_0402_5%

12

PR14

10_0603_5%

1 2

PU1B

LM358DT_SO8@

+5

-6

0

7

P8

G

4

PC121

0.1U_0603_25V7K

12

PC103

10U_1206_25V6M

12

PC107

0.1U_0603_25V7K

12

PC124

0.047U_0402_16V7K

12

G

D

S

PQ5

2N7002KW _SOT323-3

2

13

PR12

100K_0402_1%

12

PR167

100K_0402_1%

12

PC112

4.7U_1206_25V6K

1 2

PQ27

FDS6675BZ_SO8

36

5

7

8

2

4

1

PR2

31.6K_0402_1%

12

PR10

499K_0402_1%@

12

PC100

0.01U_0402_25V7K@

12

PR28

47K_0402_1%

1 2

PR177

0_0402_5%@

12

PC113

4.7U_1206_25V6K

1 2

PQ10

DTC115EUA_SC70-3

2

13

PC128

2.2U_0603_6.3V6K

12

PQ2 TP0610K-T1-E3_SOT23-3

2

13

PR160

20_0402_5%

1 2

PR151

0.02_1206_1%

1

3

4

2

PQ31

SI7716ADN-T1-GE3 _PAK1212-8

3 5

2

4

1

PQ34

FDS6675BZ_SO8

3 6

5

7

8

2

4

1

PR11

105K_0402_1%@

12

PR154

4.7_1206_5%

12

PQ7

DTA144EUA_SC70-3

2

1 3

PC120

0.1U_0603_25V7K

12

PC3

0.01U_0402_25V7K

1 2

PR159

20_0402_5%

12

G

D

S

PQ9

2N7002KW _SOT323-3

2

13

PD3

RB715F_SOT323-3

2

3

1

PU11

ISL6251AHAZ-T_QSOP24

EN

3

CELLS

4

VDD

1

ACSET

2

ICOMP

5

VCOMP

6

CHLIM

9

ACPRN 23

CSIP 19

UGATE 17

PHASE 18

BOOT 16

PGND 13

GND

12

ICM

7

VREF

8

VADJ

11

DCIN 24

CSIN 20

ACLIM

10

LGATE 14

VDDP 15

CSOP 21

CSON 22

PR162

200K_0402_1%

1 2

PU1A

LM358DT_SO8@

+3

-2

0

1

P8

G

4

PR152

0.02_1206_1%

1

3

4

2

PC105

10U_1206_25V6M

12

PR8

100K_0402_1%

12

PC118

680P_0603_50V7K

12

PR1

31.6K_0402_1%

12

PQ6

FDS6675BZ_SO8

3 6

5

7

8

2

4

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

2VREF_ISL6237

HG5

ILIM2

BST3A

UG3

EN_LDO

BST5A

SW 5

LG5

BST5A-1

SW 3

FB5

3/5V_VIN

ILM1

FB3

3/5V_VCC

3/5V_EN2

BST3A-1

3/5V_EN1

2VREF_ISL6237

LG3

5V_SKIP

3/5V_TON

EN_LDO-1

3/5V_NC

3V_SNB

5V_SNB

2VREF_ISL6237

MA INPW ON <40,41>

VL

VL

ISL6237_B+

VS

+3VALWP

+5VALWP

B+

VL

2VREF_ISL6237

ISL6237_B+

VL

+3VALWP +3VALW

+5VALWP +5VALW

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1Cus t om

43 51

Thursday, October 29, 2009

2009/01/06 2010/01/06

Compal Electronics, Inc.

3VALW/5VALW

PR43

0_0402_5%

12

PR32

0_0402_5%

12

PR150

0_0402_5%@

12

PQ33

SI7716ADN-T1-GE3_PAK1212-8

3 5

2

4

1

PJ4

JUMP_43X118@

11

2

2

PR33

47K_0402_1%@

1 2

PC42

0.22U_0603_25V7K

1 2

PC25

10U_1206_25V6M

12

PR36

61.9K_0402_1%@

1 2

PC119

680P_0402_50V7K

12

PR146

806K_0603_1%

1 2

PR153

4.7_1206_5%

12

PC40

1U_0603_10V6K

1 2

PR147

301K_0402_1%

12

PJ12

JUMP_43X118@

11

2

2

PL6

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PC104

0.047U_0402_16V7K

12

PR149

0_0402_5%

1 2

+

PC117

150U_B2_6.3VM_R45M

1

2

PR51

0_0402_5%@

12

PC22

0.1U_0603_25V7K

1 2

PQ13

SIS412DN-T1-GE3_PAK1212-8

3 5

2

4

1

PD4

RB751V-40_SOD323-2

1 2

PQ30

SI7716ADN-T1-GE3_PAK1212-8

3 5

2

4

1

PC102

0.22U_0603_25V7K

1 2

PQ14

SIS412DN-T1-GE3_PAK1212-8

3 5

2

4

1

PR42

2.2_0603_5%

12

PU2

ISL6237IRZ-T_QFN32_5X5

UGATE2

26

BOOT2

24

PHASE2

25

LGATE2

23

OUT2

30

REFIN2

32

TON

2

LDOREFIN

8

NC

20

EN_LDO

4

EN2

27

EN1

14

POK1 13

POK2 28

PVCC 19

VCC 3

SKIP 29

LDO 7

ILIM2 31

BYP 9

OUT1 10

GND

21

PGND 22

LGATE1 18

PHASE1 16

BOOT1 17

UGATE1 15

VIN 6

NC

5

REF

1

FB1 11

ILIM1 12

TP

33

PR144

200K_0402_1%

1 2

PC36

2200P_0402_50V7K

12

PC38

0.1U_0402_25V6

12

PC43

0.1U_0603_25V7K

1 2

PJ10

JUMP_43X118@

11

2

2

PR50

0_0402_5%

1 2

PR34

301K_0402_1%

12

PC23

4.7U_0805_6.3V6K

12

PR148

10K_0402_1%

@

1 2

PR41

0_0402_5%

1 2

+

PC116

150U_B2_6.3VM_R45M

1

2

PC37

0.1U_0402_25V6

12

PC27

0.1U_0603_25V7K

1 2

PC41

1U_0603_10V6K

1 2

PR156

4.7_1206_5%

12

PC115

680P_0402_50V7K

12

PR44

100K_0402_1%

1 2

PL4

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

PD11

RB751V-40_SOD323-2

1 2

PC39

2200P_0402_50V7K

12

PR52

0_0402_5%

1 2

PC108

0.047U_0402_16V7K

@

12

PC21

330P_0402_50V7K

12

LLZ5V1B_LL34-2

PD5

21

PR35

0_0402_5%

1 2

PC28

1U_0603_10V6K

12

PC26

10U_1206_25V6M

12

PR40

2.2_0603_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

0.75V_IN

0.75V_REF

0.75V_EN

BST_1.5V BST_1.5V-1

LG_1.5V

1.5V_FB

1.5V_TON

1.5V_TRIP

1.5V_V5FILT

UG_1.5V

1.5V_EN

SW _1.5V

1.5V_SNB

BST_VCCP BST_VCCP-1

LG_VCCP

VCC P_FB

VCCP_TON

SW _VCCP

VCCP_V5FILT

UG_VCCP

VCC P_EN

VCCP_TRIP

VCCP_SNB

VCC P_ IN

1.5 V_IN

SYS ON<28,34,39>

SUSP#<16,28,34,39,42,46>

1.5V_PGOOD

SUSP<8,39,45>

1.05V_PGOOD <46>

S3_0.75V_EN<5>

+1.5V

+3VALW

+0.75VSP

+0.75VS+0.75VSP

+1.5VP +1.5V

+1.05VSP +1.05VS

+5VALW

+1.5VP

B+

+5VALW

+5VALW

+1.05VSP

B+

+5VALW

+3VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1

1.5V/VCCP/0.75V

44 51Thursday, October 29, 2009

Compal Electronics, Inc.

2010/01/062009/01/06

PR190

0_0402_5%

1 2

G

D

S

PQ46

SSM3K7002FU_SC70-3

2

13

PC151

1U_0402_6.3V6K

12

PC141

2200P_0402_50V7K

@

12

PC183

4.7U_0805_6.3V6K

12

PC181

47P_0402_50V8J@

1 2

PU9

TPS51117RGYR_QFN14_3.5x3.5

@

VOUT

3

V5FILT

4

EN_PSV 1

TON

2

VFB

5

PGOOD

6DRVL 9

DRVH 13

LL 12

GND

7

PGND

8

TRIP 11

V5DRV 10

VBST 14

TP 15

PR241

4.7_1206_5%

12

PU13

G2992F1U_SO8

VOUT

4

NC 5

GND

2

VREF

3

VIN

1VCNTL 6

NC 7

NC 8

TP 9

PC178

4.7U_0603_6.3V6K

12

PC94

47P_0402_50V8J@

1 2

PC176

0.1U_0402_16V7K

12

PR181

4.7_1206_5%

@

12

PR133

240K_0402_1%

@

1 2

PQ40

SI7716ADN-T1-GE3_PAK1212-8

@

3 5

2

4

1

PR127

100_0603_1%

@

1 2

+

PC136

220U_B2_2.5VM_R15M

@

1

2

PC135

680P_0402_50V7K

@

12

PR126

100K_0402_1%

@

1 2

PC137

10U_0603_6.3V6M

@

12

PR129

13.7K_0402_1%

@

1 2

PL9

2.2UH_PCMC063T-2R2MN_8A_20%

@

1 2

PC147

0.1U_0402_16V7K@

12

PC96

0.22U_0402_6.3V6K

@

12

PC146

4.7U_0805_6.3V6K

12

PC175

10U_1206_25V6M

12

PR245

7.15K_0402_1%

1 2

PR242

100_0603_1%

1 2

PC179

0.1U_0402_16V7K

@

12

PR239

1K_0402_1%

12

PC173

0.1U_0402_25V6

12

PC182

0.1U_0603_25V7K

1 2

PJ21

JUMP_43X118@

11

2

2

PC140

10U_1206_25V6M

@

12

PJ20

JUMP_43X79@

11

2

2

PJ14

JUMP_43X118@

11

2

2

PR131

2.2_0603_5%

@

1 2

PC180

680P_0402_50V7K

12

PC95

0.1U_0603_25V7K

@

1 2

PC184

0.1U_0402_16V7K

@

12

PL13

1UH_PCMB103E-1R0MS_20A_20%

1 2

PR132

100K_0402_1%

@

1 2

PQ41

SIS412DN-T1-GE3_PAK1212-8

@

3 5

2

4

1

PR240

1K_0402_1%

12

PR130

31.6K_0402_1%

@

12

PR247

240K_0402_1%

1 2

PQ48

SI4686DY-T1-E3_SO8

3 6

5

7

8

2

4

1

PC92

4.7U_0805_6.3V6K

@

12

PU14

TPS51117RGYR_QFN14_3.5x3.5

VOUT

3

V5FILT

4

EN_PSV 1

TON

2

VFB

5

PGOOD

6DRVL 9

DRVH 13

LL 12

GND

7

PGND

8

TRIP 11

V5DRV 10

VBST 14

TP 15

PR248

0_0402_5%

1 2

PC169

10U_1206_25V6M

12

PR249

2.2_0603_5%

1 2

PR250

0_0402_5%

@

1 2

PJ16

JUMP_43X79@

11

2

2

PC93

4.7U_0603_6.3V6K

@

12

PC174

2200P_0402_50V7K

12

PQ49

TPCA8028-H_SOP-ADVANCE8-5

4

1

2

3 5

PJ19

JUMP_43X79@

11

2

2

PC149

10U_0603_6.3V6M

12

PC138

0.1U_0402_25V6

@

12

PJ17

JUMP_43X79@

11

2

2

PR244

31.6K_0402_1%

1 2

PC177

10U_0603_6.3V6M

12

PR246

30.1K_0402_1%

12

PR243

100K_0402_1%@

1 2

PR128

23.7K_0402_1%

@

1 2

+

PC172

220U_B2_2.5VM_R15M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LDO_1.8V_IN

LDO_1.8V_REF

LDO_1.8V_EN

FSET_VGA

VGA_EN_2 ISEN_VGA

BST_VGA-1

VGA_IN

SW _VGA

VGA_COMP-1

VGA_VCC

+VGA_PVCC

VGA_FB

VGA_COMP

UG_VGA

BST_VGA

LG_VGA

GVID1-1

GVID1-2

GVID0-1

VGA_VCC

VGA_FB-1

VGA_SNB

SUSP<8,39,44>

VGA_EN<16>

GPU_VID0<19>

GPU_VID1<19>

+VGASENSE <21>

+1.8VSP

+3VS

+5VS

+3VS

+VGA_COREP

B+

+VGA_COREP +VGA_CORE

+5VALW

+1.8VS+1.8VSP

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1

VGA_CORE/1.8VS/1.1VS

45 51Thursday, October 29, 2009

Compal Electronics, Inc.

2010/01/062009/01/06

VFB=0.6V

Rds=4.0mΩ

GPIO6GPIO5

N11M-GE1/LP1 PR620=22.6k

0

GPU_VID1GPU_VID0 VGA_CORE

0.85V

0

1

0

1

0.9V

1

0.8V

N11M-GE1/LP1

PC55

0.01U_0402_25V7K

@

12

PR69

42.2K_0402_1%

1 2

PC51

1U_0402_6.3V6K

12

PR67

6.04K_0402_1%

12

PR49

0_0603_5%

12

PC54

6800P_0402_25V7K

12

PR170

10K_0402_1%

12

PR180

5.36K_0402_1%

12

PU3

ISL6268CAZ-T_SSOP16

EN

5

BOOT 15

PVCC 14

VIN

3

VCC

4

PGOOD 2

PHASE 1

UG 16

LG 13

PGND 12

VO

10

COMP

6

FB

7

FSET

9

ISEN 11

GND 8

PC24

10U_1206_25V6M

12

PQ39

SI4634DY-T1-E3_SO8

4

7

8

6

5

1

2

3

PL7

0.88UH_PCMB103E-R88MS_20A_20%

1 2

PC50

2.2U_0603_6.3V6K

12

PR103

100K_0402_1%

1 2

PC127

0.01UF_0402_25V7K

12

G

D

S

PQ22

SSM3K7002FU_SC70-3

2

13

PC35

10U_1206_25V6M

12

PR63

3.6K_0402_1%

1 2

PC19

10U_0603_6.3V6M

12

PC79

1U_0402_6.3V6K

12

PC18

10U_0603_6.3V6M

12

PQ36

SI4634DY-T1-E3_SO8

4

7

8

6

5

1

2

3

PC77

0.1U_0402_16V7K

12

PR164

4.7_1206_5%

12

PR46

4.7_0603_5%

1 2

PR166

10K_0402_1%

12

PR179

1.82K_0402_1%

12

PC126

680P_0402_50V7K

12

PR70

100_0402_5%

12

PQ37B

2N700 2KDW -2N_SOT363-6

34

5

PJ2

JUMP_43X118@

11

2

2

PJ3

JUMP_43X79@

11

2

2

PR71

0_0402_5%

1 2

PR105

1.24K_0402_1%

12

PR47

10K_0402_5%

@

1 2

PR104

1K_0402_1%

12

PC20

10U_0603_6.3V6M

12

PC76

0.1U_0402_16V7K

12

PR72

10K_0402_5%

12

PC52

2.2U_0603_6.3V6K

1 2

PQ37A

2N700 2KDW -2N_SOT363-6

61

2

PJ606

JUMP_43X39@

1

122

PQ35

TPCA8030-H_SOP-ADV8-5

4

5

1

2

3

PC75

4.7U_0805_6.3V6K

12

PR62

2.2K_0402_5%

1 2

+

PC133

330U_D2_2.5VY_R9M

1

2

PR169

22.6K_0402_1%

1 2

PC49

0.1U_0603_25V7K

1 2

PC186

0.1U_0402_25V6

12

PJ13

JUMP_43X118@

11

2

2

PJ8

JUMP_43X39@

11

2

2

PC134

22P_0402_50V8J

12

PC78

10U_0603_6.3V6M

12

PU6

G2992F1U_SO8

VOUT

4

NC 5

GND

2

VREF

3

VIN

1VCNTL 6

NC 7

NC 8

TP 9

PR68

22.1K_0402_1%

12

PC185

2200P_0402_50V7K

12

PR48

2.2_0603_5%

1 2

+

PC17

330U_D2_2.5VY_R9M

1

2

PR165

10K_0402_5%

12

PC129

0.01UF_0402_25V7K

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VTT_COMP

UG_VTT

VTT_BOOT

VTT_EN-1

VTT_VCC

LG_VTT

VTT_ISEN

VTT_SNB

VTT_BOOT-1

VTT_B+

VTT_FSET

VTT_COMP-1

SW_VTT

VTT_VCC

VTT_PVCC

VTT_FB

1.1VS_PGOOD

VTT_FB-1

1.05V_PGOOD<44>

VTT_SENSE <8>

VCCP_POK<5>

SUSP#<16,28,34,39,42,44>

VTT_SELECT<8>

B+

+1.1V_VCCPP

+5VALW

+1.1V_VCCPP +VCCP

+5VS

+1.1V_VCCPP +1.05VS

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0.1

+1.1VS_VTT

Cus t om

46 51Thursday, October 29, 2009

2009/01/06 2010/01/06

Compal Electronics, Inc.

Rds=4.0mΩ

VFB=0.6V

H_VTTVID1= Low, 1.1V

H_VTTVID1= High, 1.05V

PQ21

TPCA8028-H_SOP-ADVANCE8-5

4

1

2

3 5

PQ23

TPCA8028-H_SOP-ADVANCE8-5

4

1

2

3 5

PR108

4.7_0603_5%

1 2

PC82

0.01U_0402_25V7K

@

12

PU7

ISL6268CAZ-T_SSOP16

EN

5

BOOT 15

PVCC 14

VIN

3

VCC

4

PGOOD 2

PHASE 1

UG 16

LG 13

PGND 12

VO

10

COMP

6

FB

7

FSET

9

ISEN 11

GND 8

PR106

0_0603_5%

12

PC87

0.1U_0402_16V7K@

12

PJ1

JUMP_43X118@

11

2

2

PC81

2.2U_0603_6.3V6K

1 2

PR107

4.7_1206_5%

12

PR118

22.1K_0402_1%

12

PR117

0_0402_5%@

1 2

PR116

0_0402_5%

1 2

PC188

0.1U_0402_25V6

12

PR120

1.58K_0402_1%

1 2

PR113

42.2K_0402_1%

12

PJ7

JUMP_43X118@

11

2

2

PQ24

TPCA8030-H_SOP-ADV8-5

4

5

1

2

3

PC187

2200P_0402_50V7K

12

PJ9

JUMP_43X118

@

11

2

2

PR111

0_0402_5%

12

PR114

0_0402_5%

1 2

PC86

2.2U_0603_6.3V6K

12

PR121

35.7K_0402_1%

1 2

PR109

3K_0402_1%

1 2

PC89

6800P_0402_25V7K

12

PC85

10U_1206_25V6M

12

PC84

0.1U_0603_25V7K

1 2

PL8

0.56UH_MMD-10CZ-R56M-M1_19A_20%

1 2

PJ15

JUMP_43X118@

11

2

2

PC80

1000P_0603_50V7K

12

PR119

1.96K_0402_1%

12

+

PC74

330U_D2E_2.5VM

@

1

2

+

PC139

330U_D2E_2.5VM

1

2

PR112

2.2_0603_5%

1 2

PR115

1K_0402_5%

12

PC83

10U_1206_25V6M

12

PR110

10_0402_5%

1 2

PC88

22P_0402_50V8J

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ISUM-2

ISUM-

GF X _FB -1

GF X _SN

GF X _FB -2

ISUM+

ISUM+

LG_GFX

LX_GFX

62 881_VID0

62881_VR_ON

62 8 81 _D P R SLPV R

BST_GFX BST_GFX1

ISUM-3

62 881_VID1

ISUM-

62 881_VID2

62 881_VID3

62 881_VIN

62 881_VW

62 881_VID4

62 881_ RBIAS

62 881_VID5

62 881_VID6

ISUM-4

ISUM-1

62 881_COMP

62881_VDD

62 881_FB

UG_ GFX

62 881_ VCCP

GFX_B+

GF X VR_VID_0 <8>

GF X VR_VID_1 <8>

GF X VR_VID_2 <8>

GF X VR_VID_3 <8>

GF X VR_VID_4 <8>

GF X VR_VID_5 <8>

GF X VR_VID_6 <8>

GF X VR_EN <8>

GF X VR_D PRSLPVR <8>

GF X VR_IMON <8>

VS S_AXG_SENSE <8>

VC C _AXG_SENSE<8>

VS S_AXG_SENSE<8>

GF X VR_PWRGD

GF X VR_C LKEN#

B+

+GFX_COREP

+5VALW

+5VALW

+GF X_COREP

+GF X_COREP

+GF X_COREP +GF X_CORE

Title

Size Doc umen t Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0 . 1

GFX_CORE

47 51Thu rsda y, Oc t ober 29, 2009

2009/01/06 2010/01/06

Compal Electronics, Inc.

(15A,600mils ,Via NO.= 30)

PR 2 30

47K_0402_1%

@

12

PR 2 27

2.61K_0402_1%

@

1 2

PC 1 64

0. 2 2U_0603_25V7K

@

12

PR 9 6

1_0603_5%

@

12

P C 60

680P_0402_50V7K

@

1 2

P R 90

11 K_0402_1%

@

1 2

PC 1 63

0. 2 2U_0 402_6.3V6K

@

12

PQ 47

SI 4 686 D Y-T1-E3_SO8

@

3 6

5

7

8

2

4

1

PC 1 60

2200P_0402_50V7K

@

12

PC 1 71

1000P_0402_50V7K

@

12

PQ 19

TPC A8028_PSO8

@

3 5

2

4

1

PR 2 25

0_ 0603_5%

@

1 2

PR 2 320_ 0402_5%

@

12

P R 89

100_0402_1%

@

1 2

PR 9 4

82 . 5_0402_1%

@

1 2

PR 1 00

17.8K_0402_1%

@

12

P R 93

3.01K_0402_1%

@

1 2

P R 91

22.6K_0402_1%

@

12

PJ 1 8

JUMP_43X118@

11

2

2

P C 65

0. 1 U_0402_16V7K

@

1 2

P C 61

10U_1206_25V6M

@

12

PL 12

0. 5 6UH_M MD-10CZ-R56M-M1_19A_20%

@

1 2

PR 1 02

10 _0402_5%

@

1 2

PR 2 350_ 0402_5%

@

12

PC 1 61

0. 1 U_0402_25V6

@

12

PC 1 65

1U _ 0603_10V6K

@

12

PC 7 0

0.068U_0402_10V6K

@

1 2

P R 95

0_ 0603_5%

@

1 2

PR 2 360_ 0402_5%

@

12

PJ 5

JUMP_43X118

@

11

2

2

+

PC 1 58

33 0U_D 2 _2. 5VY_R9M

@

1

2

PC 7 3

150P_0402_50V8J

@

12

PR 2 370_ 0402_5%

@

12

P C 71

100P_0402_50V8J

@

1 2

PR 2 340_ 0402_5%

@

12

P R 81

0_ 0402_5%

@

12

P R 99

825K_0402_1%

@

1 2

+

P C 67

33 0U_D 2 _2. 5VY_R9M

@

1

2

P R 98

8.06K_0402_1%

@

12

PR 2 290_ 0402_5%

@

12

P R 80

2. 2 _1206_5%

@

12

PR 1 01

10 _0402_5%

@

1 2

PR 2 24

0_ 0402_5%@

1 2

PC 1 70

22 P_0402_50V8J

@

1 2

P H 4

10 KB_0603 _5%_ERTJ1VR103J

@

1 2

PC 1 67

330P_0402_50V7K

@

1 2

P C 59

10U_1206_25V6M

@

12

PR 2 38

10 K_0402_1%

@

12

P C 69

18 0P_0402_50V8J

@

1 2

PR 9 7

1.91K_0402_1%

@

12

PC 1 62

0. 2 2U_0 603_16V7K

@

1 2

PC 7 2

330P_0402_50V7K

@

12

PR 2 330_ 0402_5%

@

12

P C 68

0. 0 1U_0 402_25V7K

@

1 2

P C 66

2. 2 U_06 03_6.3V6K

@

12

PR 2 26

10K_0402_1%

@

12

P J 6

JUMP_43X118@

11

2

2

PR 8 2

3.65K_0402_1%

@

12

PC 1 66

1000P_0402_50V7K

@

1 2

PR 2 310_ 0402_5%

@

12

P U 5

ISL 628 81HRZ-T_QFN28_4X4

@

FB

6

CLK_EN#

1

PGOOD

2

ISUM+ 10

ISUM 9

VID5

25

VID1 21

LGATE 18

VSSP 17

VID2

22

UGATE 15

RTN 8

RBIAS

3

VW

4

COMP

5

VID0 20

VCCP 19

VID3

23

VID4

24

VID6

26

VR_ON

27

DPRSLPVR

28

VSEN

7

VDD 11

VIN 12

IMON 13

BOOT 14

PHASE 16

AGND 29

P R 92

2. 2 _0603_5%

@

1 2

PR 2 280_ 0402_5%

@

12

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

C PU _SNB1

H _V ID0

H _V ID2

H _V ID3

H _V ID4

H _V ID5

H _V ID6

H _V ID1

V ID0

V ID1

V ID2

V ID3

V ID4

V ID5

V ID6

BO OT_CPU2 BOO T _ CPU2-1

C PU _SNB2

BO OT_CPU1 BOO T _ CPU1-1

PH A SE_ CPU2

LG ATE_CPU2

U GA TE _ C PU2

U GA TE _ C PU2

PH A SE_ CPU1

LG ATE_CPU1

U GA TE _ C PU1

U GA TE _ C PU1

CPU _SN- 1

C P U _ CS N 1

C PU _CSP1

CPU _CSP 1 -1

CPU _SN- 2

C P U _ CS N 2

C PU _CSP2

CPU _CSP 2 -1

CPU _OSR SEL

C PU _PGO OD

C P U _ VR _O N

C PU _T O N SEL C P U _ VR EF

C P U _ VR EF

C P U _ DR O OP

CPU _CLK _EN#

C PU _ISLE W

CPU _MODE

PS I # CPU_ PSI#

C PU_D PR SLP VRP ROC _D PRSL PVR

CPU _IMON

CPU _ VR_TT#

C PU _T H ER M

C PU _CSP1

C P U _ CS N 1

C P U _ CS N 2

C PU _CSP2

CPU _CSP 1 -2

CPU _CSN 1 -1

CPU _CSN 2 -1

CPU _CSP 2 -2

C PU _VSN S

C P U _ GN D SN S

H _V ID0

H _V ID1

H _V ID2

H _V ID6

H _V ID3

H _V ID0

H _V ID1

H _V ID2

H _V ID6

H _V ID3

P ROC _D PRSL PVR

H _V ID4

P ROC _D PRSL PVR

H _V ID5

H _V ID4

H _V ID5

C PU _T R I PSE L

V R _ON<3 4>

V C CS EN SE

<8>

VSSSENSE

<8>

IMVP_IMON

<8>

H _V ID 0

<8>

H _V ID 1

<8>

H _V ID 2

<8>

H _V ID 3

<8>

H _V ID 4

<8>

H _V ID 5

<8>

H _V ID 6

<8>

VGATE<15>

CLK _EN #<12>

PS I#

<8>

P R OC _D PR SL PV R

<8>

H_P ROCH O T#

<5,34>

VSSSENSE

<8>

CPU_B+

+5VS

+5VS

B+

CPU_B+

+5VS

+ C PU _C OR E

+5VS

+3VS

+5VS

+VC C P

+ VC C P

+3VS

Title

Size Doc umen t Number R e v

Dat e: Sh eet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

0 . 1

CPU_CORE

48 51Thu rsda y, Oc t ober 29, 2009

2009/01/06 2010/01/06

Compal Electronics, Inc.

Clarkfield:VID(0-5):001101

Auburndale:VID(0-5):001110

P R 58 1K _0 402 _5%

12

PR 2 15 0_ 0402_5%

1 2

+

PC 1 68

10 0U_25V_M

1

2

PC 1 56

100P_0402_50V8J

12

PR 2 18

5.11K_0402_1%

12

P C 53 10 U _06 03_6. 3V6 M

1 2

PR 2 12

0_0402_5%

@

12

P R 45

12.4K_0402_1%

12

PR 7 5

1K _0402_5%@

1 2

PL 11

0. 3 6UH_PCMC1 04T-R36MN1R17_30A_20%

1

3

4

2

PC 2 9

10U_1206_25V6M

12

P R 790 _0 402_ 5%

1 2

PR 1 83

28.7K_0402_1%

1 2

PC 1 59

0. 0 33U _ 0402_16V7K

1 2

PR 1 92 1K _0402_5%

12

P R 60 1K _0 402 _5%@

12

PC 1 53

100P_0402_50V8J

12

PR 2 14 0_ 0402_5%

1 2

P C 58

68 P_0402_50V8J

1 2

PR 1 96 0_ 0402_5%

1 2

PR 6 6

0_0402_5%

12

PC 1 52 33 P_0 402_50V8J

1 2

PL 10

0. 3 6UH_PCMC1 04T-R36MN1R17_30A_20%

1

3

4

2

+

PC 1 48

10 0U_25V_M

1

2

PQ 18

TPC A803 0-H_SOP-ADV8-5

@

4

5

1

2

3

PR 2 100_ 0402_5%

1 2

PR 1 86

17.8K_0402_1%

12

PR 1 980_ 0402_5%

1 2

PQ 15

TPC A803 0-H_SOP-ADV8-5

4

5

1

2

3

PC 1 45

0. 2 2U_0603_10V7K

1 2

P R 61 1K _0 402 _5%@

12

PR 1 91 1K _0402_5%

12

PC 3 0

10U_1206_25V6M

12

PR 2 16 68 _0402_5%

1 2

P R 56 1K _0 402 _5%@

12

P C 57

0. 2 2U_0 603_10V7K

1 2

P C 45

2200P_0402_50V7K

12

PR 2 04 1K _0402_5%

12

P C 47

2200P_0402_50V7K

12

PR 2 05 0_ 0402_5%

1 2

P C 44

0. 2 2U_0 402_6.3V6K

12

P R 55 1K _0 402 _5%@

12

PC 3 4

10U_1206_25V6M

12

PR 2 07 0_ 0402_5%

1 2

PR 2 01 1K _0402_5%@

12

PC 1 55 33 P_0 402_50V8J

1 2

PR 1 970_0402_5%

@

1 2

PR 2 11 1K _0402_5%@

12

PR 1 87 2 .2_0603_5%

12

PC 3 1

10U_1206_25V6M

12

P R 77

1.91K_0402_1%

1 2

PR 2 02 1K _0402_5%@

12

PR 2 03 1K _0402_5%

12

P R 57 1K _0 402 _5%

12

P R 53 20 K_ 040 2_1%

1 2

PC 1 44

0. 2 2U_0603_10V7K

1 2

PC 1 54 33 P_0 402_50V8J

1 2

PC 1 42

680P_0402_50V7K

12

PR 2 08 0_ 0402_5%

1 2

PQ 17

TPC A803 0-H_SOP-ADV8-5

4

5

1

2

3

P H 3

10 0K_0402_1%_TSM0B104F4251RZ

1 2

PC 1 57 33 P_0 402_50V8J

1 2

PC 1 43

680P_0402_50V7K

12

PR 2 22

69.8K_0402_1%

1 2

PR 2 13 0_ 0402_5%

1 2

PR 2 20 47 0_0402_1%

12

PR 1 88

28.7K_0402_1%

1 2

PR 1 94 0_ 0402_5%

1 2

P H 2

10 0K_0402 _1%_TSM 0B104F4251RZ

1 2

PQ 42

TPC A802 8-H _SOP-ADVANCE8-5

@

4

1

2

3 5

P R 780 _0 402_ 5%@

1 2

PR 1 89 2 .2_0603_5%

1 2

PQ 44

TPC A802 8-H _SOP-ADVANCE8-5

4

1

2

3 5

PR 2 21 47 0_0402_1%

12

PR 2 23 47 0_0402_1%

12

PR 1 84

4.7_1206_5%

12

P R 54 10 K_ 040 2_5%

12

PR 1 95 0_ 0402_5%

1 2

P R 64

69.8K_0402_1%

1 2

P R 59 1K _0 402 _5%

12

PC 4 8

0. 1 U_0402_25V6

12

PR 2 17 0_ 0402_5%

1 2

PR 1 82

17.8K_0402_1%

12

PR 7 6

1K _0402_5%

12

PQ 43

TPC A802 8-H _SOP-ADVANCE8-5

4

1

2

3 5

PR 1 99 0_ 0402_5%

1 2

P C 56

0. 0 33U _ 0402_16V7K

1 2

PR 6 5

0_0402_5%

12

PR 1 93 1K _0402_5%@

12

PC 4 6

0. 1 U_0402_25V6

12

PQ 16

TPC A803 0-H_SOP-ADV8-5

@

4

5

1

2

3

P D 6

1S S355_SOD323-2

1 2

P D 7

1S S355_SOD323-2

1 2

PR 2 00 0_ 0402_5%

1 2

PC 3 3

10U_1206_25V6M

12

PC 1 50

2. 2 U_06 03_6.3V6K

1 2

PR 2 06 0_ 0402_5%

1 2

PR 2 19 47 0_0402_1%

12

PR 2 09 0_ 0402_5%

1 2

P R 742 49 K_ 0402_ 1%

1 2

PC 3 2

10U_1206_25V6M

12

TPS 516 21R HAR_QFN40_6X6

P U 12

MODE

1

GND

2

CSP2

3

CSN2

4

CSN1

5

CSP1

6

GNDSNS

7

VSNS

8

THERM

9

VR_TT#

10

IMON

11

DPRSLPVR

12

PSI#

13

VID6

14

VID5

15

VID4

16

VID3

17

VID2

18

VID1

19

VID0

20

DRVH1 21

VBST1 22

LL1 23

DRVL1 24

PGND 25

V5IN 26

DRVL2 27

LL2 28

VBST2 29

DRVH2 30

TRIPSEL 31

OSRSEL 32

PGOOD 33

CLK_EN# 34

VR_ON 35

TONSEL 36

ISLEW 37

V5FILT 38

DROOP 39

VREF 40

GND 41

P R 73 0_ 04 02_ 5%

1 2

PL 1

HCB4532 KF-800T90_1812

1 2

PQ 45

TPC A802 8-H _SOP-ADVANCE8-5

@

4

1

2

3 5

PR 1 85

4. 7 _1206_5%

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number R e v

Date: Sheet o f

Security Classification

Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Deciphered Date

<Doc>

0.1

PIR (PWR)

Cus t om

49 51Thursday, October 29, 2009

2009/01/06 2009/01/06

Compal Electronics, Inc.

Version change list (P.I.R. List) Page 1 of 2

for PWR

Reason for change PG# Modify List Date PhaseItem

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

20081022

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number R e v

Date: Sheet o f

LA-5752P 0.3

HW PIR

B

50 51Thursday, October 29, 2009

Compal Electronics, Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number R e v

Date: Sheet o f

LA-5751 0.3

HW PIR

B

51 51Thursday, October 29, 2009

Compal Electronics, Inc.

www.s-manuals.com