Compal LA 5754P Schematics. Www.s Manuals.com. R0.2 Schematics
User Manual: Motherboard Compal LA-5754P NAWE6 AMD Danube - Schematics. Free.
Open the PDF directly: View PDF .Page Count: 48
A
http://hobi-elektronika.net
B
C
D
E
1
1
Compal Confidential
2
2
NAWE6 Schematics Document
AMD Danube
Champlain Processor with RS880M/SB820/Park VGA
2010-02-24
3
3
LA5754 REV: 0.2
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Cover Page
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
1
of
47
A
B
C
Compal Confidential
D
ZZZ1
E
ZZZ2
Model Name : AMD Danube + Park
LA5754P
LS-5758P
DAZ@
@
DA40000TD00
ZZZ3
POWER BTN
NOVO BTN
POWER MANAGE BTN
LS5756P
@
DA40000T300
Danube
VRAM 512MB
64M16 x 4
AMD S1G4 Processor
Memory BUS(DDR3)
uPGA-638 Package
Champlain page 4,5,6,7
PCI-Express x 16
RTS5159
HP JACK
MIC JACK
LS5753P
@
DA40000Q210
1
page 18
DDR3
ATI M93-S3
Park - S3
uFCBGA-631
ZZZ4
VOLUME UP
VOLUME DOWN
MUTE
AUDIO ENHANCE
BUTTON & LED
4 layer
DA80000IP00
1
CARD READER BD:
CAP SENSOR BD:
POWER BD:
204pin DDRIII-SO-DIMM X2
Dual Channel
page 8,9
BANK 0, 1, 2, 3
1.5V DDRIII 800~1333MHz
Hyper Transport Link
16 x 16
Page 13,14,15,16,17
Gen2
Thermal Sensor
ATI RS880M
Clock Generator
ADM1032
ICS9LPRS488
page 6
LVDS
page 19
uFCBGA-528
page 27
2
page 10,11,12,13
page 37
page 37
page 27
page 37
page 28
page 28
2
page 28
CRT
page 25
A link Express2
Gen1
HDMI Conn.
page 26
ATI SB820M
New Card
WLAN
page 28
GPP3
3G/WWAN
MINI Card
MINI Card
WLAN
page 28
GPP2
page 28
GPP1
page28
LED
USB
conn
(Right)
USB port 0
USB port 12
3.3V 48MHz
CMOS
Camera
Atheros
AR8151/8152
page 20,21,22,23,24
page 29
USB port 6
USB port 5
3G/GPS
WWAN
New Card
USB port 11
USB port 10
USB port 7
3.3V 24.576MHz/48Mhz
HD Audio
RJ45
SATA HDD
Conn. page 32
CDROM
Conn.
page 32
port 0
port 1
LPC BUS
page 30
Mini
card
(WL)X1
Gen2
S-ATA
uFCBGA-605
LAN(GbE)
Bluetooth
Conn
USB
GPP0
SIM
Card
3
USB
PORT
(LEFT)
ESATA &
USB
Combine CON
3
USB port 4
page28
USB(WWAN)
page 36
LID SW / IO BD
Touch Pad
page33
page 35
Analog
MIC_Int
BIOS
4
RTS5159-GR
MS/MS
pro/SD/SD
pro/mmc/XD
Int.KBD
page 35
page 32
DC/DC Interface CKT.
Card Reader /
Audio Jack SB CONN
Realtec ALC259
page 34
page 32
Power On/Off CKT.
USB port 2
Audio Codec
ENE KB926
Fan Control
2Channel
Speaker
page33
HP X 1+
MIC_Ext X1
page38
page33
page 34
page 31
4
page 38
Power Circuit
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
page 39,40,41,42,43,
44,45,46,47,48,49
2009/10/06
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Block Diagrams
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
2
of
47
http://hobi-elektronika.net
A
B
Voltage Rails
1
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE_0
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
+CPU_CORE_1
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
ON
OFF
OFF
+0.75VS
+0.75VS LDO power rail for DDR3 VTT
ON
ON
OFF
+1.1VS
1.1V switched power rail for NB VDDC & VGA
ON
OFF
OFF
+CPU_CORE_NB
2
C
Voltage for On-die Northbridge of CPU(0.8-1.1V)
+VGA_CORE
0.95-1.2V switched power rail
ON
OFF
OFF
+1.5VS
1.5V power rail for PCIE Card
ON
OFF
OFF
+1.5V
1.5V power rail for CPU VDDIO and DDR
ON
ON
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
+2.5VS
2.5V for CPU_VDDA
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V_LAN
3.3V power rail for LAN
ON
ON
ON
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
D
E
1
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
STATE
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Full ON
2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device
IDSEL#
REQ#/GNT#
EC SM Bus1 address
Interrupts
EC SM Bus2 address
3
3
Device
Address
HEX
Smart Battery
0001 011X b
16H
Device
Address
HEX
EMC1402-1 (CPU)
100_1100b
4CH
EMC1412-A (GPU)
111_1100b
7CH
100_1101b
4DH
EMC1403-2 (DDR,WWAN)
SB820
SM Bus 0 address
SB820
SM Bus 1 address
Device
Address
HEX
Clock Generator
(SILEGO SLG8SP626)
1101 001Xb
D2
DDR DIMM1
1001 000Xb
90
DDR DIMM2
1001 010Xb
94
Device
BOM Config
UMA only SKU: UMA@
DIS ONLY (Park S3): DIS@
EXT CLK Mode:EXT@
INT CLK mode:INT@
LAN GIGA: 8151@
LAN 100: 8152@
CMOS@
BT@
3G@
S@
H@
Address
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Issued Date
4
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Notes List
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
3
of
47
A
B
C
D
E
1
1
VLDT CAP.
+1.1VS
250 mil
2
[10] H_CADIP[0..15]
[10] H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
[10]
1
H_CADON[0..15]
H_CADON[0..15]
2
C1
10U_0805_10V4Z
1
1
C2
10U_0805_10V4Z
C3
0.22U_0603_16V4Z
2
1
C4
0.22U_0603_16V4Z
2
1
C5
180P_0402_50V8J
2
1
C6
180P_0402_50V8J
2
[10]
Near CPU Socket
+1.1VS
+1.1VS
JCPU1A
TBD
2
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
3
C7
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
[10]
[10]
[10]
[10]
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
[10]
[10]
[10]
[10]
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
2
2
1
10U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
3
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
[10]
[10]
[10]
[10]
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
[10]
[10]
[10]
[10]
FOX_PZ6382A-284S-41F_Champlian
ME@
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G4 HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
4
of
47
A
B
C
D
E
Processor DDR3 Memory Interface
JCPU1C
[9] DDRB_SDQ[63..0]
1
MEM:DATA
2
+1.5V
1
R1
1K_0402_1%
C8
1000P_0402_50V7K
1
2
C9
0.01U_0402_25V7K
2
MEM_VREF
1
R2
1K_0402_1%
1
2
+1.5V
+CPU_VDDR
+CPU_VDDR
JCPU1B
2
2
Place them
close to CPU
within 1"
R368
0_0402_5%
1
R4
1
1
R5
C588
2
10U_0805_10V4Z
@ 1
[8] MEM_MA_RST#
[8] DDRA_ODT0
[8] DDRA_ODT1
[8] DDRA_SCS0#
[8] DDRA_SCS1#
[8] DDRA_CKE0
[8] DDRA_CKE1
[8] DDRA_CLK0
[8] DDRA_CLK0#
3
[8] DDRA_CLK1
[8] DDRA_CLK1#
[8] DDRA_SMA[15..0]
[8] DDRA_SBS0#
[8] DDRA_SBS1#
[8] DDRA_SBS2#
[8] DDRA_SRAS#
[8] DDRA_SCAS#
[8] DDRA_SWE#
1.5A
D10
C10
B10
AD10
39.2_0402_1%
MEMZP AF10
2
MEMZN AE10
2
39.2_0402_1%
MEM_MA_RST#
H16
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
R20
R23
J21
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
R19
T22
T24
VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
MA_RESET_L
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MEMVREF
MB_RESET_L
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
W10
AC10
AB10
AA10
A10
Y10
FOR DDR3 1066, VDDR is 0.9V
FOR DDR3 1333, VDDR it should be 1.05V
VTT_SENSE
W17
MEM_VREF
B18
MEM_MB_RST#
W26
W23
Y26
DDRB_ODT0
DDRB_ODT1
V26
W25
U22
DDRB_SCS0#
DDRB_SCS1#
J25
H26
DDRB_CKE0
DDRB_CKE1
P22
R22
A17
A18
AF18
AF17
R26
R25
DDRB_CLK0
DDRB_CLK0#
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
R24
U26
J26
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
U25
U24
U23
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRB_CLK1
DDRB_CLK1#
PAD
T1
MEM_MB_RST# [9]
DDRB_ODT0 [9]
DDRB_ODT1 [9]
DDRB_SCS0# [9]
DDRB_SCS1# [9]
DDRB_CKE0 [9]
DDRB_CKE1 [9]
DDRB_CLK0 [9]
DDRB_CLK0# [9]
DDRB_CLK1 [9]
DDRB_CLK1# [9]
DDRB_SMA[15..0] [9]
[9] DDRB_SDM[7..0]
DDRB_SBS0# [9]
DDRB_SBS1# [9]
DDRB_SBS2# [9]
DDRB_SRAS# [9]
DDRB_SCAS# [9]
DDRB_SWE# [9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
DDRA_SDQ[63..0]
[8]
1
2
DDRA_SDM[7..0]
[8]
3
DDRA_SDQS0 [8]
DDRA_SDQS0# [8]
DDRA_SDQS1 [8]
DDRA_SDQS1# [8]
DDRA_SDQS2 [8]
DDRA_SDQS2# [8]
DDRA_SDQS3 [8]
DDRA_SDQS3# [8]
DDRA_SDQS4 [8]
DDRA_SDQS4# [8]
DDRA_SDQS5 [8]
DDRA_SDQS5# [8]
DDRA_SDQS6 [8]
DDRA_SDQS6# [8]
DDRA_SDQS7 [8]
DDRA_SDQS7# [8]
FOX_PZ6382A-284S-41F_Champlian
ME@
FOX_PZ6382A-284S-41F_Champlian
ME@
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G4 DDRII I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
5
of
47
B
C
3300P_0402_50V7K
2
+
C11
150U_B_6.3VM_R40M
4.7U_0805_10V4Z
1
C12
2
LDT_RES# / MEMHOT#
no support in S1g4
1
C13
2
2
+1.5V
1
1
FBMA-L11-201209-221LMA30T_0805 1
1
VDDA=0.25A
C14
0.22U_0603_16V4Z
1
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
2 3900P_0402_50V7K
1
1
C16
A9
A8
LDT_RST#
H_PWRGD
LDT_STOP#
2
R10
169_0402_1%
1
2
3900P_0402_50V7K
C15
+1.5V
+1.5V
+1.5VS
R12
R14
2
+1.1VS
1
R17
300_0402_5%
LDT_RST#
[20] LDT_RST#
1
1
2
2 1K_0402_5%
1K_0402_5%
R15
R16
2
1
+1.5VS [11,20] LDT_STOP#
2
1
1
R21
300_0402_5%
2
1
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
AF4
AF5
AE6
SIC
SID
ALERT_L
R6
P6
HT_REF0
HT_REF1
VDD1_FB_H
VDD1_FB_L
G10
AA9
AC9
AD9
AF9
DBRDY
TMS
TCK
TRST_L
TDI
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
LDT_STOP#
CPU_TEST23
AD7
CPU_TEST18
CPU_TEST19
H10
G9
CPU_TEST25H
CPU_TEST25L
C18
0.01U_0402_25V4Z
@
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
1
R24
2
0_0402_5%
E9
E8
AB8
AF7
AE7
AE8
AC8
AF8
C2
AA6
A3
A5
B3
B5
C1
+3VS
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA
Y6
AB6
C19
0.01U_0402_25V4Z
@
2
SVC
SVD
F6
E6
H_PWRGD
[20] H_PWRGD
VSS
RSVD11
CLKIN_H
CLKIN_L
[47] CPU_VDD1_FB_H
[47] CPU_VDD1_FB_L
R18
300_0402_5%
2
VDDA1
VDDA2
[47] CPU_VDD0_FB_H
[47] CPU_VDD0_FB_L
2
C17
0.01U_0402_25V4Z
@
T2 PAD
CPU_SIC
CPU_SID
2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1
1
1
+1.5VS
1
B7
A7
F10
C6
CPU_THERMTRIP#_R
VDD0_FB_H
VDD0_FB_L
1
R8
1
R9
CPU_SVC
CPU_SVD
CPU_SVC [47]
CPU_SVD [47]
+1.5V
CPU_THERMTRIP#_R
H_PROCHOT#
AF6
AC7
AA8
W7
W8
Q1
1
2
0_0402_5%
H_THERMTRIP# [21]
2
0_0402_5%
MAINPWON [39,40,42]
1
MMBT3904_NL_SOT23-3
M11
W18
A6
A4
3
C
F8
F9
E
JCPU1D
[19] CLK_CPU_BCLK#
B
1K_0402_5%
2
1
[19] CLK_CPU_BCLK
R6
10K_0402_5%
R7
2 2
+2.5VS
E
Champlain: C1E
C1E: LDT_REQ# no connect
CLMC: LDT_REQ# connect to NB
+2.5VDDA
L1
D
2
A
PAD
1
R11
2
300_0402_5%
H_PROCHOT#
1
R13
T3
PROCHOT:
Input: For HTC Function
Output: Over Temperature Condition
THERMDC_CPU
THERMDA_CPU
VDDIO_FB_H
VDDIO_FB_L
VDDIO_FB_H
VDDIO_FB_L
W9
Y9
VDDNB_FB_H
VDDNB_FB_L
H6
G6
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
PAD
PAD
@
2
0_0402_5%
1
R71
@
H_PROCHOT_R# [20]
2
0_0402_5%
EC_PROCHOT# [34]
T14
T16
CPU_VDDNB_FB_H [47]
CPU_VDDNB_FB_L [47]
+1.5V
TEST23
TEST28_H
TEST28_L
TEST18
TEST19
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
TEST9
TEST6
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
2
J7
H8
D7
E7
F7
C7
CPU_SVC
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
PAD
PAD
PAD
PAD
T5
T6
T7
T8
1
R19
1
R20
CPU_SVD
2
1K_0402_5%
2
1K_0402_5%
+1.5V
C3
K8
CPU_TEST25H
1
R22
1
R23
CPU_TEST25L
1
R26
1
R27
C4
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
C9
C8
2
R25
1
80.6_0402_1%
H18
H19
AA7
D5
C5
@
@
2
510_0402_5%
2
510_0402_5%
+1.5V
2
510_0402_5%
2
510_0402_5%
0.1U_0402_16V4Z
+1.5V
3
FOX_PZ6382A-284S-41F_Champlian
ME@
1
C20
CPU_TEST27
2
1
THERMDA_CPU
2
THERMDC_CPU
3
2
3300P_0402_50V7K
C21
4
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
8
EC_SMB_CK2
7
EC_SMB_DA2
CPU_TEST12
5
CPU_TEST18
EMC1402-1
(SA00001Z700)
Address 100_1100b
S IC EMC1402-1-ACZL-TR MSOP 8P SENSOR
1
2
20K_0402_5%
@
@
@
CPU_TEST24
CPU_TEST23
34.8K_0402_1%
@
HDT_RST#
CPU_DBRDY
CPU_TDO
G
2
2.09V for Gate
@
1
EC_SMB_DA
D
FDV301N_NL_SOT23-3
@
2
0_0402_5%
2
0_0402_5%
SB_SID
SB_SID [21]
EC_SMB_DA2
+1.5V
T0 SB
TO EC
1
2
3
4
5
6
7
8
9
10
11
12
R43
@
1
2
0_0402_5%
+3VS
VB @
U2
GND
GND
HDT_RST#
13
14
4
B
A
LDT_RST#
2
Y
1
SB_PWRGD [11,21,34]
4
NC7SZ08P5X_NL_SC70-5
ACES_87212-12G0
ME@
G
2
Q2
@
1
R44
1
R45
1
2
3
4
5
6
7
8
9
10
11
12
3
CPU_SID 3
S
4
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
JP17
CPU_DBREQ#
CPU_TCK
CPU_TDI
CPU_TMS
CPU_TRST#
1
1
R29
1
R30
1
R31
1
R32
1
R33
1
R34
1
R35
1
R265
5
R42 @
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
CPU_TEST22
P
C22 @ 0.1U_0402_16V4Z
R41
CPU_TEST21
VB
2
CPU_TEST20
G
1
+1.5V
2
1
220_0402_5% R36
2
1
220_0402_5% R37
2
1
220_0402_5% R38
2
1
300_0402_5% R39
1
2
300_0402_5% R40
CPU internal thermal sensor
3
For SCAN connect use
EC_SMB_DA2 [14,31,34]
6
CPU_TEST19
TI
TMP411ADGKR MSOP 8P
SA00002DE10
Address: 100 1100
+3VS
2
1K_0402_5%
EC_SMB_CK2 [14,31,34]
EMC1402-1-ACZL-TR-MSOP-8P
2 @
1
R28
U1
1
@
CPU_SIC 3
EC_SMB_CK
D
S
Q3
@
1
FDV301N_NL_SOT23-3
1
R46
1
R47
@
SB_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%
SB_SIC [21]
T0 SB
TO EC
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G4 CTRL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
E
6
of
47
A
B
C
D
JCPU1F
VDD(+CPU_CORE) decoupling.
JCPU1E
+CPU_CORE
+CPU_CORE
1
1
+
1
+
C23
330U_X_2VM_R6M
1
2
1
+
C24 @
330U_X_2VM_R6M
2
C25
330U_X_2VM_R6M
2
1
+
C26
330U_X_2VM_R6M
2
+
C27
330U_X_2VM_R6M
2
Near CPU Socket
+CPU_CORE
+CPU_CORE
+CPU_CORE_NB
1
C28
22U_0805_6.3V6M
2
1
C29
22U_0805_6.3V6M
2
1
C30
22U_0805_6.3V6M
2
1
4A
C35
22U_0805_6.3V6M
1
2
1
C31
22U_0805_6.3V6M
2
C32
22U_0805_6.3V6M
2
+CPU_CORE
1
1
C33
22U_0805_6.3V6M
2
1
C34
22U_0805_6.3V6M
2
+1.5V
+CPU_CORE
C36
0.22U_0603_16V4Z
2
1
C37
0.01U_0402_25V4Z
2
1
E
1
C38
180P_0402_50V8J
2
C39
0.22U_0603_16V4Z
2
1
C40
0.01U_0402_25V4Z
2
1
C41
180P_0402_50V8J
2
Under CPU Socket
2
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+CPU_CORE
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
36A
+1.5V
TBD
FOX_PZ6382A-284S-41F_Champlian
Athlon 64 S1
ME@
VDDIO decoupling.
Processor Socket
+CPU_CORE_NB
decoupling.
+1.5V
+CPU_CORE_NB
1
C44
22U_0805_6.3V6M
2
1
C45
22U_0805_6.3V6M
1
1
C46
0.22U_0603_16V4Z
2
2
1
C47
1
C48
C50
1
0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2
2
2
C42
22U_0805_6.3V6M
2
1
C43
22U_0805_6.3V6M
2
1
C49
22U_0805_6.3V6M
2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
1
2
FOX_PZ6382A-284S-41F_Champlian
Athlon 64 S1 ME@
Under CPU Socket
Processor Socket
Between CPU Socket and DIMM
+1.5V
+CPU_VDDR
3
1
C51
0.22U_0603_16V4Z
2
1
C52
0.22U_0603_16V4Z
2
1
C53
0.22U_0603_16V4Z
2
1
1
C54
0.22U_0603_16V4Z
2
C354
0.22U_0603_16V4Z
2
1
VDDR decoupling.
C355
0.22U_0603_16V4Z
3
Near Power Supply
1
+
2
1
C56
150U_B_6.3VM_R40M
C55
22U_0805_6.3V6M
2
2
180PF Qt'y follow the distance between
+1.5V CPU socket and DIMM0. <2.5inch>
+1.5V
1
C64
0.01U_0402_25V4Z
2
1
2
C65
0.01U_0402_25V4Z
2
1
2
C66
0.1U_0402_16V7K
1
1
C67
0.1U_0402_16V7K
C68
180P_0402_50V8J
2
+CPU_VDDR
1
C69
1
180P_0402_50V8J
2
C57
4.7U_0805_10V4Z
2
1
C58
4.7U_0805_10V4Z
2
+1.5V
1
C59
0.22U_0603_16V4Z
2
1
C60
0.22U_0603_16V4Z
2
1
C61
1000P_0402_50V7K
2
1
C62
1000P_0402_50V7K
2
1
C63
180P_0402_50V8J
2
1
C70
180P_0402_50V8J
2
Near CPU Socket Right side.
+CPU_VDDR
1
1
2
1
C71
4.7U_0805_10V4Z
2
1
C72
4.7U_0805_10V4Z
2
1
C73
4.7U_0805_10V4Z
2
C74
4.7U_0805_10V4Z
+ C75
330U_X_2VM_R6M
1
2
2
C76
4.7U_0805_10V4Z
1
C77
4.7U_0805_10V4Z
2
1
C78
0.22U_0603_16V4Z
2
1
C79
0.22U_0603_16V4Z
2
1
C80
1000P_0402_50V7K
2
1
C81
1000P_0402_50V7K
2
1
C82
180P_0402_50V8J
2
1
C83
180P_0402_50V8J
2
4
4
Near CPU Socket Left side.
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
AMD CPU S1G4 PWR & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
7
of
47
A
B
+VREF_DQ
+1.5V
C
D
E
+1.5V
JDIMM1
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
[5] DDRA_SBS2#
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
[5] DDRA_CLK0
[5] DDRA_CLK0#
[5] DDRA_SBS0#
[5] DDRA_SWE#
[5] DDRA_SCAS#
[5] DDRA_SCS1#
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
[5] DDRA_SDQS4#
[5] DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
3
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
[5] DDRA_SDQS6#
[5] DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R50
10K_0402_5%
1
2
1
+3VS
4
R51
+3VS
2
C90
1
2
C91
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
205
10K_0402_5%
2.2U_0603_6.3V4Z
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
G1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
DDRA_SMA[0..15] [5]
MEM_MA_RST# [5]
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
+VREF_CA
DDRA_SDQS3# [5]
DDRA_SDQS3 [5]
+VREF_DQ
+1.5V
+1.5V
DDRA_SDQ30
DDRA_SDQ31
R310
1K_0402_1%
R48
1K_0402_1%
DDRA_CKE1
+VREF_DQ
DDRA_CKE1 [5]
DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
1
0.01U_0402_25V7K
2
DDRA_CKE0
DDRA_SDM1
MEM_MA_RST#
C84
@
2
2
C85
1
DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
+VREF_CA
1
C10
R49
1K_0402_1%
2
1
0.01U_0402_25V7K
[5] DDRA_CKE0
1
DDRA_SMA[0..15]
2
DDRA_SDQ24
DDRA_SDQ25
[5]
DDRA_SDQ12
DDRA_SDQ13
C235
@
2
2
C485
1
1
2
C838
R315
1K_0402_1%
2
DDRA_CLK1 [5]
DDRA_CLK1# [5]
DDRA_SBS1# [5]
DDRA_SRAS# [5]
DDRA_SCS0# [5]
DDRA_ODT0 [5]
DDRA_ODT1 [5]
+VREF_CA
DDRA_SDQ36
DDRA_SDQ37
1
C89
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
2
1000P_0402_50V7K
+1.5V
3
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
0.1U_0402_16V4Z
2
2
C87
DDRA_SDQS5# [5]
DDRA_SDQS5 [5]
C840
1
0.1U_0402_16V4Z
DDRA_SDQ46
DDRA_SDQ47
0.1U_0402_16V4Z
2
2
1
C88
1
0.1U_0402_16V4Z
2
C839
1
0.1U_0402_16V4Z
2
C836
1
0.1U_0402_16V4Z
2
C833
1
0.1U_0402_16V4Z
2
C831
1
0.1U_0402_16V4Z
2
C837
1
0.1U_0402_16V4Z
2
C834
C832
1
0.1U_0402_16V4Z
1
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
+0.75VS
DDRA_SDQ54
DDRA_SDQ55
2
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
0.1U_0402_16V4Z
2
C830
1
0.1U_0402_16V4Z
DDRA_SDQS7# [5]
DDRA_SDQS7 [5]
1
C835
1
C961
2
4.7U_0603_6.3V6K
Place near DIMM1
DDRA_SDQ62
DDRA_SDQ63
PAD
T10
SB_SMDAT0 [9,19,21,28]
SB_SMCLK0 [9,19,21,28]
+0.75VS
4
FOX_AS0A626-U4RN-7F
ME@
1
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
Compal Secret Data
Security Classification
DIMM_A Rervse H:4mm
2008/10/06
Issued Date
Deciphered Date
2010/03/12
Title
DDRII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
1
DDRA_SDQ18
DDRA_SDQ19
[5]
DDRA_SDM[0..7]
2
[5] DDRA_SDQS2#
[5] DDRA_SDQS2
DDRA_SDQ[0..63]
1
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
1000P_0402_50V7K
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS0# [5]
DDRA_SDQS0 [5]
DDRA_SDQ6
DDRA_SDQ7
4.7U_0805_10V4Z
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQS0#
DDRA_SDQS0
2
DDRA_SDQS1#
DDRA_SDQS1
[5] DDRA_SDQS1#
[5] DDRA_SDQS1
DDRA_SDQ4
DDRA_SDQ5
1
DDRA_SDQ8
DDRA_SDQ9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
1
DDRA_SDQ2
DDRA_SDQ3
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1000P_0402_50V7K
DDRA_SDM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
4.7U_0805_10V4Z
DDRA_SDQ0
DDRA_SDQ1
B
C
D
Rev
0.2
NAWE6 LA-5754P
Sheet
Monday, March 01, 2010
E
8
of
47
A
B
+VREF_DQ
C
+1.5V
D
E
+1.5V
JDIMM2
DDRB_SDQ8
DDRB_SDQ9
[5] DDRB_SDQS1#
[5] DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
[5] DDRB_SDQS2#
[5] DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
[5] DDRB_CKE0
2
[5] DDRB_SBS2#
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
[5] DDRB_SWE#
[5] DDRB_SCAS#
[5] DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
[5] DDRB_SDQS4#
[5] DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
3
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
[5] DDRB_SDQS6#
[5] DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R52
10K_0402_5%
1
2
1
+3VS
4
R53
2
10K_0402_5%
205
G1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQS0# [5]
DDRB_SDQS0 [5]
DDRB_SDQ[0..63]
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
[5]
DDRB_SDM[0..7] [5]
1
DDRB_SDQ12
DDRB_SDQ13
DDRB_SMA[0..15]
DDRB_SDM1
MEM_MB_RST#
DDRB_SMA[0..15] [5]
MEM_MB_RST# [5]
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQS3# [5]
DDRB_SDQS3 [5]
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
DDRB_CKE1 [5]
DDRB_SMA15
DDRB_SMA14
2
DDRB_SMA11
DDRB_SMA7
+VREF_DQ
DDRB_SMA6
DDRB_SMA4
+VREF_CA
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
+VREF_DQ
DDRB_CLK1 [5]
DDRB_CLK1# [5]
DDRB_SBS1# [5]
DDRB_SRAS# [5]
DDRB_SCS0# [5]
DDRB_ODT0 [5]
1
C92
2
1
C93
2
+VREF_CA
1
C852
2
1
C486
2
0.1U_0402_16V4Z
[5] DDRB_SBS0#
DDRB_SMA10
DDRB_SBS0#
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDRB_SDQ4
DDRB_SDQ5
0.1U_0402_16V4Z
[5] DDRB_CLK0
[5] DDRB_CLK0#
DDRB_CLK0
DDRB_CLK0#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
2
1
C844
2
DDRB_ODT1 [5]
+VREF_CA
DDRB_SDQ36
DDRB_SDQ37
1
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
C94
1000P_0402_50V7K
2
3
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQS5# [5]
DDRB_SDQS5 [5]
+1.5V
DDRB_SDQ46
DDRB_SDQ47
0.1U_0402_16V4Z
2
2
DDRB_SDQ52
DDRB_SDQ53
C846
0.1U_0402_16V4Z
2
2
C847
1
0.1U_0402_16V4Z
DDRB_SDM6
1
C851
1
0.1U_0402_16V4Z
2
C848
1
0.1U_0402_16V4Z
2
C854
1
0.1U_0402_16V4Z
C849
1
0.1U_0402_16V4Z
2
2
C842
1
0.1U_0402_16V4Z
C850
1
0.1U_0402_16V4Z
2
2
C845
C853
1
0.1U_0402_16V4Z
1
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
+0.75VS
+1.5V
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQS7# [5]
DDRB_SDQS7 [5]
2
DDRB_SDQ62
DDRB_SDQ63
PAD
0.1U_0402_16V4Z
2
C843
1
0.1U_0402_16V4Z
T11
1
C841
1
1
+
C925
2
4.7U_0603_6.3V6K
@
C86
330U_X_2VM_R6M
2
SB_SMDAT0 [8,19,21,28]
SB_SMCLK0 [8,19,21,28]
Place near DIMM2
+0.75VS
4
FOX_AS0A626-U8RN-7F
ME@
DIMM_B Reverse H:8mm
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Issued Date
Deciphered Date
2010/03/12
Title
DDRII SO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
C487
1000P_0402_50V7K
1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
4.7U_0805_10V4Z
DDRB_SDQ2
DDRB_SDQ3
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1000P_0402_50V7K
DDRB_SDM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
4.7U_0805_10V4Z
DDRB_SDQ0
DDRB_SDQ1
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
9
of
47
http://hobi-elektronika.net
A
B
PCIE_GTX_C_MRX_P[0..15]
[13] PCIE_GTX_C_MRX_P[0..15]
C
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
[13] PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15]
D
E
PCIE_MTX_C_GRX_P[0..15] [13]
PCIE_MTX_C_GRX_N[0..15] [13]
1
1
UMA HDMI
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
C489 1
2UMA@
C490 1
2UMA@
C500 1
2UMA@
C498 1
2UMA@
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
3
[20]
[20]
[20]
[20]
[20]
[20]
[20]
[20]
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
0.1U_0402_16V7K
2UMA@
0.1U_0402_16V7K
2UMA@
0.1U_0402_16V7K
2UMA@
0.1U_0402_16V7K
UMA_HDMI_P0
UMA_HDMI_N0
UMA_HDMI_P1
UMA_HDMI_N1
UMA_HDMI_P2
UMA_HDMI_N2
UMA_HDMI_P3
UMA_HDMI_N3
[26]
[26]
[26]
[26]
[26]
[26]
[26]
[26]
PART 2 OF 6
PCIE I/F GPP
PCIE I/F SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
AC8
AB8
R59
R58
C96
1
2DIS@
C98
1
2DIS@
C100 1
2DIS@
C102 1
2DIS@
C104 1
2DIS@
C106 1
2DIS@
C108 1
2DIS@
C110 1
2DIS@
C112 1
2DIS@
C114 1
2DIS@
C116 1
2DIS@
C118 1
2DIS@
C120 1
2DIS@
C122 1
2DIS@
C124 1
2DIS@
C126 1
2DIS@
C201 1
C200
1
C482 1
C481
1
C484 1
C483
1
C133
C134
C135
C136
C137
C138
C139
C140
1
1
1
1
1
1
1
1
1
1
2
2
C95 1
0.1U_0402_16V7K
C97 1
0.1U_0402_16V7K
C99 1
0.1U_0402_16V7K
C101 1
0.1U_0402_16V7K
C103 1
0.1U_0402_16V7K
C105 1
0.1U_0402_16V7K
C107 1
0.1U_0402_16V7K
C109 1
0.1U_0402_16V7K
C111 1
0.1U_0402_16V7K
C113 1
0.1U_0402_16V7K
C115 1
0.1U_0402_16V7K
C117 1
0.1U_0402_16V7K
C119 1
0.1U_0402_16V7K
C121 1
0.1U_0402_16V7K
C123 1
0.1U_0402_16V7K
C125 1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
2
3G@ 0.1U_0402_16V7K
2
2 3G@ 0.1U_0402_16V7K
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1.27K_0402_1%
2K_0402_1%
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
2DIS@
0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
[28]
[28]
[29]
[29]
[28]
[28]
[4] H_CADOP[0..15]
[4] H_CADON[0..15]
GLAN
WWAN
+1.1VS
RS880M_FCBGA528
RS880 A11(SA000032710)
H_CADIP[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
[4]
H_CADIN[0..15]
[4]
2
U3A
WLAN
[20]
[20]
[20]
[20]
[20]
[20]
[20]
[20]
H_CADOP[0..15]
H_CADON[0..15]
[4]
[4]
[4]
[4]
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
[4]
[4]
[4]
[4]
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1
R60
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2
HT_RXCALP
HT_RXCALN
M22
M23
R21
R20
C23
A24
301_0402_1%
Place within 1" layout 1:2
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HYPER TRANSPORT CPU I/F
[28]
[28]
[29]
[29]
[28]
[28]
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
PCIE I/F GFX
2
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
2UMA@
Cap close NB
U3B
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
C488 1
0.1U_0402_16V7K
C491 1
0.1U_0402_16V7K
C497 1
0.1U_0402_16V7K
C499 1
0.1U_0402_16V7K
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
H24
H25
L21
L20
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
B24
B25
HT_TXCALP
HT_TXCALN
3
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
[4]
[4]
[4]
[4]
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
[4]
[4]
[4]
[4]
R61
1
2
301_0402_1%
Place within 1" layout 1:2
RS880M_FCBGA528
RS880 A11(SA000032710)
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
RS880-HT/PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
10
of
47
C
D
2
2
2
C147
1U_0402_6.3V4Z
2
20mA
+VDDA18HTPLL
L7
2
FBMA-L11-160808-221LMT 0603
C150
2.2U_0603_6.3V4Z
1
1
2
2
C151
1U_0402_6.3V4Z
1
2
2
L9
1
2
GMCH_CRT_G
[25] GMCH_CRT_G
GMCH_CRT_B
[25] GMCH_CRT_B
1
R65
1
2
GMCH_CRT_R
[25] GMCH_CRT_R
2
FBMA-L11-160808-221LMT 0603
C154
2.2U_0603_6.3V4Z
C149
1U_0402_6.3V4Z
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
[12,25] GMCH_CRT_HSYNC
[12,25] GMCH_CRT_VSYNC
[25] GMCH_CRT_CLK
[25] GMCH_CRT_DATA
+VDDA18PCIEPLL
1
1
GMCH_CRT_R
1 UMA@ 2
R87 140_0402_1%
GMCH_CRT_G
1 UMA@ 2
R88 150_0402_1%
GMCH_CRT_B
1 UMA@ 2
R89 150_0402_1%
2
+1.8VS
4mA
+AVDDQ
2
FBMA-L11-160808-221LMT 0603
C148
2.2U_0603_6.3V4Z
20mA
+1.8VS
[20] NB_DISP_CLKP
[20] NB_DISP_CLKN
R536 1 EXT@
2 0_0402_5%
R456 1 INT@
R439 1 INT@
2 0_0402_5%
2 0_0402_5%
+1.1VS
+3VS
R77
3
1 EXT@ 2
R69
4.7K_0402_5%
GMCH_LCD_CLK
1
2 4.7K_0402_5%
R78
1
2 4.7K_0402_5% GMCH_LCD_DATA
R79
1
@
2 4.7K_0402_5%
R80
1
@
2 4.7K_0402_5% GMCH_CRT_DATA
1
1
2
R68
R66
R67
2 0_0402_5%
2
0_0402_5%
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
G18
G17
E18
F18
E19
F19
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
1
300_0402_5%
[19] CLK_NBHT
[19] CLK_NBHT#
1 EXT@ 2
R70
4.7K_0402_5%
[19] CLK_NBGFX
[19] CLK_NBGFX#
CLK_NBHT
CLK_NBHT#
CLK_NBGFX
CLK_NBGFX#
2 INT@ 1
R504 2 INT@4.7K_0402_5%
1
R506
4.7K_0402_5%
CLK_SBLINK_BCLK
[19] CLK_SBLINK_BCLK
CLK_SBLINK_BCLK#
[19] CLK_SBLINK_BCLK#
GMCH_HDMI_CLK R641 1 UMA@ 2 0_0402_5%
GMCH_HDMI_DATA R640 1 UMA@ 2 0_0402_5%
[45] POWER_SEL
D7
E7
C25
C24
E11
F11
CLK_NBGFX
USE INT CLK GEN. PD 4.7k PD.
[27] GMCH_LCD_CLK
[27] GMCH_LCD_DATA
H17
NB_RESET#
D8
NB_PWRGD_R A10
NB_LDTSTOP#
C10
NB_ALLOW_LDTSTOP C12
NB_REFCLK_P
NB_REFCLK_N
GMCH_CRT_CLK
[26] GMCH_HDMI_CLK
[26] GMCH_HDMI_DATA
E17
F17
F15
120mA
+VDDA18PCIEPLL
[19] CLK_NB_14.318M
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
DAC_RSET 10mil G14
2
715_0402_1%
65mA
+NB_PLLVDD
A12
+NB_HTPVDD 20mA
D14
B12
+VDDA18HTPLL
[12,13,20,28,29,34] PLT_RST#
[21] NB_PWRGD
T2
T1
U1
U2
V4
V3
GMCH_LCD_CLK
GMCH_LCD_DATA
B9
A9
B8
A8
GMCH_HDMI_CLK_R1
B7
GMCH_HDMI_DATA_R1 A7
POWER_SEL
R82 2
1
2K_0402_5%
B10
G11
EMI
1
@
1
CLK_NB_14.318M
R86
2
100_0402_5%
@ C158
1
2
2
5
A
P
1
Y
4NB_PWRGD_R
@
1
2
0_0402_5%
U3C
F12
E12
F14
G15
H15
H14
+NB_PLLVDD
+NB_HTPVDD
C155
1U_0402_6.3V4Z
[6,21,34] SB_PWRGD
U4
NC7SZ08P5X_NL_SC70-5
AMD suggest
1
+1.8VS
1
1
@
+AVDDDI
2
L6
+1.8VS
NB_LDTSTOP#
4
U8
R85 2
150_0402_1%
C8
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
A22
B22
A21
B21
B20
A20
A19
B19
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
PART 3 OF 6
DAC_RSET(PWM_GPIO1)
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL
VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
A15
B15
A14
B14
GMCH_TXOUT0+ [27]
GMCH_TXOUT0- [27]
GMCH_TXOUT1+ [27]
GMCH_TXOUT1- [27]
GMCH_TXOUT2+ [27]
GMCH_TXOUT2- [27]
L8
+VDDLTP18
1
C152
1U_0402_6.3V4Z
GMCH_TXCLK+ [27]
GMCH_TXCLK- [27]
15mA
MIS.
C156
0.1U_0402_16V4Z
+VDDLT18
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
STRP_DATA
RSVD
TESTMODE
+1.8VS
1
L10
1
2
BLM18AG601SN1D_2P
1
2
+1.8VS
C157
4.7U_0805_10V4Z
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
DIS@
1
[14] VGA_ENBKL
R74 @
4.7K_0402_5%
2
R102
0_0402_5%
D12
1
3
R81
2 0_0402_5%
AE8
AD8
D13
AUX_CAL(NC)
ENBKL [34]
R75 2
1
4.7K_0402_5%
1 UMA@ 2
R642 0_0402_5%
D9
D10
GMCH_ENVDD [27]
GMCH_INVT_PWM [27]
ENBKL
R76 1 UMA@ 2 0_0402_5%
R73 @
4.7K_0402_5%
TMDS_HPD(NC)
HPD(NC)
2
2
FBMA-L11-160808-221LMT 0603
C153
2.2U_0603_6.3V4Z
+VDDLT18
2
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
+VDDLTP18
300mA
2
1
1
2
1
1
1
1
R64
125mA
1
Y
A
B
NC7SZ08P5X_NL_SC70-5
CRT/TVOUT
1
FBMA-L11-160808-221LMT 0603
C145
0.1U_0402_16V4Z
2
FBMA-L11-160808-221LMT 0603
C146
2.2U_0603_6.3V4Z
B
L4
+NB_HTPVDD
L5
1
1
[6,20] LDT_STOP#
2.2U_0603_6.3V4Z
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V4Z
+1.8VS
+1.8VS
C143
1
2
3
1
FBMA-L11-160808-221LMT 0603
C144
1
PLL PWR
LVTM
2
C679
1
PM
2
L3
C142
1U_0402_6.3V4Z
NB_PWRGD
G
+3VS
1
CLOCKs
1
1
2
+AVDD1
FBMA-L11-160808-221LMT 0603
C141
2.2U_0603_6.3V4Z
C684
1
2
+1.8VS
R63
2.2K_0402_5%
3
+NB_PLLVDD
L2
1
+1.8VS
1
R417
@
300_0402_5%
E
2
2
+1.1VS
+1.8VS
0.1U_0402_16V4Z
1
2
5
2
+1.8VS
P
B
G
A
HDMI_DET [14,26]
To SB
SUS_STAT# [21]
SUS_STAT_R# [12]
Strap pin
1
2
R84
1.8K_0402_5%
RS880M_FCBGA528
100P_0402_25V8K
RS880 A11(SA000032710)
1
+1.8VS
2
R90
1K_0402_5%
[20] ALLOW_LDTSTOP
R91
1
0_0402_5%
NB_ALLOW_LDTSTOP
2
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
RS880 VEDIO/CLK GEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
11
of
47
A
B
C174
1
C177
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
1
C178
2
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
L15
2
1
FBMA-L11-201209-221LMA30T_0805
1
C181
4.7U_0805_10V4Z
C176
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE
1
C179
2
1
C192
1
C185
1
C190
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
700mA
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
1
C186
2
0.1U_0402_16V4Z
10mA
F9
G9
AE11
AD11
+1.8VS
5mA
C197
1U_0402_6.3V4Z
1
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
NB core voltage of 1.25V is required
in order to support 590 MHz engine speed For ACF
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
AE10
AA11
Y11
AD10
AB10
AC10
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
H11
H12
VDD33_1(NC)
VDD33_2(NC)
POWER_SEL
UMA
DIS
0.95V
0.95V
1.1V
1.25V
HIGH
LOW
1
2
23mA
12A
1
2
1
2
1
2
1
2
1
2
1
2
1
2
+NB_CORE
1
1
2
2
1
1
2
+
2
330U_D2E_2.5VM
2
C175
1
C189
+1.8VS
1
C196
1
C184
2
10U_0805_10V4Z
@
C261
680mA
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX
10U_0603_6.3V6M
2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
C195
1
1
1
C172
C173
10U_0805_10V4Z
L14
2
+1.1VS
FBMA-L11-201209-221LMA30T_0805
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
C183
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
2 4.7U_0805_10V4Z
1
1
C188
H18
G19
F20
E21
D22
B23
A23
1
C168
C171
0.1U_0402_16V4Z
700mA
C161
C163
C180
C170
1
2 10U_0805_10V4Z
2 10U_0805_10V4Z
0.1U_0402_16V4Z
C169
1
+1.1VS
1
1
C194
C164
1
U3F
C160
C162
0.1U_0402_16V4Z
1
+VDDA11PCIE
C193
+VDDHTRX
0.1U_0402_16V4Z
1
2.5A
0.1U_0402_16V4Z
2
FBMA-L11-201209-221LMA30T_0805
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
C187
1U_0402_6.3V4Z
PART 5/6
0.1U_0402_16V4Z
L13
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
C182
U3E
J17
K16
L16
M16
P16
R16
T16
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
1
C191
2
4.7U_0805_10V4Z
C167
L28
1
2
FBMA-L11-201209-221LMA30T_0805
L12
1
2
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
C159
1
0.1U_0402_16V4Z
C166
1
600mA
C165
1
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
60mA
RS880 A11(SA000032710)
C198
0.1U_0402_16V4Z
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
1
2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS880M_FCBGA528
+3VS
1
RS880M_FCBGA528
PART 6/6
GROUND
+VDDHT
1
E
1U_0402_6.3V4Z
1
FBMA-L11-201209-221LMA30T_0805
POWER
2
D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L11
1.3A
+1.1VS
C
RS880 A11(SA000032710)
1
C199
2
2
0.1U_0402_16V4Z
2
U3D
3
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Debug Mode
2
R92
2
R93
1
3K_0402_5%
1
3K_0402_5%
@
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable
0 : Enable
+3VS
DFT_GPIO1: LOAD_EEPROM_STRAPS
Load EEPROM Strap
D1 @
CH751H-40PT_SOD323-2
2
1
[11] SUS_STAT_R#
2
R264 @
AD16
AE17
AD17
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
PLT_RST# [11,13,20,28,29,34]
W12
Y12
AD18
AB13
AB18
V14
1
3K_0402_5%
V15
W14
Enable Side Port Memory
Enable Side Port Memory
4
[11,25] GMCH_CRT_HSYNC
2
R94
2
R95
@
1
3K_0402_5%
1
3K_0402_5%
RS880: HSYNC#
0:
Enable
1 : Disable
+3VS
AE12
AD12
Register Readback of strap:
NB_CLKCFG:CLK_TOP_SPARE_D[1]
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
MEM_CKP(NC)
MEM_CKN(NC)
IOPLLVSS(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
MEM_VREF(NC)
C
W17
AE19
AE23
AE24
AD23
15mA
26mA
+1.8VS
+1.1VS
4
AE18
Compal Electronics, Inc.
Compal Secret Data
2008/10/06
2010/03/12
Deciphered Date
Title
RS880 PWR/GND
Date:
B
Y17
W18
AD20
AE21
RS880 A11(SA000032710)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
RS880M_FCBGA528
Security Classification
Issued Date
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
SBD_MEM/DVO_I/F
Side port and Strap setting
[11,25] GMCH_CRT_VSYNC
3
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
12
of
47
5
4
3
PCIE LANE REVERSAL
D
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
AF30
AE31
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
AH30
AG31
PCIE_GTX_MRX_P15 C269
0.1U_0402_10V7K
DIS@
1
2
PCIE_GTX_MRX_N15
DIS@
1
2
C270 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
AE29
AD28
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
AG29
AF28
PCIE_GTX_MRX_P14 C267
0.1U_0402_10V7K
DIS@
1
2
PCIE_GTX_MRX_N14
DIS@
1
2
C268 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
AD30
AC31
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
AF27
AF26
PCIE_GTX_MRX_P13 C265
0.1U_0402_10V7K
DIS@
1
2
PCIE_GTX_MRX_N13
DIS@
1
2
C266 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
AC29
AB28
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
AD27
AD26
PCIE_GTX_MRX_P12 C494
0.1U_0402_10V7K
DIS@
1
2
PCIE_GTX_MRX_N12
DIS@
1
2
C264 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
AB30
AA31
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
AC25
AB25
PCIE_GTX_MRX_P11 C262
0.1U_0402_10V7K
DIS@
1
2
PCIE_GTX_MRX_N11
DIS@
1
2
C263 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
AA29
Y28
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
Y23
Y24
PCIE_GTX_MRX_P10 C259
0.1U_0402_10V7K
DIS@
1
2
PCIE_GTX_MRX_N10
DIS@
1
2
C260 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
Y30
W31
PCIE_TX6P
PCIE_TX6N
AB27
AB26
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
C257
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C258 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_TX7P
PCIE_TX7N
Y27
Y26
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
C255
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C256 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_TX8P
PCIE_TX8N
W24
W23
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
C253
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C254 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_TX9P
PCIE_TX9N
V27
U26
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
C251
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C252 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_TX10P
PCIE_TX10N
U24
U23
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
C249
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C250 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_TX11P
PCIE_TX11N
T26
T27
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
C247
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C248 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_TX12P
PCIE_TX12N
T24
T23
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
C245
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C246 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_RX6P
PCIE_RX6N
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
W29
V28
PCIE_RX7P
PCIE_RX7N
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
V30
U31
PCIE_RX8P
PCIE_RX8N
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
U29
T28
PCIE_RX9P
PCIE_RX9N
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
T30
R31
PCIE_RX10P
PCIE_RX10N
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
R29
P28
PCIE_RX11P
PCIE_RX11N
PCI EXPRESS INTERFACE
C
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
[10] PCIE_MTX_C_GRX_P[0..15]
[10] PCIE_MTX_C_GRX_N[0..15]
U6A
2
PCIE_RX12P
PCIE_RX12N
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
N29
M28
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
P27
P26
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
C243
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C244 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
M30
L31
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
P24
P23
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
C241
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C242 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
L29
K30
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
M27
N26
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
C239
0.1U_0402_10V7K
DIS@
1
2
DIS@
1
2
C240 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
T26 PAD
PCIE_GTX_C_MRX_P[0..15] [10]
PCIE_GTX_C_MRX_N[0..15] [10]
D
R103
@
1
2
10K_0402_5%
LVDS CONTROL
P30
N31
[19] CLK_PEG_VGA
[19] CLK_PEG_VGA#
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
U6F
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
B
1
VARY_BL
DIGON
AB11
AB12
VGA_PNL_PWM [27]
VGA_ENVDD [27]
1 @
2
R104
10K_0402_5%
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AH20
AJ19
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AL21
AK20
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AH22
AJ21
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AL23
AK22
TXOUT_U3P
TXOUT_U3N
AK24
AJ23
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AL15
AK14
VGA_TXCLK+ [27]
VGA_TXCLK- [27]
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AH16
AJ15
VGA_TXOUT0+ [27]
VGA_TXOUT0- [27]
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AL17
AK16
VGA_TXOUT1+ [27]
VGA_TXOUT1- [27]
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AH18
AJ17
VGA_TXOUT2+ [27]
VGA_TXOUT2- [27]
TXOUT_L3P
TXOUT_L3N
AL19
AK18
C
LVTMDP
B
Park-S3
DIS@
CLOCK
AK30
AK32
PCIE_REFCLKP
PCIE_REFCLKN
T25 PAD
CALIBRATION
R108 2 DIS@
110K_0402_5% N10
PWRGOOD
PCIE_CALRP
Y22 1.27K_0402_1% 1 DIS@
2 R107
PCIE_CALRN
AA22
2K_0402_5% 1 DIS@
2 R109
+VGA_PCIE
A
A
[11,12,20,28,29,34]
AL27
PLT_RST#
PERSTB
Park-S3
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
DIS@
2008/10/06
Deciphered Date
2009/10/06
Title
PARK-S3 PCIE/LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.2
NAWE6 LA-5754P
Date:
5
4
3
2
Tuesday, March 02, 2010
Sheet
1
13
of
47
5
4
3
Transmitter Power Saving Enable
GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
TX_DEEMPH_EN
PCI Express Transmitter De-emphasis Enable
GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)
U6B
TX3P_DPB2P
TX3M_DPB2N
DPB
TX4P_DPB1P
TX4M_DPB1N
VGA_HDMI_TXD0+ [26]
VGA_HDMI_TXD0- [26]
AH3
AH1
VGA_HDMI_TXD1+ [26]
VGA_HDMI_TXD1- [26]
AK3
AK1
VGA_HDMI_TXD2+ [26]
VGA_HDMI_TXD2- [26]
DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17
DVPDATA_7 / TX0P_DPC2P
DVPDATA_1 / TX0M_DPC2N
DPC_VSSR#1 / DVPCLK
DPC_VSSR#2 / DVPDAT5
DPC_VSSR#3 / GND
DPC_VSSR#4 / GND
DPC_VSSR#5/ DVPCNTL_MV0
DVPDATA_13 / TX2P_DPC0P
DVPCNTL_1 / TX2M_DPC0N
VDDR4 / DPCD_CALR
PCIE TRANSMITTER DE-EMPHASIS ENABLED
1
BIF_GEN2_EN_A
GPIO2
PCIE GNE2 ENABLED
0
AK6
AM5
+3VSG
STRAPS
AJ7
AH6
GPU_GPIO0
GPU_GPIO1
R111
R112
GPU_GPIO2
R113
GPU_GPIO8
GPU_GPIO9
R114
R115
@
2
2 DIS@
BIF_VGA DIS
GPIO9
1 10K_0402_5%
1 10K_0402_5%
2
@
1 10K_0402_5%
2
2
@
@
1 10K_0402_5%
1 10K_0402_5%
W3
V2
Y4
W5
AA3
Y2
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
R117
R118
R119
2 DIS@
@
2
@
2
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_VSYNC2
VGA_CRT_HSYNC2
R120
R121
R122
R123
2
2
2
2
ROMIDCFG(2:0)
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
VB
DIS@
DIS@
@
@
1
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
AUD[1]
HSYNC
AUD[0]
VSYNC
A2VDDQ / NC
VREFG
AF14
AE14
DDC/AUX
300mA
AD14
+DPLL_VDDC
27MCLK
XTALOUT
AM28
AK28
AC22
AB22
DPLL_VDDC
AUX2P
AUX2N
DDCCLK_AUX5P
DDCDATA_AUX5N
NC#2/XO_IN
NC#1/XO_IN2
Suggest connect to GND by AMD
R152
DIS@
1
GPU_THERMAL_D+
GPU_THERMAL_D-
T4
T2
AUX1P
AUX1N
DDC2CLK
DDC2DATA
XTALIN
XTALOUT
2
2
C287
2
R129
R127
R130
R151
0.1U_0402_10V6K
C286
1U_0402_6.3V4Z
DIS@
1
+A2VDD
DIS@
1
+A2VDDQ
DIS@
1
C293
DIS@
1
C292
C285
C284
1U_0402_6.3V4Z
0.1U_0402_10V6K
L21
2
1
BLM15BD121SN1D_0402
DIS@
2
2
C306
DIS@
18P_0402_50V8J
+TSVDD
20mA
R5
AD17
AC17
@
@
@
@
2
2
2
2
R131 1
R132 1
R133 1
@
@
@
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
R136 1
@
2 10K_0402_5%
GPIO28_TDO
R138 2 DIS@
R139 2 DIS@
1 4.7K_0402_5%
1 4.7K_0402_5%
VGA_LCD_DAT
VGA_LCD_CLK
R140 2
R142 2
1 10K_0402_5%
1 10K_0402_5%
DIS@
DIS@
VGA_CRT_CLK
VGA_CRT_DATA
DDC6CLK
DDC6DATA
NC/DDCCLK_AUX3P
NC/DDCDATA_AUX3N
2
R143
10K_0402_5%
DIS@
VGA_SMB_CK2_R
AG13
AE6
AE5
VGA_CRT_B
1
6
Q7A
2N7002DW-T/R7_SOT363-6
DIS@
VGA_SMB_DA2_R
AE19
VGA_CRT_G
R144
10K_0402_5%
DIS@
4
AD13
AD11
AE16
AD16
AC1
AC3
EC_SMB_CK2
[6,31,34]
EC_SMB_DA2
[6,31,34]
DIS@ DIS@ DIS@
Q7B
DIS@
2N7002DW-T/R7_SOT363-6
1 R150
2 DIS@
715_0402_1%
VGA_CRT_CLK
VGA_CRT_DATA
VGA_CRT_CLK [25]
VGA_CRT_DATA [25]
+3VSG
AD2
AD4
AC11
AC13
3
R145 1
2
150_0402_1%
+A2VDDQ
2
+VDD2DI
DIS@
1
R148 1
2
150_0402_1%
+A2VDD
DIS@
1
1
DIS@
1
R147 1
2
150_0402_1%
1.5mA
AE17
2
1
BLM15BD121SN1D_0402
DIS@
2
C301
@
0.1U_0402_16V4Z
VGA_HDMI_SCLK [26]
VGA_HDMI_SDATA [26]
+VGA_PCIE
L26
BLM18AG121SN1D_0603
+TSVDD
2
1
DIS@
1
1
AD20
AC20
2
DIS@
2
DIS@
1
2
DIS@
VGA Thermal Sensor
ADM1032 Closed to GPU
2
1
+DPLL_VDDC
L25
2
1
BLM15BD121SN1D_0402
DIS@
+1.8VSG
DPLUS
DMINUS
TS_FDO
TSVDD
TSVSS
U7
1
DIS@
1
2
DIS@
1
2
DIS@
1
2
GPU_THERMAL_D+
2
1
2
@ C304
2200P_0402_50V7K
GPU_THERMAL_D-
3
+3VSG
1 R643 @2
4.7K_0402_5%
VB
1111_100xb
4
Issued Date
2008/10/06
Deciphered Date
SDATA
D-
ALERT#
THERM#
2
GND
8
VGA_SMB_CK2_R
7
VGA_SMB_DA2_R
6
THM_ALERT#
5
A
2 R155 @1
4.7K_0402_5%
+3VSG
EMC1412-A (SA00003YA0L)
Address 1111_100xb
S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
Compal Electronics, Inc.
2009/10/06
Title
PARK-S3 Main Generic/MSIC
Size
C
Date:
3
SCLK
D+
EMC1402-2-ACZL-TR MSOP 8P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DIS@
@
VDD
Compal Secret Data
Security Classification
4
GPU_GPIO3
GPU_GPIO4
GPU_VID0
GPU_VID1
5
AE20
+1.8VSG
+VDD2DI
Park-S3
5
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3VSG
27MHZ_16PF_X5H027000FG1H
C307
DIS@
18P_0402_50V8J
1
1
1
1
+3VSG
L23
C310
0.1U_0402_16V4Z
Y1
DDC1CLK
DDC1DATA
DPLL_PVDD
DPLL_PVSS
THERMAL
2
AD19
AC19
M92-S2/M93-S3
PLL/CLOCK
120mA
2
+1.8VSG
2
HPD1
M92-S2/M93-S3
+DPLL_PVDD
+VDD1DI
DIS@
1
DIS@
1
B
VGA_CRT_HSYNC2
VGA_CRT_VSYNC2
AL13
AJ13
50mA
VDD2DI / NC
VSS2DI / NC
R2SET / NC
2
2
2
C305
H2SYNC
V2SYNC
C309
1U_0402_6.3V4Z
27MCLK
AH12
AM10
AJ9
C308
10U_0603_6.3V6M
DIS@
1M_0603_5%
C / NC
Y / NC
COMP / NC
DIS@
1
DIS@
1
VGA_CRT_R
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DIS@
0.1U_0402_10V6K
DIS@
0_0402_5% 1
R62 2
0_0402_5% 1
R105 2
DIS@
XTALOUT
AK10
AL9
DIS@
1
2
0.1U_0402_10V6K
1
XTALIN
Voltage Swing: 1.8 V
A
AC16
L22
2
1
BLM15BD121SN1D_0402
DIS@
2
+AVDD
DIS@
1
C303
C297
1
+DPLL_PVDD
L24
1U_0402_6.3V4Z
2
1
BLM15BD121SN1D_0402
1
1
1
C298
C299
C300
DIS@
DIS@
DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
DIS@
2
2
2
+1.8VSG
2
DAC2
A2VSSQ
R272
249_0402_1%
DIS@
2
+1.8VSG
AM12
AK12
130mA
+VREFG_GPU
2
DIS@
1
0.1U_0402_10V6K
B2 / NC
B2B / NC
A2VDD / NC
0.60 V level
+VDD1DI
AL11
AJ11
2
1
BLM15BD121SN1D_0402
DIS@
+3VSG
DIS@
1
C290
G2 / NC
G2B / NC
+1.8VSG
DIS@
1 R146
2
499_0402_1%
L20
2
1
BLM15BD121SN1D_0402
DIS@
M92-S2/M93-S3
R2 / NC
R2B / NC
+3VSG
L19
1U_0402_6.3V4Z
AC14
HDMI_DET
+1.8VSG
GENERICC
GPIO21_BB_EN
[25]
[25]
C302
[11,26]
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN
[25]
10U_0603_6.3V6M
AB13
W8
W9
W7
AD10
11
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
0.1U_0402_10V6K
[15] TEST_EN
L6
L5
L3
L1
K4
AF24
1 R126
2 DIS@
70mA499_0402_1%
+AVDD
AG24
AE22
45mA
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
AD22
AE23
AD23
[25]
C296
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
TEST_EN
VGA_CRT_HSYNC
VGA_CRT_VSYNC
AH26
AJ27
VGA_CRT_G
C283
AVDD
AVSSQ
VDD1DI
VSS1DI
AH24
AG25
VGA_CRT_B
0.1U_0402_10V6K
1
R141
10K_0402_5%
DIS@
B
RSET
TEST_EN
2
R137 1 @
2
10K_0402_5%
+3VSG
HSYNC
VSYNC
VGA_CRT_G
[25]
C289
[44] GPU_VID1
GPIO26_TCK
[19] 27M_NSSC
B
BB
DAC1
AL25
AJ25
VGA_CRT_R
1U_0402_6.3V4Z
GPIO27_TMS
G
GB
VGA_CRT_R
C295
+3VSG
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
AM26
AK26
1U_0402_6.3V4Z
@
1 R135
2
10K_0402_5%
GPU_VID0
T12
THM_ALERT#
R134 10K_0402_5%
@
1
2
GPU_VID1
[44] GPU_VID0
0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
H2SYNC
R
RB
10U_0603_6.3V6M
@
R149
1
2 GPIO24_TRSTB
10K_0402_5%
0
I2C
C288
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
0
AMD RESERVED CONFIGURATION STRAPS
10U_0603_6.3V6M
GPU_GPIO8
GPU_GPIO9
IGNORE VIP DEVICE STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
C294
[11] VGA_ENBKL
001
V2SYNC
GENERICC
R124
150_0402_1%
DIS@
10U_0603_6.3V6M
[34,39]
U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
C
SCL
SDA
GENERAL PURPOSE I/O
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
@
1 R125
2
10K_0402_5%
RB751V_SOD323 D4
1
2
ACIN
@
+3VSG
0
GPIO[13:11]
H2SYNC
2
VGA_LCD_CLK R1
VGA_LCD_DAT R3
[27] VGA_LCD_CLK
[27] VGA_LCD_DAT
0
AA12
DPC
C
0
ENABLE EXTERNAL BIOS ROM
GPIO_22_ROMCSB
VIP_DEVICE_STRAP_ENA
V4
U5
VGA ENABLED
GPIO21
BIOS_ROM_EN
AK8
AL7
D
0
1U_0402_6.3V4Z
U1
W1
U3
Y6
AA1
GPIO1
GPIO8
M92-S2/M93-S3
DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N
0
TX_DEEMPH_EN
2
AA5
AA6
DPC_VDD18#1/DVPDAT10
DPC_VDD18#2/DVPDAT23
RECOMMENDED SETTINGS
PCIE FULL TX OUTPUT SWING
C282
AC6
AC5
DPC_PVDD / DVPDATA_11
DPC_PVSS / GND
DESCRIPTION OF DEFAULT SETTINGS
GPIO0
AK5
AM3
M93-S3/M92-S2
W6
V6
PIN
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
TX_PWRS_ENB
10U_0603_6.3V6M
C281
2
TXCBP_DPB3P
TXCBM_DPB3N
DVPCNTL_MV1 / TX1P_DPC1P
DVPDATA_9 / TX1M_DPC1N
0.1U_0402_10V6K
2
1U_0402_6.3V4Z
C280
C279
2
TX2P_DPA0P
TX2M_DPA0N
STRAPS
VGA_HDMI_TXC+ [26]
VGA_HDMI_TXC- [26]
AG3
AG5
C291
+DPC_PVDD
+DPC_PVDD
DIS@
1
20mA
DIS@
1
TX1P_DPA1P
TX1M_DPA1N
TX5P_DPB0P
TX5M_DPB0N
+DPC_VDD10
DIS@
1
10U_0603_6.3V6M
L18
2
1
BLM15BD121SN1D_0402
DIS@
TX0P_DPA2P
TX0M_DPA2N
DPA
DVO
+DPC_VDD18
+1.8VSG
TXCAP_DPA3P
TXCAM_DPA3N
10U_0603_6.3V6M
2
DVCNTL_0/ DVPDATA_18
DVCNTL_1 / NC
DVCNTL_2 / TESTEN#2
DVDATA_12 / DVPDATA_16
DVDATA_11 / DVPDATA_20
DVDATA_10 / DVPDATA_22
DVDATA_9 / DVPDATA_12
DVDATA_8 / DVPDATA_14
DVDATA_7 / DVPCNTL_0
DVDATA_6 / DVPDATA_8
DVDATA_5 / DVPDATA_6
DVDATA_4 DVPDATA_4
DVDATA_3 / DVPDATA_19
DVDATA_2 / DVPDATA_21
DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0
AF2
AF4
1
2
C278
C274
DIS@
1
1U_0402_6.3V4Z
2
10U_0603_6.3V6M
C277
DIS@
1
VRAM_ID2
VRAM_ID1
VRAM_ID0
[15] VRAM_ID2
[15] VRAM_ID1
[15] VRAM_ID0
+DPC_VDD10
DIS@
1
200mA
AE9
L9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
1
C275
2
+VGA_PCIE
L16
2
1
BLM15BD121SN1D_0402
DIS@
0.1U_0402_10V6K
C272
2
0.1U_0402_10V6K
2
D
+DPC_VDD18
DIS@
1
130mA
DIS@
1
1U_0402_6.3V4Z
C271
DIS@
1
10U_0603_6.3V6M
2
1
BLM15BD121SN1D_0402
DIS@
+1.8VSG
M93-S3/M92-S2
1
CONFIGURATION STRAPS
2
L17
2
TX_PWRS_ENB
Document Number
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
1
14
of
47
5
4
3
2
1
U6C
[18] M_DQS[7..0]
M_DQS#[7..0]
[18] M_DQS#[7..0]
D
C
1
+1.5VSG
MVREFSA
1
2
R165
DIS@
40.2_0402_1%
+1.5VSG
1
2
R166
DIS@
100_0402_1%
C312
0.1U_0402_16V4Z
2
DIS@
R163
DIS@
40.2_0402_1%
MVREFDA
1
2
B
1
2
R164
DIS@
100_0402_1%
1
2
C311
0.1U_0402_16V4Z
DIS@
+1.5VSG
MVREFDA
MVREFSA
240_0402_1%1 DIS@
R170 1 DIS@ 2 0_0402_5%
[14] TEST_EN
R171 1 DIS@
R172 1 DIS@
1
1
A
R174
C314DIS@
DIS@ 2 51.1_0402_1%
1
2
1
DIS@ 51.1_0402_1%
DIS@
R175
C315
2 R168
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_BA2
M_BA0
M_BA1
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
E32
E30
A21
C21
E13
D12
E3
F4
M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM4
M_DQM5
M_DQM6
M_DQM7
RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7
H28
C27
A23
E19
E15
D10
D6
G5
M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7
WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7
H27
A27
C23
C19
C15
E9
C5
H4
M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7
ODTA0
ODTA1
L18
K16
M_ODT0
M_ODT1
CLKA0
CLKA0B
H26
H25
M_CLK0
M_CLK#0
CLKA1
CLKA1B
G9
H9
M_CLK1
M_CLK#1
RASA0B
RASA1B
G22
G17
M_RAS#0
M_RAS#1
CASA0B
CASA1B
G19
G16
M_CAS#0
M_CAS#1
CSA0B_0
CSA0B_1
H22
J22
M_CS#0
CSA1B_0
CSA1B_1
G13
K13
M_CS#1
K26
J26
MVREFDA
MVREFSA
CKEA0
CKEA1
K20
J17
M_CKE0
M_CKE1
J25
K7
MEM_CALRN0
NC/TESTEN#2
WEA0B
WEA1B
G25
H10
M_WE#0
M_WE#1
MEM_CALRP1/DPC_CALR
MEM_CALRP0
PX_EN
AB16
2 150_0402_1% J8
2 240_0402_1%K25
+1.8VSG
R157
R158
R159
R160
R161
R162
1
1
1
1
1
1
2
2
2
2
2
2
H@
S@
S@
H@
@
DIS@
VRAM_ID0
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
VRAM_ID0 [14]
VRAM_ID1
VRAM_ID1 [14]
VRAM_ID2
VRAM_ID2 [14]
D
VB
M_BA2 [18]
M_BA0 [18]
M_BA1 [18]
Vendor
Hynix
VRAM_ID0
VRAM_ID1
VRAM_ID2
H5TQ1G63BFR-12C
1
0
0
Samsung K4W1G1646E-HC12
0
1
0
C
M_ODT0 [18]
M_ODT1 [18]
M_CLK0 [18]
M_CLK#0 [18]
M_CLK1 [18]
M_CLK#1 [18]
M_RAS#0 [18]
M_RAS#1 [18]
B
M_CAS#0 [18]
M_CAS#1 [18]
+VGA_CORE
M_CS#0 [18]
1
M_DQS[7..0]
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
M_CS#1 [18]
R167
2.2K_0402_5%
@
M_CKE0 [18]
M_CKE1 [18]
R169 DIS@
51.1_0402_1%
1
2
DRAM_RST
M_WE#0 [18]
M_WE#1 [18]
2
[18] M_DQM[7..0]
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
DRAM_RST# [18]
1
M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63
M_DQM[7..0]
DRAM_RST L10
DRAM_RST
20.1U_0402_16V4Z K8
L7
2
0.1U_0402_16V4Z
CLKTESTA
CLKTESTB
1
R273
10K_0402_5%
RSVD#2
G14
RSVD#3
G20
2
M_MA[13..0]
MEMORY INTERFACE
M_DA[63..0]
[18] M_DA[63..0]
[18] M_MA[13..0]
2
DIS@
C313
68P_0402_50V8J
DIS@
M_MA13
A
Park-S3
DIS@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2009/10/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PARK-S3 MEM Interface
Document Number
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
1
15
of
47
5
4
DPE_VDD10
DPF_VDD10
3
2
1
Park-S3: TMDS/DP=110mA@1.0V : LVDS=120mA@1.0V
D
D
U6G
+1.8VSG
+1.8VSG
DP E/F POWER
200mA
L54 DIS@
2
1
BLM15BD121SN1D_0402
1
1
1
C316
C320
C321DIS@
DIS@
DIS@
0.1U_0402_10V6K
10U_0603_6.3V6M
2
2
2
+VGA_PCIE
1U_0402_6.3V4Z
+DPE_VDD18
AG15
AG16
DP A/B POWER
DPE_VDD18#1
DPE_VDD18#2
130mA
DPA_VDD18#1
DPA_VDD18#2
AE11
AF11
AG14
AH14
AM14
AM16
AM18
AE1
AE3
AG1
AG6
AH5
C330DIS@
10U_0603_6.3V6M
2
2
0.1U_0402_10V6K
0.11A
L55 DIS@
2
1
BLM15BD121SN1D_0402
1
1
1
C502
C503
C501DIS@
DIS@
DIS@
0.1U_0402_10V6K
10U_0603_6.3V6M
2
2
2
+VGA_PCIE
1U_0402_6.3V4Z
L49
DIS@
1
2
MBK1608121YZF_0603
C506
C5041
DIS@ 1
1
C505DIS@
DIS@
1U_0402_6.3V4Z
10U_0603_6.3V6M
2
DIS@
MBK1608121YZF_0603
AF16
AG17
DPF_VDD18#1
DPF_VDD18#2
DPB_VDD18#1
DPB_VDD18#2
AE13
AF13
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
AF10
AG9
AH8
AM6
AM8
AF17
DPEF_CALR
DPAB_CALR
AE10
DIS@
C331
1
DIS@
2
DIS@
1
2
C333
AF23
AG23
AM20
AM22
AM24
+VPB_VDD10
1U_0402_6.3V4Z
DPB_VDD10#1
DPB_VDD10#2
1
+VGA_PCIE
L32
C332
DPF_VDD10#1
DPF_VDD10#2
AF8
AF9
1
2
1
+1.8VSG
+DPB_VDD18
10U_0603_6.3V6M
+DPF_VDD10
AF22
AG22
1
C327
DIS@
0.1U_0402_10V6K
130mA
2
1
BLM15BD121SN1D_0402
DIS@
2
BLM15BD121SN1D_0402
1
2
DIS@ L30
1
1
C
C326
DIS@
C325
DIS@
2
2 10U_0603_6.3V6M
1U_0402_6.3V4Z
2
2
0.1U_0402_10V6K
R176 DIS@
2
1
150_0402_1%
L33
DIS@
DIS@ 1 R177
2
150_0402_1%
+1.8VSG
0.02A
DPF_PVDD
DPF_PVSS
20mA
20mA
20mA
DPA_PVDD
DPA_PVSS
AG8
AG7
DPB_PVDD
DPB_PVSS
AG10
AG11
+DPA_PVDD
DIS@
DIS@
+DPF_PVDD
1
2
DIS@
1
2
C339
AG19
AF20
DP PLL POWER
20mA
C337
DPE_PVDD
DPE_PVSS
1U_0402_6.3V4Z
AG18
AF19
10U_0603_6.3V6M
+DPE_PVDD
1
2
Park-S3 DIS@
2
1
BLM15BD121SN1D_0402
DIS@
B
+1.8VSG
0.02A
2
DIS@
1
2
C342
C341
1
10U_0603_6.3V6M
C340
DIS@
1U_0402_6.3V4Z
+DPB_PVDD
DIS@
L35
2
1
BLM15BD121SN1D_0402
DIS@
1
2
0.1U_0402_10V6K
2
1
BLM15BD121SN1D_0402
1
1
1
C334
C335
C336
DIS@
DIS@
DIS@
1U_0402_6.3V4Z
10U_0603_6.3V6M
2
2
2
L50
0.1U_0402_10V6K
DIS@
2
1
BLM15BD121SN1D_0402
1
1
1
C509
C508
C507
DIS@
DIS@
DIS@
1U_0402_6.3V4Z
10U_0603_6.3V6M
2
2
2
0.1U_0402_10V6K
L34
0.1U_0402_10V6K
+1.8VSG
2
1
L27
DIS@
2
1
MBK1608121YZF_0603
C318 DIS@
10U_0603_6.3V6M
DIS@
2 C317 2
2
1U_0402_6.3V4Z
2
0.2A
0.17A
+1.8VSG
B
1
0.1U_0402_10V6K
2
+DPF_VDD18
2
DIS@
C324
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
C323
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DIS@
1
C338
C
1
1
1U_0402_6.3V4Z
DPA_VDD10#1
DPA_VDD10#2
+DPA_VDD10
DIS@
C322
DPE_VDD10#1
DPE_VDD10#2
AF6
AF7
10U_0603_6.3V6M
+DPE_VDD10
AG20
AG21
L29
0.2A
0.1U_0402_10V6K
2
+1.8VSG
C3291
DIS@
1
+VGA_PCIE
0.17A
L31
1
2
MBK1608121YZF_0603
C328
DIS@ 1
1U_0402_6.3V4Z
C319 DIS@
0.1U_0402_10V6K
+DPA_VDD18
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2009/10/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PARK-S3 DPX Power
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
1
16
of
47
5
4
3
2
1
+1.5VSG
2.2A
DIS@
1
0.1U_0402_10V6K
+1.8VSG
0.4A
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
DIS@
1
2
1U_0402_6.3V4Z
2
DIS@
1
1U_0402_6.3V4Z
2
DIS@
1
1U_0402_6.3V4Z
2
DIS@
1
1U_0402_6.3V4Z
DIS@
1
1U_0402_6.3V4Z
2
10U_0603_6.3V6M
2
DIS@
1
10U_0603_6.3V6M
2
DIS@
1
10U_0603_6.3V6M
10U_0603_6.3V6M
2
DIS@
1
SPV18
2A(RMS)/3A(Peak)
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
M13
M15
M16
M17
M18
M20
M21
N20
DIS@
1
2
DIS@ DIS@
1
1
2
2
DIS@
1
2
+VGA_CORE
10U_0603_6.3V6M
MPV18
ISOLATED
CORE I/O
1U_0402_6.3V4Z
0.1U_0402_10V6K
1U_0402_6.3V4Z
10U_0603_6.3V6M
2
DIS@
1
1U_0402_6.3V4Z
0.1U_0402_10V6K
1U_0402_6.3V4Z
10U_0603_6.3V6M
+VGA_CORE
DIS@
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0603_6.3V6M
SPV10
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
SPVSS
GND#1
GND#2
GND#3 / EVDDQ#2
GND#4
GND#5
GND#6 / EVDDQ#3
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#85
GND#86
GND
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
T11
R11
C
A32
AM1
AM32
BACK BIAS
M11
M12
DIS@
1
2
DIS@
1
2
0.1U_0402_10V6K
+VGA_CORE
1U_0402_6.3V4Z
0.1U_0402_10V6K
1U_0402_6.3V4Z
2
C401
10U_0603_6.3V6M
2
DIS@
1
C388
2
DIS@
1
C400
2
C414
2
DIS@
1
2
DIS@
1
C387
H8
2
DIS@
1
C399
100mA
2
DIS@
1
C398
L8
H7
+SPV10
C413
B
DIS@
1
C412
2
C411
C410
DIS@
1
PCIE_PVDD
50mA
+SPV18
J7
DIS@
L40
1
2
BLM15BD121SN1D_0402
VSSRHA
75mA
+MPV18
2
DIS@
1
C409
2
DIS@
1
C408
DIS@
1
2
C407
+VGA_PCIE
2
C405
2
DIS@
1
C404
DIS@
1
AM30
DIS@
1
VDDRHA
PLL
40mA
2
C406
+PCIE_PVDD
C403
1
2
BLM15BD121SN1D_0402
DIS@
2
DIS@
1
C386
L39
DIS@
1
C385
+1.8VSG
L16
+VGA_CORE
9A(RMS)/14A(Peak)
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
R21
U21
C397
MEM CLK
L17
+VGA_PCIE
C384
0.04A
+VDDRHA
R185 @
0_0402_5%
2
C396
1U_0402_6.3V4Z @
2
1C402
L38
1
2
BLM15BD121SN1D_0402
NC#3 / VDDR5
TESTEN#2 / VDDR5
2
C395
V11
U11
NC#1 / VDDR4
DVCLK / VDDR4
2
C394
@
AA11
Y11
2
C393
+1.5VSG
2
+VDDR
VDDR4#1 / VDDR5
VDDR4#2
VDDR4#3 / VDDR5
2
C392
2
V12
Y12
U12
DIS@
1
D
AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32
DIS@
1
C383
1
C391
2
DIS@
C390
C389
1
2
DIS@
1
C382
DIS@
I/O
2
DIS@
1
C381
+1.8VSG
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#20
VDDC#21
VDDC#22
VDDC#23 /BIF_VDDC
VDDC#19/BIF_VDDC
CORE
POWER
M93-S3/M92-S2
AA17
AA18
AB17
AB18
C
LEVEL
TRANSLATION
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
2
DIS@
1
C380
2
AA20
AA21
AB20
AB21
DIS@
1
C379
2
+VDDC_CT17mA
DIS@
1
C378
2
DIS@
1
C377
2
DIS@
1
C376
C375
DIS@
1
2
U6E
2A
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
1U_0402_6.3V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.06A
2
L36
1
2
MBK1608221YZF_0603
DIS@
DIS@
1
C362
+3VSG
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
DIS@
1
C361
0.1U_0402_10V6K
2
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
C374
1U_0402_6.3V4Z
2
2
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
C373
1U_0402_6.3V4Z
2
2
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22
DIS@
1
C372
10U_0603_6.3V6M
C360
2
C368
C367
C359
2
2
DIS@
1
C371
0.136A
DIS@
1
C370
C365
L37
1
2
BLM15BD121SN1D_0402 DIS@
DIS@
DIS@
DIS@
DIS@
1
1
1
1
+1.8VSG
C366
DIS@
1
+VDDC_CT
DIS@
1
C358
PCIE
C364
MEM I/O
C369
C363
+1.5VSG
D
C357
+PCIE_GDDR
DIS@
DIS@
1
1
1U_0402_6.3V4Z
U6D
1U_0402_6.3V4Z
2
10U_0603_6.3V6M
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
DIS@
1
C356
2
DIS@
1
C492
2
C493
2
C353
2
DIS@ DIS@ DIS@
1
1
1
C352
2
DIS@
1
C351
2
DIS@
1
C350
2
DIS@
1
C349
DIS@
1
C348
2
C347
2
C346
2
C345
2
C344
C343
DIS@ DIS@ DIS@ DIS@
1
1
1
1
BBP#1
BBP#2
Park-S3
120mA
DIS@
B
Park-S3
DIS@
+1.8VSG
+MPV18
2
0.1U_0402_10V6K
DIS@
1
+SPV18
DIS@
1
2
0.1U_0402_10V6K
1U_0402_6.3V4Z
2
C418
DIS@
1
C417
DIS@
L42
1
2
BLM15BD121SN1D_0402
1U_0402_6.3V4Z
2
C416
DIS@
1
C415
DIS@
L41
1
2
BLM15BD121SN1D_0402
A
A
+VDDR
DIS@
1
2
0.1U_0402_10V6K
1U_0402_6.3V4Z
2
C420
DIS@
1
C419
DIS@
L43
1
2
BLM15BD121SN1D_0402
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2009/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PARK-S3 Power
Size
C
Date:
5
4
3
2
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
1
17
of
47
5
4
3
2
1
M_DA[63..0]
[15] M_DA[63..0]
M_MA[13..0]
[15] M_MA[13..0]
M_DQM[7..0]
[15] M_DQM[7..0]
U9
U10
U11
U12
M_DQS[7..0]
[15] M_DQS[7..0]
M_DQS#[7..0]
SAMSUNG VRAM
E8
D4
M_DQS#3
M_DQS#1
G4
B8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
DRAM_RST# T3
RESET
L9
ZQ/ZQ0
J2
L2
J10
L10
R191
240_0402_1%
DIS@
1
1
R203
4.99K_0402_1%
DIS@
DIS@
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
A1
A11
T1
T11
A2
A9
C2
C10
D3
E10
F2
H3
H10
M_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1
K2
L3
J4
K4
L4
M_DQS6
M_DQS7
F4
C8
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
M_DQM6
M_DQM7
E8
D4
M_DQS#6
M_DQS#7
G4
B8
DRAM_RST# T3
L9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
NC
NC
NC
B2
B10
D2
D9
E3
E9
F10
G2
G10
J2
L2
J10
L10
R192
240_0402_1%
DIS@
A1
A11
T1
T11
DIS@
2
+1.5VSG
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
B3
D10
G8
K3
K9
N2
N10
R2
R10
+1.5VSG
A2
A9
C2
C10
D3
E10
F2
H3
H10
C
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
NC
NC
NC
B2
B10
D2
D9
E3
E9
F10
G2
G10
100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@
+1.5VSG
+1.5VSG
+1.5VSG
VREFD_Q2
1
D
M_DA57
M_DA58
M_DA60
M_DA61
M_DA63
M_DA62
M_DA56
M_DA59
D8
C4
C9
C3
A8
A3
B9
A4
+1.5VSG
R197
4.99K_0402_1%
DIS@
R204
4.99K_0402_1%
DIS@
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
M_DA54
M_DA52
M_DA53
M_DA49
M_DA51
M_DA50
M_DA55
M_DA48
E4
F8
F3
F9
H4
H9
G3
H8
1
100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@
VREFC_A2
2
C422
J8
K8
K10
2
2
2
1
M_CLK1
M_CLK#1
M_CKE1
+1.5VSG
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
R198
R199
4.99K_0402_1%
DIS@
4.99K_0402_1%
DIS@
VREFC_A3
1
R205
4.99K_0402_1%
DIS@
DIS@
2
R200
VREFD_Q3
1
R206
4.99K_0402_1%
DIS@
DIS@
2
B
4.99K_0402_1%
DIS@
VREFC_A4
1
R207
4.99K_0402_1%
DIS@
DIS@
2
VREFD_Q4
1
R208
4.99K_0402_1%
DIS@
DIS@
2
0.1U_0402_10V6K
2
M3
N9
M4
VREFCA
VREFDQ
0.1U_0402_10V6K
C421
B2
B10
D2
D9
E3
E9
F10
G2
G10
1
1
1
2
ZQ/ZQ0
M_BA0
M_BA1
M_BA2
B3
D10
G8
K3
K9
N2
N10
R2
R10
0.1U_0402_10V6K
1
RESET
0.1U_0402_10V6K
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
L9
0.1U_0402_10V6K
DIS@
1
DML
DMU
DRAM_RST# T3
R196
4.99K_0402_1%
DIS@
VREFC_A1
R202
4.99K_0402_1%
DIS@
DQSL
DQSU
G4
B8
+1.5VSG
0.1U_0402_10V6K
2
NC
NC
NC
NC
R195
4.99K_0402_1%
DIS@
0.1U_0402_10V6K
2
0.1U_0402_10V6K
DIS@
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
+1.5VSG
VREFD_Q1
1
E8
D4
M_DQS#4
M_DQS#5
100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@
R194
4.99K_0402_1%
DIS@
R201
4.99K_0402_1%
DIS@
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
A1
A11
T1
T11
+1.5VSG
R193
4.99K_0402_1%
DIS@
M_DQM4
M_DQM5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2
J2
L2
J10
L10
R190
240_0402_1%
DIS@
100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@
+1.5VSG
F4
C8
ODT/ODT0
CS
RAS
CAS
WE
1
NC
NC
NC
NC
M_DQS4
M_DQS5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
K2
L3
J4
K4
L4
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8
+1.5VSG
BA0
BA1
BA2
2
A1
A11
T1
T11
B2
B10
D2
D9
E3
E9
F10
G2
G10
M_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1
M_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
C424
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
J2
L2
J10
L10
R189
240_0402_1%
DIS@
B
DML
DMU
[15]
[15]
[15]
[15]
[15]
M_DA44
M_DA42
M_DA47
M_DA40
M_DA45
M_DA43
M_DA46
M_DA41
M9
H2
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
C428
M_DQM3
M_DQM1
DQSL
DQSU
A2
A9
C2
C10
D3
E10
F2
H3
H10
D8
C4
C9
C3
A8
A3
B9
A4
VREFC_A4
VREFD_Q4
2
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M_DA38
M_DA34
M_DA33
M_DA37
M_DA35
M_DA39
M_DA32
M_DA36
1
F4
C8
ODT/ODT0
CS
RAS
CAS
WE
M3
N9
M4
M_CLK1
J8
M_CLK#1 K8
M_CKE1 K10
[15] M_CLK1
[15] M_CLK#1
+1.5VSG [15] M_CKE1
1
ZQ/ZQ0
M_DQS3
M_DQS1
CK
CK
CKE/CKE0
M_BA0
M_BA1
M_BA2
B3
D10
G8
K3
K9
N2
N10
R2
R10
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E4
F8
F3
F9
H4
H9
G3
H8
2
RESET
K2
L3
J4
K4
L4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
1
DQSL
DQSU
M_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0
+1.5VSG
BA0
BA1
BA2
VREFCA
VREFDQ
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A2
A9
C2
C10
D3
E10
F2
H3
H10
M_DA14
M_DA10
M_DA15
M_DA11
M_DA12
M_DA8
M_DA13
M_DA9
M9
H2
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
1
DML
DMU
J8
K8
K10
1
L9
DQSL
DQSU
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M_CLK0
M_CLK#0
M_CKE0
+1.5VSG
D8
C4
C9
C3
A8
A3
B9
A4
VREFC_A3
VREFD_Q3
1
T3
[15] DRAM_RST#
ODT/ODT0
CS
RAS
CAS
WE
M3
N9
M4
M_DA25
M_DA27
M_DA24
M_DA31
M_DA26
M_DA30
M_DA28
M_DA29
2
G4
B8
CK
CK
CKE/CKE0
M_BA0
M_BA1
M_BA2
B3
D10
G8
K3
K9
N2
N10
R2
R10
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E4
F8
F3
F9
H4
H9
G3
H8
C426
E8
D4
M_DQS#2
M_DQS#0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
1
M_DQM2
M_DQM0
+1.5VSG
BA0
BA1
BA2
VREFCA
VREFDQ
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8
2
F4
C8
M_DA0
M_DA4
M_DA1
M_DA6
M_DA3
M_DA7
M_DA2
M_DA5
M9
H2
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
1
M_DQS2
M_DQS0
D8
C4
C9
C3
A8
A3
B9
A4
VREFC_A2
VREFD_Q2
1
C
K2
L3
J4
K4
L4
M_DA16
M_DA23
M_DA19
M_DA21
M_DA17
M_DA18
M_DA22
M_DA20
2
M_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0
M_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E4
F8
F3
F9
H4
H9
G3
H8
C425
M_CLK0
J8
M_CLK#0 K8
M_CKE0 K10
[15] M_CLK0
[15] M_CLK#0
[15] M_CKE0
[15]
[15]
[15]
[15]
[15]
M3
N9
M4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
S@
U12
1
M_BA0
M_BA1
M_BA2
[15] M_BA0
[15] M_BA1
[15] M_BA2
VREFCA
VREFDQ
2
Samsung
X76S@
X7622338L01
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8
1
Hynix
X76H@
X7622338L02
M9
H2
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
X76-S
C423
X76-H
SAMSUNG VRAM
S@
U11
1
VREFC_A1
VREFD_Q1
D
SAMSUNG VRAM
S@
U10
C427
S@
2
SAMSUNG VRAM
U9
2
[15] M_DQS#[7..0]
+1.5VSG
+1.5VSG
+1.5VSG
2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
A
VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/10/06
Deciphered Date
2009/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PARK-S3 DDR3 VRAM
Size
C
Date:
5
4
C445
C454
C453
C452
C444
C443
C442
C451
2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C441
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1
1
1
1
1
1
1
1
1
1
C440
C439
C450
C456
0.01U_0402_16V7K
DIS@
C438
2
C437
1
C430
2
2
2
10U_0603_6.3V6M10U_0603_6.3V6M
C436
2
56_0402_1%
C449
C448
2
C435
2
M_CLK#11
R212 DIS@
C455
0.01U_0402_16V7K
DIS@
C447
2
10U_0603_6.3V6M
C434
1
A
C429
2
C433
M_CLK#01
2
R211 DIS@ 56_0402_1%
2
56_0402_1%
10U_0603_6.3V6M
DIS@ 1
DIS@ 1
C432
C446
M_CLK1 1
R210 DIS@
10U_0603_6.3V6M
DIS@ 1
DIS@ 1
C431
M_CLK0 1
2
R209 DIS@ 56_0402_1%
10U_0603_6.3V6M
DIS@ 1
DIS@ 1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1
1
1
1
1
1
1
1
1
1
3
2
Document Number
Rev
0.2
NAWE6 LA-5754P
Sheet
Monday, March 01, 2010
1
18
of
47
5
4
3
2
1
Check Timing +1.1VS <50us +3VS for EXT CLKGEN satable
+VDDCLK_IO
VB
L45 EXT@
1
EXT@ L44
+1.1VS
0.1U_0402_16V4Z
1
1
C458
FBMA-L11-201209-221LMA30T_0805 C457
1
2
D
EXT@
2
2
22U_0805_10V4Z
EXT@
0.1U_0402_16V4Z
1
1
C459
C460
EXT@
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
1
C461
C462
EXT@
EXT@
2
0.1U_0402_16V4Z
2
+3VS
+3VS_CLK
2
FBMA-L11-201209-221LMA30T_0805
1
1
C464
C465
0.1U_0402_16V4Z
1
C466
22U_0805_10V4Z
EXT@
2 EXT@
2
0.1U_0402_16V4Z
EXT@
2
EXT@
1
0.1U_0402_16V4Z
1
C468
1
C467
EXT@
2
0.1U_0402_16V4Z
2
EXT@
0.1U_0402_16V4Z
1
C470
C469
EXT@
2
0.1U_0402_16V4Z
2
EXT@
1
1
C471
EXT@
2
0.1U_0402_16V4Z
C474
D
1U_0402_6.3V4Z
2 EXT@
12/23
1U CLOSE PIN 69
+3VS
EXT@ L46
1
+3VS_CLKVDDA
2
100mA
+3VS_CLK
FBMA-L11-201209-221LMA30T_0805
1
2
2
U13
C476
0.1U_0402_16V4Z
EXT@
1
1
ICS 9LPRS488
49
48
VDDA
GNDA
62
66
VDDREF
GNDREF
SB_SRC_SLOW#
12
18
28
37
53
VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO
CPUKG0T_LPRS
CPUKG0C_LPRS
56
55
HTT0T_LPRS / 66 M
HTT0C_LPRS / 66 M
60
59
SMBCLK
SMBDAT
1
2
R213
8.2K_0402_5%
EXT@
SB_SMCLK0 [8,9,21,28]
SB_SMDAT0 [8,9,21,28]
2
C475
22U_0805_10V4Z
EXT@
Mini Card_WLAN
WWAN
NEW CARD
[21,29] LAN_CLKREQ#
24
[21,28] WLAN_CLKREQ#
51
[20,28] WWAN_CLKREQ#
50
43
[20,28] EXP_CLKREQ#
42
27M_SEL
63
SEL_SATA
64
EXT@
[11] CLK_NB_14.318M
CLK_14.318M
2
158_0402_1%
1
R237
65
SB_SRC1T_LPRS
SB_SRC1C_LPRS
35
34
1 INT@ 2
R217 1 INT@ 0_0402_5%
2
R218
0_0402_5%
ATIG0T_LPRS
ATIG0C_LPRS
71
[21] CLK_48M_USB
CLK_48M
1
33_0402_5%
2
R240
70
CLK_XTAL_IN
67
CLK_XTAL_OUT
68
6
11
19
27
36
47
52
58
72
73
NB HT
C
NB_HT_CLKP [20]
NB_HT_CLKN [20]
+3VS_CLK
CLKREQ0 #
CLKREQ1#
ATIG1T_LPRS
ATIG1C_LPRS
CLKREQ2#
CLKREQ3#
ATIG2T_LPRS
ATIG2C_LPRS
CLKREQ4#
REF2/SEL_27
SRC1T_LPRS
SRC1C_LPRS
33
32
31
30
CLK_NBGFX [11]
CLK_NBGFX# [11]
ATIG1
1 EXT@ 2
ATIG1# R225 1 EXT@ 0_0402_5%
2
R226
0_0402_5%
1 INT@ 2
R227 1 INT@ 0_0402_5%
2
R228
0_0402_5%
1 INT@
2
R229 1 INT@ 0_0402_5%
2
R230
0_0402_5%
23
22
1 INT@ 2
R235 1 INT@ 0_0402_5%
2
R236
0_0402_5%
REF1/SEL_SATA
REF0/SEL_HTT66
SRC2T_LPRS
SRC2C_LPRS
16
15
1 INT@ 2
R238 1 INT@ 0_0402_5%
2
R239
0_0402_5%
48MHz_0
SRC3T_LPRS
SRC3C_LPRS
14
13
VGA
SEL_SATA
10
9
CLK_XTAL_OUT
CLK_XTAL_IN
B
CLK_SBLINK_BCLK [11]
CLK_SBLINK_BCLK# [11]
Y2
2
NB A LINK
GNDDOT
GNDSRC
GNDSRC
GNDATIG
GNDSB_SRC
GNDSATA
GNDCPU
GNDHTT
GND48
GNDPAD
SRC5T_LPRS
SRC5C_LPRS
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
SRC7T_LPRS/27MHz_SS
SRC7C_LPRS/27MHz_NS
PD#
8
7
C478 EXT@
33P_0402_50V8J
46
45
CLK_SBSRC_BCLK [20]
CLK_SBSRC_BCLK# [20]
5
4
CLK_SRC7C_SS
@
1
2
CLK_SRC7C
R276
0_0402_5%
1 EXT@ 2 27M_CLK 1 EXT@ 2
R277
0_0402_5% R548 0_0402_5%
57
2 EXT@ 1
+3VS_CLK
R243
8.2K_0402_5%
EXT@
1
SB RCLK
2
2
C479 EXT@
33P_0402_50V8J
Routing the trace at least 10mil
CLK_NB_14.318M
27M_NSSC [14]
1 @
2
R271 0_0402_5%
Change Y2 to
TXC-SJ100009R00
<20ppm / 20pF>
14.318MHZ_16PF_7A14300083
1
1
X1
X2
27M_SEL
R231
8.2K_0402_5%
EXT@
48MHz_1
SRC4T_LPRS
SRC4C_LPRS
R224
8.2K_0402_5%
EXT@
VGA_CLKP [20]
VGA_CLKN [20]
GPP_CLK1P [20]
GPP_CLK1N [20]
GLAN
CLK_PCIE_LAN [29]
CLK_PCIE_LAN# [29]
GPP_CLK3P [20]
GPP_CLK3N [20]
CLK_PCIE_WLAN [28] MiniCard_WLAN
CLK_PCIE_WLAN# [28]
GPP_CLK5P [20]
GPP_CLK5N [20]
CLK_PCIE_WWAN [28] MiniCard_WWAN
CLK_PCIE_WWAN# [28]
GPP_CLK7P [20]
GPP_CLK7N [20]
New Card
CLK_PCIE_EXP [28]
CLK_PCIE_EXP# [28]
1 INT@ 2
R232 1 INT@ 0_0402_5%
2
R233
0_0402_5%
21
20
R223
8.2K_0402_5%
@
NB GFX
CLK_PEG_VGA [13]
CLK_PEG_VGA# [13]
26
25
B
EXT@
CLK_NBHT [11]
CLK_NBHT# [11]
R216
8.2K_0402_5%
@
2
SB_SRC0T_LPRS
SB_SRC0C_LPRS
40
39
SRC0T_LPRS
SRC0C_LPRS
EXT@ VB
1
2
R234
90.9_0402_1%
CPU
2
VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDD48
CLK_CPU_BCLK [6]
CLK_CPU_BCLK# [6]
2
R222 8.2K_0402_5%
1
2
R221 8.2K_0402_5%
1
2
+3VS_CLK
3
17
29
38
44
54
L47
61
69
1
2
BLM18AG601SN1D_2P
EXT@
CPU_HT_CLKP [20]
CPU_HT_CLKN [20]
1
LAN
100mA
R220 8.2K_0402_5%
1
2
@
VB
R219 8.2K_0402_5%
1
2
+3VS
VB
C
SRC_SLOW
1 INT@ 2
R214 1 INT@ 0_0402_5%
2
R215
0_0402_5%
1
100mA
SRC_SLOW
2
+VDDCLK_IO
41
1
EXT@
2
1
C477
0.1U_0402_16V4Z
1
100mA
+3VS_CLK
RS780
1.1V 158R/90.0R
VGA_DBCLK [34]
1 * NON SPREAD 27M and SPREAD 27M output
SLG8SP626VTR_QFN72_10x10 EXT@
2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN
A
CLK_SBLINK_BCLK
2
0_0402_5%
CLK_SBLINK_BCLK#
2
0_0402_5%
1 INT@
R248
1 INT@
R249
CLK_SBSRC_BCLK#
2
0_0402_5%
CLK_SBSRC_BCLK
2
0_0402_5%
0
2008/10/06
SEL_SATA
3
differential 100MHz HTT output
1
NON SPREAD 100M SATA SRC6 output
A
*
0
SPREAD 100M SATA SRC6 output
* default
Title
Clock generator
Date:
4
single-ended 66MHz HTT output
0*
Compal Electronics, Inc.
2010/03/12
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
differential spread SRC_7 output
1
SEL_HTT66
Compal Secret Data
Security Classification
Issued Date
CLK_SB#
1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN
CLK_SB
27M_SEL
1 INT@
R244
1 INT@
R246
2
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
1
19
of
47
A
B
AA22
Y21
AA25
AA24
W23
V24
W24
W25
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
Workaround
Setting SpreadSpectrum =1
will enable spread spectrum
[19] NB_HT_CLKP
[19] NB_HT_CLKN
T26
T27
[19] CPU_HT_CLKP
[19] CPU_HT_CLKN
V21
T21
[19] VGA_CLKP
[19] VGA_CLKN
V23
T23
L29
L28
LAN
[19] GPP_CLK1P
[19] GPP_CLK1N
WLAN
[19] GPP_CLK3P
[19] GPP_CLK3N
N29
N28
M29
M28
T25
V25
L24
L23
3
Close to SB
P29
P28
N26
N27
[19] GPP_CLK7P
[19] GPP_CLK7N
T29
T28
L25
CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
GPP_CLK1P
GPP_CLK1N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N
25M_CLK_X2
L27
1
25M_X1
25M_X2
32K_X2
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
5
P
1
G
2
R1193 @
100K_0402_5%
[24]
[22,24]
[24]
[24]
[24]
[24]
[24]
PCI_AD24 : VDDR Voltage SW
+3VS
2
H_PWRGD
R329
4.7K_0402_5%
3
1
H_PWRGD_L [47]
Q21
FDV301N_NL_SOT23-3
level shift to ISL6265
1
2
INT@
R527 0_0402_5%
WWAN_CLKREQ# [19,28]
1
2
INT@
R531 0_0402_5%
EXP_CLKREQ# [19,28]
LPCCLK0
ISL6265 PWROK input, TTL level: 0.8V~2.0V
When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
22_0402_5%
R330
2 LPC_CLK0_EC
1
LPC_CLK0_EC [24,34]
LPC_CLK1 [24]
LPC_AD0 [28,34]
LPC_AD1 [28,34]
LPC_AD2 [28,34]
LPC_AD3 [28,34]
LPC_FRAME# [28,34]
R332 @
2
G21
H21
K19
G22
J24
SB_32KHI
Y3
2
ALLOW_LDTSTOP [11]
H_PROCHOT_R# [6]
H_PWRGD [6]
LDT_STOP# [6,11]
LDT_RST# [6]
C1
SB_32KHI
C2
SB_32KHO
20M_0402_5%
1
3
C582
SERIRQ [34]
NC
OSC
NC
OSC
2
1
18P_0402_50V8J
1
R335
20M_0603_5%
4
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
C586
2
1
18P_0402_50V8J
+RTCBATT
D2
B2
B1
PAD
T21
W=20mils
1
R333
@ C584 1
SB820M_FCBGA605
SB820 A12(SA00003IW10)
2
2
CLRP1 @
SHORT PADS
for Clear CMOS
4
Compal Electronics, Inc.
Compal Secret Data
2008/10/06
Issued Date
2
510_0402_5%
1 C585
Security Classification
2010/03/12
Deciphered Date
Title
SB820-PCIE/PCI/ACPI/LPC/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
B
1
+1.5VS
4
A
PLT_RST# [11,12,13,28,29,34]
3
1
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
1
25MHZ_20PF_7A25000012
A
NC7SZ08P5X_NL_SC70-5
PLT_RST#
4
2
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
0.1U_0402_16V4Z
C688
27P_0402_50V8J
1
2
R426
U21
Y
14M_25M_48M_OSC
1M_0603_5%
Y6
B
Check the output status of control gate when power on!!
2
C689
27P_0402_50V8J
L26
2
1
3
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
RTC
25M_CLK_X1
2
2
@ 0_0402_5%
2
0_0402_5%
0.1U_0402_16V4Z
R328
8.2K_0402_5%
@
AJ6
AG6
AG4
AJ4
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
1
R427
1
R425
A_RST#
GPP_CLK2P
GPP_CLK2N
32K_X1
1
[21] SB_GPIO_A_RST#
2
New Card
NB_HT_CLKP
NB_HT_CLKN
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
1U_0402_6.3V4Z
WWAN
P25
M25
[19] GPP_CLK5P
[19] GPP_CLK5N
NB_DISP_CLKP
NB_DISP_CLKN
C581
1
2
AMD suggest add GPIO control gate
V2
D
[11] NB_DISP_CLKP
[11] NB_DISP_CLKN
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
+3VALW
S
U29
U28
[24]
[24]
[24]
[24]
G
M23
P23
[19] CLK_SBSRC_BCLK
[19] CLK_SBSRC_BCLK#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
[28] PCIE_EXPCARD_SB_RXP
[28] PCIE_EXPCARD_SB_RXN
NEW CARD
PCIE_CALRP
PCIE_CALRN
1 C210 EXPCARD_TXP_R AA28
C207 EXPCARD_TXN_R AA29
1
Y29
Y28
Y26
Y27
W28
W29
PCIRST#
W2
W1
W3
W4
Y1
1
590_0402_1% AD29
2K_0402_1% AD28
1
1
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
1
0.1U_0402_16V7K 2
0.1U_0402_16V7K2
[28] PCIE_SB_EXPCARD_TXP
[28] PCIE_SB_EXPCARD_TXN
2
2
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
Part 1 of 5
2
R326
R327
E
2
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
VB
2
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
+1.1VS_PCIE
NEW CARD
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
2
2
2
2
2
SB800
PCIE_RST#
A_RST#
PCI INTERFACE
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
1
1
1
1
1
1
1
1
P1
L1
LPC
1
C579
C573
C574
C575
C576
C580
C577
C578
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PAD
PCI CLKS
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
D
U20A
33_0402_5%
T4
1
CPU
R325
2
PCI EXPRESS INTERFACES
2 150P_0402_50V8J
A_RST#
CLOCK GENERATOR
C572 1
C
C
D
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
E
20
of
47
A
B
C
D
E
@
@
1
R337
C587 1
2
100_0402_5%
2 100P_0402_25V8K
U20D
CLK MODE SEL: 1-> INT CLK mode
0-> EXT CLK Mode
R515 1 INT@
2 EXT@
2 2.2K_0402_5%
CLK_MODE
CLK_MODE
2 0_0402_5%
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
GPIO60
[33] SB_SPKR
[8,9,19,28] SB_SMCLK0
[8,9,19,28] SB_SMDAT0
Cinfigure to output or
Internal PU/PD
UMA/DIS SEL FOR HDMI USE:High: DIS VGA Low: UMA VGA
reserve
2
G1
100K_0402_5%
VB
+3VS
R516 1 INT@
[19,28] WLAN_CLKREQ#
[20] SB_GPIO_A_RST#
1
R593
EC_RSMRST#
[34] EC_RSMRST#
@
1
R366
@
1
R370
2
10K_0402_5%
2
10K_0402_5%
[19,29] LAN_CLKREQ#
GPIO60
[34] EC_LID_OUT#
SB_SMCLK0
SB_SMDAT0
SB_SMCLK1
SB_SMDAT1
1
2
INT@
R517 0_0402_5%
EC_LID_OUT#
Chcek leakage from SB internal pull-ups in S4/S5 states.
[33] HDA_BITCLK_AUDIO
R345 1
2 33_0402_5%
R346 1
2 33_0402_5%
[37] USB_OC#1
[37] USB_OC#0
[24] HDA_SDOUT
[33] HDA_SDOUT_AUDIO
[33] HDA_SDIN0
[33] HDA_SYNC_AUDIO
[33] HDA_RST_AUDIO#
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
R347 1
2 33_0402_5%
HDA_SYNC
R348 1
2 33_0402_5%
HDA_RST#
GBE_COL
GBE_CRS
3
GBE_MDIO
+3VS
1
R339
@
1
R349
@
1
R350
@
1
R351
GBE_RXERR
EC_RSMRST#
2
2.2K_0402_5%
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDIN1
2
10K_0402_5%
R342 1
2 2.2K_0402_5% SB_SMCLK0
R343 1
2 2.2K_0402_5% SB_SMDAT0
R344 1
2 4.7K_0402_5%
SUS_STAT#
GBE_PHY_INTR
H3
D1
E4
D4
E8
F7
E7
F8
M3
N1
L2
M2
M1
M4
N2
P2
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
E23
E24
F21
G29
+3VALW
+3VALW
4
1
R355
@
1
R357
1
R359
1
R360
1
R361
1
R362
1
R363
SB_PCIE_WAKE#
2
10K_0402_5%
EC_LID_OUT#
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SB_SMCLK1
2
2.2K_0402_5%
SB_SMDAT1
2
2.2K_0402_5%
1
R352
1
R358
2
1
R353
1
R354
1
R356
2
2
GBE_MDIO
10K_0402_5%
GBE_PHY_INTR
10K_0402_5%
D27
F28
F29
E27
USB 1.1 USB MISC
ACPI / WAKE UP EVENTS
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
USB 2.0
[6] H_THERMTRIP#
[11] NB_PWRGD
USB_FSD1P/GPIO186
USB_FSD1N
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_FCBGA605
CLK_48M_USB [19]
2
R338
1
J10
H11
OHCI4
H9
J8
B12
A12
USB20_P12 [37]
USB20_N12 [37]
Right USB(Sub b/d)
USB_HSD11P
USB_HSD11N
E14
E12
USB20_P11 [28]
USB20_N11 [28]
WLAN
USB_HSD10P
USB_HSD10N
J12
J14
USB20_P10 [28]
USB20_N10 [28]
WWAN
USB_HSD9P
USB_HSD9N
A13
B13
USB_HSD8P
USB_HSD8N
D13
C13
USB_HSD7P
USB_HSD7N
G12
G14
USB20_P7 [28]
USB20_N7 [28]
USB_HSD6P
USB_HSD6N
G16
G18
USB20_P6 [37]
USB20_N6 [37]
USB_HSD5P
USB_HSD5N
D16
C16
USB20_P5 [27]
USB20_N5 [27]
USB_HSD4P
USB_HSD4N
B14
A14
USB20_P4 [37]
USB20_N4 [37]
ESATA and USB
USB_HSD3P
USB_HSD3N
E18
E16
USB20_P2 [32]
USB20_N2 [32]
CardReader
USB20_P0 [37]
USB20_N0 [37]
Left USB
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
A10
G19 USB_RCOMP
1
Z=35ohm
11.8K_0402_1%
F11
E11
USB_HSD12P
USB_HSD12N
GPIO
+3VS
USB OC
2 R72 @ 1
20K_0402_5%
+3VALW
[28,29] SB_PCIE_WAKE#
USB_RCOMP
EMBEDDED CTRL
[34] GATEA20
[34] KB_RST#
[34] EC_SCI#
[34] EC_SMI#
SB800
USBCLK/14M_25M_48M_OSC
EMBEDDED CTRL
1
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
HD AUDIO
J2
K1
D3
F1
H1
F2
H5
SUS_STAT#
G6
B3
T24
PAD
C4
T22
PAD
F6
T23
PAD
AD21
AE21
K2
J29
H2
SYS_RESET#
J1
H6
F3
H_THERMTRIP#
J6
AC19
GBE LAN
VB
0_0402_5%
1 R545
2
[28] CPUSB#
[34] PM_SLP_S3#
[34] PM_SLP_S5#
[34] PBTN_OUT#
[6,11,34] SB_PWRGD
[11] SUS_STAT#
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
EHCI13 / OHCI3
EHCI2 / OHCI2
New Card
BT
Camera
2
EHCI1 / OHCI1
J16
J18
B17
A17
A16
B16
D25
F23
B26
E26
F25
E22
F22
E21
Check SW:
Cinfigure to output or Internal PU/PD
SB_SIC [6]
SB_SID [6]
GPIO199 [24]
GPIO200 [24]
Check SW:
Cinfigure to output or Internal PU/PD
STRAP PIN
G24
G25
E28
E29
D29
D28
C29
C28
3
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
SB820 A12(SA00003IW10)
GBE_COL
4
10K_0402_5%
GBE_CRS
2
10K_0402_5%
GBE_RXERR
2
10K_0402_5%
AMD recommend PD 10K
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB820 USB/HD audio
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
E
21
of
47
A
B
C
D
E
U20B
[32] SATA_STX_DRX_P1
[32] SATA_STX_DRX_N1
AH10
AJ10
[32] SATA_DTX_C_SRX_N1
[32] SATA_DTX_C_SRX_P1
AG10
AF10
[37] SATA_STX_DRX_P2
[37] SATA_STX_DRX_N2
AG12
AF12
SATA_TX2P
SATA_TX2N
[37] SATA_DTX_C_SRX_N2
[37] SATA_DTX_C_SRX_P2
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
2
+1.1VS_SATA
R364
2
2
R365
1K_0402_1% Z=35ohm
SATA_CALRP
1
SATA_CALRN
1
931_0402_1%
AD11
[36] SATA_LED#
+3VS
R367 1
AB14
AA14
SATA_RX0N
SATA_RX0P
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
SATA_TX1P
SATA_TX1N
SATA_RX1N
SATA_RX1P
SATA_ACT#/GPIO67
T15 PAD
AD16
AC16
J5
E2
K4
K9
G2
SATA_X1
SATA_X2
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
AH28
AG28
AF26
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
NC1
NC2
1
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
SATA_CALRP
SATA_CALRN
2 10K_0402_5%
T13 PAD
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
Part 2 of 5
FLASH
e-SATA
[32] SATA_DTX_C_SRX_N0
[32] SATA_DTX_C_SRX_P0
AJ8
AH8
SERIAL ATA
ODD
SB800
SATA_TX0P
SATA_TX0N
HW MONITOR
HDD
AH9
AJ9
[32] SATA_STX_DRX_P0
[32] SATA_STX_DRX_N0
SPI ROM
1
2
Check SW:
Cinfigure to output or Internal PU/PD
A3
B4
A4
C5
A7
B7
B8
A8
MEM_1V5
G27
Y2
SB820M_FCBGA605
3
3
SB820 A12(SA00003IW10)
MEM_1V5 is for gating the
glitch on PCI_AD24
+3VS
C685
2
1
5
0.1U_0402_16V4Z
1
B
Y
A
1 @
R423
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
U22
P
2
2
0_0402_5%
3
[20,24] PCI_AD24
1
R422
4
G
MEM_1V5
1
R424
2
33_0402_5%
VDDR_SW [45]
2
NC7SZ08P5X_NL_SC70-5
1
2
0_0402_5%
C686
150P_0402_50V8J
For VDDR Voltage Switch, AMD suggest
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB820 SATA/IDE/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
22
of
47
A
B
C
D
E
U20E
+1.1VS_VDDC
1
R369
U20C
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
71mA
1
R371
2
0_0402_5%
AF22
AE25
AF24
AC22
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
POWER
+VDDPL_3V_PCIE
43mA
AE28
+1.1VS_PCIE
L70
2
1
FBMA-L11-201209-221LMA30T_0805
+1.1VS
C604
C605
C606
C607
1
1
1
1
2
2
2
2
600mA
22U_0805_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+VDDPL_3V_SATA
C610
C611
C612
C613
C614
1
1
1
1
1
2
2
2
2
2
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
VDDRF_GBE_S
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
VDDIO_GBE_S_1
VDDIO_GBE_S_2
K28
K29
J28
K26
J21
J20
K21
J22
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
R372
1
R373
2
0_0402_5%
2
0_0402_5%
L7
L9
1
R374
2
0_0402_5%
M6
P8
1
R375
2
0_0402_5%
M10
AD14
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
C617
C618
C619
C620
C621
1
1
1
1
1
2
2
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
200mA
C11
D11
3
C625 2
C626 2
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
CORE S5
VB
658mA
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
A21
D21
B21
K10
L10
J9
T6
T8
VDDCR_11_S_1
VDDCR_11_S_2
VDDIO_AZ_S
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
VDDPL_33_SYS
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDPL_33_USB_S
VDDAN_33_HWM_S
VDDXL_33_S
1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z
F26
G26
M8
A11
B11
M21
L22
F19
D6
L20
+3VS
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
2
2
+VDDPL_3V_SATA
+3VS
2
2
C608
C609
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
+1.1VALW
Y4
C615 2
C616 2
113mA
1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z
EFUSE
+VDDIO_AZ
2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z
47mA
62mA
17mA
+VDDPL_3V
C623
C624
+VDDPL_11V
2
2
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
+VDDPL_3V_USB
5mA
197mA
+3V_HWM
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
+1.1VALW
+VDDCR_USB
197mA
+3VALW
+VDDLX_3V
M20
VSSPL_SYS
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V4Z
+1.1VALW
+VDDPL_3V_USB
2
VSSAN_HWM
M19
TBD
L76
2
1
FBMA-L11-160808-221LMT 0603
2
1
FBMA-L11-160808-221LMT 0603
2
1
1
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
1
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
3
Part 5 of 5
+3VALW
+3V_HWM
+3VALW
+3VS
1
C634
2.2U_0603_6.3V4Z
check can be removed?
32mA
L77
2
1
FBMA-L11-160808-221LMT 0603
1
C628
External Clock, connect to +1.1VS
directly, no need thick trace
C600
C601
C602
C603
SB820 A12(SA00003IW10)
+VDDPL_3V
2
1
FBMA-L11-160808-221LMT 0603
1
1
1
1
SB820M_FCBGA605
L80
1
2
2
2
2
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
SB820 A12(SA00003IW10)
L79
1
C596
C594
C597
C598
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
SB820M_FCBGA605
+VDDPL_11V
+VDDPL_3V_PCIE
1
1
1
1
SB800
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
D8
VDDPL_11_SYS_S
PLL
change to 0603 size
2
2
2
2
+3VALW
USB I/O
+3VALW
2 C590
VB
change to 0603 size
L69
2
1
+1.1VS
FBMA-L11-201209-221LMA30T_0805
VB change to 0603 size
10U_0603_6.3V6M 1
2 C595
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V1
1
+1.1VS
+1.1VS_CKVDD
400mA
check 220ohm bead
+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
2
0_0805_5%
10U_0603_6.3V6M
N13
R15
N17
U13
U17
V12
V18
W12
W18
93mA
+1.1VS_SATA
L71
2
1
FBMA-L11-201209-221LMA30T_0805
567mA
+1.1VS
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDIO_33_GBE_S
VDDPL_33_PCIE
U26
V22
V26
V27
V28
V29
W22
W26
CORE S0
1
1
1
3.3V_S5 I/O
C592
C593
C599
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
PCI/GPIO I/O
2 10U_0603_6.3V6M
CLKGEN I/O
1
GBE LAN
C591
SERIAL ATA
VB
FLASH I/O
+3VS
change to 0603 size
1
Part 3 of 5
SB800
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
PCI EXPRESS
131mA
GROUND
510mA
C635
2.2U_0603_6.3V4Z
2
+VDDIO_AZ
C630
C629
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
1
2
L78
2
1
FBMA-L11-160808-221LMT 0603
1
2
C632
C631
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
1
1
2
2
C633
2.2U_0603_6.3V4Z
+3VALW
L81
4
2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z
1
2
1
2
1
R376
4
2
0_0402_5%
1
C637
2.2U_0603_6.3V4Z
2
C638
2.2U_0603_6.3V4Z
For 3V AZ device
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB820 power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Sheet
Tuesday, March 02, 2010
E
23
of
47
A
B
C
REQUIRED STRAPS
PULL
HIGH
D
E
Check Internal PU/PD
AZ_SDOUT
PCI_CLK1
PCI_CLK2
PCI_CLK3
LOW POWER
MODE
ALLOW PCIE
GEN2
WATCHDOG
TIMER
ENABLE
USE
DEBUG
STRAP
1
PCI_CLK4
CPU/HT CLK
SEL
LPC_CLK0
LCP_CLK1
EC
ENABLE
CLOCKGEN
ENABLE
GPIO200
GPIO199
H,H = Reserved
Enable
H,L = SPI ROM
1
L,H = LPC ROM (Default L,NC)
DEFAULT
+3VS
+3VS
+3VS
+3VS
@
@
@
CLOCKGEN
DISABLE
L,L = FWH ROM
Disable
DEFAULT
+3VALW
INT@
DEFAULT
+3VALW
+3VALW
INT@
@
+3VALW
R385
2.2K_0402_5%
2
1
@
EC
DISABLE
R384
10K_0402_5%
2
1
R380
10K_0402_5%
2
1
DEFAULT
R379
10K_0402_5%
2
1
DEFAULT
R378
10K_0402_5%
2
1
DEFAULT
R377
10K_0402_5%
2
1
+VDDIO_AZ
IGNORE
DEBUG
STRAP
R383
10K_0402_5%
2
1
DEFAULT
CPU/HT CLK
SEL
WATCHDOG
TIMER
DISABLE
R382
10K_0402_5%
2
1
FORCE PCIE
GEN1
R381
10K_0402_5%
2
1
Performance
MODE
PULL
LOW
@
[21] HDA_SDOUT
[20] PCI_CLK1
[20] PCI_CLK2
[20] PCI_CLK3
[20] PCI_CLK4
[20,34] LPC_CLK0_EC
[20] LPC_CLK1
[21] GPIO200
[21] GPIO199
USE PCI
PLL
DISABLE ILA
AUTORUN
USE FC PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
PULL
LOW
BYPASS
PCI PLL
Check AD29,AD28 strap function
PCI_AD23
DEFAULT
DEFAULT
DEFAULT
DEFAULT
ENABLE ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
[20]
[20]
[20]
[20]
[20]
[20,22]
[20]
3
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
@
check default
@
@
R401
2.2K_0402_5%
2
1
PCI_AD24
R400
2.2K_0402_5%
2
1
PCI_AD25
R399
2.2K_0402_5%
2
1
PCI_AD26
R398
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD27
+3VS
R397
2.2K_0402_5%
2
1
3
@
R396
10K_0402_5%
2
1
R395
10K_0402_5%
2
1
DEBUG STRAPS
R394
2.2K_0402_5%
2
1
EXT@
+3VS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
R393
2.2K_0402_5%
2
1
R392
10K_0402_5%
2
1
EXT@
R391
10K_0402_5%
2
1
R390
10K_0402_5%
2
1
R389
10K_0402_5%
2
1
R388
10K_0402_5%
2
1
R387
10K_0402_5%
2
1
2
R386
10K_0402_5%
2
1
2
@
@
4
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
SB820 STRAPS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
24
of
47
A
B
C
D
E
W=40mils
+R_CRT_VCC
2
3
3
CRT Connector
2
+5VS
D11
2
1
1
RB491D_SC59-3
CRT_R_2
2 FCM2012CF-800T06_2P
CRT_G_2
CRT_B
L64 1
2 FCM2012CF-800T06_2P
CRT_B_2
R549
R549
UMA@ 140 Ohm
DIS @ 150 Ohm
R541
R550
C551
1
C552
2
10P_0402_50V8J
2
2
150_0402_1%
2
UMA@
140_0402_1%
150_0402_1%
DIS@
C550
0.1U_0402_16V4Z
1
2
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
2 FCM2012CF-800T06_2P
L63 1
1
L62 1
CRT_G
1
CRT_R
R549
2
1
1
D7
PJDLC05C_SOT23-3
@
W=40mils
1.1A_6VDC_FUSE
1
1
D6
PJDLC05C_SOT23-3
@
+CRT_VCC
F1
150_0402_1%
1
2
C553
1
2
10P_0402_50V8J
C554
1
C555
2
10P_0402_50V8J
1
C556
1
2
2
10P_0402_50V8J
10P_0402_50V8J
1
10P_0402_50V8J
G
G
16
17
C557
ME@ TYCO_1775763-1
2
100P_0402_50V8J
+CRT_VCC
P
2
A
1 10K_0402_5%
CRT_HSYNC_2
L66 1
2
FCM2012CF-800T06_2P
CRT_VSYNC_2
1
1
CRT_HSYNC_1
4
3
DSUB_12
2
U17
Y
L65 1
2
FCM2012CF-800T06_2P
C559
10P_0402_50V8J
G
CRT_HSYNC
1
R551 2
5
2 0.1U_0402_16V4Z
OE#
C558 1
2
2
2
1
C560
10P_0402_50V8J
74AHCT1G125GW_SOT353-5
+CRT_VCC
2
C562
68P_0402_50V8J
P
OE#
1
2 0.1U_0402_16V4Z
5
C563 1
DSUB_15
C561 2
68P_0402_50V8J 1
2
A
U18
Y
4
CRT_VSYNC_1
G
CRT_VSYNC
3
74AHCT1G125GW_SOT353-5
Close to Conn side
+CRT_VCC
For UMA Only
[11,12] GMCH_CRT_VSYNC
[11] GMCH_CRT_DATA
[11] GMCH_CRT_CLK
R542 2 UMA@ 1 0_0402_5%
CRT_G
GMCH_CRT_B
R679 2 UMA@ 1 0_0402_5%
CRT_B
GMCH_CRT_HSYNC
R547 2 UMA@ 1 0_0402_5%
CRT_HSYNC
GMCH_CRT_VSYNC
R543 2 UMA@ 1 0_0402_5%
CRT_VSYNC
GMCH_CRT_DATA
R546 2 UMA@ 1 0_0402_5%
CRT_DATA
GMCH_CRT_CLK
R678 2 UMA@ 1 0_0402_5%
CRT_CLK
1
GMCH_CRT_G
R457
4.7K_0402_5%
NOTE:
IF RS880M ONLY(NO MXM SUPPORT),
DAC_SDAT AND DAC_SCL DON'T
NEED LEVEL SHIFT, PU TO +5V DIRECTLY.
DAC_SDAT AND DAC_SCL ARE 5V TOLERANCE.
R553
4.7K_0402_5%
DSUB_12
6
DSUB_15
[14] VGA_CRT_G
[14] VGA_CRT_B
[14] VGA_CRT_HSYNC
[14] VGA_CRT_VSYNC
[14] VGA_CRT_DATA
[14] VGA_CRT_CLK
4
CRT_DATA
1
DIS@ Q87A
2N7002DW-T/R7_SOT363-6
3
VGA_CRT_R
R539 2 DIS@
1 0_0402_5%
CRT_R
VGA_CRT_G
R552 2 DIS@
1 0_0402_5%
CRT_G
VGA_CRT_B
R554 2 DIS@
1 0_0402_5%
CRT_B
VGA_CRT_HSYNC
R535 2 DIS@
1 0_0402_5%
CRT_HSYNC
VGA_CRT_VSYNC
R557 2 DIS@
1 0_0402_5%
CRT_VSYNC
VGA_CRT_DATA
R538 2 DIS@
1 0_0402_5%
CRT_DATA
VGA_CRT_CLK
R556 2 DIS@
1 0_0402_5%
CRT_CLK
UMA@1
2
R676
0_0402_5%
UMA@1
2
R544
0_0402_5%
4
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
CRT_CLK
4
DIS@ Q87B
2N7002DW-T/R7_SOT363-6
For VGA Only
[14] VGA_CRT_R
3
5
[11,12] GMCH_CRT_HSYNC
CRT_R
2
[11] GMCH_CRT_B
R677 2 UMA@ 1 0_0402_5%
2
[11] GMCH_CRT_G
+3VS
GMCH_CRT_R
1
[11] GMCH_CRT_R
2
3
C
D
CRT Connector
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
25
of
47
4
3
+3VS
+3VS
2
1
W=40mils
+HDMI_5V_OUT
1
2K_0402_5%
+5VS
2
1 +HDMI_5V_OUT_1 1
2
0_1206_5%
4
R529
HDMI_SCLK_1 2
6
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Q88B DIS@
3
R477 1
0_0402_5%
D
HDMI_SCLK
JHDMI1
HDMI_HPD
HDMI_SDATA_1 2
HDMI_SDATA
R469 1
0_0402_5%
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
Place closed to JHDMI1
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0-
UMA@1
2
R606
0_0402_5%
HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2-
R494 1
R493 1
UMA@2 0_0402_5%
UMA@2 0_0402_5%
HDMI_TX0+
HDMI_TX0-
[10] UMA_HDMI_P3
[10] UMA_HDMI_N3
R495 1
R496 1
UMA@2 0_0402_5%
UMA@2 0_0402_5%
HDMI_CLK+
HDMI_CLK-
TAITW_PDVBR9-19FLBS4NN4N1
ME@
C
C569 DIS@ 2
C570 DIS@ 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_TX2+
HDMI_TX2-
R479 1 UMA@ 2 715_0402_1%
R480 1 UMA@ 2 715_0402_1%
[14] VGA_HDMI_TXD1+
[14] VGA_HDMI_TXD1-
C571 DIS@ 2
C700 DIS@ 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_TX1+
HDMI_TX1-
R484 1 UMA@ 2 715_0402_1%
R481 1 UMA@ 2 715_0402_1%
[14] VGA_HDMI_TXD0+
[14] VGA_HDMI_TXD0-
C699 DIS@ 2
C702 DIS@ 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_TX0+
HDMI_TX0-
R486 1 UMA@ 2 715_0402_1%
R485 1 UMA@ 2 715_0402_1%
[14] VGA_HDMI_TXC+
[14] VGA_HDMI_TXC-
C701 DIS@ 2
C698 DIS@ 2
HDMI_CLK+
HDMI_CLK-
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
+3VS
R488 1 UMA@ 2 715_0402_1%
R487 1 UMA@ 2 715_0402_1%
R484
R481
R526
HDMI_HPD
E
D
2N7002_SOT23
Q78
2
G
+HDMI_5V_OUT
R474
1
2
150K_0402_5%
2
B
[11,14] HDMI_DET
3
R480
1
R479
C
Q20
MMBT3904_NL_SOT23-3
Place closed to JHDMI1
3
[14] VGA_HDMI_TXD2+
[14] VGA_HDMI_TXD2-
1
[10] UMA_HDMI_P2
[10] UMA_HDMI_N2
HDMI_R_D2+
1
[10] UMA_HDMI_P1
[10] UMA_HDMI_N1
HDMI_TX1+
HDMI_TX1-
20
21
22
23
1
HDMI_TX2+
HDMI_TX2-
UMA@2 0_0402_5%
UMA@2 0_0402_5%
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
R470 @
365K_0402_1%
R478
10K_0402_5%
S
2
UMA@2 0_0402_5%
UMA@2 0_0402_5%
R491 1
R492 1
1
C
R490 1
R497 1
C568
0.1U_0402_16V4Z
2
UMA@1
2
R718
0_0402_5%
[10] UMA_HDMI_P0
[10] UMA_HDMI_N0
1
RB491D_SC59-3
5
1 DIS@ 2
R499
0_0402_5%
[11] GMCH_HDMI_DATA
+HDMI_5V_OUT
R799
2
2
Q88A DIS@
1
[11] GMCH_HDMI_CLK
[14] VGA_HDMI_SDATA
2K_0402_5%
1
R476
2
2
1
[14] VGA_HDMI_SCLK
D
1
1 DIS@ 2
R498 0_0402_5%
R459
DIS@
10K_0402_5%
2
R460
DIS@
10K_0402_5%
D9
2
5
2
100K_0402_5%
499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1%
DIS@
DIS@
DIS@
DIS@
R486
R485
R488
R487
B
HDMI_CLK-
UMA use 715 ohm
VGA use 499 ohm
499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1%
DIS@
DIS@
DIS@
R475 1
1
L67
WCM-2012-900T_0805
@
4
2
4
3
B
3
HDMI_CLK+
R463 1
2
0_0402_5%
HDMI_R_CK+
HDMI_TX0-
R530 1
2
0_0402_5%
HDMI_R_D0-
R533 1
2
1
2
4
3
2
0_0402_5%
HDMI_R_D0+
0_0402_5%
HDMI_R_D1-
2
3
HDMI_TX1+
R467
1
2
0_0402_5%
HDMI_R_D1+
HDMI_TX2-
R528
1
2
0_0402_5%
HDMI_R_D2-
4
3
3
reverse for layout
1
2
R468 1
2
A
2
HDMI_R_D2+
0_0402_5%
Compal Electronics, Inc.
2010/03/12
Deciphered Date
Title
HDMI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3
2
HDMI_TX1-
Compal Secret Data
2008/10/06
Issued Date
3
reverse for layout
1
2
HDMI_TX2+
Security Classification
3
R532 1
4
@
WCM-2012-900T_0805
L85
1
A
4
HDMI_TX0+
1
L86
WCM-2012-900T_0805
@
4
4
2
DIS@
4
@
WCM-2012-900T_0805
L68
1
5
HDMI_R_CK-
0_0402_5%
2
1
2
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
1
26
of
47
5
4
3
2
1
LCD POWER CIRCUIT
+LCDVDD
+5VALW
W=60mils
0.1U_0402_16V4Z
+LCDVDD_CONN
L84
1
Q27
DTC124EKAT146_SC59-3
1
+LCDVDD
2
FBMA-L11-201209-221LMA30T_0805
DIS@
C680
R432
2.2K_0402_5%
1
4.7U_0805_10V4Z
1
1
2
2
2
[34] CMOS_OFF#
C678
IN
0.1U_0402_16V4Z
DTC124EKAT146_SC59-3
VB
+INVPWR_B+
C
2
1
C682
10U_0805_10V4Z
2 @
Q24
CMOS@
+INVPWR_B+
B+
2
0_0402_5%
@
1
R452
2
0_0402_5%
GMCH_INVT_PWM
W=60mils
VGA ONLY
INVT_PWM_R
DISPOFF#
1
[34] DAC_BRIG
2
+3VS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
DIS@ 1
DIS@ 1
R466 2 0_0402_5%
R505 2 0_0402_5%
VGA_TXCLK- [13]
VGA_TXCLK+ [13]
TXOUT2TXOUT2+
DIS@ 1
DIS@ 1
R509 2 0_0402_5%
R510 2 0_0402_5%
VGA_TXOUT2- [13]
VGA_TXOUT2+ [13]
TXOUT1+
TXOUT1-
DIS@ 1
DIS@ 1
R511 2 0_0402_5%
R512 2 0_0402_5%
VGA_TXOUT1+ [13]
VGA_TXOUT1- [13]
TXOUT0+
TXOUT0-
DIS@ 1
DIS@ 1
R513 2 0_0402_5%
R514 2 0_0402_5%
VGA_TXOUT0+ [13]
VGA_TXOUT0- [13]
I2CC_SCL
I2CC_SDA
DIS@ 2
DIS@ 2
R455 1 0_0402_5%
R441 1 0_0402_5%
VGA_LCD_CLK [14]
VGA_LCD_DAT [14]
C692
4.7U_0805_25V6-K
+CMOS_PW
@
680P_0402_50V7K
C690
TXCLKTXCLK+
2
JLVDS1
+LCDVDD_CONN
R442
10K_0402_5%
+3VS
B
2
1
@
1
R450
1
R436
2.2K_0402_5%
@
R438
2.2K_0402_5%
@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
GNDGND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
USB20_N5 [21]
USB20_P5 [21]
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+
31
ACES_87142-3041
ME@
B
I2CC_SCL
I2CC_SDA
+3VS
INVT_PWM_R
1
UMA ONLY
DAC_BRIG
R521 2 0_0402_5%
R537 2 0_0402_5%
TXOUT2TXOUT2+
UMA@1
UMA@
UMA@1
R555 2 0_0402_5%
R540 2 0_0402_5%
GMCH_TXOUT2- [11]
GMCH_TXOUT2+ [11]
TXOUT1+
TXOUT1-
UMA@1
UMA@1
R603 2 0_0402_5%
R600 2 0_0402_5%
GMCH_TXOUT1+ [11]
GMCH_TXOUT1- [11]
TXOUT0+
TXOUT0-
UMA@1
UMA@
UMA@1
R602 2 0_0402_5%
R601 2 0_0402_5%
GMCH_TXOUT0+ [11]
GMCH_TXOUT0- [11]
UMA@2
UMA@2
R453 1 0_0402_5%
R454 1 0_0402_5%
GMCH_LCD_CLK [11]
GMCH_LCD_DATA [11]
D10
CH751H-40PT_SOD323-2
GMCH_TXCLK- [11]
GMCH_TXCLK+ [11]
BKOFF#
1
2
DISPOFF#
2
[34] BKOFF#
4.7K_0402_5%
2
UMA@1
UMA@1
470P_0402_50V7K
R429
TXCLKTXCLK+
CMOS
TXOUT0TXOUT0+
C675
1 @
2
R431
10K_0402_5%
1 @
C677
2
470P_0402_50V7K
[11] GMCH_INVT_PWM
VGA_PNL_PWM
1
470P_0402_50V7K
[13] VGA_PNL_PWM
C691@
680P_0402_50V7K
INVT_PWM_R
2
[34] INVT_PWM
2
0_0402_5%
C
1 R437
2
0_0805_5%
1 R440
2
0_0805_5%
W=40mils
1
R451
R420
0_0603_5%
CMOS@
+CMOS_PW
1
C683
CMOS@
0.01U_0402_16V7K
2
VB
INVT_PWM
C687
0.1U_0402_16V4Z
2 CMOS@
2
CMOS@
R604
150K_0402_5%
1
2
D
1
1
1
2
AO3413_SOT23-3
Q26
OUT
2
C681
1
CMOS@
GND
3
1 0_0402_5%
CMOS@
R419
100K_0402_5%
3
IN
2
UMA@
2
1
1
OUT
R428 2
0_0402_5% LCD_ENVDD
GND
[13] VGA_ENVDD
1
3
2
1
3
[11] GMCH_ENVDD
R434 2
2
2
1
AO3413_SOT23-3
3
G
DTC124EK
220K_0402_5%
2
Q23
G
1
D
R433
2
G
+5VS
C589
4.7U_0805_10V4Z
D
D
Q25
2N7002_SOT23 S
1
S
D
CMOS Camera
W=60mils
R435
100K_0402_5%
S
R421
150_0603_1%
1
+3VS
DISPOFF#
1 @
C676
2
1
For EMI
VB
A
I2CC_SCL
I2CC_SDA
A
Compal Secret Data
Security Classification
2007/10/15
Issued Date
Deciphered Date
2008/10/15
Title
Compal Electronics, Inc.
LVDS/CAMERA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
1
27
of
47
A
B
C
D
Mini-Express Card for WLAN/WiMAX(Half)
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
+3VALW
+3VS_WLAN
+3VS_WLAN
+3VS
SB_PCIE_WAKE# R648 1
BT_ACTIVE
R650 1
SB_PCIE_WAKE#
[37] BT_ACTIVE
[19,21]
@
@
2 0_0402_5%
2 0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
WLAN_CLKREQ#
[19] CLK_PCIE_WLAN#
[19] CLK_PCIE_WLAN
1
PCI_RST#_R
[10] PCIE_PTX_C_IRX_N1
[10] PCIE_PTX_C_IRX_P1
[10] PCIE_ITX_C_PRX_N1
[10] PCIE_ITX_C_PRX_P1
+3VS_WLAN
R660
EC_TX_P80_DATA
EC_RX_P80_CLK
EC_TX_P80_DATA 1
EC_RX_P80_CLK 1
R661
100_0402_1%
2
2
100_0402_1%
53
2
[34,35]
[34,35]
R719
100K_0402_5%
GND
GND
2
C814
0.1U_0402_16V4Z
R644
R645
R647
R649
R651
R652
1
1
1
1
1
1
@
@
@
@
@
@
2
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#
LPC_FRAME# [20,34]
LPC_AD3 [20,34]
LPC_AD2 [20,34]
LPC_AD1 [20,34]
LPC_AD0 [20,34]
PLT_RST# [11,12,13,20,29,34]
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
R653 1
R654 1
R655 1
0_0402_5%
PLT_RST#
2 @ 0_0402_5%
0_0402_5%
2
R656 1
R657 1
2 @ 0_0402_5%
2 @ 0_0402_5%
1
2
WL_OFF#
[34]
PLT_RST# [11,12,13,20,29,34]
+3VALW
+3VS_WLAN
SB_SMCLK0 [8,9,19,21]
SB_SMDAT0 [8,9,19,21]
VB
R658 1
2 0_0402_5%
WLAN_LED#
R659 1
2
0_0402_5%
USB20_N11
USB20_P11
[21]
[21]
WLAN_LED#
[36]
WLAN
54
TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
1
VB
WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
1 R646
2
0_0805_5%
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
1
+1.5VS
JP10
[21,29]
E
Mini-Express Card for WWAN(Full)
2
2
+3VS_WWAN
+3VS_WWAN
@
+1.5VS
1
@
C815
10U_0805_10V4Z
2
JP9
[19,20]
@
@
2 0_0402_5%
2 0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
WWAN_CLKREQ#
[19] CLK_PCIE_WWAN#
[19] CLK_PCIE_WWAN
[10] PCIE_PTX_C_IRX_N3
[10] PCIE_PTX_C_IRX_P3
Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 1000mA
[10] PCIE_ITX_C_PRX_N3
[10] PCIE_ITX_C_PRX_P3
+3VS_WWAN
R672 1 3G@
R673 1 3G@
2 100_0402_1%
2 100_0402_1%
53
2
EC_TX_P80_DATA
EC_RX_P80_CLK
R724 @
100K_0402_5%
VB
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
1
2
3
Vn
2 0_0402_5%
R667 1
R668 1
@
2 0_0402_5%
2 0_0402_5%
+3VALW
+3VS_WWAN
R669 1
R670 1
@
@
2 0_0402_5%
2 0_0402_5%
SB_SMCLK0
SB_SMDAT0
USB20_N10
USB20_P10
1
R690 1
3G_OFF#
[21]
[21]
R704 2 0_0402_5%
@
2 0_0402_5%
[34]
PLT_RST#
4
5
6
7
CH2
6
CH3
+3VS
UIM_VPP
UIM_DATA
GND
VPP
I/O
DET
VCC
RST
CLK
WWAN
WWAN_LED#
[36]
GND
GND
@
8
9
2
2
1
C819
0.1U_0402_16V4Z
2
C820
0.1U_0402_16V4Z
3
New Card 34mm Socket (Left/TOP)
+1.5VS_CARD1
U38
+1.5VS_CARD1
1.5Vin
1.5Vin
1.5Vout
1.5Vout
3.3Vin
3.3Vin
3.3Vout
3.3Vout
11
13
40mil
2
JEXP1
1
C822
10U_0805_10V4Z
2
C823
0.1U_0402_16V4Z
[21] USB20_N7
[21] USB20_P7
New Card
CPUSB#
+3VS_CARD1
+3VALW
+3VS
2
4
+3VALW
17
[34,38,41,44,46]
SUSP#
+3VALW
R675 1
1
C827
0.1U_0402_16V4Z
[21] CPUSB#
PLT_RST#
6
SYSON
20
SUSP#
2 @ 100K_0402_5%
CPUSB#
C818
0.1U_0402_16V4Z
TAITW_PMPAT6-06GLBS7N14N0
ME@
1
12
14
SYSON
2
+UIM_PWR
1
[34,38,43]
D24
1
54
+1.5VS
C824
0.1U_0402_16V4Z
DAN217T146_SC59-3
3
1
2
40mil
1
+1.5VS
1
2
+UIM_PWR
UIM_RST
UIM_CLK
1
2
3
Imax = 0.75A
C821
0.1U_0402_16V4Z
1 +UIM_PWR
R663
2
5
Vp
JP2
R666 1 3G@
Express Card Power Switch
+3VS
2
UIM_DATA
4
CH4
+3VS
1
2
CH1
10K_0402_5%
C816
10U_0805_10V4Z
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
+1.5VS
1 R662
2
0_0805_5%
1
1
3
WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
R671
10K_0402_5%
2
1
SB_PCIE_WAKE# R664 1
BT_ACTIVE
R665 1
D23
@
CM1293-04SO_SOT23-6
+3VS
C817
4.7U_0805_10V4Z
Mini-Express Card(WWAN 3G)
1
10
9
18
AUX_IN
SYSRST#
SHDN#
AUX_OUT
OC#
PERST#
STBY#
NC
CPPE#
GND
3
5
60mil
40mil
SB_SMCLK0
SB_SMDAT0
+3VS_CARD1
+3VALW_CARD1
15
Imax = 1.35A
1
+1.5VS_CARD1
SB_PCIE_WAKE#
1
1
+3VALW_CARD1
19
8
PERST#
2
C825
10U_0805_10V4Z
2
C826
0.1U_0402_16V4Z
16
[19,20]
7
+3VALW_CARD1
Imax = 0.275A
CPUSB#
1
RCLKEN
G577BSR91U_QFN20
2
4
@
C828
10U_0805_10V4Z
1
2
C829
0.1U_0402_16V4Z
@
2 0_0402_5%
R674
PERST#
+3VS_CARD1
EXP_CLKREQ#
CPUSB#
[19] CLK_PCIE_EXP#
[19] CLK_PCIE_EXP
[20] PCIE_EXPCARD_SB_RXN
[20] PCIE_EXPCARD_SB_RXP
[20] PCIE_SB_EXPCARD_TXN
[20] PCIE_SB_EXPCARD_TXP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
4
GND
GND
SANTA_130801-5_LT
ME@
Compal Secret Data
Security Classification
Issued Date
2007/10/15
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
B
C
D
Document Number
Rev
0.2
NAWE6 LA-5754P
Date:
A
Compal Electronics, Inc.
Mini-Card/Nwe Card/SIM
Tuesday, March 02, 2010
Sheet
E
28
of
47
A
B
C
D
E
+1.7_VDDCT
+1.7_LX
@
1 JOPEN
1
2
EN_WOL# 2
G
Q43 @
2N7002_SOT23-3
D
2
S
1
C230
C220
C217
2
1
2
Close to Pin40
@
C495 @
Note:
Place Close to LAN chip
L53 DCR< 0.15 ohm
Rate current of L33 > 1A
4
Power On strapping
VB
3
[34] EN_WOL#
2
1
+1.7_LX
2
4.7UH_SIA4012-4R7M_20%
1
L53
1000P_0402_50V7K
R274 @
33K_0402_5%
1
0.1U_0402_16V4Z
2
G
C496
4.7U_0805_10V4Z
AO3414_SOT23-3
@
1
4
S
D
+5VALW
+1.7_VDDCT
+3V_LAN
3 Q42
1
10U_0805_10V4Z
J1
2
+3VALW
Layout Notice : Place as close
chip as possible.
0.1U_0402_16V4Z
Pin
Description
Chip Default
H:Over Clock Enable
LED0
L:Over Clock Disable
H
*
H:SWR Switch mode regulator Select *
U14
8152@
AR8151 Pin23=LED2.
no overclocking
PD 5.1K
R255
5.1K_0402_5%
1
2
S IC AR8152-AL1E QFN 40P E-LAN CTRL
Place Close to Chip
3
35
RX_P
32
33
REFCLK_N
REFCLK_P
PCIE_WAKE#
2 0_0402_5%
3
W AKE#
25
26
SMCLK
SMDATA
28
27
LAN_XTALO
LAN_XTALI
R96
1 8151@ 2
0_0402_5%
[19,21] LAN_CLKREQ#
2
CLKREQ_LAN#_R
0.1U_0402_16V4Z
1
2
C234 8152@
Near Near Near Near
Pin13 Pin19 Pin31 Pin34
C216
0.1U_0402_16V4Z
2
1U_0402_6.3V4Z
2
1
C223
C222
2
1
0.1U_0402_16V4Z
C208
2
1
10
LAN_RBIAS
VDD33
1
TEST_RST
TESTMODE
LX
XTLO
XTLI
4
CLKREQ#
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG
+1.7_LX
5
+1.7_VDDCT
24
37
AVDDH
AVDDH
AVDDH_REG
16
22
9
+1.1_DVDDL C218 1
C209 1
C224 1
1
LAN_XTALI
LAN_XTALO
Near
Pin6
Y4
1
2 0.1U_0402_16V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
Near
+2.7_AVDDH
+2.7_AVDDH
GND
AR8151-AL1A_QFN40_5X5
8151@
2
+1.7_VDDCT
1
2
1
2
1
2
2
2
1
2
Near
Pin9
1
2
Near
Pin22
2
2
2
2
2 R268
1
4.7K_0402_5%
PLT_RST#
2 R267 @1
4.7K_0402_5%
2
1
2
Place Close to LAN chip
R98
Near
Pin16
MDI0+
1
MDI0-
R262 1
MDI1+
R97
MDI1-
R100 1
C202
33P_0402_50V8J
MDI2+
R266 1
8151@
R101 1
8151@
R263 1
8151@
R99 1
8151@
MDI2-
VB
MDI3+
MDI3-
1
@
PCIE_WAKE#
Pin37
1
C203
33P_0402_50V8J
2
1
C215
0.1U_0402_16V4Z
25MHZ_20PF_7A25000012
1
1
1
DVDDL
DVDDL_REG
1
41
C233 & C276 Close pin1 < 200mil
C273 & 480 Close pin < 400mil
+1.7_LX
40
VB
CLKREQ_LAN#_R 2 R254
1
4.7K_0402_5%
+3V_LAN
R257
2 2.37K_0402_1%
1
+3V_LAN
VDDCT
13
19
31
34
6
+1.1_AVDDL
0.1U_0402_16V4Z
8151@
C205
2
1
0.1U_0402_16V4Z
8151@
C212
1
0.1U_0402_16V4Z
+1.1_AVDDL
+1.1_AVDDL
7
8
RBIAS
+3V_LAN
C233
2 0_0402_5%
8151@
@
CLKREQ_LAN#_R
[30]
[30]
[30]
[30]
[30]
[30]
[30]
[30]
C211
R483 1
R83
1 8152@ 2
0_0402_5%
0.1U_0402_16V4Z
R482 1
[34] EC_PME#
PERST#
C221
[21,28] SB_PCIE_WAKE#
2
0.1U_0402_16V4Z
PLT_RST#
PLT_RST#
MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+
C225
CLK_PCIE_LAN#_C
CLK_PCIE_LAN_C
MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+
0.1U_0402_16V4Z
[11,12,13,20,28,34]
1 0_0402_5%
1 0_0402_5%
12
11
15
14
18
17
21
20
C219
R261 2
R260 2
[19] CLK_PCIE_LAN#
[19] CLK_PCIE_LAN
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
ACTIVITY [30]
LAN_LINK# [30]
10U_0805_10V4Z
[10] PCIE_ITX_C_PRX_P2
8151-AL1A
38
39
23
C273
RX_N
ACTIVITY
LAN_LINK#
LED_0
LED_1
LED_2
10U_0805_10V4Z
C480
36
Atheros
C510
TX_P
[10] PCIE_ITX_C_PRX_N2
TX_N
1000P_0402_50V7K
[10] PCIE_PTX_C_IRX_P2
2 0.1U_0402_16V7K PCIE_PTX_IRX_P0 30
1U_0402_6.3V4Z
2 0.1U_0402_16V7K PCIE_PTX_IRX_N0 29
C7111
C276
C7101
0.1U_0402_16V4Z
[10] PCIE_PTX_C_IRX_N2
1U_0402_6.3V4Z
3
LED0,1,2 intel Pull UP
U14
--
AR8152, Pin23 is CLKREQ
For AR8152, pin23 is the LDO output. Mount C234
and no mount R96.close to this pin4
1
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
C204
1000P_0402_50V7K
1
2 C227 0.1U_0402_16V4Z
1
2 C214 0.1U_0402_16V4Z
C213
1
1
C231
8151@
2 C229
8151@
C232
8151@
2 C228
8151@
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
1
8152 no mount MDI3+,MDI3-,MDI2-,MDI2+ resister and cap
For AR8151, pin4 is the CLKREQn pin, mount R96
and no mount C234.close to this pin4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2006/08/04
Issued Date
Deciphered Date
2006/10/06
Title
LAN-AR8151/8152
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tuesday, March 02, 2010
Date:
A
B
C
D
Rev
0.2
NAWE6 LA-5754P
Sheet
E
29
of
47
5
4
3
2
1
+1.7_VDDCT
R57
C128 2
D
1
2 0_0603_5%
1 1U_0402_6.3V4Z
D
MDI[0..3] +/- Reverse
8151@
C127 2
1 0.01U_0402_16V7K
8151@
C206
1000P_0402_50V7K
8151@
C130 2
1 0.01U_0402_16V7K
8151@
C226
1000P_0402_50V7K
C129 2
Close to T9
T9
1000P_0402_50V7K
24
MCT3
MX1+
23
MDO0-
MX1-
22
MDO0+
MCT2
21
MCT2
20
MDO1-
TCT1
[29] MDI0-
2
TD1+
[29] MDI0+
3
TD1-
4
TCT2
MX2+
1:1
1:1
[29] MDI1-
5
TD2+
[29] MDI1+
6
TD2-
MX2-
19
MDO1+
7
TCT3
MCT3
18
MCT1
[29] MDI2-
8
TD3+
MX3+
17
MDO2-
[29] MDI2+
9
TD3-
MX3-
16
MDO2+
10
TCT4
MCT4
15
MCT0
11
TD4+
MX4+
14
MDO3-
1 0.01U_0402_16V7K
C237
MCT1
1
1:1
R275
2 8151@ 1 75_0402_5%
R56
2 8151@ 1 75_0402_5%
R55
1 75_0402_5%
2
C
C
C132 2
1 0.01U_0402_16V7K
C238
1000P_0402_50V7K
[29] MDI3-
1:1
R54
2
1 75_0402_5%
C131
Place close to TCT pin
1000P_1206_2KV7K
12
[29] MDI3+
TD4-
MX4-
13
MDO3+
1
2
LG-2446S
8151@
RJ45 Conn.
B
B
JRJ45
R501
[29] ACTIVITY
2
@ C644
68P_0402_50V8K
[29] LAN_LINK#
2
R502
2
1
2
A
1 300_0402_5%
1
2009/03/20
Issued Date
Deciphered Date
4
3
Amber LED+
SHLD4
16
MDO3-
8
PR4-
SHLD3
15
MDO3+
7
PR4+
MDO1-
6
PR2-
MDO2-
5
PR3-
MDO2+
4
PR3+
MDO1+
3
PR2+
MDO0-
2
PR1-
1
SHLD2
14
MDO0+
PR1+
SHLD1
13
10
+3V_LAN
9
Green LEDGreen LED+
FOX_JM36113-P2221-7F
ME@
C646
68P_0402_50V8K
@
A
Compal Electronics, Inc.
2010/03/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Amber LED-
11
1 300_0402_5%
Compal Secret Data
Security Classification
12
2
Title
LAN_Transformer
Size
Document Number
Custom
Date:
Monday, March 01, 2010
Rev
0.2
NAWE6 LA-5754P
Sheet
1
30
of
47
A
B
C
D
E
1
1
1
VDD
SMCLK
10
EC_SMB_CK2 [6,14,34]
2
DP1
SMDATA
9
EC_SMB_DA2 [6,14,34]
REMOTE1-
3
DN1
ALERT#
8
REMOTE2+
REMOTE2+
4
DP2
THERM#
7
DN2
GND
6
@
C514
100P_0402_50V8J
REMOTE2-
5
1
E
3
1
2
1
Q39
MMST3904-7-F_SOT323-3
2
B
REMOTE1-
REMOTE1+
Close U23
2
C
Under WWAN
REMOTE2-
1
2
2
1
C511
0.1U_0402_16V4Z
1
C
Q28
MMST3904-7-F_SOT323-3
2
B
E
3
2
@
C512
100P_0402_50V8J
R585
10K_0402_5%
@
2
U23
Close to DDR
REMOTE1+
R584
10K_0402_5%
@
+3VS
2
+3VS +3VS
1
SMSC thermal sensor
placed near by VRAM
REMOTE1+
EMC1403-2-AIZL-TR_MSOP10
1
C513
2200P_0402_50V7K
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
Address 1001_101xb
2
REMOTE1-
P/N SA000029210
REMOTE2+
1
C651
2200P_0402_50V7K
2
REMOTE2-
3
3
FAN1 Conn
+5VS
4
4
JP12
2
C647
10U_0805_10V4Z
1
[34] FAN_SPEED1
[34] EC_FAN_PWM
1
1 R508
2 0_0402_5% FAN_SPEED_R2
R507 2 0_0402_5% FAN_PWM_R 3
1
4
5
6
1
2
3
4
G5
G6
ACES_85205-04001
ME@
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
EMC1403_sensor/FAN
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
31
of
47
A
B
C
D
ON/OFF switchSW1@
Power Button
1
3
2
4
E
F
G
Power Bottom Board Conn. 8pin
H
Cap Sensor Board Conn. 8pin
6
5
SMT1-05_4P
TOP Side
ACES_85201-08051
+5VS
2
J2
1
SHORT PADS
Bottom Side
R519
100K_0402_5%
D14
ON/OFFBTN#
3
ON/OFF#
2
51_ON#
1
[34] NUM_LED#
[34] CAPS_LED#
[34] PM_BTN#
1
2
3
4
5
6
7
8
9
10
PM_BTN#
NOVO_BTN#
ON/OFFBTN#
ON/OFF# [34]
51_ON# [39]
DAN202UT106_SC70-3
1
2
3
4
5
6
7
8
GND
GND
2 0_0402_5% CAP_INT#_R
2 0_0402_5%
2 0_0402_5%
R518 1
R524 1
R525 1
[34] CAP_INT#
[34] ESB_DAT
[34] ESB_CLK
[34] CAP_RST#
+3VS
+5VS
@
C652
33P_0402_50V8J
ACES_85201-08051
D
S
2
2
1
1
GND
GND
8
7
6
5
4
3
2
1
JP1
1
@
C653
33P_0402_50V8J
+3VALW +3VS
1
R520
10K_0402_5%
1
2
2
G
Q37
2N7002_SOT23-3
1
EC_ON
3
ME@
PM_BTN#
R522
100K_0402_1%
@
Card Reader/Audio Jack SB CONN
2
1
R637
100K_0402_1%
2
[34] EC_ON
10
9
8
7
6
5
4
3
2
1
JP3
2
1
1
ME@
VB
+3VALW
12/28
D8
3
2
1
[34] NOVO#
2
PJDLC05C_SOT23-3
@
D16
PJSOT24C 3P C/A SOT-23
@
JP8
1
D17
2
NOVO_BTN#
1
51_ON#
PLUG_IN
HP_OUTR
HP_OUTL
[33] PLUG_IN
[33] HP_OUTR
[33] HP_OUTL
1
2
D15
PJSOT24C 3P C/A SOT-23
@
R523
100K_0402_5%
NOVO#
2
2
PM_BTN#
3
3
ON/OFFBTN#
2
NOVO_BTN#
+3VALW
1
MIC_JD
EXT_MIC_L
EXT_MIC_R
[33] MIC_JD
[33] EXT_MIC_L
[33] EXT_MIC_R
3
DAN202UT106_SC70-3
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
+3VALW
1
2
3
4
5
6
7
8
9
10
11
12
CardReader
[21] USB20_P2
[21] USB20_N2
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
13
14
ACES_85201-1205N
ME@
SATA HDD Conn.
SATA ODD Conn.
JHDD1
JODD1
[22] SATA_STX_DRX_P0
[22] SATA_STX_DRX_N0
3
[22] SATA_STX_DRX_P1
[22] SATA_STX_DRX_N1
C654 1
C655 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
[22] SATA_DTX_C_SRX_N1
[22] SATA_DTX_C_SRX_P1
C656 1
C657 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
+5VS
R448 1
10U_0805_10V4Z
C668
8
9
10
11
12
13
+5VS_ODD
2 0_0805_5%
0.1U_0402_16V4Z
1
C666
2
1
C669
2
1U_0402_6.3V4Z
1
2
1
2
3
4
5
6
7
C667
GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
[22] SATA_DTX_C_SRX_N0
[22] SATA_DTX_C_SRX_P0
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
C660 1
C661 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
GND
GND
17
16
+5VS
OCTEK_SLS-13SB1G_RV
ME@
1
C658 1
C659 1
R447 1
+5VS_HDD
2 0_0805_5%
10U_0805_10V4Z
2
C662
1000P_0402_50V7K
1
0.1U_0402_16V4Z
1
C663
2
C664
2
1
2
1U_0402_6.3V4Z
C665
1
2
GND
RX+
RXGND
TXTX+
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
3
GND
GND
23
24
OCTEKCONN_SAT-22SW1G
ME@
1000P_0402_50V7K
OCTEKCONN
SP01000QT00
SMT, 22P, Standart Type, H:9.2mm, P=1.27
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/15
2008/10/15
Deciphered Date
Title
HDD/ODD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
E
F
Tuesday, March 02, 2010
G
Rev
0.2
NAWE6 LA-5754P
Sheet
32
H
of
47
5
4
+3VS
3
2
2
[34] BEEP#
C
R696
1 1
2
1
2
B
E
560_0402_5%
1U_0603_10V4Z
C1243
R697
2.4K_0402_1%
1
C1244
@
1
C1250
1 1
2
1
2
1U_0603_10V4Z
560_0402_5%
1
2
MIC2_L
1
1
2
R612
0_0402_5%
INTT_MIC
[32] EXT_MIC_L
[32] EXT_MIC_R
1
1
+3VS
WM-64PCY_2P
45@
MIC2_R
R708
4.7K_0402_5%
@
D18
2
1
[34] EC_MUTE#
1
C1263
PC_BEEP
2
100P_0402_50V8J
C1266
1
C1266 close Codec
ECN for ALC259
R723
4.7K_0402_5%
@
2
2
0_0603_5%
25
38
AVDD2
AVDD1
39
46
PVDD2
1
SPK_OUT_R+
SPK_OUT_R-
45
44
SPK_R2+
SPK_R1-
21
22
MIC1_L
MIC1_R
HP_OUT_L
HP_OUT_R
32
33
16
17
MIC2_L
MIC2_R
SYNC
10
BCLK
6
SDATA_OUT
5
SDATA_IN
8
GPIO0/DMIC_DATA
3
GPIO1/DMIC_CLK
PD#
C1255
1
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
LINE2_L
LINE2_R
2.2U_0603_6.3V4Z
+MIC1_VREFO_L
2
0_0603_5%
EAPD
47
SPDIFO
48
MONO_OUT
20
RESET#
PCBEEP
13
SENSE A
18
SENSE B
36
1
1
R722
C1254
14
15
12
SENSE_A
+5VS
2
0_0603_5%
1
SPK_L2+
SPK_L1-
2
0.1U_0402_16V4Z
+5VS
1
1
C1248
@
C1249
@
HP_OUT_L
HP_OUT_R
place close to chip
Internal SPEAKER
R705
R706
75_0402_1%
75_0402_1%
HP_OUTL [32]
HP_OUTR [32]
HDA_SYNC_AUDIO
[21]
HDA_SDOUT_AUDIO
[21]
Headphone
C
HDA_BITCLK_AUDIO
AZ_SDIN0_HD_R 2
R710
1
33_0402_5%
HDA_SDIN0
2 R792 @1
33_0402_5%
[21]
[21]
C1262 @
1
2
22P_0402_50V8J
C1264
100P_0402_50V8J
@
2
1
R721
2 0.1U_0603_50V7K
C1258
40
41
11
12/28
2 0.1U_0603_50V7K
1
SPK_OUT_L+
SPK_OUT_L-
4
HDA_RST_AUDIO#
2
2
0_0603_5%
C1253
LINE1_L
LINE1_R
R630 1 EC_MUTE#_R
0_0402_5%
near pin
1
R720
U49
R698
2
1
0_0603_1%
@
C1247
23
24
RB751V_SOD323
1
2
@
[21] HDA_RST_AUDIO#
1
PVDD1
DVDD
C517
2.2U_0603_10V7K
1K_0402_5%
R716 1
MIC1_L
2
1
2
MIC1_R
2 R717
1
1
2
C518 2.2U_0603_10V7K
1K_0402_5%
MIC2_L
2 C515
MIC2_R
2 2.2U_0603_10V7K
C516 @
VB 2.2U_0603_10V7K
R709
@
2
1
0_0402_5%
2
2
1K_0402_5%
2 R707
1
MIC1
9
1
C
D
2
2
10U_0805_10V4Z
R700
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VS
0_0603_1%
2
2
1
1
VB
R703
4.7K_0402_5%
1
2
R701
4.7K_0402_5%
DVDD_IO
2
+MIC1_VREFO_L
R702
4.7K_0402_5%
2
10U_0805_10V4Z
2
10U_0805_10V4Z
D29 @
RB751V_SOD323
+MIC2_VREFO
1
R713
0.1U_0402_16V4Z
+AVDD_HDA
C1252
10U_0805_10V4Z
2
2
+MIC1_VREFO_R
B
1
@
C1251
2
place close to chip
+PVDD2
1
C1245
0.1U_0402_16V4Z
1
2SC2411KT146_SOT23-3
R699
SB Beep
C1268 1
2
10U_0805_10V4Z
Q86
2
[21] SB_SPKR
C1265 1
2
+3VS_DVDD
10U_0805_10V4Z
2
2
place close to chip
1
C1242
2
3
EC Beep
1
2
D
J5
JUMP_43X39
0.1U_0402_16V4Z
2
R695
2
1
0_0603_1%
+3VS
+5VS
C1240
1
1
1
2
C1241 1U_0603_10V4Z
PC_BEEP
2
1
0.1U_0402_16V4Z
1
1
C1239
C1238
2
R693
PC_BEEP1
R692
2
1
0_0603_1%
0.1U_0402_16V4Z
1
1
C1237
1
1
+PVDD1
R694
20K_0402_5%
10K_0402_5%
D28
RB751V_SOD323
@
1
+5VS
PC Beep
@ C1246
0.1U_0402_16V4Z
2
CBP
R711 2
1
EAPD [34]
Near PIN
For EMI
+MIC2_VREFO
MIC2_VREFO
29
MIC1_VREFO_R
LDO_CAP
30
28
LDO_CAP
C1267 10U_0805_10V4Z
1
2
+MIC1_VREFO_R
35
CBN
VREF
27
AC_VREF2.5V
31
MIC1_VREFO_L
JDREF
19
AC_JDREF2 R712
43
42
49
7
PVSS2
PVSS1
DVSS2
DVSS1
CPVEE
34
A_RVO
1
C1269
AVSS1
AVSS2
26
37
EC_MUTE#_R
0_0402_5%
1 20K_0402_1%
1
2
2.2U_0603_6.3V4Z
1
C1270
B
C1271
@
2 10U_0805_10V4Z
0.1U_0402_16V4Z 2
ALC259-GR_QFN48_7X7
place close to chip
GND
GNDA
1
A
2
@
1
2
@
1
2
C1274
1000PF_0402_25V7
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
C1273
1000PF_0402_25V7
2
2
2
2
C1272
1000PF_0402_25V7
1
1
1
1
@
1
2
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
1
2
3
4
1
2
3
4
C1275
1000PF_0402_25V7
JSPK1
L87
L88
L89
L90
AGND
External MIC
wide 20MIL
SPK_R1SPK_R2+
SPK_L1SPK_L2+
SA00003QR00
DGND
5
6
GND1
GND2
Sense Pin
Impedance
Function
Codec Signals
place close to chip
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
[32] MIC_JD
SENSE A
[32] PLUG_IN
ACES_88231-04001
ME@
2
R714
1
20K_0402_1%
R715
39.2K_0402_1%
A
5.1K
SP02000K200
(PIN 48)
@
Compal Electronics,Ltd.
Compal Secret Data
Security Classification
2008/03/25
Issued Date
Deciphered Date
2008/04/
Title
ALC259 Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Rev
0.2
NAWE6 LA-5754P
Date: Tuesday, March 02, 2010
5
SENSE_A
Sheet
1
33
of
47
+3VALW
+EC_AVCC
EC_RST#
EC_SCI#
EC_ID
R562
@
1
2
4.7K_0402_5%
R564
@
1
2
4.7K_0402_5%
1
EC_ID to identify KB926 D or E
KSO[0..17]
[35] KSO[0..17]
KSI[0..7]
[35] KSI[0..7]
+3VALW
R568 1
2 47K_0402_5% KSO1
R569 1
2 47K_0402_5% KSO2
+3VALW
VB
2 R579
1
2.2K_0402_5%
EC_SMB_CK1
2 R580
1
2.2K_0402_5%
EC_SMB_DA1
[40]
[40]
[6,14,31]
[6,14,31]
+3VS
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
2
[21] PM_SLP_S3#
[21] PM_SLP_S5#
[21] EC_SMI#
R571
10K_0402_5%
EC_SMI#
ESB_CLK
ESB_DAT
1
[32] ESB_CLK
[32] ESB_DAT
[47] VGATE
[27] INVT_PWM
[31] FAN_SPEED1
[28] 3G_OFF#
[28,35] EC_TX_P80_DATA
[28,35] EC_RX_P80_CLK
[32] ON/OFF#
[6] EC_PROCHOT#
[32] NUM_LED#
FAN_SPEED1
FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
XCLKI
XCLKO
FRD#SPI_SO
2
@ 100K_0402_1%
1
R576
FSEL#SPICS#
2
@ 100K_0402_1%
67
9
22
33
96
111
125
77
78
79
80
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
ESB_CLK
2
4.7K_0402_5%
ESB_DAT
R578
1
68
70
71
72
DAC_BRIG
PS2 Interface
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
ACOFF [39,41]
BATT_TEMP [40]
ADP_I [41]
KILL_SW# [35]
IREF
VDDIO
TP_CLK
TP_DATA
97
98
99
109
BATT_SEL_EC
LID_SW#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
FRD#SPI_SO
FWR#SPI_SI
SPICLK
FSEL#SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
PM_BTN#
CAP_INT#
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
VDDIO
+3VALW
R565 1
@
2
10K_0402_5%
2 4.7K_0402_5%
BATT_TEMP
2 10K_0402_5%
ACIN
@
@1
C725
1
C726
1
C727
BATT_SEL_EC 1
R567
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
4.7K_0402_5%
BT_OFF# [37]
EN_WOL# [29]
BATT_SEL_EC [41]
LID_SW# [35]
+3VS
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
2 4.7K_0402_5%
+3VALW
EC_MUTE# [33]
USB_ON# R566 1
USB_ON# [37]
NOVO# [32]
VDDIO [43]
Reserve 1.5VP control
TP_CLK [35]
TP_DATA [35]
USB_ON#
R561 1
TP_DATA R563 1
IREF [41]
CHGVADJ [41]
SPI Device Interface
GPIO
+5VS
TP_CLK
DAC_BRIG [27]
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPI Flash ROM
+3VS
EC_FAN_PWM [31]
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
XCLK1
XCLK0
V18R
100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118
CHARGE_LED0#
CHARGE_LED1#
SYSON
VR_ON
ACIN
EC_LID_OUT#
EC_ON
EC_PWROK
BKOFF#
CAP_RST#
FRD#SPI_SO [36]
FWR#SPI_SI [36]
SPICLK [36]
FSEL#SPICS# [36]
R570
10K_0402_5%
PM_BTN# [32]
CAP_INT# [32]
FSTCHG [41]
CHARGE_LED0# [36]
CAPS_LED# [32]
CHARGE_LED1# [36]
PWR_LED# [36]
SYSON [28,38,43]
VR_ON [47]
ACIN [14,39]
CAP_INT#
VR_ON 2
1
R572 100K_0402_5%
EC_RSMRST# [21]
EC_LID_OUT# [21]
EC_ON [32]
CMOS_OFF# [27]
1
R573
BKOFF# [27]
WL_OFF# [28]
2
0_0402_5%
SB_PWRGD [6,11,21]
CAP_RST# [32]
VLDT_EN [38,44,45,46]
ENBKL [11]
EAPD [33]
SUSP#
PBTN_OUT#
EC_PME#
SUSP# [28,38,41,44,46]
PBTN_OUT# [21]
EC_PME# [29]
@R574
R574 210K_0402_5%
1 @
124
+3VALW
1
2
C728
4.7U_0805_10V4Z
SUSP#
1
ECAGND
2
4.7K_0402_5%
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
1 R558 @2
10K_0402_5%
VGA_DBCLK [19]
BEEP# [33]
EC_MUTE#
SM Bus
KB926QFA1_LQFP128
R577
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
BATT_TEMP
AD Input
+3VS
1
AVCC
MISC
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
BEEP#
EC_FAN_PWM
ACOFF
63
64
65
66
75
76
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
21
23
26
27
PWM Output
GND
GND
GND
GND
GND
+3VALW
1
R575
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
EC_ID
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
VGA_DBCLK
EC must program to 500KHZ output
Start and stop follow SUP high/Low
1
C723
0.1U_0402_16V4Z
[21] EC_SCI#
+3VALW
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
U28
2
[20,24] LPC_CLK0_EC
[11,12,13,20,28,29] PLT_RST#
2
47K_0402_5%
2
12
13
37
20
38
10_0402_5%
2
69
1
R560
[20] SERIRQ
[20,28] LPC_FRAME#
[20,28] LPC_AD3
[20,28] LPC_AD2
[20,28] LPC_AD1
[20,28] LPC_AD0
2
11
24
35
94
113
+3VALW
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
KB_RST#
[21] KB_RST#
2
1
2
1
@C724
@
C724 22P_0402_50V8J @ R559
2
AGND
[21] GATEA20
2
1
VCC
VCC
VCC
VCC
VCC
VCC
2
1
C720
1000P_0402_50V7K
2
1
C719
1000P_0402_50V7K
C722
1000P_0402_50V7K
2 1 ECAGND 2
FBM-11-160808-601-T_0603
1
L82
1
C718
0.1U_0402_16V4Z
C721
0.1U_0402_16V4Z
C717
0.1U_0402_16V4Z
+EC_AVCC
1
1
C716
0.1U_0402_16V4Z
2
C715
0.1U_0402_16V4Z
L83 1
2
FBM-11-160808-601-T_0603
+3VALW
1
2
@
C729
1000P_0402_50V7K
ENE926 ( E0 ) SA00001J5A0
+3VS
VB
2 C730
27P_0402_50V8J
1
R582
2.2K_0402_5%
1
2
@
C731
100P_0402_50V8J
1
2
2
NC
IN
@
R583
20M_0603_5%
1
2
EC_SMB_CK2
EC_SMB_DA2
XCLKO
32.768KHZ_12.5PF_1TJS125DJ4A420P
3 NC
OUT 4
1
R581
2.2K_0402_5%
@
C732
100P_0402_50V8J
X1
1
2 C733
27P_0402_50V8J
XCLKI
Compal Secret Data
Security Classification
Issued Date
2007/10/15
Deciphered Date
2008/10/15
Title
Compal Electronics, Inc.
BIOS & EC I/O Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Tuesday, March 02, 2010
Rev
0.2
NAWE6 LA-5754P
Sheet
34
of
47
5
4
3
2
1
D
D
reversal of NIWE1
JP5
INT_KBD Conn.
KSI[0..7]
KSI[0..7]
KSO[0..17]
C
[34]
KSO[0..17] [34]
KSO16
C639 1
2 @ 100P_0402_50V8J
KSO17
C640 1
2 @ 100P_0402_50V8J
KSO2
C734 1
2 @ 100P_0402_50V8J
KSO1
C735 1
2 @ 100P_0402_50V8J
KSO15
C736 1
2 @ 100P_0402_50V8J
KSO7
C737 1
2 @ 100P_0402_50V8J
KSO6
C738 1
2 @ 100P_0402_50V8J
KSI2
C739 1
2 @ 100P_0402_50V8J
KSO8
C740 1
2 @ 100P_0402_50V8J
KSO5
C741 1
2 @ 100P_0402_50V8J
KSO13
C742 1
2 @ 100P_0402_50V8J
KSI3
C743 1
2 @ 100P_0402_50V8J
KSO12
C744 1
2 @ 100P_0402_50V8J
KSO14
C745 1
2 @ 100P_0402_50V8J
KSO11
C746 1
2 @ 100P_0402_50V8J
KSI7
C747 1
2 @ 100P_0402_50V8J
KSO10
C748 1
2 @ 100P_0402_50V8J
KSI6
C749 1
2 @ 100P_0402_50V8J
KSO3
C750 1
2 @ 100P_0402_50V8J
KSI5
C751 1
2 @ 100P_0402_50V8J
KSO4
C752 1
2 @ 100P_0402_50V8J
KSI4
C753 1
2 @ 100P_0402_50V8J
KSI0
C754 1
2 @ 100P_0402_50V8J
KSO9
C755 1
2 @ 100P_0402_50V8J
KSO0
C756 1
2 @ 100P_0402_50V8J
KSI1
C757 1
2 @ 100P_0402_50V8J
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
EC DEBUG PORT
JP11
+3VALW
[28,34] EC_TX_P80_DATA
[28,34] EC_RX_P80_CLK
1
2
3
4
EC_TX_P80_DATA
EC_RX_P80_CLK
1
2
3
4
ACES_85205-0400
ME@
C
G1
G2
Lid Switch
31
32
ACES_85201-3005N
ME@
1
R586
+3VALW
+VCC_LID
2
0_0402_5%
R587 1
2
CONN PIN define need double check
2 100K_0402_5%
VDD
A3212ELHLT-T_SOT23W -3
1
To TP/B Conn.
OUTPUT
3
LID_SW # [34]
GND
C760
0.1U_0402_16V4Z
2
1
+5VS
2
U29
1
C761
10P_0402_50V8J
C762
0.1U_0402_16V4Z
JP4
B
TP_CLK
TP_DATA
[34] TP_CLK
[34] TP_DATA
1
2
@
C763
100P_0402_50V8J
1
2
@
C764
100P_0402_50V8J
4
3
2
1
Kill Switch
4
3
2
1
B
+3VALW
100K_0402_5%
2 R691
E&T_6905-E04N-00R
ME@
[34] KILL_SW #
1
LSSM12-P-V-T-R_3P
3
3
2
2
1
1
KILL_SW#
CONN PIN define need double check
Kill
STATUS
1,2(LOW)
2,3(HI)
OFF
ON
SW 2
12/28
D12
3
TP_CLK
2
TP_DATA
1
PJDLC05C_SOT23-3
@
12/28
A
A
Compal Secret Data
Security Classification
2007/10/15
Issued Date
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
KB /SW /LPC Debug Conn.
Size
B
Date:
Document Number
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
1
35
of
47
SA00002TO00 pakage 200mil
S IC FL 16MBIT MX25L1605AM2C-12G SO8 ROM
+3VALW
20mils
C765
0.1U_0402_16V4Z
R589
10K_0402_5%
2
2
1
1
U30
FSEL#SPICS#
FRD#SPI_SO
1
R590
SPI_SO
2
0_0402_5%
1
2
3
4
CS#
SO
WP#
GND
8
7
6
5
VCC
HOLD#
SCLK
SI
HOLD#
SPI_CLK_R
SPI_SI_EC
1
1
MX25L1605AM2C-12G_SO8
R591 0_0402_5%
2
2
SPICLK
FWR#SPI_SI
SPICLK [34]
FWR#SPI_SI [34]
SPI_CLK_R
1
R592 0_0402_5%
VB
R594
0_0402_5%
@
2
Colse to EC
1
1
@ C766
10P_0402_50V8J
2
C767
12P_0402_50V8J
@
EMI
LED
FD1
3G
FD2
1
2
FD3
1
1
FD4
1
LED1
A:H_2P8
+5VALW
19-213A-T1D-CP2Q2HY-3T_WHITE
LED2
BATT_LOW_LED#
1
[34] CHARGE_LED0#
3
2
300_0402_5%
1
R595
+3VALW
4
2
300_0402_5%
1
R596
+5VALW
W
BATT_CHG_LED#
H5
HOLEA
H8
HOLEA
H9
HOLEA
I:H_3P0 X1
LED3
2
White
1
2
2
300_0402_5%
1
R597
+5VS
H10
HOLEA
C:H_3P8
RB751V_SOD323
19-213A-T1D-CP2Q2HY-3T_WHITE
H11
HOLEA
H12
HOLEA
H13
HOLEA
H14
HOLEA
1
1
H3
HOLEA
H7
HOLEA
18-225A-S2T3D-C01-3T_ORG-WHITE
D19
[28] WLAN_LED#
2
H2
HOLEA
1
White
O
1
Orange
[34] CHARGE_LED1#
H1
HOLEA
1
H30
HOLEA
1
1
R599
1
2
300_0402_5%
1
2
1
1
1
White
[34] PWR_LED#
J:H_2P8 X1
1
1
1
VB
1
[37] BT_LED#
D21
2
White
1
2
2
300_0402_5%
1
R598
H15
HOLEA
H26
HOLEA
+5VS
1
[22] SATA_LED#
H18
HOLEA
1
H17
HOLEA
LED4
1
H16
HOLEA
D:H_3P8
RB751V_SOD323
1
19-213A-T1D-CP2Q2HY-3T_WHITE
BOTTOM SIDE
FAN
BOTTOM SIDE
VGA
H20
HOLEA
H_4P5X3P0N
H22
HOLEA
1
1
H_6P0N
H21
HOLEA
3P2 X1
H23
HOLEA
H_3P0X4P0N
1
1
H29
HOLEA
1
H19
HOLEA
1
1
1
[28] WWAN_LED#
H28
HOLEA
H25
HOLEA
H27
HOLEA
H_1P9X0P5N
EMI on DIMM
H24
HOLEA
1
BOTTOM SIDE
WLAN
1
1
3G
1
[34] FSEL#SPICS#
[34] FRD#SPI_SO
H_1P9x0P5
VB
Compal Secret Data
Security Classification
Issued Date
2007/10/15
Deciphered Date
2008/10/15
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Compal Electronics, Inc.
LED/EC SPI ROM
Document Number
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
36
of
47
B
C
D
E
Right USB Conn.
+USB_VCCA
4
3
2
3
2
ACES_85205-04001
ME@
1
3
0_0402_5%
1
L92
WCM-2012-900T_0805
@
4
USB_OC#1 [21]
USB20_P12_R
0_0402_5%
2
1
4
+USB_VCCB
3
3
2
USB20_N0_R
Left USB Conn.
W=80mils
2
2
R634 1
[21] USB20_P0
JUSB2
1
0_0402_5%
USB20_P0_R
2
C1224
470P_0402_50V7K
C1223
@ 1000P_0402_50V7K
2
ESATA and USB Conn.
+USB_VCCB
2
150U_B2_6.3VM_R35M
1
2
C1227
470P_0402_50V7K
ESATA and USB
USB20_N4
8
7
6
5
1
2
SATA_DTX_SRX_N2_R
SATA_DTX_SRX_P2_R
D27
@
12
13
14
15
1
USB_OC#0 [21]
3
U47
PJDLC05_SOT23-3
E-SATA COMBO
LEFT USB PORT
5
6
7
8
9
10
11
SATA_STX_C_DRX_P2_R
SATA_STX_C_DRX_N2_R
USB20_P4
+USB_VCCB
GND
OUT
IN
OUT
IN
OUT
EN
OC#
APL3510BKI _SO8
JESAT1
1
2
3
4
USB20_N4
USB20_P4
[21] USB20_N4
[21] USB20_P4
2
+5VALW
1
2
3
USB_ON# 4
SUYIN_020173MR004S558ZL
ME@
1
C1225 +
C1226 0.1U_0402_16V4Z
2
1
D26
@
1
2
3
4
GND
GND
GND
GND
W=80mils
+USB_VCCB
USB power switch need update symbol
to SA000039E00(Low enable)
1
2
3
4
5
6
7
8
USB20_N0_R
USB20_P0_R
1
1
2
R632 1
[21] USB20_N0
RIGHT USB PORT X1
8
7
6
5
GND
OUT
IN
OUT
IN
OUT
EN
OC#
APL3510BKI_SO8
2
USB20_N12_R
2
+USB_VCCA
U46
1
2
3
USB_ON# 4
C1222 0.1U_0402_16V4Z
2
1
[34] USB_ON#
2
1
R472 1
[21] USB20_P12
+5VALW
0_0402_5%
D30
@
1
2
3
4
G5
G6
3
1
L91
WCM-2012-900T_0805
@
4
C1221
470P_0402_50V7K
1
[21] USB20_N12
2
1
2
3
4
5
6
USB20_N12_R
USB20_P12_R
PJDLC05_SOT23-3
1
2
R588 1
JUSB1
+USB_VCCA
1
1
C1220 +
150U_B2_6.3VM_R35M
Right USB(Sub b/d)
W=80mils
PJDLC05_SOT23-3
A
C1228
@ 1000P_0402_50V7K
VBUS
DD+
GND
USB
2
USB
A+ = RXP
A- = RXN
GND
A+
ESATA
AGND
BB+
GND
B- = TXN
B+ = TXP
GND
GND
GND
GND
TYCO_1759576-1
ME@
2
+3VS
1
2
EN
C1234 1
C1233 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N2
SATA_DTX_SRX_P2
4
5
3
18
13
17
19
21
1
2
BT@
R684
100K_0402_5%
BT@
C1235
1
0.1U_0402_16V4Z
2
SATA_STX_C_DRX_P2
SATA_STX_C_DRX_N2
SATA_DTX_SRX_P2
SATA_DTX_SRX_N2
IN
+3VS Q81
+3VS_BT
3
1
BT@
2
G
1
OUT
BT@
Q82
DTC124EKAT146_SC59-3
IN
2
2
SATA_STX_C_DRX_P2_R
GND
OUT0P 15
SATA_STX_C_DRX_N2_R
GND
OUT0M 14
GND
SATA_DTX_SRX_P2_R
GND
IN1M 11
SATA_DTX_SRX_N2_R
GND
IN1P 12
PAD
MAX4951ETP+T_TQFN20_4X4~D
@
R685
R687
R688
R689
1
1
1
1
2
2
2
2
1
9
8
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
R682
0_0402_5%
@
R683
0_0402_5%
@
SATA_STX_C_DRX_P2_R
SATA_STX_C_DRX_N2_R
SATA_DTX_SRX_P2_R
SATA_DTX_SRX_N2_R
0.1U_0402_16V4Z
C1236
BT@
[28] BT_ACTIVE
BTON_LED
BT_ACTIVE
1
2
3
4
5
6
1
2
3
4
5 G1 7
6 G2 8
ACES_87213-0600G
ME@
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2006/08/18
Deciphered Date
2007/8/18
Title
USB ports/BT/E-SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
2
1
B0
B1
3
JP16
[21] USB20_P6
[21] USB20_N6
3
GND
4
BT
OUT1P
OUT1M
6
10
16
20
1
AO3413_SOT23-3
[36] BT_LED#
VCC
VCC
VCC
VCC
R681
4.7K_0402_5%
@
30mils
D
S
BT@
Q80
DTC124EKAT146_SC59-3
3
[34] BT_OFF#
2
GND
OUT
1
1 R686
2
100K_0402_5%
BT@
IN0P
IN0M
4.7K_0402_5%
@
2
SATA_STX_C_DRX_P2
SATA_STX_C_DRX_N2
R680
2
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
BT MODULE CONN
C1229
0.01U_0402_16V7K
1 @
1
[22] SATA_DTX_C_SRX_N2
[22] SATA_DTX_C_SRX_P2
C1230 1
C1231 1
+5VALW
2
C1232
0.1U_0402_16V4Z~D
2 @
U48
7
3
[22] SATA_STX_DRX_P2
[22] SATA_STX_DRX_N2
1
1
1
@ R106
4.7K_0402_5%
2
2
+3VS
B
C
D
Rev
0.2
NAWE6 LA-5754P
Monday, March 01, 2010
Sheet
E
37
of
47
A
B
C
+5VALW TO +5VS
+5VALW
0.1U_0603_25V7K
VLDT_EN# 2
Q47G
2N7002_SOT23
2
S
1
D
2
S
2
VB
2
@
1 1
JUMP_43X118
1
2 VLDT_EN#
G
Q53 @
2N7002_SOT23
C864
C860
@
0.1U_0603_25V7K
1
2
10U_0805_10V4Z
C858
@
U37 @
+1.5VS
AO4430L_SO8
8
1
7
2
6
3
5
1
1U_0402_6.3V4Z
2
1.1VS_GATE
+1.5VSG
PJ507
1
C857
1
@
C859
@
10U_0805_10V4Z 2
2
2
10U_0805_10V4Z
R609
@
470_0603_5%
1
3
D
2
47K_0402_5%
VB
470_0603_5%
1
2
+1.5V to +1.5VSG
+1.5V
R622 @
D
3
S
1
R613
B+
1
D
S
1
10U_0805_10V4Z
C874
2
2
1U_0402_6.3V4Z
2
10U_0805_10V4Z
3
SUSP
2
Q65G
2N7002_SOT23
1
100K_0402_5%
3
B+
2 R1191 1 5VS_GATE
0_0402_5%
1
C870
2
1
4
R614
2 SUSP
G
Q50 @
2N7002_SOT23
C872
1
1
VB
D
1
1
2
3
1
R628
C871
1K_0402_5%
1
3
R620 @
470_0603_5%
4
1
1
1
10U_0805_10V4Z
C863
2
2
1U_0402_6.3V4Z
10U_0805_10V4Z
2
2
10U_0805_10V4Z
1
+1.1VS
8
7
6
5
2
C867
2
1
C869
1
1
+1.1VALW
U40
AO4430L_SO8
4
C865
E
+1.1VALW TO +1.1VS (NB HT)
+5VS
U36
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
D
S
SUSP
+3VALW TO +3VS
1.5VSG_GATE
1 @
2
R608
100K_0402_5%
B+
+3VS
2
G
@
Q45
2N7002_SOT23
C873
S
Q46
@
S
C856
@
0.1U_0603_25V7K
2N7002_SOT23
2
Q51
2N7002_SOT23
+1.8VS to +1.8VSG
R618
10K_0402_5%
0.1U_0603_25V7K
2
2
3
2
S
D
2
G
[34,44,45,46] VLDT_EN
1
D
2
G
3
2
VLDT_EN#
2 SUSP
G
Q54 @
2N7002_SOT23
1
VB
D
S
R625
100K_0402_5%
SUSP
2
Q52 G
2N7002_SOT23
SUSP 2
1
R610 47K_0402_5%
@
1
C862
@
0.1U_0603_25V7K
2
2
R626 @
470_0603_5%
1
D
2 R1192 1 3VS_GATE
0_0402_5%
1
1
3
1
R619
200K_0402_5%
1
C875
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
1
2
B+
C868
1 1
2
C866
10U_0805_10V4Z
2
+5VALW
3
1
1
2
1
4
C861
10U_0805_10V4Z
U41
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
1
+3VALW
+1.8VS
1
S
2
100K_0402_5%
C713
SUSP
1
1
D
Q13
S
3
2
G
1
1
D
2
G
Q74
S
2N7002_SOT23
DIS@
2
C877
DIS@
0.1U_0603_25V7K
3
SUSP
2
G
Q14 @
2N7002_SOT23
S
SSM3K7002FU_SC70-3
3
R639
2
1
47K_0402_5%
1
2
C712
DIS@
2
0.1U_0603_25V7K
D
SUSP#
1 DIS@
VB
R489
84.5K_0402_1%
1
1
10U_0805_6.3V6M
2
R313 @
470_0603_5%
1
1
3
1
G
R314
2
VLDT_EN#1 R500@ 2
200K_0402_5%
2
3
S
R623
100K_0402_5%
2
2
G
@
Q73
2N7002_SOT23
1.8VSG_GATE
1 DIS@ 2
R633 200K_0402_5%
B+
+1.5VS
2
1
3
3
S
R615
10K_0402_5%
Q59
SI2301CDS-T1-GE3_SOT23-3
+1.5V
Q30
2N7002_SOT23
D
1
D
2
G
[28,34,43] SYSON
D
SUSP
S
Q57
2N7002_SOT23
2
R638
1
1
@
C880
470_0603_5%
DIS@
C878
10U_0805_10V4Z
2
2 DIS@
1
1
DIS@
DIS@
2
2
10U_0805_10V4Z 10U_0805_10V4Z
+1.5VS
1
D
2
G
SUSP#
3
C879
SYSON#
1
1
[43] SYSON#
[28,34,41,44,46]
1
1U_0402_6.3V4Z
3
R621
100K_0402_5%
1
2
SUSP
C881
R627 @
100K_0402_5%
R110
100K_0402_5%
[43] SUSP
+5VALW
4
VB
2
+5VALW
2
1
RTCVREF
+1.8VSG
U45 DIS@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
+VGA_CORE
C714
+1.8VS
+3VSG
+CPU_VDDR
+NB_CORE
+2.5VS
SUSP#
2
1
2 SUSP
G
R404 @ 0_0402_5%
2N7002_SOT23
Q55 @
S
1 R503@ 2
200K_0402_5%
1
2
10K_0402_5% R607 1
DIS@
C876
DIS@
2
0.1U_0603_25V7K
D
2 VLDT_EN#
G
Q71 @
2N7002_SOT23
S
2 SUSP
G
Q61 @
2N7002_SOT23
B
2
G
2
D
R269 @
470_0603_5%
1
C236
D
S
DIS@
Q15
SUSP
2
G
Q29 @
2N7002_SOT23
4
S
SSM3K7002FU_SC70-3
Compal Electronics, Inc.
Compal Secret Data
2008/10/06
Issued Date
2010/03/12
Deciphered Date
Title
DC Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
2
1
2
R611 10K_0402_5%
DIS@
1
1
D
2 VLDT_EN#
G
Q56 @
2N7002_SOT23
Security Classification
1
D
S
2
2
1
1
1
1
R405 @ 0_0402_5%
2 SYSON#
R617 @
470_0603_5%
3
S
1
R636 @
470_0603_5%
3
3
S
2 SYSON#
G
Q66 @
2N7002_SOT23
3
D
R605 @
470_0603_5%
3
1
D
1
1
R624 @
470_0603_5%
1
R629 @
470_0603_5%
2
2
2
4
DIS@
10U_0805_6.3V6M
2
3
VB
+0.75VS
R270
DIS@
100K_0402_5%
1
0.1U_0603_25V7K
2
3VSG_GATE
1
3
S
SUSP
2
G
Q60 @
2N7002_SOT23
3
D
SUSP
2
G
Q70 @
2N7002_SOT23
+3VSG
1
2
1
C855 1
DIS@
1
1
1
S
3
1
D
SUSP
3
3VSG_GATE
3
+3VS
VLDT_EN#
+1.5V
Q58
SI2301CDS-T1-GE3_SOT23-3
D
S
@ 0_0402_5%
R402
1
2 VLDT_EN
R403 2
2
1
G
0_0402_5%
Q67 @
2N7002_SOT23
R616 @
470_0603_5%
G
D
R635 @
470_0603_5%
S
1
R631
470_0603_5%
@
2
2
2
0.22U_0603_16V4Z2
1
+VGA_PCIE
C
D
Rev
0.2
NAWE6 LA-5754P
Tuesday, March 02, 2010
Sheet
E
38
of
47
B
C
D
ACIN
1
PR101
1K_1206_5%
1
2
PR102
1K_1206_5%
1
2
PD101
2
VIN
1
LL4148_LL34-2
1
1
PQ102
DDTC115EUA-7-F_SOT323-3
1 2
VIN
VS
2
[34,41] ACOFF
PQ103
DDTC115EUA-7-F_SOT323-3
VIN
3
3
2
51ON-1
1
2
2
1
PR116
499K_0402_1%
1
3
1
IN
GND
PC116
10U_0603_6.3V6M
PR129
560_0603_5%
1
2
@ MAXEL_ML1220T10
+RTCBATT
1
2
+CHGRTC
RB751V-40_SOD323-2
4
RTC Battery
2CHGRTCIN
1
OUT
+
1
PR128
200_0603_5%
1
PC117
1U_0805_25V6K
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
2009/01/06
Deciphered Date
2010/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
2
1
PR118
205K_0402_1%
2
JRTC
PD106
2
3
+5VALW
2
2
3.3V
2
2
VS
-
PU102
G920AT24U_SOT89-3
1
PR130
560_0603_5%
1
2
PACIN [41]
PQ106
DDTC115EUA-7-F_SOT323-3
PC115
0.1U_0603_25V7K
51ON-3
RTCVREF
+CHGRTC
PQ105
PR125
2N7002KW _SOT323-3
47K_0402_5%
2
2
1
G
3
1
1
3
2
4
D
2
1
PC114
0.22U_0603_25V7K
2
1
2
PR127
22K_0402_1%
1
2
PR124
10K_0402_5%
2
1
RTCVREF
S
51ON-2
PR126
100K_0402_1%
[32] 51_ON#
PR122
68_1206_5%
2
PR121
68_1206_5%
PQ104
TP0610K-T1-E3_SOT23-3
PR123
200_0603_5%
CHGRTCP 1
2
3
1
1
PD105
LL4148_LL34-2
2
1
1
BATT+
1
PD104
LL4148_LL34-2
PC113
0.1U_0603_25V7K
3
PRG++ 2
6
1
5
-
1
2
BAS40CW _SOT323-3
+
O
PU101B
LM393DG_SO8
PC111
1000P_0402_50V7K
3
P
7
1
[41] ACON
G
2
4
PD103
[6,40,42] MAINPWON
VIN
8
2
1
PR117
100K_0402_1%
3.3V
RTCVREF
PR113
2.2M_0402_5%
2
1
VL
2
2
PD102
LLZ4V3B_LL34-2
PR115
10K_0402_5%
2
1
PACIN [41]
PC112
0.01U_0402_25V7K
1
PR109
10K_0805_5%
PACIN
1
O
PU101A
LM393DG_SO8
2
B+
2
ACIN [14,34]
1
PR114
10K_0402_5%
-
1
2
PR110
10K_0402_1%
1
2
2
1
P
8
+
4
1
2
PC109
0.1U_0402_16V7K
1
PR112
20K_0402_1%
VINDE-3
3
G
2
PR111
22K_0402_1%
1
2
VINDE-1
2
2
PR108
84.5K_0402_1%
PC108
0.068U_0603_16V7K
2
1
PC107
0.01U_0402_25V7K
1
2
2
1
PR119
499K_0402_1%
VINDE-2
PR104
100K_0402_1%
2
1
Max.
18.384V
17.728V
PR107
1M_0402_1%
1
2
3
PR103
1K_1206_5%
1
2
1
Vin Detector
Min.
typ.
L-->H 17.430V 17.901V
H-->L 16.976V 17.262V
PQ101
TP0610K-T1-E3_SOT23-3
2
1
2
PC106
1000P_0402_50V7K
1
2
PC105
100P_0402_50V8J
1
2
PC104
@ 0.1U_0603_25V7K
1
2
2
@ 4602-Q04C-09R 4P P2.5
JDCIN
PC103
100P_0402_50V8J
1
1
2
1
PL101
SMB3025500YA_2P
1
2
2
3
2
PF101
7A_24VDC_429007.W RML
1
2 APDIN1
PC102
1000P_0402_50V7K
3
APDIN
1
4
PC101
@ 0.1U_0603_25V7K
1
4
PR105
100K_0402_1%
2
1
DC030006J00
BATT ONLY
Precharge detector
Min.
typ.
Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V
Precharge detector
Min.
typ.
Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V
VIN
PR106
100K_0402_1%
A
B
C
DCIN & DETECTOR
Rev
0.1
Monday, March 01, 2010
D
Sheet
39
of
47
A
B
C
D
1
1
VMB2
VMB
PF201
12A_65V_451012MRL
1
2
JBATT
1
2
3
4
5
6
7
8
9
PL201
SMB3025500YA_2P
1
2
BATT+
TYCO_1775789-1
@
1
2
PC201
1000P_0402_50V7K
2
2
1
PR206
100_0402_1%
1
EC_SMCA
EC_SMDA
2
1
PR204
100_0402_1%
1
2
3
4
5
6
7
GND
GND
PC202
0.01U_0402_25V7K
PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C
2
2
VL
EC_SMB_CK1 [34]
VL
A/D
3
OT1 TMSNS2
6
OT2 RHYST2
5
2
1
1
1
1
PH203
@ 100K_0402_1%_TSM0B104F4251RZ
BATT_OUT# [41]
PQ316
D 2N7002KW _SOT323-3
S
2
3
O
-
MAINPW ON [6,39,42]
1
1
2
1
+
PH202
100K_0402_1%_TSM0B104F4251RZ
2
1
2
PR216
@ 47K_0402_1%
PR213
9.76K_0402_1%
PR88
10K_0402_1%
8
PR83
5.1M_0402_5%
1
2
G
1
PU902A
LM393DG_SO8
1
4
2
7
2
2
PR84
100K_0402_1%
3
1
2
PR89
442K_0402_1%
3
8
GND RHYST1
4
+3VALW
P
PR86
100K_0402_1%
1
2
3
VCC TMSNS1
2
G718TM1U_SOT23-8
G
2
2
PR87
649K_0402_1%
+3VALW
PC62
0.01U_0402_25V7K
1
VS
VMB2
1
2
BATT_TEMP [34]
PR215
@ 100K_0402_1%
1
PU202
1
2
PR211
10K_0402_5%
PR214
21.5K_0402_1%
2
PR212
10K_0402_1%
1
PC208
0.1U_0603_25V7K
+3VALW
2
1
2
PR209
6.49K_0402_1%
2
1
EC_SMB_DA1 [34]
2
1
RTCVREF
5
+
6
-
P
8
PR85
10K_0402_1%
4
G
O
7
PU902B
LM393DG_SO8
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/01/06
Deciphered Date
2010/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
BATTERY CONN / OTP
Document Number
Rev
0.1
Monday, March 01, 2010
Sheet
D
40
of
47
5
4
3
2
1
B+
P3
P2
3
2
1 1
CSIP
19
7
ICM
PHASE
18
CSOP
4
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
GND
PGND
13
DL_CHG
PC317
0.1U_0603_25V7K
BST_CHGA 2
1
4
PD303
RB751V-40_SOD323-2
6251_VDDP
2
12
PR320
0_0402_5%
BST_CHG 1
2
26251_VDD
1
PR323
4.7_0402_5%
PC323
4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
4
2
3
2
UMA CP mode
Vaclim=2.39*((152K//1.74K)/((152K//1.74K)+(152K//16.9K)))=0.243V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.243V, Iinput=2.75A
PQ314 TP0610K-T1-E3_SOT23-3
3
1
1.882V
4.35V
3.2935V
1
3
@
2
5
2
1
PR331
0_0402_5%
[34] BATT_SEL_EC
PQ313A
2N7002KDW -2N_SOT363-6
@
PQ313B
2N7002KDW -2N_SOT363-6
@
IREF=1.016*Icharge
PR337
2
IREF=0.254V~3.048V
1
100K_0402_1%
1
A
6251_DCIN
4.2V
PR330
0_0402_5%
CC=0.25A~3A
2
PR335
100K_0402_1%
2
1
P3
PR333
10_0603_5%
1
2
0V
@
4
4V
DIS CP mode
Vaclim=2.39*((152K//27.4K)/((152K//27.4K)+(152K//16.9K)))=1.44V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=1.44V, Iinput=4A
PR328
100K_0402_1%
@
6
CELLS
PR327
100K_0402_1%
1
CHGVADJ
6251_VDD
2
6251_VDD
1
Vcell
BATT+
2
CHGVADJ=(Vcell-4)/0.10627
C
B
1
2
PR326
31.6K_0402_1%
CHG
1
1
[34] CHGVADJ
PR325
15.4K_0402_1%
1
2
PQ309
2N7002KW _SOT323-3
PC318
10U_1206_25V6M
2
1
16
1
BOOT
2
CHLIM
@
B
2
PR319
@ 4.7_1206_5%
9
DH_CHG
1
17
2
UGATE
PR324
27.4K_0402_1%
Connect to EC A/D Pin.
1
PC322
@ 680P_0603_50V7K
VREF
PACIN
2
G
S
PL301
PR317
10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
5
8
D
PC319
10U_1206_25V6M
2
1
VCOMP
VIN
1
6
PR308
200K_0402_1%
2
2
3
20
1
PC311
0.1U_0603_25V7K
2
1
CSIN
S
PQ306
DDTC115EUA-7-F_SOT323-3
3
ICOMP
1
5
D
3
21
PQ308
SIS412DN-T1-GE3_POWERPAK8-5
CSOP
5
CELLS
CSON
PC310
0.047U_0402_16V7K
1
2
PR311
20_0402_5%
2
1
PR312
20_0402_5%
PC313
0.1U_0402_16V7K
1
2
PR315
2.2_0402_5%
LX_CHG
3
2
1
22
1
CSON
2
EN
PR310
20_0402_5%
1
2
PQ312
SI7716ADN-T1-GE3 _PAK1212-8
1
1
PR322
100K_0402_1%
2
S
2
G
[40] BATT_OUT#
S
2N7002KW_SOT323-3
1
D
3
PQ20
3
PR950
100K_0402_1%
2
G
[34] IREF
1
2
PR316
100_0402_1%
6251_VREF
1
2
PC316
0.1U_0402_16V7K
PR321
16.9K_0402_1%
6251_VREF 1
2
PC321
0.01U_0402_25V7K
2
1
2ACOFF-1
1
2N7002KW_SOT323-3
1
[34,39] ACOFF
D
1
6.81K_0402_1%
2
[34] ADP_I
PR318
154K_0402_1%
2
1
23
4
6800P_0402_25V7K
2
1
2
PC315
@ 100P_0402_50V8J
[39] ACON
PQ311
VIN
ACOFF-12
G
3
2
1
0.01U_0402_25V7K
ACSET ACPRN
1
PR314
1
2
2
PC314
1
2
2
G
24
1
S
PC312
1
DCIN
2
1
3
PACIN
[39] PACIN
PQ310
D 2N7002KW _SOT323-3
VDD
3
CELLS
C
PR313
3K_0402_1%
1
2
6251_EN
1
PC309
0.1U_0603_25V7K
6251_DCIN 2
1
2
2
3
PR307
2
1
2
PC308
0.1U_0402_16V7K
PR309
150K_0402_1%
1
1
PU301
1
3
[34] FSTCHG
100K_0402_1%
DDTC115EUA-7-F_SOT323-3
PR306
10K_0402_1%
2
1
PR305
10K_0402_1%
PQ21
2N7002KW _SOT323-3
PC307
2.2U_0603_6.3V6K
2
1
1
4
1
1
PQ305
S
D
PR304
47K_0402_1%
1
2
PD301
RB751V-40_SOD323-2
2
6251_VDD
5
PQ913A
2N7002KDW -2N_SOT363-6
2
2
G
8
7
6
5
BATT_OUT# [40]
2
PQ307
D 2N7002KW _SOT323-3
CSIN
CSIP
PQ913B
2N7002KDW -2N_SOT363-6
1
2
3
PC320
10U_1206_25V6M
2
1
1
@
@ JUMP_43X118
4
2
PR951
47K_0402_1%
PQ303
FDS6675BZ_SO8
1
1
PC305
2200P_0402_50V7K
1
2
3
2
PC304
10U_1206_25V6M
2
1
2
2
PC303
10U_1206_25V6M
2
1
4
2
4
1
2
1
1
47K
CHG_B+
PJ301
VIN
6
1
3
2
2
PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%
1
PR301
47K_0402_5%
PDTA144EU_SOT323-3
47K
PR302
0.02_1206_1%
8
7
6
5
1
1
2
3
PQ304
2
D
1
2
3
4
8
7
6
5
PC306
0.1U_0603_25V7K
VIN
PQ302
FDS6675BZ_SO8
PC302
470P_0603_50V8J
PQ301
FDS6675BZ_SO8
VCHLIM need over 95mV
PQ315
DDTC115EUA-7-F_SOT323-3
A
PD304
2
2
FSTCHG
3
SUSP#
1
3
BAS40CW _SOT323-3
FSTCHG [34]
SUSP# [28,34,38,44,46]
2007/6/22
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/6/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
CHARGER
Document Number
Rev
0.1
Monday, March 01, 2010
Sheet
1
41
of
47
5
4
3
ISL6237_B+
30
VOUT2
DRVL1
LG5
PGND
22
VOUT1
10
FB1
11
2
1
VREF2
8
LDOREFIN
VSW
PD401
5V_SKIP
SKIPSEL
NC
PGOOD2
28
EN_LDO
PGOOD1
13
TRIP1
12
ILM1
TRIP2
31
ILIM2
4
3/5V_EN1
14
EN1
3/5V_EN2
27
EN2
1 PR411 2
0_0402_5%
2 PR421 1
@ 0_0402_5%
VL
VL
2VREF_ISL6237
GND
TONSE
VREF3
21
2
5
PR415
301K_0402_1%
B
13/5V_TON
PR416
0_0402_5%
RT8206B_QFN32_5X5
2
1
PR414
301K_0402_1%
2
1
PR420
0_0402_5%
PJ402
2
+3VALWP
2
2
1
1
+3VALW
@ JUMP_43X118
2VREF_ISL6237
1
2
2
PC418
1U_0603_10V6K
2
1 3/5V_NC
1
0_0402_5%
MAINPW ON [6,39,40]
1
PR419
@ 47K_0402_1%
2VREF_ISL6237
1
PC420
0.047U_0402_16V7K
2
1
1
PR418
2
PC419
0.047U_0402_16V7K
2
PR417
RB751V-40_SOD323-2
806K_0603_1%
VL
PD403
2
C
SPOK [43]
PC417
0.22U_0603_25V7K
B
1
PR410
2
1
@ 0_0402_5%
2
EN_LDO
2
LLZ5V1B_LL34-2
2
EN_LDO-1
1
2
PR413
200K_0402_1%
1
2
1
PC413
150U_B2_6.3VM_R45M
2
9
RB751V-40_SOD323-2
20
PC406
2200P_0402_50V7K
2
1
FB5
29
2
PR412
100K_0402_1%
1
2
PC422
4.7U_0805_25V6-K
2
1
REFIN2
PC416
0.22U_0603_25V7K
PD402
PC415
330P_0603_50V8
PQ404
SI7716ADN-T1-GE3_PAK1212-8
1
1
PC412
0.1U_0603_25V7K
PR422
32
16
18
+
PR407
@ 61.9K_0402_1%
1
2
DRVL2
LL1
LL2
1
PR409
0_0402_5%
1
2
23
2
25
LG3
SW 5
4
3
2
1
SW 3
VL
@
1
2
PC411
0.1U_0603_25V7K
+5VALWP
PR404
4.7_1206_5%
1BST5A-1
PR405
2.2_0603_5%
15V_SNB
2
BST5A2
2VREF_ISL6237
VS
PC404
4.7U_0805_25V6-K
2
1
5
3
2
1
HG5
17
5
PC409
2
1
7
LDO
V5FILT
15
VBST1
1
1
VIN
DRVH1
VBST2
FB3
1
4.7U_0805_6.3V6K
PC408
3/5V_VCC
1
2
3
1U_0603_10V6K
3/5V_VIN
2
1
DRVH2
24
5
26
PQ402
SIS412DN-T1-GE3_PAK1212-8
PL402
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
100K_0402_1%
2
UG3
BST3A
PQ403
SI7716ADN-T1-GE3_PAK1212-8
PR408
10K_0402_1%
1
C
1
PR403
2.2_0603_5%
2
PC414
330P_0603_50V8
2
2
4
2
19
PC410
1U_0603_10V6K
1
2
TP
V5DRV
D
4
33
1
2
3
1
+
BST3A-1
13V_SNB
2
2
1
PU401
PR402
4.7_1206_5%
PR406
0_0402_5%
1
6
5
PL401
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
+3VALWP
PC407
0.1U_0603_25V7K
PQ401
4 SIS412DN-T1-GE3_PAK1212-8
VL
1
2
3
PC423
4.7U_0805_25V6-K
2
1
PC403
2200P_0402_50V7K
2
1
PR401
0_0402_5%
1
2
PC401
4.7U_0805_25V6-K
2
1
PC405
330P_0402_50V7K
2
1
PJ401
@ JUMP_43X118
2 2
1 1
PC421
150U_B2_6.3VM_R45M
1
ISL6237_B+
B+
D
2
@
PJ403
+5VALWP
2
2
1
1
+5VALW
@ JUMP_43X118
A
A
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/01/06
Deciphered Date
Title
3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Monday, March 01, 2010
Date:
5
4
3
2
Rev
0.1
Sheet
1
42
of
47
5
4
3
2
1
PJ501
1.1V_IN
2
1
PC504
2200P_0402_50V7K
1
2
PC503
4.7U_0805_25V6-K
1
2
B+
D
1
PC510
4.7U_0805_6.3V6K
+
2
1
TP
PU501
TPS51117RGYR_QFN14_3.5x3.5
1
PC507
10U_0805_6.3V6M
LG_1.1V
PQ502
SI4634DY-T1-E3_SO8
4
2
9
DRVL
PGND
8
7
2
PC509
@ 47P_0402_50V8J
1
2
GND
PC508
4.7U_0603_6.3V6K
1
10
PR504
4.7_1206_5%
+5VALW
PC506
220U_B2_2.5VM_R15M
PGOOD
V5DRV
1.1V_TRIP
1
2
PR506
11.5K_0402_1%
2
6
SW _1.1V
1
VFB
+1.1VALW P
PC511
680P_0603_50V7K
2
5
12
11
5
6
7
8
1.1V_FB
LL
TRIP
3
2
1
V5FILT
UG_1.1V
1
VOUT
4
13
1.1V_SNB
3
1.1V_V5FILT
DRVH
2
TON
PL501
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
14
15
1
2
EN_PSV
2
1
1
0.1U_0603_25V7K
PC501
@0.01U_0402_25V7K
PR505
100_0603_1%
1
2
+5VALW
2
@ JUMP_43X118
3
2
1
1.1V_EN
1
[42] SPOK
4
PR503
PC505
0_0402_5%
BST_1.1V 1
2BST_1.1V-1
1
2
VBST
D
PC502
4.7U_0805_25V6-K
PR502
240K_0402_1%
1
2
1.1V_TON
PR501
0_0402_5%
1
2
5
6
7
8
PQ501
SI4172DY-T1-GE3_SO8
2
1
PR508
9.76K_0402_1%
1
2
PR509
20.5K_0402_1%
PJ502
1.5V_IN
2
@
PC514
4.7U_0805_25V6-K
1
2
PC513
4.7U_0805_25V6-K
2
1
PC515
2200P_0402_50V7K
+1.5VP
4
PU502
TPS51117RGYR_QFN14_3.5x3.5
PC523
4.7U_0805_6.3V6K
+
2
PC524
@ 680P_0603_50V7K
B
1
PR517
22.1K_0402_1%
1
2
1
1
LG_1.5V
PR513
@ 4.7_1206_5%
PQ504
2
9
+5VALW
PC518
220U_B2_2.5VM_R15M
V5DRV
10
1.5V_TRIP
1
2
PR515
11.5K_0402_1%
1.5V_SNB 2
SW _1.5V
11
1
12
2
LL
TRIP
DRVL
C
B+
1
14
VBST
PGND
7
8
2
2
GND
PGOOD
PC521
@ 47P_0402_50V8J
1
2
B
TP
VFB
UG_1.5V
TPCA8028-H_SOP-ADVANCE8-5
5
13
5
1.5V_FB
DRVH
1
V5FILT
PL502
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
2
VOUT
4
1
3
1.5V_V5FILT
6
PC520
4.7U_0603_6.3V6K
15
1
TON
EN_PSV
2
2BST_1.5V-1
1
2
PC516
0.1U_0603_25V7K
1
1
PC519
10U_0805_6.3V6M
BST_1.5V 1
PR512
0_0402_5%
PC517
0.1U_0402_16V7K
PR514
100_0603_1%
1
2
+5VALW
4
2
JUMP_43X79
3
2
1
1.5V_EN
1
[28,34,38] SYSON
2
PR510
240K_0402_1%
1
2
1.5V_TON
PR511
0_0402_5%
1
2
3
2
1
PR522
@ 0_0402_5%
1
2
[34] VDDIO
1
PQ503
SI4172DY-T1-GE3_SO8
5
6
7
8
2
C
2
PR518
22.1K_0402_1%
+1.5V
PJ503
2
+1.1VALWP
1
1
2
2
1
VIN
VCNTL
6
GND
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
0.75V_REF
1
1
+1.5V
PC526
1U_0402_6.3V6K
PJ506
2
+0.75VSP
2
1
1
+0.75VS
@ JUMP_43X79
G2992F1U_SO8
+0.75VSP
S PQ505
SSM3K7002FU_SC70-3
2
2
PC530
10U_0805_6.3V6M
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1
2
PC527
0.1U_0402_16V7K
1
1
PR521
1K_0402_1%
PC529
10U_0805_6.3V6M
2010/01/06
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
2
@ JUMP_43X118
1
D
2
PC528
@ 0.1U_0402_16V7K
3
1
[38] SYSON#
1
PR520
0_0402_5%
1
20.75V_EN 2
G
2
+1.5VP
+3VALW
2
2
2
[38] SUSP
+1.1VALW
1
1
PR519
1K_0402_1%
2
PR523
0_0402_5% @
1
2
1
PJ505
PU503
0.75V_IN
2
A
1
PJ504
@ JUMP_43X79
1
PC525
4.7U_0805_6.3V6K
2
@ JUMP_43X118
4
3
2
1.1V/1.5V/0.75V
Document Number
Rev
0.1
Monday, March 01, 2010
Sheet
1
43
of
47
A
5
4
3
2
1
PJ607
2
B+
2
1
VGA_IN
1
UG_VGA
2
1
PC626
2200P_0402_50V7K
BST_VGA 1
PR619
0_0402_5%
BST_VGA-1
1
2
PC633
0.1U_0603_25V7K
2
D
1
+5VALW
PR50
0_0603_5%
5
1
2
D
PC619
10U_1206_25V6M
2
1
PC630
10U_1206_25V6M
@ JUMP_43X79
2
2
TPCA8030-H_SOP-ADV8-5
2
1
VFB=0.6V
VGA_FB-1
1
PR185
4.99K_0402_1%
1
2
2
2
1
2
1
1
2
B
VGA_PWRSEL0
VGA_PWRSEL1
GPU_VID0
GPU_VID1
Core Voltage Level
1
0
0.9V
0
1
0.95V
0
0
1.12 V
Park XT
3
2
PR75
10K_0402_5%
PQ912B
2N7002KDW -2N_SOT363-6
PC132
0.022U_0402_16V7K
5
4
2
1GVID0-1
PR182
10K_0402_1%
1
1
2
1
3
10K_0402_1%
PR635
2
2
5
4
1
PR178
10K_0402_5%
2
1
PR177
10K_0402_1%
+VGA_CORE
GVID0-2
@
[14] GPU_VID0
1
1
PJ608
PR70
13.7K_0402_1%
+3VALW
@
PQ911B
2N7002KDW -2N_SOT363-6
2
@ JUMP_43X118
2
PR186
10K_0402_5%
1
PJ606
2
+VGA_COREP
PR184
23.2K_0402_1%
@ JUMP_43X118
PC133
0.022U_0402_16V7K
2
2
1 2
PR181
10K_0402_1%
PC629
10U_0805_6.3V6M
3
2
1
10
@
1
[14] GPU_VID1
1
B
C
1
2
PR76
42.2K_0402_1%
7
VGA_FB
2
1
PC56
FSET_VGA9
0.01U_0402_25V7K
1VGA_COMP-1
2
1
PR71
22.1K_0402_1%
+
2
2
@
TPCA8028-H_SOP-ADVANCE8-5
1
2
4
PC623
10U_0805_6.3V6M
1 VGA_SNB
2
2
PR618
2.87K_0402_1%
2
ISEN_VGA
1
PC631
10U_0805_6.3V6M
11
PQ604
+VGA_COREP
PC627
330U_D2_2.5VY_R15M
2
1
ISEN
1
5
PGND
12
PR616
4.7_1206_5%
PL603
0.88UH_PCMC104T-R88MN_20A_20%
1
2
PC632
680P_0603_50V7K
BOOT
13
PC53
2.2U_0603_6.3V6K
LG_VGA
3
2
1
16
FSET
FB
NC
6
GVID1-2
PC57
6800P_0402_25V7K
PC135
22P_0402_50V8J
1
2
6
PR183
17.4K_0402_1%
2
@
1
1
6
15
EN
PQ912A
2N7002KDW -2N_SOT363-6
1
1
2
10K_0402_1%
PR634
1
1GVID1-1 2
+VGA_PVCC
1
VO
5
+3VALW
2
14
APW 7138NITRL_SSOP16
VGA_COMP @
PR169
10K_0402_1%
UG
LG
PC51
2.2U_0603_6.3V6K
C
PR170
10K_0402_5%
1
VCC
1
PC628
1U_0402_6.3V6K
PQ911A
2N7002KDW -2N_SOT363-6
PVCC
SW _VGA
VGA_EN_2
1
2
PR614
2.2K_0402_5%
SUSP#
4
2
[28,34,38,41,46]
4
VIN
1
VLDT_EN
2
[34,38,45,46]
VGA_VCC
PR623
@ 0_0402_5%
2
1
PHASE
3
PGOOD
GND
PU4
2
8
PQ603
PR47
4.7_0603_5%
1
2 VGA_VCC
2
@
@
A
A
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/01/06
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
1.5V/VGA_CORE
Document Number
Rev
0.1
Monday, March 01, 2010
Sheet
1
44
of
47
5
4
3
2
1
PJ701
C
2
1
PC705
2200P_0402_50V7K
1
PC703
4.7U_0805_25V6-K
2
1
3
2
1
LG_NB_CORE
PU701
TPS51117RGYR_QFN14_3.5x3.5
1
+
2
2
SI4634DY-T1-E3_SO8
4
1
PC712
4.7U_0805_6.3V6K
PC713
@ 470P_0402_50V7K
C
1
2
PJ702
S PQ703
2N7002KW _SOT323-3
HIGH
0.95V
LOW
1.25V
2
1
1
+NB_CORE
@ JUMP_43X118
PJ703
2
2
1
1
@ JUMP_43X118
+1.5V
PC715
0.1U_0402_16V7K
PJ705
2
+CPU_VDDRP
PJ704
@ JUMP_43X79
1
1
+CPU_VDDR
1
2
PC723
10U_0603_6.3V6M
1
2
1
2
1
2
VDDR_SW
HIGH
PC721
@0.1U_0402_16V7K
1.05V
LOW
0.9V
A
2
A
S PQ705
2N7002KW _SOT323-3
1
2
PR720
10K_0402_5%
D
2
G
1
[22] VDDR_SW
1
PR719
10K_0402_5%
3
1
2
PR717
249K_0402_1%
2
PR718
165K_0402_1%
PC722
10U_0603_6.3V6M
1
1
2
+5VALW
PC711
10U_0603_6.3V6M
+CPU_VDDRP
PR716
31.6K_0402_1%
PC719
0.01U_0402_25V7K
VIN
9
1
2
1
3
FB
B
2
1
PR715 @
47K_0402_5%
VOUT
PC718
4.7U_0805_6.3V6K
2
PC717
0.1U_0402_16V7K
EN
4
2
8
5
1
10K_0402_1%
1
2
1
VLDT_EN
VIN
VOUT
2
POK
VCNTL
7
PR714
GND
PU702
APL5912-KAC-TRL_SO8
B
6
2
2
PC716
1U_0402_6.3V6K
2
@ JUMP_43X79
2
1
1
+5VALW
1
1
PR712
2
1PW RSEL-1
2
10K_0402_1% G
2
+NB_COREP
POWER_SEL
2
1
D
3
PR710
PR711
95.3K_0402_1% 95.3K_0402_1%
2
1
S
10K_0402_1%
PR709
2
1
3
2
G
0.01U_0402_25V7K
PC714
2
1
2
1
0_0402_5%
D
2N7002KW_SOT323-3
PQ704
PR713
PQ702
PR708
31.6K_0402_1%
1
2
+5VALW
[11] POWER_SEL
PR704
@ 4.7_1206_5%
+5VALW
PC708
10U_0805_6.3V6M
V5DRV
10
9
D
+NB_COREP
PC707
220U_B2_2.5VM_R15M
NB_CORE_SW
NB_CORE_TRIP
1
2
PR706
9.1K_0402_1%
DRVL
B+
1
12
11
NB_CORE_SNB
2
LL
TRIP
1
PGND
8
7
2
PGOOD
PC710
@ 47P_0402_50V8J
1
2
GND
6
PC709
4.7U_0603_6.3V6K
1
1
1
VFB
UG_NB_CORE
13
1
NB_CORE_FB 5
V5FILT
2
@ JUMP_43X118
2
VOUT
DRVH
5
6
7
8
3
NB_CORE_V5FILT4
2
PL701
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
3
2
1
TON
2BST_NB_CORE-1
1
2
PC706
0.1U_0603_25V7K
2
2
VBST
15
1
PC701
0.1U_0402_16V7K
PR705
100_0603_1%
1
2
+5VALW
BST_NB_CORE
1
PR703
0_0402_5%
TP
2
PD804
RB751V-40_SOD323-2
1
2
4
14
NB_CORE_EN
EN_PSV
VLDT_EN
1
[34,38,44,46]
PR701
0_0402_5%
VLDT_EN 1
2
2
PR702
240K_0402_1%
1
2
NB_CORE_TON
5
6
7
8
PQ701
SI4172DY-T1-GE3_SO8
PC702
4.7U_0805_25V6-K
NB_CORE_IN
D
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/01/06
Issued Date
Deciphered Date
2010/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
+NB_CORE
Rev
0.1
Sheet
Monday, March 01, 2010
1
45
of
47
5
4
3
2
1
D
D
PU803
APL5508-25DC-TRL_SOT89-3
3
2
2
1
+2.5VSP
PC811
4.7U_0805_6.3V6K
1
1
OUT
GND
PC812
1U_0402_6.3V6K
@ PR809
150_1206_5%
2
IN
1
2
+3VS
+1.5V
PJ806
JUMP_43X79
@
C
2
PD802
PC816
1U_0402_6.3V6K
2
1
+5VALW
C
2
1
1
+5VALW
1
1
@ RB751V-40_SOD323-2
1
2
2
1
1
2
PC817
2
FB
PR812
1.15K_0402_1%
9
VIN
APL5912-KAC-TRL_SO8
PC813
0.01U_0402_25V7K
22U_0805_6.3V6M
PR810
@ 47K_0402_5%
1
2
PD803
RB751V-40_SOD323-2
1
2
PC814
@
1U_0603_10V6K
2
EN
1
SUSP#
+VGA_PCIEP
3
2
2
[28,34,38,41,44]
4
VOUT
VOUT
8
1
SUSP#
PC815
4.7U_0805_6.3V6K
5
VIN
1
POK
VCNTL
2
7
PR813
15K_0402_5%
1
2
GND
VLDT_EN
PU804
1
[34,38,44,45]
PR814
@ 0_0402_5%
1
2
6
PR817
@ 0_0402_5%
VLDT_EN
PJ805
2
+2.5VSP
2
1
1
+2.5VS
@ JUMP_43X79
VGA_PCIE
1.1 V
1.0V
PR811
4.53K_0402_1%
2
PJ807
PR811
4.53K
3K
2
+VGA_PCIEP
2
1
1
+VGA_PCIE
@ JUMP_43X118
PJ801
2
+1.8VSP
2
1
1
+1.8VS
@ JUMP_43X118
PD805
RB751V-40_SOD323-2
1
2
@
@
FB=0.6V
PR818
14.7K_0402_1%
2
TP
1
NC
7
6
1
1
FB_1.8V
PC825
22U_0805_6.3VAM
1
PR92
1M_0402_1%
PC823
0.1U_0402_10V7K
EN_1.8V
1
2
0_0402_5%
2
1
PR821
2
[28,34,38,41,44] SUSP#
FB
EN
11
5
3
SVIN
2
LX
+1.8VSP
PC824
22U_0805_6.3VAM
PVIN
1 2
8
LX_1.8V
2
1
PC820
22U_0805_6.3VAM
2
@
2
1
9
JUMP_43X79
LX
B
PL801
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
4
2
PG
2
NC
1
1
1
PR822
4.7_1206_5%
PU802
SY8033BDBC_DFN10_3X3
10
PVIN
PJ802
+5VALW
PC822
680P_0603_50V7K
B
1.8VSP
TDC 2 A
Peak Current 3 A
PR819
2
1
30K_0402_1%
2
1
2
PC64
@
22P_0402_50V8J
A
A
Compal Secret Data
Security Classification
Issued Date
2009/01/06
Deciphered Date
2010/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
2.5VS/PCIE/1.8VS
Size
Date:
5
4
3
2
Compal Electronics, Inc.
Document Number
Rev
0.1
Monday, March 01, 2010
Sheet
1
46
of
47
8
7
6
5
4
3
2
1
H
H
CPU_B+
PL901
HCB4532KF-800T90_1812
1
2
2
PR902
2_0603_5%
1
2
1
LGATE1
29
28
1
PC920
1U_0603_16V6K
PC915
10U_1206_25V6M
2
1
PC913
10U_1206_25V6M
2
1
[6] CPU_VDD1_FB_H
3
2
1
PR939
10_0402_5%
1
VW1
PC924
2200P_0402_50V7K
2
1
PC923
0.01U_0402_25V7K
2
1
PC922
10U_1206_25V6M
2
1
PC921
10U_1206_25V6M
2
1
4
1
PR936
16.2K_0402_1%
PR934
4.7_1206_5%
1 2
4
D
1
4
2
3
1 PR937 2
4.02K_0402_1%
PC926
680P_0603_50V7K
+CPU_CORE
C
PC927
2
1
2
PC925
0.22U_0603_10V7K
DIFF_1
+CPU_CORE
Design Current: 25A
Max current: 35A
OCP_min:45A
PL904
0.36UH_PCMC104T-R36MN1R17_30A_20%
5
10_0402_5%
1
2
2
1
1 2
0.1U_0402_16V7K
2
PR935 10K_0402_1%
2
1
+CPU_CORE
E
PC919
2
1
ISP0
PR932
2.2_0603_5%
BOOT1 1
2 1
@ PR938 1K_0402_1%
2
1
+1.5VS
VW0
1
3
2
1
5
TP
49
ISN1
ISP1
24
22
VW1
COMP1
FB1
21
20
ISN1
4
PHASE1
PQ907
TPCA8028-H_SOP-ADVANCE8-5
[6] CPU_VDD1_FB_L
UGATE1
C
DIFF_0
PC918
680P_0603_50V7K
CPU_B+
3
2
1
PR933
2
BOOT1
PQ905
TPCA8030-H_SOP-ADV8-5
[6] CPU_VDD0_FB_L
23
0_0402_5%
PR929
2
UGATE1
25
PQ906
TPCA8028-H_SOP-ADVANCE8-5
1
PHASE1
26
3
2
1
PR928
2
1
10_0402_5%
27
1 PR923 2
4.02K_0402_1%
+CPU_CORE
LGATE0
5
+CPU_CORE
BOOT1
ISP1
ISP0
ISN0
[6] CPU_VDD0_FB_H
19
13
D
ISN0
ISP0
VW0
VDIFF1
UGATE1
VSEN1
COMP0
RTN1
PHASE1
RTN0
12
FB0
VSEN0
11
PR927 0_0402_5%
2
1
16
0_0402_5%
2 PR930 1
17
0_0402_5%
2 PR931 1
18
10
3
ISN0
PGND1
31
30
4
2
PR920
4.7_1206_5%
2
VDIFF0
LGATE0
4
1
2
LGATE1
ISL6265IRZ-T_QFN48_6X6~D
4
+5VS
PR922
16.2K_0402_1%
2
PVCC
PHASE0
32
PQ904
TPCA8028-H_SOP-ADVANCE8-5
LGATE0
UGATE0
5
PGND0
34
33
PC917
0.22U_0603_10V7K
3
2
1
SVC
BOOT0
PL903
0.36UH_PCMC104T-R36MN1R17_30A_20%
2
PQ902
TPCA8028-H_SOP-ADVANCE8-5
PHASE0
35
PR917
2.2_0603_5%
BOOT0 1
2 1
5
UGATE0
SVD
BOOT_NB
PQ903
TPCA8030-H_SOP-ADV8-5
1
37
UGATE_NB
38
39
LGATE_NB
PHASE_NB
41
40
PGND_NB
OCSET_NB
PWROK
36
PC914
2200P_0402_50V7K
2
1
2
43
42
RTN_NB
44
45
FB_NB
46
VCC
BOOT0
OCSET
9
4
F
1
1
95.3K_0402_1%
BOOT_NB
RBIAS
PR926
UGATE0
PHASE0
ENABLE
8
[6]
PC916
0.01U_0402_25V7K
2
1
1
5
6
7
2
CPU_VDDNB_FB_L
3
2
1
1
0_0402_5%
[34] VR_ON
PR925
2
1
21.5K_0402_1%
1
PGOOD
15
2
PR924
[6] CPU_SVC
PC910
220U_D2_4VM
CPU_B+
1
5
VSEN_NB
4
3
1
0_0402_5%
FSET_NB
2
PR921
COMP_NB
2
47
48
VIN
PR918 0_0402_5%
1
2
1
2
PR919 0_0402_5% @
OFS/VFIXEN
14
[6] CPU_SVD
+
UGATE_NB
1
PU901
2
E
[6]
PR915
10_0402_5%
PR916
@ 105K_0402_1%
2
2
[20] H_PWRGD_L
2
LGATE_NB
PR912
0_0402_5%
1
[34] VGATE
1
PC911
680P_0603_50V7K
G
+VDDNB
Design Current: 2.8A
Max current: 4A
OCP_min:5A
PHASE_NB
2
PR911
@ 105K_0402_1%
+CPU_CORE_NB
PR905
4.7_1206_5%
PHASE_NB
2
2
1
1
PR914
@ 10K_0402_1%
+
2
2
CPU_VDDNB_FB_H
PR909
11.3K_0402_1%
2
1
PR908
0_0402_5%
2
PR913
105K_0402_1%
1 2
PC909
0.22U_0603_10V7K
+CPU_CORE_NB
2
F
PC912
0.1U_0402_16V7K
1
PR910
0_0402_5%
2
2
PR907
2_0603_5%
+3VS
1
+5VS
1
2
3
4
D2
D2
G1
S1
PL902
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2
PR903
0_0603_5%
BOOT_NB 1
2 1
PR906
10_0402_5%
1
2
CPU_B+
G2
S2/D1
S2/D1
S2/D1
PHASE_NB
PR904
22K_0402_1%
2
1
2
PC908
0.1U_0402_16V7K
1
8
7
6
5
1
AO4932_SO8
PC907
1000P_0402_50V7K
2
1
G
1
+5VS
UGATE_NB
1
PC902
1200P_0402_50V7K
B+
PC906
100U_25V_M
1
PR901
44.2K_0402_1%
PC904
0.01U_0402_25V7K
2
1
PC903
10U_1206_25V6M
2
1
PQ901
2
PC905
2200P_0402_50V7K
2
1
LGATE_NB
PC901
33P_0402_50V8K
2
1
0.1U_0402_16V7K
2
1
COMP0
PC929
180P_0402_50V8J
PR942
1K_0402_5%
2
1
B
PR943
2
1
PC934
2
1
2
PR941
PC931
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1
1
PC930
1000P_0402_50V7K
2
1
COMP1
PC932
180P_0402_50V8J
PR944
6.81K_0402_1%
2
1
PR945
1K_0402_5%
2
1
PR946
2
1
PC933
1000P_0402_50V7K
PR947
6.81K_0402_1%
2
1
B
54.9K_0402_1% 1200P_0402_50V7K
1
1
54.9K_0402_1% 1200P_0402_50V7K
PC935
2
1
1
2
ISP1
PR940
PC928
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1
ISN1
LGATE1
PR948
@ 1K_0402_1%
2
2
PR949
@ 1K_0402_1%
A
A
Compal Secret Data
Security Classification
2009/01/06
Issued Date
Deciphered Date
2010/01/06
Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Date:
8
7
6
5
4
3
Compal Electronics, Inc.
2
Document Number
Monday, March 01, 2010
Rev
0.1
47
Sheet
1
of
47
www.s-manuals.com
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.6
Linearized : No
XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date : 2012:06:11 20:20:43+07:00
Creator Tool : PScript5.dll Version 5.2.2
Modify Date : 2014:10:14 22:05:23+03:00
Metadata Date : 2014:10:14 22:05:23+03:00
Producer : Acrobat Distiller 10.0.0 (Windows)
Format : application/pdf
Creator :
Title : Compal LA-5754P - Schematics. www.s-manuals.com.
Subject : Compal LA-5754P - Schematics. www.s-manuals.com.
Document ID : uuid:fb279470-045c-415b-8b23-c1a26e9c6338
Instance ID : uuid:670a90ee-ee0f-44a6-b276-92911c0a3d87
Page Count : 48
Keywords : Compal, LA-5754P, -, Schematics., www.s-manuals.com.
Warning : [Minor] Ignored duplicate Info dictionary
EXIF Metadata provided by EXIF.tools