Compal LA 6041P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-6041P NALAA Hamburg 10 - Schematics. Free.
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A B C D E 1 1 NALAA Hamburg 10 2 2 LA-6041P REV 1.0 Schematic Intel Arrandale /IBEX PEAK 3 3 2009-10-01 Rev 1.0 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet E 1 of 48 A B C Compal Confidential D E Fan Control Intel Arrandale Model Name : NALAA File Name : LA-6041P Clock Generator APL5607KI-TRG RTM890N-631-GRT page 6 page 13 1 1 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 rPGA-989 Dual Channel page 5,6,7,8,9,10 1.5V DDRIII 800/1066 MT/s USB/B FDI X8 DMI X4 2.7GHz 2.5GHz page 11,12 BANK 0, 1, 2, 3 BT conn USB port 0,1 USB port 5 page 30 page 26 RTS5138-GR USB port 10 3IN1 USB port 11 page 31 USB LCD Conn. Int. Camera page 13 5V 480MHz page 13 2 2 CRT PCIeMini Card WiMax page 14 USB USB port 13 page 27 5V 480MHz HDMI Conn. PCIe 1x HDMI Level Shifter PCIeMini Card WLAN 1.5V 2.5GHz(250MB/s) page 15 PCIe port 2 page 27 Intel Ibex Peak page 15 SATA port 1 5V 3GHz(300MB/s) RJ45 PCIe 1x RTL8105E-GR 10/100M page 28 PCIe port 1 page 28 SATA port 4 BGA-951 1.5V 2.5GHz(250MB/s) 5V 3GHz(300MB/s) 3 SATA HDD page 25 SATA ODD page 25 3 SATA port 5 5V 3GHz(300MB/s) USB port 3 Power/B eSATA 5V 480MHz HD Audio RTC CKT. page 34 page 25 USB USB port 3 page 25 3.3V/1.5V 24MHz HDA Codec MDC 1.5 Conn page 16 SPI ROM page 16 USB/B 3.3V 33 MHz LPC BUS page 16~24 Debug Port ENE KB926 E0 page 33 ALC259-GR page 26 page 29 page 32 DC/DC Interface CKT. page 30 page 35 Touch Pad 4 ODD/B page 26 Power Circuit DC/DC page 25 Int.KBD page 26 page 33 2009/01/23 Issued Date Deciphered Date B C HP CONN page 30 SPK CONN page 30 4 Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A MIC CONN page 30 Compal Secret Data Security Classification page 36~44 Int. MIC CONN (LVDS CONN) page 13 EC ROM D Title Block Diagrams Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet E 2 of 48 5 4 3 2 1 NALAA Hamburg Intel Arrandale (UMA) B+ Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW DESIGN CURRENT 4A +5VS DESIGN CURRENT 5A +3VALW DESIGN CURRENT 330mA +3V_LAN DESIGN CURRENT 4A +3VS SUSP D D N-CHANNEL SI4800 TPS51125RGER Ipeak=5A, Imax=3.5A, Iocp min=7.7 WOL_EN# P-CHANNEL AO-3413 SUSP N-CHANNEL VGA_ENVDD SI4800 DESIGN CURRENT 1.5A P-CHANNEL AO-3413 C +LCD_VDD C BT_PWR# DESIGN CURRENT 180mA +BT_VCC Ipeak=48A, Imax=33.6A, Iocp min=57.28 DESIGN CURRENT 48A +CPU_CORE Ipeak=22A, Imax=15.4A, Iocp min=26 DESIGN CURRENT 22A +GFX_CORE Ipeak=20A, Imax=14A, Iocp min=27.49 DESIGN CURRENT 20A +VTT P-CHANNEL AO-3413 VR_ON ISL62883 GFXVR_EN ADP3211AMNR VTTP_EN# B B APW7138NITRL +1.05VS SYSON Ipeak=9A, Imax=6.3A, Iocp min=9.8 DESIGN CURRENT 9A +1.5V DESIGN CURRENT 1.2A +1.5VS DESIGN CURRENT 1.5A +0.75VS DESIGN CURRENT 1.5A +1.8VS +1.5V_CPU SUSP RT8209BGQW N-CHANNEL SUSP SI4856 G2992F1U SUSP# MP2121DQ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Power Tree Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 3 of 48 A B ( O MEANS ON Voltage Rails +RTCVCC C X MEANS OFF ) +B E BTO Option Table +5VALW +5VS +1.5V +3VALW +3VS +VSB +1.5VS power plane 1 D Bluetooth RJ11 LAN HDMI Card Reader description (B) (R) (E) (Y) (W) explain Bluetooth MDC LAN HDMI Card Reader BTO BT@ MDC@ Function Express Card Mini Card 1 +VGA_CORE New Card PCMCIA WIRELESS +CPU_CORE +VTT IHDMI@ WLAN@ CARD@ +1.05VS +1.8VS +1.1VS State S0 O O O O O S1 O O O O O S3 O O O O X S5 S4/AC O O O 2 3 +0.75VS SIGNAL Full ON X X S5 S4/ Battery only O O X X X S5 S4/AC & Battery don't exist O X X X X EC SM Bus1 address Power STATE Device Address +3VALW EC KB926 D3 +3VALW Smart Battery 0001 011x b 2 SLP_S3# SLP_S4# SLP_S5# HIGH HIGH HIGH S1(Power On Suspend) HIGH HIGH HIGH S3 (Suspend to RAM) LOW HIGH HIGH S4 (Suspend to Disk) LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW 3 EC SM Bus2 address Power Device +3VS EC KB926 D3 Address +3VS VGA THM Sensor ADM1032ARMZ 1001 110x b +3VS PCH 0100 110x b PCH SM Bus address 4 Power Device +3VALW PCH Address +3VS Clock Generator 1101 001x b +3VS DDR DIMM0 1001 000x b +3VS DDR DIMM1 1001 010x b +3VS Express +3VS WLAN/Wimax/3G 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet E 4 of 48 4 3 2 1 NPS@ JCPUB AT15 2 PECI R10 68_0402_5% @ 1 R9 AN26 PROCHOT# 1 +VTT 2 1 C225 100P_0402_50V8J H_PROCHOT#_D 2 68_0402_5% PECI AK15 21 H_THERMTRIP# H_CPURST# XDP_RST#_R PMSYNCH 1 H_PWRGOOD1_R R25 2 0_0402_5% +1.5V_CPU C H_PWRGOOD RESET_OBS# AL15 PM_SYNC AN14 VCCPW RGOOD_1 AN27 VCCPW RGOOD_0 2 21 H_PWRGOOD AP26 PWR MANAGEMENT 18 H_CPURST# 2 1K_0402_5% 1 R36 THERMTRIP# R28 1.1K_0402_1% NPS@ 18 DRAMPWROK 1 40 VTTPWROK_CPU DRAMPWROK AK13 SM_DRAMPW ROK VTTPWROK_CPU AM15 VTTPW RGOOD AM26 TAPPW RGOOD AL14 RSTIN# DRAMPWROK 2 TAPPWRGD R29 3K_0402_1% NPS@ 20 BUF_PLT_RST# 1.5K_0402_1% R30 1 R31 750_0402_1% CLK_PEG 17 CLK_PEG# 17 Unused by Clarksfield rPGA989 F6 SM_DRAMRST# R6 1 R7 1 R8 1 AN15 PM_EXTTS#0 AP15 PM_EXTTS#_R PM_EXT_TS#[0] PM_EXT_TS#[1] PRDY# PREQ# AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 2 R12 2 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% 1 0_0402_5% AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 DRAMPWROK Add on 11/09 2 +VTT PM_EXTTS#0 PM_EXTTS# 11,12 R15 2 1 10K_0402_5% PM_EXTTS#_R R13 2 1 10K_0402_5% XDP_TDI_R 1 R20 2 0_0402_5% XDP_TDI XDP_TDO_M 1 @ R21 2 0_0402_5% XDP_TDO 1 @ R26 2 0_0402_5% 1 R27 2 0_0402_5% R23 0_0402_5% 2 R312 1 1K_0402_5% +3VS XDP_DBRESET# 18 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_PRDY# 1 @ C7 XDP_PREQ# 1 @ C8 XDP_TCK 1 @ C9 XDP_TMS 1 @ C10 XDP_TRST# 1 @ C11 XDP_TDI_R 1 @ C12 XDP_TDO_R 1 @ C13 XDP_TDI_M 1 @ C14 XDP_TDO_M 1 @ C15 XDP_DBRESET# 1 @ C17 Close to JCPU C384 C314 PS@ 0.047U_0402_16V7K DDR3 Compensation Signals Layout Note:Please these resistors near Processor Routed as a single daisy chain EMI reverse, close to JCPU 2 D XDP_TDI_M BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] SM_DRAMRST# 11,12 Q41 BSS138_NL_SOT23-3 PS@ RST_GATE 21 C XDP_TDO_R R29 750_0402_1% PS@ B 1 SM_DRAMRST#_CPU AL1 SM_RCOMP_0 AM1 SM_RCOMP_1 AN1 SM_RCOMP_2 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] IC,AUB_CFD_rPGA,R0P9 @ VTTPWROK_CPU 3 PS@ R127 100K_0402_5% 2 A18 A17 SM_DRAMRST#_CPU 1 DPLL_REF_SSCLK DPLL_REF_SSCLK# CLK_CPU_XDP_R 1 CLK_CPU_XDP 2 CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP# R42 @ 0_0402_5% 1 For prevent noise issue 21 PEG_CLK PEG_CLK# E16 D16 1 CATERR# AR30 AT30 1 0_0402_5% 2 SKTOCC# AK14 CLOCKS AH24 CATERR# DDR3 MISC TP_SKTOCC# BCLK_ITP BCLK_ITP# JTAG & BPM COMP0 2 R19 CLK_CPU_BCLK 21 CLK_CPU_BCLK# 21 G +VTT 2 49.9_0402_1% COMP1 THERMAL 1 R18 COMP2 A16 B16 BCLK BCLK# D T41 D COMP3 S PAD +VTT H_COMP3 AT23 2 20_0402_1% H_COMP2 AT24 2 20_0402_1% H_COMP1 G16 2 49.9_0402_1% H_COMP0 AT26 2 49.9_0402_1% MISC 1 R1 1 R2 1 R4 1 R3 2 5 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K JTAG MAPPING Scan Chain (Default) STUFF -> R20, R23, R27 NO STUFF -> R21, R26 CPU Only STUFF -> R20, R21 NO STUFF -> R23, R26, R27 GMCH Only STUFF -> R26, R27 NO STUFF -> R20, R21, R23 XDP Connector 1 B 1000P_0402_50V7K SFF-24Pin 2 1 JXDP C389 XDP_PREQ# XDP_PRDY# 1000P_0402_50V7K XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 +3VALW IN2 O @ 2 0_0402_5% 4 R33 +VTT DRAMPWROK PS@ 1.5K_0402_1% SN74AHC1G08DCKR_SC70-5 PS@ XDP_RST#_R XDP_DBRESET# 1 C1 0.1U_0402_16V7K @ 2 1 R84 A H_PWRGOOD_R TAPPWRGD_R CLK_CPU_XDP CLK_CPU_XDP# 2 51_0402_5% 1 IN1 2 P 1 U16 G VTTPWROK 3 35,40 VTTPWROK H_PWRGOOD TAPPWRGD 2 0.1U_0402_16V7K 1K_0402_5% 2 2 0_0402_5% XDP_TDO XDP_TRST# XDP_TDI XDP_TMS 2 5 1 C25 @ R32 1 1 @ R35 XDP_TCK 1 R14 R11 51_0402_5% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND 25 26 A MOLEX_52435-2472 @ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 2010/01/23 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU CLK/MISC/JTAG/XDP Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 5 of 48 5 4 3 2 1 D D JCPUA A24 C23 B22 A21 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] 18 18 18 18 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] 18 18 18 18 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] 18 18 18 18 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] 18 18 18 18 18 18 18 18 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] 18 FDI_FSYNC0 18 FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] 18 FDI_INT C17 FDI_INT 18 FDI_LSYNC0 18 FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] Intel(R) FDI 18 18 18 18 18 18 18 18 B PCI EXPRESS -- GRAPHICS DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 DMI C 18 18 18 18 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_COMP 1 R38 2 49.9_0402_1% PEG_RBIAS 1 R39 2 750_0402_1% C FAN Control Circuit +5VS B 1A 2 C3 10U_0805_10V4Z JFAN +FAN1 1 1 U1 1 2 3 4 +FAN1 32 EN_DFAN1 10mil 1 2 IC,AUB_CFD_rPGA,R0P9 @ EN VIN VOUT VSET GND GND GND GND C4 1000P_0402_50V7K 2 @ 8 7 6 5 1 2 3 1 2 3 4 5 GND GND ACES_85204-0300N @ G996P11U_SOP8 C5 10U_0805_10V4Z R34 2 10K_0402_5% 1 +3VS FAN_SPEED1 32 2 C6 0.01U_0402_16V7K 1 @ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU DMI/FDI/PEG/FAN Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 6 of 48 5 4 3 2 JCPUC JCPUD 12 DDR_B_D[0..63] D C B A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 SA_BS[0] SA_BS[1] SA_BS[2] 11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_W E# AE1 AB3 AE9 SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 DDRA_CLK0 11 DDRA_CLK0# 11 DDRA_CKE0 11 SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 DDRA_CLK1 11 DDRA_CLK1# 11 DDRA_CKE1 11 SA_CS#[0] SA_CS#[1] AE2 AE8 DDRA_SCS0# 11 DDRA_SCS1# 11 SA_ODT[0] SA_ODT[1] AD8 AF9 DDRA_ODT0 11 DDRA_ODT1 11 DDR_A_DM[0..7] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SA_CK[0] SA_CK#[0] SA_CKE[0] B9 D7 H7 M7 AG6 AM7 AN10 AN13 11 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DQS#[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] 11 11 11 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] 12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# 12 12 12 SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 DDRB_CLK0 12 DDRB_CLK0# 12 DDRB_CKE0 12 SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 DDRB_CLK1 12 DDRB_CLK1# 12 DDRB_CKE1 12 SB_CS#[0] SB_CS#[1] AB8 AD6 DDRB_SCS0# 12 DDRB_SCS1# 12 SB_ODT[0] SB_ODT[1] AC7 AD1 DDRB_ODT0 12 DDRB_ODT1 12 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DM[0..7] D 12 C DDR SYSTEM MEMORY - B 11 DDR_A_D[0..63] 11 11 11 1 DDR_B_DQS#[0..7] DDR_B_DQS[0..7] 12 12 B DDR_B_MA[0..15] 12 IC,AUB_CFD_rPGA,R0P9 @ A A IC,AUB_CFD_rPGA,R0P9 @ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU DDRIII Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 7 of 48 5 4 A (Place these capacitors between inductor and socket on Bottom) +VTT +CPU_CORE AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K + D C159 1 C160 1 2 390U_2.5V_M_R10 C81 1 2 10U_0805_10V4K 2 390U_2.5V_M_R10 C83 1 2 10U_0805_10V4K C85 1 2 10U_0805_10V4K 1 2 + VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 (Place these capacitors under CPU socket Edge, top layer) 1 C71 2 10U_0805_10V4K C87 1 2 10U_0805_10V4K C89 1 2 22U_0805_6.3V6M C88 1 2 10U_0805_10V4K C91 1 2 22U_0805_6.3V6M C90 1 2 10U_0805_10V4K C92 1 2 10U_0805_10V4K C94 1 2 10U_0805_10V4K@ 1 C72 2 1 C73 2 10U_0805_10V4K 1 C74 2 1 C75 2 10U_0805_10V4K 1 C76 2 1 C77 2 10U_0805_10V4K 1 C78 2 C79 10U_0805_10V4K (Place these capacitors under CPU socket, top layer) +CPU_CORE 10U_0805_10V4K 1 2 10U_0805_10V4K 1 C98 2 10U_0805_10V4K VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 Add on 5/25 for power team request AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 1 C99 2 10U_0805_10V4K 1 C100 2 10U_0805_10V4K 1 C101 2 1 C102 2 10U_0805_10V4K 1 C103 C104 2 10U_0805_10V4K 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C105 1 C148 @ C144 @ 2 1 C131 @ 2 22U_0805_6.3V6M 1 C130 2 @ 22U_0805_6.3V6M 1 C132 @ 2 1 C +CPU_CORE +CPU_CORE C129 2 22U_0805_6.3V6M @ 1 2 C149 @ 1 C106 1 22U_0805_6.3V6M 1 C107 C108 1 C109 22U_0805_6.3V6M 1 C110 1 1 2 2 2 22U_0805_6.3V6M 2 2 22U_0805_6.3V6M 2 2 22U_0805_6.3V6M 22U_0805_6.3V6M +CPU_CORE 22U_0805_6.3V6M C111 1 C112 2 PSI# VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR VTT_SELECT AN33 H_PSI# AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 H_DPRSLPVR_R 1 R62 CPU_VID0 43 CPU_VID1 43 CPU_VID2 43 CPU_VID3 43 CPU_VID4 43 CPU_VID5 43 CPU_VID6 43 H_DPRSLPVR 43 2 0_0402_5% G15 T43 CRB default setting: VID[6:0]=[0100111] 43 VTT Rail ISENSE VCC_SENSE VSS_SENSE AN35 AJ34 AJ35 C113 2 C114 2 1 C115 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C116 2 1 2 22U_0805_6.3V6M B Co-layout with C123 +CPU_CORE +CPU_CORE C121 H_VTTSELECT = low, 1.1V 1 330U_D2_2.5VY_R9M 1 + + C122 330U_D2_2.5VY_R9M 2 2 C123 1 + 330U_D2_2.5VY_R9M 1 C124 330U_D2_2.5VY_R9M 2 1 + + 2 C125 220U_6.3V_M @ 2 IMVP_IMON 43 VCCSENSE_R R65 VSSSENSE_R R66 1 1 2 0_0402_5% 2 0_0402_5% 1 R64 VCCSENSE VSSSENSE 1 VTT_SENSE VSS_SENSE_VTT 22U_0805_6.3V6M 1 TOP side (under inductor) Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V PAD 1 22U_0805_6.3V6M H_VTTSELECT = high, 1.05V B15 A15 VTT_SENSE 40 VSS_SENSE_VTT 40 R67 2 100_0402_1% +CPU_CORE Check list: VCCSENSE 43 VSSSENSE 43 +CPU_CORE: 6x 470uF, 12x 22uF, 16x 10uF 2 100_0402_1% near CPU +VTT: 4x 330uF, 7x 22uF, 8x 10uF A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification IC,AUB_CFD_rPGA,R0P9 @ 5 1 (Place these capacitors on CPU cavity, Bottom Layer) POWER VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 1.1V RAIL POWER Auburndale:18A CPU CORE SUPPLY B Clarksfield: 21A Auburndale:48A CPU VIDS C AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Clarksfield: 65A SENSE LINES D 2 Material Note (+VTT): 330uF/ 6mohm, number are 3, power x1, HW x2 JCPUF +CPU_CORE 3 2009/01/23 2010/01/23 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title CPU POWER-1 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 8 of 48 5 4 3 2 +1.5V_CPU +1.5V Q33 1 2 3 4 2 R424 470_0805_5% PS@ S S S G FDS6676AS_SO8 1 2N7002KDW _SOT363-6 +GFX_CORE 2 PS@ D R417 820K_0402_5% PS@ Q46A PS@ 2 SUSP 1 5 0.1U_0402_25V6 C472 SUSP +VSB 6 1 1 PS@ 1 R418 2 220K_0402_5% PS@ Q46B 47P_0402_50V8J D D D D 8 7 6 5 10U_0805_10V4K 2 PS@ 3 1 C93 @ 2 C119 @ C267 4 47P_0402_50V8J 1 1 C118 @ 47P_0402_50V8J 2 2 D C97 @ 2 1 47P_0402_50V8J 1 PS@ 2 +GFX_CORE 1 SUSP 35,42 2N7002KDW _SOT363-6 near CPU JCPUG 1 2 1 2 22U_0805_6.3V6M C127 1 2 C117 1 C96 2 1U_0402_6.3V4Z 1 1 C120 2 C86 10U_0805_6.3V6M 2 10U_0805_6.3V6M J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 GRAPHICS C Clarksfield: 5A Auburndale:3A +VTT C141 22U_0805_6.3V6M 1 2 1 2 C142 FDI B VAXG_SENSE VSSAXG_SENSE GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 2 C147 22U_0805_6.3V6M VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 (Place these capacitors under CPU socket, top layer) 1 R50 2 330_0402_5% AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 2 0.1U_0402_16V4Z C205 1 2 0.1U_0402_16V4Z C186 1 2 0.1U_0402_16V4Z +1.5V_CPU 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M 2 1 1 C133 C 1 C134 2 1 C135 2 1U_0402_6.3V4Z 1 C136 1 C137 2 2 1U_0402_6.3V4Z 1 C138 2 1 C139 2 1U_0402_6.3V4Z PJ30 @ 2 1 1 +1.5V JUMP_43X79 + C217 2 2 390U_2.5V_M_R10 22U_0805_6.3V6M B VTT0_59 VTT0_60 VTT0_61 VTT0_62 P10 N10 L10 K10 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 (Place these capacitors under CPU socket Edge, top layer) 1 2 C143 10U_0805_10V4K +VTT 1 2 C145 22U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) +1.8VS VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 Clarksfield: 0.6A Auburndale:1.35A +1.8VS_H_PLL 1U_0402_6.3V4Z C151 1U_0402_6.3V4Z 1 1 2 2 4.7U_0603_6.3V6K 1 C152 2 R71 1 0_0805_5% 1 C153 C154 2 C155 2 22U_0805_6.3V6M A 2.2U_0603_6.3V4Z IC,AUB_CFD_rPGA,R0P9 @ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 2 0.1U_0402_16V4Z C218 1 1 1K_0402_5% A 5 C230 1 +VTT 1.1V K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 2 100_0402_1% 44 44 44 44 44 44 44 GFXVR_EN 44 T42 PAD GFXVR_IMON 44 +GFX_CORE VCC_AXG_SENSE 44 VSS_AXG_SENSE 44 @ 1.8V 2 1 2 0_0402_5% 2 0_0402_5% 1 1 GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 Auburndale:18A PEG & DMI 22U_0805_6.3V6M AM22 AP22 AN22 AP23 AM23 AP24 AN24 R687 2 22U_0805_6.3V6M +VTT C146 R95 R94 1 Clarksfield: 21A 1 VCC_AXG_SENSE_R VSS_AXG_SENSE_R AR22 AT22 R69 - 1.5V RAILS 2 C95 2 100_0402_1% R82 Auburndale:22A DDR3 390U_2.5V_M_R10 1 C185 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 SENSE LINES 1 + AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 GRAPHICS VIDs 1U_0402_6.3V4Z POWER 22U_0805_6.3V6M 3 2 Title CPU POWER-2 Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 9 of 48 4 3 JCPUI C B 1 JCPUH VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS NCTF D K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 2 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 H_NCTF6 H_NCTF7 PAD T4 PAD T5 PAD T6 PAD T7 IC,AUB_CFD_rPGA,R0P9 @ AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPUE VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 3.01K_0402_1% 1 @ R74 2 3.01K_0402_1% 1 @ R75 3.01K_0402_1% 1 @ R76 2 2 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 Reserve via for test RSVD17 RSVD18 B19 A19 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 CFG0 - PCI-Express Configuration Select *1:Single PEG 0:Bifurcation enabled C1 A3 CFG3 - PCI-Express Static Lane Reversal *1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ... RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 D C RSVD64 RSVD65 Reserve via for test RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 B VSS CFG4 - Display Port Presence *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port IC,AUB_CFD_rPGA,R0P9 @ RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 (SA_DIMM_VREF) RSVD10(SB_DIMM_VREF) RSVD11 RSVD12 RSVD13 RSVD14 RESERVED 5 AP34 IC,AUB_CFD_rPGA,R0P9 @ *:Default A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU GND/RESERVED Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 10 of 48 4 3 +1.5V DDR3 SO-DIMM A Standard Type JDDRH DDR_A_D8 DDR_A_D9 D DDR_A_DQS#1 DDR_A_DQS1 close to JDDRL.1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 7 DDRA_CKE0 C 7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 7 7 DDRA_CLK0 DDRA_CLK0# DDR_A_MA10 7 DDR_A_BS0 7 7 DDR_A_W E# DDR_A_CAS# DDR_A_MA13 7 DDRA_SCS1# DDR_A_D32 DDR_A_D33 B DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 R90 1 2 10K_0402_5% A 2 1 2 5 R91 10K_0402_5% 2 1 1 C182 0.1U_0402_16V4Z C181 2.2U_0603_6.3V4Z +3VS +0.75VS CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT 205 207 GND1 GND2 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 BOSS1 BOSS2 206 208 +1.5V 2 R78 7 DDR_A_DQS#[0..7] 1 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 M1 Circuit 7 DDR_A_DQS[0..7] DDR_A_DQS#0 DDR_A_DQS0 7 DDR_A_D[0..63] +1.5V R79 1K_0402_1% 7 DDR_A_DM[0..7] DDR_A_D6 DDR_A_D7 7 DDR_A_MA[0..15] R83 1K_0402_1% PS@ DDR_A_D12 DDR_A_D13 DDR_A_DM1 1 0_0402_5% +VREF_DQB +V_DDR3_DIMM_REF 2 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 2 R80 1 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 1 0_0402_5% +VREF_DQA D R81 1K_0402_1% SM_DRAMRST# 5,12 2 DDR_A_DM0 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 1 1 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 2 2 DDR_A_D0 DDR_A_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDRA_CKE1 7 DDR_A_MA15 DDR_A_MA14 C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDRA_CLK1 7 DDRA_CLK1# 7 DDR_A_BS1 7 DDR_A_RAS# 7 DDRA_SCS0# 7 DDRA_ODT0 7 +V_DDR3_DIMM_REF DDRA_ODT1 7 R89 1 0_0402_5% +DDR_VREF_CA_DIMMA DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 C161 2.2U_0603_6.3V4Z 1 C157 2.2U_0603_6.3V4Z C156 0.1U_0402_16V4Z +VREF_DQA 2 1 2 2 B Layout Note: Place near JDDRH 1 Layout Note: Place these 4 Caps near Command and Control signals of JDDRH Layout Note: Place near JDDRH.203 and 204 2 +1.5V +1.5V C268 1 + +1.5V C162 0.1U_0402_16V4Z 5 DDR_A_D46 DDR_A_D47 C166 1 +0.75VS 2 390U_2.5V_M_R10 close to JDDRL.126 C164 1 2 0.1U_0402_16V4Z C167 1 2 0.1U_0402_16V4Z C170 1 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M C169 2 1 1U_0402_6.3V4Z C172 2 1 1U_0402_6.3V4Z C175 2 1 1U_0402_6.3V4Z C177 2 1 1U_0402_6.3V4Z C22 1 68P_0402_50V8J 2 10U_0805_6.3V6M C168 1 2 10U_0805_6.3V6M DDR_A_D52 DDR_A_D53 C171 1 2 10U_0805_6.3V6M DDR_A_DM6 C174 1 2 10U_0805_6.3V6M DDR_A_D54 DDR_A_D55 C176 1 2 10U_0805_6.3V6M C178 1 2 10U_0805_6.3V6M C173 1 C21 1 2 0.1U_0402_16V4Z 2 68P_0402_50V8J For EMI Request DDR_A_D60 DDR_A_D61 2 For EMI Request DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 A PM_EXTTS# 5,12 PM_SMBDATA 12,13,17,27 PM_SMBCLK 12,13,17,27 +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FOX_AS0A626-U2SN-7F_204P @ 4 3 2 Title DDRIII-SODIMM0 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 11 of 48 B +1.5V C +1.5V 2 1 DDR_B_D2 DDR_B_D3 2 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 close to JDDRH.1 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 7 DDRB_CKE0 2 7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 7 7 DDRB_CLK0 DDRB_CLK0# DDR_B_MA10 7 DDR_B_BS0 7 7 DDR_B_W E# DDR_B_CAS# DDR_B_MA13 7 DDRB_SCS1# DDR_B_D32 DDR_B_D33 3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 R98 1 2 10K_0402_5% 4 +3VS 2.2U_0603_6.3V4Z 1 1 1 R99 2 10K_0402_5% C207 C208 2 2 0.1U_0402_16V4Z +0.75VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT 205 207 GND1 GND2 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 BOSS1 BOSS2 206 208 DDR_B_D4 DDR_B_D5 7 DDR_B_DQS[0..7] DDR_B_D6 DDR_B_D7 7 DDR_B_D[0..63] DDR_B_D12 DDR_B_D13 7 DDR_B_DM[0..7] 1 7 DDR_B_MA[0..15] DDR_B_DM1 SM_DRAMRST# 5,11 DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDRB_CKE1 7 DDR_B_MA15 DDR_B_MA14 2 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 7 DDRB_CLK1# 7 DDR_B_BS1 7 DDR_B_RAS# 7 DDRB_SCS0# 7 DDRB_ODT0 7 DDRB_ODT1 7 DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 +V_DDR3_DIMM_REF R97 1 +DDR_VREF_CA_DIMMB 1 2 2 0_0402_5% Layout Note: Place near JDDRL 1 DDR_B_DQS#5 DDR_B_DQS5 Layout Note: Place these 4 Caps near Command and Control signals of JEERL Layout Note: Place near JDDRL.203 and 204 3 +1.5V +1.5V @ C189 1 2 DDR_B_D44 DDR_B_D45 +0.75VS 2 330U_B2_2.5VM_R15M C192 1 2 10U_0805_6.3V6M C194 1 2 10U_0805_6.3V6M C197 1 2 10U_0805_6.3V6M C200 1 2 10U_0805_6.3V6M C202 1 2 10U_0805_6.3V6M C204 1 2 10U_0805_6.3V6M C190 1 2 0.1U_0402_16V4Z C193 1 2 0.1U_0402_16V4Z C196 1 close to JDDRH.126 C199 1 DDR_B_D46 DDR_B_D47 C23 DDR_B_D52 DDR_B_D53 1 C191 1 2 10U_0805_6.3V6M C195 2 1 1U_0402_6.3V4Z C198 2 1 1U_0402_6.3V4Z C201 2 1 1U_0402_6.3V4Z C203 2 1 1U_0402_6.3V4Z C24 1 68P_0402_50V8J 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 68P_0402_50V8J For EMI Request DDR_B_DM6 2 For EMI Request DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 4 PM_EXTTS# 5,11 PM_SMBDATA 11,13,17,27 PM_SMBCLK 11,13,17,27 +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FOX_AS0A626-UASN-7F_204P @ A 7 DDR_B_DQS#[0..7] DDR_B_DQS#0 DDR_B_DQS0 C188 0.1U_0402_16V4Z 1 DDR_B_DM0 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS C187 2.2U_0603_6.3V4Z 1 C184 0.1U_0402_16V4Z C183 2.2U_0603_6.3V4Z DDR_B_D0 DDR_B_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 E Standard Type DDR3 SO-DIMM B JDDRL +VREF_DQB D + A B C D Title DDRIII-SODIMM1 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet E 12 of 48 A B Clock Generator C D E F G H +3VS_CK505 1 C212 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z 2 +1.05VS For SED FBMH1608HM601-T_0603 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2 R101 1 1 1 C251 47P_0402_50V8J C219 C220 2 C221 R110 10K_0402_5% +1.05VS_CK505 1 C222 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z C252 47P_0402_50V8J CK_PW RGD 1 Q35B 1 Prevent noise coupling 2 0.1U_0402_16V4Z 1 1 1 C213 For SED C231 1U_0402_6.3V6K C214 250mA C215 2 1U_0402_6.3V6K +3VS_CK505 +3VS_CK505 17 17 H_STP_CPU# 2 31 CLK_48M_CR 17 17 CLK_SATA CLK_SATA# 1 CLK_48M_CR_R 2 CARD@ R390 33_0402_5% 17 PCH_CLK_DMI 17 PCH_CLK_DMI# H_STP_CPU# 1 2 3 4 5 6 7 8 VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48 SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP# VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC 24 23 22 21 20 19 18 17 33 10K_0402_5% 2 CPU_SEL Routing the trace at least 10mil Y1 CLK_XTAL_IN 1 2 2 2 14.318MHZ_16PF_7A14300083 C223 C224 22P_0402_50V8J 22P_0402_50V8J 1 1 TGND 1 1 R108 100K_0402_5% 2 W=60mils 3 Q17 AO3413_SOT23 2 1 1 3 C229 0.01U_0402_25V7K 1 +LCD_VDD W=60mils 2 1 4 2 1 2 47K_0402_5% Q1B 2N7002KDW _SOT363-6 5 UMA_ENVDD 2 G 6 2 +3VS +3VS D 19 R112 100K_0402_5% C233 0.1U_0402_16V4Z 19 19 19 19 19 19 LCD_TXOUT0+ LCD_TXOUT0LCD_TXOUT1+ LCD_TXOUT1LCD_TXOUT2+ LCD_TXOUT2- 19 19 19 19 19 19 LCD_TZOUT0+ LCD_TZOUT0LCD_TZOUT1+ LCD_TZOUT1LCD_TZOUT2+ LCD_TZOUT2- 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 +LCD_INV Calpella PCH request 100K ohm 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 GND GMD 20 USB20_P11 4 1 2 2 USB20_N11_R 4 3 3 USB20_P11_R R92 1 B 133MHz 133MHz 1 100MHz 100MHz BKOFF#_R 1 2 R24 33_0402_5% C226 0.1U_0402_16V4Z 2 C227 4.7U_0805_10V4Z 3 LCD_TXCLK+ 19 LCD_TXCLK- 19 D58 LCD_TZCLK+ 19 LCD_TZCLK- 19 INT_MIC_CLK 2 INT_MIC_DATA 3 1 LCD_EDID_CLK 19 LCD_EDID_DATA 19 INT_MIC_CLK 29 INT_MIC_DATA 29 AZ5125-02S.R7G_SOT23-3 +3VS PCH_PW M 19 +LCDVDD_R BKOFF#_R C302 680P_0402_50V7K +LCD_INV 1 1 2 2 C269 0.1U_0402_16V4Z B+ Rated Current MAX:1000mA For EMI request L2 2 1 FBMA-L11-201209-221LMA30T_0805 C312 68P_0402_50V8J 2 1 2 1 C255 0.1U_0402_25V6 C301 680P_0402_50V7K 2 4 Compal Electronics, Inc. Compal Secret Data 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C +LCD_VDD 1 R113 10K_0402_5% Security Classification Issued Date 0_0402_5% 2 2 L1 1 0_0805_5% 2 1 BKOFF# Prevent EC damage W CM-2012-900T_0805 A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 1 32 0_0402_5% 2 L55 @ USB20_N11 0 (Default) 2 1 Reserve for EMI request 20 CPU_1/1# 1 ACES_87242-4001-09 @ 4 CPU_0/0# JLVDS 0_0603_5% W=20mils R391 1 2 USB20_P11_R USB20_N11_R 1 2 R93 1 CPU_SEL 0.1U_0402_16V4Z 1 2 C270 +3VS_LVDS_CAM 1 R109 1 R106 1.5A S 2 +1.05VS 2 CLK_XTAL_OUT +1.5VS_CK505 10K_0402_5% 2 +LCDVDD_R C228 0.1U_0402_16V7K Q1A 2N7002KDW _SOT363-6 1 R119 IDT Have Internal Pull-Down CLK_BCLK 17 CLK_BCLK# 17 +3VS R107 150_0603_5% @ CK_PW RGD LCD/PANEL BD. Conn. 3 1 R105 PM_SMBCLK 11,12,17,27 PM_SMBDATA 11,12,17,27 CLK_14M_PCH 17 CPU_SEL 1 2 33_0402_5% R102 CLK_XTAL_IN CLK_XTAL_OUT RTM890N-631-GRT_QFN32_5X5 +LCD_VDD 10K_0402_5% 2 SA00003HQ10 U5 CLK_DOT CLK_DOT# CLK_ENABLE# 43 Silego Have Internal Pull-Up +1.5VS_CK505 +3VS_CK505 5 2 2 0.1U_0402_16V4Z +1.05VS_CK505 +1.05VS_CK505 1 2N7002KDW _SOT363-6 +1.5VS_CK505 4 FBMH1608HM601-T_0603 1 2 R126 +1.5VS 2 C211 +3VS_CK505 3 C210 0.1U_0402_16V4Z 1 1 2 2 C209 @ R401 0_0603_5% 1 0.1U_0402_16V4Z 1 1 1 For SED FBMH1608HM601-T_0603 1 2 R100 +3VS 1 For SED 2 For SED D E F Title Clock Generator (CK505)/ LVDS CONN Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 G Sheet 13 of H 48 A B C D E D5 1 D4 1 D3 1 CRT CONNECTOR +3VS 1 C239 2 L5 1 2 NBQ100505T-800Y-N_2P CRT_B_L 1 C240 2 2 1 C241 1 C242 2 1 C243 2 DAN217_SC59 @ 1 3 2 3 2 2 1 C238 CRT_G_L DAN217_SC59 @ 2.2P_0402_50V8C R140 L4 1 2 NBQ100505T-800Y-N_2P 2.2P_0402_50V8C R139 CRT_R_L 2.2P_0402_50V8C R138 L3 1 2 NBQ100505T-800Y-N_2P 2.2P_0402_50V8C UMA_CRT_B 2.2P_0402_50V8C 19 2.2P_0402_50V8C UMA_CRT_G 2 1 150_0402_1% 19 2 1 150_0402_1% UMA_CRT_R 2 1 150_0402_1% 19 3 DAN217_SC59 @ 1 2 +5VS +CRT_VCC_R +CRT_VCC F1 30mil 1 1 2 RB491D_SOT23-3 1 1.1A_6V_MINISMDC110F-2 C237 If=1A @ 0.1U_0402_16V4Z 2 D6 2 3 2 2 +CRT_VCC CRT_R_L D_CRT_HSYNC 1 L6 2 10_0402_5% HSYNC 3 U6 SN74AHCT1G125GW _SOT353-5 D_CRT_VSYNC 1 L7 2 10_0402_5% VSYNC CRT_DDC_DAT CRT_G_L +CRT_VCC 1 2 A 2 4 Y C246 @ 2 HSYNC CRT_B_L +CRT_VCC VSYNC CRT_DDC_CLK G 19 UMA_CRT_VSYNC P OE# 5 1 C245 @ 1 10P_0402_50V8J Y 4 G A JCRT 1 10K_0402_5% 10P_0402_50V8J 2 19 UMA_CRT_HSYNC 2 R141 5 1 2 0.1U_0402_16V4Z P OE# 1 C244 3 U7 SN74AHCT1G125GW _SOT353-5 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 RGND ID0 Red GGND SDA Green BGND Hsync Blue +5V Vsync res SGND SCL GND 16 17 GND GND SUYIN_070546FR015S263ZR @ 3 3 +3VS 5 19 UMA_CRT_DATA Q2B 4 19 UMA_CRT_CLK 1 C247 33P_0402_50V8K 2 @ 1 1 R146 2.2K_0402_5% R147 2.2K_0402_5% 2 Q2A 1 2 2 1 +CRT_VCC 6 CRT_DDC_DAT 2N7002KDW _SOT363-6 CRT_DDC_CLK 3 2N7002KDW _SOT363-6 C249 C248 470P_0402_50V8J 33P_0402_50V8K @ 2 @ 1 1 2 C250 470P_0402_50V8J 2 @ 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 CRT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title D Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet E 14 of 48 5 2 1 +3VS CG2 CG1 CG0 Swing Pre-amp 0 0 0 450 0 0 0 0 1 420 0 -3dB Shortest trace 0 1 0 450 0 -3dB Shortest trace 0 1 1 460 0 -4dB 11/16 Add circuit to control OE# pin for save power consumption 1 Slew-rate 0 0 340 0 0 1 0 1 400 2dB 0 Longest trace 1 1 0 400 2dB 0 Longest trace 1 1 1 420 0 0 2 2 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 C266 C257 C258 C262 C263 C261 IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ 1 1 2 2 0.1U_0402_16V4Z Q51A 2N7002KDW _SOT363-6 IHDMI@ C260 IHDMI@ 0.1U_0402_16V4Z D HDMI_HPD_R 2 2 1 OE# +3VS C256 IHDMI@ 10U_0805_10V4Z 2 R37 10K_0402_5% IHDMI@ R170 IHDMI@ 100K_0402_5% 1 2 C430 IHDMI@ 0.1U_0402_16V4Z 1 * 3 1 D 4 U10 3 SCL_SOURCE 10 UMA_DVI_TXD2- 1 2 R187 IHDMI@ 0_0402_5% @ L11 1 1 2 2 4 UMA_DVI_TXD2+ 4 3 9dB 1 0 6dB 1 1 3dB 1 R165 2.2K_0402_5% IHDMI@ IHDMI@ HDMI_TXC- 1 2 R148 2.2K_0402_5% HDMI_EQ1 OUT_D4+ OUT_D4- 16 17 UMA_DVI_TXD1+ UMA_DVI_TXD1- 19 20 UMA_DVI_TXD0+ UMA_DVI_TXD0- 22 23 OUT_D1+ OUT_D1- 1 5 12 18 24 27 31 36 37 43 GND GND GND GND GND GND GND GND GND GND +3VS 48 47 HDMI_TXC+ HDMI_TXC- IN_D3+ IN_D3- 45 44 HDMI_TX2+ HDMI_TX2- IN_D2+ IN_D2- 42 41 HDMI_TX1+ HDMI_TX1- IN_D1+ IN_D1- 39 38 HDMI_TX0+ HDMI_TX0- IN_D4+ IN_D4- OUT_D3+ OUT_D3OUT_D2+ OUT_D2- IHDMI@ C279 1 C280 1 IHDMI@ C281 1 C282 1 IHDMI@ C283 1 C284 1 IHDMI@ C285 1 C286 1 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ R162 2.2K_0402_5% IHDMI@ R164 2.2K_0402_5% @ UMA_HDMI_TXC+ 19 UMA_HDMI_TXC- 19 C 1 +3VS HDMI_EQ0 R166 2.2K_0402_5% @ UMA_HDMI_TX2+ 19 UMA_HDMI_TX2- 19 UMA_HDMI_TX1+ 19 UMA_HDMI_TX1- 19 UMA_HDMI_TX0+ 19 UMA_HDMI_TX0- 19 B THERMAL_PAD 49 ASM1442 QFN_48P_7X7 IHDMI@ HDMI Connector +5VS JHDMI HDMI_HPD +HDMI_5V_OUT HDMI_SDATA HDMI_SCLK HDMI_R_CK- HDMI_R_D1+ HDMI_R_CK+ HDMI_R_D0HDMI_R_D0+ HDMI_R_D1HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+ 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ +5VS 20 21 22 23 @ SUYIN_100042MR019S153ZL HDMI_R_D2+ 4 F2 IHDMI@ PMEG2010AEH_SOD123 IHDMI@ 2 1 2 1 1.1A_6V_MINISMDC110F-2 D53 1 2 C264 +HDMI_5V_OUT @ 0.1U_0402_16V4Z C259 IHDMI@ 0.1U_0402_16V4Z 1 @ R96 2 2 1K_0402_1% HDMI_HPD 2 2 HDMI_R_D1- 3 OCE2012120YZF_0805 1 2 R188 IHDMI@ 0_0402_5% 5 13 14 HDMI_R_D0+ HDMI_R_D2- 1 ANALOG2 UMA_DVI_TXD2+ UMA_DVI_TXD2HDMI_R_CK- A 0 For UMA HDMI level shift display compatibility issue HDMI_CG2 3 OCE2012120YZF_0805 1 2 R183 IHDMI@ 0_0402_5% UMA_DVI_TXD1+ 12dB 1 9 HDMI_R_D0- Equalization 0 2 19 UMA_HDMI_CLK HDMI_R_CK+ * HDMI_EQ0 HDMI_EQ1 EQ0 0 1 2 A R186 100K_0402_5% @ U9 Y 4 HDMI_HPD_R 1 2 R691 0_0402_5% IHDMI@ 1 C265 0.1U_0402_16V4Z IHDMI@ 1 4 34 35 PCH_HDMI_HPD 3 1 2 R182 IHDMI@ 0_0402_5% @ L10 1 1 2 2 4 FUNCTION3 FUNCTION4 1 3 OCE2012120YZF_0805 1 2 R180 IHDMI@ 0_0402_5% UMA_DVI_TXD0+ UMA_DVI_TXD1- 4 32 5 1 2 R175 IHDMI@ 0_0402_5% @ L9 1 1 2 2 4 DDC_EN HDMI_HPD_R 2 @ 1 +3VS R177 10K_0402_5% R168 2 1 4.7K_0402_5% +3VS IHDMI@ P UMA_DVI_TXD0- 30 HPD_SOURCE SDA_SOURCE 3 OCE2012120YZF_0805 1 2 R173 IHDMI@ 0_0402_5% UMA_DVI_TXC+ HPD_SINK 3 B HDMI_SDATA G 1 2 R157 IHDMI@ 0_0402_5% @ L8 1 1 2 2 3 29 EQ1 ANALOG1(REXT) 8 UMA_DVI_TXC+ UMA_DVI_TXC- 4 SDA_SINK +HDMI_5V_OUT 1 IHDMI@ 2 R122 2.2K_0402_5% 1 IHDMI@ 2 R123 2.2K_0402_5% 2 1 FUNCTION1 FUCNTION2 19 UMA_HDMI_DATA 10K_0402_5% @ 4 HDMI_SCLK OE# 2 3 4 6 1 R160 2 3.9K_0402_1% IHDMI@ 7 19,21 PCH_HDMI_HPD R161 +3VS UMA_DVI_TXC- SCL_SINK 28 1 HDMI_CG0 HDMI_CG1 @ 2 1 R159 10K_0402_5% 25 2 1 2 R163 2.2K_0402_5% @ 2 2 R154 2.2K_0402_5% @ 2 R132 2.2K_0402_5% IHDMI@ VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V 1 HDMI_CG0 1 HDMI_CG1 1 HDMI_CG2 C R167 2.2K_0402_5% IHDMI@ 2 R158 2.2K_0402_5% IHDMI@ 2 R131 2.2K_0402_5% @ 2 11 15 21 26 33 40 46 OE# OE* +3VS 1 1 +3VS 2 +3VS +3VS @ A 74AHCT1G125GW _SOT353-5 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title HDMI Connector Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 15 of 48 5 4 CMOS Setting, near DDR Door JCMOS Y3 3 NC OSC 4 2 NC OSC 1 J2 32.768KHZ_12.5PF_Q13MC14610002 2 1U_0402_6.3V4Z 2 C290 U11A PCH_RTCX1 PCH_RTCX2 B13 D13 RTCX1 RTCX2 PCH_RTCRST# C14 RTCRST# PCH_SRTCRST# D17 SRTCRST# SM_INTRUDER# 2 1M_0402_5% PCH_INTVRMEN 2 330K_0402_5% A16 INTRUDER# 1 15P_0402_50V8J FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 D33 B33 C32 A32 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4 / LFRAME# C34 LPC_FRAME# 32,33 1 R285 1 R275 High - Enable Internal VRs PCH_INTVRMEN (must be always pulled high) A14 INTVRMEN AZ_BITCLK A30 HDA_BCLK HDA_SYNC AZ_SYNC D29 HDA_SYNC This signal has a weak internal pull down. H=>On Die PLL is supplied by 1.5V Die PLL is supplied by 1.8V PCH_SPKR 19,29 PCH_SPKR P1 AZ_RST# *L=>On This signal has a weak internal pull down. This signal can't PU Low = Enabled High = Disabled HDA_RST# 29 AZ_SDIN0_HD G30 HDA_SDIN0 26 AZ_SDIN1_MD F30 HDA_SDIN1 E32 HDA_SDIN2 F32 HDA_SDIN3 B29 HDA_SDO HDA_DOCK_EN# H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 AZ_SDOUT * 26 AZ_RST_MD# 29 AZ_RST_HD# R291 1 MDC@ 2 33_0402_5% R292 1 2 33_0402_5% 26 AZ_SDOUT_MD 29 AZ_SDOUT_HD R293 1 MDC@ 2 33_0402_5% R294 1 2 33_0402_5% 2 R273 PCH_JTAG_TDO J2 JTAG_TDO PCH_JTAG_RST# J4 TRST# PCH_SPI_CLK BA2 SPI_CLK PCH_SPI_CS0# AV3 SPI_CS0# AY3 SPI_CS1# 2 2 1 1 PCH_JTAG_TDI 2 1 1PCH_SPI_MOSI 1K_0402_5% PCH_SPI_MISO SPI_MOSI AV1 SPI_MISO SERIRQ 32,33 SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA_PRX_C_DTX_N4 25 SATA_PRX_C_DTX_P4 25 SATA_PTX_DRX_N4 25 SATA_PTX_DRX_P4 25 SATA ODD SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 SATA_PRX_C_DTX_N5 25 SATA_PRX_C_DTX_P5 25 SATA_PTX_DRX_N5 25 SATA_PTX_DRX_P5 25 eSATA SATAICOMPO AF16 SATAICOMPI AF15 SATA_PRX_C_DTX_N1 25 SATA_PRX_C_DTX_P1 25 SATA_PTX_DRX_N1 25 SATA_PTX_DRX_P1 25 1ST HDD Desktop Only C +3VS SATAICOMP 1 R295 2 37.4_0402_1% SATALED# T3 SATA_LED# SATA0GP / GPIO21 Y9 PCH_GPIO21 +1.05VS SATA1GP / GPIO19 V1 PCH_GPIO19 PCH_GPIO19 R306 1 2 10K_0402_5% SATA_LED# R301 2 1 10K_0402_5% PCH_GPIO21 R303 1 2 10K_0402_5% SATA_LED# 34 B for EMI request IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ PCH_SPI_CLK 4MB 1 PCH_JTAG_RST# @ R364 10K_0402_5% R385 @ 10_0402_5% +3VS C293 0.1U_0402_16V4Z 2 @ R537 100_0402_5% AY1 @ R643 20K_0402_5% @ R536 200_0402_5% PCH_JTAG_TDO @ +3VALW 1 1 2 1 JTAG_TDI @ C16 10P_0402_50V8J U13 8 2 PCH_SPI_CS0# VCC 3 W 7 HOLD 1 S PCH_SPI_CLK 6 C PCH_SPI_MOSI 5 D PCH_JTAG_TCK 2 51_0402_5% 1 R156 A @ R363 200_0402_5% @ R535 100_0402_5% K1 AZ_SDOUT +3VALW 2 @ R355 100_0402_5% 2 1 PCH_JTAG_TMS PCH_JTAG_TDI +3VS +3VALW @ R386 200_0402_5% 2 1 +3VALW JTAG_TMS +3VS AZ_RST# High = Enabled Low = Disabled (Default) SPI_MOSI JTAG_TCK K3 AZ_SYNC Internal: Pull down 20k ITPM Enabled M3 PCH_JTAG_TMS 2 10K_0402_5% +RTCBATT VSS 4 1 D13 BAS40-04_SOT23-3 2 +RTCVCC 3 R289 1 MDC@ 2 33_0402_5% R290 1 2 33_0402_5% 26 AZ_SYNC_MD 29 AZ_SYNC_HD B AZ_BITCLK 1 10P_0402_50V8J 1 R286 SERIRQ D 1 2 @ C20 PCH_JTAG_TCK SPI 26 AZ_BITCLK_MD 29 AZ_BITCLK_HD 1 10P_0402_50V8J R287 1 MDC@ 2 33_0402_5% R288 1 2 33_0402_5% 1 2 @ C19 R118 1K_0402_5% @ JTAG 2 32 PW RME_CTRL# For EMI SERIRQ SPKR C30 Flash Descriptor Security Overide A34 F34 AB9 IHDA HDA_SDO LDRQ0# LDRQ1# / GPIO23 SATA Integrated SUS 1.05V VRM Enable RTC +RTCVCC LPC D 32,33 32,33 32,33 32,33 1 2 2 2 1U_0402_6.3V4Z 1 2PCH_SRTCRST# 1 R284 20K_0402_1% 1 C289 C 1 2 1 C288 iME Setting. 2 2 1 R283 10M_0402_5% 2 1 1 2PCH_RTCRST# R282 20K_0402_1% +RTCVCC 3 C287 15P_0402_50V8J 2 1 +CHGRTC 1 C291 0.1U_0402_16V4Z Q 2 2 PCH_SPI_MISO MX25L3205DM2I-12G SO8 A 06/01 change R125 from 4.7K to 51 ohm PCH Pin PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_RST# PCH JTAG Enable ES1 ES2 No Install 200ohm No Install 100ohm 200ohm 200ohm 100ohm 100ohm 200ohm 200ohm 100ohm 100ohm 51ohm 51ohm 20Kohm 20Kohm 10Kohm 10Kohm RefDes R358 R535 R355 R354 R536 R537 R156 R643 R353 5 PCH JTAG Disable (Default) ES1 ES2 No Install No Install No Install No Install No Install No Install No Install No Install No Install 20Kohm No Install 10Kohm 51ohm 51ohm No Install No Install No Install No Install Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title PCH-SPI/SATA/LPC/RTC/HDA Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 16 of 48 4 3 2 1 2 R229 2 R230 +3VALW +3VS 1 2.2K_0402_5% 1 2.2K_0402_5% Q3B PCH_SMBDATA R231 R232 5 5 PM_SMBDATA 11,12,13,27 2N7002KDW _SOT363-6 Q3A PCH_SMBCLK 4 2 3 4.7K_0402_5% 4.7K_0402_5% 6 1 PM_SMBCLK 11,12,13,27 2N7002KDW _SOT363-6 U11B PERN2 PERP2 PETN2 PETP2 AU30 AT30 AU32 AV32 PERN3 PERP3 PETN3 PETP3 C NC LAN 28 28 CLK_LAN# CLK_LAN CLKREQ_LAN# 28 CLKREQ_LAN# +3VS 1 10K_0402_5% 2 R246 PCH_GPIO20 1 10K_0402_5% 2 R248 CLKREQ_W LAN# WLAN 27 27 CLKREQ_W LAN# 27 CLKREQ_W LAN# PERN5 PERP5 PETN5 PETP5 BA34 AW34 BC34 BD34 PERN6 PERP6 PETN6 PETP6 AT34 AU34 AU36 AV36 PERN7 PERP7 PETN7 PETP7 BG34 BJ34 BG36 BJ36 PERN8 PERP8 PETN8 PETP8 AK48 AK47 CLKOUT_PCIE0N CLKOUT_PCIE0P U4 PCH_GPIO20 +3VALW 2 R244 CLKREQ_LAN# 1 10K_0402_5% 2 R245 PCH_GPIO25 1 10K_0402_5% 2 R249 PCH_GPIO26 1 10K_0402_5% 2 R250 PCH_GPIO44 1 10K_0402_5% 2 R251 PCH_GPIO56 N4 AH42 AH41 PCH_GPIO25 A8 AM51 AM53 PCH_GPIO26 M9 AJ50 AJ52 PCH_GPIO44 H6 AK53 AK51 PCH_GPIO56 P13 PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P PCH_SMBDATA SML0CLK C6 PCH_SMLCLK0 SML0DATA G8 PCH_SMLDATA0 SML1ALERT# / GPIO74 M14 PCH_GPIO74 SML1CLK / GPIO58 E10 PCH_SMLCLK1 SML1DATA / GPIO75 G12 CL_CLK1 T13 CL_DATA1 T11 CL_RST1# T9 PEG_A_CLKRQ# / GPIO47 H1 3 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 CLKREQ_PEG# 1 R260 2 10K_0402_5% EC_SMB_CK2 32 +3VALW 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 2 2 2 1 1 1 1 1 R237 R238 R239 R240 R241 +3VALW CLK_PEG# 5 CLK_PEG 5 PCH_CLK_DMI# 13 PCH_CLK_DMI 13 CLKIN_BCLK_N CLKIN_BCLK_P AP3 AP1 CLK_BCLK# 13 CLK_BCLK 13 CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_DOT# 13 CLK_DOT 13 AH13 AH12 CLK_SATA# 13 CLK_SATA 13 P41 CLK_14M_PCH 13 CLKIN_PCILOOPBACK 1 PCH_SMLCLK0 PCH_SMLDATA0 PCH_GPIO60 PCH_GPIO74 EC_LID_OUT# AW24 BA24 REFCLK14IN EC_SMB_DA2 32 AD43 AD45 AT1 AT3 CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P 6 4 2N7002KDW _SOT363-6 PCH_SMLDATA1 FROM CLK GEN FOR: 133/100/96/14.318 MHZ B R247 2 J42 XTAL25_IN XTAL25_OUT AH51 AH53 XCLK_RCOMP AF38 CLKOUTFLEX0 / GPIO64 T45 CLKOUTFLEX1 / GPIO65 P43 CLKOUTFLEX2 / GPIO66 T42 CLKOUTFLEX3 / GPIO67 N50 2 PCH_X2 1 27P_0402_50V8J 2 2 C277 PCH_X1 PCH_X2 1 25MHZ_20PF_7A25000012 1 CLK_PCILOOP 20 XCLK_RCOMP 1 2 R252 90.9_0402_1% 1M_0402_5% 1 Y2 PCH_X1 C278 27P_0402_50V8J +1.05VS Note: Stuff 0 ohm if 25MHz crystal un-stuff C277 @ 0_0402_5% for EMI request @ IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ A Q4B PCH_SMLDATA1 C CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKIN_DMI_N CLKIN_DMI_P +3VS 1 2.2K_0402_5% 1 2.2K_0402_5% 2N7002KDW _SOT363-6 AN4 AN2 CLKOUT_PCIE5N CLKOUT_PCIE5P 2 R233 2 R234 +3VALW PCH_SMLCLK1 CLKOUT_DMI_N CLKOUT_DMI_P PCIECLKRQ3# / GPIO25 PEG_B_CLKRQ# / GPIO56 C8 EC_LID_OUT# 32 Q4A CLKOUT_PCIE3N CLKOUT_PCIE3P CLKOUT_PEG_B_N CLKOUT_PEG_B_P PCH_SMBCLK PCH_GPIO60 CLKOUT_PEG_A_N CLKOUT_PEG_A_P PCIECLKRQ2# / GPIO20 PCIECLKRQ5# / GPIO44 H14 J14 SML0ALERT# / GPIO60 SMBus BF33 BH33 BG32 BJ32 AM47 AM48 B 1 10K_0402_5% PERN4 PERP4 PETN4 PETP4 AM43 AM45 CLK_W LAN# CLK_W LAN SMBDATA BA32 BB32 BD32 BE32 P9 SMBCLK EC_LID_OUT# 5 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K AW30 BA30 PCIE_PTX_W LANRX_N2 BC30 PCIE_PTX_W LANRX_P2 BD30 SMBALERT# / GPIO11 B9 2 PERN1 PERP1 PETN1 PETP1 Link C274 2 C275 2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K Controller PCIE_PRX_W LANTX_N2 PCIE_PRX_W LANTX_P2 PCIE_PTX_C_W LANRX_N2 PCIE_PTX_C_W LANRX_P2 C276 2 C273 2 PEG 27 27 27 27 PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_C_LANRX_N1 PCIE_PTX_C_LANRX_P1 PCI-E* For WLAN 28 28 28 28 D From CLK BUFFER For LAN BG30 BJ30 PCIE_PTX_LANRX_N1 BF29 PCIE_PTX_LANRX_P1 BH29 Clock Flex D CLK_PCILOOP @ 1 R125 CLK_14M_PCH 2 10_0402_5% @ 1 2 R70 100_0402_5% 1 2 C216 10P_0402_50V8J @ 2 1 A C206 100P_0402_50V8J Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CLK/PCIE/SMBUS Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 17 of 48 5 4 3 2 1 D D PCH_SUSPW RDN 2 10K_0402_5% PCH_LOW _BAT# 2 10K_0402_5% IBEX_RI# 2 10K_0402_5% BC24 BJ22 AW20 BJ20 DMI0RXN DMI1RXN DMI2RXN DMI3RXN 6 6 6 6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BD24 BG22 BA20 BG20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP 6 6 6 6 DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 BE22 BF21 BD20 BE18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN 6 6 6 6 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP 1 R311 +1.05VS PM_PW ROK 1 10K_0402_5% PW ROK 1 10K_0402_5% LAN_RST# 1 10K_0402_5% 2 R329 2 R322 2 R323 C BH25 BF25 Close to PCH @ 2 0_0402_5% DMI_ZCOMP 5 XDP_DBRESET# 5 32,43 XDP_DBRESET# T6 VGATE M6 4 PW ROK B17 O SN74AHC1G08DCKR_SC70-5 1 R321 LAN_RST# 2 0_0402_5% K5 A10 D9 5 DRAMPW ROK PCH_RSMRST# PWROK C16 MEPWROK LAN_RST# DRAMPWROK RSMRST# B 32 PCH_SUSPW RDN 32 PCH_SUSPW RDN 1 R324 32,34,36 2 330K_0402_5% D26 1 2 ACIN M1 SUS_PWR_DN_ACK / GPIO30 P5 PWRBTN# PCH_ACIN P7 ACPRESENT / GPIO31 PCH_LOW _BAT# A6 BATLOW# / GPIO72 PBTN_OUT# +3VALW FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 6 6 6 6 6 6 6 6 FDI_INT BJ14 FDI_INT FDI_FSYNC0 BF13 FDI_FSYNC0 FDI_FSYNC1 BH13 FDI_FSYNC1 6 FDI_LSYNC0 BJ12 FDI_LSYNC0 6 FDI_LSYNC1 BG14 FDI_LSYNC1 6 6 6 C EC_SW I# CLKRUN# / GPIO32 Y1 PM_CLKRUN# SUS_STAT# / GPIO61 P8 SUS_STAT# PADT38 PADT38 SUSCLK / GPIO62 F3 SUS_CLK PADT39 PADT39 SLP_S5# / GPIO63 E4 PM_SLP_S5# 32 SLP_S4# H7 PM_SLP_S4# 32 SLP_S3# P12 PM_SLP_S3# 32 SLP_M# K8 TP23 N2 WAKE# SYS_PWROK IN2 3 2 6 6 6 6 6 6 6 6 J12 SYS_RESET# P VGATE FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 1 R256 +3VS 0.1U_0402_16V4Z 1 2 C272 U12 1 IN1 PM_PW ROK FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 DMI_IRCOMP G 32 DMI_COMP 2 49.9_0402_1% System Power Management 1 R316 1 R318 1 R320 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI +3VALW 6 6 6 6 DMI U11C EC_SW I# EC_SW I# 28 2 R319 1 8.2K_0402_5% 1 R313 2 10K_0402_5% +3VALW +3VS B PMSYNCH BJ10 PMSYNCH 5 CH751H-40PT_SOD323-2 IBEX_RI# F14 RI# SLP_LAN# / GPIO29 F6 IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ +3VALW 1 R690 2 1K_0402_5% 0_0402_5% @1 2 R325 C Q26 1 3 E 32 EC_RSMRST# 2 MMBT3906_SOT23-3 RSMRST# circuit 5 4 2 A D15B BAV99DW -7_SOT363 1 2 R328 2.2K_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 3 6 2 1 R327 4.7K_0402_5% D15A BAV99DW -7_SOT363 1 2 B +3VALW A PCH_RSMRST# 1 R326 10K_0402_5% 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH-DMI/FDI/PWM Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 18 of 48 5 4 3 2 1 U11D 2 R59 LCD_EDID_CLK 1 2.2K_0402_5% 2 R60 LCD_EDID_DATA 1 2.2K_0402_5% +3VS 1 R63 UMA_CRT_CLK 2 2.2K_0402_5% 1 R61 UMA_CRT_DATA 2 2.2K_0402_5% 1 R56 1 R57 1 R58 2 150_0402_1% 2 150_0402_1% 2 150_0402_1% UMA_CRT_B UMA_CRT_G UMA_CRT_R 1 R55 LCTL_CLK AB46 2 V48 2 10K_0402_5% LCTL_DATA 10K_0402_5% LVDS_IBG AP39 2 2.37K_0402_1% AP41 T15 PAD AT43 AT42 LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK 13 LCD_TXOUT013 LCD_TXOUT113 LCD_TXOUT2- BB47 BA52 AY48 AV47 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 13 LCD_TXOUT0+ 13 LCD_TXOUT1+ 13 LCD_TXOUT2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 13 LCD_TZCLK13 LCD_TZCLK+ AP48 AP47 LVDSB_CLK# LVDSB_CLK 13 LCD_TZOUT013 LCD_TZOUT113 LCD_TZOUT2- AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 13 LCD_TZOUT0+ 13 LCD_TZOUT1+ 13 LCD_TZOUT2+ AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED V51 V53 14 UMA_CRT_CLK 14 UMA_CRT_DATA Y53 Y51 14 UMA_CRT_HSYNC 14 UMA_CRT_VSYNC 2 R266 1CRT_IREF AD48 AB51 1K_0402_1% PCH Strap Pin BF45 BH45 SDVO_CTRLCLK SDVO_CTRLDATA AV53 AV51 UMA_CRT_B UMA_CRT_G UMA_CRT_R SDVO_INTN SDVO_INTP L_CTRL_CLK L_CTRL_DATA 13 LCD_TXCLK13 LCD_TXCLK+ 14 14 14 SDVO_STALLN SDVO_STALLP D For INTEL issue (pending interrupts from the PCH for unused HDMI ports) DDPB_AUXN DDPB_AUXP DDPB_HPD BG44 BJ44 AU38 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 R68 2 +3VS R120 2.2K_0402_5% IHDMI@ DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 2 R189 PCH_SPKR @ 1 2 R269 1K_0402_5% @ 1 R270 1K_0402_5% 2 @ 1 R271 Check list: 4.7k PD 2 R272 @ 1 1K_0402_5% PCH_HDMI_HPD 15,21 UMA_HDMI_TX2UMA_HDMI_TX2+ UMA_HDMI_TX1UMA_HDMI_TX1+ UMA_HDMI_TX0UMA_HDMI_TX0+ UMA_HDMI_TXCUMA_HDMI_TXC+ 15 15 15 15 15 15 15 15 HDMI C U50 U52 For INTEL issue (pending interrupts from the PCH for unused HDMI ports) DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 CRT_HSYNC CRT_VSYNC 2 R77 1 100K_0402_5% Internal: Pull down 20k During Reset: Low Initial: Low +1.8VS_PCH_NAND NO REBOOT Strap PCH_SPKR Check list: 8.2k PU Low= Disable High= Enable PCH_SPKR 16,29 Internal: Pull up 20k During Reset: High Initial: High 1K_0402_5% 2 1 100K_0402_5% IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ Internal: Pull down 20k During Reset: HZ Initial: Low Check list: 10k PU R121 2.2K_0402_5% IHDMI@ UMA_HDMI_CLK 15 UMA_HDMI_DATA 15 +3VS B 100K_0402_5% 1 For INTEL issue (pending interrupts from the PCH for unused HDMI ports) DDPD_CTRLCLK DDPD_CTRLDATA CRT_DDC_CLK CRT_DDC_DATA DAC_IREF CRT_IRTN T51 T53 1 +3VS D C 1 1 R53 R54 L_DDC_CLK L_DDC_DATA 1 +3VS L_BKLTCTL BJ46 BG46 BJ48 BG48 2 AB48 Y45 SDVO_TVCLKINN SDVO_TVCLKINP 2 PCH_PW M 13 LCD_EDID_CLK 13 LCD_EDID_DATA L_BKLTEN L_VDD_EN Digital Display Interface 13 Y48 LVDS T48 T47 32 UMA_ENBKL 13 UMA_ENVDD UMA_ENBKL 2 100K_0402_5% CRT 1 R124 PCI_GNT#0 PCI_GNT#1 PCI_GNT#0 20 PCI_GNT#1 20 Internal: Pull up 20k During Reset: High Initial: High PCI_GNT#3 PCI_GNT#3 20 Internal: Pull up 20k During Reset: High Initial: High Boot BIOS Strap PCI_GNT#1 PCI_GNT#0 0 0 1 1 0 1 0 1 Danbury Technology Enabled NV_ALE 2 R267 @ 1 1K_0402_5% NV_ALE NV_ALE 20 2 R268 @ NV_CLE 1 1K_0402_5% NV_CLE 20 Boot BIOS Loaction DMI Termination Voltage Internal: Pull down 20k During Reset: Low Initial: Low LPC (Default) Reserved (NAND) PCI SPI B High = Enabled Low = Disabled (Default) NV_CLE Low= Set to Vss (Default) High= Set to Vcc A16 Swap Override Strap PCI_GNT#3 Low= A16 swap override Enable High= A16 swap override Disable A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH-CRT/LVDS/HDMI/STRAP Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 19 of 48 5 4 3 2 1 U11E 8.2K_0804_8P4R_5% C/BE0# C/BE1# C/BE2# C/BE3# RP3 1 2 3 4 PCI_STOP# PCI_PIRQE# PCI_PIRQC# PCI_PIRQG# 8 7 6 5 8.2K_0804_8P4R_5% GNT2#: Not pull low, internal pull up 20K 19 19 PCI_GNT#0 PCI_GNT#1 19 PCI_GNT#3 RP4 1 2 3 4 8 7 6 5 T37 PAD PCI_REQ#3 PCI_PIRQF# PCI_PIRQB# PCI_REQ#0 G38 H51 B37 A44 PIRQA# PIRQB# PIRQC# PIRQD# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 F51 A46 B45 M53 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 F48 K45 F36 H53 GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 B41 K53 A36 A48 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 8.2K_0804_8P4R_5% +3VS TP_PCI_RST# K6 1 2 3 4 8 7 6 5 8.2K_0804_8P4R_5% PCI_SERR# PCI_DEVSEL# PCI_PLOCK# PCI_PERR# 1 R277 E44 E50 SERR# PERR# PCI_IRDY# PCI_DEVSEL# PCI_FRAME# A42 H44 F46 C46 IRDY# PAR DEVSEL# FRAME# PCI_PLOCK# D49 PLOCK# PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# 2 PLT_RST# 100K_0402_5% M7 PME# D5 27,28,32,33 PLT_RST# 33 CLK_PCI_DDR 32 CLK_PCI_EC 17 CLK_PCILOOP PCIRST# PCI_SERR# PCI_PERR# RP5 2 1 CLK_SIO 22_0402_5% R280 2 1 CLK_EC 22_0402_5% R281 2 1 CLK_PCH 22_0402_5% R279 N52 P53 P46 P51 P48 BD3 AY6 @ 1 R253 NV_ALE 19 NV_CLE 19 AU2 NV_RB# AV7 NV_WR#0_RE# NV_WR#1_RE# AY8 AY5 NV_WE#_CK0 NV_WE#_CK1 PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 U8 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 USBRBIAS# B25 USBRBIAS D25 N16 J16 F16 L16 E14 G16 F12 T15 USB20_N0 USB20_P0 USB20_N1 USB20_P1 30 30 30 30 USB-RIGHT1 USB20_N3 25 USB20_P3 25 eSATA-USB USB20_N5 26 USB20_P5 26 BT 31 31 13 13 2 SN74AHC1G08DCKR_SC70-5 R129 100K_0402_5% @ USB20_N13 27 USB20_P13 27 USBBIAS 2 R278 1 22.6_0402_1% USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 EXP_CPPE# Card reader(3 in 1) Int. Camera WLAN Within 500 mils +3VALW USB_OC#0 30,32 USB_OC#1 25,32 USB_OC#0 2 10K_0402_5% USB_OC#1 2 10K_0402_5% USB_OC#2 2 10K_0402_5% USB_OC#3 2 10K_0402_5% USB_OC#4 2 10K_0402_5% USB_OC#5 2 10K_0402_5% USB_OC#6 2 10K_0402_5% EXP_CPPE# 2 10K_0402_5% Deciphered Date 1 R300 1 R302 1 R304 1 R305 1 R307 1 R297 1 R298 1 R299 A Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 O B USB20_N10 USB20_P10 USB20_N11 USB20_P11 Compal Secret Data 2009/01/23 Issued Date C PLT_RST# 1 USB-RIGHT2 A Security Classification IN1 IN2 IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ 4 4 5 BUF_PLT_RST# AV11 BF5 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 @ 1 2 R276 32.4_0402_1% 5 NV_RCOMP Change to 47 ohm? 5 2 0_0402_5% +3VS PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# +3VS B NVRAM J50 G42 H47 G34 NV_ALE NV_CLE P PCI_PIRQH# PCI_TRDY# PCI_FRAME# PCI_PIRQA# 8 7 6 5 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 G RP2 1 2 3 4 C NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 D 3 8.2K_0804_8P4R_5% NV_DQS0 NV_DQS1 AV9 BG8 1 PCI_REQ#1 PCI_REQ#2 PCI_PIRQD# PCI_IRDY# 8 7 6 5 AY9 BD1 AP15 BD8 2 RP1 1 2 3 4 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 USB +3VS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI D H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 2 Title PCH USB/PCI/NAND Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 20 of 48 5 4 3 2 1 U11F 15,19 PCH_HDMI_HPD GPIO8 Not pull down C38 TACH1 / GPIO1 PCH_GPIO6 D37 TACH2 / GPIO6 EC_SCI# J32 TACH3 / GPIO7 32 EC_SMI# EC_SMI# F10 GPIO8 MISC LAN_PHY_PWR_CTRL / GPIO12 A20GATE PCH_GPIO15 T7 GPIO15 Internal: Pull down 20k During Reset: Low Initial: Low PCH_GPIO16 AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# 5 PCH_GPIO17 F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5 +3VS +3VS H NWQAA 16" H L *NALAA 17.3" H H 1 1 R265 10K_0402_5% 2 L L 2 L PROJECT_ID0 PROJECT_ID1 B THM_ALT# GPIO28 M11 STP_PCI# / GPIO34 +3VS @ 1 2 PCH_HDMI_HPD 10K_0402_5% R213 1 2 PCH_GPIO1 10K_0402_5% R214 BT_DET# 1 2 8.2K_0402_5% R215 1 2 PCH_GPIO6 10K_0402_5% R218 1 2 PCH_GPIO17 10K_0402_5% R220 1 2 PCH_GPIO16 10K_0402_5% R221 1 2 PCH_GPIO38 10K_0402_5% R255 1 2 THM_ALT# 10K_0402_5% R259 1 2 PCH_GPIO48 10K_0402_5% R257 1 2 PCH_GPIO39 10K_0402_5% R216 EC_SCI# 1 2 10K_0402_5% R224 PROCPWRGD BE10 THRMTRIP# BD10 SATA2GP / GPIO36 TP1 BA22 PROJECT_ID1 AB13 RST_GATE SATA3GP / GPIO37 TP2 AW22 V3 SLOAD / GPIO38 TP3 BB22 P3 SDATAOUT0 / GPIO39 TP4 AY45 H3 PCIECLKRQ6# / GPIO45 TP5 AY46 F1 PCIECLKRQ7# / GPIO46 TP6 AV43 AB6 SDATAOUT1 / GPIO48 TP7 AV45 THM_ALT# AA4 SATA5GP / GPIO49 TP8 AF13 GPIO57 TP9 M18 TP10 N18 TP11 AJ24 TP12 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 F8 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 TP19 AA23 NC_1 AB45 NC_2 AB38 NC_3 AB42 NC_4 AB41 NC_5 T39 INIT3_3V# TP24 IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ 5 KB_RST# 32 H_PW RGOOD 5 THRMTRIP_PCH# 1 R212 2 56_0402_1% H_THERMTRIP# 5 1 R210 2 +VTT 56_0402_1% C PCH_GPIO48 PCH_GPIO57 PECI KB_RST# T1 SATACLKREQ# / GPIO35 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 PROJECT_ID R264 10K_0402_5% 32 GPIO27 V13 GATEA20 32 BG10 AB7 PCH_GPIO39 GPIO57: OPTIMUS_EN# : Pull-High for non-support OPTIMUS AB12 RCIN# GATEA20 U2 PROJECT_ID0 LVDS_SEL : GND for Dual-Channel Panel RST_GATE GPIO24 V6 BT_RST# PCH_GPIO38 5 H10 PECI CPU PCH_GPIO27 1 1K_0402_5% PCH_GPIO28 SCLOCK / GPIO22 GPIO Y7 RSVD @ BT_DET# NCTF BT_DET# 2 R274 High = Enabled (Default) Low = Disabled C NBQAA 14" D K9 26 NBQAA 11.6/13.3" AF48 AF47 PCH_GPIO12 GPIO39: CIR_EN# : Pull-High for non-support CIR ID1 AH45 AH46 GPIO15 a Strong pull up may be needed for GPIO Functionality 26,27 BT_PW R# ID0 CLKOUT_PCIE6N CLKOUT_PCIE6P CLKOUT_PCIE7N CLKOUT_PCIE7P On-Die PLL VR Name BMBUSY# / GPIO0 PCH_GPIO1 EC_SCI# 26 PCH_GPIO27 Y3 32 D Internal: Pull up 20k During Reset: High Initial: High PCH_HDMI_HPD B Not pull low internal pull up P6 C10 Internal: Pull up 20k During Reset: High Initial: High +3VALW A A EC_SMI# 1 2 R225 10K_0402_5% 1 2 PCH_GPIO57 R226 10K_0402_5% 1 2 PCH_GPIO15 R227 1K_0402_5% 1 2 PCH_GPIO28 R242 10K_0402_5% 1 2 RST_GATE R223 10K_0402_5% 1 2 PCH_GPIO12 10K_0402_5% R219 5 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title PCH CPU/GPIO Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 21 of 48 4 3 +1.05VS D 1 2 1 C294 1U_0402_6.3V4Z 2 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] +3VS 2 C310 B 1 0.1U_0402_16V4Z +PCH_VRM +1.05VS VCCADAC[2] AE52 VSSA_DAC[1] AF53 VSSA_DAC[2] AF51 > 1mA AN30 AN31 VCCAPLLEXP AH38 AH39 VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4] AP43 AP45 AT46 AT45 VCC3_3[1] AT22 VCCVRM[1] BJ18 VCCFDIPLL AM23 VCCIO[1] LVDS 1 HVCMOS 1 C297 0.1U_0402_16V4Z 2 2 +3VS_VCCADAC_R 1_0603_1% L57 1 2 BLM18PG181SN1D_2P C298 10U_0805_10V4Z D +3VS +1.8VS +1.8VS_VCCTX_LVDS 1 1 C300 0.01U_0402_25V7K +3VS 375mA VCC3_3[2] AB34 VCC3_3[3] AB35 VCC3_3[4] AD35 2 2 1 R341 2 0_0603_5% C299 0.01U_0402_25V7K 2 0.1U_0402_16V4Z C303 1 close to AB34 C +PCH_VRM 3062mA DMI 196mA 61mA 375mA 37mA VCCVRM[2] AT24 VCCDMI[1] AT16 VCCDMI[2] AU16 +VTT +PCH_VCCDMI 1 2 156mA VCCIO[54] VCCIO[55] AN35 2 2 C296 0.01U_0402_25V7K 1 L12 close to AE50 VCCALVDS PCI E* VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] 40mA +3VS_VCCADAC 1 VSSA_LVDS NAND / SPI +1.05VS 2 10U_0805_10V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 VCCIO[24] FDI BJ24 1 C304 1 C305 1 C306 1 C307 1 C308 AE50 69mA 59mA AK24 C VCCADAC[1] 1432mA +1.05VS 1 +3VS CRT C295 10U_0805_10V4Z 2 POWER U11G AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 VCC CORE 5 VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 1 R335 +PCH_VRM 2 0_0603_5% C309 1U_0402_6.3V4Z +1.8VS 2 R336 1 0_0402_5% close to AT16 +1.8VS_PCH_NAND +1.8VS 1 R338 2 2 0_0603_5% C311 0.1U_0402_16V4Z 1 close to Ak13 B +3VS 85mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 2 C313 close to AM8 IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ 0.1U_0402_16V4Z 1 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH POWER-1 Size B Date: Document Number Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 1 22 of 48 3 POWER C328 220U_6.3V_M C323 22U_0805_6.3V6M @2 2 C331 220U_6.3V_M C329 1U_0402_6.3V4Z R347 0_0603_5% @ +1.05VS_PCHDPLL_A 2 2 1 2 C332 1U_0402_6.3V4Z 2 VCCME[5] +1.05VS 1 C334 1U_0402_6.3V4Z 163mA 1849mA AF42 VCCME[6] V39 VCCME[7] V41 VCCME[8] V42 VCCME[9] Y39 VCCME[10] Y41 VCCME[11] Y42 VCCME[12] V9 DCPRTC 196mA VCCVRM[3] 68mA BB51 BB53 VCCADPLLA[1] VCCADPLLA[2] 69mA +1.05VS_PCHDPLL_B BD51 BD53 VCCADPLLB[1] VCCADPLLB[2] 1U_0402_6.3V4Z 1 1 AH23 AJ35 AH35 VCCIO[21] VCCIO[22] VCCIO[23] AF34 VCCIO[2] 1 + AF41 AU24 +PCH_VRM 1 2 L18 1 2 10UH_LB2012T100MR_20% C324 1U_0402_6.3V4Z +VCCRTCEXT 2 0.1U_0402_16V4Z 1 + VCCME[4] 1 +1.05VS AF43 1 1 C327 L17 1 2 10UH_LB2012T100MR_20% VCCME[3] C335 2 C336 2 2 1U_0402_6.3V4Z AH34 VCCIO[3] AF32 VCCIO[4] 1 C338 +VCCSST 2 0.1U_0402_16V4Z V12 DCPSST 1 C341 2 +V1.1A_INT_VCCSUS Y22 0.1U_0402_16V4Z DCPSUS VCCSUS3_3[28] U23 VCCIO[56] V23 +1.05VS V5REF_SUS F24 +PCH_VCC5REFSUS > 1mA > 1mA 375mA V5REF K49 VCC3_3[8] J38 VCC3_3[9] L38 VCC3_3[10] M36 VCC3_3[11] N36 VCC3_3[12] P36 VCC3_3[13] U35 VCC3_3[14] AD13 3062mA 31mA VCCSATAPLL[1] VCCSATAPLL[2] 0.1U_0402_16V4Z 2 2 1 1 C325 0.1U_0402_16V4Z +3VALW +5VALW D16 R344 100_0402_1% +3VS 2 C326 1 1U_0402_6.3V4Z 2 0.1U_0402_16V4Z VCCSUS3_3[29] U19 VCCSUS3_3[30] U20 VCCSUS3_3[31] U22 VCCSUS3_3[32] +3VS 1 C344 2 0.1U_0402_16V4Z 375mA V15 VCC3_3[5] V16 VCC3_3[6] Y16 VCC3_3[7] VCCIO[9] 196mA VCCVRM[4] AT20 VCCIO[10] AH19 VCCIO[11] AD20 VCCIO[12] AF22 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 3062mA +VTT 1 2 C347 2 0.1U_0402_16V4Z 1 C3461 0.1U_0402_16V4Z 1 C351 V_CPU_IO[1] AU18 V_CPU_IO[2] +RTCVCC 2 0.1U_0402_16V4Z A12 VCCRTC A 1 C348 1 C349 1849mA 2 1U_0402_6.3V4Z 2mA HDA C345 2 4.7U_0603_6.3V6K > 1mA AT18 CPU +VTT_V_CPU_IO 2 0_0603_5% RTC 1 R343 6mA IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ VCCME[13] VCCME[14] VCCME[15] VCCME[16] VCCSUSHDA 1 +3VS 2 2009/01/23 Issued Date +3VS 2 C337 1 0.1U_0402_16V4Z For HDA power rail to +1.5V B U54 +PCH_VRM +3VALW 1 C342 1U_0402_6.3V4Z C2 1U_0603_10V6K @ 2 4 3 APL5508-25DC-TRL_SOT89-3 IN 3 OUT @ +1.5VALW 1 GND 1 2 C18 4.7U_0603_6.3V6K @ +1.05VS AA34 +PCH_VCCME1 Y34 +PCH_VCCME2 Y35 +PCH_VCCME3 AA35 +PCH_VCCME4 L30 2 +1.05VS +VCCSUSHDA 1 R351 R352 R353 R354 1 1 1 1 2 2 2 2 R356 1 R357 1 @ 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 0_0402_5% +3VALW 2 0_0402_5% +1.5VALW C350 1U_0402_6.3V4Z Deciphered Date VCCSUSHDA can be either 1.5V or 3.3V A For HDA power rail to +3.3V(default) / +1.5V Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1U_0402_6.3V4Z C333 0.1U_0402_16V4Z Compal Secret Data Security Classification C330 1 2 2 0.1U_0402_16V4Z C AK3 AK1 AH22 SATA 1 C343 163mA P18 PCI/GPIO/LPC +3VALW R346 100_0402_1% +PCH_VCC5REF +1.05VS B D17 CH751H-40PT_SOD323-2 +PCH_VCC5REF 2 +5VS 1 1 C AD41 C321 2 2 VCCME[2] D +3VALW 2 C447 22U_0805_6.3V6M VCCME[1] AD39 1U_0402_6.3V4Z 1 Near V39 1 AD38 2 1 2 C318 1U_0402_6.3V4Z 320mA DCPSUSBYP 1 C391 C322 22U_0805_6.3V6M 22U_0805_6.3V6M 2 @2 If two VccME rails can be combined, only total 2 x 22 ȝF and 2 x 1 ȝF caps are necessary VCCLAN[2] Y20 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 C316 2 1 AF24 VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] 1 1 1 VCCLAN[1] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] 3062mA 2 +1.05VS AF23 52mA 1 +1.05VS V24 V26 Y24 Y26 2 Near AD38 VCCACLK[2] USB 1 +TP_PCH_VCCDSW 0.1U_0402_16V4Z 2 C320 VCCACLK[1] AP53 PCI/GPIO/LPC VccLAN may be grounded if Intel LAN is disabled AP51 1 U11J D 2 CH751H-40PT_SOD323-2 4 Clock and Miscellaneous 5 2 Title PCH POWER-2 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 23 of 48 5 4 3 2 1 U11I AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 D C B A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 U11H AB16 VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] D C B IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ A Compal Electronics, Inc. Compal Secret Data Security Classification IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 4 3 2 Title PCH-GND Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 24 of 48 5 4 3 SATA HDD Conn. +5VS SATA ODD Conn JODDB 1 C356 10U_0805_10V4Z 2 1 C357 0.1U_0402_16V4Z 2 1 C358 0.1U_0402_16V4Z 2 GND GND 12 11 10 9 8 7 6 5 4 3 2 1 C359 0.1U_0402_16V4Z 2 D SSD HDD need 400mA for 3V(PHISON) +3VS +3VS rail reserve for SSD 1 2 1 Place closely JHDD SATA CONN. 1.2A 1 2 1 C363 10U_0805_10V4Z @ 2 C364 0.1U_0402_16V4Z @ 1 1 C365 0.1U_0402_16V4Z @ 2 C366 0.1U_0402_16V4Z @ +5VS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.1A D SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 C375 1 C376 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_P4 16 SATA_PRX_C_DTX_N4 16 SATA_PTX_C_DRX_N4 SATA_PTX_C_DRX_P4 C377 1 C378 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_N4 16 SATA_PTX_DRX_P4 16 ACES_88058-120N @ 2 JHDD GND A+ AGND BB+ GND C V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 1 2 3 4 5 6 7 SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 C369 1 C367 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_P1 16 SATA_PTX_DRX_N1 16 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C368 1 C370 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N1 16 SATA_PRX_C_DTX_P1 16 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS C +5VS @ SUYIN_127072FR022G210ZR_RV +USB_VCCB eSATA/USB W=60mils 1000P_0402_50V7K 220U_6.3V_M_R15 B 1 Reserve for EMI request @ R72 1 C379 0_0402_5% 2 1 1 B + C380 2 C381 2 2 L52 0.1U_0402_16V4Z @ D18 2 20 USB20_N3 1 1 2 2 USB20_N3_R 20 USB20_P3 4 4 3 3 USB20_P3_R 1 3 eSATA/USB Conn AZC199-02S.R7G_SOT23-3 JESATA W CM-2012-900T_0805 @ R85 1 0_0402_5% 2 W=60mils 2A +5VALW 1 2 3 4 USB20_N3_R USB20_P3_R 16 SATA_PTX_DRX_P5 16 SATA_PTX_DRX_N5 C385 1 C386 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_N5 16 SATA_PRX_C_DTX_N5 16 SATA_PRX_C_DTX_P5 C387 1 C388 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_DTX_N5 SATA_PRX_DTX_P5 +USB_VCCB U15 A 30,32 USB_EN# USB_EN# 1 2 3 4 GND VOUT VIN VOUT VIN VOUT EN FLG 8 7 6 5 RT9715BGS_SO8 USB_OC#1 20,32 1 2 C383 4.7U_0805_10V4Z @ VBUS DD+ GND USB 5 6 7 8 9 10 11 GND A+ ESATA AGND BB+ GND 12 13 14 15 GND GND GND GND A @ TYCO_1759576-1 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title SATA-HDD/ODD/ESATA Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 25 of 48 5 4 3 +3VS 1 MDC 1.5 Conn. 2 BlueTooth Interface 2 +3VS D 2 3 1 2 Q28 BT@ AO3413_SOT23 @ R392 0_0603_5% +3VALW MDC@ +1.5VALW @ 1 1 1 2 R362 47K_0402_5% 1 BT@ C390 0.01U_0402_25V7K BT@ 2 21,27 BT_PW R# +MDC_VCC G 1 2 D C396 0.1U_0402_16V7K BT@ S R361 100K_0402_5% 2 R44 2 R45 1 0_0402_5% 1 0_0402_5% 1 For HDA power rail to +3.3V(default) / +1.5V 1 C488 C487 D 4.7U_0805_10V4Z 2 1 3 5 7 9 11 16 AZ_SDOUT_MD Bluetooth Connector BT@ 2 C395 4.7U_0805_10V4Z 2 MDC@ JMDC +BT_VCC BT@ 1 +BT_VCC (MAX=200mA) 1 1 C392 C393 0.1U_0402_16V4Z 1000P_0402_50V7K 2 MDC@ 2 MDC@ 16 AZ_SYNC_MD 16 AZ_SDIN1_MD 16 AZ_RST_MD# 0.1U_0402_16V4Z 2 R369 1 AZ_SDIN1_MD_R 33_0402_5% MDC@ GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK 2 4 6 8 10 12 +MDC_VCC +3VALW AZ_BITCLK_MD 16 BT_RST# BT@ R442 1 USB20_P5 USB20_N5 1 21 BT_DET# 2 0_0402_5% BT_RESET# C489 BT@ 0.1U_0402_16V4Z @ 1 2 3 4 5 G1 6 G2 ACES_88018-124G @ 13 14 15 16 17 18 21 20 20 GND GND GND GND GND GND JBT 1 2 3 4 5 6 7 8 Connector for MDC Rev1.5 ACES_87213-0600G 2 Touch PAD Connector C C please close to JKB1 KSI[0..7] KSO[0..17] KSI[0..7] KSO16 32 KSO[0..17] 32 JKB 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B JKB34 KSO16 1 2 R372 300_0402_5% +3VS KSO17 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4 2 1 CAPS_LED# R376 300_0402_5% NUM_LED# +3VS CAPS_LED# 32 NUM_LED# 32 @ ACES_88170-3400 A 1 C401 KSO17 1 C402 KSO2 1 C404 KSO1 1 C405 KSO0 1 C406 KSO4 1 C407 KSO3 1 C408 KSO5 1 C409 KSO14 1 C410 KSO6 1 C411 KSO7 1 C412 KSO13 1 C413 KSO8 1 C415 KSO9 1 C416 KSO10 1 C417 KSO11 1 C418 KSO12 1 C419 KSO15 1 C420 KSI7 1 C421 KSI2 1 C422 KSI3 1 C423 KSI4 1 C424 KSI0 1 C425 KSI5 1 C427 KSI6 1 C429 KSI1 1 C431 CAPS_LED# 1 C433 NUM_LED# 1 C435 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J JTOUCH 1 2 3 4 5 6 +5VS 32 32 34 34 TP_CLK TP_DATA SW _L SW _R D57 2 3 7 8 AZ5125-02S.R7G_SOT23-3 Touch ON OFF/B Connector JTPB 1 2 3 4 GND GND 1 2 3 4 5 6 KSO0 KSI6 SW 4 KSI6 1 3 2 4 KSO0 B NTC017-DA1J-D160T @ P-TW O_161011-04021 A Compal Electronics, Inc. Compal Secret Data 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 G7 G8 P-TW O_161021-06021 @ 1 Security Classification 5 1 2 3 4 5 6 6 5 KEYBOARD CONN. for 17" 3 2 Title BT/MDC/KB/TP Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 26 of 48 PCIe Mini Card-WLAN/WiMax 2.75A +3VS For SED +3VS +1.5VS +1.5VS BT_CTRL 1 17 CLKREQ_W LAN# D Q25 2N7002_SOT23-3 2 G 3 21,26 BT_PW R# 17 17 CLK_W LAN# CLK_W LAN S WLAN&BT Combo module circuits BT on module BT on module Enable Disable 17 PCIE_PRX_W LANTX_N2 17 PCIE_PRX_W LANTX_P2 17 PCIE_PTX_C_W LANRX_N2 17 PCIE_PTX_C_W LANRX_P2 +3VS BT_CRTL HI LO BT_PWR# LO HI 32 32 E51_TXD E51_RXD 1 1R16 R17 2 0_0402_5% 2 0_0402_5% 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 GND1 Debug card using 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 54 2 4.7U_0805_10V4Z 1A CM7 CM8 2 0.01U_0402_25V7K W L_OFF# PLT_RST# C253 47P_0402_50V8J @ For SED 0.1U_0402_16V4Z 1 1 JW LAN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 1 1 2 0.01U_0402_25V7K 1 CM3 2 CM2 CM9 2 2 4.7U_0805_10V4Z 2 1 CM1 1 0.1U_0402_16V4Z 1 C254 47P_0402_50V8J @ W L_OFF# 32 PLT_RST# 20,28,32,33 PM_SMBCLK 11,12,13,17 PM_SMBDATA 11,12,13,17 USB20_N13 20 USB20_P13 20 FOX_AS0B226-S40N-7F @ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PCIe-WLAN Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 27 of 48 A B C D E UL1 17 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 HSOP 17 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON 17 18 17 PCIE_PTX_C_LANRX_P1 17 PCIE_PTX_C_LANRX_N1 1 RL19 17 CLKREQ_LAN# 20,27,32,33 25 PLT_RST# 17 17 2 EC_SW I# 100K_0402_5% @ 18 HSIP HSIN EECS/SCL EEDI/SDA 30 32 CLKREQB MDIP0 MDIN0 MDIP1 MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3 PERSTB REFCLK_P REFCLK_N LAN_X1 43 CKXTAL1 LAN_X2 44 CKXTAL2 EC_SW I# EC_SW I# +3VS 31 37 40 19 20 CLK_LAN CLK_LAN# +3V_LAN 1 RL3 0_0402_5% 16 LED3/EEDO LED1/EESK LED0 ISOLATEB 1 RL6 1K_0402_1% 2 1 RL22 RL22 need always pull-high for RTL8105E Efuse mode ISOLATEB DVDD33 DVDD33 27 39 14 15 38 NC/SMBCLK NC/SMBDATA GPO/SMBALERT AVDD33 AVDD33 AVDD33 AVDD33 12 42 47 48 33 ENSWREG 34 35 VDDREG VDDREG 26 2 1K_0402_5% ISOLATEB ENSW REG +LAN_VDDREG RL7 15K_0402_5% 2 1 RL5 2 2.49K_0402_1% 1 2 4 5 7 8 10 11 13 29 41 46 24 49 RL2 RL1 1 10K_0402_5% 1 10K_0402_5% 2 2 +3V_LAN +LAN_REGOUT 1 2 2.2UH +-5% NLC252018T-2R2J-N Layout Note: LL1 must be within 200mil to Pin36, CL13 CL13,CL9 must be within 4.7U_0603_6.3V6K 200mil to LL1 +LAN_REGOUT: Width =60mil LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1- +LAN_VDD10 +LAN_VDD10 +3V_LAN 1 LL2 CL18 1U_0402_6.3V4Z +3V_LAN +3V_AVDDXTAL GND PGND EVDD10 21 AVDD10 AVDD10 AVDD10 AVDD10 3 6 9 45 REGOUT 36 +LAN_VDD10 1 +3V_LAN +LAN_VDDREG 2 2 0_0603_5% +LAN_REGOUT 1 LL3 CL28 4.7U_0603_6.3V6K +3V_AVDDXTAL RL8 RL9 @ 0_0402_5% 1 1 2 2 CL29 0.1U_0402_16V4Z 1 +3V_LAN CL23 68P_0402_50V8J +LAN_VDD10 Reserved For 1.05V Crystal RL23 0_0402_5% @ LAN_ACTIVITY# 2 2 LAN Conn. 1 JLAN LAN_ACTIVITY#_R RL10 1 150_0402_5% 2 RL17 +3V_LAN CL11 0.1U_0402_16V4Z 12 1 11 150_0402_5% 8 CL11 close to pin42 7 RJ45_MIDI1- +3V_LAN LAN_X1 1 2 1 CL8 2 1 1U_0402_6.3V4Z CL26 27P_0402_50V8J 2 2 1 CL27 27P_0402_50V8J CL24 68P_0402_50V8J 2 LAN_SK_LINK# 2 1 2 RL14 1 150_0402_5% SHLD4 16 PR4- SHLD3 15 PR4+ PR2PR3- 4 PR3+ RJ45_MIDI1+ 3 PR2+ RJ45_MIDI0- 2 RJ45_MIDI0+ 1 LAN_SK_LINK#_R 2 RL18 +3V_LAN Amber LED+ 5 LAN_X2 25MHZ_20PF_7A25000012 1 Amber LED- 6 YL1 2 CL15 4.7U_0805_10V4Z @ 2 CL19 2 CL20 2 CL21 2 CL22 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 3 2 1 +LAN_VDD10 1 1 G 3 1 CL19,CL20,CL21,CL22 close to Pin 3,13,29,45 D W OL_EN# 2 CL17 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z RL4 0_0402_5% S 32 2 +LAN_EVDD10 0_0402_5% 1 1 2 2 RL16 47K_0402_5% 1 AO3413_SOT23 CL14 0.01U_0402_25V7K 1 1 ENSW REG QL1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z Vgs=-4.5V,Id=3A,Rds<97mohm CL12 0.1U_0402_16V7K 0.1U_0402_16V4Z 1 RSET 2 1 1 Close to Pin 21 +3VALW RL25 100K_0402_5% 2 2 CL4 2 CL5 2 CL6 2 CL7 0.1U_0402_16V4Z CL9 0.1U_0402_16V4Z +LAN_EVDD10 2 0_0603_5% +3V_LAN +3VALW 1 2 1 RTL8105E-GR QFN _6X6 +3VALW TO +3V_LAN 1 0.1U_0402_16V4Z LANWAKEB +3V_LAN CL4,CL5,CL6,CL7 close to Pin 27,39,47,48 +LAN_VDD10 LL1 DVDD10 DVDD10 DVDD10 28 LL1,CL13 will be changed to 2.2uH&4.7uF after EVT test LAN_SK_LINK# LAN_ACTIVITY# 3 PR1SHLD2 14 PR1+ 10 Green LED- 9 1 150_0402_5% Green LED+ SHLD1 13 LIYO_101005-00803-3 @ UL3 LAN_MDI0+ LAN_MDI0- 1 2 3 4 5 6 7 8 LAN_MDI1+ LAN_MDI1- 4 Place these components colsed to LAN chip TX+ TXCT NC NC CT RX+ RX- 16 15 14 13 12 11 10 9 RJ45_MIDI0+ RJ45_MIDI0- RJ45_MIDI1+ RJ45_MIDI1- CL42 2 1000P_0402_50V7K 1 CL41 2 1000P_0402_50V7K 1 RJ45_GND 1 RL15 2 75_0402_1% 1 RL13 2 75_0402_1% 1 CL36 2 1000P_1808_3KV7K RJ45_GND 2 1 CL37 0.1U_0402_16V4Z 2 CL38 4.7U_0603_6.3V6K 4 CL34 0.1U_0402_25V4K Compal Secret Data Security Classification 2009/01/23 Issued Date 2010/01/23 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A LANGND 1 LFE8456E-R 1 2 TD+ TDCT NC NC CT RD+ RD- B C D Title Compal Electronics, Inc. RTL8105E 10/100 LAN Size Document Number Custom Date: Rev 1.0 NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet E 28 of 48 5 4 3 +PVDD1 2 CA1 0.1U_0402_16V4Z 2 1 MIC1_R_R CA23 1 2 CA29 AVDD2 25 46 PVDD2 40 41 14 15 LINE2_L LINE2_R SPK_OUT_R+ SPK_OUT_R- 45 44 HP_OUT_L HP_OUT_R 32 33 MIC1_L MIC1_R 16 17 MIC2_L MIC2_R 2 13 INT_MIC_DATA 1 L56 INT_MIC_CLK_R 3 2 FBMA-L10-160808-301LMT_2P For EMI Request 4 32 EC_MUTE# @ CA64 1 MONO_IN 2 100P_0402_50V8J SENSE_A 2 4.7K_0402_5% 13 EC_MUTE# 1 RA45 18 1 2 CA15 2.2U_0603_6.3V4Z +MIC1_VREFO_L B CA47 1 2 0.1U_0603_50V7K CA48 1 2 0.1U_0603_50V7K CA49 1 2 0.1U_0603_50V7K CA50 1 2 0.1U_0603_50V7K 12 GPIO0/DMIC_DATA BCLK GPIO1/DMIC_CLK PD# 5 8 CBN 31 MIC1_VREFO_L 43 42 49 7 EAPD 47 SPDIFO 48 MONO_OUT 20 MIC2_VREFO 29 MIC1_VREFO_R LDO_CAP 30 28 SENSE B CBP 2 2 10U_0805_10V4Z RA3 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS 0_0603_1% CA3 1 1 CA4 CA5 1 1 CA6 Pin48 Pin13 place close to chip SPKL+ SPKL- 30 30 SPKR+ SPKR- 30 30 RA4 75_0402_1% RA5 75_0402_1% Pin12 ANALOG Moat DIGITAL (Include Themal PAD) HP_L 30 HP_R 30 Beep sound PVSS2 PVSS1 DVSS2 DVSS1 AZ_SYNC_HD 6 SDATA_IN SENSE A 35 ALC259-GR 2 10U_0805_10V4Z 10 SDATA_OUT PCBEEP 36 D 0.1U_0402_16V4Z +5VS 1 1 CA62 @ @ CA58 C 2 0.01U_0402_25V7K 11 RESET# 16 AZ_RST_HD# 1 CA12 Pin39 Pin1 SPK_OUT_L+ SPK_OUT_L- 21 22 RA11 2 1 0_0603_1% @ CA63 2 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z LINE1_L LINE1_R SYNC 13 INT_MIC_CLK UA1 23 24 1 4.7U_0805_10V4Z C Pin24 EC Beep 16 AZ_BITCLK_HD 16 32 AZ_SDOUT_HD 16 AZ_SDIN0_HD_R 2 RA6 1 33_0402_5% AZ_SDIN0_HD EC_BEEP# PCI Beep 16 16,19 PCH_SPKR RA7 1 2 47K_0402_5% CA13 1 2 RA8 1 2 47K_0402_5% MONO_IN 0.1U_0402_16V4Z 1 MIC1_R_L 30 Pin37 2 10U_0805_10V4Z 1 RA12 10K_0402_5% +MIC1_VREFO_R CA28 10U_0805_10V4Z 1 2 VREF 27 AC_VREF JDREF 19 AC_JDREF2 RA9 CPVEE 34 1 CA14 AVSS1 AVSS2 26 37 2 30 4.7U_0805_10V4Z 2 PVDD1 1 DVDD 9 35mA for 3.3V level place close to chip 39 CA7 10U_0805_10V4Z 2 2 38 0.1U_0402_16V4Z 2 +AVDD 1 AVDD1 1 CA8 2 place close to chip @ 2 1 0_0603_1% Ext. Mic 2 10U_0805_10V4Z +PVDD2 1 CA61 DVDD_IO +3VS +5VS CA43 Pin38 2 +3VS_DVDD 10U_0805_10V4Z 2 2 RA1 Pin25 1 CA2 @ 1 0.1U_0402_16V4Z 1 1 CA44 CA56 1 1 1 2 @ RA20 0_0603_5% +1.5VS D JA1 JUMP_43X39 0.1U_0402_16V4Z 2 RA19 0_0603_5% RA2 2 1 0_0603_1% 0.1U_0402_16V4Z 1 1 CA57 +DVDD_IO 1 1 Pin36 Codec +3VS 2 2 CA18 0.1U_0402_16V4Z 1 20K_0402_1% 1 2 2.2U_0603_6.3V4Z 1 CA17 CA16 10U_0805_10V4Z 2 2 @ 0.1U_0402_16V4Z B ALC259-GR_QFN48_7X7 1 RA18 Sense Pin SENSE A place close to chip DGND 2 0_0603_5% Impedance AGND ALC259Q PN IS NOT READY Codec Signals Function 39.2K PORT-I (PIN 32, 33) Headphone out 20K PORT-B (PIN 21, 22) Ext. MIC 10K PORT-C (PIN 23, 24) 5.1K place close to chip 30 MIC_SENSE 30 NBA_PLUG 2 RA10 1 20K_0402_1% RA21 39.2K_0402_1% SENSE_A (PIN 48) A A 39.2K SENSE B PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-H (PIN 20) Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HD CODEC ALC259 Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 29 of 48 Speaker Connector placement near Audio Codec 29 SPKL+ SPKL+ LA2 1 2 FBMA-L11-160808-800LMT_0603 2 1 SPK_L1 DA6 CA22 470P_0402_50V8J 2 2 1 CA21 470P_0402_50V8J 29 SPKL- 29 SPKR+ 2 1 CA24 1U_0402_6.3V4Z @ JSPK LA3 1 1 2 FBMA-L11-160808-800LMT_0603 SPK_L2 LA4 SPKR+ 1 2 FBMA-L11-160808-800LMT_0603 2 SPK_R1 SPKL- 3 AZ5125-02S.R7G_SOT23-3 SPK_R1 SPK_R2 SPK_L1 SPK_L2 1 2 3 4 DA9 29 SPKR- 1 2 3 4 Ext.MIC/LINE IN ACES_85204-0400N @ 2 1 3 CA25 470P_0402_50V8J 2 1 CA27 1U_0402_6.3V4Z 2 @ 1 CA26 470P_0402_50V8J LA5 1 SPKRSPK_R2 1 2 FBMA-L11-160808-800LMT_0603 RA23 1K_0402_5% 2 1 AZ5125-02S.R7G_SOT23-3 29 MIC1_R_R 2 1 1K_0402_5% RA24 29 MIC1_R_L USB Board RA22 1 2 2.2K_0402_5% MIC1_L RA25 1 2 2.2K_0402_5% +MIC1_VREFO_L Audio & USB Sub-Board Conn. +USB_VCCA Reserve for EMI request @ R73 1 0_0402_5% 2 JUSBB W=80mils 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 L53 W=60mils 2A +5VALW 20 USB20_N0 1 20 USB20_P0 4 1 2 3 4 GND VOUT VIN VOUT VIN VOUT EN FLG 4 @ R86 1 8 7 6 5 RT9715BGS_SO8 1 2 2 USB20_N0_R 3 3 USB20_P0_R USB20_N0_R USB20_P0_R W CM-2012-900T_0805 +USB_VCCA U14 25,32 USB_EN# +MIC1_VREFO_R MIC1_R USB20_N1_R USB20_P1_R 0_0402_5% 2 29 29 Reserve for EMI request USB_OC#0 20,32 1 @ R88 1 C362 4.7U_0805_10V4Z 2 @ 20 USB20_N1 USB20_P1 1 4 AGND 0_0402_5% 2 MIC1_L MIC1_R 29 29 L54 20 HP_R HP_L 1 2 4 3 2 3 NBA_PLUG MIC_SENSE USB20_N1_R USB20_P1_R 1 CA65 0.1U_0402_16V4Z @ 2 @ ACES_85201-20051 1 2 CA66 0.1U_0402_16V4Z @ W CM-2012-900T_0805 @ R87 1 0_0402_5% 2 For EMI Request Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title SPK/AUDIO&USB Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 30 of 48 5 4 3 2 1 D D 2 100P_0402_50V8J RC2 6.19K_0402_1% 2 1 CARD@ +3VS UC1 20 20 +3VS_CR RC3 0_0603_5% USB20_N10 USB20_P10 USB20_N10 USB20_P10 +3VS_CR CARD@ 1 CARD@ 2 CC4 CARD@ 4.7U_0805_10V4Z 1 CC3 0.1U_0402_16V4Z 2 +VCC_3IN1 1 CARD@ 2 V1_8 CC7 1U_0402_6.3V4Z SDW P_MSCLK_R 1 RC24 2 0_0402_5% 1 REFE 2 3 DM DP 4 5 6 3V3_IN CARD_3V3 V18 7 XD_CD# 8 9 10 11 12 SP1 SP2 SP3 SP4 SP5 25 2 CC10 10P_0402_50V8J @ SDW P_MSCLK MSCD# SD_DATA1 SD_DATA0 MS_DATA3_SD_DATA7 1 EPAD 1 @ CC2 GPIO0 17 CR_LED# CLK_IN 24 CLK_48M_CR XD_D7 23 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 22 21 20 19 18 16 15 14 13 CR_LED# 34 CLK_48M_CR 13 < 48MHz > MSBS SD_DATA2_MS_DATA5 MS_DATA1_SD_DATA3 SDCMD MS_DATA0_SD_DATA5 MS_DATA2_SDCLK 1 RC22 2 0_0402_5% SDCD# MS_DATA2_SDCLK_R 1 CC9 10P_0402_50V8J @ RTS5138-GR_QFN24_4X4 CARD@ 2 C C < 3 in 1 Card Reader > JREAD B 22 23 SD-WP SD-DAT1 SD-DAT0 SD-GND MS-GND MS-BS SD-CLK MS-DAT1 MS-DAT0 SD-VCC MS-DAT2 SD-GND MS-INS MS-DAT3 SD-CMD MS-SCLK MS-VCC SD-DAT3 MS-GND GND1 SD-DAT2 GND2 SD-CD SDW P_MSCLK_R SD_DATA1 SD_DATA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 MSBS MS_DATA2_SDCLK_R MS_DATA1_SD_DATA3 MS_DATA0_SD_DATA5 +VCC_3IN1 MSCD# MS_DATA3_SD_DATA7 SDCMD 1 CARD@ CC6 2 0.1U_0402_16V4Z 1 CARD@ CC5 2 1U_0402_6.3V4Z B SD_DATA2_MS_DATA5 SDCD# @ TAITW _R009-025-LR_NR A A Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. RTS5138 Card Reader Size Document Number Custom Date: Tuesday, April 13, 2010 Rev 1.0 NALAA LA-6041P M/B Sheet 1 31 of 48 5 4 3 2 1 +3VL +3VL 0.1U_0402_16V4Z 2 2 C438 C439 2 2 0.1U_0402_16V4Z C440 C442 1 2 C441 1000P_0402_50V7K 1 1 1000P_0402_50V7K U19 VCC VCC VCC VCC VCC VCC for EMI request 0.1U_0402_16V4Z 67 C437 2 AVCC C436 0.1U_0402_16V4Z 1 2 9 22 33 96 111 125 0.1U_0402_16V4Z 1 1 1 1 CLK_PCI_EC D D R378 47K_0402_5% 2 1 2 C444 21 EC_SCI# 34 W L_BT_LED# ECRST# 1 0.1U_0402_16V4Z KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PLT_RST# 2 1 @ C453 0.1U_0402_16V4Z C +3VL KSO1 2 47K_0402_5% 2 47K_0402_5% KSO2 to avoid EC entry ENE test mode 26 KSI[0..7] 26 KSO[0..17] RP7 1 2 3 4 +3VL +3VS 8 7 6 5 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 2.2K_0804_8P4R_5% KSI[0..7] KSO[0..17] 37 37 17 17 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 18 PM_SLP_S3# 18 PM_SLP_S5# 21 EC_SMI# 21 THM_ALT# B 18 PCH_SUSPW RDN 6 FAN_SPEED1 R337 R342 27 E51_TXD 27 E51_RXD 34 ON/OFFBTN# 34 PW R_SUSP_LED# 26 NUM_LED# 100K_0402_5% 1 2 VTTP_EN 100K_0402_5% 1 2 E51_TXD CRY1 CRY2 122 123 97 98 99 109 SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 SPI Flash ROM GPIO SM Bus GPI BATT_TEMPA 37 ADP_I ADP_V BATT_TEMPA 1 C445 ACIN_D 1 C446 38 38 EC_MUTE# 29 USB_EN# 25,30 TP_CLK TP_DATA +5VS TP_CLK 1 4.7K_0402_5% TP_DATA 1 4.7K_0402_5% TP_CLK 26 TP_DATA 26 VGATE LID_SW # 1 R772 VGATE 18,43 W OL_EN# 28 PW RME_CTRL# 16 2 LID_SW #_R 34 1K_0402_1% ACIN_D 4 1 R5 2 4.7K_0402_5% 2 R40 1 10K_0402_5% For prevent leakage for CPU_CORE +3VL 1 2 R331 330K_0402_5% ACIN_D 2 1 ACIN 18,34,36 CH751H-40PT_SOD323-2 PM_PW ROK 18 BKOFF# 13 W L_OFF# 27 B +3VALW EC_SEL @ R128 100K_0402_5% PM_SLP_S4# 18 UMA_ENBKL 19 USB_OC#1 20,25 EC_SEL SUSP# 35,38,42 PBTN_OUT# 18 USB_OC#0 20,30 R130 100K_0402_5% +EC_V18R EC SEL EC Version High KB926D3 Low KB926E0 C448 4.7U_0805_10V4Z BT on module BT on module Enable Disable BT_CRTL HI LO BT_PWR# LO HI A Compal Electronics, Inc. Compal Secret Data 2009/01/23 Issued Date Deciphered Date 2010/01/23 3 Title ENE-KB926 RevD2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 R383 KB926QFE0_LQFP128_14X14 Security Classification 32.768KHZ_12.5PF_Q13MC14610002 C D21 EC_RSMRST# 18 EC_LID_OUT# 17 EC_ON 34 18P_0402_50V8J 2 LID_SW #_R 2 47K_0402_5% VR_ON FSTCHG 38 BATT_FULL_LED# 34 CAPS_LED# 26 BATT_CHG_LOW _LED# 34 PW R_ON_LED# 34 SYSON 41 VR_ON 43 2 R379 2 R381 +3VALW SYSON EC_SI_SPI_SO 33 EC_SO_SPI_SI 33 SPI_CLK 33 SPI_CS# 33 C450 Y4 2 100P_0402_50V8J 2 100P_0402_50V8J VTTP_EN 40 EN_DFAN1 6 IREF 38 CHGVADJ 38 SPI Device Interface GND GND GND GND GND 4 OSC NC 1 OSC NC 3 A 2 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 38 1 2 18P_0402_50V8J C449 83 84 85 86 87 88 11 24 35 94 113 @ 10M_0402_5% 1 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F XCLK1 XCLK0 2CRY2 1 PS2 Interface PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A R389 CRY1 68 70 71 72 DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KB_RST# 2 1 @ C452 0.1U_0402_16V4Z 1 R380 1 R382 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 For EMI request DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F AD Input ACOFF BATT_TEMPA 1 +3VL BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 63 64 65 66 75 76 EC_BEEP# 29 2 20 CLK_PCI_EC 20,27,28,33 PLT_RST# PWM Output 21 23 26 27 1 CLK_PCI_EC 12 13 ECRST# 37 20 38 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 2 2 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC AGND 2 1 C443 @ 22P_0402_50V8J 1 2 3 4 5 7 8 10 21 GATEA20 21 KB_RST# 16,33 SERIRQ 16,33 LPC_FRAME# 16,33 LPC_AD3 16,33 LPC_AD2 16,33 LPC_AD1 16,33 LPC_AD0 69 R377 @ 10_0402_5% 2 Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 32 of 48 SPI Flash (256KB) LPC Debug Port Socket: SP07000F500 & SP07000H900 Please place the PAD under DDR DIMM. +3VL H7 +3VS 1 20mils 6 5 SERIRQ 7 4 PLT_RST# 20,27,28,32 LPC_AD3 8 3 LPC_AD2 16,32 LPC_AD1 9 2 LPC_AD0 16,32 10 1 CLK_PCI_DDR U22 2 8 VCC 3 W HOLD 32 SPI_CS# 1 S 32 6 SPI_CLK 5 4 16,32 7 32 EC_SO_SPI_SI VSS 16,32 16,32 C D Q 2 EC_SI_SPI_SO 32 16,32 LPC_FRAME# MX25L2005CMI-12G SO8 20 2 C451 0.1U_0402_16V4Z @ DEBUG_PAD 1 R393 22_0402_5% 2 SPI_CLK 1 R394 2 10_0402_5% 1 C454 1 2 10P_0402_50V8J reserve for EMI, close to U22 C457 22P_0402_50V8J reserve for EMI Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title SPI ROM/TP/KB/Debug Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 33 of 48 5 4 3 2 Debug Button Power Button SW 2 ISPD @ 1 3 2 4 ON/OFFBTN# ZZZ 2 +3VL 1 R395 PCB 6 5 NTC017-DA1J-D160T 100K_0402_5% PCB LA-6041P REV10 ON/OFFBTN# ON/OFFBTN# 32 1 Q6A 2N7002KDW _SOT363-6 2 EC_ON PCH HM55R3@ another at page 35 1 2 32 debug phase using 6 D59 AZ5125-02S.R7G_SOT23-3 R396 10K_0402_5% PJP1 1 DC-IN 17 DC-IN LED Control Circuit PJP1 45@ Screw Hole LED/B Conn. H2 ACIN_LED# H3 LID_SW #_R ACIN_LED# 32 PW R_ON_LED# 32 PW R_SUSP_LED# 31 32 32 26 26 32 HDD LED Control Circuit SATA_LED# 2 16 2 R415 1 10K_0402_5% HDD_LED# 3 6 1 H30 1 1 1 H_4P2X4P7 @ H_4P2X4P7 @ H31 MDC H_3P3 @ H36 MINI CARD GND GND H_3P3 @ H37 17 18 H_3P3 @ H_3P3 @ @ ACES_85201-1605N 5 +3VS HDD_LED# CR_LED# BATT_FULL_LED# BATT_CHG_LOW _LED# SW _L SW _R W L_BT_LED# +3VALW +5VS +5VALW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 H_4P2 @ 1 32 another at page 35 1 1 JLEDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 C490 0.1U_0402_25V6 1 Q49A 2N7002KDW _SOT363-6 2 H5 C H_4P7 @ 1 For ESD ACIN H4 CPU 6 C 1 @ ACES_85201-0405N 18,32,36 D U11 36 2 51_ON# 3 D 1 JPOW ER 1 1 2 2 3 3 4 4 G1 5 G2 6 Q50A 2N7002KDW _SOT363-6 4 Q50B 2N7002KDW _SOT363-6 H_3P0 @ H23 H_3P0 @ 1 H18 B H_3P0 @ H24 H_3P0 @ 1 H_3P0 @ 1 H_3P0 @ 1 H_3P0 @ H17 H22 1 H21 1 H_3P0 @ 1 H_3P0 @ H_6P8 @ 1 LTW -110TLA1_W HITE @ 1 H25 H26 H_3P3X2P7N @ H27 H_2P7N @ 1 G 1 2 3 2 330_0402_5% 1 DEBUGD2 POWER LED 1 R771 @ H16 H20 1 H19 debug phase using +5VS H_3P0 @ 1 POWER LED Control Circuit H14 1 H13 B H_3P3X2P7N @ PCB Fedical Mark PAD FD3 2009/01/23 Issued Date Deciphered Date Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 A Compal Secret Data Security Classification 5 FD4 @ 1 @ 1 1 A FD2 @ 1 FD1 @ 3 2 Title Comm. SW/ Sub Conn./LEDS Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 34 of 48 A B C +3VALW TO +3VS +3VALW D E +5VALW TO +5VS +3VS +1.5V to +1.5VS +5VALW Vgs=-0V,Id=9A,Rds=18.5mohm +5VS +1.5V 4.7U_0805_10V4Z +1.5VS 4.7U_0805_10V4Z 2 2 2 Prevent noise coupling C469 2 2 R414 820K_0402_5% 1 R411 2 +VSB 220K_0402_5% 3 1 1 FDS6676AS 6 1 R408 1U_0402_6.3V4Z SI4800BDY_SO8 Q11B 1 Q12A SUSP 5 2 2N7002KDW _SOT363-6 2N7002KDW _SOT363-6 470_0805_5% C464 1 Q11A SUSP 5 2 2N7002KDW _SOT363-6 2N7002KDW _SOT363-6 1 2 3 4 1 R413 200K_0402_5% @ S S S G 1 Q12B 4 470_0805_5% 2 6 1 C468 2 +VSB C463 D D D D 2 2 1 1U_0402_6.3V4Z 1 R410 2 47K_0402_5% Q31 8 7 6 5 1 0.1U_0402_25V6 2 C467 R407 C470 2 1 2 3 1 2 4.7U_0805_10V4Z 1 1 C234 1 4 2 1 Q10B 1 2 3 4 SI4800BDY_SO8 C232 Q10A SUSP 2 5 2N7002KDW _SOT363-6 2N7002KDW _SOT363-6 S S S G C462 1 R412 330K_0402_5% +VSB D D D D 1 2 6 1 C466 2 2 1 1 R409 2 47K_0402_5% 8 7 6 5 C461 0.01U_0402_25V7K 1U_0402_6.3V4Z 0.022U_0402_25V7K 4.7U_0805_10V4Z C465 R406 4.7U_0805_10V4Z 2 100P_0402_50V8J 2 SI4800BDY_SO8 1 Q30 100P_0402_50V8J 1 2 3 4 1 4.7U_0805_10V4Z 2 S S S G C460 3 1 1 D D D D 1 4 8 7 6 5 C459 470_0805_5% Q29 Vgs=10V,Id=14.5A,Rds=6mohm 2 +3VALW PS@ R425 100K_0402_5% 1 Q48A 2N7002KDW _SOT363-6 PS@ SUSP 2 0.75VR_EN# 42 4 2 100K_0402_5% Q48B 2N7002KDW _SOT363-6 PS@ 0.75VR_EN 5 6 5,40 VTTPW ROK PS@ 1 R169 2 3 1 2 +5VALW 2 3 +0.75VS 2 3 R422 100K_0402_5% SUSP 32,38,42 SUSP# SUSP 3 3 9,42 1 R421 470_0805_5% NPS@ 1 R421 47_0805_5% PS@ Q6B 2N7002KDW _SOT363-6 5 SUSP Q49B 2N7002KDW _SOT363-6 5 4 4 2 another at page34 another at page 34 1 R423 10K_0402_5% 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC-DC INTERFACE Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet E 35 of 48 A B C D VS VIN 1 PR3 5.6K_0402_5% - O PACIN 1 LM393DG_SO8 PACIN 38 PD1 GLZ4.3B_LL34-2 PR7 10K_0402_1% 2 1 PR8 10K_0402_1% +CHGRTC Vin Detector 3.3V 2 VIN 2 2 2 2 PC8 .1U_0402_16V7K 18,32,34 1 + 2 1 ACIN PU1A 1 3 1 1 2 PC7 0.068U_0402_10V6K PR6 20K_0402_1% PR4 10K_0402_1% 1 2 2 8 2 PR5 22K_0402_1% 1 2 1 1 @ N1 PR2 84.5K_0402_1% PC6 100P_0402_50V8J 2 1 2 PC5 680P_0402_50V7K 1 2 1 @ PC4 1000P_0402_50V7K 2 @ SINGA_2DW -0005-B03 PC3 100P_0402_50V8J 4 2 - 1 - 3 2 2 PC2 680P_0402_50V7K + 1 1 1 PC1 1000P_0402_50V7K + 10A_125V_451010MRL P DC_IN_S2 2 1 1 G DC_IN_S1 PJP1 4 PF1 DC301001M80 PR1 1M_0402_1% 1 2 VIN PL1 SMB3025500YA_2P 1 2 High 18.384 17.901 17.430 Low 17.728 17.257 16.976 1 1 PD3 RLS4148_LL34-2 CHGRTCP 2 PR11 200_0603_5% 1 2 PR10 68_1206_5% N1 3 1 1 VS 1 1 PD4 2 VIN N3 1 1 2 2 PR15 22K_0402_1% 1 1 1 2 38 ACON 3 PU1B 7 1 + 5 - 6 O LM393DG_SO8 SP093MX0000 1 +3VALW 2 +1.5VP @ JUMP_43X118 2 1 1 +5VALW 2 2 1 1 +VSB 2 1 1 1 +0.75VSP 2 PACIN S 1 2 2 1 Precharge detector 15.97V/14.84V FOR ADAPTOR 1 PJ9 2 +3VLP 2 1 1 +3VL +5VALW P PQ3 DTC115EUA_SC70-3 @ JUMP_43X39 (100mA,40mils ,Via NO.= 2) 2 2 1 1 +0.75VS 4 @ JUMP_43X79 (1.5A,60mils ,Via NO.= 4) PJ13 2 2 G PJ17 1 @ JUMP_43X118 +VTTP 3 +GFX_CORE (22A,880mils ,Via NO.=44 OCP=26A) PJ11 2 PQ2 SSM3K7002FU_SC70-3 +1.8VS (2A,80mils ,Via NO.= 4) @ JUMP_43X39 2 1 @ JUMP_43X79 @ JUMP_43X118 (120mA,40mils ,Via NO.= 1) 4 1 PJ10 PJ7 2 2 @ JUMP_43X118 (5A,200mils ,Via NO.= 10 OCP=7.9A) 2 2 +1.8VSP PC14 1000P_0402_50V7K PJ8 +GFX_COREP @ JUMP_43X118 +VSBP +1.5V (9A,360mils ,Via NO.= 18 OCP=9.8A) PJ5 2 1 PR27 47K_0402_1% 2 1 D PJ3 1 @ JUMP_43X118 (5A,200mils ,Via NO.= 10 OCP=7.7A) +5VALW P 2 1 PJ4 1 PR24 499K_0402_1% PR26 191K_0402_1% 3 2 @ PR25 66.5K_0402_1% 3 PJ1 2 +CHGRTC 2 PC15 1000P_0402_50V7K PC13 1000P_0402_50V7K 1 PR23 10K_0402_1% 2 1 3 2 1 2 2 1U_0805_25V4Z EN0 1 PD5 RB715F_SOT323-3 39 2 1 @ MAXEL_ML1220T10 1 PC12 2 +RTCBATT 1 1 2 2 PC11 10U_0805_10V4Z 2 1 N2 PR18 499K_0402_1% 8 2 GND PR20 2.2M_0402_5% 2 1 P IN PR19 100K_0402_1% 1 2 VL PR22 560_0603_5% 1 2 G 1 OUT + PR21 560_0603_5% 1 2 4 3 - PBJ1 2 3.3V G920AT24U_SOT89-3 1 PU2 2 PR16 1K_1206_5% RTC Battery PR17 200_0603_5% +3VALW P B+ 1 51_ON# +CHGRTC 2 PR14 1K_1206_5% RLS4148_LL34-2 2 34 PC10 0.1U_0603_25V7K 2 PC9 0.22U_0603_25V7K 2 2 PR13 100K_0402_1% 2 2 PR12 1K_1206_5% 1 2 PR9 68_1206_5% PQ1 TP0610K-T1-E3_SOT23-3 2 2 BATT+ 1 1 PD2 RLS4148_LL34-2 1 1 +VTT @ JUMP_43X118 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification (20A,720mils ,Via NO.=40 OCP=26.38A) 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title DCIN / DETECTOR Size Document Number NALAA LA-6041P Date: Tuesday, April 13, 2010 Sheet D Rev 1.0 M/B 36 of 48 A B 1 C 1 VMB PF2 15A_65V_451015MRL 1 2 1 2 PR29 47K_0402_1% PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 56 degree C BATT+ +3VLP @ PC18 0.1U_0402_25V6K PR30 1K_0402_1% 1 2 PR28 1K_0402_1% PC16 1000P_0402_50V7K 2 1 1 BATT_P3 BATT_P4 BATT_P5 EC_SMDA EC_SMCA 1 BATT_S1 2 GND GND GND GND 1 2 3 4 5 6 7 8 9 1 10 11 12 13 1 2 3 4 5 6 7 8 9 PL2 SMB3025500YA_2P 1 2 PH2 near main Battery CONN : BAT. thermal protection at 90 degree C Recovery at 56 degree C PC17 0.01U_0402_25V7K 2 PJP2 D 2 @ SUYIN_200045MR009G171ZR VL 1 1 PR31 23.7K_0402_1% 1 2 PR33 23.7K_0402_1% 1 +3VLP 2 PC19 0.1U_0603_25V7K PR32 6.49K_0402_1% 2 1 3 2 PD6 2 PJSOT24C_SOT23-3 3 2 1 PD7 PJSOT24C_SOT23-3 PR34 11.3K_0402_1% 1 1 PU4 VCC TMSNS1 8 2 GND RHYST1 7 3 OT1 TMSNS2 6 4 OT2 RHYST2 5 2 2 PR37 100_0402_1% PH1 100K_0402_1%_NCP15W F104F03RC 1 BATT_TEMPA 32 39 1 1 PR36 100_0402_1% VS_ON 2 2 2 1 1 2 PR35 1K_0402_1% 2 PR40 11.3K_0402_1% G718TM1U_SOT23-8 2 EC_SMB_DA1 32 1 EC_SMB_CK1 32 2 PH2 100K_0402_1%_NCP15W F104F03RC PQ4 TP0610K-T1-E3_SOT23-3 3 B+ +VSBP 1 2 PR42 22K_0402_1% 1 2 1 2 2 1 2 @ PC21 0.1U_0603_25V7K VL PC20 0.22U_0603_25V7K 3 2 1 PR41 100K_0402_1% 3 @ PR44 0_0402_5% 2 1 1 D 3 POK S PQ5 SSM3K7002FU_SC70-3 2 G 2 1 39 @ PC22 .1U_0402_16V7K 1 PR43 100K_0402_1% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet D 37 of 48 B C D B+ @ PC75 10U_1206_25V6M 1 2 3 4.7U_0805_25V6-K PC26 4 4.7U_0805_25V6-K 2 1 PC25 4 4.7U_0805_25V6-K 2 1 PC24 1 CSON 22 4 CELLS CSOP 21 5 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 LX_CHG VREF UGATE 17 DH_CHG 2 1 VDDP 15 11 VADJ LGATE 14 GND PGND 13 PR70 20K_0402_1% 12 DL_CHG 26251VDD 1 1 3 2 PL3 PR63 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1% CHG1 1 2 4 1 4 PD12 RB751V-40TE17_SOD323-2 6251VDDP 2 PACIN G PQ16 SSM3K7002FU_SC70-3 2 PR71 4.7_0603_5% PC45 4.7U_0805_6.3V6K 2 BATT+ 3 @ PC74 10U_1206_25V6M 2 1 ACLIM PC40 0.1U_0603_25V7K BST_CHGA 2 1 S 2 PQ17 AO4466_SO8 1 2 1 4 PR61 2.2_0603_1% PR67 2.2_0603_1% BST_CHG 1 2 D PC42 10U_1206_25V6M 2 1 10 2 PC41 10U_1206_25V6M 2 1 16 1 PC33 0.1U_0603_25V7K PR65 4.7_1206_5% BOOT 2 5 6 7 8 2 CSON 1 CHLIM VIN PD11 PC73 10U_1206_25V6M 2 1 6251aclim 9 PR54 200K_0402_1% 1 2 3 PR57 20_0603_5% 1 2 PC32 0.047U_0603_16V7K 1 2 PR58 20_0603_5% 2 1 PR59 20_0603_5% PC37 0.1U_0603_25V7K 1 2 5 6 7 8 PR68 75K_0402_1% 6251VREF 1 2 ACOFF 2 1 3 EN 3 2 1 2 PC29 2.2U_0603_6.3V6K 2 1 3 8 1 1SS355_SOD323-2 2 PR69 120K_0402_1% 6251VREF VIN 1SS355_SOD323-2 PC43 680P_0603_50V8J PQ20 DTC115EUA_SC70-3 2 23 PQ19 AO4466_SO8 ACOFF DCIN ACSET ACPRN 1 PD9 PQ15 DTC115EUA_SC70-3 3 2 1 ACOFF VDD 1 ADP_I 1 PR66 32 154K_0402_1% 2 1 PC31 0.1U_0603_25V7K 2 1 2 6 @ PC38 100P_0402_50V8J 1 2 PC39 .1U_0402_16V7K DCIN 24 PR62 47K_0402_1% 7 2 2 1 2 32 1 6.81K_0402_1% 2 PU5 1 2 IREF 1 32 1 0.01U_0402_25V7K 6800P_0402_25V7K 2 SUSP# 32,35,42 RB715F_SOT323-3 2 ACON PR60 3 6251_EN PR52 10K_0402_1% 2 1 1 3 PACIN 36 S PR64 22K_0402_5% 1 2 PC35 1 PC36 1 2 FSTCHG 2 8 7 6 5 PR49 47K_0402_1% 1 2 PD8 1 D 2 G PACIN 1 2 2 1 2 36 PC30 .1U_0402_16V7K PR55 150K_0402_1% PQ14 SSM3K7002FU_SC70-3 2 PR56 100K_0402_1% 1 1 PC44 0.01U_0402_25V7K 2 1 S 2 G PR51 100K_0402_1% 2 1 6251VDD PR53 10K_0402_1% 2 1 FSTCHG PQ18 SSM3K7002FU_SC70-3 1 3 3 32 PQ12 DTC115EUA_SC70-3 @ PQ9 AO4435_SO8 1 2 3 @ 2 D 1 PR50 100K_0402_1% PD10 1SS355_SOD323-2 1 2 PQ13 DTC115EUA_SC70-3 DCIN 2 P3 1 PR46 200K_0402_1% PQ11 TP0610K-T1-E3_SOT23-3 PR47 10_0603_5% 3 1 1 2 8 7 6 5 1 CSIN 2 1 1 2 2 PR48 47K_0402_1% 2 3 CSIP PC28 5600P_0402_25V7K 1 2 2 2 2 1 1 1 PQ10 DTA144EUA_SC70-3 PC27 0.1U_0603_25V7K 3 1 8 7 6 5 1 2 3 CHG_B+ 1000P_0402_25V8J 2 1 1 2 3 B+ PR45 0.02_2512_1% 1 4 4 1 2 3 4 8 7 6 5 2 VIN P3 PQ8 AO4407A_SO8 PC23 P2 PQ7 AO4435_SO8 PQ6 AO4435_SO8 @ PC76 10U_1206_25V6M PL19 HCB4532KF-800T90_1812 1 2 1 A ISL6251AHAZ-T_QSOP24 1 32 CHGVADJ PR72 15.4K_0402_1% 1 2 PR73 31.6K_0402_1% 3 VIN 2 3 CP= 92%*Iada; CP=3.147A Vaclim=1.08V(65W) PR68=75k 1 CP mode Iada=0~3.42A(65W) PR74 309K_0402_1% PR75 10K_0402_1% 1 2 2 PR45=0.02 Vcell CHGVADJ IREF=0.254V~3.048V 4V VCHLIM need over 95mV 4.2V 1.882V 4.35V 3.2935V ADP_V 32 PR76 47K_0402_1% PC46 .1U_0402_16V7K 2 2 0V 1 IREF=1.016*Icharge 1 CHGVADJ=(Vcell-4)/0.10627 CC=0.25A~3A 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title CHARGER Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet D 38 of 48 5 4 3 2 1 PC47 1U_0603_10V6K 2VREF_51125 1 2 G 12 LGATE2 LGATE1 19 LG_5V 5 6 7 8 1 2 B++ S 2 + 1 VL @ PR89 0_0402_5% 2VREF_51125 2 3 2 1 2 +5VALWP 1 PC56 680P_0603_50V8J NC @ 4 18 17 16 GND EN PQ24 AO4712_SO8 RT8205EGQW _W QFN24_4X4 1 1 2 @ B Ipeak=5A Imax=3.5A F=245KHz Total Capacitor 220u ESR 15m ohm PQ27 DTC115EUA_SC70-3 2 2 1 PR92 42.2K_0402_1% A @ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 PL5 4.7U_LF919AS-4R7M-P3_5.2A_20% 1 2 1 2 PR91 100K_0402_1% A 4 37 PC54 220U_6.3V_M LG_3V POK 3 1 PC60 0.01U_0402_16V7K VS 1 VS_ON 23 1 PR90 100K_0402_1% 2 37 2 24 1 2 LX_5V PQ26 SSM3K7002FU_SC70-3 3 3 S 1 20 D 2 G ENTRIP1 PHASE1 13 2 3 PHASE2 2 PC59 0.1U_0603_25V7K 1 1 D PQ25 SSM3K7002FU_SC70-3 VO1 PGOOD C PQ22 AO4466_SO8 PC58 4.7U_0805_10V6K ENTRIP2 2 11 1 ENTRIP1 FB1 LX_3V PR88 100K_0402_5% B PC57 1U_0402_6.3V6K Total Capacitor 220u ESR 15m ohm REF 21 VREG5 22 UGATE1 VIN BOOT1 UGATE2 EN0 1 @ 4 BOOT2 10 2 B+ 36 PR87 499K_0402_1% 1 2 FB2 9 UG_3V 15 8 7 6 5 PR85 4.7_1206_5% 2 1 4 TONSEL BST_3V PC52 .1U_0402_16V7K PR84 BST_5V 1 2 1 2 0_0603_5% UG_5V SKIPSEL VREG3 1 2 3 2 6 VO2 8 PQ23 AO4712_SO8 PC55 680P_0603_50V8J 2 1 + Ipeak=5A Imax=3.5A F=305KHz PR83 2 1 2 0_0603_5% PC51 .1U_0402_16V7K @ PC53 220U_6.3V_M 1 1 2 3 1 +3VALWP P PAD 7 4 PL4 4.7U_LF919AS-4R7M-P3_5.2A_20% 1 2 ENTRIP2 1 25 5 PU6 14 PQ21 AO4466_SO8 VL PR82 150K_0402_1% 2 1 1 PR86 4.7_1206_5% ENTRIP1 PR81 150K_0402_1% 1 2 B++ 5 6 7 8 PR80 19.1K_0402_1% 1 2 3 2 1 PR79 20K_0402_1% 1 2 PC49 10U_1206_25V6M PR78 30K_0402_1% 1 2 2 PC50 4.7U_0805_10V6K 8 7 6 5 1 2 PC48 10U_1206_25V6M 1 2 PC78 10U_1206_25V6M 2 1 @ C +3VLP 1 PC77 10U_1206_25V6M 2 B+ PR77 13K_0402_1% 1 2 ENTRIP2 B++ PL20 HCB4532KF-800T90_1812 D 2 D 4 3 2 Title 3VALWP/5VALWP Size Document Number NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 39 of 48 Rev 1.0 A C D PL6 HCB4532KF-800T90_1812 1 +VTTP_B+ +5VS 5,35 4 VCC BST_+VTTP 2 BOOT PR97 4.7_0603_5% 1 2 +VTTP_VCC 5 DH_+VTTP 1 PR96 0_0402_5% 15 DH_+VTTP 2 PQ28 TPCA8030-H_SOP-ADV8-5 4 PVCC 14 LG 13 PGND 12 ISEN 11 1 2 PC65 2.2U_0603_6.3V6K Arrandale 1.05V DL_+VTTP PL7 1.0UH_PCMC104T-1R0MN_20A_20% 1 2 1 3 2 1 2 Material Note: 390uF/ 10mohm, number are 3, power x1, HW x2 Ipeak=20A Imax=14A F=231KHz @ 1 2 PR103 3.32K_0402_1% 1 3 1 1 2 PR106 4.42K_0402_1% 2 PC67 390U_2.5V_M 1 PR99 4.7_1206_5% + 2 1 2 1 @ PC70 0.01U_0402_16V7K 1 2 4 1 PC69 680P_0603_50V8J VO 2 PR98 9.76K_0402_1% 10 9 FB @ SE_+VTTP 1 +VTTP PR102 57.6K_0402_1% 2 @ PC71 33P_0402_50V8J 2 1 @ PR101 33.2K_0402_1% 2 1 2 1 PC72 2200P_0603_50V7K 6 2 1 PC68 .1U_0402_16V7K NC PR100 0_0402_5% FSET EN 7 5 2 FB_+VTTP 1 PQ29 5 2 32 VTTP_EN +VTTP APW 7138NITRL_SSOP16 TPCA8028-H_SOP-ADVANCE8-5 PC66 2.2U_0603_6.3V6K 2 +5VALW 1 PC64 0.1U_0603_25V7K 3 2 1 VIN PHASE 3 +VTTP_VCC PGOOD GND PU7 16 1 PR184 4.53K_0402_1% 1 2 PR94 2.2_0603_1% 1 2 1 PR95 2.43K_0402_1% 1 2 PR93 PR187 0_0402_5% UG VTTPW ROK 2 2 1 3.4K_0402_1% LX_+VTTP VTTPW ROK_CPU 2 5 8 2 1 PC61 4.7U_0805_25V6-K 2 1 2 1 PC63 4.7U_0805_25V6-K B+ 2 1 PC62 4.7U_0805_25V6-K 1 B 2+VTTP PR104 0_0402_5% 2 PR108 10_0402_5% 1 2 PR110 10_0402_5% 3 Total Capacitor 1170u ESR 3.33m ohm VTT_SENSE 8 PJ20 +VTTP 2 2 1 1 +1.05VS @ JUMP_43X79 VSS_SENSE_VTT 8 (7.0A,280mils ,Via NO.=14) Arrandale -- mount, Clarksfield --non mount @ 4 4 Compal Secret Data Security Classification Issued Date 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. +VTTP Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Sheet Tuesday, April 13, 2010 D 40 of 48 5 4 3 2 1 PL21 HCB2012KF-121T50_0805 PQ34 AO4466_SO8 PR127 255K_0402_1% 1 2 NC 10 LGATE 9 DL_1.5V LX_1.5V +5VALW PQ35 AO4712_SO8 1 + 2 4 1 PGND RT8209BGQW _W QFN14_3P5X3P5 2 8 7 C GND 2 PC96 4.7U_0603_6.3V6K 3 2 1 VDDP 2 PR132 18K_0402_1% 1 PC98 4.7U_0805_10V6K PC95 220U_6.3V_M PGOOD 11 1 6 12 CS PR130 4.7_1206_5% FB PHASE +1.5VP 2 5 13 1 VDD DH_1.5V UGATE 2 VOUT 4 PL10 1.8UH_SIL104R-1R8PF_9.5A_30% 1 2 5 6 7 8 3 PC94 0.1U_0603_25V7K 1 2 3 2 1 TON 14 15 1 EN/DEM 2 PR131 100_0603_1% 1 2 2 2 PR129 2.2_0603_1% 1 +5VALW PU10 B+ D PC97 680P_0603_50V8J BST_1.5V 1 @PC93 @ PC93 .1U_0402_16V7K 1 4 BOOT SYSON 1 32 PR128 0_0402_5% 1 2 2 5 6 7 8 D 2 PC92 4.7U_0805_25V6-K 1 PC91 4.7U_0805_25V6-K 2 1 1.5V_B+ Ipeak=9A Imax=6.3A F=313KHz Total Capacitor 610u ESR 6m ohm C PR134 10K_0402_1% 2 1 PR133 10K_0402_1% 1 2 B B A A Compal Secret Data Security Classification Issued Date 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. +1.5VP Size Document Number Custom Date: Tuesday, April 13, 2010 Rev 1.0 NALAA LA-6041P M/B Sheet 1 41 of 48 A B C D 1 1 +1.5V PJ23 @ JUMP_43X79 1 VIN VCNTL 6 2 GND NC 5 3 VREF NC 7 4 VOUT NC 8 TP 9 +5VALW 1 2 PC99 1U_0603_10V6K 1 +0.75VSP 2 1 2 1K_0402_1% 1K_0402_1% 1 PR135 2 1 PR138 2 S 1 G2992F1U_SO8 PC102 0.1U_0402_10V7K 2 @ PC101 .1U_0402_16V7K D 2 G 1 35 0.75VR_EN# PQ36 SSM3K7002FU_SC70-3 2 PR137 0_0402_5% 1 2 4.7U_0805_6.3V6K PC100 9,35 SUSP 1 @ PR136 0_0402_5% 1 2 PU11 3 1 2 2 1 PC103 10U_0805_6.3V6M 2 2 1 2 PR125 0_0402_5% 5 BS 7 POK TP +1.8VSP 3 6 11 @ MP2121DQ-LF-Z_QFN10_3X3 PR126 4.7_1206_5% 2 PC90 680P_0603_50V8J 1 1 IN PL9 2.2UH_FMJ-0630T-2R2 HF_8A_20% 1 2 PC89 22U_0805_6.3V6M IN 8 2 4 SW 2 PC87 10U_0805_10V4Z PC86 10U_0805_10V4Z 1 2 2 1 1 PC85 0.1U_0402_25V6 2 1 2 9 1 SW 10 GND 2 3 EN/SYNC PC88 22U_0805_6.3V6M GND 1 FB 2 1 2 2 1 PD13 B340A_SMA2 PC84 0.1U_0402_16V7K 1 3 +5VALW @PC83 @ PC83 0.1U_0402_16V7K 1 +1.8VSP PL22 HCB2012KF-121T50_0805 SUSP# 32,35,38 PU9 1 PR124 402K_0402_1% 2 1 PR123 316K_0402_1% 2 2 PR122 0_0402_5% 1 2 4 4 Compal Secret Data Security Classification Issued Date 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 0.75VSP/+1.8VSP Size Document Number Rev NALAA LA-6041P M/B1.0 Date: Sheet Tuesday, April 13, 2010 D 42 of 48 8 CPU_VID4 8 CPU_VID5 8 CPU_VID6 1 2 1 2 1 2 1 2 1 2 1 2 1 2 PR159 0_0402_5% 1 PR144 1K_0402_1% CPU_VID1 2 1 @ PR145 1K_0402_1% 2 1 PR146 1K_0402_1% CPU_VID2 2 1 @ PR147 1K_0402_1% CPU_VID3 2 1@ PR148 1K_0402_1% CPU_VID3 2 1 2 1@ PR151 1K_0402_1% CPU_VID4 2 1 CPU_VID5 2 1 PR154 1K_0402_1% CPU_VID5 2 1 @ PR155 1K_0402_1% CPU_VID6 2 1@ PR157 1K_0402_1% CPU_VID6 2 1 H_DPRSLPVR 2 1 PR160 1K_0402_1% H_DPRSLPVR 2 1 @ PR161 1K_0402_1% PR152 1K_0402_1% PR158 1K_0402_1% PQ37 PR162 0_0402_5% PR164 0_0402_5% + 2 1 + 2 B+ H H_PSI# 2 1 PR163 1K_0402_1% 4 PR165 0_0402_5% VR_ON +VTT PR166 0_0603_5% BOOT2_2 1 2 BOOT2 PC117 0.22U_0603_25V7K 1 2 PL12 0.36UH_PCMC104T-R36MN1R17_30A_20% UGATE2 PR168 0_0402_5% G PHASE2 3 2 1 3 2 1 2 PR179 1 8 H_PSI# PR180 1 2 147K_0402_1% 40 39 38 37 36 35 34 33 32 31 PR186 1 PR195 1 D PC143 0.22U_0603_25V7K 1 2 1 3 2 1 3 2 1 2 1 2 PC141 10U_1206_25V6M 2 1 2 2009/01/23 Issued Date V2N B VSUM+ ISEN1 Deciphered Date Title +CPU_CORE Size C Date: 5 4 3 A Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 6 2 VSUM- Compal Secret Data Security Classification 7 2 PR213 1_0402_5% @ PR216 0_0402_5% 1 A 8 +CPU_CORE V1N 1 1 3 1 2 PR212 10K_0402_5% PR211 3.65K_0805_1% 2 1 2 VSUM- Layout Note: Place near Phase1 Choke 1 2 1 1 2 @ PR249 100_0402_1% 1 2 10K_0402_1%_ERTJ0EG103FA 4 PC150 680P_0603_50V8J 1 @ PC168 1200P_0402_50V7K PH4 1 PR215 11K_0402_1% 2 1 2 PR214 1.2K_0402_1% 4 4 PC151 .1U_0402_16V7K 1 @ PR219 10_0402_5% 1 2 1 LGATE1 PR210 4.7_1206_5% PQ45 TPCA8028-H_SOP-ADVANCE8-5 5 PHASE1 PC147 0.01U_0402_25V7K PC149 330P_0402_50V7K 1 2 0_0402_5% 2 2 PC148 1000P_0402_50V7K PR217 1 PC140 10U_1206_25V6M PL14 0.36UH_PCMC104T-R36MN1R17_30A_20% @ VSSSENSE PC139 470P_0603_50V8J 2 1 C 3 2 1 PR207 0_0603_5% 1 2 BOOT1_1 PQ44 TPCA8028-H_SOP-ADVANCE8-5 1 2 4 5 2 PR206 82.5_0402_1% 1 PC146 330P_0402_50V7K TPCA8030-H_SOP-ADV8-5 UGATE1 PR208 2.61K_0402_1% 2 1 VSUM2 0_0402_5% 2 1 PR209 2 2 @ PR205 10_0402_5% PQ43 VSSSENSE PC145 0.22U_0603_10V7K 2 1 2 PR204 9.1K_0402_1% VSUM+ PC144 0.047U_0402_16V7K 2 1 1 PC134 0.22U_0603_25V7K 1 2 1 0_0402_5% PC133 1U_0603_10V6K 2 1 PR203 +CPU_B+ BOOT1 ISEN1 2 0_0402_5% 1 2 2 1_0402_5% 2 +5VALW Arrandale -- 2 phase 1H1L IMVP_IMON 1 PR201 0_0402_5% 2 8 5 0_0402_5% 2 +CPU_B+ PC135 0.22U_0603_25V7K PR198 1 1 ISEN2 Layout Note: PH3 place near Phase1 L-MOS 8 1 0_0402_5% 2 1 PR199 412K_0402_1% VCCSENSE 2 1 PC128 1U_0603_10V6K 2 1 PC130 2 1 PR202 8 F 2 CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 AGND 2 +CPU_CORE ISEN2 E PR196 2.55K_0402_1% 1 2 1 C VSUM- PR183 0_0402_5% 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 PR194 562_0402_1% 2 1 41 BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 PC138 0.22U_0402_6.3V6K PC132 150P_0402_50V8J V1N 2 390P_0402_50V7K 2 PC131 10P_0402_50V8J 2 2 PC126 22P_0402_50V8J 1 1 PR171 1_0402_5% @ PR175 0_0402_5% 1 +5VALW PC119 1U_0603_10V6K 1 2 ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1 1 2 3 4 5 6 7 8 9 10 PC137 0.22U_0402_6.3V6K 2 1 PR188 8.06K_0402_1% 1 2 PC127 1000P_0402_50V7K 2 1 PR189 249K_0402_1% 1 2 1 D 2 ISL62883HRZ-T_QFN40_5X5~D E 1 PR173 10K_0402_5% 1 PR169 4.7_1206_5% 0_0402_5% 2 PU13 @ +CPU_CORE V2N VSUM+ @ PR178 1K_0402_1% 1 2 +VTT F 2 1 PR170 3.65K_0805_1% 2 1 PR174 1.91K_0402_1% 2 VGATE 4 1 18,32 PR177 0_0402_5% 1 4 2 2 LGATE2 1 CLK_ENABLE# 2 1 3 TPCA8028-H_SOP-ADVANCE8-5 2 PR172 1.91K_0402_1% 1 PC118 680P_0603_50V8J @ PQ38 +3VS 4 5 13 CLK_ENABLE# PQ39 TPCA8028-H_SOP-ADVANCE8-5 8 H_DPRSLPVR 5 G B 1 TPCA8030-H_SOP-ADV8-5 PR167 0_0402_5% 32 PL11 HCB4532KF-800T90_1812 1 2 PR149 1K_0402_1% CPU_VID4 1 @ PC115 0.1U_0603_25V7K 2 1 CPU_VID3 2 CPU_VID2 2 +CPU_B+ PC111 68U_25V_M_R0.36 CPU_VID2 8 2 PR156 0_0402_5% CPU_VID1 3 PC114 68U_25V_M_R0.36 8 1 PR153 0_0402_5% 1 @ PR143 1K_0402_1% 1 CPU_VID1 2 2 CPU_VID0 8 2 CPU_VID0 3 2 1 8 1 1 PR142 1K_0402_1% PC113 10U_1206_25V6M 2 1 PR150 0_0402_5% H 4 2 PC116 10U_1206_25V6M 5 CPU_VID0 PC110 2200P_0402_50V7K 2 1 6 PC112 470P_0603_50V8J 2 1 7 5 8 2 Document Number NALAA LA-6041P M/B Tuesday, April 13, 2010 Sheet 43 1 of 48 Rev 1.0 A B C D E F G H 2 PR231 33 1 2 PC153 10U_1206_25V6M 1 2 PQ46 TPCA8030-H_SOP-ADV8-5 1 1 PC161 390U_2.5V_M 4 17 2 +GFX_COREP 1 PR235 4.7_1206_5% + 12 1 PC159 2.2U_0603_10V6K 2 PC163 680P_0603_50V8J Ipeak=22A Imax=15.4A F=350KHz 2 Total Capacitor 780u ESR 5m ohm Place RTH1 close to inductor on the same layer PR242 71.5K_0402_1% 2 1 1 1 1 PC165 560P_0402_50V7K PR246 165K_0402_1% 2 2 PC164 1000P_0402_50V7K 1 3 1 1 PR247 47K_0603_1% 2 PC166 1000P_0402_50V7K B+ PL16 0.36UH_PCMC104T-R36MN1R105_30A_20% 1 2 2 2 PQ47 GFX_DRVL 18 2 Connect to input caps 1 PH5 220K_0402_5%_ERTJ0EV224J~D 2 2 3 2 1 +5VS 3 2 1 CSCOMP CSFB 19 4 16 15 LLINE CSREF 14 RT AGND 20 GFX_RAMP-1 2 9 9 VCC_AXG_SENSE VSS_AXG_SENSE +GFX_B+ 13 12 IREF 9 PR240 237K_0402_1% 1 2 GFX_RPM GFX_CSCOMP 1 PR239 80.6K_0402_1% GFX_IREF 1 2 2 2 1 1 3 AGND GFX_SW GFX_CSCOMP PR244 0_0402_5% PR248 1K_0402_1% 2 1 GFX_CSFB PR243 0_0402_5% GFX_CSCOMP Avoid high dV/dt RAMP ILIM PR237 20K_0402_1% GFX_RAMP 1 2 PR238 10.7K_0402_1% DRVL PGND GPU 2 PC162 470P_0402_50V8J PU15 COMP GFX_ILIM 8 PR236 1K_0402_1% PVCC GFX_DRVH 21 1 1 FB GFX_VCC 7 PR245 422K_0402_1% 2 2GFX_COMP-1 1 5 GFX_COMP 6 11 1 PC160 47P_0402_50V8J GFX_RT GFX_FB 2 2 1 PC158 220P_0402_50V7K ADP3211AMNR2G_QFN32_5X5 22 PR234 PC157 0_0603_5% 0.22U_0603_25V7K 2GFX_BOOST-1 1 2 TPCA8028-H_SOP-ADVANCE8-5 SW FBRTN 24 23 GFX_BOOST 1 5 CLKEN# 4 2 26 DRVH 3 5 1 VID6 VID5 27 VID4 VID3 28 29 VID2 VID1 BST IMON RPM 2 PC156 1000P_0402_50V7K PWRGD 2 10 VSS_AXG_SENSE VCC 1 GFX_IMON PR241 340K_0402_1% 1 2 2 2 1 PR233 10K_0402_1% PC154 1U_0805_25V6K PC152 10U_1206_25V6M 1 GFX_VCC PR227 PR226 1 PR225 1 9 9 9 GFXVR_VID_2 9 GFXVR_VID_3 9 GFXVR_VID_4 9 GFXVR_VID_5 9 GFXVR_VID_6 9 GFXVR_VID_1 PR223 PR224 1 1 1 30 31 32 EN VID0 1 2 1 2 2 +3VS PR232 6.98K_0402_1% PL15 HCB4532KF-800T90_1812 PR228 10_0603_1% 1 GFX_IMON PC155 0.056U_0402_16V7K +GFX_B+ 25 2 GFXVR_IMON 1 9 +5VS GFX_EN 1 @ PR229 300K_0402_5% 1 1 PR221 +1.05VS PR222 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% GFXVR_EN 1 GFXVR_VID_0 1 PC167 1000P_0402_50V7K Switchable -- mount Non Swithchable--non mount @ Shortest the net trace 4 4 2009/10/02 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/10/02 Title +GFX_COREP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size NALAA LA-6041P M/B Date: A B C D E F Document Number G Tuesday, April 13, 2010 Sheet 44 H of 48 Rev 1.0 5 4 3 2 1 PIR (Product Improve Record) OBMBB!MB.7152Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/2!UP!1/3 OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF ........................................................................................................................................................ D C B 11/26 34 Change C296,C299,C300,CA64,CM1,CM7 from SE072103Z80 to SE068103K80 12/09 34 Connect JLEDB.15&16 to GND For reduce BOM type For T/P SW issue 12/09 25,30 Change U14 & U15 from SA00002XX00 to SA000033H00 For material issue 12/16 15 Change R159 from IHDMI@ to @ For HDMI level shift disable function 12/16 31 Change CC2 from CARD@ to @ For Card Reader issue 12/16 34 Modify JLEDB pin define For customer concern 12/16 21 Del R222 and connect PCH GPIO45 to GND For LVDS_SEL (Dual-Channel) 12/16 13 Change U5 from SA00003HQ00 to SA00003HQ10 For CLK GEN update 12/16 27 Add R22 and Net BT_PWR#_R to connect JWLAN Pin5 For BT/WLAN combo Mini Card 12/16 16 Change U13 footprint to M25P80-VMW6TP_SO8 and delete BOM structure. For delete ROM socket 12/16 34 Change H36, H37 from H_3P3 to H_3P8. For ME modify 12/16 26 Reverse JBT pin definition For ME modify 12/16 31 Change CC2 from 0.1u to 100P (SE071101J80) and add BOM structure @. For Card Reader issue 12/16 34 Change JPOWER footprint to ACES_85201-0405N_4P. For ME modify 12/16 26 Change JTPB footprint to P-TWO_161011-04021_4P-T. For ME modify 12/16 34 Change JLEDB footprint to ACES_85201-1605N_16P For ME modify 12/16 30 Change JUSBB footprint to ACES_85201-20051_20P For ME modify 12/16 34 Del H15 For ME modify 12/21 34 Change H36,H37 from H_3P8 to H_3P3 For ME modify 12/21 13 Change +LCD_INV from JLVDS.35 to JLVDS.40 For prevent burn issue 12/21 13 Change BKOFF#_R from JLVDS.40 to JLVDS.35 For prevent burn issue 12/23 16,32 Change net name from PWRME_CTRL to PWRME_CTRL# For signal is LOW active 12/23 08 Add C125 SF000002Y00 For co-lay with C123 12/23 09 Del C128 For del co-lay with C185 12/23 09 Del C140 For del co-lay with C217 12/23 17 Change Y2 P/N from SJ125P0M200 to SJ100003300 For cost down plan For BT/WLAN combo Mini Card C 12/23 27 Delete R22 and BT_PWR#_R and add Q25 and BT_CTRL at JWLAN pin5 12/24 29 Change RA26 to L56 bead 300 ohm FBMA-L10-160808-301LMT(SM010017710) For EMI issue 12/24 15 Add R96 1K ohm to connect HDMI_HPD and U9.1 For prevent U9 ESD damage issue 12/24 30 Change LA2,LA3,LA4,LA5 to 80 Ohm bead FBMA-L11-160808-800LMT (SM010015410) For EMI request 12/24 30 Change CA21,CA22,CA25,CA26 to 470P (SE071471J80) For EMI request 12/24 26 Del R361 BOM structure BT@ (always mount) For BT function 12/28 26 Change R392 BOM structure from BT@ to @. For BT function 12/28 26 Change C159,C160,C185,C217,C268 footprint from C_PXC6P3VC220MF60 to C_MP2VU390MC5R7. 12/28 25 Change JODDB footprint to ACES_88058-120N_12P-T. 12/29 13 Del C292 Only for NSWAA 12/29 28 Change UL3 P/N from SP050005W00 to SP050005V00 For EMI request D B For DFX request 12/29 28 Change UL1 P/N from SA00003PO00 to SA00003PO10 For IC chip revise version 01/05 06 Change C4 from SE068102J80 to SE074102K80 For component common design A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW PIR 0.1 TO 0.2 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 45 of 48 5 4 3 2 1 OBMBB!MB.7152Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/3!UP!1/4 OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF ........................................................................................................................................................ D 01/19 13 Change BKOFF#_R from JLVDS.35 to JLVDS.33 01/27 32 Add pull down R40 10Kohm at VR_ON. For prevent burn issue For prevent leakage for CPU_CORE 01/27 25 Change D18 from SCA00000A00 to SC600001600 For ESD request 01/27 13,26,30,34 Change D57,D58,D59,DA6,DA9 from SCA00000G00 to SCA00001A00 For ESD request 01/27 15 Add pull down R148 2.2Kohm at HDMI_TXC-. For UMA HDMI level shift display compatibility issue 01/27 28 Change UL3 from SP050005W00 to SP050005V00 For ESD request 01/27 29 Change UA1 from SA00003QR00 to SA00003QR10 For Realtek update 01/27 32 Change R128 BOM structure from mount to un-mount. For EC update 01/27 32 Change R130 BOM structure from un-mount to mount. For EC update 01/27 32 Change U19 from SA00001J580 to SA00001J5A0. For EC update 02/01 30 Change JSPK pin define For common SPK material 02/01 16 Add D19 & R133 between +RTCVCC and RTCVREF. For prevent RTC empty then can not boot up issue 02/01 19 Change R77 from SD028100280 to SD028100380 For INTEL issue (pending interrupts from the PCH for unused HDMI ports) 02/01 05 Add C225 For prevent noise issue 02/04 22 Change L12 from SM010028480 to SHI00002K00 For CRT wave issue 02/04 28 Change LL1 from SHI00004T00 to SHI0000AA00 For package limitation, Realtek criteria, 2ND source reason 02/04 28 Change CL13 from SE000000I10 to SE107475K80 For package limitation, Realtek criteria, 2ND source reason D C C B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW PIR 0.2 TO 0.3 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 46 of 48 5 4 3 2 1 OBMBB!MB.7152Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/4!UP!2/1 OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF ........................................................................................................................................................ D C 02/23 15 Change R167 BOM structure from @ to IHDMI@. 02/23 15 Change R163 BOM structure from IHDMI@ to @. For reduce HDMI choke plan For reduce HDMI choke plan 02/23 15 Change R160 from SD028330180 (3.3K ohm) to SD034390180 (3.9K ohm). For reduce HDMI choke plan 02/23 15 Change L8,L9,L10,L11 BOM structure from IHDMI@ to @. For reduce HDMI choke plan 02/23 15 Change R157,R173,R175,R180,R182,R183,R187,R188 BOM structure from @ to IHDMI@. For reduce HDMI choke plan 02/23 22 Change L12 from SHI00002K00 (10UH +-20%) to SD008100B80 (1 ohm +-1% 0805). For CRT wave issue 02/23 16 Delete D19 & R133 For prevent RTC empty then can not boot up issue 02/23 23 Change U54,C2,C18 BOM structure to @. For reserve HDA power rail to +1.5V 02/23 26,34 Change SW2,SW4 from SN100000F00 to SN100002Y00 and add BOM structure @ at SW2. For cost concern 03/09 29,32 Add Net EC_MUTE# from EC pin 83 to codec Pin4 For system has abnormally noise after S3 resume. 03/09 29 Add pull Low RA45 4.7K ohm. For system has abnormally noise after S3 resume. 03/09 29 Change CA16 BOM structure to @. For system has abnormally noise after S3 resume. 03/11 22 Add L57. For prevent EMI and CRT wave issue. 03/11 25,30 Change U14,U15 from SA000033H00 to SA00002XX00. For sourcer suggestion. 03/11 25,30 Change ZZZ from DA60000GC00 to DAZ0CK00100. For Pre-MP phase. 03/11 06 Change U1 from SA00002XA00 to SA000035G00. For voltage drop issue. 03/11 34 Change R771,D2 BOM structure to @. For Pre-MP phase. 03/11 22 Add net name +3VS_VCCADAC_R For net nameing rule 03/15 34 Add R772 & C490 and net name LID_SW#_R For prevent ESD damage 03/15 22 Change L12 from SD008100B80 to SD014100B80. For package size 03/16 29 Change CA12.1, RA12.2, CA18.2 connect to GNDA For high frequency noise issue at S0 03/16 13 Add C231 For prevent noise coupling 03/17 35 Add C232,C234 For prevent noise coupling 03/17 31 Add CC9,CC10,RC22,RC24 For EMI request 03/17 31 Del RC2,RC3,CC7,CC8 For EMI request 03/20 13 Change C213 from SE070104Z80 to SE000000K80. For prevent noise coupling 03/20 13 Change C231 from SE071101J80 to SE000000K80. For prevent noise coupling 03/23 25 Change D18 BOM structure to @. For EMI remove D C B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/23 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW PIR 0.3 TO 1.0 Size Document Number Custom Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 1 47 of 48 OP!EBUF!!!!!!!!!!!!!!!!!!!QBHF!!!!!!!!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF ................................................................................................................................ 2009/10/20 45-54 Release 2009/12/21 39 Change PR92 to 42.2K ohm circuit modify 2009/12/21 40 circuit modify 2009/12/21 42 Change PR95 to 2.43K ohm,PR101,PC71,PC72 to unmount ,PR98 to 6.49K ohm Change PR136 to unmount,PR137 to mount,PC90 toSE024681J80 2009/12/21 43 Change PQ44 to unmount,PQ45 to mount EMI request 2009/12/28 43 Change PC111,PC114 to 68U DFB request 2009/12/29 37 Change PR31 and PR33 to19.6K ohm, PR34 to 8.66K ohm,PR40 to 7.87K ohm circuit modify 2009/12/29 38 Add PR139(0_0402_5%) EMI test request 2009/12/29 44 Change PH5 to SL200000500 circuit modify 2010/01/05 43 Change PR169,PR210,PC118 and PC150 to mount EMI request 2010/01/05 44 Change PR235 and PC163 to mount Change PR196 to 2.55K ohm,PR204 to 9.1K ohm circuit modify 2010/02/03 circuit modify EMI request 2010/02/03 38 Change PC24,PC25,PC26 to 10U_1206,PR67 to 2.2 ohm PC74 to mount,PC23 to 1000P EMI request Delete PR139 circuit modify 2010/02/03 39 Change PQ27 to DTC115EUA_SC70-3 EMI request 2010/02/26 37 2010/03/16 38 2010/03/18 40 2010/04/02 40 Add PC77 Change PR31,PR33 to 23.7K ohm,PR34,PR40 to 11.3K ohm Add PD6,PD7 Change PC24,PC25,PC26 to 4.7U_0805, PC75,PC76 to unmount, Thermal request EMI request Change PR247 to 47K ohm Modify GFX load line Change PR98 to 9.76K ohm circuit modify(cut in AON6718L) Compal Secret Data Security Classification Issued Date For PCB noise ossue 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. Power PIR Size Document Number Rev 1.0 NALAA LA-6041P M/B Date: Tuesday, April 13, 2010 Sheet 48 of 48 www.s-manuals.com
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