Compal LA 7202P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-7202P PWWHA Delhi 10R - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 44
| Download | |
| Open PDF In Browser | View PDF |
A B C D E 1 1 PWWHA Delhi 10R 2 2 LA-7202P REV 1.0 Schematic Intel Processor(Sandy Bridge) / PCH(Cougar Point) 2011-02-08 Rev 1.0 3 3 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size B Date: Document Number Rev 1.0 PWWHA LA-7202P M/B Friday, February 25, 2011 Sheet E 1 of 43 A B C D E Intel CPU Sandy Bridge Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1 rPGA-989 37.5mm*37.5mm Dual Channel page 5,6,7,8,9,10 CRT FDI X8 page 14 1 page 11,12 BANK 0, 1, 2, 3 1.5V DDRIII 1066/1333/1600 MT/s DMI X4 2.7GT/s 5GT/s USB/B Left 2IN1 RTS5137 USB port 0,1 page 24 USB Int. Camera USB port 10 page 27 USB port 11 page 13 5V 480MHz LVDS Conn. page 13 2 USB 5V 480MHz PCIe 1x 1.5V 5GT/s Intel PCH Cougar Point - M RJ45 RTL8105E 10/100M page 26 2 page 25 PCIeMini Card WLAN PCIe port 2 page 25 SATA port 0 PCIe 1x 5V 6GHz(600MB/s) 1.5V 5GT/s PCIe port 1 page 26 PCIeMini Card WiMax USB port 9 SATA HDD SATA port 1 page 24 FCBGA-989 25mm*25mm SATA port 2 5V 3GHz(300MB/s) SATA ODD SATA port 4 page 24 page 15,16,17,18,19,20,21,22,23 3 3 LPC BUS HD Audio 3.3V 24MHz 3.3V 33 MHz HDA Codec SPI ROM (4MB) page 15 Debug Port ALC259 ENE KB930 page 31 page 28 page 30 RTC CKT. page 16 Touch Pad page 32 Int.KBD Int. MIC Conn EC ROM (128KB) page 31 page 32 DC/DC Interface CKT. SPK Conn page 29 HP & MIC page 29 page 29 page 33 4 4 Power Circuit DC/DC page 34,35,36,37,38,39 ,40,41 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. page 32 A Compal Electronics, Inc. Compal Secret Data Security Classification Power/B DA40000XR10 B C D Title Block Diagram Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: W ednesday, March 02, 2011 Sheet E 2 of 43 5 4 3 2 DESIGN CURRENT 0.1A 1 +3VL B+ Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 5A +5VALW DESIGN CURRENT 2A +1.8VS DESIGN CURRENT 4A +5VS SUSP# SY8033BDBC SUSP D N-CHANNEL D SI4800 ODD_EN# DESIGN CURRENT 1.8A P-CHANNEL AO-3413 +5VS_ODD TPS51125ARGER Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW WOL_EN# P-CHANNEL AO-3413 DESIGN CURRENT 330mA +3V_LAN C C SUSP DESIGN CURRENT 4A N-CHANNEL +3VS LCD_ENVDD SI4800 P-CHANNEL AO-3413 DESIGN CURRENT 1.5A +LCD_VDD VR_ON ISL95831HRTZ-T Ipeak=94A, Imax=52A, Iocp min=122A DESIGN CURRENT 94A +CPU_CORE Ipeak=33A, Imax=21.5A, Iocp min=40A DESIGN CURRENT 33A +GFX_CORE Ipeak=17A, Imax=11.9A, Iocp min=19.23A DESIGN CURRENT 15A +1.05VS_VCCP SUSP# TPS51117RGYR B B VCCPPWRGD TPS51117RGYR Ipeak=6A, Imax=4.2A, Iocp min=7A DESIGN CURRENT 6A Ipeak=9A, Imax=6.3A, Iocp min=9.92A DESIGN CURRENT 10A +VCCSA SYSON +1.5V SUSP TPS51117RGYR N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU FDS6676AS SUSP N-CHANNEL DESIGN CURRENT 2A +1.5VS DESIGN CURRENT 1A +1.05V SI4800 +3V APL5930KAI-TRG 0.75VR_EN# A A DESIGN CURRENT 1.5A UP7711U8 +0.75VS Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Power Tree Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 3 of 43 A Voltage Rails B ( O MEANS ON +RTCVCC C E X MEANS OFF ) B+ +3VL +5VALW +1.5V +3VALW +5VS +3VS +1.8VS +VSB power plane 1 D +1.5VS 1 +1.05VS +0.75VS +CPU_CORE +GFX_CORE State BTO Option Table Function S0 O O O O O O S1 O O O O O O S3 O O O O O X O O O O X X S5 S4/ Battery only O O O X X X S5 S4/AC & Battery don't exist O X X X X X description SLOT1 explain WIMAX 10/100M WIMAX@ 8105E@ BTO 2 S5 S4/AC LAN MINI PCI-E SLOT Camera & Mic LAN Camera & Mic Giga Camera & Mic 8111E@ CAM@ FAN FAN S3 Power Saving Load Power Switch S3 Power Saving Load Power Switch PWM RPM 1.5V 1.5VS Old Sch. PWM@ RPM@ WPS3@ PS3@ New Sch. OLS@ NLS@ 2 PCH SM Bus Address 3 Power Device HEX Address +3VS DDR SO-DIMM 0 A0 H 1010 0000 b +3VS DDR SO-DIMM 1 A4 H 1010 0100 b +3VS Clock Generator D2 H 1101 0010 b +3VS WLAN/WIMAX 3 SIGNAL STATE EC SM Bus1 Address EC SM Bus2 Address Full ON SLP_S3# SLP_S4# SLP_S5# HIGH HIGH HIGH Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH +3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH S4 (Suspend to Disk) LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW 4 4 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet E 4 of 43 5 4 3 2 1 JCPUB 100 MHz PM_DRAM_PWRGD_R H_SNB_IVB# <19> H_SNB_IVB# C26 SNB_IVB# @ H_PWRGOOD 1 C488 T1 TP_SKTOCC# PAD AN34 SKTOCC# <30> PAD H_PECI +1.05VS_VCCP CATERR# H_PECI AN33 PECI 1 AL32 PROCHOT# H_THERMTRIP# AN32 A16 A15 DPLL_REF_SSCLK DPLL_REF_SSCLK# +1.05VS_VCCP SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] CLK_CPU_DPLL CLK_CPU_DPLL# R8 H_DRAMRST# AK1 A5 A4 SM_RCOMP_0 R1437 2 SM_RCOMP_1 R1438 2 SM_RCOMP_2 R1439 2 AP29 AP27 XDP_PRDY#_R XDP_PREQ#_R R1 1 R2 1 @ @ 2 0_0402_5% 2 0_0402_5% XDP_PRDY# XDP_PREQ# AR26 AR27 AP30 XDP_TCK_R XDP_TMS_R XDP_TRST#_R R4 1 R6 1 R7 1 @ @ @ 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% XDP_TCK XDP_TMS XDP_TRST# AR28 AP26 XDP_TDI_R XDP_TDO_R R8 1 R10 1 @ @ 2 0_0402_5% 2 0_0402_5% XDP_TDI XDP_TDO AP33 2 PM_DRAM_PWRGD_R 130_0402_5% BUF_CPU_RST# V8 AR33 PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# +3VALW TDI TDO R41 1 2 1K_0402_5% D R36 1 2 1K_0402_5% DBR# AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R R12 1 R13 1 R15 1 R18 1 @ @ @ @ 2 2 2 2 O A 4 PU/PD for JTAG signals Close to CPU side 1 1 2 D 3 2 G Q5 2N7002_SOT23 @ U1 H_PWRGOOD PBTN_OUT# CFG0 VGATE R35 R152 R37 R451 PLT_RST# R69 75_0402_5% 1 1 1 1 1 R40 @ @ @ @ @ 2 2 2 2 1K_0402_5%XDP_CPU_HOOK0 0_0402_5% XDP_CPU_HOOK1 1K_0402_5%XDP_CPU_HOOK2 0_0402_5% XDP_CPU_HOOK3 CLK_CPU_ITP CLK_CPU_ITP# XDP_CPU_HOOK6 2 1K_0402_5% XDP_DBRESET# C8 0.1U_0402_10V6K @ R155 43_0402_1% 1 2 BUF_CPU_RST# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS 1 2 XDP_TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 51_0402_5% 2 1 51_0402_5% XDP_TCK_R R31 2 1 51_0402_5% XDP_TRST#_R R32 2 1 51_0402_5% R209 0_0402_5% @ GND GND GND GND +FAN2 2 1 8 7 6 5 1 1 2 3 C14 1000P_0402_50V7K @ 4 5 GND GND B ACES_85204-0300N APL5607KI-TRG_SO8 C15 RPM@ 10U_0805_10V6K RPM@ 2 @ 1 2 3 R14 10K_0402_5% RPM@ 1 +3VS 2 FAN_SPEED1 2 +3VS C13 0.01U_0402_25V7K @ R3 10K_0402_5% PWM@ <30> JFAN <30> FAN_SPEED1 2 +5VS 1A R154 1 2 1 2 0_0603_5% PWM@ 1 2 3 4 FANPWM FANPWM +FAN1 C6 0.01U_0402_25V7K @ +5VS 40 mil 1 +FAN1 ACES_85204-0400N @ PWM@ D57 1SS355_SOD323-2 2 2 D86 BAS16_SOT23-3 PWM@ C3 10U_0805_10V6K PWM@ 1 1 2 3 4 1000P_0402_50V7K 1 C4 PWM@ 1 10U_0805_10V6K 2 C379 PWM@ A Close to Connector MOLEX 52435-2671 2 74AHC1G125GW_SOT353-5 EN VIN VOUT VSET JFAN2 2 1 27 28 1 2 BUFO_CPU_RST# 2 R30 1 XDP_PREQ# XDP_PRDY# 1 2 4 R29 XDP_TDO 2 <17,30> PBTN_OUT# <10> CFG0 <17,30,41> VGATE <16> CLK_CPU_ITP <16> CLK_CPU_ITP# +1.05VS_VCCP 10mil 1 JXDP @ XDP_BPM#2 XDP_BPM#3 1 0.1U_0402_16V4Z C84 +1.05VS_VCCP GND 1 2 3 4 +FAN2 S +3VS IN XDP_TDI_R 01/24 pin define change by Thermal C12 10U_0805_10V6K RPM@ Buffered Reset to CPU 5 1 51_0402_5% 1A XDP_BPM#0 XDP_BPM#1 U3 2 FAN Control Circuit (RPM and PWM) XDP Connector PLT_RST# <19,25,26,30,31> R28 +5VS 3 SUSP +1.05VS_VCCP XDP_TMS_R R339 200_0402_5% <30> EN_DFAN1 OUT XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 R340 39_0402_5% @ B A 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% @ PM_SYS_PWRGD_BUF 2 0_0402_5% WPS3@ +3VS XDP_DBRESET# <17> C BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] Sandy Bridge_rPGA_Rev0p61 1 B <9,25,33,40> SUSP VCC XDP_DBRESET# 2 U10 74AHC1G09GW_TSSOP5 PS3@ 5 1 R384 1 OE# Routed as a single daisy chain 2 2 <17> DRAMPWROK 3 CLK_CPU_DPLL DDR3 Compensation Signals Layout Note:Place these resistors near Processor 1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1% +1.5V_CPU 1 P R312 0_0402_5% 1 2 PS3@ 2 2 1K_0402_5% H_DRAMRST# <7> G C93 0.1U_0402_16V4Z PS3@ TCK TMS TRST# JTAG & BPM PM_SYS_PWRGD_BUF 1 R454 C AM34 H_PWRGOOD <20> H_PWRGOOD PRDY# PREQ# PWR MANAGEMENT H_PM_SYNC <17> H_PM_SYNC 1 R42 1 THERMTRIP# Remove R14(o ohm) for HW Review demand PLT_RST# CLK_CPU_DPLL# H_PWRGOOD 1 10K_0402_5% <17,30> PM_PWROK Stuff R41 and R42 if do not support eDP CLK_CPU_DMI <16> CLK_CPU_DMI# <16> 1 2 2 H_PROCHOT#_R 56_0402_5% H_PROCHOT# 1 62_0402_5% 2 <20> H_THERMTRIP# R51 AL33 R450 <30,35> H_PROCHOT# R47 H_CATERR# CLK_CPU_DMI CLK_CPU_DMI# 120 MHz DDR3 MISC T2 THERMAL D A28 A27 BCLK BCLK# 2 1000P_0402_50V7K 2 CLOCKS 1 C487 MISC PROC_SELECT# @ 1000P_0402_50V7K 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_JTAG/XDP/FAN Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 5 of 43 5 4 3 2 1 +1.05VS_VCCP D B <17> <17> <17> <17> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 <17> <17> <17> <17> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <17> <17> <17> <17> <17> <17> <17> <17> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <17> <17> <17> <17> <17> <17> <17> <17> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 B28 B26 A24 B23 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC <17> FDI_FSYNC0 <17> FDI_FSYNC1 FDI_FSYNC0 FDI_FSYNC1 J18 J17 <17> FDI_INT FDI_INT H20 <17> FDI_LSYNC0 <17> FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 J19 H17 +1.05VS_VCCP R9 1 2 24.9_0402_1% +1.05VS_VCCP R33 2 1 10K_0402_5% EDP_COMP Reserve R33 for HW Review demand eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_INT FDI0_LSYNC FDI1_LSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD C15 D15 eDP_AUX eDP_AUX# C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] Sandy Bridge_rPGA_Rev0p61 PCI EXPRESS* - GRAPHICS DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 B27 B25 A25 B24 DMI <17> <17> <17> <17> DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 Intel(R) FDI DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 eDP C <17> <17> <17> <17> PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_COMP 2 R34 24.9_0402_1% JCPUA 1 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 m ohm (12 mils) D C M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] B @ A A 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_DMI/PEG/FDI Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 6 of 43 5 4 3 2 JCPUC <11> DDR_A_D[0..63] 1 JCPUD <12> DDR_B_D[0..63] B <11> DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] DDR_A_CAS# DDR_A_RAS# DDR_A_WE# <11> DDR_A_CAS# <11> DDR_A_RAS# <11> DDR_A_WE# AE8 AD9 AF9 SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 SA_CLK[2] SA_CLK#[2] SA_CKE[2] AB4 AA4 W9 SA_CLK[3] SA_CLK#[3] SA_CKE[3] SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] DDRA_CLK0 <11> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRA_CLK1 <11> DDRA_CLK1# <11> DDRA_CKE1 <11> AB3 AA3 W10 AK3 AL3 AG1 AH1 DDRA_SCS0# DDRA_SCS1# AH3 AG3 AG2 AH2 DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# <11> DDRA_SCS1# <11> DDRA_ODT0 <11> DDRA_ODT1 <11> DDR_A_DQS#[0..7] DDR_A_DQS#0 C4 G6 DDR_A_DQS#1 DDR_A_DQS#2 J3 M6 DDR_A_DQS#3 AL6 DDR_A_DQS#4 AM8 DDR_A_DQS#5 AR12 DDR_A_DQS#6 AM15 DDR_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DQS[0..7] <11> <11> DDR_A_MA[0..15] <11> SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_CAS# SA_RAS# SA_WE# Sandy Bridge_rPGA_Rev0p61 <12> DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 <12> DDR_B_CAS# <12> DDR_B_RAS# <12> DDR_B_WE# DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AA9 AA7 R6 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# AA10 AB8 AB9 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CLK[0] SB_CLK#[0] SB_CKE[0] AE2 AD2 R9 DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 SB_CLK[2] SB_CLK#[2] SB_CKE[2] AB2 AA2 T9 SB_CLK[3] SB_CLK#[3] SB_CKE[3] SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] DDR SYSTEM MEMORY B C C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 DDR SYSTEM MEMORY A D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# AD3 AE3 AD6 AE6 DDRB_SCS0# DDRB_SCS1# AE4 AD4 AD5 AE5 DDRB_ODT0 DDRB_ODT1 D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 Sandy Bridge_rPGA_Rev0p61 @ DDRB_CLK1 <12> DDRB_CLK1# <12> DDRB_CKE1 <12> D AA1 AB1 T10 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] DDRB_CLK0 <12> DDRB_CLK0# <12> DDRB_CKE0 <12> DDRB_SCS0# <12> DDRB_SCS1# <12> DDRB_ODT0 <12> DDRB_ODT1 <12> DDR_B_DQS#[0..7] DDR_B_DQS[0..7] <12> C <12> DDR_B_MA[0..15] <12> B @ 1 +1.5V R465 1K_0402_5% PS3@ 2 R466 0_0402_5% 1 2 WPS3@ H_DRAMRST# D S 3 2 <5> H_DRAMRST# 2 1 R467 1K_0402_5% 2 SM_DRAMRST# <11,12> A 1 A G R464 4.99K_0402_1% DDR3_DRAMRST#_R 1 Q14 BSS138_NL_SOT23-3 PS3@ <16> DRAMRST_CNTRL_PCH 1 R463 2 DRAMRST_CNTRL 0_0402_5% PS3@ 1 2 Compal Electronics, Inc. Compal Secret Data Security Classification C140 0.047U_0402_25V6K PS3@ 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_DDR3 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 7 of 43 5 +CPU_CORE 4 POWER JCPUF 94A (Quad Core 45W) 53A (SV 35W) +1.05VS_VCCP PEG AND DDR VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 22U_0805_6.3V6M 1 C146 C144 1 22U_0805_6.3V6M 1 C143 C141 1 22U_0805_6.3V6M 1 C137 C136 1 22U_0805_6.3V6M 1 C135 C134 1 22U_0805_6.3V6M 1 C133 C142 1 2 2 2 2 2 2 2 2 2 2 22U_0805_6.3V6M C147 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M +CPU_CORE Decoupling: 4X 470U (4m ohm), 16X 22U, 10X 10U 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 C145 Bottom Socket Cavity +CPU_CORE 2 2 22U_0805_6.3V6M 10U_0805_10V6K C101 1 C102 1 10U_0805_10V6K C103 1 C104 1 10U_0805_10V6K C105 1 C106 1 C107 10U_0805_10V6K 1 C108 1 10U_0805_10V6K 1 C109 C110 1 C111 1 330U_D2_2V_Y ESR 9mohm Bottom Socket Cavity x 5 1 1 C10 + C11 + 330U_D2_2V_Y 2 2 2 10U_0805_10V6K 2 2 10U_0805_10V6K 2 2 2 10U_0805_10V6K 2 10U_0805_10V6K 2 2 10U_0805_10V6K @ 2 10U_0805_10V6K 2 C Top Socket Edge +CPU_CORE J23 22U_0805_6.3V6M 1 C151 2 1 +1.05VS_VCCP +1.05VS_VCCP 1 1 R70 130_0402_5% C130 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C129 2 1 C124 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C123 2 1 22U_0805_6.3V6M C122 2 22U_0805_6.3V6M 1 C121 2 1 C125 @ 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M R68 75_0402_5% AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT 2 2 SVID Top Socket Cavity VIDALERT# VIDSCLK VIDSOUT 1 R67 1 R63 1 R66 2 2 43_0402_1% 2 0_0402_5% 0_0402_5% VR_SVID_ALRT# <41> VR_SVID_CLK <41> VR_SVID_DAT <41> +CPU_CORE B 22U_0805_6.3V6M Pull high resistor on VR side C158 1 C150 2 1 2 22U_0805_6.3V6M C128 22U_0805_6.3V6M 1 C127 2 1 C120 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C118 2 22U_0805_6.3V6M 1 22U_0805_6.3V6M C119 2 1 C117 2 1 2 22U_0805_6.3V6M +CPU_CORE 2 Bottom Socket Edge R64 100_0402_1% +CPU_CORE Close to CPU AJ35 VCCSENSE_R AJ34 VSSSENSE_R R65 1 R52 1 1 2 0_0402_5% 2 0_0402_5% VCCSENSE <41> VSSSENSE <41> C2 330U_D2_2V_Y 1 VCC_SENSE VSS_SENSE VCCIO_SENSE VCCIO_SENSE R62 100_0402_1% <40> 2 C5 1 + C7 2 1 + C9 2 330U_D2_2V_Y 1 + C1 2 + 2 330U_D2_2V_Y 2 A R105 100_0402_1% @ 1 R102 0_0402_5% +1.05VS_VCCP 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 5 + 1 2 VSS_SENSE_VCCIO B10 A10 2 VCCIO_SENSE VSSIO_SENSE Close to CPU Sandy Bridge_rPGA_Rev0p61 330U_D2_2V_Y 1 330U_D2_2V_Y 1 A VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 D C159 SENSE LINES B 1 TOP Socket Cavity x 7 VCCIO40 CORE SUPPLY C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 2 +1.05VS_VCCP Decoupling: 2X 330U (6m ohm), 12X 22U 8.5A D AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 3 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. @ 4 3 2 Title Sandy Bridge_POWER-1 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 8 of 43 5 4 3 2 +GFX_CORE Decoupling: 1X 560U (10m ohm), 12X 22U 2 +GFX_CORE +GFX_CORE POWER Change C873 from 330uF to 560uF for power issue JCPUG R74 Close 100_0402_1% 2 1 C342 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M Bottom Socket Edge 1 22U_0805_6.3V6M C344 2 Top Socket Cavity 1 C345 2 1 C346 2 22U_0805_6.3V6M 22U_0805_6.3V6M 1 C347 2 1 C348 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M Top Socket Edge 22U_0805_6.3V6M C349 @ 1 22U_0805_6.3V6M C350 @ 2 1 2 C351 @ C391 @ 2 22U_0805_6.3V6M +1.8VS 1 1 2 22U_0805_6.3V6M VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U R76 2 1 0_0805_5% B 1.2A +1.8VS_VCCPLL 10U_0805_10V6K 1 C185 @+ C186 2 330U_B2_2.5VM_R15M 1 2 C206 1 1 2 2 1U_0402_6.3V6K B6 A6 A2 VCCPLL1 VCCPLL2 VCCPLL3 C230 1U_0402_6.3V6K 1 AL1 +V_SM_VREF_CNT R486 5A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 C148 2 @ AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 1 +1.5VS @ 2 +V_SM_VREF 3 1 Q2 @ AP2302GN-HF_SOT23-3 2 1 1 SENSE LINES Sandy Bridge_rPGA_Rev0p61 SM_VREF RUN_ON_CPU1.5VS3 2 +1.5V_CPU 1K_0402_5% R122 R252 1K_0402_5% +1.5V_CPU Decoupling: 1X 330U (17m ohm), 6X 10U 2 C341 2 2 +1.5V_CPU 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 1 C114 1 1 C115 2 C116 2 10U_0805_10V6K 1 1 C149 2 C154 2 10U_0805_10V6K 1 C155 2 1 + C875 330U_2.5V_M_R17 2 2 ESR 17mohm 10U_0805_10V6K C +VCCSA Decoupling: 1X 330U (17m ohm), 4X 10U VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 M27 M26 L26 J26 J25 J24 H26 H25 10U_0805_10V6K C100 1 C447 2 C476 2 1 C477 @ 2 10U_0805_10V6K 2 +VCCSA 0 0.90 V 1 0 1 0.80 V + C877 330U_2.5V_M_R17 @ ESR 17mohm 2 1 0 0.75 V 1 1 0.65 V 2VCCSA_SENSE 0_0402_5% 1 R253 1 VCCSA_VID1 0 10U_0805_10V6K 1 VCCSA_VID0 +VCCSA Bottom Socket Cavity 6A 10U_0805_10V6K For Sandy Bridge Bottom Socket Edge VCCSA_SENSE VCCSA_VID0 FC_C22 VCCSA_VID1 H23 VCCSA_SENSE R95 1 0_0402_5% C22 VCCSA_VID0 C24 VCCSA_SENSE <39> B 2 @ VCCSAP_VID1 <39> 2 22U_0805_6.3V6M 1 1 JUMP_43X118 R114 IF WPS3@, short PJ30. R119 @ @ 10K_0402_5% 1 10K_0402_5% +1.5V_CPU 1 2 22U_0805_6.3V6M 22U_0805_6.3V6M C343 C338 PJ32 1 2 2 1 D IF PS3@, short PJ32. R75 100_0402_1% R111 0_0402_5% 2 1 0.1U_0402_16V4Z Bottom Socket Cavity C271 VCC_AXG_SENSE <41> VSS_AXG_SENSE <41> +V_SM_VREF should have 20 mil trace width 100K_0402_5% 2 1 VCC_AXG_SENSE VSS_AXG_SENSE AK35 AK34 1 22U_0805_6.3V6M C267 VAXG_SENSE VSSAXG_SENSE 2 1 VREF C266 DDR3 -1.5V RAILS 22U_0805_6.3V6M 33A SA RAIL 2 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 MISC + AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 GRAPHICS 1 1.8V RAIL ESR 10mohm C873 560U_2.5V_M_R17 to CPU 1 Bottom Socket Edge D C 1 +1.5V PJ30 +1.5V_CPU 2 +1.5V @ 2 1 1 JUMP_43X118 C211 1 Q33 1 R449 470_0805_5% @ 1 2 3 4 2 C179 10U_0805_10V4K @ S S S G @ D D D D 8 7 6 5 FDS6676AS_SO8 RUN_ON_CPU1.5VS3 1 3 1 C210 1 Vgs=10V,Id=14.5A,Rds=6mohm 2010/09/03 4 3 +VSB R420 820K_0402_5% @ 2 SUSP SUSP Q46A 2N7002DW-T/R7_SOT363-6 @ <5,25,33,40> A Compal Electronics, Inc. 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 2 Compal Secret Data Security Classification Issued Date 1 1 A 4 5 Q46B 2N7002DW-T/R7_SOT363-6 @ 2 C472 0.1U_0402_25V6 @ SUSP R455 @ 1 2 220K_0402_5% 6 C212 1 PS3@ 2 0.1U_0402_16V4Z PS3@ 2 0.1U_0402_16V4Z PS3@ 2 0.1U_0402_16V4Z PS3@ 2 0.1U_0402_16V4Z 2 C213 1 2 Title Sandy Bridge_POWER-2 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 9 of 43 4 B @ RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD33 RSVD34 RSVD35 CFG2 1 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 R254 1K_0402_1% @ AT26 AM33 AJ27 2 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG0 T5 PAD T6 PAD T7 PAD T11 PAD T12 PAD T15 PAD T18 PAD T16 PAD T19 PAD T21 PAD T20 PAD T44 PAD T45 PAD T46 PAD T47 PAD T26 PAD T27 PAD D PEG Static Lane Reversal - CFG2 is for the 16x RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 CFG2 * 1: Normal Operation; Lane # socket pin map definition definition matches 0:Lane Reversed AJ26 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 SA_DIMM_VREFDQ CPU_RSVD6 CPU_RSVD7 B4 D1 RSVD6 RSVD7 SB_DIMM_VREFDQ R115 1K_0402_1% R116 1K_0402_1% F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 J20 B18 A19 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 VCCIO_SEL J15 AR35 AT34 AT33 AP35 AR34 CFG4 R255 1K_0402_1% @ RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 B34 A33 A34 B35 C35 Embedded Display Port Presence Strap * AJ32 AK32 CFG4 AH27 1 : Disabled; No Physical Display Port attached to Embedded Display Port C 0 : Enabled; An external Display Port device is connected to the Embedded Display Port T28 PAD CFG6 RSVD54 RSVD55 AN35 AM35 CLK_RES_ITP <16> CLK_RES_ITP# <16> CFG5 1 AJ31 AH31 AJ33 AH33 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 1 PAD PAD PAD PAD R257 1K_0402_1% @ RSVD56 RSVD57 RSVD58 AT2 AT1 AR1 R256 1K_0402_1% @ 2 T22 T24 T25 T23 1 <5> 2 F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 2 VSS VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 1 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 (CFG[17:0] internal pull high to VCCIO) L7 AG7 AE7 AK2 W8 RSVD27 KEY B1 PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled Sandy Bridge_rPGA_Rev0p61 *10: x8, x8 - Device 1 function 1 enabled ; function 2 @ CFG[6:5] Sandy Bridge_rPGA_Rev0p61 B disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled @ CFG7 1 Sandy Bridge_rPGA_Rev0p61 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 2 C VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 1 CFG Straps for Processor JCPUE 1 D VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 2 JCPUI AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 2 JCPUH AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 3 RESERVED 5 2 R258 1K_0402_1% @ PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Sandy Bridge_GND/RSVD/CFG Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Sheet Friday, February 25, 2011 1 10 of 43 4 +1.5V JDDRL DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 Close to JDDRL.1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDRA_CKE0 <7> DDRA_CKE0 C DDR_A_BS2 <7> DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDRA_CLK0 DDRA_CLK0# <7> DDRA_CLK0 <7> DDRA_CLK0# DDR_A_MA10 DDR_A_BS0 <7> DDR_A_BS0 DDR_A_WE# DDR_A_CAS# <7> DDR_A_WE# <7> DDR_A_CAS# DDR_A_MA13 DDRA_SCS1# <7> DDRA_SCS1# DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 B DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 R90 1 2 10K_0402_5% A +3VS 0.1U_0402_16V4Z 2.2U_0603_6.3V6K 2 C182 1 1 1 +0.75VS R91 10K_0402_5% 2 2 C181 5 205 207 GND1 GND2 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 BOSS1 BOSS2 206 208 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_D6 DDR_A_D7 <7> <7> <7> DDR_A_D12 DDR_A_D13 SM_DRAMRST# D SM_DRAMRST# <7,12> +1.5V DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 R79 1K_0402_1% +VREF_DQA DDR_A_D22 DDR_A_D23 R81 1K_0402_1% DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDRA_CKE1 DDRA_CKE1 <7> DDR_A_MA15 DDR_A_MA14 C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDRA_CLK1 DDRA_CLK1# DDR_A_BS1 DDR_A_RAS# DDRA_SCS0# DDRA_ODT0 DDRA_ODT1 DDRA_CLK1 <7> DDRA_CLK1# <7> +1.5V DDR_A_BS1 <7> DDR_A_RAS# <7> DDRA_SCS0# <7> DDRA_ODT0 <7> DDRA_ODT1 R80 1K_0402_1% <7> +VREF_CAA DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 R82 1K_0402_1% C161 1 2 C162 0.1U_0402_16V4Z DDR_A_D40 DDR_A_D41 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD W E# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT <7> DDR_A_DQS#[0..7] 2.2U_0603_6.3V6K DDR_A_D34 DDR_A_D35 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_A_DQS[0..7] 1 DDR_A_D2 DDR_A_D3 DDR3 SO-DIMM A Reverse Type 2 2 DDR_A_D4 DDR_A_D5 1 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2 2.2U_0603_6.3V6K 0.1U_0402_16V4Z D C157 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 1 B 2 Layout Note: Place near JDDRL close to JDDRL.126 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA Layout Note: Place near JDDRL1.203 and 204 +1.5V DDR_A_D52 DDR_A_D53 +1.5V @ C218 1 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 + C156 DDR_A_D0 DDR_A_D1 1 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 1 1 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 2 +VREF_DQA 3 1 +1.5V 2 5 +0.75VS 2 390U_2.5V_M_R10 C166 1 2 10U_0603_6.3V6M C168 1 2 10U_0603_6.3V6M C171 1 2 10U_0603_6.3V6M C174 1 2 10U_0603_6.3V6M C176 1 2 10U_0603_6.3V6M C178 1 2 10U_0603_6.3V6M C164 1 2 0.1U_0402_16V4Z C167 1 2 0.1U_0402_16V4Z C170 1 2 0.1U_0402_16V4Z C173 1 2 0.1U_0402_16V4Z C165 1 2 10U_0603_6.3V6M C169 2 1 1U_0402_6.3V6K C172 2 1 1U_0402_6.3V6K C175 2 1 1U_0402_6.3V6K C177 2 1 1U_0402_6.3V6K A PM_SMBDATA PM_SMBCLK PM_SMBDATA <12,16,25> PM_SMBCLK <12,16,25> +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date FOX_AS0A626-U2SN-7F_204P @ Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title DDRIII-SODIMM0 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 11 of 43 A B +1.5V C D E +1.5V JDDRH Close to JDDRH.1 DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDRB_CKE0 <7> DDRB_CKE0 2 DDR_B_BS2 <7> DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDRB_CLK0 DDRB_CLK0# <7> DDRB_CLK0 <7> DDRB_CLK0# DDR_B_MA10 DDR_B_BS0 <7> DDR_B_BS0 DDR_B_WE# DDR_B_CAS# <7> DDR_B_WE# <7> DDR_B_CAS# DDR_B_MA13 DDRB_SCS1# <7> DDRB_SCS1# DDR_B_D37 DDR_B_D36 DDR_B_DQS#4 DDR_B_DQS4 3 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 R98 1 2 10K_0402_5% 4 +3VS C207 1 0.1U_0402_16V4Z 2.2U_0603_6.3V6K 2 C208 @ 1 R99 2 10K_0402_5% 1 @ 2 +0.75VS 205 207 GND1 GND2 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 BOSS1 BOSS2 206 208 DDR_B_D12 DDR_B_D13 SM_DRAMRST# <7> <7> <7> DDR_B_MA[0..15] 1 <7> SM_DRAMRST# <7,11> DDR_B_D14 DDR_B_D15 +1.5V DDR_B_D20 DDR_B_D21 R83 1K_0402_1% DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 +VREF_DQB DDR_B_DQS#3 DDR_B_DQS3 R84 1K_0402_1% DDR_B_D30 DDR_B_D31 DDRB_CKE1 DDRB_CKE1 <7> DDR_B_MA15 DDR_B_MA14 2 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 DDRB_CLK1# DDR_B_BS1 DDR_B_RAS# DDRB_SCS0# DDRB_ODT0 DDRB_ODT1 DDRB_CLK1 <7> DDRB_CLK1# <7> +1.5V DDR_B_BS1 <7> DDR_B_RAS# <7> DDRB_SCS0# <7> DDRB_ODT0 <7> R86 1K_0402_1% DDRB_ODT1 <7> +VREF_CAB DDR_B_D32 DDR_B_D33 R94 1K_0402_1% C187 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 1 2 C188 1 3 2 Layout Note: Place near JDDRH Layout Note: Place these 4 Caps near Command and Control signals of DIMMB Layout Note: Place near JDDRH.203 and 204 Close to JDDRH.126 +1.5V +1.5V DDR_B_D52 DDR_B_D53 DDR_B_D50 DDR_B_D51 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 C192 1 2 10U_0603_6.3V6M C194 1 2 10U_0603_6.3V6M C197 1 2 10U_0603_6.3V6M C200 1 2 10U_0603_6.3V6M C202 1 2 10U_0603_6.3V6M C204 1 2 10U_0603_6.3V6M +0.75VS C190 1 2 0.1U_0402_16V4Z C193 1 2 0.1U_0402_16V4Z C196 1 2 0.1U_0402_16V4Z C199 1 2 0.1U_0402_16V4Z C191 1 2 10U_0603_6.3V6M C195 2 1 1U_0402_6.3V6K C198 2 1 1U_0402_6.3V6K C201 2 1 1U_0402_6.3V6K C203 2 1 1U_0402_6.3V6K 4 PM_SMBDATA PM_SMBCLK PM_SMBDATA <11,16,25> PM_SMBCLK <11,16,25> +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date FOX_AS0A626-UASN-7F_204P @ A DDR_B_D[0..63] 0.1U_0402_16V4Z DDR_B_D40 DDR_B_D41 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD W E# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT DDR_B_DQS[0..7] 2.2U_0603_6.3V6K DDR_B_D34 DDR_B_D35 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_B_DQS#[0..7] 1 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D6 DDR_B_D7 2 DDR_B_D8 DDR_B_D9 DDR_B_DQS#0 DDR_B_DQS0 1 DDR_B_D2 DDR_B_D3 2 Reverse Type DDR3 SO-DIMM B DDR_B_D4 DDR_B_D5 2 2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 0.1U_0402_16V4Z 2.2U_0603_6.3V6K 1 C184 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 2 1 C183 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 1 DDR_B_D0 DDR_B_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 +VREF_DQB Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C D Title DDRIII-SODIMM1 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet E 12 of 43 A B C D E F +LCD_VDD USB20_P11_R 1 R108 100K_0402_5% +3VS 2 4 R107 150_0603_5% 2 <19> USB20_N11 +3VS 6 <19> USB20_P11 1 @ 2 R78 0_0402_5% L55 CAM@ 1 1 2 2 H 1 Reserve for EMI request G 3 C229 0.01U_0402_25V7K LCD_EDID_DATA <18> LCD_EDID_DATA 5 R120 47K_0402_5% W=60mils 1 C233 0.1U_0402_16V4Z 2 R112 100K_0402_5% 2 Close to LVDS Connector +LCD_VDD 2 Q1B 2N7002DW-T/R7_SOT363-6 1 RB751V40_SC76-2 1 Q17 AO3413_SOT23 2 1 4 LED_PWM 1 2 UMA_ENVDD <18> UMA_ENVDD D2 W=60mils 2 1 2 R109 2 LCDPWR_GATE 1 47K_0402_5% 1 LCD_EDID_CLK <18> LCD_EDID_CLK <18> PCH_PWM 2 0_0402_5% 1 1 @ R96 C228 0.1U_0402_16V7K 2 3 Q1A 2N7002DW-T/R7_SOT363-6 1 USB20_N11_R 3 G 3 D 4 WCM-2012-900T_0805 S 1 LCD/PANEL BD. Conn. W=20mils CAM@ 1 2+3VS_LVDS_CAM R388 0_0603_5% +3VS CAM@ 0.1U_0402_16V4Z 1 2 C225 2 2 D84 @ JLVDS 31 32 33 34 G1 G2 G3 G4 Pin13 is GND pin but LVDS cable is NC. 3 @ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 3 USB20_N11_R USB20_P11_R PACDN042Y3R_SOT23-3 INT_MIC_CLK INT_MIC_DATA INT_MIC_CLK <28> INT_MIC_DATA <28> 1.5A +LCD_VDD_R 1 +3VS LCD_EDID_CLK LCD_EDID_DATA 2 For EMI LCD_TXOUT0- <18> LCD_TXOUT0+ <18> LCD_TXOUT1- <18> LCD_TXOUT1+ <18> 1 @ C231 680P_0402_50V7K 2 L15 2 1 0_0805_5% C226 0.1U_0402_16V4Z 1 2 +LCD_VDD C227 4.7U_0805_10V4Z 1 2 C232 0.1U_0402_16V4Z LCD_TXOUT2- <18> LCD_TXOUT2+ <18> LCD_TXCLK- <18> LCD_TXCLK+ <18> LED_PWM BKOFF#_R D1 2 RB751V40_SC76-2 2 10K_0402_5% 1 1 R113 +LCD_INV ACES_88341-3001 1 C234 68P_0402_50V8J 2 BKOFF# <30> 3 B+ Rated Current MAX:600mA L2 2 1 1 FBMA-L11-201209-221LMA30T_0805 C235 0.1U_0402_25V6 2 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Title LVDS Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 G Sheet 13 H of 43 A B C D E D4 @ D5 1 @ 1 1 CRT CONNECTOR D3 @ +3VS If=1A +5VS +CRT_VCC_R +CRT_VCC D6 1 1 RB491D_SOT23-3 3 1 <18> UMA_CRT_R L3 1 2 NBQ100505T-800Y_0402 CRT_R_L <18> UMA_CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L <18> UMA_CRT_B L5 1 2 NBQ100505T-800Y_0402 40 mils F1 2 3 2 DAN217_SC59 3 DAN217_SC59 2 3 2 DAN217_SC59 2 1 1.1A_6V_MINISMDC110F-2 C237 0.1U_0402_16V4Z 2 @ CRT_B_L JCRT 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 2 2 C241 2 1 C242 2 1 C243 2 CRT_R_L 2.2P_0402_50V8C 2 C240 1 2.2P_0402_50V8C C239 1 2.2P_0402_50V8C C238 1 2.2P_0402_50V8C 2.2P_0402_50V8C 2 1 150_0402_1% 2 1 150_0402_1% 2 1 150_0402_1% 1 2.2P_0402_50V8C T76 PAD R138 R139 R140 1 CRT_DDC_DAT CRT_G_L HSYNC CRT_B_L +CRT_VCC VSYNC T77 PAD CRT_DDC_CLK 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 @ G G 16 17 ALLTO_C10532-11505-L_15P-T 2 2 +CRT_VCC 2 0.1U_0402_16V4Z 2 R141 1 10K_0402_5% 4 D_CRT_HSYNC 1 L6 2 10_0402_5% D_CRT_VSYNC 1 L7 2 10_0402_5% +CRT_VCC HSYNC 5 1 3 2 A 4 Y G <18> UMA_CRT_VSYNC U7 SN74AHCT1G125GW _SOT353-5 3 C245 @ VSYNC 1 2 1 C246 @ 2 10P_0402_50V8J U6 SN74AHCT1G125GW _SOT353-5 10P_0402_50V8J Y G A P OE# 2 <18> UMA_CRT_HSYNC P OE# 5 1 1 C244 3 3 +CRT_VCC 2 2 +3VS 5 Q205B 4 <18> UMA_CRT_DATA 1 C282 33P_0402_50V8K 2 @ 1 1 2 Q205A 1 <18> UMA_CRT_CLK R159 4.7K_0402_5% 1 R153 4.7K_0402_5% CRT_DDC_CLK 6 2N7002DW -T/R7_SOT363-6 CRT_DDC_DAT 3 2N7002DW -T/R7_SOT363-6 C285 33P_0402_50V8K 2 @ C284 470P_0402_50V8J @ 1 1 2 C283 470P_0402_50V8J 2 @ 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title CRT Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet E 14 of 43 5 4 3 2 1 U2A 2 3 iME Setting. R293 1 20K_0402_5% JME 1 2PCH_SRTCRST# OSC NC OSC 1 4 32.768KHZ_12.5PF_Q13MC14610002 2 1 C205 15P_0402_50V8J @ 2 C248 2 1U_0402_6.3V6K 1 15P_0402_50V8J NC R286 1 <28> AZ_BITCLK_HD Integrated SUS 1.05V VRM Enable High - Enable Internal VRs PCH_INTVRMEN (must be always pulled high) 2 33_0402_5% <28> PCH_SPKR R142 1 <28> AZ_RST_HD# +RTCVCC 2 33_0402_5% R118 1 +3VS 2 1K_0402_5% RTCX2 PCH_RTCRST# D20 RTCRST# PCH_SRTCRST# G22 SRTCRST# SM_INTRUDER# K22 PCH_INTVRMEN C17 INTRUDER# N34 HDA_BCLK AZ_SYNC L34 HDA_SYNC PCH_SPKR T10 SPKR AZ_RST# K34 HDA_RST# HDA_SDIN1 PCH_INTVRMEN C34 HDA_SDIN2 PCH_SPK High = Enabled (No Reboot) Low = Disabled (Default) @ 2 R273 +3VALW 1 1K_0402_5% <28> AZ_SDOUT_HD R289 1 2 33_0402_5% <30> PWRME_CTRL# R580 1 2 0_0402_5% A34 AZ_SDOUT A36 SERIRQ HDA_SDIN0 G34 PCH_SPKR HDA_SDIN3 HDA_SDO +3VALW CR_CPPE# CR_CPPE# HDA_SDO ME debug mode, this signal has a weak internal pull down = Disable (default) *Low High = Enable (flash descriptor security overide) C N32 J3 T37 PAD PCH_JTAG_TMS H7 T38 PAD PCH_JTAG_TDI K5 JTAG_TDI T39 PAD PCH_JTAG_TDO H1 JTAG_TDO JTAG_TMS down L=>On Die PLL is supplied by 1.8V Need to pull high for Huron River platform 2 R284 +3VALW 1 1K_0402_5% PCH_SPICLK T3 PCH_SPICS# Y14 SA000041P00 AZ_SYNC 4M Byte +3VS AD7 AD5 AH5 AH4 SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATAICOMPO SATAICOMPI 2 1M_0402_5% U13 PCH_SPICS# PCH_SPIDO 1 2 3 4 BSS138_NL_SOT23-3 @ 1 2 R285 0_0402_5% CS# DO WP# GND 1 VCC HOLD# CLK DI 8 7 6 5 SATA3RBIAS LPC_FRAME# <30,31> +3VS SERIRQ SERIRQ SERIRQ <30,31> SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 SATA_PRX_C_DTX_N0 <24> SATA_PRX_C_DTX_P0 <24> SATA_PTX_DRX_N0 <24> SATA_PTX_DRX_P0 <24> SATA_PRX_C_DTX_N2 <24> SATA_PRX_C_DTX_P2 <24> SATA_PTX_DRX_N2 <24> SATA_PTX_DRX_P2 <24> 2 R136 1 10K_0402_5% +3VS HDD ODD SATA_LED# R336 2 1 10K_0402_5% CR_WAKE# R334 2 1 10K_0402_5% PCH_GPIO19 R335 1 2 10K_0402_5% D AB8 AB10 AF3 AF1 Y7 Y5 AD3 AD1 Y3 Y1 AB3 AB1 Y11 Y10 SATAICOMP 1 R279 2 37.4_0402_1% +1.05VS_VCC_SATA SATA3_COMP 1 R280 2 49.9_0402_1% +1.05VS_SATA3 1 R281 2 750_0402_1% AB12 AB13 C AH1 RBIAS_SATA3 P3 SATA_LED# V14 CR_WAKE# P1 PCH_GPIO19 SPI_CS0# T1 SPI_CS1# V4 SPI_MOSI SATA0GP / GPIO21 PCH_SPIDO U3 SPI_MISO SATA1GP / GPIO19 for EMI <30,31> <30,31> <30,31> <30,31> SATALED# COUGARPOINT_FCBGA989~D PCH_GPIO19 <19> BOOT BIOS Strap Bit 0 Q65R3@ C494 PCH_SPICLK PCH_SPICLK PCH_SPIDI 0.1U_0402_16V4Z R397 10_0402_5% RTC schematic for non-chargeable 2 W25Q32BVSSIG_SO8 2 1 1 R1444 3 D AZ_SYNC_R 2 33_0402_5% S 1 R156 Q21 1 V5 SATA2RXN SATA2RXP SATA2TXN SATA2TXP PCH_SPIDI G 2 +5VS SPI_CLK LPC_FRAME# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 E36 K36 AM10 AM8 AP11 AP10 SATA3COMPI signal has a weak internal pull *This H=>On Die PLL is supplied by 1.5V D36 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TCK LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 AM3 AM1 AP7 AP5 HDA_DOCK_RST# / GPIO13 PCH_JTAG_TCK C38 A38 B37 C37 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA3RCOMPO HDA_SYNC <28> AZ_SYNC_HD HDA_DOCK_EN# / GPIO33 JTAG 2 10K_0402_5% SPI 1 R560 C36 LDRQ0# LDRQ1# / GPIO23 INTVRMEN AZ_BITCLK E34 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 FWH4 / LFRAME# SM_INTRUDER# @ 1 R276 RTCX1 C20 AZ_SDIN0_HD <28> AZ_SDIN0_HD 2 1M_0402_5% 2 330K_0402_5% A20 PCH_RTCX2 1 D R117 1 PCH_RTCX1 LPC 2 C216 Y3 1 SATA 6G JCOMS @ 1 2 C247 2 1U_0402_6.3V6K SATA PCH_RTCRST# RTC 2 IHDA R292 1 20K_0402_5% R291 10M_0402_5% 2 1 CMOS Setting, near DDR Door +RTCVCC 1 +RTCVCC +RTCBATT D13 3 2 +3VL 1 Please close to U2 PCH 2 1 C486 0.1U_0402_16V4Z B 2 1 R277 1K_0402_5% BAV70W_SOT323-3 1 C86 10P_0402_50V8J 2 B + remove socket for DVT phase, due to ME height limitation 2 - @ JRTC LOTES_AAA-BAT-054-K01 +3VALW +3VALW +3VALW 1 1 2 0812 -> Add R277 for RTC reserve charge R306 100_0402_1% 1 PCH_JTAG_TDI 2 PCH_JTAG_TDO 1 PCH_JTAG_TMS 1 R278 200_0402_5% R330 200_0402_5% 2 2 R363 200_0402_5% R301 100_0402_1% R295 100_0402_1% PCH_JTAG_TCK 2 51_0402_1% 1 R355 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 1 2 A 2 A 2 Title PCH_HDA/JTAG/SATA/SPI/LPC Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 15 of 43 2 U2B PERN2 PERP2 PETN2 PETP2 D BG36 BJ36 AV34 AU34 PERN3 PERP3 PETN3 PETP3 BF36 BE36 AY34 BB34 PERN4 PERP4 PETN4 PETP4 BG37 BH37 AY36 BB36 +3VS R287 1 2 10K_0402_5% CLKREQ_JET# R338 1 2 10K_0402_5% CLKREQ_WLAN# C PERN6 PERP6 PETN6 PETP6 BG40 BJ40 AY40 BB40 PERN7 PERP7 PETN7 PETP7 BE38 BC38 AW 38 AY38 LAN <26> <26> CLK_LAN# CLK_LAN CLK_LAN# CLK_LAN CLKREQ_LAN# <26> CLKREQ_LAN# WLAN Y40 Y39 J2 CLK_WLAN# CLK_WLAN <25> CLK_WLAN# <25> CLK_WLAN AB49 AB47 CLKREQ_WLAN# <25> CLKREQ_WLAN# M1 AA48 AA47 CLKREQ_JET# V10 Y37 Y36 CLKREQ_CR# A8 Y43 Y45 PCH_GPIO26 +3VALW R343 1 210K_0402_5% CLKREQ_LAN# R344 1 210K_0402_5% PCH_GPIO26 R345 1 210K_0402_5% CLKREQ_CR# R346 1 210K_0402_5% CLKREQ_USB30# R348 1 210K_0402_5% R351 1 210K_0402_5% PASSWORD_CLEAR# CLKREQ_USB30# PASSWORD_CLEAR# LVDS_SEL <10> CLK_RES_ITP# <10> CLK_RES_ITP <5> CLK_CPU_ITP# <5> CLK_CPU_ITP R233 R282 2 2 R352 R353 2 2 @ @ C9 PCH_SMBDATA 1 0_0402_5% 1 0_0402_5% PANEL_SEL SML0ALERT# / GPIO60 A12 1 0_0402_5% 1 0_0402_5% CLK_BCLK_ITP# CLK_BCLK_ITP C8 PCH_SMLCLK0 G12 PCH_SMLDATA0 SML1ALERT# / PCHHOT# / GPIO74 C13 PCH_GPIO74 SML1CLK / GPIO58 E14 PCH_SMLCLK1 M16 PCH_SMLDATA1 SML0CLK +3VS Q3B PCH_SMBDATA R400 R386 3 Q3A 6 4.7K_0402_5% 4.7K_0402_5% 4 PM_SMBDATA <11,12,25> 2N7002DW-T/R7_SOT363-6 1 PM_SMBCLK <11,12,25> 2N7002DW-T/R7_SOT363-6 DRAMRST_CNTRL_PCH <7> D +3VALW 2 R364 1 2.2K_0402_5% 2 R385 1 2.2K_0402_5% +3VS PCH_SMLDATA1 3 Q4A PCH_SMLCLK1 4 EC_SMB_DA2 <30> 2N7002DW-T/R7_SOT363-6 6 1 EC_SMB_CK2 <30> 2N7002DW-T/R7_SOT363-6 CL_CLK1 M7 CL_DATA1 T11 CL_RST1# P10 Control Link only for support Intel IAMT. +3VALW PEG_A_CLKRQ# / GPIO47 CLKOUT_PCIE0N CLKOUT_PCIE0P M10 EC_LID_OUT# R123 1 2 10K_0402_5% DRAMRST_CNTRL_PCH R228 1 2 1K_0402_5% PCH_GPIO74 R234 1 2 10K_0402_5% PCH_SMLCLK0 R238 1 2 10K_0402_5% PCH_SMLDATA0 R239 1 2 10K_0402_5% PCH_GPIO47 R251 1 2 10K_0402_5% PCH_GPIO47 C PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P CLKOUT_PEG_A_N CLKOUT_PEG_A_P AB37 AB38 CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P AM12 AM13 CLK_DPLL# CLK_DPLL CLKIN_DMI_N CLKIN_DMI_P BF18 BE18 PCH_CLK_DMI# PCH_CLK_DMI PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P PCIECLKRQ2# / GPIO20 CLKIN_GND1_N CLKIN_DMI2_N CLKIN_GND1_P CLKIN_DMI2_P CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PAD PAD 120 MHz for eDP CLKIN_GND1# CLKIN_GND1 CLK_DOT# CLK_DOT CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P AK7 AK5 CLK_SATA# CLK_SATA REFCLK14IN K45 CLK_14M_PCH CLKIN_PCILOOPBACK H45 CLK_PCILOOP XTAL25_IN XTAL25_OUT V47 V49 PCH_X1 PCH_X2 XCLK_RCOMP Y47 XCLK_RCOMP 1 R354 CLKOUT_PCIE4N CLKOUT_PCIE4P L14 BJ30 BG30 CLK_CPU_DMI# <5> CLK_CPU_DMI <5> T13 T14 G24 E24 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE5N CLKOUT_PCIE5P From Clock Gen. PCH_CLK_DMI# PCH_CLK_DMI R242 1 R243 1 2 10K_0402_5% 2 10K_0402_5% CLKIN_GND1# CLKIN_GND1 R244 1 R245 1 2 10K_0402_5% 2 10K_0402_5% CLK_DOT# CLK_DOT R246 1 R247 1 2 10K_0402_5% 2 10K_0402_5% CLK_SATA# CLK_SATA R248 1 R249 1 2 10K_0402_5% 2 10K_0402_5% CLK_14M_PCH R250 1 2 10K_0402_5% B For EMI CLK_PCILOOP <19> CLK_PCILOOP @ 2 R417 @ 2 1 C474 22P_0402_50V8J 1 10_0402_5% PEG_B_CLKRQ# / GPIO56 V40 V42 CLKOUT_PCIE6N CLKOUT_PCIE6P T13 PCIECLKRQ6# / GPIO45 V38 V37 CLKOUT_PCIE7N CLKOUT_PCIE7P AK14 AK13 1 2.2K_0402_5% EC_LID_OUT# <30> DRAMRST_CNTRL_PCH SML0DATA SML1DATA / GPIO75 PERN8 PERP8 PETN8 PETP8 V45 V46 K12 1 2.2K_0402_5% 2 R260 Q4B PCIECLKRQ4# / GPIO26 E6 2 JPW @ PCH_SMBCLK 2 R232 PCH_SMBCLK L12 AB42 AB40 Please place under DDR SODIMM. 10/25 PANEL_SEL H14 1 B E12 SMBCLK SMBDATA PERN5 PERP5 PETN5 PETP5 BJ38 BG38 AU36 AV36 SMBALERT# / GPIO11 EC_LID_OUT# 5 BE34 BF34 BB32 AY32 Link 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2 +3VALW SMBUS C501 2 C502 2 PERN1 PERP1 PETN1 PETP1 Controller PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_C_WLANRX_N2 PCIE_PTX_C_WLANRX_P2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K BG34 BJ34 AV32 AU32 2 90.9_0402_1% +1.05VS_VCCDIFFCLKN delete test-point for EMI request FLEX CLOCKS WLAN <25> <25> <25> <25> C498 2 C497 2 PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_LANRX_N1 PCIE_PTX_LANRX_P1 CLOCKS LAN PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_C_LANRX_N1 PCIE_PTX_C_LANRX_P1 PCI-E* <26> <26> <26> <26> 1 5 3 2 4 2 5 PCIECLKRQ7# / GPIO46 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P COUGARPOINT_FCBGA989~D CLKOUTFLEX0 / GPIO64 K43 CLKOUTFLEX1 / GPIO65 F47 CLKOUTFLEX2 / GPIO66 H47 PCH_48MCLK 1 R576 2 22_0402_5% CLK_FLEX2 T31 K49 CLK_FLEX3 CLKOUTFLEX3 / GPIO67 T33 48MCLK_CR <27> R365 2 1 1M_0402_5% PAD Y2 PCH_X1 PAD Q65R3@ C506 27P_0402_50V8J 1 1 2 PCH_X2 25MHZ_20PF_7A25000012 2 1 2 C507 27P_0402_50V8J +3VALW A PANEL_SEL @ 1 R584 PANEL_SEL 2 10K_0402_5% R347 1 2 10K_0402_5% A LVDS_SEL PANEL_SEL H L Channel LVDS EDP Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_PCI-E/SMBUS/CLK Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 16 of 43 5 4 3 2 1 U2C DRAMPWROK PCH_SUSPWRDN_R RI# PCH_LOW_BAT# PCH_RSMRST# 1 10K_0402_5% PM_PWROK 1 10K_0402_5% SYS_PWROK 1 10K_0402_5% 2 R127 2 R128 2 R129 BC24 BE20 BG18 BG20 DMI0RXN DMI1RXN DMI2RXN DMI3RXN <6> <6> <6> <6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP <6> <6> <6> <6> DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 AW24 AW20 BB18 AV18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN <6> <6> <6> <6> DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 AY24 AY20 AY18 AU18 DMI_COMP 2 49.9_0402_1% 1 R130 +1.05VS_PCH BG25 RBIAS_CPY 2 750_0402_1% 1 R160 0_0402_5% 1 @ R259 2 PM_PWROK 2 5 T34 SUSACK# O SYS_PWROK 4 PM_PWROK 1 R216 C12 K3 P12 PM_PWROK_R 2 0_0402_5% L22 L10 <5> DRAMPWROK SUSACK# @ 2 R137 1 PCH_SUSPWRDN_R 0_0402_5% <30> PCH_RSMRST# Stuff R137 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit 1 R320 <30> PCH_SUSPWRDN <5,30> PBTN_OUT# +3VALW B <30,36> 1 R469 2 330K_0402_5% D12 1 ACIN DRAMPWROK B13 PCH_RSMRST# C21 2 PCH_SUSPWRDN_R K16 0_0402_5% PBTN_OUT# E20 PCH_ACIN H20 PCH_LOW_BAT# E10 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_INT AW16 FDI_INT AV12 FDI_FSYNC0 BC10 FDI_FSYNC1 FDI_FSYNC0 FDI_LSYNC0 AV14 FDI_LSYNC0 FDI_LSYNC1 BB10 FDI_LSYNC1 A18 DSWVREN E22 PCH_DPWROK SYS_RESET# SYS_PWROK RI# A10 PWROK APWROK DRAMPWROK RSMRST# DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 <6> <6> <6> <6> <6> <6> <6> <6> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 <6> <6> <6> <6> <6> <6> <6> <6> D FDI_INT <6> FDI_FSYNC1 SUSACK# FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 B9 EC_SWI# N3 PM_GPIO32 G8 SUS_STAT# FDI_FSYNC0 PCH_DPWROK <6> FDI_FSYNC1 <6> FDI_LSYNC0 <6> FDI_LSYNC1 <6> Stuff R222 if do not support DeepSX state +RTCVCC DSWVREN 2 1 330K_0402_5% @ C 1 330K_0402_5% DSWVREN must be always pulled high to +RTCVCC T17 PAD * 32.768 KHz N14 CLK_EC <30> D10 PM_SLP_S5# H4 PM_SLP_S4# F4 PM_SLP_S3# G10 PM_SLP_A# T35 PAD G16 PM_SLP_SUS# T58 PAD AP14 H_PM_SYNC K14 PCH_GPIO29 ： ： DSWVREN - Internal Deep Sleep 1.05V regulator H Enable L Disable PM_SLP_S5# <30> PM_SLP_S4# <30> PM_GPIO32 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PWRBTN# SLP_A# ACPRESENT / GPIO31 SLP_SUS# BATLOW# / GPIO72 PMSYNCH R313 1 2 8.2K_0402_5% PM_SLP_S3# <30> 8/18 Change Net name from PM_CLKRUN# to PCH_GPIO32 by HW Review demand +3VALW RI# SLP_LAN# / GPIO29 H_PM_SYNC <5> EC_SWI# R319 1 2 10K_0402_5% PCH_GPIO29 R563 1 @ 2 10K_0402_5% Q65R3@ 9/1 1 2 R225 EC_SWI# <26> H_PM_SYNC PM_PWROK R224 +3VS SLP_S4# COUGARPOINT_FCBGA989~D D16 2 PCH_RSMRST# 2 0_0402_5% 1 R222 B 2 RB751V40_SC76-2 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 DMI2RBIAS IN2 SN74AHC1G08DCKR_SC70-5 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 DSWVRMEN XDP_DBRESET# <5> XDP_DBRESET# U12 IN1 3 <5,30> PM_PWROK PAD FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 DMI_IRCOMP G 1 <5,30,41> VGATE DMI_ZCOMP P 0.1U_0402_16V4Z 1 2 C250 BH21 DMI0TXP DMI1TXP DMI2TXP DMI3TXP 8/30 Reserve R259 For cost down plan +3VS C BJ24 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 System Power Management 1 200_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI PS3@ 2 R316 2 R218 2 R220 2 R221 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI +3VALW D <6> <6> <6> <6> C898 1 @ 2 220P_0402_50V7K Reserve C894 for ESD requset PCH_RSMRST# RB751V40_SC76-2 <35,37> POK D14 1 2 RB751V40_SC76-2 A A 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_DMI/FDI/PM Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 17 of 43 5 4 3 2 1 U2D UMA_ENBKL 2 100K_0402_5% C 2 R471 LCTL_CLK 1 2.2K_0402_5% 2 R472 LCTL_DATA 1 2.2K_0402_5% 2 R223 LCD_EDID_CLK 1 2.2K_0402_5% 2 R229 LCD_EDID_DATA 1 2.2K_0402_5% 2 R237 UMA_CRT_CLK 1 2.2K_0402_5% 2 R231 UMA_CRT_DATA 1 2.2K_0402_5% 1 R240 UMA_CRT_B 2 150_0402_1% 1 R241 UMA_CRT_G 2 150_0402_1% 1 R318 UMA_CRT_R 2 150_0402_1% T40 K47 L_DDC_CLK L_DDC_DATA LCTL_CLK LCTL_DATA T45 P39 L_CTRL_CLK L_CTRL_DATA LVDS_IBG 2 2.37K_0402_1% T40 PAD <13> LCD_TXCLK<13> LCD_TXCLK+ +3VS L_BKLTCTL LCD_EDID_CLK LCD_EDID_DATA <13> LCD_TXOUT0<13> LCD_TXOUT1<13> LCD_TXOUT2<13> LCD_TXOUT0+ <13> LCD_TXOUT1+ <13> LCD_TXOUT2+ <14> UMA_CRT_B <14> UMA_CRT_G <14> UMA_CRT_R <14> UMA_CRT_CLK <14> UMA_CRT_DATA <14> UMA_CRT_HSYNC <14> UMA_CRT_VSYNC 2 R311 AF37 AF36 LVD_IBG LVD_VBG AE48 AE47 LVD_VREFH LVD_VREFL LCD_TXCLKLCD_TXCLK+ AK39 AK40 LVDSA_CLK# LVDSA_CLK LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2- AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LCD_TXOUT0+ LCD_TXOUT1+ LCD_TXOUT2+ AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 AF40 AF39 LVDSB_CLK# LVDSB_CLK AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 UMA_CRT_B UMA_CRT_G UMA_CRT_R N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED UMA_CRT_CLK UMA_CRT_DATA T39 M40 CRT_DDC_CLK CRT_DDC_DATA UMA_CRT_HSYNC UMA_CRT_VSYNC M47 M49 CRT_HSYNC CRT_VSYNC CRT_IREF 1 1K_0402_0.5% T43 T42 DAC_IREF CRT_IRTN SDVO_TVCLKINN SDVO_TVCLKINP AP43 AP45 SDVO_STALLN SDVO_STALLP AM42 AM40 SDVO_INTN SDVO_INTP AP39 AP40 SDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPD AT49 AT47 AT40 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 DDPC_CTRLCLK DDPC_CTRLDATA HDMI_HPD HDMI_HPD <20> R1433 100K_0402_5% P46 P42 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPD_CTRLCLK DDPD_CTRLDATA COUGARPOINT_FCBGA989~D D P38 M39 1 1 R230 P45 2 1 R219 L_BKLTEN L_VDD_EN PCH_PW M Digital Display Interface D J47 M45 LVDS <13> PCH_PW M <13> LCD_EDID_CLK <13> LCD_EDID_DATA UMA_ENBKL UMA_ENVDD CRT <30> UMA_ENBKL <13> UMA_ENVDD R473 2 1 100K_0402_5% C M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 R524 2 1 100K_0402_5% Q65R3@ B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_CRT/LVDS Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 18 of 43 5 4 3 2 1 8.2K_0804_8P4R_5% 8/23 PIN swap for layout request 8 7 6 5 PCH_GPIO52 PCH_GPIO53 PCH_GPIO54 RF_OFF# 1 2 3 4 8.2K_0804_8P4R_5% RP3 8 7 6 5 C PCH_GPIO50 PCI_PIRQB# ODD_DA# W L_OFF# 1 2 3 4 8.2K_0804_8P4R_5% PCH_GPIO5 2 8.2K_0402_5% PCI_PIRQD# 2 8.2K_0402_5% 1 R321 1 R322 <25> <24> W L_OFF# ODD_DA# B T32 PAD PLT_RST# 2 <5,25,26,30,31> PLT_RST# <30> CLK_PCI_EC <16> CLK_PCILOOP <31> CLK_PCI_DDR 22_0402_5% 1 22_0402_5% 1 22_0402_5% 1 TP21 TP22 TP23 TP24 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 RF_OFF# PCH_GPIO53 W L_OFF# D47 E42 F46 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5 G42 G40 C42 D44 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 C6 2 R525 2 R526 2 R527 CLK_EC_R CLK_PCH CLK_SIO H49 H43 J48 K42 H40 AV5 AY1 PIRQA# PIRQB# PIRQC# PIRQD# D NV_CLE AV10 NV_RB# AT8 NV_RE#_WRB0 NV_RE#_WRB1 AY5 BA2 AT12 BF3 C USB20_N0 USB20_P0 USB20_N1 USB20_P1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB port6 and port7 are disabled on HM65 USBRBIAS# C33 USBBIAS USBRBIAS B33 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 EHCI 1 C46 C44 E40 K10 NV_ALE NV_WE#_CK0 NV_WE#_CK1 PCH_GPIO50 PCH_GPIO52 PCH_GPIO54 PLT_RST# AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 NV_RCOMP K40 K38 H38 G38 PCI_PME# AT10 BC8 DF_TVS NV_CLE PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# 1 R534 100K_0402_5% B21 M20 AY16 BG46 NV_DQS0 NV_DQS1 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 PCI RP2 AY7 AV7 AU3 BG4 EHCI 2 USB20_N0 USB20_P0 USB20_N1 USB20_P1 <24> <24> <24> <24> USB-LEFT1 USB-LEFT2 DMI & FDI Termination Voltage NV_CLE Set to VCC when HIGH Set to VSS when LOW +1.8VS USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N9 <25> USB20_P9 <25> USB20_N10 <27> USB20_P10 <27> USB20_N11 <13> USB20_P11 <13> WiMax&BT combo card 1 PCI_PIRQC# PCH_GPIO4 PCH_GPIO2 PCI_PIRQA# 1 2 3 4 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 R324 2.2K_0402_5% Card Reader Int. Camera NV_CLE 1 R535 2 RP1 8 7 6 5 USB +3VS TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 RSVD D BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 NVRAM U2E 2 R323 1 1K_0402_5% 8/18 Change R324 From 1K to 2.2K by Intel check list demand 2 22.6_0402_1% H_SNB_IVB# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 COUGARPOINT_FCBGA989~D B Within 500 mils PME# PLTRST# H_SNB_IVB# <5> USB_OC#0 USB_OC#1 USB_OC#2 SLP_CHG_M3 SLP_CHG_M4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#0 <24,30> C895 USB-Left 9/1 1 @ 2 220P_0402_50V7K Reserve C895 for ESD requset +3VALW Q65R3@ RP4 USB_OC#6 USB_OC#0 USB_OC#5 SLP_CHG_M4 Boot BIOS Strap RF_OFF# 1K_0402_5% 1K_0402_5% 2 @ 1 R537 RF_OFF# 2 @ 1 R538 PCH_GPIO19 A 1K_0402_5% 2 @ 1 R536 W L_OFF# PCH_GPIO19 <15> PCH_GPIO19 0 0 1 1 0 1 0 1 Boot BIOS Loaction 10K_0804_8P4R_5% RP5 USB_OC#1 USB_OC#2 SLP_CHG_M3 USB_OC#7 Reserved PCI * * Low= A16 swap override Enable High= A16 swap override Disable 4 5 6 7 8 A 2010/09/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 1 10K_0804_8P4R_5% A16 Swap Override Strap WL_OFF# 5 6 7 8 8/23 PIN swap for layout request LPC SPI 4 3 2 1 3 2 Title PCH_PCI/USB/NAND Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 19 of 43 5 4 3 2 1 +3VS +3VALW U2F ODD_EN# <18> HDMI_HPD PCH_GPIO28 3D_DET# C 2 R437 1 R547 2 R402 2 10K_0402_5% HDMI_HPD 2 10K_0402_5% PCH_GPIO1 2 10K_0402_5% BT_DET# 2 10K_0402_5% OPTIMUS_EN# 2 10K_0402_5% ODD_DETECT# 2 200K_0402_5% PCH_GPIO6 2 10K_0402_5% PCH_GPIO16 2 10K_0402_5% EC_SCI# 2 10K_0402_5% CIR_EN# 2 100K_0402_5% ISDBT_DET 2 10K_0402_5% PCH_GPIO49 2 10K_0402_5% PCH_GPIO17 2 10K_0402_5% @ @ B41 PCH_W L_BT_LED PCH_GPIO6 H36 TACH2 / GPIO6 TACH6 / GPIO70 C41 LOGO_LED EC_SCI# E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 MAXIC_SELECT <30> EC_SMI# EC_SMI# C10 GPIO8 BT_ON# T74 PAD <24> ODD_DETECT# PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12 USB30_SMI# G2 GPIO15 PCH_GPIO16 U2 PCH_GPIO17 D40 2 47K_0402_5% ISDBT_DET 1 @ 2 1K_0402_5% PCH_GPIO28 A20GATE SATA4GP / GPIO16 TACH0 / GPIO17 T5 SCLOCK / GPIO22 E8 GPIO24 / MEM_LED PCH_GPIO27 E16 GPIO27 PCH_GPIO28 P8 GPIO28 BT_ON# K1 STP_PCI# / GPIO34 PCH_GPIO35 K4 GPIO35 ODD_DETECT# V8 SATA2GP / GPIO36 PCH_GPIO37 M5 SATA3GP / GPIO37 OPTIMUS_EN# N2 SLOAD / GPIO38 CIR_EN# M3 SDATAOUT0 / GPIO39 V13 ISDBT_DET 1 10K_0402_5% PCH_GPIO37 2 100K_0402_5% PCH_GPIO27 1 10K_0402_5% ODD_EN# <33> EC_SCI# <25> On-Die PLL Voltage Regulator H: Enable L: Disable R325 ODD_EN# TACH5 / GPIO69 BT_DET# GPIO28 * C40 TACH1 / GPIO1 T7 PECI P4 GATEA20 P5 KB_RST# AY11 H_PW RGOOD THRMTRIP# AY10 PCH_THRMTRIP# 1 R416 RCIN# D GATEA20 <30> PROCPWRGD KB_RST# <30> H_PW RGOOD <5> 2 390_0402_5% H_THERMTRIP# <5> INIT3_3V# T14 NC_1 AH8 This signal has weak internal pull-up, can't be pulled low NC_2 AK11 8/18 Remove PCH PECI by HW Review demand NC_3 AH10 NC_4 AK10 NC_5 P37 C SDATAOUT1 / GPIO48 VSS_NCTF_15 BG2 V3 SATA5GP / GPIO49 VSS_NCTF_16 BG48 3D_DET# D6 GPIO57 VSS_NCTF_17 BH3 VSS_NCTF_18 BH47 A4 VSS_NCTF_1 VSS_NCTF_19 BJ4 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 A45 VSS_NCTF_3 VSS_NCTF_21 BJ45 A46 VSS_NCTF_4 VSS_NCTF_22 BJ46 A5 VSS_NCTF_5 VSS_NCTF_23 BJ5 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 B3 VSS_NCTF_7 VSS_NCTF_25 C2 B47 VSS_NCTF_8 VSS_NCTF_26 C48 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 BF49 VSS_NCTF_14 VSS_NCTF_32 F49 COUGARPOINT_FCBGA989~D T75 PAD 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% AU16 PCH_GPIO49 USB30_SMI# 1 R328 B TACH4 / GPIO68 A42 <30> BT_ON# @ BMBUSY# / GPIO0 PCH_GPIO1 PCH_GPIO12 +3VS 1 R567 1 R539 1 R540 1 R542 1 R554 1 R545 1 R546 1 R577 1 R550 1 R551 1 R552 1 R553 1 R555 HDMI_HPD EC_SMI# CPU/MISC USB30_SMI# GPIO D 1 1K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% NCTF 2 R390 1 R558 1 R556 1 R557 1 R549 1 R106 GATEA20 1 R548 KB_RST# 1 R559 LOGO_LED 1 R436 PCH_W L_BT_LED 1 R110 B H_THERMTRIP# C896 1 @ 2 220P_0402_50V7K H_PW RGOOD C897 1 @ 2 220P_0402_50V7K 9/1 Q65R3@ Reserve C896, C897 for ESD requset GPIO8 * Integrated Clock Chip Enable (Removed) H: Disable L: Enable R326 1 A @ 2 1K_0402_5% EC_SMI# A Integrated clock enable functionality is achieved by soft-strap The current default is clock enable Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_CPU/GPIO Size B Date: Document Number Rev 1.0 PWWHA LA-7202P M/B Friday, February 25, 2011 Sheet 1 20 of 43 4 3 U2G C289 1 D 10U_0603_6.3V6M 2 2 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K +1.05VS_PCH AN19 BJ22 T30 PAD AN16 AN17 AN21 C +1.05VS_PCH C277 1 C273 1 C279 1 C510 10U_0603_6.3V6M 2 2 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K 2 AT24 U47 1mA VCCALVDS VSSALVDS VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] AN34 +3VS BH29 1 2 AP16 T36 PAD BG6 +1.05VS_PCH AP17 +VCCP_VCCDMI AU20 2 10U_0603_6.3V6M V_PROC_IO 1 R541 V5REF_SUS +1.8VS AM37 AM38 +VCCTX_LVDS L1 2 1 BLM18PG181SN1D_0603 0.01U_0402_25V7K 1 AP36 C514 0.01U_0402_25V7K Voltage S0 Iccmax Current (A) 1.05 0.001 5 0.001 D 2 0_0603_5% AK37 AP37 PCH Power Rail Table Voltage Rail +3VS C513 5 0.001 VCC3_3 3.3 0.266 VCCADAC 3.3 0.001 VCCADPLLA 1.05 0.08 VCCADPLLB 1.05 0.08 VCCCORE 1.05 1.3 VCCDMI 1.05 0.042 VCCIO 1.05 2.925 VCCASW 1.05 1.01 VCCSPI 3.3 0.02 VCCDSW 3.3 0.002 VCCDFTERM 1.8 0.19 VCCRTC 3.3 6 uA 3.3 0.97 C256 22U_0805_6.3V6M 2 +3VS VCCIO[15] VCCIO[16] VCC3_3[6] V33 1 VCC3_3[7] V34 C272 0.1U_0402_10V7K 2 VCCIO[17] VCCVRM[3] AT16 R474 0_0603_5% 1 2 +VCCAFDI_VRM +VCCP_VCCDMI VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCDMI[1] 20mA VCCIO[1] AT20 +VCCP_VCCDMI AB36 +1.05VS_VCC_DMI 1 2 VCCIO[25] VCCPNAND[1] VCC3_3[3] VCCVRM[2] VCCFDIPLL VCCDMI[2] R477 0_0805_5% 1 2 C +1.05VS_VCCP R480 0_0805_5% 1 2 +1.05VS_PCH 1 2 C276 1U_0402_6.3V6K C270 1U_0402_6.3V6K VCCDFTERM VCCIO[26] VCCIO[27] +1.5VS +VCCAFDI_VRM C290 0.1U_0402_10V7K +VCCAFDI_VRM +3VS L12 1 R104 2 +VCCA_DAC_R 2 1 2.2_0603_1% BLM18PG181SN1D_0603 V5REF +VCCA_LVDS AK36 1U_0402_6.3V6K AN33 B C512 0.01U_0402_25V7K VCCAPLLEXP VCCIO[19] 2925mA AP26 0.1U_0402_10V7K 1 1 C288 C286 2 VCCTX_LVDS[4] AN27 AP24 1 C511 +VCCA_DAC U48 VCCIO[28] VCCIO[18] AP23 1 VCCADAC VSSADAC 60mA AN26 AP21 1U_0402_6.3V6K 1mA CRT C275 1 1 To solve CRT issue LVDS C269 1 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] 2 POWER 1300mA HVCMOS JUMP_43X118 1 C274 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 DMI 1 +1.05VS_PCH 1U_0402_6.3V6K 1 NAND / SPI 2 @ FDI PJ31 2 VCC CORE +1.05VS_VCCP VCCIO 5 VCCSUS3_3 +1.8VS AG16 VCCSusHDA VCCPNAND[2] 190mA VCCPNAND[3] 1 AJ16 VCCSPI 1.5 0.16 VCCCLKDMI 1.05 0.02 VCCSSC 1.05 0.095 VCCDIFFCLKN 1.05 0.055 VCCALVDS 3.3 0.001 VCCTX_LVDS 1.8 0.06 AJ17 V1 1 COUGARPOINT_FCBGA989~D VCCVRM C278 0.1U_0402_10V7K +3VS 20mA 0.01 AG17 2 VCCPNAND[4] 3.3 / 1.5 Q65R3@ 2 C281 1U_0402_6.3V6K B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_POWER-1 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 21 of 43 5 4 3 2 1 +3VS T42 PAD 1 D T16 2 @ C305 2 1 "@" Avoid leakage POWER U2J AD49 C324 0.1U_0402_10V7K +1.05VS_PCH VCCACLK VCCIO[29] VCCIO[30] 3mA VCCDSW3_3 VCCIO[31] +PCH_VCCDSW V12 +3VS_VCC_CLKF33 T38 DCPSUSBYP VCCIO[32] 0.1U_0402_10V7K AL29 +VCCSUS AA26 1 C312 AA27 22U_0805_6.3V6M 2 2 22U_0805_6.3V6M AA29 AA31 C C323 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1 C294 C308 2 2 AC26 1 AC27 1U_0402_6.3V6K 2 AC29 +1.05VS_PCH AC31 L13 1 2 BLM18PG181SN1D_0603 L14 1 2 BLM18PG181SN1D_0603 AD29 +1.05VS_VCCADPLLA AD31 +1.05VS_VCCADPLLB W21 W23 C287 1 C295 1 C291 1 1 C298 1U_0402_6.3V6K W24 1U_0402_6.3V6K 2 2 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M W26 W29 W31 +1.05VS_PCH R522 2 W33 +VCCDIFFCLK 1 0_0603_5% 1 DCPSUS[3] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCASW[1] VCCASW[2] VCCIO[34] 1010mA 1mA VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] V5REF_SUS +VCCRTCEXT C334 0.1U_0402_10V7K 2 N16 1 VCCSUS3_3[1] 1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] Y49 C328 1U_0402_6.3V6K T27 T29 +3VALW T23 1 T24 V23 C321 0.1U_0402_10V7K 2 +3VALW +5VALW +3VALW 1 V24 P24 2 C332 0.1U_0402_10V7K R512 100_0402_5% D8 RB751V40_SC76-2 T26 VCC3_3[8] VCCASW[16] VCC3_3[4] 1 +PCH_V5REF_SUS AN23 +VCCA_USBSUS 2 C335 1 AN24 P34 +3VALW +5VS +3VS C +PCH_V5REF_RUN +3VALW R490 100_0402_5% D7 RB751V40_SC76-2 1 N22 P20 C293 1U_0402_6.3V6K 2 +3VS +3VS W16 T34 VCCVRM[4] VCCIO[13] 1 C313 0.1U_0402_10V7K 2 +3VS AJ2 +1.05VS_SATA3 1 AF13 2 DCPRTC C304 1U_0603_10V6K AA16 1 2 C306 0.1U_0402_10V7K VCCASW[20] +PCH_V5REF_RUN 1 P22 VCCASW[18] VCC3_3[2] C326 0.1U_0603_25V7K 2 1U_0402_6.3V6K N20 VCCASW[17] VCCASW[19] +PCH_V5REF_SUS +1.05VS_PCH M26 2 VCC3_3[1] VCCIO[12] +VCCAFDI_VRM 2 @ DCPSUS[4] VCCIO[5] C337 1U_0402_6.3V6K D P28 2 AA19 AA24 1 119mA VCCIO[14] VCCSUS3_3[6] AA21 C311 VCCAPLLDMI2 PCI/GPIO/LPC 2 +1.05VS_PCH AL24 C300 1U_0402_6.3V6K @ VCCSUS3_3[7] Clock and Miscellaneous 1 1 P26 VCC3_3[5] USB BH23 T41 PAD +1.05VS_PCH VCCIO[33] N26 2 +3VALW 1 C310 1U_0402_6.3V6K 2 2 1 C301 10U_0603_6.3V6M 1 2 +3VS_VCC_CLKF33 1 1 1 2 L18 1 2 10UH_LB2012T100MR_20% 2 1 AH13 +1.05VS_SATA3 AH14 +1.05VS_PCH R516 C297 0.1U_0402_10V7K 1 0_0805_5% C329 1U_0402_6.3V6K 2 2 B +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLA BD47 R485 +1.05VS_VCCDIFFCLKN 1 1 0_0603_5% C320 1U_0402_6.3V6K +1.05VS_VCCADPLLB BF47 +VCCDIFFCLK AF17 AF33 AF34 AG34 2 +1.05VS_VCCDIFFCLKN +1.05VS_PCH VCCADPLLB 80mA 80mA C318 1U_0402_6.3V6K 1 1 2 VCCVRM[1] VCCIO[7] VCCIO[8] VCCIO[9] 55mA VCCIO[11] VCCIO[2] 2 +VCCSST V16 0.1U_0402_10V7K +1.05VM_VCCSUS C299 T17 V19 +V_CPU_IO BJ8 VCCIO[10] VCCIO[4] 95mA DCPSUS[1] DCPSUS[2] VCCASW[22] 0_0603_5% +1.05VM_VCCSUS 1 1 C316 1U_0402_6.3V6K 0_0603_5% C325 4.7U_0603_6.3V6K 1 2 C322 1 2 1 C303 1mA V_PROC_IO CPU @ AF11 +VCCAFDI_VRM AC16 +1.05VS_VCC_SATA AC17 +1.05VS_VCC_SATA 1 AD17 +1.05VS_PCH R491 2 1 0_0805_5% C331 1U_0402_6.3V6K +1.05VS_PCH VCCASW[23] VCCASW[21] T21 +VCCME_22 1 R509 2 0_0402_5% V21 +VCCME_23 1 R517 2 0_0402_5% T19 +VCCME_21 1 R520 2 0_0402_5% +RTCVCC +3VALW 0.1U_0402_10V7K 2 2 C327 A 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2 C330 1 2 1 2 A22 C336 VCCRTC RTC R521 2 0.1U_0402_10V7K T43 PAD +VCCAFDI_VRM AK1 DCPSST R511 2 AF14 2 +1.05VS_VCCP 1 VCCAPLLSATA VCCIO[3] AG33 +1.05VS_PCH VCCIO[6] MISC 2 VCCADPLLA HDA +1.05VS_PCH SATA B 10mA VCCSUSHDA COUGARPOINT_FCBGA989~D P32 1 Q65R3@ 0.1U_0402_10V7K C307 0.1U_0402_16V4Z A 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_POWER-2 Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 22 of 43 5 4 3 2 1 U2I AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 U2H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 D C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] COUGARPOINT_FCBGA989~D VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 Q65R3@ VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] COUGARPOINT_FCBGA989~D H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D C B Q65R3@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH_GND Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 23 of 43 5 4 3 2 1 SATA ODD Conn 1.2A 1 2 Place closely JHDD SATA CONN. 1 C356 10U_0603_6.3V6M 2 C357 0.1U_0402_16V4Z 1 C358 0.1U_0402_16V4Z 2 SW2 1 JODD Close to JODD @ ODD_DA#_R C359 0.1U_0402_16V4Z 2 D SATA HDD Conn. 15 14 GND GND GND A+ AGND BB+ GND 1 2 3 4 5 6 7 DP +5V +5V MD GND GND 8 9 10 11 12 13 SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 C378 1 C377 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 <15> SATA_PTX_DRX_N2 <15> SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 C376 1 C375 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N2 <15> SATA_PRX_C_DTX_P2 <15> ODD_DETECT#_R @ 1 +5VS_ODD R561 ODD_DA#_R 2 0_0402_5% @ 1 R562 1 C 24 23 GND GND 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 D 2 ODD_DA# <19> @ C450 0.1U_0402_16V4Z +5VS_ODD SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 C369 1 C367 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_P0 <15> SATA_PTX_DRX_N0 <15> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C368 1 C370 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N0 <15> SATA_PRX_C_DTX_P0 <15> Place components closely ODD CONN. 1.1A 1 1 2 3 4 5 6 7 4 SMT1-05-A_4P ESD request Close to JHDD GND A+ AGND BB+ GND 3 2 ODD_DETECT# <20> 2 0_0402_5% SANTA_206401-1_RV JHDD @ 1 6 5 +5VS 2 C352 10U_0603_6.3V6M 1 2 C353 @ 10U_0603_6.3V6M 1 2 1 C354 1U_0402_6.3V6K 2 1 C355 0.1U_0402_16V4Z 2 C360 0.1U_0402_16V4Z USB Conn. Left Side +3VS W=60mils 2.5A +5VALW +5VS +USB_VCCA <30> 1 2 3 4 USB_EN# GND VOUT VIN VOUT VIN VOUT EN FLG 8 7 6 5 2 C361 USB_OC#0 <19,30> C362 4.7U_0805_10V4Z 2 @ +5VALW 2 SANTA_191201-1 @ 1 1000P_0402_50V7K 1 RT9715BGS_SO8 C For EMI U14 USB_EN# 1 R568 100K_0402_5% B B +USB_VCCA C85 1 2 220U_6.3V_M_R15 C63 1 2 1000P_0402_50V7K C64 1 2 0.1U_0402_16V4Z W=60mils + W=60mils +USB_VCCA 2 R843 @ 1 0_0402_5% L87 <19> <19> USB20_N0 3 USB20_P0 2 JUSB1 3 2 4 4 1 1 1 2 3 4 USB20_N0_R USB20_P0_R WCM-2012-900T_0805 2 R839 @ VCC DD+ GND @ GND GND GND GND <19> <19> USB20_N1 3 USB20_P1 2 ALLTOP C107L8-10405-L D65 USB20_P0_R 1 0_0402_5% 2 4 4 1 1 @ @ 4 3 1 2 3 4 VCC DD+ GND @ GND GND GND GND 5 6 7 8 ALLTOP C107L8-10405-L USB20_N1_R 2 USB20_P1_R 3 @ 1 PJDLC05C_SOT23-3 A Compal Electronics, Inc. Compal Secret Data 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 USB20_N1_R USB20_P1_R D62 3 2010/09/03 2 0.1U_0402_16V4Z 1 0_0402_5% PJDLC05C_SOT23-3 Issued Date 2 1000P_0402_50V7K 1 JUSB2 3 2 R838 1 Security Classification 1 C60 WCM-2012-900T_0805 2 A C61 L86 5 6 7 8 1 0_0402_5% USB20_N0_R @ 2 R842 2 Title SATA-HDD/ODD/USB Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 24 of 43 WLAN&BT Combo module circuits Slot 1 Half PCIe Mini Card-WLAN/ WiMax 2 +3VALW +3VS 2 1 1 BT on module BT on module Enable Disable +3V_WLAN PJ27@ JUMP_43X79 2 1 2 1 BT_CRTL H L PJ26@ JUMP_43X79 BT_ON# L H Short PJ27 for Wimax Short PJ26 for WLAN **If +3V_WLAN is +3VS, please remove D24 3 BT_CTRL 40 mils For SED CM2 2 0.01U_0402_25V7K 5 BT_ON# CM3 C253 CM7 CM8 47P_0402_50V8J 2 2 2 @ 4.7U_0805_10V4Z 0.01U_0402_25V7K 1 Q50A 2N7002DW-T/R7_SOT363-6 2 4 1 <5,9,33,40> SUSP 1 1 1 1 1 CM1 1 <20> 0.1U_0402_16V4Z 2 1 Q50B +1.5VS 0.1U_0402_16V4Z CM9 C254 47P_0402_50V8J 2 2 @ 4.7U_0805_10V4Z 2 +3V_WLAN 6 2N7002DW-T/R7_SOT363-6 +3VS 2 G For SED +1.5VS <16> CLKREQ_WLAN# <16> CLK_WLAN# <16> CLK_WLAN <16> PCIE_PRX_WLANTX_N2 <16> PCIE_PRX_WLANTX_P2 <16> PCIE_PTX_C_WLANRX_N2 <16> PCIE_PTX_C_WLANRX_P2 WLAN/ WiFi +3V_WLAN <30> <30> E51_TXD E51_RXD Debug card using R16 10_0402_5%2 1 2 0_0402_5% R17 E51_RXD_R 53 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1 +3V_WLAN @ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 WLAN_OFF# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 FOX_AS0B226-S40N-7F 1 2N7002_SOT23-3 Q36 WLAN_OFF# 1 R565 WLAN_OFF# PLT_RST# 3 S 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 D JWLAN R1443 0_0402_5% @ 2BT_CTRL_R BT_CTRL 1 @ 2 10K_0402_5% WL_OFF# <19> Add level shift circuit for WL_OFF# to avoide leakage from WLAN to PCH +3V_WLAN PLT_RST# <5,19,26,30,31> PM_SMBCLK <11,12,16> PM_SMBDATA <11,12,16> USB20_N9 <19> USB20_P9 <19> BT_CTRL 1 R327 2 1K_0402_5% WiMax&BT combo card E51_RXD_R For isolate Intel Rainbow Peak and Compal Debug Card. 8/30 Reserve R1443 for WLAN Mini PCIE Card Pin5 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PCIe-WLAN Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 25 of 43 A B C D E UL1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 CLKREQ_LAN# <5,19,25,30,31> PLT_RST# <16> <16> +3VS NC Pin15 NC Pin38 1 2 Pin14 RTL8111E <17> NC 44 EC_SWI# EC_SWI# 28 ISOLATE# 26 10K ohm PD 1K ohm Pull-high RL21 2 8111E@ 1 10K_0402_5% RL22 1 2 1K_0402_5% 8111E@ +3V_LAN 1K_0402_5% RL6 @ ISOLATE# 43 LAN_X2 ENSWREG 1 RL433 WOL_EN 2 0_0402_5% Sx Enable Sx Disable Wake up Wake up RL7 15K_0402_5% WOL_EN LOW 33 34 35 +LAN_VDDREG 1 RL5 S0 14 15 38 2 46 2.49K_0402_1% 24 49 MDIP0 MDIN0 MDIP1 MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3 PERSTB REFCLK_P REFCLK_N 1 10K_0402_5% 1 10K_0402_5% LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3- Layout Note: LL1 must be within 200mil to Pin36, CL13,CL9 must be within 200mil to LL1 1 1 CL3 1 CL4 1 CL5 1 CL6 1 8111E@ CL7 1 8111E@ CL8 1 CL9 0.1U_0402_16V4Z 2 8111E@ CL13 4.7U_0603_6.3V6K 8111E@ 2 CKXTAL2 13 29 41 DVDD10 DVDD10 DVDD10 +LAN_VDD10 +LAN_VDD10 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +LAN_VDD10 LANWAKEB ISOLATEB 27 39 DVDD33 DVDD33 NC/SMBCLK NC/SMBDATA GPO/SMBALERT AVDD33 AVDD33 AVDD33 AVDD33 ENSWREG EVDD10 VDDREG VDDREG RSET GND PGND AVDD10 AVDD10 AVDD10 AVDD10 0.1U_0402_16V4Z REGOUT CL18 1U_0402_6.3V6K +3V_LAN 21 +LAN_EVDD10 3 6 9 45 +LAN_VDD10 1 1 2 2 CL17 0.1U_0402_16V4Z Close to Pin 21 +3V_LAN 8111E@ 8111E@ +LAN_VDDREG 8111E@ 1 LL3 8111E@ 2 0_0603_5% 1 60 mils 8111E@ 1 1 CL19 1 CL20 1 CL21 1 CL22 1 CL23 1 CL24 1 CL25 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z CL29 0.1U_0402_16V4Z 2 8111E@ CL28 4.7U_0603_6.3V6K 8111E@ 2 +LAN_REGOUT CL19, CL20,CL21 close to pin 13,29,45, respectively CL22 close to pin 3, respectively CL23,CL24,CL25 close to pin 6,9,41, respectively 2 0_0603_5% +3V_LAN 12 42 47 48 36 RTL8111E-VB RTL8105E-VL +3V_LAN 1 +3VALW TO +3V_LAN 1 CL684 10U_0805_10V6K 2 2 FOR EMI ISN TEST DEMAND. 1 CL682 1U_0402_6.3V6K LAN Conn. UL3 LAN_MDI0+ LAN_MDI0- 2 3 +3V_LAN rising time (10%~90%) need > 1ms and <100ms. LAN_MDI1+ LAN_MDI1- 1 2 3 4 5 6 7 8 TD+ TDCT NC NC CT RD+ RD- TX+ TXCT NC NC CT RX+ RX- 16 15 14 13 12 11 10 9 RJ45_MIDI0+ RJ45_MIDI0- JLAN 3 RJ45_MIDI1+ RJ45_MIDI1- X'FORM_ LFE8456E 8105E@ UL4 1 2 3 LAN_MDI2LAN_MDI2+ 4 5 6 LAN_MDI1LAN_MDI1+ 7 8 9 LAN_MDI0LAN_MDI0+ 10 11 12 TCT1 TD1+ TD1- MCT1 MX1+ MX1- TCT2 TD2+ TD2- MCT2 MX2+ MX2- TCT3 TD3+ TD3- MCT3 MX3+ MX3- TCT4 TD4+ TD4- MCT4 MX4+ MX4- CL39 1000P_0402_50V7K 2 1 1 8111E@ 2 8111E@ RL11 75_0402_1% 24 23 22 CL40 1000P_0402_50V7K 2 1 1 8111E@ 2 8111E@ RL12 75_0402_1% 21 20 19 CL41 1000P_0402_50V7K 2 1 1 2 RL13 75_0402_1% 18 17 16 CL42 1000P_0402_50V7K 2 1 1 2 RL15 75_0402_1% 15 14 13 RJ45_MIDI3RJ45_MIDI3+ RJ45_MIDI3- 8 PR4- RJ45_MIDI3+ 7 PR4+ RJ45_MIDI1- 6 RJ45_MIDI2- 5 RJ45_MIDI2+ 4 RJ45_MIDI1+ 3 RJ45_MIDI0- 2 RJ45_MIDI0+ 1 1 2 CL34 0.1U_0402_25V4K PR2+ DL1 AZC199-02SPR7G_SOT23-3 @ PR1PR1+ SHLD2 SANTA_130452-C @ 1 CL36 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C 10 AZC199-02SPR7G_SOT23-3 DL2 8/30 Reserve DL1 and DL2 for ESD request RJ45_MIDI0RJ45_MIDI0+ 2 1000P_1808_3KV7K Compal Secret Data 2010/09/03 9 @ RJ45_MIDI1RJ45_MIDI1+ LANGND 1 2 Issued Date B PR3+ SHLD1 SUPERWORLD_SWG150401 8111E@ Security Classification A PR3- RJ45_MIDI2RJ45_MIDI2+ RJ45_GND Place CL34, CL35 colse 1 @ to LAN chip CL35 0.1U_0402_25V4K 2 4 PR2- 2 LAN_MDI3LAN_MDI3+ UL1 8105E-VL 10/100M 8105E@ 2 2 8/30 Add UL3 at DVT 1 SA00003PO30 RL23 0_0402_5% 8105E@ CL27 27P_0402_50V8J 2 CL681 4.7U_0805_10V4Z @ For P/N and footprint Please place them to ISPD page 0 ohm (Pull Down) 1 1 CL26 27P_0402_50V8J NC RL23 2 2 PJ29 JUMP_43X79 @ +3V_LAN 1 1 3 1 @ CL482 0.01U_0402_25V7K LAN_X2 1 1 AO3413_SOT23 2 2 PWM Mode LDO Mode 0 ohm NC (Pull High) 2 1 G 2 D 2 @ QL51 2 2 47K_0402_5% S @ RL432 1 <30> WOL_EN 1 CL683 + 220U_6.3V_M_R16 @ 2 Vgs=-4.5V,Id=3A,Rds<97mohm CL483 @ 0.1U_0402_16V7K 1 25MHZ_20PF_7A25000012 1 1 ENSWREG YL1 LAN_X1 +3VALW 2 RL4 RL4 0_0402_5% 8111E@ +3V_LAN +3VALW RL147 100K_0402_5% @ 1 2 +LAN_EVDD10 1 LL2 RTL8111E-GR_QFN48_6X6 8111E@ 2 0.1U_0402_16V4Z 2 CKXTAL1 HIGH HIGH 2 1 RTL8105E LAN_X1 1 2 4 5 7 8 10 11 RL2 2 RL1 2 3 EC_SWI# 30 32 8111E@ +LAN_REGOUT 1 2 2.2UH +-5% NLC252018T-2R2J-N 2 CLKREQ_LAN# 1 10K_0402_5% 19 20 CLKREQB EECS/SCL EEDI/SDA CL3 to CL6 close to Pin 27,39,47,48 CL7 to CL8 close to Pin 12,42 +LAN_VDD10 LL1 D Title 3 1 10K_0402_5% RL25 2 @ CLK_LAN CLK_LAN# HSIP HSIN 31 37 40 3 RL24 2 @ CLK_LAN CLK_LAN# 1 16 0_0402_5% 25 HSON LED3/EEDO LED1/EESK LED0 2 +3V_LAN 2 RL19 PLT_RST# +3V_LAN HSOP 3 1 23 PCIE_PTX_C_LANRX_P1 17 PCIE_PTX_C_LANRX_N1 18 <16> PCIE_PTX_C_LANRX_P1 <16> PCIE_PTX_C_LANRX_N1 <16> CLKREQ_LAN# 22 2 <16> PCIE_PRX_C_LANTX_N1 CL2 1 1 CL1 1 <16> PCIE_PRX_C_LANTX_P1 CL37 220P_0402_50V6K 1 2 CL38 4.7U_0603_6.3V6K @ 4 Compal Electronics, Inc. PCIe-LAN-RTL8105E/8111E Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet E 26 of 43 5 4 3 D 2 1 D For EMI request 1 @ CC2 2 100P_0402_50V8J @ RC6 48MCLK_CR RC2 6.19K_0402_1% 2 1 <19> USB20_N10 <19> USB20_P10 RC1 RC3 2 2 +3VS +VCC_3IN1 1 2 10_0402_5% 2 @ CC10 1 10P_0402_50V8J 2 UC1 USB20_N10_R USB20_P10_R 1 0_0402_5% 1 0_0402_5% +V1_8 CC7 1U_0402_6.3V6K SDW P_MSCLK SD_DATA1 SD_DATA0 REFE 2 3 DM DP 4 5 6 3V3_IN CARD_3V3 V18 7 XD_CD# 8 9 10 11 12 SP1 SP2 SP3 SP4 SP5 25 CC3, CC4, CC5, CC6, CC7, RC2, RC3, UC1 form CARD@ to mount 1 C GPIO0 17 CLK_IN 24 XD_D7 23 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 22 21 20 19 18 16 15 14 13 EPAD Close to IC 1 0620 --> remove CR_LED# 48MCLK_CR 48MCLK_CR <16> SD_DATA2_MS_DATA5 MS_DATA1_SD_DATA3 < 48MHz > 0620 --> remove CARD-RADER LED SDCMD MS_DATA2_SDCLK SDCD# RTS5137-GR_QFN24_4X4 C 0715 --> change P/N to RTS5137 (SA000043500) < 2 in 1 Card Reader > 0624 --> change CARDREADER conn. JREAD @ D3 1 CMD 2 VSS1 3 VDD 4 CLK 5 VSS2 6 B D0 D1 D2 WP CD 7 8 9 10 11 GND1 GND2 GND3 GND4 12 13 14 15 MS_DATA1_SD_DATA3 SDCMD +VCC_3IN1 MS_DATA2_SDCLK 1 SD_DATA0 SD_DATA1 SD_DATA2_MS_DATA5 SDW P_MSCLK SDCD# 2 1 CC6 0.1U_0402_16V4Z 2 CC5 1U_0402_6.3V6K B TAITW _PSDAT3-09GLAS1N14N For EMI request @ RC4 MS_DATA2_SDCLK 10_0402_5% 2 @ CC8 1 @ CC9 1 10_0402_5% 2 @ RC5 SDW P_MSCLK 1 10P_0402_50V8J 2 1 10P_0402_50V8J 2 A A Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCIe-CardReader RTS5137 Size Document Number Custom Date: Rev 1.0 PWWHA LA-7202P M/B Friday, February 25, 2011 Sheet 1 27 of 43 5 4 Codec 3 600 mA +PVDD1 0.1U_0402_16V4Z 1 2 0_0603_5% 1 1 CA57 CA56 2 +3VS 1 2 RA19 0_0603_5% +1.5VS 1 @ 2 RA20 0_0603_5% 0.1U_0402_16V4Z 1 D 1 CA2 2 RA2 +DVDD_IO Beep sound 0.1U_0402_16V4Z +5VS 1 1 CA44 CA43 2 10U_0603_6.3V6M 2 1 2 10U_0603_6.3V6M EC Beep CA1 +3VS_DVDD 10U_0603_6.3V6M 2 2 D place close to chip PCI Beep 0.1U_0402_16V4Z 2 1 0_0603_1% 1 35 mA <15> PCH_SPKR 1 CA8 CA13 1 2 RA8 1 2 47K_0402_5% 0.1U_0402_16V4Z +AVDD CA7 68 mA 10U_0603_6.3V6M 2 2 RA3 0.1U_0402_16V4Z 1 2 0_0603_5% 10U_0603_6.3V6M MONO_IN +5VS 1 RA1 +3VS RA7 1 2 47K_0402_5% <30> EC_BEEP# CA23 1 2 4.7U_0805_10V4Z <29> MIC1_R_R 1 CA29 Int. Mic LINE2_L LINE2_R 21 22 MIC1_L MIC1_R 16 17 MIC2_L MIC2_R C <13> INT_MIC_DATA <13> INT_MIC_CLK INT_MIC_DATA INT_MIC_CLK 1 CA83 27P_0402_50V8J 2 @ RA46 FBMA-10-100505-301T EC_MUTE# 1 1 CA12 RA45 2 100P_0402_50V8J SENSE_A EC control EC_MUTE# behavior: High-state / low-state 1 2 CA15 2.2U_0603_6.3V6K +MIC1_VREFO_L B CA47 1 2 0.1U_0603_50V7K CA48 1 2 0.1U_0603_50V7K CA49 1 2 0.1U_0603_50V7K CA50 1 2 0.1U_0603_50V7K 1 RA18 32 33 GPIO1/DMIC_CLK SENSE A 18 SENSE B 1 RA12 4.7K_0402_5% place close to chip RA4 RA5 SPKL+ SPKL- <29> <29> SPKR+ SPKR- <29> <29> 75_0402_1% 75_0402_1% HP_L HP_R 2 CA6 <29> <29> 2 CA18 100P_0402_50V8J place close to chip 10 AZ_SYNC_HD <15> BCLK 6 AZ_BITCLK_HD <15> SDATA_OUT 5 AZ_SDOUT_HD <15> SDATA_IN 8 EAPD 47 SPDIFO 48 MONO_OUT 20 AZ_SDIN0_HD_R 29 30 28 VREF 27 AC_VREF JDREF 19 AC_JDREF2 RA9 CBP CBN 31 MIC1_VREFO_L PVSS2 PVSS1 DVSS2 DVSS1 CPVEE 34 AVSS1 AVSS2 26 37 1 33_0402_5% AZ_SDIN0_HD close to Audio Codec(UA1) for EMI R235 4.7K_0402_5% C 2 22P_0402_50V8J @ AZ_SYNC_HD @ 1 2 CA81 22P_0402_50V8J @ <15> AZ_RST_HD# 1 2 22P_0402_50V8J place close to chip MIC2_VREFO 35 2 RA6 @ 1 2 1 R746 10_0402_5% CA80 +3VS CA82 MIC1_VREFO_R LDO_CAP 36 43 42 49 7 1 SYNC RESET# PCBEEP 38 HP_OUT_L HP_OUT_R 3 13 AVDD2 25 AVDD1 39 46 PVDD2 SPK_OUT_R+ SPK_OUT_R- 45 44 GPIO0/DMIC_DATA 12 CA5 @ 2 4.7K_0402_5% MONO_IN 40 41 2 11 <15> AZ_RST_HD# 1 AZ_BITCLK_HD EC_MUTE# 4 PD# <30> EC_MUTE# CA4 2 4.7U_0805_10V4Z 2 <29> MIC1_R_L 14 15 1 2 2 2 2 10U_0603_6.3V6M 0.1U_0402_16V4Z SPK_OUT_L+ SPK_OUT_L- LINE1_L LINE1_R CA3 1 Ext. Mic PVDD1 9 DVDD 23 24 DVDD_IO 1 1 UA1 +MIC1_VREFO_R 1 CA28 2 10U_0603_6.3V6M 1 1 CA14 +MIC1_VREFO_R +MIC1_VREFO_L 1 20K_0402_1% 2 2.2U_0603_6.3V6K 1 CA17 2 2 0.1U_0402_16V4Z CA16 10U_0603_6.3V6M @ 1 2 ALC259-GR_QFN48_7X7 @ CA37 1U_0402_6.3V6K 1 2 @ CA36 1U_0402_6.3V6K B place close to chip DGND AGND 2 0_0603_5% RA18 CLOSE TO ALC259 Sense Pin Impedance Codec Signals Function 39.2K PORT-I (PIN 32, 33) Headphone out 20K PORT-B (PIN 21, 22) Ext. MIC 10K PORT-C (PIN 23, 24) place close to chip <29> MIC_SENSE SENSE A <29> 5.1K A SENSE B NBA_PLUG 2 RA10 1 20K_0402_1% RA21 39.2K_0402_1% SENSE_A (PIN 48) 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-H (PIN 20) A Int. MIC Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HDA-ALC259 Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 28 of 43 Speaker Connector Ext. Mic RA31 1K_0402_5% 2 1 <28> MIC1_R_L placement near Audio Codec UA1 <28> SPKR+ SPKR+ RA30 2 1 0_0603_5% 2 1 1K_0402_5% RA22 <28> MIC1_R_R 2 RA32 1 2.2K_0402_5% MIC1_L 2 RA33 1 2.2K_0402_5% +MIC1_VREFO_L MIC1_R +MIC1_VREFO_R SPK_R1 1 CA25 @ 470P_0402_50V8J 2 2 1 CA26 @ 470P_0402_50V8J 2 1 0_0603_5% 1 CA27 1U_0402_6.3V6K @ RA34 RA35 2 1 0_0603_5% SPK_L1 1 CA19 @ 470P_0402_50V8J 2 2 1 CA20 RA36 @ 470P_0402_50V8J 2 2 1 0_0603_5% SPK_L2 HeadPhone/LINE Out JACK JLINE @ DA4 5 PJDLC05_SOT23-3 3 2 JSPK SPK_L1 SPK_L2 SPK_R1 SPK_R2 1 2 3 4 @ DA5 PJDLC05_SOT23-3 3 4 <28> NBA_PLUG 1 <28> HP_R <28> HP_L LA6 1 2 HP_R_L KC FBM-L11-160808-121LMT 0603 LA7 1 2 HP_L_L KC FBM-L11-160808-121LMT 0603 1 2 3 4 3 6 2 1 2 CA45 100P_0402_50V8J CA46 100P_0402_50V8J CA11 @ 2 0.1U_0402_16V4Z DA6 @ PJDLC05_SOT23-3 1 2 10 9 8 7 FOX_JA63331-B39S4-7F @ 1 3 1 ACES_85204-0400N @ For EMI Ext.MIC/LINE IN JACK JEXMIC 5 4 <28> MIC_SENSE MIC1_R MIC1_L LA8 1 2 MIC1_L_R KC FBM-L11-160808-121LMT 0603 LA9 1 2 MIC1_L_L KC FBM-L11-160808-121LMT 0603 3 6 2 1 3 1 2 CA41 100P_0402_50V8J CA42 100P_0402_50V8J 10 9 8 7 FOX_JA63331-B39S4-7F @ 1 DA7 @ PJDLC05_SOT23-3 1 2 6 3 SPKL- 4 SPKL- CA24 1U_0402_6.3V6K @ 5 <28> 1 7 8 GND GND SPKL+ SPK_R2 1 2 6 3 SPKL+ 2 4 <28> SPKR- 5 SPKR- 7 8 GND GND <28> CA21 2 0.1U_0402_16V4Z For EMI Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title AUDIO AMP/MIC/SPK/VR Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 29 of 43 2 1 R737 0_0402_5% 2 1 2 2 0.1U_0402_16V4Z C441 1000P_0402_50V7K 1 1 1000P_0402_50V7K U19 1 R377 10_0402_5% @ <20> GATEA20 <20> KB_RST# <15,31> SERIRQ <15,31> LPC_FRAME# <15,31> LPC_AD3 <15,31> LPC_AD2 <15,31> LPC_AD1 <15,31> LPC_AD0 2 D C443 22P_0402_50V8J @ 1 2 <19> CLK_PCI_EC <5,19,25,26,31> PLT_RST# +3VL R378 47K_0402_5% 2 1 2 C444 <20> EC_SCI# GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 2 3 4 5 7 8 10 CLK_PCI_EC PLT_RST# ECRST# EC_SCI# 12 13 37 20 38 ECRST# 1 0.1U_0402_16V4Z C <31> <31> KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 KSI[0..7] KSI[0..7] KSO[0..17] KSO[0..17] RP7 +3VL +3VS 1 2 3 4 8 7 6 5 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <35> <35> <16> <16> 2.2K_0804_8P4R_5% EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ# LPC_FRAME#/LFRAME# LPC_AD3/LAD3 LPC_AD2/LAD2 LPC_AD1/LAD1 LPC_AD0/LAD0 PWM0/GPIO0F BEEP#/PWM1/GPIO10 FANPWM0/GPIO12 ACOFF/FANPWM1/GPIO13 BATT_TEMP/AD0/GPI38 BATT_OVP/AD1/GPI39 ADP_I/AD2/GPI3A AD3/GPI3B AD Input AD4/GPI42 AD5/GPI43 LPC & MISC CLK_PCI_EC/PCICLK PCIRST#/GPIO05 EC_RST#/ECRST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D <17> PCH_SUSPWRDN @ <5> FAN_SPEED1 PLT_RST# 2 1U_0402_6.3V6K 1 C819 <25> E51_TXD <25> E51_RXD <32> ON/OFFBTN# <32> PWR_LED# <31> NUM_LED# @ 1 C820 SUSP# 2 180P_0402_50V8J B <17> EC_MUTE#/PSCLK1/GPIO4A USB_EN#/PSDAT1/GPIO4B CAP_INT#/PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F PS2 Interface SDICS#/GPXIOA00 WOL_EN/SDICLK/GPXIOA01 ME_EN/SDIMOSI/GPXIOA02 LID_SW#/GPXIOD00 122 123 2 930@ 1 R743 0_0402_5% SPI Flash ROM GPIO 2 SPIDI/MISO SPIDO/MOSI SPICLK/GPIO58 SPICS# GPIO40 H_PECI/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 PWR_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_SMI#/GPIO08 EC_ON/GPXIOA05 GPIO0A EC_SWI#/GPXIOA06 GPIO0B ICH_PWROK/GPXIOA07 GPIO GPIO0C BKOFF#/GPXIOA08 GPO RF_OFF#/GPXIOA09 SUS_PWR_DN_ACK/GPIO0D INVT_PWM/PWM2/GPIO11 GPXIOA10 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 ON_OFF/GPIO18 ENBKL/GPXIOD02 SUSP_LED#/GPIO19 EAPD/GPXIOD03 GPI EC_THERM#/GPXIOD04 NUM_LED#/GPIO1A SUSP#/GPXIOD05 PBTN_OUT#/GPXIOD06 EC_PME#/GPXIOD07 XCLK1 XCLK0 V18R 1 R1446 100K_0402_5% 930@ C899 20P_0402_50V8J 2 930@ 21 23 26 27 63 64 65 66 75 76 EC_BEEP# FANPWM ACOFF EC_BEEP# <28> FANPWM <5> ACOFF <36> BATT_TEMPA ADP_I ADP_V 68 70 71 72 IREF CHGVADJ 83 84 85 86 87 88 EC_MUTE# USB_EN# 97 98 99 109 VGATE WOL_EN PWRME_CTRL# LID_SW# 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI SPI_CLK_R SPI_CS# H_PROCHOT#_EC TP_CLK TP_DATA 73 74 89 90 91 92 93 95 121 127 100 101 102 103 104 105 106 107 108 110 112 114 115 116 117 118 124 3 D 2 100P_0402_50V8J 2 100P_0402_50V8J 10K_0402_5% 2 @ +5VS TP_CLK 1 R379 TP_DATA 1 R381 VGATE <5,17,41> WOL_EN <26> PWRME_CTRL# <15> LID_SW# <31> SPI_CLK_R EC_SI_SPI_SO <31> EC_SO_SPI_SI <31> SPI_CS# 2 R738 1 0_0402_5% C449 33P_0402_50V8J @ <31> 1 930@ 2 R461 43_0402_1% FSTCHG <36> BATT_FULL_LED# <32> CAPS_LED# <31> BATT_CHG_LOW_LED# <32> SYSON VR_ON ACIN_D SYSON VR_ON PCH_RSMRST# EC_LID_OUT# EC_ON 2 4.7K_0402_5% 2 4.7K_0402_5% For EMI EC_PECI FSTCHG BATT_FULL_LED# CAPS_LED# BATT_CHG_LOW_LED# PM_PWROK BKOFF# R758 1 H_PECI SYSON C 2 1 R5 2 4.7K_0402_5% R341 330K_0402_5% 1 2 +3VL PM_PWROK <5,17> BKOFF# <13> <31> <5> <38> <41> PCH_RSMRST# <17> EC_LID_OUT# <16> EC_ON <32> SPI_CLK 1 D21 2 ACIN_D 1 ACIN <17,36> RB751V40_SC76-2 SA_PGOOD SA_PGOOD <39> @ 2 R740 UMA_ENBKL 1 0_0402_5% UMA_ENBKL <18> To avoid current leakage SUSP# PBTN_OUT# USB_OC#0_R SUSP# <33,38,40> PBTN_OUT# <5,17> B +EC_V18R SUSP# R423 2 1 10K_0402_5% VR_ON R462 2 1 10K_0402_5% Co-lay KB9012 with KB930 0.1U_0402_16V4Z SLP_S5# 9012@ 2 R744 1 EC_PECI 0_0402_5% 9012@ 2 R742 1 0_0402_5% R744 close to R461 IN2 2 R739 H_PROCHOT#_EC TP_CLK <32> TP_DATA <32> C818 @ 1 4 1 C445 1 C446 EC_MUTE# <28> USB_EN# <24> USB_OC#0_RR O C518 47P_0402_50V8J <35,36> <36> C448 4.7U_0805_10V4Z P 5 2 <17> PM_SLP_S4# U44 IN1 ACIN_D KB930QF-A1_LQFP128_14X14 G 1 <17> PM_SLP_S5# Q41 2 G BATT_TEMPA EN_DFAN1 <5> IREF <36> CHGVADJ <36> +3VALW 2 S 2N7002_SOT23 <5,35> BATT_TEMPA <35> ADP_I ADP_V SPI Device I/F EC_SMB_CK1/SCL0/GPIO44 EC_SMB_DA1/SDA0/GPIO45 EC_SMB_CK2/SCL1/GPIO46 EC_SMB_DA2/SDA1/GPIO47 1 Close to EC CLK_EC DAC_BRIG/DA0/GPO3C EN_DFAN1/DA1/GPO3D IREF/DA2/GPO3E DA3/GPO3F DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 GND GND GND GND GND EC_SMI# 6 14 15 16 17 USB_OC#0_RR 18 PCH_SUSPWRDN 19 25 FAN_SPEED1 28 29 E51_TXD 30 E51_RXD 31 ON/OFFBTN# 32 PWR_LED# 34 NUM_LED# 36 D +3VS 11 24 35 94 113 <20> PM_SLP_S3# SLP_S5# EC_SMI# H_PROCHOT#_EC H_PROCHOT# 930@ PWM Output SM Bus <17> PM_SLP_S3# VR_HOT# 0.1U_0402_16V4Z VCC VCC VCC VCC VCC VCC CLK_PCI_EC <41> C442 1 2 2 C440 67 2 2 C439 AVCC 2 1 C438 AGND 0.1U_0402_16V4Z For EMI 0.1U_0402_16V4Z 1 C437 69 1 9 22 33 96 111 125 0.1U_0402_16V4Z 1 C436 1 +3VL 2 3 +3VL 1 4 3 5 SN74AHC1G08DCKR_SC70-5 @ USB_OC#0_R 1 0_0402_5% 2 930@ 1 R741 0_0402_5% USB_OC#0 <19,24> 1 9012@ 2 H_PECI R475 43_0402_1% U19 9012@ A A 1 R342 E51_TXD 2 100K_0402_5% EC KB9012 A1 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title LPC-EC-KB930 Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 30 of 43 SPI Flash (256KB) Lid SW Place the PAD under DDR DIMM. LPC Debug Port +3VL +3VL R403 2 0_0402_5% 1 20mils <30> SPI_CS# SPI_CS# 1 S SPI_CLK 6 <30> SPI_CLK <30> EC_SO_SPI_SI C EC_SO_SPI_SI 5 D U21 APX9132ATI-TRL_SOT23-3 Q 2 2 EC_SI_SPI_SO 1 2 R394 1 930@ 2 1 10_0402_5% C454 VDD EC_SI_SPI_SO <30> W 25X10BVSNIG_SO8 SPI_CLK R401 2 0_0402_5% <15,30> SERIRQ VOUT C453 0.1U_0402_16V4Z 1 R392 2 0_0402_5% 7 4 PLT_RST# <5,19,25,26,30> <15,30> LPC_AD3 R383 47K_0402_5% 8 3 LPC_AD2 <15,30> <15,30> LPC_AD1 9 2 LPC_AD0 <15,30> 10 1 <15,30> LPC_FRAME# 3 LID_SW # CLK_PCI_DDR <19> <30> 2 HOLD 1 5 DEBUG_PAD 1 C452 10P_0402_50V8J R393 22_0402_5% @ 1 W 7 @ +3V_LID 4 @ +3VALW 1 3 930@ VSS H7 6 2 VCC GND U22 8 2 1 C451 0.1U_0402_16V4Z 930@ 1 +3VS 2 2 2 930@ 10P_0402_50V8J C457 22P_0402_50V8J 1 @ For EMI For EMI For EMI Close to JKB KSO16 KSO17 KSO2 KSO1 KSO0 KSO4 KEYBOARD CONN. KSO3 KSO5 KSI[0..7] KSO[0..17] KSI[0..7] <30> KSO14 KSO[0..17] <30> KSO6 KSO7 JKB 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ACES_88170-3400 @ JKB34 KSO16 1 2 R372 300_0402_5% +3VS KSO13 KSO8 KSO17 KSO9 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4 2 1 CAPS_LED# R376 300_0402_5% NUM_LED# KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 +3VS CAPS_LED# <30> NUM_LED# <30> CAPS_LED# NUM_LED# 1 C401 1 C402 1 C404 1 C405 1 C406 1 C407 1 C408 1 C409 1 C410 1 C411 1 C412 1 C413 1 C415 1 C416 1 C417 1 C418 1 C419 1 C420 1 C421 1 C422 1 C423 1 C424 1 C425 1 C427 1 C429 1 C431 1 C433 1 C435 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title SPI ROM/LID/Debug/KB Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 31 of 43 5 4 51_ON# ON/OFFBTN# TOP side 1 EC_ON ON/OFFBTN# <30> S Q7 2N7002_SOT23-3 2 G LEFT SW_L R396 10K_0402_5% C458 0.1U_0402_25V6 @ 1 SW1 1 3 JTOUCH @ 4 1 2 6 5 2 1 <30> 2 1 100K_0402_5% D 3 R395 For debug 2 TP Button/Conn. <34> 2 Power Button SW3 3 +3VL <30> <30> @ 1 3 2 4 1 2 3 4 5 6 +5VS SMT1-05_4P TP_CLK TP_DATA SW_L SW_R D BTM side For EMI request RIGHT SW_R 6 5 SMT1-05-A_4P 2 SW4 3 2 4 2 6 5 1 7 8 G7 G8 D P-TWO_161021-06021_6P-T 1 3 D19 @ AZ5125-02S.R7G_SOT23-3 SMT1-05_4P 0816->change JTOUCH connector ON/OFFBTN# D20 @ AZ5125-02S.R7G_SOT23-3 3 2 D83 @ AZ5125-02S.R7G_SOT23-3 1 JPOWER @ 1 1 2 2 3 3 4 4 5 G1 6 G2 3 PWR/B to MB Conn. 1 2 3 4 5 6 ACES_85201-0405N 1 For EMI request For ESD Screw Hole H12 H_3P0 @ H13 H_3P0 @ H14 H_3P0 @ H_3P0 @ 1 H11 H_3P0 @ 1 1 1 H10 H_3P0 @ 1 H9 H_3P0 @ 1 H8 H_3P0 @ 1 H6 Vf=1.9V~2.4V If=5mA 1 POWER/SUSPEND LED D22 2 2 510_0402_5% YG 1 PWR_LED# <30> H1 H26 H_2P7x3P2N @ HT-110UYG5_YELLOW GREEN 1 3 1 R398 C H_2P7N @ 1 +5VALW C SB BATT CHARGE/FULL LED H15 1 H_4P2x4P7 @ 1 H_4P7 @ H20 H_4P2x4P7 @ H_5P0N @ 1 H22 1 H21 H_4P2 @ 1 H23 1 Vf=1.8V~2.0V If=5mA(max) H16 H_5P0N @ CPU D25 A 1 2 1 R399 2 3 1 R404 2 YG 510_0402_5% BATT_CHG_LOW_LED# <30> MINI CARD -- WLAN 510_0402_5% BATT_FULL_LED# <30> H18 H19 H_3P3 @ 1 HT-210UD5-UYG5_AMBER-YEL GRN H_3P3 @ 1 +5VALW B B PCB Fedical Mark PAD 1 1 FD3 @ FD4 @ 1 FD2 @ 1 FD1 @ ISPD U2 Q65R1@ ZZZ PCH PCB LA-7202P PJP1 45@ PJP1 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PWR&TP CON/LED/ISPD Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 32 of 43 A B C +3VALW TO +3VS +3VALW +3VS D +5VALW TO +5VS +1.5V to +1.5VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW Vgs=10V,Id=9A,Rds=18.5mohm E +1.8VS +1.5V +5VS +1.5VS 2 3 1 1 1 D FDS6676AS_SO8 PS3@ Q12A S 3 2 R414 820K_0402_5% 470_0805_5% R408 1 R411 2 +VSB 220K_0402_5% Q31 Q12B SUSP 2 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 Q190 SUSP 2 G 2N7002_SOT23-3 1 4 C469 2 6 1 1 1 2 1 @ 2 R470 470_0805_5% 1 C464 C463 1U_0402_6.3V6K 2 1 C821 C470 @ 2 D S 1 D S 2 D S 3 4 D G SI4800BDY_SO8 0.1U_0402_25V6 1 C822 1 WPS3@ 8 7 6 5 4.7U_0805_10V4Z Q11B OLS@ 2 0.1U_0402_16V4Z For EMI 0.1U_0402_16V4Z 2 Q31 470_0805_5% OLS@ Q11A OLS@ SUSP 2 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R413 200K_0402_5% @ 3 1 1 C468 2 +VSB Vgs=10V,Id=14.5A,Rds=6mohm 4 C467 2 R407 6 OLS@ 2 OLS@ 1 R410 2 47K_0402_5% 1 Q10B SUSP 2 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 C461 1U_0402_6.3V6K 2 Q10A OLS@ D S 1 D S 2 D S 3 4 D G SI4800BDY_SO8 OLS@ 1 1 OLS@ 0.01U_0402_25V7K +VSB 4.7U_0805_10V4Z 2 R412 330K_0402_5% OLS@ 2 R406 470_0805_5% OLS@ 2 1 Q30 8 7 6 5 4 6 1 C466 1 4.7U_0805_10V4Z OLS@ 1 R409 2 47K_0402_5% 1 C465 2 2 C460 C459 1U_0402_6.3V6K 2 4.7U_0805_10V4Z 1 OLS@ 0.022U_0402_25V7K D S 1 D S 2 D S 3 4 D G SI4800BDY_SO8 OLS@ 1 1 3 1 1 Q29 8 7 6 5 2 4.7U_0805_10V4Z +5VS 4.7U_0805_10V4Z 1 C462 +5VS TO +5VS_ODD +5VS +3VALW +5VS_ODD 2 2 2 <40> R421 22_0805_5% R468 470_0805_5% D <30,38,40> SUSP# D 2 G Q61 2N7002_SOT23-3 S 1 Q189 SUSP 2 G 2N7002_SOT23-3 1 1 SUSP 1 <5,9,25,40> SUSP D S 2 G 2 Q60 2N7002_SOT23-3 S 1 C680 1U_0402_6.3V6K @ Q44B 2N7002DW-T/R7_SOT363-6 PS3@ 5 3 Q44A 2N7002DW-T/R7_SOT363-6 PS3@ SUSP 2 0.75VR_EN 1 PS3@ 1 2 R158 100K_0402_5% 1 3 2 1 2 R422 100K_0402_5% 1 2 <39,40> VCCPPWRGD 1 C679 4.7U_0805_10V4Z @ 0.75VR_EN# 3 1 2 2N7002DW-T/R7_SOT363-6 +1.05VS_VCCP 3 AO3413_SOT23 C217 0.01U_0402_25V7K 1 @ +0.75VS 4 2 ODD_EN# PJ28 JUMP_43X79 @ +5VS_ODD 6 47K_0402_5% Q53A @ 2 1 2N7002DW-T/R7_SOT363-6 2 1 1 1 2 6 3 3 @R440 @ R440 1 5 2 1 4 ODD_EN# +5VALW R425 100K_0402_5% PS3@ Vgs=-4.5V,Id=3A,Rds<97mohm G <20> C471 0.1U_0402_16V7K @ 1 @ Q45 2 D @ Q53B 2 @ R441 10K_0402_5% S @ R457 470_0805_5% 2 For S3 CPU Power Saving +5VS 2 +3VS +3VALW +5VALW Each 250pF on CAP_MOS1 (2) will make Slew Rate(uS/V) increase of 100uS/V +5VS U46 1 R415 2 1 0_0402_5% NLS@ @ 0.01U_0402_25V7K C496 SUSP# 3 MOS1_D +3VS NLS@ MOS1_S 10 1 2 2 3 ON_MOS1 CAP_MOS1 5_VDD GND 3 9 1 8 C236 0.1U_0402_16V4Z @ 2 4 ON_MOS2 CAP_MOS2 1 C249 0.1U_0402_16V4Z @ 2 7 +5VALW 5 MOS2_D MOS2_S NLS@ 4 11 SLG59M232VTR_TDFN14-10_3X2 1 2 C252 120P_0402_50V4Z NLS@ 1 C255 0.1U_0402_16V4Z @ 2 1 @ 2 R419 1 0_0402_5% 0.01U_0402_25V7K C499 SUSP# 2 NLS@ 0.01U_0402_25V7K C500 GND 1 6 2 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC-DC INTERFACE Size Document Number Rev 1.0 PWWHA LA-7202P M/B Date: Sheet Friday, February 25, 2011 E 33 of 43 A B C D 1 DC_IN_S1 1 @ PJP1 PD1 2 N3 1 1 2 B+ @ PR2 1K_1206_5% RLS4148_LL34-2 2 @PR3 1K_1206_5% 1 1 @ PR5 2.2M_0402_5% 2 1 PR38 @ 511K_0402_1% 1 2 1 1 2 <36> 2 <36> 1 3 1 VS 2 1 PC6 8 + 3 - 2 O LM393DG_SO8 +5VALW P @ PQ2 DTC115EUA_SC70-3 3 2 22K_0402_1% 2 P PU2A 1 G PC5 0.1U_0603_25V7K 4 2 0.22U_0603_25V7K 2 2 PACIN S N1 2 1 51_ON# 2 G SSM3K7002FU_SC70-3 2 2 @ PQ1 PR11 <32> PC14 @ 1000P_0402_50V7K @ PR39 47K_0402_1% 2 1 D PR9 68_1206_5% 1 PR10 100K_0402_1% PR35 @ 255K_0402_1% PR36 @ 150K_0402_1% 1 3 1 PR6 @ 34K_0402_1% @ PR7 66.5K_0402_1% 2 1 N1 1 RLS4148_LL34-2 @ PC13 1000P_0402_50V7K 1 2 BATT+ 2 2 1 1 1 @ PC16 1000P_0402_50V7K PR8 68_1206_5% TP0610K-T1-E3_SOT23-3 6 1 PD3 RLS4148_LL34-2 PD4 5 - 2 2 LM393DG_SO8 PQ4 + O 6251VREF 7 1 ACON P EN0 <36> G <37> 4 VIN @ PU2B 8 N1 @ PD2 RB715F_SOT323-3 2 1 3 2 VL @ PR4 100K_0402_1% 1 2 2 1 1 PC4 100P_0402_50V8J 2 1 PC3 1000P_0402_50V7K SINGA_2DW -0005-B03 2 4 1 3 - 2 - 2 1 VIN 2 @ PR1 1K_1206_5% 10A_125V_451010MRL PC2 100P_0402_50V8J 2 1 1 + PC1 1000P_0402_50V7K + DC_IN_S2 2 VIN PL1 SMB3025500YA_2P 1 2 PF1 @ @ @ 2 +3VALW P @ PJ333 +3VLP 2 2 1 2 PJ332 1 1 +3VALW JUMP_43X118 1 +3VL JUMP_43X39 (5A,200mils ,Via NO.= 10) OCP=8.6A 2 (100mA,40mils ,Via NO.= 2) 2 +5VALW P 3 @ PJ152 1 1 2 JUMP_43X118 @ PJ352 2 1 1 +5VALW +1.5VP 2 @ PJ153 1 1 2 +1.5V JUMP_43X118 JUMP_43X118 (5A,200mils ,Via NO.= 10) OCP=7.9A (16A,640mils ,Via NO.= 32) 3 @ PJ72 +VSBP 2 2 1 1 +VSB JUMP_43X39 @ PJ182 2 +1.8VSP (120mA,40mils ,Via NO.= 1) 2 2 1 1 1 @ PJ402 1 2 +1.8VS JUMP_43X118 2 1 1 JUMP_43X118 (1.65A,70mils ,Via NO.= 4) OCP=4.2A @ PJ76 +0.75VSP 2 @ PJ403 +1.05VS_VCCPP +0.75VS 2 2 1 1 +1.05VS_VCCP JUMP_43X118 JUMP_43X79 (1A,40mils ,Via NO.= 2) +VCCSAP 2 @ PJ452 2 1 1 +VCCSA JUMP_43X118 (17A,680mils ,Via NO.=34) (6A,240mils ,Via NO.= 12) 2 @ PJ502 1 1 2 JUMP_43X118 +GFX_COREP 2 @ PJ503 1 1 2 ACIN Precharge detector Min. typ. Max. H-->L 14.42V 14.74V 15.23V L-->H 15.39V 15.88V 16.39V +GFX_CORE JUMP_43X118 4 (33A,1320mils ,Via NO.=66) OCP=40A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title DCIN/VIN DECTOR Size Date: Document Number PWWHA LA-7202 M/B Sheet Friday, February 25, 2011 D 34 of Rev 1.0 43 4 A B C VMB 1 @ PJP2 1 2 PH1 under CPU botten side : CPU thermal protection at 95 degree C Recovery at 56 degree C BATT+ 1 PC7 1000P_0402_50V7K PC8 0.01U_0402_25V7K 2 SUYIN_200045MR009G171ZR @ PC15 .1U_0402_16V7K 2 PR14 1K_0402_1% 2 1 BATT_P4 BATT_P5 EC_SMDA EC_SMCA 1 15A_65V_451015MRL 2 1 PC9 0.1U_0603_25V7K PR15 19.6K_0402_1% 2 +3VL 2 2 VCC TMSNS1 8 2 GND RHYST1 7 3 OT1 TMSNS2 6 4 OT2 RHYST2 5 PR22 3.48K_0402_1% 1 1 <30,36> 100K_0402_1%_NCP15W F104F03RC BATT_TEMPA <30> VS_ON 1 1 <37> G718TM1U_SOT23-8 EC_SMB_DA1 <30> 2 PR21 100_0402_1% 1 2 PR28 3.09K_0402_1% 1 PR20 100_0402_1% 2 PH1 2 2 2 2 ADP_I 1 1 PR18 8.66K_0402_1% PU1 PR19 1K_0402_1% 1 PR16 6.49K_0402_1% 2 1 3 2 VL 1 1 1 PD6 PJSOT24C_SOT23-3 PD5 2 PJSOT24C_SOT23-3 3 2 GND GND GND GND BATT_S1 1 2 3 4 5 6 7 8 9 1 10 11 12 13 1 PL2 SMB3025500YA_2P 1 2 PF2 1 2 3 4 5 6 7 8 9 D PR27 100K_0402_1% 1 EC_SMB_CK1 <30> D PQ7 SSM3K7002FU_SC70-3 2 1 2 3 @ PJ334 2 PR29 10K_0402_1% 2 G S 2 1 <5,30> H_PROCHOT# +3VS 1 JUMP_43X39 PQ5 TP0610K-T1-E3_SOT23-3 3 B+ Adapter 1 +VSBP Throttle Watt Recovery Watt Throttle Point Recovery Point 65W_UMA 71.25W 62.4W 1.48V 1.308V 75W_DIS 85.5W 72W 1.78V 1.5V 75W_QCore 85.5W 72W 1.78V 1.5V 2 1 PR25 100K_0402_1% PR24 1 2 @ 2 1 2 VL PC10 0.22U_0603_25V7K 3 2 1 PR23 100K_0402_1% 3 PC11 @ 0.1U_0603_25V7K 2 1 D 3 1 22K_0402_1% S PR26 <17,37> 1 POK 2 PQ6 SSM3K7002FU_SC70-3 2 G @ PC12 .1U_0402_16V7K 2 1 0_0402_5% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Document Number Rev 1.0 PWWHA LA-7202 M/B Date: Friday, February 25, 2011 Sheet D 35 of 43 1 2 4 CELLS CSOP 21 5 ICOMP CSIN 20 PR2312 1 IREF 2 2 PR221 120K_0402_1% PC216 1 ACON 1 <34> PQ213 DTC115EUA_SC70-3 ACOFF 2 PHASE LX_CHG VREF UGATE 17 DH_CHG 6251VREF 1 2 CHLIM BOOT 4 1 2 1 2 16 BST_CHG 1 2 2.2_0603_1% 10 ACLIM VDDP 15 6251VDDP 11 VADJ LGATE 14 DL_CHG 12 GND PGND 13 BATT+ 4 PR206 4.7_1206_5% 3 0.02_1206_1% 4 0.1U_0603_25V7K PD202 RB751V-40_SOD323-2 1 2 6251VDD PR233 PC221 4.7U_0603_6.3V6M PR235 2 PQ202 AO4466L_SO8 PC205 BST_CHGA 2 1 75K_0402_1% PR223 20K_0402_1% PL202 10UH_MSCDRI-104A-100M-E_4.6A_20% CHG CHG1 1 2 5 6 7 8 9 6251aclim S 2 2 2_0402_5% PR205 PR222 PQ216 SSM3K7002FU_SC70-3 PC206 680P_0603_50V7K @ 4.7_0603_5% 2 ACOFF 8 ICM 18 D 2 G ISL6251AHAZ-T_QSOP24 3 <30> 6251VREF 6251VREF 19 PACIN PQ201 AO4466L_SO8 2 <34> PR220 154K_0402_1% .1U_0402_16V7K 2 1 PC220 0.1U_0603_25V7K 1 PR232 CSIP VCOMP CSOP 4 1 S 7 CSON 1 20_0402_5% 2 4 ADP_I PC215 1 2 <30> 6 PR219 1 2 100_0402_1% PR229 20_0402_5% 1 2 PC219 0.047U_0402_16V7K 1 2 PR230 20_0402_5% PC204 10U_1206_25V6M 2 1 22 PC222 1 CSON 2 PACIN <30,35> 2 2 3 EN 6800P_0402_25V7K 10K_0402_1% 1 1SS355_SOD323-2 0.1U_0402_25V6 1 <34> PR211 22K_0402_5% 1 2 1 0.01U_0402_25V7K PR218 2 PC203 10U_1206_25V6M 2 1 23 1 D 5 G PACIN PC214 1 2 1 PQ212B DMN66D0LDW -7_SOT363-6 PQ215 DTC115EUA_SC70-3 PC202 10U_1206_25V6M 2 1 ACSET ACPRN 3 VIN PD10 1 2 2 200K_0402_1% PR228 14.3K_0402_1% 0.1U_0603_25V7K ACPRN 2 PC213 1 2 PQ212A DMN66D0LDW -7_SOT363-6 0.01U_0402_25V7K S 2 3 1 2 G 1 PR290 3 DCIN 2 ACOFF 2 1 24 1 1SS355_SOD323-2 1 1 2 2 DCIN VIN 47K_0402_1% 1.26V 3 2 1 D PC217 1000P_0402_25V8J 2 1 1 1 6251_EN ACSETIN 2 PD9 PR237 10K_0402_1% PC218 VDD 2 1 2 2 100K_0402_1% 1 PR236 1 5 6 7 8 6251VDD PU200 1 PR217 PR213 150K_0402_1% PQ211 DTC115EUA_SC70-3 PR227 10_1206_5% 3 6 2 FSTCHG 1 1 1 <30> PR216 10K_0402_1% 2 1 1 2 PR226 191K_0402_1% PD201 RB751V-40_SOD323-2 1 ACSETIN LDO 5.075V 2 PR212 200K_0402_1% PC212 2.2U_0603_6.3V6K 1 2 3 PC210 0.1U_0603_25V7K 2 1 2 PQ210 DTA144EUA_SC70-3 1 1 PR210 47K_0402_1% PC211 5600P_0402_25V7K 2 CSIP VIN 1 3 CHG_B+ 2 2 8 7 6 5 PL210 1 2 1.2UH_1231AS-H-1R2N=P3_2.9A_30% CSIN 3 2 1 4 PC233 4.7U_0805_25V6-K 2 1 B+ 1 2 1 P3 8 7 6 5 4 4 1 2 3 PC232 4.7U_0805_25V6-K 2 1 PQ204 AO4409L_SO8 P2 1 2 3 1 2 3 PC231 4.7U_0805_25V6-K 2 1 8 7 6 5 VIN PR215 0.02_1206_1% D PQ208 AO4435L_SO8 PC209 10U_1206_25V6M 2 1 PQ203 AO4435L_SO8 C PC208 10U_1206_25V6M 2 1 B PC207 10U_1206_25V6M 2 1 A PR224 <30> CHGVADJ 1 2 15.4K_0402_1% 3 2 3 PR225 31.6K_0402_1% 6251VDD 1 ACIN PACIN 2 CHGVADJ 0V 4.2V 1.882V 4.35V 3.2935V CP mode Iada=0~3.42A(65W) .1U_0402_16V7K 47K_0402_1% Vin Detector 3 4V 4 PC223 PR248 PR243 14.3K_0402_1% CHGVADJ=(Vcell-4)*9.445 <30> 2 2 ADP_V 2 ACPRN 1 1 VCHLIM need over 95mV 1 PQ214 DTC115EUA_SC70-3 IREF=0.254V~3.048V Vcell PR247 10K_0402_1% 1 2 1 IREF=1.016*Icharge <17,30> PR246 309K_0402_1% 2 2 PR242 10K_0402_1% 2 PR240 47K_0402_1% CC=0.25A~3A PR241 10K_0402_1% 1 2 1 1 1 VIN High 18.089V Low 17.44V 4 1.26 / 14.3 * 205.3 = 18.089V CP= 92%*Iada; CP=3.147A Vaclim=1.08V(65W) PR222=75k PR223=20k Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A Vaclim=0.736V(75W) PR222=24k PR223=20k A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification PR215=0.02 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PR215=0.02 B C Title CHARGER Size Document Number Custom Date: Rev 1.0 PWWHA LA-7202 M/B Friday, February 25, 2011 D Sheet 36 of 43 5 4 3 2 1 2VREF_8205 D 2 PC363 1U_0603_10V6K 1 D PR364 30K_0402_1% 1 2 PR363 20K_0402_1% 1 2 PR365 19.1K_0402_1% 1 2 1 5 6 7 8 LL2 LL1 20 LX_5V LG_3V 12 DRVL2 DRVL1 19 LG_5V PQ352 AO4712L_SO8 + PC356 680P_0603_50V7K 2 1 VL RT8205_B+ PQ360B DMN66D0LDW -7_SOT363-6 PC364 4.7U_0805_10V6K B Ipeak=5A Imax=3.5A F=245KHz Total Capacitor 150uF 2 PR361 2 2 1 PC352 330U_6.3V_M 1 TPS51125ARGER_QFN24_4X4 2 4 1 VIN PL352 4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% +5VALWP 1 2 PR356 4.7_1206_5% VCLK 18 17 16 3 2 1 21 AO4466L_SO8 5 6 7 8 DRVH1 VREG5 DRVH2 11 PC355 2 0.1U_0603_25V7K 3 2 1 2 1 ENTRIP1 3 VREF VFB1 4 10 LX_3V 1 <17,35> 2 S DMN66D0LDW -7_SOT363-6 1 VFB2 UG_3V PR355 BST_5V 1 2 0_0603_5% UG_5V 1 D 5 G S TONSEL 22 1 3 6 2 5 23 ENTRIP2 4 ENTRIP1 G POK VBST1 EN0 PC362 1U_0402_6.3V6K D 24 1 2 Ipeak=5A Imax=3.5A F=305KHz Total Capacitor 150uF PQ360A 4 VO1 PGOOD PR360 499K_0402_1% 1 2 B+ C VBST2 2VREF_8205 2 AO4712L_SO8 PQ351 VREG3 EN0 <34> 6 2 PC366 10U_1206_25V6M 9 13 PC336 680P_0603_50V7K 2 PR357 150K_0402_1% 1 2 8 100K_0402_5% 2 4 1 + 330U_6.3V_M RT8205_B+ BST_3V GND 8 7 6 5 1 VO2 PR336 4.7_1206_5% 1 2 3 PC332 PQ332 7 SKIPSEL PL332 4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% 1 2 1 B PR335 1 2 0_0603_5% 2 P PAD 15 1 2 3 PC335 0.1U_0603_25V7K 1 25 ENTRIP2 4 PU330 14 PQ331 AO4466L_SO8 C +3VALWP PR337 150K_0402_1% 1 2 4.7U_0805_10V6K PC361 2 1 8 7 6 5 @ 10U_1206_25V6M 1 PC368 2 1 2 2 PC367 1U_0805_25V7 +3VLP 2 1 @ PC360 10U_1206_25V6M 1 B+ ENTRIP1 PL331 ENTRIP2 RT8205_B+ HCB2012KF-121T50_0805 PR362 13K_0402_1% 1 2 PC365 0.1U_0603_25V7K PR370 VL 2 1 1 100K_0402_1% VS_ON PR371 0.01U_0402_16V7K PR372 2 A PC370 2 1 2 1 1 2 100K_0402_1% 42.2K_0402_1% VS 3 <35> PQ361 DTC115EUA_SC70-3 A @ Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title 3VALWP/5VALWP Size Document Number Rev PWWHA LA-7202 M/B Date: Friday, February 25, 2011 Sheet 1 37 of 1.0 43 A B C D HCB2012KF-121T50_0805 PL151 12 LX_1.5V ILIM 11 VDD 10 FB 6 PGOOD VFB=0.75V 7 9 2 1 2 1 PC169 0.1U_0402_25V4K 2 1 2 PC168 0.1U_0402_25V4K +1.5VP PR157 1 2 13K_0402_1% PR156 4.7_1206_5% +5VALW 1 DL_1.5V + PC152 330U_6.3V_M 4 TPS5117_TQFN14_3P5X3P5 2 PQ152 PC162 4.7U_0805_10V6K AO4712L_SO8 PC156 680P_0603_50V7K DIS : UMA : Ipeak=16.8A Ipeak=12A Imax=12A Imax=8.4A ------------------------------------------------F=294KHz Total Capacitor 720(uma) 1050(dis)uF, 2 PR162 1 1 0.1U_0603_25V7K 2 1 2 PC165 680P_0402_50V7K PL152 1.8U_D104C-919AS-1R8N_9.5A_30% PC155 1 2 2 PGND DL @ 1 LX VCC 5 AO4466L_SO8 2 BST TP 14 1 OUT 4 2 PC161 4.7U_0603_6.3V6K DH_1.5V 3 @ PQ151 2 BST_1.5V-1 13 TON 8 1 100_0603_5% PR155 0_0603_5% DH 2 AGND 2 EN_SKIP PU150 15 1 2 PR161 1 +5VALW PC160 @ .1U_0402_16V7K 1 1 BST_1.5V @ 1 3 2 1 2 5 6 7 8 PR160 0_0402_5% 3 2 1 1 SYSON B+ 4 1 <30> 2 PC164 4.7U_0805_25V6-K 2 1 @ PR164 255K_0402_1% 1 2 PC163 4.7U_0805_25V6-K 2 1 2 5 6 7 8 1 PC166 10U_1206_25V6M 1 PC167 0.1U_0402_25V4K 1.5_B+ 1 2 2 1 10K_0402_1% 2 PR163 10K_0402_1% Ipeak=1.65A ILIM = 4A F=1MHz 0.1U_0402_10V7K 1 1 2 PC1811 1U_0603_10V6K 1 2 2 1 1 PC183 22U_0805_6.3VAM 1 2 4.7U_0805_25V6-K 2 PU1801 2 1 0.47U_0402_6.3V6K 2 @ PR1821 3K_0402_1% 2 1 2 @ PC1851 @APL5930KAI-TRG_SO8 1 FB +1.8VSP @ 2 3 4 PC1841 22U_0805_6.3V6M EN POK VOUT VOUT PC1831 0.01U_0402_25V7K 8 7 1 VCNTL VIN VIN 1 @ PR1811 0_0402_5% SUSP# 1 2 6 5 9 1 2 PC185@ @ @ PC1821 GND @ PR182 499K_0402_1% PR184 10K_0402_1% 2 1 1 0_0402_5% FB_1.8V 3 PJ1811 @ JUMP_43X39 PC182 22U_0805_6.3VAM 1 2 1 2 EN_1.8V 2 PR181 FB=0.6Volt PC186 1 11 TP <30,33,40> SUSP# 6 PC187 68P_0402_50V8J 2 1 FB EN PR186 1 2 5 PR183 20K_0402_1% 2 SVIN 3 +5VALW +1.8VSP 1 8 PC184 22U_0805_6.3VAM LX LX_1.8V 2 PVIN 2 1 9 JUMP_43X39 LX 4.7_1206_5% PVIN 680P_0603_50V7K 10 +3VALW PL182 1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2 4 1 NC 1 1 2 PG 2 NC +5VALW 7 3 2 PU180 SY8033BDBC_DFN10_3X3 @ PJ181 @ 4 4 2 @ PR1831 2.4K_0402_1% Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title +1.5VP/+1.8VSP Size Document Number Custom Date: Rev 1.0 PWWHA LA-7202 M/B Friday, February 25, 2011 D Sheet 38 of 43 5 4 3 2 1 HCB2012KF-121T50_0805 D D PL451 PR460 2 1 2 1 PC466 0.1U_0402_25V6 2 1 1 PC468 10U_1206_25V6M Ipeak=6A Imax=4.2A F=276K Toatal Capacitor 660u 6 VDD PGOOD 8 7 2 SA_PGOOD DL 11 10 PR457 1 2 14.3K_0402_1% PR456 +5VALW 1 1 4.7_1206_5% + PC452 330U_2.5V_M 2 PC462 4.7U_0805_10V6K 9 +VCCSAP 0.1U_0603_25V7K 1 LX_VCCSAP 2 ILIM FB DH_VCCSAP 12 5 6 7 8 LX VCC 13 PC456 4 DL_VCCSAP TPS5117_TQFN14_3P5X3P5 2 1 14 15 BST 1 TP OUT PL452 2.2UH_VMPI0703AR-2R2M-Z01_8A_20% 1 2 PC455 1 2 DH 2 1 2 10K_0402_1% 5 BST_VCCSAP-1 680P_0603_50V7K PR463 0_0402_5% PQ452 AO4712L_SO8 C 2 1 +3VS <30> @ PQ451 AO4466L_SO8 1 PR471 C 2 2 4 FB TON PGND 3 AGND VOUT EN_SKIP PU450 2 1 @ PC460 .1U_0402_16V7K PR461 100_0402_1% 1 2 PC461 4.7U_0805_10V6K PC467 1U_0805_25V7 0_0603_5% 2 +5VALW PR455 1 3 2 1 BST_VCCSAP 2 0_0402_5% B+ 2 4 3 2 1 1 <33,40> VCCPPWRGD 2 2 255K_0402_1% PC465 2200P_0402_50V7K 2 1 PR462 1 1 PC464 4.7U_0805_25V6-K 2 5 6 7 8 1 PC463 4.7U_0805_25V6-K VCCSAP_B+ @ PR472 10K_0402_1% VCCSA_SENSE <9> 1 1 PR464 10_0402_5% 2 1 2 PR465 680_0402_1% 1 2 1 2 C 2 B 3 @ PR470 100K_0402_1% 2 1 3 B 2 2 G S PQ453 SSM3K7002FU_SC70-3 PR468 10K_0402_1% 1 D PC470 .1U_0402_16V7K PR469 10K_0402_1% 1 2 1 2 PR467 5.1K_0402_1% 1 1 +3VS PR466 9.09K_0402_1% PR473 0_0402_5% 1 2 VCCSAP_VID1 <9> E PQ454 MMST3904-7-F_SOT323-3 B VID1 +VCCSAP 1 0.8V 0 0.9V A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title +VCCSAP Size C Date: 5 4 3 2 Document Number Rev 1.0 PWWHA LA-7202 M/B Friday, February 25, 2011 Sheet 1 39 of 43 5 4 3 2 1 @ PJ75 JUMP_43X79 2 2 1 1 +1.5V PU75 VCNTL 6 2 3 GND NC 5 VREF NC 4 7 VOUT NC 8 TP 9 D +3VALW PC264 2 PR280 1K_0402_1% 1 VIN 2 <5,9,25,33> SUSP PR282 0_0402_5% 1 2 1 1 2 PC261 4.7U_0805_6.3V6K 1 D 1U_0603_10V6K 1 +0.75VSP 2 PC263 .1U_0402_16V7K 2 1 1 2 PR281 1K_0402_1% PQ260 SSM3K7002FU_SC70-3 PC262 10U_0805_6.3V6M For shortage changed PR410 0_0402_5% 1 2 2 4 2 1 PC415 4.7U_0805_25V6-K PC414 4.7U_0805_25V6-K 2 1 PC413 4.7U_0805_25V6-K 2 1 @ 8 3 2 1 4 PC412 4.7U_0805_10V6K 9 DL_1.05VS_VCCP TPS5117_TQFN14_3P5X3P5 2 1 7 B DL 1 + PR420 0_0402_5% PGOOD 2 PQ402 FB 1 2 11K_0402_1% 1 VDD 10 VFB=0.75V PR406 4.7_1206_5% +5VALW PC406 680P_0603_50V7K LX_1.05VS_VCCP PR407 1 2 +1.05VS_VCCPP 1 1 11 1 2 12 ILIM 2 LX VCC 4 2 5 OUT 3 PL402 1UH_FDUE1040D-1R0M-P3_21.3A_20% 3 2 1 BST DH_1.05VS_VCCP PC405 0.1U_0603_25V7K 1 2 AON6788_DFN8-5 14 15 TP 1 13 TON 6 PR405 3.3_0603_1% BST_1.05VS_VCCP 1 2 DH 2 PGND PR411 100_0603_1% 1 2 EN_SKIP PU400 AGND 2 PC410 @ .1U_0402_16V7K 5 PC411 4.7U_0603_6.3V6K 1 C B+ PR510 2.2_0603_1% 1 <30,33,38> SUSP# +5VALW PQ401 PR414 255K_0402_1% 1 2 PL401 HCB4532KF-800T90_1812 1 2 1.05VS_B+ PC416 10U_1206_25V6M 2 1 C 5 CSD17308Q3_SON8-5 1 S 2 PC260 .1U_0402_16V7K D 2 G 1 <33> 0.75VR_EN# 3 G2992F1U_SO8 @ PR279 0_0402_5% 1 2 2 PC402 330U_6.3V_MB PR415 1 <33,39> VCCPPW RGD 2 +3VS 2 10K_0402_1% 1 @ PR416 10K_0402_1% PR421 10_0402_5% 2 1 VCCIO_SENSE <8> 1 PR412 4.02K_0402_1% 1 2 Ipeak=12A Imax=8.75A F=305KHz Total Capacitor 990uF 2 PR413 10K_0402_1% A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title +1.05VS_VCCP/+0.75VSP Size Document Number Custom Date: Rev 1.0 PWWHA LA-7202 M/B Friday, February 25, 2011 Sheet 1 40 of 43 PC567 10U_1206_25V6M 2 1 PC574 10U_1206_25V6M 2 1 2 1 2 1 PR575 590_0402_1% ISNG ISPG PC502 560U_6.3V_M @ PC572 470P_0402_50V7K 2 1 PR571 1_0402_5% 1 PR570 10K_0402_1% 2 2 1 PR506 4.7_1206_5% 2 1 PC506 680P_0603_50V7K PC582 4.7U_0805_25V6-K 2 1 PC581 4.7U_0805_25V6-K 2 1 PC580 4.7U_0805_25V6-K 2 1 1 PR516 2 3 2 1 680P_0603_50V7K 4.7_1206_5% 2 4 1 2 PC565 4.7U_0805_25V6-K 2 1 PC564 4.7U_0805_25V6-K 2 1 PC563 4.7U_0805_25V6-K 2 1 PQ501 CSD17308Q3_SON8-5 3 2 1 PQ505 2 +CPU_CORE PR580 ISEN2 2 PR581 1 2 10K_0402_1% 1 ISEN1 10K_0402_1% PR582 VSUM+ 2 1 3.65K_0402_1% PR583 VSUM- 2 1 2.61K_0402_1% PR509 2.2_0603_1% 2 680P_0603_50V7K 4.7_1206_5% 1 PR526 2 PC526 2 1 PQ504 3 2 1 + 2 1 + @ 2 PL504 0.36UH_PCMC104T-R36MN1R17_30A_20% 4 1 PHASE1 PC525 0.22U_0603_25V7K BOOT1 2 1 2 1 PR525 3.3_0603_1% LGATE1 4 1 PC569 100U_25V_M + PC566 100U_25V_M 4 1 PC568 100U_25V_M 1 PC585 4.7U_0805_25V6-K 2 1 2 PC584 4.7U_0805_25V6-K 2 1 UGATE1 VSUM- PC583 4.7U_0805_25V6-K 2 1 PH503 10K_0402_1%_ERTJ0EG103FA PQ503 CSD17308Q3_SON8-5 5 PC551 @PC552 @ PC552 @ PR555 330P_0402_50V7K 100_0402_1% 2 1 2 1 B CPU_B+ AON6788_DFN8-5 1000P_0402_50V7K 2 1 1 3 LGATE2 +5VALW C 4 3 2 1 PC546 @ PR554 1.47K_0402_1% 2 1 PC553 2 1 330P_0402_50V7K 2 1 1 2 @ PR576 0_0402_5% 1_0402_5% .1U_0402_16V7K PC545 2 @ PC573 0.01U_0402_16V7K PC515 0.22U_0603_25V7K BOOT2 2 1 2 1 PR515 3.3_0603_1% +5VALW 0.022U_0402_16V7K 2 1 PR556 11K_0402_1% PR557 2 1 2 1 PC544 0.22U_0402_6.3V6K 2 D PL503 0.36UH_PCMC104T-R36MN1R17_30A_20% PC549 0.22U_0603_25V7K PC550 0.22U_0402_10V6K 2 1 1 330P_0402_50V7K 470P_0402_50V7K PR551 2 1 3.24K_0603_1% <8> VCCSENSE <8> VSSSENSE 1 PC562 0.22U_0402_6.3V6K 2 + VSUM+ PC559 VSUM- 1 PC547 499_0402_1% 2 1 1 1 1 2 PC542 PR548 1U_0603_10V6K ISEN1 ISEN2 1 PR560 1.69K_0402_1% 1 PHASE2 1_0603_5% 0.22U_0402_10V6K 2 1 2 22P_0402_50V8J @ PR550 2K_0402_1% 2 1 CPU_B+ PR558 PC548 2 1 PC540 2 2 2 4 1 PR559 0_0603_5% 2 +GFX_COREP Connect to +5V can disable GFX portion, but PR575 need to be removed. PC516 2 1 PROG1 VIN VDD 22 ISUMP 21 RTN ISUMN 20 19 VSEN 18 13 PU500 1 1 PR508 2.2_0603_1% CSD17308Q3_SON8-5 BOOT1 2 PQ508 25 UGATE2 B+ PL501 HCB4532KF-800T90_1812 PH504 10K_0402_1%_ERTJ0EG103FA 1 2 1 2 1 2 PR572 7.5K_0402_1% PC570 .1U_0402_16V7K 1 2 PR573 11K_0402_1% 1 2 1 2 @ PR574 PC571 100_0402_1% .1U_0402_16V7K CPU_B+ AON6788_DFN8-5 UGATE1 +5VALW 3 2 1 LGG PHASE1 470KB_0402_5%_ERTJ0EV474J 2 AON6784_DFN8-5 PQ502 LGATE1 29 3 5 30 26 BOOT1 PR562 0_0603_5% 1 2 2 @ @ 1 PC554 2.2U_0603_10V6K 2 1 PHASEG 38 LGATEG UGATEG 39 PHG BOOTG 41 40 BOOTG NTCG 1 42 PROG2 ISNG 43 ISNG NTCG ISPG 45 46 47 44 ISPG RTNG VSENG 37 VDDP+ 27 2 Reserve for slow rate LGATE2 31 PH1 ISEN3 1000P_0402_50V7K 1 PC539 1 PR546 2 8.06K_0402_1% 2 1 PC543 PR549 150P_0402_50V8J 316K_0402_1% 2 1 2 1 @ PC555 100P_0402_50V8J 2 1 32 UG1 VW 4 33 NTC For Turbo mode , PH502 must be changed 470K (b value = 4700) PC541 10P_0402_50V8J 499K_0402_1% PHASE2 VR_HOT# 1 PR545 27.4K_0402_1% 2 UGATE2 34 28 3.83K_0402_1% 2 BOOT2 35 VSSP1 2 2 1 43P_0402_50V8J LG1 36 VDD+ PC537 PWM3 PGOOD 2 @ PR547 1 VR_ON ISEN1 12 B VDDP ISL95831CRZ-T_TQFN48_6X6 IMON 11 1 2 @ PR543 499_0402_1% UGG 2 9 1 48 GND 8 10 2 LG2 SCLK 7 <5,17,30> VGATE VSSP2 ALERT# 17 2 LGATEG BOOT2 SDA ISEN2 6 1 2 1.91K_0402_1% 1 PR567 16.5K_0402_1% PH2 16 SVID_SCLK FBG 49 5 0_0402_5% PH502 BOOTG 2 PGOODG ISEN3/ FB2 PR540 4 VR_HOT# +1.05VS_VCCPP PC558 1000P_0402_50V7K UG2 15 1 PR541 PR544 VSS_AXG_SENSE <9> IMONG FB PC561 0.033U_0603_16V7 2 1 PR542 29.4K_0402_1% 2 1 VR_ON SVID_SDA SVID_ALERT# COMPG VWG COMP 2 14 2 1 PC560 .1U_0402_16V7K 2 1 PR537 130_0402_1% 1 3 <30> 1 +1.05VS_VCCPP <8> VR_SVID_CLK +3VS 2 PC505 0.22U_0603_25V7K 1 2 1 1 PL502 0.36UH_PCMC104T-R36MN1R17_30A_20% 4 1 PHASEG PR534 2.55K_0402_1% <8> VR_SVID_ALRT# <30> 4 PR505 3.3_0603_1% <8> VR_SVID_DAT C 1 PR507 2.2_0603_1% 24 PR533 475K_0402_1% PC534 0.047U_0603_16V7K 2 1 PR539 24.9K_0402_1% 2 1 PC533 150P_0402_50V8J 1 2 VCC_AXG_SENSE <9> 23 2 PC532 330P_0402_50V7K 1 1 PR538 54.9_0402_1% 1 1 UGATEG PC556 330P_0402_50V7K 1 2 5 PR532 422_0402_1% 2 D 2 1 2 2 2 2 5 PR564 27.4K_0402_1% 2 1 3 2 1 1 3.83K_0402_1% 5 2 470KB_0402_5%_ERTJ0EV474J NTCG 1 PC557 330P_0402_50V7K 2 1 PC531 68P_0402_50V8K 2 1 1 5 1 PH501 2 PR563 @ PR531 499K_0402_1% 2 CPU_B+ PC530 1000P_0402_50V7K 2 3 1 2 1 4 PR530 8.06K_0402_1% 5 3 PR591 ISEN1 2 +CPU_CORE 2 1 10K_0402_1% VSUM+ PR590 PR592 2 1 VSUM- 1 ISEN2 2 10K_0402_1% 3.65K_0402_1% PR593 2 1 1_0402_5% A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU_CORE/GFX Size Document Number Custom Date: Rev 1.0 PWWHA LA-7202 M/B Friday, February 25, 2011 Sheet 1 41 of 43 5 4 3 2 1 PAGE MODIFICATION LIST PURPOSE ----------------------------------------------------------------------------------------------------------------------2010/12/31(PVT) P36 Charger Change PQ203,PQ208 to AO4435L Cost down 2010/12/31(PVT) P36 Charger add PQ207,PQ208,PQ209 10u EMI command 2010/12/31(PVT) P36 Charger add snubber PR206,PC206 EMI command 2010/12/31(PVT) P36 Charger change boost to 2.2 ohm PR205 EMI command 2010/12/31(PVT) P35 +3VALW/+5VALW add snubber PR336,PC336,PR356,PC336 EMI command 2010/12/31(PVT) P37 +1.5VP/+1.8VSP add snubber PR156,PC156 EMI command 2010/12/31(PVT) P37 +1.5VP/+1.8VSP add PC165 for MEI EMI command 2010/12/31(PVT) P37 +VCCSA add snubber PR456,PC456 EMI command 2010/12/31(PVT) P37 +VCCSA change output capacitor PC452 to OS-con cost down 2010/12/31(PVT) P37 +VCCSA change choke PL452 to cost down D C B D molding C 2010/12/31(PVT) P38 +1.05VS/+0.75 add snubber PC406 PR406 EMI command 2010/12/31(PVT) P38 +1.05VS/+0.75 change 0.75V enable PR279 tp PR282 HW command 2010/12/31(PVT) P39 +CPU_CORE change PC549,PC515,PC525,PC 505 to correct rating design change 2010/12/31(PVT) P39 +CPU_CORE change PL502,PL503,PL504 to DCR 5% design change 2010/12/31(PVT) P39 +CPU_CORE change PC568 PC 566 to 5.8mmm capacitor design change 2010/12/31(PVT) P39 +CPU_CORE change PL551 for load line adjust design change 2010/12/31(PVT) P39 +CPU_CORE change PR560 for program temperture design change 2010/12/31(PVT) P39 +CPU_CORE change PC502,PC531,PC532 for burn-in shun down design change B A A Title Size A Date: 5 4 3 Document Number PWWHA LA-7202P M/B Friday, February 25, 2011 2 Rev 1.0 Sheet 42 of 1 43 5 4 3 2 1 HW PIR (Product Improve Record) PWWHA LA-7202P SCHEMATIC CHANGE LIST REVISION CHANGE: 1.0 GERBER-OUT DATE: 2011/02/18 NO DATE PAGE MODIFICATION LIST PURPOSE --------------------------------------------------------------------------------------------------------------------1) 01/24 05 modify FAN with BTO item PWM and RPM For HW BTO item 2) 01/24 05 modify RPM FAN connector pin define Request from thermal team 3) 02/14 30 co-lay KB9012 For BTO item 4) 02/15 24 Add C450 For ESD request D D C C B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW-PIR Size Document Number Custom Rev 1.0 PWWHA LA-7202P M/B Date: Friday, February 25, 2011 Sheet 1 43 of 43 www.s-manuals.com </pre><hr>Source Exif Data: <br /><pre>File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Format : application/pdf Creator : Title : Compal LA-7202P - Schematics. www.s-manuals.com. Subject : Compal LA-7202P - Schematics. www.s-manuals.com. Create Date : 2011:03:02 10:09:07Z Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2013:12:03 22:51:09+02:00 Metadata Date : 2013:12:03 22:51:09+02:00 Producer : GPL Ghostscript 8.15 Document ID : uuid:53ab827e-ca05-43eb-9f35-877246d7a760 Instance ID : uuid:82e52dd8-f08d-4419-b956-3fc93e42e20a Has XFA : No Page Count : 44 Keywords : Compal, LA-7202P, -, Schematics., www.s-manuals.com. </pre> <small>EXIF Metadata provided by <a href="https://exif.tools/">EXIF.tools</a></small> <div id="ezoic-pub-ad-placeholder-110"> <script async src="//pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script> <!-- usermanual link ad --> <ins class="adsbygoogle" style="display:block" data-ad-client="ca-pub-0545639743190253" data-ad-slot="6172135303" data-ad-format="link"></ins> <script> (adsbygoogle = window.adsbygoogle || []).push({}); </script> </div> </div> <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> <div class="visualClear"></div> </div> </div> <div id="mw-navigation"> <h2>Navigation menu</h2> <div id="mw-head"> <div id="p-personal" role="navigation" class="" aria-labelledby="p-personal-label"> <!-- <div id="p-search" role="search"> <form action="https://usermanual.wiki/search.php" id="searchform"> <div id="simpleSearch"> <input type="search" name="search" placeholder="Search UserManual.wiki" title="Search UserManual.wiki [ctrl-option-f]" accesskey="f" id="searchInput" tabindex="1" autocomplete="off"><input type="hidden" value="Special:Search" name="title"><input type="submit" name="go" value="Go" title="Find a User Manual" id="searchButton" class="searchButton"> </div> </form> </div>--> <ul> <li id="pt-mycontris"><a href="https://usermanual.wiki/upload" title="Upload User Manual" accesskey="y">Upload a User Manual</a></li> </ul> </div> <div id="left-navigation"> <div id="p-namespaces" role="navigation" class="vectorTabs" aria-labelledby="p-namespaces-label"> <h3 id="p-namespaces-label">Versions of this User Manual:</h3> <ul> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/compalla7202pr10schematics.1800833457" title="User Manual Wiki" accesskey="c">Wiki Guide</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/compalla7202pr10schematics.1800833457/html" title="HTML" accesskey="c">HTML</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/compalla7202pr10schematics.1800833457/amp" title="Mobile AMP" accesskey="c">Mobile</a></span></li> <li id="ca-nstab-main" class="selected" ><span><a href="https://usermanual.wiki/Document/compalla7202pr10schematics.1800833457/help" title="Discussion / FAQ / Help" accesskey="c">Download & Help</a></span></li> </ul> </div> </div> <div id="right-navigation"> <div id="p-views" role="navigation" class="vectorTabs" aria-labelledby="p-views-label"> <h3 id="p-views-label">Views</h3> <ul> <li id="ca-view"><span><a href="#">User Manual</a></span></li> <li class="selected" id="ca-edit"><span><a href="https://usermanual.wiki/Document/compalla7202pr10schematics.1800833457/help" title="Ask a question" accesskey="e">Discussion / Help</a></span></li> </ul> </div> </div> </div> <div id="mw-panel"> <div id="p-logo" role="banner"><a class="mw-wiki-logo" href="https://usermanual.wiki/Main_Page" title="Visit the main page"></a></div> <div class="portal" role="navigation" id="p-navigation" aria-labelledby="p-navigation-label"> <h3 id="p-navigation-label">Navigation</h3> </div> <div class="portal" role="navigation" id="p-tb" aria-labelledby="p-tb-label"> </div> </div> </div> <div id="footer" role="contentinfo"> <ul id="footer-info"> <li id="footer-info-lastmod">© 2024 UserManual.wiki</li> </ul> <ul id="footer-places"> <li id="footer-places-privacy"><a href="https://usermanual.wiki/ContactUs" title="UserManual.wiki:Contact Us">Contact Us</a></li> <li id="footer-places-about"><a href="https://usermanual.wiki/DMCA" title="UserManual.wiki:DMCA">DMCA</a></li> </ul> <ul id="footer-icons" class="noprint"> <li id="footer-poweredbyico"> </li> </ul> </div> </div></body></html> <script src="/cdn-cgi/scripts/7d0fa10a/cloudflare-static/rocket-loader.min.js" data-cf-settings="e308b135431f6721696b935c-|49" defer></script>