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Compal Confidential
Model Name : JM40-HR
File Name : LA-7231P
1

1

Compal Confidential

2

2

JM40-HR M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P-GS/GV-OP
3

3

2010-02-22
REV:1.0
ZZZ

Part Number

Description

DAZ0IO00100
P4LJ0_PCB
PCB P4LJ0 LA-7231P LS-7231P/7233P/7235P/7237P
ZZZ

Part Number
4

Description

DC30100DT00
DC_IN_CABLE_90W
P4LJ0_DCIN_CABLE_90W
90W@

4

ZZZ

Part Number

Description

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DC30100DS00
DC_IN_CABLE_65W
P4LJ0_DCIN_CABLE_65W
65W@

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
E

1

of

57

A

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D

E

P4LJ0 Block Diagram

Fan Control

page 38

1

1

100MHz

PEG(DIS)
VRAM * 8
DDR3

PCI-E 2.0x16 5GT/s PER LANE

Nvidia N12P-GS/GV
973pin BGA

64*16
128*16

Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel

Intel
Sandy Bridge

133MHz

Processor
DC/QC 35W
SV
rPGA989

page22~30

EDP

(reserved)
page 32

page 4~10

HDMI(Reserved Only)
FDI x8
HDMI Conn.
page 33

CRT Conn. LVDS Conn.
page 32

page 31

2

port 3

USB 3.0 controller
UPD720200AF1
+ Charger page 46

3

USB 3.0
conn x1

100MHz

2.7GT/s

1GB/s x4

port 2

LAN(GbE)

USB port 8

AR8151

WLAN

RJ45

page 38

page 36

CMOS Camera

Mini Card
(WWAN,SIM)

USB port 0,1 on USB/B
page 37

USB port 13
page 37

USB port 10

USB port 9,12 on 3G/B
page 37

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

CX20584
page 43

SPI

page 13~21

SATA HDD
Conn.

page 34

page 14

port 2

SATA CDROM
Conn.

Int. Speaker

LPC BUS

page 34

page 46

DC/DC Interface CKT.
page 45

4

HP/SPDIF
Jack on USB/B

on USB/B
page 37

page 43

page 37

page 40

Int.KBD

Touch Pad

page 40

LS-7235P/7236P
USB_Auido/B
USB Port0,1 page 37

BIOS ROM
page 39

LS-7233P
FUN/B

4

page 41

Power Circuit DC/DC
page 47~55

LS-7234P
3G
USB Port9,12 page 37

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

3

Door/B
page 41

page 40

page 40

page 43

MIC Jack

page 39

LS-7237P

Power/B

Power On/Off CKT.

DMIC

ENE KB930

Sub-board
LS-7231P
page 13

2

HDA Codec

33MHz

RTC CKT.

page 31

SPI ROM x1
port 0

Card Reader
RTS5209

Bluetooth
Conn

989pin BGA

page 35

page 37

USB 2.0 conn x2

PCH

SATA x 6
100MHz
(GEN1 1.5GT/S ,GEN2 3GT/S)

port 1

MINI Card x1

Intel
Cougar Point-M

100MHz

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

port 4

DMI x4

100MHz

LVDS(UMA/Optimus)
CRT(UMA/Optimus)
TMDS(UMA/Optimus)

HDMI(UMA/Optimus)

page 11,12

BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333

B

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
E

2

of

57

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Voltage Rails
Power Plane

1

2

D

SIGNAL

STATE
Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

+VALW

+V

+VS

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.05VSDGPU

+1.05VSDGPU power rail for GPU

ON

OFF

OFF

+1.05VS_VCCP

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

ON

OFF

OFF

+1.05VS_PCH

+1.05VS_VCCP to +1.05VS_PCH power for PCH

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

Vcc
Ra/Rc/Re

Board ID/ Project ID Table for AD channel

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

Board ID

+1.5VS to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW_EC

+3VALW always to KBC

ON

ON

ON*

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

ON

ON

ON*

+3VALW_PCH

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

0
1
2
3
4
5
6
7

+5VALW_PCH

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON

ON

ON*

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Address
0001 011X b

Board ID
0
1
2
3
4
5
6
7

EC SM Bus2 address
Address

Device

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

Device

2

BTO Item
UMA Only
N12P-GS
N12P-GV
Discrete(OPTIMUS)
VRAM
Blue Tooth
AR8151
Connector
Unpop

PCB Revision
0.1
0.2
0.3
1.0

PCH SM Bus address
3

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BTO Option Table

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Smart Battery

Clock

1

+1.5VSDGPU

Device

SLP_S1# SLP_S3# SLP_S4# SLP_S5#
HIGH

Full ON

+CPU_CORE

EC SM Bus1 address

E

BOM Structure
UMAO@
GS@
GV@
OPT@
X76@
BT@
8151@
CONN@
@
3

Address

Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)

1101 0010b

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

Project ID Table
Project ID
0
1
2
3
4
5
6
7

USB Port Table
Project Name
P3LJ0
P4LJ0
P5LJ0
P3LS0
P4LS0
P5LS0

UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2

UHCI5

4

UHCI6

Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

0
1
2
3
4
5
6
7
8
9
10
11
12
13

USB/B (Right Side)
USB/B (Right Side)

Mini Card(WLAN)
Mini Card(WWAN)
Camera
4

SIM Card
Blue Tooth

Compal Electronics, Inc.

Compal Secret Data

Security Classification

3 External
USB Port

USB 2.0 USB 1.1 Port

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
E

3

of

57

5

4

3

2

D

1

+1.05VS_VCCP

R1
24.9_0402_1%

15
15
15
15

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

15
15
15
15

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

15
15
15
15

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

15 FDI_FSYNC0
15 FDI_FSYNC1

J18
J17

FDI0_FSYNC
FDI1_FSYNC

15 FDI_INT

H20

R2
24.9_0402_1%

FDI_INT

15 FDI_LSYNC0
15 FDI_LSYNC1

J19
H17

FDI0_LSYNC
FDI1_LSYNC

A18
A17
B16

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

PCI EXPRESS* - GRAPHICS

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

EDP_COMP
31

EDP_HPD#

31
31

EDP_AUXP
EDP_AUXN

C15
D15

eDP_AUX
eDP_AUX#

31
31

EDP_TXP0
EDP_TXP1

C17
F16
C16
G15

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

31
31

EDP_TXN0
EDP_TXN1

C18
E16
D16
F15

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

eDP

2

B

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

B27
B25
A25
B24

1

+1.05VS_VCCP

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

C

15
15
15
15

DMI

D

PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

2

JCPU1A

1

PEG_COMP

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

J22
J21
H22

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K
OPT@ 0.1U_0402_10V7K

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

PEG_GTX_C_HRX_N[0..15] 22
PEG_GTX_C_HRX_P[0..15] 22
PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

C

B

SUYIN_100361HK988_SANDY BRIDGE

CONN@

Typ- suggest 220nF. The change in AC
capacitor value from 100nF to 220nF is to
enable compatibility with future platforms
having PCIE Gen3 (8GT/s)
A

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

4

of

57

5

4

3

2

1

D

D

For eDP
CLK_CPU_DPLL_R

R25

1 EDP@

2 0_0402_5%

CLK_CPU_DPLL 14

CLK_CPU_DPLL#_R

R26

1 EDP@

2 0_0402_5%

CLK_CPU_DPLL# 14

If support EDP
1. Mount R25, R26
2. Remove R30, R31

JCPU1B

H_PROCHOT#
T5

PECI

39,50 H_PROCHOT#

H_PROCHOT#_R

AL32

PROCHOT#

18 H_THRMTRIP#

R38
0_0402_5%
1
2

H_THEMTRIP#_R

AN32

THERMTRIP#

CLK_CPU_DMI
CLK_CPU_DMI#

DPLL_REF_CLK
DPLL_REF_CLK#

A16
A15

CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R

SM_DRAMRST#

R8

H_DRAMRST#

AK1
A5
A4

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

CLK_CPU_DMI 14
CLK_CPU_DMI# 14

R30
R31

1 LVDS@ 2 1K_0402_5%
1 LVDS@ 2 1K_0402_5%

+1.05VS_VCCP

H_DRAMRST# 6

R33
R35
R37

1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%

2
2
2

PU/PD for JTAG signals

4

R49
43_0402_1%
1
2 BUF_CPU_RST#

SN74LVC1G07DCKR_SC70-5

H_CPUPWRGD_R

R51
130_0402_5%
PM_SYS_PWRGD_BUF 1
2 PM_DRAM_PWRGD_R

AP33

V8

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

3

@
R52
0_0402_5%
BUF_CPU_RST#

2

PLT_RST# 17,35,38,39,44

RESET#

TCK
TMS
TRST#

AR26
AR27
AP30

XDP_TCK
XDP_TMS
XDP_TRST#

TDI
TDO

AR28
AP26

XDP_TDI_R
XDP_TDO

DBR#

AL35

DBRESET#_R

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

+3VS

R17
1K_0402_5%

2

@

1 51_0402_5%

XDP_TDI_R R40

2

@

1 51_0402_5%

XDP_TDO

R41

2

@

1 51_0402_5%

XDP_TCK

R43

2

@

1 51_0402_5%

XDP_TRST# R46

2

@

1 51_0402_5%

B

1 R50

2 0_0402_5%

XDP_DBRESET#

XDP_DBRESET# 15

+3VALW

Follow DG 0.71

SUYIN_100361HK988_SANDY BRIDGE

+1.5V_CPU_VDDQ
1
R61
200_0402_5%

U2
74AHC1G09GW_TSSOP5

1

B

2

A

O

4

A

PM_SYS_PWRGD_BUF

1

SUSP

SUSP

S

Compal Secret Data

Security Classification

D

2
G
3

46,53

5

R63
39_0402_5%
@

2
1 2

C215
1U_0402_6.3V6K
@

3

1

G

15 PM_DRAM_PWRGD

P

2

5

R62
10K_0402_5%
1
2

CONN@

1

C36
0.1U_0402_16V4Z

2

+3VS

AR33

AP29
AP27

1

AM34

PRDY#
PREQ#

+1.05VS_VCCP

R39

2

2
BUFO_CPU_RST#

H_PM_SYNC_R

JTAG & BPM

18 H_CPUPWRGD

R48
0_0402_5%
1
2

1

5
P
G

Y

15 H_PM_SYNC

R42
0_0402_5%
1
2

R44
75_0402_5%

U1

NC

A

A28
A27

XDP_TMS

1

1

C35
0.1U_0402_16V4Z

2

B

A

CATERR#

AN33

+1.05VS_VCCP

PLT_RST# 2

AL33

BCLK
BCLK#

Buffered reset to CPU

+3VS

1

R32
0_0402_5%
1
2

H_CATERR#

H_PECI_ISO

H_PECI

1 10K_0402_5% H_CPUPWRGD_R

2

@

R36
56_0402_5%
1
2

18,39
R34

PAD

THERMAL

1 62_0402_5%

2

SKTOCC#

PWR MANAGEMENT

R28

Processor Pullups

DDR3
MISC

AN34

+1.05VS_VCCP

PROC_SELECT#

CLOCKS

C

C26

17 H_SNB_IVB#

MISC

C

Issued Date

Q2
2N7002E_SOT23-3
@

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

5

of

57

5

4

3

2

JCPU1C

JCPU1D

C

11 DDR_A_BS0
11 DDR_A_BS1
11 DDR_A_BS2

B

11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_WE#

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AE10
AF10
V6

SA_BS[0]
SA_BS[1]
SA_BS[2]

AE8
AD9
AF9

SA_CAS#
SA_RAS#
SA_WE#

SUYIN_100361HK988_SANDY BRIDGE

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

AB6
AA6
V9

M_CLK_DDR0 11
M_CLK_DDR#0 11
DDR_CKE0_DIMMA 11

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

M_CLK_DDR1 11
M_CLK_DDR#1 11
DDR_CKE1_DIMMA 11

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

AB4
AA4
W9

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

AB3
AA3
W10

SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

AK3
AL3
AG1
AH1

DDR_CS0_DIMMA# 11
DDR_CS1_DIMMA# 11

SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]

AH3
AG3
AG2
AH2

M_ODT0 11
M_ODT1 11

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

12 DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

11

11

11

12 DDR_B_BS0
12 DDR_B_BS1
12 DDR_B_BS2

12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_WE#

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9
AA7
R6

SB_BS[0]
SB_BS[1]
SB_BS[2]

AA10
AB8
AB9

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

D

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

DDR SYSTEM MEMORY A

11 DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

1

SUYIN_100361HK988_SANDY BRIDGE

CONN@

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

AE2
AD2
R9

M_CLK_DDR2 12
M_CLK_DDR#2 12
DDR_CKE2_DIMMB 12

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

M_CLK_DDR3 12
M_CLK_DDR#3 12
DDR_CKE3_DIMMB 12

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

AB2
AA2
T9

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

AA1
AB1
T10

SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

AD3
AE3
AD6
AE6

DDR_CS2_DIMMB# 12
DDR_CS3_DIMMB# 12

SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

AE4
AD4
AD5
AE5

M_ODT2 12
M_ODT3 12

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

D

12

C

12

12

B

CONN@

R65
1K_0402_5%
R66
1K_0402_5%
2

2

@ R64
0_0402_5%
1
2

1

+1.5V

D

S

H_DRAMRST#

DDR3_DRAMRST#_R
1
Q3
BSS138_NL_SOT23-3

3
2

5 H_DRAMRST#

DDR3_DRAMRST# 11,12

1

2

G

R67
4.99K_0402_1%

1

A

A

DRAMRST_CNTRL_PCH

Compal Secret Data

Security Classification

C37
0.047U_0402_16V7K

Issued Date

2010/09/28

2011/09/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

2

1

11,12,14 DRAMRST_CNTRL_PCH

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

6

of

57

5

4

3

2

1

CFG Straps for Processor

1

CFG2

2

R69
1K_0402_1%
D

JCPU1E

change
change
change
change

to
to
to
to

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

T6
T7
T8
T9

PAD
PAD
PAD
PAD

@
@
@
@

AJ31
AH31
AJ33
AH33

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

AJ26

RSVD5

B4
D1

RSVD6
RSVD7

RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
1
R72
1K_0402_1%
2

R71
1K_0402_1%
2

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC

1

11 SA_DIMM_VREFDQ
12 SB_DIMM_VREFDQ

1

+3VS

1 2

B

R75
10K_0402_5%
@
VCCIO_SEL
VCCIO_SEL

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

J20
B18
A19

RSVD24
RSVD25
VCCIO_SEL

J15

RSVD27

0:Lane Reversed

2

1

CFG4

RSVD37
RSVD38
RSVD39
RSVD40

T8
J16
H16
G16

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AR35
AT34
AT33
AP35
AR34

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

B34
A33
A34
B35
C35

RSVD51
RSVD52

AJ32
AK32

VCC_DIE_SENSE

AH27

RSVD54
RSVD55

AN35
AM35

R70
1K_0402_1%
EDP@

Display Port Presence Strap
C

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

*

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6
CFG5
R73
1K_0402_1%
@

R74
1K_0402_1%
@

PAD

T10

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]
RSVD56
RSVD57
RSVD58

*10: x8, x8 - Device 1 function 1 enabled ; function 2

B

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AT2
AT1
AR1

2

R76
10K_0402_5%
@

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

*

definition matches

1

AJ31
AH31
AJ33
AH33

RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

1: Normal Operation; Lane #
socket pin map definition

CFG2

1

C

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

2

CFG4
CFG5
CFG6
CFG7

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

L7
AG7
AE7
AK2
W8

2

CFG2

PEG Static Lane Reversal - CFG2 is for the 16x

RESERVED

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

D

KEY

B1

CFG7

*

VCCIO_SEL

R77
1K_0402_1%
@

1/NC : (Default) +1.05VS_VTT
SUYIN_100361HK988_SANDY BRIDGE

0: +1.0VS_VTT

2

A19

1

VCCIO_SEL

CONN@

For 2012 CPU support

RSVD26 had changed the name to VCCIO_SEL
Need PH +3VS 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

A

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

7

of

57

4

3

JCPU1F

SV type CPU

PEG AND DDR

1
2

1
2

1
2

1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1

1
2

2

1
2

1
2

1

1

+1.05VS_VCCP

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R79
75_0402_5%
2

2

SVID

R80
43_0402_1%
1
2
1
2 0_0402_5%
1
2 0_0402_5%

R81
R82

VR_SVID_ALRT# 54
VR_SVID_CLK 54
VR_SVID_DAT 54

B

Place the PU
resistors
close to CPU

1

+CPU_CORE

AJ35 VCCSENSE_R
AJ34 VSSSENSE_R

R84
R85

1
1

2
2

0_0402_5%
0_0402_5%

VCCSENSE 54
VSSSENSE 54
1

VCC_SENSE
VSS_SENSE

2

R83
100_0402_1%

VCCIO_SENSE
VSSIO_SENSE

B10
A10

R86
100_0402_1%

VCCIO_SENSE 53
VSSIO_SENSE 53

VSSIO_SENSE

2

1
2
1
2

1
2
1
2

1
2
1
2

1
2

1
2

C

Place the PU
resistors
close to VR

SENSE LINES

2

2
1
2
1
2

1
2
1
2
1
2

1
2

1
2

CORE SUPPLY

2
1

2
1

2
1
2

1

1

1

1
2
1

2
1
2

2
1
2
1
2

1
2
1
2

1
2
1
2

C53
22U_0805_6.3V6M

C52
22U_0805_6.3V6M

C51
22U_0805_6.3V6M

C63
330U_D2_2V_Y

+

C50
22U_0805_6.3V6M

C49
22U_0805_6.3V6M

3

C62
330U_D2_2V_Y

AJ29
AJ30
AJ28

C48
22U_0805_6.3V6M

VIDALERT#
VIDSCLK
VIDSOUT

+

D

Cap quantity follow 43890_HR_CHKLST_Rev07

A

CONN@

Compal Secret Data
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

@

R78
130_0402_5%

SUYIN_100361HK988_SANDY BRIDGE

5

C61
22U_0805_6.3V6M

J23

@

C47
22U_0805_6.3V6M

VCCIO40

C60
22U_0805_6.3V6M

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

C46
22U_0805_6.3V6M

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

+1.05VS_VCCP

+1.05VS_VCCP

Security Classification
Issued Date

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

C59
22U_0805_6.3V6M

C80
22U_0805_6.3V6M

C79
22U_0805_6.3V6M

A

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

C45
22U_0805_6.3V6M

C72
22U_0805_6.3V6M

C71
22U_0805_6.3V6M

B

+

C85
330U_D2_2V_Y

+

C84
330U_D2_2V_Y

+

C83
330U_D2_2V_Y

+

C82
330U_D2_2V_Y

C81
330U_D2_2V_Y

+

C78
22U_0805_6.3V6M

C77
22U_0805_6.3V6M

C76
22U_0805_6.3V6M

C75
22U_0805_6.3V6M

C74
22U_0805_6.3V6M

C73
22U_0805_6.3V6M

+CPU_CORE

C70
22U_0805_6.3V6M

C69
22U_0805_6.3V6M

C68
22U_0805_6.3V6M

C67
22U_0805_6.3V6M

C66
22U_0805_6.3V6M

C65
22U_0805_6.3V6M

C

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

C58
22U_0805_6.3V6M

C57
10U_0805_6.3V6M

C56
10U_0805_6.3V6M

C55
10U_0805_6.3V6M

C39
10U_0805_6.3V6M

C54
10U_0805_6.3V6M

+CPU_CORE

+1.05VS_VCCP

8.5A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

C44
22U_0805_6.3V6M

C43
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

C42
10U_0805_6.3V6M

C41
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

1

QC 94A
DC 53A

D

1

POWER

1

+CPU_CORE

2

2

5

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

8

of

57

5

4

3

2

1

D

D

1
2
1

1

SENSE
LINES

2

2

VREF

+1.5VS
@ JP2

10A

2

1

PAD-OPEN 4x4m
+

C114
330U_D2_2V_Y

2

1
2

1
2

1
2

1
2

1
2

2

1

1

B

+VCCSA

6A

VCCSA_SENSE

FC_C22
VCCSA_VID1

H23

R96

2 0_0402_5%

1

VCCSA_SENSE

1

@

+

C119
330U_D2_2V_Y

2

1
2

1
2

2

1

1

+VCCSA

M27
M26
L26
J26
J25
J24
H26
H25

2

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

R97

2 0_0402_5%

1

VSSSA_SENSE 52

VCCSA_SENSE 52

C22 H_FC_C22
C24

VCCSA_VID1 52
R99
10K_0402_5%

R100
0_0402_5%
@

A

2

1

SUYIN_100361HK988_SANDY BRIDGE
CONN@

1

2

DDR3 -1.5V RAILS
MISC

1
2

1
2

1
2

1
2

VCCPLL1
VCCPLL2
VCCPLL3

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

C118
10U_0603_6.3V6M

SA RAIL

GRAPHICS

1
2
1
2
1
2

1
2
1
2
1
2

1
2
1
2
1
2

1
2
1
2

1

2

1
2
1
2

1
2
1
2
1

R95
1K_0402_5%

C113
10U_0805_6.3V6M

2

C101
0.1U_0402_16V4Z

C112
10U_0805_6.3V6M

1

+V_SM_VREF

AL1

C117
10U_0805_6.3V6M

C123
1U_0402_6.3V6K

C122
1U_0402_6.3V6K

A

C121
10U_0805_6.3V6M

C120
330U_D2_2V_Y

+

B6
A6
A2

SM_VREF

C

R94
1K_0402_5%

C116
10U_0805_6.3V6M

+1.8VS_VCCPLL

+V_SM_VREF should
have 20 mil trace width

+1.5V_CPU_VDDQ

1.5A

R98
0_0805_5%
1
2

+1.5V_CPU_VDDQ

C115
10U_0805_6.3V6M

+1.8VS

VCC_AXG_SENSE 54
VSS_AXG_SENSE 54

C111
10U_0805_6.3V6M

Θ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
Θ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

AK35
AK34

C110
10U_0805_6.3V6M

Vaxg
B

VAXG_SENSE
VSSAXG_SENSE

C109
10U_0805_6.3V6M

@

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

C108
10U_0805_6.3V6M

C107
22U_0805_6.3V6M

2

C100
22U_0805_6.3V6M

C106
22U_0805_6.3V6M
@

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

C92
22U_0805_6.3V6M

C99
22U_0805_6.3V6M

C105
22U_0805_6.3V6M
@

C91
22U_0805_6.3V6M

C94
22U_0805_6.3V6M

@

C96
22U_0805_6.3V6M

C104
22U_0805_6.3V6M

+

C98
22U_0805_6.3V6M

C97
22U_0805_6.3V6M

C103
330U_D2_2V_Y
@

C90
22U_0805_6.3V6M

C89
22U_0805_6.3V6M

C93
22U_0805_6.3V6M

C102
330U_D2_2V_Y

+

C95
22U_0805_6.3V6M

C

POWER

JCPU1G

1.8V RAIL

QC 33A
DC 26A

+VGFX_CORE

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

9

of

57

5

4

3

2

JCPU1H
D

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

C

B

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

1

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

D

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

C

B

SUYIN_100361HK988_SANDY BRIDGE

SUYIN_100361HK988_SANDY BRIDGE

CONN@

CONN@

A

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

10

of

57

5

4

3

2

1

1

+1.5V

R101
1K_0402_1%

+1.5V

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

+3VS

2
1

1

1
2

2

R115
10K_0402_5%

R114
10K_0402_5%

DIMM_A Reverse H:8mm

C145
2.2U_0603_6.3V6K

1

+0.75VS
C144
0.1U_0402_16V4Z



2

A

205

G1

4

1
2

1
2

1

1
2

1
2

1
2

1
2

1
2

1
2

1
2

Layout Note:
Place near JDIMM1.203,204

+VREF_CA

1
2

DDR_A_DQS#5
DDR_A_DQS5

1

DDR_A_D44
DDR_A_D45

B

2

DDR_A_D38
DDR_A_D39

+0.75VS
R105
1K_0402_1%

1

DDR_A_D36
DDR_A_D37

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

For EMI

DDR_A_D60
DDR_A_D61

+1.5V

DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK

C207

C212

C214

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

D_CK_SDATA 12,14
D_CK_SCLK 12,14

A

+0.75VS

FOX_AS0A621-J8RG-7H
CONN@

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2

1
2
1
2

G2

206

R104
1K_0402_1%

6

1

DDR_A_D50
DDR_A_D51

M_ODT1

2

DDR_A_DQS#6
DDR_A_DQS6

C

C143
1U_0402_6.3V6K

DDR_A_D48
DDR_A_D49

DDR_CS0_DIMMA# 6
M_ODT0 6

M_ODT1

C142
1U_0402_6.3V6K

DDR_A_D42
DDR_A_D43

DDR_CS0_DIMMA#
M_ODT0

C141
1U_0402_6.3V6K

DDR_A_D40
DDR_A_D41

+

+1.5V

C140
1U_0402_6.3V6K

DDR_A_D34
DDR_A_D35

DDR_A_BS1 6
DDR_A_RAS# 6

2

B

M_CLK_DDR1 6
M_CLK_DDR#1 6

DDR_A_BS1
DDR_A_RAS#

C139
0.1U_0402_16V4Z

DDR_A_DQS#4
DDR_A_DQS4

M_CLK_DDR1
M_CLK_DDR#1

C138
2.2U_0603_6.3V6K

DDR_A_D32
DDR_A_D33

@

DDR_A_MA2
DDR_A_MA0

1

6 DDR_CS1_DIMMA#

DDR_A_MA6
DDR_A_MA4

2

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_MA11
DDR_A_MA7

1

DDR_A_WE#
DDR_A_CAS#

DDR_CKE1_DIMMA 6

DDR_A_MA15
DDR_A_MA14

2

6 DDR_A_WE#
6 DDR_A_CAS#

DDR_CKE1_DIMMA

C137
330U_D2_2V_Y

6 DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

+1.5V

C136
10U_0603_6.3V6M

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D30
DDR_A_D31

C135
10U_0603_6.3V6M

6 M_CLK_DDR0
6 M_CLK_DDR#0

DDR_A_DQS#3
DDR_A_DQS3

C134
10U_0603_6.3V6M

DDR_A_MA3
DDR_A_MA1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D28
DDR_A_D29

C133
10U_0603_6.3V6M

DDR_A_MA8
DDR_A_MA5

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A_D22
DDR_A_D23

C132
10U_0603_6.3V6M

DDR_A_MA12
DDR_A_MA9

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

+1.5V

C131
10U_0603_6.3V6M

6 DDR_A_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

Layout Note:
Place near JDIMM1

DDR_A_D20
DDR_A_D21

C130
10U_0603_6.3V6M

DDR_A_BS2

6

C129
1U_0402_6.3V6K

DDR_CKE0_DIMMA

6 DDR_CKE0_DIMMA

C

6

DDR3_DRAMRST# 6,12

DDR_A_D14
DDR_A_D15

C128
1U_0402_6.3V6K

DDR_A_D26
DDR_A_D27

DDR3_DRAMRST#

C127
1U_0402_6.3V6K

DDR_A_D24
DDR_A_D25

DDR_A_D[0..63]
DDR_A_MA[0..15]

D

C126
1U_0402_6.3V6K

DDR_A_D18
DDR_A_D19

6

DDR_A_D12
DDR_A_D13

1

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D6
DDR_A_D7

2

DDR_A_D16
DDR_A_D17

DDR_A_DQS#0
DDR_A_DQS0

6

DDR_A_DQS[0..7]

1

DDR_A_D10
DDR_A_D11

All VREF traces should
have 10 mil trace width

DDR_A_DQS#[0..7]

DDR_A_D4
DDR_A_D5

2

DDR_A_DQS#1
DDR_A_DQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

DDR_A_D8
DDR_A_D9

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDR_A_D2
DDR_A_D3

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

1

1
2

2

2

D

2

1
R103
1K_0402_1%

G

6,12,14 DRAMRST_CNTRL_PCH

C125
0.1U_0402_16V4Z

1

C124
2.2U_0603_6.3V6K

D

S

3
Q8
BSS138_NL_SOT23-3
@

+1.5V
JDIMM1

+DIMM0_VREF

1

R102
0_0402_5%
@
1
2
2

7 SA_DIMM_VREFDQ

2

M3 support

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

11

of

57

5

4

3

2

1

R117
1K_0402_1%

+1.5V

DDR_B_DQS#6
DDR_B_DQS6
+3VS

+3VS

1
2

1
2
2

C167
2.2U_0603_6.3V6K

1

DDR_B_D56
DDR_B_D57
C166
0.1U_0402_16V4Z

R129
10K_0402_5%

DDR_B_D50
DDR_B_D51

DDR_B_D58
DDR_B_D59

1

1
2

1

1
2

2

1
2

1
2

1
2

1
2

1
2

1

DDR_CS2_DIMMB# 6
M_ODT2 6

M_ODT3

M_ODT3

R119
1K_0402_1%


Layout Note:
Place near JDIMMB.203,204

6

+0.75VS

DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

R120
1K_0402_1%


1
2

DDR_B_D36
DDR_B_D37

1

+VREF_CB

2

206
208

2

GND2
BOSS2

2

GND1
BOSS1

1

205
207

DDR_CS2_DIMMB#
M_ODT2

+1.5V

B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 11,14
D_CK_SCLK 11,14

+0.75VS

1

+0.75VS

C

C163
1U_0402_6.3V6K

DDR_B_D48
DDR_B_D49

DDR_B_BS1 6
DDR_B_RAS# 6

C162
1U_0402_6.3V6K

DDR_B_D42
DDR_B_D43

M_CLK_DDR3 6
M_CLK_DDR#3 6

DDR_B_BS1
DDR_B_RAS#

C161
1U_0402_6.3V6K

DDR_B_D40
DDR_B_D41

M_CLK_DDR3
M_CLK_DDR#3

C160
1U_0402_6.3V6K

DDR_B_D34
DDR_B_D35

B

@

DDR_B_MA2
DDR_B_MA0

C165
0.1U_0402_16V4Z

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_MA6
DDR_B_MA4

C164
2.2U_0603_6.3V6K

DDR_B_D32
DDR_B_D33

DDR_B_MA11
DDR_B_MA7

1

DDR_B_MA13
DDR_CS3_DIMMB#

6 DDR_CS3_DIMMB#

DDR_CKE3_DIMMB 6

DDR_B_MA15
DDR_B_MA14

2

DDR_B_WE#
DDR_B_CAS#

DDR_CKE3_DIMMB

C158
10U_0603_6.3V6M

6 DDR_B_WE#
6 DDR_B_CAS#

Layout Note:
Place near JDIMMB

+1.5V

C157
10U_0603_6.3V6M

6 DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

DDR_B_D30
DDR_B_D31

C156
10U_0603_6.3V6M

6 M_CLK_DDR2
6 M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_DQS#3
DDR_B_DQS3

C155
10U_0603_6.3V6M

DDR_B_MA3
DDR_B_MA1

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDR_B_D28
DDR_B_D29

C154
10U_0603_6.3V6M

DDR_B_MA8
DDR_B_MA5

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_B_D22
DDR_B_D23

C153
10U_0603_6.3V6M

DDR_B_MA12
DDR_B_MA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

+1.5V

DDR_B_D20
DDR_B_D21

C152
10U_0603_6.3V6M

DDR_B_BS2

6 DDR_B_BS2

D

DDR3_DRAMRST# 6,11

DDR_B_D14
DDR_B_D15

2

DDR_CKE2_DIMMB

6 DDR_CKE2_DIMMB
C

6

C151
1U_0402_6.3V6K

DDR_B_D26
DDR_B_D27

DDR3_DRAMRST#

C150
1U_0402_6.3V6K

DDR_B_D24
DDR_B_D25

DDR_B_MA[0..15]

C149
1U_0402_6.3V6K

DDR_B_D18
DDR_B_D19

6
6

DDR_B_D12
DDR_B_D13

C148
1U_0402_6.3V6K

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D[0..63]

DDR_B_D6
DDR_B_D7

1

DDR_B_D16
DDR_B_D17

6

DDR_B_DQS[0..7]

2

DDR_B_D10
DDR_B_D11

DDR_B_DQS#[0..7]

DDR_B_DQS#0
DDR_B_DQS0

1

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D4
DDR_B_D5

2

All VREF traces should
have 10 mil trace width

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

1

DDR_B_D8
DDR_B_D9

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

2

DDR_B_D2
DDR_B_D3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

1

D

DDR_B_D0
DDR_B_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

2

2

6,11,14 DRAMRST_CNTRL_PCH

2

1

1

2

G

R118
1K_0402_1%

C147
0.1U_0402_16V4Z

1

C146
2.2U_0603_6.3V6K

D

S

3
Q9
BSS138_NL_SOT23-3
@

+1.5V
JDIMM2

+DIMM1_VREF

1

R116
0_0402_5%
@
1
2

2

7 SB_DIMM_VREFDQ

2

M3 support

1

+1.5V

A

2

R130
10K_0402_5%



5

FOX_AS0A621-U4RG-7H
CONN@

Compal Secret Data

Security Classification

DIMM_B Reverse type H:4mm
4

A

Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

12

of

57

5

4

3

2

1

PCH_RTCX1

1

C169
18P_0402_50V8J

2

D

+3VS

PCH_RTCX2

C20

RTCX2

PCH_RTCRST#

D20

RTCRST#

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

HDA_SDO

42

HDA_SDIN0

*

R143

SPKR
HDA_RST#

HDA_SDIN0

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34
HDA_SDOUT

1 1K_0402_5% HDA_SYNC

2

This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
R147
33_0402_5%
1
2 HDA_BIT_CLK
R148
33_0402_5%
HDA_SYNC_R
1
2
R151
33_0402_5%
HDA_RST#
1
2
R155
33_0402_5%
1
2 HDA_SDOUT_R

42 HDA_BITCLK_AUDIO
42 HDA_SYNC_AUDIO

42 HDA_RST_AUDIO#
42 HDA_SDOUT_AUDIO

RTC

JTAG_TCK
JTAG_TMS

K5

JTAG_TDI

PCH_JTAG_TDO

H1

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7
Y5
AD3
AD1

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

Y3
Y1
AB3
AB1

SATAICOMPO

Y11

SATAICOMPI

Y10

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

SATA3RCOMPO

AB12

SATA3COMPI

AB13

SATA3RBIAS

AH1

SERIRQ

SERIRQ

39

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

34
34
34
34

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

34
34
34
34

SPI ROM FOR ME ( 4MByte )
+3VS

HDD
PCH_SPI_WP#

R142 1

2

3.3K_0402_5%

PCH_SPI_HOLD# R144 1

2

3.3K_0402_5%
C

Please short PJP35
ODD

+3VS
C172
1

2

U4

0.1U_0402_16V4Z
PCH_SPI_WP#

8

VCC

3

W

PCH_SPI_HOLD# 7
PCH_SPI_CS# 1
R149
PCH_SPI_CLK 1
R150
PCH_SPI_SI
1
R154
R156
37.4_0402_1%
1
2

SATA_COMP

SATA3_COMP

R157
49.9_0402_1%
1
2

R165
100_0402_1%
@

PCH_SPI_CS#_R
2
0_0402_5%
PCH_SPI_CLK_R
2
0_0402_5%
PCH_SPI_SI_R
2
0_0402_5%

S

6

C

5

VSS

4

Q

2

HOLD

1

D

PCH_SPI_SO_R

W25Q32BVSSIG

+1.05VS_PCH

P/N:SA00003K800
C173
R158
22P_0402_50V8J
33_0402_5%
@
@
2
1
1
2PCH_SPI_CLK_R

+1.05VS_PCH

PCH_SPI_SI

V4

SPI_MOSI

PCH_SPI_SO

U3

SPI_MISO

RBIAS_SATA3
R162

1

2
750_0402_1%

P3

PCH_SATALED#

SATA0GP / GPIO21

V14

PCH_GPIO21

SATA1GP / GPIO19

P1

PCH_GPIO19

SATALED#

PCH_SATALED# 41

+3VS

PCH_GPIO19

2

1HDA_SDOUT

3

1

2

R152
0_0402_5%

Q65
BSS138_NL_SOT23-3
D

@

HDA_SDOUT_R

S

1

D

W=20mils
+RTCVCC

+3VS

Q10
BSS138_NL_SOT23-3
1HDA_SYNC

3

Debug Port DG 1.2 PH 4.7K +3VS

Prevent back drive issue.

+3VS

S

+CHGRTC

R145
0_0402_5%
1
2PCH_SPI_SO

PCH_SPI_SO_R

B

G

2

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

HDA_DOCK_RST# / GPIO13

H7

Prevent back drive issue.

D1

@

2

R768
0_0402_5%

A

1

2
1
R747
1M_0402_5%

3
BAS40-04_SOT23-3
C174
0.1U_0402_16V4Z

1

2

Compal Secret Data

Security Classification

2

R166
1K_0402_5%
2
1

AM10
AM8
AP11
AP10

LPC_FRAME# 39

PCH_JTAG_TDI

trace width 10mil

+RTCBATT

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

1 10K_0402_5%

R139

R674
4.7K_0402_5%
@

HDA_SYNC_R

W=20mils

AM3
AM1
AP7
AP5

1 10K_0402_5%

2

PCH_GPIO21

39
39
39
39

R161
200_0402_5%
@

R164
100_0402_1%
@

A

J3

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

1 10K_0402_5%

2

Reserve for EMI

G

2

R163
100_0402_1%
@

HDA_DOCK_EN# / GPIO33

PCH_JTAG_TDI

1
PCH_JTAG_TMS

C36

V5

2

R136

COUGARPOINT_FCBGA989~D

1

2

R160
200_0402_5%
@

1

PCH_JTAG_TDO

1

2

R159
200_0402_5%
@

HDA_SDO

PCH_JTAG_TMS

PCH_SPI_CS#

+3VALW_PCH

1

+3VALW_PCH

1

+3VALW_PCH

PCH_JTAG_TCK

PCH_SPI_CLK

2

B

2

*

HDA_SDIN3

A36

N32
R153
51_0402_5%
2
1

LPC

T10
K34

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
+3VALW_PCH

HDA_SYNC

HDA_RST#

HDA_SDO

SATA 6G

HDA_SPKR

LPC_FRAME#

E36
K36

SERIRQ

HDA_BCLK

HDA_SPKR

HDA_SDOUT

D36

LDRQ0#
LDRQ1# / GPIO23

R134

PCH_SATALED#

1

C

42

R140
1K_0402_5%
@
1
R141
0_0402_5%
2
1

L34

FWH4 / LFRAME#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

SERIRQ

2

2

N34

HDA_SYNC

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

SATA

+3VALW_PCH

HDA_BIT_CLK

C38
A38
B37
C37

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

IHDA

1
2

HDA_SPKR

2 1K_0402_5%

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

*

39

@
2

C171
1U_0603_10V6K

+3VS
@

RTCX1

JME1
0_0603_5%

1

1
2
R137 20K_0402_5%
1
2
R138 20K_0402_5%

(INTVRMEN should always be pull high.)

R135 1

A20

2

INTVRMEN
HΚIntegrated VRM enable
LΚIntegrated VRM disable

*

+RTCVCC
C170
1U_0603_10V6K

JTAG

PCH_INTVRMEN

U3A

SPI

SM_INTRUDER#

2 330K_0402_5%

1

2 1M_0402_5%

R133 1

JCMOS1
0_0603_5%
@
PCH_RTCX1

2

R132 1

1

+RTCVCC

2

4
OSC

OSC

NC

NC
2

2

3

1

18P_0402_50V8J

D

C168

32.768KHZ_12.5PF_Q13MC14610002

Y1

PCH_RTCX2

2
10M_0402_5%

1

1
R131

9/29 DG1.5

Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

13

of

57

5

4

3

2

1

+3VALW_PCH

U3B

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

BG36
BJ36
AV34
AU34

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

BF36
BE36
AY34
BB34

1
1

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

2

1 10K_0402_5%

PCH_GPIO18

R176

2

1 10K_0402_5%

PCH_GPIO20

R181

2

1 10K_0402_5%

PCH_GPIO26

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

+3VALW_PCH
2

1 10K_0402_5%

PCH_GPIO73

R180

2

1 10K_0402_5%

PCH_GPIO25

R182

2

1 10K_0402_5%

PCH_GPIO44

R183

2

1 10K_0402_5%

PCH_GPIO45

R184

2

1 10K_0402_5%

PCH_GPIO46

Y40
Y39
PCH_GPIO73
CLK_PCIE_MINI1#
CLK_PCIE_MINI1

37 CLK_PCIE_MINI1#
37 CLK_PCIE_MINI1

Mini Card

R187

37 MINI1_CLKREQ#

AB49
AB47
1 0_0402_5%

2

PCH_GPIO18

M1

CLK_PCIE_USB30#
CLK_PCIE_USB30

44 CLK_PCIE_USB30#
44 CLK_PCIE_USB30

USB3.0

J2

R190

44 USB30_CLKREQ#

AA48
AA47
1 0_0402_5%

2

PCH_SMBDATA

SML0ALERT# / GPIO60
SML0CLK

10K_0402_5%

DRAMRST_CNTRL_PCH

R167

1

2

1K_0402_5%

PCH_SMBDATA 37

PCH_SMBCLK

R168

1

2

2.2K_0402_5%

PCH_SMBDATA

R169

1

2

DRAMRST_CNTRL_PCH 6,11,12

2.2K_0402_5%

PCH_GPIO74

R170

1

2

10K_0402_5%

PCH_SML1CLK

R171

1

2

2.2K_0402_5%

PCH_SML1DATA

R172

1

2

2.2K_0402_5%

PCH_GPIO47

R174

1

2

10K_0402_5%

C8

D

G12

C13

PCH_GPIO74

SML1CLK / GPIO58

E14

PCH_SML1CLK

SML1DATA / GPIO75

M16

PCH_SML1DATA

For DDR
+3VS

CL_CLK1
CL_DATA1
CL_RST1#

M7

PCH_GPIO20

P10

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

3

AB37
AB38

C

+3VS
CLKOUT_DMI_N
CLKOUT_DMI_P

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AM12
AM13

CLK_CPU_DPLL#
CLK_CPU_DPLL

CLKIN_DMI_N
CLKIN_DMI_P

BF18
BE18

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

CLKIN_DMI2_N
CLKIN_DMI2_P

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

CLKIN_DOT_96N
CLKIN_DOT_96P

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

AK7
AK5

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

REFCLK14IN

K45

CLK_BUF_ICH_14M

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

Y47

XCLK_RCOMP

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

PCIECLKRQ1# / GPIO18

Pull up at EC side.

CLKOUT_PCIE2N
CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37
Y36

CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLK_CPU_DPLL# 5
CLK_CPU_DPLL 5

120MHz for eDP.

PCH_SML1DATA 6

A8

2 0_0402_5%

1

PCH_GPIO26

PCH_GPIO44

PCIECLKRQ3# / GPIO25

Y43
Y45

CLKOUT_PCIE4N
CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45
V46

CLKOUT_PCIE5N
CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

PEG_CLKREQ#_R

PCH_GPIO45

PCH_GPIO46

E6

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

CLK_PCI_LPBACK 17

CLKOUT_PCIE6N
CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38
V37

CLKOUT_PCIE7N
CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14
AK13

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

R196
R197

1
1

2
2

10K_0402_5%
10K_0402_5%

CLKIN_DMI2#
CLKIN_DMI2

R199
R200

1
1

2
2

10K_0402_5%
10K_0402_5%

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R201
R202

1
1

2
2

10K_0402_5%
10K_0402_5%

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

R203
R204

1
1

2
2

10K_0402_5%
10K_0402_5%

CLK_BUF_ICH_14M

R207

1

2

10K_0402_5%

XTAL25_OUT
CLKOUTFLEX0 / GPIO64

K43 CLK_FLEX0

CLKOUTFLEX1 / GPIO65

F47

CLKOUTFLEX2 / GPIO66

H47

CLKOUTFLEX3 / GPIO67

K49 DGPU_PRSNT#

@

1
R209

T12

B

2
1M_0402_5%
Y2

2

C183
27P_0402_50V8J

+3VS

1

25MHZ_20PF_7A25000012

1

C184
27P_0402_50V8J

R214
10K_0402_5%
UMAO@

2

1

DGPU_PRSNT#
R216
10K_0402_5%

GPIO67

Pull high @ VGA side

0
1

R219
33_0402_5%
@
2
1

C186
22P_0402_50V8J
@ 1
2

A

Reserve for EMI please close to UH4

PEG_CLKREQ# 22

R222
2.2K_0402_5%
@

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

2

2

OPTIMUS
UMA

CLK_PCI_LPBACK

1

2
G

R221
2.2K_0402_5%
@

for safe

R218
10K_0402_5%
OPT@

DGPU_PRSNT#

Q13
2N7002E_SOT23-3
R220
0_0402_5%
OPT@
3
1 OPT@ 2
S

D

1

1

17,25,46,55

1

VGA_ON

2
PEG_CLKREQ#_R

2

+3VALW_PCH

5

EC_SMB_CK2 22,39

XTAL25_IN

COUGARPOINT_FCBGA989~D

A

EC_SMB_CK2

4

+1.05VS_PCH

R208
90.9_0402_1%
1
2

PEG_B_CLKRQ# / GPIO56

V40
V42

3

1

AB42
AB40

FLEX CLOCKS

CLK_PEG_VGA#
CLK_PEG_VGA

EC_SMB_DA2 22,39

Q12B
DMN66D0LDW-7_SOT363-6

B

22 CLK_PEG_VGA#
22 CLK_PEG_VGA

EC_SMB_DA2

1

Q12A
DMN66D0LDW-7_SOT363-6

1

R198

38 CARD_CLKREQ#

D_CK_SCLK 11,12

2

PCH_GPIO25

CLK_PCIE_CARD#
CLK_PCIE_CARD

38 CLK_PCIE_CARD#
38 CLK_PCIE_CARD

Card Reader

2 0_0402_5%

1

D_CK_SCLK

4

Q11B
DMN66D0LDW-7_SOT363-6

PCH_GPIO47

M10

D_CK_SDATA 11,12

R179
4.7K_0402_5%
1
2 +3VS

2

R193

35 LAN_CLKREQ#

D_CK_SDATA

1

Q11A
DMN66D0LDW-7_SOT363-6

PCH_SML1CLK
CLK_PCIE_LAN#
CLK_PCIE_LAN

35 CLK_PCIE_LAN#
35 CLK_PCIE_LAN

PCIE LAN

R177
4.7K_0402_5%
1
2
+3VS

PCH_SMBDATA 6

T11

PCH_SMBCLK

CLKOUT_PCIE0N
CLKOUT_PCIE0P

CLKOUT_PCIE1N
CLKOUT_PCIE1P

2

PCH_SMBCLK 37

A12 DRAMRST_CNTRL_PCH

SML1ALERT# / PCHHOT# / GPIO74

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

LID_SW_OUT# 39

1

2

C

R178

C9

SML0DATA

PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

PCH_SMBCLK

SMBDATA

PERN3
PERP3
PETN3
PETP3

BG37
BH37
AY36
BB36

+3VS
R175

PERN2
PERP2
PETN2
PETP2

H14

R173

5

C181
C182

1
1

BE34
BF34
BB32
AY32

SMBCLK

LID_SW_OUT#

2

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

SMBALERT# / GPIO11

LID_SW_OUT#

5

1
1

C179
C180

44 PCIE_PRX_DTX_N4
44 PCIE_PRX_DTX_P4
44 PCIE_PTX_C_DRX_N4
44 PCIE_PTX_C_DRX_P4

USB3.0

C177
C178

SMBUS

38 PCIE_PRX_DTX_N3
38 PCIE_PRX_DTX_P3
38 PCIE_PTX_C_DRX_N3
38 PCIE_PTX_C_DRX_P3

Card Reader

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

E12

Link

D

1
1

PERN1
PERP1
PETN1
PETP1

Controller

37 PCIE_PRX_DTX_N2
37 PCIE_PRX_DTX_P2
37 PCIE_PTX_C_DRX_N2
37 PCIE_PTX_C_DRX_P2

Mini Card

C175
C176

BG34
BJ34
AV32
AU32

CLOCKS

PCIE LAN

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCI-E*

35 PCIE_PRX_DTX_N1
35 PCIE_PRX_DTX_P1
35 PCIE_PTX_C_DRX_N1
35 PCIE_PTX_C_DRX_P1

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

14

of

57

5

4

3

2

1

D

D

VGATE

IN1

2

IN2

OUT

3

54

GND

39 PCH_PWROK

1

VCC

5

+3VS

C

R228

2

4

BC24
BE20
BG18
BG20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

4
4
4
4

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

4
4
4
4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

4
4
4
4

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

+1.05VS_PCH

SYS_PWROK

U5
MC74VHC1G08DFT2G_SC70-5
@

1 10K_0402_5%

DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%

1
R226
1
R227

Have internal PU

SUSACK#_R

R231
0_0402_5%
@
2
1

5 XDP_DBRESET#

2 XDP_DBRESET#_R
0_0402_5%

1

R229

SUSACK#_R

SUSWARN#_R

SYS_PWROK
PCH_PWROK
R233

1

2

PCH_PWROK_R
0_0402_5%

PM_DRAM_PWRGD

5 PM_DRAM_PWRGD
39 PCH_RSMRST#

R237

PCH_RSMRST#_R
2
0_0402_5%

1

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

4
4
4
4
4
4
4
4

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

4
4
4
4
4
4
4
4

FDI_INT

AW16

FDI_INT

BJ24

DMI_ZCOMP

FDI_FSYNC0

AV12

FDI_FSYNC0

BG25

DMI_IRCOMP

FDI_FSYNC1

BC10

FDI_FSYNC1

BH21

DMI2RBIAS

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

DSWODVREN

DPWROK

E22

4mil width and place
within 500mil of the
PCH

SYS_PWROK

FDI

2 0_0402_5%

1

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

C12
K3
P12

System Power Management

R223

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

U3C
4
4
4
4

SUSACK#
SYS_RESET#
SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

+RTCVCC

FDI_INT 4

WAKE#

B9

PCH_RSMRST#_R
R230
0_0402_5%
WAKE#
1
2

CLKRUN# / GPIO32

N3

PCH_GPIO32

SUS_STAT# / GPIO61

G8

SUS_STAT#

SUSCLK / GPIO62

N14

SUSCLK

SLP_S5# / GPIO63

D10

DSWODVREN

FDI_FSYNC0

4

FDI_FSYNC1

4

FDI_LSYNC0

4

FDI_LSYNC1

4

*

R224

2

R225

2

1 330K_0402_5%

C

not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42
PCH_PCIE_WAKE# 35,37,44
+3VALW_PCH

@

T15

WAKE#

R232

1

2 10K_0402_5%

PCH_GPIO29

R234

1

2 10K_0402_5%

R750 1

2 8.2K_0402_5%

+3VS
SUSCLK 39
@

T16

@

T17

@

T18

PM_SLP_S5#

PCH_GPIO32

PM_SLP_S5# 39

R236

SLP_S4#

H4

SUSWARN#_R

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

F4

PM_SLP_S3#

PBTN_OUT#_R
2
0_0402_5%

E20

PWRBTN#

SLP_A#

G10

SLP_A#

@

T64

Can be left NC when IAMT is not
support on the platfrom

H20

ACPRESENT / GPIO31

SLP_SUS#

G16

PM_SLP_SUS#

@

T19

@

T20

not support Deep S4,S5 can NC
PCH EDS1.2 P.74

PMSYNCH

AP14

H_PM_SYNC

K14

PCH_GPIO29

RSMRST#

@

DSWODVREN - On Die DSW VR Enable
HΚEnable
LΚDisable

PM_SLP_S4#

C21

1 330K_0402_5%

1

@

2 10K_0402_5%

EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)

PM_SLP_S4# 39
PM_SLP_S3# 39

+3VS
B

R239

2

1 200_0402_5%

PM_DRAM_PWRGD

1
R238

39 PBTN_OUT#

D2
39,46,48

1

ACIN

+3VALW_PCH

2

PCH_ACIN

RB751V-40_SOD323-2
PCH_GPIO72

R240

2

1 10K_0402_5%

SUSWARN#_R

R241

2

1 200K_0402_5%

PCH_ACIN

R242

2

1 10K_0402_5%

PCH_GPIO72

R243

2

1 10K_0402_5%

RI#

R244

2

1 10K_0402_5%

PCH_RSMRST#_R

RI#

E10

BATLOW# / GPIO72

A10

RI#

SLP_LAN# / GPIO29

B

H_PM_SYNC 5

COUGARPOINT_FCBGA989~D

A

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

15

of

57

5

4

3

2

1

D

D

1

R246
100K_0402_5%
2
U3D

DPST_PWM
PCH_LCD_CLK
PCH_LCD_DATA

31 PCH_LCD_CLK
31 PCH_LCD_DATA

CTRL_CLK
CTRL_DATA
R247

2.37K_0402_1%
2
1

1

2 2.2K_0402_5%

CTRL_CLK

R250

1

2 2.2K_0402_5%

CTRL_DATA

R249

+3VS
C

R470 1

2 2.2K_0402_5%

PCH_LCD_CLK

R471 1

2 2.2K_0402_5%

PCH_LCD_DATA

PCH_TXCLKPCH_TXCLK+

31
31
31

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

31
31
31

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

1

2 2.2K_0402_5%

PCH_CRT_CLK

R252

1

2 2.2K_0402_5%

PCH_CRT_DATA

R253

1

2 150_0402_1%

PCH_CRT_B

R254

1

2 150_0402_1%

PCH_CRT_G

R255

1

2 150_0402_1%

PCH_CRT_R
32 PCH_CRT_B
32 PCH_CRT_G
32 PCH_CRT_R
32 PCH_CRT_CLK
32 PCH_CRT_DATA

L_BKLTCTL

T40
K47

L_DDC_CLK
L_DDC_DATA

T45
P39

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

LVD_VREF

AE48
AE47

LVD_VREFH
LVD_VREFL

PCH_TXCLKPCH_TXCLK+

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

+3VS
R251

P45

AF37
AF36

0_0402_5%
2
1

31
31

L_BKLTEN
L_VDD_EN

LVDS_IBG

+3VS
R248

J47
M45

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

PCH_CRT_CLK
PCH_CRT_DATA

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

M47
M49

CRT_HSYNC
CRT_VSYNC

T43
T42

DAC_IREF
CRT_IRTN

SDVO_TVCLKINN
SDVO_TVCLKINP

AP43
AP45

SDVO_STALLN
SDVO_STALLP

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD

Digital Display Interface

31

ENBKL

LVDS

ENBKL
PCH_ENVDD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA

32 PCH_CRT_HSYNC
32 PCH_CRT_VSYNC

1

CRT_IREF

SDVO_SCLK
SDVO_SDATA

AT49
AT47
AT40 PCH_DPB_HPD
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

SDVO_SCLK 33
SDVO_SDATA 33

PCH_DPB_HPD 33
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

33
33
33
33
33
33
33
33

HDMI D2
HDMI D1

C

HDMI D0
HDMI CLK

P46
P42
AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

B

SDVO_CTRLDATA strap pull high
at level shift page

P38
M39

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT

39
31

B

COUGARPOINT_FCBGA989~D

2

R256
1K_0402_0.5%

A

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

16

of

57

5

4

3

1

PCH_GPIO55
PCH_GPIO51
PCH_GPIO5
PCH_GPIO52

1
2
3
4

8.2K_0804_8P4R_5%
RP3
8
7
6
5

PCH_GPIO53
PCH_GPIO2
PCH_GPIO4
ODD_DA#

1
2
3
4

B21
M20
AY16
BG46

TP21
TP22
TP23
TP24

8.2K_0804_8P4R_5%
R185
10K_0402_5%
1 OPT@ 2

R258

1

R259 1

VGA_ON

2 8.2K_0402_5%
2 100K_0402_5%

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

DGPU_HOLD_RST#
PLT_RST#

C

Boot BIOS Strap bit1 BBS1

14,25,46,55 VGA_ON

Boot BIOS
Bit11 Bit10 Destination
GNT1#/
GPIO51

0

1

Reserved

1

0

PCI

1

1

SPI

0

0

34

ODD_DA#

T21

LPC

14 CLK_PCI_LPBACK
39 CLK_PCI_LPC

CLK_PCI_LPBACK
CLK_PCI_LPC

R263
R264

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

D47
E42
F46

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

H49
H43
J48
K42
H40

AV5
AY1

D

DF_TVS

DMI Termination Voltage

AV10
AT8

NV_RE#_WRB0
NV_RE#_WRB1

AY5
BA2

Set to Vcc when HIGH
DF_TVS
Set to Vss when LOW

DG1.2 CRB1.0 PH 2.2K series 1K

AT12
BF3

+1.8VS

C46
C44
E40

1 22_0402_5%
2 22_0402_5%
T22
@
T23
@
T24
@

2
1

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

NV_RB#

NV_WE#_CK0
NV_WE#_CK1

DGPU_HOLD_RST#
PCH_GPIO52
VGA_ON

C6

AT10
BC8

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PLT_RST#

5,35,38,39,44 PLT_RST#

NV_DQS0
NV_DQS1

NV_RCOMP

K40
K38
H38
G38

K10

AY7
AV7
AU3
BG4

NV_ALE
NV_CLE

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

@

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USBRBIAS#

C33

USBRBIAS

B33

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

A14
K20
B17
C16
L16
A16
D14
C14

USB20_N0
USB20_P0
USB20_N1
USB20_P1

USB20_N0
USB20_P0
USB20_N1
USB20_P1

37
37
37
37

USB/B (Right side)

1

RP2
8
7
6
5

PCI

D

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

DF_TVS
R261

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

2

1
1K_0402_5%

H_SNB_IVB# 5

CLOSE TO THE BRANCHING POINT

Some PCH config not support USB port 6 & 7.
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10

USB20_N8 37
USB20_P8 37
USB20_N9 37
USB20_P9 37
USB20_N10 31
USB20_P10 31

USB20_N12
USB20_P12
USB20_N13
USB20_P13

USB20_N12
USB20_P12
USB20_N13
USB20_P13

USBRBIAS

1
R262

Mini Card (WLAN)
+3VALW_PCH

Mini Card (3G)
RP4

CMOS Camera (LVDS)

37
37
37
37

USB_OC2#
USB_OC5#
USB_OC3#
USB_OC0#

Mini Card (SIM card)

4
3
2
1

5
6
7
8

10K_1206_8P4R_5%

Bluetooth

2
22.6_0402_1%

RP5
USB_OC1#
USB_OC4#
USB_OC7#
USB_OC6#

Within 500 mils

PME#
PLTRST#

C

R260
2.2K_0402_5%

USB/B (Right side)
2

8.2K_0804_8P4R_5%

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

USB

PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#

1
2
3
4

RSVD

RP1
8
7
6
5

NVRAM

U3E

+3VS

B

2

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0# 37

4
3
2
1

5
6
7
8

B

10K_1206_8P4R_5%

COUGARPOINT_FCBGA989~D
R265
0_0402_5%
@
2
1

+3VS

IN1

2

IN2

OUT

4

PLT_RST_BUF# 37
1

1

VCC

5

R268
100K_0402_5%
OPT@

R269
100K_0402_5%
2

U7
MC74VHC1G08DFT2G_SC70-5

2

U6
MC74VHC1G08DFT2G_SC70-5
OPT@

PLT_RST#

PLTRST_VGA# 22

GND

R266
100_0402_5%
1 OPT@ 2

4

3

IN2

OUT

3

2

IN1

1

1

DGPU_HOLD_RST#

GND

PLT_RST#

VCC

5

+3VS

A

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

17

of

57

5

4

3

2

1

+3VS

R279

2 UMAO@ 1 10K_0402_5%

R643

1 OPT@

OPTIMUS_EN#

2 10K_0402_5%

+3VS

GPIO38
OPTIMUS_EN#

*

D

0
1

OPTIMUS
Non-OPTIMUS

ODD_EN#

R275

1

2 10K_0402_5%

EC_KBRST#

R276

1

2 10K_0402_5%

D

GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up

HΚOn-Die PLL voltage regulator enable
LΚOn-Die PLL Voltage Regulator disable

U3F

PCH_GPIO28
1
1K_0402_5%

PCH_GPIO69

@ T26
@ T27

DGPU_HPD_INT#

H36

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

EC_SCI#

E38

TACH3 / GPIO7

TACH7 / GPIO71

A40

PCH_GPIO71

39

EC_SMI#

EC_SMI#

C10

GPIO8

44

1
+3VS

B41

EC_SCI#

+3VS
SMIB

R283
10K_0402_5%

C4

LAN_PHY_PWR_CTRL / GPIO12

SMIB

G2

GPIO15

PCH_GPIO16

U2

A20GATE

SATA4GP / GPIO16

1 10K_0402_5%

2

PCH_GPIO0

Q74B
DMN66D0LDW-7_SOT363-6
OPT@

R280

1

2 10K_0402_5%

PCH_GPIO1

R281

1

2 10K_0402_5%

DGPU_HPD_INT#

1

2 10K_0402_5%

PCH_GPIO16

R282

B

2

C185
1U_0402_6.3V6K
OPT@

37 BT_ON#

34 ODD_DETECT#
37 WWAN_OFF#

If GPIO36,37 did not
use, it can not PU and
reserved PD resistor
for MRC0.9.

PCH_GPIO22

SCLOCK / GPIO22

PCH_GPIO24

E8

GPIO24 / MEM_LED

PCH_GPIO27

E16

GPIO27

PCH_GPIO28

P8

GPIO28

BT_ON#

K1

STP_PCI# / GPIO34

K4

GPIO35

ODD_DETECT#

V8

WWAN_OFF#

M5
N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

PCH_GPIO48

V13

2 10K_0402_5%

R285

1

2 100K_0402_5% WWAN_OFF#

R286

1

2 200K_0402_5% ODD_DETECT#

R287

1

2 10K_0402_5%

PCH_GPIO39

R288

1

2 10K_0402_5%

BT_ON#

T32 @

A4

R289

1

2 10K_0402_5%

PCH_GPIO48

T34 @

R290

1

2 10K_0402_5%

WL_OFF#

CRB1.0 PH200K to +3VS

+3VALW_PCH
1

2 10K_0402_5%

PCH_GPIO12

R292

1

2 1K_0402_5%

SMIB

R293

1

2 10K_0402_5%

PCH_GPIO57

R291

R294

1

2 10K_0402_5%

PCH_GPIO24

CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.

+3VS

RCIN#

P4

GATEA20 39

AU16

PCH_PECI_R

P5

EC_KBRST#

PROCPWRGD

AY11

THRMTRIP#

AY10

INIT3_3V#

T14

NC_1

AH8

NC_2

AK11

NC_3

AH10

NC_4

AK10

NC_5

P37

SATA3GP / GPIO37

PCH_GPIO39

1

PECI

SATA2GP / GPIO36

OPTIMUS_EN#

R284

37 WL_OFF#

TACH0 / GPIO17

GPIO

D40
T5

4

5
1

PCH_GPIO22
Q74A
DMN66D0LDW-7_SOT363-6
OPT@

2

1

R270

DGPU_PWROK

@
1
2
0_0402_5% R274

H_PECI

5,39

EC_KBRST# 39
C

H_CPUPWRGD 5
PCH_THRMTRIP#_R 1
R278

H_THRMTRIP#
2
390_0402_5%

H_THRMTRIP# 5

INIT3_3V

This signal has weak internal
PU, can't pull low

Intel schematic reviwe recommand.

SDATAOUT1 / GPIO48

VSS_NCTF_15

BG2

@ T28

WL_OFF#

V3

SATA5GP / GPIO49

VSS_NCTF_16

BG48

@ T29

PCH_GPIO57

D6

GPIO57

VSS_NCTF_17

BH3

@ T30

VSS_NCTF_18

BH47

@ T31

VSS_NCTF_1

VSS_NCTF_19

BJ4

@ T33

A44

VSS_NCTF_2

VSS_NCTF_20

BJ44

@ T35

T36 @

A45

VSS_NCTF_3

VSS_NCTF_21

BJ45

@ T37

T38 @

A46

VSS_NCTF_4

VSS_NCTF_22

BJ46

@ T39

T40 @

A5

VSS_NCTF_5

VSS_NCTF_23

BJ5

@ T41

NCTF

R842
100K_0402_5%
OPT@

+3VS

2

R841
10K_0402_5%
OPT@

+3VSDGPU

6

PCH_GPIO27

1

2 10K_0402_5%

1

1

2

R277

3

C

ODD_EN# 34

R273
10K_0402_5%

PCH_GPIO12

2

Modify R03

ODD_EN#

TACH5 / GPIO69

39

33 DGPU_HPD_INT#

Debug Port DG 1.2 PH 4.7K +3VALW_PCH
Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70

C40

TACH1 / GPIO1

T42 @

A6

VSS_NCTF_6

VSS_NCTF_24

BJ6

@ T43

T44 @

B3

VSS_NCTF_7

VSS_NCTF_25

C2

@ T45

T46 @

B47

VSS_NCTF_8

VSS_NCTF_26

C48

@ T87

T47 @

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

@ T48

T49 @

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

@ T50

T51 @

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

@ T52

T53 @

BE49

VSS_NCTF_12

VSS_NCTF_30

E49

@ T88

T54 @

BF1

VSS_NCTF_13

VSS_NCTF_31

F1

@ T55

T56 @

BF49

VSS_NCTF_14

VSS_NCTF_32

F49

@ T89

B

Follow P5WE0 R02
+3VS
1

@

TACH4 / GPIO68

A42

R567
10K_0402_5%
X76@
PCH_GPIO71

2

R272 2

BMBUSY# / GPIO0

PCH_GPIO1

2

2 4.7K_0402_5%

R604
10K_0402_5%
X76@
1

@

T7

1

R485 1

PCH_GPIO0

2

+3VALW_PCH

CPU/MISC

*

COUGARPOINT_FCBGA989~D

GPIO71
PCH_GPIO71
A

VRAM 800 MHz
VRAM 900 MHz
Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

A

0
1

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

18

of

57

5

JP3
PAD-OPEN 4x4m
@
2
1

PCH Power Rail Table

AM38

60mA VCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

VCCIO[28]

+3VS

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

+VCCAFDI_VRM

AP16

+1.05VS_VCCAPLL_FDI

BG6

1
2

1
2

V5REF

5

0.001

V5REF_Sus

5

0.001

Vcc3_3

3.3

0.266

VccADAC

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.3

VccDMI

1.05

0.042

1
C197
0.1U_0402_10V7K

VccIO

1.05

2.925

VccASW

1.05

1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

VccSus3_3

3.3

0.119



2925mA

VCCVRM[3]

AT16

+VCCAFDI_VRM
+1.05VS_PCH

C

VCCDMI[1]

AT20

20mA

VCCIO[1]

AB36

VCCPNAND[1]

VCC3_3[3]

C205
0.1U_0402_10V7K

2

1

BH29

V34

0.1uH inductor, 200mA

1

VCCIO[18]

AN27

C195
0.01U_0402_16V7K

VCCVRM[2]
VCCFDIPLL

AG16

190mA VCCPNAND[2]

AG17

VCCPNAND[3]

AJ16

VCCPNAND[4]

AJ17

2

VCCIO[17]

AN26

VCC3_3[7]

2

VCCIO[16]

AN21

HVCMOS

AN17

VCC3_3[6]

C203
1U_0402_6.3V6K

VccSusHDA

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

+1.8VS

VccCLKDMI
1

1
2

1
2

1
2

1
2

C202
1U_0402_6.3V6K

C201
1U_0402_6.3V6K

C200
1U_0402_6.3V6K

C199
1U_0402_6.3V6K

C198
10U_0805_6.3V6M

1

C

VCCIO[15]

V33

0.001

C206
0.1U_0402_10V7K

1.05

0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

2

+1.05VS_PCH

AN16

C194
0.01U_0402_16V7K
+3VS

DMI

This pin can be left as no connect in
On-Die VR enabled mode (default).

VCCAPLLEXP

NAND / SPI

BJ22

VCCIO

+VCCAPLLEXP

T77 @

1

+VCCTX_LVDS

2

AN19
T57 @

+1.8VS
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1
1

AM37

VCCTX_LVDS[2]

1.05

V_PROC_IO

D

2

VCCTX_LVDS[1]

S0 Iccmax
Current
(A)

+3VS

1

AK37

2

VSSALVDS

1

AK36

Voltage

Voltage Rail

C216
10U_0805_6.3V6M
@

C196
22U_0805_6.3V6M

1mA VCCALVDS

2

1
U47
2

CRT
LVDS

VCC CORE

1
2

1
2

1
2

VSSADAC

+VCCADAC
C193
10U_0805_6.3V6M

VCCADAC

U48

C192
0.1U_0402_10V7K

2

1mA

C191
0.01U_0402_16V7K

C187
1U_0402_6.3V6K

C190
1U_0402_6.3V6K

C189
1U_0402_6.3V6K

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

1

+3VS
L1
4.7UH_LQM18FN4R7M00D_20%
2
1

1300mA
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

+1.05VS_PCH

2

2

POWER

U3G
+1.05VS_PCH

C188
10U_0805_6.3V6M

D

3

+1.05VS_PCH

1

+1.05VS_VCCP

4

2

B

C795
1U_0402_6.3V6K

VCCIO[27]
VCCDMI[2]

20mA VCCSPI

V1

+3VS

COUGARPOINT_FCBGA989~D

2

1

AU20

1

AP17

FDI

+1.05VS_PCH

C208
1U_0402_6.3V6K

B

+VCCAFDI_VRM
+1.5VS
R307

2

1

0_0603_5%

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A

A

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

19

of

57

5

4

3

2

1

Have internal VRM
R310
0_0603_5%
@
2
1

VCC3_3 = 266mA detal waiting for newest spec
+VCCACLK

VCCDMI = 42mA detal waiting for newest spec
+5VALW

+3VALW_PCH

V24

VCCSUS3_3[6]

P24

VCCIO[34]

T26

1mA V5REF_SUS

M26

+PCH_V5REF_SUS

DCPSUS[4]

AN23

+VCCA_USBSUS

VCCSUS3_3[1]

AN24

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]
VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

2

1

D

S
G

2
1
1
2

+3VALW_PCH
+5VS

1mA V5REF

P34

VCCSUS3_3[2]

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

C219
0.1U_0603_25V7K

T81

+PCH_V5REF_RUN

+3VALW_PCH

+3VS

R323
100_0402_5%

C

D4
RB751V-40_SOD323-2

1
C226
1U_0402_6.3V6K

2

+3VS
VCC3_3[1]

AA16

VCC3_3[8]

W16

VCC3_3[4]

T34

VCC3_3[2]

AJ2

VCCIO[5]

AF13

VCCIO[12]

AH13

VCCIO[13]

AH14

+PCH_V5REF_RUN

Place C228 near
Place C233 near
Place C234 near

C227
1U_0603_10V6K

AA16.W16 pin
T34 pin
AJ2 pin

+1.05VS_PCH

1

AD31

@

2

VCCASW[6]

+PCH_V5REF_SUS

1

VCCASW[5]

AA29

D3
RB751V-40_SOD323-2

2

AA27

D

+3VALW_PCH

R319
100_0402_5%
2

VCCASW[4]

+5VALW_PCH

1

VCCASW[3]

AA26

2

2

AA24

1010mA

1

VCCASW[2]

T23 pin
P24 pin

+1.05VS_PCH

2

VCCASW[1]

AA21

1

AA19

2

2

2

VCCSUS3_3[10]

+VCCRTCEXT

N16

DCPRTC

+VCCAFDI_VRM

Y49

VCCVRM[4]

C235
1U_0402_6.3V6K

2

2

1

1

DCPSUS[3]

Place C217 near
Place C218 near

C228
0.1U_0402_10V7K

2

V23

C233
0.1U_0402_10V7K

1

T24

VCCSUS3_3[9]

C234
0.1U_0402_10V7K

2

VCCSUS3_3[8]

1

2
1

1

1
2

C225
1U_0402_6.3V6K

1

VCCIO[14]

2

1

1
2

C221
22U_0805_6.3V6M

C224
1U_0402_6.3V6K

C223
1U_0402_6.3V6K

2

VCCAPLLDMI2

AL29
AL24

C232
1U_0402_6.3V6K

C231
220U_B2_2.5VM_R35

C230
1U_0402_6.3V6K

1

BH23

35,46 PCH_PWR_EN#

+3VALW_PCH

C218
0.1U_0402_10V7K

+VCCSUS1

+1.05VS_VCCA_B_DPL
C229
220U_B2_2.5VM_R35

2

T23

2

+VCCAPLL_CPY_PCH

C220
22U_0805_6.3V6M

119mA VCCSUS3_3[7]

1

2
VCC3_3[5]

+1.05VS_VCCA_A_DPL

C236
0.1U_0402_10V7K

T29

+5VALW_PCH

1

1

T38

1

+3VS_VCC_CLKF33

+1.05VS_PCH

+

VCCIO[33]

3

C213
1U_0402_6.3V6K

2

DCPSUSBYP

C

+

VCCIO[32]

T27

1

V12

+1.05VS_PCH

1
2
L6
10UH_LB2012T100MR_20%

P28

3mA

VCCDSW3_3

2

T16

+PCH_VCCDSW

@

VCCIO[31]

Q64
AO3413L_SOT23-3

C217
0.1U_0402_10V7K

T80

P26

USB

@

VCCIO[30]

PCI/GPIO/LPC

T79

N26
1

1
@

+1.05VS_PCH
VCCIO[29]

VCCACLK

R752
20K_0402_5%

T78

R751
0_0603_5%
@
2
1

C816
0.1U_0402_10V7K

2

2

AD49
C211
0.1U_0402_10V7K

+1.05VS_PCH

L5
10UH_LB2012T100MR_20%
1
2

POWER

U3J
C210
1U_0402_6.3V6K

D

C209
10U_0805_10V4Z

1

+3VS_VCC_CLKF33

Clock and Miscellaneous

L3
10UH_LB2012T100MR_20%
1
2

1

+1.05VS_PCH

R309
0_0805_5%
@
2

1

1

2

+3VS

B

BF47

VCCADPLLB

AF17
AF33
AF34
AG34

VCCIO[7]
VCCIO[8] 55mA
VCCIO[9]
VCCIO[11]

AG33

VCCIO[10]

80mA

B

AF14
AK1

+VCCSATAPLL
+VCCAFDI_VRM

VCCVRM[1]

AF11

+VCCAFDI_VRM

VCCIO[2]

AC16

VCCIO[3]

AC17

VCCIO[4]

AD17

VCCAPLLSATA

@

T82

+1.05VS_PCH

C241
1U_0402_6.3V6K

2

95mA

T17
V19

DCPSUS[1]
DCPSUS[2]

BJ8

V_PROC_IO 1mA

+1.05VS_PCH

VCCASW[22]

T21

+VCCME_22

R335

2

1 0_0603_5%

VCCASW[23]

V21

+VCCME_23

R336

2

1 0_0603_5%

VCCASW[21]

T19

+VCCME_21

R338

2

1 0_0603_5%

10mA VCCSUSHDA

P32

+VCCSUSHDA

R339

2

1 0_0603_5%

MISC

DCPSST

CPU

+1.05VM_VCCSUS

V16

1

COUGARPOINT_FCBGA989~D

C250
0.1U_0402_16V4Z

A

2

1
2

1
2

C249
0.1U_0402_10V7K

C248
0.1U_0402_10V7K

C247
1U_0402_6.3V6K

2

VCCRTC

HDA

+3VALW_PCH
A22

RTC

+RTCVCC

1

1
2

2
1

@

+V_CPU_IO
C246
0.1U_0402_10V7K

2

T83

C245
0.1U_0402_10V7K

C244
4.7U_0603_6.3V6K

1

1

+1.05VS_PCH

2

1

+VCCSST
C242
0.1U_0402_10V7K

2

1
2

1
2

80mA

+1.05VS_PCH
C240
1U_0402_6.3V6K

C238
1U_0402_6.3V6K

C237
1U_0402_6.3V6K

+1.05VS_PCH

VCCIO[6]
VCCADPLLA

1

+1.05VS_VCCA_B_DPL

+1.05VS_PCH

A

BD47

SATA

+1.05VS_VCCA_A_DPL

Compal Secret Data

Security Classification
2010/09/28

Issued Date

Deciphered Date

2011/09/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

20

of

57

5

4

3

2

1

U3I

D

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

U3H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

C

B

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

COUGARPOINT_FCBGA989~D

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

D

C

B

A

A

COUGARPOINT_FCBGA989~D

Compal Secret Data

Security Classification
2010/09/28

Issued Date

Deciphered Date

2011/09/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

21

of

57

A

B

C

D

E

U8A

AR16
AR17
AR13

14 CLK_PEG_VGA
14 CLK_PEG_VGA#

2 OPT@
R360
3

17 PLTRST_VGA#

150mA

OPT@
C290
0.1U_0402_16V4Z

OPT@

C289
0.1U_0402_16V4Z
2
1

C288
0.1U_0402_16V4Z
2
1

C287
0.1U_0402_16V4Z
2
1

C286
4700P_0402_25V7K
2
1

1

XTALIN
XTALOUT

PEX_RST_N
PEX_TERMP

AE9

PLLVDD

AF9

SP_PLLVDD

AD9

VID_PLLVDD

B1
B2

XTAL_OUTBUFFD1
XTAL_SSIN
D2

1

1

2

1

OPT@

XTALIN

Y3
27MHZ_16PF_X5H027000FG1H
OPT@

2

OPT@

C298
22P_0402_50V8J
OPT@

XTAL_IN
XTAL_OUT

N3
L3

MIOB_HSYNC_NC
MIOB_VSYNC_NC

W1
W2

MIOA_DE_NC
MIOA_CTL3_NC
MIOA_VREF_NC

N2
P5
N5

MIOB_DE_NC
MIOB_CTL3_NC
MIOB_VREF_NC

Y5
W3
AF1

1 10K_0402_5%
1 10K_0402_5%

R762 0_0402_5%
2 OPT@ 1

2

R763
0_0402_5%
@
2
1

NV_PERFORMANCE_R 3

+3VSDGPU

1

GPU_VID0

GPIO6

OUT

GPU_VID1

GPIO7

OUT

GPU_VID2

GPIO8

IN

OVERT

GPIO9

IN

ALERT

GPIO12

IN

Reserve for VPS

GPIO18

IN

Reserve for VPS

4

I2CS_SCL
I2CS_SDA
I2CH_SCL
I2CH_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA

R343
R344
R345
R346
R347
R348
R349
R350

I2CA_SCL
I2CA_SDA

R351 1 OPT@
R352 1 OPT@

1
1
1
1
1
1
1
1

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

2
2
2
2
2
2
2
2

2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

2

2 2.2K_0402_5%
2 2.2K_0402_5%

External Spread Spectrum

OSC_OUT

R356 1

@

MIOB_CLKIN_NC
MIOB_CLKOUT_NC

2 10K_0402_5%

OSC_OUT

XTAL_OUTBUFF

22_0402_5%

2

U9

R362 1 OPT@

E2
E1

I2CS_SCL
I2CS_SDA

I2CC_SCL
I2CC_SDA

E3
E4

I2CC_SCL
I2CC_SDA

I2CB_SCL
I2CB_SDA

G3
G2

I2CB_SCL
I2CB_SDA

I2CA_SCL
I2CA_SDA

G1
G4

I2CA_SCL
I2CA_SDA

I2CH_SCL
I2CH_SDA

F6
G6

I2CH_SCL
I2CH_SDA

DACA_RED
DACA_GREEN
DACA_BLUE

AM15
AM14
AL14

DACA_HSYNC
DACA_VSYNC

AM13
AL13

DACA_VDD
DACA_VREF
DACA_RSET

AJ12
AK12
AK13

DACB_RED
DACB_GREEN
DACB_BLUE

AK4
AL4
AJ4

DACB_HSYNC
DACB_VSYNC

AM1
AM2

DACB_VDD
DACB_VREF
DACB_RSET

AG7
AK6
AH7

1

VSS

6

REFOUT

2

XOUT

MODOUT

3

XIN/CLKIN

5

R357
10K_0402_5%
OPT@

VDD

OSC_SPREAD

4

ASM3P2872AF-06OR_TSOT-23-6
@

+3VSDGPU
C283
0.1U_0402_16V4Z
@

OSC_SPREAD R361 1

@

2 22_0402_5%

XTAL_SSIN
3

R364
10K_0402_5%
OPT@

If External Spread Spectrum not stuff then stuff resistor

R367 1 OPT@ 2 10K_0402_5%
@ C814
0.1U_0402_16V4Z
1
2
@ R744 1
2 124_0402_1%

Option Component
U8

R368 2 OPT@ 1 10K_0402_5%
@ C296
0.1U_0402_16V4Z
1
2
@ R369 1
2 124_0402_1%

N12P-GV-B-A1_BGA973
GV@

4

SA00004JO10
N12P-GV-B-A1_BGA973: SA00004GY00
N12P-GV-OP-B-A1_BGA973: SA00004JO10

N12P-GS-A1_BGA973
GS@

Issued Date

Compal Secret Data
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

1

+3VSDGPU

Security Classification

A

HPD_C

OUT

Q16B
DMN66D0LDW-7_SOT363-6
OPT@
3
EC_SMB_DA2 14,39

5
I2CS_SDA

AE1
V4

AA7
AA6

IN

GPIO5

+3VSDGPU

2 10K_0402_5%

MIOBCAL_PD_VDDQ_NC
MIOBCAL_PU_GND_NC

Q16A
DMN66D0LDW-7_SOT363-6
OPT@
6
EC_SMB_CK2 14,39

2
I2CS_SCL

R359 1 OPT@

U5
T5

Q68
2N7002E_SOT23-3
OPT@
1
NV_PERFORMANCE 39

Replace GPIO 12 with GPIO 18.
When : B stage platforms

N4
R4

MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC

+3VSDGPU

R342
10K_0402_5%
2 OPT@ 1

MIOA_CLKIN_NC
MIOA_CLKOUT_NC

T4
W4

GPIO1

1

MIOA_HSYNC_NC
MIOA_VSYNC_NC

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

XTAL_OUTBUFF
XTAL_SSIN

I2CS_SCL
I2CS_SDA

1M_0402_5%

2
4

@

@
R370

C297
22P_0402_50V8J
OPT@

+GPU_PLLVDD

2

XTALOUT

AM16
AG21
1
2.49K_0402_1%

under GPU
OPT@

C285
10U_0603_6.3V6M
2
1

2

OPT@
C284
22U_0805_6.3V6M

1

+1.05VSDGPU

2 OPT@
R365

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

R340 2 OPT@
R341 2 OPT@

GPU_VID0 39,55
GPU_VID1 39,55
GPU_VID2 55
+3VSDGPU

2

L8
BLM18PG300SN1D_2P
OPT@
2
1

AJ17
AJ18
1
200_0402_1%

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
MIOB_D3_NC
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC
MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

FUNCTION

2

2
10K_0402_5%

14 PEG_CLKREQ#

GPIO

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PCI EXPRESS
DVO

PEG_GTX_HRX_P0 AL17
PEG_GTX_HRX_N0 AM17
PEG_GTX_HRX_P1 AM18
PEG_GTX_HRX_N1 AM19
PEG_GTX_HRX_P2 AL19
PEG_GTX_HRX_N2 AK19
PEG_GTX_HRX_P3 AL20
PEG_GTX_HRX_N3 AM20
PEG_GTX_HRX_P4 AM21
PEG_GTX_HRX_N4 AM22
PEG_GTX_HRX_P5 AL22
PEG_GTX_HRX_N5 AK22
PEG_GTX_HRX_P6 AL23
PEG_GTX_HRX_N6 AM23
PEG_GTX_HRX_P7 AM24
PEG_GTX_HRX_N7 AM25
PEG_GTX_HRX_P8 AL25
PEG_GTX_HRX_N8 AK25
PEG_GTX_HRX_P9 AL26
PEG_GTX_HRX_N9 AM26
PEG_GTX_HRX_P10AM27
PEG_GTX_HRX_N10AM28
PEG_GTX_HRX_P11 AL28
PEG_GTX_HRX_N11 AK28
PEG_GTX_HRX_P12 AK29
PEG_GTX_HRX_N12 AL29
PEG_GTX_HRX_P13AM29
PEG_GTX_HRX_N13AM30
PEG_GTX_HRX_P14AM31
PEG_GTX_HRX_N14AM32
PEG_GTX_HRX_P15 AN32
PEG_GTX_HRX_N15 AP32

I/O

1

1 OPT@

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

GPIO
VGA_HDMI_DET 33

1

R358

OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC
MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

R514 1 OPT11@2 100K_0402_5%

2

+3VSDGPU

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

CLK

4 PEG_GTX_C_HRX_P[0..15]

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
M7

D

4 PEG_GTX_C_HRX_N[0..15]

C251
C252
C253
C254
C255
C256
C257
C258
C259
C260
C261
C262
C263
C264
C265
C266
C267
C268
C269
C270
C271
C272
C273
C274
C275
C276
C277
C278
C279
C280
C281
C282

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

S

2

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_N15

Part 1 of 7

G

4
4
4
4
4
4
4
4
4
4
4
4

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

I2C
DACs

1

AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34

4 PEG_HTX_C_GRX_P0
4 PEG_HTX_C_GRX_N0
4 PEG_HTX_C_GRX_P1
4 PEG_HTX_C_GRX_N1
4 PEG_HTX_C_GRX_P2
4 PEG_HTX_C_GRX_N2
4 PEG_HTX_C_GRX_P3
4 PEG_HTX_C_GRX_N3
4 PEG_HTX_C_GRX_P4
4 PEG_HTX_C_GRX_N4
4 PEG_HTX_C_GRX_P5
4 PEG_HTX_C_GRX_N5
4 PEG_HTX_C_GRX_P6
4 PEG_HTX_C_GRX_N6
4 PEG_HTX_C_GRX_P7
4 PEG_HTX_C_GRX_N7
4 PEG_HTX_C_GRX_P8
4 PEG_HTX_C_GRX_N8
4 PEG_HTX_C_GRX_P9
4 PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15

C

D

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom 4019BL
Date:

Rev
B
Sheet

Friday, March 04, 2011
E

22

of

57

A

27

MDA[15..0]

27

MDA[31..16]

28
28

MDA[15..0]

MDA[47..32]
MDA[63..48]

MDA[31..16]

29

MDC[15..0]

MDA[47..32]

29

MDC[31..16]

MDA[63..48]

30

MDC[47..32]

30

MDC[63..48]

U8B

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N

P29
R29
L29
M29
AG29
AH29
AD29
AE29

FBA_CLK0
FBA_CLK0_N

T32
T31

FBA_CLK1
FBA_CLK1_N

AC31
AC30

DQSA#[7..4] 28

DQSA[3..0] 27

DQSA[7..4] 28

K27

FBCAL_PD_VDDQ

L27

FBCAL_PU_GND

M27

FBCAL_TERM_GND

CLKA0
CLKA0#
CLKA1
CLKA1#

2 OPT@ 1
40.2_0402_1%
R371
2 OPT@ 1
40.2_0402_1%
R372
2 OPT@ 1
60.4_0402_1%
R373
FBB_DEBUG0
FBB_DEBUG1

27
27
28
28

G19
G16

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

B14
B10
D9
E14
F26
D31
A31
A26

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

C14
A10
E10
D14
E26
D32
A32
B26

FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N

G14
G15
G11
G12
G27
G28
G24
G25

FBC_CLK0
FBC_CLK0_N

E17
D17

CLKC0
CLKC0#

29
29

FBC_CLK1
FBC_CLK1_N

D23
E23

CLKC1
CLKC1#

30
30

FBC_DEBUG0
FBB_DEBUG1

DQMC[3..0] 29

DQMC[7..4] 30

DQSC#[3..0] 29

DQSC#[7..4] 30

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

DQSC[3..0]

29

DQSC[7..4]

30

1

2

2
OPT@

OPT@

OPT@

1

OPT@

2010/09/28

Deciphered Date

2011/09/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

OPT@
C308
10U_0805_6.3V6M

100mA

L10
BLM18PG330SN1_2P
OPT@
1
+1.05VSDGPU

Compal Secret Data

Security Classification
Issued Date

+FB_PLLAVDD_1
1

OPT@

1

OPT@

2

1

OPT@

L11
BLM18PG330SN1_2P
OPT@
1
+1.05VSDGPU

C303
10U_0805_6.3V6M

FBA_DEBUG1
R376
FBB_DEBUG1
R377

OPT@

2

1

2
OPT@

C302
1U_0603_10V6K

1

2 OPT@

100mA

C301
0.1U_0402_16V4Z

2 OPT@

FBA_DEBUG0
R374
FBB_DEBUG0
R375

1

1

2

1

2 OPT@

1

2 OPT@

C300
0.1U_0402_16V4Z
2
1

10K_0402_5%

DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7

2

+FB_PLLAVDD_0

10K_0402_5%

A16
D10
F11
D15
D27
D34
A34
D28

29,30

N12P-GS-A1_BGA973
GS@

+1.5VSDGPU

60.4_0402_1%

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

+1.5VSDGPU

N12P-GS-A1_BGA973
GS@

60.4_0402_1%

CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30

1

FB_VREF_NC
FBA_DEBUG0
FBA_DEBUG1

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

DQSA#[3..0] 27

C299
0.1U_0402_16V4Z

J27
FBA_DEBUG0 T30
FBA_DEBUG1 T29

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20

2

FB_DLLAVDD_1
FB_PLLAVDD_1

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

DQMA[7..4] 28

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

C307
1U_0603_10V6K

J19
J18

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

DQMA[3..0] 27

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

C306
0.1U_0402_16V4Z

+FB_PLLAVDD_1

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

1

FB_DLLAVDD_0
FB_PLLAVDD_0

P32
H34
J30
P30
AF32
AL32
AL34
AF35

CMDC[30..0]
Part 3 of 7

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

2

AG27
AF27

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

MDC[63..48]

C305
0.1U_0402_16V4Z
2
1

+FB_PLLAVDD_0

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

MDC[47..32]

C304
0.1U_0402_16V4Z

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE
A

L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29

2

1

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

MDC[31..16]

U8C

CMDA[30..0] 27,28
Part 2 of 7

MDC[15..0]

MEMORY INTERFACE C

VRAM Interface

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom 4019BL
Date:

Friday, March 04, 2011

Rev
B
Sheet

23

of

57

3

2

1

MULTI LEVEL STRAPS

For GB2-128 & GB2b-128 colayout....

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

33 VGA_HDMI_TXD2+
33 VGA_HDMI_TXD233 VGA_HDMI_TXD1+
33 VGA_HDMI_TXD133 VGA_HDMI_TXD0+
33 VGA_HDMI_TXD033 VGA_HDMI_TXC+
33 VGA_HDMI_TXC-

C

1

1

+3VSDGPU

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

AL2
AL3
AJ3
AJ2
AJ1
AH1
R395
AH2
4.7K_0402_5% AH3
OPT@

@
1
2 GV@

2 10K_0402_5%
1 4.99K_0402_1%

PGOOD

R757

2 GV@

1 10K_0402_5%

33 VGA_HDMI_SCLK
33 VGA_HDMI_SDATA

B

ROM_SCLK
STRAP2
STRAP_REF2

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

AP4
AN4

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

AB5
2
10K_0402_5%
STRAP0 W5
STRAP1 W7
STRAP2
V7

1

GS@

@

Memory Size

Memory Config

strap0

strap1

strap2

strap3

strap4

N12P-GS

900 MHz

64M* 16* 8
1GB

Hynix
SA000041S40

R378
PU 45K

R385
PD 35K

R386
PD 25K

NC

NC

N12P-GS

900 MHz

64M* 16* 8
1GB

Samsung
SA00004GS10

R378
PU 45K

R385
PD 35K

R386
PD 25K

NC

NC

R388
PD 20K

R489
PD 10K

R383
PU 15K

900 MHz

128M* 16* 8
2GB

Hynix
SA00003YO20

R378
PU 45K

R385
PD 35K

R386
PD 25K

NC

R388
PD 35K

R489
PD 10K

R383
PU 15K

900 MHz

128M* 16* 8
2GB

Samsung
SA000047Q20

R378
PU 45K

R385
PD 35K

R386
PD 25K

NC

NC

R388
PD 45K

R489
PD 10K

R383
PU 15K

Frenq.

NC

ROM_SI

ROM_SO

ROM_SCLK

R388
PD 15K

R489
PD 10K

R383
PU 15K

C

Memory Size

Memory Config

strap0

strap1

strap2

strap3

strap4

ROM_SI

ROM_SO

ROM_SCLK

N12P-GV
OP-B-A1

900 MHz

64M* 16* 4
512MB

Hynix
SA000041S40

R378
PU 45K

R385
PD 35K

R386
PD 5K

R760
PD 5K

R756
PD 10K

R388
PD 15K

R382
PU 10K

R383
PU 5K

N12P-GV
OP-B-A1

900 MHz

64M* 16* 4
512MB

Samsung
SA00004GS10

R378
PU 45K

R385
PD 35K

R386
PD 5K

R760
PD 5K

R756
PD 10K

R388
PD 20K

R382
PU 10K

R383
PU 5K

GPU

D35
P7
AD20

VGAVCC_SENSE 55

Power delete the circuit of
VGAVSS_SENSE, due to the
connection isn't
differental.

AD19
E35
R7

Frenq.

AP35
AP14
AN14
AN16
AR14
AP16

R398 1

OPT@

2 10K_0402_5%
JTAG_TCK
@ T59
JTAG_TDI
JTAG_TDO
@ T60
JTAG_TMS
@ T61
JTAG_TRST
@ T62

R399 2 OPT@

@ T58
B

1

@

2

R796
10K_0402_5%

1 10K_0402_5%

SERIAL
C3
D3
C4
D4

ROM_CS#
R400 1 OPT@
ROM_SI
ROM_SO
ROM_SCLK

R401

2 OPT@

2 10K_0402_5%

1 36K_0402_1%

NC/SPDIF_NC

A5

MULTI_STRAP_REF0_GND

N9

R402 2 OPT@

1 40.2K_0402_1%

MULTI_STRAP_REF1_GND

M9

R404 2 OPT@

1 40.2K_0402_1%

THERMDP
THERMDN

B5
B4

BUFRST_N
CEC
STRAP0
STRAP1
STRAP2

X76@

TEST

GENERAL
1 OPT@
R403

GS@

For N12P-GV-OP-B-A1 strap table

ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

A4

OPT@

For N12P-GS strap table

N12P-GS-A1_BGA973
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

@

R383 2 GV@ 1 4.99K_0402_1%
R386 2 GV@ 1 4.99K_0402_1%

1 40.2K_0402_1%

N12P-GS

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

+3VSDGPU

2 GV@

--->
--->

N12P-GS

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N

AF3
AF2

R758

ROM_SI
ROM_SO
ROM_SCLK

GS@

D

Option Component

GPU

AP2
AN3

AE4
AD4

STRAP0
STRAP1
STRAP2

GV@

2
R382
10K_0402_1%

STRAP3

R759
R760

@

2
1
R489
10K_0402_1%

2 10K_0402_5%
1 10K_0402_5%

2
1
R381
15K_0402_1%

@
1
2 GV@

@

2
1
R388
20K_0402_5%

R755
R756

@

2
1
R386
24.9K_0402_1%

STRAP4

OPT@

+3VSDGPU

2
1
R380
45.3K_0402_1%

+3VSDGPU

2
1
R385
34.8K_0402_1%

A2
A7
B7
C5
C7
D5
D6
D7
E5
E7
F4
G5
H32
J25
J26
P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

2
1
R384
45.3K_0402_1%

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29

2

2

R394
4.7K_0402_5%
OPT@

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

NC

AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

LVDS/TMDS

D

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

R379
34.8K_0402_1%

Part 4 of 7
AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11

2
1
R378
45.3K_0402_1%

+3VSDGPU
U8D

R383
15K_0402_1%

4

2
1
R389
15K_0402_1%

5

+3VSDGPU

if unuse this pin , pull down 36k

N12P-GS-A1_BGA_973P
GS@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

24

of

57

5

4

3

2

1

+3VS
+3VSDGPU
1
2

C309
10U_0805_10V4Z
OPT@

R405
0_0805_5%
@
1
2
Q17
AO3413L_SOT23-3
OPT@
1

+3VALW

2
2

Q18A
DMN66D0LDW-7_SOT363-6
OPT@

23VSdelay_gate

2

C312
0.1U_0603_25V7K
OPT@

C311
0.1U_0603_25V7K
OPT@

4

1

2

5

1

Q18B
DMN66D0LDW-7_SOT363-6
OPT@

R407
470_0603_5%
OPT@

1

3

2

R408
1K_0402_5%
1 OPT@ 2

C310
10U_0805_10V4Z
OPT@

6 1

2

3VSdelay_gate

14,17,46,55 VGA_ON

D

1

G

R406
100K_0402_5%
OPT@

R409
1K_0402_5%
1 OPT@ 2

100mil(1.5A)

D

S

3

1

D

U8E

IFPC_PLLVDD
IFPC_RSET

AJ8

IFPC_IOVDD

AC6
AB6

IFPD_PLLVDD
IFPD_RSET

AK8

IFPD_IOVDD

Under GPU
@

+IFPC_IOVDD
+IFPC_IOVDD
OPT@

Unuse 10K PD

10K_0402_5%2 OPT@
1K_0402_1% 2
@

1 R417
1 R418

AJ6
AL1

IFPEF_PLLVDD
IFPEF_RSET

10K_0402_5%1 OPT@

2 R419

AE7
AD7

IFPE_IOVDD
IFPF_IOVDD

MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

P9
R9
T9
U9

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

AA9
AB9
W9
Y9

1
2

C325
0.1U_0402_16V4Z

1
2

C324
0.1U_0402_16V4Z

1
2

C323
1U_0402_6.3V6K

1
2

C322
1U_0402_6.3V6K

1

C321
4.7U_0603_6.3V6K

2

1
2

C320
10U_0603_6.3V6M

1
2

OPT@
C

Under GPU
+1.05VSDGPU

1
2

+1.05VSDGPU
@

R793
1
0_0603_5%
+3VSDGPU

2 OPT@ 1
R410
0_0603_5%

B

+3VSDGPU
OPT@

OPT@
R791
10K_0402_5%

OPT@

OPT@

+1.05VSDGPU

1
L12
BLM18PG121SN1D_0603
OPT@

Under GPU

OPT@

Under GPU

C344
1U_0402_6.3V6K

1
2

1

C332
0.1U_0402_16V4Z

1
2

C341
1U_0402_6.3V6K

1
2

1
2

C340
4.7U_0603_6.3V6K

C339
0.1U_0402_16V4Z

C331
0.1U_0402_16V4Z

1
2

C330
1U_0402_6.3V6K

1
2

C329
1U_0402_6.3V6K

1

C328
4.7U_0603_6.3V6K

2

1
2

C327
10U_0603_6.3V6M

1
2

OPT@

OPT@

2 OPT@

1

R414
0_0603_5%

Under GPU

OPT@
R792
10K_0402_5%

2

2

@

C359
10K_0402_5%

1

@
C357
4.7U_0603_6.3V6K
2
1

@

1K_0402_1% 2

570 mA

C358
0.1U_0402_16V4Z
2
1

A

L14
BLM18BB221SN1D_2P
@
2
1

C356
1U_0402_6.3V6K

2

1

+1.05VSDGPU

+IFPC_PLLVDD
1 R416

120mA

+VDD33

OPT@

C354
4.7U_0603_6.3V6K

+IFPC_IOVDD

AJ9
AK7

OPT@

2

OPT@

1

+IFPC_PLLVDD
1 R415

OPT@

2

@

J10
J11
J12
J13
J9

2

C353
1U_0402_6.3V6K

1K_0402_1% 2

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

2

IFPA_IOVDD
IFPB_IOVDD

120mA

C343
4.7U_0603_6.3V6K

AG9
AG10

+PEX_SVDD_3V3

1

1 R413

AG19
F7

2

10K_0402_5%2 OPT@

PEX_SVDD_3V3
PEX_SVDD_3V3_NC

C342
0.1U_0402_16V4Z

IFPAB_PLLVDD
IFPAB_RSET

OPT@

OPT@
OPT@

1

AK9
AJ11

120mA

2

1 R411
1 R412

OPT@

C352
0.1U_0402_16V4Z

10K_0402_5% 2 OPT@
1K_0402_1% 2
@

Unuse 10K PD

OPT@

Under GPU

1

C338
0.1U_0402_16V4Z

OPT@

+PEX_PLLVDD

2200 mA

1

@

C348
0.1U_0402_16V4Z
2
1
C349
10K_0402_5%

@
C347
0.1U_0402_16V4Z
2
1

1
2

2

1

C346
4.7U_0603_6.3V6K
2
1

+IFPC_PLLVDD

@

AG14

OPT@

2

C337
0.1U_0402_16V4Z
2
1

440 mA

C345
1U_0402_6.3V6K

@
L13
2
1
BLM18PG331SN1D_2P
@

PEX_PLLVDD

OPT@

OPT@

1

C336
0.1U_0402_16V4Z
2
1

+3VSDGPU

AK16
AK17
AK21
AK24
AK27

OPT@

OPT@
OPT@

2

C335
0.1U_0402_16V4Z
2
1

B

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

OPT@

C351
0.1U_0402_16V4Z

C334
1U_0402_6.3V6K
2
1

under GPU

OPT@
C319
22U_0805_6.3V6M

C316
0.1U_0402_16V4Z

OPT@

OPT@

1

C318
0.1U_0402_16V4Z
2
1

OPT@

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

2

C315
0.1U_0402_16V4Z
2
1

OPT@

+1.05VSDGPU

2200mA

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

C326
22U_0805_6.3V6M

C314
0.1U_0402_16V4Z
2
1

2

OPT@

1

OPT@

2

1
2

OPT@
C333
4.7U_0603_6.3V6K

under GPU

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

2

C313
1U_0402_6.3V6K
2
1

2

C

Part 5 of 7
J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

C350
0.1U_0402_16V4Z

OPT@

1

OPT@

2

OPT@

1

OPT@

1

OPT@

1

OPT@
C317
4.7U_0603_6.3V6K

7900mA

POWER

+1.5VSDGPU

N12P-GS-A1_BGA973
GS@

A

Under GPU
Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom 4019BL
Date:

Rev
B
Sheet

Friday, March 04, 2011
1

25

of

57

5

4

D

3

2

1

D

U8F

B

A

Part 6 of 7

+VGA_CORE
+VGA_CORE

Under GPU

U8G

OPT@ C364
0.01U_0402_16V7K
2
1

OPT@ C374
0.01U_0402_16V7K
2
1

OPT@ C365
0.01U_0402_16V7K
2
1

OPT@ C366
0.01U_0402_16V7K
2
1

OPT@ C367
0.01U_0402_16V7K

OPT@ C370
0.047U_0402_16V7K
2
1

OPT@ C371
0.047U_0402_16V7K
2
1

OPT@ C376
0.047U_0402_16V7K
2
1

OPT@ C372
0.1U_0402_16V4Z
2
1

OPT@ C373
0.1U_0402_16V4Z

Put Under GPU

1
2

OPT@ C386
47U_0805_4V6

1
2

OPT@ C385
22U_0805_6.3V6M

1
2

OPT@ C384
4.7U_0805_10V4Z

1
2

OPT@ C383
10U_0603_6.3V6M

1
2

+

OPT@ C382
10U_0603_6.3V6M

+

OPT@ C381
470U_V_2.5VM

1

+VGA_CORE

Change values from
330u*1 to 470u*2.

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

C

B

N12P-GS-A1_BGA973
GS@

A

N12P-GS-A1_BGA973
GS@

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Part 7 of 7

POWER

OPT@ C363
0.01U_0402_16V7K
2
1
OPT@ C375
0.022U_0402_16V7K
2
1

1
2

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

OPT@
C380
1U_0603_10V6K

2

1

OPT@ C362
0.01U_0402_16V7K
2
1
OPT@ C369
0.022U_0402_16V7K
2
1

OPT@ C379
0.22U_0603_16V7K
2
1

OPT@ C378
0.22U_0603_16V7K
2
1

1
2
2

1

OPT@ C377
0.22U_0603_16V7K
2
1

OPT@ C368
0.022U_0402_16V7K

2

1

OPT@ C361
0.01U_0402_16V7K

41.02A

2

GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

OPT@ C857
470U_V_2.5VM
2
1

C

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96

GND

B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom 4019BL
Date:

Rev
B
Sheet

Friday, March 04, 2011
1

26

of

57

5

4

3

2

1

VRAM DDR3 chips (1GB)

Mode E
Address

64Mx16 DDR3 *8==>1GB

D

DQSA[7..0]

23,28 DQSA[7..0]

U10

U11

DQSA#[7..0]

23,28 DQSA#[7..0]

+MEM_VREF0

23,28 DQMA[7..0]

MDA[63..0]

23,28 MDA[63..0]

CMDA[30..0]

23,28 CMDA[30..0]

+1.5VSDGPU

OPT@
R420
240_0402_1%

1
2

C387 OPT@
0.1U_0402_10V6K

OPT@
R421
240_0402_1%

+1.5VSDGPU

1
2

C388 OPT@
0.1U_0402_10V6K

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA14
MDA10
MDA15
MDA8
MDA12
MDA9
MDA13
MDA11

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28
DQSA0
DQSA3

F3
C7

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA0
DQMA3

E7
D3

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA29
CMDA13
CMDA27

M2
N8
M3

CLKA0
CLKA0#
CMDA3

J7
K7
K9
K1
L2
J3
K3
L3

DQSA2
DQSA1

F3
C7

DQMA2
DQMA1

E7
D3

+MEM_VREF1
OPT@
R423
240_0402_1%

MDA17
MDA18
MDA16
MDA23
MDA22
MDA20
MDA19
MDA21

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

OPT@
R422
240_0402_1%

E3
F7
F2
F8
H3
H8
G2
H7

VREFCA
VREFDQ

+MEM_VREF0
C

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

M8
H1

DQMA[7..0]

DQSA#2
DQSA#1

G3
B7

BA0
BA1
BA2

CK
CK
CKE/CKE0

CMDA20

T2

RESET

ZQ0

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSDGPU

23

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDA29
CMDA13
CMDA27

M2
N8
M3

CLKA0
CLKA0#
CMDA3

J7
K7
K9
K1
L2
J3
K3
L3

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA0
MDA7
MDA1
MDA4
MDA3
MDA6
MDA2
MDA5

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA31
MDA26
MDA30
MDA25
MDA27
MDA28
MDA29
MDA24

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2

CK
CK
CKE/CKE0

+1.5VSDGPU

ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

T2

RESET

ZQ1

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSDGPU

CLKA0#

OPT@
R426
243_0402_1%

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

CMDA3
CMDA0
CMDA16
CMDA20
CMDA19

R427
R428
R430
R431
R432

CMD8

CMD1

32..63
D

A8

A8
CS0_L#

CMD2

CMD2

CMD21
CMD24

CMD3

A7

A6

CMD4

A2

A1

CMD23
CMD26

CMD5

A11

A9

CMD6

A5

A4

CMD7

CMD7

A0

A12

CMD15
CMD13
CMD4

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

CMD18

CMD11

A11
CS0_H#
BA0

CMD29

CMD12

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

BA1

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

A4

A5

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CS1_H#
ODT_H

C

RAS*
A7
CKE_H

Not Available

1
1
1
1
1

OPT@
OPT@
OPT@
OPT@
OPT@

2
2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

B

OPT@
C408
4.7U_0603_6.3V6K

OPT@
C407
4.7U_0603_6.3V6K
2
1

C406
OPT@
4.7U_0603_6.3V6K
2
1

OPT@
C405
4.7U_0603_6.3V6K
2
1

OPT@
C404
4.7U_0603_6.3V6K
2
1

OPT@
C403
4.7U_0603_6.3V6K
2
1

OPT@
C401
4.7U_0603_6.3V6K
2
1

1
2

OPT@
C400
4.7U_0603_6.3V6K
2
1

OPT@ C399
0.1U_0402_16V4Z

OPT@ C398
0.1U_0402_16V4Z
2
1

OPT@ C397
0.1U_0402_16V4Z
2
1

OPT@ C396
0.1U_0402_16V4Z
2
1

OPT@ C395
0.1U_0402_16V4Z
2
1

OPT@ C394
0.1U_0402_16V4Z
2
1

OPT@ C393
0.1U_0402_16V4Z
2
1

OPT@ C392
0.1U_0402_16V4Z
2
1

OPT@
C402
4.7U_0603_6.3V6K
2
1

2010/09/28

10k
10k
No Termination

ZZZ

X7603@

ZZZ

X7605@

X7607@

X76287BOL01
1Gx4 SAM 64M16

X76287BOL03
1Gx8 SAM 64M16

X76287BOL05
2Gx8 SAM 128M16

X76287BOL07
2Gx4 SAM 128M16

ZZZ

ZZZ

ZZZ

ZZZ

X7604@

X7606@

X76287BOL04
1Gx8 HYN 64M16

A

X7608@

X76287BOL06
2Gx8 HYN 128M16

X76287BOL08
2Gx4 HYN 128M16

Compal Electronics, Inc.
2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

ZZZ

Compal Secret Data

Security Classification

10k

CKEx

X76
ZZZ

X76287BOL02
1Gx4 HYN 64M16

4

ODTx
DDR3

CS*

X7602@

Issued Date

Command Bit Default Pull-down

RST

+1.5VSDGPU

OPT@ C391
0.1U_0402_16V4Z
2
1

1
2

OPT@ C390
1000P_0402_50V7K
2
1

CKE_L

CMD31

X7601@

5

CMD0

CMD30

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

+1.5VSDGPU

A

0..31

CMD3

1

CMDA20

2

OPT@
R425
243_0402_1%

2

OPT@
R429
160_0402_1%

2

CLKA0
1

23

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

DQSA#0
DQSA#3

1

B

+1.5VSDGPU

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

+MEM_VREF1 M8
H1

Mode C
Address

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

27

of

57

5

4

3

2

1

VRAM DDR3 chips (1GB)

Mode E
Address

64Mx16 DDR3 *8==>1GB
D

U12
+MEM_VREF2
DQMA[7..0]
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

CMDA[30..0]

23,27 CMDA[30..0]

DQSA#[7..0]

23,27 DQSA#[7..0]

DQSA[7..0]

23,27 DQSA[7..0]

MDA[63..0]

23,27 MDA[63..0]

+1.5VSDGPU
OPT@
R434
240_0402_1%

CMDA29
CMDA6
CMDA30

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

1
2

C409 OPT@
0.1U_0402_10V6K

C

CLKA1
CLKA1#
CMDA16

J7
K7
K9

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

K1
L2
J3
K3
L3

DQSA7
DQSA4

BA0
BA1
BA2

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CMDA29
CMDA6
CMDA30

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

CLKA1
CLKA1#
CMDA16

+1.5VSDGPU

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DQSA5
DQSA6

F3
C7

DQSL
DQSU

DQMA7
DQMA4

E7
D3

DML
DMU

E7
D3

DML
DMU

G3
B7

DQSL
DQSU

DQSA#5
DQSA#6

G3
B7

DQSL
DQSU

CMDA20

T2

RESET

CMDA20

T2

RESET

ZQ2

L8

ZQ/ZQ0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA5
DQMA6

DQSA#7
DQSA#4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ZQ3

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

E3
F7
F2
F8
H3
H8
G2
H7

MDA41
MDA45
MDA43
MDA44
MDA42
MDA47
MDA40
MDA46

D7
C3
C8
C2
A7
A2
B8
A3

MDA51
MDA52
MDA48
MDA54
MDA49
MDA55
MDA50
MDA53
+1.5VSDGPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

F3
C7

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU

J1
L1
J9
L9

CLKA1

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

OPT@
R439
243_0402_1%

J1
L1
J9
L9

1

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

CKE_L

CMD8

CMD1

CMD2

CMD2

CMD21
CMD24

CMD3

A7

A6

CMD4

A2

A1

CMD23
CMD26

CMD5

A11

A9

CMD6

A5

A4

CMD7

CMD7

A0

A12

CMD15
CMD13
CMD4

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

A11

CMD18

CMD11

CMD29

CMD12

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

BA1

32..63
A8

A8

D

CS0_L#

CS0_H#
BA0

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

A4

A5

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CMD31

CS1_H#
ODT_H
C

RAS*
A7
CKE_H

Not Available

B

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

2

OPT@
R441
160_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

0..31

CMD0

CMD30

1

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

BA0
BA1
BA2

A1
A8
C1
C9
D2
E9
F1
H2
H9

2

B

M8
H1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

OPT@
R438
243_0402_1%

23

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

1

1
2

OPT@
R437
240_0402_1%

C410 OPT@
0.1U_0402_10V6K

+MEM_VREF3

D7
C3
C8
C2
A7
A2
B8
A3

MDA35
MDA38
MDA34
MDA36
MDA33
MDA37
MDA32
MDA39

+MEM_VREF3

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

+1.5VSDGPU
OPT@
R436
240_0402_1%

MDA63
MDA57
MDA62
MDA61
MDA59
MDA56
MDA60
MDA58

+1.5VSDGPU

+MEM_VREF2
OPT@
R435
240_0402_1%

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

2

23,27 DQMA[7..0]

U13

Mode C
Address

CMD3

CLKA1#

1
2

OPT@
C430
4.7U_0603_6.3V6K

1
2

OPT@
C429
4.7U_0603_6.3V6K

1
2

OPT@
C428
4.7U_0603_6.3V6K

1
2

OPT@
C427
4.7U_0603_6.3V6K

1
2

OPT@
C426
4.7U_0603_6.3V6K

1
2

C425
OPT@
4.7U_0603_6.3V6K

1
2

OPT@
C424
4.7U_0603_6.3V6K

1
2

OPT@
C423
4.7U_0603_6.3V6K

2

1

OPT@
C421
0.1U_0402_16V7K

OPT@
C420
0.1U_0402_16V7K
2
1

OPT@
C419
0.1U_0402_16V7K
2
1

OPT@
C418
0.1U_0402_16V7K
2
1

OPT@
C417
0.1U_0402_16V7K
2
1

OPT@
C416
0.1U_0402_16V7K
2
1

OPT@
C415
1U_0402_6.3V6K
2
1

OPT@
C414
1U_0402_6.3V6K
2
1

+1.5VSDGPU

OPT@
C413
1U_0402_6.3V6K
2
1

1
2

OPT@
C412
1U_0402_6.3V6K
2
1

+1.5VSDGPU

OPT@
C422
4.7U_0603_6.3V6K

23

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

28

of

57

5

4

3

2

1

VRAM DDR3 chips (1GB)

Mode E
Address

64Mx16 DDR3 *8==>1GB
D

DQSC[7..0]

23,30 DQSC[7..0]

DQSC#[7..0]

23,30 DQSC#[7..0]

DQMC[7..0]

23,30 DQMC[7..0]

U14
+MEM_VREF4

M8
H1

VREFCA
VREFDQ

CMDC7
CMDC10
CMDC24
CMDC6
CMDC22
CMDC26
CMDC5
CMDC21
CMDC8
CMDC4
CMDC25
CMDC23
CMDC9
CMDC12
CMDC14
CMDC30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDC29
CMDC13
CMDC27

M2
N8
M3

BA0
BA1
BA2

MDC[63..0]

23,30 MDC[63..0]

CMDC[30..0]

23,30 CMDC[30..0]

+1.5VSDGPU

GS@
R443
240_0402_1%

1
2

GS@
R444
240_0402_1%

C431
GS@
0.1U_0402_10V6K

+MEM_VREF4

C

+1.5VSDGPU

GS@
R445
240_0402_1%

1
2

C432
GS@
0.1U_0402_10V6K

E3
F7
F2
F8
H3
H8
G2
H7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ

J7
K7
K9

CK
CK
CKE/CKE0

CMDC0
CMDC2
CMDC11
CMDC15
CMDC28

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSC2
DQSC1

F3
C7

DQSL
DQSU

DQMC2
DQMC1

E7
D3

DML
DMU

DQSC#2
DQSC#1

G3
B7

DQSL
DQSU

CMDC20

T2

RESET

ZQ4

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

MDC21
MDC19
MDC16
MDC17
MDC18
MDC20
MDC23
MDC22

+MEM_VREF5 M8
H1

MDC13
MDC8
MDC14
MDC9
MDC12
MDC11
MDC15
MDC10

CMDC7
CMDC10
CMDC24
CMDC6
CMDC22
CMDC26
CMDC5
CMDC21
CMDC8
CMDC4
CMDC25
CMDC23
CMDC9
CMDC12
CMDC14
CMDC30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDC29
CMDC13
CMDC27

M2
N8
M3

BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDC0
CMDC2
CMDC11
CMDC15
CMDC28

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSC0
DQSC3

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMC0
DQMC3

E7
D3

DML
DMU

DQSC#0
DQSC#3

G3
B7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

MDC31
MDC24
MDC30
MDC25
MDC28
MDC26
MDC29
MDC27

DQSL
DQSU

CMDC20

T2

RESET

ZQ5

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSDGPU

0..31

CMD3

CMD0

CKE_L

CMD8

CMD1

CMD2

CMD2

CMD21
CMD24

CMD3

CMD23
CMD26
CMD7
CMD15
CMD13
CMD4
CMD18

CMD11

CMD29

CMD12

BA0

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

A4

A5

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CMD30
CMD31

32..63
A8

A8

D

CS0_L#
A7

A6

CMD4

A2

A1

CMD5

A11

A9

CMD6

A5

A4

CMD7

A0

A12

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

A11
CS0_H#

BA1
CS1_H#
ODT_H
C

RAS*
A7
CKE_H

Not Available

B

1

+1.5VSDGPU

MDC2
MDC7
MDC0
MDC5
MDC3
MDC6
MDC1
MDC4

+1.5VSDGPU

J7
K7
K9

1

CLKC0

GS@
R448
243_0402_1%
2

2

GS@
R447
243_0402_1%

23

VREFCA
VREFDQ

CLKC0
CLKC0#
CMDC3

1

B

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VSDGPU

CLKC0
CLKC0#
CMDC3

+MEM_VREF5
GS@
R446
240_0402_1%

U15

Mode C
Address

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

R449
R450
R451
R452
R453

1
1
1
1
1

GS@
GS@
GS@
GS@
GS@

2
2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

DDR3

ODTx

10k

CKEx

10k

RST
CS*

10k
No Termination

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

2

GS@
R455
160_0402_1%

CMDC3
CMDC0
CMDC16
CMDC20
CMDC19

Command Bit Default Pull-down

23

CLKC0#

+1.5VSDGPU

GS@
C452
4.7U_0603_6.3V6K

GS@
C451
4.7U_0603_6.3V6K
2
1

GS@
C450
4.7U_0603_6.3V6K
2
1

GS@
C449
4.7U_0603_6.3V6K
2
1

GS@
C448
4.7U_0603_6.3V6K
2
1

GS@
C447
4.7U_0603_6.3V6K
2
1

GS@
C446
4.7U_0603_6.3V6K
2
1

GS@
C445
4.7U_0603_6.3V6K
2
1

GS@
C444
4.7U_0603_6.3V6K
2
1

1
2

GS@ C443
0.1U_0402_16V4Z

GS@ C442
0.1U_0402_16V4Z
2
1

GS@ C441
0.1U_0402_16V4Z
2
1

GS@ C440
0.1U_0402_16V4Z
2
1

GS@ C439
0.1U_0402_16V4Z
2
1

GS@ C438
0.1U_0402_16V4Z
2
1

GS@ C437
0.1U_0402_16V4Z
2
1

GS@ C436
0.1U_0402_16V4Z
2
1

GS@ C435
0.1U_0402_16V4Z
2
1

1
2

GS@ C434
1000P_0402_50V7K
2
1

+1.5VSDGPU

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

29

of

57

5

4

3

2

1

VRAM DDR3 chips (1GB)

Mode E
Address

64Mx16 DDR3 *8==>1GB
D

DQMC[7..0]

23,29 DQMC[7..0]

CMDC[30..0]

23,29 CMDC[30..0]

DQSC#[7..0]

23,29 DQSC#[7..0]

U16

DQSC[7..0]

23,29 DQSC[7..0]

+MEM_VREF6

M8
H1

VREFCA
VREFDQ

CMDC9
CMDC24
CMDC10
CMDC13
CMDC26
CMDC22
CMDC21
CMDC5
CMDC8
CMDC23
CMDC28
CMDC4
CMDC7
CMDC14
CMDC12
CMDC27

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDC29
CMDC6
CMDC30

M2
N8
M3

BA0
BA1
BA2

MDC[63..0]

23,29 MDC[63..0]

+1.5VSDGPU
GS@
R457
240_0402_1%

2

1

GS@
R458
240_0402_1%

C

C453
GS@
0.1U_0402_10V6K

+MEM_VREF6

+1.5VSDGPU
GS@
R459
240_0402_1%

U17
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDC63
MDC56
MDC62
MDC58
MDC61
MDC59
MDC60
MDC57

+MEM_VREF7

MDC34
MDC36
MDC35
MDC38
MDC33
MDC37
MDC32
MDC39
+1.5VSDGPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKC1
CLKC1#
CMDC16

J7
K7
K9

CK
CK
CKE/CKE0

CMDC19
CMDC18
CMDC11
CMDC15
CMDC25

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSC7
DQSC4

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

DQMC7
DQMC4

E7
D3

DML
DMU

DQSC#7
DQSC#4

G3
B7

M8
H1

VREFCA
VREFDQ

CMDC9
CMDC24
CMDC10
CMDC13
CMDC26
CMDC22
CMDC21
CMDC5
CMDC8
CMDC23
CMDC28
CMDC4
CMDC7
CMDC14
CMDC12
CMDC27

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDC29
CMDC6
CMDC30

M2
N8
M3

BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDC48
MDC53
MDC50
MDC54
MDC49
MDC52
MDC51
MDC55
+1.5VSDGPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

CLKC1
CLKC1#
CMDC16

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDC19
CMDC18
CMDC11
CMDC15
CMDC25

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSC5
DQSC6

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMC5
DQMC6

E7
D3

DML
DMU

DQSC#5
DQSC#6

G3
B7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU

MDC42
MDC43
MDC41
MDC47
MDC40
MDC46
MDC44
MDC45

+1.5VSDGPU

1
2

GS@
R460
240_0402_1%

C454
GS@
0.1U_0402_10V6K

+MEM_VREF7

DQSL
DQSU

CMDC20

T2

RESET

ZQ6

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

CMDC20
ZQ7

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

0..31

CMD3

CMD0

CKE_L

CMD8

CMD1

CMD2

CMD2

CMD21
CMD24

CMD3

CMD23
CMD26
CMD7
CMD15
CMD13
CMD4
CMD18

CMD11

CMD29

CMD12

BA0

BA0

CMD27
CMD6

CMD13

BA2

A15

CMD14

A3

CMD17

CMD15

CMD19

CMD16

CMD22

CMD17

A4

A5

CMD12

CMD18

A13

A14

CMD28

CMD19

WE*

A10

CMD10

CMD20

A1

A2

CMD25

CMD21

A10

WE*

CMD9

CMD22

A12

A0

CMD1

CMD23

CS1_L#

CMD11

CMD24

RAS*

CMD0

CMD25

ODT_L

CMD5

CMD26

A6

CMD16

CMD27

CMD20

CMD28

RST

RST

CMD14

CMD29

A14

A13

CMD30

A15

BA2

LOW

HIGH

CMD30
CMD31

32..63
A8

A8

D

CS0_L#
A7

A6

CMD4

A2

A1

CMD5

A11

A9

CMD6

A5

A4

CMD7

A0

A12

CMD8

CAS*

CAS*

CMD9

BA1

A3

CMD10

A9

A11
CS0_H#

BA1
CS1_H#
ODT_H
C

RAS*
A7
CKE_H

Not Available

B

1

1

B

DQSL
DQSU

Mode C
Address

2

2

GS@
R464
160_0402_1%
23

2

GS@
R461
243_0402_1%

CLKC1
1

23

GS@
R462
243_0402_1%

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

CLKC1#

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

+1.5VSDGPU

1
2

GS@
C474
4.7U_0603_6.3V6K

1
2

GS@
C473
4.7U_0603_6.3V6K

1
2

GS@
C472
4.7U_0603_6.3V6K

1
2

GS@
C471
4.7U_0603_6.3V6K

1
2

GS@
C470
4.7U_0603_6.3V6K

1
2

C469
GS@
4.7U_0603_6.3V6K

1
2

GS@
C468
4.7U_0603_6.3V6K

GS@
C467
4.7U_0603_6.3V6K

1
2

1
2

GS@
C466
4.7U_0603_6.3V6K

C465
GS@
0.1U_0402_16V7K

C464
GS@
0.1U_0402_16V7K
2
1

C463
GS@
0.1U_0402_16V7K
2
1

C462
GS@
0.1U_0402_16V7K
2
1

C461
GS@
0.1U_0402_16V7K
2
1

C460
GS@
0.1U_0402_16V7K
2
1

C459
GS@
1U_0402_6.3V6K
2
1

C458
GS@
1U_0402_6.3V6K
2
1

C457
GS@
1U_0402_6.3V6K
2
1

1
2

C456
GS@
1U_0402_6.3V6K
2
1

+1.5VSDGPU

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

30

of

57

5

4

2

1

LCD POWER CIRCUIT

+LCDVDD

D

+3VS

+3VALW

1

1

C477
10U_0805_10V4Z

2

1

0.1U_0402_16V4Z

2

2

C476

C478

C479
680P_0402_50V7K

0.1U_0402_16V4Z

+LCDVDD

C480
68P_0402_50V8J

SM010014520 3000ma
220ohm@100mhz DCR
0.04

W=60mils
1

C482
4.7U_0805_10V4Z

R469
100K_0402_5%

2

S

Q21
2N7002E_SOT23-3

D

1

D

2
G

C481
0.047U_0402_16V7K

Q20
AO3413L_SOT23-3

G

2

1
PCH_ENVDD

PCH_ENVDD

1

16

3

3

S

1

3

S

2
1

2
G

2

2
1

R468
1K_0402_5%
2
1

D

Q19
2N7002E_SOT23-3

1

+INVPWR_B+
B+
L15
FBMA-L11-201209-221LMA30T_0805
2
1
L16
FBMA-L11-201209-221LMA30T_0805
W=60mils
2
1

Place closed to JLVDS1

+3VS

2

+LCDVDD

C475
4.7U_0805_10V4Z

2

2

R467
10K_0402_5%

1

R466
300_0603_5%

1

1

1

W=60mils

2

D

3

C483
0.1U_0402_16V4Z

2

LCD/LED PANEL Conn.
+INVPWR_B+

W=60mils
C

39

16

2

DPST_PWM

+3VS

U27
1

3

OE#
VCC

5

OUT

4

39

BKOFF#

R474 1

2 0_0402_5%

R475 1

2 10K_0402_5%

EDP_AUX_R
EDP_AUX#_R

DISPOFF#

EDP_TX1_R
EDP_TX1#_R

IN
INVTPWM

GND

1

R783
1
2
100K_0402_5%

DAC_BRIG
DISPOFF#
INVTPWM

DAC_BRIG

R476
10K_0402_5%

C486 2

1 220P_0402_50V7K DAC_BRIG

C487 2

1 220P_0402_50V7K INVTPWM

C488 2

1 220P_0402_50V7K DISPOFF#

EDP_TX0_R
EDP_TX0#_R
16 PCH_TXCLK+
16 PCH_TXCLK16 PCH_TXOUT2+
16 PCH_TXOUT2-

2

74AHC1G125GW_SOT353-5

16 PCH_TXOUT1+
16 PCH_TXOUT1-

+LCDVDD +3VS

16 PCH_TXOUT0+
16 PCH_TXOUT016 PCH_LCD_DATA
16 PCH_LCD_CLK

PCH_TXCLK+
PCH_TXCLKPCH_TXOUT2+
PCH_TXOUT2PCH_TXOUT1+
PCH_TXOUT1PCH_TXOUT0+
PCH_TXOUT0PCH_LCD_DATA
PCH_LCD_CLK

W=60mils

eDP

B

EDP_HPD

+3VS

Near JLVDS1

EDP_HPD

EDP_TXN1
EDP_TXP1

1

2
G
3

S

4
4

EDP_AUXN
EDP_AUXP

1
1

C489
C490

EDP_TX0#_R
EDP_TX0_R

EDP_TXN1
EDP_TXP1

0.1U_0402_16V7K EDP@ 2
0.1U_0402_16V7K EDP@ 2

1
1

C491
C494

EDP_TX1#_R
EDP_TX1_R

EDP_AUXN
EDP_AUXP

0.1U_0402_16V7K EDP@ 2
0.1U_0402_16V7K EDP@ 2

1
1

C495
C496

EDP_AUX#_R
EDP_AUX_R

17
17

R478 1
R479 1

USB20_P10
USB20_N10
C492
22P_0402_50V8J
@

2

R480
100K_0402_5%
EDP@

0.1U_0402_16V7K EDP@ 2
0.1U_0402_16V7K EDP@ 2

@
@

2 0_0402_5%
2 0_0402_5%

USB20_CMOS_P10
USB20_CMOS_N10

1

4
4

D
Q22
2N7002E_SOT23-3
EDP@

EDP_TXN0
EDP_TXP0

1

EDP_TXN0
EDP_TXP0

2

EDP_HPD#

4
4
1

4

R477
1K_0402_5%
1 EDP@ 2

2

+1.05VS_VCCP

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

C

B

G1
G2
G3
G4
G5

41
42
43
44
45

ACES_50398-04071-001
CONN@

C493
22P_0402_50V8J
@

L45
USB20_N10

3

USB20_P10

2

3
2

4

4

USB20_CMOS_N10

1

1

USB20_CMOS_P10

WCM2012F2S-900T04_0805

Modify for LVDS Camera USB cancel twist issue

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

31

of

57

A

B

C

D

E

ESD team Suggestion

1

W=40mils

2

3

2

3

+5VS

+R_CRT_VCC
D8
2
D7
PJDLC05C_SOT23-3

D6
PJDLC05C_SOT23-3

1
3

1

+CRT_VCC

F1
1.1A_6V_SMD1812P110TFW=40mils
2

RB491D-YS_SOT23-3

1

1

2

1

1

C497
0.1U_0402_16V4Z

CRT Connector

UMA/Optimus

2

1
3

1

2
MBC1608121YZF_0603

CRT_VSYNC_2

C509
10P_0402_50V8J
Y

CRT_HSYNC_1

4

G
G

16
17

2

100P_0402_50V8J

1

1

1

DSUB_12

C510
10P_0402_50V8J

DSUB_15

C511
68P_0402_50V8J

U18
74AHCT1G125GW_SOT353-5

1

A

1
L24

@

6
CRT_11 11
1
7
12
2
8
13
3
9
14
4
10
15
CRT_5
5

SUYIN_070546FR015S297ZR
CONN@

2

2

1 10K_0402_5%

CRT_HSYNC_2

2

P
PCH_CRT_HSYNC

G

16 PCH_CRT_HSYNC

OE#

5

R484 2

2
MBC1608121YZF_0603

2

+CRT_VCC
2 0.1U_0402_16V4Z

1
L23

T71
C507

2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

2

CRT_B_2

SM010012010 300ma 120ohm@100mhz DCR 0.4

C508 1

@

CRT_G_2

C506
10P_0402_50V8J

1

JCRT1
T70

C505
10P_0402_50V8J

2

CRT_R_2

C504
10P_0402_50V8J

2

CRT_B_1

C503
22P_0402_50V8J

2

CRT_G_1

C502
22P_0402_50V8J

2

L18
BLM18BA470SN1D_2P
1
2
L20
BLM18BA470SN1D_2P
1
2
L22
BLM18BA470SN1D_2P
1
2

CRT_R_1

C501
22P_0402_50V8J

C500
10P_0402_50V8J

2

C499
10P_0402_50V8J

R483
150_0402_1%

C498
10P_0402_50V8J

R481
R482
150_0402_1% 150_0402_1%

1

PCH_CRT_B
1

16 PCH_CRT_B

PCH_CRT_G

1

16 PCH_CRT_G

PCH_CRT_R

1

16 PCH_CRT_R

L17
BLM18BA470SN1D_2P
1
2
L19
BLM18BA470SN1D_2P
1
2
L21
BLM18BA470SN1D_2P
1
2

C512
68P_0402_50V8J

+CRT_VCC

P
PCH_CRT_VSYNC

2

A
3

G

16 PCH_CRT_VSYNC

1

5

2 0.1U_0402_16V4Z

OE#

C513 1

Y

4

CRT_VSYNC_1

U19
74AHCT1G125GW_SOT353-5
+CRT_VCC

3

3

1

1

+3VS

PCH_CRT_DATA

3
2

PCH_CRT_CLK

3

Q23
2N7002E_SOT23-3
DSUB_15

1
D

S

PCH DDC PU 2.2K on Page 17

D

G

16 PCH_CRT_CLK

DSUB_12

1

S

16 PCH_CRT_DATA

R487
4.7K_0402_5%
2

G

2

2

R486
4.7K_0402_5%

Q24
2N7002E_SOT23-3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
E

32

of

57

5

4

R502
0_0603_5%
@
1
2

D

3

2

1

SM070001310 400ma 90ohm@100mhz DCR 0.3
+HDMI_5V

W=40mils

HDMI_CLK+

+HDMI_5V_OUT
D9
1

1

RB491D-YS_SOT23-3

2

1.1A_6V_SMD1812P110TF

C514
0.1U_0402_16V4Z

16 PCH_DPB_N3
16 PCH_DPB_P3

C522 UMA@ 2
C523 UMA@ 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_CLKHDMI_CLK+

UMA@

S

HDMI_TX0HDMI_TX0+

3

1

HDMI_TX1HDMI_TX1+

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

1

Q25
2N7002E_SOT23-3
UMA@

C858
+3VSDGPU 0.1U_0402_16V4Z
OPT11@
1
2

NVIDA Recommand 10/08
OPT1.1
1 0.1U_0402_16V7K HDMI_TX21 0.1U_0402_16V7K HDMI_TX2+

2
2

1 0.1U_0402_16V7K HDMI_TX01 0.1U_0402_16V7K HDMI_TX0+

C530 OPT11@
C531 OPT11@

2
2

1 0.1U_0402_16V7K HDMI_CLK1 0.1U_0402_16V7K HDMI_CLK+

B
A

1

Y
G

C528 OPT11@
C529 OPT11@

4

22 VGA_HDMI_DET

R505 1

2

D

HDMI_R_CK+

2
3
0_0402_5%

HDMI_R_CK-

+3VSDGPU

1

2

0_0402_5%

HDMI_R_D0+

4

3

HDMI_TX0-

R507 1

2

HDMI_TX1+

R508 1

2

HDMI_TX1-

R510

HDMI_TX2+

R511

HDMI_TX2-

1

2

4

3

1

2

1

2

1
4

3
2

3
0_0402_5%

HDMI_R_D0-

0_0402_5%

HDMI_R_D1+

2
3
0_0402_5%

HDMI_R_D1-

0_0402_5%

HDMI_R_D2+
C

2

R513 1

2

2
3
0_0402_5%

HDMI_R_D2-

HDMI_HPD

U44
NC7SZ08P5X_NL_SC70-5
OPT11@

HDMI_TX2- R515 1 UMA@ 2 680_0402_5%
HDMI_TX2+ R516 1 UMA@ 2 680_0402_5%

3

1
D

1 0.1U_0402_16V7K HDMI_TX11 0.1U_0402_16V7K HDMI_TX1+

S

24 VGA_HDMI_TXC24 VGA_HDMI_TXC+

2
2

R794
1K_0402_5%
2 OPT11@1

G

24 VGA_HDMI_TXD024 VGA_HDMI_TXD0+

C526 OPT11@
C527 OPT11@

2

3

24 VGA_HDMI_TXD124 VGA_HDMI_TXD1+

HDMI_TX0+

1
L28
WCM2012F2S-900T04_0805
@
4

2

2
2

5

C524 OPT11@
C525 OPT11@

P

24 VGA_HDMI_TXD224 VGA_HDMI_TXD2+

3
2

1
L27
WCM2012F2S-900T04_0805
@
4

R509
100K_0402_5%

C

Optimus 1.1

PCH_DPB_HPD 16

2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

C519 UMA@ 2
C520 UMA@ 2

2

C517 UMA@ 2
C518 UMA@ 2

16 PCH_DPB_N2
16 PCH_DPB_P2

1

HDMI_HPD

16 PCH_DPB_N1
16 PCH_DPB_P1

4

R504 1

L26
WCM2012F2S-900T04_0805
@
4

2

HDMI_TX2HDMI_TX2+
D

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

C521
220P_0402_50V7K

C515 UMA@ 2
C516 UMA@ 2

2

HDMI_CLK-

1

R506
1M_0402_5%
UMA@

2
G

UMA & Optimus 1.0
16 PCH_DPB_N0
16 PCH_DPB_P0

0_0402_5%

2

1

+3VS

1

2

3

1

+5VS

R503 1

1
L25
WCM2012F2S-900T04_0805
@
4

F2

2

DGPU_HPD_INT# 18

Q26
2N7002E_SOT23-3
OPT11@

HDMI_GND

HDMI_TX1- R517 1 UMA@ 2 680_0402_5%
HDMI_TX1+ R518 1 UMA@ 2 680_0402_5%
HDMI_TX0- R519 1 UMA@ 2 680_0402_5%
HDMI_TX0+ R520 1 UMA@ 2 680_0402_5%

3

1

G

2

HDMI_SCLK_R

D

HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-

3

1

HDMI_SDATA

Q29
2N7002E_SOT23-3

2

Pull high at VGA side

HDMI_SDATA_R

D

1 OPT11@2 0_0402_5%

1109 RF request
HDMI_SCLK

Q28
2N7002E_SOT23-3

S

R528

24 VGA_HDMI_SDATA

HDMI_R_CK-

2

1 OPT11@2 0_0402_5%

S

R526

24 VGA_HDMI_SCLK

HDMI_SDATA
HDMI_SCLK

1

1

G

2

1 UMA@ 2 0_0402_5%
1 UMA@ 2 0_0402_5%

1

R525
R527

16 SDVO_SCLK
16 SDVO_SDATA

HDMI_HPD
+HDMI_5V_OUT
+3VS

Place closed to JHDMI1

S

JHDMI1

2 1
R524
2.2K_0402_5%

SDVO_SDATA

Q27
2N7002E_SOT23-3

HDMI connector
D12
RB751V-40_SOD323-2

1

SDVO_SCLK

R530 1 UMA@ 2 2.2K_0402_1%

2

2

R529 1 UMA@ 2 2.2K_0402_1%

2 1
R523
2.2K_0402_5%

B

D11
RB751V-40_SOD323-2

D

2
G

+3VS

+3VS

1

UMA 680_0402_5%
DIS 499_0402_1%

+HDMI_5V_OUT

3

HDMI_CLK- R521 1 UMA@ 2 680_0402_5%
HDMI_CLK+ R522 1 UMA@ 2 680_0402_5%

C532
47P_0402_50V8J
@

HDMI_R_D1+
HDMI_R_D2-

C533
47P_0402_50V8J
@

HDMI_R_D2+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

B

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

Optimus 1.1 Option Component
20
21
22
23

R515 2 OPT11@
1 499_0402_1%
R516 2 OPT11@
1 499_0402_1%
R517 2 OPT11@
1 499_0402_1%
R518 2 OPT11@
1 499_0402_1%
R519 2 OPT11@
1 499_0402_1%
R520 2 OPT11@
1 499_0402_1%
R521 2 OPT11@
1 499_0402_1%
R522 2 OPT11@
1 499_0402_1%

SUYIN_100042GR019M23DZL
CONN@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

33

of

57

5

4

3

2

1

D

D

SATA HDD1 Conn.
CL 4.0 mm
JHDD1

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+3VS

+5VS

R531
0_0805_5%
1
2

+5VS_HDD1

C

+3VS

C538
0.1U_0402_16V4Z

+5VS_HDD1
C

100mils

C551
1000P_0402_50V7K

1U_0402_6.3V6K

C542
1000P_0402_50V7K

C540

2

C550
0.1U_0402_16V4Z

1

C541
0.1U_0402_16V4Z

C539
10U_0805_10V4Z

ACES_50406-02071-001
CONN@

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2

C536 1
C537 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4

1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

2

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2

C534 1
C535 1

1

13 SATA_PRX_DTX_N0
13 SATA_PRX_DTX_P0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

2

13 SATA_PTX_DRX_P0
13 SATA_PTX_DRX_N0

SATA ODD Conn.
JODD1

ODD_DA#

R534

1

2

0_0402_5%

ODD_DETECT#_R
+5VS_ODD

R535

1

2

0_0402_5%

ODD_DA#_R

8
9
10
11
12
13

DP
5V
5V
MD
GND
GND

+5VS_ODD

80mils

GND
GND

14
15

SUYIN_127382FB013S266ZR
CONN@

1

2

C549

1U_0402_6.3V6K

1

18 ODD_DETECT#
+5VS_ODD

GND
TX+
TXGND
RXRX+
GND

2

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
2
3
4
5
6
7

2

S
G

13 SATA_PRX_DTX_N2
13 SATA_PRX_DTX_P2

C545 1
C546 1

3

1

S

2

D

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

17

2

1
2
G
Q31
2N7002E_SOT23-3

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

C552
0.1U_0402_25V6

ODD_EN#

Q30
SI3456DDV-T1-GE3_TSOP6

R536
1.5M_0402_5%

18

3

ODD_EN

4

1

1

B

6
5
2
1

C543 1
C544 1

C548
10U_0805_10V4Z

2

R533
470K_0402_5%

C547
1U_0402_6.3V6K

1

2

D

+VSB

13 SATA_PTX_DRX_P2
13 SATA_PTX_DRX_N2

1

R532
0_0805_5%
@
1
2

2

+5VS_ODD

+5VS

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

34

of

57

5

4

3

2

1

Power On strapping
Pin
+3V_LAN

Check PU/PD on MB side
@

1
R539

D

LED0

H

LAN_MIDI0LAN_MIDI1+

H:SWR Switch mode regulator Select

LAN_WAKE#
2
4.7K_0402_5%

LED1

AR8151-BL1A
applies
switch mode
regulator.

AR8151 Pin39
*
H: switch regulator applied.
L: switch regulator isn't applied.

LAN_CLKREQ#
2
4.7K_0402_5%

1
R544

LAN_MIDI0+

L:Over Clock Disable *

PLT_RST#
2
4.7K_0402_5%

1
R541

Place Close to LAN chip

Chip Default

Description
H:Over Clock Enable

LAN_MIDI1LAN_MIDI2+
LAN_MIDI2-

AR8152, Pin23 is CLKREQ

LAN_MIDI3+

Close to lan chip.

LAN_MIDI3-

R537 1
49.9_0402_1%
R538 1
49.9_0402_1%
R540 1
49.9_0402_1%
R542 1
49.9_0402_1%
R543 1 8151@
49.9_0402_1%
R545 1 8151@
49.9_0402_1%
R546 1 8151@
49.9_0402_1%
R547 1 8151@
49.9_0402_1%

2

@1

2

1

2 C553 1000P_0402_50V7K

2

@1

2

1

2

@1

2 C557 1000P_0402_50V7K

2

1

2

@1

2 C558 0.1U_0402_16V4Z
8151@
2 C559 1000P_0402_50V7K

2

1

2 C554 0.1U_0402_16V4Z
2 C555 1000P_0402_50V7K
2 C556 0.1U_0402_16V4Z

D

2 C560 0.1U_0402_16V4Z
8151@

Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+
resister and cap
no overclocking
PD 5.1K

PCH_PCIE_WAKE#

R552 1

EC_PME#

R553 1

1 0_0402_5%
1 0_0402_5%

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
LAN_RST#

15,37,44 PCH_PCIE_WAKE#
39

C

EC_PME#

@

2 0_0402_5%

LAN_WAKE#

2 0_0402_5%

2

PERST#

3

WAKE#

25
26
28
27
LAN_XTALO
LAN_XTALI

7
8

RBIAS

10

VDD33

1

LX
VDDCT

4

20mils

2

2

1

2

C573

C574

C572

1

0.1U_0402_16V4Z

C571

C570

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

8151@

0.1U_0402_16V4Z

C569

8151@

+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL

1

2

0.1U_0402_16V4Z

14 LAN_CLKREQ#

1 8151@ 2
R556
0_0402_5%

13
19
31
34
6
41

CLKREQ#
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG

40

+1.7_LX

5

+1.7_VDDCT

24
37

AVDDH
AVDDH
AVDDH_REG

16
22
9

2

+3V_LAN

1
2
R554 2.37K_0402_1%

1

40mils

+1.7_VDDCT

2 C564
0.1U_0402_16V4Z

2

20mils

+1.1_DVDDL
+1.1_DVDDL

1

GND
AR8151-BL1A-RL
8151@

2
8152 is LED2 Function (NC)

1U_0402_6.3V6K

1

1 8151@ 2 +2.7_AVDDH
R738 0_0402_5%

1

C576

2

1

C566

2

1

2

1

@

2

+3VALW

R555
0_1206_5%
@

C

1

1

3

Q37
AO3413L_SOT23-3
@

PCH_PWR_EN#

PCH_PWR_EN# 20,46

1U_0402_6.3V6K

20mils
+2.7_AVDDH_R
+2.7_AVDDH
+2.7_AVDDH

1

2

+1.7_LX

1

DVDDL
DVDDL_REG

+3VALW_PCH
R557
0_1206_5%

40mils

C575

LAN_CLKREQ#

LAN_RBIAS

36
36
36
36
36
36
36
36

G

XTLO
XTLI

LAN_MIDI0LAN_MIDI0+
LAN_MIDI1LAN_MIDI1+
LAN_MIDI2LAN_MIDI2+
LAN_MIDI3LAN_MIDI3+

S

8152@
1
2
0.1U_0402_16V4Z

TEST_RST
TESTMODE

12
11
15
14
18
17
21
20

D

C563

SMCLK
SMDATA

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

LAN_ACT 36
LAN_LINK# 36

LAN_CLKREQ#

2

REFCLK_N
REFCLK_P

14 CLK_PCIE_LAN#
14 CLK_PCIE_LAN

R551 2
R549 2

R550 1 8152@ 2
0_0402_5%

C568

RX_P

32
33

CLK_PCIE_LAN#
CLK_PCIE_LAN

38
39
23

10U_0805_10V4Z

RX_N

35

LED_0
LED_1
LED_2

C567

36

PCIE_PTX_C_DRX_P1

14 PCIE_PTX_C_DRX_P1

8151-AL1A

10U_0805_10V4Z

PCIE_PTX_C_DRX_N1

14 PCIE_PTX_C_DRX_N1

Atheros

C565

TX_P

0.1U_0402_16V4Z

30

2

C565 & C566 Close pin1 < 200mil
C567 & C568 Close pin < 400mil

8151@
1

2

1

2

1U_0402_6.3V6K

1

C580

2

C581

PCIE_PRX_C_DTX_P1

2

1

0.1U_0402_16V4Z

2 0.1U_0402_16V7K

C579

PCIE_PRX_DTX_P1 C562 1

0.1U_0402_16V4Z

TX_N

14 PCIE_PRX_DTX_P1

C578

29

0.1U_0402_16V4Z

PCIE_PRX_C_DTX_N1

C577

2 0.1U_0402_16V7K

Note 2 : C553, C555, C557, C559 reserved for EMI.

2
5.1K_0402_5%

0.1U_0402_16V4Z

PCIE_PRX_DTX_N1 C561 1

0.1U_0402_16V4Z

U20

Place Close to Chip
14 PCIE_PRX_DTX_N1

1
R548

LED0,1,2 intel Pull UP

1U_0402_6.3V6K

LAN_XTALI
LAN_XTALO
Y4

Near
Pin34

Near
Pin9

Near
Pin6

Near
Pin22

Near Near
Pin16 Pin37

Near
Pin24
B

C583

1

Near
Pin31

2

25MHZ_20PF_7A25000012

C582

33P_0402_50V8J

1

Near
Pin19

2

1

2

33P_0402_50V8J

B

Near
Pin13

Note: Place Close to LAN chip
L2 DCR< 0.15 ohm
Rate current > 1A
+1.7_VDDCT

+1.7_LX

1

Pin4

R556

C563

Pin23

2

40mils

10U_0805_10V4Z

1

C587

LAN_RST#

2

0.1U_0402_16V4Z

4

Configure

1
2
4.7UH_SIA4012-4R7M_20%
1

C586

5

Configure

P
Y

A

@

G

PLT_RST#

5,17,38,39,44 PLT_RST#

Pull low 100K at PCH side(P17)

U21
@
2 B

C584
0.1U_0402_16V4Z
1
2
@

C585

+3V_LAN

1000P_0402_50V7K

L30

R550

3

NC7SZ08P5X_NL_SC70-5

1
R558

A

2
0_0402_5%

AR8152

VDDCT_REG

AR8151

CLKREQn

CLKREQn

*

*

Close to
Pin40

LED[2]

*

A

Reserve for 8151A/B PERST# leakage issue

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

35

of

57

5

4

3

2

1

D

D

BH GS5009-E

TAIMAG IH-160


T63
JRJ45
RJ45_MIDI0RJ45_MIDI0+

TD3TD3+
TCT3

MX3MX3+
MCT3

16
17
18

RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI2RJ45_MIDI2+
RJ45_MIDI3RJ45_MIDI3+

LAN_MIDI1LAN_MIDI1+

LAN_MIDI1LAN_MIDI1+

9
8
7

LAN_MIDI2LAN_MIDI2+

LAN_MIDI2LAN_MIDI2+

6
5
4

TD2TD2+
TCT2

MX2MX2+
MCT2

19
20
21

3
2
1

TD1TD1+
TCT1

MX1MX1+
MCT1

22
23
24

LAN_MIDI3LAN_MIDI3+

LAN_MIDI3LAN_MIDI3+

C

+1.7_VDDCT

S X'FORM_ IH-160 LAN
SP050006F00

25mil

2

@

2

0.1U_0402_16V4Z

C594
C599

0.1U_0402_16V4Z

C593
C598
@

1

RJ45_MIDI32

@ D40

2

1B88069X9231T203_4P5X3P2-2

@ D41

2

1B88069X9231T203_4P5X3P2-2

@ D42

2

1B88069X9231T203_4P5X3P2-2

@ D43

2

1B88069X9231T203_4P5X3P2-2

LAN_LINK#
@
C589
470P_0402_50V7K

Yellow LED-

7

PR4+

RJ45_MIDI1-

6

PR2-

RJ45_MIDI2-

5

PR3-

RJ45_MIDI2+

4

PR3+

RJ45_MIDI1+

3

PR2+

RJ45_MIDI0-

2

PR1-

RJ45_MIDI0+

1

PR1+

9

Green LED+

15
13

Guide Pin
C

SHLD1

10

2
300_0402_5%

SHLD1
DETECT PIN1

PR4-

RJ45_MIDI3+

1
R563

1

Yellow LED+

12
8

+3V_LAN
35

11

14

Green LEDSANTA_130452-3_13P-T
CONN@

2

RJ45_GND
RJ45_GND

C595
1000P_1206_2KV7K
1
2

LANGND

40mil

40mil
LAN_ACT
LAN_LINK#

L31
100UH_SSC0301101MCF_0.18A_20%

For EMI

D36
PJDLC05C_SOT23-3
2

2

0.1U_0402_16V4Z

C592
@

1

2

C588
470P_0402_50V7K
@

2
300_0402_5%

1

1

2

2

1

1000P_0402_50V7K

@

1

1

1000P_0402_50V7K

1

2

C597

2
2

C596

C590
1U_0402_6.3V6K

1

1000P_0402_50V7K

C591

1

1

0.1U_0402_16V4Z

R560
0_0603_5%

1
R559

LAN_ACT

Reserved for ESD

+1.7_VDDCT_R

2

1000P_0402_50V7K

1

35

1

13
14
15

3

MX4MX4+
MCT4

2

35
35

TD4TD4+
TCT4

2

35
35

12
11
10

3

35
35

LAN_MIDI0LAN_MIDI0+

LAN_MIDI0LAN_MIDI0+

2
1
R561
75_0402_1%
2
1
R562
75_0402_1%
2
1
R564
75_0402_1%
2
1
R565
75_0402_1%

35
35

D13
PJDLC05C_SOT23-3
@

Close CT3
Close CT1
Close CT2
Close CT4

LANGND
B

1

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

36

of

57

A

B

C606
0.1U_0402_16V4Z

1

C605
0.1U_0402_16V4Z

2

C604
4.7U_0805_10V4Z

C607
0.1U_0402_16V4Z

For 3G / GPS

1

+3VS_WLAN
JMINI1

14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1

14 PCIE_PRX_DTX_N2
14 PCIE_PRX_DTX_P2

14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2

R574
0_0402_5%
2 E51TXD_P80DATA1_R
2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Primary Power (mA)
Peak

Normal

+3VS

1000

750

+3V

330

250

+1.5VS

500

WL_OFF#
PLT_RST_BUF#
R569 1
MINI1_SMBCLK R570 1
MINI1_SMBDATA R571 1

2 0_0603_5%
@
@

Auxiliary Power (mA)
Normal

53
54
55
56

375

5 (Not wake enable)

USB20_N8 17
USB20_P8 17
R573 1

2 0_0402_5%
MINI1_LED# 39

(9~16mA)
R575
100K_0402_5%

22

ACES_88910-5204
CONN@

WWAN_OFF# 18
WWAN_LED# 39

USB20_N9
USB20_P9

USB20_N9 17
USB20_P9 17

USB20_N12
USB20_P12
R641 10K_0402_5%
1
2
UIM_DET_EC
EC_SIM_DETECT#

USB20_N12 17
USB20_P12 17
+3VS
UIM_DET_EC 39
EC_SIM_DETECT# 39
WWAN_DET#_EC 39

R577
1
2
100K_0402_5%
+VSB
+VSB

+3VALW

2

+USB_VCCB

2

G
1

USB20_N1
USB20_P1

USB20_N1
USB20_P1

+USB_VCCB

W=120mils
39
42
42
42
42
42
42
42

+3VALW
LID_SW#
SPDIF_OUT
+5VSPDIF
SPDIF_PLUG#
HP_LEFT
HP_RIGHT
MIC1_VREFO
MIC1_L
MIC1_R
MIC_PLUG#

LID_SW#
SPDIF_OUT
SPDIF_PLUG#
HP_LEFT
HP_RIGHT

1
2

GND

ACES_88514-02601-071
CONN@

GND

8
7

1

BT@

R580
300_0603_5%
BT@

D

S

2
G

For AUDIO GND
B

G2 6
G1 5
4
3
2
1

6
5
4
3
2
1

USB20_P13 17
USB20_N13 17

ACES_87212-06G0
CONN@

BT Wire Cable Note:
Pin 3, Pin 4 NC

Q33
2N7002E_SOT23-3
BT@

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GND

3

JBT1

+BT_VCC
BT@

+BT_VCC

(Port 13)

W=40mils
C617
0.1U_0402_16V4Z

USB20_N0
USB20_P0

17
17

USB20_N0
USB20_P0

28
27

BT Conn.

Q32
BT@
AO3413L_SOT23-3

C616
4.7U_0805_10V4Z

17
17

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND1
GND2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

C615
0.1U_0402_16V4Z
BT@

USB/B Conn.

1

SYSON#

BT@
C614
1U_0603_10V6K

2

BT_ON#

BT_ON# 1 BT@
2
R579 10K_0402_5%

S

1

C613
0.1U_0402_16V4Z
BT@

USB_OC0# 17

AP2301MPG-13_MSOP8

+3VS

2

EPAD

8
7
6
5

3

2

VOUT
VOUT
VOUT
FLG

1

+3VALW

GND
VIN
VIN
EN

9

1

1
2
3
4

(Port 0,1)

A

WWAN_OFF#
WWAN_LED#

Q54
2N7002E_SOT23-3

JUSB1

4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+3VS_WLAN

4 mm High

D

SYSON#

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_87213-2000G
CONN@

18
46

GND

PCH_SMBCLK 14
PCH_SMBDATA 14

U22

C612
4.7U_0805_10V4Z

21

WL_OFF# 18
PLT_RST_BUF# 17
+3VS

2 0_0402_5%
2 0_0402_5%

+3VALW

J3G1

2

2
R490
1K_0402_5%

+5VALW

3

Peak: 2.75A
Normal: 1.1A

250 (wake enable)

3

S

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Power

2

D

2
G

2
4
6
8
10
12
14
16

1

1
BT_ON#

3

D33
RB751V-40_SOD323-2
@
BT_CTRL
1
2

39,46,52,53 SUSP#

2
4
6
8
10
12
14
16

G1
G2
G3
G3

R578
0_0402_5%

1
3
5
7
9
11
13
15

1

To 3G Module Connect

1

1
1

39 E51TXD_P80DATA
39 E51RXD_P80CLK

1
3
5
7
9
11
13
15

1

(WLAN_BT_DATA)
(WLAN_BT_CLK)

14 MINI1_CLKREQ#

R576
100K_0402_5%
2
1

Mini Card Power Rating

+1.5VS +3VS_WLAN

R568
0_0402_5%
@
1
2

15,35,44 PCH_PCIE_WAKE#

2

E

2

1

1

1

C603
0.1U_0402_16V4Z

2

60mil

D

+3VS_WLAN

2

C602
4.7U_0805_10V4Z

+3VS_WLAN

R566
0_1206_5%
2
1

2

+3VS

+1.5VS

1

1

+3VS_WLAN

2

For Wireless LAN

C

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
E

37

of

57

A

B

C

D

+3VS

+3VS_CARD
1
R833

Card Reader

E

40 mils

40 mils

U23

1

PCIE_PTX_C_DRX_p3

1

HSIP

RREF

14 PCIE_PTX_C_DRX_N3

PCIE_PTX_C_DRX_N3

2

HSIN

3V3_IN

47

14 CLK_PCIE_CARD

CLK_PCIE_CARD

3

REFCLKP

CLK_REQ#

46

CARD_CLKREQ#

14 CLK_PCIE_CARD#

CLK_PCIE_CARD#

4

REFCLKN

PERST#

45

PLT_RST#

5

AV12

EEDO

44

6

HSOP

EECS

43

7

HSON

EESK

42

8

GND

GPIO/EEDI

41

9

DV12

MS_INS#

40

1
C618
PCIE_PRX_DTX_P3 1
C619
PCIE_PRX_DTX_N3 1
C621

14 PCIE_PRX_DTX_N3

1

2

1

2

20 mils DV12
40 mils
40 mils
XD_CD#

20 mils

2

@

1

2

C631
0.1U_0402_10V7K

Close to connector
2

C630
4.7U_0603_6.3V6K

1

DV33_18

1
R584
SD_D0_R
1
@
R585
SD_CLK_R
1
2
1
C633 5P_0402_50V8C
R586
SD_CMD_R
1
R587
SD_D3_R
1
R588

RREF R581 2

1 6.2K_0603_1%

40 mils

CARD_CLKREQ# 14
PLT_RST# 5,17,35,39,44

5IN1_LED#

5IN1_LED# 41

MS_INS#
SD_CD#

Card1_3V3

SD_CD#

39

11

3V3_IN

SP15

38

SP15_SDWP_XDD7

12

Card2_3V3

SP14

37

SP14_MSCLK_XDD6

13

XD_CD#

SP13

36

SP13_MSD7_XDD5

14

DV33_18

SP12

35

SP12_MSD3_XDD4

15

GND

SP11

34

SP11_MSD6_XDD3

SP1_SDD7_XDRDY 16

SP1

SP10

33

SP10_MSD2_XDD2

SP2_SDD6_XDRE#

17

SP2

SP9

32

SP9_MSD0_XDD1

SP3_SDD5_XDCE#

18

SP3

SP8

31

SP8_MSD4_XDD0

SD_D1
2
0_0402_5%
SD_D0
2
0_0402_5%
SD_CLK
2
33_0402_1%
SD_CMD
2
0_0402_5%
SD_D3
2
0_0402_5%

SP4

SP7

30

20

SD_D1

SP6

29

SP6_MSD5_XDALE

21

SD_D0

SP5

28

SP5_MSBS_XDCLE

DV12_S

27

GND

26

SD_D2

25

SD_CLK

23

SD_CMD

24

SD_D3

2 SP14_MSCLK_XDD6_R
2
0_0402_5%
@

1
R583

1

2

SP7_MSD1_XDWP#

22

1

2
1
C620 0.1U_0402_10V7K

10

SP4_SDD4_XDWE# 19
SD_D1_R

48

C629
5P_0402_50V8C

2

1

C628
0.1U_0402_10V7K

2

+3VS_CARD
C627
10U_0603_6.3V6M

2

1

C626
0.1U_0402_10V7K

2

1

C625
0.1U_0402_10V7K

1

C624
10U_0603_6.3V6M

2

C623
0.1U_0402_10V7K

R582
100K_0402_5%

1

2
4.7U_0603_6.3V6K
2 PCIE_PRX_C_DTX_P3
0.1U_0402_10V7K
2 PCIE_PRX_C_DTX_N3
0.1U_0402_10V7K

1
2
C622 0.1U_0402_10V7K

+ODR_PWR

@

20 mils AV12

+3VS_CARD

10 mils

14 PCIE_PTX_C_DRX_P3

14 PCIE_PRX_DTX_P3
+ODR_PWR

Modify R02, Add 0R between
+3VS and +3VS_CARD

2
0_0805_5%

20 mils
SD_D2
1
R589

1
C632

2
4.7U_0603_6.3V6K

1
C634

2
0.1U_0402_10V7K

SD_D2_R
2
0_0402_5%

RTS5209-GR_LQFP48_7X7

+ODR_PWR

+ODR_PWR

Reserve for EMI please close to JREAD1

JREAD1

3

22

XD-VCC

SP8_MSD4_XDD0
SP9_MSD0_XDD1
SP10_MSD2_XDD2
SP11_MSD6_XDD3
SP12_MSD3_XDD4
SP13_MSD7_XDD5
SP14_MSCLK_XDD6
SP15_SDWP_XDD7

30
29
28
27
26
25
24
23

XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7

SP4_SDD4_XDWE#
SP7_MSD1_XDWP#
SP6_MSD5_XDALE
XD_CD#
SP1_SDD7_XDRDY
SP2_SDD6_XDRE#
SP3_SDD5_XDCE#
SP5_MSBS_XDCLE

33
32
34
39
38
37
36
35

XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE

31
40

XD GND
XD GND

41
42

SD CD/WP GND
SD CD/WP GND

SD4-VDD
MS9-VCC

11
18

SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP

9
4
3
21
19
16
1
2

SD6-VSS
SD3-VSS

6
13

MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS

17
10
8
12
15
14
7
5
20

SD_CLK_R
SD_D0_R
SD_D1_R
SD_D2_R
SD_D3_R
SD_CMD_R
SD_CD#
SP15_SDWP_XDD7

1

2

2

R590
33_0402_5%

1

C635
6P_0402_50V8D
3

Reserve for EMI
please close to JREAD1

SP14_MSCLK_XDD6_R
SP9_MSD0_XDD1
SP7_MSD1_XDWP#
SP10_MSD2_XDD2
SP12_MSD3_XDD4
MS_INS#
SP5_MSBS_XDCLE

1

2

R591
33_0402_5%

1

2

C636
6P_0402_50V8D

T-SOL_144-1300002600_NR
CONN@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
E

38

of

57

5

4

3

2

1

+3VALW_EC

+3VLP

ESD 12/03
PLT_RST#

LID_SW#

R592

2

1 100K_0402_5%

+3VALW_EC
+5VS

EC_SMI#

R605

1

2 2.2K_0402_5%

EC_SMB_DA1

R606

1

2 2.2K_0402_5%

EC_SMB_CK1

18
EC_SCI#
41 PWR_SUSP_LED

40,41

KSI[0..7]

40,41

KSO[0..17]

R610

1

2 2.2K_0402_5% EC_SMB_CK2

R611

1

2 2.2K_0402_5% EC_SMB_DA2

R615

1

2 10K_0402_5% EC_SCI#

48,50
48,50
14,22
14,22

1
2
3
4
5
7
8
10

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
PWR_SUSP_LED

12
13
37
20
38

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

KSO[0..17]

2

4
OSC
3

2

NC

C652
15P_0402_50V8J

NC

OSC

1

1

EC_XCLK0

1
2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
WWAN_DET#_EC
MINI1_LED#
USB_CHARGE_2A#
GPU_VID0
USB_CHARGE_100mA
FAN_SPEED1
PCH_PWR_EN
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
TP_LED_ON/OFF
NUM_LED#

AD

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

DAC_BRIG
EC_SIM_DETECT#

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

Board ID

EC_ACIN

C645

1 100P_0402_50V8J ECAGND
BATT_TEMP 50
BI_EC
40
ADP_I
48,50

ACIN

15,46,48

1 100P_0402_50V8J

2

T69

DAC_BRIG 31
EC_SIM_DETECT# 37
@ T67
@ T68

U25

97
98
99
109

GPU_VID1
HDA_SDO
LID_SW#

119
120
126
128

FRD#_R
FWR#_R
SPI_CLK_R
FSEL#_R

73
74
89
90
91
92
93
95
121
127

H_PROCHOT#_EC

EC_MUTE# 42
GFX_CORE_PWRGD 54
WWAN_LED# 37

2

A

1
C648

R607
100K_0402_5%

TP_CLK 40
TP_DATA 40
54

2
0.1U_0402_16V4Z

4
C

SN74LVC1G06DCKR_SC70-5

R609
0_0402_5%
2
1

VR_HOT#

VR_HOT#

Y

H_PROCHOT# 5,50

GPU_VID1 22,55
HDA_SDO 13
LID_SW# 37
R612
R613
R614
R616

1
1
1
1

UIM_DET_EC
EC_PECI
R617 1
USB_CHARGE_CB
BATT_AMB_LED#
CAPS_LED#
BATT_BLUE_LED#
PWR_LED
SYSON
VR_ON
EC_ACIN

2
2
2
2

Latest design guide suggest change UE4 to 74LVC1G06.

0_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

FRD#
FWR#
SPI_CLK
FSEL#

2 43_0402_1%
USB_CHARGE_CB 45
BATT_AMB_LED# 41
CAPS_LED# 41
BATT_BLUE_LED# 41
PWR_LED 41
SYSON
44,46,51
VR_ON
54

UIM_DET_EC 37
H_PECI
5,18

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

PM_SLP_S4#
ENBKL
EAPD
SA_PGOOD
SUSP#
PBTN_OUT#
NV_PERFORMANCE

V18R

124

+V18R

128KB

U26
20mils
C650
0.1U_0402_16V4Z

PCH_RSMRST#
LID_SW_OUT#
EC_ON
EC_PME#
PCH_PWROK
BKOFF#
PWR_SAVE_LED#
WLAN_LED#
BATT_RED_LED#

SPI ROM

+3VALW_EC

PCH_RSMRST# 15
LID_SW_OUT# 14
EC_ON
40
EC_PME# 35
PCH_PWROK 15
BKOFF# 31
PWR_SAVE_LED# 41
WLAN_LED# 41
BATT_RED_LED# 41

8

VCC

3

W

VSS

4

7

HOLD

FSEL#

1

S

SPI_CLK

6

C

FWR#

5

D

B

Q

FRD#

2

MX25L1005AMC-12G
SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP 8P 3.3V)

GPI

PM_SLP_S4# 15
ENBKL
16
EAPD
42
SA_PGOOD 52
SUSP#
37,46,52,53
PBTN_OUT# 15
NV_PERFORMANCE 22

SPI_CLK

R618
22_0402_5%
@
2
1

C653
100P_0402_50V8J
@
1
2

Reserve for EMI please close to U26
C654
4.7U_0805_10V4Z

20mil

L33
ECAGND 2
1
FBMA-L11-160808-800LMT_0603

Analog Project ID definition,

2

Analog Board ID definition,
Please see page 3.

EC_MUTE#
GFX_CORE_PWRGD
WWAN_LED#
H_PROCHOT#_EC
TP_CLK
TP_DATA

100
101
102
103
104
105
106
107
108

Project ID
+3VALW_EC

83
84
85
86
87
88

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

XCLK1
XCLK0

KB930QF_A1

D14
1
RB751V-40_SOD323-2

2

122
123

1 200K_0402_5%

2
2

@

AGND

EC_XCLK1
EC_XCLK0
0_0402_5%

2 10K_0402_5%

1

+3VS

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

2

C647 2

BATT_TEMP
BI_EC
ADP_I
AD_BID0
AD_PID0

69

2

3G_LED# 41
BEEP#
42
FAN_PWM 45
ACOFF
47

63
64
65
66
75
76

GND
GND
GND
GND
GND

@
1
R619
R655 1
@
100K_0402_5%

SUSCLK

3G_LED#
BEEP#
FAN_PWM
ACOFF

21
23
26
27

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

11
24
35
94
113

15

1 10K_0402_5%

+3VALW_EC

PWM Output

X1
32.768KHZ_12.5PF_Q13MC14610002

2

R601

R602

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSI[0..7]

15 PM_SLP_S3#
15 PM_SLP_S5#
18
EC_SMI#
37 WWAN_DET#_EC
37 MINI1_LED#
45 USB_CHARGE_2A#
22,55 GPU_VID0
45 USB_CHARGE_100mA
45 FAN_SPEED1
46 PCH_PWR_EN
37 E51TXD_P80DATA
37 E51RXD_P80CLK
40 ON/OFF
T91@
41 NUM_LED#

B

1

AD_PID0
C843
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

2

2

1

R770
8.2K_0402_5%

Rb

2

C655
0.1U_0402_16V4Z

2

R621
33K_0402_5%

1

1

AD_BID0

A

R769
100K_0402_5%

Ra

1

1

D

BKOFF#

@

2

5

2 10K_0402_5%

17 CLK_PCI_LPC

GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3VS

Rb

+3VS
R596

P

1

R620
100K_0402_5%

4.7K_0402_5%

NC

KSO2

Reserve for EMI please close to U24

Ra

2

G

KSO1

2 47K_0402_5%

C649
22P_0402_50V8J
R608
33_0402_5%
@
@
2
1
1
2

A

1

1

2 47K_0402_5%

1

+3VALW_EC

R595

3

1

R599

C651
15P_0402_50V8J

TP_DATA

1

R598

EC_XCLK1

4.7K_0402_5%

2

10/1 ENE Recommand

C

2

EC_MUTE#

1

18
GATEA20
18 EC_KBRST#
13
SERIRQ
13 LPC_FRAME#
13
LPC_AD3
13
LPC_AD2
13
LPC_AD1
13
LPC_AD0

+3VALW_EC

R600

1

EC_RST#

0.1U_0402_16V4Z

1

R594

2

1 47K_0402_5%

C646 2

TP_CLK

C643
0.1U_0402_16V4Z

1

R603 2

+3VALW_EC

ECAGND 2

1
VCC
VCC
VCC
VCC
VCC
VCC

67

9
22
33
96
111
125

2

2
1

1

1
2

2

1
U24

C642
1000P_0402_50V7K

C641
1000P_0402_50V7K

C640
0.1U_0402_16V4Z

CLK_PCI_LPC

C639
0.1U_0402_16V4Z

R597
33_0402_5%
@
2
1

C638
0.1U_0402_16V4Z

C644
22P_0402_50V8J
@
2
1

C637
0.1U_0402_16V4Z

D

L32
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

+3VALW_EC

AVCC

R593
0_0805_5%
2
1

1

2

+3VALW

1

C703
0.1U_0402_16V4Z

2

2

1

5,17,35,38,44 PLT_RST#

R623
0_0805_5%
@
1
2

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

39

of

57

1

2

3

4

5

6

7

8

INT_KBD Conn.

27
28

G1
G2

R656
0_0402_5%
@
1
2

D18
49,50 MAINPWON
49

3V5V EN

3
1

BI_EC

50

BI

BI
SW7

S

1

BI_GATE 2

2

2

1

BI_RESET

R654
0_0402_5%
1
2

G
D

BAV70W_SOT323-3
BI_GATE

R646
10K_0402_5%

D

9

3

6

SW8
MSS6-Q-T-R_6P
@
6

2

2

5

5

1

1

4

4

A

Test Only
BI_RESET

Q38
2N7002E_SOT23-3

2
G

3

8

SKPMAME010_2P

Q35
AO3413L_SOT23-3

R653
0_0402_5%
@
2 BI_R

BI

G

39

G

R648
1K_0402_5%
1
2

3

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2

C677
C675
C673
C669
C667
C665
C663
C659
C684
C680
C674
C672
C668
C666
C664
C662
C657
C658
C670
C676
C678
C682
C671
C679
C681
C683

1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

3

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

10

R691
510K_0402_5%
2
1

+RTCVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

G

KSO[0..17] 39,41

JKB1
A

1

(Left)

D-Door Battery Power
Down Button

Reset Button

39,41

G

KSI[0..7]

KSO[0..17]

7

KSI[0..7]

JM

S

Need Check Gate Threshold Voltage
Battery BI Low voltage is 0.8V
JDOOR1
BI_R

1
2

1 GND
2 GND

3
4

ACES_85205-0200N
CONN@

ACES_85201-26051
CONN@
B

B

(Right)

To TP/B Conn.

Power Button

1

+5VS

+3VALW_EC

ON/OFF switch

2

JM

C656
0.1U_0402_16V4Z

+5VS
2

JTP1

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

R622
100K_0402_5%
1

1

D17

@

ON/OFFBTN#

41 ON/OFFBTN#

2
1

51ON#

3

ON/OFF

39

51ON#

47

C

BAV70W_SOT323-3

1

1

@

2 0_0402_5%
39

1

@

2 0_0402_5%

D

S

2
G

R624
10K_0402_5%

Q34
2N7002E_SOT23-3

1

R645

EC_ON

EC_ON

2

Bottom Side

1

TOP Side
R644

3

2

@

D15
PJDLC05C_SOT23-3

2

1

TP_CLK 39
TP_DATA 39
100P_0402_50V8J
C661

E-T_6916-Q06N-00R
CONN@

C

6
5
4
3
2
1

100P_0402_50V8J
C660

6
5
4
3
2
1

2

G2
G1

3

8
7

Test Only

LEFT_BTN#

LEFT_BTN#

SW2
SMT1-05-A_4P
1

4

2

RIGHT_BTN#

3

SW3
SMT1-05-A_4P
1

4

2
5
6

5
6

2

3

RIGHT_BTN#

3

D16
PJDLC05C_SOT23-3

100g for Press

100g for Press

D

1

D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

2

3

4

5

6

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011
7

Sheet

40
8

of

57

A

B

C

D

Battery LED

E

Battery Indicator BTN

1

1

Side View LED with Blue/Amber/Red Color

1

3

1
R625

B

3
BATT_AMB_LED# 39

2 BATT_BLUE_LED#
100_0402_5%

KSO0

1

SW6
MPTCFG-T-Q-T-R_2P
KSI2

2

KSI2

39,40

BATT_BLUE_LED# 39
6

A

1

R626
300_0402_5%
2 BATT_AMB_LED#

2

5

LED1

4

+3VALW

HT-210UD5-NB5_AMBER-BLUE

2
2

1

BATT_RED_LED# 39

HT-110USD5_RED

JPWR1
1
2
3
4

1
2
3
4

GND
GND

5
6

1

+3VALW
R627
100_0402_5%
1
2
R629
560_0402_5%
1
2

3

LED3
2

B

4

D

G

A

1

PWR_LED#

3

PWR_SUSP_LED#

2

+3VS

Q36B
DMN66D0LDW-7_SOT363-6
S

HDD LED

+3VS

2

1

4

U39
2

B
A

3

Y

JLED1

1

5

B

MEDIA_LED#

P

LED4

FUN Board
@
R632
10K_0402_5%

G

R740
150_0402_1%
1
2

HT-191NB5_BLUE

1
2
3
4
5
6
7
8
GND
GND

5IN1_LED# 38

1

PCH_SATALED# 13

MC74VHC1G08DFT2G_SC70-5

3G/Wireless LED
R741
100_0402_5%
2
R742
560_0402_5%
1
2
1

3

1
2
3
4
5
6
7
8
9
10

3G/WLAN

BlueTooth

PWR_SAVE_LED# 39
NUM_LED# 39
CAPS_LED# 39
KSO0
39,40
KSI1
39,40

LED5
2

B

1

3G_LED#

4

A

3

WLAN_LED#

3G_LED# 39

3

WLAN_LED# 39

HT-297UD5-CB5_AMBER-BLUE

Battery

+3VS

PWR_SAVE_LED#
NUM_LED#
CAPS_LED#
KSO0
KSI1

ACES_50504-0080N-001
CONN@

+3VS

Power/SUS

ON/OFFBTN# 40

HT-297UD5-CB5_AMBER-BLUE

+3VS

4

+3VALW

PWR_LED#
ON/OFFBTN#

ACES_88514-0401
CONN@

1

R630
100K_0402_5%

4

5
2

BATT_RED_LED#

Power LED

PWR_LED#

PWR_LED

1

R

PWR/B
Q36A
DMN66D0LDW-7_SOT363-6

S

2

39

LED2
2

D

G

R628
100K_0402_5%

R739
100_0402_5%
2

2

39 PWR_SUSP_LED

1

3

6

PWR_SUSP_LED#

KSO0
KSI1

PWR SAVE BTN#

KSI2

Battery ID BTN#

ACIN

4

LED Status
ON

SUS

Blue Amber

Full Charge

3G

WLAN

Blue Amber

Blue Amber

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
E

41

of

57

5

4

3

2

1

+5VAMP

4

1
2
C687
G9191-475T1U_SOT23-5 0.01U_0402_16V7K
@
@
SHDN

BYP

1

2

(output = 300 mA)

1

2

4

+3VS_CODEC

GND

1

2

Q66B
DMN66D0LDW-7_SOT363-6
5

6 1

R790
100K_0402_5%
S
Q67
AO3413L_SOT23-3

G

SPDIF_PLUG#

2

Q66A
DMN66D0LDW-7_SOT363-6

2

D

D

1

+VDDA

4.75V

3

2
2

OUT

5

1

2
3

40mil

IN

3

1

C686
0.1U_0402_16V4Z
0.1U_0402_16V4Z

HP_PLUG#
R789
100K_0402_5%

1

D

C685

2

2

@

1

L35 1
2
FBMA-L11-201209-221LMA30T_0805

U28
1

0.1U_0402_16V4Z

60mil

L34 1
2
FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z
C690

+5VAMP
+5VS

+5VAMP

2
0_0805_5%

C688

1
R633

10U_0805_10V4Z
C689

SM010014520 3000ma 220ohm@100mhz DCR 0.04

+5VSPDIF
SPDIF_PLUG# 37

PORTD_L

28

PORTD_R

33

PORTE_L

34

PORTE_R

41

D34

1
2

MONO_IN

37

MIC1_L

37

MIC1_R

MIC1_R

1

D35
HDA_SPKR

2

MIC1_L

1

2
4.7U_0603_6.3V6K
2
4.7U_0603_6.3V6K

MIC1_VREFO

R731
10K_0402_5%

RB751V-40_SOD323-2

1
C704
1
C705

FLY_P

23
2
1U_0603_10V6K

1
C702

C801
0.1U_0402_16V4Z

1

RB751V-40_SOD323-2

PORTF_R

22

35

PORTC_L

36

PORTC_R

37

C_BIAS

10U_0805_10V4Z
C691

0.1U_0402_16V4Z

2

C699
10U_0805_10V4Z

C698
10U_0805_10V4Z

2

1

20

15

18

31

29

21

9

4

FLY_N

2

1

Please bypass caps very close to device.

SPK_OUT_L+

14

SPK_OUT_L-

16

SPK_OUT_R+

19

SPK_OUT_R-

17

PORTB_L

39

PORTF_L

42

2

1

C

CLASSDREF

27

RPWR5.0

PORTA_R

LPWR5.0

PORTA_L

26

AVDD_5V

25

AVDD_HP

HP_RIGHT

VDD_IO

HP_RIGHT

DVDD_3.3

HP_LEFT

37

VAUX_3.3

37

HP_LEFT

1

C697
0.1U_0402_16V4Z

2

U29

13

Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)

+VDDA_R

1

C696
0.1U_0402_16V4Z

1

C

2

2

1
1

2

BEEP#

1

+3VS_CODEC

40mils

2

39

1

2

C695
0.1U_0402_16V4Z

2
0_0805_5%

C692

2
R635
0_1206_5%

0.1U_0402_16V4Z

1
R834

C700

40mils

2

+VDDA

+3VS_CODEC

10U_0805_10V4Z
C701

+3VS

1

0.1U_0402_16V4Z

2

C693
1

Modify R02
Add R834 between +3VS and +3VS_Codec.
change power from +3VS to +3VS_CODEC.

1U_0603_10V6K
C694

+3VS_CODEC

PORTB_R

40

B_BIAS

38

SDATA_IN

8

SDATA_OUT

6

SYNC

HDA_SDIN0_AUDIO

RESET#

11
7

1
1
1

SPKL+_L

2 C796
1000P_0402_50V7K
2 C797
1000P_0402_50V7K
2 C798
1000P_0402_50V7K
2 C799
1000P_0402_50V7K

2 33_0402_5%

HDA_RST_AUDIO#
2 22P_0402_50V8J
HDA_BITCLK_AUDIO_R
2 22P_0402_50V8J

1
@ C802
1
@ C803

SPKL-_L

43
43

Internal SPEAKER

SPKR+_L

43

SPKR-_L

43

HDA_SDIN0 13
HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO

13
13

HDA_RST_AUDIO# 13
R642 2

1 0_0402_5%

HDA_BITCLK_AUDIO

13
B

For EMI

2

B

1 R730

1

HDA_SDOUT_AUDIO
2 22P_0402_50V8J
HDA_SYNC_AUDIO

1
@ C800

10

BIT_CLK

40mils

SPKL+ L41 1
2
FBMA-L11-201209-221LMA30T_0805
SPKL- L42 1
2
FBMA-L11-201209-221LMA30T_0805
SPKR+ L43 1
2
FBMA-L11-201209-221LMA30T_0805
SPKR- L44 1
2
FBMA-L11-201209-221LMA30T_0805

5.1K_0402_1%
39.2K_0402_1%
10K_0402_1%
5.1K_0402_1%
2 R651

SPDIF_OUT

GPIO1/SPK_MUTE#
GPIO2/SPDIF2

46
45

DMIC_CLK 43
DMIC_DATA

1

R733
@

DMIC_DATA 43

FILT_1.8V

FILT_1.65V

2 EC_MUTE#

0_0402_5%

GPIO0/EAPD#

48

SPDIFO

FILT_1.8

5

FILT_1.8V

24

AVEE

FILT_1.65

32

FILT_1.65V

EP_GND

AVDD_3.3

30

LDO_OUT_3.3V

49

2
R647

R652
@

1

2

1

2

2

Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C716
1

LDO_OUT_3.3V

AVDD_3.3 pin is output of
internal LDO. Do NOT connect
to external supply.

C808
0.1U_0402_16V4Z
@ 1
2

4

C712

1
1U_0402_6.3V6K

CX20584-21Z_QFN48_7X7

C806
0.1U_0402_16V4Z
@ 1
2

5

2

2

1
2

C714
0.1U_0402_16V4Z

47

SENSE A
SENSE B

1
90.9_0402_1%

0.1U_0402_16V4Z

A

1
2

C804
0.1U_0402_16V4Z
@ 1
2

C713
10U_0805_10V4Z

AVEE

EAPD active low
0=power down ex AMP
1=power up ex AMP

44
43

3

10U_0805_10V4Z

1

SENSE_A
SENSE_B

2

DMIC_1/2

C711
2
1

0_0402_5%

EAPD
37

2
1
1
2

DMIC_CLK0

0.1U_0402_16V4Z

1
2
2
1

EXT_MUTE#

C715
1

39

R472
R650
R649
R488

PCBEEP

12

0.1U_0402_16V4Z

+3VS

13

10U_0805_10V4Z
C710

HP_PLUG#
37 MIC_PLUG#

1

1

+3VS

R732 2
0_0402_5%

2

EC_MUTE#

EC_MUTE#

1

10K_0402_5%
C709

MONO_IN
39

DMIC_3/4

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

42

of

57

A

B

C

D

E

1

1

2

2

Int. Speaker Conn.
3

3

Digital MIC CONN

JSPK1
42
42

+3VS

SPKL+_L
SPKL-_L

SPKL+_LR665 1
SPKL-_L R667 1

2 0_0603_5%
2 0_0603_5%

SPK_L+
SPK_L-

For EMI

@
2

1

2

@

1

1
2
3
4

G1
G2

3

1
2
3
4

2

2 BLM18AG121SN1D_2P +3VS_DMIC
DMIC_CLK_R
2 FBMA-L10-160808-301LMT_2P
DMIC_DATA_R
2 FBMA-L10-160808-301LMT_2P

L36 1

3

R666 1
R668 1

2

DMIC_CLK
DMIC_DATA

5
6

1 GND
2 GND

3
4

ACES_85205-0200N
CONN@

JDMIC1
42
42

1
2

D25
PJDLC05C_SOT23-3

ACES_88266-04001
CONN@

1

C719
R671
1000P_0402_50V7K10K_0402_5%
D24
PJDLC05C_SOT23-3
@

JSPK2
SPKR+_L R669 1
SPKR-_L R670 1

2 0_0603_5%
2 0_0603_5%

SPK_R+
SPK_R3

SPKR+_L
SPKR-_L

2

1

42
42

1
2

1 GND
2 GND

3
4

ACES_85205-0200N
CONN@
D26
PJDLC05C_SOT23-3
4

1

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
E

43

of

57

4

3

+3V_USB3

R715 1

+3V_USB3

2 10K_0402_5%

1
1

G

3

1

S

D

14 USB30_CLKREQ#

2

Q63
2N7002E_SOT23-3

R717
10K_0402_5%

CLKREQ_USB3

USB3_XT1
USB3_XT2
B

J2
J1
H1
P4

AUXDET
PSEL
SMI
SMIB

M2
N2
N1
M1

C14

GND

N14
M14

1
2

1
2

1

1

2

2

2

2

2

1

P13
U2AVDD10

D7
U3AVDO33

H11
K11
K12
L8
VDD10
VDD10
VDD10
VDD10

H3
H4
L5
VDD10
VDD10
VDD10

E3
E4

E11
E12
VDD10
VDD10

VDD10
VDD10

C8
C9
D8
D9
VDD10
VDD10
VDD10
VDD10

C4
C5
C6
C7
D5
VDD10
VDD10
VDD10
VDD10
VDD10

N4
N5
N6
P3

VDD33
VDD33
VDD33
VDD33

L9
L10

L13
L14
VDD33
VDD33

VDD33
VDD33

F3
G3
G4

2

2
U2DP2
U3RXDP2

P8
B8

U3RXDN2

A8

+3V_USB3
C

OCI2B
OCI1B

G14 OCI2B
H13 OCI1B

R711 1
R712 1

H14
J14

U3TXDP1

B10

U3TXDN1
U2DM1

A10 U3TX_C_DN1 1
N10 U2DN1_L

U2DP1
U3RXDP1

P10
B12

U2DP1_L
U3RXDP1_L

U3RXDN1

A12

U3RXDN1_L

RREF
GND

P12
N12

GND

N11

GND

D6

As short as possible

XT1
XT2

2 10K_0402_5%
2 10K_0402_5%
OCI1B

PPON2
PPON1

+3V_USB3

U3TX_C_DP1 1

45

C786
0.1U_0402_16V7K
U3TXDP1_L
2
U3TXDN1_L
2
C785 0.1U_0402_16V7K

U3TXDP1_L 45
U3TXDN1_L 45
U2DN1_L 45
U2DP1_L 45

U3RXDP1_L 45
U3RXDN1_L 45

B

1

+3V_USB3

2

R727
100_0402_5%

2

1
2

C793
12P_0402_50V8J

Pin compare table for support USB remote wakeup or not

Support USB
remote
wakeup
Not support USB
remote wakeup

AUXDET(Pin J2)

CSEL(Pin P6)

CLK

pull high
10k to VDD33

Tied to GND

Must use 24MHz crystal: mount
Y1,R19,C40,C41

pull high
to VDD33

Can use either 48MHz or 24MHz When
use 48MHz clock: mount R22,R25

Tied to GND
5

SMIB

18

SMI

Q69B
DMN66D0LDW-7_SOT363-6
5

R734
10K_0402_5%
@
1
2

+3V_USB3

SMI#

1

6
Q69A
DMN66D0LDW-7_SOT363-6

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1
2

C792
12P_0402_50V8J
A

Place as close as
possibile to
U3.N14 and U3.M14

C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

Y5
1

24MHZ_12PF_X5H024000DC1H

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6

2

USB3_XT1
USB3_XT2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

3

2

MX25L5121EMC-20G_SO8

A1
A2
A3
A4
A5
A7
A9
A11
A13
A14
B3
B4
B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11

CSEL

4

2
SPI_CS_USB#
USB_SI_SPI_SO

1
2
3
4

CS#
SO
WP#
GND

1

VCC
NC
SCLK
SI

@

1

1

1

8
7
SPI_CLK_USB
6
USB_SO_SPI_SI 5

R720
47K_0402_5%

2

1

R719
10K_0402_5%

U38

R725
0_0402_5%

2

C790
0.1U_0402_16V7K

P6

R723
0_0402_5%

R721
10K_0402_5%

2

2

+3V_USB3

1

+3V_USB3

1

2

A6
N8

Can be attach to EC, either.

SPISCK
SPISCB
SPISI
SPISO

GND
GND
GND

2

2

B6

PCI Express/ExpressCard select signal
1:others
0:Express Card or Mini card
PONRSTB

K13
K14
J13

1

2

U3TXDP2
U3TXDN2
U2DM2

2

2
+3VS

PERSTB
PEWAKEB
PECREQB

P5
SPI_CLK_USB
SPI_CS_USB#
USB_SO_SPI_SI
USB_SI_SPI_SO

C788
1U_0603_10V6K

1
2
D32 1 2
1SS355_SOD323-2
+3V_USB3

H2
K1
K2

C783
10U_0805_6.3V6M

R718
1.6K_0402_1%

+3V_USB3



2

+3V_USB3

R713 1
R709 1
R714 1
SMI R797 1
SMI# R798 1
@

2 0_0402_5%
2 0_0402_5%
CLKREQ_USB3
2 10K_0402_1%
@
2 100_0402_1%
2 10K_0402_5%
SMI_R
2 0_0402_5%
SMIB_R
2 0_0402_5%

VDD33
VDD33
VDD33

D10
F13
F14
VDD33
VDD33
VDD33
R708 1
R710 1

5,17,35,38,39 PLT_RST#
15,35,37 PCH_PCIE_WAKE#

2

2

+3V_USB3
+3VA
L40
BLM18AG601SN1D_2P
1
2

1

C

1

1

1

1

1

1

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1

GND

1
2

1
2

1

2

PERXP
PERXN

0.1U_0402_16V7K

F2
F1

14 PCIE_PTX_C_DRX_P4
14 PCIE_PTX_C_DRX_N4

0.1U_0402_16V7K

PETXP
PETXN

C772

+3VA

PECLKP
PECLKN

PCIE_PRX_C_DTX_P4 D2
PCIE_PRX_C_DTX_N4 D1

C771

0.01U_0402_16V7K

14 PCIE_PRX_DTX_P4
14 PCIE_PRX_DTX_N4

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

0.01U_0402_16V7K

0.01U_0402_16V7K

B2
B1

14 CLK_PCIE_USB30
14 CLK_PCIE_USB30#
C787 1
C784 1

0.1U_0402_16V7K

0.01U_0402_16V7K

RT9701-PB_SOT23-5

C770

0.01U_0402_16V7K

GND

1
5

C777

0.01U_0402_16V7K

VIN
VOUT
VIN/CE VOUT

2

C769

0.01U_0402_16V7K

3
4

C768

0.01U_0402_16V7K

SYSON

C767

0.01U_0402_16V7K

+1.05VR

U35
39,46,51 SYSON

D

7K for customer request, can use other kind
of capacitor, like Y5V.

R707
0_0805_5%
1
2

+3V_USB3

U34

C762

C766

C765

C764

+1.05V_USB3

0.01U_0402_16V7K

+3V_USB3

C776

+3VALW

@
0.01U_0402_16V7K

+3VALW to +3V Transfer

C773

R706
32.4K_0402_1%

@

+1.05VR

0.1U_0402_16V7K

APL5930KAI-TRG_SO8
Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025

R705
1
2
10K_0402_1%

C763
8P_0402_50V8D

2

C761
0.01U_0402_16V7K

FB

+3VA

C779
0.1U_0402_16V7K

EN
POK

3
4

C778
8P_0402_50V8D

SYSON
8
7
2
1
R704 5.1K_0402_1%

VOUT
VOUT

C760
0.01U_0402_16V7K

+5VALW

+3VA

VCNTL
VIN
VIN

C774
0.1U_0402_16V7K

6
5
9

1

Close to U3.P13
C759

+1.5V

Close to U3.D7
+1.05V_USB3

U33

C782
10U_0603_6.3V6M

C758
10U_0603_6.3V6M

C757
1U_0603_10V6K

D

+5VALW

C775

+1.5V

1

+1.5V to +1.05V Transfer
+5VALW

2

1

5

P/N: SA000048H10
(S IC UPD720200AF1-DAP-A FBGA
176P USB3.0 )

4

UPD720200AF1-DAP-A_FBGA176


Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

A

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

44

of

57

+USB3_VCCA

2 0_0402_5%
@

2 0_0402_5%

3

4

U2DP1

1

U2DN1

+

C789
0.1U_0402_16V4Z

CEN
DM
DP
GND
GND

1
2
3
4
9

SW_U2DN1_L
SW_U2DP1_L

2

Auto detection charger identification active

CB=1

Connect DP/DM to TDP/TDM

1

2

D31
U2DP1

MAX14566EETA+_TDFN-EP8_2X2

+USB3_VCCA

CB=0

2

WCM2012F2S-900T04_0805

Oper Drain, Low Active, need PU

6

I/O4

I/O1

1

5

REF2 REF1

2

4

I/O3

3

I/O2

2

4

Modify R02

U2DN1

+USB3_VCCA

USB3.0 Connector

PJUSB208H_SOT23-6
JUSB2
1
2
3
4
5
6
7
8
9

U2DN1
U2DP1
U3RXDN1
U3RXDP1
U3TXDN1
U3TXDP1

L37

+USB3_VCCA

44

U3TXDP1_L

U3TXDP1_L 2

44

U3TXDN1_L

U3TXDN1_L 3

+5VALW
U37
1
2
3
4

9

2

VOUT
VOUT
VOUT
FLG

8
7
6
5

R724
10K_0402_5%
1
2 OCI1B

OCI1B

44

44

U3RXDP1_L

U3RXDP1_L 2

39 USB_CHARGE_100MA

R754 1
@
10K_0402_5%

2

U3TXDN1

44

U3RXDN1_L

U3RXDN1_L 3

OCTEK_USB-09EAEB
CONN@

VL
U40
5

VIN

4

ON

1

U3RXDP1

4

U3RXDN1

OCE2012120YZF_4P

VOUT

1

GND

2

OC

3

U3RXDN1

D30
1 1

109

U3RXDN1

U3RXDP1

2 2

98

U3RXDP1

U3TXDN1

4 4

77

U3TXDN1

U3TXDP1

5 5

66

U3TXDP1

3 3
8
YSCLAMP0524P_SLP2510P8-10-9
@

TPS22945DCKR_SC70-5
@

FAN1 Conn

H1
H_2P5

H2
H_3P0

H3
H_3P0

H4
H_3P0

H10
H_2P5

H11
H_3P0

H24
H_2P5

H25
H_3P0

H13
H_3P0

H12
H_3P0

H18
H_3P9

@

@
1

1

@

1

@

1

@

1

@

1

@

1

1

1

1

@

H17
H_4P2
@

H5
H_3P2
@

1

@

H16
H_4P2

1

H15
H_4P2

FD1

1
2

40mil
+VCC_FAN1

39 FAN_SPEED1
1

@

@

FD2

FD3

@

H21
H_3P5x4p5N

H22
H_3P5N

@
@

@

FD4

FAN_PWM

C725
1000P_0402_50V7K

4
3
2
1
ACES_88231-04001
CONN@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

@

1

4
3
2
1

FIDUCIAL_C40M80

@

1

GND2
GND1

@

1

6
5

1

JFAN1

R673
10K_0402_5%

39

@

H19
H_4P0

1

C724
1000P_0402_50V7K
1
2

+3VS

H14
H_4P2

1

C723
10U_0805_10V4Z
1
2

@

1

C721
10U_0805_10V4Z

2

1

2

2

+VCC_FAN1
1
0_0603_5%

D27
1SS355_SOD323-2
@
D28
BAS16_SOT23-3
@
1
2

1

+5VS

1

1

+5VS

2
R672

GND_Frame 1
2
R728 0_0603_5%
1
2
R729 0_0603_5%
1
2
C794
0.1U_0402_16V7K

AP2301MPG-13_MSOP8

+USB3_VCCA
C204
1U_0603_10V6K
@
2
1

4

GND
GND
GND
GND

L38

W=60mils

GND
VIN
VIN
EN

EPAD

R722 1
10K_0402_5%

U3TXDP1

For customer request
10
11
12
13

OCE2012120YZF_4P

C791
0.1U_0402_16V7K
1
2
39 USB_CHARGE_2A#

1

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

1

R735 1

1

R716 1

VL

CB
TDM
TDP
VCC

2

+USB3_VCCA

8
7
6
5

2

SW_U2DN1_L

1

39 USB_CHARGE_CB
44
U2DN1_L
44
U2DP1_L

L39

U36

1

3

U2DP1
U2DN1
1

SW_U2DP1_L

USB Host Charger
R726
10K_0402_5%
1
U2DN1_L
U2DP1_L

2 0_0402_5%
2 0_0402_5%

C781
10U_0805_6.3V6M

R736 1 @
R737 1 @

C780
150U_B2_6.3VM_R35M

SW_U2DP1_L
SW_U2DN1_L

2010/09/28

Deciphered Date

2011/09/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet

45

of

57

A

B

C

2
1
6

1

1

2

+5VALW
2

Q44A
DMN66D0LDW-7_SOT363-6

R681
100K_0402_5%

C736
0.1U_0603_25V7K
5,53

1

2

R678
100K_0402_5%

SUSP

SUSP

3

4

Q44B
DMN66D0LDW-7_SOT363-6

1

1

2

2

1

5

Q45A
DMN66D0LDW-7_SOT363-6

2

PCH_PWR_EN#

2

1 200K_0402_5% 3V_GATE

PCH_PWR_EN#

SYSON

39,44,51 SYSON

6 1

1

4

1

R680 2

SYSON#

SYSON#

R677
470_0603_5%

1

+VSB

3

2

10mil

20mil

2

SUSP

2

1

1

2
1
3
4

2

2
1

1

1
2

4
6

Q43B
DMN66D0LDW-7_SOT363-6

1
2
3

C734
1U_0603_10V6K

SUSP

5

C735
0.1U_0603_25V7K
Q43A
DMN66D0LDW-7_SOT363-6

8
7
6
5

37

40mil

C733
10U_0805_10V4Z

C731
1U_0603_10V6K

20mil

C732

5VS_GATE

+3VALW_PCH

2

2

JUMP_43X79
Q42
SI4178DY-T1-GE3_SO8

R676
470_0603_5%

10U_0805_10V4Z

10mil

2
1
R679
100K_0402_5%

+VSB

C730
10U_0805_10V4Z

C729
10U_0805_10V4Z

C728
10U_0805_10V4Z

1

R675
100K_0402_5%

@

1

1

J1
1

2

+3VALW

+5VS

1
2
3

+5VALW

Short J5 for PCH VCCSUS3.3

2

Q41
SI4178DY-T1-GE3_SO8
8
7
6
5

E

+3VALW TO +3VALW(PCH AUX Power)

+5VALW TO +5VS
+5VALW

D

+3VALW

+3VS

+1.05VS_VCCP to +1.05VSDGPU for GPU

Q45B
DMN66D0LDW-7_SOT363-6

5

37,39,52,53 SUSP#

2
S

S

2
1
1
1
2

2
1
6

1
2

1

2
14,17,25,55 VGA_ON

2 SYSON#
G
Q62
2N7002E_SOT23-3
@

1
1

Q57
2N7002E_SOT23-3
@

D

3

S

S

2
G

R703
100K_0402_5%
OPT@

Q58
2N7002E_SOT23-3
OPT@
4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2010/09/28

2011/09/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

4

2
2
6 1

1

1
2

1
2

1
2

VGA_ON#

2

2 SUSP
G
Q61
2N7002E_SOT23-3

2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
0.75VS speed up discharge
A

R698
100K_0402_5%
OPT@

D

3

2 SUSP
G
Q60
2N7002E_SOT23-3

C756
0.1U_0603_25V7K
OPT@

2 VGA_ON#
Q55A
DMN66D0LDW-7_SOT363-6
OPT@

1 1

D

3

S

3

2 SUSP
G
Q59
2N7002E_SOT23-3

D

2
G

R702
470_0603_5%
@

1 1

1 1

D

R693
470_0603_5%
OPT@

1

R701
470_0603_5%

Q55B
DMN66D0LDW-7_SOT363-6
OPT@
ACIN

1

2

2

2
R700
470_0603_5%

5

3

+1.5V

OPT@

+5VALW

4

+1.8VS

OPT@

1.5VSDGPU_GATE

@

1
S

1

1
2

10mil
2
1
R696
510K_0402_5%
OPT@

3

+VSB

2
1

D

3

4

2

1

OPT@

20mil

+0.75VS

R699
22_0603_5%

1
2
3

1

2

C755
10U_0805_10V4Z
OPT@

8
7
6
5
4

SUSP

2

2
1

1

C753
0.1U_0603_25V7K

3

+1.5VSDGPU
U32
AO4430L_SO8

VGA_ON#
+1.05VS_VCCP

Q50
2N7002E_SOT23-3

2
1

+1.5V
6

1
2

1
2

4
1
S

S

+1.5V to +1.5VSDGPU for GPU

Q56
2N7002E_SOT23-3
@

2
G

D

2
G

R689
100K_0402_5%
Q51
2N7002E_SOT23-3
@

2
1

D

3

1
2

1
2

1
2

1
2

3
4

ACIN

ACIN

S

PCH_PWR_EN#

20,35 PCH_PWR_EN#

39 PCH_PWR_EN

C752
1U_0603_10V6K

5

D

2
G

R697
510K_0402_5%

15,39,48

R694
510K_0402_5%

SUSP

Q53B
DMN66D0LDW-7_SOT363-6

@

VGA_ON#

Q49A
DMN66D0LDW-7_SOT363-6
OPT@

R690
470_0603_5%

Q53A
DMN66D0LDW-7_SOT363-6

1.5VS_GATE

C745
0.1U_0603_25V7K
OPT@

C754
10U_0805_10V4Z

20mil

10mil

C747
1U_0603_10V6K

2
1
R692
750K_0402_5%

+VSB

C746
10U_0805_10V4Z

C751
0.1U_0402_16V4Z

C750
0.1U_0402_16V4Z

C749
10U_0805_10V4Z

C748
10U_0805_10V4Z

3

1
2
3

1

ACIN

Q52
AO4430L_SO8
8
7
6
5

@

3

+1.5VS

4

DMN66D0LDW-7_SOT363-6
OPT@

+1.5V to +1.5VS

R686
100K_0402_5%

2

R688
510K_0402_5%

VGA_ON# 5
Q49B

+1.5V

1

10mil

+5VALW

R684
470_0603_5%
OPT@

1.05VSDGPU_GATE
3

4

+VSB

OPT@

3

R687
510K_0402_5%
2 OPT@ 1

20mil

5

Q48B
DMN66D0LDW-7_SOT363-6

4

SUSP

2

2

2

1

1

C744
0.1U_0603_25V7K

OPT@

2

OPT@

Q48A
DMN66D0LDW-7_SOT363-6

2

3

2

4A

1
2
3

2

1

6 1

1

1
2

4

1
2

SUSP

8
7
6
5

C741
10U_0805_10V4Z
OPT@

3VS_GATE

20mil

Q47
AO4430L_SO8

C743
1U_0603_10V6K

10mil

R682
10K_0402_5%

+1.05VSDGPU
R683
470_0603_5%

C742
10U_0805_10V4Z

R685
200K_0402_5%
2
1

+VSB

+1.05VS_VCCP
C740
1U_0603_10V6K

2

1
2
3

C739
10U_0805_10V4Z

C738
10U_0805_10V4Z

2

C737
10U_0805_10V4Z

1

1

Q46
SI4178DY-T1-GE3_SO8
8
7
6
5

C

D

Title

SCHEMATIC, MB LA-7231P
Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
E

46

of

57

4

2

PC4
1000P_0402_50V7K

@ PJ3
2

2

2

1

1

+0.75VS

JUMP_43X118

1
@ PC169
1000P_0402_50V7K

@ PJ4
1

1

+5VALW

+VCCSAP

2

+VCCSA

1

1

D

3

@ PC168
1000P_0402_50V7K

2

JUMP_43X118

1

JUMP_43X118

PJ25
@JUMP_43X39
1 1
2 2

VIN

PD9 @
PJSOT24CH_SOT23-3

@ PJ5

@ PC128
1000P_0402_50V7K

2

B

1
PR9

PR10
1K_1206_5%
1
2

2

2

C

1

@ PJ12
+1.05VS_VCCP

2
+GFX_COREP

1

JUMP_43X118
@ PC165
1000P_0402_50V7K

2

2

1

1
+VGFX_CORE

JUMP_43X118
@ PJ14
2
1 1
JUMP_43X118

B+

B

1
12

0_0402_5%
PR15
PD20
1 2

PQ4
PDTC115EU_SOT323-3
1

+5VALW

1

PR14
100K_0402_5%
1

ACOFF

+VSB

1

PR13
1K_1206_5%
1
2

ML1220T13RE

39

@ PJ10
JUMP_43X39
1
2 2

1

1

+RTCBATT

2

PR12
560_0603_5%
1
2

PR7
1K_1206_5%
1
2

PQ2
TP0610K-T1-E3_SOT23-3
3

100K_0402_5%

PR11
560_0603_5%
1
2

Pre_chg

LL4148_LL34-2
PD3
1

PR8
1

+
1

2

100K_0402_5%

PR6
1K_1206_5%
1
2

2

JUMP_43X118
@ PJ13
2 2
1 1

2

1

+3VLP

2

PBJ1 @
2

1

+VSBP

@ PC166
1000P_0402_50V7K

2
+1.05VS_VCCPP

VIN

-

+1.5V
1

1

2

2

2

JUMP_43X118

1
2
PR5
0_0402_5%
1

JUMP_43X118

@ PJ11
@ PC6
0.1U_0603_25V7K

@PC156
@
PC156
1000P_0402_50V7K

+CHGRTC

1

2

1
51ON#

2

@ PC144
@PC144
1000P_0402_50V7K

2

1
PR4
22K_0402_5%
1
2

+1.5VP

1

2

PR3
100K_0402_5%

C

3

+VGA_CORE

1

@ PJ9

VS

2

PC5
0.22U_0603_25V7K
2
1

N1

1

1

JUMP_43X118
@ PR2
68_1206_5%

@ PR1
68_1206_5%

2

JUMP_43X118
@ PJ7
2 2
1 1

1
@ PC167
1000P_0402_50V7K

2

2

+VGA_COREP

@ PJ8
2

PQ1
TP0610K-T1-E3_SOT23-3

@ PJ6
+1.8VS

1

1

2

@ PJ26
JUMP_43X39
1
2 2

1

BATT+

1

1

PD2
LL4148_LL34-2
2
1

2

JUMP_43X118

1

1

@ PD1
LL4148_LL34-2

2

2

2

+1.8VSP

2

2

2

+0.75VSP

JUMP_43X118

+5VALWP

D

40

+3VALW

2

@ PC120
1000P_0402_50V7K

1
2

1

PC3
100P_0402_50V8J

2

PC2
100P_0402_50V8J

@ PJ2
1

1

2

2

+3VALWP

1
2

2

PJP1

PC1
1000P_0402_50V7K

1

@ PJ1

2

1

1
2
3
4
5
6

1

1
2
3
4
GND
GND

2

VIN

PL1
SMB3025500YA_2P
1

ACES_50305-00441-001

3

2

5

2

2

3
PQ3
PDTC115EU_SOT323-3

3

3

BAS40CW_SOT323-3

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
1

47

of

57

A

B

C

D

1

D

3

for reverse input protection

S

PQ5
SI1304BDL-T1-E3_SC70-3

2
G

1

2

1

PR16
1M_0402_5%

1

2

PJ16 @

PR17
3M_0402_5%

1

1

2

2

1

JUMP_43X118

3
2
1

SRP

13

BQ24725_ACDRV

4

ACDRV

SRN

12

5

ACOK

BATDRV

11

1

PR20
0_0402_5%

2

1

PC26
0.01U_0402_50V7K

2

PC24
2200P_0402_50V7K

PC22
10U_0805_25V6K
2
1

PC21
10U_0805_25V6K
2
1

PD10
SX34 SMA
2
1

1
2

PC25
0.1U_0402_25V6
2
1

CSON1

CSOP1

1
2

PC23
0.1U_0402_25V6

1

PR29
4.7_1206_5%

2
1

@

@

3

10

+3VALW

1

PC29
0.01U_0402_25V7K

2

PR34
100K_0402_1%

1
2

2
PR32
316K_0402_1%

1

EC_SMB_DA1 39,50

PR72
0_0402_5%
1
2

ADP_I

4

39,50

to EC

@ PC177
0.1U_0402_25V6

2

PC31
100P_0402_50V8J

1

1

2

4

1

EC_SMB_CK1 39,50

2

PC30
0.1U_0402_25V6

2

1

2

Max.

ILIM and external DPM
3.97A

9

2
1

Vin Dectector
Typ
17.23V
17.63V

SDA

PD7
RB751V-40_SOD323-2

PR35
154K_0402_1%

PR33
255K_0402_1%
1
2

PR36
66.5K_0402_1%

VIN

Min.
H-->L
L--> H

8

1

15,39,46 ACIN

3

1

2
PR31
10K_0402_1%

6

Pre_chg

IOUT

2
PR30
10K_0402_1%

7

1

SRN 1
2 CSON1
PR67
6.8_0603_5%
BQ24725_BATDRV

ILIM

CMSRC

SCL

3

ACDET

+3VALW

BQ24725_CMSRC

3

5

PR66
10_0603_5%
SRP 1
2 CSOP1

BQ24725RGRR_VQFN20_3P5X3P5

2

@

2

14

4

PC27
680P_0402_50V7K

GND

DL_CHG

3
2
1

15

PL2
PR28
10UH_FDVE1040-H-100M=P3_6.5A_20% 0.01_1206_1%
BQ24725_LX
1
2 CHG
1
4
PQ10
SIS412DN-T1-GE3_POWERPAK8-5

2

17

18

16
LODRV

2
1
PC28
0.1U_0603_16V7K

ACP

2

BATT+

PC19
1
2

REGN

2

1
2
PQ9
SIS412DN-T1-GE3_POWERPAK8-5

PD6
RB751V-40_SOD323-2

BTST

ACN

HIDRV

PAD

1

19

VCC

21

PHASE

20

2
1
@ PC20
2.2U_0805_25V6K

PC14
0.01U_0402_50V7K

5
PR70
1_0603_5%
DH_CHG 1
2 DH_CHG-1
4

1U_0603_25V6K
PU1

2

PR21
4.12K_0603_1%

PR25
10_0603_5%

1
BQ24725_BST 2

DH_CHG

BQ24725_LX

1U_0603_25V6K

@

2

PR24
10_1206_1%

1
PC18
1
2

1
2
3

4

PC13
2200P_0402_50V7K

PC12
0.1U_0402_25V6
2
1

1

PC11
10U_0805_25V6K
2
1

2

1

PC10
10U_0805_25V6K

2

1

BQ24725_BATDRV 1

0.047U_0402_25V7K

2

BQ24725_ACP

1
2

PC17
0.1U_0603_25V7K

1 2

@

PC16

@ PR27
3.3_1210_5%

2

2

2
2

3
2

PR23
4.12K_0603_1%

1

PR22
4.12K_0603_1%
2
1

1
@ PR26
3.3_1210_5%

BQ24725_ACN

2

VIN

@

8
7
6
5

PD5
BAS40CW_SOT323-3

1

2

@

PC51
10U_0805_25V6K

1
VIN
PC9
0.1U_0402_25V6
1
2

PC173
10U_0805_25V6K

3

1

2

2

PQ8
AO4466L_SO8

1

8
7
6
5
4

1
2

1
2
3

PC15
0.1U_0402_25V6

2

@

PC7
0.1U_0402_25V6

1

PR19
0_0402_5%

1
2
3

4

PC8
2200P_0402_50V7K
2
1

8
7
6
5

B+

PR18
PL16
0.02_2512_1%
1UH_FDV0630-1R0M-P3_10.3A_20%
1
2
1
4
PC109
10U_0805_25V6K
2
1

P2
PQ7
AO4466L_SO8

1

P1
PQ6
AO4466L_SO8

PC119
10U_0805_25V6K

VIN

Compal Secret Data

Security Classification
Issued Date

2010/01/25

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Sheet

Friday, March 04, 2011
D

48

of

57

5

4

3

2

1

PC32
1U_0603_10V6K

2VREF_8205

1

5

PC39
2200P_0402_50V7K
2
1

3
2
1

PC48
1U_0603_10V6K
2
1

1

1
1

VL

2

1
2

2

SI7716ADN-T1-GE3_POWERPAK8-5

PQ15B
DMN66D0LDW-7_SOT363-6

2VREF_8205

+5VALWP

1
+

4
PQ14

RT8205_B+

PR46
4.7_1206_5%

2

RT8205EGQW_WQFN24_4X4

18

17

@ PR47
0_0402_5%
2
1

PL5
4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A
1
2

5

LG_5V

NC

19

VREG5

LGATE1

VIN

LGATE2

PC49
4.7U_0805_10V6K

S

G

PC40
0.1U_0603_25V7K
2
1

PC38
4.7U_0805_25V6-K
2
1

PC37
4.7U_0805_25V6-K
2
1

1

3

4

2
FB1

REF

FB2

TONSEL

LX_5V

Typ: 175mA

PC46
150U_D2E_6.3VM_R18

2

B

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

PR51
100K_0402_1%
2
1

1

PR50
0_0402_5%
2
1
PQ16
PDTC115EU_SOT323-3

PD4
PR53
LL4148_LL34-2
1M_0402_1%
2
1 1
2

+3.3VALWP
Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A
f=375KHz, L=4.7UH
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A
Vlimit=10*10^-6*110Kohm/10=0.11V
Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A
Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT-

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=8.44~11.57A (8.44>8.4 -> OK)

A

3

PC114
4.7U_0603_6.3V6K

2

1

2

2
1
PR54
402K_0402_1%

VS

UG_5V

20

2
1
PC50
0.1U_0603_25V7K

5

3
2

D

4

ENTRIP2

6

G

VL

PR52
316K_0402_1%
2
1

21

PHASE1

PR48
499K_0402_1%
1
2

RLZ5.1B_LL34

S

VIN

UGATE1

PHASE2

PC47
680P_0402_50V7K

2

VFB=2.0V

UGATE2

PQ12
SIS412DN-T1-GE3_POWERPAK8-5

3
2
1

1
2
3

1

ENTRIP1

A

PR44
PC43
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

B+

D

40,50 MAINPWON

22

13

PD8

B

PQ15A
DMN66D0LDW-7_SOT363-6

23

BOOT1

4

+

2

3V5V EN

PGOOD

16

40

12

50

BOOT2

GND

PQ13
SI7716ADN-T1-GE3_POWERPAK8-5

PC45
680P_0402_50V7K
2
1

PC44
330U_D2E_6.3VM_R25M

LG_3V

PR49
150K_0402_1%

1

5

PR45
4.7_1206_5%
2
1

+3VALWP

SPOK

C

4
24

VREG3

EN

1
2
3

8
PR43
2 1
2 BST_3V 9
2.2_0603_5%
PC42
UG_3V
10
0.1U_0603_25V7K
LX_3V
11

PR42
154K_0402_1%
2

VO1

SKIPSEL

PQ11
SIS412DN-T1-GE3_POWERPAK8-5
1

VO2

15

7

RT8205_B+

ENTRIP1

4

1

5

6

P PAD

2

25

ENTRIP2

1

PC41
4.7U_0805_10V6K

5

PC36
2200P_0402_50V7K
2
1

PC35
4.7U_0805_25V6-K
2
1

PU2

ENTRIP1

PR40
20K_0402_1%
1
2

PR41
110K_0402_1%
1
2

PL4
4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A
1
2

1

PR39
20K_0402_1%
1
2

ENTRIP2

PR38
30K_0402_1%
1
2

Typ: 175mA +3VLP
PC34
4.7U_0805_25V6-K
2
1

C

PC33
0.1U_0603_25V7K
2
1

B+

PL3
HCB4532KF-800T90_1812
1
2

PR37
13K_0402_1%
1
2

14

RT8205_B+

D

2

D

Compal Secret Data

Security Classification
2010/07/13

Issued Date

Deciphered Date

2011/07/13

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BL

Date:

5

4

3

2

Friday, March 04, 2011

Sheet
1

49

of

57

5

3

2

1

D

ACES_50299-01001-001
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1

2

EC_SMDA
EC_SMCA
TH
BI+

PR55
100_0402_1%

2

PJP2

PR56
100_0402_1%

EC_SMB_DA1 39,48

+3VLP

1

1

<40,41>
VMB

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C

1

D

4

ADP_I 39,48
PC52
0.1U_0603_25V7K

1

MAINPWON

D
PQ22
2N7002W-T/R7_SOT323-3

2
G

8

GND RHYST1

7

3

~OT1 TMSNS2

6

4

~OT2 RHYST2

5

3

1
2

2
2

1

+VSBP

PC56
0.1U_0603_25V7K

2

1

PC55
0.22U_0603_25V7K

2

1
PR65
100K_0402_1%
2

65W@ PR77
28.7K_0402_1%

PR78
10K_0402_1%
PH1
100K_0402_1%_NCP15WF104F03RC

For 90W adapter==>action 97W , Recovery 75W

1

2

90W@ PR77
16.2K_0402_1%

2

VL

3

90W@ PR74
8.87K_0402_1%

C

1

BATT_TEMP 39

40

PQ19
TP0610K-T1-E3_SOT23-3

PR68
22K_0402_1%
1
2

PR63 1
2
9.53K_0402_1%

G718TM1U_SOT23-8

For 65W adapter==>action 70W , Recovery 54W

B+

2

VCC TMSNS1

2

S
BI

2

1

1

2

5,39 H_PROCHOT#

2

PU3

@ PR61
100K_0402_1%

2

1

PR76
100K_0402_1%
PR62
1K_0402_1%

C

PR59
21K_0402_1%

+3VALW

1

PC54
0.01U_0402_25V7K

65W@ PR74
5.62K_0402_1%

1

+3VLP

1

+3VLP
1

PR60
6.49K_0402_1%
2
1

1
PC53
1000P_0402_50V7K

2

2

1

2

EC_SMB_CK1 39,48
PR57
1K_0402_5%

2

<40,41>
BATT+

1

PL6
SMB3025500YA_2P
1
2

+3VLP

PR69
100K_0402_1%

2

@ PC57
0.1U_0603_25V7K

+3VLP

1

1

PQ20
2N7002W-T/R7_SOT323-3

MAINPWON

40,49 MAINPWON

@ PU4
1

VCC TMSNS1

2

GND RHYST1

8
7

3

OT1 TMSNS2

6

OT2 RHYST2

5

2

1

@ PR79
100K_0402_1%

2

@ PR58
10K_0402_1%
2

@ PR73
10K_0402_1%

4

1

@ PR64
47K_0402_1%

1

S

2
G

1

1

D

2

2

1

SPOK

PC58
1U_0402_6.3V6K

49

PR71
1K_0402_5%
1
2

3

B

1

B

@ PH2
100K_0402_1%_NCP15WF104F03RC
2

G718TM1U_SOT23-8

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/25

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

Size Document Number
Custom

Rev
B

4019BL

Date:

Friday, March 04, 2011

Sheet
1

50

of

57

C

D

PL17
FBMA-L11-322513-151LMA50T_1210
1
2
PC121
0.1U_0402_25V6
2
1

3
2
1
V5DRV

10

1

PR85
4.7_1206_5%

+

2
DL_1.5V

PC65
330U_D2E_2.5VM

2

4

2

1

RT8209MGQW_WQFN14_3P5X3P5

1

9

PQ24
AO4456_SO8

+5VALW

PC66
4.7U_0805_10V6K

PC67
680P_0402_50V7K

2

DRVL

1

11

5
6
7
8

LX_1.5V

TRIP

3
2
1

15

14

DH_1.5V

12

+1.5VP

2

PC68
4.7U_0603_6.3V6K

PR88
10K_0402_1%
1
2

PR89
10K_0402_1%

2

2

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=19.53A, Imax=23.44A, Iocp=13.67A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A
=>1/2Delta I=2.315A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+2.315A=35.65A
Iocpmin=((15K*9uA)/(0.0056*1.3))+2.315A=23.06A
Iocp=23.06A~35.65A

1

 VFB=0.75V
V=0.75*(1+10K/10K)=1.5V
Fsw=298KHz
2

@

PL7
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

1

PGOOD

13

LL

2

VFB

6

VFB=0.75V

DRVH

1

5

BST_1.5V

VBST

V5FILT

PGND

4

8

VOUT

TP

1

TON

3

7

PR86
100_0603_5%
1
2

2

EN_PSV

PU5
@PC64
@
PC64
.1U_0402_16V7K

GND

1
2

1

@PR84
@
PR84
47K_0402_5%

+5VALW

@

B+

1

PR83
PC63
2.2_0603_5%
0.1U_0603_25V7K
2
1BST_1.5V-1 1
2

PR87
15K_0402_1%

39,44,46 SYSON

2

1

4

PC61
4.7U_0805_25V6-K
2
1

AO4406AL_SO8
PR81
267K_0402_1%
1
2

PR82
0_0402_5%
1
2

PC60
0.1U_0603_25V7K
2
1

PQ23

PC59
2200P_0402_50V7K
2
1

5
6
7
8

1.5_8209_B+

PC81
0.1U_0402_25V6
2
1

B

PC62
4.7U_0805_25V6-K
2
1

A

3

3

4

4

Compal Secret Data

Security Classification
Issued Date

2010/07/13

Deciphered Date

2011/07/13

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BL

Date:

A

B

C

Friday, March 04, 2011

Sheet
D

51

of

57

5

4

3

2

1

1.8VSP
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
Vout=0.6*(1+(20K/10K))=1.8V

1
2

2
1
PR93
10K_0402_1%
2

1
2

PC74
680P_0603_50V7K

1

2

@ PR94
1M_0402_5%

D

PC72
22U_0805_6.3VAM

1

1
PR91
20K_0402_1%

PC71
22U_0805_6.3VAM

+1.8VSP

PC70
68P_0402_50V8J
2
1

FB_1.8V
FB=0.6Volt

2

6

1

PG

11

FB

2

EN

3

PR90
4.7_1206_5%

5

LX

LX_1.8V

NC

SVIN

2

PR92
510K_0402_5%

1

1

2

37,39,46,53 SUSP#

EN_1.8V

PVIN

8

2

PC73
0.1U_0402_10V7K

D

9

NC

PC69
22U_0805_6.3VAM

2

1

JUMP_43X118

LX

1

1

TP

1

7

2

PL8
2.2UH 20% FDSD0630-H-2R2M=P3 8.3A
1
2

4

PU6
SY8033BDBC_DFN10_3X3
10 PVIN

@ PJ17
2

+5VALW

C

C

2

+3VS

PR105
0_0402_5%
1

1

2

PR104
1M_0402_5%

@

PC84
22U_0805_6.3VAM

PC83
22U_0805_6.3VAM
2
1

1
2

1
2

PR100
3.4K_0402_1%
2
1

PC82
22U_0805_6.3VAM
2
1

2

NC

NC

@

PR102
0_0402_5%
1
2

VSSSA_SENSE 9

1

TP

FB_VCCSAP
FB=0.6Volt

PR101
0_0402_5%

PC78
22U_0805_6.3VAM

6

+VCCSAP
2

FB

1

PG

3

PL9
2.2UH 20% FDSD0630-H-2R2M=P3 8.3A
1
2

@ PC80
0.1U_0402_10V7K

2

2

PR99
100K_0402_5%

B

LX

LX_VCCSAP

1

11

2

1

1

EN

PC79
0.1U_0402_10V7K

53 VCCPPWRGOOD

2

SVIN

7

8
EN_VCCSAP
5

PVIN

1

PC76
22U_0805_6.3VAM

2

1

9

LX

PC77
680P_0603_50V7K

1

2

VCCSA_SENSE

9

B

PR107
10_0402_5%

2

+5VALW

1

PU7
SY8033BDBC_DFN10_3X3
10 PVIN

4

PL19
FBMA-L11-322513-151LMA50T_1210
1
2

SA_PGOOD 39

PC75
68P_0402_50V8J
2
1

2

PR97
4.7_1206_5%

1

PR103
10K_0402_5%

1

1

+3VS

PR108
20K_0402_1%

PR109
10K_0402_5%

2

D

@ PR112
100K_0402_5%

1

@ PC85
4700P_0402_25V7K

PQ28
PMBT2222A_SOT23-3
2

2

2

3

PQ27
2N7002W-T/R7_SOT323-3

1

1

2
G
S

2

1

1

1

PR111
10K_0402_5%
2
1

2

2

1
PR95
10K_0402_1%

VCCSA_VID1

9

@ PR114
10K_0402_5%
2

3

PR113
100K_0402_5%

VID[0]
0
0
1
1

VID[1]
0
1
1
1

VCCSA Vout
0.9 V
0.8 V
0.75V
0.65V

Require on 2011/ 2012 Required
Yes/Yes
Yes/Yes
No/Yes
No/Yes

A

A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]
(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Compal Secret Data

Security Classification
Issued Date

2010/07/13

Deciphered Date

2011/07/13

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P
Document Number

Rev
B

4019BL
Sheet

Friday, March 04, 2011
1

52

of

57

5

4

3

2

PU8

3
4

VCNTL

6

GND

NC

5

VREF

NC

7

VOUT

NC

8

TP

9

VIN

+3VALW

1

2

2

D

PC87
1U_0603_10V6K

2

PR115
1K_0402_1%

1

PC86
4.7U_0805_6.3V6K

2

1

1

+1.5V

1

D

+0.75VSP
1

S

PR117
1K_0402_1%

PC90
10U_0603_6.3V6M

2

1
D

2

SUSP 2
G
PQ29
2N7002W-T/R7_SOT323-3

1

PQ30
2N7002W-T/R7_SOT323-3

3

S

2

PC89
1U_0402_6.3V6K

D

2
G
3

1

5,46 SUSP

1

PR116
100K_0402_1%
1
2

PC88
.1U_0402_16V7K
2
1

G2992F1U_SO8

@
1.05VS_51117_B+
PC94
4.7U_0805_25V6-K
2
1

PJ19

1

1

B+

C

1

4

+

@ PC98
680P_0402_50V7K

2

B

2

PR123
0_0402_5%

1

RT8209MGQW_WQFN14_3P5X3P5

8

7

1

1

DL_1.05VS_VCCP

2

PC100
4.7U_0603_6.3V6K

@ PR122
4.7_1206_5%

PQ32
AO4456_SO8

2

DRVL

9

+5VALW

2

10

+1.05VS_VCCPP

1

1 2

VFB=0.75V V5DRV

3
2
1

14

12
11

1

PGOOD

LX_1.05VS_VCCP

LL
TRIP

2

5
6
7
8

VFB

DH_1.05VS_VCCP

PC99
4.7U_0805_10V6K

PC97
330U_2.5V_M
PR145
0_0402_5%
2

VSSIO_SENSE 8

1

3
2
1

5

13

PL10
1UH_FDUE1040D-1R0M-P3_21.3A_20%

1

V5FILT

DRVH

2

VOUT

4

VBST

3

6

15

EN_PSV

TON

PR121
PC96
0_0603_5% 0.1U_0603_25V7K
BST_1.05VS_VCCP 1
2
1
2

PR125
15K_0402_1%

PR124
100_0603_5%
1
2

2

PGND

S

TP

1

PU9
PC95
0.1U_0603_25V7K

GND

1

D

2

1

@ PR120
47K_0402_5%

2
G
3

+5VALW

2

JUMP_43X118

1

4

PQ45
2N7002W-T/R7_SOT323-3
SUSP

PQ31
AO4406AL_SO8

PC93
4.7U_0805_25V6-K
2
1

PR119
680K_0402_5%
1
2

2

37,39,46,52 SUSP#

PR118
267K_0402_1%
1
2

PC92
0.1U_0603_25V7K
2
1

PC91
2200P_0402_50V7K
2
1

5
6
7
8

C

2

B

1

PR126
4.02K_0402_1%
1
2
PR129
10K_0402_1%
1
2

VCCPPWRGOOD

PR128
10_0402_5%
2
1

VCCIO_SENSE 8

+3VALW

2

2

52
PR127
10K_0402_1%

@ PR130
10K_0402_1%

A

1

 VFB=0.75V
V=0.75*(1+4.02K/10K)=1.052V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=12.866A, Imax=9A, Iocp=15.439A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.33A
=>1/2Delta I=1.665A
choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+1.665A=37.62A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=23.02A
Iocp=23.02A~37.62A

A

Compal Secret Data

Security Classification
2010/07/13

Issued Date

Deciphered Date

2011/07/13

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BL

Date:

5

4

3

2

Friday, March 04, 2011

Sheet
1

53

of

57

LGATEG

31
LGATE2

27

LGATE2

VCCP

26

2
PWM3

25

LGATE1

24

LGATE1

PHASE1

23

PHASE1

UGATE1

22

UGATE1

BOOT1

21

BOOT1

PC164
1U_0603_10V6K

2

1
GFX@ PC118
0.047U_0402_16V4Z

1

2

+5VS

PR160
0_0402_5%

1

GFX@ PR151
1.02K_0402_1%

ISNG

@ PR152
0_0402_5%

Connect to +5V can disable
GFX portion

C

1

VDD

VIN

2

20

PR162
2.2_0603_5%

1

3
2
1
3
2
1

2-ph: PR178=1.47K for ~70A OCP

2010/01/25

@ PJ15
JUMP_43X39
CPU_B+
1
2 2

PC151
PR183
680P_0603_50V7K 4.7_1206_5%

3

ISEN1

A

10K_0402_1%
1 PR184 2

PR187
10K_0402_1%
2
1ISEN2

1_0402_5%
VSUM- 1 PR186 2

Compal Electronics, Inc.
2009/04/28

Deciphered Date

Title

SCHEMATIC, MB LA-7231P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

3

2

PR185
3.65K_0402_1%
VSUM+ 1
2

Compal Secret Data

Security Classification
Issued Date

2

1

4

3
2
1

LGATE1

1

PR171
10K_0402_1%
2
1 ISEN1

PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1
+CPU_CORE

1

1

PC150
0.22U_0603_10V7K

PQ38
TPCA8057-H_PPAK56-8-5

8

1

PR182
2.2_0603_5%
BOOT1 2
1 2

+CPU_CORE

B

PHASE1

PR181
10_0402_1%

B+

2

PR169
3.65K_0402_1%
VSUM+ 1
2
PR168
10K_0402_1%
ISEN2
1
2
PR170
1_0402_5%
VSUM1
2

PC149
4.7U_0805_25V6-K
2
1

PC140
PR166
680P_0603_50V7K 4.7_1206_5%

2
1
@

3

PC148
4.7U_0805_25V6-K
2
1

1

4

PC147
4.7U_0805_25V6-K
2
1

2

PR227
0_0603_5%

PC176
4.7U_0805_25V6-K
2
1

1

PQ37
CSD17308Q3_SON8-5

5

PC146
.1U_0402_16V7K

2

1

VSUM-

UGATE1

VSSSENSE

2

4

PQ36
TPCA8057-H_PPAK56-8-5

PC132
0.22U_0603_10V7K
LGATE2
PR167
2.61K_0402_1%

3
2
1

1
PR174
11K_0402_1%
1
2

1

2

1

PC143
0.01U_0402_50V7K
8

VCCSENSE

+CPU_CORE

2

PC142
330P_0402_50V7K
2
1

PR179
10_0402_1%
1
2

@

PR165
2.2_0603_5%
BOOT2 2
1 2

+

2

PL13
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1

PH6
10K_0402_1%_ERTJ0EG103FA

2

@

PC139
0.033U_0402_16V7K
2
1

PC138
0.22U_0402_10V6K
2
1

2
1
2

@

PR178
1.47K_0402_1%
2
1

2

PR176
3.4K_0402_1%

+GFX_CORE
Iocp=40A, IccMAX=24A
Load line=3.9mohm
DCR=1.1mohm

PC126
4.7U_0805_25V6-K
2
1

4

PC125
4.7U_0805_25V6-K
2
1

2

2

PC124
4.7U_0805_25V6-K
2
1

@

UGATE21

VSUM+

1
1

A

PQ35
CSD17308Q3_SON8-5
PC175
4.7U_0805_25V6-K
2
1

1

5

1

1

PC131
1U_0603_10V6K

1

PC127
68U_25V_M_R0.44

2

2

ISEN3

1

2

PC145
330P_0402_50V7K
1

1

PR180
100_0402_1%
2

2

PL11
HCB4532KF-800T90_1812
1
2

CPU_B+

PR226
0_0603_5%

FB

1

PC123
0.22U_0603_25V7K

PR164
1_0603_5%

VSUM-

PR177
2K_0402_1%
2 1
2

+5VS

PHASE2

PC135
PR173
1000P_0402_50V7K 887_0402_1%

PC141
470P_0402_50V8J

5

PC172
0.1U_0402_25V6
2
1

2

1

GFX@ PC103
4.7U_0805_25V6-K
PC171
0.1U_0402_25V6
2
1

1
2

2
1

GFX@ PC117
.1U_0402_16V7K
1
2

CPU_B+

19

ISUMP

ISUMN

RTN

1

1
3
2
1

1
PHASE2

2

UGATE2

28

GFX@ PC111
330U_2.5V_M

2

GFX@ PR144 GFX@ PH4
7.5K_0402_1% 10K_0402_1%_ERTJ0EG103FA
1
2 1
2
GFX@ PC115
.1U_0402_16V7K
1
2
1
2
GFX@ PR147
11K_0402_1%
1
2

1

29

PHASE2

D

+
GFX@ PR142
1_0402_5%

2

PHASEG

32

LGATEG
UGATE2

2

1

UGATEG

33

PHASEG

BOOT2

+GFX_COREP

2

BOOTG

34
BOOTG

NTCG

ISUMNG

UGATEG

30

PC133
0.22U_0402_6.3V6K2
PC136
0.22U_0402_6.3V6K2

2
1
PC134
47P_0402_50V8J

1
PR175
267K_0402_1%
2
1 2

1

+CPU_CORE
Iocp=72A, IccMAX=53A
Load line=1.9mohm
DCR=1.1mohm

2

NTCG

35

18

12

17

11

ISEN1

VW

16

NTC

ISEN2

9
10

COMP

VR_HOT#

3
GFX@ PR141
3.65K_0402_1%

PR218
0_0603_5%

BOOT2

@

1

ISPG

ISNG

36

38
RTNG

ISUMPG

39

40

PAD
PGOOD

8

4

2

ISPG

37

LGATEG

1

BOOTG 2

+5VS

ISL95835HRTZ-T_TQFN40_5X5

FB

1
2

2

2-ph: PR172=20.5K Vboot=0V, Iccmax=54A
2-ph: PR172=169K Vboot=1.1V, Iccmax=54A

comp
PC137
680P_0402_50V7K

2

VR_ON

7

PC129
1000P_0402_50V7K

1
PR163
8.06K_0402_1%

PR172
20.5K_0402_1%
1
2

2

SCLK

6

PR133
27.4K_0402_1%

1
1
2
1
2

PR131
3.83K_0402_1%

PH3
470KB_0402_5%_ERTJ0EV474J

PC122
47P_0402_50V8J
2
1

1

GFX@ PR161
27.4K_0402_1%

2
2
1

NTC

5

15

VGATE

ALERT#

ISEN1

2

SDA

4

ISEN3/ FB2

PR155

0_0402_5%

3

14

1

VR_ON

PGOODG

13

39

VWG

2

ISEN2

SVID_ALERT#

SVID_SCLK

GFX@ PR158
3.83K_0402_1%

GFX@ PH5
470KB_0402_5%_ERTJ0EV474J

1

GFX@ PC108
0.22U_0603_10V7K
1 2
1

@

CPU_B+

GFX@ PL12
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1

PHASEG

1

1

GFX_CORE_PWRGD

8 VR_SVID_CLK

FBG

41
39

1

PC130
10P_0402_50V8J
2
1comp

8 VR_SVID_DAT

COMPG

2
2
2
1

1

2

PR148
130_0402_1%

8 VR_SVID_ALRT#

NTCG

B

PU10

GFX@ PR217
1.91K_0402_1%

VR_HOT#

C

2

+3VS

+1.05VS_VCCP

1
PR156
1.91K_0402_1%
1
2

2
1
15

4

GFX@ PR137
2.2_0603_5%

GFX@ PC106
1000P_0402_50V7K
2
1

+3VS

39

VSS_AXG_SENSE 9

GFX@ PC110
0.01U_0402_50V7K

1

@ PC170
.1U_0402_16V7K
PR149
54.9_0402_1%

2

GFX@ PR221
0_0603_5%

GFX@ PR143
10_0402_1%

2

GFX@ PR132
8.06K_0402_1%

@ PR159
499_0402_1%

UGATEG 1

VCC_AXG_SENSE 9

1

2

GFX@ PC104
330P_0402_50V7K

GFX@ PQ33
CSD17308Q3_SON8-5
2
1

2

GFX@ PQ34
TPCA8057-H_PPAK56-8-5

GFX@ PR135
422_0402_1%
2
1

2

GFX@ PR139
475K_0402_1%

1

3
2
1

2

+GFX_COREP

5

1

1

GFX@ PR134
10_0402_1%

5

GFX@ PC112
150P_0402_50V8J

2

2

@
PC107
330P_0402_50V7K
1
2

5

1

GFX@ PR140
2.55K_0402_1%
2
1

FB

1

@ PR153
1K_0402_1%

2
GFX@ PR136
294K_0402_1%
2
1

@ PC116
330P_0402_50V7K
1
2
2

D

GFX@ PC105
39P_0402_50V7K
2
1

GFX@ PC102
4.7U_0805_25V6-K

1

GFX@ PC101
4.7U_0805_25V6-K

2

@ PC174
4.7U_0805_25V6-K

3

PC113
PR138
680P_0603_50V7K 4.7_1206_5%

4

5

5

2

Rev
B

4019BL
Sheet

Friday, March 04, 2011
1

54

of

57

5

B+

4

VGA@ PL18
FBMA-L11-322513-151LMA50T_1210
1
2

3

2

1

B+_CORE

1

1

@ PR188
10K_0402_5%

5

2

VGA@ PC153
10U_1206_25V6M

2

1

+3VS
VGA@ PC152
10U_1206_25V6M

4

10

BST_VCORE

DRVH

9

DH_VCORE

3

EN

SW

8

SW_VCORE

4

VFB

V5IN

7

5

RF

DRVL

6

1

1

1

VGA@ PR195
0_0402_5%
VGA@ PC158
680P_0603_50V7K
PR198
GS@
2.26K_0402_1%

2

1 2

2

VGA@ PR196
10_0402_5%
2
1

C

GCORE_SEN

VGAVCC_SENSE 24

GV@ PR198
2.15K_0402_1%
1

TPCA8057-H Rds=2.6m/3.2m ohm

PR201
GS@
10.7K_0402_1%

1

2

+3VSDGPU
2

1

GV@ PR201
8.66K_0402_1%

VGA@ PR202
10K_0402_5%

2

1

VGA@ PR200
10K_0402_1%

2

VGA@ PC160
2200P_0402_25V7K

6

VGA@ PR203
10K_0402_5%
1
2

2
1

S
GV@ PR205
10K_0402_1%

1

2

VGA@ PC162
4700P_0402_25V7K

VGA@ PR210
10K_0402_5%

2

D

NVIDIA/N12P-GV1

G

PQ44B

GPU_VID2 22

S

@ PR224
10K_0402_5%

4

P0(Cold)

1

0

1

1.0V

P0(Hot)

1

1

0

0.975V(default)

3

1.025V
2

D
VGA@

1.0V

G

PQ43B

DMN66D0LDW-7_SOT363-6

VGA@ PR214
10K_0402_5%
5 2

1

1

0.860V

0.85V(default)

0

1

1

0.900V

----

GPU_VID0 22,39
GS@ PR215
10K_0402_5%

S

A

2

1

4

GV@ PR213
10K_0402_5%

4

1

2

VGA@

DMN66D0LDW-7_SOT363-6

2

NVIDIA/N12P-GS

1

GPU_VID0

GPU_VID1 22,39
@
PR212
10K_0402_5%

S

1

GPU_VID1

G
VGA@ PQ42B
DMN66D0LDW-7_SOT363-6
+3VSDGPU

1

3

GPU_VID2

VGA@ PR225
10K_0402_5%
5
2
1

5

1

VGA@ PR211
10K_0402_5%
2
1

3

@ PR209
10K_0402_5%

1

1

+3VSDGPU

1

6

1

1

S
+3VSDGPU

B

2

@ PR220
10K_0402_5%

2

2

2

1

S

G

VGA@ PC163
4700P_0402_25V7K

VGA@ PR208
10K_0402_5%
1
2

D

1

2

2

G

VGA@ PQ44A
DMN66D0LDW-7_SOT363-6

VGA@ PR207
10K_0402_5%
VGA@ PQ43A
DMN66D0LDW-7_SOT363-6

VGA@ PR223
VGA@PR223
10K_0402_5%

P8/P12

@ PR206
10K_0402_5%

2

2

2

2
6

VGA@ PR222
10K_0402_5%
1
2

D

D

A

VGA@ PC161
4700P_0402_25V7K
1

2

+3VSDGPU

VGA@ PR216
10K_0402_5%

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm.
Ipeak=41.02A, Imax=28.714A, Iocp=43A
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A
=>1/2Delta I=3.4A
choose Rcs=75K
Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A
Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A
Iocp=48.42A~75.52A

1

B

VFB=0.7V
V=0.7*(1+Rtop/Rbottom)
Fsw=350KHz

GS@
PR205
13.3K_0402_1%

+3VSDGPU

2

1

@ PR219
37.4K_0402_1%

G

VGA@ PQ42A
DMN66D0LDW-7_SOT363-6

1

1

D

Vtrip range ==> 0.2V ~ 3V

VGA@ PC157
330U_D2E_2.5VM

+

1

2

4

VGA@ PR193
4.7_1206_5%

2

3
2
1

VGA@ PC159
.1U_0402_16V7K

4

VGA@ PQ41
TPCA8057-H_PPAK56-8-5

1

Switch freq. (RF pin setting)
47K ==>450KHz
100K ==>390KHz
200K ==>350KHz (Currently setting)
470K ==>300KHz

1
2

C

ESR=10mohm
VGA@ PC155
1U_0603_6.3V6M

VFB=0.6V

1

VGA@ PR194
10K_0402_1%
1
2

+VGA_COREP

1

DL_VCORE

11

TP

5

VGA@ PR191
200K_0402_1%

DL_VCORE

VGA_ON

4

+5VALW

RT8237_SON10_3X3

25,46 VGA_ON

VGA@ PL15
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
3
2

3
2
1

2

VBST

TRIP

VGA@ PQ40
TPCA8057-H_PPAK56-8-5

2

1
@ PR192
10K_0402_5%

PGOOD

2

5

+3VS

1

VGA@ PC154
0.1U_0603_25V7K
1
2

2

VGA@ PR190
75K_0402_1%
1
2

VGA@ PR189
2.2_0603_5%
1
2

VGA@

3
2
1

PU11

VGA@ PQ39
CSD17308Q3_SON8-5

D

2

D

SJM only ==> VPS

Issued Date

AP

Compal Secret Data

Security Classification
2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc.
SCHEMATIC, MB LA-7231P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BL

Date:

5

4

3

2

Friday, March 04, 2011

Sheet
1

55

of

57

5

4

3

2

Version change list (P.I.R. List)
Item

D

Fixed Issue

Reason for change

Rev.

PG#

1

HW/Edward request

Meet Turn off sequence

53

2

HW/Edward request

Meet Turn on sequence

53

3

HW/Edward request

Meet new VGA table

55

4

Battery Turn on time too long

Change enable 3/5V path

5

HW/Edward request

For USB 3.0 charger function

47

6

HW/Edward request

Don't need VGA_PW_OK net

55

Modify List

1

Page 1 of 2
for PWR

Date

Phase

2010
11/24

DVT

2010
11/27

DVT

2010
12/03

DVT

2010
12/04

DVT

Add PJ26

2010
12/04

DVT

Delete net

2010
12/04

DVT

Add PQ45
Change PR119 to 680Kȍ, PC95 to 0.1uF

Change PR201, PR205, PR219

C

D

C

7

HW/Edward request

Tune Power sequence

52

Change PR92 from 100K to 510K
Delete PR94

2010
12/08

DVT

8

HW/Edward request

Tune Power sequence

53

Change PR116 from 24.9K to 100K

2010
12/09

DVT

9

Costdown

54

Change PC97, PC111 to OS-CON cap.

2011
01/06

PVT

10

ISN test fail

ISN solution

49

Change PL16 to 1uH
Add PC109, PC119

2011
01/07

PVT

11

Trigger ACOC

Prevent to trigger phase to gnd threshold
Reserve RC for ADP_I

48

Change PC28 from 2.2u to 0.1u
Add PR72

2011
01/24

PVT2

B

B

12
13
14

15
16
A

A

17

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC, MB LA-7231P
Rev
B

4019BL
Sheet

Friday, March 04, 2011
1

56

of

57

A

1

2

3

B

C

D

E

A --> B Change List

B --> C Change List

1209-----------------------------------1. Page 24, Change R383 to GS@
Change R380 to @
Add Option Component for R383 and R386 4.99K_0402_1% with BOM structure GV@
2. Page 46, Change R679 to 100K_0402_5%
Change R685 to 200K_0402_5%
Change R692 to 750K_0402_5%
3. Page 40, Change SW8 to SN200002800
1206---------------------------------------------1. Page 17, U16 BOM Structure change to OPT@
2. Page 37, C613 BOM structure change to BT@
3. Page 32, Add T70, T71 for JCRT1.
4. Page 45, Change H10 to H2P5.
5. Page 14, Change C183, C184 to 27P
6. Page 22, Change C297, C298 to 22P
7. Page 35, Change C582, C583 to 33P
8. Page 43, Change R666, R668 to SM010017710 (For EMI)
9. Page 38, Pop R590, R591 with 33 ohm, C635, C636 with 6P for EMI
1203---------------------------------------------1. Page 39, Add C703 for ESD.
1202---------------------------------------------1. Update power schematics
2. Change H24 to H2P5
3. Page 35, Add R557 for power source +3VALW_PCH reserved
1201---------------------------------------------1. Page 40, Update Reset Button circuit
Add R656, Q38
2. Page 17, delete VGA_ON for PD only.
Change PR3.2 to PCH_GPIO2, PR3.1 to PCH_GPIO53
Delete R257
3. Update Power Schematics 1201
1130b---------------------------------------------1. Page 38, U23.11 change to +3VS_CARD
2. Q2, Q13, Q19, Q21~Q29, Q31, Q33, Q34, Q50, Q51, Q54, Q56~Q63, Q68, Q74 change to SB00000J200
1130---------------------------------------------1. Page 18, Add Q75,Q74,R841 (The new circuit for DGPU_PWROK after 1.5V).
Delete R271
2. Page40, Change R646 to 10K
Change R648 to 1K
Pop R646, R648, D18, Q35, R645 for Reset mainpower and BI
Change R653 BOM structure to @
Change SW8 to SN200002700
1129---------------------------------------------1. Page 07, Correct R70 bom structure to EDP@
2. Page 15,Change R244.1 net name from PCH_RSMRST# to PCH_RSMRST#_R
Unpop R231
3. Page 17, U6, U7 change to SA00000OH00 (Same as U5/U39)
4. Page 24, Delete R390, R391, R392 for space issue.
5. Page 35, Add Q37 and Unpop R555
6. Page 38, Add R833 between +3VS and +3VS_CARD
Change U23.47 to +3VS_CARD
7. Page 39,Change R621 from 0ohm to 8.2k(Board ID)
8. Page 42, Unpop R733
Pop R732, R299
Delete R637, R638, Q38, Q39, R299, R634, R636, R639, R640
Change netname of PD# to EC_MUTE#
Connect U29.4.9.21.29 to +3VS_CODEC
9. Page 45, Change C780 from SGA19151410(D size) to SGA00002N80(B2 size)
Unpop U40, C204, R754
10.Page 46, Change Q47, Q52 to AO4430L_SO8
11.Update Power Schematics (11/25)
12.C226, C540, C549, C566, C573, C576, C580, C590, C712 change material to SE000000K80
13.D8, D9 change material to SCS00003600 (Need check again)
14.D32 change to SC100001K00 (Need apply CIS Symbol)
1123---------------------------------------------1. Page 22, Change R342 PU location from R762.2 to Q68.3
2. Page 24, Fix N12P-GV device ID
R489 change BOM Structure to GS@
R382, R380, R760, R756, R758, R757 change BOM Structure to GV@
R380 change to 45.3K_0402_1% (SD034453280)
R760 change to 4.99K_0402_1% (SD034499180)
Delete Option compoent of R386
3. Page35, Modify auto boot-up issue
Unpop R552
POP R553, R541
Change R541 PU location from R552.1 to R552.2
4. Page36, L31 update CIS Symbol and PCB footprint
5. Page 40, Change R622 PU to +3VALW_EC
JTP1 pin definition upside down.
Update D-Door Circuit
Delete SW1, R631
Add JDOOR1, SW
6. Page 41, SW6 change to SN100001D10
7. Page 42, Modify PD# circuit for 3V tolerance.
Add R299
Change R637, R638 PU to +3VS
Fix Headphone/MIC detect issue
Change R649 to 10K_0402_1%
Change R650 to 39.2K_0402_1%
8. Page 44, Modify SMI circuit for leakage issue.
Delete R830
Add Q69, R734

0121A-----------------------------------1. Page 19, Change L1 to SHI00003Y00
2. Page 41, Change R626 to SD034499080 (499_1%)
Change R739 to SD034150080 (100_5%)
3. Page 17, Add R185
4. Page 46, Change R703 to 100K
0110A-----------------------------------1. Change SE107475M80 to SE107475K80
2. Change SE052105Z80 to SE080105K80
3. Change SE068221J80 to SE074221K80
4. Change SE070473Z80 to SE076473K80
5. Page 15, UnPOP U5 and POP R223
6. Page 35, Unpop Q37 and POP R557
7. Change U8 to SA000047U10(N12P-GS) and SA00004JO10(N12P-GV)
8. Page41,
R625 form 390 to 100
R626 from 820 to 200
R739 from 820 to 100
R627 from 390 to 2.49K
R629 from 820 to 3K
R740 from 390 to 3.3K
R741 from 390 to 2.2K
R740 from 820 to 3.3K
0107A-----------------------------------1. Page 40, Unpop SW8
2. Page 05, Add C215.
1. Page 11, Add C207, C212, C214 (0.1U_0402) for EMI reuqire
2. Page 12, Delete C159 for Layout space
3. Page 36, Delete R968, C994
4. Page 45, Reserved R736, R739
5. Page 18, Delete Q75
Change Q74 to Q74A, A74B (DMN66D0LDW-7_SOT363-6)
Change R842 PU to +3VSDGPU
0103-----------------------------------1. Page 40, Add R691 for EC_BI
2. Page 39, Connect EC_BI to U24.64
Change R621 to 18K_0402_5%
Delete net 65W/90W#
3. Page 25, Unpop C345, C346, C347, C348 L13, L14, C356, C357, C358
Change C349, C359 to 10K_5%_0402
Unpop R415, R416
4. Page 18, Change Q75 to AP2302GN-HF_SOT23-3
Add R842, C185 with BOM structure OPT@
Change Q74, Q75, R841 with BOM structure OPT@
5. Page 37, Delete R572
6. Page 08, change C81, C82 to SGA20331E10
7. Page 26, Change C381,C857 to SGA20471D20

1

2

C --> Pre-MP Change List
0222A-----------------------------------1. Page 41, Change R627, R741 to 100_0402_5%
Change R740 to 150_0402_1%
Change R627, R742 to 560_0402_5%
2. Page 45, Unpop D30 (Remove USB3.0 ESD Diode)
0218A-----------------------------------1.Page 31, Add L45 for USB20_P10/N10
Change R478/R479 to @
Move C492, C493 to USB20_P10/N10
Delete D5 for layout space
0215A-----------------------------------1. Page 44, Mount R720 for EEPROM (EON)
2. Change U3 to B3 version(SA00004EEY0)
3. Page 41, change R626 to 300_0402_5%
change R739 to 100_0402_5%
0125A-----------------------------------1. Page39 Change R621 to 33K_0402_5% (Board ID)
2. Update Power Schematics

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/28

2011/09/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB LA-7231P
Rev
B

4019BL

Date:

A

B

C

D

Sheet

Friday, March 04, 2011
E

57

of

57

www.s-manuals.com
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Page Count                      : 58
Keywords                        : Compal, LA-7231P, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary
EXIF Metadata provided by EXIF.tools

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