Compal LA 7552P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-7552P QBL50 - Schematics. Free.
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Page Count: 54
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Cover Page
B
1 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
APU Llano / Hudson M2_M3 / Vancouver Whistler
QBL60 Schematics Document
LA-7552P REV: 1.0
Compal Confidential
2010-04-25
AMD Sabine
UMA only / PX Muxless with BACO
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Block Diagrams
B
2 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
LPC BUS
Compal Confidential
USB2
3.3V 48MHz
HD Audio
FCH
Page 13~17
3.3V 24.576MHz/48Mhz
Model Name : QBL60
S-ATA
page 33
port 0
CMOS
Camera
Port 10
USB
ODD
Conn.
page 33
port 1
page 34 page 27
uFCBGA-656
Sabine
Gen2
AMD FS1 APU
uPGA-722 Package
Page 6~10
Llano
Hudson-M2/M3
Dual Channel BANK 0, 1, 2, 3
204pin DDRIII-SO-DIMM X2
1.5V DDRIII 800~1333MHz
Memory BUS(DDR3)
Page 11,12
page 28
Gen2GFX x 8
VRAM 1G/2G
128M16 x 4/8
DDR3
page 23, 24
ATI
uFCBGA-962
Vancuver Whistler
page 19
Thermal Sensor
ADM1032
GFX x 4
APU HDMI
(UMA / Muxless)
HDMI Conn.
page 27
LVDS Conn.
DP x1 (DP0 TXP/N0)
LVDS
Travis LVDS
Translator
page 26
DP x 4
(DP1 TXP/N 0~4)
UMI
FCH CRT (VGA DAC)
page 29
MINI Card 1
WLAN
page 32
GPP0GPP1
RJ45
page 29
LAN(GbE)
RTL8111E-VL
SATA HDD1
Conn.
page 32
Mini Card
(with BT)
P_GPP x 2
GEN1
CRT Conn.
page 27
Page 18~22
Touch Pad Int.KBD
page 36
page 37
page 37
ENE KB930
Port2 Port 3
page 30
USB2
(LS-7322P)
page 30
HDA Codec
ALC269
page 34
USB2
Port 0 Port 1
page 37
LED
RTC CKT.
page 13
DC/DC
Interface CKT.
page 38
Power Circuit
page 39~49
LS-7322P
Audio BD
page 35
LS-7326P
Power/B
page 30
External board
page 35
EC BIOS (2M)
BIOS ROM
Card Reader
RTS5137
Port 4
page 31
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QBL60 LA-7552P
1.0
CLOCK / DISPLAY DISTRIBUTION
Custom
3 53Monday, April 25, 2011
2011/04/25 2012/04/25
A_SODIMM
CPU FS1 SOCKET
FCH
Hudson-M2/M3
Internal CLK GEN
B_SODIMM
MEM_MA_CLK7_P/N
1066~1600MHz
1066~1600MHz
MEM_MA_CLK1_P/N
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
AMD AMD
CLK_PEG_VGAP/N
100MHz
100MHz
32.768KHz 25MHz
APU_DISP_CLKP/N
100MHz
APU_CLKP/N
100MHz
ATI VGA
Whistler
AMD
LVDS CONN
APU
DP0
DP0_TXP/N[0:1]
DP0_AUXP/N
C
RTD2132
DP_IN
LVDS_OUT
APU_TXOUT[0:2]+/-
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/-
APU_TZOUT_CLK+/-
APU_LVDS_CLK/DATA
R
TXOUT[0:2]+/-
TXCLK+/-
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA
VGA
CLOCK DISTRIBUTION DISPLAY DISTRIBUTION
: LVDS PATH
HDMI CONNCRT CONN
PCIE_GFX[0:7]
PCIE_GFX[12:15]
C
C
PCIE_GFX[0:7]
LS
DP1
FCH
R
: APU HDMI PATH
GbE LAN
25MHz
WLAN
Mini PCI Socket
GPP_CLK
GPP0GPP1
DP0_AUX
LVDS Transtator
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Notes List
B
4 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
BOM Config
FCH
SM Bus 1 address
DDR DIMM1
1101 000X b
DDR DIMM2
1101 001X b
FCH
SM Bus 0 address
Device Address Device Address
HEX
D0
D2
HEX
Device Address HEX
EC SM Bus1 address EC SM Bus2 address
Smart Battery
0001 011X b
16H
Device IDSEL# REQ#/GNT# Interrupts
External PCI Devices
+CPU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU
+CPU_CORE
Voltage Rails
VIN
B+
S1 S3 S5
ON OFF
N/A N/A N/A
N/AN/AN/A
Power Plane Description
OFF
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
+VGA_CORE OFFOFFON0.95-1.2V switched power rail
+0.75VS ONON OFF0.75V switched power rail for DDR terminator
+1.0VSG ON OFF OFF1.0V switched power rail for VGA
STATE SIGNAL
Full ON
S1(Power On Suspend)
LOW LOW
LOW
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF) LOW
SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW
LOW
HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+RTCVCC
+2.5VS
+5VS
+3VS
+5VALW
+3VALW
+VSB ON ON*
ONON
ON
ON
ON ON*
+LAN_IO ON ON ON
ON
OFF
OFF
OFF
ON
OFFON
ON
ON
OFF
ON*
OFF
ON
RTC power
2.5V for CPU_VDDA
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
3.3V power rail for LAN
+1.8VSG OFFON OFF1.8V switched power rail
+1.5VS
+1.5V ON
OFF
OFF
ON OFF
ON
1.5V switched power rail
1.5V power rail for CPU VDDIO and DDR
+1.1VS
+1.2VS ON OFF OFF
ON OFF OFF1.1V switched power rail for FCH
1.2V switched power rail for APU
+1.1ALW 1.1V switched power rail for FCH ON ON*ON
Device Address HEX
ADI ADM1032 (VGA)
1001 101X b
9AH
VGA@ Use VGA (Mux)
VRAM ID TableX76@
M2@ Use Hudson-M2
M3@ Use Hudson-M3
USB30@ USB30 on M/B
USB20@ USB20 on M/B
BTO Option Table
BTO ItemBOM Structure
x = 1 is read cmd, x= 0 is writee cmd.
(APU)
RTD2132S (TL)
U25
FCH M3
Part Number = SA000043ID0
M3@
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
POWER DELIVERY CHART
Custom
5 53Monday, April 25, 2011
2011/04/25 2012/04/25
EC
ENE KB930
+1.5V
+0.75VS
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
+3.3VS 3mA
+3.3VALW 30mA
SATA
HDD*2
ODD*1
+5V 45mA
+3.3VS 25mA
+3.3VALW 201mA
+5V 3A
+3.3V
BATTERY
12.6V
PU101
CHARGER
AC ADAPTOR
19V 90W
LAN
RTL8111E
RAM DDRIII SODIMMX2
VDD_MEM 4A
FAN Control
APL5607
+5VS 500mA
Audio Codec
ALC269-GR
RTC
Bettary
VTT_MEM 0.5A
Mini Card
BATT+
VIN
VDD CORE 54A
VDDNB 27.5A
VDDIO 4.6A
VDDR 6.7A
VDDA 500mA
AMD APU FS1
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
FCH AMD Hudson M2/M3
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
+1.1VALW
+1.1VS
+3VALW
+3VS
GND
VDDBT_RTC_GRTC BAT
VGA ATI
Whistler/Seymour/Granville
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VDDC 47A
A2VDD: 130 mA
VDDR3: 60 mA
+1.0VSG
+3VSG
0.85~1.1V
+1.5VSG
+1.8VSG
B+
+CPU_CORE
+CPU_CORE_NB
+5VALW
+3VALW
+USB_VCCA
+USB_VCCB
U54/U55
AP2301MPG
+CPU_CORE
+CPU_CORE_NB
0.9~1.0V
VDDR1: 3400 mA
VRAM 1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG 2.4 A
0.7~1.475V
+1.8VSG
+1.0VSG
PU201
ISL6267HRZ-T
+1.5V
PU501
RT8209MGQW
PU801
RT8209MGQW
+1.2VS
+1.2VS
+1.5V
PU901
RT8237CZQW
+VGA_CORE
+VGA_CORE
+VDDCI
+1.0VSG
PU602
APL5930KAI
PU401
SY8033BDBC
+1.8VSG
PU603
APL5508-25DC
+2.5VS
+2.5VS
PU301
RT8205LZQW
+1.1VALW
PU701
RT8209MGQW
U41
AO4430L
+1.5VSG
+1.5VSG
PU601
APL5336KAI
+0.75VS
+0.75VS
U39
AO4430L +1.1VS
+1.1VS
+1.1VALW
U40
SI4800
+3VALW
+3VS
PJ14
+3VSG
+3VSG
+3.3 350mA
B+ 300mA
LCD panel
15.6"
+INVPWR_B+
U33
SI4800
+5V
Dual+1
2.5A
USB X3
+1.5VS
+3VALW
+3VS
+5VS
+5VALW
+3VS
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B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
P_ZVDDP
UMI_FTX_MRX_P0
UMI_FTX_MRX_N0
UMI_FTX_MRX_P1
UMI_FTX_MRX_N1
UMI_FTX_MRX_P2
UMI_FTX_MRX_N2
UMI_FTX_MRX_P3
UMI_FTX_MRX_N3
PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1
PCIE_FTX_GRX_P0
PCIE_FTX_GRX_N0
PCIE_FTX_GRX_P1
PCIE_FTX_GRX_N1
PCIE_FTX_GRX_P2
PCIE_FTX_GRX_N2
PCIE_FTX_GRX_P3
PCIE_FTX_GRX_N3
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_GRX_P4
PCIE_FTX_GRX_N4
PCIE_FTX_GRX_P5
PCIE_FTX_GRX_N5
PCIE_FTX_GRX_P6
PCIE_FTX_GRX_N6
PCIE_FTX_GRX_P7
PCIE_FTX_GRX_N7
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
PCIE_FTX_GRX_P12
PCIE_FTX_GRX_N12
PCIE_FTX_GRX_P13
PCIE_FTX_GRX_N13
PCIE_FTX_GRX_P14
PCIE_FTX_GRX_N14
PCIE_FTX_GRX_P15
PCIE_FTX_GRX_N15
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
APU_SID
APU_SIC
EC_SMB_DA
EC_SMB_CK
P_ZVSS
PCIE_DTX_C_FRX_P132
PCIE_DTX_C_FRX_N132
UMI_MTX_C_FRX_P013
UMI_MTX_C_FRX_N013
UMI_MTX_C_FRX_P113
UMI_MTX_C_FRX_N113
UMI_MTX_C_FRX_P213
UMI_MTX_C_FRX_N213
UMI_MTX_C_FRX_P313
UMI_MTX_C_FRX_N313
PCIE_FTX_C_DRX_P0 29
PCIE_FTX_C_DRX_N0 29
PCIE_FTX_C_DRX_P1 32
PCIE_FTX_C_DRX_N1 32
UMI_FTX_C_MRX_P0 13
UMI_FTX_C_MRX_N0 13
UMI_FTX_C_MRX_P1 13
UMI_FTX_C_MRX_N1 13
UMI_FTX_C_MRX_P2 13
UMI_FTX_C_MRX_N2 13
UMI_FTX_C_MRX_P3 13
UMI_FTX_C_MRX_N3 13
PCIE_FTX_C_GRX_P[0..7] 18
PCIE_FTX_C_GRX_N[0..7] 18PCIE_GTX_C_FRX_N[0..7]18
PCIE_GTX_C_FRX_P[0..7]18
PCIE_FTX_GRX_P[12..15] 28
PCIE_FTX_GRX_N[12..15] 28
EC_SMB_CK2 19,36
APU_SID8,14
APU_SIC8,14
PCIE_DTX_C_FRX_P029
PCIE_DTX_C_FRX_N029
EC_SMB_DA2 19,36
+1.2VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
AMD FS1 PCIE / UMI / TSI
Custom
6 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
GLAN
WLAN
Power Sequence of APU
+1.5V
+2.5VS
+1.5VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
Group A
Group B
APU To HDMI
CPU TSI interface level shift BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
To EC
For UMA Mux.
To HDMI
2
1
0
CK
G
D
S
Q9
BSH111 1N_SOT23-3
2
13
C918 0.1U_0402_16V7KVGA@ 1 2
R537
0_0402_5%
1 2
C930 0.1U_0402_16V7KVGA@ 1 2
C922 0.1U_0402_16V7KVGA@ 1 2
C952 0.1U_0402_16V7K
1 2
R536
30K_0402_1%
1 2
C925 0.1U_0402_16V7KVGA@ 1 2
C928 0.1U_0402_16V7KVGA@ 1 2
C960 0.1U_0402_16V7K
1 2
C935 0.1U_0402_16V4Z
1 2
R535
31.6K_0402_1%
1 2
R538
0_0402_5%
1 2
C957 0.1U_0402_16V7K
1 2
G
D
S
Q10
BSH111 1N_SOT23-3
2
13
C959 0.1U_0402_16V7K
1 2
C919 0.1U_0402_16V7KVGA@ 1 2
C953 0.1U_0402_16V7K
1 2
C951 0.1U_0402_16V7K
1 2
GPPUMI-LINK GRAPHICS
PCI EXPRESS
JCPU1A
AMD_TOPEDO_FS-1
CONN@
P_GFX_RXP0
AA8
P_GFX_RXP1
Y7
P_GFX_RXP2
W5
P_GFX_RXP3
W8
P_GFX_RXP4
V7
P_GFX_RXP5
U5
P_GFX_RXP6
U8
P_GFX_RXP7
T7
P_GFX_RXP8
R5
P_GFX_RXP9
R8
P_GFX_RXP10
P7
P_GFX_RXP11
N5
P_GFX_RXP12
N8
P_GFX_RXP13
M7
P_GFX_RXP14
L5
P_GFX_RXP15
L8
P_GFX_RXN0
AA9
P_GFX_RXN1
Y8
P_GFX_RXN2
W6
P_GFX_RXN3
W9
P_GFX_RXN4
V8
P_GFX_RXN5
U6
P_GFX_RXN6
U9
P_GFX_RXN7
T8
P_GFX_RXN8
R6
P_GFX_RXN9
R9
P_GFX_RXN10
P8
P_GFX_RXN11
N6
P_GFX_RXN12
N9
P_GFX_RXN13
M8
P_GFX_RXN14
L6
P_GFX_RXN15
L9
P_GPP_RXP0
AC5
P_GPP_RXP1
AC8
P_GPP_RXP2
AB7
P_GPP_RXP3
AA5
P_GPP_RXN0
AC6
P_GPP_RXN1
AC9
P_GPP_RXN2
AB8
P_GPP_RXN3
AA6
P_UMI_RXP0
AF8
P_UMI_RXP1
AE6
P_UMI_RXP2
AE9
P_UMI_RXP3
AD8
P_UMI_RXN0
AF7
P_UMI_RXN1
AE5
P_UMI_RXN2
AE8
P_UMI_RXN3
AD7
P_ZVDDP
K5
P_GFX_TXP0 AA2
P_GFX_TXP1 Y2
P_GFX_TXP2 Y4
P_GFX_TXP3 W2
P_GFX_TXP4 V2
P_GFX_TXP5 V4
P_GFX_TXP6 U2
P_GFX_TXP7 T2
P_GFX_TXP8 T4
P_GFX_TXP9 R2
P_GFX_TXP10 P2
P_GFX_TXP11 P4
P_GFX_TXP12 N2
P_GFX_TXP13 M2
P_GFX_TXP14 M4
P_GFX_TXP15 L2
P_GFX_TXN0 AA3
P_GFX_TXN1 Y1
P_GFX_TXN2 Y5
P_GFX_TXN3 W3
P_GFX_TXN4 V1
P_GFX_TXN5 V5
P_GFX_TXN6 U3
P_GFX_TXN7 T1
P_GFX_TXN8 T5
P_GFX_TXN9 R3
P_GFX_TXN10 P1
P_GFX_TXN11 P5
P_GFX_TXN12 N3
P_GFX_TXN13 M1
P_GFX_TXN14 M5
P_GFX_TXN15 L3
P_GPP_TXP0 AD4
P_GPP_TXP1 AC2
P_GPP_TXP2 AB2
P_GPP_TXP3 AB4
P_GPP_TXN0 AD5
P_GPP_TXN1 AC3
P_GPP_TXN2 AB1
P_GPP_TXN3 AB5
P_UMI_TXP0 AF1
P_UMI_TXP1 AF5
P_UMI_TXP2 AE3
P_UMI_TXP3 AD1
P_UMI_TXN0 AF2
P_UMI_TXN1 AF4
P_UMI_TXN2 AE2
P_UMI_TXN3 AD2
P_ZVSS K4
C924 0.1U_0402_16V7KVGA@ 1 2
R540 196_0402_1%
1 2
R539 196_0402_1%
1 2
C917 0.1U_0402_16V7KVGA@ 1 2
C931 0.1U_0402_16V7KVGA@ 1 2
C929 0.1U_0402_16V7KVGA@ 1 2
C932 0.1U_0402_16V7KVGA@ 1 2
C927 0.1U_0402_16V7KVGA@ 1 2
C956 0.1U_0402_16V7K
1 2
C920 0.1U_0402_16V7KVGA@ 1 2
C921 0.1U_0402_16V7KVGA@ 1 2
C950 0.1U_0402_16V7K
1 2
C923 0.1U_0402_16V7KVGA@ 1 2
C926 0.1U_0402_16V7KVGA@ 1 2
C958 0.1U_0402_16V7K
1 2
C961 0.1U_0402_16V7K
1 2
C962 0.1U_0402_16V7K
1 2
C963 0.1U_0402_16V7K
1 2
![](asset-7.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ3
DDRA_SDQ13
DDRA_SDQ40
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ61
DDRA_SDQ15
DDRA_SDQ34
DDRA_SDQ36
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ53
DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ39
DDRA_SDQ46
DDRA_SDQ33
DDRA_SDQ24
DDRA_SDQ54
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ8
DDRA_SDQ51
DDRA_SDQ9
DDRA_SDQ50
DDRA_SDQ12
DDRA_SDQ31
DDRA_SDQ7
DDRA_SDQ63
DDRA_SDQ62
DDRA_SDQ42
DDRA_SDQ26
DDRA_SDQ58
DDRA_SDQ25
DDRA_SDQ32
DDRA_SDQ1
DDRA_SDQ44
DDRA_SDQ48
DDRA_SDQ11
DDRA_SDQ55
DDRA_SDQ2
DDRA_SDQ38
DDRA_SDQ27
DDRA_SDQ41
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ49
DDRA_SDQ30
DDRA_SDQ35
DDRA_SDQ37
DDRA_SDQ52
DDRA_SDQ45
DDRA_SDQ57
DDRA_SDQ56
DDRB_SDQ48
DDRB_SDQ39
DDRB_SDQ1
DDRB_SDQ42
DDRB_SDQ36
DDRB_SDQ2
DDRB_SDQ58
DDRB_SDQ33
DDRB_SDQ31
DDRB_SDQ21
DDRB_SDQ54
DDRB_SDQ62
DDRB_SDQ24
DDRB_SDQ15
DDRB_SDQ12
DDRB_SDQ49
DDRB_SDQ60
DDRB_SDQ43
DDRB_SDQ18
DDRB_SDQ34
DDRB_SDQ4
DDRB_SDQ61
DDRB_SDQ6
DDRB_SDQ25
DDRB_SDQ23
DDRB_SDQ57
DDRB_SDQ13
DDRB_SDQ0
DDRB_SDQ28
DDRB_SDQ16
DDRB_SDQ22
DDRB_SDQ19
DDRB_SDQ9
DDRB_SDQ50
DDRB_SDQ35
DDRB_SDQ46
DDRB_SDQ5
DDRB_SDQ37
DDRB_SDQ26
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ29
DDRB_SDQ14
DDRB_SDQ7
DDRB_SDQ51
DDRB_SDQ10
DDRB_SDQ59
DDRB_SDQ17
DDRB_SDQ44
DDRB_SDQ41
DDRB_SDQ38
DDRB_SDQ47
DDRB_SDQ32
DDRB_SDQ20
DDRB_SDQ52
DDRB_SDQ30
DDRB_SDQ63
DDRB_SDQ53
DDRB_SDQ40
DDRB_SDQ27
DDRB_SDQ45
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ11
DDRA_SWE#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SBS2#
DDRA_SBS1#
DDRA_SBS0#
DDRA_SMA15
DDRA_SMA12
DDRA_SMA14
DDRA_SMA13
DDRA_SMA11
DDRA_SMA10
DDRA_SMA6
DDRA_SMA1
DDRA_SMA7
DDRA_SMA2
DDRA_SMA3
DDRA_SMA8
DDRA_SMA5
DDRA_SMA4
DDRA_SMA9
DDRA_SMA0
DDRA_SDM6
DDRA_SDM3
DDRA_SDM5
DDRA_SDM4
DDRA_SDM2
DDRA_SDM1
DDRA_SDM7
DDRA_SDM0
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SDQS7
DDRA_CLK0#
DDRA_CLK0
DDRA_SCS1#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDRA_CKE0
DDRA_CKE1
MEM_MA_EVENT#
M_ZVDDIO
MEM_MA_RST#
DDRA_CLK1#
DDRA_CLK1
DDRA_SDQ20
DDRA_SDQ22
DDRA_SDQ21
DDRA_SDQ23
DDRA_SDQ17
DDRA_SDQ16
DDRA_SDQ18
DDRB_SMA14
DDRB_SMA10
DDRB_SMA7
DDRB_SMA1
DDRB_SMA12
DDRB_SMA6
DDRB_SMA11
DDRB_SMA0
DDRB_SMA9
DDRB_SMA15
DDRB_SMA3
DDRB_SMA5
DDRB_SMA8
DDRB_SMA13
DDRB_SMA2
DDRB_SMA4
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRB_ODT0
DDRB_ODT1
DDRB_CKE1
DDRB_CKE0
DDRB_CLK0#
DDRB_CLK0
DDRB_SCS1#
DDRB_SCS0#
DDRB_CLK1#
MEM_MB_RST#
MEM_MB_EVENT#
DDRB_CLK1
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDM6
DDRB_SDM4
DDRB_SDM2
DDRB_SDM0
DDRB_SDM5
DDRB_SDM3
DDRB_SDM1
DDRB_SDM7
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SDQ19
MEM_MA_EVENT#
MEM_MB_EVENT# +MEM_VREF
DDRB_SDQ[63..0] 12
DDRA_SBS0#11
DDRA_SBS1#11
DDRA_SBS2#11
DDRA_SDQS011
DDRA_SDQS0#11
DDRA_SDQS111
DDRA_SDQS1#11
DDRA_SDQS211
DDRA_SDQS2#11
DDRA_SDQS311
DDRA_SDQS3#11
DDRA_SDQS411
DDRA_SDQS4#11
DDRA_SDQS511
DDRA_SDQS5#11
DDRA_SDQS611
DDRA_SDQS6#11
DDRA_SDQS711
DDRA_SDQS7#11
DDRA_CLK011
DDRA_CLK0#11
DDRA_CKE011
DDRA_CKE111
DDRA_ODT011
DDRA_ODT111
DDRA_SCS0#11
DDRA_SCS1#11
DDRA_SRAS#11
DDRA_SCAS#11
DDRA_SWE#11
MEM_MA_RST#11
MEM_MA_EVENT#11
DDRA_CLK111
DDRA_CLK1#11
DDRA_SMA[15..0]11
DDRA_SDM[7..0]11
DDRA_SDQ[63..0] 11
DDRB_SBS0#12
DDRB_SBS1#12
DDRB_SBS2#12
DDRB_SMA[15..0]12
DDRB_SRAS#12
DDRB_SCAS#12
DDRB_SWE#12
DDRB_CLK012
DDRB_CLK0#12
DDRB_CKE012
DDRB_CKE112
DDRB_ODT012
DDRB_ODT112
DDRB_SCS0#12
DDRB_SCS1#12
MEM_MB_RST#12
MEM_MB_EVENT#12
DDRB_CLK112
DDRB_CLK1#12
DDRB_SDQS712
DDRB_SDQS7#12
DDRB_SDQS612
DDRB_SDQS512
DDRB_SDQS412
DDRB_SDQS312
DDRB_SDQS212
DDRB_SDQS112
DDRB_SDQS012
DDRB_SDQS6#12
DDRB_SDQS5#12
DDRB_SDQS4#12
DDRB_SDQS3#12
DDRB_SDQS2#12
DDRB_SDQS1#12
DDRB_SDQS0#12
DDRB_SDM[7..0]12
+1.5V
+MEM_VREF
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
AMD FS1 DDRIII I/F
Custom
7 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
EVENT# pull high 0.75V reference voltage
15mil
15mil
R543
1K_0402_1%
1 2
MEMORY CHANNEL A
JCPU1B
AMD_TOPEDO_FS-1
CONN@
MA_DATA0 E13
MA_DATA1 J13
MA_DATA2 H15
MA_DATA3 J15
MA_DATA4 H13
MA_DATA5 F13
MA_DATA6 F15
MA_DATA7 E15
MA_DATA8 H17
MA_DATA9 F17
MA_DATA10 E19
MA_DATA11 J19
MA_DATA12 G16
MA_DATA13 H16
MA_DATA14 H19
MA_DATA15 F19
MA_DATA16 H20
MA_DATA17 F21
MA_DATA18 J23
MA_DATA19 H23
MA_DATA20 G20
MA_DATA21 E20
MA_DATA22 G22
MA_DATA23 H22
MA_DATA24 G24
MA_DATA25 E25
MA_DATA26 G27
MA_DATA27 G26
MA_DATA28 F23
MA_DATA29 H24
MA_DATA30 E28
MA_DATA31 F27
MA_DATA32 AB28
MA_DATA33 AC27
MA_DATA34 AD25
MA_DATA35 AA24
MA_DATA36 AE28
MA_DATA37 AD28
MA_DATA38 AB26
MA_DATA39 AC25
MA_DATA40 Y23
MA_DATA41 AA23
MA_DATA42 Y21
MA_DATA43 AA20
MA_DATA44 AB24
MA_DATA45 AD24
MA_DATA46 AA21
MA_DATA47 AC21
MA_DATA48 AA19
MA_DATA49 AC19
MA_DATA50 AC17
MA_DATA51 AA17
MA_DATA52 AB20
MA_DATA53 Y19
MA_DATA54 AD18
MA_DATA55 AD17
MA_DATA56 AA16
MA_DATA57 Y15
MA_DATA58 AA13
MA_DATA59 AC13
MA_DATA60 Y17
MA_DATA61 AB16
MA_DATA62 AB14
MA_DATA63 Y13
MA_ADD0
U20
MA_ADD1
R20
MA_ADD2
R21
MA_ADD3
P22
MA_ADD4
P21
MA_ADD5
N24
MA_ADD6
N23
MA_ADD7
N20
MA_ADD8
N21
MA_ADD9
M21
MA_ADD10
U23
MA_ADD11
M22
MA_ADD12
L24
MA_ADD13
AA25
MA_ADD14
L21
MA_ADD15
L20
MA_BANK0
U24
MA_BANK1
U21
MA_BANK2
L23
MA_DM0
E14
MA_DM1
J17
MA_DM2
E21
MA_DM3
F25
MA_DM4
AD27
MA_DM5
AC23
MA_DM6
AD19
MA_DM7
AC15
MA_DQS_L7
AA15 MA_DQS_H7
AA14 MA_DQS_L6
AA18 MA_DQS_H6
AB18 MA_DQS_L5
AA22 MA_DQS_H5
AB22 MA_DQS_L4
AD26 MA_DQS_H4
AE26 MA_DQS_L3
E26 MA_DQS_H3
E27 MA_DQS_L2
H21 MA_DQS_H2
J21 MA_DQS_L1
H18 MA_DQS_H1
G18 MA_DQS_L0
H14 MA_DQS_H0
G14
MA_CLK_H0
T21
MA_CLK_L0
T22
MA_CLK_H1
R23
MA_CLK_L1
R24
MA_CKE0
H28
MA_CKE1
H27
MA_ODT0
Y25
MA_ODT1
AA27
MA_CS_L0
V22
MA_CS_L1
AA26
MA_RAS_L
V21
MA_CAS_L
W24
MA_WE_L
W23
MA_RESET_L
H25
MA_EVENT_L
T24
M_VREF
W20
M_ZVDDIO
W21
MEMORY CHANNEL B
JCPU1C
AMD_TOPEDO_FS-1
CONN@
MB_ADD0
T27
MB_ADD1
P24
MB_ADD2
P25
MB_ADD3
N27
MB_ADD4
N26
MB_ADD5
M28
MB_ADD6
M27
MB_ADD7
M24
MB_ADD8
M25
MB_ADD9
L26
MB_ADD10
U26
MB_ADD11
L27
MB_ADD12
K27
MB_ADD13
W26
MB_ADD14
K25
MB_ADD15
K24
MB_BANK0
U27
MB_BANK1
T28
MB_BANK2
K28
MB_DM0
D14
MB_DM1
A18
MB_DM2
A22
MB_DM3
C25
MB_DM4
AF25
MB_DM5
AG22
MB_DM6
AH18
MB_DM7
AD14
MB_DQS_H0
C15
MB_DQS_L0
B15
MB_DQS_H1
E18
MB_DQS_L1
D18
MB_DQS_H2
E22
MB_DQS_L2
D22
MB_DQS_H3
B26
MB_DQS_L3
A26
MB_DQS_H4
AG24
MB_DQS_L4
AG25
MB_DQS_H5
AG21
MB_DQS_L5
AF21
MB_DQS_H6
AG17
MB_DQS_L6
AG18
MB_DQS_H7
AH14
MB_DQS_L7
AG14
MB_CLK_H0
R26
MB_CLK_L0
R27
MB_CLK_H1
P27
MB_CLK_L1
P28
MB_CKE0
J26
MB_CKE1
J27
MB_ODT0
W27
MB_ODT1
Y28
MB_CS_L0
V25
MB_CS_L1
Y27
MB_RAS_L
V24
MB_CAS_L
V27
MB_WE_L
V28
MB_RESET_L
J25
MB_EVENT_L
T25
MB_DATA0 A14
MB_DATA1 B14
MB_DATA2 D16
MB_DATA3 E16
MB_DATA4 B13
MB_DATA5 C13
MB_DATA6 B16
MB_DATA7 A16
MB_DATA8 C17
MB_DATA9 B18
MB_DATA10 B20
MB_DATA11 A20
MB_DATA12 E17
MB_DATA13 B17
MB_DATA14 B19
MB_DATA15 C19
MB_DATA16 C21
MB_DATA17 B22
MB_DATA18 C23
MB_DATA19 A24
MB_DATA20 D20
MB_DATA21 B21
MB_DATA22 E23
MB_DATA23 B23
MB_DATA24 E24
MB_DATA25 B25
MB_DATA26 B27
MB_DATA27 D28
MB_DATA28 B24
MB_DATA29 D24
MB_DATA30 D26
MB_DATA31 C27
MB_DATA32 AG26
MB_DATA33 AH26
MB_DATA34 AF23
MB_DATA35 AG23
MB_DATA36 AG27
MB_DATA37 AF27
MB_DATA38 AH24
MB_DATA39 AE24
MB_DATA40 AE22
MB_DATA41 AH22
MB_DATA42 AE20
MB_DATA43 AH20
MB_DATA44 AD23
MB_DATA45 AD22
MB_DATA46 AD21
MB_DATA47 AD20
MB_DATA48 AF19
MB_DATA49 AE18
MB_DATA50 AE16
MB_DATA51 AH16
MB_DATA52 AG20
MB_DATA53 AG19
MB_DATA54 AF17
MB_DATA55 AD16
MB_DATA56 AG15
MB_DATA57 AD15
MB_DATA58 AG13
MB_DATA59 AD13
MB_DATA60 AG16
MB_DATA61 AF15
MB_DATA62 AE14
MB_DATA63 AF13
R541 39.2_0402_1%
1 2
R545 1K_0402_5%
1 2
C964
1000P_0402_50V7K
1
2
C965
0.1U_0402_16V7K
1
2
R544 1K_0402_5%
1 2
R542
1K_0402_1%
1 2
![](asset-8.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST21
APU_TEST22
APU_DISP_CLKP
APU_DISP_CLKN
APU_THERMTRIP#
APU_PROCHOT#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_PWRGD
APU_RST#
APU_CLKP
APU_CLKN
M_TEST
DP_AUX_ZVSS
APU_TEST24
TEST35
TEST25_H
TEST25_L
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_AUXP
DP0_AUXN
APU_SID
APU_SIC
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_TEST18
APU_TEST19
FS1R1
DP0_HPD
DP1_HPD
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
ML_VGA_AUXP
ML_VGA_AUXN
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_RST#
APU_PWRGD
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
ALERT_L
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALERT_L
APU_SVC
APU_SVD
APU_VDD_SEN
APU_VDDNB_SEN
DP_INT_PWM
DP_ENVDD
DP_ENBKL
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
M_TEST
APU_PWRGD
APU_RST#
FS1R1
TEST25_H
TEST25_L
TEST35
APU_PROCHOT#
APU_THERMTRIP#
APU_HDMI_DATA
APU_HDMI_CLK
DP5_HPD
DP0_TXP2
DP0_TXN2
DP0_TXN3
DP0_TXP3
ALLOW_STOP
ALLOW_STOP
APU_CLKP13
APU_CLKN13
APU_DISP_CLKP13
APU_DISP_CLKN13
APU_RST#13
APU_PWRGD13
DP0_TXP0_C26
DP0_TXN0_C26
DP0_AUXP_C 26
DP0_AUXN_C 26
APU_VDDNB_RUN_FB_L47
APU_VDD_RUN_FB_L47
DP0_HPD 10
DP1_HPD 10
ML_VGA_TXP015
ML_VGA_TXN015
ML_VGA_TXP115
ML_VGA_TXN115
ML_VGA_AUXP_C 15
ML_VGA_AUXN_C 15
APU_SID6,14
APU_SIC6,14
ML_VGA_TXP215
ML_VGA_TXN215
ML_VGA_TXP315
ML_VGA_TXN315
ALLOW_STOP 13
APU_SVC47
APU_SVD47
APU_VDD_SEN47
APU_VDDNB_SEN47
DP_INT_PWM 10
DP_ENBKL 10
DP_ENVDD 10
EC_THERM# 13,36,47
H_THERMTRIP# 14
APU_HDMI_CLK 28
APU_HDMI_DATA 28
DP5_HPD 10
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5VS
+3VALW
+1.2VS
+1.5V
+3VS+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
AMD FS1 Display / MISC / HDT
Custom
8 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
System DP
100MHz
100MHz_NSS
TSI
Cut on CPU side, Debug mount
To FCH VGA ML
HDT Debug conn
Llano do not support this thermal die
AUX 2~5 are for GFX interface
use, they could be selected to I2C
or AUX logic
VDDIO level
Need Level shift
LVDS
VDDIO level
Need Level shift
Place near APU
Place near APU
Place near APU
To LVDS
Translator
CRT
HDMI
To LVDS
Translator
To FCH
Close to Header
Chang to PU +1.5VS (DG ref.)
20101111
Serial VID
Route as differential
with VSS_SENSE
Chang to unpop (DG ref.)
20101111
VDDIO level
Need Level shift
If not used, pins are left unconnected (DG ref.)
20101111
FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use
MISC
THERMTRIP shutdown
temperature: 125 degree
Asserted as an input to force the
processor into the HTC-active state
Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately
APU_VDD_RUN_FB_L
APU_VDD_SEN route as differential
APU_VDDNB_RUN_FB_L
APU_VDDNB_SEN route as differential
R586
1K_0402_5%
1 2
R592 1K_0402_5%
1 2
R559 300_0402_5%
@
1 2
R582 1K_0402_5%
1 2
C974 0.1U_0402_16V7K
1 2
T14
C969 0.1U_0402_16V7K
1 2
R593 1K_0402_5%
1 2
R564 39.2_0402_1%@
1 2
R611
0_0402_5%
1 2
T10
C975 0.1U_0402_16V7K
1 2
R595 1K_0402_5%
1 2
R580 300_0402_5%
1 2
R577 1K_0402_5%
@
1 2
C980 0.1U_0402_16V7K
1 2
R587
10K_0402_5%
12
T9
R554 1.8K_0402_5%
12
R598 0_0402_5%
1 2
T22
R594 1K_0402_5%
1 2
R569 150_0402_1%
1 2
R602 0_0402_5%@
1 2
T25
R585 1K_0402_5%
1 2
T8
R589 1K_0402_5%
1 2
C981 0.1U_0402_16V7K
1 2
R583 1K_0402_5%
1 2
T15
C639 0.1U_0402_16V4Z
@
1 2
C977 0.1U_0402_16V7K
1 2
R791 1K_0402_5%
1 2
R567 39.2_0402_1%
1 2
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
TEST DISPLAY PORT MISC.
JCPU1D
AMD_TOPEDO_FS-1
CONN@
DP0_TXP0
F2
DP0_TXP1
E3
DP0_TXP2
D2
DP0_TXP3
C2
DP0_TXN0
F1
DP0_TXN1
E2
DP0_TXN2
D1
DP0_TXN3
C3
DP1_TXP0
K2
DP1_TXP1
J3
DP1_TXP2
H2
DP1_TXP3
G2
DP1_TXN0
K1
DP1_TXN1
J2
DP1_TXN2
H1
DP1_TXN3
G3
CLKIN_L
AH6
CLKIN_H
AH7
DISP_CLKIN_L
AH3
DISP_CLKIN_H
AH4
SVC
B8
SVD
A8
SIC
AH11
SID
AG11
RESET_L
AF10
PWROK
AE10
PROCHOT_L
AD10
THERMTRIP_L
AG12
ALERT_L
AH12
TDI
C12
TDO
A12
TCK
A11
TMS
D12
TRST_L
B12
DBRDY
B11
DBREQ_L
C11
RSVD_1
E8
RSVD_2
K21
RSVD_3
AC11
VSS_SENSE
B9
VDDP_SENSE
C8
VDDNB_SENSE
A9
VDDIO_SENSE
B10
VDD_SENSE
C9
VDDR_SENSE
A10
DP0_AUXP D4
DP1_AUXP E5
DP2_AUXP J5
DP3_AUXP H4
DP4_AUXP G5
DP5_AUXP F4
DP0_AUXN D5
DP1_AUXN E6
DP2_AUXN J6
DP3_AUXN H5
DP4_AUXN G6
DP5_AUXN F5
DP0_HPD D7
DP1_HPD E7
DP2_HPD J7
DP3_HPD H7
DP4_HPD G7
DP5_HPD F7
DP_DIGON C5
DP_BLON C6
DP_VARY_BL C7
DP_AUX_ZVSS D8
TEST6 AA10
TEST9 G10
TEST10 H10
TEST12 H12
TEST14 D9
TEST15 E9
TEST16 G9
TEST17 H9
TEST18 H11
TEST19 G11
TEST20 F12
TEST21 E11
TEST22 D11
TEST23 F10
TEST24 G12
TEST25_H AH10
TEST25_L AH9
TEST28_H K7
TEST28_L K8
TEST30_H AA12
TEST30_L AB12
TEST31 K22
TEST32_H AB11
TEST32_L AA11
TEST35 D10
FS1R1 Y11
DMAACTIVE_L AB10
THERMDA AE12
THERMDC AD12
R584 1K_0402_5%
1 2
C978 0.1U_0402_16V7K
1 2
T6
R556 1.8K_0402_5%
12
R609
10K_0402_5%
12
T19
C968 0.1U_0402_16V7K
1 2
E
B
C
Q12
MMBT3904_NL_SOT23-3
2
3 1
R599 0_0402_5%@
1 2
C970 0.1U_0402_16V7K
1 2
C979 0.1U_0402_16V7K
1 2
R600 0_0402_5%
1 2
T13
JP1
SAMTE_ASP-136446-07-B
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
R573 0_0402_5%@
1 2
R581 1K_0402_5%
1 2
R555 1.8K_0402_5%
12
R605 10K_0402_5%
1 2
R596 300_0402_5%
1 2
R601 10K_0402_5%
1 2
R547 1.8K_0402_5%
12
T21
R574 1K_0402_5%
1 2
R608 0_0402_5%
1 2
T11
R571 10K_0402_5%
1 2
R576 1K_0402_5%
1 2
T20
R588
10K_0402_5%
12
R590 1K_0402_5%
1 2
T12
T28
T16
C971 0.1U_0402_16V7K
1 2
C973 0.1U_0402_16V7K
1 2
R557 510_0402_1%
1 2
R603 10K_0402_5%
1 2
R606 0_0402_5%
1 2
R579 1K_0402_5%
1 2
E
B
C
Q11
MMBT3904_NL_SOT23-3
2
31
R610
1K_0402_5%
1 2
R558 300_0402_5%
1 2
T7
R612 1K_0402_5%
1 2
R548 510_0402_1%
1 2
C972 0.1U_0402_16V7K
1 2
R597 0_0402_5%
1 2
R591
0_0402_5%
1 2
C976 0.1U_0402_16V7K
1 2
R575 1K_0402_5%
1 2
R578 300_0402_5%
1 2
![](asset-9.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA_APU
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+1.2VS
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+1.5V
+1.5V
+CPU_CORE
+CPU_CORE_NB
+1.2VS
+1.2VS
+2.5VS
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
AMD FS1 PWR / GND
Custom
9 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Keep trace from resistor to APU
within 0.6"
Keep trace from Caps to APU
within 1.2"
Decoupling between CPU and DIMMs
across VDDIO and VSS split
CPU BOTTOM SIDE DECOUPLING
CPU_CORE
330uF X 4
22uF X 11
CORE_NB
330uF X 2
22uF X 4
VDDP decoupling
VDDR decoupling
40mil
120mil120mil
160mil160mil
160mil160mil
900mil900mil
2000mil2000mil
C1038 change to SF000002Y00
20101228
4A
VDD
+CPU_CORE
VDDA
+2.5VS 0.75A
VDDNB
+CPU_CORE_NB
VDDIO
+1.5V
Consumption
50A
VDDP / VDDR
+1.2VS
Power Name
3A / 3.5A
22.5A
VDDP/R_PWM
470uF x 2
10uF x 1
VDDP
10uF x 3
0.22uF x 2
180pF x 2
VDDIO_SUS
(CPU side)
680uF x 1
330uF x 1
22uF x 3
4.7uF x 4
0.22uF x 6
180pF x 4
VDDR
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4
Demo Board Capacitor (include PWM side)
CPU_CORE
470uF x 6
22uF x 9
0.22uF x 2
180pF x 2
10nF x 3
CORE_NB
470uF x 4
22uF x 6
0.22uF x 2
180uF x 3
VDDIO_SUS
(DIMM x2)
100uF x 4
0.1uF
C18 & C1043 follow AMD request
201012061900
JCPU1E
AMD_TOPEDO_FS-1
CONN@
VDD
C1
VDD
D3
VDD
D6
VDD
E1
VDD
F3
VDD
F6
VDD
F8
VDD
G1
VDD
H3
VDD
H6
VDD
H8
VDD
J1
VDD
K3
VDD
K6
VDD
L1
VDD
L11
VDD
L19
VDD
M3
VDD
M6
VDD
M10
VDD
M18
VDD
N1
VDD
N11
VDD
N19
VDD
P3
VDD
P6
VDD
P10
VDD
P18
VDD
R1
VDD
R11
VDD
R19
VDD
T3
VDDNB
K9
VDDNB
J9
VDDNB
J10
VDDNB
J11
VDDNB
J12
VDDNB
J14
VDDNB
J16
VDDNB
K10
VDD T6
VDD T10
VDD T18
VDD U1
VDD U11
VDD U19
VDD V3
VDD V6
VDD V10
VDD V18
VDD W1
VDD W11
VDD W13
VDD W15
VDD W17
VDD W19
VDD Y3
VDD Y6
VDD Y10
VDD Y12
VDD Y14
VDD Y16
VDD Y18
VDD Y20
VDD AA1
VDD AB3
VDD AB6
VDD AC1
VDD AD3
VDD AD6
VDD AE1
VDDNB L18
VDDNB K11
VDDNB K12
VDDNB K13
VDDNB K14
VDDNB K16
VDDNB K17
VDDNB K18
VDDIO
G28
VDDIO
H26
VDDIO
J28
VDDIO
K20
VDDIO
K23
VDDIO
K26
VDDIO
L22
VDDIO
L25
VDDIO
L28
VDDIO
M20
VDDIO
M23
VDDIO
M26
VDDIO
N22
VDDIO
N25
VDDIO
N28
VDDIO
P20
VDDIO
P23
VDDIO
P26
VDDIO R22
VDDIO R25
VDDIO R28
VDDIO T20
VDDIO T23
VDDIO T26
VDDIO U22
VDDIO U25
VDDIO U28
VDDIO V20
VDDIO V23
VDDIO V26
VDDIO W22
VDDIO W28
VDDIO W25
VDDIO Y24
VDDIO Y26
VDDIO AA28
VDDP_A_1
AG2
VDDP_A_2
AG3
VDDP_A_3
AG4
VDDP_A_4
AG5
VDDP_B_1 A3
VDDP_B_2 A4
VDDP_B_3 B3
VDDP_B_4 B4
VDDR
AG6
VDDR
AG7
VDDR
AG8
VDDR
AG9
VDDR A5
VDDR A6
VDDR B5
VDDR B6
VDDA
AE11
VDDA
AF11
C1024
180P_0402_50V8J
1
2
C1020
0.22U_0603_16V4Z
1
2
C998
0.01U_0402_16V7K
1
2
+
C1009
390U_2.5V_10M
1
2
C1001
22U_0805_6.3V6M
1
2
C11
4.7U_0603_6.3V6K
1
2
C1023
0.22U_0603_16V4Z
1
2
C17
4.7U_0603_6.3V6K
1
2
C1050
1000P_0402_50V7K
1
2
C1021
0.22U_0603_16V4Z
1
2
C990
0.01U_0402_16V7K
1
2
C1004
0.22U_0603_16V4Z
1
2
C988
0.22U_0603_16V4Z
1
2
C1007
180P_0402_50V8J
1
2
C1025
180P_0402_50V8J
1
2
C997
22U_0805_6.3V6M
1
2
C1036
0.22U_0603_16V4Z
1
2
C1053
0.22U_0603_16V4Z
1
2
C1055
0.22U_0603_16V4Z
1
2
C1041
0.22U_0603_16V4Z
1
2
C1040
3300P_0402_50V7K
12
C992
180P_0402_50V8J
1
2
+
C1038
220U_6.3V_M
1
2
C1002
22U_0805_6.3V6M
1
2
C1003
22U_0805_6.3V6M
1
2
C989
0.01U_0402_16V7K
1
2
C1006
180P_0402_50V8J
1
2
C1049
1000P_0402_50V7K
1
2
C15
4.7U_0603_6.3V6K
1
2
C1005
0.22U_0603_16V4Z
1
2
C1028
0.22U_0603_16V4Z
1
2
C1047
180P_0402_50V8J
1
2
C1035
180P_0402_50V8J
1
2
C1037
0.22U_0603_16V4Z
1
2
C1013
22U_0805_6.3V6M
1
2
C1034
180P_0402_50V8J
1
2
+
C994
390U_2.5V_10M
1
2
C10
4.7U_0603_6.3V6K
1
2
+
C993
390U_2.5V_10M
1
2
C1029
180P_0402_50V8J
1
2
C996
22U_0805_6.3V6M
1
2
C8
10U_0603_6.3V6M
1
2
C1008
180P_0402_50V8J
1
2
C982
22U_0805_6.3V6M
1
2
L1
FBMA-L11-201209-221LMA30T_0805
12
C1027
0.22U_0603_16V4Z
1
2
C987
0.22U_0603_16V4Z
1
2
C1052
0.22U_0603_16V4Z
1
2
C18
4.7U_0805_10V4Z
1
2
C1054
0.22U_0603_16V4Z
1
2
C1022
0.22U_0603_16V4Z
1
2
C984
22U_0805_6.3V6M
1
2
C1018
0.22U_0603_16V4Z
1
2
C13
4.7U_0603_6.3V6K
1
2
C1045
180P_0402_50V8J
1
2
+
C5
330U_D2_2V_Y
1
2
C1043
180P_0402_50V8J
@
1
2
JCPU1F
AMD_TOPEDO_FS-1
CONN@
VSS
A7
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A23
VSS
A25
VSS
B7
VSS
C4
VSS
C10
VSS
C14
VSS
C16
VSS
C18
VSS
C20
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D25
VSS
D27
VSS
E4
VSS
E10
VSS
E12
VSS
F9
VSS
F11
VSS
F14
VSS
F16
VSS
F18
VSS
F20
VSS
F22
VSS
F24
VSS
F26
VSS
F28
VSS
G4
VSS
G8
VSS
G13
VSS
G15
VSS
G17
VSS
G19
VSS
G21
VSS
G23
VSS
G25
VSS
J4
VSS
J8
VSS
J18
VSS
J20
VSS
J22
VSS
J24
VSS
K19
VSS
L4
VSS
L7
VSS
L10
VSS
M9
VSS
M11
VSS
M19
VSS
N4
VSS
N7
VSS
N10
VSS
N18
VSS
P9
VSS
P11
VSS
P19
VSS
R4
VSS
R7
VSS
R10
VSS
R18
VSS
T9
VSS T11
VSS T19
VSS U4
VSS U7
VSS U10
VSS U18
VSS V9
VSS V11
VSS V19
VSS W4
VSS W7
VSS W10
VSS W12
VSS W14
VSS W16
VSS W18
VSS Y9
VSS Y22
VSS AA4
VSS AA7
VSS AB9
VSS AB13
VSS AB15
VSS AB17
VSS AB19
VSS AB21
VSS AB23
VSS AB25
VSS AB27
VSS AC4
VSS AC7
VSS AC10
VSS AC12
VSS AC14
VSS AC16
VSS AC18
VSS AC20
VSS AC22
VSS AC24
VSS AC26
VSS AC28
VSS AD9
VSS AD11
VSS AE4
VSS AE7
VSS AE13
VSS AE15
VSS AE17
VSS AE19
VSS AE21
VSS AE23
VSS AE25
VSS AE27
VSS AF3
VSS AF6
VSS AF9
VSS AF12
VSS AF14
VSS AF16
VSS AF18
VSS AF20
VSS AF22
VSS AF24
VSS AF26
VSS AF28
VSS AG10
VSS AH5
VSS AH8
VSS AH13
VSS AH15
VSS AH17
VSS AH19
VSS AH21
VSS AH23
VSS AH25
C983
22U_0805_6.3V6M
1
2
C1044
180P_0402_50V8J
1
2
C1012
22U_0805_6.3V6M
1
2
C7
10U_0603_6.3V6M
1
2
C985
22U_0805_6.3V6M
1
2
C1051
1000P_0402_50V7K
1
2
C991
180P_0402_50V8J
1
2
C16
4.7U_0603_6.3V6K
1
2
C986
22U_0805_6.3V6M
1
2
C14
4.7U_0603_6.3V6K
1
2
C1000
22U_0805_6.3V6M
1
2
+
C999
390U_2.5V_10M
1
2
C1030
180P_0402_50V8J
1
2
+
C1015
390U_2.5V_10M
1
2
C6
10U_0603_6.3V6M
1
2
+
C1014
390U_2.5V_10M
1
2
C12
4.7U_0603_6.3V6K
1
2
C1019
0.22U_0603_16V4Z
1
2
C1046
180P_0402_50V8J
1
2
C1048
1000P_0402_50V7K
1
2
![](asset-a.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVDS_HPD
FCH_CRT_HPD
APU_HDMI_HPD
DP_ENBKL
APU_ENBKL
ENBKL
LVDS_HPD26 DP0_HPD 8
FCH_CRT_HPD15 DP1_HPD 8
APU_HDMI_HPD28 DP5_HPD 8
DP_ENBKL8
DP_ENVDD8
APU_ENVDD 27
DP_INT_PWM8
APU_INVT_PWM 26,27
ENBKL 36
+1.5VS
+3VS
+1.5VS
+3VS
+1.5VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
AMD FS1 Singal Level Shifter
Custom
10 53Monday, April 25, 2011
2011/04/25 2012/04/25
Translator HPD
CRT HPD
HDMI HPD
From Translator
From FCH
From HDMI Conn
Q15 / Q19 / Q21 change to SB000006A00
20101228
R637 2.2K_0402_5%
1 2
R624 0_0402_5%@
1 2
R616
1K_0402_5%
1 2
R636
4.7K_0402_5%
12
E
B
C
Q21
MMBT3904_NL_SOT23-3
2
3 1
R614
4.7K_0402_5%
@
12
R632
4.7K_0402_5%
@
12
G
D
S
Q16
2N7002K_SOT23-3
2
1 3
E
B
C
Q15
MMBT3904_NL_SOT23-3
@
2
3 1
G
D
S
Q18
2N7002K_SOT23-3
@
2
13
R620
100K_0402_5%
@
1 2
R634
100K_0402_5%
@
1 2
R630
4.7K_0402_5%
@
12
R635
47K_0402_5%
12
R677 0_0402_5%
1 2
R615
1K_0402_5%
@
1 2
E
B
C
Q19
MMBT3904_NL_SOT23-3
@
2
3 1
R659 100K_0402_5%
@12
R618 100K_0402_5%
@12
G
D
S
Q14
2N7002K_SOT23-3
@
2
13
G
D
S
Q20
2N7002K_SOT23-3
2
13
R631
100K_0402_5%
@
1 2
R613
10K_0402_5%
12
G
D
S
Q13
2N7002K_SOT23-3
2
1 3
R622
1K_0402_5%
@
1 2
R627 100K_0402_5%
@12
R633 2.2K_0402_5%
@
1 2
R619 2.2K_0402_5%
@
1 2
R676 0_0402_5%
1 2
R638
4.7K_0402_5%
12
R617
100K_0402_5%
@
1 2
R621
10K_0402_5%
12
R623
1K_0402_5%
1 2
![](asset-b.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRA_SDQ36
DDRA_SDQ63
DDRA_SDQ26
DDRA_SDQS6
DDRA_SDQ2
DDRA_SDQ5
DDRA_SDQ22
DDRA_SDQ25
DDRA_SDQ35
DDRA_SMA12
DDRA_SDQ14
DDRA_SDQS0#
DDRA_SDQS4
DDRA_SDM6
DDRA_SDQ42
DDRA_CKE1
DDRA_SDQ27
DDRA_SMA15
DDRA_SDQ31
DDRA_CKE0
DDRA_SDQ12
DDRA_SDQ59
DDRA_SMA3
DDRA_SDQ6
DDRA_SCS1#
DDRA_SDQ39
DDRA_SBS1#
DDRA_SWE#
DDRA_SMA7
DDRA_SDQS0
DDRA_SMA0
DDRA_SDM2
DDRA_SDQS7
DDRA_SDM1
DDRA_SDQ57
DDRA_SDQ46
DDRA_SDQ0
DDRA_SDQ28
DDRA_SDM0
DDRA_SDQS5#
DDRA_SDQ51
DDRA_SDQ19
DDRA_SDM4
DDRA_SDQ4
DDRA_SDQ30
DDRA_SDQS2
DDRA_SDQ44
DDRA_SRAS#
DDRA_SDQ33
DDRA_SDQ58
DDRA_SDM5
DDRA_SDQS3
DDRA_SMA8
DDRA_SCS0#
DDRA_SDQ10
DDRA_SMA6
DDRA_SMA10
DDRA_SDQ3
MEM_MA_RST#
DDRA_SDQS7#
DDRA_SDQS6#
DDRA_SDQ1
DDRA_SDQ40
DDRA_SMA9
DDRA_SDQ16
DDRA_SDQ29
DDRA_SDQS4#
DDRA_SDQ52
DDRA_SDM3
DDRA_SDQS5
DDRA_SDQ54
DDRA_SDQ49
DDRA_SBS2#
DDRA_SDQ45
DDRA_SDQ9
DDRA_SDM7
DDRA_SMA1
DDRA_SDQ7
DDRA_SDQ13
DDRA_SDQ20
DDRA_SDQ60
DDRA_SBS0#
DDRA_SCAS# DDRA_ODT0
DDRA_SDQ37
DDRA_SMA5
DDRA_SDQS1#
DDRA_SMA14
DDRA_SDQ55
DDRA_SMA4
DDRA_SDQ21
DDRA_SDQ62
DDRA_SDQ24
DDRA_SDQ15
DDRA_SDQ56
DDRA_SDQ23
DDRA_SDQ53
DDRA_SDQ47
DDRA_ODT1
DDRA_SDQ18
DDRA_SDQ43
DDRA_SDQ34
DDRA_CLK1
DDRA_CLK1#
DDRA_SDQ48
DDRA_SDQS2#
DDRA_SDQ11
DDRA_SDQ38
DDRA_CLK0
DDRA_CLK0#
DDRA_SDQ32
DDRA_SDQS3#
DDRA_SMA13
DDRA_SMA11
DDRA_SDQ50
DDRA_SDQ8
DDRA_SDQS1
DDRA_SDQ61
DDRA_SMA2
DDRA_SDQ41
DDRA_SDQ17
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
+VREF_DQ
+VREF_CA
MEM_MA_EVENT#
DDRA_CKE07
DDRA_SCS1#7
DDRA_SBS1# 7
DDRA_SWE#7
DDRA_SRAS# 7
DDRA_SCS0# 7
MEM_MA_RST# 7
DDRA_SBS2#7
DDRA_SBS0#7
DDRA_SCAS#7 DDRA_ODT0 7
DDRA_ODT1 7
DDRA_CLK1# 7
DDRA_CLK1 7
DDRA_CLK07
DDRA_CLK0#7
DDRA_CKE1 7
FCH_SDATA0 12,14,32
FCH_SCLK0 12,14,32
DDRA_SDQS3 7
DDRA_SDQS0 7
DDRA_SDQS3# 7
DDRA_SDQS0# 7
DDRA_SDQS5 7
DDRA_SDQS5# 7
DDRA_SDQS7 7
DDRA_SDQS7# 7
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
DDRA_SDQ[0..63] 7
DDRA_SDM[0..7] 7
DDRA_SMA[0..15] 7
MEM_MA_EVENT# 7
+0.75VS
+3VS
+1.5V +1.5V+VREF_DQ
+VREF_CA
+3VS
+1.5V+VREF_DQ
+1.5V+VREF_CA
+1.5V
+1.5V+0.75VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
DDRIII SO-DIMM 1
Custom
11 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
DIMM_A STD H:9.2mm
<Address: 00>
15mil
15mil
15mil
15mil
Add C1106
20101101
Place near DIMM1
C1065
1000P_0402_50V7K
1
2
R639
1K_0402_1%
1 2
C1062
1000P_0402_50V7K
1
2
R640
1K_0402_1%
1 2
C1080
2.2U_0603_6.3V4Z
1
2
C1068
0.1U_0402_16V4Z
1
2
C1060
4.7U_0603_6.3V6K
@
1
2
R642
1K_0402_1%
1 2
R645
10K_0402_5%
12
C1063
4.7U_0603_6.3V6K
@
1
2
C1066
1000P_0402_50V7K
1
2
C1074
0.1U_0402_16V4Z
1
2
C1070
0.1U_0402_16V4Z
1
2
C1106 0.1U_0402_16V4Z
@
1 2
C1081
0.1U_0402_16V4Z
1
2
C1075
0.1U_0402_16V4Z
1
2
R641
1K_0402_1%
1 2
C1069
0.1U_0402_16V4Z
1
2
C1064
0.1U_0402_16V4Z
1
2
R643 10K_0402_5%
1 2
C1073
0.1U_0402_16V4Z
1
2
C1071
0.1U_0402_16V4Z
1
2
C1072
0.1U_0402_16V4Z
1
2
C1079
4.7U_0603_6.3V6K
1
2
C1077
0.1U_0402_16V4Z
1
2
C1067
0.1U_0402_16V4Z
1
2
C1076
0.1U_0402_16V4Z
1
2
JDIMM2
TYCO_2-2013310-1
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C1061
0.1U_0402_16V4Z
1
2
C1078
0.1U_0402_16V4Z
1
2
![](asset-c.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SDQS6
DDRB_SDQ26
DDRB_SDQ63
DDRB_SDQ36
DDRB_SDQ35
DDRB_SDQ25
DDRB_SDQ22
DDRB_SDQ5
DDRB_SDQ2
DDRB_SDQS0#
DDRB_SDQ14
DDRB_SMA12
DDRB_CKE1
DDRB_SDQ42
DDRB_SDM6
DDRB_SDQS4
DDRB_SMA15
DDRB_SDQ27
DDRB_SDQ12
DDRB_CKE0
DDRB_SDQ31
DDRB_SMA3
DDRB_SDQ59
DDRB_SBS1#
DDRB_SDQ39
DDRB_SCS1#
DDRB_SDQ6
DDRB_SDQS0
DDRB_SMA7
DDRB_SWE#
DDRB_SMA0
DDRB_SDM2
DDRB_SDQ0
DDRB_SDQ46
DDRB_SDQ57
DDRB_SDM1
DDRB_SDQS7
DDRB_SDM0
DDRB_SDQ28
DDRB_SDM4
DDRB_SDQ19
DDRB_SDQ51
DDRB_SDQS5#
DDRB_SDQS2
DDRB_SDQ30
DDRB_SDQ4
DDRB_SDQ33
DDRB_SRAS#
DDRB_SDQ44
DDRB_SDQS3
DDRB_SDM5
DDRB_SDQ58
DDRB_SMA8
DDRB_SCS0#
DDRB_SMA10
DDRB_SMA6
DDRB_SDQ10
DDRB_SDQS6#
DDRB_SDQS7#
MEM_MB_RST#
DDRB_SDQ3
DDRB_SDQ16
DDRB_SMA9
DDRB_SDQ1
DDRB_SDQS4#
DDRB_SDQ29
DDRB_SDQ49
DDRB_SDQ54
DDRB_SDQS5
DDRB_SDM3
DDRB_SDQ9
DDRB_SDQ45
DDRB_SBS2#
DDRB_SDQ20
DDRB_SDQ13
DDRB_SDQ7
DDRB_SMA1
DDRB_SDM7
DDRB_SBS0#
DDRB_SDQ60
DDRB_SDQ37
DDRB_ODT0DDRB_SCAS#
DDRB_SDQ55
DDRB_SMA14
DDRB_SDQS1#
DDRB_SMA5
DDRB_SDQ21
DDRB_SMA4
DDRB_SDQ62
DDRB_SDQ15
DDRB_SDQ24
DDRB_SDQ47
DDRB_SDQ53
DDRB_SDQ23
DDRB_SDQ56
DDRB_SDQ43
DDRB_SDQ18
DDRB_ODT1
DDRB_CLK1#
DDRB_CLK1
DDRB_SDQ34
DDRB_SDQS2#
DDRB_SDQ48
DDRB_CLK0#
DDRB_CLK0
DDRB_SDQ11
DDRB_SDQ50
DDRB_SMA11
DDRB_SMA13
DDRB_SDQS3#
DDRB_SDQ32
DDRB_SMA2
DDRB_SDQ61
DDRB_SDQS1
DDRB_SDQ8
DDRB_SDQ17
DDRB_SDQ41
DDRB_SDQ40
DDRB_SDQ38
DDRB_SDQ52
+VREF_DQ +VREF_CA
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
MEM_MB_EVENT#
DDRB_SCS1#7
DDRB_CKE07
DDRB_SCS0# 7
DDRB_SRAS# 7
DDRB_SWE#7
DDRB_SBS1# 7
DDRB_SCAS#7
DDRB_SBS0#7
DDRB_SBS2#7
MEM_MB_RST# 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_ODT1 7
DDRB_ODT0 7
DDRB_CKE1 7
DDRB_CLK0#7
DDRB_CLK07
DDRB_SDQS27
DDRB_SDQS2#7
DDRB_SDQS47
DDRB_SDQS4#7
DDRB_SDQS67
DDRB_SDQS6#7
DDRB_SDQS0# 7
DDRB_SDQS0 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_SDQS5 7
DDRB_SDQS5# 7
DDRB_SDQS7 7
DDRB_SDQS7# 7
FCH_SDATA0 11,14,32
FCH_SCLK0 11,14,32
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQ[0..63] 7
DDRB_SDM[0..7] 7
DDRB_SMA[0..15] 7
MEM_MB_EVENT# 7
+0.75VS
+1.5V+1.5V
+3VS
+VREF_DQ
+VREF_CA
+VREF_DQ +VREF_CA
+1.5V+1.5V
+1.5V
+0.75VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
DDRIII SO-DIMM 2
Custom
12 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
DIMM_B STD H:5.2mm
<Address: 01>
15mil
15mil 15mil 15mil
Place near DIMM2
Add C1107
20101101
C1084
1000P_0402_50V7K
1
2
C1098
0.1U_0402_16V4Z
1
2
R648
10K_0402_5%
<BOM Structure>
12
C1089
0.1U_0402_16V4Z
1
2
C1092
0.1U_0402_16V4Z
1
2
C1093
0.1U_0402_16V4Z
1
2
C1090
0.1U_0402_16V4Z
1
2
C1086
0.1U_0402_16V4Z
1
2
C1083
0.1U_0402_16V4Z
1
2
C1099
0.1U_0402_16V4Z
1
2C1107 0.1U_0402_16V4Z
@
1 2
R646 10K_0402_5%
<BOM Structure>
1 2
C1096
0.1U_0402_16V4Z
1
2
C1085
4.7U_0603_6.3V6K
@
1
2
C1094
0.1U_0402_16V4Z
1
2
C1101
4.7U_0603_6.3V6K
1
2
C1095
0.1U_0402_16V4Z
1
2
C1082
4.7U_0603_6.3V6K
@
1
2
C1091
0.1U_0402_16V4Z
1
2
C1100
0.1U_0402_16V4Z
1
2
C1088
1000P_0402_50V7K
1
2
JDIMM1
TYCO_2-2013289-1
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
+
C9
330U_X_2VM_R6M@
1
2
C1087
1000P_0402_50V7K
1
2
C1097
0.1U_0402_16V4Z
1
2
![](asset-d.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
PCIE_CALRP
PCIE_CALRN
APU_PWRGD
CLK_CALRN
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
25M_X2
32K_X1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
25M_X1
32K_X2
32K_X1
32K_X2
VGA_PWRGD VGA_PWRGD_R
VGA_PWRGD_R
RTCVCC_R
APU_PWRGD
APU_PCIE_RST#_C
CLK_SD_48M_R
PE_GPIO1
APU_CLKP
APU_CLKN
CLK_PEG_VGA
CLK_PEG_VGA#
APU_DISP_CLKP
APU_DISP_CLKN
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
LPC_CLK1_R
APU_PCIE_RST#_C
LPC_CLK0_ECLPC_CLK0_EC_R
A_RST#_R
TRAVIS_CLKP
TRAVIS_CLKN
ALLOW_STOP 8
PCI_CLK4 16
APU_RST# 8
EC_THERM# 8,36,47
UMI_FTX_C_MRX_P06
UMI_FTX_C_MRX_N06
UMI_FTX_C_MRX_P16
UMI_FTX_C_MRX_N16
UMI_FTX_C_MRX_P26
UMI_FTX_C_MRX_N26
UMI_FTX_C_MRX_P36
UMI_FTX_C_MRX_N36
UMI_MTX_C_FRX_P06
UMI_MTX_C_FRX_N06
UMI_MTX_C_FRX_P16
UMI_MTX_C_FRX_N16
UMI_MTX_C_FRX_P26
UMI_MTX_C_FRX_N26
UMI_MTX_C_FRX_P36
UMI_MTX_C_FRX_N36
APU_PWRGD 8
LPC_CLK1 16
RTC_CLK 16,36
LPC_AD0 32,36
LPC_AD1 32,36
LPC_AD2 32,36
LPC_AD3 32,36
SERIRQ 36
LPC_FRAME# 32,36
PCI_AD27 16
PCI_CLK3 16
PCI_AD26 16
PCI_AD25 16
PCI_AD24 16
PCI_AD23 16
PCI_CLK1 16
VGA_PWRGD25,48
PE_GPIO0 18
PE_GPIO1 25,36
APU_PWRGD_L 47
LPC_CLK0_EC 16,36
CLK_SD_48M31
CLK_PEG_VGA18
CLK_PEG_VGA#18
APU_CLKP8
APU_CLKN8
APU_DISP_CLKP8
APU_DISP_CLKN8
CLK_PCIE_MINI132
CLK_PCIE_MINI1#32
CLK_PCIE_LAN29
CLK_PCIE_LAN#29
CLK_PCI_DB 32
PLT_RST# 18,26,29,32
A_RST#36
TRAVIS_CLKP26
TRAVIS_CLKN26
+1.1VS_CKVDD
+PCIE_VDDR_FCH
+3VALW
+RTCVCC
+CHGRTC
+RTCBATT
+RTCBATT
+3VS
+3VALW
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
Custom
13 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
WLAN
For PCIE device reset on FS1
(GLAN,WLAN)
Close to HUDSON-M2
PCI Host Bus Reset (To EC)
PROCHOT# : IN, 0.8V threshold
VGA
APU
APU DISP
APU_PG/APU_RST#/LDT_STP# : OD pin
LDT_STP : No use, NC
DMA_ACTIVE# : IN/OD, 0.8V threshold
W=20mils
for Clear CMOS
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
NSS
SS
SS
Q38 change to SB000006A00
20101228
GLAN
EMI
For "EXT" CLK mode, input to PCIE,
R856 0_0402_5%
1 2
C1190 0.1U_0402_16V7K
1 2
R861
20M_0402_5%
12
R625 0_0402_5%
1 2
R657 33_0402_5%
1 2
R858
1M_0402_5%
R853 0_0402_5%@
1 2
R836
4.7K_0402_5%
1 2
JRTC1
SUYIN_060003HA002G202ZL
CONN@
+1
-
2
C1206
10P_0402_50V8J
1 2
R604 0_0402_5%
1 2
C1205
10P_0402_50V8J
1 2
R842 0_0402_5%
1 2
C1191 0.1U_0402_16V7K
1 2
X1
25MHZ_20PF_7A25000012
12
T23
U27
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1Y4
P5
G
3
C1200
12P_0402_50V8J
12
R844
0_0402_5%
1 2
R843
22_0402_5%
1 2
R671
22_0402_5%
1 2
R827 590_0402_1%
1 2
R857
1K_0402_5%
12
C1199
0.1U_0402_16V4Z
@
1 2
Y4
32.768KHZ 7PF Q13MC1461000100
OSC
4
OSC
1
NC 3
NC 2
R826
8.2K_0402_5%@
1 2
T24
R835 0_0402_5%
1 2
C1202
0.1U_0402_16V4Z
1
2
R109 10K_0402_5%
@
1 2
R833 2K_0402_1%
1 2
CLRP1
SHORT PADS
@
12
C1189 0.1U_0402_16V7K
1 2
R825 33_0402_5%
1 2
C1194 0.1U_0402_16V7K
1 2
R834
10K_0402_5%
12
R855 22_0402_5%
1 2
C1197 0.1U_0402_16V7K
1 2
C1198 0.1U_0402_16V7K
1 2
C1201 12P_0402_50V8J
12
C1196 0.1U_0402_16V7K
1 2
R830 0_0402_5%@
1 2
C1192 0.1U_0402_16V7K
1 2
U26
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1Y4
P5
G
3
C1188
150P_0402_50V8J 1
2
C1195 150P_0402_50V8J
12
R829 33_0402_5%
1 2
C1203
1U_0402_6.3V4Z
1
2
R859 510_0402_5%
1 2
C1204
0.1U_0402_16V4Z
1
2
R832 0_0402_5%
1 2
C1193
0.1U_0402_16V4Z
@
1 2
E
B
C
Q38
MMBT3904_NL_SOT23-3
2
3 1
R828 2K_0402_1%
1 2
D23
DAN202UT106_SC70-3
2
3
1
R644 0_0402_5%
1 2
R572 0_0402_5%
1 2
HUDSON-2
PCI CLKS
PCI EXPRESS INTERFACES
PCI INTERFACE
CLOCK GENERATOR
LPCAPUS5 PLUS
U25A
HUDSON-M2_FCBGA656
M2@
PCIE_RST#
AE2
A_RST#
AD5
UMI_TX0P
AE30
UMI_TX0N
AE32
UMI_TX1P
AD33
UMI_TX1N
AD31
UMI_TX2P
AD28
UMI_TX2N
AD29
UMI_TX3P
AC30
UMI_TX3N
AC32
UMI_RX0P
AB33
UMI_RX0N
AB31
UMI_RX1P
AB28
UMI_RX1N
AB29
UMI_RX2P
Y33
UMI_RX2N
Y31
UMI_RX3P
Y28
UMI_RX3N
Y29
PCIE_CALRP
AF29
PCIE_CALRN
AF31
GPP_TX0P
V33
GPP_TX0N
V31
GPP_TX1P
W30
GPP_TX1N
W32
GPP_TX2P
AB26
GPP_TX2N
AB27
GPP_TX3P
AA24
GPP_TX3N
AA23
GPP_RX0P
AA27
GPP_RX0N
AA26
GPP_RX1P
W27
GPP_RX1N
V27
GPP_RX2P
V26
GPP_RX2N
W26
GPP_RX3P
W24
GPP_RX3N
W23
CLK_CALRN
F27
PCIE_RCLKP
G30
PCIE_RCLKN
G28
DISP_CLKP
R26
DISP_CLKN
T26
DISP2_CLKP
H33
DISP2_CLKN
H31
APU_CLKP
T24
APU_CLKN
T23
SLT_GFX_CLKP
J30
SLT_GFX_CLKN
K29
GPP_CLK0P
H27
GPP_CLK0N
H28
GPP_CLK1P
J27
GPP_CLK1N
K26
GPP_CLK2P
F33
GPP_CLK2N
F31
GPP_CLK3P
E33
GPP_CLK3N
E31
GPP_CLK4P
M23
GPP_CLK4N
M24
GPP_CLK5P
M27
GPP_CLK5N
M26
GPP_CLK6P
N25
GPP_CLK6N
N26
GPP_CLK7P
R23
GPP_CLK7N
R24
GPP_CLK8P
N27
GPP_CLK8N
R27
14M_25M_48M_OSC
J26
25M_X1
C31
25M_X2
C33
PCICLK0 AF3
PCICLK1/GPO36 AF1
PCICLK2/GPO37 AF5
PCICLK3/GPO38 AG2
PCICLK4/14M_OSC/GPO39 AF6
PCIRST# AB5
AD0/GPIO0 AJ3
AD1/GPIO1 AL5
AD2/GPIO2 AG4
AD3/GPIO3 AL6
AD4/GPIO4 AH3
AD5/GPIO5 AJ5
AD6/GPIO6 AL1
AD7/GPIO7 AN5
AD8/GPIO8 AN6
AD9/GPIO9 AJ1
AD10/GPIO10 AL8
AD11/GPIO11 AL3
AD12/GPIO12 AM7
AD13/GPIO13 AJ6
AD14/GPIO14 AK7
AD15/GPIO15 AN8
AD16/GPIO16 AG9
AD17/GPIO17 AM11
AD18/GPIO18 AJ10
AD19/GPIO19 AL12
AD20/GPIO20 AK11
AD21/GPIO21 AN12
AD22/GPIO22 AG12
AD23/GPIO23 AE12
AD24/GPIO24 AC12
AD25/GPIO25 AE13
AD26/GPIO26 AF13
AD27/GPIO27 AH13
AD28/GPIO28 AH14
AD29/GPIO29 AD15
AD30/GPIO30 AC15
AD31/GPIO31 AE16
CBE0# AN3
CBE1# AJ8
CBE2# AN10
CBE3# AD12
FRAME# AG10
DEVSEL# AK9
IRDY# AL10
TRDY# AF10
PAR AE10
STOP# AH1
PERR# AM9
SERR# AH8
REQ0# AG15
REQ1#/GPIO40 AG13
REQ2#/CLK_REQ8#/GPIO41 AF15
REQ3#/CLK_REQ5#/GPIO42 AM17
GNT0# AD16
GNT1#/GPO44 AD13
GNT2#/SD_LED/GPO45 AD21
GNT3#/CLK_REQ7#/GPIO46 AK17
CLKRUN# AD19
LOCK# AH9
INTE#/GPIO32 AF18
INTF#/GPIO33 AE18
INTG#/GPIO34 AC16
INTH#/GPIO35 AD18
LPCCLK0 B25
LPCCLK1 D25
LAD0 D27
LAD1 C28
LAD2 A26
LAD3 A29
LFRAME# A31
LDRQ0# B27
LDRQ1#/CLK_REQ6#/GPIO49 AE27
SERIRQ/GPIO48 AE19
DMA_ACTIVE# G25
PROCHOT# E28
APU_PG E26
LDT_STP# G26
APU_RST# F26
S5_CORE_EN H7
RTCCLK F1
INTRUDER_ALERT# F3
VDDBT_RTC_G E6
32K_X1 G2
32K_X2 G4
R831 100K_0402_5%@
1 2
![](asset-e.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB_RCOMP
USBSS_CALRP
USBSS_CALRN
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
VGA_PD
USB_OC0#
HDA_BITCLK
HDA_SYNC
HDA_SDIN0
HDA_SDIN1
HDA_SDOUT
HDA_RST#
EC_PWM2
TEST0
TEST1
TEST2
FCH_PCIE_WAKE#
USB_OC2#
EC_LID_OUT#
SYS_RESET#
APU_SID
APU_SIC
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
EC_RSMRST#
MINI1_CLKREQ#
FCH_SCLK0
FCH_SDATA0
LAN_CLKREQ#_1
EC_LID_OUT#
FCH_PCIE_WAKE#
H_THERMTRIP#
FCH_SCLK1
FCH_SDATA1
FCH_GPIO190
FCH_GPIO191
FCH_GPIO189
TEST0
TEST1
TEST2
USB30_MRX_DTX_P0
USB30_MRX_DTX_N0
USB30_MTX_DRX_P0
USB30_MTX_DRX_N0
USB_OC1#
USB20_P0
USB20_N0
USB_OC1#
USB20_P1
USB20_N1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
LAN_CLKREQ#_1
MINI1_CLKREQ#
USB_OC0#
FCH_GPIO190
FCH_GPIO191
FCH_GPIO189
USB20_N10
USB20_P10
USB_OC2#
EC_GA2036
EC_RSMRST#36
H_THERMTRIP#8
SLP_S3#36
SLP_S5#36
FCH_PWRGD36
PBTN_OUT#36
FCH_SCLK011,12,32
FCH_SDATA011,12,32
EC_SMI#36
EC_SCI#36
HDA_SYNC_AUDIO30
HDA_RST_AUDIO#30
HDA_SDIN030
HDA_SDOUT_AUDIO30
HDA_BITCLK_AUDIO30
USB_OC0#34
EC_PWM2 16
EC_KBRST#36
VGA_PD16
FCH_PCIE_WAKE#29,32,36
EC_LID_OUT#36
APU_SID 6,8
APU_SIC 6,8
USB30_MRX_DTX_N0 34
USB30_MRX_DTX_P0 34
USB30_MTX_C_DRX_N0 34
USB30_MTX_C_DRX_P0 34
USB_OC1#34
USB20_P0 34
USB20_N0 34
USB20_P1 30
USB20_N1 30
USB20_N2 27
USB20_P2 27
USB20_N3 32
USB20_P3 32
USB20_N4 31
USB20_P4 31
LAN_CLKREQ#29
MINI1_CLKREQ#32
USB20_N10 34
USB20_P10 34
USB_OC2#34
+FCH_VDD_11_SSUSB_S
+3VS
+3VALW
+3VS
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Hudson-M2/M3-ACPI/USB/EC
Custom
14 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
PCIE_RST2 : Reset PCIE device on Hudson2
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off
EHCI CTL
DEV 22, Fn 2
EHCI CTL
DEV 19, Fn 2
EHCI CTL
DEV 18, Fn 2
SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain
THERMTRIP:
Need level shift from +3VALW to +1.5V
<Disable CTL of M2>
xHCI CTL
DEV 16, Fn 1
Hudson-M2 Hudson-M3
xHCI CTL
DEV 16, Fn 0
Hudson-M2/M3
Hudson-M2/M3
Modify 20101111
For FCH internal debug use
On board
USB Conn
xHCI CTL
DEV 16, Fn 0
xHCI CTL
DEV 16, Fn 1
Hudson-M3
USB1
USB2
CMOS
WLAN(BT)
CardReder
USB3
Add Project ID Table
201011301600
GPIO189 (use VGA) L(NO)
R44
H(YES)
R43
Project SKU ID
GPIO191
GPIO190 (use PX)
L(15")
R48
H(17")
R47
L(NO)
R46
H(YES)
R45
Modify 2010212-AMD request
Modify 2010212-AMD request
Modify 2010212-AMD request
R46
8.2K_0402_5%
@
12
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
USB MISCUSB 1.1USB 2.0USB 3.0
EMBEDDED CTRL
HUDSON-2
U25D
HUDSON-M2_FCBGA656
M2@
SCL2/GPIO193 H19
SDA2/GPIO194 G19
SCL3_LV/GPIO195 G22
SDA3_LV/GPIO196 G21
EC_PWM0/EC_TIMER0/GPIO197 E22
EC_PWM1/EC_TIMER1/GPIO198 H22
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 J22
EC_PWM3/EC_TIMER3/GPIO200 H21
KSI_0/GPIO201 K21
KSI_1/GPIO202 K22
KSI_2/GPIO203 F22
KSI_3/GPIO204 F24
KSI_4/GPIO205 E24
KSI_5/GPIO206 B23
KSI_6/GPIO207 C24
KSI_7/GPIO208 F18
PS2_DAT/SDA4/GPIO187
K19
PS2_CLK/CEC/SCL4/GPIO188
J19
SPI_CS2#/GBE_STAT2/GPIO166
J21
PS2KB_DAT/GPIO189
D21
PS2KB_CLK/GPIO190
C20
PS2M_DAT/GPIO191
D23
PS2M_CLK/GPIO192
C22
KSO_0/GPIO209
F21
KSO_1/GPIO210
E20
KSO_2/GPIO211
F20
KSO_3/GPIO212
A22
KSO_4/GPIO213
E18
KSO_5/GPIO214
A20
KSO_6/GPIO215
J18
KSO_7/GPIO216
H18
KSO_8/GPIO217
G18
KSO_9/GPIO218
B21
KSO_10/GPIO219
K18
KSO_11/GPIO220
D19
KSO_12/GPIO221
A18
KSO_13/GPIO222
C18
KSO_14/GPIO223
B19
KSO_15/GPIO224
B17
KSO_16/GPIO225
A24
KSO_17/GPIO226
D17
AZ_BITCLK
AB3
AZ_SDOUT
AB1
AZ_SDIN0/GPIO167
AA2
AZ_SDIN1/GPIO168
Y5
AZ_SDIN2/GPIO169
Y3
AZ_SDIN3/GPIO170
Y1
AZ_SYNC
AD6
AZ_RST#
AE4
BLINK/USB_OC7#/GEVENT18#
M7
USB_OC6#/IR_TX1/GEVENT6#
R8
USB_OC5#/IR_TX0/GEVENT17#
T1
USB_OC4#/IR_RX0/GEVENT16#
P6
USB_OC3#/AC_PRES/TDO/GEVENT15#
F5
USB_OC2#/TCK/GEVENT14#
P5
USB_OC1#/TDI/GEVENT13#
J7
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
T8
CLK_REQ4#/SATA_IS0#/GPIO64
AG24
CLK_REQ3#/SATA_IS1#/GPIO63
AE24
SMARTVOLT1/SATA_IS2#/GPIO50
AE26
CLK_REQ0#/SATA_IS3#/GPIO60
AF22
SATA_IS4#/FANOUT3/GPIO55
AH17
SATA_IS5#/FANIN3/GPIO59
AG18
SPKR/GPIO66
AF24
SCL0/GPIO43
AD26
SDA0/GPIO47
AD25
SCL1/GPIO227
T7
SDA1/GPIO228
R7
CLK_REQ2#/FANIN4/GPIO62
AG25
CLK_REQ1#/FANOUT4/GPIO61
AG22
IR_LED#/LLB#/GPIO184
J2
SMARTVOLT2/SHUTDOWN#/GPIO51
AG26
DDR3_RST#/GEVENT7#/VGA_PD
V8
GBE_LED0/GPIO183
W8
SPI_HOLD#/GBE_LED1/GEVENT9#
Y6
GBE_LED2/GEVENT10#
V10
GBE_STAT0/GEVENT11#
AA8
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
AF25
RSMRST#
U2
TEST0
T9
TEST1/TMS
T10
TEST2
V9
GA20IN/GEVENT0#
AE22
KBRST#/GEVENT1#
AG19
LPC_PME#/GEVENT3#
R9
LPC_SMI#/GEVENT23#
C26
LPC_PD#/GEVENT5#
T5
SYS_RESET#/GEVENT19#
U4
WAKE#/GEVENT8#
K1
IR_RX1/GEVENT20#
V7
THRMTRIP#/SMBALERT#/GEVENT2#
R10
WD_PWRGD
AF19
PCIE_RST2#/PCI_PME#/GEVENT4#
AB6
RI#/GEVENT22#
R2
SPI_CS3#/GBE_STAT1/GEVENT21#
W7
SLP_S3#
T3
SLP_S5#
W2
PWR_BTN#
J4
PWR_GOOD
N7
USBCLK/14M_25M_48M_OSC G8
USB_RCOMP B9
USB_FSD1P/GPIO186 H1
USB_FSD1N H3
USB_FSD0P/GPIO185 H6
USB_FSD0N H5
USB_HSD13P H10
USB_HSD13N G10
USB_HSD12P K10
USB_HSD12N J12
USB_HSD11P G12
USB_HSD11N F12
USB_HSD10P K12
USB_HSD10N K13
USB_HSD9P B11
USB_HSD9N D11
USB_HSD8P E10
USB_HSD8N F10
USB_HSD7P C10
USB_HSD7N A10
USB_HSD6P H9
USB_HSD6N G9
USB_HSD5P A8
USB_HSD5N C8
USB_HSD4P F8
USB_HSD4N E8
USB_HSD3P C6
USB_HSD3N A6
USB_HSD2P C5
USB_HSD2N A5
USB_HSD1P C1
USB_HSD1N C3
USB_HSD0P E1
USB_HSD0N E3
USBSS_CALRP C16
USBSS_CALRN A16
USB_SS_TX3P A14
USB_SS_TX3N C14
USB_SS_RX3P C12
USB_SS_RX3N A12
USB_SS_TX2P D15
USB_SS_TX2N B15
USB_SS_RX2P E14
USB_SS_RX2N F14
USB_SS_TX1P F15
USB_SS_TX1N G15
USB_SS_RX1P H13
USB_SS_RX1N G13
USB_SS_TX0P J16
USB_SS_TX0N H16
USB_SS_RX0P J15
USB_SS_RX0N K15
R863 11.8K_0402_1%
1 2
R865 1K_0402_1%
M3@
1 2
R869 33_0402_5%
1 2
T35
R47
8.2K_0402_5%
@
12
R889 2.2K_0402_5%
@
1 2
T29
R884 2.2K_0402_5%
1 2
R877 10K_0402_5%
1 2
R45
8.2K_0402_5%
@
12
R880 2.2K_0402_5%
1 2
R888 10K_0402_5%
@
1 2
R43
8.2K_0402_5%
@
12
R81 0_0402_5%
1 2
R872 10K_0402_5%
1 2
R885 10K_0402_5%
@
1 2
R55 100K_0402_5%
1 2
R886 10K_0402_5%
@
1 2
R867 33_0402_5%
1 2
R18 10K_0402_5%
@
1 2
R871 10K_0402_5%
1 2
R882 8.2K_0402_5%
@
1 2
R881 2.2K_0402_5%
1 2
R876 2.2K_0402_5%
1 2
R44
8.2K_0402_5%
@
12
C39 0.1U_0402_16V7K
M3@
1 2
R866 33_0402_5%
1 2
R54 100K_0402_5%
1 2
R48
8.2K_0402_5%
@
12
C37 0.1U_0402_16V7K
M3@
1 2
R890 2.2K_0402_5%
@
1 2
R878 10K_0402_5%
@
1 2
R868 33_0402_5%
1 2
R862 10K_0402_5%
1 2
T31
R873 10K_0402_5%
1 2
R887 2.2K_0402_5%
@
1 2
R56 100K_0402_5%
1 2
R864 1K_0402_1%M3@
1 2
T27
R870 10K_0402_5%
1 2
R940 8.2K_0402_5%
1 2
R874 2.2K_0402_5%
1 2
![](asset-f.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GBE_MDIO
FCH_SPI_MISO
AUXCAL
GBE_PHY_INTR
FCH_SPI_MOSI
GBE_COL
GBE_CRS
GBE_RXERR
SATA_CALRP
SATA_CALRN
FCH_CRT_HPD
BT_ON
SATA_LED#
FCH_SPI_CS1#
FCH_SPI_WP#
WL_OFF#
FCH_SPI_CLK_R
FCH_SPI_WP#
FCH_SPI_MISO
FCH_SPI_CS1#
FCH_SPI_HOLD#
FCH_SPI_CLK
FCH_SPI_MOSI
FCH_CRT_HPD
FCH_SPI_CLK
GBE_COL
GBE_CRS
GBE_RXERR
GBE_MDIO
GBE_PHY_INTR
FCH_SPI_CLK
FCH_CRT_HPD 10
ML_VGA_AUXP_C 8
ML_VGA_AUXN_C 8
SATA_STX_DRX_P033
SATA_STX_DRX_N033
SATA_LED#32
FCH_CRT_R 27
FCH_CRT_G 27
FCH_CRT_B 27
FCH_CRT_HSYNC 27
FCH_CRT_VSYNC 27
FCH_CRT_DDC_SDA 27
FCH_CRT_DDC_SCL 27
ML_VGA_TXP2 8
ML_VGA_TXN2 8
ML_VGA_TXP3 8
ML_VGA_TXN3 8
SATA_DTX_C_SRX_P033
SATA_DTX_C_SRX_N033
BT_ON32
ML_VGA_TXP0 8
ML_VGA_TXN0 8
ML_VGA_TXP1 8
ML_VGA_TXN1 8
WL_OFF#32
SATA_DTX_C_SRX_P133
SATA_STX_DRX_P133
SATA_DTX_C_SRX_N133
SATA_STX_DRX_N133
+VDDAN_11_ML
+AVDD_SATA
+3VS
+FCH_VDDAN_33_DAC_R
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Hudson-M2/M3-SATA/GBE/HWM
Custom
15 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
HDD1
ODD
SYS BIOS ROM
Add SYS BIOS ROM
20101111
Change to PD 20101112
Add for EMI 201011291330
GL-02/10/2011: Please enabled integrated pull-up/pull-down and left unconnected.
C23
10P_0402_50V8J
@
1 2
R934 10K_0402_5%
@
1 2
R894 10K_0402_5%
1 2
R12 10K_0402_5%
1 2
R13 10K_0402_5%
1 2
R892 10K_0402_5%
1 2
T40
R36
10_0402_5%
@
1 2
R16 10K_0402_5%
1 2
R891 10K_0402_5%
1 2
R893 10K_0402_5%
1 2
R6 10K_0402_5%
1 2
R5 10K_0402_5%
1 2
R90410K_0402_5%
@
12
R35 0_0402_5%@
1 2
R898 150_0402_1%
1 2
R901 715_0402_1%
1 2
HUDSON-2
SERIAL ATA
SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK
HW MONITOR
U25B
HUDSON-M2_FCBGA656
M2@
SATA_TX0P
AK19
SATA_TX0N
AM19
SATA_RX0N
AL20
SATA_RX0P
AN20
SATA_TX1P
AN22
SATA_TX1N
AL22
SATA_RX1N
AH20
SATA_RX1P
AJ20
SATA_TX2P
AJ22
SATA_TX2N
AH22
SATA_RX2N
AM23
SATA_RX2P
AK23
SATA_TX3P
AH24
SATA_TX3N
AJ24
SATA_RX3N
AN24
SATA_RX3P
AL24
SATA_TX4P
AL26
SATA_TX4N
AN26
SATA_RX4N
AJ26
SATA_RX4P
AH26
SATA_TX5P
AN29
SATA_TX5N
AL28
SATA_RX5N
AK27
SATA_RX5P
AM27
NC6
AL29
NC7
AN31
NC8
AL31
NC9
AL33
NC10
AH33
NC11
AH31
NC12
AJ33
NC13
AJ31
SATA_X2
AG21
SATA_X1
AF21
SATA_CALRP
AF28
SATA_CALRN
AF27
FANOUT0/GPIO52
AH16
FANOUT1/GPIO53
AM15
FANOUT2/GPIO54
AJ16
FANIN0/GPIO56
AK15
FANIN1/GPIO57
AN16
FANIN2/GPIO58
AL16
TEMPIN0/GPIO171
K6
TEMPIN1/GPIO172
K5
TEMPIN2/GPIO173
K3
TEMPIN3/TALERT#/GPIO174
M6 NC1 AG16
NC2 AH10
NC3 A28
NC4 G27
NC5 L4
VIN0/GPIO175 N2
VIN1/GPIO176 M3
VIN2/SDATI_1/GPIO177 L2
VIN3/SDATO_1/GPIO178 N4
VIN4/SLOAD_1/GPIO179 P1
VIN5/SCLK_1/GPIO180 P3
VIN6/GBE_STAT3/GPIO181 M1
VIN7/GBE_LED3/GPIO182 M5
SD_CLK/SCLK_2/GPIO73 AL14
SD_CMD/SLOAD_2/GPIO74 AN14
SD_CD/GPIO75 AJ12
SD_WP/GPIO76 AH12
SD_DATA0/SDATI_2/GPIO77 AK13
SD_DATA1/SDATO_2/GPIO78 AM13
SD_DATA2/GPIO79 AH15
SD_DATA3/GPIO80 AJ14
GBE_COL AC4
GBE_CRS AD3
GBE_MDCK AD9
GBE_MDIO W10
GBE_RXCLK AB8
GBE_RXD3 AH7
GBE_RXD2 AF7
GBE_RXD1 AE7
GBE_RXD0 AD7
GBE_RXCTL/RXDV AG8
GBE_RXERR AD1
GBE_TXCLK AB7
GBE_TXD3 AF9
GBE_TXD2 AG6
GBE_TXD1 AE8
GBE_TXD0 AD8
GBE_TXCTL/TXEN AB9
GBE_PHY_PD AC2
GBE_PHY_RST# AA7
GBE_PHY_INTR W9
SPI_DI/GPIO164 V6
SPI_DO/GPIO163 V5
SPI_CLK/GPIO162 V3
SPI_CS1#/GPIO165 T6
ROM_RST#/SPI_WP#/GPIO161 V1
VGA_RED L30
VGA_GREEN L32
VGA_BLUE M29
VGA_DAC_RSET K31
VGA_HSYNC/GPO68 M28
VGA_VSYNC/GPO69 N30
VGA_DDC_SDA/GPO70 M33
VGA_DDC_SCL/GPO71 N32
ML_VGA_HPD/GPIO229 C29
ML_VGA_L0P T31
ML_VGA_L0N T33
ML_VGA_L1P T29
ML_VGA_L1N T28
ML_VGA_L2P R32
ML_VGA_L2N R30
ML_VGA_L3P P29
ML_VGA_L3N P28
AUXCAL U28
AUX_VGA_CH_P V28
AUX_VGA_CH_N V29
SATA_ACT#/GPIO67
AD22
R903 100_0402_1%
1 2
R935 10K_0402_5%
@
1 2
R9 10K_0402_5%
1 2
R9001K_0402_1% 12
R8991K_0402_1% 12
R11 10K_0402_5%@
1 2
R902 10K_0402_5%
1 2
R15 10K_0402_5%
1 2
R8 10K_0402_5%
1 2
C4660.1U_0402_16V4Z
@
12
R7 10K_0402_5%
1 2
R626 1K_0402_5%
@
1 2
U28
MX25L1606EM2I-12G SOP 8P
SA000041N00
@
CS#
1
SO 2
WP#
3
GND
4SI 5
SCLK 6
HOLD#
7
VCC 8
R895 10K_0402_5%
1 2
R14 10K_0402_5%
1 2
R896 150_0402_1%
1 2
R897 150_0402_1%
1 2
R10 10K_0402_5%
1 2
![](asset-10.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VGA_PD#
VGA_PD#
VGA_PD#
PCI_CLK113
PCI_CLK313
PCI_CLK413
LPC_CLK0_EC13,36
LPC_CLK113
EC_PWM214
RTC_CLK13,36
PCI_AD2713
PCI_AD2613
PCI_AD2513
PCI_AD2413
PCI_AD2313
VGA_PD14
+3VALW+3VALW+3VALW+3VALW+3VS+3VS+3VS
+3VS +FCH_VDDAN_33_DAC_R
+1.1VS +FCH_VDDAN_11_MLDAC
+3VS
+FCH_VDDAN_33_DAC
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Hudson-M2/M3-STRAP
Custom
16 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
CLKGEN
ENABLED
S5 PLUS
MODE
ENABLED
DEFAULT
CLKGEN
DISABLE
PULL
LOW
PULL
HIGH
DEFAULT
RTC_CLKLPC_CLK1
LPC ROM
SPI ROM
EC_PWM2
EC
ENABLED
EC
DISABLED
DEFAULT
PCI_CLK1
ALLOW
PCIE GEN2
PCI_CLK3
NON_FUSION
CLOCK MODE
DEFAULT
IGNORE
DEBUG
STRAP
USE
DEBUG
STRAPS
PCI_CLK4 LPC_CLK0
DEFAULT
FORCE
PCIE GEN1
FUSION
CLOCK
MODE
DEFAULT
DEFAULT
S5 PLUS
MODE
DISABLED
STRAP PINS
PCI_AD25 PCI_AD24
USE EEPROM
PCIE STRAPS
USE DEFAULT
PCIE STRAPS
DEFAULTDEFAULT
USE FC
PLL
DISABLE
ILA
AUTORUN
USE PCI
PLL
DEFAULT
BYPASS
FC PLL
PULL
HIGH
DEFAULT
BYPASS
PCI PLL
PCI_AD27PCI_AD26
PULL
LOW
DEFAULT
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD23
DEBUG STRAPS
ENABLE
ILA
AUTORUN
DISABLE PCI
MEM BOOT
ENABLE PCI
MEM BOOT
If support ML DAC power down when no VGA plug
Check VGA_PD states
AO3413 Vgs(max)=1V
VGA_PD: Support MLDAC power
save if not connect
0: MLDAC power on
1: MLDAC power off
220 ohm
220 ohm
30mil
30mil
Q40
AP2301GN-HF_SOT23-3
@
2
3 1
R914
100K_0402_5%
12
R918 10K_0402_5%
12
R912 0_0402_5%
1 2
R925
2.2K_0402_5%
1 2
C1212
1U_0402_6.3V4Z
1
2
R921 2.2K_0402_5%
@
12
R919 10K_0402_5%
12
R913 0_0402_5%
@
1 2
R906 10K_0402_5%
@
12
R905 10K_0402_5%
12
Q41A
DMN66D0LDW-7_SOT363-6
61
2
R924
0_0402_5%
@
1 2
R909 10K_0402_5%
12
L47
FBMA-L11-201209-221LMA30T_0805
1 2
R915 10K_0402_5%
@
12
C1211
1U_0402_6.3V4Z
@1
2
R922 2.2K_0402_5%
@
12
R920 10K_0402_5%
@
12
Q39
AP2301GN-HF_SOT23-3
@
2
3 1
R907 10K_0402_5%
@
12
R928 2.2K_0402_5%
@
12
R930 2.2K_0402_5%
@
12
R910 10K_0402_5%
12
R923
1K_0402_5%
@
1 2
C1210
0.1U_0402_16V4Z
1
2
R926 2.2K_0402_5%
@
12
R911 10K_0402_5%
12
L48
FBMA-L11-201209-221LMA30T_0805
@
1 2
Q41B
DMN66D0LDW-7_SOT363-6
34
5
C1209
2.2U_0603_6.3V4Z
1
2
R908 10K_0402_5%
@
12
R927 2.2K_0402_5%
@
12
R917 10K_0402_5%
12
R929 2.2K_0402_5%
@
12
R916
100K_0402_5%
12
![](asset-11.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+FCH_VDDPL_33_USB_S
+VDDPL_3.3V
+VDDPL_11_DAC_L +VDDPL_11_DAC
+VDDIO_33_S
+VDDCR_1.1V
+VDDPL_1.1V
+1.1VS_CKVDD
+PCIE_VDDR_FCH
+AVDD_SATA
+VDDXL_3.3V
+VDDCR_11_SSUSB
+VDDAN_33_USB
+FCH_VDD_11_SSUSB_S
+VDDIO_33_PCIGP
+VDDPL_33_DAC
+VDDPL_33_ML
+FCH_VDDAN_33_DAC_R
+FCH_VDDPL_33_USB_S
+VDDPL_33_PCIE
+VDDPL_33_SATA
+VDDIO_AZ
+VDDPL_33_PCIE
+VDDPL_33_SATA
+VDDCR_1.1V_USB
+VDDAN_11_USB_S
+VDDAN_SSUSB
+FCH_VDDPL_33_SSUSB_S
+FCH_VDDPL_33_SSUSB_S
+FCH_VDDPL_33_MLDAC
+VDDAN_33_HWM
+VDDAN_33_USB
+3VS
+FCH_VDDAN_11_MLDAC
+3VALW
+1.1VALW
+1.1VS
+1.1VS
+1.1VS
+PCIE_VDDR_FCH
+3VALW
+3VALW
+FCH_VDDPL_33_MLDAC
+VDDPL_3.3V
+1.1VALW
+3VS
+3VS
+3VS
+1.1VALW
+1.1VALW
+1.1VS_CKVDD
+3VALW
+1.1VALW
+FCH_VDDAN_33_DAC_R
+VCC_FCH_R
+3VS
+AVDD_SATA
+FCH_VDD_11_SSUSB_S
+VDDAN_11_ML
+3VS
+3VALW
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Hudson-M2/M3-POWER/GND
Custom
17 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
187mA
70mA
12mA
131mA
200mA
17mA
20mA
93mA
1007mA
1088mA
1337mA
59mA
197mA
LDO_CAP: Internally generated 1.8V
supply for the RGB outputs For A11: Cap = 1nF
For A12, Cap = DNI
VDDPL_33_SSUSB_S
For Hudson3 USB3.0 only
For Hudson2, connect to GND
AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.
220 ohm
220 ohm
220 ohm
220 ohm
220 ohm/2A
658mA
220 ohm
220 ohm
42 ohm/4A
220 ohm
220 ohm
VDDIO_AZ_S should be tied to
+3.3/1.5V_S5 rail if Wake on Ring
is supported
43mA
7mA
226mA
140mA
282mA
424mA
340mA
5mA
26mA
Connected to VSS through a dedicated via.
220 ohm
220 ohm/2A
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
20mils
30mils
10mils
10mils
20mils
30mils
10mils
10mils
10mils
10mils
10mils
10mils
60mils
50mils
20mils
50mils
40mils
For FCH M2 - BOM option
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S
Connected to VSS.
20mA
47mA
20mA
C1218 / C1219 / C1247 Change to SE00000I10
20101228
Change to 0ohm-AMD request
20110212
change to four 1uf-AMD request
20110212
R1242 change to 2.2uf-AMD request
20110212
C1472
2.2U_0603_6.3V4Z
1
2
R941
0_0805_5%
1 2
C1277 .1U_0402_16V7K
1 2
R936 0_0402_5%M2@ 12
C1236
.1U_0402_16V7K
1
2
L22
MBK1608221YZF_2P
1 2
C1271
2.2U_0603_6.3V4Z
1
2
R28
0_0402_5%
1 2
C1278
10U_0603_6.3V6M
M3@
1
2
R1145
0_0603_5%
1 2
C1280
.1U_0402_16V7K
M3@
1
2
C1250
1U_0402_6.3V6K
1
2
C1282
1U_0402_6.3V6K
1
2
C1235
.1U_0402_16V7K
1
2
C1223
1U_0402_6.3V6K
1
2
C1268
2.2U_0603_6.3V4Z
1
2
C1221
.1U_0402_16V7K
1
2
R938
0_0805_5%
1 2
C1281
.1U_0402_16V7K
M3@
1
2
C1220
.1U_0402_16V7K
1
2
L4
MBK1608221YZF_2P
@1 2
L57
MBK1608221YZF_2P
1 2
HUDSON-2
GROUND
U25E
HUDSON-M2_FCBGA656
M2@
VSS
A3
VSS
A33
VSS
B7
VSS
B13
VSS
D9
VSS
D13
VSS
E5
VSS
E12
VSS
E16
VSS
E29
VSS
F7
VSS
F9
VSS
F11
VSS
F13
VSS
F16
VSS
F17
VSS
F19
VSS
F23
VSS
F25
VSS
F29
VSS
G6
VSS
G16
VSS
G32
VSS
H12
VSS
H15
VSS
H29
VSS
J6
VSS
J9
VSS
J10
VSS
J13
VSS
J28
VSS
J32
VSS
K7
VSS
K16
VSS
K27
VSS
K28
VSS
L6
VSS
L12
VSS
L13
VSS
L15
VSS
L16
VSS
L21
VSS
M13
VSS
M16
VSS
M21
VSS
M25
VSS
N6
VSS
N11
VSS
N13
VSS
N23
VSS
N24
VSS
P12
VSS
P18
VSS
P20
VSS
P21
VSS
P31
VSS
P33
VSS
R4
VSS
R11
VSS
R25
VSS
R28
VSS
T11
VSS
T16
VSS
T18
VSSAN_HWM
N8
VSSXL
K25
VSSPL_SYS
H25
VSS T25
VSS T27
VSS U6
VSS U14
VSS U17
VSS U20
VSS U21
VSS U30
VSS U32
VSS V11
VSS V16
VSS V18
VSS W4
VSS W6
VSS W25
VSS W28
VSS Y14
VSS Y16
VSS Y18
VSS AA6
VSS AA12
VSS AA13
VSS AA14
VSS AA16
VSS AA17
VSS AA25
VSS AA28
VSS AA30
VSS AA32
VSS AB25
VSS AC6
VSS AC18
VSS AC28
VSS AD27
VSS AE6
VSS AE15
VSS AE21
VSS AE28
VSS AF8
VSS AF12
VSS AF16
VSS AF33
VSS AG30
VSS AG32
VSS AH5
VSS AH11
VSS AH18
VSS AH19
VSS AH21
VSS AH23
VSS AH25
VSS AH27
VSS AJ18
VSS AJ28
VSS AJ29
VSS AK21
VSS AK25
VSS AL18
VSS AM21
VSS AM25
VSS AN1
VSS AN18
VSS AN28
VSS AN33
VSSPL_DAC T21
VSSAN_DAC L28
VSSANQ_DAC K33
VSSIO_DAC N28
EFUSE R6
C1256
10U_0603_6.3V6M
1
2
C1255
10U_0603_6.3V6M
1
2
C1270
.1U_0402_16V7K
1
2
C1230
2.2U_0603_6.3V4Z
1
2
R945 0_0402_5%
1 2
2 1
C1281
0_0402_5%
M2@
C1225
.1U_0402_16V7K
1
2
C1260
.1U_0402_16V7K
1
2
C1473
.1U_0402_16V7K
1
2
C1231
.1U_0402_16V7K
1
2
L6
MBK1608221YZF_2P
M3@
1 2
L15
MBK1608221YZF_2P
1 2
C1217
2.2U_0603_6.3V4Z
1
2
L28
MBK1608221YZF_2P
1 2
C1272
.1U_0402_16V7K
1
2
C1276 2.2U_0603_6.3V4Z
1 2
C1265
2.2U_0603_6.3V4Z
1
2
C1242
2.2U_0603_6.3V4Z
1
2
C1240
4.7U_0603_6.3V6K
1
2
C1263
.1U_0402_16V7K
1
2
L54
FBMA-L11-201209-221LMA30T_0805
1 2
C1264
1U_0402_6.3V6K
1
2
C1239
.1U_0402_16V7K
M3@
1
2
C1257
.1U_0402_16V7K
1
2
C1214
1U_0402_6.3V6K
1
2
C1258
2.2U_0603_6.3V4Z
1
2
C1252
1U_0402_6.3V6K
1
2
C1248
2.2U_0603_6.3V4Z
1
2
C1224
1U_0402_6.3V6K
1
2
C1237
2.2U_0603_6.3V4Z
1
2
C1274
.1U_0402_16V7K
M3@
1
2
C1269
.1U_0402_16V7K
1
2
L3
MBK1608221YZF_2P
1 2
C1275
.1U_0402_16V7K
M3@
1
2
C1249
.1U_0402_16V7K
1
2
R1148
0_0603_5%
1 2
R27
0_0402_5%
1 2
C1254
1U_0402_6.3V6K
1
2
R937
0_0805_5%
1 2
C1222
2.2U_0603_6.3V4Z
1
2
C1247
22U_0805_6.3V6M
1
2
C1215
.1U_0402_16V7K
1
2
C1234
1U_0402_6.3V6K
1
2
C1218
22U_0805_6.3V6M
1
2
R24 0_0402_5%
1 2
C1246
.1U_0402_16V7K
1
2
L61
FBMA-L11-201209-221LMA30T_0805
M3@ 12
R19
0_0603_5%
1 2
L59
MBK1608221YZF_2P
1 2
C1233
1U_0402_6.3V6K
1
2
C1243
1U_0402_6.3V6K
1
2
HUDSON-2
CORE S0
PCI/GPIO I/O
CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O
USB SS USB MAIN LINKGBE LAN
POWER
U25C
HUDSON-M2_FCBGA656
M2@
VDDCR_11_1 T14
VDDCR_11_2 T17
VDDCR_11_3 T20
VDDCR_11_4 U16
VDDCR_11_5 U18
VDDCR_11_6 V14
VDDCR_11_7 V17
VDDCR_11_8 V20
VDDCR_11_9 Y17
VDDAN_11_CLK_1 H26
VDDAN_11_CLK_2 J25
VDDAN_11_CLK_3 K24
VDDAN_11_CLK_4 L22
VDDAN_11_CLK_5 M22
VDDAN_11_CLK_6 N21
VDDAN_11_CLK_7 N22
VDDAN_11_CLK_8 P22
VDDAN_11_PCIE_1 AB24
VDDAN_11_PCIE_2 Y21
VDDAN_11_PCIE_3 AE25
VDDAN_11_PCIE_4 AD24
VDDAN_11_PCIE_5 AB23
VDDAN_11_PCIE_6 AA22
VDDAN_11_PCIE_7 AF26
VDDAN_11_PCIE_8 AG27
VDDAN_11_SATA_1 AA21
VDDAN_11_SATA_4 Y20
VDDAN_11_SATA_2 AB21
VDDAN_11_SATA_3 AB22
VDDAN_11_SATA_5 AC22
VDDAN_11_SATA_6 AC21
VDDAN_11_SATA_7 AA20
VDDAN_11_SATA_8 AA18
VDDAN_11_SATA_9 AB20
VDDAN_11_SATA_10 AC19
VDDIO_33_S_1 N18
VDDIO_33_S_2 L19
VDDIO_33_S_3 M18
VDDIO_33_S_4 V12
VDDIO_33_S_5 V13
VDDIO_33_S_6 Y12
VDDIO_33_S_7 Y13
VDDIO_33_S_8 W11
VDDXL_33_S G24
VDDCR_11_S_1 N20
VDDCR_11_S_2 M20
VDDPL_11_SYS_S J24
VDDAN_33_HWM_S M8
VDDIO_AZ_S AA4
VDDCR_11_SSUSB_S_1
N16
VDDCR_11_SSUSB_S_2
N17
VDDCR_11_SSUSB_S_3
P17
VDDCR_11_SSUSB_S_4
M17
VDDAN_11_SSUSB_S_1
P16
VDDAN_11_SSUSB_S_2
M14
VDDAN_11_SSUSB_S_3
N14
VDDAN_11_SSUSB_S_4
P13
VDDAN_11_SSUSB_S_5
P14
VDDCR_11_USB_S_1
T12
VDDCR_11_USB_S_2
T13
VDDAN_11_USB_S_1
U12
VDDAN_11_USB_S_2
U13
VDDAN_33_USB_S_1
G7
VDDAN_33_USB_S_2
H8
VDDAN_33_USB_S_3
J8
VDDAN_33_USB_S_4
K8
VDDAN_33_USB_S_5
K9
VDDAN_33_USB_S_6
M9
VDDAN_33_USB_S_7
M10
VDDAN_33_USB_S_8
N9
VDDAN_33_USB_S_9
N10
VDDAN_33_USB_S_10
M12
VDDAN_33_USB_S_11
N12
VDDAN_33_USB_S_12
M11
VDDAN_11_ML_1
Y22
VDDAN_11_ML_2
V23
VDDAN_11_ML_3
V24
VDDAN_11_ML_4
V25
VDDIO_33_GBE_S
AB10
VDDIO_GBE_S_1
AA9
VDDIO_GBE_S_2
AA10
VDDCR_11_GBE_S_1
AB11
VDDCR_11_GBE_S_2
AA11
VDDIO_33_PCIGP_1
AB17
VDDIO_33_PCIGP_2
AB18
VDDIO_33_PCIGP_3
AE9
VDDIO_33_PCIGP_4
AD10
VDDIO_33_PCIGP_5
AG7
VDDIO_33_PCIGP_6
AC13
VDDIO_33_PCIGP_7
AB12
VDDIO_33_PCIGP_8
AB13
VDDIO_33_PCIGP_9
AB14
VDDIO_33_PCIGP_10
AB16
VDDPL_33_SYS
H24
VDDPL_33_DAC
V22
VDDPL_33_ML
U22
VDDAN_33_DAC
T22
VDDPL_33_SSUSB_S
L18
VDDPL_33_USB_S
D7
VDDPL_33_PCIE
AH29
VDDPL_33_SATA
AG28
LDO_CAP
M31
VDDPL_11_DAC
V21
R1149 0_0603_5%
M3@
1 2
C1232 2.2U_0603_6.3V4Z
@
1 2
C1226
.1U_0402_16V7K
1
2
L24
MBK1608221YZF_2P
1 2
C1241
.1U_0402_16V7K
1
2
L29
MBK1608221YZF_2P
1 2
C1266
2.2U_0603_6.3V4Z
1
2
R20
0_0603_5%
1 2
L7
0_0603_5%
1 2
R22 0_0402_5%
1 2
R1150 0_0603_5%
M3@
1 2
C1267
.1U_0402_16V7K
1
2
C1244
1U_0402_6.3V6K
1
2
C1219
22U_0805_6.3V6M
1
2
C1253
1U_0402_6.3V6K
1
2
C1261
2.2U_0603_6.3V4Z
1
2
C1238
2.2U_0603_6.3V4Z
M3@
1
2
R25
0_0603_5%
1 2
2 1
C1275
0_0402_5%
M2@
C1245
.1U_0402_16V7K
1
2
C1229
.1U_0402_16V7K
1
2
C1259
.1U_0402_16V7K
1
2
R26
0_0402_5%
1 2
C1228
.1U_0402_16V7K
1
2
C1262
2.2U_0603_6.3V4Z
1
2
C1273
1U_0402_6.3V6K
M3@
1
2
C1251
1U_0402_6.3V6K
1
2
R23 0_0402_5%
1 2
C1279
1U_0402_6.3V6K
M3@
1
2
C1213
1U_0402_6.3V6K
1
2
C1216
.1U_0402_16V7K
1
2
C1227
2.2U_0603_6.3V4Z
1
2
![](asset-12.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VGA_RST#
VGA_PCIE_CALRP
VGA_PCIE_CALRN
PCIE_GTX_C_FRX_N[0..7]
PCIE_GTX_C_FRX_P[0..7]
PCIE_FTX_C_GRX_N[0..7]
PCIE_FTX_C_GRX_P[0..7]
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P1
PCIE_GTX_FRX_N1
PCIE_GTX_FRX_P1
PCIE_GTX_FRX_N7 PCIE_GTX_C_FRX_N7
PCIE_GTX_C_FRX_P7PCIE_GTX_FRX_P7
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P3PCIE_GTX_FRX_P3
PCIE_GTX_FRX_N3
PCIE_GTX_FRX_N5 PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P5PCIE_GTX_FRX_P5
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P0PCIE_GTX_FRX_P0
PCIE_GTX_FRX_N0
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P6
PCIE_GTX_FRX_N6
PCIE_GTX_FRX_P6
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P2
PCIE_GTX_FRX_N2
PCIE_GTX_FRX_P2
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P4PCIE_GTX_FRX_P4
PCIE_GTX_FRX_N4
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_N7
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P2
VGA_RST#
CLK_PEG_VGA13
CLK_PEG_VGA#13
PCIE_GTX_C_FRX_N[0..7] 6
PCIE_GTX_C_FRX_P[0..7] 6
PCIE_FTX_C_GRX_P[0..7]6
PCIE_FTX_C_GRX_N[0..7]6
PE_GPIO013
PLT_RST#13,26,29,32
+1.0VSG
+3VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Vancouver_ PCIE / LVDS
Custom
18 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
GFX PCIE LANE REVERSAL
<VARY_BL>
LCD PWM (pulse width modulated)
output to adjust LCD brightness
Active High ,external PD need
<DIGON>
Controls panel digital power on/off.
Active High ,external PD need
For UMA Mux.
C288 0.1U_0402_16V7K
VGA@
1 2
C580 0.1U_0402_16V7K
VGA@
1 2
C316 0.1U_0402_16V7K
VGA@
1 2
R159 0_0402_5%
@
1 2
R387 10K_0402_5%VGA@
1 2
C473 0.1U_0402_16V7K
VGA@
1 2
R386 10K_0402_5%VGA@
1 2
C224 0.1U_0402_16V7K
VGA@
1 2
U21
NC7SZ08P5X_NL_SC70-5
VGA@
B
2
A
1Y4
P5
G
3
C291 0.1U_0402_16V7K
VGA@
1 2
PCI EXPRESS INTERFACE
CLOCK
CALIBRATION
U8A
2160809000A11SEYMOU_FCBGA962
VGA@
PW RGOOD
AH16 PCIE_CALRN Y29
PCIE_CALRP Y30
PCIE_REFCLKN
AA36 PCIE_REFCLKP
AB35
PCIE_RX0N
Y37 PCIE_RX0P
AA38
PCIE_RX10N
K37 PCIE_RX10P
L38
PCIE_RX11N
J36 PCIE_RX11P
K35
PCIE_RX12N
H37 PCIE_RX12P
J38
PCIE_RX13N
G36 PCIE_RX13P
H35
PCIE_RX14N
F37 PCIE_RX14P
G38
PCIE_RX15N
E37 PCIE_RX15P
F35
PCIE_RX1N
W36 PCIE_RX1P
Y35
PCIE_RX2N
V37 PCIE_RX2P
W38
PCIE_RX3N
U36 PCIE_RX3P
V35
PCIE_RX4N
T37 PCIE_RX4P
U38
PCIE_RX5N
R36 PCIE_RX5P
T35
PCIE_RX6N
P37 PCIE_RX6P
R38
PCIE_RX7N
N36 PCIE_RX7P
P35
PCIE_RX8N
M37 PCIE_RX8P
N38
PCIE_RX9N
L36 PCIE_RX9P
M35
PERSTB
AA30
PCIE_TX0N Y32
PCIE_TX0P Y33
PCIE_TX10N L32
PCIE_TX10P L33
PCIE_TX11N L29
PCIE_TX11P L30
PCIE_TX12N K32
PCIE_TX12P K33
PCIE_TX13N J32
PCIE_TX13P J33
PCIE_TX14N K29
PCIE_TX14P K30
PCIE_TX15N H32
PCIE_TX15P H33
PCIE_TX1N W32
PCIE_TX1P W33
PCIE_TX2N U32
PCIE_TX2P U33
PCIE_TX3N U29
PCIE_TX3P U30
PCIE_TX4N T32
PCIE_TX4P T33
PCIE_TX5N T29
PCIE_TX5P T30
PCIE_TX6N P32
PCIE_TX6P P33
PCIE_TX7N P29
PCIE_TX7P P30
PCIE_TX8N N32
PCIE_TX8P N33
PCIE_TX9N N29
PCIE_TX9P N30
C287 0.1U_0402_16V7K
VGA@
1 2
R388 1.27K_0402_1%
VGA@
1 2
R394
2.2K_0402_5%
@
12
R389 10K_0402_5%VGA@
12
C572 0.1U_0402_16V7K
VGA@
1 2
C295 0.1U_0402_16V7K
VGA@
1 2
C576 0.1U_0402_16V7K
VGA@
1 2
C472 0.1U_0402_16V7K
VGA@
1 2
C228 0.1U_0402_16V7K
VGA@
1 2
C579 0.1U_0402_16V7K
VGA@
1 2
C468 0.1U_0402_16V7K
VGA@
1 2
C247 0.1U_0402_16V7K
VGA@
1 2
LVTMDP
LVDS CONTROL
2160809000A11SEYMOU_FCBGA962
U8G
VGA@
DIGON AJ27
TXCLK_LN_DPE3N AR34
TXCLK_LP_DPE3P AP34
TXCLK_UN_DPF3N AL36
TXCLK_UP_DPF3P AK35
TXOUT_L0N_DPE2N AU35
TXOUT_L0P_DPE2P AW 37
TXOUT_L1N_DPE1N AU39
TXOUT_L1P_DPE1P AR37
TXOUT_L2N_DPE0N AR35
TXOUT_L2P_DPE0P AP35
TXOUT_L3N AP37
TXOUT_L3P AN36
TXOUT_U0N_DPF2N AK37
TXOUT_U0P_DPF2P AJ38
TXOUT_U1N_DPF1N AJ36
TXOUT_U1P_DPF1P AH35
TXOUT_U2N_DPF0N AH37
TXOUT_U2P_DPF0P AG38
TXOUT_U3N AG36
TXOUT_U3P AF35
VARY_BL AK27
R390 2K_0402_1%
VGA@
1 2
C242 0.1U_0402_16V7K
VGA@
1 2
![](asset-13.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
XTALOUT
27MCLK
XO_IN2
+VDD2DI
+VDD1DI
VSS2DI
+A2VDDQ
VSYNC
HSYNC
+AVDD
+A2VDD
XO_IN
VGA_GPIO1
VGA_GPIO2
THM_ALERT#
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
+DPLL_PVDD
+VGA_VREF
GPIO_22_ROMCSB
GPU_VID0
VGA_GPIO0
GPU_VID1
+DPLL_VDDC
VRAM_ID3
VRAM_ID1
VRAM_ID2
VRAM_ID0
+TSVDD
+VDD1DI
GPU_THERM_D+ VGA_SMB_DA2
GPU_THERM_D-
VGA_SMB_CK2
THM_ALERT#
SM_DA2
SM_CK2
EC_SMB_DA2
EC_SMB_CK2
VSYNC
HSYNC
VGA_GPIO3
VGA_GPIO4
VGA_ENBKL
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
GPIO_22_ROMCSB
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VRAM_ID1
VRAM_ID2
VRAM_ID3
VRAM_ID0
XTALOUT 27MCLK
VGA_SMB_CK2
VGA_SMB_DA2
VGA_GPIO4
VGA_GPIO3
SM_CK2
SM_DA2
GPU_THERM_D+
GPU_THERM_D-
GPU_THERM_D+_R
GPU_THERM_D-_R
GPU_VID048
GPU_VID148
EC_SMB_CK2 6,36
EC_SMB_DA2 6,36
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.0VSG
+1.8VSG
+3VSG
+1.8VSG
+3VSG
+3VSG
+3VSG
+3VSG
+3VSG
+3VSG
+1.8VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QBL60 LA-7552P
1.0
Vancouver_Strape/DP/HDMI//CRT
Custom
19 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
100mA
70mA
100mA
100mA
75mA
125mA
20mA
2mA
10mil
NC on Park,
Robson and Seymour
Not share via for other GND
NC on Park,
Robson and Seymour
10mil
10mil
10mil
10mil
10mil
SM010030010
200ma 120ohm@100mhz DCR 0.2
20mil
20mil
20mil
SM010030010
200ma 120ohm@100mhz DCR 0.2
(GENLK_VSYNC)
DNI
1: VHAD_0 to determine whether or not a VIP slave device
VGA_DIS
BIF_GEN2_EN GPIO2 0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
5.0 GT/s capability will be controlled by software
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
GPIO11
GPIO12
GPIO13 GPIO13,12,11 (config 2,1,0) : (Internal PD)
VIP_DEVICE_EN
1
1
VIP Device Strap Enable indicates to the software driver (Internal PD)
Strap Name Pin Straps description <all internal PD>
001
BIOS_ROM_EN
Setting
GPIO22 Enable external BIOS ROM device (Internal PD)
0: Diable, 1: Enable
00: No audio function; 10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0
0: Driver would ignore the value sampled on VHAD_0 during reset
a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.
b) If BIOS_ROM_EN = 0, then Config[2:0] defines
the primary memory aperture size.
AUD[1]
AUD(0)
memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010
HSYNC
VSYNC
GPIO9
00
VGA Disable determines (Internal PD)
V2SYNC
CONFIG[2]
0: VGA Controller capacity enabled
CONFIG[1]
1: The device will not be recognized as the system’s VGA controller
CONFIG[0]
RESERVED
TX_PWRS_ENB GPIO0 Transmitter Power Saving Enable (Internal PD)
0: 50% Tx output swing
1: full Tx output swing
H2SYNC
GPIO8
0
GPIO21
Internal use only. THIS PAD HAS AN INTERNAL
PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected
Don't have this strap on
Whistler and Seymour
(GENLK_CLK)
GPIO1
TX_DEEMPH_EN PCI Express Transmitter De-emphasis Enable (Internal PD)
0: Tx de-emphasis diabled
1: Tx de-emphasis enabled
NC on Park,
Robson and Seymour
NC on Park,
Robson and Seymour
AMD ref:470ohm/1A
AMD ref:470ohm/1A
NC on Park,
Robson and Seymour
AMD ref:120ohm/0.3A
AMD ref:120ohm/0.3A
NC on Whistler
and Seymour
Whistler and Seymour
Except A2VSSQ change to TSVSSQ,
others are NC
NC on Park, Robson
120ohm/0.3A
Global Swap Lock on
Multiple GPUs
Back compatibility(Manhattan)
Future ASIC call MLPS
OLD ASIC is Fan PWM
Move to
DDCCLK_AUX3P,DDCDATA_AUX3N,
0
1
External VGA Thermal Sensor
HSYNC:VSYNC
11: Audio for both DisplayPort and HDMI
AUD Strap
GPIO8 Serial-ROM output from ROM.
GPIO9 Serial-ROM input to ROM.
GPIO10 Serial-ROM clock to ROM.
GPIO22 erternal BIOS-ROM enable
if GPIO22 Low ,GPIO 11-13->CFG[0:2]
Config Primary memory-aperture size
CFG[3:0]
128MB 000
256MB 001 *
64MB 010
GPIO8,GPIO9,GPIO10 no use can NC
GPIO22
Enable need 3K PH ,no use must NC
if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
GPIO5 fast-power reduction:
HW control will casue display disturb
should use SW method control
GPIO6 voltage control signal ,No use can NC
Critical temperature fault
if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
Stereo Sync
no use can NC
Thermal monitor interrupt
Internal Debug
no use can floating
ON(1)/OFF(0)
GPIO6,15,16,20
Voltage control signal
GPIO6,15 no use can NC
For ATI Cross fire
no use can NC
External BIOS device
ON(1)/OFF(0) inter PD
GPIO7 Controls backlight on/off.
Active High ,need external PD
Reserved
ROM
1
1
VRAM_ID2 VRAM_ID1 VRAM_ID0
VRAM
Samsung 0 0
Location VRAM_ID3
00
1
0
SA00004GS30 64M16x8
K4W1G1646G-BC11
Hynix
Hynix
SA000041S60 64M16x8
H5TQ1G63DFR-11C
SA00003YO30 128M16x8
H5TQ2G63BFR-11C
0
0
0
Samsung
0 0
10
0
SA000047QA0 128M16x8
K4W2G1646C-HC11
Y3
27MHZ_16PF_X5H027000FG1H
VGA@
2 1
R83 0_0402_5%VGA@
1 2
R409 3K_0402_5%@
1 2
R408 10K_0402_5%@
1 2
R414 499_0402_1%
VGA@
1 2
C330
0.1U_0402_16V4Z
VGA@
1
2
R393
4.7K_0402_5%
VGA@
1 2
T18
R429
10K_0402_5%
X76@
12
R426
10K_0402_5%
X76@
12
R443
0_0402_5%
@
12
R70 0_0402_5%@
1 2
L11
BLM18AG121SN1D_0603
VGA@
12
C329
1U_0402_6.3V6K
VGA@
1
2
R82
0_0402_5%
@
1 2
C350
10U_0603_6.3V6M
VGA@
1
2
R431 249_0402_1%VGA@
1 2
T34
T33
C353
15P_0402_50V8J
VGA@
1
2
T30
C331
22U_0805_6.3V6M
VGA@
1
2
C343
0.1U_0402_16V4Z
@
1
2
R406 10K_0402_5%@
1 2
Q8A DMN66D0LDW-7_SOT363-6
VGA@
61
2
R417 10K_0402_5%@
1 2
R435
10K_0402_5%
X76@
12
R444
0_0402_5%
@
1 2
L8
BLM18AG121SN1D_0603
VGA@
12
L10
BLM18AG121SN1D_0603
VGA@
12
R79 0_0402_5%VGA@
1 2
C340
0.1U_0402_16V4Z
VGA@
1
2
R427
10K_0402_5%
X76@
12
U9
ADM1032ARMZ-2REEL_MSOP8
VGA@
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
L12
BLM18AG121SN1D_0603
VGA@
12
R436 715_0402_1%VGA@
1 2
C324
0.1U_0402_16V4Z
VGA@
1
2
R434
10K_0402_5%
X76@
12
R405 10K_0402_5%VGA@
1 2
R256 0_0402_5%@
1 2
C347
1U_0402_6.3V6K
VGA@
1
2
C344
10U_0603_6.3V6M
@
1
2
R445 1M_0402_5%
VGA@
12
R396 10K_0402_5%VGA@
1 2
R430 499_0402_1%VGA@
1 2
C335 0.1U_0402_16V4Z
VGA@
1 2
C333
0.1U_0402_16V4Z
VGA@
1
2
R397 10K_0402_5%VGA@
1 2
C342
1U_0402_6.3V6K
@
1
2
C325
2200P_0402_50V7K
VGA@
1 2
C334
10U_0603_6.3V6M
VGA@
1
2
R401 10K_0402_5%@
1 2
R398 10K_0402_5%@
1 2
R84 0_0402_5%VGA@
1 2
R209 0_0402_5%@
1 2
C345
10U_0603_6.3V6M
VGA@
1
2
R392
4.7K_0402_5%
VGA@
1 2
R432
10K_0402_5%
X76@
12
R433
10K_0402_5%
X76@
12
R80
0_0402_5%
@
1 2
R418 10K_0402_5%@
1 2
C351
1U_0402_6.3V6K
VGA@
1
2
T2
R413 10K_0402_5%
VGA@
12
R77 0_0402_5%@
1 2
C346
0.1U_0402_16V4Z
VGA@
1
2
L9
BLM18AG121SN1D_0603
VGA@
12
T3
R391 4.7K_0402_5%VGA@
1 2
T17
R428
10K_0402_5%
X76@
12
R78 0_0402_5%VGA@
1 2
T32
R395 10K_0402_5%VGA@
1 2
C352
0.1U_0402_16V4Z
VGA@
1
2
Q8B DMN66D0LDW-7_SOT363-6
VGA@
34
5
C339
10U_0603_6.3V6M
VGA@
1
2
C332
1U_0402_6.3V6K
VGA@
1
2
DPA
DPB
DPC
DPD
MUTI GFX
I2C
GENERAL PURPOSE I/O
DAC1
DAC2
DDC/AUX
THERMAL
PLL/CLOCK
2160809000A11SEYMOU_FCBGA962
U8B
VGA@
DMINUS
AG29
DPLL_PVDD
AM32
DPLL_PVSS
AN32
DPLL_VDDC
AN31
DPLUS
AF29
NC_DVPCLK
AR1
NC_DVPCNTL_0
AP8
NC_DVPCNTL_1
AW8
NC_DVPCNTL_2
AR3
NC_DVPCNTL_MVP_0
AR8
NC_DVPCNTL_MVP_1
AU8
DVPDATA_0
AU1
DVPDATA_1
AU3
DVPDATA_10
AV7
DVPDATA_11
AN7
DVPDATA_12
AV9
DVPDATA_13
AT9
DVPDATA_14
AR10
DVPDATA_15
AW10
DVPDATA_16
AU10
NC_DVPDATA_17
AP10
NC_DVPDATA_18
AV11
NC_DVPDATA_19
AT11
DVPDATA_2
AW3
NC_DVPDATA_20
AR12
NC_DVPDATA_21
AW12
NC_DVPDATA_22
AU12
NC_DVPDATA_23
AP12
DVPDATA_3
AP6
DVPDATA_4
AW5
DVPDATA_5
AU5
DVPDATA_6
AR6
DVPDATA_7
AW6
DVPDATA_8
AU6
DVPDATA_9
AT7
GENERICA
AJ19
GENERICB
AK19
GENERICC
AJ20
GENERICD
AK20
GENERICE_HPD4
AJ24
NC_GENERICF_HPD5
AH26
NC_GENERICG_HPD6
AH24
GPIO_0
AH20
GPIO_1
AH18
GPIO_10_ROMSCK
AJ16
GPIO_11
AK16
GPIO_12
AL16
GPIO_13
AM16
GPIO_14_HPD2
AM14
GPIO_15_PWRCNTL_0
AM13
GPIO_16
AK14
GPIO_17_THERMAL_INT
AG30
GPIO_18_HPD3
AN14
GPIO_19_CTF
AM17
GPIO_2
AN16
GPIO_20_PWRCNTL_1
AL13
GPIO_21_BB_EN
AJ14
GPIO_22_ROMCSB
AK13
GPIO_23_CLKREQB
AN13
GPIO_3_SMBDATA
AH23
GPIO_4_SMBCLK
AJ23
GPIO_5_AC_BATT
AH17
GPIO_6
AJ17
GPIO_7_BLON
AK17
GPIO_8_ROMSO
AJ13
GPIO_9_ROMSI
AH15
H2SYNC/GENLK_CLK AD29
HPD1
AK24
HSYNC AC36
JTAG_TCK
AK23 JTAG_TDI
AN23
JTAG_TDO
AM24 JTAG_TMS
AL24
JTAG_TRSTB
AM23
NC_DDCDATA_AUX7N AK29
NC_DDCCLK_AUX7P AK30
TS_FDO
AK32
TSVDD
AJ32
TSVSS
AJ33
VREFG
AH13
VSS1DI AC34
VSS2DI/NC AG32
XTALIN
AV33
XTALOUT
AU34
A2VDD/NC AG33
A2VDDQ/NC AD33
A2VSSQ/TSVSSQ AF33
AUX1N AL27
AUX1P AM27
AUX2N AM20
AUX2P AN20
AVDD AD34
AVSSQ AE34
BAF37
B2/NC AF30
B2B/NC AF31
BB AE38
C/NC AC32
COMP/NC AF32
DDC1CLK AM26
DDC1DATA AN26
DDC2CLK AM19
DDC2DATA AL19
DDC6CLK AJ30
DDC6DATA AJ31
DDCDATA_AUX3N AM30
DDCCLK_AUX3P AL30
NC_DDCDATA_AUX4N AM29
NC_DDCCLK_AUX4P AL29
DDCDATA_AUX5N AM21
DDCCLK_AUX5P AN21
GAE36
G2/NC AD30
G2B/NC AD31
GB AD35
RAD39
R2/NC AC30
R2B/NC AC31
R2SET/NC AA29
RB AD37
RSET AB34
SCL
AK26
SDA
AJ26
TX0M_DPA2N AR24
TX0M_DPC2N AR14
TX0P_DPA2P AT25
TX0P_DPC2P AT15
TX1M_DPA1N AV25
TX1M_DPC1N AV15
TX1P_DPA1P AU26
TX1P_DPC1P AU16
TX2M_DPA0N AR26
TX2M_DPC0N AR16
TX2P_DPA0P AT27
TX2P_DPC0P AT17
TX3M_DPB2N AU30
NC_TX3M_DPD2N AR20
TX3P_DPB2P AV31
NC_TX3P_DPD2P AT21
TX4M_DPB1N AT31
NC_TX4M_DPD1N AV21
TX4P_DPB1P AR32
NC_TX4P_DPD1P AU22
TX5M_DPB0N AU32
NC_TX5M_DPD0N AR22
TX5P_DPB0P AT33
NC_TX5P_DPD0P AT23
TXCAM_DPA3N AV23
TXCAP_DPA3P AU24
TXCBM_DPB3N AT29
TXCBP_DPB3P AR30
TXCCM_DPC3N AV13
TXCCP_DPC3P AU14
NC_TXCDM_DPD3N AT19
NC_TXCDP_DPD3P AU20
V2SYNC/GENLK_VSYNC AC29
VDD1DI AC33
VDD2DI/NC AG31
VSYNC AC38
Y/NC AD32
TS_A/NC
AL31
XO_IN
AW34
XO_IN2
AW35
SWAPLOCKA
AJ21
SWAPLOCKB
AK21
C354
12P_0402_50V8J
VGA@
1
2
C341
1U_0402_6.3V6K
VGA@
1
2
![](asset-14.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MVREFDB
MVREFSB
A_BA[0..2]
QSA[0..7]
DQMA#7
CASA0#
QSA1
CKEA0
QSA#2
DQMA#1
QSA#3
CKEA1
QSA2
QSA#4
CLKA0
MAA[0..12]
QSA3
A_BA2
QSA#5
CASA1#
DQMA#2
QSA4
CLKA0#
QSA#6
QSA5
QSA#7
RASA0#
QSA6
DQMA#3
WEA0#
QSA7
WEA1#
DQMA#4
A_BA0
RASA1#
MAA0
DQMA#5
QSA#[0..7]
MAA1
MAA2
MAA3
A_BA1
CLKA1
CSA1#_0
MAA4
QSA#0
MAA5
MAA6
CLKA1#
QSA0
CSA0#_0
MAA7
MAA8
DQMA#6
MAA9
DQMA#0
QSA#1
MAA10
MAA11
MAA12
ODTA0
ODTA1
DQMA#[0..7]
MDB51
MDB15
MDB16
MDB52
MDB17
MDB53
MDB18
MDB54
MDB19
MDB55
MDB20
MDB56
MDB21
MDB57
MDB22
MDB58
MDB23
MDB59
MDB24
MDB60
MDB25
MDB61
MDB26
MDB27
MDB62
MDB28
MDB63
MDB[0..63]
MDB29
MDB30
MDB31
MDB32
MDB0
MDB33
MDB34
MDB35
MDB36
MDB37
MDB1
MDB38
MDB39
MDB2
MDB40
MDB3
MDB41
MDB4
MDB42
MDB5
MDB6
MDB43
MDB7
MDB44
MDB8
MDB45
MDB9
MDB46
MDB10
MDB47
MDB11
MDB48
MDB12
MDB49
MDB13
MDB50
MDB14
MVREFSB
MVREFDB
TESTEN
TEST_MCLK
TEST_YCLK
MDA[0..63]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MVREFDA
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MVREFSA
MVREFDA
MVREFSA ODTB0
ODTB1
MAB12
DQMB#5
B_BA2
CKEB1
CASB0#
DQMB#6
B_BA0
CASB1#
B_BA1
DQMB#7
RASB0#
QSB#1
RASB1#
QSB0
CLKB1
MAB0
QSB#2
CLKB1#
MAB[0..12]
QSB#3
QSB#4
DQMB#1
QSB1
QSB#5
MAB1
WEB0#
QSB#6
QSB#[0..7]
QSB[0..7]
CSB0#_0
MAB2
B_BA[0..2]
QSB2
DQMB#2
QSB#7
MAB3
WEB1#
QSB3
MAB4
DQMB#0
QSB4
MAB5
CSB1#_0
DQMB#3
QSB5
MAB6
CLKB0
DQMB#[0..7]
MAB7
QSB6
MAB8
CLKB0#
DQMB#4
QSB7
MAB9
MAB10
QSB#0
MAB11
CKEB0
MAA[0..12] 23
A_BA[0..2] 23
DQMA#[0..7] 23
QSA[0..7] 23
QSA#[0..7] 23
ODTA0 23
ODTA1 23
CLKA0 23
CLKA0# 23
CLKA1 23
CLKA1# 23
RASA0# 23
RASA1# 23
CASA1# 23
CASA0# 23
CSA0#_0 23
CSA1#_0 23
CKEA0 23
CKEA1 23
WEA1# 23
WEA0# 23
MDB[0..63]24
MAA13 23
MDA[0..63]23
QSB#[0..7] 24
QSB[0..7] 24
MAB[0..12] 24
B_BA[0..2] 24
DQMB#[0..7] 24
ODTB0 24
ODTB1 24
CLKB0 24
CLKB0# 24
CLKB1 24
CLKB1# 24
RASB1# 24
RASB0# 24
CSB1#_0 24
CASB1# 24
CASB0# 24
CSB0#_0 24
WEB1# 24
CKEB1 24
CKEB0 24
WEB0# 24
VRAM_RST# 23,24
MAB13 24
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QBL60 LA-7552P
1.0
Vancouver_Memory
Custom
20 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Park&Seymour is single channel for
memory (channel B only)
15mil
15mil
15mil
15mil
Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
Note:
route 50ohms single-ended
and 100ohms diff
and keep short
REF137-03 suggest
C355
0.1U_0402_16V4Z
VGA@
1
2
R454 243_0402_1%
VGA@
1 2
R452
100_0402_1%
VGA@
12
R460 243_0402_1%
VGA@
1 2
R450
40.2_0402_1%
VGA@
12
R464
51.1_0402_1%
@
12
R465
51.1_0402_1%
@
12
R449
100_0402_1%
VGA@
12
C356
0.1U_0402_16V4Z
VGA@
1
2
R459
5.11K_0402_1%
VGA@
12
R462 51.1_0402_1%VGA@
1 2
R447
40.2_0402_1%
VGA@
12
MEMORY INTERFACE B
DDR2
GDDR5/GDDR3
DDR3
DDR2
GDDR3/GDDR5
DDR3
GDDR5
GDDR5/DDR2/GDDR3
2160809000A11SEYMOU_FCBGA962
U8D
VGA@
DQB0_0/DQB_0
C5
DQB0_1/DQB_1
C3
DQB0_10/DQB_10
J4
DQB0_11/DQB_11
K6
DQB0_12/DQB_12
K5
DQB0_13/DQB_13
L4
DQB0_14/DQB_14
M6
DQB0_15/DQB_15
M1
DQB0_16/DQB_16
M3
DQB0_17/DQB_17
M5
DQB0_18/DQB_18
N4
DQB0_19/DQB_19
P6
DQB0_2/DQB_2
E3
DQB0_20/DQB_20
P5
DQB0_21/DQB_21
R4
DQB0_22/DQB_22
T6
DQB0_23/DQB_23
T1
DQB0_24/DQB_24
U4
DQB0_25/DQB_25
V6
DQB0_26/DQB_26
V1
DQB0_27/DQB_27
V3
DQB0_28/DQB_28
Y6
DQB0_29/DQB_29
Y1
DQB0_3/DQB_3
E1
DQB0_30/DQB_30
Y3
DQB0_31/DQB_31
Y5
DQB1_0/DQB_32
AA4
DQB1_1/DQB_33
AB6
DQB1_2/DQB_34
AB1
DQB1_3/DQB_35
AB3
DQB1_4/DQB_36
AD6
DQB1_5/DQB_37
AD1
DQB1_6/DQB_38
AD3
DQB1_7/DQB_39
AD5
DQB0_4/DQB_4
F1
DQB1_8/DQB_40
AF1
DQB1_9/DQB_41
AF3
DQB1_10/DQB_42
AF6
DQB1_11/DQB_43
AG4
DQB1_12/DQB_44
AH5
DQB1_13/DQB_45
AH6
DQB1_14/DQB_46
AJ4
DQB1_15/DQB_47
AK3
DQB1_16/DQB_48
AF8
DQB1_17/DQB_49
AF9
DQB0_5/DQB_5
F3
DQB1_18/DQB_50
AG8
DQB1_19/DQB_51
AG7
DQB1_20/DQB_52
AK9
DQB1_21/DQB_53
AL7
DQB1_22/DQB_54
AM8
DQB1_23/DQB_55
AM7
DQB1_24/DQB_56
AK1
DQB1_25/DQB_57
AL4
DQB1_26/DQB_58
AM6
DQB1_27/DQB_59
AM1
DQB0_6/DQB_6
F5
DQB1_28/DQB_60
AN4
DQB1_29/DQB_61
AP3
DQB1_30/DQB_62
AP1
DQB1_31/DQB_63
AP5
DQB0_7/DQB_7
G4
DQB0_8/DQB_8
H5
DQB0_9/DQB_9
H6
MVREFDB
Y12
MVREFSB
AA12
TESTEN
AD28
CASB0B W10
CASB1B AA10
CKEB0 U10
CKEB1 AA11
CLKB0 L9
CLKB0B L8
CLKB1 AD8
CLKB1B AD7
CLKTESTA
AK10
CLKTESTB
AL10
CSB0B_0 P10
CSB0B_1 L10
CSB1B_0 AD10
CSB1B_1 AC10
WCKB0_0/DQMB_0 H3
WCKB0B_0/DQMB_1 H1
WCKB0_1/DQMB_2 T3
WCKB0B_1/DQMB_3 T5
WCKB1_0/DQMB_4 AE4
WCKB1B_0/DQMB_5 AF5
WCKB1_1/DQMB_6 AK6
WCKB1B_1/DQMB_7 AK5
DRAM_RST AH11
MAB0_0/MAB_0 P8
MAB0_1/MAB_1 T9
MAB1_2/MAB_10 AC8
MAB1_3/MAB_11 AC9
MAB1_4/MAB_12 AA7
MAB1_5/BA2 AA8
MAB1_6/BA0 Y8
MAB1_7/BA1 AA9
MAB0_2/MAB_2 P9
MAB0_3/MAB_3 N7
MAB0_4/MAB_4 N8
MAB0_5/MAB_5 N9
MAB0_6/MAB_6 U9
MAB0_7/MAB_7 U8
MAB1_0/MAB_8 Y9
MAB1_1/MAB_9 W9
ADBIB0/ODTB0 T7
ADBIB1/ODTB1 W7
RASB0B T10
RASB1B Y10
EDCB0_0/QSB_0/RDQSB_0 F6
EDCB0_1/QSB_1/RDQSB_1 K3
EDCB0_2/QSB_2/RDQSB_2 P3
EDCB0_3/QSB_3/RDQSB_3 V5
EDCB1_0/QSB_4/RDQSB_4 AB5
EDCB1_1/QSB_5/RDQSB_5 AH1
EDCB1_2/QSB_6/RDQSB_6 AJ9
EDCB1_3/QSB_7/RDQSB_7 AM5
DDBIB0_0/QSB_0B/WDQSB_0 G7
DDBIB0_1/QSB_1B/WDQSB_1 K1
DDBIB0_2/QSB_2B/WDQSB_2 P1
DDBIB0_3/QSB_3B/WDQSB_3 W4
DDBIB1_0/QSB_4B/WDQSB_4 AC4
DDBIB1_1/QSB_5B/WDQSB_5 AH3
DDBIB1_2/QSB_6B/WDQSB_6 AJ8
DDBIB1_3/QSB_7B/WDQSB_7 AM3
WEB0B N10
WEB1B AB11
MAB0_8 T8
MAB1_8 W8
R455 243_0402_1%
VGA@
1 2
R453
100_0402_1%
VGA@
12
C361
0.1U_0402_16V4Z
@
1
2
MEMORY INTERFACE A
DDR2
GDDR3/GDDR5
DDR3
GDDR5/DDR2/GDDR3
DDR2
GDDR5/GDDR3
DDR3
GDDR5
2160809000A11SEYMOU_FCBGA962
U8C
VGA@
NC_DQA0_0/DQA_0
C37
NC_DQA0_1/DQA_1
C35
NC_DQA0_10/DQA_10
C30
NC_DQA0_11/DQA_11
A30
NC_DQA0_12/DQA_12
F28
NC_DQA0_13/DQA_13
C28
NC_DQA0_14/DQA_14
A28
NC_DQA0_15/DQA_15
E28
NC_DQA0_16/DQA_16
D27
NC_DQA0_17/DQA_17
F26
NC_DQA0_18/DQA_18
C26
NC_DQA0_19/DQA_19
A26
NC_DQA0_2/DQA_2
A35
NC_DQA0_20/DQA_20
F24
NC_DQA0_21/DQA_21
C24
NC_DQA0_22/DQA_22
A24
NC_DQA0_23/DQA_23
E24
NC_DQA0_24/DQA_24
C22
NC_DQA0_25/DQA_25
A22
NC_DQA0_26/DQA_26
F22
NC_DQA0_27/DQA_27
D21
NC_DQA0_28/DQA_28
A20
NC_DQA0_29/DQA_29
F20
NC_DQA0_3/DQA_3
E34
NC_DQA0_30/DQA_30
D19
NC_DQA0_31/DQA_31
E18
NC_DQA1_0/DQA_32
C18
NC_DQA1_1/DQA_33
A18
NC_DQA1_2/DQA_34
F18
NC_DQA1_3/DQA_35
D17
NC_DQA1_4/DQA_36
A16
NC_DQA1_5/DQA_37
F16
NC_DQA1_6/DQA_38
D15
NC_DQA1_7/DQA_39
E14
NC_DQA0_4/DQA_4
G32
NC_DQA1_8/DQA_40
F14
NC_DQA1_9/DQA_41
D13
NC_DQA1_10/DQA_42
F12
NC_DQA1_11/DQA_43
A12
NC_DQA1_12/DQA_44
D11
NC_DQA1_13/DQA_45
F10
NC_DQA1_14/DQA_46
A10
NC_DQA1_15/DQA_47
C10
NC_DQA1_16/DQA_48
G13
NC_DQA1_17/DQA_49
H13
NC_DQA0_5/DQA_5
D33
NC_DQA1_18/DQA_50
J13
NC_DQA1_19/DQA_51
H11
NC_DQA1_20/DQA_52
G10
NC_DQA1_21/DQA_53
G8
NC_DQA1_22/DQA_54
K9
NC_DQA1_23/DQA_55
K10
NC_DQA1_24/DQA_56
G9
NC_DQA1_25/DQA_57
A8
NC_DQA1_26/DQA_58
C8
NC_DQA1_27/DQA_59
E8
NC_DQA0_6/DQA_6
F32
NC_DQA1_28/DQA_60
A6
NC_DQA1_29/DQA_61
C6
NC_DQA1_30/DQA_62
E6
NC_DQA1_31/DQA_63
A5
NC_DQA0_7/DQA_7
E32
NC_DQA0_8/DQA_8
D31
NC_DQA0_9/DQA_9
F30
MEM_CALRP1
M12
NC_MVREFDA
L18
NC_MVREFSA
L20
NC_MEM_CALRN0
L27
MEM_CALRN1
N12
NC_MEM_CALRN2
AG12
NC_MEM_CALRP0
M27
NC_MEM_CALRP2
AH12
NC_CASA0B K20
NC_CASA1B K17
NC_CKEA0 K21
NC_CKEA1 J20
NC_CLKA0 H27
NC_CLKA0B G27
NC_CLKA1 J14
NC_CLKA1B H14
NC_CSA0B_0 K24
NC_CSA0B_1 K27
NC_CSA1B_0 M13
NC_CSA1B_1 K16
NC_WCKA0_0/DQMA_0 A32
NC_WCKA0B_0/DQMA_1 C32
NC_WCKA0_1/DQMA_2 D23
NC_WCKA0B_1/DQMA_3 E22
NC_WCKA1_0/DQMA_4 C14
NC_WCKA1B_0/DQMA_5 A14
NC_WCKA1_1/DQMA_6 E10
NC_WCKA1B_1/DQMA_7 D9
NC_MAA0_0/MAA_0 G24
NC_MAA0_1/MAA_1 J23
NC_MAA1_2/MAA_10 L13
NC_MAA1_3/MAA_11 G16
NC_MAA1_4/MAA_12 J16
NC_MAA1_5/MAA_13_BA2 H16
NC_MAA1_6/MAA_14_BA0 J17
NC_MAA1_7/MAA_A15_BA1 H17
NC_MAA0_2/MAA_2 H24
NC_MAA0_3/MAA_3 J24
NC_MAA0_4/MAA_4 H26
NC_MAA0_5/MAA_5 J26
NC_MAA0_6/MAA_6 H21
NC_MAA0_7/MAA_7 G21
NC_MAA1_0/MAA_8 H19
NC_MAA1_1/MAA_9 H20
NC_ADBIA0/ODTA0 J21
NC_ADBIA1/ODTA1 G19
NC_RASA0B K23
NC_RASA1B K19
NC_EDCA0_0/QSA_0/RDQSA_0 C34
NC_EDCA0_1/QSA_1/RDQSA_1 D29
NC_EDCA0_2/QSA_2/RDQSA_2 D25
NC_EDCA0_3/QSA_3/RDQSA_3 E20
NC_EDCA1_0/QSA_4/RDQSA_4 E16
NC_EDCA1_1/QSA_5/RDQSA_5 E12
NC_EDCA1_2/QSA_6/RDQSA_6 J10
NC_EDCA1_3/QSA_7/RDQSA_7 D7
NC_MAA0_8 H23
NC_MAA1_8 J19
NC_DDBIA0_0/QSA_0B/WDQSA_0 A34
NC_DDBIA0_1/QSA_1B/WDQSA_1 E30
NC_DDBIA0_2/QSA_2B/WDQSA_2 E26
NC_DDBIA0_3/QSA_3B/WDQSA_3 C20
NC_DDBIA1_0/QSA_4B/WDQSA_4 C16
NC_DDBIA1_1/QSA_5B/WDQSA_5 C12
NC_DDBIA1_2/QSA_6B/WDQSA_6 J11
NC_DDBIA1_3/QSA_7B/WDQSA_7 F8
NC_WEA0B K26
NC_WEA1B L15
R446
40.2_0402_1%
VGA@
12
C359
120P_0402_50V8
VGA@
1
2
R451
40.2_0402_1%
VGA@
12
R458 243_0402_1%
VGA@
1 2
C358
0.1U_0402_16V4Z
VGA@
1
2
R456 243_0402_1%
VGA@
1 2
C357
0.1U_0402_16V4Z
VGA@
1
2
R461 10_0402_5%
VGA@
1 2
R463
5.11K_0402_1%
VGA@
1 2
R457 243_0402_1%
VGA@
1 2
R448
100_0402_1%
VGA@
12
C360
0.1U_0402_16V4Z
@
1
2
![](asset-15.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GCORE_SEN
+PCIE_VDDR
+VDDCI
+BIF_VDDC
+VDDR4_5
+VDD_CT
+SPV10
+SPV_18
+MPV_18
FB_GND
GCORE_SEN48
+1.8VSG
+1.0VSG
+1.8VSG
+VGA_CORE
+VGA_CORE
+BIF_VDDC
+1.5VSG
+1.8VSG
+3VSG
+1.8VSG
+1.8VSG
+1.0VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QBL60 LA-7552P
1.0
Vancouver_Power/GND
Custom
21 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
2010/04/27
non-BACO design,N27,T27
connect BIF_VDDC to VDDC
For BACO design
(GDDR3/DDR3 1.12V@4A VDDCI)
(GDDR5 1.12V@16A VDDCI)
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
Seymour/Whistler
PCIE_VDDR,PCIE_PVDD can combian to PCIE_VDDR
BIF_VDDC
Park/Madison:Connect to VDDC
Seymour/Whisler:
dGPU operating:VDDC
BACO mode:+1.0V
SM01000BY00 5000ma 120ohm@100mhz DCR 0.02
160mil
Granville VDDC:47A
40mil
170mA
10mil
10mil
20mil
10mil
20mil
20mil
20mil
SM010030010
300ma 120ohm@100mhz DCR 0.3
SM010030010
200ma 120ohm@100mhz DCR 0.2
SM010030010
200ma 120ohm@100mhz DCR 0.2
440mA
2A3400mA
219mA
60mA
47A
150mA
75mA
120mA
5A
470ohm/1A
55mA
SM010014520 3000ma 220ohm@100mhz DCR 0.04
220ohm/2A
120ohm/0.3A
SM010030010
300ma 120ohm@100mhz DCR 0.3
120ohm/0.3A
470ohm/1A
SM010030010
200ma 120ohm@100mhz DCR 0.2
Granville VDDCI:4.6A
Granville PRO VDDC:47A
Madison PRO VDDC+VDDCI=31.3A
Whistler PRO VDDC+VDDCI=24A
SeymourXT VDDC+VDDCI=14.2A
RobsonXT VDDC+VDDCI=12.9A
Ref137-12~ remove Bead
Seymour/Whistler
NC 20101116
C448
1U_0402_6.3V6K
VGA@
1
2
C432
10U_0603_6.3V6M
VGA@
1
2
C406
1U_0402_6.3V6K
VGA@
1
2
L17
BLM18AG121SN1D_0603
VGA@
12
R466
0_0402_5%
@
12
C434
10U_0603_6.3V6M
VGA@
1
2
C430
10U_0603_6.3V6M
VGA@
1
2
C447
0.1U_0402_16V4Z
VGA@
1
2
C415
10U_0603_6.3V6M
VGA@
1
2
C449
1U_0402_6.3V6K
VGA@
1
2
C372
10U_0603_6.3V6M
VGA@
1
2
C433
10U_0603_6.3V6M
VGA@
1
2
C364
1U_0402_6.3V6K
VGA@
1
2
C419
1U_0402_6.3V6K
VGA@
1
2
C439
0.1U_0402_16V4Z
VGA@
1
2
C410
1U_0402_6.3V6K
VGA@
1
2
C370
1U_0402_6.3V6K
VGA@
1
2
L19
FBMA-L11-201209-121LMA50T_0805
VGA@
12
C452
1U_0402_6.3V6K
VGA@
1
2
C418
1U_0402_6.3V6K
VGA@
1
2
C454
1U_0402_6.3V6K
VGA@
1
2
C451
1U_0402_6.3V6K
VGA@
1
2
C463
10U_0603_6.3V6M
VGA@
1
2
C417
1U_0402_6.3V6K
VGA@
1
2
C428
10U_0603_6.3V6M
VGA@
1
2
L18
BLM18AG121SN1D_0603
VGA@
12
C423
1U_0402_6.3V6K
VGA@
1
2
C368
1U_0402_6.3V6K
VGA@
1
2
C409
1U_0402_6.3V6K
VGA@
1
2
C392
1U_0402_6.3V6K
VGA@
1
2
L20
BLM18AG121SN1D_0603
VGA@
12
C376
1U_0402_6.3V6K
VGA@
1
2
C413
1U_0402_6.3V6K
VGA@
1
2
C422
1U_0402_6.3V6K
VGA@
1
2
C397
10U_0603_6.3V6M
VGA@
1
2
L16
BLM18AG121SN1D_0603
VGA@
12
C378
1U_0402_6.3V6K
VGA@
1
2
C365
1U_0402_6.3V6K
VGA@
1
2
C381
0.1U_0402_16V4Z
VGA@
1
2
C450
1U_0402_6.3V6K
VGA@
1
2
C371
10U_0603_6.3V6M
VGA@
1
2
C384
10U_0603_6.3V6M
VGA@
1
2
C405
1U_0402_6.3V6K
VGA@
1
2
C420
1U_0402_6.3V6K
VGA@
1
2
C396
10U_0603_6.3V6M
VGA@
1
2
C395
10U_0603_6.3V6M
VGA@
1
2
C388
1U_0402_6.3V6K
VGA@
1
2
C379
1U_0402_6.3V6K
VGA@
1
2
C369
1U_0402_6.3V6K
VGA@
1
2
C441
1U_0402_6.3V6K
VGA@
1
2
C465
10U_0603_6.3V6M
VGA@
1
2
C438
1U_0402_6.3V6K
VGA@
1
2
C366
1U_0402_6.3V6K
VGA@
1
2
C383
1U_0402_6.3V6K
VGA@
1
2
L14
BLM18AG121SN1D_0603
VGA@
12
C389
1U_0402_6.3V6K
VGA@
1
2
C445
10U_0603_6.3V6M
VGA@
1
2
C446
1U_0402_6.3V6K
VGA@
1
2
C440
10U_0603_6.3V6M
VGA@
1
2
C394
1U_0402_6.3V6K
VGA@
1
2
C404
0.1U_0402_16V4Z
VGA@
1
2
C380
1U_0402_6.3V6K
VGA@
1
2
C411
1U_0402_6.3V6K
VGA@
1
2
C456
1U_0402_6.3V6K
VGA@
1
2
C421
1U_0402_6.3V6K
VGA@
1
2
C416
1U_0402_6.3V6K
VGA@
1
2
C377
1U_0402_6.3V6K
VGA@
1
2
C431
10U_0603_6.3V6M
VGA@
1
2
C412
1U_0402_6.3V6K
VGA@
1
2
L13
FBMA-L11-201209-221LMA30T_0805
VGA@
12
C382
0.1U_0402_16V4Z
VGA@
1
2
C429
10U_0603_6.3V6M
VGA@
1
2
C399
1U_0402_6.3V6K
VGA@
1
2
C437
10U_0603_6.3V6M
VGA@
1
2
C391
1U_0402_6.3V6K
VGA@
1
2
C459
1U_0402_6.3V6K
VGA@
1
2
C401
1U_0402_6.3V6K
VGA@
1
2
C453
1U_0402_6.3V6K
VGA@
1
2
C408
1U_0402_6.3V6K
VGA@
1
2
POWER
PLL
PCIE
CORE
MEM I/O
I/O
LEVEL
TRANSLATION
ISOLATED
CORE I/O
VOLTAGE
SENESE
2160809000A11SEYMOU_FCBGA962
U8E
VGA@
PCIE_VDDR/PCIE_PVDD AB37
MPV18#1
H7
MPV18#2
H8
SPV18
AM10
PCIE_VDDC#1 G30
PCIE_VDDC#10 R28
PCIE_VDDC#11 T28
PCIE_VDDC#12 U28
PCIE_VDDC#2 G31
PCIE_VDDC#3 H29
PCIE_VDDC#4 H30
PCIE_VDDC#5 J29
PCIE_VDDC#6 J30
PCIE_VDDC#7 L28
PCIE_VDDC#8 M28
PCIE_VDDC#9 N28
PCIE_VDDR#1 AA31
PCIE_VDDR#2 AA32
PCIE_VDDR#3 AA33
PCIE_VDDR#4 AA34
PCIE_VDDR#5 V28
PCIE_VDDR#6 W29
PCIE_VDDR#7 W30
PCIE_VDDR#8 Y31
SPV10
AN9
SPVSS
AN10
VDDR1#1
AC7
VDDR1#10
G17
VDDR1#11
G20
VDDR1#12
G23
VDDR1#13
G26
VDDR1#14
G29
VDDR1#15
H10
VDDR1#16
J7
VDDR1#17
J9
VDDR1#18
K11
VDDR1#19
K13
VDDR1#2
AD11
VDDR1#20
K8
VDDR1#21
L12
VDDR1#22
L16
VDDR1#23
L21
VDDR1#24
L23
VDDR1#25
L26
VDDR1#26
L7
VDDR1#27
M11
VDDR1#28
N11
VDDR1#29
P7
VDDR1#3
AF7
VDDR1#30
R11
VDDR1#31
U11
VDDR1#32
U7
VDDR1#33
Y11
VDDR1#34
Y7
VDDR1#4
AG10
VDDR1#5
AJ7
VDDR1#6
AK8
VDDR1#7
AL9
VDDR1#8
G11
VDDR1#9
G14
VDDR3#1
AF23
VDDR3#2
AF24
VDDR3#3
AG23
VDDR3#4
AG24
VDDR4#4
AF13
VDDR4#5
AF15
VDDR4#7
AG13
VDDR4#8
AG15
VDDR4#1
AD12
VDDR4#2
AF11
VDDR4#3
AF12
VDDR4#6
AG11
NC_VDDRHA
M20
NC_VDDRHB
V12
NC_VSSRHA
M21
NC_VSSRHB
U12
VDD_CT#1
AF26
VDD_CT#2
AF27
VDD_CT#3
AG26
VDD_CT#4
AG27
VDDC#1 AA15
VDDC#9 AB21
VDDC#10 AB23
VDDC#11 AB26
VDDC#12 AB28
VDDCI#3 AC12
VDDCI#4 AC15
VDDC#13 AC17
VDDC#14 AC20
VDDC#15 AC22
VDDC#16 AC24
VDDC#2 AA17
VDDC#17 AC27
VDDCI#5 AD13
VDDCI#6 AD16
VDDC#18 AD18
VDDC#19 AD21
VDDC#20 AD23
VDDC#21 AD26
VDDC#22 AF17
VDDC#23 AF20
VDDC#24 AF22
VDDC#3 AA20
VDDC#25 AG16
VDDC#26 AG18
VDDC#27 AG21
VDDC#28 AH22
VDDCI#8 M16
VDDCI#9 M18
VDDCI#10 M23
VDDC#31 M26
VDDCI#12 N15
VDDCI#13 N17
VDDC#4 AA22
VDDCI#14 N20
VDDCI#15 N22
VDDC#32 N24
VDDC/BIF_VDDC#33 N27
VDDCI#17 R13
VDDCI#18 R16
VDDC#34 R18
VDDC#35 R21
VDDC#36 R23
VDDC#37 R26
VDDC#5 AA24
VDDCI#20 T15
VDDC#38 T17
VDDC#39 T20
VDDC#40 T22
VDDC#41 T24
VDDC/BIF_VDDC#42 T27
VDDC#43 U16
VDDC#44 U18
VDDC#45 U21
VDDC#46 U23
VDDC#6 AA27
VDDC#47 U26
VDDCI#21 V15
VDDC#48 V17
VDDC#49 V20
VDDC#50 V22
VDDC#51 V24
VDDC#52 V27
VDDC#53 Y16
VDDC#54 Y18
VDDC#55 Y21
VDDCI#2 AB13
VDDC#56 Y23
VDDC#57 Y26
VDDC#58 Y28
VDDC#7 AB16
VDDC#8 AB18
VDDCI#7 M15
VDDCI#11 N13
VDDCI#16 R12
VDDCI#19 T12
VDDCI#1 AA13
VDDCI#22 Y13
VDDC#29 AH27
VDDC#30 AH28
FB_VDDC
AF28
FB_VDDCI
AG28
FB_GND
AH29
C403
1U_0402_6.3V6K
VGA@
1
2
C424
1U_0402_6.3V6K
VGA@
1
2
C393
1U_0402_6.3V6K
VGA@
1
2
C442
0.1U_0402_16V4Z
VGA@
1
2
C460
0.1U_0402_16V4Z
VGA@
1
2
C461
1U_0402_6.3V6K
VGA@
1
2
C455
1U_0402_6.3V6K
VGA@
1
2
C402
10U_0603_6.3V6M
VGA@
1
2
C362
1U_0402_6.3V6K
VGA@
1
2
C363
1U_0402_6.3V6K
VGA@
1
2
C444
0.1U_0402_16V4Z
VGA@
1
2
C400
1U_0402_6.3V6K
VGA@
1
2
C367
1U_0402_6.3V6K
VGA@
1
2
C375
1U_0402_6.3V6K
VGA@
1
2
C458
10U_0603_6.3V6M
VGA@
1
2
C443
1U_0402_6.3V6K
VGA@
1
2
C462
0.1U_0402_16V4Z
VGA@
1
2
C407
1U_0402_6.3V6K
VGA@
1
2
C464
10U_0603_6.3V6M
VGA@
1
2
C373
10U_0603_6.3V6M
VGA@
1
2
C390
1U_0402_6.3V6K
VGA@
1
2
C414
1U_0402_6.3V6K
VGA@
1
2
C385
1U_0402_6.3V6K
VGA@
1
2
C427
0.1U_0402_16V4Z
VGA@
1
2
C425
1U_0402_6.3V6K
VGA@
1
2
C457
1U_0402_6.3V6K
VGA@
1
2
C398
1U_0402_6.3V6K
VGA@
1
2
C386
1U_0402_6.3V6K
VGA@
1
2
C387
1U_0402_6.3V6K
VGA@
1
2
L21
FBMA-L11-201209-121LMA50T_0805
VGA@
12
C426
1U_0402_6.3V6K
VGA@
1
2
![](asset-16.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+DPABCD_VDD18
+DPABCD_VDD18
+DPABCD_VDD18
+DPEF_VDD18
+DPABCD_VDD18
+DPEF_VDD18
+DPABCD_VDD10
+DPABCD_VDD18
+DPABCD_VDD18
+DPABCD_VDD10
PX_EN
+DPEF_VDD10
+DPEF_VDD10
+DPABCD_VDD18
+DPABCD_VDD18
+DPABCD_VDD10
+DPEF_VDD18
+DPABCD_VDD10
+DPEF_VDD18
PX_EN 25,36
+1.0VSG
+1.8VSG
+1.8VSG
+1.0VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Vancouver_Power/GND
Custom
22 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
10mil
10mil
10mil
20mil
Seymour/Whistler
DPA_VDD10,DPB_VDD10
can combian to DPAB_VDD10
DPC_VDD10,DPD_VDD10
can combian to DPCD_VDD10
DPE_VDD10,DPD_VDD10
can combian to DPEF_VDD10
20mA
20mil
20mil
20mil
20mA
20mA
20mA
20mA
20mA
220mA
10mil
10mil
300mA
10mil
Manhatann:300mA
Seymour:150mA
Manhatann:220mA
Seymour:110mA
DP mode:300mA
LVDS mode:440mA
DPA_VDD18,DPA_PVDD,DPB_VDD18,DPB_PVDD
can combian to DPAB_VDD18
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD
can combian to DPCD_VDD18
(DPD_VDD18,DPD_PVDD not applicable on Robson/Park)
DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD
can combian to DPEF_VDD18
DPx-VSSR,DPx_PVSS can combian to DP_VSSR
(Manhatann should have individual GND)
where x is A,B,C,D,E,F
20mil
Park/Madison :AL21left NC
Seymour/Whistler:
AL21:PX_EN
use to control discreate GPU regulators
for power express BACO mode
Support BACO:
output High3.3V:turn off regulators (BACO mode on)
output Low0V:turn on regulators (BACO mode off)
need PD resistor
No support BACO:
left NC
20mil
DP mode:220mA
LVDS mode:240mA
20mil
20mil
20mil
20mil
20mil
20mil
REF137-13 update
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
FootPrint
FootPrint
FootPrint
FootPrint
PX_EN: PU at P.20
SBIOS will control VGA power on/off.
High :BACO mode enable
LOW:BACO disable
R468
150_0402_1%
VGA@
1 2
C482
1U_0402_6.3V6K
VGA@
1
2
DP PLL POWER
DP A/B POWER
DP C/D POWER
DP E/F POWER
2160809000A11SEYMOU_FCBGA962
U8H
VGA@
DPAB_VDD18/DPA_PVDD AU28
DP_VSSR/DPA_PVSS AV27
DPAB/DPA_VDD10#1 AP31
DPAB/DPA_VDD10#2 AP32
DPAB/DPA_VDD18#1 AN24
DPAB/DPA_VDD18#2 AP24
DP/DPA_VSSR#1 AN27
DP/DPA_VSSR#2 AP27
DP/DPA_VSSR#3 AP28
DP/DPA_VSSR#4 AW24
DP/DPA_VSSR#5 AW26
DPAB_CALR AW28
DPAB_VDD18/DPB_PVDD AV29
DP_VSSR/DPB_PVSS AR28
DPAB/DPB_VDD10#1 AN33
DPAB/DPB_VDD10#2 AP33
DPAB/DPB_VDD18#1 AP25
DPAB/DPB_VDD18#2 AP26
DP/DPB_VSSR#1 AN29
DP/DPB_VSSR#2 AP29
DP/DPB_VSSR#3 AP30
DP/DPB_VSSR#4 AW30
DP/DPB_VSSR#5 AW32
DPCD_VDD18/DPC_PVDD AU18
DP_VSSR/DPC_PVSS AV17
DPCD/DPC_VDD10#1
AP13
DPCD/DPC_VDD10#2
AT13
DPCD/DPC_VDD18#1
AP20
DPCD/DPC_VDD18#2
AP21
DP/DPC_VSSR#1
AN17
DP/DPC_VSSR#2
AP16
DP/DPC_VSSR#3
AP17
DP/DPC_VSSR#4
AW14
DP/DPC_VSSR#5
AW16
DPCD_CALR
AW18
DPCD_VDD18/DPD_PVDD AV19
DP_VSSR/DPD_PVSS AR18
DPCD/DPD_VDD10#1
AP14
DPCD/DPD_VDD10#2
AP15
DPCD/DPD_VDD18#1
AP22
DPCD/DPD_VDD18#2
AP23
DP/DPD_VSSR#1
AN19
DP/DPD_VSSR#2
AP18
DP/DPD_VSSR#3
AP19
DP/DPD_VSSR#4
AW20
DP/DPD_VSSR#5
AW22
DPEF_VDD18/DPE_PVDD AM37
DP_VSSR/DPE_PVSS AN38
DPEF/DPE_VDD10#1
AL33
DPEF/DPE_VDD10#2
AM33
DPEF/DPE_VDD18#1
AH34
DPEF/DPE_VDD18#2
AJ34
DP/DPE_VSSR#1
AN34
DP/DPE_VSSR#2
AP39
DP/DPE_VSSR#3
AR39
DP/DPE_VSSR#4
AU37
DPEF_CALR
AM39
DPEF_VDD18/DPF_PVDD AL38
DP_VSSR/DPF_PVSS AM35
DPEF/DPF_VDD10#1
AK33
DPEF/DPF_VDD10#2
AK34
DPEF/DPF_VDD18#1
AF34
DPEF/DPF_VDD18#2
AG34
DP/DPF_VSSR#1
AF39
DP/DPF_VSSR#2
AH39
DP/DPF_VSSR#3
AK39
DP/DPF_VSSR#4
AL34
DP/DPF_VSSR#5
AM34
C476
1U_0402_6.3V6K
VGA@
1
2
C471
1U_0402_6.3V6K
VGA@
1
2
C479
1U_0402_6.3V6K
VGA@
1
2
R470
150_0402_1%
VGA@
12
C481
10U_0603_6.3V6M
VGA@
1
2
C470
0.1U_0402_16V4Z
VGA@
1
2
L26
MBK1608221YZF_2P
VGA@
12
C480
0.1U_0402_16V4Z
VGA@
1
2
C483
0.1U_0402_16V4Z
VGA@
1
2
C478
10U_0603_6.3V6M
VGA@
1
2
L23
MBK1608221YZF_2P
VGA@
12
GND
2160809000A11SEYMOU_FCBGA962
U8F
VGA@
PCIE_VSS#1
AB39
PCIE_VSS#10
J31
PCIE_VSS#11
J34
PCIE_VSS#12
K31
PCIE_VSS#13
K34
PCIE_VSS#14
K39
PCIE_VSS#15
L31
PCIE_VSS#16
L34
PCIE_VSS#17
M34
PCIE_VSS#18
M39
PCIE_VSS#19
N31
PCIE_VSS#2
E39
PCIE_VSS#20
N34
PCIE_VSS#21
P31
PCIE_VSS#22
P34
PCIE_VSS#23
P39
PCIE_VSS#24
R34
PCIE_VSS#25
T31
PCIE_VSS#26
T34
PCIE_VSS#27
T39
PCIE_VSS#28
U31
PCIE_VSS#29
U34
PCIE_VSS#3
F34
PCIE_VSS#30
V34
PCIE_VSS#31
V39
PCIE_VSS#32
W31
PCIE_VSS#33
W34
PCIE_VSS#34
Y34
PCIE_VSS#35
Y39
PCIE_VSS#4
F39
PCIE_VSS#5
G33
PCIE_VSS#6
G34
PCIE_VSS#7
H31
PCIE_VSS#8
H34
PCIE_VSS#9
H39
VSS_MECH#1 A39
VSS_MECH#2 AW1
VSS_MECH#3 AW39
GND#1 A3
GND#10 AA6
GND#98 F13
GND#100
F15
GND#101
F17
GND#102
F19
GND#103
F21
GND#104
F23
GND#105
F25
GND#106
F27
GND#107
F29
GND#108
F31
GND#11 AB12
GND#109
F33
GND#110
F7
GND#111
F9
GND#112
G2
GND#113
G6
GND#114
H9
GND#115
J2
GND#116
J27
GND#117
J6
GND#118
J8
GND#12 AB15
GND#119
K14
GND#120
K7
GND#121
L11
GND#122
L17
GND#123
L2
GND#124
L22
GND#125
L24
GND#126
L6
GND#127
M17
GND#128
M22
GND#13 AB17
GND#129
M24
GND#130
N16
GND#131
N18
GND#132
N2
GND#133
N21
GND#134
N23
GND#135
N26
GND#136
N6
GND#137
R15
GND#138
R17
GND#14 AB20
GND#139
R2
GND#140
R20
GND#141
R22
GND#142
R24
GND#143
R27
GND#144
R6
GND#145
T11
GND#146
T13
GND#147
T16
GND#148
T18
GND#15 AB22
GND#149
T21
GND#150
T23
GND#151
T26
GND#153
U15
GND#154
U17
GND#155
U2
GND#156
U20
GND#157
U22
GND#158
U24
GND#159
U27
GND#16 AB24
GND#160
U6
GND#161
V11
GND#163
V16
GND#164
V18
GND#165
V21
GND#166
V23
GND#167
V26
GND#168
W2
GND#169
W6
GND#170
Y15
GND#17 AB27
GND#171
Y17
GND#172
Y20
GND#173
Y22
GND#174
Y24
GND#175
Y27
GND#18 AC11
GND#19 AC13
GND#2 A37
GND#20 AC16
GND#21 AC18
GND#22 AC2
GND#23 AC21
GND#24 AC23
GND#25 AC26
GND#26 AC28
GND#27 AC6
GND#28 AD15
GND#29 AD17
GND#3 AA16
GND#30 AD20
GND#31 AD22
GND#32 AD24
GND#33 AD27
GND#34 AD9
GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16
GND#39 AF18
GND#4 AA18
GND#40 AF21
GND#41 AG17
GND#42 AG2
GND#43 AG20
GND#44 AG22
GND#45 AG6
GND#46 AG9
GND#47 AH21
GND#48 AJ10
GND#5 AA2
GND#49 AJ11
GND#50 AJ2
GND#51 AJ28
GND#52 AJ6
GND#53 AK11
GND#54 AK31
GND#55 AK7
GND#56 AL11
GND#57 AL14
GND#58 AL17
GND#6 AA21
GND#59 AL2
GND#60 AL20
GND/PX_EN#61 AL21
GND#62 AL23
GND#63 AL26
GND#64 AL32
GND#65 AL6
GND#66 AL8
GND#67 AM11
GND#68 AM31
GND#7 AA23
GND#69 AM9
GND#70 AN11
GND#71 AN2
GND#72 AN30
GND#73 AN6
GND#74 AN8
GND#75 AP11
GND#76 AP7
GND#77 AP9
GND#78 AR5
GND#8 AA26
GND#79 B11
GND#80 B13
GND#81 B15
GND#82 B17
GND#83 B19
GND#84 B21
GND#85 B23
GND#86 B25
GND#87 B27
GND#9 AA28
GND#88 B29
GND#89 B31
GND#90 B33
GND#91 B7
GND#92 B9
GND#93 C1
GND#94 C39
GND#95 E35
GND#96 E5
GND#97 F11
GND#152
U13
GND#162
V13
L25
MBK1608221YZF_2P
VGA@
12
C475
0.1U_0402_16V4Z
VGA@
1
2
R467
150_0402_1%
VGA@
12
L27
MBK1608221YZF_2P
VGA@
12
C469
10U_0603_6.3V6M
VGA@
1
2
C477
10U_0603_6.3V6M
VGA@
1
2
![](asset-17.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DQMA#3
QSA#1
QSA#3
QSA3
QSA1
DQMA#1
A_BA0
A_BA1
ODTA0_1
CLKA0#
WEA0#
CKEA0
RASA0#
CASA0#
CSA0#_0
CLKA0
MAA11
MAA9
MAA10
MAA8
MAA7
MAA6
MAA3
MAA4
MAA5
MAA1
MAA2
MAA0
VRAM_RST#
VREFDA_Q2
VREFCA_A2
MAA12
A_BA2
MDA[0..63]
MAA6
DQMA#0
MAA11
CASA1#
MAA5
MAA12
MAA4
MAA1
DQMA#7
A_BA0
MAA2
QSA4
MAA1
MAA0
QSA#2
MAA7
QSA#7
VREFDA_Q3
MAA9
MAA7
MAA0
CLKA1#
A_BA2
VREFDA_Q4
MAA5
RASA1#
MAA11
MAA4
VRAM_RST#
MAA10
MAA12
QSA7
VRAM_RST#
MAA8
DQMA#4
MAA8
A_BA1
DQMA#2
MAA2
MAA0
ODTA1_1
VRAM_RST#
ODTA1_1
MAA4
MAA7
QSA#0
VREFCA_A4
DQMA#6
QSA6
CKEA1
MAA12
MAA3MAA3
A_BA2
MAA10
MAA1
QSA#4
DQMA#5
QSA#5
VREFDA_Q1
MAA9 MAA9
CLKA1
CSA1#_0
MAA10
ODTA0_1
MAA3
MAA2
QSA2
MAA8
QSA#6
MAA11
A_BA1
A_BA0
VREFCA_A1
MAA5
WEA1#
VREFCA_A3
QSA5
MAA6
QSA0
MAA6
MDA18
MDA20
MDA16
MDA19
MDA23
MDA17
MDA21
MDA0
MDA22
MDA4
MDA6
MDA7
MDA2
MDA3
MDA1
MDA5
MDA24
MDA28
MDA29
MDA26
MDA25
MDA30
MDA27
MDA31
MDA13
MDA11
MDA12
MDA9
MDA15
MDA14
MDA10
MDA8
MDA40
MDA35
MDA47
MDA38
MDA32
MDA45
MDA37
MDA46
MDA43
MDA41
MDA34
MDA44
MDA36
MDA33
MDA39
MDA42
MDA63
MDA54
MDA56
MDA55
MDA48
MDA62
MDA57
MDA53
MDA52
MDA58
MDA49
MDA61
MDA60
MDA51
MDA50
MDA59
MAA13 MAA13 MAA13 MAA13
VREFCA_A2VREFCA_A1 VREFCA_A4VREFDA_Q1 VREFCA_A3 VREFDA_Q3 VREFDA_Q4
CLKA1#
CLKA1CLKA0
CLKA0#
ODTA1
ODTA0
ODTA0_1
ODTA1_1
VREFDA_Q2
MDA[0..63]20
VRAM_RST#20,24
CLKA020
CLKA0#20
CLKA120
CLKA1#20
CKEA120
CSA1#_020
RASA1#20
CASA1#20
WEA1#20
A_BA020
A_BA220
A_BA120
CKEA020
CSA0#_020
RASA0#20
CASA0#20
WEA0#20
MAA[13..0]20
QSA#[7..0]20
QSA[7..0]20
DQMA#[7..0]20
ODTA020
ODTA120
+1.5VSG
+1.5VSG
+1.5VSG +1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG+1.5VSG +1.5VSG+1.5VSG +1.5VSG+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG+1.5VSG +1.5VSG
+1.5VSG
+1.5VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
VRAM_DDR3 / Channel A
Custom
23 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Pull high for Madison and Park...
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
C499
1U_0402_6.3V6K
VGA@
1
2
C493
1U_0402_6.3V6K
VGA@
1
2
R485
0_0402_5%
12
R492
4.99K_0402_1%
VGA@
12
C517
10U_0603_6.3V6M
VGA@
1
2
ZZZ2
2GVRAM-SAM
X76L02@
R486
56_0402_1%
VGA@
1 2
C496
1U_0402_6.3V6K
VGA@
1
2
C506
1U_0402_6.3V6K
VGA@
1
2
C518
10U_0603_6.3V6M
VGA@
1
2
C487
0.1U_0402_16V4Z
VGA@
1
2
ZZZ1
1GVRAM-SAM
X76L01@
C502
1U_0402_6.3V6K
VGA@
1
2
C505
1U_0402_6.3V6K
VGA@
1
2
R480
4.99K_0402_1%VGA@
12
R488
4.99K_0402_1%
VGA@
12
R482
4.99K_0402_1% VGA@
12
C512
0.01U_0402_16V7K
VGA@
1
2
R473
243_0402_1%
VGA@
12
C516
10U_0603_6.3V6M
VGA@
1
2
96-BALL
SDRAM DDR3
U12
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
R471
243_0402_1%
VGA@
12
C497
1U_0402_6.3V6K
VGA@
1
2
R472
243_0402_1%
VGA@
12
C485
0.1U_0402_16V4Z
VGA@
1
2
C513
10U_0603_6.3V6M
VGA@
1
2
C486
0.1U_0402_16V4Z
VGA@
1
2
C509
1U_0402_6.3V6K
VGA@
1
2
C510
1U_0402_6.3V6K
VGA@
1
2
C488
0.1U_0402_16V4Z
VGA@
1
2
R493
4.99K_0402_1%
VGA@
12
C508
1U_0402_6.3V6K
VGA@
1
2
C490
0.1U_0402_16V4Z
VGA@
1
2
R487
4.99K_0402_1%
VGA@
12
96-BALL
SDRAM DDR3
U13
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
96-BALL
SDRAM DDR3
U11
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
R498 56_0402_1%
VGA@
1 2
R490
4.99K_0402_1%
VGA@
12
C491
0.1U_0402_16V4Z
VGA@
1
2
R496 56_0402_1%
VGA@
1 2
C507
1U_0402_6.3V6K
VGA@
1
2
C520
10U_0603_6.3V6M
VGA@
1
2
R474
243_0402_1%
VGA@
12
96-BALL
SDRAM DDR3
U14
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
C501
1U_0402_6.3V6K
VGA@
1
2
R475
4.99K_0402_1% VGA@
12
C489
0.1U_0402_16V4Z
VGA@
1
2
C495
1U_0402_6.3V6K
VGA@
1
2
C515
10U_0603_6.3V6M
VGA@
1
2
C503
1U_0402_6.3V6K
VGA@
1
2
C492
1U_0402_6.3V6K
VGA@
1
2
C511
1U_0402_6.3V6K
VGA@
1
2
R491
4.99K_0402_1%
VGA@
12
C498
1U_0402_6.3V6K
VGA@
1
2
R484
56_0402_1%
VGA@
1 2
ZZZ4
2GVRAM-HYNIX
X76L04@
R489
4.99K_0402_1%
VGA@
12
C504
1U_0402_6.3V6K
VGA@
1
2
R479
4.99K_0402_1% VGA@
12
ZZZ3
1GVRAM-HYNIX
X76L03@
R476
4.99K_0402_1% VGA@
12
R495 56_0402_1%
VGA@
1 2
R494
4.99K_0402_1%
VGA@
12
C514
10U_0603_6.3V6M
VGA@
1
2
C521
0.01U_0402_16V7K
VGA@
1
2
R481
4.99K_0402_1% VGA@
12
C494
1U_0402_6.3V6K
VGA@
1
2
R483
0_0402_5%
12
C500
1U_0402_6.3V6K
VGA@
1
2
C519
10U_0603_6.3V6M
VGA@
1
2
C484
0.1U_0402_16V4Z
VGA@
1
2
R478
4.99K_0402_1% VGA@
12
R497 56_0402_1%
VGA@
1 2
R477
4.99K_0402_1% VGA@
12
![](asset-18.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MDB[0..63]
DQMB#1
MAB11
MAB12
MAB4
MAB2
MAB1
MAB0
QSB#3
VRAM_RST#
MAB10
DQMB#3
MAB7
QSB#1
MAB3
VREFDB_Q1
MAB9
ODTB0_1
QSB3
MAB8
VREFCB_A1
MAB5
QSB1
MAB6
QSB#2
DQMB#2
QSB#0
QSB2
QSB0
DQMB#0
MAB8
VRAM_RST#
MAB12
MAB1
VREFDB_Q2
VREFCB_A2
MAB4
MAB7
MAB0
MAB10
MAB3
MAB5
MAB2
MAB9
MAB6
MAB11
QSB#4
DQMB#4
QSB#5
QSB4
QSB5
DQMB#5
ODTB1_1
MAB8
VRAM_RST#
MAB12
MAB1
VREFDB_Q3
VREFCB_A3
MAB4
MAB7
MAB0
MAB10
MAB3
MAB5
MAB2
MAB9
MAB6
MAB11
QSB#6
DQMB#6
QSB#7
QSB6
QSB7
DQMB#7
MAB8
VRAM_RST#
MAB12
MAB1
VREFDB_Q4
VREFCB_A4
MAB4
MAB7
MAB0
MAB10
MAB3
MAB5
MAB2
MAB9
MAB6
MAB11
MDB15
MDB14
MDB10
MDB9
MDB12
MDB13
MDB8
MDB11
MDB25
MDB24
MDB31
MDB29
MDB26
MDB27
MDB30
MDB28
MDB22
MDB21
MDB20
MDB19
MDB17
MDB23
MDB18
MDB16
MDB2
MDB5
MDB3
MDB7
MDB0
MDB6
MDB1
MDB4
MDB44
MDB41
MDB45
MDB43
MDB46
MDB37
MDB39
MDB32
MDB35
MDB38
MDB33
MDB40
MDB36
MDB34
MDB47
MDB42
MDB51
MDB55
MDB50
MDB58
MDB57
MDB61
MDB52
MDB53
MDB48
MDB60
MDB54
MDB49
MDB63
MDB56
MDB62
MDB59
MAB13 MAB13 MAB13 MAB13
VREFCB_A1 VREFCB_A2 VREFDB_Q2VREFDB_Q1
VREFDB_Q3VREFCB_A3 VREFCB_A4 VREFDB_Q4
CLKB1
CLKB1#CLKB1#
CLKB1
CLKB0#
CLKB0 CLKB0
CLKB0#
B_BA0
B_BA1
B_BA2 B_BA2
B_BA0
B_BA1
B_BA2
B_BA0
B_BA1
CKEB0
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#
CKEB1
ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#
ODTB0
ODTB0_1
ODTB1_1
ODTB1
CLKB020
CLKB0#20
CLKB120
CLKB1#20
QSB#[7..0]20
QSB[7..0]20
DQMB#[7..0]20
MDB[0..63]20
MAB[13..0]20
VRAM_RST#20,23
CKEB120
B_BA020
B_BA120
B_BA220
CKEB020
CSB0#_020
WEB0#20
CASB0#20
RASB0#20
CSB1#_020
RASB1#20
CASB1#20
WEB1#20
ODTB020
ODTB120
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG +1.5VSG +1.5VSG+1.5VSG
+1.5VSG +1.5VSG +1.5VSG+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG +1.5VSG
+1.5VSG
+1.5VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
VRAM_DDR3 / Channel B
Custom
24 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Pull high for Madison and Park...
96-BALL
SDRAM DDR3
U16
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
R519
4.99K_0402_1% VGA@
12
C525
0.1U_0402_16V4Z
VGA@
1
2
C530
0.01U_0402_16V7K
VGA@
1
2
C553
10U_0603_6.3V6M
VGA@
1
2
C551
10U_0603_6.3V6M
VGA@
1
2
R509
4.99K_0402_1% VGA@
12
R504
4.99K_0402_1% VGA@
12
R507
4.99K_0402_1% VGA@
12
C558
10U_0603_6.3V6M
VGA@
1
2
R508
4.99K_0402_1% VGA@
12
C529
0.1U_0402_16V4Z
VGA@
1
2
C557
10U_0603_6.3V6M
VGA@
1
2
R523 56_0402_1%
VGA@
1 2
R517
4.99K_0402_1% VGA@
12
R506
4.99K_0402_1% VGA@
12
C539
1U_0402_6.3V6K
VGA@
1
2
C550
1U_0402_6.3V6K
VGA@
1
2
R525
56_0402_1%
VGA@
1 2
R513
0_0402_5%
12
C534
1U_0402_6.3V6K
VGA@
1
2
C542
1U_0402_6.3V6K
VGA@
1
2
C548
1U_0402_6.3V6K
VGA@
1
2
C532
1U_0402_6.3V6K
VGA@
1
2
96-BALL
SDRAM DDR3
U18
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
C556
10U_0603_6.3V6M
VGA@
1
2
C538
1U_0402_6.3V6K
VGA@
1
2
C526
0.1U_0402_16V4Z
VGA@
1
2
C546
1U_0402_6.3V6K
VGA@
1
2
R518
4.99K_0402_1% VGA@
12
C552
10U_0603_6.3V6M
VGA@
1
2
C531
1U_0402_6.3V6K
VGA@
1
2
R514
56_0402_1%
VGA@
1 2
C544
1U_0402_6.3V6K
VGA@
1
2
R499
243_0402_1% VGA@
12
R502
243_0402_1% VGA@
12
R516
4.99K_0402_1% VGA@
12
R503
4.99K_0402_1% VGA@
12
R511
0_0402_5%
12
R500
243_0402_1% VGA@
12
C543
1U_0402_6.3V6K
VGA@
1
2
C524
0.1U_0402_16V4Z
VGA@
1
2
96-BALL
SDRAM DDR3
U15
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
R512
56_0402_1%
VGA@
1 2
C545
1U_0402_6.3V6K
VGA@
1
2
C541
1U_0402_6.3V6K
VGA@
1
2
C536
1U_0402_6.3V6K
VGA@
1
2
C540
1U_0402_6.3V6K
VGA@
1
2
C533
1U_0402_6.3V6K
VGA@
1
2
R522
4.99K_0402_1% VGA@
12
R505
4.99K_0402_1% VGA@
12
C528
0.1U_0402_16V4Z
VGA@
1
2
R526
56_0402_1%
VGA@
1 2
C527
0.1U_0402_16V4Z
VGA@
1
2
R520
4.99K_0402_1% VGA@
12
R524 56_0402_1%
VGA@
1 2
R510
4.99K_0402_1% VGA@
12
R515
4.99K_0402_1% VGA@
12
C555
10U_0603_6.3V6M
VGA@
1
2
C535
1U_0402_6.3V6K
VGA@
1
2
C554
10U_0603_6.3V6M
VGA@
1
2
96-BALL
SDRAM DDR3
U17
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1
NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
C547
1U_0402_6.3V6K
VGA@
1
2
R501
243_0402_1%
VGA@
12
C559
0.01U_0402_16V7K
VGA@
1
2
R521
4.99K_0402_1% VGA@
12
C523
0.1U_0402_16V4Z
VGA@
1
2
C522
0.1U_0402_16V4Z
VGA@
1
2
C537
1U_0402_6.3V6K
VGA@
1
2
C549
1U_0402_6.3V6K
VGA@
1
2
![](asset-19.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDDC_EN
1.5_VDD_PWREN
VGA_PWR_ON
1.5_VDD_PWREN
1.0_EN
VDDC_EN
1.0_EN
VGA_PWR_ON
VGA_PWRGD13,48
PX_EN22,36
1.5_VDD_PWREN 38,48
VGA_PWR_ON 38,42,45VGA_ON36
PE_GPIO113,36 +3VS
+5VS +5VS
+BIF_VDDC
+1.0VSG
+VGA_CORE
+VGA_CORE
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
VGA power sequence and BACO
Custom
25 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
From +VGA_CORE regulator
AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V
30mil20mil
30mil
Delay SUSP# 10ms For VGA Power on control
1.5_VDDC_PWREN
Power Sequence of Whistler and Seymour
(JUMP form +3VS)
+VGA_CORE
+1.5VSG
+1.0VSG
+1.8VSG 20ms
VGA_ON
VGA_PWR_ON
10ms
SUSP#
+3VSG
PE_GPIO1
VGA_PWR_ON >2ms
For PX sequence, >2mS delay is required between
PE_GPIO1 and VGA_PWR_ON
Q24 / Q25 / Q26 / Q27 change to SB00000FG10
20101228
C1105 Change to SE00000I10
20101228
0
0 1
1.5_VDDC_PWREN
VGA_ON
1 0 VGA Power Enable Signal Mapping table
Whislter
+3.3VSG ON
+1.8VSG
+3.3VSG
ON +1.8VSG
+1.0VSG
+VGA_CORE
+1.5VSG
+1.0VSG
+VGA_CORE
+1.5VSG
+VDDCI
ON
ON
ON
ON
ON
ON
OFF
OFF
+BIF_VDDC +VGA_CORE
SUSP#
+1.0VSG
VGA_PWR_ON
VGA_PWR_ON
Combine with +VGA_CORE
1.5_VDDC_PWREN
1.5_VDDC_PWREN
VDDC_EN
1.0_EN VGA_PWR_ON source signal
PX_EN
Normal mode
VGA Muxless with BACO Status Mapping table
BACO mode
1
0 1
R655 0_0402_5%
VGA@
1 2
R653
1K_0402_5%
VGA@
1 2
R119
10K_0402_1%
@
1 2
Q23B
DMN66D0LDW-7_SOT363-6
VGA@
34
5
G
D
S
Q25
AO3416_SOT23-3
VGA@
2
1 3
C1105
22U_0805_6.3V6M
VGA@
1
2
U20
NC7SZ08P5X_NL_SC70-5
VGA@
B
2
A
1Y4
P5
G
3
R649 0_0402_5%
@
1 2
C1103
0.1U_0402_16V4Z
VGA@
1 2
R111 0_0402_5%
VGA@
1 2
G
D
S
Q24
AO3416_SOT23-3
VGA@
2
13
G
D
S
Q27
AO3416_SOT23-3
VGA@
2
1 3
U19
NC7SZ08P5X_NL_SC70-5
VGA@
B
2
A
1Y4
P5
G
3
C1104
0.1U_0402_16V4Z
VGA@
12
R656 0_0805_5%
@
1 2
R651 0_0402_5%
VGA@
1 2
R652
5.11K_0402_1%
VGA@
12
Q23A
DMN66D0LDW-7_SOT363-6
VGA@
61
2
R650 10K_0402_5%
VGA@
1 2
R654
1K_0402_5%
VGA@
1 2
G
D
S
Q22
2N7002K_SOT23-3
VGA@
2
13
G
D
S
Q26
AO3416_SOT23-3
VGA@
2
13
![](asset-1a.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
APU_LVDS_CLK
APU_LVDS_DAT
TRAVIS_CLKP
TL_ENVDD
TL_INVT_PW M
APU_TXOUT_CLK-
APU_TXOUT_CLK+
APU_TXOUT1+
APU_TXOUT1-
APU_TXOUT2+
APU_TXOUT2-
APU_TXOUT0+
APU_TXOUT0-
APU_LVDS_CLK
APU_LVDS_DAT
DP0_TXP0_C
DP0_TXN0_C
DP0_AUXP_C
DP0_AUXN_C
TL_BKOFF#
R_BIAS
APU_INVT_PW M
TRAVIS_CLKN
CLK_SEL
DP0_AUXP_C
DP0_AUXN_C
APU_TXOUT_CLK+ 27
APU_TXOUT_CLK- 27
APU_TXOUT0+ 27
APU_TXOUT0- 27
APU_TXOUT1+ 27
APU_TXOUT1- 27
APU_TXOUT2+ 27
APU_TXOUT2- 27
APU_LVDS_CLK 27
APU_LVDS_DAT 27
TL_BKOFF# 27,36
APU_INVT_PW M 10,27
TRAVIS_CLKN 13
PLT_RST#13,18,29,32
TL_ENVDD27
TL_INVT_PW M 27
TRAVIS_CLKP 13
DP0_AUXP_C8
DP0_AUXN_C8
DP0_TXP0_C8
DP0_TXN0_C8
LVDS_HPD10
+DVDD33
+3VS_ANX
+3VS_ANX
+AVDD12
+3VS_ANX
+AVDD33
+DVDD12
+AVDD33
+DVDD12
+DVDD33
+AVDD12
+3VS +3VS_ANX
+1.2VS +1.2VS_ANX
+3VS_ANX
+1.2VS_ANX
+1.2VS_ANX
+3VS_ANX
+3VS_ANX
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
LVDS Translator-ANX3110
Custom
26 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
40mil
40mil
20mil
20mil
20mil
20mil
Place via on each trace bus and let resistor very close the via
C327
2.2U_0603_6.3V6K
1
2
R400 10K_0402_5%
1 2
C467
0.01U_0402_16V7K
1
2
T37
C567
0.01U_0402_16V7K
1
2
C563
0.1U_0402_16V7K
1
2
C296
0.1U_0402_16V7K
1
2
R566 4.7K_0402_5%
1 2
T26
R411 1M_0402_5%
1 2
L31
FBMA-L11-201209-221LMA30T_0805
12
U3
ANX3110_QFN64_9X9
CFG_SDA
52
AVDD33 25
AVDD12
1
AVSS
2
DPRX_LN0_P
3DPRX_LN0_N
4
LVDS_L2_P 24
DDC_CLK 49
AVSS
5
DPRX_LN1_P
6DPRX_LN1_N
7
LVDS_U1_N 37
AVDD33 8
LVDS_L1_P 22
LVDS_L3_P 29
DVDD12 9
CLK_SEL
10
TEST_EN
11
RESET_L
12
LVDS_L2_N 23
DVDD33 13
DIGON
14
BL_EN 15
GPIO_0
16
OSC_OUT 31
GPIO_1
17
GPIO_2
18
OSC_IN 30
LVDS_L0_N 19
LVDS_L0_P 20
LVDS_L3_N 28
TCK
56
DVDD33 53
LVDS_CLKL_N 26
LVDS_U2_N 40
DVDD12 32
AVDD33 33
VARY_BL 47
LVDS_U0_N 35
LVDS_U0_P 36
LVDS_L1_N 21
LVDS_U1_P 38
AVDD33 39
LVDS_U3_P 45
LVDS_U2_P 41
LVDS_CLKU_N 42
LVDS_CLKU_P 43
LVDS_U3_N 44
DVDD12 46
LVDS_CLKL_P 27
DDC_DATA 50
CFG_SCL
51
POR
34
TDI
55
TDO
54 CPU_VARY_BL 48
TMS
57
DPPX_HPD
58
DVDD12 59
DPRX_AUX_N
60
DPRX_AUX_P
61
AVDD33 63
AVSS
62
R_BIAS
64
PAD
65
R1291 0_0402_5%
1 2
C226 100P_0402_50V8J
1 2
C292
0.1U_0402_16V7K
1
2
C348
0.1U_0402_16V7K
1
2
L33
FBMA-L11-201209-221LMA30T_0805
12
C286
0.1U_0402_16V7K
1
2
C337
0.1U_0402_16V7K
1
2
L30
FBMA-L11-201209-221LMA30T_0805
12
C565
2.2U_0603_6.3V6K
1
2
T38
R402 12K_0402_1%
12
C561
0.1U_0402_16V7K
1
2
R565 4.7K_0402_5%
1 2
C336
0.01U_0402_16V7K
1
2
C317
0.01U_0402_16V7K
1
2
R531 1M_0402_5%
@
12
R532 1M_0402_5%
@
12
C326
0.01U_0402_16V7K
1
2
R410 10K_0402_5%
1 2
C225 0.1U_0402_16V7K
12
C338
0.1U_0402_16V7K
1
2
T39
C566
2.2U_0603_6.3V6K
1
2
R607
0_0805_5%
1 2
C289
0.1U_0402_16V7K
1
2
L32
FBMA-L11-201209-221LMA30T_0805
12
C562
0.01U_0402_16V7K
1
2
T36
C349
2.2U_0603_6.3V6K
1
2
R407 10K_0402_5%
1 2
C564
0.1U_0402_16V7K
1
2
T50
T51
T52
R570
0_0805_5%
1 2
![](asset-1b.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
INVTPWM
VGA_DDC_DATA_C
RED
VGA_DDC_CLK_C
CRT_VSYNC_D
CRT_HSYNC_D
GREEN
VSYNC_L
HSYNC_L
BLUE
+5VS_CRTVCC
DISPOFF#
FCH_CRT_R
FCH_CRT_G
FCH_CRT_B
B+_L
RED
GREEN
BLUECRT_B_R
CRT_G_R
FCH_CRT_HSYNC_R
FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL
CRT_R_R
FCH_CRT_VSYNC_R VSYNC_L
HSYNC_L
VGA_DDC_DATA_C
VGA_DDC_CLK_C
INVTPWM
DISPOFF#
RED
BLUE
GREEN
HSYNC_L
VSYNC_L
VGA_DDC_DATA_C
VGA_DDC_CLK_C
USB20_N2
USB20_P2
FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL VGA_DDC_CLK_C
VGA_DDC_DATA_C
TL_INVT_PWM
TL_BKOFF#
BKOFF#
APU_LVDS_CLK26
APU_LVDS_DAT26
APU_TXOUT2+26
APU_TXOUT2-26
APU_TXOUT_CLK-26
APU_TXOUT_CLK+26
EC_INVT_PWM36
APU_INVT_PWM10,26
USB20_N214
USB20_P214
FCH_CRT_VSYNC15
FCH_CRT_HSYNC15
BKOFF#36
APU_ENVDD10
DMIC_CLK30
DMIC_DATA30
APU_TXOUT1+26
APU_TXOUT1-26
APU_TXOUT0+26
APU_TXOUT0-26
TL_INVT_PWM26
TL_ENVDD26
TL_BKOFF#26,36
FCH_CRT_R15
FCH_CRT_G15
FCH_CRT_B15
FCH_CRT_DDC_SCL15
FCH_CRT_DDC_SDA15
+3VS
+LCDVDD
+5VS
+CRT_VCC
+CRT_VCC
+CRT_VCC
B+
+CRT_VCC
+LCDVDD
+5VALW
+LCDVDD
+LCDVDD
+3VS
+3VS
+CRT_VCC+3VS
+3VS
+CRT_VCC
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
P10-LVDS/CRT CONN
C
27 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
QBL60 LA-7552P
Camera
C R T
For EMI
W=40mils
DDC_MD2
W=40mils
Close to APU
W=60mils
W=60mils
W=60mils
ESD
ESD
For EMI, close to JLVDS1.
For EMI, close to JLVDS1.
For AMD DG-47520-1-10
Panel Backlight Control
Panel LCDVDD Control
Panel PWM Control
C1581
100P_0402_50V8J
@
1
2
C122680P_0402_50V7K @
1 2
C1579
0.1U_0402_16V4Z
1 2
R1635 0_0402_5%
1 2
R1662
2.2K_0402_5%
@
12
L118
CHILISIN NBQ160808T-800Y-N 0603
1 2
C1586
4.7U_0805_10V4Z
1
2
D29
AZC199-02SPR7G_SOT23-3
@
22
33
1
1
Q99A
2N7002DW-7-F_SOT363-6
61
2
R1634 0_0402_5%
1 2
C1590
0.1U_0402_16V4Z
@
1
2
L116
CHILISIN NBQ160808T-800Y-N 0603
1 2
C1577
10P_0402_50V8J
1
2
R1638
150_0402_1%
12
C1570
0.1U_0402_16V4Z
1
2
R1644
2.2K_0402_5%
12
C19
22P_0402_50V8J
@
1
2
C1585
4.7U_0805_10V4Z
1
2
C1571
0.1U_0402_16V4Z
@
1
2
L115
SMD1812P075TF .75A 13.2V
21
R31 0_0402_5%@
1 2
R1657
10K_0402_5%
12
R1656
220K_0402_1%
12
R1637
150_0402_1%
12
G
D
S
Q93
SI2301BDS-T1-E3_SOT23-3
2
1 3
R1660
100K_0402_5%
12
R1677
10K_0402_5%
12
R1652
100_0805_5%
12
C1584
15P_0402_50V8J
1
2
R1670
10K_0402_5%
@
12
R4 0_0402_5%@
1 2
R1659
0_0402_5%
@
1 2
T69 PAD
G
G
JCRT1
SUYIN_070546FR015S263ZR
CONN@
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
D6
AZC199-02SPR7G_SOT23-3
2
2
3
311
C1580
100P_0402_50V8J
1
2
R1640
1K_0402_5%
1 2
D2
AZC199-02SPR7G_SOT23-3
2
2
3
311
R1639
150_0402_1%
12
R1648
1K_0402_5%
1 2
R1642
4.7K_0402_5%
12
R722 0_0402_5%
1 2
C1578
0.1U_0402_16V4Z
1 2
R1653
47K_0402_5%
12
U87
74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
C1573
10P_0402_50V8J
1
2
R1645
2.2K_0402_5%
12
D1
AZC199-02SPR7G_SOT23-3
2
2
3
311
R712 0_0402_5%
1 2
R1641
0_0402_5%
12
C1575
10P_0402_50V8J
1
2
Q101B DMN66D0LDW-7_SOT363-6
34
5
R719 0_0402_5%
1 2
R1651
0_0402_5%
12
R21
0_0402_5%
@
1 2
D30
AZC199-02SPR7G_SOT23-3
@
22
33
1
1
C1574
10P_0402_50V8J
1
2
R1661
2.2K_0402_5%
@
12
D4
RB491D_SOT23-3
2
1
3
C1582
100P_0402_50V8J
@
1
2
C1583
15P_0402_50V8J
1
2
R1655
0_0402_5%
@
1 2
C1587
0.1U_0402_16V4Z
1
2
R718 0_0402_5%@
1 2
R1646
4.7K_0402_5%
12
R1643
0_0603_5%
1 2
C1572
10P_0402_50V8J
1
2
D3
AZC199-02SPR7G_SOT23-3
2
2
3
311
Q92
AP2230_SOT23-3
@
VIN
1
GND
2
VOUT 3
C1589
0.047U_0402_16V7K
JLVDS1
HONDA_LVD-A40SFYG+
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
G1 41
G2 42
G3 43
G4 44
G5 45
R1654
0_0402_5%
@
1 2
C1588
0.1U_0402_16V4Z
1
2
C1576
10P_0402_50V8J
1
2
D14 RB751V_SOD323
@
21
R1650
0_0603_5%
1 2
L119
FBMA-L11-201209-221LMA30T_0805
1 2
Q99B
2N7002DW-7-F_SOT363-6
3
5
4
D8 RB751V_SOD323
@
21
U88
74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R1636 0_0402_5%
1 2
L117
CHILISIN NBQ160808T-800Y-N 0603
1 2
Q101A
DMN66D0LDW-7_SOT363-6
61
2
![](asset-1c.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI_SDATA
HDMI_SCLK
HDMI_HPD
HDMI_R_CK-
HDMI_R_CK+
HDMI_C_CLK-
HDMI_C_CLK+
HDMI_C_TX0- HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D2-
HDMI_R_D2+
HDMI_C_TX0+
HDMI_R_D1+
HDMI_C_TX1-
HDMI_C_TX1+
HDMI_C_TX2+
HDMI_C_TX2-
HDMI_C_TX0+
HDMI_C_CLK-
HDMI_C_CLK+
HDMI_C_TX1-
HDMI_C_TX1+
HDMI_C_TX2+
HDMI_C_TX2-
HDMI_C_TX0-
HDMI_SCLK
HDMI_SDATA
HDMI_HPD
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
HDMI_R_D2-
HDMI_R_D2+
EN_HDMI
+HDMI_5V
HDMI_HPD HDMI_SDATA
HDMI_SCLK
HDMI_R_D1+
HDMI_R_D1- HDMI_R_D1-
HDMI_R_D1+
HDMI_R_CK+HDMI_R_D2+
HDMI_R_CK-
HDMI_R_D2+
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0- HDMI_R_D0-
HDMI_R_D2- HDMI_R_D2-
HDMI_R_D0+ HDMI_R_D0+
APU_HDMI_DATA8
APU_HDMI_CLK8
APU_HDMI_HPD10
SUSP38,45
PCIE_FTX_GRX_N126
PCIE_FTX_GRX_P126
PCIE_FTX_GRX_N136
PCIE_FTX_GRX_P136
PCIE_FTX_GRX_N146
PCIE_FTX_GRX_N156
PCIE_FTX_GRX_P156
PCIE_FTX_GRX_P146
+HDMI_5V_OUT+1.5VS
+3VS
+1.5VS
+HDMI_5V_OUT
+HDMI_5V_OUT
+VSB
+5VS
+HDMI_5V_OUT
+HDMI_5V_OUT
+5VALW
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
HDMI Connector
Custom
28 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
UMA use 604 ohm
VGA use 499 ohm
From APU
Near the connector
W=40mils
For ESD request.
For ESD request.
R784 604_0402_1%
1 2
C1169 0.1U_0402_16V7K
12
C1171 0.1U_0402_16V7K
12
R782 0_0402_5%
1 2
C1166 0.1U_0402_16V7K
12 L38
WCM2012F2SF-900T04_0805
1
122
33
4
4
L40
WCM2012F2SF-900T04_0805
1
122
33
4
4
R746
4.7K_0402_5%
12
L39
WCM2012F2SF-900T04_0805
1
122
33
4
4
D32
AZC099-04S.R7G_SOT23-6
I/O4
6
VDD
5
I/O3
4
I/O2 3
GND 2
I/O1 1
C1172 0.1U_0402_16V7K
12
R795 604_0402_1%
1 2
R792 604_0402_1%
1 2
R783 0_0402_5%
1 2
R775
10K_0402_5%
12
R745
4.7K_0402_5%
12
C1168 0.1U_0402_16V7K
12
R469
100_0402_1%
12
L41
WCM2012F2SF-900T04_0805
1
122
33
4
4
R786 604_0402_1%
1 2
R801
100K_0402_5%
12
G
D
S
Q36
BSH111 1N_SOT23-3
2
13
R762 150K_0402_5%
1 2
JHDMI1
SUYIN_100042MR019S153ZL
CONN@
D2+
1D2_shield
2D2-
3D1+
4D1_shield
5D1-
6D0+
7D0_shield
8D0-
9CK+
10 CK_shield
11 CK-
12 CEC
13 Reserved
14 SCL
15 SDA
16 DDC/CEC_GND
17 +5V
18 HP_DET
19
GND 20
GND 21
GND 22
GND 23
C1592
1U_0603_10V4Z
1
2
R797 604_0402_1%
1 2
R755
0_0402_5%
@
1 2
G
D
S
Q96
SSM3K7002FU_SC70-3
2
13
R779 0_0402_5%
1 2
C1591
1U_0603_10V6K
@1
2
R794 0_0402_5%
1 2
C1601
0.1U_0402_16V7K
1
2
R790 604_0402_1%
1 2
R799 604_0402_1%
1 2
R768
365K_0402_1%
@
12
C1170 0.1U_0402_16V7K
12
R769 0_0402_5%
1 2
R781 0_0402_5%
1 2
R788 604_0402_1%
1 2
G
D
S
Q34
2N7002K_SOT23-3
2
13
R756 0_0402_5%
1 2
G
D
S
Q35
SSM3K7002FU_SC70-3
2
13
G
D
S
Q33
BSH111 1N_SOT23-3
2
13
R765 0_0402_5%
1 2
C1173 0.1U_0402_16V7K
12
R1678
470K_0402_5%
12
R750
2K_0402_1%
12
C1167 0.1U_0402_16V7K
12
F2
0.5A_15V_SMD1812P050TF
2 1
S
G
D
Q95
SI3456BDV-T1-E3 1N TSOP6
3
6
2
4 5
1
8
7
65
4
3
2
1
9
10
D11
L15ESDL5V0NA-4 SLP2510P8
4
5
1
6
2
7
3
9
8
R748
0_0402_5%
1 2
R749
2K_0402_1%
12
8
7
65
4
3
2
1
9
10
D13
L15ESDL5V0NA-4 SLP2510P8
4
5
1
6
2
7
3
9
8
R1679
1.5M_0402_5%
12
![](asset-1d.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+LAN_VDDREG
+LAN_VDDREG
+LAN_SROUT1.05
XTLO
XTLI
XTLO
XTLI
PCIE_FRX_DTX_N0
LAN_WAKE#
+LAN_SROUT1.05
PCIE_FRX_DTX_P0
ISOLATEB
LAN_MDIP3
LAN_MDIP2
LAN_MDIN1
LAN_MDIN2
LAN_MDIP1
LAN_MDIN3
LAN_MDIN0
LAN_MDIP0
+V_DAC
+V_DAC
+V_DAC
+V_DAC
EN_WOL#
+LAN_EVDD10
+LAN_EVDD10
RJ45_TX3+
RJ45_TX2-
RJ45_RX1+
RJ45_RX1-
RJ45_TX3-
RJ45_TX0+
RJ45_TX0-
RJ45_TX2+
LAN_MDIP1
LAN_MDIN1
LAN_MDIN0
LAN_MDIP0
LAN_MDIP3
LAN_MDIN3
LAN_MDIP2
LAN_MDIN2
LAN_WAKE#
RJ45_TX0-
RJ45_TX0+
LAN_MDIN0
LAN_MDIP0
LAN_MDIP1
LAN_MDIN1
RJ45_RX1+
RJ45_RX1-
LAN_MDIP2
LAN_MDIN2
RJ45_TX2+
RJ45_TX2-
RJ45_TX3+
RJ45_TX3-LAN_MDIN3
LAN_MDIP3
RJ45_RX1+
RJ45_TX0+
RJ45_TX2+
RJ45_TX3+
RJ45_RX1-
RJ45_TX0-
RJ45_TX2-
RJ45_TX3-
EN_WOL#
EN_WOL36
PCIE_FTX_C_DRX_N06
PCIE_DTX_C_FRX_P06
PCIE_FTX_C_DRX_P06
PCIE_DTX_C_FRX_N06
CLK_PCIE_LAN#13
CLK_PCIE_LAN13
LAN_CLKREQ#14
PLT_RST#13,18,26,32
FCH_PCIE_WAKE#14,32,36
+LAN_IO
+LAN_IO
+3VALW
+LAN_VDD
+3VS
+LAN_VDD
+LAN_VDD
+LAN_VDD
+LAN_IO
+LAN_IO
+LAN_VDD
+LAN_IO
+5VALW
+LAN_IO
+LAN_IO
GND_LAN
GND_LAN
+LAN_IO
+LAN_IO
GND_LAN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
P25-LAN RTL8111E
Custom
29 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
W=60mils W=60mils
( Should be place within 200 mils )
These components close to Pin 36
These caps close to Pin 12,27,39,42,47,48
1.5A
W=60mils
W=60mils
These caps close to Pin 3,6,9,13,29,41,45
3.3V : Enable switching regulator
0V : Disable switching regulator
W=40mils W=20mils
For ESD request.
ESD
ESD
SOD323 package
R533
100K_0402_5%
1 2
C1624
0.1U_0603_25V7K
1
2
C1633
15P_0402_50V8J
1 2
JLAN1
SANTA_130452-C
PR1-
2
PR1+
1
PR2+
3
PR3+
4
PR3-
5
PR2-
6
PR4+
7
PR4-
8
SHLD2 10
SHLD1 9
C1632
4.7U_0603_6.3V6K
1
2
R546
0_0603_5%
@
1 2
C1617
0.1U_0402_16V7K
1
2
R568
0_0603_5%
@
1 2
C1625
4.7U_0603_6.3V6K
1
2
R553
10K_0402_5%
1 2
G
D
S
Q54
SSM3K7002FU_SC70-3
2
13
R560
0_0603_5%
1 2
R534
220K_0402_5%~N
1 2
C1629 0.1U_0402_16V7K
1 2
C1631
0.1U_0402_16V7K
1
2
C1612
0.1U_0402_16V7K
1
2
C163412P_0402_50V8J
1 2
R550
0_0402_5%
12
R658
0_0603_5%
1 2
D34 LSE-200NX3216TRLF_1206-2@
1 2
D41
PD10943-T7_SOD323-2
@
1
122
D22 LSE-200NX3216TRLF_1206-2@
1 2
C1610
1U_0402_6.3V6K
1
2
R662
15K_0402_5%
1 2
G
D
S
Q91
2N7002K_SOT23-3
2
1 3
C1627
0.1U_0402_16V7K
1
2
D39
PD10943-T7_SOD323-2
@
1
122
C1622
0.1U_0402_16V7K
1
2
J8
JUMP_43X118@
11
2
2
C1630 0.1U_0402_16V7K
1 2
R552 75_0603_1%
1 2
D19
AZC099-04S.R7G_SOT23-6
I/O4
6
VDD
5
I/O3
4
I/O2 3
GND 2
I/O1 1
D31 LSE-200NX3216TRLF_1206-2@
1 2
R661
1K_0402_5%
1 2
R1620
10K_0402_5%
1 2
D38
PD10943-T7_SOD323-2
@
1
122
C1619
0.1U_0402_16V7K
1
2
Y6
25MHZ_12PF_X5H025000FC1H-H
1 2
R1530 75_0603_1%
1 2
R660 10K_0402_5%
1 2
C1616
0.1U_0402_16V7K
1
2
D21 LSE-200NX3216TRLF_1206-2@
1 2
C1614
0.1U_0402_16V7K
1
2
R1106
470_0603_5%
1 2
C1618
0.1U_0402_16V7K
1
2
R563 2.49K_0402_1%
1 2
D7
AZC199-02SPR7G_SOT23-3
@
22
33
1
1
R551 10K_0402_5%
1 2
G
D
S
Q30
SSM3K7002FU_SC70-3
2
13
C1626
0.1U_0402_16V7K
1
2
U49
RTL8111E-VL-CGT_QFN48_6X6
PERSTB
25
HSOP
22
HSON
23
HSIP
17
HSIN
18
REFCLK_P
19
REFCLK_N
20 NC/MDIP2 7
NC/MDIN2 8
NC/MDIP3 10
NC/MDIN3 11
LED3/EEDO 31
LED1/EESK 37
EECS/SCL 30
LED0 40
MDIN1 5
MDIP1 4
MDIN0 2
MDIP0 1
RSET
46
LANWAKEB
28
ISOLATEB
26
CKXTAL1
43
CKXTAL2
44
AVDD10 3
EVDD10 21
DVDD10 29
DVDD10 41
VDDREG
34
ENSWREG
33
DVDD33 27
DVDD33 39
AVDD33 12
DVDD10 13
AVDD33 42
CLKREQB
16
EEDI/SDA 32
AVDD33 47
AVDD33 48
AVDD10 6
AVDD10 9
AVDD10 45
NC/SMBCLK
14
NC/SMBDATA
15
GPO/SMBALERT
38
GND
24
PGND
49 REGOUT 36
VDDREG
35
C1623
0.1U_0402_16V7K
1
2
C1636
120P_1206_2KV NPO
1
2
R561 10K_0402_5%
1 2
L120
4.7UH_SIA4012-4R7M_20%
<BOM Structure>
1 2
C1611
0.1U_0402_16V7K
1
2
D40
PD10943-T7_SOD323-2
@
1
122
G
D
S
Q29
AO3419L_SOT23-3
2
13
C1613
0.1U_0402_16V7K
1
2
C1635
0.01U_0402_16V7K
1 2
C1615
0.1U_0402_16V7K
1
2
R549 75_0603_1%
1 2
D18
AZC099-04S.R7G_SOT23-6
I/O4
6
VDD
5
I/O3
4
I/O2 3
GND 2
I/O1 1
C1628
1U_0402_6.3V6K
1
2
R1529 75_0603_1%
1 2
C1621
0.1U_0402_16V7K
1
2
C1620
0.1U_0402_16V7K
1
2
R647 0_0402_5%
1 2
TS1
S X'FORM_ IH-160 LAN
TCT1
1
TD1+
2
TD1-
3
TCT2
4
TD2+
5
TD2-
6MX2- 19
MX2+ 20
MCT2 21
MX1- 22
MX1+ 23
MCT1 24
TCT3
7
TD3+
8
TD3-
9
TCT4
10
TD4+
11
TD4-
12
MCT3 18
MX3+ 17
MX3- 16
MCT4 15
MX4+ 14
MX4- 13
R562 1K_0402_5%
1 2
![](asset-1e.png)
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
HP_OUTL
HP_OUTR
HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO
HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
HDA_SDIN_AUDIO
AC_JDREF
AC97_VREF
HDA_RST_AUDIO#
HDA_BITCLK_AUDIO
EC_MUTE#
SPKOUT_L1
SPKOUT_L2
SPKOUT_R1
SPKOUT_R2
SPKOUT_R2
SPKOUT_R1
SPKOUT_L2
SPKOUT_L1
PD#
HDA_RST_AUDIO#
SPK_R1
SPK_R2
SPK_L1
SPK_L2
SENSE_AHP_JD
MIC_JD
MIC1_C
MIC2_C
DMIC_DATA_CODEC
DMIC_CLK_CODEC
+3VS_DVDD_R
DMIC_DATA
MIC-1
MIC_JD
HPL
HPRHP_RHP_OUTR
HP_OUTL HP_L
MIC1_RMIC1
MIC2 MIC2_R
MIC-2
DMIC_CLK
HDA_BITCLK_AUDIO_R
HP_JD
HPR
HPL
MIC2
MIC1
SPK_L2
SPK_R1
SPK_L1
SPK_R2
HDA_RST_AUDIO#14
HDA_SDIN0 14
HDA_BITCLK_AUDIO 14
HDA_SYNC_AUDIO 14
HDA_SDOUT_AUDIO 14
EC_MUTE#36
DMIC_DATA27
DMIC_CLK27
EAPD 36
USB20_P114
USB20_N114
SPK_L1 37
SPK_L2 37
SPK_R1 37
SPK_R2 37
+5VS
+VDDA
+3VS
+5VS_PVDD
+5VS
+5VS_PVDD
+MIC1_VREFO_L
+MIC1_VREFO_R
+3VS_DVDD
+1.5VS
+MIC1_VREFO_R
+MIC1_VREFO_L
+3VS_DVDD
+USB_VCCB
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
P26-HD CODEC ALC259
Custom
30 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Close to JSPK1
EMI request 12.24
Change to 0.1U for EMI
R1531
0_0805_5%
12
L121
FBMA-L10-160808-301LMT_2P
1 2
R1540
1K_0402_5%
1 2
C1486
0.1U_0402_16V7K
1
2
C1505
0.1U_0402_16V7K
1
2
R1537
0_0603_5%
12
C1494
10P_0402_50V8J
@1
2
C1482
10U_0603_6.3V6M
1
2
C1478 0.22U_0603_16V7K
@
1 2
U50
ALC269-GR_QFN48_7X7
AVDD1 25
AVDD2 38
AVSS1 26
AVSS2 37
DVDD 1
DVDD_IO 9
DVSS1
7
PVDD1 39
PVDD2 46
PVSS1
42 PVSS2
43 CPVEE 34
JDREF 19
VREF 27
LDO_CAP 28
MIC1_VREFO_R 30
MIC2_VREFO 29
MIC1_VREFO_L
31
CBN
35
CBP
36
SENSE A
13
SENSE B
18
SPK_OUT_L+ 40
SPK_OUT_L- 41
SPK_OUT_R+ 45
SPK_OUT_R- 44
HP_OUT_L 32
HP_OUT_R 33
PCBEEP
12
LINE1_L
23
LINE1_R
24
LINE2_L
14
LINE2_R
15
MIC1_L
21
MIC1_R
22
MIC2_L
16
MIC2_R
17
MONO_OUT 20
RESET#
11
GPIO0/DMIC_DATA
2
GPIO1/DMIC_CLK
3
PD#
4
SYNC 10
BCLK 6
SDATA_OUT 5
SDATA_IN 8
EAPD 47
SPDIFO 48
DVSS2
49
C1495
220P_0402_50V7K
1
2
L109
BLM18PG121SN1D_0603
1 2
C1480 0.22U_0603_16V7K
@
1 2
C1485
0.1U_0402_16V7K
1
2
R1543 0_0402_5%
1 2
C1496
220P_0402_50V7K
1
2
R1545 0_0402_5%
1 2
R1533 0_0603_5%
1 2
R1557 0.1U_0402_16V7K
1 2
C1488
10U_0603_6.3V6M
1
2
C1500
0.1U_0402_16V7K
1
2
R1553
4.7K_0402_5%
@
12
C1477
0.1U_0402_16V7K
1
2
R1546
33_0402_5%
1 2
C1475
10U_0805_10V6K
1
2
C1490 4.7U_0603_6.3V6K
1 2
R1534
0_0603_5%
12
R1552
20K_0402_1%
1 2
C1493 4.7U_0603_6.3V6K
1 2
R1554
75_0603_1%
1 2
C1476
0.1U_0402_16V7K
1
2
R1559 0.1U_0402_16V7K
1 2
C1491
10P_0402_50V8J
@1
2
R1549
39.2K_0402_1%
12
C1487
10U_0805_10V6K
1
2
R1532 0_0603_5%
1 2
R1555
75_0603_1%
1 2
R1541 2.2K_0402_1%
12
C1502
470P_0402_50V7K
1
2
L112
BLM18PG121SN1D_0603
1 2
L110
BLM18PG121SN1D_0603
1 2
C24 0.22U_0603_16V7K
@
1 2
R1547
0_0402_5%
1 2
C1474 1U_0603_10V6K@
1
2
C1483 1U_0603_10V6K@
1
2
C1503
0.1U_0402_16V7K
@
1
2
C1501
10U_0805_10V6K
1
2
R1536 0_0603_5%
1 2
L111
BLM18PG121SN1D_0603
1 2
R1535 0_0603_5%
1 2
C1499
10U_0805_10V6K
@
1
2
R1548
20K_0402_1%
1 2
C1484 0.22U_0603_16V7K
@
1 2
C1498
2.2U_0603_16V6K
1 2
C1481
0.1U_0402_16V7K
1
2
C1504
470P_0402_50V7K
1
2
R1590
0_0402_5%
1 2
C1492
22P_0402_50V8J
@
1
2
R1556 0.1U_0402_16V7K
1 2
C1497 2.2U_0603_16V6K
1 2
R1539
1K_0402_5%
1 2
R1558 0.1U_0402_16V7K
1 2
JAU1
ACES_87213-1400G
1
12
23
34
45
56
67
78
89
910
10 11
11 12
12 13
13 14
14
L108
MBK1608800YZF 0603
12
R1542 2.2K_0402_1%
12
R1538
0_0402_5%
@
12
![](asset-1f.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDCLK_MSD2
SDWP_MSCLK
MS_INS#
MS_INS#
MS_BS
MS_BS
MSD0
CLK_SD_48M
SDCD#
SDCMD
SDD3_MSD1
SDD2
+RREF
+CARDPWR
+VREG
+3VS_CR
SDD1
SDD0
USB20_N4
USB20_P4
SDD2
SDCD#
SDD0
SDD1
SDCMD
MSD0
MSD3
MSD3
SDD3_MSD1
SDCLKMSD2 SDCLK_MSD2
SDCLK_MSD2
SDWP_MSCLK
SDWP_MSCLK SDWP_MSCLK_R
CLK_SD_48M 13
USB20_P414
USB20_N414
+CARDPWR
+3VS +3VS_CR
+CARDPWR
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
P27-RTS5137 Media Card Controller
Custom
31 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Card Reader RTS5137
(only SD/MMC/MS function)
Close to connector
30mil
30mil
12mil
10mil
30mil
EMI
EMI Close to U51
+RREF & +VREF need 12mils
R1561
33_0402_5%
1 2
C1515
0.1U_0402_16V4Z
1
2
C1513
0.1U_0402_16V4Z
1
2
C787
0.1U_0402_16V4Z
@
1 2
R1562
100K_0402_5%
@
1 2
C1509
22P_0402_50V8J
<BOM Structure>
1 2
R529
0_0402_5%
1 2
RTS5137-GR_QFN24_4X4
U51
REFE
1
DM
2
DP
3
3V3_IN
4
CARD_3V3
5
V18
6
NC
7
SP1
8
SP2
9
SP3
10
SP4
11
SP5
12 SP6 13
SP7 14
SP8 15
SP9 16
GPIO0 17
SP10 18
SP11 19
SP12 20
SP13 21
SP14 22
NC 23
CLK_IN 24
EPAD
25
R1560 0_0603_5%
1 2
C1511
0.1U_0402_16V4Z
1
2
R1733
6.2K_0603_1%
1 2
C1507 100P_0402_50V8J
@
12
C1510
4.7U_0805_10V4Z
1
2
C788
0.1U_0402_16V4Z
@
1 2
R441 0_0402_5%
1 2
JCR1
TAITW_R009-142-HM
CONN@
SD-CD
1
MS-GND
20 SD-D3
19
MS-D0
10
SD-D1
3
SD-CMD
16 MS-D3
15 MS-INS
14 SD-GND
13 MS-D2
12 SD-VCC
11
MS-VCC
18
MS-D1
9
MS-BS
7SD-GND
6
SD-D0
4
MS-GND
5
SD-CLK
8
SD-WP
2
MS-SCLK
17
SD-D2
21
GND
23 GND
22
C1512
1U_0402_6.3V6K
1
2
C1514
0.1U_0402_16V4Z
1
2
![](asset-20.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MINI1_CLKREQ#
FCH_SMCLK0_R
FCH_SMDAT0_R
EC_TX_P80_DATA
EC_RX_P80_CLK
WLAN_R_LED#
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB
CLK_PCI_DB
PCI_RST#_R
EC_TX_P80_DATA_R
WLAN_WAKE#
PLT_RST#
WLAN_R_LED# WLAN_D_LED#
BT_ON
EC_RX_P80_CLK_R
BT_ON
BT_R_LED#
BT_R_LED#
WLAN_LED#
BT_LED#
PWR_LED#
CHARGE_LED1#
CHARGE_LED0#
WLAN_D_LED#
SATA_LED#
NUM_LED#
CAPS_LED#
CLK_PCI_DB
FCH_PCIE_WAKE#14,29,36
MINI1_CLKREQ#14
USB20_N3 14
USB20_P3 14
PLT_RST# 13,18,26,29
WL_OFF#_EC 36
EC_TX_P80_DATA36
EC_RX_P80_CLK36
FCH_SCLK0 11,12,14
FCH_SDATA0 11,12,14
PCIE_FTX_C_DRX_N16
PCIE_FTX_C_DRX_P16
PCIE_DTX_C_FRX_N16
PCIE_DTX_C_FRX_P16
LPC_AD2 13,36
LPC_AD1 13,36
LPC_AD3 13,36
LPC_AD0 13,36
LPC_FRAME# 13,36
CLK_PCI_DB 13
CLK_PCIE_MINI1#13
CLK_PCIE_MINI113
WL_OFF# 15
SATA_LED#15
PWR_LED#35,36
CHARGE_LED1#36
CHARGE_LED0#36
RF_LED#36
CAPS_LED#36
BT_ON15
WLAN_LED# 36
BT_LED# 36
SUSP#36,38
NUM_LED#36,37
+3VS_WLAN
+3VS
+3VALW
+3VALW
+1.5VS
+3VS_WLAN+3VS
+1.5VS
+3VS
+3VS
+3VALW
+3VALW
+3VALW
+3VS
+5VALW
+3VALW
+5VALW
+3VS_WLAN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
P28-Mini PCIE/LED
32 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
QBL60 LA-7552P
Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card(WLAN/WiMAX)
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
For EC to detect
debug card insert.
LED
White
White
Orange BATT_LOW_LED#
BATT_CHG_LED#
Green
Add to prevent leakage issue.
Green
Green
ESD
EMI
W=60mils
R1588100_0402_5%
12
R1577
0_0402_5%
12
D35
YSDA0502C 3P C/A SOT-23
@
2
3
1
R1571 0_0402_5%@
1 2
C1517
0.1U_0402_16V4Z
1
2
R1591100_0402_5%
12
R1572 0_0402_5%@
1 2
R1563
0_1206_5%
@
12
R1583
100K_0402_5%
1 2
R1579 0_0402_5%
1 2
R1593100_0402_5%
12
R1586100_0402_5%
12
R1578 0_0402_5%
1 2
R1566 0_0402_5%
1 2
R1564
0_1206_5%
12
G
D
S
Q31
AO3413_SOT23-3
2
13
D24
RB751V_SOD323
@
21
C1518
0.1U_0402_16V4Z
1
2
LED3
19-21SYGC/S530-E3/TR8 0603 Y/G
21
C124
10P_0402_50V8J
@
1 2
LED1
19-21SYGC/S530-E3/TR8 0603 Y/G
21
R1568 0_0402_5%
1 2
R115 0_0402_5%
1 2
R1573 0_0402_5%
1 2
R1575
0_0402_5%
12
R1565 0_0402_5%
@
1 2
R1580 0_0402_5%
1 2
D36
YSDA0502C 3P C/A SOT-23
@
2
3
1
R1567 0_0402_5%@
1 2
R1589 0_0402_5%
1 2
R1594 0_0402_5%@
1 2
LED6
19-21SYGC/S530-E3/TR8 0603 Y/G
21
O
W
LED2
HT-297DQ/GQ 0603 AMB/YG
21
43
C1663
0.1U_0603_25V7K
1
2
D26
YSDA0502C 3P C/A SOT-23
@
2
3
1
C1516
0.1U_0402_16V4Z
@
1
2
R1581
100_0402_1%
1 2
D25
RB751V_SOD323
@
21
R1582
100_0402_1%
@
1 2
R1596
0_1206_5%
12
R1576 0_0402_5%
1 2
R1574 0_0402_5%
1 2
JMINI1
BELLW_80003-1021
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
GND1
53
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 54
LED4
19-21SYGC/S530-E3/TR8 0603 Y/G
21
R1570 0_0402_5%@
1 2
R669
10K_0402_5%
1 2
R1569 0_0402_5%@
1 2
C1664
1U_0402_6.3V6K
1
2
D37
YSDA0502C 3P C/A SOT-23
@
2
3
1
R663
100K_0402_5%
1 2
R530
0_0402_5%
@
12
R1585300_0402_5%
12
G
D
S
Q32
SSM3K7002FU_SC70-3
2
13
R1584100_0402_5%
12
![](asset-21.png)
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
SATA_DTX_SRX_P1
SATA_DTX_SRX_N1
SATA_DTX_C_SRX_P0
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
SATA_DTX_C_SRX_N0
+5VS_HDD
+5VS_ODD
SATA_STX_DRX_P0
SATA_STX_DRX_N0
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
SATA_DTX_C_SRX_P115
SATA_DTX_C_SRX_N115
SATA_STX_DRX_P115
SATA_STX_DRX_N115
SATA_STX_DRX_P015
SATA_DTX_C_SRX_N015
SATA_DTX_C_SRX_P015
SATA_STX_DRX_N015
+3VS
+5VS
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
P29-HDD & ODD CONN
B
33 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
QBL60 LA-7552P
SATA ODD FFC Conn.
SATA HDD Conn.
80mils
C648 0.01U_0402_16V7K
1 2
C660
10U_0603_6.3V6M
1
2
R1595 0_0805_5%
1 2
C22
0.1U_0402_16V4Z
1
2
JODD1
OCTEK_SLS-13DC1G_RV
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
DP
8
+5V
9
+5V
10
MD
11
GND
12
GND
13
GND 14
GND 15
C661
1U_0402_6.3V4Z
1
2
C662
0.1U_0402_16V4Z
1
2
R670 10K_0402_5%
@
1 2
JHDD1
SUYIN_127043FR022S21MZR
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
V33
8
V33
9
V33
10
GND
11
GND
12
GND
13
V5
14
V5
15
V5
16
GND
17
Reserved
18
GND
19
V12
20
V12
21
V12
22
GND1 23
GND2 24
C656 0.01U_0402_16V7K
1 2
C663
1000P_0402_50V7K
1
2
R1598 0_0805_5%
1 2
C649 0.01U_0402_16V7K
1 2
C1520 0.01U_0402_16V7K
1 2
C1521 0.01U_0402_16V7K
1 2
C658 0.01U_0402_16V7K
1 2
C1519 0.01U_0402_16V7K
1 2
C1522 0.01U_0402_16V7K
1 2
![](asset-22.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB20_N0_C
USB20_P0_C
USB20_P10_C
USB20_N10_C
USB_ON#
USB_ON#
USB30_MTX_C_DRX_P0_C
USB30_MTX_C_DRX_N0_C
USB30_MRX_DTX_P0_C
USB30_MRX_DTX_N0_C
USB30_MTX_C_DRX_N0
USB30_MRX_DTX_P0
USB30_MTX_C_DRX_P0
USB30_MTX_C_DRX_N0_C
USB30_MTX_C_DRX_P0_C
USB30_MRX_DTX_P0_C
USB30_MRX_DTX_N0_C
USB30_MTX_C_DRX_P0_CUSB30_MTX_C_DRX_P0_C
USB30_MTX_C_DRX_N0_CUSB30_MTX_C_DRX_N0_C
USB30_MRX_DTX_N0_CUSB30_MRX_DTX_N0_CUSB30_MRX_DTX_N0
USB30_MRX_DTX_P0_CUSB30_MRX_DTX_P0_CUSB30_MRX_DTX_P0_CUSB30_MRX_DTX_P0_C
USBAI_PEN#
USB20_N0
USB20_P0 USB20_P0_U
USB20_N0_U
USB20_P0_U
USB20_N0_U USB20_N0_C
USB20_P0_C
USB20_P0_C
USB20_N0_C
USB30_MTX_C_DRX_P0_C
USB30_MTX_C_DRX_N0_C
USB30_MRX_DTX_P0_C
USB30_MRX_DTX_N0_C
USB20_N10_C
USB20_P10_C
USB20_P10
USB20_N10
USB20_P10_C
USB20_N10_C
USB_OC0# 14
USB_ON#36 USB_OC1# 14
USB30_MTX_C_DRX_P014
USB30_MTX_C_DRX_N014
USB30_MRX_DTX_N014
USB30_MRX_DTX_P014
USBAI_PEN#36
USBAI_EN36
USB20_P014
USB20_N014
USB_OC2# 14
CEN# 36
USB20_N1014
USB20_P1014
+USB_VCCA
+USB_VCCA
+5VALW
+USB_VCCC
+USB_VCCB
+5VALW
+5VALW
+USB_VCCC
+5VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
1.0
P32-USB/BT/USBsub
Custom
34 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
QBL60 LA-7552P
W=80mils
Left USB Conn.
W=80mils
Left USB Conn.
EMI request
Low Active
Low Active
For ESD request.
Low Active
Right USB Conn.
Left USB Conn.
Left USB Conn.
AI CHARGER
CB=0
CB=1 Connect DP/DM to TDP/TDM
Auto detection charger identification active
For ESD request.
U54
AP2301MPG-13 MSOP 8P
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
U2
MAX14566EETA+_TDFN-EP8_2X2~D
<BOM Structure>
CEN 1
DP 3
GND 4
DM 2
VCC
5TDP
6
CB
8
TDM
7
GND 9
JUSB2
SINGA_2UB4016-000101
VBUS
1
D-
2
D+
3
GND
4
GND
10
GND
11
GND
12
GND
13
StdA_SSRX-
5
StdA_SSRX+
6
7
7
StdA_SSTX-
8
StdA_SSTX+
9
JUSB1
SUYIN_020173MR004S50DZL
CONN@
VCC
1
D-
2
D+
3
GND
4
GND1
5
GND2
6
GND3
7
GND4
8
D20
AZC099-04S.R7G_SOT23-6
I/O4
6
VDD
5
I/O3
4
I/O2 3
GND 2
I/O1 1
C714 0.1U_0402_16V4Z
12
C709
47U_0805_6.3V
1
2
L55
S COM FI_ KINGCORE WCM-2012HS-900T
1
1
4
433
22
L62
WCM-2012HS-900T
M3@
1
122
33
4
4
C710
1000P_0402_50V7K@
1
2
C713
1000P_0402_50V7K@
1
2
C711
470P_0402_50V7K
1
2
C712
47U_0805_6.3V
1
2
U55
AP2301MPG-13 MSOP 8P
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
R1016
100K_0402_5%
12
C708
470P_0402_50V7K
1
2
C716
1000P_0402_50V7K@
1
2
C715 0.1U_0402_16V4Z
12
R949 0_0402_5%
1 2
L58
S COM FI_ KINGCORE WCM-2012HS-900T
1
1
4
433
22
CU1546 0.1U_0402_16V4Z
1
2
8
7
65
4
3
2
1
9
10
D5
AZ1045-04F DFN2510P10E ESD
M3@
4
5
1
6
2
7
3
9
8
C707 0.1U_0402_16V4Z
12
U56
AP2301MPG-13 MSOP 8P
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
L60
WCM-2012HS-900T
M3@
1
122
33
4
4
![](asset-23.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EC_SPICLK_REC_SPI_W P#
EC_SO_SPI_SI_R
+SPI_VCC
EC_SI_SPI_SO_R
EC_SPICS#/FSEL#
EC_SPI_HOLD#
ON/OFFBTN#
EC_ON
ON/OFFBTN#ON/OFFBTN#
LID_SW#
FAN_SPEED
+5VS_FAN
FAN_SPEED
EC_SPICS#/FSEL#36
EC_SPICLK 36
EC_SO_SPI_SI 36
EC_SI_SPI_SO 36
EC_ON36
ON/OFF# 36
51_ON# 40
PW R_LED# 32,36
LID_SW# 36
FAN_SET36
FAN_SPEED36
+3VALW
+3VALW
+3VALW
+5VALW
+3VALW
+5VS+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
P31-KB /SW/TP/Lid
B
35 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
QBL60 LA-7552P
EC BIOS ROM
Place SW4 on Bottom Side.
ON/OFF switch Power Button
Change to SC600000B00
Fan Control Circuit
R1050 4.7K_0402_5%
1 2
U42
MX25L1606EM2I-12G SOP 8P
SA000041N00
CS#
1
SO 2
WP#
3
GND
4SI 5
SCLK 6
HOLD#
7
VCC 8
C1370 0.1U_0402_16V4Z
1 2
C703
10U_0603_6.3V6M
1
2
C702
1000P_0402_50V7K~N
1
2
R1053 0_0402_5%
1 2
C773
1000P_0402_50V7K
1
2
R1055
33_0402_5%
1 2
C700
1000P_0402_50V7K~N
1
2
C1374
22P_0402_50V8J
1 2
D27
PJSOT24CH_SOT23-3
@
1
2
3
JFAN1
ACES_85205-0300N
CONN@
1
12
23
3
GND
4GND
5
R668
10K_0402_5%
1 2
R527
100K_0402_5%
1 2
R1054 0_0402_5%
1 2
R1049
0_0603_5%
1 2
R528
10K_0402_5%
1 2
JBTN1
ACES_85201-06051
GND 7
GND 8
11
22
33
44
55
66
C701
2.2U_0603_106K
1
2
G
D
S
Q28
SSM3K7002FU_SC70-3
2
13
U53
APL5607KI-TRG_SO8
EN 1
VIN 2
VOUT 3
VSET 4
GND
8
GND
7
GND
6
GND
5
R1051 0_0402_5%
1 2
SW 4
SMT1-05-A_4P
@
3
2
1
4
5
6
R1052 4.7K_0402_5%
1 2
D12
DAN202UT106_SC70-3
2
3
1
![](asset-24.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KSI1
KSI6
KSI5
KSI7
KSO1
KSO0
KSO2
KSO4
KSO3
KSO5
KSO6
KSO7
KSO8
KSO12
KSO10
KSO13
KSO11
KSO9
KSO15
KSO14
KSI2
KSI0
KSI3
KSI4
EC_CRY2
EC_CRY1
LPC_AD0
LPC_AD1
SERIRQ
LPC_AD3
LPC_AD2
LPC_FRAME#
A_RST#
LPC_CLK0_EC
TP_DATA
TP_CLK
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
BKOFF#
EC_SMI#
EC_SCI#
EC_LID_OUT#
SLP_S3#
SLP_S5#
IREF
FAN_SET
FCH_PW RGD
VR_ON
SYSON
EC_GA20
EC_KBRST#
AD_BID0
ECAGND
BATT_TEMP
EC_RSMRST#
FAN_SPEED
CHARGE_LED0#
CHARGE_LED1#
EC_RX_P80_CLK
EC_TX_P80_DATA
+EC_VCCA
ECAGND
ECAGND
EC_SPICLK_L
ACOFF
ADP_I
EC_MUTE#
PW R_LED#
VLDT_EN
EN_WOL
PBTN_OUT#
SUSP#
CHGVADJ
EC_CRY1 EC_CRY2
EC_INVT_PW M
EC_SPICLK_L
LID_SW#
PE_GPIO1
ACIN
ON/OFF#
EC_ON
EAPD
ACIN
KSO1
KSO2
EC_SMB_DA1
EC_SMB_CK1
EC_SMB_CK2
EC_SMB_DA2
KSI[0..7]
KSO[0..15]
ENBKL
TP_DATA
TP_CLK
NUM_LED#
USB_ON#
WLAN_LED#
LID_SW#
FCH_PW RGD
CAPS_LED#
BT_LED#
USB_ON#
EC_SMI#
EC_MUTE#
EC_SCI#
EC_PME#
EC_PME#
EC_THERM#
TL_BKOFF#
USBAI_EN
USBAI_PEN#
ENBKL
ENBKL
PX_EN
LPC_FRAME#13,32
LPC_AD213,32
LPC_AD013,32
LPC_AD313,32
LPC_AD113,32
SERIRQ13
A_RST#13
LPC_CLK0_EC13,16
TP_DATA 37
TP_CLK 37
EC_SMB_DA140
EC_SMB_CK26,19
EC_SMB_DA26,19
EC_SMB_CK140
FSTCHG 39
EC_SMI#14
BKOFF# 27
EC_SCI#14
SLP_S3#14
SLP_S5#14 EC_LID_OUT# 14
FAN_SET 35
IREF 39
VR_ON 47
SYSON 38,43
EC_KBRST#14
EC_GA2014
BATT_TEMP 40
EC_RSMRST# 14
FAN_SPEED35
EC_SPICS#/FSEL# 35
EC_SO_SPI_SI 35
EC_SI_SPI_SO 35
ACOFF 39
ADP_I 39
EC_MUTE# 30
PW R_LED# 32,35
VLDT_EN 38,46
PBTN_OUT# 14
SUSP# 32,38
CHGVADJ 39
VGA_ON 25
EC_INVT_PW M27
EC_SPICLK 35
RTC_CLK13,16
FCH_PW RGD 14
EC_RX_P80_CLK32
EC_TX_P80_DATA32
EC_ON 35
ACIN 39
EAPD 30
KSI[0..7] 37
KSO[0..15] 37
AD_BID0 37
ON/OFF#35
NUM_LED#32,37
USB_ON# 34
WLAN_LED# 32
PE_GPIO1 13,25
LID_SW# 35
VGATE 47
EN_WOL 29
CHARGE_LED0# 32
CAPS_LED# 32
CHARGE_LED1# 32
RF_LED# 32
WL_OFF#_EC 32
BT_LED# 32
FCH_PCIE_W AKE#14,29,32
EC_THERM# 8,13,47
TL_BKOFF# 26,27
USBAI_EN34
USBAI_PEN#34
ENBKL 10
CEN# 34
PX_EN 22,25
+3VALW
+3VALW
+3VALW
+3VS
+3VALW
+3VALW
+5VS
+3VS
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
EC ENE KB930
B
36 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
20mil
Delay SUSP# 10ms
Reserve for EMI, close to EC
Delay EC_PWROK 50ms
for VGA criterial
BATT
APU/VGA
HI:2.4V
LOW: 0.8V
HI:2.4V
LOW: 0.8V
R10184.7K_0402_5%
12
R1015 10K_0402_5%@
1 2
C1361
15P_0402_50V8J
@
1
2
L66
FBM-11-160808-601-T_0603
1 2
R1616 10K_0402_5%
1 2
R1020 2.2K_0402_5%
@
1 2
R10194.7K_0402_5%
12
R1014 33_0402_5%
@
12
R1032
10K_0402_5%
@
12
C1349
1000P_0402_50V7K
1
2
C1348
0.1U_0402_16V4Z
1
2
L65
BLM18AG601SN1D_2P
1 2
R1021 2.2K_0402_5%
1 2
C1351
0.1U_0402_16V4Z
1
2
R37 10K_0402_5%
1 2
R1027 2.2K_0402_5%
1 2
R1623 10K_0402_5%
1 2
R30 0_0402_5%
1 2
C1353 0.1U_0402_16V4Z
12
C1347
0.1U_0402_16V4Z
1
2
R1034100K_0402_5%
@
1 2
R1030 47K_0402_5%
1 2
C1350
1000P_0402_50V7K
1
2
C1346
0.1U_0402_16V4Z
1
2
R1033
FBMA-10-100505-101T
1 2
X2
32.768KHZ_12.5PF_Q13MC14610002
@
OSC 4
OSC 1
NC
3
NC
2
C1362
15P_0402_50V8J
@
1
2
R1028 2.2K_0402_5%
1 2
R2 0_0402_5%
@
1 2
R1036 0_0402_5%
1 2
R1022 2.2K_0402_5%
1 2
C1352
22P_0402_50V8J
@
12
R32 0_0402_5%
@
1 2
C1360 100P_0402_50V8J
12
C1345
0.1U_0402_16V4Z
1
2
R1035 10K_0402_5%
@
1 2
R1617 10K_0402_5%
@
1 2
LPC & MISC
Int. K/B
Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U31
KB930QF A1 LQFP 128P
GA20/GPIO00
1
KBRST#/GPIO01
2
SERIRQ#
3
LFRAME#
4
LAD3
5
PM_SLP_S3#/GPIO04
6
LAD2
7
LAD1
8
VCC 9
LAD0
10
GND
11
PCICLK
12
PCIRST#/GPIO05
13
PM_SLP_S5#/GPIO07
14
EC_SMI#/GPIO08
15
LID_SW#/GPIO0A
16
SUSP#/GPIO0B
17
PBTN_OUT#/GPIO0C
18
EC_PME#/GPIO0D
19
SCI#/GPIO0E
20
INVT_PWM/PWM1/GPIO0F 21
VCC 22
BEEP#/PWM2/GPIO10 23
GND
24
EC_THERM#/GPIO11
25
FANPWM1/GPIO12 26
ACOFF/FANPWM2/GPIO13 27
FAN_SPEED1/FANFB1/GPIO14
28
FANFB2/GPIO15
29
EC_TX/GPIO16
30
EC_RX/GPIO17
31
ON_OFF/GPIO18
32
VCC 33
PWR_LED#/GPIO19
34
GND
35
NUMLED#/GPIO1A
36
ECRST#
37
CLKRUN#/GPIO1D
38
KSO0/GPIO20
39
KSO1/GPIO21
40
KSO2/GPIO22
41
KSO3/GPIO23
42
KSO4/GPIO24
43
KSO5/GPIO25
44
KSO6/GPIO26
45
KSO7/GPIO27
46
KSO8/GPIO28
47
KSO9/GPIO29
48
KSO10/GPIO2A
49
KSO11/GPIO2B
50
KSO12/GPIO2C
51
KSO13/GPIO2D
52
KSO14/GPIO2E
53
KSO15/GPIO2F
54
KSI0/GPIO30
55
KSI1/GPIO31
56
KSI2/GPIO32
57
KSI3/GPIO33
58
KSI4/GPIO34
59
KSI5/GPIO35
60
KSI6/GPIO36
61
KSI7/GPIO37
62
BATT_TEMP/AD0/GPIO38 63
BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65
AD3/GPIO3B 66
AVCC 67
DAC_BRIG/DA0/GPIO3C 68
AGND
69
EN_DFAN1/DA1/GPIO3D 70
IREF/DA2/GPIO3E 71
DA3/GPIO3F 72
CIR_RX/GPIO40 73
CIR_RLC_TX/GPIO41 74
AD4/GPIO42 75
SELIO2#/AD5/GPIO43 76
SCL1/GPIO44
77
SDA1/GPIO45
78
SCL2/GPIO46
79
SDA2/GPIO47
80
KSO16/GPIO48
81
KSO17/GPIO49
82
PSCLK1/GPIO4A 83
PSDAT1/GPIO4B 84
PSCLK2/GPIO4C 85
PSDAT2/GPIO4D 86
TP_CLK/PSCLK3/GPIO4E 87
TP_DATA/PSDAT3/GPIO4F 88
FSTCHG/SELIO#/GPIO50 89
BATT_CHGI_LED#/GPIO52 90
CAPS_LED#/GPIO53 91
BATT_LOW_LED#/GPIO54 92
SUSP_LED#/GPIO55 93
GND
94
SYSON/GPIO56 95
VCC 96
SDICS#/GPXOA00 97
SDICLK/GPXOA01 98
SDIDO/GPXOA02 99
EC_RSMRST#/GPXO03 100
EC_LID_OUT#/GPXO04 101
EC_ON/GPXO05 102
EC_SWI#/GPXO06 103
ICH_PWROK/GPXO06 104
BKOFF#/GPXO08 105
WL_OFF#/GPXO09 106
GPXO10 107
GPXO11 108
SDIDI/GPXID0 109
PM_SLP_S4#/GPXID1 110
VCC 111
ENBKL/GPXID2 112
GND
113
GPXID3 114
GPXID4 115
GPXID5 116
GPXID6 117
GPXID7 118
SPIDI/RD# 119
SPIDO/WR# 120
VR_ON/XCLK32K/GPIO57 121
XCLK1
122
XCLK0
123 V18R 124
VCC 125
SPICLK/GPIO58 126
AC_IN/GPIO59 127
SPICS# 128
R1619 10K_0402_5%
1 2
C1358
22P_0402_50V8J
1
2
R1011 47K_0402_5%
12
R1029 47K_0402_5%
1 2
R1037
100K_0402_5%
12
C1357 33P_0402_50V8K
@
R29 0_0402_5%
1 2
R1023 2.2K_0402_5%@
1 2
C1363 100P_0402_50V8J
12
C1359
4.7U_0603_6.3V6K
1
2
![](asset-25.png)
KSO6
KSO8
KSO4
KSO2
KSO1
KSO5
KSI5
KSI4
KSO9
KSI6
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSI3
KSI2
KSI1
KSO[0..15]
KSI[0..7]
KSO2
KSO15
KSO6
KSO8
KSO13
KSO12
KSO11
KSO10
KSO3
KSO4
KSI0
KSO0
KSO1
KSO7
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1
KSO0
KSI7
KSO7
SW /R
SW /L
TP_CLK
TP_DATA
SW /L SW /R
SPK_L2
SPK_R1
SPK_L1
SPK_R2
AD_BID0
KSI0
KSO[0..15] 36
KSI[0..7] 36
TP_CLK36
TP_DATA36
NUM_LED#32,36
SPK_L130
SPK_L230
SPK_R130
SPK_R230
AD_BID0 36
+5VS
+3VS
+3VALW
+VGA_CORE
+CPU_CORE_NB
+1.5VSG +CPU_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
P33-Other IO/USB (right)
Custom
37 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
QBL60 LA-7552P
INT_KBD Conn.
CONN PIN define need double check
Pin define
Reserve for ESD
To TP/B Conn.
Green
BRD IDID
3
VabRbRa
34.8K
100K
100K
100K
100K
56.2K
46.4K
26.1K 0.683V
1.187V
1.045V
0.851V
2
1
0
Reserve
R10 PR
R02 ER
R01 SR
Ra
Rb
Analog Board ID definition
Place SW5 for TP Left switch. Place SW6 for TP Right switch.
C1555 100P_0402_50V8J@
1 2
H19
H_4P2
@
1
H7
H_3P8
@
1
C1559 100P_0402_50V8J@
1 2
+
C374
330U_2.5V_M
VGA@
1
2
D28
YSDA0502C 3P C/A SOT-23
@
2
3
1
+
C1010
390U_2.5V_10M
1
2
C1545 100P_0402_50V8J@
1 2
D10
PJMBZ6V8_SOT23-3
@
2
3
1
D17
YSDA0502C 3P C/A SOT-23
@
2
3
1
R1026
46.4K_0402_1%
1 2
H11
H_3P0
@
1
+
C560
390U_2.5V_10M
VGA@
1
2
FD1
FIDUCIAL_C40M80
1
+
C435
390U_2.5V_10M
VGA@
1
2
C1546 100P_0402_50V8J@
1 2
C1562 100P_0402_50V8J@
1 2
C1556 100P_0402_50V8J@
1 2
+
C995
330U_D2_2V_Y
@
1
2
SW 5
NTC010-BB1G-C100C
2
3
1
4
5
C1561 100P_0402_50V8J@
1 2
H20
H_3P0
@
1
R1024
100K_0402_5%
1 2
LED5
19-21SYGC/S530-E3/TR8 0603 Y/G
21
C1563 100P_0402_50V8J@
1 2
C1564 100P_0402_50V8J@
1 2
C1543 100P_0402_50V8J@
1 2
C1551 100P_0402_50V8J@
1 2
C1557 100P_0402_50V8J@
1 2
FD4
FIDUCIAL_C40M80
1
ZZZ
PCB
C1567
0.1U_0402_16V4Z H22
H_3P0
@
1
H18
H_4P2
@
1
C1547 100P_0402_50V8J@
1 2
H14
H_3P0
@
1
+
C474
390U_2.5V_10M
VGA@
1
2
+
C1011
390U_2.5V_10M
1
2
C1544 100P_0402_50V8J@
1 2
H6
H_3P8
@
1
C1560 100P_0402_50V8J@
1 2
H16
H_4P2
@
1
H13
H_3P0
@
1
C1566 100P_0402_50V8J@
1 2
C1558 100P_0402_50V8J@
1 2
JSPK1
ACES_88266-04001
1
1
2
2
3
3
4
4G1 5
G2 6
H2
H_6P2X3P2
@
1
H8
H_3P0
@
1
SW 6
NTC010-BB1G-C100C
2
3
1
4
5
FD2
FIDUCIAL_C40M80
1
R1592100_0402_5%
12
C1548 100P_0402_50V8J@
1 2
H24
H_3P2
@
1
H3
H_3P0
@
1
C1553 100P_0402_50V8J@
1 2
C1568
100P_0402_50V8J
@
1
2
H1
H_3P0
@
1
H5
H_3P8
@
1
H25
H_3P3
@
1
C1549 100P_0402_50V8J@
1 2
C1554 100P_0402_50V8J@
1 2
FD3
FIDUCIAL_C40M80
1
+
C436
390U_2.5V_10M
VGA@
1
2
JKB1
ACES_88514-02401-071
1
12
23
34
45
56
67
78
89
910
10 11
11 12
12 13
13 14
14 15
15 16
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24
GND1
25 GND2
26
C1550 100P_0402_50V8J@
1 2
C1565 100P_0402_50V8J@
1 2
C1552 100P_0402_50V8J@
1 2
H17
H_4P2
@
1
H23
H_3P8
@
1
D9
PJMBZ6V8_SOT23-3
@
2
3
1
H15
H_3P0
@
1
JTP1
ACES_88514-00601-071
1
12
23
34
45
56
6
GND
8
GND
7
H9
H_3P0
@
1
H10
H_3P8
@
1
C1569
100P_0402_50V8J
@
1
2
![](asset-26.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUSP
VGA_PWR_ON#
SYSON#
5VS_GATE
VLDT_EN#
3VS_GATE
1.1VS_GATE
SUSP#
1.5_VDDC_PWREN#
1.5VSG_GATE
1.5_VDDC_PWREN#
1.5_VDDC_PWREN#
VGA_PWR_ON#
VLDT_EN#
SUSPSUSP
VGA_PWR_ON#
SYSON#
VLDT_EN#
SUSP
SUSP
SUSP
SUSP
SUSP
1.5_VDDC_PWREN#
VLDT_EN#
SUSP28,45
1.5_VDD_PWREN25,48
VGA_PWR_ON25,42,45
SYSON36,43
SUSP#32,36
VLDT_EN36,46
+5VALW
+5VALW
+5VALW
+3VALW +3VS
+5VS
+1.8VSG
+VSB
+1.1VALW
+VSB
+1.1VS
+VSB
+VGA_CORE
+1.5VS+1.5V
+1.5V
+VSB
+1.5VSG
+5VALW
+5VALW
+1.2VS
+0.75VS+2.5VS
+1.0VSG
+1.5V
+5VALW
+3VSG+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
DC Interface
B
38 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
+1.5V to +1.5VSG (1.5A)
+3VS to +3VSG (3.3A)
Change to Jump
201012062000
C1452
10U_0603_6.3V6M
1
2
R1135
470_0603_5%
1 2
R1137
470_0603_5%
1 2
R1126
470_0603_5%
VGA@
1 2
C1448
10U_0603_6.3V6M
1
2
R1134
10K_0402_5%
12
C1445
10U_0805_10V4Z
1
2
C1453
10U_0603_6.3V6M
1
2
G
D
S
Q52
SSM3K7002FU_SC70-3
2
13
R1109
10K_0402_5%
12
C1451
0.1U_0603_25V7K
1
2
R1125
470_0603_5%
VGA@
1 2
C1446
10U_0805_10V4Z
1
2
G
D
S
Q51
SSM3K7002FU_SC70-3
2
13
R1131
100K_0402_5%
1 2
G
D
S
Q62
SSM3K7002FU_SC70-3
<BOM Structure>
2
13
G
D
S
Q74
SSM3K7002FU_SC70-3
VGA@
2
13
C1447
10U_0603_6.3V6M
1
2
G
D
S
Q71
SSM3K7002FU_SC70-3
<BOM Structure>
2
13
R1116
100K_0402_5%
1 2
G
D
S
Q68
SSM3K7002FU_SC70-3
2
13
G
D
S
Q56
SSM3K7002FU_SC70-3
2
13
C1463
0.22U_0603_16V4Z
1
2
G
D
S
Q59
SSM3K7002FU_SC70-3
2
13
R1117
470_0603_5%
1 2
R1105 47K_0402_5%
1 2
C1462
0.1U_0603_25V7K
VGA@
1
2
R1128
470_0603_5%
1 2
R1136
470_0603_5%
1 2
C1449
1U_0402_6.3V4Z
1
2
G
D
S
Q65
SSM3K7002FU_SC70-3
VGA@
2
13
R1118 100K_0402_5%
VGA@
1 2
G
D
S
Q72
SSM3K7002FU_SC70-3
<BOM Structure>
2
13
Q63
AP2301GN-HF_SOT23-3
2
3 1
C1457
10U_0603_6.3V6M
VGA@
1
2
R1103 47K_0402_5%
1 2
R1114
470_0603_5%
VGA@
1 2
R1097
100K_0402_5%
1 2
R1101
470_0603_5%
1 2
G
D
S
Q61
SSM3K7002FU_SC70-3
2
13
G
D
S
Q73
SSM3K7002FU_SC70-3
VGA@
2
13
R1112 200K_0402_5%
12
C1455
1U_0402_6.3V4Z
1
2
G
D
S
Q77
SSM3K7002FU_SC70-3
2
13
U41
AO4430L_SO8
VGA@
6
2
4
1
3
5
7
8
C1443
10U_0805_10V4Z
1
2
C1450
0.1U_0603_25V7K
1
2
R1100
1K_0402_5%
12
U39
AO4430L_SO8
6
2
4
1
3
5
7
8
C1460
10U_0603_6.3V6M
VGA@
1
2
C1461
10U_0603_6.3V6M
1
2
PJ14
JUMP_43X118
VGA@
1
122
G
D
S
Q67
SSM3K7002FU_SC70-3
VGA@
2
13
R1119
100K_0402_5%
1 2
R1098
100K_0402_5%
1 2
U38
SI4800BDY-T1-GE3_SO8
36
5
7
8
2
4
1
R1123
100K_0402_5%
12
U40
SI4800BDY-T1-GE3_SO8
36
5
7
8
2
4
1
G
D
S
Q53
SSM3K7002FU_SC70-3
2
13
C1454
10U_0603_6.3V6M
1
2
R1120 47K_0402_5%VGA@
12
R1108
100K_0402_5%
1 2
G
D
S
Q60
SSM3K7002FU_SC70-3
2
13
R1127
33_0603_5%
VGA@
1 2
R1104
100K_0402_5%
12
R1122
47K_0402_5%
12
C1444
1U_0603_10V6K
12
R1102
10K_0402_5%
12
G
D
S
Q55
SSM3K7002FU_SC70-3
2
13
R1110
470_0603_5%
1 2
C1464
0.1U_0402_16V7K
VGA@ 1
2
C1456
0.1U_0603_25V7K
1
2
R1099
470_0603_5%
1 2
G
D
S
Q58
SSM3K7002FU_SC70-3
2
13
G
D
S
Q70
SSM3K7002FU_SC70-3
<BOM Structure>
2
13
C1458
1U_0402_6.3V4Z
VGA@
1
2
C1459
10U_0603_6.3V6M
VGA@
1
2
G
D
S
Q57
SSM3K7002FU_SC70-3
<BOM Structure>
2
13
G
D
S
Q64
SSM3K7002FU_SC70-3
2
13
G
D
S
Q66
SSM3K7002FU_SC70-3
VGA@
2
13
![](asset-27.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
ACOFF
CHG_VCOMP
CHG_ICOMP
6251_EN CSON
6251VDD
CHG_ICM
6251VDD
CHG_N_008
6251VREF
CHG_CSIN
6251VREF
PACIN
BST_CHG
ACPRN
6251aclim
DH_CHG
CSIP
DL_CHG
CSIN
CHG_CHLIM
LX_CHG
6251VDDP
BST_CHGA
CHG_N_003
CHG_N_010
CHG_N_009
CHG
CHG_VADJ
CHG_SNUB
CHG_CSIP
CSOPCHG_CSOP
CHG_CSON
CHG_N_005
PACIN
ACPRN
ACSETIN
ACPRN
CHG_VIN
DCIN
ACSETIN
CHG_N_001
CHG_N_002
CHG_N_006
CHG_N_001
IREF36
FSTCHG36
ACOFF36
CHGVADJ36
ADP_I36
ACIN 36
VIN
VIN
BATT+
P2 P3
B+
CHG_B+
B+
6251VDD
VIN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
CHARGER
39 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
NCL61 LA-6321P M/B
Vcell
CHGVADJ=(Vcell-4)/0.10627
CHGVADJ
4V
4.2V
0V
1.882V
CC=0.25A~3A
IREF=0.254V~3.048V
IREF=1.016*Icharge
VCHLIM need over 95mV
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K
90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N
CP= 85%*Iada;
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A
CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Rtop
PC120 must close EC pin.
2S: Float
3S: GND
(B+ 6A,240mils ,Via NO.= 12)
PR105
10K_0402_1%
1 2
PC110
1000P_0402_50V7K
12
PC119
@10U_0805_25V6K
12
PQ101
AO4435L_SO8
36
5
7
8
2
4
1
PR119
20_0603_5%
1 2
PR127
12.4K_0402_1%
1 2
PQ110
AO4468L_SO8
4
7
8
6
5
1
2
3
PR103
150K_0402_1%
12
PR128
20K_0402_1%
12
PC105
0.1U_0402_25V6
12
PR106
22K_0402_1%
1 2
PR110
200K_0402_1%
1 2
PQ111
LTC015EUBFS8TL NPN UMT3F
2
13
PD106
RB751V-40TE17_SOD323-2
12
PU101
ISL6251AHAZ-T QSOP 24P
EN
3
CELLS
4
VDD
1
ACSET
2
ICOMP
5
VCOMP
6
CHLIM
9
ACPRN 23
CSIP 19
UGATE 17
PHASE 18
BOOT 16
PGND 13
GND
12
ICM
7
VREF
8
VADJ
11
DCIN 24
CSIN 20
ACLIM
10
LGATE 14
VDDP 15
CSOP 21
CSON 22
PQ107A
SSM6N7002FU_US6
61
2
PC116 6800P_0402_25V7K
1 2
PC108
0.1U_0603_25V7K
12
PR109
47K_0402_1%
12
PC102
10U_0805_25V6K
12
PC113
0.047U_0603_16V7K
1 2
PQ104
LTA044EUBFS8TL PNP UMT3F
2
1 3
PC107
@5600P_0402_25V7K
1 2
PR107
200K_0402_1%
12
PL102
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
12
PR132
10K_0402_1%
12
PR121 10K_0402_1%
1 2
PQ108
AON7408L_DFN8-5
3 5
2
4
1
PC106
2200P_0402_25V7K
12
PC121
0.1U_0603_25V7K
12
PC103
4.7U_0805_25V6-K
12
PR124
22K_0402_5%
1 2
PR133
10K_0402_1%
1 2
PQ102
AO4409L_SO8
3 6
5
7
8
2
4
1
PR118
20_0603_5%
1 2
PR101
0.02_1206_1%
1
3
4
2
PC101
10U_0805_25V6K
12
PC114
@2200P_0402_25V7K
12
PR126
0_0603_5%
1 2
PQ106
LTC015EUBFS8TL NPN UMT3F
2
13
G
D
S
PQ109
@SSM3K7002FU_SC70-3
2
13
PC115
@10U_0805_25V6K
12
PL101
10UH +-20% MSCDRI-104A-100M-E
1 2
PR112
47K_0402_1%
1 2
PC117
0.01U_0402_25V7K
1 2
PC112
1U_0603_25V6K
1 2
E
B
C
PQ112
MMBT3904WH NPN SOT323-3
2
3 1
PC123
4.7U_0805_6.3V6K
1 2
PR104
140K_0402_1%
12
PR113
10_1206_5%
1 2
PR102
0.02_1206_1%
1
3
4
2
PR120
20_0603_5%
12
PR108
191K_0402_1%
1 2
PR114
10K_0402_1%
12
PC125
10U_0805_25V6K
12
PR122
2.2_0603_1%
1 2
PC118
0.1U_0603_25V7K
1 2
PQ105
LTC015EUBFS8TL NPN UMT3F
2
13
PR134
0_0402_5%
1 2
PR123 100_0402_1%
1 2
PR136
20K_0402_1%
12
PC109
2.2U_0603_6.3V6K
12
PC104
10U_0805_25V6K
12
PR125
@4.7_1206_5%
12
PR131
47K_0402_1%
12
PC120
0.1U_0402_16V7K
1 2
PR111
14.3K_0402_1%
12
PR116
150K_0402_1%
12
PC124
@680P_0402_50V7K
12
PC111
@10U_0805_25V6K
12
PR117
100K_0402_1%
12
PQ103
AO4407AL 1P SO8
3 6
5
7
8
2
4
1
PD101
RB751V-40TE17_SOD323-2
1 2
PR115
100K_0402_1%
1 2
PQ107B
SSM6N7002FU_US6
34
5
PR129
4.7_0603_5%
1 2
PC122
0.01U_0402_25V7K
12
PR130
0_0402_5%
1 2
![](asset-28.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
VS_N_001
VS_N_002
N1
ADPIN
OTP_N_002
OTP_N_001
VSB_N_002
VSB_N_003
VSB_N_001
OTP_N_003
EC_SMCA
EC_SMDA
TS_A
51_ON#35
SPOK41,44
VS_ON 41
BATT_TEMP 36
EC_SMB_DA1 36
EC_SMB_CK1 36
VIN
VIN
VS
BATT+
VL
B+
VL
+VSBP
+VSBP +VSB
BATT+
VMB
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DCIN / BATT CONN / OTP
40 53Monday, April 25, 2011
Compal Electronics, Inc.
2012/04/252011/04/25
NCL61 LA-6321P M/B
CPU thermal protection at 92 +-3 degree C
Recovery at 80 +-3 degree C
PH1 under CPU botten side :
X7R type
(120mA,40mils ,Via NO.= 1)
PR10
100K_0402_1%
12
PC13
@10U_0805_25V6K
12
PR12
22K_0402_1%
1 2
PC9
0.1U_0603_25V7K
12
PC10
0.1U_0402_16V7K
12
PR16
0_0402_5%
1 2
PC6
1000P_0402_50V7K
12
PC1
1000P_0402_50V7K
12
PC4
100P_0402_50V8J
12
PR29
100K_0402_5%
1 2
PC11
0.22U_0603_25V7K
12
PL1
HCB2012KF-121T50_0805
1 2
PC5
0.1U_0603_16V7K
12
PC3
1000P_0402_50V7K
12
PR18
68_1206_5%
12
PR1
22K_0402_1%
1 2
PC12
0.1U_0603_25V7K
12
PQ1
TP0610K-T1-GE3_SOT23-3
2
13
PL3
HCB2012KF-121T50_0805
1 2
PL4
HCB2012KF-121T50_0805
1 2
PD1
@PJSOT24CW_SOT323-3
2
3
1
PR21
100K_0402_1%
12
PR28
100_0402_1%
1 2
PD4
RLS4148_LL34-2
12
PH1
100K_0402_1%_NCP15W F104F03RC
12
PD2
@PJSOT24CW_SOT323-3
2
3
1
PR17
68_1206_5%
12
PR31
100_0402_1%
1 2
PJP2
@SUYIN_200275MR009G186ZL
11
33
44
55
66
88
99
22
77
GND
11 GND
10
PC7
0.01U_0402_25V7K
12
PR27
1K_0402_1%
1 2
PL2
HCB2012KF-121T50_0805
1 2
PR2 22.1K_0402_1%
12
PR13
100K_0402_1%
1 2
PQ3
TP0610K-T1-GE3_SOT23-3
2
13
PD3
RLS4148_LL34-2
1 2
PU1
G718TM1U_SOT23-8
RHYST2 5
OT1
3
OT2
4
GND
2
VCC
1
TMSNS2 6
RHYST1 7
TMSNS1 8
G
D
S
PQ2
SSM3K7002FU_SC70-3
2
13
PC8
0.22U_0603_25V7K
12
PR30
1K_0402_1%
1 2
PC2
100P_0402_50V8J
12
PJPDC1
@CVILU_CI0104P1VRB-NH_4P-T
11
22
33
44
PJ2
@JUMP_43X39
11
2
2
PR4
0_0402_5%
12
PC14
@10U_0805_25V6K
12
PC15
10U_0805_25V6K
12
PR22
22K_0402_1%
1 2
![](asset-29.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BST_5V
LX_5V
BST1_5VBST1_3V BST_3V
ENTRIP2
ENTRIP1
FB_3V
LG_5V
EN0
SNUB_3V
SNUB_5V
LG_3V
LX_3V
FB_5V
N_3_5V_001
ENTRIP1
ENTRIP2
UG_5VUG_3V
SPOK 40,44
VS_ON40
B++
+5VALWP
VL
+3VALWP
B++
B++
2VREF_6182
B+
+3VLP
+3VLP
2VREF_6182
+5VALWP
+3VALW
+5VALW
+3VALWP
VL
B++
VL
VS
+CHGRTC
+5VALWP +5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
3.3VALWP/5VALWP
Custom
41 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
(5A,200mils ,Via NO.= 10)
(4A,120mils ,Via NO.= 8)
EC:+3VL, reserve PR319, install PR318, PR320 100K
EC:+3VALW, reserve PR318, install PR319, PR320 42.2K
(5A,200mils ,Via NO.= 10)
PQ305
AON7408L_DFN8-5
3 5
2
4
1
PQ304
AO4468L_SO8
4
7
8
6
5
1
2
3
PC315
0.1U_0402_10V7K
1 2
PU301
RT8205LZQW(2) WQFN 24P PWM
FB1 2
REF 3
VO1 24
ENTRIP1 1
TONSEL 4
FB2 5
SKIPSEL
14
NC
18
VREG5
17
VO2
7
VREG3
8
VIN
16
GND
15
UGATE1 21
BOOT1 22
ENTRIP2 6
PGOOD 23
PHASE1 20
LGATE1 19
EN
13
BOOT2
9
UGATE2
10
PHASE2
11
LGATE2
12
P PAD
25
PR309
2.2_0402_5%
1 2
PC314
0.1U_0402_10V7K
1 2
PJP306
PAD-OPEN 4x4m
1 2
PR320
42.2K_0402_1%
12
PR305
30.9K_0402_1%
1 2
PC316
@680P_0402_50V7K
12
PC320
1U_0603_10V6K
12
PC318
4.7U_0805_10V6K
12
PJP301
PAD-OPEN 2x2m
2 1
PR311
0_0402_5%
1 2
PQ306
AO4406AL 1N SO8
4
7
8
6
5
1
2
3
PR317
100K_0402_5%
1 2
PJP302
PAD-OPEN 2x2m
2 1
PR310
0_0402_5%
1 2
PC313
10U_0805_6.3V6M
12
PJP303
PAD-OPEN 4x4m
1 2
G
D
S
PQ307B
SSM6N7002FU_US6
5
34
+
PC305
220U_6.3VM_R15
1
2
PC322
@4.7U_0805_25V6-K
12
PC309
0.1U_0402_25V6
12
PR302
20K_0402_1%
1 2
PR307
165K_0402_1%
1 2
PR315
95.3K_0402_1%
12
PR313
@4.7_1206_5%
12
PL303
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
12
PC310
2200P_0402_50V7K
12
+
PC303
220U_6.3VM_R15
1
2
PR319
100K_0402_1%
1 2
PR308
2.2_0402_5%
1 2
PR301
13.7K_0402_1%
1 2
PC304
4.7U_0805_25V6-K
12
PR303
133K_0402_1%
1 2
PQ308
LTC015EUBFS8TL NPN UMT3F
2
13
PJP305
PAD-OPEN 4x4m
1 2
PC317
@680P_0402_50V7K
12
G
D
S
PQ307A
SSM6N7002FU_US6
2
61
PR312
@4.7_1206_5%
12
PR306
20K_0402_1%
1 2
PL305
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1 2
PC306
10U_0805_25V6K
12
PC319
0.1U_0603_25V7K
12
PC311
0.1U_0402_25V6
12
PR314
499K_0402_1%
1 2
PC312
2200P_0402_50V7K
12
PC308
1U_0603_16V6K
12
PC321
2.2U_0603_10V6K
12
PL301
HCB2012KF-121T50_0805
1 2
PQ303
AON7408L_DFN8-5
3 5
2
4
1
![](asset-2a.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
1.8VSP_FB
1.8VSP_VIN
1.8VSP_LX
SNUB_1.8VSP
EN_1.8VSP
VGA_PWR_ON25,38,45
+1.8VSGP
+1.8VSGP +1.8VSG
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
+1.8VSGP
42 53Monday, April 25, 2011
Compal Electronics, Inc.
2012/04/252011/04/25
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
NCL61 LA-6321P M/B
(4A, 160mils, Via NO.= 8)
PJP401
PAD-OPEN 3x3m
1 2
PU401
RT8061AZQW WDFN 10P
EN
5
PG 4
LX 3
FB 6
SVIN
8
TP
11
LX 2
PVIN
10
NC
7
PVIN
9
NC
1
PR402
10K_0402_1%
12
PC404
68P_0402_50V8J
12
PR401
20K_0402_1%
12
PC401
22U_0805_6.3VAM
12
PL402
HCB1608KF-121T30_0603
1 2
PC403
22U_0805_6.3VAM
12
PD401
ISS355_SOD323-2
1 2
PC405
0.1U_0402_10V7K
12
PR404 200K_0402_5%
1 2
PC406
680P_0402_50V7K
12
PR405
@47K_0402_5%
12
PL401
1UH_VLS252012T-1R0N1R7_2.4A_30%
1 2
PR403
4.7_1206_5%
12
PC402
22U_0805_6.3VAM
12
![](asset-2b.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TRIP_1.5V
LG_1.5V
BST1_1.5VBST_1.5V
TON_1.5V
FB_1.5V
EN_1.5V
V5FILT_1.5V+5VALW
LX_1.5V
SNUB_1.5V
+5VALW
UG_1.5V
SYSON36,38
+1.5V
1.5V_B+
B+
+1.5V
+1.5V
+5VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
+1.5VP
43 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
(8A,320mils ,Via NO.= 16)
PR507
100_0402_1%
1 2
PC509
4.7U_0603_10V6K
12
PR506
255K_0402_1%
1 2
PC505
@0.1U_0402_10V7K
12
PU501
RT8209MGQW_WQFN14_3P5X3P5
VOUT
3
VDD
4
EN/DEM 1
TON
2
FB
5
PGOOD
6LGATE 9
UGATE 13
PHASE 12
GND
7
PGND
8
CS 11
VDDP 10
BOOT 14
NC 15
PC507
0.1U_0402_25V6
12
PC503
10U_0805_25V6K
12
PR501
2.21K_0402_1%
1 2
PC506
2200P_0402_50V7K
12
PC511
@680P_0402_50V7K
12
PL502
HCB1608KF-121T30_0603
12
PQ501
AON7408L_DFN8-5
3 5
2
4
1
PL501
1UH +-20% VMPI0703AR-1R0M-Z01 11A
1 2
PQ502
FDS6690AS-G_SO8
3 6
5
7
8
2
4
1
PR509
@4.7_1206_5%
12
PR502
2.15K_0402_1%
12
PC508
0.1U_0402_10V7K
1 2
PC504
@4.7U_0805_25V6-K
12
+
PC501
220U_B2_2.5VM_R15M
1
2
PR504
2.2_0402_5%
1 2
PR505
0_0402_5%
12
PR508 15K_0402_1%
1 2
PC510
4.7U_0805_10V6K
12
PR503
0_0402_5%
12
![](asset-2c.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TRIP_1.1V
LG_1.1V
BST1_1.1VBST_1.1V
TON_1.1V
FB_1.1V
EN_1.1V
V5FILT_1.1V+5VALW
LX_1.1V
SNUB_1.1V
+5VALW
UG_1.1V
SPOK40,41
+1.1VALW
+1.1VALWP
+1.1VALWP
1.1V_B+
B+
+1.1VALWP
+1.1VALWP
+5VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
PWR+1.1VALWP
Custom
44 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
(5A,200mils ,Via NO.=20)
PR709
@4.7_1206_5%
12
PR708 14K_0402_1%
1 2
PQ701
AON7408L_DFN8-5
3 5
2
4
1
PC708
4.7U_0603_6.3V6M
12
PR705
255K_0402_1%
1 2
+
PC701
220U_6.3VM_R15
1
2
PC707
0.1U_0402_10V7K
1 2
PC711
@10U_0805_25V6K
1
2
PC706
0.1U_0402_25V6
12
PR706
@100K_0402_5%
1 2
PR710
0_0402_5%
12
PR702
10K_0402_1%
12
PC702
10U_0805_25V6K
1
2
PJP701
PAD-OPEN 4x4m
1 2
PR707
100_0402_1%
1 2
PC710
@680P_0402_50V7K
12
PC703
@10U_0805_25V6K
1
2
PR704
2.2_0402_5%
1 2
PC705
2200P_0402_50V7K
12
PC709
4.7U_0805_10V6K
12
PL701
2.2UH_PCMC063T-2R2MN_8A_20%
1 2
PQ702
AO4468L_SO8
4
7
8
6
5
1
2
3
PR701
4.64K_0402_1%
1 2
PC704
@0.1U_0402_10V7K
12
PL702
HCB1608KF-121T30_0603
12
PU701
RT8209MGQW_WQFN14_3P5X3P5
VOUT
3
VDD
4
EN/DEM 1
TON
2
FB
5
PGOOD
6LGATE 9
UGATE 13
PHASE 12
GND
7
PGND
8
CS 11
VDDP 10
BOOT 14
NC 15
PR703
0_0402_5%
12
![](asset-2d.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0.75VS_N_002
VREF_G2992
SUSP28,38
VGA_PWR_ON25,38,42
+0.75VS
+0.75VSP
+3VALW
+0.75VSP
+1.5V
+1.5V
+5VALW
+1.0VSP
+1.0VSG
+1.0VSP
+3VS
+2.5VSP
+2.5VS
+2.5VSP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QBL60 LA-7552P
1.0
PWR 0.75VSP/1.0VSP/2.5VSP
45 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
(2A,80mils ,Via NO.= 4)
(2.5A,100mils ,Via NO.= 5)
PU602 APL5930KAI-TRG_SO8
VIN
9
EN
8
VCNTL
6
VIN
5
POK
7
GND
1
FB 2
VOUT 4
VOUT 3
PU601
APL5336KAI-TRL_SOP8P8
NC 5
VREF
3
VOUT
4
GND
2
VIN
1
VCNTL 6
NC 7
NC 8
TP 9
G
D
S
PQ602
SSM3K7002FU_SC70-3
2
13
PU603
APL5508-25DC-TRL_SOT89-3
IN
2
GND
1
OUT 3
PC615
22U_0805_6.3V6M
12
PR604
0_0402_5%
12
PC614
180P_0402_50V8J
12
PC605
10U_0805_6.3V6M
12
PR610
1.82K_0402_1%
12
PR605
@150_1206_5%
12
PR601
1K_0402_1%
12
PC608
4.7U_0805_6.3V6K
12
PD601
ISS355_SOD323-2
1 2
PR609
15K_0402_1%
1 2
PC603
1U_0603_10V6K
12
PC612
1U_0603_10V6K
12
PJP602
PAD-OPEN 3x3m
1 2
PC613
0.1U_0402_16V7K
12
PC607
1U_0402_6.3V6K
12
PJP601
PAD-OPEN 3x3m
1 2
PC606
@0.1U_0402_10V7K
12
PC601
4.7U_0805_6.3V6K
12
PJP603
PAD-OPEN 3x3m
1 2
PR602
1K_0402_1%
12
PR611
7.32K_0402_1%
12
PC611
4.7U_0805_6.3V6K
12
PC604
0.1U_0402_16V7K
12
![](asset-2e.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
TRIP_1.2V
LG_1.2V
BST1_1.2VBST_1.2V
TON_1.2V
FB_1.2V
EN_1.2V
V5FILT_1.2V+5VALW
LX_1.2V
SNUB_1.2V
+5VALW
VLDT_EN36,38
+1.2VS
+1.2VSP
+1.2VSP
1.2V_B+
B+
+1.2VSP
+1.2VSP
+5VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
+1.2VSP
46 53Monday, April 25, 2011
Compal Electronics, Inc.
2012/04/252011/04/25
NCL61 LA-6321P M/B
(6A,240mils ,Via NO.=12)
PL801
2.2UH_PCMC063T-2R2MN_8A_20%
1 2
PQ801
AON7408L_DFN8-5
3 5
2
4
1
PC805
2200P_0402_50V7K
12
PJP801
PAD-OPEN 4x4m
1 2
PR804
2.2_0402_5%
1 2
PC810
@680P_0402_50V7K
12
PC802
10U_0805_25V6K
12
PR807
100_0402_1%
1 2
PC811
@10U_0805_25V6K
12
PC804
@0.1U_0402_10V7K
12
PC806
0.1U_0402_25V6
12
PR805
255K_0402_1%
1 2
PQ802
AO4406AL 1N SO8
4
7
8
6
5
1
2
3
PR809
@4.7_1206_5%
12
PR802
5.36K_0402_1%
12
PC808
4.7U_0603_6.3V6M
12
PU801
RT8209MGQW _WQFN14_3P5X3P5
<BOM Structure>
VOUT
3
VDD
4
EN/DEM 1
TON
2
FB
5
PGOOD
6LGATE 9
UGATE 13
PHASE 12
GND
7
PGND
8
CS 11
VDDP 10
BOOT 14
NC 15
PC807
0.1U_0402_10V7K
1 2
PR808 15K_0402_1%
1 2
PR803
0_0402_5%
12
PR806
0_0402_5%
12
PL802
HCB1608KF-121T30_0603
12
PR801
3.24K_0402_1%
1 2
+
PC801
220U_6.3VM_R15
1
2
PC809
4.7U_0805_10V6K
12
![](asset-2f.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NTC_NB_1
SNUB_CPU2
ALERT#
SCLK
SDA
PROG2
NTC_NB
SNUB_CPU1
VSUMG-_1
VSUMG+_1
LGATE1
BOOT1_1
PHASE1
BOOT1
VSUM+_1
VSUM+
ISEN1
VSUM-_1VSUM-
BOOT2_1
PHASE2
BOOT2
VSUM+_2
VSUM+
ISEN2
VSUM-_2VSUM-
LGATE2
COMP_CPU_1
FB_CPU_1
SNUB_NB
PHASE_NB
PH201_CPU
VSUM-
VSUM+
ISEN1
ISEN2
FB_NB_1
COMP_NB_1
VW_CPU
PH202_CPU
FB_CPU
COMP_CPU
ISEN3_FB2_CPU
ISUMN_CPU
VIN_CPU
VDD_CPU
PROG1_CPU
BOOT1
PHASE1
LGATE1
LGATE2
PHASE2
UGATE2
BOOT2
UGATE1
6267_VCCP1
PWM3
NTC_CPU
VW_NB
COMP_NB
FB_NB
VSUMG+
VSUMG-
PH203_NB
ISUMN_NB
VSUMG+
VSUMG-
LGATE_NB
BOOST1_NB1
BOOT1_NB
UGATE_NB
ISEN2
ISEN1
VSUM-
UGATE2
6267_VCCP
UGATE1
APU_SVD8
APU_PW RGD_L13
APU_SVC8
VGATE36
VR_ON36
APU_VDDNB_RUN_FB_L8
APU_VDDNB_SEN8
APU_VDD_SEN8
APU_VDD_RUN_FB_L8
EC_THERM#8,13,36
+5VS
+CPU_CORE
+CPU_CORE
+CPU_CORE_NB
+5VS
CPU_B+
+CPU_CORE_NB
+5VS
CPU_B+
B+
CPU_B+
CPU_B+
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
PWR_+CPU_CORE/+CPU_CORE_NB
47 53
Monday, April 25, 2011
2011/04/25 2012/04/25
PLACE NEAR Phase1 L-MOS
PLACE NEAR Phase1 choke
If the layout of each phase to CPU
is symmetric, the two res. can be
removed.
They are used for phase current
balance adjustment.
PLACE NEAR NB choke
PLACE NEAR NB L-MOS
Compal Electronics, Inc.
Rfset(Kohm)=(Period(uS))-0.29)*2.65
Rfset(Kohm)=(Period(uS))-0.29)*2.65
PR223 0_0402_5%
12
PC224
10U_0805_25V6K
12
PR230
3.65K_0805_1%
12
PC233
0.1U_0402_10V7K
12
PR241
143K_0402_1%
12
PU201
ISL6267HRZ-T_QFN48_6X6
COMP_NB
3
VW_NB
4
FB2_NB
1
FB_NB
2
PGOOD_NB
5
SVD
6
SVC
8
VSEN
19
ISEN2
17
FB
15
ISUMP
22
ISEN3/FB2
16
COMP
14
NTC
12
PROC_HOT
11
PWROK
7
PGOOD
10
ISUMN
21
VDD
23
RTN
20
ISEN1
18
ENABLE
9
VIN
24
VW
13
PROG1 25
BOOT1 26
UG1 27
PH1 28
LG1 29
PWM3 30
VCCP 31
LG2 32
PH2 33
UG2 34
BOOT2 35
PWM2_NB 36
LG1_NB 37
PH1_NB 38
UG1_NB 39
BOOT1_NB 40
PROG2 41
NTC_NB 42
ISUMN_NB 43
ISUMP_NB 44
RTN_NB 45
VSEN_NB 46
ISEN2_NB 47
ISEN1_NB 48
TP
49
PR250
3.65K_0805_1%
12
PR219
0_0603_5%
12
PC246
680P_0402_50V7K
12
PC228
0.01U_0402_25V7K
12
PR214
1_0402_1%
12
PL203
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
3
4
2
PR232 3.83K_0402_1%
12
PR252
10_0402_5%
12
PR217
6.65K_0402_1%
1 2
PC223
10U_0805_25V6K
12
PR209
100K_0402_1%
12
PC263
@330P_0402_50V7K
12
PC254
0.01U_0402_25V7K
12
PR220
10K_0402_1%
12
+
PC227
68U_25V_M
1
2
PC250
0.22U_0603_25V7K
12
PC247
1000P_0402_50V7K
12
PC259
0.01U_0402_16V7K
12
PR248
10_0402_5%
12
PQ202
TPCA8059-H_PPAK56-8-5
<BOM Structure>
4
5
1
2
3
PR221
100K_0402_5%
12
PR215
2.2_0603_5%
12
PC262
0.1U_0603_50V7K
12
PC226
10U_0805_25V6K
12
PH203
10K_0402_5%_ERTJ0ER103J
12
PC245
1U_0603_10V6K
12
PR239
324_0402_1%
12
PC243
2200P_0402_50V7K
12
PR227 0_0402_5%
12
PR246
10K_0402_1%
1 2
PC265
680P_0402_50V7K
12
PR240
2.61K_0402_1%
12
PC236
470P_0402_50V7K
12
PC258
0.22U_0402_16V7K
12
PR216
8.06K_0402_1%
1 2
PR235
0_0603_5%
12
PH204
470K_0402_5%_TSM0B474J4702RE
1 2
PQ203
TPCA8065-H_PPAK56-8-5
4
5
1
2
3
PC256
0.22U_0402_10V6K
12
PC255
470P_0402_50V7K
12
PH201
10K_0402_5%_ERTJ0ER103J
12
PC261
@330P_0402_50V7K
12
PR229 0_0402_5%
12
PR247
2.2_0603_5%
12
PC221
10U_0805_25V6K
12
PL204
HCB2012KF-121T50_0805
1 2
PC244
0.1U_0603_50V7K
12
PC252
1000P_0402_50V7K
12
PR244
976_0402_1%
12
PC232
@330P_0402_50V7K
1 2
PC248 33P_0402_50V8J
1 2
PC257
0.22U_0402_10V6K
12
PR206
845_0402_1%
12
PR226
2.2_0603_5%
12
PC222
10U_0805_25V6K
12
PR205
4.7_1206_5%
12
PR207
143K_0402_1%
12
PR254
0_0603_5%
12
PL201
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
3
4
2
+
PC230
@68U_25V_M
1
2
PR202
10_0402_5%
12
PR213
3.65K_0805_1%
12
PC251
68P_0402_50V8J
12
PR204
10_0402_5%
12
PQ204
TPCA8059-H_PPAK56-8-5
<BOM Structure>
4
5
1
2
3
PR237
1_0603_5%
12
PR234
6.65K_0402_1%
1 2
PR212
3.83K_0402_1%
1 2
PR231
1_0402_1%
12
PR242
2.43K_0402_1%
12
PC231
0.01U_0402_16V7K
1 2
PC253
2200P_0402_50V7K
12
PR238
100K_0402_1%
12
PL202
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
3
4
2
PC249 1U_0603_10V6K
12
PQ201
TPCA8065-H_PPAK56-8-5
<BOM Structure>
4
5
1
2
3
PL205
HCB2012KF-121T50_0805
1 2
PR210
324_0402_1%
12
PR224
0_0402_5%
1 2
PC237
680P_0402_50V7K
12
PR211
27.4K_0402_1%
1 2
PR228
4.7_1206_5%
12
PC235
0.1U_0603_50V7K
12
PR218
0_0402_5%
12
PC266
@330P_0402_50V7K
12
PC241
1000P_0402_50V7K
1 2
PR249
4.7_1206_5%
12
PR222
10K_0402_1%
1 2
PC264
0.01U_0402_16V7K
1 2
PR243
11K_0402_1%
12
PC234
0.047U_0402_16V7K
12
PQ205
TPCA8065-H_PPAK56-8-5
<BOM Structure>
4
5
1
2
3
PR255
0_0603_5%
12
PC229
2200P_0402_50V7K
12
PR236
8.06K_0402_1%
12
PR225
@100K_0402_5%
12
PC225
10U_0805_25V6K
12
PR208
2.49K_0402_1%
12
PC240
0.1U_0603_50V7K
12
PH202 470K_0402_5%_TSM0B474J4702RE
12
PC239
1000P_0402_50V7K
12
PR245
10K_0402_1%
12
PC260
0.1U_0603_50V7K
12
PC238
100P_0402_50V8J
12
PR233 27.4K_0402_1%
12
PC242
0.01U_0402_25V7K
12
PR201
11K_0402_1%
12
PR251
1_0402_1%
12
PQ206
TPCA8059-H_PPAK56-8-5
<BOM Structure>
4
5
1
2
3
PR203
2.61K_0402_1%
12
![](asset-30.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
SNUB_VGA
GPU_VID0_1
GPU_VID1_1
DL_VGA
RF_VGA
LX_VGA
BST_VGA
VGA_B+
BST1_VGA
EN_VGA
FB0_VGA
FB_VGA
FB1_VGA
+VGA_CORE1
V5IN_VGA
TRIP_VGA DH_VGA
GPU_VID019
1.5_VDD_PW REN25,38
GPU_VID119
VGA_PW RGD13,25
GCORE_SEN 21
B+
+VGA_CORE
+5VALW
+3VS
+3VSG
+3VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
VGA_CORE
48 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Whistler ProGPU VID1 GPU VID0
X L
X
L
H H
H
H 0.9V
1.0V
Rrf = 470K, FSW = 290KHz
Rtrip = 73.2K, OCP = 34.42A
PC922
0.1U_0402_16V7K
12
PC911
10U_0805_25V6K
12
PC915
2200P_0402_50V7K
12
PR908
0_0402_5%
1 2
PC923
@10U_0805_25V6K
12
+
PC901
330U_D2_2V_Y
1
2
PR904
@10K_0402_1%
1 2
PQ902
TPCA8059-H_PPAK56-8-5
4
5
1
2
3
G
D
S
PQ904
@SSM3K7002FU_SC70-3
2
13
PR912
100_0402_1%
12
G
D
S
PQ905
SSM3K7002FU_SC70-3
2
13
PR914
10K_0402_1%
1 2
PL901
0.36UH_PDME104T-R36MS0R825_37A_20%
1 2
PC925
@10U_0805_25V6K
12
PC917
@0.1U_0402_16V7K
12
PR911
470K_0402_1%
1 2
PC918
0.1U_0402_10V7K
1 2
PC916
0.1U_0603_25V7K
1 2
PQ906
@TPCA8065-H_PPAK56-8-5
4
5
1
2
3
PQ903
TPCA8059-H_PPAK56-8-5
4
5
1
2
3
PC919
2.2U_0603_6.3V6K
1 2
PR903
6.19K_0402_1%
1 2
PR913
@10K_0402_1%
1 2
PQ901
TPCA8065-H_PPAK56-8-5
4
5
1
2
3
PR918
@10K_0402_5%
1 2
PR902
6.98K_0402_1%
12
PC914
0.1U_0402_25V6
12
PR907
73.2K_0603_1%
1 2
PR905
10K_0402_1%
1 2
PR901
2.94K_0402_1%
1 2
PC913
@10U_0805_25V6K
12
PC924
@10U_0805_25V6K
12
PU901
RT8237CZQW (2) WDFN
EN
3
TRIP
2
V5IN 7
DRVH 9
SW 8
DRVL 6
VBST 10
RF
5
VFB
4
PGOOD
1
TP 11
PR917
5.1K_0402_1%
1 2
PC921
@0.1U_0402_16V7K
12
PR909
0_0603_5%
1 2
PR916
@10K_0402_5%
1 2
PR910
@4.7_1206_5%
12
PR919 0_0603_5%
12
PL902
HCB2012KF-121T50_0805
1 2
PC912
10U_0805_25V6K
12
PR915
@5.1K_0402_1%
1 2
PC920
@680P_0402_50V7K
12
PR906
2.2_0603_5%
1 2
![](asset-31.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Changed-List History
49 53Monday, April 25 , 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Version change list (P.I.R. List) Power section Page 1 of 1
Item Reason for change PG# Modify List Date Phase
1
2
3
4
5
6
7
![](asset-32.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
Power Sequence
50 53
Monday, Ap ril 25, 2011
2011/04/25 2012/04/25
+5VALW
VGA_PWRGD
VR_ON
+1.5V
+VGA_CORE/+1.5VSG
+1.8VSG/+1.0VSG
ACIN/BATT-IN
+5VS
EC_RSMRST#
APU_RST#
1.5_VDDC_PWREN
SLP_S5#
SLP_S3#
PBTN_OUT#
SUSP#
+1.05VS/+0.75VS
Delay SUSP# 10ms
T<20ms
VGA_ON
VLDT_EN
FCH_PWRGD
POWER SEQUENCE
T2>10ms
SYSON
+1.1VS
+APU_CORE/+APU_CORE_NB
VGATE
VGA_ON Delay 20ms
Delay SUSP# 10ms
AND from VGA_ON & PX_EN
+3VSG to +1.0VSG power up
PLT_RST#
Delay SLP_S3#
T2A<50ms
RTC_CLK T3>16ms
T13>8ns
Delay SLP_S5#
APU_PWRGD
T7A<50ms
98ms<T7<150ms
A_RST#
T8A<100ns
101ms<T9<113ms
101ms<T9A<113ms
1ms<T8C<2.3ms
T7B<1ms
T13A>80ns
FCH_PWRGD
+3VALW
+1.1VALW
+3VS
+1.8VS
![](asset-33.png)
5
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1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
HW-PIR1
Custom
51 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Version change list (P.I.R. List) Page 1 of 3 for HW
Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
For PBL60 MEMO
Add U2 & U56For AI charge function
PG#32
PG#340.11
0.11
03/15 ERPG#260.11For AMD reuqest Translator change to ANX3110
24
25
26
27
ER
ER
03/15
03/15Change LED1 to Green color.
For switch quality of ME. Change SW5,SW6 to 100g switch for ME.0.11 PG#37 03/15 ER
For LED brightness. Change R1584 to 200 ohm.
Change R1586,R1588,R1591,R1592,R1593 to 100 ohm
0.11 PG#32 03/15 ER
For DFB. 0.12 PG#11 JDIMM1 footprint change to FOX_AS0A626-J8SG-7H_204P-T 03/17 ER
For USB3.0 & AI charge. 0.12 PG#34 USBP0 connect to JUSB1 and USBP10 connect to JUSB2. 03/17 ER
For Back light function. 0.12 PG#36 U31.15 connect to ENBKL from APU. 03/17 ER
For HDMI HPD issue. 0.12 PG#10 Q34 change to 2N7002(ESD)
Add R469 to +1.5VS.
For DP0_HPD & DP1_HPD from AMD recommend. 0.12 PG#10 Swap Q13.1 & Q13.3, R618 unmount.
Swap Q16.1 & Q16.3, R627 unmount.
03/19
03/19
ER
ER
For Travis Vendor request Del DP0_TXN0_C & DP0_TXP0_C0.12 PG#26 03/22 ER
For LED1 0.12 LED1 connect to +3VALW 03/22 ERPG#32
R1021,R1022 change to install.0.2 PG#36For EC SMBUS 03/24 ER
For Sourcer recommend
SE103225Z80 change to SE000008880
SE100105Z80 change to SE000000K80 03/24 ER0.2
0.2For Sourcer recommend
For Sourcer recommend SB000006A00 change to SB000006A100.2
03/24 ER
03/24 ER
For Thermal 0.2 Del H4 03/24 ERPG#37
For +5VS rising time 0.2 PG#38 R1103 change to 47K 03/24 ER
For Crystal EA 0.2 C1634 change to 12P & C1633 change to 15P 03/24 ER
C1200 & C1201 change to 12P
C353 change to 15P & C354 change to 12P
03/24 ER
03/24 ER
0.2
0.2
For Crystal EA
For Crystal EA
PG#13
PG#19
PG#29
For EMI request 0.2 PG#36 R1033 change to SM01000DI00
R1055 change to 33 ohm
03/24 ER
For EMI request 0.2 PG#28 L38,L39,L40,L41 change to SM070001S00 03/24 ER
For EMI request 03/24D1,D2,D3,D6 change to installPG#270.2 ER
For Crystal EA 0.2 PG#13 C1205,C1206 change to 10P 03/24 ER
For AI charge 0.2 PG#36
PG#34
U2 reserve CEN# to EC 03/25 ER
For AMD spec 0.2 PG#27 R1642 & R1646 change to 4.6K ohm 03/29 ER
![](asset-34.png)
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2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
HW-PIR2
Custom
52 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Version change list (P.I.R. List) Page 2 of 3 for HW
Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
03/29 ERPG#300.2For EMI reuqest R1555,R1556,R1557,R1558 change to 0.1uf
24
25
26
27
For share ROM reuqest 0.2 PG#15
PG#16
U28,R626,R934,R935,R35 change to Un-install
R921 change un-install & U910 change to install
03/29 ER
For EMI reuqest 0.2 PG#34 D5 change to SC300001Y00 03/29 ER
For +3VS leakage from CRT 0.21 PG#27 Add Q101,R1644,R1645
Del R4,R31
03/31 ER
For Crystal EA 0.21 PG#13 Y4 change to SJ100007N00 (32.768KHZ 7PF) 03/31 ER
For HDMI EA 0.21 PG#34 D32.5 change to connect +5VALW from +5VS 03/31 ER
For EMC team requirement (ISN). 0.22 PG#29 Change C1636 from 1000pF to 120pF. 04/19 PR
For Thermal team recommend. 0.22 PG#19 Add R78, R79 and reserve R80, R82. 04/19 PR
Reserve PX_EN signal. 0.22 PG#36 Reserve PX_EN in EC pin 74. 04/19 PR
Follow ME BOM. 0.22 PG#11
PG#12
Swap the location of JDIMM1 & JDIMM2. 04/19 PR
Don't use for MP. 0.22 PG#35 Unstuff SW4. 04/19 PR
Update Board ID for PR (R1.0). 0.22 PG#37 Change R1026 to 46.4K ohm. 04/19 PR
DFM team requirement. 0.22 PG#35 Delete SW3. 04/19 PR
DMC team requirement. 0.23 PG#29 Reserve D7 between GND_LAN and GND. 04/21 PR
0.23 PG#29 Unstuff C1193.Don't use for MP. 04/21 PR
0.23Key Part list is updated from the customer. PG#4 Update U25 (M3-FCH) P/N to SA000043ID0
(S IC 218-0755042 A13 02G050005815 T88!) 04/21 PR
04/21 PRKey Part list is updated from the customer. 0.23 PG#13 Update U25 (M2-FCH) P/N to SA000042C80
(S IC 218-0755046 A13 02G050005814 T88!)
Update TS1 as ER build Memo. 0.23 PG#29 Change TS1 from SP050005L00 to SP050006F00. 04/21 PR
(S X'FORM_ IH-160 LAN)
For VGA Sequence. 0.23 PG#38 Change R1127 from 470 ohm to 33 ohm. 04/21 PR
DFB team requirement. 0.23 PG#34 Del R664~R667 and R672~R675. 04/21 PR
Add R1644, R1645, Q101 and Del R4, R31.0.23 PG#27Prevent the leakage from CRT monitor. 04/21 PR
ESD team requirement. 0.23 PG#34 Change D5 from SC300001D00 (YSCLAMP0524P SLP2510P8) 04/21 PR
to SC300001Y00 (AZ1045-04F DFN2510P10E ESD).
DMC team requirement. 0.23
DMC team requirement. 0.23 PG#29 Change the ground of D21, D22, D31, D34 and H8. 04/22 PR
from GND_LAN to LAN.
PG#19 Add R83, R84. 04/22 PR
DMC team requirement. 1.0 PG#13 Change R657 from 22 ohm to 33 ohm. 04/25 PR
04/25 PRPG#13 Stuff R1561 to 33 ohm and C1509 to 22pF.DMC team requirement. 1.0
![](asset-35.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL60 LA-7552P
1.0
HW-PIR3
Custom
53 53Monday, April 25, 2011
2011/04/25 2012/04/25
Compal Electronics, Inc.
Version change list (P.I.R. List) Page 3 of 3 for HW
Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
04/25 PR1.0Reduce the component count for MP. Change below the footprints from 0 ohm to R short.
24
25
26
27